[picodrive.git] / Pico / PicoInt.h

// Pico Library - Internal Header File\r
\r
// (c) Copyright 2004 Dave, All rights reserved.\r
// (c) Copyright 2006,2007 Grazvydas "notaz" Ignotas, all rights reserved.\r
// Free for non-commercial use.\r
\r
// For commercial use, separate licencing terms must be obtained.\r
\r
#ifndef PICO_INTERNAL_INCLUDED\r
#define PICO_INTERNAL_INCLUDED\r
\r
#include <stdio.h>\r
#include <stdlib.h>\r
#include <string.h>\r
#include "Pico.h"\r
\r
//\r
#define USE_POLL_DETECT\r
\r
#ifndef PICO_INTERNAL\r
#define PICO_INTERNAL\r
#endif\r
#ifndef PICO_INTERNAL_ASM\r
#define PICO_INTERNAL_ASM\r
#endif\r
\r
// to select core, define EMU_C68K, EMU_M68K or EMU_F68K in your makefile or project\r
\r
#ifdef __cplusplus\r
extern "C" {\r
#endif\r
\r
\r
// ----------------------- 68000 CPU -----------------------\r
#ifdef EMU_C68K\r
#include "../cpu/Cyclone/Cyclone.h"\r
extern struct Cyclone PicoCpuCM68k, PicoCpuCS68k;\r
#define SekCyclesLeftNoMCD PicoCpuCM68k.cycles // cycles left for this run\r
#define SekCyclesLeft \\r
	(((PicoMCD&1) && (PicoOpt & 0x2000)) ? (SekCycleAim-SekCycleCnt) : SekCyclesLeftNoMCD)\r
#define SekCyclesLeftS68k \\r
	((PicoOpt & 0x2000) ? (SekCycleAimS68k-SekCycleCntS68k) : PicoCpuCS68k.cycles)\r
#define SekSetCyclesLeftNoMCD(c) PicoCpuCM68k.cycles=c\r
#define SekSetCyclesLeft(c) { \\r
	if ((PicoMCD&1) && (PicoOpt & 0x2000)) SekCycleCnt=SekCycleAim-(c); else SekSetCyclesLeftNoMCD(c); \\r
}\r
#define SekPc (PicoCpuCM68k.pc-PicoCpuCM68k.membase)\r
#define SekPcS68k (PicoCpuCS68k.pc-PicoCpuCS68k.membase)\r
#define SekSetStop(x) { PicoCpuCM68k.state_flags&=~1; if (x) { PicoCpuCM68k.state_flags|=1; PicoCpuCM68k.cycles=0; } }\r
#define SekSetStopS68k(x) { PicoCpuCS68k.state_flags&=~1; if (x) { PicoCpuCS68k.state_flags|=1; PicoCpuCS68k.cycles=0; } }\r
#define SekShouldInterrupt (PicoCpuCM68k.irq > (PicoCpuCM68k.srh&7))\r
#ifdef EMU_M68K\r
#define EMU_CORE_DEBUG\r
#endif\r
#endif\r
\r
#ifdef EMU_F68K\r
#include "../cpu/fame/fame.h"\r
M68K_CONTEXT PicoCpuFM68k, PicoCpuFS68k;\r
#define SekCyclesLeftNoMCD PicoCpuFM68k.io_cycle_counter\r
#define SekCyclesLeft \\r
	(((PicoMCD&1) && (PicoOpt & 0x2000)) ? (SekCycleAim-SekCycleCnt) : SekCyclesLeftNoMCD)\r
#define SekCyclesLeftS68k \\r
	((PicoOpt & 0x2000) ? (SekCycleAimS68k-SekCycleCntS68k) : PicoCpuFS68k.io_cycle_counter)\r
#define SekSetCyclesLeftNoMCD(c) PicoCpuFM68k.io_cycle_counter=c\r
#define SekSetCyclesLeft(c) { \\r
	if ((PicoMCD&1) && (PicoOpt & 0x2000)) SekCycleCnt=SekCycleAim-(c); else SekSetCyclesLeftNoMCD(c); \\r
}\r
#define SekPc     fm68k_get_pc(&PicoCpuFM68k)\r
#define SekPcS68k fm68k_get_pc(&PicoCpuFS68k)\r
#define SekSetStop(x) { \\r
	PicoCpuFM68k.execinfo &= ~FM68K_HALTED; \\r
	if (x) { PicoCpuFM68k.execinfo |= FM68K_HALTED; PicoCpuFM68k.io_cycle_counter = 0; } \\r
}\r
#define SekSetStopS68k(x) { \\r
	PicoCpuFS68k.execinfo &= ~FM68K_HALTED; \\r
	if (x) { PicoCpuFS68k.execinfo |= FM68K_HALTED; PicoCpuFS68k.io_cycle_counter = 0; } \\r
}\r
#define SekShouldInterrupt fm68k_would_interrupt()\r
#ifdef EMU_M68K\r
#define EMU_CORE_DEBUG\r
#endif\r
#endif\r
\r
#ifdef EMU_M68K\r
#include "../cpu/musashi/m68kcpu.h"\r
extern m68ki_cpu_core PicoCpuMM68k, PicoCpuMS68k;\r
#ifndef SekCyclesLeft\r
#define SekCyclesLeftNoMCD PicoCpuMM68k.cyc_remaining_cycles\r
#define SekCyclesLeft \\r
	(((PicoMCD&1) && (PicoOpt & 0x2000)) ? (SekCycleAim-SekCycleCnt) : SekCyclesLeftNoMCD)\r
#define SekCyclesLeftS68k \\r
	((PicoOpt & 0x2000) ? (SekCycleAimS68k-SekCycleCntS68k) : PicoCpuMS68k.cyc_remaining_cycles)\r
#define SekSetCyclesLeftNoMCD(c) SET_CYCLES(c)\r
#define SekSetCyclesLeft(c) { \\r
	if ((PicoMCD&1) && (PicoOpt & 0x2000)) SekCycleCnt=SekCycleAim-(c); else SET_CYCLES(c); \\r
}\r
#define SekPc m68k_get_reg(&PicoCpuMM68k, M68K_REG_PC)\r
#define SekPcS68k m68k_get_reg(&PicoCpuMS68k, M68K_REG_PC)\r
#define SekSetStop(x) { \\r
	if(x) { SET_CYCLES(0); PicoCpuMM68k.stopped=STOP_LEVEL_STOP; } \\r
	else PicoCpuMM68k.stopped=0; \\r
}\r
#define SekSetStopS68k(x) { \\r
	if(x) { SET_CYCLES(0); PicoCpuMS68k.stopped=STOP_LEVEL_STOP; } \\r
	else PicoCpuMS68k.stopped=0; \\r
}\r
#define SekShouldInterrupt (CPU_INT_LEVEL > FLAG_INT_MASK)\r
#endif\r
#endif\r
\r
extern int SekCycleCnt; // cycles done in this frame\r
extern int SekCycleAim; // cycle aim\r
extern unsigned int SekCycleCntT; // total cycle counter, updated once per frame\r
\r
#define SekCyclesReset() { \\r
	SekCycleCntT+=SekCycleAim; \\r
	SekCycleCnt-=SekCycleAim; \\r
	SekCycleAim=0; \\r
}\r
#define SekCyclesBurn(c)  SekCycleCnt+=c\r
#define SekCyclesDone()  (SekCycleAim-SekCyclesLeft)    // nuber of cycles done in this frame (can be checked anywhere)\r
#define SekCyclesDoneT() (SekCycleCntT+SekCyclesDone()) // total nuber of cycles done for this rom\r
\r
#define SekEndRun(after) { \\r
	SekCycleCnt -= SekCyclesLeft - after; \\r
	if(SekCycleCnt < 0) SekCycleCnt = 0; \\r
	SekSetCyclesLeft(after); \\r
}\r
\r
extern int SekCycleCntS68k;\r
extern int SekCycleAimS68k;\r
\r
#define SekCyclesResetS68k() { \\r
	SekCycleCntS68k-=SekCycleAimS68k; \\r
	SekCycleAimS68k=0; \\r
}\r
#define SekCyclesDoneS68k()  (SekCycleAimS68k-SekCyclesLeftS68k)\r
\r
#ifdef EMU_CORE_DEBUG\r
#undef SekSetCyclesLeftNoMCD\r
#undef SekSetCyclesLeft\r
#undef SekCyclesBurn\r
#undef SekEndRun\r
#define SekSetCyclesLeftNoMCD(c)\r
#define SekSetCyclesLeft(c)\r
#define SekCyclesBurn(c) c\r
#define SekEndRun(c)\r
#endif\r
\r
// ---------------------------------------------------------\r
\r
extern int PicoMCD;\r
\r
// main oscillator clock which controls timing\r
#define OSC_NTSC 53693100\r
// seems to be accurate, see scans from http://www.hot.ee/tmeeco/\r
#define OSC_PAL  53203424\r
\r
struct PicoVideo\r
{\r
  unsigned char reg[0x20];\r
  unsigned int command;       // 32-bit Command\r
  unsigned char pending;      // 1 if waiting for second half of 32-bit command\r
  unsigned char type;         // Command type (v/c/vsram read/write)\r
  unsigned short addr;        // Read/Write address\r
  int status;                 // Status bits\r
  unsigned char pending_ints; // pending interrupts: ??VH????\r
  signed char lwrite_cnt;     // VDP write count during active display line\r
  unsigned char pad[0x12];\r
};\r
\r
struct PicoMisc\r
{\r
  unsigned char rotate;\r
  unsigned char z80Run;\r
  unsigned char padTHPhase[2]; // 02 phase of gamepad TH switches\r
  short scanline;              // 04 0 to 261||311; -1 in fast mode\r
  char dirtyPal;               // 06 Is the palette dirty (1 - change @ this frame, 2 - some time before)\r
  unsigned char hardware;      // 07 Hardware value for country\r
  unsigned char pal;           // 08 1=PAL 0=NTSC\r
  unsigned char sram_reg;      // SRAM mode register. bit0: allow read? bit1: deny write? bit2: EEPROM? bit4: detected? (header or by access)\r
  unsigned short z80_bank68k;  // 0a\r
  unsigned short z80_lastaddr; // this is for Z80 faking\r
  unsigned char  z80_fakeval;\r
  unsigned char  pad0;\r
  unsigned char  padDelay[2];  // 10 gamepad phase time outs, so we count a delay\r
  unsigned short eeprom_addr;  // EEPROM address register\r
  unsigned char  eeprom_cycle; // EEPROM SRAM cycle number\r
  unsigned char  eeprom_slave; // EEPROM slave word for X24C02 and better SRAMs\r
  unsigned char prot_bytes[2]; // simple protection faking\r
  unsigned short dma_xfers;\r
  unsigned char pad[2];\r
  unsigned int  frame_count; // mainly for movies\r
};\r
\r
// some assembly stuff depend on these, do not touch!\r
struct Pico\r
{\r
  unsigned char ram[0x10000];  // 0x00000 scratch ram\r
  unsigned short vram[0x8000]; // 0x10000\r
  unsigned char zram[0x2000];  // 0x20000 Z80 ram\r
  unsigned char ioports[0x10];\r
  unsigned int pad[0x3c];      // unused\r
  unsigned short cram[0x40];   // 0x22100\r
  unsigned short vsram[0x40];  // 0x22180\r
\r
  unsigned char *rom;          // 0x22200\r
  unsigned int romsize;        // 0x22204\r
\r
  struct PicoMisc m;\r
  struct PicoVideo video;\r
};\r
\r
// sram\r
struct PicoSRAM\r
{\r
  unsigned char *data;		// actual data\r
  unsigned int start;		// start address in 68k address space\r
  unsigned int end;\r
  unsigned char unused1;	// 0c: unused\r
  unsigned char unused2;\r
  unsigned char changed;\r
  unsigned char eeprom_type;    // eeprom type: 0: 7bit (24C01), 2: device with 2 addr words (X24C02+), 3: dev with 3 addr words\r
  unsigned char eeprom_abits;	// eeprom access must be odd addr for: bit0 ~ cl, bit1 ~ out\r
  unsigned char eeprom_bit_cl;	// bit number for cl\r
  unsigned char eeprom_bit_in;  // bit number for in\r
  unsigned char eeprom_bit_out; // bit number for out\r
};\r
\r
// MCD\r
#include "cd/cd_sys.h"\r
#include "cd/LC89510.h"\r
#include "cd/gfx_cd.h"\r
\r
struct mcd_pcm\r
{\r
	unsigned char control; // reg7\r
	unsigned char enabled; // reg8\r
	unsigned char cur_ch;\r
	unsigned char bank;\r
	int pad1;\r
\r
	struct pcm_chan			// 08, size 0x10\r
	{\r
		unsigned char regs[8];\r
		unsigned int  addr;	// .08: played sample address\r
		int pad;\r
	} ch[8];\r
};\r
\r
struct mcd_misc\r
{\r
	unsigned short hint_vector;\r
	unsigned char  busreq;\r
	unsigned char  s68k_pend_ints;\r
	unsigned int   state_flags;	// 04: emu state: reset_pending, dmna_pending\r
	unsigned int   counter75hz;\r
	unsigned short audio_offset;	// 0c: for savestates: play pointer offset (0-1023)\r
	unsigned char  audio_track;	// playing audio track # (zero based)\r
	char           pad1;\r
	int            timer_int3;	// 10\r
	unsigned int   timer_stopwatch;\r
	unsigned char  bcram_reg;	// 18: battery-backed RAM cart register\r
	unsigned char  pad2;\r
	unsigned short pad3;\r
	int pad[9];\r
};\r
\r
typedef struct\r
{\r
	unsigned char bios[0x20000];			// 000000: 128K\r
	union {						// 020000: 512K\r
		unsigned char prg_ram[0x80000];\r
		unsigned char prg_ram_b[4][0x20000];\r
	};\r
	union {						// 0a0000: 256K\r
		struct {\r
			unsigned char word_ram2M[0x40000];\r
			unsigned char unused[0x20000];\r
		};\r
		struct {\r
			unsigned char unused[0x20000];\r
			unsigned char word_ram1M[2][0x20000];\r
		};\r
	};\r
	union {						// 100000: 64K\r
		unsigned char pcm_ram[0x10000];\r
		unsigned char pcm_ram_b[0x10][0x1000];\r
	};\r
	unsigned char s68k_regs[0x200];			// 110000: GA, not CPU regs\r
	unsigned char bram[0x2000];			// 110200: 8K\r
	struct mcd_misc m;				// 112200: misc\r
	struct mcd_pcm pcm;				// 112240:\r
	_scd_toc TOC;					// not to be saved\r
	CDD  cdd;\r
	CDC  cdc;\r
	_scd scd;\r
	Rot_Comp rot_comp;\r
} mcd_state;\r
\r
#define Pico_mcd ((mcd_state *)Pico.rom)\r
\r
// Area.c\r
PICO_INTERNAL int PicoAreaPackCpu(unsigned char *cpu, int is_sub);\r
PICO_INTERNAL int PicoAreaUnpackCpu(unsigned char *cpu, int is_sub);\r
\r
// cd/Area.c\r
PICO_INTERNAL int PicoCdSaveState(void *file);\r
PICO_INTERNAL int PicoCdLoadState(void *file);\r
\r
// Cart.c\r
PICO_INTERNAL void PicoCartDetect(void);\r
\r
// Debug.c\r
int CM_compareRun(int cyc);\r
\r
// Draw.c\r
PICO_INTERNAL int PicoLine(int scan);\r
PICO_INTERNAL void PicoFrameStart(void);\r
\r
// Draw2.c\r
PICO_INTERNAL void PicoFrameFull();\r
\r
// Memory.c\r
PICO_INTERNAL int PicoInitPc(unsigned int pc);\r
PICO_INTERNAL_ASM unsigned int PicoRead32(unsigned int a);\r
PICO_INTERNAL void PicoMemSetup(void);\r
PICO_INTERNAL_ASM void PicoMemReset(void);\r
PICO_INTERNAL int PadRead(int i);\r
PICO_INTERNAL unsigned char z80_read(unsigned short a);\r
#ifndef _USE_CZ80\r
PICO_INTERNAL_ASM void z80_write(unsigned char data, unsigned short a);\r
PICO_INTERNAL void z80_write16(unsigned short data, unsigned short a);\r
PICO_INTERNAL unsigned short z80_read16(unsigned short a);\r
#else\r
PICO_INTERNAL_ASM void z80_write(unsigned int a, unsigned char data);\r
#endif\r
\r
// cd/Memory.c\r
PICO_INTERNAL void PicoMemSetupCD(void);\r
PICO_INTERNAL_ASM void PicoMemResetCD(int r3);\r
PICO_INTERNAL_ASM void PicoMemResetCDdecode(int r3);\r
\r
// Pico.c\r
extern struct Pico Pico;\r
extern struct PicoSRAM SRam;\r
extern int emustatus;\r
extern int z80startCycle, z80stopCycle; // in 68k cycles\r
PICO_INTERNAL int CheckDMA(void);\r
\r
// cd/Pico.c\r
PICO_INTERNAL int  PicoInitMCD(void);\r
PICO_INTERNAL void PicoExitMCD(void);\r
PICO_INTERNAL int PicoResetMCD(int hard);\r
PICO_INTERNAL int PicoFrameMCD(void);\r
\r
// Sek.c\r
PICO_INTERNAL int SekInit(void);\r
PICO_INTERNAL int SekReset(void);\r
PICO_INTERNAL int SekInterrupt(int irq);\r
PICO_INTERNAL void SekState(int *data);\r
PICO_INTERNAL void SekSetRealTAS(int use_real);\r
\r
// cd/Sek.c\r
PICO_INTERNAL int SekInitS68k(void);\r
PICO_INTERNAL int SekResetS68k(void);\r
PICO_INTERNAL int SekInterruptS68k(int irq);\r
\r
// sound/sound.c\r
extern int PsndLen_exc_cnt;\r
extern int PsndLen_exc_add;\r
\r
// VideoPort.c\r
PICO_INTERNAL_ASM void PicoVideoWrite(unsigned int a,unsigned short d);\r
PICO_INTERNAL_ASM unsigned int PicoVideoRead(unsigned int a);\r
\r
// Misc.c\r
PICO_INTERNAL void SRAMWriteEEPROM(unsigned int d);\r
PICO_INTERNAL void SRAMUpdPending(unsigned int a, unsigned int d);\r
PICO_INTERNAL_ASM unsigned int SRAMReadEEPROM(void);\r
PICO_INTERNAL_ASM void memcpy16(unsigned short *dest, unsigned short *src, int count);\r
PICO_INTERNAL_ASM void memcpy16bswap(unsigned short *dest, void *src, int count);\r
PICO_INTERNAL_ASM void memcpy32(int *dest, int *src, int count); // 32bit word count\r
PICO_INTERNAL_ASM void memset32(int *dest, int c, int count);\r
\r
// cd/Misc.c\r
PICO_INTERNAL_ASM void wram_2M_to_1M(unsigned char *m);\r
PICO_INTERNAL_ASM void wram_1M_to_2M(unsigned char *m);\r
\r
// cd/buffering.c\r
PICO_INTERNAL void PicoCDBufferRead(void *dest, int lba);\r
\r
// sound/sound.c\r
PICO_INTERNAL void PsndReset(void);\r
PICO_INTERNAL void Psnd_timers_and_dac(int raster);\r
PICO_INTERNAL int  PsndRender(int offset, int length);\r
PICO_INTERNAL void PsndClear(void);\r
// z80 functionality wrappers\r
PICO_INTERNAL void z80_init(void);\r
PICO_INTERNAL void z80_resetCycles(void);\r
PICO_INTERNAL void z80_int(void);\r
PICO_INTERNAL int  z80_run(int cycles);\r
PICO_INTERNAL void z80_pack(unsigned char *data);\r
PICO_INTERNAL void z80_unpack(unsigned char *data);\r
PICO_INTERNAL void z80_reset(void);\r
PICO_INTERNAL void z80_exit(void);\r
\r
\r
#ifdef __cplusplus\r
} // End of extern "C"\r
#endif\r
\r
// emulation event logging\r
#ifndef EL_LOGMASK\r
#define EL_LOGMASK 0\r
#endif\r
\r
#define EL_HVCNT   0x0001 /* hv counter reads */\r
#define EL_SR      0x0002 /* SR reads */\r
#define EL_INTS    0x0004 /* ints and acks */\r
#define EL_YM2612R 0x0008 /* 68k ym2612 reads */\r
#define EL_INTSW   0x0010 /* log irq switching on/off */\r
#define EL_ASVDP   0x0020 /* VDP accesses during active scan */\r
#define EL_VDPDMA  0x0040 /* VDP DMA transfers and their timing */\r
#define EL_BUSREQ  0x0080 /* z80 busreq r/w or reset w */\r
#define EL_Z80BNK  0x0100 /* z80 i/o through bank area */\r
#define EL_SRAMIO  0x0200 /* sram i/o */\r
#define EL_EEPROM  0x0400 /* eeprom debug */\r
#define EL_UIO     0x0800 /* unmapped i/o */\r
#define EL_IO      0x1000 /* all i/o (TODO) */\r
\r
#define EL_STATUS  0x4000 /* status messages */\r
#define EL_ANOMALY 0x8000 /* some unexpected conditions */\r
\r
#if EL_LOGMASK\r
#define elprintf(w,f,...) \\r
{ \\r
	if ((w) & EL_LOGMASK) \\r
		printf("%05i:%03i: " f "\n",Pico.m.frame_count,Pico.m.scanline,##__VA_ARGS__); \\r
}\r
#else\r
#define elprintf(w,f,...)\r
#endif\r
\r
#endif // PICO_INTERNAL_INCLUDED\r
\r
Commit	Line	Data
eff55556	1	// Pico Library - Internal Header File\r
cc68a136	2	\r
cc68a136	3	// (c) Copyright 2004 Dave, All rights reserved.\r
6cadc2da	4	// (c) Copyright 2006,2007 Grazvydas "notaz" Ignotas, all rights reserved.\r
cc68a136	5	// Free for non-commercial use.\r
	6	\r
	7	// For commercial use, separate licencing terms must be obtained.\r
	8	\r
eff55556	9	#ifndef PICO_INTERNAL_INCLUDED\r
eff55556	10	#define PICO_INTERNAL_INCLUDED\r
cc68a136	11	\r
	12	#include <stdio.h>\r
	13	#include <stdlib.h>\r
	14	#include <string.h>\r
	15	#include "Pico.h"\r
	16	\r
89fa852d	17	//\r
	18	#define USE_POLL_DETECT\r
	19	\r
eff55556	20	#ifndef PICO_INTERNAL\r
	21	#define PICO_INTERNAL\r
	22	#endif\r
	23	#ifndef PICO_INTERNAL_ASM\r
	24	#define PICO_INTERNAL_ASM\r
	25	#endif\r
cc68a136	26	\r
70357ce5	27	// to select core, define EMU_C68K, EMU_M68K or EMU_F68K in your makefile or project\r
cc68a136	28	\r
	29	#ifdef __cplusplus\r
	30	extern "C" {\r
	31	#endif\r
	32	\r
	33	\r
	34	// ----------------------- 68000 CPU -----------------------\r
	35	#ifdef EMU_C68K\r
	36	#include "../cpu/Cyclone/Cyclone.h"\r
3aa1e148	37	extern struct Cyclone PicoCpuCM68k, PicoCpuCS68k;\r
3aa1e148	38	#define SekCyclesLeftNoMCD PicoCpuCM68k.cycles // cycles left for this run\r
7336a99a	39	#define SekCyclesLeft \\r
7336a99a	40	(((PicoMCD&1) && (PicoOpt & 0x2000)) ? (SekCycleAim-SekCycleCnt) : SekCyclesLeftNoMCD)\r
7a1f6e45	41	#define SekCyclesLeftS68k \\r
3aa1e148	42	((PicoOpt & 0x2000) ? (SekCycleAimS68k-SekCycleCntS68k) : PicoCpuCS68k.cycles)\r
3aa1e148	43	#define SekSetCyclesLeftNoMCD(c) PicoCpuCM68k.cycles=c\r
7336a99a	44	#define SekSetCyclesLeft(c) { \\r
	45	if ((PicoMCD&1) && (PicoOpt & 0x2000)) SekCycleCnt=SekCycleAim-(c); else SekSetCyclesLeftNoMCD(c); \\r
	46	}\r
3aa1e148	47	#define SekPc (PicoCpuCM68k.pc-PicoCpuCM68k.membase)\r
	48	#define SekPcS68k (PicoCpuCS68k.pc-PicoCpuCS68k.membase)\r
	49	#define SekSetStop(x) { PicoCpuCM68k.state_flags&=~1; if (x) { PicoCpuCM68k.state_flags\|=1; PicoCpuCM68k.cycles=0; } }\r
	50	#define SekSetStopS68k(x) { PicoCpuCS68k.state_flags&=~1; if (x) { PicoCpuCS68k.state_flags\|=1; PicoCpuCS68k.cycles=0; } }\r
03e4f2a3	51	#define SekShouldInterrupt (PicoCpuCM68k.irq > (PicoCpuCM68k.srh&7))\r
	52	#ifdef EMU_M68K\r
	53	#define EMU_CORE_DEBUG\r
	54	#endif\r
cc68a136	55	#endif\r
cc68a136	56	\r
70357ce5	57	#ifdef EMU_F68K\r
70357ce5	58	#include "../cpu/fame/fame.h"\r
3aa1e148	59	M68K_CONTEXT PicoCpuFM68k, PicoCpuFS68k;\r
3aa1e148	60	#define SekCyclesLeftNoMCD PicoCpuFM68k.io_cycle_counter\r
70357ce5	61	#define SekCyclesLeft \\r
	62	(((PicoMCD&1) && (PicoOpt & 0x2000)) ? (SekCycleAim-SekCycleCnt) : SekCyclesLeftNoMCD)\r
	63	#define SekCyclesLeftS68k \\r
3aa1e148	64	((PicoOpt & 0x2000) ? (SekCycleAimS68k-SekCycleCntS68k) : PicoCpuFS68k.io_cycle_counter)\r
3aa1e148	65	#define SekSetCyclesLeftNoMCD(c) PicoCpuFM68k.io_cycle_counter=c\r
70357ce5	66	#define SekSetCyclesLeft(c) { \\r
	67	if ((PicoMCD&1) && (PicoOpt & 0x2000)) SekCycleCnt=SekCycleAim-(c); else SekSetCyclesLeftNoMCD(c); \\r
	68	}\r
03e4f2a3	69	#define SekPc fm68k_get_pc(&PicoCpuFM68k)\r
03e4f2a3	70	#define SekPcS68k fm68k_get_pc(&PicoCpuFS68k)\r
70357ce5	71	#define SekSetStop(x) { \\r
03e4f2a3	72	PicoCpuFM68k.execinfo &= ~FM68K_HALTED; \\r
03e4f2a3	73	if (x) { PicoCpuFM68k.execinfo \|= FM68K_HALTED; PicoCpuFM68k.io_cycle_counter = 0; } \\r
70357ce5	74	}\r
70357ce5	75	#define SekSetStopS68k(x) { \\r
03e4f2a3	76	PicoCpuFS68k.execinfo &= ~FM68K_HALTED; \\r
03e4f2a3	77	if (x) { PicoCpuFS68k.execinfo \|= FM68K_HALTED; PicoCpuFS68k.io_cycle_counter = 0; } \\r
70357ce5	78	}\r
03e4f2a3	79	#define SekShouldInterrupt fm68k_would_interrupt()\r
	80	#ifdef EMU_M68K\r
	81	#define EMU_CORE_DEBUG\r
	82	#endif\r
cc68a136	83	#endif\r
	84	\r
	85	#ifdef EMU_M68K\r
	86	#include "../cpu/musashi/m68kcpu.h"\r
3aa1e148	87	extern m68ki_cpu_core PicoCpuMM68k, PicoCpuMS68k;\r
cc68a136	88	#ifndef SekCyclesLeft\r
3aa1e148	89	#define SekCyclesLeftNoMCD PicoCpuMM68k.cyc_remaining_cycles\r
7336a99a	90	#define SekCyclesLeft \\r
7336a99a	91	(((PicoMCD&1) && (PicoOpt & 0x2000)) ? (SekCycleAim-SekCycleCnt) : SekCyclesLeftNoMCD)\r
7a1f6e45	92	#define SekCyclesLeftS68k \\r
3aa1e148	93	((PicoOpt & 0x2000) ? (SekCycleAimS68k-SekCycleCntS68k) : PicoCpuMS68k.cyc_remaining_cycles)\r
7336a99a	94	#define SekSetCyclesLeftNoMCD(c) SET_CYCLES(c)\r
	95	#define SekSetCyclesLeft(c) { \\r
	96	if ((PicoMCD&1) && (PicoOpt & 0x2000)) SekCycleCnt=SekCycleAim-(c); else SET_CYCLES(c); \\r
	97	}\r
3aa1e148	98	#define SekPc m68k_get_reg(&PicoCpuMM68k, M68K_REG_PC)\r
3aa1e148	99	#define SekPcS68k m68k_get_reg(&PicoCpuMS68k, M68K_REG_PC)\r
7a1f6e45	100	#define SekSetStop(x) { \\r
3aa1e148	101	if(x) { SET_CYCLES(0); PicoCpuMM68k.stopped=STOP_LEVEL_STOP; } \\r
3aa1e148	102	else PicoCpuMM68k.stopped=0; \\r
7a1f6e45	103	}\r
7a1f6e45	104	#define SekSetStopS68k(x) { \\r
3aa1e148	105	if(x) { SET_CYCLES(0); PicoCpuMS68k.stopped=STOP_LEVEL_STOP; } \\r
3aa1e148	106	else PicoCpuMS68k.stopped=0; \\r
7a1f6e45	107	}\r
03e4f2a3	108	#define SekShouldInterrupt (CPU_INT_LEVEL > FLAG_INT_MASK)\r
cc68a136	109	#endif\r
	110	#endif\r
	111	\r
	112	extern int SekCycleCnt; // cycles done in this frame\r
	113	extern int SekCycleAim; // cycle aim\r
	114	extern unsigned int SekCycleCntT; // total cycle counter, updated once per frame\r
	115	\r
b8cbd802	116	#define SekCyclesReset() { \\r
	117	SekCycleCntT+=SekCycleAim; \\r
	118	SekCycleCnt-=SekCycleAim; \\r
	119	SekCycleAim=0; \\r
	120	}\r
cc68a136	121	#define SekCyclesBurn(c) SekCycleCnt+=c\r
	122	#define SekCyclesDone() (SekCycleAim-SekCyclesLeft) // nuber of cycles done in this frame (can be checked anywhere)\r
	123	#define SekCyclesDoneT() (SekCycleCntT+SekCyclesDone()) // total nuber of cycles done for this rom\r
	124	\r
	125	#define SekEndRun(after) { \\r
	126	SekCycleCnt -= SekCyclesLeft - after; \\r
	127	if(SekCycleCnt < 0) SekCycleCnt = 0; \\r
	128	SekSetCyclesLeft(after); \\r
	129	}\r
	130	\r
	131	extern int SekCycleCntS68k;\r
	132	extern int SekCycleAimS68k;\r
	133	\r
bf5fbbb4	134	#define SekCyclesResetS68k() { \\r
	135	SekCycleCntS68k-=SekCycleAimS68k; \\r
	136	SekCycleAimS68k=0; \\r
	137	}\r
7a1f6e45	138	#define SekCyclesDoneS68k() (SekCycleAimS68k-SekCyclesLeftS68k)\r
cc68a136	139	\r
03e4f2a3	140	#ifdef EMU_CORE_DEBUG\r
2d0b15bb	141	#undef SekSetCyclesLeftNoMCD\r
	142	#undef SekSetCyclesLeft\r
	143	#undef SekCyclesBurn\r
	144	#undef SekEndRun\r
	145	#define SekSetCyclesLeftNoMCD(c)\r
	146	#define SekSetCyclesLeft(c)\r
2270612a	147	#define SekCyclesBurn(c) c\r
2d0b15bb	148	#define SekEndRun(c)\r
2d0b15bb	149	#endif\r
cc68a136	150	\r
cc68a136	151	// ---------------------------------------------------------\r
cc68a136	152	\r
70357ce5	153	extern int PicoMCD;\r
70357ce5	154	\r
cc68a136	155	// main oscillator clock which controls timing\r
cc68a136	156	#define OSC_NTSC 53693100\r
b8cbd802	157	// seems to be accurate, see scans from http://www.hot.ee/tmeeco/\r
b8cbd802	158	#define OSC_PAL 53203424\r
cc68a136	159	\r
	160	struct PicoVideo\r
	161	{\r
	162	unsigned char reg[0x20];\r
b8cbd802	163	unsigned int command; // 32-bit Command\r
	164	unsigned char pending; // 1 if waiting for second half of 32-bit command\r
	165	unsigned char type; // Command type (v/c/vsram read/write)\r
	166	unsigned short addr; // Read/Write address\r
	167	int status; // Status bits\r
cc68a136	168	unsigned char pending_ints; // pending interrupts: ??VH????\r
b8cbd802	169	signed char lwrite_cnt; // VDP write count during active display line\r
b8cbd802	170	unsigned char pad[0x12];\r
cc68a136	171	};\r
	172	\r
	173	struct PicoMisc\r
	174	{\r
	175	unsigned char rotate;\r
	176	unsigned char z80Run;\r
e5503e2f	177	unsigned char padTHPhase[2]; // 02 phase of gamepad TH switches\r
	178	short scanline; // 04 0 to 261\|\|311; -1 in fast mode\r
	179	char dirtyPal; // 06 Is the palette dirty (1 - change @ this frame, 2 - some time before)\r
	180	unsigned char hardware; // 07 Hardware value for country\r
	181	unsigned char pal; // 08 1=PAL 0=NTSC\r
	182	unsigned char sram_reg; // SRAM mode register. bit0: allow read? bit1: deny write? bit2: EEPROM? bit4: detected? (header or by access)\r
	183	unsigned short z80_bank68k; // 0a\r
cc68a136	184	unsigned short z80_lastaddr; // this is for Z80 faking\r
	185	unsigned char z80_fakeval;\r
	186	unsigned char pad0;\r
e5503e2f	187	unsigned char padDelay[2]; // 10 gamepad phase time outs, so we count a delay\r
1dceadae	188	unsigned short eeprom_addr; // EEPROM address register\r
	189	unsigned char eeprom_cycle; // EEPROM SRAM cycle number\r
	190	unsigned char eeprom_slave; // EEPROM slave word for X24C02 and better SRAMs\r
721cd396	191	unsigned char prot_bytes[2]; // simple protection faking\r
b8cbd802	192	unsigned short dma_xfers;\r
312e9ce1	193	unsigned char pad[2];\r
312e9ce1	194	unsigned int frame_count; // mainly for movies\r
cc68a136	195	};\r
	196	\r
	197	// some assembly stuff depend on these, do not touch!\r
	198	struct Pico\r
	199	{\r
	200	unsigned char ram[0x10000]; // 0x00000 scratch ram\r
	201	unsigned short vram[0x8000]; // 0x10000\r
	202	unsigned char zram[0x2000]; // 0x20000 Z80 ram\r
	203	unsigned char ioports[0x10];\r
	204	unsigned int pad[0x3c]; // unused\r
	205	unsigned short cram[0x40]; // 0x22100\r
	206	unsigned short vsram[0x40]; // 0x22180\r
	207	\r
	208	unsigned char *rom; // 0x22200\r
	209	unsigned int romsize; // 0x22204\r
	210	\r
	211	struct PicoMisc m;\r
	212	struct PicoVideo video;\r
	213	};\r
	214	\r
	215	// sram\r
	216	struct PicoSRAM\r
	217	{\r
4ff2d527	218	unsigned char *data; // actual data\r
4ff2d527	219	unsigned int start; // start address in 68k address space\r
cc68a136	220	unsigned int end;\r
1dceadae	221	unsigned char unused1; // 0c: unused\r
1dceadae	222	unsigned char unused2;\r
cc68a136	223	unsigned char changed;\r
1dceadae	224	unsigned char eeprom_type; // eeprom type: 0: 7bit (24C01), 2: device with 2 addr words (X24C02+), 3: dev with 3 addr words\r
	225	unsigned char eeprom_abits; // eeprom access must be odd addr for: bit0 ~ cl, bit1 ~ out\r
	226	unsigned char eeprom_bit_cl; // bit number for cl\r
	227	unsigned char eeprom_bit_in; // bit number for in\r
	228	unsigned char eeprom_bit_out; // bit number for out\r
cc68a136	229	};\r
	230	\r
	231	// MCD\r
	232	#include "cd/cd_sys.h"\r
	233	#include "cd/LC89510.h"\r
d1df8786	234	#include "cd/gfx_cd.h"\r
cc68a136	235	\r
4f265db7	236	struct mcd_pcm\r
	237	{\r
	238	unsigned char control; // reg7\r
	239	unsigned char enabled; // reg8\r
	240	unsigned char cur_ch;\r
	241	unsigned char bank;\r
	242	int pad1;\r
	243	\r
4ff2d527	244	struct pcm_chan // 08, size 0x10\r
4f265db7	245	{\r
4f265db7	246	unsigned char regs[8];\r
4ff2d527	247	unsigned int addr; // .08: played sample address\r
4f265db7	248	int pad;\r
	249	} ch[8];\r
	250	};\r
	251	\r
c459aefd	252	struct mcd_misc\r
	253	{\r
	254	unsigned short hint_vector;\r
	255	unsigned char busreq;\r
51a902ae	256	unsigned char s68k_pend_ints;\r
89fa852d	257	unsigned int state_flags; // 04: emu state: reset_pending, dmna_pending\r
51a902ae	258	unsigned int counter75hz;\r
4ff2d527	259	unsigned short audio_offset; // 0c: for savestates: play pointer offset (0-1023)\r
75736070	260	unsigned char audio_track; // playing audio track # (zero based)\r
6cadc2da	261	char pad1;\r
4ff2d527	262	int timer_int3; // 10\r
4f265db7	263	unsigned int timer_stopwatch;\r
6cadc2da	264	unsigned char bcram_reg; // 18: battery-backed RAM cart register\r
	265	unsigned char pad2;\r
	266	unsigned short pad3;\r
	267	int pad[9];\r
c459aefd	268	};\r
c459aefd	269	\r
cc68a136	270	typedef struct\r
cc68a136	271	{\r
4ff2d527	272	unsigned char bios[0x20000]; // 000000: 128K\r
4ff2d527	273	union { // 020000: 512K\r
fa1e5e29	274	unsigned char prg_ram[0x80000];\r
cc68a136	275	unsigned char prg_ram_b[4][0x20000];\r
cc68a136	276	};\r
4ff2d527	277	union { // 0a0000: 256K\r
fa1e5e29	278	struct {\r
	279	unsigned char word_ram2M[0x40000];\r
	280	unsigned char unused[0x20000];\r
	281	};\r
	282	struct {\r
	283	unsigned char unused[0x20000];\r
	284	unsigned char word_ram1M[2][0x20000];\r
	285	};\r
	286	};\r
4ff2d527	287	union { // 100000: 64K\r
fa1e5e29	288	unsigned char pcm_ram[0x10000];\r
4f265db7	289	unsigned char pcm_ram_b[0x10][0x1000];\r
4f265db7	290	};\r
4ff2d527	291	unsigned char s68k_regs[0x200]; // 110000: GA, not CPU regs\r
	292	unsigned char bram[0x2000]; // 110200: 8K\r
	293	struct mcd_misc m; // 112200: misc\r
	294	struct mcd_pcm pcm; // 112240:\r
75736070	295	_scd_toc TOC; // not to be saved\r
cc68a136	296	CDD cdd;\r
	297	CDC cdc;\r
	298	_scd scd;\r
d1df8786	299	Rot_Comp rot_comp;\r
cc68a136	300	} mcd_state;\r
	301	\r
	302	#define Pico_mcd ((mcd_state *)Pico.rom)\r
	303	\r
51a902ae	304	// Area.c\r
eff55556	305	PICO_INTERNAL int PicoAreaPackCpu(unsigned char *cpu, int is_sub);\r
eff55556	306	PICO_INTERNAL int PicoAreaUnpackCpu(unsigned char *cpu, int is_sub);\r
51a902ae	307	\r
51a902ae	308	// cd/Area.c\r
eff55556	309	PICO_INTERNAL int PicoCdSaveState(void *file);\r
eff55556	310	PICO_INTERNAL int PicoCdLoadState(void *file);\r
cc68a136	311	\r
1dceadae	312	// Cart.c\r
	313	PICO_INTERNAL void PicoCartDetect(void);\r
	314	\r
03e4f2a3	315	// Debug.c\r
	316	int CM_compareRun(int cyc);\r
	317	\r
cc68a136	318	// Draw.c\r
eff55556	319	PICO_INTERNAL int PicoLine(int scan);\r
eff55556	320	PICO_INTERNAL void PicoFrameStart(void);\r
cc68a136	321	\r
cc68a136	322	// Draw2.c\r
eff55556	323	PICO_INTERNAL void PicoFrameFull();\r
cc68a136	324	\r
cc68a136	325	// Memory.c\r
eff55556	326	PICO_INTERNAL int PicoInitPc(unsigned int pc);\r
8ab3e3c1	327	PICO_INTERNAL_ASM unsigned int PicoRead32(unsigned int a);\r
eff55556	328	PICO_INTERNAL void PicoMemSetup(void);\r
eff55556	329	PICO_INTERNAL_ASM void PicoMemReset(void);\r
e5503e2f	330	PICO_INTERNAL int PadRead(int i);\r
eff55556	331	PICO_INTERNAL unsigned char z80_read(unsigned short a);\r
a4221917	332	#ifndef _USE_CZ80\r
eff55556	333	PICO_INTERNAL_ASM void z80_write(unsigned char data, unsigned short a);\r
eff55556	334	PICO_INTERNAL void z80_write16(unsigned short data, unsigned short a);\r
a4221917	335	PICO_INTERNAL unsigned short z80_read16(unsigned short a);\r
	336	#else\r
	337	PICO_INTERNAL_ASM void z80_write(unsigned int a, unsigned char data);\r
	338	#endif\r
cc68a136	339	\r
cc68a136	340	// cd/Memory.c\r
eff55556	341	PICO_INTERNAL void PicoMemSetupCD(void);\r
	342	PICO_INTERNAL_ASM void PicoMemResetCD(int r3);\r
	343	PICO_INTERNAL_ASM void PicoMemResetCDdecode(int r3);\r
cc68a136	344	\r
	345	// Pico.c\r
	346	extern struct Pico Pico;\r
	347	extern struct PicoSRAM SRam;\r
	348	extern int emustatus;\r
d9153729	349	extern int z80startCycle, z80stopCycle; // in 68k cycles\r
eff55556	350	PICO_INTERNAL int CheckDMA(void);\r
cc68a136	351	\r
cc68a136	352	// cd/Pico.c\r
e5f426aa	353	PICO_INTERNAL int PicoInitMCD(void);\r
e5f426aa	354	PICO_INTERNAL void PicoExitMCD(void);\r
eff55556	355	PICO_INTERNAL int PicoResetMCD(int hard);\r
eff55556	356	PICO_INTERNAL int PicoFrameMCD(void);\r
cc68a136	357	\r
cc68a136	358	// Sek.c\r
eff55556	359	PICO_INTERNAL int SekInit(void);\r
	360	PICO_INTERNAL int SekReset(void);\r
	361	PICO_INTERNAL int SekInterrupt(int irq);\r
3aa1e148	362	PICO_INTERNAL void SekState(int *data);\r
eff55556	363	PICO_INTERNAL void SekSetRealTAS(int use_real);\r
cc68a136	364	\r
cc68a136	365	// cd/Sek.c\r
eff55556	366	PICO_INTERNAL int SekInitS68k(void);\r
	367	PICO_INTERNAL int SekResetS68k(void);\r
	368	PICO_INTERNAL int SekInterruptS68k(int irq);\r
cc68a136	369	\r
7a93adeb	370	// sound/sound.c\r
	371	extern int PsndLen_exc_cnt;\r
	372	extern int PsndLen_exc_add;\r
	373	\r
cc68a136	374	// VideoPort.c\r
eff55556	375	PICO_INTERNAL_ASM void PicoVideoWrite(unsigned int a,unsigned short d);\r
eff55556	376	PICO_INTERNAL_ASM unsigned int PicoVideoRead(unsigned int a);\r
cc68a136	377	\r
cc68a136	378	// Misc.c\r
eff55556	379	PICO_INTERNAL void SRAMWriteEEPROM(unsigned int d);\r
	380	PICO_INTERNAL void SRAMUpdPending(unsigned int a, unsigned int d);\r
	381	PICO_INTERNAL_ASM unsigned int SRAMReadEEPROM(void);\r
	382	PICO_INTERNAL_ASM void memcpy16(unsigned short dest, unsigned short src, int count);\r
	383	PICO_INTERNAL_ASM void memcpy16bswap(unsigned short dest, void src, int count);\r
	384	PICO_INTERNAL_ASM void memcpy32(int dest, int src, int count); // 32bit word count\r
	385	PICO_INTERNAL_ASM void memset32(int *dest, int c, int count);\r
cc68a136	386	\r
fa1e5e29	387	// cd/Misc.c\r
eff55556	388	PICO_INTERNAL_ASM void wram_2M_to_1M(unsigned char *m);\r
	389	PICO_INTERNAL_ASM void wram_1M_to_2M(unsigned char *m);\r
	390	\r
	391	// cd/buffering.c\r
	392	PICO_INTERNAL void PicoCDBufferRead(void *dest, int lba);\r
	393	\r
	394	// sound/sound.c\r
9d917eea	395	PICO_INTERNAL void PsndReset(void);\r
	396	PICO_INTERNAL void Psnd_timers_and_dac(int raster);\r
	397	PICO_INTERNAL int PsndRender(int offset, int length);\r
	398	PICO_INTERNAL void PsndClear(void);\r
eff55556	399	// z80 functionality wrappers\r
	400	PICO_INTERNAL void z80_init(void);\r
	401	PICO_INTERNAL void z80_resetCycles(void);\r
	402	PICO_INTERNAL void z80_int(void);\r
	403	PICO_INTERNAL int z80_run(int cycles);\r
	404	PICO_INTERNAL void z80_pack(unsigned char *data);\r
	405	PICO_INTERNAL void z80_unpack(unsigned char *data);\r
	406	PICO_INTERNAL void z80_reset(void);\r
	407	PICO_INTERNAL void z80_exit(void);\r
fa1e5e29	408	\r
cc68a136	409	\r
	410	#ifdef __cplusplus\r
	411	} // End of extern "C"\r
	412	#endif\r
eff55556	413	\r
b8cbd802	414	// emulation event logging\r
	415	#ifndef EL_LOGMASK\r
	416	#define EL_LOGMASK 0\r
	417	#endif\r
	418	\r
	419	#define EL_HVCNT 0x0001 /* hv counter reads */\r
	420	#define EL_SR 0x0002 /* SR reads */\r
	421	#define EL_INTS 0x0004 /* ints and acks */\r
	422	#define EL_YM2612R 0x0008 /* 68k ym2612 reads */\r
	423	#define EL_INTSW 0x0010 /* log irq switching on/off */\r
	424	#define EL_ASVDP 0x0020 /* VDP accesses during active scan */\r
	425	#define EL_VDPDMA 0x0040 /* VDP DMA transfers and their timing */\r
5f20bb80	426	#define EL_BUSREQ 0x0080 /* z80 busreq r/w or reset w */\r
b8cbd802	427	#define EL_Z80BNK 0x0100 /* z80 i/o through bank area */\r
1dceadae	428	#define EL_SRAMIO 0x0200 /* sram i/o */\r
	429	#define EL_EEPROM 0x0400 /* eeprom debug */\r
	430	#define EL_UIO 0x0800 /* unmapped i/o */\r
5f20bb80	431	#define EL_IO 0x1000 /* all i/o (TODO) */\r
b8cbd802	432	\r
	433	#define EL_STATUS 0x4000 /* status messages */\r
	434	#define EL_ANOMALY 0x8000 /* some unexpected conditions */\r
	435	\r
	436	#if EL_LOGMASK\r
	437	#define elprintf(w,f,...) \\r
	438	{ \\r
	439	if ((w) & EL_LOGMASK) \\r
	440	printf("%05i:%03i: " f "\n",Pico.m.frame_count,Pico.m.scanline,##__VA_ARGS__); \\r
	441	}\r
	442	#else\r
	443	#define elprintf(w,f,...)\r
	444	#endif\r
	445	\r
eff55556	446	#endif // PICO_INTERNAL_INCLUDED\r
eff55556	447	\r