cff531af |
1 | /* |
2 | * PicoDrive |
ae214f1c |
3 | * (C) notaz, 2007,2013 |
cff531af |
4 | * |
5 | * This work is licensed under the terms of MAME license. |
6 | * See COPYING file in the top-level directory. |
7 | */ |
cc68a136 |
8 | |
efcba75f |
9 | #include "../pico_int.h" |
43e6eaad |
10 | #include "../sound/ym2612.h" |
cc68a136 |
11 | |
76276b0b |
12 | extern unsigned char formatted_bram[4*0x10]; |
ae214f1c |
13 | |
a6523294 |
14 | static unsigned int mcd_m68k_cycle_mult; |
15 | static unsigned int mcd_m68k_cycle_base; |
16 | static unsigned int mcd_s68k_cycle_base; |
89fa852d |
17 | |
721cd396 |
18 | void (*PicoMCDopenTray)(void) = NULL; |
d687ef50 |
19 | void (*PicoMCDcloseTray)(void) = NULL; |
89fa852d |
20 | |
cc68a136 |
21 | |
2aa27095 |
22 | PICO_INTERNAL void PicoInitMCD(void) |
cc68a136 |
23 | { |
24 | SekInitS68k(); |
cc68a136 |
25 | } |
26 | |
eff55556 |
27 | PICO_INTERNAL void PicoExitMCD(void) |
cc68a136 |
28 | { |
cc68a136 |
29 | } |
30 | |
1cb1584b |
31 | PICO_INTERNAL void PicoPowerMCD(void) |
32 | { |
8e4e84c2 |
33 | SekCycleCntS68k = SekCycleAimS68k = 0; |
34 | |
1cb1584b |
35 | int fmt_size = sizeof(formatted_bram); |
36 | memset(Pico_mcd->prg_ram, 0, sizeof(Pico_mcd->prg_ram)); |
37 | memset(Pico_mcd->word_ram2M, 0, sizeof(Pico_mcd->word_ram2M)); |
38 | memset(Pico_mcd->pcm_ram, 0, sizeof(Pico_mcd->pcm_ram)); |
39 | memset(Pico_mcd->bram, 0, sizeof(Pico_mcd->bram)); |
4fb43555 |
40 | memcpy(Pico_mcd->bram + sizeof(Pico_mcd->bram) - fmt_size, |
41 | formatted_bram, fmt_size); |
51a902ae |
42 | memset(Pico_mcd->s68k_regs, 0, sizeof(Pico_mcd->s68k_regs)); |
4f265db7 |
43 | memset(&Pico_mcd->pcm, 0, sizeof(Pico_mcd->pcm)); |
5c69a605 |
44 | memset(&Pico_mcd->m, 0, sizeof(Pico_mcd->m)); |
51a902ae |
45 | |
3f23709e |
46 | cdc_init(); |
274fcc35 |
47 | gfx_init(); |
d0132772 |
48 | |
4fb43555 |
49 | // cold reset state (tested) |
50 | Pico_mcd->m.state_flags = PCD_ST_S68K_RST; |
51 | Pico_mcd->m.busreq = 2; // busreq on, s68k in reset |
52 | Pico_mcd->s68k_regs[3] = 1; // 2M word RAM mode, m68k access |
4fb43555 |
53 | memset(Pico_mcd->bios + 0x70, 0xff, 4); |
54 | } |
cc68a136 |
55 | |
d0132772 |
56 | void pcd_soft_reset(void) |
4fb43555 |
57 | { |
7b3ddc11 |
58 | elprintf(EL_CD, "cd: soft reset"); |
d0132772 |
59 | |
3f23709e |
60 | Pico_mcd->m.s68k_pend_ints = 0; |
61 | cdc_reset(); |
274fcc35 |
62 | cdd_reset(); |
3aa1e148 |
63 | #ifdef _ASM_CD_MEMORY_C |
00bd648e |
64 | //PicoMemResetCDdecode(1); // don't have to call this in 2M mode |
4ff2d527 |
65 | #endif |
cc68a136 |
66 | |
7b3ddc11 |
67 | memset(&Pico_mcd->s68k_regs[0x38], 0, 9); |
68 | Pico_mcd->s68k_regs[0x38+9] = 0x0f; // default checksum |
69 | |
d0132772 |
70 | pcd_event_schedule_s68k(PCD_EVENT_CDC, 12500000/75); |
71 | |
72 | // TODO: test if register state/timers change |
73 | } |
74 | |
75 | PICO_INTERNAL int PicoResetMCD(void) |
76 | { |
77 | // reset button doesn't affect MCD hardware |
78 | |
6cadc2da |
79 | // use SRam.data for RAM cart |
af37bca8 |
80 | if (PicoOpt & POPT_EN_MCD_RAMCART) { |
d6114368 |
81 | if (SRam.data == NULL) |
82 | SRam.data = calloc(1, 0x12000); |
83 | } |
84 | else if (SRam.data != NULL) { |
85 | free(SRam.data); |
86 | SRam.data = NULL; |
87 | } |
b542be46 |
88 | SRam.start = SRam.end = 0; // unused |
6cadc2da |
89 | |
cc68a136 |
90 | return 0; |
91 | } |
92 | |
ae214f1c |
93 | static __inline void SekRunS68k(unsigned int to) |
cc68a136 |
94 | { |
95 | int cyc_do; |
ae214f1c |
96 | |
97 | SekCycleAimS68k = to; |
98 | if ((cyc_do = SekCycleAimS68k - SekCycleCntS68k) <= 0) |
99 | return; |
100 | |
30e8aac4 |
101 | if (SekShouldInterrupt()) |
102 | Pico_mcd->m.s68k_poll_a = 0; |
103 | |
ae214f1c |
104 | SekCycleCntS68k += cyc_do; |
105 | #if defined(EMU_C68K) |
106 | PicoCpuCS68k.cycles = cyc_do; |
3aa1e148 |
107 | CycloneRun(&PicoCpuCS68k); |
ae214f1c |
108 | SekCycleCntS68k -= PicoCpuCS68k.cycles; |
b837b69b |
109 | #elif defined(EMU_M68K) |
3aa1e148 |
110 | m68k_set_context(&PicoCpuMS68k); |
ae214f1c |
111 | SekCycleCntS68k += m68k_execute(cyc_do) - cyc_do; |
ed4402a7 |
112 | m68k_set_context(&PicoCpuMM68k); |
3aa1e148 |
113 | #elif defined(EMU_F68K) |
ae214f1c |
114 | g_m68kcontext = &PicoCpuFS68k; |
99ade2ee |
115 | SekCycleCntS68k += fm68k_emulate(cyc_do, 0) - cyc_do; |
ae214f1c |
116 | g_m68kcontext = &PicoCpuFM68k; |
cc68a136 |
117 | #endif |
118 | } |
119 | |
8e4e84c2 |
120 | static void pcd_set_cycle_mult(void) |
121 | { |
122 | // ~1.63 for NTSC, ~1.645 for PAL |
123 | if (Pico.m.pal) |
a6523294 |
124 | mcd_m68k_cycle_mult = ((12500000ull << 16) / (50*312*488)); |
8e4e84c2 |
125 | else |
a6523294 |
126 | mcd_m68k_cycle_mult = ((12500000ull << 16) / (60*262*488)) + 1; |
8e4e84c2 |
127 | } |
68cba51e |
128 | |
ae214f1c |
129 | unsigned int pcd_cycles_m68k_to_s68k(unsigned int c) |
8022f53d |
130 | { |
a6523294 |
131 | return (long long)c * mcd_m68k_cycle_mult >> 16; |
8022f53d |
132 | } |
ae214f1c |
133 | |
134 | /* events */ |
135 | static void pcd_cdc_event(unsigned int now) |
68cba51e |
136 | { |
ae214f1c |
137 | // 75Hz CDC update |
274fcc35 |
138 | cdd_update(); |
139 | |
140 | /* check if a new CDD command has been processed */ |
141 | if (!(Pico_mcd->s68k_regs[0x4b] & 0xf0)) |
142 | { |
143 | /* reset CDD command wait flag */ |
144 | Pico_mcd->s68k_regs[0x4b] = 0xf0; |
145 | |
146 | if (Pico_mcd->s68k_regs[0x33] & PCDS_IEN4) { |
147 | elprintf(EL_INTS|EL_CD, "s68k: cdd irq 4"); |
148 | SekInterruptS68k(4); |
149 | } |
150 | } |
151 | |
ae214f1c |
152 | pcd_event_schedule(now, PCD_EVENT_CDC, 12500000/75); |
153 | } |
7336a99a |
154 | |
ae214f1c |
155 | static void pcd_int3_timer_event(unsigned int now) |
156 | { |
157 | if (Pico_mcd->s68k_regs[0x33] & PCDS_IEN3) { |
158 | elprintf(EL_INTS|EL_CD, "s68k: timer irq 3"); |
159 | SekInterruptS68k(3); |
160 | } |
7336a99a |
161 | |
ae214f1c |
162 | if (Pico_mcd->s68k_regs[0x31] != 0) |
163 | pcd_event_schedule(now, PCD_EVENT_TIMER3, |
164 | Pico_mcd->s68k_regs[0x31] * 384); |
165 | } |
166 | |
ae214f1c |
167 | static void pcd_dma_event(unsigned int now) |
168 | { |
3f23709e |
169 | cdc_dma_update(); |
ae214f1c |
170 | } |
68cba51e |
171 | |
ae214f1c |
172 | typedef void (event_cb)(unsigned int now); |
173 | |
174 | /* times are in s68k (12.5MHz) cycles */ |
175 | unsigned int pcd_event_times[PCD_EVENT_COUNT]; |
176 | static unsigned int event_time_next; |
177 | static event_cb *pcd_event_cbs[PCD_EVENT_COUNT] = { |
178 | [PCD_EVENT_CDC] = pcd_cdc_event, |
179 | [PCD_EVENT_TIMER3] = pcd_int3_timer_event, |
a93a80de |
180 | [PCD_EVENT_GFX] = gfx_update, |
ae214f1c |
181 | [PCD_EVENT_DMA] = pcd_dma_event, |
182 | }; |
183 | |
184 | void pcd_event_schedule(unsigned int now, enum pcd_event event, int after) |
bf098bc5 |
185 | { |
ae214f1c |
186 | unsigned int when; |
187 | |
188 | when = now + after; |
189 | if (when == 0) { |
190 | // event cancelled |
191 | pcd_event_times[event] = 0; |
192 | return; |
193 | } |
bf098bc5 |
194 | |
ae214f1c |
195 | when |= 1; |
bf098bc5 |
196 | |
ae214f1c |
197 | elprintf(EL_CD, "cd: new event #%u %u->%u", event, now, when); |
198 | pcd_event_times[event] = when; |
bf098bc5 |
199 | |
ae214f1c |
200 | if (event_time_next == 0 || CYCLES_GT(event_time_next, when)) |
201 | event_time_next = when; |
bf098bc5 |
202 | } |
203 | |
ae214f1c |
204 | void pcd_event_schedule_s68k(enum pcd_event event, int after) |
4f265db7 |
205 | { |
ae214f1c |
206 | if (SekCyclesLeftS68k > after) |
207 | SekEndRunS68k(after); |
4f265db7 |
208 | |
ae214f1c |
209 | pcd_event_schedule(SekCyclesDoneS68k(), event, after); |
210 | } |
4f265db7 |
211 | |
ae214f1c |
212 | static void pcd_run_events(unsigned int until) |
213 | { |
214 | int oldest, oldest_diff, time; |
215 | int i, diff; |
216 | |
217 | while (1) { |
218 | oldest = -1, oldest_diff = 0x7fffffff; |
219 | |
220 | for (i = 0; i < PCD_EVENT_COUNT; i++) { |
221 | if (pcd_event_times[i]) { |
222 | diff = pcd_event_times[i] - until; |
223 | if (diff < oldest_diff) { |
224 | oldest_diff = diff; |
225 | oldest = i; |
226 | } |
227 | } |
228 | } |
229 | |
230 | if (oldest_diff <= 0) { |
231 | time = pcd_event_times[oldest]; |
232 | pcd_event_times[oldest] = 0; |
233 | elprintf(EL_CD, "cd: run event #%d %u", oldest, time); |
234 | pcd_event_cbs[oldest](time); |
235 | } |
236 | else if (oldest_diff < 0x7fffffff) { |
237 | event_time_next = pcd_event_times[oldest]; |
238 | break; |
239 | } |
240 | else { |
241 | event_time_next = 0; |
242 | break; |
243 | } |
244 | } |
4f265db7 |
245 | |
ae214f1c |
246 | if (oldest != -1) |
247 | elprintf(EL_CD, "cd: next event #%d at %u", |
248 | oldest, event_time_next); |
4f265db7 |
249 | } |
250 | |
08769494 |
251 | int pcd_sync_s68k(unsigned int m68k_target, int m68k_poll_sync) |
ae214f1c |
252 | { |
253 | #define now SekCycleCntS68k |
a6523294 |
254 | unsigned int s68k_target; |
ae214f1c |
255 | unsigned int target; |
b837b69b |
256 | |
a6523294 |
257 | target = m68k_target - mcd_m68k_cycle_base; |
258 | s68k_target = mcd_s68k_cycle_base + |
259 | ((unsigned long long)target * mcd_m68k_cycle_mult >> 16); |
260 | |
08769494 |
261 | elprintf(EL_CD, "s68k sync to %u, %u->%u", |
262 | m68k_target, now, s68k_target); |
ae214f1c |
263 | |
4fb43555 |
264 | if (Pico_mcd->m.busreq != 1) { /* busreq/reset */ |
ae214f1c |
265 | SekCycleCntS68k = SekCycleAimS68k = s68k_target; |
266 | pcd_run_events(m68k_target); |
08769494 |
267 | return 0; |
ae214f1c |
268 | } |
269 | |
270 | while (CYCLES_GT(s68k_target, now)) { |
271 | if (event_time_next && CYCLES_GE(now, event_time_next)) |
272 | pcd_run_events(now); |
273 | |
274 | target = s68k_target; |
275 | if (event_time_next && CYCLES_GT(target, event_time_next)) |
276 | target = event_time_next; |
277 | |
278 | SekRunS68k(target); |
08769494 |
279 | if (m68k_poll_sync && Pico_mcd->m.m68k_poll_cnt == 0) |
280 | break; |
ae214f1c |
281 | } |
08769494 |
282 | |
283 | return s68k_target - now; |
ae214f1c |
284 | #undef now |
c987bb5c |
285 | } |
ae214f1c |
286 | |
ba6e8bfd |
287 | #define pcd_run_cpus_normal pcd_run_cpus |
288 | //#define pcd_run_cpus_lockstep pcd_run_cpus |
289 | |
08769494 |
290 | static void SekSyncM68k(void); |
291 | |
fa8fb754 |
292 | void pcd_run_cpus_normal(int m68k_cycles) |
08769494 |
293 | { |
294 | SekCycleAim += m68k_cycles; |
30e8aac4 |
295 | if (SekShouldInterrupt() || Pico_mcd->m.m68k_poll_cnt < 12) |
cc5ffc3c |
296 | Pico_mcd->m.m68k_poll_cnt = 0; |
297 | else if (Pico_mcd->m.m68k_poll_cnt >= 16) { |
08769494 |
298 | int s68k_left = pcd_sync_s68k(SekCycleAim, 1); |
299 | if (s68k_left <= 0) { |
ba6e8bfd |
300 | elprintf(EL_CDPOLL, "m68k poll [%02x] x%d @%06x", |
08769494 |
301 | Pico_mcd->m.m68k_poll_a, Pico_mcd->m.m68k_poll_cnt, SekPc); |
302 | SekCycleCnt = SekCycleAim; |
303 | return; |
304 | } |
305 | SekCycleCnt = SekCycleAim - (s68k_left * 40220 >> 16); |
306 | } |
307 | |
308 | SekSyncM68k(); |
309 | } |
310 | |
fa8fb754 |
311 | void pcd_run_cpus_lockstep(int m68k_cycles) |
ba6e8bfd |
312 | { |
313 | unsigned int target = SekCycleAim + m68k_cycles; |
314 | do { |
315 | SekCycleAim += 8; |
316 | SekSyncM68k(); |
317 | pcd_sync_s68k(SekCycleAim, 0); |
318 | } while (CYCLES_GT(target, SekCycleAim)); |
cc5ffc3c |
319 | |
320 | SekCycleAim = target; |
ba6e8bfd |
321 | } |
322 | |
ae214f1c |
323 | #define PICO_CD |
324 | #define CPUS_RUN(m68k_cycles) \ |
08769494 |
325 | pcd_run_cpus(m68k_cycles) |
ae214f1c |
326 | |
efcba75f |
327 | #include "../pico_cmn.c" |
cc68a136 |
328 | |
329 | |
a6523294 |
330 | void pcd_prepare_frame(void) |
331 | { |
332 | pcd_set_cycle_mult(); |
333 | |
334 | // need this because we can't have direct mapping between |
335 | // master<->slave cycle counters because of overflows |
336 | mcd_m68k_cycle_base = SekCycleAim; |
337 | mcd_s68k_cycle_base = SekCycleAimS68k; |
338 | } |
339 | |
2aa27095 |
340 | PICO_INTERNAL void PicoFrameMCD(void) |
cc68a136 |
341 | { |
a6523294 |
342 | PicoFrameStart(); |
cc68a136 |
343 | |
a6523294 |
344 | pcd_prepare_frame(); |
bf5fbbb4 |
345 | PicoFrameHints(); |
cc68a136 |
346 | } |
347 | |
ae214f1c |
348 | void pcd_state_loaded(void) |
349 | { |
350 | unsigned int cycles; |
351 | int diff; |
352 | |
8e4e84c2 |
353 | pcd_set_cycle_mult(); |
ae214f1c |
354 | pcd_state_loaded_mem(); |
355 | |
33be04ca |
356 | memset(Pico_mcd->pcm_mixbuf, 0, sizeof(Pico_mcd->pcm_mixbuf)); |
357 | Pico_mcd->pcm_mixbuf_dirty = 0; |
358 | Pico_mcd->pcm_mixpos = 0; |
021e47b3 |
359 | Pico_mcd->pcm_regs_dirty = 1; |
33be04ca |
360 | |
ae214f1c |
361 | // old savestates.. |
362 | cycles = pcd_cycles_m68k_to_s68k(SekCycleAim); |
363 | diff = cycles - SekCycleAimS68k; |
364 | if (diff < -1000 || diff > 1000) { |
365 | SekCycleCntS68k = SekCycleAimS68k = cycles; |
366 | } |
367 | if (pcd_event_times[PCD_EVENT_CDC] == 0) { |
368 | pcd_event_schedule(SekCycleAimS68k, PCD_EVENT_CDC, 12500000/75); |
369 | |
370 | if (Pico_mcd->s68k_regs[0x31]) |
371 | pcd_event_schedule(SekCycleAimS68k, PCD_EVENT_TIMER3, |
372 | Pico_mcd->s68k_regs[0x31] * 384); |
ae214f1c |
373 | } |
334d9fb6 |
374 | |
375 | diff = cycles - Pico_mcd->pcm.update_cycles; |
376 | if ((unsigned int)diff > 12500000/50) |
33be04ca |
377 | Pico_mcd->pcm.update_cycles = cycles; |
8e4e84c2 |
378 | |
379 | // reschedule |
380 | event_time_next = 0; |
381 | pcd_run_events(SekCycleCntS68k); |
ae214f1c |
382 | } |
cc68a136 |
383 | |
ae214f1c |
384 | // vim:shiftwidth=2:ts=2:expandtab |