Merge pull request #26 from EXL/fix_avcodec_compile_errors
[picodrive.git] / pico / cd / mcd.c
CommitLineData
cff531af 1/*
2 * PicoDrive
ae214f1c 3 * (C) notaz, 2007,2013
cff531af 4 *
5 * This work is licensed under the terms of MAME license.
6 * See COPYING file in the top-level directory.
7 */
cc68a136 8
efcba75f 9#include "../pico_int.h"
43e6eaad 10#include "../sound/ym2612.h"
cc68a136 11
76276b0b 12extern unsigned char formatted_bram[4*0x10];
ae214f1c 13
a6523294 14static unsigned int mcd_m68k_cycle_mult;
15static unsigned int mcd_m68k_cycle_base;
16static unsigned int mcd_s68k_cycle_base;
89fa852d 17
721cd396 18void (*PicoMCDopenTray)(void) = NULL;
d687ef50 19void (*PicoMCDcloseTray)(void) = NULL;
89fa852d 20
cc68a136 21
2aa27095 22PICO_INTERNAL void PicoInitMCD(void)
cc68a136 23{
24 SekInitS68k();
cc68a136 25}
26
eff55556 27PICO_INTERNAL void PicoExitMCD(void)
cc68a136 28{
cc68a136 29}
30
1cb1584b 31PICO_INTERNAL void PicoPowerMCD(void)
32{
8e4e84c2 33 SekCycleCntS68k = SekCycleAimS68k = 0;
34
1cb1584b 35 int fmt_size = sizeof(formatted_bram);
36 memset(Pico_mcd->prg_ram, 0, sizeof(Pico_mcd->prg_ram));
37 memset(Pico_mcd->word_ram2M, 0, sizeof(Pico_mcd->word_ram2M));
38 memset(Pico_mcd->pcm_ram, 0, sizeof(Pico_mcd->pcm_ram));
39 memset(Pico_mcd->bram, 0, sizeof(Pico_mcd->bram));
4fb43555 40 memcpy(Pico_mcd->bram + sizeof(Pico_mcd->bram) - fmt_size,
41 formatted_bram, fmt_size);
51a902ae 42 memset(Pico_mcd->s68k_regs, 0, sizeof(Pico_mcd->s68k_regs));
4f265db7 43 memset(&Pico_mcd->pcm, 0, sizeof(Pico_mcd->pcm));
5c69a605 44 memset(&Pico_mcd->m, 0, sizeof(Pico_mcd->m));
51a902ae 45
3f23709e 46 cdc_init();
274fcc35 47 gfx_init();
d0132772 48
4fb43555 49 // cold reset state (tested)
50 Pico_mcd->m.state_flags = PCD_ST_S68K_RST;
51 Pico_mcd->m.busreq = 2; // busreq on, s68k in reset
52 Pico_mcd->s68k_regs[3] = 1; // 2M word RAM mode, m68k access
4fb43555 53 memset(Pico_mcd->bios + 0x70, 0xff, 4);
54}
cc68a136 55
d0132772 56void pcd_soft_reset(void)
4fb43555 57{
7b3ddc11 58 elprintf(EL_CD, "cd: soft reset");
d0132772 59
3f23709e 60 Pico_mcd->m.s68k_pend_ints = 0;
61 cdc_reset();
274fcc35 62 cdd_reset();
3aa1e148 63#ifdef _ASM_CD_MEMORY_C
00bd648e 64 //PicoMemResetCDdecode(1); // don't have to call this in 2M mode
4ff2d527 65#endif
cc68a136 66
7b3ddc11 67 memset(&Pico_mcd->s68k_regs[0x38], 0, 9);
68 Pico_mcd->s68k_regs[0x38+9] = 0x0f; // default checksum
69
d0132772 70 pcd_event_schedule_s68k(PCD_EVENT_CDC, 12500000/75);
71
72 // TODO: test if register state/timers change
73}
74
75PICO_INTERNAL int PicoResetMCD(void)
76{
77 // reset button doesn't affect MCD hardware
78
6cadc2da 79 // use SRam.data for RAM cart
af37bca8 80 if (PicoOpt & POPT_EN_MCD_RAMCART) {
d6114368 81 if (SRam.data == NULL)
82 SRam.data = calloc(1, 0x12000);
83 }
84 else if (SRam.data != NULL) {
85 free(SRam.data);
86 SRam.data = NULL;
87 }
b542be46 88 SRam.start = SRam.end = 0; // unused
6cadc2da 89
cc68a136 90 return 0;
91}
92
6901d0e4 93static void SekRunM68kOnce(void)
94{
95 int cyc_do;
96 pevt_log_m68k_o(EVT_RUN_START);
97
98 if ((cyc_do = SekCycleAim - SekCycleCnt) > 0) {
99 SekCycleCnt += cyc_do;
100
101#if defined(EMU_C68K)
102 PicoCpuCM68k.cycles = cyc_do;
103 CycloneRun(&PicoCpuCM68k);
104 SekCycleCnt -= PicoCpuCM68k.cycles;
105#elif defined(EMU_M68K)
106 SekCycleCnt += m68k_execute(cyc_do) - cyc_do;
107#elif defined(EMU_F68K)
108 SekCycleCnt += fm68k_emulate(cyc_do, 0) - cyc_do;
109#endif
110 }
111
112 SekCyclesLeft = 0;
113
114 SekTrace(0);
115 pevt_log_m68k_o(EVT_RUN_END);
116}
117
118static void SekRunS68k(unsigned int to)
cc68a136 119{
120 int cyc_do;
ae214f1c 121
122 SekCycleAimS68k = to;
123 if ((cyc_do = SekCycleAimS68k - SekCycleCntS68k) <= 0)
124 return;
125
30e8aac4 126 if (SekShouldInterrupt())
127 Pico_mcd->m.s68k_poll_a = 0;
128
ae214f1c 129 SekCycleCntS68k += cyc_do;
130#if defined(EMU_C68K)
131 PicoCpuCS68k.cycles = cyc_do;
3aa1e148 132 CycloneRun(&PicoCpuCS68k);
ae214f1c 133 SekCycleCntS68k -= PicoCpuCS68k.cycles;
b837b69b 134#elif defined(EMU_M68K)
3aa1e148 135 m68k_set_context(&PicoCpuMS68k);
ae214f1c 136 SekCycleCntS68k += m68k_execute(cyc_do) - cyc_do;
ed4402a7 137 m68k_set_context(&PicoCpuMM68k);
3aa1e148 138#elif defined(EMU_F68K)
ae214f1c 139 g_m68kcontext = &PicoCpuFS68k;
99ade2ee 140 SekCycleCntS68k += fm68k_emulate(cyc_do, 0) - cyc_do;
ae214f1c 141 g_m68kcontext = &PicoCpuFM68k;
cc68a136 142#endif
143}
144
8e4e84c2 145static void pcd_set_cycle_mult(void)
146{
147 // ~1.63 for NTSC, ~1.645 for PAL
148 if (Pico.m.pal)
a6523294 149 mcd_m68k_cycle_mult = ((12500000ull << 16) / (50*312*488));
8e4e84c2 150 else
a6523294 151 mcd_m68k_cycle_mult = ((12500000ull << 16) / (60*262*488)) + 1;
8e4e84c2 152}
68cba51e 153
ae214f1c 154unsigned int pcd_cycles_m68k_to_s68k(unsigned int c)
8022f53d 155{
a6523294 156 return (long long)c * mcd_m68k_cycle_mult >> 16;
8022f53d 157}
ae214f1c 158
159/* events */
160static void pcd_cdc_event(unsigned int now)
68cba51e 161{
ae214f1c 162 // 75Hz CDC update
274fcc35 163 cdd_update();
164
165 /* check if a new CDD command has been processed */
166 if (!(Pico_mcd->s68k_regs[0x4b] & 0xf0))
167 {
168 /* reset CDD command wait flag */
169 Pico_mcd->s68k_regs[0x4b] = 0xf0;
170
171 if (Pico_mcd->s68k_regs[0x33] & PCDS_IEN4) {
172 elprintf(EL_INTS|EL_CD, "s68k: cdd irq 4");
173 SekInterruptS68k(4);
174 }
175 }
176
ae214f1c 177 pcd_event_schedule(now, PCD_EVENT_CDC, 12500000/75);
178}
7336a99a 179
ae214f1c 180static void pcd_int3_timer_event(unsigned int now)
181{
182 if (Pico_mcd->s68k_regs[0x33] & PCDS_IEN3) {
183 elprintf(EL_INTS|EL_CD, "s68k: timer irq 3");
184 SekInterruptS68k(3);
185 }
7336a99a 186
ae214f1c 187 if (Pico_mcd->s68k_regs[0x31] != 0)
188 pcd_event_schedule(now, PCD_EVENT_TIMER3,
189 Pico_mcd->s68k_regs[0x31] * 384);
190}
191
ae214f1c 192static void pcd_dma_event(unsigned int now)
193{
3f23709e 194 cdc_dma_update();
ae214f1c 195}
68cba51e 196
ae214f1c 197typedef void (event_cb)(unsigned int now);
198
199/* times are in s68k (12.5MHz) cycles */
200unsigned int pcd_event_times[PCD_EVENT_COUNT];
201static unsigned int event_time_next;
202static event_cb *pcd_event_cbs[PCD_EVENT_COUNT] = {
203 [PCD_EVENT_CDC] = pcd_cdc_event,
204 [PCD_EVENT_TIMER3] = pcd_int3_timer_event,
a93a80de 205 [PCD_EVENT_GFX] = gfx_update,
ae214f1c 206 [PCD_EVENT_DMA] = pcd_dma_event,
207};
208
209void pcd_event_schedule(unsigned int now, enum pcd_event event, int after)
bf098bc5 210{
ae214f1c 211 unsigned int when;
212
213 when = now + after;
214 if (when == 0) {
215 // event cancelled
216 pcd_event_times[event] = 0;
217 return;
218 }
bf098bc5 219
ae214f1c 220 when |= 1;
bf098bc5 221
ae214f1c 222 elprintf(EL_CD, "cd: new event #%u %u->%u", event, now, when);
223 pcd_event_times[event] = when;
bf098bc5 224
ae214f1c 225 if (event_time_next == 0 || CYCLES_GT(event_time_next, when))
226 event_time_next = when;
bf098bc5 227}
228
ae214f1c 229void pcd_event_schedule_s68k(enum pcd_event event, int after)
4f265db7 230{
ae214f1c 231 if (SekCyclesLeftS68k > after)
232 SekEndRunS68k(after);
4f265db7 233
ae214f1c 234 pcd_event_schedule(SekCyclesDoneS68k(), event, after);
235}
4f265db7 236
ae214f1c 237static void pcd_run_events(unsigned int until)
238{
239 int oldest, oldest_diff, time;
240 int i, diff;
241
242 while (1) {
243 oldest = -1, oldest_diff = 0x7fffffff;
244
245 for (i = 0; i < PCD_EVENT_COUNT; i++) {
246 if (pcd_event_times[i]) {
247 diff = pcd_event_times[i] - until;
248 if (diff < oldest_diff) {
249 oldest_diff = diff;
250 oldest = i;
251 }
252 }
253 }
254
255 if (oldest_diff <= 0) {
256 time = pcd_event_times[oldest];
257 pcd_event_times[oldest] = 0;
258 elprintf(EL_CD, "cd: run event #%d %u", oldest, time);
259 pcd_event_cbs[oldest](time);
260 }
261 else if (oldest_diff < 0x7fffffff) {
262 event_time_next = pcd_event_times[oldest];
263 break;
264 }
265 else {
266 event_time_next = 0;
267 break;
268 }
269 }
4f265db7 270
ae214f1c 271 if (oldest != -1)
272 elprintf(EL_CD, "cd: next event #%d at %u",
273 oldest, event_time_next);
4f265db7 274}
275
08769494 276int pcd_sync_s68k(unsigned int m68k_target, int m68k_poll_sync)
ae214f1c 277{
278 #define now SekCycleCntS68k
a6523294 279 unsigned int s68k_target;
ae214f1c 280 unsigned int target;
b837b69b 281
a6523294 282 target = m68k_target - mcd_m68k_cycle_base;
283 s68k_target = mcd_s68k_cycle_base +
284 ((unsigned long long)target * mcd_m68k_cycle_mult >> 16);
285
08769494 286 elprintf(EL_CD, "s68k sync to %u, %u->%u",
287 m68k_target, now, s68k_target);
ae214f1c 288
4fb43555 289 if (Pico_mcd->m.busreq != 1) { /* busreq/reset */
ae214f1c 290 SekCycleCntS68k = SekCycleAimS68k = s68k_target;
291 pcd_run_events(m68k_target);
08769494 292 return 0;
ae214f1c 293 }
294
295 while (CYCLES_GT(s68k_target, now)) {
296 if (event_time_next && CYCLES_GE(now, event_time_next))
297 pcd_run_events(now);
298
299 target = s68k_target;
300 if (event_time_next && CYCLES_GT(target, event_time_next))
301 target = event_time_next;
302
303 SekRunS68k(target);
08769494 304 if (m68k_poll_sync && Pico_mcd->m.m68k_poll_cnt == 0)
305 break;
ae214f1c 306 }
08769494 307
308 return s68k_target - now;
ae214f1c 309 #undef now
c987bb5c 310}
ae214f1c 311
ba6e8bfd 312#define pcd_run_cpus_normal pcd_run_cpus
313//#define pcd_run_cpus_lockstep pcd_run_cpus
314
08769494 315static void SekSyncM68k(void);
316
fa8fb754 317void pcd_run_cpus_normal(int m68k_cycles)
08769494 318{
319 SekCycleAim += m68k_cycles;
30e8aac4 320 if (SekShouldInterrupt() || Pico_mcd->m.m68k_poll_cnt < 12)
cc5ffc3c 321 Pico_mcd->m.m68k_poll_cnt = 0;
322 else if (Pico_mcd->m.m68k_poll_cnt >= 16) {
08769494 323 int s68k_left = pcd_sync_s68k(SekCycleAim, 1);
324 if (s68k_left <= 0) {
ba6e8bfd 325 elprintf(EL_CDPOLL, "m68k poll [%02x] x%d @%06x",
08769494 326 Pico_mcd->m.m68k_poll_a, Pico_mcd->m.m68k_poll_cnt, SekPc);
327 SekCycleCnt = SekCycleAim;
328 return;
329 }
330 SekCycleCnt = SekCycleAim - (s68k_left * 40220 >> 16);
331 }
332
6901d0e4 333 while (CYCLES_GT(SekCycleAim, SekCycleCnt)) {
334 SekRunM68kOnce();
335 if (Pico_mcd->m.need_sync) {
336 Pico_mcd->m.need_sync = 0;
337 pcd_sync_s68k(SekCycleCnt, 0);
338 }
339 }
08769494 340}
341
fa8fb754 342void pcd_run_cpus_lockstep(int m68k_cycles)
ba6e8bfd 343{
344 unsigned int target = SekCycleAim + m68k_cycles;
345 do {
346 SekCycleAim += 8;
347 SekSyncM68k();
348 pcd_sync_s68k(SekCycleAim, 0);
349 } while (CYCLES_GT(target, SekCycleAim));
cc5ffc3c 350
351 SekCycleAim = target;
ba6e8bfd 352}
353
ae214f1c 354#define PICO_CD
355#define CPUS_RUN(m68k_cycles) \
08769494 356 pcd_run_cpus(m68k_cycles)
ae214f1c 357
efcba75f 358#include "../pico_cmn.c"
cc68a136 359
360
a6523294 361void pcd_prepare_frame(void)
362{
363 pcd_set_cycle_mult();
364
365 // need this because we can't have direct mapping between
366 // master<->slave cycle counters because of overflows
367 mcd_m68k_cycle_base = SekCycleAim;
368 mcd_s68k_cycle_base = SekCycleAimS68k;
369}
370
2aa27095 371PICO_INTERNAL void PicoFrameMCD(void)
cc68a136 372{
a6523294 373 PicoFrameStart();
cc68a136 374
a6523294 375 pcd_prepare_frame();
bf5fbbb4 376 PicoFrameHints();
cc68a136 377}
378
ae214f1c 379void pcd_state_loaded(void)
380{
381 unsigned int cycles;
382 int diff;
383
8e4e84c2 384 pcd_set_cycle_mult();
ae214f1c 385 pcd_state_loaded_mem();
386
33be04ca 387 memset(Pico_mcd->pcm_mixbuf, 0, sizeof(Pico_mcd->pcm_mixbuf));
388 Pico_mcd->pcm_mixbuf_dirty = 0;
389 Pico_mcd->pcm_mixpos = 0;
021e47b3 390 Pico_mcd->pcm_regs_dirty = 1;
33be04ca 391
ae214f1c 392 // old savestates..
393 cycles = pcd_cycles_m68k_to_s68k(SekCycleAim);
394 diff = cycles - SekCycleAimS68k;
395 if (diff < -1000 || diff > 1000) {
396 SekCycleCntS68k = SekCycleAimS68k = cycles;
397 }
398 if (pcd_event_times[PCD_EVENT_CDC] == 0) {
399 pcd_event_schedule(SekCycleAimS68k, PCD_EVENT_CDC, 12500000/75);
400
401 if (Pico_mcd->s68k_regs[0x31])
402 pcd_event_schedule(SekCycleAimS68k, PCD_EVENT_TIMER3,
403 Pico_mcd->s68k_regs[0x31] * 384);
ae214f1c 404 }
334d9fb6 405
406 diff = cycles - Pico_mcd->pcm.update_cycles;
407 if ((unsigned int)diff > 12500000/50)
33be04ca 408 Pico_mcd->pcm.update_cycles = cycles;
8e4e84c2 409
410 // reschedule
411 event_time_next = 0;
412 pcd_run_events(SekCycleCntS68k);
ae214f1c 413}
cc68a136 414
ae214f1c 415// vim:shiftwidth=2:ts=2:expandtab