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[picodrive.git] / Pico / PicoInt.h
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eff55556 1// Pico Library - Internal Header File\r
cc68a136 2\r
3// (c) Copyright 2004 Dave, All rights reserved.\r
6cadc2da 4// (c) Copyright 2006,2007 Grazvydas "notaz" Ignotas, all rights reserved.\r
cc68a136 5// Free for non-commercial use.\r
6\r
7// For commercial use, separate licencing terms must be obtained.\r
8\r
eff55556 9#ifndef PICO_INTERNAL_INCLUDED\r
10#define PICO_INTERNAL_INCLUDED\r
cc68a136 11\r
12#include <stdio.h>\r
13#include <stdlib.h>\r
14#include <string.h>\r
15#include "Pico.h"\r
16\r
89fa852d 17//\r
18#define USE_POLL_DETECT\r
19\r
eff55556 20#ifndef PICO_INTERNAL\r
21#define PICO_INTERNAL\r
22#endif\r
23#ifndef PICO_INTERNAL_ASM\r
24#define PICO_INTERNAL_ASM\r
25#endif\r
cc68a136 26\r
70357ce5 27// to select core, define EMU_C68K, EMU_M68K or EMU_F68K in your makefile or project\r
cc68a136 28\r
29#ifdef __cplusplus\r
30extern "C" {\r
31#endif\r
32\r
33\r
34// ----------------------- 68000 CPU -----------------------\r
35#ifdef EMU_C68K\r
36#include "../cpu/Cyclone/Cyclone.h"\r
3aa1e148 37extern struct Cyclone PicoCpuCM68k, PicoCpuCS68k;\r
38#define SekCyclesLeftNoMCD PicoCpuCM68k.cycles // cycles left for this run\r
7336a99a 39#define SekCyclesLeft \\r
40 (((PicoMCD&1) && (PicoOpt & 0x2000)) ? (SekCycleAim-SekCycleCnt) : SekCyclesLeftNoMCD)\r
7a1f6e45 41#define SekCyclesLeftS68k \\r
3aa1e148 42 ((PicoOpt & 0x2000) ? (SekCycleAimS68k-SekCycleCntS68k) : PicoCpuCS68k.cycles)\r
43#define SekSetCyclesLeftNoMCD(c) PicoCpuCM68k.cycles=c\r
7336a99a 44#define SekSetCyclesLeft(c) { \\r
45 if ((PicoMCD&1) && (PicoOpt & 0x2000)) SekCycleCnt=SekCycleAim-(c); else SekSetCyclesLeftNoMCD(c); \\r
46}\r
3aa1e148 47#define SekPc (PicoCpuCM68k.pc-PicoCpuCM68k.membase)\r
48#define SekPcS68k (PicoCpuCS68k.pc-PicoCpuCS68k.membase)\r
49#define SekSetStop(x) { PicoCpuCM68k.state_flags&=~1; if (x) { PicoCpuCM68k.state_flags|=1; PicoCpuCM68k.cycles=0; } }\r
50#define SekSetStopS68k(x) { PicoCpuCS68k.state_flags&=~1; if (x) { PicoCpuCS68k.state_flags|=1; PicoCpuCS68k.cycles=0; } }\r
03e4f2a3 51#define SekShouldInterrupt (PicoCpuCM68k.irq > (PicoCpuCM68k.srh&7))\r
b542be46 52\r
53#define SekInterrupt(i) PicoCpuCM68k.irq=i\r
54\r
03e4f2a3 55#ifdef EMU_M68K\r
56#define EMU_CORE_DEBUG\r
57#endif\r
cc68a136 58#endif\r
59\r
70357ce5 60#ifdef EMU_F68K\r
61#include "../cpu/fame/fame.h"\r
b542be46 62extern M68K_CONTEXT PicoCpuFM68k, PicoCpuFS68k;\r
3aa1e148 63#define SekCyclesLeftNoMCD PicoCpuFM68k.io_cycle_counter\r
70357ce5 64#define SekCyclesLeft \\r
65 (((PicoMCD&1) && (PicoOpt & 0x2000)) ? (SekCycleAim-SekCycleCnt) : SekCyclesLeftNoMCD)\r
66#define SekCyclesLeftS68k \\r
3aa1e148 67 ((PicoOpt & 0x2000) ? (SekCycleAimS68k-SekCycleCntS68k) : PicoCpuFS68k.io_cycle_counter)\r
68#define SekSetCyclesLeftNoMCD(c) PicoCpuFM68k.io_cycle_counter=c\r
70357ce5 69#define SekSetCyclesLeft(c) { \\r
70 if ((PicoMCD&1) && (PicoOpt & 0x2000)) SekCycleCnt=SekCycleAim-(c); else SekSetCyclesLeftNoMCD(c); \\r
71}\r
03e4f2a3 72#define SekPc fm68k_get_pc(&PicoCpuFM68k)\r
73#define SekPcS68k fm68k_get_pc(&PicoCpuFS68k)\r
70357ce5 74#define SekSetStop(x) { \\r
03e4f2a3 75 PicoCpuFM68k.execinfo &= ~FM68K_HALTED; \\r
76 if (x) { PicoCpuFM68k.execinfo |= FM68K_HALTED; PicoCpuFM68k.io_cycle_counter = 0; } \\r
70357ce5 77}\r
78#define SekSetStopS68k(x) { \\r
03e4f2a3 79 PicoCpuFS68k.execinfo &= ~FM68K_HALTED; \\r
80 if (x) { PicoCpuFS68k.execinfo |= FM68K_HALTED; PicoCpuFS68k.io_cycle_counter = 0; } \\r
70357ce5 81}\r
03e4f2a3 82#define SekShouldInterrupt fm68k_would_interrupt()\r
b542be46 83\r
84#define SekInterrupt(irq) PicoCpuFM68k.interrupts[0]=irq\r
85\r
03e4f2a3 86#ifdef EMU_M68K\r
87#define EMU_CORE_DEBUG\r
88#endif\r
cc68a136 89#endif\r
90\r
91#ifdef EMU_M68K\r
92#include "../cpu/musashi/m68kcpu.h"\r
3aa1e148 93extern m68ki_cpu_core PicoCpuMM68k, PicoCpuMS68k;\r
cc68a136 94#ifndef SekCyclesLeft\r
3aa1e148 95#define SekCyclesLeftNoMCD PicoCpuMM68k.cyc_remaining_cycles\r
7336a99a 96#define SekCyclesLeft \\r
97 (((PicoMCD&1) && (PicoOpt & 0x2000)) ? (SekCycleAim-SekCycleCnt) : SekCyclesLeftNoMCD)\r
7a1f6e45 98#define SekCyclesLeftS68k \\r
3aa1e148 99 ((PicoOpt & 0x2000) ? (SekCycleAimS68k-SekCycleCntS68k) : PicoCpuMS68k.cyc_remaining_cycles)\r
7336a99a 100#define SekSetCyclesLeftNoMCD(c) SET_CYCLES(c)\r
101#define SekSetCyclesLeft(c) { \\r
102 if ((PicoMCD&1) && (PicoOpt & 0x2000)) SekCycleCnt=SekCycleAim-(c); else SET_CYCLES(c); \\r
103}\r
3aa1e148 104#define SekPc m68k_get_reg(&PicoCpuMM68k, M68K_REG_PC)\r
105#define SekPcS68k m68k_get_reg(&PicoCpuMS68k, M68K_REG_PC)\r
7a1f6e45 106#define SekSetStop(x) { \\r
3aa1e148 107 if(x) { SET_CYCLES(0); PicoCpuMM68k.stopped=STOP_LEVEL_STOP; } \\r
108 else PicoCpuMM68k.stopped=0; \\r
7a1f6e45 109}\r
110#define SekSetStopS68k(x) { \\r
3aa1e148 111 if(x) { SET_CYCLES(0); PicoCpuMS68k.stopped=STOP_LEVEL_STOP; } \\r
112 else PicoCpuMS68k.stopped=0; \\r
7a1f6e45 113}\r
03e4f2a3 114#define SekShouldInterrupt (CPU_INT_LEVEL > FLAG_INT_MASK)\r
b542be46 115\r
71de3cd9 116#define SekInterrupt(irq) { \\r
b542be46 117 void *oldcontext = m68ki_cpu_p; \\r
118 m68k_set_context(&PicoCpuMM68k); \\r
119 m68k_set_irq(irq); \\r
120 m68k_set_context(oldcontext); \\r
121}\r
122\r
cc68a136 123#endif\r
124#endif\r
125\r
126extern int SekCycleCnt; // cycles done in this frame\r
127extern int SekCycleAim; // cycle aim\r
128extern unsigned int SekCycleCntT; // total cycle counter, updated once per frame\r
129\r
b8cbd802 130#define SekCyclesReset() { \\r
131 SekCycleCntT+=SekCycleAim; \\r
132 SekCycleCnt-=SekCycleAim; \\r
133 SekCycleAim=0; \\r
134}\r
cc68a136 135#define SekCyclesBurn(c) SekCycleCnt+=c\r
136#define SekCyclesDone() (SekCycleAim-SekCyclesLeft) // nuber of cycles done in this frame (can be checked anywhere)\r
137#define SekCyclesDoneT() (SekCycleCntT+SekCyclesDone()) // total nuber of cycles done for this rom\r
138\r
139#define SekEndRun(after) { \\r
140 SekCycleCnt -= SekCyclesLeft - after; \\r
141 if(SekCycleCnt < 0) SekCycleCnt = 0; \\r
142 SekSetCyclesLeft(after); \\r
143}\r
144\r
145extern int SekCycleCntS68k;\r
146extern int SekCycleAimS68k;\r
147\r
bf5fbbb4 148#define SekCyclesResetS68k() { \\r
149 SekCycleCntS68k-=SekCycleAimS68k; \\r
150 SekCycleAimS68k=0; \\r
151}\r
7a1f6e45 152#define SekCyclesDoneS68k() (SekCycleAimS68k-SekCyclesLeftS68k)\r
cc68a136 153\r
03e4f2a3 154#ifdef EMU_CORE_DEBUG\r
2d0b15bb 155#undef SekSetCyclesLeftNoMCD\r
156#undef SekSetCyclesLeft\r
157#undef SekCyclesBurn\r
158#undef SekEndRun\r
159#define SekSetCyclesLeftNoMCD(c)\r
160#define SekSetCyclesLeft(c)\r
2270612a 161#define SekCyclesBurn(c) c\r
2d0b15bb 162#define SekEndRun(c)\r
163#endif\r
cc68a136 164\r
b542be46 165// ----------------------- Z80 CPU -----------------------\r
166\r
167#if defined(_USE_MZ80)\r
168#include "../../cpu/mz80/mz80.h"\r
169\r
170#define z80_run(cycles) mz80_run(cycles)\r
171#define z80_run_nr(cycles) mz80_run(cycles)\r
172#define z80_int() mz80int(0)\r
173#define z80_resetCycles() mz80GetElapsedTicks(1)\r
174\r
175#elif defined(_USE_DRZ80)\r
176#include "../../cpu/DrZ80/drz80.h"\r
177\r
178extern struct DrZ80 drZ80;\r
179\r
180#define z80_run(cycles) ((cycles) - DrZ80Run(&drZ80, cycles))\r
181#define z80_run_nr(cycles) DrZ80Run(&drZ80, cycles)\r
182#define z80_int() { \\r
183 drZ80.z80irqvector = 0xFF; /* default IRQ vector RST opcode */ \\r
184 drZ80.Z80_IRQ = 1; \\r
185}\r
186#define z80_resetCycles()\r
187\r
188#elif defined(_USE_CZ80)\r
189#include "../../cpu/cz80/cz80.h"\r
190\r
191#define z80_run(cycles) Cz80_Exec(&CZ80, cycles)\r
192#define z80_run_nr(cycles) Cz80_Exec(&CZ80, cycles)\r
193#define z80_int() Cz80_Set_IRQ(&CZ80, 0, HOLD_LINE)\r
194#define z80_resetCycles()\r
195\r
196#else\r
197\r
198#define z80_run(cycles) (cycles)\r
199#define z80_run_nr(cycles)\r
200#define z80_int()\r
201#define z80_resetCycles()\r
202\r
203#endif\r
204\r
cc68a136 205// ---------------------------------------------------------\r
206\r
70357ce5 207extern int PicoMCD;\r
208\r
cc68a136 209// main oscillator clock which controls timing\r
210#define OSC_NTSC 53693100\r
b8cbd802 211// seems to be accurate, see scans from http://www.hot.ee/tmeeco/\r
212#define OSC_PAL 53203424\r
cc68a136 213\r
214struct PicoVideo\r
215{\r
216 unsigned char reg[0x20];\r
b8cbd802 217 unsigned int command; // 32-bit Command\r
218 unsigned char pending; // 1 if waiting for second half of 32-bit command\r
219 unsigned char type; // Command type (v/c/vsram read/write)\r
220 unsigned short addr; // Read/Write address\r
221 int status; // Status bits\r
cc68a136 222 unsigned char pending_ints; // pending interrupts: ??VH????\r
b8cbd802 223 signed char lwrite_cnt; // VDP write count during active display line\r
224 unsigned char pad[0x12];\r
cc68a136 225};\r
226\r
227struct PicoMisc\r
228{\r
229 unsigned char rotate;\r
230 unsigned char z80Run;\r
e5503e2f 231 unsigned char padTHPhase[2]; // 02 phase of gamepad TH switches\r
232 short scanline; // 04 0 to 261||311; -1 in fast mode\r
233 char dirtyPal; // 06 Is the palette dirty (1 - change @ this frame, 2 - some time before)\r
234 unsigned char hardware; // 07 Hardware value for country\r
235 unsigned char pal; // 08 1=PAL 0=NTSC\r
236 unsigned char sram_reg; // SRAM mode register. bit0: allow read? bit1: deny write? bit2: EEPROM? bit4: detected? (header or by access)\r
237 unsigned short z80_bank68k; // 0a\r
cc68a136 238 unsigned short z80_lastaddr; // this is for Z80 faking\r
239 unsigned char z80_fakeval;\r
240 unsigned char pad0;\r
e5503e2f 241 unsigned char padDelay[2]; // 10 gamepad phase time outs, so we count a delay\r
1dceadae 242 unsigned short eeprom_addr; // EEPROM address register\r
243 unsigned char eeprom_cycle; // EEPROM SRAM cycle number\r
244 unsigned char eeprom_slave; // EEPROM slave word for X24C02 and better SRAMs\r
721cd396 245 unsigned char prot_bytes[2]; // simple protection faking\r
b8cbd802 246 unsigned short dma_xfers;\r
312e9ce1 247 unsigned char pad[2];\r
248 unsigned int frame_count; // mainly for movies\r
cc68a136 249};\r
250\r
251// some assembly stuff depend on these, do not touch!\r
252struct Pico\r
253{\r
254 unsigned char ram[0x10000]; // 0x00000 scratch ram\r
255 unsigned short vram[0x8000]; // 0x10000\r
256 unsigned char zram[0x2000]; // 0x20000 Z80 ram\r
257 unsigned char ioports[0x10];\r
258 unsigned int pad[0x3c]; // unused\r
259 unsigned short cram[0x40]; // 0x22100\r
260 unsigned short vsram[0x40]; // 0x22180\r
261\r
262 unsigned char *rom; // 0x22200\r
263 unsigned int romsize; // 0x22204\r
264\r
265 struct PicoMisc m;\r
266 struct PicoVideo video;\r
267};\r
268\r
269// sram\r
270struct PicoSRAM\r
271{\r
4ff2d527 272 unsigned char *data; // actual data\r
273 unsigned int start; // start address in 68k address space\r
cc68a136 274 unsigned int end;\r
1dceadae 275 unsigned char unused1; // 0c: unused\r
276 unsigned char unused2;\r
cc68a136 277 unsigned char changed;\r
1dceadae 278 unsigned char eeprom_type; // eeprom type: 0: 7bit (24C01), 2: device with 2 addr words (X24C02+), 3: dev with 3 addr words\r
279 unsigned char eeprom_abits; // eeprom access must be odd addr for: bit0 ~ cl, bit1 ~ out\r
280 unsigned char eeprom_bit_cl; // bit number for cl\r
281 unsigned char eeprom_bit_in; // bit number for in\r
282 unsigned char eeprom_bit_out; // bit number for out\r
cc68a136 283};\r
284\r
285// MCD\r
286#include "cd/cd_sys.h"\r
287#include "cd/LC89510.h"\r
d1df8786 288#include "cd/gfx_cd.h"\r
cc68a136 289\r
4f265db7 290struct mcd_pcm\r
291{\r
292 unsigned char control; // reg7\r
293 unsigned char enabled; // reg8\r
294 unsigned char cur_ch;\r
295 unsigned char bank;\r
296 int pad1;\r
297\r
4ff2d527 298 struct pcm_chan // 08, size 0x10\r
4f265db7 299 {\r
300 unsigned char regs[8];\r
4ff2d527 301 unsigned int addr; // .08: played sample address\r
4f265db7 302 int pad;\r
303 } ch[8];\r
304};\r
305\r
c459aefd 306struct mcd_misc\r
307{\r
308 unsigned short hint_vector;\r
309 unsigned char busreq;\r
51a902ae 310 unsigned char s68k_pend_ints;\r
89fa852d 311 unsigned int state_flags; // 04: emu state: reset_pending, dmna_pending\r
51a902ae 312 unsigned int counter75hz;\r
4ff2d527 313 unsigned short audio_offset; // 0c: for savestates: play pointer offset (0-1023)\r
75736070 314 unsigned char audio_track; // playing audio track # (zero based)\r
6cadc2da 315 char pad1;\r
4ff2d527 316 int timer_int3; // 10\r
4f265db7 317 unsigned int timer_stopwatch;\r
6cadc2da 318 unsigned char bcram_reg; // 18: battery-backed RAM cart register\r
319 unsigned char pad2;\r
320 unsigned short pad3;\r
321 int pad[9];\r
c459aefd 322};\r
323\r
cc68a136 324typedef struct\r
325{\r
4ff2d527 326 unsigned char bios[0x20000]; // 000000: 128K\r
327 union { // 020000: 512K\r
fa1e5e29 328 unsigned char prg_ram[0x80000];\r
cc68a136 329 unsigned char prg_ram_b[4][0x20000];\r
330 };\r
4ff2d527 331 union { // 0a0000: 256K\r
fa1e5e29 332 struct {\r
333 unsigned char word_ram2M[0x40000];\r
334 unsigned char unused[0x20000];\r
335 };\r
336 struct {\r
337 unsigned char unused[0x20000];\r
338 unsigned char word_ram1M[2][0x20000];\r
339 };\r
340 };\r
4ff2d527 341 union { // 100000: 64K\r
fa1e5e29 342 unsigned char pcm_ram[0x10000];\r
4f265db7 343 unsigned char pcm_ram_b[0x10][0x1000];\r
344 };\r
4ff2d527 345 unsigned char s68k_regs[0x200]; // 110000: GA, not CPU regs\r
346 unsigned char bram[0x2000]; // 110200: 8K\r
347 struct mcd_misc m; // 112200: misc\r
348 struct mcd_pcm pcm; // 112240:\r
75736070 349 _scd_toc TOC; // not to be saved\r
cc68a136 350 CDD cdd;\r
351 CDC cdc;\r
352 _scd scd;\r
d1df8786 353 Rot_Comp rot_comp;\r
cc68a136 354} mcd_state;\r
355\r
356#define Pico_mcd ((mcd_state *)Pico.rom)\r
357\r
51a902ae 358// Area.c\r
eff55556 359PICO_INTERNAL int PicoAreaPackCpu(unsigned char *cpu, int is_sub);\r
360PICO_INTERNAL int PicoAreaUnpackCpu(unsigned char *cpu, int is_sub);\r
51a902ae 361\r
362// cd/Area.c\r
eff55556 363PICO_INTERNAL int PicoCdSaveState(void *file);\r
364PICO_INTERNAL int PicoCdLoadState(void *file);\r
cc68a136 365\r
1dceadae 366// Cart.c\r
367PICO_INTERNAL void PicoCartDetect(void);\r
368\r
03e4f2a3 369// Debug.c\r
b5e5172d 370int CM_compareRun(int cyc, int is_sub);\r
03e4f2a3 371\r
cc68a136 372// Draw.c\r
eff55556 373PICO_INTERNAL int PicoLine(int scan);\r
374PICO_INTERNAL void PicoFrameStart(void);\r
cc68a136 375\r
376// Draw2.c\r
eff55556 377PICO_INTERNAL void PicoFrameFull();\r
cc68a136 378\r
379// Memory.c\r
eff55556 380PICO_INTERNAL int PicoInitPc(unsigned int pc);\r
8ab3e3c1 381PICO_INTERNAL_ASM unsigned int PicoRead32(unsigned int a);\r
eff55556 382PICO_INTERNAL void PicoMemSetup(void);\r
383PICO_INTERNAL_ASM void PicoMemReset(void);\r
e5503e2f 384PICO_INTERNAL int PadRead(int i);\r
eff55556 385PICO_INTERNAL unsigned char z80_read(unsigned short a);\r
a4221917 386#ifndef _USE_CZ80\r
eff55556 387PICO_INTERNAL_ASM void z80_write(unsigned char data, unsigned short a);\r
388PICO_INTERNAL void z80_write16(unsigned short data, unsigned short a);\r
a4221917 389PICO_INTERNAL unsigned short z80_read16(unsigned short a);\r
390#else\r
391PICO_INTERNAL_ASM void z80_write(unsigned int a, unsigned char data);\r
392#endif\r
cc68a136 393\r
394// cd/Memory.c\r
eff55556 395PICO_INTERNAL void PicoMemSetupCD(void);\r
396PICO_INTERNAL_ASM void PicoMemResetCD(int r3);\r
397PICO_INTERNAL_ASM void PicoMemResetCDdecode(int r3);\r
cc68a136 398\r
399// Pico.c\r
400extern struct Pico Pico;\r
401extern struct PicoSRAM SRam;\r
402extern int emustatus;\r
d9153729 403extern int z80startCycle, z80stopCycle; // in 68k cycles\r
eff55556 404PICO_INTERNAL int CheckDMA(void);\r
cc68a136 405\r
406// cd/Pico.c\r
e5f426aa 407PICO_INTERNAL int PicoInitMCD(void);\r
408PICO_INTERNAL void PicoExitMCD(void);\r
eff55556 409PICO_INTERNAL int PicoResetMCD(int hard);\r
410PICO_INTERNAL int PicoFrameMCD(void);\r
cc68a136 411\r
412// Sek.c\r
eff55556 413PICO_INTERNAL int SekInit(void);\r
414PICO_INTERNAL int SekReset(void);\r
3aa1e148 415PICO_INTERNAL void SekState(int *data);\r
eff55556 416PICO_INTERNAL void SekSetRealTAS(int use_real);\r
cc68a136 417\r
418// cd/Sek.c\r
eff55556 419PICO_INTERNAL int SekInitS68k(void);\r
420PICO_INTERNAL int SekResetS68k(void);\r
421PICO_INTERNAL int SekInterruptS68k(int irq);\r
cc68a136 422\r
7a93adeb 423// sound/sound.c\r
424extern int PsndLen_exc_cnt;\r
425extern int PsndLen_exc_add;\r
426\r
cc68a136 427// VideoPort.c\r
eff55556 428PICO_INTERNAL_ASM void PicoVideoWrite(unsigned int a,unsigned short d);\r
429PICO_INTERNAL_ASM unsigned int PicoVideoRead(unsigned int a);\r
cc68a136 430\r
431// Misc.c\r
eff55556 432PICO_INTERNAL void SRAMWriteEEPROM(unsigned int d);\r
433PICO_INTERNAL void SRAMUpdPending(unsigned int a, unsigned int d);\r
434PICO_INTERNAL_ASM unsigned int SRAMReadEEPROM(void);\r
435PICO_INTERNAL_ASM void memcpy16(unsigned short *dest, unsigned short *src, int count);\r
436PICO_INTERNAL_ASM void memcpy16bswap(unsigned short *dest, void *src, int count);\r
437PICO_INTERNAL_ASM void memcpy32(int *dest, int *src, int count); // 32bit word count\r
438PICO_INTERNAL_ASM void memset32(int *dest, int c, int count);\r
cc68a136 439\r
fa1e5e29 440// cd/Misc.c\r
eff55556 441PICO_INTERNAL_ASM void wram_2M_to_1M(unsigned char *m);\r
442PICO_INTERNAL_ASM void wram_1M_to_2M(unsigned char *m);\r
443\r
444// cd/buffering.c\r
445PICO_INTERNAL void PicoCDBufferRead(void *dest, int lba);\r
446\r
447// sound/sound.c\r
9d917eea 448PICO_INTERNAL void PsndReset(void);\r
449PICO_INTERNAL void Psnd_timers_and_dac(int raster);\r
450PICO_INTERNAL int PsndRender(int offset, int length);\r
451PICO_INTERNAL void PsndClear(void);\r
eff55556 452// z80 functionality wrappers\r
453PICO_INTERNAL void z80_init(void);\r
eff55556 454PICO_INTERNAL void z80_pack(unsigned char *data);\r
455PICO_INTERNAL void z80_unpack(unsigned char *data);\r
456PICO_INTERNAL void z80_reset(void);\r
457PICO_INTERNAL void z80_exit(void);\r
fa1e5e29 458\r
cc68a136 459\r
460#ifdef __cplusplus\r
461} // End of extern "C"\r
462#endif\r
eff55556 463\r
b8cbd802 464// emulation event logging\r
465#ifndef EL_LOGMASK\r
466#define EL_LOGMASK 0\r
467#endif\r
468\r
469#define EL_HVCNT 0x0001 /* hv counter reads */\r
470#define EL_SR 0x0002 /* SR reads */\r
471#define EL_INTS 0x0004 /* ints and acks */\r
472#define EL_YM2612R 0x0008 /* 68k ym2612 reads */\r
473#define EL_INTSW 0x0010 /* log irq switching on/off */\r
474#define EL_ASVDP 0x0020 /* VDP accesses during active scan */\r
475#define EL_VDPDMA 0x0040 /* VDP DMA transfers and their timing */\r
5f20bb80 476#define EL_BUSREQ 0x0080 /* z80 busreq r/w or reset w */\r
b8cbd802 477#define EL_Z80BNK 0x0100 /* z80 i/o through bank area */\r
1dceadae 478#define EL_SRAMIO 0x0200 /* sram i/o */\r
479#define EL_EEPROM 0x0400 /* eeprom debug */\r
480#define EL_UIO 0x0800 /* unmapped i/o */\r
5f20bb80 481#define EL_IO 0x1000 /* all i/o (TODO) */\r
b8cbd802 482\r
483#define EL_STATUS 0x4000 /* status messages */\r
71de3cd9 484#define EL_ANOMALY 0x8000 /* some unexpected conditions (during emulation) */\r
b8cbd802 485\r
486#if EL_LOGMASK\r
487#define elprintf(w,f,...) \\r
488{ \\r
489 if ((w) & EL_LOGMASK) \\r
490 printf("%05i:%03i: " f "\n",Pico.m.frame_count,Pico.m.scanline,##__VA_ARGS__); \\r
491}\r
492#else\r
493#define elprintf(w,f,...)\r
494#endif\r
495\r
eff55556 496#endif // PICO_INTERNAL_INCLUDED\r
497\r
fast MegaDrive/MegaCD/32X emulator