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[picodrive.git] / Pico / PicoInt.h
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eff55556 1// Pico Library - Internal Header File\r
cc68a136 2\r
3// (c) Copyright 2004 Dave, All rights reserved.\r
6cadc2da 4// (c) Copyright 2006,2007 Grazvydas "notaz" Ignotas, all rights reserved.\r
cc68a136 5// Free for non-commercial use.\r
6\r
7// For commercial use, separate licencing terms must be obtained.\r
8\r
eff55556 9#ifndef PICO_INTERNAL_INCLUDED\r
10#define PICO_INTERNAL_INCLUDED\r
cc68a136 11\r
12#include <stdio.h>\r
13#include <stdlib.h>\r
14#include <string.h>\r
15#include "Pico.h"\r
16\r
89fa852d 17//\r
18#define USE_POLL_DETECT\r
19\r
eff55556 20#ifndef PICO_INTERNAL\r
21#define PICO_INTERNAL\r
22#endif\r
23#ifndef PICO_INTERNAL_ASM\r
24#define PICO_INTERNAL_ASM\r
25#endif\r
cc68a136 26\r
70357ce5 27// to select core, define EMU_C68K, EMU_M68K or EMU_F68K in your makefile or project\r
cc68a136 28\r
29#ifdef __cplusplus\r
30extern "C" {\r
31#endif\r
32\r
33\r
34// ----------------------- 68000 CPU -----------------------\r
35#ifdef EMU_C68K\r
36#include "../cpu/Cyclone/Cyclone.h"\r
3aa1e148 37extern struct Cyclone PicoCpuCM68k, PicoCpuCS68k;\r
38#define SekCyclesLeftNoMCD PicoCpuCM68k.cycles // cycles left for this run\r
7336a99a 39#define SekCyclesLeft \\r
40 (((PicoMCD&1) && (PicoOpt & 0x2000)) ? (SekCycleAim-SekCycleCnt) : SekCyclesLeftNoMCD)\r
7a1f6e45 41#define SekCyclesLeftS68k \\r
3aa1e148 42 ((PicoOpt & 0x2000) ? (SekCycleAimS68k-SekCycleCntS68k) : PicoCpuCS68k.cycles)\r
43#define SekSetCyclesLeftNoMCD(c) PicoCpuCM68k.cycles=c\r
7336a99a 44#define SekSetCyclesLeft(c) { \\r
45 if ((PicoMCD&1) && (PicoOpt & 0x2000)) SekCycleCnt=SekCycleAim-(c); else SekSetCyclesLeftNoMCD(c); \\r
46}\r
3aa1e148 47#define SekPc (PicoCpuCM68k.pc-PicoCpuCM68k.membase)\r
48#define SekPcS68k (PicoCpuCS68k.pc-PicoCpuCS68k.membase)\r
49#define SekSetStop(x) { PicoCpuCM68k.state_flags&=~1; if (x) { PicoCpuCM68k.state_flags|=1; PicoCpuCM68k.cycles=0; } }\r
50#define SekSetStopS68k(x) { PicoCpuCS68k.state_flags&=~1; if (x) { PicoCpuCS68k.state_flags|=1; PicoCpuCS68k.cycles=0; } }\r
ca61ee42 51#define SekIsStoppedS68k() (PicoCpuCS68k.state_flags&1)\r
03e4f2a3 52#define SekShouldInterrupt (PicoCpuCM68k.irq > (PicoCpuCM68k.srh&7))\r
b542be46 53\r
54#define SekInterrupt(i) PicoCpuCM68k.irq=i\r
55\r
03e4f2a3 56#ifdef EMU_M68K\r
57#define EMU_CORE_DEBUG\r
58#endif\r
cc68a136 59#endif\r
60\r
70357ce5 61#ifdef EMU_F68K\r
62#include "../cpu/fame/fame.h"\r
b542be46 63extern M68K_CONTEXT PicoCpuFM68k, PicoCpuFS68k;\r
3aa1e148 64#define SekCyclesLeftNoMCD PicoCpuFM68k.io_cycle_counter\r
70357ce5 65#define SekCyclesLeft \\r
66 (((PicoMCD&1) && (PicoOpt & 0x2000)) ? (SekCycleAim-SekCycleCnt) : SekCyclesLeftNoMCD)\r
67#define SekCyclesLeftS68k \\r
3aa1e148 68 ((PicoOpt & 0x2000) ? (SekCycleAimS68k-SekCycleCntS68k) : PicoCpuFS68k.io_cycle_counter)\r
69#define SekSetCyclesLeftNoMCD(c) PicoCpuFM68k.io_cycle_counter=c\r
70357ce5 70#define SekSetCyclesLeft(c) { \\r
71 if ((PicoMCD&1) && (PicoOpt & 0x2000)) SekCycleCnt=SekCycleAim-(c); else SekSetCyclesLeftNoMCD(c); \\r
72}\r
03e4f2a3 73#define SekPc fm68k_get_pc(&PicoCpuFM68k)\r
74#define SekPcS68k fm68k_get_pc(&PicoCpuFS68k)\r
70357ce5 75#define SekSetStop(x) { \\r
03e4f2a3 76 PicoCpuFM68k.execinfo &= ~FM68K_HALTED; \\r
77 if (x) { PicoCpuFM68k.execinfo |= FM68K_HALTED; PicoCpuFM68k.io_cycle_counter = 0; } \\r
70357ce5 78}\r
79#define SekSetStopS68k(x) { \\r
03e4f2a3 80 PicoCpuFS68k.execinfo &= ~FM68K_HALTED; \\r
81 if (x) { PicoCpuFS68k.execinfo |= FM68K_HALTED; PicoCpuFS68k.io_cycle_counter = 0; } \\r
70357ce5 82}\r
ca61ee42 83#define SekIsStoppedS68k() (PicoCpuFS68k.execinfo&FM68K_HALTED)\r
03e4f2a3 84#define SekShouldInterrupt fm68k_would_interrupt()\r
b542be46 85\r
86#define SekInterrupt(irq) PicoCpuFM68k.interrupts[0]=irq\r
87\r
03e4f2a3 88#ifdef EMU_M68K\r
89#define EMU_CORE_DEBUG\r
90#endif\r
cc68a136 91#endif\r
92\r
93#ifdef EMU_M68K\r
94#include "../cpu/musashi/m68kcpu.h"\r
3aa1e148 95extern m68ki_cpu_core PicoCpuMM68k, PicoCpuMS68k;\r
cc68a136 96#ifndef SekCyclesLeft\r
3aa1e148 97#define SekCyclesLeftNoMCD PicoCpuMM68k.cyc_remaining_cycles\r
7336a99a 98#define SekCyclesLeft \\r
99 (((PicoMCD&1) && (PicoOpt & 0x2000)) ? (SekCycleAim-SekCycleCnt) : SekCyclesLeftNoMCD)\r
7a1f6e45 100#define SekCyclesLeftS68k \\r
3aa1e148 101 ((PicoOpt & 0x2000) ? (SekCycleAimS68k-SekCycleCntS68k) : PicoCpuMS68k.cyc_remaining_cycles)\r
7336a99a 102#define SekSetCyclesLeftNoMCD(c) SET_CYCLES(c)\r
103#define SekSetCyclesLeft(c) { \\r
104 if ((PicoMCD&1) && (PicoOpt & 0x2000)) SekCycleCnt=SekCycleAim-(c); else SET_CYCLES(c); \\r
105}\r
3aa1e148 106#define SekPc m68k_get_reg(&PicoCpuMM68k, M68K_REG_PC)\r
107#define SekPcS68k m68k_get_reg(&PicoCpuMS68k, M68K_REG_PC)\r
7a1f6e45 108#define SekSetStop(x) { \\r
3aa1e148 109 if(x) { SET_CYCLES(0); PicoCpuMM68k.stopped=STOP_LEVEL_STOP; } \\r
110 else PicoCpuMM68k.stopped=0; \\r
7a1f6e45 111}\r
112#define SekSetStopS68k(x) { \\r
3aa1e148 113 if(x) { SET_CYCLES(0); PicoCpuMS68k.stopped=STOP_LEVEL_STOP; } \\r
114 else PicoCpuMS68k.stopped=0; \\r
7a1f6e45 115}\r
ca61ee42 116#define SekIsStoppedS68k() (PicoCpuMS68k.stopped==STOP_LEVEL_STOP)\r
03e4f2a3 117#define SekShouldInterrupt (CPU_INT_LEVEL > FLAG_INT_MASK)\r
b542be46 118\r
71de3cd9 119#define SekInterrupt(irq) { \\r
b542be46 120 void *oldcontext = m68ki_cpu_p; \\r
121 m68k_set_context(&PicoCpuMM68k); \\r
122 m68k_set_irq(irq); \\r
123 m68k_set_context(oldcontext); \\r
124}\r
125\r
cc68a136 126#endif\r
127#endif\r
128\r
129extern int SekCycleCnt; // cycles done in this frame\r
130extern int SekCycleAim; // cycle aim\r
131extern unsigned int SekCycleCntT; // total cycle counter, updated once per frame\r
132\r
b8cbd802 133#define SekCyclesReset() { \\r
134 SekCycleCntT+=SekCycleAim; \\r
135 SekCycleCnt-=SekCycleAim; \\r
136 SekCycleAim=0; \\r
137}\r
cc68a136 138#define SekCyclesBurn(c) SekCycleCnt+=c\r
139#define SekCyclesDone() (SekCycleAim-SekCyclesLeft) // nuber of cycles done in this frame (can be checked anywhere)\r
140#define SekCyclesDoneT() (SekCycleCntT+SekCyclesDone()) // total nuber of cycles done for this rom\r
141\r
142#define SekEndRun(after) { \\r
143 SekCycleCnt -= SekCyclesLeft - after; \\r
144 if(SekCycleCnt < 0) SekCycleCnt = 0; \\r
145 SekSetCyclesLeft(after); \\r
146}\r
147\r
148extern int SekCycleCntS68k;\r
149extern int SekCycleAimS68k;\r
150\r
bf5fbbb4 151#define SekCyclesResetS68k() { \\r
152 SekCycleCntS68k-=SekCycleAimS68k; \\r
153 SekCycleAimS68k=0; \\r
154}\r
7a1f6e45 155#define SekCyclesDoneS68k() (SekCycleAimS68k-SekCyclesLeftS68k)\r
cc68a136 156\r
03e4f2a3 157#ifdef EMU_CORE_DEBUG\r
2d0b15bb 158#undef SekSetCyclesLeftNoMCD\r
159#undef SekSetCyclesLeft\r
160#undef SekCyclesBurn\r
161#undef SekEndRun\r
162#define SekSetCyclesLeftNoMCD(c)\r
163#define SekSetCyclesLeft(c)\r
2270612a 164#define SekCyclesBurn(c) c\r
2d0b15bb 165#define SekEndRun(c)\r
166#endif\r
cc68a136 167\r
b542be46 168// ----------------------- Z80 CPU -----------------------\r
169\r
170#if defined(_USE_MZ80)\r
171#include "../../cpu/mz80/mz80.h"\r
172\r
173#define z80_run(cycles) mz80_run(cycles)\r
174#define z80_run_nr(cycles) mz80_run(cycles)\r
175#define z80_int() mz80int(0)\r
176#define z80_resetCycles() mz80GetElapsedTicks(1)\r
177\r
178#elif defined(_USE_DRZ80)\r
179#include "../../cpu/DrZ80/drz80.h"\r
180\r
181extern struct DrZ80 drZ80;\r
182\r
183#define z80_run(cycles) ((cycles) - DrZ80Run(&drZ80, cycles))\r
184#define z80_run_nr(cycles) DrZ80Run(&drZ80, cycles)\r
185#define z80_int() { \\r
186 drZ80.z80irqvector = 0xFF; /* default IRQ vector RST opcode */ \\r
187 drZ80.Z80_IRQ = 1; \\r
188}\r
189#define z80_resetCycles()\r
190\r
191#elif defined(_USE_CZ80)\r
192#include "../../cpu/cz80/cz80.h"\r
193\r
194#define z80_run(cycles) Cz80_Exec(&CZ80, cycles)\r
195#define z80_run_nr(cycles) Cz80_Exec(&CZ80, cycles)\r
196#define z80_int() Cz80_Set_IRQ(&CZ80, 0, HOLD_LINE)\r
197#define z80_resetCycles()\r
198\r
199#else\r
200\r
201#define z80_run(cycles) (cycles)\r
202#define z80_run_nr(cycles)\r
203#define z80_int()\r
204#define z80_resetCycles()\r
205\r
206#endif\r
207\r
cc68a136 208// ---------------------------------------------------------\r
209\r
70357ce5 210extern int PicoMCD;\r
211\r
cc68a136 212// main oscillator clock which controls timing\r
213#define OSC_NTSC 53693100\r
b8cbd802 214// seems to be accurate, see scans from http://www.hot.ee/tmeeco/\r
215#define OSC_PAL 53203424\r
cc68a136 216\r
217struct PicoVideo\r
218{\r
219 unsigned char reg[0x20];\r
b8cbd802 220 unsigned int command; // 32-bit Command\r
221 unsigned char pending; // 1 if waiting for second half of 32-bit command\r
222 unsigned char type; // Command type (v/c/vsram read/write)\r
223 unsigned short addr; // Read/Write address\r
224 int status; // Status bits\r
cc68a136 225 unsigned char pending_ints; // pending interrupts: ??VH????\r
b8cbd802 226 signed char lwrite_cnt; // VDP write count during active display line\r
227 unsigned char pad[0x12];\r
cc68a136 228};\r
229\r
230struct PicoMisc\r
231{\r
232 unsigned char rotate;\r
233 unsigned char z80Run;\r
e5503e2f 234 unsigned char padTHPhase[2]; // 02 phase of gamepad TH switches\r
235 short scanline; // 04 0 to 261||311; -1 in fast mode\r
236 char dirtyPal; // 06 Is the palette dirty (1 - change @ this frame, 2 - some time before)\r
237 unsigned char hardware; // 07 Hardware value for country\r
238 unsigned char pal; // 08 1=PAL 0=NTSC\r
239 unsigned char sram_reg; // SRAM mode register. bit0: allow read? bit1: deny write? bit2: EEPROM? bit4: detected? (header or by access)\r
240 unsigned short z80_bank68k; // 0a\r
cc68a136 241 unsigned short z80_lastaddr; // this is for Z80 faking\r
242 unsigned char z80_fakeval;\r
243 unsigned char pad0;\r
e5503e2f 244 unsigned char padDelay[2]; // 10 gamepad phase time outs, so we count a delay\r
1dceadae 245 unsigned short eeprom_addr; // EEPROM address register\r
246 unsigned char eeprom_cycle; // EEPROM SRAM cycle number\r
247 unsigned char eeprom_slave; // EEPROM slave word for X24C02 and better SRAMs\r
721cd396 248 unsigned char prot_bytes[2]; // simple protection faking\r
b8cbd802 249 unsigned short dma_xfers;\r
312e9ce1 250 unsigned char pad[2];\r
251 unsigned int frame_count; // mainly for movies\r
cc68a136 252};\r
253\r
254// some assembly stuff depend on these, do not touch!\r
255struct Pico\r
256{\r
257 unsigned char ram[0x10000]; // 0x00000 scratch ram\r
258 unsigned short vram[0x8000]; // 0x10000\r
259 unsigned char zram[0x2000]; // 0x20000 Z80 ram\r
260 unsigned char ioports[0x10];\r
261 unsigned int pad[0x3c]; // unused\r
262 unsigned short cram[0x40]; // 0x22100\r
263 unsigned short vsram[0x40]; // 0x22180\r
264\r
265 unsigned char *rom; // 0x22200\r
266 unsigned int romsize; // 0x22204\r
267\r
268 struct PicoMisc m;\r
269 struct PicoVideo video;\r
270};\r
271\r
272// sram\r
273struct PicoSRAM\r
274{\r
4ff2d527 275 unsigned char *data; // actual data\r
276 unsigned int start; // start address in 68k address space\r
cc68a136 277 unsigned int end;\r
1dceadae 278 unsigned char unused1; // 0c: unused\r
279 unsigned char unused2;\r
cc68a136 280 unsigned char changed;\r
1dceadae 281 unsigned char eeprom_type; // eeprom type: 0: 7bit (24C01), 2: device with 2 addr words (X24C02+), 3: dev with 3 addr words\r
282 unsigned char eeprom_abits; // eeprom access must be odd addr for: bit0 ~ cl, bit1 ~ out\r
283 unsigned char eeprom_bit_cl; // bit number for cl\r
284 unsigned char eeprom_bit_in; // bit number for in\r
285 unsigned char eeprom_bit_out; // bit number for out\r
cc68a136 286};\r
287\r
288// MCD\r
289#include "cd/cd_sys.h"\r
290#include "cd/LC89510.h"\r
d1df8786 291#include "cd/gfx_cd.h"\r
cc68a136 292\r
4f265db7 293struct mcd_pcm\r
294{\r
295 unsigned char control; // reg7\r
296 unsigned char enabled; // reg8\r
297 unsigned char cur_ch;\r
298 unsigned char bank;\r
299 int pad1;\r
300\r
4ff2d527 301 struct pcm_chan // 08, size 0x10\r
4f265db7 302 {\r
303 unsigned char regs[8];\r
4ff2d527 304 unsigned int addr; // .08: played sample address\r
4f265db7 305 int pad;\r
306 } ch[8];\r
307};\r
308\r
c459aefd 309struct mcd_misc\r
310{\r
311 unsigned short hint_vector;\r
312 unsigned char busreq;\r
51a902ae 313 unsigned char s68k_pend_ints;\r
89fa852d 314 unsigned int state_flags; // 04: emu state: reset_pending, dmna_pending\r
51a902ae 315 unsigned int counter75hz;\r
4ff2d527 316 unsigned short audio_offset; // 0c: for savestates: play pointer offset (0-1023)\r
75736070 317 unsigned char audio_track; // playing audio track # (zero based)\r
6cadc2da 318 char pad1;\r
4ff2d527 319 int timer_int3; // 10\r
4f265db7 320 unsigned int timer_stopwatch;\r
6cadc2da 321 unsigned char bcram_reg; // 18: battery-backed RAM cart register\r
322 unsigned char pad2;\r
323 unsigned short pad3;\r
324 int pad[9];\r
c459aefd 325};\r
326\r
cc68a136 327typedef struct\r
328{\r
4ff2d527 329 unsigned char bios[0x20000]; // 000000: 128K\r
330 union { // 020000: 512K\r
fa1e5e29 331 unsigned char prg_ram[0x80000];\r
cc68a136 332 unsigned char prg_ram_b[4][0x20000];\r
333 };\r
4ff2d527 334 union { // 0a0000: 256K\r
fa1e5e29 335 struct {\r
336 unsigned char word_ram2M[0x40000];\r
337 unsigned char unused[0x20000];\r
338 };\r
339 struct {\r
340 unsigned char unused[0x20000];\r
341 unsigned char word_ram1M[2][0x20000];\r
342 };\r
343 };\r
4ff2d527 344 union { // 100000: 64K\r
fa1e5e29 345 unsigned char pcm_ram[0x10000];\r
4f265db7 346 unsigned char pcm_ram_b[0x10][0x1000];\r
347 };\r
4ff2d527 348 unsigned char s68k_regs[0x200]; // 110000: GA, not CPU regs\r
349 unsigned char bram[0x2000]; // 110200: 8K\r
350 struct mcd_misc m; // 112200: misc\r
351 struct mcd_pcm pcm; // 112240:\r
75736070 352 _scd_toc TOC; // not to be saved\r
cc68a136 353 CDD cdd;\r
354 CDC cdc;\r
355 _scd scd;\r
d1df8786 356 Rot_Comp rot_comp;\r
cc68a136 357} mcd_state;\r
358\r
359#define Pico_mcd ((mcd_state *)Pico.rom)\r
360\r
51a902ae 361// Area.c\r
eff55556 362PICO_INTERNAL int PicoAreaPackCpu(unsigned char *cpu, int is_sub);\r
363PICO_INTERNAL int PicoAreaUnpackCpu(unsigned char *cpu, int is_sub);\r
51a902ae 364\r
365// cd/Area.c\r
eff55556 366PICO_INTERNAL int PicoCdSaveState(void *file);\r
367PICO_INTERNAL int PicoCdLoadState(void *file);\r
cc68a136 368\r
1dceadae 369// Cart.c\r
370PICO_INTERNAL void PicoCartDetect(void);\r
371\r
03e4f2a3 372// Debug.c\r
b5e5172d 373int CM_compareRun(int cyc, int is_sub);\r
03e4f2a3 374\r
cc68a136 375// Draw.c\r
eff55556 376PICO_INTERNAL int PicoLine(int scan);\r
377PICO_INTERNAL void PicoFrameStart(void);\r
cc68a136 378\r
379// Draw2.c\r
eff55556 380PICO_INTERNAL void PicoFrameFull();\r
cc68a136 381\r
382// Memory.c\r
eff55556 383PICO_INTERNAL int PicoInitPc(unsigned int pc);\r
8ab3e3c1 384PICO_INTERNAL_ASM unsigned int PicoRead32(unsigned int a);\r
eff55556 385PICO_INTERNAL void PicoMemSetup(void);\r
386PICO_INTERNAL_ASM void PicoMemReset(void);\r
e5503e2f 387PICO_INTERNAL int PadRead(int i);\r
eff55556 388PICO_INTERNAL unsigned char z80_read(unsigned short a);\r
a4221917 389#ifndef _USE_CZ80\r
eff55556 390PICO_INTERNAL_ASM void z80_write(unsigned char data, unsigned short a);\r
391PICO_INTERNAL void z80_write16(unsigned short data, unsigned short a);\r
a4221917 392PICO_INTERNAL unsigned short z80_read16(unsigned short a);\r
393#else\r
394PICO_INTERNAL_ASM void z80_write(unsigned int a, unsigned char data);\r
395#endif\r
cc68a136 396\r
397// cd/Memory.c\r
eff55556 398PICO_INTERNAL void PicoMemSetupCD(void);\r
399PICO_INTERNAL_ASM void PicoMemResetCD(int r3);\r
400PICO_INTERNAL_ASM void PicoMemResetCDdecode(int r3);\r
cc68a136 401\r
402// Pico.c\r
403extern struct Pico Pico;\r
404extern struct PicoSRAM SRam;\r
405extern int emustatus;\r
d9153729 406extern int z80startCycle, z80stopCycle; // in 68k cycles\r
eff55556 407PICO_INTERNAL int CheckDMA(void);\r
cc68a136 408\r
409// cd/Pico.c\r
e5f426aa 410PICO_INTERNAL int PicoInitMCD(void);\r
411PICO_INTERNAL void PicoExitMCD(void);\r
eff55556 412PICO_INTERNAL int PicoResetMCD(int hard);\r
413PICO_INTERNAL int PicoFrameMCD(void);\r
cc68a136 414\r
415// Sek.c\r
eff55556 416PICO_INTERNAL int SekInit(void);\r
417PICO_INTERNAL int SekReset(void);\r
3aa1e148 418PICO_INTERNAL void SekState(int *data);\r
eff55556 419PICO_INTERNAL void SekSetRealTAS(int use_real);\r
cc68a136 420\r
421// cd/Sek.c\r
eff55556 422PICO_INTERNAL int SekInitS68k(void);\r
423PICO_INTERNAL int SekResetS68k(void);\r
424PICO_INTERNAL int SekInterruptS68k(int irq);\r
cc68a136 425\r
7a93adeb 426// sound/sound.c\r
427extern int PsndLen_exc_cnt;\r
428extern int PsndLen_exc_add;\r
429\r
cc68a136 430// VideoPort.c\r
eff55556 431PICO_INTERNAL_ASM void PicoVideoWrite(unsigned int a,unsigned short d);\r
432PICO_INTERNAL_ASM unsigned int PicoVideoRead(unsigned int a);\r
cc68a136 433\r
434// Misc.c\r
eff55556 435PICO_INTERNAL void SRAMWriteEEPROM(unsigned int d);\r
436PICO_INTERNAL void SRAMUpdPending(unsigned int a, unsigned int d);\r
437PICO_INTERNAL_ASM unsigned int SRAMReadEEPROM(void);\r
438PICO_INTERNAL_ASM void memcpy16(unsigned short *dest, unsigned short *src, int count);\r
439PICO_INTERNAL_ASM void memcpy16bswap(unsigned short *dest, void *src, int count);\r
440PICO_INTERNAL_ASM void memcpy32(int *dest, int *src, int count); // 32bit word count\r
441PICO_INTERNAL_ASM void memset32(int *dest, int c, int count);\r
cc68a136 442\r
fa1e5e29 443// cd/Misc.c\r
eff55556 444PICO_INTERNAL_ASM void wram_2M_to_1M(unsigned char *m);\r
445PICO_INTERNAL_ASM void wram_1M_to_2M(unsigned char *m);\r
446\r
447// cd/buffering.c\r
448PICO_INTERNAL void PicoCDBufferRead(void *dest, int lba);\r
449\r
450// sound/sound.c\r
9d917eea 451PICO_INTERNAL void PsndReset(void);\r
452PICO_INTERNAL void Psnd_timers_and_dac(int raster);\r
453PICO_INTERNAL int PsndRender(int offset, int length);\r
454PICO_INTERNAL void PsndClear(void);\r
eff55556 455// z80 functionality wrappers\r
456PICO_INTERNAL void z80_init(void);\r
eff55556 457PICO_INTERNAL void z80_pack(unsigned char *data);\r
458PICO_INTERNAL void z80_unpack(unsigned char *data);\r
459PICO_INTERNAL void z80_reset(void);\r
460PICO_INTERNAL void z80_exit(void);\r
fa1e5e29 461\r
cc68a136 462\r
463#ifdef __cplusplus\r
464} // End of extern "C"\r
465#endif\r
eff55556 466\r
b8cbd802 467// emulation event logging\r
468#ifndef EL_LOGMASK\r
469#define EL_LOGMASK 0\r
470#endif\r
471\r
472#define EL_HVCNT 0x0001 /* hv counter reads */\r
473#define EL_SR 0x0002 /* SR reads */\r
474#define EL_INTS 0x0004 /* ints and acks */\r
475#define EL_YM2612R 0x0008 /* 68k ym2612 reads */\r
476#define EL_INTSW 0x0010 /* log irq switching on/off */\r
477#define EL_ASVDP 0x0020 /* VDP accesses during active scan */\r
478#define EL_VDPDMA 0x0040 /* VDP DMA transfers and their timing */\r
5f20bb80 479#define EL_BUSREQ 0x0080 /* z80 busreq r/w or reset w */\r
b8cbd802 480#define EL_Z80BNK 0x0100 /* z80 i/o through bank area */\r
1dceadae 481#define EL_SRAMIO 0x0200 /* sram i/o */\r
482#define EL_EEPROM 0x0400 /* eeprom debug */\r
483#define EL_UIO 0x0800 /* unmapped i/o */\r
ca61ee42 484#define EL_IO 0x1000 /* all i/o */\r
485#define EL_CDPOLL 0x2000 /* MCD: log poll detection */\r
b8cbd802 486\r
487#define EL_STATUS 0x4000 /* status messages */\r
71de3cd9 488#define EL_ANOMALY 0x8000 /* some unexpected conditions (during emulation) */\r
b8cbd802 489\r
490#if EL_LOGMASK\r
7d0143a2 491extern void lprintf(const char *fmt, ...);\r
b8cbd802 492#define elprintf(w,f,...) \\r
493{ \\r
494 if ((w) & EL_LOGMASK) \\r
7d0143a2 495 lprintf("%05i:%03i: " f "\n",Pico.m.frame_count,Pico.m.scanline,##__VA_ARGS__); \\r
b8cbd802 496}\r
497#else\r
498#define elprintf(w,f,...)\r
499#endif\r
500\r
eff55556 501#endif // PICO_INTERNAL_INCLUDED\r
502\r
fast MegaDrive/MegaCD/32X emulator