[picodrive.git] / Pico / PicoInt.h

// Pico Library - Internal Header File\r
\r
// (c) Copyright 2004 Dave, All rights reserved.\r
// (c) Copyright 2006,2007 Grazvydas "notaz" Ignotas, all rights reserved.\r
// Free for non-commercial use.\r
\r
// For commercial use, separate licencing terms must be obtained.\r
\r
#ifndef PICO_INTERNAL_INCLUDED\r
#define PICO_INTERNAL_INCLUDED\r
\r
#include <stdio.h>\r
#include <stdlib.h>\r
#include <string.h>\r
#include "Pico.h"\r
#include "carthw/carthw.h"\r
\r
//\r
#define USE_POLL_DETECT\r
\r
#ifndef PICO_INTERNAL\r
#define PICO_INTERNAL\r
#endif\r
#ifndef PICO_INTERNAL_ASM\r
#define PICO_INTERNAL_ASM\r
#endif\r
\r
// to select core, define EMU_C68K, EMU_M68K or EMU_F68K in your makefile or project\r
\r
#ifdef __cplusplus\r
extern "C" {\r
#endif\r
\r
\r
// ----------------------- 68000 CPU -----------------------\r
#ifdef EMU_C68K\r
#include "../cpu/Cyclone/Cyclone.h"\r
extern struct Cyclone PicoCpuCM68k, PicoCpuCS68k;\r
#define SekCyclesLeftNoMCD PicoCpuCM68k.cycles // cycles left for this run\r
#define SekCyclesLeft \\r
	(((PicoMCD&1) && (PicoOpt & 0x2000)) ? (SekCycleAim-SekCycleCnt) : SekCyclesLeftNoMCD)\r
#define SekCyclesLeftS68k \\r
	((PicoOpt & 0x2000) ? (SekCycleAimS68k-SekCycleCntS68k) : PicoCpuCS68k.cycles)\r
#define SekSetCyclesLeftNoMCD(c) PicoCpuCM68k.cycles=c\r
#define SekSetCyclesLeft(c) { \\r
	if ((PicoMCD&1) && (PicoOpt & 0x2000)) SekCycleCnt=SekCycleAim-(c); else SekSetCyclesLeftNoMCD(c); \\r
}\r
#define SekPc (PicoCpuCM68k.pc-PicoCpuCM68k.membase)\r
#define SekPcS68k (PicoCpuCS68k.pc-PicoCpuCS68k.membase)\r
#define SekSetStop(x) { PicoCpuCM68k.state_flags&=~1; if (x) { PicoCpuCM68k.state_flags|=1; PicoCpuCM68k.cycles=0; } }\r
#define SekSetStopS68k(x) { PicoCpuCS68k.state_flags&=~1; if (x) { PicoCpuCS68k.state_flags|=1; PicoCpuCS68k.cycles=0; } }\r
#define SekIsStoppedS68k() (PicoCpuCS68k.state_flags&1)\r
#define SekShouldInterrupt (PicoCpuCM68k.irq > (PicoCpuCM68k.srh&7))\r
\r
#define SekInterrupt(i) PicoCpuCM68k.irq=i\r
\r
#ifdef EMU_M68K\r
#define EMU_CORE_DEBUG\r
#endif\r
#endif\r
\r
#ifdef EMU_F68K\r
#include "../cpu/fame/fame.h"\r
extern M68K_CONTEXT PicoCpuFM68k, PicoCpuFS68k;\r
#define SekCyclesLeftNoMCD PicoCpuFM68k.io_cycle_counter\r
#define SekCyclesLeft \\r
	(((PicoMCD&1) && (PicoOpt & 0x2000)) ? (SekCycleAim-SekCycleCnt) : SekCyclesLeftNoMCD)\r
#define SekCyclesLeftS68k \\r
	((PicoOpt & 0x2000) ? (SekCycleAimS68k-SekCycleCntS68k) : PicoCpuFS68k.io_cycle_counter)\r
#define SekSetCyclesLeftNoMCD(c) PicoCpuFM68k.io_cycle_counter=c\r
#define SekSetCyclesLeft(c) { \\r
	if ((PicoMCD&1) && (PicoOpt & 0x2000)) SekCycleCnt=SekCycleAim-(c); else SekSetCyclesLeftNoMCD(c); \\r
}\r
#define SekPc     fm68k_get_pc(&PicoCpuFM68k)\r
#define SekPcS68k fm68k_get_pc(&PicoCpuFS68k)\r
#define SekSetStop(x) { \\r
	PicoCpuFM68k.execinfo &= ~FM68K_HALTED; \\r
	if (x) { PicoCpuFM68k.execinfo |= FM68K_HALTED; PicoCpuFM68k.io_cycle_counter = 0; } \\r
}\r
#define SekSetStopS68k(x) { \\r
	PicoCpuFS68k.execinfo &= ~FM68K_HALTED; \\r
	if (x) { PicoCpuFS68k.execinfo |= FM68K_HALTED; PicoCpuFS68k.io_cycle_counter = 0; } \\r
}\r
#define SekIsStoppedS68k() (PicoCpuFS68k.execinfo&FM68K_HALTED)\r
#define SekShouldInterrupt fm68k_would_interrupt()\r
\r
#define SekInterrupt(irq) PicoCpuFM68k.interrupts[0]=irq\r
\r
#ifdef EMU_M68K\r
#define EMU_CORE_DEBUG\r
#endif\r
#endif\r
\r
#ifdef EMU_M68K\r
#include "../cpu/musashi/m68kcpu.h"\r
extern m68ki_cpu_core PicoCpuMM68k, PicoCpuMS68k;\r
#ifndef SekCyclesLeft\r
#define SekCyclesLeftNoMCD PicoCpuMM68k.cyc_remaining_cycles\r
#define SekCyclesLeft \\r
	(((PicoMCD&1) && (PicoOpt & 0x2000)) ? (SekCycleAim-SekCycleCnt) : SekCyclesLeftNoMCD)\r
#define SekCyclesLeftS68k \\r
	((PicoOpt & 0x2000) ? (SekCycleAimS68k-SekCycleCntS68k) : PicoCpuMS68k.cyc_remaining_cycles)\r
#define SekSetCyclesLeftNoMCD(c) SET_CYCLES(c)\r
#define SekSetCyclesLeft(c) { \\r
	if ((PicoMCD&1) && (PicoOpt & 0x2000)) SekCycleCnt=SekCycleAim-(c); else SET_CYCLES(c); \\r
}\r
#define SekPc m68k_get_reg(&PicoCpuMM68k, M68K_REG_PC)\r
#define SekPcS68k m68k_get_reg(&PicoCpuMS68k, M68K_REG_PC)\r
#define SekSetStop(x) { \\r
	if(x) { SET_CYCLES(0); PicoCpuMM68k.stopped=STOP_LEVEL_STOP; } \\r
	else PicoCpuMM68k.stopped=0; \\r
}\r
#define SekSetStopS68k(x) { \\r
	if(x) { SET_CYCLES(0); PicoCpuMS68k.stopped=STOP_LEVEL_STOP; } \\r
	else PicoCpuMS68k.stopped=0; \\r
}\r
#define SekIsStoppedS68k() (PicoCpuMS68k.stopped==STOP_LEVEL_STOP)\r
#define SekShouldInterrupt (CPU_INT_LEVEL > FLAG_INT_MASK)\r
\r
#define SekInterrupt(irq) { \\r
	void *oldcontext = m68ki_cpu_p; \\r
	m68k_set_context(&PicoCpuMM68k); \\r
	m68k_set_irq(irq); \\r
	m68k_set_context(oldcontext); \\r
}\r
\r
#endif\r
#endif\r
\r
extern int SekCycleCnt; // cycles done in this frame\r
extern int SekCycleAim; // cycle aim\r
extern unsigned int SekCycleCntT; // total cycle counter, updated once per frame\r
\r
#define SekCyclesReset() { \\r
	SekCycleCntT+=SekCycleAim; \\r
	SekCycleCnt-=SekCycleAim; \\r
	SekCycleAim=0; \\r
}\r
#define SekCyclesBurn(c)  SekCycleCnt+=c\r
#define SekCyclesDone()  (SekCycleAim-SekCyclesLeft)    // nuber of cycles done in this frame (can be checked anywhere)\r
#define SekCyclesDoneT() (SekCycleCntT+SekCyclesDone()) // total nuber of cycles done for this rom\r
\r
#define SekEndRun(after) { \\r
	SekCycleCnt -= SekCyclesLeft - after; \\r
	if(SekCycleCnt < 0) SekCycleCnt = 0; \\r
	SekSetCyclesLeft(after); \\r
}\r
\r
extern int SekCycleCntS68k;\r
extern int SekCycleAimS68k;\r
\r
#define SekCyclesResetS68k() { \\r
	SekCycleCntS68k-=SekCycleAimS68k; \\r
	SekCycleAimS68k=0; \\r
}\r
#define SekCyclesDoneS68k()  (SekCycleAimS68k-SekCyclesLeftS68k)\r
\r
#ifdef EMU_CORE_DEBUG\r
#undef SekSetCyclesLeftNoMCD\r
#undef SekSetCyclesLeft\r
#undef SekCyclesBurn\r
#undef SekEndRun\r
#define SekSetCyclesLeftNoMCD(c)\r
#define SekSetCyclesLeft(c)\r
#define SekCyclesBurn(c) c\r
#define SekEndRun(c)\r
#endif\r
\r
// ----------------------- Z80 CPU -----------------------\r
\r
#if defined(_USE_MZ80)\r
#include "../../cpu/mz80/mz80.h"\r
\r
#define z80_run(cycles)    mz80_run(cycles)\r
#define z80_run_nr(cycles) mz80_run(cycles)\r
#define z80_int()          mz80int(0)\r
#define z80_resetCycles()  mz80GetElapsedTicks(1)\r
\r
#elif defined(_USE_DRZ80)\r
#include "../../cpu/DrZ80/drz80.h"\r
\r
extern struct DrZ80 drZ80;\r
\r
#define z80_run(cycles)    ((cycles) - DrZ80Run(&drZ80, cycles))\r
#define z80_run_nr(cycles) DrZ80Run(&drZ80, cycles)\r
#define z80_int() { \\r
  drZ80.z80irqvector = 0xFF; /* default IRQ vector RST opcode */ \\r
  drZ80.Z80_IRQ = 1; \\r
}\r
#define z80_resetCycles()\r
\r
#elif defined(_USE_CZ80)\r
#include "../../cpu/cz80/cz80.h"\r
\r
#define z80_run(cycles)    Cz80_Exec(&CZ80, cycles)\r
#define z80_run_nr(cycles) Cz80_Exec(&CZ80, cycles)\r
#define z80_int()          Cz80_Set_IRQ(&CZ80, 0, HOLD_LINE)\r
#define z80_resetCycles()\r
\r
#else\r
\r
#define z80_run(cycles)    (cycles)\r
#define z80_run_nr(cycles)\r
#define z80_int()\r
#define z80_resetCycles()\r
\r
#endif\r
\r
// ---------------------------------------------------------\r
\r
extern int PicoMCD;\r
\r
// main oscillator clock which controls timing\r
#define OSC_NTSC 53693100\r
// seems to be accurate, see scans from http://www.hot.ee/tmeeco/\r
#define OSC_PAL  53203424\r
\r
struct PicoVideo\r
{\r
  unsigned char reg[0x20];\r
  unsigned int command;       // 32-bit Command\r
  unsigned char pending;      // 1 if waiting for second half of 32-bit command\r
  unsigned char type;         // Command type (v/c/vsram read/write)\r
  unsigned short addr;        // Read/Write address\r
  int status;                 // Status bits\r
  unsigned char pending_ints; // pending interrupts: ??VH????\r
  signed char lwrite_cnt;     // VDP write count during active display line\r
  unsigned char pad[0x12];\r
};\r
\r
struct PicoMisc\r
{\r
  unsigned char rotate;\r
  unsigned char z80Run;\r
  unsigned char padTHPhase[2]; // 02 phase of gamepad TH switches\r
  short scanline;              // 04 0 to 261||311; -1 in fast mode\r
  char dirtyPal;               // 06 Is the palette dirty (1 - change @ this frame, 2 - some time before)\r
  unsigned char hardware;      // 07 Hardware value for country\r
  unsigned char pal;           // 08 1=PAL 0=NTSC\r
  unsigned char sram_reg;      // SRAM mode register. bit0: allow read? bit1: deny write? bit2: EEPROM? bit4: detected? (header or by access)\r
  unsigned short z80_bank68k;  // 0a\r
  unsigned short z80_lastaddr; // this is for Z80 faking\r
  unsigned char  z80_fakeval;\r
  unsigned char  pad0;\r
  unsigned char  padDelay[2];  // 10 gamepad phase time outs, so we count a delay\r
  unsigned short eeprom_addr;  // EEPROM address register\r
  unsigned char  eeprom_cycle; // EEPROM SRAM cycle number\r
  unsigned char  eeprom_slave; // EEPROM slave word for X24C02 and better SRAMs\r
  unsigned char prot_bytes[2]; // simple protection faking\r
  unsigned short dma_xfers;\r
  unsigned char pad[2];\r
  unsigned int  frame_count; // mainly for movies\r
};\r
\r
// some assembly stuff depend on these, do not touch!\r
struct Pico\r
{\r
  unsigned char ram[0x10000];  // 0x00000 scratch ram\r
  unsigned short vram[0x8000]; // 0x10000\r
  unsigned char zram[0x2000];  // 0x20000 Z80 ram\r
  unsigned char ioports[0x10];\r
  unsigned int pad[0x3c];      // unused\r
  unsigned short cram[0x40];   // 0x22100\r
  unsigned short vsram[0x40];  // 0x22180\r
\r
  unsigned char *rom;          // 0x22200\r
  unsigned int romsize;        // 0x22204\r
\r
  struct PicoMisc m;\r
  struct PicoVideo video;\r
};\r
\r
// sram\r
struct PicoSRAM\r
{\r
  unsigned char *data;		// actual data\r
  unsigned int start;		// start address in 68k address space\r
  unsigned int end;\r
  unsigned char unused1;	// 0c: unused\r
  unsigned char unused2;\r
  unsigned char changed;\r
  unsigned char eeprom_type;    // eeprom type: 0: 7bit (24C01), 2: device with 2 addr words (X24C02+), 3: dev with 3 addr words\r
  unsigned char eeprom_abits;	// eeprom access must be odd addr for: bit0 ~ cl, bit1 ~ out\r
  unsigned char eeprom_bit_cl;	// bit number for cl\r
  unsigned char eeprom_bit_in;  // bit number for in\r
  unsigned char eeprom_bit_out; // bit number for out\r
};\r
\r
// MCD\r
#include "cd/cd_sys.h"\r
#include "cd/LC89510.h"\r
#include "cd/gfx_cd.h"\r
\r
struct mcd_pcm\r
{\r
	unsigned char control; // reg7\r
	unsigned char enabled; // reg8\r
	unsigned char cur_ch;\r
	unsigned char bank;\r
	int pad1;\r
\r
	struct pcm_chan			// 08, size 0x10\r
	{\r
		unsigned char regs[8];\r
		unsigned int  addr;	// .08: played sample address\r
		int pad;\r
	} ch[8];\r
};\r
\r
struct mcd_misc\r
{\r
	unsigned short hint_vector;\r
	unsigned char  busreq;\r
	unsigned char  s68k_pend_ints;\r
	unsigned int   state_flags;	// 04: emu state: reset_pending, dmna_pending\r
	unsigned int   counter75hz;\r
	unsigned short audio_offset;	// 0c: for savestates: play pointer offset (0-1023)\r
	unsigned char  audio_track;	// playing audio track # (zero based)\r
	char           pad1;\r
	int            timer_int3;	// 10\r
	unsigned int   timer_stopwatch;\r
	unsigned char  bcram_reg;	// 18: battery-backed RAM cart register\r
	unsigned char  pad2;\r
	unsigned short pad3;\r
	int pad[9];\r
};\r
\r
typedef struct\r
{\r
	unsigned char bios[0x20000];			// 000000: 128K\r
	union {						// 020000: 512K\r
		unsigned char prg_ram[0x80000];\r
		unsigned char prg_ram_b[4][0x20000];\r
	};\r
	union {						// 0a0000: 256K\r
		struct {\r
			unsigned char word_ram2M[0x40000];\r
			unsigned char unused[0x20000];\r
		};\r
		struct {\r
			unsigned char unused[0x20000];\r
			unsigned char word_ram1M[2][0x20000];\r
		};\r
	};\r
	union {						// 100000: 64K\r
		unsigned char pcm_ram[0x10000];\r
		unsigned char pcm_ram_b[0x10][0x1000];\r
	};\r
	unsigned char s68k_regs[0x200];			// 110000: GA, not CPU regs\r
	unsigned char bram[0x2000];			// 110200: 8K\r
	struct mcd_misc m;				// 112200: misc\r
	struct mcd_pcm pcm;				// 112240:\r
	_scd_toc TOC;					// not to be saved\r
	CDD  cdd;\r
	CDC  cdc;\r
	_scd scd;\r
	Rot_Comp rot_comp;\r
} mcd_state;\r
\r
#define Pico_mcd ((mcd_state *)Pico.rom)\r
\r
// Area.c\r
PICO_INTERNAL int PicoAreaPackCpu(unsigned char *cpu, int is_sub);\r
PICO_INTERNAL int PicoAreaUnpackCpu(unsigned char *cpu, int is_sub);\r
\r
// cd/Area.c\r
PICO_INTERNAL int PicoCdSaveState(void *file);\r
PICO_INTERNAL int PicoCdLoadState(void *file);\r
\r
// Cart.c\r
PICO_INTERNAL void PicoCartDetect(void);\r
\r
// Debug.c\r
int CM_compareRun(int cyc, int is_sub);\r
\r
// Draw.c\r
PICO_INTERNAL int PicoLine(int scan);\r
PICO_INTERNAL void PicoFrameStart(void);\r
\r
// Draw2.c\r
PICO_INTERNAL void PicoFrameFull();\r
\r
// Memory.c\r
PICO_INTERNAL int PicoInitPc(unsigned int pc);\r
PICO_INTERNAL_ASM unsigned int PicoRead32(unsigned int a);\r
PICO_INTERNAL void PicoMemSetup(void);\r
PICO_INTERNAL_ASM void PicoMemReset(void);\r
PICO_INTERNAL void PicoMemResetHooks(void);\r
PICO_INTERNAL int PadRead(int i);\r
PICO_INTERNAL unsigned char z80_read(unsigned short a);\r
#ifndef _USE_CZ80\r
PICO_INTERNAL_ASM void z80_write(unsigned char data, unsigned short a);\r
PICO_INTERNAL void z80_write16(unsigned short data, unsigned short a);\r
PICO_INTERNAL unsigned short z80_read16(unsigned short a);\r
#else\r
PICO_INTERNAL_ASM void z80_write(unsigned int a, unsigned char data);\r
#endif\r
extern unsigned int (*PicoRead16Hook)(unsigned int a, int realsize);\r
extern void (*PicoWrite8Hook) (unsigned int a,unsigned int d,int realsize);\r
extern void (*PicoWrite16Hook)(unsigned int a,unsigned int d,int realsize);\r
\r
// cd/Memory.c\r
PICO_INTERNAL void PicoMemSetupCD(void);\r
PICO_INTERNAL_ASM void PicoMemResetCD(int r3);\r
PICO_INTERNAL_ASM void PicoMemResetCDdecode(int r3);\r
\r
// Pico.c\r
extern struct Pico Pico;\r
extern struct PicoSRAM SRam;\r
extern int emustatus;\r
extern int z80startCycle, z80stopCycle; // in 68k cycles\r
extern void (*PicoResetHook)(void);\r
extern void (*PicoLineHook)(void);\r
PICO_INTERNAL int CheckDMA(void);\r
\r
// cd/Pico.c\r
PICO_INTERNAL int  PicoInitMCD(void);\r
PICO_INTERNAL void PicoExitMCD(void);\r
PICO_INTERNAL int PicoResetMCD(int hard);\r
PICO_INTERNAL int PicoFrameMCD(void);\r
\r
// Sek.c\r
PICO_INTERNAL int SekInit(void);\r
PICO_INTERNAL int SekReset(void);\r
PICO_INTERNAL void SekState(int *data);\r
PICO_INTERNAL void SekSetRealTAS(int use_real);\r
\r
// cd/Sek.c\r
PICO_INTERNAL int SekInitS68k(void);\r
PICO_INTERNAL int SekResetS68k(void);\r
PICO_INTERNAL int SekInterruptS68k(int irq);\r
\r
// sound/sound.c\r
extern int PsndLen_exc_cnt;\r
extern int PsndLen_exc_add;\r
\r
// VideoPort.c\r
PICO_INTERNAL_ASM void PicoVideoWrite(unsigned int a,unsigned short d);\r
PICO_INTERNAL_ASM unsigned int PicoVideoRead(unsigned int a);\r
extern int (*PicoDmaHook)(unsigned int source, int len, unsigned short **srcp, unsigned short **limitp);\r
\r
// Misc.c\r
PICO_INTERNAL void SRAMWriteEEPROM(unsigned int d);\r
PICO_INTERNAL void SRAMUpdPending(unsigned int a, unsigned int d);\r
PICO_INTERNAL_ASM unsigned int SRAMReadEEPROM(void);\r
PICO_INTERNAL_ASM void memcpy16(unsigned short *dest, unsigned short *src, int count);\r
PICO_INTERNAL_ASM void memcpy16bswap(unsigned short *dest, void *src, int count);\r
PICO_INTERNAL_ASM void memcpy32(int *dest, int *src, int count); // 32bit word count\r
PICO_INTERNAL_ASM void memset32(int *dest, int c, int count);\r
\r
// cd/Misc.c\r
PICO_INTERNAL_ASM void wram_2M_to_1M(unsigned char *m);\r
PICO_INTERNAL_ASM void wram_1M_to_2M(unsigned char *m);\r
\r
// cd/buffering.c\r
PICO_INTERNAL void PicoCDBufferRead(void *dest, int lba);\r
\r
// sound/sound.c\r
PICO_INTERNAL void PsndReset(void);\r
PICO_INTERNAL void Psnd_timers_and_dac(int raster);\r
PICO_INTERNAL int  PsndRender(int offset, int length);\r
PICO_INTERNAL void PsndClear(void);\r
// z80 functionality wrappers\r
PICO_INTERNAL void z80_init(void);\r
PICO_INTERNAL void z80_pack(unsigned char *data);\r
PICO_INTERNAL void z80_unpack(unsigned char *data);\r
PICO_INTERNAL void z80_reset(void);\r
PICO_INTERNAL void z80_exit(void);\r
\r
\r
#ifdef __cplusplus\r
} // End of extern "C"\r
#endif\r
\r
// emulation event logging\r
#ifndef EL_LOGMASK\r
#define EL_LOGMASK 0\r
#endif\r
\r
#define EL_HVCNT   0x00000001 /* hv counter reads */\r
#define EL_SR      0x00000002 /* SR reads */\r
#define EL_INTS    0x00000004 /* ints and acks */\r
#define EL_YM2612R 0x00000008 /* 68k ym2612 reads */\r
#define EL_INTSW   0x00000010 /* log irq switching on/off */\r
#define EL_ASVDP   0x00000020 /* VDP accesses during active scan */\r
#define EL_VDPDMA  0x00000040 /* VDP DMA transfers and their timing */\r
#define EL_BUSREQ  0x00000080 /* z80 busreq r/w or reset w */\r
#define EL_Z80BNK  0x00000100 /* z80 i/o through bank area */\r
#define EL_SRAMIO  0x00000200 /* sram i/o */\r
#define EL_EEPROM  0x00000400 /* eeprom debug */\r
#define EL_UIO     0x00000800 /* unmapped i/o */\r
#define EL_IO      0x00001000 /* all i/o */\r
#define EL_CDPOLL  0x00002000 /* MCD: log poll detection */\r
#define EL_SVP     0x00004000 /* SVP stuff */\r
\r
#define EL_STATUS  0x40000000 /* status messages */\r
#define EL_ANOMALY 0x80000000 /* some unexpected conditions (during emulation) */\r
\r
#if EL_LOGMASK\r
extern void lprintf(const char *fmt, ...);\r
#define elprintf(w,f,...) \\r
{ \\r
	if ((w) & EL_LOGMASK) \\r
		lprintf("%05i:%03i: " f "\n",Pico.m.frame_count,Pico.m.scanline,##__VA_ARGS__); \\r
}\r
#else\r
#define elprintf(w,f,...)\r
#endif\r
\r
#endif // PICO_INTERNAL_INCLUDED\r
\r
Commit	Line	Data
eff55556	1	// Pico Library - Internal Header File\r
cc68a136	2	\r
cc68a136	3	// (c) Copyright 2004 Dave, All rights reserved.\r
6cadc2da	4	// (c) Copyright 2006,2007 Grazvydas "notaz" Ignotas, all rights reserved.\r
cc68a136	5	// Free for non-commercial use.\r
	6	\r
	7	// For commercial use, separate licencing terms must be obtained.\r
	8	\r
eff55556	9	#ifndef PICO_INTERNAL_INCLUDED\r
eff55556	10	#define PICO_INTERNAL_INCLUDED\r
cc68a136	11	\r
	12	#include <stdio.h>\r
	13	#include <stdlib.h>\r
	14	#include <string.h>\r
	15	#include "Pico.h"\r
f53f286a	16	#include "carthw/carthw.h"\r
cc68a136	17	\r
89fa852d	18	//\r
	19	#define USE_POLL_DETECT\r
	20	\r
eff55556	21	#ifndef PICO_INTERNAL\r
	22	#define PICO_INTERNAL\r
	23	#endif\r
	24	#ifndef PICO_INTERNAL_ASM\r
	25	#define PICO_INTERNAL_ASM\r
	26	#endif\r
cc68a136	27	\r
70357ce5	28	// to select core, define EMU_C68K, EMU_M68K or EMU_F68K in your makefile or project\r
cc68a136	29	\r
	30	#ifdef __cplusplus\r
	31	extern "C" {\r
	32	#endif\r
	33	\r
	34	\r
	35	// ----------------------- 68000 CPU -----------------------\r
	36	#ifdef EMU_C68K\r
	37	#include "../cpu/Cyclone/Cyclone.h"\r
3aa1e148	38	extern struct Cyclone PicoCpuCM68k, PicoCpuCS68k;\r
3aa1e148	39	#define SekCyclesLeftNoMCD PicoCpuCM68k.cycles // cycles left for this run\r
7336a99a	40	#define SekCyclesLeft \\r
7336a99a	41	(((PicoMCD&1) && (PicoOpt & 0x2000)) ? (SekCycleAim-SekCycleCnt) : SekCyclesLeftNoMCD)\r
7a1f6e45	42	#define SekCyclesLeftS68k \\r
3aa1e148	43	((PicoOpt & 0x2000) ? (SekCycleAimS68k-SekCycleCntS68k) : PicoCpuCS68k.cycles)\r
3aa1e148	44	#define SekSetCyclesLeftNoMCD(c) PicoCpuCM68k.cycles=c\r
7336a99a	45	#define SekSetCyclesLeft(c) { \\r
	46	if ((PicoMCD&1) && (PicoOpt & 0x2000)) SekCycleCnt=SekCycleAim-(c); else SekSetCyclesLeftNoMCD(c); \\r
	47	}\r
3aa1e148	48	#define SekPc (PicoCpuCM68k.pc-PicoCpuCM68k.membase)\r
	49	#define SekPcS68k (PicoCpuCS68k.pc-PicoCpuCS68k.membase)\r
	50	#define SekSetStop(x) { PicoCpuCM68k.state_flags&=~1; if (x) { PicoCpuCM68k.state_flags\|=1; PicoCpuCM68k.cycles=0; } }\r
	51	#define SekSetStopS68k(x) { PicoCpuCS68k.state_flags&=~1; if (x) { PicoCpuCS68k.state_flags\|=1; PicoCpuCS68k.cycles=0; } }\r
ca61ee42	52	#define SekIsStoppedS68k() (PicoCpuCS68k.state_flags&1)\r
03e4f2a3	53	#define SekShouldInterrupt (PicoCpuCM68k.irq > (PicoCpuCM68k.srh&7))\r
b542be46	54	\r
	55	#define SekInterrupt(i) PicoCpuCM68k.irq=i\r
	56	\r
03e4f2a3	57	#ifdef EMU_M68K\r
	58	#define EMU_CORE_DEBUG\r
	59	#endif\r
cc68a136	60	#endif\r
cc68a136	61	\r
70357ce5	62	#ifdef EMU_F68K\r
70357ce5	63	#include "../cpu/fame/fame.h"\r
b542be46	64	extern M68K_CONTEXT PicoCpuFM68k, PicoCpuFS68k;\r
3aa1e148	65	#define SekCyclesLeftNoMCD PicoCpuFM68k.io_cycle_counter\r
70357ce5	66	#define SekCyclesLeft \\r
	67	(((PicoMCD&1) && (PicoOpt & 0x2000)) ? (SekCycleAim-SekCycleCnt) : SekCyclesLeftNoMCD)\r
	68	#define SekCyclesLeftS68k \\r
3aa1e148	69	((PicoOpt & 0x2000) ? (SekCycleAimS68k-SekCycleCntS68k) : PicoCpuFS68k.io_cycle_counter)\r
3aa1e148	70	#define SekSetCyclesLeftNoMCD(c) PicoCpuFM68k.io_cycle_counter=c\r
70357ce5	71	#define SekSetCyclesLeft(c) { \\r
	72	if ((PicoMCD&1) && (PicoOpt & 0x2000)) SekCycleCnt=SekCycleAim-(c); else SekSetCyclesLeftNoMCD(c); \\r
	73	}\r
03e4f2a3	74	#define SekPc fm68k_get_pc(&PicoCpuFM68k)\r
03e4f2a3	75	#define SekPcS68k fm68k_get_pc(&PicoCpuFS68k)\r
70357ce5	76	#define SekSetStop(x) { \\r
03e4f2a3	77	PicoCpuFM68k.execinfo &= ~FM68K_HALTED; \\r
03e4f2a3	78	if (x) { PicoCpuFM68k.execinfo \|= FM68K_HALTED; PicoCpuFM68k.io_cycle_counter = 0; } \\r
70357ce5	79	}\r
70357ce5	80	#define SekSetStopS68k(x) { \\r
03e4f2a3	81	PicoCpuFS68k.execinfo &= ~FM68K_HALTED; \\r
03e4f2a3	82	if (x) { PicoCpuFS68k.execinfo \|= FM68K_HALTED; PicoCpuFS68k.io_cycle_counter = 0; } \\r
70357ce5	83	}\r
ca61ee42	84	#define SekIsStoppedS68k() (PicoCpuFS68k.execinfo&FM68K_HALTED)\r
03e4f2a3	85	#define SekShouldInterrupt fm68k_would_interrupt()\r
b542be46	86	\r
	87	#define SekInterrupt(irq) PicoCpuFM68k.interrupts[0]=irq\r
	88	\r
03e4f2a3	89	#ifdef EMU_M68K\r
	90	#define EMU_CORE_DEBUG\r
	91	#endif\r
cc68a136	92	#endif\r
	93	\r
	94	#ifdef EMU_M68K\r
	95	#include "../cpu/musashi/m68kcpu.h"\r
3aa1e148	96	extern m68ki_cpu_core PicoCpuMM68k, PicoCpuMS68k;\r
cc68a136	97	#ifndef SekCyclesLeft\r
3aa1e148	98	#define SekCyclesLeftNoMCD PicoCpuMM68k.cyc_remaining_cycles\r
7336a99a	99	#define SekCyclesLeft \\r
7336a99a	100	(((PicoMCD&1) && (PicoOpt & 0x2000)) ? (SekCycleAim-SekCycleCnt) : SekCyclesLeftNoMCD)\r
7a1f6e45	101	#define SekCyclesLeftS68k \\r
3aa1e148	102	((PicoOpt & 0x2000) ? (SekCycleAimS68k-SekCycleCntS68k) : PicoCpuMS68k.cyc_remaining_cycles)\r
7336a99a	103	#define SekSetCyclesLeftNoMCD(c) SET_CYCLES(c)\r
	104	#define SekSetCyclesLeft(c) { \\r
	105	if ((PicoMCD&1) && (PicoOpt & 0x2000)) SekCycleCnt=SekCycleAim-(c); else SET_CYCLES(c); \\r
	106	}\r
3aa1e148	107	#define SekPc m68k_get_reg(&PicoCpuMM68k, M68K_REG_PC)\r
3aa1e148	108	#define SekPcS68k m68k_get_reg(&PicoCpuMS68k, M68K_REG_PC)\r
7a1f6e45	109	#define SekSetStop(x) { \\r
3aa1e148	110	if(x) { SET_CYCLES(0); PicoCpuMM68k.stopped=STOP_LEVEL_STOP; } \\r
3aa1e148	111	else PicoCpuMM68k.stopped=0; \\r
7a1f6e45	112	}\r
7a1f6e45	113	#define SekSetStopS68k(x) { \\r
3aa1e148	114	if(x) { SET_CYCLES(0); PicoCpuMS68k.stopped=STOP_LEVEL_STOP; } \\r
3aa1e148	115	else PicoCpuMS68k.stopped=0; \\r
7a1f6e45	116	}\r
ca61ee42	117	#define SekIsStoppedS68k() (PicoCpuMS68k.stopped==STOP_LEVEL_STOP)\r
03e4f2a3	118	#define SekShouldInterrupt (CPU_INT_LEVEL > FLAG_INT_MASK)\r
b542be46	119	\r
71de3cd9	120	#define SekInterrupt(irq) { \\r
b542be46	121	void *oldcontext = m68ki_cpu_p; \\r
	122	m68k_set_context(&PicoCpuMM68k); \\r
	123	m68k_set_irq(irq); \\r
	124	m68k_set_context(oldcontext); \\r
	125	}\r
	126	\r
cc68a136	127	#endif\r
	128	#endif\r
	129	\r
	130	extern int SekCycleCnt; // cycles done in this frame\r
	131	extern int SekCycleAim; // cycle aim\r
	132	extern unsigned int SekCycleCntT; // total cycle counter, updated once per frame\r
	133	\r
b8cbd802	134	#define SekCyclesReset() { \\r
	135	SekCycleCntT+=SekCycleAim; \\r
	136	SekCycleCnt-=SekCycleAim; \\r
	137	SekCycleAim=0; \\r
	138	}\r
cc68a136	139	#define SekCyclesBurn(c) SekCycleCnt+=c\r
	140	#define SekCyclesDone() (SekCycleAim-SekCyclesLeft) // nuber of cycles done in this frame (can be checked anywhere)\r
	141	#define SekCyclesDoneT() (SekCycleCntT+SekCyclesDone()) // total nuber of cycles done for this rom\r
	142	\r
	143	#define SekEndRun(after) { \\r
	144	SekCycleCnt -= SekCyclesLeft - after; \\r
	145	if(SekCycleCnt < 0) SekCycleCnt = 0; \\r
	146	SekSetCyclesLeft(after); \\r
	147	}\r
	148	\r
	149	extern int SekCycleCntS68k;\r
	150	extern int SekCycleAimS68k;\r
	151	\r
bf5fbbb4	152	#define SekCyclesResetS68k() { \\r
	153	SekCycleCntS68k-=SekCycleAimS68k; \\r
	154	SekCycleAimS68k=0; \\r
	155	}\r
7a1f6e45	156	#define SekCyclesDoneS68k() (SekCycleAimS68k-SekCyclesLeftS68k)\r
cc68a136	157	\r
03e4f2a3	158	#ifdef EMU_CORE_DEBUG\r
2d0b15bb	159	#undef SekSetCyclesLeftNoMCD\r
	160	#undef SekSetCyclesLeft\r
	161	#undef SekCyclesBurn\r
	162	#undef SekEndRun\r
	163	#define SekSetCyclesLeftNoMCD(c)\r
	164	#define SekSetCyclesLeft(c)\r
2270612a	165	#define SekCyclesBurn(c) c\r
2d0b15bb	166	#define SekEndRun(c)\r
2d0b15bb	167	#endif\r
cc68a136	168	\r
b542be46	169	// ----------------------- Z80 CPU -----------------------\r
	170	\r
	171	#if defined(_USE_MZ80)\r
	172	#include "../../cpu/mz80/mz80.h"\r
	173	\r
	174	#define z80_run(cycles) mz80_run(cycles)\r
	175	#define z80_run_nr(cycles) mz80_run(cycles)\r
	176	#define z80_int() mz80int(0)\r
	177	#define z80_resetCycles() mz80GetElapsedTicks(1)\r
	178	\r
	179	#elif defined(_USE_DRZ80)\r
	180	#include "../../cpu/DrZ80/drz80.h"\r
	181	\r
	182	extern struct DrZ80 drZ80;\r
	183	\r
	184	#define z80_run(cycles) ((cycles) - DrZ80Run(&drZ80, cycles))\r
	185	#define z80_run_nr(cycles) DrZ80Run(&drZ80, cycles)\r
	186	#define z80_int() { \\r
	187	drZ80.z80irqvector = 0xFF; /* default IRQ vector RST opcode */ \\r
	188	drZ80.Z80_IRQ = 1; \\r
	189	}\r
	190	#define z80_resetCycles()\r
	191	\r
	192	#elif defined(_USE_CZ80)\r
	193	#include "../../cpu/cz80/cz80.h"\r
	194	\r
	195	#define z80_run(cycles) Cz80_Exec(&CZ80, cycles)\r
	196	#define z80_run_nr(cycles) Cz80_Exec(&CZ80, cycles)\r
	197	#define z80_int() Cz80_Set_IRQ(&CZ80, 0, HOLD_LINE)\r
	198	#define z80_resetCycles()\r
	199	\r
	200	#else\r
	201	\r
	202	#define z80_run(cycles) (cycles)\r
	203	#define z80_run_nr(cycles)\r
	204	#define z80_int()\r
	205	#define z80_resetCycles()\r
	206	\r
	207	#endif\r
	208	\r
cc68a136	209	// ---------------------------------------------------------\r
cc68a136	210	\r
70357ce5	211	extern int PicoMCD;\r
70357ce5	212	\r
cc68a136	213	// main oscillator clock which controls timing\r
cc68a136	214	#define OSC_NTSC 53693100\r
b8cbd802	215	// seems to be accurate, see scans from http://www.hot.ee/tmeeco/\r
b8cbd802	216	#define OSC_PAL 53203424\r
cc68a136	217	\r
	218	struct PicoVideo\r
	219	{\r
	220	unsigned char reg[0x20];\r
b8cbd802	221	unsigned int command; // 32-bit Command\r
	222	unsigned char pending; // 1 if waiting for second half of 32-bit command\r
	223	unsigned char type; // Command type (v/c/vsram read/write)\r
	224	unsigned short addr; // Read/Write address\r
	225	int status; // Status bits\r
cc68a136	226	unsigned char pending_ints; // pending interrupts: ??VH????\r
b8cbd802	227	signed char lwrite_cnt; // VDP write count during active display line\r
b8cbd802	228	unsigned char pad[0x12];\r
cc68a136	229	};\r
	230	\r
	231	struct PicoMisc\r
	232	{\r
	233	unsigned char rotate;\r
	234	unsigned char z80Run;\r
e5503e2f	235	unsigned char padTHPhase[2]; // 02 phase of gamepad TH switches\r
	236	short scanline; // 04 0 to 261\|\|311; -1 in fast mode\r
	237	char dirtyPal; // 06 Is the palette dirty (1 - change @ this frame, 2 - some time before)\r
	238	unsigned char hardware; // 07 Hardware value for country\r
	239	unsigned char pal; // 08 1=PAL 0=NTSC\r
	240	unsigned char sram_reg; // SRAM mode register. bit0: allow read? bit1: deny write? bit2: EEPROM? bit4: detected? (header or by access)\r
	241	unsigned short z80_bank68k; // 0a\r
cc68a136	242	unsigned short z80_lastaddr; // this is for Z80 faking\r
	243	unsigned char z80_fakeval;\r
	244	unsigned char pad0;\r
e5503e2f	245	unsigned char padDelay[2]; // 10 gamepad phase time outs, so we count a delay\r
1dceadae	246	unsigned short eeprom_addr; // EEPROM address register\r
	247	unsigned char eeprom_cycle; // EEPROM SRAM cycle number\r
	248	unsigned char eeprom_slave; // EEPROM slave word for X24C02 and better SRAMs\r
721cd396	249	unsigned char prot_bytes[2]; // simple protection faking\r
b8cbd802	250	unsigned short dma_xfers;\r
312e9ce1	251	unsigned char pad[2];\r
312e9ce1	252	unsigned int frame_count; // mainly for movies\r
cc68a136	253	};\r
	254	\r
	255	// some assembly stuff depend on these, do not touch!\r
	256	struct Pico\r
	257	{\r
	258	unsigned char ram[0x10000]; // 0x00000 scratch ram\r
	259	unsigned short vram[0x8000]; // 0x10000\r
	260	unsigned char zram[0x2000]; // 0x20000 Z80 ram\r
	261	unsigned char ioports[0x10];\r
	262	unsigned int pad[0x3c]; // unused\r
	263	unsigned short cram[0x40]; // 0x22100\r
	264	unsigned short vsram[0x40]; // 0x22180\r
	265	\r
	266	unsigned char *rom; // 0x22200\r
	267	unsigned int romsize; // 0x22204\r
	268	\r
	269	struct PicoMisc m;\r
	270	struct PicoVideo video;\r
	271	};\r
	272	\r
	273	// sram\r
	274	struct PicoSRAM\r
	275	{\r
4ff2d527	276	unsigned char *data; // actual data\r
4ff2d527	277	unsigned int start; // start address in 68k address space\r
cc68a136	278	unsigned int end;\r
1dceadae	279	unsigned char unused1; // 0c: unused\r
1dceadae	280	unsigned char unused2;\r
cc68a136	281	unsigned char changed;\r
1dceadae	282	unsigned char eeprom_type; // eeprom type: 0: 7bit (24C01), 2: device with 2 addr words (X24C02+), 3: dev with 3 addr words\r
	283	unsigned char eeprom_abits; // eeprom access must be odd addr for: bit0 ~ cl, bit1 ~ out\r
	284	unsigned char eeprom_bit_cl; // bit number for cl\r
	285	unsigned char eeprom_bit_in; // bit number for in\r
	286	unsigned char eeprom_bit_out; // bit number for out\r
cc68a136	287	};\r
	288	\r
	289	// MCD\r
	290	#include "cd/cd_sys.h"\r
	291	#include "cd/LC89510.h"\r
d1df8786	292	#include "cd/gfx_cd.h"\r
cc68a136	293	\r
4f265db7	294	struct mcd_pcm\r
	295	{\r
	296	unsigned char control; // reg7\r
	297	unsigned char enabled; // reg8\r
	298	unsigned char cur_ch;\r
	299	unsigned char bank;\r
	300	int pad1;\r
	301	\r
4ff2d527	302	struct pcm_chan // 08, size 0x10\r
4f265db7	303	{\r
4f265db7	304	unsigned char regs[8];\r
4ff2d527	305	unsigned int addr; // .08: played sample address\r
4f265db7	306	int pad;\r
	307	} ch[8];\r
	308	};\r
	309	\r
c459aefd	310	struct mcd_misc\r
	311	{\r
	312	unsigned short hint_vector;\r
	313	unsigned char busreq;\r
51a902ae	314	unsigned char s68k_pend_ints;\r
89fa852d	315	unsigned int state_flags; // 04: emu state: reset_pending, dmna_pending\r
51a902ae	316	unsigned int counter75hz;\r
4ff2d527	317	unsigned short audio_offset; // 0c: for savestates: play pointer offset (0-1023)\r
75736070	318	unsigned char audio_track; // playing audio track # (zero based)\r
6cadc2da	319	char pad1;\r
4ff2d527	320	int timer_int3; // 10\r
4f265db7	321	unsigned int timer_stopwatch;\r
6cadc2da	322	unsigned char bcram_reg; // 18: battery-backed RAM cart register\r
	323	unsigned char pad2;\r
	324	unsigned short pad3;\r
	325	int pad[9];\r
c459aefd	326	};\r
c459aefd	327	\r
cc68a136	328	typedef struct\r
cc68a136	329	{\r
4ff2d527	330	unsigned char bios[0x20000]; // 000000: 128K\r
4ff2d527	331	union { // 020000: 512K\r
fa1e5e29	332	unsigned char prg_ram[0x80000];\r
cc68a136	333	unsigned char prg_ram_b[4][0x20000];\r
cc68a136	334	};\r
4ff2d527	335	union { // 0a0000: 256K\r
fa1e5e29	336	struct {\r
	337	unsigned char word_ram2M[0x40000];\r
	338	unsigned char unused[0x20000];\r
	339	};\r
	340	struct {\r
	341	unsigned char unused[0x20000];\r
	342	unsigned char word_ram1M[2][0x20000];\r
	343	};\r
	344	};\r
4ff2d527	345	union { // 100000: 64K\r
fa1e5e29	346	unsigned char pcm_ram[0x10000];\r
4f265db7	347	unsigned char pcm_ram_b[0x10][0x1000];\r
4f265db7	348	};\r
4ff2d527	349	unsigned char s68k_regs[0x200]; // 110000: GA, not CPU regs\r
	350	unsigned char bram[0x2000]; // 110200: 8K\r
	351	struct mcd_misc m; // 112200: misc\r
	352	struct mcd_pcm pcm; // 112240:\r
75736070	353	_scd_toc TOC; // not to be saved\r
cc68a136	354	CDD cdd;\r
	355	CDC cdc;\r
	356	_scd scd;\r
d1df8786	357	Rot_Comp rot_comp;\r
cc68a136	358	} mcd_state;\r
	359	\r
	360	#define Pico_mcd ((mcd_state *)Pico.rom)\r
	361	\r
51a902ae	362	// Area.c\r
eff55556	363	PICO_INTERNAL int PicoAreaPackCpu(unsigned char *cpu, int is_sub);\r
eff55556	364	PICO_INTERNAL int PicoAreaUnpackCpu(unsigned char *cpu, int is_sub);\r
51a902ae	365	\r
51a902ae	366	// cd/Area.c\r
eff55556	367	PICO_INTERNAL int PicoCdSaveState(void *file);\r
eff55556	368	PICO_INTERNAL int PicoCdLoadState(void *file);\r
cc68a136	369	\r
1dceadae	370	// Cart.c\r
	371	PICO_INTERNAL void PicoCartDetect(void);\r
	372	\r
03e4f2a3	373	// Debug.c\r
b5e5172d	374	int CM_compareRun(int cyc, int is_sub);\r
03e4f2a3	375	\r
cc68a136	376	// Draw.c\r
eff55556	377	PICO_INTERNAL int PicoLine(int scan);\r
eff55556	378	PICO_INTERNAL void PicoFrameStart(void);\r
cc68a136	379	\r
cc68a136	380	// Draw2.c\r
eff55556	381	PICO_INTERNAL void PicoFrameFull();\r
cc68a136	382	\r
cc68a136	383	// Memory.c\r
eff55556	384	PICO_INTERNAL int PicoInitPc(unsigned int pc);\r
8ab3e3c1	385	PICO_INTERNAL_ASM unsigned int PicoRead32(unsigned int a);\r
eff55556	386	PICO_INTERNAL void PicoMemSetup(void);\r
eff55556	387	PICO_INTERNAL_ASM void PicoMemReset(void);\r
f8ef8ff7	388	PICO_INTERNAL void PicoMemResetHooks(void);\r
e5503e2f	389	PICO_INTERNAL int PadRead(int i);\r
eff55556	390	PICO_INTERNAL unsigned char z80_read(unsigned short a);\r
a4221917	391	#ifndef _USE_CZ80\r
eff55556	392	PICO_INTERNAL_ASM void z80_write(unsigned char data, unsigned short a);\r
eff55556	393	PICO_INTERNAL void z80_write16(unsigned short data, unsigned short a);\r
a4221917	394	PICO_INTERNAL unsigned short z80_read16(unsigned short a);\r
	395	#else\r
	396	PICO_INTERNAL_ASM void z80_write(unsigned int a, unsigned char data);\r
	397	#endif\r
f53f286a	398	extern unsigned int (*PicoRead16Hook)(unsigned int a, int realsize);\r
f8ef8ff7	399	extern void (*PicoWrite8Hook) (unsigned int a,unsigned int d,int realsize);\r
f8ef8ff7	400	extern void (*PicoWrite16Hook)(unsigned int a,unsigned int d,int realsize);\r
cc68a136	401	\r
cc68a136	402	// cd/Memory.c\r
eff55556	403	PICO_INTERNAL void PicoMemSetupCD(void);\r
	404	PICO_INTERNAL_ASM void PicoMemResetCD(int r3);\r
	405	PICO_INTERNAL_ASM void PicoMemResetCDdecode(int r3);\r
cc68a136	406	\r
	407	// Pico.c\r
	408	extern struct Pico Pico;\r
	409	extern struct PicoSRAM SRam;\r
	410	extern int emustatus;\r
d9153729	411	extern int z80startCycle, z80stopCycle; // in 68k cycles\r
f8ef8ff7	412	extern void (*PicoResetHook)(void);\r
017512f2	413	extern void (*PicoLineHook)(void);\r
eff55556	414	PICO_INTERNAL int CheckDMA(void);\r
cc68a136	415	\r
cc68a136	416	// cd/Pico.c\r
e5f426aa	417	PICO_INTERNAL int PicoInitMCD(void);\r
e5f426aa	418	PICO_INTERNAL void PicoExitMCD(void);\r
eff55556	419	PICO_INTERNAL int PicoResetMCD(int hard);\r
eff55556	420	PICO_INTERNAL int PicoFrameMCD(void);\r
cc68a136	421	\r
cc68a136	422	// Sek.c\r
eff55556	423	PICO_INTERNAL int SekInit(void);\r
eff55556	424	PICO_INTERNAL int SekReset(void);\r
3aa1e148	425	PICO_INTERNAL void SekState(int *data);\r
eff55556	426	PICO_INTERNAL void SekSetRealTAS(int use_real);\r
cc68a136	427	\r
cc68a136	428	// cd/Sek.c\r
eff55556	429	PICO_INTERNAL int SekInitS68k(void);\r
	430	PICO_INTERNAL int SekResetS68k(void);\r
	431	PICO_INTERNAL int SekInterruptS68k(int irq);\r
cc68a136	432	\r
7a93adeb	433	// sound/sound.c\r
	434	extern int PsndLen_exc_cnt;\r
	435	extern int PsndLen_exc_add;\r
	436	\r
cc68a136	437	// VideoPort.c\r
eff55556	438	PICO_INTERNAL_ASM void PicoVideoWrite(unsigned int a,unsigned short d);\r
eff55556	439	PICO_INTERNAL_ASM unsigned int PicoVideoRead(unsigned int a);\r
5de27868	440	extern int (PicoDmaHook)(unsigned int source, int len, unsigned short srcp, unsigned short *limitp);\r
cc68a136	441	\r
cc68a136	442	// Misc.c\r
eff55556	443	PICO_INTERNAL void SRAMWriteEEPROM(unsigned int d);\r
	444	PICO_INTERNAL void SRAMUpdPending(unsigned int a, unsigned int d);\r
	445	PICO_INTERNAL_ASM unsigned int SRAMReadEEPROM(void);\r
	446	PICO_INTERNAL_ASM void memcpy16(unsigned short dest, unsigned short src, int count);\r
	447	PICO_INTERNAL_ASM void memcpy16bswap(unsigned short dest, void src, int count);\r
	448	PICO_INTERNAL_ASM void memcpy32(int dest, int src, int count); // 32bit word count\r
	449	PICO_INTERNAL_ASM void memset32(int *dest, int c, int count);\r
cc68a136	450	\r
fa1e5e29	451	// cd/Misc.c\r
eff55556	452	PICO_INTERNAL_ASM void wram_2M_to_1M(unsigned char *m);\r
	453	PICO_INTERNAL_ASM void wram_1M_to_2M(unsigned char *m);\r
	454	\r
	455	// cd/buffering.c\r
	456	PICO_INTERNAL void PicoCDBufferRead(void *dest, int lba);\r
	457	\r
	458	// sound/sound.c\r
9d917eea	459	PICO_INTERNAL void PsndReset(void);\r
	460	PICO_INTERNAL void Psnd_timers_and_dac(int raster);\r
	461	PICO_INTERNAL int PsndRender(int offset, int length);\r
	462	PICO_INTERNAL void PsndClear(void);\r
eff55556	463	// z80 functionality wrappers\r
eff55556	464	PICO_INTERNAL void z80_init(void);\r
eff55556	465	PICO_INTERNAL void z80_pack(unsigned char *data);\r
	466	PICO_INTERNAL void z80_unpack(unsigned char *data);\r
	467	PICO_INTERNAL void z80_reset(void);\r
	468	PICO_INTERNAL void z80_exit(void);\r
fa1e5e29	469	\r
cc68a136	470	\r
	471	#ifdef __cplusplus\r
	472	} // End of extern "C"\r
	473	#endif\r
eff55556	474	\r
b8cbd802	475	// emulation event logging\r
	476	#ifndef EL_LOGMASK\r
	477	#define EL_LOGMASK 0\r
	478	#endif\r
	479	\r
017512f2	480	#define EL_HVCNT 0x00000001 /* hv counter reads */\r
	481	#define EL_SR 0x00000002 /* SR reads */\r
	482	#define EL_INTS 0x00000004 /* ints and acks */\r
	483	#define EL_YM2612R 0x00000008 /* 68k ym2612 reads */\r
	484	#define EL_INTSW 0x00000010 /* log irq switching on/off */\r
	485	#define EL_ASVDP 0x00000020 /* VDP accesses during active scan */\r
	486	#define EL_VDPDMA 0x00000040 /* VDP DMA transfers and their timing */\r
	487	#define EL_BUSREQ 0x00000080 /* z80 busreq r/w or reset w */\r
	488	#define EL_Z80BNK 0x00000100 /* z80 i/o through bank area */\r
	489	#define EL_SRAMIO 0x00000200 /* sram i/o */\r
	490	#define EL_EEPROM 0x00000400 /* eeprom debug */\r
	491	#define EL_UIO 0x00000800 /* unmapped i/o */\r
	492	#define EL_IO 0x00001000 /* all i/o */\r
	493	#define EL_CDPOLL 0x00002000 /* MCD: log poll detection */\r
	494	#define EL_SVP 0x00004000 /* SVP stuff */\r
	495	\r
	496	#define EL_STATUS 0x40000000 /* status messages */\r
	497	#define EL_ANOMALY 0x80000000 /* some unexpected conditions (during emulation) */\r
b8cbd802	498	\r
b8cbd802	499	#if EL_LOGMASK\r
7d0143a2	500	extern void lprintf(const char *fmt, ...);\r
b8cbd802	501	#define elprintf(w,f,...) \\r
	502	{ \\r
	503	if ((w) & EL_LOGMASK) \\r
7d0143a2	504	lprintf("%05i:%03i: " f "\n",Pico.m.frame_count,Pico.m.scanline,##__VA_ARGS__); \\r
b8cbd802	505	}\r
	506	#else\r
	507	#define elprintf(w,f,...)\r
	508	#endif\r
	509	\r
eff55556	510	#endif // PICO_INTERNAL_INCLUDED\r
eff55556	511	\r