drc: rm unneeded writebacks in stubs, as suggested by Ari64
[pcsx_rearmed.git] / libpcsxcore / new_dynarec / new_dynarec.c
CommitLineData
57871462 1/* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
2 * Mupen64plus - new_dynarec.c *
3 * Copyright (C) 2009-2010 Ari64 *
4 * *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
9 * *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
14 * *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. *
19 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */
20
21#include <stdlib.h>
22#include <stdint.h> //include for uint64_t
23#include <assert.h>
24
3d624f89 25#include "emu_if.h" //emulator interface
57871462 26
27#include <sys/mman.h>
28
29#ifdef __i386__
30#include "assem_x86.h"
31#endif
32#ifdef __x86_64__
33#include "assem_x64.h"
34#endif
35#ifdef __arm__
36#include "assem_arm.h"
37#endif
38
39#define MAXBLOCK 4096
40#define MAX_OUTPUT_BLOCK_SIZE 262144
41#define CLOCK_DIVIDER 2
42
43struct regstat
44{
45 signed char regmap_entry[HOST_REGS];
46 signed char regmap[HOST_REGS];
47 uint64_t was32;
48 uint64_t is32;
49 uint64_t wasdirty;
50 uint64_t dirty;
51 uint64_t u;
52 uint64_t uu;
53 u_int wasconst;
54 u_int isconst;
55 uint64_t constmap[HOST_REGS];
56};
57
58struct ll_entry
59{
60 u_int vaddr;
61 u_int reg32;
62 void *addr;
63 struct ll_entry *next;
64};
65
66 u_int start;
67 u_int *source;
68 u_int pagelimit;
69 char insn[MAXBLOCK][10];
70 u_char itype[MAXBLOCK];
71 u_char opcode[MAXBLOCK];
72 u_char opcode2[MAXBLOCK];
73 u_char bt[MAXBLOCK];
74 u_char rs1[MAXBLOCK];
75 u_char rs2[MAXBLOCK];
76 u_char rt1[MAXBLOCK];
77 u_char rt2[MAXBLOCK];
78 u_char us1[MAXBLOCK];
79 u_char us2[MAXBLOCK];
80 u_char dep1[MAXBLOCK];
81 u_char dep2[MAXBLOCK];
82 u_char lt1[MAXBLOCK];
83 int imm[MAXBLOCK];
84 u_int ba[MAXBLOCK];
85 char likely[MAXBLOCK];
86 char is_ds[MAXBLOCK];
e1190b87 87 char ooo[MAXBLOCK];
57871462 88 uint64_t unneeded_reg[MAXBLOCK];
89 uint64_t unneeded_reg_upper[MAXBLOCK];
90 uint64_t branch_unneeded_reg[MAXBLOCK];
91 uint64_t branch_unneeded_reg_upper[MAXBLOCK];
92 uint64_t p32[MAXBLOCK];
93 uint64_t pr32[MAXBLOCK];
94 signed char regmap_pre[MAXBLOCK][HOST_REGS];
95 signed char regmap[MAXBLOCK][HOST_REGS];
96 signed char regmap_entry[MAXBLOCK][HOST_REGS];
97 uint64_t constmap[MAXBLOCK][HOST_REGS];
57871462 98 struct regstat regs[MAXBLOCK];
99 struct regstat branch_regs[MAXBLOCK];
e1190b87 100 signed char minimum_free_regs[MAXBLOCK];
57871462 101 u_int needed_reg[MAXBLOCK];
102 uint64_t requires_32bit[MAXBLOCK];
103 u_int wont_dirty[MAXBLOCK];
104 u_int will_dirty[MAXBLOCK];
105 int ccadj[MAXBLOCK];
106 int slen;
107 u_int instr_addr[MAXBLOCK];
108 u_int link_addr[MAXBLOCK][3];
109 int linkcount;
110 u_int stubs[MAXBLOCK*3][8];
111 int stubcount;
112 u_int literals[1024][2];
113 int literalcount;
114 int is_delayslot;
115 int cop1_usable;
116 u_char *out;
117 struct ll_entry *jump_in[4096];
118 struct ll_entry *jump_out[4096];
119 struct ll_entry *jump_dirty[4096];
120 u_int hash_table[65536][4] __attribute__((aligned(16)));
121 char shadow[1048576] __attribute__((aligned(16)));
122 void *copy;
123 int expirep;
124 u_int using_tlb;
125 u_int stop_after_jal;
126 extern u_char restore_candidate[512];
127 extern int cycle_count;
128
129 /* registers that may be allocated */
130 /* 1-31 gpr */
131#define HIREG 32 // hi
132#define LOREG 33 // lo
133#define FSREG 34 // FPU status (FCSR)
134#define CSREG 35 // Coprocessor status
135#define CCREG 36 // Cycle count
136#define INVCP 37 // Pointer to invalid_code
619e5ded 137#define MMREG 38 // Pointer to memory_map
138#define ROREG 39 // ram offset (if rdram!=0x80000000)
139#define TEMPREG 40
140#define FTEMP 40 // FPU temporary register
141#define PTEMP 41 // Prefetch temporary register
142#define TLREG 42 // TLB mapping offset
143#define RHASH 43 // Return address hash
144#define RHTBL 44 // Return address hash table address
145#define RTEMP 45 // JR/JALR address register
146#define MAXREG 45
147#define AGEN1 46 // Address generation temporary register
148#define AGEN2 47 // Address generation temporary register
149#define MGEN1 48 // Maptable address generation temporary register
150#define MGEN2 49 // Maptable address generation temporary register
151#define BTREG 50 // Branch target temporary register
57871462 152
153 /* instruction types */
154#define NOP 0 // No operation
155#define LOAD 1 // Load
156#define STORE 2 // Store
157#define LOADLR 3 // Unaligned load
158#define STORELR 4 // Unaligned store
159#define MOV 5 // Move
160#define ALU 6 // Arithmetic/logic
161#define MULTDIV 7 // Multiply/divide
162#define SHIFT 8 // Shift by register
163#define SHIFTIMM 9// Shift by immediate
164#define IMM16 10 // 16-bit immediate
165#define RJUMP 11 // Unconditional jump to register
166#define UJUMP 12 // Unconditional jump
167#define CJUMP 13 // Conditional branch (BEQ/BNE/BGTZ/BLEZ)
168#define SJUMP 14 // Conditional branch (regimm format)
169#define COP0 15 // Coprocessor 0
170#define COP1 16 // Coprocessor 1
171#define C1LS 17 // Coprocessor 1 load/store
172#define FJUMP 18 // Conditional branch (floating point)
173#define FLOAT 19 // Floating point unit
174#define FCONV 20 // Convert integer to float
175#define FCOMP 21 // Floating point compare (sets FSREG)
176#define SYSCALL 22// SYSCALL
177#define OTHER 23 // Other
178#define SPAN 24 // Branch/delay slot spans 2 pages
179#define NI 25 // Not implemented
7139f3c8 180#define HLECALL 26// PCSX fake opcodes for HLE
b9b61529 181#define COP2 27 // Coprocessor 2 move
182#define C2LS 28 // Coprocessor 2 load/store
183#define C2OP 29 // Coprocessor 2 operation
1e973cb0 184#define INTCALL 30// Call interpreter to handle rare corner cases
57871462 185
186 /* stubs */
187#define CC_STUB 1
188#define FP_STUB 2
189#define LOADB_STUB 3
190#define LOADH_STUB 4
191#define LOADW_STUB 5
192#define LOADD_STUB 6
193#define LOADBU_STUB 7
194#define LOADHU_STUB 8
195#define STOREB_STUB 9
196#define STOREH_STUB 10
197#define STOREW_STUB 11
198#define STORED_STUB 12
199#define STORELR_STUB 13
200#define INVCODE_STUB 14
201
202 /* branch codes */
203#define TAKEN 1
204#define NOTTAKEN 2
205#define NULLDS 3
206
207// asm linkage
208int new_recompile_block(int addr);
209void *get_addr_ht(u_int vaddr);
210void invalidate_block(u_int block);
211void invalidate_addr(u_int addr);
212void remove_hash(int vaddr);
213void jump_vaddr();
214void dyna_linker();
215void dyna_linker_ds();
216void verify_code();
217void verify_code_vm();
218void verify_code_ds();
219void cc_interrupt();
220void fp_exception();
221void fp_exception_ds();
222void jump_syscall();
7139f3c8 223void jump_syscall_hle();
57871462 224void jump_eret();
7139f3c8 225void jump_hlecall();
1e973cb0 226void jump_intcall();
7139f3c8 227void new_dyna_leave();
57871462 228
229// TLB
230void TLBWI_new();
231void TLBWR_new();
232void read_nomem_new();
233void read_nomemb_new();
234void read_nomemh_new();
235void read_nomemd_new();
236void write_nomem_new();
237void write_nomemb_new();
238void write_nomemh_new();
239void write_nomemd_new();
240void write_rdram_new();
241void write_rdramb_new();
242void write_rdramh_new();
243void write_rdramd_new();
244extern u_int memory_map[1048576];
245
246// Needed by assembler
247void wb_register(signed char r,signed char regmap[],uint64_t dirty,uint64_t is32);
248void wb_dirtys(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty);
249void wb_needed_dirtys(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr);
250void load_all_regs(signed char i_regmap[]);
251void load_needed_regs(signed char i_regmap[],signed char next_regmap[]);
252void load_regs_entry(int t);
253void load_all_consts(signed char regmap[],int is32,u_int dirty,int i);
254
255int tracedebug=0;
256
257//#define DEBUG_CYCLE_COUNT 1
258
259void nullf() {}
260//#define assem_debug printf
261//#define inv_debug printf
262#define assem_debug nullf
263#define inv_debug nullf
264
94d23bb9 265static void tlb_hacks()
57871462 266{
94d23bb9 267#ifndef DISABLE_TLB
57871462 268 // Goldeneye hack
269 if (strncmp((char *) ROM_HEADER->nom, "GOLDENEYE",9) == 0)
270 {
271 u_int addr;
272 int n;
273 switch (ROM_HEADER->Country_code&0xFF)
274 {
275 case 0x45: // U
276 addr=0x34b30;
277 break;
278 case 0x4A: // J
279 addr=0x34b70;
280 break;
281 case 0x50: // E
282 addr=0x329f0;
283 break;
284 default:
285 // Unknown country code
286 addr=0;
287 break;
288 }
289 u_int rom_addr=(u_int)rom;
290 #ifdef ROM_COPY
291 // Since memory_map is 32-bit, on 64-bit systems the rom needs to be
292 // in the lower 4G of memory to use this hack. Copy it if necessary.
293 if((void *)rom>(void *)0xffffffff) {
294 munmap(ROM_COPY, 67108864);
295 if(mmap(ROM_COPY, 12582912,
296 PROT_READ | PROT_WRITE,
297 MAP_FIXED | MAP_PRIVATE | MAP_ANONYMOUS,
298 -1, 0) <= 0) {printf("mmap() failed\n");}
299 memcpy(ROM_COPY,rom,12582912);
300 rom_addr=(u_int)ROM_COPY;
301 }
302 #endif
303 if(addr) {
304 for(n=0x7F000;n<0x80000;n++) {
305 memory_map[n]=(((u_int)(rom_addr+addr-0x7F000000))>>2)|0x40000000;
306 }
307 }
308 }
94d23bb9 309#endif
57871462 310}
311
94d23bb9 312static u_int get_page(u_int vaddr)
57871462 313{
0ce47d46 314#ifndef PCSX
57871462 315 u_int page=(vaddr^0x80000000)>>12;
0ce47d46 316#else
317 u_int page=vaddr&~0xe0000000;
318 if (page < 0x1000000)
319 page &= ~0x0e00000; // RAM mirrors
320 page>>=12;
321#endif
94d23bb9 322#ifndef DISABLE_TLB
57871462 323 if(page>262143&&tlb_LUT_r[vaddr>>12]) page=(tlb_LUT_r[vaddr>>12]^0x80000000)>>12;
94d23bb9 324#endif
57871462 325 if(page>2048) page=2048+(page&2047);
94d23bb9 326 return page;
327}
328
329static u_int get_vpage(u_int vaddr)
330{
331 u_int vpage=(vaddr^0x80000000)>>12;
332#ifndef DISABLE_TLB
57871462 333 if(vpage>262143&&tlb_LUT_r[vaddr>>12]) vpage&=2047; // jump_dirty uses a hash of the virtual address instead
94d23bb9 334#endif
57871462 335 if(vpage>2048) vpage=2048+(vpage&2047);
94d23bb9 336 return vpage;
337}
338
339// Get address from virtual address
340// This is called from the recompiled JR/JALR instructions
341void *get_addr(u_int vaddr)
342{
343 u_int page=get_page(vaddr);
344 u_int vpage=get_vpage(vaddr);
57871462 345 struct ll_entry *head;
346 //printf("TRACE: count=%d next=%d (get_addr %x,page %d)\n",Count,next_interupt,vaddr,page);
347 head=jump_in[page];
348 while(head!=NULL) {
349 if(head->vaddr==vaddr&&head->reg32==0) {
350 //printf("TRACE: count=%d next=%d (get_addr match %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr);
351 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
352 ht_bin[3]=ht_bin[1];
353 ht_bin[2]=ht_bin[0];
354 ht_bin[1]=(int)head->addr;
355 ht_bin[0]=vaddr;
356 return head->addr;
357 }
358 head=head->next;
359 }
360 head=jump_dirty[vpage];
361 while(head!=NULL) {
362 if(head->vaddr==vaddr&&head->reg32==0) {
363 //printf("TRACE: count=%d next=%d (get_addr match dirty %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr);
364 // Don't restore blocks which are about to expire from the cache
365 if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
366 if(verify_dirty(head->addr)) {
367 //printf("restore candidate: %x (%d) d=%d\n",vaddr,page,invalid_code[vaddr>>12]);
368 invalid_code[vaddr>>12]=0;
369 memory_map[vaddr>>12]|=0x40000000;
370 if(vpage<2048) {
94d23bb9 371#ifndef DISABLE_TLB
57871462 372 if(tlb_LUT_r[vaddr>>12]) {
373 invalid_code[tlb_LUT_r[vaddr>>12]>>12]=0;
374 memory_map[tlb_LUT_r[vaddr>>12]>>12]|=0x40000000;
375 }
94d23bb9 376#endif
57871462 377 restore_candidate[vpage>>3]|=1<<(vpage&7);
378 }
379 else restore_candidate[page>>3]|=1<<(page&7);
380 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
381 if(ht_bin[0]==vaddr) {
382 ht_bin[1]=(int)head->addr; // Replace existing entry
383 }
384 else
385 {
386 ht_bin[3]=ht_bin[1];
387 ht_bin[2]=ht_bin[0];
388 ht_bin[1]=(int)head->addr;
389 ht_bin[0]=vaddr;
390 }
391 return head->addr;
392 }
393 }
394 head=head->next;
395 }
396 //printf("TRACE: count=%d next=%d (get_addr no-match %x)\n",Count,next_interupt,vaddr);
397 int r=new_recompile_block(vaddr);
398 if(r==0) return get_addr(vaddr);
399 // Execute in unmapped page, generate pagefault execption
400 Status|=2;
401 Cause=(vaddr<<31)|0x8;
402 EPC=(vaddr&1)?vaddr-5:vaddr;
403 BadVAddr=(vaddr&~1);
404 Context=(Context&0xFF80000F)|((BadVAddr>>9)&0x007FFFF0);
405 EntryHi=BadVAddr&0xFFFFE000;
406 return get_addr_ht(0x80000000);
407}
408// Look up address in hash table first
409void *get_addr_ht(u_int vaddr)
410{
411 //printf("TRACE: count=%d next=%d (get_addr_ht %x)\n",Count,next_interupt,vaddr);
412 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
413 if(ht_bin[0]==vaddr) return (void *)ht_bin[1];
414 if(ht_bin[2]==vaddr) return (void *)ht_bin[3];
415 return get_addr(vaddr);
416}
417
418void *get_addr_32(u_int vaddr,u_int flags)
419{
7139f3c8 420#ifdef FORCE32
421 return get_addr(vaddr);
560e4a12 422#else
57871462 423 //printf("TRACE: count=%d next=%d (get_addr_32 %x,flags %x)\n",Count,next_interupt,vaddr,flags);
424 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
425 if(ht_bin[0]==vaddr) return (void *)ht_bin[1];
426 if(ht_bin[2]==vaddr) return (void *)ht_bin[3];
94d23bb9 427 u_int page=get_page(vaddr);
428 u_int vpage=get_vpage(vaddr);
57871462 429 struct ll_entry *head;
430 head=jump_in[page];
431 while(head!=NULL) {
432 if(head->vaddr==vaddr&&(head->reg32&flags)==0) {
433 //printf("TRACE: count=%d next=%d (get_addr_32 match %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr);
434 if(head->reg32==0) {
435 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
436 if(ht_bin[0]==-1) {
437 ht_bin[1]=(int)head->addr;
438 ht_bin[0]=vaddr;
439 }else if(ht_bin[2]==-1) {
440 ht_bin[3]=(int)head->addr;
441 ht_bin[2]=vaddr;
442 }
443 //ht_bin[3]=ht_bin[1];
444 //ht_bin[2]=ht_bin[0];
445 //ht_bin[1]=(int)head->addr;
446 //ht_bin[0]=vaddr;
447 }
448 return head->addr;
449 }
450 head=head->next;
451 }
452 head=jump_dirty[vpage];
453 while(head!=NULL) {
454 if(head->vaddr==vaddr&&(head->reg32&flags)==0) {
455 //printf("TRACE: count=%d next=%d (get_addr_32 match dirty %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr);
456 // Don't restore blocks which are about to expire from the cache
457 if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
458 if(verify_dirty(head->addr)) {
459 //printf("restore candidate: %x (%d) d=%d\n",vaddr,page,invalid_code[vaddr>>12]);
460 invalid_code[vaddr>>12]=0;
461 memory_map[vaddr>>12]|=0x40000000;
462 if(vpage<2048) {
94d23bb9 463#ifndef DISABLE_TLB
57871462 464 if(tlb_LUT_r[vaddr>>12]) {
465 invalid_code[tlb_LUT_r[vaddr>>12]>>12]=0;
466 memory_map[tlb_LUT_r[vaddr>>12]>>12]|=0x40000000;
467 }
94d23bb9 468#endif
57871462 469 restore_candidate[vpage>>3]|=1<<(vpage&7);
470 }
471 else restore_candidate[page>>3]|=1<<(page&7);
472 if(head->reg32==0) {
473 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
474 if(ht_bin[0]==-1) {
475 ht_bin[1]=(int)head->addr;
476 ht_bin[0]=vaddr;
477 }else if(ht_bin[2]==-1) {
478 ht_bin[3]=(int)head->addr;
479 ht_bin[2]=vaddr;
480 }
481 //ht_bin[3]=ht_bin[1];
482 //ht_bin[2]=ht_bin[0];
483 //ht_bin[1]=(int)head->addr;
484 //ht_bin[0]=vaddr;
485 }
486 return head->addr;
487 }
488 }
489 head=head->next;
490 }
491 //printf("TRACE: count=%d next=%d (get_addr_32 no-match %x,flags %x)\n",Count,next_interupt,vaddr,flags);
492 int r=new_recompile_block(vaddr);
493 if(r==0) return get_addr(vaddr);
494 // Execute in unmapped page, generate pagefault execption
495 Status|=2;
496 Cause=(vaddr<<31)|0x8;
497 EPC=(vaddr&1)?vaddr-5:vaddr;
498 BadVAddr=(vaddr&~1);
499 Context=(Context&0xFF80000F)|((BadVAddr>>9)&0x007FFFF0);
500 EntryHi=BadVAddr&0xFFFFE000;
501 return get_addr_ht(0x80000000);
560e4a12 502#endif
57871462 503}
504
505void clear_all_regs(signed char regmap[])
506{
507 int hr;
508 for (hr=0;hr<HOST_REGS;hr++) regmap[hr]=-1;
509}
510
511signed char get_reg(signed char regmap[],int r)
512{
513 int hr;
514 for (hr=0;hr<HOST_REGS;hr++) if(hr!=EXCLUDE_REG&&regmap[hr]==r) return hr;
515 return -1;
516}
517
518// Find a register that is available for two consecutive cycles
519signed char get_reg2(signed char regmap1[],signed char regmap2[],int r)
520{
521 int hr;
522 for (hr=0;hr<HOST_REGS;hr++) if(hr!=EXCLUDE_REG&&regmap1[hr]==r&&regmap2[hr]==r) return hr;
523 return -1;
524}
525
526int count_free_regs(signed char regmap[])
527{
528 int count=0;
529 int hr;
530 for(hr=0;hr<HOST_REGS;hr++)
531 {
532 if(hr!=EXCLUDE_REG) {
533 if(regmap[hr]<0) count++;
534 }
535 }
536 return count;
537}
538
539void dirty_reg(struct regstat *cur,signed char reg)
540{
541 int hr;
542 if(!reg) return;
543 for (hr=0;hr<HOST_REGS;hr++) {
544 if((cur->regmap[hr]&63)==reg) {
545 cur->dirty|=1<<hr;
546 }
547 }
548}
549
550// If we dirty the lower half of a 64 bit register which is now being
551// sign-extended, we need to dump the upper half.
552// Note: Do this only after completion of the instruction, because
553// some instructions may need to read the full 64-bit value even if
554// overwriting it (eg SLTI, DSRA32).
555static void flush_dirty_uppers(struct regstat *cur)
556{
557 int hr,reg;
558 for (hr=0;hr<HOST_REGS;hr++) {
559 if((cur->dirty>>hr)&1) {
560 reg=cur->regmap[hr];
561 if(reg>=64)
562 if((cur->is32>>(reg&63))&1) cur->regmap[hr]=-1;
563 }
564 }
565}
566
567void set_const(struct regstat *cur,signed char reg,uint64_t value)
568{
569 int hr;
570 if(!reg) return;
571 for (hr=0;hr<HOST_REGS;hr++) {
572 if(cur->regmap[hr]==reg) {
573 cur->isconst|=1<<hr;
574 cur->constmap[hr]=value;
575 }
576 else if((cur->regmap[hr]^64)==reg) {
577 cur->isconst|=1<<hr;
578 cur->constmap[hr]=value>>32;
579 }
580 }
581}
582
583void clear_const(struct regstat *cur,signed char reg)
584{
585 int hr;
586 if(!reg) return;
587 for (hr=0;hr<HOST_REGS;hr++) {
588 if((cur->regmap[hr]&63)==reg) {
589 cur->isconst&=~(1<<hr);
590 }
591 }
592}
593
594int is_const(struct regstat *cur,signed char reg)
595{
596 int hr;
597 if(!reg) return 1;
598 for (hr=0;hr<HOST_REGS;hr++) {
599 if((cur->regmap[hr]&63)==reg) {
600 return (cur->isconst>>hr)&1;
601 }
602 }
603 return 0;
604}
605uint64_t get_const(struct regstat *cur,signed char reg)
606{
607 int hr;
608 if(!reg) return 0;
609 for (hr=0;hr<HOST_REGS;hr++) {
610 if(cur->regmap[hr]==reg) {
611 return cur->constmap[hr];
612 }
613 }
614 printf("Unknown constant in r%d\n",reg);
615 exit(1);
616}
617
618// Least soon needed registers
619// Look at the next ten instructions and see which registers
620// will be used. Try not to reallocate these.
621void lsn(u_char hsn[], int i, int *preferred_reg)
622{
623 int j;
624 int b=-1;
625 for(j=0;j<9;j++)
626 {
627 if(i+j>=slen) {
628 j=slen-i-1;
629 break;
630 }
631 if(itype[i+j]==UJUMP||itype[i+j]==RJUMP||(source[i+j]>>16)==0x1000)
632 {
633 // Don't go past an unconditonal jump
634 j++;
635 break;
636 }
637 }
638 for(;j>=0;j--)
639 {
640 if(rs1[i+j]) hsn[rs1[i+j]]=j;
641 if(rs2[i+j]) hsn[rs2[i+j]]=j;
642 if(rt1[i+j]) hsn[rt1[i+j]]=j;
643 if(rt2[i+j]) hsn[rt2[i+j]]=j;
644 if(itype[i+j]==STORE || itype[i+j]==STORELR) {
645 // Stores can allocate zero
646 hsn[rs1[i+j]]=j;
647 hsn[rs2[i+j]]=j;
648 }
649 // On some architectures stores need invc_ptr
650 #if defined(HOST_IMM8)
b9b61529 651 if(itype[i+j]==STORE || itype[i+j]==STORELR || (opcode[i+j]&0x3b)==0x39 || (opcode[i+j]&0x3b)==0x3a) {
57871462 652 hsn[INVCP]=j;
653 }
654 #endif
655 if(i+j>=0&&(itype[i+j]==UJUMP||itype[i+j]==CJUMP||itype[i+j]==SJUMP||itype[i+j]==FJUMP))
656 {
657 hsn[CCREG]=j;
658 b=j;
659 }
660 }
661 if(b>=0)
662 {
663 if(ba[i+b]>=start && ba[i+b]<(start+slen*4))
664 {
665 // Follow first branch
666 int t=(ba[i+b]-start)>>2;
667 j=7-b;if(t+j>=slen) j=slen-t-1;
668 for(;j>=0;j--)
669 {
670 if(rs1[t+j]) if(hsn[rs1[t+j]]>j+b+2) hsn[rs1[t+j]]=j+b+2;
671 if(rs2[t+j]) if(hsn[rs2[t+j]]>j+b+2) hsn[rs2[t+j]]=j+b+2;
672 //if(rt1[t+j]) if(hsn[rt1[t+j]]>j+b+2) hsn[rt1[t+j]]=j+b+2;
673 //if(rt2[t+j]) if(hsn[rt2[t+j]]>j+b+2) hsn[rt2[t+j]]=j+b+2;
674 }
675 }
676 // TODO: preferred register based on backward branch
677 }
678 // Delay slot should preferably not overwrite branch conditions or cycle count
679 if(i>0&&(itype[i-1]==RJUMP||itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP)) {
680 if(rs1[i-1]) if(hsn[rs1[i-1]]>1) hsn[rs1[i-1]]=1;
681 if(rs2[i-1]) if(hsn[rs2[i-1]]>1) hsn[rs2[i-1]]=1;
682 hsn[CCREG]=1;
683 // ...or hash tables
684 hsn[RHASH]=1;
685 hsn[RHTBL]=1;
686 }
687 // Coprocessor load/store needs FTEMP, even if not declared
b9b61529 688 if(itype[i]==C1LS||itype[i]==C2LS) {
57871462 689 hsn[FTEMP]=0;
690 }
691 // Load L/R also uses FTEMP as a temporary register
692 if(itype[i]==LOADLR) {
693 hsn[FTEMP]=0;
694 }
b7918751 695 // Also SWL/SWR/SDL/SDR
696 if(opcode[i]==0x2a||opcode[i]==0x2e||opcode[i]==0x2c||opcode[i]==0x2d) {
57871462 697 hsn[FTEMP]=0;
698 }
699 // Don't remove the TLB registers either
b9b61529 700 if(itype[i]==LOAD || itype[i]==LOADLR || itype[i]==STORE || itype[i]==STORELR || itype[i]==C1LS || itype[i]==C2LS) {
57871462 701 hsn[TLREG]=0;
702 }
703 // Don't remove the miniht registers
704 if(itype[i]==UJUMP||itype[i]==RJUMP)
705 {
706 hsn[RHASH]=0;
707 hsn[RHTBL]=0;
708 }
709}
710
711// We only want to allocate registers if we're going to use them again soon
712int needed_again(int r, int i)
713{
714 int j;
715 int b=-1;
716 int rn=10;
717 int hr;
718 u_char hsn[MAXREG+1];
719 int preferred_reg;
720
721 memset(hsn,10,sizeof(hsn));
722 lsn(hsn,i,&preferred_reg);
723
724 if(i>0&&(itype[i-1]==UJUMP||itype[i-1]==RJUMP||(source[i-1]>>16)==0x1000))
725 {
726 if(ba[i-1]<start || ba[i-1]>start+slen*4-4)
727 return 0; // Don't need any registers if exiting the block
728 }
729 for(j=0;j<9;j++)
730 {
731 if(i+j>=slen) {
732 j=slen-i-1;
733 break;
734 }
735 if(itype[i+j]==UJUMP||itype[i+j]==RJUMP||(source[i+j]>>16)==0x1000)
736 {
737 // Don't go past an unconditonal jump
738 j++;
739 break;
740 }
1e973cb0 741 if(itype[i+j]==SYSCALL||itype[i+j]==HLECALL||itype[i+j]==INTCALL||((source[i+j]&0xfc00003f)==0x0d))
57871462 742 {
743 break;
744 }
745 }
746 for(;j>=1;j--)
747 {
748 if(rs1[i+j]==r) rn=j;
749 if(rs2[i+j]==r) rn=j;
750 if((unneeded_reg[i+j]>>r)&1) rn=10;
751 if(i+j>=0&&(itype[i+j]==UJUMP||itype[i+j]==CJUMP||itype[i+j]==SJUMP||itype[i+j]==FJUMP))
752 {
753 b=j;
754 }
755 }
756 /*
757 if(b>=0)
758 {
759 if(ba[i+b]>=start && ba[i+b]<(start+slen*4))
760 {
761 // Follow first branch
762 int o=rn;
763 int t=(ba[i+b]-start)>>2;
764 j=7-b;if(t+j>=slen) j=slen-t-1;
765 for(;j>=0;j--)
766 {
767 if(!((unneeded_reg[t+j]>>r)&1)) {
768 if(rs1[t+j]==r) if(rn>j+b+2) rn=j+b+2;
769 if(rs2[t+j]==r) if(rn>j+b+2) rn=j+b+2;
770 }
771 else rn=o;
772 }
773 }
774 }*/
775 for(hr=0;hr<HOST_REGS;hr++) {
776 if(hr!=EXCLUDE_REG) {
777 if(rn<hsn[hr]) return 1;
778 }
779 }
780 return 0;
781}
782
783// Try to match register allocations at the end of a loop with those
784// at the beginning
785int loop_reg(int i, int r, int hr)
786{
787 int j,k;
788 for(j=0;j<9;j++)
789 {
790 if(i+j>=slen) {
791 j=slen-i-1;
792 break;
793 }
794 if(itype[i+j]==UJUMP||itype[i+j]==RJUMP||(source[i+j]>>16)==0x1000)
795 {
796 // Don't go past an unconditonal jump
797 j++;
798 break;
799 }
800 }
801 k=0;
802 if(i>0){
803 if(itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP)
804 k--;
805 }
806 for(;k<j;k++)
807 {
808 if(r<64&&((unneeded_reg[i+k]>>r)&1)) return hr;
809 if(r>64&&((unneeded_reg_upper[i+k]>>r)&1)) return hr;
810 if(i+k>=0&&(itype[i+k]==UJUMP||itype[i+k]==CJUMP||itype[i+k]==SJUMP||itype[i+k]==FJUMP))
811 {
812 if(ba[i+k]>=start && ba[i+k]<(start+i*4))
813 {
814 int t=(ba[i+k]-start)>>2;
815 int reg=get_reg(regs[t].regmap_entry,r);
816 if(reg>=0) return reg;
817 //reg=get_reg(regs[t+1].regmap_entry,r);
818 //if(reg>=0) return reg;
819 }
820 }
821 }
822 return hr;
823}
824
825
826// Allocate every register, preserving source/target regs
827void alloc_all(struct regstat *cur,int i)
828{
829 int hr;
830
831 for(hr=0;hr<HOST_REGS;hr++) {
832 if(hr!=EXCLUDE_REG) {
833 if(((cur->regmap[hr]&63)!=rs1[i])&&((cur->regmap[hr]&63)!=rs2[i])&&
834 ((cur->regmap[hr]&63)!=rt1[i])&&((cur->regmap[hr]&63)!=rt2[i]))
835 {
836 cur->regmap[hr]=-1;
837 cur->dirty&=~(1<<hr);
838 }
839 // Don't need zeros
840 if((cur->regmap[hr]&63)==0)
841 {
842 cur->regmap[hr]=-1;
843 cur->dirty&=~(1<<hr);
844 }
845 }
846 }
847}
848
849
850void div64(int64_t dividend,int64_t divisor)
851{
852 lo=dividend/divisor;
853 hi=dividend%divisor;
854 //printf("TRACE: ddiv %8x%8x %8x%8x\n" ,(int)reg[HIREG],(int)(reg[HIREG]>>32)
855 // ,(int)reg[LOREG],(int)(reg[LOREG]>>32));
856}
857void divu64(uint64_t dividend,uint64_t divisor)
858{
859 lo=dividend/divisor;
860 hi=dividend%divisor;
861 //printf("TRACE: ddivu %8x%8x %8x%8x\n",(int)reg[HIREG],(int)(reg[HIREG]>>32)
862 // ,(int)reg[LOREG],(int)(reg[LOREG]>>32));
863}
864
865void mult64(uint64_t m1,uint64_t m2)
866{
867 unsigned long long int op1, op2, op3, op4;
868 unsigned long long int result1, result2, result3, result4;
869 unsigned long long int temp1, temp2, temp3, temp4;
870 int sign = 0;
871
872 if (m1 < 0)
873 {
874 op2 = -m1;
875 sign = 1 - sign;
876 }
877 else op2 = m1;
878 if (m2 < 0)
879 {
880 op4 = -m2;
881 sign = 1 - sign;
882 }
883 else op4 = m2;
884
885 op1 = op2 & 0xFFFFFFFF;
886 op2 = (op2 >> 32) & 0xFFFFFFFF;
887 op3 = op4 & 0xFFFFFFFF;
888 op4 = (op4 >> 32) & 0xFFFFFFFF;
889
890 temp1 = op1 * op3;
891 temp2 = (temp1 >> 32) + op1 * op4;
892 temp3 = op2 * op3;
893 temp4 = (temp3 >> 32) + op2 * op4;
894
895 result1 = temp1 & 0xFFFFFFFF;
896 result2 = temp2 + (temp3 & 0xFFFFFFFF);
897 result3 = (result2 >> 32) + temp4;
898 result4 = (result3 >> 32);
899
900 lo = result1 | (result2 << 32);
901 hi = (result3 & 0xFFFFFFFF) | (result4 << 32);
902 if (sign)
903 {
904 hi = ~hi;
905 if (!lo) hi++;
906 else lo = ~lo + 1;
907 }
908}
909
910void multu64(uint64_t m1,uint64_t m2)
911{
912 unsigned long long int op1, op2, op3, op4;
913 unsigned long long int result1, result2, result3, result4;
914 unsigned long long int temp1, temp2, temp3, temp4;
915
916 op1 = m1 & 0xFFFFFFFF;
917 op2 = (m1 >> 32) & 0xFFFFFFFF;
918 op3 = m2 & 0xFFFFFFFF;
919 op4 = (m2 >> 32) & 0xFFFFFFFF;
920
921 temp1 = op1 * op3;
922 temp2 = (temp1 >> 32) + op1 * op4;
923 temp3 = op2 * op3;
924 temp4 = (temp3 >> 32) + op2 * op4;
925
926 result1 = temp1 & 0xFFFFFFFF;
927 result2 = temp2 + (temp3 & 0xFFFFFFFF);
928 result3 = (result2 >> 32) + temp4;
929 result4 = (result3 >> 32);
930
931 lo = result1 | (result2 << 32);
932 hi = (result3 & 0xFFFFFFFF) | (result4 << 32);
933
934 //printf("TRACE: dmultu %8x%8x %8x%8x\n",(int)reg[HIREG],(int)(reg[HIREG]>>32)
935 // ,(int)reg[LOREG],(int)(reg[LOREG]>>32));
936}
937
938uint64_t ldl_merge(uint64_t original,uint64_t loaded,u_int bits)
939{
940 if(bits) {
941 original<<=64-bits;
942 original>>=64-bits;
943 loaded<<=bits;
944 original|=loaded;
945 }
946 else original=loaded;
947 return original;
948}
949uint64_t ldr_merge(uint64_t original,uint64_t loaded,u_int bits)
950{
951 if(bits^56) {
952 original>>=64-(bits^56);
953 original<<=64-(bits^56);
954 loaded>>=bits^56;
955 original|=loaded;
956 }
957 else original=loaded;
958 return original;
959}
960
961#ifdef __i386__
962#include "assem_x86.c"
963#endif
964#ifdef __x86_64__
965#include "assem_x64.c"
966#endif
967#ifdef __arm__
968#include "assem_arm.c"
969#endif
970
971// Add virtual address mapping to linked list
972void ll_add(struct ll_entry **head,int vaddr,void *addr)
973{
974 struct ll_entry *new_entry;
975 new_entry=malloc(sizeof(struct ll_entry));
976 assert(new_entry!=NULL);
977 new_entry->vaddr=vaddr;
978 new_entry->reg32=0;
979 new_entry->addr=addr;
980 new_entry->next=*head;
981 *head=new_entry;
982}
983
984// Add virtual address mapping for 32-bit compiled block
985void ll_add_32(struct ll_entry **head,int vaddr,u_int reg32,void *addr)
986{
7139f3c8 987 ll_add(head,vaddr,addr);
988#ifndef FORCE32
989 (*head)->reg32=reg32;
990#endif
57871462 991}
992
993// Check if an address is already compiled
994// but don't return addresses which are about to expire from the cache
995void *check_addr(u_int vaddr)
996{
997 u_int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
998 if(ht_bin[0]==vaddr) {
999 if(((ht_bin[1]-MAX_OUTPUT_BLOCK_SIZE-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
1000 if(isclean(ht_bin[1])) return (void *)ht_bin[1];
1001 }
1002 if(ht_bin[2]==vaddr) {
1003 if(((ht_bin[3]-MAX_OUTPUT_BLOCK_SIZE-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
1004 if(isclean(ht_bin[3])) return (void *)ht_bin[3];
1005 }
94d23bb9 1006 u_int page=get_page(vaddr);
57871462 1007 struct ll_entry *head;
1008 head=jump_in[page];
1009 while(head!=NULL) {
1010 if(head->vaddr==vaddr&&head->reg32==0) {
1011 if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2))) {
1012 // Update existing entry with current address
1013 if(ht_bin[0]==vaddr) {
1014 ht_bin[1]=(int)head->addr;
1015 return head->addr;
1016 }
1017 if(ht_bin[2]==vaddr) {
1018 ht_bin[3]=(int)head->addr;
1019 return head->addr;
1020 }
1021 // Insert into hash table with low priority.
1022 // Don't evict existing entries, as they are probably
1023 // addresses that are being accessed frequently.
1024 if(ht_bin[0]==-1) {
1025 ht_bin[1]=(int)head->addr;
1026 ht_bin[0]=vaddr;
1027 }else if(ht_bin[2]==-1) {
1028 ht_bin[3]=(int)head->addr;
1029 ht_bin[2]=vaddr;
1030 }
1031 return head->addr;
1032 }
1033 }
1034 head=head->next;
1035 }
1036 return 0;
1037}
1038
1039void remove_hash(int vaddr)
1040{
1041 //printf("remove hash: %x\n",vaddr);
1042 int *ht_bin=hash_table[(((vaddr)>>16)^vaddr)&0xFFFF];
1043 if(ht_bin[2]==vaddr) {
1044 ht_bin[2]=ht_bin[3]=-1;
1045 }
1046 if(ht_bin[0]==vaddr) {
1047 ht_bin[0]=ht_bin[2];
1048 ht_bin[1]=ht_bin[3];
1049 ht_bin[2]=ht_bin[3]=-1;
1050 }
1051}
1052
1053void ll_remove_matching_addrs(struct ll_entry **head,int addr,int shift)
1054{
1055 struct ll_entry *next;
1056 while(*head) {
1057 if(((u_int)((*head)->addr)>>shift)==(addr>>shift) ||
1058 ((u_int)((*head)->addr-MAX_OUTPUT_BLOCK_SIZE)>>shift)==(addr>>shift))
1059 {
1060 inv_debug("EXP: Remove pointer to %x (%x)\n",(int)(*head)->addr,(*head)->vaddr);
1061 remove_hash((*head)->vaddr);
1062 next=(*head)->next;
1063 free(*head);
1064 *head=next;
1065 }
1066 else
1067 {
1068 head=&((*head)->next);
1069 }
1070 }
1071}
1072
1073// Remove all entries from linked list
1074void ll_clear(struct ll_entry **head)
1075{
1076 struct ll_entry *cur;
1077 struct ll_entry *next;
1078 if(cur=*head) {
1079 *head=0;
1080 while(cur) {
1081 next=cur->next;
1082 free(cur);
1083 cur=next;
1084 }
1085 }
1086}
1087
1088// Dereference the pointers and remove if it matches
1089void ll_kill_pointers(struct ll_entry *head,int addr,int shift)
1090{
1091 while(head) {
1092 int ptr=get_pointer(head->addr);
1093 inv_debug("EXP: Lookup pointer to %x at %x (%x)\n",(int)ptr,(int)head->addr,head->vaddr);
1094 if(((ptr>>shift)==(addr>>shift)) ||
1095 (((ptr-MAX_OUTPUT_BLOCK_SIZE)>>shift)==(addr>>shift)))
1096 {
5088bb70 1097 inv_debug("EXP: Kill pointer at %x (%x)\n",(int)head->addr,head->vaddr);
f76eeef9 1098 u_int host_addr=(u_int)kill_pointer(head->addr);
dd3a91a1 1099 #ifdef __arm__
1100 needs_clear_cache[(host_addr-(u_int)BASE_ADDR)>>17]|=1<<(((host_addr-(u_int)BASE_ADDR)>>12)&31);
1101 #endif
57871462 1102 }
1103 head=head->next;
1104 }
1105}
1106
1107// This is called when we write to a compiled block (see do_invstub)
f76eeef9 1108void invalidate_page(u_int page)
57871462 1109{
57871462 1110 struct ll_entry *head;
1111 struct ll_entry *next;
1112 head=jump_in[page];
1113 jump_in[page]=0;
1114 while(head!=NULL) {
1115 inv_debug("INVALIDATE: %x\n",head->vaddr);
1116 remove_hash(head->vaddr);
1117 next=head->next;
1118 free(head);
1119 head=next;
1120 }
1121 head=jump_out[page];
1122 jump_out[page]=0;
1123 while(head!=NULL) {
1124 inv_debug("INVALIDATE: kill pointer to %x (%x)\n",head->vaddr,(int)head->addr);
f76eeef9 1125 u_int host_addr=(u_int)kill_pointer(head->addr);
dd3a91a1 1126 #ifdef __arm__
1127 needs_clear_cache[(host_addr-(u_int)BASE_ADDR)>>17]|=1<<(((host_addr-(u_int)BASE_ADDR)>>12)&31);
1128 #endif
57871462 1129 next=head->next;
1130 free(head);
1131 head=next;
1132 }
57871462 1133}
1134void invalidate_block(u_int block)
1135{
94d23bb9 1136 u_int page=get_page(block<<12);
1137 u_int vpage=get_vpage(block<<12);
57871462 1138 inv_debug("INVALIDATE: %x (%d)\n",block<<12,page);
1139 //inv_debug("invalid_code[block]=%d\n",invalid_code[block]);
1140 u_int first,last;
1141 first=last=page;
1142 struct ll_entry *head;
1143 head=jump_dirty[vpage];
1144 //printf("page=%d vpage=%d\n",page,vpage);
1145 while(head!=NULL) {
1146 u_int start,end;
1147 if(vpage>2047||(head->vaddr>>12)==block) { // Ignore vaddr hash collision
1148 get_bounds((int)head->addr,&start,&end);
1149 //printf("start: %x end: %x\n",start,end);
4cb76aa4 1150 if(page<2048&&start>=0x80000000&&end<0x80000000+RAM_SIZE) {
57871462 1151 if(((start-(u_int)rdram)>>12)<=page&&((end-1-(u_int)rdram)>>12)>=page) {
1152 if((((start-(u_int)rdram)>>12)&2047)<first) first=((start-(u_int)rdram)>>12)&2047;
1153 if((((end-1-(u_int)rdram)>>12)&2047)>last) last=((end-1-(u_int)rdram)>>12)&2047;
1154 }
1155 }
90ae6d4e 1156#ifndef DISABLE_TLB
57871462 1157 if(page<2048&&(signed int)start>=(signed int)0xC0000000&&(signed int)end>=(signed int)0xC0000000) {
1158 if(((start+memory_map[start>>12]-(u_int)rdram)>>12)<=page&&((end-1+memory_map[(end-1)>>12]-(u_int)rdram)>>12)>=page) {
1159 if((((start+memory_map[start>>12]-(u_int)rdram)>>12)&2047)<first) first=((start+memory_map[start>>12]-(u_int)rdram)>>12)&2047;
1160 if((((end-1+memory_map[(end-1)>>12]-(u_int)rdram)>>12)&2047)>last) last=((end-1+memory_map[(end-1)>>12]-(u_int)rdram)>>12)&2047;
1161 }
1162 }
90ae6d4e 1163#endif
57871462 1164 }
1165 head=head->next;
1166 }
1167 //printf("first=%d last=%d\n",first,last);
f76eeef9 1168 invalidate_page(page);
57871462 1169 assert(first+5>page); // NB: this assumes MAXBLOCK<=4096 (4 pages)
1170 assert(last<page+5);
1171 // Invalidate the adjacent pages if a block crosses a 4K boundary
1172 while(first<page) {
1173 invalidate_page(first);
1174 first++;
1175 }
1176 for(first=page+1;first<last;first++) {
1177 invalidate_page(first);
1178 }
dd3a91a1 1179 #ifdef __arm__
1180 do_clear_cache();
1181 #endif
57871462 1182
1183 // Don't trap writes
1184 invalid_code[block]=1;
94d23bb9 1185#ifndef DISABLE_TLB
57871462 1186 // If there is a valid TLB entry for this page, remove write protect
1187 if(tlb_LUT_w[block]) {
1188 assert(tlb_LUT_r[block]==tlb_LUT_w[block]);
1189 // CHECK: Is this right?
1190 memory_map[block]=((tlb_LUT_w[block]&0xFFFFF000)-(block<<12)+(unsigned int)rdram-0x80000000)>>2;
1191 u_int real_block=tlb_LUT_w[block]>>12;
1192 invalid_code[real_block]=1;
1193 if(real_block>=0x80000&&real_block<0x80800) memory_map[real_block]=((u_int)rdram-0x80000000)>>2;
1194 }
1195 else if(block>=0x80000&&block<0x80800) memory_map[block]=((u_int)rdram-0x80000000)>>2;
94d23bb9 1196#endif
f76eeef9 1197
57871462 1198 #ifdef USE_MINI_HT
1199 memset(mini_ht,-1,sizeof(mini_ht));
1200 #endif
1201}
1202void invalidate_addr(u_int addr)
1203{
1204 invalidate_block(addr>>12);
1205}
dd3a91a1 1206// This is called when loading a save state.
1207// Anything could have changed, so invalidate everything.
57871462 1208void invalidate_all_pages()
1209{
1210 u_int page,n;
1211 for(page=0;page<4096;page++)
1212 invalidate_page(page);
1213 for(page=0;page<1048576;page++)
1214 if(!invalid_code[page]) {
1215 restore_candidate[(page&2047)>>3]|=1<<(page&7);
1216 restore_candidate[((page&2047)>>3)+256]|=1<<(page&7);
1217 }
1218 #ifdef __arm__
1219 __clear_cache((void *)BASE_ADDR,(void *)BASE_ADDR+(1<<TARGET_SIZE_2));
1220 #endif
1221 #ifdef USE_MINI_HT
1222 memset(mini_ht,-1,sizeof(mini_ht));
1223 #endif
94d23bb9 1224 #ifndef DISABLE_TLB
57871462 1225 // TLB
1226 for(page=0;page<0x100000;page++) {
1227 if(tlb_LUT_r[page]) {
1228 memory_map[page]=((tlb_LUT_r[page]&0xFFFFF000)-(page<<12)+(unsigned int)rdram-0x80000000)>>2;
1229 if(!tlb_LUT_w[page]||!invalid_code[page])
1230 memory_map[page]|=0x40000000; // Write protect
1231 }
1232 else memory_map[page]=-1;
1233 if(page==0x80000) page=0xC0000;
1234 }
1235 tlb_hacks();
94d23bb9 1236 #endif
57871462 1237}
1238
1239// Add an entry to jump_out after making a link
1240void add_link(u_int vaddr,void *src)
1241{
94d23bb9 1242 u_int page=get_page(vaddr);
57871462 1243 inv_debug("add_link: %x -> %x (%d)\n",(int)src,vaddr,page);
1244 ll_add(jump_out+page,vaddr,src);
1245 //int ptr=get_pointer(src);
1246 //inv_debug("add_link: Pointer is to %x\n",(int)ptr);
1247}
1248
1249// If a code block was found to be unmodified (bit was set in
1250// restore_candidate) and it remains unmodified (bit is clear
1251// in invalid_code) then move the entries for that 4K page from
1252// the dirty list to the clean list.
1253void clean_blocks(u_int page)
1254{
1255 struct ll_entry *head;
1256 inv_debug("INV: clean_blocks page=%d\n",page);
1257 head=jump_dirty[page];
1258 while(head!=NULL) {
1259 if(!invalid_code[head->vaddr>>12]) {
1260 // Don't restore blocks which are about to expire from the cache
1261 if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2))) {
1262 u_int start,end;
1263 if(verify_dirty((int)head->addr)) {
1264 //printf("Possibly Restore %x (%x)\n",head->vaddr, (int)head->addr);
1265 u_int i;
1266 u_int inv=0;
1267 get_bounds((int)head->addr,&start,&end);
4cb76aa4 1268 if(start-(u_int)rdram<RAM_SIZE) {
57871462 1269 for(i=(start-(u_int)rdram+0x80000000)>>12;i<=(end-1-(u_int)rdram+0x80000000)>>12;i++) {
1270 inv|=invalid_code[i];
1271 }
1272 }
1273 if((signed int)head->vaddr>=(signed int)0xC0000000) {
1274 u_int addr = (head->vaddr+(memory_map[head->vaddr>>12]<<2));
1275 //printf("addr=%x start=%x end=%x\n",addr,start,end);
1276 if(addr<start||addr>=end) inv=1;
1277 }
4cb76aa4 1278 else if((signed int)head->vaddr>=(signed int)0x80000000+RAM_SIZE) {
57871462 1279 inv=1;
1280 }
1281 if(!inv) {
1282 void * clean_addr=(void *)get_clean_addr((int)head->addr);
1283 if((((u_int)clean_addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2))) {
1284 u_int ppage=page;
94d23bb9 1285#ifndef DISABLE_TLB
57871462 1286 if(page<2048&&tlb_LUT_r[head->vaddr>>12]) ppage=(tlb_LUT_r[head->vaddr>>12]^0x80000000)>>12;
94d23bb9 1287#endif
57871462 1288 inv_debug("INV: Restored %x (%x/%x)\n",head->vaddr, (int)head->addr, (int)clean_addr);
1289 //printf("page=%x, addr=%x\n",page,head->vaddr);
1290 //assert(head->vaddr>>12==(page|0x80000));
1291 ll_add_32(jump_in+ppage,head->vaddr,head->reg32,clean_addr);
1292 int *ht_bin=hash_table[((head->vaddr>>16)^head->vaddr)&0xFFFF];
1293 if(!head->reg32) {
1294 if(ht_bin[0]==head->vaddr) {
1295 ht_bin[1]=(int)clean_addr; // Replace existing entry
1296 }
1297 if(ht_bin[2]==head->vaddr) {
1298 ht_bin[3]=(int)clean_addr; // Replace existing entry
1299 }
1300 }
1301 }
1302 }
1303 }
1304 }
1305 }
1306 head=head->next;
1307 }
1308}
1309
1310
1311void mov_alloc(struct regstat *current,int i)
1312{
1313 // Note: Don't need to actually alloc the source registers
1314 if((~current->is32>>rs1[i])&1) {
1315 //alloc_reg64(current,i,rs1[i]);
1316 alloc_reg64(current,i,rt1[i]);
1317 current->is32&=~(1LL<<rt1[i]);
1318 } else {
1319 //alloc_reg(current,i,rs1[i]);
1320 alloc_reg(current,i,rt1[i]);
1321 current->is32|=(1LL<<rt1[i]);
1322 }
1323 clear_const(current,rs1[i]);
1324 clear_const(current,rt1[i]);
1325 dirty_reg(current,rt1[i]);
1326}
1327
1328void shiftimm_alloc(struct regstat *current,int i)
1329{
1330 clear_const(current,rs1[i]);
1331 clear_const(current,rt1[i]);
1332 if(opcode2[i]<=0x3) // SLL/SRL/SRA
1333 {
1334 if(rt1[i]) {
1335 if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1336 else lt1[i]=rs1[i];
1337 alloc_reg(current,i,rt1[i]);
1338 current->is32|=1LL<<rt1[i];
1339 dirty_reg(current,rt1[i]);
1340 }
1341 }
1342 if(opcode2[i]>=0x38&&opcode2[i]<=0x3b) // DSLL/DSRL/DSRA
1343 {
1344 if(rt1[i]) {
1345 if(rs1[i]) alloc_reg64(current,i,rs1[i]);
1346 alloc_reg64(current,i,rt1[i]);
1347 current->is32&=~(1LL<<rt1[i]);
1348 dirty_reg(current,rt1[i]);
1349 }
1350 }
1351 if(opcode2[i]==0x3c) // DSLL32
1352 {
1353 if(rt1[i]) {
1354 if(rs1[i]) alloc_reg(current,i,rs1[i]);
1355 alloc_reg64(current,i,rt1[i]);
1356 current->is32&=~(1LL<<rt1[i]);
1357 dirty_reg(current,rt1[i]);
1358 }
1359 }
1360 if(opcode2[i]==0x3e) // DSRL32
1361 {
1362 if(rt1[i]) {
1363 alloc_reg64(current,i,rs1[i]);
1364 if(imm[i]==32) {
1365 alloc_reg64(current,i,rt1[i]);
1366 current->is32&=~(1LL<<rt1[i]);
1367 } else {
1368 alloc_reg(current,i,rt1[i]);
1369 current->is32|=1LL<<rt1[i];
1370 }
1371 dirty_reg(current,rt1[i]);
1372 }
1373 }
1374 if(opcode2[i]==0x3f) // DSRA32
1375 {
1376 if(rt1[i]) {
1377 alloc_reg64(current,i,rs1[i]);
1378 alloc_reg(current,i,rt1[i]);
1379 current->is32|=1LL<<rt1[i];
1380 dirty_reg(current,rt1[i]);
1381 }
1382 }
1383}
1384
1385void shift_alloc(struct regstat *current,int i)
1386{
1387 if(rt1[i]) {
1388 if(opcode2[i]<=0x07) // SLLV/SRLV/SRAV
1389 {
1390 if(rs1[i]) alloc_reg(current,i,rs1[i]);
1391 if(rs2[i]) alloc_reg(current,i,rs2[i]);
1392 alloc_reg(current,i,rt1[i]);
e1190b87 1393 if(rt1[i]==rs2[i]) {
1394 alloc_reg_temp(current,i,-1);
1395 minimum_free_regs[i]=1;
1396 }
57871462 1397 current->is32|=1LL<<rt1[i];
1398 } else { // DSLLV/DSRLV/DSRAV
1399 if(rs1[i]) alloc_reg64(current,i,rs1[i]);
1400 if(rs2[i]) alloc_reg(current,i,rs2[i]);
1401 alloc_reg64(current,i,rt1[i]);
1402 current->is32&=~(1LL<<rt1[i]);
1403 if(opcode2[i]==0x16||opcode2[i]==0x17) // DSRLV and DSRAV need a temporary register
e1190b87 1404 {
57871462 1405 alloc_reg_temp(current,i,-1);
e1190b87 1406 minimum_free_regs[i]=1;
1407 }
57871462 1408 }
1409 clear_const(current,rs1[i]);
1410 clear_const(current,rs2[i]);
1411 clear_const(current,rt1[i]);
1412 dirty_reg(current,rt1[i]);
1413 }
1414}
1415
1416void alu_alloc(struct regstat *current,int i)
1417{
1418 if(opcode2[i]>=0x20&&opcode2[i]<=0x23) { // ADD/ADDU/SUB/SUBU
1419 if(rt1[i]) {
1420 if(rs1[i]&&rs2[i]) {
1421 alloc_reg(current,i,rs1[i]);
1422 alloc_reg(current,i,rs2[i]);
1423 }
1424 else {
1425 if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1426 if(rs2[i]&&needed_again(rs2[i],i)) alloc_reg(current,i,rs2[i]);
1427 }
1428 alloc_reg(current,i,rt1[i]);
1429 }
1430 current->is32|=1LL<<rt1[i];
1431 }
1432 if(opcode2[i]==0x2a||opcode2[i]==0x2b) { // SLT/SLTU
1433 if(rt1[i]) {
1434 if(!((current->is32>>rs1[i])&(current->is32>>rs2[i])&1))
1435 {
1436 alloc_reg64(current,i,rs1[i]);
1437 alloc_reg64(current,i,rs2[i]);
1438 alloc_reg(current,i,rt1[i]);
1439 } else {
1440 alloc_reg(current,i,rs1[i]);
1441 alloc_reg(current,i,rs2[i]);
1442 alloc_reg(current,i,rt1[i]);
1443 }
1444 }
1445 current->is32|=1LL<<rt1[i];
1446 }
1447 if(opcode2[i]>=0x24&&opcode2[i]<=0x27) { // AND/OR/XOR/NOR
1448 if(rt1[i]) {
1449 if(rs1[i]&&rs2[i]) {
1450 alloc_reg(current,i,rs1[i]);
1451 alloc_reg(current,i,rs2[i]);
1452 }
1453 else
1454 {
1455 if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1456 if(rs2[i]&&needed_again(rs2[i],i)) alloc_reg(current,i,rs2[i]);
1457 }
1458 alloc_reg(current,i,rt1[i]);
1459 if(!((current->is32>>rs1[i])&(current->is32>>rs2[i])&1))
1460 {
1461 if(!((current->uu>>rt1[i])&1)) {
1462 alloc_reg64(current,i,rt1[i]);
1463 }
1464 if(get_reg(current->regmap,rt1[i]|64)>=0) {
1465 if(rs1[i]&&rs2[i]) {
1466 alloc_reg64(current,i,rs1[i]);
1467 alloc_reg64(current,i,rs2[i]);
1468 }
1469 else
1470 {
1471 // Is is really worth it to keep 64-bit values in registers?
1472 #ifdef NATIVE_64BIT
1473 if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg64(current,i,rs1[i]);
1474 if(rs2[i]&&needed_again(rs2[i],i)) alloc_reg64(current,i,rs2[i]);
1475 #endif
1476 }
1477 }
1478 current->is32&=~(1LL<<rt1[i]);
1479 } else {
1480 current->is32|=1LL<<rt1[i];
1481 }
1482 }
1483 }
1484 if(opcode2[i]>=0x2c&&opcode2[i]<=0x2f) { // DADD/DADDU/DSUB/DSUBU
1485 if(rt1[i]) {
1486 if(rs1[i]&&rs2[i]) {
1487 if(!((current->uu>>rt1[i])&1)||get_reg(current->regmap,rt1[i]|64)>=0) {
1488 alloc_reg64(current,i,rs1[i]);
1489 alloc_reg64(current,i,rs2[i]);
1490 alloc_reg64(current,i,rt1[i]);
1491 } else {
1492 alloc_reg(current,i,rs1[i]);
1493 alloc_reg(current,i,rs2[i]);
1494 alloc_reg(current,i,rt1[i]);
1495 }
1496 }
1497 else {
1498 alloc_reg(current,i,rt1[i]);
1499 if(!((current->uu>>rt1[i])&1)||get_reg(current->regmap,rt1[i]|64)>=0) {
1500 // DADD used as move, or zeroing
1501 // If we have a 64-bit source, then make the target 64 bits too
1502 if(rs1[i]&&!((current->is32>>rs1[i])&1)) {
1503 if(get_reg(current->regmap,rs1[i])>=0) alloc_reg64(current,i,rs1[i]);
1504 alloc_reg64(current,i,rt1[i]);
1505 } else if(rs2[i]&&!((current->is32>>rs2[i])&1)) {
1506 if(get_reg(current->regmap,rs2[i])>=0) alloc_reg64(current,i,rs2[i]);
1507 alloc_reg64(current,i,rt1[i]);
1508 }
1509 if(opcode2[i]>=0x2e&&rs2[i]) {
1510 // DSUB used as negation - 64-bit result
1511 // If we have a 32-bit register, extend it to 64 bits
1512 if(get_reg(current->regmap,rs2[i])>=0) alloc_reg64(current,i,rs2[i]);
1513 alloc_reg64(current,i,rt1[i]);
1514 }
1515 }
1516 }
1517 if(rs1[i]&&rs2[i]) {
1518 current->is32&=~(1LL<<rt1[i]);
1519 } else if(rs1[i]) {
1520 current->is32&=~(1LL<<rt1[i]);
1521 if((current->is32>>rs1[i])&1)
1522 current->is32|=1LL<<rt1[i];
1523 } else if(rs2[i]) {
1524 current->is32&=~(1LL<<rt1[i]);
1525 if((current->is32>>rs2[i])&1)
1526 current->is32|=1LL<<rt1[i];
1527 } else {
1528 current->is32|=1LL<<rt1[i];
1529 }
1530 }
1531 }
1532 clear_const(current,rs1[i]);
1533 clear_const(current,rs2[i]);
1534 clear_const(current,rt1[i]);
1535 dirty_reg(current,rt1[i]);
1536}
1537
1538void imm16_alloc(struct regstat *current,int i)
1539{
1540 if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1541 else lt1[i]=rs1[i];
1542 if(rt1[i]) alloc_reg(current,i,rt1[i]);
1543 if(opcode[i]==0x18||opcode[i]==0x19) { // DADDI/DADDIU
1544 current->is32&=~(1LL<<rt1[i]);
1545 if(!((current->uu>>rt1[i])&1)||get_reg(current->regmap,rt1[i]|64)>=0) {
1546 // TODO: Could preserve the 32-bit flag if the immediate is zero
1547 alloc_reg64(current,i,rt1[i]);
1548 alloc_reg64(current,i,rs1[i]);
1549 }
1550 clear_const(current,rs1[i]);
1551 clear_const(current,rt1[i]);
1552 }
1553 else if(opcode[i]==0x0a||opcode[i]==0x0b) { // SLTI/SLTIU
1554 if((~current->is32>>rs1[i])&1) alloc_reg64(current,i,rs1[i]);
1555 current->is32|=1LL<<rt1[i];
1556 clear_const(current,rs1[i]);
1557 clear_const(current,rt1[i]);
1558 }
1559 else if(opcode[i]>=0x0c&&opcode[i]<=0x0e) { // ANDI/ORI/XORI
1560 if(((~current->is32>>rs1[i])&1)&&opcode[i]>0x0c) {
1561 if(rs1[i]!=rt1[i]) {
1562 if(needed_again(rs1[i],i)) alloc_reg64(current,i,rs1[i]);
1563 alloc_reg64(current,i,rt1[i]);
1564 current->is32&=~(1LL<<rt1[i]);
1565 }
1566 }
1567 else current->is32|=1LL<<rt1[i]; // ANDI clears upper bits
1568 if(is_const(current,rs1[i])) {
1569 int v=get_const(current,rs1[i]);
1570 if(opcode[i]==0x0c) set_const(current,rt1[i],v&imm[i]);
1571 if(opcode[i]==0x0d) set_const(current,rt1[i],v|imm[i]);
1572 if(opcode[i]==0x0e) set_const(current,rt1[i],v^imm[i]);
1573 }
1574 else clear_const(current,rt1[i]);
1575 }
1576 else if(opcode[i]==0x08||opcode[i]==0x09) { // ADDI/ADDIU
1577 if(is_const(current,rs1[i])) {
1578 int v=get_const(current,rs1[i]);
1579 set_const(current,rt1[i],v+imm[i]);
1580 }
1581 else clear_const(current,rt1[i]);
1582 current->is32|=1LL<<rt1[i];
1583 }
1584 else {
1585 set_const(current,rt1[i],((long long)((short)imm[i]))<<16); // LUI
1586 current->is32|=1LL<<rt1[i];
1587 }
1588 dirty_reg(current,rt1[i]);
1589}
1590
1591void load_alloc(struct regstat *current,int i)
1592{
1593 clear_const(current,rt1[i]);
1594 //if(rs1[i]!=rt1[i]&&needed_again(rs1[i],i)) clear_const(current,rs1[i]); // Does this help or hurt?
1595 if(!rs1[i]) current->u&=~1LL; // Allow allocating r0 if it's the source register
1596 if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1597 if(rt1[i]) {
1598 alloc_reg(current,i,rt1[i]);
535d208a 1599 if(get_reg(current->regmap,rt1[i])<0) {
1600 // dummy load, but we still need a register to calculate the address
1601 alloc_reg_temp(current,i,-1);
e1190b87 1602 minimum_free_regs[i]=1;
535d208a 1603 }
57871462 1604 if(opcode[i]==0x27||opcode[i]==0x37) // LWU/LD
1605 {
1606 current->is32&=~(1LL<<rt1[i]);
1607 alloc_reg64(current,i,rt1[i]);
1608 }
1609 else if(opcode[i]==0x1A||opcode[i]==0x1B) // LDL/LDR
1610 {
1611 current->is32&=~(1LL<<rt1[i]);
1612 alloc_reg64(current,i,rt1[i]);
1613 alloc_all(current,i);
1614 alloc_reg64(current,i,FTEMP);
e1190b87 1615 minimum_free_regs[i]=HOST_REGS;
57871462 1616 }
1617 else current->is32|=1LL<<rt1[i];
1618 dirty_reg(current,rt1[i]);
1619 // If using TLB, need a register for pointer to the mapping table
1620 if(using_tlb) alloc_reg(current,i,TLREG);
1621 // LWL/LWR need a temporary register for the old value
1622 if(opcode[i]==0x22||opcode[i]==0x26)
1623 {
1624 alloc_reg(current,i,FTEMP);
1625 alloc_reg_temp(current,i,-1);
e1190b87 1626 minimum_free_regs[i]=1;
57871462 1627 }
1628 }
1629 else
1630 {
1631 // Load to r0 (dummy load)
1632 // but we still need a register to calculate the address
535d208a 1633 if(opcode[i]==0x22||opcode[i]==0x26)
1634 {
1635 alloc_reg(current,i,FTEMP); // LWL/LWR need another temporary
1636 }
57871462 1637 alloc_reg_temp(current,i,-1);
e1190b87 1638 minimum_free_regs[i]=1;
535d208a 1639 if(opcode[i]==0x1A||opcode[i]==0x1B) // LDL/LDR
1640 {
1641 alloc_all(current,i);
1642 alloc_reg64(current,i,FTEMP);
e1190b87 1643 minimum_free_regs[i]=HOST_REGS;
535d208a 1644 }
57871462 1645 }
1646}
1647
1648void store_alloc(struct regstat *current,int i)
1649{
1650 clear_const(current,rs2[i]);
1651 if(!(rs2[i])) current->u&=~1LL; // Allow allocating r0 if necessary
1652 if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1653 alloc_reg(current,i,rs2[i]);
1654 if(opcode[i]==0x2c||opcode[i]==0x2d||opcode[i]==0x3f) { // 64-bit SDL/SDR/SD
1655 alloc_reg64(current,i,rs2[i]);
1656 if(rs2[i]) alloc_reg(current,i,FTEMP);
1657 }
1658 // If using TLB, need a register for pointer to the mapping table
1659 if(using_tlb) alloc_reg(current,i,TLREG);
1660 #if defined(HOST_IMM8)
1661 // On CPUs without 32-bit immediates we need a pointer to invalid_code
1662 else alloc_reg(current,i,INVCP);
1663 #endif
b7918751 1664 if(opcode[i]==0x2a||opcode[i]==0x2e||opcode[i]==0x2c||opcode[i]==0x2d) { // SWL/SWL/SDL/SDR
57871462 1665 alloc_reg(current,i,FTEMP);
1666 }
1667 // We need a temporary register for address generation
1668 alloc_reg_temp(current,i,-1);
e1190b87 1669 minimum_free_regs[i]=1;
57871462 1670}
1671
1672void c1ls_alloc(struct regstat *current,int i)
1673{
1674 //clear_const(current,rs1[i]); // FIXME
1675 clear_const(current,rt1[i]);
1676 if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1677 alloc_reg(current,i,CSREG); // Status
1678 alloc_reg(current,i,FTEMP);
1679 if(opcode[i]==0x35||opcode[i]==0x3d) { // 64-bit LDC1/SDC1
1680 alloc_reg64(current,i,FTEMP);
1681 }
1682 // If using TLB, need a register for pointer to the mapping table
1683 if(using_tlb) alloc_reg(current,i,TLREG);
1684 #if defined(HOST_IMM8)
1685 // On CPUs without 32-bit immediates we need a pointer to invalid_code
1686 else if((opcode[i]&0x3b)==0x39) // SWC1/SDC1
1687 alloc_reg(current,i,INVCP);
1688 #endif
1689 // We need a temporary register for address generation
1690 alloc_reg_temp(current,i,-1);
1691}
1692
b9b61529 1693void c2ls_alloc(struct regstat *current,int i)
1694{
1695 clear_const(current,rt1[i]);
1696 if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1697 alloc_reg(current,i,FTEMP);
1698 // If using TLB, need a register for pointer to the mapping table
1699 if(using_tlb) alloc_reg(current,i,TLREG);
1700 #if defined(HOST_IMM8)
1701 // On CPUs without 32-bit immediates we need a pointer to invalid_code
1702 else if((opcode[i]&0x3b)==0x3a) // SWC2/SDC2
1703 alloc_reg(current,i,INVCP);
1704 #endif
1705 // We need a temporary register for address generation
1706 alloc_reg_temp(current,i,-1);
e1190b87 1707 minimum_free_regs[i]=1;
b9b61529 1708}
1709
57871462 1710#ifndef multdiv_alloc
1711void multdiv_alloc(struct regstat *current,int i)
1712{
1713 // case 0x18: MULT
1714 // case 0x19: MULTU
1715 // case 0x1A: DIV
1716 // case 0x1B: DIVU
1717 // case 0x1C: DMULT
1718 // case 0x1D: DMULTU
1719 // case 0x1E: DDIV
1720 // case 0x1F: DDIVU
1721 clear_const(current,rs1[i]);
1722 clear_const(current,rs2[i]);
1723 if(rs1[i]&&rs2[i])
1724 {
1725 if((opcode2[i]&4)==0) // 32-bit
1726 {
1727 current->u&=~(1LL<<HIREG);
1728 current->u&=~(1LL<<LOREG);
1729 alloc_reg(current,i,HIREG);
1730 alloc_reg(current,i,LOREG);
1731 alloc_reg(current,i,rs1[i]);
1732 alloc_reg(current,i,rs2[i]);
1733 current->is32|=1LL<<HIREG;
1734 current->is32|=1LL<<LOREG;
1735 dirty_reg(current,HIREG);
1736 dirty_reg(current,LOREG);
1737 }
1738 else // 64-bit
1739 {
1740 current->u&=~(1LL<<HIREG);
1741 current->u&=~(1LL<<LOREG);
1742 current->uu&=~(1LL<<HIREG);
1743 current->uu&=~(1LL<<LOREG);
1744 alloc_reg64(current,i,HIREG);
1745 //if(HOST_REGS>10) alloc_reg64(current,i,LOREG);
1746 alloc_reg64(current,i,rs1[i]);
1747 alloc_reg64(current,i,rs2[i]);
1748 alloc_all(current,i);
1749 current->is32&=~(1LL<<HIREG);
1750 current->is32&=~(1LL<<LOREG);
1751 dirty_reg(current,HIREG);
1752 dirty_reg(current,LOREG);
e1190b87 1753 minimum_free_regs[i]=HOST_REGS;
57871462 1754 }
1755 }
1756 else
1757 {
1758 // Multiply by zero is zero.
1759 // MIPS does not have a divide by zero exception.
1760 // The result is undefined, we return zero.
1761 alloc_reg(current,i,HIREG);
1762 alloc_reg(current,i,LOREG);
1763 current->is32|=1LL<<HIREG;
1764 current->is32|=1LL<<LOREG;
1765 dirty_reg(current,HIREG);
1766 dirty_reg(current,LOREG);
1767 }
1768}
1769#endif
1770
1771void cop0_alloc(struct regstat *current,int i)
1772{
1773 if(opcode2[i]==0) // MFC0
1774 {
1775 if(rt1[i]) {
1776 clear_const(current,rt1[i]);
1777 alloc_all(current,i);
1778 alloc_reg(current,i,rt1[i]);
1779 current->is32|=1LL<<rt1[i];
1780 dirty_reg(current,rt1[i]);
1781 }
1782 }
1783 else if(opcode2[i]==4) // MTC0
1784 {
1785 if(rs1[i]){
1786 clear_const(current,rs1[i]);
1787 alloc_reg(current,i,rs1[i]);
1788 alloc_all(current,i);
1789 }
1790 else {
1791 alloc_all(current,i); // FIXME: Keep r0
1792 current->u&=~1LL;
1793 alloc_reg(current,i,0);
1794 }
1795 }
1796 else
1797 {
1798 // TLBR/TLBWI/TLBWR/TLBP/ERET
1799 assert(opcode2[i]==0x10);
1800 alloc_all(current,i);
1801 }
e1190b87 1802 minimum_free_regs[i]=HOST_REGS;
57871462 1803}
1804
1805void cop1_alloc(struct regstat *current,int i)
1806{
1807 alloc_reg(current,i,CSREG); // Load status
1808 if(opcode2[i]<3) // MFC1/DMFC1/CFC1
1809 {
7de557a6 1810 if(rt1[i]){
1811 clear_const(current,rt1[i]);
1812 if(opcode2[i]==1) {
1813 alloc_reg64(current,i,rt1[i]); // DMFC1
1814 current->is32&=~(1LL<<rt1[i]);
1815 }else{
1816 alloc_reg(current,i,rt1[i]); // MFC1/CFC1
1817 current->is32|=1LL<<rt1[i];
1818 }
1819 dirty_reg(current,rt1[i]);
57871462 1820 }
57871462 1821 alloc_reg_temp(current,i,-1);
1822 }
1823 else if(opcode2[i]>3) // MTC1/DMTC1/CTC1
1824 {
1825 if(rs1[i]){
1826 clear_const(current,rs1[i]);
1827 if(opcode2[i]==5)
1828 alloc_reg64(current,i,rs1[i]); // DMTC1
1829 else
1830 alloc_reg(current,i,rs1[i]); // MTC1/CTC1
1831 alloc_reg_temp(current,i,-1);
1832 }
1833 else {
1834 current->u&=~1LL;
1835 alloc_reg(current,i,0);
1836 alloc_reg_temp(current,i,-1);
1837 }
1838 }
e1190b87 1839 minimum_free_regs[i]=1;
57871462 1840}
1841void fconv_alloc(struct regstat *current,int i)
1842{
1843 alloc_reg(current,i,CSREG); // Load status
1844 alloc_reg_temp(current,i,-1);
e1190b87 1845 minimum_free_regs[i]=1;
57871462 1846}
1847void float_alloc(struct regstat *current,int i)
1848{
1849 alloc_reg(current,i,CSREG); // Load status
1850 alloc_reg_temp(current,i,-1);
e1190b87 1851 minimum_free_regs[i]=1;
57871462 1852}
b9b61529 1853void c2op_alloc(struct regstat *current,int i)
1854{
1855 alloc_reg_temp(current,i,-1);
1856}
57871462 1857void fcomp_alloc(struct regstat *current,int i)
1858{
1859 alloc_reg(current,i,CSREG); // Load status
1860 alloc_reg(current,i,FSREG); // Load flags
1861 dirty_reg(current,FSREG); // Flag will be modified
1862 alloc_reg_temp(current,i,-1);
e1190b87 1863 minimum_free_regs[i]=1;
57871462 1864}
1865
1866void syscall_alloc(struct regstat *current,int i)
1867{
1868 alloc_cc(current,i);
1869 dirty_reg(current,CCREG);
1870 alloc_all(current,i);
e1190b87 1871 minimum_free_regs[i]=HOST_REGS;
57871462 1872 current->isconst=0;
1873}
1874
1875void delayslot_alloc(struct regstat *current,int i)
1876{
1877 switch(itype[i]) {
1878 case UJUMP:
1879 case CJUMP:
1880 case SJUMP:
1881 case RJUMP:
1882 case FJUMP:
1883 case SYSCALL:
7139f3c8 1884 case HLECALL:
57871462 1885 case SPAN:
1886 assem_debug("jump in the delay slot. this shouldn't happen.\n");//exit(1);
1887 printf("Disabled speculative precompilation\n");
1888 stop_after_jal=1;
1889 break;
1890 case IMM16:
1891 imm16_alloc(current,i);
1892 break;
1893 case LOAD:
1894 case LOADLR:
1895 load_alloc(current,i);
1896 break;
1897 case STORE:
1898 case STORELR:
1899 store_alloc(current,i);
1900 break;
1901 case ALU:
1902 alu_alloc(current,i);
1903 break;
1904 case SHIFT:
1905 shift_alloc(current,i);
1906 break;
1907 case MULTDIV:
1908 multdiv_alloc(current,i);
1909 break;
1910 case SHIFTIMM:
1911 shiftimm_alloc(current,i);
1912 break;
1913 case MOV:
1914 mov_alloc(current,i);
1915 break;
1916 case COP0:
1917 cop0_alloc(current,i);
1918 break;
1919 case COP1:
b9b61529 1920 case COP2:
57871462 1921 cop1_alloc(current,i);
1922 break;
1923 case C1LS:
1924 c1ls_alloc(current,i);
1925 break;
b9b61529 1926 case C2LS:
1927 c2ls_alloc(current,i);
1928 break;
57871462 1929 case FCONV:
1930 fconv_alloc(current,i);
1931 break;
1932 case FLOAT:
1933 float_alloc(current,i);
1934 break;
1935 case FCOMP:
1936 fcomp_alloc(current,i);
1937 break;
b9b61529 1938 case C2OP:
1939 c2op_alloc(current,i);
1940 break;
57871462 1941 }
1942}
1943
1944// Special case where a branch and delay slot span two pages in virtual memory
1945static void pagespan_alloc(struct regstat *current,int i)
1946{
1947 current->isconst=0;
1948 current->wasconst=0;
1949 regs[i].wasconst=0;
e1190b87 1950 minimum_free_regs[i]=HOST_REGS;
57871462 1951 alloc_all(current,i);
1952 alloc_cc(current,i);
1953 dirty_reg(current,CCREG);
1954 if(opcode[i]==3) // JAL
1955 {
1956 alloc_reg(current,i,31);
1957 dirty_reg(current,31);
1958 }
1959 if(opcode[i]==0&&(opcode2[i]&0x3E)==8) // JR/JALR
1960 {
1961 alloc_reg(current,i,rs1[i]);
5067f341 1962 if (rt1[i]!=0) {
1963 alloc_reg(current,i,rt1[i]);
1964 dirty_reg(current,rt1[i]);
57871462 1965 }
1966 }
1967 if((opcode[i]&0x2E)==4) // BEQ/BNE/BEQL/BNEL
1968 {
1969 if(rs1[i]) alloc_reg(current,i,rs1[i]);
1970 if(rs2[i]) alloc_reg(current,i,rs2[i]);
1971 if(!((current->is32>>rs1[i])&(current->is32>>rs2[i])&1))
1972 {
1973 if(rs1[i]) alloc_reg64(current,i,rs1[i]);
1974 if(rs2[i]) alloc_reg64(current,i,rs2[i]);
1975 }
1976 }
1977 else
1978 if((opcode[i]&0x2E)==6) // BLEZ/BGTZ/BLEZL/BGTZL
1979 {
1980 if(rs1[i]) alloc_reg(current,i,rs1[i]);
1981 if(!((current->is32>>rs1[i])&1))
1982 {
1983 if(rs1[i]) alloc_reg64(current,i,rs1[i]);
1984 }
1985 }
1986 else
1987 if(opcode[i]==0x11) // BC1
1988 {
1989 alloc_reg(current,i,FSREG);
1990 alloc_reg(current,i,CSREG);
1991 }
1992 //else ...
1993}
1994
1995add_stub(int type,int addr,int retaddr,int a,int b,int c,int d,int e)
1996{
1997 stubs[stubcount][0]=type;
1998 stubs[stubcount][1]=addr;
1999 stubs[stubcount][2]=retaddr;
2000 stubs[stubcount][3]=a;
2001 stubs[stubcount][4]=b;
2002 stubs[stubcount][5]=c;
2003 stubs[stubcount][6]=d;
2004 stubs[stubcount][7]=e;
2005 stubcount++;
2006}
2007
2008// Write out a single register
2009void wb_register(signed char r,signed char regmap[],uint64_t dirty,uint64_t is32)
2010{
2011 int hr;
2012 for(hr=0;hr<HOST_REGS;hr++) {
2013 if(hr!=EXCLUDE_REG) {
2014 if((regmap[hr]&63)==r) {
2015 if((dirty>>hr)&1) {
2016 if(regmap[hr]<64) {
2017 emit_storereg(r,hr);
24385cae 2018#ifndef FORCE32
57871462 2019 if((is32>>regmap[hr])&1) {
2020 emit_sarimm(hr,31,hr);
2021 emit_storereg(r|64,hr);
2022 }
24385cae 2023#endif
57871462 2024 }else{
2025 emit_storereg(r|64,hr);
2026 }
2027 }
2028 }
2029 }
2030 }
2031}
2032
2033int mchecksum()
2034{
2035 //if(!tracedebug) return 0;
2036 int i;
2037 int sum=0;
2038 for(i=0;i<2097152;i++) {
2039 unsigned int temp=sum;
2040 sum<<=1;
2041 sum|=(~temp)>>31;
2042 sum^=((u_int *)rdram)[i];
2043 }
2044 return sum;
2045}
2046int rchecksum()
2047{
2048 int i;
2049 int sum=0;
2050 for(i=0;i<64;i++)
2051 sum^=((u_int *)reg)[i];
2052 return sum;
2053}
57871462 2054void rlist()
2055{
2056 int i;
2057 printf("TRACE: ");
2058 for(i=0;i<32;i++)
2059 printf("r%d:%8x%8x ",i,((int *)(reg+i))[1],((int *)(reg+i))[0]);
2060 printf("\n");
3d624f89 2061#ifndef DISABLE_COP1
57871462 2062 printf("TRACE: ");
2063 for(i=0;i<32;i++)
2064 printf("f%d:%8x%8x ",i,((int*)reg_cop1_simple[i])[1],*((int*)reg_cop1_simple[i]));
2065 printf("\n");
3d624f89 2066#endif
57871462 2067}
2068
2069void enabletrace()
2070{
2071 tracedebug=1;
2072}
2073
2074void memdebug(int i)
2075{
2076 //printf("TRACE: count=%d next=%d (checksum %x) lo=%8x%8x\n",Count,next_interupt,mchecksum(),(int)(reg[LOREG]>>32),(int)reg[LOREG]);
2077 //printf("TRACE: count=%d next=%d (rchecksum %x)\n",Count,next_interupt,rchecksum());
2078 //rlist();
2079 //if(tracedebug) {
2080 //if(Count>=-2084597794) {
2081 if((signed int)Count>=-2084597794&&(signed int)Count<0) {
2082 //if(0) {
2083 printf("TRACE: count=%d next=%d (checksum %x)\n",Count,next_interupt,mchecksum());
2084 //printf("TRACE: count=%d next=%d (checksum %x) Status=%x\n",Count,next_interupt,mchecksum(),Status);
2085 //printf("TRACE: count=%d next=%d (checksum %x) hi=%8x%8x\n",Count,next_interupt,mchecksum(),(int)(reg[HIREG]>>32),(int)reg[HIREG]);
2086 rlist();
2087 #ifdef __i386__
2088 printf("TRACE: %x\n",(&i)[-1]);
2089 #endif
2090 #ifdef __arm__
2091 int j;
2092 printf("TRACE: %x \n",(&j)[10]);
2093 printf("TRACE: %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x\n",(&j)[1],(&j)[2],(&j)[3],(&j)[4],(&j)[5],(&j)[6],(&j)[7],(&j)[8],(&j)[9],(&j)[10],(&j)[11],(&j)[12],(&j)[13],(&j)[14],(&j)[15],(&j)[16],(&j)[17],(&j)[18],(&j)[19],(&j)[20]);
2094 #endif
2095 //fflush(stdout);
2096 }
2097 //printf("TRACE: %x\n",(&i)[-1]);
2098}
2099
2100void tlb_debug(u_int cause, u_int addr, u_int iaddr)
2101{
2102 printf("TLB Exception: instruction=%x addr=%x cause=%x\n",iaddr, addr, cause);
2103}
2104
2105void alu_assemble(int i,struct regstat *i_regs)
2106{
2107 if(opcode2[i]>=0x20&&opcode2[i]<=0x23) { // ADD/ADDU/SUB/SUBU
2108 if(rt1[i]) {
2109 signed char s1,s2,t;
2110 t=get_reg(i_regs->regmap,rt1[i]);
2111 if(t>=0) {
2112 s1=get_reg(i_regs->regmap,rs1[i]);
2113 s2=get_reg(i_regs->regmap,rs2[i]);
2114 if(rs1[i]&&rs2[i]) {
2115 assert(s1>=0);
2116 assert(s2>=0);
2117 if(opcode2[i]&2) emit_sub(s1,s2,t);
2118 else emit_add(s1,s2,t);
2119 }
2120 else if(rs1[i]) {
2121 if(s1>=0) emit_mov(s1,t);
2122 else emit_loadreg(rs1[i],t);
2123 }
2124 else if(rs2[i]) {
2125 if(s2>=0) {
2126 if(opcode2[i]&2) emit_neg(s2,t);
2127 else emit_mov(s2,t);
2128 }
2129 else {
2130 emit_loadreg(rs2[i],t);
2131 if(opcode2[i]&2) emit_neg(t,t);
2132 }
2133 }
2134 else emit_zeroreg(t);
2135 }
2136 }
2137 }
2138 if(opcode2[i]>=0x2c&&opcode2[i]<=0x2f) { // DADD/DADDU/DSUB/DSUBU
2139 if(rt1[i]) {
2140 signed char s1l,s2l,s1h,s2h,tl,th;
2141 tl=get_reg(i_regs->regmap,rt1[i]);
2142 th=get_reg(i_regs->regmap,rt1[i]|64);
2143 if(tl>=0) {
2144 s1l=get_reg(i_regs->regmap,rs1[i]);
2145 s2l=get_reg(i_regs->regmap,rs2[i]);
2146 s1h=get_reg(i_regs->regmap,rs1[i]|64);
2147 s2h=get_reg(i_regs->regmap,rs2[i]|64);
2148 if(rs1[i]&&rs2[i]) {
2149 assert(s1l>=0);
2150 assert(s2l>=0);
2151 if(opcode2[i]&2) emit_subs(s1l,s2l,tl);
2152 else emit_adds(s1l,s2l,tl);
2153 if(th>=0) {
2154 #ifdef INVERTED_CARRY
2155 if(opcode2[i]&2) {if(s1h!=th) emit_mov(s1h,th);emit_sbb(th,s2h);}
2156 #else
2157 if(opcode2[i]&2) emit_sbc(s1h,s2h,th);
2158 #endif
2159 else emit_add(s1h,s2h,th);
2160 }
2161 }
2162 else if(rs1[i]) {
2163 if(s1l>=0) emit_mov(s1l,tl);
2164 else emit_loadreg(rs1[i],tl);
2165 if(th>=0) {
2166 if(s1h>=0) emit_mov(s1h,th);
2167 else emit_loadreg(rs1[i]|64,th);
2168 }
2169 }
2170 else if(rs2[i]) {
2171 if(s2l>=0) {
2172 if(opcode2[i]&2) emit_negs(s2l,tl);
2173 else emit_mov(s2l,tl);
2174 }
2175 else {
2176 emit_loadreg(rs2[i],tl);
2177 if(opcode2[i]&2) emit_negs(tl,tl);
2178 }
2179 if(th>=0) {
2180 #ifdef INVERTED_CARRY
2181 if(s2h>=0) emit_mov(s2h,th);
2182 else emit_loadreg(rs2[i]|64,th);
2183 if(opcode2[i]&2) {
2184 emit_adcimm(-1,th); // x86 has inverted carry flag
2185 emit_not(th,th);
2186 }
2187 #else
2188 if(opcode2[i]&2) {
2189 if(s2h>=0) emit_rscimm(s2h,0,th);
2190 else {
2191 emit_loadreg(rs2[i]|64,th);
2192 emit_rscimm(th,0,th);
2193 }
2194 }else{
2195 if(s2h>=0) emit_mov(s2h,th);
2196 else emit_loadreg(rs2[i]|64,th);
2197 }
2198 #endif
2199 }
2200 }
2201 else {
2202 emit_zeroreg(tl);
2203 if(th>=0) emit_zeroreg(th);
2204 }
2205 }
2206 }
2207 }
2208 if(opcode2[i]==0x2a||opcode2[i]==0x2b) { // SLT/SLTU
2209 if(rt1[i]) {
2210 signed char s1l,s1h,s2l,s2h,t;
2211 if(!((i_regs->was32>>rs1[i])&(i_regs->was32>>rs2[i])&1))
2212 {
2213 t=get_reg(i_regs->regmap,rt1[i]);
2214 //assert(t>=0);
2215 if(t>=0) {
2216 s1l=get_reg(i_regs->regmap,rs1[i]);
2217 s1h=get_reg(i_regs->regmap,rs1[i]|64);
2218 s2l=get_reg(i_regs->regmap,rs2[i]);
2219 s2h=get_reg(i_regs->regmap,rs2[i]|64);
2220 if(rs2[i]==0) // rx<r0
2221 {
2222 assert(s1h>=0);
2223 if(opcode2[i]==0x2a) // SLT
2224 emit_shrimm(s1h,31,t);
2225 else // SLTU (unsigned can not be less than zero)
2226 emit_zeroreg(t);
2227 }
2228 else if(rs1[i]==0) // r0<rx
2229 {
2230 assert(s2h>=0);
2231 if(opcode2[i]==0x2a) // SLT
2232 emit_set_gz64_32(s2h,s2l,t);
2233 else // SLTU (set if not zero)
2234 emit_set_nz64_32(s2h,s2l,t);
2235 }
2236 else {
2237 assert(s1l>=0);assert(s1h>=0);
2238 assert(s2l>=0);assert(s2h>=0);
2239 if(opcode2[i]==0x2a) // SLT
2240 emit_set_if_less64_32(s1h,s1l,s2h,s2l,t);
2241 else // SLTU
2242 emit_set_if_carry64_32(s1h,s1l,s2h,s2l,t);
2243 }
2244 }
2245 } else {
2246 t=get_reg(i_regs->regmap,rt1[i]);
2247 //assert(t>=0);
2248 if(t>=0) {
2249 s1l=get_reg(i_regs->regmap,rs1[i]);
2250 s2l=get_reg(i_regs->regmap,rs2[i]);
2251 if(rs2[i]==0) // rx<r0
2252 {
2253 assert(s1l>=0);
2254 if(opcode2[i]==0x2a) // SLT
2255 emit_shrimm(s1l,31,t);
2256 else // SLTU (unsigned can not be less than zero)
2257 emit_zeroreg(t);
2258 }
2259 else if(rs1[i]==0) // r0<rx
2260 {
2261 assert(s2l>=0);
2262 if(opcode2[i]==0x2a) // SLT
2263 emit_set_gz32(s2l,t);
2264 else // SLTU (set if not zero)
2265 emit_set_nz32(s2l,t);
2266 }
2267 else{
2268 assert(s1l>=0);assert(s2l>=0);
2269 if(opcode2[i]==0x2a) // SLT
2270 emit_set_if_less32(s1l,s2l,t);
2271 else // SLTU
2272 emit_set_if_carry32(s1l,s2l,t);
2273 }
2274 }
2275 }
2276 }
2277 }
2278 if(opcode2[i]>=0x24&&opcode2[i]<=0x27) { // AND/OR/XOR/NOR
2279 if(rt1[i]) {
2280 signed char s1l,s1h,s2l,s2h,th,tl;
2281 tl=get_reg(i_regs->regmap,rt1[i]);
2282 th=get_reg(i_regs->regmap,rt1[i]|64);
2283 if(!((i_regs->was32>>rs1[i])&(i_regs->was32>>rs2[i])&1)&&th>=0)
2284 {
2285 assert(tl>=0);
2286 if(tl>=0) {
2287 s1l=get_reg(i_regs->regmap,rs1[i]);
2288 s1h=get_reg(i_regs->regmap,rs1[i]|64);
2289 s2l=get_reg(i_regs->regmap,rs2[i]);
2290 s2h=get_reg(i_regs->regmap,rs2[i]|64);
2291 if(rs1[i]&&rs2[i]) {
2292 assert(s1l>=0);assert(s1h>=0);
2293 assert(s2l>=0);assert(s2h>=0);
2294 if(opcode2[i]==0x24) { // AND
2295 emit_and(s1l,s2l,tl);
2296 emit_and(s1h,s2h,th);
2297 } else
2298 if(opcode2[i]==0x25) { // OR
2299 emit_or(s1l,s2l,tl);
2300 emit_or(s1h,s2h,th);
2301 } else
2302 if(opcode2[i]==0x26) { // XOR
2303 emit_xor(s1l,s2l,tl);
2304 emit_xor(s1h,s2h,th);
2305 } else
2306 if(opcode2[i]==0x27) { // NOR
2307 emit_or(s1l,s2l,tl);
2308 emit_or(s1h,s2h,th);
2309 emit_not(tl,tl);
2310 emit_not(th,th);
2311 }
2312 }
2313 else
2314 {
2315 if(opcode2[i]==0x24) { // AND
2316 emit_zeroreg(tl);
2317 emit_zeroreg(th);
2318 } else
2319 if(opcode2[i]==0x25||opcode2[i]==0x26) { // OR/XOR
2320 if(rs1[i]){
2321 if(s1l>=0) emit_mov(s1l,tl);
2322 else emit_loadreg(rs1[i],tl);
2323 if(s1h>=0) emit_mov(s1h,th);
2324 else emit_loadreg(rs1[i]|64,th);
2325 }
2326 else
2327 if(rs2[i]){
2328 if(s2l>=0) emit_mov(s2l,tl);
2329 else emit_loadreg(rs2[i],tl);
2330 if(s2h>=0) emit_mov(s2h,th);
2331 else emit_loadreg(rs2[i]|64,th);
2332 }
2333 else{
2334 emit_zeroreg(tl);
2335 emit_zeroreg(th);
2336 }
2337 } else
2338 if(opcode2[i]==0x27) { // NOR
2339 if(rs1[i]){
2340 if(s1l>=0) emit_not(s1l,tl);
2341 else{
2342 emit_loadreg(rs1[i],tl);
2343 emit_not(tl,tl);
2344 }
2345 if(s1h>=0) emit_not(s1h,th);
2346 else{
2347 emit_loadreg(rs1[i]|64,th);
2348 emit_not(th,th);
2349 }
2350 }
2351 else
2352 if(rs2[i]){
2353 if(s2l>=0) emit_not(s2l,tl);
2354 else{
2355 emit_loadreg(rs2[i],tl);
2356 emit_not(tl,tl);
2357 }
2358 if(s2h>=0) emit_not(s2h,th);
2359 else{
2360 emit_loadreg(rs2[i]|64,th);
2361 emit_not(th,th);
2362 }
2363 }
2364 else {
2365 emit_movimm(-1,tl);
2366 emit_movimm(-1,th);
2367 }
2368 }
2369 }
2370 }
2371 }
2372 else
2373 {
2374 // 32 bit
2375 if(tl>=0) {
2376 s1l=get_reg(i_regs->regmap,rs1[i]);
2377 s2l=get_reg(i_regs->regmap,rs2[i]);
2378 if(rs1[i]&&rs2[i]) {
2379 assert(s1l>=0);
2380 assert(s2l>=0);
2381 if(opcode2[i]==0x24) { // AND
2382 emit_and(s1l,s2l,tl);
2383 } else
2384 if(opcode2[i]==0x25) { // OR
2385 emit_or(s1l,s2l,tl);
2386 } else
2387 if(opcode2[i]==0x26) { // XOR
2388 emit_xor(s1l,s2l,tl);
2389 } else
2390 if(opcode2[i]==0x27) { // NOR
2391 emit_or(s1l,s2l,tl);
2392 emit_not(tl,tl);
2393 }
2394 }
2395 else
2396 {
2397 if(opcode2[i]==0x24) { // AND
2398 emit_zeroreg(tl);
2399 } else
2400 if(opcode2[i]==0x25||opcode2[i]==0x26) { // OR/XOR
2401 if(rs1[i]){
2402 if(s1l>=0) emit_mov(s1l,tl);
2403 else emit_loadreg(rs1[i],tl); // CHECK: regmap_entry?
2404 }
2405 else
2406 if(rs2[i]){
2407 if(s2l>=0) emit_mov(s2l,tl);
2408 else emit_loadreg(rs2[i],tl); // CHECK: regmap_entry?
2409 }
2410 else emit_zeroreg(tl);
2411 } else
2412 if(opcode2[i]==0x27) { // NOR
2413 if(rs1[i]){
2414 if(s1l>=0) emit_not(s1l,tl);
2415 else {
2416 emit_loadreg(rs1[i],tl);
2417 emit_not(tl,tl);
2418 }
2419 }
2420 else
2421 if(rs2[i]){
2422 if(s2l>=0) emit_not(s2l,tl);
2423 else {
2424 emit_loadreg(rs2[i],tl);
2425 emit_not(tl,tl);
2426 }
2427 }
2428 else emit_movimm(-1,tl);
2429 }
2430 }
2431 }
2432 }
2433 }
2434 }
2435}
2436
2437void imm16_assemble(int i,struct regstat *i_regs)
2438{
2439 if (opcode[i]==0x0f) { // LUI
2440 if(rt1[i]) {
2441 signed char t;
2442 t=get_reg(i_regs->regmap,rt1[i]);
2443 //assert(t>=0);
2444 if(t>=0) {
2445 if(!((i_regs->isconst>>t)&1))
2446 emit_movimm(imm[i]<<16,t);
2447 }
2448 }
2449 }
2450 if(opcode[i]==0x08||opcode[i]==0x09) { // ADDI/ADDIU
2451 if(rt1[i]) {
2452 signed char s,t;
2453 t=get_reg(i_regs->regmap,rt1[i]);
2454 s=get_reg(i_regs->regmap,rs1[i]);
2455 if(rs1[i]) {
2456 //assert(t>=0);
2457 //assert(s>=0);
2458 if(t>=0) {
2459 if(!((i_regs->isconst>>t)&1)) {
2460 if(s<0) {
2461 if(i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2462 emit_addimm(t,imm[i],t);
2463 }else{
2464 if(!((i_regs->wasconst>>s)&1))
2465 emit_addimm(s,imm[i],t);
2466 else
2467 emit_movimm(constmap[i][s]+imm[i],t);
2468 }
2469 }
2470 }
2471 } else {
2472 if(t>=0) {
2473 if(!((i_regs->isconst>>t)&1))
2474 emit_movimm(imm[i],t);
2475 }
2476 }
2477 }
2478 }
2479 if(opcode[i]==0x18||opcode[i]==0x19) { // DADDI/DADDIU
2480 if(rt1[i]) {
2481 signed char sh,sl,th,tl;
2482 th=get_reg(i_regs->regmap,rt1[i]|64);
2483 tl=get_reg(i_regs->regmap,rt1[i]);
2484 sh=get_reg(i_regs->regmap,rs1[i]|64);
2485 sl=get_reg(i_regs->regmap,rs1[i]);
2486 if(tl>=0) {
2487 if(rs1[i]) {
2488 assert(sh>=0);
2489 assert(sl>=0);
2490 if(th>=0) {
2491 emit_addimm64_32(sh,sl,imm[i],th,tl);
2492 }
2493 else {
2494 emit_addimm(sl,imm[i],tl);
2495 }
2496 } else {
2497 emit_movimm(imm[i],tl);
2498 if(th>=0) emit_movimm(((signed int)imm[i])>>31,th);
2499 }
2500 }
2501 }
2502 }
2503 else if(opcode[i]==0x0a||opcode[i]==0x0b) { // SLTI/SLTIU
2504 if(rt1[i]) {
2505 //assert(rs1[i]!=0); // r0 might be valid, but it's probably a bug
2506 signed char sh,sl,t;
2507 t=get_reg(i_regs->regmap,rt1[i]);
2508 sh=get_reg(i_regs->regmap,rs1[i]|64);
2509 sl=get_reg(i_regs->regmap,rs1[i]);
2510 //assert(t>=0);
2511 if(t>=0) {
2512 if(rs1[i]>0) {
2513 if(sh<0) assert((i_regs->was32>>rs1[i])&1);
2514 if(sh<0||((i_regs->was32>>rs1[i])&1)) {
2515 if(opcode[i]==0x0a) { // SLTI
2516 if(sl<0) {
2517 if(i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2518 emit_slti32(t,imm[i],t);
2519 }else{
2520 emit_slti32(sl,imm[i],t);
2521 }
2522 }
2523 else { // SLTIU
2524 if(sl<0) {
2525 if(i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2526 emit_sltiu32(t,imm[i],t);
2527 }else{
2528 emit_sltiu32(sl,imm[i],t);
2529 }
2530 }
2531 }else{ // 64-bit
2532 assert(sl>=0);
2533 if(opcode[i]==0x0a) // SLTI
2534 emit_slti64_32(sh,sl,imm[i],t);
2535 else // SLTIU
2536 emit_sltiu64_32(sh,sl,imm[i],t);
2537 }
2538 }else{
2539 // SLTI(U) with r0 is just stupid,
2540 // nonetheless examples can be found
2541 if(opcode[i]==0x0a) // SLTI
2542 if(0<imm[i]) emit_movimm(1,t);
2543 else emit_zeroreg(t);
2544 else // SLTIU
2545 {
2546 if(imm[i]) emit_movimm(1,t);
2547 else emit_zeroreg(t);
2548 }
2549 }
2550 }
2551 }
2552 }
2553 else if(opcode[i]>=0x0c&&opcode[i]<=0x0e) { // ANDI/ORI/XORI
2554 if(rt1[i]) {
2555 signed char sh,sl,th,tl;
2556 th=get_reg(i_regs->regmap,rt1[i]|64);
2557 tl=get_reg(i_regs->regmap,rt1[i]);
2558 sh=get_reg(i_regs->regmap,rs1[i]|64);
2559 sl=get_reg(i_regs->regmap,rs1[i]);
2560 if(tl>=0 && !((i_regs->isconst>>tl)&1)) {
2561 if(opcode[i]==0x0c) //ANDI
2562 {
2563 if(rs1[i]) {
2564 if(sl<0) {
2565 if(i_regs->regmap_entry[tl]!=rs1[i]) emit_loadreg(rs1[i],tl);
2566 emit_andimm(tl,imm[i],tl);
2567 }else{
2568 if(!((i_regs->wasconst>>sl)&1))
2569 emit_andimm(sl,imm[i],tl);
2570 else
2571 emit_movimm(constmap[i][sl]&imm[i],tl);
2572 }
2573 }
2574 else
2575 emit_zeroreg(tl);
2576 if(th>=0) emit_zeroreg(th);
2577 }
2578 else
2579 {
2580 if(rs1[i]) {
2581 if(sl<0) {
2582 if(i_regs->regmap_entry[tl]!=rs1[i]) emit_loadreg(rs1[i],tl);
2583 }
2584 if(th>=0) {
2585 if(sh<0) {
2586 emit_loadreg(rs1[i]|64,th);
2587 }else{
2588 emit_mov(sh,th);
2589 }
2590 }
2591 if(opcode[i]==0x0d) //ORI
2592 if(sl<0) {
2593 emit_orimm(tl,imm[i],tl);
2594 }else{
2595 if(!((i_regs->wasconst>>sl)&1))
2596 emit_orimm(sl,imm[i],tl);
2597 else
2598 emit_movimm(constmap[i][sl]|imm[i],tl);
2599 }
2600 if(opcode[i]==0x0e) //XORI
2601 if(sl<0) {
2602 emit_xorimm(tl,imm[i],tl);
2603 }else{
2604 if(!((i_regs->wasconst>>sl)&1))
2605 emit_xorimm(sl,imm[i],tl);
2606 else
2607 emit_movimm(constmap[i][sl]^imm[i],tl);
2608 }
2609 }
2610 else {
2611 emit_movimm(imm[i],tl);
2612 if(th>=0) emit_zeroreg(th);
2613 }
2614 }
2615 }
2616 }
2617 }
2618}
2619
2620void shiftimm_assemble(int i,struct regstat *i_regs)
2621{
2622 if(opcode2[i]<=0x3) // SLL/SRL/SRA
2623 {
2624 if(rt1[i]) {
2625 signed char s,t;
2626 t=get_reg(i_regs->regmap,rt1[i]);
2627 s=get_reg(i_regs->regmap,rs1[i]);
2628 //assert(t>=0);
2629 if(t>=0){
2630 if(rs1[i]==0)
2631 {
2632 emit_zeroreg(t);
2633 }
2634 else
2635 {
2636 if(s<0&&i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2637 if(imm[i]) {
2638 if(opcode2[i]==0) // SLL
2639 {
2640 emit_shlimm(s<0?t:s,imm[i],t);
2641 }
2642 if(opcode2[i]==2) // SRL
2643 {
2644 emit_shrimm(s<0?t:s,imm[i],t);
2645 }
2646 if(opcode2[i]==3) // SRA
2647 {
2648 emit_sarimm(s<0?t:s,imm[i],t);
2649 }
2650 }else{
2651 // Shift by zero
2652 if(s>=0 && s!=t) emit_mov(s,t);
2653 }
2654 }
2655 }
2656 //emit_storereg(rt1[i],t); //DEBUG
2657 }
2658 }
2659 if(opcode2[i]>=0x38&&opcode2[i]<=0x3b) // DSLL/DSRL/DSRA
2660 {
2661 if(rt1[i]) {
2662 signed char sh,sl,th,tl;
2663 th=get_reg(i_regs->regmap,rt1[i]|64);
2664 tl=get_reg(i_regs->regmap,rt1[i]);
2665 sh=get_reg(i_regs->regmap,rs1[i]|64);
2666 sl=get_reg(i_regs->regmap,rs1[i]);
2667 if(tl>=0) {
2668 if(rs1[i]==0)
2669 {
2670 emit_zeroreg(tl);
2671 if(th>=0) emit_zeroreg(th);
2672 }
2673 else
2674 {
2675 assert(sl>=0);
2676 assert(sh>=0);
2677 if(imm[i]) {
2678 if(opcode2[i]==0x38) // DSLL
2679 {
2680 if(th>=0) emit_shldimm(sh,sl,imm[i],th);
2681 emit_shlimm(sl,imm[i],tl);
2682 }
2683 if(opcode2[i]==0x3a) // DSRL
2684 {
2685 emit_shrdimm(sl,sh,imm[i],tl);
2686 if(th>=0) emit_shrimm(sh,imm[i],th);
2687 }
2688 if(opcode2[i]==0x3b) // DSRA
2689 {
2690 emit_shrdimm(sl,sh,imm[i],tl);
2691 if(th>=0) emit_sarimm(sh,imm[i],th);
2692 }
2693 }else{
2694 // Shift by zero
2695 if(sl!=tl) emit_mov(sl,tl);
2696 if(th>=0&&sh!=th) emit_mov(sh,th);
2697 }
2698 }
2699 }
2700 }
2701 }
2702 if(opcode2[i]==0x3c) // DSLL32
2703 {
2704 if(rt1[i]) {
2705 signed char sl,tl,th;
2706 tl=get_reg(i_regs->regmap,rt1[i]);
2707 th=get_reg(i_regs->regmap,rt1[i]|64);
2708 sl=get_reg(i_regs->regmap,rs1[i]);
2709 if(th>=0||tl>=0){
2710 assert(tl>=0);
2711 assert(th>=0);
2712 assert(sl>=0);
2713 emit_mov(sl,th);
2714 emit_zeroreg(tl);
2715 if(imm[i]>32)
2716 {
2717 emit_shlimm(th,imm[i]&31,th);
2718 }
2719 }
2720 }
2721 }
2722 if(opcode2[i]==0x3e) // DSRL32
2723 {
2724 if(rt1[i]) {
2725 signed char sh,tl,th;
2726 tl=get_reg(i_regs->regmap,rt1[i]);
2727 th=get_reg(i_regs->regmap,rt1[i]|64);
2728 sh=get_reg(i_regs->regmap,rs1[i]|64);
2729 if(tl>=0){
2730 assert(sh>=0);
2731 emit_mov(sh,tl);
2732 if(th>=0) emit_zeroreg(th);
2733 if(imm[i]>32)
2734 {
2735 emit_shrimm(tl,imm[i]&31,tl);
2736 }
2737 }
2738 }
2739 }
2740 if(opcode2[i]==0x3f) // DSRA32
2741 {
2742 if(rt1[i]) {
2743 signed char sh,tl;
2744 tl=get_reg(i_regs->regmap,rt1[i]);
2745 sh=get_reg(i_regs->regmap,rs1[i]|64);
2746 if(tl>=0){
2747 assert(sh>=0);
2748 emit_mov(sh,tl);
2749 if(imm[i]>32)
2750 {
2751 emit_sarimm(tl,imm[i]&31,tl);
2752 }
2753 }
2754 }
2755 }
2756}
2757
2758#ifndef shift_assemble
2759void shift_assemble(int i,struct regstat *i_regs)
2760{
2761 printf("Need shift_assemble for this architecture.\n");
2762 exit(1);
2763}
2764#endif
2765
2766void load_assemble(int i,struct regstat *i_regs)
2767{
2768 int s,th,tl,addr,map=-1;
2769 int offset;
2770 int jaddr=0;
5bf843dc 2771 int memtarget=0,c=0;
57871462 2772 u_int hr,reglist=0;
2773 th=get_reg(i_regs->regmap,rt1[i]|64);
2774 tl=get_reg(i_regs->regmap,rt1[i]);
2775 s=get_reg(i_regs->regmap,rs1[i]);
2776 offset=imm[i];
2777 for(hr=0;hr<HOST_REGS;hr++) {
2778 if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
2779 }
2780 if(i_regs->regmap[HOST_CCREG]==CCREG) reglist&=~(1<<HOST_CCREG);
2781 if(s>=0) {
2782 c=(i_regs->wasconst>>s)&1;
4cb76aa4 2783 memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
57871462 2784 if(using_tlb&&((signed int)(constmap[i][s]+offset))>=(signed int)0xC0000000) memtarget=1;
2785 }
57871462 2786 //printf("load_assemble: c=%d\n",c);
2787 //if(c) printf("load_assemble: const=%x\n",(int)constmap[i][s]+offset);
2788 // FIXME: Even if the load is a NOP, we should check for pagefaults...
5bf843dc 2789#ifdef PCSX
f18c0f46 2790 if(tl<0&&(!c||(((u_int)constmap[i][s]+offset)>>16)==0x1f80)
2791 ||rt1[i]==0) {
5bf843dc 2792 // could be FIFO, must perform the read
f18c0f46 2793 // ||dummy read
5bf843dc 2794 assem_debug("(forced read)\n");
2795 tl=get_reg(i_regs->regmap,-1);
2796 assert(tl>=0);
5bf843dc 2797 }
f18c0f46 2798#endif
5bf843dc 2799 if(offset||s<0||c) addr=tl;
2800 else addr=s;
535d208a 2801 //if(tl<0) tl=get_reg(i_regs->regmap,-1);
2802 if(tl>=0) {
2803 //printf("load_assemble: c=%d\n",c);
2804 //if(c) printf("load_assemble: const=%x\n",(int)constmap[i][s]+offset);
2805 assert(tl>=0); // Even if the load is a NOP, we must check for pagefaults and I/O
2806 reglist&=~(1<<tl);
2807 if(th>=0) reglist&=~(1<<th);
2808 if(!using_tlb) {
2809 if(!c) {
2810 #ifdef RAM_OFFSET
2811 map=get_reg(i_regs->regmap,ROREG);
2812 if(map<0) emit_loadreg(ROREG,map=HOST_TEMPREG);
2813 #endif
57871462 2814//#define R29_HACK 1
535d208a 2815 #ifdef R29_HACK
2816 // Strmnnrmn's speed hack
2817 if(rs1[i]!=29||start<0x80001000||start>=0x80000000+RAM_SIZE)
2818 #endif
2819 {
2820 emit_cmpimm(addr,RAM_SIZE);
2821 jaddr=(int)out;
2822 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
2823 // Hint to branch predictor that the branch is unlikely to be taken
2824 if(rs1[i]>=28)
2825 emit_jno_unlikely(0);
2826 else
57871462 2827 #endif
535d208a 2828 emit_jno(0);
57871462 2829 }
535d208a 2830 }
2831 }else{ // using tlb
2832 int x=0;
2833 if (opcode[i]==0x20||opcode[i]==0x24) x=3; // LB/LBU
2834 if (opcode[i]==0x21||opcode[i]==0x25) x=2; // LH/LHU
2835 map=get_reg(i_regs->regmap,TLREG);
2836 assert(map>=0);
2837 map=do_tlb_r(addr,tl,map,x,-1,-1,c,constmap[i][s]+offset);
2838 do_tlb_r_branch(map,c,constmap[i][s]+offset,&jaddr);
2839 }
2840 int dummy=(rt1[i]==0)||(tl!=get_reg(i_regs->regmap,rt1[i])); // ignore loads to r0 and unneeded reg
2841 if (opcode[i]==0x20) { // LB
2842 if(!c||memtarget) {
2843 if(!dummy) {
57871462 2844 #ifdef HOST_IMM_ADDR32
2845 if(c)
2846 emit_movsbl_tlb((constmap[i][s]+offset)^3,map,tl);
2847 else
2848 #endif
2849 {
2850 //emit_xorimm(addr,3,tl);
2851 //gen_tlb_addr_r(tl,map);
2852 //emit_movsbl_indexed((int)rdram-0x80000000,tl,tl);
535d208a 2853 int x=0,a=tl;
2002a1db 2854#ifdef BIG_ENDIAN_MIPS
57871462 2855 if(!c) emit_xorimm(addr,3,tl);
2856 else x=((constmap[i][s]+offset)^3)-(constmap[i][s]+offset);
2002a1db 2857#else
535d208a 2858 if(!c) a=addr;
2002a1db 2859#endif
535d208a 2860 emit_movsbl_indexed_tlb(x,a,map,tl);
57871462 2861 }
57871462 2862 }
535d208a 2863 if(jaddr)
2864 add_stub(LOADB_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
57871462 2865 }
535d208a 2866 else
2867 inline_readstub(LOADB_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2868 }
2869 if (opcode[i]==0x21) { // LH
2870 if(!c||memtarget) {
2871 if(!dummy) {
57871462 2872 #ifdef HOST_IMM_ADDR32
2873 if(c)
2874 emit_movswl_tlb((constmap[i][s]+offset)^2,map,tl);
2875 else
2876 #endif
2877 {
535d208a 2878 int x=0,a=tl;
2002a1db 2879#ifdef BIG_ENDIAN_MIPS
57871462 2880 if(!c) emit_xorimm(addr,2,tl);
2881 else x=((constmap[i][s]+offset)^2)-(constmap[i][s]+offset);
2002a1db 2882#else
535d208a 2883 if(!c) a=addr;
2002a1db 2884#endif
57871462 2885 //#ifdef
2886 //emit_movswl_indexed_tlb(x,tl,map,tl);
2887 //else
2888 if(map>=0) {
535d208a 2889 gen_tlb_addr_r(a,map);
2890 emit_movswl_indexed(x,a,tl);
2891 }else{
2892 #ifdef RAM_OFFSET
2893 emit_movswl_indexed(x,a,tl);
2894 #else
2895 emit_movswl_indexed((int)rdram-0x80000000+x,a,tl);
2896 #endif
2897 }
57871462 2898 }
57871462 2899 }
535d208a 2900 if(jaddr)
2901 add_stub(LOADH_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
57871462 2902 }
535d208a 2903 else
2904 inline_readstub(LOADH_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2905 }
2906 if (opcode[i]==0x23) { // LW
2907 if(!c||memtarget) {
2908 if(!dummy) {
57871462 2909 //emit_readword_indexed((int)rdram-0x80000000,addr,tl);
2910 #ifdef HOST_IMM_ADDR32
2911 if(c)
2912 emit_readword_tlb(constmap[i][s]+offset,map,tl);
2913 else
2914 #endif
2915 emit_readword_indexed_tlb(0,addr,map,tl);
57871462 2916 }
535d208a 2917 if(jaddr)
2918 add_stub(LOADW_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
57871462 2919 }
535d208a 2920 else
2921 inline_readstub(LOADW_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2922 }
2923 if (opcode[i]==0x24) { // LBU
2924 if(!c||memtarget) {
2925 if(!dummy) {
57871462 2926 #ifdef HOST_IMM_ADDR32
2927 if(c)
2928 emit_movzbl_tlb((constmap[i][s]+offset)^3,map,tl);
2929 else
2930 #endif
2931 {
2932 //emit_xorimm(addr,3,tl);
2933 //gen_tlb_addr_r(tl,map);
2934 //emit_movzbl_indexed((int)rdram-0x80000000,tl,tl);
535d208a 2935 int x=0,a=tl;
2002a1db 2936#ifdef BIG_ENDIAN_MIPS
57871462 2937 if(!c) emit_xorimm(addr,3,tl);
2938 else x=((constmap[i][s]+offset)^3)-(constmap[i][s]+offset);
2002a1db 2939#else
535d208a 2940 if(!c) a=addr;
2002a1db 2941#endif
535d208a 2942 emit_movzbl_indexed_tlb(x,a,map,tl);
57871462 2943 }
57871462 2944 }
535d208a 2945 if(jaddr)
2946 add_stub(LOADBU_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
57871462 2947 }
535d208a 2948 else
2949 inline_readstub(LOADBU_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2950 }
2951 if (opcode[i]==0x25) { // LHU
2952 if(!c||memtarget) {
2953 if(!dummy) {
57871462 2954 #ifdef HOST_IMM_ADDR32
2955 if(c)
2956 emit_movzwl_tlb((constmap[i][s]+offset)^2,map,tl);
2957 else
2958 #endif
2959 {
535d208a 2960 int x=0,a=tl;
2002a1db 2961#ifdef BIG_ENDIAN_MIPS
57871462 2962 if(!c) emit_xorimm(addr,2,tl);
2963 else x=((constmap[i][s]+offset)^2)-(constmap[i][s]+offset);
2002a1db 2964#else
535d208a 2965 if(!c) a=addr;
2002a1db 2966#endif
57871462 2967 //#ifdef
2968 //emit_movzwl_indexed_tlb(x,tl,map,tl);
2969 //#else
2970 if(map>=0) {
535d208a 2971 gen_tlb_addr_r(a,map);
2972 emit_movzwl_indexed(x,a,tl);
2973 }else{
2974 #ifdef RAM_OFFSET
2975 emit_movzwl_indexed(x,a,tl);
2976 #else
2977 emit_movzwl_indexed((int)rdram-0x80000000+x,a,tl);
2978 #endif
2979 }
57871462 2980 }
2981 }
535d208a 2982 if(jaddr)
2983 add_stub(LOADHU_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
57871462 2984 }
535d208a 2985 else
2986 inline_readstub(LOADHU_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2987 }
2988 if (opcode[i]==0x27) { // LWU
2989 assert(th>=0);
2990 if(!c||memtarget) {
2991 if(!dummy) {
57871462 2992 //emit_readword_indexed((int)rdram-0x80000000,addr,tl);
2993 #ifdef HOST_IMM_ADDR32
2994 if(c)
2995 emit_readword_tlb(constmap[i][s]+offset,map,tl);
2996 else
2997 #endif
2998 emit_readword_indexed_tlb(0,addr,map,tl);
57871462 2999 }
535d208a 3000 if(jaddr)
3001 add_stub(LOADW_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
3002 }
3003 else {
3004 inline_readstub(LOADW_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
57871462 3005 }
535d208a 3006 emit_zeroreg(th);
3007 }
3008 if (opcode[i]==0x37) { // LD
3009 if(!c||memtarget) {
3010 if(!dummy) {
57871462 3011 //gen_tlb_addr_r(tl,map);
3012 //if(th>=0) emit_readword_indexed((int)rdram-0x80000000,addr,th);
3013 //emit_readword_indexed((int)rdram-0x7FFFFFFC,addr,tl);
3014 #ifdef HOST_IMM_ADDR32
3015 if(c)
3016 emit_readdword_tlb(constmap[i][s]+offset,map,th,tl);
3017 else
3018 #endif
3019 emit_readdword_indexed_tlb(0,addr,map,th,tl);
57871462 3020 }
535d208a 3021 if(jaddr)
3022 add_stub(LOADD_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
57871462 3023 }
535d208a 3024 else
3025 inline_readstub(LOADD_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
57871462 3026 }
535d208a 3027 }
3028 //emit_storereg(rt1[i],tl); // DEBUG
57871462 3029 //if(opcode[i]==0x23)
3030 //if(opcode[i]==0x24)
3031 //if(opcode[i]==0x23||opcode[i]==0x24)
3032 /*if(opcode[i]==0x21||opcode[i]==0x23||opcode[i]==0x24)
3033 {
3034 //emit_pusha();
3035 save_regs(0x100f);
3036 emit_readword((int)&last_count,ECX);
3037 #ifdef __i386__
3038 if(get_reg(i_regs->regmap,CCREG)<0)
3039 emit_loadreg(CCREG,HOST_CCREG);
3040 emit_add(HOST_CCREG,ECX,HOST_CCREG);
3041 emit_addimm(HOST_CCREG,2*ccadj[i],HOST_CCREG);
3042 emit_writeword(HOST_CCREG,(int)&Count);
3043 #endif
3044 #ifdef __arm__
3045 if(get_reg(i_regs->regmap,CCREG)<0)
3046 emit_loadreg(CCREG,0);
3047 else
3048 emit_mov(HOST_CCREG,0);
3049 emit_add(0,ECX,0);
3050 emit_addimm(0,2*ccadj[i],0);
3051 emit_writeword(0,(int)&Count);
3052 #endif
3053 emit_call((int)memdebug);
3054 //emit_popa();
3055 restore_regs(0x100f);
3056 }/**/
3057}
3058
3059#ifndef loadlr_assemble
3060void loadlr_assemble(int i,struct regstat *i_regs)
3061{
3062 printf("Need loadlr_assemble for this architecture.\n");
3063 exit(1);
3064}
3065#endif
3066
3067void store_assemble(int i,struct regstat *i_regs)
3068{
3069 int s,th,tl,map=-1;
3070 int addr,temp;
3071 int offset;
3072 int jaddr=0,jaddr2,type;
666a299d 3073 int memtarget=0,c=0;
57871462 3074 int agr=AGEN1+(i&1);
3075 u_int hr,reglist=0;
3076 th=get_reg(i_regs->regmap,rs2[i]|64);
3077 tl=get_reg(i_regs->regmap,rs2[i]);
3078 s=get_reg(i_regs->regmap,rs1[i]);
3079 temp=get_reg(i_regs->regmap,agr);
3080 if(temp<0) temp=get_reg(i_regs->regmap,-1);
3081 offset=imm[i];
3082 if(s>=0) {
3083 c=(i_regs->wasconst>>s)&1;
4cb76aa4 3084 memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
57871462 3085 if(using_tlb&&((signed int)(constmap[i][s]+offset))>=(signed int)0xC0000000) memtarget=1;
3086 }
3087 assert(tl>=0);
3088 assert(temp>=0);
3089 for(hr=0;hr<HOST_REGS;hr++) {
3090 if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
3091 }
3092 if(i_regs->regmap[HOST_CCREG]==CCREG) reglist&=~(1<<HOST_CCREG);
3093 if(offset||s<0||c) addr=temp;
3094 else addr=s;
3095 if(!using_tlb) {
3096 if(!c) {
3097 #ifdef R29_HACK
3098 // Strmnnrmn's speed hack
3099 memtarget=1;
4cb76aa4 3100 if(rs1[i]!=29||start<0x80001000||start>=0x80000000+RAM_SIZE)
57871462 3101 #endif
4cb76aa4 3102 emit_cmpimm(addr,RAM_SIZE);
57871462 3103 #ifdef DESTRUCTIVE_SHIFT
3104 if(s==addr) emit_mov(s,temp);
3105 #endif
3106 #ifdef R29_HACK
4cb76aa4 3107 if(rs1[i]!=29||start<0x80001000||start>=0x80000000+RAM_SIZE)
57871462 3108 #endif
3109 {
3110 jaddr=(int)out;
3111 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
3112 // Hint to branch predictor that the branch is unlikely to be taken
3113 if(rs1[i]>=28)
3114 emit_jno_unlikely(0);
3115 else
3116 #endif
3117 emit_jno(0);
3118 }
3119 }
3120 }else{ // using tlb
3121 int x=0;
3122 if (opcode[i]==0x28) x=3; // SB
3123 if (opcode[i]==0x29) x=2; // SH
3124 map=get_reg(i_regs->regmap,TLREG);
3125 assert(map>=0);
3126 map=do_tlb_w(addr,temp,map,x,c,constmap[i][s]+offset);
3127 do_tlb_w_branch(map,c,constmap[i][s]+offset,&jaddr);
3128 }
3129
3130 if (opcode[i]==0x28) { // SB
3131 if(!c||memtarget) {
97a238a6 3132 int x=0,a=temp;
2002a1db 3133#ifdef BIG_ENDIAN_MIPS
57871462 3134 if(!c) emit_xorimm(addr,3,temp);
3135 else x=((constmap[i][s]+offset)^3)-(constmap[i][s]+offset);
2002a1db 3136#else
97a238a6 3137 if(!c) a=addr;
2002a1db 3138#endif
57871462 3139 //gen_tlb_addr_w(temp,map);
3140 //emit_writebyte_indexed(tl,(int)rdram-0x80000000,temp);
97a238a6 3141 emit_writebyte_indexed_tlb(tl,x,a,map,a);
57871462 3142 }
3143 type=STOREB_STUB;
3144 }
3145 if (opcode[i]==0x29) { // SH
3146 if(!c||memtarget) {
97a238a6 3147 int x=0,a=temp;
2002a1db 3148#ifdef BIG_ENDIAN_MIPS
57871462 3149 if(!c) emit_xorimm(addr,2,temp);
3150 else x=((constmap[i][s]+offset)^2)-(constmap[i][s]+offset);
2002a1db 3151#else
97a238a6 3152 if(!c) a=addr;
2002a1db 3153#endif
57871462 3154 //#ifdef
3155 //emit_writehword_indexed_tlb(tl,x,temp,map,temp);
3156 //#else
3157 if(map>=0) {
97a238a6 3158 gen_tlb_addr_w(a,map);
3159 emit_writehword_indexed(tl,x,a);
57871462 3160 }else
97a238a6 3161 emit_writehword_indexed(tl,(int)rdram-0x80000000+x,a);
57871462 3162 }
3163 type=STOREH_STUB;
3164 }
3165 if (opcode[i]==0x2B) { // SW
3166 if(!c||memtarget)
3167 //emit_writeword_indexed(tl,(int)rdram-0x80000000,addr);
3168 emit_writeword_indexed_tlb(tl,0,addr,map,temp);
3169 type=STOREW_STUB;
3170 }
3171 if (opcode[i]==0x3F) { // SD
3172 if(!c||memtarget) {
3173 if(rs2[i]) {
3174 assert(th>=0);
3175 //emit_writeword_indexed(th,(int)rdram-0x80000000,addr);
3176 //emit_writeword_indexed(tl,(int)rdram-0x7FFFFFFC,addr);
3177 emit_writedword_indexed_tlb(th,tl,0,addr,map,temp);
3178 }else{
3179 // Store zero
3180 //emit_writeword_indexed(tl,(int)rdram-0x80000000,temp);
3181 //emit_writeword_indexed(tl,(int)rdram-0x7FFFFFFC,temp);
3182 emit_writedword_indexed_tlb(tl,tl,0,addr,map,temp);
3183 }
3184 }
3185 type=STORED_STUB;
3186 }
57871462 3187 if(!using_tlb) {
3188 if(!c||memtarget) {
3189 #ifdef DESTRUCTIVE_SHIFT
3190 // The x86 shift operation is 'destructive'; it overwrites the
3191 // source register, so we need to make a copy first and use that.
3192 addr=temp;
3193 #endif
3194 #if defined(HOST_IMM8)
3195 int ir=get_reg(i_regs->regmap,INVCP);
3196 assert(ir>=0);
3197 emit_cmpmem_indexedsr12_reg(ir,addr,1);
3198 #else
3199 emit_cmpmem_indexedsr12_imm((int)invalid_code,addr,1);
3200 #endif
0bbd1454 3201 #if defined(HAVE_CONDITIONAL_CALL) && !defined(DESTRUCTIVE_SHIFT)
3202 emit_callne(invalidate_addr_reg[addr]);
3203 #else
57871462 3204 jaddr2=(int)out;
3205 emit_jne(0);
3206 add_stub(INVCODE_STUB,jaddr2,(int)out,reglist|(1<<HOST_CCREG),addr,0,0,0);
0bbd1454 3207 #endif
57871462 3208 }
3209 }
3eaa7048 3210 if(jaddr) {
3211 add_stub(type,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
3212 } else if(c&&!memtarget) {
3213 inline_writestub(type,i,constmap[i][s]+offset,i_regs->regmap,rs2[i],ccadj[i],reglist);
3214 }
57871462 3215 //if(opcode[i]==0x2B || opcode[i]==0x3F)
3216 //if(opcode[i]==0x2B || opcode[i]==0x28)
3217 //if(opcode[i]==0x2B || opcode[i]==0x29)
3218 //if(opcode[i]==0x2B)
3219 /*if(opcode[i]==0x2B || opcode[i]==0x28 || opcode[i]==0x29 || opcode[i]==0x3F)
3220 {
3221 //emit_pusha();
3222 save_regs(0x100f);
3223 emit_readword((int)&last_count,ECX);
3224 #ifdef __i386__
3225 if(get_reg(i_regs->regmap,CCREG)<0)
3226 emit_loadreg(CCREG,HOST_CCREG);
3227 emit_add(HOST_CCREG,ECX,HOST_CCREG);
3228 emit_addimm(HOST_CCREG,2*ccadj[i],HOST_CCREG);
3229 emit_writeword(HOST_CCREG,(int)&Count);
3230 #endif
3231 #ifdef __arm__
3232 if(get_reg(i_regs->regmap,CCREG)<0)
3233 emit_loadreg(CCREG,0);
3234 else
3235 emit_mov(HOST_CCREG,0);
3236 emit_add(0,ECX,0);
3237 emit_addimm(0,2*ccadj[i],0);
3238 emit_writeword(0,(int)&Count);
3239 #endif
3240 emit_call((int)memdebug);
3241 //emit_popa();
3242 restore_regs(0x100f);
3243 }/**/
3244}
3245
3246void storelr_assemble(int i,struct regstat *i_regs)
3247{
3248 int s,th,tl;
3249 int temp;
3250 int temp2;
3251 int offset;
3252 int jaddr=0,jaddr2;
3253 int case1,case2,case3;
3254 int done0,done1,done2;
3255 int memtarget,c=0;
fab5d06d 3256 int agr=AGEN1+(i&1);
57871462 3257 u_int hr,reglist=0;
3258 th=get_reg(i_regs->regmap,rs2[i]|64);
3259 tl=get_reg(i_regs->regmap,rs2[i]);
3260 s=get_reg(i_regs->regmap,rs1[i]);
fab5d06d 3261 temp=get_reg(i_regs->regmap,agr);
3262 if(temp<0) temp=get_reg(i_regs->regmap,-1);
57871462 3263 offset=imm[i];
3264 if(s>=0) {
3265 c=(i_regs->isconst>>s)&1;
4cb76aa4 3266 memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
57871462 3267 if(using_tlb&&((signed int)(constmap[i][s]+offset))>=(signed int)0xC0000000) memtarget=1;
3268 }
3269 assert(tl>=0);
3270 for(hr=0;hr<HOST_REGS;hr++) {
3271 if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
3272 }
535d208a 3273 assert(temp>=0);
3274 if(!using_tlb) {
3275 if(!c) {
3276 emit_cmpimm(s<0||offset?temp:s,RAM_SIZE);
3277 if(!offset&&s!=temp) emit_mov(s,temp);
3278 jaddr=(int)out;
3279 emit_jno(0);
3280 }
3281 else
3282 {
3283 if(!memtarget||!rs1[i]) {
57871462 3284 jaddr=(int)out;
3285 emit_jmp(0);
3286 }
57871462 3287 }
535d208a 3288 #ifdef RAM_OFFSET
3289 int map=get_reg(i_regs->regmap,ROREG);
3290 if(map<0) emit_loadreg(ROREG,map=HOST_TEMPREG);
3291 gen_tlb_addr_w(temp,map);
3292 #else
3293 if((u_int)rdram!=0x80000000)
3294 emit_addimm_no_flags((u_int)rdram-(u_int)0x80000000,temp);
3295 #endif
3296 }else{ // using tlb
3297 int map=get_reg(i_regs->regmap,TLREG);
3298 assert(map>=0);
3299 map=do_tlb_w(c||s<0||offset?temp:s,temp,map,0,c,constmap[i][s]+offset);
3300 if(!c&&!offset&&s>=0) emit_mov(s,temp);
3301 do_tlb_w_branch(map,c,constmap[i][s]+offset,&jaddr);
3302 if(!jaddr&&!memtarget) {
3303 jaddr=(int)out;
3304 emit_jmp(0);
57871462 3305 }
535d208a 3306 gen_tlb_addr_w(temp,map);
3307 }
3308
3309 if (opcode[i]==0x2C||opcode[i]==0x2D) { // SDL/SDR
3310 temp2=get_reg(i_regs->regmap,FTEMP);
3311 if(!rs2[i]) temp2=th=tl;
3312 }
57871462 3313
2002a1db 3314#ifndef BIG_ENDIAN_MIPS
3315 emit_xorimm(temp,3,temp);
3316#endif
535d208a 3317 emit_testimm(temp,2);
3318 case2=(int)out;
3319 emit_jne(0);
3320 emit_testimm(temp,1);
3321 case1=(int)out;
3322 emit_jne(0);
3323 // 0
3324 if (opcode[i]==0x2A) { // SWL
3325 emit_writeword_indexed(tl,0,temp);
3326 }
3327 if (opcode[i]==0x2E) { // SWR
3328 emit_writebyte_indexed(tl,3,temp);
3329 }
3330 if (opcode[i]==0x2C) { // SDL
3331 emit_writeword_indexed(th,0,temp);
3332 if(rs2[i]) emit_mov(tl,temp2);
3333 }
3334 if (opcode[i]==0x2D) { // SDR
3335 emit_writebyte_indexed(tl,3,temp);
3336 if(rs2[i]) emit_shldimm(th,tl,24,temp2);
3337 }
3338 done0=(int)out;
3339 emit_jmp(0);
3340 // 1