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[picodrive.git] / Pico / PicoInt.h
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eff55556 1// Pico Library - Internal Header File\r
cc68a136 2\r
3// (c) Copyright 2004 Dave, All rights reserved.\r
6cadc2da 4// (c) Copyright 2006,2007 Grazvydas "notaz" Ignotas, all rights reserved.\r
cc68a136 5// Free for non-commercial use.\r
6\r
7// For commercial use, separate licencing terms must be obtained.\r
8\r
eff55556 9#ifndef PICO_INTERNAL_INCLUDED\r
10#define PICO_INTERNAL_INCLUDED\r
cc68a136 11\r
12#include <stdio.h>\r
13#include <stdlib.h>\r
14#include <string.h>\r
15#include "Pico.h"\r
f53f286a 16#include "carthw/carthw.h"\r
cc68a136 17\r
89fa852d 18//\r
19#define USE_POLL_DETECT\r
20\r
eff55556 21#ifndef PICO_INTERNAL\r
22#define PICO_INTERNAL\r
23#endif\r
24#ifndef PICO_INTERNAL_ASM\r
25#define PICO_INTERNAL_ASM\r
26#endif\r
cc68a136 27\r
70357ce5 28// to select core, define EMU_C68K, EMU_M68K or EMU_F68K in your makefile or project\r
cc68a136 29\r
30#ifdef __cplusplus\r
31extern "C" {\r
32#endif\r
33\r
34\r
35// ----------------------- 68000 CPU -----------------------\r
36#ifdef EMU_C68K\r
37#include "../cpu/Cyclone/Cyclone.h"\r
3aa1e148 38extern struct Cyclone PicoCpuCM68k, PicoCpuCS68k;\r
39#define SekCyclesLeftNoMCD PicoCpuCM68k.cycles // cycles left for this run\r
7336a99a 40#define SekCyclesLeft \\r
41 (((PicoMCD&1) && (PicoOpt & 0x2000)) ? (SekCycleAim-SekCycleCnt) : SekCyclesLeftNoMCD)\r
7a1f6e45 42#define SekCyclesLeftS68k \\r
3aa1e148 43 ((PicoOpt & 0x2000) ? (SekCycleAimS68k-SekCycleCntS68k) : PicoCpuCS68k.cycles)\r
44#define SekSetCyclesLeftNoMCD(c) PicoCpuCM68k.cycles=c\r
7336a99a 45#define SekSetCyclesLeft(c) { \\r
46 if ((PicoMCD&1) && (PicoOpt & 0x2000)) SekCycleCnt=SekCycleAim-(c); else SekSetCyclesLeftNoMCD(c); \\r
47}\r
3aa1e148 48#define SekPc (PicoCpuCM68k.pc-PicoCpuCM68k.membase)\r
49#define SekPcS68k (PicoCpuCS68k.pc-PicoCpuCS68k.membase)\r
50#define SekSetStop(x) { PicoCpuCM68k.state_flags&=~1; if (x) { PicoCpuCM68k.state_flags|=1; PicoCpuCM68k.cycles=0; } }\r
51#define SekSetStopS68k(x) { PicoCpuCS68k.state_flags&=~1; if (x) { PicoCpuCS68k.state_flags|=1; PicoCpuCS68k.cycles=0; } }\r
ca61ee42 52#define SekIsStoppedS68k() (PicoCpuCS68k.state_flags&1)\r
03e4f2a3 53#define SekShouldInterrupt (PicoCpuCM68k.irq > (PicoCpuCM68k.srh&7))\r
b542be46 54\r
55#define SekInterrupt(i) PicoCpuCM68k.irq=i\r
56\r
03e4f2a3 57#ifdef EMU_M68K\r
58#define EMU_CORE_DEBUG\r
59#endif\r
cc68a136 60#endif\r
61\r
70357ce5 62#ifdef EMU_F68K\r
63#include "../cpu/fame/fame.h"\r
b542be46 64extern M68K_CONTEXT PicoCpuFM68k, PicoCpuFS68k;\r
3aa1e148 65#define SekCyclesLeftNoMCD PicoCpuFM68k.io_cycle_counter\r
70357ce5 66#define SekCyclesLeft \\r
67 (((PicoMCD&1) && (PicoOpt & 0x2000)) ? (SekCycleAim-SekCycleCnt) : SekCyclesLeftNoMCD)\r
68#define SekCyclesLeftS68k \\r
3aa1e148 69 ((PicoOpt & 0x2000) ? (SekCycleAimS68k-SekCycleCntS68k) : PicoCpuFS68k.io_cycle_counter)\r
70#define SekSetCyclesLeftNoMCD(c) PicoCpuFM68k.io_cycle_counter=c\r
70357ce5 71#define SekSetCyclesLeft(c) { \\r
72 if ((PicoMCD&1) && (PicoOpt & 0x2000)) SekCycleCnt=SekCycleAim-(c); else SekSetCyclesLeftNoMCD(c); \\r
73}\r
03e4f2a3 74#define SekPc fm68k_get_pc(&PicoCpuFM68k)\r
75#define SekPcS68k fm68k_get_pc(&PicoCpuFS68k)\r
70357ce5 76#define SekSetStop(x) { \\r
03e4f2a3 77 PicoCpuFM68k.execinfo &= ~FM68K_HALTED; \\r
78 if (x) { PicoCpuFM68k.execinfo |= FM68K_HALTED; PicoCpuFM68k.io_cycle_counter = 0; } \\r
70357ce5 79}\r
80#define SekSetStopS68k(x) { \\r
03e4f2a3 81 PicoCpuFS68k.execinfo &= ~FM68K_HALTED; \\r
82 if (x) { PicoCpuFS68k.execinfo |= FM68K_HALTED; PicoCpuFS68k.io_cycle_counter = 0; } \\r
70357ce5 83}\r
ca61ee42 84#define SekIsStoppedS68k() (PicoCpuFS68k.execinfo&FM68K_HALTED)\r
03e4f2a3 85#define SekShouldInterrupt fm68k_would_interrupt()\r
b542be46 86\r
87#define SekInterrupt(irq) PicoCpuFM68k.interrupts[0]=irq\r
88\r
03e4f2a3 89#ifdef EMU_M68K\r
90#define EMU_CORE_DEBUG\r
91#endif\r
cc68a136 92#endif\r
93\r
94#ifdef EMU_M68K\r
95#include "../cpu/musashi/m68kcpu.h"\r
3aa1e148 96extern m68ki_cpu_core PicoCpuMM68k, PicoCpuMS68k;\r
cc68a136 97#ifndef SekCyclesLeft\r
3aa1e148 98#define SekCyclesLeftNoMCD PicoCpuMM68k.cyc_remaining_cycles\r
7336a99a 99#define SekCyclesLeft \\r
100 (((PicoMCD&1) && (PicoOpt & 0x2000)) ? (SekCycleAim-SekCycleCnt) : SekCyclesLeftNoMCD)\r
7a1f6e45 101#define SekCyclesLeftS68k \\r
3aa1e148 102 ((PicoOpt & 0x2000) ? (SekCycleAimS68k-SekCycleCntS68k) : PicoCpuMS68k.cyc_remaining_cycles)\r
7336a99a 103#define SekSetCyclesLeftNoMCD(c) SET_CYCLES(c)\r
104#define SekSetCyclesLeft(c) { \\r
105 if ((PicoMCD&1) && (PicoOpt & 0x2000)) SekCycleCnt=SekCycleAim-(c); else SET_CYCLES(c); \\r
106}\r
3aa1e148 107#define SekPc m68k_get_reg(&PicoCpuMM68k, M68K_REG_PC)\r
108#define SekPcS68k m68k_get_reg(&PicoCpuMS68k, M68K_REG_PC)\r
7a1f6e45 109#define SekSetStop(x) { \\r
3aa1e148 110 if(x) { SET_CYCLES(0); PicoCpuMM68k.stopped=STOP_LEVEL_STOP; } \\r
111 else PicoCpuMM68k.stopped=0; \\r
7a1f6e45 112}\r
113#define SekSetStopS68k(x) { \\r
3aa1e148 114 if(x) { SET_CYCLES(0); PicoCpuMS68k.stopped=STOP_LEVEL_STOP; } \\r
115 else PicoCpuMS68k.stopped=0; \\r
7a1f6e45 116}\r
ca61ee42 117#define SekIsStoppedS68k() (PicoCpuMS68k.stopped==STOP_LEVEL_STOP)\r
03e4f2a3 118#define SekShouldInterrupt (CPU_INT_LEVEL > FLAG_INT_MASK)\r
b542be46 119\r
71de3cd9 120#define SekInterrupt(irq) { \\r
b542be46 121 void *oldcontext = m68ki_cpu_p; \\r
122 m68k_set_context(&PicoCpuMM68k); \\r
123 m68k_set_irq(irq); \\r
124 m68k_set_context(oldcontext); \\r
125}\r
126\r
cc68a136 127#endif\r
128#endif\r
129\r
130extern int SekCycleCnt; // cycles done in this frame\r
131extern int SekCycleAim; // cycle aim\r
132extern unsigned int SekCycleCntT; // total cycle counter, updated once per frame\r
133\r
b8cbd802 134#define SekCyclesReset() { \\r
135 SekCycleCntT+=SekCycleAim; \\r
136 SekCycleCnt-=SekCycleAim; \\r
137 SekCycleAim=0; \\r
138}\r
cc68a136 139#define SekCyclesBurn(c) SekCycleCnt+=c\r
140#define SekCyclesDone() (SekCycleAim-SekCyclesLeft) // nuber of cycles done in this frame (can be checked anywhere)\r
141#define SekCyclesDoneT() (SekCycleCntT+SekCyclesDone()) // total nuber of cycles done for this rom\r
142\r
143#define SekEndRun(after) { \\r
144 SekCycleCnt -= SekCyclesLeft - after; \\r
145 if(SekCycleCnt < 0) SekCycleCnt = 0; \\r
146 SekSetCyclesLeft(after); \\r
147}\r
148\r
149extern int SekCycleCntS68k;\r
150extern int SekCycleAimS68k;\r
151\r
bf5fbbb4 152#define SekCyclesResetS68k() { \\r
153 SekCycleCntS68k-=SekCycleAimS68k; \\r
154 SekCycleAimS68k=0; \\r
155}\r
7a1f6e45 156#define SekCyclesDoneS68k() (SekCycleAimS68k-SekCyclesLeftS68k)\r
cc68a136 157\r
03e4f2a3 158#ifdef EMU_CORE_DEBUG\r
2d0b15bb 159#undef SekSetCyclesLeftNoMCD\r
160#undef SekSetCyclesLeft\r
161#undef SekCyclesBurn\r
162#undef SekEndRun\r
163#define SekSetCyclesLeftNoMCD(c)\r
164#define SekSetCyclesLeft(c)\r
2270612a 165#define SekCyclesBurn(c) c\r
2d0b15bb 166#define SekEndRun(c)\r
167#endif\r
cc68a136 168\r
b542be46 169// ----------------------- Z80 CPU -----------------------\r
170\r
171#if defined(_USE_MZ80)\r
dca310c4 172#include "../cpu/mz80/mz80.h"\r
b542be46 173\r
174#define z80_run(cycles) mz80_run(cycles)\r
175#define z80_run_nr(cycles) mz80_run(cycles)\r
176#define z80_int() mz80int(0)\r
177#define z80_resetCycles() mz80GetElapsedTicks(1)\r
178\r
179#elif defined(_USE_DRZ80)\r
dca310c4 180#include "../cpu/DrZ80/drz80.h"\r
b542be46 181\r
182extern struct DrZ80 drZ80;\r
183\r
184#define z80_run(cycles) ((cycles) - DrZ80Run(&drZ80, cycles))\r
185#define z80_run_nr(cycles) DrZ80Run(&drZ80, cycles)\r
186#define z80_int() { \\r
187 drZ80.z80irqvector = 0xFF; /* default IRQ vector RST opcode */ \\r
188 drZ80.Z80_IRQ = 1; \\r
189}\r
190#define z80_resetCycles()\r
191\r
192#elif defined(_USE_CZ80)\r
dca310c4 193#include "../cpu/cz80/cz80.h"\r
b542be46 194\r
195#define z80_run(cycles) Cz80_Exec(&CZ80, cycles)\r
196#define z80_run_nr(cycles) Cz80_Exec(&CZ80, cycles)\r
197#define z80_int() Cz80_Set_IRQ(&CZ80, 0, HOLD_LINE)\r
198#define z80_resetCycles()\r
199\r
200#else\r
201\r
202#define z80_run(cycles) (cycles)\r
203#define z80_run_nr(cycles)\r
204#define z80_int()\r
205#define z80_resetCycles()\r
206\r
207#endif\r
208\r
cc68a136 209// ---------------------------------------------------------\r
210\r
70357ce5 211extern int PicoMCD;\r
212\r
cc68a136 213// main oscillator clock which controls timing\r
214#define OSC_NTSC 53693100\r
b8cbd802 215// seems to be accurate, see scans from http://www.hot.ee/tmeeco/\r
216#define OSC_PAL 53203424\r
cc68a136 217\r
218struct PicoVideo\r
219{\r
220 unsigned char reg[0x20];\r
b8cbd802 221 unsigned int command; // 32-bit Command\r
222 unsigned char pending; // 1 if waiting for second half of 32-bit command\r
223 unsigned char type; // Command type (v/c/vsram read/write)\r
224 unsigned short addr; // Read/Write address\r
225 int status; // Status bits\r
cc68a136 226 unsigned char pending_ints; // pending interrupts: ??VH????\r
b8cbd802 227 signed char lwrite_cnt; // VDP write count during active display line\r
228 unsigned char pad[0x12];\r
cc68a136 229};\r
230\r
231struct PicoMisc\r
232{\r
233 unsigned char rotate;\r
234 unsigned char z80Run;\r
e5503e2f 235 unsigned char padTHPhase[2]; // 02 phase of gamepad TH switches\r
236 short scanline; // 04 0 to 261||311; -1 in fast mode\r
237 char dirtyPal; // 06 Is the palette dirty (1 - change @ this frame, 2 - some time before)\r
238 unsigned char hardware; // 07 Hardware value for country\r
239 unsigned char pal; // 08 1=PAL 0=NTSC\r
240 unsigned char sram_reg; // SRAM mode register. bit0: allow read? bit1: deny write? bit2: EEPROM? bit4: detected? (header or by access)\r
241 unsigned short z80_bank68k; // 0a\r
cc68a136 242 unsigned short z80_lastaddr; // this is for Z80 faking\r
243 unsigned char z80_fakeval;\r
244 unsigned char pad0;\r
e5503e2f 245 unsigned char padDelay[2]; // 10 gamepad phase time outs, so we count a delay\r
1dceadae 246 unsigned short eeprom_addr; // EEPROM address register\r
247 unsigned char eeprom_cycle; // EEPROM SRAM cycle number\r
248 unsigned char eeprom_slave; // EEPROM slave word for X24C02 and better SRAMs\r
721cd396 249 unsigned char prot_bytes[2]; // simple protection faking\r
b8cbd802 250 unsigned short dma_xfers;\r
312e9ce1 251 unsigned char pad[2];\r
252 unsigned int frame_count; // mainly for movies\r
cc68a136 253};\r
254\r
255// some assembly stuff depend on these, do not touch!\r
256struct Pico\r
257{\r
258 unsigned char ram[0x10000]; // 0x00000 scratch ram\r
259 unsigned short vram[0x8000]; // 0x10000\r
260 unsigned char zram[0x2000]; // 0x20000 Z80 ram\r
261 unsigned char ioports[0x10];\r
262 unsigned int pad[0x3c]; // unused\r
263 unsigned short cram[0x40]; // 0x22100\r
264 unsigned short vsram[0x40]; // 0x22180\r
265\r
266 unsigned char *rom; // 0x22200\r
267 unsigned int romsize; // 0x22204\r
268\r
269 struct PicoMisc m;\r
270 struct PicoVideo video;\r
271};\r
272\r
273// sram\r
274struct PicoSRAM\r
275{\r
4ff2d527 276 unsigned char *data; // actual data\r
277 unsigned int start; // start address in 68k address space\r
cc68a136 278 unsigned int end;\r
1dceadae 279 unsigned char unused1; // 0c: unused\r
280 unsigned char unused2;\r
cc68a136 281 unsigned char changed;\r
1dceadae 282 unsigned char eeprom_type; // eeprom type: 0: 7bit (24C01), 2: device with 2 addr words (X24C02+), 3: dev with 3 addr words\r
283 unsigned char eeprom_abits; // eeprom access must be odd addr for: bit0 ~ cl, bit1 ~ out\r
284 unsigned char eeprom_bit_cl; // bit number for cl\r
285 unsigned char eeprom_bit_in; // bit number for in\r
286 unsigned char eeprom_bit_out; // bit number for out\r
cc68a136 287};\r
288\r
289// MCD\r
290#include "cd/cd_sys.h"\r
291#include "cd/LC89510.h"\r
d1df8786 292#include "cd/gfx_cd.h"\r
cc68a136 293\r
4f265db7 294struct mcd_pcm\r
295{\r
296 unsigned char control; // reg7\r
297 unsigned char enabled; // reg8\r
298 unsigned char cur_ch;\r
299 unsigned char bank;\r
300 int pad1;\r
301\r
4ff2d527 302 struct pcm_chan // 08, size 0x10\r
4f265db7 303 {\r
304 unsigned char regs[8];\r
4ff2d527 305 unsigned int addr; // .08: played sample address\r
4f265db7 306 int pad;\r
307 } ch[8];\r
308};\r
309\r
c459aefd 310struct mcd_misc\r
311{\r
312 unsigned short hint_vector;\r
313 unsigned char busreq;\r
51a902ae 314 unsigned char s68k_pend_ints;\r
89fa852d 315 unsigned int state_flags; // 04: emu state: reset_pending, dmna_pending\r
51a902ae 316 unsigned int counter75hz;\r
4ff2d527 317 unsigned short audio_offset; // 0c: for savestates: play pointer offset (0-1023)\r
75736070 318 unsigned char audio_track; // playing audio track # (zero based)\r
6cadc2da 319 char pad1;\r
4ff2d527 320 int timer_int3; // 10\r
4f265db7 321 unsigned int timer_stopwatch;\r
6cadc2da 322 unsigned char bcram_reg; // 18: battery-backed RAM cart register\r
323 unsigned char pad2;\r
324 unsigned short pad3;\r
325 int pad[9];\r
c459aefd 326};\r
327\r
cc68a136 328typedef struct\r
329{\r
4ff2d527 330 unsigned char bios[0x20000]; // 000000: 128K\r
331 union { // 020000: 512K\r
fa1e5e29 332 unsigned char prg_ram[0x80000];\r
cc68a136 333 unsigned char prg_ram_b[4][0x20000];\r
334 };\r
4ff2d527 335 union { // 0a0000: 256K\r
fa1e5e29 336 struct {\r
337 unsigned char word_ram2M[0x40000];\r
dca310c4 338 unsigned char unused0[0x20000];\r
fa1e5e29 339 };\r
340 struct {\r
dca310c4 341 unsigned char unused1[0x20000];\r
fa1e5e29 342 unsigned char word_ram1M[2][0x20000];\r
343 };\r
344 };\r
4ff2d527 345 union { // 100000: 64K\r
fa1e5e29 346 unsigned char pcm_ram[0x10000];\r
4f265db7 347 unsigned char pcm_ram_b[0x10][0x1000];\r
348 };\r
4ff2d527 349 unsigned char s68k_regs[0x200]; // 110000: GA, not CPU regs\r
350 unsigned char bram[0x2000]; // 110200: 8K\r
351 struct mcd_misc m; // 112200: misc\r
352 struct mcd_pcm pcm; // 112240:\r
75736070 353 _scd_toc TOC; // not to be saved\r
cc68a136 354 CDD cdd;\r
355 CDC cdc;\r
356 _scd scd;\r
d1df8786 357 Rot_Comp rot_comp;\r
cc68a136 358} mcd_state;\r
359\r
360#define Pico_mcd ((mcd_state *)Pico.rom)\r
361\r
51a902ae 362// Area.c\r
eff55556 363PICO_INTERNAL int PicoAreaPackCpu(unsigned char *cpu, int is_sub);\r
364PICO_INTERNAL int PicoAreaUnpackCpu(unsigned char *cpu, int is_sub);\r
fad24893 365extern void (*PicoLoadStateHook)(void);\r
51a902ae 366\r
367// cd/Area.c\r
eff55556 368PICO_INTERNAL int PicoCdSaveState(void *file);\r
369PICO_INTERNAL int PicoCdLoadState(void *file);\r
cc68a136 370\r
945c2fdc 371typedef struct {\r
372 int chunk;\r
373 int size;\r
374 void *ptr;\r
375} carthw_state_chunk;\r
376extern carthw_state_chunk *carthw_chunks;\r
377#define CHUNK_CARTHW 64\r
378\r
1dceadae 379// Cart.c\r
e807ac75 380extern void (*PicoCartUnloadHook)(void);\r
1dceadae 381\r
03e4f2a3 382// Debug.c\r
b5e5172d 383int CM_compareRun(int cyc, int is_sub);\r
03e4f2a3 384\r
cc68a136 385// Draw.c\r
eff55556 386PICO_INTERNAL int PicoLine(int scan);\r
387PICO_INTERNAL void PicoFrameStart(void);\r
cc68a136 388\r
389// Draw2.c\r
eff55556 390PICO_INTERNAL void PicoFrameFull();\r
cc68a136 391\r
392// Memory.c\r
eff55556 393PICO_INTERNAL int PicoInitPc(unsigned int pc);\r
8ab3e3c1 394PICO_INTERNAL_ASM unsigned int PicoRead32(unsigned int a);\r
eff55556 395PICO_INTERNAL void PicoMemSetup(void);\r
396PICO_INTERNAL_ASM void PicoMemReset(void);\r
f8ef8ff7 397PICO_INTERNAL void PicoMemResetHooks(void);\r
e5503e2f 398PICO_INTERNAL int PadRead(int i);\r
eff55556 399PICO_INTERNAL unsigned char z80_read(unsigned short a);\r
a4221917 400#ifndef _USE_CZ80\r
eff55556 401PICO_INTERNAL_ASM void z80_write(unsigned char data, unsigned short a);\r
402PICO_INTERNAL void z80_write16(unsigned short data, unsigned short a);\r
a4221917 403PICO_INTERNAL unsigned short z80_read16(unsigned short a);\r
404#else\r
405PICO_INTERNAL_ASM void z80_write(unsigned int a, unsigned char data);\r
406#endif\r
f53f286a 407extern unsigned int (*PicoRead16Hook)(unsigned int a, int realsize);\r
f8ef8ff7 408extern void (*PicoWrite8Hook) (unsigned int a,unsigned int d,int realsize);\r
409extern void (*PicoWrite16Hook)(unsigned int a,unsigned int d,int realsize);\r
cc68a136 410\r
411// cd/Memory.c\r
eff55556 412PICO_INTERNAL void PicoMemSetupCD(void);\r
413PICO_INTERNAL_ASM void PicoMemResetCD(int r3);\r
414PICO_INTERNAL_ASM void PicoMemResetCDdecode(int r3);\r
cc68a136 415\r
416// Pico.c\r
417extern struct Pico Pico;\r
418extern struct PicoSRAM SRam;\r
419extern int emustatus;\r
d9153729 420extern int z80startCycle, z80stopCycle; // in 68k cycles\r
f8ef8ff7 421extern void (*PicoResetHook)(void);\r
0ffefdb8 422extern void (*PicoLineHook)(int count);\r
eff55556 423PICO_INTERNAL int CheckDMA(void);\r
cc68a136 424\r
425// cd/Pico.c\r
e5f426aa 426PICO_INTERNAL int PicoInitMCD(void);\r
427PICO_INTERNAL void PicoExitMCD(void);\r
eff55556 428PICO_INTERNAL int PicoResetMCD(int hard);\r
429PICO_INTERNAL int PicoFrameMCD(void);\r
cc68a136 430\r
431// Sek.c\r
eff55556 432PICO_INTERNAL int SekInit(void);\r
433PICO_INTERNAL int SekReset(void);\r
3aa1e148 434PICO_INTERNAL void SekState(int *data);\r
eff55556 435PICO_INTERNAL void SekSetRealTAS(int use_real);\r
cc68a136 436\r
437// cd/Sek.c\r
eff55556 438PICO_INTERNAL int SekInitS68k(void);\r
439PICO_INTERNAL int SekResetS68k(void);\r
440PICO_INTERNAL int SekInterruptS68k(int irq);\r
cc68a136 441\r
7a93adeb 442// sound/sound.c\r
443extern int PsndLen_exc_cnt;\r
444extern int PsndLen_exc_add;\r
445\r
cc68a136 446// VideoPort.c\r
eff55556 447PICO_INTERNAL_ASM void PicoVideoWrite(unsigned int a,unsigned short d);\r
448PICO_INTERNAL_ASM unsigned int PicoVideoRead(unsigned int a);\r
5de27868 449extern int (*PicoDmaHook)(unsigned int source, int len, unsigned short **srcp, unsigned short **limitp);\r
cc68a136 450\r
451// Misc.c\r
eff55556 452PICO_INTERNAL void SRAMWriteEEPROM(unsigned int d);\r
453PICO_INTERNAL void SRAMUpdPending(unsigned int a, unsigned int d);\r
454PICO_INTERNAL_ASM unsigned int SRAMReadEEPROM(void);\r
455PICO_INTERNAL_ASM void memcpy16(unsigned short *dest, unsigned short *src, int count);\r
456PICO_INTERNAL_ASM void memcpy16bswap(unsigned short *dest, void *src, int count);\r
457PICO_INTERNAL_ASM void memcpy32(int *dest, int *src, int count); // 32bit word count\r
458PICO_INTERNAL_ASM void memset32(int *dest, int c, int count);\r
cc68a136 459\r
fa1e5e29 460// cd/Misc.c\r
eff55556 461PICO_INTERNAL_ASM void wram_2M_to_1M(unsigned char *m);\r
462PICO_INTERNAL_ASM void wram_1M_to_2M(unsigned char *m);\r
463\r
464// cd/buffering.c\r
465PICO_INTERNAL void PicoCDBufferRead(void *dest, int lba);\r
466\r
467// sound/sound.c\r
9d917eea 468PICO_INTERNAL void PsndReset(void);\r
469PICO_INTERNAL void Psnd_timers_and_dac(int raster);\r
470PICO_INTERNAL int PsndRender(int offset, int length);\r
471PICO_INTERNAL void PsndClear(void);\r
eff55556 472// z80 functionality wrappers\r
473PICO_INTERNAL void z80_init(void);\r
eff55556 474PICO_INTERNAL void z80_pack(unsigned char *data);\r
475PICO_INTERNAL void z80_unpack(unsigned char *data);\r
476PICO_INTERNAL void z80_reset(void);\r
477PICO_INTERNAL void z80_exit(void);\r
fa1e5e29 478\r
cc68a136 479\r
480#ifdef __cplusplus\r
481} // End of extern "C"\r
482#endif\r
eff55556 483\r
b8cbd802 484// emulation event logging\r
485#ifndef EL_LOGMASK\r
486#define EL_LOGMASK 0\r
487#endif\r
488\r
017512f2 489#define EL_HVCNT 0x00000001 /* hv counter reads */\r
490#define EL_SR 0x00000002 /* SR reads */\r
491#define EL_INTS 0x00000004 /* ints and acks */\r
492#define EL_YM2612R 0x00000008 /* 68k ym2612 reads */\r
493#define EL_INTSW 0x00000010 /* log irq switching on/off */\r
494#define EL_ASVDP 0x00000020 /* VDP accesses during active scan */\r
495#define EL_VDPDMA 0x00000040 /* VDP DMA transfers and their timing */\r
496#define EL_BUSREQ 0x00000080 /* z80 busreq r/w or reset w */\r
497#define EL_Z80BNK 0x00000100 /* z80 i/o through bank area */\r
498#define EL_SRAMIO 0x00000200 /* sram i/o */\r
499#define EL_EEPROM 0x00000400 /* eeprom debug */\r
500#define EL_UIO 0x00000800 /* unmapped i/o */\r
501#define EL_IO 0x00001000 /* all i/o */\r
502#define EL_CDPOLL 0x00002000 /* MCD: log poll detection */\r
503#define EL_SVP 0x00004000 /* SVP stuff */\r
504\r
505#define EL_STATUS 0x40000000 /* status messages */\r
506#define EL_ANOMALY 0x80000000 /* some unexpected conditions (during emulation) */\r
b8cbd802 507\r
508#if EL_LOGMASK\r
7d0143a2 509extern void lprintf(const char *fmt, ...);\r
b8cbd802 510#define elprintf(w,f,...) \\r
511{ \\r
512 if ((w) & EL_LOGMASK) \\r
7d0143a2 513 lprintf("%05i:%03i: " f "\n",Pico.m.frame_count,Pico.m.scanline,##__VA_ARGS__); \\r
b8cbd802 514}\r
dca310c4 515#elif defined(_MSC_VER)\r
516#define elprintf\r
b8cbd802 517#else\r
518#define elprintf(w,f,...)\r
519#endif\r
520\r
dca310c4 521#ifdef _MSC_VER\r
522#define cdprintf\r
523#else\r
524#define cdprintf(x...)\r
525#endif\r
526\r
eff55556 527#endif // PICO_INTERNAL_INCLUDED\r
528\r
fast MegaDrive/MegaCD/32X emulator