notaz.gp2x.de / pcsx_rearmed.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
drc: merge Ari64's patch: 12_cycle_count
[pcsx_rearmed.git] / libpcsxcore / new_dynarec / new_dynarec.c
CommitLineData
57871462 1/* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
2 * Mupen64plus - new_dynarec.c *
20d507ba 3 * Copyright (C) 2009-2011 Ari64 *
57871462 4 * *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
9 * *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
14 * *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. *
19 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */
20
21#include <stdlib.h>
22#include <stdint.h> //include for uint64_t
23#include <assert.h>
24
3d624f89 25#include "emu_if.h" //emulator interface
57871462 26
27#include <sys/mman.h>
28
29#ifdef __i386__
30#include "assem_x86.h"
31#endif
32#ifdef __x86_64__
33#include "assem_x64.h"
34#endif
35#ifdef __arm__
36#include "assem_arm.h"
37#endif
38
39#define MAXBLOCK 4096
40#define MAX_OUTPUT_BLOCK_SIZE 262144
41#define CLOCK_DIVIDER 2
42
43struct regstat
44{
45 signed char regmap_entry[HOST_REGS];
46 signed char regmap[HOST_REGS];
47 uint64_t was32;
48 uint64_t is32;
49 uint64_t wasdirty;
50 uint64_t dirty;
51 uint64_t u;
52 uint64_t uu;
53 u_int wasconst;
54 u_int isconst;
55 uint64_t constmap[HOST_REGS];
56};
57
58struct ll_entry
59{
60 u_int vaddr;
61 u_int reg32;
62 void *addr;
63 struct ll_entry *next;
64};
65
66 u_int start;
67 u_int *source;
68 u_int pagelimit;
69 char insn[MAXBLOCK][10];
70 u_char itype[MAXBLOCK];
71 u_char opcode[MAXBLOCK];
72 u_char opcode2[MAXBLOCK];
73 u_char bt[MAXBLOCK];
74 u_char rs1[MAXBLOCK];
75 u_char rs2[MAXBLOCK];
76 u_char rt1[MAXBLOCK];
77 u_char rt2[MAXBLOCK];
78 u_char us1[MAXBLOCK];
79 u_char us2[MAXBLOCK];
80 u_char dep1[MAXBLOCK];
81 u_char dep2[MAXBLOCK];
82 u_char lt1[MAXBLOCK];
83 int imm[MAXBLOCK];
84 u_int ba[MAXBLOCK];
85 char likely[MAXBLOCK];
86 char is_ds[MAXBLOCK];
e1190b87 87 char ooo[MAXBLOCK];
57871462 88 uint64_t unneeded_reg[MAXBLOCK];
89 uint64_t unneeded_reg_upper[MAXBLOCK];
90 uint64_t branch_unneeded_reg[MAXBLOCK];
91 uint64_t branch_unneeded_reg_upper[MAXBLOCK];
92 uint64_t p32[MAXBLOCK];
93 uint64_t pr32[MAXBLOCK];
94 signed char regmap_pre[MAXBLOCK][HOST_REGS];
95 signed char regmap[MAXBLOCK][HOST_REGS];
96 signed char regmap_entry[MAXBLOCK][HOST_REGS];
97 uint64_t constmap[MAXBLOCK][HOST_REGS];
57871462 98 struct regstat regs[MAXBLOCK];
99 struct regstat branch_regs[MAXBLOCK];
e1190b87 100 signed char minimum_free_regs[MAXBLOCK];
57871462 101 u_int needed_reg[MAXBLOCK];
102 uint64_t requires_32bit[MAXBLOCK];
103 u_int wont_dirty[MAXBLOCK];
104 u_int will_dirty[MAXBLOCK];
105 int ccadj[MAXBLOCK];
106 int slen;
107 u_int instr_addr[MAXBLOCK];
108 u_int link_addr[MAXBLOCK][3];
109 int linkcount;
110 u_int stubs[MAXBLOCK*3][8];
111 int stubcount;
112 u_int literals[1024][2];
113 int literalcount;
114 int is_delayslot;
115 int cop1_usable;
116 u_char *out;
117 struct ll_entry *jump_in[4096];
118 struct ll_entry *jump_out[4096];
119 struct ll_entry *jump_dirty[4096];
120 u_int hash_table[65536][4] __attribute__((aligned(16)));
121 char shadow[1048576] __attribute__((aligned(16)));
122 void *copy;
123 int expirep;
af4ee1fe 124#ifndef PCSX
57871462 125 u_int using_tlb;
af4ee1fe 126#else
127 static const u_int using_tlb=0;
128#endif
dadf55f2 129 static u_int sp_in_mirror;
57871462 130 u_int stop_after_jal;
131 extern u_char restore_candidate[512];
132 extern int cycle_count;
133
134 /* registers that may be allocated */
135 /* 1-31 gpr */
136#define HIREG 32 // hi
137#define LOREG 33 // lo
138#define FSREG 34 // FPU status (FCSR)
139#define CSREG 35 // Coprocessor status
140#define CCREG 36 // Cycle count
141#define INVCP 37 // Pointer to invalid_code
619e5ded 142#define MMREG 38 // Pointer to memory_map
143#define ROREG 39 // ram offset (if rdram!=0x80000000)
144#define TEMPREG 40
145#define FTEMP 40 // FPU temporary register
146#define PTEMP 41 // Prefetch temporary register
147#define TLREG 42 // TLB mapping offset
148#define RHASH 43 // Return address hash
149#define RHTBL 44 // Return address hash table address
150#define RTEMP 45 // JR/JALR address register
151#define MAXREG 45
152#define AGEN1 46 // Address generation temporary register
153#define AGEN2 47 // Address generation temporary register
154#define MGEN1 48 // Maptable address generation temporary register
155#define MGEN2 49 // Maptable address generation temporary register
156#define BTREG 50 // Branch target temporary register
57871462 157
158 /* instruction types */
159#define NOP 0 // No operation
160#define LOAD 1 // Load
161#define STORE 2 // Store
162#define LOADLR 3 // Unaligned load
163#define STORELR 4 // Unaligned store
164#define MOV 5 // Move
165#define ALU 6 // Arithmetic/logic
166#define MULTDIV 7 // Multiply/divide
167#define SHIFT 8 // Shift by register
168#define SHIFTIMM 9// Shift by immediate
169#define IMM16 10 // 16-bit immediate
170#define RJUMP 11 // Unconditional jump to register
171#define UJUMP 12 // Unconditional jump
172#define CJUMP 13 // Conditional branch (BEQ/BNE/BGTZ/BLEZ)
173#define SJUMP 14 // Conditional branch (regimm format)
174#define COP0 15 // Coprocessor 0
175#define COP1 16 // Coprocessor 1
176#define C1LS 17 // Coprocessor 1 load/store
177#define FJUMP 18 // Conditional branch (floating point)
178#define FLOAT 19 // Floating point unit
179#define FCONV 20 // Convert integer to float
180#define FCOMP 21 // Floating point compare (sets FSREG)
181#define SYSCALL 22// SYSCALL
182#define OTHER 23 // Other
183#define SPAN 24 // Branch/delay slot spans 2 pages
184#define NI 25 // Not implemented
7139f3c8 185#define HLECALL 26// PCSX fake opcodes for HLE
b9b61529 186#define COP2 27 // Coprocessor 2 move
187#define C2LS 28 // Coprocessor 2 load/store
188#define C2OP 29 // Coprocessor 2 operation
1e973cb0 189#define INTCALL 30// Call interpreter to handle rare corner cases
57871462 190
191 /* stubs */
192#define CC_STUB 1
193#define FP_STUB 2
194#define LOADB_STUB 3
195#define LOADH_STUB 4
196#define LOADW_STUB 5
197#define LOADD_STUB 6
198#define LOADBU_STUB 7
199#define LOADHU_STUB 8
200#define STOREB_STUB 9
201#define STOREH_STUB 10
202#define STOREW_STUB 11
203#define STORED_STUB 12
204#define STORELR_STUB 13
205#define INVCODE_STUB 14
206
207 /* branch codes */
208#define TAKEN 1
209#define NOTTAKEN 2
210#define NULLDS 3
211
212// asm linkage
213int new_recompile_block(int addr);
214void *get_addr_ht(u_int vaddr);
215void invalidate_block(u_int block);
216void invalidate_addr(u_int addr);
217void remove_hash(int vaddr);
218void jump_vaddr();
219void dyna_linker();
220void dyna_linker_ds();
221void verify_code();
222void verify_code_vm();
223void verify_code_ds();
224void cc_interrupt();
225void fp_exception();
226void fp_exception_ds();
227void jump_syscall();
7139f3c8 228void jump_syscall_hle();
57871462 229void jump_eret();
7139f3c8 230void jump_hlecall();
1e973cb0 231void jump_intcall();
7139f3c8 232void new_dyna_leave();
57871462 233
234// TLB
235void TLBWI_new();
236void TLBWR_new();
237void read_nomem_new();
238void read_nomemb_new();
239void read_nomemh_new();
240void read_nomemd_new();
241void write_nomem_new();
242void write_nomemb_new();
243void write_nomemh_new();
244void write_nomemd_new();
245void write_rdram_new();
246void write_rdramb_new();
247void write_rdramh_new();
248void write_rdramd_new();
249extern u_int memory_map[1048576];
250
251// Needed by assembler
252void wb_register(signed char r,signed char regmap[],uint64_t dirty,uint64_t is32);
253void wb_dirtys(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty);
254void wb_needed_dirtys(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr);
255void load_all_regs(signed char i_regmap[]);
256void load_needed_regs(signed char i_regmap[],signed char next_regmap[]);
257void load_regs_entry(int t);
258void load_all_consts(signed char regmap[],int is32,u_int dirty,int i);
259
260int tracedebug=0;
261
262//#define DEBUG_CYCLE_COUNT 1
263
264void nullf() {}
265//#define assem_debug printf
266//#define inv_debug printf
267#define assem_debug nullf
268#define inv_debug nullf
269
94d23bb9 270static void tlb_hacks()
57871462 271{
94d23bb9 272#ifndef DISABLE_TLB
57871462 273 // Goldeneye hack
274 if (strncmp((char *) ROM_HEADER->nom, "GOLDENEYE",9) == 0)
275 {
276 u_int addr;
277 int n;
278 switch (ROM_HEADER->Country_code&0xFF)
279 {
280 case 0x45: // U
281 addr=0x34b30;
282 break;
283 case 0x4A: // J
284 addr=0x34b70;
285 break;
286 case 0x50: // E
287 addr=0x329f0;
288 break;
289 default:
290 // Unknown country code
291 addr=0;
292 break;
293 }
294 u_int rom_addr=(u_int)rom;
295 #ifdef ROM_COPY
296 // Since memory_map is 32-bit, on 64-bit systems the rom needs to be
297 // in the lower 4G of memory to use this hack. Copy it if necessary.
298 if((void *)rom>(void *)0xffffffff) {
299 munmap(ROM_COPY, 67108864);
300 if(mmap(ROM_COPY, 12582912,
301 PROT_READ | PROT_WRITE,
302 MAP_FIXED | MAP_PRIVATE | MAP_ANONYMOUS,
303 -1, 0) <= 0) {printf("mmap() failed\n");}
304 memcpy(ROM_COPY,rom,12582912);
305 rom_addr=(u_int)ROM_COPY;
306 }
307 #endif
308 if(addr) {
309 for(n=0x7F000;n<0x80000;n++) {
310 memory_map[n]=(((u_int)(rom_addr+addr-0x7F000000))>>2)|0x40000000;
311 }
312 }
313 }
94d23bb9 314#endif
57871462 315}
316
94d23bb9 317static u_int get_page(u_int vaddr)
57871462 318{
0ce47d46 319#ifndef PCSX
57871462 320 u_int page=(vaddr^0x80000000)>>12;
0ce47d46 321#else
322 u_int page=vaddr&~0xe0000000;
323 if (page < 0x1000000)
324 page &= ~0x0e00000; // RAM mirrors
325 page>>=12;
326#endif
94d23bb9 327#ifndef DISABLE_TLB
57871462 328 if(page>262143&&tlb_LUT_r[vaddr>>12]) page=(tlb_LUT_r[vaddr>>12]^0x80000000)>>12;
94d23bb9 329#endif
57871462 330 if(page>2048) page=2048+(page&2047);
94d23bb9 331 return page;
332}
333
334static u_int get_vpage(u_int vaddr)
335{
336 u_int vpage=(vaddr^0x80000000)>>12;
337#ifndef DISABLE_TLB
57871462 338 if(vpage>262143&&tlb_LUT_r[vaddr>>12]) vpage&=2047; // jump_dirty uses a hash of the virtual address instead
94d23bb9 339#endif
57871462 340 if(vpage>2048) vpage=2048+(vpage&2047);
94d23bb9 341 return vpage;
342}
343
344// Get address from virtual address
345// This is called from the recompiled JR/JALR instructions
346void *get_addr(u_int vaddr)
347{
348 u_int page=get_page(vaddr);
349 u_int vpage=get_vpage(vaddr);
57871462 350 struct ll_entry *head;
351 //printf("TRACE: count=%d next=%d (get_addr %x,page %d)\n",Count,next_interupt,vaddr,page);
352 head=jump_in[page];
353 while(head!=NULL) {
354 if(head->vaddr==vaddr&&head->reg32==0) {
355 //printf("TRACE: count=%d next=%d (get_addr match %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr);
356 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
357 ht_bin[3]=ht_bin[1];
358 ht_bin[2]=ht_bin[0];
359 ht_bin[1]=(int)head->addr;
360 ht_bin[0]=vaddr;
361 return head->addr;
362 }
363 head=head->next;
364 }
365 head=jump_dirty[vpage];
366 while(head!=NULL) {
367 if(head->vaddr==vaddr&&head->reg32==0) {
368 //printf("TRACE: count=%d next=%d (get_addr match dirty %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr);
369 // Don't restore blocks which are about to expire from the cache
370 if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
371 if(verify_dirty(head->addr)) {
372 //printf("restore candidate: %x (%d) d=%d\n",vaddr,page,invalid_code[vaddr>>12]);
373 invalid_code[vaddr>>12]=0;
374 memory_map[vaddr>>12]|=0x40000000;
375 if(vpage<2048) {
94d23bb9 376#ifndef DISABLE_TLB
57871462 377 if(tlb_LUT_r[vaddr>>12]) {
378 invalid_code[tlb_LUT_r[vaddr>>12]>>12]=0;
379 memory_map[tlb_LUT_r[vaddr>>12]>>12]|=0x40000000;
380 }
94d23bb9 381#endif
57871462 382 restore_candidate[vpage>>3]|=1<<(vpage&7);
383 }
384 else restore_candidate[page>>3]|=1<<(page&7);
385 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
386 if(ht_bin[0]==vaddr) {
387 ht_bin[1]=(int)head->addr; // Replace existing entry
388 }
389 else
390 {
391 ht_bin[3]=ht_bin[1];
392 ht_bin[2]=ht_bin[0];
393 ht_bin[1]=(int)head->addr;
394 ht_bin[0]=vaddr;
395 }
396 return head->addr;
397 }
398 }
399 head=head->next;
400 }
401 //printf("TRACE: count=%d next=%d (get_addr no-match %x)\n",Count,next_interupt,vaddr);
402 int r=new_recompile_block(vaddr);
403 if(r==0) return get_addr(vaddr);
404 // Execute in unmapped page, generate pagefault execption
405 Status|=2;
406 Cause=(vaddr<<31)|0x8;
407 EPC=(vaddr&1)?vaddr-5:vaddr;
408 BadVAddr=(vaddr&~1);
409 Context=(Context&0xFF80000F)|((BadVAddr>>9)&0x007FFFF0);
410 EntryHi=BadVAddr&0xFFFFE000;
411 return get_addr_ht(0x80000000);
412}
413// Look up address in hash table first
414void *get_addr_ht(u_int vaddr)
415{
416 //printf("TRACE: count=%d next=%d (get_addr_ht %x)\n",Count,next_interupt,vaddr);
417 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
418 if(ht_bin[0]==vaddr) return (void *)ht_bin[1];
419 if(ht_bin[2]==vaddr) return (void *)ht_bin[3];
420 return get_addr(vaddr);
421}
422
423void *get_addr_32(u_int vaddr,u_int flags)
424{
7139f3c8 425#ifdef FORCE32
426 return get_addr(vaddr);
560e4a12 427#else
57871462 428 //printf("TRACE: count=%d next=%d (get_addr_32 %x,flags %x)\n",Count,next_interupt,vaddr,flags);
429 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
430 if(ht_bin[0]==vaddr) return (void *)ht_bin[1];
431 if(ht_bin[2]==vaddr) return (void *)ht_bin[3];
94d23bb9 432 u_int page=get_page(vaddr);
433 u_int vpage=get_vpage(vaddr);
57871462 434 struct ll_entry *head;
435 head=jump_in[page];
436 while(head!=NULL) {
437 if(head->vaddr==vaddr&&(head->reg32&flags)==0) {
438 //printf("TRACE: count=%d next=%d (get_addr_32 match %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr);
439 if(head->reg32==0) {
440 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
441 if(ht_bin[0]==-1) {
442 ht_bin[1]=(int)head->addr;
443 ht_bin[0]=vaddr;
444 }else if(ht_bin[2]==-1) {
445 ht_bin[3]=(int)head->addr;
446 ht_bin[2]=vaddr;
447 }
448 //ht_bin[3]=ht_bin[1];
449 //ht_bin[2]=ht_bin[0];
450 //ht_bin[1]=(int)head->addr;
451 //ht_bin[0]=vaddr;
452 }
453 return head->addr;
454 }
455 head=head->next;
456 }
457 head=jump_dirty[vpage];
458 while(head!=NULL) {
459 if(head->vaddr==vaddr&&(head->reg32&flags)==0) {
460 //printf("TRACE: count=%d next=%d (get_addr_32 match dirty %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr);
461 // Don't restore blocks which are about to expire from the cache
462 if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
463 if(verify_dirty(head->addr)) {
464 //printf("restore candidate: %x (%d) d=%d\n",vaddr,page,invalid_code[vaddr>>12]);
465 invalid_code[vaddr>>12]=0;
466 memory_map[vaddr>>12]|=0x40000000;
467 if(vpage<2048) {
94d23bb9 468#ifndef DISABLE_TLB
57871462 469 if(tlb_LUT_r[vaddr>>12]) {
470 invalid_code[tlb_LUT_r[vaddr>>12]>>12]=0;
471 memory_map[tlb_LUT_r[vaddr>>12]>>12]|=0x40000000;
472 }
94d23bb9 473#endif
57871462 474 restore_candidate[vpage>>3]|=1<<(vpage&7);
475 }
476 else restore_candidate[page>>3]|=1<<(page&7);
477 if(head->reg32==0) {
478 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
479 if(ht_bin[0]==-1) {
480 ht_bin[1]=(int)head->addr;
481 ht_bin[0]=vaddr;
482 }else if(ht_bin[2]==-1) {
483 ht_bin[3]=(int)head->addr;
484 ht_bin[2]=vaddr;
485 }
486 //ht_bin[3]=ht_bin[1];
487 //ht_bin[2]=ht_bin[0];
488 //ht_bin[1]=(int)head->addr;
489 //ht_bin[0]=vaddr;
490 }
491 return head->addr;
492 }
493 }
494 head=head->next;
495 }
496 //printf("TRACE: count=%d next=%d (get_addr_32 no-match %x,flags %x)\n",Count,next_interupt,vaddr,flags);
497 int r=new_recompile_block(vaddr);
498 if(r==0) return get_addr(vaddr);
499 // Execute in unmapped page, generate pagefault execption
500 Status|=2;
501 Cause=(vaddr<<31)|0x8;
502 EPC=(vaddr&1)?vaddr-5:vaddr;
503 BadVAddr=(vaddr&~1);
504 Context=(Context&0xFF80000F)|((BadVAddr>>9)&0x007FFFF0);
505 EntryHi=BadVAddr&0xFFFFE000;
506 return get_addr_ht(0x80000000);
560e4a12 507#endif
57871462 508}
509
510void clear_all_regs(signed char regmap[])
511{
512 int hr;
513 for (hr=0;hr<HOST_REGS;hr++) regmap[hr]=-1;
514}
515
516signed char get_reg(signed char regmap[],int r)
517{
518 int hr;
519 for (hr=0;hr<HOST_REGS;hr++) if(hr!=EXCLUDE_REG&&regmap[hr]==r) return hr;
520 return -1;
521}
522
523// Find a register that is available for two consecutive cycles
524signed char get_reg2(signed char regmap1[],signed char regmap2[],int r)
525{
526 int hr;
527 for (hr=0;hr<HOST_REGS;hr++) if(hr!=EXCLUDE_REG&&regmap1[hr]==r&&regmap2[hr]==r) return hr;
528 return -1;
529}
530
531int count_free_regs(signed char regmap[])
532{
533 int count=0;
534 int hr;
535 for(hr=0;hr<HOST_REGS;hr++)
536 {
537 if(hr!=EXCLUDE_REG) {
538 if(regmap[hr]<0) count++;
539 }
540 }
541 return count;
542}
543
544void dirty_reg(struct regstat *cur,signed char reg)
545{
546 int hr;
547 if(!reg) return;
548 for (hr=0;hr<HOST_REGS;hr++) {
549 if((cur->regmap[hr]&63)==reg) {
550 cur->dirty|=1<<hr;
551 }
552 }
553}
554
555// If we dirty the lower half of a 64 bit register which is now being
556// sign-extended, we need to dump the upper half.
557// Note: Do this only after completion of the instruction, because
558// some instructions may need to read the full 64-bit value even if
559// overwriting it (eg SLTI, DSRA32).
560static void flush_dirty_uppers(struct regstat *cur)
561{
562 int hr,reg;
563 for (hr=0;hr<HOST_REGS;hr++) {
564 if((cur->dirty>>hr)&1) {
565 reg=cur->regmap[hr];
566 if(reg>=64)
567 if((cur->is32>>(reg&63))&1) cur->regmap[hr]=-1;
568 }
569 }
570}
571
572void set_const(struct regstat *cur,signed char reg,uint64_t value)
573{
574 int hr;
575 if(!reg) return;
576 for (hr=0;hr<HOST_REGS;hr++) {
577 if(cur->regmap[hr]==reg) {
578 cur->isconst|=1<<hr;
579 cur->constmap[hr]=value;
580 }
581 else if((cur->regmap[hr]^64)==reg) {
582 cur->isconst|=1<<hr;
583 cur->constmap[hr]=value>>32;
584 }
585 }
586}
587
588void clear_const(struct regstat *cur,signed char reg)
589{
590 int hr;
591 if(!reg) return;
592 for (hr=0;hr<HOST_REGS;hr++) {
593 if((cur->regmap[hr]&63)==reg) {
594 cur->isconst&=~(1<<hr);
595 }
596 }
597}
598
599int is_const(struct regstat *cur,signed char reg)
600{
601 int hr;
79c75f1b 602 if(reg<0) return 0;
57871462 603 if(!reg) return 1;
604 for (hr=0;hr<HOST_REGS;hr++) {
605 if((cur->regmap[hr]&63)==reg) {
606 return (cur->isconst>>hr)&1;
607 }
608 }
609 return 0;
610}
611uint64_t get_const(struct regstat *cur,signed char reg)
612{
613 int hr;
614 if(!reg) return 0;
615 for (hr=0;hr<HOST_REGS;hr++) {
616 if(cur->regmap[hr]==reg) {
617 return cur->constmap[hr];
618 }
619 }
620 printf("Unknown constant in r%d\n",reg);
621 exit(1);
622}
623
624// Least soon needed registers
625// Look at the next ten instructions and see which registers
626// will be used. Try not to reallocate these.
627void lsn(u_char hsn[], int i, int *preferred_reg)
628{
629 int j;
630 int b=-1;
631 for(j=0;j<9;j++)
632 {
633 if(i+j>=slen) {
634 j=slen-i-1;
635 break;
636 }
637 if(itype[i+j]==UJUMP||itype[i+j]==RJUMP||(source[i+j]>>16)==0x1000)
638 {
639 // Don't go past an unconditonal jump
640 j++;
641 break;
642 }
643 }
644 for(;j>=0;j--)
645 {
646 if(rs1[i+j]) hsn[rs1[i+j]]=j;
647 if(rs2[i+j]) hsn[rs2[i+j]]=j;
648 if(rt1[i+j]) hsn[rt1[i+j]]=j;
649 if(rt2[i+j]) hsn[rt2[i+j]]=j;
650 if(itype[i+j]==STORE || itype[i+j]==STORELR) {
651 // Stores can allocate zero
652 hsn[rs1[i+j]]=j;
653 hsn[rs2[i+j]]=j;
654 }
655 // On some architectures stores need invc_ptr
656 #if defined(HOST_IMM8)
b9b61529 657 if(itype[i+j]==STORE || itype[i+j]==STORELR || (opcode[i+j]&0x3b)==0x39 || (opcode[i+j]&0x3b)==0x3a) {
57871462 658 hsn[INVCP]=j;
659 }
660 #endif
661 if(i+j>=0&&(itype[i+j]==UJUMP||itype[i+j]==CJUMP||itype[i+j]==SJUMP||itype[i+j]==FJUMP))
662 {
663 hsn[CCREG]=j;
664 b=j;
665 }
666 }
667 if(b>=0)
668 {
669 if(ba[i+b]>=start && ba[i+b]<(start+slen*4))
670 {
671 // Follow first branch
672 int t=(ba[i+b]-start)>>2;
673 j=7-b;if(t+j>=slen) j=slen-t-1;
674 for(;j>=0;j--)
675 {
676 if(rs1[t+j]) if(hsn[rs1[t+j]]>j+b+2) hsn[rs1[t+j]]=j+b+2;
677 if(rs2[t+j]) if(hsn[rs2[t+j]]>j+b+2) hsn[rs2[t+j]]=j+b+2;
678 //if(rt1[t+j]) if(hsn[rt1[t+j]]>j+b+2) hsn[rt1[t+j]]=j+b+2;
679 //if(rt2[t+j]) if(hsn[rt2[t+j]]>j+b+2) hsn[rt2[t+j]]=j+b+2;
680 }
681 }
682 // TODO: preferred register based on backward branch
683 }
684 // Delay slot should preferably not overwrite branch conditions or cycle count
685 if(i>0&&(itype[i-1]==RJUMP||itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP)) {
686 if(rs1[i-1]) if(hsn[rs1[i-1]]>1) hsn[rs1[i-1]]=1;
687 if(rs2[i-1]) if(hsn[rs2[i-1]]>1) hsn[rs2[i-1]]=1;
688 hsn[CCREG]=1;
689 // ...or hash tables
690 hsn[RHASH]=1;
691 hsn[RHTBL]=1;
692 }
693 // Coprocessor load/store needs FTEMP, even if not declared
b9b61529 694 if(itype[i]==C1LS||itype[i]==C2LS) {
57871462 695 hsn[FTEMP]=0;
696 }
697 // Load L/R also uses FTEMP as a temporary register
698 if(itype[i]==LOADLR) {
699 hsn[FTEMP]=0;
700 }
b7918751 701 // Also SWL/SWR/SDL/SDR
702 if(opcode[i]==0x2a||opcode[i]==0x2e||opcode[i]==0x2c||opcode[i]==0x2d) {
57871462 703 hsn[FTEMP]=0;
704 }
705 // Don't remove the TLB registers either
b9b61529 706 if(itype[i]==LOAD || itype[i]==LOADLR || itype[i]==STORE || itype[i]==STORELR || itype[i]==C1LS || itype[i]==C2LS) {
57871462 707 hsn[TLREG]=0;
708 }
709 // Don't remove the miniht registers
710 if(itype[i]==UJUMP||itype[i]==RJUMP)
711 {
712 hsn[RHASH]=0;
713 hsn[RHTBL]=0;
714 }
715}
716
717// We only want to allocate registers if we're going to use them again soon
718int needed_again(int r, int i)
719{
720 int j;
721 int b=-1;
722 int rn=10;
57871462 723
724 if(i>0&&(itype[i-1]==UJUMP||itype[i-1]==RJUMP||(source[i-1]>>16)==0x1000))
725 {
726 if(ba[i-1]<start || ba[i-1]>start+slen*4-4)
727 return 0; // Don't need any registers if exiting the block
728 }
729 for(j=0;j<9;j++)
730 {
731 if(i+j>=slen) {
732 j=slen-i-1;
733 break;
734 }
735 if(itype[i+j]==UJUMP||itype[i+j]==RJUMP||(source[i+j]>>16)==0x1000)
736 {
737 // Don't go past an unconditonal jump
738 j++;
739 break;
740 }
1e973cb0 741 if(itype[i+j]==SYSCALL||itype[i+j]==HLECALL||itype[i+j]==INTCALL||((source[i+j]&0xfc00003f)==0x0d))
57871462 742 {
743 break;
744 }
745 }
746 for(;j>=1;j--)
747 {
748 if(rs1[i+j]==r) rn=j;
749 if(rs2[i+j]==r) rn=j;
750 if((unneeded_reg[i+j]>>r)&1) rn=10;
751 if(i+j>=0&&(itype[i+j]==UJUMP||itype[i+j]==CJUMP||itype[i+j]==SJUMP||itype[i+j]==FJUMP))
752 {
753 b=j;
754 }
755 }
756 /*
757 if(b>=0)
758 {
759 if(ba[i+b]>=start && ba[i+b]<(start+slen*4))
760 {
761 // Follow first branch
762 int o=rn;
763 int t=(ba[i+b]-start)>>2;
764 j=7-b;if(t+j>=slen) j=slen-t-1;
765 for(;j>=0;j--)
766 {
767 if(!((unneeded_reg[t+j]>>r)&1)) {
768 if(rs1[t+j]==r) if(rn>j+b+2) rn=j+b+2;
769 if(rs2[t+j]==r) if(rn>j+b+2) rn=j+b+2;
770 }
771 else rn=o;
772 }
773 }
774 }*/
b7217e13 775 if(rn<10) return 1;
57871462 776 return 0;
777}
778
779// Try to match register allocations at the end of a loop with those
780// at the beginning
781int loop_reg(int i, int r, int hr)
782{
783 int j,k;
784 for(j=0;j<9;j++)
785 {
786 if(i+j>=slen) {
787 j=slen-i-1;
788 break;
789 }
790 if(itype[i+j]==UJUMP||itype[i+j]==RJUMP||(source[i+j]>>16)==0x1000)
791 {
792 // Don't go past an unconditonal jump
793 j++;
794 break;
795 }
796 }
797 k=0;
798 if(i>0){
799 if(itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP)
800 k--;
801 }
802 for(;k<j;k++)
803 {
804 if(r<64&&((unneeded_reg[i+k]>>r)&1)) return hr;
805 if(r>64&&((unneeded_reg_upper[i+k]>>r)&1)) return hr;
806 if(i+k>=0&&(itype[i+k]==UJUMP||itype[i+k]==CJUMP||itype[i+k]==SJUMP||itype[i+k]==FJUMP))
807 {
808 if(ba[i+k]>=start && ba[i+k]<(start+i*4))
809 {
810 int t=(ba[i+k]-start)>>2;
811 int reg=get_reg(regs[t].regmap_entry,r);
812 if(reg>=0) return reg;
813 //reg=get_reg(regs[t+1].regmap_entry,r);
814 //if(reg>=0) return reg;
815 }
816 }
817 }
818 return hr;
819}
820
821
822// Allocate every register, preserving source/target regs
823void alloc_all(struct regstat *cur,int i)
824{
825 int hr;
826
827 for(hr=0;hr<HOST_REGS;hr++) {
828 if(hr!=EXCLUDE_REG) {
829 if(((cur->regmap[hr]&63)!=rs1[i])&&((cur->regmap[hr]&63)!=rs2[i])&&
830 ((cur->regmap[hr]&63)!=rt1[i])&&((cur->regmap[hr]&63)!=rt2[i]))
831 {
832 cur->regmap[hr]=-1;
833 cur->dirty&=~(1<<hr);
834 }
835 // Don't need zeros
836 if((cur->regmap[hr]&63)==0)
837 {
838 cur->regmap[hr]=-1;
839 cur->dirty&=~(1<<hr);
840 }
841 }
842 }
843}
844
845
846void div64(int64_t dividend,int64_t divisor)
847{
848 lo=dividend/divisor;
849 hi=dividend%divisor;
850 //printf("TRACE: ddiv %8x%8x %8x%8x\n" ,(int)reg[HIREG],(int)(reg[HIREG]>>32)
851 // ,(int)reg[LOREG],(int)(reg[LOREG]>>32));
852}
853void divu64(uint64_t dividend,uint64_t divisor)
854{
855 lo=dividend/divisor;
856 hi=dividend%divisor;
857 //printf("TRACE: ddivu %8x%8x %8x%8x\n",(int)reg[HIREG],(int)(reg[HIREG]>>32)
858 // ,(int)reg[LOREG],(int)(reg[LOREG]>>32));
859}
860
861void mult64(uint64_t m1,uint64_t m2)
862{
863 unsigned long long int op1, op2, op3, op4;
864 unsigned long long int result1, result2, result3, result4;
865 unsigned long long int temp1, temp2, temp3, temp4;
866 int sign = 0;
867
868 if (m1 < 0)
869 {
870 op2 = -m1;
871 sign = 1 - sign;
872 }
873 else op2 = m1;
874 if (m2 < 0)
875 {
876 op4 = -m2;
877 sign = 1 - sign;
878 }
879 else op4 = m2;
880
881 op1 = op2 & 0xFFFFFFFF;
882 op2 = (op2 >> 32) & 0xFFFFFFFF;
883 op3 = op4 & 0xFFFFFFFF;
884 op4 = (op4 >> 32) & 0xFFFFFFFF;
885
886 temp1 = op1 * op3;
887 temp2 = (temp1 >> 32) + op1 * op4;
888 temp3 = op2 * op3;
889 temp4 = (temp3 >> 32) + op2 * op4;
890
891 result1 = temp1 & 0xFFFFFFFF;
892 result2 = temp2 + (temp3 & 0xFFFFFFFF);
893 result3 = (result2 >> 32) + temp4;
894 result4 = (result3 >> 32);
895
896 lo = result1 | (result2 << 32);
897 hi = (result3 & 0xFFFFFFFF) | (result4 << 32);
898 if (sign)
899 {
900 hi = ~hi;
901 if (!lo) hi++;
902 else lo = ~lo + 1;
903 }
904}
905
906void multu64(uint64_t m1,uint64_t m2)
907{
908 unsigned long long int op1, op2, op3, op4;
909 unsigned long long int result1, result2, result3, result4;
910 unsigned long long int temp1, temp2, temp3, temp4;
911
912 op1 = m1 & 0xFFFFFFFF;
913 op2 = (m1 >> 32) & 0xFFFFFFFF;
914 op3 = m2 & 0xFFFFFFFF;
915 op4 = (m2 >> 32) & 0xFFFFFFFF;
916
917 temp1 = op1 * op3;
918 temp2 = (temp1 >> 32) + op1 * op4;
919 temp3 = op2 * op3;
920 temp4 = (temp3 >> 32) + op2 * op4;
921
922 result1 = temp1 & 0xFFFFFFFF;
923 result2 = temp2 + (temp3 & 0xFFFFFFFF);
924 result3 = (result2 >> 32) + temp4;
925 result4 = (result3 >> 32);
926
927 lo = result1 | (result2 << 32);
928 hi = (result3 & 0xFFFFFFFF) | (result4 << 32);
929
930 //printf("TRACE: dmultu %8x%8x %8x%8x\n",(int)reg[HIREG],(int)(reg[HIREG]>>32)
931 // ,(int)reg[LOREG],(int)(reg[LOREG]>>32));
932}
933
934uint64_t ldl_merge(uint64_t original,uint64_t loaded,u_int bits)
935{
936 if(bits) {
937 original<<=64-bits;
938 original>>=64-bits;
939 loaded<<=bits;
940 original|=loaded;
941 }
942 else original=loaded;
943 return original;
944}
945uint64_t ldr_merge(uint64_t original,uint64_t loaded,u_int bits)
946{
947 if(bits^56) {
948 original>>=64-(bits^56);
949 original<<=64-(bits^56);
950 loaded>>=bits^56;
951 original|=loaded;
952 }
953 else original=loaded;
954 return original;
955}
956
957#ifdef __i386__
958#include "assem_x86.c"
959#endif
960#ifdef __x86_64__
961#include "assem_x64.c"
962#endif
963#ifdef __arm__
964#include "assem_arm.c"
965#endif
966
967// Add virtual address mapping to linked list
968void ll_add(struct ll_entry **head,int vaddr,void *addr)
969{
970 struct ll_entry *new_entry;
971 new_entry=malloc(sizeof(struct ll_entry));
972 assert(new_entry!=NULL);
973 new_entry->vaddr=vaddr;
974 new_entry->reg32=0;
975 new_entry->addr=addr;
976 new_entry->next=*head;
977 *head=new_entry;
978}
979
980// Add virtual address mapping for 32-bit compiled block
981void ll_add_32(struct ll_entry **head,int vaddr,u_int reg32,void *addr)
982{
7139f3c8 983 ll_add(head,vaddr,addr);
984#ifndef FORCE32
985 (*head)->reg32=reg32;
986#endif
57871462 987}
988
989// Check if an address is already compiled
990// but don't return addresses which are about to expire from the cache
991void *check_addr(u_int vaddr)
992{
993 u_int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
994 if(ht_bin[0]==vaddr) {
995 if(((ht_bin[1]-MAX_OUTPUT_BLOCK_SIZE-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
996 if(isclean(ht_bin[1])) return (void *)ht_bin[1];
997 }
998 if(ht_bin[2]==vaddr) {
999 if(((ht_bin[3]-MAX_OUTPUT_BLOCK_SIZE-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
1000 if(isclean(ht_bin[3])) return (void *)ht_bin[3];
1001 }
94d23bb9 1002 u_int page=get_page(vaddr);
57871462 1003 struct ll_entry *head;
1004 head=jump_in[page];
1005 while(head!=NULL) {
1006 if(head->vaddr==vaddr&&head->reg32==0) {
1007 if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2))) {
1008 // Update existing entry with current address
1009 if(ht_bin[0]==vaddr) {
1010 ht_bin[1]=(int)head->addr;
1011 return head->addr;
1012 }
1013 if(ht_bin[2]==vaddr) {
1014 ht_bin[3]=(int)head->addr;
1015 return head->addr;
1016 }
1017 // Insert into hash table with low priority.
1018 // Don't evict existing entries, as they are probably
1019 // addresses that are being accessed frequently.
1020 if(ht_bin[0]==-1) {
1021 ht_bin[1]=(int)head->addr;
1022 ht_bin[0]=vaddr;
1023 }else if(ht_bin[2]==-1) {
1024 ht_bin[3]=(int)head->addr;
1025 ht_bin[2]=vaddr;
1026 }
1027 return head->addr;
1028 }
1029 }
1030 head=head->next;
1031 }
1032 return 0;
1033}
1034
1035void remove_hash(int vaddr)
1036{
1037 //printf("remove hash: %x\n",vaddr);
1038 int *ht_bin=hash_table[(((vaddr)>>16)^vaddr)&0xFFFF];
1039 if(ht_bin[2]==vaddr) {
1040 ht_bin[2]=ht_bin[3]=-1;
1041 }
1042 if(ht_bin[0]==vaddr) {
1043 ht_bin[0]=ht_bin[2];
1044 ht_bin[1]=ht_bin[3];
1045 ht_bin[2]=ht_bin[3]=-1;
1046 }
1047}
1048
1049void ll_remove_matching_addrs(struct ll_entry **head,int addr,int shift)
1050{
1051 struct ll_entry *next;
1052 while(*head) {
1053 if(((u_int)((*head)->addr)>>shift)==(addr>>shift) ||
1054 ((u_int)((*head)->addr-MAX_OUTPUT_BLOCK_SIZE)>>shift)==(addr>>shift))
1055 {
1056 inv_debug("EXP: Remove pointer to %x (%x)\n",(int)(*head)->addr,(*head)->vaddr);
1057 remove_hash((*head)->vaddr);
1058 next=(*head)->next;
1059 free(*head);
1060 *head=next;
1061 }
1062 else
1063 {
1064 head=&((*head)->next);
1065 }
1066 }
1067}
1068
1069// Remove all entries from linked list
1070void ll_clear(struct ll_entry **head)
1071{
1072 struct ll_entry *cur;
1073 struct ll_entry *next;
1074 if(cur=*head) {
1075 *head=0;
1076 while(cur) {
1077 next=cur->next;
1078 free(cur);
1079 cur=next;
1080 }
1081 }
1082}
1083
1084// Dereference the pointers and remove if it matches
1085void ll_kill_pointers(struct ll_entry *head,int addr,int shift)
1086{
1087 while(head) {
1088 int ptr=get_pointer(head->addr);
1089 inv_debug("EXP: Lookup pointer to %x at %x (%x)\n",(int)ptr,(int)head->addr,head->vaddr);
1090 if(((ptr>>shift)==(addr>>shift)) ||
1091 (((ptr-MAX_OUTPUT_BLOCK_SIZE)>>shift)==(addr>>shift)))
1092 {
5088bb70 1093 inv_debug("EXP: Kill pointer at %x (%x)\n",(int)head->addr,head->vaddr);
f76eeef9 1094 u_int host_addr=(u_int)kill_pointer(head->addr);
dd3a91a1 1095 #ifdef __arm__
1096 needs_clear_cache[(host_addr-(u_int)BASE_ADDR)>>17]|=1<<(((host_addr-(u_int)BASE_ADDR)>>12)&31);
1097 #endif
57871462 1098 }
1099 head=head->next;
1100 }
1101}
1102
1103// This is called when we write to a compiled block (see do_invstub)
f76eeef9 1104void invalidate_page(u_int page)
57871462 1105{
57871462 1106 struct ll_entry *head;
1107 struct ll_entry *next;
1108 head=jump_in[page];
1109 jump_in[page]=0;
1110 while(head!=NULL) {
1111 inv_debug("INVALIDATE: %x\n",head->vaddr);
1112 remove_hash(head->vaddr);
1113 next=head->next;
1114 free(head);
1115 head=next;
1116 }
1117 head=jump_out[page];
1118 jump_out[page]=0;
1119 while(head!=NULL) {
1120 inv_debug("INVALIDATE: kill pointer to %x (%x)\n",head->vaddr,(int)head->addr);
f76eeef9 1121 u_int host_addr=(u_int)kill_pointer(head->addr);
dd3a91a1 1122 #ifdef __arm__
1123 needs_clear_cache[(host_addr-(u_int)BASE_ADDR)>>17]|=1<<(((host_addr-(u_int)BASE_ADDR)>>12)&31);
1124 #endif
57871462 1125 next=head->next;
1126 free(head);
1127 head=next;
1128 }
57871462 1129}
1130void invalidate_block(u_int block)
1131{
94d23bb9 1132 u_int page=get_page(block<<12);
1133 u_int vpage=get_vpage(block<<12);
57871462 1134 inv_debug("INVALIDATE: %x (%d)\n",block<<12,page);
1135 //inv_debug("invalid_code[block]=%d\n",invalid_code[block]);
1136 u_int first,last;
1137 first=last=page;
1138 struct ll_entry *head;
1139 head=jump_dirty[vpage];
1140 //printf("page=%d vpage=%d\n",page,vpage);
1141 while(head!=NULL) {
1142 u_int start,end;
1143 if(vpage>2047||(head->vaddr>>12)==block) { // Ignore vaddr hash collision
1144 get_bounds((int)head->addr,&start,&end);
1145 //printf("start: %x end: %x\n",start,end);
4cb76aa4 1146 if(page<2048&&start>=0x80000000&&end<0x80000000+RAM_SIZE) {
57871462 1147 if(((start-(u_int)rdram)>>12)<=page&&((end-1-(u_int)rdram)>>12)>=page) {
1148 if((((start-(u_int)rdram)>>12)&2047)<first) first=((start-(u_int)rdram)>>12)&2047;
1149 if((((end-1-(u_int)rdram)>>12)&2047)>last) last=((end-1-(u_int)rdram)>>12)&2047;
1150 }
1151 }
90ae6d4e 1152#ifndef DISABLE_TLB
57871462 1153 if(page<2048&&(signed int)start>=(signed int)0xC0000000&&(signed int)end>=(signed int)0xC0000000) {
1154 if(((start+memory_map[start>>12]-(u_int)rdram)>>12)<=page&&((end-1+memory_map[(end-1)>>12]-(u_int)rdram)>>12)>=page) {
1155 if((((start+memory_map[start>>12]-(u_int)rdram)>>12)&2047)<first) first=((start+memory_map[start>>12]-(u_int)rdram)>>12)&2047;
1156 if((((end-1+memory_map[(end-1)>>12]-(u_int)rdram)>>12)&2047)>last) last=((end-1+memory_map[(end-1)>>12]-(u_int)rdram)>>12)&2047;
1157 }
1158 }
90ae6d4e 1159#endif
57871462 1160 }
1161 head=head->next;
1162 }
1163 //printf("first=%d last=%d\n",first,last);
f76eeef9 1164 invalidate_page(page);
57871462 1165 assert(first+5>page); // NB: this assumes MAXBLOCK<=4096 (4 pages)
1166 assert(last<page+5);
1167 // Invalidate the adjacent pages if a block crosses a 4K boundary
1168 while(first<page) {
1169 invalidate_page(first);
1170 first++;
1171 }
1172 for(first=page+1;first<last;first++) {
1173 invalidate_page(first);
1174 }
dd3a91a1 1175 #ifdef __arm__
1176 do_clear_cache();
1177 #endif
57871462 1178
1179 // Don't trap writes
1180 invalid_code[block]=1;
b12c9fb8 1181#ifdef PCSX
1182 invalid_code[((u_int)0x80000000>>12)|page]=1;
1183#endif
94d23bb9 1184#ifndef DISABLE_TLB
57871462 1185 // If there is a valid TLB entry for this page, remove write protect
1186 if(tlb_LUT_w[block]) {
1187 assert(tlb_LUT_r[block]==tlb_LUT_w[block]);
1188 // CHECK: Is this right?
1189 memory_map[block]=((tlb_LUT_w[block]&0xFFFFF000)-(block<<12)+(unsigned int)rdram-0x80000000)>>2;
1190 u_int real_block=tlb_LUT_w[block]>>12;
1191 invalid_code[real_block]=1;
1192 if(real_block>=0x80000&&real_block<0x80800) memory_map[real_block]=((u_int)rdram-0x80000000)>>2;
1193 }
1194 else if(block>=0x80000&&block<0x80800) memory_map[block]=((u_int)rdram-0x80000000)>>2;
94d23bb9 1195#endif
f76eeef9 1196
57871462 1197 #ifdef USE_MINI_HT
1198 memset(mini_ht,-1,sizeof(mini_ht));
1199 #endif
1200}
1201void invalidate_addr(u_int addr)
1202{
1203 invalidate_block(addr>>12);
1204}
dd3a91a1 1205// This is called when loading a save state.
1206// Anything could have changed, so invalidate everything.
57871462 1207void invalidate_all_pages()
1208{
1209 u_int page,n;
1210 for(page=0;page<4096;page++)
1211 invalidate_page(page);
1212 for(page=0;page<1048576;page++)
1213 if(!invalid_code[page]) {
1214 restore_candidate[(page&2047)>>3]|=1<<(page&7);
1215 restore_candidate[((page&2047)>>3)+256]|=1<<(page&7);
1216 }
1217 #ifdef __arm__
1218 __clear_cache((void *)BASE_ADDR,(void *)BASE_ADDR+(1<<TARGET_SIZE_2));
1219 #endif
1220 #ifdef USE_MINI_HT
1221 memset(mini_ht,-1,sizeof(mini_ht));
1222 #endif
94d23bb9 1223 #ifndef DISABLE_TLB
57871462 1224 // TLB
1225 for(page=0;page<0x100000;page++) {
1226 if(tlb_LUT_r[page]) {
1227 memory_map[page]=((tlb_LUT_r[page]&0xFFFFF000)-(page<<12)+(unsigned int)rdram-0x80000000)>>2;
1228 if(!tlb_LUT_w[page]||!invalid_code[page])
1229 memory_map[page]|=0x40000000; // Write protect
1230 }
1231 else memory_map[page]=-1;
1232 if(page==0x80000) page=0xC0000;
1233 }
1234 tlb_hacks();
94d23bb9 1235 #endif
57871462 1236}
1237
1238// Add an entry to jump_out after making a link
1239void add_link(u_int vaddr,void *src)
1240{
94d23bb9 1241 u_int page=get_page(vaddr);
57871462 1242 inv_debug("add_link: %x -> %x (%d)\n",(int)src,vaddr,page);
1243 ll_add(jump_out+page,vaddr,src);
1244 //int ptr=get_pointer(src);
1245 //inv_debug("add_link: Pointer is to %x\n",(int)ptr);
1246}
1247
1248// If a code block was found to be unmodified (bit was set in
1249// restore_candidate) and it remains unmodified (bit is clear
1250// in invalid_code) then move the entries for that 4K page from
1251// the dirty list to the clean list.
1252void clean_blocks(u_int page)
1253{
1254 struct ll_entry *head;
1255 inv_debug("INV: clean_blocks page=%d\n",page);
1256 head=jump_dirty[page];
1257 while(head!=NULL) {
1258 if(!invalid_code[head->vaddr>>12]) {
1259 // Don't restore blocks which are about to expire from the cache
1260 if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2))) {
1261 u_int start,end;
1262 if(verify_dirty((int)head->addr)) {
1263 //printf("Possibly Restore %x (%x)\n",head->vaddr, (int)head->addr);
1264 u_int i;
1265 u_int inv=0;
1266 get_bounds((int)head->addr,&start,&end);
4cb76aa4 1267 if(start-(u_int)rdram<RAM_SIZE) {
57871462 1268 for(i=(start-(u_int)rdram+0x80000000)>>12;i<=(end-1-(u_int)rdram+0x80000000)>>12;i++) {
1269 inv|=invalid_code[i];
1270 }
1271 }
1272 if((signed int)head->vaddr>=(signed int)0xC0000000) {
1273 u_int addr = (head->vaddr+(memory_map[head->vaddr>>12]<<2));
1274 //printf("addr=%x start=%x end=%x\n",addr,start,end);
1275 if(addr<start||addr>=end) inv=1;
1276 }
4cb76aa4 1277 else if((signed int)head->vaddr>=(signed int)0x80000000+RAM_SIZE) {
57871462 1278 inv=1;
1279 }
1280 if(!inv) {
1281 void * clean_addr=(void *)get_clean_addr((int)head->addr);
1282 if((((u_int)clean_addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2))) {
1283 u_int ppage=page;
94d23bb9 1284#ifndef DISABLE_TLB
57871462 1285 if(page<2048&&tlb_LUT_r[head->vaddr>>12]) ppage=(tlb_LUT_r[head->vaddr>>12]^0x80000000)>>12;
94d23bb9 1286#endif
57871462 1287 inv_debug("INV: Restored %x (%x/%x)\n",head->vaddr, (int)head->addr, (int)clean_addr);
1288 //printf("page=%x, addr=%x\n",page,head->vaddr);
1289 //assert(head->vaddr>>12==(page|0x80000));
1290 ll_add_32(jump_in+ppage,head->vaddr,head->reg32,clean_addr);
1291 int *ht_bin=hash_table[((head->vaddr>>16)^head->vaddr)&0xFFFF];
1292 if(!head->reg32) {
1293 if(ht_bin[0]==head->vaddr) {
1294 ht_bin[1]=(int)clean_addr; // Replace existing entry
1295 }
1296 if(ht_bin[2]==head->vaddr) {
1297 ht_bin[3]=(int)clean_addr; // Replace existing entry
1298 }
1299 }
1300 }
1301 }
1302 }
1303 }
1304 }
1305 head=head->next;
1306 }
1307}
1308
1309
1310void mov_alloc(struct regstat *current,int i)
1311{
1312 // Note: Don't need to actually alloc the source registers
1313 if((~current->is32>>rs1[i])&1) {
1314 //alloc_reg64(current,i,rs1[i]);
1315 alloc_reg64(current,i,rt1[i]);
1316 current->is32&=~(1LL<<rt1[i]);
1317 } else {
1318 //alloc_reg(current,i,rs1[i]);
1319 alloc_reg(current,i,rt1[i]);
1320 current->is32|=(1LL<<rt1[i]);
1321 }
1322 clear_const(current,rs1[i]);
1323 clear_const(current,rt1[i]);
1324 dirty_reg(current,rt1[i]);
1325}
1326
1327void shiftimm_alloc(struct regstat *current,int i)
1328{
1329 clear_const(current,rs1[i]);
1330 clear_const(current,rt1[i]);
1331 if(opcode2[i]<=0x3) // SLL/SRL/SRA
1332 {
1333 if(rt1[i]) {
1334 if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1335 else lt1[i]=rs1[i];
1336 alloc_reg(current,i,rt1[i]);
1337 current->is32|=1LL<<rt1[i];
1338 dirty_reg(current,rt1[i]);
1339 }
1340 }
1341 if(opcode2[i]>=0x38&&opcode2[i]<=0x3b) // DSLL/DSRL/DSRA
1342 {
1343 if(rt1[i]) {
1344 if(rs1[i]) alloc_reg64(current,i,rs1[i]);
1345 alloc_reg64(current,i,rt1[i]);
1346 current->is32&=~(1LL<<rt1[i]);
1347 dirty_reg(current,rt1[i]);
1348 }
1349 }
1350 if(opcode2[i]==0x3c) // DSLL32
1351 {
1352 if(rt1[i]) {
1353 if(rs1[i]) alloc_reg(current,i,rs1[i]);
1354 alloc_reg64(current,i,rt1[i]);
1355 current->is32&=~(1LL<<rt1[i]);
1356 dirty_reg(current,rt1[i]);
1357 }
1358 }
1359 if(opcode2[i]==0x3e) // DSRL32
1360 {
1361 if(rt1[i]) {
1362 alloc_reg64(current,i,rs1[i]);
1363 if(imm[i]==32) {
1364 alloc_reg64(current,i,rt1[i]);
1365 current->is32&=~(1LL<<rt1[i]);
1366 } else {
1367 alloc_reg(current,i,rt1[i]);
1368 current->is32|=1LL<<rt1[i];
1369 }
1370 dirty_reg(current,rt1[i]);
1371 }
1372 }
1373 if(opcode2[i]==0x3f) // DSRA32
1374 {
1375 if(rt1[i]) {
1376 alloc_reg64(current,i,rs1[i]);
1377 alloc_reg(current,i,rt1[i]);
1378 current->is32|=1LL<<rt1[i];
1379 dirty_reg(current,rt1[i]);
1380 }
1381 }
1382}
1383
1384void shift_alloc(struct regstat *current,int i)
1385{
1386 if(rt1[i]) {
1387 if(opcode2[i]<=0x07) // SLLV/SRLV/SRAV
1388 {
1389 if(rs1[i]) alloc_reg(current,i,rs1[i]);
1390 if(rs2[i]) alloc_reg(current,i,rs2[i]);
1391 alloc_reg(current,i,rt1[i]);
e1190b87 1392 if(rt1[i]==rs2[i]) {
1393 alloc_reg_temp(current,i,-1);
1394 minimum_free_regs[i]=1;
1395 }
57871462 1396 current->is32|=1LL<<rt1[i];
1397 } else { // DSLLV/DSRLV/DSRAV
1398 if(rs1[i]) alloc_reg64(current,i,rs1[i]);
1399 if(rs2[i]) alloc_reg(current,i,rs2[i]);
1400 alloc_reg64(current,i,rt1[i]);
1401 current->is32&=~(1LL<<rt1[i]);
1402 if(opcode2[i]==0x16||opcode2[i]==0x17) // DSRLV and DSRAV need a temporary register
e1190b87 1403 {
57871462 1404 alloc_reg_temp(current,i,-1);
e1190b87 1405 minimum_free_regs[i]=1;
1406 }
57871462 1407 }
1408 clear_const(current,rs1[i]);
1409 clear_const(current,rs2[i]);
1410 clear_const(current,rt1[i]);
1411 dirty_reg(current,rt1[i]);
1412 }
1413}
1414
1415void alu_alloc(struct regstat *current,int i)
1416{
1417 if(opcode2[i]>=0x20&&opcode2[i]<=0x23) { // ADD/ADDU/SUB/SUBU
1418 if(rt1[i]) {
1419 if(rs1[i]&&rs2[i]) {
1420 alloc_reg(current,i,rs1[i]);
1421 alloc_reg(current,i,rs2[i]);
1422 }
1423 else {
1424 if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1425 if(rs2[i]&&needed_again(rs2[i],i)) alloc_reg(current,i,rs2[i]);
1426 }
1427 alloc_reg(current,i,rt1[i]);
1428 }
1429 current->is32|=1LL<<rt1[i];
1430 }
1431 if(opcode2[i]==0x2a||opcode2[i]==0x2b) { // SLT/SLTU
1432 if(rt1[i]) {
1433 if(!((current->is32>>rs1[i])&(current->is32>>rs2[i])&1))
1434 {
1435 alloc_reg64(current,i,rs1[i]);
1436 alloc_reg64(current,i,rs2[i]);
1437 alloc_reg(current,i,rt1[i]);
1438 } else {
1439 alloc_reg(current,i,rs1[i]);
1440 alloc_reg(current,i,rs2[i]);
1441 alloc_reg(current,i,rt1[i]);
1442 }
1443 }
1444 current->is32|=1LL<<rt1[i];
1445 }
1446 if(opcode2[i]>=0x24&&opcode2[i]<=0x27) { // AND/OR/XOR/NOR
1447 if(rt1[i]) {
1448 if(rs1[i]&&rs2[i]) {
1449 alloc_reg(current,i,rs1[i]);
1450 alloc_reg(current,i,rs2[i]);
1451 }
1452 else
1453 {
1454 if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1455 if(rs2[i]&&needed_again(rs2[i],i)) alloc_reg(current,i,rs2[i]);
1456 }
1457 alloc_reg(current,i,rt1[i]);
1458 if(!((current->is32>>rs1[i])&(current->is32>>rs2[i])&1))
1459 {
1460 if(!((current->uu>>rt1[i])&1)) {
1461 alloc_reg64(current,i,rt1[i]);
1462 }
1463 if(get_reg(current->regmap,rt1[i]|64)>=0) {
1464 if(rs1[i]&&rs2[i]) {
1465 alloc_reg64(current,i,rs1[i]);
1466 alloc_reg64(current,i,rs2[i]);
1467 }
1468 else
1469 {
1470 // Is is really worth it to keep 64-bit values in registers?
1471 #ifdef NATIVE_64BIT
1472 if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg64(current,i,rs1[i]);
1473 if(rs2[i]&&needed_again(rs2[i],i)) alloc_reg64(current,i,rs2[i]);
1474 #endif
1475 }
1476 }
1477 current->is32&=~(1LL<<rt1[i]);
1478 } else {
1479 current->is32|=1LL<<rt1[i];
1480 }
1481 }
1482 }
1483 if(opcode2[i]>=0x2c&&opcode2[i]<=0x2f) { // DADD/DADDU/DSUB/DSUBU
1484 if(rt1[i]) {
1485 if(rs1[i]&&rs2[i]) {
1486 if(!((current->uu>>rt1[i])&1)||get_reg(current->regmap,rt1[i]|64)>=0) {
1487 alloc_reg64(current,i,rs1[i]);
1488 alloc_reg64(current,i,rs2[i]);
1489 alloc_reg64(current,i,rt1[i]);
1490 } else {
1491 alloc_reg(current,i,rs1[i]);
1492 alloc_reg(current,i,rs2[i]);
1493 alloc_reg(current,i,rt1[i]);
1494 }
1495 }
1496 else {
1497 alloc_reg(current,i,rt1[i]);
1498 if(!((current->uu>>rt1[i])&1)||get_reg(current->regmap,rt1[i]|64)>=0) {
1499 // DADD used as move, or zeroing
1500 // If we have a 64-bit source, then make the target 64 bits too
1501 if(rs1[i]&&!((current->is32>>rs1[i])&1)) {
1502 if(get_reg(current->regmap,rs1[i])>=0) alloc_reg64(current,i,rs1[i]);
1503 alloc_reg64(current,i,rt1[i]);
1504 } else if(rs2[i]&&!((current->is32>>rs2[i])&1)) {
1505 if(get_reg(current->regmap,rs2[i])>=0) alloc_reg64(current,i,rs2[i]);
1506 alloc_reg64(current,i,rt1[i]);
1507 }
1508 if(opcode2[i]>=0x2e&&rs2[i]) {
1509 // DSUB used as negation - 64-bit result
1510 // If we have a 32-bit register, extend it to 64 bits
1511 if(get_reg(current->regmap,rs2[i])>=0) alloc_reg64(current,i,rs2[i]);
1512 alloc_reg64(current,i,rt1[i]);
1513 }
1514 }
1515 }
1516 if(rs1[i]&&rs2[i]) {
1517 current->is32&=~(1LL<<rt1[i]);
1518 } else if(rs1[i]) {
1519 current->is32&=~(1LL<<rt1[i]);
1520 if((current->is32>>rs1[i])&1)
1521 current->is32|=1LL<<rt1[i];
1522 } else if(rs2[i]) {
1523 current->is32&=~(1LL<<rt1[i]);
1524 if((current->is32>>rs2[i])&1)
1525 current->is32|=1LL<<rt1[i];
1526 } else {
1527 current->is32|=1LL<<rt1[i];
1528 }
1529 }
1530 }
1531 clear_const(current,rs1[i]);
1532 clear_const(current,rs2[i]);
1533 clear_const(current,rt1[i]);
1534 dirty_reg(current,rt1[i]);
1535}
1536
1537void imm16_alloc(struct regstat *current,int i)
1538{
1539 if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1540 else lt1[i]=rs1[i];
1541 if(rt1[i]) alloc_reg(current,i,rt1[i]);
1542 if(opcode[i]==0x18||opcode[i]==0x19) { // DADDI/DADDIU
1543 current->is32&=~(1LL<<rt1[i]);
1544 if(!((current->uu>>rt1[i])&1)||get_reg(current->regmap,rt1[i]|64)>=0) {
1545 // TODO: Could preserve the 32-bit flag if the immediate is zero
1546 alloc_reg64(current,i,rt1[i]);
1547 alloc_reg64(current,i,rs1[i]);
1548 }
1549 clear_const(current,rs1[i]);
1550 clear_const(current,rt1[i]);
1551 }
1552 else if(opcode[i]==0x0a||opcode[i]==0x0b) { // SLTI/SLTIU
1553 if((~current->is32>>rs1[i])&1) alloc_reg64(current,i,rs1[i]);
1554 current->is32|=1LL<<rt1[i];
1555 clear_const(current,rs1[i]);
1556 clear_const(current,rt1[i]);
1557 }
1558 else if(opcode[i]>=0x0c&&opcode[i]<=0x0e) { // ANDI/ORI/XORI
1559 if(((~current->is32>>rs1[i])&1)&&opcode[i]>0x0c) {
1560 if(rs1[i]!=rt1[i]) {
1561 if(needed_again(rs1[i],i)) alloc_reg64(current,i,rs1[i]);
1562 alloc_reg64(current,i,rt1[i]);
1563 current->is32&=~(1LL<<rt1[i]);
1564 }
1565 }
1566 else current->is32|=1LL<<rt1[i]; // ANDI clears upper bits
1567 if(is_const(current,rs1[i])) {
1568 int v=get_const(current,rs1[i]);
1569 if(opcode[i]==0x0c) set_const(current,rt1[i],v&imm[i]);
1570 if(opcode[i]==0x0d) set_const(current,rt1[i],v|imm[i]);
1571 if(opcode[i]==0x0e) set_const(current,rt1[i],v^imm[i]);
1572 }
1573 else clear_const(current,rt1[i]);
1574 }
1575 else if(opcode[i]==0x08||opcode[i]==0x09) { // ADDI/ADDIU
1576 if(is_const(current,rs1[i])) {
1577 int v=get_const(current,rs1[i]);
1578 set_const(current,rt1[i],v+imm[i]);
1579 }
1580 else clear_const(current,rt1[i]);
1581 current->is32|=1LL<<rt1[i];
1582 }
1583 else {
1584 set_const(current,rt1[i],((long long)((short)imm[i]))<<16); // LUI
1585 current->is32|=1LL<<rt1[i];
1586 }
1587 dirty_reg(current,rt1[i]);
1588}
1589
1590void load_alloc(struct regstat *current,int i)
1591{
1592 clear_const(current,rt1[i]);
1593 //if(rs1[i]!=rt1[i]&&needed_again(rs1[i],i)) clear_const(current,rs1[i]); // Does this help or hurt?
1594 if(!rs1[i]) current->u&=~1LL; // Allow allocating r0 if it's the source register
1595 if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1596 if(rt1[i]) {
1597 alloc_reg(current,i,rt1[i]);
535d208a 1598 if(get_reg(current->regmap,rt1[i])<0) {
1599 // dummy load, but we still need a register to calculate the address
1600 alloc_reg_temp(current,i,-1);
e1190b87 1601 minimum_free_regs[i]=1;
535d208a 1602 }
57871462 1603 if(opcode[i]==0x27||opcode[i]==0x37) // LWU/LD
1604 {
1605 current->is32&=~(1LL<<rt1[i]);
1606 alloc_reg64(current,i,rt1[i]);
1607 }
1608 else if(opcode[i]==0x1A||opcode[i]==0x1B) // LDL/LDR
1609 {
1610 current->is32&=~(1LL<<rt1[i]);
1611 alloc_reg64(current,i,rt1[i]);
1612 alloc_all(current,i);
1613 alloc_reg64(current,i,FTEMP);
e1190b87 1614 minimum_free_regs[i]=HOST_REGS;
57871462 1615 }
1616 else current->is32|=1LL<<rt1[i];
1617 dirty_reg(current,rt1[i]);
1618 // If using TLB, need a register for pointer to the mapping table
1619 if(using_tlb) alloc_reg(current,i,TLREG);
1620 // LWL/LWR need a temporary register for the old value
1621 if(opcode[i]==0x22||opcode[i]==0x26)
1622 {
1623 alloc_reg(current,i,FTEMP);
1624 alloc_reg_temp(current,i,-1);
e1190b87 1625 minimum_free_regs[i]=1;
57871462 1626 }
1627 }
1628 else
1629 {
1630 // Load to r0 (dummy load)
1631 // but we still need a register to calculate the address
535d208a 1632 if(opcode[i]==0x22||opcode[i]==0x26)
1633 {
1634 alloc_reg(current,i,FTEMP); // LWL/LWR need another temporary
1635 }
57871462 1636 alloc_reg_temp(current,i,-1);
e1190b87 1637 minimum_free_regs[i]=1;
535d208a 1638 if(opcode[i]==0x1A||opcode[i]==0x1B) // LDL/LDR
1639 {
1640 alloc_all(current,i);
1641 alloc_reg64(current,i,FTEMP);
e1190b87 1642 minimum_free_regs[i]=HOST_REGS;
535d208a 1643 }
57871462 1644 }
1645}
1646
1647void store_alloc(struct regstat *current,int i)
1648{
1649 clear_const(current,rs2[i]);
1650 if(!(rs2[i])) current->u&=~1LL; // Allow allocating r0 if necessary
1651 if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1652 alloc_reg(current,i,rs2[i]);
1653 if(opcode[i]==0x2c||opcode[i]==0x2d||opcode[i]==0x3f) { // 64-bit SDL/SDR/SD
1654 alloc_reg64(current,i,rs2[i]);
1655 if(rs2[i]) alloc_reg(current,i,FTEMP);
1656 }
1657 // If using TLB, need a register for pointer to the mapping table
1658 if(using_tlb) alloc_reg(current,i,TLREG);
1659 #if defined(HOST_IMM8)
1660 // On CPUs without 32-bit immediates we need a pointer to invalid_code
1661 else alloc_reg(current,i,INVCP);
1662 #endif
b7918751 1663 if(opcode[i]==0x2a||opcode[i]==0x2e||opcode[i]==0x2c||opcode[i]==0x2d) { // SWL/SWL/SDL/SDR
57871462 1664 alloc_reg(current,i,FTEMP);
1665 }
1666 // We need a temporary register for address generation
1667 alloc_reg_temp(current,i,-1);
e1190b87 1668 minimum_free_regs[i]=1;
57871462 1669}
1670
1671void c1ls_alloc(struct regstat *current,int i)
1672{
1673 //clear_const(current,rs1[i]); // FIXME
1674 clear_const(current,rt1[i]);
1675 if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1676 alloc_reg(current,i,CSREG); // Status
1677 alloc_reg(current,i,FTEMP);
1678 if(opcode[i]==0x35||opcode[i]==0x3d) { // 64-bit LDC1/SDC1
1679 alloc_reg64(current,i,FTEMP);
1680 }
1681 // If using TLB, need a register for pointer to the mapping table
1682 if(using_tlb) alloc_reg(current,i,TLREG);
1683 #if defined(HOST_IMM8)
1684 // On CPUs without 32-bit immediates we need a pointer to invalid_code
1685 else if((opcode[i]&0x3b)==0x39) // SWC1/SDC1
1686 alloc_reg(current,i,INVCP);
1687 #endif
1688 // We need a temporary register for address generation
1689 alloc_reg_temp(current,i,-1);
1690}
1691
b9b61529 1692void c2ls_alloc(struct regstat *current,int i)
1693{
1694 clear_const(current,rt1[i]);
1695 if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1696 alloc_reg(current,i,FTEMP);
1697 // If using TLB, need a register for pointer to the mapping table
1698 if(using_tlb) alloc_reg(current,i,TLREG);
1699 #if defined(HOST_IMM8)
1700 // On CPUs without 32-bit immediates we need a pointer to invalid_code
1701 else if((opcode[i]&0x3b)==0x3a) // SWC2/SDC2
1702 alloc_reg(current,i,INVCP);
1703 #endif
1704 // We need a temporary register for address generation
1705 alloc_reg_temp(current,i,-1);
e1190b87 1706 minimum_free_regs[i]=1;
b9b61529 1707}
1708
57871462 1709#ifndef multdiv_alloc
1710void multdiv_alloc(struct regstat *current,int i)
1711{
1712 // case 0x18: MULT
1713 // case 0x19: MULTU
1714 // case 0x1A: DIV
1715 // case 0x1B: DIVU
1716 // case 0x1C: DMULT
1717 // case 0x1D: DMULTU
1718 // case 0x1E: DDIV
1719 // case 0x1F: DDIVU
1720 clear_const(current,rs1[i]);
1721 clear_const(current,rs2[i]);
1722 if(rs1[i]&&rs2[i])
1723 {
1724 if((opcode2[i]&4)==0) // 32-bit
1725 {
1726 current->u&=~(1LL<<HIREG);
1727 current->u&=~(1LL<<LOREG);
1728 alloc_reg(current,i,HIREG);
1729 alloc_reg(current,i,LOREG);
1730 alloc_reg(current,i,rs1[i]);
1731 alloc_reg(current,i,rs2[i]);
1732 current->is32|=1LL<<HIREG;
1733 current->is32|=1LL<<LOREG;
1734 dirty_reg(current,HIREG);
1735 dirty_reg(current,LOREG);
1736 }
1737 else // 64-bit
1738 {
1739 current->u&=~(1LL<<HIREG);
1740 current->u&=~(1LL<<LOREG);
1741 current->uu&=~(1LL<<HIREG);
1742 current->uu&=~(1LL<<LOREG);
1743 alloc_reg64(current,i,HIREG);
1744 //if(HOST_REGS>10) alloc_reg64(current,i,LOREG);
1745 alloc_reg64(current,i,rs1[i]);
1746 alloc_reg64(current,i,rs2[i]);
1747 alloc_all(current,i);
1748 current->is32&=~(1LL<<HIREG);
1749 current->is32&=~(1LL<<LOREG);
1750 dirty_reg(current,HIREG);
1751 dirty_reg(current,LOREG);
e1190b87 1752 minimum_free_regs[i]=HOST_REGS;
57871462 1753 }
1754 }
1755 else
1756 {
1757 // Multiply by zero is zero.
1758 // MIPS does not have a divide by zero exception.
1759 // The result is undefined, we return zero.
1760 alloc_reg(current,i,HIREG);
1761 alloc_reg(current,i,LOREG);
1762 current->is32|=1LL<<HIREG;
1763 current->is32|=1LL<<LOREG;
1764 dirty_reg(current,HIREG);
1765 dirty_reg(current,LOREG);
1766 }
1767}
1768#endif
1769
1770void cop0_alloc(struct regstat *current,int i)
1771{
1772 if(opcode2[i]==0) // MFC0
1773 {
1774 if(rt1[i]) {
1775 clear_const(current,rt1[i]);
1776 alloc_all(current,i);
1777 alloc_reg(current,i,rt1[i]);
1778 current->is32|=1LL<<rt1[i];
1779 dirty_reg(current,rt1[i]);
1780 }
1781 }
1782 else if(opcode2[i]==4) // MTC0
1783 {
1784 if(rs1[i]){
1785 clear_const(current,rs1[i]);
1786 alloc_reg(current,i,rs1[i]);
1787 alloc_all(current,i);
1788 }
1789 else {
1790 alloc_all(current,i); // FIXME: Keep r0
1791 current->u&=~1LL;
1792 alloc_reg(current,i,0);
1793 }
1794 }
1795 else
1796 {
1797 // TLBR/TLBWI/TLBWR/TLBP/ERET
1798 assert(opcode2[i]==0x10);
1799 alloc_all(current,i);
1800 }
e1190b87 1801 minimum_free_regs[i]=HOST_REGS;
57871462 1802}
1803
1804void cop1_alloc(struct regstat *current,int i)
1805{
1806 alloc_reg(current,i,CSREG); // Load status
1807 if(opcode2[i]<3) // MFC1/DMFC1/CFC1
1808 {
7de557a6 1809 if(rt1[i]){
1810 clear_const(current,rt1[i]);
1811 if(opcode2[i]==1) {
1812 alloc_reg64(current,i,rt1[i]); // DMFC1
1813 current->is32&=~(1LL<<rt1[i]);
1814 }else{
1815 alloc_reg(current,i,rt1[i]); // MFC1/CFC1
1816 current->is32|=1LL<<rt1[i];
1817 }
1818 dirty_reg(current,rt1[i]);
57871462 1819 }
57871462 1820 alloc_reg_temp(current,i,-1);
1821 }
1822 else if(opcode2[i]>3) // MTC1/DMTC1/CTC1
1823 {
1824 if(rs1[i]){
1825 clear_const(current,rs1[i]);
1826 if(opcode2[i]==5)
1827 alloc_reg64(current,i,rs1[i]); // DMTC1
1828 else
1829 alloc_reg(current,i,rs1[i]); // MTC1/CTC1
1830 alloc_reg_temp(current,i,-1);
1831 }
1832 else {
1833 current->u&=~1LL;
1834 alloc_reg(current,i,0);
1835 alloc_reg_temp(current,i,-1);
1836 }
1837 }
e1190b87 1838 minimum_free_regs[i]=1;
57871462 1839}
1840void fconv_alloc(struct regstat *current,int i)
1841{
1842 alloc_reg(current,i,CSREG); // Load status
1843 alloc_reg_temp(current,i,-1);
e1190b87 1844 minimum_free_regs[i]=1;
57871462 1845}
1846void float_alloc(struct regstat *current,int i)
1847{
1848 alloc_reg(current,i,CSREG); // Load status
1849 alloc_reg_temp(current,i,-1);
e1190b87 1850 minimum_free_regs[i]=1;
57871462 1851}
b9b61529 1852void c2op_alloc(struct regstat *current,int i)
1853{
1854 alloc_reg_temp(current,i,-1);
1855}
57871462 1856void fcomp_alloc(struct regstat *current,int i)
1857{
1858 alloc_reg(current,i,CSREG); // Load status
1859 alloc_reg(current,i,FSREG); // Load flags
1860 dirty_reg(current,FSREG); // Flag will be modified
1861 alloc_reg_temp(current,i,-1);
e1190b87 1862 minimum_free_regs[i]=1;
57871462 1863}
1864
1865void syscall_alloc(struct regstat *current,int i)
1866{
1867 alloc_cc(current,i);
1868 dirty_reg(current,CCREG);
1869 alloc_all(current,i);
e1190b87 1870 minimum_free_regs[i]=HOST_REGS;
57871462 1871 current->isconst=0;
1872}
1873
1874void delayslot_alloc(struct regstat *current,int i)
1875{
1876 switch(itype[i]) {
1877 case UJUMP:
1878 case CJUMP:
1879 case SJUMP:
1880 case RJUMP:
1881 case FJUMP:
1882 case SYSCALL:
7139f3c8 1883 case HLECALL:
57871462 1884 case SPAN:
1885 assem_debug("jump in the delay slot. this shouldn't happen.\n");//exit(1);
1886 printf("Disabled speculative precompilation\n");
1887 stop_after_jal=1;
1888 break;
1889 case IMM16:
1890 imm16_alloc(current,i);
1891 break;
1892 case LOAD:
1893 case LOADLR:
1894 load_alloc(current,i);
1895 break;
1896 case STORE:
1897 case STORELR:
1898 store_alloc(current,i);
1899 break;
1900 case ALU:
1901 alu_alloc(current,i);
1902 break;
1903 case SHIFT:
1904 shift_alloc(current,i);
1905 break;
1906 case MULTDIV:
1907 multdiv_alloc(current,i);
1908 break;
1909 case SHIFTIMM:
1910 shiftimm_alloc(current,i);
1911 break;
1912 case MOV:
1913 mov_alloc(current,i);
1914 break;
1915 case COP0:
1916 cop0_alloc(current,i);
1917 break;
1918 case COP1:
b9b61529 1919 case COP2:
57871462 1920 cop1_alloc(current,i);
1921 break;
1922 case C1LS:
1923 c1ls_alloc(current,i);
1924 break;
b9b61529 1925 case C2LS:
1926 c2ls_alloc(current,i);
1927 break;
57871462 1928 case FCONV:
1929 fconv_alloc(current,i);
1930 break;
1931 case FLOAT:
1932 float_alloc(current,i);
1933 break;
1934 case FCOMP:
1935 fcomp_alloc(current,i);
1936 break;
b9b61529 1937 case C2OP:
1938 c2op_alloc(current,i);
1939 break;
57871462 1940 }
1941}
1942
1943// Special case where a branch and delay slot span two pages in virtual memory
1944static void pagespan_alloc(struct regstat *current,int i)
1945{
1946 current->isconst=0;
1947 current->wasconst=0;
1948 regs[i].wasconst=0;
e1190b87 1949 minimum_free_regs[i]=HOST_REGS;
57871462 1950 alloc_all(current,i);
1951 alloc_cc(current,i);
1952 dirty_reg(current,CCREG);
1953 if(opcode[i]==3) // JAL
1954 {
1955 alloc_reg(current,i,31);
1956 dirty_reg(current,31);
1957 }
1958 if(opcode[i]==0&&(opcode2[i]&0x3E)==8) // JR/JALR
1959 {
1960 alloc_reg(current,i,rs1[i]);
5067f341 1961 if (rt1[i]!=0) {
1962 alloc_reg(current,i,rt1[i]);
1963 dirty_reg(current,rt1[i]);
57871462 1964 }
1965 }
1966 if((opcode[i]&0x2E)==4) // BEQ/BNE/BEQL/BNEL
1967 {
1968 if(rs1[i]) alloc_reg(current,i,rs1[i]);
1969 if(rs2[i]) alloc_reg(current,i,rs2[i]);
1970 if(!((current->is32>>rs1[i])&(current->is32>>rs2[i])&1))
1971 {
1972 if(rs1[i]) alloc_reg64(current,i,rs1[i]);
1973 if(rs2[i]) alloc_reg64(current,i,rs2[i]);
1974 }
1975 }
1976 else
1977 if((opcode[i]&0x2E)==6) // BLEZ/BGTZ/BLEZL/BGTZL
1978 {
1979 if(rs1[i]) alloc_reg(current,i,rs1[i]);
1980 if(!((current->is32>>rs1[i])&1))
1981 {
1982 if(rs1[i]) alloc_reg64(current,i,rs1[i]);
1983 }
1984 }
1985 else
1986 if(opcode[i]==0x11) // BC1
1987 {
1988 alloc_reg(current,i,FSREG);
1989 alloc_reg(current,i,CSREG);
1990 }
1991 //else ...
1992}
1993
1994add_stub(int type,int addr,int retaddr,int a,int b,int c,int d,int e)
1995{
1996 stubs[stubcount][0]=type;
1997 stubs[stubcount][1]=addr;
1998 stubs[stubcount][2]=retaddr;
1999 stubs[stubcount][3]=a;
2000 stubs[stubcount][4]=b;
2001 stubs[stubcount][5]=c;
2002 stubs[stubcount][6]=d;
2003 stubs[stubcount][7]=e;
2004 stubcount++;
2005}
2006
2007// Write out a single register
2008void wb_register(signed char r,signed char regmap[],uint64_t dirty,uint64_t is32)
2009{
2010 int hr;
2011 for(hr=0;hr<HOST_REGS;hr++) {
2012 if(hr!=EXCLUDE_REG) {
2013 if((regmap[hr]&63)==r) {
2014 if((dirty>>hr)&1) {
2015 if(regmap[hr]<64) {
2016 emit_storereg(r,hr);
24385cae 2017#ifndef FORCE32
57871462 2018 if((is32>>regmap[hr])&1) {
2019 emit_sarimm(hr,31,hr);
2020 emit_storereg(r|64,hr);
2021 }
24385cae 2022#endif
57871462 2023 }else{
2024 emit_storereg(r|64,hr);
2025 }
2026 }
2027 }
2028 }
2029 }
2030}
2031
2032int mchecksum()
2033{
2034 //if(!tracedebug) return 0;
2035 int i;
2036 int sum=0;
2037 for(i=0;i<2097152;i++) {
2038 unsigned int temp=sum;
2039 sum<<=1;
2040 sum|=(~temp)>>31;
2041 sum^=((u_int *)rdram)[i];
2042 }
2043 return sum;
2044}
2045int rchecksum()
2046{
2047 int i;
2048 int sum=0;
2049 for(i=0;i<64;i++)
2050 sum^=((u_int *)reg)[i];
2051 return sum;
2052}
57871462 2053void rlist()
2054{
2055 int i;
2056 printf("TRACE: ");
2057 for(i=0;i<32;i++)
2058 printf("r%d:%8x%8x ",i,((int *)(reg+i))[1],((int *)(reg+i))[0]);
2059 printf("\n");
3d624f89 2060#ifndef DISABLE_COP1
57871462 2061 printf("TRACE: ");
2062 for(i=0;i<32;i++)
2063 printf("f%d:%8x%8x ",i,((int*)reg_cop1_simple[i])[1],*((int*)reg_cop1_simple[i]));
2064 printf("\n");
3d624f89 2065#endif
57871462 2066}
2067
2068void enabletrace()
2069{
2070 tracedebug=1;
2071}
2072
2073void memdebug(int i)
2074{
2075 //printf("TRACE: count=%d next=%d (checksum %x) lo=%8x%8x\n",Count,next_interupt,mchecksum(),(int)(reg[LOREG]>>32),(int)reg[LOREG]);
2076 //printf("TRACE: count=%d next=%d (rchecksum %x)\n",Count,next_interupt,rchecksum());
2077 //rlist();
2078 //if(tracedebug) {
2079 //if(Count>=-2084597794) {
2080 if((signed int)Count>=-2084597794&&(signed int)Count<0) {
2081 //if(0) {
2082 printf("TRACE: count=%d next=%d (checksum %x)\n",Count,next_interupt,mchecksum());
2083 //printf("TRACE: count=%d next=%d (checksum %x) Status=%x\n",Count,next_interupt,mchecksum(),Status);
2084 //printf("TRACE: count=%d next=%d (checksum %x) hi=%8x%8x\n",Count,next_interupt,mchecksum(),(int)(reg[HIREG]>>32),(int)reg[HIREG]);
2085 rlist();
2086 #ifdef __i386__
2087 printf("TRACE: %x\n",(&i)[-1]);
2088 #endif
2089 #ifdef __arm__
2090 int j;
2091 printf("TRACE: %x \n",(&j)[10]);
2092 printf("TRACE: %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x\n",(&j)[1],(&j)[2],(&j)[3],(&j)[4],(&j)[5],(&j)[6],(&j)[7],(&j)[8],(&j)[9],(&j)[10],(&j)[11],(&j)[12],(&j)[13],(&j)[14],(&j)[15],(&j)[16],(&j)[17],(&j)[18],(&j)[19],(&j)[20]);
2093 #endif
2094 //fflush(stdout);
2095 }
2096 //printf("TRACE: %x\n",(&i)[-1]);
2097}
2098
2099void tlb_debug(u_int cause, u_int addr, u_int iaddr)
2100{
2101 printf("TLB Exception: instruction=%x addr=%x cause=%x\n",iaddr, addr, cause);
2102}
2103
2104void alu_assemble(int i,struct regstat *i_regs)
2105{
2106 if(opcode2[i]>=0x20&&opcode2[i]<=0x23) { // ADD/ADDU/SUB/SUBU
2107 if(rt1[i]) {
2108 signed char s1,s2,t;
2109 t=get_reg(i_regs->regmap,rt1[i]);
2110 if(t>=0) {
2111 s1=get_reg(i_regs->regmap,rs1[i]);
2112 s2=get_reg(i_regs->regmap,rs2[i]);
2113 if(rs1[i]&&rs2[i]) {
2114 assert(s1>=0);
2115 assert(s2>=0);
2116 if(opcode2[i]&2) emit_sub(s1,s2,t);
2117 else emit_add(s1,s2,t);
2118 }
2119 else if(rs1[i]) {
2120 if(s1>=0) emit_mov(s1,t);
2121 else emit_loadreg(rs1[i],t);
2122 }
2123 else if(rs2[i]) {
2124 if(s2>=0) {
2125 if(opcode2[i]&2) emit_neg(s2,t);
2126 else emit_mov(s2,t);
2127 }
2128 else {
2129 emit_loadreg(rs2[i],t);
2130 if(opcode2[i]&2) emit_neg(t,t);
2131 }
2132 }
2133 else emit_zeroreg(t);
2134 }
2135 }
2136 }
2137 if(opcode2[i]>=0x2c&&opcode2[i]<=0x2f) { // DADD/DADDU/DSUB/DSUBU
2138 if(rt1[i]) {
2139 signed char s1l,s2l,s1h,s2h,tl,th;
2140 tl=get_reg(i_regs->regmap,rt1[i]);
2141 th=get_reg(i_regs->regmap,rt1[i]|64);
2142 if(tl>=0) {
2143 s1l=get_reg(i_regs->regmap,rs1[i]);
2144 s2l=get_reg(i_regs->regmap,rs2[i]);
2145 s1h=get_reg(i_regs->regmap,rs1[i]|64);
2146 s2h=get_reg(i_regs->regmap,rs2[i]|64);
2147 if(rs1[i]&&rs2[i]) {
2148 assert(s1l>=0);
2149 assert(s2l>=0);
2150 if(opcode2[i]&2) emit_subs(s1l,s2l,tl);
2151 else emit_adds(s1l,s2l,tl);
2152 if(th>=0) {
2153 #ifdef INVERTED_CARRY
2154 if(opcode2[i]&2) {if(s1h!=th) emit_mov(s1h,th);emit_sbb(th,s2h);}
2155 #else
2156 if(opcode2[i]&2) emit_sbc(s1h,s2h,th);
2157 #endif
2158 else emit_add(s1h,s2h,th);
2159 }
2160 }
2161 else if(rs1[i]) {
2162 if(s1l>=0) emit_mov(s1l,tl);
2163 else emit_loadreg(rs1[i],tl);
2164 if(th>=0) {
2165 if(s1h>=0) emit_mov(s1h,th);
2166 else emit_loadreg(rs1[i]|64,th);
2167 }
2168 }
2169 else if(rs2[i]) {
2170 if(s2l>=0) {
2171 if(opcode2[i]&2) emit_negs(s2l,tl);
2172 else emit_mov(s2l,tl);
2173 }
2174 else {
2175 emit_loadreg(rs2[i],tl);
2176 if(opcode2[i]&2) emit_negs(tl,tl);
2177 }
2178 if(th>=0) {
2179 #ifdef INVERTED_CARRY
2180 if(s2h>=0) emit_mov(s2h,th);
2181 else emit_loadreg(rs2[i]|64,th);
2182 if(opcode2[i]&2) {
2183 emit_adcimm(-1,th); // x86 has inverted carry flag
2184 emit_not(th,th);
2185 }
2186 #else
2187 if(opcode2[i]&2) {
2188 if(s2h>=0) emit_rscimm(s2h,0,th);
2189 else {
2190 emit_loadreg(rs2[i]|64,th);
2191 emit_rscimm(th,0,th);
2192 }
2193 }else{
2194 if(s2h>=0) emit_mov(s2h,th);
2195 else emit_loadreg(rs2[i]|64,th);
2196 }
2197 #endif
2198 }
2199 }
2200 else {
2201 emit_zeroreg(tl);
2202 if(th>=0) emit_zeroreg(th);
2203 }
2204 }
2205 }
2206 }
2207 if(opcode2[i]==0x2a||opcode2[i]==0x2b) { // SLT/SLTU
2208 if(rt1[i]) {
2209 signed char s1l,s1h,s2l,s2h,t;
2210 if(!((i_regs->was32>>rs1[i])&(i_regs->was32>>rs2[i])&1))
2211 {
2212 t=get_reg(i_regs->regmap,rt1[i]);
2213 //assert(t>=0);
2214 if(t>=0) {
2215 s1l=get_reg(i_regs->regmap,rs1[i]);
2216 s1h=get_reg(i_regs->regmap,rs1[i]|64);
2217 s2l=get_reg(i_regs->regmap,rs2[i]);
2218 s2h=get_reg(i_regs->regmap,rs2[i]|64);
2219 if(rs2[i]==0) // rx<r0
2220 {
2221 assert(s1h>=0);
2222 if(opcode2[i]==0x2a) // SLT
2223 emit_shrimm(s1h,31,t);
2224 else // SLTU (unsigned can not be less than zero)
2225 emit_zeroreg(t);
2226 }
2227 else if(rs1[i]==0) // r0<rx
2228 {
2229 assert(s2h>=0);
2230 if(opcode2[i]==0x2a) // SLT
2231 emit_set_gz64_32(s2h,s2l,t);
2232 else // SLTU (set if not zero)
2233 emit_set_nz64_32(s2h,s2l,t);
2234 }
2235 else {
2236 assert(s1l>=0);assert(s1h>=0);
2237 assert(s2l>=0);assert(s2h>=0);
2238 if(opcode2[i]==0x2a) // SLT
2239 emit_set_if_less64_32(s1h,s1l,s2h,s2l,t);
2240 else // SLTU
2241 emit_set_if_carry64_32(s1h,s1l,s2h,s2l,t);
2242 }
2243 }
2244 } else {
2245 t=get_reg(i_regs->regmap,rt1[i]);
2246 //assert(t>=0);
2247 if(t>=0) {
2248 s1l=get_reg(i_regs->regmap,rs1[i]);
2249 s2l=get_reg(i_regs->regmap,rs2[i]);
2250 if(rs2[i]==0) // rx<r0
2251 {
2252 assert(s1l>=0);
2253 if(opcode2[i]==0x2a) // SLT
2254 emit_shrimm(s1l,31,t);
2255 else // SLTU (unsigned can not be less than zero)
2256 emit_zeroreg(t);
2257 }
2258 else if(rs1[i]==0) // r0<rx
2259 {
2260 assert(s2l>=0);
2261 if(opcode2[i]==0x2a) // SLT
2262 emit_set_gz32(s2l,t);
2263 else // SLTU (set if not zero)
2264 emit_set_nz32(s2l,t);
2265 }
2266 else{
2267 assert(s1l>=0);assert(s2l>=0);
2268 if(opcode2[i]==0x2a) // SLT
2269 emit_set_if_less32(s1l,s2l,t);
2270 else // SLTU
2271 emit_set_if_carry32(s1l,s2l,t);
2272 }
2273 }
2274 }
2275 }
2276 }
2277 if(opcode2[i]>=0x24&&opcode2[i]<=0x27) { // AND/OR/XOR/NOR
2278 if(rt1[i]) {
2279 signed char s1l,s1h,s2l,s2h,th,tl;
2280 tl=get_reg(i_regs->regmap,rt1[i]);
2281 th=get_reg(i_regs->regmap,rt1[i]|64);
2282 if(!((i_regs->was32>>rs1[i])&(i_regs->was32>>rs2[i])&1)&&th>=0)
2283 {
2284 assert(tl>=0);
2285 if(tl>=0) {
2286 s1l=get_reg(i_regs->regmap,rs1[i]);
2287 s1h=get_reg(i_regs->regmap,rs1[i]|64);
2288 s2l=get_reg(i_regs->regmap,rs2[i]);
2289 s2h=get_reg(i_regs->regmap,rs2[i]|64);
2290 if(rs1[i]&&rs2[i]) {
2291 assert(s1l>=0);assert(s1h>=0);
2292 assert(s2l>=0);assert(s2h>=0);
2293 if(opcode2[i]==0x24) { // AND
2294 emit_and(s1l,s2l,tl);
2295 emit_and(s1h,s2h,th);
2296 } else
2297 if(opcode2[i]==0x25) { // OR
2298 emit_or(s1l,s2l,tl);
2299 emit_or(s1h,s2h,th);
2300 } else
2301 if(opcode2[i]==0x26) { // XOR
2302 emit_xor(s1l,s2l,tl);
2303 emit_xor(s1h,s2h,th);
2304 } else
2305 if(opcode2[i]==0x27) { // NOR
2306 emit_or(s1l,s2l,tl);
2307 emit_or(s1h,s2h,th);
2308 emit_not(tl,tl);
2309 emit_not(th,th);
2310 }
2311 }
2312 else
2313 {
2314 if(opcode2[i]==0x24) { // AND
2315 emit_zeroreg(tl);
2316 emit_zeroreg(th);
2317 } else
2318 if(opcode2[i]==0x25||opcode2[i]==0x26) { // OR/XOR
2319 if(rs1[i]){
2320 if(s1l>=0) emit_mov(s1l,tl);
2321 else emit_loadreg(rs1[i],tl);
2322 if(s1h>=0) emit_mov(s1h,th);
2323 else emit_loadreg(rs1[i]|64,th);
2324 }
2325 else
2326 if(rs2[i]){
2327 if(s2l>=0) emit_mov(s2l,tl);
2328 else emit_loadreg(rs2[i],tl);
2329 if(s2h>=0) emit_mov(s2h,th);
2330 else emit_loadreg(rs2[i]|64,th);
2331 }
2332 else{
2333 emit_zeroreg(tl);
2334 emit_zeroreg(th);
2335 }
2336 } else
2337 if(opcode2[i]==0x27) { // NOR
2338 if(rs1[i]){
2339 if(s1l>=0) emit_not(s1l,tl);
2340 else{
2341 emit_loadreg(rs1[i],tl);
2342 emit_not(tl,tl);
2343 }
2344 if(s1h>=0) emit_not(s1h,th);
2345 else{
2346 emit_loadreg(rs1[i]|64,th);
2347 emit_not(th,th);
2348 }
2349 }
2350 else
2351 if(rs2[i]){
2352 if(s2l>=0) emit_not(s2l,tl);
2353 else{
2354 emit_loadreg(rs2[i],tl);
2355 emit_not(tl,tl);
2356 }
2357 if(s2h>=0) emit_not(s2h,th);
2358 else{
2359 emit_loadreg(rs2[i]|64,th);
2360 emit_not(th,th);
2361 }
2362 }
2363 else {
2364 emit_movimm(-1,tl);
2365 emit_movimm(-1,th);
2366 }
2367 }
2368 }
2369 }
2370 }
2371 else
2372 {
2373 // 32 bit
2374 if(tl>=0) {
2375 s1l=get_reg(i_regs->regmap,rs1[i]);
2376 s2l=get_reg(i_regs->regmap,rs2[i]);
2377 if(rs1[i]&&rs2[i]) {
2378 assert(s1l>=0);
2379 assert(s2l>=0);
2380 if(opcode2[i]==0x24) { // AND
2381 emit_and(s1l,s2l,tl);
2382 } else
2383 if(opcode2[i]==0x25) { // OR
2384 emit_or(s1l,s2l,tl);
2385 } else
2386 if(opcode2[i]==0x26) { // XOR
2387 emit_xor(s1l,s2l,tl);
2388 } else
2389 if(opcode2[i]==0x27) { // NOR
2390 emit_or(s1l,s2l,tl);
2391 emit_not(tl,tl);
2392 }
2393 }
2394 else
2395 {
2396 if(opcode2[i]==0x24) { // AND
2397 emit_zeroreg(tl);
2398 } else
2399 if(opcode2[i]==0x25||opcode2[i]==0x26) { // OR/XOR
2400 if(rs1[i]){
2401 if(s1l>=0) emit_mov(s1l,tl);
2402 else emit_loadreg(rs1[i],tl); // CHECK: regmap_entry?
2403 }
2404 else
2405 if(rs2[i]){
2406 if(s2l>=0) emit_mov(s2l,tl);
2407 else emit_loadreg(rs2[i],tl); // CHECK: regmap_entry?
2408 }
2409 else emit_zeroreg(tl);
2410 } else
2411 if(opcode2[i]==0x27) { // NOR
2412 if(rs1[i]){
2413 if(s1l>=0) emit_not(s1l,tl);
2414 else {
2415 emit_loadreg(rs1[i],tl);
2416 emit_not(tl,tl);
2417 }
2418 }
2419 else
2420 if(rs2[i]){
2421 if(s2l>=0) emit_not(s2l,tl);
2422 else {
2423 emit_loadreg(rs2[i],tl);
2424 emit_not(tl,tl);
2425 }
2426 }
2427 else emit_movimm(-1,tl);
2428 }
2429 }
2430 }
2431 }
2432 }
2433 }
2434}
2435
2436void imm16_assemble(int i,struct regstat *i_regs)
2437{
2438 if (opcode[i]==0x0f) { // LUI
2439 if(rt1[i]) {
2440 signed char t;
2441 t=get_reg(i_regs->regmap,rt1[i]);
2442 //assert(t>=0);
2443 if(t>=0) {
2444 if(!((i_regs->isconst>>t)&1))
2445 emit_movimm(imm[i]<<16,t);
2446 }
2447 }
2448 }
2449 if(opcode[i]==0x08||opcode[i]==0x09) { // ADDI/ADDIU
2450 if(rt1[i]) {
2451 signed char s,t;
2452 t=get_reg(i_regs->regmap,rt1[i]);
2453 s=get_reg(i_regs->regmap,rs1[i]);
2454 if(rs1[i]) {
2455 //assert(t>=0);
2456 //assert(s>=0);
2457 if(t>=0) {
2458 if(!((i_regs->isconst>>t)&1)) {
2459 if(s<0) {
2460 if(i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2461 emit_addimm(t,imm[i],t);
2462 }else{
2463 if(!((i_regs->wasconst>>s)&1))
2464 emit_addimm(s,imm[i],t);
2465 else
2466 emit_movimm(constmap[i][s]+imm[i],t);
2467 }
2468 }
2469 }
2470 } else {
2471 if(t>=0) {
2472 if(!((i_regs->isconst>>t)&1))
2473 emit_movimm(imm[i],t);
2474 }
2475 }
2476 }
2477 }
2478 if(opcode[i]==0x18||opcode[i]==0x19) { // DADDI/DADDIU
2479 if(rt1[i]) {
2480 signed char sh,sl,th,tl;
2481 th=get_reg(i_regs->regmap,rt1[i]|64);
2482 tl=get_reg(i_regs->regmap,rt1[i]);
2483 sh=get_reg(i_regs->regmap,rs1[i]|64);
2484 sl=get_reg(i_regs->regmap,rs1[i]);
2485 if(tl>=0) {
2486 if(rs1[i]) {
2487 assert(sh>=0);
2488 assert(sl>=0);
2489 if(th>=0) {
2490 emit_addimm64_32(sh,sl,imm[i],th,tl);
2491 }
2492 else {
2493 emit_addimm(sl,imm[i],tl);
2494 }
2495 } else {
2496 emit_movimm(imm[i],tl);
2497 if(th>=0) emit_movimm(((signed int)imm[i])>>31,th);
2498 }
2499 }
2500 }
2501 }
2502 else if(opcode[i]==0x0a||opcode[i]==0x0b) { // SLTI/SLTIU
2503 if(rt1[i]) {
2504 //assert(rs1[i]!=0); // r0 might be valid, but it's probably a bug
2505 signed char sh,sl,t;
2506 t=get_reg(i_regs->regmap,rt1[i]);
2507 sh=get_reg(i_regs->regmap,rs1[i]|64);
2508 sl=get_reg(i_regs->regmap,rs1[i]);
2509 //assert(t>=0);
2510 if(t>=0) {
2511 if(rs1[i]>0) {
2512 if(sh<0) assert((i_regs->was32>>rs1[i])&1);
2513 if(sh<0||((i_regs->was32>>rs1[i])&1)) {
2514 if(opcode[i]==0x0a) { // SLTI
2515 if(sl<0) {
2516 if(i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2517 emit_slti32(t,imm[i],t);
2518 }else{
2519 emit_slti32(sl,imm[i],t);
2520 }
2521 }
2522 else { // SLTIU
2523 if(sl<0) {
2524 if(i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2525 emit_sltiu32(t,imm[i],t);
2526 }else{
2527 emit_sltiu32(sl,imm[i],t);
2528 }
2529 }
2530 }else{ // 64-bit
2531 assert(sl>=0);
2532 if(opcode[i]==0x0a) // SLTI
2533 emit_slti64_32(sh,sl,imm[i],t);
2534 else // SLTIU
2535 emit_sltiu64_32(sh,sl,imm[i],t);
2536 }
2537 }else{
2538 // SLTI(U) with r0 is just stupid,
2539 // nonetheless examples can be found
2540 if(opcode[i]==0x0a) // SLTI
2541 if(0<imm[i]) emit_movimm(1,t);
2542 else emit_zeroreg(t);
2543 else // SLTIU
2544 {
2545 if(imm[i]) emit_movimm(1,t);
2546 else emit_zeroreg(t);
2547 }
2548 }
2549 }
2550 }
2551 }
2552 else if(opcode[i]>=0x0c&&opcode[i]<=0x0e) { // ANDI/ORI/XORI
2553 if(rt1[i]) {
2554 signed char sh,sl,th,tl;
2555 th=get_reg(i_regs->regmap,rt1[i]|64);
2556 tl=get_reg(i_regs->regmap,rt1[i]);
2557 sh=get_reg(i_regs->regmap,rs1[i]|64);
2558 sl=get_reg(i_regs->regmap,rs1[i]);
2559 if(tl>=0 && !((i_regs->isconst>>tl)&1)) {
2560 if(opcode[i]==0x0c) //ANDI
2561 {
2562 if(rs1[i]) {
2563 if(sl<0) {
2564 if(i_regs->regmap_entry[tl]!=rs1[i]) emit_loadreg(rs1[i],tl);
2565 emit_andimm(tl,imm[i],tl);
2566 }else{
2567 if(!((i_regs->wasconst>>sl)&1))
2568 emit_andimm(sl,imm[i],tl);
2569 else
2570 emit_movimm(constmap[i][sl]&imm[i],tl);
2571 }
2572 }
2573 else
2574 emit_zeroreg(tl);
2575 if(th>=0) emit_zeroreg(th);
2576 }
2577 else
2578 {
2579 if(rs1[i]) {
2580 if(sl<0) {
2581 if(i_regs->regmap_entry[tl]!=rs1[i]) emit_loadreg(rs1[i],tl);
2582 }
2583 if(th>=0) {
2584 if(sh<0) {
2585 emit_loadreg(rs1[i]|64,th);
2586 }else{
2587 emit_mov(sh,th);
2588 }
2589 }
2590 if(opcode[i]==0x0d) //ORI
2591 if(sl<0) {
2592 emit_orimm(tl,imm[i],tl);
2593 }else{
2594 if(!((i_regs->wasconst>>sl)&1))
2595 emit_orimm(sl,imm[i],tl);
2596 else
2597 emit_movimm(constmap[i][sl]|imm[i],tl);
2598 }
2599 if(opcode[i]==0x0e) //XORI
2600 if(sl<0) {
2601 emit_xorimm(tl,imm[i],tl);
2602 }else{
2603 if(!((i_regs->wasconst>>sl)&1))
2604 emit_xorimm(sl,imm[i],tl);
2605 else
2606 emit_movimm(constmap[i][sl]^imm[i],tl);
2607 }
2608 }
2609 else {
2610 emit_movimm(imm[i],tl);
2611 if(th>=0) emit_zeroreg(th);
2612 }
2613 }
2614 }
2615 }
2616 }
2617}
2618
2619void shiftimm_assemble(int i,struct regstat *i_regs)
2620{
2621 if(opcode2[i]<=0x3) // SLL/SRL/SRA
2622 {
2623 if(rt1[i]) {
2624 signed char s,t;
2625 t=get_reg(i_regs->regmap,rt1[i]);
2626 s=get_reg(i_regs->regmap,rs1[i]);
2627 //assert(t>=0);
2628 if(t>=0){
2629 if(rs1[i]==0)
2630 {
2631 emit_zeroreg(t);
2632 }
2633 else
2634 {
2635 if(s<0&&i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2636 if(imm[i]) {
2637 if(opcode2[i]==0) // SLL
2638 {
2639 emit_shlimm(s<0?t:s,imm[i],t);
2640 }
2641 if(opcode2[i]==2) // SRL
2642 {
2643 emit_shrimm(s<0?t:s,imm[i],t);
2644 }
2645 if(opcode2[i]==3) // SRA
2646 {
2647 emit_sarimm(s<0?t:s,imm[i],t);
2648 }
2649 }else{
2650 // Shift by zero
2651 if(s>=0 && s!=t) emit_mov(s,t);
2652 }
2653 }
2654 }
2655 //emit_storereg(rt1[i],t); //DEBUG
2656 }
2657 }
2658 if(opcode2[i]>=0x38&&opcode2[i]<=0x3b) // DSLL/DSRL/DSRA
2659 {
2660 if(rt1[i]) {
2661 signed char sh,sl,th,tl;
2662 th=get_reg(i_regs->regmap,rt1[i]|64);
2663 tl=get_reg(i_regs->regmap,rt1[i]);
2664 sh=get_reg(i_regs->regmap,rs1[i]|64);
2665 sl=get_reg(i_regs->regmap,rs1[i]);
2666 if(tl>=0) {
2667 if(rs1[i]==0)
2668 {
2669 emit_zeroreg(tl);
2670 if(th>=0) emit_zeroreg(th);
2671 }
2672 else
2673 {
2674 assert(sl>=0);
2675 assert(sh>=0);
2676 if(imm[i]) {
2677 if(opcode2[i]==0x38) // DSLL
2678 {
2679 if(th>=0) emit_shldimm(sh,sl,imm[i],th);
2680 emit_shlimm(sl,imm[i],tl);
2681 }
2682 if(opcode2[i]==0x3a) // DSRL
2683 {
2684 emit_shrdimm(sl,sh,imm[i],tl);
2685 if(th>=0) emit_shrimm(sh,imm[i],th);
2686 }
2687 if(opcode2[i]==0x3b) // DSRA
2688 {
2689 emit_shrdimm(sl,sh,imm[i],tl);
2690 if(th>=0) emit_sarimm(sh,imm[i],th);
2691 }
2692 }else{
2693 // Shift by zero
2694 if(sl!=tl) emit_mov(sl,tl);
2695 if(th>=0&&sh!=th) emit_mov(sh,th);
2696 }
2697 }
2698 }
2699 }
2700 }
2701 if(opcode2[i]==0x3c) // DSLL32
2702 {
2703 if(rt1[i]) {
2704 signed char sl,tl,th;
2705 tl=get_reg(i_regs->regmap,rt1[i]);
2706 th=get_reg(i_regs->regmap,rt1[i]|64);
2707 sl=get_reg(i_regs->regmap,rs1[i]);
2708 if(th>=0||tl>=0){
2709 assert(tl>=0);
2710 assert(th>=0);
2711 assert(sl>=0);
2712 emit_mov(sl,th);
2713 emit_zeroreg(tl);
2714 if(imm[i]>32)
2715 {
2716 emit_shlimm(th,imm[i]&31,th);
2717 }
2718 }
2719 }
2720 }
2721 if(opcode2[i]==0x3e) // DSRL32
2722 {
2723 if(rt1[i]) {
2724 signed char sh,tl,th;
2725 tl=get_reg(i_regs->regmap,rt1[i]);
2726 th=get_reg(i_regs->regmap,rt1[i]|64);
2727 sh=get_reg(i_regs->regmap,rs1[i]|64);
2728 if(tl>=0){
2729 assert(sh>=0);
2730 emit_mov(sh,tl);
2731 if(th>=0) emit_zeroreg(th);
2732 if(imm[i]>32)
2733 {
2734 emit_shrimm(tl,imm[i]&31,tl);
2735 }
2736 }
2737 }
2738 }
2739 if(opcode2[i]==0x3f) // DSRA32
2740 {
2741 if(rt1[i]) {
2742 signed char sh,tl;
2743 tl=get_reg(i_regs->regmap,rt1[i]);
2744 sh=get_reg(i_regs->regmap,rs1[i]|64);
2745 if(tl>=0){
2746 assert(sh>=0);
2747 emit_mov(sh,tl);
2748 if(imm[i]>32)
2749 {
2750 emit_sarimm(tl,imm[i]&31,tl);
2751 }
2752 }
2753 }
2754 }
2755}
2756
2757#ifndef shift_assemble
2758void shift_assemble(int i,struct regstat *i_regs)
2759{
2760 printf("Need shift_assemble for this architecture.\n");
2761 exit(1);
2762}
2763#endif
2764
2765void load_assemble(int i,struct regstat *i_regs)
2766{
2767 int s,th,tl,addr,map=-1;
2768 int offset;
2769 int jaddr=0;
5bf843dc 2770 int memtarget=0,c=0;
57871462 2771 u_int hr,reglist=0;
2772 th=get_reg(i_regs->regmap,rt1[i]|64);
2773 tl=get_reg(i_regs->regmap,rt1[i]);
2774 s=get_reg(i_regs->regmap,rs1[i]);
2775 offset=imm[i];
2776 for(hr=0;hr<HOST_REGS;hr++) {
2777 if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
2778 }
2779 if(i_regs->regmap[HOST_CCREG]==CCREG) reglist&=~(1<<HOST_CCREG);
2780 if(s>=0) {
2781 c=(i_regs->wasconst>>s)&1;
af4ee1fe 2782 if (c) {
2783 memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
2784 if(using_tlb&&((signed int)(constmap[i][s]+offset))>=(signed int)0xC0000000) memtarget=1;
2785 }
57871462 2786 }
57871462 2787 //printf("load_assemble: c=%d\n",c);
2788 //if(c) printf("load_assemble: const=%x\n",(int)constmap[i][s]+offset);
2789 // FIXME: Even if the load is a NOP, we should check for pagefaults...
5bf843dc 2790#ifdef PCSX
f18c0f46 2791 if(tl<0&&(!c||(((u_int)constmap[i][s]+offset)>>16)==0x1f80)
2792 ||rt1[i]==0) {
5bf843dc 2793 // could be FIFO, must perform the read
f18c0f46 2794 // ||dummy read
5bf843dc 2795 assem_debug("(forced read)\n");
2796 tl=get_reg(i_regs->regmap,-1);
2797 assert(tl>=0);
5bf843dc 2798 }
f18c0f46 2799#endif
5bf843dc 2800 if(offset||s<0||c) addr=tl;
2801 else addr=s;
535d208a 2802 //if(tl<0) tl=get_reg(i_regs->regmap,-1);
2803 if(tl>=0) {
2804 //printf("load_assemble: c=%d\n",c);
2805 //if(c) printf("load_assemble: const=%x\n",(int)constmap[i][s]+offset);
2806 assert(tl>=0); // Even if the load is a NOP, we must check for pagefaults and I/O
2807 reglist&=~(1<<tl);
2808 if(th>=0) reglist&=~(1<<th);
2809 if(!using_tlb) {
2810 if(!c) {
2811 #ifdef RAM_OFFSET
2812 map=get_reg(i_regs->regmap,ROREG);
2813 if(map<0) emit_loadreg(ROREG,map=HOST_TEMPREG);
2814 #endif
57871462 2815//#define R29_HACK 1
535d208a 2816 #ifdef R29_HACK
2817 // Strmnnrmn's speed hack
2818 if(rs1[i]!=29||start<0x80001000||start>=0x80000000+RAM_SIZE)
2819 #endif
2820 {
dadf55f2 2821 #ifdef PCSX
2822 if(sp_in_mirror&&rs1[i]==29) {
2823 emit_andimm(addr,~0x00e00000,HOST_TEMPREG);
2824 emit_cmpimm(HOST_TEMPREG,RAM_SIZE);
2825 }
2826 else
2827 #endif
535d208a 2828 emit_cmpimm(addr,RAM_SIZE);
2829 jaddr=(int)out;
2830 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
2831 // Hint to branch predictor that the branch is unlikely to be taken
2832 if(rs1[i]>=28)
2833 emit_jno_unlikely(0);
2834 else
57871462 2835 #endif
535d208a 2836 emit_jno(0);
57871462 2837 }
535d208a 2838 }
2839 }else{ // using tlb
2840 int x=0;
2841 if (opcode[i]==0x20||opcode[i]==0x24) x=3; // LB/LBU
2842 if (opcode[i]==0x21||opcode[i]==0x25) x=2; // LH/LHU
2843 map=get_reg(i_regs->regmap,TLREG);
2844 assert(map>=0);
2845 map=do_tlb_r(addr,tl,map,x,-1,-1,c,constmap[i][s]+offset);
2846 do_tlb_r_branch(map,c,constmap[i][s]+offset,&jaddr);
2847 }
2848 int dummy=(rt1[i]==0)||(tl!=get_reg(i_regs->regmap,rt1[i])); // ignore loads to r0 and unneeded reg
2849 if (opcode[i]==0x20) { // LB
2850 if(!c||memtarget) {
2851 if(!dummy) {
57871462 2852 #ifdef HOST_IMM_ADDR32
2853 if(c)
2854 emit_movsbl_tlb((constmap[i][s]+offset)^3,map,tl);
2855 else
2856 #endif
2857 {
2858 //emit_xorimm(addr,3,tl);
2859 //gen_tlb_addr_r(tl,map);
2860 //emit_movsbl_indexed((int)rdram-0x80000000,tl,tl);
535d208a 2861 int x=0,a=tl;
2002a1db 2862#ifdef BIG_ENDIAN_MIPS
57871462 2863 if(!c) emit_xorimm(addr,3,tl);
2864 else x=((constmap[i][s]+offset)^3)-(constmap[i][s]+offset);
2002a1db 2865#else
535d208a 2866 if(!c) a=addr;
dadf55f2 2867#endif
2868#ifdef PCSX
2869 if(sp_in_mirror&&rs1[i]==29) a=HOST_TEMPREG;
2002a1db 2870#endif
535d208a 2871 emit_movsbl_indexed_tlb(x,a,map,tl);
57871462 2872 }
57871462 2873 }
535d208a 2874 if(jaddr)
2875 add_stub(LOADB_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
57871462 2876 }
535d208a 2877 else
2878 inline_readstub(LOADB_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2879 }
2880 if (opcode[i]==0x21) { // LH
2881 if(!c||memtarget) {
2882 if(!dummy) {
57871462 2883 #ifdef HOST_IMM_ADDR32
2884 if(c)
2885 emit_movswl_tlb((constmap[i][s]+offset)^2,map,tl);
2886 else
2887 #endif
2888 {
535d208a 2889 int x=0,a=tl;
2002a1db 2890#ifdef BIG_ENDIAN_MIPS
57871462 2891 if(!c) emit_xorimm(addr,2,tl);
2892 else x=((constmap[i][s]+offset)^2)-(constmap[i][s]+offset);
2002a1db 2893#else
535d208a 2894 if(!c) a=addr;
dadf55f2 2895#endif
2896#ifdef PCSX
2897 if(sp_in_mirror&&rs1[i]==29) a=HOST_TEMPREG;
2002a1db 2898#endif
57871462 2899 //#ifdef
2900 //emit_movswl_indexed_tlb(x,tl,map,tl);
2901 //else
2902 if(map>=0) {
535d208a 2903 gen_tlb_addr_r(a,map);
2904 emit_movswl_indexed(x,a,tl);
2905 }else{
2906 #ifdef RAM_OFFSET
2907 emit_movswl_indexed(x,a,tl);
2908 #else
2909 emit_movswl_indexed((int)rdram-0x80000000+x,a,tl);
2910 #endif
2911 }
57871462 2912 }
57871462 2913 }
535d208a 2914 if(jaddr)
2915 add_stub(LOADH_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
57871462 2916 }
535d208a 2917 else
2918 inline_readstub(LOADH_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2919 }
2920 if (opcode[i]==0x23) { // LW
2921 if(!c||memtarget) {
2922 if(!dummy) {
dadf55f2 2923 int a=addr;
2924#ifdef PCSX
2925 if(sp_in_mirror&&rs1[i]==29) a=HOST_TEMPREG;
2926#endif
57871462 2927 //emit_readword_indexed((int)rdram-0x80000000,addr,tl);
2928 #ifdef HOST_IMM_ADDR32
2929 if(c)
2930 emit_readword_tlb(constmap[i][s]+offset,map,tl);
2931 else
2932 #endif
dadf55f2 2933 emit_readword_indexed_tlb(0,a,map,tl);
57871462 2934 }
535d208a 2935 if(jaddr)
2936 add_stub(LOADW_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
57871462 2937 }
535d208a 2938 else
2939 inline_readstub(LOADW_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2940 }
2941 if (opcode[i]==0x24) { // LBU
2942 if(!c||memtarget) {
2943 if(!dummy) {
57871462 2944 #ifdef HOST_IMM_ADDR32
2945 if(c)
2946 emit_movzbl_tlb((constmap[i][s]+offset)^3,map,tl);
2947 else
2948 #endif
2949 {
2950 //emit_xorimm(addr,3,tl);
2951 //gen_tlb_addr_r(tl,map);
2952 //emit_movzbl_indexed((int)rdram-0x80000000,tl,tl);
535d208a 2953 int x=0,a=tl;
2002a1db 2954#ifdef BIG_ENDIAN_MIPS
57871462 2955 if(!c) emit_xorimm(addr,3,tl);
2956 else x=((constmap[i][s]+offset)^3)-(constmap[i][s]+offset);
2002a1db 2957#else
535d208a 2958 if(!c) a=addr;
dadf55f2 2959#endif
2960#ifdef PCSX
2961 if(sp_in_mirror&&rs1[i]==29) a=HOST_TEMPREG;
2002a1db 2962#endif
535d208a 2963 emit_movzbl_indexed_tlb(x,a,map,tl);
57871462 2964 }
57871462 2965 }
535d208a 2966 if(jaddr)
2967 add_stub(LOADBU_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
57871462 2968 }
535d208a 2969 else
2970 inline_readstub(LOADBU_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2971 }
2972 if (opcode[i]==0x25) { // LHU
2973 if(!c||memtarget) {
2974 if(!dummy) {
57871462 2975 #ifdef HOST_IMM_ADDR32
2976 if(c)
2977 emit_movzwl_tlb((constmap[i][s]+offset)^2,map,tl);
2978 else
2979 #endif
2980 {
535d208a 2981 int x=0,a=tl;
2002a1db 2982#ifdef BIG_ENDIAN_MIPS
57871462 2983 if(!c) emit_xorimm(addr,2,tl);
2984 else x=((constmap[i][s]+offset)^2)-(constmap[i][s]+offset);
2002a1db 2985#else
535d208a 2986 if(!c) a=addr;
dadf55f2 2987#endif
2988#ifdef PCSX
2989 if(sp_in_mirror&&rs1[i]==29) a=HOST_TEMPREG;
2002a1db 2990#endif
57871462 2991 //#ifdef
2992 //emit_movzwl_indexed_tlb(x,tl,map,tl);
2993 //#else
2994 if(map>=0) {
535d208a 2995 gen_tlb_addr_r(a,map);
2996 emit_movzwl_indexed(x,a,tl);
2997 }else{
2998 #ifdef RAM_OFFSET
2999 emit_movzwl_indexed(x,a,tl);
3000 #else
3001 emit_movzwl_indexed((int)rdram-0x80000000+x,a,tl);
3002 #endif
3003 }
57871462 3004 }
3005 }
535d208a 3006 if(jaddr)
3007 add_stub(LOADHU_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
57871462 3008 }
535d208a 3009 else
3010 inline_readstub(LOADHU_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
3011 }
3012 if (opcode[i]==0x27) { // LWU
3013 assert(th>=0);
3014 if(!c||memtarget) {
3015 if(!dummy) {
dadf55f2 3016 int a=addr;
3017#ifdef PCSX
3018 if(sp_in_mirror&&rs1[i]==29) a=HOST_TEMPREG;
3019#endif
57871462 3020 //emit_readword_indexed((int)rdram-0x80000000,addr,tl);
3021 #ifdef HOST_IMM_ADDR32
3022 if(c)
3023 emit_readword_tlb(constmap[i][s]+offset,map,tl);
3024 else
3025 #endif
dadf55f2 3026 emit_readword_indexed_tlb(0,a,map,tl);
57871462 3027 }
535d208a 3028 if(jaddr)
3029 add_stub(LOADW_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
3030 }
3031 else {
3032 inline_readstub(LOADW_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
57871462 3033 }
535d208a 3034 emit_zeroreg(th);
3035 }
3036 if (opcode[i]==0x37) { // LD
3037 if(!c||memtarget) {
3038 if(!dummy) {
dadf55f2 3039 int a=addr;
3040#ifdef PCSX
3041 if(sp_in_mirror&&rs1[i]==29) a=HOST_TEMPREG;
3042#endif
57871462 3043 //gen_tlb_addr_r(tl,map);
3044 //if(th>=0) emit_readword_indexed((int)rdram-0x80000000,addr,th);
3045 //emit_readword_indexed((int)rdram-0x7FFFFFFC,addr,tl);
3046 #ifdef HOST_IMM_ADDR32
3047 if(c)
3048 emit_readdword_tlb(constmap[i][s]+offset,map,th,tl);
3049 else
3050 #endif
dadf55f2 3051 emit_readdword_indexed_tlb(0,a,map,th,tl);
57871462 3052 }
535d208a 3053 if(jaddr)
3054 add_stub(LOADD_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
57871462 3055 }
535d208a 3056 else
3057 inline_readstub(LOADD_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
57871462 3058 }
535d208a 3059 }
3060 //emit_storereg(rt1[i],tl); // DEBUG
57871462 3061 //if(opcode[i]==0x23)
3062 //if(opcode[i]==0x24)
3063 //if(opcode[i]==0x23||opcode[i]==0x24)
3064 /*if(opcode[i]==0x21||opcode[i]==0x23||opcode[i]==0x24)
3065 {
3066 //emit_pusha();
3067 save_regs(0x100f);
3068 emit_readword((int)&last_count,ECX);
3069 #ifdef __i386__
3070 if(get_reg(i_regs->regmap,CCREG)<0)
3071 emit_loadreg(CCREG,HOST_CCREG);
3072 emit_add(HOST_CCREG,ECX,HOST_CCREG);
3073 emit_addimm(HOST_CCREG,2*ccadj[i],HOST_CCREG);
3074 emit_writeword(HOST_CCREG,(int)&Count);
3075 #endif
3076 #ifdef __arm__
3077 if(get_reg(i_regs->regmap,CCREG)<0)
3078 emit_loadreg(CCREG,0);
3079 else
3080 emit_mov(HOST_CCREG,0);
3081 emit_add(0,ECX,0);
3082 emit_addimm(0,2*ccadj[i],0);
3083 emit_writeword(0,(int)&Count);
3084 #endif
3085 emit_call((int)memdebug);
3086 //emit_popa();
3087 restore_regs(0x100f);
3088 }/**/
3089}
3090
3091#ifndef loadlr_assemble
3092void loadlr_assemble(int i,struct regstat *i_regs)
3093{
3094 printf("Need loadlr_assemble for this architecture.\n");
3095 exit(1);
3096}
3097#endif
3098
3099void store_assemble(int i,struct regstat *i_regs)
3100{
3101 int s,th,tl,map=-1;
3102 int addr,temp;
3103 int offset;
3104 int jaddr=0,jaddr2,type;
666a299d 3105 int memtarget=0,c=0;
57871462 3106 int agr=AGEN1+(i&1);
3107 u_int hr,reglist=0;
3108 th=get_reg(i_regs->regmap,rs2[i]|64);
3109 tl=get_reg(i_regs->regmap,rs2[i]);
3110 s=get_reg(i_regs->regmap,rs1[i]);
3111 temp=get_reg(i_regs->regmap,agr);
3112 if(temp<0) temp=get_reg(i_regs->regmap,-1);
3113 offset=imm[i];
3114 if(s>=0) {
3115 c=(i_regs->wasconst>>s)&1;
af4ee1fe 3116 if(c) {
3117 memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
3118 if(using_tlb&&((signed int)(constmap[i][s]+offset))>=(signed int)0xC0000000) memtarget=1;
3119 }
57871462 3120 }
3121 assert(tl>=0);
3122 assert(temp>=0);
3123 for(hr=0;hr<HOST_REGS;hr++) {
3124 if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
3125 }
3126 if(i_regs->regmap[HOST_CCREG]==CCREG) reglist&=~(1<<HOST_CCREG);
3127 if(offset||s<0||c) addr=temp;
3128 else addr=s;
3129 if(!using_tlb) {
3130 if(!c) {
dadf55f2 3131 #ifdef PCSX
3132 if(sp_in_mirror&&rs1[i]==29) {
3133 emit_andimm(addr,~0x00e00000,HOST_TEMPREG);
3134 emit_cmpimm(HOST_TEMPREG,RAM_SIZE);
3135 }
3136 else
3137 #endif
57871462 3138 #ifdef R29_HACK
3139 // Strmnnrmn's speed hack
4cb76aa4 3140 if(rs1[i]!=29||start<0x80001000||start>=0x80000000+RAM_SIZE)
57871462 3141 #endif
4cb76aa4 3142 emit_cmpimm(addr,RAM_SIZE);
57871462 3143 #ifdef DESTRUCTIVE_SHIFT
3144 if(s==addr) emit_mov(s,temp);
3145 #endif
3146 #ifdef R29_HACK
dadf55f2 3147 memtarget=1;
4cb76aa4 3148 if(rs1[i]!=29||start<0x80001000||start>=0x80000000+RAM_SIZE)
57871462 3149 #endif
3150 {
3151 jaddr=(int)out;
3152 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
3153 // Hint to branch predictor that the branch is unlikely to be taken
3154 if(rs1[i]>=28)
3155 emit_jno_unlikely(0);
3156 else
3157 #endif
3158 emit_jno(0);
3159 }
3160 }
3161 }else{ // using tlb
3162 int x=0;
3163 if (opcode[i]==0x28) x=3; // SB
3164 if (opcode[i]==0x29) x=2; // SH
3165 map=get_reg(i_regs->regmap,TLREG);
3166 assert(map>=0);
3167 map=do_tlb_w(addr,temp,map,x,c,constmap[i][s]+offset);
3168 do_tlb_w_branch(map,c,constmap[i][s]+offset,&jaddr);
3169 }
3170
3171 if (opcode[i]==0x28) { // SB
3172 if(!c||memtarget) {
97a238a6 3173 int x=0,a=temp;
2002a1db 3174#ifdef BIG_ENDIAN_MIPS
57871462 3175 if(!c) emit_xorimm(addr,3,temp);
3176 else x=((constmap[i][s]+offset)^3)-(constmap[i][s]+offset);
2002a1db 3177#else
97a238a6 3178 if(!c) a=addr;
dadf55f2 3179#endif
3180#ifdef PCSX
3181 if(sp_in_mirror&&rs1[i]==29) a=HOST_TEMPREG;
2002a1db 3182#endif
57871462 3183 //gen_tlb_addr_w(temp,map);
3184 //emit_writebyte_indexed(tl,(int)rdram-0x80000000,temp);
97a238a6 3185 emit_writebyte_indexed_tlb(tl,x,a,map,a);
57871462 3186 }
3187 type=STOREB_STUB;
3188 }
3189 if (opcode[i]==0x29) { // SH
3190 if(!c||memtarget) {
97a238a6 3191 int x=0,a=temp;
2002a1db 3192#ifdef BIG_ENDIAN_MIPS
57871462 3193 if(!c) emit_xorimm(addr,2,temp);
3194 else x=((constmap[i][s]+offset)^2)-(constmap[i][s]+offset);
2002a1db 3195#else
97a238a6 3196 if(!c) a=addr;
dadf55f2 3197#endif
3198#ifdef PCSX
3199 if(sp_in_mirror&&rs1[i]==29) a=HOST_TEMPREG;
2002a1db 3200#endif
57871462 3201 //#ifdef
3202 //emit_writehword_indexed_tlb(tl,x,temp,map,temp);
3203 //#else
3204 if(map>=0) {
97a238a6 3205 gen_tlb_addr_w(a,map);
3206 emit_writehword_indexed(tl,x,a);
57871462 3207 }else
97a238a6 3208 emit_writehword_indexed(tl,(int)rdram-0x80000000+x,a);
57871462 3209 }
3210 type=STOREH_STUB;
3211 }
3212 if (opcode[i]==0x2B) { // SW
dadf55f2 3213 if(!c||memtarget) {
3214 int a=addr;
3215#ifdef PCSX
3216 if(sp_in_mirror&&rs1[i]==29) a=HOST_TEMPREG;
3217#endif
57871462 3218 //emit_writeword_indexed(tl,(int)rdram-0x80000000,addr);
dadf55f2 3219 emit_writeword_indexed_tlb(tl,0,a,map,temp);
3220 }
57871462 3221 type=STOREW_STUB;
3222 }
3223 if (opcode[i]==0x3F) { // SD
3224 if(!c||memtarget) {
dadf55f2 3225 int a=addr;
3226#ifdef PCSX
3227 if(sp_in_mirror&&rs1[i]==29) a=HOST_TEMPREG;
3228#endif
57871462 3229 if(rs2[i]) {
3230 assert(th>=0);
3231 //emit_writeword_indexed(th,(int)rdram-0x80000000,addr);
3232 //emit_writeword_indexed(tl,(int)rdram-0x7FFFFFFC,addr);
dadf55f2 3233 emit_writedword_indexed_tlb(th,tl,0,a,map,temp);
57871462 3234 }else{
3235 // Store zero
3236 //emit_writeword_indexed(tl,(int)rdram-0x80000000,temp);
3237 //emit_writeword_indexed(tl,(int)rdram-0x7FFFFFFC,temp);
dadf55f2 3238 emit_writedword_indexed_tlb(tl,tl,0,a,map,temp);
57871462 3239 }
3240 }
3241 type=STORED_STUB;
3242 }
57871462 3243 if(!using_tlb) {
3244 if(!c||memtarget) {
3245 #ifdef DESTRUCTIVE_SHIFT
3246 // The x86 shift operation is 'destructive'; it overwrites the
3247 // source register, so we need to make a copy first and use that.
3248 addr=temp;
3249 #endif
3250 #if defined(HOST_IMM8)
3251 int ir=get_reg(i_regs->regmap,INVCP);
3252 assert(ir>=0);
3253 emit_cmpmem_indexedsr12_reg(ir,addr,1);
3254 #else
3255 emit_cmpmem_indexedsr12_imm((int)invalid_code,addr,1);
3256 #endif
0bbd1454 3257 #if defined(HAVE_CONDITIONAL_CALL) && !defined(DESTRUCTIVE_SHIFT)
3258 emit_callne(invalidate_addr_reg[addr]);
3259 #else
57871462 3260 jaddr2=(int)out;
3261 emit_jne(0);
3262 add_stub(INVCODE_STUB,jaddr2,(int)out,reglist|(1<<HOST_CCREG),addr,0,0,0);
0bbd1454 3263 #endif
57871462 3264 }
3265 }
3eaa7048 3266 if(jaddr) {
3267 add_stub(type,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
3268 } else if(c&&!memtarget) {
3269 inline_writestub(type,i,constmap[i][s]+offset,i_regs->regmap,rs2[i],ccadj[i],reglist);
3270 }
57871462 3271 //if(opcode[i]==0x2B || opcode[i]==0x3F)
3272 //if(opcode[i]==0x2B || opcode[i]==0x28)
3273 //if(opcode[i]==0x2B || opcode[i]==0x29)
3274 //if(opcode[i]==0x2B)
3275 /*if(opcode[i]==0x2B || opcode[i]==0x28 || opcode[i]==0x29 || opcode[i]==0x3F)
3276 {
3277 //emit_pusha();
3278 save_regs(0x100f);
3279 emit_readword((int)&last_count,ECX);
3280 #ifdef __i386__
3281 if(get_reg(i_regs->regmap,CCREG)<0)
3282 emit_loadreg(CCREG,HOST_CCREG);
3283 emit_add(HOST_CCREG,ECX,HOST_CCREG);
3284 emit_addimm(HOST_CCREG,2*ccadj[i],HOST_CCREG);
3285 emit_writeword(HOST_CCREG,(int)&Count);
3286 #endif
3287 #ifdef __arm__
3288 if(get_reg(i_regs->regmap,CCREG)<0)
3289 emit_loadreg(CCREG,0);
3290 else
3291 emit_mov(HOST_CCREG,0);
3292 emit_add(0,ECX,0);
3293 emit_addimm(0,2*ccadj[i],0);
3294 emit_writeword(0,(int)&Count);
3295 #endif
3296 emit_call((int)memdebug);
3297 //emit_popa();
3298 restore_regs(0x100f);
3299 }/**/
3300}
3301
3302void storelr_assemble(int i,struct regstat *i_regs)
3303{
3304 int s,th,tl;
3305 int temp;
3306 int temp2;
3307 int offset;
3308 int jaddr=0,jaddr2;
3309 int case1,case2,case3;
3310 int done0,done1,done2;
af4ee1fe 3311 int memtarget=0,c=0;
fab5d06d 3312 int agr=AGEN1+(i&1);
57871462 3313 u_int hr,reglist=0;
3314 th=get_reg(i_regs->regmap,rs2[i]|64);
3315 tl=get_reg(i_regs->regmap,rs2[i]);
3316 s=get_reg(i_regs->regmap,rs1[i]);
fab5d06d 3317 temp=get_reg(i_regs->regmap,agr);
3318 if(temp<0) temp=get_reg(i_regs->regmap,-1);
57871462 3319 offset=imm[i];
3320 if(s>=0) {
3321 c=(i_regs->isconst>>s)&1;
af4ee1fe 3322 if(c) {
3323 memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
3324 if(using_tlb&&((signed int)(constmap[i][s]+offset))>=(signed int)0xC0000000) memtarget=1;
3325 }
57871462 3326 }
3327 assert(tl>=0);
3328 for(hr=0;hr<HOST_REGS;hr++) {
3329 if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
3330 }
535d208a 3331 assert(temp>=0);
3332 if(!using_tlb) {
3333 if(!c) {
3334 emit_cmpimm(s<0||offset?temp:s,RAM_SIZE);
3335 if(!offset&&s!=temp) emit_mov(s,temp);
3336 jaddr=(int)out;
3337 emit_jno(0);
3338 }
3339 else
3340 {
3341 if(!memtarget||!rs1[i]) {
57871462 3342 jaddr=(int)out;
3343 emit_jmp(0);
3344 }
57871462 3345 }
535d208a 3346 #ifdef RAM_OFFSET
3347 int map=get_reg(i_regs->regmap,ROREG);
3348 if(map<0) emit_loadreg(ROREG,map=HOST_TEMPREG);
3349 gen_tlb_addr_w(temp,map);
3350 #else
3351 if((u_int)rdram!=0x80000000)
3352 emit_addimm_no_flags((u_int)rdram-(u_int)0x80000000,temp);
3353 #endif
3354 }else{ // using tlb
3355 int map=get_reg(i_regs->regmap,TLREG);
3356 assert(map>=0);
3357 map=do_tlb_w(c||s<0||offset?temp:s,temp,map,0,c,constmap[i][s]+offset);
3358 if(!c&&!offset&&s>=0) emit_mov(s,temp);
3359 do_tlb_w_branch(map,c,constmap[i][s]+offset,&jaddr);
3360 if(!jaddr&&!memtarget) {
3361 jaddr=(int)out;
3362 emit_jmp(0);
57871462 3363 }
535d208a 3364 gen_tlb_addr_w(temp,map);
3365 }
3366
3367 if (opcode[i]==0x2C||opcode[i]==0x2D) { // SDL/SDR
3368 temp2=get_reg(i_regs->regmap,FTEMP);
3369 if(!rs2[i]) temp2=th=tl;
3370 }
57871462 3371
2002a1db 3372#ifndef BIG_ENDIAN_MIPS
3373 emit_xorimm(temp,3,temp);
3374#endif
535d208a 3375 emit_testimm(temp,2);
3376 case2=(int)out;
3377 emit_jne(0);
3378 emit_testimm(temp,1);
3379 case1=(int)out;
3380 emit_jne(0);
3381 // 0
3382 if (opcode[i]==0x2A) { // SWL
3383 emit_writeword_indexed(tl,0,temp);
3384 }
3385 if (opcode[i]==0x2E) { // SWR
3386 emit_writebyte_indexed(tl,3,temp);
3387 }
3388 if (opcode[i]==0x2C) { // SDL
3389 emit_writeword_indexed(th,0,temp);
3390 if(rs2[i]) emit_mov(tl,temp2);
3391 }
3392 if (opcode[i]==0x2D) { // SDR
3393 emit_writebyte_indexed(tl,3,temp);
3394 if(rs2[i]) emit_shldimm(th,tl,24,temp2);
3395 }
3396 done0=(int)out;
3397 emit_jmp(0);
3398 // 1
3399 set_jump_target(case1,(int)out);
3400 if (opcode[i]==0x2A) { // SWL
3401 // Write 3 msb into three least significant bytes
3402 if(rs2[i]) emit_rorimm(tl,8,tl);
3403 emit_writehword_indexed(tl,-1,temp);
3404 if(rs2[i]) emit_rorimm(tl,16,tl);
3405 emit_writebyte_indexed(tl,1,temp);
3406 if(rs2[i]) emit_rorimm(tl,8,tl);
3407 }
3408 if (opcode[i]==0x2E) { // SWR
3409 // Write two lsb into two most significant bytes
3410 emit_writehword_indexed(tl,1,temp);
3411 }
3412 if (opcode[i]==0x2C) { // SDL
3413 if(rs2[i]) emit_shrdimm(tl,th,8,temp2);
3414 // Write 3 msb into three least significant bytes
3415 if(rs2[i]) emit_rorimm(th,8,th);
3416 emit_writehword_indexed(th,-1,temp);
3417 if(rs2[i]) emit_rorimm(th,16,th);
3418 emit_writebyte_indexed(th,1,temp);
3419 if(rs2[i]) emit_rorimm(th,8,th);
3420 }
3421 if (opcode[i]==0x2D) { // SDR
3422 if(rs2[i]) emit_shldimm(th,tl,16,temp2);
3423 // Write two lsb into two most significant bytes
3424 emit_writehword_indexed(tl,1,temp);
3425 }
3426 done1=(int)out;
3427 emit_jmp(0);
3428 // 2
3429 set_jump_target(case2,(int)out);
3430 emit_testimm(temp,1);
3431 case3=(int)out;
3432 emit_jne(0);
3433 if (opcode[i]==0x2A) { // SWL
3434 // Write two msb into two least significant bytes
3435 if(rs2[i]) emit_rorimm(tl,16,tl);
3436 emit_writehword_indexed(tl,-2,temp);
3437 if(rs2[i]) emit_rorimm(tl,16,tl);
3438 }
3439 if (opcode[i]==0x2E) { // SWR
3440 // Write 3 lsb into three most significant bytes
3441 emit_writebyte_indexed(tl,-1,temp);
3442 if(rs2[i]) emit_rorimm(tl,8,tl);
3443 emit_writehword_indexed(tl,0,temp);
3444 if(rs2[i]) emit_rorimm(tl,24,tl);
3445 }
3446 if (opcode[i]==0x2C) { // SDL
3447 if(rs2[i]) emit_shrdimm(tl,th,16,temp2);
3448 // Write two msb into two least significant bytes
3449 if(rs2[i]) emit_rorimm(th,16,th);
3450 emit_writehword_indexed(th,-2,temp);
3451 if(rs2[i]) emit_rorimm(th,16,th);
3452 }
3453 if (opcode[i]==0x2D) { // SDR
3454 if(rs2[i]) emit_shldimm(th,tl,8,temp2);
3455 // Write 3 lsb into three most significant bytes
3456 emit_writebyte_indexed(tl,-1,temp);
3457 if(rs2[i]) emit_rorimm(tl,8,tl);
3458 emit_writehword_indexed(tl,0,temp);
3459 if(rs2[i]) emit_rorimm(tl,24,tl);
3460 }
3461 done2=(int)out;
3462 emit_jmp(0);
3463 // 3
3464 set_jump_target(case3,(int)out);
3465 if (opcode[i]==0x2A) { // SWL
3466 // Write msb into least significant byte
3467 if(rs2[i]) emit_rorimm(tl,24,tl);
3468 emit_writebyte_indexed(tl,-3,temp);
3469 if(rs2[i]) emit_rorimm(tl,8,tl);
3470 }
3471 if (opcode[i]==0x2E) { // SWR
3472 // Write entire word
3473 emit_writeword_indexed(tl,-3,temp);
3474 }
3475 if (opcode[i]==0x2C) { // SDL
3476 if(rs2[i]) emit_shrdimm(tl,th,24,temp2);
3477 // Write msb into least significant byte
3478 if(rs2[i]) emit_rorimm(th,24,th);
3479 emit_writebyte_indexed(th,-3,temp);
3480 if(rs2[i]) emit_rorimm(th,8,th);
3481 }
3482 if (opcode[i]==0x2D) { // SDR
3483 if(rs2[i]) emit_mov(th,temp2);
3484 // Write entire word
3485 emit_writeword_indexed(tl,-3,temp);
3486 }
3487 set_jump_target(done0,(int)out);
3488 set_jump_target(done1,(int)out);
3489 set_jump_target(done2,(int)out);
3490 if (opcode[i]==0x2C) { // SDL
3491 emit_testimm(temp,4);
57871462 3492 done0=(int)out;
57871462 3493 emit_jne(0);
535d208a 3494 emit_andimm(temp,~3,temp);
3495 emit_writeword_indexed(temp2,4,temp);
3496 set_jump_target(done0,(int)out);
3497 }
3498 if (opcode[i]==0x2D) { // SDR
3499 emit_testimm(temp,4);
3500 done0=(int)out;
3501 emit_jeq(0);
3502 emit_andimm(temp,~3,temp);
3503 emit_writeword_indexed(temp2,-4,temp);
57871462 3504 set_jump_target(done0,(int)out);
57871462 3505 }
535d208a 3506 if(!c||!memtarget)
3507 add_stub(STORELR_STUB,jaddr,(int)out,i,(int)i_regs,temp,ccadj[i],reglist);
57871462 3508 if(!using_tlb) {
535d208a 3509 #ifdef RAM_OFFSET
3510 int map=get_reg(i_regs->regmap,ROREG);
3511 if(map<0) map=HOST_TEMPREG;
3512 gen_orig_addr_w(temp,map);
3513 #else
57871462 3514 emit_addimm_no_flags((u_int)0x80000000-(u_int)rdram,temp);
535d208a 3515 #endif
57871462 3516 #if defined(HOST_IMM8)
3517 int ir=get_reg(i_regs->regmap,INVCP);
3518 assert(ir>=0);
3519 emit_cmpmem_indexedsr12_reg(ir,temp,1);
3520 #else
3521 emit_cmpmem_indexedsr12_imm((int)invalid_code,temp,1);
3522 #endif
535d208a 3523 #if defined(HAVE_CONDITIONAL_CALL) && !defined(DESTRUCTIVE_SHIFT)
3524 emit_callne(invalidate_addr_reg[temp]);
3525 #else
57871462 3526 jaddr2=(int)out;
3527 emit_jne(0);
3528 add_stub(INVCODE_STUB,jaddr2,(int)out,reglist|(1<<HOST_CCREG),temp,0,0,0);
535d208a 3529 #endif
57871462 3530 }
3531 /*
3532 emit_pusha();
3533 //save_regs(0x100f);
3534 emit_readword((int)&last_count,ECX);
3535 if(get_reg(i_regs->regmap,CCREG)<0)
3536 emit_loadreg(CCREG,HOST_CCREG);
3537 emit_add(HOST_CCREG,ECX,HOST_CCREG);
3538 emit_addimm(HOST_CCREG,2*ccadj[i],HOST_CCREG);
3539 emit_writeword(HOST_CCREG,(int)&Count);
3540 emit_call((int)memdebug);
3541 emit_popa();
3542 //restore_regs(0x100f);
3543 /**/
3544}
3545
3546void c1ls_assemble(int i,struct regstat *i_regs)
3547{
3d624f89 3548#ifndef DISABLE_COP1
57871462 3549 int s,th,tl;
3550 int temp,ar;
3551 int map=-1;
3552 int offset;
3553 int c=0;
3554 int jaddr,jaddr2=0,jaddr3,type;
3555 int agr=AGEN1+(i&1);
3556 u_int hr,reglist=0;
3557 th=get_reg(i_regs->regmap,FTEMP|64);
3558 tl=get_reg(i_regs->regmap,FTEMP);
3559 s=get_reg(i_regs->regmap,rs1[i]);
3560 temp=get_reg(i_regs->regmap,agr);
3561 if(temp<0) temp=get_reg(i_regs->regmap,-1);
3562 offset=imm[i];
3563 assert(tl>=0);
3564 assert(rs1[i]>0);
3565 assert(temp>=0);
3566 for(hr=0;hr<HOST_REGS;hr++) {
3567 if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
3568 }
3569 if(i_regs->regmap[HOST_CCREG]==CCREG) reglist&=~(1<<HOST_CCREG);
3570 if (opcode[i]==0x31||opcode[i]==0x35) // LWC1/LDC1
3571 {
3572 // Loads use a temporary register which we need to save
3573 reglist|=1<<temp;
3574 }
3575 if (opcode[i]==0x39||opcode[i]==0x3D) // SWC1/SDC1
3576 ar=temp;
3577 else // LWC1/LDC1
3578 ar=tl;
3579 //if(s<0) emit_loadreg(rs1[i],ar); //address_generation does this now
3580 //else c=(i_regs->wasconst>>s)&1;
3581 if(s>=0) c=(i_regs->wasconst>>s)&1;
3582 // Check cop1 unusable
3583 if(!cop1_usable) {
3584 signed char rs=get_reg(i_regs->regmap,CSREG);
3585 assert(rs>=0);
3586 emit_testimm(rs,0x20000000);
3587 jaddr=(int)out;
3588 emit_jeq(0);
3589 add_stub(FP_STUB,jaddr,(int)out,i,rs,(int)i_regs,is_delayslot,0);
3590 cop1_usable=1;
3591 }
3592 if (opcode[i]==0x39) { // SWC1 (get float address)
3593 emit_readword((int)&reg_cop1_simple[(source[i]>>16)&0x1f],tl);
3594 }
3595 if (opcode[i]==0x3D) { // SDC1 (get double address)
3596 emit_readword((int)&reg_cop1_double[(source[i]>>16)&0x1f],tl);
3597 }
3598 // Generate address + offset
3599 if(!using_tlb) {
3600 if(!c)
4cb76aa4 3601 emit_cmpimm(offset||c||s<0?ar:s,RAM_SIZE);
57871462 3602 }
3603 else
3604 {
3605 map=get_reg(i_regs->regmap,TLREG);
3606 assert(map>=0);
3607 if (opcode[i]==0x31||opcode[i]==0x35) { // LWC1/LDC1
3608 map=do_tlb_r(offset||c||s<0?ar:s,ar,map,0,-1,-1,c,constmap[i][s]+offset);
3609 }
3610 if (opcode[i]==0x39||opcode[i]==0x3D) { // SWC1/SDC1
3611 map=do_tlb_w(offset||c||s<0?ar:s,ar,map,0,c,constmap[i][s]+offset);
3612 }
3613 }
3614 if (opcode[i]==0x39) { // SWC1 (read float)
3615 emit_readword_indexed(0,tl,tl);
3616 }
3617 if (opcode[i]==0x3D) { // SDC1 (read double)
3618 emit_readword_indexed(4,tl,th);
3619 emit_readword_indexed(0,tl,tl);
3620 }
3621 if (opcode[i]==0x31) { // LWC1 (get target address)
3622 emit_readword((int)&reg_cop1_simple[(source[i]>>16)&0x1f],temp);
3623 }
3624 if (opcode[i]==0x35) { // LDC1 (get target address)
3625 emit_readword((int)&reg_cop1_double[(source[i]>>16)&0x1f],temp);
3626 }
3627 if(!using_tlb) {
3628 if(!c) {
3629 jaddr2=(int)out;
3630 emit_jno(0);
3631 }
4cb76aa4 3632 else if(((signed int)(constmap[i][s]+offset))>=(signed int)0x80000000+RAM_SIZE) {
57871462 3633 jaddr2=(int)out;
3634 emit_jmp(0); // inline_readstub/inline_writestub? Very rare case
3635 }
3636 #ifdef DESTRUCTIVE_SHIFT
3637 if (opcode[i]==0x39||opcode[i]==0x3D) { // SWC1/SDC1
3638 if(!offset&&!c&&s>=0) emit_mov(s,ar);
3639 }
3640 #endif
3641 }else{
3642 if (opcode[i]==0x31||opcode[i]==0x35) { // LWC1/LDC1
3643 do_tlb_r_branch(map,c,constmap[i][s]+offset,&jaddr2);
3644 }
3645 if (opcode[i]==0x39||opcode[i]==0x3D) { // SWC1/SDC1
3646 do_tlb_w_branch(map,c,constmap[i][s]+offset,&jaddr2);
3647 }
3648 }
3649 if (opcode[i]==0x31) { // LWC1
3650 //if(s>=0&&!c&&!offset) emit_mov(s,tl);
3651 //gen_tlb_addr_r(ar,map);
3652 //emit_readword_indexed((int)rdram-0x80000000,tl,tl);
3653 #ifdef HOST_IMM_ADDR32
3654 if(c) emit_readword_tlb(constmap[i][s]+offset,map,tl);
3655 else
3656 #endif
3657 emit_readword_indexed_tlb(0,offset||c||s<0?tl:s,map,tl);
3658 type=LOADW_STUB;
3659 }
3660 if (opcode[i]==0x35) { // LDC1
3661 assert(th>=0);
3662 //if(s>=0&&!c&&!offset) emit_mov(s,tl);
3663 //gen_tlb_addr_r(ar,map);
3664 //emit_readword_indexed((int)rdram-0x80000000,tl,th);
3665 //emit_readword_indexed((int)rdram-0x7FFFFFFC,tl,tl);
3666 #ifdef HOST_IMM_ADDR32
3667 if(c) emit_readdword_tlb(constmap[i][s]+offset,map,th,tl);
3668 else
3669 #endif
3670 emit_readdword_indexed_tlb(0,offset||c||s<0?tl:s,map,th,tl);
3671 type=LOADD_STUB;
3672 }
3673 if (opcode[i]==0x39) { // SWC1
3674 //emit_writeword_indexed(tl,(int)rdram-0x80000000,temp);
3675 emit_writeword_indexed_tlb(tl,0,offset||c||s<0?temp:s,map,temp);
3676 type=STOREW_STUB;
3677 }
3678 if (opcode[i]==0x3D) { // SDC1
3679 assert(th>=0);
3680 //emit_writeword_indexed(th,(int)rdram-0x80000000,temp);
3681 //emit_writeword_indexed(tl,(int)rdram-0x7FFFFFFC,temp);
3682 emit_writedword_indexed_tlb(th,tl,0,offset||c||s<0?temp:s,map,temp);
3683 type=STORED_STUB;
3684 }
3685 if(!using_tlb) {
3686 if (opcode[i]==0x39||opcode[i]==0x3D) { // SWC1/SDC1
3687 #ifndef DESTRUCTIVE_SHIFT
3688 temp=offset||c||s<0?ar:s;
3689 #endif
3690 #if defined(HOST_IMM8)
3691 int ir=get_reg(i_regs->regmap,INVCP);
3692 assert(ir>=0);
3693 emit_cmpmem_indexedsr12_reg(ir,temp,1);
3694 #else
3695 emit_cmpmem_indexedsr12_imm((int)invalid_code,temp,1);
3696 #endif
0bbd1454 3697 #if defined(HAVE_CONDITIONAL_CALL) && !defined(DESTRUCTIVE_SHIFT)
3698 emit_callne(invalidate_addr_reg[temp]);
3699 #else
57871462 3700 jaddr3=(int)out;
3701 emit_jne(0);
3702 add_stub(INVCODE_STUB,jaddr3,(int)out,reglist|(1<<HOST_CCREG),temp,0,0,0);
0bbd1454 3703 #endif
57871462 3704 }
3705 }
3706 if(jaddr2) add_stub(type,jaddr2,(int)out,i,offset||c||s<0?ar:s,(int)i_regs,ccadj[i],reglist);
3707 if (opcode[i]==0x31) { // LWC1 (write float)
3708 emit_writeword_indexed(tl,0,temp);
3709 }
3710 if (opcode[i]==0x35) { // LDC1 (write double)
3711 emit_writeword_indexed(th,4,temp);
3712 emit_writeword_indexed(tl,0,temp);
3713 }
3714 //if(opcode[i]==0x39)
3715 /*if(opcode[i]==0x39||opcode[i]==0x31)
3716 {
3717 emit_pusha();
3718 emit_readword((int)&last_count,ECX);
3719 if(get_reg(i_regs->regmap,CCREG)<0)
3720 emit_loadreg(CCREG,HOST_CCREG);
3721 emit_add(HOST_CCREG,ECX,HOST_CCREG);
3722 emit_addimm(HOST_CCREG,2*ccadj[i],HOST_CCREG);
3723 emit_writeword(HOST_CCREG,(int)&Count);
3724 emit_call((int)memdebug);
3725 emit_popa();
3726 }/**/
3d624f89 3727#else
3728 cop1_unusable(i, i_regs);
3729#endif
57871462 3730}
3731
b9b61529 3732void c2ls_assemble(int i,struct regstat *i_regs)
3733{
3734 int s,tl;
3735 int ar;
3736 int offset;
1fd1aceb 3737 int memtarget=0,c=0;
c2e3bd42 3738 int jaddr2=0,jaddr3,type;
b9b61529 3739 int agr=AGEN1+(i&1);
3740 u_int hr,reglist=0;
3741 u_int copr=(source[i]>>16)&0x1f;
3742 s=get_reg(i_regs->regmap,rs1[i]);
3743 tl=get_reg(i_regs->regmap,FTEMP);
3744 offset=imm[i];
3745 assert(rs1[i]>0);
3746 assert(tl>=0);
3747 assert(!using_tlb);
3748
3749 for(hr=0;hr<HOST_REGS;hr++) {
3750 if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
3751 }
3752 if(i_regs->regmap[HOST_CCREG]==CCREG)
3753 reglist&=~(1<<HOST_CCREG);
3754
3755 // get the address
3756 if (opcode[i]==0x3a) { // SWC2
3757 ar=get_reg(i_regs->regmap,agr);
3758 if(ar<0) ar=get_reg(i_regs->regmap,-1);
3759 reglist|=1<<ar;
3760 } else { // LWC2
3761 ar=tl;
3762 }
1fd1aceb 3763 if(s>=0) c=(i_regs->wasconst>>s)&1;
3764 memtarget=c&&(((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE);
b9b61529 3765 if (!offset&&!c&&s>=0) ar=s;
3766 assert(ar>=0);
3767
3768 if (opcode[i]==0x3a) { // SWC2
3769 cop2_get_dreg(copr,tl,HOST_TEMPREG);
1fd1aceb 3770 type=STOREW_STUB;
b9b61529 3771 }
1fd1aceb 3772 else
b9b61529 3773 type=LOADW_STUB;
1fd1aceb 3774
3775 if(c&&!memtarget) {
3776 jaddr2=(int)out;
3777 emit_jmp(0); // inline_readstub/inline_writestub?
b9b61529 3778 }
1fd1aceb 3779 else {
3780 if(!c) {
3781 emit_cmpimm(offset||c||s<0?ar:s,RAM_SIZE);
3782 jaddr2=(int)out;
3783 emit_jno(0);
3784 }
3785 if (opcode[i]==0x32) { // LWC2
3786 #ifdef HOST_IMM_ADDR32
3787 if(c) emit_readword_tlb(constmap[i][s]+offset,-1,tl);
3788 else
3789 #endif
3790 emit_readword_indexed(0,ar,tl);
3791 }
3792 if (opcode[i]==0x3a) { // SWC2
3793 #ifdef DESTRUCTIVE_SHIFT
3794 if(!offset&&!c&&s>=0) emit_mov(s,ar);
3795 #endif
3796 emit_writeword_indexed(tl,0,ar);
3797 }
b9b61529 3798 }
3799 if(jaddr2)
3800 add_stub(type,jaddr2,(int)out,i,ar,(int)i_regs,ccadj[i],reglist);
3801 if (opcode[i]==0x3a) { // SWC2
3802#if defined(HOST_IMM8)
3803 int ir=get_reg(i_regs->regmap,INVCP);
3804 assert(ir>=0);
3805 emit_cmpmem_indexedsr12_reg(ir,ar,1);
3806#else
3807 emit_cmpmem_indexedsr12_imm((int)invalid_code,ar,1);
3808#endif
0bbd1454 3809 #if defined(HAVE_CONDITIONAL_CALL) && !defined(DESTRUCTIVE_SHIFT)
3810 emit_callne(invalidate_addr_reg[ar]);
3811 #else
b9b61529 3812 jaddr3=(int)out;
3813 emit_jne(0);
3814 add_stub(INVCODE_STUB,jaddr3,(int)out,reglist|(1<<HOST_CCREG),ar,0,0,0);
0bbd1454 3815 #endif
b9b61529 3816 }
3817 if (opcode[i]==0x32) { // LWC2
3818 cop2_put_dreg(copr,tl,HOST_TEMPREG);
3819 }
3820}
3821
57871462 3822#ifndef multdiv_assemble
3823void multdiv_assemble(int i,struct regstat *i_regs)
3824{
3825 printf("Need multdiv_assemble for this architecture.\n");
3826 exit(1);
3827}
3828#endif
3829
3830void mov_assemble(int i,struct regstat *i_regs)
3831{
3832 //if(opcode2[i]==0x10||opcode2[i]==0x12) { // MFHI/MFLO
3833 //if(opcode2[i]==0x11||opcode2[i]==0x13) { // MTHI/MTLO
57871462 3834 if(rt1[i]) {
3835 signed char sh,sl,th,tl;
3836 th=get_reg(i_regs->regmap,rt1[i]|64);
3837 tl=get_reg(i_regs->regmap,rt1[i]);
3838 //assert(tl>=0);
3839 if(tl>=0) {
3840 sh=get_reg(i_regs->regmap,rs1[i]|64);
3841 sl=get_reg(i_regs->regmap,rs1[i]);
3842 if(sl>=0) emit_mov(sl,tl);
3843 else emit_loadreg(rs1[i],tl);
3844 if(th>=0) {
3845 if(sh>=0) emit_mov(sh,th);
3846 else emit_loadreg(rs1[i]|64,th);
3847 }
3848 }
3849 }
3850}
3851
3852#ifndef fconv_assemble
3853void fconv_assemble(int i,struct regstat *i_regs)
3854{
3855 printf("Need fconv_assemble for this architecture.\n");
3856 exit(1);
3857}
3858#endif
3859
3860#if 0
3861void float_assemble(int i,struct regstat *i_regs)
3862{
3863 printf("Need float_assemble for this architecture.\n");
3864 exit(1);
3865}
3866#endif
3867
3868void syscall_assemble(int i,struct regstat *i_regs)
3869{
3870 signed char ccreg=get_reg(i_regs->regmap,CCREG);
3871 assert(ccreg==HOST_CCREG);
3872 assert(!is_delayslot);
3873 emit_movimm(start+i*4,EAX); // Get PC
3874 emit_addimm(HOST_CCREG,CLOCK_DIVIDER*ccadj[i],HOST_CCREG); // CHECK: is this right? There should probably be an extra cycle...
7139f3c8 3875 emit_jmp((int)jump_syscall_hle); // XXX
3876}
3877
3878void hlecall_assemble(int i,struct regstat *i_regs)
3879{
3880 signed char ccreg=get_reg(i_regs->regmap,CCREG);
3881 assert(ccreg==HOST_CCREG);
3882 assert(!is_delayslot);
3883 emit_movimm(start+i*4+4,0); // Get PC
67ba0fb4 3884 emit_movimm((int)psxHLEt[source[i]&7],1);
7139f3c8 3885 emit_addimm(HOST_CCREG,CLOCK_DIVIDER*ccadj[i],HOST_CCREG); // XXX
67ba0fb4 3886 emit_jmp((int)jump_hlecall);
57871462 3887}
3888
1e973cb0 3889void intcall_assemble(int i,struct regstat *i_regs)
3890{
3891 signed char ccreg=get_reg(i_regs->regmap,CCREG);
3892 assert(ccreg==HOST_CCREG);
3893 assert(!is_delayslot);
3894 emit_movimm(start+i*4,0); // Get PC
3895 emit_addimm(HOST_CCREG,CLOCK_DIVIDER*ccadj[i],HOST_CCREG);
3896 emit_jmp((int)jump_intcall);
3897}
3898
57871462 3899void ds_assemble(int i,struct regstat *i_regs)
3900{
3901 is_delayslot=1;
3902 switch(itype[i]) {
3903 case ALU:
3904 alu_assemble(i,i_regs);break;
3905 case IMM16:
3906 imm16_assemble(i,i_regs);break;
3907 case SHIFT:
3908 shift_assemble(i,i_regs);break;
3909 case SHIFTIMM:
3910 shiftimm_assemble(i,i_regs);break;
3911 case LOAD:
3912 load_assemble(i,i_regs);break;
3913 case LOADLR:
3914 loadlr_assemble(i,i_regs);break;
3915 case STORE:
3916 store_assemble(i,i_regs);break;
3917 case STORELR:
3918 storelr_assemble(i,i_regs);break;
3919 case COP0:
3920 cop0_assemble(i,i_regs);break;
3921 case COP1:
3922 cop1_assemble(i,i_regs);break;
3923 case C1LS:
3924 c1ls_assemble(i,i_regs);break;
b9b61529 3925 case COP2:
3926 cop2_assemble(i,i_regs);break;
3927 case C2LS:
3928 c2ls_assemble(i,i_regs);break;
3929 case C2OP:
3930 c2op_assemble(i,i_regs);break;
57871462 3931 case FCONV:
3932 fconv_assemble(i,i_regs);break;
3933 case FLOAT:
3934 float_assemble(i,i_regs);break;
3935 case FCOMP:
3936 fcomp_assemble(i,i_regs);break;
3937 case MULTDIV:
3938 multdiv_assemble(i,i_regs);break;
3939 case MOV:
3940 mov_assemble(i,i_regs);break;
3941 case SYSCALL:
7139f3c8 3942 case HLECALL:
1e973cb0 3943 case INTCALL:
57871462 3944 case SPAN:
3945 case UJUMP:
3946 case RJUMP:
3947 case CJUMP:
3948 case SJUMP:
3949 case FJUMP:
3950 printf("Jump in the delay slot. This is probably a bug.\n");
3951 }
3952 is_delayslot=0;
3953}
3954
3955// Is the branch target a valid internal jump?
3956int internal_branch(uint64_t i_is32,int addr)
3957{
3958 if(addr&1) return 0; // Indirect (register) jump
3959 if(addr>=start && addr<start+slen*4-4)
3960 {
3961 int t=(addr-start)>>2;
3962 // Delay slots are not valid branch targets
3963 //if(t>0&&(itype[t-1]==RJUMP||itype[t-1]==UJUMP||itype[t-1]==CJUMP||itype[t-1]==SJUMP||itype[t-1]==FJUMP)) return 0;
3964 // 64 -> 32 bit transition requires a recompile
3965 /*if(is32[t]&~unneeded_reg_upper[t]&~i_is32)
3966 {
3967 if(requires_32bit[t]&~i_is32) printf("optimizable: no\n");
3968 else printf("optimizable: yes\n");
3969 }*/
3970 //if(is32[t]&~unneeded_reg_upper[t]&~i_is32) return 0;
a28c6ce8 3971#ifndef FORCE32
57871462 3972 if(requires_32bit[t]&~i_is32) return 0;
a28c6ce8 3973 else
3974#endif
3975 return 1;
57871462 3976 }
3977 return 0;
3978}
3979
3980#ifndef wb_invalidate
3981void wb_invalidate(signed char pre[],signed char entry[],uint64_t dirty,uint64_t is32,
3982 uint64_t u,uint64_t uu)
3983{
3984 int hr;
3985 for(hr=0;hr<HOST_REGS;hr++) {
3986 if(hr!=EXCLUDE_REG) {
3987 if(pre[hr]!=entry[hr]) {
3988 if(pre[hr]>=0) {
3989 if((dirty>>hr)&1) {
3990 if(get_reg(entry,pre[hr])<0) {
3991 if(pre[hr]<64) {
3992 if(!((u>>pre[hr])&1)) {
3993 emit_storereg(pre[hr],hr);
3994 if( ((is32>>pre[hr])&1) && !((uu>>pre[hr])&1) ) {
3995 emit_sarimm(hr,31,hr);
3996 emit_storereg(pre[hr]|64,hr);
3997 }
3998 }
3999 }else{
4000 if(!((uu>>(pre[hr]&63))&1) && !((is32>>(pre[hr]&63))&1)) {
4001 emit_storereg(pre[hr],hr);
4002 }
4003 }
4004 }
4005 }
4006 }
4007 }
4008 }
4009 }
4010 // Move from one register to another (no writeback)
4011 for(hr=0;hr<HOST_REGS;hr++) {
4012 if(hr!=EXCLUDE_REG) {
4013 if(pre[hr]!=entry[hr]) {
4014 if(pre[hr]>=0&&(pre[hr]&63)<TEMPREG) {
4015 int nr;
4016 if((nr=get_reg(entry,pre[hr]))>=0) {
4017 emit_mov(hr,nr);
4018 }
4019 }
4020 }
4021 }
4022 }
4023}
4024#endif
4025
4026// Load the specified registers
4027// This only loads the registers given as arguments because
4028// we don't want to load things that will be overwritten
4029void load_regs(signed char entry[],signed char regmap[],int is32,int rs1,int rs2)
4030{
4031 int hr;
4032 // Load 32-bit regs
4033 for(hr=0;hr<HOST_REGS;hr++) {
4034 if(hr!=EXCLUDE_REG&&regmap[hr]>=0) {
4035 if(entry[hr]!=regmap[hr]) {
4036 if(regmap[hr]==rs1||regmap[hr]==rs2)
4037 {
4038 if(regmap[hr]==0) {
4039 emit_zeroreg(hr);
4040 }
4041 else
4042 {
4043 emit_loadreg(regmap[hr],hr);
4044 }
4045 }
4046 }
4047 }
4048 }
4049 //Load 64-bit regs
4050 for(hr=0;hr<HOST_REGS;hr++) {
4051 if(hr!=EXCLUDE_REG&&regmap[hr]>=0) {
4052 if(entry[hr]!=regmap[hr]) {
4053 if(regmap[hr]-64==rs1||regmap[hr]-64==rs2)
4054 {
4055 assert(regmap[hr]!=64);
4056 if((is32>>(regmap[hr]&63))&1) {
4057 int lr=get_reg(regmap,regmap[hr]-64);
4058 if(lr>=0)
4059 emit_sarimm(lr,31,hr);
4060 else
4061 emit_loadreg(regmap[hr],hr);
4062 }
4063 else
4064 {
4065 emit_loadreg(regmap[hr],hr);
4066 }
4067 }
4068 }
4069 }
4070 }
4071}
4072
4073// Load registers prior to the start of a loop
4074// so that they are not loaded within the loop
4075static void loop_preload(signed char pre[],signed char entry[])
4076{
4077 int hr;
4078 for(hr=0;hr<HOST_REGS;hr++) {
4079 if(hr!=EXCLUDE_REG) {
4080 if(pre[hr]!=entry[hr]) {
4081 if(entry[hr]>=0) {
4082 if(get_reg(pre,entry[hr])<0) {
4083 assem_debug("loop preload:\n");
4084 //printf("loop preload: %d\n",hr);
4085 if(entry[hr]==0) {
4086 emit_zeroreg(hr);
4087 }
4088 else if(entry[hr]<TEMPREG)
4089 {
4090 emit_loadreg(entry[hr],hr);
4091 }
4092 else if(entry[hr]-64<TEMPREG)
4093 {
4094 emit_loadreg(entry[hr],hr);
4095 }
4096 }
4097 }
4098 }
4099 }
4100 }
4101}
4102
4103// Generate address for load/store instruction
b9b61529 4104// goes to AGEN for writes, FTEMP for LOADLR and cop1/2 loads
57871462 4105void address_generation(int i,struct regstat *i_regs,signed char entry[])
4106{
b9b61529 4107 if(itype[i]==LOAD||itype[i]==LOADLR||itype[i]==STORE||itype[i]==STORELR||itype[i]==C1LS||itype[i]==C2LS) {
5194fb95 4108 int ra=-1;
57871462 4109 int agr=AGEN1+(i&1);
4110 int mgr=MGEN1+(i&1);
4111 if(itype[i]==LOAD) {
4112 ra=get_reg(i_regs->regmap,rt1[i]);
535d208a 4113 if(ra<0) ra=get_reg(i_regs->regmap,-1);
4114 assert(ra>=0);
57871462 4115 }
4116 if(itype[i]==LOADLR) {
4117 ra=get_reg(i_regs->regmap,FTEMP);
4118 }
4119 if(itype[i]==STORE||itype[i]==STORELR) {
4120 ra=get_reg(i_regs->regmap,agr);
4121 if(ra<0) ra=get_reg(i_regs->regmap,-1);
4122 }
b9b61529 4123 if(itype[i]==C1LS||itype[i]==C2LS) {
4124 if ((opcode[i]&0x3b)==0x31||(opcode[i]&0x3b)==0x32) // LWC1/LDC1/LWC2/LDC2
57871462 4125 ra=get_reg(i_regs->regmap,FTEMP);
1fd1aceb 4126 else { // SWC1/SDC1/SWC2/SDC2
57871462 4127 ra=get_reg(i_regs->regmap,agr);
4128 if(ra<0) ra=get_reg(i_regs->regmap,-1);
4129 }
4130 }
4131 int rs=get_reg(i_regs->regmap,rs1[i]);
4132 int rm=get_reg(i_regs->regmap,TLREG);
4133 if(ra>=0) {
4134 int offset=imm[i];
4135 int c=(i_regs->wasconst>>rs)&1;
4136 if(rs1[i]==0) {
4137 // Using r0 as a base address
4138 /*if(rm>=0) {
4139 if(!entry||entry[rm]!=mgr) {
4140 generate_map_const(offset,rm);
4141 } // else did it in the previous cycle
4142 }*/
4143 if(!entry||entry[ra]!=agr) {
4144 if (opcode[i]==0x22||opcode[i]==0x26) {
4145 emit_movimm(offset&0xFFFFFFFC,ra); // LWL/LWR
4146 }else if (opcode[i]==0x1a||opcode[i]==0x1b) {
4147 emit_movimm(offset&0xFFFFFFF8,ra); // LDL/LDR
4148 }else{
4149 emit_movimm(offset,ra);
4150 }
4151 } // else did it in the previous cycle
4152 }
4153 else if(rs<0) {
4154 if(!entry||entry[ra]!=rs1[i])
4155 emit_loadreg(rs1[i],ra);
4156 //if(!entry||entry[ra]!=rs1[i])
4157 // printf("poor load scheduling!\n");
4158 }
4159 else if(c) {
4160 if(rm>=0) {
4161 if(!entry||entry[rm]!=mgr) {
b9b61529 4162 if(itype[i]==STORE||itype[i]==STORELR||(opcode[i]&0x3b)==0x39||(opcode[i]&0x3b)==0x3a) {
57871462 4163 // Stores to memory go thru the mapper to detect self-modifying
4164 // code, loads don't.
4165 if((unsigned int)(constmap[i][rs]+offset)>=0xC0000000 ||
4cb76aa4 4166 (unsigned int)(constmap[i][rs]+offset)<0x80000000+RAM_SIZE )
57871462 4167 generate_map_const(constmap[i][rs]+offset,rm);
4168 }else{
4169 if((signed int)(constmap[i][rs]+offset)>=(signed int)0xC0000000)
4170 generate_map_const(constmap[i][rs]+offset,rm);
4171 }
4172 }
4173 }
4174 if(rs1[i]!=rt1[i]||itype[i]!=LOAD) {
4175 if(!entry||entry[ra]!=agr) {
4176 if (opcode[i]==0x22||opcode[i]==0x26) {
4177 emit_movimm((constmap[i][rs]+offset)&0xFFFFFFFC,ra); // LWL/LWR
4178 }else if (opcode[i]==0x1a||opcode[i]==0x1b) {
4179 emit_movimm((constmap[i][rs]+offset)&0xFFFFFFF8,ra); // LDL/LDR
4180 }else{
4181 #ifdef HOST_IMM_ADDR32
b9b61529 4182 if((itype[i]!=LOAD&&(opcode[i]&0x3b)!=0x31&&(opcode[i]&0x3b)!=0x32) || // LWC1/LDC1/LWC2/LDC2
57871462 4183 (using_tlb&&((signed int)constmap[i][rs]+offset)>=(signed int)0xC0000000))
4184 #endif
4185 emit_movimm(constmap[i][rs]+offset,ra);
4186 }
4187 } // else did it in the previous cycle
4188 } // else load_consts already did it
4189 }
4190 if(offset&&!c&&rs1[i]) {
4191 if(rs>=0) {
4192 emit_addimm(rs,offset,ra);
4193 }else{
4194 emit_addimm(ra,offset,ra);
4195 }
4196 }
4197 }
4198 }
4199 // Preload constants for next instruction
b9b61529 4200 if(itype[i+1]==LOAD||itype[i+1]==LOADLR||itype[i+1]==STORE||itype[i+1]==STORELR||itype[i+1]==C1LS||itype[i+1]==C2LS) {
57871462 4201 int agr,ra;
4202 #ifndef HOST_IMM_ADDR32
4203 // Mapper entry
4204 agr=MGEN1+((i+1)&1);
4205 ra=get_reg(i_regs->regmap,agr);
4206 if(ra>=0) {
4207 int rs=get_reg(regs[i+1].regmap,rs1[i+1]);
4208 int offset=imm[i+1];
4209 int c=(regs[i+1].wasconst>>rs)&1;
4210 if(c) {
b9b61529 4211 if(itype[i+1]==STORE||itype[i+1]==STORELR
4212 ||(opcode[i+1]&0x3b)==0x39||(opcode[i+1]&0x3b)==0x3a) { // SWC1/SDC1, SWC2/SDC2
57871462 4213 // Stores to memory go thru the mapper to detect self-modifying
4214 // code, loads don't.
4215 if((unsigned int)(constmap[i+1][rs]+offset)>=0xC0000000 ||
4cb76aa4 4216 (unsigned int)(constmap[i+1][rs]+offset)<0x80000000+RAM_SIZE )
57871462 4217 generate_map_const(constmap[i+1][rs]+offset,ra);
4218 }else{
4219 if((signed int)(constmap[i+1][rs]+offset)>=(signed int)0xC0000000)
4220 generate_map_const(constmap[i+1][rs]+offset,ra);
4221 }
4222 }
4223 /*else if(rs1[i]==0) {
4224 generate_map_const(offset,ra);
4225 }*/
4226 }
4227 #endif
4228 // Actual address
4229 agr=AGEN1+((i+1)&1);
4230 ra=get_reg(i_regs->regmap,agr);
4231 if(ra>=0) {
4232 int rs=get_reg(regs[i+1].regmap,rs1[i+1]);
4233 int offset=imm[i+1];
4234 int c=(regs[i+1].wasconst>>rs)&1;
4235 if(c&&(rs1[i+1]!=rt1[i+1]||itype[i+1]!=LOAD)) {
4236 if (opcode[i+1]==0x22||opcode[i+1]==0x26) {
4237 emit_movimm((constmap[i+1][rs]+offset)&0xFFFFFFFC,ra); // LWL/LWR
4238 }else if (opcode[i+1]==0x1a||opcode[i+1]==0x1b) {
4239 emit_movimm((constmap[i+1][rs]+offset)&0xFFFFFFF8,ra); // LDL/LDR
4240 }else{
4241 #ifdef HOST_IMM_ADDR32
b9b61529 4242 if((itype[i+1]!=LOAD&&(opcode[i+1]&0x3b)!=0x31&&(opcode[i+1]&0x3b)!=0x32) || // LWC1/LDC1/LWC2/LDC2
57871462 4243 (using_tlb&&((signed int)constmap[i+1][rs]+offset)>=(signed int)0xC0000000))
4244 #endif
4245 emit_movimm(constmap[i+1][rs]+offset,ra);
4246 }
4247 }
4248 else if(rs1[i+1]==0) {
4249 // Using r0 as a base address
4250 if (opcode[i+1]==0x22||opcode[i+1]==0x26) {
4251 emit_movimm(offset&0xFFFFFFFC,ra); // LWL/LWR
4252 }else if (opcode[i+1]==0x1a||opcode[i+1]==0x1b) {
4253 emit_movimm(offset&0xFFFFFFF8,ra); // LDL/LDR
4254 }else{
4255 emit_movimm(offset,ra);
4256 }
4257 }
4258 }
4259 }
4260}
4261
4262int get_final_value(int hr, int i, int *value)
4263{
4264 int reg=regs[i].regmap[hr];
4265 while(i<slen-1) {
4266 if(regs[i+1].regmap[hr]!=reg) break;
4267 if(!((regs[i+1].isconst>>hr)&1)) break;
4268 if(bt[i+1]) break;
4269 i++;
4270 }
4271 if(i<slen-1) {
4272 if(itype[i]==UJUMP||itype[i]==RJUMP||itype[i]==CJUMP||itype[i]==SJUMP) {
4273 *value=constmap[i][hr];
4274 return 1;
4275 }
4276 if(!bt[i+1]) {
4277 if(itype[i+1]==UJUMP||itype[i+1]==RJUMP||itype[i+1]==CJUMP||itype[i+1]==SJUMP) {
4278 // Load in delay slot, out-of-order execution
4279 if(itype[i+2]==LOAD&&rs1[i+2]==reg&&rt1[i+2]==reg&&((regs[i+1].wasconst>>hr)&1))
4280 {
4281 #ifdef HOST_IMM_ADDR32
4282 if(!using_tlb||((signed int)constmap[i][hr]+imm[i+2])<(signed int)0xC0000000) return 0;
4283 #endif
4284 // Precompute load address
4285 *value=constmap[i][hr]+imm[i+2];
4286 return 1;
4287 }
4288 }
4289 if(itype[i+1]==LOAD&&rs1[i+1]==reg&&rt1[i+1]==reg)
4290 {
4291 #ifdef HOST_IMM_ADDR32
4292 if(!using_tlb||((signed int)constmap[i][hr]+imm[i+1])<(signed int)0xC0000000) return 0;
4293 #endif
4294 // Precompute load address
4295 *value=constmap[i][hr]+imm[i+1];
4296 //printf("c=%x imm=%x\n",(int)constmap[i][hr],imm[i+1]);
4297 return 1;
4298 }
4299 }
4300 }
4301 *value=constmap[i][hr];
4302 //printf("c=%x\n",(int)constmap[i][hr]);
4303 if(i==slen-1) return 1;
4304 if(reg<64) {
4305 return !((unneeded_reg[i+1]>>reg)&1);
4306 }else{
4307 return !((unneeded_reg_upper[i+1]>>reg)&1);
4308 }
4309}
4310
4311// Load registers with known constants
4312void load_consts(signed char pre[],signed char regmap[],int is32,int i)
4313{
4314 int hr;
4315 // Load 32-bit regs
4316 for(hr=0;hr<HOST_REGS;hr++) {
4317 if(hr!=EXCLUDE_REG&&regmap[hr]>=0) {
4318 //if(entry[hr]!=regmap[hr]) {
4319 if(i==0||!((regs[i-1].isconst>>hr)&1)||pre[hr]!=regmap[hr]||bt[i]) {
4320 if(((regs[i].isconst>>hr)&1)&&regmap[hr]<64&&regmap[hr]>0) {
4321 int value;
4322 if(get_final_value(hr,i,&value)) {
4323 if(value==0) {
4324 emit_zeroreg(hr);
4325 }
4326 else {
4327 emit_movimm(value,hr);
4328 }
4329 }
4330 }
4331 }
4332 }
4333 }
4334 // Load 64-bit regs
4335 for(hr=0;hr<HOST_REGS;hr++) {
4336 if(hr!=EXCLUDE_REG&&regmap[hr]>=0) {
4337 //if(entry[hr]!=regmap[hr]) {
4338 if(i==0||!((regs[i-1].isconst>>hr)&1)||pre[hr]!=regmap[hr]||bt[i]) {
4339 if(((regs[i].isconst>>hr)&1)&&regmap[hr]>64) {
4340 if((is32>>(regmap[hr]&63))&1) {
4341 int lr=get_reg(regmap,regmap[hr]-64);
4342 assert(lr>=0);
4343 emit_sarimm(lr,31,hr);
4344 }
4345 else
4346 {
4347 int value;
4348 if(get_final_value(hr,i,&value)) {
4349 if(value==0) {
4350 emit_zeroreg(hr);
4351 }
4352 else {
4353 emit_movimm(value,hr);
4354 }
4355 }
4356 }
4357 }
4358 }
4359 }
4360 }
4361}
4362void load_all_consts(signed char regmap[],int is32,u_int dirty,int i)
4363{
4364 int hr;
4365 // Load 32-bit regs
4366 for(hr=0;hr<HOST_REGS;hr++) {
4367 if(hr!=EXCLUDE_REG&&regmap[hr]>=0&&((dirty>>hr)&1)) {
4368 if(((regs[i].isconst>>hr)&1)&&regmap[hr]<64&&regmap[hr]>0) {
4369 int value=constmap[i][hr];
4370 if(value==0) {
4371 emit_zeroreg(hr);
4372 }
4373 else {
4374 emit_movimm(value,hr);
4375 }
4376 }
4377 }
4378 }
4379 // Load 64-bit regs
4380 for(hr=0;hr<HOST_REGS;hr++) {
4381 if(hr!=EXCLUDE_REG&&regmap[hr]>=0&&((dirty>>hr)&1)) {
4382 if(((regs[i].isconst>>hr)&1)&&regmap[hr]>64) {
4383 if((is32>>(regmap[hr]&63))&1) {
4384 int lr=get_reg(regmap,regmap[hr]-64);
4385 assert(lr>=0);
4386 emit_sarimm(lr,31,hr);
4387 }
4388 else
4389 {
4390 int value=constmap[i][hr];
4391 if(value==0) {
4392 emit_zeroreg(hr);
4393 }
4394 else {
4395 emit_movimm(value,hr);
4396 }
4397 }
4398 }
4399 }
4400 }
4401}
4402
4403// Write out all dirty registers (except cycle count)
4404void wb_dirtys(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty)
4405{
4406 int hr;
4407 for(hr=0;hr<HOST_REGS;hr++) {
4408 if(hr!=EXCLUDE_REG) {
4409 if(i_regmap[hr]>0) {
4410 if(i_regmap[hr]!=CCREG) {
4411 if((i_dirty>>hr)&1) {
4412 if(i_regmap[hr]<64) {
4413 emit_storereg(i_regmap[hr],hr);
24385cae 4414#ifndef FORCE32
57871462 4415 if( ((i_is32>>i_regmap[hr])&1) ) {
4416 #ifdef DESTRUCTIVE_WRITEBACK
4417 emit_sarimm(hr,31,hr);
4418 emit_storereg(i_regmap[hr]|64,hr);
4419 #else
4420 emit_sarimm(hr,31,HOST_TEMPREG);
4421 emit_storereg(i_regmap[hr]|64,HOST_TEMPREG);
4422 #endif
4423 }
24385cae 4424#endif
57871462 4425 }else{
4426 if( !((i_is32>>(i_regmap[hr]&63))&1) ) {
4427 emit_storereg(i_regmap[hr],hr);
4428 }
4429 }
4430 }
4431 }
4432 }
4433 }
4434 }
4435}
4436// Write out dirty registers that we need to reload (pair with load_needed_regs)
4437// This writes the registers not written by store_regs_bt
4438void wb_needed_dirtys(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr)
4439{
4440 int hr;
4441 int t=(addr-start)>>2;
4442 for(hr=0;hr<HOST_REGS;hr++) {
4443 if(hr!=EXCLUDE_REG) {
4444 if(i_regmap[hr]>0) {
4445 if(i_regmap[hr]!=CCREG) {
4446 if(i_regmap[hr]==regs[t].regmap_entry[hr] && ((regs[t].dirty>>hr)&1) && !(((i_is32&~regs[t].was32&~unneeded_reg_upper[t])>>(i_regmap[hr]&63))&1)) {
4447 if((i_dirty>>hr)&1) {
4448 if(i_regmap[hr]<64) {
4449 emit_storereg(i_regmap[hr],hr);
24385cae 4450#ifndef FORCE32
57871462 4451 if( ((i_is32>>i_regmap[hr])&1) ) {
4452 #ifdef DESTRUCTIVE_WRITEBACK
4453 emit_sarimm(hr,31,hr);
4454 emit_storereg(i_regmap[hr]|64,hr);
4455 #else
4456 emit_sarimm(hr,31,HOST_TEMPREG);
4457 emit_storereg(i_regmap[hr]|64,HOST_TEMPREG);
4458 #endif
4459 }
24385cae 4460#endif
57871462 4461 }else{
4462 if( !((i_is32>>(i_regmap[hr]&63))&1) ) {
4463 emit_storereg(i_regmap[hr],hr);
4464 }
4465 }
4466 }
4467 }
4468 }
4469 }
4470 }
4471 }
4472}
4473
4474// Load all registers (except cycle count)
4475void load_all_regs(signed char i_regmap[])
4476{
4477 int hr;
4478 for(hr=0;hr<HOST_REGS;hr++) {
4479 if(hr!=EXCLUDE_REG) {
4480 if(i_regmap[hr]==0) {
4481 emit_zeroreg(hr);
4482 }
4483 else
4484 if(i_regmap[hr]>0 && i_regmap[hr]!=CCREG)
4485 {
4486 emit_loadreg(i_regmap[hr],hr);
4487 }
4488 }
4489 }
4490}
4491
4492// Load all current registers also needed by next instruction
4493void load_needed_regs(signed char i_regmap[],signed char next_regmap[])
4494{
4495 int hr;
4496 for(hr=0;hr<HOST_REGS;hr++) {
4497 if(hr!=EXCLUDE_REG) {
4498 if(get_reg(next_regmap,i_regmap[hr])>=0) {
4499 if(i_regmap[hr]==0) {
4500 emit_zeroreg(hr);
4501 }
4502 else
4503 if(i_regmap[hr]>0 && i_regmap[hr]!=CCREG)
4504 {
4505 emit_loadreg(i_regmap[hr],hr);
4506 }
4507 }
4508 }
4509 }
4510}
4511
4512// Load all regs, storing cycle count if necessary
4513void load_regs_entry(int t)
4514{
4515 int hr;
4516 if(is_ds[t]) emit_addimm(HOST_CCREG,CLOCK_DIVIDER,HOST_CCREG);
4517 else if(ccadj[t]) emit_addimm(HOST_CCREG,-ccadj[t]*CLOCK_DIVIDER,HOST_CCREG);
4518 if(regs[t].regmap_entry[HOST_CCREG]!=CCREG) {
4519 emit_storereg(CCREG,HOST_CCREG);
4520 }
4521 // Load 32-bit regs
4522 for(hr=0;hr<HOST_REGS;hr++) {
4523 if(regs[t].regmap_entry[hr]>=0&&regs[t].regmap_entry[hr]<64) {
4524 if(regs[t].regmap_entry[hr]==0) {
4525 emit_zeroreg(hr);
4526 }
4527 else if(regs[t].regmap_entry[hr]!=CCREG)
4528 {
4529 emit_loadreg(regs[t].regmap_entry[hr],hr);
4530 }
4531 }
4532 }
4533 // Load 64-bit regs
4534 for(hr=0;hr<HOST_REGS;hr++) {
4535 if(regs[t].regmap_entry[hr]>=64) {
4536 assert(regs[t].regmap_entry[hr]!=64);
4537 if((regs[t].was32>>(regs[t].regmap_entry[hr]&63))&1) {
4538 int lr=get_reg(regs[t].regmap_entry,regs[t].regmap_entry[hr]-64);
4539 if(lr<0) {
4540 emit_loadreg(regs[t].regmap_entry[hr],hr);
4541 }
4542 else
4543 {
4544 emit_sarimm(lr,31,hr);
4545 }
4546 }
4547 else
4548 {
4549 emit_loadreg(regs[t].regmap_entry[hr],hr);
4550 }
4551 }
4552 }
4553}
4554
4555// Store dirty registers prior to branch
4556void store_regs_bt(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr)
4557{
4558 if(internal_branch(i_is32,addr))
4559 {
4560 int t=(addr-start)>>2;
4561 int hr;
4562 for(hr=0;hr<HOST_REGS;hr++) {
4563 if(hr!=EXCLUDE_REG) {
4564 if(i_regmap[hr]>0 && i_regmap[hr]!=CCREG) {
4565 if(i_regmap[hr]!=regs[t].regmap_entry[hr] || !((regs[t].dirty>>hr)&1) || (((i_is32&~regs[t].was32&~unneeded_reg_upper[t])>>(i_regmap[hr]&63))&1)) {
4566 if((i_dirty>>hr)&1) {
4567 if(i_regmap[hr]<64) {
4568 if(!((unneeded_reg[t]>>i_regmap[hr])&1)) {
4569 emit_storereg(i_regmap[hr],hr);
4570 if( ((i_is32>>i_regmap[hr])&1) && !((unneeded_reg_upper[t]>>i_regmap[hr])&1) ) {
4571 #ifdef DESTRUCTIVE_WRITEBACK
4572 emit_sarimm(hr,31,hr);
4573 emit_storereg(i_regmap[hr]|64,hr);
4574 #else
4575 emit_sarimm(hr,31,HOST_TEMPREG);
4576 emit_storereg(i_regmap[hr]|64,HOST_TEMPREG);
4577 #endif
4578 }
4579 }
4580 }else{
4581 if( !((i_is32>>(i_regmap[hr]&63))&1) && !((unneeded_reg_upper[t]>>(i_regmap[hr]&63))&1) ) {
4582 emit_storereg(i_regmap[hr],hr);
4583 }
4584 }
4585 }
4586 }
4587 }
4588 }
4589 }
4590 }
4591 else
4592 {
4593 // Branch out of this block, write out all dirty regs
4594 wb_dirtys(i_regmap,i_is32,i_dirty);
4595 }
4596}
4597
4598// Load all needed registers for branch target
4599void load_regs_bt(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr)
4600{
4601 //if(addr>=start && addr<(start+slen*4))
4602 if(internal_branch(i_is32,addr))
4603 {
4604 int t=(addr-start)>>2;
4605 int hr;
4606 // Store the cycle count before loading something else
4607 if(i_regmap[HOST_CCREG]!=CCREG) {
4608 assert(i_regmap[HOST_CCREG]==-1);
4609 }
4610 if(regs[t].regmap_entry[HOST_CCREG]!=CCREG) {
4611 emit_storereg(CCREG,HOST_CCREG);
4612 }
4613 // Load 32-bit regs
4614 for(hr=0;hr<HOST_REGS;hr++) {
4615 if(hr!=EXCLUDE_REG&&regs[t].regmap_entry[hr]>=0&&regs[t].regmap_entry[hr]<64) {
4616 #ifdef DESTRUCTIVE_WRITEBACK
4617 if(i_regmap[hr]!=regs[t].regmap_entry[hr] || ( !((regs[t].dirty>>hr)&1) && ((i_dirty>>hr)&1) && (((i_is32&~unneeded_reg_upper[t])>>i_regmap[hr])&1) ) || (((i_is32&~regs[t].was32&~unneeded_reg_upper[t])>>(i_regmap[hr]&63))&1)) {
4618 #else
4619 if(i_regmap[hr]!=regs[t].regmap_entry[hr] ) {
4620 #endif
4621 if(regs[t].regmap_entry[hr]==0) {
4622 emit_zeroreg(hr);
4623 }
4624 else if(regs[t].regmap_entry[hr]!=CCREG)
4625 {
4626 emit_loadreg(regs[t].regmap_entry[hr],hr);
4627 }
4628 }
4629 }
4630 }
4631 //Load 64-bit regs
4632 for(hr=0;hr<HOST_REGS;hr++) {
4633 if(hr!=EXCLUDE_REG&&regs[t].regmap_entry[hr]>=64) {
4634 if(i_regmap[hr]!=regs[t].regmap_entry[hr]) {
4635 assert(regs[t].regmap_entry[hr]!=64);
4636 if((i_is32>>(regs[t].regmap_entry[hr]&63))&1) {
4637 int lr=get_reg(regs[t].regmap_entry,regs[t].regmap_entry[hr]-64);
4638 if(lr<0) {
4639 emit_loadreg(regs[t].regmap_entry[hr],hr);
4640 }
4641 else
4642 {
4643 emit_sarimm(lr,31,hr);
4644 }
4645 }
4646 else
4647 {
4648 emit_loadreg(regs[t].regmap_entry[hr],hr);
4649 }
4650 }
4651 else if((i_is32>>(regs[t].regmap_entry[hr]&63))&1) {
4652 int lr=get_reg(regs[t].regmap_entry,regs[t].regmap_entry[hr]-64);
4653 assert(lr>=0);
4654 emit_sarimm(lr,31,hr);
4655 }
4656 }
4657 }
4658 }
4659}
4660
4661int match_bt(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr)
4662{
4663 if(addr>=start && addr<start+slen*4-4)
4664 {
4665 int t=(addr-start)>>2;
4666 int hr;
4667 if(regs[t].regmap_entry[HOST_CCREG]!=CCREG) return 0;
4668 for(hr=0;hr<HOST_REGS;hr++)
4669 {
4670 if(hr!=EXCLUDE_REG)
4671 {
4672 if(i_regmap[hr]!=regs[t].regmap_entry[hr])
4673 {
4674 if(regs[t].regmap_entry[hr]!=-1)
4675 {
4676 return 0;
4677 }
4678 else
4679 if((i_dirty>>hr)&1)
4680 {
4681 if(i_regmap[hr]<64)
4682 {
4683 if(!((unneeded_reg[t]>>i_regmap[hr])&1))
4684 return 0;
4685 }
4686 else
4687 {
4688 if(!((unneeded_reg_upper[t]>>(i_regmap[hr]&63))&1))
4689 return 0;
4690 }
4691 }
4692 }
4693 else // Same register but is it 32-bit or dirty?
4694 if(i_regmap[hr]>=0)
4695 {
4696 if(!((regs[t].dirty>>hr)&1))
4697 {
4698 if((i_dirty>>hr)&1)
4699 {
4700 if(!((unneeded_reg[t]>>i_regmap[hr])&1))
4701 {
4702 //printf("%x: dirty no match\n",addr);
4703 return 0;
4704 }
4705 }
4706 }
4707 if((((regs[t].was32^i_is32)&~unneeded_reg_upper[t])>>(i_regmap[hr]&63))&1)
4708 {
4709 //printf("%x: is32 no match\n",addr);
4710 return 0;
4711 }
4712 }
4713 }
4714 }
4715 //if(is32[t]&~unneeded_reg_upper[t]&~i_is32) return 0;
a28c6ce8 4716#ifndef FORCE32
57871462 4717 if(requires_32bit[t]&~i_is32) return 0;
a28c6ce8 4718#endif
57871462 4719 // Delay slots are not valid branch targets
4720 //if(t>0&&(itype[t-1]==RJUMP||itype[t-1]==UJUMP||itype[t-1]==CJUMP||itype[t-1]==SJUMP||itype[t-1]==FJUMP)) return 0;
4721 // Delay slots require additional processing, so do not match
4722 if(is_ds[t]) return 0;
4723 }
4724 else
4725 {
4726 int hr;
4727 for(hr=0;hr<HOST_REGS;hr++)
4728 {
4729 if(hr!=EXCLUDE_REG)
4730 {
4731 if(i_regmap[hr]>=0)
4732 {
4733 if(hr!=HOST_CCREG||i_regmap[hr]!=CCREG)
4734 {
4735 if((i_dirty>>hr)&1)
4736 {
4737 return 0;
4738 }
4739 }
4740 }
4741 }
4742 }
4743 }
4744 return 1;
4745}
4746
4747// Used when a branch jumps into the delay slot of another branch
4748void ds_assemble_entry(int i)
4749{
4750 int t=(ba[i]-start)>>2;
4751 if(!instr_addr[t]) instr_addr[t]=(u_int)out;
4752 assem_debug("Assemble delay slot at %x\n",ba[i]);
4753 assem_debug("<->\n");
4754 if(regs[t].regmap_entry[HOST_CCREG]==CCREG&&regs[t].regmap[HOST_CCREG]!=CCREG)
4755 wb_register(CCREG,regs[t].regmap_entry,regs[t].wasdirty,regs[t].was32);
4756 load_regs(regs[t].regmap_entry,regs[t].regmap,regs[t].was32,rs1[t],rs2[t]);
4757 address_generation(t,&regs[t],regs[t].regmap_entry);
b9b61529 4758 if(itype[t]==STORE||itype[t]==STORELR||(opcode[t]&0x3b)==0x39||(opcode[t]&0x3b)==0x3a)
57871462 4759 load_regs(regs[t].regmap_entry,regs[t].regmap,regs[t].was32,INVCP,INVCP);
4760 cop1_usable=0;
4761 is_delayslot=0;
4762 switch(itype[t]) {
4763 case ALU:
4764 alu_assemble(t,&regs[t]);break;
4765 case IMM16:
4766 imm16_assemble(t,&regs[t]);break;
4767 case SHIFT:
4768 shift_assemble(t,&regs[t]);break;
4769 case SHIFTIMM:
4770 shiftimm_assemble(t,&regs[t]);break;
4771 case LOAD:
4772 load_assemble(t,&regs[t]);break;
4773 case LOADLR:
4774 loadlr_assemble(t,&regs[t]);break;
4775 case STORE:
4776 store_assemble(t,&regs[t]);break;
4777 case STORELR:
4778 storelr_assemble(t,&regs[t]);break;
4779 case COP0:
4780 cop0_assemble(t,&regs[t]);break;
4781 case COP1:
4782 cop1_assemble(t,&regs[t]);break;
4783 case C1LS:
4784 c1ls_assemble(t,&regs[t]);break;
b9b61529 4785 case COP2:
4786 cop2_assemble(t,&regs[t]);break;
4787 case C2LS:
4788 c2ls_assemble(t,&regs[t]);break;
4789 case C2OP:
4790 c2op_assemble(t,&regs[t]);break;
57871462 4791 case FCONV:
4792 fconv_assemble(t,&regs[t]);break;
4793 case FLOAT:
4794 float_assemble(t,&regs[t]);break;
4795 case FCOMP:
4796 fcomp_assemble(t,&regs[t]);break;
4797 case MULTDIV:
4798 multdiv_assemble(t,&regs[t]);break;
4799 case MOV:
4800 mov_assemble(t,&regs[t]);break;
4801 case SYSCALL:
7139f3c8 4802 case HLECALL:
1e973cb0 4803 case INTCALL:
57871462 4804 case SPAN:
4805 case UJUMP:
4806 case RJUMP:
4807 case CJUMP:
4808 case SJUMP:
4809 case FJUMP:
4810 printf("Jump in the delay slot. This is probably a bug.\n");
4811 }
4812 store_regs_bt(regs[t].regmap,regs[t].is32,regs[t].dirty,ba[i]+4);
4813 load_regs_bt(regs[t].regmap,regs[t].is32,regs[t].dirty,ba[i]+4);
4814 if(internal_branch(regs[t].is32,ba[i]+4))
4815 assem_debug("branch: internal\n");
4816 else
4817 assem_debug("branch: external\n");
4818 assert(internal_branch(regs[t].is32,ba[i]+4));
4819 add_to_linker((int)out,ba[i]+4,internal_branch(regs[t].is32,ba[i]+4));
4820 emit_jmp(0);
4821}
4822
4823void do_cc(int i,signed char i_regmap[],int *adj,int addr,int taken,int invert)
4824{
4825 int count;
4826 int jaddr;
4827 int idle=0;
4828 if(itype[i]==RJUMP)
4829 {
4830 *adj=0;
4831 }
4832 //if(ba[i]>=start && ba[i]<(start+slen*4))
4833 if(internal_branch(branch_regs[i].is32,ba[i]))
4834 {
4835 int t=(ba[i]-start)>>2;
4836 if(is_ds[t]) *adj=-1; // Branch into delay slot adds an extra cycle
4837 else *adj=ccadj[t];
4838 }
4839 else
4840 {
4841 *adj=0;
4842 }
4843 count=ccadj[i];
4844 if(taken==TAKEN && i==(ba[i]-start)>>2 && source[i+1]==0) {
4845 // Idle loop
4846 if(count&1) emit_addimm_and_set_flags(2*(count+2),HOST_CCREG);
4847 idle=(int)out;
4848 //emit_subfrommem(&idlecount,HOST_CCREG); // Count idle cycles
4849 emit_andimm(HOST_CCREG,3,HOST_CCREG);
4850 jaddr=(int)out;
4851 emit_jmp(0);
4852 }
4853 else if(*adj==0||invert) {
4854 emit_addimm_and_set_flags(CLOCK_DIVIDER*(count+2),HOST_CCREG);
4855 jaddr=(int)out;
4856 emit_jns(0);
4857 }
4858 else
4859 {
eeb1feeb 4860 emit_cmpimm(HOST_CCREG,-CLOCK_DIVIDER*(count+2));
57871462 4861 jaddr=(int)out;
4862 emit_jns(0);
4863 }
4864 add_stub(CC_STUB,jaddr,idle?idle:(int)out,(*adj==0||invert||idle)?0:(count+2),i,addr,taken,0);
4865}
4866
4867void do_ccstub(int n)
4868{
4869 literal_pool(256);
4870 assem_debug("do_ccstub %x\n",start+stubs[n][4]*4);
4871 set_jump_target(stubs[n][1],(int)out);
4872 int i=stubs[n][4];
4873 if(stubs[n][6]==NULLDS) {
4874 // Delay slot instruction is nullified ("likely" branch)
4875 wb_dirtys(regs[i].regmap,regs[i].is32,regs[i].dirty);
4876 }
4877 else if(stubs[n][6]!=TAKEN) {
4878 wb_dirtys(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty);
4879 }
4880 else {
4881 if(internal_branch(branch_regs[i].is32,ba[i]))
4882 wb_needed_dirtys(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
4883 }
4884 if(stubs[n][5]!=-1)
4885 {
4886 // Save PC as return address
4887 emit_movimm(stubs[n][5],EAX);
4888 emit_writeword(EAX,(int)&pcaddr);
4889 }
4890 else
4891 {
4892 // Return address depends on which way the branch goes
4893 if(itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
4894 {
4895 int s1l=get_reg(branch_regs[i].regmap,rs1[i]);
4896 int s1h=get_reg(branch_regs[i].regmap,rs1[i]|64);
4897 int s2l=get_reg(branch_regs[i].regmap,rs2[i]);
4898 int s2h=get_reg(branch_regs[i].regmap,rs2[i]|64);
4899 if(rs1[i]==0)
4900 {
4901 s1l=s2l;s1h=s2h;
4902 s2l=s2h=-1;
4903 }
4904 else if(rs2[i]==0)
4905 {
4906 s2l=s2h=-1;
4907 }
4908 if((branch_regs[i].is32>>rs1[i])&(branch_regs[i].is32>>rs2[i])&1) {
4909 s1h=s2h=-1;
4910 }
4911 assert(s1l>=0);
4912 #ifdef DESTRUCTIVE_WRITEBACK
4913 if(rs1[i]) {
4914 if((branch_regs[i].dirty>>s1l)&(branch_regs[i].is32>>rs1[i])&1)
4915 emit_loadreg(rs1[i],s1l);
4916 }
4917 else {
4918 if((branch_regs[i].dirty>>s1l)&(branch_regs[i].is32>>rs2[i])&1)
4919 emit_loadreg(rs2[i],s1l);
4920 }
4921 if(s2l>=0)
4922 if((branch_regs[i].dirty>>s2l)&(branch_regs[i].is32>>rs2[i])&1)
4923 emit_loadreg(rs2[i],s2l);
4924 #endif
4925 int hr=0;
5194fb95 4926 int addr=-1,alt=-1,ntaddr=-1;
57871462 4927 while(hr<HOST_REGS)
4928 {
4929 if(hr!=EXCLUDE_REG && hr!=HOST_CCREG &&
4930 (branch_regs[i].regmap[hr]&63)!=rs1[i] &&
4931 (branch_regs[i].regmap[hr]&63)!=rs2[i] )
4932 {
4933 addr=hr++;break;
4934 }
4935 hr++;
4936 }
4937 while(hr<HOST_REGS)
4938 {
4939 if(hr!=EXCLUDE_REG && hr!=HOST_CCREG &&
4940 (branch_regs[i].regmap[hr]&63)!=rs1[i] &&
4941 (branch_regs[i].regmap[hr]&63)!=rs2[i] )
4942 {
4943 alt=hr++;break;
4944 }
4945 hr++;
4946 }
4947 if((opcode[i]&0x2E)==6) // BLEZ/BGTZ needs another register
4948 {
4949 while(hr<HOST_REGS)
4950 {
4951 if(hr!=EXCLUDE_REG && hr!=HOST_CCREG &&
4952 (branch_regs[i].regmap[hr]&63)!=rs1[i] &&
4953 (branch_regs[i].regmap[hr]&63)!=rs2[i] )
4954 {
4955 ntaddr=hr;break;
4956 }
4957 hr++;
4958 }
4959 assert(hr<HOST_REGS);
4960 }
4961 if((opcode[i]&0x2f)==4) // BEQ
4962 {
4963 #ifdef HAVE_CMOV_IMM
4964 if(s1h<0) {
4965 if(s2l>=0) emit_cmp(s1l,s2l);
4966 else emit_test(s1l,s1l);
4967 emit_cmov2imm_e_ne_compact(ba[i],start+i*4+8,addr);
4968 }
4969 else
4970 #endif
4971 {
4972 emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
4973 if(s1h>=0) {
4974 if(s2h>=0) emit_cmp(s1h,s2h);
4975 else emit_test(s1h,s1h);
4976 emit_cmovne_reg(alt,addr);
4977 }
4978 if(s2l>=0) emit_cmp(s1l,s2l);
4979 else emit_test(s1l,s1l);
4980 emit_cmovne_reg(alt,addr);
4981 }
4982 }
4983 if((opcode[i]&0x2f)==5) // BNE
4984 {
4985 #ifdef HAVE_CMOV_IMM
4986 if(s1h<0) {
4987 if(s2l>=0) emit_cmp(s1l,s2l);
4988 else emit_test(s1l,s1l);
4989 emit_cmov2imm_e_ne_compact(start+i*4+8,ba[i],addr);
4990 }
4991 else
4992 #endif
4993 {
4994 emit_mov2imm_compact(start+i*4+8,addr,ba[i],alt);
4995 if(s1h>=0) {
4996 if(s2h>=0) emit_cmp(s1h,s2h);
4997 else emit_test(s1h,s1h);
4998 emit_cmovne_reg(alt,addr);
4999 }
5000 if(s2l>=0) emit_cmp(s1l,s2l);
5001 else emit_test(s1l,s1l);
5002 emit_cmovne_reg(alt,addr);
5003 }
5004 }
5005 if((opcode[i]&0x2f)==6) // BLEZ
5006 {
5007 //emit_movimm(ba[i],alt);
5008 //emit_movimm(start+i*4+8,addr);
5009 emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
5010 emit_cmpimm(s1l,1);
5011 if(s1h>=0) emit_mov(addr,ntaddr);
5012 emit_cmovl_reg(alt,addr);
5013 if(s1h>=0) {
5014 emit_test(s1h,s1h);
5015 emit_cmovne_reg(ntaddr,addr);
5016 emit_cmovs_reg(alt,addr);
5017 }
5018 }
5019 if((opcode[i]&0x2f)==7) // BGTZ
5020 {
5021 //emit_movimm(ba[i],addr);
5022 //emit_movimm(start+i*4+8,ntaddr);
5023 emit_mov2imm_compact(ba[i],addr,start+i*4+8,ntaddr);
5024 emit_cmpimm(s1l,1);
5025 if(s1h>=0) emit_mov(addr,alt);
5026 emit_cmovl_reg(ntaddr,addr);
5027 if(s1h>=0) {
5028 emit_test(s1h,s1h);
5029 emit_cmovne_reg(alt,addr);
5030 emit_cmovs_reg(ntaddr,addr);
5031 }
5032 }
5033 if((opcode[i]==1)&&(opcode2[i]&0x2D)==0) // BLTZ
5034 {
5035 //emit_movimm(ba[i],alt);
5036 //emit_movimm(start+i*4+8,addr);
5037 emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
5038 if(s1h>=0) emit_test(s1h,s1h);
5039 else emit_test(s1l,s1l);
5040 emit_cmovs_reg(alt,addr);
5041 }
5042 if((opcode[i]==1)&&(opcode2[i]&0x2D)==1) // BGEZ
5043 {
5044 //emit_movimm(ba[i],addr);
5045 //emit_movimm(start+i*4+8,alt);
5046 emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
5047 if(s1h>=0) emit_test(s1h,s1h);
5048 else emit_test(s1l,s1l);
5049 emit_cmovs_reg(alt,addr);
5050 }
5051 if(opcode[i]==0x11 && opcode2[i]==0x08 ) {
5052 if(source[i]&0x10000) // BC1T
5053 {
5054 //emit_movimm(ba[i],alt);
5055 //emit_movimm(start+i*4+8,addr);
5056 emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
5057 emit_testimm(s1l,0x800000);
5058 emit_cmovne_reg(alt,addr);
5059 }
5060 else // BC1F
5061 {
5062 //emit_movimm(ba[i],addr);
5063 //emit_movimm(start+i*4+8,alt);
5064 emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
5065 emit_testimm(s1l,0x800000);
5066 emit_cmovne_reg(alt,addr);
5067 }
5068 }
5069 emit_writeword(addr,(int)&pcaddr);
5070 }
5071 else
5072 if(itype[i]==RJUMP)
5073 {
5074 int r=get_reg(branch_regs[i].regmap,rs1[i]);
5075 if(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1]) {
5076 r=get_reg(branch_regs[i].regmap,RTEMP);
5077 }
5078 emit_writeword(r,(int)&pcaddr);
5079 }
5080 else {printf("Unknown branch type in do_ccstub\n");exit(1);}
5081 }
5082 // Update cycle count
5083 assert(branch_regs[i].regmap[HOST_CCREG]==CCREG||branch_regs[i].regmap[HOST_CCREG]==-1);
5084 if(stubs[n][3]) emit_addimm(HOST_CCREG,CLOCK_DIVIDER*stubs[n][3],HOST_CCREG);
5085 emit_call((int)cc_interrupt);
5086 if(stubs[n][3]) emit_addimm(HOST_CCREG,-CLOCK_DIVIDER*stubs[n][3],HOST_CCREG);
5087 if(stubs[n][6]==TAKEN) {
5088 if(internal_branch(branch_regs[i].is32,ba[i]))
5089 load_needed_regs(branch_regs[i].regmap,regs[(ba[i]-start)>>2].regmap_entry);
5090 else if(itype[i]==RJUMP) {
5091 if(get_reg(branch_regs[i].regmap,RTEMP)>=0)
5092 emit_readword((int)&pcaddr,get_reg(branch_regs[i].regmap,RTEMP));
5093 else
5094 emit_loadreg(rs1[i],get_reg(branch_regs[i].regmap,rs1[i]));
5095 }
5096 }else if(stubs[n][6]==NOTTAKEN) {
5097 if(i<slen-2) load_needed_regs(branch_regs[i].regmap,regmap_pre[i+2]);
5098 else load_all_regs(branch_regs[i].regmap);
5099 }else if(stubs[n][6]==NULLDS) {
5100 // Delay slot instruction is nullified ("likely" branch)
5101 if(i<slen-2) load_needed_regs(regs[i].regmap,regmap_pre[i+2]);
5102 else load_all_regs(regs[i].regmap);
5103 }else{
5104 load_all_regs(branch_regs[i].regmap);
5105 }
5106 emit_jmp(stubs[n][2]); // return address
5107
5108 /* This works but uses a lot of memory...
5109 emit_readword((int)&last_count,ECX);
5110 emit_add(HOST_CCREG,ECX,EAX);
5111 emit_writeword(EAX,(int)&Count);
5112 emit_call((int)gen_interupt);
5113 emit_readword((int)&Count,HOST_CCREG);
5114 emit_readword((int)&next_interupt,EAX);
5115 emit_readword((int)&pending_exception,EBX);
5116 emit_writeword(EAX,(int)&last_count);
5117 emit_sub(HOST_CCREG,EAX,HOST_CCREG);
5118 emit_test(EBX,EBX);
5119 int jne_instr=(int)out;
5120 emit_jne(0);
5121 if(stubs[n][3]) emit_addimm(HOST_CCREG,-2*stubs[n][3],HOST_CCREG);
5122 load_all_regs(branch_regs[i].regmap);
5123 emit_jmp(stubs[n][2]); // return address
5124 set_jump_target(jne_instr,(int)out);
5125 emit_readword((int)&pcaddr,EAX);
5126 // Call get_addr_ht instead of doing the hash table here.
5127 // This code is executed infrequently and takes up a lot of space
5128 // so smaller is better.
5129 emit_storereg(CCREG,HOST_CCREG);
5130 emit_pushreg(EAX);
5131 emit_call((int)get_addr_ht);
5132 emit_loadreg(CCREG,HOST_CCREG);
5133 emit_addimm(ESP,4,ESP);
5134 emit_jmpreg(EAX);*/
5135}
5136
5137add_to_linker(int addr,int target,int ext)
5138{
5139 link_addr[linkcount][0]=addr;
5140 link_addr[linkcount][1]=target;
5141 link_addr[linkcount][2]=ext;
5142 linkcount++;
5143}
5144
5145void ujump_assemble(int i,struct regstat *i_regs)
5146{
5147 signed char *i_regmap=i_regs->regmap;
5148 if(i==(ba[i]-start)>>2) assem_debug("idle loop\n");
5149 address_generation(i+1,i_regs,regs[i].regmap_entry);
5150 #ifdef REG_PREFETCH
5151 int temp=get_reg(branch_regs[i].regmap,PTEMP);
5152 if(rt1[i]==31&&temp>=0)
5153 {
5154 int return_address=start+i*4+8;
5155 if(get_reg(branch_regs[i].regmap,31)>0)
5156 if(i_regmap[temp]==PTEMP) emit_movimm((int)hash_table[((return_address>>16)^return_address)&0xFFFF],temp);
5157 }
5158 #endif
57871462 5159 if(rt1[i]==31) {
5160 int rt;
5161 unsigned int return_address;
57871462 5162 rt=get_reg(branch_regs[i].regmap,31);
5163 assem_debug("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5164 //assert(rt>=0);
5165 return_address=start+i*4+8;
5166 if(rt>=0) {
5167 #ifdef USE_MINI_HT
4ef8f67d 5168 if(internal_branch(branch_regs[i].is32,return_address)&&rt1[i+1]!=31) {
5169 int temp=-1; // note: must be ds-safe
57871462 5170 #ifdef HOST_TEMPREG
4ef8f67d 5171 temp=HOST_TEMPREG;
57871462 5172 #endif
5173 if(temp>=0) do_miniht_insert(return_address,rt,temp);
5174 else emit_movimm(return_address,rt);
5175 }
5176 else
5177 #endif
5178 {
5179 #ifdef REG_PREFETCH
5180 if(temp>=0)
5181 {
5182 if(i_regmap[temp]!=PTEMP) emit_movimm((int)hash_table[((return_address>>16)^return_address)&0xFFFF],temp);
5183 }
5184 #endif
5185 emit_movimm(return_address,rt); // PC into link register
5186 #ifdef IMM_PREFETCH
5187 emit_prefetch(hash_table[((return_address>>16)^return_address)&0xFFFF]);
5188 #endif
5189 }
5190 }
5191 }
4ef8f67d 5192 ds_assemble(i+1,i_regs);
5193 uint64_t bc_unneeded=branch_regs[i].u;
5194 uint64_t bc_unneeded_upper=branch_regs[i].uu;
5195 bc_unneeded|=1|(1LL<<rt1[i]);
5196 bc_unneeded_upper|=1|(1LL<<rt1[i]);
5197 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5198 bc_unneeded,bc_unneeded_upper);
5199 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
57871462 5200 int cc,adj;
5201 cc=get_reg(branch_regs[i].regmap,CCREG);
5202 assert(cc==HOST_CCREG);
5203 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5204 #ifdef REG_PREFETCH
5205 if(rt1[i]==31&&temp>=0) emit_prefetchreg(temp);
5206 #endif
5207 do_cc(i,branch_regs[i].regmap,&adj,ba[i],TAKEN,0);
5208 if(adj) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc);
5209 load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5210 if(internal_branch(branch_regs[i].is32,ba[i]))
5211 assem_debug("branch: internal\n");
5212 else
5213 assem_debug("branch: external\n");
5214 if(internal_branch(branch_regs[i].is32,ba[i])&&is_ds[(ba[i]-start)>>2]) {
5215 ds_assemble_entry(i);
5216 }
5217 else {
5218 add_to_linker((int)out,ba[i],internal_branch(branch_regs[i].is32,ba[i]));
5219 emit_jmp(0);
5220 }
5221}
5222
5223void rjump_assemble(int i,struct regstat *i_regs)
5224{
5225 signed char *i_regmap=i_regs->regmap;
5226 int temp;
5227 int rs,cc,adj;
5228 rs=get_reg(branch_regs[i].regmap,rs1[i]);
5229 assert(rs>=0);
5230 if(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1]) {
5231 // Delay slot abuse, make a copy of the branch address register
5232 temp=get_reg(branch_regs[i].regmap,RTEMP);
5233 assert(temp>=0);
5234 assert(regs[i].regmap[temp]==RTEMP);
5235 emit_mov(rs,temp);
5236 rs=temp;
5237 }
5238 address_generation(i+1,i_regs,regs[i].regmap_entry);
5239 #ifdef REG_PREFETCH
5240 if(rt1[i]==31)
5241 {
5242 if((temp=get_reg(branch_regs[i].regmap,PTEMP))>=0) {
5243 int return_address=start+i*4+8;
5244 if(i_regmap[temp]==PTEMP) emit_movimm((int)hash_table[((return_address>>16)^return_address)&0xFFFF],temp);
5245 }
5246 }
5247 #endif
5248 #ifdef USE_MINI_HT
5249 if(rs1[i]==31) {
5250 int rh=get_reg(regs[i].regmap,RHASH);
5251 if(rh>=0) do_preload_rhash(rh);
5252 }
5253 #endif
5254 ds_assemble(i+1,i_regs);
5255 uint64_t bc_unneeded=branch_regs[i].u;
5256 uint64_t bc_unneeded_upper=branch_regs[i].uu;
5257 bc_unneeded|=1|(1LL<<rt1[i]);
5258 bc_unneeded_upper|=1|(1LL<<rt1[i]);
5259 bc_unneeded&=~(1LL<<rs1[i]);
5260 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5261 bc_unneeded,bc_unneeded_upper);
5262 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i],CCREG);
5067f341 5263 if(rt1[i]!=0) {
57871462 5264 int rt,return_address;
5067f341 5265 assert(rt1[i+1]!=rt1[i]);
5266 assert(rt2[i+1]!=rt1[i]);
5267 rt=get_reg(branch_regs[i].regmap,rt1[i]);
57871462 5268 assem_debug("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5269 assert(rt>=0);
5270 return_address=start+i*4+8;
5271 #ifdef REG_PREFETCH
5272 if(temp>=0)
5273 {
5274 if(i_regmap[temp]!=PTEMP) emit_movimm((int)hash_table[((return_address>>16)^return_address)&0xFFFF],temp);
5275 }
5276 #endif
5277 emit_movimm(return_address,rt); // PC into link register
5278 #ifdef IMM_PREFETCH
5279 emit_prefetch(hash_table[((return_address>>16)^return_address)&0xFFFF]);
5280 #endif
5281 }
5282 cc=get_reg(branch_regs[i].regmap,CCREG);
5283 assert(cc==HOST_CCREG);
5284 #ifdef USE_MINI_HT
5285 int rh=get_reg(branch_regs[i].regmap,RHASH);
5286 int ht=get_reg(branch_regs[i].regmap,RHTBL);
5287 if(rs1[i]==31) {
5288 if(regs[i].regmap[rh]!=RHASH) do_preload_rhash(rh);
5289 do_preload_rhtbl(ht);
5290 do_rhash(rs,rh);
5291 }
5292 #endif
5293 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,-1);
5294 #ifdef DESTRUCTIVE_WRITEBACK
5295 if((branch_regs[i].dirty>>rs)&(branch_regs[i].is32>>rs1[i])&1) {
5296 if(rs1[i]!=rt1[i+1]&&rs1[i]!=rt2[i+1]) {
5297 emit_loadreg(rs1[i],rs);
5298 }
5299 }
5300 #endif
5301 #ifdef REG_PREFETCH
5302 if(rt1[i]==31&&temp>=0) emit_prefetchreg(temp);
5303 #endif
5304 #ifdef USE_MINI_HT
5305 if(rs1[i]==31) {
5306 do_miniht_load(ht,rh);
5307 }
5308 #endif
5309 //do_cc(i,branch_regs[i].regmap,&adj,-1,TAKEN);
5310 //if(adj) emit_addimm(cc,2*(ccadj[i]+2-adj),cc); // ??? - Shouldn't happen
5311 //assert(adj==0);
5312 emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),HOST_CCREG);
5313 add_stub(CC_STUB,(int)out,jump_vaddr_reg[rs],0,i,-1,TAKEN,0);
5314 emit_jns(0);
5315 //load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,-1);
5316 #ifdef USE_MINI_HT
5317 if(rs1[i]==31) {
5318 do_miniht_jump(rs,rh,ht);
5319 }
5320 else
5321 #endif
5322 {
5323 //if(rs!=EAX) emit_mov(rs,EAX);
5324 //emit_jmp((int)jump_vaddr_eax);
5325 emit_jmp(jump_vaddr_reg[rs]);
5326 }
5327 /* Check hash table
5328 temp=!rs;
5329 emit_mov(rs,temp);
5330 emit_shrimm(rs,16,rs);
5331 emit_xor(temp,rs,rs);
5332 emit_movzwl_reg(rs,rs);
5333 emit_shlimm(rs,4,rs);
5334 emit_cmpmem_indexed((int)hash_table,rs,temp);
5335 emit_jne((int)out+14);
5336 emit_readword_indexed((int)hash_table+4,rs,rs);
5337 emit_jmpreg(rs);
5338 emit_cmpmem_indexed((int)hash_table+8,rs,temp);
5339 emit_addimm_no_flags(8,rs);
5340 emit_jeq((int)out-17);
5341 // No hit on hash table, call compiler
5342 emit_pushreg(temp);
5343//DEBUG >
5344#ifdef DEBUG_CYCLE_COUNT
5345 emit_readword((int)&last_count,ECX);
5346 emit_add(HOST_CCREG,ECX,HOST_CCREG);
5347 emit_readword((int)&next_interupt,ECX);
5348 emit_writeword(HOST_CCREG,(int)&Count);
5349 emit_sub(HOST_CCREG,ECX,HOST_CCREG);
5350 emit_writeword(ECX,(int)&last_count);
5351#endif
5352//DEBUG <
5353 emit_storereg(CCREG,HOST_CCREG);
5354 emit_call((int)get_addr);
5355 emit_loadreg(CCREG,HOST_CCREG);
5356 emit_addimm(ESP,4,ESP);
5357 emit_jmpreg(EAX);*/
5358 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5359 if(rt1[i]!=31&&i<slen-2&&(((u_int)out)&7)) emit_mov(13,13);
5360 #endif
5361}
5362
5363void cjump_assemble(int i,struct regstat *i_regs)
5364{
5365 signed char *i_regmap=i_regs->regmap;
5366 int cc;
5367 int match;
5368 match=match_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5369 assem_debug("match=%d\n",match);
5370 int s1h,s1l,s2h,s2l;
5371 int prev_cop1_usable=cop1_usable;
5372 int unconditional=0,nop=0;
5373 int only32=0;
57871462 5374 int invert=0;
5375 int internal=internal_branch(branch_regs[i].is32,ba[i]);
5376 if(i==(ba[i]-start)>>2) assem_debug("idle loop\n");
57871462 5377 if(!match) invert=1;
5378 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5379 if(i>(ba[i]-start)>>2) invert=1;
5380 #endif
e1190b87 5381
5382 if(ooo[i]) {
57871462 5383 s1l=get_reg(branch_regs[i].regmap,rs1[i]);
5384 s1h=get_reg(branch_regs[i].regmap,rs1[i]|64);
5385 s2l=get_reg(branch_regs[i].regmap,rs2[i]);
5386 s2h=get_reg(branch_regs[i].regmap,rs2[i]|64);
5387 }
5388 else {
5389 s1l=get_reg(i_regmap,rs1[i]);
5390 s1h=get_reg(i_regmap,rs1[i]|64);
5391 s2l=get_reg(i_regmap,rs2[i]);
5392 s2h=get_reg(i_regmap,rs2[i]|64);
5393 }
5394 if(rs1[i]==0&&rs2[i]==0)
5395 {
5396 if(opcode[i]&1) nop=1;
5397 else unconditional=1;
5398 //assert(opcode[i]!=5);
5399 //assert(opcode[i]!=7);
5400 //assert(opcode[i]!=0x15);
5401 //assert(opcode[i]!=0x17);
5402 }
5403 else if(rs1[i]==0)
5404 {
5405 s1l=s2l;s1h=s2h;
5406 s2l=s2h=-1;
5407 only32=(regs[i].was32>>rs2[i])&1;
5408 }
5409 else if(rs2[i]==0)
5410 {
5411 s2l=s2h=-1;
5412 only32=(regs[i].was32>>rs1[i])&1;
5413 }
5414 else {
5415 only32=(regs[i].was32>>rs1[i])&(regs[i].was32>>rs2[i])&1;
5416 }
5417
e1190b87 5418 if(ooo[i]) {
57871462 5419 // Out of order execution (delay slot first)
5420 //printf("OOOE\n");
5421 address_generation(i+1,i_regs,regs[i].regmap_entry);
5422 ds_assemble(i+1,i_regs);
5423 int adj;
5424 uint64_t bc_unneeded=branch_regs[i].u;
5425 uint64_t bc_unneeded_upper=branch_regs[i].uu;
5426 bc_unneeded&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
5427 bc_unneeded_upper&=~((1LL<<us1[i])|(1LL<<us2[i]));
5428 bc_unneeded|=1;
5429 bc_unneeded_upper|=1;
5430 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5431 bc_unneeded,bc_unneeded_upper);
5432 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i],rs2[i]);
5433 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
5434 cc=get_reg(branch_regs[i].regmap,CCREG);
5435 assert(cc==HOST_CCREG);
5436 if(unconditional)
5437 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5438 //do_cc(i,branch_regs[i].regmap,&adj,unconditional?ba[i]:-1,unconditional);
5439 //assem_debug("cycle count (adj)\n");
5440 if(unconditional) {
5441 do_cc(i,branch_regs[i].regmap,&adj,ba[i],TAKEN,0);
5442 if(i!=(ba[i]-start)>>2 || source[i+1]!=0) {
5443 if(adj) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc);
5444 load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5445 if(internal)
5446 assem_debug("branch: internal\n");
5447 else
5448 assem_debug("branch: external\n");
5449 if(internal&&is_ds[(ba[i]-start)>>2]) {
5450 ds_assemble_entry(i);
5451 }
5452 else {
5453 add_to_linker((int)out,ba[i],internal);
5454 emit_jmp(0);
5455 }
5456 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5457 if(((u_int)out)&7) emit_addnop(0);
5458 #endif
5459 }
5460 }
5461 else if(nop) {
5462 emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),cc);
5463 int jaddr=(int)out;
5464 emit_jns(0);
5465 add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,NOTTAKEN,0);
5466 }
5467 else {
5468 int taken=0,nottaken=0,nottaken1=0;
5469 do_cc(i,branch_regs[i].regmap,&adj,-1,0,invert);
5470 if(adj&&!invert) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc);
5471 if(!only32)
5472 {
5473 assert(s1h>=0);
5474 if(opcode[i]==4) // BEQ
5475 {
5476 if(s2h>=0) emit_cmp(s1h,s2h);
5477 else emit_test(s1h,s1h);
5478 nottaken1=(int)out;
5479 emit_jne(1);
5480 }
5481 if(opcode[i]==5) // BNE
5482 {
5483 if(s2h>=0) emit_cmp(s1h,s2h);
5484 else emit_test(s1h,s1h);
5485 if(invert) taken=(int)out;
5486 else add_to_linker((int)out,ba[i],internal);
5487 emit_jne(0);
5488 }
5489 if(opcode[i]==6) // BLEZ
5490 {
5491 emit_test(s1h,s1h);
5492 if(invert) taken=(int)out;
5493 else add_to_linker((int)out,ba[i],internal);
5494 emit_js(0);
5495 nottaken1=(int)out;
5496 emit_jne(1);
5497 }
5498 if(opcode[i]==7) // BGTZ
5499 {
5500 emit_test(s1h,s1h);
5501 nottaken1=(int)out;
5502 emit_js(1);
5503 if(invert) taken=(int)out;
5504 else add_to_linker((int)out,ba[i],internal);
5505 emit_jne(0);
5506 }
5507 } // if(!only32)
5508
5509 //printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5510 assert(s1l>=0);
5511 if(opcode[i]==4) // BEQ
5512 {
5513 if(s2l>=0) emit_cmp(s1l,s2l);
5514 else emit_test(s1l,s1l);
5515 if(invert){
5516 nottaken=(int)out;
5517 emit_jne(1);
5518 }else{
5519 add_to_linker((int)out,ba[i],internal);
5520 emit_jeq(0);
5521 }
5522 }
5523 if(opcode[i]==5) // BNE
5524 {
5525 if(s2l>=0) emit_cmp(s1l,s2l);
5526 else emit_test(s1l,s1l);
5527 if(invert){
5528 nottaken=(int)out;
5529 emit_jeq(1);
5530 }else{
5531 add_to_linker((int)out,ba[i],internal);
5532 emit_jne(0);
5533 }
5534 }
5535 if(opcode[i]==6) // BLEZ
5536 {
5537 emit_cmpimm(s1l,1);
5538 if(invert){
5539 nottaken=(int)out;
5540 emit_jge(1);
5541 }else{
5542 add_to_linker((int)out,ba[i],internal);
5543 emit_jl(0);
5544 }
5545 }
5546 if(opcode[i]==7) // BGTZ
5547 {
5548 emit_cmpimm(s1l,1);
5549 if(invert){
5550 nottaken=(int)out;
5551 emit_jl(1);
5552 }else{
5553 add_to_linker((int)out,ba[i],internal);
5554 emit_jge(0);
5555 }
5556 }
5557 if(invert) {
5558 if(taken) set_jump_target(taken,(int)out);
5559 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5560 if(match&&(!internal||!is_ds[(ba[i]-start)>>2])) {
5561 if(adj) {
5562 emit_addimm(cc,-CLOCK_DIVIDER*adj,cc);
5563 add_to_linker((int)out,ba[i],internal);
5564 }else{
5565 emit_addnop(13);
5566 add_to_linker((int)out,ba[i],internal*2);
5567 }
5568 emit_jmp(0);
5569 }else
5570 #endif
5571 {
5572 if(adj) emit_addimm(cc,-CLOCK_DIVIDER*adj,cc);
5573 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5574 load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5575 if(internal)
5576 assem_debug("branch: internal\n");
5577 else
5578 assem_debug("branch: external\n");
5579 if(internal&&is_ds[(ba[i]-start)>>2]) {
5580 ds_assemble_entry(i);
5581 }
5582 else {
5583 add_to_linker((int)out,ba[i],internal);
5584 emit_jmp(0);
5585 }
5586 }
5587 set_jump_target(nottaken,(int)out);
5588 }
5589
5590 if(nottaken1) set_jump_target(nottaken1,(int)out);
5591 if(adj) {
5592 if(!invert) emit_addimm(cc,CLOCK_DIVIDER*adj,cc);
5593 }
5594 } // (!unconditional)
5595 } // if(ooo)
5596 else
5597 {
5598 // In-order execution (branch first)
5599 //if(likely[i]) printf("IOL\n");
5600 //else
5601 //printf("IOE\n");
5602 int taken=0,nottaken=0,nottaken1=0;
5603 if(!unconditional&&!nop) {
5604 if(!only32)
5605 {
5606 assert(s1h>=0);
5607 if((opcode[i]&0x2f)==4) // BEQ
5608 {
5609 if(s2h>=0) emit_cmp(s1h,s2h);
5610 else emit_test(s1h,s1h);
5611 nottaken1=(int)out;
5612 emit_jne(2);
5613 }
5614 if((opcode[i]&0x2f)==5) // BNE
5615 {
5616 if(s2h>=0) emit_cmp(s1h,s2h);
5617 else emit_test(s1h,s1h);
5618 taken=(int)out;
5619 emit_jne(1);
5620 }
5621 if((opcode[i]&0x2f)==6) // BLEZ
5622 {
5623 emit_test(s1h,s1h);
5624 taken=(int)out;
5625 emit_js(1);
5626 nottaken1=(int)out;
5627 emit_jne(2);
5628 }
5629 if((opcode[i]&0x2f)==7) // BGTZ
5630 {
5631 emit_test(s1h,s1h);
5632 nottaken1=(int)out;
5633 emit_js(2);
5634 taken=(int)out;
5635 emit_jne(1);
5636 }
5637 } // if(!only32)
5638
5639 //printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5640 assert(s1l>=0);
5641 if((opcode[i]&0x2f)==4) // BEQ
5642 {
5643 if(s2l>=0) emit_cmp(s1l,s2l);
5644 else emit_test(s1l,s1l);
5645 nottaken=(int)out;
5646 emit_jne(2);
5647 }
5648 if((opcode[i]&0x2f)==5) // BNE
5649 {
5650 if(s2l>=0) emit_cmp(s1l,s2l);
5651 else emit_test(s1l,s1l);
5652 nottaken=(int)out;
5653 emit_jeq(2);
5654 }
5655 if((opcode[i]&0x2f)==6) // BLEZ
5656 {
5657 emit_cmpimm(s1l,1);
5658 nottaken=(int)out;
5659 emit_jge(2);
5660 }
5661 if((opcode[i]&0x2f)==7) // BGTZ
5662 {
5663 emit_cmpimm(s1l,1);
5664 nottaken=(int)out;
5665 emit_jl(2);
5666 }
5667 } // if(!unconditional)
5668 int adj;
5669 uint64_t ds_unneeded=branch_regs[i].u;
5670 uint64_t ds_unneeded_upper=branch_regs[i].uu;
5671 ds_unneeded&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
5672 ds_unneeded_upper&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
5673 if((~ds_unneeded_upper>>rt1[i+1])&1) ds_unneeded_upper&=~((1LL<<dep1[i+1])|(1LL<<dep2[i+1]));
5674 ds_unneeded|=1;
5675 ds_unneeded_upper|=1;
5676 // branch taken
5677 if(!nop) {
5678 if(taken) set_jump_target(taken,(int)out);
5679 assem_debug("1:\n");
5680 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5681 ds_unneeded,ds_unneeded_upper);
5682 // load regs
5683 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
5684 address_generation(i+1,&branch_regs[i],0);
5685 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,INVCP);
5686 ds_assemble(i+1,&branch_regs[i]);
5687 cc=get_reg(branch_regs[i].regmap,CCREG);
5688 if(cc==-1) {
5689 emit_loadreg(CCREG,cc=HOST_CCREG);
5690 // CHECK: Is the following instruction (fall thru) allocated ok?
5691 }
5692 assert(cc==HOST_CCREG);
5693 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5694 do_cc(i,i_regmap,&adj,ba[i],TAKEN,0);
5695 assem_debug("cycle count (adj)\n");
5696 if(adj) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc);
5697 load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5698 if(internal)
5699 assem_debug("branch: internal\n");
5700 else
5701 assem_debug("branch: external\n");
5702 if(internal&&is_ds[(ba[i]-start)>>2]) {
5703 ds_assemble_entry(i);
5704 }
5705 else {
5706 add_to_linker((int)out,ba[i],internal);
5707 emit_jmp(0);
5708 }
5709 }
5710 // branch not taken
5711 cop1_usable=prev_cop1_usable;
5712 if(!unconditional) {
5713 if(nottaken1) set_jump_target(nottaken1,(int)out);
5714 set_jump_target(nottaken,(int)out);
5715 assem_debug("2:\n");
5716 if(!likely[i]) {
5717 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5718 ds_unneeded,ds_unneeded_upper);
5719 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
5720 address_generation(i+1,&branch_regs[i],0);
5721 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
5722 ds_assemble(i+1,&branch_regs[i]);
5723 }
5724 cc=get_reg(branch_regs[i].regmap,CCREG);
5725 if(cc==-1&&!likely[i]) {
5726 // Cycle count isn't in a register, temporarily load it then write it out
5727 emit_loadreg(CCREG,HOST_CCREG);
5728 emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),HOST_CCREG);
5729 int jaddr=(int)out;
5730 emit_jns(0);
5731 add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,NOTTAKEN,0);
5732 emit_storereg(CCREG,HOST_CCREG);
5733 }
5734 else{
5735 cc=get_reg(i_regmap,CCREG);
5736 assert(cc==HOST_CCREG);
5737 emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),cc);
5738 int jaddr=(int)out;
5739 emit_jns(0);
5740 add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,likely[i]?NULLDS:NOTTAKEN,0);
5741 }
5742 }
5743 }
5744}
5745
5746void sjump_assemble(int i,struct regstat *i_regs)
5747{
5748 signed char *i_regmap=i_regs->regmap;
5749 int cc;
5750 int match;
5751 match=match_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5752 assem_debug("smatch=%d\n",match);
5753 int s1h,s1l;
5754 int prev_cop1_usable=cop1_usable;
5755 int unconditional=0,nevertaken=0;
5756 int only32=0;
57871462 5757 int invert=0;
5758 int internal=internal_branch(branch_regs[i].is32,ba[i]);
5759 if(i==(ba[i]-start)>>2) assem_debug("idle loop\n");
57871462 5760 if(!match) invert=1;
5761 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5762 if(i>(ba[i]-start)>>2) invert=1;
5763 #endif
5764
5765 //if(opcode2[i]>=0x10) return; // FIXME (BxxZAL)
df894a3a 5766 //assert(opcode2[i]<0x10||rs1[i]==0); // FIXME (BxxZAL)
57871462 5767
e1190b87 5768 if(ooo[i]) {
57871462 5769 s1l=get_reg(branch_regs[i].regmap,rs1[i]);
5770 s1h=get_reg(branch_regs[i].regmap,rs1[i]|64);
5771 }
5772 else {
5773 s1l=get_reg(i_regmap,rs1[i]);
5774 s1h=get_reg(i_regmap,rs1[i]|64);
5775 }
5776 if(rs1[i]==0)
5777 {
5778 if(opcode2[i]&1) unconditional=1;
5779 else nevertaken=1;
5780 // These are never taken (r0 is never less than zero)
5781 //assert(opcode2[i]!=0);
5782 //assert(opcode2[i]!=2);
5783 //assert(opcode2[i]!=0x10);
5784 //assert(opcode2[i]!=0x12);
5785 }
5786 else {
5787 only32=(regs[i].was32>>rs1[i])&1;
5788 }
5789
e1190b87 5790 if(ooo[i]) {
57871462 5791 // Out of order execution (delay slot first)
5792 //printf("OOOE\n");
5793 address_generation(i+1,i_regs,regs[i].regmap_entry);
5794 ds_assemble(i+1,i_regs);
5795 int adj;
5796 uint64_t bc_unneeded=branch_regs[i].u;
5797 uint64_t bc_unneeded_upper=branch_regs[i].uu;
5798 bc_unneeded&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
5799 bc_unneeded_upper&=~((1LL<<us1[i])|(1LL<<us2[i]));
5800 bc_unneeded|=1;
5801 bc_unneeded_upper|=1;
5802 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5803 bc_unneeded,bc_unneeded_upper);
5804 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i],rs1[i]);
5805 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
5806 if(rt1[i]==31) {
5807 int rt,return_address;
57871462 5808 rt=get_reg(branch_regs[i].regmap,31);
5809 assem_debug("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5810 if(rt>=0) {
5811 // Save the PC even if the branch is not taken
5812 return_address=start+i*4+8;
5813 emit_movimm(return_address,rt); // PC into link register
5814 #ifdef IMM_PREFETCH
5815 if(!nevertaken) emit_prefetch(hash_table[((return_address>>16)^return_address)&0xFFFF]);
5816 #endif
5817 }
5818 }
5819 cc=get_reg(branch_regs[i].regmap,CCREG);
5820 assert(cc==HOST_CCREG);
5821 if(unconditional)
5822 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5823 //do_cc(i,branch_regs[i].regmap,&adj,unconditional?ba[i]:-1,unconditional);
5824 assem_debug("cycle count (adj)\n");
5825 if(unconditional) {
5826 do_cc(i,branch_regs[i].regmap,&adj,ba[i],TAKEN,0);
5827 if(i!=(ba[i]-start)>>2 || source[i+1]!=0) {
5828 if(adj) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc);
5829 load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5830 if(internal)
5831 assem_debug("branch: internal\n");
5832 else
5833 assem_debug("branch: external\n");
5834 if(internal&&is_ds[(ba[i]-start)>>2]) {
5835 ds_assemble_entry(i);
5836 }
5837 else {
5838 add_to_linker((int)out,ba[i],internal);
5839 emit_jmp(0);
5840 }
5841 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5842 if(((u_int)out)&7) emit_addnop(0);
5843 #endif
5844 }
5845 }
5846 else if(nevertaken) {
5847 emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),cc);
5848 int jaddr=(int)out;
5849 emit_jns(0);
5850 add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,NOTTAKEN,0);
5851 }
5852 else {
5853 int nottaken=0;
5854 do_cc(i,branch_regs[i].regmap,&adj,-1,0,invert);
5855 if(adj&&!invert) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc);
5856 if(!only32)
5857 {
5858 assert(s1h>=0);
df894a3a 5859 if((opcode2[i]&0xf)==0) // BLTZ/BLTZAL
57871462 5860 {
5861 emit_test(s1h,s1h);
5862 if(invert){
5863 nottaken=(int)out;
5864 emit_jns(1);
5865 }else{
5866 add_to_linker((int)out,ba[i],internal);
5867 emit_js(0);
5868 }
5869 }
df894a3a 5870 if((opcode2[i]&0xf)==1) // BGEZ/BLTZAL
57871462 5871 {
5872 emit_test(s1h,s1h);
5873 if(invert){
5874 nottaken=(int)out;
5875 emit_js(1);
5876 }else{
5877 add_to_linker((int)out,ba[i],internal);
5878 emit_jns(0);
5879 }
5880 }
5881 } // if(!only32)
5882 else
5883 {
5884 assert(s1l>=0);
df894a3a 5885 if((opcode2[i]&0xf)==0) // BLTZ/BLTZAL
57871462 5886 {
5887 emit_test(s1l,s1l);
5888 if(invert){
5889 nottaken=(int)out;
5890 emit_jns(1);
5891 }else{
5892 add_to_linker((int)out,ba[i],internal);
5893 emit_js(0);
5894 }
5895 }
df894a3a 5896 if((opcode2[i]&0xf)==1) // BGEZ/BLTZAL
57871462 5897 {
5898 emit_test(s1l,s1l);
5899 if(invert){
5900 nottaken=(int)out;
5901 emit_js(1);
5902 }else{
5903 add_to_linker((int)out,ba[i],internal);
5904 emit_jns(0);
5905 }
5906 }
5907 } // if(!only32)
5908
5909 if(invert) {
5910 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5911 if(match&&(!internal||!is_ds[(ba[i]-start)>>2])) {
5912 if(adj) {
5913 emit_addimm(cc,-CLOCK_DIVIDER*adj,cc);
5914 add_to_linker((int)out,ba[i],internal);
5915 }else{
5916 emit_addnop(13);
5917 add_to_linker((int)out,ba[i],internal*2);
5918 }
5919 emit_jmp(0);
5920 }else
5921 #endif
5922 {
5923 if(adj) emit_addimm(cc,-CLOCK_DIVIDER*adj,cc);
5924 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5925 load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5926 if(internal)
5927 assem_debug("branch: internal\n");
5928 else
5929 assem_debug("branch: external\n");
5930 if(internal&&is_ds[(ba[i]-start)>>2]) {
5931 ds_assemble_entry(i);
5932 }
5933 else {
5934 add_to_linker((int)out,ba[i],internal);
5935 emit_jmp(0);
5936 }
5937 }
5938 set_jump_target(nottaken,(int)out);
5939 }
5940
5941 if(adj) {
5942 if(!invert) emit_addimm(cc,CLOCK_DIVIDER*adj,cc);
5943 }
5944 } // (!unconditional)
5945 } // if(ooo)
5946 else
5947 {
5948 // In-order execution (branch first)
5949 //printf("IOE\n");
5950 int nottaken=0;
a6491170 5951 if(rt1[i]==31) {
5952 int rt,return_address;
a6491170 5953 rt=get_reg(branch_regs[i].regmap,31);
5954 if(rt>=0) {
5955 // Save the PC even if the branch is not taken
5956 return_address=start+i*4+8;
5957 emit_movimm(return_address,rt); // PC into link register
5958 #ifdef IMM_PREFETCH
5959 emit_prefetch(hash_table[((return_address>>16)^return_address)&0xFFFF]);
5960 #endif
5961 }
5962 }
57871462 5963 if(!unconditional) {
5964 //printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5965 if(!only32)
5966 {
5967 assert(s1h>=0);
a6491170 5968 if((opcode2[i]&0x0d)==0) // BLTZ/BLTZL/BLTZAL/BLTZALL
57871462 5969 {
5970 emit_test(s1h,s1h);
5971 nottaken=(int)out;
5972 emit_jns(1);
5973 }
a6491170 5974 if((opcode2[i]&0x0d)==1) // BGEZ/BGEZL/BGEZAL/BGEZALL
57871462 5975 {
5976 emit_test(s1h,s1h);
5977 nottaken=(int)out;
5978 emit_js(1);
5979 }
5980 } // if(!only32)
5981 else
5982 {
5983 assert(s1l>=0);
a6491170 5984 if((opcode2[i]&0x0d)==0) // BLTZ/BLTZL/BLTZAL/BLTZALL
57871462 5985 {
5986 emit_test(s1l,s1l);
5987 nottaken=(int)out;
5988 emit_jns(1);
5989 }
a6491170 5990 if((opcode2[i]&0x0d)==1) // BGEZ/BGEZL/BGEZAL/BGEZALL
57871462 5991 {
5992 emit_test(s1l,s1l);
5993 nottaken=(int)out;
5994 emit_js(1);
5995 }
5996 }
5997 } // if(!unconditional)
5998 int adj;
5999 uint64_t ds_unneeded=branch_regs[i].u;
6000 uint64_t ds_unneeded_upper=branch_regs[i].uu;
6001 ds_unneeded&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
6002 ds_unneeded_upper&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
6003 if((~ds_unneeded_upper>>rt1[i+1])&1) ds_unneeded_upper&=~((1LL<<dep1[i+1])|(1LL<<dep2[i+1]));
6004 ds_unneeded|=1;
6005 ds_unneeded_upper|=1;
6006 // branch taken
6007 if(!nevertaken) {
6008 //assem_debug("1:\n");
6009 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
6010 ds_unneeded,ds_unneeded_upper);
6011 // load regs
6012 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
6013 address_generation(i+1,&branch_regs[i],0);
6014 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,INVCP);
6015 ds_assemble(i+1,&branch_regs[i]);
6016 cc=get_reg(branch_regs[i].regmap,CCREG);
6017 if(cc==-1) {
6018 emit_loadreg(CCREG,cc=HOST_CCREG);
6019 // CHECK: Is the following instruction (fall thru) allocated ok?
6020 }
6021 assert(cc==HOST_CCREG);
6022 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6023 do_cc(i,i_regmap,&adj,ba[i],TAKEN,0);
6024 assem_debug("cycle count (adj)\n");
6025 if(adj) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc);
6026 load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6027 if(internal)
6028 assem_debug("branch: internal\n");
6029 else
6030 assem_debug("branch: external\n");
6031 if(internal&&is_ds[(ba[i]-start)>>2]) {
6032 ds_assemble_entry(i);
6033 }
6034 else {
6035 add_to_linker((int)out,ba[i],internal);
6036 emit_jmp(0);
6037 }
6038 }
6039 // branch not taken
6040 cop1_usable=prev_cop1_usable;
6041 if(!unconditional) {
6042 set_jump_target(nottaken,(int)out);
6043 assem_debug("1:\n");
6044 if(!likely[i]) {
6045 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
6046 ds_unneeded,ds_unneeded_upper);
6047 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
6048 address_generation(i+1,&branch_regs[i],0);
6049 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
6050 ds_assemble(i+1,&branch_regs[i]);
6051 }
6052 cc=get_reg(branch_regs[i].regmap,CCREG);
6053 if(cc==-1&&!likely[i]) {
6054 // Cycle count isn't in a register, temporarily load it then write it out
6055 emit_loadreg(CCREG,HOST_CCREG);
6056 emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),HOST_CCREG);
6057 int jaddr=(int)out;
6058 emit_jns(0);
6059 add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,NOTTAKEN,0);
6060 emit_storereg(CCREG,HOST_CCREG);
6061 }
6062 else{
6063 cc=get_reg(i_regmap,CCREG);
6064 assert(cc==HOST_CCREG);
6065 emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),cc);
6066 int jaddr=(int)out;
6067 emit_jns(0);
6068 add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,likely[i]?NULLDS:NOTTAKEN,0);
6069 }
6070 }
6071 }
6072}
6073
6074void fjump_assemble(int i,struct regstat *i_regs)
6075{
6076 signed char *i_regmap=i_regs->regmap;
6077 int cc;
6078 int match;
6079 match=match_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6080 assem_debug("fmatch=%d\n",match);
6081 int fs,cs;
6082 int eaddr;
57871462 6083 int invert=0;
6084 int internal=internal_branch(branch_regs[i].is32,ba[i]);
6085 if(i==(ba[i]-start)>>2) assem_debug("idle loop\n");
57871462 6086 if(!match) invert=1;
6087 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
6088 if(i>(ba[i]-start)>>2) invert=1;
6089 #endif
6090
e1190b87 6091 if(ooo[i]) {
57871462 6092 fs=get_reg(branch_regs[i].regmap,FSREG);
6093 address_generation(i+1,i_regs,regs[i].regmap_entry); // Is this okay?
6094 }
6095 else {
6096 fs=get_reg(i_regmap,FSREG);
6097 }
6098
6099 // Check cop1 unusable
6100 if(!cop1_usable) {
6101 cs=get_reg(i_regmap,CSREG);
6102 assert(cs>=0);
6103 emit_testimm(cs,0x20000000);
6104 eaddr=(int)out;
6105 emit_jeq(0);
6106 add_stub(FP_STUB,eaddr,(int)out,i,cs,(int)i_regs,0,0);
6107 cop1_usable=1;
6108 }
6109
e1190b87 6110 if(ooo[i]) {
57871462 6111 // Out of order execution (delay slot first)
6112 //printf("OOOE\n");
6113 ds_assemble(i+1,i_regs);
6114 int adj;
6115 uint64_t bc_unneeded=branch_regs[i].u;
6116 uint64_t bc_unneeded_upper=branch_regs[i].uu;
6117 bc_unneeded&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
6118 bc_unneeded_upper&=~((1LL<<us1[i])|(1LL<<us2[i]));
6119 bc_unneeded|=1;
6120 bc_unneeded_upper|=1;
6121 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
6122 bc_unneeded,bc_unneeded_upper);
6123 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i],rs1[i]);
6124 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
6125 cc=get_reg(branch_regs[i].regmap,CCREG);
6126 assert(cc==HOST_CCREG);
6127 do_cc(i,branch_regs[i].regmap,&adj,-1,0,invert);
6128 assem_debug("cycle count (adj)\n");
6129 if(1) {
6130 int nottaken=0;
6131 if(adj&&!invert) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc);
6132 if(1) {
6133 assert(fs>=0);
6134 emit_testimm(fs,0x800000);
6135 if(source[i]&0x10000) // BC1T
6136 {
6137 if(invert){
6138 nottaken=(int)out;
6139 emit_jeq(1);
6140 }else{
6141 add_to_linker((int)out,ba[i],internal);
6142 emit_jne(0);
6143 }
6144 }
6145 else // BC1F
6146 if(invert){
6147 nottaken=(int)out;
6148 emit_jne(1);
6149 }else{
6150 add_to_linker((int)out,ba[i],internal);
6151 emit_jeq(0);
6152 }
6153 {
6154 }
6155 } // if(!only32)
6156
6157 if(invert) {
6158 if(adj) emit_addimm(cc,-CLOCK_DIVIDER*adj,cc);
6159 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
6160 else if(match) emit_addnop(13);
6161 #endif
6162 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6163 load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6164 if(internal)
6165 assem_debug("branch: internal\n");
6166 else
6167 assem_debug("branch: external\n");
6168 if(internal&&is_ds[(ba[i]-start)>>2]) {
6169 ds_assemble_entry(i);
6170 }
6171 else {
6172 add_to_linker((int)out,ba[i],internal);
6173 emit_jmp(0);
6174 }
6175 set_jump_target(nottaken,(int)out);
6176 }
6177
6178 if(adj) {
6179 if(!invert) emit_addimm(cc,CLOCK_DIVIDER*adj,cc);
6180 }
6181 } // (!unconditional)
6182 } // if(ooo)
6183 else
6184 {
6185 // In-order execution (branch first)
6186 //printf("IOE\n");
6187 int nottaken=0;
6188 if(1) {
6189 //printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
6190 if(1) {
6191 assert(fs>=0);
6192 emit_testimm(fs,0x800000);
6193 if(source[i]&0x10000) // BC1T
6194 {
6195 nottaken=(int)out;
6196 emit_jeq(1);
6197 }
6198 else // BC1F
6199 {
6200 nottaken=(int)out;
6201 emit_jne(1);
6202 }
6203 }
6204 } // if(!unconditional)
6205 int adj;
6206 uint64_t ds_unneeded=branch_regs[i].u;
6207 uint64_t ds_unneeded_upper=branch_regs[i].uu;
6208 ds_unneeded&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
6209 ds_unneeded_upper&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
6210 if((~ds_unneeded_upper>>rt1[i+1])&1) ds_unneeded_upper&=~((1LL<<dep1[i+1])|(1LL<<dep2[i+1]));
6211 ds_unneeded|=1;
6212 ds_unneeded_upper|=1;
6213 // branch taken
6214 //assem_debug("1:\n");
6215 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
6216 ds_unneeded,ds_unneeded_upper);
6217 // load regs
6218 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
6219 address_generation(i+1,&branch_regs[i],0);
6220 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,INVCP);
6221 ds_assemble(i+1,&branch_regs[i]);
6222 cc=get_reg(branch_regs[i].regmap,CCREG);
6223 if(cc==-1) {
6224 emit_loadreg(CCREG,cc=HOST_CCREG);
6225 // CHECK: Is the following instruction (fall thru) allocated ok?
6226 }
6227 assert(cc==HOST_CCREG);
6228 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6229 do_cc(i,i_regmap,&adj,ba[i],TAKEN,0);
6230 assem_debug("cycle count (adj)\n");
6231 if(adj) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc);
6232 load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6233 if(internal)
6234 assem_debug("branch: internal\n");
6235 else
6236 assem_debug("branch: external\n");
6237 if(internal&&is_ds[(ba[i]-start)>>2]) {
6238 ds_assemble_entry(i);
6239 }
6240 else {
6241 add_to_linker((int)out,ba[i],internal);
6242 emit_jmp(0);
6243 }
6244
6245 // branch not taken
6246 if(1) { // <- FIXME (don't need this)
6247 set_jump_target(nottaken,(int)out);
6248 assem_debug("1:\n");
6249 if(!likely[i]) {
6250 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
6251 ds_unneeded,ds_unneeded_upper);
6252 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
6253 address_generation(i+1,&branch_regs[i],0);
6254 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
6255 ds_assemble(i+1,&branch_regs[i]);
6256 }
6257 cc=get_reg(branch_regs[i].regmap,CCREG);
6258 if(cc==-1&&!likely[i]) {
6259 // Cycle count isn't in a register, temporarily load it then write it out
6260 emit_loadreg(CCREG,HOST_CCREG);
6261 emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),HOST_CCREG);
6262 int jaddr=(int)out;
6263 emit_jns(0);
6264 add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,NOTTAKEN,0);
6265 emit_storereg(CCREG,HOST_CCREG);
6266 }
6267 else{
6268 cc=get_reg(i_regmap,CCREG);
6269 assert(cc==HOST_CCREG);
6270 emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),cc);
6271 int jaddr=(int)out;
6272 emit_jns(0);
6273 add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,likely[i]?NULLDS:NOTTAKEN,0);
6274 }
6275 }
6276 }
6277}
6278
6279static void pagespan_assemble(int i,struct regstat *i_regs)
6280{
6281 int s1l=get_reg(i_regs->regmap,rs1[i]);
6282 int s1h=get_reg(i_regs->regmap,rs1[i]|64);
6283 int s2l=get_reg(i_regs->regmap,rs2[i]);
6284 int s2h=get_reg(i_regs->regmap,rs2[i]|64);
6285 void *nt_branch=NULL;
6286 int taken=0;
6287 int nottaken=0;
6288 int unconditional=0;
6289 if(rs1[i]==0)
6290 {
6291 s1l=s2l;s1h=s2h;
6292 s2l=s2h=-1;
6293 }
6294 else if(rs2[i]==0)
6295 {
6296 s2l=s2h=-1;
6297 }
6298 if((i_regs->is32>>rs1[i])&(i_regs->is32>>rs2[i])&1) {
6299 s1h=s2h=-1;
6300 }
6301 int hr=0;
6302 int addr,alt,ntaddr;
6303 if(i_regs->regmap[HOST_BTREG]<0) {addr=HOST_BTREG;}
6304 else {
6305 while(hr<HOST_REGS)
6306 {
6307 if(hr!=EXCLUDE_REG && hr!=HOST_CCREG &&
6308 (i_regs->regmap[hr]&63)!=rs1[i] &&
6309 (i_regs->regmap[hr]&63)!=rs2[i] )
6310 {
6311 addr=hr++;break;
6312 }
6313 hr++;
6314 }
6315 }
6316 while(hr<HOST_REGS)
6317 {
6318 if(hr!=EXCLUDE_REG && hr!=HOST_CCREG && hr!=HOST_BTREG &&
6319 (i_regs->regmap[hr]&63)!=rs1[i] &&
6320 (i_regs->regmap[hr]&63)!=rs2[i] )
6321 {
6322 alt=hr++;break;
6323 }
6324 hr++;
6325 }
6326 if((opcode[i]&0x2E)==6) // BLEZ/BGTZ needs another register
6327 {
6328 while(hr<HOST_REGS)
6329 {
6330 if(hr!=EXCLUDE_REG && hr!=HOST_CCREG && hr!=HOST_BTREG &&
6331 (i_regs->regmap[hr]&63)!=rs1[i] &&
6332 (i_regs->regmap[hr]&63)!=rs2[i] )
6333 {
6334 ntaddr=hr;break;
6335 }
6336 hr++;
6337 }
6338 }
6339 assert(hr<HOST_REGS);
6340 if((opcode[i]&0x2e)==4||opcode[i]==0x11) { // BEQ/BNE/BEQL/BNEL/BC1
6341 load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,CCREG,CCREG);
6342 }
6343 emit_addimm(HOST_CCREG,CLOCK_DIVIDER*(ccadj[i]+2),HOST_CCREG);
6344 if(opcode[i]==2) // J
6345 {
6346 unconditional=1;
6347 }
6348 if(opcode[i]==3) // JAL
6349 {
6350 // TODO: mini_ht
6351 int rt=get_reg(i_regs->regmap,31);
6352 emit_movimm(start+i*4+8,rt);
6353 unconditional=1;
6354 }
6355 if(opcode[i]==0&&(opcode2[i]&0x3E)==8) // JR/JALR
6356 {
6357 emit_mov(s1l,addr);
6358 if(opcode2[i]==9) // JALR
6359 {
5067f341 6360 int rt=get_reg(i_regs->regmap,rt1[i]);
57871462 6361 emit_movimm(start+i*4+8,rt);
6362 }
6363 }
6364 if((opcode[i]&0x3f)==4) // BEQ
6365 {
6366 if(rs1[i]==rs2[i])
6367 {
6368 unconditional=1;
6369 }
6370 else
6371 #ifdef HAVE_CMOV_IMM
6372 if(s1h<0) {
6373 if(s2l>=0) emit_cmp(s1l,s2l);
6374 else emit_test(s1l,s1l);
6375 emit_cmov2imm_e_ne_compact(ba[i],start+i*4+8,addr);
6376 }
6377 else
6378 #endif
6379 {
6380 assert(s1l>=0);
6381 emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
6382 if(s1h>=0) {
6383 if(s2h>=0) emit_cmp(s1h,s2h);
6384 else emit_test(s1h,s1h);
6385 emit_cmovne_reg(alt,addr);
6386 }
6387 if(s2l>=0) emit_cmp(s1l,s2l);
6388 else emit_test(s1l,s1l);
6389 emit_cmovne_reg(alt,addr);
6390 }
6391 }
6392 if((opcode[i]&0x3f)==5) // BNE
6393 {
6394 #ifdef HAVE_CMOV_IMM
6395 if(s1h<0) {
6396 if(s2l>=0) emit_cmp(s1l,s2l);
6397 else emit_test(s1l,s1l);
6398 emit_cmov2imm_e_ne_compact(start+i*4+8,ba[i],addr);
6399 }
6400 else
6401 #endif
6402 {
6403 assert(s1l>=0);
6404 emit_mov2imm_compact(start+i*4+8,addr,ba[i],alt);
6405 if(s1h>=0) {
6406 if(s2h>=0) emit_cmp(s1h,s2h);
6407 else emit_test(s1h,s1h);
6408 emit_cmovne_reg(alt,addr);
6409 }
6410 if(s2l>=0) emit_cmp(s1l,s2l);
6411 else emit_test(s1l,s1l);
6412 emit_cmovne_reg(alt,addr);
6413 }
6414 }
6415 if((opcode[i]&0x3f)==0x14) // BEQL
6416 {
6417 if(s1h>=0) {
6418 if(s2h>=0) emit_cmp(s1h,s2h);
6419 else emit_test(s1h,s1h);
6420 nottaken=(int)out;
6421 emit_jne(0);
6422 }
6423 if(s2l>=0) emit_cmp(s1l,s2l);
6424 else emit_test(s1l,s1l);
6425 if(nottaken) set_jump_target(nottaken,(int)out);
6426 nottaken=(int)out;
6427 emit_jne(0);
6428 }
6429 if((opcode[i]&0x3f)==0x15) // BNEL
6430 {
6431 if(s1h>=0) {
6432 if(s2h>=0) emit_cmp(s1h,s2h);
6433 else emit_test(s1h,s1h);
6434 taken=(int)out;
6435 emit_jne(0);
6436 }
6437 if(s2l>=0) emit_cmp(s1l,s2l);
6438 else emit_test(s1l,s1l);
6439 nottaken=(int)out;
6440 emit_jeq(0);
6441 if(taken) set_jump_target(taken,(int)out);
6442 }
6443 if((opcode[i]&0x3f)==6) // BLEZ
6444 {
6445 emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
6446 emit_cmpimm(s1l,1);
6447 if(s1h>=0) emit_mov(addr,ntaddr);
6448 emit_cmovl_reg(alt,addr);
6449 if(s1h>=0) {
6450 emit_test(s1h,s1h);
6451 emit_cmovne_reg(ntaddr,addr);
6452 emit_cmovs_reg(alt,addr);
6453 }
6454 }
6455 if((opcode[i]&0x3f)==7) // BGTZ
6456 {
6457 emit_mov2imm_compact(ba[i],addr,start+i*4+8,ntaddr);
6458 emit_cmpimm(s1l,1);
6459 if(s1h>=0) emit_mov(addr,alt);
6460 emit_cmovl_reg(ntaddr,addr);
6461 if(s1h>=0) {
6462 emit_test(s1h,s1h);
6463 emit_cmovne_reg(alt,addr);
6464 emit_cmovs_reg(ntaddr,addr);
6465 }
6466 }
6467 if((opcode[i]&0x3f)==0x16) // BLEZL
6468 {
6469 assert((opcode[i]&0x3f)!=0x16);
6470 }
6471 if((opcode[i]&0x3f)==0x17) // BGTZL
6472 {
6473 assert((opcode[i]&0x3f)!=0x17);
6474 }
6475 assert(opcode[i]!=1); // BLTZ/BGEZ
6476
6477 //FIXME: Check CSREG
6478 if(opcode[i]==0x11 && opcode2[i]==0x08 ) {
6479 if((source[i]&0x30000)==0) // BC1F
6480 {
6481 emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
6482 emit_testimm(s1l,0x800000);
6483 emit_cmovne_reg(alt,addr);
6484 }
6485 if((source[i]&0x30000)==0x10000) // BC1T
6486 {
6487 emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
6488 emit_testimm(s1l,0x800000);
6489 emit_cmovne_reg(alt,addr);
6490 }
6491 if((source[i]&0x30000)==0x20000) // BC1FL
6492 {
6493 emit_testimm(s1l,0x800000);
6494 nottaken=(int)out;
6495 emit_jne(0);
6496 }
6497 if((source[i]&0x30000)==0x30000) // BC1TL
6498 {
6499 emit_testimm(s1l,0x800000);
6500 nottaken=(int)out;
6501 emit_jeq(0);
6502 }
6503 }
6504
6505 assert(i_regs->regmap[HOST_CCREG]==CCREG);
6506 wb_dirtys(regs[i].regmap,regs[i].is32,regs[i].dirty);
6507 if(likely[i]||unconditional)
6508 {
6509 emit_movimm(ba[i],HOST_BTREG);
6510 }
6511 else if(addr!=HOST_BTREG)
6512 {
6513 emit_mov(addr,HOST_BTREG);
6514 }
6515 void *branch_addr=out;
6516 emit_jmp(0);
6517 int target_addr=start+i*4+5;
6518 void *stub=out;
6519 void *compiled_target_addr=check_addr(target_addr);
6520 emit_extjump_ds((int)branch_addr,target_addr);
6521 if(compiled_target_addr) {
6522 set_jump_target((int)branch_addr,(int)compiled_target_addr);
6523 add_link(target_addr,stub);
6524 }
6525 else set_jump_target((int)branch_addr,(int)stub);
6526 if(likely[i]) {
6527 // Not-taken path
6528 set_jump_target((int)nottaken,(int)out);
6529 wb_dirtys(regs[i].regmap,regs[i].is32,regs[i].dirty);
6530 void *branch_addr=out;
6531 emit_jmp(0);
6532 int target_addr=start+i*4+8;
6533 void *stub=out;
6534 void *compiled_target_addr=check_addr(target_addr);
6535 emit_extjump_ds((int)branch_addr,target_addr);
6536 if(compiled_target_addr) {
6537 set_jump_target((int)branch_addr,(int)compiled_target_addr);
6538 add_link(target_addr,stub);
6539 }
6540 else set_jump_target((int)branch_addr,(int)stub);
6541 }
6542}
6543
6544// Assemble the delay slot for the above
6545static void pagespan_ds()
6546{
6547 assem_debug("initial delay slot:\n");
6548 u_int vaddr=start+1;
94d23bb9 6549 u_int page=get_page(vaddr);
6550 u_int vpage=get_vpage(vaddr);
57871462 6551 ll_add(jump_dirty+vpage,vaddr,(void *)out);
6552 do_dirty_stub_ds();
6553 ll_add(jump_in+page,vaddr,(void *)out);
6554 assert(regs[0].regmap_entry[HOST_CCREG]==CCREG);
6555 if(regs[0].regmap[HOST_CCREG]!=CCREG)
6556 wb_register(CCREG,regs[0].regmap_entry,regs[0].wasdirty,regs[0].was32);
6557 if(regs[0].regmap[HOST_BTREG]!=BTREG)
6558 emit_writeword(HOST_BTREG,(int)&branch_target);
6559 load_regs(regs[0].regmap_entry,regs[0].regmap,regs[0].was32,rs1[0],rs2[0]);
6560 address_generation(0,&regs[0],regs[0].regmap_entry);
b9b61529 6561 if(itype[0]==STORE||itype[0]==STORELR||(opcode[0]&0x3b)==0x39||(opcode[0]&0x3b)==0x3a)
57871462 6562 load_regs(regs[0].regmap_entry,regs[0].regmap,regs[0].was32,INVCP,INVCP);
6563 cop1_usable=0;
6564 is_delayslot=0;
6565 switch(itype[0]) {
6566 case ALU:
6567 alu_assemble(0,&regs[0]);break;
6568 case IMM16:
6569 imm16_assemble(0,&regs[0]);break;
6570 case SHIFT:
6571 shift_assemble(0,&regs[0]);break;
6572 case SHIFTIMM:
6573 shiftimm_assemble(0,&regs[0]);break;
6574 case LOAD:
6575 load_assemble(0,&regs[0]);break;
6576 case LOADLR:
6577 loadlr_assemble(0,&regs[0]);break;
6578 case STORE:
6579 store_assemble(0,&regs[0]);break;
6580 case STORELR:
6581 storelr_assemble(0,&regs[0]);break;
6582 case COP0:
6583 cop0_assemble(0,&regs[0]);break;
6584 case COP1:
6585 cop1_assemble(0,&regs[0]);break;
6586 case C1LS:
6587 c1ls_assemble(0,&regs[0]);break;
b9b61529 6588 case COP2:
6589 cop2_assemble(0,&regs[0]);break;
6590 case C2LS:
6591 c2ls_assemble(0,&regs[0]);break;
6592 case C2OP:
6593 c2op_assemble(0,&regs[0]);break;
57871462 6594 case FCONV:
6595 fconv_assemble(0,&regs[0]);break;
6596 case FLOAT:
6597 float_assemble(0,&regs[0]);break;
6598 case FCOMP:
6599 fcomp_assemble(0,&regs[0]);break;
6600 case MULTDIV:
6601 multdiv_assemble(0,&regs[0]);break;
6602 case MOV:
6603 mov_assemble(0,&regs[0]);break;
6604 case SYSCALL:
7139f3c8 6605 case HLECALL:
1e973cb0 6606 case INTCALL:
57871462 6607 case SPAN:
6608 case UJUMP:
6609 case RJUMP:
6610 case CJUMP:
6611 case SJUMP:
6612 case FJUMP:
6613 printf("Jump in the delay slot. This is probably a bug.\n");
6614 }
6615 int btaddr=get_reg(regs[0].regmap,BTREG);
6616 if(btaddr<0) {
6617 btaddr=get_reg(regs[0].regmap,-1);
6618 emit_readword((int)&branch_target,btaddr);
6619 }
6620 assert(btaddr!=HOST_CCREG);
6621 if(regs[0].regmap[HOST_CCREG]!=CCREG) emit_loadreg(CCREG,HOST_CCREG);
6622#ifdef HOST_IMM8
6623 emit_movimm(start+4,HOST_TEMPREG);
6624 emit_cmp(btaddr,HOST_TEMPREG);
6625#else
6626 emit_cmpimm(btaddr,start+4);
6627#endif
6628 int branch=(int)out;
6629 emit_jeq(0);
6630 store_regs_bt(regs[0].regmap,regs[0].is32,regs[0].dirty,-1);
6631 emit_jmp(jump_vaddr_reg[btaddr]);
6632 set_jump_target(branch,(int)out);
6633 store_regs_bt(regs[0].regmap,regs[0].is32,regs[0].dirty,start+4);
6634 load_regs_bt(regs[0].regmap,regs[0].is32,regs[0].dirty,start+4);
6635}
6636
6637// Basic liveness analysis for MIPS registers
6638void unneeded_registers(int istart,int iend,int r)
6639{
6640 int i;
6641 uint64_t u,uu,b,bu;
6642 uint64_t temp_u,temp_uu;
6643 uint64_t tdep;
6644 if(iend==slen-1) {
6645 u=1;uu=1;
6646 }else{
6647 u=unneeded_reg[iend+1];
6648 uu=unneeded_reg_upper[iend+1];
6649 u=1;uu=1;
6650 }
6651 for (i=iend;i>=istart;i--)
6652 {
6653 //printf("unneeded registers i=%d (%d,%d) r=%d\n",i,istart,iend,r);
6654 if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
6655 {
6656 // If subroutine call, flag return address as a possible branch target
6657 if(rt1[i]==31 && i<slen-2) bt[i+2]=1;
6658
6659 if(ba[i]<start || ba[i]>=(start+slen*4))
6660 {
6661 // Branch out of this block, flush all regs
6662 u=1;
6663 uu=1;
6664 /* Hexagon hack
6665 if(itype[i]==UJUMP&&rt1[i]==31)
6666 {
6667 uu=u=0x300C00F; // Discard at, v0-v1, t6-t9
6668 }
6669 if(itype[i]==RJUMP&&rs1[i]==31)
6670 {
6671 uu=u=0x300C0F3; // Discard at, a0-a3, t6-t9
6672 }
4cb76aa4 6673 if(start>0x80000400&&start<0x80000000+RAM_SIZE) {
57871462 6674 if(itype[i]==UJUMP&&rt1[i]==31)
6675 {
6676 //uu=u=0x30300FF0FLL; // Discard at, v0-v1, t0-t9, lo, hi
6677 uu=u=0x300FF0F; // Discard at, v0-v1, t0-t9
6678 }
6679 if(itype[i]==RJUMP&&rs1[i]==31)
6680 {
6681 //uu=u=0x30300FFF3LL; // Discard at, a0-a3, t0-t9, lo, hi
6682 uu=u=0x300FFF3; // Discard at, a0-a3, t0-t9
6683 }
6684 }*/
6685 branch_unneeded_reg[i]=u;
6686 branch_unneeded_reg_upper[i]=uu;
6687 // Merge in delay slot
6688 tdep=(~uu>>rt1[i+1])&1;
6689 u|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6690 uu|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6691 u&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
6692 uu&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
6693 uu&=~((tdep<<dep1[i+1])|(tdep<<dep2[i+1]));
6694 u|=1;uu|=1;
6695 // If branch is "likely" (and conditional)
6696 // then we skip the delay slot on the fall-thru path
6697 if(likely[i]) {
6698 if(i<slen-1) {
6699 u&=unneeded_reg[i+2];
6700 uu&=unneeded_reg_upper[i+2];
6701 }
6702 else
6703 {
6704 u=1;
6705 uu=1;
6706 }
6707 }
6708 }
6709 else
6710 {
6711 // Internal branch, flag target
6712 bt[(ba[i]-start)>>2]=1;
6713 if(ba[i]<=start+i*4) {
6714 // Backward branch
6715 if(itype[i]==RJUMP||itype[i]==UJUMP||(source[i]>>16)==0x1000)
6716 {
6717 // Unconditional branch
6718 temp_u=1;temp_uu=1;
6719 } else {
6720 // Conditional branch (not taken case)
6721 temp_u=unneeded_reg[i+2];
6722 temp_uu=unneeded_reg_upper[i+2];
6723 }
6724 // Merge in delay slot
6725 tdep=(~temp_uu>>rt1[i+1])&1;
6726 temp_u|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6727 temp_uu|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6728 temp_u&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
6729 temp_uu&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
6730 temp_uu&=~((tdep<<dep1[i+1])|(tdep<<dep2[i+1]));
6731 temp_u|=1;temp_uu|=1;
6732 // If branch is "likely" (and conditional)
6733 // then we skip the delay slot on the fall-thru path
6734 if(likely[i]) {
6735 if(i<slen-1) {
6736 temp_u&=unneeded_reg[i+2];
6737 temp_uu&=unneeded_reg_upper[i+2];
6738 }
6739 else
6740 {
6741 temp_u=1;
6742 temp_uu=1;
6743 }
6744 }
6745 tdep=(~temp_uu>>rt1[i])&1;
6746 temp_u|=(1LL<<rt1[i])|(1LL<<rt2[i]);
6747 temp_uu|=(1LL<<rt1[i])|(1LL<<rt2[i]);
6748 temp_u&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
6749 temp_uu&=~((1LL<<us1[i])|(1LL<<us2[i]));
6750 temp_uu&=~((tdep<<dep1[i])|(tdep<<dep2[i]));
6751 temp_u|=1;temp_uu|=1;
6752 unneeded_reg[i]=temp_u;
6753 unneeded_reg_upper[i]=temp_uu;
6754 // Only go three levels deep. This recursion can take an
6755 // excessive amount of time if there are a lot of nested loops.
6756 if(r<2) {
6757 unneeded_registers((ba[i]-start)>>2,i-1,r+1);
6758 }else{
6759 unneeded_reg[(ba[i]-start)>>2]=1;
6760 unneeded_reg_upper[(ba[i]-start)>>2]=1;
6761 }
6762 } /*else*/ if(1) {
6763 if(itype[i]==RJUMP||itype[i]==UJUMP||(source[i]>>16)==0x1000)
6764 {
6765 // Unconditional branch
6766 u=unneeded_reg[(ba[i]-start)>>2];
6767 uu=unneeded_reg_upper[(ba[i]-start)>>2];
6768 branch_unneeded_reg[i]=u;
6769 branch_unneeded_reg_upper[i]=uu;
6770 //u=1;
6771 //uu=1;
6772 //branch_unneeded_reg[i]=u;
6773 //branch_unneeded_reg_upper[i]=uu;
6774 // Merge in delay slot
6775 tdep=(~uu>>rt1[i+1])&1;
6776 u|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6777 uu|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6778 u&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
6779 uu&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
6780 uu&=~((tdep<<dep1[i+1])|(tdep<<dep2[i+1]));
6781 u|=1;uu|=1;
6782 } else {
6783 // Conditional branch
6784 b=unneeded_reg[(ba[i]-start)>>2];
6785 bu=unneeded_reg_upper[(ba[i]-start)>>2];
6786 branch_unneeded_reg[i]=b;
6787 branch_unneeded_reg_upper[i]=bu;
6788 //b=1;
6789 //bu=1;
6790 //branch_unneeded_reg[i]=b;
6791 //branch_unneeded_reg_upper[i]=bu;
6792 // Branch delay slot
6793 tdep=(~uu>>rt1[i+1])&1;
6794 b|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6795 bu|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6796 b&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
6797 bu&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
6798 bu&=~((tdep<<dep1[i+1])|(tdep<<dep2[i+1]));
6799 b|=1;bu|=1;
6800 // If branch is "likely" then we skip the
6801 // delay slot on the fall-thru path
6802 if(likely[i]) {
6803 u=b;
6804 uu=bu;
6805 if(i<slen-1) {
6806 u&=unneeded_reg[i+2];
6807 uu&=unneeded_reg_upper[i+2];
6808 //u=1;
6809 //uu=1;
6810 }
6811 } else {
6812 u&=b;
6813 uu&=bu;
6814 //u=1;
6815 //uu=1;
6816 }
6817 if(i<slen-1) {
6818 branch_unneeded_reg[i]&=unneeded_reg[i+2];
6819 branch_unneeded_reg_upper[i]&=unneeded_reg_upper[i+2];
6820 //branch_unneeded_reg[i]=1;
6821 //branch_unneeded_reg_upper[i]=1;
6822 } else {
6823 branch_unneeded_reg[i]=1;
6824 branch_unneeded_reg_upper[i]=1;
6825 }
6826 }
6827 }
6828 }
6829 }
1e973cb0 6830 else if(itype[i]==SYSCALL||itype[i]==HLECALL||itype[i]==INTCALL)
57871462 6831 {
6832 // SYSCALL instruction (software interrupt)
6833 u=1;
6834 uu=1;
6835 }
6836 else if(itype[i]==COP0 && (source[i]&0x3f)==0x18)
6837 {
6838 // ERET instruction (return from interrupt)
6839 u=1;
6840 uu=1;
6841 }
6842 //u=uu=1; // DEBUG
6843 tdep=(~uu>>rt1[i])&1;
6844 // Written registers are unneeded
6845 u|=1LL<<rt1[i];
6846 u|=1LL<<rt2[i];
6847 uu|=1LL<<rt1[i];
6848 uu|=1LL<<rt2[i];
6849 // Accessed registers are needed
6850 u&=~(1LL<<rs1[i]);
6851 u&=~(1LL<<rs2[i]);
6852 uu&=~(1LL<<us1[i]);
6853 uu&=~(1LL<<us2[i]);
6854 // Source-target dependencies
6855 uu&=~(tdep<<dep1[i]);
6856 uu&=~(tdep<<dep2[i]);
6857 // R0 is always unneeded
6858 u|=1;uu|=1;
6859 // Save it
6860 unneeded_reg[i]=u;
6861 unneeded_reg_upper[i]=uu;
6862 /*
6863 printf("ur (%d,%d) %x: ",istart,iend,start+i*4);
6864 printf("U:");
6865 int r;
6866 for(r=1;r<=CCREG;r++) {
6867 if((unneeded_reg[i]>>r)&1) {
6868 if(r==HIREG) printf(" HI");
6869 else if(r==LOREG) printf(" LO");
6870 else printf(" r%d",r);
6871 }
6872 }
6873 printf(" UU:");
6874 for(r=1;r<=CCREG;r++) {
6875 if(((unneeded_reg_upper[i]&~unneeded_reg[i])>>r)&1) {
6876 if(r==HIREG) printf(" HI");
6877 else if(r==LOREG) printf(" LO");
6878 else printf(" r%d",r);
6879 }
6880 }
6881 printf("\n");*/
6882 }
252c20fc 6883#ifdef FORCE32
6884 for (i=iend;i>=istart;i--)
6885 {
6886 unneeded_reg_upper[i]=branch_unneeded_reg_upper[i]=-1LL;
6887 }
6888#endif
57871462 6889}
6890
6891// Identify registers which are likely to contain 32-bit values
6892// This is used to predict whether any branches will jump to a
6893// location with 64-bit values in registers.
6894static void provisional_32bit()
6895{
6896 int i,j;
6897 uint64_t is32=1;
6898 uint64_t lastbranch=1;
6899
6900 for(i=0;i<slen;i++)
6901 {
6902 if(i>0) {
6903 if(itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP) {
6904 if(i>1) is32=lastbranch;
6905 else is32=1;
6906 }
6907 }
6908 if(i>1)
6909 {
6910 if(itype[i-2]==CJUMP||itype[i-2]==SJUMP||itype[i-2]==FJUMP) {
6911 if(likely[i-2]) {
6912 if(i>2) is32=lastbranch;
6913 else is32=1;
6914 }
6915 }
6916 if((opcode[i-2]&0x2f)==0x05) // BNE/BNEL
6917 {
6918 if(rs1[i-2]==0||rs2[i-2]==0)
6919 {
6920 if(rs1[i-2]) {
6921 is32|=1LL<<rs1[i-2];
6922 }
6923 if(rs2[i-2]) {
6924 is32|=1LL<<rs2[i-2];
6925 }
6926 }
6927 }
6928 }
6929 // If something jumps here with 64-bit values
6930 // then promote those registers to 64 bits
6931 if(bt[i])
6932 {
6933 uint64_t temp_is32=is32;
6934 for(j=i-1;j>=0;j--)
6935 {
6936 if(ba[j]==start+i*4)
6937 //temp_is32&=branch_regs[j].is32;
6938 temp_is32&=p32[j];
6939 }
6940 for(j=i;j<slen;j++)
6941 {
6942 if(ba[j]==start+i*4)
6943 temp_is32=1;
6944 }
6945 is32=temp_is32;
6946 }
6947 int type=itype[i];
6948 int op=opcode[i];
6949 int op2=opcode2[i];
6950 int rt=rt1[i];
6951 int s1=rs1[i];
6952 int s2=rs2[i];
6953 if(type==UJUMP||type==RJUMP||type==CJUMP||type==SJUMP||type==FJUMP) {
6954 // Branches don't write registers, consider the delay slot instead.
6955 type=itype[i+1];
6956 op=opcode[i+1];
6957 op2=opcode2[i+1];
6958 rt=rt1[i+1];
6959 s1=rs1[i+1];
6960 s2=rs2[i+1];
6961 lastbranch=is32;
6962 }
6963 switch(type) {
6964 case LOAD:
6965 if(opcode[i]==0x27||opcode[i]==0x37|| // LWU/LD
6966 opcode[i]==0x1A||opcode[i]==0x1B) // LDL/LDR
6967 is32&=~(1LL<<rt);
6968 else
6969 is32|=1LL<<rt;
6970 break;
6971 case STORE:
6972 case STORELR:
6973 break;
6974 case LOADLR:
6975 if(op==0x1a||op==0x1b) is32&=~(1LL<<rt); // LDR/LDL
6976 if(op==0x22) is32|=1LL<<rt; // LWL
6977 break;
6978 case IMM16:
6979 if (op==0x08||op==0x09|| // ADDI/ADDIU
6980 op==0x0a||op==0x0b|| // SLTI/SLTIU
6981 op==0x0c|| // ANDI
6982 op==0x0f) // LUI
6983 {
6984 is32|=1LL<<rt;
6985 }
6986 if(op==0x18||op==0x19) { // DADDI/DADDIU
6987 is32&=~(1LL<<rt);
6988 //if(imm[i]==0)
6989 // is32|=((is32>>s1)&1LL)<<rt;
6990 }
6991 if(op==0x0d||op==0x0e) { // ORI/XORI
6992 uint64_t sr=((is32>>s1)&1LL);
6993 is32&=~(1LL<<rt);
6994 is32|=sr<<rt;
6995 }
6996 break;
6997 case UJUMP:
6998 break;
6999 case RJUMP:
7000 break;
7001 case CJUMP:
7002 break;
7003 case SJUMP:
7004 break;
7005 case FJUMP:
7006 break;
7007 case ALU:
7008 if(op2>=0x20&&op2<=0x23) { // ADD/ADDU/SUB/SUBU
7009 is32|=1LL<<rt;
7010 }
7011 if(op2==0x2a||op2==0x2b) { // SLT/SLTU
7012 is32|=1LL<<rt;
7013 }
7014 else if(op2>=0x24&&op2<=0x27) { // AND/OR/XOR/NOR
7015 uint64_t sr=((is32>>s1)&(is32>>s2)&1LL);
7016 is32&=~(1LL<<rt);
7017 is32|=sr<<rt;
7018 }
7019 else if(op2>=0x2c&&op2<=0x2d) { // DADD/DADDU
7020 if(s1==0&&s2==0) {
7021 is32|=1LL<<rt;
7022 }
7023 else if(s2==0) {
7024 uint64_t sr=((is32>>s1)&1LL);
7025 is32&=~(1LL<<rt);
7026 is32|=sr<<rt;
7027 }
7028 else if(s1==0) {
7029 uint64_t sr=((is32>>s2)&1LL);
7030 is32&=~(1LL<<rt);
7031 is32|=sr<<rt;
7032 }
7033 else {
7034 is32&=~(1LL<<rt);
7035 }
7036 }
7037 else if(op2>=0x2e&&op2<=0x2f) { // DSUB/DSUBU
7038 if(s1==0&&s2==0) {
7039 is32|=1LL<<rt;
7040 }
7041 else if(s2==0) {
7042 uint64_t sr=((is32>>s1)&1LL);
7043 is32&=~(1LL<<rt);
7044 is32|=sr<<rt;
7045 }
7046 else {
7047 is32&=~(1LL<<rt);
7048 }
7049 }
7050 break;
7051 case MULTDIV:
7052 if (op2>=0x1c&&op2<=0x1f) { // DMULT/DMULTU/DDIV/DDIVU
7053 is32&=~((1LL<<HIREG)|(1LL<<LOREG));
7054 }
7055 else {
7056 is32|=(1LL<<HIREG)|(1LL<<LOREG);
7057 }
7058 break;
7059 case MOV:
7060 {
7061 uint64_t sr=((is32>>s1)&1LL);
7062 is32&=~(1LL<<rt);
7063 is32|=sr<<rt;
7064 }
7065 break;
7066 case SHIFT:
7067 if(op2>=0x14&&op2<=0x17) is32&=~(1LL<<rt); // DSLLV/DSRLV/DSRAV
7068 else is32|=1LL<<rt; // SLLV/SRLV/SRAV
7069 break;
7070 case SHIFTIMM:
7071 is32|=1LL<<rt;
7072 // DSLL/DSRL/DSRA/DSLL32/DSRL32 but not DSRA32 have 64-bit result
7073 if(op2>=0x38&&op2<0x3f) is32&=~(1LL<<rt);
7074 break;
7075 case COP0:
7076 if(op2==0) is32|=1LL<<rt; // MFC0
7077 break;
7078 case COP1:
b9b61529 7079 case COP2:
57871462 7080 if(op2==0) is32|=1LL<<rt; // MFC1
7081 if(op2==1) is32&=~(1LL<<rt); // DMFC1
7082 if(op2==2) is32|=1LL<<rt; // CFC1
7083 break;
7084 case C1LS:
b9b61529 7085 case C2LS:
57871462 7086 break;
7087 case FLOAT:
7088 case FCONV:
7089 break;
7090 case FCOMP:
7091 break;
b9b61529 7092 case C2OP:
57871462 7093 case SYSCALL:
7139f3c8 7094 case HLECALL:
57871462 7095 break;
7096 default:
7097 break;
7098 }
7099 is32|=1;
7100 p32[i]=is32;
7101
7102 if(i>0)
7103 {
7104 if(itype[i-1]==UJUMP||itype[i-1]==RJUMP||(source[i-1]>>16)==0x1000)
7105 {
7106 if(rt1[i-1]==31) // JAL/JALR
7107 {
7108 // Subroutine call will return here, don't alloc any registers
7109 is32=1;
7110 }
7111 else if(i+1<slen)
7112 {
7113 // Internal branch will jump here, match registers to caller
7114 is32=0x3FFFFFFFFLL;
7115 }
7116 }
7117 }
7118 }
7119}
7120
7121// Identify registers which may be assumed to contain 32-bit values
7122// and where optimizations will rely on this.
7123// This is used to determine whether backward branches can safely
7124// jump to a location with 64-bit values in registers.
7125static void provisional_r32()
7126{
7127 u_int r32=0;
7128 int i;
7129
7130 for (i=slen-1;i>=0;i--)
7131 {
7132 int hr;
7133 if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
7134 {
7135 if(ba[i]<start || ba[i]>=(start+slen*4))
7136 {
7137 // Branch out of this block, don't need anything
7138 r32=0;
7139 }
7140 else
7141 {
7142 // Internal branch
7143 // Need whatever matches the target
7144 // (and doesn't get overwritten by the delay slot instruction)
7145 r32=0;
7146 int t=(ba[i]-start)>>2;
7147 if(ba[i]>start+i*4) {
7148 // Forward branch
7149 //if(!(requires_32bit[t]&~regs[i].was32))
7150 // r32|=requires_32bit[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
7151 if(!(pr32[t]&~regs[i].was32))
7152 r32|=pr32[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
7153 }else{
7154 // Backward branch
7155 if(!(regs[t].was32&~unneeded_reg_upper[t]&~regs[i].was32))
7156 r32|=regs[t].was32&~unneeded_reg_upper[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
7157 }
7158 }
7159 // Conditional branch may need registers for following instructions
7160 if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000)
7161 {
7162 if(i<slen-2) {
7163 //r32|=requires_32bit[i+2];
7164 r32|=pr32[i+2];
7165 r32&=regs[i].was32;
7166 // Mark this address as a branch target since it may be called
7167 // upon return from interrupt
7168 //bt[i+2]=1;
7169 }
7170 }
7171 // Merge in delay slot
7172 if(!likely[i]) {
7173 // These are overwritten unless the branch is "likely"
7174 // and the delay slot is nullified if not taken
7175 r32&=~(1LL<<rt1[i+1]);
7176 r32&=~(1LL<<rt2[i+1]);
7177 }
7178 // Assume these are needed (delay slot)
7179 if(us1[i+1]>0)
7180 {
7181 if((regs[i].was32>>us1[i+1])&1) r32|=1LL<<us1[i+1];
7182 }
7183 if(us2[i+1]>0)
7184 {
7185 if((regs[i].was32>>us2[i+1])&1) r32|=1LL<<us2[i+1];
7186 }
7187 if(dep1[i+1]&&!((unneeded_reg_upper[i]>>dep1[i+1])&1))
7188 {
7189 if((regs[i].was32>>dep1[i+1])&1) r32|=1LL<<dep1[i+1];
7190 }
7191 if(dep2[i+1]&&!((unneeded_reg_upper[i]>>dep2[i+1])&1))
7192 {
7193 if((regs[i].was32>>dep2[i+1])&1) r32|=1LL<<dep2[i+1];
7194 }
7195 }
1e973cb0 7196 else if(itype[i]==SYSCALL||itype[i]==HLECALL||itype[i]==INTCALL)
57871462 7197 {
7198 // SYSCALL instruction (software interrupt)
7199 r32=0;
7200 }
7201 else if(itype[i]==COP0 && (source[i]&0x3f)==0x18)
7202 {
7203 // ERET instruction (return from interrupt)
7204 r32=0;
7205 }
7206 // Check 32 bits
7207 r32&=~(1LL<<rt1[i]);
7208 r32&=~(1LL<<rt2[i]);
7209 if(us1[i]>0)
7210 {
7211 if((regs[i].was32>>us1[i])&1) r32|=1LL<<us1[i];
7212 }
7213 if(us2[i]>0)
7214 {
7215 if((regs[i].was32>>us2[i])&1) r32|=1LL<<us2[i];
7216 }
7217 if(dep1[i]&&!((unneeded_reg_upper[i]>>dep1[i])&1))
7218 {
7219 if((regs[i].was32>>dep1[i])&1) r32|=1LL<<dep1[i];
7220 }
7221 if(dep2[i]&&!((unneeded_reg_upper[i]>>dep2[i])&1))
7222 {
7223 if((regs[i].was32>>dep2[i])&1) r32|=1LL<<dep2[i];
7224 }
7225 //requires_32bit[i]=r32;
7226 pr32[i]=r32;
7227
7228 // Dirty registers which are 32-bit, require 32-bit input
7229 // as they will be written as 32-bit values
7230 for(hr=0;hr<HOST_REGS;hr++)
7231 {
7232 if(regs[i].regmap_entry[hr]>0&&regs[i].regmap_entry[hr]<64) {
7233 if((regs[i].was32>>regs[i].regmap_entry[hr])&(regs[i].wasdirty>>hr)&1) {
7234 if(!((unneeded_reg_upper[i]>>regs[i].regmap_entry[hr])&1))
7235 pr32[i]|=1LL<<regs[i].regmap_entry[hr];
7236 //requires_32bit[i]|=1LL<<regs[i].regmap_entry[hr];
7237 }
7238 }
7239 }
7240 }
7241}
7242
7243// Write back dirty registers as soon as we will no longer modify them,
7244// so that we don't end up with lots of writes at the branches.
7245void clean_registers(int istart,int iend,int wr)
7246{
7247 int i;
7248 int r;
7249 u_int will_dirty_i,will_dirty_next,temp_will_dirty;
7250 u_int wont_dirty_i,wont_dirty_next,temp_wont_dirty;
7251 if(iend==slen-1) {
7252 will_dirty_i=will_dirty_next=0;
7253 wont_dirty_i=wont_dirty_next=0;
7254 }else{
7255 will_dirty_i=will_dirty_next=will_dirty[iend+1];
7256 wont_dirty_i=wont_dirty_next=wont_dirty[iend+1];
7257 }
7258 for (i=iend;i>=istart;i--)
7259 {
7260 if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
7261 {
7262 if(ba[i]<start || ba[i]>=(start+slen*4))
7263 {
7264 // Branch out of this block, flush all regs
7265 if(itype[i]==RJUMP||itype[i]==UJUMP||(source[i]>>16)==0x1000)
7266 {
7267 // Unconditional branch
7268 will_dirty_i=0;
7269 wont_dirty_i=0;
7270 // Merge in delay slot (will dirty)
7271 for(r=0;r<HOST_REGS;r++) {
7272 if(r!=EXCLUDE_REG) {
7273 if((branch_regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7274 if((branch_regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7275 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7276 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7277 if((branch_regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7278 if(branch_regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7279 if(branch_regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7280 if((regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7281 if((regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7282 if((regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7283 if((regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7284 if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7285 if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7286 if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7287 }
7288 }
7289 }
7290 else
7291 {
7292 // Conditional branch
7293 will_dirty_i=0;
7294 wont_dirty_i=wont_dirty_next;
7295 // Merge in delay slot (will dirty)
7296 for(r=0;r<HOST_REGS;r++) {
7297 if(r!=EXCLUDE_REG) {
7298 if(!likely[i]) {
7299 // Might not dirty if likely branch is not taken
7300 if((branch_regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7301 if((branch_regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7302 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7303 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7304 if((branch_regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7305 if(branch_regs[i].regmap[r]==0) will_dirty_i&=~(1<<r);
7306 if(branch_regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7307 //if((regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7308 //if((regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7309 if((regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7310 if((regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7311 if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7312 if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7313 if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7314 }
7315 }
7316 }
7317 }
7318 // Merge in delay slot (wont dirty)
7319 for(r=0;r<HOST_REGS;r++) {
7320 if(r!=EXCLUDE_REG) {
7321 if((regs[i].regmap[r]&63)==rt1[i]) wont_dirty_i|=1<<r;
7322 if((regs[i].regmap[r]&63)==rt2[i]) wont_dirty_i|=1<<r;
7323 if((regs[i].regmap[r]&63)==rt1[i+1]) wont_dirty_i|=1<<r;
7324 if((regs[i].regmap[r]&63)==rt2[i+1]) wont_dirty_i|=1<<r;
7325 if(regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
7326 if((branch_regs[i].regmap[r]&63)==rt1[i]) wont_dirty_i|=1<<r;
7327 if((branch_regs[i].regmap[r]&63)==rt2[i]) wont_dirty_i|=1<<r;
7328 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) wont_dirty_i|=1<<r;
7329 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) wont_dirty_i|=1<<r;
7330 if(branch_regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
7331 }
7332 }
7333 if(wr) {
7334 #ifndef DESTRUCTIVE_WRITEBACK
7335 branch_regs[i].dirty&=wont_dirty_i;
7336 #endif
7337 branch_regs[i].dirty|=will_dirty_i;
7338 }
7339 }
7340 else
7341 {
7342 // Internal branch
7343 if(ba[i]<=start+i*4) {
7344 // Backward branch
7345 if(itype[i]==RJUMP||itype[i]==UJUMP||(source[i]>>16)==0x1000)
7346 {
7347 // Unconditional branch
7348 temp_will_dirty=0;
7349 temp_wont_dirty=0;
7350 // Merge in delay slot (will dirty)
7351 for(r=0;r<HOST_REGS;r++) {
7352 if(r!=EXCLUDE_REG) {
7353 if((branch_regs[i].regmap[r]&63)==rt1[i]) temp_will_dirty|=1<<r;
7354 if((branch_regs[i].regmap[r]&63)==rt2[i]) temp_will_dirty|=1<<r;
7355 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) temp_will_dirty|=1<<r;
7356 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) temp_will_dirty|=1<<r;
7357 if((branch_regs[i].regmap[r]&63)>33) temp_will_dirty&=~(1<<r);
7358 if(branch_regs[i].regmap[r]<=0) temp_will_dirty&=~(1<<r);
7359 if(branch_regs[i].regmap[r]==CCREG) temp_will_dirty|=1<<r;
7360 if((regs[i].regmap[r]&63)==rt1[i]) temp_will_dirty|=1<<r;
7361 if((regs[i].regmap[r]&63)==rt2[i]) temp_will_dirty|=1<<r;
7362 if((regs[i].regmap[r]&63)==rt1[i+1]) temp_will_dirty|=1<<r;
7363 if((regs[i].regmap[r]&63)==rt2[i+1]) temp_will_dirty|=1<<r;
7364 if((regs[i].regmap[r]&63)>33) temp_will_dirty&=~(1<<r);
7365 if(regs[i].regmap[r]<=0) temp_will_dirty&=~(1<<r);
7366 if(regs[i].regmap[r]==CCREG) temp_will_dirty|=1<<r;
7367 }
7368 }
7369 } else {
7370 // Conditional branch (not taken case)
7371 temp_will_dirty=will_dirty_next;
7372 temp_wont_dirty=wont_dirty_next;
7373 // Merge in delay slot (will dirty)
7374 for(r=0;r<HOST_REGS;r++) {
7375 if(r!=EXCLUDE_REG) {
7376 if(!likely[i]) {
7377 // Will not dirty if likely branch is not taken
7378 if((branch_regs[i].regmap[r]&63)==rt1[i]) temp_will_dirty|=1<<r;
7379 if((branch_regs[i].regmap[r]&63)==rt2[i]) temp_will_dirty|=1<<r;
7380 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) temp_will_dirty|=1<<r;
7381 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) temp_will_dirty|=1<<r;
7382 if((branch_regs[i].regmap[r]&63)>33) temp_will_dirty&=~(1<<r);
7383 if(branch_regs[i].regmap[r]==0) temp_will_dirty&=~(1<<r);
7384 if(branch_regs[i].regmap[r]==CCREG) temp_will_dirty|=1<<r;
7385 //if((regs[i].regmap[r]&63)==rt1[i]) temp_will_dirty|=1<<r;
7386 //if((regs[i].regmap[r]&63)==rt2[i]) temp_will_dirty|=1<<r;
7387 if((regs[i].regmap[r]&63)==rt1[i+1]) temp_will_dirty|=1<<r;
7388 if((regs[i].regmap[r]&63)==rt2[i+1]) temp_will_dirty|=1<<r;
7389 if((regs[i].regmap[r]&63)>33) temp_will_dirty&=~(1<<r);
7390 if(regs[i].regmap[r]<=0) temp_will_dirty&=~(1<<r);
7391 if(regs[i].regmap[r]==CCREG) temp_will_dirty|=1<<r;
7392 }
7393 }
7394 }
7395 }
7396 // Merge in delay slot (wont dirty)
7397 for(r=0;r<HOST_REGS;r++) {
7398 if(r!=EXCLUDE_REG) {
7399 if((regs[i].regmap[r]&63)==rt1[i]) temp_wont_dirty|=1<<r;
7400 if((regs[i].regmap[r]&63)==rt2[i]) temp_wont_dirty|=1<<r;
7401 if((regs[i].regmap[r]&63)==rt1[i+1]) temp_wont_dirty|=1<<r;
7402 if((regs[i].regmap[r]&63)==rt2[i+1]) temp_wont_dirty|=1<<r;
7403 if(regs[i].regmap[r]==CCREG) temp_wont_dirty|=1<<r;
7404 if((branch_regs[i].regmap[r]&63)==rt1[i]) temp_wont_dirty|=1<<r;
7405 if((branch_regs[i].regmap[r]&63)==rt2[i]) temp_wont_dirty|=1<<r;
7406 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) temp_wont_dirty|=1<<r;
7407 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) temp_wont_dirty|=1<<r;
7408 if(branch_regs[i].regmap[r]==CCREG) temp_wont_dirty|=1<<r;
7409 }
7410 }
7411 // Deal with changed mappings
7412 if(i<iend) {
7413 for(r=0;r<HOST_REGS;r++) {
7414 if(r!=EXCLUDE_REG) {
7415 if(regs[i].regmap[r]!=regmap_pre[i][r]) {
7416 temp_will_dirty&=~(1<<r);
7417 temp_wont_dirty&=~(1<<r);
7418 if((regmap_pre[i][r]&63)>0 && (regmap_pre[i][r]&63)<34) {
7419 temp_will_dirty|=((unneeded_reg[i]>>(regmap_pre[i][r]&63))&1)<<r;
7420 temp_wont_dirty|=((unneeded_reg[i]>>(regmap_pre[i][r]&63))&1)<<r;
7421 } else {
7422 temp_will_dirty|=1<<r;
7423 temp_wont_dirty|=1<<r;
7424 }
7425 }
7426 }
7427 }
7428 }
7429 if(wr) {
7430 will_dirty[i]=temp_will_dirty;
7431 wont_dirty[i]=temp_wont_dirty;
7432 clean_registers((ba[i]-start)>>2,i-1,0);
7433 }else{
7434 // Limit recursion. It can take an excessive amount
7435 // of time if there are a lot of nested loops.
7436 will_dirty[(ba[i]-start)>>2]=0;
7437 wont_dirty[(ba[i]-start)>>2]=-1;
7438 }
7439 }
7440 /*else*/ if(1)
7441 {
7442 if(itype[i]==RJUMP||itype[i]==UJUMP||(source[i]>>16)==0x1000)
7443 {
7444 // Unconditional branch
7445 will_dirty_i=0;
7446 wont_dirty_i=0;
7447 //if(ba[i]>start+i*4) { // Disable recursion (for debugging)
7448 for(r=0;r<HOST_REGS;r++) {
7449 if(r!=EXCLUDE_REG) {
7450 if(branch_regs[i].regmap[r]==regs[(ba[i]-start)>>2].regmap_entry[r]) {
7451 will_dirty_i|=will_dirty[(ba[i]-start)>>2]&(1<<r);
7452 wont_dirty_i|=wont_dirty[(ba[i]-start)>>2]&(1<<r);
7453 }
7454 }
7455 }
7456 //}
7457 // Merge in delay slot
7458 for(r=0;r<HOST_REGS;r++) {
7459 if(r!=EXCLUDE_REG) {
7460 if((branch_regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7461 if((branch_regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7462 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7463 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7464 if((branch_regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7465 if(branch_regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7466 if(branch_regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7467 if((regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7468 if((regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7469 if((regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7470 if((regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7471 if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7472 if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7473 if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7474 }
7475 }
7476 } else {
7477 // Conditional branch
7478 will_dirty_i=will_dirty_next;
7479 wont_dirty_i=wont_dirty_next;
7480 //if(ba[i]>start+i*4) { // Disable recursion (for debugging)
7481 for(r=0;r<HOST_REGS;r++) {
7482 if(r!=EXCLUDE_REG) {
7483 if(branch_regs[i].regmap[r]==regs[(ba[i]-start)>>2].regmap_entry[r]) {
7484 will_dirty_i&=will_dirty[(ba[i]-start)>>2]&(1<<r);
7485 wont_dirty_i|=wont_dirty[(ba[i]-start)>>2]&(1<<r);
7486 }
7487 else
7488 {
7489 will_dirty_i&=~(1<<r);
7490 }
7491 // Treat delay slot as part of branch too
7492 /*if(regs[i+1].regmap[r]==regs[(ba[i]-start)>>2].regmap_entry[r]) {
7493 will_dirty[i+1]&=will_dirty[(ba[i]-start)>>2]&(1<<r);
7494 wont_dirty[i+1]|=wont_dirty[(ba[i]-start)>>2]&(1<<r);
7495 }
7496 else
7497 {
7498 will_dirty[i+1]&=~(1<<r);
7499 }*/
7500 }
7501 }
7502 //}
7503 // Merge in delay slot
7504 for(r=0;r<HOST_REGS;r++) {
7505 if(r!=EXCLUDE_REG) {
7506 if(!likely[i]) {
7507 // Might not dirty if likely branch is not taken
7508 if((branch_regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7509 if((branch_regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7510 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7511 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7512 if((branch_regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7513 if(branch_regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7514 if(branch_regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7515 //if((regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7516 //if((regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7517 if((regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7518 if((regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7519 if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7520 if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7521 if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7522 }
7523 }
7524 }
7525 }
7526 // Merge in delay slot
7527 for(r=0;r<HOST_REGS;r++) {
7528 if(r!=EXCLUDE_REG) {
7529 if((regs[i].regmap[r]&63)==rt1[i]) wont_dirty_i|=1<<r;
7530 if((regs[i].regmap[r]&63)==rt2[i]) wont_dirty_i|=1<<r;
7531 if((regs[i].regmap[r]&63)==rt1[i+1]) wont_dirty_i|=1<<r;
7532 if((regs[i].regmap[r]&63)==rt2[i+1]) wont_dirty_i|=1<<r;
7533 if(regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
7534 if((branch_regs[i].regmap[r]&63)==rt1[i]) wont_dirty_i|=1<<r;
7535 if((branch_regs[i].regmap[r]&63)==rt2[i]) wont_dirty_i|=1<<r;
7536 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) wont_dirty_i|=1<<r;
7537 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) wont_dirty_i|=1<<r;
7538 if(branch_regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
7539 }
7540 }
7541 if(wr) {
7542 #ifndef DESTRUCTIVE_WRITEBACK
7543 branch_regs[i].dirty&=wont_dirty_i;
7544 #endif
7545 branch_regs[i].dirty|=will_dirty_i;
7546 }
7547 }
7548 }
7549 }
1e973cb0 7550 else if(itype[i]==SYSCALL||itype[i]==HLECALL||itype[i]==INTCALL)
57871462 7551 {
7552 // SYSCALL instruction (software interrupt)
7553 will_dirty_i=0;
7554 wont_dirty_i=0;
7555 }
7556 else if(itype[i]==COP0 && (source[i]&0x3f)==0x18)
7557 {
7558 // ERET instruction (return from interrupt)
7559 will_dirty_i=0;
7560 wont_dirty_i=0;
7561 }
7562 will_dirty_next=will_dirty_i;
7563 wont_dirty_next=wont_dirty_i;
7564 for(r=0;r<HOST_REGS;r++) {
7565 if(r!=EXCLUDE_REG) {
7566 if((regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7567 if((regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7568 if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7569 if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7570 if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7571 if((regs[i].regmap[r]&63)==rt1[i]) wont_dirty_i|=1<<r;
7572 if((regs[i].regmap[r]&63)==rt2[i]) wont_dirty_i|=1<<r;
7573 if(regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
7574 if(i>istart) {
7575 if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&itype[i]!=CJUMP&&itype[i]!=SJUMP&&itype[i]!=FJUMP)
7576 {
7577 // Don't store a register immediately after writing it,
7578 // may prevent dual-issue.
7579 if((regs[i].regmap[r]&63)==rt1[i-1]) wont_dirty_i|=1<<r;
7580 if((regs[i].regmap[r]&63)==rt2[i-1]) wont_dirty_i|=1<<r;
7581 }
7582 }
7583 }
7584 }
7585 // Save it
7586 will_dirty[i]=will_dirty_i;
7587 wont_dirty[i]=wont_dirty_i;
7588 // Mark registers that won't be dirtied as not dirty
7589 if(wr) {
7590 /*printf("wr (%d,%d) %x will:",istart,iend,start+i*4);
7591 for(r=0;r<HOST_REGS;r++) {
7592 if((will_dirty_i>>r)&1) {
7593 printf(" r%d",r);
7594 }
7595 }
7596 printf("\n");*/
7597
7598 //if(i==istart||(itype[i-1]!=RJUMP&&itype[i-1]!=UJUMP&&itype[i-1]!=CJUMP&&itype[i-1]!=SJUMP&&itype[i-1]!=FJUMP)) {
7599 regs[i].dirty|=will_dirty_i;
7600 #ifndef DESTRUCTIVE_WRITEBACK
7601 regs[i].dirty&=wont_dirty_i;
7602 if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
7603 {
7604 if(i<iend-1&&itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000) {
7605 for(r=0;r<HOST_REGS;r++) {
7606 if(r!=EXCLUDE_REG) {
7607 if(regs[i].regmap[r]==regmap_pre[i+2][r]) {
7608 regs[i+2].wasdirty&=wont_dirty_i|~(1<<r);
7609 }else {/*printf("i: %x (%d) mismatch(+2): %d\n",start+i*4,i,r);/*assert(!((wont_dirty_i>>r)&1));*/}
7610 }
7611 }
7612 }
7613 }
7614 else
7615 {
7616 if(i<iend) {
7617 for(r=0;r<HOST_REGS;r++) {
7618 if(r!=EXCLUDE_REG) {
7619 if(regs[i].regmap[r]==regmap_pre[i+1][r]) {
7620 regs[i+1].wasdirty&=wont_dirty_i|~(1<<r);
7621 }else {/*printf("i: %x (%d) mismatch(+1): %d\n",start+i*4,i,r);/*assert(!((wont_dirty_i>>r)&1));*/}
7622 }
7623 }
7624 }
7625 }
7626 #endif
7627 //}
7628 }
7629 // Deal with changed mappings
7630 temp_will_dirty=will_dirty_i;
7631 temp_wont_dirty=wont_dirty_i;
7632 for(r=0;r<HOST_REGS;r++) {
7633 if(r!=EXCLUDE_REG) {
7634 int nr;
7635 if(regs[i].regmap[r]==regmap_pre[i][r]) {
7636 if(wr) {
7637 #ifndef DESTRUCTIVE_WRITEBACK
7638 regs[i].wasdirty&=wont_dirty_i|~(1<<r);
7639 #endif
7640 regs[i].wasdirty|=will_dirty_i&(1<<r);
7641 }
7642 }
7643 else if((nr=get_reg(regs[i].regmap,regmap_pre[i][r]))>=0) {
7644 // Register moved to a different register
7645 will_dirty_i&=~(1<<r);
7646 wont_dirty_i&=~(1<<r);
7647 will_dirty_i|=((temp_will_dirty>>nr)&1)<<r;
7648 wont_dirty_i|=((temp_wont_dirty>>nr)&1)<<r;
7649 if(wr) {
7650 #ifndef DESTRUCTIVE_WRITEBACK
7651 regs[i].wasdirty&=wont_dirty_i|~(1<<r);
7652 #endif
7653 regs[i].wasdirty|=will_dirty_i&(1<<r);
7654 }
7655 }
7656 else {
7657 will_dirty_i&=~(1<<r);
7658 wont_dirty_i&=~(1<<r);
7659 if((regmap_pre[i][r]&63)>0 && (regmap_pre[i][r]&63)<34) {
7660 will_dirty_i|=((unneeded_reg[i]>>(regmap_pre[i][r]&63))&1)<<r;
7661 wont_dirty_i|=((unneeded_reg[i]>>(regmap_pre[i][r]&63))&1)<<r;
7662 } else {
7663 wont_dirty_i|=1<<r;
7664 /*printf("i: %x (%d) mismatch: %d\n",start+i*4,i,r);/*assert(!((will_dirty>>r)&1));*/
7665 }
7666 }
7667 }
7668 }
7669 }
7670}
7671
7672 /* disassembly */
7673void disassemble_inst(int i)
7674{
7675 if (bt[i]) printf("*"); else printf(" ");
7676 switch(itype[i]) {
7677 case UJUMP:
7678 printf (" %x: %s %8x\n",start+i*4,insn[i],ba[i]);break;
7679 case CJUMP:
7680 printf (" %x: %s r%d,r%d,%8x\n",start+i*4,insn[i],rs1[i],rs2[i],i?start+i*4+4+((signed int)((unsigned int)source[i]<<16)>>14):*ba);break;
7681 case SJUMP:
7682 printf (" %x: %s r%d,%8x\n",start+i*4,insn[i],rs1[i],start+i*4+4+((signed int)((unsigned int)source[i]<<16)>>14));break;
7683 case FJUMP:
7684 printf (" %x: %s %8x\n",start+i*4,insn[i],ba[i]);break;
7685 case RJUMP:
74426039 7686 if (opcode[i]==0x9&&rt1[i]!=31)
5067f341 7687 printf (" %x: %s r%d,r%d\n",start+i*4,insn[i],rt1[i],rs1[i]);
7688 else
7689 printf (" %x: %s r%d\n",start+i*4,insn[i],rs1[i]);
7690 break;
57871462 7691 case SPAN:
7692 printf (" %x: %s (pagespan) r%d,r%d,%8x\n",start+i*4,insn[i],rs1[i],rs2[i],ba[i]);break;
7693 case IMM16:
7694 if(opcode[i]==0xf) //LUI
7695 printf (" %x: %s r%d,%4x0000\n",start+i*4,insn[i],rt1[i],imm[i]&0xffff);
7696 else
7697 printf (" %x: %s r%d,r%d,%d\n",start+i*4,insn[i],rt1[i],rs1[i],imm[i]);
7698 break;
7699 case LOAD:
7700 case LOADLR:
7701 printf (" %x: %s r%d,r%d+%x\n",start+i*4,insn[i],rt1[i],rs1[i],imm[i]);
7702 break;
7703 case STORE:
7704 case STORELR:
7705 printf (" %x: %s r%d,r%d+%x\n",start+i*4,insn[i],rs2[i],rs1[i],imm[i]);
7706 break;
7707 case ALU:
7708 case SHIFT:
7709 printf (" %x: %s r%d,r%d,r%d\n",start+i*4,insn[i],rt1[i],rs1[i],rs2[i]);
7710 break;
7711 case MULTDIV:
7712 printf (" %x: %s r%d,r%d\n",start+i*4,insn[i],rs1[i],rs2[i]);
7713 break;
7714 case SHIFTIMM:
7715 printf (" %x: %s r%d,r%d,%d\n",start+i*4,insn[i],rt1[i],rs1[i],imm[i]);
7716 break;
7717 case MOV:
7718 if((opcode2[i]&0x1d)==0x10)
7719 printf (" %x: %s r%d\n",start+i*4,insn[i],rt1[i]);
7720 else if((opcode2[i]&0x1d)==0x11)
7721 printf (" %x: %s r%d\n",start+i*4,insn[i],rs1[i]);
7722 else
7723 printf (" %x: %s\n",start+i*4,insn[i]);
7724 break;
7725 case COP0:
7726 if(opcode2[i]==0)
7727 printf (" %x: %s r%d,cpr0[%d]\n",start+i*4,insn[i],rt1[i],(source[i]>>11)&0x1f); // MFC0
7728 else if(opcode2[i]==4)
7729 printf (" %x: %s r%d,cpr0[%d]\n",start+i*4,insn[i],rs1[i],(source[i]>>11)&0x1f); // MTC0
7730 else printf (" %x: %s\n",start+i*4,insn[i]);
7731 break;
7732 case COP1:
7733 if(opcode2[i]<3)
7734 printf (" %x: %s r%d,cpr1[%d]\n",start+i*4,insn[i],rt1[i],(source[i]>>11)&0x1f); // MFC1
7735 else if(opcode2[i]>3)
7736 printf (" %x: %s r%d,cpr1[%d]\n",start+i*4,insn[i],rs1[i],(source[i]>>11)&0x1f); // MTC1
7737 else printf (" %x: %s\n",start+i*4,insn[i]);
7738 break;
b9b61529 7739 case COP2:
7740 if(opcode2[i]<3)
7741 printf (" %x: %s r%d,cpr2[%d]\n",start+i*4,insn[i],rt1[i],(source[i]>>11)&0x1f); // MFC2
7742 else if(opcode2[i]>3)
7743 printf (" %x: %s r%d,cpr2[%d]\n",start+i*4,insn[i],rs1[i],(source[i]>>11)&0x1f); // MTC2
7744 else printf (" %x: %s\n",start+i*4,insn[i]);
7745 break;
57871462 7746 case C1LS:
7747 printf (" %x: %s cpr1[%d],r%d+%x\n",start+i*4,insn[i],(source[i]>>16)&0x1f,rs1[i],imm[i]);
7748 break;
b9b61529 7749 case C2LS:
7750 printf (" %x: %s cpr2[%d],r%d+%x\n",start+i*4,insn[i],(source[i]>>16)&0x1f,rs1[i],imm[i]);
7751 break;
1e973cb0 7752 case INTCALL:
7753 printf (" %x: %s (INTCALL)\n",start+i*4,insn[i]);
7754 break;
57871462 7755 default:
7756 //printf (" %s %8x\n",insn[i],source[i]);
7757 printf (" %x: %s\n",start+i*4,insn[i]);
7758 }
7759}
7760
dc990066 7761// clear the state completely, instead of just marking
7762// things invalid like invalidate_all_pages() does
7763void new_dynarec_clear_full()
57871462 7764{
57871462 7765 int n;
35775df7 7766 out=(u_char *)BASE_ADDR;
7767 memset(invalid_code,1,sizeof(invalid_code));
7768 memset(hash_table,0xff,sizeof(hash_table));
57871462 7769 memset(mini_ht,-1,sizeof(mini_ht));
7770 memset(restore_candidate,0,sizeof(restore_candidate));
dc990066 7771 memset(shadow,0,sizeof(shadow));
57871462 7772 copy=shadow;
7773 expirep=16384; // Expiry pointer, +2 blocks
7774 pending_exception=0;
7775 literalcount=0;
57871462 7776 stop_after_jal=0;
7777 // TLB
af4ee1fe 7778#ifndef DISABLE_TLB
57871462 7779 using_tlb=0;
af4ee1fe 7780#endif
dadf55f2 7781 sp_in_mirror=0;
57871462 7782 for(n=0;n<524288;n++) // 0 .. 0x7FFFFFFF
7783 memory_map[n]=-1;
7784 for(n=524288;n<526336;n++) // 0x80000000 .. 0x807FFFFF
7785 memory_map[n]=((u_int)rdram-0x80000000)>>2;
7786 for(n=526336;n<1048576;n++) // 0x80800000 .. 0xFFFFFFFF
7787 memory_map[n]=-1;
dc990066 7788 for(n=0;n<4096;n++) ll_clear(jump_in+n);
7789 for(n=0;n<4096;n++) ll_clear(jump_out+n);
7790 for(n=0;n<4096;n++) ll_clear(jump_dirty+n);
7791}
7792
7793void new_dynarec_init()
7794{
7795 printf("Init new dynarec\n");
7796 out=(u_char *)BASE_ADDR;
7797 if (mmap (out, 1<<TARGET_SIZE_2,
7798 PROT_READ | PROT_WRITE | PROT_EXEC,
7799 MAP_FIXED | MAP_PRIVATE | MAP_ANONYMOUS,
7800 -1, 0) <= 0) {printf("mmap() failed\n");}
7801#ifdef MUPEN64
7802 rdword=&readmem_dword;
7803 fake_pc.f.r.rs=&readmem_dword;
7804 fake_pc.f.r.rt=&readmem_dword;
7805 fake_pc.f.r.rd=&readmem_dword;
7806#endif
7807 int n;
7808 new_dynarec_clear_full();
7809#ifdef HOST_IMM8
7810 // Copy this into local area so we don't have to put it in every literal pool
7811 invc_ptr=invalid_code;
7812#endif
24385cae 7813#ifdef MUPEN64
57871462 7814 for(n=0;n<0x8000;n++) { // 0 .. 0x7FFFFFFF
7815 writemem[n] = write_nomem_new;
7816 writememb[n] = write_nomemb_new;
7817 writememh[n] = write_nomemh_new;
24385cae 7818#ifndef FORCE32
57871462 7819 writememd[n] = write_nomemd_new;
24385cae 7820#endif
57871462 7821 readmem[n] = read_nomem_new;
7822 readmemb[n] = read_nomemb_new;
7823 readmemh[n] = read_nomemh_new;
24385cae 7824#ifndef FORCE32
57871462 7825 readmemd[n] = read_nomemd_new;
24385cae 7826#endif
57871462 7827 }
7828 for(n=0x8000;n<0x8080;n++) { // 0x80000000 .. 0x807FFFFF
7829 writemem[n] = write_rdram_new;
7830 writememb[n] = write_rdramb_new;
7831 writememh[n] = write_rdramh_new;
24385cae 7832#ifndef FORCE32
57871462 7833 writememd[n] = write_rdramd_new;
24385cae 7834#endif
57871462 7835 }
7836 for(n=0xC000;n<0x10000;n++) { // 0xC0000000 .. 0xFFFFFFFF
7837 writemem[n] = write_nomem_new;
7838 writememb[n] = write_nomemb_new;
7839 writememh[n] = write_nomemh_new;
24385cae 7840#ifndef FORCE32
57871462 7841 writememd[n] = write_nomemd_new;
24385cae 7842#endif
57871462 7843 readmem[n] = read_nomem_new;
7844 readmemb[n] = read_nomemb_new;
7845 readmemh[n] = read_nomemh_new;
24385cae 7846#ifndef FORCE32
57871462 7847 readmemd[n] = read_nomemd_new;
24385cae 7848#endif
57871462 7849 }
24385cae 7850#endif
57871462 7851 tlb_hacks();
7852 arch_init();
7853}
7854
7855void new_dynarec_cleanup()
7856{
7857 int n;
7858 if (munmap ((void *)BASE_ADDR, 1<<TARGET_SIZE_2) < 0) {printf("munmap() failed\n");}
7859 for(n=0;n<4096;n++) ll_clear(jump_in+n);
7860 for(n=0;n<4096;n++) ll_clear(jump_out+n);
7861 for(n=0;n<4096;n++) ll_clear(jump_dirty+n);
7862 #ifdef ROM_COPY
7863 if (munmap (ROM_COPY, 67108864) < 0) {printf("munmap() failed\n");}
7864 #endif
7865}
7866
7867int new_recompile_block(int addr)
7868{
7869/*
7870 if(addr==0x800cd050) {
7871 int block;
7872 for(block=0x80000;block<0x80800;block++) invalidate_block(block);
7873 int n;
7874 for(n=0;n<=2048;n++) ll_clear(jump_dirty+n);
7875 }
7876*/
7877 //if(Count==365117028) tracedebug=1;
7878 assem_debug("NOTCOMPILED: addr = %x -> %x\n", (int)addr, (int)out);
7879 //printf("NOTCOMPILED: addr = %x -> %x\n", (int)addr, (int)out);
7880 //printf("TRACE: count=%d next=%d (compile %x)\n",Count,next_interupt,addr);
7881 //if(debug)
7882 //printf("TRACE: count=%d next=%d (checksum %x)\n",Count,next_interupt,mchecksum());
7883 //printf("fpu mapping=%x enabled=%x\n",(Status & 0x04000000)>>26,(Status & 0x20000000)>>29);
7884 /*if(Count>=312978186) {
7885 rlist();
7886 }*/
7887 //rlist();
7888 start = (u_int)addr&~3;
7889 //assert(((u_int)addr&1)==0);
7139f3c8 7890#ifdef PCSX
dadf55f2 7891 if(!sp_in_mirror&&(signed int)(psxRegs.GPR.n.sp&0xffe00000)>0x80200000&&
7892 0x10000<=psxRegs.GPR.n.sp&&(psxRegs.GPR.n.sp&~0xe0e00000)<RAM_SIZE) {
c2e3bd42 7893 printf("SP hack enabled (%08x), @%08x\n", psxRegs.GPR.n.sp, psxRegs.pc);
dadf55f2 7894 sp_in_mirror=1;
7895 }
9ad4d757 7896 if (Config.HLE && start == 0x80001000) // hlecall
560e4a12 7897 {
7139f3c8 7898 // XXX: is this enough? Maybe check hleSoftCall?
bb5285ef 7899 u_int beginning=(u_int)out;
7139f3c8 7900 u_int page=get_page(start);
7139f3c8 7901 invalid_code[start>>12]=0;
7902 emit_movimm(start,0);
7903 emit_writeword(0,(int)&pcaddr);
bb5285ef 7904 emit_jmp((int)new_dyna_leave);
7905#ifdef __arm__
7906 __clear_cache((void *)beginning,out);
7907#endif
9ad4d757 7908 ll_add(jump_in+page,start,(void *)beginning);
7139f3c8 7909 return 0;
7910 }
560e4a12 7911 else if ((u_int)addr < 0x00200000 ||
7912 (0xa0000000 <= addr && addr < 0xa0200000)) {
7139f3c8 7913 // used for BIOS calls mostly?
560e4a12 7914 source = (u_int *)((u_int)rdram+(start&0x1fffff));
7915 pagelimit = (addr&0xa0000000)|0x00200000;
7916 }
7917 else if (!Config.HLE && (
7918/* (0x9fc00000 <= addr && addr < 0x9fc80000) ||*/
7919 (0xbfc00000 <= addr && addr < 0xbfc80000))) {
7920 // BIOS
7921 source = (u_int *)((u_int)psxR+(start&0x7ffff));
7922 pagelimit = (addr&0xfff00000)|0x80000;
7139f3c8 7923 }
7924 else
7925#endif
3d624f89 7926#ifdef MUPEN64
57871462 7927 if ((int)addr >= 0xa4000000 && (int)addr < 0xa4001000) {
7928 source = (u_int *)((u_int)SP_DMEM+start-0xa4000000);
7929 pagelimit = 0xa4001000;
7930 }
3d624f89 7931 else
7932#endif
4cb76aa4 7933 if ((int)addr >= 0x80000000 && (int)addr < 0x80000000+RAM_SIZE) {
57871462 7934 source = (u_int *)((u_int)rdram+start-0x80000000);
4cb76aa4 7935 pagelimit = 0x80000000+RAM_SIZE;
57871462 7936 }
90ae6d4e 7937#ifndef DISABLE_TLB
57871462 7938 else if ((signed int)addr >= (signed int)0xC0000000) {
7939 //printf("addr=%x mm=%x\n",(u_int)addr,(memory_map[start>>12]<<2));
7940 //if(tlb_LUT_r[start>>12])
7941 //source = (u_int *)(((int)rdram)+(tlb_LUT_r[start>>12]&0xFFFFF000)+(((int)addr)&0xFFF)-0x80000000);
7942 if((signed int)memory_map[start>>12]>=0) {
7943 source = (u_int *)((u_int)(start+(memory_map[start>>12]<<2)));
7944 pagelimit=(start+4096)&0xFFFFF000;
7945 int map=memory_map[start>>12];
7946 int i;
7947 for(i=0;i<5;i++) {
7948 //printf("start: %x next: %x\n",map,memory_map[pagelimit>>12]);
7949 if((map&0xBFFFFFFF)==(memory_map[pagelimit>>12]&0xBFFFFFFF)) pagelimit+=4096;
7950 }
7951 assem_debug("pagelimit=%x\n",pagelimit);
7952 assem_debug("mapping=%x (%x)\n",memory_map[start>>12],(memory_map[start>>12]<<2)+start);
7953 }
7954 else {
7955 assem_debug("Compile at unmapped memory address: %x \n", (int)addr);
7956 //assem_debug("start: %x next: %x\n",memory_map[start>>12],memory_map[(start+4096)>>12]);
560e4a12 7957 return -1; // Caller will invoke exception handler
57871462 7958 }
7959 //printf("source= %x\n",(int)source);
7960 }
90ae6d4e 7961#endif
57871462 7962 else {
7963 printf("Compile at bogus memory address: %x \n", (int)addr);
7964 exit(1);
7965 }
7966
7967 /* Pass 1: disassemble */
7968 /* Pass 2: register dependencies, branch targets */
7969 /* Pass 3: register allocation */
7970 /* Pass 4: branch dependencies */
7971 /* Pass 5: pre-alloc */
7972 /* Pass 6: optimize clean/dirty state */
7973 /* Pass 7: flag 32-bit registers */
7974 /* Pass 8: assembly */
7975 /* Pass 9: linker */
7976 /* Pass 10: garbage collection / free memory */
7977
7978 int i,j;
7979 int done=0;
7980 unsigned int type,op,op2;
7981
7982 //printf("addr = %x source = %x %x\n", addr,source,source[0]);
7983
7984 /* Pass 1 disassembly */
7985
7986 for(i=0;!done;i++) {
e1190b87 7987 bt[i]=0;likely[i]=0;ooo[i]=0;op2=0;
7988 minimum_free_regs[i]=0;
57871462 7989 opcode[i]=op=source[i]>>26;
7990 switch(op)
7991 {
7992 case 0x00: strcpy(insn[i],"special"); type=NI;
7993 op2=source[i]&0x3f;
7994 switch(op2)
7995 {
7996 case 0x00: strcpy(insn[i],"SLL"); type=SHIFTIMM; break;
7997 case 0x02: strcpy(insn[i],"SRL"); type=SHIFTIMM; break;
7998 case 0x03: strcpy(insn[i],"SRA"); type=SHIFTIMM; break;
7999 case 0x04: strcpy(insn[i],"SLLV"); type=SHIFT; break;
8000 case 0x06: strcpy(insn[i],"SRLV"); type=SHIFT; break;
8001 case 0x07: strcpy(insn[i],"SRAV"); type=SHIFT; break;
8002 case 0x08: strcpy(insn[i],"JR"); type=RJUMP; break;
8003 case 0x09: strcpy(insn[i],"JALR"); type=RJUMP; break;
8004 case 0x0C: strcpy(insn[i],"SYSCALL"); type=SYSCALL; break;
8005 case 0x0D: strcpy(insn[i],"BREAK"); type=OTHER; break;
8006 case 0x0F: strcpy(insn[i],"SYNC"); type=OTHER; break;
8007 case 0x10: strcpy(insn[i],"MFHI"); type=MOV; break;
8008 case 0x11: strcpy(insn[i],"MTHI"); type=MOV; break;
8009 case 0x12: strcpy(insn[i],"MFLO"); type=MOV; break;
8010 case 0x13: strcpy(insn[i],"MTLO"); type=MOV; break;
57871462 8011 case 0x18: strcpy(insn[i],"MULT"); type=MULTDIV; break;
8012 case 0x19: strcpy(insn[i],"MULTU"); type=MULTDIV; break;
8013 case 0x1A: strcpy(insn[i],"DIV"); type=MULTDIV; break;
8014 case 0x1B: strcpy(insn[i],"DIVU"); type=MULTDIV; break;
57871462 8015 case 0x20: strcpy(insn[i],"ADD"); type=ALU; break;
8016 case 0x21: strcpy(insn[i],"ADDU"); type=ALU; break;
8017 case 0x22: strcpy(insn[i],"SUB"); type=ALU; break;
8018 case 0x23: strcpy(insn[i],"SUBU"); type=ALU; break;
8019 case 0x24: strcpy(insn[i],"AND"); type=ALU; break;
8020 case 0x25: strcpy(insn[i],"OR"); type=ALU; break;
8021 case 0x26: strcpy(insn[i],"XOR"); type=ALU; break;
8022 case 0x27: strcpy(insn[i],"NOR"); type=ALU; break;
8023 case 0x2A: strcpy(insn[i],"SLT"); type=ALU; break;
8024 case 0x2B: strcpy(insn[i],"SLTU"); type=ALU; break;
57871462 8025 case 0x30: strcpy(insn[i],"TGE"); type=NI; break;
8026 case 0x31: strcpy(insn[i],"TGEU"); type=NI; break;
8027 case 0x32: strcpy(insn[i],"TLT"); type=NI; break;
8028 case 0x33: strcpy(insn[i],"TLTU"); type=NI; break;
8029 case 0x34: strcpy(insn[i],"TEQ"); type=NI; break;
8030 case 0x36: strcpy(insn[i],"TNE"); type=NI; break;
7f2607ea 8031#ifndef FORCE32
8032 case 0x14: strcpy(insn[i],"DSLLV"); type=SHIFT; break;
8033 case 0x16: strcpy(insn[i],"DSRLV"); type=SHIFT; break;
8034 case 0x17: strcpy(insn[i],"DSRAV"); type=SHIFT; break;
8035 case 0x1C: strcpy(insn[i],"DMULT"); type=MULTDIV; break;
8036 case 0x1D: strcpy(insn[i],"DMULTU"); type=MULTDIV; break;
8037 case 0x1E: strcpy(insn[i],"DDIV"); type=MULTDIV; break;
8038 case 0x1F: strcpy(insn[i],"DDIVU"); type=MULTDIV; break;
8039 case 0x2C: strcpy(insn[i],"DADD"); type=ALU; break;
8040 case 0x2D: strcpy(insn[i],"DADDU"); type=ALU; break;
8041 case 0x2E: strcpy(insn[i],"DSUB"); type=ALU; break;
8042 case 0x2F: strcpy(insn[i],"DSUBU"); type=ALU; break;
57871462 8043 case 0x38: strcpy(insn[i],"DSLL"); type=SHIFTIMM; break;
8044 case 0x3A: strcpy(insn[i],"DSRL"); type=SHIFTIMM; break;
8045 case 0x3B: strcpy(insn[i],"DSRA"); type=SHIFTIMM; break;
8046 case 0x3C: strcpy(insn[i],"DSLL32"); type=SHIFTIMM; break;
8047 case 0x3E: strcpy(insn[i],"DSRL32"); type=SHIFTIMM; break;
8048 case 0x3F: strcpy(insn[i],"DSRA32"); type=SHIFTIMM; break;
7f2607ea 8049#endif
57871462 8050 }
8051 break;
8052 case 0x01: strcpy(insn[i],"regimm"); type=NI;
8053 op2=(source[i]>>16)&0x1f;
8054 switch(op2)
8055 {
8056 case 0x00: strcpy(insn[i],"BLTZ"); type=SJUMP; break;
8057 case 0x01: strcpy(insn[i],"BGEZ"); type=SJUMP; break;
8058 case 0x02: strcpy(insn[i],"BLTZL"); type=SJUMP; break;
8059 case 0x03: strcpy(insn[i],"BGEZL"); type=SJUMP; break;
8060 case 0x08: strcpy(insn[i],"TGEI"); type=NI; break;
8061 case 0x09: strcpy(insn[i],"TGEIU"); type=NI; break;
8062 case 0x0A: strcpy(insn[i],"TLTI"); type=NI; break;
8063 case 0x0B: strcpy(insn[i],"TLTIU"); type=NI; break;
8064 case 0x0C: strcpy(insn[i],"TEQI"); type=NI; break;
8065 case 0x0E: strcpy(insn[i],"TNEI"); type=NI; break;
8066 case 0x10: strcpy(insn[i],"BLTZAL"); type=SJUMP; break;
8067 case 0x11: strcpy(insn[i],"BGEZAL"); type=SJUMP; break;
8068 case 0x12: strcpy(insn[i],"BLTZALL"); type=SJUMP; break;
8069 case 0x13: strcpy(insn[i],"BGEZALL"); type=SJUMP; break;
8070 }
8071 break;
8072 case 0x02: strcpy(insn[i],"J"); type=UJUMP; break;
8073 case 0x03: strcpy(insn[i],"JAL"); type=UJUMP; break;
8074 case 0x04: strcpy(insn[i],"BEQ"); type=CJUMP; break;
8075 case 0x05: strcpy(insn[i],"BNE"); type=CJUMP; break;
8076 case 0x06: strcpy(insn[i],"BLEZ"); type=CJUMP; break;
8077 case 0x07: strcpy(insn[i],"BGTZ"); type=CJUMP; break;
8078 case 0x08: strcpy(insn[i],"ADDI"); type=IMM16; break;
8079 case 0x09: strcpy(insn[i],"ADDIU"); type=IMM16; break;
8080 case 0x0A: strcpy(insn[i],"SLTI"); type=IMM16; break;
8081 case 0x0B: strcpy(insn[i],"SLTIU"); type=IMM16; break;
8082 case 0x0C: strcpy(insn[i],"ANDI"); type=IMM16; break;
8083 case 0x0D: strcpy(insn[i],"ORI"); type=IMM16; break;
8084 case 0x0E: strcpy(insn[i],"XORI"); type=IMM16; break;
8085 case 0x0F: strcpy(insn[i],"LUI"); type=IMM16; break;
8086 case 0x10: strcpy(insn[i],"cop0"); type=NI;
8087 op2=(source[i]>>21)&0x1f;
8088 switch(op2)
8089 {
8090 case 0x00: strcpy(insn[i],"MFC0"); type=COP0; break;
8091 case 0x04: strcpy(insn[i],"MTC0"); type=COP0; break;
8092 case 0x10: strcpy(insn[i],"tlb"); type=NI;
8093 switch(source[i]&0x3f)
8094 {
8095 case 0x01: strcpy(insn[i],"TLBR"); type=COP0; break;
8096 case 0x02: strcpy(insn[i],"TLBWI"); type=COP0; break;
8097 case 0x06: strcpy(insn[i],"TLBWR"); type=COP0; break;
8098 case 0x08: strcpy(insn[i],"TLBP"); type=COP0; break;
576bbd8f 8099#ifdef PCSX
8100 case 0x10: strcpy(insn[i],"RFE"); type=COP0; break;
8101#else
57871462 8102 case 0x18: strcpy(insn[i],"ERET"); type=COP0; break;
576bbd8f 8103#endif
57871462 8104 }
8105 }
8106 break;
8107 case 0x11: strcpy(insn[i],"cop1"); type=NI;
8108 op2=(source[i]>>21)&0x1f;
8109 switch(op2)
8110 {
8111 case 0x00: strcpy(insn[i],"MFC1"); type=COP1; break;
8112 case 0x01: strcpy(insn[i],"DMFC1"); type=COP1; break;
8113 case 0x02: strcpy(insn[i],"CFC1"); type=COP1; break;
8114 case 0x04: strcpy(insn[i],"MTC1"); type=COP1; break;
8115 case 0x05: strcpy(insn[i],"DMTC1"); type=COP1; break;
8116 case 0x06: strcpy(insn[i],"CTC1"); type=COP1; break;
8117 case 0x08: strcpy(insn[i],"BC1"); type=FJUMP;
8118 switch((source[i]>>16)&0x3)
8119 {
8120 case 0x00: strcpy(insn[i],"BC1F"); break;
8121 case 0x01: strcpy(insn[i],"BC1T"); break;
8122 case 0x02: strcpy(insn[i],"BC1FL"); break;
8123 case 0x03: strcpy(insn[i],"BC1TL"); break;
8124 }
8125 break;
8126 case 0x10: strcpy(insn[i],"C1.S"); type=NI;
8127 switch(source[i]&0x3f)
8128 {
8129 case 0x00: strcpy(insn[i],"ADD.S"); type=FLOAT; break;
8130 case 0x01: strcpy(insn[i],"SUB.S"); type=FLOAT; break;
8131 case 0x02: strcpy(insn[i],"MUL.S"); type=FLOAT; break;
8132 case 0x03: strcpy(insn[i],"DIV.S"); type=FLOAT; break;
8133 case 0x04: strcpy(insn[i],"SQRT.S"); type=FLOAT; break;
8134 case 0x05: strcpy(insn[i],"ABS.S"); type=FLOAT; break;
8135 case 0x06: strcpy(insn[i],"MOV.S"); type=FLOAT; break;
8136 case 0x07: strcpy(insn[i],"NEG.S"); type=FLOAT; break;
8137 case 0x08: strcpy(insn[i],"ROUND.L.S"); type=FCONV; break;
8138 case 0x09: strcpy(insn[i],"TRUNC.L.S"); type=FCONV; break;
8139 case 0x0A: strcpy(insn[i],"CEIL.L.S"); type=FCONV; break;
8140 case 0x0B: strcpy(insn[i],"FLOOR.L.S"); type=FCONV; break;
8141 case 0x0C: strcpy(insn[i],"ROUND.W.S"); type=FCONV; break;
8142 case 0x0D: strcpy(insn[i],"TRUNC.W.S"); type=FCONV; break;
8143 case 0x0E: strcpy(insn[i],"CEIL.W.S"); type=FCONV; break;
8144 case 0x0F: strcpy(insn[i],"FLOOR.W.S"); type=FCONV; break;
8145 case 0x21: strcpy(insn[i],"CVT.D.S"); type=FCONV; break;
8146 case 0x24: strcpy(insn[i],"CVT.W.S"); type=FCONV; break;
8147 case 0x25: strcpy(insn[i],"CVT.L.S"); type=FCONV; break;
8148 case 0x30: strcpy(insn[i],"C.F.S"); type=FCOMP; break;
8149 case 0x31: strcpy(insn[i],"C.UN.S"); type=FCOMP; break;
8150 case 0x32: strcpy(insn[i],"C.EQ.S"); type=FCOMP; break;
8151 case 0x33: strcpy(insn[i],"C.UEQ.S"); type=FCOMP; break;
8152 case 0x34: strcpy(insn[i],"C.OLT.S"); type=FCOMP; break;
8153 case 0x35: strcpy(insn[i],"C.ULT.S"); type=FCOMP; break;
8154 case 0x36: strcpy(insn[i],"C.OLE.S"); type=FCOMP; break;
8155 case 0x37: strcpy(insn[i],"C.ULE.S"); type=FCOMP; break;
8156 case 0x38: strcpy(insn[i],"C.SF.S"); type=FCOMP; break;
8157 case 0x39: strcpy(insn[i],"C.NGLE.S"); type=FCOMP; break;
8158 case 0x3A: strcpy(insn[i],"C.SEQ.S"); type=FCOMP; break;
8159 case 0x3B: strcpy(insn[i],"C.NGL.S"); type=FCOMP; break;
8160 case 0x3C: strcpy(insn[i],"C.LT.S"); type=FCOMP; break;
8161 case 0x3D: strcpy(insn[i],"C.NGE.S"); type=FCOMP; break;
8162 case 0x3E: strcpy(insn[i],"C.LE.S"); type=FCOMP; break;
8163 case 0x3F: strcpy(insn[i],"C.NGT.S"); type=FCOMP; break;
8164 }
8165 break;
8166 case 0x11: strcpy(insn[i],"C1.D"); type=NI;
8167 switch(source[i]&0x3f)
8168 {
8169 case 0x00: strcpy(insn[i],"ADD.D"); type=FLOAT; break;
8170 case 0x01: strcpy(insn[i],"SUB.D"); type=FLOAT; break;
8171 case 0x02: strcpy(insn[i],"MUL.D"); type=FLOAT; break;
8172 case 0x03: strcpy(insn[i],"DIV.D"); type=FLOAT; break;
8173 case 0x04: strcpy(insn[i],"SQRT.D"); type=FLOAT; break;
8174 case 0x05: strcpy(insn[i],"ABS.D"); type=FLOAT; break;
8175 case 0x06: strcpy(insn[i],"MOV.D"); type=FLOAT; break;
8176 case 0x07: strcpy(insn[i],"NEG.D"); type=FLOAT; break;
8177 case 0x08: strcpy(insn[i],"ROUND.L.D"); type=FCONV; break;
8178 case 0x09: strcpy(insn[i],"TRUNC.L.D"); type=FCONV; break;
8179 case 0x0A: strcpy(insn[i],"CEIL.L.D"); type=FCONV; break;
8180 case 0x0B: strcpy(insn[i],"FLOOR.L.D"); type=FCONV; break;
8181 case 0x0C: strcpy(insn[i],"ROUND.W.D"); type=FCONV; break;
8182 case 0x0D: strcpy(insn[i],"TRUNC.W.D"); type=FCONV; break;
8183 case 0x0E: strcpy(insn[i],"CEIL.W.D"); type=FCONV; break;
8184 case 0x0F: strcpy(insn[i],"FLOOR.W.D"); type=FCONV; break;
8185 case 0x20: strcpy(insn[i],"CVT.S.D"); type=FCONV; break;
8186 case 0x24: strcpy(insn[i],"CVT.W.D"); type=FCONV; break;
8187 case 0x25: strcpy(insn[i],"CVT.L.D"); type=FCONV; break;
8188 case 0x30: strcpy(insn[i],"C.F.D"); type=FCOMP; break;
8189 case 0x31: strcpy(insn[i],"C.UN.D"); type=FCOMP; break;
8190 case 0x32: strcpy(insn[i],"C.EQ.D"); type=FCOMP; break;
8191 case 0x33: strcpy(insn[i],"C.UEQ.D"); type=FCOMP; break;
8192 case 0x34: strcpy(insn[i],"C.OLT.D"); type=FCOMP; break;
8193 case 0x35: strcpy(insn[i],"C.ULT.D"); type=FCOMP; break;
8194 case 0x36: strcpy(insn[i],"C.OLE.D"); type=FCOMP; break;
8195 case 0x37: strcpy(insn[i],"C.ULE.D"); type=FCOMP; break;
8196 case 0x38: strcpy(insn[i],"C.SF.D"); type=FCOMP; break;
8197 case 0x39: strcpy(insn[i],"C.NGLE.D"); type=FCOMP; break;
8198 case 0x3A: strcpy(insn[i],"C.SEQ.D"); type=FCOMP; break;
8199 case 0x3B: strcpy(insn[i],"C.NGL.D"); type=FCOMP; break;
8200 case 0x3C: strcpy(insn[i],"C.LT.D"); type=FCOMP; break;
8201 case 0x3D: strcpy(insn[i],"C.NGE.D"); type=FCOMP; break;
8202 case 0x3E: strcpy(insn[i],"C.LE.D"); type=FCOMP; break;
8203 case 0x3F: strcpy(insn[i],"C.NGT.D"); type=FCOMP; break;
8204 }
8205 break;
8206 case 0x14: strcpy(insn[i],"C1.W"); type=NI;
8207 switch(source[i]&0x3f)
8208 {
8209 case 0x20: strcpy(insn[i],"CVT.S.W"); type=FCONV; break;
8210 case 0x21: strcpy(insn[i],"CVT.D.W"); type=FCONV; break;
8211 }
8212 break;
8213 case 0x15: strcpy(insn[i],"C1.L"); type=NI;
8214 switch(source[i]&0x3f)
8215 {
8216 case 0x20: strcpy(insn[i],"CVT.S.L"); type=FCONV; break;
8217 case 0x21: strcpy(insn[i],"CVT.D.L"); type=FCONV; break;
8218 }
8219 break;
8220 }
8221 break;
909168d6 8222#ifndef FORCE32
57871462 8223 case 0x14: strcpy(insn[i],"BEQL"); type=CJUMP; break;
8224 case 0x15: strcpy(insn[i],"BNEL"); type=CJUMP; break;
8225 case 0x16: strcpy(insn[i],"BLEZL"); type=CJUMP; break;
8226 case 0x17: strcpy(insn[i],"BGTZL"); type=CJUMP; break;
8227 case 0x18: strcpy(insn[i],"DADDI"); type=IMM16; break;
8228 case 0x19: strcpy(insn[i],"DADDIU"); type=IMM16; break;
8229 case 0x1A: strcpy(insn[i],"LDL"); type=LOADLR; break;
8230 case 0x1B: strcpy(insn[i],"LDR"); type=LOADLR; break;
996cc15d 8231#endif
57871462 8232 case 0x20: strcpy(insn[i],"LB"); type=LOAD; break;
8233 case 0x21: strcpy(insn[i],"LH"); type=LOAD; break;
8234 case 0x22: strcpy(insn[i],"LWL"); type=LOADLR; break;
8235 case 0x23: strcpy(insn[i],"LW"); type=LOAD; break;
8236 case 0x24: strcpy(insn[i],"LBU"); type=LOAD; break;
8237 case 0x25: strcpy(insn[i],"LHU"); type=LOAD; break;
8238 case 0x26: strcpy(insn[i],"LWR"); type=LOADLR; break;
8239 case 0x27: strcpy(insn[i],"LWU"); type=LOAD; break;
8240 case 0x28: strcpy(insn[i],"SB"); type=STORE; break;
8241 case 0x29: strcpy(insn[i],"SH"); type=STORE; break;
8242 case 0x2A: strcpy(insn[i],"SWL"); type=STORELR; break;
8243 case 0x2B: strcpy(insn[i],"SW"); type=STORE; break;
996cc15d 8244#ifndef FORCE32
57871462 8245 case 0x2C: strcpy(insn[i],"SDL"); type=STORELR; break;
8246 case 0x2D: strcpy(insn[i],"SDR"); type=STORELR; break;
996cc15d 8247#endif
57871462 8248 case 0x2E: strcpy(insn[i],"SWR"); type=STORELR; break;
8249 case 0x2F: strcpy(insn[i],"CACHE"); type=NOP; break;
8250 case 0x30: strcpy(insn[i],"LL"); type=NI; break;
8251 case 0x31: strcpy(insn[i],"LWC1"); type=C1LS; break;
996cc15d 8252#ifndef FORCE32
57871462 8253 case 0x34: strcpy(insn[i],"LLD"); type=NI; break;
8254 case 0x35: strcpy(insn[i],"LDC1"); type=C1LS; break;
8255 case 0x37: strcpy(insn[i],"LD"); type=LOAD; break;
996cc15d 8256#endif
57871462 8257 case 0x38: strcpy(insn[i],"SC"); type=NI; break;
8258 case 0x39: strcpy(insn[i],"SWC1"); type=C1LS; break;
996cc15d 8259#ifndef FORCE32
57871462 8260 case 0x3C: strcpy(insn[i],"SCD"); type=NI; break;
8261 case 0x3D: strcpy(insn[i],"SDC1"); type=C1LS; break;
8262 case 0x3F: strcpy(insn[i],"SD"); type=STORE; break;
996cc15d 8263#endif
b9b61529 8264#ifdef PCSX
8265 case 0x12: strcpy(insn[i],"COP2"); type=NI;
c7abc864 8266 // note: COP MIPS-1 encoding differs from MIPS32
b9b61529 8267 op2=(source[i]>>21)&0x1f;
c7abc864 8268 if (source[i]&0x3f) {
8269 if (gte_handlers[source[i]&0x3f]!=NULL) {
8270 snprintf(insn[i], sizeof(insn[i]), "COP2 %x", source[i]&0x3f);
8271 type=C2OP;
8272 }
8273 }
8274 else switch(op2)
b9b61529 8275 {
8276 case 0x00: strcpy(insn[i],"MFC2"); type=COP2; break;
8277 case 0x02: strcpy(insn[i],"CFC2"); type=COP2; break;
8278 case 0x04: strcpy(insn[i],"MTC2"); type=COP2; break;
8279 case 0x06: strcpy(insn[i],"CTC2"); type=COP2; break;
b9b61529 8280 }
8281 break;
8282 case 0x32: strcpy(insn[i],"LWC2"); type=C2LS; break;
8283 case 0x3A: strcpy(insn[i],"SWC2"); type=C2LS; break;
8284 case 0x3B: strcpy(insn[i],"HLECALL"); type=HLECALL; break;
8285#endif
90ae6d4e 8286 default: strcpy(insn[i],"???"); type=NI;
75dec299 8287 printf("NI %08x @%08x (%08x)\n", source[i], addr + i*4, addr);
90ae6d4e 8288 break;
57871462 8289 }
8290 itype[i]=type;
8291 opcode2[i]=op2;
8292 /* Get registers/immediates */
8293 lt1[i]=0;
8294 us1[i]=0;
8295 us2[i]=0;
8296 dep1[i]=0;
8297 dep2[i]=0;
8298 switch(type) {
8299 case LOAD:
8300 rs1[i]=(source[i]>>21)&0x1f;
8301 rs2[i]=0;
8302 rt1[i]=(source[i]>>16)&0x1f;
8303 rt2[i]=0;
8304 imm[i]=(short)source[i];
8305 break;
8306 case STORE:
8307 case STORELR:
8308 rs1[i]=(source[i]>>21)&0x1f;
8309 rs2[i]=(source[i]>>16)&0x1f;
8310 rt1[i]=0;
8311 rt2[i]=0;
8312 imm[i]=(short)source[i];
8313 if(op==0x2c||op==0x2d||op==0x3f) us1[i]=rs2[i]; // 64-bit SDL/SDR/SD
8314 break;
8315 case LOADLR:
8316 // LWL/LWR only load part of the register,
8317 // therefore the target register must be treated as a source too
8318 rs1[i]=(source[i]>>21)&0x1f;
8319 rs2[i]=(source[i]>>16)&0x1f;
8320 rt1[i]=(source[i]>>16)&0x1f;
8321 rt2[i]=0;
8322 imm[i]=(short)source[i];
8323 if(op==0x1a||op==0x1b) us1[i]=rs2[i]; // LDR/LDL
8324 if(op==0x26) dep1[i]=rt1[i]; // LWR
8325 break;
8326 case IMM16:
8327 if (op==0x0f) rs1[i]=0; // LUI instruction has no source register
8328 else rs1[i]=(source[i]>>21)&0x1f;
8329 rs2[i]=0;
8330 rt1[i]=(source[i]>>16)&0x1f;
8331 rt2[i]=0;
8332 if(op>=0x0c&&op<=0x0e) { // ANDI/ORI/XORI
8333 imm[i]=(unsigned short)source[i];
8334 }else{
8335 imm[i]=(short)source[i];
8336 }
8337 if(op==0x18||op==0x19) us1[i]=rs1[i]; // DADDI/DADDIU
8338 if(op==0x0a||op==0x0b) us1[i]=rs1[i]; // SLTI/SLTIU
8339 if(op==0x0d||op==0x0e) dep1[i]=rs1[i]; // ORI/XORI
8340 break;
8341 case UJUMP:
8342 rs1[i]=0;
8343 rs2[i]=0;
8344 rt1[i]=0;
8345 rt2[i]=0;
8346 // The JAL instruction writes to r31.
8347 if (op&1) {
8348 rt1[i]=31;
8349 }
8350 rs2[i]=CCREG;
8351 break;
8352 case RJUMP:
8353 rs1[i]=(source[i]>>21)&0x1f;
8354 rs2[i]=0;
8355 rt1[i]=0;
8356 rt2[i]=0;
5067f341 8357 // The JALR instruction writes to rd.
57871462 8358 if (op2&1) {
5067f341 8359 rt1[i]=(source[i]>>11)&0x1f;
57871462 8360 }
8361 rs2[i]=CCREG;
8362 break;
8363 case CJUMP:
8364 rs1[i]=(source[i]>>21)&0x1f;
8365 rs2[i]=(source[i]>>16)&0x1f;
8366 rt1[i]=0;
8367 rt2[i]=0;
8368 if(op&2) { // BGTZ/BLEZ
8369 rs2[i]=0;
8370 }
8371 us1[i]=rs1[i];
8372 us2[i]=rs2[i];
8373 likely[i]=op>>4;
8374 break;
8375 case SJUMP:
8376 rs1[i]=(source[i]>>21)&0x1f;
8377 rs2[i]=CCREG;
8378 rt1[i]=0;
8379 rt2[i]=0;
8380 us1[i]=rs1[i];
8381 if(op2&0x10) { // BxxAL
8382 rt1[i]=31;
8383 // NOTE: If the branch is not taken, r31 is still overwritten
8384 }
8385 likely[i]=(op2&2)>>1;
8386 break;
8387 case FJUMP:
8388 rs1[i]=FSREG;
8389 rs2[i]=CSREG;
8390 rt1[i]=0;
8391 rt2[i]=0;
8392 likely[i]=((source[i])>>17)&1;
8393 break;
8394 case ALU:
8395 rs1[i]=(source[i]>>21)&0x1f; // source
8396 rs2[i]=(source[i]>>16)&0x1f; // subtract amount
8397 rt1[i]=(source[i]>>11)&0x1f; // destination
8398 rt2[i]=0;
8399 if(op2==0x2a||op2==0x2b) { // SLT/SLTU
8400 us1[i]=rs1[i];us2[i]=rs2[i];
8401 }
8402 else if(op2>=0x24&&op2<=0x27) { // AND/OR/XOR/NOR
8403 dep1[i]=rs1[i];dep2[i]=rs2[i];
8404 }
8405 else if(op2>=0x2c&&op2<=0x2f) { // DADD/DSUB
8406 dep1[i]=rs1[i];dep2[i]=rs2[i];
8407 }
8408 break;
8409 case MULTDIV:
8410 rs1[i]=(source[i]>>21)&0x1f; // source
8411 rs2[i]=(source[i]>>16)&0x1f; // divisor
8412 rt1[i]=HIREG;
8413 rt2[i]=LOREG;
8414 if (op2>=0x1c&&op2<=0x1f) { // DMULT/DMULTU/DDIV/DDIVU
8415 us1[i]=rs1[i];us2[i]=rs2[i];
8416 }
8417 break;
8418 case MOV:
8419 rs1[i]=0;
8420 rs2[i]=0;
8421 rt1[i]=0;
8422 rt2[i]=0;
8423 if(op2==0x10) rs1[i]=HIREG; // MFHI
8424 if(op2==0x11) rt1[i]=HIREG; // MTHI
8425 if(op2==0x12) rs1[i]=LOREG; // MFLO
8426 if(op2==0x13) rt1[i]=LOREG; // MTLO
8427 if((op2&0x1d)==0x10) rt1[i]=(source[i]>>11)&0x1f; // MFxx
8428 if((op2&0x1d)==0x11) rs1[i]=(source[i]>>21)&0x1f; // MTxx
8429 dep1[i]=rs1[i];
8430 break;
8431 case SHIFT:
8432 rs1[i]=(source[i]>>16)&0x1f; // target of shift
8433 rs2[i]=(source[i]>>21)&0x1f; // shift amount
8434 rt1[i]=(source[i]>>11)&0x1f; // destination
8435 rt2[i]=0;
8436 // DSLLV/DSRLV/DSRAV are 64-bit
8437 if(op2>=0x14&&op2<=0x17) us1[i]=rs1[i];
8438 break;
8439 case SHIFTIMM:
8440 rs1[i]=(source[i]>>16)&0x1f;
8441 rs2[i]=0;
8442 rt1[i]=(source[i]>>11)&0x1f;
8443 rt2[i]=0;
8444 imm[i]=(source[i]>>6)&0x1f;
8445 // DSxx32 instructions
8446 if(op2>=0x3c) imm[i]|=0x20;
8447 // DSLL/DSRL/DSRA/DSRA32/DSRL32 but not DSLL32 require 64-bit source
8448 if(op2>=0x38&&op2!=0x3c) us1[i]=rs1[i];
8449 break;
8450 case COP0:
8451 rs1[i]=0;
8452 rs2[i]=0;
8453 rt1[i]=0;
8454 rt2[i]=0;
8455 if(op2==0) rt1[i]=(source[i]>>16)&0x1F; // MFC0
8456 if(op2==4) rs1[i]=(source[i]>>16)&0x1F; // MTC0
8457 if(op2==4&&((source[i]>>11)&0x1f)==12) rt2[i]=CSREG; // Status
8458 if(op2==16) if((source[i]&0x3f)==0x18) rs2[i]=CCREG; // ERET
8459 break;
8460 case COP1:
b9b61529 8461 case COP2:
57871462 8462 rs1[i]=0;
8463 rs2[i]=0;
8464 rt1[i]=0;
8465 rt2[i]=0;
8466 if(op2<3) rt1[i]=(source[i]>>16)&0x1F; // MFC1/DMFC1/CFC1
8467 if(op2>3) rs1[i]=(source[i]>>16)&0x1F; // MTC1/DMTC1/CTC1
8468 if(op2==5) us1[i]=rs1[i]; // DMTC1
8469 rs2[i]=CSREG;
8470 break;
8471 case C1LS:
8472 rs1[i]=(source[i]>>21)&0x1F;
8473 rs2[i]=CSREG;
8474 rt1[i]=0;
8475 rt2[i]=0;
8476 imm[i]=(short)source[i];
8477 break;
b9b61529 8478 case C2LS:
8479 rs1[i]=(source[i]>>21)&0x1F;
8480 rs2[i]=0;
8481 rt1[i]=0;
8482 rt2[i]=0;
8483 imm[i]=(short)source[i];
8484 break;
57871462 8485 case FLOAT:
8486 case FCONV:
8487 rs1[i]=0;
8488 rs2[i]=CSREG;
8489 rt1[i]=0;
8490 rt2[i]=0;
8491 break;
8492 case FCOMP:
8493 rs1[i]=FSREG;
8494 rs2[i]=CSREG;
8495 rt1[i]=FSREG;
8496 rt2[i]=0;
8497 break;
8498 case SYSCALL:
7139f3c8 8499 case HLECALL:
1e973cb0 8500 case INTCALL:
57871462 8501 rs1[i]=CCREG;
8502 rs2[i]=0;
8503 rt1[i]=0;
8504 rt2[i]=0;
8505 break;
8506 default:
8507 rs1[i]=0;
8508 rs2[i]=0;
8509 rt1[i]=0;
8510 rt2[i]=0;
8511 }
8512 /* Calculate branch target addresses */
8513 if(type==UJUMP)
8514 ba[i]=((start+i*4+4)&0xF0000000)|(((unsigned int)source[i]<<6)>>4);
8515 else if(type==CJUMP&&rs1[i]==rs2[i]&&(op&1))
8516 ba[i]=start+i*4+8; // Ignore never taken branch
8517 else if(type==SJUMP&&rs1[i]==0&&!(op2&1))
8518 ba[i]=start+i*4+8; // Ignore never taken branch
8519 else if(type==CJUMP||type==SJUMP||type==FJUMP)
8520 ba[i]=start+i*4+4+((signed int)((unsigned int)source[i]<<16)>>14);
8521 else ba[i]=-1;
26869094 8522#ifdef PCSX
3e535354 8523 if(i>0&&(itype[i-1]==RJUMP||itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP)) {
8524 int do_in_intrp=0;
8525 // branch in delay slot?
8526 if(type==RJUMP||type==UJUMP||type==CJUMP||type==SJUMP||type==FJUMP) {
8527 // don't handle first branch and call interpreter if it's hit
8528 printf("branch in delay slot @%08x (%08x)\n", addr + i*4, addr);
8529 do_in_intrp=1;
8530 }
8531 // basic load delay detection
8532 else if((type==LOAD||type==LOADLR||type==COP0||type==COP2||type==C2LS)&&rt1[i]!=0) {
8533 int t=(ba[i-1]-start)/4;
8534 if(0 <= t && t < i &&(rt1[i]==rs1[t]||rt1[i]==rs2[t])&&itype[t]!=CJUMP&&itype[t]!=SJUMP) {
8535 // jump target wants DS result - potential load delay effect
8536 printf("load delay @%08x (%08x)\n", addr + i*4, addr);
8537 do_in_intrp=1;
8538 bt[t+1]=1; // expected return from interpreter
8539 }
8540 else if(i>=2&&rt1[i-2]==2&&rt1[i]==2&&rs1[i]!=2&&rs2[i]!=2&&rs1[i-1]!=2&&rs2[i-1]!=2&&
8541 !(i>=3&&(itype[i-3]==RJUMP||itype[i-3]==UJUMP||itype[i-3]==CJUMP||itype[i-3]==SJUMP))) {
8542 // v0 overwrite like this is a sign of trouble, bail out
8543 printf("v0 overwrite @%08x (%08x)\n", addr + i*4, addr);
8544 do_in_intrp=1;
8545 }
8546 }
3e535354 8547 if(do_in_intrp) {
8548 rs1[i-1]=CCREG;
8549 rs2[i-1]=rt1[i-1]=rt2[i-1]=0;
26869094 8550 ba[i-1]=-1;
8551 itype[i-1]=INTCALL;
8552 done=2;
3e535354 8553 i--; // don't compile the DS
26869094 8554 }
3e535354 8555 }
26869094 8556#endif
3e535354 8557 /* Is this the end of the block? */
8558 if(i>0&&(itype[i-1]==UJUMP||itype[i-1]==RJUMP||(source[i-1]>>16)==0x1000)) {
5067f341 8559 if(rt1[i-1]==0) { // Continue past subroutine call (JAL)
1e973cb0 8560 done=2;
57871462 8561 }
8562 else {
8563 if(stop_after_jal) done=1;
8564 // Stop on BREAK
8565 if((source[i+1]&0xfc00003f)==0x0d) done=1;
8566 }
8567 // Don't recompile stuff that's already compiled
8568 if(check_addr(start+i*4+4)) done=1;
8569 // Don't get too close to the limit
8570 if(i>MAXBLOCK/2) done=1;
8571 }
75dec299 8572 if(itype[i]==SYSCALL&&stop_after_jal) done=1;
1e973cb0 8573 if(itype[i]==HLECALL||itype[i]==INTCALL) done=2;
8574 if(done==2) {
8575 // Does the block continue due to a branch?
8576 for(j=i-1;j>=0;j--)
8577 {
8578 if(ba[j]==start+i*4+4) done=j=0;
8579 if(ba[j]==start+i*4+8) done=j=0;
8580 }
8581 }
75dec299 8582 //assert(i<MAXBLOCK-1);
57871462 8583 if(start+i*4==pagelimit-4) done=1;
8584 assert(start+i*4<pagelimit);
8585 if (i==MAXBLOCK-1) done=1;
8586 // Stop if we're compiling junk
8587 if(itype[i]==NI&&opcode[i]==0x11) {
8588 done=stop_after_jal=1;
8589 printf("Disabled speculative precompilation\n");
8590 }
8591 }
8592 slen=i;
8593 if(itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==RJUMP||itype[i-1]==FJUMP) {
8594 if(start+i*4==pagelimit) {
8595 itype[i-1]=SPAN;
8596 }
8597 }
8598 assert(slen>0);
8599
8600 /* Pass 2 - Register dependencies and branch targets */
8601
8602 unneeded_registers(0,slen-1,0);
8603
8604 /* Pass 3 - Register allocation */
8605
8606 struct regstat current; // Current register allocations/status
8607 current.is32=1;
8608 current.dirty=0;
8609 current.u=unneeded_reg[0];
8610 current.uu=unneeded_reg_upper[0];
8611 clear_all_regs(current.regmap);
8612 alloc_reg(&current,0,CCREG);
8613 dirty_reg(&current,CCREG);
8614 current.isconst=0;
8615 current.wasconst=0;
8616 int ds=0;
8617 int cc=0;
5194fb95 8618 int hr=-1;
6ebf4adf 8619
8620#ifndef FORCE32
57871462 8621 provisional_32bit();
6ebf4adf 8622#endif
57871462 8623 if((u_int)addr&1) {
8624 // First instruction is delay slot
8625 cc=-1;
8626 bt[1]=1;
8627 ds=1;
8628 unneeded_reg[0]=1;
8629 unneeded_reg_upper[0]=1;
8630 current.regmap[HOST_BTREG]=BTREG;
8631 }
8632
8633 for(i=0;i<slen;i++)
8634 {
8635 if(bt[i])
8636 {
8637 int hr;
8638 for(hr=0;hr<HOST_REGS;hr++)
8639 {
8640 // Is this really necessary?
8641 if(current.regmap[hr]==0) current.regmap[hr]=-1;
8642 }
8643 current.isconst=0;
8644 }
8645 if(i>1)
8646 {
8647 if((opcode[i-2]&0x2f)==0x05) // BNE/BNEL
8648 {
8649 if(rs1[i-2]==0||rs2[i-2]==0)
8650 {
8651 if(rs1[i-2]) {
8652 current.is32|=1LL<<rs1[i-2];
8653 int hr=get_reg(current.regmap,rs1[i-2]|64);
8654 if(hr>=0) current.regmap[hr]=-1;
8655 }
8656 if(rs2[i-2]) {
8657 current.is32|=1LL<<rs2[i-2];
8658 int hr=get_reg(current.regmap,rs2[i-2]|64);
8659 if(hr>=0) current.regmap[hr]=-1;
8660 }
8661 }
8662 }
8663 }
6ebf4adf 8664#ifndef FORCE32
57871462 8665 // If something jumps here with 64-bit values
8666 // then promote those registers to 64 bits
8667 if(bt[i])
8668 {
8669 uint64_t temp_is32=current.is32;
8670 for(j=i-1;j>=0;j--)
8671 {
8672 if(ba[j]==start+i*4)
8673 temp_is32&=branch_regs[j].is32;
8674 }
8675 for(j=i;j<slen;j++)
8676 {
8677 if(ba[j]==start+i*4)
8678 //temp_is32=1;
8679 temp_is32&=p32[j];
8680 }
8681 if(temp_is32!=current.is32) {
8682 //printf("dumping 32-bit regs (%x)\n",start+i*4);
8683 #ifdef DESTRUCTIVE_WRITEBACK
8684 for(hr=0;hr<HOST_REGS;hr++)
8685 {
8686 int r=current.regmap[hr];
8687 if(r>0&&r<64)
8688 {
8689 if((current.dirty>>hr)&((current.is32&~temp_is32)>>r)&1) {
8690 temp_is32|=1LL<<r;
8691 //printf("restore %d\n",r);
8692 }
8693 }
8694 }
8695 #endif
8696 current.is32=temp_is32;
8697 }
8698 }
6ebf4adf 8699#else
24385cae 8700 current.is32=-1LL;
8701#endif
8702
57871462 8703 memcpy(regmap_pre[i],current.regmap,sizeof(current.regmap));
8704 regs[i].wasconst=current.isconst;
8705 regs[i].was32=current.is32;
8706 regs[i].wasdirty=current.dirty;
6ebf4adf 8707 #if defined(DESTRUCTIVE_WRITEBACK) && !defined(FORCE32)
57871462 8708 // To change a dirty register from 32 to 64 bits, we must write
8709 // it out during the previous cycle (for branches, 2 cycles)
8710 if(i<slen-1&&bt[i+1]&&itype[i-1]!=UJUMP&&itype[i-1]!=CJUMP&&itype[i-1]!=SJUMP&&itype[i-1]!=RJUMP&&itype[i-1]!=FJUMP)
8711 {
8712 uint64_t temp_is32=current.is32;
8713 for(j=i-1;j>=0;j--)
8714 {
8715 if(ba[j]==start+i*4+4)
8716 temp_is32&=branch_regs[j].is32;
8717 }
8718 for(j=i;j<slen;j++)
8719 {
8720 if(ba[j]==start+i*4+4)
8721 //temp_is32=1;
8722 temp_is32&=p32[j];
8723 }
8724 if(temp_is32!=current.is32) {
8725 //printf("pre-dumping 32-bit regs (%x)\n",start+i*4);
8726 for(hr=0;hr<HOST_REGS;hr++)
8727 {
8728 int r=current.regmap[hr];
8729 if(r>0)
8730 {
8731 if((current.dirty>>hr)&((current.is32&~temp_is32)>>(r&63))&1) {
8732 if(itype[i]!=UJUMP&&itype[i]!=CJUMP&&itype[i]!=SJUMP&&itype[i]!=RJUMP&&itype[i]!=FJUMP)
8733 {
8734 if(rs1[i]!=(r&63)&&rs2[i]!=(r&63))
8735 {
8736 //printf("dump %d/r%d\n",hr,r);
8737 current.regmap[hr]=-1;
8738 if(get_reg(current.regmap,r|64)>=0)
8739 current.regmap[get_reg(current.regmap,r|64)]=-1;
8740 }
8741 }
8742 }
8743 }
8744 }
8745 }
8746 }
8747 else if(i<slen-2&&bt[i+2]&&(source[i-1]>>16)!=0x1000&&(itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP))
8748 {
8749 uint64_t temp_is32=current.is32;
8750 for(j=i-1;j>=0;j--)
8751 {
8752 if(ba[j]==start+i*4+8)
8753 temp_is32&=branch_regs[j].is32;
8754 }
8755 for(j=i;j<slen;j++)
8756 {
8757 if(ba[j]==start+i*4+8)
8758 //temp_is32=1;
8759 temp_is32&=p32[j];
8760 }
8761 if(temp_is32!=current.is32) {
8762 //printf("pre-dumping 32-bit regs (%x)\n",start+i*4);
8763 for(hr=0;hr<HOST_REGS;hr++)
8764 {
8765 int r=current.regmap[hr];
8766 if(r>0)
8767 {
8768 if((current.dirty>>hr)&((current.is32&~temp_is32)>>(r&63))&1) {
8769 if(rs1[i]!=(r&63)&&rs2[i]!=(r&63)&&rs1[i+1]!=(r&63)&&rs2[i+1]!=(r&63))
8770 {
8771 //printf("dump %d/r%d\n",hr,r);
8772 current.regmap[hr]=-1;
8773 if(get_reg(current.regmap,r|64)>=0)
8774 current.regmap[get_reg(current.regmap,r|64)]=-1;
8775 }
8776 }
8777 }
8778 }
8779 }
8780 }
8781 #endif
8782 if(itype[i]!=UJUMP&&itype[i]!=CJUMP&&itype[i]!=SJUMP&&itype[i]!=RJUMP&&itype[i]!=FJUMP) {
8783 if(i+1<slen) {
8784 current.u=unneeded_reg[i+1]&~((1LL<<rs1[i])|(1LL<<rs2[i]));
8785 current.uu=unneeded_reg_upper[i+1]&~((1LL<<us1[i])|(1LL<<us2[i]));
8786 if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
8787 current.u|=1;
8788 current.uu|=1;
8789 } else {
8790 current.u=1;
8791 current.uu=1;
8792 }
8793 } else {
8794 if(i+1<slen) {
8795 current.u=branch_unneeded_reg[i]&~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
8796 current.uu=branch_unneeded_reg_upper[i]&~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
8797 if((~current.uu>>rt1[i+1])&1) current.uu&=~((1LL<<dep1[i+1])|(1LL<<dep2[i+1]));
8798 current.u&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
8799 current.uu&=~((1LL<<us1[i])|(1LL<<us2[i]));
8800 current.u|=1;
8801 current.uu|=1;
8802 } else { printf("oops, branch at end of block with no delay slot\n");exit(1); }
8803 }
8804 is_ds[i]=ds;
8805 if(ds) {
8806 ds=0; // Skip delay slot, already allocated as part of branch
8807 // ...but we need to alloc it in case something jumps here
8808 if(i+1<slen) {
8809 current.u=branch_unneeded_reg[i-1]&unneeded_reg[i+1];
8810 current.uu=branch_unneeded_reg_upper[i-1]&unneeded_reg_upper[i+1];
8811 }else{
8812 current.u=branch_unneeded_reg[i-1];
8813 current.uu=branch_unneeded_reg_upper[i-1];
8814 }
8815 current.u&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
8816 current.uu&=~((1LL<<us1[i])|(1LL<<us2[i]));
8817 if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
8818 current.u|=1;
8819 current.uu|=1;
8820 struct regstat temp;
8821 memcpy(&temp,&current,sizeof(current));
8822 temp.wasdirty=temp.dirty;
8823 temp.was32=temp.is32;
8824 // TODO: Take into account unconditional branches, as below
8825 delayslot_alloc(&temp,i);
8826 memcpy(regs[i].regmap,temp.regmap,sizeof(temp.regmap));
8827 regs[i].wasdirty=temp.wasdirty;
8828 regs[i].was32=temp.was32;
8829 regs[i].dirty=temp.dirty;
8830 regs[i].is32=temp.is32;
8831 regs[i].isconst=0;
8832 regs[i].wasconst=0;
8833 current.isconst=0;
8834 // Create entry (branch target) regmap
8835 for(hr=0;hr<HOST_REGS;hr++)
8836 {
8837 int r=temp.regmap[hr];
8838 if(r>=0) {
8839 if(r!=regmap_pre[i][hr]) {
8840 regs[i].regmap_entry[hr]=-1;
8841 }
8842 else
8843 {
8844 if(r<64){
8845 if((current.u>>r)&1) {
8846 regs[i].regmap_entry[hr]=-1;
8847 regs[i].regmap[hr]=-1;
8848 //Don't clear regs in the delay slot as the branch might need them
8849 //current.regmap[hr]=-1;
8850 }else
8851 regs[i].regmap_entry[hr]=r;
8852 }
8853 else {
8854 if((current.uu>>(r&63))&1) {
8855 regs[i].regmap_entry[hr]=-1;
8856 regs[i].regmap[hr]=-1;
8857 //Don't clear regs in the delay slot as the branch might need them
8858 //current.regmap[hr]=-1;
8859 }else
8860 regs[i].regmap_entry[hr]=r;
8861 }
8862 }
8863 } else {
8864 // First instruction expects CCREG to be allocated
8865 if(i==0&&hr==HOST_CCREG)
8866 regs[i].regmap_entry[hr]=CCREG;
8867 else
8868 regs[i].regmap_entry[hr]=-1;
8869 }
8870 }
8871 }
8872 else { // Not delay slot
8873 switch(itype[i]) {
8874 case UJUMP:
8875 //current.isconst=0; // DEBUG
8876 //current.wasconst=0; // DEBUG
8877 //regs[i].wasconst=0; // DEBUG
8878 clear_const(&current,rt1[i]);
8879 alloc_cc(&current,i);
8880 dirty_reg(&current,CCREG);
2adcd6fa 8881 ooo[i]=1;
8882 delayslot_alloc(&current,i+1);
57871462 8883 if (rt1[i]==31) {
8884 alloc_reg(&current,i,31);
8885 dirty_reg(&current,31);
4ef8f67d 8886 //assert(rs1[i+1]!=31&&rs2[i+1]!=31);
8887 //assert(rt1[i+1]!=rt1[i]);
57871462 8888 #ifdef REG_PREFETCH
8889 alloc_reg(&current,i,PTEMP);
8890 #endif
8891 //current.is32|=1LL<<rt1[i];
8892 }
57871462 8893 //current.isconst=0; // DEBUG
8894 ds=1;
8895 //printf("i=%d, isconst=%x\n",i,current.isconst);
8896 break;
8897 case RJUMP:
8898 //current.isconst=0;
8899 //current.wasconst=0;
8900 //regs[i].wasconst=0;
8901 clear_const(&current,rs1[i]);
8902 clear_const(&current,rt1[i]);
8903 alloc_cc(&current,i);
8904 dirty_reg(&current,CCREG);
8905 if(rs1[i]!=rt1[i+1]&&rs1[i]!=rt2[i+1]) {
8906 alloc_reg(&current,i,rs1[i]);
5067f341 8907 if (rt1[i]!=0) {
8908 alloc_reg(&current,i,rt1[i]);
8909 dirty_reg(&current,rt1[i]);
68b3faee 8910 assert(rs1[i+1]!=rt1[i]&&rs2[i+1]!=rt1[i]);
076655d1 8911 assert(rt1[i+1]!=rt1[i]);
57871462 8912 #ifdef REG_PREFETCH
8913 alloc_reg(&current,i,PTEMP);
8914 #endif
8915 }
8916 #ifdef USE_MINI_HT
8917 if(rs1[i]==31) { // JALR
8918 alloc_reg(&current,i,RHASH);
8919 #ifndef HOST_IMM_ADDR32
8920 alloc_reg(&current,i,RHTBL);
8921 #endif
8922 }
8923 #endif
8924 delayslot_alloc(&current,i+1);
8925 } else {
8926 // The delay slot overwrites our source register,
8927 // allocate a temporary register to hold the old value.
8928 current.isconst=0;
8929 current.wasconst=0;
8930 regs[i].wasconst=0;
8931 delayslot_alloc(&current,i+1);
8932 current.isconst=0;
8933 alloc_reg(&current,i,RTEMP);
8934 }
8935 //current.isconst=0; // DEBUG
e1190b87 8936 ooo[i]=1;
57871462 8937 ds=1;
8938 break;
8939 case CJUMP:
8940 //current.isconst=0;
8941 //current.wasconst=0;
8942 //regs[i].wasconst=0;
8943 clear_const(&current,rs1[i]);
8944 clear_const(&current,rs2[i]);
8945 if((opcode[i]&0x3E)==4) // BEQ/BNE
8946 {
8947 alloc_cc(&current,i);
8948 dirty_reg(&current,CCREG);
8949 if(rs1[i]) alloc_reg(&current,i,rs1[i]);
8950 if(rs2[i]) alloc_reg(&current,i,rs2[i]);
8951 if(!((current.is32>>rs1[i])&(current.is32>>rs2[i])&1))
8952 {
8953 if(rs1[i]) alloc_reg64(&current,i,rs1[i]);
8954 if(rs2[i]) alloc_reg64(&current,i,rs2[i]);
8955 }
8956 if((rs1[i]&&(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1]))||
8957 (rs2[i]&&(rs2[i]==rt1[i+1]||rs2[i]==rt2[i+1]))) {
8958 // The delay slot overwrites one of our conditions.
8959 // Allocate the branch condition registers instead.
57871462 8960 current.isconst=0;
8961 current.wasconst=0;
8962 regs[i].wasconst=0;
8963 if(rs1[i]) alloc_reg(&current,i,rs1[i]);
8964 if(rs2[i]) alloc_reg(&current,i,rs2[i]);
8965 if(!((current.is32>>rs1[i])&(current.is32>>rs2[i])&1))
8966 {
8967 if(rs1[i]) alloc_reg64(&current,i,rs1[i]);
8968 if(rs2[i]) alloc_reg64(&current,i,rs2[i]);
8969 }
8970 }
e1190b87 8971 else
8972 {
8973 ooo[i]=1;
8974 delayslot_alloc(&current,i+1);
8975 }
57871462 8976 }
8977 else
8978 if((opcode[i]&0x3E)==6) // BLEZ/BGTZ
8979 {
8980 alloc_cc(&current,i);
8981 dirty_reg(&current,CCREG);
8982 alloc_reg(&current,i,rs1[i]);
8983 if(!(current.is32>>rs1[i]&1))
8984 {
8985 alloc_reg64(&current,i,rs1[i]);
8986 }
8987 if(rs1[i]&&(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1])) {
8988 // The delay slot overwrites one of our conditions.
8989 // Allocate the branch condition registers instead.
57871462 8990 current.isconst=0;
8991 current.wasconst=0;
8992 regs[i].wasconst=0;
8993 if(rs1[i]) alloc_reg(&current,i,rs1[i]);
8994 if(!((current.is32>>rs1[i])&1))
8995 {
8996 if(rs1[i]) alloc_reg64(&current,i,rs1[i]);
8997 }
8998 }
e1190b87 8999 else
9000 {
9001 ooo[i]=1;
9002 delayslot_alloc(&current,i+1);
9003 }
57871462 9004 }
9005 else
9006 // Don't alloc the delay slot yet because we might not execute it
9007 if((opcode[i]&0x3E)==0x14) // BEQL/BNEL
9008 {
9009 current.isconst=0;
9010 current.wasconst=0;
9011 regs[i].wasconst=0;
9012 alloc_cc(&current,i);
9013 dirty_reg(&current,CCREG);
9014 alloc_reg(&current,i,rs1[i]);
9015 alloc_reg(&current,i,rs2[i]);
9016 if(!((current.is32>>rs1[i])&(current.is32>>rs2[i])&1))
9017 {
9018 alloc_reg64(&current,i,rs1[i]);
9019 alloc_reg64(&current,i,rs2[i]);
9020 }
9021 }
9022 else
9023 if((opcode[i]&0x3E)==0x16) // BLEZL/BGTZL
9024 {
9025 current.isconst=0;
9026 current.wasconst=0;
9027 regs[i].wasconst=0;
9028 alloc_cc(&current,i);
9029 dirty_reg(&current,CCREG);
9030 alloc_reg(&current,i,rs1[i]);
9031 if(!(current.is32>>rs1[i]&1))
9032 {
9033 alloc_reg64(&current,i,rs1[i]);
9034 }
9035 }
9036 ds=1;
9037 //current.isconst=0;
9038 break;
9039 case SJUMP:
9040 //current.isconst=0;
9041 //current.wasconst=0;
9042 //regs[i].wasconst=0;
9043 clear_const(&current,rs1[i]);
9044 clear_const(&current,rt1[i]);
9045 //if((opcode2[i]&0x1E)==0x0) // BLTZ/BGEZ
9046 if((opcode2[i]&0x0E)==0x0) // BLTZ/BGEZ
9047 {
9048 alloc_cc(&current,i);
9049 dirty_reg(&current,CCREG);
9050 alloc_reg(&current,i,rs1[i]);
9051 if(!(current.is32>>rs1[i]&1))
9052 {
9053 alloc_reg64(&current,i,rs1[i]);
9054 }
9055 if (rt1[i]==31) { // BLTZAL/BGEZAL
9056 alloc_reg(&current,i,31);
9057 dirty_reg(&current,31);
57871462 9058 //#ifdef REG_PREFETCH
9059 //alloc_reg(&current,i,PTEMP);
9060 //#endif
9061 //current.is32|=1LL<<rt1[i];
9062 }
e1190b87 9063 if((rs1[i]&&(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1])) // The delay slot overwrites the branch condition.
9064 ||(rt1[i]==31&&(rs1[i+1]==31||rs2[i+1]==31||rt1[i+1]==31||rt2[i+1]==31))) { // DS touches $ra
57871462 9065 // Allocate the branch condition registers instead.
57871462 9066 current.isconst=0;
9067 current.wasconst=0;
9068 regs[i].wasconst=0;
9069 if(rs1[i]) alloc_reg(&current,i,rs1[i]);
9070 if(!((current.is32>>rs1[i])&1))
9071 {
9072 if(rs1[i]) alloc_reg64(&current,i,rs1[i]);
9073 }
9074 }
e1190b87 9075 else
9076 {
9077 ooo[i]=1;
9078 delayslot_alloc(&current,i+1);
9079 }
57871462 9080 }
9081 else
9082 // Don't alloc the delay slot yet because we might not execute it
9083 if((opcode2[i]&0x1E)==0x2) // BLTZL/BGEZL
9084 {
9085 current.isconst=0;
9086 current.wasconst=0;
9087 regs[i].wasconst=0;
9088 alloc_cc(&current,i);
9089 dirty_reg(&current,CCREG);
9090 alloc_reg(&current,i,rs1[i]);
9091 if(!(current.is32>>rs1[i]&1))
9092 {
9093 alloc_reg64(&current,i,rs1[i]);
9094 }
9095 }
9096 ds=1;
9097 //current.isconst=0;
9098 break;
9099 case FJUMP:
9100 current.isconst=0;
9101 current.wasconst=0;
9102 regs[i].wasconst=0;
9103 if(likely[i]==0) // BC1F/BC1T
9104 {
9105 // TODO: Theoretically we can run out of registers here on x86.
9106 // The delay slot can allocate up to six, and we need to check
9107 // CSREG before executing the delay slot. Possibly we can drop
9108 // the cycle count and then reload it after checking that the
9109 // FPU is in a usable state, or don't do out-of-order execution.
9110 alloc_cc(&current,i);
9111 dirty_reg(&current,CCREG);
9112 alloc_reg(&current,i,FSREG);
9113 alloc_reg(&current,i,CSREG);
9114 if(itype[i+1]==FCOMP) {
9115 // The delay slot overwrites the branch condition.
9116 // Allocate the branch condition registers instead.
57871462 9117 alloc_cc(&current,i);
9118 dirty_reg(&current,CCREG);
9119 alloc_reg(&current,i,CSREG);
9120 alloc_reg(&current,i,FSREG);
9121 }
9122 else {
e1190b87 9123 ooo[i]=1;
57871462 9124 delayslot_alloc(&current,i+1);
9125 alloc_reg(&current,i+1,CSREG);
9126 }
9127 }
9128 else
9129 // Don't alloc the delay slot yet because we might not execute it
9130 if(likely[i]) // BC1FL/BC1TL
9131 {
9132 alloc_cc(&current,i);
9133 dirty_reg(&current,CCREG);
9134 alloc_reg(&current,i,CSREG);
9135 alloc_reg(&current,i,FSREG);
9136 }
9137 ds=1;
9138 current.isconst=0;
9139 break;
9140 case IMM16:
9141 imm16_alloc(&current,i);
9142 break;
9143 case LOAD:
9144 case LOADLR:
9145 load_alloc(&current,i);
9146 break;
9147 case STORE:
9148 case STORELR:
9149 store_alloc(&current,i);
9150 break;
9151 case ALU:
9152 alu_alloc(&current,i);
9153 break;
9154 case SHIFT:
9155 shift_alloc(&current,i);
9156 break;
9157 case MULTDIV:
9158 multdiv_alloc(&current,i);
9159 break;
9160 case SHIFTIMM:
9161 shiftimm_alloc(&current,i);
9162 break;
9163 case MOV:
9164 mov_alloc(&current,i);
9165 break;
9166 case COP0:
9167 cop0_alloc(&current,i);
9168 break;
9169 case COP1:
b9b61529 9170 case COP2:
57871462 9171 cop1_alloc(&current,i);
9172 break;
9173 case C1LS:
9174 c1ls_alloc(&current,i);
9175 break;
b9b61529 9176 case C2LS:
9177 c2ls_alloc(&current,i);
9178 break;
9179 case C2OP:
9180 c2op_alloc(&current,i);
9181 break;
57871462 9182 case FCONV:
9183 fconv_alloc(&current,i);
9184 break;
9185 case FLOAT:
9186 float_alloc(&current,i);
9187 break;
9188 case FCOMP:
9189 fcomp_alloc(&current,i);
9190 break;
9191 case SYSCALL:
7139f3c8 9192 case HLECALL:
1e973cb0 9193 case INTCALL:
57871462 9194 syscall_alloc(&current,i);
9195 break;
9196 case SPAN:
9197 pagespan_alloc(&current,i);
9198 break;
9199 }
9200
9201 // Drop the upper half of registers that have become 32-bit
9202 current.uu|=current.is32&((1LL<<rt1[i])|(1LL<<rt2[i]));
9203 if(itype[i]!=UJUMP&&itype[i]!=CJUMP&&itype[i]!=SJUMP&&itype[i]!=RJUMP&&itype[i]!=FJUMP) {
9204 current.uu&=~((1LL<<us1[i])|(1LL<<us2[i]));
9205 if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
9206 current.uu|=1;
9207 } else {
9208 current.uu|=current.is32&((1LL<<rt1[i+1])|(1LL<<rt2[i+1]));
9209 current.uu&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
9210 if((~current.uu>>rt1[i+1])&1) current.uu&=~((1LL<<dep1[i+1])|(1LL<<dep2[i+1]));
9211 current.uu&=~((1LL<<us1[i])|(1LL<<us2[i]));
9212 current.uu|=1;
9213 }
9214
9215 // Create entry (branch target) regmap
9216 for(hr=0;hr<HOST_REGS;hr++)
9217 {
9218 int r,or,er;
9219 r=current.regmap[hr];
9220 if(r>=0) {
9221 if(r!=regmap_pre[i][hr]) {
9222 // TODO: delay slot (?)
9223 or=get_reg(regmap_pre[i],r); // Get old mapping for this register
9224 if(or<0||(r&63)>=TEMPREG){
9225 regs[i].regmap_entry[hr]=-1;
9226 }
9227 else
9228 {
9229 // Just move it to a different register
9230 regs[i].regmap_entry[hr]=r;
9231 // If it was dirty before, it's still dirty
9232 if((regs[i].wasdirty>>or)&1) dirty_reg(&current,r&63);
9233 }
9234 }
9235 else
9236 {
9237 // Unneeded
9238 if(r==0){
9239 regs[i].regmap_entry[hr]=0;
9240 }
9241 else
9242 if(r<64){
9243 if((current.u>>r)&1) {
9244 regs[i].regmap_entry[hr]=-1;
9245 //regs[i].regmap[hr]=-1;
9246 current.regmap[hr]=-1;
9247 }else
9248 regs[i].regmap_entry[hr]=r;
9249 }
9250 else {
9251 if((current.uu>>(r&63))&1) {
9252 regs[i].regmap_entry[hr]=-1;
9253 //regs[i].regmap[hr]=-1;
9254 current.regmap[hr]=-1;
9255 }else
9256 regs[i].regmap_entry[hr]=r;
9257 }
9258 }
9259 } else {
9260 // Branches expect CCREG to be allocated at the target
9261 if(regmap_pre[i][hr]==CCREG)
9262 regs[i].regmap_entry[hr]=CCREG;
9263 else
9264 regs[i].regmap_entry[hr]=-1;
9265 }
9266 }
9267 memcpy(regs[i].regmap,current.regmap,sizeof(current.regmap));
9268 }
9269 /* Branch post-alloc */
9270 if(i>0)
9271 {
9272 current.was32=current.is32;
9273 current.wasdirty=current.dirty;
9274 switch(itype[i-1]) {
9275 case UJUMP:
9276 memcpy(&branch_regs[i-1],&current,sizeof(current));
9277 branch_regs[i-1].isconst=0;
9278 branch_regs[i-1].wasconst=0;
9279 branch_regs[i-1].u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i-1])|(1LL<<rs2[i-1]));
9280 branch_regs[i-1].uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i-1])|(1LL<<us2[i-1]));
9281 alloc_cc(&branch_regs[i-1],i-1);
9282 dirty_reg(&branch_regs[i-1],CCREG);
9283 if(rt1[i-1]==31) { // JAL
9284 alloc_reg(&branch_regs[i-1],i-1,31);
9285 dirty_reg(&branch_regs[i-1],31);
9286 branch_regs[i-1].is32|=1LL<<31;
9287 }
9288 memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
9289 memcpy(constmap[i],constmap[i-1],sizeof(current.constmap));
9290 break;
9291 case RJUMP:
9292 memcpy(&branch_regs[i-1],&current,sizeof(current));
9293 branch_regs[i-1].isconst=0;
9294 branch_regs[i-1].wasconst=0;
9295 branch_regs[i-1].u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i-1])|(1LL<<rs2[i-1]));
9296 branch_regs[i-1].uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i-1])|(1LL<<us2[i-1]));
9297 alloc_cc(&branch_regs[i-1],i-1);
9298 dirty_reg(&branch_regs[i-1],CCREG);
9299 alloc_reg(&branch_regs[i-1],i-1,rs1[i-1]);
5067f341 9300 if(rt1[i-1]!=0) { // JALR
9301 alloc_reg(&branch_regs[i-1],i-1,rt1[i-1]);
9302 dirty_reg(&branch_regs[i-1],rt1[i-1]);
9303 branch_regs[i-1].is32|=1LL<<rt1[i-1];
57871462 9304 }
9305 #ifdef USE_MINI_HT
9306 if(rs1[i-1]==31) { // JALR
9307 alloc_reg(&branch_regs[i-1],i-1,RHASH);
9308 #ifndef HOST_IMM_ADDR32
9309 alloc_reg(&branch_regs[i-1],i-1,RHTBL);
9310 #endif
9311 }
9312 #endif
9313 memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
9314 memcpy(constmap[i],constmap[i-1],sizeof(current.constmap));
9315 break;
9316 case CJUMP:
9317 if((opcode[i-1]&0x3E)==4) // BEQ/BNE
9318 {
9319 alloc_cc(&current,i-1);
9320 dirty_reg(&current,CCREG);
9321 if((rs1[i-1]&&(rs1[i-1]==rt1[i]||rs1[i-1]==rt2[i]))||
9322 (rs2[i-1]&&(rs2[i-1]==rt1[i]||rs2[i-1]==rt2[i]))) {
9323 // The delay slot overwrote one of our conditions
9324 // Delay slot goes after the test (in order)
9325 current.u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i]));
9326 current.uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i]));
9327 if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
9328 current.u|=1;
9329 current.uu|=1;
9330 delayslot_alloc(&current,i);
9331 current.isconst=0;
9332 }
9333 else
9334 {
9335 current.u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i-1])|(1LL<<rs2[i-1]));
9336 current.uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i-1])|(1LL<<us2[i-1]));
9337 // Alloc the branch condition registers
9338 if(rs1[i-1]) alloc_reg(&current,i-1,rs1[i-1]);
9339 if(rs2[i-1]) alloc_reg(&current,i-1,rs2[i-1]);
9340 if(!((current.is32>>rs1[i-1])&(current.is32>>rs2[i-1])&1))
9341 {
9342 if(rs1[i-1]) alloc_reg64(&current,i-1,rs1[i-1]);
9343 if(rs2[i-1]) alloc_reg64(&current,i-1,rs2[i-1]);
9344 }
9345 }
9346 memcpy(&branch_regs[i-1],&current,sizeof(current));
9347 branch_regs[i-1].isconst=0;
9348 branch_regs[i-1].wasconst=0;
9349 memcpy(&branch_regs[i-1].regmap_entry,&current.regmap,sizeof(current.regmap));
9350 memcpy(constmap[i],constmap[i-1],sizeof(current.constmap));
9351 }
9352 else
9353 if((opcode[i-1]&0x3E)==6) // BLEZ/BGTZ
9354 {
9355 alloc_cc(&current,i-1);
9356 dirty_reg(&current,CCREG);
9357 if(rs1[i-1]==rt1[i]||rs1[i-1]==rt2[i]) {
9358 // The delay slot overwrote the branch condition
9359 // Delay slot goes after the test (in order)
9360 current.u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i]));
9361 current.uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i]));
9362 if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
9363 current.u|=1;
9364 current.uu|=1;
9365 delayslot_alloc(&current,i);
9366 current.isconst=0;
9367 }
9368 else
9369 {
9370 current.u=branch_unneeded_reg[i-1]&~(1LL<<rs1[i-1]);
9371 current.uu=branch_unneeded_reg_upper[i-1]&~(1LL<<us1[i-1]);
9372 // Alloc the branch condition register
9373 alloc_reg(&current,i-1,rs1[i-1]);
9374 if(!(current.is32>>rs1[i-1]&1))
9375 {
9376 alloc_reg64(&current,i-1,rs1[i-1]);
9377 }
9378 }
9379 memcpy(&branch_regs[i-1],&current,sizeof(current));
9380 branch_regs[i-1].isconst=0;
9381 branch_regs[i-1].wasconst=0;
9382 memcpy(&branch_regs[i-1].regmap_entry,&current.regmap,sizeof(current.regmap));
9383 memcpy(constmap[i],constmap[i-1],sizeof(current.constmap));
9384 }
9385 else
9386 // Alloc the delay slot in case the branch is taken
9387 if((opcode[i-1]&0x3E)==0x14) // BEQL/BNEL
9388 {
9389 memcpy(&branch_regs[i-1],&current,sizeof(current));
9390 branch_regs[i-1].u=(branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9391 branch_regs[i-1].uu=(branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9392 if((~branch_regs[i-1].uu>>rt1[i])&1) branch_regs[i-1].uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]))|1;
9393 alloc_cc(&branch_regs[i-1],i);
9394 dirty_reg(&branch_regs[i-1],CCREG);
9395 delayslot_alloc(&branch_regs[i-1],i);
9396 branch_regs[i-1].isconst=0;
9397 alloc_reg(&current,i,CCREG); // Not taken path
9398 dirty_reg(&current,CCREG);
9399 memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
9400 }
9401 else
9402 if((opcode[i-1]&0x3E)==0x16) // BLEZL/BGTZL
9403 {
9404 memcpy(&branch_regs[i-1],&current,sizeof(current));
9405 branch_regs[i-1].u=(branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9406 branch_regs[i-1].uu=(branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9407 if((~branch_regs[i-1].uu>>rt1[i])&1) branch_regs[i-1].uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]))|1;
9408 alloc_cc(&branch_regs[i-1],i);
9409 dirty_reg(&branch_regs[i-1],CCREG);
9410 delayslot_alloc(&branch_regs[i-1],i);
9411 branch_regs[i-1].isconst=0;
9412 alloc_reg(&current,i,CCREG); // Not taken path
9413 dirty_reg(&current,CCREG);
9414 memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
9415 }
9416 break;
9417 case SJUMP:
9418 //if((opcode2[i-1]&0x1E)==0) // BLTZ/BGEZ
9419 if((opcode2[i-1]&0x0E)==0) // BLTZ/BGEZ
9420 {
9421 alloc_cc(&current,i-1);
9422 dirty_reg(&current,CCREG);
9423 if(rs1[i-1]==rt1[i]||rs1[i-1]==rt2[i]) {
9424 // The delay slot overwrote the branch condition
9425 // Delay slot goes after the test (in order)
9426 current.u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i]));
9427 current.uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i]));
9428 if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
9429 current.u|=1;
9430 current.uu|=1;
9431 delayslot_alloc(&current,i);
9432 current.isconst=0;
9433 }
9434 else
9435 {
9436 current.u=branch_unneeded_reg[i-1]&~(1LL<<rs1[i-1]);
9437 current.uu=branch_unneeded_reg_upper[i-1]&~(1LL<<us1[i-1]);
9438 // Alloc the branch condition register
9439 alloc_reg(&current,i-1,rs1[i-1]);
9440 if(!(current.is32>>rs1[i-1]&1))
9441 {
9442 alloc_reg64(&current,i-1,rs1[i-1]);
9443 }
9444 }
9445 memcpy(&branch_regs[i-1],&current,sizeof(current));
9446 branch_regs[i-1].isconst=0;
9447 branch_regs[i-1].wasconst=0;
9448 memcpy(&branch_regs[i-1].regmap_entry,&current.regmap,sizeof(current.regmap));
9449 memcpy(constmap[i],constmap[i-1],sizeof(current.constmap));
9450 }
9451 else
9452 // Alloc the delay slot in case the branch is taken
9453 if((opcode2[i-1]&0x1E)==2) // BLTZL/BGEZL
9454 {
9455 memcpy(&branch_regs[i-1],&current,sizeof(current));
9456 branch_regs[i-1].u=(branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9457 branch_regs[i-1].uu=(branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9458 if((~branch_regs[i-1].uu>>rt1[i])&1) branch_regs[i-1].uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]))|1;
9459 alloc_cc(&branch_regs[i-1],i);
9460 dirty_reg(&branch_regs[i-1],CCREG);
9461 delayslot_alloc(&branch_regs[i-1],i);
9462 branch_regs[i-1].isconst=0;
9463 alloc_reg(&current,i,CCREG); // Not taken path
9464 dirty_reg(&current,CCREG);
9465 memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
9466 }
9467 // FIXME: BLTZAL/BGEZAL
9468 if(opcode2[i-1]&0x10) { // BxxZAL
9469 alloc_reg(&branch_regs[i-1],i-1,31);
9470 dirty_reg(&branch_regs[i-1],31);
9471 branch_regs[i-1].is32|=1LL<<31;
9472 }
9473 break;
9474 case FJUMP:
9475 if(likely[i-1]==0) // BC1F/BC1T
9476 {
9477 alloc_cc(&current,i-1);
9478 dirty_reg(&current,CCREG);
9479 if(itype[i]==FCOMP) {
9480 // The delay slot overwrote the branch condition
9481 // Delay slot goes after the test (in order)
9482 delayslot_alloc(&current,i);
9483 current.isconst=0;
9484 }
9485 else
9486 {
9487 current.u=branch_unneeded_reg[i-1]&~(1LL<<rs1[i-1]);
9488 current.uu=branch_unneeded_reg_upper[i-1]&~(1LL<<us1[i-1]);
9489 // Alloc the branch condition register
9490 alloc_reg(&current,i-1,FSREG);
9491 }
9492 memcpy(&branch_regs[i-1],&current,sizeof(current));
9493 memcpy(&branch_regs[i-1].regmap_entry,&current.regmap,sizeof(current.regmap));
9494 }
9495 else // BC1FL/BC1TL
9496 {
9497 // Alloc the delay slot in case the branch is taken
9498 memcpy(&branch_regs[i-1],&current,sizeof(current));
9499 branch_regs[i-1].u=(branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9500 branch_regs[i-1].uu=(branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9501 if((~branch_regs[i-1].uu>>rt1[i])&1) branch_regs[i-1].uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]))|1;
9502 alloc_cc(&branch_regs[i-1],i);
9503 dirty_reg(&branch_regs[i-1],CCREG);
9504 delayslot_alloc(&branch_regs[i-1],i);
9505 branch_regs[i-1].isconst=0;
9506 alloc_reg(&current,i,CCREG); // Not taken path
9507 dirty_reg(&current,CCREG);
9508 memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
9509 }
9510 break;
9511 }
9512
9513 if(itype[i-1]==UJUMP||itype[i-1]==RJUMP||(source[i-1]>>16)==0x1000)
9514 {
9515 if(rt1[i-1]==31) // JAL/JALR
9516 {
9517 // Subroutine call will return here, don't alloc any registers
9518 current.is32=1;
9519 current.dirty=0;
9520 clear_all_regs(current.regmap);
9521 alloc_reg(&current,i,CCREG);
9522 dirty_reg(&current,CCREG);
9523 }
9524 else if(i+1<slen)
9525 {
9526 // Internal branch will jump here, match registers to caller
9527 current.is32=0x3FFFFFFFFLL;
9528 current.dirty=0;
9529 clear_all_regs(current.regmap);
9530 alloc_reg(&current,i,CCREG);
9531 dirty_reg(&current,CCREG);
9532 for(j=i-1;j>=0;j--)
9533 {
9534 if(ba[j]==start+i*4+4) {
9535 memcpy(current.regmap,branch_regs[j].regmap,sizeof(current.regmap));
9536 current.is32=branch_regs[j].is32;
9537 current.dirty=branch_regs[j].dirty;
9538 break;
9539 }
9540 }
9541 while(j>=0) {
9542 if(ba[j]==start+i*4+4) {
9543 for(hr=0;hr<HOST_REGS;hr++) {
9544 if(current.regmap[hr]!=branch_regs[j].regmap[hr]) {
9545 current.regmap[hr]=-1;
9546 }
9547 current.is32&=branch_regs[j].is32;
9548 current.dirty&=branch_regs[j].dirty;
9549 }
9550 }
9551 j--;
9552 }
9553 }
9554 }
9555 }
9556
9557 // Count cycles in between branches
9558 ccadj[i]=cc;
7139f3c8 9559 if(i>0&&(itype[i-1]==RJUMP||itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP||itype[i]==SYSCALL||itype[i]==HLECALL))
57871462 9560 {
9561 cc=0;
9562 }
fb407447 9563#ifdef PCSX
9564 else if(/*itype[i]==LOAD||*/itype[i]==STORE||itype[i]==C1LS) // load causes weird timing issues
9565 {
9566 cc+=2; // 2 cycle penalty (after CLOCK_DIVIDER)
9567 }
9568 else if(itype[i]==C2LS)
9569 {
9570 cc+=4;
9571 }
9572#endif
57871462 9573 else
9574 {
9575 cc++;
9576 }
9577
9578 flush_dirty_uppers(&current);
9579 if(!is_ds[i]) {
9580 regs[i].is32=current.is32;
9581 regs[i].dirty=current.dirty;
9582 regs[i].isconst=current.isconst;
9583 memcpy(constmap[i],current.constmap,sizeof(current.constmap));
9584 }
9585 for(hr=0;hr<HOST_REGS;hr++) {
9586 if(hr!=EXCLUDE_REG&&regs[i].regmap[hr]>=0) {
9587 if(regmap_pre[i][hr]!=regs[i].regmap[hr]) {
9588 regs[i].wasconst&=~(1<<hr);
9589 }
9590 }
9591 }
9592 if(current.regmap[HOST_BTREG]==BTREG) current.regmap[HOST_BTREG]=-1;
9593 }
9594
9595 /* Pass 4 - Cull unused host registers */
9596
9597 uint64_t nr=0;
9598
9599 for (i=slen-1;i>=0;i--)
9600 {
9601 int hr;
9602 if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
9603 {
9604 if(ba[i]<start || ba[i]>=(start+slen*4))
9605 {
9606 // Branch out of this block, don't need anything
9607 nr=0;
9608 }
9609 else
9610 {
9611 // Internal branch
9612 // Need whatever matches the target
9613 nr=0;
9614 int t=(ba[i]-start)>>2;
9615 for(hr=0;hr<HOST_REGS;hr++)
9616 {
9617 if(regs[i].regmap_entry[hr]>=0) {
9618 if(regs[i].regmap_entry[hr]==regs[t].regmap_entry[hr]) nr|=1<<hr;
9619 }
9620 }
9621 }
9622 // Conditional branch may need registers for following instructions
9623 if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000)
9624 {
9625 if(i<slen-2) {
9626 nr|=needed_reg[i+2];
9627 for(hr=0;hr<HOST_REGS;hr++)
9628 {
9629 if(regmap_pre[i+2][hr]>=0&&get_reg(regs[i+2].regmap_entry,regmap_pre[i+2][hr])<0) nr&=~(1<<hr);
9630 //if((regmap_entry[i+2][hr])>=0) if(!((nr>>hr)&1)) printf("%x-bogus(%d=%d)\n",start+i*4,hr,regmap_entry[i+2][hr]);
9631 }
9632 }
9633 }
9634 // Don't need stuff which is overwritten
f5955059 9635 //if(regs[i].regmap[hr]!=regmap_pre[i][hr]) nr&=~(1<<hr);
9636 //if(regs[i].regmap[hr]<0) nr&=~(1<<hr);
57871462 9637 // Merge in delay slot
9638 for(hr=0;hr<HOST_REGS;hr++)
9639 {
9640 if(!likely[i]) {
9641 // These are overwritten unless the branch is "likely"
9642 // and the delay slot is nullified if not taken
9643 if(rt1[i+1]&&rt1[i+1]==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
9644 if(rt2[i+1]&&rt2[i+1]==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
9645 }
9646 if(us1[i+1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9647 if(us2[i+1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9648 if(rs1[i+1]==regmap_pre[i][hr]) nr|=1<<hr;
9649 if(rs2[i+1]==regmap_pre[i][hr]) nr|=1<<hr;
9650 if(us1[i+1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9651 if(us2[i+1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9652 if(rs1[i+1]==regs[i].regmap_entry[hr]) nr|=1<<hr;
9653 if(rs2[i+1]==regs[i].regmap_entry[hr]) nr|=1<<hr;
9654 if(dep1[i+1]&&!((unneeded_reg_upper[i]>>dep1[i+1])&1)) {
9655 if(dep1[i+1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9656 if(dep2[i+1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9657 }
9658 if(dep2[i+1]&&!((unneeded_reg_upper[i]>>dep2[i+1])&1)) {
9659 if(dep1[i+1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9660 if(dep2[i+1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9661 }
b9b61529 9662 if(itype[i+1]==STORE || itype[i+1]==STORELR || (opcode[i+1]&0x3b)==0x39 || (opcode[i+1]&0x3b)==0x3a) {
57871462 9663 if(regmap_pre[i][hr]==INVCP) nr|=1<<hr;
9664 if(regs[i].regmap_entry[hr]==INVCP) nr|=1<<hr;
9665 }
9666 }
9667 }
1e973cb0 9668 else if(itype[i]==SYSCALL||itype[i]==HLECALL||itype[i]==INTCALL)
57871462 9669 {
9670 // SYSCALL instruction (software interrupt)
9671 nr=0;
9672 }
9673 else if(itype[i]==COP0 && (source[i]&0x3f)==0x18)
9674 {
9675 // ERET instruction (return from interrupt)
9676 nr=0;
9677 }
9678 else // Non-branch
9679 {
9680 if(i<slen-1) {
9681 for(hr=0;hr<HOST_REGS;hr++) {
9682 if(regmap_pre[i+1][hr]>=0&&get_reg(regs[i+1].regmap_entry,regmap_pre[i+1][hr])<0) nr&=~(1<<hr);
9683 if(regs[i].regmap[hr]!=regmap_pre[i+1][hr]) nr&=~(1<<hr);
9684 if(regs[i].regmap[hr]!=regmap_pre[i][hr]) nr&=~(1<<hr);
9685 if(regs[i].regmap[hr]<0) nr&=~(1<<hr);
9686 }
9687 }
9688 }
9689 for(hr=0;hr<HOST_REGS;hr++)
9690 {
9691 // Overwritten registers are not needed
9692 if(rt1[i]&&rt1[i]==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
9693 if(rt2[i]&&rt2[i]==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
9694 if(FTEMP==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
9695 // Source registers are needed
9696 if(us1[i]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9697 if(us2[i]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9698 if(rs1[i]==regmap_pre[i][hr]) nr|=1<<hr;
9699 if(rs2[i]==regmap_pre[i][hr]) nr|=1<<hr;
9700 if(us1[i]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9701 if(us2[i]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9702 if(rs1[i]==regs[i].regmap_entry[hr]) nr|=1<<hr;
9703 if(rs2[i]==regs[i].regmap_entry[hr]) nr|=1<<hr;
9704 if(dep1[i]&&!((unneeded_reg_upper[i]>>dep1[i])&1)) {
9705 if(dep1[i]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9706 if(dep1[i]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9707 }
9708 if(dep2[i]&&!((unneeded_reg_upper[i]>>dep2[i])&1)) {
9709 if(dep2[i]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9710 if(dep2[i]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9711 }
b9b61529 9712 if(itype[i]==STORE || itype[i]==STORELR || (opcode[i]&0x3b)==0x39 || (opcode[i]&0x3b)==0x3a) {
57871462 9713 if(regmap_pre[i][hr]==INVCP) nr|=1<<hr;
9714 if(regs[i].regmap_entry[hr]==INVCP) nr|=1<<hr;
9715 }
9716 // Don't store a register immediately after writing it,
9717 // may prevent dual-issue.
9718 // But do so if this is a branch target, otherwise we
9719 // might have to load the register before the branch.
9720 if(i>0&&!bt[i]&&((regs[i].wasdirty>>hr)&1)) {
9721 if((regmap_pre[i][hr]>0&&regmap_pre[i][hr]<64&&!((unneeded_reg[i]>>regmap_pre[i][hr])&1)) ||
9722 (regmap_pre[i][hr]>64&&!((unneeded_reg_upper[i]>>(regmap_pre[i][hr]&63))&1)) ) {
9723 if(rt1[i-1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9724 if(rt2[i-1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9725 }
9726 if((regs[i].regmap_entry[hr]>0&&regs[i].regmap_entry[hr]<64&&!((unneeded_reg[i]>>regs[i].regmap_entry[hr])&1)) ||
9727 (regs[i].regmap_entry[hr]>64&&!((unneeded_reg_upper[i]>>(regs[i].regmap_entry[hr]&63))&1)) ) {
9728 if(rt1[i-1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9729 if(rt2[i-1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9730 }
9731 }
9732 }
9733 // Cycle count is needed at branches. Assume it is needed at the target too.
9734 if(i==0||bt[i]||itype[i]==CJUMP||itype[i]==FJUMP||itype[i]==SPAN) {
9735 if(regmap_pre[i][HOST_CCREG]==CCREG) nr|=1<<HOST_CCREG;
9736 if(regs[i].regmap_entry[HOST_CCREG]==CCREG) nr|=1<<HOST_CCREG;
9737 }
9738 // Save it
9739 needed_reg[i]=nr;
9740
9741 // Deallocate unneeded registers
9742 for(hr=0;hr<HOST_REGS;hr++)
9743 {
9744 if(!((nr>>hr)&1)) {
9745 if(regs[i].regmap_entry[hr]!=CCREG) regs[i].regmap_entry[hr]=-1;
9746 if((regs[i].regmap[hr]&63)!=rs1[i] && (regs[i].regmap[hr]&63)!=rs2[i] &&
9747 (regs[i].regmap[hr]&63)!=rt1[i] && (regs[i].regmap[hr]&63)!=rt2[i] &&
9748 (regs[i].regmap[hr]&63)!=PTEMP && (regs[i].regmap[hr]&63)!=CCREG)
9749 {
9750 if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000)
9751 {
9752 if(likely[i]) {
9753 regs[i].regmap[hr]=-1;
9754 regs[i].isconst&=~(1<<hr);
79c75f1b 9755 if(i<slen-2) {
9756 regmap_pre[i+2][hr]=-1;
9757 regs[i+2].wasconst&=~(1<<hr);
9758 }
57871462 9759 }
9760 }
9761 }
9762 if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
9763 {
9764 int d1=0,d2=0,map=0,temp=0;
9765 if(get_reg(regs[i].regmap,rt1[i+1]|64)>=0||get_reg(branch_regs[i].regmap,rt1[i+1]|64)>=0)
9766 {
9767 d1=dep1[i+1];
9768 d2=dep2[i+1];
9769 }
9770 if(using_tlb) {
9771 if(itype[i+1]==LOAD || itype[i+1]==LOADLR ||
9772 itype[i+1]==STORE || itype[i+1]==STORELR ||
b9b61529 9773 itype[i+1]==C1LS || itype[i+1]==C2LS)
57871462 9774 map=TLREG;
9775 } else
b9b61529 9776 if(itype[i+1]==STORE || itype[i+1]==STORELR ||
9777 (opcode[i+1]&0x3b)==0x39 || (opcode[i+1]&0x3b)==0x3a) { // SWC1/SDC1 || SWC2/SDC2
57871462 9778 map=INVCP;
9779 }
9780 if(itype[i+1]==LOADLR || itype[i+1]==STORELR ||
b9b61529 9781 itype[i+1]==C1LS || itype[i+1]==C2LS)
57871462 9782 temp=FTEMP;
9783 if((regs[i].regmap[hr]&63)!=rs1[i] && (regs[i].regmap[hr]&63)!=rs2[i] &&
9784 (regs[i].regmap[hr]&63)!=rt1[i] && (regs[i].regmap[hr]&63)!=rt2[i] &&
9785 (regs[i].regmap[hr]&63)!=rt1[i+1] && (regs[i].regmap[hr]&63)!=rt2[i+1] &&
9786 (regs[i].regmap[hr]^64)!=us1[i+1] && (regs[i].regmap[hr]^64)!=us2[i+1] &&
9787 (regs[i].regmap[hr]^64)!=d1 && (regs[i].regmap[hr]^64)!=d2 &&
9788 regs[i].regmap[hr]!=rs1[i+1] && regs[i].regmap[hr]!=rs2[i+1] &&
9789 (regs[i].regmap[hr]&63)!=temp && regs[i].regmap[hr]!=PTEMP &&
9790 regs[i].regmap[hr]!=RHASH && regs[i].regmap[hr]!=RHTBL &&
9791 regs[i].regmap[hr]!=RTEMP && regs[i].regmap[hr]!=CCREG &&
9792 regs[i].regmap[hr]!=map )
9793 {
9794 regs[i].regmap[hr]=-1;
9795 regs[i].isconst&=~(1<<hr);
9796 if((branch_regs[i].regmap[hr]&63)!=rs1[i] && (branch_regs[i].regmap[hr]&63)!=rs2[i] &&
9797 (branch_regs[i].regmap[hr]&63)!=rt1[i] && (branch_regs[i].regmap[hr]&63)!=rt2[i] &&
9798 (branch_regs[i].regmap[hr]&63)!=rt1[i+1] && (branch_regs[i].regmap[hr]&63)!=rt2[i+1] &&
9799 (branch_regs[i].regmap[hr]^64)!=us1[i+1] && (branch_regs[i].regmap[hr]^64)!=us2[i+1] &&
9800 (branch_regs[i].regmap[hr]^64)!=d1 && (branch_regs[i].regmap[hr]^64)!=d2 &&
9801 branch_regs[i].regmap[hr]!=rs1[i+1] && branch_regs[i].regmap[hr]!=rs2[i+1] &&
9802 (branch_regs[i].regmap[hr]&63)!=temp && branch_regs[i].regmap[hr]!=PTEMP &&
9803 branch_regs[i].regmap[hr]!=RHASH && branch_regs[i].regmap[hr]!=RHTBL &&
9804 branch_regs[i].regmap[hr]!=RTEMP && branch_regs[i].regmap[hr]!=CCREG &&
9805 branch_regs[i].regmap[hr]!=map)
9806 {
9807 branch_regs[i].regmap[hr]=-1;
9808 branch_regs[i].regmap_entry[hr]=-1;
9809 if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000)
9810 {
9811 if(!likely[i]&&i<slen-2) {
9812 regmap_pre[i+2][hr]=-1;
79c75f1b 9813 regs[i+2].wasconst&=~(1<<hr);
57871462 9814 }
9815 }
9816 }
9817 }
9818 }
9819 else
9820 {
9821 // Non-branch
9822 if(i>0)
9823 {
9824 int d1=0,d2=0,map=-1,temp=-1;
9825 if(get_reg(regs[i].regmap,rt1[i]|64)>=0)
9826 {
9827 d1=dep1[i];
9828 d2=dep2[i];
9829 }
9830 if(using_tlb) {
9831 if(itype[i]==LOAD || itype[i]==LOADLR ||
9832 itype[i]==STORE || itype[i]==STORELR ||
b9b61529 9833 itype[i]==C1LS || itype[i]==C2LS)
57871462 9834 map=TLREG;
b9b61529 9835 } else if(itype[i]==STORE || itype[i]==STORELR ||
9836 (opcode[i]&0x3b)==0x39 || (opcode[i]&0x3b)==0x3a) { // SWC1/SDC1 || SWC2/SDC2
57871462 9837 map=INVCP;
9838 }
9839 if(itype[i]==LOADLR || itype[i]==STORELR ||
b9b61529 9840 itype[i]==C1LS || itype[i]==C2LS)
57871462 9841 temp=FTEMP;
9842 if((regs[i].regmap[hr]&63)!=rt1[i] && (regs[i].regmap[hr]&63)!=rt2[i] &&
9843 (regs[i].regmap[hr]^64)!=us1[i] && (regs[i].regmap[hr]^64)!=us2[i] &&
9844 (regs[i].regmap[hr]^64)!=d1 && (regs[i].regmap[hr]^64)!=d2 &&
9845 regs[i].regmap[hr]!=rs1[i] && regs[i].regmap[hr]!=rs2[i] &&
9846 (regs[i].regmap[hr]&63)!=temp && regs[i].regmap[hr]!=map &&
9847 (itype[i]!=SPAN||regs[i].regmap[hr]!=CCREG))
9848 {
9849 if(i<slen-1&&!is_ds[i]) {
9850 if(regmap_pre[i+1][hr]!=-1 || regs[i].regmap[hr]!=-1)
9851 if(regmap_pre[i+1][hr]!=regs[i].regmap[hr])
9852 if(regs[i].regmap[hr]<64||!((regs[i].was32>>(regs[i].regmap[hr]&63))&1))
9853 {
9854 printf("fail: %x (%d %d!=%d)\n",start+i*4,hr,regmap_pre[i+1][hr],regs[i].regmap[hr]);
9855 assert(regmap_pre[i+1][hr]==regs[i].regmap[hr]);
9856 }
9857 regmap_pre[i+1][hr]=-1;
9858 if(regs[i+1].regmap_entry[hr]==CCREG) regs[i+1].regmap_entry[hr]=-1;
79c75f1b 9859 regs[i+1].wasconst&=~(1<<hr);
57871462 9860 }
9861 regs[i].regmap[hr]=-1;
9862 regs[i].isconst&=~(1<<hr);
9863 }
9864 }
9865 }
9866 }
9867 }
9868 }
9869
9870 /* Pass 5 - Pre-allocate registers */
9871
9872 // If a register is allocated during a loop, try to allocate it for the
9873 // entire loop, if possible. This avoids loading/storing registers
9874 // inside of the loop.
9875
9876 signed char f_regmap[HOST_REGS];
9877 clear_all_regs(f_regmap);
9878 for(i=0;i<slen-1;i++)
9879 {
9880 if(itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
9881 {
9882 if(ba[i]>=start && ba[i]<(start+i*4))
9883 if(itype[i+1]==NOP||itype[i+1]==MOV||itype[i+1]==ALU
9884 ||itype[i+1]==SHIFTIMM||itype[i+1]==IMM16||itype[i+1]==LOAD
9885 ||itype[i+1]==STORE||itype[i+1]==STORELR||itype[i+1]==C1LS
9886 ||itype[i+1]==SHIFT||itype[i+1]==COP1||itype[i+1]==FLOAT
b9b61529 9887 ||itype[i+1]==FCOMP||itype[i+1]==FCONV
9888 ||itype[i+1]==COP2||itype[i+1]==C2LS||itype[i+1]==C2OP)
57871462 9889 {
9890 int t=(ba[i]-start)>>2;
9891 if(t>0&&(itype[t-1]!=UJUMP&&itype[t-1]!=RJUMP&&itype[t-1]!=CJUMP&&itype[t-1]!=SJUMP&&itype[t-1]!=FJUMP)) // loop_preload can't handle jumps into delay slots
9892 if(t<2||(itype[t-2]!=UJUMP)) // call/ret assumes no registers allocated
9893 for(hr=0;hr<HOST_REGS;hr++)
9894 {
9895 if(regs[i].regmap[hr]>64) {
9896 if(!((regs[i].dirty>>hr)&1))
9897 f_regmap[hr]=regs[i].regmap[hr];
9898 else f_regmap[hr]=-1;
9899 }
b372a952 9900 else if(regs[i].regmap[hr]>=0) {
9901 if(f_regmap[hr]!=regs[i].regmap[hr]) {
9902 // dealloc old register
9903 int n;
9904 for(n=0;n<HOST_REGS;n++)
9905 {
9906 if(f_regmap[n]==regs[i].regmap[hr]) {f_regmap[n]=-1;}
9907 }
9908 // and alloc new one
9909 f_regmap[hr]=regs[i].regmap[hr];
9910 }
9911 }
57871462 9912 if(branch_regs[i].regmap[hr]>64) {
9913 if(!((branch_regs[i].dirty>>hr)&1))
9914 f_regmap[hr]=branch_regs[i].regmap[hr];
9915 else f_regmap[hr]=-1;
9916 }
b372a952 9917 else if(branch_regs[i].regmap[hr]>=0) {
9918 if(f_regmap[hr]!=branch_regs[i].regmap[hr]) {
9919 // dealloc old register
9920 int n;
9921 for(n=0;n<HOST_REGS;n++)
9922 {
9923 if(f_regmap[n]==branch_regs[i].regmap[hr]) {f_regmap[n]=-1;}
9924 }
9925 // and alloc new one
9926 f_regmap[hr]=branch_regs[i].regmap[hr];
9927 }
9928 }
e1190b87 9929 if(ooo[i]) {
9930 if(count_free_regs(regs[i].regmap)<=minimum_free_regs[i+1])
9931 f_regmap[hr]=branch_regs[i].regmap[hr];
9932 }else{
9933 if(count_free_regs(branch_regs[i].regmap)<=minimum_free_regs[i+1])
57871462 9934 f_regmap[hr]=branch_regs[i].regmap[hr];
9935 }
9936 // Avoid dirty->clean transition
e1190b87 9937 #ifdef DESTRUCTIVE_WRITEBACK
57871462 9938 if(t>0) if(get_reg(regmap_pre[t],f_regmap[hr])>=0) if((regs[t].wasdirty>>get_reg(regmap_pre[t],f_regmap[hr]))&1) f_regmap[hr]=-1;
e1190b87 9939 #endif
9940 // This check is only strictly required in the DESTRUCTIVE_WRITEBACK
9941 // case above, however it's always a good idea. We can't hoist the
9942 // load if the register was already allocated, so there's no point
9943 // wasting time analyzing most of these cases. It only "succeeds"
9944 // when the mapping was different and the load can be replaced with
9945 // a mov, which is of negligible benefit. So such cases are
9946 // skipped below.
57871462 9947 if(f_regmap[hr]>0) {
e1190b87 9948 if(regs[t].regmap_entry[hr]<0&&get_reg(regmap_pre[t],f_regmap[hr])<0) {
57871462 9949 int r=f_regmap[hr];
9950 for(j=t;j<=i;j++)
9951 {
9952 //printf("Test %x -> %x, %x %d/%d\n",start+i*4,ba[i],start+j*4,hr,r);
9953 if(r<34&&((unneeded_reg[j]>>r)&1)) break;
9954 if(r>63&&((unneeded_reg_upper[j]>>(r&63))&1)) break;
9955 if(r>63) {
9956 // NB This can exclude the case where the upper-half
9957 // register is lower numbered than the lower-half
9958 // register. Not sure if it's worth fixing...
9959 if(get_reg(regs[j].regmap,r&63)<0) break;
e1190b87 9960 if(get_reg(regs[j].regmap_entry,r&63)<0) break;
57871462 9961 if(regs[j].is32&(1LL<<(r&63))) break;
9962 }
9963 if(regs[j].regmap[hr]==f_regmap[hr]&&(f_regmap[hr]&63)<TEMPREG) {
9964 //printf("Hit %x -> %x, %x %d/%d\n",start+i*4,ba[i],start+j*4,hr,r);
9965 int k;
9966 if(regs[i].regmap[hr]==-1&&branch_regs[i].regmap[hr]==-1) {
9967 if(get_reg(regs[i+2].regmap,f_regmap[hr])>=0) break;
9968 if(r>63) {
9969 if(get_reg(regs[i].regmap,r&63)<0) break;
9970 if(get_reg(branch_regs[i].regmap,r&63)<0) break;
9971 }
9972 k=i;
9973 while(k>1&&regs[k-1].regmap[hr]==-1) {
e1190b87 9974 if(count_free_regs(regs[k-1].regmap)<=minimum_free_regs[k-1]) {
9975 //printf("no free regs for store %x\n",start+(k-1)*4);
9976 break;
57871462 9977 }
57871462 9978 if(get_reg(regs[k-1].regmap,f_regmap[hr])>=0) {
9979 //printf("no-match due to different register\n");
9980 break;
9981 }
9982 if(itype[k-2]==UJUMP||itype[k-2]==RJUMP||itype[k-2]==CJUMP||itype[k-2]==SJUMP||itype[k-2]==FJUMP) {
9983 //printf("no-match due to branch\n");
9984 break;
9985 }
9986 // call/ret fast path assumes no registers allocated
9987 if(k>2&&(itype[k-3]==UJUMP||itype[k-3]==RJUMP)) {
9988 break;
9989 }
9990 if(r>63) {
9991 // NB This can exclude the case where the upper-half
9992 // register is lower numbered than the lower-half
9993 // register. Not sure if it's worth fixing...
9994 if(get_reg(regs[k-1].regmap,r&63)<0) break;
9995 if(regs[k-1].is32&(1LL<<(r&63))) break;
9996 }
9997 k--;
9998 }
9999 if(i<slen-1) {
10000 if((regs[k].is32&(1LL<<f_regmap[hr]))!=
10001 (regs[i+2].was32&(1LL<<f_regmap[hr]))) {
10002 //printf("bad match after branch\n");
10003 break;
10004 }
10005 }
10006 if(regs[k-1].regmap[hr]==f_regmap[hr]&&regmap_pre[k][hr]==f_regmap[hr]) {
10007 //printf("Extend r%d, %x ->\n",hr,start+k*4);
10008 while(k<i) {
10009 regs[k].regmap_entry[hr]=f_regmap[hr];
10010 regs[k].regmap[hr]=f_regmap[hr];
10011 regmap_pre[k+1][hr]=f_regmap[hr];
10012 regs[k].wasdirty&=~(1<<hr);
10013 regs[k].dirty&=~(1<<hr);
10014 regs[k].wasdirty|=(1<<hr)&regs[k-1].dirty;
10015 regs[k].dirty|=(1<<hr)&regs[k].wasdirty;
10016 regs[k].wasconst&=~(1<<hr);
10017 regs[k].isconst&=~(1<<hr);
10018 k++;
10019 }
10020 }
10021 else {
10022 //printf("Fail Extend r%d, %x ->\n",hr,start+k*4);
10023 break;
10024 }
10025 assert(regs[i-1].regmap[hr]==f_regmap[hr]);
10026 if(regs[i-1].regmap[hr]==f_regmap[hr]&&regmap_pre[i][hr]==f_regmap[hr]) {
10027 //printf("OK fill %x (r%d)\n",start+i*4,hr);
10028 regs[i].regmap_entry[hr]=f_regmap[hr];
10029 regs[i].regmap[hr]=f_regmap[hr];
10030 regs[i].wasdirty&=~(1<<hr);
10031 regs[i].dirty&=~(1<<hr);
10032 regs[i].wasdirty|=(1<<hr)&regs[i-1].dirty;
10033 regs[i].dirty|=(1<<hr)&regs[i-1].dirty;
10034 regs[i].wasconst&=~(1<<hr);
10035 regs[i].isconst&=~(1<<hr);
10036 branch_regs[i].regmap_entry[hr]=f_regmap[hr];
10037 branch_regs[i].wasdirty&=~(1<<hr);
10038 branch_regs[i].wasdirty|=(1<<hr)&regs[i].dirty;
10039 branch_regs[i].regmap[hr]=f_regmap[hr];
10040 branch_regs[i].dirty&=~(1<<hr);
10041 branch_regs[i].dirty|=(1<<hr)&regs[i].dirty;
10042 branch_regs[i].wasconst&=~(1<<hr);
10043 branch_regs[i].isconst&=~(1<<hr);
10044 if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000) {
10045 regmap_pre[i+2][hr]=f_regmap[hr];
10046 regs[i+2].wasdirty&=~(1<<hr);
10047 regs[i+2].wasdirty|=(1<<hr)&regs[i].dirty;
10048 assert((branch_regs[i].is32&(1LL<<f_regmap[hr]))==
10049 (regs[i+2].was32&(1LL<<f_regmap[hr])));
10050 }
10051 }
10052 }
10053 for(k=t;k<j;k++) {
e1190b87 10054 // Alloc register clean at beginning of loop,
10055 // but may dirty it in pass 6
57871462 10056 regs[k].regmap_entry[hr]=f_regmap[hr];
10057 regs[k].regmap[hr]=f_regmap[hr];
57871462 10058 regs[k].dirty&=~(1<<hr);
10059 regs[k].wasconst&=~(1<<hr);
10060 regs[k].isconst&=~(1<<hr);
e1190b87 10061 if(itype[k]==UJUMP||itype[k]==RJUMP||itype[k]==CJUMP||itype[k]==SJUMP||itype[k]==FJUMP) {
10062 branch_regs[k].regmap_entry[hr]=f_regmap[hr];
10063 branch_regs[k].regmap[hr]=f_regmap[hr];
10064 branch_regs[k].dirty&=~(1<<hr);
10065 branch_regs[k].wasconst&=~(1<<hr);
10066 branch_regs[k].isconst&=~(1<<hr);
10067 if(itype[k]!=RJUMP&&itype[k]!=UJUMP&&(source[k]>>16)!=0x1000) {
10068 regmap_pre[k+2][hr]=f_regmap[hr];
10069 regs[k+2].wasdirty&=~(1<<hr);
10070 assert((branch_regs[k].is32&(1LL<<f_regmap[hr]))==
10071 (regs[k+2].was32&(1LL<<f_regmap[hr])));
10072 }
10073 }
10074 else
10075 {
10076 regmap_pre[k+1][hr]=f_regmap[hr];
10077 regs[k+1].wasdirty&=~(1<<hr);
10078 }
57871462 10079 }
10080 if(regs[j].regmap[hr]==f_regmap[hr])
10081 regs[j].regmap_entry[hr]=f_regmap[hr];
10082 break;
10083 }
10084 if(j==i) break;
10085 if(regs[j].regmap[hr]>=0)
10086 break;
10087 if(get_reg(regs[j].regmap,f_regmap[hr])>=0) {
10088 //printf("no-match due to different register\n");
10089 break;
10090 }
10091 if((regs[j+1].is32&(1LL<<f_regmap[hr]))!=(regs[j].is32&(1LL<<f_regmap[hr]))) {
10092 //printf("32/64 mismatch %x %d\n",start+j*4,hr);
10093 break;
10094 }
e1190b87 10095 if(itype[j]==UJUMP||itype[j]==RJUMP||(source[j]>>16)==0x1000)
10096 {
10097 // Stop on unconditional branch
10098 break;
10099 }
10100 if(itype[j]==CJUMP||itype[j]==SJUMP||itype[j]==FJUMP)
10101 {
10102 if(ooo[j]) {
10103 if(count_free_regs(regs[j].regmap)<=minimum_free_regs[j+1])
10104 break;
10105 }else{
10106 if(count_free_regs(branch_regs[j].regmap)<=minimum_free_regs[j+1])
10107 break;
10108 }
10109 if(get_reg(branch_regs[j].regmap,f_regmap[hr])>=0) {
10110 //printf("no-match due to different register (branch)\n");
57871462 10111 break;
10112 }
10113 }
e1190b87 10114 if(count_free_regs(regs[j].regmap)<=minimum_free_regs[j]) {
10115 //printf("No free regs for store %x\n",start+j*4);
10116 break;
10117 }
57871462 10118 if(f_regmap[hr]>=64) {
10119 if(regs[j].is32&(1LL<<(f_regmap[hr]&63))) {
10120 break;
10121 }
10122 else
10123 {
10124 if(get_reg(regs[j].regmap,f_regmap[hr]&63)<0) {
10125 break;
10126 }
10127 }
10128 }
10129 }
10130 }
10131 }
10132 }
10133 }
10134 }else{
10135 int count=0;
10136 for(hr=0;hr<HOST_REGS;hr++)
10137 {
10138 if(hr!=EXCLUDE_REG) {
10139 if(regs[i].regmap[hr]>64) {
10140 if(!((regs[i].dirty>>hr)&1))
10141 f_regmap[hr]=regs[i].regmap[hr];
10142 }
b372a952 10143 else if(regs[i].regmap[hr]>=0) {
10144 if(f_regmap[hr]!=regs[i].regmap[hr]) {
10145 // dealloc old register
10146 int n;
10147 for(n=0;n<HOST_REGS;n++)
10148 {
10149 if(f_regmap[n]==regs[i].regmap[hr]) {f_regmap[n]=-1;}
10150 }
10151 // and alloc new one
10152 f_regmap[hr]=regs[i].regmap[hr];
10153 }
10154 }
57871462 10155 else if(regs[i].regmap[hr]<0) count++;
10156 }
10157 }
10158 // Try to restore cycle count at branch targets
10159 if(bt[i]) {
10160 for(j=i;j<slen-1;j++) {
10161 if(regs[j].regmap[HOST_CCREG]!=-1) break;
e1190b87 10162 if(count_free_regs(regs[j].regmap)<=minimum_free_regs[j]) {
10163 //printf("no free regs for store %x\n",start+j*4);
10164 break;
57871462 10165 }
57871462 10166 }
10167 if(regs[j].regmap[HOST_CCREG]==CCREG) {
10168 int k=i;
10169 //printf("Extend CC, %x -> %x\n",start+k*4,start+j*4);
10170 while(k<j) {
10171 regs[k].regmap_entry[HOST_CCREG]=CCREG;
10172 regs[k].regmap[HOST_CCREG]=CCREG;
10173 regmap_pre[k+1][HOST_CCREG]=CCREG;
10174 regs[k+1].wasdirty|=1<<HOST_CCREG;
10175 regs[k].dirty|=1<<HOST_CCREG;
10176 regs[k].wasconst&=~(1<<HOST_CCREG);
10177 regs[k].isconst&=~(1<<HOST_CCREG);
10178 k++;
10179 }
10180 regs[j].regmap_entry[HOST_CCREG]=CCREG;
10181 }
10182 // Work backwards from the branch target
10183 if(j>i&&f_regmap[HOST_CCREG]==CCREG)
10184 {
10185 //printf("Extend backwards\n");
10186 int k;
10187 k=i;
10188 while(regs[k-1].regmap[HOST_CCREG]==-1) {
e1190b87 10189 if(count_free_regs(regs[k-1].regmap)<=minimum_free_regs[k-1]) {
10190 //printf("no free regs for store %x\n",start+(k-1)*4);
10191 break;
57871462 10192 }
57871462 10193 k--;
10194 }
10195 if(regs[k-1].regmap[HOST_CCREG]==CCREG) {
10196 //printf("Extend CC, %x ->\n",start+k*4);
10197 while(k<=i) {
10198 regs[k].regmap_entry[HOST_CCREG]=CCREG;
10199 regs[k].regmap[HOST_CCREG]=CCREG;
10200 regmap_pre[k+1][HOST_CCREG]=CCREG;
10201 regs[k+1].wasdirty|=1<<HOST_CCREG;
10202 regs[k].dirty|=1<<HOST_CCREG;
10203 regs[k].wasconst&=~(1<<HOST_CCREG);
10204 regs[k].isconst&=~(1<<HOST_CCREG);
10205 k++;
10206 }
10207 }
10208 else {
10209 //printf("Fail Extend CC, %x ->\n",start+k*4);
10210 }
10211 }
10212 }
10213 if(itype[i]!=STORE&&itype[i]!=STORELR&&itype[i]!=C1LS&&itype[i]!=SHIFT&&
10214 itype[i]!=NOP&&itype[i]!=MOV&&itype[i]!=ALU&&itype[i]!=SHIFTIMM&&
10215 itype[i]!=IMM16&&itype[i]!=LOAD&&itype[i]!=COP1&&itype[i]!=FLOAT&&
e1190b87 10216 itype[i]!=FCONV&&itype[i]!=FCOMP)
57871462 10217 {
10218 memcpy(f_regmap,regs[i].regmap,sizeof(f_regmap));
10219 }
10220 }
10221 }
10222
10223 // This allocates registers (if possible) one instruction prior
10224 // to use, which can avoid a load-use penalty on certain CPUs.
10225 for(i=0;i<slen-1;i++)
10226 {
10227 if(!i||(itype[i-1]!=UJUMP&&itype[i-1]!=CJUMP&&itype[i-1]!=SJUMP&&itype[i-1]!=RJUMP&&itype[i-1]!=FJUMP))
10228 {
10229 if(!bt[i+1])
10230 {
b9b61529 10231 if(itype[i]==ALU||itype[i]==MOV||itype[i]==LOAD||itype[i]==SHIFTIMM||itype[i]==IMM16
10232 ||((itype[i]==COP1||itype[i]==COP2)&&opcode2[i]<3))
57871462 10233 {
10234 if(rs1[i+1]) {
10235 if((hr=get_reg(regs[i+1].regmap,rs1[i+1]))>=0)
10236 {
10237 if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
10238 {
10239 regs[i].regmap[hr]=regs[i+1].regmap[hr];
10240 regmap_pre[i+1][hr]=regs[i+1].regmap[hr];
10241 regs[i+1].regmap_entry[hr]=regs[i+1].regmap[hr];
10242 regs[i].isconst&=~(1<<hr);
10243 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10244 constmap[i][hr]=constmap[i+1][hr];
10245 regs[i+1].wasdirty&=~(1<<hr);
10246 regs[i].dirty&=~(1<<hr);
10247 }
10248 }
10249 }
10250 if(rs2[i+1]) {
10251 if((hr=get_reg(regs[i+1].regmap,rs2[i+1]))>=0)
10252 {
10253 if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
10254 {
10255 regs[i].regmap[hr]=regs[i+1].regmap[hr];
10256 regmap_pre[i+1][hr]=regs[i+1].regmap[hr];
10257 regs[i+1].regmap_entry[hr]=regs[i+1].regmap[hr];
10258 regs[i].isconst&=~(1<<hr);
10259 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10260 constmap[i][hr]=constmap[i+1][hr];
10261 regs[i+1].wasdirty&=~(1<<hr);
10262 regs[i].dirty&=~(1<<hr);
10263 }
10264 }
10265 }
10266 if(itype[i+1]==LOAD&&rs1[i+1]&&get_reg(regs[i+1].regmap,rs1[i+1])<0) {
10267 if((hr=get_reg(regs[i+1].regmap,rt1[i+1]))>=0)
10268 {
10269 if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
10270 {
10271 regs[i].regmap[hr]=rs1[i+1];
10272 regmap_pre[i+1][hr]=rs1[i+1];
10273 regs[i+1].regmap_entry[hr]=rs1[i+1];
10274 regs[i].isconst&=~(1<<hr);
10275 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10276 constmap[i][hr]=constmap[i+1][hr];
10277 regs[i+1].wasdirty&=~(1<<hr);
10278 regs[i].dirty&=~(1<<hr);
10279 }
10280 }
10281 }
10282 if(lt1[i+1]&&get_reg(regs[i+1].regmap,rs1[i+1])<0) {
10283 if((hr=get_reg(regs[i+1].regmap,rt1[i+1]))>=0)
10284 {
10285 if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
10286 {
10287 regs[i].regmap[hr]=rs1[i+1];
10288 regmap_pre[i+1][hr]=rs1[i+1];
10289 regs[i+1].regmap_entry[hr]=rs1[i+1];
10290 regs[i].isconst&=~(1<<hr);
10291 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10292 constmap[i][hr]=constmap[i+1][hr];
10293 regs[i+1].wasdirty&=~(1<<hr);
10294 regs[i].dirty&=~(1<<hr);
10295 }
10296 }
10297 }
10298 #ifndef HOST_IMM_ADDR32
b9b61529 10299 if(itype[i+1]==LOAD||itype[i+1]==LOADLR||itype[i+1]==STORE||itype[i+1]==STORELR||itype[i+1]==C1LS||itype[i+1]==C2LS) {
57871462 10300 hr=get_reg(regs[i+1].regmap,TLREG);
10301 if(hr>=0) {
10302 int sr=get_reg(regs[i+1].regmap,rs1[i+1]);
10303 if(sr>=0&&((regs[i+1].wasconst>>sr)&1)) {
10304 int nr;
10305 if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
10306 {
10307 regs[i].regmap[hr]=MGEN1+((i+1)&1);
10308 regmap_pre[i+1][hr]=MGEN1+((i+1)&1);
10309 regs[i+1].regmap_entry[hr]=MGEN1+((i+1)&1);
10310 regs[i].isconst&=~(1<<hr);
10311 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10312 constmap[i][hr]=constmap[i+1][hr];
10313 regs[i+1].wasdirty&=~(1<<hr);
10314 regs[i].dirty&=~(1<<hr);
10315 }
10316 else if((nr=get_reg2(regs[i].regmap,regs[i+1].regmap,-1))>=0)
10317 {
10318 // move it to another register
10319 regs[i+1].regmap[hr]=-1;
10320 regmap_pre[i+2][hr]=-1;
10321 regs[i+1].regmap[nr]=TLREG;
10322 regmap_pre[i+2][nr]=TLREG;
10323 regs[i].regmap[nr]=MGEN1+((i+1)&1);
10324 regmap_pre[i+1][nr]=MGEN1+((i+1)&1);
10325 regs[i+1].regmap_entry[nr]=MGEN1+((i+1)&1);
10326 regs[i].isconst&=~(1<<nr);
10327 regs[i+1].isconst&=~(1<<nr);
10328 regs[i].dirty&=~(1<<nr);
10329 regs[i+1].wasdirty&=~(1<<nr);
10330 regs[i+1].dirty&=~(1<<nr);
10331 regs[i+2].wasdirty&=~(1<<nr);
10332 }
10333 }
10334 }
10335 }
10336 #endif
b9b61529 10337 if(itype[i+1]==STORE||itype[i+1]==STORELR
10338 ||(opcode[i+1]&0x3b)==0x39||(opcode[i+1]&0x3b)==0x3a) { // SB/SH/SW/SD/SWC1/SDC1/SWC2/SDC2
57871462 10339 if(get_reg(regs[i+1].regmap,rs1[i+1])<0) {
10340 hr=get_reg2(regs[i].regmap,regs[i+1].regmap,-1);
10341 if(hr<0) hr=get_reg(regs[i+1].regmap,-1);
10342 else {regs[i+1].regmap[hr]=AGEN1+((i+1)&1);regs[i+1].isconst&=~(1<<hr);}
10343 assert(hr>=0);
10344 if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
10345 {
10346 regs[i].regmap[hr]=rs1[i+1];
10347 regmap_pre[i+1][hr]=rs1[i+1];
10348 regs[i+1].regmap_entry[hr]=rs1[i+1];
10349 regs[i].isconst&=~(1<<hr);
10350 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10351 constmap[i][hr]=constmap[i+1][hr];
10352 regs[i+1].wasdirty&=~(1<<hr);
10353 regs[i].dirty&=~(1<<hr);
10354 }
10355 }
10356 }
b9b61529 10357 if(itype[i+1]==LOADLR||(opcode[i+1]&0x3b)==0x31||(opcode[i+1]&0x3b)==0x32) { // LWC1/LDC1, LWC2/LDC2
57871462 10358 if(get_reg(regs[i+1].regmap,rs1[i+1])<0) {
10359 int nr;
10360 hr=get_reg(regs[i+1].regmap,FTEMP);
10361 assert(hr>=0);
10362 if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
10363 {
10364 regs[i].regmap[hr]=rs1[i+1];
10365 regmap_pre[i+1][hr]=rs1[i+1];
10366 regs[i+1].regmap_entry[hr]=rs1[i+1];
10367 regs[i].isconst&=~(1<<hr);
10368 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10369 constmap[i][hr]=constmap[i+1][hr];
10370 regs[i+1].wasdirty&=~(1<<hr);
10371 regs[i].dirty&=~(1<<hr);
10372 }
10373 else if((nr=get_reg2(regs[i].regmap,regs[i+1].regmap,-1))>=0)
10374 {
10375 // move it to another register
10376 regs[i+1].regmap[hr]=-1;
10377 regmap_pre[i+2][hr]=-1;
10378 regs[i+1].regmap[nr]=FTEMP;
10379 regmap_pre[i+2][nr]=FTEMP;
10380 regs[i].regmap[nr]=rs1[i+1];
10381 regmap_pre[i+1][nr]=rs1[i+1];
10382 regs[i+1].regmap_entry[nr]=rs1[i+1];
10383 regs[i].isconst&=~(1<<nr);
10384 regs[i+1].isconst&=~(1<<nr);
10385 regs[i].dirty&=~(1<<nr);
10386 regs[i+1].wasdirty&=~(1<<nr);
10387 regs[i+1].dirty&=~(1<<nr);
10388 regs[i+2].wasdirty&=~(1<<nr);
10389 }
10390 }
10391 }
b9b61529 10392 if(itype[i+1]==LOAD||itype[i+1]==LOADLR||itype[i+1]==STORE||itype[i+1]==STORELR/*||itype[i+1]==C1LS||||itype[i+1]==C2LS*/) {
57871462 10393 if(itype[i+1]==LOAD)
10394 hr=get_reg(regs[i+1].regmap,rt1[i+1]);
b9b61529 10395 if(itype[i+1]==LOADLR||(opcode[i+1]&0x3b)==0x31||(opcode[i+1]&0x3b)==0x32) // LWC1/LDC1, LWC2/LDC2
57871462 10396 hr=get_reg(regs[i+1].regmap,FTEMP);
b9b61529 10397 if(itype[i+1]==STORE||itype[i+1]==STORELR||(opcode[i+1]&0x3b)==0x39||(opcode[i+1]&0x3b)==0x3a) { // SWC1/SDC1/SWC2/SDC2
57871462 10398 hr=get_reg(regs[i+1].regmap,AGEN1+((i+1)&1));
10399 if(hr<0) hr=get_reg(regs[i+1].regmap,-1);
10400 }
10401 if(hr>=0&&regs[i].regmap[hr]<0) {
10402 int rs=get_reg(regs[i+1].regmap,rs1[i+1]);
10403 if(rs>=0&&((regs[i+1].wasconst>>rs)&1)) {
10404 regs[i].regmap[hr]=AGEN1+((i+1)&1);
10405 regmap_pre[i+1][hr]=AGEN1+((i+1)&1);
10406 regs[i+1].regmap_entry[hr]=AGEN1+((i+1)&1);
10407 regs[i].isconst&=~(1<<hr);
10408 regs[i+1].wasdirty&=~(1<<hr);
10409 regs[i].dirty&=~(1<<hr);
10410 }
10411 }
10412 }
10413 }
10414 }
10415 }
10416 }
10417
10418 /* Pass 6 - Optimize clean/dirty state */
10419 clean_registers(0,slen-1,1);
10420
10421 /* Pass 7 - Identify 32-bit registers */
a28c6ce8 10422#ifndef FORCE32
57871462 10423 provisional_r32();
10424
10425 u_int r32=0;
10426
10427 for (i=slen-1;i>=0;i--)
10428 {
10429 int hr;
10430 if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
10431 {
10432 if(ba[i]<start || ba[i]>=(start+slen*4))
10433 {
10434 // Branch out of this block, don't need anything
10435 r32=0;
10436 }
10437 else
10438 {
10439 // Internal branch
10440 // Need whatever matches the target
10441 // (and doesn't get overwritten by the delay slot instruction)
10442 r32=0;
10443 int t=(ba[i]-start)>>2;
10444 if(ba[i]>start+i*4) {
10445 // Forward branch
10446 if(!(requires_32bit[t]&~regs[i].was32))
10447 r32|=requires_32bit[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
10448 }else{
10449 // Backward branch
10450 //if(!(regs[t].was32&~unneeded_reg_upper[t]&~regs[i].was32))
10451 // r32|=regs[t].was32&~unneeded_reg_upper[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
10452 if(!(pr32[t]&~regs[i].was32))
10453 r32|=pr32[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
10454 }
10455 }
10456 // Conditional branch may need registers for following instructions
10457 if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000)
10458 {
10459 if(i<slen-2) {
10460 r32|=requires_32bit[i+2];
10461 r32&=regs[i].was32;
10462 // Mark this address as a branch target since it may be called
10463 // upon return from interrupt
10464 bt[i+2]=1;
10465 }
10466 }
10467 // Merge in delay slot
10468 if(!likely[i]) {
10469 // These are overwritten unless the branch is "likely"
10470 // and the delay slot is nullified if not taken
10471 r32&=~(1LL<<rt1[i+1]);
10472 r32&=~(1LL<<rt2[i+1]);
10473 }
10474 // Assume these are needed (delay slot)
10475 if(us1[i+1]>0)
10476 {
10477 if((regs[i].was32>>us1[i+1])&1) r32|=1LL<<us1[i+1];
10478 }
10479 if(us2[i+1]>0)
10480 {
10481 if((regs[i].was32>>us2[i+1])&1) r32|=1LL<<us2[i+1];
10482 }
10483 if(dep1[i+1]&&!((unneeded_reg_upper[i]>>dep1[i+1])&1))
10484 {
10485 if((regs[i].was32>>dep1[i+1])&1) r32|=1LL<<dep1[i+1];
10486 }
10487 if(dep2[i+1]&&!((unneeded_reg_upper[i]>>dep2[i+1])&1))
10488 {
10489 if((regs[i].was32>>dep2[i+1])&1) r32|=1LL<<dep2[i+1];
10490 }
10491 }
1e973cb0 10492 else if(itype[i]==SYSCALL||itype[i]==HLECALL||itype[i]==INTCALL)
57871462 10493 {
10494 // SYSCALL instruction (software interrupt)
10495 r32=0;
10496 }
10497 else if(itype[i]==COP0 && (source[i]&0x3f)==0x18)
10498 {
10499 // ERET instruction (return from interrupt)
10500 r32=0;
10501 }
10502 // Check 32 bits
10503 r32&=~(1LL<<rt1[i]);
10504 r32&=~(1LL<<rt2[i]);
10505 if(us1[i]>0)
10506 {
10507 if((regs[i].was32>>us1[i])&1) r32|=1LL<<us1[i];
10508 }
10509 if(us2[i]>0)
10510 {
10511 if((regs[i].was32>>us2[i])&1) r32|=1LL<<us2[i];
10512 }
10513 if(dep1[i]&&!((unneeded_reg_upper[i]>>dep1[i])&1))
10514 {
10515 if((regs[i].was32>>dep1[i])&1) r32|=1LL<<dep1[i];
10516 }
10517 if(dep2[i]&&!((unneeded_reg_upper[i]>>dep2[i])&1))
10518 {
10519 if((regs[i].was32>>dep2[i])&1) r32|=1LL<<dep2[i];
10520 }
10521 requires_32bit[i]=r32;
10522
10523 // Dirty registers which are 32-bit, require 32-bit input
10524 // as they will be written as 32-bit values
10525 for(hr=0;hr<HOST_REGS;hr++)
10526 {
10527 if(regs[i].regmap_entry[hr]>0&&regs[i].regmap_entry[hr]<64) {
10528 if((regs[i].was32>>regs[i].regmap_entry[hr])&(regs[i].wasdirty>>hr)&1) {
10529 if(!((unneeded_reg_upper[i]>>regs[i].regmap_entry[hr])&1))
10530 requires_32bit[i]|=1LL<<regs[i].regmap_entry[hr];
10531 }
10532 }
10533 }
10534 //requires_32bit[i]=is32[i]&~unneeded_reg_upper[i]; // DEBUG
10535 }
04fd948a 10536#else
10537 for (i=slen-1;i>=0;i--)
10538 {
10539 if(itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
10540 {
10541 // Conditional branch
10542 if((source[i]>>16)!=0x1000&&i<slen-2) {
10543 // Mark this address as a branch target since it may be called
10544 // upon return from interrupt
10545 bt[i+2]=1;
10546 }
10547 }
10548 }
a28c6ce8 10549#endif
57871462 10550
10551 if(itype[slen-1]==SPAN) {
10552 bt[slen-1]=1; // Mark as a branch target so instruction can restart after exception
10553 }
10554
10555 /* Debug/disassembly */
10556 if((void*)assem_debug==(void*)printf)
10557 for(i=0;i<slen;i++)
10558 {
10559 printf("U:");
10560 int r;
10561 for(r=1;r<=CCREG;r++) {
10562 if((unneeded_reg[i]>>r)&1) {
10563 if(r==HIREG) printf(" HI");
10564 else if(r==LOREG) printf(" LO");
10565 else printf(" r%d",r);
10566 }
10567 }
90ae6d4e 10568#ifndef FORCE32
57871462 10569 printf(" UU:");
10570 for(r=1;r<=CCREG;r++) {
10571 if(((unneeded_reg_upper[i]&~unneeded_reg[i])>>r)&1) {
10572 if(r==HIREG) printf(" HI");
10573 else if(r==LOREG) printf(" LO");
10574 else printf(" r%d",r);
10575 }
10576 }
10577 printf(" 32:");
10578 for(r=0;r<=CCREG;r++) {
10579 //if(((is32[i]>>r)&(~unneeded_reg[i]>>r))&1) {
10580 if((regs[i].was32>>r)&1) {
10581 if(r==CCREG) printf(" CC");
10582 else if(r==HIREG) printf(" HI");
10583 else if(r==LOREG) printf(" LO");
10584 else printf(" r%d",r);
10585 }
10586 }
90ae6d4e 10587#endif
57871462 10588 printf("\n");
10589 #if defined(__i386__) || defined(__x86_64__)
10590 printf("pre: eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",regmap_pre[i][0],regmap_pre[i][1],regmap_pre[i][2],regmap_pre[i][3],regmap_pre[i][5],regmap_pre[i][6],regmap_pre[i][7]);
10591 #endif
10592 #ifdef __arm__
10593 printf("pre: r0=%d r1=%d r2=%d r3=%d r4=%d r5=%d r6=%d r7=%d r8=%d r9=%d r10=%d r12=%d\n",regmap_pre[i][0],regmap_pre[i][1],regmap_pre[i][2],regmap_pre[i][3],regmap_pre[i][4],regmap_pre[i][5],regmap_pre[i][6],regmap_pre[i][7],regmap_pre[i][8],regmap_pre[i][9],regmap_pre[i][10],regmap_pre[i][12]);
10594 #endif
10595 printf("needs: ");
10596 if(needed_reg[i]&1) printf("eax ");
10597 if((needed_reg[i]>>1)&1) printf("ecx ");
10598 if((needed_reg[i]>>2)&1) printf("edx ");
10599 if((needed_reg[i]>>3)&1) printf("ebx ");
10600 if((needed_reg[i]>>5)&1) printf("ebp ");
10601 if((needed_reg[i]>>6)&1) printf("esi ");
10602 if((needed_reg[i]>>7)&1) printf("edi ");
10603 printf("r:");
10604 for(r=0;r<=CCREG;r++) {
10605 //if(((requires_32bit[i]>>r)&(~unneeded_reg[i]>>r))&1) {
10606 if((requires_32bit[i]>>r)&1) {
10607 if(r==CCREG) printf(" CC");
10608 else if(r==HIREG) printf(" HI");
10609 else if(r==LOREG) printf(" LO");
10610 else printf(" r%d",r);
10611 }
10612 }
10613 printf("\n");
10614 /*printf("pr:");
10615 for(r=0;r<=CCREG;r++) {
10616 //if(((requires_32bit[i]>>r)&(~unneeded_reg[i]>>r))&1) {
10617 if((pr32[i]>>r)&1) {
10618 if(r==CCREG) printf(" CC");
10619 else if(r==HIREG) printf(" HI");
10620 else if(r==LOREG) printf(" LO");
10621 else printf(" r%d",r);
10622 }
10623 }
10624 if(pr32[i]!=requires_32bit[i]) printf(" OOPS");
10625 printf("\n");*/
10626 #if defined(__i386__) || defined(__x86_64__)
10627 printf("entry: eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",regs[i].regmap_entry[0],regs[i].regmap_entry[1],regs[i].regmap_entry[2],regs[i].regmap_entry[3],regs[i].regmap_entry[5],regs[i].regmap_entry[6],regs[i].regmap_entry[7]);
10628 printf("dirty: ");
10629 if(regs[i].wasdirty&1) printf("eax ");
10630 if((regs[i].wasdirty>>1)&1) printf("ecx ");
10631 if((regs[i].wasdirty>>2)&1) printf("edx ");
10632 if((regs[i].wasdirty>>3)&1) printf("ebx ");
10633 if((regs[i].wasdirty>>5)&1) printf("ebp ");
10634 if((regs[i].wasdirty>>6)&1) printf("esi ");
10635 if((regs[i].wasdirty>>7)&1) printf("edi ");
10636 #endif
10637 #ifdef __arm__
10638 printf("entry: r0=%d r1=%d r2=%d r3=%d r4=%d r5=%d r6=%d r7=%d r8=%d r9=%d r10=%d r12=%d\n",regs[i].regmap_entry[0],regs[i].regmap_entry[1],regs[i].regmap_entry[2],regs[i].regmap_entry[3],regs[i].regmap_entry[4],regs[i].regmap_entry[5],regs[i].regmap_entry[6],regs[i].regmap_entry[7],regs[i].regmap_entry[8],regs[i].regmap_entry[9],regs[i].regmap_entry[10],regs[i].regmap_entry[12]);
10639 printf("dirty: ");
10640 if(regs[i].wasdirty&1) printf("r0 ");
10641 if((regs[i].wasdirty>>1)&1) printf("r1 ");
10642 if((regs[i].wasdirty>>2)&1) printf("r2 ");
10643 if((regs[i].wasdirty>>3)&1) printf("r3 ");
10644 if((regs[i].wasdirty>>4)&1) printf("r4 ");
10645 if((regs[i].wasdirty>>5)&1) printf("r5 ");
10646 if((regs[i].wasdirty>>6)&1) printf("r6 ");
10647 if((regs[i].wasdirty>>7)&1) printf("r7 ");
10648 if((regs[i].wasdirty>>8)&1) printf("r8 ");
10649 if((regs[i].wasdirty>>9)&1) printf("r9 ");
10650 if((regs[i].wasdirty>>10)&1) printf("r10 ");
10651 if((regs[i].wasdirty>>12)&1) printf("r12 ");
10652 #endif
10653 printf("\n");
10654 disassemble_inst(i);
10655 //printf ("ccadj[%d] = %d\n",i,ccadj[i]);
10656 #if defined(__i386__) || defined(__x86_64__)
10657 printf("eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d dirty: ",regs[i].regmap[0],regs[i].regmap[1],regs[i].regmap[2],regs[i].regmap[3],regs[i].regmap[5],regs[i].regmap[6],regs[i].regmap[7]);
10658 if(regs[i].dirty&1) printf("eax ");
10659 if((regs[i].dirty>>1)&1) printf("ecx ");
10660 if((regs[i].dirty>>2)&1) printf("edx ");
10661 if((regs[i].dirty>>3)&1) printf("ebx ");
10662 if((regs[i].dirty>>5)&1) printf("ebp ");
10663 if((regs[i].dirty>>6)&1) printf("esi ");
10664 if((regs[i].dirty>>7)&1) printf("edi ");
10665 #endif
10666 #ifdef __arm__
10667 printf("r0=%d r1=%d r2=%d r3=%d r4=%d r5=%d r6=%d r7=%d r8=%d r9=%d r10=%d r12=%d dirty: ",regs[i].regmap[0],regs[i].regmap[1],regs[i].regmap[2],regs[i].regmap[3],regs[i].regmap[4],regs[i].regmap[5],regs[i].regmap[6],regs[i].regmap[7],regs[i].regmap[8],regs[i].regmap[9],regs[i].regmap[10],regs[i].regmap[12]);
10668 if(regs[i].dirty&1) printf("r0 ");
10669 if((regs[i].dirty>>1)&1) printf("r1 ");
10670 if((regs[i].dirty>>2)&1) printf("r2 ");
10671 if((regs[i].dirty>>3)&1) printf("r3 ");
10672 if((regs[i].dirty>>4)&1) printf("r4 ");
10673 if((regs[i].dirty>>5)&1) printf("r5 ");
10674 if((regs[i].dirty>>6)&1) printf("r6 ");
10675 if((regs[i].dirty>>7)&1) printf("r7 ");
10676 if((regs[i].dirty>>8)&1) printf("r8 ");
10677 if((regs[i].dirty>>9)&1) printf("r9 ");
10678 if((regs[i].dirty>>10)&1) printf("r10 ");
10679 if((regs[i].dirty>>12)&1) printf("r12 ");
10680 #endif
10681 printf("\n");
10682 if(regs[i].isconst) {
10683 printf("constants: ");
10684 #if defined(__i386__) || defined(__x86_64__)
10685 if(regs[i].isconst&1) printf("eax=%x ",(int)constmap[i][0]);
10686 if((regs[i].isconst>>1)&1) printf("ecx=%x ",(int)constmap[i][1]);
10687 if((regs[i].isconst>>2)&1) printf("edx=%x ",(int)constmap[i][2]);
10688 if((regs[i].isconst>>3)&1) printf("ebx=%x ",(int)constmap[i][3]);
10689 if((regs[i].isconst>>5)&1) printf("ebp=%x ",(int)constmap[i][5]);
10690 if((regs[i].isconst>>6)&1) printf("esi=%x ",(int)constmap[i][6]);
10691 if((regs[i].isconst>>7)&1) printf("edi=%x ",(int)constmap[i][7]);
10692 #endif
10693 #ifdef __arm__
10694 if(regs[i].isconst&1) printf("r0=%x ",(int)constmap[i][0]);
10695 if((regs[i].isconst>>1)&1) printf("r1=%x ",(int)constmap[i][1]);
10696 if((regs[i].isconst>>2)&1) printf("r2=%x ",(int)constmap[i][2]);
10697 if((regs[i].isconst>>3)&1) printf("r3=%x ",(int)constmap[i][3]);
10698 if((regs[i].isconst>>4)&1) printf("r4=%x ",(int)constmap[i][4]);
10699 if((regs[i].isconst>>5)&1) printf("r5=%x ",(int)constmap[i][5]);
10700 if((regs[i].isconst>>6)&1) printf("r6=%x ",(int)constmap[i][6]);
10701 if((regs[i].isconst>>7)&1) printf("r7=%x ",(int)constmap[i][7]);
10702 if((regs[i].isconst>>8)&1) printf("r8=%x ",(int)constmap[i][8]);
10703 if((regs[i].isconst>>9)&1) printf("r9=%x ",(int)constmap[i][9]);
10704 if((regs[i].isconst>>10)&1) printf("r10=%x ",(int)constmap[i][10]);
10705 if((regs[i].isconst>>12)&1) printf("r12=%x ",(int)constmap[i][12]);
10706 #endif
10707 printf("\n");
10708 }
90ae6d4e 10709#ifndef FORCE32
57871462 10710 printf(" 32:");
10711 for(r=0;r<=CCREG;r++) {
10712 if((regs[i].is32>>r)&1) {
10713 if(r==CCREG) printf(" CC");
10714 else if(r==HIREG) printf(" HI");
10715 else if(r==LOREG) printf(" LO");
10716 else printf(" r%d",r);
10717 }
10718 }
10719 printf("\n");
90ae6d4e 10720#endif
57871462 10721 /*printf(" p32:");
10722 for(r=0;r<=CCREG;r++) {
10723 if((p32[i]>>r)&1) {
10724 if(r==CCREG) printf(" CC");
10725 else if(r==HIREG) printf(" HI");
10726 else if(r==LOREG) printf(" LO");
10727 else printf(" r%d",r);
10728 }
10729 }
10730 if(p32[i]!=regs[i].is32) printf(" NO MATCH\n");
10731 else printf("\n");*/
10732 if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP) {
10733 #if defined(__i386__) || defined(__x86_64__)
10734 printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d dirty: ",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
10735 if(branch_regs[i].dirty&1) printf("eax ");
10736 if((branch_regs[i].dirty>>1)&1) printf("ecx ");
10737 if((branch_regs[i].dirty>>2)&1) printf("edx ");
10738 if((branch_regs[i].dirty>>3)&1) printf("ebx ");
10739 if((branch_regs[i].dirty>>5)&1) printf("ebp ");
10740 if((branch_regs[i].dirty>>6)&1) printf("esi ");
10741 if((branch_regs[i].dirty>>7)&1) printf("edi ");
10742 #endif
10743 #ifdef __arm__
10744 printf("branch(%d): r0=%d r1=%d r2=%d r3=%d r4=%d r5=%d r6=%d r7=%d r8=%d r9=%d r10=%d r12=%d dirty: ",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[4],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7],branch_regs[i].regmap[8],branch_regs[i].regmap[9],branch_regs[i].regmap[10],branch_regs[i].regmap[12]);
10745 if(branch_regs[i].dirty&1) printf("r0 ");
10746 if((branch_regs[i].dirty>>1)&1) printf("r1 ");
10747 if((branch_regs[i].dirty>>2)&1) printf("r2 ");
10748 if((branch_regs[i].dirty>>3)&1) printf("r3 ");
10749 if((branch_regs[i].dirty>>4)&1) printf("r4 ");
10750 if((branch_regs[i].dirty>>5)&1) printf("r5 ");
10751 if((branch_regs[i].dirty>>6)&1) printf("r6 ");
10752 if((branch_regs[i].dirty>>7)&1) printf("r7 ");
10753 if((branch_regs[i].dirty>>8)&1) printf("r8 ");
10754 if((branch_regs[i].dirty>>9)&1) printf("r9 ");
10755 if((branch_regs[i].dirty>>10)&1) printf("r10 ");
10756 if((branch_regs[i].dirty>>12)&1) printf("r12 ");
10757 #endif
90ae6d4e 10758#ifndef FORCE32
57871462 10759 printf(" 32:");
10760 for(r=0;r<=CCREG;r++) {
10761 if((branch_regs[i].is32>>r)&1) {
10762 if(r==CCREG) printf(" CC");
10763 else if(r==HIREG) printf(" HI");
10764 else if(r==LOREG) printf(" LO");
10765 else printf(" r%d",r);
10766 }
10767 }
10768 printf("\n");
90ae6d4e 10769#endif
57871462 10770 }
10771 }
10772
10773 /* Pass 8 - Assembly */
10774 linkcount=0;stubcount=0;
10775 ds=0;is_delayslot=0;
10776 cop1_usable=0;
10777 uint64_t is32_pre=0;
10778 u_int dirty_pre=0;
10779 u_int beginning=(u_int)out;
10780 if((u_int)addr&1) {
10781 ds=1;
10782 pagespan_ds();
10783 }
9ad4d757 10784 u_int instr_addr0_override=0;
10785
10786#ifdef PCSX
10787 if (start == 0x80030000) {
10788 // nasty hack for fastbios thing
10789 instr_addr0_override=(u_int)out;
10790 emit_movimm(start,0);
10791 emit_readword((int)&pcaddr,1);
10792 emit_writeword(0,(int)&pcaddr);
10793 emit_cmp(0,1);
10794 emit_jne((int)new_dyna_leave);
10795 }
10796#endif
57871462 10797 for(i=0;i<slen;i++)
10798 {
10799 //if(ds) printf("ds: ");
10800 if((void*)assem_debug==(void*)printf) disassemble_inst(i);
10801 if(ds) {
10802 ds=0; // Skip delay slot
10803 if(bt[i]) assem_debug("OOPS - branch into delay slot\n");
10804 instr_addr[i]=0;
10805 } else {
10806 #ifndef DESTRUCTIVE_WRITEBACK
10807 if(i<2||(itype[i-2]!=UJUMP&&itype[i-2]!=RJUMP&&(source[i-2]>>16)!=0x1000))
10808 {
10809 wb_sx(regmap_pre[i],regs[i].regmap_entry,regs[i].wasdirty,is32_pre,regs[i].was32,
10810 unneeded_reg[i],unneeded_reg_upper[i]);
10811 wb_valid(regmap_pre[i],regs[i].regmap_entry,dirty_pre,regs[i].wasdirty,is32_pre,
10812 unneeded_reg[i],unneeded_reg_upper[i]);
10813 }
10814 is32_pre=regs[i].is32;
10815 dirty_pre=regs[i].dirty;
10816 #endif
10817 // write back
10818 if(i<2||(itype[i-2]!=UJUMP&&itype[i-2]!=RJUMP&&(source[i-2]>>16)!=0x1000))
10819 {
10820 wb_invalidate(regmap_pre[i],regs[i].regmap_entry,regs[i].wasdirty,regs[i].was32,
10821 unneeded_reg[i],unneeded_reg_upper[i]);
10822 loop_preload(regmap_pre[i],regs[i].regmap_entry);
10823 }
10824 // branch target entry point
10825 instr_addr[i]=(u_int)out;
10826 assem_debug("<->\n");
10827 // load regs
10828 if(regs[i].regmap_entry[HOST_CCREG]==CCREG&&regs[i].regmap[HOST_CCREG]!=CCREG)
10829 wb_register(CCREG,regs[i].regmap_entry,regs[i].wasdirty,regs[i].was32);
10830 load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,rs1[i],rs2[i]);
10831 address_generation(i,&regs[i],regs[i].regmap_entry);
10832 load_consts(regmap_pre[i],regs[i].regmap,regs[i].was32,i);
10833 if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
10834 {
10835 // Load the delay slot registers if necessary
4ef8f67d 10836 if(rs1[i+1]!=rs1[i]&&rs1[i+1]!=rs2[i]&&(rs1[i+1]!=rt1[i]||rt1[i]==0))
57871462 10837 load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,rs1[i+1],rs1[i+1]);
4ef8f67d 10838 if(rs2[i+1]!=rs1[i+1]&&rs2[i+1]!=rs1[i]&&rs2[i+1]!=rs2[i]&&(rs2[i+1]!=rt1[i]||rt1[i]==0))
57871462 10839 load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,rs2[i+1],rs2[i+1]);
b9b61529 10840 if(itype[i+1]==STORE||itype[i+1]==STORELR||(opcode[i+1]&0x3b)==0x39||(opcode[i+1]&0x3b)==0x3a)
57871462 10841 load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,INVCP,INVCP);
10842 }
10843 else if(i+1<slen)
10844 {
10845 // Preload registers for following instruction
10846 if(rs1[i+1]!=rs1[i]&&rs1[i+1]!=rs2[i])
10847 if(rs1[i+1]!=rt1[i]&&rs1[i+1]!=rt2[i])
10848 load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,rs1[i+1],rs1[i+1]);
10849 if(rs2[i+1]!=rs1[i+1]&&rs2[i+1]!=rs1[i]&&rs2[i+1]!=rs2[i])
10850 if(rs2[i+1]!=rt1[i]&&rs2[i+1]!=rt2[i])
10851 load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,rs2[i+1],rs2[i+1]);
10852 }
10853 // TODO: if(is_ooo(i)) address_generation(i+1);
10854 if(itype[i]==CJUMP||itype[i]==FJUMP)
10855 load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,CCREG,CCREG);
b9b61529 10856 if(itype[i]==STORE||itype[i]==STORELR||(opcode[i]&0x3b)==0x39||(opcode[i]&0x3b)==0x3a)
57871462 10857 load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,INVCP,INVCP);
10858 if(bt[i]) cop1_usable=0;
10859 // assemble
10860 switch(itype[i]) {
10861 case ALU:
10862 alu_assemble(i,&regs[i]);break;
10863 case IMM16:
10864 imm16_assemble(i,&regs[i]);break;
10865 case SHIFT:
10866 shift_assemble(i,&regs[i]);break;
10867 case SHIFTIMM:
10868 shiftimm_assemble(i,&regs[i]);break;
10869 case LOAD:
10870 load_assemble(i,&regs[i]);break;
10871 case LOADLR:
10872 loadlr_assemble(i,&regs[i]);break;
10873 case STORE:
10874 store_assemble(i,&regs[i]);break;
10875 case STORELR:
10876 storelr_assemble(i,&regs[i]);break;
10877 case COP0:
10878 cop0_assemble(i,&regs[i]);break;
10879 case COP1:
10880 cop1_assemble(i,&regs[i]);break;
10881 case C1LS:
10882 c1ls_assemble(i,&regs[i]);break;
b9b61529 10883 case COP2:
10884 cop2_assemble(i,&regs[i]);break;
10885 case C2LS:
10886 c2ls_assemble(i,&regs[i]);break;
10887 case C2OP:
10888 c2op_assemble(i,&regs[i]);break;
57871462 10889 case FCONV:
10890 fconv_assemble(i,&regs[i]);break;
10891 case FLOAT:
10892 float_assemble(i,&regs[i]);break;
10893 case FCOMP:
10894 fcomp_assemble(i,&regs[i]);break;
10895 case MULTDIV:
10896 multdiv_assemble(i,&regs[i]);break;
10897 case MOV:
10898 mov_assemble(i,&regs[i]);break;
10899 case SYSCALL:
10900 syscall_assemble(i,&regs[i]);break;
7139f3c8 10901 case HLECALL:
10902 hlecall_assemble(i,&regs[i]);break;
1e973cb0 10903 case INTCALL:
10904 intcall_assemble(i,&regs[i]);break;
57871462 10905 case UJUMP:
10906 ujump_assemble(i,&regs[i]);ds=1;break;
10907 case RJUMP:
10908 rjump_assemble(i,&regs[i]);ds=1;break;
10909 case CJUMP:
10910 cjump_assemble(i,&regs[i]);ds=1;break;
10911 case SJUMP:
10912 sjump_assemble(i,&regs[i]);ds=1;break;
10913 case FJUMP:
10914 fjump_assemble(i,&regs[i]);ds=1;break;
10915 case SPAN:
10916 pagespan_assemble(i,&regs[i]);break;
10917 }
10918 if(itype[i]==UJUMP||itype[i]==RJUMP||(source[i]>>16)==0x1000)
10919 literal_pool(1024);
10920 else
10921 literal_pool_jumpover(256);
10922 }
10923 }
10924 //assert(itype[i-2]==UJUMP||itype[i-2]==RJUMP||(source[i-2]>>16)==0x1000);
10925 // If the block did not end with an unconditional branch,
10926 // add a jump to the next instruction.
10927 if(i>1) {
10928 if(itype[i-2]!=UJUMP&&itype[i-2]!=RJUMP&&(source[i-2]>>16)!=0x1000&&itype[i-1]!=SPAN) {
10929 assert(itype[i-1]!=UJUMP&&itype[i-1]!=CJUMP&&itype[i-1]!=SJUMP&&itype[i-1]!=RJUMP&&itype[i-1]!=FJUMP);
10930 assert(i==slen);
10931 if(itype[i-2]!=CJUMP&&itype[i-2]!=SJUMP&&itype[i-2]!=FJUMP) {
10932 store_regs_bt(regs[i-1].regmap,regs[i-1].is32,regs[i-1].dirty,start+i*4);
10933 if(regs[i-1].regmap[HOST_CCREG]!=CCREG)
10934 emit_loadreg(CCREG,HOST_CCREG);
10935 emit_addimm(HOST_CCREG,CLOCK_DIVIDER*(ccadj[i-1]+1),HOST_CCREG);
10936 }
10937 else if(!likely[i-2])
10938 {
10939 store_regs_bt(branch_regs[i-2].regmap,branch_regs[i-2].is32,branch_regs[i-2].dirty,start+i*4);
10940 assert(branch_regs[i-2].regmap[HOST_CCREG]==CCREG);
10941 }
10942 else
10943 {
10944 store_regs_bt(regs[i-2].regmap,regs[i-2].is32,regs[i-2].dirty,start+i*4);
10945 assert(regs[i-2].regmap[HOST_CCREG]==CCREG);
10946 }
10947 add_to_linker((int)out,start+i*4,0);
10948 emit_jmp(0);
10949 }
10950 }
10951 else
10952 {
10953 assert(i>0);
10954 assert(itype[i-1]!=UJUMP&&itype[i-1]!=CJUMP&&itype[i-1]!=SJUMP&&itype[i-1]!=RJUMP&&itype[i-1]!=FJUMP);
10955 store_regs_bt(regs[i-1].regmap,regs[i-1].is32,regs[i-1].dirty,start+i*4);
10956 if(regs[i-1].regmap[HOST_CCREG]!=CCREG)
10957 emit_loadreg(CCREG,HOST_CCREG);
10958 emit_addimm(HOST_CCREG,CLOCK_DIVIDER*(ccadj[i-1]+1),HOST_CCREG);
10959 add_to_linker((int)out,start+i*4,0);
10960 emit_jmp(0);
10961 }
10962
10963 // TODO: delay slot stubs?
10964 // Stubs
10965 for(i=0;i<stubcount;i++)
10966 {
10967 switch(stubs[i][0])
10968 {
10969 case LOADB_STUB:
10970 case LOADH_STUB:
10971 case LOADW_STUB:
10972 case LOADD_STUB:
10973 case LOADBU_STUB:
10974 case LOADHU_STUB:
10975 do_readstub(i);break;
10976 case STOREB_STUB:
10977 case STOREH_STUB:
10978 case STOREW_STUB:
10979 case STORED_STUB:
10980 do_writestub(i);break;
10981 case CC_STUB:
10982 do_ccstub(i);break;
10983 case INVCODE_STUB:
10984 do_invstub(i);break;
10985 case FP_STUB:
10986 do_cop1stub(i);break;
10987 case STORELR_STUB:
10988 do_unalignedwritestub(i);break;
10989 }
10990 }
10991
9ad4d757 10992 if (instr_addr0_override)
10993 instr_addr[0] = instr_addr0_override;
10994
57871462 10995 /* Pass 9 - Linker */
10996 for(i=0;i<linkcount;i++)
10997 {
10998 assem_debug("%8x -> %8x\n",link_addr[i][0],link_addr[i][1]);
10999 literal_pool(64);
11000 if(!link_addr[i][2])
11001 {
11002 void *stub=out;
11003 void *addr=check_addr(link_addr[i][1]);
11004 emit_extjump(link_addr[i][0],link_addr[i][1]);
11005 if(addr) {
11006 set_jump_target(link_addr[i][0],(int)addr);
11007 add_link(link_addr[i][1],stub);
11008 }
11009 else set_jump_target(link_addr[i][0],(int)stub);
11010 }
11011 else
11012 {
11013 // Internal branch
11014 int target=(link_addr[i][1]-start)>>2;
11015 assert(target>=0&&target<slen);
11016 assert(instr_addr[target]);
11017 //#ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
11018 //set_jump_target_fillslot(link_addr[i][0],instr_addr[target],link_addr[i][2]>>1);
11019 //#else
11020 set_jump_target(link_addr[i][0],instr_addr[target]);
11021 //#endif
11022 }
11023 }
11024 // External Branch Targets (jump_in)
11025 if(copy+slen*4>(void *)shadow+sizeof(shadow)) copy=shadow;
11026 for(i=0;i<slen;i++)
11027 {
11028 if(bt[i]||i==0)
11029 {
11030 if(instr_addr[i]) // TODO - delay slots (=null)
11031 {
11032 u_int vaddr=start+i*4;
94d23bb9 11033 u_int page=get_page(vaddr);
11034 u_int vpage=get_vpage(vaddr);
57871462 11035 literal_pool(256);
11036 //if(!(is32[i]&(~unneeded_reg_upper[i])&~(1LL<<CCREG)))
a28c6ce8 11037#ifndef FORCE32
57871462 11038 if(!requires_32bit[i])
a28c6ce8 11039#else
11040 if(1)
11041#endif
57871462 11042 {
11043 assem_debug("%8x (%d) <- %8x\n",instr_addr[i],i,start+i*4);
11044 assem_debug("jump_in: %x\n",start+i*4);
11045 ll_add(jump_dirty+vpage,vaddr,(void *)out);
11046 int entry_point=do_dirty_stub(i);
11047 ll_add(jump_in+page,vaddr,(void *)entry_point);
11048 // If there was an existing entry in the hash table,
11049 // replace it with the new address.
11050 // Don't add new entries. We'll insert the
11051 // ones that actually get used in check_addr().
11052 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
11053 if(ht_bin[0]==vaddr) {
11054 ht_bin[1]=entry_point;
11055 }
11056 if(ht_bin[2]==vaddr) {
11057 ht_bin[3]=entry_point;
11058 }
11059 }
11060 else
11061 {
11062 u_int r=requires_32bit[i]|!!(requires_32bit[i]>>32);
11063 assem_debug("%8x (%d) <- %8x\n",instr_addr[i],i,start+i*4);
11064 assem_debug("jump_in: %x (restricted - %x)\n",start+i*4,r);
11065 //int entry_point=(int)out;
11066 ////assem_debug("entry_point: %x\n",entry_point);
11067 //load_regs_entry(i);
11068 //if(entry_point==(int)out)
11069 // entry_point=instr_addr[i];
11070 //else
11071 // emit_jmp(instr_addr[i]);
11072 //ll_add_32(jump_in+page,vaddr,r,(void *)entry_point);
11073 ll_add_32(jump_dirty+vpage,vaddr,r,(void *)out);
11074 int entry_point=do_dirty_stub(i);
11075 ll_add_32(jump_in+page,vaddr,r,(void *)entry_point);
11076 }
11077 }
11078 }
11079 }
11080 // Write out the literal pool if necessary
11081 literal_pool(0);
11082 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
11083 // Align code
11084 if(((u_int)out)&7) emit_addnop(13);
11085 #endif
11086 assert((u_int)out-beginning<MAX_OUTPUT_BLOCK_SIZE);
11087 //printf("shadow buffer: %x-%x\n",(int)copy,(int)copy+slen*4);
11088 memcpy(copy,source,slen*4);
11089 copy+=slen*4;
11090
11091 #ifdef __arm__
11092 __clear_cache((void *)beginning,out);
11093 #endif
11094
11095 // If we're within 256K of the end of the buffer,
11096 // start over from the beginning. (Is 256K enough?)
11097 if((int)out>BASE_ADDR+(1<<TARGET_SIZE_2)-MAX_OUTPUT_BLOCK_SIZE) out=(u_char *)BASE_ADDR;
11098
11099 // Trap writes to any of the pages we compiled
11100 for(i=start>>12;i<=(start+slen*4)>>12;i++) {
11101 invalid_code[i]=0;
90ae6d4e 11102#ifndef DISABLE_TLB
57871462 11103 memory_map[i]|=0x40000000;
11104 if((signed int)start>=(signed int)0xC0000000) {
11105 assert(using_tlb);
11106 j=(((u_int)i<<12)+(memory_map[i]<<2)-(u_int)rdram+(u_int)0x80000000)>>12;
11107 invalid_code[j]=0;
11108 memory_map[j]|=0x40000000;
11109 //printf("write protect physical page: %x (virtual %x)\n",j<<12,start);
11110 }
90ae6d4e 11111#endif
57871462 11112 }
b12c9fb8 11113#ifdef PCSX
11114 // PCSX maps all RAM mirror invalid_code tests to 0x80000000..0x80000000+RAM_SIZE
11115 if(get_page(start)<(RAM_SIZE>>12))
11116 for(i=start>>12;i<=(start+slen*4)>>12;i++)
11117 invalid_code[((u_int)0x80000000>>12)|i]=0;
11118#endif
57871462 11119
11120 /* Pass 10 - Free memory by expiring oldest blocks */
11121
11122 int end=((((int)out-BASE_ADDR)>>(TARGET_SIZE_2-16))+16384)&65535;
11123 while(expirep!=end)
11124 {
11125 int shift=TARGET_SIZE_2-3; // Divide into 8 blocks
11126 int base=BASE_ADDR+((expirep>>13)<<shift); // Base address of this block
11127 inv_debug("EXP: Phase %d\n",expirep);
11128 switch((expirep>>11)&3)
11129 {
11130 case 0:
11131 // Clear jump_in and jump_dirty
11132 ll_remove_matching_addrs(jump_in+(expirep&2047),base,shift);
11133 ll_remove_matching_addrs(jump_dirty+(expirep&2047),base,shift);
11134 ll_remove_matching_addrs(jump_in+2048+(expirep&2047),base,shift);
11135 ll_remove_matching_addrs(jump_dirty+2048+(expirep&2047),base,shift);
11136 break;
11137 case 1:
11138 // Clear pointers
11139 ll_kill_pointers(jump_out[expirep&2047],base,shift);
11140 ll_kill_pointers(jump_out[(expirep&2047)+2048],base,shift);
11141 break;
11142 case 2:
11143 // Clear hash table
11144 for(i=0;i<32;i++) {
11145 int *ht_bin=hash_table[((expirep&2047)<<5)+i];
11146 if((ht_bin[3]>>shift)==(base>>shift) ||
11147 ((ht_bin[3]-MAX_OUTPUT_BLOCK_SIZE)>>shift)==(base>>shift)) {
11148 inv_debug("EXP: Remove hash %x -> %x\n",ht_bin[2],ht_bin[3]);
11149 ht_bin[2]=ht_bin[3]=-1;
11150 }
11151 if((ht_bin[1]>>shift)==(base>>shift) ||
11152 ((ht_bin[1]-MAX_OUTPUT_BLOCK_SIZE)>>shift)==(base>>shift)) {
11153 inv_debug("EXP: Remove hash %x -> %x\n",ht_bin[0],ht_bin[1]);
11154 ht_bin[0]=ht_bin[2];
11155 ht_bin[1]=ht_bin[3];
11156 ht_bin[2]=ht_bin[3]=-1;
11157 }
11158 }
11159 break;
11160 case 3:
11161 // Clear jump_out
dd3a91a1 11162 #ifdef __arm__
11163 if((expirep&2047)==0)
11164 do_clear_cache();
11165 #endif
57871462 11166 ll_remove_matching_addrs(jump_out+(expirep&2047),base,shift);
11167 ll_remove_matching_addrs(jump_out+2048+(expirep&2047),base,shift);
11168 break;
11169 }
11170 expirep=(expirep+1)&65535;
11171 }
11172 return 0;
11173}
b9b61529 11174
11175// vim:shiftwidth=2:expandtab
ARM optimized PCSX fork