drc: implement ra accesses in ujump DS
[pcsx_rearmed.git] / libpcsxcore / new_dynarec / new_dynarec.c
CommitLineData
57871462 1/* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
2 * Mupen64plus - new_dynarec.c *
3 * Copyright (C) 2009-2010 Ari64 *
4 * *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
9 * *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
14 * *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. *
19 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */
20
21#include <stdlib.h>
22#include <stdint.h> //include for uint64_t
23#include <assert.h>
24
3d624f89 25#include "emu_if.h" //emulator interface
57871462 26
27#include <sys/mman.h>
28
29#ifdef __i386__
30#include "assem_x86.h"
31#endif
32#ifdef __x86_64__
33#include "assem_x64.h"
34#endif
35#ifdef __arm__
36#include "assem_arm.h"
37#endif
38
39#define MAXBLOCK 4096
40#define MAX_OUTPUT_BLOCK_SIZE 262144
41#define CLOCK_DIVIDER 2
42
43struct regstat
44{
45 signed char regmap_entry[HOST_REGS];
46 signed char regmap[HOST_REGS];
47 uint64_t was32;
48 uint64_t is32;
49 uint64_t wasdirty;
50 uint64_t dirty;
51 uint64_t u;
52 uint64_t uu;
53 u_int wasconst;
54 u_int isconst;
55 uint64_t constmap[HOST_REGS];
56};
57
58struct ll_entry
59{
60 u_int vaddr;
61 u_int reg32;
62 void *addr;
63 struct ll_entry *next;
64};
65
66 u_int start;
67 u_int *source;
68 u_int pagelimit;
69 char insn[MAXBLOCK][10];
70 u_char itype[MAXBLOCK];
71 u_char opcode[MAXBLOCK];
72 u_char opcode2[MAXBLOCK];
73 u_char bt[MAXBLOCK];
74 u_char rs1[MAXBLOCK];
75 u_char rs2[MAXBLOCK];
76 u_char rt1[MAXBLOCK];
77 u_char rt2[MAXBLOCK];
78 u_char us1[MAXBLOCK];
79 u_char us2[MAXBLOCK];
80 u_char dep1[MAXBLOCK];
81 u_char dep2[MAXBLOCK];
82 u_char lt1[MAXBLOCK];
83 int imm[MAXBLOCK];
84 u_int ba[MAXBLOCK];
85 char likely[MAXBLOCK];
86 char is_ds[MAXBLOCK];
e1190b87 87 char ooo[MAXBLOCK];
57871462 88 uint64_t unneeded_reg[MAXBLOCK];
89 uint64_t unneeded_reg_upper[MAXBLOCK];
90 uint64_t branch_unneeded_reg[MAXBLOCK];
91 uint64_t branch_unneeded_reg_upper[MAXBLOCK];
92 uint64_t p32[MAXBLOCK];
93 uint64_t pr32[MAXBLOCK];
94 signed char regmap_pre[MAXBLOCK][HOST_REGS];
95 signed char regmap[MAXBLOCK][HOST_REGS];
96 signed char regmap_entry[MAXBLOCK][HOST_REGS];
97 uint64_t constmap[MAXBLOCK][HOST_REGS];
57871462 98 struct regstat regs[MAXBLOCK];
99 struct regstat branch_regs[MAXBLOCK];
e1190b87 100 signed char minimum_free_regs[MAXBLOCK];
57871462 101 u_int needed_reg[MAXBLOCK];
102 uint64_t requires_32bit[MAXBLOCK];
103 u_int wont_dirty[MAXBLOCK];
104 u_int will_dirty[MAXBLOCK];
105 int ccadj[MAXBLOCK];
106 int slen;
107 u_int instr_addr[MAXBLOCK];
108 u_int link_addr[MAXBLOCK][3];
109 int linkcount;
110 u_int stubs[MAXBLOCK*3][8];
111 int stubcount;
112 u_int literals[1024][2];
113 int literalcount;
114 int is_delayslot;
115 int cop1_usable;
116 u_char *out;
117 struct ll_entry *jump_in[4096];
118 struct ll_entry *jump_out[4096];
119 struct ll_entry *jump_dirty[4096];
120 u_int hash_table[65536][4] __attribute__((aligned(16)));
121 char shadow[1048576] __attribute__((aligned(16)));
122 void *copy;
123 int expirep;
af4ee1fe 124#ifndef PCSX
57871462 125 u_int using_tlb;
af4ee1fe 126#else
127 static const u_int using_tlb=0;
128#endif
57871462 129 u_int stop_after_jal;
130 extern u_char restore_candidate[512];
131 extern int cycle_count;
132
133 /* registers that may be allocated */
134 /* 1-31 gpr */
135#define HIREG 32 // hi
136#define LOREG 33 // lo
137#define FSREG 34 // FPU status (FCSR)
138#define CSREG 35 // Coprocessor status
139#define CCREG 36 // Cycle count
140#define INVCP 37 // Pointer to invalid_code
619e5ded 141#define MMREG 38 // Pointer to memory_map
142#define ROREG 39 // ram offset (if rdram!=0x80000000)
143#define TEMPREG 40
144#define FTEMP 40 // FPU temporary register
145#define PTEMP 41 // Prefetch temporary register
146#define TLREG 42 // TLB mapping offset
147#define RHASH 43 // Return address hash
148#define RHTBL 44 // Return address hash table address
149#define RTEMP 45 // JR/JALR address register
150#define MAXREG 45
151#define AGEN1 46 // Address generation temporary register
152#define AGEN2 47 // Address generation temporary register
153#define MGEN1 48 // Maptable address generation temporary register
154#define MGEN2 49 // Maptable address generation temporary register
155#define BTREG 50 // Branch target temporary register
57871462 156
157 /* instruction types */
158#define NOP 0 // No operation
159#define LOAD 1 // Load
160#define STORE 2 // Store
161#define LOADLR 3 // Unaligned load
162#define STORELR 4 // Unaligned store
163#define MOV 5 // Move
164#define ALU 6 // Arithmetic/logic
165#define MULTDIV 7 // Multiply/divide
166#define SHIFT 8 // Shift by register
167#define SHIFTIMM 9// Shift by immediate
168#define IMM16 10 // 16-bit immediate
169#define RJUMP 11 // Unconditional jump to register
170#define UJUMP 12 // Unconditional jump
171#define CJUMP 13 // Conditional branch (BEQ/BNE/BGTZ/BLEZ)
172#define SJUMP 14 // Conditional branch (regimm format)
173#define COP0 15 // Coprocessor 0
174#define COP1 16 // Coprocessor 1
175#define C1LS 17 // Coprocessor 1 load/store
176#define FJUMP 18 // Conditional branch (floating point)
177#define FLOAT 19 // Floating point unit
178#define FCONV 20 // Convert integer to float
179#define FCOMP 21 // Floating point compare (sets FSREG)
180#define SYSCALL 22// SYSCALL
181#define OTHER 23 // Other
182#define SPAN 24 // Branch/delay slot spans 2 pages
183#define NI 25 // Not implemented
7139f3c8 184#define HLECALL 26// PCSX fake opcodes for HLE
b9b61529 185#define COP2 27 // Coprocessor 2 move
186#define C2LS 28 // Coprocessor 2 load/store
187#define C2OP 29 // Coprocessor 2 operation
1e973cb0 188#define INTCALL 30// Call interpreter to handle rare corner cases
57871462 189
190 /* stubs */
191#define CC_STUB 1
192#define FP_STUB 2
193#define LOADB_STUB 3
194#define LOADH_STUB 4
195#define LOADW_STUB 5
196#define LOADD_STUB 6
197#define LOADBU_STUB 7
198#define LOADHU_STUB 8
199#define STOREB_STUB 9
200#define STOREH_STUB 10
201#define STOREW_STUB 11
202#define STORED_STUB 12
203#define STORELR_STUB 13
204#define INVCODE_STUB 14
205
206 /* branch codes */
207#define TAKEN 1
208#define NOTTAKEN 2
209#define NULLDS 3
210
211// asm linkage
212int new_recompile_block(int addr);
213void *get_addr_ht(u_int vaddr);
214void invalidate_block(u_int block);
215void invalidate_addr(u_int addr);
216void remove_hash(int vaddr);
217void jump_vaddr();
218void dyna_linker();
219void dyna_linker_ds();
220void verify_code();
221void verify_code_vm();
222void verify_code_ds();
223void cc_interrupt();
224void fp_exception();
225void fp_exception_ds();
226void jump_syscall();
7139f3c8 227void jump_syscall_hle();
57871462 228void jump_eret();
7139f3c8 229void jump_hlecall();
1e973cb0 230void jump_intcall();
7139f3c8 231void new_dyna_leave();
57871462 232
233// TLB
234void TLBWI_new();
235void TLBWR_new();
236void read_nomem_new();
237void read_nomemb_new();
238void read_nomemh_new();
239void read_nomemd_new();
240void write_nomem_new();
241void write_nomemb_new();
242void write_nomemh_new();
243void write_nomemd_new();
244void write_rdram_new();
245void write_rdramb_new();
246void write_rdramh_new();
247void write_rdramd_new();
248extern u_int memory_map[1048576];
249
250// Needed by assembler
251void wb_register(signed char r,signed char regmap[],uint64_t dirty,uint64_t is32);
252void wb_dirtys(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty);
253void wb_needed_dirtys(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr);
254void load_all_regs(signed char i_regmap[]);
255void load_needed_regs(signed char i_regmap[],signed char next_regmap[]);
256void load_regs_entry(int t);
257void load_all_consts(signed char regmap[],int is32,u_int dirty,int i);
258
259int tracedebug=0;
260
261//#define DEBUG_CYCLE_COUNT 1
262
263void nullf() {}
264//#define assem_debug printf
265//#define inv_debug printf
266#define assem_debug nullf
267#define inv_debug nullf
268
94d23bb9 269static void tlb_hacks()
57871462 270{
94d23bb9 271#ifndef DISABLE_TLB
57871462 272 // Goldeneye hack
273 if (strncmp((char *) ROM_HEADER->nom, "GOLDENEYE",9) == 0)
274 {
275 u_int addr;
276 int n;
277 switch (ROM_HEADER->Country_code&0xFF)
278 {
279 case 0x45: // U
280 addr=0x34b30;
281 break;
282 case 0x4A: // J
283 addr=0x34b70;
284 break;
285 case 0x50: // E
286 addr=0x329f0;
287 break;
288 default:
289 // Unknown country code
290 addr=0;
291 break;
292 }
293 u_int rom_addr=(u_int)rom;
294 #ifdef ROM_COPY
295 // Since memory_map is 32-bit, on 64-bit systems the rom needs to be
296 // in the lower 4G of memory to use this hack. Copy it if necessary.
297 if((void *)rom>(void *)0xffffffff) {
298 munmap(ROM_COPY, 67108864);
299 if(mmap(ROM_COPY, 12582912,
300 PROT_READ | PROT_WRITE,
301 MAP_FIXED | MAP_PRIVATE | MAP_ANONYMOUS,
302 -1, 0) <= 0) {printf("mmap() failed\n");}
303 memcpy(ROM_COPY,rom,12582912);
304 rom_addr=(u_int)ROM_COPY;
305 }
306 #endif
307 if(addr) {
308 for(n=0x7F000;n<0x80000;n++) {
309 memory_map[n]=(((u_int)(rom_addr+addr-0x7F000000))>>2)|0x40000000;
310 }
311 }
312 }
94d23bb9 313#endif
57871462 314}
315
94d23bb9 316static u_int get_page(u_int vaddr)
57871462 317{
0ce47d46 318#ifndef PCSX
57871462 319 u_int page=(vaddr^0x80000000)>>12;
0ce47d46 320#else
321 u_int page=vaddr&~0xe0000000;
322 if (page < 0x1000000)
323 page &= ~0x0e00000; // RAM mirrors
324 page>>=12;
325#endif
94d23bb9 326#ifndef DISABLE_TLB
57871462 327 if(page>262143&&tlb_LUT_r[vaddr>>12]) page=(tlb_LUT_r[vaddr>>12]^0x80000000)>>12;
94d23bb9 328#endif
57871462 329 if(page>2048) page=2048+(page&2047);
94d23bb9 330 return page;
331}
332
333static u_int get_vpage(u_int vaddr)
334{
335 u_int vpage=(vaddr^0x80000000)>>12;
336#ifndef DISABLE_TLB
57871462 337 if(vpage>262143&&tlb_LUT_r[vaddr>>12]) vpage&=2047; // jump_dirty uses a hash of the virtual address instead
94d23bb9 338#endif
57871462 339 if(vpage>2048) vpage=2048+(vpage&2047);
94d23bb9 340 return vpage;
341}
342
343// Get address from virtual address
344// This is called from the recompiled JR/JALR instructions
345void *get_addr(u_int vaddr)
346{
347 u_int page=get_page(vaddr);
348 u_int vpage=get_vpage(vaddr);
57871462 349 struct ll_entry *head;
350 //printf("TRACE: count=%d next=%d (get_addr %x,page %d)\n",Count,next_interupt,vaddr,page);
351 head=jump_in[page];
352 while(head!=NULL) {
353 if(head->vaddr==vaddr&&head->reg32==0) {
354 //printf("TRACE: count=%d next=%d (get_addr match %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr);
355 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
356 ht_bin[3]=ht_bin[1];
357 ht_bin[2]=ht_bin[0];
358 ht_bin[1]=(int)head->addr;
359 ht_bin[0]=vaddr;
360 return head->addr;
361 }
362 head=head->next;
363 }
364 head=jump_dirty[vpage];
365 while(head!=NULL) {
366 if(head->vaddr==vaddr&&head->reg32==0) {
367 //printf("TRACE: count=%d next=%d (get_addr match dirty %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr);
368 // Don't restore blocks which are about to expire from the cache
369 if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
370 if(verify_dirty(head->addr)) {
371 //printf("restore candidate: %x (%d) d=%d\n",vaddr,page,invalid_code[vaddr>>12]);
372 invalid_code[vaddr>>12]=0;
373 memory_map[vaddr>>12]|=0x40000000;
374 if(vpage<2048) {
94d23bb9 375#ifndef DISABLE_TLB
57871462 376 if(tlb_LUT_r[vaddr>>12]) {
377 invalid_code[tlb_LUT_r[vaddr>>12]>>12]=0;
378 memory_map[tlb_LUT_r[vaddr>>12]>>12]|=0x40000000;
379 }
94d23bb9 380#endif
57871462 381 restore_candidate[vpage>>3]|=1<<(vpage&7);
382 }
383 else restore_candidate[page>>3]|=1<<(page&7);
384 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
385 if(ht_bin[0]==vaddr) {
386 ht_bin[1]=(int)head->addr; // Replace existing entry
387 }
388 else
389 {
390 ht_bin[3]=ht_bin[1];
391 ht_bin[2]=ht_bin[0];
392 ht_bin[1]=(int)head->addr;
393 ht_bin[0]=vaddr;
394 }
395 return head->addr;
396 }
397 }
398 head=head->next;
399 }
400 //printf("TRACE: count=%d next=%d (get_addr no-match %x)\n",Count,next_interupt,vaddr);
401 int r=new_recompile_block(vaddr);
402 if(r==0) return get_addr(vaddr);
403 // Execute in unmapped page, generate pagefault execption
404 Status|=2;
405 Cause=(vaddr<<31)|0x8;
406 EPC=(vaddr&1)?vaddr-5:vaddr;
407 BadVAddr=(vaddr&~1);
408 Context=(Context&0xFF80000F)|((BadVAddr>>9)&0x007FFFF0);
409 EntryHi=BadVAddr&0xFFFFE000;
410 return get_addr_ht(0x80000000);
411}
412// Look up address in hash table first
413void *get_addr_ht(u_int vaddr)
414{
415 //printf("TRACE: count=%d next=%d (get_addr_ht %x)\n",Count,next_interupt,vaddr);
416 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
417 if(ht_bin[0]==vaddr) return (void *)ht_bin[1];
418 if(ht_bin[2]==vaddr) return (void *)ht_bin[3];
419 return get_addr(vaddr);
420}
421
422void *get_addr_32(u_int vaddr,u_int flags)
423{
7139f3c8 424#ifdef FORCE32
425 return get_addr(vaddr);
560e4a12 426#else
57871462 427 //printf("TRACE: count=%d next=%d (get_addr_32 %x,flags %x)\n",Count,next_interupt,vaddr,flags);
428 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
429 if(ht_bin[0]==vaddr) return (void *)ht_bin[1];
430 if(ht_bin[2]==vaddr) return (void *)ht_bin[3];
94d23bb9 431 u_int page=get_page(vaddr);
432 u_int vpage=get_vpage(vaddr);
57871462 433 struct ll_entry *head;
434 head=jump_in[page];
435 while(head!=NULL) {
436 if(head->vaddr==vaddr&&(head->reg32&flags)==0) {
437 //printf("TRACE: count=%d next=%d (get_addr_32 match %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr);
438 if(head->reg32==0) {
439 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
440 if(ht_bin[0]==-1) {
441 ht_bin[1]=(int)head->addr;
442 ht_bin[0]=vaddr;
443 }else if(ht_bin[2]==-1) {
444 ht_bin[3]=(int)head->addr;
445 ht_bin[2]=vaddr;
446 }
447 //ht_bin[3]=ht_bin[1];
448 //ht_bin[2]=ht_bin[0];
449 //ht_bin[1]=(int)head->addr;
450 //ht_bin[0]=vaddr;
451 }
452 return head->addr;
453 }
454 head=head->next;
455 }
456 head=jump_dirty[vpage];
457 while(head!=NULL) {
458 if(head->vaddr==vaddr&&(head->reg32&flags)==0) {
459 //printf("TRACE: count=%d next=%d (get_addr_32 match dirty %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr);
460 // Don't restore blocks which are about to expire from the cache
461 if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
462 if(verify_dirty(head->addr)) {
463 //printf("restore candidate: %x (%d) d=%d\n",vaddr,page,invalid_code[vaddr>>12]);
464 invalid_code[vaddr>>12]=0;
465 memory_map[vaddr>>12]|=0x40000000;
466 if(vpage<2048) {
94d23bb9 467#ifndef DISABLE_TLB
57871462 468 if(tlb_LUT_r[vaddr>>12]) {
469 invalid_code[tlb_LUT_r[vaddr>>12]>>12]=0;
470 memory_map[tlb_LUT_r[vaddr>>12]>>12]|=0x40000000;
471 }
94d23bb9 472#endif
57871462 473 restore_candidate[vpage>>3]|=1<<(vpage&7);
474 }
475 else restore_candidate[page>>3]|=1<<(page&7);
476 if(head->reg32==0) {
477 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
478 if(ht_bin[0]==-1) {
479 ht_bin[1]=(int)head->addr;
480 ht_bin[0]=vaddr;
481 }else if(ht_bin[2]==-1) {
482 ht_bin[3]=(int)head->addr;
483 ht_bin[2]=vaddr;
484 }
485 //ht_bin[3]=ht_bin[1];
486 //ht_bin[2]=ht_bin[0];
487 //ht_bin[1]=(int)head->addr;
488 //ht_bin[0]=vaddr;
489 }
490 return head->addr;
491 }
492 }
493 head=head->next;
494 }
495 //printf("TRACE: count=%d next=%d (get_addr_32 no-match %x,flags %x)\n",Count,next_interupt,vaddr,flags);
496 int r=new_recompile_block(vaddr);
497 if(r==0) return get_addr(vaddr);
498 // Execute in unmapped page, generate pagefault execption
499 Status|=2;
500 Cause=(vaddr<<31)|0x8;
501 EPC=(vaddr&1)?vaddr-5:vaddr;
502 BadVAddr=(vaddr&~1);
503 Context=(Context&0xFF80000F)|((BadVAddr>>9)&0x007FFFF0);
504 EntryHi=BadVAddr&0xFFFFE000;
505 return get_addr_ht(0x80000000);
560e4a12 506#endif
57871462 507}
508
509void clear_all_regs(signed char regmap[])
510{
511 int hr;
512 for (hr=0;hr<HOST_REGS;hr++) regmap[hr]=-1;
513}
514
515signed char get_reg(signed char regmap[],int r)
516{
517 int hr;
518 for (hr=0;hr<HOST_REGS;hr++) if(hr!=EXCLUDE_REG&&regmap[hr]==r) return hr;
519 return -1;
520}
521
522// Find a register that is available for two consecutive cycles
523signed char get_reg2(signed char regmap1[],signed char regmap2[],int r)
524{
525 int hr;
526 for (hr=0;hr<HOST_REGS;hr++) if(hr!=EXCLUDE_REG&&regmap1[hr]==r&&regmap2[hr]==r) return hr;
527 return -1;
528}
529
530int count_free_regs(signed char regmap[])
531{
532 int count=0;
533 int hr;
534 for(hr=0;hr<HOST_REGS;hr++)
535 {
536 if(hr!=EXCLUDE_REG) {
537 if(regmap[hr]<0) count++;
538 }
539 }
540 return count;
541}
542
543void dirty_reg(struct regstat *cur,signed char reg)
544{
545 int hr;
546 if(!reg) return;
547 for (hr=0;hr<HOST_REGS;hr++) {
548 if((cur->regmap[hr]&63)==reg) {
549 cur->dirty|=1<<hr;
550 }
551 }
552}
553
554// If we dirty the lower half of a 64 bit register which is now being
555// sign-extended, we need to dump the upper half.
556// Note: Do this only after completion of the instruction, because
557// some instructions may need to read the full 64-bit value even if
558// overwriting it (eg SLTI, DSRA32).
559static void flush_dirty_uppers(struct regstat *cur)
560{
561 int hr,reg;
562 for (hr=0;hr<HOST_REGS;hr++) {
563 if((cur->dirty>>hr)&1) {
564 reg=cur->regmap[hr];
565 if(reg>=64)
566 if((cur->is32>>(reg&63))&1) cur->regmap[hr]=-1;
567 }
568 }
569}
570
571void set_const(struct regstat *cur,signed char reg,uint64_t value)
572{
573 int hr;
574 if(!reg) return;
575 for (hr=0;hr<HOST_REGS;hr++) {
576 if(cur->regmap[hr]==reg) {
577 cur->isconst|=1<<hr;
578 cur->constmap[hr]=value;
579 }
580 else if((cur->regmap[hr]^64)==reg) {
581 cur->isconst|=1<<hr;
582 cur->constmap[hr]=value>>32;
583 }
584 }
585}
586
587void clear_const(struct regstat *cur,signed char reg)
588{
589 int hr;
590 if(!reg) return;
591 for (hr=0;hr<HOST_REGS;hr++) {
592 if((cur->regmap[hr]&63)==reg) {
593 cur->isconst&=~(1<<hr);
594 }
595 }
596}
597
598int is_const(struct regstat *cur,signed char reg)
599{
600 int hr;
601 if(!reg) return 1;
602 for (hr=0;hr<HOST_REGS;hr++) {
603 if((cur->regmap[hr]&63)==reg) {
604 return (cur->isconst>>hr)&1;
605 }
606 }
607 return 0;
608}
609uint64_t get_const(struct regstat *cur,signed char reg)
610{
611 int hr;
612 if(!reg) return 0;
613 for (hr=0;hr<HOST_REGS;hr++) {
614 if(cur->regmap[hr]==reg) {
615 return cur->constmap[hr];
616 }
617 }
618 printf("Unknown constant in r%d\n",reg);
619 exit(1);
620}
621
622// Least soon needed registers
623// Look at the next ten instructions and see which registers
624// will be used. Try not to reallocate these.
625void lsn(u_char hsn[], int i, int *preferred_reg)
626{
627 int j;
628 int b=-1;
629 for(j=0;j<9;j++)
630 {
631 if(i+j>=slen) {
632 j=slen-i-1;
633 break;
634 }
635 if(itype[i+j]==UJUMP||itype[i+j]==RJUMP||(source[i+j]>>16)==0x1000)
636 {
637 // Don't go past an unconditonal jump
638 j++;
639 break;
640 }
641 }
642 for(;j>=0;j--)
643 {
644 if(rs1[i+j]) hsn[rs1[i+j]]=j;
645 if(rs2[i+j]) hsn[rs2[i+j]]=j;
646 if(rt1[i+j]) hsn[rt1[i+j]]=j;
647 if(rt2[i+j]) hsn[rt2[i+j]]=j;
648 if(itype[i+j]==STORE || itype[i+j]==STORELR) {
649 // Stores can allocate zero
650 hsn[rs1[i+j]]=j;
651 hsn[rs2[i+j]]=j;
652 }
653 // On some architectures stores need invc_ptr
654 #if defined(HOST_IMM8)
b9b61529 655 if(itype[i+j]==STORE || itype[i+j]==STORELR || (opcode[i+j]&0x3b)==0x39 || (opcode[i+j]&0x3b)==0x3a) {
57871462 656 hsn[INVCP]=j;
657 }
658 #endif
659 if(i+j>=0&&(itype[i+j]==UJUMP||itype[i+j]==CJUMP||itype[i+j]==SJUMP||itype[i+j]==FJUMP))
660 {
661 hsn[CCREG]=j;
662 b=j;
663 }
664 }
665 if(b>=0)
666 {
667 if(ba[i+b]>=start && ba[i+b]<(start+slen*4))
668 {
669 // Follow first branch
670 int t=(ba[i+b]-start)>>2;
671 j=7-b;if(t+j>=slen) j=slen-t-1;
672 for(;j>=0;j--)
673 {
674 if(rs1[t+j]) if(hsn[rs1[t+j]]>j+b+2) hsn[rs1[t+j]]=j+b+2;
675 if(rs2[t+j]) if(hsn[rs2[t+j]]>j+b+2) hsn[rs2[t+j]]=j+b+2;
676 //if(rt1[t+j]) if(hsn[rt1[t+j]]>j+b+2) hsn[rt1[t+j]]=j+b+2;
677 //if(rt2[t+j]) if(hsn[rt2[t+j]]>j+b+2) hsn[rt2[t+j]]=j+b+2;
678 }
679 }
680 // TODO: preferred register based on backward branch
681 }
682 // Delay slot should preferably not overwrite branch conditions or cycle count
683 if(i>0&&(itype[i-1]==RJUMP||itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP)) {
684 if(rs1[i-1]) if(hsn[rs1[i-1]]>1) hsn[rs1[i-1]]=1;
685 if(rs2[i-1]) if(hsn[rs2[i-1]]>1) hsn[rs2[i-1]]=1;
686 hsn[CCREG]=1;
687 // ...or hash tables
688 hsn[RHASH]=1;
689 hsn[RHTBL]=1;
690 }
691 // Coprocessor load/store needs FTEMP, even if not declared
b9b61529 692 if(itype[i]==C1LS||itype[i]==C2LS) {
57871462 693 hsn[FTEMP]=0;
694 }
695 // Load L/R also uses FTEMP as a temporary register
696 if(itype[i]==LOADLR) {
697 hsn[FTEMP]=0;
698 }
b7918751 699 // Also SWL/SWR/SDL/SDR
700 if(opcode[i]==0x2a||opcode[i]==0x2e||opcode[i]==0x2c||opcode[i]==0x2d) {
57871462 701 hsn[FTEMP]=0;
702 }
703 // Don't remove the TLB registers either
b9b61529 704 if(itype[i]==LOAD || itype[i]==LOADLR || itype[i]==STORE || itype[i]==STORELR || itype[i]==C1LS || itype[i]==C2LS) {
57871462 705 hsn[TLREG]=0;
706 }
707 // Don't remove the miniht registers
708 if(itype[i]==UJUMP||itype[i]==RJUMP)
709 {
710 hsn[RHASH]=0;
711 hsn[RHTBL]=0;
712 }
713}
714
715// We only want to allocate registers if we're going to use them again soon
716int needed_again(int r, int i)
717{
718 int j;
719 int b=-1;
720 int rn=10;
721 int hr;
722 u_char hsn[MAXREG+1];
723 int preferred_reg;
724
725 memset(hsn,10,sizeof(hsn));
726 lsn(hsn,i,&preferred_reg);
727
728 if(i>0&&(itype[i-1]==UJUMP||itype[i-1]==RJUMP||(source[i-1]>>16)==0x1000))
729 {
730 if(ba[i-1]<start || ba[i-1]>start+slen*4-4)
731 return 0; // Don't need any registers if exiting the block
732 }
733 for(j=0;j<9;j++)
734 {
735 if(i+j>=slen) {
736 j=slen-i-1;
737 break;
738 }
739 if(itype[i+j]==UJUMP||itype[i+j]==RJUMP||(source[i+j]>>16)==0x1000)
740 {
741 // Don't go past an unconditonal jump
742 j++;
743 break;
744 }
1e973cb0 745 if(itype[i+j]==SYSCALL||itype[i+j]==HLECALL||itype[i+j]==INTCALL||((source[i+j]&0xfc00003f)==0x0d))
57871462 746 {
747 break;
748 }
749 }
750 for(;j>=1;j--)
751 {
752 if(rs1[i+j]==r) rn=j;
753 if(rs2[i+j]==r) rn=j;
754 if((unneeded_reg[i+j]>>r)&1) rn=10;
755 if(i+j>=0&&(itype[i+j]==UJUMP||itype[i+j]==CJUMP||itype[i+j]==SJUMP||itype[i+j]==FJUMP))
756 {
757 b=j;
758 }
759 }
760 /*
761 if(b>=0)
762 {
763 if(ba[i+b]>=start && ba[i+b]<(start+slen*4))
764 {
765 // Follow first branch
766 int o=rn;
767 int t=(ba[i+b]-start)>>2;
768 j=7-b;if(t+j>=slen) j=slen-t-1;
769 for(;j>=0;j--)
770 {
771 if(!((unneeded_reg[t+j]>>r)&1)) {
772 if(rs1[t+j]==r) if(rn>j+b+2) rn=j+b+2;
773 if(rs2[t+j]==r) if(rn>j+b+2) rn=j+b+2;
774 }
775 else rn=o;
776 }
777 }
778 }*/
779 for(hr=0;hr<HOST_REGS;hr++) {
780 if(hr!=EXCLUDE_REG) {
781 if(rn<hsn[hr]) return 1;
782 }
783 }
784 return 0;
785}
786
787// Try to match register allocations at the end of a loop with those
788// at the beginning
789int loop_reg(int i, int r, int hr)
790{
791 int j,k;
792 for(j=0;j<9;j++)
793 {
794 if(i+j>=slen) {
795 j=slen-i-1;
796 break;
797 }
798 if(itype[i+j]==UJUMP||itype[i+j]==RJUMP||(source[i+j]>>16)==0x1000)
799 {
800 // Don't go past an unconditonal jump
801 j++;
802 break;
803 }
804 }
805 k=0;
806 if(i>0){
807 if(itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP)
808 k--;
809 }
810 for(;k<j;k++)
811 {
812 if(r<64&&((unneeded_reg[i+k]>>r)&1)) return hr;
813 if(r>64&&((unneeded_reg_upper[i+k]>>r)&1)) return hr;
814 if(i+k>=0&&(itype[i+k]==UJUMP||itype[i+k]==CJUMP||itype[i+k]==SJUMP||itype[i+k]==FJUMP))
815 {
816 if(ba[i+k]>=start && ba[i+k]<(start+i*4))
817 {
818 int t=(ba[i+k]-start)>>2;
819 int reg=get_reg(regs[t].regmap_entry,r);
820 if(reg>=0) return reg;
821 //reg=get_reg(regs[t+1].regmap_entry,r);
822 //if(reg>=0) return reg;
823 }
824 }
825 }
826 return hr;
827}
828
829
830// Allocate every register, preserving source/target regs
831void alloc_all(struct regstat *cur,int i)
832{
833 int hr;
834
835 for(hr=0;hr<HOST_REGS;hr++) {
836 if(hr!=EXCLUDE_REG) {
837 if(((cur->regmap[hr]&63)!=rs1[i])&&((cur->regmap[hr]&63)!=rs2[i])&&
838 ((cur->regmap[hr]&63)!=rt1[i])&&((cur->regmap[hr]&63)!=rt2[i]))
839 {
840 cur->regmap[hr]=-1;
841 cur->dirty&=~(1<<hr);
842 }
843 // Don't need zeros
844 if((cur->regmap[hr]&63)==0)
845 {
846 cur->regmap[hr]=-1;
847 cur->dirty&=~(1<<hr);
848 }
849 }
850 }
851}
852
853
854void div64(int64_t dividend,int64_t divisor)
855{
856 lo=dividend/divisor;
857 hi=dividend%divisor;
858 //printf("TRACE: ddiv %8x%8x %8x%8x\n" ,(int)reg[HIREG],(int)(reg[HIREG]>>32)
859 // ,(int)reg[LOREG],(int)(reg[LOREG]>>32));
860}
861void divu64(uint64_t dividend,uint64_t divisor)
862{
863 lo=dividend/divisor;
864 hi=dividend%divisor;
865 //printf("TRACE: ddivu %8x%8x %8x%8x\n",(int)reg[HIREG],(int)(reg[HIREG]>>32)
866 // ,(int)reg[LOREG],(int)(reg[LOREG]>>32));
867}
868
869void mult64(uint64_t m1,uint64_t m2)
870{
871 unsigned long long int op1, op2, op3, op4;
872 unsigned long long int result1, result2, result3, result4;
873 unsigned long long int temp1, temp2, temp3, temp4;
874 int sign = 0;
875
876 if (m1 < 0)
877 {
878 op2 = -m1;
879 sign = 1 - sign;
880 }
881 else op2 = m1;
882 if (m2 < 0)
883 {
884 op4 = -m2;
885 sign = 1 - sign;
886 }
887 else op4 = m2;
888
889 op1 = op2 & 0xFFFFFFFF;
890 op2 = (op2 >> 32) & 0xFFFFFFFF;
891 op3 = op4 & 0xFFFFFFFF;
892 op4 = (op4 >> 32) & 0xFFFFFFFF;
893
894 temp1 = op1 * op3;
895 temp2 = (temp1 >> 32) + op1 * op4;
896 temp3 = op2 * op3;
897 temp4 = (temp3 >> 32) + op2 * op4;
898
899 result1 = temp1 & 0xFFFFFFFF;
900 result2 = temp2 + (temp3 & 0xFFFFFFFF);
901 result3 = (result2 >> 32) + temp4;
902 result4 = (result3 >> 32);
903
904 lo = result1 | (result2 << 32);
905 hi = (result3 & 0xFFFFFFFF) | (result4 << 32);
906 if (sign)
907 {
908 hi = ~hi;
909 if (!lo) hi++;
910 else lo = ~lo + 1;
911 }
912}
913
914void multu64(uint64_t m1,uint64_t m2)
915{
916 unsigned long long int op1, op2, op3, op4;
917 unsigned long long int result1, result2, result3, result4;
918 unsigned long long int temp1, temp2, temp3, temp4;
919
920 op1 = m1 & 0xFFFFFFFF;
921 op2 = (m1 >> 32) & 0xFFFFFFFF;
922 op3 = m2 & 0xFFFFFFFF;
923 op4 = (m2 >> 32) & 0xFFFFFFFF;
924
925 temp1 = op1 * op3;
926 temp2 = (temp1 >> 32) + op1 * op4;
927 temp3 = op2 * op3;
928 temp4 = (temp3 >> 32) + op2 * op4;
929
930 result1 = temp1 & 0xFFFFFFFF;
931 result2 = temp2 + (temp3 & 0xFFFFFFFF);
932 result3 = (result2 >> 32) + temp4;
933 result4 = (result3 >> 32);
934
935 lo = result1 | (result2 << 32);
936 hi = (result3 & 0xFFFFFFFF) | (result4 << 32);
937
938 //printf("TRACE: dmultu %8x%8x %8x%8x\n",(int)reg[HIREG],(int)(reg[HIREG]>>32)
939 // ,(int)reg[LOREG],(int)(reg[LOREG]>>32));
940}
941
942uint64_t ldl_merge(uint64_t original,uint64_t loaded,u_int bits)
943{
944 if(bits) {
945 original<<=64-bits;
946 original>>=64-bits;
947 loaded<<=bits;
948 original|=loaded;
949 }
950 else original=loaded;
951 return original;
952}
953uint64_t ldr_merge(uint64_t original,uint64_t loaded,u_int bits)
954{
955 if(bits^56) {
956 original>>=64-(bits^56);
957 original<<=64-(bits^56);
958 loaded>>=bits^56;
959 original|=loaded;
960 }
961 else original=loaded;
962 return original;
963}
964
965#ifdef __i386__
966#include "assem_x86.c"
967#endif
968#ifdef __x86_64__
969#include "assem_x64.c"
970#endif
971#ifdef __arm__
972#include "assem_arm.c"
973#endif
974
975// Add virtual address mapping to linked list
976void ll_add(struct ll_entry **head,int vaddr,void *addr)
977{
978 struct ll_entry *new_entry;
979 new_entry=malloc(sizeof(struct ll_entry));
980 assert(new_entry!=NULL);
981 new_entry->vaddr=vaddr;
982 new_entry->reg32=0;
983 new_entry->addr=addr;
984 new_entry->next=*head;
985 *head=new_entry;
986}
987
988// Add virtual address mapping for 32-bit compiled block
989void ll_add_32(struct ll_entry **head,int vaddr,u_int reg32,void *addr)
990{
7139f3c8 991 ll_add(head,vaddr,addr);
992#ifndef FORCE32
993 (*head)->reg32=reg32;
994#endif
57871462 995}
996
997// Check if an address is already compiled
998// but don't return addresses which are about to expire from the cache
999void *check_addr(u_int vaddr)
1000{
1001 u_int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
1002 if(ht_bin[0]==vaddr) {
1003 if(((ht_bin[1]-MAX_OUTPUT_BLOCK_SIZE-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
1004 if(isclean(ht_bin[1])) return (void *)ht_bin[1];
1005 }
1006 if(ht_bin[2]==vaddr) {
1007 if(((ht_bin[3]-MAX_OUTPUT_BLOCK_SIZE-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
1008 if(isclean(ht_bin[3])) return (void *)ht_bin[3];
1009 }
94d23bb9 1010 u_int page=get_page(vaddr);
57871462 1011 struct ll_entry *head;
1012 head=jump_in[page];
1013 while(head!=NULL) {
1014 if(head->vaddr==vaddr&&head->reg32==0) {
1015 if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2))) {
1016 // Update existing entry with current address
1017 if(ht_bin[0]==vaddr) {
1018 ht_bin[1]=(int)head->addr;
1019 return head->addr;
1020 }
1021 if(ht_bin[2]==vaddr) {
1022 ht_bin[3]=(int)head->addr;
1023 return head->addr;
1024 }
1025 // Insert into hash table with low priority.
1026 // Don't evict existing entries, as they are probably
1027 // addresses that are being accessed frequently.
1028 if(ht_bin[0]==-1) {
1029 ht_bin[1]=(int)head->addr;
1030 ht_bin[0]=vaddr;
1031 }else if(ht_bin[2]==-1) {
1032 ht_bin[3]=(int)head->addr;
1033 ht_bin[2]=vaddr;
1034 }
1035 return head->addr;
1036 }
1037 }
1038 head=head->next;
1039 }
1040 return 0;
1041}
1042
1043void remove_hash(int vaddr)
1044{
1045 //printf("remove hash: %x\n",vaddr);
1046 int *ht_bin=hash_table[(((vaddr)>>16)^vaddr)&0xFFFF];
1047 if(ht_bin[2]==vaddr) {
1048 ht_bin[2]=ht_bin[3]=-1;
1049 }
1050 if(ht_bin[0]==vaddr) {
1051 ht_bin[0]=ht_bin[2];
1052 ht_bin[1]=ht_bin[3];
1053 ht_bin[2]=ht_bin[3]=-1;
1054 }
1055}
1056
1057void ll_remove_matching_addrs(struct ll_entry **head,int addr,int shift)
1058{
1059 struct ll_entry *next;
1060 while(*head) {
1061 if(((u_int)((*head)->addr)>>shift)==(addr>>shift) ||
1062 ((u_int)((*head)->addr-MAX_OUTPUT_BLOCK_SIZE)>>shift)==(addr>>shift))
1063 {
1064 inv_debug("EXP: Remove pointer to %x (%x)\n",(int)(*head)->addr,(*head)->vaddr);
1065 remove_hash((*head)->vaddr);
1066 next=(*head)->next;
1067 free(*head);
1068 *head=next;
1069 }
1070 else
1071 {
1072 head=&((*head)->next);
1073 }
1074 }
1075}
1076
1077// Remove all entries from linked list
1078void ll_clear(struct ll_entry **head)
1079{
1080 struct ll_entry *cur;
1081 struct ll_entry *next;
1082 if(cur=*head) {
1083 *head=0;
1084 while(cur) {
1085 next=cur->next;
1086 free(cur);
1087 cur=next;
1088 }
1089 }
1090}
1091
1092// Dereference the pointers and remove if it matches
1093void ll_kill_pointers(struct ll_entry *head,int addr,int shift)
1094{
1095 while(head) {
1096 int ptr=get_pointer(head->addr);
1097 inv_debug("EXP: Lookup pointer to %x at %x (%x)\n",(int)ptr,(int)head->addr,head->vaddr);
1098 if(((ptr>>shift)==(addr>>shift)) ||
1099 (((ptr-MAX_OUTPUT_BLOCK_SIZE)>>shift)==(addr>>shift)))
1100 {
5088bb70 1101 inv_debug("EXP: Kill pointer at %x (%x)\n",(int)head->addr,head->vaddr);
f76eeef9 1102 u_int host_addr=(u_int)kill_pointer(head->addr);
dd3a91a1 1103 #ifdef __arm__
1104 needs_clear_cache[(host_addr-(u_int)BASE_ADDR)>>17]|=1<<(((host_addr-(u_int)BASE_ADDR)>>12)&31);
1105 #endif
57871462 1106 }
1107 head=head->next;
1108 }
1109}
1110
1111// This is called when we write to a compiled block (see do_invstub)
f76eeef9 1112void invalidate_page(u_int page)
57871462 1113{
57871462 1114 struct ll_entry *head;
1115 struct ll_entry *next;
1116 head=jump_in[page];
1117 jump_in[page]=0;
1118 while(head!=NULL) {
1119 inv_debug("INVALIDATE: %x\n",head->vaddr);
1120 remove_hash(head->vaddr);
1121 next=head->next;
1122 free(head);
1123 head=next;
1124 }
1125 head=jump_out[page];
1126 jump_out[page]=0;
1127 while(head!=NULL) {
1128 inv_debug("INVALIDATE: kill pointer to %x (%x)\n",head->vaddr,(int)head->addr);
f76eeef9 1129 u_int host_addr=(u_int)kill_pointer(head->addr);
dd3a91a1 1130 #ifdef __arm__
1131 needs_clear_cache[(host_addr-(u_int)BASE_ADDR)>>17]|=1<<(((host_addr-(u_int)BASE_ADDR)>>12)&31);
1132 #endif
57871462 1133 next=head->next;
1134 free(head);
1135 head=next;
1136 }
57871462 1137}
1138void invalidate_block(u_int block)
1139{
94d23bb9 1140 u_int page=get_page(block<<12);
1141 u_int vpage=get_vpage(block<<12);
57871462 1142 inv_debug("INVALIDATE: %x (%d)\n",block<<12,page);
1143 //inv_debug("invalid_code[block]=%d\n",invalid_code[block]);
1144 u_int first,last;
1145 first=last=page;
1146 struct ll_entry *head;
1147 head=jump_dirty[vpage];
1148 //printf("page=%d vpage=%d\n",page,vpage);
1149 while(head!=NULL) {
1150 u_int start,end;
1151 if(vpage>2047||(head->vaddr>>12)==block) { // Ignore vaddr hash collision
1152 get_bounds((int)head->addr,&start,&end);
1153 //printf("start: %x end: %x\n",start,end);
4cb76aa4 1154 if(page<2048&&start>=0x80000000&&end<0x80000000+RAM_SIZE) {
57871462 1155 if(((start-(u_int)rdram)>>12)<=page&&((end-1-(u_int)rdram)>>12)>=page) {
1156 if((((start-(u_int)rdram)>>12)&2047)<first) first=((start-(u_int)rdram)>>12)&2047;
1157 if((((end-1-(u_int)rdram)>>12)&2047)>last) last=((end-1-(u_int)rdram)>>12)&2047;
1158 }
1159 }
90ae6d4e 1160#ifndef DISABLE_TLB
57871462 1161 if(page<2048&&(signed int)start>=(signed int)0xC0000000&&(signed int)end>=(signed int)0xC0000000) {
1162 if(((start+memory_map[start>>12]-(u_int)rdram)>>12)<=page&&((end-1+memory_map[(end-1)>>12]-(u_int)rdram)>>12)>=page) {
1163 if((((start+memory_map[start>>12]-(u_int)rdram)>>12)&2047)<first) first=((start+memory_map[start>>12]-(u_int)rdram)>>12)&2047;
1164 if((((end-1+memory_map[(end-1)>>12]-(u_int)rdram)>>12)&2047)>last) last=((end-1+memory_map[(end-1)>>12]-(u_int)rdram)>>12)&2047;
1165 }
1166 }
90ae6d4e 1167#endif
57871462 1168 }
1169 head=head->next;
1170 }
1171 //printf("first=%d last=%d\n",first,last);
f76eeef9 1172 invalidate_page(page);
57871462 1173 assert(first+5>page); // NB: this assumes MAXBLOCK<=4096 (4 pages)
1174 assert(last<page+5);
1175 // Invalidate the adjacent pages if a block crosses a 4K boundary
1176 while(first<page) {
1177 invalidate_page(first);
1178 first++;
1179 }
1180 for(first=page+1;first<last;first++) {
1181 invalidate_page(first);
1182 }
dd3a91a1 1183 #ifdef __arm__
1184 do_clear_cache();
1185 #endif
57871462 1186
1187 // Don't trap writes
1188 invalid_code[block]=1;
b12c9fb8 1189#ifdef PCSX
1190 invalid_code[((u_int)0x80000000>>12)|page]=1;
1191#endif
94d23bb9 1192#ifndef DISABLE_TLB
57871462 1193 // If there is a valid TLB entry for this page, remove write protect
1194 if(tlb_LUT_w[block]) {
1195 assert(tlb_LUT_r[block]==tlb_LUT_w[block]);
1196 // CHECK: Is this right?
1197 memory_map[block]=((tlb_LUT_w[block]&0xFFFFF000)-(block<<12)+(unsigned int)rdram-0x80000000)>>2;
1198 u_int real_block=tlb_LUT_w[block]>>12;
1199 invalid_code[real_block]=1;
1200 if(real_block>=0x80000&&real_block<0x80800) memory_map[real_block]=((u_int)rdram-0x80000000)>>2;
1201 }
1202 else if(block>=0x80000&&block<0x80800) memory_map[block]=((u_int)rdram-0x80000000)>>2;
94d23bb9 1203#endif
f76eeef9 1204
57871462 1205 #ifdef USE_MINI_HT
1206 memset(mini_ht,-1,sizeof(mini_ht));
1207 #endif
1208}
1209void invalidate_addr(u_int addr)
1210{
1211 invalidate_block(addr>>12);
1212}
dd3a91a1 1213// This is called when loading a save state.
1214// Anything could have changed, so invalidate everything.
57871462 1215void invalidate_all_pages()
1216{
1217 u_int page,n;
1218 for(page=0;page<4096;page++)
1219 invalidate_page(page);
1220 for(page=0;page<1048576;page++)
1221 if(!invalid_code[page]) {
1222 restore_candidate[(page&2047)>>3]|=1<<(page&7);
1223 restore_candidate[((page&2047)>>3)+256]|=1<<(page&7);
1224 }
1225 #ifdef __arm__
1226 __clear_cache((void *)BASE_ADDR,(void *)BASE_ADDR+(1<<TARGET_SIZE_2));
1227 #endif
1228 #ifdef USE_MINI_HT
1229 memset(mini_ht,-1,sizeof(mini_ht));
1230 #endif
94d23bb9 1231 #ifndef DISABLE_TLB
57871462 1232 // TLB
1233 for(page=0;page<0x100000;page++) {
1234 if(tlb_LUT_r[page]) {
1235 memory_map[page]=((tlb_LUT_r[page]&0xFFFFF000)-(page<<12)+(unsigned int)rdram-0x80000000)>>2;
1236 if(!tlb_LUT_w[page]||!invalid_code[page])
1237 memory_map[page]|=0x40000000; // Write protect
1238 }
1239 else memory_map[page]=-1;
1240 if(page==0x80000) page=0xC0000;
1241 }
1242 tlb_hacks();
94d23bb9 1243 #endif
57871462 1244}
1245
1246// Add an entry to jump_out after making a link
1247void add_link(u_int vaddr,void *src)
1248{
94d23bb9 1249 u_int page=get_page(vaddr);
57871462 1250 inv_debug("add_link: %x -> %x (%d)\n",(int)src,vaddr,page);
1251 ll_add(jump_out+page,vaddr,src);
1252 //int ptr=get_pointer(src);
1253 //inv_debug("add_link: Pointer is to %x\n",(int)ptr);
1254}
1255
1256// If a code block was found to be unmodified (bit was set in
1257// restore_candidate) and it remains unmodified (bit is clear
1258// in invalid_code) then move the entries for that 4K page from
1259// the dirty list to the clean list.
1260void clean_blocks(u_int page)
1261{
1262 struct ll_entry *head;
1263 inv_debug("INV: clean_blocks page=%d\n",page);
1264 head=jump_dirty[page];
1265 while(head!=NULL) {
1266 if(!invalid_code[head->vaddr>>12]) {
1267 // Don't restore blocks which are about to expire from the cache
1268 if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2))) {
1269 u_int start,end;
1270 if(verify_dirty((int)head->addr)) {
1271 //printf("Possibly Restore %x (%x)\n",head->vaddr, (int)head->addr);
1272 u_int i;
1273 u_int inv=0;
1274 get_bounds((int)head->addr,&start,&end);
4cb76aa4 1275 if(start-(u_int)rdram<RAM_SIZE) {
57871462 1276 for(i=(start-(u_int)rdram+0x80000000)>>12;i<=(end-1-(u_int)rdram+0x80000000)>>12;i++) {
1277 inv|=invalid_code[i];
1278 }
1279 }
1280 if((signed int)head->vaddr>=(signed int)0xC0000000) {
1281 u_int addr = (head->vaddr+(memory_map[head->vaddr>>12]<<2));
1282 //printf("addr=%x start=%x end=%x\n",addr,start,end);
1283 if(addr<start||addr>=end) inv=1;
1284 }
4cb76aa4 1285 else if((signed int)head->vaddr>=(signed int)0x80000000+RAM_SIZE) {
57871462 1286 inv=1;
1287 }
1288 if(!inv) {
1289 void * clean_addr=(void *)get_clean_addr((int)head->addr);
1290 if((((u_int)clean_addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2))) {
1291 u_int ppage=page;
94d23bb9 1292#ifndef DISABLE_TLB
57871462 1293 if(page<2048&&tlb_LUT_r[head->vaddr>>12]) ppage=(tlb_LUT_r[head->vaddr>>12]^0x80000000)>>12;
94d23bb9 1294#endif
57871462 1295 inv_debug("INV: Restored %x (%x/%x)\n",head->vaddr, (int)head->addr, (int)clean_addr);
1296 //printf("page=%x, addr=%x\n",page,head->vaddr);
1297 //assert(head->vaddr>>12==(page|0x80000));
1298 ll_add_32(jump_in+ppage,head->vaddr,head->reg32,clean_addr);
1299 int *ht_bin=hash_table[((head->vaddr>>16)^head->vaddr)&0xFFFF];
1300 if(!head->reg32) {
1301 if(ht_bin[0]==head->vaddr) {
1302 ht_bin[1]=(int)clean_addr; // Replace existing entry
1303 }
1304 if(ht_bin[2]==head->vaddr) {
1305 ht_bin[3]=(int)clean_addr; // Replace existing entry
1306 }
1307 }
1308 }
1309 }
1310 }
1311 }
1312 }
1313 head=head->next;
1314 }
1315}
1316
1317
1318void mov_alloc(struct regstat *current,int i)
1319{
1320 // Note: Don't need to actually alloc the source registers
1321 if((~current->is32>>rs1[i])&1) {
1322 //alloc_reg64(current,i,rs1[i]);
1323 alloc_reg64(current,i,rt1[i]);
1324 current->is32&=~(1LL<<rt1[i]);
1325 } else {
1326 //alloc_reg(current,i,rs1[i]);
1327 alloc_reg(current,i,rt1[i]);
1328 current->is32|=(1LL<<rt1[i]);
1329 }
1330 clear_const(current,rs1[i]);
1331 clear_const(current,rt1[i]);
1332 dirty_reg(current,rt1[i]);
1333}
1334
1335void shiftimm_alloc(struct regstat *current,int i)
1336{
1337 clear_const(current,rs1[i]);
1338 clear_const(current,rt1[i]);
1339 if(opcode2[i]<=0x3) // SLL/SRL/SRA
1340 {
1341 if(rt1[i]) {
1342 if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1343 else lt1[i]=rs1[i];
1344 alloc_reg(current,i,rt1[i]);
1345 current->is32|=1LL<<rt1[i];
1346 dirty_reg(current,rt1[i]);
1347 }
1348 }
1349 if(opcode2[i]>=0x38&&opcode2[i]<=0x3b) // DSLL/DSRL/DSRA
1350 {
1351 if(rt1[i]) {
1352 if(rs1[i]) alloc_reg64(current,i,rs1[i]);
1353 alloc_reg64(current,i,rt1[i]);
1354 current->is32&=~(1LL<<rt1[i]);
1355 dirty_reg(current,rt1[i]);
1356 }
1357 }
1358 if(opcode2[i]==0x3c) // DSLL32
1359 {
1360 if(rt1[i]) {
1361 if(rs1[i]) alloc_reg(current,i,rs1[i]);
1362 alloc_reg64(current,i,rt1[i]);
1363 current->is32&=~(1LL<<rt1[i]);
1364 dirty_reg(current,rt1[i]);
1365 }
1366 }
1367 if(opcode2[i]==0x3e) // DSRL32
1368 {
1369 if(rt1[i]) {
1370 alloc_reg64(current,i,rs1[i]);
1371 if(imm[i]==32) {
1372 alloc_reg64(current,i,rt1[i]);
1373 current->is32&=~(1LL<<rt1[i]);
1374 } else {
1375 alloc_reg(current,i,rt1[i]);
1376 current->is32|=1LL<<rt1[i];
1377 }
1378 dirty_reg(current,rt1[i]);
1379 }
1380 }
1381 if(opcode2[i]==0x3f) // DSRA32
1382 {
1383 if(rt1[i]) {
1384 alloc_reg64(current,i,rs1[i]);
1385 alloc_reg(current,i,rt1[i]);
1386 current->is32|=1LL<<rt1[i];
1387 dirty_reg(current,rt1[i]);
1388 }
1389 }
1390}
1391
1392void shift_alloc(struct regstat *current,int i)
1393{
1394 if(rt1[i]) {
1395 if(opcode2[i]<=0x07) // SLLV/SRLV/SRAV
1396 {
1397 if(rs1[i]) alloc_reg(current,i,rs1[i]);
1398 if(rs2[i]) alloc_reg(current,i,rs2[i]);
1399 alloc_reg(current,i,rt1[i]);
e1190b87 1400 if(rt1[i]==rs2[i]) {
1401 alloc_reg_temp(current,i,-1);
1402 minimum_free_regs[i]=1;
1403 }
57871462 1404 current->is32|=1LL<<rt1[i];
1405 } else { // DSLLV/DSRLV/DSRAV
1406 if(rs1[i]) alloc_reg64(current,i,rs1[i]);
1407 if(rs2[i]) alloc_reg(current,i,rs2[i]);
1408 alloc_reg64(current,i,rt1[i]);
1409 current->is32&=~(1LL<<rt1[i]);
1410 if(opcode2[i]==0x16||opcode2[i]==0x17) // DSRLV and DSRAV need a temporary register
e1190b87 1411 {
57871462 1412 alloc_reg_temp(current,i,-1);
e1190b87 1413 minimum_free_regs[i]=1;
1414 }
57871462 1415 }
1416 clear_const(current,rs1[i]);
1417 clear_const(current,rs2[i]);
1418 clear_const(current,rt1[i]);
1419 dirty_reg(current,rt1[i]);
1420 }
1421}
1422
1423void alu_alloc(struct regstat *current,int i)
1424{
1425 if(opcode2[i]>=0x20&&opcode2[i]<=0x23) { // ADD/ADDU/SUB/SUBU
1426 if(rt1[i]) {
1427 if(rs1[i]&&rs2[i]) {
1428 alloc_reg(current,i,rs1[i]);
1429 alloc_reg(current,i,rs2[i]);
1430 }
1431 else {
1432 if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1433 if(rs2[i]&&needed_again(rs2[i],i)) alloc_reg(current,i,rs2[i]);
1434 }
1435 alloc_reg(current,i,rt1[i]);
1436 }
1437 current->is32|=1LL<<rt1[i];
1438 }
1439 if(opcode2[i]==0x2a||opcode2[i]==0x2b) { // SLT/SLTU
1440 if(rt1[i]) {
1441 if(!((current->is32>>rs1[i])&(current->is32>>rs2[i])&1))
1442 {
1443 alloc_reg64(current,i,rs1[i]);
1444 alloc_reg64(current,i,rs2[i]);
1445 alloc_reg(current,i,rt1[i]);
1446 } else {
1447 alloc_reg(current,i,rs1[i]);
1448 alloc_reg(current,i,rs2[i]);
1449 alloc_reg(current,i,rt1[i]);
1450 }
1451 }
1452 current->is32|=1LL<<rt1[i];
1453 }
1454 if(opcode2[i]>=0x24&&opcode2[i]<=0x27) { // AND/OR/XOR/NOR
1455 if(rt1[i]) {
1456 if(rs1[i]&&rs2[i]) {
1457 alloc_reg(current,i,rs1[i]);
1458 alloc_reg(current,i,rs2[i]);
1459 }
1460 else
1461 {
1462 if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1463 if(rs2[i]&&needed_again(rs2[i],i)) alloc_reg(current,i,rs2[i]);
1464 }
1465 alloc_reg(current,i,rt1[i]);
1466 if(!((current->is32>>rs1[i])&(current->is32>>rs2[i])&1))
1467 {
1468 if(!((current->uu>>rt1[i])&1)) {
1469 alloc_reg64(current,i,rt1[i]);
1470 }
1471 if(get_reg(current->regmap,rt1[i]|64)>=0) {
1472 if(rs1[i]&&rs2[i]) {
1473 alloc_reg64(current,i,rs1[i]);
1474 alloc_reg64(current,i,rs2[i]);
1475 }
1476 else
1477 {
1478 // Is is really worth it to keep 64-bit values in registers?
1479 #ifdef NATIVE_64BIT
1480 if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg64(current,i,rs1[i]);
1481 if(rs2[i]&&needed_again(rs2[i],i)) alloc_reg64(current,i,rs2[i]);
1482 #endif
1483 }
1484 }
1485 current->is32&=~(1LL<<rt1[i]);
1486 } else {
1487 current->is32|=1LL<<rt1[i];
1488 }
1489 }
1490 }
1491 if(opcode2[i]>=0x2c&&opcode2[i]<=0x2f) { // DADD/DADDU/DSUB/DSUBU
1492 if(rt1[i]) {
1493 if(rs1[i]&&rs2[i]) {
1494 if(!((current->uu>>rt1[i])&1)||get_reg(current->regmap,rt1[i]|64)>=0) {
1495 alloc_reg64(current,i,rs1[i]);
1496 alloc_reg64(current,i,rs2[i]);
1497 alloc_reg64(current,i,rt1[i]);
1498 } else {
1499 alloc_reg(current,i,rs1[i]);
1500 alloc_reg(current,i,rs2[i]);
1501 alloc_reg(current,i,rt1[i]);
1502 }
1503 }
1504 else {
1505 alloc_reg(current,i,rt1[i]);
1506 if(!((current->uu>>rt1[i])&1)||get_reg(current->regmap,rt1[i]|64)>=0) {
1507 // DADD used as move, or zeroing
1508 // If we have a 64-bit source, then make the target 64 bits too
1509 if(rs1[i]&&!((current->is32>>rs1[i])&1)) {
1510 if(get_reg(current->regmap,rs1[i])>=0) alloc_reg64(current,i,rs1[i]);
1511 alloc_reg64(current,i,rt1[i]);
1512 } else if(rs2[i]&&!((current->is32>>rs2[i])&1)) {
1513 if(get_reg(current->regmap,rs2[i])>=0) alloc_reg64(current,i,rs2[i]);
1514 alloc_reg64(current,i,rt1[i]);
1515 }
1516 if(opcode2[i]>=0x2e&&rs2[i]) {
1517 // DSUB used as negation - 64-bit result
1518 // If we have a 32-bit register, extend it to 64 bits
1519 if(get_reg(current->regmap,rs2[i])>=0) alloc_reg64(current,i,rs2[i]);
1520 alloc_reg64(current,i,rt1[i]);
1521 }
1522 }
1523 }
1524 if(rs1[i]&&rs2[i]) {
1525 current->is32&=~(1LL<<rt1[i]);
1526 } else if(rs1[i]) {
1527 current->is32&=~(1LL<<rt1[i]);
1528 if((current->is32>>rs1[i])&1)
1529 current->is32|=1LL<<rt1[i];
1530 } else if(rs2[i]) {
1531 current->is32&=~(1LL<<rt1[i]);
1532 if((current->is32>>rs2[i])&1)
1533 current->is32|=1LL<<rt1[i];
1534 } else {
1535 current->is32|=1LL<<rt1[i];
1536 }
1537 }
1538 }
1539 clear_const(current,rs1[i]);
1540 clear_const(current,rs2[i]);
1541 clear_const(current,rt1[i]);
1542 dirty_reg(current,rt1[i]);
1543}
1544
1545void imm16_alloc(struct regstat *current,int i)
1546{
1547 if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1548 else lt1[i]=rs1[i];
1549 if(rt1[i]) alloc_reg(current,i,rt1[i]);
1550 if(opcode[i]==0x18||opcode[i]==0x19) { // DADDI/DADDIU
1551 current->is32&=~(1LL<<rt1[i]);
1552 if(!((current->uu>>rt1[i])&1)||get_reg(current->regmap,rt1[i]|64)>=0) {
1553 // TODO: Could preserve the 32-bit flag if the immediate is zero
1554 alloc_reg64(current,i,rt1[i]);
1555 alloc_reg64(current,i,rs1[i]);
1556 }
1557 clear_const(current,rs1[i]);
1558 clear_const(current,rt1[i]);
1559 }
1560 else if(opcode[i]==0x0a||opcode[i]==0x0b) { // SLTI/SLTIU
1561 if((~current->is32>>rs1[i])&1) alloc_reg64(current,i,rs1[i]);
1562 current->is32|=1LL<<rt1[i];
1563 clear_const(current,rs1[i]);
1564 clear_const(current,rt1[i]);
1565 }
1566 else if(opcode[i]>=0x0c&&opcode[i]<=0x0e) { // ANDI/ORI/XORI
1567 if(((~current->is32>>rs1[i])&1)&&opcode[i]>0x0c) {
1568 if(rs1[i]!=rt1[i]) {
1569 if(needed_again(rs1[i],i)) alloc_reg64(current,i,rs1[i]);
1570 alloc_reg64(current,i,rt1[i]);
1571 current->is32&=~(1LL<<rt1[i]);
1572 }
1573 }
1574 else current->is32|=1LL<<rt1[i]; // ANDI clears upper bits
1575 if(is_const(current,rs1[i])) {
1576 int v=get_const(current,rs1[i]);
1577 if(opcode[i]==0x0c) set_const(current,rt1[i],v&imm[i]);
1578 if(opcode[i]==0x0d) set_const(current,rt1[i],v|imm[i]);
1579 if(opcode[i]==0x0e) set_const(current,rt1[i],v^imm[i]);
1580 }
1581 else clear_const(current,rt1[i]);
1582 }
1583 else if(opcode[i]==0x08||opcode[i]==0x09) { // ADDI/ADDIU
1584 if(is_const(current,rs1[i])) {
1585 int v=get_const(current,rs1[i]);
1586 set_const(current,rt1[i],v+imm[i]);
1587 }
1588 else clear_const(current,rt1[i]);
1589 current->is32|=1LL<<rt1[i];
1590 }
1591 else {
1592 set_const(current,rt1[i],((long long)((short)imm[i]))<<16); // LUI
1593 current->is32|=1LL<<rt1[i];
1594 }
1595 dirty_reg(current,rt1[i]);
1596}
1597
1598void load_alloc(struct regstat *current,int i)
1599{
1600 clear_const(current,rt1[i]);
1601 //if(rs1[i]!=rt1[i]&&needed_again(rs1[i],i)) clear_const(current,rs1[i]); // Does this help or hurt?
1602 if(!rs1[i]) current->u&=~1LL; // Allow allocating r0 if it's the source register
1603 if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1604 if(rt1[i]) {
1605 alloc_reg(current,i,rt1[i]);
535d208a 1606 if(get_reg(current->regmap,rt1[i])<0) {
1607 // dummy load, but we still need a register to calculate the address
1608 alloc_reg_temp(current,i,-1);
e1190b87 1609 minimum_free_regs[i]=1;
535d208a 1610 }
57871462 1611 if(opcode[i]==0x27||opcode[i]==0x37) // LWU/LD
1612 {
1613 current->is32&=~(1LL<<rt1[i]);
1614 alloc_reg64(current,i,rt1[i]);
1615 }
1616 else if(opcode[i]==0x1A||opcode[i]==0x1B) // LDL/LDR
1617 {
1618 current->is32&=~(1LL<<rt1[i]);
1619 alloc_reg64(current,i,rt1[i]);
1620 alloc_all(current,i);
1621 alloc_reg64(current,i,FTEMP);
e1190b87 1622 minimum_free_regs[i]=HOST_REGS;
57871462 1623 }
1624 else current->is32|=1LL<<rt1[i];
1625 dirty_reg(current,rt1[i]);
1626 // If using TLB, need a register for pointer to the mapping table
1627 if(using_tlb) alloc_reg(current,i,TLREG);
1628 // LWL/LWR need a temporary register for the old value
1629 if(opcode[i]==0x22||opcode[i]==0x26)
1630 {
1631 alloc_reg(current,i,FTEMP);
1632 alloc_reg_temp(current,i,-1);
e1190b87 1633 minimum_free_regs[i]=1;
57871462 1634 }
1635 }
1636 else
1637 {
1638 // Load to r0 (dummy load)
1639 // but we still need a register to calculate the address
535d208a 1640 if(opcode[i]==0x22||opcode[i]==0x26)
1641 {
1642 alloc_reg(current,i,FTEMP); // LWL/LWR need another temporary
1643 }
57871462 1644 alloc_reg_temp(current,i,-1);
e1190b87 1645 minimum_free_regs[i]=1;
535d208a 1646 if(opcode[i]==0x1A||opcode[i]==0x1B) // LDL/LDR
1647 {
1648 alloc_all(current,i);
1649 alloc_reg64(current,i,FTEMP);
e1190b87 1650 minimum_free_regs[i]=HOST_REGS;
535d208a 1651 }
57871462 1652 }
1653}
1654
1655void store_alloc(struct regstat *current,int i)
1656{
1657 clear_const(current,rs2[i]);
1658 if(!(rs2[i])) current->u&=~1LL; // Allow allocating r0 if necessary
1659 if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1660 alloc_reg(current,i,rs2[i]);
1661 if(opcode[i]==0x2c||opcode[i]==0x2d||opcode[i]==0x3f) { // 64-bit SDL/SDR/SD
1662 alloc_reg64(current,i,rs2[i]);
1663 if(rs2[i]) alloc_reg(current,i,FTEMP);
1664 }
1665 // If using TLB, need a register for pointer to the mapping table
1666 if(using_tlb) alloc_reg(current,i,TLREG);
1667 #if defined(HOST_IMM8)
1668 // On CPUs without 32-bit immediates we need a pointer to invalid_code
1669 else alloc_reg(current,i,INVCP);
1670 #endif
b7918751 1671 if(opcode[i]==0x2a||opcode[i]==0x2e||opcode[i]==0x2c||opcode[i]==0x2d) { // SWL/SWL/SDL/SDR
57871462 1672 alloc_reg(current,i,FTEMP);
1673 }
1674 // We need a temporary register for address generation
1675 alloc_reg_temp(current,i,-1);
e1190b87 1676 minimum_free_regs[i]=1;
57871462 1677}
1678
1679void c1ls_alloc(struct regstat *current,int i)
1680{
1681 //clear_const(current,rs1[i]); // FIXME
1682 clear_const(current,rt1[i]);
1683 if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1684 alloc_reg(current,i,CSREG); // Status
1685 alloc_reg(current,i,FTEMP);
1686 if(opcode[i]==0x35||opcode[i]==0x3d) { // 64-bit LDC1/SDC1
1687 alloc_reg64(current,i,FTEMP);
1688 }
1689 // If using TLB, need a register for pointer to the mapping table
1690 if(using_tlb) alloc_reg(current,i,TLREG);
1691 #if defined(HOST_IMM8)
1692 // On CPUs without 32-bit immediates we need a pointer to invalid_code
1693 else if((opcode[i]&0x3b)==0x39) // SWC1/SDC1
1694 alloc_reg(current,i,INVCP);
1695 #endif
1696 // We need a temporary register for address generation
1697 alloc_reg_temp(current,i,-1);
1698}
1699
b9b61529 1700void c2ls_alloc(struct regstat *current,int i)
1701{
1702 clear_const(current,rt1[i]);
1703 if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1704 alloc_reg(current,i,FTEMP);
1705 // If using TLB, need a register for pointer to the mapping table
1706 if(using_tlb) alloc_reg(current,i,TLREG);
1707 #if defined(HOST_IMM8)
1708 // On CPUs without 32-bit immediates we need a pointer to invalid_code
1709 else if((opcode[i]&0x3b)==0x3a) // SWC2/SDC2
1710 alloc_reg(current,i,INVCP);
1711 #endif
1712 // We need a temporary register for address generation
1713 alloc_reg_temp(current,i,-1);
e1190b87 1714 minimum_free_regs[i]=1;
b9b61529 1715}
1716
57871462 1717#ifndef multdiv_alloc
1718void multdiv_alloc(struct regstat *current,int i)
1719{
1720 // case 0x18: MULT
1721 // case 0x19: MULTU
1722 // case 0x1A: DIV
1723 // case 0x1B: DIVU
1724 // case 0x1C: DMULT
1725 // case 0x1D: DMULTU
1726 // case 0x1E: DDIV
1727 // case 0x1F: DDIVU
1728 clear_const(current,rs1[i]);
1729 clear_const(current,rs2[i]);
1730 if(rs1[i]&&rs2[i])
1731 {
1732 if((opcode2[i]&4)==0) // 32-bit
1733 {
1734 current->u&=~(1LL<<HIREG);
1735 current->u&=~(1LL<<LOREG);
1736 alloc_reg(current,i,HIREG);
1737 alloc_reg(current,i,LOREG);
1738 alloc_reg(current,i,rs1[i]);
1739 alloc_reg(current,i,rs2[i]);
1740 current->is32|=1LL<<HIREG;
1741 current->is32|=1LL<<LOREG;
1742 dirty_reg(current,HIREG);
1743 dirty_reg(current,LOREG);
1744 }
1745 else // 64-bit
1746 {
1747 current->u&=~(1LL<<HIREG);
1748 current->u&=~(1LL<<LOREG);
1749 current->uu&=~(1LL<<HIREG);
1750 current->uu&=~(1LL<<LOREG);
1751 alloc_reg64(current,i,HIREG);
1752 //if(HOST_REGS>10) alloc_reg64(current,i,LOREG);
1753 alloc_reg64(current,i,rs1[i]);
1754 alloc_reg64(current,i,rs2[i]);
1755 alloc_all(current,i);
1756 current->is32&=~(1LL<<HIREG);
1757 current->is32&=~(1LL<<LOREG);
1758 dirty_reg(current,HIREG);
1759 dirty_reg(current,LOREG);
e1190b87 1760 minimum_free_regs[i]=HOST_REGS;
57871462 1761 }
1762 }
1763 else
1764 {
1765 // Multiply by zero is zero.
1766 // MIPS does not have a divide by zero exception.
1767 // The result is undefined, we return zero.
1768 alloc_reg(current,i,HIREG);
1769 alloc_reg(current,i,LOREG);
1770 current->is32|=1LL<<HIREG;
1771 current->is32|=1LL<<LOREG;
1772 dirty_reg(current,HIREG);
1773 dirty_reg(current,LOREG);
1774 }
1775}
1776#endif
1777
1778void cop0_alloc(struct regstat *current,int i)
1779{
1780 if(opcode2[i]==0) // MFC0
1781 {
1782 if(rt1[i]) {
1783 clear_const(current,rt1[i]);
1784 alloc_all(current,i);
1785 alloc_reg(current,i,rt1[i]);
1786 current->is32|=1LL<<rt1[i];
1787 dirty_reg(current,rt1[i]);
1788 }
1789 }
1790 else if(opcode2[i]==4) // MTC0
1791 {
1792 if(rs1[i]){
1793 clear_const(current,rs1[i]);
1794 alloc_reg(current,i,rs1[i]);
1795 alloc_all(current,i);
1796 }
1797 else {
1798 alloc_all(current,i); // FIXME: Keep r0
1799 current->u&=~1LL;
1800 alloc_reg(current,i,0);
1801 }
1802 }
1803 else
1804 {
1805 // TLBR/TLBWI/TLBWR/TLBP/ERET
1806 assert(opcode2[i]==0x10);
1807 alloc_all(current,i);
1808 }
e1190b87 1809 minimum_free_regs[i]=HOST_REGS;
57871462 1810}
1811
1812void cop1_alloc(struct regstat *current,int i)
1813{
1814 alloc_reg(current,i,CSREG); // Load status
1815 if(opcode2[i]<3) // MFC1/DMFC1/CFC1
1816 {
7de557a6 1817 if(rt1[i]){
1818 clear_const(current,rt1[i]);
1819 if(opcode2[i]==1) {
1820 alloc_reg64(current,i,rt1[i]); // DMFC1
1821 current->is32&=~(1LL<<rt1[i]);
1822 }else{
1823 alloc_reg(current,i,rt1[i]); // MFC1/CFC1
1824 current->is32|=1LL<<rt1[i];
1825 }
1826 dirty_reg(current,rt1[i]);
57871462 1827 }
57871462 1828 alloc_reg_temp(current,i,-1);
1829 }
1830 else if(opcode2[i]>3) // MTC1/DMTC1/CTC1
1831 {
1832 if(rs1[i]){
1833 clear_const(current,rs1[i]);
1834 if(opcode2[i]==5)
1835 alloc_reg64(current,i,rs1[i]); // DMTC1
1836 else
1837 alloc_reg(current,i,rs1[i]); // MTC1/CTC1
1838 alloc_reg_temp(current,i,-1);
1839 }
1840 else {
1841 current->u&=~1LL;
1842 alloc_reg(current,i,0);
1843 alloc_reg_temp(current,i,-1);
1844 }
1845 }
e1190b87 1846 minimum_free_regs[i]=1;
57871462 1847}
1848void fconv_alloc(struct regstat *current,int i)
1849{
1850 alloc_reg(current,i,CSREG); // Load status
1851 alloc_reg_temp(current,i,-1);
e1190b87 1852 minimum_free_regs[i]=1;
57871462 1853}
1854void float_alloc(struct regstat *current,int i)
1855{
1856 alloc_reg(current,i,CSREG); // Load status
1857 alloc_reg_temp(current,i,-1);
e1190b87 1858 minimum_free_regs[i]=1;
57871462 1859}
b9b61529 1860void c2op_alloc(struct regstat *current,int i)
1861{
1862 alloc_reg_temp(current,i,-1);
1863}
57871462 1864void fcomp_alloc(struct regstat *current,int i)
1865{
1866 alloc_reg(current,i,CSREG); // Load status
1867 alloc_reg(current,i,FSREG); // Load flags
1868 dirty_reg(current,FSREG); // Flag will be modified
1869 alloc_reg_temp(current,i,-1);
e1190b87 1870 minimum_free_regs[i]=1;
57871462 1871}
1872
1873void syscall_alloc(struct regstat *current,int i)
1874{
1875 alloc_cc(current,i);
1876 dirty_reg(current,CCREG);
1877 alloc_all(current,i);
e1190b87 1878 minimum_free_regs[i]=HOST_REGS;
57871462 1879 current->isconst=0;
1880}
1881
1882void delayslot_alloc(struct regstat *current,int i)
1883{
1884 switch(itype[i]) {
1885 case UJUMP:
1886 case CJUMP:
1887 case SJUMP:
1888 case RJUMP:
1889 case FJUMP:
1890 case SYSCALL:
7139f3c8 1891 case HLECALL:
57871462 1892 case SPAN:
1893 assem_debug("jump in the delay slot. this shouldn't happen.\n");//exit(1);
1894 printf("Disabled speculative precompilation\n");
1895 stop_after_jal=1;
1896 break;
1897 case IMM16:
1898 imm16_alloc(current,i);
1899 break;
1900 case LOAD:
1901 case LOADLR:
1902 load_alloc(current,i);
1903 break;
1904 case STORE:
1905 case STORELR:
1906 store_alloc(current,i);
1907 break;
1908 case ALU:
1909 alu_alloc(current,i);
1910 break;
1911 case SHIFT:
1912 shift_alloc(current,i);
1913 break;
1914 case MULTDIV:
1915 multdiv_alloc(current,i);
1916 break;
1917 case SHIFTIMM:
1918 shiftimm_alloc(current,i);
1919 break;
1920 case MOV:
1921 mov_alloc(current,i);
1922 break;
1923 case COP0:
1924 cop0_alloc(current,i);
1925 break;
1926 case COP1:
b9b61529 1927 case COP2:
57871462 1928 cop1_alloc(current,i);
1929 break;
1930 case C1LS:
1931 c1ls_alloc(current,i);
1932 break;
b9b61529 1933 case C2LS:
1934 c2ls_alloc(current,i);
1935 break;
57871462 1936 case FCONV:
1937 fconv_alloc(current,i);
1938 break;
1939 case FLOAT:
1940 float_alloc(current,i);
1941 break;
1942 case FCOMP:
1943 fcomp_alloc(current,i);
1944 break;
b9b61529 1945 case C2OP:
1946 c2op_alloc(current,i);
1947 break;
57871462 1948 }
1949}
1950
1951// Special case where a branch and delay slot span two pages in virtual memory
1952static void pagespan_alloc(struct regstat *current,int i)
1953{
1954 current->isconst=0;
1955 current->wasconst=0;
1956 regs[i].wasconst=0;
e1190b87 1957 minimum_free_regs[i]=HOST_REGS;
57871462 1958 alloc_all(current,i);
1959 alloc_cc(current,i);
1960 dirty_reg(current,CCREG);
1961 if(opcode[i]==3) // JAL
1962 {
1963 alloc_reg(current,i,31);
1964 dirty_reg(current,31);
1965 }
1966 if(opcode[i]==0&&(opcode2[i]&0x3E)==8) // JR/JALR
1967 {
1968 alloc_reg(current,i,rs1[i]);
5067f341 1969 if (rt1[i]!=0) {
1970 alloc_reg(current,i,rt1[i]);
1971 dirty_reg(current,rt1[i]);
57871462 1972 }
1973 }
1974 if((opcode[i]&0x2E)==4) // BEQ/BNE/BEQL/BNEL
1975 {
1976 if(rs1[i]) alloc_reg(current,i,rs1[i]);
1977 if(rs2[i]) alloc_reg(current,i,rs2[i]);
1978 if(!((current->is32>>rs1[i])&(current->is32>>rs2[i])&1))
1979 {
1980 if(rs1[i]) alloc_reg64(current,i,rs1[i]);
1981 if(rs2[i]) alloc_reg64(current,i,rs2[i]);
1982 }
1983 }
1984 else
1985 if((opcode[i]&0x2E)==6) // BLEZ/BGTZ/BLEZL/BGTZL
1986 {
1987 if(rs1[i]) alloc_reg(current,i,rs1[i]);
1988 if(!((current->is32>>rs1[i])&1))
1989 {
1990 if(rs1[i]) alloc_reg64(current,i,rs1[i]);
1991 }
1992 }
1993 else
1994 if(opcode[i]==0x11) // BC1
1995 {
1996 alloc_reg(current,i,FSREG);
1997 alloc_reg(current,i,CSREG);
1998 }
1999 //else ...
2000}
2001
2002add_stub(int type,int addr,int retaddr,int a,int b,int c,int d,int e)
2003{
2004 stubs[stubcount][0]=type;
2005 stubs[stubcount][1]=addr;
2006 stubs[stubcount][2]=retaddr;
2007 stubs[stubcount][3]=a;
2008 stubs[stubcount][4]=b;
2009 stubs[stubcount][5]=c;
2010 stubs[stubcount][6]=d;
2011 stubs[stubcount][7]=e;
2012 stubcount++;
2013}
2014
2015// Write out a single register
2016void wb_register(signed char r,signed char regmap[],uint64_t dirty,uint64_t is32)
2017{
2018 int hr;
2019 for(hr=0;hr<HOST_REGS;hr++) {
2020 if(hr!=EXCLUDE_REG) {
2021 if((regmap[hr]&63)==r) {
2022 if((dirty>>hr)&1) {
2023 if(regmap[hr]<64) {
2024 emit_storereg(r,hr);
24385cae 2025#ifndef FORCE32
57871462 2026 if((is32>>regmap[hr])&1) {
2027 emit_sarimm(hr,31,hr);
2028 emit_storereg(r|64,hr);
2029 }
24385cae 2030#endif
57871462 2031 }else{
2032 emit_storereg(r|64,hr);
2033 }
2034 }
2035 }
2036 }
2037 }
2038}
2039
2040int mchecksum()
2041{
2042 //if(!tracedebug) return 0;
2043 int i;
2044 int sum=0;
2045 for(i=0;i<2097152;i++) {
2046 unsigned int temp=sum;
2047 sum<<=1;
2048 sum|=(~temp)>>31;
2049 sum^=((u_int *)rdram)[i];
2050 }
2051 return sum;
2052}
2053int rchecksum()
2054{
2055 int i;
2056 int sum=0;
2057 for(i=0;i<64;i++)
2058 sum^=((u_int *)reg)[i];
2059 return sum;
2060}
57871462 2061void rlist()
2062{
2063 int i;
2064 printf("TRACE: ");
2065 for(i=0;i<32;i++)
2066 printf("r%d:%8x%8x ",i,((int *)(reg+i))[1],((int *)(reg+i))[0]);
2067 printf("\n");
3d624f89 2068#ifndef DISABLE_COP1
57871462 2069 printf("TRACE: ");
2070 for(i=0;i<32;i++)
2071 printf("f%d:%8x%8x ",i,((int*)reg_cop1_simple[i])[1],*((int*)reg_cop1_simple[i]));
2072 printf("\n");
3d624f89 2073#endif
57871462 2074}
2075
2076void enabletrace()
2077{
2078 tracedebug=1;
2079}
2080
2081void memdebug(int i)
2082{
2083 //printf("TRACE: count=%d next=%d (checksum %x) lo=%8x%8x\n",Count,next_interupt,mchecksum(),(int)(reg[LOREG]>>32),(int)reg[LOREG]);
2084 //printf("TRACE: count=%d next=%d (rchecksum %x)\n",Count,next_interupt,rchecksum());
2085 //rlist();
2086 //if(tracedebug) {
2087 //if(Count>=-2084597794) {
2088 if((signed int)Count>=-2084597794&&(signed int)Count<0) {
2089 //if(0) {
2090 printf("TRACE: count=%d next=%d (checksum %x)\n",Count,next_interupt,mchecksum());
2091 //printf("TRACE: count=%d next=%d (checksum %x) Status=%x\n",Count,next_interupt,mchecksum(),Status);
2092 //printf("TRACE: count=%d next=%d (checksum %x) hi=%8x%8x\n",Count,next_interupt,mchecksum(),(int)(reg[HIREG]>>32),(int)reg[HIREG]);
2093 rlist();
2094 #ifdef __i386__
2095 printf("TRACE: %x\n",(&i)[-1]);
2096 #endif
2097 #ifdef __arm__
2098 int j;
2099 printf("TRACE: %x \n",(&j)[10]);
2100 printf("TRACE: %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x\n",(&j)[1],(&j)[2],(&j)[3],(&j)[4],(&j)[5],(&j)[6],(&j)[7],(&j)[8],(&j)[9],(&j)[10],(&j)[11],(&j)[12],(&j)[13],(&j)[14],(&j)[15],(&j)[16],(&j)[17],(&j)[18],(&j)[19],(&j)[20]);
2101 #endif
2102 //fflush(stdout);
2103 }
2104 //printf("TRACE: %x\n",(&i)[-1]);
2105}
2106
2107void tlb_debug(u_int cause, u_int addr, u_int iaddr)
2108{
2109 printf("TLB Exception: instruction=%x addr=%x cause=%x\n",iaddr, addr, cause);
2110}
2111
2112void alu_assemble(int i,struct regstat *i_regs)
2113{
2114 if(opcode2[i]>=0x20&&opcode2[i]<=0x23) { // ADD/ADDU/SUB/SUBU
2115 if(rt1[i]) {
2116 signed char s1,s2,t;
2117 t=get_reg(i_regs->regmap,rt1[i]);
2118 if(t>=0) {
2119 s1=get_reg(i_regs->regmap,rs1[i]);
2120 s2=get_reg(i_regs->regmap,rs2[i]);
2121 if(rs1[i]&&rs2[i]) {
2122 assert(s1>=0);
2123 assert(s2>=0);
2124 if(opcode2[i]&2) emit_sub(s1,s2,t);
2125 else emit_add(s1,s2,t);
2126 }
2127 else if(rs1[i]) {
2128 if(s1>=0) emit_mov(s1,t);
2129 else emit_loadreg(rs1[i],t);
2130 }
2131 else if(rs2[i]) {
2132 if(s2>=0) {
2133 if(opcode2[i]&2) emit_neg(s2,t);
2134 else emit_mov(s2,t);
2135 }
2136 else {
2137 emit_loadreg(rs2[i],t);
2138 if(opcode2[i]&2) emit_neg(t,t);
2139 }
2140 }
2141 else emit_zeroreg(t);
2142 }
2143 }
2144 }
2145 if(opcode2[i]>=0x2c&&opcode2[i]<=0x2f) { // DADD/DADDU/DSUB/DSUBU
2146 if(rt1[i]) {
2147 signed char s1l,s2l,s1h,s2h,tl,th;
2148 tl=get_reg(i_regs->regmap,rt1[i]);
2149 th=get_reg(i_regs->regmap,rt1[i]|64);
2150 if(tl>=0) {
2151 s1l=get_reg(i_regs->regmap,rs1[i]);
2152 s2l=get_reg(i_regs->regmap,rs2[i]);
2153 s1h=get_reg(i_regs->regmap,rs1[i]|64);
2154 s2h=get_reg(i_regs->regmap,rs2[i]|64);
2155 if(rs1[i]&&rs2[i]) {
2156 assert(s1l>=0);
2157 assert(s2l>=0);
2158 if(opcode2[i]&2) emit_subs(s1l,s2l,tl);
2159 else emit_adds(s1l,s2l,tl);
2160 if(th>=0) {
2161 #ifdef INVERTED_CARRY
2162 if(opcode2[i]&2) {if(s1h!=th) emit_mov(s1h,th);emit_sbb(th,s2h);}
2163 #else
2164 if(opcode2[i]&2) emit_sbc(s1h,s2h,th);
2165 #endif
2166 else emit_add(s1h,s2h,th);
2167 }
2168 }
2169 else if(rs1[i]) {
2170 if(s1l>=0) emit_mov(s1l,tl);
2171 else emit_loadreg(rs1[i],tl);
2172 if(th>=0) {
2173 if(s1h>=0) emit_mov(s1h,th);
2174 else emit_loadreg(rs1[i]|64,th);
2175 }
2176 }
2177 else if(rs2[i]) {
2178 if(s2l>=0) {
2179 if(opcode2[i]&2) emit_negs(s2l,tl);
2180 else emit_mov(s2l,tl);
2181 }
2182 else {
2183 emit_loadreg(rs2[i],tl);
2184 if(opcode2[i]&2) emit_negs(tl,tl);
2185 }
2186 if(th>=0) {
2187 #ifdef INVERTED_CARRY
2188 if(s2h>=0) emit_mov(s2h,th);
2189 else emit_loadreg(rs2[i]|64,th);
2190 if(opcode2[i]&2) {
2191 emit_adcimm(-1,th); // x86 has inverted carry flag
2192 emit_not(th,th);
2193 }
2194 #else
2195 if(opcode2[i]&2) {
2196 if(s2h>=0) emit_rscimm(s2h,0,th);
2197 else {
2198 emit_loadreg(rs2[i]|64,th);
2199 emit_rscimm(th,0,th);
2200 }
2201 }else{
2202 if(s2h>=0) emit_mov(s2h,th);
2203 else emit_loadreg(rs2[i]|64,th);
2204 }
2205 #endif
2206 }
2207 }
2208 else {
2209 emit_zeroreg(tl);
2210 if(th>=0) emit_zeroreg(th);
2211 }
2212 }
2213 }
2214 }
2215 if(opcode2[i]==0x2a||opcode2[i]==0x2b) { // SLT/SLTU
2216 if(rt1[i]) {
2217 signed char s1l,s1h,s2l,s2h,t;
2218 if(!((i_regs->was32>>rs1[i])&(i_regs->was32>>rs2[i])&1))
2219 {
2220 t=get_reg(i_regs->regmap,rt1[i]);
2221 //assert(t>=0);
2222 if(t>=0) {
2223 s1l=get_reg(i_regs->regmap,rs1[i]);
2224 s1h=get_reg(i_regs->regmap,rs1[i]|64);
2225 s2l=get_reg(i_regs->regmap,rs2[i]);
2226 s2h=get_reg(i_regs->regmap,rs2[i]|64);
2227 if(rs2[i]==0) // rx<r0
2228 {
2229 assert(s1h>=0);
2230 if(opcode2[i]==0x2a) // SLT
2231 emit_shrimm(s1h,31,t);
2232 else // SLTU (unsigned can not be less than zero)
2233 emit_zeroreg(t);
2234 }
2235 else if(rs1[i]==0) // r0<rx
2236 {
2237 assert(s2h>=0);
2238 if(opcode2[i]==0x2a) // SLT
2239 emit_set_gz64_32(s2h,s2l,t);
2240 else // SLTU (set if not zero)
2241 emit_set_nz64_32(s2h,s2l,t);
2242 }
2243 else {
2244 assert(s1l>=0);assert(s1h>=0);
2245 assert(s2l>=0);assert(s2h>=0);
2246 if(opcode2[i]==0x2a) // SLT
2247 emit_set_if_less64_32(s1h,s1l,s2h,s2l,t);
2248 else // SLTU
2249 emit_set_if_carry64_32(s1h,s1l,s2h,s2l,t);
2250 }
2251 }
2252 } else {
2253 t=get_reg(i_regs->regmap,rt1[i]);
2254 //assert(t>=0);
2255 if(t>=0) {
2256 s1l=get_reg(i_regs->regmap,rs1[i]);
2257 s2l=get_reg(i_regs->regmap,rs2[i]);
2258 if(rs2[i]==0) // rx<r0
2259 {
2260 assert(s1l>=0);
2261 if(opcode2[i]==0x2a) // SLT
2262 emit_shrimm(s1l,31,t);
2263 else // SLTU (unsigned can not be less than zero)
2264 emit_zeroreg(t);
2265 }
2266 else if(rs1[i]==0) // r0<rx
2267 {
2268 assert(s2l>=0);
2269 if(opcode2[i]==0x2a) // SLT
2270 emit_set_gz32(s2l,t);
2271 else // SLTU (set if not zero)
2272 emit_set_nz32(s2l,t);
2273 }
2274 else{
2275 assert(s1l>=0);assert(s2l>=0);
2276 if(opcode2[i]==0x2a) // SLT
2277 emit_set_if_less32(s1l,s2l,t);
2278 else // SLTU
2279 emit_set_if_carry32(s1l,s2l,t);
2280 }
2281 }
2282 }
2283 }
2284 }
2285 if(opcode2[i]>=0x24&&opcode2[i]<=0x27) { // AND/OR/XOR/NOR
2286 if(rt1[i]) {
2287 signed char s1l,s1h,s2l,s2h,th,tl;
2288 tl=get_reg(i_regs->regmap,rt1[i]);
2289 th=get_reg(i_regs->regmap,rt1[i]|64);
2290 if(!((i_regs->was32>>rs1[i])&(i_regs->was32>>rs2[i])&1)&&th>=0)
2291 {
2292 assert(tl>=0);
2293 if(tl>=0) {
2294 s1l=get_reg(i_regs->regmap,rs1[i]);
2295 s1h=get_reg(i_regs->regmap,rs1[i]|64);
2296 s2l=get_reg(i_regs->regmap,rs2[i]);
2297 s2h=get_reg(i_regs->regmap,rs2[i]|64);
2298 if(rs1[i]&&rs2[i]) {
2299 assert(s1l>=0);assert(s1h>=0);
2300 assert(s2l>=0);assert(s2h>=0);
2301 if(opcode2[i]==0x24) { // AND
2302 emit_and(s1l,s2l,tl);
2303 emit_and(s1h,s2h,th);
2304 } else
2305 if(opcode2[i]==0x25) { // OR
2306 emit_or(s1l,s2l,tl);
2307 emit_or(s1h,s2h,th);
2308 } else
2309 if(opcode2[i]==0x26) { // XOR
2310 emit_xor(s1l,s2l,tl);
2311 emit_xor(s1h,s2h,th);
2312 } else
2313 if(opcode2[i]==0x27) { // NOR
2314 emit_or(s1l,s2l,tl);
2315 emit_or(s1h,s2h,th);
2316 emit_not(tl,tl);
2317 emit_not(th,th);
2318 }
2319 }
2320 else
2321 {
2322 if(opcode2[i]==0x24) { // AND
2323 emit_zeroreg(tl);
2324 emit_zeroreg(th);
2325 } else
2326 if(opcode2[i]==0x25||opcode2[i]==0x26) { // OR/XOR
2327 if(rs1[i]){
2328 if(s1l>=0) emit_mov(s1l,tl);
2329 else emit_loadreg(rs1[i],tl);
2330 if(s1h>=0) emit_mov(s1h,th);
2331 else emit_loadreg(rs1[i]|64,th);
2332 }
2333 else
2334 if(rs2[i]){
2335 if(s2l>=0) emit_mov(s2l,tl);
2336 else emit_loadreg(rs2[i],tl);
2337 if(s2h>=0) emit_mov(s2h,th);
2338 else emit_loadreg(rs2[i]|64,th);
2339 }
2340 else{
2341 emit_zeroreg(tl);
2342 emit_zeroreg(th);
2343 }
2344 } else
2345 if(opcode2[i]==0x27) { // NOR
2346 if(rs1[i]){
2347 if(s1l>=0) emit_not(s1l,tl);
2348 else{
2349 emit_loadreg(rs1[i],tl);
2350 emit_not(tl,tl);
2351 }
2352 if(s1h>=0) emit_not(s1h,th);
2353 else{
2354 emit_loadreg(rs1[i]|64,th);
2355 emit_not(th,th);
2356 }
2357 }
2358 else
2359 if(rs2[i]){
2360 if(s2l>=0) emit_not(s2l,tl);
2361 else{
2362 emit_loadreg(rs2[i],tl);
2363 emit_not(tl,tl);
2364 }
2365 if(s2h>=0) emit_not(s2h,th);
2366 else{
2367 emit_loadreg(rs2[i]|64,th);
2368 emit_not(th,th);
2369 }
2370 }
2371 else {
2372 emit_movimm(-1,tl);
2373 emit_movimm(-1,th);
2374 }
2375 }
2376 }
2377 }
2378 }
2379 else
2380 {
2381 // 32 bit
2382 if(tl>=0) {
2383 s1l=get_reg(i_regs->regmap,rs1[i]);
2384 s2l=get_reg(i_regs->regmap,rs2[i]);
2385 if(rs1[i]&&rs2[i]) {
2386 assert(s1l>=0);
2387 assert(s2l>=0);
2388 if(opcode2[i]==0x24) { // AND
2389 emit_and(s1l,s2l,tl);
2390 } else
2391 if(opcode2[i]==0x25) { // OR
2392 emit_or(s1l,s2l,tl);
2393 } else
2394 if(opcode2[i]==0x26) { // XOR
2395 emit_xor(s1l,s2l,tl);
2396 } else
2397 if(opcode2[i]==0x27) { // NOR
2398 emit_or(s1l,s2l,tl);
2399 emit_not(tl,tl);
2400 }
2401 }
2402 else
2403 {
2404 if(opcode2[i]==0x24) { // AND
2405 emit_zeroreg(tl);
2406 } else
2407 if(opcode2[i]==0x25||opcode2[i]==0x26) { // OR/XOR
2408 if(rs1[i]){
2409 if(s1l>=0) emit_mov(s1l,tl);
2410 else emit_loadreg(rs1[i],tl); // CHECK: regmap_entry?
2411 }
2412 else
2413 if(rs2[i]){
2414 if(s2l>=0) emit_mov(s2l,tl);
2415 else emit_loadreg(rs2[i],tl); // CHECK: regmap_entry?
2416 }
2417 else emit_zeroreg(tl);
2418 } else
2419 if(opcode2[i]==0x27) { // NOR
2420 if(rs1[i]){
2421 if(s1l>=0) emit_not(s1l,tl);
2422 else {
2423 emit_loadreg(rs1[i],tl);
2424 emit_not(tl,tl);
2425 }
2426 }
2427 else
2428 if(rs2[i]){
2429 if(s2l>=0) emit_not(s2l,tl);
2430 else {
2431 emit_loadreg(rs2[i],tl);
2432 emit_not(tl,tl);
2433 }
2434 }
2435 else emit_movimm(-1,tl);
2436 }
2437 }
2438 }
2439 }
2440 }
2441 }
2442}
2443
2444void imm16_assemble(int i,struct regstat *i_regs)
2445{
2446 if (opcode[i]==0x0f) { // LUI
2447 if(rt1[i]) {
2448 signed char t;
2449 t=get_reg(i_regs->regmap,rt1[i]);
2450 //assert(t>=0);
2451 if(t>=0) {
2452 if(!((i_regs->isconst>>t)&1))
2453 emit_movimm(imm[i]<<16,t);
2454 }
2455 }
2456 }
2457 if(opcode[i]==0x08||opcode[i]==0x09) { // ADDI/ADDIU
2458 if(rt1[i]) {
2459 signed char s,t;
2460 t=get_reg(i_regs->regmap,rt1[i]);
2461 s=get_reg(i_regs->regmap,rs1[i]);
2462 if(rs1[i]) {
2463 //assert(t>=0);
2464 //assert(s>=0);
2465 if(t>=0) {
2466 if(!((i_regs->isconst>>t)&1)) {
2467 if(s<0) {
2468 if(i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2469 emit_addimm(t,imm[i],t);
2470 }else{
2471 if(!((i_regs->wasconst>>s)&1))
2472 emit_addimm(s,imm[i],t);
2473 else
2474 emit_movimm(constmap[i][s]+imm[i],t);
2475 }
2476 }
2477 }
2478 } else {
2479 if(t>=0) {
2480 if(!((i_regs->isconst>>t)&1))
2481 emit_movimm(imm[i],t);
2482 }
2483 }
2484 }
2485 }
2486 if(opcode[i]==0x18||opcode[i]==0x19) { // DADDI/DADDIU
2487 if(rt1[i]) {
2488 signed char sh,sl,th,tl;
2489 th=get_reg(i_regs->regmap,rt1[i]|64);
2490 tl=get_reg(i_regs->regmap,rt1[i]);
2491 sh=get_reg(i_regs->regmap,rs1[i]|64);
2492 sl=get_reg(i_regs->regmap,rs1[i]);
2493 if(tl>=0) {
2494 if(rs1[i]) {
2495 assert(sh>=0);
2496 assert(sl>=0);
2497 if(th>=0) {
2498 emit_addimm64_32(sh,sl,imm[i],th,tl);
2499 }
2500 else {
2501 emit_addimm(sl,imm[i],tl);
2502 }
2503 } else {
2504 emit_movimm(imm[i],tl);
2505 if(th>=0) emit_movimm(((signed int)imm[i])>>31,th);
2506 }
2507 }
2508 }
2509 }
2510 else if(opcode[i]==0x0a||opcode[i]==0x0b) { // SLTI/SLTIU
2511 if(rt1[i]) {
2512 //assert(rs1[i]!=0); // r0 might be valid, but it's probably a bug
2513 signed char sh,sl,t;
2514 t=get_reg(i_regs->regmap,rt1[i]);
2515 sh=get_reg(i_regs->regmap,rs1[i]|64);
2516 sl=get_reg(i_regs->regmap,rs1[i]);
2517 //assert(t>=0);
2518 if(t>=0) {
2519 if(rs1[i]>0) {
2520 if(sh<0) assert((i_regs->was32>>rs1[i])&1);
2521 if(sh<0||((i_regs->was32>>rs1[i])&1)) {
2522 if(opcode[i]==0x0a) { // SLTI
2523 if(sl<0) {
2524 if(i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2525 emit_slti32(t,imm[i],t);
2526 }else{
2527 emit_slti32(sl,imm[i],t);
2528 }
2529 }
2530 else { // SLTIU
2531 if(sl<0) {
2532 if(i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2533 emit_sltiu32(t,imm[i],t);
2534 }else{
2535 emit_sltiu32(sl,imm[i],t);
2536 }
2537 }
2538 }else{ // 64-bit
2539 assert(sl>=0);
2540 if(opcode[i]==0x0a) // SLTI
2541 emit_slti64_32(sh,sl,imm[i],t);
2542 else // SLTIU
2543 emit_sltiu64_32(sh,sl,imm[i],t);
2544 }
2545 }else{
2546 // SLTI(U) with r0 is just stupid,
2547 // nonetheless examples can be found
2548 if(opcode[i]==0x0a) // SLTI
2549 if(0<imm[i]) emit_movimm(1,t);
2550 else emit_zeroreg(t);
2551 else // SLTIU
2552 {
2553 if(imm[i]) emit_movimm(1,t);
2554 else emit_zeroreg(t);
2555 }
2556 }
2557 }
2558 }
2559 }
2560 else if(opcode[i]>=0x0c&&opcode[i]<=0x0e) { // ANDI/ORI/XORI
2561 if(rt1[i]) {
2562 signed char sh,sl,th,tl;
2563 th=get_reg(i_regs->regmap,rt1[i]|64);
2564 tl=get_reg(i_regs->regmap,rt1[i]);
2565 sh=get_reg(i_regs->regmap,rs1[i]|64);
2566 sl=get_reg(i_regs->regmap,rs1[i]);
2567 if(tl>=0 && !((i_regs->isconst>>tl)&1)) {
2568 if(opcode[i]==0x0c) //ANDI
2569 {
2570 if(rs1[i]) {
2571 if(sl<0) {
2572 if(i_regs->regmap_entry[tl]!=rs1[i]) emit_loadreg(rs1[i],tl);
2573 emit_andimm(tl,imm[i],tl);
2574 }else{
2575 if(!((i_regs->wasconst>>sl)&1))
2576 emit_andimm(sl,imm[i],tl);
2577 else
2578 emit_movimm(constmap[i][sl]&imm[i],tl);
2579 }
2580 }
2581 else
2582 emit_zeroreg(tl);
2583 if(th>=0) emit_zeroreg(th);
2584 }
2585 else
2586 {
2587 if(rs1[i]) {
2588 if(sl<0) {
2589 if(i_regs->regmap_entry[tl]!=rs1[i]) emit_loadreg(rs1[i],tl);
2590 }
2591 if(th>=0) {
2592 if(sh<0) {
2593 emit_loadreg(rs1[i]|64,th);
2594 }else{
2595 emit_mov(sh,th);
2596 }
2597 }
2598 if(opcode[i]==0x0d) //ORI
2599 if(sl<0) {
2600 emit_orimm(tl,imm[i],tl);
2601 }else{
2602 if(!((i_regs->wasconst>>sl)&1))
2603 emit_orimm(sl,imm[i],tl);
2604 else
2605 emit_movimm(constmap[i][sl]|imm[i],tl);
2606 }
2607 if(opcode[i]==0x0e) //XORI
2608 if(sl<0) {
2609 emit_xorimm(tl,imm[i],tl);
2610 }else{
2611 if(!((i_regs->wasconst>>sl)&1))
2612 emit_xorimm(sl,imm[i],tl);
2613 else
2614 emit_movimm(constmap[i][sl]^imm[i],tl);
2615 }
2616 }
2617 else {
2618 emit_movimm(imm[i],tl);
2619 if(th>=0) emit_zeroreg(th);
2620 }
2621 }
2622 }
2623 }
2624 }
2625}
2626
2627void shiftimm_assemble(int i,struct regstat *i_regs)
2628{
2629 if(opcode2[i]<=0x3) // SLL/SRL/SRA
2630 {
2631 if(rt1[i]) {
2632 signed char s,t;
2633 t=get_reg(i_regs->regmap,rt1[i]);
2634 s=get_reg(i_regs->regmap,rs1[i]);
2635 //assert(t>=0);
2636 if(t>=0){
2637 if(rs1[i]==0)
2638 {
2639 emit_zeroreg(t);
2640 }
2641 else
2642 {
2643 if(s<0&&i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2644 if(imm[i]) {
2645 if(opcode2[i]==0) // SLL
2646 {
2647 emit_shlimm(s<0?t:s,imm[i],t);
2648 }
2649 if(opcode2[i]==2) // SRL
2650 {
2651 emit_shrimm(s<0?t:s,imm[i],t);
2652 }
2653 if(opcode2[i]==3) // SRA
2654 {
2655 emit_sarimm(s<0?t:s,imm[i],t);
2656 }
2657 }else{
2658 // Shift by zero
2659 if(s>=0 && s!=t) emit_mov(s,t);
2660 }
2661 }
2662 }
2663 //emit_storereg(rt1[i],t); //DEBUG
2664 }
2665 }
2666 if(opcode2[i]>=0x38&&opcode2[i]<=0x3b) // DSLL/DSRL/DSRA
2667 {
2668 if(rt1[i]) {
2669 signed char sh,sl,th,tl;
2670 th=get_reg(i_regs->regmap,rt1[i]|64);
2671 tl=get_reg(i_regs->regmap,rt1[i]);
2672 sh=get_reg(i_regs->regmap,rs1[i]|64);
2673 sl=get_reg(i_regs->regmap,rs1[i]);
2674 if(tl>=0) {
2675 if(rs1[i]==0)
2676 {
2677 emit_zeroreg(tl);
2678 if(th>=0) emit_zeroreg(th);
2679 }
2680 else
2681 {
2682 assert(sl>=0);
2683 assert(sh>=0);
2684 if(imm[i]) {
2685 if(opcode2[i]==0x38) // DSLL
2686 {
2687 if(th>=0) emit_shldimm(sh,sl,imm[i],th);
2688 emit_shlimm(sl,imm[i],tl);
2689 }
2690 if(opcode2[i]==0x3a) // DSRL
2691 {
2692 emit_shrdimm(sl,sh,imm[i],tl);
2693 if(th>=0) emit_shrimm(sh,imm[i],th);
2694 }
2695 if(opcode2[i]==0x3b) // DSRA
2696 {
2697 emit_shrdimm(sl,sh,imm[i],tl);
2698 if(th>=0) emit_sarimm(sh,imm[i],th);
2699 }
2700 }else{
2701 // Shift by zero
2702 if(sl!=tl) emit_mov(sl,tl);
2703 if(th>=0&&sh!=th) emit_mov(sh,th);
2704 }
2705 }
2706 }
2707 }
2708 }
2709 if(opcode2[i]==0x3c) // DSLL32
2710 {
2711 if(rt1[i]) {
2712 signed char sl,tl,th;
2713 tl=get_reg(i_regs->regmap,rt1[i]);
2714 th=get_reg(i_regs->regmap,rt1[i]|64);
2715 sl=get_reg(i_regs->regmap,rs1[i]);
2716 if(th>=0||tl>=0){
2717 assert(tl>=0);
2718 assert(th>=0);
2719 assert(sl>=0);
2720 emit_mov(sl,th);
2721 emit_zeroreg(tl);
2722 if(imm[i]>32)
2723 {
2724 emit_shlimm(th,imm[i]&31,th);
2725 }
2726 }
2727 }
2728 }
2729 if(opcode2[i]==0x3e) // DSRL32
2730 {
2731 if(rt1[i]) {
2732 signed char sh,tl,th;
2733 tl=get_reg(i_regs->regmap,rt1[i]);
2734 th=get_reg(i_regs->regmap,rt1[i]|64);
2735 sh=get_reg(i_regs->regmap,rs1[i]|64);
2736 if(tl>=0){
2737 assert(sh>=0);
2738 emit_mov(sh,tl);
2739 if(th>=0) emit_zeroreg(th);
2740 if(imm[i]>32)
2741 {
2742 emit_shrimm(tl,imm[i]&31,tl);
2743 }
2744 }
2745 }
2746 }
2747 if(opcode2[i]==0x3f) // DSRA32
2748 {
2749 if(rt1[i]) {
2750 signed char sh,tl;
2751 tl=get_reg(i_regs->regmap,rt1[i]);
2752 sh=get_reg(i_regs->regmap,rs1[i]|64);
2753 if(tl>=0){
2754 assert(sh>=0);
2755 emit_mov(sh,tl);
2756 if(imm[i]>32)
2757 {
2758 emit_sarimm(tl,imm[i]&31,tl);
2759 }
2760 }
2761 }
2762 }
2763}
2764
2765#ifndef shift_assemble
2766void shift_assemble(int i,struct regstat *i_regs)
2767{
2768 printf("Need shift_assemble for this architecture.\n");
2769 exit(1);
2770}
2771#endif
2772
2773void load_assemble(int i,struct regstat *i_regs)
2774{
2775 int s,th,tl,addr,map=-1;
2776 int offset;
2777 int jaddr=0;
5bf843dc 2778 int memtarget=0,c=0;
57871462 2779 u_int hr,reglist=0;
2780 th=get_reg(i_regs->regmap,rt1[i]|64);
2781 tl=get_reg(i_regs->regmap,rt1[i]);
2782 s=get_reg(i_regs->regmap,rs1[i]);
2783 offset=imm[i];
2784 for(hr=0;hr<HOST_REGS;hr++) {
2785 if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
2786 }
2787 if(i_regs->regmap[HOST_CCREG]==CCREG) reglist&=~(1<<HOST_CCREG);
2788 if(s>=0) {
2789 c=(i_regs->wasconst>>s)&1;
af4ee1fe 2790 if (c) {
2791 memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
2792 if(using_tlb&&((signed int)(constmap[i][s]+offset))>=(signed int)0xC0000000) memtarget=1;
2793 }
57871462 2794 }
57871462 2795 //printf("load_assemble: c=%d\n",c);
2796 //if(c) printf("load_assemble: const=%x\n",(int)constmap[i][s]+offset);
2797 // FIXME: Even if the load is a NOP, we should check for pagefaults...
5bf843dc 2798#ifdef PCSX
f18c0f46 2799 if(tl<0&&(!c||(((u_int)constmap[i][s]+offset)>>16)==0x1f80)
2800 ||rt1[i]==0) {
5bf843dc 2801 // could be FIFO, must perform the read
f18c0f46 2802 // ||dummy read
5bf843dc 2803 assem_debug("(forced read)\n");
2804 tl=get_reg(i_regs->regmap,-1);
2805 assert(tl>=0);
5bf843dc 2806 }
f18c0f46 2807#endif
5bf843dc 2808 if(offset||s<0||c) addr=tl;
2809 else addr=s;
535d208a 2810 //if(tl<0) tl=get_reg(i_regs->regmap,-1);
2811 if(tl>=0) {
2812 //printf("load_assemble: c=%d\n",c);
2813 //if(c) printf("load_assemble: const=%x\n",(int)constmap[i][s]+offset);
2814 assert(tl>=0); // Even if the load is a NOP, we must check for pagefaults and I/O
2815 reglist&=~(1<<tl);
2816 if(th>=0) reglist&=~(1<<th);
2817 if(!using_tlb) {
2818 if(!c) {
2819 #ifdef RAM_OFFSET
2820 map=get_reg(i_regs->regmap,ROREG);
2821 if(map<0) emit_loadreg(ROREG,map=HOST_TEMPREG);
2822 #endif
57871462 2823//#define R29_HACK 1
535d208a 2824 #ifdef R29_HACK
2825 // Strmnnrmn's speed hack
2826 if(rs1[i]!=29||start<0x80001000||start>=0x80000000+RAM_SIZE)
2827 #endif
2828 {
2829 emit_cmpimm(addr,RAM_SIZE);
2830 jaddr=(int)out;
2831 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
2832 // Hint to branch predictor that the branch is unlikely to be taken
2833 if(rs1[i]>=28)
2834 emit_jno_unlikely(0);
2835 else
57871462 2836 #endif
535d208a 2837 emit_jno(0);
57871462 2838 }
535d208a 2839 }
2840 }else{ // using tlb
2841 int x=0;
2842 if (opcode[i]==0x20||opcode[i]==0x24) x=3; // LB/LBU
2843 if (opcode[i]==0x21||opcode[i]==0x25) x=2; // LH/LHU
2844 map=get_reg(i_regs->regmap,TLREG);
2845 assert(map>=0);
2846 map=do_tlb_r(addr,tl,map,x,-1,-1,c,constmap[i][s]+offset);
2847 do_tlb_r_branch(map,c,constmap[i][s]+offset,&jaddr);
2848 }
2849 int dummy=(rt1[i]==0)||(tl!=get_reg(i_regs->regmap,rt1[i])); // ignore loads to r0 and unneeded reg
2850 if (opcode[i]==0x20) { // LB
2851 if(!c||memtarget) {
2852 if(!dummy) {
57871462 2853 #ifdef HOST_IMM_ADDR32
2854 if(c)
2855 emit_movsbl_tlb((constmap[i][s]+offset)^3,map,tl);
2856 else
2857 #endif
2858 {
2859 //emit_xorimm(addr,3,tl);
2860 //gen_tlb_addr_r(tl,map);
2861 //emit_movsbl_indexed((int)rdram-0x80000000,tl,tl);
535d208a 2862 int x=0,a=tl;
2002a1db 2863#ifdef BIG_ENDIAN_MIPS
57871462 2864 if(!c) emit_xorimm(addr,3,tl);
2865 else x=((constmap[i][s]+offset)^3)-(constmap[i][s]+offset);
2002a1db 2866#else
535d208a 2867 if(!c) a=addr;
2002a1db 2868#endif
535d208a 2869 emit_movsbl_indexed_tlb(x,a,map,tl);
57871462 2870 }
57871462 2871 }
535d208a 2872 if(jaddr)
2873 add_stub(LOADB_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
57871462 2874 }
535d208a 2875 else
2876 inline_readstub(LOADB_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2877 }
2878 if (opcode[i]==0x21) { // LH
2879 if(!c||memtarget) {
2880 if(!dummy) {
57871462 2881 #ifdef HOST_IMM_ADDR32
2882 if(c)
2883 emit_movswl_tlb((constmap[i][s]+offset)^2,map,tl);
2884 else
2885 #endif
2886 {
535d208a 2887 int x=0,a=tl;
2002a1db 2888#ifdef BIG_ENDIAN_MIPS
57871462 2889 if(!c) emit_xorimm(addr,2,tl);
2890 else x=((constmap[i][s]+offset)^2)-(constmap[i][s]+offset);
2002a1db 2891#else
535d208a 2892 if(!c) a=addr;
2002a1db 2893#endif
57871462 2894 //#ifdef
2895 //emit_movswl_indexed_tlb(x,tl,map,tl);
2896 //else
2897 if(map>=0) {
535d208a 2898 gen_tlb_addr_r(a,map);
2899 emit_movswl_indexed(x,a,tl);
2900 }else{
2901 #ifdef RAM_OFFSET
2902 emit_movswl_indexed(x,a,tl);
2903 #else
2904 emit_movswl_indexed((int)rdram-0x80000000+x,a,tl);
2905 #endif
2906 }
57871462 2907 }
57871462 2908 }
535d208a 2909 if(jaddr)
2910 add_stub(LOADH_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
57871462 2911 }
535d208a 2912 else
2913 inline_readstub(LOADH_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2914 }
2915 if (opcode[i]==0x23) { // LW
2916 if(!c||memtarget) {
2917 if(!dummy) {
57871462 2918 //emit_readword_indexed((int)rdram-0x80000000,addr,tl);
2919 #ifdef HOST_IMM_ADDR32
2920 if(c)
2921 emit_readword_tlb(constmap[i][s]+offset,map,tl);
2922 else
2923 #endif
2924 emit_readword_indexed_tlb(0,addr,map,tl);
57871462 2925 }
535d208a 2926 if(jaddr)
2927 add_stub(LOADW_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
57871462 2928 }
535d208a 2929 else
2930 inline_readstub(LOADW_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2931 }
2932 if (opcode[i]==0x24) { // LBU
2933 if(!c||memtarget) {
2934 if(!dummy) {
57871462 2935 #ifdef HOST_IMM_ADDR32
2936 if(c)
2937 emit_movzbl_tlb((constmap[i][s]+offset)^3,map,tl);
2938 else
2939 #endif
2940 {
2941 //emit_xorimm(addr,3,tl);
2942 //gen_tlb_addr_r(tl,map);
2943 //emit_movzbl_indexed((int)rdram-0x80000000,tl,tl);
535d208a 2944 int x=0,a=tl;
2002a1db 2945#ifdef BIG_ENDIAN_MIPS
57871462 2946 if(!c) emit_xorimm(addr,3,tl);
2947 else x=((constmap[i][s]+offset)^3)-(constmap[i][s]+offset);
2002a1db 2948#else
535d208a 2949 if(!c) a=addr;
2002a1db 2950#endif
535d208a 2951 emit_movzbl_indexed_tlb(x,a,map,tl);
57871462 2952 }
57871462 2953 }
535d208a 2954 if(jaddr)
2955 add_stub(LOADBU_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
57871462 2956 }
535d208a 2957 else
2958 inline_readstub(LOADBU_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2959 }
2960 if (opcode[i]==0x25) { // LHU
2961 if(!c||memtarget) {
2962 if(!dummy) {
57871462 2963 #ifdef HOST_IMM_ADDR32
2964 if(c)
2965 emit_movzwl_tlb((constmap[i][s]+offset)^2,map,tl);
2966 else
2967 #endif
2968 {
535d208a 2969 int x=0,a=tl;
2002a1db 2970#ifdef BIG_ENDIAN_MIPS
57871462 2971 if(!c) emit_xorimm(addr,2,tl);
2972 else x=((constmap[i][s]+offset)^2)-(constmap[i][s]+offset);
2002a1db 2973#else
535d208a 2974 if(!c) a=addr;
2002a1db 2975#endif
57871462 2976 //#ifdef
2977 //emit_movzwl_indexed_tlb(x,tl,map,tl);
2978 //#else
2979 if(map>=0) {
535d208a 2980 gen_tlb_addr_r(a,map);
2981 emit_movzwl_indexed(x,a,tl);
2982 }else{
2983 #ifdef RAM_OFFSET
2984 emit_movzwl_indexed(x,a,tl);
2985 #else
2986 emit_movzwl_indexed((int)rdram-0x80000000+x,a,tl);
2987 #endif
2988 }
57871462 2989 }
2990 }
535d208a 2991 if(jaddr)
2992 add_stub(LOADHU_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
57871462 2993 }
535d208a 2994 else
2995 inline_readstub(LOADHU_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2996 }
2997 if (opcode[i]==0x27) { // LWU
2998 assert(th>=0);
2999 if(!c||memtarget) {
3000 if(!dummy) {
57871462 3001 //emit_readword_indexed((int)rdram-0x80000000,addr,tl);
3002 #ifdef HOST_IMM_ADDR32
3003 if(c)
3004 emit_readword_tlb(constmap[i][s]+offset,map,tl);
3005 else
3006 #endif
3007 emit_readword_indexed_tlb(0,addr,map,tl);
57871462 3008 }
535d208a 3009 if(jaddr)
3010 add_stub(LOADW_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
3011 }
3012 else {
3013 inline_readstub(LOADW_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
57871462 3014 }
535d208a 3015 emit_zeroreg(th);
3016 }
3017 if (opcode[i]==0x37) { // LD
3018 if(!c||memtarget) {
3019 if(!dummy) {
57871462 3020 //gen_tlb_addr_r(tl,map);
3021 //if(th>=0) emit_readword_indexed((int)rdram-0x80000000,addr,th);
3022 //emit_readword_indexed((int)rdram-0x7FFFFFFC,addr,tl);
3023 #ifdef HOST_IMM_ADDR32
3024 if(c)
3025 emit_readdword_tlb(constmap[i][s]+offset,map,th,tl);
3026 else
3027 #endif
3028 emit_readdword_indexed_tlb(0,addr,map,th,tl);
57871462 3029 }
535d208a 3030 if(jaddr)
3031 add_stub(LOADD_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
57871462 3032 }
535d208a 3033 else
3034 inline_readstub(LOADD_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
57871462 3035 }
535d208a 3036 }
3037 //emit_storereg(rt1[i],tl); // DEBUG
57871462 3038 //if(opcode[i]==0x23)
3039 //if(opcode[i]==0x24)
3040 //if(opcode[i]==0x23||opcode[i]==0x24)
3041 /*if(opcode[i]==0x21||opcode[i]==0x23||opcode[i]==0x24)
3042 {
3043 //emit_pusha();
3044 save_regs(0x100f);
3045 emit_readword((int)&last_count,ECX);
3046 #ifdef __i386__
3047 if(get_reg(i_regs->regmap,CCREG)<0)
3048 emit_loadreg(CCREG,HOST_CCREG);
3049 emit_add(HOST_CCREG,ECX,HOST_CCREG);
3050 emit_addimm(HOST_CCREG,2*ccadj[i],HOST_CCREG);
3051 emit_writeword(HOST_CCREG,(int)&Count);
3052 #endif
3053 #ifdef __arm__
3054 if(get_reg(i_regs->regmap,CCREG)<0)
3055 emit_loadreg(CCREG,0);
3056 else
3057 emit_mov(HOST_CCREG,0);
3058 emit_add(0,ECX,0);
3059 emit_addimm(0,2*ccadj[i],0);
3060 emit_writeword(0,(int)&Count);
3061 #endif
3062 emit_call((int)memdebug);
3063 //emit_popa();
3064 restore_regs(0x100f);
3065 }/**/
3066}
3067
3068#ifndef loadlr_assemble
3069void loadlr_assemble(int i,struct regstat *i_regs)
3070{
3071 printf("Need loadlr_assemble for this architecture.\n");
3072 exit(1);
3073}
3074#endif
3075
3076void store_assemble(int i,struct regstat *i_regs)
3077{
3078 int s,th,tl,map=-1;
3079 int addr,temp;
3080 int offset;
3081 int jaddr=0,jaddr2,type;
666a299d 3082 int memtarget=0,c=0;
57871462 3083 int agr=AGEN1+(i&1);
3084 u_int hr,reglist=0;
3085 th=get_reg(i_regs->regmap,rs2[i]|64);
3086 tl=get_reg(i_regs->regmap,rs2[i]);
3087 s=get_reg(i_regs->regmap,rs1[i]);
3088 temp=get_reg(i_regs->regmap,agr);
3089 if(temp<0) temp=get_reg(i_regs->regmap,-1);
3090 offset=imm[i];
3091 if(s>=0) {
3092 c=(i_regs->wasconst>>s)&1;
af4ee1fe 3093 if(c) {
3094 memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
3095 if(using_tlb&&((signed int)(constmap[i][s]+offset))>=(signed int)0xC0000000) memtarget=1;
3096 }
57871462 3097 }
3098 assert(tl>=0);
3099 assert(temp>=0);
3100 for(hr=0;hr<HOST_REGS;hr++) {
3101 if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
3102 }
3103 if(i_regs->regmap[HOST_CCREG]==CCREG) reglist&=~(1<<HOST_CCREG);
3104 if(offset||s<0||c) addr=temp;
3105 else addr=s;
3106 if(!using_tlb) {
3107 if(!c) {
3108 #ifdef R29_HACK
3109 // Strmnnrmn's speed hack
3110 memtarget=1;
4cb76aa4 3111 if(rs1[i]!=29||start<0x80001000||start>=0x80000000+RAM_SIZE)
57871462 3112 #endif
4cb76aa4 3113 emit_cmpimm(addr,RAM_SIZE);
57871462 3114 #ifdef DESTRUCTIVE_SHIFT
3115 if(s==addr) emit_mov(s,temp);
3116 #endif
3117 #ifdef R29_HACK
4cb76aa4 3118 if(rs1[i]!=29||start<0x80001000||start>=0x80000000+RAM_SIZE)
57871462 3119 #endif
3120 {
3121 jaddr=(int)out;
3122 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
3123 // Hint to branch predictor that the branch is unlikely to be taken
3124 if(rs1[i]>=28)
3125 emit_jno_unlikely(0);
3126 else
3127 #endif
3128 emit_jno(0);
3129 }
3130 }
3131 }else{ // using tlb
3132 int x=0;
3133 if (opcode[i]==0x28) x=3; // SB
3134 if (opcode[i]==0x29) x=2; // SH
3135 map=get_reg(i_regs->regmap,TLREG);
3136 assert(map>=0);
3137 map=do_tlb_w(addr,temp,map,x,c,constmap[i][s]+offset);
3138 do_tlb_w_branch(map,c,constmap[i][s]+offset,&jaddr);
3139 }
3140
3141 if (opcode[i]==0x28) { // SB
3142 if(!c||memtarget) {
97a238a6 3143 int x=0,a=temp;
2002a1db 3144#ifdef BIG_ENDIAN_MIPS
57871462 3145 if(!c) emit_xorimm(addr,3,temp);
3146 else x=((constmap[i][s]+offset)^3)-(constmap[i][s]+offset);
2002a1db 3147#else
97a238a6 3148 if(!c) a=addr;
2002a1db 3149#endif
57871462 3150 //gen_tlb_addr_w(temp,map);
3151 //emit_writebyte_indexed(tl,(int)rdram-0x80000000,temp);
97a238a6 3152 emit_writebyte_indexed_tlb(tl,x,a,map,a);
57871462 3153 }
3154 type=STOREB_STUB;
3155 }
3156 if (opcode[i]==0x29) { // SH
3157 if(!c||memtarget) {
97a238a6 3158 int x=0,a=temp;
2002a1db 3159#ifdef BIG_ENDIAN_MIPS
57871462 3160 if(!c) emit_xorimm(addr,2,temp);
3161 else x=((constmap[i][s]+offset)^2)-(constmap[i][s]+offset);
2002a1db 3162#else
97a238a6 3163 if(!c) a=addr;
2002a1db 3164#endif
57871462 3165 //#ifdef
3166 //emit_writehword_indexed_tlb(tl,x,temp,map,temp);
3167 //#else
3168 if(map>=0) {
97a238a6 3169 gen_tlb_addr_w(a,map);
3170 emit_writehword_indexed(tl,x,a);
57871462 3171 }else
97a238a6 3172 emit_writehword_indexed(tl,(int)rdram-0x80000000+x,a);
57871462 3173 }
3174 type=STOREH_STUB;
3175 }
3176 if (opcode[i]==0x2B) { // SW
3177 if(!c||memtarget)
3178 //emit_writeword_indexed(tl,(int)rdram-0x80000000,addr);
3179 emit_writeword_indexed_tlb(tl,0,addr,map,temp);
3180 type=STOREW_STUB;
3181 }
3182 if (opcode[i]==0x3F) { // SD
3183 if(!c||memtarget) {
3184 if(rs2[i]) {
3185 assert(th>=0);
3186 //emit_writeword_indexed(th,(int)rdram-0x80000000,addr);
3187 //emit_writeword_indexed(tl,(int)rdram-0x7FFFFFFC,addr);
3188 emit_writedword_indexed_tlb(th,tl,0,addr,map,temp);
3189 }else{
3190 // Store zero
3191 //emit_writeword_indexed(tl,(int)rdram-0x80000000,temp);
3192 //emit_writeword_indexed(tl,(int)rdram-0x7FFFFFFC,temp);
3193 emit_writedword_indexed_tlb(tl,tl,0,addr,map,temp);
3194 }
3195 }
3196 type=STORED_STUB;
3197 }
57871462 3198 if(!using_tlb) {
3199 if(!c||memtarget) {
3200 #ifdef DESTRUCTIVE_SHIFT
3201 // The x86 shift operation is 'destructive'; it overwrites the
3202 // source register, so we need to make a copy first and use that.
3203 addr=temp;
3204 #endif
3205 #if defined(HOST_IMM8)
3206 int ir=get_reg(i_regs->regmap,INVCP);
3207 assert(ir>=0);
3208 emit_cmpmem_indexedsr12_reg(ir,addr,1);
3209 #else
3210 emit_cmpmem_indexedsr12_imm((int)invalid_code,addr,1);
3211 #endif
0bbd1454 3212 #if defined(HAVE_CONDITIONAL_CALL) && !defined(DESTRUCTIVE_SHIFT)
3213 emit_callne(invalidate_addr_reg[addr]);
3214 #else
57871462 3215 jaddr2=(int)out;
3216 emit_jne(0);
3217 add_stub(INVCODE_STUB,jaddr2,(int)out,reglist|(1<<HOST_CCREG),addr,0,0,0);
0bbd1454 3218 #endif
57871462 3219 }
3220 }
3eaa7048 3221 if(jaddr) {
3222 add_stub(type,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
3223 } else if(c&&!memtarget) {
3224 inline_writestub(type,i,constmap[i][s]+offset,i_regs->regmap,rs2[i],ccadj[i],reglist);
3225 }
57871462 3226 //if(opcode[i]==0x2B || opcode[i]==0x3F)
3227 //if(opcode[i]==0x2B || opcode[i]==0x28)
3228 //if(opcode[i]==0x2B || opcode[i]==0x29)
3229 //if(opcode[i]==0x2B)
3230 /*if(opcode[i]==0x2B || opcode[i]==0x28 || opcode[i]==0x29 || opcode[i]==0x3F)
3231 {
3232 //emit_pusha();
3233 save_regs(0x100f);
3234 emit_readword((int)&last_count,ECX);
3235 #ifdef __i386__
3236 if(get_reg(i_regs->regmap,CCREG)<0)
3237 emit_loadreg(CCREG,HOST_CCREG);
3238 emit_add(HOST_CCREG,ECX,HOST_CCREG);
3239 emit_addimm(HOST_CCREG,2*ccadj[i],HOST_CCREG);
3240 emit_writeword(HOST_CCREG,(int)&Count);
3241 #endif
3242 #ifdef __arm__
3243 if(get_reg(i_regs->regmap,CCREG)<0)
3244 emit_loadreg(CCREG,0);
3245 else
3246 emit_mov(HOST_CCREG,0);
3247 emit_add(0,ECX,0);
3248 emit_addimm(0,2*ccadj[i],0);
3249 emit_writeword(0,(int)&Count);
3250 #endif
3251 emit_call((int)memdebug);
3252 //emit_popa();
3253 restore_regs(0x100f);
3254 }/**/
3255}
3256
3257void storelr_assemble(int i,struct regstat *i_regs)
3258{
3259 int s,th,tl;
3260 int temp;
3261 int temp2;
3262 int offset;
3263 int jaddr=0,jaddr2;
3264 int case1,case2,case3;
3265 int done0,done1,done2;
af4ee1fe 3266 int memtarget=0,c=0;
fab5d06d 3267 int agr=AGEN1+(i&1);
57871462 3268 u_int hr,reglist=0;
3269 th=get_reg(i_regs->regmap,rs2[i]|64);
3270 tl=get_reg(i_regs->regmap,rs2[i]);
3271 s=get_reg(i_regs->regmap,rs1[i]);
fab5d06d 3272 temp=get_reg(i_regs->regmap,agr);
3273 if(temp<0) temp=get_reg(i_regs->regmap,-1);
57871462 3274 offset=imm[i];
3275 if(s>=0) {
3276 c=(i_regs->isconst>>s)&1;
af4ee1fe 3277 if(c) {
3278 memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
3279 if(using_tlb&&((signed int)(constmap[i][s]+offset))>=(signed int)0xC0000000) memtarget=1;
3280 }
57871462 3281 }
3282 assert(tl>=0);
3283 for(hr=0;hr<HOST_REGS;hr++) {
3284 if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
3285 }
535d208a 3286 assert(temp>=0);
3287 if(!using_tlb) {
3288 if(!c) {
3289 emit_cmpimm(s<0||offset?temp:s,RAM_SIZE);
3290 if(!offset&&s!=temp) emit_mov(s,temp);
3291 jaddr=(int)out;
3292 emit_jno(0);
3293 }
3294 else
3295 {
3296 if(!memtarget||!rs1[i]) {
57871462 3297 jaddr=(int)out;
3298 emit_jmp(0);
3299 }
57871462 3300 }
535d208a 3301 #ifdef RAM_OFFSET
3302 int map=get_reg(i_regs->regmap,ROREG);
3303 if(map<0) emit_loadreg(ROREG,map=HOST_TEMPREG);
3304 gen_tlb_addr_w(temp,map);
3305 #else
3306 if((u_int)rdram!=0x80000000)
3307 emit_addimm_no_flags((u_int)rdram-(u_int)0x80000000,temp);
3308 #endif
3309 }else{ // using tlb
3310 int map=get_reg(i_regs->regmap,TLREG);
3311 assert(map>=0);
3312 map=do_tlb_w(c||s<0||offset?temp:s,temp,map,0,c,constmap[i][s]+offset);
3313 if(!c&&!offset&&s>=0) emit_mov(s,temp);
3314 do_tlb_w_branch(map,c,constmap[i][s]+offset,&jaddr);
3315 if(!jaddr&&!memtarget) {
3316 jaddr=(int)out;
3317 emit_jmp(0);
57871462 3318 }
535d208a 3319 gen_tlb_addr_w(temp,map);
3320 }
3321
3322 if (opcode[i]==0x2C||opcode[i]==0x2D) { // SDL/SDR
3323 temp2=get_reg(i_regs->regmap,FTEMP);
3324 if(!rs2[i]) temp2=th=tl;
3325 }
57871462 3326
2002a1db 3327#ifndef BIG_ENDIAN_MIPS
3328 emit_xorimm(temp,3,temp);
3329#endif
535d208a 3330 emit_testimm(temp,2);
3331 case2=(int)out;
3332 emit_jne(0);
3333 emit_testimm(temp,1);
3334 case1=(int)out;
3335 emit_jne(0);