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improved irq handling Cz80_Exec() calls with lots of cycles
[picodrive.git] / Pico / PicoInt.h
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eff55556 1// Pico Library - Internal Header File\r
cc68a136 2\r
3// (c) Copyright 2004 Dave, All rights reserved.\r
6cadc2da 4// (c) Copyright 2006,2007 Grazvydas "notaz" Ignotas, all rights reserved.\r
cc68a136 5// Free for non-commercial use.\r
6\r
7// For commercial use, separate licencing terms must be obtained.\r
8\r
eff55556 9#ifndef PICO_INTERNAL_INCLUDED\r
10#define PICO_INTERNAL_INCLUDED\r
cc68a136 11\r
12#include <stdio.h>\r
13#include <stdlib.h>\r
14#include <string.h>\r
15#include "Pico.h"\r
f53f286a 16#include "carthw/carthw.h"\r
cc68a136 17\r
89fa852d 18//\r
19#define USE_POLL_DETECT\r
20\r
eff55556 21#ifndef PICO_INTERNAL\r
22#define PICO_INTERNAL\r
23#endif\r
24#ifndef PICO_INTERNAL_ASM\r
25#define PICO_INTERNAL_ASM\r
26#endif\r
cc68a136 27\r
70357ce5 28// to select core, define EMU_C68K, EMU_M68K or EMU_F68K in your makefile or project\r
cc68a136 29\r
30#ifdef __cplusplus\r
31extern "C" {\r
32#endif\r
33\r
34\r
35// ----------------------- 68000 CPU -----------------------\r
36#ifdef EMU_C68K\r
37#include "../cpu/Cyclone/Cyclone.h"\r
3aa1e148 38extern struct Cyclone PicoCpuCM68k, PicoCpuCS68k;\r
39#define SekCyclesLeftNoMCD PicoCpuCM68k.cycles // cycles left for this run\r
7336a99a 40#define SekCyclesLeft \\r
602133e1 41 (((PicoAHW&1) && (PicoOpt & POPT_EN_MCD_PSYNC)) ? (SekCycleAim-SekCycleCnt) : SekCyclesLeftNoMCD)\r
7a1f6e45 42#define SekCyclesLeftS68k \\r
602133e1 43 ((PicoOpt & POPT_EN_MCD_PSYNC) ? (SekCycleAimS68k-SekCycleCntS68k) : PicoCpuCS68k.cycles)\r
3aa1e148 44#define SekSetCyclesLeftNoMCD(c) PicoCpuCM68k.cycles=c\r
7336a99a 45#define SekSetCyclesLeft(c) { \\r
602133e1 46 if ((PicoAHW&1) && (PicoOpt & POPT_EN_MCD_PSYNC)) SekCycleCnt=SekCycleAim-(c); else SekSetCyclesLeftNoMCD(c); \\r
7336a99a 47}\r
3aa1e148 48#define SekPc (PicoCpuCM68k.pc-PicoCpuCM68k.membase)\r
49#define SekPcS68k (PicoCpuCS68k.pc-PicoCpuCS68k.membase)\r
50#define SekSetStop(x) { PicoCpuCM68k.state_flags&=~1; if (x) { PicoCpuCM68k.state_flags|=1; PicoCpuCM68k.cycles=0; } }\r
51#define SekSetStopS68k(x) { PicoCpuCS68k.state_flags&=~1; if (x) { PicoCpuCS68k.state_flags|=1; PicoCpuCS68k.cycles=0; } }\r
ca61ee42 52#define SekIsStoppedS68k() (PicoCpuCS68k.state_flags&1)\r
03e4f2a3 53#define SekShouldInterrupt (PicoCpuCM68k.irq > (PicoCpuCM68k.srh&7))\r
b542be46 54\r
55#define SekInterrupt(i) PicoCpuCM68k.irq=i\r
56\r
03e4f2a3 57#ifdef EMU_M68K\r
58#define EMU_CORE_DEBUG\r
59#endif\r
cc68a136 60#endif\r
61\r
70357ce5 62#ifdef EMU_F68K\r
63#include "../cpu/fame/fame.h"\r
b542be46 64extern M68K_CONTEXT PicoCpuFM68k, PicoCpuFS68k;\r
3aa1e148 65#define SekCyclesLeftNoMCD PicoCpuFM68k.io_cycle_counter\r
70357ce5 66#define SekCyclesLeft \\r
602133e1 67 (((PicoAHW&1) && (PicoOpt & POPT_EN_MCD_PSYNC)) ? (SekCycleAim-SekCycleCnt) : SekCyclesLeftNoMCD)\r
70357ce5 68#define SekCyclesLeftS68k \\r
602133e1 69 ((PicoOpt & POPT_EN_MCD_PSYNC) ? (SekCycleAimS68k-SekCycleCntS68k) : PicoCpuFS68k.io_cycle_counter)\r
3aa1e148 70#define SekSetCyclesLeftNoMCD(c) PicoCpuFM68k.io_cycle_counter=c\r
70357ce5 71#define SekSetCyclesLeft(c) { \\r
602133e1 72 if ((PicoAHW&1) && (PicoOpt & POPT_EN_MCD_PSYNC)) SekCycleCnt=SekCycleAim-(c); else SekSetCyclesLeftNoMCD(c); \\r
70357ce5 73}\r
03e4f2a3 74#define SekPc fm68k_get_pc(&PicoCpuFM68k)\r
75#define SekPcS68k fm68k_get_pc(&PicoCpuFS68k)\r
70357ce5 76#define SekSetStop(x) { \\r
03e4f2a3 77 PicoCpuFM68k.execinfo &= ~FM68K_HALTED; \\r
78 if (x) { PicoCpuFM68k.execinfo |= FM68K_HALTED; PicoCpuFM68k.io_cycle_counter = 0; } \\r
70357ce5 79}\r
80#define SekSetStopS68k(x) { \\r
03e4f2a3 81 PicoCpuFS68k.execinfo &= ~FM68K_HALTED; \\r
82 if (x) { PicoCpuFS68k.execinfo |= FM68K_HALTED; PicoCpuFS68k.io_cycle_counter = 0; } \\r
70357ce5 83}\r
ca61ee42 84#define SekIsStoppedS68k() (PicoCpuFS68k.execinfo&FM68K_HALTED)\r
03e4f2a3 85#define SekShouldInterrupt fm68k_would_interrupt()\r
b542be46 86\r
87#define SekInterrupt(irq) PicoCpuFM68k.interrupts[0]=irq\r
88\r
03e4f2a3 89#ifdef EMU_M68K\r
90#define EMU_CORE_DEBUG\r
91#endif\r
cc68a136 92#endif\r
93\r
94#ifdef EMU_M68K\r
95#include "../cpu/musashi/m68kcpu.h"\r
3aa1e148 96extern m68ki_cpu_core PicoCpuMM68k, PicoCpuMS68k;\r
cc68a136 97#ifndef SekCyclesLeft\r
3aa1e148 98#define SekCyclesLeftNoMCD PicoCpuMM68k.cyc_remaining_cycles\r
7336a99a 99#define SekCyclesLeft \\r
602133e1 100 (((PicoAHW&1) && (PicoOpt & POPT_EN_MCD_PSYNC)) ? (SekCycleAim-SekCycleCnt) : SekCyclesLeftNoMCD)\r
7a1f6e45 101#define SekCyclesLeftS68k \\r
602133e1 102 ((PicoOpt & POPT_EN_MCD_PSYNC) ? (SekCycleAimS68k-SekCycleCntS68k) : PicoCpuMS68k.cyc_remaining_cycles)\r
7336a99a 103#define SekSetCyclesLeftNoMCD(c) SET_CYCLES(c)\r
104#define SekSetCyclesLeft(c) { \\r
602133e1 105 if ((PicoAHW&1) && (PicoOpt & POPT_EN_MCD_PSYNC)) SekCycleCnt=SekCycleAim-(c); else SET_CYCLES(c); \\r
7336a99a 106}\r
3aa1e148 107#define SekPc m68k_get_reg(&PicoCpuMM68k, M68K_REG_PC)\r
108#define SekPcS68k m68k_get_reg(&PicoCpuMS68k, M68K_REG_PC)\r
7a1f6e45 109#define SekSetStop(x) { \\r
3aa1e148 110 if(x) { SET_CYCLES(0); PicoCpuMM68k.stopped=STOP_LEVEL_STOP; } \\r
111 else PicoCpuMM68k.stopped=0; \\r
7a1f6e45 112}\r
113#define SekSetStopS68k(x) { \\r
3aa1e148 114 if(x) { SET_CYCLES(0); PicoCpuMS68k.stopped=STOP_LEVEL_STOP; } \\r
115 else PicoCpuMS68k.stopped=0; \\r
7a1f6e45 116}\r
ca61ee42 117#define SekIsStoppedS68k() (PicoCpuMS68k.stopped==STOP_LEVEL_STOP)\r
03e4f2a3 118#define SekShouldInterrupt (CPU_INT_LEVEL > FLAG_INT_MASK)\r
b542be46 119\r
71de3cd9 120#define SekInterrupt(irq) { \\r
b542be46 121 void *oldcontext = m68ki_cpu_p; \\r
122 m68k_set_context(&PicoCpuMM68k); \\r
123 m68k_set_irq(irq); \\r
124 m68k_set_context(oldcontext); \\r
125}\r
126\r
cc68a136 127#endif\r
128#endif\r
129\r
130extern int SekCycleCnt; // cycles done in this frame\r
131extern int SekCycleAim; // cycle aim\r
132extern unsigned int SekCycleCntT; // total cycle counter, updated once per frame\r
133\r
b8cbd802 134#define SekCyclesReset() { \\r
135 SekCycleCntT+=SekCycleAim; \\r
136 SekCycleCnt-=SekCycleAim; \\r
137 SekCycleAim=0; \\r
138}\r
cc68a136 139#define SekCyclesBurn(c) SekCycleCnt+=c\r
140#define SekCyclesDone() (SekCycleAim-SekCyclesLeft) // nuber of cycles done in this frame (can be checked anywhere)\r
141#define SekCyclesDoneT() (SekCycleCntT+SekCyclesDone()) // total nuber of cycles done for this rom\r
142\r
143#define SekEndRun(after) { \\r
144 SekCycleCnt -= SekCyclesLeft - after; \\r
145 if(SekCycleCnt < 0) SekCycleCnt = 0; \\r
146 SekSetCyclesLeft(after); \\r
147}\r
148\r
149extern int SekCycleCntS68k;\r
150extern int SekCycleAimS68k;\r
151\r
bf5fbbb4 152#define SekCyclesResetS68k() { \\r
153 SekCycleCntS68k-=SekCycleAimS68k; \\r
154 SekCycleAimS68k=0; \\r
155}\r
7a1f6e45 156#define SekCyclesDoneS68k() (SekCycleAimS68k-SekCyclesLeftS68k)\r
cc68a136 157\r
03e4f2a3 158#ifdef EMU_CORE_DEBUG\r
99464b62 159extern int dbg_irq_level;\r
2d0b15bb 160#undef SekSetCyclesLeftNoMCD\r
161#undef SekSetCyclesLeft\r
162#undef SekCyclesBurn\r
163#undef SekEndRun\r
99464b62 164#undef SekInterrupt\r
2d0b15bb 165#define SekSetCyclesLeftNoMCD(c)\r
166#define SekSetCyclesLeft(c)\r
2270612a 167#define SekCyclesBurn(c) c\r
2d0b15bb 168#define SekEndRun(c)\r
99464b62 169#define SekInterrupt(irq) dbg_irq_level=irq\r
2d0b15bb 170#endif\r
cc68a136 171\r
b542be46 172// ----------------------- Z80 CPU -----------------------\r
173\r
174#if defined(_USE_MZ80)\r
dca310c4 175#include "../cpu/mz80/mz80.h"\r
b542be46 176\r
177#define z80_run(cycles) mz80_run(cycles)\r
178#define z80_run_nr(cycles) mz80_run(cycles)\r
179#define z80_int() mz80int(0)\r
180#define z80_resetCycles() mz80GetElapsedTicks(1)\r
181\r
182#elif defined(_USE_DRZ80)\r
dca310c4 183#include "../cpu/DrZ80/drz80.h"\r
b542be46 184\r
185extern struct DrZ80 drZ80;\r
186\r
187#define z80_run(cycles) ((cycles) - DrZ80Run(&drZ80, cycles))\r
188#define z80_run_nr(cycles) DrZ80Run(&drZ80, cycles)\r
189#define z80_int() { \\r
190 drZ80.z80irqvector = 0xFF; /* default IRQ vector RST opcode */ \\r
191 drZ80.Z80_IRQ = 1; \\r
192}\r
193#define z80_resetCycles()\r
194\r
195#elif defined(_USE_CZ80)\r
dca310c4 196#include "../cpu/cz80/cz80.h"\r
b542be46 197\r
198#define z80_run(cycles) Cz80_Exec(&CZ80, cycles)\r
199#define z80_run_nr(cycles) Cz80_Exec(&CZ80, cycles)\r
200#define z80_int() Cz80_Set_IRQ(&CZ80, 0, HOLD_LINE)\r
201#define z80_resetCycles()\r
202\r
203#else\r
204\r
205#define z80_run(cycles) (cycles)\r
206#define z80_run_nr(cycles)\r
207#define z80_int()\r
208#define z80_resetCycles()\r
209\r
210#endif\r
211\r
cc68a136 212// ---------------------------------------------------------\r
213\r
214// main oscillator clock which controls timing\r
215#define OSC_NTSC 53693100\r
b8cbd802 216// seems to be accurate, see scans from http://www.hot.ee/tmeeco/\r
217#define OSC_PAL 53203424\r
cc68a136 218\r
219struct PicoVideo\r
220{\r
221 unsigned char reg[0x20];\r
b8cbd802 222 unsigned int command; // 32-bit Command\r
223 unsigned char pending; // 1 if waiting for second half of 32-bit command\r
224 unsigned char type; // Command type (v/c/vsram read/write)\r
225 unsigned short addr; // Read/Write address\r
226 int status; // Status bits\r
cc68a136 227 unsigned char pending_ints; // pending interrupts: ??VH????\r
b8cbd802 228 signed char lwrite_cnt; // VDP write count during active display line\r
229 unsigned char pad[0x12];\r
cc68a136 230};\r
231\r
232struct PicoMisc\r
233{\r
234 unsigned char rotate;\r
235 unsigned char z80Run;\r
e5503e2f 236 unsigned char padTHPhase[2]; // 02 phase of gamepad TH switches\r
237 short scanline; // 04 0 to 261||311; -1 in fast mode\r
238 char dirtyPal; // 06 Is the palette dirty (1 - change @ this frame, 2 - some time before)\r
239 unsigned char hardware; // 07 Hardware value for country\r
240 unsigned char pal; // 08 1=PAL 0=NTSC\r
241 unsigned char sram_reg; // SRAM mode register. bit0: allow read? bit1: deny write? bit2: EEPROM? bit4: detected? (header or by access)\r
242 unsigned short z80_bank68k; // 0a\r
cc68a136 243 unsigned short z80_lastaddr; // this is for Z80 faking\r
244 unsigned char z80_fakeval;\r
bd613473 245 unsigned char z80_reset; // z80 reset held\r
e5503e2f 246 unsigned char padDelay[2]; // 10 gamepad phase time outs, so we count a delay\r
1dceadae 247 unsigned short eeprom_addr; // EEPROM address register\r
248 unsigned char eeprom_cycle; // EEPROM SRAM cycle number\r
249 unsigned char eeprom_slave; // EEPROM slave word for X24C02 and better SRAMs\r
721cd396 250 unsigned char prot_bytes[2]; // simple protection faking\r
b8cbd802 251 unsigned short dma_xfers;\r
312e9ce1 252 unsigned char pad[2];\r
253 unsigned int frame_count; // mainly for movies\r
cc68a136 254};\r
255\r
256// some assembly stuff depend on these, do not touch!\r
257struct Pico\r
258{\r
259 unsigned char ram[0x10000]; // 0x00000 scratch ram\r
260 unsigned short vram[0x8000]; // 0x10000\r
261 unsigned char zram[0x2000]; // 0x20000 Z80 ram\r
262 unsigned char ioports[0x10];\r
263 unsigned int pad[0x3c]; // unused\r
264 unsigned short cram[0x40]; // 0x22100\r
265 unsigned short vsram[0x40]; // 0x22180\r
266\r
267 unsigned char *rom; // 0x22200\r
268 unsigned int romsize; // 0x22204\r
269\r
270 struct PicoMisc m;\r
271 struct PicoVideo video;\r
272};\r
273\r
274// sram\r
275struct PicoSRAM\r
276{\r
4ff2d527 277 unsigned char *data; // actual data\r
278 unsigned int start; // start address in 68k address space\r
cc68a136 279 unsigned int end;\r
1dceadae 280 unsigned char unused1; // 0c: unused\r
281 unsigned char unused2;\r
cc68a136 282 unsigned char changed;\r
1dceadae 283 unsigned char eeprom_type; // eeprom type: 0: 7bit (24C01), 2: device with 2 addr words (X24C02+), 3: dev with 3 addr words\r
284 unsigned char eeprom_abits; // eeprom access must be odd addr for: bit0 ~ cl, bit1 ~ out\r
285 unsigned char eeprom_bit_cl; // bit number for cl\r
286 unsigned char eeprom_bit_in; // bit number for in\r
287 unsigned char eeprom_bit_out; // bit number for out\r
cc68a136 288};\r
289\r
290// MCD\r
291#include "cd/cd_sys.h"\r
292#include "cd/LC89510.h"\r
d1df8786 293#include "cd/gfx_cd.h"\r
cc68a136 294\r
4f265db7 295struct mcd_pcm\r
296{\r
297 unsigned char control; // reg7\r
298 unsigned char enabled; // reg8\r
299 unsigned char cur_ch;\r
300 unsigned char bank;\r
301 int pad1;\r
302\r
4ff2d527 303 struct pcm_chan // 08, size 0x10\r
4f265db7 304 {\r
305 unsigned char regs[8];\r
4ff2d527 306 unsigned int addr; // .08: played sample address\r
4f265db7 307 int pad;\r
308 } ch[8];\r
309};\r
310\r
c459aefd 311struct mcd_misc\r
312{\r
313 unsigned short hint_vector;\r
314 unsigned char busreq;\r
51a902ae 315 unsigned char s68k_pend_ints;\r
89fa852d 316 unsigned int state_flags; // 04: emu state: reset_pending, dmna_pending\r
51a902ae 317 unsigned int counter75hz;\r
c9e1affc 318 unsigned int pad0;\r
4ff2d527 319 int timer_int3; // 10\r
4f265db7 320 unsigned int timer_stopwatch;\r
6cadc2da 321 unsigned char bcram_reg; // 18: battery-backed RAM cart register\r
322 unsigned char pad2;\r
323 unsigned short pad3;\r
324 int pad[9];\r
c459aefd 325};\r
326\r
cc68a136 327typedef struct\r
328{\r
4ff2d527 329 unsigned char bios[0x20000]; // 000000: 128K\r
330 union { // 020000: 512K\r
fa1e5e29 331 unsigned char prg_ram[0x80000];\r
cc68a136 332 unsigned char prg_ram_b[4][0x20000];\r
333 };\r
4ff2d527 334 union { // 0a0000: 256K\r
fa1e5e29 335 struct {\r
336 unsigned char word_ram2M[0x40000];\r
dca310c4 337 unsigned char unused0[0x20000];\r
fa1e5e29 338 };\r
339 struct {\r
dca310c4 340 unsigned char unused1[0x20000];\r
fa1e5e29 341 unsigned char word_ram1M[2][0x20000];\r
342 };\r
343 };\r
4ff2d527 344 union { // 100000: 64K\r
fa1e5e29 345 unsigned char pcm_ram[0x10000];\r
4f265db7 346 unsigned char pcm_ram_b[0x10][0x1000];\r
347 };\r
4ff2d527 348 unsigned char s68k_regs[0x200]; // 110000: GA, not CPU regs\r
349 unsigned char bram[0x2000]; // 110200: 8K\r
350 struct mcd_misc m; // 112200: misc\r
351 struct mcd_pcm pcm; // 112240:\r
75736070 352 _scd_toc TOC; // not to be saved\r
cc68a136 353 CDD cdd;\r
354 CDC cdc;\r
355 _scd scd;\r
d1df8786 356 Rot_Comp rot_comp;\r
cc68a136 357} mcd_state;\r
358\r
359#define Pico_mcd ((mcd_state *)Pico.rom)\r
360\r
d49b10c2 361\r
51a902ae 362// Area.c\r
eff55556 363PICO_INTERNAL int PicoAreaPackCpu(unsigned char *cpu, int is_sub);\r
364PICO_INTERNAL int PicoAreaUnpackCpu(unsigned char *cpu, int is_sub);\r
fad24893 365extern void (*PicoLoadStateHook)(void);\r
51a902ae 366\r
367// cd/Area.c\r
eff55556 368PICO_INTERNAL int PicoCdSaveState(void *file);\r
369PICO_INTERNAL int PicoCdLoadState(void *file);\r
cc68a136 370\r
945c2fdc 371typedef struct {\r
372 int chunk;\r
373 int size;\r
374 void *ptr;\r
375} carthw_state_chunk;\r
376extern carthw_state_chunk *carthw_chunks;\r
377#define CHUNK_CARTHW 64\r
378\r
1dceadae 379// Cart.c\r
e807ac75 380extern void (*PicoCartUnloadHook)(void);\r
1dceadae 381\r
03e4f2a3 382// Debug.c\r
b5e5172d 383int CM_compareRun(int cyc, int is_sub);\r
03e4f2a3 384\r
cc68a136 385// Draw.c\r
eff55556 386PICO_INTERNAL int PicoLine(int scan);\r
387PICO_INTERNAL void PicoFrameStart(void);\r
cc68a136 388\r
389// Draw2.c\r
eff55556 390PICO_INTERNAL void PicoFrameFull();\r
cc68a136 391\r
392// Memory.c\r
eff55556 393PICO_INTERNAL int PicoInitPc(unsigned int pc);\r
406c96c5 394PICO_INTERNAL unsigned int PicoCheckPc(unsigned int pc);\r
8ab3e3c1 395PICO_INTERNAL_ASM unsigned int PicoRead32(unsigned int a);\r
eff55556 396PICO_INTERNAL void PicoMemSetup(void);\r
397PICO_INTERNAL_ASM void PicoMemReset(void);\r
f8ef8ff7 398PICO_INTERNAL void PicoMemResetHooks(void);\r
e5503e2f 399PICO_INTERNAL int PadRead(int i);\r
eff55556 400PICO_INTERNAL unsigned char z80_read(unsigned short a);\r
a4221917 401#ifndef _USE_CZ80\r
eff55556 402PICO_INTERNAL_ASM void z80_write(unsigned char data, unsigned short a);\r
403PICO_INTERNAL void z80_write16(unsigned short data, unsigned short a);\r
a4221917 404PICO_INTERNAL unsigned short z80_read16(unsigned short a);\r
405#else\r
406PICO_INTERNAL_ASM void z80_write(unsigned int a, unsigned char data);\r
407#endif\r
f53f286a 408extern unsigned int (*PicoRead16Hook)(unsigned int a, int realsize);\r
f8ef8ff7 409extern void (*PicoWrite8Hook) (unsigned int a,unsigned int d,int realsize);\r
410extern void (*PicoWrite16Hook)(unsigned int a,unsigned int d,int realsize);\r
cc68a136 411\r
412// cd/Memory.c\r
eff55556 413PICO_INTERNAL void PicoMemSetupCD(void);\r
414PICO_INTERNAL_ASM void PicoMemResetCD(int r3);\r
415PICO_INTERNAL_ASM void PicoMemResetCDdecode(int r3);\r
cc68a136 416\r
9037e45d 417// Pico/Memory.c\r
418PICO_INTERNAL void PicoMemSetupPico(void);\r
419\r
cc68a136 420// Pico.c\r
421extern struct Pico Pico;\r
422extern struct PicoSRAM SRam;\r
423extern int emustatus;\r
d9153729 424extern int z80startCycle, z80stopCycle; // in 68k cycles\r
f8ef8ff7 425extern void (*PicoResetHook)(void);\r
0ffefdb8 426extern void (*PicoLineHook)(int count);\r
1e6b5e39 427PICO_INTERNAL int CheckDMA(void);\r
428PICO_INTERNAL void PicoDetectRegion(void);\r
cc68a136 429\r
430// cd/Pico.c\r
e5f426aa 431PICO_INTERNAL int PicoInitMCD(void);\r
432PICO_INTERNAL void PicoExitMCD(void);\r
1cb1584b 433PICO_INTERNAL void PicoPowerMCD(void);\r
434PICO_INTERNAL int PicoResetMCD(void);\r
eff55556 435PICO_INTERNAL int PicoFrameMCD(void);\r
cc68a136 436\r
9037e45d 437// Pico/Pico.c\r
438PICO_INTERNAL int PicoInitPico(void);\r
ed367a3f 439PICO_INTERNAL void PicoReratePico(void);\r
9037e45d 440\r
ef4eb506 441// Pico/xpcm.c\r
442PICO_INTERNAL void PicoPicoPCMUpdate(short *buffer, int length, int stereo);\r
443PICO_INTERNAL void PicoPicoPCMReset(void);\r
213c16ad 444PICO_INTERNAL void PicoPicoPCMRerate(int xpcm_rate);\r
ef4eb506 445\r
cc68a136 446// Sek.c\r
eff55556 447PICO_INTERNAL int SekInit(void);\r
448PICO_INTERNAL int SekReset(void);\r
3aa1e148 449PICO_INTERNAL void SekState(int *data);\r
eff55556 450PICO_INTERNAL void SekSetRealTAS(int use_real);\r
cc68a136 451\r
452// cd/Sek.c\r
eff55556 453PICO_INTERNAL int SekInitS68k(void);\r
454PICO_INTERNAL int SekResetS68k(void);\r
455PICO_INTERNAL int SekInterruptS68k(int irq);\r
cc68a136 456\r
7a93adeb 457// sound/sound.c\r
c9e1affc 458PICO_INTERNAL void cdda_start_play();\r
459extern short cdda_out_buffer[2*1152];\r
7a93adeb 460extern int PsndLen_exc_cnt;\r
461extern int PsndLen_exc_add;\r
462\r
cc68a136 463// VideoPort.c\r
eff55556 464PICO_INTERNAL_ASM void PicoVideoWrite(unsigned int a,unsigned short d);\r
465PICO_INTERNAL_ASM unsigned int PicoVideoRead(unsigned int a);\r
5de27868 466extern int (*PicoDmaHook)(unsigned int source, int len, unsigned short **srcp, unsigned short **limitp);\r
cc68a136 467\r
468// Misc.c\r
eff55556 469PICO_INTERNAL void SRAMWriteEEPROM(unsigned int d);\r
470PICO_INTERNAL void SRAMUpdPending(unsigned int a, unsigned int d);\r
471PICO_INTERNAL_ASM unsigned int SRAMReadEEPROM(void);\r
472PICO_INTERNAL_ASM void memcpy16(unsigned short *dest, unsigned short *src, int count);\r
473PICO_INTERNAL_ASM void memcpy16bswap(unsigned short *dest, void *src, int count);\r
474PICO_INTERNAL_ASM void memcpy32(int *dest, int *src, int count); // 32bit word count\r
475PICO_INTERNAL_ASM void memset32(int *dest, int c, int count);\r
cc68a136 476\r
fa1e5e29 477// cd/Misc.c\r
eff55556 478PICO_INTERNAL_ASM void wram_2M_to_1M(unsigned char *m);\r
479PICO_INTERNAL_ASM void wram_1M_to_2M(unsigned char *m);\r
480\r
481// cd/buffering.c\r
482PICO_INTERNAL void PicoCDBufferRead(void *dest, int lba);\r
483\r
484// sound/sound.c\r
9d917eea 485PICO_INTERNAL void PsndReset(void);\r
486PICO_INTERNAL void Psnd_timers_and_dac(int raster);\r
487PICO_INTERNAL int PsndRender(int offset, int length);\r
488PICO_INTERNAL void PsndClear(void);\r
eff55556 489// z80 functionality wrappers\r
490PICO_INTERNAL void z80_init(void);\r
eff55556 491PICO_INTERNAL void z80_pack(unsigned char *data);\r
492PICO_INTERNAL void z80_unpack(unsigned char *data);\r
493PICO_INTERNAL void z80_reset(void);\r
494PICO_INTERNAL void z80_exit(void);\r
fa1e5e29 495\r
cc68a136 496\r
497#ifdef __cplusplus\r
498} // End of extern "C"\r
499#endif\r
eff55556 500\r
b8cbd802 501// emulation event logging\r
502#ifndef EL_LOGMASK\r
503#define EL_LOGMASK 0\r
504#endif\r
505\r
017512f2 506#define EL_HVCNT 0x00000001 /* hv counter reads */\r
507#define EL_SR 0x00000002 /* SR reads */\r
508#define EL_INTS 0x00000004 /* ints and acks */\r
509#define EL_YM2612R 0x00000008 /* 68k ym2612 reads */\r
510#define EL_INTSW 0x00000010 /* log irq switching on/off */\r
511#define EL_ASVDP 0x00000020 /* VDP accesses during active scan */\r
512#define EL_VDPDMA 0x00000040 /* VDP DMA transfers and their timing */\r
513#define EL_BUSREQ 0x00000080 /* z80 busreq r/w or reset w */\r
514#define EL_Z80BNK 0x00000100 /* z80 i/o through bank area */\r
515#define EL_SRAMIO 0x00000200 /* sram i/o */\r
516#define EL_EEPROM 0x00000400 /* eeprom debug */\r
517#define EL_UIO 0x00000800 /* unmapped i/o */\r
518#define EL_IO 0x00001000 /* all i/o */\r
519#define EL_CDPOLL 0x00002000 /* MCD: log poll detection */\r
520#define EL_SVP 0x00004000 /* SVP stuff */\r
fa22af4c 521#define EL_PICOHW 0x00008000 /* Pico stuff */\r
017512f2 522\r
523#define EL_STATUS 0x40000000 /* status messages */\r
524#define EL_ANOMALY 0x80000000 /* some unexpected conditions (during emulation) */\r
b8cbd802 525\r
526#if EL_LOGMASK\r
7d0143a2 527extern void lprintf(const char *fmt, ...);\r
b8cbd802 528#define elprintf(w,f,...) \\r
529{ \\r
530 if ((w) & EL_LOGMASK) \\r
7d0143a2 531 lprintf("%05i:%03i: " f "\n",Pico.m.frame_count,Pico.m.scanline,##__VA_ARGS__); \\r
b8cbd802 532}\r
dca310c4 533#elif defined(_MSC_VER)\r
534#define elprintf\r
b8cbd802 535#else\r
536#define elprintf(w,f,...)\r
537#endif\r
538\r
dca310c4 539#ifdef _MSC_VER\r
540#define cdprintf\r
541#else\r
542#define cdprintf(x...)\r
543#endif\r
544\r
eff55556 545#endif // PICO_INTERNAL_INCLUDED\r
546\r
fast MegaDrive/MegaCD/32X emulator