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drc: merge Ari64's patch: 17_branch_target_liveness_analysis
[pcsx_rearmed.git] / libpcsxcore / new_dynarec / new_dynarec.c
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57871462 1/* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
2 * Mupen64plus - new_dynarec.c *
20d507ba 3 * Copyright (C) 2009-2011 Ari64 *
57871462 4 * *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
9 * *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
14 * *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. *
19 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */
20
21#include <stdlib.h>
22#include <stdint.h> //include for uint64_t
23#include <assert.h>
24
3d624f89 25#include "emu_if.h" //emulator interface
57871462 26
27#include <sys/mman.h>
28
29#ifdef __i386__
30#include "assem_x86.h"
31#endif
32#ifdef __x86_64__
33#include "assem_x64.h"
34#endif
35#ifdef __arm__
36#include "assem_arm.h"
37#endif
38
39#define MAXBLOCK 4096
40#define MAX_OUTPUT_BLOCK_SIZE 262144
41#define CLOCK_DIVIDER 2
42
43struct regstat
44{
45 signed char regmap_entry[HOST_REGS];
46 signed char regmap[HOST_REGS];
47 uint64_t was32;
48 uint64_t is32;
49 uint64_t wasdirty;
50 uint64_t dirty;
51 uint64_t u;
52 uint64_t uu;
53 u_int wasconst;
54 u_int isconst;
55 uint64_t constmap[HOST_REGS];
56};
57
58struct ll_entry
59{
60 u_int vaddr;
61 u_int reg32;
62 void *addr;
63 struct ll_entry *next;
64};
65
66 u_int start;
67 u_int *source;
68 u_int pagelimit;
69 char insn[MAXBLOCK][10];
70 u_char itype[MAXBLOCK];
71 u_char opcode[MAXBLOCK];
72 u_char opcode2[MAXBLOCK];
73 u_char bt[MAXBLOCK];
74 u_char rs1[MAXBLOCK];
75 u_char rs2[MAXBLOCK];
76 u_char rt1[MAXBLOCK];
77 u_char rt2[MAXBLOCK];
78 u_char us1[MAXBLOCK];
79 u_char us2[MAXBLOCK];
80 u_char dep1[MAXBLOCK];
81 u_char dep2[MAXBLOCK];
82 u_char lt1[MAXBLOCK];
83 int imm[MAXBLOCK];
84 u_int ba[MAXBLOCK];
85 char likely[MAXBLOCK];
86 char is_ds[MAXBLOCK];
e1190b87 87 char ooo[MAXBLOCK];
57871462 88 uint64_t unneeded_reg[MAXBLOCK];
89 uint64_t unneeded_reg_upper[MAXBLOCK];
90 uint64_t branch_unneeded_reg[MAXBLOCK];
91 uint64_t branch_unneeded_reg_upper[MAXBLOCK];
92 uint64_t p32[MAXBLOCK];
93 uint64_t pr32[MAXBLOCK];
94 signed char regmap_pre[MAXBLOCK][HOST_REGS];
95 signed char regmap[MAXBLOCK][HOST_REGS];
96 signed char regmap_entry[MAXBLOCK][HOST_REGS];
97 uint64_t constmap[MAXBLOCK][HOST_REGS];
57871462 98 struct regstat regs[MAXBLOCK];
99 struct regstat branch_regs[MAXBLOCK];
e1190b87 100 signed char minimum_free_regs[MAXBLOCK];
57871462 101 u_int needed_reg[MAXBLOCK];
102 uint64_t requires_32bit[MAXBLOCK];
103 u_int wont_dirty[MAXBLOCK];
104 u_int will_dirty[MAXBLOCK];
105 int ccadj[MAXBLOCK];
106 int slen;
107 u_int instr_addr[MAXBLOCK];
108 u_int link_addr[MAXBLOCK][3];
109 int linkcount;
110 u_int stubs[MAXBLOCK*3][8];
111 int stubcount;
112 u_int literals[1024][2];
113 int literalcount;
114 int is_delayslot;
115 int cop1_usable;
116 u_char *out;
117 struct ll_entry *jump_in[4096];
118 struct ll_entry *jump_out[4096];
119 struct ll_entry *jump_dirty[4096];
120 u_int hash_table[65536][4] __attribute__((aligned(16)));
121 char shadow[1048576] __attribute__((aligned(16)));
122 void *copy;
123 int expirep;
af4ee1fe 124#ifndef PCSX
57871462 125 u_int using_tlb;
af4ee1fe 126#else
127 static const u_int using_tlb=0;
128#endif
dadf55f2 129 static u_int sp_in_mirror;
57871462 130 u_int stop_after_jal;
131 extern u_char restore_candidate[512];
132 extern int cycle_count;
133
134 /* registers that may be allocated */
135 /* 1-31 gpr */
136#define HIREG 32 // hi
137#define LOREG 33 // lo
138#define FSREG 34 // FPU status (FCSR)
139#define CSREG 35 // Coprocessor status
140#define CCREG 36 // Cycle count
141#define INVCP 37 // Pointer to invalid_code
619e5ded 142#define MMREG 38 // Pointer to memory_map
143#define ROREG 39 // ram offset (if rdram!=0x80000000)
144#define TEMPREG 40
145#define FTEMP 40 // FPU temporary register
146#define PTEMP 41 // Prefetch temporary register
147#define TLREG 42 // TLB mapping offset
148#define RHASH 43 // Return address hash
149#define RHTBL 44 // Return address hash table address
150#define RTEMP 45 // JR/JALR address register
151#define MAXREG 45
152#define AGEN1 46 // Address generation temporary register
153#define AGEN2 47 // Address generation temporary register
154#define MGEN1 48 // Maptable address generation temporary register
155#define MGEN2 49 // Maptable address generation temporary register
156#define BTREG 50 // Branch target temporary register
57871462 157
158 /* instruction types */
159#define NOP 0 // No operation
160#define LOAD 1 // Load
161#define STORE 2 // Store
162#define LOADLR 3 // Unaligned load
163#define STORELR 4 // Unaligned store
164#define MOV 5 // Move
165#define ALU 6 // Arithmetic/logic
166#define MULTDIV 7 // Multiply/divide
167#define SHIFT 8 // Shift by register
168#define SHIFTIMM 9// Shift by immediate
169#define IMM16 10 // 16-bit immediate
170#define RJUMP 11 // Unconditional jump to register
171#define UJUMP 12 // Unconditional jump
172#define CJUMP 13 // Conditional branch (BEQ/BNE/BGTZ/BLEZ)
173#define SJUMP 14 // Conditional branch (regimm format)
174#define COP0 15 // Coprocessor 0
175#define COP1 16 // Coprocessor 1
176#define C1LS 17 // Coprocessor 1 load/store
177#define FJUMP 18 // Conditional branch (floating point)
178#define FLOAT 19 // Floating point unit
179#define FCONV 20 // Convert integer to float
180#define FCOMP 21 // Floating point compare (sets FSREG)
181#define SYSCALL 22// SYSCALL
182#define OTHER 23 // Other
183#define SPAN 24 // Branch/delay slot spans 2 pages
184#define NI 25 // Not implemented
7139f3c8 185#define HLECALL 26// PCSX fake opcodes for HLE
b9b61529 186#define COP2 27 // Coprocessor 2 move
187#define C2LS 28 // Coprocessor 2 load/store
188#define C2OP 29 // Coprocessor 2 operation
1e973cb0 189#define INTCALL 30// Call interpreter to handle rare corner cases
57871462 190
191 /* stubs */
192#define CC_STUB 1
193#define FP_STUB 2
194#define LOADB_STUB 3
195#define LOADH_STUB 4
196#define LOADW_STUB 5
197#define LOADD_STUB 6
198#define LOADBU_STUB 7
199#define LOADHU_STUB 8
200#define STOREB_STUB 9
201#define STOREH_STUB 10
202#define STOREW_STUB 11
203#define STORED_STUB 12
204#define STORELR_STUB 13
205#define INVCODE_STUB 14
206
207 /* branch codes */
208#define TAKEN 1
209#define NOTTAKEN 2
210#define NULLDS 3
211
212// asm linkage
213int new_recompile_block(int addr);
214void *get_addr_ht(u_int vaddr);
215void invalidate_block(u_int block);
216void invalidate_addr(u_int addr);
217void remove_hash(int vaddr);
218void jump_vaddr();
219void dyna_linker();
220void dyna_linker_ds();
221void verify_code();
222void verify_code_vm();
223void verify_code_ds();
224void cc_interrupt();
225void fp_exception();
226void fp_exception_ds();
227void jump_syscall();
7139f3c8 228void jump_syscall_hle();
57871462 229void jump_eret();
7139f3c8 230void jump_hlecall();
1e973cb0 231void jump_intcall();
7139f3c8 232void new_dyna_leave();
57871462 233
234// TLB
235void TLBWI_new();
236void TLBWR_new();
237void read_nomem_new();
238void read_nomemb_new();
239void read_nomemh_new();
240void read_nomemd_new();
241void write_nomem_new();
242void write_nomemb_new();
243void write_nomemh_new();
244void write_nomemd_new();
245void write_rdram_new();
246void write_rdramb_new();
247void write_rdramh_new();
248void write_rdramd_new();
249extern u_int memory_map[1048576];
250
251// Needed by assembler
252void wb_register(signed char r,signed char regmap[],uint64_t dirty,uint64_t is32);
253void wb_dirtys(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty);
254void wb_needed_dirtys(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr);
255void load_all_regs(signed char i_regmap[]);
256void load_needed_regs(signed char i_regmap[],signed char next_regmap[]);
257void load_regs_entry(int t);
258void load_all_consts(signed char regmap[],int is32,u_int dirty,int i);
259
260int tracedebug=0;
261
262//#define DEBUG_CYCLE_COUNT 1
263
264void nullf() {}
265//#define assem_debug printf
266//#define inv_debug printf
267#define assem_debug nullf
268#define inv_debug nullf
269
94d23bb9 270static void tlb_hacks()
57871462 271{
94d23bb9 272#ifndef DISABLE_TLB
57871462 273 // Goldeneye hack
274 if (strncmp((char *) ROM_HEADER->nom, "GOLDENEYE",9) == 0)
275 {
276 u_int addr;
277 int n;
278 switch (ROM_HEADER->Country_code&0xFF)
279 {
280 case 0x45: // U
281 addr=0x34b30;
282 break;
283 case 0x4A: // J
284 addr=0x34b70;
285 break;
286 case 0x50: // E
287 addr=0x329f0;
288 break;
289 default:
290 // Unknown country code
291 addr=0;
292 break;
293 }
294 u_int rom_addr=(u_int)rom;
295 #ifdef ROM_COPY
296 // Since memory_map is 32-bit, on 64-bit systems the rom needs to be
297 // in the lower 4G of memory to use this hack. Copy it if necessary.
298 if((void *)rom>(void *)0xffffffff) {
299 munmap(ROM_COPY, 67108864);
300 if(mmap(ROM_COPY, 12582912,
301 PROT_READ | PROT_WRITE,
302 MAP_FIXED | MAP_PRIVATE | MAP_ANONYMOUS,
303 -1, 0) <= 0) {printf("mmap() failed\n");}
304 memcpy(ROM_COPY,rom,12582912);
305 rom_addr=(u_int)ROM_COPY;
306 }
307 #endif
308 if(addr) {
309 for(n=0x7F000;n<0x80000;n++) {
310 memory_map[n]=(((u_int)(rom_addr+addr-0x7F000000))>>2)|0x40000000;
311 }
312 }
313 }
94d23bb9 314#endif
57871462 315}
316
94d23bb9 317static u_int get_page(u_int vaddr)
57871462 318{
0ce47d46 319#ifndef PCSX
57871462 320 u_int page=(vaddr^0x80000000)>>12;
0ce47d46 321#else
322 u_int page=vaddr&~0xe0000000;
323 if (page < 0x1000000)
324 page &= ~0x0e00000; // RAM mirrors
325 page>>=12;
326#endif
94d23bb9 327#ifndef DISABLE_TLB
57871462 328 if(page>262143&&tlb_LUT_r[vaddr>>12]) page=(tlb_LUT_r[vaddr>>12]^0x80000000)>>12;
94d23bb9 329#endif
57871462 330 if(page>2048) page=2048+(page&2047);
94d23bb9 331 return page;
332}
333
334static u_int get_vpage(u_int vaddr)
335{
336 u_int vpage=(vaddr^0x80000000)>>12;
337#ifndef DISABLE_TLB
57871462 338 if(vpage>262143&&tlb_LUT_r[vaddr>>12]) vpage&=2047; // jump_dirty uses a hash of the virtual address instead
94d23bb9 339#endif
57871462 340 if(vpage>2048) vpage=2048+(vpage&2047);
94d23bb9 341 return vpage;
342}
343
344// Get address from virtual address
345// This is called from the recompiled JR/JALR instructions
346void *get_addr(u_int vaddr)
347{
348 u_int page=get_page(vaddr);
349 u_int vpage=get_vpage(vaddr);
57871462 350 struct ll_entry *head;
351 //printf("TRACE: count=%d next=%d (get_addr %x,page %d)\n",Count,next_interupt,vaddr,page);
352 head=jump_in[page];
353 while(head!=NULL) {
354 if(head->vaddr==vaddr&&head->reg32==0) {
355 //printf("TRACE: count=%d next=%d (get_addr match %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr);
356 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
357 ht_bin[3]=ht_bin[1];
358 ht_bin[2]=ht_bin[0];
359 ht_bin[1]=(int)head->addr;
360 ht_bin[0]=vaddr;
361 return head->addr;
362 }
363 head=head->next;
364 }
365 head=jump_dirty[vpage];
366 while(head!=NULL) {
367 if(head->vaddr==vaddr&&head->reg32==0) {
368 //printf("TRACE: count=%d next=%d (get_addr match dirty %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr);
369 // Don't restore blocks which are about to expire from the cache
370 if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
371 if(verify_dirty(head->addr)) {
372 //printf("restore candidate: %x (%d) d=%d\n",vaddr,page,invalid_code[vaddr>>12]);
373 invalid_code[vaddr>>12]=0;
374 memory_map[vaddr>>12]|=0x40000000;
375 if(vpage<2048) {
94d23bb9 376#ifndef DISABLE_TLB
57871462 377 if(tlb_LUT_r[vaddr>>12]) {
378 invalid_code[tlb_LUT_r[vaddr>>12]>>12]=0;
379 memory_map[tlb_LUT_r[vaddr>>12]>>12]|=0x40000000;
380 }
94d23bb9 381#endif
57871462 382 restore_candidate[vpage>>3]|=1<<(vpage&7);
383 }
384 else restore_candidate[page>>3]|=1<<(page&7);
385 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
386 if(ht_bin[0]==vaddr) {
387 ht_bin[1]=(int)head->addr; // Replace existing entry
388 }
389 else
390 {
391 ht_bin[3]=ht_bin[1];
392 ht_bin[2]=ht_bin[0];
393 ht_bin[1]=(int)head->addr;
394 ht_bin[0]=vaddr;
395 }
396 return head->addr;
397 }
398 }
399 head=head->next;
400 }
401 //printf("TRACE: count=%d next=%d (get_addr no-match %x)\n",Count,next_interupt,vaddr);
402 int r=new_recompile_block(vaddr);
403 if(r==0) return get_addr(vaddr);
404 // Execute in unmapped page, generate pagefault execption
405 Status|=2;
406 Cause=(vaddr<<31)|0x8;
407 EPC=(vaddr&1)?vaddr-5:vaddr;
408 BadVAddr=(vaddr&~1);
409 Context=(Context&0xFF80000F)|((BadVAddr>>9)&0x007FFFF0);
410 EntryHi=BadVAddr&0xFFFFE000;
411 return get_addr_ht(0x80000000);
412}
413// Look up address in hash table first
414void *get_addr_ht(u_int vaddr)
415{
416 //printf("TRACE: count=%d next=%d (get_addr_ht %x)\n",Count,next_interupt,vaddr);
417 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
418 if(ht_bin[0]==vaddr) return (void *)ht_bin[1];
419 if(ht_bin[2]==vaddr) return (void *)ht_bin[3];
420 return get_addr(vaddr);
421}
422
423void *get_addr_32(u_int vaddr,u_int flags)
424{
7139f3c8 425#ifdef FORCE32
426 return get_addr(vaddr);
560e4a12 427#else
57871462 428 //printf("TRACE: count=%d next=%d (get_addr_32 %x,flags %x)\n",Count,next_interupt,vaddr,flags);
429 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
430 if(ht_bin[0]==vaddr) return (void *)ht_bin[1];
431 if(ht_bin[2]==vaddr) return (void *)ht_bin[3];
94d23bb9 432 u_int page=get_page(vaddr);
433 u_int vpage=get_vpage(vaddr);
57871462 434 struct ll_entry *head;
435 head=jump_in[page];
436 while(head!=NULL) {
437 if(head->vaddr==vaddr&&(head->reg32&flags)==0) {
438 //printf("TRACE: count=%d next=%d (get_addr_32 match %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr);
439 if(head->reg32==0) {
440 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
441 if(ht_bin[0]==-1) {
442 ht_bin[1]=(int)head->addr;
443 ht_bin[0]=vaddr;
444 }else if(ht_bin[2]==-1) {
445 ht_bin[3]=(int)head->addr;
446 ht_bin[2]=vaddr;
447 }
448 //ht_bin[3]=ht_bin[1];
449 //ht_bin[2]=ht_bin[0];
450 //ht_bin[1]=(int)head->addr;
451 //ht_bin[0]=vaddr;
452 }
453 return head->addr;
454 }
455 head=head->next;
456 }
457 head=jump_dirty[vpage];
458 while(head!=NULL) {
459 if(head->vaddr==vaddr&&(head->reg32&flags)==0) {
460 //printf("TRACE: count=%d next=%d (get_addr_32 match dirty %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr);
461 // Don't restore blocks which are about to expire from the cache
462 if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
463 if(verify_dirty(head->addr)) {
464 //printf("restore candidate: %x (%d) d=%d\n",vaddr,page,invalid_code[vaddr>>12]);
465 invalid_code[vaddr>>12]=0;
466 memory_map[vaddr>>12]|=0x40000000;
467 if(vpage<2048) {
94d23bb9 468#ifndef DISABLE_TLB
57871462 469 if(tlb_LUT_r[vaddr>>12]) {
470 invalid_code[tlb_LUT_r[vaddr>>12]>>12]=0;
471 memory_map[tlb_LUT_r[vaddr>>12]>>12]|=0x40000000;
472 }
94d23bb9 473#endif
57871462 474 restore_candidate[vpage>>3]|=1<<(vpage&7);
475 }
476 else restore_candidate[page>>3]|=1<<(page&7);
477 if(head->reg32==0) {
478 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
479 if(ht_bin[0]==-1) {
480 ht_bin[1]=(int)head->addr;
481 ht_bin[0]=vaddr;
482 }else if(ht_bin[2]==-1) {
483 ht_bin[3]=(int)head->addr;
484 ht_bin[2]=vaddr;
485 }
486 //ht_bin[3]=ht_bin[1];
487 //ht_bin[2]=ht_bin[0];
488 //ht_bin[1]=(int)head->addr;
489 //ht_bin[0]=vaddr;
490 }
491 return head->addr;
492 }
493 }
494 head=head->next;
495 }
496 //printf("TRACE: count=%d next=%d (get_addr_32 no-match %x,flags %x)\n",Count,next_interupt,vaddr,flags);
497 int r=new_recompile_block(vaddr);
498 if(r==0) return get_addr(vaddr);
499 // Execute in unmapped page, generate pagefault execption
500 Status|=2;
501 Cause=(vaddr<<31)|0x8;
502 EPC=(vaddr&1)?vaddr-5:vaddr;
503 BadVAddr=(vaddr&~1);
504 Context=(Context&0xFF80000F)|((BadVAddr>>9)&0x007FFFF0);
505 EntryHi=BadVAddr&0xFFFFE000;
506 return get_addr_ht(0x80000000);
560e4a12 507#endif
57871462 508}
509
510void clear_all_regs(signed char regmap[])
511{
512 int hr;
513 for (hr=0;hr<HOST_REGS;hr++) regmap[hr]=-1;
514}
515
516signed char get_reg(signed char regmap[],int r)
517{
518 int hr;
519 for (hr=0;hr<HOST_REGS;hr++) if(hr!=EXCLUDE_REG&&regmap[hr]==r) return hr;
520 return -1;
521}
522
523// Find a register that is available for two consecutive cycles
524signed char get_reg2(signed char regmap1[],signed char regmap2[],int r)
525{
526 int hr;
527 for (hr=0;hr<HOST_REGS;hr++) if(hr!=EXCLUDE_REG&&regmap1[hr]==r&&regmap2[hr]==r) return hr;
528 return -1;
529}
530
531int count_free_regs(signed char regmap[])
532{
533 int count=0;
534 int hr;
535 for(hr=0;hr<HOST_REGS;hr++)
536 {
537 if(hr!=EXCLUDE_REG) {
538 if(regmap[hr]<0) count++;
539 }
540 }
541 return count;
542}
543
544void dirty_reg(struct regstat *cur,signed char reg)
545{
546 int hr;
547 if(!reg) return;
548 for (hr=0;hr<HOST_REGS;hr++) {
549 if((cur->regmap[hr]&63)==reg) {
550 cur->dirty|=1<<hr;
551 }
552 }
553}
554
555// If we dirty the lower half of a 64 bit register which is now being
556// sign-extended, we need to dump the upper half.
557// Note: Do this only after completion of the instruction, because
558// some instructions may need to read the full 64-bit value even if
559// overwriting it (eg SLTI, DSRA32).
560static void flush_dirty_uppers(struct regstat *cur)
561{
562 int hr,reg;
563 for (hr=0;hr<HOST_REGS;hr++) {
564 if((cur->dirty>>hr)&1) {
565 reg=cur->regmap[hr];
566 if(reg>=64)
567 if((cur->is32>>(reg&63))&1) cur->regmap[hr]=-1;
568 }
569 }
570}
571
572void set_const(struct regstat *cur,signed char reg,uint64_t value)
573{
574 int hr;
575 if(!reg) return;
576 for (hr=0;hr<HOST_REGS;hr++) {
577 if(cur->regmap[hr]==reg) {
578 cur->isconst|=1<<hr;
579 cur->constmap[hr]=value;
580 }
581 else if((cur->regmap[hr]^64)==reg) {
582 cur->isconst|=1<<hr;
583 cur->constmap[hr]=value>>32;
584 }
585 }
586}
587
588void clear_const(struct regstat *cur,signed char reg)
589{
590 int hr;
591 if(!reg) return;
592 for (hr=0;hr<HOST_REGS;hr++) {
593 if((cur->regmap[hr]&63)==reg) {
594 cur->isconst&=~(1<<hr);
595 }
596 }
597}
598
599int is_const(struct regstat *cur,signed char reg)
600{
601 int hr;
79c75f1b 602 if(reg<0) return 0;
57871462 603 if(!reg) return 1;
604 for (hr=0;hr<HOST_REGS;hr++) {
605 if((cur->regmap[hr]&63)==reg) {
606 return (cur->isconst>>hr)&1;
607 }
608 }
609 return 0;
610}
611uint64_t get_const(struct regstat *cur,signed char reg)
612{
613 int hr;
614 if(!reg) return 0;
615 for (hr=0;hr<HOST_REGS;hr++) {
616 if(cur->regmap[hr]==reg) {
617 return cur->constmap[hr];
618 }
619 }
620 printf("Unknown constant in r%d\n",reg);
621 exit(1);
622}
623
624// Least soon needed registers
625// Look at the next ten instructions and see which registers
626// will be used. Try not to reallocate these.
627void lsn(u_char hsn[], int i, int *preferred_reg)
628{
629 int j;
630 int b=-1;
631 for(j=0;j<9;j++)
632 {
633 if(i+j>=slen) {
634 j=slen-i-1;
635 break;
636 }
637 if(itype[i+j]==UJUMP||itype[i+j]==RJUMP||(source[i+j]>>16)==0x1000)
638 {
639 // Don't go past an unconditonal jump
640 j++;
641 break;
642 }
643 }
644 for(;j>=0;j--)
645 {
646 if(rs1[i+j]) hsn[rs1[i+j]]=j;
647 if(rs2[i+j]) hsn[rs2[i+j]]=j;
648 if(rt1[i+j]) hsn[rt1[i+j]]=j;
649 if(rt2[i+j]) hsn[rt2[i+j]]=j;
650 if(itype[i+j]==STORE || itype[i+j]==STORELR) {
651 // Stores can allocate zero
652 hsn[rs1[i+j]]=j;
653 hsn[rs2[i+j]]=j;
654 }
655 // On some architectures stores need invc_ptr
656 #if defined(HOST_IMM8)
b9b61529 657 if(itype[i+j]==STORE || itype[i+j]==STORELR || (opcode[i+j]&0x3b)==0x39 || (opcode[i+j]&0x3b)==0x3a) {
57871462 658 hsn[INVCP]=j;
659 }
660 #endif
661 if(i+j>=0&&(itype[i+j]==UJUMP||itype[i+j]==CJUMP||itype[i+j]==SJUMP||itype[i+j]==FJUMP))
662 {
663 hsn[CCREG]=j;
664 b=j;
665 }
666 }
667 if(b>=0)
668 {
669 if(ba[i+b]>=start && ba[i+b]<(start+slen*4))
670 {
671 // Follow first branch
672 int t=(ba[i+b]-start)>>2;
673 j=7-b;if(t+j>=slen) j=slen-t-1;
674 for(;j>=0;j--)
675 {
676 if(rs1[t+j]) if(hsn[rs1[t+j]]>j+b+2) hsn[rs1[t+j]]=j+b+2;
677 if(rs2[t+j]) if(hsn[rs2[t+j]]>j+b+2) hsn[rs2[t+j]]=j+b+2;
678 //if(rt1[t+j]) if(hsn[rt1[t+j]]>j+b+2) hsn[rt1[t+j]]=j+b+2;
679 //if(rt2[t+j]) if(hsn[rt2[t+j]]>j+b+2) hsn[rt2[t+j]]=j+b+2;
680 }
681 }
682 // TODO: preferred register based on backward branch
683 }
684 // Delay slot should preferably not overwrite branch conditions or cycle count
685 if(i>0&&(itype[i-1]==RJUMP||itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP)) {
686 if(rs1[i-1]) if(hsn[rs1[i-1]]>1) hsn[rs1[i-1]]=1;
687 if(rs2[i-1]) if(hsn[rs2[i-1]]>1) hsn[rs2[i-1]]=1;
688 hsn[CCREG]=1;
689 // ...or hash tables
690 hsn[RHASH]=1;
691 hsn[RHTBL]=1;
692 }
693 // Coprocessor load/store needs FTEMP, even if not declared
b9b61529 694 if(itype[i]==C1LS||itype[i]==C2LS) {
57871462 695 hsn[FTEMP]=0;
696 }
697 // Load L/R also uses FTEMP as a temporary register
698 if(itype[i]==LOADLR) {
699 hsn[FTEMP]=0;
700 }
b7918751 701 // Also SWL/SWR/SDL/SDR
702 if(opcode[i]==0x2a||opcode[i]==0x2e||opcode[i]==0x2c||opcode[i]==0x2d) {
57871462 703 hsn[FTEMP]=0;
704 }
705 // Don't remove the TLB registers either
b9b61529 706 if(itype[i]==LOAD || itype[i]==LOADLR || itype[i]==STORE || itype[i]==STORELR || itype[i]==C1LS || itype[i]==C2LS) {
57871462 707 hsn[TLREG]=0;
708 }
709 // Don't remove the miniht registers
710 if(itype[i]==UJUMP||itype[i]==RJUMP)
711 {
712 hsn[RHASH]=0;
713 hsn[RHTBL]=0;
714 }
715}
716
717// We only want to allocate registers if we're going to use them again soon
718int needed_again(int r, int i)
719{
720 int j;
721 int b=-1;
722 int rn=10;
57871462 723
724 if(i>0&&(itype[i-1]==UJUMP||itype[i-1]==RJUMP||(source[i-1]>>16)==0x1000))
725 {
726 if(ba[i-1]<start || ba[i-1]>start+slen*4-4)
727 return 0; // Don't need any registers if exiting the block
728 }
729 for(j=0;j<9;j++)
730 {
731 if(i+j>=slen) {
732 j=slen-i-1;
733 break;
734 }
735 if(itype[i+j]==UJUMP||itype[i+j]==RJUMP||(source[i+j]>>16)==0x1000)
736 {
737 // Don't go past an unconditonal jump
738 j++;
739 break;
740 }
1e973cb0 741 if(itype[i+j]==SYSCALL||itype[i+j]==HLECALL||itype[i+j]==INTCALL||((source[i+j]&0xfc00003f)==0x0d))
57871462 742 {
743 break;
744 }
745 }
746 for(;j>=1;j--)
747 {
748 if(rs1[i+j]==r) rn=j;
749 if(rs2[i+j]==r) rn=j;
750 if((unneeded_reg[i+j]>>r)&1) rn=10;
751 if(i+j>=0&&(itype[i+j]==UJUMP||itype[i+j]==CJUMP||itype[i+j]==SJUMP||itype[i+j]==FJUMP))
752 {
753 b=j;
754 }
755 }
756 /*
757 if(b>=0)
758 {
759 if(ba[i+b]>=start && ba[i+b]<(start+slen*4))
760 {
761 // Follow first branch
762 int o=rn;
763 int t=(ba[i+b]-start)>>2;
764 j=7-b;if(t+j>=slen) j=slen-t-1;
765 for(;j>=0;j--)
766 {
767 if(!((unneeded_reg[t+j]>>r)&1)) {
768 if(rs1[t+j]==r) if(rn>j+b+2) rn=j+b+2;
769 if(rs2[t+j]==r) if(rn>j+b+2) rn=j+b+2;
770 }
771 else rn=o;
772 }
773 }
774 }*/
b7217e13 775 if(rn<10) return 1;
57871462 776 return 0;
777}
778
779// Try to match register allocations at the end of a loop with those
780// at the beginning
781int loop_reg(int i, int r, int hr)
782{
783 int j,k;
784 for(j=0;j<9;j++)
785 {
786 if(i+j>=slen) {
787 j=slen-i-1;
788 break;
789 }
790 if(itype[i+j]==UJUMP||itype[i+j]==RJUMP||(source[i+j]>>16)==0x1000)
791 {
792 // Don't go past an unconditonal jump
793 j++;
794 break;
795 }
796 }
797 k=0;
798 if(i>0){
799 if(itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP)
800 k--;
801 }
802 for(;k<j;k++)
803 {
804 if(r<64&&((unneeded_reg[i+k]>>r)&1)) return hr;
805 if(r>64&&((unneeded_reg_upper[i+k]>>r)&1)) return hr;
806 if(i+k>=0&&(itype[i+k]==UJUMP||itype[i+k]==CJUMP||itype[i+k]==SJUMP||itype[i+k]==FJUMP))
807 {
808 if(ba[i+k]>=start && ba[i+k]<(start+i*4))
809 {
810 int t=(ba[i+k]-start)>>2;
811 int reg=get_reg(regs[t].regmap_entry,r);
812 if(reg>=0) return reg;
813 //reg=get_reg(regs[t+1].regmap_entry,r);
814 //if(reg>=0) return reg;
815 }
816 }
817 }
818 return hr;
819}
820
821
822// Allocate every register, preserving source/target regs
823void alloc_all(struct regstat *cur,int i)
824{
825 int hr;
826
827 for(hr=0;hr<HOST_REGS;hr++) {
828 if(hr!=EXCLUDE_REG) {
829 if(((cur->regmap[hr]&63)!=rs1[i])&&((cur->regmap[hr]&63)!=rs2[i])&&
830 ((cur->regmap[hr]&63)!=rt1[i])&&((cur->regmap[hr]&63)!=rt2[i]))
831 {
832 cur->regmap[hr]=-1;
833 cur->dirty&=~(1<<hr);
834 }
835 // Don't need zeros
836 if((cur->regmap[hr]&63)==0)
837 {
838 cur->regmap[hr]=-1;
839 cur->dirty&=~(1<<hr);
840 }
841 }
842 }
843}
844
845
846void div64(int64_t dividend,int64_t divisor)
847{
848 lo=dividend/divisor;
849 hi=dividend%divisor;
850 //printf("TRACE: ddiv %8x%8x %8x%8x\n" ,(int)reg[HIREG],(int)(reg[HIREG]>>32)
851 // ,(int)reg[LOREG],(int)(reg[LOREG]>>32));
852}
853void divu64(uint64_t dividend,uint64_t divisor)
854{
855 lo=dividend/divisor;
856 hi=dividend%divisor;
857 //printf("TRACE: ddivu %8x%8x %8x%8x\n",(int)reg[HIREG],(int)(reg[HIREG]>>32)
858 // ,(int)reg[LOREG],(int)(reg[LOREG]>>32));
859}
860
861void mult64(uint64_t m1,uint64_t m2)
862{
863 unsigned long long int op1, op2, op3, op4;
864 unsigned long long int result1, result2, result3, result4;
865 unsigned long long int temp1, temp2, temp3, temp4;
866 int sign = 0;
867
868 if (m1 < 0)
869 {
870 op2 = -m1;
871 sign = 1 - sign;
872 }
873 else op2 = m1;
874 if (m2 < 0)
875 {
876 op4 = -m2;
877 sign = 1 - sign;
878 }
879 else op4 = m2;
880
881 op1 = op2 & 0xFFFFFFFF;
882 op2 = (op2 >> 32) & 0xFFFFFFFF;
883 op3 = op4 & 0xFFFFFFFF;
884 op4 = (op4 >> 32) & 0xFFFFFFFF;
885
886 temp1 = op1 * op3;
887 temp2 = (temp1 >> 32) + op1 * op4;
888 temp3 = op2 * op3;
889 temp4 = (temp3 >> 32) + op2 * op4;
890
891 result1 = temp1 & 0xFFFFFFFF;
892 result2 = temp2 + (temp3 & 0xFFFFFFFF);
893 result3 = (result2 >> 32) + temp4;
894 result4 = (result3 >> 32);
895
896 lo = result1 | (result2 << 32);
897 hi = (result3 & 0xFFFFFFFF) | (result4 << 32);
898 if (sign)
899 {
900 hi = ~hi;
901 if (!lo) hi++;
902 else lo = ~lo + 1;
903 }
904}
905
906void multu64(uint64_t m1,uint64_t m2)
907{
908 unsigned long long int op1, op2, op3, op4;
909 unsigned long long int result1, result2, result3, result4;
910 unsigned long long int temp1, temp2, temp3, temp4;
911
912 op1 = m1 & 0xFFFFFFFF;
913 op2 = (m1 >> 32) & 0xFFFFFFFF;
914 op3 = m2 & 0xFFFFFFFF;
915 op4 = (m2 >> 32) & 0xFFFFFFFF;
916
917 temp1 = op1 * op3;
918 temp2 = (temp1 >> 32) + op1 * op4;
919 temp3 = op2 * op3;
920 temp4 = (temp3 >> 32) + op2 * op4;
921
922 result1 = temp1 & 0xFFFFFFFF;
923 result2 = temp2 + (temp3 & 0xFFFFFFFF);
924 result3 = (result2 >> 32) + temp4;
925 result4 = (result3 >> 32);
926
927 lo = result1 | (result2 << 32);
928 hi = (result3 & 0xFFFFFFFF) | (result4 << 32);
929
930 //printf("TRACE: dmultu %8x%8x %8x%8x\n",(int)reg[HIREG],(int)(reg[HIREG]>>32)
931 // ,(int)reg[LOREG],(int)(reg[LOREG]>>32));
932}
933
934uint64_t ldl_merge(uint64_t original,uint64_t loaded,u_int bits)
935{
936 if(bits) {
937 original<<=64-bits;
938 original>>=64-bits;
939 loaded<<=bits;
940 original|=loaded;
941 }
942 else original=loaded;
943 return original;
944}
945uint64_t ldr_merge(uint64_t original,uint64_t loaded,u_int bits)
946{
947 if(bits^56) {
948 original>>=64-(bits^56);
949 original<<=64-(bits^56);
950 loaded>>=bits^56;
951 original|=loaded;
952 }
953 else original=loaded;
954 return original;
955}
956
957#ifdef __i386__
958#include "assem_x86.c"
959#endif
960#ifdef __x86_64__
961#include "assem_x64.c"
962#endif
963#ifdef __arm__
964#include "assem_arm.c"
965#endif
966
967// Add virtual address mapping to linked list
968void ll_add(struct ll_entry **head,int vaddr,void *addr)
969{
970 struct ll_entry *new_entry;
971 new_entry=malloc(sizeof(struct ll_entry));
972 assert(new_entry!=NULL);
973 new_entry->vaddr=vaddr;
974 new_entry->reg32=0;
975 new_entry->addr=addr;
976 new_entry->next=*head;
977 *head=new_entry;
978}
979
980// Add virtual address mapping for 32-bit compiled block
981void ll_add_32(struct ll_entry **head,int vaddr,u_int reg32,void *addr)
982{
7139f3c8 983 ll_add(head,vaddr,addr);
984#ifndef FORCE32
985 (*head)->reg32=reg32;
986#endif
57871462 987}
988
989// Check if an address is already compiled
990// but don't return addresses which are about to expire from the cache
991void *check_addr(u_int vaddr)
992{
993 u_int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
994 if(ht_bin[0]==vaddr) {
995 if(((ht_bin[1]-MAX_OUTPUT_BLOCK_SIZE-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
996 if(isclean(ht_bin[1])) return (void *)ht_bin[1];
997 }
998 if(ht_bin[2]==vaddr) {
999 if(((ht_bin[3]-MAX_OUTPUT_BLOCK_SIZE-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
1000 if(isclean(ht_bin[3])) return (void *)ht_bin[3];
1001 }
94d23bb9 1002 u_int page=get_page(vaddr);
57871462 1003 struct ll_entry *head;
1004 head=jump_in[page];
1005 while(head!=NULL) {
1006 if(head->vaddr==vaddr&&head->reg32==0) {
1007 if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2))) {
1008 // Update existing entry with current address
1009 if(ht_bin[0]==vaddr) {
1010 ht_bin[1]=(int)head->addr;
1011 return head->addr;
1012 }
1013 if(ht_bin[2]==vaddr) {
1014 ht_bin[3]=(int)head->addr;
1015 return head->addr;
1016 }
1017 // Insert into hash table with low priority.
1018 // Don't evict existing entries, as they are probably
1019 // addresses that are being accessed frequently.
1020 if(ht_bin[0]==-1) {
1021 ht_bin[1]=(int)head->addr;
1022 ht_bin[0]=vaddr;
1023 }else if(ht_bin[2]==-1) {
1024 ht_bin[3]=(int)head->addr;
1025 ht_bin[2]=vaddr;
1026 }
1027 return head->addr;
1028 }
1029 }
1030 head=head->next;
1031 }
1032 return 0;
1033}
1034
1035void remove_hash(int vaddr)
1036{
1037 //printf("remove hash: %x\n",vaddr);
1038 int *ht_bin=hash_table[(((vaddr)>>16)^vaddr)&0xFFFF];
1039 if(ht_bin[2]==vaddr) {
1040 ht_bin[2]=ht_bin[3]=-1;
1041 }
1042 if(ht_bin[0]==vaddr) {
1043 ht_bin[0]=ht_bin[2];
1044 ht_bin[1]=ht_bin[3];
1045 ht_bin[2]=ht_bin[3]=-1;
1046 }
1047}
1048
1049void ll_remove_matching_addrs(struct ll_entry **head,int addr,int shift)
1050{
1051 struct ll_entry *next;
1052 while(*head) {
1053 if(((u_int)((*head)->addr)>>shift)==(addr>>shift) ||
1054 ((u_int)((*head)->addr-MAX_OUTPUT_BLOCK_SIZE)>>shift)==(addr>>shift))
1055 {
1056 inv_debug("EXP: Remove pointer to %x (%x)\n",(int)(*head)->addr,(*head)->vaddr);
1057 remove_hash((*head)->vaddr);
1058 next=(*head)->next;
1059 free(*head);
1060 *head=next;
1061 }
1062 else
1063 {
1064 head=&((*head)->next);
1065 }
1066 }
1067}
1068
1069// Remove all entries from linked list
1070void ll_clear(struct ll_entry **head)
1071{
1072 struct ll_entry *cur;
1073 struct ll_entry *next;
1074 if(cur=*head) {
1075 *head=0;
1076 while(cur) {
1077 next=cur->next;
1078 free(cur);
1079 cur=next;
1080 }
1081 }
1082}
1083
1084// Dereference the pointers and remove if it matches
1085void ll_kill_pointers(struct ll_entry *head,int addr,int shift)
1086{
1087 while(head) {
1088 int ptr=get_pointer(head->addr);
1089 inv_debug("EXP: Lookup pointer to %x at %x (%x)\n",(int)ptr,(int)head->addr,head->vaddr);
1090 if(((ptr>>shift)==(addr>>shift)) ||
1091 (((ptr-MAX_OUTPUT_BLOCK_SIZE)>>shift)==(addr>>shift)))
1092 {
5088bb70 1093 inv_debug("EXP: Kill pointer at %x (%x)\n",(int)head->addr,head->vaddr);
f76eeef9 1094 u_int host_addr=(u_int)kill_pointer(head->addr);
dd3a91a1 1095 #ifdef __arm__
1096 needs_clear_cache[(host_addr-(u_int)BASE_ADDR)>>17]|=1<<(((host_addr-(u_int)BASE_ADDR)>>12)&31);
1097 #endif
57871462 1098 }
1099 head=head->next;
1100 }
1101}
1102
1103// This is called when we write to a compiled block (see do_invstub)
f76eeef9 1104void invalidate_page(u_int page)
57871462 1105{
57871462 1106 struct ll_entry *head;
1107 struct ll_entry *next;
1108 head=jump_in[page];
1109 jump_in[page]=0;
1110 while(head!=NULL) {
1111 inv_debug("INVALIDATE: %x\n",head->vaddr);
1112 remove_hash(head->vaddr);
1113 next=head->next;
1114 free(head);
1115 head=next;
1116 }
1117 head=jump_out[page];
1118 jump_out[page]=0;
1119 while(head!=NULL) {
1120 inv_debug("INVALIDATE: kill pointer to %x (%x)\n",head->vaddr,(int)head->addr);
f76eeef9 1121 u_int host_addr=(u_int)kill_pointer(head->addr);
dd3a91a1 1122 #ifdef __arm__
1123 needs_clear_cache[(host_addr-(u_int)BASE_ADDR)>>17]|=1<<(((host_addr-(u_int)BASE_ADDR)>>12)&31);
1124 #endif
57871462 1125 next=head->next;
1126 free(head);
1127 head=next;
1128 }
57871462 1129}
1130void invalidate_block(u_int block)
1131{
94d23bb9 1132 u_int page=get_page(block<<12);
1133 u_int vpage=get_vpage(block<<12);
57871462 1134 inv_debug("INVALIDATE: %x (%d)\n",block<<12,page);
1135 //inv_debug("invalid_code[block]=%d\n",invalid_code[block]);
1136 u_int first,last;
1137 first=last=page;
1138 struct ll_entry *head;
1139 head=jump_dirty[vpage];
1140 //printf("page=%d vpage=%d\n",page,vpage);
1141 while(head!=NULL) {
1142 u_int start,end;
1143 if(vpage>2047||(head->vaddr>>12)==block) { // Ignore vaddr hash collision
1144 get_bounds((int)head->addr,&start,&end);
1145 //printf("start: %x end: %x\n",start,end);
4cb76aa4 1146 if(page<2048&&start>=0x80000000&&end<0x80000000+RAM_SIZE) {
57871462 1147 if(((start-(u_int)rdram)>>12)<=page&&((end-1-(u_int)rdram)>>12)>=page) {
1148 if((((start-(u_int)rdram)>>12)&2047)<first) first=((start-(u_int)rdram)>>12)&2047;
1149 if((((end-1-(u_int)rdram)>>12)&2047)>last) last=((end-1-(u_int)rdram)>>12)&2047;
1150 }
1151 }
90ae6d4e 1152#ifndef DISABLE_TLB
57871462 1153 if(page<2048&&(signed int)start>=(signed int)0xC0000000&&(signed int)end>=(signed int)0xC0000000) {
1154 if(((start+memory_map[start>>12]-(u_int)rdram)>>12)<=page&&((end-1+memory_map[(end-1)>>12]-(u_int)rdram)>>12)>=page) {
1155 if((((start+memory_map[start>>12]-(u_int)rdram)>>12)&2047)<first) first=((start+memory_map[start>>12]-(u_int)rdram)>>12)&2047;
1156 if((((end-1+memory_map[(end-1)>>12]-(u_int)rdram)>>12)&2047)>last) last=((end-1+memory_map[(end-1)>>12]-(u_int)rdram)>>12)&2047;
1157 }
1158 }
90ae6d4e 1159#endif
57871462 1160 }
1161 head=head->next;
1162 }
1163 //printf("first=%d last=%d\n",first,last);
f76eeef9 1164 invalidate_page(page);
57871462 1165 assert(first+5>page); // NB: this assumes MAXBLOCK<=4096 (4 pages)
1166 assert(last<page+5);
1167 // Invalidate the adjacent pages if a block crosses a 4K boundary
1168 while(first<page) {
1169 invalidate_page(first);
1170 first++;
1171 }
1172 for(first=page+1;first<last;first++) {
1173 invalidate_page(first);
1174 }
dd3a91a1 1175 #ifdef __arm__
1176 do_clear_cache();
1177 #endif
57871462 1178
1179 // Don't trap writes
1180 invalid_code[block]=1;
b12c9fb8 1181#ifdef PCSX
1182 invalid_code[((u_int)0x80000000>>12)|page]=1;
1183#endif
94d23bb9 1184#ifndef DISABLE_TLB
57871462 1185 // If there is a valid TLB entry for this page, remove write protect
1186 if(tlb_LUT_w[block]) {
1187 assert(tlb_LUT_r[block]==tlb_LUT_w[block]);
1188 // CHECK: Is this right?
1189 memory_map[block]=((tlb_LUT_w[block]&0xFFFFF000)-(block<<12)+(unsigned int)rdram-0x80000000)>>2;
1190 u_int real_block=tlb_LUT_w[block]>>12;
1191 invalid_code[real_block]=1;
1192 if(real_block>=0x80000&&real_block<0x80800) memory_map[real_block]=((u_int)rdram-0x80000000)>>2;
1193 }
1194 else if(block>=0x80000&&block<0x80800) memory_map[block]=((u_int)rdram-0x80000000)>>2;
94d23bb9 1195#endif
f76eeef9 1196
57871462 1197 #ifdef USE_MINI_HT
1198 memset(mini_ht,-1,sizeof(mini_ht));
1199 #endif
1200}
1201void invalidate_addr(u_int addr)
1202{
1203 invalidate_block(addr>>12);
1204}
dd3a91a1 1205// This is called when loading a save state.
1206// Anything could have changed, so invalidate everything.
57871462 1207void invalidate_all_pages()
1208{
1209 u_int page,n;
1210 for(page=0;page<4096;page++)
1211 invalidate_page(page);
1212 for(page=0;page<1048576;page++)
1213 if(!invalid_code[page]) {
1214 restore_candidate[(page&2047)>>3]|=1<<(page&7);
1215 restore_candidate[((page&2047)>>3)+256]|=1<<(page&7);
1216 }
1217 #ifdef __arm__
1218 __clear_cache((void *)BASE_ADDR,(void *)BASE_ADDR+(1<<TARGET_SIZE_2));
1219 #endif
1220 #ifdef USE_MINI_HT
1221 memset(mini_ht,-1,sizeof(mini_ht));
1222 #endif
94d23bb9 1223 #ifndef DISABLE_TLB
57871462 1224 // TLB
1225 for(page=0;page<0x100000;page++) {
1226 if(tlb_LUT_r[page]) {
1227 memory_map[page]=((tlb_LUT_r[page]&0xFFFFF000)-(page<<12)+(unsigned int)rdram-0x80000000)>>2;
1228 if(!tlb_LUT_w[page]||!invalid_code[page])
1229 memory_map[page]|=0x40000000; // Write protect
1230 }
1231 else memory_map[page]=-1;
1232 if(page==0x80000) page=0xC0000;
1233 }
1234 tlb_hacks();
94d23bb9 1235 #endif
57871462 1236}
1237
1238// Add an entry to jump_out after making a link
1239void add_link(u_int vaddr,void *src)
1240{
94d23bb9 1241 u_int page=get_page(vaddr);
57871462 1242 inv_debug("add_link: %x -> %x (%d)\n",(int)src,vaddr,page);
1243 ll_add(jump_out+page,vaddr,src);
1244 //int ptr=get_pointer(src);
1245 //inv_debug("add_link: Pointer is to %x\n",(int)ptr);
1246}
1247
1248// If a code block was found to be unmodified (bit was set in
1249// restore_candidate) and it remains unmodified (bit is clear
1250// in invalid_code) then move the entries for that 4K page from
1251// the dirty list to the clean list.
1252void clean_blocks(u_int page)
1253{
1254 struct ll_entry *head;
1255 inv_debug("INV: clean_blocks page=%d\n",page);
1256 head=jump_dirty[page];
1257 while(head!=NULL) {
1258 if(!invalid_code[head->vaddr>>12]) {
1259 // Don't restore blocks which are about to expire from the cache
1260 if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2))) {
1261 u_int start,end;
1262 if(verify_dirty((int)head->addr)) {
1263 //printf("Possibly Restore %x (%x)\n",head->vaddr, (int)head->addr);
1264 u_int i;
1265 u_int inv=0;
1266 get_bounds((int)head->addr,&start,&end);
4cb76aa4 1267 if(start-(u_int)rdram<RAM_SIZE) {
57871462 1268 for(i=(start-(u_int)rdram+0x80000000)>>12;i<=(end-1-(u_int)rdram+0x80000000)>>12;i++) {
1269 inv|=invalid_code[i];
1270 }
1271 }
1272 if((signed int)head->vaddr>=(signed int)0xC0000000) {
1273 u_int addr = (head->vaddr+(memory_map[head->vaddr>>12]<<2));
1274 //printf("addr=%x start=%x end=%x\n",addr,start,end);
1275 if(addr<start||addr>=end) inv=1;
1276 }
4cb76aa4 1277 else if((signed int)head->vaddr>=(signed int)0x80000000+RAM_SIZE) {
57871462 1278 inv=1;
1279 }
1280 if(!inv) {
1281 void * clean_addr=(void *)get_clean_addr((int)head->addr);
1282 if((((u_int)clean_addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2))) {
1283 u_int ppage=page;
94d23bb9 1284#ifndef DISABLE_TLB
57871462 1285 if(page<2048&&tlb_LUT_r[head->vaddr>>12]) ppage=(tlb_LUT_r[head->vaddr>>12]^0x80000000)>>12;
94d23bb9 1286#endif
57871462 1287 inv_debug("INV: Restored %x (%x/%x)\n",head->vaddr, (int)head->addr, (int)clean_addr);
1288 //printf("page=%x, addr=%x\n",page,head->vaddr);
1289 //assert(head->vaddr>>12==(page|0x80000));
1290 ll_add_32(jump_in+ppage,head->vaddr,head->reg32,clean_addr);
1291 int *ht_bin=hash_table[((head->vaddr>>16)^head->vaddr)&0xFFFF];
1292 if(!head->reg32) {
1293 if(ht_bin[0]==head->vaddr) {
1294 ht_bin[1]=(int)clean_addr; // Replace existing entry
1295 }
1296 if(ht_bin[2]==head->vaddr) {
1297 ht_bin[3]=(int)clean_addr; // Replace existing entry
1298 }
1299 }
1300 }
1301 }
1302 }
1303 }
1304 }
1305 head=head->next;
1306 }
1307}
1308
1309
1310void mov_alloc(struct regstat *current,int i)
1311{
1312 // Note: Don't need to actually alloc the source registers
1313 if((~current->is32>>rs1[i])&1) {
1314 //alloc_reg64(current,i,rs1[i]);
1315 alloc_reg64(current,i,rt1[i]);
1316 current->is32&=~(1LL<<rt1[i]);
1317 } else {
1318 //alloc_reg(current,i,rs1[i]);
1319 alloc_reg(current,i,rt1[i]);
1320 current->is32|=(1LL<<rt1[i]);
1321 }
1322 clear_const(current,rs1[i]);
1323 clear_const(current,rt1[i]);
1324 dirty_reg(current,rt1[i]);
1325}
1326
1327void shiftimm_alloc(struct regstat *current,int i)
1328{
1329 clear_const(current,rs1[i]);
1330 clear_const(current,rt1[i]);
1331 if(opcode2[i]<=0x3) // SLL/SRL/SRA
1332 {
1333 if(rt1[i]) {
1334 if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1335 else lt1[i]=rs1[i];
1336 alloc_reg(current,i,rt1[i]);
1337 current->is32|=1LL<<rt1[i];
1338 dirty_reg(current,rt1[i]);
1339 }
1340 }
1341 if(opcode2[i]>=0x38&&opcode2[i]<=0x3b) // DSLL/DSRL/DSRA
1342 {
1343 if(rt1[i]) {
1344 if(rs1[i]) alloc_reg64(current,i,rs1[i]);
1345 alloc_reg64(current,i,rt1[i]);
1346 current->is32&=~(1LL<<rt1[i]);
1347 dirty_reg(current,rt1[i]);
1348 }
1349 }
1350 if(opcode2[i]==0x3c) // DSLL32
1351 {
1352 if(rt1[i]) {
1353 if(rs1[i]) alloc_reg(current,i,rs1[i]);
1354 alloc_reg64(current,i,rt1[i]);
1355 current->is32&=~(1LL<<rt1[i]);
1356 dirty_reg(current,rt1[i]);
1357 }
1358 }
1359 if(opcode2[i]==0x3e) // DSRL32
1360 {
1361 if(rt1[i]) {
1362 alloc_reg64(current,i,rs1[i]);
1363 if(imm[i]==32) {
1364 alloc_reg64(current,i,rt1[i]);
1365 current->is32&=~(1LL<<rt1[i]);
1366 } else {
1367 alloc_reg(current,i,rt1[i]);
1368 current->is32|=1LL<<rt1[i];
1369 }
1370 dirty_reg(current,rt1[i]);
1371 }
1372 }
1373 if(opcode2[i]==0x3f) // DSRA32
1374 {
1375 if(rt1[i]) {
1376 alloc_reg64(current,i,rs1[i]);
1377 alloc_reg(current,i,rt1[i]);
1378 current->is32|=1LL<<rt1[i];
1379 dirty_reg(current,rt1[i]);
1380 }
1381 }
1382}
1383
1384void shift_alloc(struct regstat *current,int i)
1385{
1386 if(rt1[i]) {
1387 if(opcode2[i]<=0x07) // SLLV/SRLV/SRAV
1388 {
1389 if(rs1[i]) alloc_reg(current,i,rs1[i]);
1390 if(rs2[i]) alloc_reg(current,i,rs2[i]);
1391 alloc_reg(current,i,rt1[i]);
e1190b87 1392 if(rt1[i]==rs2[i]) {
1393 alloc_reg_temp(current,i,-1);
1394 minimum_free_regs[i]=1;
1395 }
57871462 1396 current->is32|=1LL<<rt1[i];
1397 } else { // DSLLV/DSRLV/DSRAV
1398 if(rs1[i]) alloc_reg64(current,i,rs1[i]);
1399 if(rs2[i]) alloc_reg(current,i,rs2[i]);
1400 alloc_reg64(current,i,rt1[i]);
1401 current->is32&=~(1LL<<rt1[i]);
1402 if(opcode2[i]==0x16||opcode2[i]==0x17) // DSRLV and DSRAV need a temporary register
e1190b87 1403 {
57871462 1404 alloc_reg_temp(current,i,-1);
e1190b87 1405 minimum_free_regs[i]=1;
1406 }
57871462 1407 }
1408 clear_const(current,rs1[i]);
1409 clear_const(current,rs2[i]);
1410 clear_const(current,rt1[i]);
1411 dirty_reg(current,rt1[i]);
1412 }
1413}
1414
1415void alu_alloc(struct regstat *current,int i)
1416{
1417 if(opcode2[i]>=0x20&&opcode2[i]<=0x23) { // ADD/ADDU/SUB/SUBU
1418 if(rt1[i]) {
1419 if(rs1[i]&&rs2[i]) {
1420 alloc_reg(current,i,rs1[i]);
1421 alloc_reg(current,i,rs2[i]);
1422 }
1423 else {
1424 if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1425 if(rs2[i]&&needed_again(rs2[i],i)) alloc_reg(current,i,rs2[i]);
1426 }
1427 alloc_reg(current,i,rt1[i]);
1428 }
1429 current->is32|=1LL<<rt1[i];
1430 }
1431 if(opcode2[i]==0x2a||opcode2[i]==0x2b) { // SLT/SLTU
1432 if(rt1[i]) {
1433 if(!((current->is32>>rs1[i])&(current->is32>>rs2[i])&1))
1434 {
1435 alloc_reg64(current,i,rs1[i]);
1436 alloc_reg64(current,i,rs2[i]);
1437 alloc_reg(current,i,rt1[i]);
1438 } else {
1439 alloc_reg(current,i,rs1[i]);
1440 alloc_reg(current,i,rs2[i]);
1441 alloc_reg(current,i,rt1[i]);
1442 }
1443 }
1444 current->is32|=1LL<<rt1[i];
1445 }
1446 if(opcode2[i]>=0x24&&opcode2[i]<=0x27) { // AND/OR/XOR/NOR
1447 if(rt1[i]) {
1448 if(rs1[i]&&rs2[i]) {
1449 alloc_reg(current,i,rs1[i]);
1450 alloc_reg(current,i,rs2[i]);
1451 }
1452 else
1453 {
1454 if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1455 if(rs2[i]&&needed_again(rs2[i],i)) alloc_reg(current,i,rs2[i]);
1456 }
1457 alloc_reg(current,i,rt1[i]);
1458 if(!((current->is32>>rs1[i])&(current->is32>>rs2[i])&1))
1459 {
1460 if(!((current->uu>>rt1[i])&1)) {
1461 alloc_reg64(current,i,rt1[i]);
1462 }
1463 if(get_reg(current->regmap,rt1[i]|64)>=0) {
1464 if(rs1[i]&&rs2[i]) {
1465 alloc_reg64(current,i,rs1[i]);
1466 alloc_reg64(current,i,rs2[i]);
1467 }
1468 else
1469 {
1470 // Is is really worth it to keep 64-bit values in registers?
1471 #ifdef NATIVE_64BIT
1472 if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg64(current,i,rs1[i]);
1473 if(rs2[i]&&needed_again(rs2[i],i)) alloc_reg64(current,i,rs2[i]);
1474 #endif
1475 }
1476 }
1477 current->is32&=~(1LL<<rt1[i]);
1478 } else {
1479 current->is32|=1LL<<rt1[i];
1480 }
1481 }
1482 }
1483 if(opcode2[i]>=0x2c&&opcode2[i]<=0x2f) { // DADD/DADDU/DSUB/DSUBU
1484 if(rt1[i]) {
1485 if(rs1[i]&&rs2[i]) {
1486 if(!((current->uu>>rt1[i])&1)||get_reg(current->regmap,rt1[i]|64)>=0) {
1487 alloc_reg64(current,i,rs1[i]);
1488 alloc_reg64(current,i,rs2[i]);
1489 alloc_reg64(current,i,rt1[i]);
1490 } else {
1491 alloc_reg(current,i,rs1[i]);
1492 alloc_reg(current,i,rs2[i]);
1493 alloc_reg(current,i,rt1[i]);
1494 }
1495 }
1496 else {
1497 alloc_reg(current,i,rt1[i]);
1498 if(!((current->uu>>rt1[i])&1)||get_reg(current->regmap,rt1[i]|64)>=0) {
1499 // DADD used as move, or zeroing
1500 // If we have a 64-bit source, then make the target 64 bits too
1501 if(rs1[i]&&!((current->is32>>rs1[i])&1)) {
1502 if(get_reg(current->regmap,rs1[i])>=0) alloc_reg64(current,i,rs1[i]);
1503 alloc_reg64(current,i,rt1[i]);
1504 } else if(rs2[i]&&!((current->is32>>rs2[i])&1)) {
1505 if(get_reg(current->regmap,rs2[i])>=0) alloc_reg64(current,i,rs2[i]);
1506 alloc_reg64(current,i,rt1[i]);
1507 }
1508 if(opcode2[i]>=0x2e&&rs2[i]) {
1509 // DSUB used as negation - 64-bit result
1510 // If we have a 32-bit register, extend it to 64 bits
1511 if(get_reg(current->regmap,rs2[i])>=0) alloc_reg64(current,i,rs2[i]);
1512 alloc_reg64(current,i,rt1[i]);
1513 }
1514 }
1515 }
1516 if(rs1[i]&&rs2[i]) {
1517 current->is32&=~(1LL<<rt1[i]);
1518 } else if(rs1[i]) {
1519 current->is32&=~(1LL<<rt1[i]);
1520 if((current->is32>>rs1[i])&1)
1521 current->is32|=1LL<<rt1[i];
1522 } else if(rs2[i]) {
1523 current->is32&=~(1LL<<rt1[i]);
1524 if((current->is32>>rs2[i])&1)
1525 current->is32|=1LL<<rt1[i];
1526 } else {
1527 current->is32|=1LL<<rt1[i];
1528 }
1529 }
1530 }
1531 clear_const(current,rs1[i]);
1532 clear_const(current,rs2[i]);
1533 clear_const(current,rt1[i]);
1534 dirty_reg(current,rt1[i]);
1535}
1536
1537void imm16_alloc(struct regstat *current,int i)
1538{
1539 if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1540 else lt1[i]=rs1[i];
1541 if(rt1[i]) alloc_reg(current,i,rt1[i]);
1542 if(opcode[i]==0x18||opcode[i]==0x19) { // DADDI/DADDIU
1543 current->is32&=~(1LL<<rt1[i]);
1544 if(!((current->uu>>rt1[i])&1)||get_reg(current->regmap,rt1[i]|64)>=0) {
1545 // TODO: Could preserve the 32-bit flag if the immediate is zero
1546 alloc_reg64(current,i,rt1[i]);
1547 alloc_reg64(current,i,rs1[i]);
1548 }
1549 clear_const(current,rs1[i]);
1550 clear_const(current,rt1[i]);
1551 }
1552 else if(opcode[i]==0x0a||opcode[i]==0x0b) { // SLTI/SLTIU
1553 if((~current->is32>>rs1[i])&1) alloc_reg64(current,i,rs1[i]);
1554 current->is32|=1LL<<rt1[i];
1555 clear_const(current,rs1[i]);
1556 clear_const(current,rt1[i]);
1557 }
1558 else if(opcode[i]>=0x0c&&opcode[i]<=0x0e) { // ANDI/ORI/XORI
1559 if(((~current->is32>>rs1[i])&1)&&opcode[i]>0x0c) {
1560 if(rs1[i]!=rt1[i]) {
1561 if(needed_again(rs1[i],i)) alloc_reg64(current,i,rs1[i]);
1562 alloc_reg64(current,i,rt1[i]);
1563 current->is32&=~(1LL<<rt1[i]);
1564 }
1565 }
1566 else current->is32|=1LL<<rt1[i]; // ANDI clears upper bits
1567 if(is_const(current,rs1[i])) {
1568 int v=get_const(current,rs1[i]);
1569 if(opcode[i]==0x0c) set_const(current,rt1[i],v&imm[i]);
1570 if(opcode[i]==0x0d) set_const(current,rt1[i],v|imm[i]);
1571 if(opcode[i]==0x0e) set_const(current,rt1[i],v^imm[i]);
1572 }
1573 else clear_const(current,rt1[i]);
1574 }
1575 else if(opcode[i]==0x08||opcode[i]==0x09) { // ADDI/ADDIU
1576 if(is_const(current,rs1[i])) {
1577 int v=get_const(current,rs1[i]);
1578 set_const(current,rt1[i],v+imm[i]);
1579 }
1580 else clear_const(current,rt1[i]);
1581 current->is32|=1LL<<rt1[i];
1582 }
1583 else {
1584 set_const(current,rt1[i],((long long)((short)imm[i]))<<16); // LUI
1585 current->is32|=1LL<<rt1[i];
1586 }
1587 dirty_reg(current,rt1[i]);
1588}
1589
1590void load_alloc(struct regstat *current,int i)
1591{
1592 clear_const(current,rt1[i]);
1593 //if(rs1[i]!=rt1[i]&&needed_again(rs1[i],i)) clear_const(current,rs1[i]); // Does this help or hurt?
1594 if(!rs1[i]) current->u&=~1LL; // Allow allocating r0 if it's the source register
1595 if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
373d1d07 1596 if(rt1[i]&&!((current->u>>rt1[i])&1)) {
57871462 1597 alloc_reg(current,i,rt1[i]);
373d1d07 1598 assert(get_reg(current->regmap,rt1[i])>=0);
57871462 1599 if(opcode[i]==0x27||opcode[i]==0x37) // LWU/LD
1600 {
1601 current->is32&=~(1LL<<rt1[i]);
1602 alloc_reg64(current,i,rt1[i]);
1603 }
1604 else if(opcode[i]==0x1A||opcode[i]==0x1B) // LDL/LDR
1605 {
1606 current->is32&=~(1LL<<rt1[i]);
1607 alloc_reg64(current,i,rt1[i]);
1608 alloc_all(current,i);
1609 alloc_reg64(current,i,FTEMP);
e1190b87 1610 minimum_free_regs[i]=HOST_REGS;
57871462 1611 }
1612 else current->is32|=1LL<<rt1[i];
1613 dirty_reg(current,rt1[i]);
1614 // If using TLB, need a register for pointer to the mapping table
1615 if(using_tlb) alloc_reg(current,i,TLREG);
1616 // LWL/LWR need a temporary register for the old value
1617 if(opcode[i]==0x22||opcode[i]==0x26)
1618 {
1619 alloc_reg(current,i,FTEMP);
1620 alloc_reg_temp(current,i,-1);
e1190b87 1621 minimum_free_regs[i]=1;
57871462 1622 }
1623 }
1624 else
1625 {
373d1d07 1626 // Load to r0 or unneeded register (dummy load)
57871462 1627 // but we still need a register to calculate the address
535d208a 1628 if(opcode[i]==0x22||opcode[i]==0x26)
1629 {
1630 alloc_reg(current,i,FTEMP); // LWL/LWR need another temporary
1631 }
373d1d07 1632 // If using TLB, need a register for pointer to the mapping table
1633 if(using_tlb) alloc_reg(current,i,TLREG);
57871462 1634 alloc_reg_temp(current,i,-1);
e1190b87 1635 minimum_free_regs[i]=1;
535d208a 1636 if(opcode[i]==0x1A||opcode[i]==0x1B) // LDL/LDR
1637 {
1638 alloc_all(current,i);
1639 alloc_reg64(current,i,FTEMP);
e1190b87 1640 minimum_free_regs[i]=HOST_REGS;
535d208a 1641 }
57871462 1642 }
1643}
1644
1645void store_alloc(struct regstat *current,int i)
1646{
1647 clear_const(current,rs2[i]);
1648 if(!(rs2[i])) current->u&=~1LL; // Allow allocating r0 if necessary
1649 if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1650 alloc_reg(current,i,rs2[i]);
1651 if(opcode[i]==0x2c||opcode[i]==0x2d||opcode[i]==0x3f) { // 64-bit SDL/SDR/SD
1652 alloc_reg64(current,i,rs2[i]);
1653 if(rs2[i]) alloc_reg(current,i,FTEMP);
1654 }
1655 // If using TLB, need a register for pointer to the mapping table
1656 if(using_tlb) alloc_reg(current,i,TLREG);
1657 #if defined(HOST_IMM8)
1658 // On CPUs without 32-bit immediates we need a pointer to invalid_code
1659 else alloc_reg(current,i,INVCP);
1660 #endif
b7918751 1661 if(opcode[i]==0x2a||opcode[i]==0x2e||opcode[i]==0x2c||opcode[i]==0x2d) { // SWL/SWL/SDL/SDR
57871462 1662 alloc_reg(current,i,FTEMP);
1663 }
1664 // We need a temporary register for address generation
1665 alloc_reg_temp(current,i,-1);
e1190b87 1666 minimum_free_regs[i]=1;
57871462 1667}
1668
1669void c1ls_alloc(struct regstat *current,int i)
1670{
1671 //clear_const(current,rs1[i]); // FIXME
1672 clear_const(current,rt1[i]);
1673 if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1674 alloc_reg(current,i,CSREG); // Status
1675 alloc_reg(current,i,FTEMP);
1676 if(opcode[i]==0x35||opcode[i]==0x3d) { // 64-bit LDC1/SDC1
1677 alloc_reg64(current,i,FTEMP);
1678 }
1679 // If using TLB, need a register for pointer to the mapping table
1680 if(using_tlb) alloc_reg(current,i,TLREG);
1681 #if defined(HOST_IMM8)
1682 // On CPUs without 32-bit immediates we need a pointer to invalid_code
1683 else if((opcode[i]&0x3b)==0x39) // SWC1/SDC1
1684 alloc_reg(current,i,INVCP);
1685 #endif
1686 // We need a temporary register for address generation
1687 alloc_reg_temp(current,i,-1);
1688}
1689
b9b61529 1690void c2ls_alloc(struct regstat *current,int i)
1691{
1692 clear_const(current,rt1[i]);
1693 if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1694 alloc_reg(current,i,FTEMP);
1695 // If using TLB, need a register for pointer to the mapping table
1696 if(using_tlb) alloc_reg(current,i,TLREG);
1697 #if defined(HOST_IMM8)
1698 // On CPUs without 32-bit immediates we need a pointer to invalid_code
1699 else if((opcode[i]&0x3b)==0x3a) // SWC2/SDC2
1700 alloc_reg(current,i,INVCP);
1701 #endif
1702 // We need a temporary register for address generation
1703 alloc_reg_temp(current,i,-1);
e1190b87 1704 minimum_free_regs[i]=1;
b9b61529 1705}
1706
57871462 1707#ifndef multdiv_alloc
1708void multdiv_alloc(struct regstat *current,int i)
1709{
1710 // case 0x18: MULT
1711 // case 0x19: MULTU
1712 // case 0x1A: DIV
1713 // case 0x1B: DIVU
1714 // case 0x1C: DMULT
1715 // case 0x1D: DMULTU
1716 // case 0x1E: DDIV
1717 // case 0x1F: DDIVU
1718 clear_const(current,rs1[i]);
1719 clear_const(current,rs2[i]);
1720 if(rs1[i]&&rs2[i])
1721 {
1722 if((opcode2[i]&4)==0) // 32-bit
1723 {
1724 current->u&=~(1LL<<HIREG);
1725 current->u&=~(1LL<<LOREG);
1726 alloc_reg(current,i,HIREG);
1727 alloc_reg(current,i,LOREG);
1728 alloc_reg(current,i,rs1[i]);
1729 alloc_reg(current,i,rs2[i]);
1730 current->is32|=1LL<<HIREG;
1731 current->is32|=1LL<<LOREG;
1732 dirty_reg(current,HIREG);
1733 dirty_reg(current,LOREG);
1734 }
1735 else // 64-bit
1736 {
1737 current->u&=~(1LL<<HIREG);
1738 current->u&=~(1LL<<LOREG);
1739 current->uu&=~(1LL<<HIREG);
1740 current->uu&=~(1LL<<LOREG);
1741 alloc_reg64(current,i,HIREG);
1742 //if(HOST_REGS>10) alloc_reg64(current,i,LOREG);
1743 alloc_reg64(current,i,rs1[i]);
1744 alloc_reg64(current,i,rs2[i]);
1745 alloc_all(current,i);
1746 current->is32&=~(1LL<<HIREG);
1747 current->is32&=~(1LL<<LOREG);
1748 dirty_reg(current,HIREG);
1749 dirty_reg(current,LOREG);
e1190b87 1750 minimum_free_regs[i]=HOST_REGS;
57871462 1751 }
1752 }
1753 else
1754 {
1755 // Multiply by zero is zero.
1756 // MIPS does not have a divide by zero exception.
1757 // The result is undefined, we return zero.
1758 alloc_reg(current,i,HIREG);
1759 alloc_reg(current,i,LOREG);
1760 current->is32|=1LL<<HIREG;
1761 current->is32|=1LL<<LOREG;
1762 dirty_reg(current,HIREG);
1763 dirty_reg(current,LOREG);
1764 }
1765}
1766#endif
1767
1768void cop0_alloc(struct regstat *current,int i)
1769{
1770 if(opcode2[i]==0) // MFC0
1771 {
1772 if(rt1[i]) {
1773 clear_const(current,rt1[i]);
1774 alloc_all(current,i);
1775 alloc_reg(current,i,rt1[i]);
1776 current->is32|=1LL<<rt1[i];
1777 dirty_reg(current,rt1[i]);
1778 }
1779 }
1780 else if(opcode2[i]==4) // MTC0
1781 {
1782 if(rs1[i]){
1783 clear_const(current,rs1[i]);
1784 alloc_reg(current,i,rs1[i]);
1785 alloc_all(current,i);
1786 }
1787 else {
1788 alloc_all(current,i); // FIXME: Keep r0
1789 current->u&=~1LL;
1790 alloc_reg(current,i,0);
1791 }
1792 }
1793 else
1794 {
1795 // TLBR/TLBWI/TLBWR/TLBP/ERET
1796 assert(opcode2[i]==0x10);
1797 alloc_all(current,i);
1798 }
e1190b87 1799 minimum_free_regs[i]=HOST_REGS;
57871462 1800}
1801
1802void cop1_alloc(struct regstat *current,int i)
1803{
1804 alloc_reg(current,i,CSREG); // Load status
1805 if(opcode2[i]<3) // MFC1/DMFC1/CFC1
1806 {
7de557a6 1807 if(rt1[i]){
1808 clear_const(current,rt1[i]);
1809 if(opcode2[i]==1) {
1810 alloc_reg64(current,i,rt1[i]); // DMFC1
1811 current->is32&=~(1LL<<rt1[i]);
1812 }else{
1813 alloc_reg(current,i,rt1[i]); // MFC1/CFC1
1814 current->is32|=1LL<<rt1[i];
1815 }
1816 dirty_reg(current,rt1[i]);
57871462 1817 }
57871462 1818 alloc_reg_temp(current,i,-1);
1819 }
1820 else if(opcode2[i]>3) // MTC1/DMTC1/CTC1
1821 {
1822 if(rs1[i]){
1823 clear_const(current,rs1[i]);
1824 if(opcode2[i]==5)
1825 alloc_reg64(current,i,rs1[i]); // DMTC1
1826 else
1827 alloc_reg(current,i,rs1[i]); // MTC1/CTC1
1828 alloc_reg_temp(current,i,-1);
1829 }
1830 else {
1831 current->u&=~1LL;
1832 alloc_reg(current,i,0);
1833 alloc_reg_temp(current,i,-1);
1834 }
1835 }
e1190b87 1836 minimum_free_regs[i]=1;
57871462 1837}
1838void fconv_alloc(struct regstat *current,int i)
1839{
1840 alloc_reg(current,i,CSREG); // Load status
1841 alloc_reg_temp(current,i,-1);
e1190b87 1842 minimum_free_regs[i]=1;
57871462 1843}
1844void float_alloc(struct regstat *current,int i)
1845{
1846 alloc_reg(current,i,CSREG); // Load status
1847 alloc_reg_temp(current,i,-1);
e1190b87 1848 minimum_free_regs[i]=1;
57871462 1849}
b9b61529 1850void c2op_alloc(struct regstat *current,int i)
1851{
1852 alloc_reg_temp(current,i,-1);
1853}
57871462 1854void fcomp_alloc(struct regstat *current,int i)
1855{
1856 alloc_reg(current,i,CSREG); // Load status
1857 alloc_reg(current,i,FSREG); // Load flags
1858 dirty_reg(current,FSREG); // Flag will be modified
1859 alloc_reg_temp(current,i,-1);
e1190b87 1860 minimum_free_regs[i]=1;
57871462 1861}
1862
1863void syscall_alloc(struct regstat *current,int i)
1864{
1865 alloc_cc(current,i);
1866 dirty_reg(current,CCREG);
1867 alloc_all(current,i);
e1190b87 1868 minimum_free_regs[i]=HOST_REGS;
57871462 1869 current->isconst=0;
1870}
1871
1872void delayslot_alloc(struct regstat *current,int i)
1873{
1874 switch(itype[i]) {
1875 case UJUMP:
1876 case CJUMP:
1877 case SJUMP:
1878 case RJUMP:
1879 case FJUMP:
1880 case SYSCALL:
7139f3c8 1881 case HLECALL:
57871462 1882 case SPAN:
1883 assem_debug("jump in the delay slot. this shouldn't happen.\n");//exit(1);
1884 printf("Disabled speculative precompilation\n");
1885 stop_after_jal=1;
1886 break;
1887 case IMM16:
1888 imm16_alloc(current,i);
1889 break;
1890 case LOAD:
1891 case LOADLR:
1892 load_alloc(current,i);
1893 break;
1894 case STORE:
1895 case STORELR:
1896 store_alloc(current,i);
1897 break;
1898 case ALU:
1899 alu_alloc(current,i);
1900 break;
1901 case SHIFT:
1902 shift_alloc(current,i);
1903 break;
1904 case MULTDIV:
1905 multdiv_alloc(current,i);
1906 break;
1907 case SHIFTIMM:
1908 shiftimm_alloc(current,i);
1909 break;
1910 case MOV:
1911 mov_alloc(current,i);
1912 break;
1913 case COP0:
1914 cop0_alloc(current,i);
1915 break;
1916 case COP1:
b9b61529 1917 case COP2:
57871462 1918 cop1_alloc(current,i);
1919 break;
1920 case C1LS:
1921 c1ls_alloc(current,i);
1922 break;
b9b61529 1923 case C2LS:
1924 c2ls_alloc(current,i);
1925 break;
57871462 1926 case FCONV:
1927 fconv_alloc(current,i);
1928 break;
1929 case FLOAT:
1930 float_alloc(current,i);
1931 break;
1932 case FCOMP:
1933 fcomp_alloc(current,i);
1934 break;
b9b61529 1935 case C2OP:
1936 c2op_alloc(current,i);
1937 break;
57871462 1938 }
1939}
1940
1941// Special case where a branch and delay slot span two pages in virtual memory
1942static void pagespan_alloc(struct regstat *current,int i)
1943{
1944 current->isconst=0;
1945 current->wasconst=0;
1946 regs[i].wasconst=0;
e1190b87 1947 minimum_free_regs[i]=HOST_REGS;
57871462 1948 alloc_all(current,i);
1949 alloc_cc(current,i);
1950 dirty_reg(current,CCREG);
1951 if(opcode[i]==3) // JAL
1952 {
1953 alloc_reg(current,i,31);
1954 dirty_reg(current,31);
1955 }
1956 if(opcode[i]==0&&(opcode2[i]&0x3E)==8) // JR/JALR
1957 {
1958 alloc_reg(current,i,rs1[i]);
5067f341 1959 if (rt1[i]!=0) {
1960 alloc_reg(current,i,rt1[i]);
1961 dirty_reg(current,rt1[i]);
57871462 1962 }
1963 }
1964 if((opcode[i]&0x2E)==4) // BEQ/BNE/BEQL/BNEL
1965 {
1966 if(rs1[i]) alloc_reg(current,i,rs1[i]);
1967 if(rs2[i]) alloc_reg(current,i,rs2[i]);
1968 if(!((current->is32>>rs1[i])&(current->is32>>rs2[i])&1))
1969 {
1970 if(rs1[i]) alloc_reg64(current,i,rs1[i]);
1971 if(rs2[i]) alloc_reg64(current,i,rs2[i]);
1972 }
1973 }
1974 else
1975 if((opcode[i]&0x2E)==6) // BLEZ/BGTZ/BLEZL/BGTZL
1976 {
1977 if(rs1[i]) alloc_reg(current,i,rs1[i]);
1978 if(!((current->is32>>rs1[i])&1))
1979 {
1980 if(rs1[i]) alloc_reg64(current,i,rs1[i]);
1981 }
1982 }
1983 else
1984 if(opcode[i]==0x11) // BC1
1985 {
1986 alloc_reg(current,i,FSREG);
1987 alloc_reg(current,i,CSREG);
1988 }
1989 //else ...
1990}
1991
1992add_stub(int type,int addr,int retaddr,int a,int b,int c,int d,int e)
1993{
1994 stubs[stubcount][0]=type;
1995 stubs[stubcount][1]=addr;
1996 stubs[stubcount][2]=retaddr;
1997 stubs[stubcount][3]=a;
1998 stubs[stubcount][4]=b;
1999 stubs[stubcount][5]=c;
2000 stubs[stubcount][6]=d;
2001 stubs[stubcount][7]=e;
2002 stubcount++;
2003}
2004
2005// Write out a single register
2006void wb_register(signed char r,signed char regmap[],uint64_t dirty,uint64_t is32)
2007{
2008 int hr;
2009 for(hr=0;hr<HOST_REGS;hr++) {
2010 if(hr!=EXCLUDE_REG) {
2011 if((regmap[hr]&63)==r) {
2012 if((dirty>>hr)&1) {
2013 if(regmap[hr]<64) {
2014 emit_storereg(r,hr);
24385cae 2015#ifndef FORCE32
57871462 2016 if((is32>>regmap[hr])&1) {
2017 emit_sarimm(hr,31,hr);
2018 emit_storereg(r|64,hr);
2019 }
24385cae 2020#endif
57871462 2021 }else{
2022 emit_storereg(r|64,hr);
2023 }
2024 }
2025 }
2026 }
2027 }
2028}
2029
2030int mchecksum()
2031{
2032 //if(!tracedebug) return 0;
2033 int i;
2034 int sum=0;
2035 for(i=0;i<2097152;i++) {
2036 unsigned int temp=sum;
2037 sum<<=1;
2038 sum|=(~temp)>>31;
2039 sum^=((u_int *)rdram)[i];
2040 }
2041 return sum;
2042}
2043int rchecksum()
2044{
2045 int i;
2046 int sum=0;
2047 for(i=0;i<64;i++)
2048 sum^=((u_int *)reg)[i];
2049 return sum;
2050}
57871462 2051void rlist()
2052{
2053 int i;
2054 printf("TRACE: ");
2055 for(i=0;i<32;i++)
2056 printf("r%d:%8x%8x ",i,((int *)(reg+i))[1],((int *)(reg+i))[0]);
2057 printf("\n");
3d624f89 2058#ifndef DISABLE_COP1
57871462 2059 printf("TRACE: ");
2060 for(i=0;i<32;i++)
2061 printf("f%d:%8x%8x ",i,((int*)reg_cop1_simple[i])[1],*((int*)reg_cop1_simple[i]));
2062 printf("\n");
3d624f89 2063#endif
57871462 2064}
2065
2066void enabletrace()
2067{
2068 tracedebug=1;
2069}
2070
2071void memdebug(int i)
2072{
2073 //printf("TRACE: count=%d next=%d (checksum %x) lo=%8x%8x\n",Count,next_interupt,mchecksum(),(int)(reg[LOREG]>>32),(int)reg[LOREG]);
2074 //printf("TRACE: count=%d next=%d (rchecksum %x)\n",Count,next_interupt,rchecksum());
2075 //rlist();
2076 //if(tracedebug) {
2077 //if(Count>=-2084597794) {
2078 if((signed int)Count>=-2084597794&&(signed int)Count<0) {
2079 //if(0) {
2080 printf("TRACE: count=%d next=%d (checksum %x)\n",Count,next_interupt,mchecksum());
2081 //printf("TRACE: count=%d next=%d (checksum %x) Status=%x\n",Count,next_interupt,mchecksum(),Status);
2082 //printf("TRACE: count=%d next=%d (checksum %x) hi=%8x%8x\n",Count,next_interupt,mchecksum(),(int)(reg[HIREG]>>32),(int)reg[HIREG]);
2083 rlist();
2084 #ifdef __i386__
2085 printf("TRACE: %x\n",(&i)[-1]);
2086 #endif
2087 #ifdef __arm__
2088 int j;
2089 printf("TRACE: %x \n",(&j)[10]);
2090 printf("TRACE: %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x\n",(&j)[1],(&j)[2],(&j)[3],(&j)[4],(&j)[5],(&j)[6],(&j)[7],(&j)[8],(&j)[9],(&j)[10],(&j)[11],(&j)[12],(&j)[13],(&j)[14],(&j)[15],(&j)[16],(&j)[17],(&j)[18],(&j)[19],(&j)[20]);
2091 #endif
2092 //fflush(stdout);
2093 }
2094 //printf("TRACE: %x\n",(&i)[-1]);
2095}
2096
2097void tlb_debug(u_int cause, u_int addr, u_int iaddr)
2098{
2099 printf("TLB Exception: instruction=%x addr=%x cause=%x\n",iaddr, addr, cause);
2100}
2101
2102void alu_assemble(int i,struct regstat *i_regs)
2103{
2104 if(opcode2[i]>=0x20&&opcode2[i]<=0x23) { // ADD/ADDU/SUB/SUBU
2105 if(rt1[i]) {
2106 signed char s1,s2,t;
2107 t=get_reg(i_regs->regmap,rt1[i]);
2108 if(t>=0) {
2109 s1=get_reg(i_regs->regmap,rs1[i]);
2110 s2=get_reg(i_regs->regmap,rs2[i]);
2111 if(rs1[i]&&rs2[i]) {
2112 assert(s1>=0);
2113 assert(s2>=0);
2114 if(opcode2[i]&2) emit_sub(s1,s2,t);
2115 else emit_add(s1,s2,t);
2116 }
2117 else if(rs1[i]) {
2118 if(s1>=0) emit_mov(s1,t);
2119 else emit_loadreg(rs1[i],t);
2120 }
2121 else if(rs2[i]) {
2122 if(s2>=0) {
2123 if(opcode2[i]&2) emit_neg(s2,t);
2124 else emit_mov(s2,t);
2125 }
2126 else {
2127 emit_loadreg(rs2[i],t);
2128 if(opcode2[i]&2) emit_neg(t,t);
2129 }
2130 }
2131 else emit_zeroreg(t);
2132 }
2133 }
2134 }
2135 if(opcode2[i]>=0x2c&&opcode2[i]<=0x2f) { // DADD/DADDU/DSUB/DSUBU
2136 if(rt1[i]) {
2137 signed char s1l,s2l,s1h,s2h,tl,th;
2138 tl=get_reg(i_regs->regmap,rt1[i]);
2139 th=get_reg(i_regs->regmap,rt1[i]|64);
2140 if(tl>=0) {
2141 s1l=get_reg(i_regs->regmap,rs1[i]);
2142 s2l=get_reg(i_regs->regmap,rs2[i]);
2143 s1h=get_reg(i_regs->regmap,rs1[i]|64);
2144 s2h=get_reg(i_regs->regmap,rs2[i]|64);
2145 if(rs1[i]&&rs2[i]) {
2146 assert(s1l>=0);
2147 assert(s2l>=0);
2148 if(opcode2[i]&2) emit_subs(s1l,s2l,tl);
2149 else emit_adds(s1l,s2l,tl);
2150 if(th>=0) {
2151 #ifdef INVERTED_CARRY
2152 if(opcode2[i]&2) {if(s1h!=th) emit_mov(s1h,th);emit_sbb(th,s2h);}
2153 #else
2154 if(opcode2[i]&2) emit_sbc(s1h,s2h,th);
2155 #endif
2156 else emit_add(s1h,s2h,th);
2157 }
2158 }
2159 else if(rs1[i]) {
2160 if(s1l>=0) emit_mov(s1l,tl);
2161 else emit_loadreg(rs1[i],tl);
2162 if(th>=0) {
2163 if(s1h>=0) emit_mov(s1h,th);
2164 else emit_loadreg(rs1[i]|64,th);
2165 }
2166 }
2167 else if(rs2[i]) {
2168 if(s2l>=0) {
2169 if(opcode2[i]&2) emit_negs(s2l,tl);
2170 else emit_mov(s2l,tl);
2171 }
2172 else {
2173 emit_loadreg(rs2[i],tl);
2174 if(opcode2[i]&2) emit_negs(tl,tl);
2175 }
2176 if(th>=0) {
2177 #ifdef INVERTED_CARRY
2178 if(s2h>=0) emit_mov(s2h,th);
2179 else emit_loadreg(rs2[i]|64,th);
2180 if(opcode2[i]&2) {
2181 emit_adcimm(-1,th); // x86 has inverted carry flag
2182 emit_not(th,th);
2183 }
2184 #else
2185 if(opcode2[i]&2) {
2186 if(s2h>=0) emit_rscimm(s2h,0,th);
2187 else {
2188 emit_loadreg(rs2[i]|64,th);
2189 emit_rscimm(th,0,th);
2190 }
2191 }else{
2192 if(s2h>=0) emit_mov(s2h,th);
2193 else emit_loadreg(rs2[i]|64,th);
2194 }
2195 #endif
2196 }
2197 }
2198 else {
2199 emit_zeroreg(tl);
2200 if(th>=0) emit_zeroreg(th);
2201 }
2202 }
2203 }
2204 }
2205 if(opcode2[i]==0x2a||opcode2[i]==0x2b) { // SLT/SLTU
2206 if(rt1[i]) {
2207 signed char s1l,s1h,s2l,s2h,t;
2208 if(!((i_regs->was32>>rs1[i])&(i_regs->was32>>rs2[i])&1))
2209 {
2210 t=get_reg(i_regs->regmap,rt1[i]);
2211 //assert(t>=0);
2212 if(t>=0) {
2213 s1l=get_reg(i_regs->regmap,rs1[i]);
2214 s1h=get_reg(i_regs->regmap,rs1[i]|64);
2215 s2l=get_reg(i_regs->regmap,rs2[i]);
2216 s2h=get_reg(i_regs->regmap,rs2[i]|64);
2217 if(rs2[i]==0) // rx<r0
2218 {
2219 assert(s1h>=0);
2220 if(opcode2[i]==0x2a) // SLT
2221 emit_shrimm(s1h,31,t);
2222 else // SLTU (unsigned can not be less than zero)
2223 emit_zeroreg(t);
2224 }
2225 else if(rs1[i]==0) // r0<rx
2226 {
2227 assert(s2h>=0);
2228 if(opcode2[i]==0x2a) // SLT
2229 emit_set_gz64_32(s2h,s2l,t);
2230 else // SLTU (set if not zero)
2231 emit_set_nz64_32(s2h,s2l,t);
2232 }
2233 else {
2234 assert(s1l>=0);assert(s1h>=0);
2235 assert(s2l>=0);assert(s2h>=0);
2236 if(opcode2[i]==0x2a) // SLT
2237 emit_set_if_less64_32(s1h,s1l,s2h,s2l,t);
2238 else // SLTU
2239 emit_set_if_carry64_32(s1h,s1l,s2h,s2l,t);
2240 }
2241 }
2242 } else {
2243 t=get_reg(i_regs->regmap,rt1[i]);
2244 //assert(t>=0);
2245 if(t>=0) {
2246 s1l=get_reg(i_regs->regmap,rs1[i]);
2247 s2l=get_reg(i_regs->regmap,rs2[i]);
2248 if(rs2[i]==0) // rx<r0
2249 {
2250 assert(s1l>=0);
2251 if(opcode2[i]==0x2a) // SLT
2252 emit_shrimm(s1l,31,t);
2253 else // SLTU (unsigned can not be less than zero)
2254 emit_zeroreg(t);
2255 }
2256 else if(rs1[i]==0) // r0<rx
2257 {
2258 assert(s2l>=0);
2259 if(opcode2[i]==0x2a) // SLT
2260 emit_set_gz32(s2l,t);
2261 else // SLTU (set if not zero)
2262 emit_set_nz32(s2l,t);
2263 }
2264 else{
2265 assert(s1l>=0);assert(s2l>=0);
2266 if(opcode2[i]==0x2a) // SLT
2267 emit_set_if_less32(s1l,s2l,t);
2268 else // SLTU
2269 emit_set_if_carry32(s1l,s2l,t);
2270 }
2271 }
2272 }
2273 }
2274 }
2275 if(opcode2[i]>=0x24&&opcode2[i]<=0x27) { // AND/OR/XOR/NOR
2276 if(rt1[i]) {
2277 signed char s1l,s1h,s2l,s2h,th,tl;
2278 tl=get_reg(i_regs->regmap,rt1[i]);
2279 th=get_reg(i_regs->regmap,rt1[i]|64);
2280 if(!((i_regs->was32>>rs1[i])&(i_regs->was32>>rs2[i])&1)&&th>=0)
2281 {
2282 assert(tl>=0);
2283 if(tl>=0) {
2284 s1l=get_reg(i_regs->regmap,rs1[i]);
2285 s1h=get_reg(i_regs->regmap,rs1[i]|64);
2286 s2l=get_reg(i_regs->regmap,rs2[i]);
2287 s2h=get_reg(i_regs->regmap,rs2[i]|64);
2288 if(rs1[i]&&rs2[i]) {
2289 assert(s1l>=0);assert(s1h>=0);
2290 assert(s2l>=0);assert(s2h>=0);
2291 if(opcode2[i]==0x24) { // AND
2292 emit_and(s1l,s2l,tl);
2293 emit_and(s1h,s2h,th);
2294 } else
2295 if(opcode2[i]==0x25) { // OR
2296 emit_or(s1l,s2l,tl);
2297 emit_or(s1h,s2h,th);
2298 } else
2299 if(opcode2[i]==0x26) { // XOR
2300 emit_xor(s1l,s2l,tl);
2301 emit_xor(s1h,s2h,th);
2302 } else
2303 if(opcode2[i]==0x27) { // NOR
2304 emit_or(s1l,s2l,tl);
2305 emit_or(s1h,s2h,th);
2306 emit_not(tl,tl);
2307 emit_not(th,th);
2308 }
2309 }
2310 else
2311 {
2312 if(opcode2[i]==0x24) { // AND
2313 emit_zeroreg(tl);
2314 emit_zeroreg(th);
2315 } else
2316 if(opcode2[i]==0x25||opcode2[i]==0x26) { // OR/XOR
2317 if(rs1[i]){
2318 if(s1l>=0) emit_mov(s1l,tl);
2319 else emit_loadreg(rs1[i],tl);
2320 if(s1h>=0) emit_mov(s1h,th);
2321 else emit_loadreg(rs1[i]|64,th);
2322 }
2323 else
2324 if(rs2[i]){
2325 if(s2l>=0) emit_mov(s2l,tl);
2326 else emit_loadreg(rs2[i],tl);
2327 if(s2h>=0) emit_mov(s2h,th);
2328 else emit_loadreg(rs2[i]|64,th);
2329 }
2330 else{
2331 emit_zeroreg(tl);
2332 emit_zeroreg(th);
2333 }
2334 } else
2335 if(opcode2[i]==0x27) { // NOR
2336 if(rs1[i]){
2337 if(s1l>=0) emit_not(s1l,tl);
2338 else{
2339 emit_loadreg(rs1[i],tl);
2340 emit_not(tl,tl);
2341 }
2342 if(s1h>=0) emit_not(s1h,th);
2343 else{
2344 emit_loadreg(rs1[i]|64,th);
2345 emit_not(th,th);
2346 }
2347 }
2348 else
2349 if(rs2[i]){
2350 if(s2l>=0) emit_not(s2l,tl);
2351 else{
2352 emit_loadreg(rs2[i],tl);
2353 emit_not(tl,tl);
2354 }
2355 if(s2h>=0) emit_not(s2h,th);
2356 else{
2357 emit_loadreg(rs2[i]|64,th);
2358 emit_not(th,th);
2359 }
2360 }
2361 else {
2362 emit_movimm(-1,tl);
2363 emit_movimm(-1,th);
2364 }
2365 }
2366 }
2367 }
2368 }
2369 else
2370 {
2371 // 32 bit
2372 if(tl>=0) {
2373 s1l=get_reg(i_regs->regmap,rs1[i]);
2374 s2l=get_reg(i_regs->regmap,rs2[i]);
2375 if(rs1[i]&&rs2[i]) {
2376 assert(s1l>=0);
2377 assert(s2l>=0);
2378 if(opcode2[i]==0x24) { // AND
2379 emit_and(s1l,s2l,tl);
2380 } else
2381 if(opcode2[i]==0x25) { // OR
2382 emit_or(s1l,s2l,tl);
2383 } else
2384 if(opcode2[i]==0x26) { // XOR
2385 emit_xor(s1l,s2l,tl);
2386 } else
2387 if(opcode2[i]==0x27) { // NOR
2388 emit_or(s1l,s2l,tl);
2389 emit_not(tl,tl);
2390 }
2391 }
2392 else
2393 {
2394 if(opcode2[i]==0x24) { // AND
2395 emit_zeroreg(tl);
2396 } else
2397 if(opcode2[i]==0x25||opcode2[i]==0x26) { // OR/XOR
2398 if(rs1[i]){
2399 if(s1l>=0) emit_mov(s1l,tl);
2400 else emit_loadreg(rs1[i],tl); // CHECK: regmap_entry?
2401 }
2402 else
2403 if(rs2[i]){
2404 if(s2l>=0) emit_mov(s2l,tl);
2405 else emit_loadreg(rs2[i],tl); // CHECK: regmap_entry?
2406 }
2407 else emit_zeroreg(tl);
2408 } else
2409 if(opcode2[i]==0x27) { // NOR
2410 if(rs1[i]){
2411 if(s1l>=0) emit_not(s1l,tl);
2412 else {
2413 emit_loadreg(rs1[i],tl);
2414 emit_not(tl,tl);
2415 }
2416 }
2417 else
2418 if(rs2[i]){
2419 if(s2l>=0) emit_not(s2l,tl);
2420 else {
2421 emit_loadreg(rs2[i],tl);
2422 emit_not(tl,tl);
2423 }
2424 }
2425 else emit_movimm(-1,tl);
2426 }
2427 }
2428 }
2429 }
2430 }
2431 }
2432}
2433
2434void imm16_assemble(int i,struct regstat *i_regs)
2435{
2436 if (opcode[i]==0x0f) { // LUI
2437 if(rt1[i]) {
2438 signed char t;
2439 t=get_reg(i_regs->regmap,rt1[i]);
2440 //assert(t>=0);
2441 if(t>=0) {
2442 if(!((i_regs->isconst>>t)&1))
2443 emit_movimm(imm[i]<<16,t);
2444 }
2445 }
2446 }
2447 if(opcode[i]==0x08||opcode[i]==0x09) { // ADDI/ADDIU
2448 if(rt1[i]) {
2449 signed char s,t;
2450 t=get_reg(i_regs->regmap,rt1[i]);
2451 s=get_reg(i_regs->regmap,rs1[i]);
2452 if(rs1[i]) {
2453 //assert(t>=0);
2454 //assert(s>=0);
2455 if(t>=0) {
2456 if(!((i_regs->isconst>>t)&1)) {
2457 if(s<0) {
2458 if(i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2459 emit_addimm(t,imm[i],t);
2460 }else{
2461 if(!((i_regs->wasconst>>s)&1))
2462 emit_addimm(s,imm[i],t);
2463 else
2464 emit_movimm(constmap[i][s]+imm[i],t);
2465 }
2466 }
2467 }
2468 } else {
2469 if(t>=0) {
2470 if(!((i_regs->isconst>>t)&1))
2471 emit_movimm(imm[i],t);
2472 }
2473 }
2474 }
2475 }
2476 if(opcode[i]==0x18||opcode[i]==0x19) { // DADDI/DADDIU
2477 if(rt1[i]) {
2478 signed char sh,sl,th,tl;
2479 th=get_reg(i_regs->regmap,rt1[i]|64);
2480 tl=get_reg(i_regs->regmap,rt1[i]);
2481 sh=get_reg(i_regs->regmap,rs1[i]|64);
2482 sl=get_reg(i_regs->regmap,rs1[i]);
2483 if(tl>=0) {
2484 if(rs1[i]) {
2485 assert(sh>=0);
2486 assert(sl>=0);
2487 if(th>=0) {
2488 emit_addimm64_32(sh,sl,imm[i],th,tl);
2489 }
2490 else {
2491 emit_addimm(sl,imm[i],tl);
2492 }
2493 } else {
2494 emit_movimm(imm[i],tl);
2495 if(th>=0) emit_movimm(((signed int)imm[i])>>31,th);
2496 }
2497 }
2498 }
2499 }
2500 else if(opcode[i]==0x0a||opcode[i]==0x0b) { // SLTI/SLTIU
2501 if(rt1[i]) {
2502 //assert(rs1[i]!=0); // r0 might be valid, but it's probably a bug
2503 signed char sh,sl,t;
2504 t=get_reg(i_regs->regmap,rt1[i]);
2505 sh=get_reg(i_regs->regmap,rs1[i]|64);
2506 sl=get_reg(i_regs->regmap,rs1[i]);
2507 //assert(t>=0);
2508 if(t>=0) {
2509 if(rs1[i]>0) {
2510 if(sh<0) assert((i_regs->was32>>rs1[i])&1);
2511 if(sh<0||((i_regs->was32>>rs1[i])&1)) {
2512 if(opcode[i]==0x0a) { // SLTI
2513 if(sl<0) {
2514 if(i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2515 emit_slti32(t,imm[i],t);
2516 }else{
2517 emit_slti32(sl,imm[i],t);
2518 }
2519 }
2520 else { // SLTIU
2521 if(sl<0) {
2522 if(i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2523 emit_sltiu32(t,imm[i],t);
2524 }else{
2525 emit_sltiu32(sl,imm[i],t);
2526 }
2527 }
2528 }else{ // 64-bit
2529 assert(sl>=0);
2530 if(opcode[i]==0x0a) // SLTI
2531 emit_slti64_32(sh,sl,imm[i],t);
2532 else // SLTIU
2533 emit_sltiu64_32(sh,sl,imm[i],t);
2534 }
2535 }else{
2536 // SLTI(U) with r0 is just stupid,
2537 // nonetheless examples can be found
2538 if(opcode[i]==0x0a) // SLTI
2539 if(0<imm[i]) emit_movimm(1,t);
2540 else emit_zeroreg(t);
2541 else // SLTIU
2542 {
2543 if(imm[i]) emit_movimm(1,t);
2544 else emit_zeroreg(t);
2545 }
2546 }
2547 }
2548 }
2549 }
2550 else if(opcode[i]>=0x0c&&opcode[i]<=0x0e) { // ANDI/ORI/XORI
2551 if(rt1[i]) {
2552 signed char sh,sl,th,tl;
2553 th=get_reg(i_regs->regmap,rt1[i]|64);
2554 tl=get_reg(i_regs->regmap,rt1[i]);
2555 sh=get_reg(i_regs->regmap,rs1[i]|64);
2556 sl=get_reg(i_regs->regmap,rs1[i]);
2557 if(tl>=0 && !((i_regs->isconst>>tl)&1)) {
2558 if(opcode[i]==0x0c) //ANDI
2559 {
2560 if(rs1[i]) {
2561 if(sl<0) {
2562 if(i_regs->regmap_entry[tl]!=rs1[i]) emit_loadreg(rs1[i],tl);
2563 emit_andimm(tl,imm[i],tl);
2564 }else{
2565 if(!((i_regs->wasconst>>sl)&1))
2566 emit_andimm(sl,imm[i],tl);
2567 else
2568 emit_movimm(constmap[i][sl]&imm[i],tl);
2569 }
2570 }
2571 else
2572 emit_zeroreg(tl);
2573 if(th>=0) emit_zeroreg(th);
2574 }
2575 else
2576 {
2577 if(rs1[i]) {
2578 if(sl<0) {
2579 if(i_regs->regmap_entry[tl]!=rs1[i]) emit_loadreg(rs1[i],tl);
2580 }
2581 if(th>=0) {
2582 if(sh<0) {
2583 emit_loadreg(rs1[i]|64,th);
2584 }else{
2585 emit_mov(sh,th);
2586 }
2587 }
2588 if(opcode[i]==0x0d) //ORI
2589 if(sl<0) {
2590 emit_orimm(tl,imm[i],tl);
2591 }else{
2592 if(!((i_regs->wasconst>>sl)&1))
2593 emit_orimm(sl,imm[i],tl);
2594 else
2595 emit_movimm(constmap[i][sl]|imm[i],tl);
2596 }
2597 if(opcode[i]==0x0e) //XORI
2598 if(sl<0) {
2599 emit_xorimm(tl,imm[i],tl);
2600 }else{
2601 if(!((i_regs->wasconst>>sl)&1))
2602 emit_xorimm(sl,imm[i],tl);
2603 else
2604 emit_movimm(constmap[i][sl]^imm[i],tl);
2605 }
2606 }
2607 else {
2608 emit_movimm(imm[i],tl);
2609 if(th>=0) emit_zeroreg(th);
2610 }
2611 }
2612 }
2613 }
2614 }
2615}
2616
2617void shiftimm_assemble(int i,struct regstat *i_regs)
2618{
2619 if(opcode2[i]<=0x3) // SLL/SRL/SRA
2620 {
2621 if(rt1[i]) {
2622 signed char s,t;
2623 t=get_reg(i_regs->regmap,rt1[i]);
2624 s=get_reg(i_regs->regmap,rs1[i]);
2625 //assert(t>=0);
2626 if(t>=0){
2627 if(rs1[i]==0)
2628 {
2629 emit_zeroreg(t);
2630 }
2631 else
2632 {
2633 if(s<0&&i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2634 if(imm[i]) {
2635 if(opcode2[i]==0) // SLL
2636 {
2637 emit_shlimm(s<0?t:s,imm[i],t);
2638 }
2639 if(opcode2[i]==2) // SRL
2640 {
2641 emit_shrimm(s<0?t:s,imm[i],t);
2642 }
2643 if(opcode2[i]==3) // SRA
2644 {
2645 emit_sarimm(s<0?t:s,imm[i],t);
2646 }
2647 }else{
2648 // Shift by zero
2649 if(s>=0 && s!=t) emit_mov(s,t);
2650 }
2651 }
2652 }
2653 //emit_storereg(rt1[i],t); //DEBUG
2654 }
2655 }
2656 if(opcode2[i]>=0x38&&opcode2[i]<=0x3b) // DSLL/DSRL/DSRA
2657 {
2658 if(rt1[i]) {
2659 signed char sh,sl,th,tl;
2660 th=get_reg(i_regs->regmap,rt1[i]|64);
2661 tl=get_reg(i_regs->regmap,rt1[i]);
2662 sh=get_reg(i_regs->regmap,rs1[i]|64);
2663 sl=get_reg(i_regs->regmap,rs1[i]);
2664 if(tl>=0) {
2665 if(rs1[i]==0)
2666 {
2667 emit_zeroreg(tl);
2668 if(th>=0) emit_zeroreg(th);
2669 }
2670 else
2671 {
2672 assert(sl>=0);
2673 assert(sh>=0);
2674 if(imm[i]) {
2675 if(opcode2[i]==0x38) // DSLL
2676 {
2677 if(th>=0) emit_shldimm(sh,sl,imm[i],th);
2678 emit_shlimm(sl,imm[i],tl);
2679 }
2680 if(opcode2[i]==0x3a) // DSRL
2681 {
2682 emit_shrdimm(sl,sh,imm[i],tl);
2683 if(th>=0) emit_shrimm(sh,imm[i],th);
2684 }
2685 if(opcode2[i]==0x3b) // DSRA
2686 {
2687 emit_shrdimm(sl,sh,imm[i],tl);
2688 if(th>=0) emit_sarimm(sh,imm[i],th);
2689 }
2690 }else{
2691 // Shift by zero
2692 if(sl!=tl) emit_mov(sl,tl);
2693 if(th>=0&&sh!=th) emit_mov(sh,th);
2694 }
2695 }
2696 }
2697 }
2698 }
2699 if(opcode2[i]==0x3c) // DSLL32
2700 {
2701 if(rt1[i]) {
2702 signed char sl,tl,th;
2703 tl=get_reg(i_regs->regmap,rt1[i]);
2704 th=get_reg(i_regs->regmap,rt1[i]|64);
2705 sl=get_reg(i_regs->regmap,rs1[i]);
2706 if(th>=0||tl>=0){
2707 assert(tl>=0);
2708 assert(th>=0);
2709 assert(sl>=0);
2710 emit_mov(sl,th);
2711 emit_zeroreg(tl);
2712 if(imm[i]>32)
2713 {
2714 emit_shlimm(th,imm[i]&31,th);
2715 }
2716 }
2717 }
2718 }
2719 if(opcode2[i]==0x3e) // DSRL32
2720 {
2721 if(rt1[i]) {
2722 signed char sh,tl,th;
2723 tl=get_reg(i_regs->regmap,rt1[i]);
2724 th=get_reg(i_regs->regmap,rt1[i]|64);
2725 sh=get_reg(i_regs->regmap,rs1[i]|64);
2726 if(tl>=0){
2727 assert(sh>=0);
2728 emit_mov(sh,tl);
2729 if(th>=0) emit_zeroreg(th);
2730 if(imm[i]>32)
2731 {
2732 emit_shrimm(tl,imm[i]&31,tl);
2733 }
2734 }
2735 }
2736 }
2737 if(opcode2[i]==0x3f) // DSRA32
2738 {
2739 if(rt1[i]) {
2740 signed char sh,tl;
2741 tl=get_reg(i_regs->regmap,rt1[i]);
2742 sh=get_reg(i_regs->regmap,rs1[i]|64);
2743 if(tl>=0){
2744 assert(sh>=0);
2745 emit_mov(sh,tl);
2746 if(imm[i]>32)
2747 {
2748 emit_sarimm(tl,imm[i]&31,tl);
2749 }
2750 }
2751 }
2752 }
2753}
2754
2755#ifndef shift_assemble
2756void shift_assemble(int i,struct regstat *i_regs)
2757{
2758 printf("Need shift_assemble for this architecture.\n");
2759 exit(1);
2760}
2761#endif
2762
2763void load_assemble(int i,struct regstat *i_regs)
2764{
2765 int s,th,tl,addr,map=-1;
2766 int offset;
2767 int jaddr=0;
5bf843dc 2768 int memtarget=0,c=0;
57871462 2769 u_int hr,reglist=0;
2770 th=get_reg(i_regs->regmap,rt1[i]|64);
2771 tl=get_reg(i_regs->regmap,rt1[i]);
2772 s=get_reg(i_regs->regmap,rs1[i]);
2773 offset=imm[i];
2774 for(hr=0;hr<HOST_REGS;hr++) {
2775 if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
2776 }
2777 if(i_regs->regmap[HOST_CCREG]==CCREG) reglist&=~(1<<HOST_CCREG);
2778 if(s>=0) {
2779 c=(i_regs->wasconst>>s)&1;
af4ee1fe 2780 if (c) {
2781 memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
2782 if(using_tlb&&((signed int)(constmap[i][s]+offset))>=(signed int)0xC0000000) memtarget=1;
2783 }
57871462 2784 }
57871462 2785 //printf("load_assemble: c=%d\n",c);
2786 //if(c) printf("load_assemble: const=%x\n",(int)constmap[i][s]+offset);
2787 // FIXME: Even if the load is a NOP, we should check for pagefaults...
5bf843dc 2788#ifdef PCSX
f18c0f46 2789 if(tl<0&&(!c||(((u_int)constmap[i][s]+offset)>>16)==0x1f80)
2790 ||rt1[i]==0) {
5bf843dc 2791 // could be FIFO, must perform the read
f18c0f46 2792 // ||dummy read
5bf843dc 2793 assem_debug("(forced read)\n");
2794 tl=get_reg(i_regs->regmap,-1);
2795 assert(tl>=0);
5bf843dc 2796 }
f18c0f46 2797#endif
5bf843dc 2798 if(offset||s<0||c) addr=tl;
2799 else addr=s;
535d208a 2800 //if(tl<0) tl=get_reg(i_regs->regmap,-1);
2801 if(tl>=0) {
2802 //printf("load_assemble: c=%d\n",c);
2803 //if(c) printf("load_assemble: const=%x\n",(int)constmap[i][s]+offset);
2804 assert(tl>=0); // Even if the load is a NOP, we must check for pagefaults and I/O
2805 reglist&=~(1<<tl);
2806 if(th>=0) reglist&=~(1<<th);
2807 if(!using_tlb) {
2808 if(!c) {
2809 #ifdef RAM_OFFSET
2810 map=get_reg(i_regs->regmap,ROREG);
2811 if(map<0) emit_loadreg(ROREG,map=HOST_TEMPREG);
2812 #endif
57871462 2813//#define R29_HACK 1
535d208a 2814 #ifdef R29_HACK
2815 // Strmnnrmn's speed hack
2816 if(rs1[i]!=29||start<0x80001000||start>=0x80000000+RAM_SIZE)
2817 #endif
2818 {
dadf55f2 2819 #ifdef PCSX
2820 if(sp_in_mirror&&rs1[i]==29) {
2821 emit_andimm(addr,~0x00e00000,HOST_TEMPREG);
2822 emit_cmpimm(HOST_TEMPREG,RAM_SIZE);
2823 }
2824 else
2825 #endif
535d208a 2826 emit_cmpimm(addr,RAM_SIZE);
2827 jaddr=(int)out;
2828 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
2829 // Hint to branch predictor that the branch is unlikely to be taken
2830 if(rs1[i]>=28)
2831 emit_jno_unlikely(0);
2832 else
57871462 2833 #endif
535d208a 2834 emit_jno(0);
57871462 2835 }
535d208a 2836 }
2837 }else{ // using tlb
2838 int x=0;
2839 if (opcode[i]==0x20||opcode[i]==0x24) x=3; // LB/LBU
2840 if (opcode[i]==0x21||opcode[i]==0x25) x=2; // LH/LHU
2841 map=get_reg(i_regs->regmap,TLREG);
2842 assert(map>=0);
ea3d2e6e 2843 reglist&=~(1<<map);
535d208a 2844 map=do_tlb_r(addr,tl,map,x,-1,-1,c,constmap[i][s]+offset);
2845 do_tlb_r_branch(map,c,constmap[i][s]+offset,&jaddr);
2846 }
2847 int dummy=(rt1[i]==0)||(tl!=get_reg(i_regs->regmap,rt1[i])); // ignore loads to r0 and unneeded reg
2848 if (opcode[i]==0x20) { // LB
2849 if(!c||memtarget) {
2850 if(!dummy) {
57871462 2851 #ifdef HOST_IMM_ADDR32
2852 if(c)
2853 emit_movsbl_tlb((constmap[i][s]+offset)^3,map,tl);
2854 else
2855 #endif
2856 {
2857 //emit_xorimm(addr,3,tl);
2858 //gen_tlb_addr_r(tl,map);
2859 //emit_movsbl_indexed((int)rdram-0x80000000,tl,tl);
535d208a 2860 int x=0,a=tl;
2002a1db 2861#ifdef BIG_ENDIAN_MIPS
57871462 2862 if(!c) emit_xorimm(addr,3,tl);
2863 else x=((constmap[i][s]+offset)^3)-(constmap[i][s]+offset);
2002a1db 2864#else
535d208a 2865 if(!c) a=addr;
dadf55f2 2866#endif
2867#ifdef PCSX
2868 if(sp_in_mirror&&rs1[i]==29) a=HOST_TEMPREG;
2002a1db 2869#endif
535d208a 2870 emit_movsbl_indexed_tlb(x,a,map,tl);
57871462 2871 }
57871462 2872 }
535d208a 2873 if(jaddr)
2874 add_stub(LOADB_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
57871462 2875 }
535d208a 2876 else
2877 inline_readstub(LOADB_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2878 }
2879 if (opcode[i]==0x21) { // LH
2880 if(!c||memtarget) {
2881 if(!dummy) {
57871462 2882 #ifdef HOST_IMM_ADDR32
2883 if(c)
2884 emit_movswl_tlb((constmap[i][s]+offset)^2,map,tl);
2885 else
2886 #endif
2887 {
535d208a 2888 int x=0,a=tl;
2002a1db 2889#ifdef BIG_ENDIAN_MIPS
57871462 2890 if(!c) emit_xorimm(addr,2,tl);
2891 else x=((constmap[i][s]+offset)^2)-(constmap[i][s]+offset);
2002a1db 2892#else
535d208a 2893 if(!c) a=addr;
dadf55f2 2894#endif
2895#ifdef PCSX
2896 if(sp_in_mirror&&rs1[i]==29) a=HOST_TEMPREG;
2002a1db 2897#endif
57871462 2898 //#ifdef
2899 //emit_movswl_indexed_tlb(x,tl,map,tl);
2900 //else
2901 if(map>=0) {
535d208a 2902 gen_tlb_addr_r(a,map);
2903 emit_movswl_indexed(x,a,tl);
2904 }else{
2905 #ifdef RAM_OFFSET
2906 emit_movswl_indexed(x,a,tl);
2907 #else
2908 emit_movswl_indexed((int)rdram-0x80000000+x,a,tl);
2909 #endif
2910 }
57871462 2911 }
57871462 2912 }
535d208a 2913 if(jaddr)
2914 add_stub(LOADH_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
57871462 2915 }
535d208a 2916 else
2917 inline_readstub(LOADH_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2918 }
2919 if (opcode[i]==0x23) { // LW
2920 if(!c||memtarget) {
2921 if(!dummy) {
dadf55f2 2922 int a=addr;
2923#ifdef PCSX
2924 if(sp_in_mirror&&rs1[i]==29) a=HOST_TEMPREG;
2925#endif
57871462 2926 //emit_readword_indexed((int)rdram-0x80000000,addr,tl);
2927 #ifdef HOST_IMM_ADDR32
2928 if(c)
2929 emit_readword_tlb(constmap[i][s]+offset,map,tl);
2930 else
2931 #endif
dadf55f2 2932 emit_readword_indexed_tlb(0,a,map,tl);
57871462 2933 }
535d208a 2934 if(jaddr)
2935 add_stub(LOADW_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
57871462 2936 }
535d208a 2937 else
2938 inline_readstub(LOADW_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2939 }
2940 if (opcode[i]==0x24) { // LBU
2941 if(!c||memtarget) {
2942 if(!dummy) {
57871462 2943 #ifdef HOST_IMM_ADDR32
2944 if(c)
2945 emit_movzbl_tlb((constmap[i][s]+offset)^3,map,tl);
2946 else
2947 #endif
2948 {
2949 //emit_xorimm(addr,3,tl);
2950 //gen_tlb_addr_r(tl,map);
2951 //emit_movzbl_indexed((int)rdram-0x80000000,tl,tl);
535d208a 2952 int x=0,a=tl;
2002a1db 2953#ifdef BIG_ENDIAN_MIPS
57871462 2954 if(!c) emit_xorimm(addr,3,tl);
2955 else x=((constmap[i][s]+offset)^3)-(constmap[i][s]+offset);
2002a1db 2956#else
535d208a 2957 if(!c) a=addr;
dadf55f2 2958#endif
2959#ifdef PCSX
2960 if(sp_in_mirror&&rs1[i]==29) a=HOST_TEMPREG;
2002a1db 2961#endif
535d208a 2962 emit_movzbl_indexed_tlb(x,a,map,tl);
57871462 2963 }
57871462 2964 }
535d208a 2965 if(jaddr)
2966 add_stub(LOADBU_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
57871462 2967 }
535d208a 2968 else
2969 inline_readstub(LOADBU_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2970 }
2971 if (opcode[i]==0x25) { // LHU
2972 if(!c||memtarget) {
2973 if(!dummy) {
57871462 2974 #ifdef HOST_IMM_ADDR32
2975 if(c)
2976 emit_movzwl_tlb((constmap[i][s]+offset)^2,map,tl);
2977 else
2978 #endif
2979 {
535d208a 2980 int x=0,a=tl;
2002a1db 2981#ifdef BIG_ENDIAN_MIPS
57871462 2982 if(!c) emit_xorimm(addr,2,tl);
2983 else x=((constmap[i][s]+offset)^2)-(constmap[i][s]+offset);
2002a1db 2984#else
535d208a 2985 if(!c) a=addr;
dadf55f2 2986#endif
2987#ifdef PCSX
2988 if(sp_in_mirror&&rs1[i]==29) a=HOST_TEMPREG;
2002a1db 2989#endif
57871462 2990 //#ifdef
2991 //emit_movzwl_indexed_tlb(x,tl,map,tl);
2992 //#else
2993 if(map>=0) {
535d208a 2994 gen_tlb_addr_r(a,map);
2995 emit_movzwl_indexed(x,a,tl);
2996 }else{
2997 #ifdef RAM_OFFSET
2998 emit_movzwl_indexed(x,a,tl);
2999 #else
3000 emit_movzwl_indexed((int)rdram-0x80000000+x,a,tl);
3001 #endif
3002 }
57871462 3003 }
3004 }
535d208a 3005 if(jaddr)
3006 add_stub(LOADHU_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
57871462 3007 }
535d208a 3008 else
3009 inline_readstub(LOADHU_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
3010 }
3011 if (opcode[i]==0x27) { // LWU
3012 assert(th>=0);
3013 if(!c||memtarget) {
3014 if(!dummy) {
dadf55f2 3015 int a=addr;
3016#ifdef PCSX
3017 if(sp_in_mirror&&rs1[i]==29) a=HOST_TEMPREG;
3018#endif
57871462 3019 //emit_readword_indexed((int)rdram-0x80000000,addr,tl);
3020 #ifdef HOST_IMM_ADDR32
3021 if(c)
3022 emit_readword_tlb(constmap[i][s]+offset,map,tl);
3023 else
3024 #endif
dadf55f2 3025 emit_readword_indexed_tlb(0,a,map,tl);
57871462 3026 }
535d208a 3027 if(jaddr)
3028 add_stub(LOADW_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
3029 }
3030 else {
3031 inline_readstub(LOADW_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
57871462 3032 }
535d208a 3033 emit_zeroreg(th);
3034 }
3035 if (opcode[i]==0x37) { // LD
3036 if(!c||memtarget) {
3037 if(!dummy) {
dadf55f2 3038 int a=addr;
3039#ifdef PCSX
3040 if(sp_in_mirror&&rs1[i]==29) a=HOST_TEMPREG;
3041#endif
57871462 3042 //gen_tlb_addr_r(tl,map);
3043 //if(th>=0) emit_readword_indexed((int)rdram-0x80000000,addr,th);
3044 //emit_readword_indexed((int)rdram-0x7FFFFFFC,addr,tl);
3045 #ifdef HOST_IMM_ADDR32
3046 if(c)
3047 emit_readdword_tlb(constmap[i][s]+offset,map,th,tl);
3048 else
3049 #endif
dadf55f2 3050 emit_readdword_indexed_tlb(0,a,map,th,tl);
57871462 3051 }
535d208a 3052 if(jaddr)
3053 add_stub(LOADD_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
57871462 3054 }
535d208a 3055 else
3056 inline_readstub(LOADD_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
57871462 3057 }
535d208a 3058 }
3059 //emit_storereg(rt1[i],tl); // DEBUG
57871462 3060 //if(opcode[i]==0x23)
3061 //if(opcode[i]==0x24)
3062 //if(opcode[i]==0x23||opcode[i]==0x24)
3063 /*if(opcode[i]==0x21||opcode[i]==0x23||opcode[i]==0x24)
3064 {
3065 //emit_pusha();
3066 save_regs(0x100f);
3067 emit_readword((int)&last_count,ECX);
3068 #ifdef __i386__
3069 if(get_reg(i_regs->regmap,CCREG)<0)
3070 emit_loadreg(CCREG,HOST_CCREG);
3071 emit_add(HOST_CCREG,ECX,HOST_CCREG);
3072 emit_addimm(HOST_CCREG,2*ccadj[i],HOST_CCREG);
3073 emit_writeword(HOST_CCREG,(int)&Count);
3074 #endif
3075 #ifdef __arm__
3076 if(get_reg(i_regs->regmap,CCREG)<0)
3077 emit_loadreg(CCREG,0);
3078 else
3079 emit_mov(HOST_CCREG,0);
3080 emit_add(0,ECX,0);
3081 emit_addimm(0,2*ccadj[i],0);
3082 emit_writeword(0,(int)&Count);
3083 #endif
3084 emit_call((int)memdebug);
3085 //emit_popa();
3086 restore_regs(0x100f);
3087 }/**/
3088}
3089
3090#ifndef loadlr_assemble
3091void loadlr_assemble(int i,struct regstat *i_regs)
3092{
3093 printf("Need loadlr_assemble for this architecture.\n");
3094 exit(1);
3095}
3096#endif
3097
3098void store_assemble(int i,struct regstat *i_regs)
3099{
3100 int s,th,tl,map=-1;
3101 int addr,temp;
3102 int offset;
3103 int jaddr=0,jaddr2,type;
666a299d 3104 int memtarget=0,c=0;
57871462 3105 int agr=AGEN1+(i&1);
3106 u_int hr,reglist=0;
3107 th=get_reg(i_regs->regmap,rs2[i]|64);
3108 tl=get_reg(i_regs->regmap,rs2[i]);
3109 s=get_reg(i_regs->regmap,rs1[i]);
3110 temp=get_reg(i_regs->regmap,agr);
3111 if(temp<0) temp=get_reg(i_regs->regmap,-1);
3112 offset=imm[i];
3113 if(s>=0) {
3114 c=(i_regs->wasconst>>s)&1;
af4ee1fe 3115 if(c) {
3116 memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
3117 if(using_tlb&&((signed int)(constmap[i][s]+offset))>=(signed int)0xC0000000) memtarget=1;
3118 }
57871462 3119 }
3120 assert(tl>=0);
3121 assert(temp>=0);
3122 for(hr=0;hr<HOST_REGS;hr++) {
3123 if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
3124 }
3125 if(i_regs->regmap[HOST_CCREG]==CCREG) reglist&=~(1<<HOST_CCREG);
3126 if(offset||s<0||c) addr=temp;
3127 else addr=s;
3128 if(!using_tlb) {
3129 if(!c) {
dadf55f2 3130 #ifdef PCSX
3131 if(sp_in_mirror&&rs1[i]==29) {
3132 emit_andimm(addr,~0x00e00000,HOST_TEMPREG);
3133 emit_cmpimm(HOST_TEMPREG,RAM_SIZE);
3134 }
3135 else
3136 #endif
57871462 3137 #ifdef R29_HACK
3138 // Strmnnrmn's speed hack
4cb76aa4 3139 if(rs1[i]!=29||start<0x80001000||start>=0x80000000+RAM_SIZE)
57871462 3140 #endif
4cb76aa4 3141 emit_cmpimm(addr,RAM_SIZE);
57871462 3142 #ifdef DESTRUCTIVE_SHIFT
3143 if(s==addr) emit_mov(s,temp);
3144 #endif
3145 #ifdef R29_HACK
dadf55f2 3146 memtarget=1;
4cb76aa4 3147 if(rs1[i]!=29||start<0x80001000||start>=0x80000000+RAM_SIZE)
57871462 3148 #endif
3149 {
3150 jaddr=(int)out;
3151 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
3152 // Hint to branch predictor that the branch is unlikely to be taken
3153 if(rs1[i]>=28)
3154 emit_jno_unlikely(0);
3155 else
3156 #endif
3157 emit_jno(0);
3158 }
3159 }
3160 }else{ // using tlb
3161 int x=0;
3162 if (opcode[i]==0x28) x=3; // SB
3163 if (opcode[i]==0x29) x=2; // SH
3164 map=get_reg(i_regs->regmap,TLREG);
3165 assert(map>=0);
ea3d2e6e 3166 reglist&=~(1<<map);
57871462 3167 map=do_tlb_w(addr,temp,map,x,c,constmap[i][s]+offset);
3168 do_tlb_w_branch(map,c,constmap[i][s]+offset,&jaddr);
3169 }
3170
3171 if (opcode[i]==0x28) { // SB
3172 if(!c||memtarget) {
97a238a6 3173 int x=0,a=temp;
2002a1db 3174#ifdef BIG_ENDIAN_MIPS
57871462 3175 if(!c) emit_xorimm(addr,3,temp);
3176 else x=((constmap[i][s]+offset)^3)-(constmap[i][s]+offset);
2002a1db 3177#else
97a238a6 3178 if(!c) a=addr;
dadf55f2 3179#endif
3180#ifdef PCSX
3181 if(sp_in_mirror&&rs1[i]==29) a=HOST_TEMPREG;
2002a1db 3182#endif
57871462 3183 //gen_tlb_addr_w(temp,map);
3184 //emit_writebyte_indexed(tl,(int)rdram-0x80000000,temp);
97a238a6 3185 emit_writebyte_indexed_tlb(tl,x,a,map,a);
57871462 3186 }
3187 type=STOREB_STUB;
3188 }
3189 if (opcode[i]==0x29) { // SH
3190 if(!c||memtarget) {
97a238a6 3191 int x=0,a=temp;
2002a1db 3192#ifdef BIG_ENDIAN_MIPS
57871462 3193 if(!c) emit_xorimm(addr,2,temp);
3194 else x=((constmap[i][s]+offset)^2)-(constmap[i][s]+offset);
2002a1db 3195#else
97a238a6 3196 if(!c) a=addr;
dadf55f2 3197#endif
3198#ifdef PCSX
3199 if(sp_in_mirror&&rs1[i]==29) a=HOST_TEMPREG;
2002a1db 3200#endif
57871462 3201 //#ifdef
3202 //emit_writehword_indexed_tlb(tl,x,temp,map,temp);
3203 //#else
3204 if(map>=0) {
97a238a6 3205 gen_tlb_addr_w(a,map);
3206 emit_writehword_indexed(tl,x,a);
57871462 3207 }else
97a238a6 3208 emit_writehword_indexed(tl,(int)rdram-0x80000000+x,a);
57871462 3209 }
3210 type=STOREH_STUB;
3211 }
3212 if (opcode[i]==0x2B) { // SW
dadf55f2 3213 if(!c||memtarget) {
3214 int a=addr;
3215#ifdef PCSX
3216 if(sp_in_mirror&&rs1[i]==29) a=HOST_TEMPREG;
3217#endif
57871462 3218 //emit_writeword_indexed(tl,(int)rdram-0x80000000,addr);
dadf55f2 3219 emit_writeword_indexed_tlb(tl,0,a,map,temp);
3220 }
57871462 3221 type=STOREW_STUB;
3222 }
3223 if (opcode[i]==0x3F) { // SD
3224 if(!c||memtarget) {
dadf55f2 3225 int a=addr;
3226#ifdef PCSX
3227 if(sp_in_mirror&&rs1[i]==29) a=HOST_TEMPREG;
3228#endif
57871462 3229 if(rs2[i]) {
3230 assert(th>=0);
3231 //emit_writeword_indexed(th,(int)rdram-0x80000000,addr);
3232 //emit_writeword_indexed(tl,(int)rdram-0x7FFFFFFC,addr);
dadf55f2 3233 emit_writedword_indexed_tlb(th,tl,0,a,map,temp);
57871462 3234 }else{
3235 // Store zero
3236 //emit_writeword_indexed(tl,(int)rdram-0x80000000,temp);
3237 //emit_writeword_indexed(tl,(int)rdram-0x7FFFFFFC,temp);
dadf55f2 3238 emit_writedword_indexed_tlb(tl,tl,0,a,map,temp);
57871462 3239 }
3240 }
3241 type=STORED_STUB;
3242 }
57871462 3243 if(!using_tlb) {
3244 if(!c||memtarget) {
3245 #ifdef DESTRUCTIVE_SHIFT
3246 // The x86 shift operation is 'destructive'; it overwrites the
3247 // source register, so we need to make a copy first and use that.
3248 addr=temp;
3249 #endif
3250 #if defined(HOST_IMM8)
3251 int ir=get_reg(i_regs->regmap,INVCP);
3252 assert(ir>=0);
3253 emit_cmpmem_indexedsr12_reg(ir,addr,1);
3254 #else
3255 emit_cmpmem_indexedsr12_imm((int)invalid_code,addr,1);
3256 #endif
0bbd1454 3257 #if defined(HAVE_CONDITIONAL_CALL) && !defined(DESTRUCTIVE_SHIFT)
3258 emit_callne(invalidate_addr_reg[addr]);
3259 #else
57871462 3260 jaddr2=(int)out;
3261 emit_jne(0);
3262 add_stub(INVCODE_STUB,jaddr2,(int)out,reglist|(1<<HOST_CCREG),addr,0,0,0);
0bbd1454 3263 #endif
57871462 3264 }
3265 }
3eaa7048 3266 if(jaddr) {
3267 add_stub(type,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
3268 } else if(c&&!memtarget) {
3269 inline_writestub(type,i,constmap[i][s]+offset,i_regs->regmap,rs2[i],ccadj[i],reglist);
3270 }
57871462 3271 //if(opcode[i]==0x2B || opcode[i]==0x3F)
3272 //if(opcode[i]==0x2B || opcode[i]==0x28)
3273 //if(opcode[i]==0x2B || opcode[i]==0x29)
3274 //if(opcode[i]==0x2B)
3275 /*if(opcode[i]==0x2B || opcode[i]==0x28 || opcode[i]==0x29 || opcode[i]==0x3F)
3276 {
3277 //emit_pusha();
3278 save_regs(0x100f);
3279 emit_readword((int)&last_count,ECX);
3280 #ifdef __i386__
3281 if(get_reg(i_regs->regmap,CCREG)<0)
3282 emit_loadreg(CCREG,HOST_CCREG);
3283 emit_add(HOST_CCREG,ECX,HOST_CCREG);
3284 emit_addimm(HOST_CCREG,2*ccadj[i],HOST_CCREG);
3285 emit_writeword(HOST_CCREG,(int)&Count);
3286 #endif
3287 #ifdef __arm__
3288 if(get_reg(i_regs->regmap,CCREG)<0)
3289 emit_loadreg(CCREG,0);
3290 else
3291 emit_mov(HOST_CCREG,0);
3292 emit_add(0,ECX,0);
3293 emit_addimm(0,2*ccadj[i],0);
3294 emit_writeword(0,(int)&Count);
3295 #endif
3296 emit_call((int)memdebug);
3297 //emit_popa();
3298 restore_regs(0x100f);
3299 }/**/
3300}
3301
3302void storelr_assemble(int i,struct regstat *i_regs)
3303{
3304 int s,th,tl;
3305 int temp;
3306 int temp2;
3307 int offset;
3308 int jaddr=0,jaddr2;
3309 int case1,case2,case3;
3310 int done0,done1,done2;
af4ee1fe 3311 int memtarget=0,c=0;
fab5d06d 3312 int agr=AGEN1+(i&1);
57871462 3313 u_int hr,reglist=0;
3314 th=get_reg(i_regs->regmap,rs2[i]|64);
3315 tl=get_reg(i_regs->regmap,rs2[i]);
3316 s=get_reg(i_regs->regmap,rs1[i]);
fab5d06d 3317 temp=get_reg(i_regs->regmap,agr);
3318 if(temp<0) temp=get_reg(i_regs->regmap,-1);
57871462 3319 offset=imm[i];
3320 if(s>=0) {
3321 c=(i_regs->isconst>>s)&1;
af4ee1fe 3322 if(c) {
3323 memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
3324 if(using_tlb&&((signed int)(constmap[i][s]+offset))>=(signed int)0xC0000000) memtarget=1;
3325 }
57871462 3326 }
3327 assert(tl>=0);
3328 for(hr=0;hr<HOST_REGS;hr++) {
3329 if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
3330 }
535d208a 3331 assert(temp>=0);
3332 if(!using_tlb) {
3333 if(!c) {
3334 emit_cmpimm(s<0||offset?temp:s,RAM_SIZE);
3335 if(!offset&&s!=temp) emit_mov(s,temp);
3336 jaddr=(int)out;
3337 emit_jno(0);
3338 }
3339 else
3340 {
3341 if(!memtarget||!rs1[i]) {
57871462 3342 jaddr=(int)out;
3343 emit_jmp(0);
3344 }
57871462 3345 }
535d208a 3346 #ifdef RAM_OFFSET
3347 int map=get_reg(i_regs->regmap,ROREG);
3348 if(map<0) emit_loadreg(ROREG,map=HOST_TEMPREG);
3349 gen_tlb_addr_w(temp,map);
3350 #else
3351 if((u_int)rdram!=0x80000000)
3352 emit_addimm_no_flags((u_int)rdram-(u_int)0x80000000,temp);
3353 #endif
3354 }else{ // using tlb
3355 int map=get_reg(i_regs->regmap,TLREG);
3356 assert(map>=0);
ea3d2e6e 3357 reglist&=~(1<<map);
535d208a 3358 map=do_tlb_w(c||s<0||offset?temp:s,temp,map,0,c,constmap[i][s]+offset);
3359 if(!c&&!offset&&s>=0) emit_mov(s,temp);
3360 do_tlb_w_branch(map,c,constmap[i][s]+offset,&jaddr);
3361 if(!jaddr&&!memtarget) {
3362 jaddr=(int)out;
3363 emit_jmp(0);
57871462 3364 }
535d208a 3365 gen_tlb_addr_w(temp,map);
3366 }
3367
3368 if (opcode[i]==0x2C||opcode[i]==0x2D) { // SDL/SDR
3369 temp2=get_reg(i_regs->regmap,FTEMP);
3370 if(!rs2[i]) temp2=th=tl;
3371 }
57871462 3372
2002a1db 3373#ifndef BIG_ENDIAN_MIPS
3374 emit_xorimm(temp,3,temp);
3375#endif
535d208a 3376 emit_testimm(temp,2);
3377 case2=(int)out;
3378 emit_jne(0);
3379 emit_testimm(temp,1);
3380 case1=(int)out;
3381 emit_jne(0);
3382 // 0
3383 if (opcode[i]==0x2A) { // SWL
3384 emit_writeword_indexed(tl,0,temp);
3385 }
3386 if (opcode[i]==0x2E) { // SWR
3387 emit_writebyte_indexed(tl,3,temp);
3388 }
3389 if (opcode[i]==0x2C) { // SDL
3390 emit_writeword_indexed(th,0,temp);
3391 if(rs2[i]) emit_mov(tl,temp2);
3392 }
3393 if (opcode[i]==0x2D) { // SDR
3394 emit_writebyte_indexed(tl,3,temp);
3395 if(rs2[i]) emit_shldimm(th,tl,24,temp2);
3396 }
3397 done0=(int)out;
3398 emit_jmp(0);
3399 // 1
3400 set_jump_target(case1,(int)out);
3401 if (opcode[i]==0x2A) { // SWL
3402 // Write 3 msb into three least significant bytes
3403 if(rs2[i]) emit_rorimm(tl,8,tl);
3404 emit_writehword_indexed(tl,-1,temp);
3405 if(rs2[i]) emit_rorimm(tl,16,tl);
3406 emit_writebyte_indexed(tl,1,temp);
3407 if(rs2[i]) emit_rorimm(tl,8,tl);
3408 }
3409 if (opcode[i]==0x2E) { // SWR
3410 // Write two lsb into two most significant bytes
3411 emit_writehword_indexed(tl,1,temp);
3412 }
3413 if (opcode[i]==0x2C) { // SDL
3414 if(rs2[i]) emit_shrdimm(tl,th,8,temp2);
3415 // Write 3 msb into three least significant bytes
3416 if(rs2[i]) emit_rorimm(th,8,th);
3417 emit_writehword_indexed(th,-1,temp);
3418 if(rs2[i]) emit_rorimm(th,16,th);
3419 emit_writebyte_indexed(th,1,temp);
3420 if(rs2[i]) emit_rorimm(th,8,th);
3421 }
3422 if (opcode[i]==0x2D) { // SDR
3423 if(rs2[i]) emit_shldimm(th,tl,16,temp2);
3424 // Write two lsb into two most significant bytes
3425 emit_writehword_indexed(tl,1,temp);
3426 }
3427 done1=(int)out;
3428 emit_jmp(0);
3429 // 2
3430 set_jump_target(case2,(int)out);
3431 emit_testimm(temp,1);
3432 case3=(int)out;
3433 emit_jne(0);
3434 if (opcode[i]==0x2A) { // SWL
3435 // Write two msb into two least significant bytes
3436 if(rs2[i]) emit_rorimm(tl,16,tl);
3437 emit_writehword_indexed(tl,-2,temp);
3438 if(rs2[i]) emit_rorimm(tl,16,tl);
3439 }
3440 if (opcode[i]==0x2E) { // SWR
3441 // Write 3 lsb into three most significant bytes
3442 emit_writebyte_indexed(tl,-1,temp);
3443 if(rs2[i]) emit_rorimm(tl,8,tl);
3444 emit_writehword_indexed(tl,0,temp);
3445 if(rs2[i]) emit_rorimm(tl,24,tl);
3446 }
3447 if (opcode[i]==0x2C) { // SDL
3448 if(rs2[i]) emit_shrdimm(tl,th,16,temp2);
3449 // Write two msb into two least significant bytes
3450 if(rs2[i]) emit_rorimm(th,16,th);
3451 emit_writehword_indexed(th,-2,temp);
3452 if(rs2[i]) emit_rorimm(th,16,th);
3453 }
3454 if (opcode[i]==0x2D) { // SDR
3455 if(rs2[i]) emit_shldimm(th,tl,8,temp2);
3456 // Write 3 lsb into three most significant bytes
3457 emit_writebyte_indexed(tl,-1,temp);
3458 if(rs2[i]) emit_rorimm(tl,8,tl);
3459 emit_writehword_indexed(tl,0,temp);
3460 if(rs2[i]) emit_rorimm(tl,24,tl);
3461 }
3462 done2=(int)out;
3463 emit_jmp(0);
3464 // 3
3465 set_jump_target(case3,(int)out);
3466 if (opcode[i]==0x2A) { // SWL
3467 // Write msb into least significant byte
3468 if(rs2[i]) emit_rorimm(tl,24,tl);
3469 emit_writebyte_indexed(tl,-3,temp);
3470 if(rs2[i]) emit_rorimm(tl,8,tl);
3471 }
3472 if (opcode[i]==0x2E) { // SWR
3473 // Write entire word
3474 emit_writeword_indexed(tl,-3,temp);
3475 }
3476 if (opcode[i]==0x2C) { // SDL
3477 if(rs2[i]) emit_shrdimm(tl,th,24,temp2);
3478 // Write msb into least significant byte
3479 if(rs2[i]) emit_rorimm(th,24,th);
3480 emit_writebyte_indexed(th,-3,temp);
3481 if(rs2[i]) emit_rorimm(th,8,th);
3482 }
3483 if (opcode[i]==0x2D) { // SDR
3484 if(rs2[i]) emit_mov(th,temp2);
3485 // Write entire word
3486 emit_writeword_indexed(tl,-3,temp);
3487 }
3488 set_jump_target(done0,(int)out);
3489 set_jump_target(done1,(int)out);
3490 set_jump_target(done2,(int)out);
3491 if (opcode[i]==0x2C) { // SDL
3492 emit_testimm(temp,4);
57871462 3493 done0=(int)out;
57871462 3494 emit_jne(0);
535d208a 3495 emit_andimm(temp,~3,temp);
3496 emit_writeword_indexed(temp2,4,temp);
3497 set_jump_target(done0,(int)out);
3498 }
3499 if (opcode[i]==0x2D) { // SDR
3500 emit_testimm(temp,4);
3501 done0=(int)out;
3502 emit_jeq(0);
3503 emit_andimm(temp,~3,temp);
3504 emit_writeword_indexed(temp2,-4,temp);
57871462 3505 set_jump_target(done0,(int)out);
57871462 3506 }
535d208a 3507 if(!c||!memtarget)
3508 add_stub(STORELR_STUB,jaddr,(int)out,i,(int)i_regs,temp,ccadj[i],reglist);
57871462 3509 if(!using_tlb) {
535d208a 3510 #ifdef RAM_OFFSET
3511 int map=get_reg(i_regs->regmap,ROREG);
3512 if(map<0) map=HOST_TEMPREG;
3513 gen_orig_addr_w(temp,map);
3514 #else
57871462 3515 emit_addimm_no_flags((u_int)0x80000000-(u_int)rdram,temp);
535d208a 3516 #endif
57871462 3517 #if defined(HOST_IMM8)
3518 int ir=get_reg(i_regs->regmap,INVCP);
3519 assert(ir>=0);
3520 emit_cmpmem_indexedsr12_reg(ir,temp,1);
3521 #else
3522 emit_cmpmem_indexedsr12_imm((int)invalid_code,temp,1);
3523 #endif
535d208a 3524 #if defined(HAVE_CONDITIONAL_CALL) && !defined(DESTRUCTIVE_SHIFT)
3525 emit_callne(invalidate_addr_reg[temp]);
3526 #else
57871462 3527 jaddr2=(int)out;
3528 emit_jne(0);
3529 add_stub(INVCODE_STUB,jaddr2,(int)out,reglist|(1<<HOST_CCREG),temp,0,0,0);
535d208a 3530 #endif
57871462 3531 }
3532 /*
3533 emit_pusha();
3534 //save_regs(0x100f);
3535 emit_readword((int)&last_count,ECX);
3536 if(get_reg(i_regs->regmap,CCREG)<0)
3537 emit_loadreg(CCREG,HOST_CCREG);
3538 emit_add(HOST_CCREG,ECX,HOST_CCREG);
3539 emit_addimm(HOST_CCREG,2*ccadj[i],HOST_CCREG);
3540 emit_writeword(HOST_CCREG,(int)&Count);
3541 emit_call((int)memdebug);
3542 emit_popa();
3543 //restore_regs(0x100f);
3544 /**/
3545}
3546
3547void c1ls_assemble(int i,struct regstat *i_regs)
3548{
3d624f89 3549#ifndef DISABLE_COP1
57871462 3550 int s,th,tl;
3551 int temp,ar;
3552 int map=-1;
3553 int offset;
3554 int c=0;
3555 int jaddr,jaddr2=0,jaddr3,type;
3556 int agr=AGEN1+(i&1);
3557 u_int hr,reglist=0;
3558 th=get_reg(i_regs->regmap,FTEMP|64);
3559 tl=get_reg(i_regs->regmap,FTEMP);
3560 s=get_reg(i_regs->regmap,rs1[i]);
3561 temp=get_reg(i_regs->regmap,agr);
3562 if(temp<0) temp=get_reg(i_regs->regmap,-1);
3563 offset=imm[i];
3564 assert(tl>=0);
3565 assert(rs1[i]>0);
3566 assert(temp>=0);
3567 for(hr=0;hr<HOST_REGS;hr++) {
3568 if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
3569 }
3570 if(i_regs->regmap[HOST_CCREG]==CCREG) reglist&=~(1<<HOST_CCREG);
3571 if (opcode[i]==0x31||opcode[i]==0x35) // LWC1/LDC1
3572 {
3573 // Loads use a temporary register which we need to save
3574 reglist|=1<<temp;
3575 }
3576 if (opcode[i]==0x39||opcode[i]==0x3D) // SWC1/SDC1
3577 ar=temp;
3578 else // LWC1/LDC1
3579 ar=tl;
3580 //if(s<0) emit_loadreg(rs1[i],ar); //address_generation does this now
3581 //else c=(i_regs->wasconst>>s)&1;
3582 if(s>=0) c=(i_regs->wasconst>>s)&1;
3583 // Check cop1 unusable
3584 if(!cop1_usable) {
3585 signed char rs=get_reg(i_regs->regmap,CSREG);
3586 assert(rs>=0);
3587 emit_testimm(rs,0x20000000);
3588 jaddr=(int)out;
3589 emit_jeq(0);
3590 add_stub(FP_STUB,jaddr,(int)out,i,rs,(int)i_regs,is_delayslot,0);
3591 cop1_usable=1;
3592 }
3593 if (opcode[i]==0x39) { // SWC1 (get float address)
3594 emit_readword((int)&reg_cop1_simple[(source[i]>>16)&0x1f],tl);
3595 }
3596 if (opcode[i]==0x3D) { // SDC1 (get double address)
3597 emit_readword((int)&reg_cop1_double[(source[i]>>16)&0x1f],tl);
3598 }
3599 // Generate address + offset
3600 if(!using_tlb) {
3601 if(!c)
4cb76aa4 3602 emit_cmpimm(offset||c||s<0?ar:s,RAM_SIZE);
57871462 3603 }
3604 else
3605 {
3606 map=get_reg(i_regs->regmap,TLREG);
3607 assert(map>=0);
ea3d2e6e 3608 reglist&=~(1<<map);
57871462 3609 if (opcode[i]==0x31||opcode[i]==0x35) { // LWC1/LDC1
3610 map=do_tlb_r(offset||c||s<0?ar:s,ar,map,0,-1,-1,c,constmap[i][s]+offset);
3611 }
3612 if (opcode[i]==0x39||opcode[i]==0x3D) { // SWC1/SDC1
3613 map=do_tlb_w(offset||c||s<0?ar:s,ar,map,0,c,constmap[i][s]+offset);
3614 }
3615 }
3616 if (opcode[i]==0x39) { // SWC1 (read float)
3617 emit_readword_indexed(0,tl,tl);
3618 }
3619 if (opcode[i]==0x3D) { // SDC1 (read double)
3620 emit_readword_indexed(4,tl,th);
3621 emit_readword_indexed(0,tl,tl);
3622 }
3623 if (opcode[i]==0x31) { // LWC1 (get target address)
3624 emit_readword((int)&reg_cop1_simple[(source[i]>>16)&0x1f],temp);
3625 }
3626 if (opcode[i]==0x35) { // LDC1 (get target address)
3627 emit_readword((int)&reg_cop1_double[(source[i]>>16)&0x1f],temp);
3628 }
3629 if(!using_tlb) {
3630 if(!c) {
3631 jaddr2=(int)out;
3632 emit_jno(0);
3633 }
4cb76aa4 3634 else if(((signed int)(constmap[i][s]+offset))>=(signed int)0x80000000+RAM_SIZE) {
57871462 3635 jaddr2=(int)out;
3636 emit_jmp(0); // inline_readstub/inline_writestub? Very rare case
3637 }
3638 #ifdef DESTRUCTIVE_SHIFT
3639 if (opcode[i]==0x39||opcode[i]==0x3D) { // SWC1/SDC1
3640 if(!offset&&!c&&s>=0) emit_mov(s,ar);
3641 }
3642 #endif
3643 }else{
3644 if (opcode[i]==0x31||opcode[i]==0x35) { // LWC1/LDC1
3645 do_tlb_r_branch(map,c,constmap[i][s]+offset,&jaddr2);
3646 }
3647 if (opcode[i]==0x39||opcode[i]==0x3D) { // SWC1/SDC1
3648 do_tlb_w_branch(map,c,constmap[i][s]+offset,&jaddr2);
3649 }
3650 }
3651 if (opcode[i]==0x31) { // LWC1
3652 //if(s>=0&&!c&&!offset) emit_mov(s,tl);
3653 //gen_tlb_addr_r(ar,map);
3654 //emit_readword_indexed((int)rdram-0x80000000,tl,tl);
3655 #ifdef HOST_IMM_ADDR32
3656 if(c) emit_readword_tlb(constmap[i][s]+offset,map,tl);
3657 else
3658 #endif
3659 emit_readword_indexed_tlb(0,offset||c||s<0?tl:s,map,tl);
3660 type=LOADW_STUB;
3661 }
3662 if (opcode[i]==0x35) { // LDC1
3663 assert(th>=0);
3664 //if(s>=0&&!c&&!offset) emit_mov(s,tl);
3665 //gen_tlb_addr_r(ar,map);
3666 //emit_readword_indexed((int)rdram-0x80000000,tl,th);
3667 //emit_readword_indexed((int)rdram-0x7FFFFFFC,tl,tl);
3668 #ifdef HOST_IMM_ADDR32
3669 if(c) emit_readdword_tlb(constmap[i][s]+offset,map,th,tl);
3670 else
3671 #endif
3672 emit_readdword_indexed_tlb(0,offset||c||s<0?tl:s,map,th,tl);
3673 type=LOADD_STUB;
3674 }
3675 if (opcode[i]==0x39) { // SWC1
3676 //emit_writeword_indexed(tl,(int)rdram-0x80000000,temp);
3677 emit_writeword_indexed_tlb(tl,0,offset||c||s<0?temp:s,map,temp);
3678 type=STOREW_STUB;
3679 }
3680 if (opcode[i]==0x3D) { // SDC1
3681 assert(th>=0);
3682 //emit_writeword_indexed(th,(int)rdram-0x80000000,temp);
3683 //emit_writeword_indexed(tl,(int)rdram-0x7FFFFFFC,temp);
3684 emit_writedword_indexed_tlb(th,tl,0,offset||c||s<0?temp:s,map,temp);
3685 type=STORED_STUB;
3686 }
3687 if(!using_tlb) {
3688 if (opcode[i]==0x39||opcode[i]==0x3D) { // SWC1/SDC1
3689 #ifndef DESTRUCTIVE_SHIFT
3690 temp=offset||c||s<0?ar:s;
3691 #endif
3692 #if defined(HOST_IMM8)
3693 int ir=get_reg(i_regs->regmap,INVCP);
3694 assert(ir>=0);
3695 emit_cmpmem_indexedsr12_reg(ir,temp,1);
3696 #else
3697 emit_cmpmem_indexedsr12_imm((int)invalid_code,temp,1);
3698 #endif
0bbd1454 3699 #if defined(HAVE_CONDITIONAL_CALL) && !defined(DESTRUCTIVE_SHIFT)
3700 emit_callne(invalidate_addr_reg[temp]);
3701 #else
57871462 3702 jaddr3=(int)out;
3703 emit_jne(0);
3704 add_stub(INVCODE_STUB,jaddr3,(int)out,reglist|(1<<HOST_CCREG),temp,0,0,0);
0bbd1454 3705 #endif
57871462 3706 }
3707 }
3708 if(jaddr2) add_stub(type,jaddr2,(int)out,i,offset||c||s<0?ar:s,(int)i_regs,ccadj[i],reglist);
3709 if (opcode[i]==0x31) { // LWC1 (write float)
3710 emit_writeword_indexed(tl,0,temp);
3711 }
3712 if (opcode[i]==0x35) { // LDC1 (write double)
3713 emit_writeword_indexed(th,4,temp);
3714 emit_writeword_indexed(tl,0,temp);
3715 }
3716 //if(opcode[i]==0x39)
3717 /*if(opcode[i]==0x39||opcode[i]==0x31)
3718 {
3719 emit_pusha();
3720 emit_readword((int)&last_count,ECX);
3721 if(get_reg(i_regs->regmap,CCREG)<0)
3722 emit_loadreg(CCREG,HOST_CCREG);
3723 emit_add(HOST_CCREG,ECX,HOST_CCREG);
3724 emit_addimm(HOST_CCREG,2*ccadj[i],HOST_CCREG);
3725 emit_writeword(HOST_CCREG,(int)&Count);
3726 emit_call((int)memdebug);
3727 emit_popa();
3728 }/**/
3d624f89 3729#else
3730 cop1_unusable(i, i_regs);
3731#endif
57871462 3732}
3733
b9b61529 3734void c2ls_assemble(int i,struct regstat *i_regs)
3735{
3736 int s,tl;
3737 int ar;
3738 int offset;
1fd1aceb 3739 int memtarget=0,c=0;
c2e3bd42 3740 int jaddr2=0,jaddr3,type;
b9b61529 3741 int agr=AGEN1+(i&1);
3742 u_int hr,reglist=0;
3743 u_int copr=(source[i]>>16)&0x1f;
3744 s=get_reg(i_regs->regmap,rs1[i]);
3745 tl=get_reg(i_regs->regmap,FTEMP);
3746 offset=imm[i];
3747 assert(rs1[i]>0);
3748 assert(tl>=0);
3749 assert(!using_tlb);
3750
3751 for(hr=0;hr<HOST_REGS;hr++) {
3752 if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
3753 }
3754 if(i_regs->regmap[HOST_CCREG]==CCREG)
3755 reglist&=~(1<<HOST_CCREG);
3756
3757 // get the address
3758 if (opcode[i]==0x3a) { // SWC2
3759 ar=get_reg(i_regs->regmap,agr);
3760 if(ar<0) ar=get_reg(i_regs->regmap,-1);
3761 reglist|=1<<ar;
3762 } else { // LWC2
3763 ar=tl;
3764 }
1fd1aceb 3765 if(s>=0) c=(i_regs->wasconst>>s)&1;
3766 memtarget=c&&(((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE);
b9b61529 3767 if (!offset&&!c&&s>=0) ar=s;
3768 assert(ar>=0);
3769
3770 if (opcode[i]==0x3a) { // SWC2
3771 cop2_get_dreg(copr,tl,HOST_TEMPREG);
1fd1aceb 3772 type=STOREW_STUB;
b9b61529 3773 }
1fd1aceb 3774 else
b9b61529 3775 type=LOADW_STUB;
1fd1aceb 3776
3777 if(c&&!memtarget) {
3778 jaddr2=(int)out;
3779 emit_jmp(0); // inline_readstub/inline_writestub?
b9b61529 3780 }
1fd1aceb 3781 else {
3782 if(!c) {
3783 emit_cmpimm(offset||c||s<0?ar:s,RAM_SIZE);
3784 jaddr2=(int)out;
3785 emit_jno(0);
3786 }
3787 if (opcode[i]==0x32) { // LWC2
3788 #ifdef HOST_IMM_ADDR32
3789 if(c) emit_readword_tlb(constmap[i][s]+offset,-1,tl);
3790 else
3791 #endif
3792 emit_readword_indexed(0,ar,tl);
3793 }
3794 if (opcode[i]==0x3a) { // SWC2
3795 #ifdef DESTRUCTIVE_SHIFT
3796 if(!offset&&!c&&s>=0) emit_mov(s,ar);
3797 #endif
3798 emit_writeword_indexed(tl,0,ar);
3799 }
b9b61529 3800 }
3801 if(jaddr2)
3802 add_stub(type,jaddr2,(int)out,i,ar,(int)i_regs,ccadj[i],reglist);
3803 if (opcode[i]==0x3a) { // SWC2
3804#if defined(HOST_IMM8)
3805 int ir=get_reg(i_regs->regmap,INVCP);
3806 assert(ir>=0);
3807 emit_cmpmem_indexedsr12_reg(ir,ar,1);
3808#else
3809 emit_cmpmem_indexedsr12_imm((int)invalid_code,ar,1);
3810#endif
0bbd1454 3811 #if defined(HAVE_CONDITIONAL_CALL) && !defined(DESTRUCTIVE_SHIFT)
3812 emit_callne(invalidate_addr_reg[ar]);
3813 #else
b9b61529 3814 jaddr3=(int)out;
3815 emit_jne(0);
3816 add_stub(INVCODE_STUB,jaddr3,(int)out,reglist|(1<<HOST_CCREG),ar,0,0,0);
0bbd1454 3817 #endif
b9b61529 3818 }
3819 if (opcode[i]==0x32) { // LWC2
3820 cop2_put_dreg(copr,tl,HOST_TEMPREG);
3821 }
3822}
3823
57871462 3824#ifndef multdiv_assemble
3825void multdiv_assemble(int i,struct regstat *i_regs)
3826{
3827 printf("Need multdiv_assemble for this architecture.\n");
3828 exit(1);
3829}
3830#endif
3831
3832void mov_assemble(int i,struct regstat *i_regs)
3833{
3834 //if(opcode2[i]==0x10||opcode2[i]==0x12) { // MFHI/MFLO
3835 //if(opcode2[i]==0x11||opcode2[i]==0x13) { // MTHI/MTLO
57871462 3836 if(rt1[i]) {
3837 signed char sh,sl,th,tl;
3838 th=get_reg(i_regs->regmap,rt1[i]|64);
3839 tl=get_reg(i_regs->regmap,rt1[i]);
3840 //assert(tl>=0);
3841 if(tl>=0) {
3842 sh=get_reg(i_regs->regmap,rs1[i]|64);
3843 sl=get_reg(i_regs->regmap,rs1[i]);
3844 if(sl>=0) emit_mov(sl,tl);
3845 else emit_loadreg(rs1[i],tl);
3846 if(th>=0) {
3847 if(sh>=0) emit_mov(sh,th);
3848 else emit_loadreg(rs1[i]|64,th);
3849 }
3850 }
3851 }
3852}
3853
3854#ifndef fconv_assemble
3855void fconv_assemble(int i,struct regstat *i_regs)
3856{
3857 printf("Need fconv_assemble for this architecture.\n");
3858 exit(1);
3859}
3860#endif
3861
3862#if 0
3863void float_assemble(int i,struct regstat *i_regs)
3864{
3865 printf("Need float_assemble for this architecture.\n");
3866 exit(1);
3867}
3868#endif
3869
3870void syscall_assemble(int i,struct regstat *i_regs)
3871{
3872 signed char ccreg=get_reg(i_regs->regmap,CCREG);
3873 assert(ccreg==HOST_CCREG);
3874 assert(!is_delayslot);
3875 emit_movimm(start+i*4,EAX); // Get PC
3876 emit_addimm(HOST_CCREG,CLOCK_DIVIDER*ccadj[i],HOST_CCREG); // CHECK: is this right? There should probably be an extra cycle...
7139f3c8 3877 emit_jmp((int)jump_syscall_hle); // XXX
3878}
3879
3880void hlecall_assemble(int i,struct regstat *i_regs)
3881{
3882 signed char ccreg=get_reg(i_regs->regmap,CCREG);
3883 assert(ccreg==HOST_CCREG);
3884 assert(!is_delayslot);
3885 emit_movimm(start+i*4+4,0); // Get PC
67ba0fb4 3886 emit_movimm((int)psxHLEt[source[i]&7],1);
7139f3c8 3887 emit_addimm(HOST_CCREG,CLOCK_DIVIDER*ccadj[i],HOST_CCREG); // XXX
67ba0fb4 3888 emit_jmp((int)jump_hlecall);
57871462 3889}
3890
1e973cb0 3891void intcall_assemble(int i,struct regstat *i_regs)
3892{
3893 signed char ccreg=get_reg(i_regs->regmap,CCREG);
3894 assert(ccreg==HOST_CCREG);
3895 assert(!is_delayslot);
3896 emit_movimm(start+i*4,0); // Get PC
3897 emit_addimm(HOST_CCREG,CLOCK_DIVIDER*ccadj[i],HOST_CCREG);
3898 emit_jmp((int)jump_intcall);
3899}
3900
57871462 3901void ds_assemble(int i,struct regstat *i_regs)
3902{
3903 is_delayslot=1;
3904 switch(itype[i]) {
3905 case ALU:
3906 alu_assemble(i,i_regs);break;
3907 case IMM16:
3908 imm16_assemble(i,i_regs);break;
3909 case SHIFT:
3910 shift_assemble(i,i_regs);break;
3911 case SHIFTIMM:
3912 shiftimm_assemble(i,i_regs);break;
3913 case LOAD:
3914 load_assemble(i,i_regs);break;
3915 case LOADLR:
3916 loadlr_assemble(i,i_regs);break;
3917 case STORE:
3918 store_assemble(i,i_regs);break;
3919 case STORELR:
3920 storelr_assemble(i,i_regs);break;
3921 case COP0:
3922 cop0_assemble(i,i_regs);break;
3923 case COP1:
3924 cop1_assemble(i,i_regs);break;
3925 case C1LS:
3926 c1ls_assemble(i,i_regs);break;
b9b61529 3927 case COP2:
3928 cop2_assemble(i,i_regs);break;
3929 case C2LS:
3930 c2ls_assemble(i,i_regs);break;
3931 case C2OP:
3932 c2op_assemble(i,i_regs);break;
57871462 3933 case FCONV:
3934 fconv_assemble(i,i_regs);break;
3935 case FLOAT:
3936 float_assemble(i,i_regs);break;
3937 case FCOMP:
3938 fcomp_assemble(i,i_regs);break;
3939 case MULTDIV:
3940 multdiv_assemble(i,i_regs);break;
3941 case MOV:
3942 mov_assemble(i,i_regs);break;
3943 case SYSCALL:
7139f3c8 3944 case HLECALL:
1e973cb0 3945 case INTCALL:
57871462 3946 case SPAN:
3947 case UJUMP:
3948 case RJUMP:
3949 case CJUMP:
3950 case SJUMP:
3951 case FJUMP:
3952 printf("Jump in the delay slot. This is probably a bug.\n");
3953 }
3954 is_delayslot=0;
3955}
3956
3957// Is the branch target a valid internal jump?
3958int internal_branch(uint64_t i_is32,int addr)
3959{
3960 if(addr&1) return 0; // Indirect (register) jump
3961 if(addr>=start && addr<start+slen*4-4)
3962 {
3963 int t=(addr-start)>>2;
3964 // Delay slots are not valid branch targets
3965 //if(t>0&&(itype[t-1]==RJUMP||itype[t-1]==UJUMP||itype[t-1]==CJUMP||itype[t-1]==SJUMP||itype[t-1]==FJUMP)) return 0;
3966 // 64 -> 32 bit transition requires a recompile
3967 /*if(is32[t]&~unneeded_reg_upper[t]&~i_is32)
3968 {
3969 if(requires_32bit[t]&~i_is32) printf("optimizable: no\n");
3970 else printf("optimizable: yes\n");
3971 }*/
3972 //if(is32[t]&~unneeded_reg_upper[t]&~i_is32) return 0;
a28c6ce8 3973#ifndef FORCE32
57871462 3974 if(requires_32bit[t]&~i_is32) return 0;
a28c6ce8 3975 else
3976#endif
3977 return 1;
57871462 3978 }
3979 return 0;
3980}
3981
3982#ifndef wb_invalidate
3983void wb_invalidate(signed char pre[],signed char entry[],uint64_t dirty,uint64_t is32,
3984 uint64_t u,uint64_t uu)
3985{
3986 int hr;
3987 for(hr=0;hr<HOST_REGS;hr++) {
3988 if(hr!=EXCLUDE_REG) {
3989 if(pre[hr]!=entry[hr]) {
3990 if(pre[hr]>=0) {
3991 if((dirty>>hr)&1) {
3992 if(get_reg(entry,pre[hr])<0) {
3993 if(pre[hr]<64) {
3994 if(!((u>>pre[hr])&1)) {
3995 emit_storereg(pre[hr],hr);
3996 if( ((is32>>pre[hr])&1) && !((uu>>pre[hr])&1) ) {
3997 emit_sarimm(hr,31,hr);
3998 emit_storereg(pre[hr]|64,hr);
3999 }
4000 }
4001 }else{
4002 if(!((uu>>(pre[hr]&63))&1) && !((is32>>(pre[hr]&63))&1)) {
4003 emit_storereg(pre[hr],hr);
4004 }
4005 }
4006 }
4007 }
4008 }
4009 }
4010 }
4011 }
4012 // Move from one register to another (no writeback)
4013 for(hr=0;hr<HOST_REGS;hr++) {
4014 if(hr!=EXCLUDE_REG) {
4015 if(pre[hr]!=entry[hr]) {
4016 if(pre[hr]>=0&&(pre[hr]&63)<TEMPREG) {
4017 int nr;
4018 if((nr=get_reg(entry,pre[hr]))>=0) {
4019 emit_mov(hr,nr);
4020 }
4021 }
4022 }
4023 }
4024 }
4025}
4026#endif
4027
4028// Load the specified registers
4029// This only loads the registers given as arguments because
4030// we don't want to load things that will be overwritten
4031void load_regs(signed char entry[],signed char regmap[],int is32,int rs1,int rs2)
4032{
4033 int hr;
4034 // Load 32-bit regs
4035 for(hr=0;hr<HOST_REGS;hr++) {
4036 if(hr!=EXCLUDE_REG&&regmap[hr]>=0) {
4037 if(entry[hr]!=regmap[hr]) {
4038 if(regmap[hr]==rs1||regmap[hr]==rs2)
4039 {
4040 if(regmap[hr]==0) {
4041 emit_zeroreg(hr);
4042 }
4043 else
4044 {
4045 emit_loadreg(regmap[hr],hr);
4046 }
4047 }
4048 }
4049 }
4050 }
4051 //Load 64-bit regs
4052 for(hr=0;hr<HOST_REGS;hr++) {
4053 if(hr!=EXCLUDE_REG&&regmap[hr]>=0) {
4054 if(entry[hr]!=regmap[hr]) {
4055 if(regmap[hr]-64==rs1||regmap[hr]-64==rs2)
4056 {
4057 assert(regmap[hr]!=64);
4058 if((is32>>(regmap[hr]&63))&1) {
4059 int lr=get_reg(regmap,regmap[hr]-64);
4060 if(lr>=0)
4061 emit_sarimm(lr,31,hr);
4062 else
4063 emit_loadreg(regmap[hr],hr);
4064 }
4065 else
4066 {
4067 emit_loadreg(regmap[hr],hr);
4068 }
4069 }
4070 }
4071 }
4072 }
4073}
4074
4075// Load registers prior to the start of a loop
4076// so that they are not loaded within the loop
4077static void loop_preload(signed char pre[],signed char entry[])
4078{
4079 int hr;
4080 for(hr=0;hr<HOST_REGS;hr++) {
4081 if(hr!=EXCLUDE_REG) {
4082 if(pre[hr]!=entry[hr]) {
4083 if(entry[hr]>=0) {
4084 if(get_reg(pre,entry[hr])<0) {
4085 assem_debug("loop preload:\n");
4086 //printf("loop preload: %d\n",hr);
4087 if(entry[hr]==0) {
4088 emit_zeroreg(hr);
4089 }
4090 else if(entry[hr]<TEMPREG)
4091 {
4092 emit_loadreg(entry[hr],hr);
4093 }
4094 else if(entry[hr]-64<TEMPREG)
4095 {
4096 emit_loadreg(entry[hr],hr);
4097 }
4098 }
4099 }
4100 }
4101 }
4102 }
4103}
4104
4105// Generate address for load/store instruction
b9b61529 4106// goes to AGEN for writes, FTEMP for LOADLR and cop1/2 loads
57871462 4107void address_generation(int i,struct regstat *i_regs,signed char entry[])
4108{
b9b61529 4109 if(itype[i]==LOAD||itype[i]==LOADLR||itype[i]==STORE||itype[i]==STORELR||itype[i]==C1LS||itype[i]==C2LS) {
5194fb95 4110 int ra=-1;
57871462 4111 int agr=AGEN1+(i&1);
4112 int mgr=MGEN1+(i&1);
4113 if(itype[i]==LOAD) {
4114 ra=get_reg(i_regs->regmap,rt1[i]);
535d208a 4115 if(ra<0) ra=get_reg(i_regs->regmap,-1);
4116 assert(ra>=0);
57871462 4117 }
4118 if(itype[i]==LOADLR) {
4119 ra=get_reg(i_regs->regmap,FTEMP);
4120 }
4121 if(itype[i]==STORE||itype[i]==STORELR) {
4122 ra=get_reg(i_regs->regmap,agr);
4123 if(ra<0) ra=get_reg(i_regs->regmap,-1);
4124 }
b9b61529 4125 if(itype[i]==C1LS||itype[i]==C2LS) {
4126 if ((opcode[i]&0x3b)==0x31||(opcode[i]&0x3b)==0x32) // LWC1/LDC1/LWC2/LDC2
57871462 4127 ra=get_reg(i_regs->regmap,FTEMP);
1fd1aceb 4128 else { // SWC1/SDC1/SWC2/SDC2
57871462 4129 ra=get_reg(i_regs->regmap,agr);
4130 if(ra<0) ra=get_reg(i_regs->regmap,-1);
4131 }
4132 }
4133 int rs=get_reg(i_regs->regmap,rs1[i]);
4134 int rm=get_reg(i_regs->regmap,TLREG);
4135 if(ra>=0) {
4136 int offset=imm[i];
4137 int c=(i_regs->wasconst>>rs)&1;
4138 if(rs1[i]==0) {
4139 // Using r0 as a base address
4140 /*if(rm>=0) {
4141 if(!entry||entry[rm]!=mgr) {
4142 generate_map_const(offset,rm);
4143 } // else did it in the previous cycle
4144 }*/
4145 if(!entry||entry[ra]!=agr) {
4146 if (opcode[i]==0x22||opcode[i]==0x26) {
4147 emit_movimm(offset&0xFFFFFFFC,ra); // LWL/LWR
4148 }else if (opcode[i]==0x1a||opcode[i]==0x1b) {
4149 emit_movimm(offset&0xFFFFFFF8,ra); // LDL/LDR
4150 }else{
4151 emit_movimm(offset,ra);
4152 }
4153 } // else did it in the previous cycle
4154 }
4155 else if(rs<0) {
4156 if(!entry||entry[ra]!=rs1[i])
4157 emit_loadreg(rs1[i],ra);
4158 //if(!entry||entry[ra]!=rs1[i])
4159 // printf("poor load scheduling!\n");
4160 }
4161 else if(c) {
4162 if(rm>=0) {
4163 if(!entry||entry[rm]!=mgr) {
b9b61529 4164 if(itype[i]==STORE||itype[i]==STORELR||(opcode[i]&0x3b)==0x39||(opcode[i]&0x3b)==0x3a) {
57871462 4165 // Stores to memory go thru the mapper to detect self-modifying
4166 // code, loads don't.
4167 if((unsigned int)(constmap[i][rs]+offset)>=0xC0000000 ||
4cb76aa4 4168 (unsigned int)(constmap[i][rs]+offset)<0x80000000+RAM_SIZE )
57871462 4169 generate_map_const(constmap[i][rs]+offset,rm);
4170 }else{
4171 if((signed int)(constmap[i][rs]+offset)>=(signed int)0xC0000000)
4172 generate_map_const(constmap[i][rs]+offset,rm);
4173 }
4174 }
4175 }
4176 if(rs1[i]!=rt1[i]||itype[i]!=LOAD) {
4177 if(!entry||entry[ra]!=agr) {
4178 if (opcode[i]==0x22||opcode[i]==0x26) {
4179 emit_movimm((constmap[i][rs]+offset)&0xFFFFFFFC,ra); // LWL/LWR
4180 }else if (opcode[i]==0x1a||opcode[i]==0x1b) {
4181 emit_movimm((constmap[i][rs]+offset)&0xFFFFFFF8,ra); // LDL/LDR
4182 }else{
4183 #ifdef HOST_IMM_ADDR32
b9b61529 4184 if((itype[i]!=LOAD&&(opcode[i]&0x3b)!=0x31&&(opcode[i]&0x3b)!=0x32) || // LWC1/LDC1/LWC2/LDC2
57871462 4185 (using_tlb&&((signed int)constmap[i][rs]+offset)>=(signed int)0xC0000000))
4186 #endif
4187 emit_movimm(constmap[i][rs]+offset,ra);
4188 }
4189 } // else did it in the previous cycle
4190 } // else load_consts already did it
4191 }
4192 if(offset&&!c&&rs1[i]) {
4193 if(rs>=0) {
4194 emit_addimm(rs,offset,ra);
4195 }else{
4196 emit_addimm(ra,offset,ra);
4197 }
4198 }
4199 }
4200 }
4201 // Preload constants for next instruction
b9b61529 4202 if(itype[i+1]==LOAD||itype[i+1]==LOADLR||itype[i+1]==STORE||itype[i+1]==STORELR||itype[i+1]==C1LS||itype[i+1]==C2LS) {
57871462 4203 int agr,ra;
4204 #ifndef HOST_IMM_ADDR32
4205 // Mapper entry
4206 agr=MGEN1+((i+1)&1);
4207 ra=get_reg(i_regs->regmap,agr);
4208 if(ra>=0) {
4209 int rs=get_reg(regs[i+1].regmap,rs1[i+1]);
4210 int offset=imm[i+1];
4211 int c=(regs[i+1].wasconst>>rs)&1;
4212 if(c) {
b9b61529 4213 if(itype[i+1]==STORE||itype[i+1]==STORELR
4214 ||(opcode[i+1]&0x3b)==0x39||(opcode[i+1]&0x3b)==0x3a) { // SWC1/SDC1, SWC2/SDC2
57871462 4215 // Stores to memory go thru the mapper to detect self-modifying
4216 // code, loads don't.
4217 if((unsigned int)(constmap[i+1][rs]+offset)>=0xC0000000 ||
4cb76aa4 4218 (unsigned int)(constmap[i+1][rs]+offset)<0x80000000+RAM_SIZE )
57871462 4219 generate_map_const(constmap[i+1][rs]+offset,ra);
4220 }else{
4221 if((signed int)(constmap[i+1][rs]+offset)>=(signed int)0xC0000000)
4222 generate_map_const(constmap[i+1][rs]+offset,ra);
4223 }
4224 }
4225 /*else if(rs1[i]==0) {
4226 generate_map_const(offset,ra);
4227 }*/
4228 }
4229 #endif
4230 // Actual address
4231 agr=AGEN1+((i+1)&1);
4232 ra=get_reg(i_regs->regmap,agr);
4233 if(ra>=0) {
4234 int rs=get_reg(regs[i+1].regmap,rs1[i+1]);
4235 int offset=imm[i+1];
4236 int c=(regs[i+1].wasconst>>rs)&1;
4237 if(c&&(rs1[i+1]!=rt1[i+1]||itype[i+1]!=LOAD)) {
4238 if (opcode[i+1]==0x22||opcode[i+1]==0x26) {
4239 emit_movimm((constmap[i+1][rs]+offset)&0xFFFFFFFC,ra); // LWL/LWR
4240 }else if (opcode[i+1]==0x1a||opcode[i+1]==0x1b) {
4241 emit_movimm((constmap[i+1][rs]+offset)&0xFFFFFFF8,ra); // LDL/LDR
4242 }else{
4243 #ifdef HOST_IMM_ADDR32
b9b61529 4244 if((itype[i+1]!=LOAD&&(opcode[i+1]&0x3b)!=0x31&&(opcode[i+1]&0x3b)!=0x32) || // LWC1/LDC1/LWC2/LDC2
57871462 4245 (using_tlb&&((signed int)constmap[i+1][rs]+offset)>=(signed int)0xC0000000))
4246 #endif
4247 emit_movimm(constmap[i+1][rs]+offset,ra);
4248 }
4249 }
4250 else if(rs1[i+1]==0) {
4251 // Using r0 as a base address
4252 if (opcode[i+1]==0x22||opcode[i+1]==0x26) {
4253 emit_movimm(offset&0xFFFFFFFC,ra); // LWL/LWR
4254 }else if (opcode[i+1]==0x1a||opcode[i+1]==0x1b) {
4255 emit_movimm(offset&0xFFFFFFF8,ra); // LDL/LDR
4256 }else{
4257 emit_movimm(offset,ra);
4258 }
4259 }
4260 }
4261 }
4262}
4263
4264int get_final_value(int hr, int i, int *value)
4265{
4266 int reg=regs[i].regmap[hr];
4267 while(i<slen-1) {
4268 if(regs[i+1].regmap[hr]!=reg) break;
4269 if(!((regs[i+1].isconst>>hr)&1)) break;
4270 if(bt[i+1]) break;
4271 i++;
4272 }
4273 if(i<slen-1) {
4274 if(itype[i]==UJUMP||itype[i]==RJUMP||itype[i]==CJUMP||itype[i]==SJUMP) {
4275 *value=constmap[i][hr];
4276 return 1;
4277 }
4278 if(!bt[i+1]) {
4279 if(itype[i+1]==UJUMP||itype[i+1]==RJUMP||itype[i+1]==CJUMP||itype[i+1]==SJUMP) {
4280 // Load in delay slot, out-of-order execution
4281 if(itype[i+2]==LOAD&&rs1[i+2]==reg&&rt1[i+2]==reg&&((regs[i+1].wasconst>>hr)&1))
4282 {
4283 #ifdef HOST_IMM_ADDR32
4284 if(!using_tlb||((signed int)constmap[i][hr]+imm[i+2])<(signed int)0xC0000000) return 0;
4285 #endif
4286 // Precompute load address
4287 *value=constmap[i][hr]+imm[i+2];
4288 return 1;
4289 }
4290 }
4291 if(itype[i+1]==LOAD&&rs1[i+1]==reg&&rt1[i+1]==reg)
4292 {
4293 #ifdef HOST_IMM_ADDR32
4294 if(!using_tlb||((signed int)constmap[i][hr]+imm[i+1])<(signed int)0xC0000000) return 0;
4295 #endif
4296 // Precompute load address
4297 *value=constmap[i][hr]+imm[i+1];
4298 //printf("c=%x imm=%x\n",(int)constmap[i][hr],imm[i+1]);
4299 return 1;
4300 }
4301 }
4302 }
4303 *value=constmap[i][hr];
4304 //printf("c=%x\n",(int)constmap[i][hr]);
4305 if(i==slen-1) return 1;
4306 if(reg<64) {
4307 return !((unneeded_reg[i+1]>>reg)&1);
4308 }else{
4309 return !((unneeded_reg_upper[i+1]>>reg)&1);
4310 }
4311}
4312
4313// Load registers with known constants
4314void load_consts(signed char pre[],signed char regmap[],int is32,int i)
4315{
4316 int hr;
4317 // Load 32-bit regs
4318 for(hr=0;hr<HOST_REGS;hr++) {
4319 if(hr!=EXCLUDE_REG&&regmap[hr]>=0) {
4320 //if(entry[hr]!=regmap[hr]) {
4321 if(i==0||!((regs[i-1].isconst>>hr)&1)||pre[hr]!=regmap[hr]||bt[i]) {
4322 if(((regs[i].isconst>>hr)&1)&&regmap[hr]<64&&regmap[hr]>0) {
4323 int value;
4324 if(get_final_value(hr,i,&value)) {
4325 if(value==0) {
4326 emit_zeroreg(hr);
4327 }
4328 else {
4329 emit_movimm(value,hr);
4330 }
4331 }
4332 }
4333 }
4334 }
4335 }
4336 // Load 64-bit regs
4337 for(hr=0;hr<HOST_REGS;hr++) {
4338 if(hr!=EXCLUDE_REG&&regmap[hr]>=0) {
4339 //if(entry[hr]!=regmap[hr]) {
4340 if(i==0||!((regs[i-1].isconst>>hr)&1)||pre[hr]!=regmap[hr]||bt[i]) {
4341 if(((regs[i].isconst>>hr)&1)&&regmap[hr]>64) {
4342 if((is32>>(regmap[hr]&63))&1) {
4343 int lr=get_reg(regmap,regmap[hr]-64);
4344 assert(lr>=0);
4345 emit_sarimm(lr,31,hr);
4346 }
4347 else
4348 {
4349 int value;
4350 if(get_final_value(hr,i,&value)) {
4351 if(value==0) {
4352 emit_zeroreg(hr);
4353 }
4354 else {
4355 emit_movimm(value,hr);
4356 }
4357 }
4358 }
4359 }
4360 }
4361 }
4362 }
4363}
4364void load_all_consts(signed char regmap[],int is32,u_int dirty,int i)
4365{
4366 int hr;
4367 // Load 32-bit regs
4368 for(hr=0;hr<HOST_REGS;hr++) {
4369 if(hr!=EXCLUDE_REG&&regmap[hr]>=0&&((dirty>>hr)&1)) {
4370 if(((regs[i].isconst>>hr)&1)&&regmap[hr]<64&&regmap[hr]>0) {
4371 int value=constmap[i][hr];
4372 if(value==0) {
4373 emit_zeroreg(hr);
4374 }
4375 else {
4376 emit_movimm(value,hr);
4377 }
4378 }
4379 }
4380 }
4381 // Load 64-bit regs
4382 for(hr=0;hr<HOST_REGS;hr++) {
4383 if(hr!=EXCLUDE_REG&&regmap[hr]>=0&&((dirty>>hr)&1)) {
4384 if(((regs[i].isconst>>hr)&1)&&regmap[hr]>64) {
4385 if((is32>>(regmap[hr]&63))&1) {
4386 int lr=get_reg(regmap,regmap[hr]-64);
4387 assert(lr>=0);
4388 emit_sarimm(lr,31,hr);
4389 }
4390 else
4391 {
4392 int value=constmap[i][hr];
4393 if(value==0) {
4394 emit_zeroreg(hr);
4395 }
4396 else {
4397 emit_movimm(value,hr);
4398 }
4399 }
4400 }
4401 }
4402 }
4403}
4404
4405// Write out all dirty registers (except cycle count)
4406void wb_dirtys(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty)
4407{
4408 int hr;
4409 for(hr=0;hr<HOST_REGS;hr++) {
4410 if(hr!=EXCLUDE_REG) {
4411 if(i_regmap[hr]>0) {
4412 if(i_regmap[hr]!=CCREG) {
4413 if((i_dirty>>hr)&1) {
4414 if(i_regmap[hr]<64) {
4415 emit_storereg(i_regmap[hr],hr);
24385cae 4416#ifndef FORCE32
57871462 4417 if( ((i_is32>>i_regmap[hr])&1) ) {
4418 #ifdef DESTRUCTIVE_WRITEBACK
4419 emit_sarimm(hr,31,hr);
4420 emit_storereg(i_regmap[hr]|64,hr);
4421 #else
4422 emit_sarimm(hr,31,HOST_TEMPREG);
4423 emit_storereg(i_regmap[hr]|64,HOST_TEMPREG);
4424 #endif
4425 }
24385cae 4426#endif
57871462 4427 }else{
4428 if( !((i_is32>>(i_regmap[hr]&63))&1) ) {
4429 emit_storereg(i_regmap[hr],hr);
4430 }
4431 }
4432 }
4433 }
4434 }
4435 }
4436 }
4437}
4438// Write out dirty registers that we need to reload (pair with load_needed_regs)
4439// This writes the registers not written by store_regs_bt
4440void wb_needed_dirtys(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr)
4441{
4442 int hr;
4443 int t=(addr-start)>>2;
4444 for(hr=0;hr<HOST_REGS;hr++) {
4445 if(hr!=EXCLUDE_REG) {
4446 if(i_regmap[hr]>0) {
4447 if(i_regmap[hr]!=CCREG) {
4448 if(i_regmap[hr]==regs[t].regmap_entry[hr] && ((regs[t].dirty>>hr)&1) && !(((i_is32&~regs[t].was32&~unneeded_reg_upper[t])>>(i_regmap[hr]&63))&1)) {
4449 if((i_dirty>>hr)&1) {
4450 if(i_regmap[hr]<64) {
4451 emit_storereg(i_regmap[hr],hr);
24385cae 4452#ifndef FORCE32
57871462 4453 if( ((i_is32>>i_regmap[hr])&1) ) {
4454 #ifdef DESTRUCTIVE_WRITEBACK
4455 emit_sarimm(hr,31,hr);
4456 emit_storereg(i_regmap[hr]|64,hr);
4457 #else
4458 emit_sarimm(hr,31,HOST_TEMPREG);
4459 emit_storereg(i_regmap[hr]|64,HOST_TEMPREG);
4460 #endif
4461 }
24385cae 4462#endif
57871462 4463 }else{
4464 if( !((i_is32>>(i_regmap[hr]&63))&1) ) {
4465 emit_storereg(i_regmap[hr],hr);
4466 }
4467 }
4468 }
4469 }
4470 }
4471 }
4472 }
4473 }
4474}
4475
4476// Load all registers (except cycle count)
4477void load_all_regs(signed char i_regmap[])
4478{
4479 int hr;
4480 for(hr=0;hr<HOST_REGS;hr++) {
4481 if(hr!=EXCLUDE_REG) {
4482 if(i_regmap[hr]==0) {
4483 emit_zeroreg(hr);
4484 }
4485 else
ea3d2e6e 4486 if(i_regmap[hr]>0 && (i_regmap[hr]&63)<TEMPREG && i_regmap[hr]!=CCREG)
57871462 4487 {
4488 emit_loadreg(i_regmap[hr],hr);
4489 }
4490 }
4491 }
4492}
4493
4494// Load all current registers also needed by next instruction
4495void load_needed_regs(signed char i_regmap[],signed char next_regmap[])
4496{
4497 int hr;
4498 for(hr=0;hr<HOST_REGS;hr++) {
4499 if(hr!=EXCLUDE_REG) {
4500 if(get_reg(next_regmap,i_regmap[hr])>=0) {
4501 if(i_regmap[hr]==0) {
4502 emit_zeroreg(hr);
4503 }
4504 else
ea3d2e6e 4505 if(i_regmap[hr]>0 && (i_regmap[hr]&63)<TEMPREG && i_regmap[hr]!=CCREG)
57871462 4506 {
4507 emit_loadreg(i_regmap[hr],hr);
4508 }
4509 }
4510 }
4511 }
4512}
4513
4514// Load all regs, storing cycle count if necessary
4515void load_regs_entry(int t)
4516{
4517 int hr;
4518 if(is_ds[t]) emit_addimm(HOST_CCREG,CLOCK_DIVIDER,HOST_CCREG);
4519 else if(ccadj[t]) emit_addimm(HOST_CCREG,-ccadj[t]*CLOCK_DIVIDER,HOST_CCREG);
4520 if(regs[t].regmap_entry[HOST_CCREG]!=CCREG) {
4521 emit_storereg(CCREG,HOST_CCREG);
4522 }
4523 // Load 32-bit regs
4524 for(hr=0;hr<HOST_REGS;hr++) {
ea3d2e6e 4525 if(regs[t].regmap_entry[hr]>=0&&regs[t].regmap_entry[hr]<TEMPREG) {
57871462 4526 if(regs[t].regmap_entry[hr]==0) {
4527 emit_zeroreg(hr);
4528 }
4529 else if(regs[t].regmap_entry[hr]!=CCREG)
4530 {
4531 emit_loadreg(regs[t].regmap_entry[hr],hr);
4532 }
4533 }
4534 }
4535 // Load 64-bit regs
4536 for(hr=0;hr<HOST_REGS;hr++) {
ea3d2e6e 4537 if(regs[t].regmap_entry[hr]>=64&&regs[t].regmap_entry[hr]<TEMPREG+64) {
57871462 4538 assert(regs[t].regmap_entry[hr]!=64);
4539 if((regs[t].was32>>(regs[t].regmap_entry[hr]&63))&1) {
4540 int lr=get_reg(regs[t].regmap_entry,regs[t].regmap_entry[hr]-64);
4541 if(lr<0) {
4542 emit_loadreg(regs[t].regmap_entry[hr],hr);
4543 }
4544 else
4545 {
4546 emit_sarimm(lr,31,hr);
4547 }
4548 }
4549 else
4550 {
4551 emit_loadreg(regs[t].regmap_entry[hr],hr);
4552 }
4553 }
4554 }
4555}
4556
4557// Store dirty registers prior to branch
4558void store_regs_bt(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr)
4559{
4560 if(internal_branch(i_is32,addr))
4561 {
4562 int t=(addr-start)>>2;
4563 int hr;
4564 for(hr=0;hr<HOST_REGS;hr++) {
4565 if(hr!=EXCLUDE_REG) {
4566 if(i_regmap[hr]>0 && i_regmap[hr]!=CCREG) {
4567 if(i_regmap[hr]!=regs[t].regmap_entry[hr] || !((regs[t].dirty>>hr)&1) || (((i_is32&~regs[t].was32&~unneeded_reg_upper[t])>>(i_regmap[hr]&63))&1)) {
4568 if((i_dirty>>hr)&1) {
4569 if(i_regmap[hr]<64) {
4570 if(!((unneeded_reg[t]>>i_regmap[hr])&1)) {
4571 emit_storereg(i_regmap[hr],hr);
4572 if( ((i_is32>>i_regmap[hr])&1) && !((unneeded_reg_upper[t]>>i_regmap[hr])&1) ) {
4573 #ifdef DESTRUCTIVE_WRITEBACK
4574 emit_sarimm(hr,31,hr);
4575 emit_storereg(i_regmap[hr]|64,hr);
4576 #else
4577 emit_sarimm(hr,31,HOST_TEMPREG);
4578 emit_storereg(i_regmap[hr]|64,HOST_TEMPREG);
4579 #endif
4580 }
4581 }
4582 }else{
4583 if( !((i_is32>>(i_regmap[hr]&63))&1) && !((unneeded_reg_upper[t]>>(i_regmap[hr]&63))&1) ) {
4584 emit_storereg(i_regmap[hr],hr);
4585 }
4586 }
4587 }
4588 }
4589 }
4590 }
4591 }
4592 }
4593 else
4594 {
4595 // Branch out of this block, write out all dirty regs
4596 wb_dirtys(i_regmap,i_is32,i_dirty);
4597 }
4598}
4599
4600// Load all needed registers for branch target
4601void load_regs_bt(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr)
4602{
4603 //if(addr>=start && addr<(start+slen*4))
4604 if(internal_branch(i_is32,addr))
4605 {
4606 int t=(addr-start)>>2;
4607 int hr;
4608 // Store the cycle count before loading something else
4609 if(i_regmap[HOST_CCREG]!=CCREG) {
4610 assert(i_regmap[HOST_CCREG]==-1);
4611 }
4612 if(regs[t].regmap_entry[HOST_CCREG]!=CCREG) {
4613 emit_storereg(CCREG,HOST_CCREG);
4614 }
4615 // Load 32-bit regs
4616 for(hr=0;hr<HOST_REGS;hr++) {
ea3d2e6e 4617 if(hr!=EXCLUDE_REG&&regs[t].regmap_entry[hr]>=0&&regs[t].regmap_entry[hr]<TEMPREG) {
57871462 4618 #ifdef DESTRUCTIVE_WRITEBACK
4619 if(i_regmap[hr]!=regs[t].regmap_entry[hr] || ( !((regs[t].dirty>>hr)&1) && ((i_dirty>>hr)&1) && (((i_is32&~unneeded_reg_upper[t])>>i_regmap[hr])&1) ) || (((i_is32&~regs[t].was32&~unneeded_reg_upper[t])>>(i_regmap[hr]&63))&1)) {
4620 #else
4621 if(i_regmap[hr]!=regs[t].regmap_entry[hr] ) {
4622 #endif
4623 if(regs[t].regmap_entry[hr]==0) {
4624 emit_zeroreg(hr);
4625 }
4626 else if(regs[t].regmap_entry[hr]!=CCREG)
4627 {
4628 emit_loadreg(regs[t].regmap_entry[hr],hr);
4629 }
4630 }
4631 }
4632 }
4633 //Load 64-bit regs
4634 for(hr=0;hr<HOST_REGS;hr++) {
ea3d2e6e 4635 if(hr!=EXCLUDE_REG&&regs[t].regmap_entry[hr]>=64&&regs[t].regmap_entry[hr]<TEMPREG+64) {
57871462 4636 if(i_regmap[hr]!=regs[t].regmap_entry[hr]) {
4637 assert(regs[t].regmap_entry[hr]!=64);
4638 if((i_is32>>(regs[t].regmap_entry[hr]&63))&1) {
4639 int lr=get_reg(regs[t].regmap_entry,regs[t].regmap_entry[hr]-64);
4640 if(lr<0) {
4641 emit_loadreg(regs[t].regmap_entry[hr],hr);
4642 }
4643 else
4644 {
4645 emit_sarimm(lr,31,hr);
4646 }
4647 }
4648 else
4649 {
4650 emit_loadreg(regs[t].regmap_entry[hr],hr);
4651 }
4652 }
4653 else if((i_is32>>(regs[t].regmap_entry[hr]&63))&1) {
4654 int lr=get_reg(regs[t].regmap_entry,regs[t].regmap_entry[hr]-64);
4655 assert(lr>=0);
4656 emit_sarimm(lr,31,hr);
4657 }
4658 }
4659 }
4660 }
4661}
4662
4663int match_bt(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr)
4664{
4665 if(addr>=start && addr<start+slen*4-4)
4666 {
4667 int t=(addr-start)>>2;
4668 int hr;
4669 if(regs[t].regmap_entry[HOST_CCREG]!=CCREG) return 0;
4670 for(hr=0;hr<HOST_REGS;hr++)
4671 {
4672 if(hr!=EXCLUDE_REG)
4673 {
4674 if(i_regmap[hr]!=regs[t].regmap_entry[hr])
4675 {
ea3d2e6e 4676 if(regs[t].regmap_entry[hr]>=0&&(regs[t].regmap_entry[hr]|64)<TEMPREG+64)
57871462 4677 {
4678 return 0;
4679 }
4680 else
4681 if((i_dirty>>hr)&1)
4682 {
ea3d2e6e 4683 if(i_regmap[hr]<TEMPREG)
57871462 4684 {
4685 if(!((unneeded_reg[t]>>i_regmap[hr])&1))
4686 return 0;
4687 }
ea3d2e6e 4688 else if(i_regmap[hr]>=64&&i_regmap[hr]<TEMPREG+64)
57871462 4689 {
4690 if(!((unneeded_reg_upper[t]>>(i_regmap[hr]&63))&1))
4691 return 0;
4692 }
4693 }
4694 }
4695 else // Same register but is it 32-bit or dirty?
4696 if(i_regmap[hr]>=0)
4697 {
4698 if(!((regs[t].dirty>>hr)&1))
4699 {
4700 if((i_dirty>>hr)&1)
4701 {
4702 if(!((unneeded_reg[t]>>i_regmap[hr])&1))
4703 {
4704 //printf("%x: dirty no match\n",addr);
4705 return 0;
4706 }
4707 }
4708 }
4709 if((((regs[t].was32^i_is32)&~unneeded_reg_upper[t])>>(i_regmap[hr]&63))&1)
4710 {
4711 //printf("%x: is32 no match\n",addr);
4712 return 0;
4713 }
4714 }
4715 }
4716 }
4717 //if(is32[t]&~unneeded_reg_upper[t]&~i_is32) return 0;
a28c6ce8 4718#ifndef FORCE32
57871462 4719 if(requires_32bit[t]&~i_is32) return 0;
a28c6ce8 4720#endif
57871462 4721 // Delay slots are not valid branch targets
4722 //if(t>0&&(itype[t-1]==RJUMP||itype[t-1]==UJUMP||itype[t-1]==CJUMP||itype[t-1]==SJUMP||itype[t-1]==FJUMP)) return 0;
4723 // Delay slots require additional processing, so do not match
4724 if(is_ds[t]) return 0;
4725 }
4726 else
4727 {
4728 int hr;
4729 for(hr=0;hr<HOST_REGS;hr++)
4730 {
4731 if(hr!=EXCLUDE_REG)
4732 {
4733 if(i_regmap[hr]>=0)
4734 {
4735 if(hr!=HOST_CCREG||i_regmap[hr]!=CCREG)
4736 {
4737 if((i_dirty>>hr)&1)
4738 {
4739 return 0;
4740 }
4741 }
4742 }
4743 }
4744 }
4745 }
4746 return 1;
4747}
4748
4749// Used when a branch jumps into the delay slot of another branch
4750void ds_assemble_entry(int i)
4751{
4752 int t=(ba[i]-start)>>2;
4753 if(!instr_addr[t]) instr_addr[t]=(u_int)out;
4754 assem_debug("Assemble delay slot at %x\n",ba[i]);
4755 assem_debug("<->\n");
4756 if(regs[t].regmap_entry[HOST_CCREG]==CCREG&&regs[t].regmap[HOST_CCREG]!=CCREG)
4757 wb_register(CCREG,regs[t].regmap_entry,regs[t].wasdirty,regs[t].was32);
4758 load_regs(regs[t].regmap_entry,regs[t].regmap,regs[t].was32,rs1[t],rs2[t]);
4759 address_generation(t,&regs[t],regs[t].regmap_entry);
b9b61529 4760 if(itype[t]==STORE||itype[t]==STORELR||(opcode[t]&0x3b)==0x39||(opcode[t]&0x3b)==0x3a)
57871462 4761 load_regs(regs[t].regmap_entry,regs[t].regmap,regs[t].was32,INVCP,INVCP);
4762 cop1_usable=0;
4763 is_delayslot=0;
4764 switch(itype[t]) {
4765 case ALU:
4766 alu_assemble(t,&regs[t]);break;
4767 case IMM16:
4768 imm16_assemble(t,&regs[t]);break;
4769 case SHIFT:
4770 shift_assemble(t,&regs[t]);break;
4771 case SHIFTIMM:
4772 shiftimm_assemble(t,&regs[t]);break;
4773 case LOAD:
4774 load_assemble(t,&regs[t]);break;
4775 case LOADLR:
4776 loadlr_assemble(t,&regs[t]);break;
4777 case STORE:
4778 store_assemble(t,&regs[t]);break;
4779 case STORELR:
4780 storelr_assemble(t,&regs[t]);break;
4781 case COP0:
4782 cop0_assemble(t,&regs[t]);break;
4783 case COP1:
4784 cop1_assemble(t,&regs[t]);break;
4785 case C1LS:
4786 c1ls_assemble(t,&regs[t]);break;
b9b61529 4787 case COP2:
4788 cop2_assemble(t,&regs[t]);break;
4789 case C2LS:
4790 c2ls_assemble(t,&regs[t]);break;
4791 case C2OP:
4792 c2op_assemble(t,&regs[t]);break;
57871462 4793 case FCONV:
4794 fconv_assemble(t,&regs[t]);break;
4795 case FLOAT:
4796 float_assemble(t,&regs[t]);break;
4797 case FCOMP:
4798 fcomp_assemble(t,&regs[t]);break;
4799 case MULTDIV:
4800 multdiv_assemble(t,&regs[t]);break;
4801 case MOV:
4802 mov_assemble(t,&regs[t]);break;
4803 case SYSCALL:
7139f3c8 4804 case HLECALL:
1e973cb0 4805 case INTCALL:
57871462 4806 case SPAN:
4807 case UJUMP:
4808 case RJUMP:
4809 case CJUMP:
4810 case SJUMP:
4811 case FJUMP:
4812 printf("Jump in the delay slot. This is probably a bug.\n");
4813 }
4814 store_regs_bt(regs[t].regmap,regs[t].is32,regs[t].dirty,ba[i]+4);
4815 load_regs_bt(regs[t].regmap,regs[t].is32,regs[t].dirty,ba[i]+4);
4816 if(internal_branch(regs[t].is32,ba[i]+4))
4817 assem_debug("branch: internal\n");
4818 else
4819 assem_debug("branch: external\n");
4820 assert(internal_branch(regs[t].is32,ba[i]+4));
4821 add_to_linker((int)out,ba[i]+4,internal_branch(regs[t].is32,ba[i]+4));
4822 emit_jmp(0);
4823}
4824
4825void do_cc(int i,signed char i_regmap[],int *adj,int addr,int taken,int invert)
4826{
4827 int count;
4828 int jaddr;
4829 int idle=0;
4830 if(itype[i]==RJUMP)
4831 {
4832 *adj=0;
4833 }
4834 //if(ba[i]>=start && ba[i]<(start+slen*4))
4835 if(internal_branch(branch_regs[i].is32,ba[i]))
4836 {
4837 int t=(ba[i]-start)>>2;
4838 if(is_ds[t]) *adj=-1; // Branch into delay slot adds an extra cycle
4839 else *adj=ccadj[t];
4840 }
4841 else
4842 {
4843 *adj=0;
4844 }
4845 count=ccadj[i];
4846 if(taken==TAKEN && i==(ba[i]-start)>>2 && source[i+1]==0) {
4847 // Idle loop
4848 if(count&1) emit_addimm_and_set_flags(2*(count+2),HOST_CCREG);
4849 idle=(int)out;
4850 //emit_subfrommem(&idlecount,HOST_CCREG); // Count idle cycles
4851 emit_andimm(HOST_CCREG,3,HOST_CCREG);
4852 jaddr=(int)out;
4853 emit_jmp(0);
4854 }
4855 else if(*adj==0||invert) {
4856 emit_addimm_and_set_flags(CLOCK_DIVIDER*(count+2),HOST_CCREG);
4857 jaddr=(int)out;
4858 emit_jns(0);
4859 }
4860 else
4861 {
eeb1feeb 4862 emit_cmpimm(HOST_CCREG,-CLOCK_DIVIDER*(count+2));
57871462 4863 jaddr=(int)out;
4864 emit_jns(0);
4865 }
4866 add_stub(CC_STUB,jaddr,idle?idle:(int)out,(*adj==0||invert||idle)?0:(count+2),i,addr,taken,0);
4867}
4868
4869void do_ccstub(int n)
4870{
4871 literal_pool(256);
4872 assem_debug("do_ccstub %x\n",start+stubs[n][4]*4);
4873 set_jump_target(stubs[n][1],(int)out);
4874 int i=stubs[n][4];
4875 if(stubs[n][6]==NULLDS) {
4876 // Delay slot instruction is nullified ("likely" branch)
4877 wb_dirtys(regs[i].regmap,regs[i].is32,regs[i].dirty);
4878 }
4879 else if(stubs[n][6]!=TAKEN) {
4880 wb_dirtys(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty);
4881 }
4882 else {
4883 if(internal_branch(branch_regs[i].is32,ba[i]))
4884 wb_needed_dirtys(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
4885 }
4886 if(stubs[n][5]!=-1)
4887 {
4888 // Save PC as return address
4889 emit_movimm(stubs[n][5],EAX);
4890 emit_writeword(EAX,(int)&pcaddr);
4891 }
4892 else
4893 {
4894 // Return address depends on which way the branch goes
4895 if(itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
4896 {
4897 int s1l=get_reg(branch_regs[i].regmap,rs1[i]);
4898 int s1h=get_reg(branch_regs[i].regmap,rs1[i]|64);
4899 int s2l=get_reg(branch_regs[i].regmap,rs2[i]);
4900 int s2h=get_reg(branch_regs[i].regmap,rs2[i]|64);
4901 if(rs1[i]==0)
4902 {
4903 s1l=s2l;s1h=s2h;
4904 s2l=s2h=-1;
4905 }
4906 else if(rs2[i]==0)
4907 {
4908 s2l=s2h=-1;
4909 }
4910 if((branch_regs[i].is32>>rs1[i])&(branch_regs[i].is32>>rs2[i])&1) {
4911 s1h=s2h=-1;
4912 }
4913 assert(s1l>=0);
4914 #ifdef DESTRUCTIVE_WRITEBACK
4915 if(rs1[i]) {
4916 if((branch_regs[i].dirty>>s1l)&(branch_regs[i].is32>>rs1[i])&1)
4917 emit_loadreg(rs1[i],s1l);
4918 }
4919 else {
4920 if((branch_regs[i].dirty>>s1l)&(branch_regs[i].is32>>rs2[i])&1)
4921 emit_loadreg(rs2[i],s1l);
4922 }
4923 if(s2l>=0)
4924 if((branch_regs[i].dirty>>s2l)&(branch_regs[i].is32>>rs2[i])&1)
4925 emit_loadreg(rs2[i],s2l);
4926 #endif
4927 int hr=0;
5194fb95 4928 int addr=-1,alt=-1,ntaddr=-1;
57871462 4929 while(hr<HOST_REGS)
4930 {
4931 if(hr!=EXCLUDE_REG && hr!=HOST_CCREG &&
4932 (branch_regs[i].regmap[hr]&63)!=rs1[i] &&
4933 (branch_regs[i].regmap[hr]&63)!=rs2[i] )
4934 {
4935 addr=hr++;break;
4936 }
4937 hr++;
4938 }
4939 while(hr<HOST_REGS)
4940 {
4941 if(hr!=EXCLUDE_REG && hr!=HOST_CCREG &&
4942 (branch_regs[i].regmap[hr]&63)!=rs1[i] &&
4943 (branch_regs[i].regmap[hr]&63)!=rs2[i] )
4944 {
4945 alt=hr++;break;
4946 }
4947 hr++;
4948 }
4949 if((opcode[i]&0x2E)==6) // BLEZ/BGTZ needs another register
4950 {
4951 while(hr<HOST_REGS)
4952 {
4953 if(hr!=EXCLUDE_REG && hr!=HOST_CCREG &&
4954 (branch_regs[i].regmap[hr]&63)!=rs1[i] &&
4955 (branch_regs[i].regmap[hr]&63)!=rs2[i] )
4956 {
4957 ntaddr=hr;break;
4958 }
4959 hr++;
4960 }
4961 assert(hr<HOST_REGS);
4962 }
4963 if((opcode[i]&0x2f)==4) // BEQ
4964 {
4965 #ifdef HAVE_CMOV_IMM
4966 if(s1h<0) {
4967 if(s2l>=0) emit_cmp(s1l,s2l);
4968 else emit_test(s1l,s1l);
4969 emit_cmov2imm_e_ne_compact(ba[i],start+i*4+8,addr);
4970 }
4971 else
4972 #endif
4973 {
4974 emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
4975 if(s1h>=0) {
4976 if(s2h>=0) emit_cmp(s1h,s2h);
4977 else emit_test(s1h,s1h);
4978 emit_cmovne_reg(alt,addr);
4979 }
4980 if(s2l>=0) emit_cmp(s1l,s2l);
4981 else emit_test(s1l,s1l);
4982 emit_cmovne_reg(alt,addr);
4983 }
4984 }
4985 if((opcode[i]&0x2f)==5) // BNE
4986 {
4987 #ifdef HAVE_CMOV_IMM
4988 if(s1h<0) {
4989 if(s2l>=0) emit_cmp(s1l,s2l);
4990 else emit_test(s1l,s1l);
4991 emit_cmov2imm_e_ne_compact(start+i*4+8,ba[i],addr);
4992 }
4993 else
4994 #endif
4995 {
4996 emit_mov2imm_compact(start+i*4+8,addr,ba[i],alt);
4997 if(s1h>=0) {
4998 if(s2h>=0) emit_cmp(s1h,s2h);
4999 else emit_test(s1h,s1h);
5000 emit_cmovne_reg(alt,addr);
5001 }
5002 if(s2l>=0) emit_cmp(s1l,s2l);
5003 else emit_test(s1l,s1l);
5004 emit_cmovne_reg(alt,addr);
5005 }
5006 }
5007 if((opcode[i]&0x2f)==6) // BLEZ
5008 {
5009 //emit_movimm(ba[i],alt);
5010 //emit_movimm(start+i*4+8,addr);
5011 emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
5012 emit_cmpimm(s1l,1);
5013 if(s1h>=0) emit_mov(addr,ntaddr);
5014 emit_cmovl_reg(alt,addr);
5015 if(s1h>=0) {
5016 emit_test(s1h,s1h);
5017 emit_cmovne_reg(ntaddr,addr);
5018 emit_cmovs_reg(alt,addr);
5019 }
5020 }
5021 if((opcode[i]&0x2f)==7) // BGTZ
5022 {
5023 //emit_movimm(ba[i],addr);
5024 //emit_movimm(start+i*4+8,ntaddr);
5025 emit_mov2imm_compact(ba[i],addr,start+i*4+8,ntaddr);
5026 emit_cmpimm(s1l,1);
5027 if(s1h>=0) emit_mov(addr,alt);
5028 emit_cmovl_reg(ntaddr,addr);
5029 if(s1h>=0) {
5030 emit_test(s1h,s1h);
5031 emit_cmovne_reg(alt,addr);
5032 emit_cmovs_reg(ntaddr,addr);
5033 }
5034 }
5035 if((opcode[i]==1)&&(opcode2[i]&0x2D)==0) // BLTZ
5036 {
5037 //emit_movimm(ba[i],alt);
5038 //emit_movimm(start+i*4+8,addr);
5039 emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
5040 if(s1h>=0) emit_test(s1h,s1h);
5041 else emit_test(s1l,s1l);
5042 emit_cmovs_reg(alt,addr);
5043 }
5044 if((opcode[i]==1)&&(opcode2[i]&0x2D)==1) // BGEZ
5045 {
5046 //emit_movimm(ba[i],addr);
5047 //emit_movimm(start+i*4+8,alt);
5048 emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
5049 if(s1h>=0) emit_test(s1h,s1h);
5050 else emit_test(s1l,s1l);
5051 emit_cmovs_reg(alt,addr);
5052 }
5053 if(opcode[i]==0x11 && opcode2[i]==0x08 ) {
5054 if(source[i]&0x10000) // BC1T
5055 {
5056 //emit_movimm(ba[i],alt);
5057 //emit_movimm(start+i*4+8,addr);
5058 emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
5059 emit_testimm(s1l,0x800000);
5060 emit_cmovne_reg(alt,addr);
5061 }
5062 else // BC1F
5063 {
5064 //emit_movimm(ba[i],addr);
5065 //emit_movimm(start+i*4+8,alt);
5066 emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
5067 emit_testimm(s1l,0x800000);
5068 emit_cmovne_reg(alt,addr);
5069 }
5070 }
5071 emit_writeword(addr,(int)&pcaddr);
5072 }
5073 else
5074 if(itype[i]==RJUMP)
5075 {
5076 int r=get_reg(branch_regs[i].regmap,rs1[i]);
5077 if(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1]) {
5078 r=get_reg(branch_regs[i].regmap,RTEMP);
5079 }
5080 emit_writeword(r,(int)&pcaddr);
5081 }
5082 else {printf("Unknown branch type in do_ccstub\n");exit(1);}
5083 }
5084 // Update cycle count
5085 assert(branch_regs[i].regmap[HOST_CCREG]==CCREG||branch_regs[i].regmap[HOST_CCREG]==-1);
5086 if(stubs[n][3]) emit_addimm(HOST_CCREG,CLOCK_DIVIDER*stubs[n][3],HOST_CCREG);
5087 emit_call((int)cc_interrupt);
5088 if(stubs[n][3]) emit_addimm(HOST_CCREG,-CLOCK_DIVIDER*stubs[n][3],HOST_CCREG);
5089 if(stubs[n][6]==TAKEN) {
5090 if(internal_branch(branch_regs[i].is32,ba[i]))
5091 load_needed_regs(branch_regs[i].regmap,regs[(ba[i]-start)>>2].regmap_entry);
5092 else if(itype[i]==RJUMP) {
5093 if(get_reg(branch_regs[i].regmap,RTEMP)>=0)
5094 emit_readword((int)&pcaddr,get_reg(branch_regs[i].regmap,RTEMP));
5095 else
5096 emit_loadreg(rs1[i],get_reg(branch_regs[i].regmap,rs1[i]));
5097 }
5098 }else if(stubs[n][6]==NOTTAKEN) {
5099 if(i<slen-2) load_needed_regs(branch_regs[i].regmap,regmap_pre[i+2]);
5100 else load_all_regs(branch_regs[i].regmap);
5101 }else if(stubs[n][6]==NULLDS) {
5102 // Delay slot instruction is nullified ("likely" branch)
5103 if(i<slen-2) load_needed_regs(regs[i].regmap,regmap_pre[i+2]);
5104 else load_all_regs(regs[i].regmap);
5105 }else{
5106 load_all_regs(branch_regs[i].regmap);
5107 }
5108 emit_jmp(stubs[n][2]); // return address
5109
5110 /* This works but uses a lot of memory...
5111 emit_readword((int)&last_count,ECX);
5112 emit_add(HOST_CCREG,ECX,EAX);
5113 emit_writeword(EAX,(int)&Count);
5114 emit_call((int)gen_interupt);
5115 emit_readword((int)&Count,HOST_CCREG);
5116 emit_readword((int)&next_interupt,EAX);
5117 emit_readword((int)&pending_exception,EBX);
5118 emit_writeword(EAX,(int)&last_count);
5119 emit_sub(HOST_CCREG,EAX,HOST_CCREG);
5120 emit_test(EBX,EBX);
5121 int jne_instr=(int)out;
5122 emit_jne(0);
5123 if(stubs[n][3]) emit_addimm(HOST_CCREG,-2*stubs[n][3],HOST_CCREG);
5124 load_all_regs(branch_regs[i].regmap);
5125 emit_jmp(stubs[n][2]); // return address
5126 set_jump_target(jne_instr,(int)out);
5127 emit_readword((int)&pcaddr,EAX);
5128 // Call get_addr_ht instead of doing the hash table here.
5129 // This code is executed infrequently and takes up a lot of space
5130 // so smaller is better.
5131 emit_storereg(CCREG,HOST_CCREG);
5132 emit_pushreg(EAX);
5133 emit_call((int)get_addr_ht);
5134 emit_loadreg(CCREG,HOST_CCREG);
5135 emit_addimm(ESP,4,ESP);
5136 emit_jmpreg(EAX);*/
5137}
5138
5139add_to_linker(int addr,int target,int ext)
5140{
5141 link_addr[linkcount][0]=addr;
5142 link_addr[linkcount][1]=target;
5143 link_addr[linkcount][2]=ext;
5144 linkcount++;
5145}
5146
5147void ujump_assemble(int i,struct regstat *i_regs)
5148{
5149 signed char *i_regmap=i_regs->regmap;
5150 if(i==(ba[i]-start)>>2) assem_debug("idle loop\n");
5151 address_generation(i+1,i_regs,regs[i].regmap_entry);
5152 #ifdef REG_PREFETCH
5153 int temp=get_reg(branch_regs[i].regmap,PTEMP);
5154 if(rt1[i]==31&&temp>=0)
5155 {
5156 int return_address=start+i*4+8;
5157 if(get_reg(branch_regs[i].regmap,31)>0)
5158 if(i_regmap[temp]==PTEMP) emit_movimm((int)hash_table[((return_address>>16)^return_address)&0xFFFF],temp);
5159 }
5160 #endif
57871462 5161 if(rt1[i]==31) {
5162 int rt;
5163 unsigned int return_address;
57871462 5164 rt=get_reg(branch_regs[i].regmap,31);
5165 assem_debug("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5166 //assert(rt>=0);
5167 return_address=start+i*4+8;
5168 if(rt>=0) {
5169 #ifdef USE_MINI_HT
4ef8f67d 5170 if(internal_branch(branch_regs[i].is32,return_address)&&rt1[i+1]!=31) {
5171 int temp=-1; // note: must be ds-safe
57871462 5172 #ifdef HOST_TEMPREG
4ef8f67d 5173 temp=HOST_TEMPREG;
57871462 5174 #endif
5175 if(temp>=0) do_miniht_insert(return_address,rt,temp);
5176 else emit_movimm(return_address,rt);
5177 }
5178 else
5179 #endif
5180 {
5181 #ifdef REG_PREFETCH
5182 if(temp>=0)
5183 {
5184 if(i_regmap[temp]!=PTEMP) emit_movimm((int)hash_table[((return_address>>16)^return_address)&0xFFFF],temp);
5185 }
5186 #endif
5187 emit_movimm(return_address,rt); // PC into link register
5188 #ifdef IMM_PREFETCH
5189 emit_prefetch(hash_table[((return_address>>16)^return_address)&0xFFFF]);
5190 #endif
5191 }
5192 }
5193 }
4ef8f67d 5194 ds_assemble(i+1,i_regs);
5195 uint64_t bc_unneeded=branch_regs[i].u;
5196 uint64_t bc_unneeded_upper=branch_regs[i].uu;
5197 bc_unneeded|=1|(1LL<<rt1[i]);
5198 bc_unneeded_upper|=1|(1LL<<rt1[i]);
5199 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5200 bc_unneeded,bc_unneeded_upper);
5201 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
57871462 5202 int cc,adj;
5203 cc=get_reg(branch_regs[i].regmap,CCREG);
5204 assert(cc==HOST_CCREG);
5205 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5206 #ifdef REG_PREFETCH
5207 if(rt1[i]==31&&temp>=0) emit_prefetchreg(temp);
5208 #endif
5209 do_cc(i,branch_regs[i].regmap,&adj,ba[i],TAKEN,0);
5210 if(adj) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc);
5211 load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5212 if(internal_branch(branch_regs[i].is32,ba[i]))
5213 assem_debug("branch: internal\n");
5214 else
5215 assem_debug("branch: external\n");
5216 if(internal_branch(branch_regs[i].is32,ba[i])&&is_ds[(ba[i]-start)>>2]) {
5217 ds_assemble_entry(i);
5218 }
5219 else {
5220 add_to_linker((int)out,ba[i],internal_branch(branch_regs[i].is32,ba[i]));
5221 emit_jmp(0);
5222 }
5223}
5224
5225void rjump_assemble(int i,struct regstat *i_regs)
5226{
5227 signed char *i_regmap=i_regs->regmap;
5228 int temp;
5229 int rs,cc,adj;
5230 rs=get_reg(branch_regs[i].regmap,rs1[i]);
5231 assert(rs>=0);
5232 if(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1]) {
5233 // Delay slot abuse, make a copy of the branch address register
5234 temp=get_reg(branch_regs[i].regmap,RTEMP);
5235 assert(temp>=0);
5236 assert(regs[i].regmap[temp]==RTEMP);
5237 emit_mov(rs,temp);
5238 rs=temp;
5239 }
5240 address_generation(i+1,i_regs,regs[i].regmap_entry);
5241 #ifdef REG_PREFETCH
5242 if(rt1[i]==31)
5243 {
5244 if((temp=get_reg(branch_regs[i].regmap,PTEMP))>=0) {
5245 int return_address=start+i*4+8;
5246 if(i_regmap[temp]==PTEMP) emit_movimm((int)hash_table[((return_address>>16)^return_address)&0xFFFF],temp);
5247 }
5248 }
5249 #endif
5250 #ifdef USE_MINI_HT
5251 if(rs1[i]==31) {
5252 int rh=get_reg(regs[i].regmap,RHASH);
5253 if(rh>=0) do_preload_rhash(rh);
5254 }
5255 #endif
5256 ds_assemble(i+1,i_regs);
5257 uint64_t bc_unneeded=branch_regs[i].u;
5258 uint64_t bc_unneeded_upper=branch_regs[i].uu;
5259 bc_unneeded|=1|(1LL<<rt1[i]);
5260 bc_unneeded_upper|=1|(1LL<<rt1[i]);
5261 bc_unneeded&=~(1LL<<rs1[i]);
5262 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5263 bc_unneeded,bc_unneeded_upper);
5264 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i],CCREG);
5067f341 5265 if(rt1[i]!=0) {
57871462 5266 int rt,return_address;
5067f341 5267 assert(rt1[i+1]!=rt1[i]);
5268 assert(rt2[i+1]!=rt1[i]);
5269 rt=get_reg(branch_regs[i].regmap,rt1[i]);
57871462 5270 assem_debug("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5271 assert(rt>=0);
5272 return_address=start+i*4+8;
5273 #ifdef REG_PREFETCH
5274 if(temp>=0)
5275 {
5276 if(i_regmap[temp]!=PTEMP) emit_movimm((int)hash_table[((return_address>>16)^return_address)&0xFFFF],temp);
5277 }
5278 #endif
5279 emit_movimm(return_address,rt); // PC into link register
5280 #ifdef IMM_PREFETCH
5281 emit_prefetch(hash_table[((return_address>>16)^return_address)&0xFFFF]);
5282 #endif
5283 }
5284 cc=get_reg(branch_regs[i].regmap,CCREG);
5285 assert(cc==HOST_CCREG);
5286 #ifdef USE_MINI_HT
5287 int rh=get_reg(branch_regs[i].regmap,RHASH);
5288 int ht=get_reg(branch_regs[i].regmap,RHTBL);
5289 if(rs1[i]==31) {
5290 if(regs[i].regmap[rh]!=RHASH) do_preload_rhash(rh);
5291 do_preload_rhtbl(ht);
5292 do_rhash(rs,rh);
5293 }
5294 #endif
5295 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,-1);
5296 #ifdef DESTRUCTIVE_WRITEBACK
5297 if((branch_regs[i].dirty>>rs)&(branch_regs[i].is32>>rs1[i])&1) {
5298 if(rs1[i]!=rt1[i+1]&&rs1[i]!=rt2[i+1]) {
5299 emit_loadreg(rs1[i],rs);
5300 }
5301 }
5302 #endif
5303 #ifdef REG_PREFETCH
5304 if(rt1[i]==31&&temp>=0) emit_prefetchreg(temp);
5305 #endif
5306 #ifdef USE_MINI_HT
5307 if(rs1[i]==31) {
5308 do_miniht_load(ht,rh);
5309 }
5310 #endif
5311 //do_cc(i,branch_regs[i].regmap,&adj,-1,TAKEN);
5312 //if(adj) emit_addimm(cc,2*(ccadj[i]+2-adj),cc); // ??? - Shouldn't happen
5313 //assert(adj==0);
5314 emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),HOST_CCREG);
5315 add_stub(CC_STUB,(int)out,jump_vaddr_reg[rs],0,i,-1,TAKEN,0);
5316 emit_jns(0);
5317 //load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,-1);
5318 #ifdef USE_MINI_HT
5319 if(rs1[i]==31) {
5320 do_miniht_jump(rs,rh,ht);
5321 }
5322 else
5323 #endif
5324 {
5325 //if(rs!=EAX) emit_mov(rs,EAX);
5326 //emit_jmp((int)jump_vaddr_eax);
5327 emit_jmp(jump_vaddr_reg[rs]);
5328 }
5329 /* Check hash table
5330 temp=!rs;
5331 emit_mov(rs,temp);
5332 emit_shrimm(rs,16,rs);
5333 emit_xor(temp,rs,rs);
5334 emit_movzwl_reg(rs,rs);
5335 emit_shlimm(rs,4,rs);
5336 emit_cmpmem_indexed((int)hash_table,rs,temp);
5337 emit_jne((int)out+14);
5338 emit_readword_indexed((int)hash_table+4,rs,rs);
5339 emit_jmpreg(rs);
5340 emit_cmpmem_indexed((int)hash_table+8,rs,temp);
5341 emit_addimm_no_flags(8,rs);
5342 emit_jeq((int)out-17);
5343 // No hit on hash table, call compiler
5344 emit_pushreg(temp);
5345//DEBUG >
5346#ifdef DEBUG_CYCLE_COUNT
5347 emit_readword((int)&last_count,ECX);
5348 emit_add(HOST_CCREG,ECX,HOST_CCREG);
5349 emit_readword((int)&next_interupt,ECX);
5350 emit_writeword(HOST_CCREG,(int)&Count);
5351 emit_sub(HOST_CCREG,ECX,HOST_CCREG);
5352 emit_writeword(ECX,(int)&last_count);
5353#endif
5354//DEBUG <
5355 emit_storereg(CCREG,HOST_CCREG);
5356 emit_call((int)get_addr);
5357 emit_loadreg(CCREG,HOST_CCREG);
5358 emit_addimm(ESP,4,ESP);
5359 emit_jmpreg(EAX);*/
5360 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5361 if(rt1[i]!=31&&i<slen-2&&(((u_int)out)&7)) emit_mov(13,13);
5362 #endif
5363}
5364
5365void cjump_assemble(int i,struct regstat *i_regs)
5366{
5367 signed char *i_regmap=i_regs->regmap;
5368 int cc;
5369 int match;
5370 match=match_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5371 assem_debug("match=%d\n",match);
5372 int s1h,s1l,s2h,s2l;
5373 int prev_cop1_usable=cop1_usable;
5374 int unconditional=0,nop=0;
5375 int only32=0;
57871462 5376 int invert=0;
5377 int internal=internal_branch(branch_regs[i].is32,ba[i]);
5378 if(i==(ba[i]-start)>>2) assem_debug("idle loop\n");
57871462 5379 if(!match) invert=1;
5380 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5381 if(i>(ba[i]-start)>>2) invert=1;
5382 #endif
e1190b87 5383
5384 if(ooo[i]) {
57871462 5385 s1l=get_reg(branch_regs[i].regmap,rs1[i]);
5386 s1h=get_reg(branch_regs[i].regmap,rs1[i]|64);
5387 s2l=get_reg(branch_regs[i].regmap,rs2[i]);
5388 s2h=get_reg(branch_regs[i].regmap,rs2[i]|64);
5389 }
5390 else {
5391 s1l=get_reg(i_regmap,rs1[i]);
5392 s1h=get_reg(i_regmap,rs1[i]|64);
5393 s2l=get_reg(i_regmap,rs2[i]);
5394 s2h=get_reg(i_regmap,rs2[i]|64);
5395 }
5396 if(rs1[i]==0&&rs2[i]==0)
5397 {
5398 if(opcode[i]&1) nop=1;
5399 else unconditional=1;
5400 //assert(opcode[i]!=5);
5401 //assert(opcode[i]!=7);
5402 //assert(opcode[i]!=0x15);
5403 //assert(opcode[i]!=0x17);
5404 }
5405 else if(rs1[i]==0)
5406 {
5407 s1l=s2l;s1h=s2h;
5408 s2l=s2h=-1;
5409 only32=(regs[i].was32>>rs2[i])&1;
5410 }
5411 else if(rs2[i]==0)
5412 {
5413 s2l=s2h=-1;
5414 only32=(regs[i].was32>>rs1[i])&1;
5415 }
5416 else {
5417 only32=(regs[i].was32>>rs1[i])&(regs[i].was32>>rs2[i])&1;
5418 }
5419
e1190b87 5420 if(ooo[i]) {
57871462 5421 // Out of order execution (delay slot first)
5422 //printf("OOOE\n");
5423 address_generation(i+1,i_regs,regs[i].regmap_entry);
5424 ds_assemble(i+1,i_regs);
5425 int adj;
5426 uint64_t bc_unneeded=branch_regs[i].u;
5427 uint64_t bc_unneeded_upper=branch_regs[i].uu;
5428 bc_unneeded&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
5429 bc_unneeded_upper&=~((1LL<<us1[i])|(1LL<<us2[i]));
5430 bc_unneeded|=1;
5431 bc_unneeded_upper|=1;
5432 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5433 bc_unneeded,bc_unneeded_upper);
5434 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i],rs2[i]);
5435 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
5436 cc=get_reg(branch_regs[i].regmap,CCREG);
5437 assert(cc==HOST_CCREG);
5438 if(unconditional)
5439 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5440 //do_cc(i,branch_regs[i].regmap,&adj,unconditional?ba[i]:-1,unconditional);
5441 //assem_debug("cycle count (adj)\n");
5442 if(unconditional) {
5443 do_cc(i,branch_regs[i].regmap,&adj,ba[i],TAKEN,0);
5444 if(i!=(ba[i]-start)>>2 || source[i+1]!=0) {
5445 if(adj) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc);
5446 load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5447 if(internal)
5448 assem_debug("branch: internal\n");
5449 else
5450 assem_debug("branch: external\n");
5451 if(internal&&is_ds[(ba[i]-start)>>2]) {
5452 ds_assemble_entry(i);
5453 }
5454 else {
5455 add_to_linker((int)out,ba[i],internal);
5456 emit_jmp(0);
5457 }
5458 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5459 if(((u_int)out)&7) emit_addnop(0);
5460 #endif
5461 }
5462 }
5463 else if(nop) {
5464 emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),cc);
5465 int jaddr=(int)out;
5466 emit_jns(0);
5467 add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,NOTTAKEN,0);
5468 }
5469 else {
5470 int taken=0,nottaken=0,nottaken1=0;
5471 do_cc(i,branch_regs[i].regmap,&adj,-1,0,invert);
5472 if(adj&&!invert) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc);
5473 if(!only32)
5474 {
5475 assert(s1h>=0);
5476 if(opcode[i]==4) // BEQ
5477 {
5478 if(s2h>=0) emit_cmp(s1h,s2h);
5479 else emit_test(s1h,s1h);
5480 nottaken1=(int)out;
5481 emit_jne(1);
5482 }
5483 if(opcode[i]==5) // BNE
5484 {
5485 if(s2h>=0) emit_cmp(s1h,s2h);
5486 else emit_test(s1h,s1h);
5487 if(invert) taken=(int)out;
5488 else add_to_linker((int)out,ba[i],internal);
5489 emit_jne(0);
5490 }
5491 if(opcode[i]==6) // BLEZ
5492 {
5493 emit_test(s1h,s1h);
5494 if(invert) taken=(int)out;
5495 else add_to_linker((int)out,ba[i],internal);
5496 emit_js(0);
5497 nottaken1=(int)out;
5498 emit_jne(1);
5499 }
5500 if(opcode[i]==7) // BGTZ
5501 {
5502 emit_test(s1h,s1h);
5503 nottaken1=(int)out;
5504 emit_js(1);
5505 if(invert) taken=(int)out;
5506 else add_to_linker((int)out,ba[i],internal);
5507 emit_jne(0);
5508 }
5509 } // if(!only32)
5510
5511 //printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5512 assert(s1l>=0);
5513 if(opcode[i]==4) // BEQ
5514 {
5515 if(s2l>=0) emit_cmp(s1l,s2l);
5516 else emit_test(s1l,s1l);
5517 if(invert){
5518 nottaken=(int)out;
5519 emit_jne(1);
5520 }else{
5521 add_to_linker((int)out,ba[i],internal);
5522 emit_jeq(0);
5523 }
5524 }
5525 if(opcode[i]==5) // BNE
5526 {
5527 if(s2l>=0) emit_cmp(s1l,s2l);
5528 else emit_test(s1l,s1l);
5529 if(invert){
5530 nottaken=(int)out;
5531 emit_jeq(1);
5532 }else{
5533 add_to_linker((int)out,ba[i],internal);
5534 emit_jne(0);
5535 }
5536 }
5537 if(opcode[i]==6) // BLEZ
5538 {
5539 emit_cmpimm(s1l,1);
5540 if(invert){
5541 nottaken=(int)out;
5542 emit_jge(1);
5543 }else{
5544 add_to_linker((int)out,ba[i],internal);
5545 emit_jl(0);
5546 }
5547 }
5548 if(opcode[i]==7) // BGTZ
5549 {
5550 emit_cmpimm(s1l,1);
5551 if(invert){
5552 nottaken=(int)out;
5553 emit_jl(1);
5554 }else{
5555 add_to_linker((int)out,ba[i],internal);
5556 emit_jge(0);
5557 }
5558 }
5559 if(invert) {
5560 if(taken) set_jump_target(taken,(int)out);
5561 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5562 if(match&&(!internal||!is_ds[(ba[i]-start)>>2])) {
5563 if(adj) {
5564 emit_addimm(cc,-CLOCK_DIVIDER*adj,cc);
5565 add_to_linker((int)out,ba[i],internal);
5566 }else{
5567 emit_addnop(13);
5568 add_to_linker((int)out,ba[i],internal*2);
5569 }
5570 emit_jmp(0);
5571 }else
5572 #endif
5573 {
5574 if(adj) emit_addimm(cc,-CLOCK_DIVIDER*adj,cc);
5575 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5576 load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5577 if(internal)
5578 assem_debug("branch: internal\n");
5579 else
5580 assem_debug("branch: external\n");
5581 if(internal&&is_ds[(ba[i]-start)>>2]) {
5582 ds_assemble_entry(i);
5583 }
5584 else {
5585 add_to_linker((int)out,ba[i],internal);
5586 emit_jmp(0);
5587 }
5588 }
5589 set_jump_target(nottaken,(int)out);
5590 }
5591
5592 if(nottaken1) set_jump_target(nottaken1,(int)out);
5593 if(adj) {
5594 if(!invert) emit_addimm(cc,CLOCK_DIVIDER*adj,cc);
5595 }
5596 } // (!unconditional)
5597 } // if(ooo)
5598 else
5599 {
5600 // In-order execution (branch first)
5601 //if(likely[i]) printf("IOL\n");
5602 //else
5603 //printf("IOE\n");
5604 int taken=0,nottaken=0,nottaken1=0;
5605 if(!unconditional&&!nop) {
5606 if(!only32)
5607 {
5608 assert(s1h>=0);
5609 if((opcode[i]&0x2f)==4) // BEQ
5610 {
5611 if(s2h>=0) emit_cmp(s1h,s2h);
5612 else emit_test(s1h,s1h);
5613 nottaken1=(int)out;
5614 emit_jne(2);
5615 }
5616 if((opcode[i]&0x2f)==5) // BNE
5617 {
5618 if(s2h>=0) emit_cmp(s1h,s2h);
5619 else emit_test(s1h,s1h);
5620 taken=(int)out;
5621 emit_jne(1);
5622 }
5623 if((opcode[i]&0x2f)==6) // BLEZ
5624 {
5625 emit_test(s1h,s1h);
5626 taken=(int)out;
5627 emit_js(1);
5628 nottaken1=(int)out;
5629 emit_jne(2);
5630 }
5631 if((opcode[i]&0x2f)==7) // BGTZ
5632 {
5633 emit_test(s1h,s1h);
5634 nottaken1=(int)out;
5635 emit_js(2);
5636 taken=(int)out;
5637 emit_jne(1);
5638 }
5639 } // if(!only32)
5640
5641 //printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5642 assert(s1l>=0);
5643 if((opcode[i]&0x2f)==4) // BEQ
5644 {
5645 if(s2l>=0) emit_cmp(s1l,s2l);
5646 else emit_test(s1l,s1l);
5647 nottaken=(int)out;
5648 emit_jne(2);
5649 }
5650 if((opcode[i]&0x2f)==5) // BNE
5651 {
5652 if(s2l>=0) emit_cmp(s1l,s2l);
5653 else emit_test(s1l,s1l);
5654 nottaken=(int)out;
5655 emit_jeq(2);
5656 }
5657 if((opcode[i]&0x2f)==6) // BLEZ
5658 {
5659 emit_cmpimm(s1l,1);
5660 nottaken=(int)out;
5661 emit_jge(2);
5662 }
5663 if((opcode[i]&0x2f)==7) // BGTZ
5664 {
5665 emit_cmpimm(s1l,1);
5666 nottaken=(int)out;
5667 emit_jl(2);
5668 }
5669 } // if(!unconditional)
5670 int adj;
5671 uint64_t ds_unneeded=branch_regs[i].u;
5672 uint64_t ds_unneeded_upper=branch_regs[i].uu;
5673 ds_unneeded&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
5674 ds_unneeded_upper&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
5675 if((~ds_unneeded_upper>>rt1[i+1])&1) ds_unneeded_upper&=~((1LL<<dep1[i+1])|(1LL<<dep2[i+1]));
5676 ds_unneeded|=1;
5677 ds_unneeded_upper|=1;
5678 // branch taken
5679 if(!nop) {
5680 if(taken) set_jump_target(taken,(int)out);
5681 assem_debug("1:\n");
5682 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5683 ds_unneeded,ds_unneeded_upper);
5684 // load regs
5685 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
5686 address_generation(i+1,&branch_regs[i],0);
5687 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,INVCP);
5688 ds_assemble(i+1,&branch_regs[i]);
5689 cc=get_reg(branch_regs[i].regmap,CCREG);
5690 if(cc==-1) {
5691 emit_loadreg(CCREG,cc=HOST_CCREG);
5692 // CHECK: Is the following instruction (fall thru) allocated ok?
5693 }
5694 assert(cc==HOST_CCREG);
5695 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5696 do_cc(i,i_regmap,&adj,ba[i],TAKEN,0);
5697 assem_debug("cycle count (adj)\n");
5698 if(adj) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc);
5699 load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5700 if(internal)
5701 assem_debug("branch: internal\n");
5702 else
5703 assem_debug("branch: external\n");
5704 if(internal&&is_ds[(ba[i]-start)>>2]) {
5705 ds_assemble_entry(i);
5706 }
5707 else {
5708 add_to_linker((int)out,ba[i],internal);
5709 emit_jmp(0);
5710 }
5711 }
5712 // branch not taken
5713 cop1_usable=prev_cop1_usable;
5714 if(!unconditional) {
5715 if(nottaken1) set_jump_target(nottaken1,(int)out);
5716 set_jump_target(nottaken,(int)out);
5717 assem_debug("2:\n");
5718 if(!likely[i]) {
5719 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5720 ds_unneeded,ds_unneeded_upper);
5721 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
5722 address_generation(i+1,&branch_regs[i],0);
5723 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
5724 ds_assemble(i+1,&branch_regs[i]);
5725 }
5726 cc=get_reg(branch_regs[i].regmap,CCREG);
5727 if(cc==-1&&!likely[i]) {
5728 // Cycle count isn't in a register, temporarily load it then write it out
5729 emit_loadreg(CCREG,HOST_CCREG);
5730 emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),HOST_CCREG);
5731 int jaddr=(int)out;
5732 emit_jns(0);
5733 add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,NOTTAKEN,0);
5734 emit_storereg(CCREG,HOST_CCREG);
5735 }
5736 else{
5737 cc=get_reg(i_regmap,CCREG);
5738 assert(cc==HOST_CCREG);
5739 emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),cc);
5740 int jaddr=(int)out;
5741 emit_jns(0);
5742 add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,likely[i]?NULLDS:NOTTAKEN,0);
5743 }
5744 }
5745 }
5746}
5747
5748void sjump_assemble(int i,struct regstat *i_regs)
5749{
5750 signed char *i_regmap=i_regs->regmap;
5751 int cc;
5752 int match;
5753 match=match_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5754 assem_debug("smatch=%d\n",match);
5755 int s1h,s1l;
5756 int prev_cop1_usable=cop1_usable;
5757 int unconditional=0,nevertaken=0;
5758 int only32=0;
57871462 5759 int invert=0;
5760 int internal=internal_branch(branch_regs[i].is32,ba[i]);
5761 if(i==(ba[i]-start)>>2) assem_debug("idle loop\n");
57871462 5762 if(!match) invert=1;
5763 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5764 if(i>(ba[i]-start)>>2) invert=1;
5765 #endif
5766
5767 //if(opcode2[i]>=0x10) return; // FIXME (BxxZAL)
df894a3a 5768 //assert(opcode2[i]<0x10||rs1[i]==0); // FIXME (BxxZAL)
57871462 5769
e1190b87 5770 if(ooo[i]) {
57871462 5771 s1l=get_reg(branch_regs[i].regmap,rs1[i]);
5772 s1h=get_reg(branch_regs[i].regmap,rs1[i]|64);
5773 }
5774 else {
5775 s1l=get_reg(i_regmap,rs1[i]);
5776 s1h=get_reg(i_regmap,rs1[i]|64);
5777 }
5778 if(rs1[i]==0)
5779 {
5780 if(opcode2[i]&1) unconditional=1;
5781 else nevertaken=1;
5782 // These are never taken (r0 is never less than zero)
5783 //assert(opcode2[i]!=0);
5784 //assert(opcode2[i]!=2);
5785 //assert(opcode2[i]!=0x10);
5786 //assert(opcode2[i]!=0x12);
5787 }
5788 else {
5789 only32=(regs[i].was32>>rs1[i])&1;
5790 }
5791
e1190b87 5792 if(ooo[i]) {
57871462 5793 // Out of order execution (delay slot first)
5794 //printf("OOOE\n");
5795 address_generation(i+1,i_regs,regs[i].regmap_entry);
5796 ds_assemble(i+1,i_regs);
5797 int adj;
5798 uint64_t bc_unneeded=branch_regs[i].u;
5799 uint64_t bc_unneeded_upper=branch_regs[i].uu;
5800 bc_unneeded&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
5801 bc_unneeded_upper&=~((1LL<<us1[i])|(1LL<<us2[i]));
5802 bc_unneeded|=1;
5803 bc_unneeded_upper|=1;
5804 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5805 bc_unneeded,bc_unneeded_upper);
5806 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i],rs1[i]);
5807 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
5808 if(rt1[i]==31) {
5809 int rt,return_address;
57871462 5810 rt=get_reg(branch_regs[i].regmap,31);
5811 assem_debug("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5812 if(rt>=0) {
5813 // Save the PC even if the branch is not taken
5814 return_address=start+i*4+8;
5815 emit_movimm(return_address,rt); // PC into link register
5816 #ifdef IMM_PREFETCH
5817 if(!nevertaken) emit_prefetch(hash_table[((return_address>>16)^return_address)&0xFFFF]);
5818 #endif
5819 }
5820 }
5821 cc=get_reg(branch_regs[i].regmap,CCREG);
5822 assert(cc==HOST_CCREG);
5823 if(unconditional)
5824 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5825 //do_cc(i,branch_regs[i].regmap,&adj,unconditional?ba[i]:-1,unconditional);
5826 assem_debug("cycle count (adj)\n");
5827 if(unconditional) {
5828 do_cc(i,branch_regs[i].regmap,&adj,ba[i],TAKEN,0);
5829 if(i!=(ba[i]-start)>>2 || source[i+1]!=0) {
5830 if(adj) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc);
5831 load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5832 if(internal)
5833 assem_debug("branch: internal\n");
5834 else
5835 assem_debug("branch: external\n");
5836 if(internal&&is_ds[(ba[i]-start)>>2]) {
5837 ds_assemble_entry(i);
5838 }
5839 else {
5840 add_to_linker((int)out,ba[i],internal);
5841 emit_jmp(0);
5842 }
5843 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5844 if(((u_int)out)&7) emit_addnop(0);
5845 #endif
5846 }
5847 }
5848 else if(nevertaken) {
5849 emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),cc);
5850 int jaddr=(int)out;
5851 emit_jns(0);
5852 add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,NOTTAKEN,0);
5853 }
5854 else {
5855 int nottaken=0;
5856 do_cc(i,branch_regs[i].regmap,&adj,-1,0,invert);
5857 if(adj&&!invert) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc);
5858 if(!only32)
5859 {
5860 assert(s1h>=0);
df894a3a 5861 if((opcode2[i]&0xf)==0) // BLTZ/BLTZAL
57871462 5862 {
5863 emit_test(s1h,s1h);
5864 if(invert){
5865 nottaken=(int)out;
5866 emit_jns(1);
5867 }else{
5868 add_to_linker((int)out,ba[i],internal);
5869 emit_js(0);
5870 }
5871 }
df894a3a 5872 if((opcode2[i]&0xf)==1) // BGEZ/BLTZAL
57871462 5873 {
5874 emit_test(s1h,s1h);
5875 if(invert){
5876 nottaken=(int)out;
5877 emit_js(1);
5878 }else{
5879 add_to_linker((int)out,ba[i],internal);
5880 emit_jns(0);
5881 }
5882 }
5883 } // if(!only32)
5884 else
5885 {
5886 assert(s1l>=0);
df894a3a 5887 if((opcode2[i]&0xf)==0) // BLTZ/BLTZAL
57871462 5888 {
5889 emit_test(s1l,s1l);
5890 if(invert){
5891 nottaken=(int)out;
5892 emit_jns(1);
5893 }else{
5894 add_to_linker((int)out,ba[i],internal);
5895 emit_js(0);
5896 }
5897 }
df894a3a 5898 if((opcode2[i]&0xf)==1) // BGEZ/BLTZAL
57871462 5899 {
5900 emit_test(s1l,s1l);
5901 if(invert){
5902 nottaken=(int)out;
5903 emit_js(1);
5904 }else{
5905 add_to_linker((int)out,ba[i],internal);
5906 emit_jns(0);
5907 }
5908 }
5909 } // if(!only32)
5910
5911 if(invert) {
5912 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5913 if(match&&(!internal||!is_ds[(ba[i]-start)>>2])) {
5914 if(adj) {
5915 emit_addimm(cc,-CLOCK_DIVIDER*adj,cc);
5916 add_to_linker((int)out,ba[i],internal);
5917 }else{
5918 emit_addnop(13);
5919 add_to_linker((int)out,ba[i],internal*2);
5920 }
5921 emit_jmp(0);
5922 }else
5923 #endif
5924 {
5925 if(adj) emit_addimm(cc,-CLOCK_DIVIDER*adj,cc);
5926 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5927 load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5928 if(internal)
5929 assem_debug("branch: internal\n");
5930 else
5931 assem_debug("branch: external\n");
5932 if(internal&&is_ds[(ba[i]-start)>>2]) {
5933 ds_assemble_entry(i);
5934 }
5935 else {
5936 add_to_linker((int)out,ba[i],internal);
5937 emit_jmp(0);
5938 }
5939 }
5940 set_jump_target(nottaken,(int)out);
5941 }
5942
5943 if(adj) {
5944 if(!invert) emit_addimm(cc,CLOCK_DIVIDER*adj,cc);
5945 }
5946 } // (!unconditional)
5947 } // if(ooo)
5948 else
5949 {
5950 // In-order execution (branch first)
5951 //printf("IOE\n");
5952 int nottaken=0;
a6491170 5953 if(rt1[i]==31) {
5954 int rt,return_address;
a6491170 5955 rt=get_reg(branch_regs[i].regmap,31);
5956 if(rt>=0) {
5957 // Save the PC even if the branch is not taken
5958 return_address=start+i*4+8;
5959 emit_movimm(return_address,rt); // PC into link register
5960 #ifdef IMM_PREFETCH
5961 emit_prefetch(hash_table[((return_address>>16)^return_address)&0xFFFF]);
5962 #endif
5963 }
5964 }
57871462 5965 if(!unconditional) {
5966 //printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5967 if(!only32)
5968 {
5969 assert(s1h>=0);
a6491170 5970 if((opcode2[i]&0x0d)==0) // BLTZ/BLTZL/BLTZAL/BLTZALL
57871462 5971 {
5972 emit_test(s1h,s1h);
5973 nottaken=(int)out;
5974 emit_jns(1);
5975 }
a6491170 5976 if((opcode2[i]&0x0d)==1) // BGEZ/BGEZL/BGEZAL/BGEZALL
57871462 5977 {
5978 emit_test(s1h,s1h);
5979 nottaken=(int)out;
5980 emit_js(1);
5981 }
5982 } // if(!only32)
5983 else
5984 {
5985 assert(s1l>=0);
a6491170 5986 if((opcode2[i]&0x0d)==0) // BLTZ/BLTZL/BLTZAL/BLTZALL
57871462 5987 {
5988 emit_test(s1l,s1l);
5989 nottaken=(int)out;
5990 emit_jns(1);
5991 }
a6491170 5992 if((opcode2[i]&0x0d)==1) // BGEZ/BGEZL/BGEZAL/BGEZALL
57871462 5993 {
5994 emit_test(s1l,s1l);
5995 nottaken=(int)out;
5996 emit_js(1);
5997 }
5998 }
5999 } // if(!unconditional)
6000 int adj;
6001 uint64_t ds_unneeded=branch_regs[i].u;
6002 uint64_t ds_unneeded_upper=branch_regs[i].uu;
6003 ds_unneeded&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
6004 ds_unneeded_upper&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
6005 if((~ds_unneeded_upper>>rt1[i+1])&1) ds_unneeded_upper&=~((1LL<<dep1[i+1])|(1LL<<dep2[i+1]));
6006 ds_unneeded|=1;
6007 ds_unneeded_upper|=1;
6008 // branch taken
6009 if(!nevertaken) {
6010 //assem_debug("1:\n");
6011 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
6012 ds_unneeded,ds_unneeded_upper);
6013 // load regs
6014 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
6015 address_generation(i+1,&branch_regs[i],0);
6016 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,INVCP);
6017 ds_assemble(i+1,&branch_regs[i]);
6018 cc=get_reg(branch_regs[i].regmap,CCREG);
6019 if(cc==-1) {
6020 emit_loadreg(CCREG,cc=HOST_CCREG);
6021 // CHECK: Is the following instruction (fall thru) allocated ok?
6022 }
6023 assert(cc==HOST_CCREG);
6024 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6025 do_cc(i,i_regmap,&adj,ba[i],TAKEN,0);
6026 assem_debug("cycle count (adj)\n");
6027 if(adj) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc);
6028 load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6029 if(internal)
6030 assem_debug("branch: internal\n");
6031 else
6032 assem_debug("branch: external\n");
6033 if(internal&&is_ds[(ba[i]-start)>>2]) {
6034 ds_assemble_entry(i);
6035 }
6036 else {
6037 add_to_linker((int)out,ba[i],internal);
6038 emit_jmp(0);
6039 }
6040 }
6041 // branch not taken
6042 cop1_usable=prev_cop1_usable;
6043 if(!unconditional) {
6044 set_jump_target(nottaken,(int)out);
6045 assem_debug("1:\n");
6046 if(!likely[i]) {
6047 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
6048 ds_unneeded,ds_unneeded_upper);
6049 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
6050 address_generation(i+1,&branch_regs[i],0);
6051 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
6052 ds_assemble(i+1,&branch_regs[i]);
6053 }
6054 cc=get_reg(branch_regs[i].regmap,CCREG);
6055 if(cc==-1&&!likely[i]) {
6056 // Cycle count isn't in a register, temporarily load it then write it out
6057 emit_loadreg(CCREG,HOST_CCREG);
6058 emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),HOST_CCREG);
6059 int jaddr=(int)out;
6060 emit_jns(0);
6061 add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,NOTTAKEN,0);
6062 emit_storereg(CCREG,HOST_CCREG);
6063 }
6064 else{
6065 cc=get_reg(i_regmap,CCREG);
6066 assert(cc==HOST_CCREG);
6067 emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),cc);
6068 int jaddr=(int)out;
6069 emit_jns(0);
6070 add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,likely[i]?NULLDS:NOTTAKEN,0);
6071 }
6072 }
6073 }
6074}
6075
6076void fjump_assemble(int i,struct regstat *i_regs)
6077{
6078 signed char *i_regmap=i_regs->regmap;
6079 int cc;
6080 int match;
6081 match=match_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6082 assem_debug("fmatch=%d\n",match);
6083 int fs,cs;
6084 int eaddr;
57871462 6085 int invert=0;
6086 int internal=internal_branch(branch_regs[i].is32,ba[i]);
6087 if(i==(ba[i]-start)>>2) assem_debug("idle loop\n");
57871462 6088 if(!match) invert=1;
6089 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
6090 if(i>(ba[i]-start)>>2) invert=1;
6091 #endif
6092
e1190b87 6093 if(ooo[i]) {
57871462 6094 fs=get_reg(branch_regs[i].regmap,FSREG);
6095 address_generation(i+1,i_regs,regs[i].regmap_entry); // Is this okay?
6096 }
6097 else {
6098 fs=get_reg(i_regmap,FSREG);
6099 }
6100
6101 // Check cop1 unusable
6102 if(!cop1_usable) {
6103 cs=get_reg(i_regmap,CSREG);
6104 assert(cs>=0);
6105 emit_testimm(cs,0x20000000);
6106 eaddr=(int)out;
6107 emit_jeq(0);
6108 add_stub(FP_STUB,eaddr,(int)out,i,cs,(int)i_regs,0,0);
6109 cop1_usable=1;
6110 }
6111
e1190b87 6112 if(ooo[i]) {
57871462 6113 // Out of order execution (delay slot first)
6114 //printf("OOOE\n");
6115 ds_assemble(i+1,i_regs);
6116 int adj;
6117 uint64_t bc_unneeded=branch_regs[i].u;
6118 uint64_t bc_unneeded_upper=branch_regs[i].uu;
6119 bc_unneeded&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
6120 bc_unneeded_upper&=~((1LL<<us1[i])|(1LL<<us2[i]));
6121 bc_unneeded|=1;
6122 bc_unneeded_upper|=1;
6123 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
6124 bc_unneeded,bc_unneeded_upper);
6125 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i],rs1[i]);
6126 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
6127 cc=get_reg(branch_regs[i].regmap,CCREG);
6128 assert(cc==HOST_CCREG);
6129 do_cc(i,branch_regs[i].regmap,&adj,-1,0,invert);
6130 assem_debug("cycle count (adj)\n");
6131 if(1) {
6132 int nottaken=0;
6133 if(adj&&!invert) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc);
6134 if(1) {
6135 assert(fs>=0);
6136 emit_testimm(fs,0x800000);
6137 if(source[i]&0x10000) // BC1T
6138 {
6139 if(invert){
6140 nottaken=(int)out;
6141 emit_jeq(1);
6142 }else{
6143 add_to_linker((int)out,ba[i],internal);
6144 emit_jne(0);
6145 }
6146 }
6147 else // BC1F
6148 if(invert){
6149 nottaken=(int)out;
6150 emit_jne(1);
6151 }else{
6152 add_to_linker((int)out,ba[i],internal);
6153 emit_jeq(0);
6154 }
6155 {
6156 }
6157 } // if(!only32)
6158
6159 if(invert) {
6160 if(adj) emit_addimm(cc,-CLOCK_DIVIDER*adj,cc);
6161 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
6162 else if(match) emit_addnop(13);
6163 #endif
6164 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6165 load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6166 if(internal)
6167 assem_debug("branch: internal\n");
6168 else
6169 assem_debug("branch: external\n");
6170 if(internal&&is_ds[(ba[i]-start)>>2]) {
6171 ds_assemble_entry(i);
6172 }
6173 else {
6174 add_to_linker((int)out,ba[i],internal);
6175 emit_jmp(0);
6176 }
6177 set_jump_target(nottaken,(int)out);
6178 }
6179
6180 if(adj) {
6181 if(!invert) emit_addimm(cc,CLOCK_DIVIDER*adj,cc);
6182 }
6183 } // (!unconditional)
6184 } // if(ooo)
6185 else
6186 {
6187 // In-order execution (branch first)
6188 //printf("IOE\n");
6189 int nottaken=0;
6190 if(1) {
6191 //printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
6192 if(1) {
6193 assert(fs>=0);
6194 emit_testimm(fs,0x800000);
6195 if(source[i]&0x10000) // BC1T
6196 {
6197 nottaken=(int)out;
6198 emit_jeq(1);
6199 }
6200 else // BC1F
6201 {
6202 nottaken=(int)out;
6203 emit_jne(1);
6204 }
6205 }
6206 } // if(!unconditional)
6207 int adj;
6208 uint64_t ds_unneeded=branch_regs[i].u;
6209 uint64_t ds_unneeded_upper=branch_regs[i].uu;
6210 ds_unneeded&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
6211 ds_unneeded_upper&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
6212 if((~ds_unneeded_upper>>rt1[i+1])&1) ds_unneeded_upper&=~((1LL<<dep1[i+1])|(1LL<<dep2[i+1]));
6213 ds_unneeded|=1;
6214 ds_unneeded_upper|=1;
6215 // branch taken
6216 //assem_debug("1:\n");
6217 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
6218 ds_unneeded,ds_unneeded_upper);
6219 // load regs
6220 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
6221 address_generation(i+1,&branch_regs[i],0);
6222 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,INVCP);
6223 ds_assemble(i+1,&branch_regs[i]);
6224 cc=get_reg(branch_regs[i].regmap,CCREG);
6225 if(cc==-1) {
6226 emit_loadreg(CCREG,cc=HOST_CCREG);
6227 // CHECK: Is the following instruction (fall thru) allocated ok?
6228 }
6229 assert(cc==HOST_CCREG);
6230 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6231 do_cc(i,i_regmap,&adj,ba[i],TAKEN,0);
6232 assem_debug("cycle count (adj)\n");
6233 if(adj) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc);
6234 load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6235 if(internal)
6236 assem_debug("branch: internal\n");
6237 else
6238 assem_debug("branch: external\n");
6239 if(internal&&is_ds[(ba[i]-start)>>2]) {
6240 ds_assemble_entry(i);
6241 }
6242 else {
6243 add_to_linker((int)out,ba[i],internal);
6244 emit_jmp(0);
6245 }
6246
6247 // branch not taken
6248 if(1) { // <- FIXME (don't need this)
6249 set_jump_target(nottaken,(int)out);
6250 assem_debug("1:\n");
6251 if(!likely[i]) {
6252 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
6253 ds_unneeded,ds_unneeded_upper);
6254 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
6255 address_generation(i+1,&branch_regs[i],0);
6256 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
6257 ds_assemble(i+1,&branch_regs[i]);
6258 }
6259 cc=get_reg(branch_regs[i].regmap,CCREG);
6260 if(cc==-1&&!likely[i]) {
6261 // Cycle count isn't in a register, temporarily load it then write it out
6262 emit_loadreg(CCREG,HOST_CCREG);
6263 emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),HOST_CCREG);
6264 int jaddr=(int)out;
6265 emit_jns(0);
6266 add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,NOTTAKEN,0);
6267 emit_storereg(CCREG,HOST_CCREG);
6268 }
6269 else{
6270 cc=get_reg(i_regmap,CCREG);
6271 assert(cc==HOST_CCREG);
6272 emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),cc);
6273 int jaddr=(int)out;
6274 emit_jns(0);
6275 add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,likely[i]?NULLDS:NOTTAKEN,0);
6276 }
6277 }
6278 }
6279}
6280
6281static void pagespan_assemble(int i,struct regstat *i_regs)
6282{
6283 int s1l=get_reg(i_regs->regmap,rs1[i]);
6284 int s1h=get_reg(i_regs->regmap,rs1[i]|64);
6285 int s2l=get_reg(i_regs->regmap,rs2[i]);
6286 int s2h=get_reg(i_regs->regmap,rs2[i]|64);
6287 void *nt_branch=NULL;
6288 int taken=0;
6289 int nottaken=0;
6290 int unconditional=0;
6291 if(rs1[i]==0)
6292 {
6293 s1l=s2l;s1h=s2h;
6294 s2l=s2h=-1;
6295 }
6296 else if(rs2[i]==0)
6297 {
6298 s2l=s2h=-1;
6299 }
6300 if((i_regs->is32>>rs1[i])&(i_regs->is32>>rs2[i])&1) {
6301 s1h=s2h=-1;
6302 }
6303 int hr=0;
6304 int addr,alt,ntaddr;
6305 if(i_regs->regmap[HOST_BTREG]<0) {addr=HOST_BTREG;}
6306 else {
6307 while(hr<HOST_REGS)
6308 {
6309 if(hr!=EXCLUDE_REG && hr!=HOST_CCREG &&
6310 (i_regs->regmap[hr]&63)!=rs1[i] &&
6311 (i_regs->regmap[hr]&63)!=rs2[i] )
6312 {
6313 addr=hr++;break;
6314 }
6315 hr++;
6316 }
6317 }
6318 while(hr<HOST_REGS)
6319 {
6320 if(hr!=EXCLUDE_REG && hr!=HOST_CCREG && hr!=HOST_BTREG &&
6321 (i_regs->regmap[hr]&63)!=rs1[i] &&
6322 (i_regs->regmap[hr]&63)!=rs2[i] )
6323 {
6324 alt=hr++;break;
6325 }
6326 hr++;
6327 }
6328 if((opcode[i]&0x2E)==6) // BLEZ/BGTZ needs another register
6329 {
6330 while(hr<HOST_REGS)
6331 {
6332 if(hr!=EXCLUDE_REG && hr!=HOST_CCREG && hr!=HOST_BTREG &&
6333 (i_regs->regmap[hr]&63)!=rs1[i] &&
6334 (i_regs->regmap[hr]&63)!=rs2[i] )
6335 {
6336 ntaddr=hr;break;
6337 }
6338 hr++;
6339 }
6340 }
6341 assert(hr<HOST_REGS);
6342 if((opcode[i]&0x2e)==4||opcode[i]==0x11) { // BEQ/BNE/BEQL/BNEL/BC1
6343 load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,CCREG,CCREG);
6344 }
6345 emit_addimm(HOST_CCREG,CLOCK_DIVIDER*(ccadj[i]+2),HOST_CCREG);
6346 if(opcode[i]==2) // J
6347 {
6348 unconditional=1;
6349 }
6350 if(opcode[i]==3) // JAL
6351 {
6352 // TODO: mini_ht
6353 int rt=get_reg(i_regs->regmap,31);
6354 emit_movimm(start+i*4+8,rt);
6355 unconditional=1;
6356 }
6357 if(opcode[i]==0&&(opcode2[i]&0x3E)==8) // JR/JALR
6358 {
6359 emit_mov(s1l,addr);
6360 if(opcode2[i]==9) // JALR
6361 {
5067f341 6362 int rt=get_reg(i_regs->regmap,rt1[i]);
57871462 6363 emit_movimm(start+i*4+8,rt);
6364 }
6365 }
6366 if((opcode[i]&0x3f)==4) // BEQ
6367 {
6368 if(rs1[i]==rs2[i])
6369 {
6370 unconditional=1;
6371 }
6372 else
6373 #ifdef HAVE_CMOV_IMM
6374 if(s1h<0) {
6375 if(s2l>=0) emit_cmp(s1l,s2l);
6376 else emit_test(s1l,s1l);
6377 emit_cmov2imm_e_ne_compact(ba[i],start+i*4+8,addr);
6378 }
6379 else
6380 #endif
6381 {
6382 assert(s1l>=0);
6383 emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
6384 if(s1h>=0) {
6385 if(s2h>=0) emit_cmp(s1h,s2h);
6386 else emit_test(s1h,s1h);
6387 emit_cmovne_reg(alt,addr);
6388 }
6389 if(s2l>=0) emit_cmp(s1l,s2l);
6390 else emit_test(s1l,s1l);
6391 emit_cmovne_reg(alt,addr);
6392 }
6393 }
6394 if((opcode[i]&0x3f)==5) // BNE
6395 {
6396 #ifdef HAVE_CMOV_IMM
6397 if(s1h<0) {
6398 if(s2l>=0) emit_cmp(s1l,s2l);
6399 else emit_test(s1l,s1l);
6400 emit_cmov2imm_e_ne_compact(start+i*4+8,ba[i],addr);
6401 }
6402 else
6403 #endif
6404 {
6405 assert(s1l>=0);
6406 emit_mov2imm_compact(start+i*4+8,addr,ba[i],alt);
6407 if(s1h>=0) {
6408 if(s2h>=0) emit_cmp(s1h,s2h);
6409 else emit_test(s1h,s1h);
6410 emit_cmovne_reg(alt,addr);
6411 }
6412 if(s2l>=0) emit_cmp(s1l,s2l);
6413 else emit_test(s1l,s1l);
6414 emit_cmovne_reg(alt,addr);
6415 }
6416 }
6417 if((opcode[i]&0x3f)==0x14) // BEQL
6418 {
6419 if(s1h>=0) {
6420 if(s2h>=0) emit_cmp(s1h,s2h);
6421 else emit_test(s1h,s1h);
6422 nottaken=(int)out;
6423 emit_jne(0);
6424 }
6425 if(s2l>=0) emit_cmp(s1l,s2l);
6426 else emit_test(s1l,s1l);
6427 if(nottaken) set_jump_target(nottaken,(int)out);
6428 nottaken=(int)out;
6429 emit_jne(0);
6430 }
6431 if((opcode[i]&0x3f)==0x15) // BNEL
6432 {
6433 if(s1h>=0) {
6434 if(s2h>=0) emit_cmp(s1h,s2h);
6435 else emit_test(s1h,s1h);
6436 taken=(int)out;
6437 emit_jne(0);
6438 }
6439 if(s2l>=0) emit_cmp(s1l,s2l);
6440 else emit_test(s1l,s1l);
6441 nottaken=(int)out;
6442 emit_jeq(0);
6443 if(taken) set_jump_target(taken,(int)out);
6444 }
6445 if((opcode[i]&0x3f)==6) // BLEZ
6446 {
6447 emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
6448 emit_cmpimm(s1l,1);
6449 if(s1h>=0) emit_mov(addr,ntaddr);
6450 emit_cmovl_reg(alt,addr);
6451 if(s1h>=0) {
6452 emit_test(s1h,s1h);
6453 emit_cmovne_reg(ntaddr,addr);
6454 emit_cmovs_reg(alt,addr);
6455 }
6456 }
6457 if((opcode[i]&0x3f)==7) // BGTZ
6458 {
6459 emit_mov2imm_compact(ba[i],addr,start+i*4+8,ntaddr);
6460 emit_cmpimm(s1l,1);
6461 if(s1h>=0) emit_mov(addr,alt);
6462 emit_cmovl_reg(ntaddr,addr);
6463 if(s1h>=0) {
6464 emit_test(s1h,s1h);
6465 emit_cmovne_reg(alt,addr);
6466 emit_cmovs_reg(ntaddr,addr);
6467 }
6468 }
6469 if((opcode[i]&0x3f)==0x16) // BLEZL
6470 {
6471 assert((opcode[i]&0x3f)!=0x16);
6472 }
6473 if((opcode[i]&0x3f)==0x17) // BGTZL
6474 {
6475 assert((opcode[i]&0x3f)!=0x17);
6476 }
6477 assert(opcode[i]!=1); // BLTZ/BGEZ
6478
6479 //FIXME: Check CSREG
6480 if(opcode[i]==0x11 && opcode2[i]==0x08 ) {
6481 if((source[i]&0x30000)==0) // BC1F
6482 {
6483 emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
6484 emit_testimm(s1l,0x800000);
6485 emit_cmovne_reg(alt,addr);
6486 }
6487 if((source[i]&0x30000)==0x10000) // BC1T
6488 {
6489 emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
6490 emit_testimm(s1l,0x800000);
6491 emit_cmovne_reg(alt,addr);
6492 }
6493 if((source[i]&0x30000)==0x20000) // BC1FL
6494 {
6495 emit_testimm(s1l,0x800000);
6496 nottaken=(int)out;
6497 emit_jne(0);
6498 }
6499 if((source[i]&0x30000)==0x30000) // BC1TL
6500 {
6501 emit_testimm(s1l,0x800000);
6502 nottaken=(int)out;
6503 emit_jeq(0);
6504 }
6505 }
6506
6507 assert(i_regs->regmap[HOST_CCREG]==CCREG);
6508 wb_dirtys(regs[i].regmap,regs[i].is32,regs[i].dirty);
6509 if(likely[i]||unconditional)
6510 {
6511 emit_movimm(ba[i],HOST_BTREG);
6512 }
6513 else if(addr!=HOST_BTREG)
6514 {
6515 emit_mov(addr,HOST_BTREG);
6516 }
6517 void *branch_addr=out;
6518 emit_jmp(0);
6519 int target_addr=start+i*4+5;
6520 void *stub=out;
6521 void *compiled_target_addr=check_addr(target_addr);
6522 emit_extjump_ds((int)branch_addr,target_addr);
6523 if(compiled_target_addr) {
6524 set_jump_target((int)branch_addr,(int)compiled_target_addr);
6525 add_link(target_addr,stub);
6526 }
6527 else set_jump_target((int)branch_addr,(int)stub);
6528 if(likely[i]) {
6529 // Not-taken path
6530 set_jump_target((int)nottaken,(int)out);
6531 wb_dirtys(regs[i].regmap,regs[i].is32,regs[i].dirty);
6532 void *branch_addr=out;
6533 emit_jmp(0);
6534 int target_addr=start+i*4+8;
6535 void *stub=out;
6536 void *compiled_target_addr=check_addr(target_addr);
6537 emit_extjump_ds((int)branch_addr,target_addr);
6538 if(compiled_target_addr) {
6539 set_jump_target((int)branch_addr,(int)compiled_target_addr);
6540 add_link(target_addr,stub);
6541 }
6542 else set_jump_target((int)branch_addr,(int)stub);
6543 }
6544}
6545
6546// Assemble the delay slot for the above
6547static void pagespan_ds()
6548{
6549 assem_debug("initial delay slot:\n");
6550 u_int vaddr=start+1;
94d23bb9 6551 u_int page=get_page(vaddr);
6552 u_int vpage=get_vpage(vaddr);
57871462 6553 ll_add(jump_dirty+vpage,vaddr,(void *)out);
6554 do_dirty_stub_ds();
6555 ll_add(jump_in+page,vaddr,(void *)out);
6556 assert(regs[0].regmap_entry[HOST_CCREG]==CCREG);
6557 if(regs[0].regmap[HOST_CCREG]!=CCREG)
6558 wb_register(CCREG,regs[0].regmap_entry,regs[0].wasdirty,regs[0].was32);
6559 if(regs[0].regmap[HOST_BTREG]!=BTREG)
6560 emit_writeword(HOST_BTREG,(int)&branch_target);
6561 load_regs(regs[0].regmap_entry,regs[0].regmap,regs[0].was32,rs1[0],rs2[0]);
6562 address_generation(0,&regs[0],regs[0].regmap_entry);
b9b61529 6563 if(itype[0]==STORE||itype[0]==STORELR||(opcode[0]&0x3b)==0x39||(opcode[0]&0x3b)==0x3a)
57871462 6564 load_regs(regs[0].regmap_entry,regs[0].regmap,regs[0].was32,INVCP,INVCP);
6565 cop1_usable=0;
6566 is_delayslot=0;
6567 switch(itype[0]) {
6568 case ALU:
6569 alu_assemble(0,&regs[0]);break;
6570 case IMM16:
6571 imm16_assemble(0,&regs[0]);break;
6572 case SHIFT:
6573 shift_assemble(0,&regs[0]);break;
6574 case SHIFTIMM:
6575 shiftimm_assemble(0,&regs[0]);break;
6576 case LOAD:
6577 load_assemble(0,&regs[0]);break;
6578 case LOADLR:
6579 loadlr_assemble(0,&regs[0]);break;
6580 case STORE:
6581 store_assemble(0,&regs[0]);break;
6582 case STORELR:
6583 storelr_assemble(0,&regs[0]);break;
6584 case COP0:
6585 cop0_assemble(0,&regs[0]);break;
6586 case COP1:
6587 cop1_assemble(0,&regs[0]);break;
6588 case C1LS:
6589 c1ls_assemble(0,&regs[0]);break;
b9b61529 6590 case COP2:
6591 cop2_assemble(0,&regs[0]);break;
6592 case C2LS:
6593 c2ls_assemble(0,&regs[0]);break;
6594 case C2OP:
6595 c2op_assemble(0,&regs[0]);break;
57871462 6596 case FCONV:
6597 fconv_assemble(0,&regs[0]);break;
6598 case FLOAT:
6599 float_assemble(0,&regs[0]);break;
6600 case FCOMP:
6601 fcomp_assemble(0,&regs[0]);break;
6602 case MULTDIV:
6603 multdiv_assemble(0,&regs[0]);break;
6604 case MOV:
6605 mov_assemble(0,&regs[0]);break;
6606 case SYSCALL:
7139f3c8 6607 case HLECALL:
1e973cb0 6608 case INTCALL:
57871462 6609 case SPAN:
6610 case UJUMP:
6611 case RJUMP:
6612 case CJUMP:
6613 case SJUMP:
6614 case FJUMP:
6615 printf("Jump in the delay slot. This is probably a bug.\n");
6616 }
6617 int btaddr=get_reg(regs[0].regmap,BTREG);
6618 if(btaddr<0) {
6619 btaddr=get_reg(regs[0].regmap,-1);
6620 emit_readword((int)&branch_target,btaddr);
6621 }
6622 assert(btaddr!=HOST_CCREG);
6623 if(regs[0].regmap[HOST_CCREG]!=CCREG) emit_loadreg(CCREG,HOST_CCREG);
6624#ifdef HOST_IMM8
6625 emit_movimm(start+4,HOST_TEMPREG);
6626 emit_cmp(btaddr,HOST_TEMPREG);
6627#else
6628 emit_cmpimm(btaddr,start+4);
6629#endif
6630 int branch=(int)out;
6631 emit_jeq(0);
6632 store_regs_bt(regs[0].regmap,regs[0].is32,regs[0].dirty,-1);
6633 emit_jmp(jump_vaddr_reg[btaddr]);
6634 set_jump_target(branch,(int)out);
6635 store_regs_bt(regs[0].regmap,regs[0].is32,regs[0].dirty,start+4);
6636 load_regs_bt(regs[0].regmap,regs[0].is32,regs[0].dirty,start+4);
6637}
6638
6639// Basic liveness analysis for MIPS registers
6640void unneeded_registers(int istart,int iend,int r)
6641{
6642 int i;
6643 uint64_t u,uu,b,bu;
6644 uint64_t temp_u,temp_uu;
6645 uint64_t tdep;
6646 if(iend==slen-1) {
6647 u=1;uu=1;
6648 }else{
6649 u=unneeded_reg[iend+1];
6650 uu=unneeded_reg_upper[iend+1];
6651 u=1;uu=1;
6652 }
6653 for (i=iend;i>=istart;i--)
6654 {
6655 //printf("unneeded registers i=%d (%d,%d) r=%d\n",i,istart,iend,r);
6656 if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
6657 {
6658 // If subroutine call, flag return address as a possible branch target
6659 if(rt1[i]==31 && i<slen-2) bt[i+2]=1;
6660
6661 if(ba[i]<start || ba[i]>=(start+slen*4))
6662 {
6663 // Branch out of this block, flush all regs
6664 u=1;
6665 uu=1;
6666 /* Hexagon hack
6667 if(itype[i]==UJUMP&&rt1[i]==31)
6668 {
6669 uu=u=0x300C00F; // Discard at, v0-v1, t6-t9
6670 }
6671 if(itype[i]==RJUMP&&rs1[i]==31)
6672 {
6673 uu=u=0x300C0F3; // Discard at, a0-a3, t6-t9
6674 }
4cb76aa4 6675 if(start>0x80000400&&start<0x80000000+RAM_SIZE) {
57871462 6676 if(itype[i]==UJUMP&&rt1[i]==31)
6677 {
6678 //uu=u=0x30300FF0FLL; // Discard at, v0-v1, t0-t9, lo, hi
6679 uu=u=0x300FF0F; // Discard at, v0-v1, t0-t9
6680 }
6681 if(itype[i]==RJUMP&&rs1[i]==31)
6682 {
6683 //uu=u=0x30300FFF3LL; // Discard at, a0-a3, t0-t9, lo, hi
6684 uu=u=0x300FFF3; // Discard at, a0-a3, t0-t9
6685 }
6686 }*/
6687 branch_unneeded_reg[i]=u;
6688 branch_unneeded_reg_upper[i]=uu;
6689 // Merge in delay slot
6690 tdep=(~uu>>rt1[i+1])&1;
6691 u|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6692 uu|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6693 u&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
6694 uu&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
6695 uu&=~((tdep<<dep1[i+1])|(tdep<<dep2[i+1]));
6696 u|=1;uu|=1;
6697 // If branch is "likely" (and conditional)
6698 // then we skip the delay slot on the fall-thru path
6699 if(likely[i]) {
6700 if(i<slen-1) {
6701 u&=unneeded_reg[i+2];
6702 uu&=unneeded_reg_upper[i+2];
6703 }
6704 else
6705 {
6706 u=1;
6707 uu=1;
6708 }
6709 }
6710 }
6711 else
6712 {
6713 // Internal branch, flag target
6714 bt[(ba[i]-start)>>2]=1;
6715 if(ba[i]<=start+i*4) {
6716 // Backward branch
6717 if(itype[i]==RJUMP||itype[i]==UJUMP||(source[i]>>16)==0x1000)
6718 {
6719 // Unconditional branch
6720 temp_u=1;temp_uu=1;
6721 } else {
6722 // Conditional branch (not taken case)
6723 temp_u=unneeded_reg[i+2];
6724 temp_uu=unneeded_reg_upper[i+2];
6725 }
6726 // Merge in delay slot
6727 tdep=(~temp_uu>>rt1[i+1])&1;
6728 temp_u|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6729 temp_uu|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6730 temp_u&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
6731 temp_uu&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
6732 temp_uu&=~((tdep<<dep1[i+1])|(tdep<<dep2[i+1]));
6733 temp_u|=1;temp_uu|=1;
6734 // If branch is "likely" (and conditional)
6735 // then we skip the delay slot on the fall-thru path
6736 if(likely[i]) {
6737 if(i<slen-1) {
6738 temp_u&=unneeded_reg[i+2];
6739 temp_uu&=unneeded_reg_upper[i+2];
6740 }
6741 else
6742 {
6743 temp_u=1;
6744 temp_uu=1;
6745 }
6746 }
6747 tdep=(~temp_uu>>rt1[i])&1;
6748 temp_u|=(1LL<<rt1[i])|(1LL<<rt2[i]);
6749 temp_uu|=(1LL<<rt1[i])|(1LL<<rt2[i]);
6750 temp_u&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
6751 temp_uu&=~((1LL<<us1[i])|(1LL<<us2[i]));
6752 temp_uu&=~((tdep<<dep1[i])|(tdep<<dep2[i]));
6753 temp_u|=1;temp_uu|=1;
6754 unneeded_reg[i]=temp_u;
6755 unneeded_reg_upper[i]=temp_uu;
6756 // Only go three levels deep. This recursion can take an
6757 // excessive amount of time if there are a lot of nested loops.
6758 if(r<2) {
6759 unneeded_registers((ba[i]-start)>>2,i-1,r+1);
6760 }else{
6761 unneeded_reg[(ba[i]-start)>>2]=1;
6762 unneeded_reg_upper[(ba[i]-start)>>2]=1;
6763 }
6764 } /*else*/ if(1) {
6765 if(itype[i]==RJUMP||itype[i]==UJUMP||(source[i]>>16)==0x1000)
6766 {
6767 // Unconditional branch
6768 u=unneeded_reg[(ba[i]-start)>>2];
6769 uu=unneeded_reg_upper[(ba[i]-start)>>2];
6770 branch_unneeded_reg[i]=u;
6771 branch_unneeded_reg_upper[i]=uu;
6772 //u=1;
6773 //uu=1;
6774 //branch_unneeded_reg[i]=u;
6775 //branch_unneeded_reg_upper[i]=uu;
6776 // Merge in delay slot
6777 tdep=(~uu>>rt1[i+1])&1;
6778 u|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6779 uu|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6780 u&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
6781 uu&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
6782 uu&=~((tdep<<dep1[i+1])|(tdep<<dep2[i+1]));
6783 u|=1;uu|=1;
6784 } else {
6785 // Conditional branch
6786 b=unneeded_reg[(ba[i]-start)>>2];
6787 bu=unneeded_reg_upper[(ba[i]-start)>>2];
6788 branch_unneeded_reg[i]=b;
6789 branch_unneeded_reg_upper[i]=bu;
6790 //b=1;
6791 //bu=1;
6792 //branch_unneeded_reg[i]=b;
6793 //branch_unneeded_reg_upper[i]=bu;
6794 // Branch delay slot
6795 tdep=(~uu>>rt1[i+1])&1;
6796 b|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6797 bu|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6798 b&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
6799 bu&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
6800 bu&=~((tdep<<dep1[i+1])|(tdep<<dep2[i+1]));
6801 b|=1;bu|=1;
6802 // If branch is "likely" then we skip the
6803 // delay slot on the fall-thru path
6804 if(likely[i]) {
6805 u=b;
6806 uu=bu;
6807 if(i<slen-1) {
6808 u&=unneeded_reg[i+2];
6809 uu&=unneeded_reg_upper[i+2];
6810 //u=1;
6811 //uu=1;
6812 }
6813 } else {
6814 u&=b;
6815 uu&=bu;
6816 //u=1;
6817 //uu=1;
6818 }
6819 if(i<slen-1) {
6820 branch_unneeded_reg[i]&=unneeded_reg[i+2];
6821 branch_unneeded_reg_upper[i]&=unneeded_reg_upper[i+2];
6822 //branch_unneeded_reg[i]=1;
6823 //branch_unneeded_reg_upper[i]=1;
6824 } else {
6825 branch_unneeded_reg[i]=1;
6826 branch_unneeded_reg_upper[i]=1;
6827 }
6828 }
6829 }
6830 }
6831 }
1e973cb0 6832 else if(itype[i]==SYSCALL||itype[i]==HLECALL||itype[i]==INTCALL)
57871462 6833 {
6834 // SYSCALL instruction (software interrupt)
6835 u=1;
6836 uu=1;
6837 }
6838 else if(itype[i]==COP0 && (source[i]&0x3f)==0x18)
6839 {
6840 // ERET instruction (return from interrupt)
6841 u=1;
6842 uu=1;
6843 }
6844 //u=uu=1; // DEBUG
6845 tdep=(~uu>>rt1[i])&1;
6846 // Written registers are unneeded
6847 u|=1LL<<rt1[i];
6848 u|=1LL<<rt2[i];
6849 uu|=1LL<<rt1[i];
6850 uu|=1LL<<rt2[i];
6851 // Accessed registers are needed
6852 u&=~(1LL<<rs1[i]);
6853 u&=~(1LL<<rs2[i]);
6854 uu&=~(1LL<<us1[i]);
6855 uu&=~(1LL<<us2[i]);
6856 // Source-target dependencies
6857 uu&=~(tdep<<dep1[i]);
6858 uu&=~(tdep<<dep2[i]);
6859 // R0 is always unneeded
6860 u|=1;uu|=1;
6861 // Save it
6862 unneeded_reg[i]=u;
6863 unneeded_reg_upper[i]=uu;
6864 /*
6865 printf("ur (%d,%d) %x: ",istart,iend,start+i*4);
6866 printf("U:");
6867 int r;
6868 for(r=1;r<=CCREG;r++) {
6869 if((unneeded_reg[i]>>r)&1) {
6870 if(r==HIREG) printf(" HI");
6871 else if(r==LOREG) printf(" LO");
6872 else printf(" r%d",r);
6873 }
6874 }
6875 printf(" UU:");
6876 for(r=1;r<=CCREG;r++) {
6877 if(((unneeded_reg_upper[i]&~unneeded_reg[i])>>r)&1) {
6878 if(r==HIREG) printf(" HI");
6879 else if(r==LOREG) printf(" LO");
6880 else printf(" r%d",r);
6881 }
6882 }
6883 printf("\n");*/
6884 }
252c20fc 6885#ifdef FORCE32
6886 for (i=iend;i>=istart;i--)
6887 {
6888 unneeded_reg_upper[i]=branch_unneeded_reg_upper[i]=-1LL;
6889 }
6890#endif
57871462 6891}
6892
6893// Identify registers which are likely to contain 32-bit values
6894// This is used to predict whether any branches will jump to a
6895// location with 64-bit values in registers.
6896static void provisional_32bit()
6897{
6898 int i,j;
6899 uint64_t is32=1;
6900 uint64_t lastbranch=1;
6901
6902 for(i=0;i<slen;i++)
6903 {
6904 if(i>0) {
6905 if(itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP) {
6906 if(i>1) is32=lastbranch;
6907 else is32=1;
6908 }
6909 }
6910 if(i>1)
6911 {
6912 if(itype[i-2]==CJUMP||itype[i-2]==SJUMP||itype[i-2]==FJUMP) {
6913 if(likely[i-2]) {
6914 if(i>2) is32=lastbranch;
6915 else is32=1;
6916 }
6917 }
6918 if((opcode[i-2]&0x2f)==0x05) // BNE/BNEL
6919 {
6920 if(rs1[i-2]==0||rs2[i-2]==0)
6921 {
6922 if(rs1[i-2]) {
6923 is32|=1LL<<rs1[i-2];
6924 }
6925 if(rs2[i-2]) {
6926 is32|=1LL<<rs2[i-2];
6927 }
6928 }
6929 }
6930 }
6931 // If something jumps here with 64-bit values
6932 // then promote those registers to 64 bits
6933 if(bt[i])
6934 {
6935 uint64_t temp_is32=is32;
6936 for(j=i-1;j>=0;j--)
6937 {
6938 if(ba[j]==start+i*4)
6939 //temp_is32&=branch_regs[j].is32;
6940 temp_is32&=p32[j];
6941 }
6942 for(j=i;j<slen;j++)
6943 {
6944 if(ba[j]==start+i*4)
6945 temp_is32=1;
6946 }
6947 is32=temp_is32;
6948 }
6949 int type=itype[i];
6950 int op=opcode[i];
6951 int op2=opcode2[i];
6952 int rt=rt1[i];
6953 int s1=rs1[i];
6954 int s2=rs2[i];
6955 if(type==UJUMP||type==RJUMP||type==CJUMP||type==SJUMP||type==FJUMP) {
6956 // Branches don't write registers, consider the delay slot instead.
6957 type=itype[i+1];
6958 op=opcode[i+1];
6959 op2=opcode2[i+1];
6960 rt=rt1[i+1];
6961 s1=rs1[i+1];
6962 s2=rs2[i+1];
6963 lastbranch=is32;
6964 }
6965 switch(type) {
6966 case LOAD:
6967 if(opcode[i]==0x27||opcode[i]==0x37|| // LWU/LD
6968 opcode[i]==0x1A||opcode[i]==0x1B) // LDL/LDR
6969 is32&=~(1LL<<rt);
6970 else
6971 is32|=1LL<<rt;
6972 break;
6973 case STORE:
6974 case STORELR:
6975 break;
6976 case LOADLR:
6977 if(op==0x1a||op==0x1b) is32&=~(1LL<<rt); // LDR/LDL
6978 if(op==0x22) is32|=1LL<<rt; // LWL
6979 break;
6980 case IMM16:
6981 if (op==0x08||op==0x09|| // ADDI/ADDIU
6982 op==0x0a||op==0x0b|| // SLTI/SLTIU
6983 op==0x0c|| // ANDI
6984 op==0x0f) // LUI
6985 {
6986 is32|=1LL<<rt;
6987 }
6988 if(op==0x18||op==0x19) { // DADDI/DADDIU
6989 is32&=~(1LL<<rt);
6990 //if(imm[i]==0)
6991 // is32|=((is32>>s1)&1LL)<<rt;
6992 }
6993 if(op==0x0d||op==0x0e) { // ORI/XORI
6994 uint64_t sr=((is32>>s1)&1LL);
6995 is32&=~(1LL<<rt);
6996 is32|=sr<<rt;
6997 }
6998 break;
6999 case UJUMP:
7000 break;
7001 case RJUMP:
7002 break;
7003 case CJUMP:
7004 break;
7005 case SJUMP:
7006 break;
7007 case FJUMP:
7008 break;
7009 case ALU:
7010 if(op2>=0x20&&op2<=0x23) { // ADD/ADDU/SUB/SUBU
7011 is32|=1LL<<rt;
7012 }
7013 if(op2==0x2a||op2==0x2b) { // SLT/SLTU
7014 is32|=1LL<<rt;
7015 }
7016 else if(op2>=0x24&&op2<=0x27) { // AND/OR/XOR/NOR
7017 uint64_t sr=((is32>>s1)&(is32>>s2)&1LL);
7018 is32&=~(1LL<<rt);
7019 is32|=sr<<rt;
7020 }
7021 else if(op2>=0x2c&&op2<=0x2d) { // DADD/DADDU
7022 if(s1==0&&s2==0) {
7023 is32|=1LL<<rt;
7024 }
7025 else if(s2==0) {
7026 uint64_t sr=((is32>>s1)&1LL);
7027 is32&=~(1LL<<rt);
7028 is32|=sr<<rt;
7029 }
7030 else if(s1==0) {
7031 uint64_t sr=((is32>>s2)&1LL);
7032 is32&=~(1LL<<rt);
7033 is32|=sr<<rt;
7034 }
7035 else {
7036 is32&=~(1LL<<rt);
7037 }
7038 }
7039 else if(op2>=0x2e&&op2<=0x2f) { // DSUB/DSUBU
7040 if(s1==0&&s2==0) {
7041 is32|=1LL<<rt;
7042 }
7043 else if(s2==0) {
7044 uint64_t sr=((is32>>s1)&1LL);
7045 is32&=~(1LL<<rt);
7046 is32|=sr<<rt;
7047 }
7048 else {
7049 is32&=~(1LL<<rt);
7050 }
7051 }
7052 break;
7053 case MULTDIV:
7054 if (op2>=0x1c&&op2<=0x1f) { // DMULT/DMULTU/DDIV/DDIVU
7055 is32&=~((1LL<<HIREG)|(1LL<<LOREG));
7056 }
7057 else {
7058 is32|=(1LL<<HIREG)|(1LL<<LOREG);
7059 }
7060 break;
7061 case MOV:
7062 {
7063 uint64_t sr=((is32>>s1)&1LL);
7064 is32&=~(1LL<<rt);
7065 is32|=sr<<rt;
7066 }
7067 break;
7068 case SHIFT:
7069 if(op2>=0x14&&op2<=0x17) is32&=~(1LL<<rt); // DSLLV/DSRLV/DSRAV
7070 else is32|=1LL<<rt; // SLLV/SRLV/SRAV
7071 break;
7072 case SHIFTIMM:
7073 is32|=1LL<<rt;
7074 // DSLL/DSRL/DSRA/DSLL32/DSRL32 but not DSRA32 have 64-bit result
7075 if(op2>=0x38&&op2<0x3f) is32&=~(1LL<<rt);
7076 break;
7077 case COP0:
7078 if(op2==0) is32|=1LL<<rt; // MFC0
7079 break;
7080 case COP1:
b9b61529 7081 case COP2:
57871462 7082 if(op2==0) is32|=1LL<<rt; // MFC1
7083 if(op2==1) is32&=~(1LL<<rt); // DMFC1
7084 if(op2==2) is32|=1LL<<rt; // CFC1
7085 break;
7086 case C1LS:
b9b61529 7087 case C2LS:
57871462 7088 break;
7089 case FLOAT:
7090 case FCONV:
7091 break;
7092 case FCOMP:
7093 break;
b9b61529 7094 case C2OP:
57871462 7095 case SYSCALL:
7139f3c8 7096 case HLECALL:
57871462 7097 break;
7098 default:
7099 break;
7100 }
7101 is32|=1;
7102 p32[i]=is32;
7103
7104 if(i>0)
7105 {
7106 if(itype[i-1]==UJUMP||itype[i-1]==RJUMP||(source[i-1]>>16)==0x1000)
7107 {
7108 if(rt1[i-1]==31) // JAL/JALR
7109 {
7110 // Subroutine call will return here, don't alloc any registers
7111 is32=1;
7112 }
7113 else if(i+1<slen)
7114 {
7115 // Internal branch will jump here, match registers to caller
7116 is32=0x3FFFFFFFFLL;
7117 }
7118 }
7119 }
7120 }
7121}
7122
7123// Identify registers which may be assumed to contain 32-bit values
7124// and where optimizations will rely on this.
7125// This is used to determine whether backward branches can safely
7126// jump to a location with 64-bit values in registers.
7127static void provisional_r32()
7128{
7129 u_int r32=0;
7130 int i;
7131
7132 for (i=slen-1;i>=0;i--)
7133 {
7134 int hr;
7135 if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
7136 {
7137 if(ba[i]<start || ba[i]>=(start+slen*4))
7138 {
7139 // Branch out of this block, don't need anything
7140 r32=0;
7141 }
7142 else
7143 {
7144 // Internal branch
7145 // Need whatever matches the target
7146 // (and doesn't get overwritten by the delay slot instruction)
7147 r32=0;
7148 int t=(ba[i]-start)>>2;
7149 if(ba[i]>start+i*4) {
7150 // Forward branch
7151 //if(!(requires_32bit[t]&~regs[i].was32))
7152 // r32|=requires_32bit[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
7153 if(!(pr32[t]&~regs[i].was32))
7154 r32|=pr32[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
7155 }else{
7156 // Backward branch
7157 if(!(regs[t].was32&~unneeded_reg_upper[t]&~regs[i].was32))
7158 r32|=regs[t].was32&~unneeded_reg_upper[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
7159 }
7160 }
7161 // Conditional branch may need registers for following instructions
7162 if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000)
7163 {
7164 if(i<slen-2) {
7165 //r32|=requires_32bit[i+2];
7166 r32|=pr32[i+2];
7167 r32&=regs[i].was32;
7168 // Mark this address as a branch target since it may be called
7169 // upon return from interrupt
7170 //bt[i+2]=1;
7171 }
7172 }
7173 // Merge in delay slot
7174 if(!likely[i]) {
7175 // These are overwritten unless the branch is "likely"
7176 // and the delay slot is nullified if not taken
7177 r32&=~(1LL<<rt1[i+1]);
7178 r32&=~(1LL<<rt2[i+1]);
7179 }
7180 // Assume these are needed (delay slot)
7181 if(us1[i+1]>0)
7182 {
7183 if((regs[i].was32>>us1[i+1])&1) r32|=1LL<<us1[i+1];
7184 }
7185 if(us2[i+1]>0)
7186 {
7187 if((regs[i].was32>>us2[i+1])&1) r32|=1LL<<us2[i+1];
7188 }
7189 if(dep1[i+1]&&!((unneeded_reg_upper[i]>>dep1[i+1])&1))
7190 {
7191 if((regs[i].was32>>dep1[i+1])&1) r32|=1LL<<dep1[i+1];
7192 }
7193 if(dep2[i+1]&&!((unneeded_reg_upper[i]>>dep2[i+1])&1))
7194 {
7195 if((regs[i].was32>>dep2[i+1])&1) r32|=1LL<<dep2[i+1];
7196 }
7197 }
1e973cb0 7198 else if(itype[i]==SYSCALL||itype[i]==HLECALL||itype[i]==INTCALL)
57871462 7199 {
7200 // SYSCALL instruction (software interrupt)
7201 r32=0;
7202 }
7203 else if(itype[i]==COP0 && (source[i]&0x3f)==0x18)
7204 {
7205 // ERET instruction (return from interrupt)
7206 r32=0;
7207 }
7208 // Check 32 bits
7209 r32&=~(1LL<<rt1[i]);
7210 r32&=~(1LL<<rt2[i]);
7211 if(us1[i]>0)
7212 {
7213 if((regs[i].was32>>us1[i])&1) r32|=1LL<<us1[i];
7214 }
7215 if(us2[i]>0)
7216 {
7217 if((regs[i].was32>>us2[i])&1) r32|=1LL<<us2[i];
7218 }
7219 if(dep1[i]&&!((unneeded_reg_upper[i]>>dep1[i])&1))
7220 {
7221 if((regs[i].was32>>dep1[i])&1) r32|=1LL<<dep1[i];
7222 }
7223 if(dep2[i]&&!((unneeded_reg_upper[i]>>dep2[i])&1))
7224 {
7225 if((regs[i].was32>>dep2[i])&1) r32|=1LL<<dep2[i];
7226 }
7227 //requires_32bit[i]=r32;
7228 pr32[i]=r32;
7229
7230 // Dirty registers which are 32-bit, require 32-bit input
7231 // as they will be written as 32-bit values
7232 for(hr=0;hr<HOST_REGS;hr++)
7233 {
7234 if(regs[i].regmap_entry[hr]>0&&regs[i].regmap_entry[hr]<64) {
7235 if((regs[i].was32>>regs[i].regmap_entry[hr])&(regs[i].wasdirty>>hr)&1) {
7236 if(!((unneeded_reg_upper[i]>>regs[i].regmap_entry[hr])&1))
7237 pr32[i]|=1LL<<regs[i].regmap_entry[hr];
7238 //requires_32bit[i]|=1LL<<regs[i].regmap_entry[hr];
7239 }
7240 }
7241 }
7242 }
7243}
7244
7245// Write back dirty registers as soon as we will no longer modify them,
7246// so that we don't end up with lots of writes at the branches.
7247void clean_registers(int istart,int iend,int wr)
7248{
7249 int i;
7250 int r;
7251 u_int will_dirty_i,will_dirty_next,temp_will_dirty;
7252 u_int wont_dirty_i,wont_dirty_next,temp_wont_dirty;
7253 if(iend==slen-1) {
7254 will_dirty_i=will_dirty_next=0;
7255 wont_dirty_i=wont_dirty_next=0;
7256 }else{
7257 will_dirty_i=will_dirty_next=will_dirty[iend+1];
7258 wont_dirty_i=wont_dirty_next=wont_dirty[iend+1];
7259 }
7260 for (i=iend;i>=istart;i--)
7261 {
7262 if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
7263 {
7264 if(ba[i]<start || ba[i]>=(start+slen*4))
7265 {
7266 // Branch out of this block, flush all regs
7267 if(itype[i]==RJUMP||itype[i]==UJUMP||(source[i]>>16)==0x1000)
7268 {
7269 // Unconditional branch
7270 will_dirty_i=0;
7271 wont_dirty_i=0;
7272 // Merge in delay slot (will dirty)
7273 for(r=0;r<HOST_REGS;r++) {
7274 if(r!=EXCLUDE_REG) {
7275 if((branch_regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7276 if((branch_regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7277 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7278 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7279 if((branch_regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7280 if(branch_regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7281 if(branch_regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7282 if((regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7283 if((regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7284 if((regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7285 if((regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7286 if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7287 if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7288 if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7289 }
7290 }
7291 }
7292 else
7293 {
7294 // Conditional branch
7295 will_dirty_i=0;
7296 wont_dirty_i=wont_dirty_next;
7297 // Merge in delay slot (will dirty)
7298 for(r=0;r<HOST_REGS;r++) {
7299 if(r!=EXCLUDE_REG) {
7300 if(!likely[i]) {
7301 // Might not dirty if likely branch is not taken
7302 if((branch_regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7303 if((branch_regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7304 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7305 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7306 if((branch_regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7307 if(branch_regs[i].regmap[r]==0) will_dirty_i&=~(1<<r);
7308 if(branch_regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7309 //if((regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7310 //if((regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7311 if((regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7312 if((regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7313 if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7314 if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7315 if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7316 }
7317 }
7318 }
7319 }
7320 // Merge in delay slot (wont dirty)
7321 for(r=0;r<HOST_REGS;r++) {
7322 if(r!=EXCLUDE_REG) {
7323 if((regs[i].regmap[r]&63)==rt1[i]) wont_dirty_i|=1<<r;
7324 if((regs[i].regmap[r]&63)==rt2[i]) wont_dirty_i|=1<<r;
7325 if((regs[i].regmap[r]&63)==rt1[i+1]) wont_dirty_i|=1<<r;
7326 if((regs[i].regmap[r]&63)==rt2[i+1]) wont_dirty_i|=1<<r;
7327 if(regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
7328 if((branch_regs[i].regmap[r]&63)==rt1[i]) wont_dirty_i|=1<<r;
7329 if((branch_regs[i].regmap[r]&63)==rt2[i]) wont_dirty_i|=1<<r;
7330 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) wont_dirty_i|=1<<r;
7331 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) wont_dirty_i|=1<<r;
7332 if(branch_regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
7333 }
7334 }
7335 if(wr) {
7336 #ifndef DESTRUCTIVE_WRITEBACK
7337 branch_regs[i].dirty&=wont_dirty_i;
7338 #endif
7339 branch_regs[i].dirty|=will_dirty_i;
7340 }
7341 }
7342 else
7343 {
7344 // Internal branch
7345 if(ba[i]<=start+i*4) {
7346 // Backward branch
7347 if(itype[i]==RJUMP||itype[i]==UJUMP||(source[i]>>16)==0x1000)
7348 {
7349 // Unconditional branch
7350 temp_will_dirty=0;
7351 temp_wont_dirty=0;
7352 // Merge in delay slot (will dirty)
7353 for(r=0;r<HOST_REGS;r++) {
7354 if(r!=EXCLUDE_REG) {
7355 if((branch_regs[i].regmap[r]&63)==rt1[i]) temp_will_dirty|=1<<r;
7356 if((branch_regs[i].regmap[r]&63)==rt2[i]) temp_will_dirty|=1<<r;
7357 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) temp_will_dirty|=1<<r;
7358 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) temp_will_dirty|=1<<r;
7359 if((branch_regs[i].regmap[r]&63)>33) temp_will_dirty&=~(1<<r);
7360 if(branch_regs[i].regmap[r]<=0) temp_will_dirty&=~(1<<r);
7361 if(branch_regs[i].regmap[r]==CCREG) temp_will_dirty|=1<<r;
7362 if((regs[i].regmap[r]&63)==rt1[i]) temp_will_dirty|=1<<r;
7363 if((regs[i].regmap[r]&63)==rt2[i]) temp_will_dirty|=1<<r;
7364 if((regs[i].regmap[r]&63)==rt1[i+1]) temp_will_dirty|=1<<r;
7365 if((regs[i].regmap[r]&63)==rt2[i+1]) temp_will_dirty|=1<<r;
7366 if((regs[i].regmap[r]&63)>33) temp_will_dirty&=~(1<<r);
7367 if(regs[i].regmap[r]<=0) temp_will_dirty&=~(1<<r);
7368 if(regs[i].regmap[r]==CCREG) temp_will_dirty|=1<<r;
7369 }
7370 }
7371 } else {
7372 // Conditional branch (not taken case)
7373 temp_will_dirty=will_dirty_next;
7374 temp_wont_dirty=wont_dirty_next;
7375 // Merge in delay slot (will dirty)
7376 for(r=0;r<HOST_REGS;r++) {
7377 if(r!=EXCLUDE_REG) {
7378 if(!likely[i]) {
7379 // Will not dirty if likely branch is not taken
7380 if((branch_regs[i].regmap[r]&63)==rt1[i]) temp_will_dirty|=1<<r;
7381 if((branch_regs[i].regmap[r]&63)==rt2[i]) temp_will_dirty|=1<<r;
7382 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) temp_will_dirty|=1<<r;
7383 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) temp_will_dirty|=1<<r;
7384 if((branch_regs[i].regmap[r]&63)>33) temp_will_dirty&=~(1<<r);
7385 if(branch_regs[i].regmap[r]==0) temp_will_dirty&=~(1<<r);
7386 if(branch_regs[i].regmap[r]==CCREG) temp_will_dirty|=1<<r;
7387 //if((regs[i].regmap[r]&63)==rt1[i]) temp_will_dirty|=1<<r;
7388 //if((regs[i].regmap[r]&63)==rt2[i]) temp_will_dirty|=1<<r;
7389 if((regs[i].regmap[r]&63)==rt1[i+1]) temp_will_dirty|=1<<r;
7390 if((regs[i].regmap[r]&63)==rt2[i+1]) temp_will_dirty|=1<<r;
7391 if((regs[i].regmap[r]&63)>33) temp_will_dirty&=~(1<<r);
7392 if(regs[i].regmap[r]<=0) temp_will_dirty&=~(1<<r);
7393 if(regs[i].regmap[r]==CCREG) temp_will_dirty|=1<<r;
7394 }
7395 }
7396 }
7397 }
7398 // Merge in delay slot (wont dirty)
7399 for(r=0;r<HOST_REGS;r++) {
7400 if(r!=EXCLUDE_REG) {
7401 if((regs[i].regmap[r]&63)==rt1[i]) temp_wont_dirty|=1<<r;
7402 if((regs[i].regmap[r]&63)==rt2[i]) temp_wont_dirty|=1<<r;
7403 if((regs[i].regmap[r]&63)==rt1[i+1]) temp_wont_dirty|=1<<r;
7404 if((regs[i].regmap[r]&63)==rt2[i+1]) temp_wont_dirty|=1<<r;
7405 if(regs[i].regmap[r]==CCREG) temp_wont_dirty|=1<<r;
7406 if((branch_regs[i].regmap[r]&63)==rt1[i]) temp_wont_dirty|=1<<r;
7407 if((branch_regs[i].regmap[r]&63)==rt2[i]) temp_wont_dirty|=1<<r;
7408 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) temp_wont_dirty|=1<<r;
7409 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) temp_wont_dirty|=1<<r;
7410 if(branch_regs[i].regmap[r]==CCREG) temp_wont_dirty|=1<<r;
7411 }
7412 }
7413 // Deal with changed mappings
7414 if(i<iend) {
7415 for(r=0;r<HOST_REGS;r++) {
7416 if(r!=EXCLUDE_REG) {
7417 if(regs[i].regmap[r]!=regmap_pre[i][r]) {
7418 temp_will_dirty&=~(1<<r);
7419 temp_wont_dirty&=~(1<<r);
7420 if((regmap_pre[i][r]&63)>0 && (regmap_pre[i][r]&63)<34) {
7421 temp_will_dirty|=((unneeded_reg[i]>>(regmap_pre[i][r]&63))&1)<<r;
7422 temp_wont_dirty|=((unneeded_reg[i]>>(regmap_pre[i][r]&63))&1)<<r;
7423 } else {
7424 temp_will_dirty|=1<<r;
7425 temp_wont_dirty|=1<<r;
7426 }
7427 }
7428 }
7429 }
7430 }
7431 if(wr) {
7432 will_dirty[i]=temp_will_dirty;
7433 wont_dirty[i]=temp_wont_dirty;
7434 clean_registers((ba[i]-start)>>2,i-1,0);
7435 }else{
7436 // Limit recursion. It can take an excessive amount
7437 // of time if there are a lot of nested loops.
7438 will_dirty[(ba[i]-start)>>2]=0;
7439 wont_dirty[(ba[i]-start)>>2]=-1;
7440 }
7441 }
7442 /*else*/ if(1)
7443 {
7444 if(itype[i]==RJUMP||itype[i]==UJUMP||(source[i]>>16)==0x1000)
7445 {
7446 // Unconditional branch
7447 will_dirty_i=0;
7448 wont_dirty_i=0;
7449 //if(ba[i]>start+i*4) { // Disable recursion (for debugging)
7450 for(r=0;r<HOST_REGS;r++) {
7451 if(r!=EXCLUDE_REG) {
7452 if(branch_regs[i].regmap[r]==regs[(ba[i]-start)>>2].regmap_entry[r]) {
7453 will_dirty_i|=will_dirty[(ba[i]-start)>>2]&(1<<r);
7454 wont_dirty_i|=wont_dirty[(ba[i]-start)>>2]&(1<<r);
7455 }
e3234ecf 7456 if(branch_regs[i].regmap[r]>=0) {
7457 will_dirty_i|=((unneeded_reg[(ba[i]-start)>>2]>>(branch_regs[i].regmap[r]&63))&1)<<r;
7458 wont_dirty_i|=((unneeded_reg[(ba[i]-start)>>2]>>(branch_regs[i].regmap[r]&63))&1)<<r;
7459 }
57871462 7460 }
7461 }
7462 //}
7463 // Merge in delay slot
7464 for(r=0;r<HOST_REGS;r++) {
7465 if(r!=EXCLUDE_REG) {
7466 if((branch_regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7467 if((branch_regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7468 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7469 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7470 if((branch_regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7471 if(branch_regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7472 if(branch_regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7473 if((regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7474 if((regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7475 if((regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7476 if((regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7477 if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7478 if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7479 if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7480 }
7481 }
7482 } else {
7483 // Conditional branch
7484 will_dirty_i=will_dirty_next;
7485 wont_dirty_i=wont_dirty_next;
7486 //if(ba[i]>start+i*4) { // Disable recursion (for debugging)
7487 for(r=0;r<HOST_REGS;r++) {
7488 if(r!=EXCLUDE_REG) {
e3234ecf 7489 signed char target_reg=branch_regs[i].regmap[r];
7490 if(target_reg==regs[(ba[i]-start)>>2].regmap_entry[r]) {
57871462 7491 will_dirty_i&=will_dirty[(ba[i]-start)>>2]&(1<<r);
7492 wont_dirty_i|=wont_dirty[(ba[i]-start)>>2]&(1<<r);
7493 }
e3234ecf 7494 else if(target_reg>=0) {
7495 will_dirty_i&=((unneeded_reg[(ba[i]-start)>>2]>>(target_reg&63))&1)<<r;
7496 wont_dirty_i|=((unneeded_reg[(ba[i]-start)>>2]>>(target_reg&63))&1)<<r;
57871462 7497 }
7498 // Treat delay slot as part of branch too
7499 /*if(regs[i+1].regmap[r]==regs[(ba[i]-start)>>2].regmap_entry[r]) {
7500 will_dirty[i+1]&=will_dirty[(ba[i]-start)>>2]&(1<<r);
7501 wont_dirty[i+1]|=wont_dirty[(ba[i]-start)>>2]&(1<<r);
7502 }
7503 else
7504 {
7505 will_dirty[i+1]&=~(1<<r);
7506 }*/
7507 }
7508 }
7509 //}
7510 // Merge in delay slot
7511 for(r=0;r<HOST_REGS;r++) {
7512 if(r!=EXCLUDE_REG) {
7513 if(!likely[i]) {
7514 // Might not dirty if likely branch is not taken
7515 if((branch_regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7516 if((branch_regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7517 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7518 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7519 if((branch_regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7520 if(branch_regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7521 if(branch_regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7522 //if((regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7523 //if((regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7524 if((regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7525 if((regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7526 if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7527 if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7528 if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7529 }
7530 }
7531 }
7532 }
e3234ecf 7533 // Merge in delay slot (won't dirty)
57871462 7534 for(r=0;r<HOST_REGS;r++) {
7535 if(r!=EXCLUDE_REG) {
7536 if((regs[i].regmap[r]&63)==rt1[i]) wont_dirty_i|=1<<r;
7537 if((regs[i].regmap[r]&63)==rt2[i]) wont_dirty_i|=1<<r;
7538 if((regs[i].regmap[r]&63)==rt1[i+1]) wont_dirty_i|=1<<r;
7539 if((regs[i].regmap[r]&63)==rt2[i+1]) wont_dirty_i|=1<<r;
7540 if(regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
7541 if((branch_regs[i].regmap[r]&63)==rt1[i]) wont_dirty_i|=1<<r;
7542 if((branch_regs[i].regmap[r]&63)==rt2[i]) wont_dirty_i|=1<<r;
7543 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) wont_dirty_i|=1<<r;
7544 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) wont_dirty_i|=1<<r;
7545 if(branch_regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
7546 }
7547 }
7548 if(wr) {
7549 #ifndef DESTRUCTIVE_WRITEBACK
7550 branch_regs[i].dirty&=wont_dirty_i;
7551 #endif
7552 branch_regs[i].dirty|=will_dirty_i;
7553 }
7554 }
7555 }
7556 }
1e973cb0 7557 else if(itype[i]==SYSCALL||itype[i]==HLECALL||itype[i]==INTCALL)
57871462 7558 {
7559 // SYSCALL instruction (software interrupt)
7560 will_dirty_i=0;
7561 wont_dirty_i=0;
7562 }
7563 else if(itype[i]==COP0 && (source[i]&0x3f)==0x18)
7564 {
7565 // ERET instruction (return from interrupt)
7566 will_dirty_i=0;
7567 wont_dirty_i=0;
7568 }
7569 will_dirty_next=will_dirty_i;
7570 wont_dirty_next=wont_dirty_i;
7571 for(r=0;r<HOST_REGS;r++) {
7572 if(r!=EXCLUDE_REG) {
7573 if((regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7574 if((regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7575 if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7576 if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7577 if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7578 if((regs[i].regmap[r]&63)==rt1[i]) wont_dirty_i|=1<<r;
7579 if((regs[i].regmap[r]&63)==rt2[i]) wont_dirty_i|=1<<r;
7580 if(regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
7581 if(i>istart) {
7582 if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&itype[i]!=CJUMP&&itype[i]!=SJUMP&&itype[i]!=FJUMP)
7583 {
7584 // Don't store a register immediately after writing it,
7585 // may prevent dual-issue.
7586 if((regs[i].regmap[r]&63)==rt1[i-1]) wont_dirty_i|=1<<r;
7587 if((regs[i].regmap[r]&63)==rt2[i-1]) wont_dirty_i|=1<<r;
7588 }
7589 }
7590 }
7591 }
7592 // Save it
7593 will_dirty[i]=will_dirty_i;
7594 wont_dirty[i]=wont_dirty_i;
7595 // Mark registers that won't be dirtied as not dirty
7596 if(wr) {
7597 /*printf("wr (%d,%d) %x will:",istart,iend,start+i*4);
7598 for(r=0;r<HOST_REGS;r++) {
7599 if((will_dirty_i>>r)&1) {
7600 printf(" r%d",r);
7601 }
7602 }
7603 printf("\n");*/
7604
7605 //if(i==istart||(itype[i-1]!=RJUMP&&itype[i-1]!=UJUMP&&itype[i-1]!=CJUMP&&itype[i-1]!=SJUMP&&itype[i-1]!=FJUMP)) {
7606 regs[i].dirty|=will_dirty_i;
7607 #ifndef DESTRUCTIVE_WRITEBACK
7608 regs[i].dirty&=wont_dirty_i;
7609 if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
7610 {
7611 if(i<iend-1&&itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000) {
7612 for(r=0;r<HOST_REGS;r++) {
7613 if(r!=EXCLUDE_REG) {
7614 if(regs[i].regmap[r]==regmap_pre[i+2][r]) {
7615 regs[i+2].wasdirty&=wont_dirty_i|~(1<<r);
7616 }else {/*printf("i: %x (%d) mismatch(+2): %d\n",start+i*4,i,r);/*assert(!((wont_dirty_i>>r)&1));*/}
7617 }
7618 }
7619 }
7620 }
7621 else
7622 {
7623 if(i<iend) {
7624 for(r=0;r<HOST_REGS;r++) {
7625 if(r!=EXCLUDE_REG) {
7626 if(regs[i].regmap[r]==regmap_pre[i+1][r]) {
7627 regs[i+1].wasdirty&=wont_dirty_i|~(1<<r);
7628 }else {/*printf("i: %x (%d) mismatch(+1): %d\n",start+i*4,i,r);/*assert(!((wont_dirty_i>>r)&1));*/}
7629 }
7630 }
7631 }
7632 }
7633 #endif
7634 //}
7635 }
7636 // Deal with changed mappings
7637 temp_will_dirty=will_dirty_i;
7638 temp_wont_dirty=wont_dirty_i;
7639 for(r=0;r<HOST_REGS;r++) {
7640 if(r!=EXCLUDE_REG) {
7641 int nr;
7642 if(regs[i].regmap[r]==regmap_pre[i][r]) {
7643 if(wr) {
7644 #ifndef DESTRUCTIVE_WRITEBACK
7645 regs[i].wasdirty&=wont_dirty_i|~(1<<r);
7646 #endif
7647 regs[i].wasdirty|=will_dirty_i&(1<<r);
7648 }
7649 }
f776eb14 7650 else if(regmap_pre[i][r]>=0&&(nr=get_reg(regs[i].regmap,regmap_pre[i][r]))>=0) {
57871462 7651 // Register moved to a different register
7652 will_dirty_i&=~(1<<r);
7653 wont_dirty_i&=~(1<<r);
7654 will_dirty_i|=((temp_will_dirty>>nr)&1)<<r;
7655 wont_dirty_i|=((temp_wont_dirty>>nr)&1)<<r;
7656 if(wr) {
7657 #ifndef DESTRUCTIVE_WRITEBACK
7658 regs[i].wasdirty&=wont_dirty_i|~(1<<r);
7659 #endif
7660 regs[i].wasdirty|=will_dirty_i&(1<<r);
7661 }
7662 }
7663 else {
7664 will_dirty_i&=~(1<<r);
7665 wont_dirty_i&=~(1<<r);
7666 if((regmap_pre[i][r]&63)>0 && (regmap_pre[i][r]&63)<34) {
7667 will_dirty_i|=((unneeded_reg[i]>>(regmap_pre[i][r]&63))&1)<<r;
7668 wont_dirty_i|=((unneeded_reg[i]>>(regmap_pre[i][r]&63))&1)<<r;
7669 } else {
7670 wont_dirty_i|=1<<r;
7671 /*printf("i: %x (%d) mismatch: %d\n",start+i*4,i,r);/*assert(!((will_dirty>>r)&1));*/
7672 }
7673 }
7674 }
7675 }
7676 }
7677}
7678
7679 /* disassembly */
7680void disassemble_inst(int i)
7681{
7682 if (bt[i]) printf("*"); else printf(" ");
7683 switch(itype[i]) {
7684 case UJUMP:
7685 printf (" %x: %s %8x\n",start+i*4,insn[i],ba[i]);break;
7686 case CJUMP:
7687 printf (" %x: %s r%d,r%d,%8x\n",start+i*4,insn[i],rs1[i],rs2[i],i?start+i*4+4+((signed int)((unsigned int)source[i]<<16)>>14):*ba);break;
7688 case SJUMP:
7689 printf (" %x: %s r%d,%8x\n",start+i*4,insn[i],rs1[i],start+i*4+4+((signed int)((unsigned int)source[i]<<16)>>14));break;
7690 case FJUMP:
7691 printf (" %x: %s %8x\n",start+i*4,insn[i],ba[i]);break;
7692 case RJUMP:
74426039 7693 if (opcode[i]==0x9&&rt1[i]!=31)
5067f341 7694 printf (" %x: %s r%d,r%d\n",start+i*4,insn[i],rt1[i],rs1[i]);
7695 else
7696 printf (" %x: %s r%d\n",start+i*4,insn[i],rs1[i]);
7697 break;
57871462 7698 case SPAN:
7699 printf (" %x: %s (pagespan) r%d,r%d,%8x\n",start+i*4,insn[i],rs1[i],rs2[i],ba[i]);break;
7700 case IMM16:
7701 if(opcode[i]==0xf) //LUI
7702 printf (" %x: %s r%d,%4x0000\n",start+i*4,insn[i],rt1[i],imm[i]&0xffff);
7703 else
7704 printf (" %x: %s r%d,r%d,%d\n",start+i*4,insn[i],rt1[i],rs1[i],imm[i]);
7705 break;
7706 case LOAD:
7707 case LOADLR:
7708 printf (" %x: %s r%d,r%d+%x\n",start+i*4,insn[i],rt1[i],rs1[i],imm[i]);
7709 break;
7710 case STORE:
7711 case STORELR:
7712 printf (" %x: %s r%d,r%d+%x\n",start+i*4,insn[i],rs2[i],rs1[i],imm[i]);
7713 break;
7714 case ALU:
7715 case SHIFT:
7716 printf (" %x: %s r%d,r%d,r%d\n",start+i*4,insn[i],rt1[i],rs1[i],rs2[i]);
7717 break;
7718 case MULTDIV:
7719 printf (" %x: %s r%d,r%d\n",start+i*4,insn[i],rs1[i],rs2[i]);
7720 break;
7721 case SHIFTIMM:
7722 printf (" %x: %s r%d,r%d,%d\n",start+i*4,insn[i],rt1[i],rs1[i],imm[i]);
7723 break;
7724 case MOV:
7725 if((opcode2[i]&0x1d)==0x10)
7726 printf (" %x: %s r%d\n",start+i*4,insn[i],rt1[i]);
7727 else if((opcode2[i]&0x1d)==0x11)
7728 printf (" %x: %s r%d\n",start+i*4,insn[i],rs1[i]);
7729 else
7730 printf (" %x: %s\n",start+i*4,insn[i]);
7731 break;
7732 case COP0:
7733 if(opcode2[i]==0)
7734 printf (" %x: %s r%d,cpr0[%d]\n",start+i*4,insn[i],rt1[i],(source[i]>>11)&0x1f); // MFC0
7735 else if(opcode2[i]==4)
7736 printf (" %x: %s r%d,cpr0[%d]\n",start+i*4,insn[i],rs1[i],(source[i]>>11)&0x1f); // MTC0
7737 else printf (" %x: %s\n",start+i*4,insn[i]);
7738 break;
7739 case COP1:
7740 if(opcode2[i]<3)
7741 printf (" %x: %s r%d,cpr1[%d]\n",start+i*4,insn[i],rt1[i],(source[i]>>11)&0x1f); // MFC1
7742 else if(opcode2[i]>3)
7743 printf (" %x: %s r%d,cpr1[%d]\n",start+i*4,insn[i],rs1[i],(source[i]>>11)&0x1f); // MTC1
7744 else printf (" %x: %s\n",start+i*4,insn[i]);
7745 break;
b9b61529 7746 case COP2:
7747 if(opcode2[i]<3)
7748 printf (" %x: %s r%d,cpr2[%d]\n",start+i*4,insn[i],rt1[i],(source[i]>>11)&0x1f); // MFC2
7749 else if(opcode2[i]>3)
7750 printf (" %x: %s r%d,cpr2[%d]\n",start+i*4,insn[i],rs1[i],(source[i]>>11)&0x1f); // MTC2
7751 else printf (" %x: %s\n",start+i*4,insn[i]);
7752 break;
57871462 7753 case C1LS:
7754 printf (" %x: %s cpr1[%d],r%d+%x\n",start+i*4,insn[i],(source[i]>>16)&0x1f,rs1[i],imm[i]);
7755 break;
b9b61529 7756 case C2LS:
7757 printf (" %x: %s cpr2[%d],r%d+%x\n",start+i*4,insn[i],(source[i]>>16)&0x1f,rs1[i],imm[i]);
7758 break;
1e973cb0 7759 case INTCALL:
7760 printf (" %x: %s (INTCALL)\n",start+i*4,insn[i]);
7761 break;
57871462 7762 default:
7763 //printf (" %s %8x\n",insn[i],source[i]);
7764 printf (" %x: %s\n",start+i*4,insn[i]);
7765 }
7766}
7767
dc990066 7768// clear the state completely, instead of just marking
7769// things invalid like invalidate_all_pages() does
7770void new_dynarec_clear_full()
57871462 7771{
57871462 7772 int n;
35775df7 7773 out=(u_char *)BASE_ADDR;
7774 memset(invalid_code,1,sizeof(invalid_code));
7775 memset(hash_table,0xff,sizeof(hash_table));
57871462 7776 memset(mini_ht,-1,sizeof(mini_ht));
7777 memset(restore_candidate,0,sizeof(restore_candidate));
dc990066 7778 memset(shadow,0,sizeof(shadow));
57871462 7779 copy=shadow;
7780 expirep=16384; // Expiry pointer, +2 blocks
7781 pending_exception=0;
7782 literalcount=0;
57871462 7783 stop_after_jal=0;
7784 // TLB
af4ee1fe 7785#ifndef DISABLE_TLB
57871462 7786 using_tlb=0;
af4ee1fe 7787#endif
dadf55f2 7788 sp_in_mirror=0;
57871462 7789 for(n=0;n<524288;n++) // 0 .. 0x7FFFFFFF
7790 memory_map[n]=-1;
7791 for(n=524288;n<526336;n++) // 0x80000000 .. 0x807FFFFF
7792 memory_map[n]=((u_int)rdram-0x80000000)>>2;
7793 for(n=526336;n<1048576;n++) // 0x80800000 .. 0xFFFFFFFF
7794 memory_map[n]=-1;
dc990066 7795 for(n=0;n<4096;n++) ll_clear(jump_in+n);
7796 for(n=0;n<4096;n++) ll_clear(jump_out+n);
7797 for(n=0;n<4096;n++) ll_clear(jump_dirty+n);
7798}
7799
7800void new_dynarec_init()
7801{
7802 printf("Init new dynarec\n");
7803 out=(u_char *)BASE_ADDR;
7804 if (mmap (out, 1<<TARGET_SIZE_2,
7805 PROT_READ | PROT_WRITE | PROT_EXEC,
7806 MAP_FIXED | MAP_PRIVATE | MAP_ANONYMOUS,
7807 -1, 0) <= 0) {printf("mmap() failed\n");}
7808#ifdef MUPEN64
7809 rdword=&readmem_dword;
7810 fake_pc.f.r.rs=&readmem_dword;
7811 fake_pc.f.r.rt=&readmem_dword;
7812 fake_pc.f.r.rd=&readmem_dword;
7813#endif
7814 int n;
7815 new_dynarec_clear_full();
7816#ifdef HOST_IMM8
7817 // Copy this into local area so we don't have to put it in every literal pool
7818 invc_ptr=invalid_code;
7819#endif
24385cae 7820#ifdef MUPEN64
57871462 7821 for(n=0;n<0x8000;n++) { // 0 .. 0x7FFFFFFF
7822 writemem[n] = write_nomem_new;
7823 writememb[n] = write_nomemb_new;
7824 writememh[n] = write_nomemh_new;
24385cae 7825#ifndef FORCE32
57871462 7826 writememd[n] = write_nomemd_new;
24385cae 7827#endif
57871462 7828 readmem[n] = read_nomem_new;
7829 readmemb[n] = read_nomemb_new;
7830 readmemh[n] = read_nomemh_new;
24385cae 7831#ifndef FORCE32
57871462 7832 readmemd[n] = read_nomemd_new;
24385cae 7833#endif
57871462 7834 }
7835 for(n=0x8000;n<0x8080;n++) { // 0x80000000 .. 0x807FFFFF
7836 writemem[n] = write_rdram_new;
7837 writememb[n] = write_rdramb_new;
7838 writememh[n] = write_rdramh_new;
24385cae 7839#ifndef FORCE32
57871462 7840 writememd[n] = write_rdramd_new;
24385cae 7841#endif
57871462 7842 }
7843 for(n=0xC000;n<0x10000;n++) { // 0xC0000000 .. 0xFFFFFFFF
7844 writemem[n] = write_nomem_new;
7845 writememb[n] = write_nomemb_new;
7846 writememh[n] = write_nomemh_new;
24385cae 7847#ifndef FORCE32
57871462 7848 writememd[n] = write_nomemd_new;
24385cae 7849#endif
57871462 7850 readmem[n] = read_nomem_new;
7851 readmemb[n] = read_nomemb_new;
7852 readmemh[n] = read_nomemh_new;
24385cae 7853#ifndef FORCE32
57871462 7854 readmemd[n] = read_nomemd_new;
24385cae 7855#endif
57871462 7856 }
24385cae 7857#endif
57871462 7858 tlb_hacks();
7859 arch_init();
7860}
7861
7862void new_dynarec_cleanup()
7863{
7864 int n;
7865 if (munmap ((void *)BASE_ADDR, 1<<TARGET_SIZE_2) < 0) {printf("munmap() failed\n");}
7866 for(n=0;n<4096;n++) ll_clear(jump_in+n);
7867 for(n=0;n<4096;n++) ll_clear(jump_out+n);
7868 for(n=0;n<4096;n++) ll_clear(jump_dirty+n);
7869 #ifdef ROM_COPY
7870 if (munmap (ROM_COPY, 67108864) < 0) {printf("munmap() failed\n");}
7871 #endif
7872}
7873
7874int new_recompile_block(int addr)
7875{
7876/*
7877 if(addr==0x800cd050) {
7878 int block;
7879 for(block=0x80000;block<0x80800;block++) invalidate_block(block);
7880 int n;
7881 for(n=0;n<=2048;n++) ll_clear(jump_dirty+n);
7882 }
7883*/
7884 //if(Count==365117028) tracedebug=1;
7885 assem_debug("NOTCOMPILED: addr = %x -> %x\n", (int)addr, (int)out);
7886 //printf("NOTCOMPILED: addr = %x -> %x\n", (int)addr, (int)out);
7887 //printf("TRACE: count=%d next=%d (compile %x)\n",Count,next_interupt,addr);
7888 //if(debug)
7889 //printf("TRACE: count=%d next=%d (checksum %x)\n",Count,next_interupt,mchecksum());
7890 //printf("fpu mapping=%x enabled=%x\n",(Status & 0x04000000)>>26,(Status & 0x20000000)>>29);
7891 /*if(Count>=312978186) {
7892 rlist();
7893 }*/
7894 //rlist();
7895 start = (u_int)addr&~3;
7896 //assert(((u_int)addr&1)==0);
7139f3c8 7897#ifdef PCSX
dadf55f2 7898 if(!sp_in_mirror&&(signed int)(psxRegs.GPR.n.sp&0xffe00000)>0x80200000&&
7899 0x10000<=psxRegs.GPR.n.sp&&(psxRegs.GPR.n.sp&~0xe0e00000)<RAM_SIZE) {
c2e3bd42 7900 printf("SP hack enabled (%08x), @%08x\n", psxRegs.GPR.n.sp, psxRegs.pc);
dadf55f2 7901 sp_in_mirror=1;
7902 }
9ad4d757 7903 if (Config.HLE && start == 0x80001000) // hlecall
560e4a12 7904 {
7139f3c8 7905 // XXX: is this enough? Maybe check hleSoftCall?
bb5285ef 7906 u_int beginning=(u_int)out;
7139f3c8 7907 u_int page=get_page(start);
7139f3c8 7908 invalid_code[start>>12]=0;
7909 emit_movimm(start,0);
7910 emit_writeword(0,(int)&pcaddr);
bb5285ef 7911 emit_jmp((int)new_dyna_leave);
7912#ifdef __arm__
7913 __clear_cache((void *)beginning,out);
7914#endif
9ad4d757 7915 ll_add(jump_in+page,start,(void *)beginning);
7139f3c8 7916 return 0;
7917 }
560e4a12 7918 else if ((u_int)addr < 0x00200000 ||
7919 (0xa0000000 <= addr && addr < 0xa0200000)) {
7139f3c8 7920 // used for BIOS calls mostly?
560e4a12 7921 source = (u_int *)((u_int)rdram+(start&0x1fffff));
7922 pagelimit = (addr&0xa0000000)|0x00200000;
7923 }
7924 else if (!Config.HLE && (
7925/* (0x9fc00000 <= addr && addr < 0x9fc80000) ||*/
7926 (0xbfc00000 <= addr && addr < 0xbfc80000))) {
7927 // BIOS
7928 source = (u_int *)((u_int)psxR+(start&0x7ffff));
7929 pagelimit = (addr&0xfff00000)|0x80000;
7139f3c8 7930 }
7931 else
7932#endif
3d624f89 7933#ifdef MUPEN64
57871462 7934 if ((int)addr >= 0xa4000000 && (int)addr < 0xa4001000) {
7935 source = (u_int *)((u_int)SP_DMEM+start-0xa4000000);
7936 pagelimit = 0xa4001000;
7937 }
3d624f89 7938 else
7939#endif
4cb76aa4 7940 if ((int)addr >= 0x80000000 && (int)addr < 0x80000000+RAM_SIZE) {
57871462 7941 source = (u_int *)((u_int)rdram+start-0x80000000);
4cb76aa4 7942 pagelimit = 0x80000000+RAM_SIZE;
57871462 7943 }
90ae6d4e 7944#ifndef DISABLE_TLB
57871462 7945 else if ((signed int)addr >= (signed int)0xC0000000) {
7946 //printf("addr=%x mm=%x\n",(u_int)addr,(memory_map[start>>12]<<2));
7947 //if(tlb_LUT_r[start>>12])
7948 //source = (u_int *)(((int)rdram)+(tlb_LUT_r[start>>12]&0xFFFFF000)+(((int)addr)&0xFFF)-0x80000000);
7949 if((signed int)memory_map[start>>12]>=0) {
7950 source = (u_int *)((u_int)(start+(memory_map[start>>12]<<2)));
7951 pagelimit=(start+4096)&0xFFFFF000;
7952 int map=memory_map[start>>12];
7953 int i;
7954 for(i=0;i<5;i++) {
7955 //printf("start: %x next: %x\n",map,memory_map[pagelimit>>12]);
7956 if((map&0xBFFFFFFF)==(memory_map[pagelimit>>12]&0xBFFFFFFF)) pagelimit+=4096;
7957 }
7958 assem_debug("pagelimit=%x\n",pagelimit);
7959 assem_debug("mapping=%x (%x)\n",memory_map[start>>12],(memory_map[start>>12]<<2)+start);
7960 }
7961 else {
7962 assem_debug("Compile at unmapped memory address: %x \n", (int)addr);
7963 //assem_debug("start: %x next: %x\n",memory_map[start>>12],memory_map[(start+4096)>>12]);
560e4a12 7964 return -1; // Caller will invoke exception handler
57871462 7965 }
7966 //printf("source= %x\n",(int)source);
7967 }
90ae6d4e 7968#endif
57871462 7969 else {
7970 printf("Compile at bogus memory address: %x \n", (int)addr);
7971 exit(1);
7972 }
7973
7974 /* Pass 1: disassemble */
7975 /* Pass 2: register dependencies, branch targets */
7976 /* Pass 3: register allocation */
7977 /* Pass 4: branch dependencies */
7978 /* Pass 5: pre-alloc */
7979 /* Pass 6: optimize clean/dirty state */
7980 /* Pass 7: flag 32-bit registers */
7981 /* Pass 8: assembly */
7982 /* Pass 9: linker */
7983 /* Pass 10: garbage collection / free memory */
7984
7985 int i,j;
7986 int done=0;
7987 unsigned int type,op,op2;
7988
7989 //printf("addr = %x source = %x %x\n", addr,source,source[0]);
7990
7991 /* Pass 1 disassembly */
7992
7993 for(i=0;!done;i++) {
e1190b87 7994 bt[i]=0;likely[i]=0;ooo[i]=0;op2=0;
7995 minimum_free_regs[i]=0;
57871462 7996 opcode[i]=op=source[i]>>26;
7997 switch(op)
7998 {
7999 case 0x00: strcpy(insn[i],"special"); type=NI;
8000 op2=source[i]&0x3f;
8001 switch(op2)
8002 {
8003 case 0x00: strcpy(insn[i],"SLL"); type=SHIFTIMM; break;
8004 case 0x02: strcpy(insn[i],"SRL"); type=SHIFTIMM; break;
8005 case 0x03: strcpy(insn[i],"SRA"); type=SHIFTIMM; break;
8006 case 0x04: strcpy(insn[i],"SLLV"); type=SHIFT; break;
8007 case 0x06: strcpy(insn[i],"SRLV"); type=SHIFT; break;
8008 case 0x07: strcpy(insn[i],"SRAV"); type=SHIFT; break;
8009 case 0x08: strcpy(insn[i],"JR"); type=RJUMP; break;
8010 case 0x09: strcpy(insn[i],"JALR"); type=RJUMP; break;
8011 case 0x0C: strcpy(insn[i],"SYSCALL"); type=SYSCALL; break;
8012 case 0x0D: strcpy(insn[i],"BREAK"); type=OTHER; break;
8013 case 0x0F: strcpy(insn[i],"SYNC"); type=OTHER; break;
8014 case 0x10: strcpy(insn[i],"MFHI"); type=MOV; break;
8015 case 0x11: strcpy(insn[i],"MTHI"); type=MOV; break;
8016 case 0x12: strcpy(insn[i],"MFLO"); type=MOV; break;
8017 case 0x13: strcpy(insn[i],"MTLO"); type=MOV; break;
57871462 8018 case 0x18: strcpy(insn[i],"MULT"); type=MULTDIV; break;
8019 case 0x19: strcpy(insn[i],"MULTU"); type=MULTDIV; break;
8020 case 0x1A: strcpy(insn[i],"DIV"); type=MULTDIV; break;
8021 case 0x1B: strcpy(insn[i],"DIVU"); type=MULTDIV; break;
57871462 8022 case 0x20: strcpy(insn[i],"ADD"); type=ALU; break;
8023 case 0x21: strcpy(insn[i],"ADDU"); type=ALU; break;
8024 case 0x22: strcpy(insn[i],"SUB"); type=ALU; break;
8025 case 0x23: strcpy(insn[i],"SUBU"); type=ALU; break;
8026 case 0x24: strcpy(insn[i],"AND"); type=ALU; break;
8027 case 0x25: strcpy(insn[i],"OR"); type=ALU; break;
8028 case 0x26: strcpy(insn[i],"XOR"); type=ALU; break;
8029 case 0x27: strcpy(insn[i],"NOR"); type=ALU; break;
8030 case 0x2A: strcpy(insn[i],"SLT"); type=ALU; break;
8031 case 0x2B: strcpy(insn[i],"SLTU"); type=ALU; break;
57871462 8032 case 0x30: strcpy(insn[i],"TGE"); type=NI; break;
8033 case 0x31: strcpy(insn[i],"TGEU"); type=NI; break;
8034 case 0x32: strcpy(insn[i],"TLT"); type=NI; break;
8035 case 0x33: strcpy(insn[i],"TLTU"); type=NI; break;
8036 case 0x34: strcpy(insn[i],"TEQ"); type=NI; break;
8037 case 0x36: strcpy(insn[i],"TNE"); type=NI; break;
7f2607ea 8038#ifndef FORCE32
8039 case 0x14: strcpy(insn[i],"DSLLV"); type=SHIFT; break;
8040 case 0x16: strcpy(insn[i],"DSRLV"); type=SHIFT; break;
8041 case 0x17: strcpy(insn[i],"DSRAV"); type=SHIFT; break;
8042 case 0x1C: strcpy(insn[i],"DMULT"); type=MULTDIV; break;
8043 case 0x1D: strcpy(insn[i],"DMULTU"); type=MULTDIV; break;
8044 case 0x1E: strcpy(insn[i],"DDIV"); type=MULTDIV; break;
8045 case 0x1F: strcpy(insn[i],"DDIVU"); type=MULTDIV; break;
8046 case 0x2C: strcpy(insn[i],"DADD"); type=ALU; break;
8047 case 0x2D: strcpy(insn[i],"DADDU"); type=ALU; break;
8048 case 0x2E: strcpy(insn[i],"DSUB"); type=ALU; break;
8049 case 0x2F: strcpy(insn[i],"DSUBU"); type=ALU; break;
57871462 8050 case 0x38: strcpy(insn[i],"DSLL"); type=SHIFTIMM; break;
8051 case 0x3A: strcpy(insn[i],"DSRL"); type=SHIFTIMM; break;
8052 case 0x3B: strcpy(insn[i],"DSRA"); type=SHIFTIMM; break;
8053 case 0x3C: strcpy(insn[i],"DSLL32"); type=SHIFTIMM; break;
8054 case 0x3E: strcpy(insn[i],"DSRL32"); type=SHIFTIMM; break;
8055 case 0x3F: strcpy(insn[i],"DSRA32"); type=SHIFTIMM; break;
7f2607ea 8056#endif
57871462 8057 }
8058 break;
8059 case 0x01: strcpy(insn[i],"regimm"); type=NI;
8060 op2=(source[i]>>16)&0x1f;
8061 switch(op2)
8062 {
8063 case 0x00: strcpy(insn[i],"BLTZ"); type=SJUMP; break;
8064 case 0x01: strcpy(insn[i],"BGEZ"); type=SJUMP; break;
8065 case 0x02: strcpy(insn[i],"BLTZL"); type=SJUMP; break;
8066 case 0x03: strcpy(insn[i],"BGEZL"); type=SJUMP; break;
8067 case 0x08: strcpy(insn[i],"TGEI"); type=NI; break;
8068 case 0x09: strcpy(insn[i],"TGEIU"); type=NI; break;
8069 case 0x0A: strcpy(insn[i],"TLTI"); type=NI; break;
8070 case 0x0B: strcpy(insn[i],"TLTIU"); type=NI; break;
8071 case 0x0C: strcpy(insn[i],"TEQI"); type=NI; break;
8072 case 0x0E: strcpy(insn[i],"TNEI"); type=NI; break;
8073 case 0x10: strcpy(insn[i],"BLTZAL"); type=SJUMP; break;
8074 case 0x11: strcpy(insn[i],"BGEZAL"); type=SJUMP; break;
8075 case 0x12: strcpy(insn[i],"BLTZALL"); type=SJUMP; break;
8076 case 0x13: strcpy(insn[i],"BGEZALL"); type=SJUMP; break;
8077 }
8078 break;
8079 case 0x02: strcpy(insn[i],"J"); type=UJUMP; break;
8080 case 0x03: strcpy(insn[i],"JAL"); type=UJUMP; break;
8081 case 0x04: strcpy(insn[i],"BEQ"); type=CJUMP; break;
8082 case 0x05: strcpy(insn[i],"BNE"); type=CJUMP; break;
8083 case 0x06: strcpy(insn[i],"BLEZ"); type=CJUMP; break;
8084 case 0x07: strcpy(insn[i],"BGTZ"); type=CJUMP; break;
8085 case 0x08: strcpy(insn[i],"ADDI"); type=IMM16; break;
8086 case 0x09: strcpy(insn[i],"ADDIU"); type=IMM16; break;
8087 case 0x0A: strcpy(insn[i],"SLTI"); type=IMM16; break;
8088 case 0x0B: strcpy(insn[i],"SLTIU"); type=IMM16; break;
8089 case 0x0C: strcpy(insn[i],"ANDI"); type=IMM16; break;
8090 case 0x0D: strcpy(insn[i],"ORI"); type=IMM16; break;
8091 case 0x0E: strcpy(insn[i],"XORI"); type=IMM16; break;
8092 case 0x0F: strcpy(insn[i],"LUI"); type=IMM16; break;
8093 case 0x10: strcpy(insn[i],"cop0"); type=NI;
8094 op2=(source[i]>>21)&0x1f;
8095 switch(op2)
8096 {
8097 case 0x00: strcpy(insn[i],"MFC0"); type=COP0; break;
8098 case 0x04: strcpy(insn[i],"MTC0"); type=COP0; break;
8099 case 0x10: strcpy(insn[i],"tlb"); type=NI;
8100 switch(source[i]&0x3f)
8101 {
8102 case 0x01: strcpy(insn[i],"TLBR"); type=COP0; break;
8103 case 0x02: strcpy(insn[i],"TLBWI"); type=COP0; break;
8104 case 0x06: strcpy(insn[i],"TLBWR"); type=COP0; break;
8105 case 0x08: strcpy(insn[i],"TLBP"); type=COP0; break;
576bbd8f 8106#ifdef PCSX
8107 case 0x10: strcpy(insn[i],"RFE"); type=COP0; break;
8108#else
57871462 8109 case 0x18: strcpy(insn[i],"ERET"); type=COP0; break;
576bbd8f 8110#endif
57871462 8111 }
8112 }
8113 break;
8114 case 0x11: strcpy(insn[i],"cop1"); type=NI;
8115 op2=(source[i]>>21)&0x1f;
8116 switch(op2)
8117 {
8118 case 0x00: strcpy(insn[i],"MFC1"); type=COP1; break;
8119 case 0x01: strcpy(insn[i],"DMFC1"); type=COP1; break;
8120 case 0x02: strcpy(insn[i],"CFC1"); type=COP1; break;
8121 case 0x04: strcpy(insn[i],"MTC1"); type=COP1; break;
8122 case 0x05: strcpy(insn[i],"DMTC1"); type=COP1; break;
8123 case 0x06: strcpy(insn[i],"CTC1"); type=COP1; break;
8124 case 0x08: strcpy(insn[i],"BC1"); type=FJUMP;
8125 switch((source[i]>>16)&0x3)
8126 {
8127 case 0x00: strcpy(insn[i],"BC1F"); break;
8128 case 0x01: strcpy(insn[i],"BC1T"); break;
8129 case 0x02: strcpy(insn[i],"BC1FL"); break;
8130 case 0x03: strcpy(insn[i],"BC1TL"); break;
8131 }
8132 break;
8133 case 0x10: strcpy(insn[i],"C1.S"); type=NI;
8134 switch(source[i]&0x3f)
8135 {
8136 case 0x00: strcpy(insn[i],"ADD.S"); type=FLOAT; break;
8137 case 0x01: strcpy(insn[i],"SUB.S"); type=FLOAT; break;
8138 case 0x02: strcpy(insn[i],"MUL.S"); type=FLOAT; break;
8139 case 0x03: strcpy(insn[i],"DIV.S"); type=FLOAT; break;
8140 case 0x04: strcpy(insn[i],"SQRT.S"); type=FLOAT; break;
8141 case 0x05: strcpy(insn[i],"ABS.S"); type=FLOAT; break;
8142 case 0x06: strcpy(insn[i],"MOV.S"); type=FLOAT; break;
8143 case 0x07: strcpy(insn[i],"NEG.S"); type=FLOAT; break;
8144 case 0x08: strcpy(insn[i],"ROUND.L.S"); type=FCONV; break;
8145 case 0x09: strcpy(insn[i],"TRUNC.L.S"); type=FCONV; break;
8146 case 0x0A: strcpy(insn[i],"CEIL.L.S"); type=FCONV; break;
8147 case 0x0B: strcpy(insn[i],"FLOOR.L.S"); type=FCONV; break;
8148 case 0x0C: strcpy(insn[i],"ROUND.W.S"); type=FCONV; break;
8149 case 0x0D: strcpy(insn[i],"TRUNC.W.S"); type=FCONV; break;
8150 case 0x0E: strcpy(insn[i],"CEIL.W.S"); type=FCONV; break;
8151 case 0x0F: strcpy(insn[i],"FLOOR.W.S"); type=FCONV; break;
8152 case 0x21: strcpy(insn[i],"CVT.D.S"); type=FCONV; break;
8153 case 0x24: strcpy(insn[i],"CVT.W.S"); type=FCONV; break;
8154 case 0x25: strcpy(insn[i],"CVT.L.S"); type=FCONV; break;
8155 case 0x30: strcpy(insn[i],"C.F.S"); type=FCOMP; break;
8156 case 0x31: strcpy(insn[i],"C.UN.S"); type=FCOMP; break;
8157 case 0x32: strcpy(insn[i],"C.EQ.S"); type=FCOMP; break;
8158 case 0x33: strcpy(insn[i],"C.UEQ.S"); type=FCOMP; break;
8159 case 0x34: strcpy(insn[i],"C.OLT.S"); type=FCOMP; break;
8160 case 0x35: strcpy(insn[i],"C.ULT.S"); type=FCOMP; break;
8161 case 0x36: strcpy(insn[i],"C.OLE.S"); type=FCOMP; break;
8162 case 0x37: strcpy(insn[i],"C.ULE.S"); type=FCOMP; break;
8163 case 0x38: strcpy(insn[i],"C.SF.S"); type=FCOMP; break;
8164 case 0x39: strcpy(insn[i],"C.NGLE.S"); type=FCOMP; break;
8165 case 0x3A: strcpy(insn[i],"C.SEQ.S"); type=FCOMP; break;
8166 case 0x3B: strcpy(insn[i],"C.NGL.S"); type=FCOMP; break;
8167 case 0x3C: strcpy(insn[i],"C.LT.S"); type=FCOMP; break;
8168 case 0x3D: strcpy(insn[i],"C.NGE.S"); type=FCOMP; break;
8169 case 0x3E: strcpy(insn[i],"C.LE.S"); type=FCOMP; break;
8170 case 0x3F: strcpy(insn[i],"C.NGT.S"); type=FCOMP; break;
8171 }
8172 break;
8173 case 0x11: strcpy(insn[i],"C1.D"); type=NI;
8174 switch(source[i]&0x3f)
8175 {
8176 case 0x00: strcpy(insn[i],"ADD.D"); type=FLOAT; break;
8177 case 0x01: strcpy(insn[i],"SUB.D"); type=FLOAT; break;
8178 case 0x02: strcpy(insn[i],"MUL.D"); type=FLOAT; break;
8179 case 0x03: strcpy(insn[i],"DIV.D"); type=FLOAT; break;
8180 case 0x04: strcpy(insn[i],"SQRT.D"); type=FLOAT; break;
8181 case 0x05: strcpy(insn[i],"ABS.D"); type=FLOAT; break;
8182 case 0x06: strcpy(insn[i],"MOV.D"); type=FLOAT; break;
8183 case 0x07: strcpy(insn[i],"NEG.D"); type=FLOAT; break;
8184 case 0x08: strcpy(insn[i],"ROUND.L.D"); type=FCONV; break;
8185 case 0x09: strcpy(insn[i],"TRUNC.L.D"); type=FCONV; break;
8186 case 0x0A: strcpy(insn[i],"CEIL.L.D"); type=FCONV; break;
8187 case 0x0B: strcpy(insn[i],"FLOOR.L.D"); type=FCONV; break;
8188 case 0x0C: strcpy(insn[i],"ROUND.W.D"); type=FCONV; break;
8189 case 0x0D: strcpy(insn[i],"TRUNC.W.D"); type=FCONV; break;
8190 case 0x0E: strcpy(insn[i],"CEIL.W.D"); type=FCONV; break;
8191 case 0x0F: strcpy(insn[i],"FLOOR.W.D"); type=FCONV; break;
8192 case 0x20: strcpy(insn[i],"CVT.S.D"); type=FCONV; break;
8193 case 0x24: strcpy(insn[i],"CVT.W.D"); type=FCONV; break;
8194 case 0x25: strcpy(insn[i],"CVT.L.D"); type=FCONV; break;
8195 case 0x30: strcpy(insn[i],"C.F.D"); type=FCOMP; break;
8196 case 0x31: strcpy(insn[i],"C.UN.D"); type=FCOMP; break;
8197 case 0x32: strcpy(insn[i],"C.EQ.D"); type=FCOMP; break;
8198 case 0x33: strcpy(insn[i],"C.UEQ.D"); type=FCOMP; break;
8199 case 0x34: strcpy(insn[i],"C.OLT.D"); type=FCOMP; break;
8200 case 0x35: strcpy(insn[i],"C.ULT.D"); type=FCOMP; break;
8201 case 0x36: strcpy(insn[i],"C.OLE.D"); type=FCOMP; break;
8202 case 0x37: strcpy(insn[i],"C.ULE.D"); type=FCOMP; break;
8203 case 0x38: strcpy(insn[i],"C.SF.D"); type=FCOMP; break;
8204 case 0x39: strcpy(insn[i],"C.NGLE.D"); type=FCOMP; break;
8205 case 0x3A: strcpy(insn[i],"C.SEQ.D"); type=FCOMP; break;
8206 case 0x3B: strcpy(insn[i],"C.NGL.D"); type=FCOMP; break;
8207 case 0x3C: strcpy(insn[i],"C.LT.D"); type=FCOMP; break;
8208 case 0x3D: strcpy(insn[i],"C.NGE.D"); type=FCOMP; break;
8209 case 0x3E: strcpy(insn[i],"C.LE.D"); type=FCOMP; break;
8210 case 0x3F: strcpy(insn[i],"C.NGT.D"); type=FCOMP; break;
8211 }
8212 break;
8213 case 0x14: strcpy(insn[i],"C1.W"); type=NI;
8214 switch(source[i]&0x3f)
8215 {
8216 case 0x20: strcpy(insn[i],"CVT.S.W"); type=FCONV; break;
8217 case 0x21: strcpy(insn[i],"CVT.D.W"); type=FCONV; break;
8218 }
8219 break;
8220 case 0x15: strcpy(insn[i],"C1.L"); type=NI;
8221 switch(source[i]&0x3f)
8222 {
8223 case 0x20: strcpy(insn[i],"CVT.S.L"); type=FCONV; break;
8224 case 0x21: strcpy(insn[i],"CVT.D.L"); type=FCONV; break;
8225 }
8226 break;
8227 }
8228 break;
909168d6 8229#ifndef FORCE32
57871462 8230 case 0x14: strcpy(insn[i],"BEQL"); type=CJUMP; break;
8231 case 0x15: strcpy(insn[i],"BNEL"); type=CJUMP; break;
8232 case 0x16: strcpy(insn[i],"BLEZL"); type=CJUMP; break;
8233 case 0x17: strcpy(insn[i],"BGTZL"); type=CJUMP; break;
8234 case 0x18: strcpy(insn[i],"DADDI"); type=IMM16; break;
8235 case 0x19: strcpy(insn[i],"DADDIU"); type=IMM16; break;
8236 case 0x1A: strcpy(insn[i],"LDL"); type=LOADLR; break;
8237 case 0x1B: strcpy(insn[i],"LDR"); type=LOADLR; break;
996cc15d 8238#endif
57871462 8239 case 0x20: strcpy(insn[i],"LB"); type=LOAD; break;
8240 case 0x21: strcpy(insn[i],"LH"); type=LOAD; break;
8241 case 0x22: strcpy(insn[i],"LWL"); type=LOADLR; break;
8242 case 0x23: strcpy(insn[i],"LW"); type=LOAD; break;
8243 case 0x24: strcpy(insn[i],"LBU"); type=LOAD; break;
8244 case 0x25: strcpy(insn[i],"LHU"); type=LOAD; break;
8245 case 0x26: strcpy(insn[i],"LWR"); type=LOADLR; break;
8246 case 0x27: strcpy(insn[i],"LWU"); type=LOAD; break;
8247 case 0x28: strcpy(insn[i],"SB"); type=STORE; break;
8248 case 0x29: strcpy(insn[i],"SH"); type=STORE; break;
8249 case 0x2A: strcpy(insn[i],"SWL"); type=STORELR; break;
8250 case 0x2B: strcpy(insn[i],"SW"); type=STORE; break;
996cc15d 8251#ifndef FORCE32
57871462 8252 case 0x2C: strcpy(insn[i],"SDL"); type=STORELR; break;
8253 case 0x2D: strcpy(insn[i],"SDR"); type=STORELR; break;
996cc15d 8254#endif
57871462 8255 case 0x2E: strcpy(insn[i],"SWR"); type=STORELR; break;
8256 case 0x2F: strcpy(insn[i],"CACHE"); type=NOP; break;
8257 case 0x30: strcpy(insn[i],"LL"); type=NI; break;
8258 case 0x31: strcpy(insn[i],"LWC1"); type=C1LS; break;
996cc15d 8259#ifndef FORCE32
57871462 8260 case 0x34: strcpy(insn[i],"LLD"); type=NI; break;
8261 case 0x35: strcpy(insn[i],"LDC1"); type=C1LS; break;
8262 case 0x37: strcpy(insn[i],"LD"); type=LOAD; break;
996cc15d 8263#endif
57871462 8264 case 0x38: strcpy(insn[i],"SC"); type=NI; break;
8265 case 0x39: strcpy(insn[i],"SWC1"); type=C1LS; break;
996cc15d 8266#ifndef FORCE32
57871462 8267 case 0x3C: strcpy(insn[i],"SCD"); type=NI; break;
8268 case 0x3D: strcpy(insn[i],"SDC1"); type=C1LS; break;
8269 case 0x3F: strcpy(insn[i],"SD"); type=STORE; break;
996cc15d 8270#endif
b9b61529 8271#ifdef PCSX
8272 case 0x12: strcpy(insn[i],"COP2"); type=NI;
c7abc864 8273 // note: COP MIPS-1 encoding differs from MIPS32
b9b61529 8274 op2=(source[i]>>21)&0x1f;
c7abc864 8275 if (source[i]&0x3f) {
8276 if (gte_handlers[source[i]&0x3f]!=NULL) {
8277 snprintf(insn[i], sizeof(insn[i]), "COP2 %x", source[i]&0x3f);
8278 type=C2OP;
8279 }
8280 }
8281 else switch(op2)
b9b61529 8282 {
8283 case 0x00: strcpy(insn[i],"MFC2"); type=COP2; break;
8284 case 0x02: strcpy(insn[i],"CFC2"); type=COP2; break;
8285 case 0x04: strcpy(insn[i],"MTC2"); type=COP2; break;
8286 case 0x06: strcpy(insn[i],"CTC2"); type=COP2; break;
b9b61529 8287 }
8288 break;
8289 case 0x32: strcpy(insn[i],"LWC2"); type=C2LS; break;
8290 case 0x3A: strcpy(insn[i],"SWC2"); type=C2LS; break;
8291 case 0x3B: strcpy(insn[i],"HLECALL"); type=HLECALL; break;
8292#endif
90ae6d4e 8293 default: strcpy(insn[i],"???"); type=NI;
75dec299 8294 printf("NI %08x @%08x (%08x)\n", source[i], addr + i*4, addr);
90ae6d4e 8295 break;
57871462 8296 }
8297 itype[i]=type;
8298 opcode2[i]=op2;
8299 /* Get registers/immediates */
8300 lt1[i]=0;
8301 us1[i]=0;
8302 us2[i]=0;
8303 dep1[i]=0;
8304 dep2[i]=0;
8305 switch(type) {
8306 case LOAD:
8307 rs1[i]=(source[i]>>21)&0x1f;
8308 rs2[i]=0;
8309 rt1[i]=(source[i]>>16)&0x1f;
8310 rt2[i]=0;
8311 imm[i]=(short)source[i];
8312 break;
8313 case STORE:
8314 case STORELR:
8315 rs1[i]=(source[i]>>21)&0x1f;
8316 rs2[i]=(source[i]>>16)&0x1f;
8317 rt1[i]=0;
8318 rt2[i]=0;
8319 imm[i]=(short)source[i];
8320 if(op==0x2c||op==0x2d||op==0x3f) us1[i]=rs2[i]; // 64-bit SDL/SDR/SD
8321 break;
8322 case LOADLR:
8323 // LWL/LWR only load part of the register,
8324 // therefore the target register must be treated as a source too
8325 rs1[i]=(source[i]>>21)&0x1f;
8326 rs2[i]=(source[i]>>16)&0x1f;
8327 rt1[i]=(source[i]>>16)&0x1f;
8328 rt2[i]=0;
8329 imm[i]=(short)source[i];
8330 if(op==0x1a||op==0x1b) us1[i]=rs2[i]; // LDR/LDL
8331 if(op==0x26) dep1[i]=rt1[i]; // LWR
8332 break;
8333 case IMM16:
8334 if (op==0x0f) rs1[i]=0; // LUI instruction has no source register
8335 else rs1[i]=(source[i]>>21)&0x1f;
8336 rs2[i]=0;
8337 rt1[i]=(source[i]>>16)&0x1f;
8338 rt2[i]=0;
8339 if(op>=0x0c&&op<=0x0e) { // ANDI/ORI/XORI
8340 imm[i]=(unsigned short)source[i];
8341 }else{
8342 imm[i]=(short)source[i];
8343 }
8344 if(op==0x18||op==0x19) us1[i]=rs1[i]; // DADDI/DADDIU
8345 if(op==0x0a||op==0x0b) us1[i]=rs1[i]; // SLTI/SLTIU
8346 if(op==0x0d||op==0x0e) dep1[i]=rs1[i]; // ORI/XORI
8347 break;
8348 case UJUMP:
8349 rs1[i]=0;
8350 rs2[i]=0;
8351 rt1[i]=0;
8352 rt2[i]=0;
8353 // The JAL instruction writes to r31.
8354 if (op&1) {
8355 rt1[i]=31;
8356 }
8357 rs2[i]=CCREG;
8358 break;
8359 case RJUMP:
8360 rs1[i]=(source[i]>>21)&0x1f;
8361 rs2[i]=0;
8362 rt1[i]=0;
8363 rt2[i]=0;
5067f341 8364 // The JALR instruction writes to rd.
57871462 8365 if (op2&1) {
5067f341 8366 rt1[i]=(source[i]>>11)&0x1f;
57871462 8367 }
8368 rs2[i]=CCREG;
8369 break;
8370 case CJUMP:
8371 rs1[i]=(source[i]>>21)&0x1f;
8372 rs2[i]=(source[i]>>16)&0x1f;
8373 rt1[i]=0;
8374 rt2[i]=0;
8375 if(op&2) { // BGTZ/BLEZ
8376 rs2[i]=0;
8377 }
8378 us1[i]=rs1[i];
8379 us2[i]=rs2[i];
8380 likely[i]=op>>4;
8381 break;
8382 case SJUMP:
8383 rs1[i]=(source[i]>>21)&0x1f;
8384 rs2[i]=CCREG;
8385 rt1[i]=0;
8386 rt2[i]=0;
8387 us1[i]=rs1[i];
8388 if(op2&0x10) { // BxxAL
8389 rt1[i]=31;
8390 // NOTE: If the branch is not taken, r31 is still overwritten
8391 }
8392 likely[i]=(op2&2)>>1;
8393 break;
8394 case FJUMP:
8395 rs1[i]=FSREG;
8396 rs2[i]=CSREG;
8397 rt1[i]=0;
8398 rt2[i]=0;
8399 likely[i]=((source[i])>>17)&1;
8400 break;
8401 case ALU:
8402 rs1[i]=(source[i]>>21)&0x1f; // source
8403 rs2[i]=(source[i]>>16)&0x1f; // subtract amount
8404 rt1[i]=(source[i]>>11)&0x1f; // destination
8405 rt2[i]=0;
8406 if(op2==0x2a||op2==0x2b) { // SLT/SLTU
8407 us1[i]=rs1[i];us2[i]=rs2[i];
8408 }
8409 else if(op2>=0x24&&op2<=0x27) { // AND/OR/XOR/NOR
8410 dep1[i]=rs1[i];dep2[i]=rs2[i];
8411 }
8412 else if(op2>=0x2c&&op2<=0x2f) { // DADD/DSUB
8413 dep1[i]=rs1[i];dep2[i]=rs2[i];
8414 }
8415 break;
8416 case MULTDIV:
8417 rs1[i]=(source[i]>>21)&0x1f; // source
8418 rs2[i]=(source[i]>>16)&0x1f; // divisor
8419 rt1[i]=HIREG;
8420 rt2[i]=LOREG;
8421 if (op2>=0x1c&&op2<=0x1f) { // DMULT/DMULTU/DDIV/DDIVU
8422 us1[i]=rs1[i];us2[i]=rs2[i];
8423 }
8424 break;
8425 case MOV:
8426 rs1[i]=0;
8427 rs2[i]=0;
8428 rt1[i]=0;
8429 rt2[i]=0;
8430 if(op2==0x10) rs1[i]=HIREG; // MFHI
8431 if(op2==0x11) rt1[i]=HIREG; // MTHI
8432 if(op2==0x12) rs1[i]=LOREG; // MFLO
8433 if(op2==0x13) rt1[i]=LOREG; // MTLO
8434 if((op2&0x1d)==0x10) rt1[i]=(source[i]>>11)&0x1f; // MFxx
8435 if((op2&0x1d)==0x11) rs1[i]=(source[i]>>21)&0x1f; // MTxx
8436 dep1[i]=rs1[i];
8437 break;
8438 case SHIFT:
8439 rs1[i]=(source[i]>>16)&0x1f; // target of shift
8440 rs2[i]=(source[i]>>21)&0x1f; // shift amount
8441 rt1[i]=(source[i]>>11)&0x1f; // destination
8442 rt2[i]=0;
8443 // DSLLV/DSRLV/DSRAV are 64-bit
8444 if(op2>=0x14&&op2<=0x17) us1[i]=rs1[i];
8445 break;
8446 case SHIFTIMM:
8447 rs1[i]=(source[i]>>16)&0x1f;
8448 rs2[i]=0;
8449 rt1[i]=(source[i]>>11)&0x1f;
8450 rt2[i]=0;
8451 imm[i]=(source[i]>>6)&0x1f;
8452 // DSxx32 instructions
8453 if(op2>=0x3c) imm[i]|=0x20;
8454 // DSLL/DSRL/DSRA/DSRA32/DSRL32 but not DSLL32 require 64-bit source
8455 if(op2>=0x38&&op2!=0x3c) us1[i]=rs1[i];
8456 break;
8457 case COP0:
8458 rs1[i]=0;
8459 rs2[i]=0;
8460 rt1[i]=0;
8461 rt2[i]=0;
8462 if(op2==0) rt1[i]=(source[i]>>16)&0x1F; // MFC0
8463 if(op2==4) rs1[i]=(source[i]>>16)&0x1F; // MTC0
8464 if(op2==4&&((source[i]>>11)&0x1f)==12) rt2[i]=CSREG; // Status
8465 if(op2==16) if((source[i]&0x3f)==0x18) rs2[i]=CCREG; // ERET
8466 break;
8467 case COP1:
b9b61529 8468 case COP2:
57871462 8469 rs1[i]=0;
8470 rs2[i]=0;
8471 rt1[i]=0;
8472 rt2[i]=0;
8473 if(op2<3) rt1[i]=(source[i]>>16)&0x1F; // MFC1/DMFC1/CFC1
8474 if(op2>3) rs1[i]=(source[i]>>16)&0x1F; // MTC1/DMTC1/CTC1
8475 if(op2==5) us1[i]=rs1[i]; // DMTC1
8476 rs2[i]=CSREG;
8477 break;
8478 case C1LS:
8479 rs1[i]=(source[i]>>21)&0x1F;
8480 rs2[i]=CSREG;
8481 rt1[i]=0;
8482 rt2[i]=0;
8483 imm[i]=(short)source[i];
8484 break;
b9b61529 8485 case C2LS:
8486 rs1[i]=(source[i]>>21)&0x1F;
8487 rs2[i]=0;
8488 rt1[i]=0;
8489 rt2[i]=0;
8490 imm[i]=(short)source[i];
8491 break;
57871462 8492 case FLOAT:
8493 case FCONV:
8494 rs1[i]=0;
8495 rs2[i]=CSREG;
8496 rt1[i]=0;
8497 rt2[i]=0;
8498 break;
8499 case FCOMP:
8500 rs1[i]=FSREG;
8501 rs2[i]=CSREG;
8502 rt1[i]=FSREG;
8503 rt2[i]=0;
8504 break;
8505 case SYSCALL:
7139f3c8 8506 case HLECALL:
1e973cb0 8507 case INTCALL:
57871462 8508 rs1[i]=CCREG;
8509 rs2[i]=0;
8510 rt1[i]=0;
8511 rt2[i]=0;
8512 break;
8513 default:
8514 rs1[i]=0;
8515 rs2[i]=0;
8516 rt1[i]=0;
8517 rt2[i]=0;
8518 }
8519 /* Calculate branch target addresses */
8520 if(type==UJUMP)
8521 ba[i]=((start+i*4+4)&0xF0000000)|(((unsigned int)source[i]<<6)>>4);
8522 else if(type==CJUMP&&rs1[i]==rs2[i]&&(op&1))
8523 ba[i]=start+i*4+8; // Ignore never taken branch
8524 else if(type==SJUMP&&rs1[i]==0&&!(op2&1))
8525 ba[i]=start+i*4+8; // Ignore never taken branch
8526 else if(type==CJUMP||type==SJUMP||type==FJUMP)
8527 ba[i]=start+i*4+4+((signed int)((unsigned int)source[i]<<16)>>14);
8528 else ba[i]=-1;
26869094 8529#ifdef PCSX
3e535354 8530 if(i>0&&(itype[i-1]==RJUMP||itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP)) {
8531 int do_in_intrp=0;
8532 // branch in delay slot?
8533 if(type==RJUMP||type==UJUMP||type==CJUMP||type==SJUMP||type==FJUMP) {
8534 // don't handle first branch and call interpreter if it's hit
8535 printf("branch in delay slot @%08x (%08x)\n", addr + i*4, addr);
8536 do_in_intrp=1;
8537 }
8538 // basic load delay detection
8539 else if((type==LOAD||type==LOADLR||type==COP0||type==COP2||type==C2LS)&&rt1[i]!=0) {
8540 int t=(ba[i-1]-start)/4;
8541 if(0 <= t && t < i &&(rt1[i]==rs1[t]||rt1[i]==rs2[t])&&itype[t]!=CJUMP&&itype[t]!=SJUMP) {
8542 // jump target wants DS result - potential load delay effect
8543 printf("load delay @%08x (%08x)\n", addr + i*4, addr);
8544 do_in_intrp=1;
8545 bt[t+1]=1; // expected return from interpreter
8546 }
8547 else if(i>=2&&rt1[i-2]==2&&rt1[i]==2&&rs1[i]!=2&&rs2[i]!=2&&rs1[i-1]!=2&&rs2[i-1]!=2&&
8548 !(i>=3&&(itype[i-3]==RJUMP||itype[i-3]==UJUMP||itype[i-3]==CJUMP||itype[i-3]==SJUMP))) {
8549 // v0 overwrite like this is a sign of trouble, bail out
8550 printf("v0 overwrite @%08x (%08x)\n", addr + i*4, addr);
8551 do_in_intrp=1;
8552 }
8553 }
3e535354 8554 if(do_in_intrp) {
8555 rs1[i-1]=CCREG;
8556 rs2[i-1]=rt1[i-1]=rt2[i-1]=0;
26869094 8557 ba[i-1]=-1;
8558 itype[i-1]=INTCALL;
8559 done=2;
3e535354 8560 i--; // don't compile the DS
26869094 8561 }
3e535354 8562 }
26869094 8563#endif
3e535354 8564 /* Is this the end of the block? */
8565 if(i>0&&(itype[i-1]==UJUMP||itype[i-1]==RJUMP||(source[i-1]>>16)==0x1000)) {
5067f341 8566 if(rt1[i-1]==0) { // Continue past subroutine call (JAL)
1e973cb0 8567 done=2;
57871462 8568 }
8569 else {
8570 if(stop_after_jal) done=1;
8571 // Stop on BREAK
8572 if((source[i+1]&0xfc00003f)==0x0d) done=1;
8573 }
8574 // Don't recompile stuff that's already compiled
8575 if(check_addr(start+i*4+4)) done=1;
8576 // Don't get too close to the limit
8577 if(i>MAXBLOCK/2) done=1;
8578 }
75dec299 8579 if(itype[i]==SYSCALL&&stop_after_jal) done=1;
1e973cb0 8580 if(itype[i]==HLECALL||itype[i]==INTCALL) done=2;
8581 if(done==2) {
8582 // Does the block continue due to a branch?
8583 for(j=i-1;j>=0;j--)
8584 {
2a706964 8585 if(ba[j]==start+i*4) done=j=0; // Branch into delay slot
1e973cb0 8586 if(ba[j]==start+i*4+4) done=j=0;
8587 if(ba[j]==start+i*4+8) done=j=0;
8588 }
8589 }
75dec299 8590 //assert(i<MAXBLOCK-1);
57871462 8591 if(start+i*4==pagelimit-4) done=1;
8592 assert(start+i*4<pagelimit);
8593 if (i==MAXBLOCK-1) done=1;
8594 // Stop if we're compiling junk
8595 if(itype[i]==NI&&opcode[i]==0x11) {
8596 done=stop_after_jal=1;
8597 printf("Disabled speculative precompilation\n");
8598 }
8599 }
8600 slen=i;
8601 if(itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==RJUMP||itype[i-1]==FJUMP) {
8602 if(start+i*4==pagelimit) {
8603 itype[i-1]=SPAN;
8604 }
8605 }
8606 assert(slen>0);
8607
8608 /* Pass 2 - Register dependencies and branch targets */
8609
8610 unneeded_registers(0,slen-1,0);
8611
8612 /* Pass 3 - Register allocation */
8613
8614 struct regstat current; // Current register allocations/status
8615 current.is32=1;
8616 current.dirty=0;
8617 current.u=unneeded_reg[0];
8618 current.uu=unneeded_reg_upper[0];
8619 clear_all_regs(current.regmap);
8620 alloc_reg(&current,0,CCREG);
8621 dirty_reg(&current,CCREG);
8622 current.isconst=0;
8623 current.wasconst=0;
8624 int ds=0;
8625 int cc=0;
5194fb95 8626 int hr=-1;
6ebf4adf 8627
8628#ifndef FORCE32
57871462 8629 provisional_32bit();
6ebf4adf 8630#endif
57871462 8631 if((u_int)addr&1) {
8632 // First instruction is delay slot
8633 cc=-1;
8634 bt[1]=1;
8635 ds=1;
8636 unneeded_reg[0]=1;
8637 unneeded_reg_upper[0]=1;
8638 current.regmap[HOST_BTREG]=BTREG;
8639 }
8640
8641 for(i=0;i<slen;i++)
8642 {
8643 if(bt[i])
8644 {
8645 int hr;
8646 for(hr=0;hr<HOST_REGS;hr++)
8647 {
8648 // Is this really necessary?
8649 if(current.regmap[hr]==0) current.regmap[hr]=-1;
8650 }
8651 current.isconst=0;
8652 }
8653 if(i>1)
8654 {
8655 if((opcode[i-2]&0x2f)==0x05) // BNE/BNEL
8656 {
8657 if(rs1[i-2]==0||rs2[i-2]==0)
8658 {
8659 if(rs1[i-2]) {
8660 current.is32|=1LL<<rs1[i-2];
8661 int hr=get_reg(current.regmap,rs1[i-2]|64);
8662 if(hr>=0) current.regmap[hr]=-1;
8663 }
8664 if(rs2[i-2]) {
8665 current.is32|=1LL<<rs2[i-2];
8666 int hr=get_reg(current.regmap,rs2[i-2]|64);
8667 if(hr>=0) current.regmap[hr]=-1;
8668 }
8669 }
8670 }
8671 }
6ebf4adf 8672#ifndef FORCE32
57871462 8673 // If something jumps here with 64-bit values
8674 // then promote those registers to 64 bits
8675 if(bt[i])
8676 {
8677 uint64_t temp_is32=current.is32;
8678 for(j=i-1;j>=0;j--)
8679 {
8680 if(ba[j]==start+i*4)
8681 temp_is32&=branch_regs[j].is32;
8682 }
8683 for(j=i;j<slen;j++)
8684 {
8685 if(ba[j]==start+i*4)
8686 //temp_is32=1;
8687 temp_is32&=p32[j];
8688 }
8689 if(temp_is32!=current.is32) {
8690 //printf("dumping 32-bit regs (%x)\n",start+i*4);
8691 #ifdef DESTRUCTIVE_WRITEBACK
8692 for(hr=0;hr<HOST_REGS;hr++)
8693 {
8694 int r=current.regmap[hr];
8695 if(r>0&&r<64)
8696 {
8697 if((current.dirty>>hr)&((current.is32&~temp_is32)>>r)&1) {
8698 temp_is32|=1LL<<r;
8699 //printf("restore %d\n",r);
8700 }
8701 }
8702 }
8703 #endif
8704 current.is32=temp_is32;
8705 }
8706 }
6ebf4adf 8707#else
24385cae 8708 current.is32=-1LL;
8709#endif
8710
57871462 8711 memcpy(regmap_pre[i],current.regmap,sizeof(current.regmap));
8712 regs[i].wasconst=current.isconst;
8713 regs[i].was32=current.is32;
8714 regs[i].wasdirty=current.dirty;
6ebf4adf 8715 #if defined(DESTRUCTIVE_WRITEBACK) && !defined(FORCE32)
57871462 8716 // To change a dirty register from 32 to 64 bits, we must write
8717 // it out during the previous cycle (for branches, 2 cycles)
8718 if(i<slen-1&&bt[i+1]&&itype[i-1]!=UJUMP&&itype[i-1]!=CJUMP&&itype[i-1]!=SJUMP&&itype[i-1]!=RJUMP&&itype[i-1]!=FJUMP)
8719 {
8720 uint64_t temp_is32=current.is32;
8721 for(j=i-1;j>=0;j--)
8722 {
8723 if(ba[j]==start+i*4+4)
8724 temp_is32&=branch_regs[j].is32;
8725 }
8726 for(j=i;j<slen;j++)
8727 {
8728 if(ba[j]==start+i*4+4)
8729 //temp_is32=1;
8730 temp_is32&=p32[j];
8731 }
8732 if(temp_is32!=current.is32) {
8733 //printf("pre-dumping 32-bit regs (%x)\n",start+i*4);
8734 for(hr=0;hr<HOST_REGS;hr++)
8735 {
8736 int r=current.regmap[hr];
8737 if(r>0)
8738 {
8739 if((current.dirty>>hr)&((current.is32&~temp_is32)>>(r&63))&1) {
8740 if(itype[i]!=UJUMP&&itype[i]!=CJUMP&&itype[i]!=SJUMP&&itype[i]!=RJUMP&&itype[i]!=FJUMP)
8741 {
8742 if(rs1[i]!=(r&63)&&rs2[i]!=(r&63))
8743 {
8744 //printf("dump %d/r%d\n",hr,r);
8745 current.regmap[hr]=-1;
8746 if(get_reg(current.regmap,r|64)>=0)
8747 current.regmap[get_reg(current.regmap,r|64)]=-1;
8748 }
8749 }
8750 }
8751 }
8752 }
8753 }
8754 }
8755 else if(i<slen-2&&bt[i+2]&&(source[i-1]>>16)!=0x1000&&(itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP))
8756 {
8757 uint64_t temp_is32=current.is32;
8758 for(j=i-1;j>=0;j--)
8759 {
8760 if(ba[j]==start+i*4+8)
8761 temp_is32&=branch_regs[j].is32;
8762 }
8763 for(j=i;j<slen;j++)
8764 {
8765 if(ba[j]==start+i*4+8)
8766 //temp_is32=1;
8767 temp_is32&=p32[j];
8768 }
8769 if(temp_is32!=current.is32) {
8770 //printf("pre-dumping 32-bit regs (%x)\n",start+i*4);
8771 for(hr=0;hr<HOST_REGS;hr++)
8772 {
8773 int r=current.regmap[hr];
8774 if(r>0)
8775 {
8776 if((current.dirty>>hr)&((current.is32&~temp_is32)>>(r&63))&1) {
8777 if(rs1[i]!=(r&63)&&rs2[i]!=(r&63)&&rs1[i+1]!=(r&63)&&rs2[i+1]!=(r&63))
8778 {
8779 //printf("dump %d/r%d\n",hr,r);
8780 current.regmap[hr]=-1;
8781 if(get_reg(current.regmap,r|64)>=0)
8782 current.regmap[get_reg(current.regmap,r|64)]=-1;
8783 }
8784 }
8785 }
8786 }
8787 }
8788 }
8789 #endif
8790 if(itype[i]!=UJUMP&&itype[i]!=CJUMP&&itype[i]!=SJUMP&&itype[i]!=RJUMP&&itype[i]!=FJUMP) {
8791 if(i+1<slen) {
8792 current.u=unneeded_reg[i+1]&~((1LL<<rs1[i])|(1LL<<rs2[i]));
8793 current.uu=unneeded_reg_upper[i+1]&~((1LL<<us1[i])|(1LL<<us2[i]));
8794 if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
8795 current.u|=1;
8796 current.uu|=1;
8797 } else {
8798 current.u=1;
8799 current.uu=1;
8800 }
8801 } else {
8802 if(i+1<slen) {
8803 current.u=branch_unneeded_reg[i]&~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
8804 current.uu=branch_unneeded_reg_upper[i]&~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
8805 if((~current.uu>>rt1[i+1])&1) current.uu&=~((1LL<<dep1[i+1])|(1LL<<dep2[i+1]));
8806 current.u&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
8807 current.uu&=~((1LL<<us1[i])|(1LL<<us2[i]));
8808 current.u|=1;
8809 current.uu|=1;
8810 } else { printf("oops, branch at end of block with no delay slot\n");exit(1); }
8811 }
8812 is_ds[i]=ds;
8813 if(ds) {
8814 ds=0; // Skip delay slot, already allocated as part of branch
8815 // ...but we need to alloc it in case something jumps here
8816 if(i+1<slen) {
8817 current.u=branch_unneeded_reg[i-1]&unneeded_reg[i+1];
8818 current.uu=branch_unneeded_reg_upper[i-1]&unneeded_reg_upper[i+1];
8819 }else{
8820 current.u=branch_unneeded_reg[i-1];
8821 current.uu=branch_unneeded_reg_upper[i-1];
8822 }
8823 current.u&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
8824 current.uu&=~((1LL<<us1[i])|(1LL<<us2[i]));
8825 if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
8826 current.u|=1;
8827 current.uu|=1;
8828 struct regstat temp;
8829 memcpy(&temp,&current,sizeof(current));
8830 temp.wasdirty=temp.dirty;
8831 temp.was32=temp.is32;
8832 // TODO: Take into account unconditional branches, as below
8833 delayslot_alloc(&temp,i);
8834 memcpy(regs[i].regmap,temp.regmap,sizeof(temp.regmap));
8835 regs[i].wasdirty=temp.wasdirty;
8836 regs[i].was32=temp.was32;
8837 regs[i].dirty=temp.dirty;
8838 regs[i].is32=temp.is32;
8839 regs[i].isconst=0;
8840 regs[i].wasconst=0;
8841 current.isconst=0;
8842 // Create entry (branch target) regmap
8843 for(hr=0;hr<HOST_REGS;hr++)
8844 {
8845 int r=temp.regmap[hr];
8846 if(r>=0) {
8847 if(r!=regmap_pre[i][hr]) {
8848 regs[i].regmap_entry[hr]=-1;
8849 }
8850 else
8851 {
8852 if(r<64){
8853 if((current.u>>r)&1) {
8854 regs[i].regmap_entry[hr]=-1;
8855 regs[i].regmap[hr]=-1;
8856 //Don't clear regs in the delay slot as the branch might need them
8857 //current.regmap[hr]=-1;
8858 }else
8859 regs[i].regmap_entry[hr]=r;
8860 }
8861 else {
8862 if((current.uu>>(r&63))&1) {
8863 regs[i].regmap_entry[hr]=-1;
8864 regs[i].regmap[hr]=-1;
8865 //Don't clear regs in the delay slot as the branch might need them
8866 //current.regmap[hr]=-1;
8867 }else
8868 regs[i].regmap_entry[hr]=r;
8869 }
8870 }
8871 } else {
8872 // First instruction expects CCREG to be allocated
8873 if(i==0&&hr==HOST_CCREG)
8874 regs[i].regmap_entry[hr]=CCREG;
8875 else
8876 regs[i].regmap_entry[hr]=-1;
8877 }
8878 }
8879 }
8880 else { // Not delay slot
8881 switch(itype[i]) {
8882 case UJUMP:
8883 //current.isconst=0; // DEBUG
8884 //current.wasconst=0; // DEBUG
8885 //regs[i].wasconst=0; // DEBUG
8886 clear_const(&current,rt1[i]);
8887 alloc_cc(&current,i);
8888 dirty_reg(&current,CCREG);
2adcd6fa 8889 ooo[i]=1;
8890 delayslot_alloc(&current,i+1);
57871462 8891 if (rt1[i]==31) {
8892 alloc_reg(&current,i,31);
8893 dirty_reg(&current,31);
4ef8f67d 8894 //assert(rs1[i+1]!=31&&rs2[i+1]!=31);
8895 //assert(rt1[i+1]!=rt1[i]);
57871462 8896 #ifdef REG_PREFETCH
8897 alloc_reg(&current,i,PTEMP);
8898 #endif
8899 //current.is32|=1LL<<rt1[i];
8900 }
57871462 8901 //current.isconst=0; // DEBUG
8902 ds=1;
8903 //printf("i=%d, isconst=%x\n",i,current.isconst);
8904 break;
8905 case RJUMP:
8906 //current.isconst=0;
8907 //current.wasconst=0;
8908 //regs[i].wasconst=0;
8909 clear_const(&current,rs1[i]);
8910 clear_const(&current,rt1[i]);
8911 alloc_cc(&current,i);
8912 dirty_reg(&current,CCREG);
8913 if(rs1[i]!=rt1[i+1]&&rs1[i]!=rt2[i+1]) {
8914 alloc_reg(&current,i,rs1[i]);
5067f341 8915 if (rt1[i]!=0) {
8916 alloc_reg(&current,i,rt1[i]);
8917 dirty_reg(&current,rt1[i]);
68b3faee 8918 assert(rs1[i+1]!=rt1[i]&&rs2[i+1]!=rt1[i]);
076655d1 8919 assert(rt1[i+1]!=rt1[i]);
57871462 8920 #ifdef REG_PREFETCH
8921 alloc_reg(&current,i,PTEMP);
8922 #endif
8923 }
8924 #ifdef USE_MINI_HT
8925 if(rs1[i]==31) { // JALR
8926 alloc_reg(&current,i,RHASH);
8927 #ifndef HOST_IMM_ADDR32
8928 alloc_reg(&current,i,RHTBL);
8929 #endif
8930 }
8931 #endif
8932 delayslot_alloc(&current,i+1);
8933 } else {
8934 // The delay slot overwrites our source register,
8935 // allocate a temporary register to hold the old value.
8936 current.isconst=0;
8937 current.wasconst=0;
8938 regs[i].wasconst=0;
8939 delayslot_alloc(&current,i+1);
8940 current.isconst=0;
8941 alloc_reg(&current,i,RTEMP);
8942 }
8943 //current.isconst=0; // DEBUG
e1190b87 8944 ooo[i]=1;
57871462 8945 ds=1;
8946 break;
8947 case CJUMP:
8948 //current.isconst=0;
8949 //current.wasconst=0;
8950 //regs[i].wasconst=0;
8951 clear_const(&current,rs1[i]);
8952 clear_const(&current,rs2[i]);
8953 if((opcode[i]&0x3E)==4) // BEQ/BNE
8954 {
8955 alloc_cc(&current,i);
8956 dirty_reg(&current,CCREG);
8957 if(rs1[i]) alloc_reg(&current,i,rs1[i]);
8958 if(rs2[i]) alloc_reg(&current,i,rs2[i]);
8959 if(!((current.is32>>rs1[i])&(current.is32>>rs2[i])&1))
8960 {
8961 if(rs1[i]) alloc_reg64(&current,i,rs1[i]);
8962 if(rs2[i]) alloc_reg64(&current,i,rs2[i]);
8963 }
8964 if((rs1[i]&&(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1]))||
8965 (rs2[i]&&(rs2[i]==rt1[i+1]||rs2[i]==rt2[i+1]))) {
8966 // The delay slot overwrites one of our conditions.
8967 // Allocate the branch condition registers instead.
57871462 8968 current.isconst=0;
8969 current.wasconst=0;
8970 regs[i].wasconst=0;
8971 if(rs1[i]) alloc_reg(&current,i,rs1[i]);
8972 if(rs2[i]) alloc_reg(&current,i,rs2[i]);
8973 if(!((current.is32>>rs1[i])&(current.is32>>rs2[i])&1))
8974 {
8975 if(rs1[i]) alloc_reg64(&current,i,rs1[i]);
8976 if(rs2[i]) alloc_reg64(&current,i,rs2[i]);
8977 }
8978 }
e1190b87 8979 else
8980 {
8981 ooo[i]=1;
8982 delayslot_alloc(&current,i+1);
8983 }
57871462 8984 }
8985 else
8986 if((opcode[i]&0x3E)==6) // BLEZ/BGTZ
8987 {
8988 alloc_cc(&current,i);
8989 dirty_reg(&current,CCREG);
8990 alloc_reg(&current,i,rs1[i]);
8991 if(!(current.is32>>rs1[i]&1))
8992 {
8993 alloc_reg64(&current,i,rs1[i]);
8994 }
8995 if(rs1[i]&&(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1])) {
8996 // The delay slot overwrites one of our conditions.
8997 // Allocate the branch condition registers instead.
57871462 8998 current.isconst=0;
8999 current.wasconst=0;
9000 regs[i].wasconst=0;
9001 if(rs1[i]) alloc_reg(&current,i,rs1[i]);
9002 if(!((current.is32>>rs1[i])&1))
9003 {
9004 if(rs1[i]) alloc_reg64(&current,i,rs1[i]);
9005 }
9006 }
e1190b87 9007 else
9008 {
9009 ooo[i]=1;
9010 delayslot_alloc(&current,i+1);
9011 }
57871462 9012 }
9013 else
9014 // Don't alloc the delay slot yet because we might not execute it
9015 if((opcode[i]&0x3E)==0x14) // BEQL/BNEL
9016 {
9017 current.isconst=0;
9018 current.wasconst=0;
9019 regs[i].wasconst=0;
9020 alloc_cc(&current,i);
9021 dirty_reg(&current,CCREG);
9022 alloc_reg(&current,i,rs1[i]);
9023 alloc_reg(&current,i,rs2[i]);
9024 if(!((current.is32>>rs1[i])&(current.is32>>rs2[i])&1))
9025 {
9026 alloc_reg64(&current,i,rs1[i]);
9027 alloc_reg64(&current,i,rs2[i]);
9028 }
9029 }
9030 else
9031 if((opcode[i]&0x3E)==0x16) // BLEZL/BGTZL
9032 {
9033 current.isconst=0;
9034 current.wasconst=0;
9035 regs[i].wasconst=0;
9036 alloc_cc(&current,i);
9037 dirty_reg(&current,CCREG);
9038 alloc_reg(&current,i,rs1[i]);
9039 if(!(current.is32>>rs1[i]&1))
9040 {
9041 alloc_reg64(&current,i,rs1[i]);
9042 }
9043 }
9044 ds=1;
9045 //current.isconst=0;
9046 break;
9047 case SJUMP:
9048 //current.isconst=0;
9049 //current.wasconst=0;
9050 //regs[i].wasconst=0;
9051 clear_const(&current,rs1[i]);
9052 clear_const(&current,rt1[i]);
9053 //if((opcode2[i]&0x1E)==0x0) // BLTZ/BGEZ
9054 if((opcode2[i]&0x0E)==0x0) // BLTZ/BGEZ
9055 {
9056 alloc_cc(&current,i);
9057 dirty_reg(&current,CCREG);
9058 alloc_reg(&current,i,rs1[i]);
9059 if(!(current.is32>>rs1[i]&1))
9060 {
9061 alloc_reg64(&current,i,rs1[i]);
9062 }
9063 if (rt1[i]==31) { // BLTZAL/BGEZAL
9064 alloc_reg(&current,i,31);
9065 dirty_reg(&current,31);
57871462 9066 //#ifdef REG_PREFETCH
9067 //alloc_reg(&current,i,PTEMP);
9068 //#endif
9069 //current.is32|=1LL<<rt1[i];
9070 }
e1190b87 9071 if((rs1[i]&&(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1])) // The delay slot overwrites the branch condition.
9072 ||(rt1[i]==31&&(rs1[i+1]==31||rs2[i+1]==31||rt1[i+1]==31||rt2[i+1]==31))) { // DS touches $ra
57871462 9073 // Allocate the branch condition registers instead.
57871462 9074 current.isconst=0;
9075 current.wasconst=0;
9076 regs[i].wasconst=0;
9077 if(rs1[i]) alloc_reg(&current,i,rs1[i]);
9078 if(!((current.is32>>rs1[i])&1))
9079 {
9080 if(rs1[i]) alloc_reg64(&current,i,rs1[i]);
9081 }
9082 }
e1190b87 9083 else
9084 {
9085 ooo[i]=1;
9086 delayslot_alloc(&current,i+1);
9087 }
57871462 9088 }
9089 else
9090 // Don't alloc the delay slot yet because we might not execute it
9091 if((opcode2[i]&0x1E)==0x2) // BLTZL/BGEZL
9092 {
9093 current.isconst=0;
9094 current.wasconst=0;
9095 regs[i].wasconst=0;
9096 alloc_cc(&current,i);
9097 dirty_reg(&current,CCREG);
9098 alloc_reg(&current,i,rs1[i]);
9099 if(!(current.is32>>rs1[i]&1))
9100 {
9101 alloc_reg64(&current,i,rs1[i]);
9102 }
9103 }
9104 ds=1;
9105 //current.isconst=0;
9106 break;
9107 case FJUMP:
9108 current.isconst=0;
9109 current.wasconst=0;
9110 regs[i].wasconst=0;
9111 if(likely[i]==0) // BC1F/BC1T
9112 {
9113 // TODO: Theoretically we can run out of registers here on x86.
9114 // The delay slot can allocate up to six, and we need to check
9115 // CSREG before executing the delay slot. Possibly we can drop
9116 // the cycle count and then reload it after checking that the
9117 // FPU is in a usable state, or don't do out-of-order execution.
9118 alloc_cc(&current,i);
9119 dirty_reg(&current,CCREG);
9120 alloc_reg(&current,i,FSREG);
9121 alloc_reg(&current,i,CSREG);
9122 if(itype[i+1]==FCOMP) {
9123 // The delay slot overwrites the branch condition.
9124 // Allocate the branch condition registers instead.
57871462 9125 alloc_cc(&current,i);
9126 dirty_reg(&current,CCREG);
9127 alloc_reg(&current,i,CSREG);
9128 alloc_reg(&current,i,FSREG);
9129 }
9130 else {
e1190b87 9131 ooo[i]=1;
57871462 9132 delayslot_alloc(&current,i+1);
9133 alloc_reg(&current,i+1,CSREG);
9134 }
9135 }
9136 else
9137 // Don't alloc the delay slot yet because we might not execute it
9138 if(likely[i]) // BC1FL/BC1TL
9139 {
9140 alloc_cc(&current,i);
9141 dirty_reg(&current,CCREG);
9142 alloc_reg(&current,i,CSREG);
9143 alloc_reg(&current,i,FSREG);
9144 }
9145 ds=1;
9146 current.isconst=0;
9147 break;
9148 case IMM16:
9149 imm16_alloc(&current,i);
9150 break;
9151 case LOAD:
9152 case LOADLR:
9153 load_alloc(&current,i);
9154 break;
9155 case STORE:
9156 case STORELR:
9157 store_alloc(&current,i);
9158 break;
9159 case ALU:
9160 alu_alloc(&current,i);
9161 break;
9162 case SHIFT:
9163 shift_alloc(&current,i);
9164 break;
9165 case MULTDIV:
9166 multdiv_alloc(&current,i);
9167 break;
9168 case SHIFTIMM:
9169 shiftimm_alloc(&current,i);
9170 break;
9171 case MOV:
9172 mov_alloc(&current,i);
9173 break;
9174 case COP0:
9175 cop0_alloc(&current,i);
9176 break;
9177 case COP1:
b9b61529 9178 case COP2:
57871462 9179 cop1_alloc(&current,i);
9180 break;
9181 case C1LS:
9182 c1ls_alloc(&current,i);
9183 break;
b9b61529 9184 case C2LS:
9185 c2ls_alloc(&current,i);
9186 break;
9187 case C2OP:
9188 c2op_alloc(&current,i);
9189 break;
57871462 9190 case FCONV:
9191 fconv_alloc(&current,i);
9192 break;
9193 case FLOAT:
9194 float_alloc(&current,i);
9195 break;
9196 case FCOMP:
9197 fcomp_alloc(&current,i);
9198 break;
9199 case SYSCALL:
7139f3c8 9200 case HLECALL:
1e973cb0 9201 case INTCALL:
57871462 9202 syscall_alloc(&current,i);
9203 break;
9204 case SPAN:
9205 pagespan_alloc(&current,i);
9206 break;
9207 }
9208
9209 // Drop the upper half of registers that have become 32-bit
9210 current.uu|=current.is32&((1LL<<rt1[i])|(1LL<<rt2[i]));
9211 if(itype[i]!=UJUMP&&itype[i]!=CJUMP&&itype[i]!=SJUMP&&itype[i]!=RJUMP&&itype[i]!=FJUMP) {
9212 current.uu&=~((1LL<<us1[i])|(1LL<<us2[i]));
9213 if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
9214 current.uu|=1;
9215 } else {
9216 current.uu|=current.is32&((1LL<<rt1[i+1])|(1LL<<rt2[i+1]));
9217 current.uu&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
9218 if((~current.uu>>rt1[i+1])&1) current.uu&=~((1LL<<dep1[i+1])|(1LL<<dep2[i+1]));
9219 current.uu&=~((1LL<<us1[i])|(1LL<<us2[i]));
9220 current.uu|=1;
9221 }
9222
9223 // Create entry (branch target) regmap
9224 for(hr=0;hr<HOST_REGS;hr++)
9225 {
9226 int r,or,er;
9227 r=current.regmap[hr];
9228 if(r>=0) {
9229 if(r!=regmap_pre[i][hr]) {
9230 // TODO: delay slot (?)
9231 or=get_reg(regmap_pre[i],r); // Get old mapping for this register
9232 if(or<0||(r&63)>=TEMPREG){
9233 regs[i].regmap_entry[hr]=-1;
9234 }
9235 else
9236 {
9237 // Just move it to a different register
9238 regs[i].regmap_entry[hr]=r;
9239 // If it was dirty before, it's still dirty
9240 if((regs[i].wasdirty>>or)&1) dirty_reg(&current,r&63);
9241 }
9242 }
9243 else
9244 {
9245 // Unneeded
9246 if(r==0){
9247 regs[i].regmap_entry[hr]=0;
9248 }
9249 else
9250 if(r<64){
9251 if((current.u>>r)&1) {
9252 regs[i].regmap_entry[hr]=-1;
9253 //regs[i].regmap[hr]=-1;
9254 current.regmap[hr]=-1;
9255 }else
9256 regs[i].regmap_entry[hr]=r;
9257 }
9258 else {
9259 if((current.uu>>(r&63))&1) {
9260 regs[i].regmap_entry[hr]=-1;
9261 //regs[i].regmap[hr]=-1;
9262 current.regmap[hr]=-1;
9263 }else
9264 regs[i].regmap_entry[hr]=r;
9265 }
9266 }
9267 } else {
9268 // Branches expect CCREG to be allocated at the target
9269 if(regmap_pre[i][hr]==CCREG)
9270 regs[i].regmap_entry[hr]=CCREG;
9271 else
9272 regs[i].regmap_entry[hr]=-1;
9273 }
9274 }
9275 memcpy(regs[i].regmap,current.regmap,sizeof(current.regmap));
9276 }
9277 /* Branch post-alloc */
9278 if(i>0)
9279 {
9280 current.was32=current.is32;
9281 current.wasdirty=current.dirty;
9282 switch(itype[i-1]) {
9283 case UJUMP:
9284 memcpy(&branch_regs[i-1],&current,sizeof(current));
9285 branch_regs[i-1].isconst=0;
9286 branch_regs[i-1].wasconst=0;
9287 branch_regs[i-1].u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i-1])|(1LL<<rs2[i-1]));
9288 branch_regs[i-1].uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i-1])|(1LL<<us2[i-1]));
9289 alloc_cc(&branch_regs[i-1],i-1);
9290 dirty_reg(&branch_regs[i-1],CCREG);
9291 if(rt1[i-1]==31) { // JAL
9292 alloc_reg(&branch_regs[i-1],i-1,31);
9293 dirty_reg(&branch_regs[i-1],31);
9294 branch_regs[i-1].is32|=1LL<<31;
9295 }
9296 memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
9297 memcpy(constmap[i],constmap[i-1],sizeof(current.constmap));
9298 break;
9299 case RJUMP:
9300 memcpy(&branch_regs[i-1],&current,sizeof(current));
9301 branch_regs[i-1].isconst=0;
9302 branch_regs[i-1].wasconst=0;
9303 branch_regs[i-1].u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i-1])|(1LL<<rs2[i-1]));
9304 branch_regs[i-1].uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i-1])|(1LL<<us2[i-1]));
9305 alloc_cc(&branch_regs[i-1],i-1);
9306 dirty_reg(&branch_regs[i-1],CCREG);
9307 alloc_reg(&branch_regs[i-1],i-1,rs1[i-1]);
5067f341 9308 if(rt1[i-1]!=0) { // JALR
9309 alloc_reg(&branch_regs[i-1],i-1,rt1[i-1]);
9310 dirty_reg(&branch_regs[i-1],rt1[i-1]);
9311 branch_regs[i-1].is32|=1LL<<rt1[i-1];
57871462 9312 }
9313 #ifdef USE_MINI_HT
9314 if(rs1[i-1]==31) { // JALR
9315 alloc_reg(&branch_regs[i-1],i-1,RHASH);
9316 #ifndef HOST_IMM_ADDR32
9317 alloc_reg(&branch_regs[i-1],i-1,RHTBL);
9318 #endif
9319 }
9320 #endif
9321 memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
9322 memcpy(constmap[i],constmap[i-1],sizeof(current.constmap));
9323 break;
9324 case CJUMP:
9325 if((opcode[i-1]&0x3E)==4) // BEQ/BNE
9326 {
9327 alloc_cc(&current,i-1);
9328 dirty_reg(&current,CCREG);
9329 if((rs1[i-1]&&(rs1[i-1]==rt1[i]||rs1[i-1]==rt2[i]))||
9330 (rs2[i-1]&&(rs2[i-1]==rt1[i]||rs2[i-1]==rt2[i]))) {
9331 // The delay slot overwrote one of our conditions
9332 // Delay slot goes after the test (in order)
9333 current.u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i]));
9334 current.uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i]));
9335 if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
9336 current.u|=1;
9337 current.uu|=1;
9338 delayslot_alloc(&current,i);
9339 current.isconst=0;
9340 }
9341 else
9342 {
9343 current.u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i-1])|(1LL<<rs2[i-1]));
9344 current.uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i-1])|(1LL<<us2[i-1]));
9345 // Alloc the branch condition registers
9346 if(rs1[i-1]) alloc_reg(&current,i-1,rs1[i-1]);
9347 if(rs2[i-1]) alloc_reg(&current,i-1,rs2[i-1]);
9348 if(!((current.is32>>rs1[i-1])&(current.is32>>rs2[i-1])&1))
9349 {
9350 if(rs1[i-1]) alloc_reg64(&current,i-1,rs1[i-1]);
9351 if(rs2[i-1]) alloc_reg64(&current,i-1,rs2[i-1]);
9352 }
9353 }
9354 memcpy(&branch_regs[i-1],&current,sizeof(current));
9355 branch_regs[i-1].isconst=0;
9356 branch_regs[i-1].wasconst=0;
9357 memcpy(&branch_regs[i-1].regmap_entry,&current.regmap,sizeof(current.regmap));
9358 memcpy(constmap[i],constmap[i-1],sizeof(current.constmap));
9359 }
9360 else
9361 if((opcode[i-1]&0x3E)==6) // BLEZ/BGTZ
9362 {
9363 alloc_cc(&current,i-1);
9364 dirty_reg(&current,CCREG);
9365 if(rs1[i-1]==rt1[i]||rs1[i-1]==rt2[i]) {
9366 // The delay slot overwrote the branch condition
9367 // Delay slot goes after the test (in order)
9368 current.u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i]));
9369 current.uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i]));
9370 if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
9371 current.u|=1;
9372 current.uu|=1;
9373 delayslot_alloc(&current,i);
9374 current.isconst=0;
9375 }
9376 else
9377 {
9378 current.u=branch_unneeded_reg[i-1]&~(1LL<<rs1[i-1]);
9379 current.uu=branch_unneeded_reg_upper[i-1]&~(1LL<<us1[i-1]);
9380 // Alloc the branch condition register
9381 alloc_reg(&current,i-1,rs1[i-1]);
9382 if(!(current.is32>>rs1[i-1]&1))
9383 {
9384 alloc_reg64(&current,i-1,rs1[i-1]);
9385 }
9386 }
9387 memcpy(&branch_regs[i-1],&current,sizeof(current));
9388 branch_regs[i-1].isconst=0;
9389 branch_regs[i-1].wasconst=0;
9390 memcpy(&branch_regs[i-1].regmap_entry,&current.regmap,sizeof(current.regmap));
9391 memcpy(constmap[i],constmap[i-1],sizeof(current.constmap));
9392 }
9393 else
9394 // Alloc the delay slot in case the branch is taken
9395 if((opcode[i-1]&0x3E)==0x14) // BEQL/BNEL
9396 {
9397 memcpy(&branch_regs[i-1],&current,sizeof(current));
9398 branch_regs[i-1].u=(branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9399 branch_regs[i-1].uu=(branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9400 if((~branch_regs[i-1].uu>>rt1[i])&1) branch_regs[i-1].uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]))|1;
9401 alloc_cc(&branch_regs[i-1],i);
9402 dirty_reg(&branch_regs[i-1],CCREG);
9403 delayslot_alloc(&branch_regs[i-1],i);
9404 branch_regs[i-1].isconst=0;
9405 alloc_reg(&current,i,CCREG); // Not taken path
9406 dirty_reg(&current,CCREG);
9407 memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
9408 }
9409 else
9410 if((opcode[i-1]&0x3E)==0x16) // BLEZL/BGTZL
9411 {
9412 memcpy(&branch_regs[i-1],&current,sizeof(current));
9413 branch_regs[i-1].u=(branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9414 branch_regs[i-1].uu=(branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9415 if((~branch_regs[i-1].uu>>rt1[i])&1) branch_regs[i-1].uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]))|1;
9416 alloc_cc(&branch_regs[i-1],i);
9417 dirty_reg(&branch_regs[i-1],CCREG);
9418 delayslot_alloc(&branch_regs[i-1],i);
9419 branch_regs[i-1].isconst=0;
9420 alloc_reg(&current,i,CCREG); // Not taken path
9421 dirty_reg(&current,CCREG);
9422 memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
9423 }
9424 break;
9425 case SJUMP:
9426 //if((opcode2[i-1]&0x1E)==0) // BLTZ/BGEZ
9427 if((opcode2[i-1]&0x0E)==0) // BLTZ/BGEZ
9428 {
9429 alloc_cc(&current,i-1);
9430 dirty_reg(&current,CCREG);
9431 if(rs1[i-1]==rt1[i]||rs1[i-1]==rt2[i]) {
9432 // The delay slot overwrote the branch condition
9433 // Delay slot goes after the test (in order)
9434 current.u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i]));
9435 current.uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i]));
9436 if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
9437 current.u|=1;
9438 current.uu|=1;
9439 delayslot_alloc(&current,i);
9440 current.isconst=0;
9441 }
9442 else
9443 {
9444 current.u=branch_unneeded_reg[i-1]&~(1LL<<rs1[i-1]);
9445 current.uu=branch_unneeded_reg_upper[i-1]&~(1LL<<us1[i-1]);
9446 // Alloc the branch condition register
9447 alloc_reg(&current,i-1,rs1[i-1]);
9448 if(!(current.is32>>rs1[i-1]&1))
9449 {
9450 alloc_reg64(&current,i-1,rs1[i-1]);
9451 }
9452 }
9453 memcpy(&branch_regs[i-1],&current,sizeof(current));
9454 branch_regs[i-1].isconst=0;
9455 branch_regs[i-1].wasconst=0;
9456 memcpy(&branch_regs[i-1].regmap_entry,&current.regmap,sizeof(current.regmap));
9457 memcpy(constmap[i],constmap[i-1],sizeof(current.constmap));
9458 }
9459 else
9460 // Alloc the delay slot in case the branch is taken
9461 if((opcode2[i-1]&0x1E)==2) // BLTZL/BGEZL
9462 {
9463 memcpy(&branch_regs[i-1],&current,sizeof(current));
9464 branch_regs[i-1].u=(branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9465 branch_regs[i-1].uu=(branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9466 if((~branch_regs[i-1].uu>>rt1[i])&1) branch_regs[i-1].uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]))|1;
9467 alloc_cc(&branch_regs[i-1],i);
9468 dirty_reg(&branch_regs[i-1],CCREG);
9469 delayslot_alloc(&branch_regs[i-1],i);
9470 branch_regs[i-1].isconst=0;
9471 alloc_reg(&current,i,CCREG); // Not taken path
9472 dirty_reg(&current,CCREG);
9473 memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
9474 }
9475 // FIXME: BLTZAL/BGEZAL
9476 if(opcode2[i-1]&0x10) { // BxxZAL
9477 alloc_reg(&branch_regs[i-1],i-1,31);
9478 dirty_reg(&branch_regs[i-1],31);
9479 branch_regs[i-1].is32|=1LL<<31;
9480 }
9481 break;
9482 case FJUMP:
9483 if(likely[i-1]==0) // BC1F/BC1T
9484 {
9485 alloc_cc(&current,i-1);
9486 dirty_reg(&current,CCREG);
9487 if(itype[i]==FCOMP) {
9488 // The delay slot overwrote the branch condition
9489 // Delay slot goes after the test (in order)
9490 delayslot_alloc(&current,i);
9491 current.isconst=0;
9492 }
9493 else
9494 {
9495 current.u=branch_unneeded_reg[i-1]&~(1LL<<rs1[i-1]);
9496 current.uu=branch_unneeded_reg_upper[i-1]&~(1LL<<us1[i-1]);
9497 // Alloc the branch condition register
9498 alloc_reg(&current,i-1,FSREG);
9499 }
9500 memcpy(&branch_regs[i-1],&current,sizeof(current));
9501 memcpy(&branch_regs[i-1].regmap_entry,&current.regmap,sizeof(current.regmap));
9502 }
9503 else // BC1FL/BC1TL
9504 {
9505 // Alloc the delay slot in case the branch is taken
9506 memcpy(&branch_regs[i-1],&current,sizeof(current));
9507 branch_regs[i-1].u=(branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9508 branch_regs[i-1].uu=(branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9509 if((~branch_regs[i-1].uu>>rt1[i])&1) branch_regs[i-1].uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]))|1;
9510 alloc_cc(&branch_regs[i-1],i);
9511 dirty_reg(&branch_regs[i-1],CCREG);
9512 delayslot_alloc(&branch_regs[i-1],i);
9513 branch_regs[i-1].isconst=0;
9514 alloc_reg(&current,i,CCREG); // Not taken path
9515 dirty_reg(&current,CCREG);
9516 memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
9517 }
9518 break;
9519 }
9520
9521 if(itype[i-1]==UJUMP||itype[i-1]==RJUMP||(source[i-1]>>16)==0x1000)
9522 {
9523 if(rt1[i-1]==31) // JAL/JALR
9524 {
9525 // Subroutine call will return here, don't alloc any registers
9526 current.is32=1;
9527 current.dirty=0;
9528 clear_all_regs(current.regmap);
9529 alloc_reg(&current,i,CCREG);
9530 dirty_reg(&current,CCREG);
9531 }
9532 else if(i+1<slen)
9533 {
9534 // Internal branch will jump here, match registers to caller
9535 current.is32=0x3FFFFFFFFLL;
9536 current.dirty=0;
9537 clear_all_regs(current.regmap);
9538 alloc_reg(&current,i,CCREG);
9539 dirty_reg(&current,CCREG);
9540 for(j=i-1;j>=0;j--)
9541 {
9542 if(ba[j]==start+i*4+4) {
9543 memcpy(current.regmap,branch_regs[j].regmap,sizeof(current.regmap));
9544 current.is32=branch_regs[j].is32;
9545 current.dirty=branch_regs[j].dirty;
9546 break;
9547 }
9548 }
9549 while(j>=0) {
9550 if(ba[j]==start+i*4+4) {
9551 for(hr=0;hr<HOST_REGS;hr++) {
9552 if(current.regmap[hr]!=branch_regs[j].regmap[hr]) {
9553 current.regmap[hr]=-1;
9554 }
9555 current.is32&=branch_regs[j].is32;
9556 current.dirty&=branch_regs[j].dirty;
9557 }
9558 }
9559 j--;
9560 }
9561 }
9562 }
9563 }
9564
9565 // Count cycles in between branches
9566 ccadj[i]=cc;
7139f3c8 9567 if(i>0&&(itype[i-1]==RJUMP||itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP||itype[i]==SYSCALL||itype[i]==HLECALL))
57871462 9568 {
9569 cc=0;
9570 }
fb407447 9571#ifdef PCSX
9572 else if(/*itype[i]==LOAD||*/itype[i]==STORE||itype[i]==C1LS) // load causes weird timing issues
9573 {
9574 cc+=2; // 2 cycle penalty (after CLOCK_DIVIDER)
9575 }
9576 else if(itype[i]==C2LS)
9577 {
9578 cc+=4;
9579 }
9580#endif
57871462 9581 else
9582 {
9583 cc++;
9584 }
9585
9586 flush_dirty_uppers(&current);
9587 if(!is_ds[i]) {
9588 regs[i].is32=current.is32;
9589 regs[i].dirty=current.dirty;
9590 regs[i].isconst=current.isconst;
9591 memcpy(constmap[i],current.constmap,sizeof(current.constmap));
9592 }
9593 for(hr=0;hr<HOST_REGS;hr++) {
9594 if(hr!=EXCLUDE_REG&&regs[i].regmap[hr]>=0) {
9595 if(regmap_pre[i][hr]!=regs[i].regmap[hr]) {
9596 regs[i].wasconst&=~(1<<hr);
9597 }
9598 }
9599 }
9600 if(current.regmap[HOST_BTREG]==BTREG) current.regmap[HOST_BTREG]=-1;
9601 }
9602
9603 /* Pass 4 - Cull unused host registers */
9604
9605 uint64_t nr=0;
9606
9607 for (i=slen-1;i>=0;i--)
9608 {
9609 int hr;
9610 if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
9611 {
9612 if(ba[i]<start || ba[i]>=(start+slen*4))
9613 {
9614 // Branch out of this block, don't need anything
9615 nr=0;
9616 }
9617 else
9618 {
9619 // Internal branch
9620 // Need whatever matches the target
9621 nr=0;
9622 int t=(ba[i]-start)>>2;
9623 for(hr=0;hr<HOST_REGS;hr++)
9624 {
9625 if(regs[i].regmap_entry[hr]>=0) {
9626 if(regs[i].regmap_entry[hr]==regs[t].regmap_entry[hr]) nr|=1<<hr;
9627 }
9628 }
9629 }
9630 // Conditional branch may need registers for following instructions
9631 if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000)
9632 {
9633 if(i<slen-2) {
9634 nr|=needed_reg[i+2];
9635 for(hr=0;hr<HOST_REGS;hr++)
9636 {
9637 if(regmap_pre[i+2][hr]>=0&&get_reg(regs[i+2].regmap_entry,regmap_pre[i+2][hr])<0) nr&=~(1<<hr);
9638 //if((regmap_entry[i+2][hr])>=0) if(!((nr>>hr)&1)) printf("%x-bogus(%d=%d)\n",start+i*4,hr,regmap_entry[i+2][hr]);
9639 }
9640 }
9641 }
9642 // Don't need stuff which is overwritten
f5955059 9643 //if(regs[i].regmap[hr]!=regmap_pre[i][hr]) nr&=~(1<<hr);
9644 //if(regs[i].regmap[hr]<0) nr&=~(1<<hr);
57871462 9645 // Merge in delay slot
9646 for(hr=0;hr<HOST_REGS;hr++)
9647 {
9648 if(!likely[i]) {
9649 // These are overwritten unless the branch is "likely"
9650 // and the delay slot is nullified if not taken
9651 if(rt1[i+1]&&rt1[i+1]==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
9652 if(rt2[i+1]&&rt2[i+1]==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
9653 }
9654 if(us1[i+1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9655 if(us2[i+1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9656 if(rs1[i+1]==regmap_pre[i][hr]) nr|=1<<hr;
9657 if(rs2[i+1]==regmap_pre[i][hr]) nr|=1<<hr;
9658 if(us1[i+1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9659 if(us2[i+1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9660 if(rs1[i+1]==regs[i].regmap_entry[hr]) nr|=1<<hr;
9661 if(rs2[i+1]==regs[i].regmap_entry[hr]) nr|=1<<hr;
9662 if(dep1[i+1]&&!((unneeded_reg_upper[i]>>dep1[i+1])&1)) {
9663 if(dep1[i+1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9664 if(dep2[i+1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9665 }
9666 if(dep2[i+1]&&!((unneeded_reg_upper[i]>>dep2[i+1])&1)) {
9667 if(dep1[i+1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9668 if(dep2[i+1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9669 }
b9b61529 9670 if(itype[i+1]==STORE || itype[i+1]==STORELR || (opcode[i+1]&0x3b)==0x39 || (opcode[i+1]&0x3b)==0x3a) {
57871462 9671 if(regmap_pre[i][hr]==INVCP) nr|=1<<hr;
9672 if(regs[i].regmap_entry[hr]==INVCP) nr|=1<<hr;
9673 }
9674 }
9675 }
1e973cb0 9676 else if(itype[i]==SYSCALL||itype[i]==HLECALL||itype[i]==INTCALL)
57871462 9677 {
9678 // SYSCALL instruction (software interrupt)
9679 nr=0;
9680 }
9681 else if(itype[i]==COP0 && (source[i]&0x3f)==0x18)
9682 {
9683 // ERET instruction (return from interrupt)
9684 nr=0;
9685 }
9686 else // Non-branch
9687 {
9688 if(i<slen-1) {
9689 for(hr=0;hr<HOST_REGS;hr++) {
9690 if(regmap_pre[i+1][hr]>=0&&get_reg(regs[i+1].regmap_entry,regmap_pre[i+1][hr])<0) nr&=~(1<<hr);
9691 if(regs[i].regmap[hr]!=regmap_pre[i+1][hr]) nr&=~(1<<hr);
9692 if(regs[i].regmap[hr]!=regmap_pre[i][hr]) nr&=~(1<<hr);
9693 if(regs[i].regmap[hr]<0) nr&=~(1<<hr);
9694 }
9695 }
9696 }
9697 for(hr=0;hr<HOST_REGS;hr++)
9698 {
9699 // Overwritten registers are not needed
9700 if(rt1[i]&&rt1[i]==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
9701 if(rt2[i]&&rt2[i]==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
9702 if(FTEMP==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
9703 // Source registers are needed
9704 if(us1[i]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9705 if(us2[i]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9706 if(rs1[i]==regmap_pre[i][hr]) nr|=1<<hr;
9707 if(rs2[i]==regmap_pre[i][hr]) nr|=1<<hr;
9708 if(us1[i]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9709 if(us2[i]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9710 if(rs1[i]==regs[i].regmap_entry[hr]) nr|=1<<hr;
9711 if(rs2[i]==regs[i].regmap_entry[hr]) nr|=1<<hr;
9712 if(dep1[i]&&!((unneeded_reg_upper[i]>>dep1[i])&1)) {
9713 if(dep1[i]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9714 if(dep1[i]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9715 }
9716 if(dep2[i]&&!((unneeded_reg_upper[i]>>dep2[i])&1)) {
9717 if(dep2[i]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9718 if(dep2[i]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9719 }
b9b61529 9720 if(itype[i]==STORE || itype[i]==STORELR || (opcode[i]&0x3b)==0x39 || (opcode[i]&0x3b)==0x3a) {
57871462 9721 if(regmap_pre[i][hr]==INVCP) nr|=1<<hr;
9722 if(regs[i].regmap_entry[hr]==INVCP) nr|=1<<hr;
9723 }
9724 // Don't store a register immediately after writing it,
9725 // may prevent dual-issue.
9726 // But do so if this is a branch target, otherwise we
9727 // might have to load the register before the branch.
9728 if(i>0&&!bt[i]&&((regs[i].wasdirty>>hr)&1)) {
9729 if((regmap_pre[i][hr]>0&&regmap_pre[i][hr]<64&&!((unneeded_reg[i]>>regmap_pre[i][hr])&1)) ||
9730 (regmap_pre[i][hr]>64&&!((unneeded_reg_upper[i]>>(regmap_pre[i][hr]&63))&1)) ) {
9731 if(rt1[i-1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9732 if(rt2[i-1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9733 }
9734 if((regs[i].regmap_entry[hr]>0&&regs[i].regmap_entry[hr]<64&&!((unneeded_reg[i]>>regs[i].regmap_entry[hr])&1)) ||
9735 (regs[i].regmap_entry[hr]>64&&!((unneeded_reg_upper[i]>>(regs[i].regmap_entry[hr]&63))&1)) ) {
9736 if(rt1[i-1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9737 if(rt2[i-1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9738 }
9739 }
9740 }
9741 // Cycle count is needed at branches. Assume it is needed at the target too.
9742 if(i==0||bt[i]||itype[i]==CJUMP||itype[i]==FJUMP||itype[i]==SPAN) {
9743 if(regmap_pre[i][HOST_CCREG]==CCREG) nr|=1<<HOST_CCREG;
9744 if(regs[i].regmap_entry[HOST_CCREG]==CCREG) nr|=1<<HOST_CCREG;
9745 }
9746 // Save it
9747 needed_reg[i]=nr;
9748
9749 // Deallocate unneeded registers
9750 for(hr=0;hr<HOST_REGS;hr++)
9751 {
9752 if(!((nr>>hr)&1)) {
9753 if(regs[i].regmap_entry[hr]!=CCREG) regs[i].regmap_entry[hr]=-1;
9754 if((regs[i].regmap[hr]&63)!=rs1[i] && (regs[i].regmap[hr]&63)!=rs2[i] &&
9755 (regs[i].regmap[hr]&63)!=rt1[i] && (regs[i].regmap[hr]&63)!=rt2[i] &&
9756 (regs[i].regmap[hr]&63)!=PTEMP && (regs[i].regmap[hr]&63)!=CCREG)
9757 {
9758 if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000)
9759 {
9760 if(likely[i]) {
9761 regs[i].regmap[hr]=-1;
9762 regs[i].isconst&=~(1<<hr);
79c75f1b 9763 if(i<slen-2) {
9764 regmap_pre[i+2][hr]=-1;
9765 regs[i+2].wasconst&=~(1<<hr);
9766 }
57871462 9767 }
9768 }
9769 }
9770 if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
9771 {
9772 int d1=0,d2=0,map=0,temp=0;
9773 if(get_reg(regs[i].regmap,rt1[i+1]|64)>=0||get_reg(branch_regs[i].regmap,rt1[i+1]|64)>=0)
9774 {
9775 d1=dep1[i+1];
9776 d2=dep2[i+1];
9777 }
9778 if(using_tlb) {
9779 if(itype[i+1]==LOAD || itype[i+1]==LOADLR ||
9780 itype[i+1]==STORE || itype[i+1]==STORELR ||
b9b61529 9781 itype[i+1]==C1LS || itype[i+1]==C2LS)
57871462 9782 map=TLREG;
9783 } else
b9b61529 9784 if(itype[i+1]==STORE || itype[i+1]==STORELR ||
9785 (opcode[i+1]&0x3b)==0x39 || (opcode[i+1]&0x3b)==0x3a) { // SWC1/SDC1 || SWC2/SDC2
57871462 9786 map=INVCP;
9787 }
9788 if(itype[i+1]==LOADLR || itype[i+1]==STORELR ||
b9b61529 9789 itype[i+1]==C1LS || itype[i+1]==C2LS)
57871462 9790 temp=FTEMP;
9791 if((regs[i].regmap[hr]&63)!=rs1[i] && (regs[i].regmap[hr]&63)!=rs2[i] &&
9792 (regs[i].regmap[hr]&63)!=rt1[i] && (regs[i].regmap[hr]&63)!=rt2[i] &&
9793 (regs[i].regmap[hr]&63)!=rt1[i+1] && (regs[i].regmap[hr]&63)!=rt2[i+1] &&
9794 (regs[i].regmap[hr]^64)!=us1[i+1] && (regs[i].regmap[hr]^64)!=us2[i+1] &&
9795 (regs[i].regmap[hr]^64)!=d1 && (regs[i].regmap[hr]^64)!=d2 &&
9796 regs[i].regmap[hr]!=rs1[i+1] && regs[i].regmap[hr]!=rs2[i+1] &&
9797 (regs[i].regmap[hr]&63)!=temp && regs[i].regmap[hr]!=PTEMP &&
9798 regs[i].regmap[hr]!=RHASH && regs[i].regmap[hr]!=RHTBL &&
9799 regs[i].regmap[hr]!=RTEMP && regs[i].regmap[hr]!=CCREG &&
9800 regs[i].regmap[hr]!=map )
9801 {
9802 regs[i].regmap[hr]=-1;
9803 regs[i].isconst&=~(1<<hr);
9804 if((branch_regs[i].regmap[hr]&63)!=rs1[i] && (branch_regs[i].regmap[hr]&63)!=rs2[i] &&
9805 (branch_regs[i].regmap[hr]&63)!=rt1[i] && (branch_regs[i].regmap[hr]&63)!=rt2[i] &&
9806 (branch_regs[i].regmap[hr]&63)!=rt1[i+1] && (branch_regs[i].regmap[hr]&63)!=rt2[i+1] &&
9807 (branch_regs[i].regmap[hr]^64)!=us1[i+1] && (branch_regs[i].regmap[hr]^64)!=us2[i+1] &&
9808 (branch_regs[i].regmap[hr]^64)!=d1 && (branch_regs[i].regmap[hr]^64)!=d2 &&
9809 branch_regs[i].regmap[hr]!=rs1[i+1] && branch_regs[i].regmap[hr]!=rs2[i+1] &&
9810 (branch_regs[i].regmap[hr]&63)!=temp && branch_regs[i].regmap[hr]!=PTEMP &&
9811 branch_regs[i].regmap[hr]!=RHASH && branch_regs[i].regmap[hr]!=RHTBL &&
9812 branch_regs[i].regmap[hr]!=RTEMP && branch_regs[i].regmap[hr]!=CCREG &&
9813 branch_regs[i].regmap[hr]!=map)
9814 {
9815 branch_regs[i].regmap[hr]=-1;
9816 branch_regs[i].regmap_entry[hr]=-1;
9817 if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000)
9818 {
9819 if(!likely[i]&&i<slen-2) {
9820 regmap_pre[i+2][hr]=-1;
79c75f1b 9821 regs[i+2].wasconst&=~(1<<hr);
57871462 9822 }
9823 }
9824 }
9825 }
9826 }
9827 else
9828 {
9829 // Non-branch
9830 if(i>0)
9831 {
9832 int d1=0,d2=0,map=-1,temp=-1;
9833 if(get_reg(regs[i].regmap,rt1[i]|64)>=0)
9834 {
9835 d1=dep1[i];
9836 d2=dep2[i];
9837 }
9838 if(using_tlb) {
9839 if(itype[i]==LOAD || itype[i]==LOADLR ||
9840 itype[i]==STORE || itype[i]==STORELR ||
b9b61529 9841 itype[i]==C1LS || itype[i]==C2LS)
57871462 9842 map=TLREG;
b9b61529 9843 } else if(itype[i]==STORE || itype[i]==STORELR ||
9844 (opcode[i]&0x3b)==0x39 || (opcode[i]&0x3b)==0x3a) { // SWC1/SDC1 || SWC2/SDC2
57871462 9845 map=INVCP;
9846 }
9847 if(itype[i]==LOADLR || itype[i]==STORELR ||
b9b61529 9848 itype[i]==C1LS || itype[i]==C2LS)
57871462 9849 temp=FTEMP;
9850 if((regs[i].regmap[hr]&63)!=rt1[i] && (regs[i].regmap[hr]&63)!=rt2[i] &&
9851 (regs[i].regmap[hr]^64)!=us1[i] && (regs[i].regmap[hr]^64)!=us2[i] &&
9852 (regs[i].regmap[hr]^64)!=d1 && (regs[i].regmap[hr]^64)!=d2 &&
9853 regs[i].regmap[hr]!=rs1[i] && regs[i].regmap[hr]!=rs2[i] &&
9854 (regs[i].regmap[hr]&63)!=temp && regs[i].regmap[hr]!=map &&
9855 (itype[i]!=SPAN||regs[i].regmap[hr]!=CCREG))
9856 {
9857 if(i<slen-1&&!is_ds[i]) {
9858 if(regmap_pre[i+1][hr]!=-1 || regs[i].regmap[hr]!=-1)
9859 if(regmap_pre[i+1][hr]!=regs[i].regmap[hr])
9860 if(regs[i].regmap[hr]<64||!((regs[i].was32>>(regs[i].regmap[hr]&63))&1))
9861 {
9862 printf("fail: %x (%d %d!=%d)\n",start+i*4,hr,regmap_pre[i+1][hr],regs[i].regmap[hr]);
9863 assert(regmap_pre[i+1][hr]==regs[i].regmap[hr]);
9864 }
9865 regmap_pre[i+1][hr]=-1;
9866 if(regs[i+1].regmap_entry[hr]==CCREG) regs[i+1].regmap_entry[hr]=-1;
79c75f1b 9867 regs[i+1].wasconst&=~(1<<hr);
57871462 9868 }
9869 regs[i].regmap[hr]=-1;
9870 regs[i].isconst&=~(1<<hr);
9871 }
9872 }
9873 }
9874 }
9875 }
9876 }
9877
9878 /* Pass 5 - Pre-allocate registers */
9879
9880 // If a register is allocated during a loop, try to allocate it for the
9881 // entire loop, if possible. This avoids loading/storing registers
9882 // inside of the loop.
9883
9884 signed char f_regmap[HOST_REGS];
9885 clear_all_regs(f_regmap);
9886 for(i=0;i<slen-1;i++)
9887 {
9888 if(itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
9889 {
9890 if(ba[i]>=start && ba[i]<(start+i*4))
9891 if(itype[i+1]==NOP||itype[i+1]==MOV||itype[i+1]==ALU
9892 ||itype[i+1]==SHIFTIMM||itype[i+1]==IMM16||itype[i+1]==LOAD
9893 ||itype[i+1]==STORE||itype[i+1]==STORELR||itype[i+1]==C1LS
9894 ||itype[i+1]==SHIFT||itype[i+1]==COP1||itype[i+1]==FLOAT
b9b61529 9895 ||itype[i+1]==FCOMP||itype[i+1]==FCONV
9896 ||itype[i+1]==COP2||itype[i+1]==C2LS||itype[i+1]==C2OP)
57871462 9897 {
9898 int t=(ba[i]-start)>>2;
9899 if(t>0&&(itype[t-1]!=UJUMP&&itype[t-1]!=RJUMP&&itype[t-1]!=CJUMP&&itype[t-1]!=SJUMP&&itype[t-1]!=FJUMP)) // loop_preload can't handle jumps into delay slots
9900 if(t<2||(itype[t-2]!=UJUMP)) // call/ret assumes no registers allocated
9901 for(hr=0;hr<HOST_REGS;hr++)
9902 {
9903 if(regs[i].regmap[hr]>64) {
9904 if(!((regs[i].dirty>>hr)&1))
9905 f_regmap[hr]=regs[i].regmap[hr];
9906 else f_regmap[hr]=-1;
9907 }
b372a952 9908 else if(regs[i].regmap[hr]>=0) {
9909 if(f_regmap[hr]!=regs[i].regmap[hr]) {
9910 // dealloc old register
9911 int n;
9912 for(n=0;n<HOST_REGS;n++)
9913 {
9914 if(f_regmap[n]==regs[i].regmap[hr]) {f_regmap[n]=-1;}
9915 }
9916 // and alloc new one
9917 f_regmap[hr]=regs[i].regmap[hr];
9918 }
9919 }
57871462 9920 if(branch_regs[i].regmap[hr]>64) {
9921 if(!((branch_regs[i].dirty>>hr)&1))
9922 f_regmap[hr]=branch_regs[i].regmap[hr];
9923 else f_regmap[hr]=-1;
9924 }
b372a952 9925 else if(branch_regs[i].regmap[hr]>=0) {
9926 if(f_regmap[hr]!=branch_regs[i].regmap[hr]) {
9927 // dealloc old register
9928 int n;
9929 for(n=0;n<HOST_REGS;n++)
9930 {
9931 if(f_regmap[n]==branch_regs[i].regmap[hr]) {f_regmap[n]=-1;}
9932 }
9933 // and alloc new one
9934 f_regmap[hr]=branch_regs[i].regmap[hr];
9935 }
9936 }
e1190b87 9937 if(ooo[i]) {
9938 if(count_free_regs(regs[i].regmap)<=minimum_free_regs[i+1])
9939 f_regmap[hr]=branch_regs[i].regmap[hr];
9940 }else{
9941 if(count_free_regs(branch_regs[i].regmap)<=minimum_free_regs[i+1])
57871462 9942 f_regmap[hr]=branch_regs[i].regmap[hr];
9943 }
9944 // Avoid dirty->clean transition
e1190b87 9945 #ifdef DESTRUCTIVE_WRITEBACK
57871462 9946 if(t>0) if(get_reg(regmap_pre[t],f_regmap[hr])>=0) if((regs[t].wasdirty>>get_reg(regmap_pre[t],f_regmap[hr]))&1) f_regmap[hr]=-1;
e1190b87 9947 #endif
9948 // This check is only strictly required in the DESTRUCTIVE_WRITEBACK
9949 // case above, however it's always a good idea. We can't hoist the
9950 // load if the register was already allocated, so there's no point
9951 // wasting time analyzing most of these cases. It only "succeeds"
9952 // when the mapping was different and the load can be replaced with
9953 // a mov, which is of negligible benefit. So such cases are
9954 // skipped below.
57871462 9955 if(f_regmap[hr]>0) {
e1190b87 9956 if(regs[t].regmap_entry[hr]<0&&get_reg(regmap_pre[t],f_regmap[hr])<0) {
57871462 9957 int r=f_regmap[hr];
9958 for(j=t;j<=i;j++)
9959 {
9960 //printf("Test %x -> %x, %x %d/%d\n",start+i*4,ba[i],start+j*4,hr,r);
9961 if(r<34&&((unneeded_reg[j]>>r)&1)) break;
9962 if(r>63&&((unneeded_reg_upper[j]>>(r&63))&1)) break;
9963 if(r>63) {
9964 // NB This can exclude the case where the upper-half
9965 // register is lower numbered than the lower-half
9966 // register. Not sure if it's worth fixing...
9967 if(get_reg(regs[j].regmap,r&63)<0) break;
e1190b87 9968 if(get_reg(regs[j].regmap_entry,r&63)<0) break;
57871462 9969 if(regs[j].is32&(1LL<<(r&63))) break;
9970 }
9971 if(regs[j].regmap[hr]==f_regmap[hr]&&(f_regmap[hr]&63)<TEMPREG) {
9972 //printf("Hit %x -> %x, %x %d/%d\n",start+i*4,ba[i],start+j*4,hr,r);
9973 int k;
9974 if(regs[i].regmap[hr]==-1&&branch_regs[i].regmap[hr]==-1) {
9975 if(get_reg(regs[i+2].regmap,f_regmap[hr])>=0) break;
9976 if(r>63) {
9977 if(get_reg(regs[i].regmap,r&63)<0) break;
9978 if(get_reg(branch_regs[i].regmap,r&63)<0) break;
9979 }
9980 k=i;
9981 while(k>1&&regs[k-1].regmap[hr]==-1) {
e1190b87 9982 if(count_free_regs(regs[k-1].regmap)<=minimum_free_regs[k-1]) {
9983 //printf("no free regs for store %x\n",start+(k-1)*4);
9984 break;
57871462 9985 }
57871462 9986 if(get_reg(regs[k-1].regmap,f_regmap[hr])>=0) {
9987 //printf("no-match due to different register\n");
9988 break;
9989 }
9990 if(itype[k-2]==UJUMP||itype[k-2]==RJUMP||itype[k-2]==CJUMP||itype[k-2]==SJUMP||itype[k-2]==FJUMP) {
9991 //printf("no-match due to branch\n");
9992 break;
9993 }
9994 // call/ret fast path assumes no registers allocated
9995 if(k>2&&(itype[k-3]==UJUMP||itype[k-3]==RJUMP)) {
9996 break;
9997 }
9998 if(r>63) {
9999 // NB This can exclude the case where the upper-half
10000 // register is lower numbered than the lower-half
10001 // register. Not sure if it's worth fixing...
10002 if(get_reg(regs[k-1].regmap,r&63)<0) break;
10003 if(regs[k-1].is32&(1LL<<(r&63))) break;
10004 }
10005 k--;
10006 }
10007 if(i<slen-1) {
10008 if((regs[k].is32&(1LL<<f_regmap[hr]))!=
10009 (regs[i+2].was32&(1LL<<f_regmap[hr]))) {
10010 //printf("bad match after branch\n");
10011 break;
10012 }
10013 }
10014 if(regs[k-1].regmap[hr]==f_regmap[hr]&&regmap_pre[k][hr]==f_regmap[hr]) {
10015 //printf("Extend r%d, %x ->\n",hr,start+k*4);
10016 while(k<i) {
10017 regs[k].regmap_entry[hr]=f_regmap[hr];
10018 regs[k].regmap[hr]=f_regmap[hr];
10019 regmap_pre[k+1][hr]=f_regmap[hr];
10020 regs[k].wasdirty&=~(1<<hr);
10021 regs[k].dirty&=~(1<<hr);
10022 regs[k].wasdirty|=(1<<hr)&regs[k-1].dirty;
10023 regs[k].dirty|=(1<<hr)&regs[k].wasdirty;
10024 regs[k].wasconst&=~(1<<hr);
10025 regs[k].isconst&=~(1<<hr);
10026 k++;
10027 }
10028 }
10029 else {
10030 //printf("Fail Extend r%d, %x ->\n",hr,start+k*4);
10031 break;
10032 }
10033 assert(regs[i-1].regmap[hr]==f_regmap[hr]);
10034 if(regs[i-1].regmap[hr]==f_regmap[hr]&&regmap_pre[i][hr]==f_regmap[hr]) {
10035 //printf("OK fill %x (r%d)\n",start+i*4,hr);
10036 regs[i].regmap_entry[hr]=f_regmap[hr];
10037 regs[i].regmap[hr]=f_regmap[hr];
10038 regs[i].wasdirty&=~(1<<hr);
10039 regs[i].dirty&=~(1<<hr);
10040 regs[i].wasdirty|=(1<<hr)&regs[i-1].dirty;
10041 regs[i].dirty|=(1<<hr)&regs[i-1].dirty;
10042 regs[i].wasconst&=~(1<<hr);
10043 regs[i].isconst&=~(1<<hr);
10044 branch_regs[i].regmap_entry[hr]=f_regmap[hr];
10045 branch_regs[i].wasdirty&=~(1<<hr);
10046 branch_regs[i].wasdirty|=(1<<hr)&regs[i].dirty;
10047 branch_regs[i].regmap[hr]=f_regmap[hr];
10048 branch_regs[i].dirty&=~(1<<hr);
10049 branch_regs[i].dirty|=(1<<hr)&regs[i].dirty;
10050 branch_regs[i].wasconst&=~(1<<hr);
10051 branch_regs[i].isconst&=~(1<<hr);
10052 if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000) {
10053 regmap_pre[i+2][hr]=f_regmap[hr];
10054 regs[i+2].wasdirty&=~(1<<hr);
10055 regs[i+2].wasdirty|=(1<<hr)&regs[i].dirty;
10056 assert((branch_regs[i].is32&(1LL<<f_regmap[hr]))==
10057 (regs[i+2].was32&(1LL<<f_regmap[hr])));
10058 }
10059 }
10060 }
10061 for(k=t;k<j;k++) {
e1190b87 10062 // Alloc register clean at beginning of loop,
10063 // but may dirty it in pass 6
57871462 10064 regs[k].regmap_entry[hr]=f_regmap[hr];
10065 regs[k].regmap[hr]=f_regmap[hr];
57871462 10066 regs[k].dirty&=~(1<<hr);
10067 regs[k].wasconst&=~(1<<hr);
10068 regs[k].isconst&=~(1<<hr);
e1190b87 10069 if(itype[k]==UJUMP||itype[k]==RJUMP||itype[k]==CJUMP||itype[k]==SJUMP||itype[k]==FJUMP) {
10070 branch_regs[k].regmap_entry[hr]=f_regmap[hr];
10071 branch_regs[k].regmap[hr]=f_regmap[hr];
10072 branch_regs[k].dirty&=~(1<<hr);
10073 branch_regs[k].wasconst&=~(1<<hr);
10074 branch_regs[k].isconst&=~(1<<hr);
10075 if(itype[k]!=RJUMP&&itype[k]!=UJUMP&&(source[k]>>16)!=0x1000) {
10076 regmap_pre[k+2][hr]=f_regmap[hr];
10077 regs[k+2].wasdirty&=~(1<<hr);
10078 assert((branch_regs[k].is32&(1LL<<f_regmap[hr]))==
10079 (regs[k+2].was32&(1LL<<f_regmap[hr])));
10080 }
10081 }
10082 else
10083 {
10084 regmap_pre[k+1][hr]=f_regmap[hr];
10085 regs[k+1].wasdirty&=~(1<<hr);
10086 }
57871462 10087 }
10088 if(regs[j].regmap[hr]==f_regmap[hr])
10089 regs[j].regmap_entry[hr]=f_regmap[hr];
10090 break;
10091 }
10092 if(j==i) break;
10093 if(regs[j].regmap[hr]>=0)
10094 break;
10095 if(get_reg(regs[j].regmap,f_regmap[hr])>=0) {
10096 //printf("no-match due to different register\n");
10097 break;
10098 }
10099 if((regs[j+1].is32&(1LL<<f_regmap[hr]))!=(regs[j].is32&(1LL<<f_regmap[hr]))) {
10100 //printf("32/64 mismatch %x %d\n",start+j*4,hr);
10101 break;
10102 }
e1190b87 10103 if(itype[j]==UJUMP||itype[j]==RJUMP||(source[j]>>16)==0x1000)
10104 {
10105 // Stop on unconditional branch
10106 break;
10107 }
10108 if(itype[j]==CJUMP||itype[j]==SJUMP||itype[j]==FJUMP)
10109 {
10110 if(ooo[j]) {
10111 if(count_free_regs(regs[j].regmap)<=minimum_free_regs[j+1])
10112 break;
10113 }else{
10114 if(count_free_regs(branch_regs[j].regmap)<=minimum_free_regs[j+1])
10115 break;
10116 }
10117 if(get_reg(branch_regs[j].regmap,f_regmap[hr])>=0) {
10118 //printf("no-match due to different register (branch)\n");
57871462 10119 break;
10120 }
10121 }
e1190b87 10122 if(count_free_regs(regs[j].regmap)<=minimum_free_regs[j]) {
10123 //printf("No free regs for store %x\n",start+j*4);
10124 break;
10125 }
57871462 10126 if(f_regmap[hr]>=64) {
10127 if(regs[j].is32&(1LL<<(f_regmap[hr]&63))) {
10128 break;
10129 }
10130 else
10131 {
10132 if(get_reg(regs[j].regmap,f_regmap[hr]&63)<0) {
10133 break;
10134 }
10135 }
10136 }
10137 }
10138 }
10139 }
10140 }
10141 }
10142 }else{
10143 int count=0;
10144 for(hr=0;hr<HOST_REGS;hr++)
10145 {
10146 if(hr!=EXCLUDE_REG) {
10147 if(regs[i].regmap[hr]>64) {
10148 if(!((regs[i].dirty>>hr)&1))
10149 f_regmap[hr]=regs[i].regmap[hr];
10150 }
b372a952 10151 else if(regs[i].regmap[hr]>=0) {
10152 if(f_regmap[hr]!=regs[i].regmap[hr]) {
10153 // dealloc old register
10154 int n;
10155 for(n=0;n<HOST_REGS;n++)
10156 {
10157 if(f_regmap[n]==regs[i].regmap[hr]) {f_regmap[n]=-1;}
10158 }
10159 // and alloc new one
10160 f_regmap[hr]=regs[i].regmap[hr];
10161 }
10162 }
57871462 10163 else if(regs[i].regmap[hr]<0) count++;
10164 }
10165 }
10166 // Try to restore cycle count at branch targets
10167 if(bt[i]) {
10168 for(j=i;j<slen-1;j++) {
10169 if(regs[j].regmap[HOST_CCREG]!=-1) break;
e1190b87 10170 if(count_free_regs(regs[j].regmap)<=minimum_free_regs[j]) {
10171 //printf("no free regs for store %x\n",start+j*4);
10172 break;
57871462 10173 }
57871462 10174 }
10175 if(regs[j].regmap[HOST_CCREG]==CCREG) {
10176 int k=i;
10177 //printf("Extend CC, %x -> %x\n",start+k*4,start+j*4);
10178 while(k<j) {
10179 regs[k].regmap_entry[HOST_CCREG]=CCREG;
10180 regs[k].regmap[HOST_CCREG]=CCREG;
10181 regmap_pre[k+1][HOST_CCREG]=CCREG;
10182 regs[k+1].wasdirty|=1<<HOST_CCREG;
10183 regs[k].dirty|=1<<HOST_CCREG;
10184 regs[k].wasconst&=~(1<<HOST_CCREG);
10185 regs[k].isconst&=~(1<<HOST_CCREG);
10186 k++;
10187 }
10188 regs[j].regmap_entry[HOST_CCREG]=CCREG;
10189 }
10190 // Work backwards from the branch target
10191 if(j>i&&f_regmap[HOST_CCREG]==CCREG)
10192 {
10193 //printf("Extend backwards\n");
10194 int k;
10195 k=i;
10196 while(regs[k-1].regmap[HOST_CCREG]==-1) {
e1190b87 10197 if(count_free_regs(regs[k-1].regmap)<=minimum_free_regs[k-1]) {
10198 //printf("no free regs for store %x\n",start+(k-1)*4);
10199 break;
57871462 10200 }
57871462 10201 k--;
10202 }
10203 if(regs[k-1].regmap[HOST_CCREG]==CCREG) {
10204 //printf("Extend CC, %x ->\n",start+k*4);
10205 while(k<=i) {
10206 regs[k].regmap_entry[HOST_CCREG]=CCREG;
10207 regs[k].regmap[HOST_CCREG]=CCREG;
10208 regmap_pre[k+1][HOST_CCREG]=CCREG;
10209 regs[k+1].wasdirty|=1<<HOST_CCREG;
10210 regs[k].dirty|=1<<HOST_CCREG;
10211 regs[k].wasconst&=~(1<<HOST_CCREG);
10212 regs[k].isconst&=~(1<<HOST_CCREG);
10213 k++;
10214 }
10215 }
10216 else {
10217 //printf("Fail Extend CC, %x ->\n",start+k*4);
10218 }
10219 }
10220 }
10221 if(itype[i]!=STORE&&itype[i]!=STORELR&&itype[i]!=C1LS&&itype[i]!=SHIFT&&
10222 itype[i]!=NOP&&itype[i]!=MOV&&itype[i]!=ALU&&itype[i]!=SHIFTIMM&&
10223 itype[i]!=IMM16&&itype[i]!=LOAD&&itype[i]!=COP1&&itype[i]!=FLOAT&&
e1190b87 10224 itype[i]!=FCONV&&itype[i]!=FCOMP)
57871462 10225 {
10226 memcpy(f_regmap,regs[i].regmap,sizeof(f_regmap));
10227 }
10228 }
10229 }
10230
10231 // This allocates registers (if possible) one instruction prior
10232 // to use, which can avoid a load-use penalty on certain CPUs.
10233 for(i=0;i<slen-1;i++)
10234 {
10235 if(!i||(itype[i-1]!=UJUMP&&itype[i-1]!=CJUMP&&itype[i-1]!=SJUMP&&itype[i-1]!=RJUMP&&itype[i-1]!=FJUMP))
10236 {
10237 if(!bt[i+1])
10238 {
b9b61529 10239 if(itype[i]==ALU||itype[i]==MOV||itype[i]==LOAD||itype[i]==SHIFTIMM||itype[i]==IMM16
10240 ||((itype[i]==COP1||itype[i]==COP2)&&opcode2[i]<3))
57871462 10241 {
10242 if(rs1[i+1]) {
10243 if((hr=get_reg(regs[i+1].regmap,rs1[i+1]))>=0)
10244 {
10245 if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
10246 {
10247 regs[i].regmap[hr]=regs[i+1].regmap[hr];
10248 regmap_pre[i+1][hr]=regs[i+1].regmap[hr];
10249 regs[i+1].regmap_entry[hr]=regs[i+1].regmap[hr];
10250 regs[i].isconst&=~(1<<hr);
10251 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10252 constmap[i][hr]=constmap[i+1][hr];
10253 regs[i+1].wasdirty&=~(1<<hr);
10254 regs[i].dirty&=~(1<<hr);
10255 }
10256 }
10257 }
10258 if(rs2[i+1]) {
10259 if((hr=get_reg(regs[i+1].regmap,rs2[i+1]))>=0)
10260 {
10261 if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
10262 {
10263 regs[i].regmap[hr]=regs[i+1].regmap[hr];
10264 regmap_pre[i+1][hr]=regs[i+1].regmap[hr];
10265 regs[i+1].regmap_entry[hr]=regs[i+1].regmap[hr];
10266 regs[i].isconst&=~(1<<hr);
10267 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10268 constmap[i][hr]=constmap[i+1][hr];
10269 regs[i+1].wasdirty&=~(1<<hr);
10270 regs[i].dirty&=~(1<<hr);
10271 }
10272 }
10273 }
10274 if(itype[i+1]==LOAD&&rs1[i+1]&&get_reg(regs[i+1].regmap,rs1[i+1])<0) {
10275 if((hr=get_reg(regs[i+1].regmap,rt1[i+1]))>=0)
10276 {
10277 if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
10278 {
10279 regs[i].regmap[hr]=rs1[i+1];
10280 regmap_pre[i+1][hr]=rs1[i+1];
10281 regs[i+1].regmap_entry[hr]=rs1[i+1];
10282 regs[i].isconst&=~(1<<hr);
10283 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10284 constmap[i][hr]=constmap[i+1][hr];
10285 regs[i+1].wasdirty&=~(1<<hr);
10286 regs[i].dirty&=~(1<<hr);
10287 }
10288 }
10289 }
10290 if(lt1[i+1]&&get_reg(regs[i+1].regmap,rs1[i+1])<0) {
10291 if((hr=get_reg(regs[i+1].regmap,rt1[i+1]))>=0)
10292 {
10293 if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
10294 {
10295 regs[i].regmap[hr]=rs1[i+1];
10296 regmap_pre[i+1][hr]=rs1[i+1];
10297 regs[i+1].regmap_entry[hr]=rs1[i+1];
10298 regs[i].isconst&=~(1<<hr);
10299 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10300 constmap[i][hr]=constmap[i+1][hr];
10301 regs[i+1].wasdirty&=~(1<<hr);
10302 regs[i].dirty&=~(1<<hr);
10303 }
10304 }
10305 }
10306 #ifndef HOST_IMM_ADDR32
b9b61529 10307 if(itype[i+1]==LOAD||itype[i+1]==LOADLR||itype[i+1]==STORE||itype[i+1]==STORELR||itype[i+1]==C1LS||itype[i+1]==C2LS) {
57871462 10308 hr=get_reg(regs[i+1].regmap,TLREG);
10309 if(hr>=0) {
10310 int sr=get_reg(regs[i+1].regmap,rs1[i+1]);
10311 if(sr>=0&&((regs[i+1].wasconst>>sr)&1)) {
10312 int nr;
10313 if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
10314 {
10315 regs[i].regmap[hr]=MGEN1+((i+1)&1);
10316 regmap_pre[i+1][hr]=MGEN1+((i+1)&1);
10317 regs[i+1].regmap_entry[hr]=MGEN1+((i+1)&1);
10318 regs[i].isconst&=~(1<<hr);
10319 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10320 constmap[i][hr]=constmap[i+1][hr];
10321 regs[i+1].wasdirty&=~(1<<hr);
10322 regs[i].dirty&=~(1<<hr);
10323 }
10324 else if((nr=get_reg2(regs[i].regmap,regs[i+1].regmap,-1))>=0)
10325 {
10326 // move it to another register
10327 regs[i+1].regmap[hr]=-1;
10328 regmap_pre[i+2][hr]=-1;
10329 regs[i+1].regmap[nr]=TLREG;
10330 regmap_pre[i+2][nr]=TLREG;
10331 regs[i].regmap[nr]=MGEN1+((i+1)&1);
10332 regmap_pre[i+1][nr]=MGEN1+((i+1)&1);
10333 regs[i+1].regmap_entry[nr]=MGEN1+((i+1)&1);
10334 regs[i].isconst&=~(1<<nr);
10335 regs[i+1].isconst&=~(1<<nr);
10336 regs[i].dirty&=~(1<<nr);
10337 regs[i+1].wasdirty&=~(1<<nr);
10338 regs[i+1].dirty&=~(1<<nr);
10339 regs[i+2].wasdirty&=~(1<<nr);
10340 }
10341 }
10342 }
10343 }
10344 #endif
b9b61529 10345 if(itype[i+1]==STORE||itype[i+1]==STORELR
10346 ||(opcode[i+1]&0x3b)==0x39||(opcode[i+1]&0x3b)==0x3a) { // SB/SH/SW/SD/SWC1/SDC1/SWC2/SDC2
57871462 10347 if(get_reg(regs[i+1].regmap,rs1[i+1])<0) {
10348 hr=get_reg2(regs[i].regmap,regs[i+1].regmap,-1);
10349 if(hr<0) hr=get_reg(regs[i+1].regmap,-1);
10350 else {regs[i+1].regmap[hr]=AGEN1+((i+1)&1);regs[i+1].isconst&=~(1<<hr);}
10351 assert(hr>=0);
10352 if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
10353 {
10354 regs[i].regmap[hr]=rs1[i+1];
10355 regmap_pre[i+1][hr]=rs1[i+1];
10356 regs[i+1].regmap_entry[hr]=rs1[i+1];
10357 regs[i].isconst&=~(1<<hr);
10358 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10359 constmap[i][hr]=constmap[i+1][hr];
10360 regs[i+1].wasdirty&=~(1<<hr);
10361 regs[i].dirty&=~(1<<hr);
10362 }
10363 }
10364 }
b9b61529 10365 if(itype[i+1]==LOADLR||(opcode[i+1]&0x3b)==0x31||(opcode[i+1]&0x3b)==0x32) { // LWC1/LDC1, LWC2/LDC2
57871462 10366 if(get_reg(regs[i+1].regmap,rs1[i+1])<0) {
10367 int nr;
10368 hr=get_reg(regs[i+1].regmap,FTEMP);
10369 assert(hr>=0);
10370 if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
10371 {
10372 regs[i].regmap[hr]=rs1[i+1];
10373 regmap_pre[i+1][hr]=rs1[i+1];
10374 regs[i+1].regmap_entry[hr]=rs1[i+1];
10375 regs[i].isconst&=~(1<<hr);
10376 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10377 constmap[i][hr]=constmap[i+1][hr];
10378 regs[i+1].wasdirty&=~(1<<hr);
10379 regs[i].dirty&=~(1<<hr);
10380 }
10381 else if((nr=get_reg2(regs[i].regmap,regs[i+1].regmap,-1))>=0)
10382 {
10383 // move it to another register
10384 regs[i+1].regmap[hr]=-1;
10385 regmap_pre[i+2][hr]=-1;
10386 regs[i+1].regmap[nr]=FTEMP;
10387 regmap_pre[i+2][nr]=FTEMP;
10388 regs[i].regmap[nr]=rs1[i+1];
10389 regmap_pre[i+1][nr]=rs1[i+1];
10390 regs[i+1].regmap_entry[nr]=rs1[i+1];
10391 regs[i].isconst&=~(1<<nr);
10392 regs[i+1].isconst&=~(1<<nr);
10393 regs[i].dirty&=~(1<<nr);
10394 regs[i+1].wasdirty&=~(1<<nr);
10395 regs[i+1].dirty&=~(1<<nr);
10396 regs[i+2].wasdirty&=~(1<<nr);
10397 }
10398 }
10399 }
b9b61529 10400 if(itype[i+1]==LOAD||itype[i+1]==LOADLR||itype[i+1]==STORE||itype[i+1]==STORELR/*||itype[i+1]==C1LS||||itype[i+1]==C2LS*/) {
57871462 10401 if(itype[i+1]==LOAD)
10402 hr=get_reg(regs[i+1].regmap,rt1[i+1]);
b9b61529 10403 if(itype[i+1]==LOADLR||(opcode[i+1]&0x3b)==0x31||(opcode[i+1]&0x3b)==0x32) // LWC1/LDC1, LWC2/LDC2
57871462 10404 hr=get_reg(regs[i+1].regmap,FTEMP);
b9b61529 10405 if(itype[i+1]==STORE||itype[i+1]==STORELR||(opcode[i+1]&0x3b)==0x39||(opcode[i+1]&0x3b)==0x3a) { // SWC1/SDC1/SWC2/SDC2
57871462 10406 hr=get_reg(regs[i+1].regmap,AGEN1+((i+1)&1));
10407 if(hr<0) hr=get_reg(regs[i+1].regmap,-1);
10408 }
10409 if(hr>=0&&regs[i].regmap[hr]<0) {
10410 int rs=get_reg(regs[i+1].regmap,rs1[i+1]);
10411 if(rs>=0&&((regs[i+1].wasconst>>rs)&1)) {
10412 regs[i].regmap[hr]=AGEN1+((i+1)&1);
10413 regmap_pre[i+1][hr]=AGEN1+((i+1)&1);
10414 regs[i+1].regmap_entry[hr]=AGEN1+((i+1)&1);
10415 regs[i].isconst&=~(1<<hr);
10416 regs[i+1].wasdirty&=~(1<<hr);
10417 regs[i].dirty&=~(1<<hr);
10418 }
10419 }
10420 }
10421 }
10422 }
10423 }
10424 }
10425
10426 /* Pass 6 - Optimize clean/dirty state */
10427 clean_registers(0,slen-1,1);
10428
10429 /* Pass 7 - Identify 32-bit registers */
a28c6ce8 10430#ifndef FORCE32
57871462 10431 provisional_r32();
10432
10433 u_int r32=0;
10434
10435 for (i=slen-1;i>=0;i--)
10436 {
10437 int hr;
10438 if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
10439 {
10440 if(ba[i]<start || ba[i]>=(start+slen*4))
10441 {
10442 // Branch out of this block, don't need anything
10443 r32=0;
10444 }
10445 else
10446 {
10447 // Internal branch
10448 // Need whatever matches the target
10449 // (and doesn't get overwritten by the delay slot instruction)
10450 r32=0;
10451 int t=(ba[i]-start)>>2;
10452 if(ba[i]>start+i*4) {
10453 // Forward branch
10454 if(!(requires_32bit[t]&~regs[i].was32))
10455 r32|=requires_32bit[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
10456 }else{
10457 // Backward branch
10458 //if(!(regs[t].was32&~unneeded_reg_upper[t]&~regs[i].was32))
10459 // r32|=regs[t].was32&~unneeded_reg_upper[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
10460 if(!(pr32[t]&~regs[i].was32))
10461 r32|=pr32[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
10462 }
10463 }
10464 // Conditional branch may need registers for following instructions
10465 if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000)
10466 {
10467 if(i<slen-2) {
10468 r32|=requires_32bit[i+2];
10469 r32&=regs[i].was32;
10470 // Mark this address as a branch target since it may be called
10471 // upon return from interrupt
10472 bt[i+2]=1;
10473 }
10474 }
10475 // Merge in delay slot
10476 if(!likely[i]) {
10477 // These are overwritten unless the branch is "likely"
10478 // and the delay slot is nullified if not taken
10479 r32&=~(1LL<<rt1[i+1]);
10480 r32&=~(1LL<<rt2[i+1]);
10481 }
10482 // Assume these are needed (delay slot)
10483 if(us1[i+1]>0)
10484 {
10485 if((regs[i].was32>>us1[i+1])&1) r32|=1LL<<us1[i+1];
10486 }
10487 if(us2[i+1]>0)
10488 {
10489 if((regs[i].was32>>us2[i+1])&1) r32|=1LL<<us2[i+1];
10490 }
10491 if(dep1[i+1]&&!((unneeded_reg_upper[i]>>dep1[i+1])&1))
10492 {
10493 if((regs[i].was32>>dep1[i+1])&1) r32|=1LL<<dep1[i+1];
10494 }
10495 if(dep2[i+1]&&!((unneeded_reg_upper[i]>>dep2[i+1])&1))
10496 {
10497 if((regs[i].was32>>dep2[i+1])&1) r32|=1LL<<dep2[i+1];
10498 }
10499 }
1e973cb0 10500 else if(itype[i]==SYSCALL||itype[i]==HLECALL||itype[i]==INTCALL)
57871462 10501 {
10502 // SYSCALL instruction (software interrupt)
10503 r32=0;
10504 }
10505 else if(itype[i]==COP0 && (source[i]&0x3f)==0x18)
10506 {
10507 // ERET instruction (return from interrupt)
10508 r32=0;
10509 }
10510 // Check 32 bits
10511 r32&=~(1LL<<rt1[i]);
10512 r32&=~(1LL<<rt2[i]);
10513 if(us1[i]>0)
10514 {
10515 if((regs[i].was32>>us1[i])&1) r32|=1LL<<us1[i];
10516 }
10517 if(us2[i]>0)
10518 {
10519 if((regs[i].was32>>us2[i])&1) r32|=1LL<<us2[i];
10520 }
10521 if(dep1[i]&&!((unneeded_reg_upper[i]>>dep1[i])&1))
10522 {
10523 if((regs[i].was32>>dep1[i])&1) r32|=1LL<<dep1[i];
10524 }
10525 if(dep2[i]&&!((unneeded_reg_upper[i]>>dep2[i])&1))
10526 {
10527 if((regs[i].was32>>dep2[i])&1) r32|=1LL<<dep2[i];
10528 }
10529 requires_32bit[i]=r32;
10530
10531 // Dirty registers which are 32-bit, require 32-bit input
10532 // as they will be written as 32-bit values
10533 for(hr=0;hr<HOST_REGS;hr++)
10534 {
10535 if(regs[i].regmap_entry[hr]>0&&regs[i].regmap_entry[hr]<64) {
10536 if((regs[i].was32>>regs[i].regmap_entry[hr])&(regs[i].wasdirty>>hr)&1) {
10537 if(!((unneeded_reg_upper[i]>>regs[i].regmap_entry[hr])&1))
10538 requires_32bit[i]|=1LL<<regs[i].regmap_entry[hr];
10539 }
10540 }
10541 }
10542 //requires_32bit[i]=is32[i]&~unneeded_reg_upper[i]; // DEBUG
10543 }
04fd948a 10544#else
10545 for (i=slen-1;i>=0;i--)
10546 {
10547 if(itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
10548 {
10549 // Conditional branch
10550 if((source[i]>>16)!=0x1000&&i<slen-2) {
10551 // Mark this address as a branch target since it may be called
10552 // upon return from interrupt
10553 bt[i+2]=1;
10554 }
10555 }
10556 }
a28c6ce8 10557#endif
57871462 10558
10559 if(itype[slen-1]==SPAN) {
10560 bt[slen-1]=1; // Mark as a branch target so instruction can restart after exception
10561 }
10562
10563 /* Debug/disassembly */
10564 if((void*)assem_debug==(void*)printf)
10565 for(i=0;i<slen;i++)
10566 {
10567 printf("U:");
10568 int r;
10569 for(r=1;r<=CCREG;r++) {
10570 if((unneeded_reg[i]>>r)&1) {
10571 if(r==HIREG) printf(" HI");
10572 else if(r==LOREG) printf(" LO");
10573 else printf(" r%d",r);
10574 }
10575 }
90ae6d4e 10576#ifndef FORCE32
57871462 10577 printf(" UU:");
10578 for(r=1;r<=CCREG;r++) {
10579 if(((unneeded_reg_upper[i]&~unneeded_reg[i])>>r)&1) {
10580 if(r==HIREG) printf(" HI");
10581 else if(r==LOREG) printf(" LO");
10582 else printf(" r%d",r);
10583 }
10584 }
10585 printf(" 32:");
10586 for(r=0;r<=CCREG;r++) {
10587 //if(((is32[i]>>r)&(~unneeded_reg[i]>>r))&1) {
10588 if((regs[i].was32>>r)&1) {
10589 if(r==CCREG) printf(" CC");
10590 else if(r==HIREG) printf(" HI");
10591 else if(r==LOREG) printf(" LO");
10592 else printf(" r%d",r);
10593 }
10594 }
90ae6d4e 10595#endif
57871462 10596 printf("\n");
10597 #if defined(__i386__) || defined(__x86_64__)
10598 printf("pre: eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",regmap_pre[i][0],regmap_pre[i][1],regmap_pre[i][2],regmap_pre[i][3],regmap_pre[i][5],regmap_pre[i][6],regmap_pre[i][7]);
10599 #endif
10600 #ifdef __arm__
10601 printf("pre: r0=%d r1=%d r2=%d r3=%d r4=%d r5=%d r6=%d r7=%d r8=%d r9=%d r10=%d r12=%d\n",regmap_pre[i][0],regmap_pre[i][1],regmap_pre[i][2],regmap_pre[i][3],regmap_pre[i][4],regmap_pre[i][5],regmap_pre[i][6],regmap_pre[i][7],regmap_pre[i][8],regmap_pre[i][9],regmap_pre[i][10],regmap_pre[i][12]);
10602 #endif
10603 printf("needs: ");
10604 if(needed_reg[i]&1) printf("eax ");
10605 if((needed_reg[i]>>1)&1) printf("ecx ");
10606 if((needed_reg[i]>>2)&1) printf("edx ");
10607 if((needed_reg[i]>>3)&1) printf("ebx ");
10608 if((needed_reg[i]>>5)&1) printf("ebp ");
10609 if((needed_reg[i]>>6)&1) printf("esi ");
10610 if((needed_reg[i]>>7)&1) printf("edi ");
10611 printf("r:");
10612 for(r=0;r<=CCREG;r++) {
10613 //if(((requires_32bit[i]>>r)&(~unneeded_reg[i]>>r))&1) {
10614 if((requires_32bit[i]>>r)&1) {
10615 if(r==CCREG) printf(" CC");
10616 else if(r==HIREG) printf(" HI");
10617 else if(r==LOREG) printf(" LO");
10618 else printf(" r%d",r);
10619 }
10620 }
10621 printf("\n");
10622 /*printf("pr:");
10623 for(r=0;r<=CCREG;r++) {
10624 //if(((requires_32bit[i]>>r)&(~unneeded_reg[i]>>r))&1) {
10625 if((pr32[i]>>r)&1) {
10626 if(r==CCREG) printf(" CC");
10627 else if(r==HIREG) printf(" HI");
10628 else if(r==LOREG) printf(" LO");
10629 else printf(" r%d",r);
10630 }
10631 }
10632 if(pr32[i]!=requires_32bit[i]) printf(" OOPS");
10633 printf("\n");*/
10634 #if defined(__i386__) || defined(__x86_64__)
10635 printf("entry: eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",regs[i].regmap_entry[0],regs[i].regmap_entry[1],regs[i].regmap_entry[2],regs[i].regmap_entry[3],regs[i].regmap_entry[5],regs[i].regmap_entry[6],regs[i].regmap_entry[7]);
10636 printf("dirty: ");
10637 if(regs[i].wasdirty&1) printf("eax ");
10638 if((regs[i].wasdirty>>1)&1) printf("ecx ");
10639 if((regs[i].wasdirty>>2)&1) printf("edx ");
10640 if((regs[i].wasdirty>>3)&1) printf("ebx ");
10641 if((regs[i].wasdirty>>5)&1) printf("ebp ");
10642 if((regs[i].wasdirty>>6)&1) printf("esi ");
10643 if((regs[i].wasdirty>>7)&1) printf("edi ");
10644 #endif
10645 #ifdef __arm__
10646 printf("entry: r0=%d r1=%d r2=%d r3=%d r4=%d r5=%d r6=%d r7=%d r8=%d r9=%d r10=%d r12=%d\n",regs[i].regmap_entry[0],regs[i].regmap_entry[1],regs[i].regmap_entry[2],regs[i].regmap_entry[3],regs[i].regmap_entry[4],regs[i].regmap_entry[5],regs[i].regmap_entry[6],regs[i].regmap_entry[7],regs[i].regmap_entry[8],regs[i].regmap_entry[9],regs[i].regmap_entry[10],regs[i].regmap_entry[12]);
10647 printf("dirty: ");
10648 if(regs[i].wasdirty&1) printf("r0 ");
10649 if((regs[i].wasdirty>>1)&1) printf("r1 ");
10650 if((regs[i].wasdirty>>2)&1) printf("r2 ");
10651 if((regs[i].wasdirty>>3)&1) printf("r3 ");
10652 if((regs[i].wasdirty>>4)&1) printf("r4 ");
10653 if((regs[i].wasdirty>>5)&1) printf("r5 ");
10654 if((regs[i].wasdirty>>6)&1) printf("r6 ");
10655 if((regs[i].wasdirty>>7)&1) printf("r7 ");
10656 if((regs[i].wasdirty>>8)&1) printf("r8 ");
10657 if((regs[i].wasdirty>>9)&1) printf("r9 ");
10658 if((regs[i].wasdirty>>10)&1) printf("r10 ");
10659 if((regs[i].wasdirty>>12)&1) printf("r12 ");
10660 #endif
10661 printf("\n");
10662 disassemble_inst(i);
10663 //printf ("ccadj[%d] = %d\n",i,ccadj[i]);
10664 #if defined(__i386__) || defined(__x86_64__)
10665 printf("eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d dirty: ",regs[i].regmap[0],regs[i].regmap[1],regs[i].regmap[2],regs[i].regmap[3],regs[i].regmap[5],regs[i].regmap[6],regs[i].regmap[7]);
10666 if(regs[i].dirty&1) printf("eax ");
10667 if((regs[i].dirty>>1)&1) printf("ecx ");
10668 if((regs[i].dirty>>2)&1) printf("edx ");
10669 if((regs[i].dirty>>3)&1) printf("ebx ");
10670 if((regs[i].dirty>>5)&1) printf("ebp ");
10671 if((regs[i].dirty>>6)&1) printf("esi ");
10672 if((regs[i].dirty>>7)&1) printf("edi ");
10673 #endif
10674 #ifdef __arm__
10675 printf("r0=%d r1=%d r2=%d r3=%d r4=%d r5=%d r6=%d r7=%d r8=%d r9=%d r10=%d r12=%d dirty: ",regs[i].regmap[0],regs[i].regmap[1],regs[i].regmap[2],regs[i].regmap[3],regs[i].regmap[4],regs[i].regmap[5],regs[i].regmap[6],regs[i].regmap[7],regs[i].regmap[8],regs[i].regmap[9],regs[i].regmap[10],regs[i].regmap[12]);
10676 if(regs[i].dirty&1) printf("r0 ");
10677 if((regs[i].dirty>>1)&1) printf("r1 ");
10678 if((regs[i].dirty>>2)&1) printf("r2 ");
10679 if((regs[i].dirty>>3)&1) printf("r3 ");
10680 if((regs[i].dirty>>4)&1) printf("r4 ");
10681 if((regs[i].dirty>>5)&1) printf("r5 ");
10682 if((regs[i].dirty>>6)&1) printf("r6 ");
10683 if((regs[i].dirty>>7)&1) printf("r7 ");
10684 if((regs[i].dirty>>8)&1) printf("r8 ");
10685 if((regs[i].dirty>>9)&1) printf("r9 ");
10686 if((regs[i].dirty>>10)&1) printf("r10 ");
10687 if((regs[i].dirty>>12)&1) printf("r12 ");
10688 #endif
10689 printf("\n");
10690 if(regs[i].isconst) {
10691 printf("constants: ");
10692 #if defined(__i386__) || defined(__x86_64__)
10693 if(regs[i].isconst&1) printf("eax=%x ",(int)constmap[i][0]);
10694 if((regs[i].isconst>>1)&1) printf("ecx=%x ",(int)constmap[i][1]);
10695 if((regs[i].isconst>>2)&1) printf("edx=%x ",(int)constmap[i][2]);
10696 if((regs[i].isconst>>3)&1) printf("ebx=%x ",(int)constmap[i][3]);
10697 if((regs[i].isconst>>5)&1) printf("ebp=%x ",(int)constmap[i][5]);
10698 if((regs[i].isconst>>6)&1) printf("esi=%x ",(int)constmap[i][6]);
10699 if((regs[i].isconst>>7)&1) printf("edi=%x ",(int)constmap[i][7]);
10700 #endif
10701 #ifdef __arm__
10702 if(regs[i].isconst&1) printf("r0=%x ",(int)constmap[i][0]);
10703 if((regs[i].isconst>>1)&1) printf("r1=%x ",(int)constmap[i][1]);
10704 if((regs[i].isconst>>2)&1) printf("r2=%x ",(int)constmap[i][2]);
10705 if((regs[i].isconst>>3)&1) printf("r3=%x ",(int)constmap[i][3]);
10706 if((regs[i].isconst>>4)&1) printf("r4=%x ",(int)constmap[i][4]);
10707 if((regs[i].isconst>>5)&1) printf("r5=%x ",(int)constmap[i][5]);
10708 if((regs[i].isconst>>6)&1) printf("r6=%x ",(int)constmap[i][6]);
10709 if((regs[i].isconst>>7)&1) printf("r7=%x ",(int)constmap[i][7]);
10710 if((regs[i].isconst>>8)&1) printf("r8=%x ",(int)constmap[i][8]);
10711 if((regs[i].isconst>>9)&1) printf("r9=%x ",(int)constmap[i][9]);
10712 if((regs[i].isconst>>10)&1) printf("r10=%x ",(int)constmap[i][10]);
10713 if((regs[i].isconst>>12)&1) printf("r12=%x ",(int)constmap[i][12]);
10714 #endif
10715 printf("\n");
10716 }
90ae6d4e 10717#ifndef FORCE32
57871462 10718 printf(" 32:");
10719 for(r=0;r<=CCREG;r++) {
10720 if((regs[i].is32>>r)&1) {
10721 if(r==CCREG) printf(" CC");
10722 else if(r==HIREG) printf(" HI");
10723 else if(r==LOREG) printf(" LO");
10724 else printf(" r%d",r);
10725 }
10726 }
10727 printf("\n");
90ae6d4e 10728#endif
57871462 10729 /*printf(" p32:");
10730 for(r=0;r<=CCREG;r++) {
10731 if((p32[i]>>r)&1) {
10732 if(r==CCREG) printf(" CC");
10733 else if(r==HIREG) printf(" HI");
10734 else if(r==LOREG) printf(" LO");
10735 else printf(" r%d",r);
10736 }
10737 }
10738 if(p32[i]!=regs[i].is32) printf(" NO MATCH\n");
10739 else printf("\n");*/
10740 if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP) {
10741 #if defined(__i386__) || defined(__x86_64__)
10742 printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d dirty: ",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
10743 if(branch_regs[i].dirty&1) printf("eax ");
10744 if((branch_regs[i].dirty>>1)&1) printf("ecx ");
10745 if((branch_regs[i].dirty>>2)&1) printf("edx ");
10746 if((branch_regs[i].dirty>>3)&1) printf("ebx ");
10747 if((branch_regs[i].dirty>>5)&1) printf("ebp ");
10748 if((branch_regs[i].dirty>>6)&1) printf("esi ");
10749 if((branch_regs[i].dirty>>7)&1) printf("edi ");
10750 #endif
10751 #ifdef __arm__
10752 printf("branch(%d): r0=%d r1=%d r2=%d r3=%d r4=%d r5=%d r6=%d r7=%d r8=%d r9=%d r10=%d r12=%d dirty: ",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[4],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7],branch_regs[i].regmap[8],branch_regs[i].regmap[9],branch_regs[i].regmap[10],branch_regs[i].regmap[12]);
10753 if(branch_regs[i].dirty&1) printf("r0 ");
10754 if((branch_regs[i].dirty>>1)&1) printf("r1 ");
10755 if((branch_regs[i].dirty>>2)&1) printf("r2 ");
10756 if((branch_regs[i].dirty>>3)&1) printf("r3 ");
10757 if((branch_regs[i].dirty>>4)&1) printf("r4 ");
10758 if((branch_regs[i].dirty>>5)&1) printf("r5 ");
10759 if((branch_regs[i].dirty>>6)&1) printf("r6 ");
10760 if((branch_regs[i].dirty>>7)&1) printf("r7 ");
10761 if((branch_regs[i].dirty>>8)&1) printf("r8 ");
10762 if((branch_regs[i].dirty>>9)&1) printf("r9 ");
10763 if((branch_regs[i].dirty>>10)&1) printf("r10 ");
10764 if((branch_regs[i].dirty>>12)&1) printf("r12 ");
10765 #endif
90ae6d4e 10766#ifndef FORCE32
57871462 10767 printf(" 32:");
10768 for(r=0;r<=CCREG;r++) {
10769 if((branch_regs[i].is32>>r)&1) {
10770 if(r==CCREG) printf(" CC");
10771 else if(r==HIREG) printf(" HI");
10772 else if(r==LOREG) printf(" LO");
10773 else printf(" r%d",r);
10774 }
10775 }
10776 printf("\n");
90ae6d4e 10777#endif
57871462 10778 }
10779 }
10780
10781 /* Pass 8 - Assembly */
10782 linkcount=0;stubcount=0;
10783 ds=0;is_delayslot=0;
10784 cop1_usable=0;
10785 uint64_t is32_pre=0;
10786 u_int dirty_pre=0;
10787 u_int beginning=(u_int)out;
10788 if((u_int)addr&1) {
10789 ds=1;
10790 pagespan_ds();
10791 }
9ad4d757 10792 u_int instr_addr0_override=0;
10793
10794#ifdef PCSX
10795 if (start == 0x80030000) {
10796 // nasty hack for fastbios thing
10797 instr_addr0_override=(u_int)out;
10798 emit_movimm(start,0);
10799 emit_readword((int)&pcaddr,1);
10800 emit_writeword(0,(int)&pcaddr);
10801 emit_cmp(0,1);
10802 emit_jne((int)new_dyna_leave);
10803 }
10804#endif
57871462 10805 for(i=0;i<slen;i++)
10806 {
10807 //if(ds) printf("ds: ");
10808 if((void*)assem_debug==(void*)printf) disassemble_inst(i);
10809 if(ds) {
10810 ds=0; // Skip delay slot
10811 if(bt[i]) assem_debug("OOPS - branch into delay slot\n");
10812 instr_addr[i]=0;
10813 } else {
10814 #ifndef DESTRUCTIVE_WRITEBACK
10815 if(i<2||(itype[i-2]!=UJUMP&&itype[i-2]!=RJUMP&&(source[i-2]>>16)!=0x1000))
10816 {
10817 wb_sx(regmap_pre[i],regs[i].regmap_entry,regs[i].wasdirty,is32_pre,regs[i].was32,
10818 unneeded_reg[i],unneeded_reg_upper[i]);
10819 wb_valid(regmap_pre[i],regs[i].regmap_entry,dirty_pre,regs[i].wasdirty,is32_pre,
10820 unneeded_reg[i],unneeded_reg_upper[i]);
10821 }
f776eb14 10822 if((itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)&&!likely[i]) {
10823 is32_pre=branch_regs[i].is32;
10824 dirty_pre=branch_regs[i].dirty;
10825 }else{
10826 is32_pre=regs[i].is32;
10827 dirty_pre=regs[i].dirty;
10828 }
57871462 10829 #endif
10830 // write back
10831 if(i<2||(itype[i-2]!=UJUMP&&itype[i-2]!=RJUMP&&(source[i-2]>>16)!=0x1000))
10832 {
10833 wb_invalidate(regmap_pre[i],regs[i].regmap_entry,regs[i].wasdirty,regs[i].was32,
10834 unneeded_reg[i],unneeded_reg_upper[i]);
10835 loop_preload(regmap_pre[i],regs[i].regmap_entry);
10836 }
10837 // branch target entry point
10838 instr_addr[i]=(u_int)out;
10839 assem_debug("<->\n");
10840 // load regs
10841 if(regs[i].regmap_entry[HOST_CCREG]==CCREG&&regs[i].regmap[HOST_CCREG]!=CCREG)
10842 wb_register(CCREG,regs[i].regmap_entry,regs[i].wasdirty,regs[i].was32);
10843 load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,rs1[i],rs2[i]);
10844 address_generation(i,&regs[i],regs[i].regmap_entry);
10845 load_consts(regmap_pre[i],regs[i].regmap,regs[i].was32,i);
10846 if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
10847 {
10848 // Load the delay slot registers if necessary
4ef8f67d 10849 if(rs1[i+1]!=rs1[i]&&rs1[i+1]!=rs2[i]&&(rs1[i+1]!=rt1[i]||rt1[i]==0))
57871462 10850 load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,rs1[i+1],rs1[i+1]);
4ef8f67d 10851 if(rs2[i+1]!=rs1[i+1]&&rs2[i+1]!=rs1[i]&&rs2[i+1]!=rs2[i]&&(rs2[i+1]!=rt1[i]||rt1[i]==0))
57871462 10852 load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,rs2[i+1],rs2[i+1]);
b9b61529 10853 if(itype[i+1]==STORE||itype[i+1]==STORELR||(opcode[i+1]&0x3b)==0x39||(opcode[i+1]&0x3b)==0x3a)
57871462 10854 load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,INVCP,INVCP);
10855 }
10856 else if(i+1<slen)
10857 {
10858 // Preload registers for following instruction
10859 if(rs1[i+1]!=rs1[i]&&rs1[i+1]!=rs2[i])
10860 if(rs1[i+1]!=rt1[i]&&rs1[i+1]!=rt2[i])
10861 load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,rs1[i+1],rs1[i+1]);
10862 if(rs2[i+1]!=rs1[i+1]&&rs2[i+1]!=rs1[i]&&rs2[i+1]!=rs2[i])
10863 if(rs2[i+1]!=rt1[i]&&rs2[i+1]!=rt2[i])
10864 load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,rs2[i+1],rs2[i+1]);
10865 }
10866 // TODO: if(is_ooo(i)) address_generation(i+1);
10867 if(itype[i]==CJUMP||itype[i]==FJUMP)
10868 load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,CCREG,CCREG);
b9b61529 10869 if(itype[i]==STORE||itype[i]==STORELR||(opcode[i]&0x3b)==0x39||(opcode[i]&0x3b)==0x3a)
57871462 10870 load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,INVCP,INVCP);
10871 if(bt[i]) cop1_usable=0;
10872 // assemble
10873 switch(itype[i]) {
10874 case ALU:
10875 alu_assemble(i,&regs[i]);break;
10876 case IMM16:
10877 imm16_assemble(i,&regs[i]);break;
10878 case SHIFT:
10879 shift_assemble(i,&regs[i]);break;
10880 case SHIFTIMM:
10881 shiftimm_assemble(i,&regs[i]);break;
10882 case LOAD:
10883 load_assemble(i,&regs[i]);break;
10884 case LOADLR:
10885 loadlr_assemble(i,&regs[i]);break;
10886 case STORE:
10887 store_assemble(i,&regs[i]);break;
10888 case STORELR:
10889 storelr_assemble(i,&regs[i]);break;
10890 case COP0:
10891 cop0_assemble(i,&regs[i]);break;
10892 case COP1:
10893 cop1_assemble(i,&regs[i]);break;
10894 case C1LS:
10895 c1ls_assemble(i,&regs[i]);break;
b9b61529 10896 case COP2:
10897 cop2_assemble(i,&regs[i]);break;
10898 case C2LS:
10899 c2ls_assemble(i,&regs[i]);break;
10900 case C2OP:
10901 c2op_assemble(i,&regs[i]);break;
57871462 10902 case FCONV:
10903 fconv_assemble(i,&regs[i]);break;
10904 case FLOAT:
10905 float_assemble(i,&regs[i]);break;
10906 case FCOMP:
10907 fcomp_assemble(i,&regs[i]);break;
10908 case MULTDIV:
10909 multdiv_assemble(i,&regs[i]);break;
10910 case MOV:
10911 mov_assemble(i,&regs[i]);break;
10912 case SYSCALL:
10913 syscall_assemble(i,&regs[i]);break;
7139f3c8 10914 case HLECALL:
10915 hlecall_assemble(i,&regs[i]);break;
1e973cb0 10916 case INTCALL:
10917 intcall_assemble(i,&regs[i]);break;
57871462 10918 case UJUMP:
10919 ujump_assemble(i,&regs[i]);ds=1;break;
10920 case RJUMP:
10921 rjump_assemble(i,&regs[i]);ds=1;break;
10922 case CJUMP:
10923 cjump_assemble(i,&regs[i]);ds=1;break;
10924 case SJUMP:
10925 sjump_assemble(i,&regs[i]);ds=1;break;
10926 case FJUMP:
10927 fjump_assemble(i,&regs[i]);ds=1;break;
10928 case SPAN:
10929 pagespan_assemble(i,&regs[i]);break;
10930 }
10931 if(itype[i]==UJUMP||itype[i]==RJUMP||(source[i]>>16)==0x1000)
10932 literal_pool(1024);
10933 else
10934 literal_pool_jumpover(256);
10935 }
10936 }
10937 //assert(itype[i-2]==UJUMP||itype[i-2]==RJUMP||(source[i-2]>>16)==0x1000);
10938 // If the block did not end with an unconditional branch,
10939 // add a jump to the next instruction.
10940 if(i>1) {
10941 if(itype[i-2]!=UJUMP&&itype[i-2]!=RJUMP&&(source[i-2]>>16)!=0x1000&&itype[i-1]!=SPAN) {
10942 assert(itype[i-1]!=UJUMP&&itype[i-1]!=CJUMP&&itype[i-1]!=SJUMP&&itype[i-1]!=RJUMP&&itype[i-1]!=FJUMP);
10943 assert(i==slen);
10944 if(itype[i-2]!=CJUMP&&itype[i-2]!=SJUMP&&itype[i-2]!=FJUMP) {
10945 store_regs_bt(regs[i-1].regmap,regs[i-1].is32,regs[i-1].dirty,start+i*4);
10946 if(regs[i-1].regmap[HOST_CCREG]!=CCREG)
10947 emit_loadreg(CCREG,HOST_CCREG);
10948 emit_addimm(HOST_CCREG,CLOCK_DIVIDER*(ccadj[i-1]+1),HOST_CCREG);
10949 }
10950 else if(!likely[i-2])
10951 {
10952 store_regs_bt(branch_regs[i-2].regmap,branch_regs[i-2].is32,branch_regs[i-2].dirty,start+i*4);
10953 assert(branch_regs[i-2].regmap[HOST_CCREG]==CCREG);
10954 }
10955 else
10956 {
10957 store_regs_bt(regs[i-2].regmap,regs[i-2].is32,regs[i-2].dirty,start+i*4);
10958 assert(regs[i-2].regmap[HOST_CCREG]==CCREG);
10959 }
10960 add_to_linker((int)out,start+i*4,0);
10961 emit_jmp(0);
10962 }
10963 }
10964 else
10965 {
10966 assert(i>0);
10967 assert(itype[i-1]!=UJUMP&&itype[i-1]!=CJUMP&&itype[i-1]!=SJUMP&&itype[i-1]!=RJUMP&&itype[i-1]!=FJUMP);
10968 store_regs_bt(regs[i-1].regmap,regs[i-1].is32,regs[i-1].dirty,start+i*4);
10969 if(regs[i-1].regmap[HOST_CCREG]!=CCREG)
10970 emit_loadreg(CCREG,HOST_CCREG);
10971 emit_addimm(HOST_CCREG,CLOCK_DIVIDER*(ccadj[i-1]+1),HOST_CCREG);
10972 add_to_linker((int)out,start+i*4,0);
10973 emit_jmp(0);
10974 }
10975
10976 // TODO: delay slot stubs?
10977 // Stubs
10978 for(i=0;i<stubcount;i++)
10979 {
10980 switch(stubs[i][0])
10981 {
10982 case LOADB_STUB:
10983 case LOADH_STUB:
10984 case LOADW_STUB:
10985 case LOADD_STUB:
10986 case LOADBU_STUB:
10987 case LOADHU_STUB:
10988 do_readstub(i);break;
10989 case STOREB_STUB:
10990 case STOREH_STUB:
10991 case STOREW_STUB:
10992 case STORED_STUB:
10993 do_writestub(i);break;
10994 case CC_STUB:
10995 do_ccstub(i);break;
10996 case INVCODE_STUB:
10997 do_invstub(i);break;
10998 case FP_STUB:
10999 do_cop1stub(i);break;
11000 case STORELR_STUB:
11001 do_unalignedwritestub(i);break;
11002 }
11003 }
11004
9ad4d757 11005 if (instr_addr0_override)
11006 instr_addr[0] = instr_addr0_override;
11007
57871462 11008 /* Pass 9 - Linker */
11009 for(i=0;i<linkcount;i++)
11010 {
11011 assem_debug("%8x -> %8x\n",link_addr[i][0],link_addr[i][1]);
11012 literal_pool(64);
11013 if(!link_addr[i][2])
11014 {
11015 void *stub=out;
11016 void *addr=check_addr(link_addr[i][1]);
11017 emit_extjump(link_addr[i][0],link_addr[i][1]);
11018 if(addr) {
11019 set_jump_target(link_addr[i][0],(int)addr);
11020 add_link(link_addr[i][1],stub);
11021 }
11022 else set_jump_target(link_addr[i][0],(int)stub);
11023 }
11024 else
11025 {
11026 // Internal branch
11027 int target=(link_addr[i][1]-start)>>2;
11028 assert(target>=0&&target<slen);
11029 assert(instr_addr[target]);
11030 //#ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
11031 //set_jump_target_fillslot(link_addr[i][0],instr_addr[target],link_addr[i][2]>>1);
11032 //#else
11033 set_jump_target(link_addr[i][0],instr_addr[target]);
11034 //#endif
11035 }
11036 }
11037 // External Branch Targets (jump_in)
11038 if(copy+slen*4>(void *)shadow+sizeof(shadow)) copy=shadow;
11039 for(i=0;i<slen;i++)
11040 {
11041 if(bt[i]||i==0)
11042 {
11043 if(instr_addr[i]) // TODO - delay slots (=null)
11044 {
11045 u_int vaddr=start+i*4;
94d23bb9 11046 u_int page=get_page(vaddr);
11047 u_int vpage=get_vpage(vaddr);
57871462 11048 literal_pool(256);
11049 //if(!(is32[i]&(~unneeded_reg_upper[i])&~(1LL<<CCREG)))
a28c6ce8 11050#ifndef FORCE32
57871462 11051 if(!requires_32bit[i])
a28c6ce8 11052#else
11053 if(1)
11054#endif
57871462 11055 {
11056 assem_debug("%8x (%d) <- %8x\n",instr_addr[i],i,start+i*4);
11057 assem_debug("jump_in: %x\n",start+i*4);
11058 ll_add(jump_dirty+vpage,vaddr,(void *)out);
11059 int entry_point=do_dirty_stub(i);
11060 ll_add(jump_in+page,vaddr,(void *)entry_point);
11061 // If there was an existing entry in the hash table,
11062 // replace it with the new address.
11063 // Don't add new entries. We'll insert the
11064 // ones that actually get used in check_addr().
11065 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
11066 if(ht_bin[0]==vaddr) {
11067 ht_bin[1]=entry_point;
11068 }
11069 if(ht_bin[2]==vaddr) {
11070 ht_bin[3]=entry_point;
11071 }
11072 }
11073 else
11074 {
11075 u_int r=requires_32bit[i]|!!(requires_32bit[i]>>32);
11076 assem_debug("%8x (%d) <- %8x\n",instr_addr[i],i,start+i*4);
11077 assem_debug("jump_in: %x (restricted - %x)\n",start+i*4,r);
11078 //int entry_point=(int)out;
11079 ////assem_debug("entry_point: %x\n",entry_point);
11080 //load_regs_entry(i);
11081 //if(entry_point==(int)out)
11082 // entry_point=instr_addr[i];
11083 //else
11084 // emit_jmp(instr_addr[i]);
11085 //ll_add_32(jump_in+page,vaddr,r,(void *)entry_point);
11086 ll_add_32(jump_dirty+vpage,vaddr,r,(void *)out);
11087 int entry_point=do_dirty_stub(i);
11088 ll_add_32(jump_in+page,vaddr,r,(void *)entry_point);
11089 }
11090 }
11091 }
11092 }
11093 // Write out the literal pool if necessary
11094 literal_pool(0);
11095 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
11096 // Align code
11097 if(((u_int)out)&7) emit_addnop(13);
11098 #endif
11099 assert((u_int)out-beginning<MAX_OUTPUT_BLOCK_SIZE);
11100 //printf("shadow buffer: %x-%x\n",(int)copy,(int)copy+slen*4);
11101 memcpy(copy,source,slen*4);
11102 copy+=slen*4;
11103
11104 #ifdef __arm__
11105 __clear_cache((void *)beginning,out);
11106 #endif
11107
11108 // If we're within 256K of the end of the buffer,
11109 // start over from the beginning. (Is 256K enough?)
11110 if((int)out>BASE_ADDR+(1<<TARGET_SIZE_2)-MAX_OUTPUT_BLOCK_SIZE) out=(u_char *)BASE_ADDR;
11111
11112 // Trap writes to any of the pages we compiled
11113 for(i=start>>12;i<=(start+slen*4)>>12;i++) {
11114 invalid_code[i]=0;
90ae6d4e 11115#ifndef DISABLE_TLB
57871462 11116 memory_map[i]|=0x40000000;
11117 if((signed int)start>=(signed int)0xC0000000) {
11118 assert(using_tlb);
11119 j=(((u_int)i<<12)+(memory_map[i]<<2)-(u_int)rdram+(u_int)0x80000000)>>12;
11120 invalid_code[j]=0;
11121 memory_map[j]|=0x40000000;
11122 //printf("write protect physical page: %x (virtual %x)\n",j<<12,start);
11123 }
90ae6d4e 11124#endif
57871462 11125 }
b12c9fb8 11126#ifdef PCSX
11127 // PCSX maps all RAM mirror invalid_code tests to 0x80000000..0x80000000+RAM_SIZE
11128 if(get_page(start)<(RAM_SIZE>>12))
11129 for(i=start>>12;i<=(start+slen*4)>>12;i++)
11130 invalid_code[((u_int)0x80000000>>12)|i]=0;
11131#endif
57871462 11132
11133 /* Pass 10 - Free memory by expiring oldest blocks */
11134
11135 int end=((((int)out-BASE_ADDR)>>(TARGET_SIZE_2-16))+16384)&65535;
11136 while(expirep!=end)
11137 {
11138 int shift=TARGET_SIZE_2-3; // Divide into 8 blocks
11139 int base=BASE_ADDR+((expirep>>13)<<shift); // Base address of this block
11140 inv_debug("EXP: Phase %d\n",expirep);
11141 switch((expirep>>11)&3)
11142 {
11143 case 0:
11144 // Clear jump_in and jump_dirty
11145 ll_remove_matching_addrs(jump_in+(expirep&2047),base,shift);
11146 ll_remove_matching_addrs(jump_dirty+(expirep&2047),base,shift);
11147 ll_remove_matching_addrs(jump_in+2048+(expirep&2047),base,shift);
11148 ll_remove_matching_addrs(jump_dirty+2048+(expirep&2047),base,shift);
11149 break;
11150 case 1:
11151 // Clear pointers
11152 ll_kill_pointers(jump_out[expirep&2047],base,shift);
11153 ll_kill_pointers(jump_out[(expirep&2047)+2048],base,shift);
11154 break;
11155 case 2:
11156 // Clear hash table
11157 for(i=0;i<32;i++) {
11158 int *ht_bin=hash_table[((expirep&2047)<<5)+i];
11159 if((ht_bin[3]>>shift)==(base>>shift) ||
11160 ((ht_bin[3]-MAX_OUTPUT_BLOCK_SIZE)>>shift)==(base>>shift)) {
11161 inv_debug("EXP: Remove hash %x -> %x\n",ht_bin[2],ht_bin[3]);
11162 ht_bin[2]=ht_bin[3]=-1;
11163 }
11164 if((ht_bin[1]>>shift)==(base>>shift) ||
11165 ((ht_bin[1]-MAX_OUTPUT_BLOCK_SIZE)>>shift)==(base>>shift)) {
11166 inv_debug("EXP: Remove hash %x -> %x\n",ht_bin[0],ht_bin[1]);
11167 ht_bin[0]=ht_bin[2];
11168 ht_bin[1]=ht_bin[3];
11169 ht_bin[2]=ht_bin[3]=-1;
11170 }
11171 }
11172 break;
11173 case 3:
11174 // Clear jump_out
dd3a91a1 11175 #ifdef __arm__
11176 if((expirep&2047)==0)
11177 do_clear_cache();
11178 #endif
57871462 11179 ll_remove_matching_addrs(jump_out+(expirep&2047),base,shift);
11180 ll_remove_matching_addrs(jump_out+2048+(expirep&2047),base,shift);
11181 break;
11182 }
11183 expirep=(expirep+1)&65535;
11184 }
11185 return 0;
11186}
b9b61529 11187
11188// vim:shiftwidth=2:expandtab
ARM optimized PCSX fork