| eff55556 |
1 | // Pico Library - Internal Header File\r |
| cc68a136 |
2 | \r |
| 3 | // (c) Copyright 2004 Dave, All rights reserved.\r |
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4 | // (c) Copyright 2006-2008 Grazvydas "notaz" Ignotas, all rights reserved.\r |
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5 | // Free for non-commercial use.\r |
| 6 | \r |
| 7 | // For commercial use, separate licencing terms must be obtained.\r |
| 8 | \r |
| eff55556 |
9 | #ifndef PICO_INTERNAL_INCLUDED\r |
| 10 | #define PICO_INTERNAL_INCLUDED\r |
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11 | \r |
| 12 | #include <stdio.h>\r |
| 13 | #include <stdlib.h>\r |
| 14 | #include <string.h>\r |
| 15 | #include "Pico.h"\r |
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16 | #include "carthw/carthw.h"\r |
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17 | \r |
| 89fa852d |
18 | //\r |
| 19 | #define USE_POLL_DETECT\r |
| 20 | \r |
| eff55556 |
21 | #ifndef PICO_INTERNAL\r |
| 22 | #define PICO_INTERNAL\r |
| 23 | #endif\r |
| 24 | #ifndef PICO_INTERNAL_ASM\r |
| 25 | #define PICO_INTERNAL_ASM\r |
| 26 | #endif\r |
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27 | \r |
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28 | // to select core, define EMU_C68K, EMU_M68K or EMU_F68K in your makefile or project\r |
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29 | \r |
| 30 | #ifdef __cplusplus\r |
| 31 | extern "C" {\r |
| 32 | #endif\r |
| 33 | \r |
| 34 | \r |
| 35 | // ----------------------- 68000 CPU -----------------------\r |
| 36 | #ifdef EMU_C68K\r |
| 37 | #include "../cpu/Cyclone/Cyclone.h"\r |
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38 | extern struct Cyclone PicoCpuCM68k, PicoCpuCS68k;\r |
| 39 | #define SekCyclesLeftNoMCD PicoCpuCM68k.cycles // cycles left for this run\r |
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40 | #define SekCyclesLeft \\r |
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41 | (((PicoAHW&1) && (PicoOpt & POPT_EN_MCD_PSYNC)) ? (SekCycleAim-SekCycleCnt) : SekCyclesLeftNoMCD)\r |
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42 | #define SekCyclesLeftS68k \\r |
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43 | ((PicoOpt & POPT_EN_MCD_PSYNC) ? (SekCycleAimS68k-SekCycleCntS68k) : PicoCpuCS68k.cycles)\r |
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44 | #define SekSetCyclesLeftNoMCD(c) PicoCpuCM68k.cycles=c\r |
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45 | #define SekSetCyclesLeft(c) { \\r |
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46 | if ((PicoAHW&1) && (PicoOpt & POPT_EN_MCD_PSYNC)) SekCycleCnt=SekCycleAim-(c); else SekSetCyclesLeftNoMCD(c); \\r |
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47 | }\r |
| 3aa1e148 |
48 | #define SekPc (PicoCpuCM68k.pc-PicoCpuCM68k.membase)\r |
| 49 | #define SekPcS68k (PicoCpuCS68k.pc-PicoCpuCS68k.membase)\r |
| 50 | #define SekSetStop(x) { PicoCpuCM68k.state_flags&=~1; if (x) { PicoCpuCM68k.state_flags|=1; PicoCpuCM68k.cycles=0; } }\r |
| 51 | #define SekSetStopS68k(x) { PicoCpuCS68k.state_flags&=~1; if (x) { PicoCpuCS68k.state_flags|=1; PicoCpuCS68k.cycles=0; } }\r |
| ca61ee42 |
52 | #define SekIsStoppedS68k() (PicoCpuCS68k.state_flags&1)\r |
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53 | #define SekShouldInterrupt (PicoCpuCM68k.irq > (PicoCpuCM68k.srh&7))\r |
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54 | \r |
| 55 | #define SekInterrupt(i) PicoCpuCM68k.irq=i\r |
| 56 | \r |
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57 | #ifdef EMU_M68K\r |
| 58 | #define EMU_CORE_DEBUG\r |
| 59 | #endif\r |
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60 | #endif\r |
| 61 | \r |
| 70357ce5 |
62 | #ifdef EMU_F68K\r |
| 63 | #include "../cpu/fame/fame.h"\r |
| b542be46 |
64 | extern M68K_CONTEXT PicoCpuFM68k, PicoCpuFS68k;\r |
| 3aa1e148 |
65 | #define SekCyclesLeftNoMCD PicoCpuFM68k.io_cycle_counter\r |
| 70357ce5 |
66 | #define SekCyclesLeft \\r |
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67 | (((PicoAHW&1) && (PicoOpt & POPT_EN_MCD_PSYNC)) ? (SekCycleAim-SekCycleCnt) : SekCyclesLeftNoMCD)\r |
| 70357ce5 |
68 | #define SekCyclesLeftS68k \\r |
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69 | ((PicoOpt & POPT_EN_MCD_PSYNC) ? (SekCycleAimS68k-SekCycleCntS68k) : PicoCpuFS68k.io_cycle_counter)\r |
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70 | #define SekSetCyclesLeftNoMCD(c) PicoCpuFM68k.io_cycle_counter=c\r |
| 70357ce5 |
71 | #define SekSetCyclesLeft(c) { \\r |
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72 | if ((PicoAHW&1) && (PicoOpt & POPT_EN_MCD_PSYNC)) SekCycleCnt=SekCycleAim-(c); else SekSetCyclesLeftNoMCD(c); \\r |
| 70357ce5 |
73 | }\r |
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74 | #define SekPc fm68k_get_pc(&PicoCpuFM68k)\r |
| 75 | #define SekPcS68k fm68k_get_pc(&PicoCpuFS68k)\r |
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76 | #define SekSetStop(x) { \\r |
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77 | PicoCpuFM68k.execinfo &= ~FM68K_HALTED; \\r |
| 78 | if (x) { PicoCpuFM68k.execinfo |= FM68K_HALTED; PicoCpuFM68k.io_cycle_counter = 0; } \\r |
| 70357ce5 |
79 | }\r |
| 80 | #define SekSetStopS68k(x) { \\r |
| 03e4f2a3 |
81 | PicoCpuFS68k.execinfo &= ~FM68K_HALTED; \\r |
| 82 | if (x) { PicoCpuFS68k.execinfo |= FM68K_HALTED; PicoCpuFS68k.io_cycle_counter = 0; } \\r |
| 70357ce5 |
83 | }\r |
| ca61ee42 |
84 | #define SekIsStoppedS68k() (PicoCpuFS68k.execinfo&FM68K_HALTED)\r |
| 03e4f2a3 |
85 | #define SekShouldInterrupt fm68k_would_interrupt()\r |
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86 | \r |
| 87 | #define SekInterrupt(irq) PicoCpuFM68k.interrupts[0]=irq\r |
| 88 | \r |
| 03e4f2a3 |
89 | #ifdef EMU_M68K\r |
| 90 | #define EMU_CORE_DEBUG\r |
| 91 | #endif\r |
| cc68a136 |
92 | #endif\r |
| 93 | \r |
| 94 | #ifdef EMU_M68K\r |
| 95 | #include "../cpu/musashi/m68kcpu.h"\r |
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96 | extern m68ki_cpu_core PicoCpuMM68k, PicoCpuMS68k;\r |
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97 | #ifndef SekCyclesLeft\r |
| 3aa1e148 |
98 | #define SekCyclesLeftNoMCD PicoCpuMM68k.cyc_remaining_cycles\r |
| 7336a99a |
99 | #define SekCyclesLeft \\r |
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100 | (((PicoAHW&1) && (PicoOpt & POPT_EN_MCD_PSYNC)) ? (SekCycleAim-SekCycleCnt) : SekCyclesLeftNoMCD)\r |
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101 | #define SekCyclesLeftS68k \\r |
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102 | ((PicoOpt & POPT_EN_MCD_PSYNC) ? (SekCycleAimS68k-SekCycleCntS68k) : PicoCpuMS68k.cyc_remaining_cycles)\r |
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103 | #define SekSetCyclesLeftNoMCD(c) SET_CYCLES(c)\r |
| 104 | #define SekSetCyclesLeft(c) { \\r |
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105 | if ((PicoAHW&1) && (PicoOpt & POPT_EN_MCD_PSYNC)) SekCycleCnt=SekCycleAim-(c); else SET_CYCLES(c); \\r |
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106 | }\r |
| 3aa1e148 |
107 | #define SekPc m68k_get_reg(&PicoCpuMM68k, M68K_REG_PC)\r |
| 108 | #define SekPcS68k m68k_get_reg(&PicoCpuMS68k, M68K_REG_PC)\r |
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109 | #define SekSetStop(x) { \\r |
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110 | if(x) { SET_CYCLES(0); PicoCpuMM68k.stopped=STOP_LEVEL_STOP; } \\r |
| 111 | else PicoCpuMM68k.stopped=0; \\r |
| 7a1f6e45 |
112 | }\r |
| 113 | #define SekSetStopS68k(x) { \\r |
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114 | if(x) { SET_CYCLES(0); PicoCpuMS68k.stopped=STOP_LEVEL_STOP; } \\r |
| 115 | else PicoCpuMS68k.stopped=0; \\r |
| 7a1f6e45 |
116 | }\r |
| ca61ee42 |
117 | #define SekIsStoppedS68k() (PicoCpuMS68k.stopped==STOP_LEVEL_STOP)\r |
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118 | #define SekShouldInterrupt (CPU_INT_LEVEL > FLAG_INT_MASK)\r |
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119 | \r |
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120 | #define SekInterrupt(irq) { \\r |
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121 | void *oldcontext = m68ki_cpu_p; \\r |
| 122 | m68k_set_context(&PicoCpuMM68k); \\r |
| 123 | m68k_set_irq(irq); \\r |
| 124 | m68k_set_context(oldcontext); \\r |
| 125 | }\r |
| 126 | \r |
| cc68a136 |
127 | #endif\r |
| 128 | #endif\r |
| 129 | \r |
| 130 | extern int SekCycleCnt; // cycles done in this frame\r |
| 131 | extern int SekCycleAim; // cycle aim\r |
| 132 | extern unsigned int SekCycleCntT; // total cycle counter, updated once per frame\r |
| 133 | \r |
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134 | #define SekCyclesReset() { \\r |
| 135 | SekCycleCntT+=SekCycleAim; \\r |
| 136 | SekCycleCnt-=SekCycleAim; \\r |
| 137 | SekCycleAim=0; \\r |
| 138 | }\r |
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139 | #define SekCyclesBurn(c) SekCycleCnt+=c\r |
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140 | #define SekCyclesDone() (SekCycleAim-SekCyclesLeft) // number of cycles done in this frame (can be checked anywhere)\r |
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141 | #define SekCyclesDoneT() (SekCycleCntT+SekCyclesDone()) // total nuber of cycles done for this rom\r |
| 142 | \r |
| 143 | #define SekEndRun(after) { \\r |
| 144 | SekCycleCnt -= SekCyclesLeft - after; \\r |
| 145 | if(SekCycleCnt < 0) SekCycleCnt = 0; \\r |
| 146 | SekSetCyclesLeft(after); \\r |
| 147 | }\r |
| 148 | \r |
| 149 | extern int SekCycleCntS68k;\r |
| 150 | extern int SekCycleAimS68k;\r |
| 151 | \r |
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152 | #define SekCyclesResetS68k() { \\r |
| 153 | SekCycleCntS68k-=SekCycleAimS68k; \\r |
| 154 | SekCycleAimS68k=0; \\r |
| 155 | }\r |
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156 | #define SekCyclesDoneS68k() (SekCycleAimS68k-SekCyclesLeftS68k)\r |
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157 | \r |
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158 | #ifdef EMU_CORE_DEBUG\r |
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159 | extern int dbg_irq_level;\r |
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160 | #undef SekSetCyclesLeftNoMCD\r |
| 161 | #undef SekSetCyclesLeft\r |
| 162 | #undef SekCyclesBurn\r |
| 163 | #undef SekEndRun\r |
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164 | #undef SekInterrupt\r |
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165 | #define SekSetCyclesLeftNoMCD(c)\r |
| 166 | #define SekSetCyclesLeft(c)\r |
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167 | #define SekCyclesBurn(c) c\r |
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168 | #define SekEndRun(c)\r |
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169 | #define SekInterrupt(irq) dbg_irq_level=irq\r |
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170 | #endif\r |
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171 | \r |
| b542be46 |
172 | // ----------------------- Z80 CPU -----------------------\r |
| 173 | \r |
| 174 | #if defined(_USE_MZ80)\r |
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175 | #include "../cpu/mz80/mz80.h"\r |
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176 | \r |
| 4b9c5888 |
177 | #define z80_run(cycles) { mz80GetElapsedTicks(1); mz80_run(cycles) }\r |
| b542be46 |
178 | #define z80_run_nr(cycles) mz80_run(cycles)\r |
| 179 | #define z80_int() mz80int(0)\r |
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180 | \r |
| 181 | #elif defined(_USE_DRZ80)\r |
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182 | #include "../cpu/DrZ80/drz80.h"\r |
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183 | \r |
| 184 | extern struct DrZ80 drZ80;\r |
| 185 | \r |
| 186 | #define z80_run(cycles) ((cycles) - DrZ80Run(&drZ80, cycles))\r |
| 187 | #define z80_run_nr(cycles) DrZ80Run(&drZ80, cycles)\r |
| 4936aac1 |
188 | #define z80_int() drZ80.Z80_IRQ = 1\r |
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189 | \r |
| 190 | #define z80_cyclesLeft drZ80.cycles\r |
| b542be46 |
191 | \r |
| 192 | #elif defined(_USE_CZ80)\r |
| dca310c4 |
193 | #include "../cpu/cz80/cz80.h"\r |
| b542be46 |
194 | \r |
| 195 | #define z80_run(cycles) Cz80_Exec(&CZ80, cycles)\r |
| 196 | #define z80_run_nr(cycles) Cz80_Exec(&CZ80, cycles)\r |
| 197 | #define z80_int() Cz80_Set_IRQ(&CZ80, 0, HOLD_LINE)\r |
| 4b9c5888 |
198 | \r |
| 199 | #define z80_cyclesLeft (CZ80.ICount - CZ80.ExtraCycles)\r |
| b542be46 |
200 | \r |
| 201 | #else\r |
| 202 | \r |
| 203 | #define z80_run(cycles) (cycles)\r |
| 204 | #define z80_run_nr(cycles)\r |
| 205 | #define z80_int()\r |
| b542be46 |
206 | \r |
| 207 | #endif\r |
| 208 | \r |
| 4b9c5888 |
209 | extern int z80stopCycle; /* in 68k cycles */\r |
| 210 | extern int z80_cycle_cnt; /* 'done' z80 cycles before z80_run() */\r |
| 211 | extern int z80_cycle_aim;\r |
| 212 | extern int z80_scanline;\r |
| 213 | extern int z80_scanline_cycles; /* cycles done until z80_scanline */\r |
| 214 | \r |
| 215 | #define z80_resetCycles() \\r |
| 216 | z80_cycle_cnt = z80_cycle_aim = z80_scanline = z80_scanline_cycles = 0;\r |
| 217 | \r |
| 218 | #define z80_cyclesDone() \\r |
| 219 | (z80_cycle_aim - z80_cyclesLeft)\r |
| 220 | \r |
| 221 | #define cycles_68k_to_z80(x) ((x)*957 >> 11)\r |
| 222 | \r |
| cc68a136 |
223 | // ---------------------------------------------------------\r |
| 224 | \r |
| 225 | // main oscillator clock which controls timing\r |
| 226 | #define OSC_NTSC 53693100\r |
| b8cbd802 |
227 | // seems to be accurate, see scans from http://www.hot.ee/tmeeco/\r |
| 228 | #define OSC_PAL 53203424\r |
| cc68a136 |
229 | \r |
| 230 | struct PicoVideo\r |
| 231 | {\r |
| 232 | unsigned char reg[0x20];\r |
| b8cbd802 |
233 | unsigned int command; // 32-bit Command\r |
| 234 | unsigned char pending; // 1 if waiting for second half of 32-bit command\r |
| 235 | unsigned char type; // Command type (v/c/vsram read/write)\r |
| 236 | unsigned short addr; // Read/Write address\r |
| 237 | int status; // Status bits\r |
| cc68a136 |
238 | unsigned char pending_ints; // pending interrupts: ??VH????\r |
| b8cbd802 |
239 | signed char lwrite_cnt; // VDP write count during active display line\r |
| 240 | unsigned char pad[0x12];\r |
| cc68a136 |
241 | };\r |
| 242 | \r |
| 243 | struct PicoMisc\r |
| 244 | {\r |
| 245 | unsigned char rotate;\r |
| 246 | unsigned char z80Run;\r |
| e5503e2f |
247 | unsigned char padTHPhase[2]; // 02 phase of gamepad TH switches\r |
| 248 | short scanline; // 04 0 to 261||311; -1 in fast mode\r |
| 249 | char dirtyPal; // 06 Is the palette dirty (1 - change @ this frame, 2 - some time before)\r |
| 250 | unsigned char hardware; // 07 Hardware value for country\r |
| 251 | unsigned char pal; // 08 1=PAL 0=NTSC\r |
| 252 | unsigned char sram_reg; // SRAM mode register. bit0: allow read? bit1: deny write? bit2: EEPROM? bit4: detected? (header or by access)\r |
| 253 | unsigned short z80_bank68k; // 0a\r |
| cc68a136 |
254 | unsigned short z80_lastaddr; // this is for Z80 faking\r |
| 255 | unsigned char z80_fakeval;\r |
| bd613473 |
256 | unsigned char z80_reset; // z80 reset held\r |
| e5503e2f |
257 | unsigned char padDelay[2]; // 10 gamepad phase time outs, so we count a delay\r |
| 1dceadae |
258 | unsigned short eeprom_addr; // EEPROM address register\r |
| 259 | unsigned char eeprom_cycle; // EEPROM SRAM cycle number\r |
| 260 | unsigned char eeprom_slave; // EEPROM slave word for X24C02 and better SRAMs\r |
| 721cd396 |
261 | unsigned char prot_bytes[2]; // simple protection faking\r |
| b8cbd802 |
262 | unsigned short dma_xfers;\r |
| 312e9ce1 |
263 | unsigned char pad[2];\r |
| 264 | unsigned int frame_count; // mainly for movies\r |
| cc68a136 |
265 | };\r |
| 266 | \r |
| 267 | // some assembly stuff depend on these, do not touch!\r |
| 268 | struct Pico\r |
| 269 | {\r |
| 270 | unsigned char ram[0x10000]; // 0x00000 scratch ram\r |
| 271 | unsigned short vram[0x8000]; // 0x10000\r |
| 272 | unsigned char zram[0x2000]; // 0x20000 Z80 ram\r |
| 273 | unsigned char ioports[0x10];\r |
| 274 | unsigned int pad[0x3c]; // unused\r |
| 275 | unsigned short cram[0x40]; // 0x22100\r |
| 276 | unsigned short vsram[0x40]; // 0x22180\r |
| 277 | \r |
| 278 | unsigned char *rom; // 0x22200\r |
| 279 | unsigned int romsize; // 0x22204\r |
| 280 | \r |
| 281 | struct PicoMisc m;\r |
| 282 | struct PicoVideo video;\r |
| 283 | };\r |
| 284 | \r |
| 285 | // sram\r |
| 286 | struct PicoSRAM\r |
| 287 | {\r |
| 4ff2d527 |
288 | unsigned char *data; // actual data\r |
| 289 | unsigned int start; // start address in 68k address space\r |
| cc68a136 |
290 | unsigned int end;\r |
| 1dceadae |
291 | unsigned char unused1; // 0c: unused\r |
| 292 | unsigned char unused2;\r |
| cc68a136 |
293 | unsigned char changed;\r |
| 1dceadae |
294 | unsigned char eeprom_type; // eeprom type: 0: 7bit (24C01), 2: device with 2 addr words (X24C02+), 3: dev with 3 addr words\r |
| 295 | unsigned char eeprom_abits; // eeprom access must be odd addr for: bit0 ~ cl, bit1 ~ out\r |
| 296 | unsigned char eeprom_bit_cl; // bit number for cl\r |
| 297 | unsigned char eeprom_bit_in; // bit number for in\r |
| 298 | unsigned char eeprom_bit_out; // bit number for out\r |
| cc68a136 |
299 | };\r |
| 300 | \r |
| 301 | // MCD\r |
| 302 | #include "cd/cd_sys.h"\r |
| 303 | #include "cd/LC89510.h"\r |
| d1df8786 |
304 | #include "cd/gfx_cd.h"\r |
| cc68a136 |
305 | \r |
| 4f265db7 |
306 | struct mcd_pcm\r |
| 307 | {\r |
| 308 | unsigned char control; // reg7\r |
| 309 | unsigned char enabled; // reg8\r |
| 310 | unsigned char cur_ch;\r |
| 311 | unsigned char bank;\r |
| 312 | int pad1;\r |
| 313 | \r |
| 4ff2d527 |
314 | struct pcm_chan // 08, size 0x10\r |
| 4f265db7 |
315 | {\r |
| 316 | unsigned char regs[8];\r |
| 4ff2d527 |
317 | unsigned int addr; // .08: played sample address\r |
| 4f265db7 |
318 | int pad;\r |
| 319 | } ch[8];\r |
| 320 | };\r |
| 321 | \r |
| c459aefd |
322 | struct mcd_misc\r |
| 323 | {\r |
| 324 | unsigned short hint_vector;\r |
| 325 | unsigned char busreq;\r |
| 51a902ae |
326 | unsigned char s68k_pend_ints;\r |
| 89fa852d |
327 | unsigned int state_flags; // 04: emu state: reset_pending, dmna_pending\r |
| 51a902ae |
328 | unsigned int counter75hz;\r |
| c9e1affc |
329 | unsigned int pad0;\r |
| 4ff2d527 |
330 | int timer_int3; // 10\r |
| 4f265db7 |
331 | unsigned int timer_stopwatch;\r |
| 6cadc2da |
332 | unsigned char bcram_reg; // 18: battery-backed RAM cart register\r |
| 333 | unsigned char pad2;\r |
| 334 | unsigned short pad3;\r |
| 335 | int pad[9];\r |
| c459aefd |
336 | };\r |
| 337 | \r |
| cc68a136 |
338 | typedef struct\r |
| 339 | {\r |
| 4ff2d527 |
340 | unsigned char bios[0x20000]; // 000000: 128K\r |
| 341 | union { // 020000: 512K\r |
| fa1e5e29 |
342 | unsigned char prg_ram[0x80000];\r |
| cc68a136 |
343 | unsigned char prg_ram_b[4][0x20000];\r |
| 344 | };\r |
| 4ff2d527 |
345 | union { // 0a0000: 256K\r |
| fa1e5e29 |
346 | struct {\r |
| 347 | unsigned char word_ram2M[0x40000];\r |
| dca310c4 |
348 | unsigned char unused0[0x20000];\r |
| fa1e5e29 |
349 | };\r |
| 350 | struct {\r |
| dca310c4 |
351 | unsigned char unused1[0x20000];\r |
| fa1e5e29 |
352 | unsigned char word_ram1M[2][0x20000];\r |
| 353 | };\r |
| 354 | };\r |
| 4ff2d527 |
355 | union { // 100000: 64K\r |
| fa1e5e29 |
356 | unsigned char pcm_ram[0x10000];\r |
| 4f265db7 |
357 | unsigned char pcm_ram_b[0x10][0x1000];\r |
| 358 | };\r |
| 4ff2d527 |
359 | unsigned char s68k_regs[0x200]; // 110000: GA, not CPU regs\r |
| 360 | unsigned char bram[0x2000]; // 110200: 8K\r |
| 361 | struct mcd_misc m; // 112200: misc\r |
| 362 | struct mcd_pcm pcm; // 112240:\r |
| 75736070 |
363 | _scd_toc TOC; // not to be saved\r |
| cc68a136 |
364 | CDD cdd;\r |
| 365 | CDC cdc;\r |
| 366 | _scd scd;\r |
| d1df8786 |
367 | Rot_Comp rot_comp;\r |
| cc68a136 |
368 | } mcd_state;\r |
| 369 | \r |
| 370 | #define Pico_mcd ((mcd_state *)Pico.rom)\r |
| 371 | \r |
| d49b10c2 |
372 | \r |
| 51a902ae |
373 | // Area.c\r |
| eff55556 |
374 | PICO_INTERNAL int PicoAreaPackCpu(unsigned char *cpu, int is_sub);\r |
| 375 | PICO_INTERNAL int PicoAreaUnpackCpu(unsigned char *cpu, int is_sub);\r |
| fad24893 |
376 | extern void (*PicoLoadStateHook)(void);\r |
| 51a902ae |
377 | \r |
| 378 | // cd/Area.c\r |
| eff55556 |
379 | PICO_INTERNAL int PicoCdSaveState(void *file);\r |
| 380 | PICO_INTERNAL int PicoCdLoadState(void *file);\r |
| cc68a136 |
381 | \r |
| 945c2fdc |
382 | typedef struct {\r |
| 383 | int chunk;\r |
| 384 | int size;\r |
| 385 | void *ptr;\r |
| 386 | } carthw_state_chunk;\r |
| 387 | extern carthw_state_chunk *carthw_chunks;\r |
| 388 | #define CHUNK_CARTHW 64\r |
| 389 | \r |
| 1dceadae |
390 | // Cart.c\r |
| e807ac75 |
391 | extern void (*PicoCartUnloadHook)(void);\r |
| 1dceadae |
392 | \r |
| 03e4f2a3 |
393 | // Debug.c\r |
| b5e5172d |
394 | int CM_compareRun(int cyc, int is_sub);\r |
| 03e4f2a3 |
395 | \r |
| cc68a136 |
396 | // Draw.c\r |
| eff55556 |
397 | PICO_INTERNAL int PicoLine(int scan);\r |
| 398 | PICO_INTERNAL void PicoFrameStart(void);\r |
| cc68a136 |
399 | \r |
| 400 | // Draw2.c\r |
| eff55556 |
401 | PICO_INTERNAL void PicoFrameFull();\r |
| cc68a136 |
402 | \r |
| 403 | // Memory.c\r |
| eff55556 |
404 | PICO_INTERNAL int PicoInitPc(unsigned int pc);\r |
| 406c96c5 |
405 | PICO_INTERNAL unsigned int PicoCheckPc(unsigned int pc);\r |
| 8ab3e3c1 |
406 | PICO_INTERNAL_ASM unsigned int PicoRead32(unsigned int a);\r |
| eff55556 |
407 | PICO_INTERNAL void PicoMemSetup(void);\r |
| 408 | PICO_INTERNAL_ASM void PicoMemReset(void);\r |
| f8ef8ff7 |
409 | PICO_INTERNAL void PicoMemResetHooks(void);\r |
| e5503e2f |
410 | PICO_INTERNAL int PadRead(int i);\r |
| eff55556 |
411 | PICO_INTERNAL unsigned char z80_read(unsigned short a);\r |
| a4221917 |
412 | #ifndef _USE_CZ80\r |
| eff55556 |
413 | PICO_INTERNAL_ASM void z80_write(unsigned char data, unsigned short a);\r |
| 414 | PICO_INTERNAL void z80_write16(unsigned short data, unsigned short a);\r |
| a4221917 |
415 | PICO_INTERNAL unsigned short z80_read16(unsigned short a);\r |
| 416 | #else\r |
| 417 | PICO_INTERNAL_ASM void z80_write(unsigned int a, unsigned char data);\r |
| 418 | #endif\r |
| 4b9c5888 |
419 | PICO_INTERNAL int ym2612_write_local(unsigned int a, unsigned int d, int is_from_z80);\r |
| f53f286a |
420 | extern unsigned int (*PicoRead16Hook)(unsigned int a, int realsize);\r |
| f8ef8ff7 |
421 | extern void (*PicoWrite8Hook) (unsigned int a,unsigned int d,int realsize);\r |
| 422 | extern void (*PicoWrite16Hook)(unsigned int a,unsigned int d,int realsize);\r |
| cc68a136 |
423 | \r |
| 424 | // cd/Memory.c\r |
| eff55556 |
425 | PICO_INTERNAL void PicoMemSetupCD(void);\r |
| 426 | PICO_INTERNAL_ASM void PicoMemResetCD(int r3);\r |
| 427 | PICO_INTERNAL_ASM void PicoMemResetCDdecode(int r3);\r |
| cc68a136 |
428 | \r |
| 9037e45d |
429 | // Pico/Memory.c\r |
| 430 | PICO_INTERNAL void PicoMemSetupPico(void);\r |
| 43e6eaad |
431 | PICO_INTERNAL unsigned int ym2612_read_local_68k(void);\r |
| 9037e45d |
432 | \r |
| cc68a136 |
433 | // Pico.c\r |
| 434 | extern struct Pico Pico;\r |
| 435 | extern struct PicoSRAM SRam;\r |
| 436 | extern int emustatus;\r |
| f8ef8ff7 |
437 | extern void (*PicoResetHook)(void);\r |
| 0ffefdb8 |
438 | extern void (*PicoLineHook)(int count);\r |
| 1e6b5e39 |
439 | PICO_INTERNAL int CheckDMA(void);\r |
| 440 | PICO_INTERNAL void PicoDetectRegion(void);\r |
| 4b9c5888 |
441 | PICO_INTERNAL void PicoSyncZ80(int m68k_cycles_done);\r |
| cc68a136 |
442 | \r |
| 443 | // cd/Pico.c\r |
| e5f426aa |
444 | PICO_INTERNAL int PicoInitMCD(void);\r |
| 445 | PICO_INTERNAL void PicoExitMCD(void);\r |
| 1cb1584b |
446 | PICO_INTERNAL void PicoPowerMCD(void);\r |
| 447 | PICO_INTERNAL int PicoResetMCD(void);\r |
| eff55556 |
448 | PICO_INTERNAL int PicoFrameMCD(void);\r |
| cc68a136 |
449 | \r |
| 9037e45d |
450 | // Pico/Pico.c\r |
| 451 | PICO_INTERNAL int PicoInitPico(void);\r |
| ed367a3f |
452 | PICO_INTERNAL void PicoReratePico(void);\r |
| 9037e45d |
453 | \r |
| ef4eb506 |
454 | // Pico/xpcm.c\r |
| 455 | PICO_INTERNAL void PicoPicoPCMUpdate(short *buffer, int length, int stereo);\r |
| 456 | PICO_INTERNAL void PicoPicoPCMReset(void);\r |
| 213c16ad |
457 | PICO_INTERNAL void PicoPicoPCMRerate(int xpcm_rate);\r |
| ef4eb506 |
458 | \r |
| cc68a136 |
459 | // Sek.c\r |
| eff55556 |
460 | PICO_INTERNAL int SekInit(void);\r |
| 461 | PICO_INTERNAL int SekReset(void);\r |
| 3aa1e148 |
462 | PICO_INTERNAL void SekState(int *data);\r |
| eff55556 |
463 | PICO_INTERNAL void SekSetRealTAS(int use_real);\r |
| cc68a136 |
464 | \r |
| 465 | // cd/Sek.c\r |
| eff55556 |
466 | PICO_INTERNAL int SekInitS68k(void);\r |
| 467 | PICO_INTERNAL int SekResetS68k(void);\r |
| 468 | PICO_INTERNAL int SekInterruptS68k(int irq);\r |
| cc68a136 |
469 | \r |
| 7a93adeb |
470 | // sound/sound.c\r |
| c9e1affc |
471 | PICO_INTERNAL void cdda_start_play();\r |
| 472 | extern short cdda_out_buffer[2*1152];\r |
| 7a93adeb |
473 | extern int PsndLen_exc_cnt;\r |
| 474 | extern int PsndLen_exc_add;\r |
| 43e6eaad |
475 | extern int timer_a_next_oflow, timer_a_step, timer_a_offset; // in z80 cycles\r |
| 476 | extern int timer_b_next_oflow, timer_b_step, timer_b_offset;\r |
| 477 | \r |
| 478 | void ym2612_sync_timers(int z80_cycles, int mode_old, int mode_new);\r |
| d2721b08 |
479 | void ym2612_pack_state(void);\r |
| 453d2a6e |
480 | void ym2612_unpack_state(void);\r |
| 4b9c5888 |
481 | \r |
| e53704e6 |
482 | #define TIMER_NO_OFLOW 0x70000000\r |
| 483 | \r |
| 4b9c5888 |
484 | #define timers_cycle() \\r |
| e53704e6 |
485 | if (timer_a_next_oflow > 0 && timer_a_next_oflow < TIMER_NO_OFLOW) \\r |
| 43e6eaad |
486 | timer_a_next_oflow -= Pico.m.pal ? 70938*256 : 59659*256; \\r |
| e53704e6 |
487 | if (timer_b_next_oflow > 0 && timer_b_next_oflow < TIMER_NO_OFLOW) \\r |
| 43e6eaad |
488 | timer_b_next_oflow -= Pico.m.pal ? 70938*256 : 59659*256; \\r |
| 489 | ym2612_sync_timers(0, ym2612.OPN.ST.mode, ym2612.OPN.ST.mode);\r |
| 4b9c5888 |
490 | \r |
| 491 | #define timers_reset() \\r |
| e53704e6 |
492 | timer_a_next_oflow = timer_b_next_oflow = TIMER_NO_OFLOW; \\r |
| 43e6eaad |
493 | timer_a_step = timer_a_offset = 16495 * 1024; \\r |
| 494 | timer_b_step = timer_b_offset = 263912 * 256;\r |
| 495 | \r |
| 7a93adeb |
496 | \r |
| cc68a136 |
497 | // VideoPort.c\r |
| eff55556 |
498 | PICO_INTERNAL_ASM void PicoVideoWrite(unsigned int a,unsigned short d);\r |
| 499 | PICO_INTERNAL_ASM unsigned int PicoVideoRead(unsigned int a);\r |
| 5de27868 |
500 | extern int (*PicoDmaHook)(unsigned int source, int len, unsigned short **srcp, unsigned short **limitp);\r |
| cc68a136 |
501 | \r |
| 502 | // Misc.c\r |
| eff55556 |
503 | PICO_INTERNAL void SRAMWriteEEPROM(unsigned int d);\r |
| 504 | PICO_INTERNAL void SRAMUpdPending(unsigned int a, unsigned int d);\r |
| 505 | PICO_INTERNAL_ASM unsigned int SRAMReadEEPROM(void);\r |
| 506 | PICO_INTERNAL_ASM void memcpy16(unsigned short *dest, unsigned short *src, int count);\r |
| 507 | PICO_INTERNAL_ASM void memcpy16bswap(unsigned short *dest, void *src, int count);\r |
| 508 | PICO_INTERNAL_ASM void memcpy32(int *dest, int *src, int count); // 32bit word count\r |
| 509 | PICO_INTERNAL_ASM void memset32(int *dest, int c, int count);\r |
| cc68a136 |
510 | \r |
| fa1e5e29 |
511 | // cd/Misc.c\r |
| eff55556 |
512 | PICO_INTERNAL_ASM void wram_2M_to_1M(unsigned char *m);\r |
| 513 | PICO_INTERNAL_ASM void wram_1M_to_2M(unsigned char *m);\r |
| 514 | \r |
| 515 | // cd/buffering.c\r |
| 516 | PICO_INTERNAL void PicoCDBufferRead(void *dest, int lba);\r |
| 517 | \r |
| 518 | // sound/sound.c\r |
| 9d917eea |
519 | PICO_INTERNAL void PsndReset(void);\r |
| 4b9c5888 |
520 | PICO_INTERNAL void PsndDoDAC(int line_to);\r |
| 9d917eea |
521 | PICO_INTERNAL int PsndRender(int offset, int length);\r |
| 522 | PICO_INTERNAL void PsndClear(void);\r |
| eff55556 |
523 | // z80 functionality wrappers\r |
| 524 | PICO_INTERNAL void z80_init(void);\r |
| eff55556 |
525 | PICO_INTERNAL void z80_pack(unsigned char *data);\r |
| 526 | PICO_INTERNAL void z80_unpack(unsigned char *data);\r |
| 527 | PICO_INTERNAL void z80_reset(void);\r |
| 528 | PICO_INTERNAL void z80_exit(void);\r |
| 4b9c5888 |
529 | extern int PsndDacLine;\r |
| cc68a136 |
530 | \r |
| 531 | #ifdef __cplusplus\r |
| 532 | } // End of extern "C"\r |
| 533 | #endif\r |
| eff55556 |
534 | \r |
| b8cbd802 |
535 | // emulation event logging\r |
| 536 | #ifndef EL_LOGMASK\r |
| 537 | #define EL_LOGMASK 0\r |
| 538 | #endif\r |
| 539 | \r |
| 017512f2 |
540 | #define EL_HVCNT 0x00000001 /* hv counter reads */\r |
| 541 | #define EL_SR 0x00000002 /* SR reads */\r |
| 542 | #define EL_INTS 0x00000004 /* ints and acks */\r |
| 43e6eaad |
543 | #define EL_YMTIMER 0x00000008 /* ym2612 timer stuff */\r |
| 017512f2 |
544 | #define EL_INTSW 0x00000010 /* log irq switching on/off */\r |
| 545 | #define EL_ASVDP 0x00000020 /* VDP accesses during active scan */\r |
| 546 | #define EL_VDPDMA 0x00000040 /* VDP DMA transfers and their timing */\r |
| 547 | #define EL_BUSREQ 0x00000080 /* z80 busreq r/w or reset w */\r |
| 548 | #define EL_Z80BNK 0x00000100 /* z80 i/o through bank area */\r |
| 549 | #define EL_SRAMIO 0x00000200 /* sram i/o */\r |
| 550 | #define EL_EEPROM 0x00000400 /* eeprom debug */\r |
| 551 | #define EL_UIO 0x00000800 /* unmapped i/o */\r |
| 552 | #define EL_IO 0x00001000 /* all i/o */\r |
| 553 | #define EL_CDPOLL 0x00002000 /* MCD: log poll detection */\r |
| 554 | #define EL_SVP 0x00004000 /* SVP stuff */\r |
| fa22af4c |
555 | #define EL_PICOHW 0x00008000 /* Pico stuff */\r |
| 017512f2 |
556 | \r |
| 557 | #define EL_STATUS 0x40000000 /* status messages */\r |
| 558 | #define EL_ANOMALY 0x80000000 /* some unexpected conditions (during emulation) */\r |
| b8cbd802 |
559 | \r |
| 560 | #if EL_LOGMASK\r |
| 7d0143a2 |
561 | extern void lprintf(const char *fmt, ...);\r |
| b8cbd802 |
562 | #define elprintf(w,f,...) \\r |
| 563 | { \\r |
| 564 | if ((w) & EL_LOGMASK) \\r |
| 7d0143a2 |
565 | lprintf("%05i:%03i: " f "\n",Pico.m.frame_count,Pico.m.scanline,##__VA_ARGS__); \\r |
| b8cbd802 |
566 | }\r |
| dca310c4 |
567 | #elif defined(_MSC_VER)\r |
| 568 | #define elprintf\r |
| b8cbd802 |
569 | #else\r |
| 570 | #define elprintf(w,f,...)\r |
| 571 | #endif\r |
| 572 | \r |
| dca310c4 |
573 | #ifdef _MSC_VER\r |
| 574 | #define cdprintf\r |
| 575 | #else\r |
| 576 | #define cdprintf(x...)\r |
| 577 | #endif\r |
| 578 | \r |
| eff55556 |
579 | #endif // PICO_INTERNAL_INCLUDED\r |
| 580 | \r |
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