spu: get rid of pCurr -1, pass right chans to silent handler
[pcsx_rearmed.git] / libpcsxcore / new_dynarec / new_dynarec.c
CommitLineData
57871462 1/* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
2 * Mupen64plus - new_dynarec.c *
20d507ba 3 * Copyright (C) 2009-2011 Ari64 *
57871462 4 * *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
9 * *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
14 * *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. *
19 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */
20
21#include <stdlib.h>
22#include <stdint.h> //include for uint64_t
23#include <assert.h>
24
3d624f89 25#include "emu_if.h" //emulator interface
57871462 26
27#include <sys/mman.h>
28
29#ifdef __i386__
30#include "assem_x86.h"
31#endif
32#ifdef __x86_64__
33#include "assem_x64.h"
34#endif
35#ifdef __arm__
36#include "assem_arm.h"
37#endif
38
39#define MAXBLOCK 4096
40#define MAX_OUTPUT_BLOCK_SIZE 262144
41#define CLOCK_DIVIDER 2
42
43struct regstat
44{
45 signed char regmap_entry[HOST_REGS];
46 signed char regmap[HOST_REGS];
47 uint64_t was32;
48 uint64_t is32;
49 uint64_t wasdirty;
50 uint64_t dirty;
51 uint64_t u;
52 uint64_t uu;
53 u_int wasconst;
54 u_int isconst;
55 uint64_t constmap[HOST_REGS];
56};
57
58struct ll_entry
59{
60 u_int vaddr;
61 u_int reg32;
62 void *addr;
63 struct ll_entry *next;
64};
65
66 u_int start;
67 u_int *source;
68 u_int pagelimit;
69 char insn[MAXBLOCK][10];
70 u_char itype[MAXBLOCK];
71 u_char opcode[MAXBLOCK];
72 u_char opcode2[MAXBLOCK];
73 u_char bt[MAXBLOCK];
74 u_char rs1[MAXBLOCK];
75 u_char rs2[MAXBLOCK];
76 u_char rt1[MAXBLOCK];
77 u_char rt2[MAXBLOCK];
78 u_char us1[MAXBLOCK];
79 u_char us2[MAXBLOCK];
80 u_char dep1[MAXBLOCK];
81 u_char dep2[MAXBLOCK];
82 u_char lt1[MAXBLOCK];
83 int imm[MAXBLOCK];
84 u_int ba[MAXBLOCK];
85 char likely[MAXBLOCK];
86 char is_ds[MAXBLOCK];
e1190b87 87 char ooo[MAXBLOCK];
57871462 88 uint64_t unneeded_reg[MAXBLOCK];
89 uint64_t unneeded_reg_upper[MAXBLOCK];
90 uint64_t branch_unneeded_reg[MAXBLOCK];
91 uint64_t branch_unneeded_reg_upper[MAXBLOCK];
92 uint64_t p32[MAXBLOCK];
93 uint64_t pr32[MAXBLOCK];
94 signed char regmap_pre[MAXBLOCK][HOST_REGS];
95 signed char regmap[MAXBLOCK][HOST_REGS];
96 signed char regmap_entry[MAXBLOCK][HOST_REGS];
97 uint64_t constmap[MAXBLOCK][HOST_REGS];
57871462 98 struct regstat regs[MAXBLOCK];
99 struct regstat branch_regs[MAXBLOCK];
e1190b87 100 signed char minimum_free_regs[MAXBLOCK];
57871462 101 u_int needed_reg[MAXBLOCK];
102 uint64_t requires_32bit[MAXBLOCK];
103 u_int wont_dirty[MAXBLOCK];
104 u_int will_dirty[MAXBLOCK];
105 int ccadj[MAXBLOCK];
106 int slen;
107 u_int instr_addr[MAXBLOCK];
108 u_int link_addr[MAXBLOCK][3];
109 int linkcount;
110 u_int stubs[MAXBLOCK*3][8];
111 int stubcount;
112 u_int literals[1024][2];
113 int literalcount;
114 int is_delayslot;
115 int cop1_usable;
116 u_char *out;
117 struct ll_entry *jump_in[4096];
118 struct ll_entry *jump_out[4096];
119 struct ll_entry *jump_dirty[4096];
120 u_int hash_table[65536][4] __attribute__((aligned(16)));
121 char shadow[1048576] __attribute__((aligned(16)));
122 void *copy;
123 int expirep;
af4ee1fe 124#ifndef PCSX
57871462 125 u_int using_tlb;
af4ee1fe 126#else
127 static const u_int using_tlb=0;
128#endif
dadf55f2 129 static u_int sp_in_mirror;
57871462 130 u_int stop_after_jal;
131 extern u_char restore_candidate[512];
132 extern int cycle_count;
133
134 /* registers that may be allocated */
135 /* 1-31 gpr */
136#define HIREG 32 // hi
137#define LOREG 33 // lo
138#define FSREG 34 // FPU status (FCSR)
139#define CSREG 35 // Coprocessor status
140#define CCREG 36 // Cycle count
141#define INVCP 37 // Pointer to invalid_code
619e5ded 142#define MMREG 38 // Pointer to memory_map
143#define ROREG 39 // ram offset (if rdram!=0x80000000)
144#define TEMPREG 40
145#define FTEMP 40 // FPU temporary register
146#define PTEMP 41 // Prefetch temporary register
147#define TLREG 42 // TLB mapping offset
148#define RHASH 43 // Return address hash
149#define RHTBL 44 // Return address hash table address
150#define RTEMP 45 // JR/JALR address register
151#define MAXREG 45
152#define AGEN1 46 // Address generation temporary register
153#define AGEN2 47 // Address generation temporary register
154#define MGEN1 48 // Maptable address generation temporary register
155#define MGEN2 49 // Maptable address generation temporary register
156#define BTREG 50 // Branch target temporary register
57871462 157
158 /* instruction types */
159#define NOP 0 // No operation
160#define LOAD 1 // Load
161#define STORE 2 // Store
162#define LOADLR 3 // Unaligned load
163#define STORELR 4 // Unaligned store
164#define MOV 5 // Move
165#define ALU 6 // Arithmetic/logic
166#define MULTDIV 7 // Multiply/divide
167#define SHIFT 8 // Shift by register
168#define SHIFTIMM 9// Shift by immediate
169#define IMM16 10 // 16-bit immediate
170#define RJUMP 11 // Unconditional jump to register
171#define UJUMP 12 // Unconditional jump
172#define CJUMP 13 // Conditional branch (BEQ/BNE/BGTZ/BLEZ)
173#define SJUMP 14 // Conditional branch (regimm format)
174#define COP0 15 // Coprocessor 0
175#define COP1 16 // Coprocessor 1
176#define C1LS 17 // Coprocessor 1 load/store
177#define FJUMP 18 // Conditional branch (floating point)
178#define FLOAT 19 // Floating point unit
179#define FCONV 20 // Convert integer to float
180#define FCOMP 21 // Floating point compare (sets FSREG)
181#define SYSCALL 22// SYSCALL
182#define OTHER 23 // Other
183#define SPAN 24 // Branch/delay slot spans 2 pages
184#define NI 25 // Not implemented
7139f3c8 185#define HLECALL 26// PCSX fake opcodes for HLE
b9b61529 186#define COP2 27 // Coprocessor 2 move
187#define C2LS 28 // Coprocessor 2 load/store
188#define C2OP 29 // Coprocessor 2 operation
1e973cb0 189#define INTCALL 30// Call interpreter to handle rare corner cases
57871462 190
191 /* stubs */
192#define CC_STUB 1
193#define FP_STUB 2
194#define LOADB_STUB 3
195#define LOADH_STUB 4
196#define LOADW_STUB 5
197#define LOADD_STUB 6
198#define LOADBU_STUB 7
199#define LOADHU_STUB 8
200#define STOREB_STUB 9
201#define STOREH_STUB 10
202#define STOREW_STUB 11
203#define STORED_STUB 12
204#define STORELR_STUB 13
205#define INVCODE_STUB 14
206
207 /* branch codes */
208#define TAKEN 1
209#define NOTTAKEN 2
210#define NULLDS 3
211
212// asm linkage
213int new_recompile_block(int addr);
214void *get_addr_ht(u_int vaddr);
215void invalidate_block(u_int block);
216void invalidate_addr(u_int addr);
217void remove_hash(int vaddr);
218void jump_vaddr();
219void dyna_linker();
220void dyna_linker_ds();
221void verify_code();
222void verify_code_vm();
223void verify_code_ds();
224void cc_interrupt();
225void fp_exception();
226void fp_exception_ds();
227void jump_syscall();
7139f3c8 228void jump_syscall_hle();
57871462 229void jump_eret();
7139f3c8 230void jump_hlecall();
1e973cb0 231void jump_intcall();
7139f3c8 232void new_dyna_leave();
57871462 233
234// TLB
235void TLBWI_new();
236void TLBWR_new();
237void read_nomem_new();
238void read_nomemb_new();
239void read_nomemh_new();
240void read_nomemd_new();
241void write_nomem_new();
242void write_nomemb_new();
243void write_nomemh_new();
244void write_nomemd_new();
245void write_rdram_new();
246void write_rdramb_new();
247void write_rdramh_new();
248void write_rdramd_new();
249extern u_int memory_map[1048576];
250
251// Needed by assembler
252void wb_register(signed char r,signed char regmap[],uint64_t dirty,uint64_t is32);
253void wb_dirtys(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty);
254void wb_needed_dirtys(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr);
255void load_all_regs(signed char i_regmap[]);
256void load_needed_regs(signed char i_regmap[],signed char next_regmap[]);
257void load_regs_entry(int t);
258void load_all_consts(signed char regmap[],int is32,u_int dirty,int i);
259
260int tracedebug=0;
261
262//#define DEBUG_CYCLE_COUNT 1
263
264void nullf() {}
265//#define assem_debug printf
266//#define inv_debug printf
267#define assem_debug nullf
268#define inv_debug nullf
269
94d23bb9 270static void tlb_hacks()
57871462 271{
94d23bb9 272#ifndef DISABLE_TLB
57871462 273 // Goldeneye hack
274 if (strncmp((char *) ROM_HEADER->nom, "GOLDENEYE",9) == 0)
275 {
276 u_int addr;
277 int n;
278 switch (ROM_HEADER->Country_code&0xFF)
279 {
280 case 0x45: // U
281 addr=0x34b30;
282 break;
283 case 0x4A: // J
284 addr=0x34b70;
285 break;
286 case 0x50: // E
287 addr=0x329f0;
288 break;
289 default:
290 // Unknown country code
291 addr=0;
292 break;
293 }
294 u_int rom_addr=(u_int)rom;
295 #ifdef ROM_COPY
296 // Since memory_map is 32-bit, on 64-bit systems the rom needs to be
297 // in the lower 4G of memory to use this hack. Copy it if necessary.
298 if((void *)rom>(void *)0xffffffff) {
299 munmap(ROM_COPY, 67108864);
300 if(mmap(ROM_COPY, 12582912,
301 PROT_READ | PROT_WRITE,
302 MAP_FIXED | MAP_PRIVATE | MAP_ANONYMOUS,
303 -1, 0) <= 0) {printf("mmap() failed\n");}
304 memcpy(ROM_COPY,rom,12582912);
305 rom_addr=(u_int)ROM_COPY;
306 }
307 #endif
308 if(addr) {
309 for(n=0x7F000;n<0x80000;n++) {
310 memory_map[n]=(((u_int)(rom_addr+addr-0x7F000000))>>2)|0x40000000;
311 }
312 }
313 }
94d23bb9 314#endif
57871462 315}
316
94d23bb9 317static u_int get_page(u_int vaddr)
57871462 318{
0ce47d46 319#ifndef PCSX
57871462 320 u_int page=(vaddr^0x80000000)>>12;
0ce47d46 321#else
322 u_int page=vaddr&~0xe0000000;
323 if (page < 0x1000000)
324 page &= ~0x0e00000; // RAM mirrors
325 page>>=12;
326#endif
94d23bb9 327#ifndef DISABLE_TLB
57871462 328 if(page>262143&&tlb_LUT_r[vaddr>>12]) page=(tlb_LUT_r[vaddr>>12]^0x80000000)>>12;
94d23bb9 329#endif
57871462 330 if(page>2048) page=2048+(page&2047);
94d23bb9 331 return page;
332}
333
334static u_int get_vpage(u_int vaddr)
335{
336 u_int vpage=(vaddr^0x80000000)>>12;
337#ifndef DISABLE_TLB
57871462 338 if(vpage>262143&&tlb_LUT_r[vaddr>>12]) vpage&=2047; // jump_dirty uses a hash of the virtual address instead
94d23bb9 339#endif
57871462 340 if(vpage>2048) vpage=2048+(vpage&2047);
94d23bb9 341 return vpage;
342}
343
344// Get address from virtual address
345// This is called from the recompiled JR/JALR instructions
346void *get_addr(u_int vaddr)
347{
348 u_int page=get_page(vaddr);
349 u_int vpage=get_vpage(vaddr);
57871462 350 struct ll_entry *head;
351 //printf("TRACE: count=%d next=%d (get_addr %x,page %d)\n",Count,next_interupt,vaddr,page);
352 head=jump_in[page];
353 while(head!=NULL) {
354 if(head->vaddr==vaddr&&head->reg32==0) {
355 //printf("TRACE: count=%d next=%d (get_addr match %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr);
356 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
357 ht_bin[3]=ht_bin[1];
358 ht_bin[2]=ht_bin[0];
359 ht_bin[1]=(int)head->addr;
360 ht_bin[0]=vaddr;
361 return head->addr;
362 }
363 head=head->next;
364 }
365 head=jump_dirty[vpage];
366 while(head!=NULL) {
367 if(head->vaddr==vaddr&&head->reg32==0) {
368 //printf("TRACE: count=%d next=%d (get_addr match dirty %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr);
369 // Don't restore blocks which are about to expire from the cache
370 if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
371 if(verify_dirty(head->addr)) {
372 //printf("restore candidate: %x (%d) d=%d\n",vaddr,page,invalid_code[vaddr>>12]);
373 invalid_code[vaddr>>12]=0;
374 memory_map[vaddr>>12]|=0x40000000;
375 if(vpage<2048) {
94d23bb9 376#ifndef DISABLE_TLB
57871462 377 if(tlb_LUT_r[vaddr>>12]) {
378 invalid_code[tlb_LUT_r[vaddr>>12]>>12]=0;
379 memory_map[tlb_LUT_r[vaddr>>12]>>12]|=0x40000000;
380 }
94d23bb9 381#endif
57871462 382 restore_candidate[vpage>>3]|=1<<(vpage&7);
383 }
384 else restore_candidate[page>>3]|=1<<(page&7);
385 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
386 if(ht_bin[0]==vaddr) {
387 ht_bin[1]=(int)head->addr; // Replace existing entry
388 }
389 else
390 {
391 ht_bin[3]=ht_bin[1];
392 ht_bin[2]=ht_bin[0];
393 ht_bin[1]=(int)head->addr;
394 ht_bin[0]=vaddr;
395 }
396 return head->addr;
397 }
398 }
399 head=head->next;
400 }
401 //printf("TRACE: count=%d next=%d (get_addr no-match %x)\n",Count,next_interupt,vaddr);
402 int r=new_recompile_block(vaddr);
403 if(r==0) return get_addr(vaddr);
404 // Execute in unmapped page, generate pagefault execption
405 Status|=2;
406 Cause=(vaddr<<31)|0x8;
407 EPC=(vaddr&1)?vaddr-5:vaddr;
408 BadVAddr=(vaddr&~1);
409 Context=(Context&0xFF80000F)|((BadVAddr>>9)&0x007FFFF0);
410 EntryHi=BadVAddr&0xFFFFE000;
411 return get_addr_ht(0x80000000);
412}
413// Look up address in hash table first
414void *get_addr_ht(u_int vaddr)
415{
416 //printf("TRACE: count=%d next=%d (get_addr_ht %x)\n",Count,next_interupt,vaddr);
417 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
418 if(ht_bin[0]==vaddr) return (void *)ht_bin[1];
419 if(ht_bin[2]==vaddr) return (void *)ht_bin[3];
420 return get_addr(vaddr);
421}
422
423void *get_addr_32(u_int vaddr,u_int flags)
424{
7139f3c8 425#ifdef FORCE32
426 return get_addr(vaddr);
560e4a12 427#else
57871462 428 //printf("TRACE: count=%d next=%d (get_addr_32 %x,flags %x)\n",Count,next_interupt,vaddr,flags);
429 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
430 if(ht_bin[0]==vaddr) return (void *)ht_bin[1];
431 if(ht_bin[2]==vaddr) return (void *)ht_bin[3];
94d23bb9 432 u_int page=get_page(vaddr);
433 u_int vpage=get_vpage(vaddr);
57871462 434 struct ll_entry *head;
435 head=jump_in[page];
436 while(head!=NULL) {
437 if(head->vaddr==vaddr&&(head->reg32&flags)==0) {
438 //printf("TRACE: count=%d next=%d (get_addr_32 match %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr);
439 if(head->reg32==0) {
440 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
441 if(ht_bin[0]==-1) {
442 ht_bin[1]=(int)head->addr;
443 ht_bin[0]=vaddr;
444 }else if(ht_bin[2]==-1) {
445 ht_bin[3]=(int)head->addr;
446 ht_bin[2]=vaddr;
447 }
448 //ht_bin[3]=ht_bin[1];
449 //ht_bin[2]=ht_bin[0];
450 //ht_bin[1]=(int)head->addr;
451 //ht_bin[0]=vaddr;
452 }
453 return head->addr;
454 }
455 head=head->next;
456 }
457 head=jump_dirty[vpage];
458 while(head!=NULL) {
459 if(head->vaddr==vaddr&&(head->reg32&flags)==0) {
460 //printf("TRACE: count=%d next=%d (get_addr_32 match dirty %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr);
461 // Don't restore blocks which are about to expire from the cache
462 if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
463 if(verify_dirty(head->addr)) {
464 //printf("restore candidate: %x (%d) d=%d\n",vaddr,page,invalid_code[vaddr>>12]);
465 invalid_code[vaddr>>12]=0;
466 memory_map[vaddr>>12]|=0x40000000;
467 if(vpage<2048) {
94d23bb9 468#ifndef DISABLE_TLB
57871462 469 if(tlb_LUT_r[vaddr>>12]) {
470 invalid_code[tlb_LUT_r[vaddr>>12]>>12]=0;
471 memory_map[tlb_LUT_r[vaddr>>12]>>12]|=0x40000000;
472 }
94d23bb9 473#endif
57871462 474 restore_candidate[vpage>>3]|=1<<(vpage&7);
475 }
476 else restore_candidate[page>>3]|=1<<(page&7);
477 if(head->reg32==0) {
478 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
479 if(ht_bin[0]==-1) {
480 ht_bin[1]=(int)head->addr;
481 ht_bin[0]=vaddr;
482 }else if(ht_bin[2]==-1) {
483 ht_bin[3]=(int)head->addr;
484 ht_bin[2]=vaddr;
485 }
486 //ht_bin[3]=ht_bin[1];
487 //ht_bin[2]=ht_bin[0];
488 //ht_bin[1]=(int)head->addr;
489 //ht_bin[0]=vaddr;
490 }
491 return head->addr;
492 }
493 }
494 head=head->next;
495 }
496 //printf("TRACE: count=%d next=%d (get_addr_32 no-match %x,flags %x)\n",Count,next_interupt,vaddr,flags);
497 int r=new_recompile_block(vaddr);
498 if(r==0) return get_addr(vaddr);
499 // Execute in unmapped page, generate pagefault execption
500 Status|=2;
501 Cause=(vaddr<<31)|0x8;
502 EPC=(vaddr&1)?vaddr-5:vaddr;
503 BadVAddr=(vaddr&~1);
504 Context=(Context&0xFF80000F)|((BadVAddr>>9)&0x007FFFF0);
505 EntryHi=BadVAddr&0xFFFFE000;
506 return get_addr_ht(0x80000000);
560e4a12 507#endif
57871462 508}
509
510void clear_all_regs(signed char regmap[])
511{
512 int hr;
513 for (hr=0;hr<HOST_REGS;hr++) regmap[hr]=-1;
514}
515
516signed char get_reg(signed char regmap[],int r)
517{
518 int hr;
519 for (hr=0;hr<HOST_REGS;hr++) if(hr!=EXCLUDE_REG&&regmap[hr]==r) return hr;
520 return -1;
521}
522
523// Find a register that is available for two consecutive cycles
524signed char get_reg2(signed char regmap1[],signed char regmap2[],int r)
525{
526 int hr;
527 for (hr=0;hr<HOST_REGS;hr++) if(hr!=EXCLUDE_REG&&regmap1[hr]==r&&regmap2[hr]==r) return hr;
528 return -1;
529}
530
531int count_free_regs(signed char regmap[])
532{
533 int count=0;
534 int hr;
535 for(hr=0;hr<HOST_REGS;hr++)
536 {
537 if(hr!=EXCLUDE_REG) {
538 if(regmap[hr]<0) count++;
539 }
540 }
541 return count;
542}
543
544void dirty_reg(struct regstat *cur,signed char reg)
545{
546 int hr;
547 if(!reg) return;
548 for (hr=0;hr<HOST_REGS;hr++) {
549 if((cur->regmap[hr]&63)==reg) {
550 cur->dirty|=1<<hr;
551 }
552 }
553}
554
555// If we dirty the lower half of a 64 bit register which is now being
556// sign-extended, we need to dump the upper half.
557// Note: Do this only after completion of the instruction, because
558// some instructions may need to read the full 64-bit value even if
559// overwriting it (eg SLTI, DSRA32).
560static void flush_dirty_uppers(struct regstat *cur)
561{
562 int hr,reg;
563 for (hr=0;hr<HOST_REGS;hr++) {
564 if((cur->dirty>>hr)&1) {
565 reg=cur->regmap[hr];
566 if(reg>=64)
567 if((cur->is32>>(reg&63))&1) cur->regmap[hr]=-1;
568 }
569 }
570}
571
572void set_const(struct regstat *cur,signed char reg,uint64_t value)
573{
574 int hr;
575 if(!reg) return;
576 for (hr=0;hr<HOST_REGS;hr++) {
577 if(cur->regmap[hr]==reg) {
578 cur->isconst|=1<<hr;
579 cur->constmap[hr]=value;
580 }
581 else if((cur->regmap[hr]^64)==reg) {
582 cur->isconst|=1<<hr;
583 cur->constmap[hr]=value>>32;
584 }
585 }
586}
587
588void clear_const(struct regstat *cur,signed char reg)
589{
590 int hr;
591 if(!reg) return;
592 for (hr=0;hr<HOST_REGS;hr++) {
593 if((cur->regmap[hr]&63)==reg) {
594 cur->isconst&=~(1<<hr);
595 }
596 }
597}
598
599int is_const(struct regstat *cur,signed char reg)
600{
601 int hr;
79c75f1b 602 if(reg<0) return 0;
57871462 603 if(!reg) return 1;
604 for (hr=0;hr<HOST_REGS;hr++) {
605 if((cur->regmap[hr]&63)==reg) {
606 return (cur->isconst>>hr)&1;
607 }
608 }
609 return 0;
610}
611uint64_t get_const(struct regstat *cur,signed char reg)
612{
613 int hr;
614 if(!reg) return 0;
615 for (hr=0;hr<HOST_REGS;hr++) {
616 if(cur->regmap[hr]==reg) {
617 return cur->constmap[hr];
618 }
619 }
620 printf("Unknown constant in r%d\n",reg);
621 exit(1);
622}
623
624// Least soon needed registers
625// Look at the next ten instructions and see which registers
626// will be used. Try not to reallocate these.
627void lsn(u_char hsn[], int i, int *preferred_reg)
628{
629 int j;
630 int b=-1;
631 for(j=0;j<9;j++)
632 {
633 if(i+j>=slen) {
634 j=slen-i-1;
635 break;
636 }
637 if(itype[i+j]==UJUMP||itype[i+j]==RJUMP||(source[i+j]>>16)==0x1000)
638 {
639 // Don't go past an unconditonal jump
640 j++;
641 break;
642 }
643 }
644 for(;j>=0;j--)
645 {
646 if(rs1[i+j]) hsn[rs1[i+j]]=j;
647 if(rs2[i+j]) hsn[rs2[i+j]]=j;
648 if(rt1[i+j]) hsn[rt1[i+j]]=j;
649 if(rt2[i+j]) hsn[rt2[i+j]]=j;
650 if(itype[i+j]==STORE || itype[i+j]==STORELR) {
651 // Stores can allocate zero
652 hsn[rs1[i+j]]=j;
653 hsn[rs2[i+j]]=j;
654 }
655 // On some architectures stores need invc_ptr
656 #if defined(HOST_IMM8)
b9b61529 657 if(itype[i+j]==STORE || itype[i+j]==STORELR || (opcode[i+j]&0x3b)==0x39 || (opcode[i+j]&0x3b)==0x3a) {
57871462 658 hsn[INVCP]=j;
659 }
660 #endif
661 if(i+j>=0&&(itype[i+j]==UJUMP||itype[i+j]==CJUMP||itype[i+j]==SJUMP||itype[i+j]==FJUMP))
662 {
663 hsn[CCREG]=j;
664 b=j;
665 }
666 }
667 if(b>=0)
668 {
669 if(ba[i+b]>=start && ba[i+b]<(start+slen*4))
670 {
671 // Follow first branch
672 int t=(ba[i+b]-start)>>2;
673 j=7-b;if(t+j>=slen) j=slen-t-1;
674 for(;j>=0;j--)
675 {
676 if(rs1[t+j]) if(hsn[rs1[t+j]]>j+b+2) hsn[rs1[t+j]]=j+b+2;
677 if(rs2[t+j]) if(hsn[rs2[t+j]]>j+b+2) hsn[rs2[t+j]]=j+b+2;
678 //if(rt1[t+j]) if(hsn[rt1[t+j]]>j+b+2) hsn[rt1[t+j]]=j+b+2;
679 //if(rt2[t+j]) if(hsn[rt2[t+j]]>j+b+2) hsn[rt2[t+j]]=j+b+2;
680 }
681 }
682 // TODO: preferred register based on backward branch
683 }
684 // Delay slot should preferably not overwrite branch conditions or cycle count
685 if(i>0&&(itype[i-1]==RJUMP||itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP)) {
686 if(rs1[i-1]) if(hsn[rs1[i-1]]>1) hsn[rs1[i-1]]=1;
687 if(rs2[i-1]) if(hsn[rs2[i-1]]>1) hsn[rs2[i-1]]=1;
688 hsn[CCREG]=1;
689 // ...or hash tables
690 hsn[RHASH]=1;
691 hsn[RHTBL]=1;
692 }
693 // Coprocessor load/store needs FTEMP, even if not declared
b9b61529 694 if(itype[i]==C1LS||itype[i]==C2LS) {
57871462 695 hsn[FTEMP]=0;
696 }
697 // Load L/R also uses FTEMP as a temporary register
698 if(itype[i]==LOADLR) {
699 hsn[FTEMP]=0;
700 }
b7918751 701 // Also SWL/SWR/SDL/SDR
702 if(opcode[i]==0x2a||opcode[i]==0x2e||opcode[i]==0x2c||opcode[i]==0x2d) {
57871462 703 hsn[FTEMP]=0;
704 }
705 // Don't remove the TLB registers either
b9b61529 706 if(itype[i]==LOAD || itype[i]==LOADLR || itype[i]==STORE || itype[i]==STORELR || itype[i]==C1LS || itype[i]==C2LS) {
57871462 707 hsn[TLREG]=0;
708 }
709 // Don't remove the miniht registers
710 if(itype[i]==UJUMP||itype[i]==RJUMP)
711 {
712 hsn[RHASH]=0;
713 hsn[RHTBL]=0;
714 }
715}
716
717// We only want to allocate registers if we're going to use them again soon
718int needed_again(int r, int i)
719{
720 int j;
721 int b=-1;
722 int rn=10;
57871462 723
724 if(i>0&&(itype[i-1]==UJUMP||itype[i-1]==RJUMP||(source[i-1]>>16)==0x1000))
725 {
726 if(ba[i-1]<start || ba[i-1]>start+slen*4-4)
727 return 0; // Don't need any registers if exiting the block
728 }
729 for(j=0;j<9;j++)
730 {
731 if(i+j>=slen) {
732 j=slen-i-1;
733 break;
734 }
735 if(itype[i+j]==UJUMP||itype[i+j]==RJUMP||(source[i+j]>>16)==0x1000)
736 {
737 // Don't go past an unconditonal jump
738 j++;
739 break;
740 }
1e973cb0 741 if(itype[i+j]==SYSCALL||itype[i+j]==HLECALL||itype[i+j]==INTCALL||((source[i+j]&0xfc00003f)==0x0d))
57871462 742 {
743 break;
744 }
745 }
746 for(;j>=1;j--)
747 {
748 if(rs1[i+j]==r) rn=j;
749 if(rs2[i+j]==r) rn=j;
750 if((unneeded_reg[i+j]>>r)&1) rn=10;
751 if(i+j>=0&&(itype[i+j]==UJUMP||itype[i+j]==CJUMP||itype[i+j]==SJUMP||itype[i+j]==FJUMP))
752 {
753 b=j;
754 }
755 }
756 /*
757 if(b>=0)
758 {
759 if(ba[i+b]>=start && ba[i+b]<(start+slen*4))
760 {
761 // Follow first branch
762 int o=rn;
763 int t=(ba[i+b]-start)>>2;
764 j=7-b;if(t+j>=slen) j=slen-t-1;
765 for(;j>=0;j--)
766 {
767 if(!((unneeded_reg[t+j]>>r)&1)) {
768 if(rs1[t+j]==r) if(rn>j+b+2) rn=j+b+2;
769 if(rs2[t+j]==r) if(rn>j+b+2) rn=j+b+2;
770 }
771 else rn=o;
772 }
773 }
774 }*/
b7217e13 775 if(rn<10) return 1;
57871462 776 return 0;
777}
778
779// Try to match register allocations at the end of a loop with those
780// at the beginning
781int loop_reg(int i, int r, int hr)
782{
783 int j,k;
784 for(j=0;j<9;j++)
785 {
786 if(i+j>=slen) {
787 j=slen-i-1;
788 break;
789 }
790 if(itype[i+j]==UJUMP||itype[i+j]==RJUMP||(source[i+j]>>16)==0x1000)
791 {
792 // Don't go past an unconditonal jump
793 j++;
794 break;
795 }
796 }
797 k=0;
798 if(i>0){
799 if(itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP)
800 k--;
801 }
802 for(;k<j;k++)
803 {
804 if(r<64&&((unneeded_reg[i+k]>>r)&1)) return hr;
805 if(r>64&&((unneeded_reg_upper[i+k]>>r)&1)) return hr;
806 if(i+k>=0&&(itype[i+k]==UJUMP||itype[i+k]==CJUMP||itype[i+k]==SJUMP||itype[i+k]==FJUMP))
807 {
808 if(ba[i+k]>=start && ba[i+k]<(start+i*4))
809 {
810 int t=(ba[i+k]-start)>>2;
811 int reg=get_reg(regs[t].regmap_entry,r);
812 if(reg>=0) return reg;
813 //reg=get_reg(regs[t+1].regmap_entry,r);
814 //if(reg>=0) return reg;
815 }
816 }
817 }
818 return hr;
819}
820
821
822// Allocate every register, preserving source/target regs
823void alloc_all(struct regstat *cur,int i)
824{
825 int hr;
826
827 for(hr=0;hr<HOST_REGS;hr++) {
828 if(hr!=EXCLUDE_REG) {
829 if(((cur->regmap[hr]&63)!=rs1[i])&&((cur->regmap[hr]&63)!=rs2[i])&&
830 ((cur->regmap[hr]&63)!=rt1[i])&&((cur->regmap[hr]&63)!=rt2[i]))
831 {
832 cur->regmap[hr]=-1;
833 cur->dirty&=~(1<<hr);
834 }
835 // Don't need zeros
836 if((cur->regmap[hr]&63)==0)
837 {
838 cur->regmap[hr]=-1;
839 cur->dirty&=~(1<<hr);
840 }
841 }
842 }
843}
844
845
846void div64(int64_t dividend,int64_t divisor)
847{
848 lo=dividend/divisor;
849 hi=dividend%divisor;
850 //printf("TRACE: ddiv %8x%8x %8x%8x\n" ,(int)reg[HIREG],(int)(reg[HIREG]>>32)
851 // ,(int)reg[LOREG],(int)(reg[LOREG]>>32));
852}
853void divu64(uint64_t dividend,uint64_t divisor)
854{
855 lo=dividend/divisor;
856 hi=dividend%divisor;
857 //printf("TRACE: ddivu %8x%8x %8x%8x\n",(int)reg[HIREG],(int)(reg[HIREG]>>32)
858 // ,(int)reg[LOREG],(int)(reg[LOREG]>>32));
859}
860
861void mult64(uint64_t m1,uint64_t m2)
862{
863 unsigned long long int op1, op2, op3, op4;
864 unsigned long long int result1, result2, result3, result4;
865 unsigned long long int temp1, temp2, temp3, temp4;
866 int sign = 0;
867
868 if (m1 < 0)
869 {
870 op2 = -m1;
871 sign = 1 - sign;
872 }
873 else op2 = m1;
874 if (m2 < 0)
875 {
876 op4 = -m2;
877 sign = 1 - sign;
878 }
879 else op4 = m2;
880
881 op1 = op2 & 0xFFFFFFFF;
882 op2 = (op2 >> 32) & 0xFFFFFFFF;
883 op3 = op4 & 0xFFFFFFFF;
884 op4 = (op4 >> 32) & 0xFFFFFFFF;
885
886 temp1 = op1 * op3;
887 temp2 = (temp1 >> 32) + op1 * op4;
888 temp3 = op2 * op3;
889 temp4 = (temp3 >> 32) + op2 * op4;
890
891 result1 = temp1 & 0xFFFFFFFF;
892 result2 = temp2 + (temp3 & 0xFFFFFFFF);
893 result3 = (result2 >> 32) + temp4;
894 result4 = (result3 >> 32);
895
896 lo = result1 | (result2 << 32);
897 hi = (result3 & 0xFFFFFFFF) | (result4 << 32);
898 if (sign)
899 {
900 hi = ~hi;
901 if (!lo) hi++;
902 else lo = ~lo + 1;
903 }
904}
905
906void multu64(uint64_t m1,uint64_t m2)
907{
908 unsigned long long int op1, op2, op3, op4;
909 unsigned long long int result1, result2, result3, result4;
910 unsigned long long int temp1, temp2, temp3, temp4;
911
912 op1 = m1 & 0xFFFFFFFF;
913 op2 = (m1 >> 32) & 0xFFFFFFFF;
914 op3 = m2 & 0xFFFFFFFF;
915 op4 = (m2 >> 32) & 0xFFFFFFFF;
916
917 temp1 = op1 * op3;
918 temp2 = (temp1 >> 32) + op1 * op4;
919 temp3 = op2 * op3;
920 temp4 = (temp3 >> 32) + op2 * op4;
921
922 result1 = temp1 & 0xFFFFFFFF;
923 result2 = temp2 + (temp3 & 0xFFFFFFFF);
924 result3 = (result2 >> 32) + temp4;
925 result4 = (result3 >> 32);
926
927 lo = result1 | (result2 << 32);
928 hi = (result3 & 0xFFFFFFFF) | (result4 << 32);
929
930 //printf("TRACE: dmultu %8x%8x %8x%8x\n",(int)reg[HIREG],(int)(reg[HIREG]>>32)
931 // ,(int)reg[LOREG],(int)(reg[LOREG]>>32));
932}
933
934uint64_t ldl_merge(uint64_t original,uint64_t loaded,u_int bits)
935{
936 if(bits) {
937 original<<=64-bits;
938 original>>=64-bits;
939 loaded<<=bits;
940 original|=loaded;
941 }
942 else original=loaded;
943 return original;
944}
945uint64_t ldr_merge(uint64_t original,uint64_t loaded,u_int bits)
946{
947 if(bits^56) {
948 original>>=64-(bits^56);
949 original<<=64-(bits^56);
950 loaded>>=bits^56;
951 original|=loaded;
952 }
953 else original=loaded;
954 return original;
955}
956
957#ifdef __i386__
958#include "assem_x86.c"
959#endif
960#ifdef __x86_64__
961#include "assem_x64.c"
962#endif
963#ifdef __arm__
964#include "assem_arm.c"
965#endif
966
967// Add virtual address mapping to linked list
968void ll_add(struct ll_entry **head,int vaddr,void *addr)
969{
970 struct ll_entry *new_entry;
971 new_entry=malloc(sizeof(struct ll_entry));
972 assert(new_entry!=NULL);
973 new_entry->vaddr=vaddr;
974 new_entry->reg32=0;
975 new_entry->addr=addr;
976 new_entry->next=*head;
977 *head=new_entry;
978}
979
980// Add virtual address mapping for 32-bit compiled block
981void ll_add_32(struct ll_entry **head,int vaddr,u_int reg32,void *addr)
982{
7139f3c8 983 ll_add(head,vaddr,addr);
984#ifndef FORCE32
985 (*head)->reg32=reg32;
986#endif
57871462 987}
988
989// Check if an address is already compiled
990// but don't return addresses which are about to expire from the cache
991void *check_addr(u_int vaddr)
992{
993 u_int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
994 if(ht_bin[0]==vaddr) {
995 if(((ht_bin[1]-MAX_OUTPUT_BLOCK_SIZE-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
996 if(isclean(ht_bin[1])) return (void *)ht_bin[1];
997 }
998 if(ht_bin[2]==vaddr) {
999 if(((ht_bin[3]-MAX_OUTPUT_BLOCK_SIZE-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
1000 if(isclean(ht_bin[3])) return (void *)ht_bin[3];
1001 }
94d23bb9 1002 u_int page=get_page(vaddr);
57871462 1003 struct ll_entry *head;
1004 head=jump_in[page];
1005 while(head!=NULL) {
1006 if(head->vaddr==vaddr&&head->reg32==0) {
1007 if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2))) {
1008 // Update existing entry with current address
1009 if(ht_bin[0]==vaddr) {
1010 ht_bin[1]=(int)head->addr;
1011 return head->addr;
1012 }
1013 if(ht_bin[2]==vaddr) {
1014 ht_bin[3]=(int)head->addr;
1015 return head->addr;
1016 }
1017 // Insert into hash table with low priority.
1018 // Don't evict existing entries, as they are probably
1019 // addresses that are being accessed frequently.
1020 if(ht_bin[0]==-1) {
1021 ht_bin[1]=(int)head->addr;
1022 ht_bin[0]=vaddr;
1023 }else if(ht_bin[2]==-1) {
1024 ht_bin[3]=(int)head->addr;
1025 ht_bin[2]=vaddr;
1026 }
1027 return head->addr;
1028 }
1029 }
1030 head=head->next;
1031 }
1032 return 0;
1033}
1034
1035void remove_hash(int vaddr)
1036{
1037 //printf("remove hash: %x\n",vaddr);
1038 int *ht_bin=hash_table[(((vaddr)>>16)^vaddr)&0xFFFF];
1039 if(ht_bin[2]==vaddr) {
1040 ht_bin[2]=ht_bin[3]=-1;
1041 }
1042 if(ht_bin[0]==vaddr) {
1043 ht_bin[0]=ht_bin[2];
1044 ht_bin[1]=ht_bin[3];
1045 ht_bin[2]=ht_bin[3]=-1;
1046 }
1047}
1048
1049void ll_remove_matching_addrs(struct ll_entry **head,int addr,int shift)
1050{
1051 struct ll_entry *next;
1052 while(*head) {
1053 if(((u_int)((*head)->addr)>>shift)==(addr>>shift) ||
1054 ((u_int)((*head)->addr-MAX_OUTPUT_BLOCK_SIZE)>>shift)==(addr>>shift))
1055 {
1056 inv_debug("EXP: Remove pointer to %x (%x)\n",(int)(*head)->addr,(*head)->vaddr);
1057 remove_hash((*head)->vaddr);
1058 next=(*head)->next;
1059 free(*head);
1060 *head=next;
1061 }
1062 else
1063 {
1064 head=&((*head)->next);
1065 }
1066 }
1067}
1068
1069// Remove all entries from linked list
1070void ll_clear(struct ll_entry **head)
1071{
1072 struct ll_entry *cur;
1073 struct ll_entry *next;
1074 if(cur=*head) {
1075 *head=0;
1076 while(cur) {
1077 next=cur->next;
1078 free(cur);
1079 cur=next;
1080 }
1081 }
1082}
1083
1084// Dereference the pointers and remove if it matches
1085void ll_kill_pointers(struct ll_entry *head,int addr,int shift)
1086{
1087 while(head) {
1088 int ptr=get_pointer(head->addr);
1089 inv_debug("EXP: Lookup pointer to %x at %x (%x)\n",(int)ptr,(int)head->addr,head->vaddr);
1090 if(((ptr>>shift)==(addr>>shift)) ||
1091 (((ptr-MAX_OUTPUT_BLOCK_SIZE)>>shift)==(addr>>shift)))
1092 {
5088bb70 1093 inv_debug("EXP: Kill pointer at %x (%x)\n",(int)head->addr,head->vaddr);
f76eeef9 1094 u_int host_addr=(u_int)kill_pointer(head->addr);
dd3a91a1 1095 #ifdef __arm__
1096 needs_clear_cache[(host_addr-(u_int)BASE_ADDR)>>17]|=1<<(((host_addr-(u_int)BASE_ADDR)>>12)&31);
1097 #endif
57871462 1098 }
1099 head=head->next;
1100 }
1101}
1102
1103// This is called when we write to a compiled block (see do_invstub)
f76eeef9 1104void invalidate_page(u_int page)
57871462 1105{
57871462 1106 struct ll_entry *head;
1107 struct ll_entry *next;
1108 head=jump_in[page];
1109 jump_in[page]=0;
1110 while(head!=NULL) {
1111 inv_debug("INVALIDATE: %x\n",head->vaddr);
1112 remove_hash(head->vaddr);
1113 next=head->next;
1114 free(head);
1115 head=next;
1116 }
1117 head=jump_out[page];
1118 jump_out[page]=0;
1119 while(head!=NULL) {
1120 inv_debug("INVALIDATE: kill pointer to %x (%x)\n",head->vaddr,(int)head->addr);
f76eeef9 1121 u_int host_addr=(u_int)kill_pointer(head->addr);
dd3a91a1 1122 #ifdef __arm__
1123 needs_clear_cache[(host_addr-(u_int)BASE_ADDR)>>17]|=1<<(((host_addr-(u_int)BASE_ADDR)>>12)&31);
1124 #endif
57871462 1125 next=head->next;
1126 free(head);
1127 head=next;
1128 }
57871462 1129}
1130void invalidate_block(u_int block)
1131{
94d23bb9 1132 u_int page=get_page(block<<12);
1133 u_int vpage=get_vpage(block<<12);
57871462 1134 inv_debug("INVALIDATE: %x (%d)\n",block<<12,page);
1135 //inv_debug("invalid_code[block]=%d\n",invalid_code[block]);
1136 u_int first,last;
1137 first=last=page;
1138 struct ll_entry *head;
1139 head=jump_dirty[vpage];
1140 //printf("page=%d vpage=%d\n",page,vpage);
1141 while(head!=NULL) {
1142 u_int start,end;
1143 if(vpage>2047||(head->vaddr>>12)==block) { // Ignore vaddr hash collision
1144 get_bounds((int)head->addr,&start,&end);
1145 //printf("start: %x end: %x\n",start,end);
4cb76aa4 1146 if(page<2048&&start>=0x80000000&&end<0x80000000+RAM_SIZE) {
57871462 1147 if(((start-(u_int)rdram)>>12)<=page&&((end-1-(u_int)rdram)>>12)>=page) {
1148 if((((start-(u_int)rdram)>>12)&2047)<first) first=((start-(u_int)rdram)>>12)&2047;
1149 if((((end-1-(u_int)rdram)>>12)&2047)>last) last=((end-1-(u_int)rdram)>>12)&2047;
1150 }
1151 }
90ae6d4e 1152#ifndef DISABLE_TLB
57871462 1153 if(page<2048&&(signed int)start>=(signed int)0xC0000000&&(signed int)end>=(signed int)0xC0000000) {
1154 if(((start+memory_map[start>>12]-(u_int)rdram)>>12)<=page&&((end-1+memory_map[(end-1)>>12]-(u_int)rdram)>>12)>=page) {
1155 if((((start+memory_map[start>>12]-(u_int)rdram)>>12)&2047)<first) first=((start+memory_map[start>>12]-(u_int)rdram)>>12)&2047;
1156 if((((end-1+memory_map[(end-1)>>12]-(u_int)rdram)>>12)&2047)>last) last=((end-1+memory_map[(end-1)>>12]-(u_int)rdram)>>12)&2047;
1157 }
1158 }
90ae6d4e 1159#endif
57871462 1160 }
1161 head=head->next;
1162 }
1163 //printf("first=%d last=%d\n",first,last);
f76eeef9 1164 invalidate_page(page);
57871462 1165 assert(first+5>page); // NB: this assumes MAXBLOCK<=4096 (4 pages)
1166 assert(last<page+5);
1167 // Invalidate the adjacent pages if a block crosses a 4K boundary
1168 while(first<page) {
1169 invalidate_page(first);
1170 first++;
1171 }
1172 for(first=page+1;first<last;first++) {
1173 invalidate_page(first);
1174 }
dd3a91a1 1175 #ifdef __arm__
1176 do_clear_cache();
1177 #endif
57871462 1178
1179 // Don't trap writes
1180 invalid_code[block]=1;
b12c9fb8 1181#ifdef PCSX
1182 invalid_code[((u_int)0x80000000>>12)|page]=1;
1183#endif
94d23bb9 1184#ifndef DISABLE_TLB
57871462 1185 // If there is a valid TLB entry for this page, remove write protect
1186 if(tlb_LUT_w[block]) {
1187 assert(tlb_LUT_r[block]==tlb_LUT_w[block]);
1188 // CHECK: Is this right?
1189 memory_map[block]=((tlb_LUT_w[block]&0xFFFFF000)-(block<<12)+(unsigned int)rdram-0x80000000)>>2;
1190 u_int real_block=tlb_LUT_w[block]>>12;
1191 invalid_code[real_block]=1;
1192 if(real_block>=0x80000&&real_block<0x80800) memory_map[real_block]=((u_int)rdram-0x80000000)>>2;
1193 }
1194 else if(block>=0x80000&&block<0x80800) memory_map[block]=((u_int)rdram-0x80000000)>>2;
94d23bb9 1195#endif
f76eeef9 1196
57871462 1197 #ifdef USE_MINI_HT
1198 memset(mini_ht,-1,sizeof(mini_ht));
1199 #endif
1200}
1201void invalidate_addr(u_int addr)
1202{
1203 invalidate_block(addr>>12);
1204}
dd3a91a1 1205// This is called when loading a save state.
1206// Anything could have changed, so invalidate everything.
57871462 1207void invalidate_all_pages()
1208{
1209 u_int page,n;
1210 for(page=0;page<4096;page++)
1211 invalidate_page(page);
1212 for(page=0;page<1048576;page++)
1213 if(!invalid_code[page]) {
1214 restore_candidate[(page&2047)>>3]|=1<<(page&7);
1215 restore_candidate[((page&2047)>>3)+256]|=1<<(page&7);
1216 }
1217 #ifdef __arm__
1218 __clear_cache((void *)BASE_ADDR,(void *)BASE_ADDR+(1<<TARGET_SIZE_2));
1219 #endif
1220 #ifdef USE_MINI_HT
1221 memset(mini_ht,-1,sizeof(mini_ht));
1222 #endif
94d23bb9 1223 #ifndef DISABLE_TLB
57871462 1224 // TLB
1225 for(page=0;page<0x100000;page++) {
1226 if(tlb_LUT_r[page]) {
1227 memory_map[page]=((tlb_LUT_r[page]&0xFFFFF000)-(page<<12)+(unsigned int)rdram-0x80000000)>>2;
1228 if(!tlb_LUT_w[page]||!invalid_code[page])
1229 memory_map[page]|=0x40000000; // Write protect
1230 }
1231 else memory_map[page]=-1;
1232 if(page==0x80000) page=0xC0000;
1233 }
1234 tlb_hacks();
94d23bb9 1235 #endif
57871462 1236}
1237
1238// Add an entry to jump_out after making a link
1239void add_link(u_int vaddr,void *src)
1240{
94d23bb9 1241 u_int page=get_page(vaddr);
57871462 1242 inv_debug("add_link: %x -> %x (%d)\n",(int)src,vaddr,page);
76f71c27 1243 int *ptr=(int *)(src+4);
1244 assert((*ptr&0x0fff0000)==0x059f0000);
57871462 1245 ll_add(jump_out+page,vaddr,src);
1246 //int ptr=get_pointer(src);
1247 //inv_debug("add_link: Pointer is to %x\n",(int)ptr);
1248}
1249
1250// If a code block was found to be unmodified (bit was set in
1251// restore_candidate) and it remains unmodified (bit is clear
1252// in invalid_code) then move the entries for that 4K page from
1253// the dirty list to the clean list.
1254void clean_blocks(u_int page)
1255{
1256 struct ll_entry *head;
1257 inv_debug("INV: clean_blocks page=%d\n",page);
1258 head=jump_dirty[page];
1259 while(head!=NULL) {
1260 if(!invalid_code[head->vaddr>>12]) {
1261 // Don't restore blocks which are about to expire from the cache
1262 if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2))) {
1263 u_int start,end;
1264 if(verify_dirty((int)head->addr)) {
1265 //printf("Possibly Restore %x (%x)\n",head->vaddr, (int)head->addr);
1266 u_int i;
1267 u_int inv=0;
1268 get_bounds((int)head->addr,&start,&end);
4cb76aa4 1269 if(start-(u_int)rdram<RAM_SIZE) {
57871462 1270 for(i=(start-(u_int)rdram+0x80000000)>>12;i<=(end-1-(u_int)rdram+0x80000000)>>12;i++) {
1271 inv|=invalid_code[i];
1272 }
1273 }
1274 if((signed int)head->vaddr>=(signed int)0xC0000000) {
1275 u_int addr = (head->vaddr+(memory_map[head->vaddr>>12]<<2));
1276 //printf("addr=%x start=%x end=%x\n",addr,start,end);
1277 if(addr<start||addr>=end) inv=1;
1278 }
4cb76aa4 1279 else if((signed int)head->vaddr>=(signed int)0x80000000+RAM_SIZE) {
57871462 1280 inv=1;
1281 }
1282 if(!inv) {
1283 void * clean_addr=(void *)get_clean_addr((int)head->addr);
1284 if((((u_int)clean_addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2))) {
1285 u_int ppage=page;
94d23bb9 1286#ifndef DISABLE_TLB
57871462 1287 if(page<2048&&tlb_LUT_r[head->vaddr>>12]) ppage=(tlb_LUT_r[head->vaddr>>12]^0x80000000)>>12;
94d23bb9 1288#endif
57871462 1289 inv_debug("INV: Restored %x (%x/%x)\n",head->vaddr, (int)head->addr, (int)clean_addr);
1290 //printf("page=%x, addr=%x\n",page,head->vaddr);
1291 //assert(head->vaddr>>12==(page|0x80000));
1292 ll_add_32(jump_in+ppage,head->vaddr,head->reg32,clean_addr);
1293 int *ht_bin=hash_table[((head->vaddr>>16)^head->vaddr)&0xFFFF];
1294 if(!head->reg32) {
1295 if(ht_bin[0]==head->vaddr) {
1296 ht_bin[1]=(int)clean_addr; // Replace existing entry
1297 }
1298 if(ht_bin[2]==head->vaddr) {
1299 ht_bin[3]=(int)clean_addr; // Replace existing entry
1300 }
1301 }
1302 }
1303 }
1304 }
1305 }
1306 }
1307 head=head->next;
1308 }
1309}
1310
1311
1312void mov_alloc(struct regstat *current,int i)
1313{
1314 // Note: Don't need to actually alloc the source registers
1315 if((~current->is32>>rs1[i])&1) {
1316 //alloc_reg64(current,i,rs1[i]);
1317 alloc_reg64(current,i,rt1[i]);
1318 current->is32&=~(1LL<<rt1[i]);
1319 } else {
1320 //alloc_reg(current,i,rs1[i]);
1321 alloc_reg(current,i,rt1[i]);
1322 current->is32|=(1LL<<rt1[i]);
1323 }
1324 clear_const(current,rs1[i]);
1325 clear_const(current,rt1[i]);
1326 dirty_reg(current,rt1[i]);
1327}
1328
1329void shiftimm_alloc(struct regstat *current,int i)
1330{
1331 clear_const(current,rs1[i]);
1332 clear_const(current,rt1[i]);
1333 if(opcode2[i]<=0x3) // SLL/SRL/SRA
1334 {
1335 if(rt1[i]) {
1336 if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1337 else lt1[i]=rs1[i];
1338 alloc_reg(current,i,rt1[i]);
1339 current->is32|=1LL<<rt1[i];
1340 dirty_reg(current,rt1[i]);
1341 }
1342 }
1343 if(opcode2[i]>=0x38&&opcode2[i]<=0x3b) // DSLL/DSRL/DSRA
1344 {
1345 if(rt1[i]) {
1346 if(rs1[i]) alloc_reg64(current,i,rs1[i]);
1347 alloc_reg64(current,i,rt1[i]);
1348 current->is32&=~(1LL<<rt1[i]);
1349 dirty_reg(current,rt1[i]);
1350 }
1351 }
1352 if(opcode2[i]==0x3c) // DSLL32
1353 {
1354 if(rt1[i]) {
1355 if(rs1[i]) alloc_reg(current,i,rs1[i]);
1356 alloc_reg64(current,i,rt1[i]);
1357 current->is32&=~(1LL<<rt1[i]);
1358 dirty_reg(current,rt1[i]);
1359 }
1360 }
1361 if(opcode2[i]==0x3e) // DSRL32
1362 {
1363 if(rt1[i]) {
1364 alloc_reg64(current,i,rs1[i]);
1365 if(imm[i]==32) {
1366 alloc_reg64(current,i,rt1[i]);
1367 current->is32&=~(1LL<<rt1[i]);
1368 } else {
1369 alloc_reg(current,i,rt1[i]);
1370 current->is32|=1LL<<rt1[i];
1371 }
1372 dirty_reg(current,rt1[i]);
1373 }
1374 }
1375 if(opcode2[i]==0x3f) // DSRA32
1376 {
1377 if(rt1[i]) {
1378 alloc_reg64(current,i,rs1[i]);
1379 alloc_reg(current,i,rt1[i]);
1380 current->is32|=1LL<<rt1[i];
1381 dirty_reg(current,rt1[i]);
1382 }
1383 }
1384}
1385
1386void shift_alloc(struct regstat *current,int i)
1387{
1388 if(rt1[i]) {
1389 if(opcode2[i]<=0x07) // SLLV/SRLV/SRAV
1390 {
1391 if(rs1[i]) alloc_reg(current,i,rs1[i]);
1392 if(rs2[i]) alloc_reg(current,i,rs2[i]);
1393 alloc_reg(current,i,rt1[i]);
e1190b87 1394 if(rt1[i]==rs2[i]) {
1395 alloc_reg_temp(current,i,-1);
1396 minimum_free_regs[i]=1;
1397 }
57871462 1398 current->is32|=1LL<<rt1[i];
1399 } else { // DSLLV/DSRLV/DSRAV
1400 if(rs1[i]) alloc_reg64(current,i,rs1[i]);
1401 if(rs2[i]) alloc_reg(current,i,rs2[i]);
1402 alloc_reg64(current,i,rt1[i]);
1403 current->is32&=~(1LL<<rt1[i]);
1404 if(opcode2[i]==0x16||opcode2[i]==0x17) // DSRLV and DSRAV need a temporary register
e1190b87 1405 {
57871462 1406 alloc_reg_temp(current,i,-1);
e1190b87 1407 minimum_free_regs[i]=1;
1408 }
57871462 1409 }
1410 clear_const(current,rs1[i]);
1411 clear_const(current,rs2[i]);
1412 clear_const(current,rt1[i]);
1413 dirty_reg(current,rt1[i]);
1414 }
1415}
1416
1417void alu_alloc(struct regstat *current,int i)
1418{
1419 if(opcode2[i]>=0x20&&opcode2[i]<=0x23) { // ADD/ADDU/SUB/SUBU
1420 if(rt1[i]) {
1421 if(rs1[i]&&rs2[i]) {
1422 alloc_reg(current,i,rs1[i]);
1423 alloc_reg(current,i,rs2[i]);
1424 }
1425 else {
1426 if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1427 if(rs2[i]&&needed_again(rs2[i],i)) alloc_reg(current,i,rs2[i]);
1428 }
1429 alloc_reg(current,i,rt1[i]);
1430 }
1431 current->is32|=1LL<<rt1[i];
1432 }
1433 if(opcode2[i]==0x2a||opcode2[i]==0x2b) { // SLT/SLTU
1434 if(rt1[i]) {
1435 if(!((current->is32>>rs1[i])&(current->is32>>rs2[i])&1))
1436 {
1437 alloc_reg64(current,i,rs1[i]);
1438 alloc_reg64(current,i,rs2[i]);
1439 alloc_reg(current,i,rt1[i]);
1440 } else {
1441 alloc_reg(current,i,rs1[i]);
1442 alloc_reg(current,i,rs2[i]);
1443 alloc_reg(current,i,rt1[i]);
1444 }
1445 }
1446 current->is32|=1LL<<rt1[i];
1447 }
1448 if(opcode2[i]>=0x24&&opcode2[i]<=0x27) { // AND/OR/XOR/NOR
1449 if(rt1[i]) {
1450 if(rs1[i]&&rs2[i]) {
1451 alloc_reg(current,i,rs1[i]);
1452 alloc_reg(current,i,rs2[i]);
1453 }
1454 else
1455 {
1456 if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1457 if(rs2[i]&&needed_again(rs2[i],i)) alloc_reg(current,i,rs2[i]);
1458 }
1459 alloc_reg(current,i,rt1[i]);
1460 if(!((current->is32>>rs1[i])&(current->is32>>rs2[i])&1))
1461 {
1462 if(!((current->uu>>rt1[i])&1)) {
1463 alloc_reg64(current,i,rt1[i]);
1464 }
1465 if(get_reg(current->regmap,rt1[i]|64)>=0) {
1466 if(rs1[i]&&rs2[i]) {
1467 alloc_reg64(current,i,rs1[i]);
1468 alloc_reg64(current,i,rs2[i]);
1469 }
1470 else
1471 {
1472 // Is is really worth it to keep 64-bit values in registers?
1473 #ifdef NATIVE_64BIT
1474 if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg64(current,i,rs1[i]);
1475 if(rs2[i]&&needed_again(rs2[i],i)) alloc_reg64(current,i,rs2[i]);
1476 #endif
1477 }
1478 }
1479 current->is32&=~(1LL<<rt1[i]);
1480 } else {
1481 current->is32|=1LL<<rt1[i];
1482 }
1483 }
1484 }
1485 if(opcode2[i]>=0x2c&&opcode2[i]<=0x2f) { // DADD/DADDU/DSUB/DSUBU
1486 if(rt1[i]) {
1487 if(rs1[i]&&rs2[i]) {
1488 if(!((current->uu>>rt1[i])&1)||get_reg(current->regmap,rt1[i]|64)>=0) {
1489 alloc_reg64(current,i,rs1[i]);
1490 alloc_reg64(current,i,rs2[i]);
1491 alloc_reg64(current,i,rt1[i]);
1492 } else {
1493 alloc_reg(current,i,rs1[i]);
1494 alloc_reg(current,i,rs2[i]);
1495 alloc_reg(current,i,rt1[i]);
1496 }
1497 }
1498 else {
1499 alloc_reg(current,i,rt1[i]);
1500 if(!((current->uu>>rt1[i])&1)||get_reg(current->regmap,rt1[i]|64)>=0) {
1501 // DADD used as move, or zeroing
1502 // If we have a 64-bit source, then make the target 64 bits too
1503 if(rs1[i]&&!((current->is32>>rs1[i])&1)) {
1504 if(get_reg(current->regmap,rs1[i])>=0) alloc_reg64(current,i,rs1[i]);
1505 alloc_reg64(current,i,rt1[i]);
1506 } else if(rs2[i]&&!((current->is32>>rs2[i])&1)) {
1507 if(get_reg(current->regmap,rs2[i])>=0) alloc_reg64(current,i,rs2[i]);
1508 alloc_reg64(current,i,rt1[i]);
1509 }
1510 if(opcode2[i]>=0x2e&&rs2[i]) {
1511 // DSUB used as negation - 64-bit result
1512 // If we have a 32-bit register, extend it to 64 bits
1513 if(get_reg(current->regmap,rs2[i])>=0) alloc_reg64(current,i,rs2[i]);
1514 alloc_reg64(current,i,rt1[i]);
1515 }
1516 }
1517 }
1518 if(rs1[i]&&rs2[i]) {
1519 current->is32&=~(1LL<<rt1[i]);
1520 } else if(rs1[i]) {
1521 current->is32&=~(1LL<<rt1[i]);
1522 if((current->is32>>rs1[i])&1)
1523 current->is32|=1LL<<rt1[i];
1524 } else if(rs2[i]) {
1525 current->is32&=~(1LL<<rt1[i]);
1526 if((current->is32>>rs2[i])&1)
1527 current->is32|=1LL<<rt1[i];
1528 } else {
1529 current->is32|=1LL<<rt1[i];
1530 }
1531 }
1532 }
1533 clear_const(current,rs1[i]);
1534 clear_const(current,rs2[i]);
1535 clear_const(current,rt1[i]);
1536 dirty_reg(current,rt1[i]);
1537}
1538
1539void imm16_alloc(struct regstat *current,int i)
1540{
1541 if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1542 else lt1[i]=rs1[i];
1543 if(rt1[i]) alloc_reg(current,i,rt1[i]);
1544 if(opcode[i]==0x18||opcode[i]==0x19) { // DADDI/DADDIU
1545 current->is32&=~(1LL<<rt1[i]);
1546 if(!((current->uu>>rt1[i])&1)||get_reg(current->regmap,rt1[i]|64)>=0) {
1547 // TODO: Could preserve the 32-bit flag if the immediate is zero
1548 alloc_reg64(current,i,rt1[i]);
1549 alloc_reg64(current,i,rs1[i]);
1550 }
1551 clear_const(current,rs1[i]);
1552 clear_const(current,rt1[i]);
1553 }
1554 else if(opcode[i]==0x0a||opcode[i]==0x0b) { // SLTI/SLTIU
1555 if((~current->is32>>rs1[i])&1) alloc_reg64(current,i,rs1[i]);
1556 current->is32|=1LL<<rt1[i];
1557 clear_const(current,rs1[i]);
1558 clear_const(current,rt1[i]);
1559 }
1560 else if(opcode[i]>=0x0c&&opcode[i]<=0x0e) { // ANDI/ORI/XORI
1561 if(((~current->is32>>rs1[i])&1)&&opcode[i]>0x0c) {
1562 if(rs1[i]!=rt1[i]) {
1563 if(needed_again(rs1[i],i)) alloc_reg64(current,i,rs1[i]);
1564 alloc_reg64(current,i,rt1[i]);
1565 current->is32&=~(1LL<<rt1[i]);
1566 }
1567 }
1568 else current->is32|=1LL<<rt1[i]; // ANDI clears upper bits
1569 if(is_const(current,rs1[i])) {
1570 int v=get_const(current,rs1[i]);
1571 if(opcode[i]==0x0c) set_const(current,rt1[i],v&imm[i]);
1572 if(opcode[i]==0x0d) set_const(current,rt1[i],v|imm[i]);
1573 if(opcode[i]==0x0e) set_const(current,rt1[i],v^imm[i]);
1574 }
1575 else clear_const(current,rt1[i]);
1576 }
1577 else if(opcode[i]==0x08||opcode[i]==0x09) { // ADDI/ADDIU
1578 if(is_const(current,rs1[i])) {
1579 int v=get_const(current,rs1[i]);
1580 set_const(current,rt1[i],v+imm[i]);
1581 }
1582 else clear_const(current,rt1[i]);
1583 current->is32|=1LL<<rt1[i];
1584 }
1585 else {
1586 set_const(current,rt1[i],((long long)((short)imm[i]))<<16); // LUI
1587 current->is32|=1LL<<rt1[i];
1588 }
1589 dirty_reg(current,rt1[i]);
1590}
1591
1592void load_alloc(struct regstat *current,int i)
1593{
1594 clear_const(current,rt1[i]);
1595 //if(rs1[i]!=rt1[i]&&needed_again(rs1[i],i)) clear_const(current,rs1[i]); // Does this help or hurt?
1596 if(!rs1[i]) current->u&=~1LL; // Allow allocating r0 if it's the source register
1597 if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
373d1d07 1598 if(rt1[i]&&!((current->u>>rt1[i])&1)) {
57871462 1599 alloc_reg(current,i,rt1[i]);
373d1d07 1600 assert(get_reg(current->regmap,rt1[i])>=0);
57871462 1601 if(opcode[i]==0x27||opcode[i]==0x37) // LWU/LD
1602 {
1603 current->is32&=~(1LL<<rt1[i]);
1604 alloc_reg64(current,i,rt1[i]);
1605 }
1606 else if(opcode[i]==0x1A||opcode[i]==0x1B) // LDL/LDR
1607 {
1608 current->is32&=~(1LL<<rt1[i]);
1609 alloc_reg64(current,i,rt1[i]);
1610 alloc_all(current,i);
1611 alloc_reg64(current,i,FTEMP);
e1190b87 1612 minimum_free_regs[i]=HOST_REGS;
57871462 1613 }
1614 else current->is32|=1LL<<rt1[i];
1615 dirty_reg(current,rt1[i]);
1616 // If using TLB, need a register for pointer to the mapping table
1617 if(using_tlb) alloc_reg(current,i,TLREG);
1618 // LWL/LWR need a temporary register for the old value
1619 if(opcode[i]==0x22||opcode[i]==0x26)
1620 {
1621 alloc_reg(current,i,FTEMP);
1622 alloc_reg_temp(current,i,-1);
e1190b87 1623 minimum_free_regs[i]=1;
57871462 1624 }
1625 }
1626 else
1627 {
373d1d07 1628 // Load to r0 or unneeded register (dummy load)
57871462 1629 // but we still need a register to calculate the address
535d208a 1630 if(opcode[i]==0x22||opcode[i]==0x26)
1631 {
1632 alloc_reg(current,i,FTEMP); // LWL/LWR need another temporary
1633 }
373d1d07 1634 // If using TLB, need a register for pointer to the mapping table
1635 if(using_tlb) alloc_reg(current,i,TLREG);
57871462 1636 alloc_reg_temp(current,i,-1);
e1190b87 1637 minimum_free_regs[i]=1;
535d208a 1638 if(opcode[i]==0x1A||opcode[i]==0x1B) // LDL/LDR
1639 {
1640 alloc_all(current,i);
1641 alloc_reg64(current,i,FTEMP);
e1190b87 1642 minimum_free_regs[i]=HOST_REGS;
535d208a 1643 }
57871462 1644 }
1645}
1646
1647void store_alloc(struct regstat *current,int i)
1648{
1649 clear_const(current,rs2[i]);
1650 if(!(rs2[i])) current->u&=~1LL; // Allow allocating r0 if necessary
1651 if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1652 alloc_reg(current,i,rs2[i]);
1653 if(opcode[i]==0x2c||opcode[i]==0x2d||opcode[i]==0x3f) { // 64-bit SDL/SDR/SD
1654 alloc_reg64(current,i,rs2[i]);
1655 if(rs2[i]) alloc_reg(current,i,FTEMP);
1656 }
1657 // If using TLB, need a register for pointer to the mapping table
1658 if(using_tlb) alloc_reg(current,i,TLREG);
1659 #if defined(HOST_IMM8)
1660 // On CPUs without 32-bit immediates we need a pointer to invalid_code
1661 else alloc_reg(current,i,INVCP);
1662 #endif
b7918751 1663 if(opcode[i]==0x2a||opcode[i]==0x2e||opcode[i]==0x2c||opcode[i]==0x2d) { // SWL/SWL/SDL/SDR
57871462 1664 alloc_reg(current,i,FTEMP);
1665 }
1666 // We need a temporary register for address generation
1667 alloc_reg_temp(current,i,-1);
e1190b87 1668 minimum_free_regs[i]=1;
57871462 1669}
1670
1671void c1ls_alloc(struct regstat *current,int i)
1672{
1673 //clear_const(current,rs1[i]); // FIXME
1674 clear_const(current,rt1[i]);
1675 if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1676 alloc_reg(current,i,CSREG); // Status
1677 alloc_reg(current,i,FTEMP);
1678 if(opcode[i]==0x35||opcode[i]==0x3d) { // 64-bit LDC1/SDC1
1679 alloc_reg64(current,i,FTEMP);
1680 }
1681 // If using TLB, need a register for pointer to the mapping table
1682 if(using_tlb) alloc_reg(current,i,TLREG);
1683 #if defined(HOST_IMM8)
1684 // On CPUs without 32-bit immediates we need a pointer to invalid_code
1685 else if((opcode[i]&0x3b)==0x39) // SWC1/SDC1
1686 alloc_reg(current,i,INVCP);
1687 #endif
1688 // We need a temporary register for address generation
1689 alloc_reg_temp(current,i,-1);
1690}
1691
b9b61529 1692void c2ls_alloc(struct regstat *current,int i)
1693{
1694 clear_const(current,rt1[i]);
1695 if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1696 alloc_reg(current,i,FTEMP);
1697 // If using TLB, need a register for pointer to the mapping table
1698 if(using_tlb) alloc_reg(current,i,TLREG);
1699 #if defined(HOST_IMM8)
1700 // On CPUs without 32-bit immediates we need a pointer to invalid_code
1701 else if((opcode[i]&0x3b)==0x3a) // SWC2/SDC2
1702 alloc_reg(current,i,INVCP);
1703 #endif
1704 // We need a temporary register for address generation
1705 alloc_reg_temp(current,i,-1);
e1190b87 1706 minimum_free_regs[i]=1;
b9b61529 1707}
1708
57871462 1709#ifndef multdiv_alloc
1710void multdiv_alloc(struct regstat *current,int i)
1711{
1712 // case 0x18: MULT
1713 // case 0x19: MULTU
1714 // case 0x1A: DIV
1715 // case 0x1B: DIVU
1716 // case 0x1C: DMULT
1717 // case 0x1D: DMULTU
1718 // case 0x1E: DDIV
1719 // case 0x1F: DDIVU
1720 clear_const(current,rs1[i]);
1721 clear_const(current,rs2[i]);
1722 if(rs1[i]&&rs2[i])
1723 {
1724 if((opcode2[i]&4)==0) // 32-bit
1725 {
1726 current->u&=~(1LL<<HIREG);
1727 current->u&=~(1LL<<LOREG);
1728 alloc_reg(current,i,HIREG);
1729 alloc_reg(current,i,LOREG);
1730 alloc_reg(current,i,rs1[i]);
1731 alloc_reg(current,i,rs2[i]);
1732 current->is32|=1LL<<HIREG;
1733 current->is32|=1LL<<LOREG;
1734 dirty_reg(current,HIREG);
1735 dirty_reg(current,LOREG);
1736 }
1737 else // 64-bit
1738 {
1739 current->u&=~(1LL<<HIREG);
1740 current->u&=~(1LL<<LOREG);
1741 current->uu&=~(1LL<<HIREG);
1742 current->uu&=~(1LL<<LOREG);
1743 alloc_reg64(current,i,HIREG);
1744 //if(HOST_REGS>10) alloc_reg64(current,i,LOREG);
1745 alloc_reg64(current,i,rs1[i]);
1746 alloc_reg64(current,i,rs2[i]);
1747 alloc_all(current,i);
1748 current->is32&=~(1LL<<HIREG);
1749 current->is32&=~(1LL<<LOREG);
1750 dirty_reg(current,HIREG);
1751 dirty_reg(current,LOREG);
e1190b87 1752 minimum_free_regs[i]=HOST_REGS;
57871462 1753 }
1754 }
1755 else
1756 {
1757 // Multiply by zero is zero.
1758 // MIPS does not have a divide by zero exception.
1759 // The result is undefined, we return zero.
1760 alloc_reg(current,i,HIREG);
1761 alloc_reg(current,i,LOREG);
1762 current->is32|=1LL<<HIREG;
1763 current->is32|=1LL<<LOREG;
1764 dirty_reg(current,HIREG);
1765 dirty_reg(current,LOREG);
1766 }
1767}
1768#endif
1769
1770void cop0_alloc(struct regstat *current,int i)
1771{
1772 if(opcode2[i]==0) // MFC0
1773 {
1774 if(rt1[i]) {
1775 clear_const(current,rt1[i]);
1776 alloc_all(current,i);
1777 alloc_reg(current,i,rt1[i]);
1778 current->is32|=1LL<<rt1[i];
1779 dirty_reg(current,rt1[i]);
1780 }
1781 }
1782 else if(opcode2[i]==4) // MTC0
1783 {
1784 if(rs1[i]){
1785 clear_const(current,rs1[i]);
1786 alloc_reg(current,i,rs1[i]);
1787 alloc_all(current,i);
1788 }
1789 else {
1790 alloc_all(current,i); // FIXME: Keep r0
1791 current->u&=~1LL;
1792 alloc_reg(current,i,0);
1793 }
1794 }
1795 else
1796 {
1797 // TLBR/TLBWI/TLBWR/TLBP/ERET
1798 assert(opcode2[i]==0x10);
1799 alloc_all(current,i);
1800 }
e1190b87 1801 minimum_free_regs[i]=HOST_REGS;
57871462 1802}
1803
1804void cop1_alloc(struct regstat *current,int i)
1805{
1806 alloc_reg(current,i,CSREG); // Load status
1807 if(opcode2[i]<3) // MFC1/DMFC1/CFC1
1808 {
7de557a6 1809 if(rt1[i]){
1810 clear_const(current,rt1[i]);
1811 if(opcode2[i]==1) {
1812 alloc_reg64(current,i,rt1[i]); // DMFC1
1813 current->is32&=~(1LL<<rt1[i]);
1814 }else{
1815 alloc_reg(current,i,rt1[i]); // MFC1/CFC1
1816 current->is32|=1LL<<rt1[i];
1817 }
1818 dirty_reg(current,rt1[i]);
57871462 1819 }
57871462 1820 alloc_reg_temp(current,i,-1);
1821 }
1822 else if(opcode2[i]>3) // MTC1/DMTC1/CTC1
1823 {
1824 if(rs1[i]){
1825 clear_const(current,rs1[i]);
1826 if(opcode2[i]==5)
1827 alloc_reg64(current,i,rs1[i]); // DMTC1
1828 else
1829 alloc_reg(current,i,rs1[i]); // MTC1/CTC1
1830 alloc_reg_temp(current,i,-1);
1831 }
1832 else {
1833 current->u&=~1LL;
1834 alloc_reg(current,i,0);
1835 alloc_reg_temp(current,i,-1);
1836 }
1837 }
e1190b87 1838 minimum_free_regs[i]=1;
57871462 1839}
1840void fconv_alloc(struct regstat *current,int i)
1841{
1842 alloc_reg(current,i,CSREG); // Load status
1843 alloc_reg_temp(current,i,-1);
e1190b87 1844 minimum_free_regs[i]=1;
57871462 1845}
1846void float_alloc(struct regstat *current,int i)
1847{
1848 alloc_reg(current,i,CSREG); // Load status
1849 alloc_reg_temp(current,i,-1);
e1190b87 1850 minimum_free_regs[i]=1;
57871462 1851}
b9b61529 1852void c2op_alloc(struct regstat *current,int i)
1853{
1854 alloc_reg_temp(current,i,-1);
1855}
57871462 1856void fcomp_alloc(struct regstat *current,int i)
1857{
1858 alloc_reg(current,i,CSREG); // Load status
1859 alloc_reg(current,i,FSREG); // Load flags
1860 dirty_reg(current,FSREG); // Flag will be modified
1861 alloc_reg_temp(current,i,-1);
e1190b87 1862 minimum_free_regs[i]=1;
57871462 1863}
1864
1865void syscall_alloc(struct regstat *current,int i)
1866{
1867 alloc_cc(current,i);
1868 dirty_reg(current,CCREG);
1869 alloc_all(current,i);
e1190b87 1870 minimum_free_regs[i]=HOST_REGS;
57871462 1871 current->isconst=0;
1872}
1873
1874void delayslot_alloc(struct regstat *current,int i)
1875{
1876 switch(itype[i]) {
1877 case UJUMP:
1878 case CJUMP:
1879 case SJUMP:
1880 case RJUMP:
1881 case FJUMP:
1882 case SYSCALL:
7139f3c8 1883 case HLECALL:
57871462 1884 case SPAN:
1885 assem_debug("jump in the delay slot. this shouldn't happen.\n");//exit(1);
1886 printf("Disabled speculative precompilation\n");
1887 stop_after_jal=1;
1888 break;
1889 case IMM16:
1890 imm16_alloc(current,i);
1891 break;
1892 case LOAD:
1893 case LOADLR:
1894 load_alloc(current,i);
1895 break;
1896 case STORE:
1897 case STORELR:
1898 store_alloc(current,i);
1899 break;
1900 case ALU:
1901 alu_alloc(current,i);
1902 break;
1903 case SHIFT:
1904 shift_alloc(current,i);
1905 break;
1906 case MULTDIV:
1907 multdiv_alloc(current,i);
1908 break;
1909 case SHIFTIMM:
1910 shiftimm_alloc(current,i);
1911 break;
1912 case MOV:
1913 mov_alloc(current,i);
1914 break;
1915 case COP0:
1916 cop0_alloc(current,i);
1917 break;
1918 case COP1:
b9b61529 1919 case COP2:
57871462 1920 cop1_alloc(current,i);
1921 break;
1922 case C1LS:
1923 c1ls_alloc(current,i);
1924 break;
b9b61529 1925 case C2LS:
1926 c2ls_alloc(current,i);
1927 break;
57871462 1928 case FCONV:
1929 fconv_alloc(current,i);
1930 break;
1931 case FLOAT:
1932 float_alloc(current,i);
1933 break;
1934 case FCOMP:
1935 fcomp_alloc(current,i);
1936 break;
b9b61529 1937 case C2OP:
1938 c2op_alloc(current,i);
1939 break;
57871462 1940 }
1941}
1942
1943// Special case where a branch and delay slot span two pages in virtual memory
1944static void pagespan_alloc(struct regstat *current,int i)
1945{
1946 current->isconst=0;
1947 current->wasconst=0;
1948 regs[i].wasconst=0;
e1190b87 1949 minimum_free_regs[i]=HOST_REGS;
57871462 1950 alloc_all(current,i);
1951 alloc_cc(current,i);
1952 dirty_reg(current,CCREG);
1953 if(opcode[i]==3) // JAL
1954 {
1955 alloc_reg(current,i,31);
1956 dirty_reg(current,31);
1957 }
1958 if(opcode[i]==0&&(opcode2[i]&0x3E)==8) // JR/JALR
1959 {
1960 alloc_reg(current,i,rs1[i]);
5067f341 1961 if (rt1[i]!=0) {
1962 alloc_reg(current,i,rt1[i]);
1963 dirty_reg(current,rt1[i]);
57871462 1964 }
1965 }
1966 if((opcode[i]&0x2E)==4) // BEQ/BNE/BEQL/BNEL
1967 {
1968 if(rs1[i]) alloc_reg(current,i,rs1[i]);
1969 if(rs2[i]) alloc_reg(current,i,rs2[i]);
1970 if(!((current->is32>>rs1[i])&(current->is32>>rs2[i])&1))
1971 {
1972 if(rs1[i]) alloc_reg64(current,i,rs1[i]);
1973 if(rs2[i]) alloc_reg64(current,i,rs2[i]);
1974 }
1975 }
1976 else
1977 if((opcode[i]&0x2E)==6) // BLEZ/BGTZ/BLEZL/BGTZL
1978 {
1979 if(rs1[i]) alloc_reg(current,i,rs1[i]);
1980 if(!((current->is32>>rs1[i])&1))
1981 {
1982 if(rs1[i]) alloc_reg64(current,i,rs1[i]);
1983 }
1984 }
1985 else
1986 if(opcode[i]==0x11) // BC1
1987 {
1988 alloc_reg(current,i,FSREG);
1989 alloc_reg(current,i,CSREG);
1990 }
1991 //else ...
1992}
1993
1994add_stub(int type,int addr,int retaddr,int a,int b,int c,int d,int e)
1995{
1996 stubs[stubcount][0]=type;
1997 stubs[stubcount][1]=addr;
1998 stubs[stubcount][2]=retaddr;
1999 stubs[stubcount][3]=a;
2000 stubs[stubcount][4]=b;
2001 stubs[stubcount][5]=c;
2002 stubs[stubcount][6]=d;
2003 stubs[stubcount][7]=e;
2004 stubcount++;
2005}
2006
2007// Write out a single register
2008void wb_register(signed char r,signed char regmap[],uint64_t dirty,uint64_t is32)
2009{
2010 int hr;
2011 for(hr=0;hr<HOST_REGS;hr++) {
2012 if(hr!=EXCLUDE_REG) {
2013 if((regmap[hr]&63)==r) {
2014 if((dirty>>hr)&1) {
2015 if(regmap[hr]<64) {
2016 emit_storereg(r,hr);
24385cae 2017#ifndef FORCE32
57871462 2018 if((is32>>regmap[hr])&1) {
2019 emit_sarimm(hr,31,hr);
2020 emit_storereg(r|64,hr);
2021 }
24385cae 2022#endif
57871462 2023 }else{
2024 emit_storereg(r|64,hr);
2025 }
2026 }
2027 }
2028 }
2029 }
2030}
2031
2032int mchecksum()
2033{
2034 //if(!tracedebug) return 0;
2035 int i;
2036 int sum=0;
2037 for(i=0;i<2097152;i++) {
2038 unsigned int temp=sum;
2039 sum<<=1;
2040 sum|=(~temp)>>31;
2041 sum^=((u_int *)rdram)[i];
2042 }
2043 return sum;
2044}
2045int rchecksum()
2046{
2047 int i;
2048 int sum=0;
2049 for(i=0;i<64;i++)
2050 sum^=((u_int *)reg)[i];
2051 return sum;
2052}
57871462 2053void rlist()
2054{
2055 int i;
2056 printf("TRACE: ");
2057 for(i=0;i<32;i++)
2058 printf("r%d:%8x%8x ",i,((int *)(reg+i))[1],((int *)(reg+i))[0]);
2059 printf("\n");
3d624f89 2060#ifndef DISABLE_COP1
57871462 2061 printf("TRACE: ");
2062 for(i=0;i<32;i++)
2063 printf("f%d:%8x%8x ",i,((int*)reg_cop1_simple[i])[1],*((int*)reg_cop1_simple[i]));
2064 printf("\n");
3d624f89 2065#endif
57871462 2066}
2067
2068void enabletrace()
2069{
2070 tracedebug=1;
2071}
2072
2073void memdebug(int i)
2074{
2075 //printf("TRACE: count=%d next=%d (checksum %x) lo=%8x%8x\n",Count,next_interupt,mchecksum(),(int)(reg[LOREG]>>32),(int)reg[LOREG]);
2076 //printf("TRACE: count=%d next=%d (rchecksum %x)\n",Count,next_interupt,rchecksum());
2077 //rlist();
2078 //if(tracedebug) {
2079 //if(Count>=-2084597794) {
2080 if((signed int)Count>=-2084597794&&(signed int)Count<0) {
2081 //if(0) {
2082 printf("TRACE: count=%d next=%d (checksum %x)\n",Count,next_interupt,mchecksum());
2083 //printf("TRACE: count=%d next=%d (checksum %x) Status=%x\n",Count,next_interupt,mchecksum(),Status);
2084 //printf("TRACE: count=%d next=%d (checksum %x) hi=%8x%8x\n",Count,next_interupt,mchecksum(),(int)(reg[HIREG]>>32),(int)reg[HIREG]);
2085 rlist();
2086 #ifdef __i386__
2087 printf("TRACE: %x\n",(&i)[-1]);
2088 #endif
2089 #ifdef __arm__
2090 int j;
2091 printf("TRACE: %x \n",(&j)[10]);
2092 printf("TRACE: %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x\n",(&j)[1],(&j)[2],(&j)[3],(&j)[4],(&j)[5],(&j)[6],(&j)[7],(&j)[8],(&j)[9],(&j)[10],(&j)[11],(&j)[12],(&j)[13],(&j)[14],(&j)[15],(&j)[16],(&j)[17],(&j)[18],(&j)[19],(&j)[20]);
2093 #endif
2094 //fflush(stdout);
2095 }
2096 //printf("TRACE: %x\n",(&i)[-1]);
2097}
2098
2099void tlb_debug(u_int cause, u_int addr, u_int iaddr)
2100{
2101 printf("TLB Exception: instruction=%x addr=%x cause=%x\n",iaddr, addr, cause);
2102}
2103
2104void alu_assemble(int i,struct regstat *i_regs)
2105{
2106 if(opcode2[i]>=0x20&&opcode2[i]<=0x23) { // ADD/ADDU/SUB/SUBU
2107 if(rt1[i]) {
2108 signed char s1,s2,t;
2109 t=get_reg(i_regs->regmap,rt1[i]);
2110 if(t>=0) {
2111 s1=get_reg(i_regs->regmap,rs1[i]);
2112 s2=get_reg(i_regs->regmap,rs2[i]);
2113 if(rs1[i]&&rs2[i]) {
2114 assert(s1>=0);
2115 assert(s2>=0);
2116 if(opcode2[i]&2) emit_sub(s1,s2,t);
2117 else emit_add(s1,s2,t);
2118 }
2119 else if(rs1[i]) {
2120 if(s1>=0) emit_mov(s1,t);
2121 else emit_loadreg(rs1[i],t);
2122 }
2123 else if(rs2[i]) {
2124 if(s2>=0) {
2125 if(opcode2[i]&2) emit_neg(s2,t);
2126 else emit_mov(s2,t);
2127 }
2128 else {
2129 emit_loadreg(rs2[i],t);
2130 if(opcode2[i]&2) emit_neg(t,t);
2131 }
2132 }
2133 else emit_zeroreg(t);
2134 }
2135 }
2136 }
2137 if(opcode2[i]>=0x2c&&opcode2[i]<=0x2f) { // DADD/DADDU/DSUB/DSUBU
2138 if(rt1[i]) {
2139 signed char s1l,s2l,s1h,s2h,tl,th;
2140 tl=get_reg(i_regs->regmap,rt1[i]);
2141 th=get_reg(i_regs->regmap,rt1[i]|64);
2142 if(tl>=0) {
2143 s1l=get_reg(i_regs->regmap,rs1[i]);
2144 s2l=get_reg(i_regs->regmap,rs2[i]);
2145 s1h=get_reg(i_regs->regmap,rs1[i]|64);
2146 s2h=get_reg(i_regs->regmap,rs2[i]|64);
2147 if(rs1[i]&&rs2[i]) {
2148 assert(s1l>=0);
2149 assert(s2l>=0);
2150 if(opcode2[i]&2) emit_subs(s1l,s2l,tl);
2151 else emit_adds(s1l,s2l,tl);
2152 if(th>=0) {
2153 #ifdef INVERTED_CARRY
2154 if(opcode2[i]&2) {if(s1h!=th) emit_mov(s1h,th);emit_sbb(th,s2h);}
2155 #else
2156 if(opcode2[i]&2) emit_sbc(s1h,s2h,th);
2157 #endif
2158 else emit_add(s1h,s2h,th);
2159 }
2160 }
2161 else if(rs1[i]) {
2162 if(s1l>=0) emit_mov(s1l,tl);
2163 else emit_loadreg(rs1[i],tl);
2164 if(th>=0) {
2165 if(s1h>=0) emit_mov(s1h,th);
2166 else emit_loadreg(rs1[i]|64,th);
2167 }
2168 }
2169 else if(rs2[i]) {
2170 if(s2l>=0) {
2171 if(opcode2[i]&2) emit_negs(s2l,tl);
2172 else emit_mov(s2l,tl);
2173 }
2174 else {
2175 emit_loadreg(rs2[i],tl);
2176 if(opcode2[i]&2) emit_negs(tl,tl);
2177 }
2178 if(th>=0) {
2179 #ifdef INVERTED_CARRY
2180 if(s2h>=0) emit_mov(s2h,th);
2181 else emit_loadreg(rs2[i]|64,th);
2182 if(opcode2[i]&2) {
2183 emit_adcimm(-1,th); // x86 has inverted carry flag
2184 emit_not(th,th);
2185 }
2186 #else
2187 if(opcode2[i]&2) {
2188 if(s2h>=0) emit_rscimm(s2h,0,th);
2189 else {
2190 emit_loadreg(rs2[i]|64,th);
2191 emit_rscimm(th,0,th);
2192 }
2193 }else{
2194 if(s2h>=0) emit_mov(s2h,th);
2195 else emit_loadreg(rs2[i]|64,th);
2196 }
2197 #endif
2198 }
2199 }
2200 else {
2201 emit_zeroreg(tl);
2202 if(th>=0) emit_zeroreg(th);
2203 }
2204 }
2205 }
2206 }
2207 if(opcode2[i]==0x2a||opcode2[i]==0x2b) { // SLT/SLTU
2208 if(rt1[i]) {
2209 signed char s1l,s1h,s2l,s2h,t;
2210 if(!((i_regs->was32>>rs1[i])&(i_regs->was32>>rs2[i])&1))
2211 {
2212 t=get_reg(i_regs->regmap,rt1[i]);
2213 //assert(t>=0);
2214 if(t>=0) {
2215 s1l=get_reg(i_regs->regmap,rs1[i]);
2216 s1h=get_reg(i_regs->regmap,rs1[i]|64);
2217 s2l=get_reg(i_regs->regmap,rs2[i]);
2218 s2h=get_reg(i_regs->regmap,rs2[i]|64);
2219 if(rs2[i]==0) // rx<r0
2220 {
2221 assert(s1h>=0);
2222 if(opcode2[i]==0x2a) // SLT
2223 emit_shrimm(s1h,31,t);
2224 else // SLTU (unsigned can not be less than zero)
2225 emit_zeroreg(t);
2226 }
2227 else if(rs1[i]==0) // r0<rx
2228 {
2229 assert(s2h>=0);
2230 if(opcode2[i]==0x2a) // SLT
2231 emit_set_gz64_32(s2h,s2l,t);
2232 else // SLTU (set if not zero)
2233 emit_set_nz64_32(s2h,s2l,t);
2234 }
2235 else {
2236 assert(s1l>=0);assert(s1h>=0);
2237 assert(s2l>=0);assert(s2h>=0);
2238 if(opcode2[i]==0x2a) // SLT
2239 emit_set_if_less64_32(s1h,s1l,s2h,s2l,t);
2240 else // SLTU
2241 emit_set_if_carry64_32(s1h,s1l,s2h,s2l,t);
2242 }
2243 }
2244 } else {
2245 t=get_reg(i_regs->regmap,rt1[i]);
2246 //assert(t>=0);
2247 if(t>=0) {
2248 s1l=get_reg(i_regs->regmap,rs1[i]);
2249 s2l=get_reg(i_regs->regmap,rs2[i]);
2250 if(rs2[i]==0) // rx<r0
2251 {
2252 assert(s1l>=0);
2253 if(opcode2[i]==0x2a) // SLT
2254 emit_shrimm(s1l,31,t);
2255 else // SLTU (unsigned can not be less than zero)
2256 emit_zeroreg(t);
2257 }
2258 else if(rs1[i]==0) // r0<rx
2259 {
2260 assert(s2l>=0);
2261 if(opcode2[i]==0x2a) // SLT
2262 emit_set_gz32(s2l,t);
2263 else // SLTU (set if not zero)
2264 emit_set_nz32(s2l,t);
2265 }
2266 else{
2267 assert(s1l>=0);assert(s2l>=0);
2268 if(opcode2[i]==0x2a) // SLT
2269 emit_set_if_less32(s1l,s2l,t);
2270 else // SLTU
2271 emit_set_if_carry32(s1l,s2l,t);
2272 }
2273 }
2274 }
2275 }
2276 }
2277 if(opcode2[i]>=0x24&&opcode2[i]<=0x27) { // AND/OR/XOR/NOR
2278 if(rt1[i]) {
2279 signed char s1l,s1h,s2l,s2h,th,tl;
2280 tl=get_reg(i_regs->regmap,rt1[i]);
2281 th=get_reg(i_regs->regmap,rt1[i]|64);
2282 if(!((i_regs->was32>>rs1[i])&(i_regs->was32>>rs2[i])&1)&&th>=0)
2283 {
2284 assert(tl>=0);
2285 if(tl>=0) {
2286 s1l=get_reg(i_regs->regmap,rs1[i]);
2287 s1h=get_reg(i_regs->regmap,rs1[i]|64);
2288 s2l=get_reg(i_regs->regmap,rs2[i]);
2289 s2h=get_reg(i_regs->regmap,rs2[i]|64);
2290 if(rs1[i]&&rs2[i]) {
2291 assert(s1l>=0);assert(s1h>=0);
2292 assert(s2l>=0);assert(s2h>=0);
2293 if(opcode2[i]==0x24) { // AND
2294 emit_and(s1l,s2l,tl);
2295 emit_and(s1h,s2h,th);
2296 } else
2297 if(opcode2[i]==0x25) { // OR
2298 emit_or(s1l,s2l,tl);
2299 emit_or(s1h,s2h,th);
2300 } else
2301 if(opcode2[i]==0x26) { // XOR
2302 emit_xor(s1l,s2l,tl);
2303 emit_xor(s1h,s2h,th);
2304 } else
2305 if(opcode2[i]==0x27) { // NOR
2306 emit_or(s1l,s2l,tl);
2307 emit_or(s1h,s2h,th);
2308 emit_not(tl,tl);
2309 emit_not(th,th);
2310 }
2311 }
2312 else
2313 {
2314 if(opcode2[i]==0x24) { // AND
2315 emit_zeroreg(tl);
2316 emit_zeroreg(th);
2317 } else
2318 if(opcode2[i]==0x25||opcode2[i]==0x26) { // OR/XOR
2319 if(rs1[i]){
2320 if(s1l>=0) emit_mov(s1l,tl);
2321 else emit_loadreg(rs1[i],tl);
2322 if(s1h>=0) emit_mov(s1h,th);
2323 else emit_loadreg(rs1[i]|64,th);
2324 }
2325 else
2326 if(rs2[i]){
2327 if(s2l>=0) emit_mov(s2l,tl);
2328 else emit_loadreg(rs2[i],tl);
2329 if(s2h>=0) emit_mov(s2h,th);
2330 else emit_loadreg(rs2[i]|64,th);
2331 }
2332 else{
2333 emit_zeroreg(tl);
2334 emit_zeroreg(th);
2335 }
2336 } else
2337 if(opcode2[i]==0x27) { // NOR
2338 if(rs1[i]){
2339 if(s1l>=0) emit_not(s1l,tl);
2340 else{
2341 emit_loadreg(rs1[i],tl);
2342 emit_not(tl,tl);
2343 }
2344 if(s1h>=0) emit_not(s1h,th);
2345 else{
2346 emit_loadreg(rs1[i]|64,th);
2347 emit_not(th,th);
2348 }
2349 }
2350 else
2351 if(rs2[i]){
2352 if(s2l>=0) emit_not(s2l,tl);
2353 else{
2354 emit_loadreg(rs2[i],tl);
2355 emit_not(tl,tl);
2356 }
2357 if(s2h>=0) emit_not(s2h,th);
2358 else{
2359 emit_loadreg(rs2[i]|64,th);
2360 emit_not(th,th);
2361 }
2362 }
2363 else {
2364 emit_movimm(-1,tl);
2365 emit_movimm(-1,th);
2366 }
2367 }
2368 }
2369 }
2370 }
2371 else
2372 {
2373 // 32 bit
2374 if(tl>=0) {
2375 s1l=get_reg(i_regs->regmap,rs1[i]);
2376 s2l=get_reg(i_regs->regmap,rs2[i]);
2377 if(rs1[i]&&rs2[i]) {
2378 assert(s1l>=0);
2379 assert(s2l>=0);
2380 if(opcode2[i]==0x24) { // AND
2381 emit_and(s1l,s2l,tl);
2382 } else
2383 if(opcode2[i]==0x25) { // OR
2384 emit_or(s1l,s2l,tl);
2385 } else
2386 if(opcode2[i]==0x26) { // XOR
2387 emit_xor(s1l,s2l,tl);
2388 } else
2389 if(opcode2[i]==0x27) { // NOR
2390 emit_or(s1l,s2l,tl);
2391 emit_not(tl,tl);
2392 }
2393 }
2394 else
2395 {
2396 if(opcode2[i]==0x24) { // AND
2397 emit_zeroreg(tl);
2398 } else
2399 if(opcode2[i]==0x25||opcode2[i]==0x26) { // OR/XOR
2400 if(rs1[i]){
2401 if(s1l>=0) emit_mov(s1l,tl);
2402 else emit_loadreg(rs1[i],tl); // CHECK: regmap_entry?
2403 }
2404 else
2405 if(rs2[i]){
2406 if(s2l>=0) emit_mov(s2l,tl);
2407 else emit_loadreg(rs2[i],tl); // CHECK: regmap_entry?
2408 }
2409 else emit_zeroreg(tl);
2410 } else
2411 if(opcode2[i]==0x27) { // NOR
2412 if(rs1[i]){
2413 if(s1l>=0) emit_not(s1l,tl);
2414 else {
2415 emit_loadreg(rs1[i],tl);
2416 emit_not(tl,tl);
2417 }
2418 }
2419 else
2420 if(rs2[i]){
2421 if(s2l>=0) emit_not(s2l,tl);
2422 else {
2423 emit_loadreg(rs2[i],tl);
2424 emit_not(tl,tl);
2425 }
2426 }
2427 else emit_movimm(-1,tl);
2428 }
2429 }
2430 }
2431 }
2432 }
2433 }
2434}
2435
2436void imm16_assemble(int i,struct regstat *i_regs)
2437{
2438 if (opcode[i]==0x0f) { // LUI
2439 if(rt1[i]) {
2440 signed char t;
2441 t=get_reg(i_regs->regmap,rt1[i]);
2442 //assert(t>=0);
2443 if(t>=0) {
2444 if(!((i_regs->isconst>>t)&1))
2445 emit_movimm(imm[i]<<16,t);
2446 }
2447 }
2448 }
2449 if(opcode[i]==0x08||opcode[i]==0x09) { // ADDI/ADDIU
2450 if(rt1[i]) {
2451 signed char s,t;
2452 t=get_reg(i_regs->regmap,rt1[i]);
2453 s=get_reg(i_regs->regmap,rs1[i]);
2454 if(rs1[i]) {
2455 //assert(t>=0);
2456 //assert(s>=0);
2457 if(t>=0) {
2458 if(!((i_regs->isconst>>t)&1)) {
2459 if(s<0) {
2460 if(i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2461 emit_addimm(t,imm[i],t);
2462 }else{
2463 if(!((i_regs->wasconst>>s)&1))
2464 emit_addimm(s,imm[i],t);
2465 else
2466 emit_movimm(constmap[i][s]+imm[i],t);
2467 }
2468 }
2469 }
2470 } else {
2471 if(t>=0) {
2472 if(!((i_regs->isconst>>t)&1))
2473 emit_movimm(imm[i],t);
2474 }
2475 }
2476 }
2477 }
2478 if(opcode[i]==0x18||opcode[i]==0x19) { // DADDI/DADDIU
2479 if(rt1[i]) {
2480 signed char sh,sl,th,tl;
2481 th=get_reg(i_regs->regmap,rt1[i]|64);
2482 tl=get_reg(i_regs->regmap,rt1[i]);
2483 sh=get_reg(i_regs->regmap,rs1[i]|64);
2484 sl=get_reg(i_regs->regmap,rs1[i]);
2485 if(tl>=0) {
2486 if(rs1[i]) {
2487 assert(sh>=0);
2488 assert(sl>=0);
2489 if(th>=0) {
2490 emit_addimm64_32(sh,sl,imm[i],th,tl);
2491 }
2492 else {
2493 emit_addimm(sl,imm[i],tl);
2494 }
2495 } else {
2496 emit_movimm(imm[i],tl);
2497 if(th>=0) emit_movimm(((signed int)imm[i])>>31,th);
2498 }
2499 }
2500 }
2501 }
2502 else if(opcode[i]==0x0a||opcode[i]==0x0b) { // SLTI/SLTIU
2503 if(rt1[i]) {
2504 //assert(rs1[i]!=0); // r0 might be valid, but it's probably a bug
2505 signed char sh,sl,t;
2506 t=get_reg(i_regs->regmap,rt1[i]);
2507 sh=get_reg(i_regs->regmap,rs1[i]|64);
2508 sl=get_reg(i_regs->regmap,rs1[i]);
2509 //assert(t>=0);
2510 if(t>=0) {
2511 if(rs1[i]>0) {
2512 if(sh<0) assert((i_regs->was32>>rs1[i])&1);
2513 if(sh<0||((i_regs->was32>>rs1[i])&1)) {
2514 if(opcode[i]==0x0a) { // SLTI
2515 if(sl<0) {
2516 if(i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2517 emit_slti32(t,imm[i],t);
2518 }else{
2519 emit_slti32(sl,imm[i],t);
2520 }
2521 }
2522 else { // SLTIU
2523 if(sl<0) {
2524 if(i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2525 emit_sltiu32(t,imm[i],t);
2526 }else{
2527 emit_sltiu32(sl,imm[i],t);
2528 }
2529 }
2530 }else{ // 64-bit
2531 assert(sl>=0);
2532 if(opcode[i]==0x0a) // SLTI
2533 emit_slti64_32(sh,sl,imm[i],t);
2534 else // SLTIU
2535 emit_sltiu64_32(sh,sl,imm[i],t);
2536 }
2537 }else{
2538 // SLTI(U) with r0 is just stupid,
2539 // nonetheless examples can be found
2540 if(opcode[i]==0x0a) // SLTI
2541 if(0<imm[i]) emit_movimm(1,t);
2542 else emit_zeroreg(t);
2543 else // SLTIU
2544 {
2545 if(imm[i]) emit_movimm(1,t);
2546 else emit_zeroreg(t);
2547 }
2548 }
2549 }
2550 }
2551 }
2552 else if(opcode[i]>=0x0c&&opcode[i]<=0x0e) { // ANDI/ORI/XORI
2553 if(rt1[i]) {
2554 signed char sh,sl,th,tl;
2555 th=get_reg(i_regs->regmap,rt1[i]|64);
2556 tl=get_reg(i_regs->regmap,rt1[i]);
2557 sh=get_reg(i_regs->regmap,rs1[i]|64);
2558 sl=get_reg(i_regs->regmap,rs1[i]);
2559 if(tl>=0 && !((i_regs->isconst>>tl)&1)) {
2560 if(opcode[i]==0x0c) //ANDI
2561 {
2562 if(rs1[i]) {
2563 if(sl<0) {
2564 if(i_regs->regmap_entry[tl]!=rs1[i]) emit_loadreg(rs1[i],tl);
2565 emit_andimm(tl,imm[i],tl);
2566 }else{
2567 if(!((i_regs->wasconst>>sl)&1))
2568 emit_andimm(sl,imm[i],tl);
2569 else
2570 emit_movimm(constmap[i][sl]&imm[i],tl);
2571 }
2572 }
2573 else
2574 emit_zeroreg(tl);
2575 if(th>=0) emit_zeroreg(th);
2576 }
2577 else
2578 {
2579 if(rs1[i]) {
2580 if(sl<0) {
2581 if(i_regs->regmap_entry[tl]!=rs1[i]) emit_loadreg(rs1[i],tl);
2582 }
2583 if(th>=0) {
2584 if(sh<0) {
2585 emit_loadreg(rs1[i]|64,th);
2586 }else{
2587 emit_mov(sh,th);
2588 }
2589 }
2590 if(opcode[i]==0x0d) //ORI
2591 if(sl<0) {
2592 emit_orimm(tl,imm[i],tl);
2593 }else{
2594 if(!((i_regs->wasconst>>sl)&1))
2595 emit_orimm(sl,imm[i],tl);
2596 else
2597 emit_movimm(constmap[i][sl]|imm[i],tl);
2598 }
2599 if(opcode[i]==0x0e) //XORI
2600 if(sl<0) {
2601 emit_xorimm(tl,imm[i],tl);
2602 }else{
2603 if(!((i_regs->wasconst>>sl)&1))
2604 emit_xorimm(sl,imm[i],tl);
2605 else
2606 emit_movimm(constmap[i][sl]^imm[i],tl);
2607 }
2608 }
2609 else {
2610 emit_movimm(imm[i],tl);
2611 if(th>=0) emit_zeroreg(th);
2612 }
2613 }
2614 }
2615 }
2616 }
2617}
2618
2619void shiftimm_assemble(int i,struct regstat *i_regs)
2620{
2621 if(opcode2[i]<=0x3) // SLL/SRL/SRA
2622 {
2623 if(rt1[i]) {
2624 signed char s,t;
2625 t=get_reg(i_regs->regmap,rt1[i]);
2626 s=get_reg(i_regs->regmap,rs1[i]);
2627 //assert(t>=0);
2628 if(t>=0){
2629 if(rs1[i]==0)
2630 {
2631 emit_zeroreg(t);
2632 }
2633 else
2634 {
2635 if(s<0&&i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2636 if(imm[i]) {
2637 if(opcode2[i]==0) // SLL
2638 {
2639 emit_shlimm(s<0?t:s,imm[i],t);
2640 }
2641 if(opcode2[i]==2) // SRL
2642 {
2643 emit_shrimm(s<0?t:s,imm[i],t);
2644 }
2645 if(opcode2[i]==3) // SRA
2646 {
2647 emit_sarimm(s<0?t:s,imm[i],t);
2648 }
2649 }else{
2650 // Shift by zero
2651 if(s>=0 && s!=t) emit_mov(s,t);
2652 }
2653 }
2654 }
2655 //emit_storereg(rt1[i],t); //DEBUG
2656 }
2657 }
2658 if(opcode2[i]>=0x38&&opcode2[i]<=0x3b) // DSLL/DSRL/DSRA
2659 {
2660 if(rt1[i]) {
2661 signed char sh,sl,th,tl;
2662 th=get_reg(i_regs->regmap,rt1[i]|64);
2663 tl=get_reg(i_regs->regmap,rt1[i]);
2664 sh=get_reg(i_regs->regmap,rs1[i]|64);
2665 sl=get_reg(i_regs->regmap,rs1[i]);
2666 if(tl>=0) {
2667 if(rs1[i]==0)
2668 {
2669 emit_zeroreg(tl);
2670 if(th>=0) emit_zeroreg(th);
2671 }
2672 else
2673 {
2674 assert(sl>=0);
2675 assert(sh>=0);
2676 if(imm[i]) {
2677 if(opcode2[i]==0x38) // DSLL
2678 {
2679 if(th>=0) emit_shldimm(sh,sl,imm[i],th);
2680 emit_shlimm(sl,imm[i],tl);
2681 }
2682 if(opcode2[i]==0x3a) // DSRL
2683 {
2684 emit_shrdimm(sl,sh,imm[i],tl);
2685 if(th>=0) emit_shrimm(sh,imm[i],th);
2686 }
2687 if(opcode2[i]==0x3b) // DSRA
2688 {
2689 emit_shrdimm(sl,sh,imm[i],tl);
2690 if(th>=0) emit_sarimm(sh,imm[i],th);
2691 }
2692 }else{
2693 // Shift by zero
2694 if(sl!=tl) emit_mov(sl,tl);
2695 if(th>=0&&sh!=th) emit_mov(sh,th);
2696 }
2697 }
2698 }
2699 }
2700 }
2701 if(opcode2[i]==0x3c) // DSLL32
2702 {
2703 if(rt1[i]) {
2704 signed char sl,tl,th;
2705 tl=get_reg(i_regs->regmap,rt1[i]);
2706 th=get_reg(i_regs->regmap,rt1[i]|64);
2707 sl=get_reg(i_regs->regmap,rs1[i]);
2708 if(th>=0||tl>=0){
2709 assert(tl>=0);
2710 assert(th>=0);
2711 assert(sl>=0);
2712 emit_mov(sl,th);
2713 emit_zeroreg(tl);
2714 if(imm[i]>32)
2715 {
2716 emit_shlimm(th,imm[i]&31,th);
2717 }
2718 }
2719 }
2720 }
2721 if(opcode2[i]==0x3e) // DSRL32
2722 {
2723 if(rt1[i]) {
2724 signed char sh,tl,th;
2725 tl=get_reg(i_regs->regmap,rt1[i]);
2726 th=get_reg(i_regs->regmap,rt1[i]|64);
2727 sh=get_reg(i_regs->regmap,rs1[i]|64);
2728 if(tl>=0){
2729 assert(sh>=0);
2730 emit_mov(sh,tl);
2731 if(th>=0) emit_zeroreg(th);
2732 if(imm[i]>32)
2733 {
2734 emit_shrimm(tl,imm[i]&31,tl);
2735 }
2736 }
2737 }
2738 }
2739 if(opcode2[i]==0x3f) // DSRA32
2740 {
2741 if(rt1[i]) {
2742 signed char sh,tl;
2743 tl=get_reg(i_regs->regmap,rt1[i]);
2744 sh=get_reg(i_regs->regmap,rs1[i]|64);
2745 if(tl>=0){
2746 assert(sh>=0);
2747 emit_mov(sh,tl);
2748 if(imm[i]>32)
2749 {
2750 emit_sarimm(tl,imm[i]&31,tl);
2751 }
2752 }
2753 }
2754 }
2755}
2756
2757#ifndef shift_assemble
2758void shift_assemble(int i,struct regstat *i_regs)
2759{
2760 printf("Need shift_assemble for this architecture.\n");
2761 exit(1);
2762}
2763#endif
2764
2765void load_assemble(int i,struct regstat *i_regs)
2766{
2767 int s,th,tl,addr,map=-1;
2768 int offset;
2769 int jaddr=0;
5bf843dc 2770 int memtarget=0,c=0;
b1570849 2771 int fastload_reg_override=0;
57871462 2772 u_int hr,reglist=0;
2773 th=get_reg(i_regs->regmap,rt1[i]|64);
2774 tl=get_reg(i_regs->regmap,rt1[i]);
2775 s=get_reg(i_regs->regmap,rs1[i]);
2776 offset=imm[i];
2777 for(hr=0;hr<HOST_REGS;hr++) {
2778 if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
2779 }
2780 if(i_regs->regmap[HOST_CCREG]==CCREG) reglist&=~(1<<HOST_CCREG);
2781 if(s>=0) {
2782 c=(i_regs->wasconst>>s)&1;
af4ee1fe 2783 if (c) {
2784 memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
2785 if(using_tlb&&((signed int)(constmap[i][s]+offset))>=(signed int)0xC0000000) memtarget=1;
2786 }
57871462 2787 }
57871462 2788 //printf("load_assemble: c=%d\n",c);
2789 //if(c) printf("load_assemble: const=%x\n",(int)constmap[i][s]+offset);
2790 // FIXME: Even if the load is a NOP, we should check for pagefaults...
5bf843dc 2791#ifdef PCSX
f18c0f46 2792 if(tl<0&&(!c||(((u_int)constmap[i][s]+offset)>>16)==0x1f80)
2793 ||rt1[i]==0) {
5bf843dc 2794 // could be FIFO, must perform the read
f18c0f46 2795 // ||dummy read
5bf843dc 2796 assem_debug("(forced read)\n");
2797 tl=get_reg(i_regs->regmap,-1);
2798 assert(tl>=0);
5bf843dc 2799 }
f18c0f46 2800#endif
5bf843dc 2801 if(offset||s<0||c) addr=tl;
2802 else addr=s;
535d208a 2803 //if(tl<0) tl=get_reg(i_regs->regmap,-1);
2804 if(tl>=0) {
2805 //printf("load_assemble: c=%d\n",c);
2806 //if(c) printf("load_assemble: const=%x\n",(int)constmap[i][s]+offset);
2807 assert(tl>=0); // Even if the load is a NOP, we must check for pagefaults and I/O
2808 reglist&=~(1<<tl);
2809 if(th>=0) reglist&=~(1<<th);
2810 if(!using_tlb) {
2811 if(!c) {
2812 #ifdef RAM_OFFSET
2813 map=get_reg(i_regs->regmap,ROREG);
2814 if(map<0) emit_loadreg(ROREG,map=HOST_TEMPREG);
2815 #endif
57871462 2816//#define R29_HACK 1
535d208a 2817 #ifdef R29_HACK
2818 // Strmnnrmn's speed hack
2819 if(rs1[i]!=29||start<0x80001000||start>=0x80000000+RAM_SIZE)
2820 #endif
2821 {
dadf55f2 2822 #ifdef PCSX
2823 if(sp_in_mirror&&rs1[i]==29) {
2824 emit_andimm(addr,~0x00e00000,HOST_TEMPREG);
2825 emit_cmpimm(HOST_TEMPREG,RAM_SIZE);
b1570849 2826 fastload_reg_override=HOST_TEMPREG;
dadf55f2 2827 }
2828 else
2829 #endif
535d208a 2830 emit_cmpimm(addr,RAM_SIZE);
2831 jaddr=(int)out;
2832 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
2833 // Hint to branch predictor that the branch is unlikely to be taken
2834 if(rs1[i]>=28)
2835 emit_jno_unlikely(0);
2836 else
57871462 2837 #endif
535d208a 2838 emit_jno(0);
57871462 2839 }
535d208a 2840 }
2841 }else{ // using tlb
2842 int x=0;
2843 if (opcode[i]==0x20||opcode[i]==0x24) x=3; // LB/LBU
2844 if (opcode[i]==0x21||opcode[i]==0x25) x=2; // LH/LHU
2845 map=get_reg(i_regs->regmap,TLREG);
2846 assert(map>=0);
ea3d2e6e 2847 reglist&=~(1<<map);
535d208a 2848 map=do_tlb_r(addr,tl,map,x,-1,-1,c,constmap[i][s]+offset);
2849 do_tlb_r_branch(map,c,constmap[i][s]+offset,&jaddr);
2850 }
2851 int dummy=(rt1[i]==0)||(tl!=get_reg(i_regs->regmap,rt1[i])); // ignore loads to r0 and unneeded reg
2852 if (opcode[i]==0x20) { // LB
2853 if(!c||memtarget) {
2854 if(!dummy) {
57871462 2855 #ifdef HOST_IMM_ADDR32
2856 if(c)
2857 emit_movsbl_tlb((constmap[i][s]+offset)^3,map,tl);
2858 else
2859 #endif
2860 {
2861 //emit_xorimm(addr,3,tl);
2862 //gen_tlb_addr_r(tl,map);
2863 //emit_movsbl_indexed((int)rdram-0x80000000,tl,tl);
535d208a 2864 int x=0,a=tl;
2002a1db 2865#ifdef BIG_ENDIAN_MIPS
57871462 2866 if(!c) emit_xorimm(addr,3,tl);
2867 else x=((constmap[i][s]+offset)^3)-(constmap[i][s]+offset);
2002a1db 2868#else
535d208a 2869 if(!c) a=addr;
dadf55f2 2870#endif
b1570849 2871 if(fastload_reg_override) a=fastload_reg_override;
2872
535d208a 2873 emit_movsbl_indexed_tlb(x,a,map,tl);
57871462 2874 }
57871462 2875 }
535d208a 2876 if(jaddr)
2877 add_stub(LOADB_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
57871462 2878 }
535d208a 2879 else
2880 inline_readstub(LOADB_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2881 }
2882 if (opcode[i]==0x21) { // LH
2883 if(!c||memtarget) {
2884 if(!dummy) {
57871462 2885 #ifdef HOST_IMM_ADDR32
2886 if(c)
2887 emit_movswl_tlb((constmap[i][s]+offset)^2,map,tl);
2888 else
2889 #endif
2890 {
535d208a 2891 int x=0,a=tl;
2002a1db 2892#ifdef BIG_ENDIAN_MIPS
57871462 2893 if(!c) emit_xorimm(addr,2,tl);
2894 else x=((constmap[i][s]+offset)^2)-(constmap[i][s]+offset);
2002a1db 2895#else
535d208a 2896 if(!c) a=addr;
dadf55f2 2897#endif
b1570849 2898 if(fastload_reg_override) a=fastload_reg_override;
57871462 2899 //#ifdef
2900 //emit_movswl_indexed_tlb(x,tl,map,tl);
2901 //else
2902 if(map>=0) {
535d208a 2903 gen_tlb_addr_r(a,map);
2904 emit_movswl_indexed(x,a,tl);
2905 }else{
2906 #ifdef RAM_OFFSET
2907 emit_movswl_indexed(x,a,tl);
2908 #else
2909 emit_movswl_indexed((int)rdram-0x80000000+x,a,tl);
2910 #endif
2911 }
57871462 2912 }
57871462 2913 }
535d208a 2914 if(jaddr)
2915 add_stub(LOADH_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
57871462 2916 }
535d208a 2917 else
2918 inline_readstub(LOADH_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2919 }
2920 if (opcode[i]==0x23) { // LW
2921 if(!c||memtarget) {
2922 if(!dummy) {
dadf55f2 2923 int a=addr;
b1570849 2924 if(fastload_reg_override) a=fastload_reg_override;
57871462 2925 //emit_readword_indexed((int)rdram-0x80000000,addr,tl);
2926 #ifdef HOST_IMM_ADDR32
2927 if(c)
2928 emit_readword_tlb(constmap[i][s]+offset,map,tl);
2929 else
2930 #endif
dadf55f2 2931 emit_readword_indexed_tlb(0,a,map,tl);
57871462 2932 }
535d208a 2933 if(jaddr)
2934 add_stub(LOADW_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
57871462 2935 }
535d208a 2936 else
2937 inline_readstub(LOADW_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2938 }
2939 if (opcode[i]==0x24) { // LBU
2940 if(!c||memtarget) {
2941 if(!dummy) {
57871462 2942 #ifdef HOST_IMM_ADDR32
2943 if(c)
2944 emit_movzbl_tlb((constmap[i][s]+offset)^3,map,tl);
2945 else
2946 #endif
2947 {
2948 //emit_xorimm(addr,3,tl);
2949 //gen_tlb_addr_r(tl,map);
2950 //emit_movzbl_indexed((int)rdram-0x80000000,tl,tl);
535d208a 2951 int x=0,a=tl;
2002a1db 2952#ifdef BIG_ENDIAN_MIPS
57871462 2953 if(!c) emit_xorimm(addr,3,tl);
2954 else x=((constmap[i][s]+offset)^3)-(constmap[i][s]+offset);
2002a1db 2955#else
535d208a 2956 if(!c) a=addr;
dadf55f2 2957#endif
b1570849 2958 if(fastload_reg_override) a=fastload_reg_override;
2959
535d208a 2960 emit_movzbl_indexed_tlb(x,a,map,tl);
57871462 2961 }
57871462 2962 }
535d208a 2963 if(jaddr)
2964 add_stub(LOADBU_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
57871462 2965 }
535d208a 2966 else
2967 inline_readstub(LOADBU_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2968 }
2969 if (opcode[i]==0x25) { // LHU
2970 if(!c||memtarget) {
2971 if(!dummy) {
57871462 2972 #ifdef HOST_IMM_ADDR32
2973 if(c)
2974 emit_movzwl_tlb((constmap[i][s]+offset)^2,map,tl);
2975 else
2976 #endif
2977 {
535d208a 2978 int x=0,a=tl;
2002a1db 2979#ifdef BIG_ENDIAN_MIPS
57871462 2980 if(!c) emit_xorimm(addr,2,tl);
2981 else x=((constmap[i][s]+offset)^2)-(constmap[i][s]+offset);
2002a1db 2982#else
535d208a 2983 if(!c) a=addr;
dadf55f2 2984#endif
b1570849 2985 if(fastload_reg_override) a=fastload_reg_override;
57871462 2986 //#ifdef
2987 //emit_movzwl_indexed_tlb(x,tl,map,tl);
2988 //#else
2989 if(map>=0) {
535d208a 2990 gen_tlb_addr_r(a,map);
2991 emit_movzwl_indexed(x,a,tl);
2992 }else{
2993 #ifdef RAM_OFFSET
2994 emit_movzwl_indexed(x,a,tl);
2995 #else
2996 emit_movzwl_indexed((int)rdram-0x80000000+x,a,tl);
2997 #endif
2998 }
57871462 2999 }
3000 }
535d208a 3001 if(jaddr)
3002 add_stub(LOADHU_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
57871462 3003 }
535d208a 3004 else
3005 inline_readstub(LOADHU_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
3006 }
3007 if (opcode[i]==0x27) { // LWU
3008 assert(th>=0);
3009 if(!c||memtarget) {
3010 if(!dummy) {
dadf55f2 3011 int a=addr;
b1570849 3012 if(fastload_reg_override) a=fastload_reg_override;
57871462 3013 //emit_readword_indexed((int)rdram-0x80000000,addr,tl);
3014 #ifdef HOST_IMM_ADDR32
3015 if(c)
3016 emit_readword_tlb(constmap[i][s]+offset,map,tl);
3017 else
3018 #endif
dadf55f2 3019 emit_readword_indexed_tlb(0,a,map,tl);
57871462 3020 }
535d208a 3021 if(jaddr)
3022 add_stub(LOADW_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
3023 }
3024 else {
3025 inline_readstub(LOADW_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
57871462 3026 }
535d208a 3027 emit_zeroreg(th);
3028 }
3029 if (opcode[i]==0x37) { // LD
3030 if(!c||memtarget) {
3031 if(!dummy) {
dadf55f2 3032 int a=addr;
b1570849 3033 if(fastload_reg_override) a=fastload_reg_override;
57871462 3034 //gen_tlb_addr_r(tl,map);
3035 //if(th>=0) emit_readword_indexed((int)rdram-0x80000000,addr,th);
3036 //emit_readword_indexed((int)rdram-0x7FFFFFFC,addr,tl);
3037 #ifdef HOST_IMM_ADDR32
3038 if(c)
3039 emit_readdword_tlb(constmap[i][s]+offset,map,th,tl);
3040 else
3041 #endif
dadf55f2 3042 emit_readdword_indexed_tlb(0,a,map,th,tl);
57871462 3043 }
535d208a 3044 if(jaddr)
3045 add_stub(LOADD_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
57871462 3046 }
535d208a 3047 else
3048 inline_readstub(LOADD_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
57871462 3049 }
535d208a 3050 }
3051 //emit_storereg(rt1[i],tl); // DEBUG
57871462 3052 //if(opcode[i]==0x23)
3053 //if(opcode[i]==0x24)
3054 //if(opcode[i]==0x23||opcode[i]==0x24)
3055 /*if(opcode[i]==0x21||opcode[i]==0x23||opcode[i]==0x24)
3056 {
3057 //emit_pusha();
3058 save_regs(0x100f);
3059 emit_readword((int)&last_count,ECX);
3060 #ifdef __i386__
3061 if(get_reg(i_regs->regmap,CCREG)<0)
3062 emit_loadreg(CCREG,HOST_CCREG);
3063 emit_add(HOST_CCREG,ECX,HOST_CCREG);
3064 emit_addimm(HOST_CCREG,2*ccadj[i],HOST_CCREG);
3065 emit_writeword(HOST_CCREG,(int)&Count);
3066 #endif
3067 #ifdef __arm__
3068 if(get_reg(i_regs->regmap,CCREG)<0)
3069 emit_loadreg(CCREG,0);
3070 else
3071 emit_mov(HOST_CCREG,0);
3072 emit_add(0,ECX,0);
3073 emit_addimm(0,2*ccadj[i],0);
3074 emit_writeword(0,(int)&Count);
3075 #endif
3076 emit_call((int)memdebug);
3077 //emit_popa();
3078 restore_regs(0x100f);
3079 }/**/
3080}
3081
3082#ifndef loadlr_assemble
3083void loadlr_assemble(int i,struct regstat *i_regs)
3084{
3085 printf("Need loadlr_assemble for this architecture.\n");
3086 exit(1);
3087}
3088#endif
3089
3090void store_assemble(int i,struct regstat *i_regs)
3091{
3092 int s,th,tl,map=-1;
3093 int addr,temp;
3094 int offset;
3095 int jaddr=0,jaddr2,type;
666a299d 3096 int memtarget=0,c=0;
57871462 3097 int agr=AGEN1+(i&1);
b1570849 3098 int faststore_reg_override=0;
57871462 3099 u_int hr,reglist=0;
3100 th=get_reg(i_regs->regmap,rs2[i]|64);
3101 tl=get_reg(i_regs->regmap,rs2[i]);
3102 s=get_reg(i_regs->regmap,rs1[i]);
3103 temp=get_reg(i_regs->regmap,agr);
3104 if(temp<0) temp=get_reg(i_regs->regmap,-1);
3105 offset=imm[i];
3106 if(s>=0) {
3107 c=(i_regs->wasconst>>s)&1;
af4ee1fe 3108 if(c) {
3109 memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
3110 if(using_tlb&&((signed int)(constmap[i][s]+offset))>=(signed int)0xC0000000) memtarget=1;
3111 }
57871462 3112 }
3113 assert(tl>=0);
3114 assert(temp>=0);
3115 for(hr=0;hr<HOST_REGS;hr++) {
3116 if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
3117 }
3118 if(i_regs->regmap[HOST_CCREG]==CCREG) reglist&=~(1<<HOST_CCREG);
3119 if(offset||s<0||c) addr=temp;
3120 else addr=s;
3121 if(!using_tlb) {
3122 if(!c) {
dadf55f2 3123 #ifdef PCSX
3124 if(sp_in_mirror&&rs1[i]==29) {
3125 emit_andimm(addr,~0x00e00000,HOST_TEMPREG);
3126 emit_cmpimm(HOST_TEMPREG,RAM_SIZE);
b1570849 3127 faststore_reg_override=HOST_TEMPREG;
dadf55f2 3128 }
3129 else
3130 #endif
57871462 3131 #ifdef R29_HACK
3132 // Strmnnrmn's speed hack
4cb76aa4 3133 if(rs1[i]!=29||start<0x80001000||start>=0x80000000+RAM_SIZE)
57871462 3134 #endif
4cb76aa4 3135 emit_cmpimm(addr,RAM_SIZE);
57871462 3136 #ifdef DESTRUCTIVE_SHIFT
3137 if(s==addr) emit_mov(s,temp);
3138 #endif
3139 #ifdef R29_HACK
dadf55f2 3140 memtarget=1;
4cb76aa4 3141 if(rs1[i]!=29||start<0x80001000||start>=0x80000000+RAM_SIZE)
57871462 3142 #endif
3143 {
3144 jaddr=(int)out;
3145 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
3146 // Hint to branch predictor that the branch is unlikely to be taken
3147 if(rs1[i]>=28)
3148 emit_jno_unlikely(0);
3149 else
3150 #endif
3151 emit_jno(0);
3152 }
3153 }
3154 }else{ // using tlb
3155 int x=0;
3156 if (opcode[i]==0x28) x=3; // SB
3157 if (opcode[i]==0x29) x=2; // SH
3158 map=get_reg(i_regs->regmap,TLREG);
3159 assert(map>=0);
ea3d2e6e 3160 reglist&=~(1<<map);
57871462 3161 map=do_tlb_w(addr,temp,map,x,c,constmap[i][s]+offset);
3162 do_tlb_w_branch(map,c,constmap[i][s]+offset,&jaddr);
3163 }
3164
3165 if (opcode[i]==0x28) { // SB
3166 if(!c||memtarget) {
97a238a6 3167 int x=0,a=temp;
2002a1db 3168#ifdef BIG_ENDIAN_MIPS
57871462 3169 if(!c) emit_xorimm(addr,3,temp);
3170 else x=((constmap[i][s]+offset)^3)-(constmap[i][s]+offset);
2002a1db 3171#else
97a238a6 3172 if(!c) a=addr;
dadf55f2 3173#endif
b1570849 3174 if(faststore_reg_override) a=faststore_reg_override;
57871462 3175 //gen_tlb_addr_w(temp,map);
3176 //emit_writebyte_indexed(tl,(int)rdram-0x80000000,temp);
97a238a6 3177 emit_writebyte_indexed_tlb(tl,x,a,map,a);
57871462 3178 }
3179 type=STOREB_STUB;
3180 }
3181 if (opcode[i]==0x29) { // SH
3182 if(!c||memtarget) {
97a238a6 3183 int x=0,a=temp;
2002a1db 3184#ifdef BIG_ENDIAN_MIPS
57871462 3185 if(!c) emit_xorimm(addr,2,temp);
3186 else x=((constmap[i][s]+offset)^2)-(constmap[i][s]+offset);
2002a1db 3187#else
97a238a6 3188 if(!c) a=addr;
dadf55f2 3189#endif
b1570849 3190 if(faststore_reg_override) a=faststore_reg_override;
57871462 3191 //#ifdef
3192 //emit_writehword_indexed_tlb(tl,x,temp,map,temp);
3193 //#else
3194 if(map>=0) {
97a238a6 3195 gen_tlb_addr_w(a,map);
3196 emit_writehword_indexed(tl,x,a);
57871462 3197 }else
97a238a6 3198 emit_writehword_indexed(tl,(int)rdram-0x80000000+x,a);
57871462 3199 }
3200 type=STOREH_STUB;
3201 }
3202 if (opcode[i]==0x2B) { // SW
dadf55f2 3203 if(!c||memtarget) {
3204 int a=addr;
b1570849 3205 if(faststore_reg_override) a=faststore_reg_override;
57871462 3206 //emit_writeword_indexed(tl,(int)rdram-0x80000000,addr);
dadf55f2 3207 emit_writeword_indexed_tlb(tl,0,a,map,temp);
3208 }
57871462 3209 type=STOREW_STUB;
3210 }
3211 if (opcode[i]==0x3F) { // SD
3212 if(!c||memtarget) {
dadf55f2 3213 int a=addr;
b1570849 3214 if(faststore_reg_override) a=faststore_reg_override;
57871462 3215 if(rs2[i]) {
3216 assert(th>=0);
3217 //emit_writeword_indexed(th,(int)rdram-0x80000000,addr);
3218 //emit_writeword_indexed(tl,(int)rdram-0x7FFFFFFC,addr);
dadf55f2 3219 emit_writedword_indexed_tlb(th,tl,0,a,map,temp);
57871462 3220 }else{
3221 // Store zero
3222 //emit_writeword_indexed(tl,(int)rdram-0x80000000,temp);
3223 //emit_writeword_indexed(tl,(int)rdram-0x7FFFFFFC,temp);
dadf55f2 3224 emit_writedword_indexed_tlb(tl,tl,0,a,map,temp);
57871462 3225 }
3226 }
3227 type=STORED_STUB;
3228 }
57871462 3229 if(!using_tlb) {
3230 if(!c||memtarget) {
3231 #ifdef DESTRUCTIVE_SHIFT
3232 // The x86 shift operation is 'destructive'; it overwrites the
3233 // source register, so we need to make a copy first and use that.
3234 addr=temp;
3235 #endif
3236 #if defined(HOST_IMM8)
3237 int ir=get_reg(i_regs->regmap,INVCP);
3238 assert(ir>=0);
3239 emit_cmpmem_indexedsr12_reg(ir,addr,1);
3240 #else
3241 emit_cmpmem_indexedsr12_imm((int)invalid_code,addr,1);
3242 #endif
0bbd1454 3243 #if defined(HAVE_CONDITIONAL_CALL) && !defined(DESTRUCTIVE_SHIFT)
3244 emit_callne(invalidate_addr_reg[addr]);
3245 #else
57871462 3246 jaddr2=(int)out;
3247 emit_jne(0);
3248 add_stub(INVCODE_STUB,jaddr2,(int)out,reglist|(1<<HOST_CCREG),addr,0,0,0);
0bbd1454 3249 #endif
57871462 3250 }
3251 }
3eaa7048 3252 if(jaddr) {
3253 add_stub(type,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
3254 } else if(c&&!memtarget) {
3255 inline_writestub(type,i,constmap[i][s]+offset,i_regs->regmap,rs2[i],ccadj[i],reglist);
3256 }
57871462 3257 //if(opcode[i]==0x2B || opcode[i]==0x3F)
3258 //if(opcode[i]==0x2B || opcode[i]==0x28)
3259 //if(opcode[i]==0x2B || opcode[i]==0x29)
3260 //if(opcode[i]==0x2B)
3261 /*if(opcode[i]==0x2B || opcode[i]==0x28 || opcode[i]==0x29 || opcode[i]==0x3F)
3262 {
28d74ee8 3263 #ifdef __i386__
3264 emit_pusha();
3265 #endif
3266 #ifdef __arm__
57871462 3267 save_regs(0x100f);
28d74ee8 3268 #endif
57871462 3269 emit_readword((int)&last_count,ECX);
3270 #ifdef __i386__
3271 if(get_reg(i_regs->regmap,CCREG)<0)
3272 emit_loadreg(CCREG,HOST_CCREG);
3273 emit_add(HOST_CCREG,ECX,HOST_CCREG);
3274 emit_addimm(HOST_CCREG,2*ccadj[i],HOST_CCREG);
3275 emit_writeword(HOST_CCREG,(int)&Count);
3276 #endif
3277 #ifdef __arm__
3278 if(get_reg(i_regs->regmap,CCREG)<0)
3279 emit_loadreg(CCREG,0);
3280 else
3281 emit_mov(HOST_CCREG,0);
3282 emit_add(0,ECX,0);
3283 emit_addimm(0,2*ccadj[i],0);
3284 emit_writeword(0,(int)&Count);
3285 #endif
3286 emit_call((int)memdebug);
28d74ee8 3287 #ifdef __i386__
3288 emit_popa();
3289 #endif
3290 #ifdef __arm__
57871462 3291 restore_regs(0x100f);
28d74ee8 3292 #endif
57871462 3293 }/**/
3294}
3295
3296void storelr_assemble(int i,struct regstat *i_regs)
3297{
3298 int s,th,tl;
3299 int temp;
3300 int temp2;
3301 int offset;