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Revert "drc: ujump DS $ra overwrite fix?"
[pcsx_rearmed.git] / libpcsxcore / new_dynarec / new_dynarec.c
CommitLineData
57871462 1/* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
2 * Mupen64plus - new_dynarec.c *
20d507ba 3 * Copyright (C) 2009-2011 Ari64 *
57871462 4 * *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
9 * *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
14 * *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. *
19 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */
20
21#include <stdlib.h>
22#include <stdint.h> //include for uint64_t
23#include <assert.h>
24
3d624f89 25#include "emu_if.h" //emulator interface
57871462 26
27#include <sys/mman.h>
28
29#ifdef __i386__
30#include "assem_x86.h"
31#endif
32#ifdef __x86_64__
33#include "assem_x64.h"
34#endif
35#ifdef __arm__
36#include "assem_arm.h"
37#endif
38
39#define MAXBLOCK 4096
40#define MAX_OUTPUT_BLOCK_SIZE 262144
41#define CLOCK_DIVIDER 2
42
43struct regstat
44{
45 signed char regmap_entry[HOST_REGS];
46 signed char regmap[HOST_REGS];
47 uint64_t was32;
48 uint64_t is32;
49 uint64_t wasdirty;
50 uint64_t dirty;
51 uint64_t u;
52 uint64_t uu;
53 u_int wasconst;
54 u_int isconst;
55 uint64_t constmap[HOST_REGS];
56};
57
58struct ll_entry
59{
60 u_int vaddr;
61 u_int reg32;
62 void *addr;
63 struct ll_entry *next;
64};
65
66 u_int start;
67 u_int *source;
68 u_int pagelimit;
69 char insn[MAXBLOCK][10];
70 u_char itype[MAXBLOCK];
71 u_char opcode[MAXBLOCK];
72 u_char opcode2[MAXBLOCK];
73 u_char bt[MAXBLOCK];
74 u_char rs1[MAXBLOCK];
75 u_char rs2[MAXBLOCK];
76 u_char rt1[MAXBLOCK];
77 u_char rt2[MAXBLOCK];
78 u_char us1[MAXBLOCK];
79 u_char us2[MAXBLOCK];
80 u_char dep1[MAXBLOCK];
81 u_char dep2[MAXBLOCK];
82 u_char lt1[MAXBLOCK];
83 int imm[MAXBLOCK];
84 u_int ba[MAXBLOCK];
85 char likely[MAXBLOCK];
86 char is_ds[MAXBLOCK];
e1190b87 87 char ooo[MAXBLOCK];
57871462 88 uint64_t unneeded_reg[MAXBLOCK];
89 uint64_t unneeded_reg_upper[MAXBLOCK];
90 uint64_t branch_unneeded_reg[MAXBLOCK];
91 uint64_t branch_unneeded_reg_upper[MAXBLOCK];
92 uint64_t p32[MAXBLOCK];
93 uint64_t pr32[MAXBLOCK];
94 signed char regmap_pre[MAXBLOCK][HOST_REGS];
95 signed char regmap[MAXBLOCK][HOST_REGS];
96 signed char regmap_entry[MAXBLOCK][HOST_REGS];
97 uint64_t constmap[MAXBLOCK][HOST_REGS];
57871462 98 struct regstat regs[MAXBLOCK];
99 struct regstat branch_regs[MAXBLOCK];
e1190b87 100 signed char minimum_free_regs[MAXBLOCK];
57871462 101 u_int needed_reg[MAXBLOCK];
102 uint64_t requires_32bit[MAXBLOCK];
103 u_int wont_dirty[MAXBLOCK];
104 u_int will_dirty[MAXBLOCK];
105 int ccadj[MAXBLOCK];
106 int slen;
107 u_int instr_addr[MAXBLOCK];
108 u_int link_addr[MAXBLOCK][3];
109 int linkcount;
110 u_int stubs[MAXBLOCK*3][8];
111 int stubcount;
112 u_int literals[1024][2];
113 int literalcount;
114 int is_delayslot;
115 int cop1_usable;
116 u_char *out;
117 struct ll_entry *jump_in[4096];
118 struct ll_entry *jump_out[4096];
119 struct ll_entry *jump_dirty[4096];
120 u_int hash_table[65536][4] __attribute__((aligned(16)));
121 char shadow[1048576] __attribute__((aligned(16)));
122 void *copy;
123 int expirep;
af4ee1fe 124#ifndef PCSX
57871462 125 u_int using_tlb;
af4ee1fe 126#else
127 static const u_int using_tlb=0;
128#endif
dadf55f2 129 static u_int sp_in_mirror;
57871462 130 u_int stop_after_jal;
131 extern u_char restore_candidate[512];
132 extern int cycle_count;
133
134 /* registers that may be allocated */
135 /* 1-31 gpr */
136#define HIREG 32 // hi
137#define LOREG 33 // lo
138#define FSREG 34 // FPU status (FCSR)
139#define CSREG 35 // Coprocessor status
140#define CCREG 36 // Cycle count
141#define INVCP 37 // Pointer to invalid_code
619e5ded 142#define MMREG 38 // Pointer to memory_map
143#define ROREG 39 // ram offset (if rdram!=0x80000000)
144#define TEMPREG 40
145#define FTEMP 40 // FPU temporary register
146#define PTEMP 41 // Prefetch temporary register
147#define TLREG 42 // TLB mapping offset
148#define RHASH 43 // Return address hash
149#define RHTBL 44 // Return address hash table address
150#define RTEMP 45 // JR/JALR address register
151#define MAXREG 45
152#define AGEN1 46 // Address generation temporary register
153#define AGEN2 47 // Address generation temporary register
154#define MGEN1 48 // Maptable address generation temporary register
155#define MGEN2 49 // Maptable address generation temporary register
156#define BTREG 50 // Branch target temporary register
57871462 157
158 /* instruction types */
159#define NOP 0 // No operation
160#define LOAD 1 // Load
161#define STORE 2 // Store
162#define LOADLR 3 // Unaligned load
163#define STORELR 4 // Unaligned store
164#define MOV 5 // Move
165#define ALU 6 // Arithmetic/logic
166#define MULTDIV 7 // Multiply/divide
167#define SHIFT 8 // Shift by register
168#define SHIFTIMM 9// Shift by immediate
169#define IMM16 10 // 16-bit immediate
170#define RJUMP 11 // Unconditional jump to register
171#define UJUMP 12 // Unconditional jump
172#define CJUMP 13 // Conditional branch (BEQ/BNE/BGTZ/BLEZ)
173#define SJUMP 14 // Conditional branch (regimm format)
174#define COP0 15 // Coprocessor 0
175#define COP1 16 // Coprocessor 1
176#define C1LS 17 // Coprocessor 1 load/store
177#define FJUMP 18 // Conditional branch (floating point)
178#define FLOAT 19 // Floating point unit
179#define FCONV 20 // Convert integer to float
180#define FCOMP 21 // Floating point compare (sets FSREG)
181#define SYSCALL 22// SYSCALL
182#define OTHER 23 // Other
183#define SPAN 24 // Branch/delay slot spans 2 pages
184#define NI 25 // Not implemented
7139f3c8 185#define HLECALL 26// PCSX fake opcodes for HLE
b9b61529 186#define COP2 27 // Coprocessor 2 move
187#define C2LS 28 // Coprocessor 2 load/store
188#define C2OP 29 // Coprocessor 2 operation
1e973cb0 189#define INTCALL 30// Call interpreter to handle rare corner cases
57871462 190
191 /* stubs */
192#define CC_STUB 1
193#define FP_STUB 2
194#define LOADB_STUB 3
195#define LOADH_STUB 4
196#define LOADW_STUB 5
197#define LOADD_STUB 6
198#define LOADBU_STUB 7
199#define LOADHU_STUB 8
200#define STOREB_STUB 9
201#define STOREH_STUB 10
202#define STOREW_STUB 11
203#define STORED_STUB 12
204#define STORELR_STUB 13
205#define INVCODE_STUB 14
206
207 /* branch codes */
208#define TAKEN 1
209#define NOTTAKEN 2
210#define NULLDS 3
211
212// asm linkage
213int new_recompile_block(int addr);
214void *get_addr_ht(u_int vaddr);
215void invalidate_block(u_int block);
216void invalidate_addr(u_int addr);
217void remove_hash(int vaddr);
218void jump_vaddr();
219void dyna_linker();
220void dyna_linker_ds();
221void verify_code();
222void verify_code_vm();
223void verify_code_ds();
224void cc_interrupt();
225void fp_exception();
226void fp_exception_ds();
227void jump_syscall();
7139f3c8 228void jump_syscall_hle();
57871462 229void jump_eret();
7139f3c8 230void jump_hlecall();
1e973cb0 231void jump_intcall();
7139f3c8 232void new_dyna_leave();
57871462 233
234// TLB
235void TLBWI_new();
236void TLBWR_new();
237void read_nomem_new();
238void read_nomemb_new();
239void read_nomemh_new();
240void read_nomemd_new();
241void write_nomem_new();
242void write_nomemb_new();
243void write_nomemh_new();
244void write_nomemd_new();
245void write_rdram_new();
246void write_rdramb_new();
247void write_rdramh_new();
248void write_rdramd_new();
249extern u_int memory_map[1048576];
250
251// Needed by assembler
252void wb_register(signed char r,signed char regmap[],uint64_t dirty,uint64_t is32);
253void wb_dirtys(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty);
254void wb_needed_dirtys(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr);
255void load_all_regs(signed char i_regmap[]);
256void load_needed_regs(signed char i_regmap[],signed char next_regmap[]);
257void load_regs_entry(int t);
258void load_all_consts(signed char regmap[],int is32,u_int dirty,int i);
259
260int tracedebug=0;
261
262//#define DEBUG_CYCLE_COUNT 1
263
264void nullf() {}
265//#define assem_debug printf
266//#define inv_debug printf
267#define assem_debug nullf
268#define inv_debug nullf
269
94d23bb9 270static void tlb_hacks()
57871462 271{
94d23bb9 272#ifndef DISABLE_TLB
57871462 273 // Goldeneye hack
274 if (strncmp((char *) ROM_HEADER->nom, "GOLDENEYE",9) == 0)
275 {
276 u_int addr;
277 int n;
278 switch (ROM_HEADER->Country_code&0xFF)
279 {
280 case 0x45: // U
281 addr=0x34b30;
282 break;
283 case 0x4A: // J
284 addr=0x34b70;
285 break;
286 case 0x50: // E
287 addr=0x329f0;
288 break;
289 default:
290 // Unknown country code
291 addr=0;
292 break;
293 }
294 u_int rom_addr=(u_int)rom;
295 #ifdef ROM_COPY
296 // Since memory_map is 32-bit, on 64-bit systems the rom needs to be
297 // in the lower 4G of memory to use this hack. Copy it if necessary.
298 if((void *)rom>(void *)0xffffffff) {
299 munmap(ROM_COPY, 67108864);
300 if(mmap(ROM_COPY, 12582912,
301 PROT_READ | PROT_WRITE,
302 MAP_FIXED | MAP_PRIVATE | MAP_ANONYMOUS,
303 -1, 0) <= 0) {printf("mmap() failed\n");}
304 memcpy(ROM_COPY,rom,12582912);
305 rom_addr=(u_int)ROM_COPY;
306 }
307 #endif
308 if(addr) {
309 for(n=0x7F000;n<0x80000;n++) {
310 memory_map[n]=(((u_int)(rom_addr+addr-0x7F000000))>>2)|0x40000000;
311 }
312 }
313 }
94d23bb9 314#endif
57871462 315}
316
94d23bb9 317static u_int get_page(u_int vaddr)
57871462 318{
0ce47d46 319#ifndef PCSX
57871462 320 u_int page=(vaddr^0x80000000)>>12;
0ce47d46 321#else
322 u_int page=vaddr&~0xe0000000;
323 if (page < 0x1000000)
324 page &= ~0x0e00000; // RAM mirrors
325 page>>=12;
326#endif
94d23bb9 327#ifndef DISABLE_TLB
57871462 328 if(page>262143&&tlb_LUT_r[vaddr>>12]) page=(tlb_LUT_r[vaddr>>12]^0x80000000)>>12;
94d23bb9 329#endif
57871462 330 if(page>2048) page=2048+(page&2047);
94d23bb9 331 return page;
332}
333
334static u_int get_vpage(u_int vaddr)
335{
336 u_int vpage=(vaddr^0x80000000)>>12;
337#ifndef DISABLE_TLB
57871462 338 if(vpage>262143&&tlb_LUT_r[vaddr>>12]) vpage&=2047; // jump_dirty uses a hash of the virtual address instead
94d23bb9 339#endif
57871462 340 if(vpage>2048) vpage=2048+(vpage&2047);
94d23bb9 341 return vpage;
342}
343
344// Get address from virtual address
345// This is called from the recompiled JR/JALR instructions
346void *get_addr(u_int vaddr)
347{
348 u_int page=get_page(vaddr);
349 u_int vpage=get_vpage(vaddr);
57871462 350 struct ll_entry *head;
351 //printf("TRACE: count=%d next=%d (get_addr %x,page %d)\n",Count,next_interupt,vaddr,page);
352 head=jump_in[page];
353 while(head!=NULL) {
354 if(head->vaddr==vaddr&&head->reg32==0) {
355 //printf("TRACE: count=%d next=%d (get_addr match %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr);
356 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
357 ht_bin[3]=ht_bin[1];
358 ht_bin[2]=ht_bin[0];
359 ht_bin[1]=(int)head->addr;
360 ht_bin[0]=vaddr;
361 return head->addr;
362 }
363 head=head->next;
364 }
365 head=jump_dirty[vpage];
366 while(head!=NULL) {
367 if(head->vaddr==vaddr&&head->reg32==0) {
368 //printf("TRACE: count=%d next=%d (get_addr match dirty %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr);
369 // Don't restore blocks which are about to expire from the cache
370 if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
371 if(verify_dirty(head->addr)) {
372 //printf("restore candidate: %x (%d) d=%d\n",vaddr,page,invalid_code[vaddr>>12]);
373 invalid_code[vaddr>>12]=0;
374 memory_map[vaddr>>12]|=0x40000000;
375 if(vpage<2048) {
94d23bb9 376#ifndef DISABLE_TLB
57871462 377 if(tlb_LUT_r[vaddr>>12]) {
378 invalid_code[tlb_LUT_r[vaddr>>12]>>12]=0;
379 memory_map[tlb_LUT_r[vaddr>>12]>>12]|=0x40000000;
380 }
94d23bb9 381#endif
57871462 382 restore_candidate[vpage>>3]|=1<<(vpage&7);
383 }
384 else restore_candidate[page>>3]|=1<<(page&7);
385 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
386 if(ht_bin[0]==vaddr) {
387 ht_bin[1]=(int)head->addr; // Replace existing entry
388 }
389 else
390 {
391 ht_bin[3]=ht_bin[1];
392 ht_bin[2]=ht_bin[0];
393 ht_bin[1]=(int)head->addr;
394 ht_bin[0]=vaddr;
395 }
396 return head->addr;
397 }
398 }
399 head=head->next;
400 }
401 //printf("TRACE: count=%d next=%d (get_addr no-match %x)\n",Count,next_interupt,vaddr);
402 int r=new_recompile_block(vaddr);
403 if(r==0) return get_addr(vaddr);
404 // Execute in unmapped page, generate pagefault execption
405 Status|=2;
406 Cause=(vaddr<<31)|0x8;
407 EPC=(vaddr&1)?vaddr-5:vaddr;
408 BadVAddr=(vaddr&~1);
409 Context=(Context&0xFF80000F)|((BadVAddr>>9)&0x007FFFF0);
410 EntryHi=BadVAddr&0xFFFFE000;
411 return get_addr_ht(0x80000000);
412}
413// Look up address in hash table first
414void *get_addr_ht(u_int vaddr)
415{
416 //printf("TRACE: count=%d next=%d (get_addr_ht %x)\n",Count,next_interupt,vaddr);
417 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
418 if(ht_bin[0]==vaddr) return (void *)ht_bin[1];
419 if(ht_bin[2]==vaddr) return (void *)ht_bin[3];
420 return get_addr(vaddr);
421}
422
423void *get_addr_32(u_int vaddr,u_int flags)
424{
7139f3c8 425#ifdef FORCE32
426 return get_addr(vaddr);
560e4a12 427#else
57871462 428 //printf("TRACE: count=%d next=%d (get_addr_32 %x,flags %x)\n",Count,next_interupt,vaddr,flags);
429 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
430 if(ht_bin[0]==vaddr) return (void *)ht_bin[1];
431 if(ht_bin[2]==vaddr) return (void *)ht_bin[3];
94d23bb9 432 u_int page=get_page(vaddr);
433 u_int vpage=get_vpage(vaddr);
57871462 434 struct ll_entry *head;
435 head=jump_in[page];
436 while(head!=NULL) {
437 if(head->vaddr==vaddr&&(head->reg32&flags)==0) {
438 //printf("TRACE: count=%d next=%d (get_addr_32 match %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr);
439 if(head->reg32==0) {
440 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
441 if(ht_bin[0]==-1) {
442 ht_bin[1]=(int)head->addr;
443 ht_bin[0]=vaddr;
444 }else if(ht_bin[2]==-1) {
445 ht_bin[3]=(int)head->addr;
446 ht_bin[2]=vaddr;
447 }
448 //ht_bin[3]=ht_bin[1];
449 //ht_bin[2]=ht_bin[0];
450 //ht_bin[1]=(int)head->addr;
451 //ht_bin[0]=vaddr;
452 }
453 return head->addr;
454 }
455 head=head->next;
456 }
457 head=jump_dirty[vpage];
458 while(head!=NULL) {
459 if(head->vaddr==vaddr&&(head->reg32&flags)==0) {
460 //printf("TRACE: count=%d next=%d (get_addr_32 match dirty %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr);
461 // Don't restore blocks which are about to expire from the cache
462 if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
463 if(verify_dirty(head->addr)) {
464 //printf("restore candidate: %x (%d) d=%d\n",vaddr,page,invalid_code[vaddr>>12]);
465 invalid_code[vaddr>>12]=0;
466 memory_map[vaddr>>12]|=0x40000000;
467 if(vpage<2048) {
94d23bb9 468#ifndef DISABLE_TLB
57871462 469 if(tlb_LUT_r[vaddr>>12]) {
470 invalid_code[tlb_LUT_r[vaddr>>12]>>12]=0;
471 memory_map[tlb_LUT_r[vaddr>>12]>>12]|=0x40000000;
472 }
94d23bb9 473#endif
57871462 474 restore_candidate[vpage>>3]|=1<<(vpage&7);
475 }
476 else restore_candidate[page>>3]|=1<<(page&7);
477 if(head->reg32==0) {
478 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
479 if(ht_bin[0]==-1) {
480 ht_bin[1]=(int)head->addr;
481 ht_bin[0]=vaddr;
482 }else if(ht_bin[2]==-1) {
483 ht_bin[3]=(int)head->addr;
484 ht_bin[2]=vaddr;
485 }
486 //ht_bin[3]=ht_bin[1];
487 //ht_bin[2]=ht_bin[0];
488 //ht_bin[1]=(int)head->addr;
489 //ht_bin[0]=vaddr;
490 }
491 return head->addr;
492 }
493 }
494 head=head->next;
495 }
496 //printf("TRACE: count=%d next=%d (get_addr_32 no-match %x,flags %x)\n",Count,next_interupt,vaddr,flags);
497 int r=new_recompile_block(vaddr);
498 if(r==0) return get_addr(vaddr);
499 // Execute in unmapped page, generate pagefault execption
500 Status|=2;
501 Cause=(vaddr<<31)|0x8;
502 EPC=(vaddr&1)?vaddr-5:vaddr;
503 BadVAddr=(vaddr&~1);
504 Context=(Context&0xFF80000F)|((BadVAddr>>9)&0x007FFFF0);
505 EntryHi=BadVAddr&0xFFFFE000;
506 return get_addr_ht(0x80000000);
560e4a12 507#endif
57871462 508}
509
510void clear_all_regs(signed char regmap[])
511{
512 int hr;
513 for (hr=0;hr<HOST_REGS;hr++) regmap[hr]=-1;
514}
515
516signed char get_reg(signed char regmap[],int r)
517{
518 int hr;
519 for (hr=0;hr<HOST_REGS;hr++) if(hr!=EXCLUDE_REG&&regmap[hr]==r) return hr;
520 return -1;
521}
522
523// Find a register that is available for two consecutive cycles
524signed char get_reg2(signed char regmap1[],signed char regmap2[],int r)
525{
526 int hr;
527 for (hr=0;hr<HOST_REGS;hr++) if(hr!=EXCLUDE_REG&&regmap1[hr]==r&&regmap2[hr]==r) return hr;
528 return -1;
529}
530
531int count_free_regs(signed char regmap[])
532{
533 int count=0;
534 int hr;
535 for(hr=0;hr<HOST_REGS;hr++)
536 {
537 if(hr!=EXCLUDE_REG) {
538 if(regmap[hr]<0) count++;
539 }
540 }
541 return count;
542}
543
544void dirty_reg(struct regstat *cur,signed char reg)
545{
546 int hr;
547 if(!reg) return;
548 for (hr=0;hr<HOST_REGS;hr++) {
549 if((cur->regmap[hr]&63)==reg) {
550 cur->dirty|=1<<hr;
551 }
552 }
553}
554
555// If we dirty the lower half of a 64 bit register which is now being
556// sign-extended, we need to dump the upper half.
557// Note: Do this only after completion of the instruction, because
558// some instructions may need to read the full 64-bit value even if
559// overwriting it (eg SLTI, DSRA32).
560static void flush_dirty_uppers(struct regstat *cur)
561{
562 int hr,reg;
563 for (hr=0;hr<HOST_REGS;hr++) {
564 if((cur->dirty>>hr)&1) {
565 reg=cur->regmap[hr];
566 if(reg>=64)
567 if((cur->is32>>(reg&63))&1) cur->regmap[hr]=-1;
568 }
569 }
570}
571
572void set_const(struct regstat *cur,signed char reg,uint64_t value)
573{
574 int hr;
575 if(!reg) return;
576 for (hr=0;hr<HOST_REGS;hr++) {
577 if(cur->regmap[hr]==reg) {
578 cur->isconst|=1<<hr;
579 cur->constmap[hr]=value;
580 }
581 else if((cur->regmap[hr]^64)==reg) {
582 cur->isconst|=1<<hr;
583 cur->constmap[hr]=value>>32;
584 }
585 }
586}
587
588void clear_const(struct regstat *cur,signed char reg)
589{
590 int hr;
591 if(!reg) return;
592 for (hr=0;hr<HOST_REGS;hr++) {
593 if((cur->regmap[hr]&63)==reg) {
594 cur->isconst&=~(1<<hr);
595 }
596 }
597}
598
599int is_const(struct regstat *cur,signed char reg)
600{
601 int hr;
79c75f1b 602 if(reg<0) return 0;
57871462 603 if(!reg) return 1;
604 for (hr=0;hr<HOST_REGS;hr++) {
605 if((cur->regmap[hr]&63)==reg) {
606 return (cur->isconst>>hr)&1;
607 }
608 }
609 return 0;
610}
611uint64_t get_const(struct regstat *cur,signed char reg)
612{
613 int hr;
614 if(!reg) return 0;
615 for (hr=0;hr<HOST_REGS;hr++) {
616 if(cur->regmap[hr]==reg) {
617 return cur->constmap[hr];
618 }
619 }
620 printf("Unknown constant in r%d\n",reg);
621 exit(1);
622}
623
624// Least soon needed registers
625// Look at the next ten instructions and see which registers
626// will be used. Try not to reallocate these.
627void lsn(u_char hsn[], int i, int *preferred_reg)
628{
629 int j;
630 int b=-1;
631 for(j=0;j<9;j++)
632 {
633 if(i+j>=slen) {
634 j=slen-i-1;
635 break;
636 }
637 if(itype[i+j]==UJUMP||itype[i+j]==RJUMP||(source[i+j]>>16)==0x1000)
638 {
639 // Don't go past an unconditonal jump
640 j++;
641 break;
642 }
643 }
644 for(;j>=0;j--)
645 {
646 if(rs1[i+j]) hsn[rs1[i+j]]=j;
647 if(rs2[i+j]) hsn[rs2[i+j]]=j;
648 if(rt1[i+j]) hsn[rt1[i+j]]=j;
649 if(rt2[i+j]) hsn[rt2[i+j]]=j;
650 if(itype[i+j]==STORE || itype[i+j]==STORELR) {
651 // Stores can allocate zero
652 hsn[rs1[i+j]]=j;
653 hsn[rs2[i+j]]=j;
654 }
655 // On some architectures stores need invc_ptr
656 #if defined(HOST_IMM8)
b9b61529 657 if(itype[i+j]==STORE || itype[i+j]==STORELR || (opcode[i+j]&0x3b)==0x39 || (opcode[i+j]&0x3b)==0x3a) {
57871462 658 hsn[INVCP]=j;
659 }
660 #endif
661 if(i+j>=0&&(itype[i+j]==UJUMP||itype[i+j]==CJUMP||itype[i+j]==SJUMP||itype[i+j]==FJUMP))
662 {
663 hsn[CCREG]=j;
664 b=j;
665 }
666 }
667 if(b>=0)
668 {
669 if(ba[i+b]>=start && ba[i+b]<(start+slen*4))
670 {
671 // Follow first branch
672 int t=(ba[i+b]-start)>>2;
673 j=7-b;if(t+j>=slen) j=slen-t-1;
674 for(;j>=0;j--)
675 {
676 if(rs1[t+j]) if(hsn[rs1[t+j]]>j+b+2) hsn[rs1[t+j]]=j+b+2;
677 if(rs2[t+j]) if(hsn[rs2[t+j]]>j+b+2) hsn[rs2[t+j]]=j+b+2;
678 //if(rt1[t+j]) if(hsn[rt1[t+j]]>j+b+2) hsn[rt1[t+j]]=j+b+2;
679 //if(rt2[t+j]) if(hsn[rt2[t+j]]>j+b+2) hsn[rt2[t+j]]=j+b+2;
680 }
681 }
682 // TODO: preferred register based on backward branch
683 }
684 // Delay slot should preferably not overwrite branch conditions or cycle count
685 if(i>0&&(itype[i-1]==RJUMP||itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP)) {
686 if(rs1[i-1]) if(hsn[rs1[i-1]]>1) hsn[rs1[i-1]]=1;
687 if(rs2[i-1]) if(hsn[rs2[i-1]]>1) hsn[rs2[i-1]]=1;
688 hsn[CCREG]=1;
689 // ...or hash tables
690 hsn[RHASH]=1;
691 hsn[RHTBL]=1;
692 }
693 // Coprocessor load/store needs FTEMP, even if not declared
b9b61529 694 if(itype[i]==C1LS||itype[i]==C2LS) {
57871462 695 hsn[FTEMP]=0;
696 }
697 // Load L/R also uses FTEMP as a temporary register
698 if(itype[i]==LOADLR) {
699 hsn[FTEMP]=0;
700 }
b7918751 701 // Also SWL/SWR/SDL/SDR
702 if(opcode[i]==0x2a||opcode[i]==0x2e||opcode[i]==0x2c||opcode[i]==0x2d) {
57871462 703 hsn[FTEMP]=0;
704 }
705 // Don't remove the TLB registers either
b9b61529 706 if(itype[i]==LOAD || itype[i]==LOADLR || itype[i]==STORE || itype[i]==STORELR || itype[i]==C1LS || itype[i]==C2LS) {
57871462 707 hsn[TLREG]=0;
708 }
709 // Don't remove the miniht registers
710 if(itype[i]==UJUMP||itype[i]==RJUMP)
711 {
712 hsn[RHASH]=0;
713 hsn[RHTBL]=0;
714 }
715}
716
717// We only want to allocate registers if we're going to use them again soon
718int needed_again(int r, int i)
719{
720 int j;
721 int b=-1;
722 int rn=10;
57871462 723
724 if(i>0&&(itype[i-1]==UJUMP||itype[i-1]==RJUMP||(source[i-1]>>16)==0x1000))
725 {
726 if(ba[i-1]<start || ba[i-1]>start+slen*4-4)
727 return 0; // Don't need any registers if exiting the block
728 }
729 for(j=0;j<9;j++)
730 {
731 if(i+j>=slen) {
732 j=slen-i-1;
733 break;
734 }
735 if(itype[i+j]==UJUMP||itype[i+j]==RJUMP||(source[i+j]>>16)==0x1000)
736 {
737 // Don't go past an unconditonal jump
738 j++;
739 break;
740 }
1e973cb0 741 if(itype[i+j]==SYSCALL||itype[i+j]==HLECALL||itype[i+j]==INTCALL||((source[i+j]&0xfc00003f)==0x0d))
57871462 742 {
743 break;
744 }
745 }
746 for(;j>=1;j--)
747 {
748 if(rs1[i+j]==r) rn=j;
749 if(rs2[i+j]==r) rn=j;
750 if((unneeded_reg[i+j]>>r)&1) rn=10;
751 if(i+j>=0&&(itype[i+j]==UJUMP||itype[i+j]==CJUMP||itype[i+j]==SJUMP||itype[i+j]==FJUMP))
752 {
753 b=j;
754 }
755 }
756 /*
757 if(b>=0)
758 {
759 if(ba[i+b]>=start && ba[i+b]<(start+slen*4))
760 {
761 // Follow first branch
762 int o=rn;
763 int t=(ba[i+b]-start)>>2;
764 j=7-b;if(t+j>=slen) j=slen-t-1;
765 for(;j>=0;j--)
766 {
767 if(!((unneeded_reg[t+j]>>r)&1)) {
768 if(rs1[t+j]==r) if(rn>j+b+2) rn=j+b+2;
769 if(rs2[t+j]==r) if(rn>j+b+2) rn=j+b+2;
770 }
771 else rn=o;
772 }
773 }
774 }*/
b7217e13 775 if(rn<10) return 1;
57871462 776 return 0;
777}
778
779// Try to match register allocations at the end of a loop with those
780// at the beginning
781int loop_reg(int i, int r, int hr)
782{
783 int j,k;
784 for(j=0;j<9;j++)
785 {
786 if(i+j>=slen) {
787 j=slen-i-1;
788 break;
789 }
790 if(itype[i+j]==UJUMP||itype[i+j]==RJUMP||(source[i+j]>>16)==0x1000)
791 {
792 // Don't go past an unconditonal jump
793 j++;
794 break;
795 }
796 }
797 k=0;
798 if(i>0){
799 if(itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP)
800 k--;
801 }
802 for(;k<j;k++)
803 {
804 if(r<64&&((unneeded_reg[i+k]>>r)&1)) return hr;
805 if(r>64&&((unneeded_reg_upper[i+k]>>r)&1)) return hr;
806 if(i+k>=0&&(itype[i+k]==UJUMP||itype[i+k]==CJUMP||itype[i+k]==SJUMP||itype[i+k]==FJUMP))
807 {
808 if(ba[i+k]>=start && ba[i+k]<(start+i*4))
809 {
810 int t=(ba[i+k]-start)>>2;
811 int reg=get_reg(regs[t].regmap_entry,r);
812 if(reg>=0) return reg;
813 //reg=get_reg(regs[t+1].regmap_entry,r);
814 //if(reg>=0) return reg;
815 }
816 }
817 }
818 return hr;
819}
820
821
822// Allocate every register, preserving source/target regs
823void alloc_all(struct regstat *cur,int i)
824{
825 int hr;
826
827 for(hr=0;hr<HOST_REGS;hr++) {
828 if(hr!=EXCLUDE_REG) {
829 if(((cur->regmap[hr]&63)!=rs1[i])&&((cur->regmap[hr]&63)!=rs2[i])&&
830 ((cur->regmap[hr]&63)!=rt1[i])&&((cur->regmap[hr]&63)!=rt2[i]))
831 {
832 cur->regmap[hr]=-1;
833 cur->dirty&=~(1<<hr);
834 }
835 // Don't need zeros
836 if((cur->regmap[hr]&63)==0)
837 {
838 cur->regmap[hr]=-1;
839 cur->dirty&=~(1<<hr);
840 }
841 }
842 }
843}
844
845
846void div64(int64_t dividend,int64_t divisor)
847{
848 lo=dividend/divisor;
849 hi=dividend%divisor;
850 //printf("TRACE: ddiv %8x%8x %8x%8x\n" ,(int)reg[HIREG],(int)(reg[HIREG]>>32)
851 // ,(int)reg[LOREG],(int)(reg[LOREG]>>32));
852}
853void divu64(uint64_t dividend,uint64_t divisor)
854{
855 lo=dividend/divisor;
856 hi=dividend%divisor;
857 //printf("TRACE: ddivu %8x%8x %8x%8x\n",(int)reg[HIREG],(int)(reg[HIREG]>>32)
858 // ,(int)reg[LOREG],(int)(reg[LOREG]>>32));
859}
860
861void mult64(uint64_t m1,uint64_t m2)
862{
863 unsigned long long int op1, op2, op3, op4;
864 unsigned long long int result1, result2, result3, result4;
865 unsigned long long int temp1, temp2, temp3, temp4;
866 int sign = 0;
867
868 if (m1 < 0)
869 {
870 op2 = -m1;
871 sign = 1 - sign;
872 }
873 else op2 = m1;
874 if (m2 < 0)
875 {
876 op4 = -m2;
877 sign = 1 - sign;
878 }
879 else op4 = m2;
880
881 op1 = op2 & 0xFFFFFFFF;
882 op2 = (op2 >> 32) & 0xFFFFFFFF;
883 op3 = op4 & 0xFFFFFFFF;
884 op4 = (op4 >> 32) & 0xFFFFFFFF;
885
886 temp1 = op1 * op3;
887 temp2 = (temp1 >> 32) + op1 * op4;
888 temp3 = op2 * op3;
889 temp4 = (temp3 >> 32) + op2 * op4;
890
891 result1 = temp1 & 0xFFFFFFFF;
892 result2 = temp2 + (temp3 & 0xFFFFFFFF);
893 result3 = (result2 >> 32) + temp4;
894 result4 = (result3 >> 32);
895
896 lo = result1 | (result2 << 32);
897 hi = (result3 & 0xFFFFFFFF) | (result4 << 32);
898 if (sign)
899 {
900 hi = ~hi;
901 if (!lo) hi++;
902 else lo = ~lo + 1;
903 }
904}
905
906void multu64(uint64_t m1,uint64_t m2)
907{
908 unsigned long long int op1, op2, op3, op4;
909 unsigned long long int result1, result2, result3, result4;
910 unsigned long long int temp1, temp2, temp3, temp4;
911
912 op1 = m1 & 0xFFFFFFFF;
913 op2 = (m1 >> 32) & 0xFFFFFFFF;
914 op3 = m2 & 0xFFFFFFFF;
915 op4 = (m2 >> 32) & 0xFFFFFFFF;
916
917 temp1 = op1 * op3;
918 temp2 = (temp1 >> 32) + op1 * op4;
919 temp3 = op2 * op3;
920 temp4 = (temp3 >> 32) + op2 * op4;
921
922 result1 = temp1 & 0xFFFFFFFF;
923 result2 = temp2 + (temp3 & 0xFFFFFFFF);
924 result3 = (result2 >> 32) + temp4;
925 result4 = (result3 >> 32);
926
927 lo = result1 | (result2 << 32);
928 hi = (result3 & 0xFFFFFFFF) | (result4 << 32);
929
930 //printf("TRACE: dmultu %8x%8x %8x%8x\n",(int)reg[HIREG],(int)(reg[HIREG]>>32)
931 // ,(int)reg[LOREG],(int)(reg[LOREG]>>32));
932}
933
934uint64_t ldl_merge(uint64_t original,uint64_t loaded,u_int bits)
935{
936 if(bits) {
937 original<<=64-bits;
938 original>>=64-bits;
939 loaded<<=bits;
940 original|=loaded;
941 }
942 else original=loaded;
943 return original;
944}
945uint64_t ldr_merge(uint64_t original,uint64_t loaded,u_int bits)
946{
947 if(bits^56) {
948 original>>=64-(bits^56);
949 original<<=64-(bits^56);
950 loaded>>=bits^56;
951 original|=loaded;
952 }
953 else original=loaded;
954 return original;
955}
956
957#ifdef __i386__
958#include "assem_x86.c"
959#endif
960#ifdef __x86_64__
961#include "assem_x64.c"
962#endif
963#ifdef __arm__
964#include "assem_arm.c"
965#endif
966
967// Add virtual address mapping to linked list
968void ll_add(struct ll_entry **head,int vaddr,void *addr)
969{
970 struct ll_entry *new_entry;
971 new_entry=malloc(sizeof(struct ll_entry));
972 assert(new_entry!=NULL);
973 new_entry->vaddr=vaddr;
974 new_entry->reg32=0;
975 new_entry->addr=addr;
976 new_entry->next=*head;
977 *head=new_entry;
978}
979
980// Add virtual address mapping for 32-bit compiled block
981void ll_add_32(struct ll_entry **head,int vaddr,u_int reg32,void *addr)
982{
7139f3c8 983 ll_add(head,vaddr,addr);
984#ifndef FORCE32
985 (*head)->reg32=reg32;
986#endif
57871462 987}
988
989// Check if an address is already compiled
990// but don't return addresses which are about to expire from the cache
991void *check_addr(u_int vaddr)
992{
993 u_int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
994 if(ht_bin[0]==vaddr) {
995 if(((ht_bin[1]-MAX_OUTPUT_BLOCK_SIZE-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
996 if(isclean(ht_bin[1])) return (void *)ht_bin[1];
997 }
998 if(ht_bin[2]==vaddr) {
999 if(((ht_bin[3]-MAX_OUTPUT_BLOCK_SIZE-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
1000 if(isclean(ht_bin[3])) return (void *)ht_bin[3];
1001 }
94d23bb9 1002 u_int page=get_page(vaddr);
57871462 1003 struct ll_entry *head;
1004 head=jump_in[page];
1005 while(head!=NULL) {
1006 if(head->vaddr==vaddr&&head->reg32==0) {
1007 if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2))) {
1008 // Update existing entry with current address
1009 if(ht_bin[0]==vaddr) {
1010 ht_bin[1]=(int)head->addr;
1011 return head->addr;
1012 }
1013 if(ht_bin[2]==vaddr) {
1014 ht_bin[3]=(int)head->addr;
1015 return head->addr;
1016 }
1017 // Insert into hash table with low priority.
1018 // Don't evict existing entries, as they are probably
1019 // addresses that are being accessed frequently.
1020 if(ht_bin[0]==-1) {
1021 ht_bin[1]=(int)head->addr;
1022 ht_bin[0]=vaddr;
1023 }else if(ht_bin[2]==-1) {
1024 ht_bin[3]=(int)head->addr;
1025 ht_bin[2]=vaddr;
1026 }
1027 return head->addr;
1028 }
1029 }
1030 head=head->next;
1031 }
1032 return 0;
1033}
1034
1035void remove_hash(int vaddr)
1036{
1037 //printf("remove hash: %x\n",vaddr);
1038 int *ht_bin=hash_table[(((vaddr)>>16)^vaddr)&0xFFFF];
1039 if(ht_bin[2]==vaddr) {
1040 ht_bin[2]=ht_bin[3]=-1;
1041 }
1042 if(ht_bin[0]==vaddr) {
1043 ht_bin[0]=ht_bin[2];
1044 ht_bin[1]=ht_bin[3];
1045 ht_bin[2]=ht_bin[3]=-1;
1046 }
1047}
1048
1049void ll_remove_matching_addrs(struct ll_entry **head,int addr,int shift)
1050{
1051 struct ll_entry *next;
1052 while(*head) {
1053 if(((u_int)((*head)->addr)>>shift)==(addr>>shift) ||
1054 ((u_int)((*head)->addr-MAX_OUTPUT_BLOCK_SIZE)>>shift)==(addr>>shift))
1055 {
1056 inv_debug("EXP: Remove pointer to %x (%x)\n",(int)(*head)->addr,(*head)->vaddr);
1057 remove_hash((*head)->vaddr);
1058 next=(*head)->next;
1059 free(*head);
1060 *head=next;
1061 }
1062 else
1063 {
1064 head=&((*head)->next);
1065 }
1066 }
1067}
1068
1069// Remove all entries from linked list
1070void ll_clear(struct ll_entry **head)
1071{
1072 struct ll_entry *cur;
1073 struct ll_entry *next;
1074 if(cur=*head) {
1075 *head=0;
1076 while(cur) {
1077 next=cur->next;
1078 free(cur);
1079 cur=next;
1080 }
1081 }
1082}
1083
1084// Dereference the pointers and remove if it matches
1085void ll_kill_pointers(struct ll_entry *head,int addr,int shift)
1086{
1087 while(head) {
1088 int ptr=get_pointer(head->addr);
1089 inv_debug("EXP: Lookup pointer to %x at %x (%x)\n",(int)ptr,(int)head->addr,head->vaddr);
1090 if(((ptr>>shift)==(addr>>shift)) ||
1091 (((ptr-MAX_OUTPUT_BLOCK_SIZE)>>shift)==(addr>>shift)))
1092 {
5088bb70 1093 inv_debug("EXP: Kill pointer at %x (%x)\n",(int)head->addr,head->vaddr);
f76eeef9 1094 u_int host_addr=(u_int)kill_pointer(head->addr);
dd3a91a1 1095 #ifdef __arm__
1096 needs_clear_cache[(host_addr-(u_int)BASE_ADDR)>>17]|=1<<(((host_addr-(u_int)BASE_ADDR)>>12)&31);
1097 #endif
57871462 1098 }
1099 head=head->next;
1100 }
1101}
1102
1103// This is called when we write to a compiled block (see do_invstub)
f76eeef9 1104void invalidate_page(u_int page)
57871462 1105{
57871462 1106 struct ll_entry *head;
1107 struct ll_entry *next;
1108 head=jump_in[page];
1109 jump_in[page]=0;
1110 while(head!=NULL) {
1111 inv_debug("INVALIDATE: %x\n",head->vaddr);
1112 remove_hash(head->vaddr);
1113 next=head->next;
1114 free(head);
1115 head=next;
1116 }
1117 head=jump_out[page];
1118 jump_out[page]=0;
1119 while(head!=NULL) {
1120 inv_debug("INVALIDATE: kill pointer to %x (%x)\n",head->vaddr,(int)head->addr);
f76eeef9 1121 u_int host_addr=(u_int)kill_pointer(head->addr);
dd3a91a1 1122 #ifdef __arm__
1123 needs_clear_cache[(host_addr-(u_int)BASE_ADDR)>>17]|=1<<(((host_addr-(u_int)BASE_ADDR)>>12)&31);
1124 #endif
57871462 1125 next=head->next;
1126 free(head);
1127 head=next;
1128 }
57871462 1129}
1130void invalidate_block(u_int block)
1131{
94d23bb9 1132 u_int page=get_page(block<<12);
1133 u_int vpage=get_vpage(block<<12);
57871462 1134 inv_debug("INVALIDATE: %x (%d)\n",block<<12,page);
1135 //inv_debug("invalid_code[block]=%d\n",invalid_code[block]);
1136 u_int first,last;
1137 first=last=page;
1138 struct ll_entry *head;
1139 head=jump_dirty[vpage];
1140 //printf("page=%d vpage=%d\n",page,vpage);
1141 while(head!=NULL) {
1142 u_int start,end;
1143 if(vpage>2047||(head->vaddr>>12)==block) { // Ignore vaddr hash collision
1144 get_bounds((int)head->addr,&start,&end);
1145 //printf("start: %x end: %x\n",start,end);
4cb76aa4 1146 if(page<2048&&start>=0x80000000&&end<0x80000000+RAM_SIZE) {
57871462 1147 if(((start-(u_int)rdram)>>12)<=page&&((end-1-(u_int)rdram)>>12)>=page) {
1148 if((((start-(u_int)rdram)>>12)&2047)<first) first=((start-(u_int)rdram)>>12)&2047;
1149 if((((end-1-(u_int)rdram)>>12)&2047)>last) last=((end-1-(u_int)rdram)>>12)&2047;
1150 }
1151 }
90ae6d4e 1152#ifndef DISABLE_TLB
57871462 1153 if(page<2048&&(signed int)start>=(signed int)0xC0000000&&(signed int)end>=(signed int)0xC0000000) {
1154 if(((start+memory_map[start>>12]-(u_int)rdram)>>12)<=page&&((end-1+memory_map[(end-1)>>12]-(u_int)rdram)>>12)>=page) {
1155 if((((start+memory_map[start>>12]-(u_int)rdram)>>12)&2047)<first) first=((start+memory_map[start>>12]-(u_int)rdram)>>12)&2047;
1156 if((((end-1+memory_map[(end-1)>>12]-(u_int)rdram)>>12)&2047)>last) last=((end-1+memory_map[(end-1)>>12]-(u_int)rdram)>>12)&2047;
1157 }
1158 }
90ae6d4e 1159#endif
57871462 1160 }
1161 head=head->next;
1162 }
1163 //printf("first=%d last=%d\n",first,last);
f76eeef9 1164 invalidate_page(page);
57871462 1165 assert(first+5>page); // NB: this assumes MAXBLOCK<=4096 (4 pages)
1166 assert(last<page+5);
1167 // Invalidate the adjacent pages if a block crosses a 4K boundary
1168 while(first<page) {
1169 invalidate_page(first);
1170 first++;
1171 }
1172 for(first=page+1;first<last;first++) {
1173 invalidate_page(first);
1174 }
dd3a91a1 1175 #ifdef __arm__
1176 do_clear_cache();
1177 #endif
57871462 1178
1179 // Don't trap writes
1180 invalid_code[block]=1;
b12c9fb8 1181#ifdef PCSX
1182 invalid_code[((u_int)0x80000000>>12)|page]=1;
1183#endif
94d23bb9 1184#ifndef DISABLE_TLB
57871462 1185 // If there is a valid TLB entry for this page, remove write protect
1186 if(tlb_LUT_w[block]) {
1187 assert(tlb_LUT_r[block]==tlb_LUT_w[block]);
1188 // CHECK: Is this right?
1189 memory_map[block]=((tlb_LUT_w[block]&0xFFFFF000)-(block<<12)+(unsigned int)rdram-0x80000000)>>2;
1190 u_int real_block=tlb_LUT_w[block]>>12;
1191 invalid_code[real_block]=1;
1192 if(real_block>=0x80000&&real_block<0x80800) memory_map[real_block]=((u_int)rdram-0x80000000)>>2;
1193 }
1194 else if(block>=0x80000&&block<0x80800) memory_map[block]=((u_int)rdram-0x80000000)>>2;
94d23bb9 1195#endif
f76eeef9 1196
57871462 1197 #ifdef USE_MINI_HT
1198 memset(mini_ht,-1,sizeof(mini_ht));
1199 #endif
1200}
1201void invalidate_addr(u_int addr)
1202{
1203 invalidate_block(addr>>12);
1204}
dd3a91a1 1205// This is called when loading a save state.
1206// Anything could have changed, so invalidate everything.
57871462 1207void invalidate_all_pages()
1208{
1209 u_int page,n;
1210 for(page=0;page<4096;page++)
1211 invalidate_page(page);
1212 for(page=0;page<1048576;page++)
1213 if(!invalid_code[page]) {
1214 restore_candidate[(page&2047)>>3]|=1<<(page&7);
1215 restore_candidate[((page&2047)>>3)+256]|=1<<(page&7);
1216 }
1217 #ifdef __arm__
1218 __clear_cache((void *)BASE_ADDR,(void *)BASE_ADDR+(1<<TARGET_SIZE_2));
1219 #endif
1220 #ifdef USE_MINI_HT
1221 memset(mini_ht,-1,sizeof(mini_ht));
1222 #endif
94d23bb9 1223 #ifndef DISABLE_TLB
57871462 1224 // TLB
1225 for(page=0;page<0x100000;page++) {
1226 if(tlb_LUT_r[page]) {
1227 memory_map[page]=((tlb_LUT_r[page]&0xFFFFF000)-(page<<12)+(unsigned int)rdram-0x80000000)>>2;
1228 if(!tlb_LUT_w[page]||!invalid_code[page])
1229 memory_map[page]|=0x40000000; // Write protect
1230 }
1231 else memory_map[page]=-1;
1232 if(page==0x80000) page=0xC0000;
1233 }
1234 tlb_hacks();
94d23bb9 1235 #endif
57871462 1236}
1237
1238// Add an entry to jump_out after making a link
1239void add_link(u_int vaddr,void *src)
1240{
94d23bb9 1241 u_int page=get_page(vaddr);
57871462 1242 inv_debug("add_link: %x -> %x (%d)\n",(int)src,vaddr,page);
1243 ll_add(jump_out+page,vaddr,src);
1244 //int ptr=get_pointer(src);
1245 //inv_debug("add_link: Pointer is to %x\n",(int)ptr);
1246}
1247
1248// If a code block was found to be unmodified (bit was set in
1249// restore_candidate) and it remains unmodified (bit is clear
1250// in invalid_code) then move the entries for that 4K page from
1251// the dirty list to the clean list.
1252void clean_blocks(u_int page)
1253{
1254 struct ll_entry *head;
1255 inv_debug("INV: clean_blocks page=%d\n",page);
1256 head=jump_dirty[page];
1257 while(head!=NULL) {
1258 if(!invalid_code[head->vaddr>>12]) {
1259 // Don't restore blocks which are about to expire from the cache
1260 if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2))) {
1261 u_int start,end;
1262 if(verify_dirty((int)head->addr)) {
1263 //printf("Possibly Restore %x (%x)\n",head->vaddr, (int)head->addr);
1264 u_int i;
1265 u_int inv=0;
1266 get_bounds((int)head->addr,&start,&end);
4cb76aa4 1267 if(start-(u_int)rdram<RAM_SIZE) {
57871462 1268 for(i=(start-(u_int)rdram+0x80000000)>>12;i<=(end-1-(u_int)rdram+0x80000000)>>12;i++) {
1269 inv|=invalid_code[i];
1270 }
1271 }
1272 if((signed int)head->vaddr>=(signed int)0xC0000000) {
1273 u_int addr = (head->vaddr+(memory_map[head->vaddr>>12]<<2));
1274 //printf("addr=%x start=%x end=%x\n",addr,start,end);
1275 if(addr<start||addr>=end) inv=1;
1276 }
4cb76aa4 1277 else if((signed int)head->vaddr>=(signed int)0x80000000+RAM_SIZE) {
57871462 1278 inv=1;
1279 }
1280 if(!inv) {
1281 void * clean_addr=(void *)get_clean_addr((int)head->addr);
1282 if((((u_int)clean_addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2))) {
1283 u_int ppage=page;
94d23bb9 1284#ifndef DISABLE_TLB
57871462 1285 if(page<2048&&tlb_LUT_r[head->vaddr>>12]) ppage=(tlb_LUT_r[head->vaddr>>12]^0x80000000)>>12;
94d23bb9 1286#endif
57871462 1287 inv_debug("INV: Restored %x (%x/%x)\n",head->vaddr, (int)head->addr, (int)clean_addr);
1288 //printf("page=%x, addr=%x\n",page,head->vaddr);
1289 //assert(head->vaddr>>12==(page|0x80000));
1290 ll_add_32(jump_in+ppage,head->vaddr,head->reg32,clean_addr);
1291 int *ht_bin=hash_table[((head->vaddr>>16)^head->vaddr)&0xFFFF];
1292 if(!head->reg32) {
1293 if(ht_bin[0]==head->vaddr) {
1294 ht_bin[1]=(int)clean_addr; // Replace existing entry
1295 }
1296 if(ht_bin[2]==head->vaddr) {
1297 ht_bin[3]=(int)clean_addr; // Replace existing entry
1298 }
1299 }
1300 }
1301 }
1302 }
1303 }
1304 }
1305 head=head->next;
1306 }
1307}
1308
1309
1310void mov_alloc(struct regstat *current,int i)
1311{
1312 // Note: Don't need to actually alloc the source registers
1313 if((~current->is32>>rs1[i])&1) {
1314 //alloc_reg64(current,i,rs1[i]);
1315 alloc_reg64(current,i,rt1[i]);
1316 current->is32&=~(1LL<<rt1[i]);
1317 } else {
1318 //alloc_reg(current,i,rs1[i]);
1319 alloc_reg(current,i,rt1[i]);
1320 current->is32|=(1LL<<rt1[i]);
1321 }
1322 clear_const(current,rs1[i]);
1323 clear_const(current,rt1[i]);
1324 dirty_reg(current,rt1[i]);
1325}
1326
1327void shiftimm_alloc(struct regstat *current,int i)
1328{
1329 clear_const(current,rs1[i]);
1330 clear_const(current,rt1[i]);
1331 if(opcode2[i]<=0x3) // SLL/SRL/SRA
1332 {
1333 if(rt1[i]) {
1334 if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1335 else lt1[i]=rs1[i];
1336 alloc_reg(current,i,rt1[i]);
1337 current->is32|=1LL<<rt1[i];
1338 dirty_reg(current,rt1[i]);
1339 }
1340 }
1341 if(opcode2[i]>=0x38&&opcode2[i]<=0x3b) // DSLL/DSRL/DSRA
1342 {
1343 if(rt1[i]) {
1344 if(rs1[i]) alloc_reg64(current,i,rs1[i]);
1345 alloc_reg64(current,i,rt1[i]);
1346 current->is32&=~(1LL<<rt1[i]);
1347 dirty_reg(current,rt1[i]);
1348 }
1349 }
1350 if(opcode2[i]==0x3c) // DSLL32
1351 {
1352 if(rt1[i]) {
1353 if(rs1[i]) alloc_reg(current,i,rs1[i]);
1354 alloc_reg64(current,i,rt1[i]);
1355 current->is32&=~(1LL<<rt1[i]);
1356 dirty_reg(current,rt1[i]);
1357 }
1358 }
1359 if(opcode2[i]==0x3e) // DSRL32
1360 {
1361 if(rt1[i]) {
1362 alloc_reg64(current,i,rs1[i]);
1363 if(imm[i]==32) {
1364 alloc_reg64(current,i,rt1[i]);
1365 current->is32&=~(1LL<<rt1[i]);
1366 } else {
1367 alloc_reg(current,i,rt1[i]);
1368 current->is32|=1LL<<rt1[i];
1369 }
1370 dirty_reg(current,rt1[i]);
1371 }
1372 }
1373 if(opcode2[i]==0x3f) // DSRA32
1374 {
1375 if(rt1[i]) {
1376 alloc_reg64(current,i,rs1[i]);
1377 alloc_reg(current,i,rt1[i]);
1378 current->is32|=1LL<<rt1[i];
1379 dirty_reg(current,rt1[i]);
1380 }
1381 }
1382}
1383
1384void shift_alloc(struct regstat *current,int i)
1385{
1386 if(rt1[i]) {
1387 if(opcode2[i]<=0x07) // SLLV/SRLV/SRAV
1388 {
1389 if(rs1[i]) alloc_reg(current,i,rs1[i]);
1390 if(rs2[i]) alloc_reg(current,i,rs2[i]);
1391 alloc_reg(current,i,rt1[i]);
e1190b87 1392 if(rt1[i]==rs2[i]) {
1393 alloc_reg_temp(current,i,-1);
1394 minimum_free_regs[i]=1;
1395 }
57871462 1396 current->is32|=1LL<<rt1[i];
1397 } else { // DSLLV/DSRLV/DSRAV
1398 if(rs1[i]) alloc_reg64(current,i,rs1[i]);
1399 if(rs2[i]) alloc_reg(current,i,rs2[i]);
1400 alloc_reg64(current,i,rt1[i]);
1401 current->is32&=~(1LL<<rt1[i]);
1402 if(opcode2[i]==0x16||opcode2[i]==0x17) // DSRLV and DSRAV need a temporary register
e1190b87 1403 {
57871462 1404 alloc_reg_temp(current,i,-1);
e1190b87 1405 minimum_free_regs[i]=1;
1406 }
57871462 1407 }
1408 clear_const(current,rs1[i]);
1409 clear_const(current,rs2[i]);
1410 clear_const(current,rt1[i]);
1411 dirty_reg(current,rt1[i]);
1412 }
1413}
1414
1415void alu_alloc(struct regstat *current,int i)
1416{
1417 if(opcode2[i]>=0x20&&opcode2[i]<=0x23) { // ADD/ADDU/SUB/SUBU
1418 if(rt1[i]) {
1419 if(rs1[i]&&rs2[i]) {
1420 alloc_reg(current,i,rs1[i]);
1421 alloc_reg(current,i,rs2[i]);
1422 }
1423 else {
1424 if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1425 if(rs2[i]&&needed_again(rs2[i],i)) alloc_reg(current,i,rs2[i]);
1426 }
1427 alloc_reg(current,i,rt1[i]);
1428 }
1429 current->is32|=1LL<<rt1[i];
1430 }
1431 if(opcode2[i]==0x2a||opcode2[i]==0x2b) { // SLT/SLTU
1432 if(rt1[i]) {
1433 if(!((current->is32>>rs1[i])&(current->is32>>rs2[i])&1))
1434 {
1435 alloc_reg64(current,i,rs1[i]);
1436 alloc_reg64(current,i,rs2[i]);
1437 alloc_reg(current,i,rt1[i]);
1438 } else {
1439 alloc_reg(current,i,rs1[i]);
1440 alloc_reg(current,i,rs2[i]);
1441 alloc_reg(current,i,rt1[i]);
1442 }
1443 }
1444 current->is32|=1LL<<rt1[i];
1445 }
1446 if(opcode2[i]>=0x24&&opcode2[i]<=0x27) { // AND/OR/XOR/NOR
1447 if(rt1[i]) {
1448 if(rs1[i]&&rs2[i]) {
1449 alloc_reg(current,i,rs1[i]);
1450 alloc_reg(current,i,rs2[i]);
1451 }
1452 else
1453 {
1454 if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1455 if(rs2[i]&&needed_again(rs2[i],i)) alloc_reg(current,i,rs2[i]);
1456 }
1457 alloc_reg(current,i,rt1[i]);
1458 if(!((current->is32>>rs1[i])&(current->is32>>rs2[i])&1))
1459 {
1460 if(!((current->uu>>rt1[i])&1)) {
1461 alloc_reg64(current,i,rt1[i]);
1462 }
1463 if(get_reg(current->regmap,rt1[i]|64)>=0) {
1464 if(rs1[i]&&rs2[i]) {
1465 alloc_reg64(current,i,rs1[i]);
1466 alloc_reg64(current,i,rs2[i]);
1467 }
1468 else
1469 {
1470 // Is is really worth it to keep 64-bit values in registers?
1471 #ifdef NATIVE_64BIT
1472 if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg64(current,i,rs1[i]);
1473 if(rs2[i]&&needed_again(rs2[i],i)) alloc_reg64(current,i,rs2[i]);
1474 #endif
1475 }
1476 }
1477 current->is32&=~(1LL<<rt1[i]);
1478 } else {
1479 current->is32|=1LL<<rt1[i];
1480 }
1481 }
1482 }
1483 if(opcode2[i]>=0x2c&&opcode2[i]<=0x2f) { // DADD/DADDU/DSUB/DSUBU
1484 if(rt1[i]) {
1485 if(rs1[i]&&rs2[i]) {
1486 if(!((current->uu>>rt1[i])&1)||get_reg(current->regmap,rt1[i]|64)>=0) {
1487 alloc_reg64(current,i,rs1[i]);
1488 alloc_reg64(current,i,rs2[i]);
1489 alloc_reg64(current,i,rt1[i]);
1490 } else {
1491 alloc_reg(current,i,rs1[i]);
1492 alloc_reg(current,i,rs2[i]);
1493 alloc_reg(current,i,rt1[i]);
1494 }
1495 }
1496 else {
1497 alloc_reg(current,i,rt1[i]);
1498 if(!((current->uu>>rt1[i])&1)||get_reg(current->regmap,rt1[i]|64)>=0) {
1499 // DADD used as move, or zeroing
1500 // If we have a 64-bit source, then make the target 64 bits too
1501 if(rs1[i]&&!((current->is32>>rs1[i])&1)) {
1502 if(get_reg(current->regmap,rs1[i])>=0) alloc_reg64(current,i,rs1[i]);
1503 alloc_reg64(current,i,rt1[i]);
1504 } else if(rs2[i]&&!((current->is32>>rs2[i])&1)) {
1505 if(get_reg(current->regmap,rs2[i])>=0) alloc_reg64(current,i,rs2[i]);
1506 alloc_reg64(current,i,rt1[i]);
1507 }
1508 if(opcode2[i]>=0x2e&&rs2[i]) {
1509 // DSUB used as negation - 64-bit result
1510 // If we have a 32-bit register, extend it to 64 bits
1511 if(get_reg(current->regmap,rs2[i])>=0) alloc_reg64(current,i,rs2[i]);
1512 alloc_reg64(current,i,rt1[i]);
1513 }
1514 }
1515 }
1516 if(rs1[i]&&rs2[i]) {
1517 current->is32&=~(1LL<<rt1[i]);
1518 } else if(rs1[i]) {
1519 current->is32&=~(1LL<<rt1[i]);
1520 if((current->is32>>rs1[i])&1)
1521 current->is32|=1LL<<rt1[i];
1522 } else if(rs2[i]) {
1523 current->is32&=~(1LL<<rt1[i]);
1524 if((current->is32>>rs2[i])&1)
1525 current->is32|=1LL<<rt1[i];
1526 } else {
1527 current->is32|=1LL<<rt1[i];
1528 }
1529 }
1530 }
1531 clear_const(current,rs1[i]);
1532 clear_const(current,rs2[i]);
1533 clear_const(current,rt1[i]);
1534 dirty_reg(current,rt1[i]);
1535}
1536
1537void imm16_alloc(struct regstat *current,int i)
1538{
1539 if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1540 else lt1[i]=rs1[i];
1541 if(rt1[i]) alloc_reg(current,i,rt1[i]);
1542 if(opcode[i]==0x18||opcode[i]==0x19) { // DADDI/DADDIU
1543 current->is32&=~(1LL<<rt1[i]);
1544 if(!((current->uu>>rt1[i])&1)||get_reg(current->regmap,rt1[i]|64)>=0) {
1545 // TODO: Could preserve the 32-bit flag if the immediate is zero
1546 alloc_reg64(current,i,rt1[i]);
1547 alloc_reg64(current,i,rs1[i]);
1548 }
1549 clear_const(current,rs1[i]);
1550 clear_const(current,rt1[i]);
1551 }
1552 else if(opcode[i]==0x0a||opcode[i]==0x0b) { // SLTI/SLTIU
1553 if((~current->is32>>rs1[i])&1) alloc_reg64(current,i,rs1[i]);
1554 current->is32|=1LL<<rt1[i];
1555 clear_const(current,rs1[i]);
1556 clear_const(current,rt1[i]);
1557 }
1558 else if(opcode[i]>=0x0c&&opcode[i]<=0x0e) { // ANDI/ORI/XORI
1559 if(((~current->is32>>rs1[i])&1)&&opcode[i]>0x0c) {
1560 if(rs1[i]!=rt1[i]) {
1561 if(needed_again(rs1[i],i)) alloc_reg64(current,i,rs1[i]);
1562 alloc_reg64(current,i,rt1[i]);
1563 current->is32&=~(1LL<<rt1[i]);
1564 }
1565 }
1566 else current->is32|=1LL<<rt1[i]; // ANDI clears upper bits
1567 if(is_const(current,rs1[i])) {
1568 int v=get_const(current,rs1[i]);
1569 if(opcode[i]==0x0c) set_const(current,rt1[i],v&imm[i]);
1570 if(opcode[i]==0x0d) set_const(current,rt1[i],v|imm[i]);
1571 if(opcode[i]==0x0e) set_const(current,rt1[i],v^imm[i]);
1572 }
1573 else clear_const(current,rt1[i]);
1574 }
1575 else if(opcode[i]==0x08||opcode[i]==0x09) { // ADDI/ADDIU
1576 if(is_const(current,rs1[i])) {
1577 int v=get_const(current,rs1[i]);
1578 set_const(current,rt1[i],v+imm[i]);
1579 }
1580 else clear_const(current,rt1[i]);
1581 current->is32|=1LL<<rt1[i];
1582 }
1583 else {
1584 set_const(current,rt1[i],((long long)((short)imm[i]))<<16); // LUI
1585 current->is32|=1LL<<rt1[i];
1586 }
1587 dirty_reg(current,rt1[i]);
1588}
1589
1590void load_alloc(struct regstat *current,int i)
1591{
1592 clear_const(current,rt1[i]);
1593 //if(rs1[i]!=rt1[i]&&needed_again(rs1[i],i)) clear_const(current,rs1[i]); // Does this help or hurt?
1594 if(!rs1[i]) current->u&=~1LL; // Allow allocating r0 if it's the source register
1595 if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
373d1d07 1596 if(rt1[i]&&!((current->u>>rt1[i])&1)) {
57871462 1597 alloc_reg(current,i,rt1[i]);
373d1d07 1598 assert(get_reg(current->regmap,rt1[i])>=0);
57871462 1599 if(opcode[i]==0x27||opcode[i]==0x37) // LWU/LD
1600 {
1601 current->is32&=~(1LL<<rt1[i]);
1602 alloc_reg64(current,i,rt1[i]);
1603 }
1604 else if(opcode[i]==0x1A||opcode[i]==0x1B) // LDL/LDR
1605 {
1606 current->is32&=~(1LL<<rt1[i]);
1607 alloc_reg64(current,i,rt1[i]);
1608 alloc_all(current,i);
1609 alloc_reg64(current,i,FTEMP);
e1190b87 1610 minimum_free_regs[i]=HOST_REGS;
57871462 1611 }
1612 else current->is32|=1LL<<rt1[i];
1613 dirty_reg(current,rt1[i]);
1614 // If using TLB, need a register for pointer to the mapping table
1615 if(using_tlb) alloc_reg(current,i,TLREG);
1616 // LWL/LWR need a temporary register for the old value
1617 if(opcode[i]==0x22||opcode[i]==0x26)
1618 {
1619 alloc_reg(current,i,FTEMP);
1620 alloc_reg_temp(current,i,-1);
e1190b87 1621 minimum_free_regs[i]=1;
57871462 1622 }
1623 }
1624 else
1625 {
373d1d07 1626 // Load to r0 or unneeded register (dummy load)
57871462 1627 // but we still need a register to calculate the address
535d208a 1628 if(opcode[i]==0x22||opcode[i]==0x26)
1629 {
1630 alloc_reg(current,i,FTEMP); // LWL/LWR need another temporary
1631 }
373d1d07 1632 // If using TLB, need a register for pointer to the mapping table
1633 if(using_tlb) alloc_reg(current,i,TLREG);
57871462 1634 alloc_reg_temp(current,i,-1);
e1190b87 1635 minimum_free_regs[i]=1;
535d208a 1636 if(opcode[i]==0x1A||opcode[i]==0x1B) // LDL/LDR
1637 {
1638 alloc_all(current,i);
1639 alloc_reg64(current,i,FTEMP);
e1190b87 1640 minimum_free_regs[i]=HOST_REGS;
535d208a 1641 }
57871462 1642 }
1643}
1644
1645void store_alloc(struct regstat *current,int i)
1646{
1647 clear_const(current,rs2[i]);
1648 if(!(rs2[i])) current->u&=~1LL; // Allow allocating r0 if necessary
1649 if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1650 alloc_reg(current,i,rs2[i]);
1651 if(opcode[i]==0x2c||opcode[i]==0x2d||opcode[i]==0x3f) { // 64-bit SDL/SDR/SD
1652 alloc_reg64(current,i,rs2[i]);
1653 if(rs2[i]) alloc_reg(current,i,FTEMP);
1654 }
1655 // If using TLB, need a register for pointer to the mapping table
1656 if(using_tlb) alloc_reg(current,i,TLREG);
1657 #if defined(HOST_IMM8)
1658 // On CPUs without 32-bit immediates we need a pointer to invalid_code
1659 else alloc_reg(current,i,INVCP);
1660 #endif
b7918751 1661 if(opcode[i]==0x2a||opcode[i]==0x2e||opcode[i]==0x2c||opcode[i]==0x2d) { // SWL/SWL/SDL/SDR
57871462 1662 alloc_reg(current,i,FTEMP);
1663 }
1664 // We need a temporary register for address generation
1665 alloc_reg_temp(current,i,-1);
e1190b87 1666 minimum_free_regs[i]=1;
57871462 1667}
1668
1669void c1ls_alloc(struct regstat *current,int i)
1670{
1671 //clear_const(current,rs1[i]); // FIXME
1672 clear_const(current,rt1[i]);
1673 if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1674 alloc_reg(current,i,CSREG); // Status
1675 alloc_reg(current,i,FTEMP);
1676 if(opcode[i]==0x35||opcode[i]==0x3d) { // 64-bit LDC1/SDC1
1677 alloc_reg64(current,i,FTEMP);
1678 }
1679 // If using TLB, need a register for pointer to the mapping table
1680 if(using_tlb) alloc_reg(current,i,TLREG);
1681 #if defined(HOST_IMM8)
1682 // On CPUs without 32-bit immediates we need a pointer to invalid_code
1683 else if((opcode[i]&0x3b)==0x39) // SWC1/SDC1
1684 alloc_reg(current,i,INVCP);
1685 #endif
1686 // We need a temporary register for address generation
1687 alloc_reg_temp(current,i,-1);
1688}
1689
b9b61529 1690void c2ls_alloc(struct regstat *current,int i)
1691{
1692 clear_const(current,rt1[i]);
1693 if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1694 alloc_reg(current,i,FTEMP);
1695 // If using TLB, need a register for pointer to the mapping table
1696 if(using_tlb) alloc_reg(current,i,TLREG);
1697 #if defined(HOST_IMM8)
1698 // On CPUs without 32-bit immediates we need a pointer to invalid_code
1699 else if((opcode[i]&0x3b)==0x3a) // SWC2/SDC2
1700 alloc_reg(current,i,INVCP);
1701 #endif
1702 // We need a temporary register for address generation
1703 alloc_reg_temp(current,i,-1);
e1190b87 1704 minimum_free_regs[i]=1;
b9b61529 1705}
1706
57871462 1707#ifndef multdiv_alloc
1708void multdiv_alloc(struct regstat *current,int i)
1709{
1710 // case 0x18: MULT
1711 // case 0x19: MULTU
1712 // case 0x1A: DIV
1713 // case 0x1B: DIVU
1714 // case 0x1C: DMULT
1715 // case 0x1D: DMULTU
1716 // case 0x1E: DDIV
1717 // case 0x1F: DDIVU
1718 clear_const(current,rs1[i]);
1719 clear_const(current,rs2[i]);
1720 if(rs1[i]&&rs2[i])
1721 {
1722 if((opcode2[i]&4)==0) // 32-bit
1723 {
1724 current->u&=~(1LL<<HIREG);
1725 current->u&=~(1LL<<LOREG);
1726 alloc_reg(current,i,HIREG);
1727 alloc_reg(current,i,LOREG);
1728 alloc_reg(current,i,rs1[i]);
1729 alloc_reg(current,i,rs2[i]);
1730 current->is32|=1LL<<HIREG;
1731 current->is32|=1LL<<LOREG;
1732 dirty_reg(current,HIREG);
1733 dirty_reg(current,LOREG);
1734 }
1735 else // 64-bit
1736 {
1737 current->u&=~(1LL<<HIREG);
1738 current->u&=~(1LL<<LOREG);
1739 current->uu&=~(1LL<<HIREG);
1740 current->uu&=~(1LL<<LOREG);
1741 alloc_reg64(current,i,HIREG);
1742 //if(HOST_REGS>10) alloc_reg64(current,i,LOREG);
1743 alloc_reg64(current,i,rs1[i]);
1744 alloc_reg64(current,i,rs2[i]);
1745 alloc_all(current,i);
1746 current->is32&=~(1LL<<HIREG);
1747 current->is32&=~(1LL<<LOREG);
1748 dirty_reg(current,HIREG);
1749 dirty_reg(current,LOREG);
e1190b87 1750 minimum_free_regs[i]=HOST_REGS;
57871462 1751 }
1752 }
1753 else
1754 {
1755 // Multiply by zero is zero.
1756 // MIPS does not have a divide by zero exception.
1757 // The result is undefined, we return zero.
1758 alloc_reg(current,i,HIREG);
1759 alloc_reg(current,i,LOREG);
1760 current->is32|=1LL<<HIREG;
1761 current->is32|=1LL<<LOREG;
1762 dirty_reg(current,HIREG);
1763 dirty_reg(current,LOREG);
1764 }
1765}
1766#endif
1767
1768void cop0_alloc(struct regstat *current,int i)
1769{
1770 if(opcode2[i]==0) // MFC0
1771 {
1772 if(rt1[i]) {
1773 clear_const(current,rt1[i]);
1774 alloc_all(current,i);
1775 alloc_reg(current,i,rt1[i]);
1776 current->is32|=1LL<<rt1[i];
1777 dirty_reg(current,rt1[i]);
1778 }
1779 }
1780 else if(opcode2[i]==4) // MTC0
1781 {
1782 if(rs1[i]){
1783 clear_const(current,rs1[i]);
1784 alloc_reg(current,i,rs1[i]);
1785 alloc_all(current,i);
1786 }
1787 else {
1788 alloc_all(current,i); // FIXME: Keep r0
1789 current->u&=~1LL;
1790 alloc_reg(current,i,0);
1791 }
1792 }
1793 else
1794 {
1795 // TLBR/TLBWI/TLBWR/TLBP/ERET
1796 assert(opcode2[i]==0x10);
1797 alloc_all(current,i);
1798 }
e1190b87 1799 minimum_free_regs[i]=HOST_REGS;
57871462 1800}
1801
1802void cop1_alloc(struct regstat *current,int i)
1803{
1804 alloc_reg(current,i,CSREG); // Load status
1805 if(opcode2[i]<3) // MFC1/DMFC1/CFC1
1806 {
7de557a6 1807 if(rt1[i]){
1808 clear_const(current,rt1[i]);
1809 if(opcode2[i]==1) {
1810 alloc_reg64(current,i,rt1[i]); // DMFC1
1811 current->is32&=~(1LL<<rt1[i]);
1812 }else{
1813 alloc_reg(current,i,rt1[i]); // MFC1/CFC1
1814 current->is32|=1LL<<rt1[i];
1815 }
1816 dirty_reg(current,rt1[i]);
57871462 1817 }
57871462 1818 alloc_reg_temp(current,i,-1);
1819 }
1820 else if(opcode2[i]>3) // MTC1/DMTC1/CTC1
1821 {
1822 if(rs1[i]){
1823 clear_const(current,rs1[i]);
1824 if(opcode2[i]==5)
1825 alloc_reg64(current,i,rs1[i]); // DMTC1
1826 else
1827 alloc_reg(current,i,rs1[i]); // MTC1/CTC1
1828 alloc_reg_temp(current,i,-1);
1829 }
1830 else {
1831 current->u&=~1LL;
1832 alloc_reg(current,i,0);
1833 alloc_reg_temp(current,i,-1);
1834 }
1835 }
e1190b87 1836 minimum_free_regs[i]=1;
57871462 1837}
1838void fconv_alloc(struct regstat *current,int i)
1839{
1840 alloc_reg(current,i,CSREG); // Load status
1841 alloc_reg_temp(current,i,-1);
e1190b87 1842 minimum_free_regs[i]=1;
57871462 1843}
1844void float_alloc(struct regstat *current,int i)
1845{
1846 alloc_reg(current,i,CSREG); // Load status
1847 alloc_reg_temp(current,i,-1);
e1190b87 1848 minimum_free_regs[i]=1;
57871462 1849}
b9b61529 1850void c2op_alloc(struct regstat *current,int i)
1851{
1852 alloc_reg_temp(current,i,-1);
1853}
57871462 1854void fcomp_alloc(struct regstat *current,int i)
1855{
1856 alloc_reg(current,i,CSREG); // Load status
1857 alloc_reg(current,i,FSREG); // Load flags
1858 dirty_reg(current,FSREG); // Flag will be modified
1859 alloc_reg_temp(current,i,-1);
e1190b87 1860 minimum_free_regs[i]=1;
57871462 1861}
1862
1863void syscall_alloc(struct regstat *current,int i)
1864{
1865 alloc_cc(current,i);
1866 dirty_reg(current,CCREG);
1867 alloc_all(current,i);
e1190b87 1868 minimum_free_regs[i]=HOST_REGS;
57871462 1869 current->isconst=0;
1870}
1871
1872void delayslot_alloc(struct regstat *current,int i)
1873{
1874 switch(itype[i]) {
1875 case UJUMP:
1876 case CJUMP:
1877 case SJUMP:
1878 case RJUMP:
1879 case FJUMP:
1880 case SYSCALL:
7139f3c8 1881 case HLECALL:
57871462 1882 case SPAN:
1883 assem_debug("jump in the delay slot. this shouldn't happen.\n");//exit(1);
1884 printf("Disabled speculative precompilation\n");
1885 stop_after_jal=1;
1886 break;
1887 case IMM16:
1888 imm16_alloc(current,i);
1889 break;
1890 case LOAD:
1891 case LOADLR:
1892 load_alloc(current,i);
1893 break;
1894 case STORE:
1895 case STORELR:
1896 store_alloc(current,i);
1897 break;
1898 case ALU:
1899 alu_alloc(current,i);
1900 break;
1901 case SHIFT:
1902 shift_alloc(current,i);
1903 break;
1904 case MULTDIV:
1905 multdiv_alloc(current,i);
1906 break;
1907 case SHIFTIMM:
1908 shiftimm_alloc(current,i);
1909 break;
1910 case MOV:
1911 mov_alloc(current,i);
1912 break;
1913 case COP0:
1914 cop0_alloc(current,i);
1915 break;
1916 case COP1:
b9b61529 1917 case COP2:
57871462 1918 cop1_alloc(current,i);
1919 break;
1920 case C1LS:
1921 c1ls_alloc(current,i);
1922 break;
b9b61529 1923 case C2LS:
1924 c2ls_alloc(current,i);
1925 break;
57871462 1926 case FCONV:
1927 fconv_alloc(current,i);
1928 break;
1929 case FLOAT:
1930 float_alloc(current,i);
1931 break;
1932 case FCOMP:
1933 fcomp_alloc(current,i);
1934 break;
b9b61529 1935 case C2OP:
1936 c2op_alloc(current,i);
1937 break;
57871462 1938 }
1939}
1940
1941// Special case where a branch and delay slot span two pages in virtual memory
1942static void pagespan_alloc(struct regstat *current,int i)
1943{
1944 current->isconst=0;
1945 current->wasconst=0;
1946 regs[i].wasconst=0;
e1190b87 1947 minimum_free_regs[i]=HOST_REGS;
57871462 1948 alloc_all(current,i);
1949 alloc_cc(current,i);
1950 dirty_reg(current,CCREG);
1951 if(opcode[i]==3) // JAL
1952 {
1953 alloc_reg(current,i,31);
1954 dirty_reg(current,31);
1955 }
1956 if(opcode[i]==0&&(opcode2[i]&0x3E)==8) // JR/JALR
1957 {
1958 alloc_reg(current,i,rs1[i]);
5067f341 1959 if (rt1[i]!=0) {
1960 alloc_reg(current,i,rt1[i]);
1961 dirty_reg(current,rt1[i]);
57871462 1962 }
1963 }
1964 if((opcode[i]&0x2E)==4) // BEQ/BNE/BEQL/BNEL
1965 {
1966 if(rs1[i]) alloc_reg(current,i,rs1[i]);
1967 if(rs2[i]) alloc_reg(current,i,rs2[i]);
1968 if(!((current->is32>>rs1[i])&(current->is32>>rs2[i])&1))
1969 {
1970 if(rs1[i]) alloc_reg64(current,i,rs1[i]);
1971 if(rs2[i]) alloc_reg64(current,i,rs2[i]);
1972 }
1973 }
1974 else
1975 if((opcode[i]&0x2E)==6) // BLEZ/BGTZ/BLEZL/BGTZL
1976 {
1977 if(rs1[i]) alloc_reg(current,i,rs1[i]);
1978 if(!((current->is32>>rs1[i])&1))
1979 {
1980 if(rs1[i]) alloc_reg64(current,i,rs1[i]);
1981 }
1982 }
1983 else
1984 if(opcode[i]==0x11) // BC1
1985 {
1986 alloc_reg(current,i,FSREG);
1987 alloc_reg(current,i,CSREG);
1988 }
1989 //else ...
1990}
1991
1992add_stub(int type,int addr,int retaddr,int a,int b,int c,int d,int e)
1993{
1994 stubs[stubcount][0]=type;
1995 stubs[stubcount][1]=addr;
1996 stubs[stubcount][2]=retaddr;
1997 stubs[stubcount][3]=a;
1998 stubs[stubcount][4]=b;
1999 stubs[stubcount][5]=c;
2000 stubs[stubcount][6]=d;
2001 stubs[stubcount][7]=e;
2002 stubcount++;
2003}
2004
2005// Write out a single register
2006void wb_register(signed char r,signed char regmap[],uint64_t dirty,uint64_t is32)
2007{
2008 int hr;
2009 for(hr=0;hr<HOST_REGS;hr++) {
2010 if(hr!=EXCLUDE_REG) {
2011 if((regmap[hr]&63)==r) {
2012 if((dirty>>hr)&1) {
2013 if(regmap[hr]<64) {
2014 emit_storereg(r,hr);
24385cae 2015#ifndef FORCE32
57871462 2016 if((is32>>regmap[hr])&1) {
2017 emit_sarimm(hr,31,hr);
2018 emit_storereg(r|64,hr);
2019 }
24385cae 2020#endif
57871462 2021 }else{
2022 emit_storereg(r|64,hr);
2023 }
2024 }
2025 }
2026 }
2027 }
2028}
2029
2030int mchecksum()
2031{
2032 //if(!tracedebug) return 0;
2033 int i;
2034 int sum=0;
2035 for(i=0;i<2097152;i++) {
2036 unsigned int temp=sum;
2037 sum<<=1;
2038 sum|=(~temp)>>31;
2039 sum^=((u_int *)rdram)[i];
2040 }
2041 return sum;
2042}
2043int rchecksum()
2044{
2045 int i;
2046 int sum=0;
2047 for(i=0;i<64;i++)
2048 sum^=((u_int *)reg)[i];
2049 return sum;
2050}
57871462 2051void rlist()
2052{
2053 int i;
2054 printf("TRACE: ");
2055 for(i=0;i<32;i++)
2056 printf("r%d:%8x%8x ",i,((int *)(reg+i))[1],((int *)(reg+i))[0]);
2057 printf("\n");
3d624f89 2058#ifndef DISABLE_COP1
57871462 2059 printf("TRACE: ");
2060 for(i=0;i<32;i++)
2061 printf("f%d:%8x%8x ",i,((int*)reg_cop1_simple[i])[1],*((int*)reg_cop1_simple[i]));
2062 printf("\n");
3d624f89 2063#endif
57871462 2064}
2065
2066void enabletrace()
2067{
2068 tracedebug=1;
2069}
2070
2071void memdebug(int i)
2072{
2073 //printf("TRACE: count=%d next=%d (checksum %x) lo=%8x%8x\n",Count,next_interupt,mchecksum(),(int)(reg[LOREG]>>32),(int)reg[LOREG]);
2074 //printf("TRACE: count=%d next=%d (rchecksum %x)\n",Count,next_interupt,rchecksum());
2075 //rlist();
2076 //if(tracedebug) {
2077 //if(Count>=-2084597794) {
2078 if((signed int)Count>=-2084597794&&(signed int)Count<0) {
2079 //if(0) {
2080 printf("TRACE: count=%d next=%d (checksum %x)\n",Count,next_interupt,mchecksum());
2081 //printf("TRACE: count=%d next=%d (checksum %x) Status=%x\n",Count,next_interupt,mchecksum(),Status);
2082 //printf("TRACE: count=%d next=%d (checksum %x) hi=%8x%8x\n",Count,next_interupt,mchecksum(),(int)(reg[HIREG]>>32),(int)reg[HIREG]);
2083 rlist();
2084 #ifdef __i386__
2085 printf("TRACE: %x\n",(&i)[-1]);
2086 #endif
2087 #ifdef __arm__
2088 int j;
2089 printf("TRACE: %x \n",(&j)[10]);
2090 printf("TRACE: %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x\n",(&j)[1],(&j)[2],(&j)[3],(&j)[4],(&j)[5],(&j)[6],(&j)[7],(&j)[8],(&j)[9],(&j)[10],(&j)[11],(&j)[12],(&j)[13],(&j)[14],(&j)[15],(&j)[16],(&j)[17],(&j)[18],(&j)[19],(&j)[20]);
2091 #endif
2092 //fflush(stdout);
2093 }
2094 //printf("TRACE: %x\n",(&i)[-1]);
2095}
2096
2097void tlb_debug(u_int cause, u_int addr, u_int iaddr)
2098{
2099 printf("TLB Exception: instruction=%x addr=%x cause=%x\n",iaddr, addr, cause);
2100}
2101
2102void alu_assemble(int i,struct regstat *i_regs)
2103{
2104 if(opcode2[i]>=0x20&&opcode2[i]<=0x23) { // ADD/ADDU/SUB/SUBU
2105 if(rt1[i]) {
2106 signed char s1,s2,t;
2107 t=get_reg(i_regs->regmap,rt1[i]);
2108 if(t>=0) {
2109 s1=get_reg(i_regs->regmap,rs1[i]);
2110 s2=get_reg(i_regs->regmap,rs2[i]);
2111 if(rs1[i]&&rs2[i]) {
2112 assert(s1>=0);
2113 assert(s2>=0);
2114 if(opcode2[i]&2) emit_sub(s1,s2,t);
2115 else emit_add(s1,s2,t);
2116 }
2117 else if(rs1[i]) {
2118 if(s1>=0) emit_mov(s1,t);
2119 else emit_loadreg(rs1[i],t);
2120 }
2121 else if(rs2[i]) {
2122 if(s2>=0) {
2123 if(opcode2[i]&2) emit_neg(s2,t);
2124 else emit_mov(s2,t);
2125 }
2126 else {
2127 emit_loadreg(rs2[i],t);
2128 if(opcode2[i]&2) emit_neg(t,t);
2129 }
2130 }
2131 else emit_zeroreg(t);
2132 }
2133 }
2134 }
2135 if(opcode2[i]>=0x2c&&opcode2[i]<=0x2f) { // DADD/DADDU/DSUB/DSUBU
2136 if(rt1[i]) {
2137 signed char s1l,s2l,s1h,s2h,tl,th;
2138 tl=get_reg(i_regs->regmap,rt1[i]);
2139 th=get_reg(i_regs->regmap,rt1[i]|64);
2140 if(tl>=0) {
2141 s1l=get_reg(i_regs->regmap,rs1[i]);
2142 s2l=get_reg(i_regs->regmap,rs2[i]);
2143 s1h=get_reg(i_regs->regmap,rs1[i]|64);
2144 s2h=get_reg(i_regs->regmap,rs2[i]|64);
2145 if(rs1[i]&&rs2[i]) {
2146 assert(s1l>=0);
2147 assert(s2l>=0);
2148 if(opcode2[i]&2) emit_subs(s1l,s2l,tl);
2149 else emit_adds(s1l,s2l,tl);
2150 if(th>=0) {
2151 #ifdef INVERTED_CARRY
2152 if(opcode2[i]&2) {if(s1h!=th) emit_mov(s1h,th);emit_sbb(th,s2h);}
2153 #else
2154 if(opcode2[i]&2) emit_sbc(s1h,s2h,th);
2155 #endif
2156 else emit_add(s1h,s2h,th);
2157 }
2158 }
2159 else if(rs1[i]) {
2160 if(s1l>=0) emit_mov(s1l,tl);
2161 else emit_loadreg(rs1[i],tl);
2162 if(th>=0) {
2163 if(s1h>=0) emit_mov(s1h,th);
2164 else emit_loadreg(rs1[i]|64,th);
2165 }
2166 }
2167 else if(rs2[i]) {
2168 if(s2l>=0) {
2169 if(opcode2[i]&2) emit_negs(s2l,tl);
2170 else emit_mov(s2l,tl);
2171 }
2172 else {
2173 emit_loadreg(rs2[i],tl);
2174 if(opcode2[i]&2) emit_negs(tl,tl);
2175 }
2176 if(th>=0) {
2177 #ifdef INVERTED_CARRY
2178 if(s2h>=0) emit_mov(s2h,th);
2179 else emit_loadreg(rs2[i]|64,th);
2180 if(opcode2[i]&2) {
2181 emit_adcimm(-1,th); // x86 has inverted carry flag
2182 emit_not(th,th);
2183 }
2184 #else
2185 if(opcode2[i]&2) {
2186 if(s2h>=0) emit_rscimm(s2h,0,th);
2187 else {
2188 emit_loadreg(rs2[i]|64,th);
2189 emit_rscimm(th,0,th);
2190 }
2191 }else{
2192 if(s2h>=0) emit_mov(s2h,th);
2193 else emit_loadreg(rs2[i]|64,th);
2194 }
2195 #endif
2196 }
2197 }
2198 else {
2199 emit_zeroreg(tl);
2200 if(th>=0) emit_zeroreg(th);
2201 }
2202 }
2203 }
2204 }
2205 if(opcode2[i]==0x2a||opcode2[i]==0x2b) { // SLT/SLTU
2206 if(rt1[i]) {
2207 signed char s1l,s1h,s2l,s2h,t;
2208 if(!((i_regs->was32>>rs1[i])&(i_regs->was32>>rs2[i])&1))
2209 {
2210 t=get_reg(i_regs->regmap,rt1[i]);
2211 //assert(t>=0);
2212 if(t>=0) {
2213 s1l=get_reg(i_regs->regmap,rs1[i]);
2214 s1h=get_reg(i_regs->regmap,rs1[i]|64);
2215 s2l=get_reg(i_regs->regmap,rs2[i]);
2216 s2h=get_reg(i_regs->regmap,rs2[i]|64);
2217 if(rs2[i]==0) // rx<r0
2218 {
2219 assert(s1h>=0);
2220 if(opcode2[i]==0x2a) // SLT
2221 emit_shrimm(s1h,31,t);
2222 else // SLTU (unsigned can not be less than zero)
2223 emit_zeroreg(t);
2224 }
2225 else if(rs1[i]==0) // r0<rx
2226 {
2227 assert(s2h>=0);
2228 if(opcode2[i]==0x2a) // SLT
2229 emit_set_gz64_32(s2h,s2l,t);
2230 else // SLTU (set if not zero)
2231 emit_set_nz64_32(s2h,s2l,t);
2232 }
2233 else {
2234 assert(s1l>=0);assert(s1h>=0);
2235 assert(s2l>=0);assert(s2h>=0);
2236 if(opcode2[i]==0x2a) // SLT
2237 emit_set_if_less64_32(s1h,s1l,s2h,s2l,t);
2238 else // SLTU
2239 emit_set_if_carry64_32(s1h,s1l,s2h,s2l,t);
2240 }
2241 }
2242 } else {
2243 t=get_reg(i_regs->regmap,rt1[i]);
2244 //assert(t>=0);
2245 if(t>=0) {
2246 s1l=get_reg(i_regs->regmap,rs1[i]);
2247 s2l=get_reg(i_regs->regmap,rs2[i]);
2248 if(rs2[i]==0) // rx<r0
2249 {
2250 assert(s1l>=0);
2251 if(opcode2[i]==0x2a) // SLT
2252 emit_shrimm(s1l,31,t);
2253 else // SLTU (unsigned can not be less than zero)
2254 emit_zeroreg(t);
2255 }
2256 else if(rs1[i]==0) // r0<rx
2257 {
2258 assert(s2l>=0);
2259 if(opcode2[i]==0x2a) // SLT
2260 emit_set_gz32(s2l,t);
2261 else // SLTU (set if not zero)
2262 emit_set_nz32(s2l,t);
2263 }
2264 else{
2265 assert(s1l>=0);assert(s2l>=0);
2266 if(opcode2[i]==0x2a) // SLT
2267 emit_set_if_less32(s1l,s2l,t);
2268 else // SLTU
2269 emit_set_if_carry32(s1l,s2l,t);
2270 }
2271 }
2272 }
2273 }
2274 }
2275 if(opcode2[i]>=0x24&&opcode2[i]<=0x27) { // AND/OR/XOR/NOR
2276 if(rt1[i]) {
2277 signed char s1l,s1h,s2l,s2h,th,tl;
2278 tl=get_reg(i_regs->regmap,rt1[i]);
2279 th=get_reg(i_regs->regmap,rt1[i]|64);
2280 if(!((i_regs->was32>>rs1[i])&(i_regs->was32>>rs2[i])&1)&&th>=0)
2281 {
2282 assert(tl>=0);
2283 if(tl>=0) {
2284 s1l=get_reg(i_regs->regmap,rs1[i]);
2285 s1h=get_reg(i_regs->regmap,rs1[i]|64);
2286 s2l=get_reg(i_regs->regmap,rs2[i]);
2287 s2h=get_reg(i_regs->regmap,rs2[i]|64);
2288 if(rs1[i]&&rs2[i]) {
2289 assert(s1l>=0);assert(s1h>=0);
2290 assert(s2l>=0);assert(s2h>=0);
2291 if(opcode2[i]==0x24) { // AND
2292 emit_and(s1l,s2l,tl);
2293 emit_and(s1h,s2h,th);
2294 } else
2295 if(opcode2[i]==0x25) { // OR
2296 emit_or(s1l,s2l,tl);
2297 emit_or(s1h,s2h,th);
2298 } else
2299 if(opcode2[i]==0x26) { // XOR
2300 emit_xor(s1l,s2l,tl);
2301 emit_xor(s1h,s2h,th);
2302 } else
2303 if(opcode2[i]==0x27) { // NOR
2304 emit_or(s1l,s2l,tl);
2305 emit_or(s1h,s2h,th);
2306 emit_not(tl,tl);
2307 emit_not(th,th);
2308 }
2309 }
2310 else
2311 {
2312 if(opcode2[i]==0x24) { // AND
2313 emit_zeroreg(tl);
2314 emit_zeroreg(th);
2315 } else
2316 if(opcode2[i]==0x25||opcode2[i]==0x26) { // OR/XOR
2317 if(rs1[i]){
2318 if(s1l>=0) emit_mov(s1l,tl);
2319 else emit_loadreg(rs1[i],tl);
2320 if(s1h>=0) emit_mov(s1h,th);
2321 else emit_loadreg(rs1[i]|64,th);
2322 }
2323 else
2324 if(rs2[i]){
2325 if(s2l>=0) emit_mov(s2l,tl);
2326 else emit_loadreg(rs2[i],tl);
2327 if(s2h>=0) emit_mov(s2h,th);
2328 else emit_loadreg(rs2[i]|64,th);
2329 }
2330 else{
2331 emit_zeroreg(tl);
2332 emit_zeroreg(th);
2333 }
2334 } else
2335 if(opcode2[i]==0x27) { // NOR
2336 if(rs1[i]){
2337 if(s1l>=0) emit_not(s1l,tl);
2338 else{
2339 emit_loadreg(rs1[i],tl);
2340 emit_not(tl,tl);
2341 }
2342 if(s1h>=0) emit_not(s1h,th);
2343 else{
2344 emit_loadreg(rs1[i]|64,th);
2345 emit_not(th,th);
2346 }
2347 }
2348 else
2349 if(rs2[i]){
2350 if(s2l>=0) emit_not(s2l,tl);
2351 else{
2352 emit_loadreg(rs2[i],tl);
2353 emit_not(tl,tl);
2354 }
2355 if(s2h>=0) emit_not(s2h,th);
2356 else{
2357 emit_loadreg(rs2[i]|64,th);
2358 emit_not(th,th);
2359 }
2360 }
2361 else {
2362 emit_movimm(-1,tl);
2363 emit_movimm(-1,th);
2364 }
2365 }
2366 }
2367 }
2368 }
2369 else
2370 {
2371 // 32 bit
2372 if(tl>=0) {
2373 s1l=get_reg(i_regs->regmap,rs1[i]);
2374 s2l=get_reg(i_regs->regmap,rs2[i]);
2375 if(rs1[i]&&rs2[i]) {
2376 assert(s1l>=0);
2377 assert(s2l>=0);
2378 if(opcode2[i]==0x24) { // AND
2379 emit_and(s1l,s2l,tl);
2380 } else
2381 if(opcode2[i]==0x25) { // OR
2382 emit_or(s1l,s2l,tl);
2383 } else
2384 if(opcode2[i]==0x26) { // XOR
2385 emit_xor(s1l,s2l,tl);
2386 } else
2387 if(opcode2[i]==0x27) { // NOR
2388 emit_or(s1l,s2l,tl);
2389 emit_not(tl,tl);
2390 }
2391 }
2392 else
2393 {
2394 if(opcode2[i]==0x24) { // AND
2395 emit_zeroreg(tl);
2396 } else
2397 if(opcode2[i]==0x25||opcode2[i]==0x26) { // OR/XOR
2398 if(rs1[i]){
2399 if(s1l>=0) emit_mov(s1l,tl);
2400 else emit_loadreg(rs1[i],tl); // CHECK: regmap_entry?
2401 }
2402 else
2403 if(rs2[i]){
2404 if(s2l>=0) emit_mov(s2l,tl);
2405 else emit_loadreg(rs2[i],tl); // CHECK: regmap_entry?
2406 }
2407 else emit_zeroreg(tl);
2408 } else
2409 if(opcode2[i]==0x27) { // NOR
2410 if(rs1[i]){
2411 if(s1l>=0) emit_not(s1l,tl);
2412 else {
2413 emit_loadreg(rs1[i],tl);
2414 emit_not(tl,tl);
2415 }
2416 }
2417 else
2418 if(rs2[i]){
2419 if(s2l>=0) emit_not(s2l,tl);
2420 else {
2421 emit_loadreg(rs2[i],tl);
2422 emit_not(tl,tl);
2423 }
2424 }
2425 else emit_movimm(-1,tl);
2426 }
2427 }
2428 }
2429 }
2430 }
2431 }
2432}
2433
2434void imm16_assemble(int i,struct regstat *i_regs)
2435{
2436 if (opcode[i]==0x0f) { // LUI
2437 if(rt1[i]) {
2438 signed char t;
2439 t=get_reg(i_regs->regmap,rt1[i]);
2440 //assert(t>=0);
2441 if(t>=0) {
2442 if(!((i_regs->isconst>>t)&1))
2443 emit_movimm(imm[i]<<16,t);
2444 }
2445 }
2446 }
2447 if(opcode[i]==0x08||opcode[i]==0x09) { // ADDI/ADDIU
2448 if(rt1[i]) {
2449 signed char s,t;
2450 t=get_reg(i_regs->regmap,rt1[i]);
2451 s=get_reg(i_regs->regmap,rs1[i]);
2452 if(rs1[i]) {
2453 //assert(t>=0);
2454 //assert(s>=0);
2455 if(t>=0) {
2456 if(!((i_regs->isconst>>t)&1)) {
2457 if(s<0) {
2458 if(i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2459 emit_addimm(t,imm[i],t);
2460 }else{
2461 if(!((i_regs->wasconst>>s)&1))
2462 emit_addimm(s,imm[i],t);
2463 else
2464 emit_movimm(constmap[i][s]+imm[i],t);
2465 }
2466 }
2467 }
2468 } else {
2469 if(t>=0) {
2470 if(!((i_regs->isconst>>t)&1))
2471 emit_movimm(imm[i],t);
2472 }
2473 }
2474 }
2475 }
2476 if(opcode[i]==0x18||opcode[i]==0x19) { // DADDI/DADDIU
2477 if(rt1[i]) {
2478 signed char sh,sl,th,tl;
2479 th=get_reg(i_regs->regmap,rt1[i]|64);
2480 tl=get_reg(i_regs->regmap,rt1[i]);
2481 sh=get_reg(i_regs->regmap,rs1[i]|64);
2482 sl=get_reg(i_regs->regmap,rs1[i]);
2483 if(tl>=0) {
2484 if(rs1[i]) {
2485 assert(sh>=0);
2486 assert(sl>=0);
2487 if(th>=0) {
2488 emit_addimm64_32(sh,sl,imm[i],th,tl);
2489 }
2490 else {
2491 emit_addimm(sl,imm[i],tl);
2492 }
2493 } else {
2494 emit_movimm(imm[i],tl);
2495 if(th>=0) emit_movimm(((signed int)imm[i])>>31,th);
2496 }
2497 }
2498 }
2499 }
2500 else if(opcode[i]==0x0a||opcode[i]==0x0b) { // SLTI/SLTIU
2501 if(rt1[i]) {
2502 //assert(rs1[i]!=0); // r0 might be valid, but it's probably a bug
2503 signed char sh,sl,t;
2504 t=get_reg(i_regs->regmap,rt1[i]);
2505 sh=get_reg(i_regs->regmap,rs1[i]|64);
2506 sl=get_reg(i_regs->regmap,rs1[i]);
2507 //assert(t>=0);
2508 if(t>=0) {
2509 if(rs1[i]>0) {
2510 if(sh<0) assert((i_regs->was32>>rs1[i])&1);
2511 if(sh<0||((i_regs->was32>>rs1[i])&1)) {
2512 if(opcode[i]==0x0a) { // SLTI
2513 if(sl<0) {
2514 if(i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2515 emit_slti32(t,imm[i],t);
2516 }else{
2517 emit_slti32(sl,imm[i],t);
2518 }
2519 }
2520 else { // SLTIU
2521 if(sl<0) {
2522 if(i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2523 emit_sltiu32(t,imm[i],t);
2524 }else{
2525 emit_sltiu32(sl,imm[i],t);
2526 }
2527 }
2528 }else{ // 64-bit
2529 assert(sl>=0);
2530 if(opcode[i]==0x0a) // SLTI
2531 emit_slti64_32(sh,sl,imm[i],t);
2532 else // SLTIU
2533 emit_sltiu64_32(sh,sl,imm[i],t);
2534 }
2535 }else{
2536 // SLTI(U) with r0 is just stupid,
2537 // nonetheless examples can be found
2538 if(opcode[i]==0x0a) // SLTI
2539 if(0<imm[i]) emit_movimm(1,t);
2540 else emit_zeroreg(t);
2541 else // SLTIU
2542 {
2543 if(imm[i]) emit_movimm(1,t);
2544 else emit_zeroreg(t);
2545 }
2546 }
2547 }
2548 }
2549 }
2550 else if(opcode[i]>=0x0c&&opcode[i]<=0x0e) { // ANDI/ORI/XORI
2551 if(rt1[i]) {
2552 signed char sh,sl,th,tl;
2553 th=get_reg(i_regs->regmap,rt1[i]|64);
2554 tl=get_reg(i_regs->regmap,rt1[i]);
2555 sh=get_reg(i_regs->regmap,rs1[i]|64);
2556 sl=get_reg(i_regs->regmap,rs1[i]);
2557 if(tl>=0 && !((i_regs->isconst>>tl)&1)) {
2558 if(opcode[i]==0x0c) //ANDI
2559 {
2560 if(rs1[i]) {
2561 if(sl<0) {
2562 if(i_regs->regmap_entry[tl]!=rs1[i]) emit_loadreg(rs1[i],tl);
2563 emit_andimm(tl,imm[i],tl);
2564 }else{
2565 if(!((i_regs->wasconst>>sl)&1))
2566 emit_andimm(sl,imm[i],tl);
2567 else
2568 emit_movimm(constmap[i][sl]&imm[i],tl);
2569 }
2570 }
2571 else
2572 emit_zeroreg(tl);
2573 if(th>=0) emit_zeroreg(th);
2574 }
2575 else
2576 {
2577 if(rs1[i]) {
2578 if(sl<0) {
2579 if(i_regs->regmap_entry[tl]!=rs1[i]) emit_loadreg(rs1[i],tl);
2580 }
2581 if(th>=0) {
2582 if(sh<0) {
2583 emit_loadreg(rs1[i]|64,th);
2584 }else{
2585 emit_mov(sh,th);
2586 }
2587 }
2588 if(opcode[i]==0x0d) //ORI
2589 if(sl<0) {
2590 emit_orimm(tl,imm[i],tl);
2591 }else{
2592 if(!((i_regs->wasconst>>sl)&1))
2593 emit_orimm(sl,imm[i],tl);
2594 else
2595 emit_movimm(constmap[i][sl]|imm[i],tl);
2596 }
2597 if(opcode[i]==0x0e) //XORI
2598 if(sl<0) {
2599 emit_xorimm(tl,imm[i],tl);
2600 }else{
2601 if(!((i_regs->wasconst>>sl)&1))
2602 emit_xorimm(sl,imm[i],tl);
2603 else
2604 emit_movimm(constmap[i][sl]^imm[i],tl);
2605 }
2606 }
2607 else {
2608 emit_movimm(imm[i],tl);
2609 if(th>=0) emit_zeroreg(th);
2610 }
2611 }
2612 }
2613 }
2614 }
2615}
2616
2617void shiftimm_assemble(int i,struct regstat *i_regs)
2618{
2619 if(opcode2[i]<=0x3) // SLL/SRL/SRA
2620 {
2621 if(rt1[i]) {
2622 signed char s,t;
2623 t=get_reg(i_regs->regmap,rt1[i]);
2624 s=get_reg(i_regs->regmap,rs1[i]);
2625 //assert(t>=0);
2626 if(t>=0){
2627 if(rs1[i]==0)
2628 {
2629 emit_zeroreg(t);
2630 }
2631 else
2632 {
2633 if(s<0&&i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2634 if(imm[i]) {
2635 if(opcode2[i]==0) // SLL
2636 {
2637 emit_shlimm(s<0?t:s,imm[i],t);
2638 }
2639 if(opcode2[i]==2) // SRL
2640 {
2641 emit_shrimm(s<0?t:s,imm[i],t);
2642 }
2643 if(opcode2[i]==3) // SRA
2644 {
2645 emit_sarimm(s<0?t:s,imm[i],t);
2646 }
2647 }else{
2648 // Shift by zero
2649 if(s>=0 && s!=t) emit_mov(s,t);
2650 }
2651 }
2652 }
2653 //emit_storereg(rt1[i],t); //DEBUG
2654 }
2655 }
2656 if(opcode2[i]>=0x38&&opcode2[i]<=0x3b) // DSLL/DSRL/DSRA
2657 {
2658 if(rt1[i]) {
2659 signed char sh,sl,th,tl;
2660 th=get_reg(i_regs->regmap,rt1[i]|64);
2661 tl=get_reg(i_regs->regmap,rt1[i]);
2662 sh=get_reg(i_regs->regmap,rs1[i]|64);
2663 sl=get_reg(i_regs->regmap,rs1[i]);
2664 if(tl>=0) {
2665 if(rs1[i]==0)
2666 {
2667 emit_zeroreg(tl);
2668 if(th>=0) emit_zeroreg(th);
2669 }
2670 else
2671 {
2672 assert(sl>=0);
2673 assert(sh>=0);
2674 if(imm[i]) {
2675 if(opcode2[i]==0x38) // DSLL
2676 {
2677 if(th>=0) emit_shldimm(sh,sl,imm[i],th);
2678 emit_shlimm(sl,imm[i],tl);
2679 }
2680 if(opcode2[i]==0x3a) // DSRL
2681 {
2682 emit_shrdimm(sl,sh,imm[i],tl);
2683 if(th>=0) emit_shrimm(sh,imm[i],th);
2684 }
2685 if(opcode2[i]==0x3b) // DSRA
2686 {
2687 emit_shrdimm(sl,sh,imm[i],tl);
2688 if(th>=0) emit_sarimm(sh,imm[i],th);
2689 }
2690 }else{
2691 // Shift by zero
2692 if(sl!=tl) emit_mov(sl,tl);
2693 if(th>=0&&sh!=th) emit_mov(sh,th);
2694 }
2695 }
2696 }
2697 }
2698 }
2699 if(opcode2[i]==0x3c) // DSLL32
2700 {
2701 if(rt1[i]) {
2702 signed char sl,tl,th;
2703 tl=get_reg(i_regs->regmap,rt1[i]);
2704 th=get_reg(i_regs->regmap,rt1[i]|64);
2705 sl=get_reg(i_regs->regmap,rs1[i]);
2706 if(th>=0||tl>=0){
2707 assert(tl>=0);
2708 assert(th>=0);
2709 assert(sl>=0);
2710 emit_mov(sl,th);
2711 emit_zeroreg(tl);
2712 if(imm[i]>32)
2713 {
2714 emit_shlimm(th,imm[i]&31,th);
2715 }
2716 }
2717 }
2718 }
2719 if(opcode2[i]==0x3e) // DSRL32
2720 {
2721 if(rt1[i]) {
2722 signed char sh,tl,th;
2723 tl=get_reg(i_regs->regmap,rt1[i]);
2724 th=get_reg(i_regs->regmap,rt1[i]|64);
2725 sh=get_reg(i_regs->regmap,rs1[i]|64);
2726 if(tl>=0){
2727 assert(sh>=0);
2728 emit_mov(sh,tl);
2729 if(th>=0) emit_zeroreg(th);
2730 if(imm[i]>32)
2731 {
2732 emit_shrimm(tl,imm[i]&31,tl);
2733 }
2734 }
2735 }
2736 }
2737 if(opcode2[i]==0x3f) // DSRA32
2738 {
2739 if(rt1[i]) {
2740 signed char sh,tl;
2741 tl=get_reg(i_regs->regmap,rt1[i]);
2742 sh=get_reg(i_regs->regmap,rs1[i]|64);
2743 if(tl>=0){
2744 assert(sh>=0);
2745 emit_mov(sh,tl);
2746 if(imm[i]>32)
2747 {
2748 emit_sarimm(tl,imm[i]&31,tl);
2749 }
2750 }
2751 }
2752 }
2753}
2754
2755#ifndef shift_assemble
2756void shift_assemble(int i,struct regstat *i_regs)
2757{
2758 printf("Need shift_assemble for this architecture.\n");
2759 exit(1);
2760}
2761#endif
2762
2763void load_assemble(int i,struct regstat *i_regs)
2764{
2765 int s,th,tl,addr,map=-1;
2766 int offset;
2767 int jaddr=0;
5bf843dc 2768 int memtarget=0,c=0;
b1570849 2769 int fastload_reg_override=0;
57871462 2770 u_int hr,reglist=0;
2771 th=get_reg(i_regs->regmap,rt1[i]|64);
2772 tl=get_reg(i_regs->regmap,rt1[i]);
2773 s=get_reg(i_regs->regmap,rs1[i]);
2774 offset=imm[i];
2775 for(hr=0;hr<HOST_REGS;hr++) {
2776 if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
2777 }
2778 if(i_regs->regmap[HOST_CCREG]==CCREG) reglist&=~(1<<HOST_CCREG);
2779 if(s>=0) {
2780 c=(i_regs->wasconst>>s)&1;
af4ee1fe 2781 if (c) {
2782 memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
2783 if(using_tlb&&((signed int)(constmap[i][s]+offset))>=(signed int)0xC0000000) memtarget=1;
2784 }
57871462 2785 }
57871462 2786 //printf("load_assemble: c=%d\n",c);
2787 //if(c) printf("load_assemble: const=%x\n",(int)constmap[i][s]+offset);
2788 // FIXME: Even if the load is a NOP, we should check for pagefaults...
5bf843dc 2789#ifdef PCSX
f18c0f46 2790 if(tl<0&&(!c||(((u_int)constmap[i][s]+offset)>>16)==0x1f80)
2791 ||rt1[i]==0) {
5bf843dc 2792 // could be FIFO, must perform the read
f18c0f46 2793 // ||dummy read
5bf843dc 2794 assem_debug("(forced read)\n");
2795 tl=get_reg(i_regs->regmap,-1);
2796 assert(tl>=0);
5bf843dc 2797 }
f18c0f46 2798#endif
5bf843dc 2799 if(offset||s<0||c) addr=tl;
2800 else addr=s;
535d208a 2801 //if(tl<0) tl=get_reg(i_regs->regmap,-1);
2802 if(tl>=0) {
2803 //printf("load_assemble: c=%d\n",c);
2804 //if(c) printf("load_assemble: const=%x\n",(int)constmap[i][s]+offset);
2805 assert(tl>=0); // Even if the load is a NOP, we must check for pagefaults and I/O
2806 reglist&=~(1<<tl);
2807 if(th>=0) reglist&=~(1<<th);
2808 if(!using_tlb) {
2809 if(!c) {
2810 #ifdef RAM_OFFSET
2811 map=get_reg(i_regs->regmap,ROREG);
2812 if(map<0) emit_loadreg(ROREG,map=HOST_TEMPREG);
2813 #endif
57871462 2814//#define R29_HACK 1
535d208a 2815 #ifdef R29_HACK
2816 // Strmnnrmn's speed hack
2817 if(rs1[i]!=29||start<0x80001000||start>=0x80000000+RAM_SIZE)
2818 #endif
2819 {
dadf55f2 2820 #ifdef PCSX
2821 if(sp_in_mirror&&rs1[i]==29) {
2822 emit_andimm(addr,~0x00e00000,HOST_TEMPREG);
2823 emit_cmpimm(HOST_TEMPREG,RAM_SIZE);
b1570849 2824 fastload_reg_override=HOST_TEMPREG;
dadf55f2 2825 }
2826 else
2827 #endif
535d208a 2828 emit_cmpimm(addr,RAM_SIZE);
2829 jaddr=(int)out;
2830 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
2831 // Hint to branch predictor that the branch is unlikely to be taken
2832 if(rs1[i]>=28)
2833 emit_jno_unlikely(0);
2834 else
57871462 2835 #endif
535d208a 2836 emit_jno(0);
57871462 2837 }
535d208a 2838 }
2839 }else{ // using tlb
2840 int x=0;
2841 if (opcode[i]==0x20||opcode[i]==0x24) x=3; // LB/LBU
2842 if (opcode[i]==0x21||opcode[i]==0x25) x=2; // LH/LHU
2843 map=get_reg(i_regs->regmap,TLREG);
2844 assert(map>=0);
ea3d2e6e 2845 reglist&=~(1<<map);
535d208a 2846 map=do_tlb_r(addr,tl,map,x,-1,-1,c,constmap[i][s]+offset);
2847 do_tlb_r_branch(map,c,constmap[i][s]+offset,&jaddr);
2848 }
2849 int dummy=(rt1[i]==0)||(tl!=get_reg(i_regs->regmap,rt1[i])); // ignore loads to r0 and unneeded reg
2850 if (opcode[i]==0x20) { // LB
2851 if(!c||memtarget) {
2852 if(!dummy) {
57871462 2853 #ifdef HOST_IMM_ADDR32
2854 if(c)
2855 emit_movsbl_tlb((constmap[i][s]+offset)^3,map,tl);
2856 else
2857 #endif
2858 {
2859 //emit_xorimm(addr,3,tl);
2860 //gen_tlb_addr_r(tl,map);
2861 //emit_movsbl_indexed((int)rdram-0x80000000,tl,tl);
535d208a 2862 int x=0,a=tl;
2002a1db 2863#ifdef BIG_ENDIAN_MIPS
57871462 2864 if(!c) emit_xorimm(addr,3,tl);
2865 else x=((constmap[i][s]+offset)^3)-(constmap[i][s]+offset);
2002a1db 2866#else
535d208a 2867 if(!c) a=addr;
dadf55f2 2868#endif
b1570849 2869 if(fastload_reg_override) a=fastload_reg_override;
2870
535d208a 2871 emit_movsbl_indexed_tlb(x,a,map,tl);
57871462 2872 }
57871462 2873 }
535d208a 2874 if(jaddr)
2875 add_stub(LOADB_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
57871462 2876 }
535d208a 2877 else
2878 inline_readstub(LOADB_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2879 }
2880 if (opcode[i]==0x21) { // LH
2881 if(!c||memtarget) {
2882 if(!dummy) {
57871462 2883 #ifdef HOST_IMM_ADDR32
2884 if(c)
2885 emit_movswl_tlb((constmap[i][s]+offset)^2,map,tl);
2886 else
2887 #endif
2888 {
535d208a 2889 int x=0,a=tl;
2002a1db 2890#ifdef BIG_ENDIAN_MIPS
57871462 2891 if(!c) emit_xorimm(addr,2,tl);
2892 else x=((constmap[i][s]+offset)^2)-(constmap[i][s]+offset);
2002a1db 2893#else
535d208a 2894 if(!c) a=addr;
dadf55f2 2895#endif
b1570849 2896 if(fastload_reg_override) a=fastload_reg_override;
57871462 2897 //#ifdef
2898 //emit_movswl_indexed_tlb(x,tl,map,tl);
2899 //else
2900 if(map>=0) {
535d208a 2901 gen_tlb_addr_r(a,map);
2902 emit_movswl_indexed(x,a,tl);
2903 }else{
2904 #ifdef RAM_OFFSET
2905 emit_movswl_indexed(x,a,tl);
2906 #else
2907 emit_movswl_indexed((int)rdram-0x80000000+x,a,tl);
2908 #endif
2909 }
57871462 2910 }
57871462 2911 }
535d208a 2912 if(jaddr)
2913 add_stub(LOADH_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
57871462 2914 }
535d208a 2915 else
2916 inline_readstub(LOADH_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2917 }
2918 if (opcode[i]==0x23) { // LW
2919 if(!c||memtarget) {
2920 if(!dummy) {
dadf55f2 2921 int a=addr;
b1570849 2922 if(fastload_reg_override) a=fastload_reg_override;
57871462 2923 //emit_readword_indexed((int)rdram-0x80000000,addr,tl);
2924 #ifdef HOST_IMM_ADDR32
2925 if(c)
2926 emit_readword_tlb(constmap[i][s]+offset,map,tl);
2927 else
2928 #endif
dadf55f2 2929 emit_readword_indexed_tlb(0,a,map,tl);
57871462 2930 }
535d208a 2931 if(jaddr)
2932 add_stub(LOADW_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
57871462 2933 }
535d208a 2934 else
2935 inline_readstub(LOADW_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2936 }
2937 if (opcode[i]==0x24) { // LBU
2938 if(!c||memtarget) {
2939 if(!dummy) {
57871462 2940 #ifdef HOST_IMM_ADDR32
2941 if(c)
2942 emit_movzbl_tlb((constmap[i][s]+offset)^3,map,tl);
2943 else
2944 #endif
2945 {
2946 //emit_xorimm(addr,3,tl);
2947 //gen_tlb_addr_r(tl,map);
2948 //emit_movzbl_indexed((int)rdram-0x80000000,tl,tl);
535d208a 2949 int x=0,a=tl;
2002a1db 2950#ifdef BIG_ENDIAN_MIPS
57871462 2951 if(!c) emit_xorimm(addr,3,tl);
2952 else x=((constmap[i][s]+offset)^3)-(constmap[i][s]+offset);
2002a1db 2953#else
535d208a 2954 if(!c) a=addr;
dadf55f2 2955#endif
b1570849 2956 if(fastload_reg_override) a=fastload_reg_override;
2957
535d208a 2958 emit_movzbl_indexed_tlb(x,a,map,tl);
57871462 2959 }
57871462 2960 }
535d208a 2961 if(jaddr)
2962 add_stub(LOADBU_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
57871462 2963 }
535d208a 2964 else
2965 inline_readstub(LOADBU_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2966 }
2967 if (opcode[i]==0x25) { // LHU
2968 if(!c||memtarget) {
2969 if(!dummy) {
57871462 2970 #ifdef HOST_IMM_ADDR32
2971 if(c)
2972 emit_movzwl_tlb((constmap[i][s]+offset)^2,map,tl);
2973 else
2974 #endif
2975 {
535d208a 2976 int x=0,a=tl;
2002a1db 2977#ifdef BIG_ENDIAN_MIPS
57871462 2978 if(!c) emit_xorimm(addr,2,tl);
2979 else x=((constmap[i][s]+offset)^2)-(constmap[i][s]+offset);
2002a1db 2980#else
535d208a 2981 if(!c) a=addr;
dadf55f2 2982#endif
b1570849 2983 if(fastload_reg_override) a=fastload_reg_override;
57871462 2984 //#ifdef
2985 //emit_movzwl_indexed_tlb(x,tl,map,tl);
2986 //#else
2987 if(map>=0) {
535d208a 2988 gen_tlb_addr_r(a,map);
2989 emit_movzwl_indexed(x,a,tl);
2990 }else{
2991 #ifdef RAM_OFFSET
2992 emit_movzwl_indexed(x,a,tl);
2993 #else
2994 emit_movzwl_indexed((int)rdram-0x80000000+x,a,tl);
2995 #endif
2996 }
57871462 2997 }
2998 }
535d208a 2999 if(jaddr)
3000 add_stub(LOADHU_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
57871462 3001 }
535d208a 3002 else
3003 inline_readstub(LOADHU_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
3004 }
3005 if (opcode[i]==0x27) { // LWU
3006 assert(th>=0);
3007 if(!c||memtarget) {
3008 if(!dummy) {
dadf55f2 3009 int a=addr;
b1570849 3010 if(fastload_reg_override) a=fastload_reg_override;
57871462 3011 //emit_readword_indexed((int)rdram-0x80000000,addr,tl);
3012 #ifdef HOST_IMM_ADDR32
3013 if(c)
3014 emit_readword_tlb(constmap[i][s]+offset,map,tl);
3015 else
3016 #endif
dadf55f2 3017 emit_readword_indexed_tlb(0,a,map,tl);
57871462 3018 }
535d208a 3019 if(jaddr)
3020 add_stub(LOADW_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
3021 }
3022 else {
3023 inline_readstub(LOADW_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
57871462 3024 }
535d208a 3025 emit_zeroreg(th);
3026 }
3027 if (opcode[i]==0x37) { // LD
3028 if(!c||memtarget) {
3029 if(!dummy) {
dadf55f2 3030 int a=addr;
b1570849 3031 if(fastload_reg_override) a=fastload_reg_override;
57871462 3032 //gen_tlb_addr_r(tl,map);
3033 //if(th>=0) emit_readword_indexed((int)rdram-0x80000000,addr,th);
3034 //emit_readword_indexed((int)rdram-0x7FFFFFFC,addr,tl);
3035 #ifdef HOST_IMM_ADDR32
3036 if(c)
3037 emit_readdword_tlb(constmap[i][s]+offset,map,th,tl);
3038 else
3039 #endif
dadf55f2 3040 emit_readdword_indexed_tlb(0,a,map,th,tl);
57871462 3041 }
535d208a 3042 if(jaddr)
3043 add_stub(LOADD_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
57871462 3044 }
535d208a 3045 else
3046 inline_readstub(LOADD_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
57871462 3047 }
535d208a 3048 }
3049 //emit_storereg(rt1[i],tl); // DEBUG
57871462 3050 //if(opcode[i]==0x23)
3051 //if(opcode[i]==0x24)
3052 //if(opcode[i]==0x23||opcode[i]==0x24)
3053 /*if(opcode[i]==0x21||opcode[i]==0x23||opcode[i]==0x24)
3054 {
3055 //emit_pusha();
3056 save_regs(0x100f);
3057 emit_readword((int)&last_count,ECX);
3058 #ifdef __i386__
3059 if(get_reg(i_regs->regmap,CCREG)<0)
3060 emit_loadreg(CCREG,HOST_CCREG);
3061 emit_add(HOST_CCREG,ECX,HOST_CCREG);
3062 emit_addimm(HOST_CCREG,2*ccadj[i],HOST_CCREG);
3063 emit_writeword(HOST_CCREG,(int)&Count);
3064 #endif
3065 #ifdef __arm__
3066 if(get_reg(i_regs->regmap,CCREG)<0)
3067 emit_loadreg(CCREG,0);
3068 else
3069 emit_mov(HOST_CCREG,0);
3070 emit_add(0,ECX,0);
3071 emit_addimm(0,2*ccadj[i],0);
3072 emit_writeword(0,(int)&Count);
3073 #endif
3074 emit_call((int)memdebug);
3075 //emit_popa();
3076 restore_regs(0x100f);
3077 }/**/
3078}
3079
3080#ifndef loadlr_assemble
3081void loadlr_assemble(int i,struct regstat *i_regs)
3082{
3083 printf("Need loadlr_assemble for this architecture.\n");
3084 exit(1);
3085}
3086#endif
3087
3088void store_assemble(int i,struct regstat *i_regs)
3089{
3090 int s,th,tl,map=-1;
3091 int addr,temp;
3092 int offset;
3093 int jaddr=0,jaddr2,type;
666a299d 3094 int memtarget=0,c=0;
57871462 3095 int agr=AGEN1+(i&1);
b1570849 3096 int faststore_reg_override=0;
57871462 3097 u_int hr,reglist=0;
3098 th=get_reg(i_regs->regmap,rs2[i]|64);
3099 tl=get_reg(i_regs->regmap,rs2[i]);
3100 s=get_reg(i_regs->regmap,rs1[i]);
3101 temp=get_reg(i_regs->regmap,agr);
3102 if(temp<0) temp=get_reg(i_regs->regmap,-1);
3103 offset=imm[i];
3104 if(s>=0) {
3105 c=(i_regs->wasconst>>s)&1;
af4ee1fe 3106 if(c) {
3107 memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
3108 if(using_tlb&&((signed int)(constmap[i][s]+offset))>=(signed int)0xC0000000) memtarget=1;
3109 }
57871462 3110 }
3111 assert(tl>=0);
3112 assert(temp>=0);
3113 for(hr=0;hr<HOST_REGS;hr++) {
3114 if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
3115 }
3116 if(i_regs->regmap[HOST_CCREG]==CCREG) reglist&=~(1<<HOST_CCREG);
3117 if(offset||s<0||c) addr=temp;
3118 else addr=s;
3119 if(!using_tlb) {
3120 if(!c) {
dadf55f2 3121 #ifdef PCSX
3122 if(sp_in_mirror&&rs1[i]==29) {
3123 emit_andimm(addr,~0x00e00000,HOST_TEMPREG);
3124 emit_cmpimm(HOST_TEMPREG,RAM_SIZE);
b1570849 3125 faststore_reg_override=HOST_TEMPREG;
dadf55f2 3126 }
3127 else
3128 #endif
57871462 3129 #ifdef R29_HACK
3130 // Strmnnrmn's speed hack
4cb76aa4 3131 if(rs1[i]!=29||start<0x80001000||start>=0x80000000+RAM_SIZE)
57871462 3132 #endif
4cb76aa4 3133 emit_cmpimm(addr,RAM_SIZE);
57871462 3134 #ifdef DESTRUCTIVE_SHIFT
3135 if(s==addr) emit_mov(s,temp);
3136 #endif
3137 #ifdef R29_HACK
dadf55f2 3138 memtarget=1;
4cb76aa4 3139 if(rs1[i]!=29||start<0x80001000||start>=0x80000000+RAM_SIZE)
57871462 3140 #endif
3141 {
3142 jaddr=(int)out;
3143 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
3144 // Hint to branch predictor that the branch is unlikely to be taken
3145 if(rs1[i]>=28)
3146 emit_jno_unlikely(0);
3147 else
3148 #endif
3149 emit_jno(0);
3150 }
3151 }
3152 }else{ // using tlb
3153 int x=0;
3154 if (opcode[i]==0x28) x=3; // SB
3155 if (opcode[i]==0x29) x=2; // SH
3156 map=get_reg(i_regs->regmap,TLREG);
3157 assert(map>=0);
ea3d2e6e 3158 reglist&=~(1<<map);
57871462 3159 map=do_tlb_w(addr,temp,map,x,c,constmap[i][s]+offset);
3160 do_tlb_w_branch(map,c,constmap[i][s]+offset,&jaddr);
3161 }
3162
3163 if (opcode[i]==0x28) { // SB
3164 if(!c||memtarget) {
97a238a6 3165 int x=0,a=temp;
2002a1db 3166#ifdef BIG_ENDIAN_MIPS
57871462 3167 if(!c) emit_xorimm(addr,3,temp);
3168 else x=((constmap[i][s]+offset)^3)-(constmap[i][s]+offset);
2002a1db 3169#else
97a238a6 3170 if(!c) a=addr;
dadf55f2 3171#endif
b1570849 3172 if(faststore_reg_override) a=faststore_reg_override;
57871462 3173 //gen_tlb_addr_w(temp,map);
3174 //emit_writebyte_indexed(tl,(int)rdram-0x80000000,temp);
97a238a6 3175 emit_writebyte_indexed_tlb(tl,x,a,map,a);
57871462 3176 }
3177 type=STOREB_STUB;
3178 }
3179 if (opcode[i]==0x29) { // SH
3180 if(!c||memtarget) {
97a238a6 3181 int x=0,a=temp;
2002a1db 3182#ifdef BIG_ENDIAN_MIPS
57871462 3183 if(!c) emit_xorimm(addr,2,temp);
3184 else x=((constmap[i][s]+offset)^2)-(constmap[i][s]+offset);
2002a1db 3185#else
97a238a6 3186 if(!c) a=addr;
dadf55f2 3187#endif
b1570849 3188 if(faststore_reg_override) a=faststore_reg_override;
57871462 3189 //#ifdef
3190 //emit_writehword_indexed_tlb(tl,x,temp,map,temp);
3191 //#else
3192 if(map>=0) {
97a238a6 3193 gen_tlb_addr_w(a,map);
3194 emit_writehword_indexed(tl,x,a);
57871462 3195 }else
97a238a6 3196 emit_writehword_indexed(tl,(int)rdram-0x80000000+x,a);
57871462 3197 }
3198 type=STOREH_STUB;
3199 }
3200 if (opcode[i]==0x2B) { // SW
dadf55f2 3201 if(!c||memtarget) {
3202 int a=addr;
b1570849 3203 if(faststore_reg_override) a=faststore_reg_override;
57871462 3204 //emit_writeword_indexed(tl,(int)rdram-0x80000000,addr);
dadf55f2 3205 emit_writeword_indexed_tlb(tl,0,a,map,temp);
3206 }
57871462 3207 type=STOREW_STUB;
3208 }
3209 if (opcode[i]==0x3F) { // SD
3210 if(!c||memtarget) {
dadf55f2 3211 int a=addr;
b1570849 3212 if(faststore_reg_override) a=faststore_reg_override;
57871462 3213 if(rs2[i]) {
3214 assert(th>=0);
3215 //emit_writeword_indexed(th,(int)rdram-0x80000000,addr);
3216 //emit_writeword_indexed(tl,(int)rdram-0x7FFFFFFC,addr);
dadf55f2 3217 emit_writedword_indexed_tlb(th,tl,0,a,map,temp);
57871462 3218 }else{
3219 // Store zero
3220 //emit_writeword_indexed(tl,(int)rdram-0x80000000,temp);
3221 //emit_writeword_indexed(tl,(int)rdram-0x7FFFFFFC,temp);
dadf55f2 3222 emit_writedword_indexed_tlb(tl,tl,0,a,map,temp);
57871462 3223 }
3224 }
3225 type=STORED_STUB;
3226 }
57871462 3227 if(!using_tlb) {
3228 if(!c||memtarget) {
3229 #ifdef DESTRUCTIVE_SHIFT
3230 // The x86 shift operation is 'destructive'; it overwrites the
3231 // source register, so we need to make a copy first and use that.
3232 addr=temp;
3233 #endif
3234 #if defined(HOST_IMM8)
3235 int ir=get_reg(i_regs->regmap,INVCP);
3236 assert(ir>=0);
3237 emit_cmpmem_indexedsr12_reg(ir,addr,1);
3238 #else
3239 emit_cmpmem_indexedsr12_imm((int)invalid_code,addr,1);
3240 #endif
0bbd1454 3241 #if defined(HAVE_CONDITIONAL_CALL) && !defined(DESTRUCTIVE_SHIFT)
3242 emit_callne(invalidate_addr_reg[addr]);
3243 #else
57871462 3244 jaddr2=(int)out;
3245 emit_jne(0);
3246 add_stub(INVCODE_STUB,jaddr2,(int)out,reglist|(1<<HOST_CCREG),addr,0,0,0);
0bbd1454 3247 #endif
57871462 3248 }
3249 }
3eaa7048 3250 if(jaddr) {
3251 add_stub(type,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
3252 } else if(c&&!memtarget) {
3253 inline_writestub(type,i,constmap[i][s]+offset,i_regs->regmap,rs2[i],ccadj[i],reglist);
3254 }
57871462 3255 //if(opcode[i]==0x2B || opcode[i]==0x3F)
3256 //if(opcode[i]==0x2B || opcode[i]==0x28)
3257 //if(opcode[i]==0x2B || opcode[i]==0x29)
3258 //if(opcode[i]==0x2B)
3259 /*if(opcode[i]==0x2B || opcode[i]==0x28 || opcode[i]==0x29 || opcode[i]==0x3F)
3260 {
28d74ee8 3261 #ifdef __i386__
3262 emit_pusha();
3263 #endif
3264 #ifdef __arm__
57871462 3265 save_regs(0x100f);
28d74ee8 3266 #endif
57871462 3267 emit_readword((int)&last_count,ECX);
3268 #ifdef __i386__
3269 if(get_reg(i_regs->regmap,CCREG)<0)
3270 emit_loadreg(CCREG,HOST_CCREG);
3271 emit_add(HOST_CCREG,ECX,HOST_CCREG);
3272 emit_addimm(HOST_CCREG,2*ccadj[i],HOST_CCREG);
3273 emit_writeword(HOST_CCREG,(int)&Count);
3274 #endif
3275 #ifdef __arm__
3276 if(get_reg(i_regs->regmap,CCREG)<0)
3277 emit_loadreg(CCREG,0);
3278 else
3279 emit_mov(HOST_CCREG,0);
3280 emit_add(0,ECX,0);
3281 emit_addimm(0,2*ccadj[i],0);
3282 emit_writeword(0,(int)&Count);
3283 #endif
3284 emit_call((int)memdebug);
28d74ee8 3285 #ifdef __i386__
3286 emit_popa();
3287 #endif
3288 #ifdef __arm__
57871462 3289 restore_regs(0x100f);
28d74ee8 3290 #endif
57871462 3291 }/**/
3292}
3293
3294void storelr_assemble(int i,struct regstat *i_regs)
3295{
3296 int s,th,tl;
3297 int temp;
3298 int temp2;
3299 int offset;
3300 int jaddr=0,jaddr2;
3301 int case1,case2,case3;
3302 int done0,done1,done2;
af4ee1fe 3303 int memtarget=0,c=0;
fab5d06d 3304 int agr=AGEN1+(i&1);
57871462 3305 u_int hr,reglist=0;
3306 th=get_reg(i_regs->regmap,rs2[i]|64);
3307 tl=get_reg(i_regs->regmap,rs2[i]);
3308 s=get_reg(i_regs->regmap,rs1[i]);
fab5d06d 3309 temp=get_reg(i_regs->regmap,agr);
3310 if(temp<0) temp=get_reg(i_regs->regmap,-1);
57871462 3311 offset=imm[i];
3312 if(s>=0) {
3313 c=(i_regs->isconst>>s)&1;
af4ee1fe 3314 if(c) {
3315 memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
3316 if(using_tlb&&((signed int)(constmap[i][s]+offset))>=(signed int)0xC0000000) memtarget=1;
3317 }
57871462 3318 }
3319 assert(tl>=0);
3320 for(hr=0;hr<HOST_REGS;hr++) {
3321 if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
3322 }
535d208a 3323 assert(temp>=0);
3324 if(!using_tlb) {
3325 if(!c) {
3326 emit_cmpimm(s<0||offset?temp:s,RAM_SIZE);
3327 if(!offset&&s!=temp) emit_mov(s,temp);
3328 jaddr=(int)out;
3329 emit_jno(0);
3330 }
3331 else
3332 {
3333 if(!memtarget||!rs1[i]) {
57871462 3334 jaddr=(int)out;
3335 emit_jmp(0);
3336 }
57871462 3337 }
535d208a 3338 #ifdef RAM_OFFSET
3339 int map=get_reg(i_regs->regmap,ROREG);
3340 if(map<0) emit_loadreg(ROREG,map=HOST_TEMPREG);
3341 gen_tlb_addr_w(temp,map);
3342 #else
3343 if((u_int)rdram!=0x80000000)
3344 emit_addimm_no_flags((u_int)rdram-(u_int)0x80000000,temp);
3345 #endif
3346 }else{ // using tlb
3347 int map=get_reg(i_regs->regmap,TLREG);
3348 assert(map>=0);
ea3d2e6e 3349 reglist&=~(1<<map);
535d208a 3350 map=do_tlb_w(c||s<0||offset?temp:s,temp,map,0,c,constmap[i][s]+offset);
3351 if(!c&&!offset&&s>=0) emit_mov(s,temp);
3352 do_tlb_w_branch(map,c,constmap[i][s]+offset,&jaddr);
3353 if(!jaddr&&!memtarget) {
3354 jaddr=(int)out;
3355 emit_jmp(0);
57871462 3356 }
535d208a 3357 gen_tlb_addr_w(temp,map);
3358 }
3359
3360 if (opcode[i]==0x2C||opcode[i]==0x2D) { // SDL/SDR
3361 temp2=get_reg(i_regs->regmap,FTEMP);
3362 if(!rs2[i]) temp2=th=tl;
3363 }
57871462 3364
2002a1db 3365#ifndef BIG_ENDIAN_MIPS
3366 emit_xorimm(temp,3,temp);
3367#endif
535d208a 3368 emit_testimm(temp,2);
3369 case2=(int)out;
3370 emit_jne(0);
3371 emit_testimm(temp,1);
3372 case1=(int)out;
3373 emit_jne(0);
3374 // 0
3375 if (opcode[i]==0x2A) { // SWL
3376 emit_writeword_indexed(tl,0,temp);
3377 }
3378 if (opcode[i]==0x2E) { // SWR
3379 emit_writebyte_indexed(tl,3,temp);
3380 }
3381 if (opcode[i]==0x2C) { // SDL
3382 emit_writeword_indexed(th,0,temp);
3383 if(rs2[i]) emit_mov(tl,temp2);
3384 }
3385 if (opcode[i]==0x2D) { // SDR
3386 emit_writebyte_indexed(tl,3,temp);
3387 if(rs2[i]) emit_shldimm(th,tl,24,temp2);
3388 }
3389 done0=(int)out;
3390 emit_jmp(0);
3391 // 1
3392 set_jump_target(case1,(int)out);
3393 if (opcode[i]==0x2A) { // SWL
3394 // Write 3 msb into three least significant bytes
3395 if(rs2[i]) emit_rorimm(tl,8,tl);
3396 emit_writehword_indexed(tl,-1,temp);
3397 if(rs2[i]) emit_rorimm(tl,16,tl);
3398 emit_writebyte_indexed(tl,1,temp);
3399 if(rs2[i]) emit_rorimm(tl,8,tl);
3400 }
3401 if (opcode[i]==0x2E) { // SWR
3402 // Write two lsb into two most significant bytes
3403 emit_writehword_indexed(tl,1,temp);
3404 }
3405 if (opcode[i]==0x2C) { // SDL
3406 if(rs2[i]) emit_shrdimm(tl,th,8,temp2);
3407 // Write 3 msb into three least significant bytes
3408 if(rs2[i]) emit_rorimm(th,8,th);
3409 emit_writehword_indexed(th,-1,temp);
3410 if(rs2[i]) emit_rorimm(th,16,th);
3411 emit_writebyte_indexed(th,1,temp);
3412 if(rs2[i]) emit_rorimm(th,8,th);
3413 }
3414 if (opcode[i]==0x2D) { // SDR
3415 if(rs2[i]) emit_shldimm(th,tl,16,temp2);
3416 // Write two lsb into two most significant bytes
3417 emit_writehword_indexed(tl,1,temp);
3418 }
3419 done1=(int)out;
3420 emit_jmp(0);
3421 // 2
3422 set_jump_target(case2,(int)out);
3423 emit_testimm(temp,1);
3424 case3=(int)out;
3425 emit_jne(0);
3426 if (opcode[i]==0x2A) { // SWL
3427 // Write two msb into two least significant bytes
3428 if(rs2[i]) emit_rorimm(tl,16,tl);
3429 emit_writehword_indexed(tl,-2,temp);
3430 if(rs2[i]) emit_rorimm(tl,16,tl);
3431 }
3432 if (opcode[i]==0x2E) { // SWR
3433 // Write 3 lsb into three most significant bytes
3434 emit_writebyte_indexed(tl,-1,temp);
3435 if(rs2[i]) emit_rorimm(tl,8,tl);
3436 emit_writehword_indexed(tl,0,temp);
3437 if(rs2[i]) emit_rorimm(tl,24,tl);
3438 }
3439 if (opcode[i]==0x2C) { // SDL
3440 if(rs2[i]) emit_shrdimm(tl,th,16,temp2);
3441 // Write two msb into two least significant bytes
3442 if(rs2[i]) emit_rorimm(th,16,th);
3443 emit_writehword_indexed(th,-2,temp);
3444 if(rs2[i]) emit_rorimm(th,16,th);
3445 }
3446 if (opcode[i]==0x2D) { // SDR
3447 if(rs2[i]) emit_shldimm(th,tl,8,temp2);
3448 // Write 3 lsb into three most significant bytes
3449 emit_writebyte_indexed(tl,-1,temp);
3450 if(rs2[i]) emit_rorimm(tl,8,tl);
3451 emit_writehword_indexed(tl,0,temp);
3452 if(rs2[i]) emit_rorimm(tl,24,tl);
3453 }
3454 done2=(int)out;
3455 emit_jmp(0);
3456 // 3
3457 set_jump_target(case3,(int)out);
3458 if (opcode[i]==0x2A) { // SWL
3459 // Write msb into least significant byte
3460 if(rs2[i]) emit_rorimm(tl,24,tl);
3461 emit_writebyte_indexed(tl,-3,temp);
3462 if(rs2[i]) emit_rorimm(tl,8,tl);
3463 }
3464 if (opcode[i]==0x2E) { // SWR
3465 // Write entire word
3466 emit_writeword_indexed(tl,-3,temp);
3467 }
3468 if (opcode[i]==0x2C) { // SDL
3469 if(rs2[i]) emit_shrdimm(tl,th,24,temp2);
3470 // Write msb into least significant byte
3471 if(rs2[i]) emit_rorimm(th,24,th);
3472 emit_writebyte_indexed(th,-3,temp);
3473 if(rs2[i]) emit_rorimm(th,8,th);
3474 }
3475 if (opcode[i]==0x2D) { // SDR
3476 if(rs2[i]) emit_mov(th,temp2);
3477 // Write entire word
3478 emit_writeword_indexed(tl,-3,temp);
3479 }
3480 set_jump_target(done0,(int)out);
3481 set_jump_target(done1,(int)out);
3482 set_jump_target(done2,(int)out);
3483 if (opcode[i]==0x2C) { // SDL
3484 emit_testimm(temp,4);
57871462 3485 done0=(int)out;
57871462 3486 emit_jne(0);
535d208a 3487 emit_andimm(temp,~3,temp);
3488 emit_writeword_indexed(temp2,4,temp);
3489 set_jump_target(done0,(int)out);
3490 }
3491 if (opcode[i]==0x2D) { // SDR
3492 emit_testimm(temp,4);
3493 done0=(int)out;
3494 emit_jeq(0);
3495 emit_andimm(temp,~3,temp);
3496 emit_writeword_indexed(temp2,-4,temp);
57871462 3497 set_jump_target(done0,(int)out);
57871462 3498 }
535d208a 3499 if(!c||!memtarget)
3500 add_stub(STORELR_STUB,jaddr,(int)out,i,(int)i_regs,temp,ccadj[i],reglist);
57871462 3501 if(!using_tlb) {
535d208a 3502 #ifdef RAM_OFFSET
3503 int map=get_reg(i_regs->regmap,ROREG);
3504 if(map<0) map=HOST_TEMPREG;
3505 gen_orig_addr_w(temp,map);
3506 #else
57871462 3507 emit_addimm_no_flags((u_int)0x80000000-(u_int)rdram,temp);
535d208a 3508 #endif
57871462 3509 #if defined(HOST_IMM8)
3510 int ir=get_reg(i_regs->regmap,INVCP);
3511 assert(ir>=0);
3512 emit_cmpmem_indexedsr12_reg(ir,temp,1);
3513 #else
3514 emit_cmpmem_indexedsr12_imm((int)invalid_code,temp,1);
3515 #endif
535d208a 3516 #if defined(HAVE_CONDITIONAL_CALL) && !defined(DESTRUCTIVE_SHIFT)
3517 emit_callne(invalidate_addr_reg[temp]);
3518 #else
57871462 3519 jaddr2=(int)out;
3520 emit_jne(0);
3521 add_stub(INVCODE_STUB,jaddr2,(int)out,reglist|(1<<HOST_CCREG),temp,0,0,0);
535d208a 3522 #endif
57871462 3523 }
3524 /*
3525 emit_pusha();
3526 //save_regs(0x100f);
3527 emit_readword((int)&last_count,ECX);
3528 if(get_reg(i_regs->regmap,CCREG)<0)
3529 emit_loadreg(CCREG,HOST_CCREG);
3530 emit_add(HOST_CCREG,ECX,HOST_CCREG);
3531 emit_addimm(HOST_CCREG,2*ccadj[i],HOST_CCREG);
3532 emit_writeword(HOST_CCREG,(int)&Count);
3533 emit_call((int)memdebug);
3534 emit_popa();
3535 //restore_regs(0x100f);
3536 /**/
3537}
3538
3539void c1ls_assemble(int i,struct regstat *i_regs)
3540{
3d624f89 3541#ifndef DISABLE_COP1
57871462 3542 int s,th,tl;
3543 int temp,ar;
3544 int map=-1;
3545 int offset;
3546 int c=0;
3547 int jaddr,jaddr2=0,jaddr3,type;
3548 int agr=AGEN1+(i&1);
3549 u_int hr,reglist=0;
3550 th=get_reg(i_regs->regmap,FTEMP|64);
3551 tl=get_reg(i_regs->regmap,FTEMP);
3552 s=get_reg(i_regs->regmap,rs1[i]);
3553 temp=get_reg(i_regs->regmap,agr);
3554 if(temp<0) temp=get_reg(i_regs->regmap,-1);
3555 offset=imm[i];
3556 assert(tl>=0);
3557 assert(rs1[i]>0);
3558 assert(temp>=0);
3559 for(hr=0;hr<HOST_REGS;hr++) {
3560 if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
3561 }
3562 if(i_regs->regmap[HOST_CCREG]==CCREG) reglist&=~(1<<HOST_CCREG);
3563 if (opcode[i]==0x31||opcode[i]==0x35) // LWC1/LDC1
3564 {
3565 // Loads use a temporary register which we need to save
3566 reglist|=1<<temp;
3567 }
3568 if (opcode[i]==0x39||opcode[i]==0x3D) // SWC1/SDC1
3569 ar=temp;
3570 else // LWC1/LDC1
3571 ar=tl;
3572 //if(s<0) emit_loadreg(rs1[i],ar); //address_generation does this now
3573 //else c=(i_regs->wasconst>>s)&1;
3574 if(s>=0) c=(i_regs->wasconst>>s)&1;
3575 // Check cop1 unusable
3576 if(!cop1_usable) {
3577 signed char rs=get_reg(i_regs->regmap,CSREG);
3578 assert(rs>=0);
3579 emit_testimm(rs,0x20000000);
3580 jaddr=(int)out;
3581 emit_jeq(0);
3582 add_stub(FP_STUB,jaddr,(int)out,i,rs,(int)i_regs,is_delayslot,0);
3583 cop1_usable=1;
3584 }
3585 if (opcode[i]==0x39) { // SWC1 (get float address)
3586 emit_readword((int)&reg_cop1_simple[(source[i]>>16)&0x1f],tl);
3587 }
3588 if (opcode[i]==0x3D) { // SDC1 (get double address)
3589 emit_readword((int)&reg_cop1_double[(source[i]>>16)&0x1f],tl);
3590 }
3591 // Generate address + offset
3592 if(!using_tlb) {
3593 if(!c)
4cb76aa4 3594 emit_cmpimm(offset||c||s<0?ar:s,RAM_SIZE);
57871462 3595 }
3596 else
3597 {
3598 map=get_reg(i_regs->regmap,TLREG);
3599 assert(map>=0);
ea3d2e6e 3600 reglist&=~(1<<map);
57871462 3601 if (opcode[i]==0x31||opcode[i]==0x35) { // LWC1/LDC1
3602 map=do_tlb_r(offset||c||s<0?ar:s,ar,map,0,-1,-1,c,constmap[i][s]+offset);
3603 }
3604 if (opcode[i]==0x39||opcode[i]==0x3D) { // SWC1/SDC1
3605 map=do_tlb_w(offset||c||s<0?ar:s,ar,map,0,c,constmap[i][s]+offset);
3606 }
3607 }
3608 if (opcode[i]==0x39) { // SWC1 (read float)
3609 emit_readword_indexed(0,tl,tl);
3610 }
3611 if (opcode[i]==0x3D) { // SDC1 (read double)
3612 emit_readword_indexed(4,tl,th);
3613 emit_readword_indexed(0,tl,tl);
3614 }
3615 if (opcode[i]==0x31) { // LWC1 (get target address)
3616 emit_readword((int)&reg_cop1_simple[(source[i]>>16)&0x1f],temp);
3617 }
3618 if (opcode[i]==0x35) { // LDC1 (get target address)
3619 emit_readword((int)&reg_cop1_double[(source[i]>>16)&0x1f],temp);
3620 }
3621 if(!using_tlb) {
3622 if(!c) {
3623 jaddr2=(int)out;
3624 emit_jno(0);
3625 }
4cb76aa4 3626 else if(((signed int)(constmap[i][s]+offset))>=(signed int)0x80000000+RAM_SIZE) {
57871462 3627 jaddr2=(int)out;
3628 emit_jmp(0); // inline_readstub/inline_writestub? Very rare case
3629 }
3630 #ifdef DESTRUCTIVE_SHIFT
3631 if (opcode[i]==0x39||opcode[i]==0x3D) { // SWC1/SDC1
3632 if(!offset&&!c&&s>=0) emit_mov(s,ar);
3633 }
3634 #endif
3635 }else{
3636 if (opcode[i]==0x31||opcode[i]==0x35) { // LWC1/LDC1
3637 do_tlb_r_branch(map,c,constmap[i][s]+offset,&jaddr2);
3638 }
3639 if (opcode[i]==0x39||opcode[i]==0x3D) { // SWC1/SDC1
3640 do_tlb_w_branch(map,c,constmap[i][s]+offset,&jaddr2);
3641 }
3642 }
3643 if (opcode[i]==0x31) { // LWC1
3644 //if(s>=0&&!c&&!offset) emit_mov(s,tl);
3645 //gen_tlb_addr_r(ar,map);
3646 //emit_readword_indexed((int)rdram-0x80000000,tl,tl);
3647 #ifdef HOST_IMM_ADDR32
3648 if(c) emit_readword_tlb(constmap[i][s]+offset,map,tl);
3649 else
3650 #endif
3651 emit_readword_indexed_tlb(0,offset||c||s<0?tl:s,map,tl);
3652 type=LOADW_STUB;
3653 }
3654 if (opcode[i]==0x35) { // LDC1
3655 assert(th>=0);
3656 //if(s>=0&&!c&&!offset) emit_mov(s,tl);
3657 //gen_tlb_addr_r(ar,map);
3658 //emit_readword_indexed((int)rdram-0x80000000,tl,th);
3659 //emit_readword_indexed((int)rdram-0x7FFFFFFC,tl,tl);
3660 #ifdef HOST_IMM_ADDR32
3661 if(c) emit_readdword_tlb(constmap[i][s]+offset,map,th,tl);
3662 else
3663 #endif
3664 emit_readdword_indexed_tlb(0,offset||c||s<0?tl:s,map,th,tl);
3665 type=LOADD_STUB;
3666 }
3667 if (opcode[i]==0x39) { // SWC1
3668 //emit_writeword_indexed(tl,(int)rdram-0x80000000,temp);
3669 emit_writeword_indexed_tlb(tl,0,offset||c||s<0?temp:s,map,temp);
3670 type=STOREW_STUB;
3671 }
3672 if (opcode[i]==0x3D) { // SDC1
3673 assert(th>=0);
3674 //emit_writeword_indexed(th,(int)rdram-0x80000000,temp);
3675 //emit_writeword_indexed(tl,(int)rdram-0x7FFFFFFC,temp);
3676 emit_writedword_indexed_tlb(th,tl,0,offset||c||s<0?temp:s,map,temp);
3677 type=STORED_STUB;
3678 }
3679 if(!using_tlb) {
3680 if (opcode[i]==0x39||opcode[i]==0x3D) { // SWC1/SDC1
3681 #ifndef DESTRUCTIVE_SHIFT
3682 temp=offset||c||s<0?ar:s;
3683 #endif
3684 #if defined(HOST_IMM8)
3685 int ir=get_reg(i_regs->regmap,INVCP);
3686 assert(ir>=0);
3687 emit_cmpmem_indexedsr12_reg(ir,temp,1);
3688 #else
3689 emit_cmpmem_indexedsr12_imm((int)invalid_code,temp,1);
3690 #endif
0bbd1454 3691 #if defined(HAVE_CONDITIONAL_CALL) && !defined(DESTRUCTIVE_SHIFT)
3692 emit_callne(invalidate_addr_reg[temp]);
3693 #else
57871462 3694 jaddr3=(int)out;
3695 emit_jne(0);
3696 add_stub(INVCODE_STUB,jaddr3,(int)out,reglist|(1<<HOST_CCREG),temp,0,0,0);
0bbd1454 3697 #endif
57871462 3698 }
3699 }
3700 if(jaddr2) add_stub(type,jaddr2,(int)out,i,offset||c||s<0?ar:s,(int)i_regs,ccadj[i],reglist);
3701 if (opcode[i]==0x31) { // LWC1 (write float)
3702 emit_writeword_indexed(tl,0,temp);
3703 }
3704 if (opcode[i]==0x35) { // LDC1 (write double)
3705 emit_writeword_indexed(th,4,temp);
3706 emit_writeword_indexed(tl,0,temp);
3707 }
3708 //if(opcode[i]==0x39)
3709 /*if(opcode[i]==0x39||opcode[i]==0x31)
3710 {
3711 emit_pusha();
3712 emit_readword((int)&last_count,ECX);
3713 if(get_reg(i_regs->regmap,CCREG)<0)
3714 emit_loadreg(CCREG,HOST_CCREG);
3715 emit_add(HOST_CCREG,ECX,HOST_CCREG);
3716 emit_addimm(HOST_CCREG,2*ccadj[i],HOST_CCREG);
3717 emit_writeword(HOST_CCREG,(int)&Count);
3718 emit_call((int)memdebug);
3719 emit_popa();
3720 }/**/
3d624f89 3721#else
3722 cop1_unusable(i, i_regs);
3723#endif
57871462 3724}
3725
b9b61529 3726void c2ls_assemble(int i,struct regstat *i_regs)
3727{
3728 int s,tl;
3729 int ar;
3730 int offset;
1fd1aceb 3731 int memtarget=0,c=0;
c2e3bd42 3732 int jaddr2=0,jaddr3,type;
b9b61529 3733 int agr=AGEN1+(i&1);
3734 u_int hr,reglist=0;
3735 u_int copr=(source[i]>>16)&0x1f;
3736 s=get_reg(i_regs->regmap,rs1[i]);
3737 tl=get_reg(i_regs->regmap,FTEMP);
3738 offset=imm[i];
3739 assert(rs1[i]>0);
3740 assert(tl>=0);
3741 assert(!using_tlb);
3742
3743 for(hr=0;hr<HOST_REGS;hr++) {
3744 if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
3745 }
3746 if(i_regs->regmap[HOST_CCREG]==CCREG)
3747 reglist&=~(1<<HOST_CCREG);
3748
3749 // get the address
3750 if (opcode[i]==0x3a) { // SWC2
3751 ar=get_reg(i_regs->regmap,agr);
3752 if(ar<0) ar=get_reg(i_regs->regmap,-1);
3753 reglist|=1<<ar;
3754 } else { // LWC2
3755 ar=tl;
3756 }
1fd1aceb 3757 if(s>=0) c=(i_regs->wasconst>>s)&1;
3758 memtarget=c&&(((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE);
b9b61529 3759 if (!offset&&!c&&s>=0) ar=s;
3760 assert(ar>=0);
3761
3762 if (opcode[i]==0x3a) { // SWC2
3763 cop2_get_dreg(copr,tl,HOST_TEMPREG);
1fd1aceb 3764 type=STOREW_STUB;
b9b61529 3765 }
1fd1aceb 3766 else
b9b61529 3767 type=LOADW_STUB;
1fd1aceb 3768
3769 if(c&&!memtarget) {
3770 jaddr2=(int)out;
3771 emit_jmp(0); // inline_readstub/inline_writestub?
b9b61529 3772 }
1fd1aceb 3773 else {
3774 if(!c) {
3775 emit_cmpimm(offset||c||s<0?ar:s,RAM_SIZE);
3776 jaddr2=(int)out;
3777 emit_jno(0);
3778 }
3779 if (opcode[i]==0x32) { // LWC2
3780 #ifdef HOST_IMM_ADDR32
3781 if(c) emit_readword_tlb(constmap[i][s]+offset,-1,tl);
3782 else
3783 #endif
3784 emit_readword_indexed(0,ar,tl);
3785 }
3786 if (opcode[i]==0x3a) { // SWC2
3787 #ifdef DESTRUCTIVE_SHIFT
3788 if(!offset&&!c&&s>=0) emit_mov(s,ar);
3789 #endif
3790 emit_writeword_indexed(tl,0,ar);
3791 }
b9b61529 3792 }
3793 if(jaddr2)
3794 add_stub(type,jaddr2,(int)out,i,ar,(int)i_regs,ccadj[i],reglist);
3795 if (opcode[i]==0x3a) { // SWC2
3796#if defined(HOST_IMM8)
3797 int ir=get_reg(i_regs->regmap,INVCP);
3798 assert(ir>=0);
3799 emit_cmpmem_indexedsr12_reg(ir,ar,1);
3800#else
3801 emit_cmpmem_indexedsr12_imm((int)invalid_code,ar,1);
3802#endif
0bbd1454 3803 #if defined(HAVE_CONDITIONAL_CALL) && !defined(DESTRUCTIVE_SHIFT)
3804 emit_callne(invalidate_addr_reg[ar]);
3805 #else
b9b61529 3806 jaddr3=(int)out;
3807 emit_jne(0);
3808 add_stub(INVCODE_STUB,jaddr3,(int)out,reglist|(1<<HOST_CCREG),ar,0,0,0);
0bbd1454 3809 #endif
b9b61529 3810 }
3811 if (opcode[i]==0x32) { // LWC2
3812 cop2_put_dreg(copr,tl,HOST_TEMPREG);
3813 }
3814}
3815
57871462 3816#ifndef multdiv_assemble
3817void multdiv_assemble(int i,struct regstat *i_regs)
3818{
3819 printf("Need multdiv_assemble for this architecture.\n");
3820 exit(1);
3821}
3822#endif
3823
3824void mov_assemble(int i,struct regstat *i_regs)
3825{
3826 //if(opcode2[i]==0x10||opcode2[i]==0x12) { // MFHI/MFLO
3827 //if(opcode2[i]==0x11||opcode2[i]==0x13) { // MTHI/MTLO
57871462 3828 if(rt1[i]) {
3829 signed char sh,sl,th,tl;
3830 th=get_reg(i_regs->regmap,rt1[i]|64);
3831 tl=get_reg(i_regs->regmap,rt1[i]);
3832 //assert(tl>=0);
3833 if(tl>=0) {
3834 sh=get_reg(i_regs->regmap,rs1[i]|64);
3835 sl=get_reg(i_regs->regmap,rs1[i]);
3836 if(sl>=0) emit_mov(sl,tl);
3837 else emit_loadreg(rs1[i],tl);
3838 if(th>=0) {
3839 if(sh>=0) emit_mov(sh,th);
3840 else emit_loadreg(rs1[i]|64,th);
3841 }
3842 }
3843 }
3844}
3845
3846#ifndef fconv_assemble
3847void fconv_assemble(int i,struct regstat *i_regs)
3848{
3849 printf("Need fconv_assemble for this architecture.\n");
3850 exit(1);
3851}
3852#endif
3853
3854#if 0
3855void float_assemble(int i,struct regstat *i_regs)
3856{
3857 printf("Need float_assemble for this architecture.\n");
3858 exit(1);
3859}
3860#endif
3861
3862void syscall_assemble(int i,struct regstat *i_regs)
3863{
3864 signed char ccreg=get_reg(i_regs->regmap,CCREG);
3865 assert(ccreg==HOST_CCREG);
3866 assert(!is_delayslot);
3867 emit_movimm(start+i*4,EAX); // Get PC
3868 emit_addimm(HOST_CCREG,CLOCK_DIVIDER*ccadj[i],HOST_CCREG); // CHECK: is this right? There should probably be an extra cycle...
7139f3c8 3869 emit_jmp((int)jump_syscall_hle); // XXX
3870}
3871
3872void hlecall_assemble(int i,struct regstat *i_regs)
3873{
3874 signed char ccreg=get_reg(i_regs->regmap,CCREG);
3875 assert(ccreg==HOST_CCREG);
3876 assert(!is_delayslot);
3877 emit_movimm(start+i*4+4,0); // Get PC
67ba0fb4 3878 emit_movimm((int)psxHLEt[source[i]&7],1);
7139f3c8 3879 emit_addimm(HOST_CCREG,CLOCK_DIVIDER*ccadj[i],HOST_CCREG); // XXX
67ba0fb4 3880 emit_jmp((int)jump_hlecall);
57871462 3881}
3882
1e973cb0 3883void intcall_assemble(int i,struct regstat *i_regs)
3884{
3885 signed char ccreg=get_reg(i_regs->regmap,CCREG);
3886 assert(ccreg==HOST_CCREG);
3887 assert(!is_delayslot);
3888 emit_movimm(start+i*4,0); // Get PC
3889 emit_addimm(HOST_CCREG,CLOCK_DIVIDER*ccadj[i],HOST_CCREG);
3890 emit_jmp((int)jump_intcall);
3891}
3892
57871462 3893void ds_assemble(int i,struct regstat *i_regs)
3894{
3895 is_delayslot=1;
3896 switch(itype[i]) {
3897 case ALU:
3898 alu_assemble(i,i_regs);break;
3899 case IMM16:
3900 imm16_assemble(i,i_regs);break;
3901 case SHIFT:
3902 shift_assemble(i,i_regs);break;
3903 case SHIFTIMM:
3904 shiftimm_assemble(i,i_regs);break;
3905 case LOAD:
3906 load_assemble(i,i_regs);break;
3907 case LOADLR:
3908 loadlr_assemble(i,i_regs);break;
3909 case STORE:
3910 store_assemble(i,i_regs);break;
3911 case STORELR:
3912 storelr_assemble(i,i_regs);break;
3913 case COP0:
3914 cop0_assemble(i,i_regs);break;
3915 case COP1:
3916 cop1_assemble(i,i_regs);break;
3917 case C1LS:
3918 c1ls_assemble(i,i_regs);break;
b9b61529 3919 case COP2:
3920 cop2_assemble(i,i_regs);break;
3921 case C2LS:
3922 c2ls_assemble(i,i_regs);break;
3923 case C2OP:
3924 c2op_assemble(i,i_regs);break;
57871462 3925 case FCONV:
3926 fconv_assemble(i,i_regs);break;
3927 case FLOAT:
3928 float_assemble(i,i_regs);break;
3929 case FCOMP:
3930 fcomp_assemble(i,i_regs);break;
3931 case MULTDIV:
3932 multdiv_assemble(i,i_regs);break;
3933 case MOV:
3934 mov_assemble(i,i_regs);break;
3935 case SYSCALL:
7139f3c8 3936 case HLECALL:
1e973cb0 3937 case INTCALL:
57871462 3938 case SPAN:
3939 case UJUMP:
3940 case RJUMP:
3941 case CJUMP:
3942 case SJUMP:
3943 case FJUMP:
3944 printf("Jump in the delay slot. This is probably a bug.\n");
3945 }
3946 is_delayslot=0;
3947}
3948
3949// Is the branch target a valid internal jump?
3950int internal_branch(uint64_t i_is32,int addr)
3951{
3952 if(addr&1) return 0; // Indirect (register) jump
3953 if(addr>=start && addr<start+slen*4-4)
3954 {
3955 int t=(addr-start)>>2;
3956 // Delay slots are not valid branch targets
3957 //if(t>0&&(itype[t-1]==RJUMP||itype[t-1]==UJUMP||itype[t-1]==CJUMP||itype[t-1]==SJUMP||itype[t-1]==FJUMP)) return 0;
3958 // 64 -> 32 bit transition requires a recompile
3959 /*if(is32[t]&~unneeded_reg_upper[t]&~i_is32)
3960 {
3961 if(requires_32bit[t]&~i_is32) printf("optimizable: no\n");
3962 else printf("optimizable: yes\n");
3963 }*/
3964 //if(is32[t]&~unneeded_reg_upper[t]&~i_is32) return 0;
a28c6ce8 3965#ifndef FORCE32
57871462 3966 if(requires_32bit[t]&~i_is32) return 0;
a28c6ce8 3967 else
3968#endif
3969 return 1;
57871462 3970 }
3971 return 0;
3972}
3973
3974#ifndef wb_invalidate
3975void wb_invalidate(signed char pre[],signed char entry[],uint64_t dirty,uint64_t is32,
3976 uint64_t u,uint64_t uu)
3977{
3978 int hr;
3979 for(hr=0;hr<HOST_REGS;hr++) {
3980 if(hr!=EXCLUDE_REG) {
3981 if(pre[hr]!=entry[hr]) {
3982 if(pre[hr]>=0) {
3983 if((dirty>>hr)&1) {
3984 if(get_reg(entry,pre[hr])<0) {
3985 if(pre[hr]<64) {
3986 if(!((u>>pre[hr])&1)) {
3987 emit_storereg(pre[hr],hr);
3988 if( ((is32>>pre[hr])&1) && !((uu>>pre[hr])&1) ) {
3989 emit_sarimm(hr,31,hr);
3990 emit_storereg(pre[hr]|64,hr);
3991 }
3992 }
3993 }else{
3994 if(!((uu>>(pre[hr]&63))&1) && !((is32>>(pre[hr]&63))&1)) {
3995 emit_storereg(pre[hr],hr);
3996 }
3997 }
3998 }
3999 }
4000 }
4001 }
4002 }
4003 }
4004 // Move from one register to another (no writeback)
4005 for(hr=0;hr<HOST_REGS;hr++) {
4006 if(hr!=EXCLUDE_REG) {
4007 if(pre[hr]!=entry[hr]) {
4008 if(pre[hr]>=0&&(pre[hr]&63)<TEMPREG) {
4009 int nr;
4010 if((nr=get_reg(entry,pre[hr]))>=0) {
4011 emit_mov(hr,nr);
4012 }
4013 }
4014 }
4015 }
4016 }
4017}
4018#endif
4019
4020// Load the specified registers
4021// This only loads the registers given as arguments because
4022// we don't want to load things that will be overwritten
4023void load_regs(signed char entry[],signed char regmap[],int is32,int rs1,int rs2)
4024{
4025 int hr;
4026 // Load 32-bit regs
4027 for(hr=0;hr<HOST_REGS;hr++) {
4028 if(hr!=EXCLUDE_REG&&regmap[hr]>=0) {
4029 if(entry[hr]!=regmap[hr]) {
4030 if(regmap[hr]==rs1||regmap[hr]==rs2)
4031 {
4032 if(regmap[hr]==0) {
4033 emit_zeroreg(hr);
4034 }
4035 else
4036 {
4037 emit_loadreg(regmap[hr],hr);
4038 }
4039 }
4040 }
4041 }
4042 }
4043 //Load 64-bit regs
4044 for(hr=0;hr<HOST_REGS;hr++) {
4045 if(hr!=EXCLUDE_REG&&regmap[hr]>=0) {
4046 if(entry[hr]!=regmap[hr]) {
4047 if(regmap[hr]-64==rs1||regmap[hr]-64==rs2)
4048 {
4049 assert(regmap[hr]!=64);
4050 if((is32>>(regmap[hr]&63))&1) {
4051 int lr=get_reg(regmap,regmap[hr]-64);
4052 if(lr>=0)
4053 emit_sarimm(lr,31,hr);
4054 else
4055 emit_loadreg(regmap[hr],hr);
4056 }
4057 else
4058 {
4059 emit_loadreg(regmap[hr],hr);
4060 }
4061 }
4062 }
4063 }
4064 }
4065}
4066
4067// Load registers prior to the start of a loop
4068// so that they are not loaded within the loop
4069static void loop_preload(signed char pre[],signed char entry[])
4070{
4071 int hr;
4072 for(hr=0;hr<HOST_REGS;hr++) {
4073 if(hr!=EXCLUDE_REG) {
4074 if(pre[hr]!=entry[hr]) {
4075 if(entry[hr]>=0) {
4076 if(get_reg(pre,entry[hr])<0) {
4077 assem_debug("loop preload:\n");
4078 //printf("loop preload: %d\n",hr);
4079 if(entry[hr]==0) {
4080 emit_zeroreg(hr);
4081 }
4082 else if(entry[hr]<TEMPREG)
4083 {
4084 emit_loadreg(entry[hr],hr);
4085 }
4086 else if(entry[hr]-64<TEMPREG)
4087 {
4088 emit_loadreg(entry[hr],hr);
4089 }
4090 }
4091 }
4092 }
4093 }
4094 }
4095}
4096
4097// Generate address for load/store instruction
b9b61529 4098// goes to AGEN for writes, FTEMP for LOADLR and cop1/2 loads
57871462 4099void address_generation(int i,struct regstat *i_regs,signed char entry[])
4100{
b9b61529 4101 if(itype[i]==LOAD||itype[i]==LOADLR||itype[i]==STORE||itype[i]==STORELR||itype[i]==C1LS||itype[i]==C2LS) {
5194fb95 4102 int ra=-1;
57871462 4103 int agr=AGEN1+(i&1);
4104 int mgr=MGEN1+(i&1);
4105 if(itype[i]==LOAD) {
4106 ra=get_reg(i_regs->regmap,rt1[i]);
535d208a 4107 if(ra<0) ra=get_reg(i_regs->regmap,-1);
4108 assert(ra>=0);
57871462 4109 }
4110 if(itype[i]==LOADLR) {
4111 ra=get_reg(i_regs->regmap,FTEMP);
4112 }
4113 if(itype[i]==STORE||itype[i]==STORELR) {
4114 ra=get_reg(i_regs->regmap,agr);
4115 if(ra<0) ra=get_reg(i_regs->regmap,-1);
4116 }
b9b61529 4117 if(itype[i]==C1LS||itype[i]==C2LS) {
4118 if ((opcode[i]&0x3b)==0x31||(opcode[i]&0x3b)==0x32) // LWC1/LDC1/LWC2/LDC2
57871462 4119 ra=get_reg(i_regs->regmap,FTEMP);
1fd1aceb 4120 else { // SWC1/SDC1/SWC2/SDC2
57871462 4121 ra=get_reg(i_regs->regmap,agr);
4122 if(ra<0) ra=get_reg(i_regs->regmap,-1);
4123 }
4124 }
4125 int rs=get_reg(i_regs->regmap,rs1[i]);
4126 int rm=get_reg(i_regs->regmap,TLREG);
4127 if(ra>=0) {
4128 int offset=imm[i];
4129 int c=(i_regs->wasconst>>rs)&1;
4130 if(rs1[i]==0) {
4131 // Using r0 as a base address
4132 /*if(rm>=0) {
4133 if(!entry||entry[rm]!=mgr) {
4134 generate_map_const(offset,rm);
4135 } // else did it in the previous cycle
4136 }*/
4137 if(!entry||entry[ra]!=agr) {
4138 if (opcode[i]==0x22||opcode[i]==0x26) {
4139 emit_movimm(offset&0xFFFFFFFC,ra); // LWL/LWR
4140 }else if (opcode[i]==0x1a||opcode[i]==0x1b) {
4141 emit_movimm(offset&0xFFFFFFF8,ra); // LDL/LDR
4142 }else{
4143 emit_movimm(offset,ra);
4144 }
4145 } // else did it in the previous cycle
4146 }
4147 else if(rs<0) {
4148 if(!entry||entry[ra]!=rs1[i])
4149 emit_loadreg(rs1[i],ra);
4150 //if(!entry||entry[ra]!=rs1[i])
4151 // printf("poor load scheduling!\n");
4152 }
4153 else if(c) {
4154 if(rm>=0) {
4155 if(!entry||entry[rm]!=mgr) {
b9b61529 4156 if(itype[i]==STORE||itype[i]==STORELR||(opcode[i]&0x3b)==0x39||(opcode[i]&0x3b)==0x3a) {
57871462 4157 // Stores to memory go thru the mapper to detect self-modifying
4158 // code, loads don't.
4159 if((unsigned int)(constmap[i][rs]+offset)>=0xC0000000 ||
4cb76aa4 4160 (unsigned int)(constmap[i][rs]+offset)<0x80000000+RAM_SIZE )
57871462 4161 generate_map_const(constmap[i][rs]+offset,rm);
4162 }else{
4163 if((signed int)(constmap[i][rs]+offset)>=(signed int)0xC0000000)
4164 generate_map_const(constmap[i][rs]+offset,rm);
4165 }
4166 }
4167 }
4168 if(rs1[i]!=rt1[i]||itype[i]!=LOAD) {
4169 if(!entry||entry[ra]!=agr) {
4170 if (opcode[i]==0x22||opcode[i]==0x26) {
4171 emit_movimm((constmap[i][rs]+offset)&0xFFFFFFFC,ra); // LWL/LWR
4172 }else if (opcode[i]==0x1a||opcode[i]==0x1b) {
4173 emit_movimm((constmap[i][rs]+offset)&0xFFFFFFF8,ra); // LDL/LDR
4174 }else{
4175 #ifdef HOST_IMM_ADDR32
b9b61529 4176 if((itype[i]!=LOAD&&(opcode[i]&0x3b)!=0x31&&(opcode[i]&0x3b)!=0x32) || // LWC1/LDC1/LWC2/LDC2
57871462 4177 (using_tlb&&((signed int)constmap[i][rs]+offset)>=(signed int)0xC0000000))
4178 #endif
4179 emit_movimm(constmap[i][rs]+offset,ra);
4180 }
4181 } // else did it in the previous cycle
4182 } // else load_consts already did it
4183 }
4184 if(offset&&!c&&rs1[i]) {
4185 if(rs>=0) {
4186 emit_addimm(rs,offset,ra);
4187 }else{
4188 emit_addimm(ra,offset,ra);
4189 }
4190 }
4191 }
4192 }
4193 // Preload constants for next instruction
b9b61529 4194 if(itype[i+1]==LOAD||itype[i+1]==LOADLR||itype[i+1]==STORE||itype[i+1]==STORELR||itype[i+1]==C1LS||itype[i+1]==C2LS) {
57871462 4195 int agr,ra;
4196 #ifndef HOST_IMM_ADDR32
4197 // Mapper entry
4198 agr=MGEN1+((i+1)&1);
4199 ra=get_reg(i_regs->regmap,agr);
4200 if(ra>=0) {
4201 int rs=get_reg(regs[i+1].regmap,rs1[i+1]);
4202 int offset=imm[i+1];
4203 int c=(regs[i+1].wasconst>>rs)&1;
4204 if(c) {
b9b61529 4205 if(itype[i+1]==STORE||itype[i+1]==STORELR
4206 ||(opcode[i+1]&0x3b)==0x39||(opcode[i+1]&0x3b)==0x3a) { // SWC1/SDC1, SWC2/SDC2
57871462 4207 // Stores to memory go thru the mapper to detect self-modifying
4208 // code, loads don't.
4209 if((unsigned int)(constmap[i+1][rs]+offset)>=0xC0000000 ||
4cb76aa4 4210 (unsigned int)(constmap[i+1][rs]+offset)<0x80000000+RAM_SIZE )
57871462 4211 generate_map_const(constmap[i+1][rs]+offset,ra);
4212 }else{
4213 if((signed int)(constmap[i+1][rs]+offset)>=(signed int)0xC0000000)
4214 generate_map_const(constmap[i+1][rs]+offset,ra);
4215 }
4216 }
4217 /*else if(rs1[i]==0) {
4218 generate_map_const(offset,ra);
4219 }*/
4220 }
4221 #endif
4222 // Actual address
4223 agr=AGEN1+((i+1)&1);
4224 ra=get_reg(i_regs->regmap,agr);
4225 if(ra>=0) {
4226 int rs=get_reg(regs[i+1].regmap,rs1[i+1]);
4227 int offset=imm[i+1];
4228 int c=(regs[i+1].wasconst>>rs)&1;
4229 if(c&&(rs1[i+1]!=rt1[i+1]||itype[i+1]!=LOAD)) {
4230 if (opcode[i+1]==0x22||opcode[i+1]==0x26) {
4231 emit_movimm((constmap[i+1][rs]+offset)&0xFFFFFFFC,ra); // LWL/LWR
4232 }else if (opcode[i+1]==0x1a||opcode[i+1]==0x1b) {
4233 emit_movimm((constmap[i+1][rs]+offset)&0xFFFFFFF8,ra); // LDL/LDR
4234 }else{
4235 #ifdef HOST_IMM_ADDR32
b9b61529 4236 if((itype[i+1]!=LOAD&&(opcode[i+1]&0x3b)!=0x31&&(opcode[i+1]&0x3b)!=0x32) || // LWC1/LDC1/LWC2/LDC2
57871462 4237 (using_tlb&&((signed int)constmap[i+1][rs]+offset)>=(signed int)0xC0000000))
4238 #endif
4239 emit_movimm(constmap[i+1][rs]+offset,ra);
4240 }
4241 }
4242 else if(rs1[i+1]==0) {
4243 // Using r0 as a base address
4244 if (opcode[i+1]==0x22||opcode[i+1]==0x26) {
4245 emit_movimm(offset&0xFFFFFFFC,ra); // LWL/LWR
4246 }else if (opcode[i+1]==0x1a||opcode[i+1]==0x1b) {
4247 emit_movimm(offset&0xFFFFFFF8,ra); // LDL/LDR
4248 }else{
4249 emit_movimm(offset,ra);
4250 }
4251 }
4252 }
4253 }
4254}
4255
4256int get_final_value(int hr, int i, int *value)
4257{
4258 int reg=regs[i].regmap[hr];
4259 while(i<slen-1) {
4260 if(regs[i+1].regmap[hr]!=reg) break;
4261 if(!((regs[i+1].isconst>>hr)&1)) break;
4262 if(bt[i+1]) break;
4263 i++;
4264 }
4265 if(i<slen-1) {
4266 if(itype[i]==UJUMP||itype[i]==RJUMP||itype[i]==CJUMP||itype[i]==SJUMP) {
4267 *value=constmap[i][hr];
4268 return 1;
4269 }
4270 if(!bt[i+1]) {
4271 if(itype[i+1]==UJUMP||itype[i+1]==RJUMP||itype[i+1]==CJUMP||itype[i+1]==SJUMP) {
4272 // Load in delay slot, out-of-order execution
4273 if(itype[i+2]==LOAD&&rs1[i+2]==reg&&rt1[i+2]==reg&&((regs[i+1].wasconst>>hr)&1))
4274 {
4275 #ifdef HOST_IMM_ADDR32
4276 if(!using_tlb||((signed int)constmap[i][hr]+imm[i+2])<(signed int)0xC0000000) return 0;
4277 #endif
4278 // Precompute load address
4279 *value=constmap[i][hr]+imm[i+2];
4280 return 1;
4281 }
4282 }
4283 if(itype[i+1]==LOAD&&rs1[i+1]==reg&&rt1[i+1]==reg)
4284 {
4285 #ifdef HOST_IMM_ADDR32
4286 if(!using_tlb||((signed int)constmap[i][hr]+imm[i+1])<(signed int)0xC0000000) return 0;
4287 #endif
4288 // Precompute load address
4289 *value=constmap[i][hr]+imm[i+1];
4290 //printf("c=%x imm=%x\n",(int)constmap[i][hr],imm[i+1]);
4291 return 1;
4292 }
4293 }
4294 }
4295 *value=constmap[i][hr];
4296 //printf("c=%x\n",(int)constmap[i][hr]);
4297 if(i==slen-1) return 1;
4298 if(reg<64) {
4299 return !((unneeded_reg[i+1]>>reg)&1);
4300 }else{
4301 return !((unneeded_reg_upper[i+1]>>reg)&1);
4302 }
4303}
4304
4305// Load registers with known constants
4306void load_consts(signed char pre[],signed char regmap[],int is32,int i)
4307{
4308 int hr;
4309 // Load 32-bit regs
4310 for(hr=0;hr<HOST_REGS;hr++) {
4311 if(hr!=EXCLUDE_REG&&regmap[hr]>=0) {
4312 //if(entry[hr]!=regmap[hr]) {
4313 if(i==0||!((regs[i-1].isconst>>hr)&1)||pre[hr]!=regmap[hr]||bt[i]) {
4314 if(((regs[i].isconst>>hr)&1)&&regmap[hr]<64&&regmap[hr]>0) {
4315 int value;
4316 if(get_final_value(hr,i,&value)) {
4317 if(value==0) {
4318 emit_zeroreg(hr);
4319 }
4320 else {
4321 emit_movimm(value,hr);
4322 }
4323 }
4324 }
4325 }
4326 }
4327 }
4328 // Load 64-bit regs
4329 for(hr=0;hr<HOST_REGS;hr++) {
4330 if(hr!=EXCLUDE_REG&&regmap[hr]>=0) {
4331 //if(entry[hr]!=regmap[hr]) {
4332 if(i==0||!((regs[i-1].isconst>>hr)&1)||pre[hr]!=regmap[hr]||bt[i]) {
4333 if(((regs[i].isconst>>hr)&1)&&regmap[hr]>64) {
4334 if((is32>>(regmap[hr]&63))&1) {
4335 int lr=get_reg(regmap,regmap[hr]-64);
4336 assert(lr>=0);
4337 emit_sarimm(lr,31,hr);
4338 }
4339 else
4340 {
4341 int value;
4342 if(get_final_value(hr,i,&value)) {
4343 if(value==0) {
4344 emit_zeroreg(hr);
4345 }
4346 else {
4347 emit_movimm(value,hr);
4348 }
4349 }
4350 }
4351 }
4352 }
4353 }
4354 }
4355}
4356void load_all_consts(signed char regmap[],int is32,u_int dirty,int i)
4357{
4358 int hr;
4359 // Load 32-bit regs
4360 for(hr=0;hr<HOST_REGS;hr++) {
4361 if(hr!=EXCLUDE_REG&&regmap[hr]>=0&&((dirty>>hr)&1)) {
4362 if(((regs[i].isconst>>hr)&1)&&regmap[hr]<64&&regmap[hr]>0) {
4363 int value=constmap[i][hr];
4364 if(value==0) {
4365 emit_zeroreg(hr);
4366 }
4367 else {
4368 emit_movimm(value,hr);
4369 }
4370 }
4371 }
4372 }
4373 // Load 64-bit regs
4374 for(hr=0;hr<HOST_REGS;hr++) {
4375 if(hr!=EXCLUDE_REG&&regmap[hr]>=0&&((dirty>>hr)&1)) {
4376 if(((regs[i].isconst>>hr)&1)&&regmap[hr]>64) {
4377 if((is32>>(regmap[hr]&63))&1) {
4378 int lr=get_reg(regmap,regmap[hr]-64);
4379 assert(lr>=0);
4380 emit_sarimm(lr,31,hr);
4381 }
4382 else
4383 {
4384 int value=constmap[i][hr];
4385 if(value==0) {
4386 emit_zeroreg(hr);
4387 }
4388 else {
4389 emit_movimm(value,hr);
4390 }
4391 }
4392 }
4393 }
4394 }
4395}
4396
4397// Write out all dirty registers (except cycle count)
4398void wb_dirtys(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty)
4399{
4400 int hr;
4401 for(hr=0;hr<HOST_REGS;hr++) {
4402 if(hr!=EXCLUDE_REG) {
4403 if(i_regmap[hr]>0) {
4404 if(i_regmap[hr]!=CCREG) {
4405 if((i_dirty>>hr)&1) {
4406 if(i_regmap[hr]<64) {
4407 emit_storereg(i_regmap[hr],hr);
24385cae 4408#ifndef FORCE32
57871462 4409 if( ((i_is32>>i_regmap[hr])&1) ) {
4410 #ifdef DESTRUCTIVE_WRITEBACK
4411 emit_sarimm(hr,31,hr);
4412 emit_storereg(i_regmap[hr]|64,hr);
4413 #else
4414 emit_sarimm(hr,31,HOST_TEMPREG);
4415 emit_storereg(i_regmap[hr]|64,HOST_TEMPREG);
4416 #endif
4417 }
24385cae 4418#endif
57871462 4419 }else{
4420 if( !((i_is32>>(i_regmap[hr]&63))&1) ) {
4421 emit_storereg(i_regmap[hr],hr);
4422 }
4423 }
4424 }
4425 }
4426 }
4427 }
4428 }
4429}
4430// Write out dirty registers that we need to reload (pair with load_needed_regs)
4431// This writes the registers not written by store_regs_bt
4432void wb_needed_dirtys(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr)
4433{
4434 int hr;
4435 int t=(addr-start)>>2;
4436 for(hr=0;hr<HOST_REGS;hr++) {
4437 if(hr!=EXCLUDE_REG) {
4438 if(i_regmap[hr]>0) {
4439 if(i_regmap[hr]!=CCREG) {
4440 if(i_regmap[hr]==regs[t].regmap_entry[hr] && ((regs[t].dirty>>hr)&1) && !(((i_is32&~regs[t].was32&~unneeded_reg_upper[t])>>(i_regmap[hr]&63))&1)) {
4441 if((i_dirty>>hr)&1) {
4442 if(i_regmap[hr]<64) {
4443 emit_storereg(i_regmap[hr],hr);
24385cae 4444#ifndef FORCE32
57871462 4445 if( ((i_is32>>i_regmap[hr])&1) ) {
4446 #ifdef DESTRUCTIVE_WRITEBACK
4447 emit_sarimm(hr,31,hr);
4448 emit_storereg(i_regmap[hr]|64,hr);
4449 #else
4450 emit_sarimm(hr,31,HOST_TEMPREG);
4451 emit_storereg(i_regmap[hr]|64,HOST_TEMPREG);
4452 #endif
4453 }
24385cae 4454#endif
57871462 4455 }else{
4456 if( !((i_is32>>(i_regmap[hr]&63))&1) ) {
4457 emit_storereg(i_regmap[hr],hr);
4458 }
4459 }
4460 }
4461 }
4462 }
4463 }
4464 }
4465 }
4466}
4467
4468// Load all registers (except cycle count)
4469void load_all_regs(signed char i_regmap[])
4470{
4471 int hr;
4472 for(hr=0;hr<HOST_REGS;hr++) {
4473 if(hr!=EXCLUDE_REG) {
4474 if(i_regmap[hr]==0) {
4475 emit_zeroreg(hr);
4476 }
4477 else
ea3d2e6e 4478 if(i_regmap[hr]>0 && (i_regmap[hr]&63)<TEMPREG && i_regmap[hr]!=CCREG)
57871462 4479 {
4480 emit_loadreg(i_regmap[hr],hr);
4481 }
4482 }
4483 }
4484}
4485
4486// Load all current registers also needed by next instruction
4487void load_needed_regs(signed char i_regmap[],signed char next_regmap[])
4488{
4489 int hr;
4490 for(hr=0;hr<HOST_REGS;hr++) {
4491 if(hr!=EXCLUDE_REG) {
4492 if(get_reg(next_regmap,i_regmap[hr])>=0) {
4493 if(i_regmap[hr]==0) {
4494 emit_zeroreg(hr);
4495 }
4496 else
ea3d2e6e 4497 if(i_regmap[hr]>0 && (i_regmap[hr]&63)<TEMPREG && i_regmap[hr]!=CCREG)
57871462 4498 {
4499 emit_loadreg(i_regmap[hr],hr);
4500 }
4501 }
4502 }
4503 }
4504}
4505
4506// Load all regs, storing cycle count if necessary
4507void load_regs_entry(int t)
4508{
4509 int hr;
4510 if(is_ds[t]) emit_addimm(HOST_CCREG,CLOCK_DIVIDER,HOST_CCREG);
4511 else if(ccadj[t]) emit_addimm(HOST_CCREG,-ccadj[t]*CLOCK_DIVIDER,HOST_CCREG);
4512 if(regs[t].regmap_entry[HOST_CCREG]!=CCREG) {
4513 emit_storereg(CCREG,HOST_CCREG);
4514 }
4515 // Load 32-bit regs
4516 for(hr=0;hr<HOST_REGS;hr++) {
ea3d2e6e 4517 if(regs[t].regmap_entry[hr]>=0&&regs[t].regmap_entry[hr]<TEMPREG) {
57871462 4518 if(regs[t].regmap_entry[hr]==0) {
4519 emit_zeroreg(hr);
4520 }
4521 else if(regs[t].regmap_entry[hr]!=CCREG)
4522 {
4523 emit_loadreg(regs[t].regmap_entry[hr],hr);
4524 }
4525 }
4526 }
4527 // Load 64-bit regs
4528 for(hr=0;hr<HOST_REGS;hr++) {
ea3d2e6e 4529 if(regs[t].regmap_entry[hr]>=64&&regs[t].regmap_entry[hr]<TEMPREG+64) {
57871462 4530 assert(regs[t].regmap_entry[hr]!=64);
4531 if((regs[t].was32>>(regs[t].regmap_entry[hr]&63))&1) {
4532 int lr=get_reg(regs[t].regmap_entry,regs[t].regmap_entry[hr]-64);
4533 if(lr<0) {
4534 emit_loadreg(regs[t].regmap_entry[hr],hr);
4535 }
4536 else
4537 {
4538 emit_sarimm(lr,31,hr);
4539 }
4540 }
4541 else
4542 {
4543 emit_loadreg(regs[t].regmap_entry[hr],hr);
4544 }
4545 }
4546 }
4547}
4548
4549// Store dirty registers prior to branch
4550void store_regs_bt(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr)
4551{
4552 if(internal_branch(i_is32,addr))
4553 {
4554 int t=(addr-start)>>2;
4555 int hr;
4556 for(hr=0;hr<HOST_REGS;hr++) {
4557 if(hr!=EXCLUDE_REG) {
4558 if(i_regmap[hr]>0 && i_regmap[hr]!=CCREG) {
4559 if(i_regmap[hr]!=regs[t].regmap_entry[hr] || !((regs[t].dirty>>hr)&1) || (((i_is32&~regs[t].was32&~unneeded_reg_upper[t])>>(i_regmap[hr]&63))&1)) {
4560 if((i_dirty>>hr)&1) {
4561 if(i_regmap[hr]<64) {
4562 if(!((unneeded_reg[t]>>i_regmap[hr])&1)) {
4563 emit_storereg(i_regmap[hr],hr);
4564 if( ((i_is32>>i_regmap[hr])&1) && !((unneeded_reg_upper[t]>>i_regmap[hr])&1) ) {
4565 #ifdef DESTRUCTIVE_WRITEBACK
4566 emit_sarimm(hr,31,hr);
4567 emit_storereg(i_regmap[hr]|64,hr);
4568 #else
4569 emit_sarimm(hr,31,HOST_TEMPREG);
4570 emit_storereg(i_regmap[hr]|64,HOST_TEMPREG);
4571 #endif
4572 }
4573 }
4574 }else{
4575 if( !((i_is32>>(i_regmap[hr]&63))&1) && !((unneeded_reg_upper[t]>>(i_regmap[hr]&63))&1) ) {
4576 emit_storereg(i_regmap[hr],hr);
4577 }
4578 }
4579 }
4580 }
4581 }
4582 }
4583 }
4584 }
4585 else
4586 {
4587 // Branch out of this block, write out all dirty regs
4588 wb_dirtys(i_regmap,i_is32,i_dirty);
4589 }
4590}
4591
4592// Load all needed registers for branch target
4593void load_regs_bt(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr)
4594{
4595 //if(addr>=start && addr<(start+slen*4))
4596 if(internal_branch(i_is32,addr))
4597 {
4598 int t=(addr-start)>>2;
4599 int hr;
4600 // Store the cycle count before loading something else
4601 if(i_regmap[HOST_CCREG]!=CCREG) {
4602 assert(i_regmap[HOST_CCREG]==-1);
4603 }
4604 if(regs[t].regmap_entry[HOST_CCREG]!=CCREG) {
4605 emit_storereg(CCREG,HOST_CCREG);
4606 }
4607 // Load 32-bit regs
4608 for(hr=0;hr<HOST_REGS;hr++) {
ea3d2e6e 4609 if(hr!=EXCLUDE_REG&&regs[t].regmap_entry[hr]>=0&&regs[t].regmap_entry[hr]<TEMPREG) {
57871462 4610 #ifdef DESTRUCTIVE_WRITEBACK
4611 if(i_regmap[hr]!=regs[t].regmap_entry[hr] || ( !((regs[t].dirty>>hr)&1) && ((i_dirty>>hr)&1) && (((i_is32&~unneeded_reg_upper[t])>>i_regmap[hr])&1) ) || (((i_is32&~regs[t].was32&~unneeded_reg_upper[t])>>(i_regmap[hr]&63))&1)) {
4612 #else
4613 if(i_regmap[hr]!=regs[t].regmap_entry[hr] ) {
4614 #endif
4615 if(regs[t].regmap_entry[hr]==0) {
4616 emit_zeroreg(hr);
4617 }
4618 else if(regs[t].regmap_entry[hr]!=CCREG)
4619 {
4620 emit_loadreg(regs[t].regmap_entry[hr],hr);
4621 }
4622 }
4623 }
4624 }
4625 //Load 64-bit regs
4626 for(hr=0;hr<HOST_REGS;hr++) {
ea3d2e6e 4627 if(hr!=EXCLUDE_REG&&regs[t].regmap_entry[hr]>=64&&regs[t].regmap_entry[hr]<TEMPREG+64) {
57871462 4628 if(i_regmap[hr]!=regs[t].regmap_entry[hr]) {
4629 assert(regs[t].regmap_entry[hr]!=64);
4630 if((i_is32>>(regs[t].regmap_entry[hr]&63))&1) {
4631 int lr=get_reg(regs[t].regmap_entry,regs[t].regmap_entry[hr]-64);
4632 if(lr<0) {
4633 emit_loadreg(regs[t].regmap_entry[hr],hr);
4634 }
4635 else
4636 {
4637 emit_sarimm(lr,31,hr);
4638 }
4639 }
4640 else
4641 {
4642 emit_loadreg(regs[t].regmap_entry[hr],hr);
4643 }
4644 }
4645 else if((i_is32>>(regs[t].regmap_entry[hr]&63))&1) {
4646 int lr=get_reg(regs[t].regmap_entry,regs[t].regmap_entry[hr]-64);
4647 assert(lr>=0);
4648 emit_sarimm(lr,31,hr);
4649 }
4650 }
4651 }
4652 }
4653}
4654
4655int match_bt(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr)
4656{
4657 if(addr>=start && addr<start+slen*4-4)
4658 {
4659 int t=(addr-start)>>2;
4660 int hr;
4661 if(regs[t].regmap_entry[HOST_CCREG]!=CCREG) return 0;
4662 for(hr=0;hr<HOST_REGS;hr++)
4663 {
4664 if(hr!=EXCLUDE_REG)
4665 {
4666 if(i_regmap[hr]!=regs[t].regmap_entry[hr])
4667 {
ea3d2e6e 4668 if(regs[t].regmap_entry[hr]>=0&&(regs[t].regmap_entry[hr]|64)<TEMPREG+64)
57871462 4669 {
4670 return 0;
4671 }
4672 else
4673 if((i_dirty>>hr)&1)
4674 {
ea3d2e6e 4675 if(i_regmap[hr]<TEMPREG)
57871462 4676 {
4677 if(!((unneeded_reg[t]>>i_regmap[hr])&1))
4678 return 0;
4679 }
ea3d2e6e 4680 else if(i_regmap[hr]>=64&&i_regmap[hr]<TEMPREG+64)
57871462 4681 {
4682 if(!((unneeded_reg_upper[t]>>(i_regmap[hr]&63))&1))
4683 return 0;
4684 }
4685 }
4686 }
4687 else // Same register but is it 32-bit or dirty?
4688 if(i_regmap[hr]>=0)
4689 {
4690 if(!((regs[t].dirty>>hr)&1))
4691 {
4692 if((i_dirty>>hr)&1)
4693 {
4694 if(!((unneeded_reg[t]>>i_regmap[hr])&1))
4695 {
4696 //printf("%x: dirty no match\n",addr);
4697 return 0;
4698 }
4699 }
4700 }
4701 if((((regs[t].was32^i_is32)&~unneeded_reg_upper[t])>>(i_regmap[hr]&63))&1)
4702 {
4703 //printf("%x: is32 no match\n",addr);
4704 return 0;
4705 }
4706 }
4707 }
4708 }
4709 //if(is32[t]&~unneeded_reg_upper[t]&~i_is32) return 0;
a28c6ce8 4710#ifndef FORCE32
57871462 4711 if(requires_32bit[t]&~i_is32) return 0;
a28c6ce8 4712#endif
57871462 4713 // Delay slots are not valid branch targets
4714 //if(t>0&&(itype[t-1]==RJUMP||itype[t-1]==UJUMP||itype[t-1]==CJUMP||itype[t-1]==SJUMP||itype[t-1]==FJUMP)) return 0;
4715 // Delay slots require additional processing, so do not match
4716 if(is_ds[t]) return 0;
4717 }
4718 else
4719 {
4720 int hr;
4721 for(hr=0;hr<HOST_REGS;hr++)
4722 {
4723 if(hr!=EXCLUDE_REG)
4724 {
4725 if(i_regmap[hr]>=0)
4726 {
4727 if(hr!=HOST_CCREG||i_regmap[hr]!=CCREG)
4728 {
4729 if((i_dirty>>hr)&1)
4730 {
4731 return 0;
4732 }
4733 }
4734 }
4735 }
4736 }
4737 }
4738 return 1;
4739}
4740
4741// Used when a branch jumps into the delay slot of another branch
4742void ds_assemble_entry(int i)
4743{
4744 int t=(ba[i]-start)>>2;
4745 if(!instr_addr[t]) instr_addr[t]=(u_int)out;
4746 assem_debug("Assemble delay slot at %x\n",ba[i]);
4747 assem_debug("<->\n");
4748 if(regs[t].regmap_entry[HOST_CCREG]==CCREG&&regs[t].regmap[HOST_CCREG]!=CCREG)
4749 wb_register(CCREG,regs[t].regmap_entry,regs[t].wasdirty,regs[t].was32);
4750 load_regs(regs[t].regmap_entry,regs[t].regmap,regs[t].was32,rs1[t],rs2[t]);
4751 address_generation(t,&regs[t],regs[t].regmap_entry);
b9b61529 4752 if(itype[t]==STORE||itype[t]==STORELR||(opcode[t]&0x3b)==0x39||(opcode[t]&0x3b)==0x3a)
57871462 4753 load_regs(regs[t].regmap_entry,regs[t].regmap,regs[t].was32,INVCP,INVCP);
4754 cop1_usable=0;
4755 is_delayslot=0;
4756 switch(itype[t]) {
4757 case ALU:
4758 alu_assemble(t,&regs[t]);break;
4759 case IMM16:
4760 imm16_assemble(t,&regs[t]);break;
4761 case SHIFT:
4762 shift_assemble(t,&regs[t]);break;
4763 case SHIFTIMM:
4764 shiftimm_assemble(t,&regs[t]);break;
4765 case LOAD:
4766 load_assemble(t,&regs[t]);break;
4767 case LOADLR:
4768 loadlr_assemble(t,&regs[t]);break;
4769 case STORE:
4770 store_assemble(t,&regs[t]);break;
4771 case STORELR:
4772 storelr_assemble(t,&regs[t]);break;
4773 case COP0:
4774 cop0_assemble(t,&regs[t]);break;
4775 case COP1:
4776 cop1_assemble(t,&regs[t]);break;
4777 case C1LS:
4778 c1ls_assemble(t,&regs[t]);break;
b9b61529 4779 case COP2:
4780 cop2_assemble(t,&regs[t]);break;
4781 case C2LS:
4782 c2ls_assemble(t,&regs[t]);break;
4783 case C2OP:
4784 c2op_assemble(t,&regs[t]);break;
57871462 4785 case FCONV:
4786 fconv_assemble(t,&regs[t]);break;
4787 case FLOAT:
4788 float_assemble(t,&regs[t]);break;
4789 case FCOMP:
4790 fcomp_assemble(t,&regs[t]);break;
4791 case MULTDIV:
4792 multdiv_assemble(t,&regs[t]);break;
4793 case MOV:
4794 mov_assemble(t,&regs[t]);break;
4795 case SYSCALL:
7139f3c8 4796 case HLECALL:
1e973cb0 4797 case INTCALL:
57871462 4798 case SPAN:
4799 case UJUMP:
4800 case RJUMP:
4801 case CJUMP:
4802 case SJUMP:
4803 case FJUMP:
4804 printf("Jump in the delay slot. This is probably a bug.\n");
4805 }
4806 store_regs_bt(regs[t].regmap,regs[t].is32,regs[t].dirty,ba[i]+4);
4807 load_regs_bt(regs[t].regmap,regs[t].is32,regs[t].dirty,ba[i]+4);
4808 if(internal_branch(regs[t].is32,ba[i]+4))
4809 assem_debug("branch: internal\n");
4810 else
4811 assem_debug("branch: external\n");
4812 assert(internal_branch(regs[t].is32,ba[i]+4));
4813 add_to_linker((int)out,ba[i]+4,internal_branch(regs[t].is32,ba[i]+4));
4814 emit_jmp(0);
4815}
4816
4817void do_cc(int i,signed char i_regmap[],int *adj,int addr,int taken,int invert)
4818{
4819 int count;
4820 int jaddr;
4821 int idle=0;
4822 if(itype[i]==RJUMP)
4823 {
4824 *adj=0;
4825 }
4826 //if(ba[i]>=start && ba[i]<(start+slen*4))
4827 if(internal_branch(branch_regs[i].is32,ba[i]))
4828 {
4829 int t=(ba[i]-start)>>2;
4830 if(is_ds[t]) *adj=-1; // Branch into delay slot adds an extra cycle
4831 else *adj=ccadj[t];
4832 }
4833 else
4834 {
4835 *adj=0;
4836 }
4837 count=ccadj[i];
4838 if(taken==TAKEN && i==(ba[i]-start)>>2 && source[i+1]==0) {
4839 // Idle loop
4840 if(count&1) emit_addimm_and_set_flags(2*(count+2),HOST_CCREG);
4841 idle=(int)out;
4842 //emit_subfrommem(&idlecount,HOST_CCREG); // Count idle cycles
4843 emit_andimm(HOST_CCREG,3,HOST_CCREG);
4844 jaddr=(int)out;
4845 emit_jmp(0);
4846 }
4847 else if(*adj==0||invert) {
4848 emit_addimm_and_set_flags(CLOCK_DIVIDER*(count+2),HOST_CCREG);
4849 jaddr=(int)out;
4850 emit_jns(0);
4851 }
4852 else
4853 {
eeb1feeb 4854 emit_cmpimm(HOST_CCREG,-CLOCK_DIVIDER*(count+2));
57871462 4855 jaddr=(int)out;
4856 emit_jns(0);
4857 }
4858 add_stub(CC_STUB,jaddr,idle?idle:(int)out,(*adj==0||invert||idle)?0:(count+2),i,addr,taken,0);
4859}
4860
4861void do_ccstub(int n)
4862{
4863 literal_pool(256);
4864 assem_debug("do_ccstub %x\n",start+stubs[n][4]*4);
4865 set_jump_target(stubs[n][1],(int)out);
4866 int i=stubs[n][4];
4867 if(stubs[n][6]==NULLDS) {
4868 // Delay slot instruction is nullified ("likely" branch)
4869 wb_dirtys(regs[i].regmap,regs[i].is32,regs[i].dirty);
4870 }
4871 else if(stubs[n][6]!=TAKEN) {
4872 wb_dirtys(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty);
4873 }
4874 else {
4875 if(internal_branch(branch_regs[i].is32,ba[i]))
4876 wb_needed_dirtys(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
4877 }
4878 if(stubs[n][5]!=-1)
4879 {
4880 // Save PC as return address
4881 emit_movimm(stubs[n][5],EAX);
4882 emit_writeword(EAX,(int)&pcaddr);
4883 }
4884 else
4885 {
4886 // Return address depends on which way the branch goes
4887 if(itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
4888 {
4889 int s1l=get_reg(branch_regs[i].regmap,rs1[i]);
4890 int s1h=get_reg(branch_regs[i].regmap,rs1[i]|64);
4891 int s2l=get_reg(branch_regs[i].regmap,rs2[i]);
4892 int s2h=get_reg(branch_regs[i].regmap,rs2[i]|64);
4893 if(rs1[i]==0)
4894 {
4895 s1l=s2l;s1h=s2h;
4896 s2l=s2h=-1;
4897 }
4898 else if(rs2[i]==0)
4899 {
4900 s2l=s2h=-1;
4901 }
4902 if((branch_regs[i].is32>>rs1[i])&(branch_regs[i].is32>>rs2[i])&1) {
4903 s1h=s2h=-1;
4904 }
4905 assert(s1l>=0);
4906 #ifdef DESTRUCTIVE_WRITEBACK
4907 if(rs1[i]) {
4908 if((branch_regs[i].dirty>>s1l)&(branch_regs[i].is32>>rs1[i])&1)
4909 emit_loadreg(rs1[i],s1l);
4910 }
4911 else {
4912 if((branch_regs[i].dirty>>s1l)&(branch_regs[i].is32>>rs2[i])&1)
4913 emit_loadreg(rs2[i],s1l);
4914 }
4915 if(s2l>=0)
4916 if((branch_regs[i].dirty>>s2l)&(branch_regs[i].is32>>rs2[i])&1)
4917 emit_loadreg(rs2[i],s2l);
4918 #endif
4919 int hr=0;
5194fb95 4920 int addr=-1,alt=-1,ntaddr=-1;
57871462 4921 while(hr<HOST_REGS)
4922 {
4923 if(hr!=EXCLUDE_REG && hr!=HOST_CCREG &&
4924 (branch_regs[i].regmap[hr]&63)!=rs1[i] &&
4925 (branch_regs[i].regmap[hr]&63)!=rs2[i] )
4926 {
4927 addr=hr++;break;
4928 }
4929 hr++;
4930 }
4931 while(hr<HOST_REGS)
4932 {
4933 if(hr!=EXCLUDE_REG && hr!=HOST_CCREG &&
4934 (branch_regs[i].regmap[hr]&63)!=rs1[i] &&
4935 (branch_regs[i].regmap[hr]&63)!=rs2[i] )
4936 {
4937 alt=hr++;break;
4938 }
4939 hr++;
4940 }
4941 if((opcode[i]&0x2E)==6) // BLEZ/BGTZ needs another register
4942 {
4943 while(hr<HOST_REGS)
4944 {
4945 if(hr!=EXCLUDE_REG && hr!=HOST_CCREG &&
4946 (branch_regs[i].regmap[hr]&63)!=rs1[i] &&
4947 (branch_regs[i].regmap[hr]&63)!=rs2[i] )
4948 {
4949 ntaddr=hr;break;
4950 }
4951 hr++;
4952 }
4953 assert(hr<HOST_REGS);
4954 }
4955 if((opcode[i]&0x2f)==4) // BEQ
4956 {
4957 #ifdef HAVE_CMOV_IMM
4958 if(s1h<0) {
4959 if(s2l>=0) emit_cmp(s1l,s2l);
4960 else emit_test(s1l,s1l);
4961 emit_cmov2imm_e_ne_compact(ba[i],start+i*4+8,addr);
4962 }
4963 else
4964 #endif
4965 {
4966 emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
4967 if(s1h>=0) {
4968 if(s2h>=0) emit_cmp(s1h,s2h);
4969 else emit_test(s1h,s1h);
4970 emit_cmovne_reg(alt,addr);
4971 }
4972 if(s2l>=0) emit_cmp(s1l,s2l);
4973 else emit_test(s1l,s1l);
4974 emit_cmovne_reg(alt,addr);
4975 }
4976 }
4977 if((opcode[i]&0x2f)==5) // BNE
4978 {
4979 #ifdef HAVE_CMOV_IMM
4980 if(s1h<0) {
4981 if(s2l>=0) emit_cmp(s1l,s2l);
4982 else emit_test(s1l,s1l);
4983 emit_cmov2imm_e_ne_compact(start+i*4+8,ba[i],addr);
4984 }
4985 else
4986 #endif
4987 {
4988 emit_mov2imm_compact(start+i*4+8,addr,ba[i],alt);
4989 if(s1h>=0) {
4990 if(s2h>=0) emit_cmp(s1h,s2h);
4991 else emit_test(s1h,s1h);
4992 emit_cmovne_reg(alt,addr);
4993 }
4994 if(s2l>=0) emit_cmp(s1l,s2l);
4995 else emit_test(s1l,s1l);
4996 emit_cmovne_reg(alt,addr);
4997 }
4998 }
4999 if((opcode[i]&0x2f)==6) // BLEZ
5000 {
5001 //emit_movimm(ba[i],alt);
5002 //emit_movimm(start+i*4+8,addr);
5003 emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
5004 emit_cmpimm(s1l,1);
5005 if(s1h>=0) emit_mov(addr,ntaddr);
5006 emit_cmovl_reg(alt,addr);
5007 if(s1h>=0) {
5008 emit_test(s1h,s1h);
5009 emit_cmovne_reg(ntaddr,addr);
5010 emit_cmovs_reg(alt,addr);
5011 }
5012 }
5013 if((opcode[i]&0x2f)==7) // BGTZ
5014 {
5015 //emit_movimm(ba[i],addr);
5016 //emit_movimm(start+i*4+8,ntaddr);
5017 emit_mov2imm_compact(ba[i],addr,start+i*4+8,ntaddr);
5018 emit_cmpimm(s1l,1);
5019 if(s1h>=0) emit_mov(addr,alt);
5020 emit_cmovl_reg(ntaddr,addr);
5021 if(s1h>=0) {
5022 emit_test(s1h,s1h);
5023 emit_cmovne_reg(alt,addr);
5024 emit_cmovs_reg(ntaddr,addr);
5025 }
5026 }
5027 if((opcode[i]==1)&&(opcode2[i]&0x2D)==0) // BLTZ
5028 {
5029 //emit_movimm(ba[i],alt);
5030 //emit_movimm(start+i*4+8,addr);
5031 emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
5032 if(s1h>=0) emit_test(s1h,s1h);
5033 else emit_test(s1l,s1l);
5034 emit_cmovs_reg(alt,addr);
5035 }
5036 if((opcode[i]==1)&&(opcode2[i]&0x2D)==1) // BGEZ
5037 {
5038 //emit_movimm(ba[i],addr);
5039 //emit_movimm(start+i*4+8,alt);
5040 emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
5041 if(s1h>=0) emit_test(s1h,s1h);
5042 else emit_test(s1l,s1l);
5043 emit_cmovs_reg(alt,addr);
5044 }
5045 if(opcode[i]==0x11 && opcode2[i]==0x08 ) {
5046 if(source[i]&0x10000) // BC1T
5047 {
5048 //emit_movimm(ba[i],alt);
5049 //emit_movimm(start+i*4+8,addr);
5050 emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
5051 emit_testimm(s1l,0x800000);
5052 emit_cmovne_reg(alt,addr);
5053 }
5054 else // BC1F
5055 {
5056 //emit_movimm(ba[i],addr);
5057 //emit_movimm(start+i*4+8,alt);
5058 emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
5059 emit_testimm(s1l,0x800000);
5060 emit_cmovne_reg(alt,addr);
5061 }
5062 }
5063 emit_writeword(addr,(int)&pcaddr);
5064 }
5065 else
5066 if(itype[i]==RJUMP)
5067 {
5068 int r=get_reg(branch_regs[i].regmap,rs1[i]);
5069 if(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1]) {
5070 r=get_reg(branch_regs[i].regmap,RTEMP);
5071 }
5072 emit_writeword(r,(int)&pcaddr);
5073 }
5074 else {printf("Unknown branch type in do_ccstub\n");exit(1);}
5075 }
5076 // Update cycle count
5077 assert(branch_regs[i].regmap[HOST_CCREG]==CCREG||branch_regs[i].regmap[HOST_CCREG]==-1);
5078 if(stubs[n][3]) emit_addimm(HOST_CCREG,CLOCK_DIVIDER*stubs[n][3],HOST_CCREG);
5079 emit_call((int)cc_interrupt);
5080 if(stubs[n][3]) emit_addimm(HOST_CCREG,-CLOCK_DIVIDER*stubs[n][3],HOST_CCREG);
5081 if(stubs[n][6]==TAKEN) {
5082 if(internal_branch(branch_regs[i].is32,ba[i]))
5083 load_needed_regs(branch_regs[i].regmap,regs[(ba[i]-start)>>2].regmap_entry);
5084 else if(itype[i]==RJUMP) {
5085 if(get_reg(branch_regs[i].regmap,RTEMP)>=0)
5086 emit_readword((int)&pcaddr,get_reg(branch_regs[i].regmap,RTEMP));
5087 else
5088 emit_loadreg(rs1[i],get_reg(branch_regs[i].regmap,rs1[i]));
5089 }
5090 }else if(stubs[n][6]==NOTTAKEN) {
5091 if(i<slen-2) load_needed_regs(branch_regs[i].regmap,regmap_pre[i+2]);
5092 else load_all_regs(branch_regs[i].regmap);
5093 }else if(stubs[n][6]==NULLDS) {
5094 // Delay slot instruction is nullified ("likely" branch)
5095 if(i<slen-2) load_needed_regs(regs[i].regmap,regmap_pre[i+2]);
5096 else load_all_regs(regs[i].regmap);
5097 }else{
5098 load_all_regs(branch_regs[i].regmap);
5099 }
5100 emit_jmp(stubs[n][2]); // return address
5101
5102 /* This works but uses a lot of memory...
5103 emit_readword((int)&last_count,ECX);
5104 emit_add(HOST_CCREG,ECX,EAX);
5105 emit_writeword(EAX,(int)&Count);
5106 emit_call((int)gen_interupt);
5107 emit_readword((int)&Count,HOST_CCREG);
5108 emit_readword((int)&next_interupt,EAX);
5109 emit_readword((int)&pending_exception,EBX);
5110 emit_writeword(EAX,(int)&last_count);
5111 emit_sub(HOST_CCREG,EAX,HOST_CCREG);
5112 emit_test(EBX,EBX);
5113 int jne_instr=(int)out;
5114 emit_jne(0);
5115 if(stubs[n][3]) emit_addimm(HOST_CCREG,-2*stubs[n][3],HOST_CCREG);
5116 load_all_regs(branch_regs[i].regmap);
5117 emit_jmp(stubs[n][2]); // return address
5118 set_jump_target(jne_instr,(int)out);
5119 emit_readword((int)&pcaddr,EAX);
5120 // Call get_addr_ht instead of doing the hash table here.
5121 // This code is executed infrequently and takes up a lot of space
5122 // so smaller is better.
5123 emit_storereg(CCREG,HOST_CCREG);
5124 emit_pushreg(EAX);
5125 emit_call((int)get_addr_ht);
5126 emit_loadreg(CCREG,HOST_CCREG);
5127 emit_addimm(ESP,4,ESP);
5128 emit_jmpreg(EAX);*/
5129}
5130
5131add_to_linker(int addr,int target,int ext)
5132{
5133 link_addr[linkcount][0]=addr;
5134 link_addr[linkcount][1]=target;
5135 link_addr[linkcount][2]=ext;
5136 linkcount++;
5137}
5138
5139void ujump_assemble(int i,struct regstat *i_regs)
5140{
5141 signed char *i_regmap=i_regs->regmap;
5142 if(i==(ba[i]-start)>>2) assem_debug("idle loop\n");
5143 address_generation(i+1,i_regs,regs[i].regmap_entry);
5144 #ifdef REG_PREFETCH
5145 int temp=get_reg(branch_regs[i].regmap,PTEMP);
5146 if(rt1[i]==31&&temp>=0)
5147 {
5148 int return_address=start+i*4+8;
5149 if(get_reg(branch_regs[i].regmap,31)>0)
5150 if(i_regmap[temp]==PTEMP) emit_movimm((int)hash_table[((return_address>>16)^return_address)&0xFFFF],temp);
5151 }
5152 #endif
57871462 5153 if(rt1[i]==31) {
5154 int rt;
5155 unsigned int return_address;
57871462 5156 rt=get_reg(branch_regs[i].regmap,31);
5157 assem_debug("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5158 //assert(rt>=0);
5159 return_address=start+i*4+8;
5160 if(rt>=0) {
5161 #ifdef USE_MINI_HT
4ef8f67d 5162 if(internal_branch(branch_regs[i].is32,return_address)&&rt1[i+1]!=31) {
5163 int temp=-1; // note: must be ds-safe
57871462 5164 #ifdef HOST_TEMPREG
4ef8f67d 5165 temp=HOST_TEMPREG;
57871462 5166 #endif
5167 if(temp>=0) do_miniht_insert(return_address,rt,temp);
5168 else emit_movimm(return_address,rt);
5169 }
5170 else
5171 #endif
5172 {
5173 #ifdef REG_PREFETCH
5174 if(temp>=0)
5175 {
5176 if(i_regmap[temp]!=PTEMP) emit_movimm((int)hash_table[((return_address>>16)^return_address)&0xFFFF],temp);
5177 }
5178 #endif
5179 emit_movimm(return_address,rt); // PC into link register
5180 #ifdef IMM_PREFETCH
5181 emit_prefetch(hash_table[((return_address>>16)^return_address)&0xFFFF]);
5182 #endif
5183 }
5184 }
5185 }
4ef8f67d 5186 ds_assemble(i+1,i_regs);
5187 uint64_t bc_unneeded=branch_regs[i].u;
5188 uint64_t bc_unneeded_upper=branch_regs[i].uu;
5189 bc_unneeded|=1|(1LL<<rt1[i]);
5190 bc_unneeded_upper|=1|(1LL<<rt1[i]);
5191 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5192 bc_unneeded,bc_unneeded_upper);
5193 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
57871462 5194 int cc,adj;
5195 cc=get_reg(branch_regs[i].regmap,CCREG);
5196 assert(cc==HOST_CCREG);
5197 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5198 #ifdef REG_PREFETCH
5199 if(rt1[i]==31&&temp>=0) emit_prefetchreg(temp);
5200 #endif
5201 do_cc(i,branch_regs[i].regmap,&adj,ba[i],TAKEN,0);
5202 if(adj) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc);
5203 load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5204 if(internal_branch(branch_regs[i].is32,ba[i]))
5205 assem_debug("branch: internal\n");
5206 else
5207 assem_debug("branch: external\n");
5208 if(internal_branch(branch_regs[i].is32,ba[i])&&is_ds[(ba[i]-start)>>2]) {
5209 ds_assemble_entry(i);
5210 }
5211 else {
5212 add_to_linker((int)out,ba[i],internal_branch(branch_regs[i].is32,ba[i]));
5213 emit_jmp(0);
5214 }
5215}
5216
5217void rjump_assemble(int i,struct regstat *i_regs)
5218{
5219 signed char *i_regmap=i_regs->regmap;
5220 int temp;
5221 int rs,cc,adj;
5222 rs=get_reg(branch_regs[i].regmap,rs1[i]);
5223 assert(rs>=0);
5224 if(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1]) {
5225 // Delay slot abuse, make a copy of the branch address register
5226 temp=get_reg(branch_regs[i].regmap,RTEMP);
5227 assert(temp>=0);
5228 assert(regs[i].regmap[temp]==RTEMP);
5229 emit_mov(rs,temp);
5230 rs=temp;
5231 }
5232 address_generation(i+1,i_regs,regs[i].regmap_entry);
5233 #ifdef REG_PREFETCH
5234 if(rt1[i]==31)
5235 {
5236 if((temp=get_reg(branch_regs[i].regmap,PTEMP))>=0) {
5237 int return_address=start+i*4+8;
5238 if(i_regmap[temp]==PTEMP) emit_movimm((int)hash_table[((return_address>>16)^return_address)&0xFFFF],temp);
5239 }
5240 }
5241 #endif
5242 #ifdef USE_MINI_HT
5243 if(rs1[i]==31) {
5244 int rh=get_reg(regs[i].regmap,RHASH);
5245 if(rh>=0) do_preload_rhash(rh);
5246 }
5247 #endif
5248 ds_assemble(i+1,i_regs);
5249 uint64_t bc_unneeded=branch_regs[i].u;
5250 uint64_t bc_unneeded_upper=branch_regs[i].uu;
5251 bc_unneeded|=1|(1LL<<rt1[i]);
5252 bc_unneeded_upper|=1|(1LL<<rt1[i]);
5253 bc_unneeded&=~(1LL<<rs1[i]);
5254 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5255 bc_unneeded,bc_unneeded_upper);
5256 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i],CCREG);
5067f341 5257 if(rt1[i]!=0) {
57871462 5258 int rt,return_address;
5067f341 5259 assert(rt1[i+1]!=rt1[i]);
5260 assert(rt2[i+1]!=rt1[i]);
5261 rt=get_reg(branch_regs[i].regmap,rt1[i]);
57871462 5262 assem_debug("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5263 assert(rt>=0);
5264 return_address=start+i*4+8;
5265 #ifdef REG_PREFETCH
5266 if(temp>=0)
5267 {
5268 if(i_regmap[temp]!=PTEMP) emit_movimm((int)hash_table[((return_address>>16)^return_address)&0xFFFF],temp);
5269 }
5270 #endif
5271 emit_movimm(return_address,rt); // PC into link register
5272 #ifdef IMM_PREFETCH
5273 emit_prefetch(hash_table[((return_address>>16)^return_address)&0xFFFF]);
5274 #endif
5275 }
5276 cc=get_reg(branch_regs[i].regmap,CCREG);
5277 assert(cc==HOST_CCREG);
5278 #ifdef USE_MINI_HT
5279 int rh=get_reg(branch_regs[i].regmap,RHASH);
5280 int ht=get_reg(branch_regs[i].regmap,RHTBL);
5281 if(rs1[i]==31) {
5282 if(regs[i].regmap[rh]!=RHASH) do_preload_rhash(rh);
5283 do_preload_rhtbl(ht);
5284 do_rhash(rs,rh);
5285 }
5286 #endif
5287 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,-1);
5288 #ifdef DESTRUCTIVE_WRITEBACK
5289 if((branch_regs[i].dirty>>rs)&(branch_regs[i].is32>>rs1[i])&1) {
5290 if(rs1[i]!=rt1[i+1]&&rs1[i]!=rt2[i+1]) {
5291 emit_loadreg(rs1[i],rs);
5292 }
5293 }
5294 #endif
5295 #ifdef REG_PREFETCH
5296 if(rt1[i]==31&&temp>=0) emit_prefetchreg(temp);
5297 #endif
5298 #ifdef USE_MINI_HT
5299 if(rs1[i]==31) {
5300 do_miniht_load(ht,rh);
5301 }
5302 #endif
5303 //do_cc(i,branch_regs[i].regmap,&adj,-1,TAKEN);
5304 //if(adj) emit_addimm(cc,2*(ccadj[i]+2-adj),cc); // ??? - Shouldn't happen
5305 //assert(adj==0);
5306 emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),HOST_CCREG);
5307 add_stub(CC_STUB,(int)out,jump_vaddr_reg[rs],0,i,-1,TAKEN,0);
5308 emit_jns(0);
5309 //load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,-1);
5310 #ifdef USE_MINI_HT
5311 if(rs1[i]==31) {
5312 do_miniht_jump(rs,rh,ht);
5313 }
5314 else
5315 #endif
5316 {
5317 //if(rs!=EAX) emit_mov(rs,EAX);
5318 //emit_jmp((int)jump_vaddr_eax);
5319 emit_jmp(jump_vaddr_reg[rs]);
5320 }
5321 /* Check hash table
5322 temp=!rs;
5323 emit_mov(rs,temp);
5324 emit_shrimm(rs,16,rs);
5325 emit_xor(temp,rs,rs);
5326 emit_movzwl_reg(rs,rs);
5327 emit_shlimm(rs,4,rs);
5328 emit_cmpmem_indexed((int)hash_table,rs,temp);
5329 emit_jne((int)out+14);
5330 emit_readword_indexed((int)hash_table+4,rs,rs);
5331 emit_jmpreg(rs);
5332 emit_cmpmem_indexed((int)hash_table+8,rs,temp);
5333 emit_addimm_no_flags(8,rs);
5334 emit_jeq((int)out-17);
5335 // No hit on hash table, call compiler
5336 emit_pushreg(temp);
5337//DEBUG >
5338#ifdef DEBUG_CYCLE_COUNT
5339 emit_readword((int)&last_count,ECX);
5340 emit_add(HOST_CCREG,ECX,HOST_CCREG);
5341 emit_readword((int)&next_interupt,ECX);
5342 emit_writeword(HOST_CCREG,(int)&Count);
5343 emit_sub(HOST_CCREG,ECX,HOST_CCREG);
5344 emit_writeword(ECX,(int)&last_count);
5345#endif
5346//DEBUG <
5347 emit_storereg(CCREG,HOST_CCREG);
5348 emit_call((int)get_addr);
5349 emit_loadreg(CCREG,HOST_CCREG);
5350 emit_addimm(ESP,4,ESP);
5351 emit_jmpreg(EAX);*/
5352 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5353 if(rt1[i]!=31&&i<slen-2&&(((u_int)out)&7)) emit_mov(13,13);
5354 #endif
5355}
5356
5357void cjump_assemble(int i,struct regstat *i_regs)
5358{
5359 signed char *i_regmap=i_regs->regmap;
5360 int cc;
5361 int match;
5362 match=match_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5363 assem_debug("match=%d\n",match);
5364 int s1h,s1l,s2h,s2l;
5365 int prev_cop1_usable=cop1_usable;
5366 int unconditional=0,nop=0;
5367 int only32=0;
57871462 5368 int invert=0;
5369 int internal=internal_branch(branch_regs[i].is32,ba[i]);
5370 if(i==(ba[i]-start)>>2) assem_debug("idle loop\n");
57871462 5371 if(!match) invert=1;
5372 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5373 if(i>(ba[i]-start)>>2) invert=1;
5374 #endif
e1190b87 5375
5376 if(ooo[i]) {
57871462 5377 s1l=get_reg(branch_regs[i].regmap,rs1[i]);
5378 s1h=get_reg(branch_regs[i].regmap,rs1[i]|64);
5379 s2l=get_reg(branch_regs[i].regmap,rs2[i]);
5380 s2h=get_reg(branch_regs[i].regmap,rs2[i]|64);
5381 }
5382 else {
5383 s1l=get_reg(i_regmap,rs1[i]);
5384 s1h=get_reg(i_regmap,rs1[i]|64);
5385 s2l=get_reg(i_regmap,rs2[i]);
5386 s2h=get_reg(i_regmap,rs2[i]|64);
5387 }
5388 if(rs1[i]==0&&rs2[i]==0)
5389 {
5390 if(opcode[i]&1) nop=1;
5391 else unconditional=1;
5392 //assert(opcode[i]!=5);
5393 //assert(opcode[i]!=7);
5394 //assert(opcode[i]!=0x15);
5395 //assert(opcode[i]!=0x17);
5396 }
5397 else if(rs1[i]==0)
5398 {
5399 s1l=s2l;s1h=s2h;
5400 s2l=s2h=-1;
5401 only32=(regs[i].was32>>rs2[i])&1;
5402 }
5403 else if(rs2[i]==0)
5404 {
5405 s2l=s2h=-1;
5406 only32=(regs[i].was32>>rs1[i])&1;
5407 }
5408 else {
5409 only32=(regs[i].was32>>rs1[i])&(regs[i].was32>>rs2[i])&1;
5410 }
5411
e1190b87 5412 if(ooo[i]) {
57871462 5413 // Out of order execution (delay slot first)
5414 //printf("OOOE\n");
5415 address_generation(i+1,i_regs,regs[i].regmap_entry);
5416 ds_assemble(i+1,i_regs);
5417 int adj;
5418 uint64_t bc_unneeded=branch_regs[i].u;
5419 uint64_t bc_unneeded_upper=branch_regs[i].uu;
5420 bc_unneeded&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
5421 bc_unneeded_upper&=~((1LL<<us1[i])|(1LL<<us2[i]));
5422 bc_unneeded|=1;
5423 bc_unneeded_upper|=1;
5424 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5425 bc_unneeded,bc_unneeded_upper);
5426 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i],rs2[i]);
5427 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
5428 cc=get_reg(branch_regs[i].regmap,CCREG);
5429 assert(cc==HOST_CCREG);
5430 if(unconditional)
5431 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5432 //do_cc(i,branch_regs[i].regmap,&adj,unconditional?ba[i]:-1,unconditional);
5433 //assem_debug("cycle count (adj)\n");
5434 if(unconditional) {
5435 do_cc(i,branch_regs[i].regmap,&adj,ba[i],TAKEN,0);
5436 if(i!=(ba[i]-start)>>2 || source[i+1]!=0) {
5437 if(adj) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc);
5438 load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5439 if(internal)
5440 assem_debug("branch: internal\n");
5441 else
5442 assem_debug("branch: external\n");
5443 if(internal&&is_ds[(ba[i]-start)>>2]) {
5444 ds_assemble_entry(i);
5445 }
5446 else {
5447 add_to_linker((int)out,ba[i],internal);
5448 emit_jmp(0);
5449 }
5450 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5451 if(((u_int)out)&7) emit_addnop(0);
5452 #endif
5453 }
5454 }
5455 else if(nop) {
5456 emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),cc);
5457 int jaddr=(int)out;
5458 emit_jns(0);
5459 add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,NOTTAKEN,0);
5460 }
5461 else {
5462 int taken=0,nottaken=0,nottaken1=0;
5463 do_cc(i,branch_regs[i].regmap,&adj,-1,0,invert);
5464 if(adj&&!invert) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc);
5465 if(!only32)
5466 {
5467 assert(s1h>=0);
5468 if(opcode[i]==4) // BEQ
5469 {
5470 if(s2h>=0) emit_cmp(s1h,s2h);
5471 else emit_test(s1h,s1h);
5472 nottaken1=(int)out;
5473 emit_jne(1);
5474 }
5475 if(opcode[i]==5) // BNE
5476 {
5477 if(s2h>=0) emit_cmp(s1h,s2h);
5478 else emit_test(s1h,s1h);
5479 if(invert) taken=(int)out;
5480 else add_to_linker((int)out,ba[i],internal);
5481 emit_jne(0);
5482 }
5483 if(opcode[i]==6) // BLEZ
5484 {
5485 emit_test(s1h,s1h);
5486 if(invert) taken=(int)out;
5487 else add_to_linker((int)out,ba[i],internal);
5488 emit_js(0);
5489 nottaken1=(int)out;
5490 emit_jne(1);
5491 }
5492 if(opcode[i]==7) // BGTZ
5493 {
5494 emit_test(s1h,s1h);
5495 nottaken1=(int)out;
5496 emit_js(1);
5497 if(invert) taken=(int)out;
5498 else add_to_linker((int)out,ba[i],internal);
5499 emit_jne(0);
5500 }
5501 } // if(!only32)
5502
5503 //printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5504 assert(s1l>=0);
5505 if(opcode[i]==4) // BEQ
5506 {
5507 if(s2l>=0) emit_cmp(s1l,s2l);
5508 else emit_test(s1l,s1l);
5509 if(invert){
5510 nottaken=(int)out;
5511 emit_jne(1);
5512 }else{
5513 add_to_linker((int)out,ba[i],internal);
5514 emit_jeq(0);
5515 }
5516 }
5517 if(opcode[i]==5) // BNE
5518 {
5519 if(s2l>=0) emit_cmp(s1l,s2l);
5520 else emit_test(s1l,s1l);
5521 if(invert){
5522 nottaken=(int)out;
5523 emit_jeq(1);
5524 }else{
5525 add_to_linker((int)out,ba[i],internal);
5526 emit_jne(0);
5527 }
5528 }
5529 if(opcode[i]==6) // BLEZ
5530 {
5531 emit_cmpimm(s1l,1);
5532 if(invert){
5533 nottaken=(int)out;
5534 emit_jge(1);
5535 }else{
5536 add_to_linker((int)out,ba[i],internal);
5537 emit_jl(0);
5538 }
5539 }
5540 if(opcode[i]==7) // BGTZ
5541 {
5542 emit_cmpimm(s1l,1);
5543 if(invert){
5544 nottaken=(int)out;
5545 emit_jl(1);
5546 }else{
5547 add_to_linker((int)out,ba[i],internal);
5548 emit_jge(0);
5549 }
5550 }
5551 if(invert) {
5552 if(taken) set_jump_target(taken,(int)out);
5553 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5554 if(match&&(!internal||!is_ds[(ba[i]-start)>>2])) {
5555 if(adj) {
5556 emit_addimm(cc,-CLOCK_DIVIDER*adj,cc);
5557 add_to_linker((int)out,ba[i],internal);
5558 }else{
5559 emit_addnop(13);
5560 add_to_linker((int)out,ba[i],internal*2);
5561 }
5562 emit_jmp(0);
5563 }else
5564 #endif
5565 {
5566 if(adj) emit_addimm(cc,-CLOCK_DIVIDER*adj,cc);
5567 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5568 load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5569 if(internal)
5570 assem_debug("branch: internal\n");
5571 else
5572 assem_debug("branch: external\n");
5573 if(internal&&is_ds[(ba[i]-start)>>2]) {
5574 ds_assemble_entry(i);
5575 }
5576 else {
5577 add_to_linker((int)out,ba[i],internal);
5578 emit_jmp(0);
5579 }
5580 }
5581 set_jump_target(nottaken,(int)out);
5582 }
5583
5584 if(nottaken1) set_jump_target(nottaken1,(int)out);
5585 if(adj) {
5586 if(!invert) emit_addimm(cc,CLOCK_DIVIDER*adj,cc);
5587 }
5588 } // (!unconditional)
5589 } // if(ooo)
5590 else
5591 {
5592 // In-order execution (branch first)
5593 //if(likely[i]) printf("IOL\n");
5594 //else
5595 //printf("IOE\n");
5596 int taken=0,nottaken=0,nottaken1=0;
5597 if(!unconditional&&!nop) {
5598 if(!only32)
5599 {
5600 assert(s1h>=0);
5601 if((opcode[i]&0x2f)==4) // BEQ
5602 {
5603 if(s2h>=0) emit_cmp(s1h,s2h);
5604 else emit_test(s1h,s1h);
5605 nottaken1=(int)out;
5606 emit_jne(2);
5607 }
5608 if((opcode[i]&0x2f)==5) // BNE
5609 {
5610 if(s2h>=0) emit_cmp(s1h,s2h);
5611 else emit_test(s1h,s1h);
5612 taken=(int)out;
5613 emit_jne(1);
5614 }
5615 if((opcode[i]&0x2f)==6) // BLEZ
5616 {
5617 emit_test(s1h,s1h);
5618 taken=(int)out;
5619 emit_js(1);
5620 nottaken1=(int)out;
5621 emit_jne(2);
5622 }
5623 if((opcode[i]&0x2f)==7) // BGTZ
5624 {
5625 emit_test(s1h,s1h);
5626 nottaken1=(int)out;
5627 emit_js(2);
5628 taken=(int)out;
5629 emit_jne(1);
5630 }
5631 } // if(!only32)
5632
5633 //printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5634 assert(s1l>=0);
5635 if((opcode[i]&0x2f)==4) // BEQ
5636 {
5637 if(s2l>=0) emit_cmp(s1l,s2l);
5638 else emit_test(s1l,s1l);
5639 nottaken=(int)out;
5640 emit_jne(2);
5641 }
5642 if((opcode[i]&0x2f)==5) // BNE
5643 {
5644 if(s2l>=0) emit_cmp(s1l,s2l);
5645 else emit_test(s1l,s1l);
5646 nottaken=(int)out;
5647 emit_jeq(2);
5648 }
5649 if((opcode[i]&0x2f)==6) // BLEZ
5650 {
5651 emit_cmpimm(s1l,1);
5652 nottaken=(int)out;
5653 emit_jge(2);
5654 }
5655 if((opcode[i]&0x2f)==7) // BGTZ
5656 {
5657 emit_cmpimm(s1l,1);
5658 nottaken=(int)out;
5659 emit_jl(2);
5660 }
5661 } // if(!unconditional)
5662 int adj;
5663 uint64_t ds_unneeded=branch_regs[i].u;
5664 uint64_t ds_unneeded_upper=branch_regs[i].uu;
5665 ds_unneeded&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
5666 ds_unneeded_upper&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
5667 if((~ds_unneeded_upper>>rt1[i+1])&1) ds_unneeded_upper&=~((1LL<<dep1[i+1])|(1LL<<dep2[i+1]));
5668 ds_unneeded|=1;
5669 ds_unneeded_upper|=1;
5670 // branch taken
5671 if(!nop) {
5672 if(taken) set_jump_target(taken,(int)out);
5673 assem_debug("1:\n");
5674 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5675 ds_unneeded,ds_unneeded_upper);
5676 // load regs
5677 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
5678 address_generation(i+1,&branch_regs[i],0);
5679 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,INVCP);
5680 ds_assemble(i+1,&branch_regs[i]);
5681 cc=get_reg(branch_regs[i].regmap,CCREG);
5682 if(cc==-1) {
5683 emit_loadreg(CCREG,cc=HOST_CCREG);
5684 // CHECK: Is the following instruction (fall thru) allocated ok?
5685 }
5686 assert(cc==HOST_CCREG);
5687 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5688 do_cc(i,i_regmap,&adj,ba[i],TAKEN,0);
5689 assem_debug("cycle count (adj)\n");
5690 if(adj) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc);
5691 load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5692 if(internal)
5693 assem_debug("branch: internal\n");
5694 else
5695 assem_debug("branch: external\n");
5696 if(internal&&is_ds[(ba[i]-start)>>2]) {
5697 ds_assemble_entry(i);
5698 }
5699 else {
5700 add_to_linker((int)out,ba[i],internal);
5701 emit_jmp(0);
5702 }
5703 }
5704 // branch not taken
5705 cop1_usable=prev_cop1_usable;
5706 if(!unconditional) {
5707 if(nottaken1) set_jump_target(nottaken1,(int)out);
5708 set_jump_target(nottaken,(int)out);
5709 assem_debug("2:\n");
5710 if(!likely[i]) {
5711 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5712 ds_unneeded,ds_unneeded_upper);
5713 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
5714 address_generation(i+1,&branch_regs[i],0);
5715 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
5716 ds_assemble(i+1,&branch_regs[i]);
5717 }
5718 cc=get_reg(branch_regs[i].regmap,CCREG);
5719 if(cc==-1&&!likely[i]) {
5720 // Cycle count isn't in a register, temporarily load it then write it out
5721 emit_loadreg(CCREG,HOST_CCREG);
5722 emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),HOST_CCREG);
5723 int jaddr=(int)out;
5724 emit_jns(0);
5725 add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,NOTTAKEN,0);
5726 emit_storereg(CCREG,HOST_CCREG);
5727 }
5728 else{
5729 cc=get_reg(i_regmap,CCREG);
5730 assert(cc==HOST_CCREG);
5731 emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),cc);
5732 int jaddr=(int)out;
5733 emit_jns(0);
5734 add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,likely[i]?NULLDS:NOTTAKEN,0);
5735 }
5736 }
5737 }
5738}
5739
5740void sjump_assemble(int i,struct regstat *i_regs)
5741{
5742 signed char *i_regmap=i_regs->regmap;
5743 int cc;
5744 int match;
5745 match=match_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5746 assem_debug("smatch=%d\n",match);
5747 int s1h,s1l;
5748 int prev_cop1_usable=cop1_usable;
5749 int unconditional=0,nevertaken=0;
5750 int only32=0;
57871462 5751 int invert=0;
5752 int internal=internal_branch(branch_regs[i].is32,ba[i]);
5753 if(i==(ba[i]-start)>>2) assem_debug("idle loop\n");
57871462 5754 if(!match) invert=1;
5755 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5756 if(i>(ba[i]-start)>>2) invert=1;
5757 #endif
5758
5759 //if(opcode2[i]>=0x10) return; // FIXME (BxxZAL)
df894a3a 5760 //assert(opcode2[i]<0x10||rs1[i]==0); // FIXME (BxxZAL)
57871462 5761
e1190b87 5762 if(ooo[i]) {
57871462 5763 s1l=get_reg(branch_regs[i].regmap,rs1[i]);
5764 s1h=get_reg(branch_regs[i].regmap,rs1[i]|64);
5765 }
5766 else {
5767 s1l=get_reg(i_regmap,rs1[i]);
5768 s1h=get_reg(i_regmap,rs1[i]|64);
5769 }
5770 if(rs1[i]==0)
5771 {
5772 if(opcode2[i]&1) unconditional=1;
5773 else nevertaken=1;
5774 // These are never taken (r0 is never less than zero)
5775 //assert(opcode2[i]!=0);
5776 //assert(opcode2[i]!=2);
5777 //assert(opcode2[i]!=0x10);
5778 //assert(opcode2[i]!=0x12);
5779 }
5780 else {
5781 only32=(regs[i].was32>>rs1[i])&1;
5782 }
5783
e1190b87 5784 if(ooo[i]) {
57871462 5785 // Out of order execution (delay slot first)
5786 //printf("OOOE\n");
5787 address_generation(i+1,i_regs,regs[i].regmap_entry);
5788 ds_assemble(i+1,i_regs);
5789 int adj;
5790 uint64_t bc_unneeded=branch_regs[i].u;
5791 uint64_t bc_unneeded_upper=branch_regs[i].uu;
5792 bc_unneeded&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
5793 bc_unneeded_upper&=~((1LL<<us1[i])|(1LL<<us2[i]));
5794 bc_unneeded|=1;
5795 bc_unneeded_upper|=1;
5796 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5797 bc_unneeded,bc_unneeded_upper);
5798 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i],rs1[i]);
5799 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
5800 if(rt1[i]==31) {
5801 int rt,return_address;
57871462 5802 rt=get_reg(branch_regs[i].regmap,31);
5803 assem_debug("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5804 if(rt>=0) {
5805 // Save the PC even if the branch is not taken
5806 return_address=start+i*4+8;
5807 emit_movimm(return_address,rt); // PC into link register
5808 #ifdef IMM_PREFETCH
5809 if(!nevertaken) emit_prefetch(hash_table[((return_address>>16)^return_address)&0xFFFF]);
5810 #endif
5811 }
5812 }
5813 cc=get_reg(branch_regs[i].regmap,CCREG);
5814 assert(cc==HOST_CCREG);
5815 if(unconditional)
5816 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5817 //do_cc(i,branch_regs[i].regmap,&adj,unconditional?ba[i]:-1,unconditional);
5818 assem_debug("cycle count (adj)\n");
5819 if(unconditional) {
5820 do_cc(i,branch_regs[i].regmap,&adj,ba[i],TAKEN,0);
5821 if(i!=(ba[i]-start)>>2 || source[i+1]!=0) {
5822 if(adj) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc);
5823 load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5824 if(internal)
5825 assem_debug("branch: internal\n");
5826 else
5827 assem_debug("branch: external\n");
5828 if(internal&&is_ds[(ba[i]-start)>>2]) {
5829 ds_assemble_entry(i);
5830 }
5831 else {
5832 add_to_linker((int)out,ba[i],internal);
5833 emit_jmp(0);
5834 }
5835 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5836 if(((u_int)out)&7) emit_addnop(0);
5837 #endif
5838 }
5839 }
5840 else if(nevertaken) {
5841 emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),cc);
5842 int jaddr=(int)out;
5843 emit_jns(0);
5844 add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,NOTTAKEN,0);
5845 }
5846 else {
5847 int nottaken=0;
5848 do_cc(i,branch_regs[i].regmap,&adj,-1,0,invert);
5849 if(adj&&!invert) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc);
5850 if(!only32)
5851 {
5852 assert(s1h>=0);
df894a3a 5853 if((opcode2[i]&0xf)==0) // BLTZ/BLTZAL
57871462 5854 {
5855 emit_test(s1h,s1h);
5856 if(invert){
5857 nottaken=(int)out;
5858 emit_jns(1);
5859 }else{
5860 add_to_linker((int)out,ba[i],internal);
5861 emit_js(0);
5862 }
5863 }
df894a3a 5864 if((opcode2[i]&0xf)==1) // BGEZ/BLTZAL
57871462 5865 {
5866 emit_test(s1h,s1h);
5867 if(invert){
5868 nottaken=(int)out;
5869 emit_js(1);
5870 }else{
5871 add_to_linker((int)out,ba[i],internal);
5872 emit_jns(0);
5873 }
5874 }
5875 } // if(!only32)
5876 else
5877 {
5878 assert(s1l>=0);
df894a3a 5879 if((opcode2[i]&0xf)==0) // BLTZ/BLTZAL
57871462 5880 {
5881 emit_test(s1l,s1l);
5882 if(invert){
5883 nottaken=(int)out;
5884 emit_jns(1);
5885 }else{
5886 add_to_linker((int)out,ba[i],internal);
5887 emit_js(0);
5888 }
5889 }
df894a3a 5890 if((opcode2[i]&0xf)==1) // BGEZ/BLTZAL
57871462 5891 {
5892 emit_test(s1l,s1l);
5893 if(invert){
5894 nottaken=(int)out;
5895 emit_js(1);
5896 }else{
5897 add_to_linker((int)out,ba[i],internal);
5898 emit_jns(0);
5899 }
5900 }
5901 } // if(!only32)
5902
5903 if(invert) {
5904 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5905 if(match&&(!internal||!is_ds[(ba[i]-start)>>2])) {
5906 if(adj) {
5907 emit_addimm(cc,-CLOCK_DIVIDER*adj,cc);
5908 add_to_linker((int)out,ba[i],internal);
5909 }else{
5910 emit_addnop(13);
5911 add_to_linker((int)out,ba[i],internal*2);
5912 }
5913 emit_jmp(0);
5914 }else
5915 #endif
5916 {
5917 if(adj) emit_addimm(cc,-CLOCK_DIVIDER*adj,cc);
5918 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5919 load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5920 if(internal)
5921 assem_debug("branch: internal\n");
5922 else
5923 assem_debug("branch: external\n");
5924 if(internal&&is_ds[(ba[i]-start)>>2]) {
5925 ds_assemble_entry(i);
5926 }
5927 else {
5928 add_to_linker((int)out,ba[i],internal);
5929 emit_jmp(0);
5930 }
5931 }
5932 set_jump_target(nottaken,(int)out);
5933 }
5934
5935 if(adj) {
5936 if(!invert) emit_addimm(cc,CLOCK_DIVIDER*adj,cc);
5937 }
5938 } // (!unconditional)
5939 } // if(ooo)
5940 else
5941 {
5942 // In-order execution (branch first)
5943 //printf("IOE\n");
5944 int nottaken=0;
a6491170 5945 if(rt1[i]==31) {
5946 int rt,return_address;
a6491170 5947 rt=get_reg(branch_regs[i].regmap,31);
5948 if(rt>=0) {
5949 // Save the PC even if the branch is not taken
5950 return_address=start+i*4+8;
5951 emit_movimm(return_address,rt); // PC into link register
5952 #ifdef IMM_PREFETCH
5953 emit_prefetch(hash_table[((return_address>>16)^return_address)&0xFFFF]);
5954 #endif
5955 }
5956 }
57871462 5957 if(!unconditional) {
5958 //printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5959 if(!only32)
5960 {
5961 assert(s1h>=0);
a6491170 5962 if((opcode2[i]&0x0d)==0) // BLTZ/BLTZL/BLTZAL/BLTZALL
57871462 5963 {
5964 emit_test(s1h,s1h);
5965 nottaken=(int)out;
5966 emit_jns(1);
5967 }
a6491170 5968 if((opcode2[i]&0x0d)==1) // BGEZ/BGEZL/BGEZAL/BGEZALL
57871462 5969 {
5970 emit_test(s1h,s1h);
5971 nottaken=(int)out;
5972 emit_js(1);
5973 }
5974 } // if(!only32)
5975 else
5976 {
5977 assert(s1l>=0);
a6491170 5978 if((opcode2[i]&0x0d)==0) // BLTZ/BLTZL/BLTZAL/BLTZALL
57871462 5979 {
5980 emit_test(s1l,s1l);
5981 nottaken=(int)out;
5982 emit_jns(1);
5983 }
a6491170 5984 if((opcode2[i]&0x0d)==1) // BGEZ/BGEZL/BGEZAL/BGEZALL
57871462 5985 {
5986 emit_test(s1l,s1l);
5987 nottaken=(int)out;
5988 emit_js(1);
5989 }
5990 }
5991 } // if(!unconditional)
5992 int adj;
5993 uint64_t ds_unneeded=branch_regs[i].u;
5994 uint64_t ds_unneeded_upper=branch_regs[i].uu;
5995 ds_unneeded&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
5996 ds_unneeded_upper&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
5997 if((~ds_unneeded_upper>>rt1[i+1])&1) ds_unneeded_upper&=~((1LL<<dep1[i+1])|(1LL<<dep2[i+1]));
5998 ds_unneeded|=1;
5999 ds_unneeded_upper|=1;
6000 // branch taken
6001 if(!nevertaken) {
6002 //assem_debug("1:\n");
6003 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
6004 ds_unneeded,ds_unneeded_upper);
6005 // load regs
6006 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
6007 address_generation(i+1,&branch_regs[i],0);
6008 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,INVCP);
6009 ds_assemble(i+1,&branch_regs[i]);
6010 cc=get_reg(branch_regs[i].regmap,CCREG);
6011 if(cc==-1) {
6012 emit_loadreg(CCREG,cc=HOST_CCREG);
6013 // CHECK: Is the following instruction (fall thru) allocated ok?
6014 }
6015 assert(cc==HOST_CCREG);
6016 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6017 do_cc(i,i_regmap,&adj,ba[i],TAKEN,0);
6018 assem_debug("cycle count (adj)\n");
6019 if(adj) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc);
6020 load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6021 if(internal)
6022 assem_debug("branch: internal\n");
6023 else
6024 assem_debug("branch: external\n");
6025 if(internal&&is_ds[(ba[i]-start)>>2]) {
6026 ds_assemble_entry(i);
6027 }
6028 else {
6029 add_to_linker((int)out,ba[i],internal);
6030 emit_jmp(0);
6031 }
6032 }
6033 // branch not taken
6034 cop1_usable=prev_cop1_usable;
6035 if(!unconditional) {
6036 set_jump_target(nottaken,(int)out);
6037 assem_debug("1:\n");
6038 if(!likely[i]) {
6039 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
6040 ds_unneeded,ds_unneeded_upper);
6041 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
6042 address_generation(i+1,&branch_regs[i],0);
6043 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
6044 ds_assemble(i+1,&branch_regs[i]);
6045 }
6046 cc=get_reg(branch_regs[i].regmap,CCREG);
6047 if(cc==-1&&!likely[i]) {
6048 // Cycle count isn't in a register, temporarily load it then write it out
6049 emit_loadreg(CCREG,HOST_CCREG);
6050 emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),HOST_CCREG);
6051 int jaddr=(int)out;
6052 emit_jns(0);
6053 add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,NOTTAKEN,0);
6054 emit_storereg(CCREG,HOST_CCREG);
6055 }
6056 else{
6057 cc=get_reg(i_regmap,CCREG);
6058 assert(cc==HOST_CCREG);
6059 emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),cc);
6060 int jaddr=(int)out;
6061 emit_jns(0);
6062 add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,likely[i]?NULLDS:NOTTAKEN,0);
6063 }
6064 }
6065 }
6066}
6067
6068void fjump_assemble(int i,struct regstat *i_regs)
6069{
6070 signed char *i_regmap=i_regs->regmap;
6071 int cc;
6072 int match;
6073 match=match_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6074 assem_debug("fmatch=%d\n",match);
6075 int fs,cs;
6076 int eaddr;
57871462 6077 int invert=0;
6078 int internal=internal_branch(branch_regs[i].is32,ba[i]);
6079 if(i==(ba[i]-start)>>2) assem_debug("idle loop\n");
57871462 6080 if(!match) invert=1;
6081 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
6082 if(i>(ba[i]-start)>>2) invert=1;
6083 #endif
6084
e1190b87 6085 if(ooo[i]) {
57871462 6086 fs=get_reg(branch_regs[i].regmap,FSREG);
6087 address_generation(i+1,i_regs,regs[i].regmap_entry); // Is this okay?
6088 }
6089 else {
6090 fs=get_reg(i_regmap,FSREG);
6091 }
6092
6093 // Check cop1 unusable
6094 if(!cop1_usable) {
6095 cs=get_reg(i_regmap,CSREG);
6096 assert(cs>=0);
6097 emit_testimm(cs,0x20000000);
6098 eaddr=(int)out;
6099 emit_jeq(0);
6100 add_stub(FP_STUB,eaddr,(int)out,i,cs,(int)i_regs,0,0);
6101 cop1_usable=1;
6102 }
6103
e1190b87 6104 if(ooo[i]) {
57871462 6105 // Out of order execution (delay slot first)
6106 //printf("OOOE\n");
6107 ds_assemble(i+1,i_regs);
6108 int adj;
6109 uint64_t bc_unneeded=branch_regs[i].u;
6110 uint64_t bc_unneeded_upper=branch_regs[i].uu;
6111 bc_unneeded&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
6112 bc_unneeded_upper&=~((1LL<<us1[i])|(1LL<<us2[i]));
6113 bc_unneeded|=1;
6114 bc_unneeded_upper|=1;
6115 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
6116 bc_unneeded,bc_unneeded_upper);
6117 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i],rs1[i]);
6118 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
6119 cc=get_reg(branch_regs[i].regmap,CCREG);
6120 assert(cc==HOST_CCREG);
6121 do_cc(i,branch_regs[i].regmap,&adj,-1,0,invert);
6122 assem_debug("cycle count (adj)\n");
6123 if(1) {
6124 int nottaken=0;
6125 if(adj&&!invert) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc);
6126 if(1) {
6127 assert(fs>=0);
6128 emit_testimm(fs,0x800000);
6129 if(source[i]&0x10000) // BC1T
6130 {
6131 if(invert){
6132 nottaken=(int)out;
6133 emit_jeq(1);
6134 }else{
6135 add_to_linker((int)out,ba[i],internal);
6136 emit_jne(0);
6137 }
6138 }
6139 else // BC1F
6140 if(invert){
6141 nottaken=(int)out;
6142 emit_jne(1);
6143 }else{
6144 add_to_linker((int)out,ba[i],internal);
6145 emit_jeq(0);
6146 }
6147 {
6148 }
6149 } // if(!only32)
6150
6151 if(invert) {
6152 if(adj) emit_addimm(cc,-CLOCK_DIVIDER*adj,cc);
6153 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
6154 else if(match) emit_addnop(13);
6155 #endif
6156 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6157 load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6158 if(internal)
6159 assem_debug("branch: internal\n");
6160 else
6161 assem_debug("branch: external\n");
6162 if(internal&&is_ds[(ba[i]-start)>>2]) {
6163 ds_assemble_entry(i);
6164 }
6165 else {
6166 add_to_linker((int)out,ba[i],internal);
6167 emit_jmp(0);
6168 }
6169 set_jump_target(nottaken,(int)out);
6170 }
6171
6172 if(adj) {
6173 if(!invert) emit_addimm(cc,CLOCK_DIVIDER*adj,cc);
6174 }
6175 } // (!unconditional)
6176 } // if(ooo)
6177 else
6178 {
6179 // In-order execution (branch first)
6180 //printf("IOE\n");
6181 int nottaken=0;
6182 if(1) {
6183 //printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
6184 if(1) {
6185 assert(fs>=0);
6186 emit_testimm(fs,0x800000);
6187 if(source[i]&0x10000) // BC1T
6188 {
6189 nottaken=(int)out;
6190 emit_jeq(1);
6191 }
6192 else // BC1F
6193 {
6194 nottaken=(int)out;
6195 emit_jne(1);
6196 }
6197 }
6198 } // if(!unconditional)
6199 int adj;
6200 uint64_t ds_unneeded=branch_regs[i].u;
6201 uint64_t ds_unneeded_upper=branch_regs[i].uu;
6202 ds_unneeded&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
6203 ds_unneeded_upper&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
6204 if((~ds_unneeded_upper>>rt1[i+1])&1) ds_unneeded_upper&=~((1LL<<dep1[i+1])|(1LL<<dep2[i+1]));
6205 ds_unneeded|=1;
6206 ds_unneeded_upper|=1;
6207 // branch taken
6208 //assem_debug("1:\n");
6209 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
6210 ds_unneeded,ds_unneeded_upper);
6211 // load regs
6212 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
6213 address_generation(i+1,&branch_regs[i],0);
6214 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,INVCP);
6215 ds_assemble(i+1,&branch_regs[i]);
6216 cc=get_reg(branch_regs[i].regmap,CCREG);
6217 if(cc==-1) {
6218 emit_loadreg(CCREG,cc=HOST_CCREG);
6219 // CHECK: Is the following instruction (fall thru) allocated ok?
6220 }
6221 assert(cc==HOST_CCREG);
6222 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6223 do_cc(i,i_regmap,&adj,ba[i],TAKEN,0);
6224 assem_debug("cycle count (adj)\n");
6225 if(adj) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc);
6226 load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6227 if(internal)
6228 assem_debug("branch: internal\n");
6229 else
6230 assem_debug("branch: external\n");
6231 if(internal&&is_ds[(ba[i]-start)>>2]) {
6232 ds_assemble_entry(i);
6233 }
6234 else {
6235 add_to_linker((int)out,ba[i],internal);
6236 emit_jmp(0);
6237 }
6238
6239 // branch not taken
6240 if(1) { // <- FIXME (don't need this)
6241 set_jump_target(nottaken,(int)out);
6242 assem_debug("1:\n");
6243 if(!likely[i]) {
6244 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
6245 ds_unneeded,ds_unneeded_upper);
6246 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
6247 address_generation(i+1,&branch_regs[i],0);
6248 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
6249 ds_assemble(i+1,&branch_regs[i]);
6250 }
6251 cc=get_reg(branch_regs[i].regmap,CCREG);
6252 if(cc==-1&&!likely[i]) {
6253 // Cycle count isn't in a register, temporarily load it then write it out
6254 emit_loadreg(CCREG,HOST_CCREG);
6255 emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),HOST_CCREG);
6256 int jaddr=(int)out;
6257 emit_jns(0);
6258 add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,NOTTAKEN,0);
6259 emit_storereg(CCREG,HOST_CCREG);
6260 }
6261 else{
6262 cc=get_reg(i_regmap,CCREG);
6263 assert(cc==HOST_CCREG);
6264 emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),cc);
6265 int jaddr=(int)out;
6266 emit_jns(0);
6267 add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,likely[i]?NULLDS:NOTTAKEN,0);
6268 }
6269 }
6270 }
6271}
6272
6273static void pagespan_assemble(int i,struct regstat *i_regs)
6274{
6275 int s1l=get_reg(i_regs->regmap,rs1[i]);
6276 int s1h=get_reg(i_regs->regmap,rs1[i]|64);
6277 int s2l=get_reg(i_regs->regmap,rs2[i]);
6278 int s2h=get_reg(i_regs->regmap,rs2[i]|64);
6279 void *nt_branch=NULL;
6280 int taken=0;
6281 int nottaken=0;
6282 int unconditional=0;
6283 if(rs1[i]==0)
6284 {
6285 s1l=s2l;s1h=s2h;
6286 s2l=s2h=-1;
6287 }
6288 else if(rs2[i]==0)
6289 {
6290 s2l=s2h=-1;
6291 }
6292 if((i_regs->is32>>rs1[i])&(i_regs->is32>>rs2[i])&1) {
6293 s1h=s2h=-1;
6294 }
6295 int hr=0;
6296 int addr,alt,ntaddr;
6297 if(i_regs->regmap[HOST_BTREG]<0) {addr=HOST_BTREG;}
6298 else {
6299 while(hr<HOST_REGS)
6300 {
6301 if(hr!=EXCLUDE_REG && hr!=HOST_CCREG &&
6302 (i_regs->regmap[hr]&63)!=rs1[i] &&
6303 (i_regs->regmap[hr]&63)!=rs2[i] )
6304 {
6305 addr=hr++;break;
6306 }
6307 hr++;
6308 }
6309 }
6310 while(hr<HOST_REGS)
6311 {
6312 if(hr!=EXCLUDE_REG && hr!=HOST_CCREG && hr!=HOST_BTREG &&
6313 (i_regs->regmap[hr]&63)!=rs1[i] &&
6314 (i_regs->regmap[hr]&63)!=rs2[i] )
6315 {
6316 alt=hr++;break;
6317 }
6318 hr++;
6319 }
6320 if((opcode[i]&0x2E)==6) // BLEZ/BGTZ needs another register
6321 {
6322 while(hr<HOST_REGS)
6323 {
6324 if(hr!=EXCLUDE_REG && hr!=HOST_CCREG && hr!=HOST_BTREG &&
6325 (i_regs->regmap[hr]&63)!=rs1[i] &&
6326 (i_regs->regmap[hr]&63)!=rs2[i] )
6327 {
6328 ntaddr=hr;break;
6329 }
6330 hr++;
6331 }
6332 }
6333 assert(hr<HOST_REGS);
6334 if((opcode[i]&0x2e)==4||opcode[i]==0x11) { // BEQ/BNE/BEQL/BNEL/BC1
6335 load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,CCREG,CCREG);
6336 }
6337 emit_addimm(HOST_CCREG,CLOCK_DIVIDER*(ccadj[i]+2),HOST_CCREG);
6338 if(opcode[i]==2) // J
6339 {
6340 unconditional=1;
6341 }
6342 if(opcode[i]==3) // JAL
6343 {
6344 // TODO: mini_ht
6345 int rt=get_reg(i_regs->regmap,31);
6346 emit_movimm(start+i*4+8,rt);
6347 unconditional=1;
6348 }
6349 if(opcode[i]==0&&(opcode2[i]&0x3E)==8) // JR/JALR
6350 {
6351 emit_mov(s1l,addr);
6352 if(opcode2[i]==9) // JALR
6353 {
5067f341 6354 int rt=get_reg(i_regs->regmap,rt1[i]);
57871462 6355 emit_movimm(start+i*4+8,rt);
6356 }
6357 }
6358 if((opcode[i]&0x3f)==4) // BEQ
6359 {
6360 if(rs1[i]==rs2[i])
6361 {
6362 unconditional=1;
6363 }
6364 else
6365 #ifdef HAVE_CMOV_IMM
6366 if(s1h<0) {
6367 if(s2l>=0) emit_cmp(s1l,s2l);
6368 else emit_test(s1l,s1l);
6369 emit_cmov2imm_e_ne_compact(ba[i],start+i*4+8,addr);
6370 }
6371 else
6372 #endif
6373 {
6374 assert(s1l>=0);
6375 emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
6376 if(s1h>=0) {
6377 if(s2h>=0) emit_cmp(s1h,s2h);
6378 else emit_test(s1h,s1h);
6379 emit_cmovne_reg(alt,addr);
6380 }
6381 if(s2l>=0) emit_cmp(s1l,s2l);
6382 else emit_test(s1l,s1l);
6383 emit_cmovne_reg(alt,addr);
6384 }
6385 }
6386 if((opcode[i]&0x3f)==5) // BNE
6387 {
6388 #ifdef HAVE_CMOV_IMM
6389 if(s1h<0) {
6390 if(s2l>=0) emit_cmp(s1l,s2l);
6391 else emit_test(s1l,s1l);
6392 emit_cmov2imm_e_ne_compact(start+i*4+8,ba[i],addr);
6393 }
6394 else
6395 #endif
6396 {
6397 assert(s1l>=0);
6398 emit_mov2imm_compact(start+i*4+8,addr,ba[i],alt);
6399 if(s1h>=0) {
6400 if(s2h>=0) emit_cmp(s1h,s2h);
6401 else emit_test(s1h,s1h);
6402 emit_cmovne_reg(alt,addr);
6403 }
6404 if(s2l>=0) emit_cmp(s1l,s2l);
6405 else emit_test(s1l,s1l);
6406 emit_cmovne_reg(alt,addr);
6407 }
6408 }
6409 if((opcode[i]&0x3f)==0x14) // BEQL
6410 {
6411 if(s1h>=0) {
6412 if(s2h>=0) emit_cmp(s1h,s2h);
6413 else emit_test(s1h,s1h);
6414 nottaken=(int)out;
6415 emit_jne(0);
6416 }
6417 if(s2l>=0) emit_cmp(s1l,s2l);
6418 else emit_test(s1l,s1l);
6419 if(nottaken) set_jump_target(nottaken,(int)out);
6420 nottaken=(int)out;
6421 emit_jne(0);
6422 }
6423 if((opcode[i]&0x3f)==0x15) // BNEL
6424 {
6425 if(s1h>=0) {
6426 if(s2h>=0) emit_cmp(s1h,s2h);
6427 else emit_test(s1h,s1h);
6428 taken=(int)out;
6429 emit_jne(0);
6430 }
6431 if(s2l>=0) emit_cmp(s1l,s2l);
6432 else emit_test(s1l,s1l);
6433 nottaken=(int)out;
6434 emit_jeq(0);
6435 if(taken) set_jump_target(taken,(int)out);
6436 }
6437 if((opcode[i]&0x3f)==6) // BLEZ
6438 {
6439 emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
6440 emit_cmpimm(s1l,1);
6441 if(s1h>=0) emit_mov(addr,ntaddr);
6442 emit_cmovl_reg(alt,addr);
6443 if(s1h>=0) {
6444 emit_test(s1h,s1h);
6445 emit_cmovne_reg(ntaddr,addr);
6446 emit_cmovs_reg(alt,addr);
6447 }
6448 }
6449 if((opcode[i]&0x3f)==7) // BGTZ
6450 {
6451 emit_mov2imm_compact(ba[i],addr,start+i*4+8,ntaddr);
6452 emit_cmpimm(s1l,1);
6453 if(s1h>=0) emit_mov(addr,alt);
6454 emit_cmovl_reg(ntaddr,addr);
6455 if(s1h>=0) {
6456 emit_test(s1h,s1h);
6457 emit_cmovne_reg(alt,addr);
6458 emit_cmovs_reg(ntaddr,addr);
6459 }
6460 }
6461 if((opcode[i]&0x3f)==0x16) // BLEZL
6462 {
6463 assert((opcode[i]&0x3f)!=0x16);
6464 }
6465 if((opcode[i]&0x3f)==0x17) // BGTZL
6466 {
6467 assert((opcode[i]&0x3f)!=0x17);
6468 }
6469 assert(opcode[i]!=1); // BLTZ/BGEZ
6470
6471 //FIXME: Check CSREG
6472 if(opcode[i]==0x11 && opcode2[i]==0x08 ) {
6473 if((source[i]&0x30000)==0) // BC1F
6474 {
6475 emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
6476 emit_testimm(s1l,0x800000);
6477 emit_cmovne_reg(alt,addr);
6478 }
6479 if((source[i]&0x30000)==0x10000) // BC1T
6480 {
6481 emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
6482 emit_testimm(s1l,0x800000);
6483 emit_cmovne_reg(alt,addr);
6484 }
6485 if((source[i]&0x30000)==0x20000) // BC1FL
6486 {
6487 emit_testimm(s1l,0x800000);
6488 nottaken=(int)out;
6489 emit_jne(0);
6490 }
6491 if((source[i]&0x30000)==0x30000) // BC1TL
6492 {
6493 emit_testimm(s1l,0x800000);
6494 nottaken=(int)out;
6495 emit_jeq(0);
6496 }
6497 }
6498
6499 assert(i_regs->regmap[HOST_CCREG]==CCREG);
6500 wb_dirtys(regs[i].regmap,regs[i].is32,regs[i].dirty);
6501 if(likely[i]||unconditional)
6502 {
6503 emit_movimm(ba[i],HOST_BTREG);
6504 }
6505 else if(addr!=HOST_BTREG)
6506 {
6507 emit_mov(addr,HOST_BTREG);
6508 }
6509 void *branch_addr=out;
6510 emit_jmp(0);
6511 int target_addr=start+i*4+5;
6512 void *stub=out;
6513 void *compiled_target_addr=check_addr(target_addr);
6514 emit_extjump_ds((int)branch_addr,target_addr);
6515 if(compiled_target_addr) {
6516 set_jump_target((int)branch_addr,(int)compiled_target_addr);
6517 add_link(target_addr,stub);
6518 }
6519 else set_jump_target((int)branch_addr,(int)stub);
6520 if(likely[i]) {
6521 // Not-taken path
6522 set_jump_target((int)nottaken,(int)out);
6523 wb_dirtys(regs[i].regmap,regs[i].is32,regs[i].dirty);
6524 void *branch_addr=out;
6525 emit_jmp(0);
6526 int target_addr=start+i*4+8;
6527 void *stub=out;
6528 void *compiled_target_addr=check_addr(target_addr);
6529 emit_extjump_ds((int)branch_addr,target_addr);
6530 if(compiled_target_addr) {
6531 set_jump_target((int)branch_addr,(int)compiled_target_addr);
6532 add_link(target_addr,stub);
6533 }
6534 else set_jump_target((int)branch_addr,(int)stub);
6535 }
6536}
6537
6538// Assemble the delay slot for the above
6539static void pagespan_ds()
6540{
6541 assem_debug("initial delay slot:\n");
6542 u_int vaddr=start+1;
94d23bb9 6543 u_int page=get_page(vaddr);
6544 u_int vpage=get_vpage(vaddr);
57871462 6545 ll_add(jump_dirty+vpage,vaddr,(void *)out);
6546 do_dirty_stub_ds();
6547 ll_add(jump_in+page,vaddr,(void *)out);
6548 assert(regs[0].regmap_entry[HOST_CCREG]==CCREG);
6549 if(regs[0].regmap[HOST_CCREG]!=CCREG)
6550 wb_register(CCREG,regs[0].regmap_entry,regs[0].wasdirty,regs[0].was32);
6551 if(regs[0].regmap[HOST_BTREG]!=BTREG)
6552 emit_writeword(HOST_BTREG,(int)&branch_target);
6553 load_regs(regs[0].regmap_entry,regs[0].regmap,regs[0].was32,rs1[0],rs2[0]);
6554 address_generation(0,&regs[0],regs[0].regmap_entry);
b9b61529 6555 if(itype[0]==STORE||itype[0]==STORELR||(opcode[0]&0x3b)==0x39||(opcode[0]&0x3b)==0x3a)
57871462 6556 load_regs(regs[0].regmap_entry,regs[0].regmap,regs[0].was32,INVCP,INVCP);
6557 cop1_usable=0;
6558 is_delayslot=0;
6559 switch(itype[0]) {
6560 case ALU:
6561 alu_assemble(0,&regs[0]);break;
6562 case IMM16:
6563 imm16_assemble(0,&regs[0]);break;
6564 case SHIFT:
6565 shift_assemble(0,&regs[0]);break;
6566 case SHIFTIMM:
6567 shiftimm_assemble(0,&regs[0]);break;
6568 case LOAD:
6569 load_assemble(0,&regs[0]);break;
6570 case LOADLR:
6571 loadlr_assemble(0,&regs[0]);break;
6572 case STORE:
6573 store_assemble(0,&regs[0]);break;
6574 case STORELR:
6575 storelr_assemble(0,&regs[0]);break;
6576 case COP0:
6577 cop0_assemble(0,&regs[0]);break;
6578 case COP1:
6579 cop1_assemble(0,&regs[0]);break;
6580 case C1LS:
6581 c1ls_assemble(0,&regs[0]);break;
b9b61529 6582 case COP2:
6583 cop2_assemble(0,&regs[0]);break;
6584 case C2LS:
6585 c2ls_assemble(0,&regs[0]);break;
6586 case C2OP:
6587 c2op_assemble(0,&regs[0]);break;
57871462 6588 case FCONV:
6589 fconv_assemble(0,&regs[0]);break;
6590 case FLOAT:
6591 float_assemble(0,&regs[0]);break;
6592 case FCOMP:
6593 fcomp_assemble(0,&regs[0]);break;
6594 case MULTDIV:
6595 multdiv_assemble(0,&regs[0]);break;
6596 case MOV:
6597 mov_assemble(0,&regs[0]);break;
6598 case SYSCALL:
7139f3c8 6599 case HLECALL:
1e973cb0 6600 case INTCALL:
57871462 6601 case SPAN:
6602 case UJUMP:
6603 case RJUMP:
6604 case CJUMP:
6605 case SJUMP:
6606 case FJUMP:
6607 printf("Jump in the delay slot. This is probably a bug.\n");
6608 }
6609 int btaddr=get_reg(regs[0].regmap,BTREG);
6610 if(btaddr<0) {
6611 btaddr=get_reg(regs[0].regmap,-1);
6612 emit_readword((int)&branch_target,btaddr);
6613 }
6614 assert(btaddr!=HOST_CCREG);
6615 if(regs[0].regmap[HOST_CCREG]!=CCREG) emit_loadreg(CCREG,HOST_CCREG);
6616#ifdef HOST_IMM8
6617 emit_movimm(start+4,HOST_TEMPREG);
6618 emit_cmp(btaddr,HOST_TEMPREG);
6619#else
6620 emit_cmpimm(btaddr,start+4);
6621#endif
6622 int branch=(int)out;
6623 emit_jeq(0);
6624 store_regs_bt(regs[0].regmap,regs[0].is32,regs[0].dirty,-1);
6625 emit_jmp(jump_vaddr_reg[btaddr]);
6626 set_jump_target(branch,(int)out);
6627 store_regs_bt(regs[0].regmap,regs[0].is32,regs[0].dirty,start+4);
6628 load_regs_bt(regs[0].regmap,regs[0].is32,regs[0].dirty,start+4);
6629}
6630
6631// Basic liveness analysis for MIPS registers
6632void unneeded_registers(int istart,int iend,int r)
6633{
6634 int i;
6635 uint64_t u,uu,b,bu;
6636 uint64_t temp_u,temp_uu;
6637 uint64_t tdep;
6638 if(iend==slen-1) {
6639 u=1;uu=1;
6640 }else{
6641 u=unneeded_reg[iend+1];
6642 uu=unneeded_reg_upper[iend+1];
6643 u=1;uu=1;
6644 }
6645 for (i=iend;i>=istart;i--)
6646 {
6647 //printf("unneeded registers i=%d (%d,%d) r=%d\n",i,istart,iend,r);
6648 if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
6649 {
6650 // If subroutine call, flag return address as a possible branch target
6651 if(rt1[i]==31 && i<slen-2) bt[i+2]=1;
6652
6653 if(ba[i]<start || ba[i]>=(start+slen*4))
6654 {
6655 // Branch out of this block, flush all regs
6656 u=1;
6657 uu=1;
6658 /* Hexagon hack
6659 if(itype[i]==UJUMP&&rt1[i]==31)
6660 {
6661 uu=u=0x300C00F; // Discard at, v0-v1, t6-t9
6662 }
6663 if(itype[i]==RJUMP&&rs1[i]==31)
6664 {
6665 uu=u=0x300C0F3; // Discard at, a0-a3, t6-t9
6666 }
4cb76aa4 6667 if(start>0x80000400&&start<0x80000000+RAM_SIZE) {
57871462 6668 if(itype[i]==UJUMP&&rt1[i]==31)
6669 {
6670 //uu=u=0x30300FF0FLL; // Discard at, v0-v1, t0-t9, lo, hi
6671 uu=u=0x300FF0F; // Discard at, v0-v1, t0-t9
6672 }
6673 if(itype[i]==RJUMP&&rs1[i]==31)
6674 {
6675 //uu=u=0x30300FFF3LL; // Discard at, a0-a3, t0-t9, lo, hi
6676 uu=u=0x300FFF3; // Discard at, a0-a3, t0-t9
6677 }
6678 }*/
6679 branch_unneeded_reg[i]=u;
6680 branch_unneeded_reg_upper[i]=uu;
6681 // Merge in delay slot
6682 tdep=(~uu>>rt1[i+1])&1;
6683 u|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6684 uu|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6685 u&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
6686 uu&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
6687 uu&=~((tdep<<dep1[i+1])|(tdep<<dep2[i+1]));
6688 u|=1;uu|=1;
6689 // If branch is "likely" (and conditional)
6690 // then we skip the delay slot on the fall-thru path
6691 if(likely[i]) {
6692 if(i<slen-1) {
6693 u&=unneeded_reg[i+2];
6694 uu&=unneeded_reg_upper[i+2];
6695 }
6696 else
6697 {
6698 u=1;
6699 uu=1;
6700 }
6701 }
6702 }
6703 else
6704 {
6705 // Internal branch, flag target
6706 bt[(ba[i]-start)>>2]=1;
6707 if(ba[i]<=start+i*4) {
6708 // Backward branch
6709 if(itype[i]==RJUMP||itype[i]==UJUMP||(source[i]>>16)==0x1000)
6710 {
6711 // Unconditional branch
6712 temp_u=1;temp_uu=1;
6713 } else {
6714 // Conditional branch (not taken case)
6715 temp_u=unneeded_reg[i+2];
6716 temp_uu=unneeded_reg_upper[i+2];
6717 }
6718 // Merge in delay slot
6719 tdep=(~temp_uu>>rt1[i+1])&1;
6720 temp_u|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6721 temp_uu|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6722 temp_u&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
6723 temp_uu&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
6724 temp_uu&=~((tdep<<dep1[i+1])|(tdep<<dep2[i+1]));
6725 temp_u|=1;temp_uu|=1;
6726 // If branch is "likely" (and conditional)
6727 // then we skip the delay slot on the fall-thru path
6728 if(likely[i]) {
6729 if(i<slen-1) {
6730 temp_u&=unneeded_reg[i+2];
6731 temp_uu&=unneeded_reg_upper[i+2];
6732 }
6733 else
6734 {
6735 temp_u=1;
6736 temp_uu=1;
6737 }
6738 }
6739 tdep=(~temp_uu>>rt1[i])&1;
6740 temp_u|=(1LL<<rt1[i])|(1LL<<rt2[i]);
6741 temp_uu|=(1LL<<rt1[i])|(1LL<<rt2[i]);
6742 temp_u&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
6743 temp_uu&=~((1LL<<us1[i])|(1LL<<us2[i]));
6744 temp_uu&=~((tdep<<dep1[i])|(tdep<<dep2[i]));
6745 temp_u|=1;temp_uu|=1;
6746 unneeded_reg[i]=temp_u;
6747 unneeded_reg_upper[i]=temp_uu;
6748 // Only go three levels deep. This recursion can take an
6749 // excessive amount of time if there are a lot of nested loops.
6750 if(r<2) {
6751 unneeded_registers((ba[i]-start)>>2,i-1,r+1);
6752 }else{
6753 unneeded_reg[(ba[i]-start)>>2]=1;
6754 unneeded_reg_upper[(ba[i]-start)>>2]=1;
6755 }
6756 } /*else*/ if(1) {
6757 if(itype[i]==RJUMP||itype[i]==UJUMP||(source[i]>>16)==0x1000)
6758 {
6759 // Unconditional branch
6760 u=unneeded_reg[(ba[i]-start)>>2];
6761 uu=unneeded_reg_upper[(ba[i]-start)>>2];
6762 branch_unneeded_reg[i]=u;
6763 branch_unneeded_reg_upper[i]=uu;
6764 //u=1;
6765 //uu=1;
6766 //branch_unneeded_reg[i]=u;
6767 //branch_unneeded_reg_upper[i]=uu;
6768 // Merge in delay slot
6769 tdep=(~uu>>rt1[i+1])&1;
6770 u|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6771 uu|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6772 u&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
6773 uu&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
6774 uu&=~((tdep<<dep1[i+1])|(tdep<<dep2[i+1]));
6775 u|=1;uu|=1;
6776 } else {
6777 // Conditional branch
6778 b=unneeded_reg[(ba[i]-start)>>2];
6779 bu=unneeded_reg_upper[(ba[i]-start)>>2];
6780 branch_unneeded_reg[i]=b;
6781 branch_unneeded_reg_upper[i]=bu;
6782 //b=1;
6783 //bu=1;
6784 //branch_unneeded_reg[i]=b;
6785 //branch_unneeded_reg_upper[i]=bu;
6786 // Branch delay slot
6787 tdep=(~uu>>rt1[i+1])&1;
6788 b|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6789 bu|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6790 b&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
6791 bu&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
6792 bu&=~((tdep<<dep1[i+1])|(tdep<<dep2[i+1]));
6793 b|=1;bu|=1;
6794 // If branch is "likely" then we skip the
6795 // delay slot on the fall-thru path
6796 if(likely[i]) {
6797 u=b;
6798 uu=bu;
6799 if(i<slen-1) {
6800 u&=unneeded_reg[i+2];
6801 uu&=unneeded_reg_upper[i+2];
6802 //u=1;
6803 //uu=1;
6804 }
6805 } else {
6806 u&=b;
6807 uu&=bu;
6808 //u=1;
6809 //uu=1;
6810 }
6811 if(i<slen-1) {
6812 branch_unneeded_reg[i]&=unneeded_reg[i+2];
6813 branch_unneeded_reg_upper[i]&=unneeded_reg_upper[i+2];
6814 //branch_unneeded_reg[i]=1;
6815 //branch_unneeded_reg_upper[i]=1;
6816 } else {
6817 branch_unneeded_reg[i]=1;
6818 branch_unneeded_reg_upper[i]=1;
6819 }
6820 }
6821 }
6822 }
6823 }
1e973cb0 6824 else if(itype[i]==SYSCALL||itype[i]==HLECALL||itype[i]==INTCALL)
57871462 6825 {
6826 // SYSCALL instruction (software interrupt)
6827 u=1;
6828 uu=1;
6829 }
6830 else if(itype[i]==COP0 && (source[i]&0x3f)==0x18)
6831 {
6832 // ERET instruction (return from interrupt)
6833 u=1;
6834 uu=1;
6835 }
6836 //u=uu=1; // DEBUG
6837 tdep=(~uu>>rt1[i])&1;
6838 // Written registers are unneeded
6839 u|=1LL<<rt1[i];
6840 u|=1LL<<rt2[i];
6841 uu|=1LL<<rt1[i];
6842 uu|=1LL<<rt2[i];
6843 // Accessed registers are needed
6844 u&=~(1LL<<rs1[i]);
6845 u&=~(1LL<<rs2[i]);
6846 uu&=~(1LL<<us1[i]);
6847 uu&=~(1LL<<us2[i]);
6848 // Source-target dependencies
6849 uu&=~(tdep<<dep1[i]);
6850 uu&=~(tdep<<dep2[i]);
6851 // R0 is always unneeded
6852 u|=1;uu|=1;
6853 // Save it
6854 unneeded_reg[i]=u;
6855 unneeded_reg_upper[i]=uu;
6856 /*
6857 printf("ur (%d,%d) %x: ",istart,iend,start+i*4);
6858 printf("U:");
6859 int r;
6860 for(r=1;r<=CCREG;r++) {
6861 if((unneeded_reg[i]>>r)&1) {
6862 if(r==HIREG) printf(" HI");
6863 else if(r==LOREG) printf(" LO");
6864 else printf(" r%d",r);
6865 }
6866 }
6867 printf(" UU:");
6868 for(r=1;r<=CCREG;r++) {
6869 if(((unneeded_reg_upper[i]&~unneeded_reg[i])>>r)&1) {
6870 if(r==HIREG) printf(" HI");
6871 else if(r==LOREG) printf(" LO");
6872 else printf(" r%d",r);
6873 }
6874 }
6875 printf("\n");*/
6876 }
252c20fc 6877#ifdef FORCE32
6878 for (i=iend;i>=istart;i--)
6879 {
6880 unneeded_reg_upper[i]=branch_unneeded_reg_upper[i]=-1LL;
6881 }
6882#endif
57871462 6883}
6884
6885// Identify registers which are likely to contain 32-bit values
6886// This is used to predict whether any branches will jump to a
6887// location with 64-bit values in registers.
6888static void provisional_32bit()
6889{
6890 int i,j;
6891 uint64_t is32=1;
6892 uint64_t lastbranch=1;
6893
6894 for(i=0;i<slen;i++)
6895 {
6896 if(i>0) {
6897 if(itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP) {
6898 if(i>1) is32=lastbranch;
6899 else is32=1;
6900 }
6901 }
6902 if(i>1)
6903 {
6904 if(itype[i-2]==CJUMP||itype[i-2]==SJUMP||itype[i-2]==FJUMP) {
6905 if(likely[i-2]) {
6906 if(i>2) is32=lastbranch;
6907 else is32=1;
6908 }
6909 }
6910 if((opcode[i-2]&0x2f)==0x05) // BNE/BNEL
6911 {
6912 if(rs1[i-2]==0||rs2[i-2]==0)
6913 {
6914 if(rs1[i-2]) {
6915 is32|=1LL<<rs1[i-2];
6916 }
6917 if(rs2[i-2]) {
6918 is32|=1LL<<rs2[i-2];
6919 }
6920 }
6921 }
6922 }
6923 // If something jumps here with 64-bit values
6924 // then promote those registers to 64 bits
6925 if(bt[i])
6926 {
6927 uint64_t temp_is32=is32;
6928 for(j=i-1;j>=0;j--)
6929 {
6930 if(ba[j]==start+i*4)
6931 //temp_is32&=branch_regs[j].is32;
6932 temp_is32&=p32[j];
6933 }
6934 for(j=i;j<slen;j++)
6935 {
6936 if(ba[j]==start+i*4)
6937 temp_is32=1;
6938 }
6939 is32=temp_is32;
6940 }
6941 int type=itype[i];
6942 int op=opcode[i];
6943 int op2=opcode2[i];
6944 int rt=rt1[i];
6945 int s1=rs1[i];
6946 int s2=rs2[i];
6947 if(type==UJUMP||type==RJUMP||type==CJUMP||type==SJUMP||type==FJUMP) {
6948 // Branches don't write registers, consider the delay slot instead.
6949 type=itype[i+1];
6950 op=opcode[i+1];
6951 op2=opcode2[i+1];
6952 rt=rt1[i+1];
6953 s1=rs1[i+1];
6954 s2=rs2[i+1];
6955 lastbranch=is32;
6956 }
6957 switch(type) {
6958 case LOAD:
6959 if(opcode[i]==0x27||opcode[i]==0x37|| // LWU/LD
6960 opcode[i]==0x1A||opcode[i]==0x1B) // LDL/LDR
6961 is32&=~(1LL<<rt);
6962 else
6963 is32|=1LL<<rt;
6964 break;
6965 case STORE:
6966 case STORELR:
6967 break;
6968 case LOADLR:
6969 if(op==0x1a||op==0x1b) is32&=~(1LL<<rt); // LDR/LDL
6970 if(op==0x22) is32|=1LL<<rt; // LWL
6971 break;
6972 case IMM16:
6973 if (op==0x08||op==0x09|| // ADDI/ADDIU
6974 op==0x0a||op==0x0b|| // SLTI/SLTIU
6975 op==0x0c|| // ANDI
6976 op==0x0f) // LUI
6977 {
6978 is32|=1LL<<rt;
6979 }
6980 if(op==0x18||op==0x19) { // DADDI/DADDIU
6981 is32&=~(1LL<<rt);
6982 //if(imm[i]==0)
6983 // is32|=((is32>>s1)&1LL)<<rt;
6984 }
6985 if(op==0x0d||op==0x0e) { // ORI/XORI
6986 uint64_t sr=((is32>>s1)&1LL);
6987 is32&=~(1LL<<rt);
6988 is32|=sr<<rt;
6989 }
6990 break;
6991 case UJUMP:
6992 break;
6993 case RJUMP:
6994 break;
6995 case CJUMP:
6996 break;
6997 case SJUMP:
6998 break;
6999 case FJUMP:
7000 break;
7001 case ALU:
7002 if(op2>=0x20&&op2<=0x23) { // ADD/ADDU/SUB/SUBU
7003 is32|=1LL<<rt;
7004 }
7005 if(op2==0x2a||op2==0x2b) { // SLT/SLTU
7006 is32|=1LL<<rt;
7007 }
7008 else if(op2>=0x24&&op2<=0x27) { // AND/OR/XOR/NOR
7009 uint64_t sr=((is32>>s1)&(is32>>s2)&1LL);
7010 is32&=~(1LL<<rt);
7011 is32|=sr<<rt;
7012 }
7013 else if(op2>=0x2c&&op2<=0x2d) { // DADD/DADDU
7014 if(s1==0&&s2==0) {
7015 is32|=1LL<<rt;
7016 }
7017 else if(s2==0) {
7018 uint64_t sr=((is32>>s1)&1LL);
7019 is32&=~(1LL<<rt);
7020 is32|=sr<<rt;
7021 }
7022 else if(s1==0) {
7023 uint64_t sr=((is32>>s2)&1LL);
7024 is32&=~(1LL<<rt);
7025 is32|=sr<<rt;
7026 }
7027 else {
7028 is32&=~(1LL<<rt);
7029 }
7030 }
7031 else if(op2>=0x2e&&op2<=0x2f) { // DSUB/DSUBU
7032 if(s1==0&&s2==0) {
7033 is32|=1LL<<rt;
7034 }
7035 else if(s2==0) {
7036 uint64_t sr=((is32>>s1)&1LL);
7037 is32&=~(1LL<<rt);
7038 is32|=sr<<rt;
7039 }
7040 else {
7041 is32&=~(1LL<<rt);
7042 }
7043 }
7044 break;
7045 case MULTDIV:
7046 if (op2>=0x1c&&op2<=0x1f) { // DMULT/DMULTU/DDIV/DDIVU
7047 is32&=~((1LL<<HIREG)|(1LL<<LOREG));
7048 }
7049 else {
7050 is32|=(1LL<<HIREG)|(1LL<<LOREG);
7051 }
7052 break;
7053 case MOV:
7054 {
7055 uint64_t sr=((is32>>s1)&1LL);
7056 is32&=~(1LL<<rt);
7057 is32|=sr<<rt;
7058 }
7059 break;
7060 case SHIFT:
7061 if(op2>=0x14&&op2<=0x17) is32&=~(1LL<<rt); // DSLLV/DSRLV/DSRAV
7062 else is32|=1LL<<rt; // SLLV/SRLV/SRAV
7063 break;
7064 case SHIFTIMM:
7065 is32|=1LL<<rt;
7066 // DSLL/DSRL/DSRA/DSLL32/DSRL32 but not DSRA32 have 64-bit result
7067 if(op2>=0x38&&op2<0x3f) is32&=~(1LL<<rt);
7068 break;
7069 case COP0:
7070 if(op2==0) is32|=1LL<<rt; // MFC0
7071 break;
7072 case COP1:
b9b61529 7073 case COP2:
57871462 7074 if(op2==0) is32|=1LL<<rt; // MFC1
7075 if(op2==1) is32&=~(1LL<<rt); // DMFC1
7076 if(op2==2) is32|=1LL<<rt; // CFC1
7077 break;
7078 case C1LS:
b9b61529 7079 case C2LS:
57871462 7080 break;
7081 case FLOAT:
7082 case FCONV:
7083 break;
7084 case FCOMP:
7085 break;
b9b61529 7086 case C2OP:
57871462 7087 case SYSCALL:
7139f3c8 7088 case HLECALL:
57871462 7089 break;
7090 default:
7091 break;
7092 }
7093 is32|=1;
7094 p32[i]=is32;
7095
7096 if(i>0)
7097 {
7098 if(itype[i-1]==UJUMP||itype[i-1]==RJUMP||(source[i-1]>>16)==0x1000)
7099 {
7100 if(rt1[i-1]==31) // JAL/JALR
7101 {
7102 // Subroutine call will return here, don't alloc any registers
7103 is32=1;
7104 }
7105 else if(i+1<slen)
7106 {
7107 // Internal branch will jump here, match registers to caller
7108 is32=0x3FFFFFFFFLL;
7109 }
7110 }
7111 }
7112 }
7113}
7114
7115// Identify registers which may be assumed to contain 32-bit values
7116// and where optimizations will rely on this.
7117// This is used to determine whether backward branches can safely
7118// jump to a location with 64-bit values in registers.
7119static void provisional_r32()
7120{
7121 u_int r32=0;
7122 int i;
7123
7124 for (i=slen-1;i>=0;i--)
7125 {
7126 int hr;
7127 if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
7128 {
7129 if(ba[i]<start || ba[i]>=(start+slen*4))
7130 {
7131 // Branch out of this block, don't need anything
7132 r32=0;
7133 }
7134 else
7135 {
7136 // Internal branch
7137 // Need whatever matches the target
7138 // (and doesn't get overwritten by the delay slot instruction)
7139 r32=0;
7140 int t=(ba[i]-start)>>2;
7141 if(ba[i]>start+i*4) {
7142 // Forward branch
7143 //if(!(requires_32bit[t]&~regs[i].was32))
7144 // r32|=requires_32bit[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
7145 if(!(pr32[t]&~regs[i].was32))
7146 r32|=pr32[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
7147 }else{
7148 // Backward branch
7149 if(!(regs[t].was32&~unneeded_reg_upper[t]&~regs[i].was32))
7150 r32|=regs[t].was32&~unneeded_reg_upper[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
7151 }
7152 }
7153 // Conditional branch may need registers for following instructions
7154 if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000)
7155 {
7156 if(i<slen-2) {
7157 //r32|=requires_32bit[i+2];
7158 r32|=pr32[i+2];
7159 r32&=regs[i].was32;
7160 // Mark this address as a branch target since it may be called
7161 // upon return from interrupt
7162 //bt[i+2]=1;
7163 }
7164 }
7165 // Merge in delay slot
7166 if(!likely[i]) {
7167 // These are overwritten unless the branch is "likely"
7168 // and the delay slot is nullified if not taken
7169 r32&=~(1LL<<rt1[i+1]);
7170 r32&=~(1LL<<rt2[i+1]);
7171 }
7172 // Assume these are needed (delay slot)
7173 if(us1[i+1]>0)
7174 {
7175 if((regs[i].was32>>us1[i+1])&1) r32|=1LL<<us1[i+1];
7176 }
7177 if(us2[i+1]>0)
7178 {
7179 if((regs[i].was32>>us2[i+1])&1) r32|=1LL<<us2[i+1];
7180 }
7181 if(dep1[i+1]&&!((unneeded_reg_upper[i]>>dep1[i+1])&1))
7182 {
7183 if((regs[i].was32>>dep1[i+1])&1) r32|=1LL<<dep1[i+1];
7184 }
7185 if(dep2[i+1]&&!((unneeded_reg_upper[i]>>dep2[i+1])&1))
7186 {
7187 if((regs[i].was32>>dep2[i+1])&1) r32|=1LL<<dep2[i+1];
7188 }
7189 }
1e973cb0 7190 else if(itype[i]==SYSCALL||itype[i]==HLECALL||itype[i]==INTCALL)
57871462 7191 {
7192 // SYSCALL instruction (software interrupt)
7193 r32=0;
7194 }
7195 else if(itype[i]==COP0 && (source[i]&0x3f)==0x18)
7196 {
7197 // ERET instruction (return from interrupt)
7198 r32=0;
7199 }
7200 // Check 32 bits
7201 r32&=~(1LL<<rt1[i]);
7202 r32&=~(1LL<<rt2[i]);
7203 if(us1[i]>0)
7204 {
7205 if((regs[i].was32>>us1[i])&1) r32|=1LL<<us1[i];
7206 }
7207 if(us2[i]>0)
7208 {
7209 if((regs[i].was32>>us2[i])&1) r32|=1LL<<us2[i];
7210 }
7211 if(dep1[i]&&!((unneeded_reg_upper[i]>>dep1[i])&1))
7212 {
7213 if((regs[i].was32>>dep1[i])&1) r32|=1LL<<dep1[i];
7214 }
7215 if(dep2[i]&&!((unneeded_reg_upper[i]>>dep2[i])&1))
7216 {
7217 if((regs[i].was32>>dep2[i])&1) r32|=1LL<<dep2[i];
7218 }
7219 //requires_32bit[i]=r32;
7220 pr32[i]=r32;
7221
7222 // Dirty registers which are 32-bit, require 32-bit input
7223 // as they will be written as 32-bit values
7224 for(hr=0;hr<HOST_REGS;hr++)
7225 {
7226 if(regs[i].regmap_entry[hr]>0&&regs[i].regmap_entry[hr]<64) {
7227 if((regs[i].was32>>regs[i].regmap_entry[hr])&(regs[i].wasdirty>>hr)&1) {
7228 if(!((unneeded_reg_upper[i]>>regs[i].regmap_entry[hr])&1))
7229 pr32[i]|=1LL<<regs[i].regmap_entry[hr];
7230 //requires_32bit[i]|=1LL<<regs[i].regmap_entry[hr];
7231 }
7232 }
7233 }
7234 }
7235}
7236
7237// Write back dirty registers as soon as we will no longer modify them,
7238// so that we don't end up with lots of writes at the branches.
7239void clean_registers(int istart,int iend,int wr)
7240{
7241 int i;
7242 int r;
7243 u_int will_dirty_i,will_dirty_next,temp_will_dirty;
7244 u_int wont_dirty_i,wont_dirty_next,temp_wont_dirty;
7245 if(iend==slen-1) {
7246 will_dirty_i=will_dirty_next=0;
7247 wont_dirty_i=wont_dirty_next=0;
7248 }else{
7249 will_dirty_i=will_dirty_next=will_dirty[iend+1];
7250 wont_dirty_i=wont_dirty_next=wont_dirty[iend+1];
7251 }
7252 for (i=iend;i>=istart;i--)
7253 {
7254 if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
7255 {
7256 if(ba[i]<start || ba[i]>=(start+slen*4))
7257 {
7258 // Branch out of this block, flush all regs
7259 if(itype[i]==RJUMP||itype[i]==UJUMP||(source[i]>>16)==0x1000)
7260 {
7261 // Unconditional branch
7262 will_dirty_i=0;
7263 wont_dirty_i=0;
7264 // Merge in delay slot (will dirty)
7265 for(r=0;r<HOST_REGS;r++) {
7266 if(r!=EXCLUDE_REG) {
7267 if((branch_regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7268 if((branch_regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7269 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7270 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7271 if((branch_regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7272 if(branch_regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7273 if(branch_regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7274 if((regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7275 if((regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7276 if((regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7277 if((regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7278 if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7279 if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7280 if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7281 }
7282 }
7283 }
7284 else
7285 {
7286 // Conditional branch
7287 will_dirty_i=0;
7288 wont_dirty_i=wont_dirty_next;
7289 // Merge in delay slot (will dirty)
7290 for(r=0;r<HOST_REGS;r++) {
7291 if(r!=EXCLUDE_REG) {
7292 if(!likely[i]) {
7293 // Might not dirty if likely branch is not taken
7294 if((branch_regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7295 if((branch_regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7296 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7297 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7298 if((branch_regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7299 if(branch_regs[i].regmap[r]==0) will_dirty_i&=~(1<<r);
7300 if(branch_regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7301 //if((regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7302 //if((regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7303 if((regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7304 if((regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7305 if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7306 if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7307 if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7308 }
7309 }
7310 }
7311 }
7312 // Merge in delay slot (wont dirty)
7313 for(r=0;r<HOST_REGS;r++) {
7314 if(r!=EXCLUDE_REG) {
7315 if((regs[i].regmap[r]&63)==rt1[i]) wont_dirty_i|=1<<r;
7316 if((regs[i].regmap[r]&63)==rt2[i]) wont_dirty_i|=1<<r;
7317 if((regs[i].regmap[r]&63)==rt1[i+1]) wont_dirty_i|=1<<r;
7318 if((regs[i].regmap[r]&63)==rt2[i+1]) wont_dirty_i|=1<<r;
7319 if(regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
7320 if((branch_regs[i].regmap[r]&63)==rt1[i]) wont_dirty_i|=1<<r;
7321 if((branch_regs[i].regmap[r]&63)==rt2[i]) wont_dirty_i|=1<<r;
7322 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) wont_dirty_i|=1<<r;
7323 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) wont_dirty_i|=1<<r;
7324 if(branch_regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
7325 }
7326 }
7327 if(wr) {
7328 #ifndef DESTRUCTIVE_WRITEBACK
7329 branch_regs[i].dirty&=wont_dirty_i;
7330 #endif
7331 branch_regs[i].dirty|=will_dirty_i;
7332 }
7333 }
7334 else
7335 {
7336 // Internal branch
7337 if(ba[i]<=start+i*4) {
7338 // Backward branch
7339 if(itype[i]==RJUMP||itype[i]==UJUMP||(source[i]>>16)==0x1000)
7340 {
7341 // Unconditional branch
7342 temp_will_dirty=0;
7343 temp_wont_dirty=0;
7344 // Merge in delay slot (will dirty)
7345 for(r=0;r<HOST_REGS;r++) {
7346 if(r!=EXCLUDE_REG) {
7347 if((branch_regs[i].regmap[r]&63)==rt1[i]) temp_will_dirty|=1<<r;
7348 if((branch_regs[i].regmap[r]&63)==rt2[i]) temp_will_dirty|=1<<r;
7349 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) temp_will_dirty|=1<<r;
7350 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) temp_will_dirty|=1<<r;
7351 if((branch_regs[i].regmap[r]&63)>33) temp_will_dirty&=~(1<<r);
7352 if(branch_regs[i].regmap[r]<=0) temp_will_dirty&=~(1<<r);
7353 if(branch_regs[i].regmap[r]==CCREG) temp_will_dirty|=1<<r;
7354 if((regs[i].regmap[r]&63)==rt1[i]) temp_will_dirty|=1<<r;
7355 if((regs[i].regmap[r]&63)==rt2[i]) temp_will_dirty|=1<<r;
7356 if((regs[i].regmap[r]&63)==rt1[i+1]) temp_will_dirty|=1<<r;
7357 if((regs[i].regmap[r]&63)==rt2[i+1]) temp_will_dirty|=1<<r;
7358 if((regs[i].regmap[r]&63)>33) temp_will_dirty&=~(1<<r);
7359 if(regs[i].regmap[r]<=0) temp_will_dirty&=~(1<<r);
7360 if(regs[i].regmap[r]==CCREG) temp_will_dirty|=1<<r;
7361 }
7362 }
7363 } else {
7364 // Conditional branch (not taken case)
7365 temp_will_dirty=will_dirty_next;
7366 temp_wont_dirty=wont_dirty_next;
7367 // Merge in delay slot (will dirty)
7368 for(r=0;r<HOST_REGS;r++) {
7369 if(r!=EXCLUDE_REG) {
7370 if(!likely[i]) {
7371 // Will not dirty if likely branch is not taken
7372 if((branch_regs[i].regmap[r]&63)==rt1[i]) temp_will_dirty|=1<<r;
7373 if((branch_regs[i].regmap[r]&63)==rt2[i]) temp_will_dirty|=1<<r;
7374 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) temp_will_dirty|=1<<r;
7375 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) temp_will_dirty|=1<<r;
7376 if((branch_regs[i].regmap[r]&63)>33) temp_will_dirty&=~(1<<r);
7377 if(branch_regs[i].regmap[r]==0) temp_will_dirty&=~(1<<r);
7378 if(branch_regs[i].regmap[r]==CCREG) temp_will_dirty|=1<<r;
7379 //if((regs[i].regmap[r]&63)==rt1[i]) temp_will_dirty|=1<<r;
7380 //if((regs[i].regmap[r]&63)==rt2[i]) temp_will_dirty|=1<<r;
7381 if((regs[i].regmap[r]&63)==rt1[i+1]) temp_will_dirty|=1<<r;
7382 if((regs[i].regmap[r]&63)==rt2[i+1]) temp_will_dirty|=1<<r;
7383 if((regs[i].regmap[r]&63)>33) temp_will_dirty&=~(1<<r);
7384 if(regs[i].regmap[r]<=0) temp_will_dirty&=~(1<<r);
7385 if(regs[i].regmap[r]==CCREG) temp_will_dirty|=1<<r;
7386 }
7387 }
7388 }
7389 }
7390 // Merge in delay slot (wont dirty)
7391 for(r=0;r<HOST_REGS;r++) {
7392 if(r!=EXCLUDE_REG) {
7393 if((regs[i].regmap[r]&63)==rt1[i]) temp_wont_dirty|=1<<r;
7394 if((regs[i].regmap[r]&63)==rt2[i]) temp_wont_dirty|=1<<r;
7395 if((regs[i].regmap[r]&63)==rt1[i+1]) temp_wont_dirty|=1<<r;
7396 if((regs[i].regmap[r]&63)==rt2[i+1]) temp_wont_dirty|=1<<r;
7397 if(regs[i].regmap[r]==CCREG) temp_wont_dirty|=1<<r;
7398 if((branch_regs[i].regmap[r]&63)==rt1[i]) temp_wont_dirty|=1<<r;
7399 if((branch_regs[i].regmap[r]&63)==rt2[i]) temp_wont_dirty|=1<<r;
7400 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) temp_wont_dirty|=1<<r;
7401 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) temp_wont_dirty|=1<<r;
7402 if(branch_regs[i].regmap[r]==CCREG) temp_wont_dirty|=1<<r;
7403 }
7404 }
7405 // Deal with changed mappings
7406 if(i<iend) {
7407 for(r=0;r<HOST_REGS;r++) {
7408 if(r!=EXCLUDE_REG) {
7409 if(regs[i].regmap[r]!=regmap_pre[i][r]) {
7410 temp_will_dirty&=~(1<<r);
7411 temp_wont_dirty&=~(1<<r);
7412 if((regmap_pre[i][r]&63)>0 && (regmap_pre[i][r]&63)<34) {
7413 temp_will_dirty|=((unneeded_reg[i]>>(regmap_pre[i][r]&63))&1)<<r;
7414 temp_wont_dirty|=((unneeded_reg[i]>>(regmap_pre[i][r]&63))&1)<<r;
7415 } else {
7416 temp_will_dirty|=1<<r;
7417 temp_wont_dirty|=1<<r;
7418 }
7419 }
7420 }
7421 }
7422 }
7423 if(wr) {
7424 will_dirty[i]=temp_will_dirty;
7425 wont_dirty[i]=temp_wont_dirty;
7426 clean_registers((ba[i]-start)>>2,i-1,0);
7427 }else{
7428 // Limit recursion. It can take an excessive amount
7429 // of time if there are a lot of nested loops.
7430 will_dirty[(ba[i]-start)>>2]=0;
7431 wont_dirty[(ba[i]-start)>>2]=-1;
7432 }
7433 }
7434 /*else*/ if(1)
7435 {
7436 if(itype[i]==RJUMP||itype[i]==UJUMP||(source[i]>>16)==0x1000)
7437 {
7438 // Unconditional branch
7439 will_dirty_i=0;
7440 wont_dirty_i=0;
7441 //if(ba[i]>start+i*4) { // Disable recursion (for debugging)
7442 for(r=0;r<HOST_REGS;r++) {
7443 if(r!=EXCLUDE_REG) {
7444 if(branch_regs[i].regmap[r]==regs[(ba[i]-start)>>2].regmap_entry[r]) {
7445 will_dirty_i|=will_dirty[(ba[i]-start)>>2]&(1<<r);
7446 wont_dirty_i|=wont_dirty[(ba[i]-start)>>2]&(1<<r);
7447 }
e3234ecf 7448 if(branch_regs[i].regmap[r]>=0) {
7449 will_dirty_i|=((unneeded_reg[(ba[i]-start)>>2]>>(branch_regs[i].regmap[r]&63))&1)<<r;
7450 wont_dirty_i|=((unneeded_reg[(ba[i]-start)>>2]>>(branch_regs[i].regmap[r]&63))&1)<<r;
7451 }
57871462 7452 }
7453 }
7454 //}
7455 // Merge in delay slot
7456 for(r=0;r<HOST_REGS;r++) {
7457 if(r!=EXCLUDE_REG) {
7458 if((branch_regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7459 if((branch_regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7460 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7461 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7462 if((branch_regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7463 if(branch_regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7464 if(branch_regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7465 if((regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7466 if((regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7467 if((regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7468 if((regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7469 if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7470 if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7471 if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7472 }
7473 }
7474 } else {
7475 // Conditional branch
7476 will_dirty_i=will_dirty_next;
7477 wont_dirty_i=wont_dirty_next;
7478 //if(ba[i]>start+i*4) { // Disable recursion (for debugging)
7479 for(r=0;r<HOST_REGS;r++) {
7480 if(r!=EXCLUDE_REG) {
e3234ecf 7481 signed char target_reg=branch_regs[i].regmap[r];
7482 if(target_reg==regs[(ba[i]-start)>>2].regmap_entry[r]) {
57871462 7483 will_dirty_i&=will_dirty[(ba[i]-start)>>2]&(1<<r);
7484 wont_dirty_i|=wont_dirty[(ba[i]-start)>>2]&(1<<r);
7485 }
e3234ecf 7486 else if(target_reg>=0) {
7487 will_dirty_i&=((unneeded_reg[(ba[i]-start)>>2]>>(target_reg&63))&1)<<r;
7488 wont_dirty_i|=((unneeded_reg[(ba[i]-start)>>2]>>(target_reg&63))&1)<<r;
57871462 7489 }
7490 // Treat delay slot as part of branch too
7491 /*if(regs[i+1].regmap[r]==regs[(ba[i]-start)>>2].regmap_entry[r]) {
7492 will_dirty[i+1]&=will_dirty[(ba[i]-start)>>2]&(1<<r);
7493 wont_dirty[i+1]|=wont_dirty[(ba[i]-start)>>2]&(1<<r);
7494 }
7495 else
7496 {
7497 will_dirty[i+1]&=~(1<<r);
7498 }*/
7499 }
7500 }
7501 //}
7502 // Merge in delay slot
7503 for(r=0;r<HOST_REGS;r++) {
7504 if(r!=EXCLUDE_REG) {
7505 if(!likely[i]) {
7506 // Might not dirty if likely branch is not taken
7507 if((branch_regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7508 if((branch_regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7509 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7510 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7511 if((branch_regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7512 if(branch_regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7513 if(branch_regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7514 //if((regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7515 //if((regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7516 if((regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7517 if((regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7518 if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7519 if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7520 if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7521 }
7522 }
7523 }
7524 }
e3234ecf 7525 // Merge in delay slot (won't dirty)
57871462 7526 for(r=0;r<HOST_REGS;r++) {
7527 if(r!=EXCLUDE_REG) {
7528 if((regs[i].regmap[r]&63)==rt1[i]) wont_dirty_i|=1<<r;
7529 if((regs[i].regmap[r]&63)==rt2[i]) wont_dirty_i|=1<<r;
7530 if((regs[i].regmap[r]&63)==rt1[i+1]) wont_dirty_i|=1<<r;
7531 if((regs[i].regmap[r]&63)==rt2[i+1]) wont_dirty_i|=1<<r;
7532 if(regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
7533 if((branch_regs[i].regmap[r]&63)==rt1[i]) wont_dirty_i|=1<<r;
7534 if((branch_regs[i].regmap[r]&63)==rt2[i]) wont_dirty_i|=1<<r;
7535 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) wont_dirty_i|=1<<r;
7536 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) wont_dirty_i|=1<<r;
7537 if(branch_regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
7538 }
7539 }
7540 if(wr) {
7541 #ifndef DESTRUCTIVE_WRITEBACK
7542 branch_regs[i].dirty&=wont_dirty_i;
7543 #endif
7544 branch_regs[i].dirty|=will_dirty_i;
7545 }
7546 }
7547 }
7548 }
1e973cb0 7549 else if(itype[i]==SYSCALL||itype[i]==HLECALL||itype[i]==INTCALL)
57871462 7550 {
7551 // SYSCALL instruction (software interrupt)
7552 will_dirty_i=0;
7553 wont_dirty_i=0;
7554 }
7555 else if(itype[i]==COP0 && (source[i]&0x3f)==0x18)
7556 {
7557 // ERET instruction (return from interrupt)
7558 will_dirty_i=0;
7559 wont_dirty_i=0;
7560 }
7561 will_dirty_next=will_dirty_i;
7562 wont_dirty_next=wont_dirty_i;
7563 for(r=0;r<HOST_REGS;r++) {
7564 if(r!=EXCLUDE_REG) {
7565 if((regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7566 if((regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7567 if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7568 if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7569 if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7570 if((regs[i].regmap[r]&63)==rt1[i]) wont_dirty_i|=1<<r;
7571 if((regs[i].regmap[r]&63)==rt2[i]) wont_dirty_i|=1<<r;
7572 if(regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
7573 if(i>istart) {
7574 if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&itype[i]!=CJUMP&&itype[i]!=SJUMP&&itype[i]!=FJUMP)
7575 {
7576 // Don't store a register immediately after writing it,
7577 // may prevent dual-issue.
7578 if((regs[i].regmap[r]&63)==rt1[i-1]) wont_dirty_i|=1<<r;
7579 if((regs[i].regmap[r]&63)==rt2[i-1]) wont_dirty_i|=1<<r;
7580 }
7581 }
7582 }
7583 }
7584 // Save it
7585 will_dirty[i]=will_dirty_i;
7586 wont_dirty[i]=wont_dirty_i;
7587 // Mark registers that won't be dirtied as not dirty
7588 if(wr) {
7589 /*printf("wr (%d,%d) %x will:",istart,iend,start+i*4);
7590 for(r=0;r<HOST_REGS;r++) {
7591 if((will_dirty_i>>r)&1) {
7592 printf(" r%d",r);
7593 }
7594 }
7595 printf("\n");*/
7596
7597 //if(i==istart||(itype[i-1]!=RJUMP&&itype[i-1]!=UJUMP&&itype[i-1]!=CJUMP&&itype[i-1]!=SJUMP&&itype[i-1]!=FJUMP)) {
7598 regs[i].dirty|=will_dirty_i;
7599 #ifndef DESTRUCTIVE_WRITEBACK
7600 regs[i].dirty&=wont_dirty_i;
7601 if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
7602 {
7603 if(i<iend-1&&itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000) {
7604 for(r=0;r<HOST_REGS;r++) {
7605 if(r!=EXCLUDE_REG) {
7606 if(regs[i].regmap[r]==regmap_pre[i+2][r]) {
7607 regs[i+2].wasdirty&=wont_dirty_i|~(1<<r);
7608 }else {/*printf("i: %x (%d) mismatch(+2): %d\n",start+i*4,i,r);/*assert(!((wont_dirty_i>>r)&1));*/}
7609 }
7610 }
7611 }
7612 }
7613 else
7614 {
7615 if(i<iend) {
7616 for(r=0;r<HOST_REGS;r++) {
7617 if(r!=EXCLUDE_REG) {
7618 if(regs[i].regmap[r]==regmap_pre[i+1][r]) {
7619 regs[i+1].wasdirty&=wont_dirty_i|~(1<<r);
7620 }else {/*printf("i: %x (%d) mismatch(+1): %d\n",start+i*4,i,r);/*assert(!((wont_dirty_i>>r)&1));*/}
7621 }
7622 }
7623 }
7624 }
7625 #endif
7626 //}
7627 }
7628 // Deal with changed mappings
7629 temp_will_dirty=will_dirty_i;
7630 temp_wont_dirty=wont_dirty_i;
7631 for(r=0;r<HOST_REGS;r++) {
7632 if(r!=EXCLUDE_REG) {
7633 int nr;
7634 if(regs[i].regmap[r]==regmap_pre[i][r]) {
7635 if(wr) {
7636 #ifndef DESTRUCTIVE_WRITEBACK
7637 regs[i].wasdirty&=wont_dirty_i|~(1<<r);
7638 #endif
7639 regs[i].wasdirty|=will_dirty_i&(1<<r);
7640 }
7641 }
f776eb14 7642 else if(regmap_pre[i][r]>=0&&(nr=get_reg(regs[i].regmap,regmap_pre[i][r]))>=0) {
57871462 7643 // Register moved to a different register
7644 will_dirty_i&=~(1<<r);
7645 wont_dirty_i&=~(1<<r);
7646 will_dirty_i|=((temp_will_dirty>>nr)&1)<<r;
7647 wont_dirty_i|=((temp_wont_dirty>>nr)&1)<<r;
7648 if(wr) {
7649 #ifndef DESTRUCTIVE_WRITEBACK
7650 regs[i].wasdirty&=wont_dirty_i|~(1<<r);
7651 #endif
7652 regs[i].wasdirty|=will_dirty_i&(1<<r);
7653 }
7654 }
7655 else {
7656 will_dirty_i&=~(1<<r);
7657 wont_dirty_i&=~(1<<r);
7658 if((regmap_pre[i][r]&63)>0 && (regmap_pre[i][r]&63)<34) {
7659 will_dirty_i|=((unneeded_reg[i]>>(regmap_pre[i][r]&63))&1)<<r;
7660 wont_dirty_i|=((unneeded_reg[i]>>(regmap_pre[i][r]&63))&1)<<r;
7661 } else {
7662 wont_dirty_i|=1<<r;
7663 /*printf("i: %x (%d) mismatch: %d\n",start+i*4,i,r);/*assert(!((will_dirty>>r)&1));*/
7664 }
7665 }
7666 }
7667 }
7668 }
7669}
7670
7671 /* disassembly */
7672void disassemble_inst(int i)
7673{
7674 if (bt[i]) printf("*"); else printf(" ");
7675 switch(itype[i]) {
7676 case UJUMP:
7677 printf (" %x: %s %8x\n",start+i*4,insn[i],ba[i]);break;
7678 case CJUMP:
7679 printf (" %x: %s r%d,r%d,%8x\n",start+i*4,insn[i],rs1[i],rs2[i],i?start+i*4+4+((signed int)((unsigned int)source[i]<<16)>>14):*ba);break;
7680 case SJUMP:
7681 printf (" %x: %s r%d,%8x\n",start+i*4,insn[i],rs1[i],start+i*4+4+((signed int)((unsigned int)source[i]<<16)>>14));break;
7682 case FJUMP:
7683 printf (" %x: %s %8x\n",start+i*4,insn[i],ba[i]);break;
7684 case RJUMP:
74426039 7685 if (opcode[i]==0x9&&rt1[i]!=31)
5067f341 7686 printf (" %x: %s r%d,r%d\n",start+i*4,insn[i],rt1[i],rs1[i]);
7687 else
7688 printf (" %x: %s r%d\n",start+i*4,insn[i],rs1[i]);
7689 break;
57871462 7690 case SPAN:
7691 printf (" %x: %s (pagespan) r%d,r%d,%8x\n",start+i*4,insn[i],rs1[i],rs2[i],ba[i]);break;
7692 case IMM16:
7693 if(opcode[i]==0xf) //LUI
7694 printf (" %x: %s r%d,%4x0000\n",start+i*4,insn[i],rt1[i],imm[i]&0xffff);
7695 else
7696 printf (" %x: %s r%d,r%d,%d\n",start+i*4,insn[i],rt1[i],rs1[i],imm[i]);
7697 break;
7698 case LOAD:
7699 case LOADLR:
7700 printf (" %x: %s r%d,r%d+%x\n",start+i*4,insn[i],rt1[i],rs1[i],imm[i]);
7701 break;
7702 case STORE:
7703 case STORELR:
7704 printf (" %x: %s r%d,r%d+%x\n",start+i*4,insn[i],rs2[i],rs1[i],imm[i]);
7705 break;
7706 case ALU:
7707 case SHIFT:
7708 printf (" %x: %s r%d,r%d,r%d\n",start+i*4,insn[i],rt1[i],rs1[i],rs2[i]);
7709 break;
7710 case MULTDIV:
7711 printf (" %x: %s r%d,r%d\n",start+i*4,insn[i],rs1[i],rs2[i]);
7712 break;
7713 case SHIFTIMM:
7714 printf (" %x: %s r%d,r%d,%d\n",start+i*4,insn[i],rt1[i],rs1[i],imm[i]);
7715 break;
7716 case MOV:
7717 if((opcode2[i]&0x1d)==0x10)
7718 printf (" %x: %s r%d\n",start+i*4,insn[i],rt1[i]);
7719 else if((opcode2[i]&0x1d)==0x11)
7720 printf (" %x: %s r%d\n",start+i*4,insn[i],rs1[i]);
7721 else
7722 printf (" %x: %s\n",start+i*4,insn[i]);
7723 break;
7724 case COP0:
7725 if(opcode2[i]==0)
7726 printf (" %x: %s r%d,cpr0[%d]\n",start+i*4,insn[i],rt1[i],(source[i]>>11)&0x1f); // MFC0
7727 else if(opcode2[i]==4)
7728 printf (" %x: %s r%d,cpr0[%d]\n",start+i*4,insn[i],rs1[i],(source[i]>>11)&0x1f); // MTC0
7729 else printf (" %x: %s\n",start+i*4,insn[i]);
7730 break;
7731 case COP1:
7732 if(opcode2[i]<3)
7733 printf (" %x: %s r%d,cpr1[%d]\n",start+i*4,insn[i],rt1[i],(source[i]>>11)&0x1f); // MFC1
7734 else if(opcode2[i]>3)
7735 printf (" %x: %s r%d,cpr1[%d]\n",start+i*4,insn[i],rs1[i],(source[i]>>11)&0x1f); // MTC1
7736 else printf (" %x: %s\n",start+i*4,insn[i]);
7737 break;
b9b61529 7738 case COP2:
7739 if(opcode2[i]<3)
7740 printf (" %x: %s r%d,cpr2[%d]\n",start+i*4,insn[i],rt1[i],(source[i]>>11)&0x1f); // MFC2
7741 else if(opcode2[i]>3)
7742 printf (" %x: %s r%d,cpr2[%d]\n",start+i*4,insn[i],rs1[i],(source[i]>>11)&0x1f); // MTC2
7743 else printf (" %x: %s\n",start+i*4,insn[i]);
7744 break;
57871462 7745 case C1LS:
7746 printf (" %x: %s cpr1[%d],r%d+%x\n",start+i*4,insn[i],(source[i]>>16)&0x1f,rs1[i],imm[i]);
7747 break;
b9b61529 7748 case C2LS:
7749 printf (" %x: %s cpr2[%d],r%d+%x\n",start+i*4,insn[i],(source[i]>>16)&0x1f,rs1[i],imm[i]);
7750 break;
1e973cb0 7751 case INTCALL:
7752 printf (" %x: %s (INTCALL)\n",start+i*4,insn[i]);
7753 break;
57871462 7754 default:
7755 //printf (" %s %8x\n",insn[i],source[i]);
7756 printf (" %x: %s\n",start+i*4,insn[i]);
7757 }
7758}
7759
dc990066 7760// clear the state completely, instead of just marking
7761// things invalid like invalidate_all_pages() does
7762void new_dynarec_clear_full()
57871462 7763{
57871462 7764 int n;
35775df7 7765 out=(u_char *)BASE_ADDR;
7766 memset(invalid_code,1,sizeof(invalid_code));
7767 memset(hash_table,0xff,sizeof(hash_table));
57871462 7768 memset(mini_ht,-1,sizeof(mini_ht));
7769 memset(restore_candidate,0,sizeof(restore_candidate));
dc990066 7770 memset(shadow,0,sizeof(shadow));
57871462 7771 copy=shadow;
7772 expirep=16384; // Expiry pointer, +2 blocks
7773 pending_exception=0;
7774 literalcount=0;
57871462 7775 stop_after_jal=0;
7776 // TLB
af4ee1fe 7777#ifndef DISABLE_TLB
57871462 7778 using_tlb=0;
af4ee1fe 7779#endif
dadf55f2 7780 sp_in_mirror=0;
57871462 7781 for(n=0;n<524288;n++) // 0 .. 0x7FFFFFFF
7782 memory_map[n]=-1;
7783 for(n=524288;n<526336;n++) // 0x80000000 .. 0x807FFFFF
7784 memory_map[n]=((u_int)rdram-0x80000000)>>2;
7785 for(n=526336;n<1048576;n++) // 0x80800000 .. 0xFFFFFFFF
7786 memory_map[n]=-1;
dc990066 7787 for(n=0;n<4096;n++) ll_clear(jump_in+n);
7788 for(n=0;n<4096;n++) ll_clear(jump_out+n);
7789 for(n=0;n<4096;n++) ll_clear(jump_dirty+n);
7790}
7791
7792void new_dynarec_init()
7793{
7794 printf("Init new dynarec\n");
7795 out=(u_char *)BASE_ADDR;
7796 if (mmap (out, 1<<TARGET_SIZE_2,
7797 PROT_READ | PROT_WRITE | PROT_EXEC,
7798 MAP_FIXED | MAP_PRIVATE | MAP_ANONYMOUS,
7799 -1, 0) <= 0) {printf("mmap() failed\n");}
7800#ifdef MUPEN64
7801 rdword=&readmem_dword;
7802 fake_pc.f.r.rs=&readmem_dword;
7803 fake_pc.f.r.rt=&readmem_dword;
7804 fake_pc.f.r.rd=&readmem_dword;
7805#endif
7806 int n;
7807 new_dynarec_clear_full();
7808#ifdef HOST_IMM8
7809 // Copy this into local area so we don't have to put it in every literal pool
7810 invc_ptr=invalid_code;
7811#endif
24385cae 7812#ifdef MUPEN64
57871462 7813 for(n=0;n<0x8000;n++) { // 0 .. 0x7FFFFFFF
7814 writemem[n] = write_nomem_new;
7815 writememb[n] = write_nomemb_new;
7816 writememh[n] = write_nomemh_new;
24385cae 7817#ifndef FORCE32
57871462 7818 writememd[n] = write_nomemd_new;
24385cae 7819#endif
57871462 7820 readmem[n] = read_nomem_new;
7821 readmemb[n] = read_nomemb_new;
7822 readmemh[n] = read_nomemh_new;
24385cae 7823#ifndef FORCE32
57871462 7824 readmemd[n] = read_nomemd_new;
24385cae 7825#endif
57871462 7826 }
7827 for(n=0x8000;n<0x8080;n++) { // 0x80000000 .. 0x807FFFFF
7828 writemem[n] = write_rdram_new;
7829 writememb[n] = write_rdramb_new;
7830 writememh[n] = write_rdramh_new;
24385cae 7831#ifndef FORCE32
57871462 7832 writememd[n] = write_rdramd_new;
24385cae 7833#endif
57871462 7834 }
7835 for(n=0xC000;n<0x10000;n++) { // 0xC0000000 .. 0xFFFFFFFF
7836 writemem[n] = write_nomem_new;
7837 writememb[n] = write_nomemb_new;
7838 writememh[n] = write_nomemh_new;
24385cae 7839#ifndef FORCE32
57871462 7840 writememd[n] = write_nomemd_new;
24385cae 7841#endif
57871462 7842 readmem[n] = read_nomem_new;
7843 readmemb[n] = read_nomemb_new;
7844 readmemh[n] = read_nomemh_new;
24385cae 7845#ifndef FORCE32
57871462 7846 readmemd[n] = read_nomemd_new;
24385cae 7847#endif
57871462 7848 }
24385cae 7849#endif
57871462 7850 tlb_hacks();
7851 arch_init();
7852}
7853
7854void new_dynarec_cleanup()
7855{
7856 int n;
7857 if (munmap ((void *)BASE_ADDR, 1<<TARGET_SIZE_2) < 0) {printf("munmap() failed\n");}
7858 for(n=0;n<4096;n++) ll_clear(jump_in+n);
7859 for(n=0;n<4096;n++) ll_clear(jump_out+n);
7860 for(n=0;n<4096;n++) ll_clear(jump_dirty+n);
7861 #ifdef ROM_COPY
7862 if (munmap (ROM_COPY, 67108864) < 0) {printf("munmap() failed\n");}
7863 #endif
7864}
7865
7866int new_recompile_block(int addr)
7867{
7868/*
7869 if(addr==0x800cd050) {
7870 int block;
7871 for(block=0x80000;block<0x80800;block++) invalidate_block(block);
7872 int n;
7873 for(n=0;n<=2048;n++) ll_clear(jump_dirty+n);
7874 }
7875*/
7876 //if(Count==365117028) tracedebug=1;
7877 assem_debug("NOTCOMPILED: addr = %x -> %x\n", (int)addr, (int)out);
7878 //printf("NOTCOMPILED: addr = %x -> %x\n", (int)addr, (int)out);
7879 //printf("TRACE: count=%d next=%d (compile %x)\n",Count,next_interupt,addr);
7880 //if(debug)
7881 //printf("TRACE: count=%d next=%d (checksum %x)\n",Count,next_interupt,mchecksum());
7882 //printf("fpu mapping=%x enabled=%x\n",(Status & 0x04000000)>>26,(Status & 0x20000000)>>29);
7883 /*if(Count>=312978186) {
7884 rlist();
7885 }*/
7886 //rlist();
7887 start = (u_int)addr&~3;
7888 //assert(((u_int)addr&1)==0);
7139f3c8 7889#ifdef PCSX
dadf55f2 7890 if(!sp_in_mirror&&(signed int)(psxRegs.GPR.n.sp&0xffe00000)>0x80200000&&
7891 0x10000<=psxRegs.GPR.n.sp&&(psxRegs.GPR.n.sp&~0xe0e00000)<RAM_SIZE) {
c2e3bd42 7892 printf("SP hack enabled (%08x), @%08x\n", psxRegs.GPR.n.sp, psxRegs.pc);
dadf55f2 7893 sp_in_mirror=1;
7894 }
9ad4d757 7895 if (Config.HLE && start == 0x80001000) // hlecall
560e4a12 7896 {
7139f3c8 7897 // XXX: is this enough? Maybe check hleSoftCall?
bb5285ef 7898 u_int beginning=(u_int)out;
7139f3c8 7899 u_int page=get_page(start);
7139f3c8 7900 invalid_code[start>>12]=0;
7901 emit_movimm(start,0);
7902 emit_writeword(0,(int)&pcaddr);
bb5285ef 7903 emit_jmp((int)new_dyna_leave);
7904#ifdef __arm__
7905 __clear_cache((void *)beginning,out);
7906#endif
9ad4d757 7907 ll_add(jump_in+page,start,(void *)beginning);
7139f3c8 7908 return 0;
7909 }
560e4a12 7910 else if ((u_int)addr < 0x00200000 ||
7911 (0xa0000000 <= addr && addr < 0xa0200000)) {
7139f3c8 7912 // used for BIOS calls mostly?
560e4a12 7913 source = (u_int *)((u_int)rdram+(start&0x1fffff));
7914 pagelimit = (addr&0xa0000000)|0x00200000;
7915 }
7916 else if (!Config.HLE && (
7917/* (0x9fc00000 <= addr && addr < 0x9fc80000) ||*/
7918 (0xbfc00000 <= addr && addr < 0xbfc80000))) {
7919 // BIOS
7920 source = (u_int *)((u_int)psxR+(start&0x7ffff));
7921 pagelimit = (addr&0xfff00000)|0x80000;
7139f3c8 7922 }
7923 else
7924#endif
3d624f89 7925#ifdef MUPEN64
57871462 7926 if ((int)addr >= 0xa4000000 && (int)addr < 0xa4001000) {
7927 source = (u_int *)((u_int)SP_DMEM+start-0xa4000000);
7928 pagelimit = 0xa4001000;
7929 }
3d624f89 7930 else
7931#endif
4cb76aa4 7932 if ((int)addr >= 0x80000000 && (int)addr < 0x80000000+RAM_SIZE) {
57871462 7933 source = (u_int *)((u_int)rdram+start-0x80000000);
4cb76aa4 7934 pagelimit = 0x80000000+RAM_SIZE;
57871462 7935 }
90ae6d4e 7936#ifndef DISABLE_TLB
57871462 7937 else if ((signed int)addr >= (signed int)0xC0000000) {
7938 //printf("addr=%x mm=%x\n",(u_int)addr,(memory_map[start>>12]<<2));
7939 //if(tlb_LUT_r[start>>12])
7940 //source = (u_int *)(((int)rdram)+(tlb_LUT_r[start>>12]&0xFFFFF000)+(((int)addr)&0xFFF)-0x80000000);
7941 if((signed int)memory_map[start>>12]>=0) {
7942 source = (u_int *)((u_int)(start+(memory_map[start>>12]<<2)));
7943 pagelimit=(start+4096)&0xFFFFF000;
7944 int map=memory_map[start>>12];
7945 int i;
7946 for(i=0;i<5;i++) {
7947 //printf("start: %x next: %x\n",map,memory_map[pagelimit>>12]);
7948 if((map&0xBFFFFFFF)==(memory_map[pagelimit>>12]&0xBFFFFFFF)) pagelimit+=4096;
7949 }
7950 assem_debug("pagelimit=%x\n",pagelimit);
7951 assem_debug("mapping=%x (%x)\n",memory_map[start>>12],(memory_map[start>>12]<<2)+start);
7952 }
7953 else {
7954 assem_debug("Compile at unmapped memory address: %x \n", (int)addr);
7955 //assem_debug("start: %x next: %x\n",memory_map[start>>12],memory_map[(start+4096)>>12]);
560e4a12 7956 return -1; // Caller will invoke exception handler
57871462 7957 }
7958 //printf("source= %x\n",(int)source);
7959 }
90ae6d4e 7960#endif
57871462 7961 else {
7962 printf("Compile at bogus memory address: %x \n", (int)addr);
7963 exit(1);
7964 }
7965
7966 /* Pass 1: disassemble */
7967 /* Pass 2: register dependencies, branch targets */
7968 /* Pass 3: register allocation */
7969 /* Pass 4: branch dependencies */
7970 /* Pass 5: pre-alloc */
7971 /* Pass 6: optimize clean/dirty state */
7972 /* Pass 7: flag 32-bit registers */
7973 /* Pass 8: assembly */
7974 /* Pass 9: linker */
7975 /* Pass 10: garbage collection / free memory */
7976
7977 int i,j;
7978 int done=0;
7979 unsigned int type,op,op2;
7980
7981 //printf("addr = %x source = %x %x\n", addr,source,source[0]);
7982
7983 /* Pass 1 disassembly */
7984
7985 for(i=0;!done;i++) {
e1190b87 7986 bt[i]=0;likely[i]=0;ooo[i]=0;op2=0;
7987 minimum_free_regs[i]=0;
57871462 7988 opcode[i]=op=source[i]>>26;
7989 switch(op)
7990 {
7991 case 0x00: strcpy(insn[i],"special"); type=NI;
7992 op2=source[i]&0x3f;
7993 switch(op2)
7994 {
7995 case 0x00: strcpy(insn[i],"SLL"); type=SHIFTIMM; break;
7996 case 0x02: strcpy(insn[i],"SRL"); type=SHIFTIMM; break;
7997 case 0x03: strcpy(insn[i],"SRA"); type=SHIFTIMM; break;
7998 case 0x04: strcpy(insn[i],"SLLV"); type=SHIFT; break;
7999 case 0x06: strcpy(insn[i],"SRLV"); type=SHIFT; break;
8000 case 0x07: strcpy(insn[i],"SRAV"); type=SHIFT; break;
8001 case 0x08: strcpy(insn[i],"JR"); type=RJUMP; break;
8002 case 0x09: strcpy(insn[i],"JALR"); type=RJUMP; break;
8003 case 0x0C: strcpy(insn[i],"SYSCALL"); type=SYSCALL; break;
8004 case 0x0D: strcpy(insn[i],"BREAK"); type=OTHER; break;
8005 case 0x0F: strcpy(insn[i],"SYNC"); type=OTHER; break;
8006 case 0x10: strcpy(insn[i],"MFHI"); type=MOV; break;
8007 case 0x11: strcpy(insn[i],"MTHI"); type=MOV; break;
8008 case 0x12: strcpy(insn[i],"MFLO"); type=MOV; break;
8009 case 0x13: strcpy(insn[i],"MTLO"); type=MOV; break;
57871462 8010 case 0x18: strcpy(insn[i],"MULT"); type=MULTDIV; break;
8011 case 0x19: strcpy(insn[i],"MULTU"); type=MULTDIV; break;
8012 case 0x1A: strcpy(insn[i],"DIV"); type=MULTDIV; break;
8013 case 0x1B: strcpy(insn[i],"DIVU"); type=MULTDIV; break;
57871462 8014 case 0x20: strcpy(insn[i],"ADD"); type=ALU; break;
8015 case 0x21: strcpy(insn[i],"ADDU"); type=ALU; break;
8016 case 0x22: strcpy(insn[i],"SUB"); type=ALU; break;
8017 case 0x23: strcpy(insn[i],"SUBU"); type=ALU; break;
8018 case 0x24: strcpy(insn[i],"AND"); type=ALU; break;
8019 case 0x25: strcpy(insn[i],"OR"); type=ALU; break;
8020 case 0x26: strcpy(insn[i],"XOR"); type=ALU; break;
8021 case 0x27: strcpy(insn[i],"NOR"); type=ALU; break;
8022 case 0x2A: strcpy(insn[i],"SLT"); type=ALU; break;
8023 case 0x2B: strcpy(insn[i],"SLTU"); type=ALU; break;
57871462 8024 case 0x30: strcpy(insn[i],"TGE"); type=NI; break;
8025 case 0x31: strcpy(insn[i],"TGEU"); type=NI; break;
8026 case 0x32: strcpy(insn[i],"TLT"); type=NI; break;
8027 case 0x33: strcpy(insn[i],"TLTU"); type=NI; break;
8028 case 0x34: strcpy(insn[i],"TEQ"); type=NI; break;
8029 case 0x36: strcpy(insn[i],"TNE"); type=NI; break;
7f2607ea 8030#ifndef FORCE32
8031 case 0x14: strcpy(insn[i],"DSLLV"); type=SHIFT; break;
8032 case 0x16: strcpy(insn[i],"DSRLV"); type=SHIFT; break;
8033 case 0x17: strcpy(insn[i],"DSRAV"); type=SHIFT; break;
8034 case 0x1C: strcpy(insn[i],"DMULT"); type=MULTDIV; break;
8035 case 0x1D: strcpy(insn[i],"DMULTU"); type=MULTDIV; break;
8036 case 0x1E: strcpy(insn[i],"DDIV"); type=MULTDIV; break;
8037 case 0x1F: strcpy(insn[i],"DDIVU"); type=MULTDIV; break;
8038 case 0x2C: strcpy(insn[i],"DADD"); type=ALU; break;
8039 case 0x2D: strcpy(insn[i],"DADDU"); type=ALU; break;
8040 case 0x2E: strcpy(insn[i],"DSUB"); type=ALU; break;
8041 case 0x2F: strcpy(insn[i],"DSUBU"); type=ALU; break;
57871462 8042 case 0x38: strcpy(insn[i],"DSLL"); type=SHIFTIMM; break;
8043 case 0x3A: strcpy(insn[i],"DSRL"); type=SHIFTIMM; break;
8044 case 0x3B: strcpy(insn[i],"DSRA"); type=SHIFTIMM; break;
8045 case 0x3C: strcpy(insn[i],"DSLL32"); type=SHIFTIMM; break;
8046 case 0x3E: strcpy(insn[i],"DSRL32"); type=SHIFTIMM; break;
8047 case 0x3F: strcpy(insn[i],"DSRA32"); type=SHIFTIMM; break;
7f2607ea 8048#endif
57871462 8049 }
8050 break;
8051 case 0x01: strcpy(insn[i],"regimm"); type=NI;
8052 op2=(source[i]>>16)&0x1f;
8053 switch(op2)
8054 {
8055 case 0x00: strcpy(insn[i],"BLTZ"); type=SJUMP; break;
8056 case 0x01: strcpy(insn[i],"BGEZ"); type=SJUMP; break;
8057 case 0x02: strcpy(insn[i],"BLTZL"); type=SJUMP; break;
8058 case 0x03: strcpy(insn[i],"BGEZL"); type=SJUMP; break;
8059 case 0x08: strcpy(insn[i],"TGEI"); type=NI; break;
8060 case 0x09: strcpy(insn[i],"TGEIU"); type=NI; break;
8061 case 0x0A: strcpy(insn[i],"TLTI"); type=NI; break;
8062 case 0x0B: strcpy(insn[i],"TLTIU"); type=NI; break;
8063 case 0x0C: strcpy(insn[i],"TEQI"); type=NI; break;
8064 case 0x0E: strcpy(insn[i],"TNEI"); type=NI; break;
8065 case 0x10: strcpy(insn[i],"BLTZAL"); type=SJUMP; break;
8066 case 0x11: strcpy(insn[i],"BGEZAL"); type=SJUMP; break;
8067 case 0x12: strcpy(insn[i],"BLTZALL"); type=SJUMP; break;
8068 case 0x13: strcpy(insn[i],"BGEZALL"); type=SJUMP; break;
8069 }
8070 break;
8071 case 0x02: strcpy(insn[i],"J"); type=UJUMP; break;
8072 case 0x03: strcpy(insn[i],"JAL"); type=UJUMP; break;
8073 case 0x04: strcpy(insn[i],"BEQ"); type=CJUMP; break;
8074 case 0x05: strcpy(insn[i],"BNE"); type=CJUMP; break;
8075 case 0x06: strcpy(insn[i],"BLEZ"); type=CJUMP; break;
8076 case 0x07: strcpy(insn[i],"BGTZ"); type=CJUMP; break;
8077 case 0x08: strcpy(insn[i],"ADDI"); type=IMM16; break;
8078 case 0x09: strcpy(insn[i],"ADDIU"); type=IMM16; break;
8079 case 0x0A: strcpy(insn[i],"SLTI"); type=IMM16; break;
8080 case 0x0B: strcpy(insn[i],"SLTIU"); type=IMM16; break;
8081 case 0x0C: strcpy(insn[i],"ANDI"); type=IMM16; break;
8082 case 0x0D: strcpy(insn[i],"ORI"); type=IMM16; break;
8083 case 0x0E: strcpy(insn[i],"XORI"); type=IMM16; break;
8084 case 0x0F: strcpy(insn[i],"LUI"); type=IMM16; break;
8085 case 0x10: strcpy(insn[i],"cop0"); type=NI;
8086 op2=(source[i]>>21)&0x1f;
8087 switch(op2)
8088 {
8089 case 0x00: strcpy(insn[i],"MFC0"); type=COP0; break;
8090 case 0x04: strcpy(insn[i],"MTC0"); type=COP0; break;
8091 case 0x10: strcpy(insn[i],"tlb"); type=NI;
8092 switch(source[i]&0x3f)
8093 {
8094 case 0x01: strcpy(insn[i],"TLBR"); type=COP0; break;
8095 case 0x02: strcpy(insn[i],"TLBWI"); type=COP0; break;
8096 case 0x06: strcpy(insn[i],"TLBWR"); type=COP0; break;
8097 case 0x08: strcpy(insn[i],"TLBP"); type=COP0; break;
576bbd8f 8098#ifdef PCSX
8099 case 0x10: strcpy(insn[i],"RFE"); type=COP0; break;
8100#else
57871462 8101 case 0x18: strcpy(insn[i],"ERET"); type=COP0; break;
576bbd8f 8102#endif
57871462 8103 }
8104 }
8105 break;
8106 case 0x11: strcpy(insn[i],"cop1"); type=NI;
8107 op2=(source[i]>>21)&0x1f;
8108 switch(op2)
8109 {
8110 case 0x00: strcpy(insn[i],"MFC1"); type=COP1; break;
8111 case 0x01: strcpy(insn[i],"DMFC1"); type=COP1; break;
8112 case 0x02: strcpy(insn[i],"CFC1"); type=COP1; break;
8113 case 0x04: strcpy(insn[i],"MTC1"); type=COP1; break;
8114 case 0x05: strcpy(insn[i],"DMTC1"); type=COP1; break;
8115 case 0x06: strcpy(insn[i],"CTC1"); type=COP1; break;
8116 case 0x08: strcpy(insn[i],"BC1"); type=FJUMP;
8117 switch((source[i]>>16)&0x3)
8118 {
8119 case 0x00: strcpy(insn[i],"BC1F"); break;
8120 case 0x01: strcpy(insn[i],"BC1T"); break;
8121 case 0x02: strcpy(insn[i],"BC1FL"); break;
8122 case 0x03: strcpy(insn[i],"BC1TL"); break;
8123 }
8124 break;
8125 case 0x10: strcpy(insn[i],"C1.S"); type=NI;
8126 switch(source[i]&0x3f)
8127 {
8128 case 0x00: strcpy(insn[i],"ADD.S"); type=FLOAT; break;
8129 case 0x01: strcpy(insn[i],"SUB.S"); type=FLOAT; break;
8130 case 0x02: strcpy(insn[i],"MUL.S"); type=FLOAT; break;
8131 case 0x03: strcpy(insn[i],"DIV.S"); type=FLOAT; break;
8132 case 0x04: strcpy(insn[i],"SQRT.S"); type=FLOAT; break;
8133 case 0x05: strcpy(insn[i],"ABS.S"); type=FLOAT; break;
8134 case 0x06: strcpy(insn[i],"MOV.S"); type=FLOAT; break;
8135 case 0x07: strcpy(insn[i],"NEG.S"); type=FLOAT; break;
8136 case 0x08: strcpy(insn[i],"ROUND.L.S"); type=FCONV; break;
8137 case 0x09: strcpy(insn[i],"TRUNC.L.S"); type=FCONV; break;
8138 case 0x0A: strcpy(insn[i],"CEIL.L.S"); type=FCONV; break;
8139 case 0x0B: strcpy(insn[i],"FLOOR.L.S"); type=FCONV; break;
8140 case 0x0C: strcpy(insn[i],"ROUND.W.S"); type=FCONV; break;
8141 case 0x0D: strcpy(insn[i],"TRUNC.W.S"); type=FCONV; break;
8142 case 0x0E: strcpy(insn[i],"CEIL.W.S"); type=FCONV; break;
8143 case 0x0F: strcpy(insn[i],"FLOOR.W.S"); type=FCONV; break;
8144 case 0x21: strcpy(insn[i],"CVT.D.S"); type=FCONV; break;
8145 case 0x24: strcpy(insn[i],"CVT.W.S"); type=FCONV; break;
8146 case 0x25: strcpy(insn[i],"CVT.L.S"); type=FCONV; break;
8147 case 0x30: strcpy(insn[i],"C.F.S"); type=FCOMP; break;
8148 case 0x31: strcpy(insn[i],"C.UN.S"); type=FCOMP; break;
8149 case 0x32: strcpy(insn[i],"C.EQ.S"); type=FCOMP; break;
8150 case 0x33: strcpy(insn[i],"C.UEQ.S"); type=FCOMP; break;
8151 case 0x34: strcpy(insn[i],"C.OLT.S"); type=FCOMP; break;
8152 case 0x35: strcpy(insn[i],"C.ULT.S"); type=FCOMP; break;
8153 case 0x36: strcpy(insn[i],"C.OLE.S"); type=FCOMP; break;
8154 case 0x37: strcpy(insn[i],"C.ULE.S"); type=FCOMP; break;
8155 case 0x38: strcpy(insn[i],"C.SF.S"); type=FCOMP; break;
8156 case 0x39: strcpy(insn[i],"C.NGLE.S"); type=FCOMP; break;
8157 case 0x3A: strcpy(insn[i],"C.SEQ.S"); type=FCOMP; break;
8158 case 0x3B: strcpy(insn[i],"C.NGL.S"); type=FCOMP; break;
8159 case 0x3C: strcpy(insn[i],"C.LT.S"); type=FCOMP; break;
8160 case 0x3D: strcpy(insn[i],"C.NGE.S"); type=FCOMP; break;
8161 case 0x3E: strcpy(insn[i],"C.LE.S"); type=FCOMP; break;
8162 case 0x3F: strcpy(insn[i],"C.NGT.S"); type=FCOMP; break;
8163 }
8164 break;
8165 case 0x11: strcpy(insn[i],"C1.D"); type=NI;
8166 switch(source[i]&0x3f)
8167 {
8168 case 0x00: strcpy(insn[i],"ADD.D"); type=FLOAT; break;
8169 case 0x01: strcpy(insn[i],"SUB.D"); type=FLOAT; break;
8170 case 0x02: strcpy(insn[i],"MUL.D"); type=FLOAT; break;
8171 case 0x03: strcpy(insn[i],"DIV.D"); type=FLOAT; break;
8172 case 0x04: strcpy(insn[i],"SQRT.D"); type=FLOAT; break;
8173 case 0x05: strcpy(insn[i],"ABS.D"); type=FLOAT; break;
8174 case 0x06: strcpy(insn[i],"MOV.D"); type=FLOAT; break;
8175 case 0x07: strcpy(insn[i],"NEG.D"); type=FLOAT; break;
8176 case 0x08: strcpy(insn[i],"ROUND.L.D"); type=FCONV; break;
8177 case 0x09: strcpy(insn[i],"TRUNC.L.D"); type=FCONV; break;
8178 case 0x0A: strcpy(insn[i],"CEIL.L.D"); type=FCONV; break;
8179 case 0x0B: strcpy(insn[i],"FLOOR.L.D"); type=FCONV; break;
8180 case 0x0C: strcpy(insn[i],"ROUND.W.D"); type=FCONV; break;
8181 case 0x0D: strcpy(insn[i],"TRUNC.W.D"); type=FCONV; break;
8182 case 0x0E: strcpy(insn[i],"CEIL.W.D"); type=FCONV; break;
8183 case 0x0F: strcpy(insn[i],"FLOOR.W.D"); type=FCONV; break;
8184 case 0x20: strcpy(insn[i],"CVT.S.D"); type=FCONV; break;
8185 case 0x24: strcpy(insn[i],"CVT.W.D"); type=FCONV; break;
8186 case 0x25: strcpy(insn[i],"CVT.L.D"); type=FCONV; break;
8187 case 0x30: strcpy(insn[i],"C.F.D"); type=FCOMP; break;
8188 case 0x31: strcpy(insn[i],"C.UN.D"); type=FCOMP; break;
8189 case 0x32: strcpy(insn[i],"C.EQ.D"); type=FCOMP; break;
8190 case 0x33: strcpy(insn[i],"C.UEQ.D"); type=FCOMP; break;
8191 case 0x34: strcpy(insn[i],"C.OLT.D"); type=FCOMP; break;
8192 case 0x35: strcpy(insn[i],"C.ULT.D"); type=FCOMP; break;
8193 case 0x36: strcpy(insn[i],"C.OLE.D"); type=FCOMP; break;
8194 case 0x37: strcpy(insn[i],"C.ULE.D"); type=FCOMP; break;
8195 case 0x38: strcpy(insn[i],"C.SF.D"); type=FCOMP; break;
8196 case 0x39: strcpy(insn[i],"C.NGLE.D"); type=FCOMP; break;
8197 case 0x3A: strcpy(insn[i],"C.SEQ.D"); type=FCOMP; break;
8198 case 0x3B: strcpy(insn[i],"C.NGL.D"); type=FCOMP; break;
8199 case 0x3C: strcpy(insn[i],"C.LT.D"); type=FCOMP; break;
8200 case 0x3D: strcpy(insn[i],"C.NGE.D"); type=FCOMP; break;
8201 case 0x3E: strcpy(insn[i],"C.LE.D"); type=FCOMP; break;
8202 case 0x3F: strcpy(insn[i],"C.NGT.D"); type=FCOMP; break;
8203 }
8204 break;
8205 case 0x14: strcpy(insn[i],"C1.W"); type=NI;
8206 switch(source[i]&0x3f)
8207 {
8208 case 0x20: strcpy(insn[i],"CVT.S.W"); type=FCONV; break;
8209 case 0x21: strcpy(insn[i],"CVT.D.W"); type=FCONV; break;
8210 }
8211 break;
8212 case 0x15: strcpy(insn[i],"C1.L"); type=NI;
8213 switch(source[i]&0x3f)
8214 {
8215 case 0x20: strcpy(insn[i],"CVT.S.L"); type=FCONV; break;
8216 case 0x21: strcpy(insn[i],"CVT.D.L"); type=FCONV; break;
8217 }
8218 break;
8219 }
8220 break;
909168d6 8221#ifndef FORCE32
57871462 8222 case 0x14: strcpy(insn[i],"BEQL"); type=CJUMP; break;
8223 case 0x15: strcpy(insn[i],"BNEL"); type=CJUMP; break;
8224 case 0x16: strcpy(insn[i],"BLEZL"); type=CJUMP; break;
8225 case 0x17: strcpy(insn[i],"BGTZL"); type=CJUMP; break;
8226 case 0x18: strcpy(insn[i],"DADDI"); type=IMM16; break;
8227 case 0x19: strcpy(insn[i],"DADDIU"); type=IMM16; break;
8228 case 0x1A: strcpy(insn[i],"LDL"); type=LOADLR; break;
8229 case 0x1B: strcpy(insn[i],"LDR"); type=LOADLR; break;
996cc15d 8230#endif
57871462 8231 case 0x20: strcpy(insn[i],"LB"); type=LOAD; break;
8232 case 0x21: strcpy(insn[i],"LH"); type=LOAD; break;
8233 case 0x22: strcpy(insn[i],"LWL"); type=LOADLR; break;
8234 case 0x23: strcpy(insn[i],"LW"); type=LOAD; break;
8235 case 0x24: strcpy(insn[i],"LBU"); type=LOAD; break;
8236 case 0x25: strcpy(insn[i],"LHU"); type=LOAD; break;
8237 case 0x26: strcpy(insn[i],"LWR"); type=LOADLR; break;
64bd6f82 8238#ifndef FORCE32
57871462 8239 case 0x27: strcpy(insn[i],"LWU"); type=LOAD; break;
64bd6f82 8240#endif
57871462 8241 case 0x28: strcpy(insn[i],"SB"); type=STORE; break;
8242 case 0x29: strcpy(insn[i],"SH"); type=STORE; break;
8243 case 0x2A: strcpy(insn[i],"SWL"); type=STORELR; break;
8244 case 0x2B: strcpy(insn[i],"SW"); type=STORE; break;
996cc15d 8245#ifndef FORCE32
57871462 8246 case 0x2C: strcpy(insn[i],"SDL"); type=STORELR; break;
8247 case 0x2D: strcpy(insn[i],"SDR"); type=STORELR; break;
996cc15d 8248#endif
57871462 8249 case 0x2E: strcpy(insn[i],"SWR"); type=STORELR; break;
8250 case 0x2F: strcpy(insn[i],"CACHE"); type=NOP; break;
8251 case 0x30: strcpy(insn[i],"LL"); type=NI; break;
8252 case 0x31: strcpy(insn[i],"LWC1"); type=C1LS; break;
996cc15d 8253#ifndef FORCE32
57871462 8254 case 0x34: strcpy(insn[i],"LLD"); type=NI; break;
8255 case 0x35: strcpy(insn[i],"LDC1"); type=C1LS; break;
8256 case 0x37: strcpy(insn[i],"LD"); type=LOAD; break;
996cc15d 8257#endif
57871462 8258 case 0x38: strcpy(insn[i],"SC"); type=NI; break;
8259 case 0x39: strcpy(insn[i],"SWC1"); type=C1LS; break;
996cc15d 8260#ifndef FORCE32
57871462 8261 case 0x3C: strcpy(insn[i],"SCD"); type=NI; break;
8262 case 0x3D: strcpy(insn[i],"SDC1"); type=C1LS; break;
8263 case 0x3F: strcpy(insn[i],"SD"); type=STORE; break;
996cc15d 8264#endif
b9b61529 8265#ifdef PCSX
8266 case 0x12: strcpy(insn[i],"COP2"); type=NI;
c7abc864 8267 // note: COP MIPS-1 encoding differs from MIPS32
b9b61529 8268 op2=(source[i]>>21)&0x1f;
c7abc864 8269 if (source[i]&0x3f) {
8270 if (gte_handlers[source[i]&0x3f]!=NULL) {
8271 snprintf(insn[i], sizeof(insn[i]), "COP2 %x", source[i]&0x3f);
8272 type=C2OP;
8273 }
8274 }
8275 else switch(op2)
b9b61529 8276 {
8277 case 0x00: strcpy(insn[i],"MFC2"); type=COP2; break;
8278 case 0x02: strcpy(insn[i],"CFC2"); type=COP2; break;
8279 case 0x04: strcpy(insn[i],"MTC2"); type=COP2; break;
8280 case 0x06: strcpy(insn[i],"CTC2"); type=COP2; break;
b9b61529 8281 }
8282 break;
8283 case 0x32: strcpy(insn[i],"LWC2"); type=C2LS; break;
8284 case 0x3A: strcpy(insn[i],"SWC2"); type=C2LS; break;
8285 case 0x3B: strcpy(insn[i],"HLECALL"); type=HLECALL; break;
8286#endif
90ae6d4e 8287 default: strcpy(insn[i],"???"); type=NI;
75dec299 8288 printf("NI %08x @%08x (%08x)\n", source[i], addr + i*4, addr);
90ae6d4e 8289 break;
57871462 8290 }
8291 itype[i]=type;
8292 opcode2[i]=op2;
8293 /* Get registers/immediates */
8294 lt1[i]=0;
8295 us1[i]=0;
8296 us2[i]=0;
8297 dep1[i]=0;
8298 dep2[i]=0;
8299 switch(type) {
8300 case LOAD:
8301 rs1[i]=(source[i]>>21)&0x1f;
8302 rs2[i]=0;
8303 rt1[i]=(source[i]>>16)&0x1f;
8304 rt2[i]=0;
8305 imm[i]=(short)source[i];
8306 break;
8307 case STORE:
8308 case STORELR:
8309 rs1[i]=(source[i]>>21)&0x1f;
8310 rs2[i]=(source[i]>>16)&0x1f;
8311 rt1[i]=0;
8312 rt2[i]=0;
8313 imm[i]=(short)source[i];
8314 if(op==0x2c||op==0x2d||op==0x3f) us1[i]=rs2[i]; // 64-bit SDL/SDR/SD
8315 break;
8316 case LOADLR:
8317 // LWL/LWR only load part of the register,
8318 // therefore the target register must be treated as a source too
8319 rs1[i]=(source[i]>>21)&0x1f;
8320 rs2[i]=(source[i]>>16)&0x1f;
8321 rt1[i]=(source[i]>>16)&0x1f;
8322 rt2[i]=0;
8323 imm[i]=(short)source[i];
8324 if(op==0x1a||op==0x1b) us1[i]=rs2[i]; // LDR/LDL
8325 if(op==0x26) dep1[i]=rt1[i]; // LWR
8326 break;
8327 case IMM16:
8328 if (op==0x0f) rs1[i]=0; // LUI instruction has no source register
8329 else rs1[i]=(source[i]>>21)&0x1f;
8330 rs2[i]=0;
8331 rt1[i]=(source[i]>>16)&0x1f;
8332 rt2[i]=0;
8333 if(op>=0x0c&&op<=0x0e) { // ANDI/ORI/XORI
8334 imm[i]=(unsigned short)source[i];
8335 }else{
8336 imm[i]=(short)source[i];
8337 }
8338 if(op==0x18||op==0x19) us1[i]=rs1[i]; // DADDI/DADDIU
8339 if(op==0x0a||op==0x0b) us1[i]=rs1[i]; // SLTI/SLTIU
8340 if(op==0x0d||op==0x0e) dep1[i]=rs1[i]; // ORI/XORI
8341 break;
8342 case UJUMP:
8343 rs1[i]=0;
8344 rs2[i]=0;
8345 rt1[i]=0;
8346 rt2[i]=0;
8347 // The JAL instruction writes to r31.
8348 if (op&1) {
8349 rt1[i]=31;
8350 }
8351 rs2[i]=CCREG;
8352 break;
8353 case RJUMP:
8354 rs1[i]=(source[i]>>21)&0x1f;
8355 rs2[i]=0;
8356 rt1[i]=0;
8357 rt2[i]=0;
5067f341 8358 // The JALR instruction writes to rd.
57871462 8359 if (op2&1) {
5067f341 8360 rt1[i]=(source[i]>>11)&0x1f;
57871462 8361 }
8362 rs2[i]=CCREG;
8363 break;
8364 case CJUMP:
8365 rs1[i]=(source[i]>>21)&0x1f;
8366 rs2[i]=(source[i]>>16)&0x1f;
8367 rt1[i]=0;
8368 rt2[i]=0;
8369 if(op&2) { // BGTZ/BLEZ
8370 rs2[i]=0;
8371 }
8372 us1[i]=rs1[i];
8373 us2[i]=rs2[i];
8374 likely[i]=op>>4;
8375 break;
8376 case SJUMP:
8377 rs1[i]=(source[i]>>21)&0x1f;
8378 rs2[i]=CCREG;
8379 rt1[i]=0;
8380 rt2[i]=0;
8381 us1[i]=rs1[i];
8382 if(op2&0x10) { // BxxAL
8383 rt1[i]=31;
8384 // NOTE: If the branch is not taken, r31 is still overwritten
8385 }
8386 likely[i]=(op2&2)>>1;
8387 break;
8388 case FJUMP:
8389 rs1[i]=FSREG;
8390 rs2[i]=CSREG;
8391 rt1[i]=0;
8392 rt2[i]=0;
8393 likely[i]=((source[i])>>17)&1;
8394 break;
8395 case ALU:
8396 rs1[i]=(source[i]>>21)&0x1f; // source
8397 rs2[i]=(source[i]>>16)&0x1f; // subtract amount
8398 rt1[i]=(source[i]>>11)&0x1f; // destination
8399 rt2[i]=0;
8400 if(op2==0x2a||op2==0x2b) { // SLT/SLTU
8401 us1[i]=rs1[i];us2[i]=rs2[i];
8402 }
8403 else if(op2>=0x24&&op2<=0x27) { // AND/OR/XOR/NOR
8404 dep1[i]=rs1[i];dep2[i]=rs2[i];
8405 }
8406 else if(op2>=0x2c&&op2<=0x2f) { // DADD/DSUB
8407 dep1[i]=rs1[i];dep2[i]=rs2[i];
8408 }
8409 break;
8410 case MULTDIV:
8411 rs1[i]=(source[i]>>21)&0x1f; // source
8412 rs2[i]=(source[i]>>16)&0x1f; // divisor
8413 rt1[i]=HIREG;
8414 rt2[i]=LOREG;
8415 if (op2>=0x1c&&op2<=0x1f) { // DMULT/DMULTU/DDIV/DDIVU
8416 us1[i]=rs1[i];us2[i]=rs2[i];
8417 }
8418 break;
8419 case MOV:
8420 rs1[i]=0;
8421 rs2[i]=0;
8422 rt1[i]=0;
8423 rt2[i]=0;
8424 if(op2==0x10) rs1[i]=HIREG; // MFHI
8425 if(op2==0x11) rt1[i]=HIREG; // MTHI
8426 if(op2==0x12) rs1[i]=LOREG; // MFLO
8427 if(op2==0x13) rt1[i]=LOREG; // MTLO
8428 if((op2&0x1d)==0x10) rt1[i]=(source[i]>>11)&0x1f; // MFxx
8429 if((op2&0x1d)==0x11) rs1[i]=(source[i]>>21)&0x1f; // MTxx
8430 dep1[i]=rs1[i];
8431 break;
8432 case SHIFT:
8433 rs1[i]=(source[i]>>16)&0x1f; // target of shift
8434 rs2[i]=(source[i]>>21)&0x1f; // shift amount
8435 rt1[i]=(source[i]>>11)&0x1f; // destination
8436 rt2[i]=0;
8437 // DSLLV/DSRLV/DSRAV are 64-bit
8438 if(op2>=0x14&&op2<=0x17) us1[i]=rs1[i];
8439 break;
8440 case SHIFTIMM:
8441 rs1[i]=(source[i]>>16)&0x1f;
8442 rs2[i]=0;
8443 rt1[i]=(source[i]>>11)&0x1f;
8444 rt2[i]=0;
8445 imm[i]=(source[i]>>6)&0x1f;
8446 // DSxx32 instructions
8447 if(op2>=0x3c) imm[i]|=0x20;
8448 // DSLL/DSRL/DSRA/DSRA32/DSRL32 but not DSLL32 require 64-bit source
8449 if(op2>=0x38&&op2!=0x3c) us1[i]=rs1[i];
8450 break;
8451 case COP0:
8452 rs1[i]=0;
8453 rs2[i]=0;
8454 rt1[i]=0;
8455 rt2[i]=0;
8456 if(op2==0) rt1[i]=(source[i]>>16)&0x1F; // MFC0
8457 if(op2==4) rs1[i]=(source[i]>>16)&0x1F; // MTC0
8458 if(op2==4&&((source[i]>>11)&0x1f)==12) rt2[i]=CSREG; // Status
8459 if(op2==16) if((source[i]&0x3f)==0x18) rs2[i]=CCREG; // ERET
8460 break;
8461 case COP1:
b9b61529 8462 case COP2:
57871462 8463 rs1[i]=0;
8464 rs2[i]=0;
8465 rt1[i]=0;
8466 rt2[i]=0;
8467 if(op2<3) rt1[i]=(source[i]>>16)&0x1F; // MFC1/DMFC1/CFC1
8468 if(op2>3) rs1[i]=(source[i]>>16)&0x1F; // MTC1/DMTC1/CTC1
8469 if(op2==5) us1[i]=rs1[i]; // DMTC1
8470 rs2[i]=CSREG;
8471 break;
8472 case C1LS:
8473 rs1[i]=(source[i]>>21)&0x1F;
8474 rs2[i]=CSREG;
8475 rt1[i]=0;
8476 rt2[i]=0;
8477 imm[i]=(short)source[i];
8478 break;
b9b61529 8479 case C2LS:
8480 rs1[i]=(source[i]>>21)&0x1F;
8481 rs2[i]=0;
8482 rt1[i]=0;
8483 rt2[i]=0;
8484 imm[i]=(short)source[i];
8485 break;
57871462 8486 case FLOAT:
8487 case FCONV:
8488 rs1[i]=0;
8489 rs2[i]=CSREG;
8490 rt1[i]=0;
8491 rt2[i]=0;
8492 break;
8493 case FCOMP:
8494 rs1[i]=FSREG;
8495 rs2[i]=CSREG;
8496 rt1[i]=FSREG;
8497 rt2[i]=0;
8498 break;
8499 case SYSCALL:
7139f3c8 8500 case HLECALL:
1e973cb0 8501 case INTCALL:
57871462 8502 rs1[i]=CCREG;
8503 rs2[i]=0;
8504 rt1[i]=0;
8505 rt2[i]=0;
8506 break;
8507 default:
8508 rs1[i]=0;
8509 rs2[i]=0;
8510 rt1[i]=0;
8511 rt2[i]=0;
8512 }
8513 /* Calculate branch target addresses */
8514 if(type==UJUMP)
8515 ba[i]=((start+i*4+4)&0xF0000000)|(((unsigned int)source[i]<<6)>>4);
8516 else if(type==CJUMP&&rs1[i]==rs2[i]&&(op&1))
8517 ba[i]=start+i*4+8; // Ignore never taken branch
8518 else if(type==SJUMP&&rs1[i]==0&&!(op2&1))
8519 ba[i]=start+i*4+8; // Ignore never taken branch
8520 else if(type==CJUMP||type==SJUMP||type==FJUMP)
8521 ba[i]=start+i*4+4+((signed int)((unsigned int)source[i]<<16)>>14);
8522 else ba[i]=-1;
26869094 8523#ifdef PCSX
3e535354 8524 if(i>0&&(itype[i-1]==RJUMP||itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP)) {
8525 int do_in_intrp=0;
8526 // branch in delay slot?
8527 if(type==RJUMP||type==UJUMP||type==CJUMP||type==SJUMP||type==FJUMP) {
8528 // don't handle first branch and call interpreter if it's hit
8529 printf("branch in delay slot @%08x (%08x)\n", addr + i*4, addr);
8530 do_in_intrp=1;
8531 }
8532 // basic load delay detection
8533 else if((type==LOAD||type==LOADLR||type==COP0||type==COP2||type==C2LS)&&rt1[i]!=0) {
8534 int t=(ba[i-1]-start)/4;
8535 if(0 <= t && t < i &&(rt1[i]==rs1[t]||rt1[i]==rs2[t])&&itype[t]!=CJUMP&&itype[t]!=SJUMP) {
8536 // jump target wants DS result - potential load delay effect
8537 printf("load delay @%08x (%08x)\n", addr + i*4, addr);
8538 do_in_intrp=1;
8539 bt[t+1]=1; // expected return from interpreter
8540 }
8541 else if(i>=2&&rt1[i-2]==2&&rt1[i]==2&&rs1[i]!=2&&rs2[i]!=2&&rs1[i-1]!=2&&rs2[i-1]!=2&&
8542 !(i>=3&&(itype[i-3]==RJUMP||itype[i-3]==UJUMP||itype[i-3]==CJUMP||itype[i-3]==SJUMP))) {
8543 // v0 overwrite like this is a sign of trouble, bail out
8544 printf("v0 overwrite @%08x (%08x)\n", addr + i*4, addr);
8545 do_in_intrp=1;
8546 }
8547 }
3e535354 8548 if(do_in_intrp) {
8549 rs1[i-1]=CCREG;
8550 rs2[i-1]=rt1[i-1]=rt2[i-1]=0;
26869094 8551 ba[i-1]=-1;
8552 itype[i-1]=INTCALL;
8553 done=2;
3e535354 8554 i--; // don't compile the DS
26869094 8555 }
3e535354 8556 }
26869094 8557#endif
3e535354 8558 /* Is this the end of the block? */
8559 if(i>0&&(itype[i-1]==UJUMP||itype[i-1]==RJUMP||(source[i-1]>>16)==0x1000)) {
5067f341 8560 if(rt1[i-1]==0) { // Continue past subroutine call (JAL)
1e973cb0 8561 done=2;
57871462 8562 }
8563 else {
8564 if(stop_after_jal) done=1;
8565 // Stop on BREAK
8566 if((source[i+1]&0xfc00003f)==0x0d) done=1;
8567 }
8568 // Don't recompile stuff that's already compiled
8569 if(check_addr(start+i*4+4)) done=1;
8570 // Don't get too close to the limit
8571 if(i>MAXBLOCK/2) done=1;
8572 }
75dec299 8573 if(itype[i]==SYSCALL&&stop_after_jal) done=1;
1e973cb0 8574 if(itype[i]==HLECALL||itype[i]==INTCALL) done=2;
8575 if(done==2) {
8576 // Does the block continue due to a branch?
8577 for(j=i-1;j>=0;j--)
8578 {
2a706964 8579 if(ba[j]==start+i*4) done=j=0; // Branch into delay slot
1e973cb0 8580 if(ba[j]==start+i*4+4) done=j=0;
8581 if(ba[j]==start+i*4+8) done=j=0;
8582 }
8583 }
75dec299 8584 //assert(i<MAXBLOCK-1);
57871462 8585 if(start+i*4==pagelimit-4) done=1;
8586 assert(start+i*4<pagelimit);
8587 if (i==MAXBLOCK-1) done=1;
8588 // Stop if we're compiling junk
8589 if(itype[i]==NI&&opcode[i]==0x11) {
8590 done=stop_after_jal=1;
8591 printf("Disabled speculative precompilation\n");
8592 }
8593 }
8594 slen=i;
8595 if(itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==RJUMP||itype[i-1]==FJUMP) {
8596 if(start+i*4==pagelimit) {
8597 itype[i-1]=SPAN;
8598 }
8599 }
8600 assert(slen>0);
8601
8602 /* Pass 2 - Register dependencies and branch targets */
8603
8604 unneeded_registers(0,slen-1,0);
8605
8606 /* Pass 3 - Register allocation */
8607
8608 struct regstat current; // Current register allocations/status
8609 current.is32=1;
8610 current.dirty=0;
8611 current.u=unneeded_reg[0];
8612 current.uu=unneeded_reg_upper[0];
8613 clear_all_regs(current.regmap);
8614 alloc_reg(&current,0,CCREG);
8615 dirty_reg(&current,CCREG);
8616 current.isconst=0;
8617 current.wasconst=0;
8618 int ds=0;
8619 int cc=0;
5194fb95 8620 int hr=-1;
6ebf4adf 8621
8622#ifndef FORCE32
57871462 8623 provisional_32bit();
6ebf4adf 8624#endif
57871462 8625 if((u_int)addr&1) {
8626 // First instruction is delay slot
8627 cc=-1;
8628 bt[1]=1;
8629 ds=1;
8630 unneeded_reg[0]=1;
8631 unneeded_reg_upper[0]=1;
8632 current.regmap[HOST_BTREG]=BTREG;
8633 }
8634
8635 for(i=0;i<slen;i++)
8636 {
8637 if(bt[i])
8638 {
8639 int hr;
8640 for(hr=0;hr<HOST_REGS;hr++)
8641 {
8642 // Is this really necessary?
8643 if(current.regmap[hr]==0) current.regmap[hr]=-1;
8644 }
8645 current.isconst=0;
8646 }
8647 if(i>1)
8648 {
8649 if((opcode[i-2]&0x2f)==0x05) // BNE/BNEL
8650 {
8651 if(rs1[i-2]==0||rs2[i-2]==0)
8652 {
8653 if(rs1[i-2]) {
8654 current.is32|=1LL<<rs1[i-2];
8655 int hr=get_reg(current.regmap,rs1[i-2]|64);
8656 if(hr>=0) current.regmap[hr]=-1;
8657 }
8658 if(rs2[i-2]) {
8659 current.is32|=1LL<<rs2[i-2];
8660 int hr=get_reg(current.regmap,rs2[i-2]|64);
8661 if(hr>=0) current.regmap[hr]=-1;
8662 }
8663 }
8664 }
8665 }
6ebf4adf 8666#ifndef FORCE32
57871462 8667 // If something jumps here with 64-bit values
8668 // then promote those registers to 64 bits
8669 if(bt[i])
8670 {
8671 uint64_t temp_is32=current.is32;
8672 for(j=i-1;j>=0;j--)
8673 {
8674 if(ba[j]==start+i*4)
8675 temp_is32&=branch_regs[j].is32;
8676 }
8677 for(j=i;j<slen;j++)
8678 {
8679 if(ba[j]==start+i*4)
8680 //temp_is32=1;
8681 temp_is32&=p32[j];
8682 }
8683 if(temp_is32!=current.is32) {
8684 //printf("dumping 32-bit regs (%x)\n",start+i*4);
311301dc 8685 #ifndef DESTRUCTIVE_WRITEBACK
8686 if(ds)
8687 #endif
57871462 8688 for(hr=0;hr<HOST_REGS;hr++)
8689 {
8690 int r=current.regmap[hr];
8691 if(r>0&&r<64)
8692 {
8693 if((current.dirty>>hr)&((current.is32&~temp_is32)>>r)&1) {
8694 temp_is32|=1LL<<r;
8695 //printf("restore %d\n",r);
8696 }
8697 }
8698 }
57871462 8699 current.is32=temp_is32;
8700 }
8701 }
6ebf4adf 8702#else
24385cae 8703 current.is32=-1LL;
8704#endif
8705
57871462 8706 memcpy(regmap_pre[i],current.regmap,sizeof(current.regmap));
8707 regs[i].wasconst=current.isconst;
8708 regs[i].was32=current.is32;
8709 regs[i].wasdirty=current.dirty;
6ebf4adf 8710 #if defined(DESTRUCTIVE_WRITEBACK) && !defined(FORCE32)
57871462 8711 // To change a dirty register from 32 to 64 bits, we must write
8712 // it out during the previous cycle (for branches, 2 cycles)
8713 if(i<slen-1&&bt[i+1]&&itype[i-1]!=UJUMP&&itype[i-1]!=CJUMP&&itype[i-1]!=SJUMP&&itype[i-1]!=RJUMP&&itype[i-1]!=FJUMP)
8714 {
8715 uint64_t temp_is32=current.is32;
8716 for(j=i-1;j>=0;j--)
8717 {
8718 if(ba[j]==start+i*4+4)
8719 temp_is32&=branch_regs[j].is32;
8720 }
8721 for(j=i;j<slen;j++)
8722 {
8723 if(ba[j]==start+i*4+4)
8724 //temp_is32=1;
8725 temp_is32&=p32[j];
8726 }
8727 if(temp_is32!=current.is32) {
8728 //printf("pre-dumping 32-bit regs (%x)\n",start+i*4);
8729 for(hr=0;hr<HOST_REGS;hr++)
8730 {
8731 int r=current.regmap[hr];
8732 if(r>0)
8733 {
8734 if((current.dirty>>hr)&((current.is32&~temp_is32)>>(r&63))&1) {
8735 if(itype[i]!=UJUMP&&itype[i]!=CJUMP&&itype[i]!=SJUMP&&itype[i]!=RJUMP&&itype[i]!=FJUMP)
8736 {
8737 if(rs1[i]!=(r&63)&&rs2[i]!=(r&63))
8738 {
8739 //printf("dump %d/r%d\n",hr,r);
8740 current.regmap[hr]=-1;
8741 if(get_reg(current.regmap,r|64)>=0)
8742 current.regmap[get_reg(current.regmap,r|64)]=-1;
8743 }
8744 }
8745 }
8746 }
8747 }
8748 }
8749 }
8750 else if(i<slen-2&&bt[i+2]&&(source[i-1]>>16)!=0x1000&&(itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP))
8751 {
8752 uint64_t temp_is32=current.is32;
8753 for(j=i-1;j>=0;j--)
8754 {
8755 if(ba[j]==start+i*4+8)
8756 temp_is32&=branch_regs[j].is32;
8757 }
8758 for(j=i;j<slen;j++)
8759 {
8760 if(ba[j]==start+i*4+8)
8761 //temp_is32=1;
8762 temp_is32&=p32[j];
8763 }
8764 if(temp_is32!=current.is32) {
8765 //printf("pre-dumping 32-bit regs (%x)\n",start+i*4);
8766 for(hr=0;hr<HOST_REGS;hr++)
8767 {
8768 int r=current.regmap[hr];
8769 if(r>0)
8770 {
8771 if((current.dirty>>hr)&((current.is32&~temp_is32)>>(r&63))&1) {
8772 if(rs1[i]!=(r&63)&&rs2[i]!=(r&63)&&rs1[i+1]!=(r&63)&&rs2[i+1]!=(r&63))
8773 {
8774 //printf("dump %d/r%d\n",hr,r);
8775 current.regmap[hr]=-1;
8776 if(get_reg(current.regmap,r|64)>=0)
8777 current.regmap[get_reg(current.regmap,r|64)]=-1;
8778 }
8779 }
8780 }
8781 }
8782 }
8783 }
8784 #endif
8785 if(itype[i]!=UJUMP&&itype[i]!=CJUMP&&itype[i]!=SJUMP&&itype[i]!=RJUMP&&itype[i]!=FJUMP) {
8786 if(i+1<slen) {
8787 current.u=unneeded_reg[i+1]&~((1LL<<rs1[i])|(1LL<<rs2[i]));
8788 current.uu=unneeded_reg_upper[i+1]&~((1LL<<us1[i])|(1LL<<us2[i]));
8789 if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
8790 current.u|=1;
8791 current.uu|=1;
8792 } else {
8793 current.u=1;
8794 current.uu=1;
8795 }
8796 } else {
8797 if(i+1<slen) {
8798 current.u=branch_unneeded_reg[i]&~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
8799 current.uu=branch_unneeded_reg_upper[i]&~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
8800 if((~current.uu>>rt1[i+1])&1) current.uu&=~((1LL<<dep1[i+1])|(1LL<<dep2[i+1]));
8801 current.u&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
8802 current.uu&=~((1LL<<us1[i])|(1LL<<us2[i]));
8803 current.u|=1;
8804 current.uu|=1;
8805 } else { printf("oops, branch at end of block with no delay slot\n");exit(1); }
8806 }
8807 is_ds[i]=ds;
8808 if(ds) {
8809 ds=0; // Skip delay slot, already allocated as part of branch
8810 // ...but we need to alloc it in case something jumps here
8811 if(i+1<slen) {
8812 current.u=branch_unneeded_reg[i-1]&unneeded_reg[i+1];
8813 current.uu=branch_unneeded_reg_upper[i-1]&unneeded_reg_upper[i+1];
8814 }else{
8815 current.u=branch_unneeded_reg[i-1];
8816 current.uu=branch_unneeded_reg_upper[i-1];
8817 }
8818 current.u&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
8819 current.uu&=~((1LL<<us1[i])|(1LL<<us2[i]));
8820 if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
8821 current.u|=1;
8822 current.uu|=1;
8823 struct regstat temp;
8824 memcpy(&temp,&current,sizeof(current));
8825 temp.wasdirty=temp.dirty;
8826 temp.was32=temp.is32;
8827 // TODO: Take into account unconditional branches, as below
8828 delayslot_alloc(&temp,i);
8829 memcpy(regs[i].regmap,temp.regmap,sizeof(temp.regmap));
8830 regs[i].wasdirty=temp.wasdirty;
8831 regs[i].was32=temp.was32;
8832 regs[i].dirty=temp.dirty;
8833 regs[i].is32=temp.is32;
8834 regs[i].isconst=0;
8835 regs[i].wasconst=0;
8836 current.isconst=0;
8837 // Create entry (branch target) regmap
8838 for(hr=0;hr<HOST_REGS;hr++)
8839 {
8840 int r=temp.regmap[hr];
8841 if(r>=0) {
8842 if(r!=regmap_pre[i][hr]) {
8843 regs[i].regmap_entry[hr]=-1;
8844 }
8845 else
8846 {
8847 if(r<64){
8848 if((current.u>>r)&1) {
8849 regs[i].regmap_entry[hr]=-1;
8850 regs[i].regmap[hr]=-1;
8851 //Don't clear regs in the delay slot as the branch might need them
8852 //current.regmap[hr]=-1;
8853 }else
8854 regs[i].regmap_entry[hr]=r;
8855 }
8856 else {
8857 if((current.uu>>(r&63))&1) {
8858 regs[i].regmap_entry[hr]=-1;
8859 regs[i].regmap[hr]=-1;
8860 //Don't clear regs in the delay slot as the branch might need them
8861 //current.regmap[hr]=-1;
8862 }else
8863 regs[i].regmap_entry[hr]=r;
8864 }
8865 }
8866 } else {
8867 // First instruction expects CCREG to be allocated
8868 if(i==0&&hr==HOST_CCREG)
8869 regs[i].regmap_entry[hr]=CCREG;
8870 else
8871 regs[i].regmap_entry[hr]=-1;
8872 }
8873 }
8874 }
8875 else { // Not delay slot
8876 switch(itype[i]) {
8877 case UJUMP:
8878 //current.isconst=0; // DEBUG
8879 //current.wasconst=0; // DEBUG
8880 //regs[i].wasconst=0; // DEBUG
8881 clear_const(&current,rt1[i]);
8882 alloc_cc(&current,i);
8883 dirty_reg(&current,CCREG);
8884 if (rt1[i]==31) {
8885 alloc_reg(&current,i,31);
8886 dirty_reg(&current,31);
4ef8f67d 8887 //assert(rs1[i+1]!=31&&rs2[i+1]!=31);
8888 //assert(rt1[i+1]!=rt1[i]);
57871462 8889 #ifdef REG_PREFETCH
8890 alloc_reg(&current,i,PTEMP);
8891 #endif
8892 //current.is32|=1LL<<rt1[i];
8893 }
269bb29a 8894 ooo[i]=1;
8895 delayslot_alloc(&current,i+1);
57871462 8896 //current.isconst=0; // DEBUG
8897 ds=1;
8898 //printf("i=%d, isconst=%x\n",i,current.isconst);
8899 break;
8900 case RJUMP:
8901 //current.isconst=0;
8902 //current.wasconst=0;
8903 //regs[i].wasconst=0;
8904 clear_const(&current,rs1[i]);
8905 clear_const(&current,rt1[i]);
8906 alloc_cc(&current,i);
8907 dirty_reg(&current,CCREG);
8908 if(rs1[i]!=rt1[i+1]&&rs1[i]!=rt2[i+1]) {
8909 alloc_reg(&current,i,rs1[i]);
5067f341 8910 if (rt1[i]!=0) {
8911 alloc_reg(&current,i,rt1[i]);
8912 dirty_reg(&current,rt1[i]);
68b3faee 8913 assert(rs1[i+1]!=rt1[i]&&rs2[i+1]!=rt1[i]);
076655d1 8914 assert(rt1[i+1]!=rt1[i]);
57871462 8915 #ifdef REG_PREFETCH
8916 alloc_reg(&current,i,PTEMP);
8917 #endif
8918 }
8919 #ifdef USE_MINI_HT
8920 if(rs1[i]==31) { // JALR
8921 alloc_reg(&current,i,RHASH);
8922 #ifndef HOST_IMM_ADDR32
8923 alloc_reg(&current,i,RHTBL);
8924 #endif
8925 }
8926 #endif
8927 delayslot_alloc(&current,i+1);
8928 } else {
8929 // The delay slot overwrites our source register,
8930 // allocate a temporary register to hold the old value.
8931 current.isconst=0;
8932 current.wasconst=0;
8933 regs[i].wasconst=0;
8934 delayslot_alloc(&current,i+1);
8935 current.isconst=0;
8936 alloc_reg(&current,i,RTEMP);
8937 }
8938 //current.isconst=0; // DEBUG
e1190b87 8939 ooo[i]=1;
57871462 8940 ds=1;
8941 break;
8942 case CJUMP:
8943 //current.isconst=0;
8944 //current.wasconst=0;
8945 //regs[i].wasconst=0;
8946 clear_const(&current,rs1[i]);
8947 clear_const(&current,rs2[i]);
8948 if((opcode[i]&0x3E)==4) // BEQ/BNE
8949 {
8950 alloc_cc(&current,i);
8951 dirty_reg(&current,CCREG);
8952 if(rs1[i]) alloc_reg(&current,i,rs1[i]);
8953 if(rs2[i]) alloc_reg(&current,i,rs2[i]);
8954 if(!((current.is32>>rs1[i])&(current.is32>>rs2[i])&1))
8955 {
8956 if(rs1[i]) alloc_reg64(&current,i,rs1[i]);
8957 if(rs2[i]) alloc_reg64(&current,i,rs2[i]);
8958 }
8959 if((rs1[i]&&(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1]))||
8960 (rs2[i]&&(rs2[i]==rt1[i+1]||rs2[i]==rt2[i+1]))) {
8961 // The delay slot overwrites one of our conditions.
8962 // Allocate the branch condition registers instead.
57871462 8963 current.isconst=0;
8964 current.wasconst=0;
8965 regs[i].wasconst=0;
8966 if(rs1[i]) alloc_reg(&current,i,rs1[i]);
8967 if(rs2[i]) alloc_reg(&current,i,rs2[i]);
8968 if(!((current.is32>>rs1[i])&(current.is32>>rs2[i])&1))
8969 {
8970 if(rs1[i]) alloc_reg64(&current,i,rs1[i]);
8971 if(rs2[i]) alloc_reg64(&current,i,rs2[i]);
8972 }
8973 }
e1190b87 8974 else
8975 {
8976 ooo[i]=1;
8977 delayslot_alloc(&current,i+1);
8978 }
57871462 8979 }
8980 else
8981 if((opcode[i]&0x3E)==6) // BLEZ/BGTZ
8982 {
8983 alloc_cc(&current,i);
8984 dirty_reg(&current,CCREG);
8985 alloc_reg(&current,i,rs1[i]);
8986 if(!(current.is32>>rs1[i]&1))
8987 {
8988 alloc_reg64(&current,i,rs1[i]);
8989 }
8990 if(rs1[i]&&(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1])) {
8991 // The delay slot overwrites one of our conditions.
8992 // Allocate the branch condition registers instead.
57871462 8993 current.isconst=0;
8994 current.wasconst=0;
8995 regs[i].wasconst=0;
8996 if(rs1[i]) alloc_reg(&current,i,rs1[i]);
8997 if(!((current.is32>>rs1[i])&1))
8998 {
8999 if(rs1[i]) alloc_reg64(&current,i,rs1[i]);
9000 }
9001 }
e1190b87 9002 else
9003 {
9004 ooo[i]=1;
9005 delayslot_alloc(&current,i+1);
9006 }
57871462 9007 }
9008 else
9009 // Don't alloc the delay slot yet because we might not execute it
9010 if((opcode[i]&0x3E)==0x14) // BEQL/BNEL
9011 {
9012 current.isconst=0;
9013 current.wasconst=0;
9014 regs[i].wasconst=0;
9015 alloc_cc(&current,i);
9016 dirty_reg(&current,CCREG);
9017 alloc_reg(&current,i,rs1[i]);
9018 alloc_reg(&current,i,rs2[i]);
9019 if(!((current.is32>>rs1[i])&(current.is32>>rs2[i])&1))
9020 {
9021 alloc_reg64(&current,i,rs1[i]);
9022 alloc_reg64(&current,i,rs2[i]);
9023 }
9024 }
9025 else
9026 if((opcode[i]&0x3E)==0x16) // BLEZL/BGTZL
9027 {
9028 current.isconst=0;
9029 current.wasconst=0;
9030 regs[i].wasconst=0;
9031 alloc_cc(&current,i);
9032 dirty_reg(&current,CCREG);
9033 alloc_reg(&current,i,rs1[i]);
9034 if(!(current.is32>>rs1[i]&1))
9035 {
9036 alloc_reg64(&current,i,rs1[i]);
9037 }
9038 }
9039 ds=1;
9040 //current.isconst=0;
9041 break;
9042 case SJUMP:
9043 //current.isconst=0;
9044 //current.wasconst=0;
9045 //regs[i].wasconst=0;
9046 clear_const(&current,rs1[i]);
9047 clear_const(&current,rt1[i]);
9048 //if((opcode2[i]&0x1E)==0x0) // BLTZ/BGEZ
9049 if((opcode2[i]&0x0E)==0x0) // BLTZ/BGEZ
9050 {
9051 alloc_cc(&current,i);
9052 dirty_reg(&current,CCREG);
9053 alloc_reg(&current,i,rs1[i]);
9054 if(!(current.is32>>rs1[i]&1))
9055 {
9056 alloc_reg64(&current,i,rs1[i]);
9057 }
9058 if (rt1[i]==31) { // BLTZAL/BGEZAL
9059 alloc_reg(&current,i,31);
9060 dirty_reg(&current,31);
57871462 9061 //#ifdef REG_PREFETCH
9062 //alloc_reg(&current,i,PTEMP);
9063 //#endif
9064 //current.is32|=1LL<<rt1[i];
9065 }
e1190b87 9066 if((rs1[i]&&(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1])) // The delay slot overwrites the branch condition.
9067 ||(rt1[i]==31&&(rs1[i+1]==31||rs2[i+1]==31||rt1[i+1]==31||rt2[i+1]==31))) { // DS touches $ra
57871462 9068 // Allocate the branch condition registers instead.
57871462 9069 current.isconst=0;
9070 current.wasconst=0;
9071 regs[i].wasconst=0;
9072 if(rs1[i]) alloc_reg(&current,i,rs1[i]);
9073 if(!((current.is32>>rs1[i])&1))
9074 {
9075 if(rs1[i]) alloc_reg64(&current,i,rs1[i]);
9076 }
9077 }
e1190b87 9078 else
9079 {
9080 ooo[i]=1;
9081 delayslot_alloc(&current,i+1);
9082 }
57871462 9083 }
9084 else
9085 // Don't alloc the delay slot yet because we might not execute it
9086 if((opcode2[i]&0x1E)==0x2) // BLTZL/BGEZL
9087 {
9088 current.isconst=0;
9089 current.wasconst=0;
9090 regs[i].wasconst=0;
9091 alloc_cc(&current,i);
9092 dirty_reg(&current,CCREG);
9093 alloc_reg(&current,i,rs1[i]);
9094 if(!(current.is32>>rs1[i]&1))
9095 {
9096 alloc_reg64(&current,i,rs1[i]);
9097 }
9098 }
9099 ds=1;
9100 //current.isconst=0;
9101 break;
9102 case FJUMP:
9103 current.isconst=0;
9104 current.wasconst=0;
9105 regs[i].wasconst=0;
9106 if(likely[i]==0) // BC1F/BC1T
9107 {
9108 // TODO: Theoretically we can run out of registers here on x86.
9109 // The delay slot can allocate up to six, and we need to check
9110 // CSREG before executing the delay slot. Possibly we can drop
9111 // the cycle count and then reload it after checking that the
9112 // FPU is in a usable state, or don't do out-of-order execution.
9113 alloc_cc(&current,i);
9114 dirty_reg(&current,CCREG);
9115 alloc_reg(&current,i,FSREG);
9116 alloc_reg(&current,i,CSREG);
9117 if(itype[i+1]==FCOMP) {
9118 // The delay slot overwrites the branch condition.
9119 // Allocate the branch condition registers instead.
57871462 9120 alloc_cc(&current,i);
9121 dirty_reg(&current,CCREG);
9122 alloc_reg(&current,i,CSREG);
9123 alloc_reg(&current,i,FSREG);
9124 }
9125 else {
e1190b87 9126 ooo[i]=1;
57871462 9127 delayslot_alloc(&current,i+1);
9128 alloc_reg(&current,i+1,CSREG);
9129 }
9130 }
9131 else
9132 // Don't alloc the delay slot yet because we might not execute it
9133 if(likely[i]) // BC1FL/BC1TL
9134 {
9135 alloc_cc(&current,i);
9136 dirty_reg(&current,CCREG);
9137 alloc_reg(&current,i,CSREG);
9138 alloc_reg(&current,i,FSREG);
9139 }
9140 ds=1;
9141 current.isconst=0;
9142 break;
9143 case IMM16:
9144 imm16_alloc(&current,i);
9145 break;
9146 case LOAD:
9147 case LOADLR:
9148 load_alloc(&current,i);
9149 break;
9150 case STORE:
9151 case STORELR:
9152 store_alloc(&current,i);
9153 break;
9154 case ALU:
9155 alu_alloc(&current,i);
9156 break;
9157 case SHIFT:
9158 shift_alloc(&current,i);
9159 break;
9160 case MULTDIV:
9161 multdiv_alloc(&current,i);
9162 break;
9163 case SHIFTIMM:
9164 shiftimm_alloc(&current,i);
9165 break;
9166 case MOV:
9167 mov_alloc(&current,i);
9168 break;
9169 case COP0:
9170 cop0_alloc(&current,i);
9171 break;
9172 case COP1:
b9b61529 9173 case COP2:
57871462 9174 cop1_alloc(&current,i);
9175 break;
9176 case C1LS:
9177 c1ls_alloc(&current,i);
9178 break;
b9b61529 9179 case C2LS:
9180 c2ls_alloc(&current,i);
9181 break;
9182 case C2OP:
9183 c2op_alloc(&current,i);
9184 break;
57871462 9185 case FCONV:
9186 fconv_alloc(&current,i);
9187 break;
9188 case FLOAT:
9189 float_alloc(&current,i);
9190 break;
9191 case FCOMP:
9192 fcomp_alloc(&current,i);
9193 break;
9194 case SYSCALL:
7139f3c8 9195 case HLECALL:
1e973cb0 9196 case INTCALL:
57871462 9197 syscall_alloc(&current,i);
9198 break;
9199 case SPAN:
9200 pagespan_alloc(&current,i);
9201 break;
9202 }
9203
9204 // Drop the upper half of registers that have become 32-bit
9205 current.uu|=current.is32&((1LL<<rt1[i])|(1LL<<rt2[i]));
9206 if(itype[i]!=UJUMP&&itype[i]!=CJUMP&&itype[i]!=SJUMP&&itype[i]!=RJUMP&&itype[i]!=FJUMP) {
9207 current.uu&=~((1LL<<us1[i])|(1LL<<us2[i]));
9208 if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
9209 current.uu|=1;
9210 } else {
9211 current.uu|=current.is32&((1LL<<rt1[i+1])|(1LL<<rt2[i+1]));
9212 current.uu&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
9213 if((~current.uu>>rt1[i+1])&1) current.uu&=~((1LL<<dep1[i+1])|(1LL<<dep2[i+1]));
9214 current.uu&=~((1LL<<us1[i])|(1LL<<us2[i]));
9215 current.uu|=1;
9216 }
9217
9218 // Create entry (branch target) regmap
9219 for(hr=0;hr<HOST_REGS;hr++)
9220 {
9221 int r,or,er;
9222 r=current.regmap[hr];
9223 if(r>=0) {
9224 if(r!=regmap_pre[i][hr]) {
9225 // TODO: delay slot (?)
9226 or=get_reg(regmap_pre[i],r); // Get old mapping for this register
9227 if(or<0||(r&63)>=TEMPREG){
9228 regs[i].regmap_entry[hr]=-1;
9229 }
9230 else
9231 {
9232 // Just move it to a different register
9233 regs[i].regmap_entry[hr]=r;
9234 // If it was dirty before, it's still dirty
9235 if((regs[i].wasdirty>>or)&1) dirty_reg(&current,r&63);
9236 }
9237 }
9238 else
9239 {
9240 // Unneeded
9241 if(r==0){
9242 regs[i].regmap_entry[hr]=0;
9243 }
9244 else
9245 if(r<64){
9246 if((current.u>>r)&1) {
9247 regs[i].regmap_entry[hr]=-1;
9248 //regs[i].regmap[hr]=-1;
9249 current.regmap[hr]=-1;
9250 }else
9251 regs[i].regmap_entry[hr]=r;
9252 }
9253 else {
9254 if((current.uu>>(r&63))&1) {
9255 regs[i].regmap_entry[hr]=-1;
9256 //regs[i].regmap[hr]=-1;
9257 current.regmap[hr]=-1;
9258 }else
9259 regs[i].regmap_entry[hr]=r;
9260 }
9261 }
9262 } else {
9263 // Branches expect CCREG to be allocated at the target
9264 if(regmap_pre[i][hr]==CCREG)
9265 regs[i].regmap_entry[hr]=CCREG;
9266 else
9267 regs[i].regmap_entry[hr]=-1;
9268 }
9269 }
9270 memcpy(regs[i].regmap,current.regmap,sizeof(current.regmap));
9271 }
9272 /* Branch post-alloc */
9273 if(i>0)
9274 {
9275 current.was32=current.is32;
9276 current.wasdirty=current.dirty;
9277 switch(itype[i-1]) {
9278 case UJUMP:
9279 memcpy(&branch_regs[i-1],&current,sizeof(current));
9280 branch_regs[i-1].isconst=0;
9281 branch_regs[i-1].wasconst=0;
9282 branch_regs[i-1].u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i-1])|(1LL<<rs2[i-1]));
9283 branch_regs[i-1].uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i-1])|(1LL<<us2[i-1]));
9284 alloc_cc(&branch_regs[i-1],i-1);
9285 dirty_reg(&branch_regs[i-1],CCREG);
9286 if(rt1[i-1]==31) { // JAL
9287 alloc_reg(&branch_regs[i-1],i-1,31);
9288 dirty_reg(&branch_regs[i-1],31);
9289 branch_regs[i-1].is32|=1LL<<31;
9290 }
9291 memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
9292 memcpy(constmap[i],constmap[i-1],sizeof(current.constmap));
9293 break;
9294 case RJUMP:
9295 memcpy(&branch_regs[i-1],&current,sizeof(current));
9296 branch_regs[i-1].isconst=0;
9297 branch_regs[i-1].wasconst=0;
9298 branch_regs[i-1].u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i-1])|(1LL<<rs2[i-1]));
9299 branch_regs[i-1].uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i-1])|(1LL<<us2[i-1]));
9300 alloc_cc(&branch_regs[i-1],i-1);
9301 dirty_reg(&branch_regs[i-1],CCREG);
9302 alloc_reg(&branch_regs[i-1],i-1,rs1[i-1]);
5067f341 9303 if(rt1[i-1]!=0) { // JALR
9304 alloc_reg(&branch_regs[i-1],i-1,rt1[i-1]);
9305 dirty_reg(&branch_regs[i-1],rt1[i-1]);
9306 branch_regs[i-1].is32|=1LL<<rt1[i-1];
57871462 9307 }
9308 #ifdef USE_MINI_HT
9309 if(rs1[i-1]==31) { // JALR
9310 alloc_reg(&branch_regs[i-1],i-1,RHASH);
9311 #ifndef HOST_IMM_ADDR32
9312 alloc_reg(&branch_regs[i-1],i-1,RHTBL);
9313 #endif
9314 }
9315 #endif
9316 memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
9317 memcpy(constmap[i],constmap[i-1],sizeof(current.constmap));
9318 break;
9319 case CJUMP:
9320 if((opcode[i-1]&0x3E)==4) // BEQ/BNE
9321 {
9322 alloc_cc(&current,i-1);
9323 dirty_reg(&current,CCREG);
9324 if((rs1[i-1]&&(rs1[i-1]==rt1[i]||rs1[i-1]==rt2[i]))||
9325 (rs2[i-1]&&(rs2[i-1]==rt1[i]||rs2[i-1]==rt2[i]))) {
9326 // The delay slot overwrote one of our conditions
9327 // Delay slot goes after the test (in order)
9328 current.u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i]));
9329 current.uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i]));
9330 if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
9331 current.u|=1;
9332 current.uu|=1;
9333 delayslot_alloc(&current,i);
9334 current.isconst=0;
9335 }
9336 else
9337 {
9338 current.u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i-1])|(1LL<<rs2[i-1]));
9339 current.uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i-1])|(1LL<<us2[i-1]));
9340 // Alloc the branch condition registers
9341 if(rs1[i-1]) alloc_reg(&current,i-1,rs1[i-1]);
9342 if(rs2[i-1]) alloc_reg(&current,i-1,rs2[i-1]);
9343 if(!((current.is32>>rs1[i-1])&(current.is32>>rs2[i-1])&1))
9344 {
9345 if(rs1[i-1]) alloc_reg64(&current,i-1,rs1[i-1]);
9346 if(rs2[i-1]) alloc_reg64(&current,i-1,rs2[i-1]);
9347 }
9348 }
9349 memcpy(&branch_regs[i-1],&current,sizeof(current));
9350 branch_regs[i-1].isconst=0;
9351 branch_regs[i-1].wasconst=0;
9352 memcpy(&branch_regs[i-1].regmap_entry,&current.regmap,sizeof(current.regmap));
9353 memcpy(constmap[i],constmap[i-1],sizeof(current.constmap));
9354 }
9355 else
9356 if((opcode[i-1]&0x3E)==6) // BLEZ/BGTZ
9357 {
9358 alloc_cc(&current,i-1);
9359 dirty_reg(&current,CCREG);
9360 if(rs1[i-1]==rt1[i]||rs1[i-1]==rt2[i]) {
9361 // The delay slot overwrote the branch condition
9362 // Delay slot goes after the test (in order)
9363 current.u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i]));
9364 current.uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i]));
9365 if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
9366 current.u|=1;
9367 current.uu|=1;
9368 delayslot_alloc(&current,i);
9369 current.isconst=0;
9370 }
9371 else
9372 {
9373 current.u=branch_unneeded_reg[i-1]&~(1LL<<rs1[i-1]);
9374 current.uu=branch_unneeded_reg_upper[i-1]&~(1LL<<us1[i-1]);
9375 // Alloc the branch condition register
9376 alloc_reg(&current,i-1,rs1[i-1]);
9377 if(!(current.is32>>rs1[i-1]&1))
9378 {
9379 alloc_reg64(&current,i-1,rs1[i-1]);
9380 }
9381 }
9382 memcpy(&branch_regs[i-1],&current,sizeof(current));
9383 branch_regs[i-1].isconst=0;
9384 branch_regs[i-1].wasconst=0;
9385 memcpy(&branch_regs[i-1].regmap_entry,&current.regmap,sizeof(current.regmap));
9386 memcpy(constmap[i],constmap[i-1],sizeof(current.constmap));
9387 }
9388 else
9389 // Alloc the delay slot in case the branch is taken
9390 if((opcode[i-1]&0x3E)==0x14) // BEQL/BNEL
9391 {
9392 memcpy(&branch_regs[i-1],&current,sizeof(current));
9393 branch_regs[i-1].u=(branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9394 branch_regs[i-1].uu=(branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9395 if((~branch_regs[i-1].uu>>rt1[i])&1) branch_regs[i-1].uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]))|1;
9396 alloc_cc(&branch_regs[i-1],i);
9397 dirty_reg(&branch_regs[i-1],CCREG);
9398 delayslot_alloc(&branch_regs[i-1],i);
9399 branch_regs[i-1].isconst=0;
9400 alloc_reg(&current,i,CCREG); // Not taken path
9401 dirty_reg(&current,CCREG);
9402 memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
9403 }
9404 else
9405 if((opcode[i-1]&0x3E)==0x16) // BLEZL/BGTZL
9406 {
9407 memcpy(&branch_regs[i-1],&current,sizeof(current));
9408 branch_regs[i-1].u=(branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9409 branch_regs[i-1].uu=(branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9410 if((~branch_regs[i-1].uu>>rt1[i])&1) branch_regs[i-1].uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]))|1;
9411 alloc_cc(&branch_regs[i-1],i);
9412 dirty_reg(&branch_regs[i-1],CCREG);
9413 delayslot_alloc(&branch_regs[i-1],i);
9414 branch_regs[i-1].isconst=0;
9415 alloc_reg(&current,i,CCREG); // Not taken path
9416 dirty_reg(&current,CCREG);
9417 memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
9418 }
9419 break;
9420 case SJUMP:
9421 //if((opcode2[i-1]&0x1E)==0) // BLTZ/BGEZ
9422 if((opcode2[i-1]&0x0E)==0) // BLTZ/BGEZ
9423 {
9424 alloc_cc(&current,i-1);
9425 dirty_reg(&current,CCREG);
9426 if(rs1[i-1]==rt1[i]||rs1[i-1]==rt2[i]) {
9427 // The delay slot overwrote the branch condition
9428 // Delay slot goes after the test (in order)
9429 current.u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i]));
9430 current.uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i]));
9431 if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
9432 current.u|=1;
9433 current.uu|=1;
9434 delayslot_alloc(&current,i);
9435 current.isconst=0;
9436 }
9437 else
9438 {
9439 current.u=branch_unneeded_reg[i-1]&~(1LL<<rs1[i-1]);
9440 current.uu=branch_unneeded_reg_upper[i-1]&~(1LL<<us1[i-1]);
9441 // Alloc the branch condition register
9442 alloc_reg(&current,i-1,rs1[i-1]);
9443 if(!(current.is32>>rs1[i-1]&1))
9444 {
9445 alloc_reg64(&current,i-1,rs1[i-1]);
9446 }
9447 }
9448 memcpy(&branch_regs[i-1],&current,sizeof(current));
9449 branch_regs[i-1].isconst=0;
9450 branch_regs[i-1].wasconst=0;
9451 memcpy(&branch_regs[i-1].regmap_entry,&current.regmap,sizeof(current.regmap));
9452 memcpy(constmap[i],constmap[i-1],sizeof(current.constmap));
9453 }
9454 else
9455 // Alloc the delay slot in case the branch is taken
9456 if((opcode2[i-1]&0x1E)==2) // BLTZL/BGEZL
9457 {
9458 memcpy(&branch_regs[i-1],&current,sizeof(current));
9459 branch_regs[i-1].u=(branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9460 branch_regs[i-1].uu=(branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9461 if((~branch_regs[i-1].uu>>rt1[i])&1) branch_regs[i-1].uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]))|1;
9462 alloc_cc(&branch_regs[i-1],i);
9463 dirty_reg(&branch_regs[i-1],CCREG);
9464 delayslot_alloc(&branch_regs[i-1],i);
9465 branch_regs[i-1].isconst=0;
9466 alloc_reg(&current,i,CCREG); // Not taken path
9467 dirty_reg(&current,CCREG);
9468 memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
9469 }
9470 // FIXME: BLTZAL/BGEZAL
9471 if(opcode2[i-1]&0x10) { // BxxZAL
9472 alloc_reg(&branch_regs[i-1],i-1,31);
9473 dirty_reg(&branch_regs[i-1],31);
9474 branch_regs[i-1].is32|=1LL<<31;
9475 }
9476 break;
9477 case FJUMP:
9478 if(likely[i-1]==0) // BC1F/BC1T
9479 {
9480 alloc_cc(&current,i-1);
9481 dirty_reg(&current,CCREG);
9482 if(itype[i]==FCOMP) {
9483 // The delay slot overwrote the branch condition
9484 // Delay slot goes after the test (in order)
9485 delayslot_alloc(&current,i);
9486 current.isconst=0;
9487 }
9488 else
9489 {
9490 current.u=branch_unneeded_reg[i-1]&~(1LL<<rs1[i-1]);
9491 current.uu=branch_unneeded_reg_upper[i-1]&~(1LL<<us1[i-1]);
9492 // Alloc the branch condition register
9493 alloc_reg(&current,i-1,FSREG);
9494 }
9495 memcpy(&branch_regs[i-1],&current,sizeof(current));
9496 memcpy(&branch_regs[i-1].regmap_entry,&current.regmap,sizeof(current.regmap));
9497 }
9498 else // BC1FL/BC1TL
9499 {
9500 // Alloc the delay slot in case the branch is taken
9501 memcpy(&branch_regs[i-1],&current,sizeof(current));
9502 branch_regs[i-1].u=(branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9503 branch_regs[i-1].uu=(branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9504 if((~branch_regs[i-1].uu>>rt1[i])&1) branch_regs[i-1].uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]))|1;
9505 alloc_cc(&branch_regs[i-1],i);
9506 dirty_reg(&branch_regs[i-1],CCREG);
9507 delayslot_alloc(&branch_regs[i-1],i);
9508 branch_regs[i-1].isconst=0;
9509 alloc_reg(&current,i,CCREG); // Not taken path
9510 dirty_reg(&current,CCREG);
9511 memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
9512 }
9513 break;
9514 }
9515
9516 if(itype[i-1]==UJUMP||itype[i-1]==RJUMP||(source[i-1]>>16)==0x1000)
9517 {
9518 if(rt1[i-1]==31) // JAL/JALR
9519 {
9520 // Subroutine call will return here, don't alloc any registers
9521 current.is32=1;
9522 current.dirty=0;
9523 clear_all_regs(current.regmap);
9524 alloc_reg(&current,i,CCREG);
9525 dirty_reg(&current,CCREG);
9526 }
9527 else if(i+1<slen)
9528 {
9529 // Internal branch will jump here, match registers to caller
9530 current.is32=0x3FFFFFFFFLL;
9531 current.dirty=0;
9532 clear_all_regs(current.regmap);
9533 alloc_reg(&current,i,CCREG);
9534 dirty_reg(&current,CCREG);
9535 for(j=i-1;j>=0;j--)
9536 {
9537 if(ba[j]==start+i*4+4) {
9538 memcpy(current.regmap,branch_regs[j].regmap,sizeof(current.regmap));
9539 current.is32=branch_regs[j].is32;
9540 current.dirty=branch_regs[j].dirty;
9541 break;
9542 }
9543 }
9544 while(j>=0) {
9545 if(ba[j]==start+i*4+4) {
9546 for(hr=0;hr<HOST_REGS;hr++) {
9547 if(current.regmap[hr]!=branch_regs[j].regmap[hr]) {
9548 current.regmap[hr]=-1;
9549 }
9550 current.is32&=branch_regs[j].is32;
9551 current.dirty&=branch_regs[j].dirty;
9552 }
9553 }
9554 j--;
9555 }
9556 }
9557 }
9558 }
9559
9560 // Count cycles in between branches
9561 ccadj[i]=cc;
7139f3c8 9562 if(i>0&&(itype[i-1]==RJUMP||itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP||itype[i]==SYSCALL||itype[i]==HLECALL))
57871462 9563 {
9564 cc=0;
9565 }
fb407447 9566#ifdef PCSX
9567 else if(/*itype[i]==LOAD||*/itype[i]==STORE||itype[i]==C1LS) // load causes weird timing issues
9568 {
9569 cc+=2; // 2 cycle penalty (after CLOCK_DIVIDER)
9570 }
9571 else if(itype[i]==C2LS)
9572 {
9573 cc+=4;
9574 }
9575#endif
57871462 9576 else
9577 {
9578 cc++;
9579 }
9580
9581 flush_dirty_uppers(&current);
9582 if(!is_ds[i]) {
9583 regs[i].is32=current.is32;
9584 regs[i].dirty=current.dirty;
9585 regs[i].isconst=current.isconst;
9586 memcpy(constmap[i],current.constmap,sizeof(current.constmap));
9587 }
9588 for(hr=0;hr<HOST_REGS;hr++) {
9589 if(hr!=EXCLUDE_REG&&regs[i].regmap[hr]>=0) {
9590 if(regmap_pre[i][hr]!=regs[i].regmap[hr]) {
9591 regs[i].wasconst&=~(1<<hr);
9592 }
9593 }
9594 }
9595 if(current.regmap[HOST_BTREG]==BTREG) current.regmap[HOST_BTREG]=-1;
9596 }
9597
9598 /* Pass 4 - Cull unused host registers */
9599
9600 uint64_t nr=0;
9601
9602 for (i=slen-1;i>=0;i--)
9603 {
9604 int hr;
9605 if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
9606 {
9607 if(ba[i]<start || ba[i]>=(start+slen*4))
9608 {
9609 // Branch out of this block, don't need anything
9610 nr=0;
9611 }
9612 else
9613 {
9614 // Internal branch
9615 // Need whatever matches the target
9616 nr=0;
9617 int t=(ba[i]-start)>>2;
9618 for(hr=0;hr<HOST_REGS;hr++)
9619 {
9620 if(regs[i].regmap_entry[hr]>=0) {
9621 if(regs[i].regmap_entry[hr]==regs[t].regmap_entry[hr]) nr|=1<<hr;
9622 }
9623 }
9624 }
9625 // Conditional branch may need registers for following instructions
9626 if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000)
9627 {
9628 if(i<slen-2) {
9629 nr|=needed_reg[i+2];
9630 for(hr=0;hr<HOST_REGS;hr++)
9631 {
9632 if(regmap_pre[i+2][hr]>=0&&get_reg(regs[i+2].regmap_entry,regmap_pre[i+2][hr])<0) nr&=~(1<<hr);
9633 //if((regmap_entry[i+2][hr])>=0) if(!((nr>>hr)&1)) printf("%x-bogus(%d=%d)\n",start+i*4,hr,regmap_entry[i+2][hr]);
9634 }
9635 }
9636 }
9637 // Don't need stuff which is overwritten
f5955059 9638 //if(regs[i].regmap[hr]!=regmap_pre[i][hr]) nr&=~(1<<hr);
9639 //if(regs[i].regmap[hr]<0) nr&=~(1<<hr);
57871462 9640 // Merge in delay slot
9641 for(hr=0;hr<HOST_REGS;hr++)
9642 {
9643 if(!likely[i]) {
9644 // These are overwritten unless the branch is "likely"
9645 // and the delay slot is nullified if not taken
9646 if(rt1[i+1]&&rt1[i+1]==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
9647 if(rt2[i+1]&&rt2[i+1]==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
9648 }
9649 if(us1[i+1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9650 if(us2[i+1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9651 if(rs1[i+1]==regmap_pre[i][hr]) nr|=1<<hr;
9652 if(rs2[i+1]==regmap_pre[i][hr]) nr|=1<<hr;
9653 if(us1[i+1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9654 if(us2[i+1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9655 if(rs1[i+1]==regs[i].regmap_entry[hr]) nr|=1<<hr;
9656 if(rs2[i+1]==regs[i].regmap_entry[hr]) nr|=1<<hr;
9657 if(dep1[i+1]&&!((unneeded_reg_upper[i]>>dep1[i+1])&1)) {
9658 if(dep1[i+1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9659 if(dep2[i+1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9660 }
9661 if(dep2[i+1]&&!((unneeded_reg_upper[i]>>dep2[i+1])&1)) {
9662 if(dep1[i+1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9663 if(dep2[i+1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9664 }
b9b61529 9665 if(itype[i+1]==STORE || itype[i+1]==STORELR || (opcode[i+1]&0x3b)==0x39 || (opcode[i+1]&0x3b)==0x3a) {
57871462 9666 if(regmap_pre[i][hr]==INVCP) nr|=1<<hr;
9667 if(regs[i].regmap_entry[hr]==INVCP) nr|=1<<hr;
9668 }
9669 }
9670 }
1e973cb0 9671 else if(itype[i]==SYSCALL||itype[i]==HLECALL||itype[i]==INTCALL)
57871462 9672 {
9673 // SYSCALL instruction (software interrupt)
9674 nr=0;
9675 }
9676 else if(itype[i]==COP0 && (source[i]&0x3f)==0x18)
9677 {
9678 // ERET instruction (return from interrupt)
9679 nr=0;
9680 }
9681 else // Non-branch
9682 {
9683 if(i<slen-1) {
9684 for(hr=0;hr<HOST_REGS;hr++) {
9685 if(regmap_pre[i+1][hr]>=0&&get_reg(regs[i+1].regmap_entry,regmap_pre[i+1][hr])<0) nr&=~(1<<hr);
9686 if(regs[i].regmap[hr]!=regmap_pre[i+1][hr]) nr&=~(1<<hr);
9687 if(regs[i].regmap[hr]!=regmap_pre[i][hr]) nr&=~(1<<hr);
9688 if(regs[i].regmap[hr]<0) nr&=~(1<<hr);
9689 }
9690 }
9691 }
9692 for(hr=0;hr<HOST_REGS;hr++)
9693 {
9694 // Overwritten registers are not needed
9695 if(rt1[i]&&rt1[i]==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
9696 if(rt2[i]&&rt2[i]==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
9697 if(FTEMP==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
9698 // Source registers are needed
9699 if(us1[i]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9700 if(us2[i]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9701 if(rs1[i]==regmap_pre[i][hr]) nr|=1<<hr;
9702 if(rs2[i]==regmap_pre[i][hr]) nr|=1<<hr;
9703 if(us1[i]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9704 if(us2[i]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9705 if(rs1[i]==regs[i].regmap_entry[hr]) nr|=1<<hr;
9706 if(rs2[i]==regs[i].regmap_entry[hr]) nr|=1<<hr;
9707 if(dep1[i]&&!((unneeded_reg_upper[i]>>dep1[i])&1)) {
9708 if(dep1[i]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9709 if(dep1[i]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9710 }
9711 if(dep2[i]&&!((unneeded_reg_upper[i]>>dep2[i])&1)) {
9712 if(dep2[i]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9713 if(dep2[i]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9714 }
b9b61529 9715 if(itype[i]==STORE || itype[i]==STORELR || (opcode[i]&0x3b)==0x39 || (opcode[i]&0x3b)==0x3a) {
57871462 9716 if(regmap_pre[i][hr]==INVCP) nr|=1<<hr;
9717 if(regs[i].regmap_entry[hr]==INVCP) nr|=1<<hr;
9718 }
9719 // Don't store a register immediately after writing it,
9720 // may prevent dual-issue.
9721 // But do so if this is a branch target, otherwise we
9722 // might have to load the register before the branch.
9723 if(i>0&&!bt[i]&&((regs[i].wasdirty>>hr)&1)) {
9724 if((regmap_pre[i][hr]>0&&regmap_pre[i][hr]<64&&!((unneeded_reg[i]>>regmap_pre[i][hr])&1)) ||
9725 (regmap_pre[i][hr]>64&&!((unneeded_reg_upper[i]>>(regmap_pre[i][hr]&63))&1)) ) {
9726 if(rt1[i-1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9727 if(rt2[i-1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9728 }
9729 if((regs[i].regmap_entry[hr]>0&&regs[i].regmap_entry[hr]<64&&!((unneeded_reg[i]>>regs[i].regmap_entry[hr])&1)) ||
9730 (regs[i].regmap_entry[hr]>64&&!((unneeded_reg_upper[i]>>(regs[i].regmap_entry[hr]&63))&1)) ) {
9731 if(rt1[i-1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9732 if(rt2[i-1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9733 }
9734 }
9735 }
9736 // Cycle count is needed at branches. Assume it is needed at the target too.
9737 if(i==0||bt[i]||itype[i]==CJUMP||itype[i]==FJUMP||itype[i]==SPAN) {
9738 if(regmap_pre[i][HOST_CCREG]==CCREG) nr|=1<<HOST_CCREG;
9739 if(regs[i].regmap_entry[HOST_CCREG]==CCREG) nr|=1<<HOST_CCREG;
9740 }
9741 // Save it
9742 needed_reg[i]=nr;
9743
9744 // Deallocate unneeded registers
9745 for(hr=0;hr<HOST_REGS;hr++)
9746 {
9747 if(!((nr>>hr)&1)) {
9748 if(regs[i].regmap_entry[hr]!=CCREG) regs[i].regmap_entry[hr]=-1;
9749 if((regs[i].regmap[hr]&63)!=rs1[i] && (regs[i].regmap[hr]&63)!=rs2[i] &&
9750 (regs[i].regmap[hr]&63)!=rt1[i] && (regs[i].regmap[hr]&63)!=rt2[i] &&
9751 (regs[i].regmap[hr]&63)!=PTEMP && (regs[i].regmap[hr]&63)!=CCREG)
9752 {
9753 if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000)
9754 {
9755 if(likely[i]) {
9756 regs[i].regmap[hr]=-1;
9757 regs[i].isconst&=~(1<<hr);
79c75f1b 9758 if(i<slen-2) {
9759 regmap_pre[i+2][hr]=-1;
9760 regs[i+2].wasconst&=~(1<<hr);
9761 }
57871462 9762 }
9763 }
9764 }
9765 if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
9766 {
9767 int d1=0,d2=0,map=0,temp=0;
9768 if(get_reg(regs[i].regmap,rt1[i+1]|64)>=0||get_reg(branch_regs[i].regmap,rt1[i+1]|64)>=0)
9769 {
9770 d1=dep1[i+1];
9771 d2=dep2[i+1];
9772 }
9773 if(using_tlb) {
9774 if(itype[i+1]==LOAD || itype[i+1]==LOADLR ||
9775 itype[i+1]==STORE || itype[i+1]==STORELR ||
b9b61529 9776 itype[i+1]==C1LS || itype[i+1]==C2LS)
57871462 9777 map=TLREG;
9778 } else
b9b61529 9779 if(itype[i+1]==STORE || itype[i+1]==STORELR ||
9780 (opcode[i+1]&0x3b)==0x39 || (opcode[i+1]&0x3b)==0x3a) { // SWC1/SDC1 || SWC2/SDC2
57871462 9781 map=INVCP;
9782 }
9783 if(itype[i+1]==LOADLR || itype[i+1]==STORELR ||
b9b61529 9784 itype[i+1]==C1LS || itype[i+1]==C2LS)
57871462 9785 temp=FTEMP;
9786 if((regs[i].regmap[hr]&63)!=rs1[i] && (regs[i].regmap[hr]&63)!=rs2[i] &&
9787 (regs[i].regmap[hr]&63)!=rt1[i] && (regs[i].regmap[hr]&63)!=rt2[i] &&
9788 (regs[i].regmap[hr]&63)!=rt1[i+1] && (regs[i].regmap[hr]&63)!=rt2[i+1] &&
9789 (regs[i].regmap[hr]^64)!=us1[i+1] && (regs[i].regmap[hr]^64)!=us2[i+1] &&
9790 (regs[i].regmap[hr]^64)!=d1 && (regs[i].regmap[hr]^64)!=d2 &&
9791 regs[i].regmap[hr]!=rs1[i+1] && regs[i].regmap[hr]!=rs2[i+1] &&
9792 (regs[i].regmap[hr]&63)!=temp && regs[i].regmap[hr]!=PTEMP &&
9793 regs[i].regmap[hr]!=RHASH && regs[i].regmap[hr]!=RHTBL &&
9794 regs[i].regmap[hr]!=RTEMP && regs[i].regmap[hr]!=CCREG &&
9795 regs[i].regmap[hr]!=map )
9796 {
9797 regs[i].regmap[hr]=-1;
9798 regs[i].isconst&=~(1<<hr);
9799 if((branch_regs[i].regmap[hr]&63)!=rs1[i] && (branch_regs[i].regmap[hr]&63)!=rs2[i] &&
9800 (branch_regs[i].regmap[hr]&63)!=rt1[i] && (branch_regs[i].regmap[hr]&63)!=rt2[i] &&
9801 (branch_regs[i].regmap[hr]&63)!=rt1[i+1] && (branch_regs[i].regmap[hr]&63)!=rt2[i+1] &&
9802 (branch_regs[i].regmap[hr]^64)!=us1[i+1] && (branch_regs[i].regmap[hr]^64)!=us2[i+1] &&
9803 (branch_regs[i].regmap[hr]^64)!=d1 && (branch_regs[i].regmap[hr]^64)!=d2 &&
9804 branch_regs[i].regmap[hr]!=rs1[i+1] && branch_regs[i].regmap[hr]!=rs2[i+1] &&
9805 (branch_regs[i].regmap[hr]&63)!=temp && branch_regs[i].regmap[hr]!=PTEMP &&
9806 branch_regs[i].regmap[hr]!=RHASH && branch_regs[i].regmap[hr]!=RHTBL &&
9807 branch_regs[i].regmap[hr]!=RTEMP && branch_regs[i].regmap[hr]!=CCREG &&
9808 branch_regs[i].regmap[hr]!=map)
9809 {
9810 branch_regs[i].regmap[hr]=-1;
9811 branch_regs[i].regmap_entry[hr]=-1;
9812 if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000)
9813 {
9814 if(!likely[i]&&i<slen-2) {
9815 regmap_pre[i+2][hr]=-1;
79c75f1b 9816 regs[i+2].wasconst&=~(1<<hr);
57871462 9817 }
9818 }
9819 }
9820 }
9821 }
9822 else
9823 {
9824 // Non-branch
9825 if(i>0)
9826 {
9827 int d1=0,d2=0,map=-1,temp=-1;
9828 if(get_reg(regs[i].regmap,rt1[i]|64)>=0)
9829 {
9830 d1=dep1[i];
9831 d2=dep2[i];
9832 }
9833 if(using_tlb) {
9834 if(itype[i]==LOAD || itype[i]==LOADLR ||
9835 itype[i]==STORE || itype[i]==STORELR ||
b9b61529 9836 itype[i]==C1LS || itype[i]==C2LS)
57871462 9837 map=TLREG;
b9b61529 9838 } else if(itype[i]==STORE || itype[i]==STORELR ||
9839 (opcode[i]&0x3b)==0x39 || (opcode[i]&0x3b)==0x3a) { // SWC1/SDC1 || SWC2/SDC2
57871462 9840 map=INVCP;
9841 }
9842 if(itype[i]==LOADLR || itype[i]==STORELR ||
b9b61529 9843 itype[i]==C1LS || itype[i]==C2LS)
57871462 9844 temp=FTEMP;
9845 if((regs[i].regmap[hr]&63)!=rt1[i] && (regs[i].regmap[hr]&63)!=rt2[i] &&
9846 (regs[i].regmap[hr]^64)!=us1[i] && (regs[i].regmap[hr]^64)!=us2[i] &&
9847 (regs[i].regmap[hr]^64)!=d1 && (regs[i].regmap[hr]^64)!=d2 &&
9848 regs[i].regmap[hr]!=rs1[i] && regs[i].regmap[hr]!=rs2[i] &&
9849 (regs[i].regmap[hr]&63)!=temp && regs[i].regmap[hr]!=map &&
9850 (itype[i]!=SPAN||regs[i].regmap[hr]!=CCREG))
9851 {
9852 if(i<slen-1&&!is_ds[i]) {
9853 if(regmap_pre[i+1][hr]!=-1 || regs[i].regmap[hr]!=-1)
9854 if(regmap_pre[i+1][hr]!=regs[i].regmap[hr])
9855 if(regs[i].regmap[hr]<64||!((regs[i].was32>>(regs[i].regmap[hr]&63))&1))
9856 {
9857 printf("fail: %x (%d %d!=%d)\n",start+i*4,hr,regmap_pre[i+1][hr],regs[i].regmap[hr]);
9858 assert(regmap_pre[i+1][hr]==regs[i].regmap[hr]);
9859 }
9860 regmap_pre[i+1][hr]=-1;
9861 if(regs[i+1].regmap_entry[hr]==CCREG) regs[i+1].regmap_entry[hr]=-1;
79c75f1b 9862 regs[i+1].wasconst&=~(1<<hr);
57871462 9863 }
9864 regs[i].regmap[hr]=-1;
9865 regs[i].isconst&=~(1<<hr);
9866 }
9867 }
9868 }
9869 }
9870 }
9871 }
9872
9873 /* Pass 5 - Pre-allocate registers */
9874
9875 // If a register is allocated during a loop, try to allocate it for the
9876 // entire loop, if possible. This avoids loading/storing registers
9877 // inside of the loop.
198df76f 9878
57871462 9879 signed char f_regmap[HOST_REGS];
9880 clear_all_regs(f_regmap);
9881 for(i=0;i<slen-1;i++)
9882 {
9883 if(itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
9884 {
9885 if(ba[i]>=start && ba[i]<(start+i*4))
9886 if(itype[i+1]==NOP||itype[i+1]==MOV||itype[i+1]==ALU
9887 ||itype[i+1]==SHIFTIMM||itype[i+1]==IMM16||itype[i+1]==LOAD
9888 ||itype[i+1]==STORE||itype[i+1]==STORELR||itype[i+1]==C1LS
9889 ||itype[i+1]==SHIFT||itype[i+1]==COP1||itype[i+1]==FLOAT
b9b61529 9890 ||itype[i+1]==FCOMP||itype[i+1]==FCONV
9891 ||itype[i+1]==COP2||itype[i+1]==C2LS||itype[i+1]==C2OP)
57871462 9892 {
9893 int t=(ba[i]-start)>>2;
9894 if(t>0&&(itype[t-1]!=UJUMP&&itype[t-1]!=RJUMP&&itype[t-1]!=CJUMP&&itype[t-1]!=SJUMP&&itype[t-1]!=FJUMP)) // loop_preload can't handle jumps into delay slots
198df76f 9895 if(t<2||(itype[t-2]!=UJUMP&&itype[t-2]!=RJUMP)||rt1[t-2]!=31) // call/ret assumes no registers allocated
57871462 9896 for(hr=0;hr<HOST_REGS;hr++)
9897 {
9898 if(regs[i].regmap[hr]>64) {
9899 if(!((regs[i].dirty>>hr)&1))
9900 f_regmap[hr]=regs[i].regmap[hr];
9901 else f_regmap[hr]=-1;
9902 }
b372a952 9903 else if(regs[i].regmap[hr]>=0) {
9904 if(f_regmap[hr]!=regs[i].regmap[hr]) {
9905 // dealloc old register
9906 int n;
9907 for(n=0;n<HOST_REGS;n++)
9908 {
9909 if(f_regmap[n]==regs[i].regmap[hr]) {f_regmap[n]=-1;}
9910 }
9911 // and alloc new one
9912 f_regmap[hr]=regs[i].regmap[hr];
9913 }
9914 }
57871462 9915 if(branch_regs[i].regmap[hr]>64) {
9916 if(!((branch_regs[i].dirty>>hr)&1))
9917 f_regmap[hr]=branch_regs[i].regmap[hr];
9918 else f_regmap[hr]=-1;
9919 }
b372a952 9920 else if(branch_regs[i].regmap[hr]>=0) {
9921 if(f_regmap[hr]!=branch_regs[i].regmap[hr]) {
9922 // dealloc old register
9923 int n;
9924 for(n=0;n<HOST_REGS;n++)
9925 {
9926 if(f_regmap[n]==branch_regs[i].regmap[hr]) {f_regmap[n]=-1;}
9927 }
9928 // and alloc new one
9929 f_regmap[hr]=branch_regs[i].regmap[hr];
9930 }
9931 }
e1190b87 9932 if(ooo[i]) {
9933 if(count_free_regs(regs[i].regmap)<=minimum_free_regs[i+1])
9934 f_regmap[hr]=branch_regs[i].regmap[hr];
9935 }else{
9936 if(count_free_regs(branch_regs[i].regmap)<=minimum_free_regs[i+1])
57871462 9937 f_regmap[hr]=branch_regs[i].regmap[hr];
9938 }
9939 // Avoid dirty->clean transition
e1190b87 9940 #ifdef DESTRUCTIVE_WRITEBACK
57871462 9941 if(t>0) if(get_reg(regmap_pre[t],f_regmap[hr])>=0) if((regs[t].wasdirty>>get_reg(regmap_pre[t],f_regmap[hr]))&1) f_regmap[hr]=-1;
e1190b87 9942 #endif
9943 // This check is only strictly required in the DESTRUCTIVE_WRITEBACK
9944 // case above, however it's always a good idea. We can't hoist the
9945 // load if the register was already allocated, so there's no point
9946 // wasting time analyzing most of these cases. It only "succeeds"
9947 // when the mapping was different and the load can be replaced with
9948 // a mov, which is of negligible benefit. So such cases are
9949 // skipped below.
57871462 9950 if(f_regmap[hr]>0) {
198df76f 9951 if(regs[t].regmap[hr]==f_regmap[hr]||(regs[t].regmap_entry[hr]<0&&get_reg(regmap_pre[t],f_regmap[hr])<0)) {
57871462 9952 int r=f_regmap[hr];
9953 for(j=t;j<=i;j++)
9954 {
9955 //printf("Test %x -> %x, %x %d/%d\n",start+i*4,ba[i],start+j*4,hr,r);
9956 if(r<34&&((unneeded_reg[j]>>r)&1)) break;
9957 if(r>63&&((unneeded_reg_upper[j]>>(r&63))&1)) break;
9958 if(r>63) {
9959 // NB This can exclude the case where the upper-half
9960 // register is lower numbered than the lower-half
9961 // register. Not sure if it's worth fixing...
9962 if(get_reg(regs[j].regmap,r&63)<0) break;
e1190b87 9963 if(get_reg(regs[j].regmap_entry,r&63)<0) break;
57871462 9964 if(regs[j].is32&(1LL<<(r&63))) break;
9965 }
9966 if(regs[j].regmap[hr]==f_regmap[hr]&&(f_regmap[hr]&63)<TEMPREG) {
9967 //printf("Hit %x -> %x, %x %d/%d\n",start+i*4,ba[i],start+j*4,hr,r);
9968 int k;
9969 if(regs[i].regmap[hr]==-1&&branch_regs[i].regmap[hr]==-1) {
9970 if(get_reg(regs[i+2].regmap,f_regmap[hr])>=0) break;
9971 if(r>63) {
9972 if(get_reg(regs[i].regmap,r&63)<0) break;
9973 if(get_reg(branch_regs[i].regmap,r&63)<0) break;
9974 }
9975 k=i;
9976 while(k>1&&regs[k-1].regmap[hr]==-1) {
e1190b87 9977 if(count_free_regs(regs[k-1].regmap)<=minimum_free_regs[k-1]) {
9978 //printf("no free regs for store %x\n",start+(k-1)*4);
9979 break;
57871462 9980 }
57871462 9981 if(get_reg(regs[k-1].regmap,f_regmap[hr])>=0) {
9982 //printf("no-match due to different register\n");
9983 break;
9984 }
9985 if(itype[k-2]==UJUMP||itype[k-2]==RJUMP||itype[k-2]==CJUMP||itype[k-2]==SJUMP||itype[k-2]==FJUMP) {
9986 //printf("no-match due to branch\n");
9987 break;
9988 }
9989 // call/ret fast path assumes no registers allocated
198df76f 9990 if(k>2&&(itype[k-3]==UJUMP||itype[k-3]==RJUMP)&&rt1[k-3]==31) {
57871462 9991 break;
9992 }
9993 if(r>63) {
9994 // NB This can exclude the case where the upper-half
9995 // register is lower numbered than the lower-half
9996 // register. Not sure if it's worth fixing...
9997 if(get_reg(regs[k-1].regmap,r&63)<0) break;
9998 if(regs[k-1].is32&(1LL<<(r&63))) break;
9999 }
10000 k--;
10001 }
10002 if(i<slen-1) {
10003 if((regs[k].is32&(1LL<<f_regmap[hr]))!=
10004 (regs[i+2].was32&(1LL<<f_regmap[hr]))) {
10005 //printf("bad match after branch\n");
10006 break;
10007 }
10008 }
10009 if(regs[k-1].regmap[hr]==f_regmap[hr]&&regmap_pre[k][hr]==f_regmap[hr]) {
10010 //printf("Extend r%d, %x ->\n",hr,start+k*4);
10011 while(k<i) {
10012 regs[k].regmap_entry[hr]=f_regmap[hr];
10013 regs[k].regmap[hr]=f_regmap[hr];
10014 regmap_pre[k+1][hr]=f_regmap[hr];
10015 regs[k].wasdirty&=~(1<<hr);
10016 regs[k].dirty&=~(1<<hr);
10017 regs[k].wasdirty|=(1<<hr)&regs[k-1].dirty;
10018 regs[k].dirty|=(1<<hr)&regs[k].wasdirty;
10019 regs[k].wasconst&=~(1<<hr);
10020 regs[k].isconst&=~(1<<hr);
10021 k++;
10022 }
10023 }
10024 else {
10025 //printf("Fail Extend r%d, %x ->\n",hr,start+k*4);
10026 break;
10027 }
10028 assert(regs[i-1].regmap[hr]==f_regmap[hr]);
10029 if(regs[i-1].regmap[hr]==f_regmap[hr]&&regmap_pre[i][hr]==f_regmap[hr]) {
10030 //printf("OK fill %x (r%d)\n",start+i*4,hr);
10031 regs[i].regmap_entry[hr]=f_regmap[hr];
10032 regs[i].regmap[hr]=f_regmap[hr];
10033 regs[i].wasdirty&=~(1<<hr);
10034 regs[i].dirty&=~(1<<hr);
10035 regs[i].wasdirty|=(1<<hr)&regs[i-1].dirty;
10036 regs[i].dirty|=(1<<hr)&regs[i-1].dirty;
10037 regs[i].wasconst&=~(1<<hr);
10038 regs[i].isconst&=~(1<<hr);
10039 branch_regs[i].regmap_entry[hr]=f_regmap[hr];
10040 branch_regs[i].wasdirty&=~(1<<hr);
10041 branch_regs[i].wasdirty|=(1<<hr)&regs[i].dirty;
10042 branch_regs[i].regmap[hr]=f_regmap[hr];
10043 branch_regs[i].dirty&=~(1<<hr);
10044 branch_regs[i].dirty|=(1<<hr)&regs[i].dirty;
10045 branch_regs[i].wasconst&=~(1<<hr);
10046 branch_regs[i].isconst&=~(1<<hr);
10047 if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000) {
10048 regmap_pre[i+2][hr]=f_regmap[hr];
10049 regs[i+2].wasdirty&=~(1<<hr);
10050 regs[i+2].wasdirty|=(1<<hr)&regs[i].dirty;
10051 assert((branch_regs[i].is32&(1LL<<f_regmap[hr]))==
10052 (regs[i+2].was32&(1LL<<f_regmap[hr])));
10053 }
10054 }
10055 }
10056 for(k=t;k<j;k++) {
e1190b87 10057 // Alloc register clean at beginning of loop,
10058 // but may dirty it in pass 6
57871462 10059 regs[k].regmap_entry[hr]=f_regmap[hr];
10060 regs[k].regmap[hr]=f_regmap[hr];
57871462 10061 regs[k].dirty&=~(1<<hr);
10062 regs[k].wasconst&=~(1<<hr);
10063 regs[k].isconst&=~(1<<hr);
e1190b87 10064 if(itype[k]==UJUMP||itype[k]==RJUMP||itype[k]==CJUMP||itype[k]==SJUMP||itype[k]==FJUMP) {
10065 branch_regs[k].regmap_entry[hr]=f_regmap[hr];
10066 branch_regs[k].regmap[hr]=f_regmap[hr];
10067 branch_regs[k].dirty&=~(1<<hr);
10068 branch_regs[k].wasconst&=~(1<<hr);
10069 branch_regs[k].isconst&=~(1<<hr);
10070 if(itype[k]!=RJUMP&&itype[k]!=UJUMP&&(source[k]>>16)!=0x1000) {
10071 regmap_pre[k+2][hr]=f_regmap[hr];
10072 regs[k+2].wasdirty&=~(1<<hr);
10073 assert((branch_regs[k].is32&(1LL<<f_regmap[hr]))==
10074 (regs[k+2].was32&(1LL<<f_regmap[hr])));
10075 }
10076 }
10077 else
10078 {
10079 regmap_pre[k+1][hr]=f_regmap[hr];
10080 regs[k+1].wasdirty&=~(1<<hr);
10081 }
57871462 10082 }
10083 if(regs[j].regmap[hr]==f_regmap[hr])
10084 regs[j].regmap_entry[hr]=f_regmap[hr];
10085 break;
10086 }
10087 if(j==i) break;
10088 if(regs[j].regmap[hr]>=0)
10089 break;
10090 if(get_reg(regs[j].regmap,f_regmap[hr])>=0) {
10091 //printf("no-match due to different register\n");
10092 break;
10093 }
10094 if((regs[j+1].is32&(1LL<<f_regmap[hr]))!=(regs[j].is32&(1LL<<f_regmap[hr]))) {
10095 //printf("32/64 mismatch %x %d\n",start+j*4,hr);
10096 break;
10097 }
e1190b87 10098 if(itype[j]==UJUMP||itype[j]==RJUMP||(source[j]>>16)==0x1000)
10099 {
10100 // Stop on unconditional branch
10101 break;
10102 }
10103 if(itype[j]==CJUMP||itype[j]==SJUMP||itype[j]==FJUMP)
10104 {
10105 if(ooo[j]) {
10106 if(count_free_regs(regs[j].regmap)<=minimum_free_regs[j+1])
10107 break;
10108 }else{
10109 if(count_free_regs(branch_regs[j].regmap)<=minimum_free_regs[j+1])
10110 break;
10111 }
10112 if(get_reg(branch_regs[j].regmap,f_regmap[hr])>=0) {
10113 //printf("no-match due to different register (branch)\n");
57871462 10114 break;
10115 }
10116 }
e1190b87 10117 if(count_free_regs(regs[j].regmap)<=minimum_free_regs[j]) {
10118 //printf("No free regs for store %x\n",start+j*4);
10119 break;
10120 }
57871462 10121 if(f_regmap[hr]>=64) {
10122 if(regs[j].is32&(1LL<<(f_regmap[hr]&63))) {
10123 break;
10124 }
10125 else
10126 {
10127 if(get_reg(regs[j].regmap,f_regmap[hr]&63)<0) {
10128 break;
10129 }
10130 }
10131 }
10132 }
10133 }
10134 }
10135 }
10136 }
10137 }else{
198df76f 10138 // Non branch or undetermined branch target
57871462 10139 for(hr=0;hr<HOST_REGS;hr++)
10140 {
10141 if(hr!=EXCLUDE_REG) {
10142 if(regs[i].regmap[hr]>64) {
10143 if(!((regs[i].dirty>>hr)&1))
10144 f_regmap[hr]=regs[i].regmap[hr];
10145 }
b372a952 10146 else if(regs[i].regmap[hr]>=0) {
10147 if(f_regmap[hr]!=regs[i].regmap[hr]) {
10148 // dealloc old register
10149 int n;
10150 for(n=0;n<HOST_REGS;n++)
10151 {
10152 if(f_regmap[n]==regs[i].regmap[hr]) {f_regmap[n]=-1;}
10153 }
10154 // and alloc new one
10155 f_regmap[hr]=regs[i].regmap[hr];
10156 }
10157 }
57871462 10158 }
10159 }
10160 // Try to restore cycle count at branch targets
10161 if(bt[i]) {
10162 for(j=i;j<slen-1;j++) {
10163 if(regs[j].regmap[HOST_CCREG]!=-1) break;
e1190b87 10164 if(count_free_regs(regs[j].regmap)<=minimum_free_regs[j]) {
10165 //printf("no free regs for store %x\n",start+j*4);
10166 break;
57871462 10167 }
57871462 10168 }
10169 if(regs[j].regmap[HOST_CCREG]==CCREG) {
10170 int k=i;
10171 //printf("Extend CC, %x -> %x\n",start+k*4,start+j*4);
10172 while(k<j) {
10173 regs[k].regmap_entry[HOST_CCREG]=CCREG;
10174 regs[k].regmap[HOST_CCREG]=CCREG;
10175 regmap_pre[k+1][HOST_CCREG]=CCREG;
10176 regs[k+1].wasdirty|=1<<HOST_CCREG;
10177 regs[k].dirty|=1<<HOST_CCREG;
10178 regs[k].wasconst&=~(1<<HOST_CCREG);
10179 regs[k].isconst&=~(1<<HOST_CCREG);
10180 k++;
10181 }
10182 regs[j].regmap_entry[HOST_CCREG]=CCREG;
10183 }
10184 // Work backwards from the branch target
10185 if(j>i&&f_regmap[HOST_CCREG]==CCREG)
10186 {
10187 //printf("Extend backwards\n");
10188 int k;
10189 k=i;
10190 while(regs[k-1].regmap[HOST_CCREG]==-1) {
e1190b87 10191 if(count_free_regs(regs[k-1].regmap)<=minimum_free_regs[k-1]) {
10192 //printf("no free regs for store %x\n",start+(k-1)*4);
10193 break;
57871462 10194 }
57871462 10195 k--;
10196 }
10197 if(regs[k-1].regmap[HOST_CCREG]==CCREG) {
10198 //printf("Extend CC, %x ->\n",start+k*4);
10199 while(k<=i) {
10200 regs[k].regmap_entry[HOST_CCREG]=CCREG;
10201 regs[k].regmap[HOST_CCREG]=CCREG;
10202 regmap_pre[k+1][HOST_CCREG]=CCREG;
10203 regs[k+1].wasdirty|=1<<HOST_CCREG;
10204 regs[k].dirty|=1<<HOST_CCREG;
10205 regs[k].wasconst&=~(1<<HOST_CCREG);
10206 regs[k].isconst&=~(1<<HOST_CCREG);
10207 k++;
10208 }
10209 }
10210 else {
10211 //printf("Fail Extend CC, %x ->\n",start+k*4);
10212 }
10213 }
10214 }
10215 if(itype[i]!=STORE&&itype[i]!=STORELR&&itype[i]!=C1LS&&itype[i]!=SHIFT&&
10216 itype[i]!=NOP&&itype[i]!=MOV&&itype[i]!=ALU&&itype[i]!=SHIFTIMM&&
10217 itype[i]!=IMM16&&itype[i]!=LOAD&&itype[i]!=COP1&&itype[i]!=FLOAT&&
e1190b87 10218 itype[i]!=FCONV&&itype[i]!=FCOMP)
57871462 10219 {
10220 memcpy(f_regmap,regs[i].regmap,sizeof(f_regmap));
10221 }
10222 }
10223 }
10224
d61de97e 10225 // Cache memory offset or tlb map pointer if a register is available
10226 #ifndef HOST_IMM_ADDR32
10227 #ifndef RAM_OFFSET
10228 if(using_tlb)
10229 #endif
10230 {
10231 int earliest_available[HOST_REGS];
10232 int loop_start[HOST_REGS];
10233 int score[HOST_REGS];
10234 int end[HOST_REGS];
10235 int reg=using_tlb?MMREG:ROREG;
10236
10237 // Init
10238 for(hr=0;hr<HOST_REGS;hr++) {
10239 score[hr]=0;earliest_available[hr]=0;
10240 loop_start[hr]=MAXBLOCK;
10241 }
10242 for(i=0;i<slen-1;i++)
10243 {
10244 // Can't do anything if no registers are available
10245 if(count_free_regs(regs[i].regmap)<=minimum_free_regs[i]) {
10246 for(hr=0;hr<HOST_REGS;hr++) {
10247 score[hr]=0;earliest_available[hr]=i+1;
10248 loop_start[hr]=MAXBLOCK;
10249 }
10250 }
10251 if(itype[i]==UJUMP||itype[i]==RJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP) {
10252 if(!ooo[i]) {
10253 if(count_free_regs(branch_regs[i].regmap)<=minimum_free_regs[i+1]) {
10254 for(hr=0;hr<HOST_REGS;hr++) {
10255 score[hr]=0;earliest_available[hr]=i+1;
10256 loop_start[hr]=MAXBLOCK;
10257 }
10258 }
198df76f 10259 }else{
10260 if(count_free_regs(regs[i].regmap)<=minimum_free_regs[i+1]) {
10261 for(hr=0;hr<HOST_REGS;hr++) {
10262 score[hr]=0;earliest_available[hr]=i+1;
10263 loop_start[hr]=MAXBLOCK;
10264 }
10265 }
d61de97e 10266 }
10267 }
10268 // Mark unavailable registers
10269 for(hr=0;hr<HOST_REGS;hr++) {
10270 if(regs[i].regmap[hr]>=0) {
10271 score[hr]=0;earliest_available[hr]=i+1;
10272 loop_start[hr]=MAXBLOCK;
10273 }
10274 if(itype[i]==UJUMP||itype[i]==RJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP) {
10275 if(branch_regs[i].regmap[hr]>=0) {
10276 score[hr]=0;earliest_available[hr]=i+2;
10277 loop_start[hr]=MAXBLOCK;
10278 }
10279 }
10280 }
10281 // No register allocations after unconditional jumps
10282 if(itype[i]==UJUMP||itype[i]==RJUMP||(source[i]>>16)==0x1000)
10283 {
10284 for(hr=0;hr<HOST_REGS;hr++) {
10285 score[hr]=0;earliest_available[hr]=i+2;
10286 loop_start[hr]=MAXBLOCK;
10287 }
10288 i++; // Skip delay slot too
10289 //printf("skip delay slot: %x\n",start+i*4);
10290 }
10291 else
10292 // Possible match
10293 if(itype[i]==LOAD||itype[i]==LOADLR||
10294 itype[i]==STORE||itype[i]==STORELR||itype[i]==C1LS) {
10295 for(hr=0;hr<HOST_REGS;hr++) {
10296 if(hr!=EXCLUDE_REG) {
10297 end[hr]=i-1;
10298 for(j=i;j<slen-1;j++) {
10299 if(regs[j].regmap[hr]>=0) break;
10300 if(itype[j]==UJUMP||itype[j]==RJUMP||itype[j]==CJUMP||itype[j]==SJUMP||itype[j]==FJUMP) {
10301 if(branch_regs[j].regmap[hr]>=0) break;
10302 if(ooo[j]) {
10303 if(count_free_regs(regs[j].regmap)<=minimum_free_regs[j+1]) break;
10304 }else{
10305 if(count_free_regs(branch_regs[j].regmap)<=minimum_free_regs[j+1]) break;
10306 }
10307 }
10308 else if(count_free_regs(regs[j].regmap)<=minimum_free_regs[j]) break;
10309 if(itype[j]==UJUMP||itype[j]==RJUMP||itype[j]==CJUMP||itype[j]==SJUMP||itype[j]==FJUMP) {
10310 int t=(ba[j]-start)>>2;
10311 if(t<j&&t>=earliest_available[hr]) {
198df76f 10312 if(t==1||(t>1&&itype[t-2]!=UJUMP&&itype[t-2]!=RJUMP)||(t>1&&rt1[t-2]!=31)) { // call/ret assumes no registers allocated
10313 // Score a point for hoisting loop invariant
10314 if(t<loop_start[hr]) loop_start[hr]=t;
10315 //printf("set loop_start: i=%x j=%x (%x)\n",start+i*4,start+j*4,start+t*4);
10316 score[hr]++;
10317 end[hr]=j;
10318 }
d61de97e 10319 }
10320 else if(t<j) {
10321 if(regs[t].regmap[hr]==reg) {
10322 // Score a point if the branch target matches this register
10323 score[hr]++;
10324 end[hr]=j;
10325 }
10326 }
10327 if(itype[j+1]==LOAD||itype[j+1]==LOADLR||
10328 itype[j+1]==STORE||itype[j+1]==STORELR||itype[j+1]==C1LS) {
10329 score[hr]++;
10330 end[hr]=j;
10331 }
10332 }
10333 if(itype[j]==UJUMP||itype[j]==RJUMP||(source[j]>>16)==0x1000)
10334 {
10335 // Stop on unconditional branch
10336 break;
10337 }
10338 else
10339 if(itype[j]==LOAD||itype[j]==LOADLR||
10340 itype[j]==STORE||itype[j]==STORELR||itype[j]==C1LS) {
10341 score[hr]++;
10342 end[hr]=j;
10343 }
10344 }
10345 }
10346 }
10347 // Find highest score and allocate that register
10348 int maxscore=0;
10349 for(hr=0;hr<HOST_REGS;hr++) {
10350 if(hr!=EXCLUDE_REG) {
10351 if(score[hr]>score[maxscore]) {
10352 maxscore=hr;
10353 //printf("highest score: %d %d (%x->%x)\n",score[hr],hr,start+i*4,start+end[hr]*4);
10354 }
10355 }
10356 }
10357 if(score[maxscore]>1)
10358 {
10359 if(i<loop_start[maxscore]) loop_start[maxscore]=i;
10360 for(j=loop_start[maxscore];j<slen&&j<=end[maxscore];j++) {
10361 //if(regs[j].regmap[maxscore]>=0) {printf("oops: %x %x was %d=%d\n",loop_start[maxscore]*4+start,j*4+start,maxscore,regs[j].regmap[maxscore]);}
10362 assert(regs[j].regmap[maxscore]<0);
10363 if(j>loop_start[maxscore]) regs[j].regmap_entry[maxscore]=reg;
10364 regs[j].regmap[maxscore]=reg;
10365 regs[j].dirty&=~(1<<maxscore);
10366 regs[j].wasconst&=~(1<<maxscore);
10367 regs[j].isconst&=~(1<<maxscore);
10368 if(itype[j]==UJUMP||itype[j]==RJUMP||itype[j]==CJUMP||itype[j]==SJUMP||itype[j]==FJUMP) {
10369 branch_regs[j].regmap[maxscore]=reg;
10370 branch_regs[j].wasdirty&=~(1<<maxscore);
10371 branch_regs[j].dirty&=~(1<<maxscore);
10372 branch_regs[j].wasconst&=~(1<<maxscore);
10373 branch_regs[j].isconst&=~(1<<maxscore);
10374 if(itype[j]!=RJUMP&&itype[j]!=UJUMP&&(source[j]>>16)!=0x1000) {
10375 regmap_pre[j+2][maxscore]=reg;
10376 regs[j+2].wasdirty&=~(1<<maxscore);
10377 }
10378 // loop optimization (loop_preload)
10379 int t=(ba[j]-start)>>2;
198df76f 10380 if(t==loop_start[maxscore]) {
10381 if(t==1||(t>1&&itype[t-2]!=UJUMP&&itype[t-2]!=RJUMP)||(t>1&&rt1[t-2]!=31)) // call/ret assumes no registers allocated
10382 regs[t].regmap_entry[maxscore]=reg;
10383 }
d61de97e 10384 }
10385 else
10386 {
10387 if(j<1||(itype[j-1]!=RJUMP&&itype[j-1]!=UJUMP&&itype[j-1]!=CJUMP&&itype[j-1]!=SJUMP&&itype[j-1]!=FJUMP)) {
10388 regmap_pre[j+1][maxscore]=reg;
10389 regs[j+1].wasdirty&=~(1<<maxscore);
10390 }
10391 }
10392 }
10393 i=j-1;
10394 if(itype[j-1]==RJUMP||itype[j-1]==UJUMP||itype[j-1]==CJUMP||itype[j-1]==SJUMP||itype[j-1]==FJUMP) i++; // skip delay slot
10395 for(hr=0;hr<HOST_REGS;hr++) {
10396 score[hr]=0;earliest_available[hr]=i+i;
10397 loop_start[hr]=MAXBLOCK;
10398 }
10399 }
10400 }
10401 }
10402 }
10403 #endif
10404
57871462 10405 // This allocates registers (if possible) one instruction prior
10406 // to use, which can avoid a load-use penalty on certain CPUs.
10407 for(i=0;i<slen-1;i++)
10408 {
10409 if(!i||(itype[i-1]!=UJUMP&&itype[i-1]!=CJUMP&&itype[i-1]!=SJUMP&&itype[i-1]!=RJUMP&&itype[i-1]!=FJUMP))
10410 {
10411 if(!bt[i+1])
10412 {
b9b61529 10413 if(itype[i]==ALU||itype[i]==MOV||itype[i]==LOAD||itype[i]==SHIFTIMM||itype[i]==IMM16
10414 ||((itype[i]==COP1||itype[i]==COP2)&&opcode2[i]<3))
57871462 10415 {
10416 if(rs1[i+1]) {
10417 if((hr=get_reg(regs[i+1].regmap,rs1[i+1]))>=0)
10418 {
10419 if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
10420 {
10421 regs[i].regmap[hr]=regs[i+1].regmap[hr];
10422 regmap_pre[i+1][hr]=regs[i+1].regmap[hr];
10423 regs[i+1].regmap_entry[hr]=regs[i+1].regmap[hr];
10424 regs[i].isconst&=~(1<<hr);
10425 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10426 constmap[i][hr]=constmap[i+1][hr];
10427 regs[i+1].wasdirty&=~(1<<hr);
10428 regs[i].dirty&=~(1<<hr);
10429 }
10430 }
10431 }
10432 if(rs2[i+1]) {
10433 if((hr=get_reg(regs[i+1].regmap,rs2[i+1]))>=0)
10434 {
10435 if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
10436 {
10437 regs[i].regmap[hr]=regs[i+1].regmap[hr];
10438 regmap_pre[i+1][hr]=regs[i+1].regmap[hr];
10439 regs[i+1].regmap_entry[hr]=regs[i+1].regmap[hr];
10440 regs[i].isconst&=~(1<<hr);
10441 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10442 constmap[i][hr]=constmap[i+1][hr];
10443 regs[i+1].wasdirty&=~(1<<hr);
10444 regs[i].dirty&=~(1<<hr);
10445 }
10446 }
10447 }
198df76f 10448 // Preload target address for load instruction (non-constant)
57871462 10449 if(itype[i+1]==LOAD&&rs1[i+1]&&get_reg(regs[i+1].regmap,rs1[i+1])<0) {
10450 if((hr=get_reg(regs[i+1].regmap,rt1[i+1]))>=0)
10451 {
10452 if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
10453 {
10454 regs[i].regmap[hr]=rs1[i+1];
10455 regmap_pre[i+1][hr]=rs1[i+1];
10456 regs[i+1].regmap_entry[hr]=rs1[i+1];
10457 regs[i].isconst&=~(1<<hr);
10458 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10459 constmap[i][hr]=constmap[i+1][hr];
10460 regs[i+1].wasdirty&=~(1<<hr);
10461 regs[i].dirty&=~(1<<hr);
10462 }
10463 }
10464 }
198df76f 10465 // Load source into target register
57871462 10466 if(lt1[i+1]&&get_reg(regs[i+1].regmap,rs1[i+1])<0) {
10467 if((hr=get_reg(regs[i+1].regmap,rt1[i+1]))>=0)
10468 {
10469 if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
10470 {
10471 regs[i].regmap[hr]=rs1[i+1];
10472 regmap_pre[i+1][hr]=rs1[i+1];
10473 regs[i+1].regmap_entry[hr]=rs1[i+1];
10474 regs[i].isconst&=~(1<<hr);
10475 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10476 constmap[i][hr]=constmap[i+1][hr];
10477 regs[i+1].wasdirty&=~(1<<hr);
10478 regs[i].dirty&=~(1<<hr);
10479 }
10480 }
10481 }
198df76f 10482 // Preload map address
57871462 10483 #ifndef HOST_IMM_ADDR32
b9b61529 10484 if(itype[i+1]==LOAD||itype[i+1]==LOADLR||itype[i+1]==STORE||itype[i+1]==STORELR||itype[i+1]==C1LS||itype[i+1]==C2LS) {
57871462 10485 hr=get_reg(regs[i+1].regmap,TLREG);
10486 if(hr>=0) {
10487 int sr=get_reg(regs[i+1].regmap,rs1[i+1]);
10488 if(sr>=0&&((regs[i+1].wasconst>>sr)&1)) {
10489 int nr;
10490 if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
10491 {
10492 regs[i].regmap[hr]=MGEN1+((i+1)&1);
10493 regmap_pre[i+1][hr]=MGEN1+((i+1)&1);
10494 regs[i+1].regmap_entry[hr]=MGEN1+((i+1)&1);
10495 regs[i].isconst&=~(1<<hr);
10496 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10497 constmap[i][hr]=constmap[i+1][hr];
10498 regs[i+1].wasdirty&=~(1<<hr);
10499 regs[i].dirty&=~(1<<hr);
10500 }
10501 else if((nr=get_reg2(regs[i].regmap,regs[i+1].regmap,-1))>=0)
10502 {
10503 // move it to another register
10504 regs[i+1].regmap[hr]=-1;
10505 regmap_pre[i+2][hr]=-1;
10506 regs[i+1].regmap[nr]=TLREG;
10507 regmap_pre[i+2][nr]=TLREG;
10508 regs[i].regmap[nr]=MGEN1+((i+1)&1);
10509 regmap_pre[i+1][nr]=MGEN1+((i+1)&1);
10510 regs[i+1].regmap_entry[nr]=MGEN1+((i+1)&1);
10511 regs[i].isconst&=~(1<<nr);
10512 regs[i+1].isconst&=~(1<<nr);
10513 regs[i].dirty&=~(1<<nr);
10514 regs[i+1].wasdirty&=~(1<<nr);
10515 regs[i+1].dirty&=~(1<<nr);
10516 regs[i+2].wasdirty&=~(1<<nr);
10517 }
10518 }
10519 }
10520 }
10521 #endif
198df76f 10522 // Address for store instruction (non-constant)
b9b61529 10523 if(itype[i+1]==STORE||itype[i+1]==STORELR
10524 ||(opcode[i+1]&0x3b)==0x39||(opcode[i+1]&0x3b)==0x3a) { // SB/SH/SW/SD/SWC1/SDC1/SWC2/SDC2
57871462 10525 if(get_reg(regs[i+1].regmap,rs1[i+1])<0) {
10526 hr=get_reg2(regs[i].regmap,regs[i+1].regmap,-1);
10527 if(hr<0) hr=get_reg(regs[i+1].regmap,-1);
10528 else {regs[i+1].regmap[hr]=AGEN1+((i+1)&1);regs[i+1].isconst&=~(1<<hr);}
10529 assert(hr>=0);
10530 if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
10531 {
10532 regs[i].regmap[hr]=rs1[i+1];
10533 regmap_pre[i+1][hr]=rs1[i+1];
10534 regs[i+1].regmap_entry[hr]=rs1[i+1];
10535 regs[i].isconst&=~(1<<hr);
10536 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10537 constmap[i][hr]=constmap[i+1][hr];
10538 regs[i+1].wasdirty&=~(1<<hr);
10539 regs[i].dirty&=~(1<<hr);
10540 }
10541 }
10542 }
b9b61529 10543 if(itype[i+1]==LOADLR||(opcode[i+1]&0x3b)==0x31||(opcode[i+1]&0x3b)==0x32) { // LWC1/LDC1, LWC2/LDC2
57871462 10544 if(get_reg(regs[i+1].regmap,rs1[i+1])<0) {
10545 int nr;
10546 hr=get_reg(regs[i+1].regmap,FTEMP);
10547 assert(hr>=0);
10548 if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
10549 {
10550 regs[i].regmap[hr]=rs1[i+1];
10551 regmap_pre[i+1][hr]=rs1[i+1];
10552 regs[i+1].regmap_entry[hr]=rs1[i+1];
10553 regs[i].isconst&=~(1<<hr);
10554 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10555 constmap[i][hr]=constmap[i+1][hr];
10556 regs[i+1].wasdirty&=~(1<<hr);
10557 regs[i].dirty&=~(1<<hr);
10558 }
10559 else if((nr=get_reg2(regs[i].regmap,regs[i+1].regmap,-1))>=0)
10560 {
10561 // move it to another register
10562 regs[i+1].regmap[hr]=-1;
10563 regmap_pre[i+2][hr]=-1;
10564 regs[i+1].regmap[nr]=FTEMP;
10565 regmap_pre[i+2][nr]=FTEMP;
10566 regs[i].regmap[nr]=rs1[i+1];
10567 regmap_pre[i+1][nr]=rs1[i+1];
10568 regs[i+1].regmap_entry[nr]=rs1[i+1];
10569 regs[i].isconst&=~(1<<nr);
10570 regs[i+1].isconst&=~(1<<nr);
10571 regs[i].dirty&=~(1<<nr);
10572 regs[i+1].wasdirty&=~(1<<nr);
10573 regs[i+1].dirty&=~(1<<nr);
10574 regs[i+2].wasdirty&=~(1<<nr);
10575 }
10576 }
10577 }
b9b61529 10578 if(itype[i+1]==LOAD||itype[i+1]==LOADLR||itype[i+1]==STORE||itype[i+1]==STORELR/*||itype[i+1]==C1LS||||itype[i+1]==C2LS*/) {
57871462 10579 if(itype[i+1]==LOAD)
10580 hr=get_reg(regs[i+1].regmap,rt1[i+1]);
b9b61529 10581 if(itype[i+1]==LOADLR||(opcode[i+1]&0x3b)==0x31||(opcode[i+1]&0x3b)==0x32) // LWC1/LDC1, LWC2/LDC2
57871462 10582 hr=get_reg(regs[i+1].regmap,FTEMP);
b9b61529 10583 if(itype[i+1]==STORE||itype[i+1]==STORELR||(opcode[i+1]&0x3b)==0x39||(opcode[i+1]&0x3b)==0x3a) { // SWC1/SDC1/SWC2/SDC2
57871462 10584 hr=get_reg(regs[i+1].regmap,AGEN1+((i+1)&1));
10585 if(hr<0) hr=get_reg(regs[i+1].regmap,-1);
10586 }
10587 if(hr>=0&&regs[i].regmap[hr]<0) {
10588 int rs=get_reg(regs[i+1].regmap,rs1[i+1]);
10589 if(rs>=0&&((regs[i+1].wasconst>>rs)&1)) {
10590 regs[i].regmap[hr]=AGEN1+((i+1)&1);
10591 regmap_pre[i+1][hr]=AGEN1+((i+1)&1);
10592 regs[i+1].regmap_entry[hr]=AGEN1+((i+1)&1);
10593 regs[i].isconst&=~(1<<hr);
10594 regs[i+1].wasdirty&=~(1<<hr);
10595 regs[i].dirty&=~(1<<hr);
10596 }
10597 }
10598 }
10599 }
10600 }
10601 }
10602 }
10603
10604 /* Pass 6 - Optimize clean/dirty state */
10605 clean_registers(0,slen-1,1);
10606
10607 /* Pass 7 - Identify 32-bit registers */
a28c6ce8 10608#ifndef FORCE32
57871462 10609 provisional_r32();
10610
10611 u_int r32=0;
10612
10613 for (i=slen-1;i>=0;i--)
10614 {
10615 int hr;
10616 if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
10617 {
10618 if(ba[i]<start || ba[i]>=(start+slen*4))
10619 {
10620 // Branch out of this block, don't need anything
10621 r32=0;
10622 }
10623 else
10624 {
10625 // Internal branch
10626 // Need whatever matches the target
10627 // (and doesn't get overwritten by the delay slot instruction)
10628 r32=0;
10629 int t=(ba[i]-start)>>2;
10630 if(ba[i]>start+i*4) {
10631 // Forward branch
10632 if(!(requires_32bit[t]&~regs[i].was32))
10633 r32|=requires_32bit[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
10634 }else{
10635 // Backward branch
10636 //if(!(regs[t].was32&~unneeded_reg_upper[t]&~regs[i].was32))
10637 // r32|=regs[t].was32&~unneeded_reg_upper[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
10638 if(!(pr32[t]&~regs[i].was32))
10639 r32|=pr32[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
10640 }
10641 }
10642 // Conditional branch may need registers for following instructions
10643 if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000)
10644 {
10645 if(i<slen-2) {
10646 r32|=requires_32bit[i+2];
10647 r32&=regs[i].was32;
10648 // Mark this address as a branch target since it may be called
10649 // upon return from interrupt
10650 bt[i+2]=1;
10651 }
10652 }
10653 // Merge in delay slot
10654 if(!likely[i]) {
10655 // These are overwritten unless the branch is "likely"
10656 // and the delay slot is nullified if not taken
10657 r32&=~(1LL<<rt1[i+1]);
10658 r32&=~(1LL<<rt2[i+1]);
10659 }
10660 // Assume these are needed (delay slot)
10661 if(us1[i+1]>0)
10662 {
10663 if((regs[i].was32>>us1[i+1])&1) r32|=1LL<<us1[i+1];
10664 }
10665 if(us2[i+1]>0)
10666 {
10667 if((regs[i].was32>>us2[i+1])&1) r32|=1LL<<us2[i+1];
10668 }
10669 if(dep1[i+1]&&!((unneeded_reg_upper[i]>>dep1[i+1])&1))
10670 {
10671 if((regs[i].was32>>dep1[i+1])&1) r32|=1LL<<dep1[i+1];
10672 }
10673 if(dep2[i+1]&&!((unneeded_reg_upper[i]>>dep2[i+1])&1))
10674 {
10675 if((regs[i].was32>>dep2[i+1])&1) r32|=1LL<<dep2[i+1];
10676 }
10677 }
1e973cb0 10678 else if(itype[i]==SYSCALL||itype[i]==HLECALL||itype[i]==INTCALL)
57871462 10679 {
10680 // SYSCALL instruction (software interrupt)
10681 r32=0;
10682 }
10683 else if(itype[i]==COP0 && (source[i]&0x3f)==0x18)
10684 {
10685 // ERET instruction (return from interrupt)
10686 r32=0;
10687 }
10688 // Check 32 bits
10689 r32&=~(1LL<<rt1[i]);
10690 r32&=~(1LL<<rt2[i]);
10691 if(us1[i]>0)
10692 {
10693 if((regs[i].was32>>us1[i])&1) r32|=1LL<<us1[i];
10694 }
10695 if(us2[i]>0)
10696 {
10697 if((regs[i].was32>>us2[i])&1) r32|=1LL<<us2[i];
10698 }
10699 if(dep1[i]&&!((unneeded_reg_upper[i]>>dep1[i])&1))
10700 {
10701 if((regs[i].was32>>dep1[i])&1) r32|=1LL<<dep1[i];
10702 }
10703 if(dep2[i]&&!((unneeded_reg_upper[i]>>dep2[i])&1))
10704 {
10705 if((regs[i].was32>>dep2[i])&1) r32|=1LL<<dep2[i];
10706 }
10707 requires_32bit[i]=r32;
10708
10709 // Dirty registers which are 32-bit, require 32-bit input
10710 // as they will be written as 32-bit values
10711 for(hr=0;hr<HOST_REGS;hr++)
10712 {
10713 if(regs[i].regmap_entry[hr]>0&&regs[i].regmap_entry[hr]<64) {
10714 if((regs[i].was32>>regs[i].regmap_entry[hr])&(regs[i].wasdirty>>hr)&1) {
10715 if(!((unneeded_reg_upper[i]>>regs[i].regmap_entry[hr])&1))
10716 requires_32bit[i]|=1LL<<regs[i].regmap_entry[hr];
10717 }
10718 }
10719 }
10720 //requires_32bit[i]=is32[i]&~unneeded_reg_upper[i]; // DEBUG
10721 }
04fd948a 10722#else
10723 for (i=slen-1;i>=0;i--)
10724 {
10725 if(itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
10726 {
10727 // Conditional branch
10728 if((source[i]>>16)!=0x1000&&i<slen-2) {
10729 // Mark this address as a branch target since it may be called
10730 // upon return from interrupt
10731 bt[i+2]=1;
10732 }
10733 }
10734 }
a28c6ce8 10735#endif
57871462 10736
10737 if(itype[slen-1]==SPAN) {
10738 bt[slen-1]=1; // Mark as a branch target so instruction can restart after exception
10739 }
10740
10741 /* Debug/disassembly */
10742 if((void*)assem_debug==(void*)printf)
10743 for(i=0;i<slen;i++)
10744 {
10745 printf("U:");
10746 int r;
10747 for(r=1;r<=CCREG;r++) {
10748 if((unneeded_reg[i]>>r)&1) {
10749 if(r==HIREG) printf(" HI");
10750 else if(r==LOREG) printf(" LO");
10751 else printf(" r%d",r);
10752 }
10753 }
90ae6d4e 10754#ifndef FORCE32
57871462 10755 printf(" UU:");
10756 for(r=1;r<=CCREG;r++) {
10757 if(((unneeded_reg_upper[i]&~unneeded_reg[i])>>r)&1) {
10758 if(r==HIREG) printf(" HI");
10759 else if(r==LOREG) printf(" LO");
10760 else printf(" r%d",r);
10761 }
10762 }
10763 printf(" 32:");
10764 for(r=0;r<=CCREG;r++) {
10765 //if(((is32[i]>>r)&(~unneeded_reg[i]>>r))&1) {
10766 if((regs[i].was32>>r)&1) {
10767 if(r==CCREG) printf(" CC");
10768 else if(r==HIREG) printf(" HI");
10769 else if(r==LOREG) printf(" LO");
10770 else printf(" r%d",r);
10771 }
10772 }
90ae6d4e 10773#endif
57871462 10774 printf("\n");
10775 #if defined(__i386__) || defined(__x86_64__)
10776 printf("pre: eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",regmap_pre[i][0],regmap_pre[i][1],regmap_pre[i][2],regmap_pre[i][3],regmap_pre[i][5],regmap_pre[i][6],regmap_pre[i][7]);
10777 #endif
10778 #ifdef __arm__
10779 printf("pre: r0=%d r1=%d r2=%d r3=%d r4=%d r5=%d r6=%d r7=%d r8=%d r9=%d r10=%d r12=%d\n",regmap_pre[i][0],regmap_pre[i][1],regmap_pre[i][2],regmap_pre[i][3],regmap_pre[i][4],regmap_pre[i][5],regmap_pre[i][6],regmap_pre[i][7],regmap_pre[i][8],regmap_pre[i][9],regmap_pre[i][10],regmap_pre[i][12]);
10780 #endif
10781 printf("needs: ");
10782 if(needed_reg[i]&1) printf("eax ");
10783 if((needed_reg[i]>>1)&1) printf("ecx ");
10784 if((needed_reg[i]>>2)&1) printf("edx ");
10785 if((needed_reg[i]>>3)&1) printf("ebx ");
10786 if((needed_reg[i]>>5)&1) printf("ebp ");
10787 if((needed_reg[i]>>6)&1) printf("esi ");
10788 if((needed_reg[i]>>7)&1) printf("edi ");
10789 printf("r:");
10790 for(r=0;r<=CCREG;r++) {
10791 //if(((requires_32bit[i]>>r)&(~unneeded_reg[i]>>r))&1) {
10792 if((requires_32bit[i]>>r)&1) {
10793 if(r==CCREG) printf(" CC");
10794 else if(r==HIREG) printf(" HI");
10795 else if(r==LOREG) printf(" LO");
10796 else printf(" r%d",r);
10797 }
10798 }
10799 printf("\n");
10800 /*printf("pr:");
10801 for(r=0;r<=CCREG;r++) {
10802 //if(((requires_32bit[i]>>r)&(~unneeded_reg[i]>>r))&1) {
10803 if((pr32[i]>>r)&1) {
10804 if(r==CCREG) printf(" CC");
10805 else if(r==HIREG) printf(" HI");
10806 else if(r==LOREG) printf(" LO");
10807 else printf(" r%d",r);
10808 }
10809 }
10810 if(pr32[i]!=requires_32bit[i]) printf(" OOPS");
10811 printf("\n");*/
10812 #if defined(__i386__) || defined(__x86_64__)
10813 printf("entry: eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",regs[i].regmap_entry[0],regs[i].regmap_entry[1],regs[i].regmap_entry[2],regs[i].regmap_entry[3],regs[i].regmap_entry[5],regs[i].regmap_entry[6],regs[i].regmap_entry[7]);
10814 printf("dirty: ");
10815 if(regs[i].wasdirty&1) printf("eax ");
10816 if((regs[i].wasdirty>>1)&1) printf("ecx ");
10817 if((regs[i].wasdirty>>2)&1) printf("edx ");
10818 if((regs[i].wasdirty>>3)&1) printf("ebx ");
10819 if((regs[i].wasdirty>>5)&1) printf("ebp ");
10820 if((regs[i].wasdirty>>6)&1) printf("esi ");
10821 if((regs[i].wasdirty>>7)&1) printf("edi ");
10822 #endif
10823 #ifdef __arm__
10824 printf("entry: r0=%d r1=%d r2=%d r3=%d r4=%d r5=%d r6=%d r7=%d r8=%d r9=%d r10=%d r12=%d\n",regs[i].regmap_entry[0],regs[i].regmap_entry[1],regs[i].regmap_entry[2],regs[i].regmap_entry[3],regs[i].regmap_entry[4],regs[i].regmap_entry[5],regs[i].regmap_entry[6],regs[i].regmap_entry[7],regs[i].regmap_entry[8],regs[i].regmap_entry[9],regs[i].regmap_entry[10],regs[i].regmap_entry[12]);
10825 printf("dirty: ");
10826 if(regs[i].wasdirty&1) printf("r0 ");
10827 if((regs[i].wasdirty>>1)&1) printf("r1 ");
10828 if((regs[i].wasdirty>>2)&1) printf("r2 ");
10829 if((regs[i].wasdirty>>3)&1) printf("r3 ");
10830 if((regs[i].wasdirty>>4)&1) printf("r4 ");
10831 if((regs[i].wasdirty>>5)&1) printf("r5 ");
10832 if((regs[i].wasdirty>>6)&1) printf("r6 ");
10833 if((regs[i].wasdirty>>7)&1) printf("r7 ");
10834 if((regs[i].wasdirty>>8)&1) printf("r8 ");
10835 if((regs[i].wasdirty>>9)&1) printf("r9 ");
10836 if((regs[i].wasdirty>>10)&1) printf("r10 ");
10837 if((regs[i].wasdirty>>12)&1) printf("r12 ");
10838 #endif
10839 printf("\n");
10840 disassemble_inst(i);
10841 //printf ("ccadj[%d] = %d\n",i,ccadj[i]);
10842 #if defined(__i386__) || defined(__x86_64__)
10843 printf("eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d dirty: ",regs[i].regmap[0],regs[i].regmap[1],regs[i].regmap[2],regs[i].regmap[3],regs[i].regmap[5],regs[i].regmap[6],regs[i].regmap[7]);
10844 if(regs[i].dirty&1) printf("eax ");
10845 if((regs[i].dirty>>1)&1) printf("ecx ");
10846 if((regs[i].dirty>>2)&1) printf("edx ");
10847 if((regs[i].dirty>>3)&1) printf("ebx ");
10848 if((regs[i].dirty>>5)&1) printf("ebp ");
10849 if((regs[i].dirty>>6)&1) printf("esi ");
10850 if((regs[i].dirty>>7)&1) printf("edi ");
10851 #endif
10852 #ifdef __arm__
10853 printf("r0=%d r1=%d r2=%d r3=%d r4=%d r5=%d r6=%d r7=%d r8=%d r9=%d r10=%d r12=%d dirty: ",regs[i].regmap[0],regs[i].regmap[1],regs[i].regmap[2],regs[i].regmap[3],regs[i].regmap[4],regs[i].regmap[5],regs[i].regmap[6],regs[i].regmap[7],regs[i].regmap[8],regs[i].regmap[9],regs[i].regmap[10],regs[i].regmap[12]);
10854 if(regs[i].dirty&1) printf("r0 ");
10855 if((regs[i].dirty>>1)&1) printf("r1 ");
10856 if((regs[i].dirty>>2)&1) printf("r2 ");
10857 if((regs[i].dirty>>3)&1) printf("r3 ");
10858 if((regs[i].dirty>>4)&1) printf("r4 ");
10859 if((regs[i].dirty>>5)&1) printf("r5 ");
10860 if((regs[i].dirty>>6)&1) printf("r6 ");
10861 if((regs[i].dirty>>7)&1) printf("r7 ");
10862 if((regs[i].dirty>>8)&1) printf("r8 ");
10863 if((regs[i].dirty>>9)&1) printf("r9 ");
10864 if((regs[i].dirty>>10)&1) printf("r10 ");
10865 if((regs[i].dirty>>12)&1) printf("r12 ");
10866 #endif
10867 printf("\n");
10868 if(regs[i].isconst) {
10869 printf("constants: ");
10870 #if defined(__i386__) || defined(__x86_64__)
10871 if(regs[i].isconst&1) printf("eax=%x ",(int)constmap[i][0]);
10872 if((regs[i].isconst>>1)&1) printf("ecx=%x ",(int)constmap[i][1]);
10873 if((regs[i].isconst>>2)&1) printf("edx=%x ",(int)constmap[i][2]);
10874 if((regs[i].isconst>>3)&1) printf("ebx=%x ",(int)constmap[i][3]);
10875 if((regs[i].isconst>>5)&1) printf("ebp=%x ",(int)constmap[i][5]);
10876 if((regs[i].isconst>>6)&1) printf("esi=%x ",(int)constmap[i][6]);
10877 if((regs[i].isconst>>7)&1) printf("edi=%x ",(int)constmap[i][7]);
10878 #endif
10879 #ifdef __arm__
10880 if(regs[i].isconst&1) printf("r0=%x ",(int)constmap[i][0]);
10881 if((regs[i].isconst>>1)&1) printf("r1=%x ",(int)constmap[i][1]);
10882 if((regs[i].isconst>>2)&1) printf("r2=%x ",(int)constmap[i][2]);
10883 if((regs[i].isconst>>3)&1) printf("r3=%x ",(int)constmap[i][3]);
10884 if((regs[i].isconst>>4)&1) printf("r4=%x ",(int)constmap[i][4]);
10885 if((regs[i].isconst>>5)&1) printf("r5=%x ",(int)constmap[i][5]);
10886 if((regs[i].isconst>>6)&1) printf("r6=%x ",(int)constmap[i][6]);
10887 if((regs[i].isconst>>7)&1) printf("r7=%x ",(int)constmap[i][7]);
10888 if((regs[i].isconst>>8)&1) printf("r8=%x ",(int)constmap[i][8]);
10889 if((regs[i].isconst>>9)&1) printf("r9=%x ",(int)constmap[i][9]);
10890 if((regs[i].isconst>>10)&1) printf("r10=%x ",(int)constmap[i][10]);
10891 if((regs[i].isconst>>12)&1) printf("r12=%x ",(int)constmap[i][12]);
10892 #endif
10893 printf("\n");
10894 }
90ae6d4e 10895#ifndef FORCE32
57871462 10896 printf(" 32:");
10897 for(r=0;r<=CCREG;r++) {
10898 if((regs[i].is32>>r)&1) {
10899 if(r==CCREG) printf(" CC");
10900 else if(r==HIREG) printf(" HI");
10901 else if(r==LOREG) printf(" LO");
10902 else printf(" r%d",r);
10903 }
10904 }
10905 printf("\n");
90ae6d4e 10906#endif
57871462 10907 /*printf(" p32:");
10908 for(r=0;r<=CCREG;r++) {
10909 if((p32[i]>>r)&1) {
10910 if(r==CCREG) printf(" CC");
10911 else if(r==HIREG) printf(" HI");
10912 else if(r==LOREG) printf(" LO");
10913 else printf(" r%d",r);
10914 }
10915 }
10916 if(p32[i]!=regs[i].is32) printf(" NO MATCH\n");
10917 else printf("\n");*/
10918 if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP) {
10919 #if defined(__i386__) || defined(__x86_64__)
10920 printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d dirty: ",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
10921 if(branch_regs[i].dirty&1) printf("eax ");
10922 if((branch_regs[i].dirty>>1)&1) printf("ecx ");
10923 if((branch_regs[i].dirty>>2)&1) printf("edx ");
10924 if((branch_regs[i].dirty>>3)&1) printf("ebx ");
10925 if((branch_regs[i].dirty>>5)&1) printf("ebp ");
10926 if((branch_regs[i].dirty>>6)&1) printf("esi ");
10927 if((branch_regs[i].dirty>>7)&1) printf("edi ");
10928 #endif
10929 #ifdef __arm__
10930 printf("branch(%d): r0=%d r1=%d r2=%d r3=%d r4=%d r5=%d r6=%d r7=%d r8=%d r9=%d r10=%d r12=%d dirty: ",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[4],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7],branch_regs[i].regmap[8],branch_regs[i].regmap[9],branch_regs[i].regmap[10],branch_regs[i].regmap[12]);
10931 if(branch_regs[i].dirty&1) printf("r0 ");
10932 if((branch_regs[i].dirty>>1)&1) printf("r1 ");
10933 if((branch_regs[i].dirty>>2)&1) printf("r2 ");
10934 if((branch_regs[i].dirty>>3)&1) printf("r3 ");
10935 if((branch_regs[i].dirty>>4)&1) printf("r4 ");
10936 if((branch_regs[i].dirty>>5)&1) printf("r5 ");
10937 if((branch_regs[i].dirty>>6)&1) printf("r6 ");
10938 if((branch_regs[i].dirty>>7)&1) printf("r7 ");
10939 if((branch_regs[i].dirty>>8)&1) printf("r8 ");
10940 if((branch_regs[i].dirty>>9)&1) printf("r9 ");
10941 if((branch_regs[i].dirty>>10)&1) printf("r10 ");
10942 if((branch_regs[i].dirty>>12)&1) printf("r12 ");
10943 #endif
90ae6d4e 10944#ifndef FORCE32
57871462 10945 printf(" 32:");
10946 for(r=0;r<=CCREG;r++) {
10947 if((branch_regs[i].is32>>r)&1) {
10948 if(r==CCREG) printf(" CC");
10949 else if(r==HIREG) printf(" HI");
10950 else if(r==LOREG) printf(" LO");
10951 else printf(" r%d",r);
10952 }
10953 }
10954 printf("\n");
90ae6d4e 10955#endif
57871462 10956 }
10957 }
10958
10959 /* Pass 8 - Assembly */
10960 linkcount=0;stubcount=0;
10961 ds=0;is_delayslot=0;
10962 cop1_usable=0;
10963 uint64_t is32_pre=0;
10964 u_int dirty_pre=0;
10965 u_int beginning=(u_int)out;
10966 if((u_int)addr&1) {
10967 ds=1;
10968 pagespan_ds();
10969 }
9ad4d757 10970 u_int instr_addr0_override=0;
10971
10972#ifdef PCSX
10973 if (start == 0x80030000) {
10974 // nasty hack for fastbios thing
96186eba 10975 // override block entry to this code
9ad4d757 10976 instr_addr0_override=(u_int)out;
10977 emit_movimm(start,0);
96186eba 10978 // abuse io address var as a flag that we
10979 // have already returned here once
10980 emit_readword((int)&address,1);
9ad4d757 10981 emit_writeword(0,(int)&pcaddr);
96186eba 10982 emit_writeword(0,(int)&address);
9ad4d757 10983 emit_cmp(0,1);
10984 emit_jne((int)new_dyna_leave);
10985 }
10986#endif
57871462 10987 for(i=0;i<slen;i++)
10988 {
10989 //if(ds) printf("ds: ");
10990 if((void*)assem_debug==(void*)printf) disassemble_inst(i);
10991 if(ds) {
10992 ds=0; // Skip delay slot
10993 if(bt[i]) assem_debug("OOPS - branch into delay slot\n");
10994 instr_addr[i]=0;
10995 } else {
10996 #ifndef DESTRUCTIVE_WRITEBACK
10997 if(i<2||(itype[i-2]!=UJUMP&&itype[i-2]!=RJUMP&&(source[i-2]>>16)!=0x1000))
10998 {
10999 wb_sx(regmap_pre[i],regs[i].regmap_entry,regs[i].wasdirty,is32_pre,regs[i].was32,
11000 unneeded_reg[i],unneeded_reg_upper[i]);
11001 wb_valid(regmap_pre[i],regs[i].regmap_entry,dirty_pre,regs[i].wasdirty,is32_pre,
11002 unneeded_reg[i],unneeded_reg_upper[i]);
11003 }
f776eb14 11004 if((itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)&&!likely[i]) {
11005 is32_pre=branch_regs[i].is32;
11006 dirty_pre=branch_regs[i].dirty;
11007 }else{
11008 is32_pre=regs[i].is32;
11009 dirty_pre=regs[i].dirty;
11010 }
57871462 11011 #endif
11012 // write back
11013 if(i<2||(itype[i-2]!=UJUMP&&itype[i-2]!=RJUMP&&(source[i-2]>>16)!=0x1000))
11014 {
11015 wb_invalidate(regmap_pre[i],regs[i].regmap_entry,regs[i].wasdirty,regs[i].was32,
11016 unneeded_reg[i],unneeded_reg_upper[i]);
11017 loop_preload(regmap_pre[i],regs[i].regmap_entry);
11018 }
11019 // branch target entry point
11020 instr_addr[i]=(u_int)out;
11021 assem_debug("<->\n");
11022 // load regs
11023 if(regs[i].regmap_entry[HOST_CCREG]==CCREG&&regs[i].regmap[HOST_CCREG]!=CCREG)
11024 wb_register(CCREG,regs[i].regmap_entry,regs[i].wasdirty,regs[i].was32);
11025 load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,rs1[i],rs2[i]);
11026 address_generation(i,&regs[i],regs[i].regmap_entry);
11027 load_consts(regmap_pre[i],regs[i].regmap,regs[i].was32,i);
11028 if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
11029 {
11030 // Load the delay slot registers if necessary
4ef8f67d 11031 if(rs1[i+1]!=rs1[i]&&rs1[i+1]!=rs2[i]&&(rs1[i+1]!=rt1[i]||rt1[i]==0))
57871462 11032 load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,rs1[i+1],rs1[i+1]);
4ef8f67d 11033 if(rs2[i+1]!=rs1[i+1]&&rs2[i+1]!=rs1[i]&&rs2[i+1]!=rs2[i]&&(rs2[i+1]!=rt1[i]||rt1[i]==0))
57871462 11034 load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,rs2[i+1],rs2[i+1]);
b9b61529 11035 if(itype[i+1]==STORE||itype[i+1]==STORELR||(opcode[i+1]&0x3b)==0x39||(opcode[i+1]&0x3b)==0x3a)
57871462 11036 load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,INVCP,INVCP);
11037 }
11038 else if(i+1<slen)
11039 {
11040 // Preload registers for following instruction
11041 if(rs1[i+1]!=rs1[i]&&rs1[i+1]!=rs2[i])
11042 if(rs1[i+1]!=rt1[i]&&rs1[i+1]!=rt2[i])
11043 load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,rs1[i+1],rs1[i+1]);
11044 if(rs2[i+1]!=rs1[i+1]&&rs2[i+1]!=rs1[i]&&rs2[i+1]!=rs2[i])
11045 if(rs2[i+1]!=rt1[i]&&rs2[i+1]!=rt2[i])
11046 load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,rs2[i+1],rs2[i+1]);
11047 }
11048 // TODO: if(is_ooo(i)) address_generation(i+1);
11049 if(itype[i]==CJUMP||itype[i]==FJUMP)
11050 load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,CCREG,CCREG);
b9b61529 11051 if(itype[i]==STORE||itype[i]==STORELR||(opcode[i]&0x3b)==0x39||(opcode[i]&0x3b)==0x3a)
57871462 11052 load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,INVCP,INVCP);
11053 if(bt[i]) cop1_usable=0;
11054 // assemble
11055 switch(itype[i]) {
11056 case ALU:
11057 alu_assemble(i,&regs[i]);break;
11058 case IMM16:
11059 imm16_assemble(i,&regs[i]);break;
11060 case SHIFT:
11061 shift_assemble(i,&regs[i]);break;
11062 case SHIFTIMM:
11063 shiftimm_assemble(i,&regs[i]);break;
11064 case LOAD:
11065 load_assemble(i,&regs[i]);break;
11066 case LOADLR:
11067 loadlr_assemble(i,&regs[i]);break;
11068 case STORE:
11069 store_assemble(i,&regs[i]);break;
11070 case STORELR:
11071 storelr_assemble(i,&regs[i]);break;
11072 case COP0:
11073 cop0_assemble(i,&regs[i]);break;
11074 case COP1:
11075 cop1_assemble(i,&regs[i]);break;
11076 case C1LS:
11077 c1ls_assemble(i,&regs[i]);break;
b9b61529 11078 case COP2:
11079 cop2_assemble(i,&regs[i]);break;
11080 case C2LS:
11081 c2ls_assemble(i,&regs[i]);break;
11082 case C2OP:
11083 c2op_assemble(i,&regs[i]);break;
57871462 11084 case FCONV:
11085 fconv_assemble(i,&regs[i]);break;
11086 case FLOAT:
11087 float_assemble(i,&regs[i]);break;
11088 case FCOMP:
11089 fcomp_assemble(i,&regs[i]);break;
11090 case MULTDIV:
11091 multdiv_assemble(i,&regs[i]);break;
11092 case MOV:
11093 mov_assemble(i,&regs[i]);break;
11094 case SYSCALL:
11095 syscall_assemble(i,&regs[i]);break;
7139f3c8 11096 case HLECALL:
11097 hlecall_assemble(i,&regs[i]);break;
1e973cb0 11098 case INTCALL:
11099 intcall_assemble(i,&regs[i]);break;
57871462 11100 case UJUMP:
11101 ujump_assemble(i,&regs[i]);ds=1;break;
11102 case RJUMP:
11103 rjump_assemble(i,&regs[i]);ds=1;break;
11104 case CJUMP:
11105 cjump_assemble(i,&regs[i]);ds=1;break;
11106 case SJUMP:
11107 sjump_assemble(i,&regs[i]);ds=1;break;
11108 case FJUMP:
11109 fjump_assemble(i,&regs[i]);ds=1;break;
11110 case SPAN:
11111 pagespan_assemble(i,&regs[i]);break;
11112 }
11113 if(itype[i]==UJUMP||itype[i]==RJUMP||(source[i]>>16)==0x1000)
11114 literal_pool(1024);
11115 else
11116 literal_pool_jumpover(256);
11117 }
11118 }
11119 //assert(itype[i-2]==UJUMP||itype[i-2]==RJUMP||(source[i-2]>>16)==0x1000);
11120 // If the block did not end with an unconditional branch,
11121 // add a jump to the next instruction.
11122 if(i>1) {
11123 if(itype[i-2]!=UJUMP&&itype[i-2]!=RJUMP&&(source[i-2]>>16)!=0x1000&&itype[i-1]!=SPAN) {
11124 assert(itype[i-1]!=UJUMP&&itype[i-1]!=CJUMP&&itype[i-1]!=SJUMP&&itype[i-1]!=RJUMP&&itype[i-1]!=FJUMP);
11125 assert(i==slen);
11126 if(itype[i-2]!=CJUMP&&itype[i-2]!=SJUMP&&itype[i-2]!=FJUMP) {
11127 store_regs_bt(regs[i-1].regmap,regs[i-1].is32,regs[i-1].dirty,start+i*4);
11128 if(regs[i-1].regmap[HOST_CCREG]!=CCREG)
11129 emit_loadreg(CCREG,HOST_CCREG);
11130 emit_addimm(HOST_CCREG,CLOCK_DIVIDER*(ccadj[i-1]+1),HOST_CCREG);
11131 }
11132 else if(!likely[i-2])
11133 {
11134 store_regs_bt(branch_regs[i-2].regmap,branch_regs[i-2].is32,branch_regs[i-2].dirty,start+i*4);
11135 assert(branch_regs[i-2].regmap[HOST_CCREG]==CCREG);
11136 }
11137 else
11138 {
11139 store_regs_bt(regs[i-2].regmap,regs[i-2].is32,regs[i-2].dirty,start+i*4);
11140 assert(regs[i-2].regmap[HOST_CCREG]==CCREG);
11141 }
11142 add_to_linker((int)out,start+i*4,0);
11143 emit_jmp(0);
11144 }
11145 }
11146 else
11147 {
11148 assert(i>0);
11149 assert(itype[i-1]!=UJUMP&&itype[i-1]!=CJUMP&&itype[i-1]!=SJUMP&&itype[i-1]!=RJUMP&&itype[i-1]!=FJUMP);
11150 store_regs_bt(regs[i-1].regmap,regs[i-1].is32,regs[i-1].dirty,start+i*4);
11151 if(regs[i-1].regmap[HOST_CCREG]!=CCREG)
11152 emit_loadreg(CCREG,HOST_CCREG);
11153 emit_addimm(HOST_CCREG,CLOCK_DIVIDER*(ccadj[i-1]+1),HOST_CCREG);
11154 add_to_linker((int)out,start+i*4,0);
11155 emit_jmp(0);
11156 }
11157
11158 // TODO: delay slot stubs?
11159 // Stubs
11160 for(i=0;i<stubcount;i++)
11161 {
11162 switch(stubs[i][0])
11163 {
11164 case LOADB_STUB:
11165 case LOADH_STUB:
11166 case LOADW_STUB:
11167 case LOADD_STUB:
11168 case LOADBU_STUB:
11169 case LOADHU_STUB:
11170 do_readstub(i);break;
11171 case STOREB_STUB:
11172 case STOREH_STUB:
11173 case STOREW_STUB:
11174 case STORED_STUB:
11175 do_writestub(i);break;
11176 case CC_STUB:
11177 do_ccstub(i);break;
11178 case INVCODE_STUB:
11179 do_invstub(i);break;
11180 case FP_STUB:
11181 do_cop1stub(i);break;
11182 case STORELR_STUB:
11183 do_unalignedwritestub(i);break;
11184 }
11185 }
11186
9ad4d757 11187 if (instr_addr0_override)
11188 instr_addr[0] = instr_addr0_override;
11189
57871462 11190 /* Pass 9 - Linker */
11191 for(i=0;i<linkcount;i++)
11192 {
11193 assem_debug("%8x -> %8x\n",link_addr[i][0],link_addr[i][1]);
11194 literal_pool(64);
11195 if(!link_addr[i][2])
11196 {
11197 void *stub=out;
11198 void *addr=check_addr(link_addr[i][1]);
11199 emit_extjump(link_addr[i][0],link_addr[i][1]);
11200 if(addr) {
11201 set_jump_target(link_addr[i][0],(int)addr);
11202 add_link(link_addr[i][1],stub);
11203 }
11204 else set_jump_target(link_addr[i][0],(int)stub);
11205 }
11206 else
11207 {
11208 // Internal branch
11209 int target=(link_addr[i][1]-start)>>2;
11210 assert(target>=0&&target<slen);
11211 assert(instr_addr[target]);
11212 //#ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
11213 //set_jump_target_fillslot(link_addr[i][0],instr_addr[target],link_addr[i][2]>>1);
11214 //#else
11215 set_jump_target(link_addr[i][0],instr_addr[target]);
11216 //#endif
11217 }
11218 }
11219 // External Branch Targets (jump_in)
11220 if(copy+slen*4>(void *)shadow+sizeof(shadow)) copy=shadow;
11221 for(i=0;i<slen;i++)
11222 {
11223 if(bt[i]||i==0)
11224 {
11225 if(instr_addr[i]) // TODO - delay slots (=null)
11226 {
11227 u_int vaddr=start+i*4;
94d23bb9 11228 u_int page=get_page(vaddr);
11229 u_int vpage=get_vpage(vaddr);
57871462 11230 literal_pool(256);
11231 //if(!(is32[i]&(~unneeded_reg_upper[i])&~(1LL<<CCREG)))
a28c6ce8 11232#ifndef FORCE32
57871462 11233 if(!requires_32bit[i])
a28c6ce8 11234#else
11235 if(1)
11236#endif
57871462 11237 {
11238 assem_debug("%8x (%d) <- %8x\n",instr_addr[i],i,start+i*4);
11239 assem_debug("jump_in: %x\n",start+i*4);
11240 ll_add(jump_dirty+vpage,vaddr,(void *)out);
11241 int entry_point=do_dirty_stub(i);
11242 ll_add(jump_in+page,vaddr,(void *)entry_point);
11243 // If there was an existing entry in the hash table,
11244 // replace it with the new address.
11245 // Don't add new entries. We'll insert the
11246 // ones that actually get used in check_addr().
11247 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
11248 if(ht_bin[0]==vaddr) {
11249 ht_bin[1]=entry_point;
11250 }
11251 if(ht_bin[2]==vaddr) {
11252 ht_bin[3]=entry_point;
11253 }
11254 }
11255 else
11256 {
11257 u_int r=requires_32bit[i]|!!(requires_32bit[i]>>32);
11258 assem_debug("%8x (%d) <- %8x\n",instr_addr[i],i,start+i*4);
11259 assem_debug("jump_in: %x (restricted - %x)\n",start+i*4,r);
11260 //int entry_point=(int)out;
11261 ////assem_debug("entry_point: %x\n",entry_point);
11262 //load_regs_entry(i);
11263 //if(entry_point==(int)out)
11264 // entry_point=instr_addr[i];
11265 //else
11266 // emit_jmp(instr_addr[i]);
11267 //ll_add_32(jump_in+page,vaddr,r,(void *)entry_point);
11268 ll_add_32(jump_dirty+vpage,vaddr,r,(void *)out);
11269 int entry_point=do_dirty_stub(i);
11270 ll_add_32(jump_in+page,vaddr,r,(void *)entry_point);
11271 }
11272 }
11273 }
11274 }
11275 // Write out the literal pool if necessary
11276 literal_pool(0);
11277 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
11278 // Align code
11279 if(((u_int)out)&7) emit_addnop(13);
11280 #endif
11281 assert((u_int)out-beginning<MAX_OUTPUT_BLOCK_SIZE);
11282 //printf("shadow buffer: %x-%x\n",(int)copy,(int)copy+slen*4);
11283 memcpy(copy,source,slen*4);
11284 copy+=slen*4;
11285
11286 #ifdef __arm__
11287 __clear_cache((void *)beginning,out);
11288 #endif
11289
11290 // If we're within 256K of the end of the buffer,
11291 // start over from the beginning. (Is 256K enough?)
11292 if((int)out>BASE_ADDR+(1<<TARGET_SIZE_2)-MAX_OUTPUT_BLOCK_SIZE) out=(u_char *)BASE_ADDR;
11293
11294 // Trap writes to any of the pages we compiled
11295 for(i=start>>12;i<=(start+slen*4)>>12;i++) {
11296 invalid_code[i]=0;
90ae6d4e 11297#ifndef DISABLE_TLB
57871462 11298 memory_map[i]|=0x40000000;
11299 if((signed int)start>=(signed int)0xC0000000) {
11300 assert(using_tlb);
11301 j=(((u_int)i<<12)+(memory_map[i]<<2)-(u_int)rdram+(u_int)0x80000000)>>12;
11302 invalid_code[j]=0;
11303 memory_map[j]|=0x40000000;
11304 //printf("write protect physical page: %x (virtual %x)\n",j<<12,start);
11305 }
90ae6d4e 11306#endif
57871462 11307 }
b12c9fb8 11308#ifdef PCSX
11309 // PCSX maps all RAM mirror invalid_code tests to 0x80000000..0x80000000+RAM_SIZE
11310 if(get_page(start)<(RAM_SIZE>>12))
11311 for(i=start>>12;i<=(start+slen*4)>>12;i++)
11312 invalid_code[((u_int)0x80000000>>12)|i]=0;
11313#endif
57871462 11314
11315 /* Pass 10 - Free memory by expiring oldest blocks */
11316
11317 int end=((((int)out-BASE_ADDR)>>(TARGET_SIZE_2-16))+16384)&65535;
11318 while(expirep!=end)
11319 {
11320 int shift=TARGET_SIZE_2-3; // Divide into 8 blocks
11321 int base=BASE_ADDR+((expirep>>13)<<shift); // Base address of this block
11322 inv_debug("EXP: Phase %d\n",expirep);
11323 switch((expirep>>11)&3)
11324 {
11325 case 0:
11326 // Clear jump_in and jump_dirty
11327 ll_remove_matching_addrs(jump_in+(expirep&2047),base,shift);
11328 ll_remove_matching_addrs(jump_dirty+(expirep&2047),base,shift);
11329 ll_remove_matching_addrs(jump_in+2048+(expirep&2047),base,shift);
11330 ll_remove_matching_addrs(jump_dirty+2048+(expirep&2047),base,shift);
11331 break;
11332 case 1:
11333 // Clear pointers
11334 ll_kill_pointers(jump_out[expirep&2047],base,shift);
11335 ll_kill_pointers(jump_out[(expirep&2047)+2048],base,shift);
11336 break;
11337 case 2:
11338 // Clear hash table
11339 for(i=0;i<32;i++) {
11340 int *ht_bin=hash_table[((expirep&2047)<<5)+i];
11341 if((ht_bin[3]>>shift)==(base>>shift) ||
11342 ((ht_bin[3]-MAX_OUTPUT_BLOCK_SIZE)>>shift)==(base>>shift)) {
11343 inv_debug("EXP: Remove hash %x -> %x\n",ht_bin[2],ht_bin[3]);
11344 ht_bin[2]=ht_bin[3]=-1;
11345 }
11346 if((ht_bin[1]>>shift)==(base>>shift) ||
11347 ((ht_bin[1]-MAX_OUTPUT_BLOCK_SIZE)>>shift)==(base>>shift)) {
11348 inv_debug("EXP: Remove hash %x -> %x\n",ht_bin[0],ht_bin[1]);
11349 ht_bin[0]=ht_bin[2];
11350 ht_bin[1]=ht_bin[3];
11351 ht_bin[2]=ht_bin[3]=-1;
11352 }
11353 }
11354 break;
11355 case 3:
11356 // Clear jump_out
dd3a91a1 11357 #ifdef __arm__
11358 if((expirep&2047)==0)
11359 do_clear_cache();
11360 #endif
57871462 11361 ll_remove_matching_addrs(jump_out+(expirep&2047),base,shift);
11362 ll_remove_matching_addrs(jump_out+2048+(expirep&2047),base,shift);
11363 break;
11364 }
11365 expirep=(expirep+1)&65535;
11366 }
11367 return 0;
11368}
b9b61529 11369
11370// vim:shiftwidth=2:expandtab
ARM optimized PCSX fork