try to support more compilers
[pcsx_rearmed.git] / libpcsxcore / new_dynarec / new_dynarec.c
CommitLineData
57871462 1/* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
2 * Mupen64plus - new_dynarec.c *
20d507ba 3 * Copyright (C) 2009-2011 Ari64 *
57871462 4 * *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
9 * *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
14 * *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. *
19 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */
20
21#include <stdlib.h>
22#include <stdint.h> //include for uint64_t
23#include <assert.h>
4600ba03 24#include <sys/mman.h>
57871462 25
3d624f89 26#include "emu_if.h" //emulator interface
57871462 27
4600ba03 28//#define DISASM
29//#define assem_debug printf
30//#define inv_debug printf
31#define assem_debug(...)
32#define inv_debug(...)
57871462 33
34#ifdef __i386__
35#include "assem_x86.h"
36#endif
37#ifdef __x86_64__
38#include "assem_x64.h"
39#endif
40#ifdef __arm__
41#include "assem_arm.h"
42#endif
43
44#define MAXBLOCK 4096
45#define MAX_OUTPUT_BLOCK_SIZE 262144
46#define CLOCK_DIVIDER 2
47
48struct regstat
49{
50 signed char regmap_entry[HOST_REGS];
51 signed char regmap[HOST_REGS];
52 uint64_t was32;
53 uint64_t is32;
54 uint64_t wasdirty;
55 uint64_t dirty;
56 uint64_t u;
57 uint64_t uu;
58 u_int wasconst;
59 u_int isconst;
60 uint64_t constmap[HOST_REGS];
61};
62
63struct ll_entry
64{
65 u_int vaddr;
66 u_int reg32;
67 void *addr;
68 struct ll_entry *next;
69};
70
71 u_int start;
72 u_int *source;
73 u_int pagelimit;
74 char insn[MAXBLOCK][10];
75 u_char itype[MAXBLOCK];
76 u_char opcode[MAXBLOCK];
77 u_char opcode2[MAXBLOCK];
78 u_char bt[MAXBLOCK];
79 u_char rs1[MAXBLOCK];
80 u_char rs2[MAXBLOCK];
81 u_char rt1[MAXBLOCK];
82 u_char rt2[MAXBLOCK];
83 u_char us1[MAXBLOCK];
84 u_char us2[MAXBLOCK];
85 u_char dep1[MAXBLOCK];
86 u_char dep2[MAXBLOCK];
87 u_char lt1[MAXBLOCK];
bedfea38 88 static uint64_t gte_rs[MAXBLOCK]; // gte: 32 data and 32 ctl regs
89 static uint64_t gte_rt[MAXBLOCK];
90 static uint64_t gte_unneeded[MAXBLOCK];
91 static int gte_reads_flags; // gte flag read encountered
57871462 92 int imm[MAXBLOCK];
93 u_int ba[MAXBLOCK];
94 char likely[MAXBLOCK];
95 char is_ds[MAXBLOCK];
e1190b87 96 char ooo[MAXBLOCK];
57871462 97 uint64_t unneeded_reg[MAXBLOCK];
98 uint64_t unneeded_reg_upper[MAXBLOCK];
99 uint64_t branch_unneeded_reg[MAXBLOCK];
100 uint64_t branch_unneeded_reg_upper[MAXBLOCK];
101 uint64_t p32[MAXBLOCK];
102 uint64_t pr32[MAXBLOCK];
103 signed char regmap_pre[MAXBLOCK][HOST_REGS];
104 signed char regmap[MAXBLOCK][HOST_REGS];
105 signed char regmap_entry[MAXBLOCK][HOST_REGS];
106 uint64_t constmap[MAXBLOCK][HOST_REGS];
57871462 107 struct regstat regs[MAXBLOCK];
108 struct regstat branch_regs[MAXBLOCK];
e1190b87 109 signed char minimum_free_regs[MAXBLOCK];
57871462 110 u_int needed_reg[MAXBLOCK];
111 uint64_t requires_32bit[MAXBLOCK];
112 u_int wont_dirty[MAXBLOCK];
113 u_int will_dirty[MAXBLOCK];
114 int ccadj[MAXBLOCK];
115 int slen;
116 u_int instr_addr[MAXBLOCK];
117 u_int link_addr[MAXBLOCK][3];
118 int linkcount;
119 u_int stubs[MAXBLOCK*3][8];
120 int stubcount;
121 u_int literals[1024][2];
122 int literalcount;
123 int is_delayslot;
124 int cop1_usable;
125 u_char *out;
126 struct ll_entry *jump_in[4096];
127 struct ll_entry *jump_out[4096];
128 struct ll_entry *jump_dirty[4096];
129 u_int hash_table[65536][4] __attribute__((aligned(16)));
130 char shadow[1048576] __attribute__((aligned(16)));
131 void *copy;
132 int expirep;
af4ee1fe 133#ifndef PCSX
57871462 134 u_int using_tlb;
af4ee1fe 135#else
136 static const u_int using_tlb=0;
137#endif
dadf55f2 138 static u_int sp_in_mirror;
57871462 139 u_int stop_after_jal;
140 extern u_char restore_candidate[512];
141 extern int cycle_count;
142
143 /* registers that may be allocated */
144 /* 1-31 gpr */
145#define HIREG 32 // hi
146#define LOREG 33 // lo
147#define FSREG 34 // FPU status (FCSR)
148#define CSREG 35 // Coprocessor status
149#define CCREG 36 // Cycle count
150#define INVCP 37 // Pointer to invalid_code
619e5ded 151#define MMREG 38 // Pointer to memory_map
152#define ROREG 39 // ram offset (if rdram!=0x80000000)
153#define TEMPREG 40
154#define FTEMP 40 // FPU temporary register
155#define PTEMP 41 // Prefetch temporary register
156#define TLREG 42 // TLB mapping offset
157#define RHASH 43 // Return address hash
158#define RHTBL 44 // Return address hash table address
159#define RTEMP 45 // JR/JALR address register
160#define MAXREG 45
161#define AGEN1 46 // Address generation temporary register
162#define AGEN2 47 // Address generation temporary register
163#define MGEN1 48 // Maptable address generation temporary register
164#define MGEN2 49 // Maptable address generation temporary register
165#define BTREG 50 // Branch target temporary register
57871462 166
167 /* instruction types */
168#define NOP 0 // No operation
169#define LOAD 1 // Load
170#define STORE 2 // Store
171#define LOADLR 3 // Unaligned load
172#define STORELR 4 // Unaligned store
173#define MOV 5 // Move
174#define ALU 6 // Arithmetic/logic
175#define MULTDIV 7 // Multiply/divide
176#define SHIFT 8 // Shift by register
177#define SHIFTIMM 9// Shift by immediate
178#define IMM16 10 // 16-bit immediate
179#define RJUMP 11 // Unconditional jump to register
180#define UJUMP 12 // Unconditional jump
181#define CJUMP 13 // Conditional branch (BEQ/BNE/BGTZ/BLEZ)
182#define SJUMP 14 // Conditional branch (regimm format)
183#define COP0 15 // Coprocessor 0
184#define COP1 16 // Coprocessor 1
185#define C1LS 17 // Coprocessor 1 load/store
186#define FJUMP 18 // Conditional branch (floating point)
187#define FLOAT 19 // Floating point unit
188#define FCONV 20 // Convert integer to float
189#define FCOMP 21 // Floating point compare (sets FSREG)
190#define SYSCALL 22// SYSCALL
191#define OTHER 23 // Other
192#define SPAN 24 // Branch/delay slot spans 2 pages
193#define NI 25 // Not implemented
7139f3c8 194#define HLECALL 26// PCSX fake opcodes for HLE
b9b61529 195#define COP2 27 // Coprocessor 2 move
196#define C2LS 28 // Coprocessor 2 load/store
197#define C2OP 29 // Coprocessor 2 operation
1e973cb0 198#define INTCALL 30// Call interpreter to handle rare corner cases
57871462 199
200 /* stubs */
201#define CC_STUB 1
202#define FP_STUB 2
203#define LOADB_STUB 3
204#define LOADH_STUB 4
205#define LOADW_STUB 5
206#define LOADD_STUB 6
207#define LOADBU_STUB 7
208#define LOADHU_STUB 8
209#define STOREB_STUB 9
210#define STOREH_STUB 10
211#define STOREW_STUB 11
212#define STORED_STUB 12
213#define STORELR_STUB 13
214#define INVCODE_STUB 14
215
216 /* branch codes */
217#define TAKEN 1
218#define NOTTAKEN 2
219#define NULLDS 3
220
221// asm linkage
222int new_recompile_block(int addr);
223void *get_addr_ht(u_int vaddr);
224void invalidate_block(u_int block);
225void invalidate_addr(u_int addr);
226void remove_hash(int vaddr);
227void jump_vaddr();
228void dyna_linker();
229void dyna_linker_ds();
230void verify_code();
231void verify_code_vm();
232void verify_code_ds();
233void cc_interrupt();
234void fp_exception();
235void fp_exception_ds();
236void jump_syscall();
7139f3c8 237void jump_syscall_hle();
57871462 238void jump_eret();
7139f3c8 239void jump_hlecall();
1e973cb0 240void jump_intcall();
7139f3c8 241void new_dyna_leave();
57871462 242
243// TLB
244void TLBWI_new();
245void TLBWR_new();
246void read_nomem_new();
247void read_nomemb_new();
248void read_nomemh_new();
249void read_nomemd_new();
250void write_nomem_new();
251void write_nomemb_new();
252void write_nomemh_new();
253void write_nomemd_new();
254void write_rdram_new();
255void write_rdramb_new();
256void write_rdramh_new();
257void write_rdramd_new();
258extern u_int memory_map[1048576];
259
260// Needed by assembler
261void wb_register(signed char r,signed char regmap[],uint64_t dirty,uint64_t is32);
262void wb_dirtys(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty);
263void wb_needed_dirtys(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr);
264void load_all_regs(signed char i_regmap[]);
265void load_needed_regs(signed char i_regmap[],signed char next_regmap[]);
266void load_regs_entry(int t);
267void load_all_consts(signed char regmap[],int is32,u_int dirty,int i);
268
269int tracedebug=0;
270
271//#define DEBUG_CYCLE_COUNT 1
272
94d23bb9 273static void tlb_hacks()
57871462 274{
94d23bb9 275#ifndef DISABLE_TLB
57871462 276 // Goldeneye hack
277 if (strncmp((char *) ROM_HEADER->nom, "GOLDENEYE",9) == 0)
278 {
279 u_int addr;
280 int n;
281 switch (ROM_HEADER->Country_code&0xFF)
282 {
283 case 0x45: // U
284 addr=0x34b30;
285 break;
286 case 0x4A: // J
287 addr=0x34b70;
288 break;
289 case 0x50: // E
290 addr=0x329f0;
291 break;
292 default:
293 // Unknown country code
294 addr=0;
295 break;
296 }
297 u_int rom_addr=(u_int)rom;
298 #ifdef ROM_COPY
299 // Since memory_map is 32-bit, on 64-bit systems the rom needs to be
300 // in the lower 4G of memory to use this hack. Copy it if necessary.
301 if((void *)rom>(void *)0xffffffff) {
302 munmap(ROM_COPY, 67108864);
303 if(mmap(ROM_COPY, 12582912,
304 PROT_READ | PROT_WRITE,
305 MAP_FIXED | MAP_PRIVATE | MAP_ANONYMOUS,
306 -1, 0) <= 0) {printf("mmap() failed\n");}
307 memcpy(ROM_COPY,rom,12582912);
308 rom_addr=(u_int)ROM_COPY;
309 }
310 #endif
311 if(addr) {
312 for(n=0x7F000;n<0x80000;n++) {
313 memory_map[n]=(((u_int)(rom_addr+addr-0x7F000000))>>2)|0x40000000;
314 }
315 }
316 }
94d23bb9 317#endif
57871462 318}
319
94d23bb9 320static u_int get_page(u_int vaddr)
57871462 321{
0ce47d46 322#ifndef PCSX
57871462 323 u_int page=(vaddr^0x80000000)>>12;
0ce47d46 324#else
325 u_int page=vaddr&~0xe0000000;
326 if (page < 0x1000000)
327 page &= ~0x0e00000; // RAM mirrors
328 page>>=12;
329#endif
94d23bb9 330#ifndef DISABLE_TLB
57871462 331 if(page>262143&&tlb_LUT_r[vaddr>>12]) page=(tlb_LUT_r[vaddr>>12]^0x80000000)>>12;
94d23bb9 332#endif
57871462 333 if(page>2048) page=2048+(page&2047);
94d23bb9 334 return page;
335}
336
337static u_int get_vpage(u_int vaddr)
338{
339 u_int vpage=(vaddr^0x80000000)>>12;
340#ifndef DISABLE_TLB
57871462 341 if(vpage>262143&&tlb_LUT_r[vaddr>>12]) vpage&=2047; // jump_dirty uses a hash of the virtual address instead
94d23bb9 342#endif
57871462 343 if(vpage>2048) vpage=2048+(vpage&2047);
94d23bb9 344 return vpage;
345}
346
347// Get address from virtual address
348// This is called from the recompiled JR/JALR instructions
349void *get_addr(u_int vaddr)
350{
351 u_int page=get_page(vaddr);
352 u_int vpage=get_vpage(vaddr);
57871462 353 struct ll_entry *head;
354 //printf("TRACE: count=%d next=%d (get_addr %x,page %d)\n",Count,next_interupt,vaddr,page);
355 head=jump_in[page];
356 while(head!=NULL) {
357 if(head->vaddr==vaddr&&head->reg32==0) {
358 //printf("TRACE: count=%d next=%d (get_addr match %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr);
359 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
360 ht_bin[3]=ht_bin[1];
361 ht_bin[2]=ht_bin[0];
362 ht_bin[1]=(int)head->addr;
363 ht_bin[0]=vaddr;
364 return head->addr;
365 }
366 head=head->next;
367 }
368 head=jump_dirty[vpage];
369 while(head!=NULL) {
370 if(head->vaddr==vaddr&&head->reg32==0) {
371 //printf("TRACE: count=%d next=%d (get_addr match dirty %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr);
372 // Don't restore blocks which are about to expire from the cache
373 if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
374 if(verify_dirty(head->addr)) {
375 //printf("restore candidate: %x (%d) d=%d\n",vaddr,page,invalid_code[vaddr>>12]);
376 invalid_code[vaddr>>12]=0;
9be4ba64 377 inv_code_start=inv_code_end=~0;
57871462 378 memory_map[vaddr>>12]|=0x40000000;
379 if(vpage<2048) {
94d23bb9 380#ifndef DISABLE_TLB
57871462 381 if(tlb_LUT_r[vaddr>>12]) {
382 invalid_code[tlb_LUT_r[vaddr>>12]>>12]=0;
383 memory_map[tlb_LUT_r[vaddr>>12]>>12]|=0x40000000;
384 }
94d23bb9 385#endif
57871462 386 restore_candidate[vpage>>3]|=1<<(vpage&7);
387 }
388 else restore_candidate[page>>3]|=1<<(page&7);
389 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
390 if(ht_bin[0]==vaddr) {
391 ht_bin[1]=(int)head->addr; // Replace existing entry
392 }
393 else
394 {
395 ht_bin[3]=ht_bin[1];
396 ht_bin[2]=ht_bin[0];
397 ht_bin[1]=(int)head->addr;
398 ht_bin[0]=vaddr;
399 }
400 return head->addr;
401 }
402 }
403 head=head->next;
404 }
405 //printf("TRACE: count=%d next=%d (get_addr no-match %x)\n",Count,next_interupt,vaddr);
406 int r=new_recompile_block(vaddr);
407 if(r==0) return get_addr(vaddr);
408 // Execute in unmapped page, generate pagefault execption
409 Status|=2;
410 Cause=(vaddr<<31)|0x8;
411 EPC=(vaddr&1)?vaddr-5:vaddr;
412 BadVAddr=(vaddr&~1);
413 Context=(Context&0xFF80000F)|((BadVAddr>>9)&0x007FFFF0);
414 EntryHi=BadVAddr&0xFFFFE000;
415 return get_addr_ht(0x80000000);
416}
417// Look up address in hash table first
418void *get_addr_ht(u_int vaddr)
419{
420 //printf("TRACE: count=%d next=%d (get_addr_ht %x)\n",Count,next_interupt,vaddr);
421 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
422 if(ht_bin[0]==vaddr) return (void *)ht_bin[1];
423 if(ht_bin[2]==vaddr) return (void *)ht_bin[3];
424 return get_addr(vaddr);
425}
426
427void *get_addr_32(u_int vaddr,u_int flags)
428{
7139f3c8 429#ifdef FORCE32
430 return get_addr(vaddr);
560e4a12 431#else
57871462 432 //printf("TRACE: count=%d next=%d (get_addr_32 %x,flags %x)\n",Count,next_interupt,vaddr,flags);
433 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
434 if(ht_bin[0]==vaddr) return (void *)ht_bin[1];
435 if(ht_bin[2]==vaddr) return (void *)ht_bin[3];
94d23bb9 436 u_int page=get_page(vaddr);
437 u_int vpage=get_vpage(vaddr);
57871462 438 struct ll_entry *head;
439 head=jump_in[page];
440 while(head!=NULL) {
441 if(head->vaddr==vaddr&&(head->reg32&flags)==0) {
442 //printf("TRACE: count=%d next=%d (get_addr_32 match %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr);
443 if(head->reg32==0) {
444 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
445 if(ht_bin[0]==-1) {
446 ht_bin[1]=(int)head->addr;
447 ht_bin[0]=vaddr;
448 }else if(ht_bin[2]==-1) {
449 ht_bin[3]=(int)head->addr;
450 ht_bin[2]=vaddr;
451 }
452 //ht_bin[3]=ht_bin[1];
453 //ht_bin[2]=ht_bin[0];
454 //ht_bin[1]=(int)head->addr;
455 //ht_bin[0]=vaddr;
456 }
457 return head->addr;
458 }
459 head=head->next;
460 }
461 head=jump_dirty[vpage];
462 while(head!=NULL) {
463 if(head->vaddr==vaddr&&(head->reg32&flags)==0) {
464 //printf("TRACE: count=%d next=%d (get_addr_32 match dirty %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr);
465 // Don't restore blocks which are about to expire from the cache
466 if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
467 if(verify_dirty(head->addr)) {
468 //printf("restore candidate: %x (%d) d=%d\n",vaddr,page,invalid_code[vaddr>>12]);
469 invalid_code[vaddr>>12]=0;
9be4ba64 470 inv_code_start=inv_code_end=~0;
57871462 471 memory_map[vaddr>>12]|=0x40000000;
472 if(vpage<2048) {
94d23bb9 473#ifndef DISABLE_TLB
57871462 474 if(tlb_LUT_r[vaddr>>12]) {
475 invalid_code[tlb_LUT_r[vaddr>>12]>>12]=0;
476 memory_map[tlb_LUT_r[vaddr>>12]>>12]|=0x40000000;
477 }
94d23bb9 478#endif
57871462 479 restore_candidate[vpage>>3]|=1<<(vpage&7);
480 }
481 else restore_candidate[page>>3]|=1<<(page&7);
482 if(head->reg32==0) {
483 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
484 if(ht_bin[0]==-1) {
485 ht_bin[1]=(int)head->addr;
486 ht_bin[0]=vaddr;
487 }else if(ht_bin[2]==-1) {
488 ht_bin[3]=(int)head->addr;
489 ht_bin[2]=vaddr;
490 }
491 //ht_bin[3]=ht_bin[1];
492 //ht_bin[2]=ht_bin[0];
493 //ht_bin[1]=(int)head->addr;
494 //ht_bin[0]=vaddr;
495 }
496 return head->addr;
497 }
498 }
499 head=head->next;
500 }
501 //printf("TRACE: count=%d next=%d (get_addr_32 no-match %x,flags %x)\n",Count,next_interupt,vaddr,flags);
502 int r=new_recompile_block(vaddr);
503 if(r==0) return get_addr(vaddr);
504 // Execute in unmapped page, generate pagefault execption
505 Status|=2;
506 Cause=(vaddr<<31)|0x8;
507 EPC=(vaddr&1)?vaddr-5:vaddr;
508 BadVAddr=(vaddr&~1);
509 Context=(Context&0xFF80000F)|((BadVAddr>>9)&0x007FFFF0);
510 EntryHi=BadVAddr&0xFFFFE000;
511 return get_addr_ht(0x80000000);
560e4a12 512#endif
57871462 513}
514
515void clear_all_regs(signed char regmap[])
516{
517 int hr;
518 for (hr=0;hr<HOST_REGS;hr++) regmap[hr]=-1;
519}
520
521signed char get_reg(signed char regmap[],int r)
522{
523 int hr;
524 for (hr=0;hr<HOST_REGS;hr++) if(hr!=EXCLUDE_REG&&regmap[hr]==r) return hr;
525 return -1;
526}
527
528// Find a register that is available for two consecutive cycles
529signed char get_reg2(signed char regmap1[],signed char regmap2[],int r)
530{
531 int hr;
532 for (hr=0;hr<HOST_REGS;hr++) if(hr!=EXCLUDE_REG&&regmap1[hr]==r&&regmap2[hr]==r) return hr;
533 return -1;
534}
535
536int count_free_regs(signed char regmap[])
537{
538 int count=0;
539 int hr;
540 for(hr=0;hr<HOST_REGS;hr++)
541 {
542 if(hr!=EXCLUDE_REG) {
543 if(regmap[hr]<0) count++;
544 }
545 }
546 return count;
547}
548
549void dirty_reg(struct regstat *cur,signed char reg)
550{
551 int hr;
552 if(!reg) return;
553 for (hr=0;hr<HOST_REGS;hr++) {
554 if((cur->regmap[hr]&63)==reg) {
555 cur->dirty|=1<<hr;
556 }
557 }
558}
559
560// If we dirty the lower half of a 64 bit register which is now being
561// sign-extended, we need to dump the upper half.
562// Note: Do this only after completion of the instruction, because
563// some instructions may need to read the full 64-bit value even if
564// overwriting it (eg SLTI, DSRA32).
565static void flush_dirty_uppers(struct regstat *cur)
566{
567 int hr,reg;
568 for (hr=0;hr<HOST_REGS;hr++) {
569 if((cur->dirty>>hr)&1) {
570 reg=cur->regmap[hr];
571 if(reg>=64)
572 if((cur->is32>>(reg&63))&1) cur->regmap[hr]=-1;
573 }
574 }
575}
576
577void set_const(struct regstat *cur,signed char reg,uint64_t value)
578{
579 int hr;
580 if(!reg) return;
581 for (hr=0;hr<HOST_REGS;hr++) {
582 if(cur->regmap[hr]==reg) {
583 cur->isconst|=1<<hr;
584 cur->constmap[hr]=value;
585 }
586 else if((cur->regmap[hr]^64)==reg) {
587 cur->isconst|=1<<hr;
588 cur->constmap[hr]=value>>32;
589 }
590 }
591}
592
593void clear_const(struct regstat *cur,signed char reg)
594{
595 int hr;
596 if(!reg) return;
597 for (hr=0;hr<HOST_REGS;hr++) {
598 if((cur->regmap[hr]&63)==reg) {
599 cur->isconst&=~(1<<hr);
600 }
601 }
602}
603
604int is_const(struct regstat *cur,signed char reg)
605{
606 int hr;
79c75f1b 607 if(reg<0) return 0;
57871462 608 if(!reg) return 1;
609 for (hr=0;hr<HOST_REGS;hr++) {
610 if((cur->regmap[hr]&63)==reg) {
611 return (cur->isconst>>hr)&1;
612 }
613 }
614 return 0;
615}
616uint64_t get_const(struct regstat *cur,signed char reg)
617{
618 int hr;
619 if(!reg) return 0;
620 for (hr=0;hr<HOST_REGS;hr++) {
621 if(cur->regmap[hr]==reg) {
622 return cur->constmap[hr];
623 }
624 }
625 printf("Unknown constant in r%d\n",reg);
626 exit(1);
627}
628
629// Least soon needed registers
630// Look at the next ten instructions and see which registers
631// will be used. Try not to reallocate these.
632void lsn(u_char hsn[], int i, int *preferred_reg)
633{
634 int j;
635 int b=-1;
636 for(j=0;j<9;j++)
637 {
638 if(i+j>=slen) {
639 j=slen-i-1;
640 break;
641 }
642 if(itype[i+j]==UJUMP||itype[i+j]==RJUMP||(source[i+j]>>16)==0x1000)
643 {
644 // Don't go past an unconditonal jump
645 j++;
646 break;
647 }
648 }
649 for(;j>=0;j--)
650 {
651 if(rs1[i+j]) hsn[rs1[i+j]]=j;
652 if(rs2[i+j]) hsn[rs2[i+j]]=j;
653 if(rt1[i+j]) hsn[rt1[i+j]]=j;
654 if(rt2[i+j]) hsn[rt2[i+j]]=j;
655 if(itype[i+j]==STORE || itype[i+j]==STORELR) {
656 // Stores can allocate zero
657 hsn[rs1[i+j]]=j;
658 hsn[rs2[i+j]]=j;
659 }
660 // On some architectures stores need invc_ptr
661 #if defined(HOST_IMM8)
b9b61529 662 if(itype[i+j]==STORE || itype[i+j]==STORELR || (opcode[i+j]&0x3b)==0x39 || (opcode[i+j]&0x3b)==0x3a) {
57871462 663 hsn[INVCP]=j;
664 }
665 #endif
666 if(i+j>=0&&(itype[i+j]==UJUMP||itype[i+j]==CJUMP||itype[i+j]==SJUMP||itype[i+j]==FJUMP))
667 {
668 hsn[CCREG]=j;
669 b=j;
670 }
671 }
672 if(b>=0)
673 {
674 if(ba[i+b]>=start && ba[i+b]<(start+slen*4))
675 {
676 // Follow first branch
677 int t=(ba[i+b]-start)>>2;
678 j=7-b;if(t+j>=slen) j=slen-t-1;
679 for(;j>=0;j--)
680 {
681 if(rs1[t+j]) if(hsn[rs1[t+j]]>j+b+2) hsn[rs1[t+j]]=j+b+2;
682 if(rs2[t+j]) if(hsn[rs2[t+j]]>j+b+2) hsn[rs2[t+j]]=j+b+2;
683 //if(rt1[t+j]) if(hsn[rt1[t+j]]>j+b+2) hsn[rt1[t+j]]=j+b+2;
684 //if(rt2[t+j]) if(hsn[rt2[t+j]]>j+b+2) hsn[rt2[t+j]]=j+b+2;
685 }
686 }
687 // TODO: preferred register based on backward branch
688 }
689 // Delay slot should preferably not overwrite branch conditions or cycle count
690 if(i>0&&(itype[i-1]==RJUMP||itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP)) {
691 if(rs1[i-1]) if(hsn[rs1[i-1]]>1) hsn[rs1[i-1]]=1;
692 if(rs2[i-1]) if(hsn[rs2[i-1]]>1) hsn[rs2[i-1]]=1;
693 hsn[CCREG]=1;
694 // ...or hash tables
695 hsn[RHASH]=1;
696 hsn[RHTBL]=1;
697 }
698 // Coprocessor load/store needs FTEMP, even if not declared
b9b61529 699 if(itype[i]==C1LS||itype[i]==C2LS) {
57871462 700 hsn[FTEMP]=0;
701 }
702 // Load L/R also uses FTEMP as a temporary register
703 if(itype[i]==LOADLR) {
704 hsn[FTEMP]=0;
705 }
b7918751 706 // Also SWL/SWR/SDL/SDR
707 if(opcode[i]==0x2a||opcode[i]==0x2e||opcode[i]==0x2c||opcode[i]==0x2d) {
57871462 708 hsn[FTEMP]=0;
709 }
710 // Don't remove the TLB registers either
b9b61529 711 if(itype[i]==LOAD || itype[i]==LOADLR || itype[i]==STORE || itype[i]==STORELR || itype[i]==C1LS || itype[i]==C2LS) {
57871462 712 hsn[TLREG]=0;
713 }
714 // Don't remove the miniht registers
715 if(itype[i]==UJUMP||itype[i]==RJUMP)
716 {
717 hsn[RHASH]=0;
718 hsn[RHTBL]=0;
719 }
720}
721
722// We only want to allocate registers if we're going to use them again soon
723int needed_again(int r, int i)
724{
725 int j;
726 int b=-1;
727 int rn=10;
57871462 728
729 if(i>0&&(itype[i-1]==UJUMP||itype[i-1]==RJUMP||(source[i-1]>>16)==0x1000))
730 {
731 if(ba[i-1]<start || ba[i-1]>start+slen*4-4)
732 return 0; // Don't need any registers if exiting the block
733 }
734 for(j=0;j<9;j++)
735 {
736 if(i+j>=slen) {
737 j=slen-i-1;
738 break;
739 }
740 if(itype[i+j]==UJUMP||itype[i+j]==RJUMP||(source[i+j]>>16)==0x1000)
741 {
742 // Don't go past an unconditonal jump
743 j++;
744 break;
745 }
1e973cb0 746 if(itype[i+j]==SYSCALL||itype[i+j]==HLECALL||itype[i+j]==INTCALL||((source[i+j]&0xfc00003f)==0x0d))
57871462 747 {
748 break;
749 }
750 }
751 for(;j>=1;j--)
752 {
753 if(rs1[i+j]==r) rn=j;
754 if(rs2[i+j]==r) rn=j;
755 if((unneeded_reg[i+j]>>r)&1) rn=10;
756 if(i+j>=0&&(itype[i+j]==UJUMP||itype[i+j]==CJUMP||itype[i+j]==SJUMP||itype[i+j]==FJUMP))
757 {
758 b=j;
759 }
760 }
761 /*
762 if(b>=0)
763 {
764 if(ba[i+b]>=start && ba[i+b]<(start+slen*4))
765 {
766 // Follow first branch
767 int o=rn;
768 int t=(ba[i+b]-start)>>2;
769 j=7-b;if(t+j>=slen) j=slen-t-1;
770 for(;j>=0;j--)
771 {
772 if(!((unneeded_reg[t+j]>>r)&1)) {
773 if(rs1[t+j]==r) if(rn>j+b+2) rn=j+b+2;
774 if(rs2[t+j]==r) if(rn>j+b+2) rn=j+b+2;
775 }
776 else rn=o;
777 }
778 }
779 }*/
b7217e13 780 if(rn<10) return 1;
57871462 781 return 0;
782}
783
784// Try to match register allocations at the end of a loop with those
785// at the beginning
786int loop_reg(int i, int r, int hr)
787{
788 int j,k;
789 for(j=0;j<9;j++)
790 {
791 if(i+j>=slen) {
792 j=slen-i-1;
793 break;
794 }
795 if(itype[i+j]==UJUMP||itype[i+j]==RJUMP||(source[i+j]>>16)==0x1000)
796 {
797 // Don't go past an unconditonal jump
798 j++;
799 break;
800 }
801 }
802 k=0;
803 if(i>0){
804 if(itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP)
805 k--;
806 }
807 for(;k<j;k++)
808 {
809 if(r<64&&((unneeded_reg[i+k]>>r)&1)) return hr;
810 if(r>64&&((unneeded_reg_upper[i+k]>>r)&1)) return hr;
811 if(i+k>=0&&(itype[i+k]==UJUMP||itype[i+k]==CJUMP||itype[i+k]==SJUMP||itype[i+k]==FJUMP))
812 {
813 if(ba[i+k]>=start && ba[i+k]<(start+i*4))
814 {
815 int t=(ba[i+k]-start)>>2;
816 int reg=get_reg(regs[t].regmap_entry,r);
817 if(reg>=0) return reg;
818 //reg=get_reg(regs[t+1].regmap_entry,r);
819 //if(reg>=0) return reg;
820 }
821 }
822 }
823 return hr;
824}
825
826
827// Allocate every register, preserving source/target regs
828void alloc_all(struct regstat *cur,int i)
829{
830 int hr;
831
832 for(hr=0;hr<HOST_REGS;hr++) {
833 if(hr!=EXCLUDE_REG) {
834 if(((cur->regmap[hr]&63)!=rs1[i])&&((cur->regmap[hr]&63)!=rs2[i])&&
835 ((cur->regmap[hr]&63)!=rt1[i])&&((cur->regmap[hr]&63)!=rt2[i]))
836 {
837 cur->regmap[hr]=-1;
838 cur->dirty&=~(1<<hr);
839 }
840 // Don't need zeros
841 if((cur->regmap[hr]&63)==0)
842 {
843 cur->regmap[hr]=-1;
844 cur->dirty&=~(1<<hr);
845 }
846 }
847 }
848}
849
4600ba03 850#ifndef FORCE32
57871462 851void div64(int64_t dividend,int64_t divisor)
852{
853 lo=dividend/divisor;
854 hi=dividend%divisor;
855 //printf("TRACE: ddiv %8x%8x %8x%8x\n" ,(int)reg[HIREG],(int)(reg[HIREG]>>32)
856 // ,(int)reg[LOREG],(int)(reg[LOREG]>>32));
857}
858void divu64(uint64_t dividend,uint64_t divisor)
859{
860 lo=dividend/divisor;
861 hi=dividend%divisor;
862 //printf("TRACE: ddivu %8x%8x %8x%8x\n",(int)reg[HIREG],(int)(reg[HIREG]>>32)
863 // ,(int)reg[LOREG],(int)(reg[LOREG]>>32));
864}
865
866void mult64(uint64_t m1,uint64_t m2)
867{
868 unsigned long long int op1, op2, op3, op4;
869 unsigned long long int result1, result2, result3, result4;
870 unsigned long long int temp1, temp2, temp3, temp4;
871 int sign = 0;
872
873 if (m1 < 0)
874 {
875 op2 = -m1;
876 sign = 1 - sign;
877 }
878 else op2 = m1;
879 if (m2 < 0)
880 {
881 op4 = -m2;
882 sign = 1 - sign;
883 }
884 else op4 = m2;
885
886 op1 = op2 & 0xFFFFFFFF;
887 op2 = (op2 >> 32) & 0xFFFFFFFF;
888 op3 = op4 & 0xFFFFFFFF;
889 op4 = (op4 >> 32) & 0xFFFFFFFF;
890
891 temp1 = op1 * op3;
892 temp2 = (temp1 >> 32) + op1 * op4;
893 temp3 = op2 * op3;
894 temp4 = (temp3 >> 32) + op2 * op4;
895
896 result1 = temp1 & 0xFFFFFFFF;
897 result2 = temp2 + (temp3 & 0xFFFFFFFF);
898 result3 = (result2 >> 32) + temp4;
899 result4 = (result3 >> 32);
900
901 lo = result1 | (result2 << 32);
902 hi = (result3 & 0xFFFFFFFF) | (result4 << 32);
903 if (sign)
904 {
905 hi = ~hi;
906 if (!lo) hi++;
907 else lo = ~lo + 1;
908 }
909}
910
911void multu64(uint64_t m1,uint64_t m2)
912{
913 unsigned long long int op1, op2, op3, op4;
914 unsigned long long int result1, result2, result3, result4;
915 unsigned long long int temp1, temp2, temp3, temp4;
916
917 op1 = m1 & 0xFFFFFFFF;
918 op2 = (m1 >> 32) & 0xFFFFFFFF;
919 op3 = m2 & 0xFFFFFFFF;
920 op4 = (m2 >> 32) & 0xFFFFFFFF;
921
922 temp1 = op1 * op3;
923 temp2 = (temp1 >> 32) + op1 * op4;
924 temp3 = op2 * op3;
925 temp4 = (temp3 >> 32) + op2 * op4;
926
927 result1 = temp1 & 0xFFFFFFFF;
928 result2 = temp2 + (temp3 & 0xFFFFFFFF);
929 result3 = (result2 >> 32) + temp4;
930 result4 = (result3 >> 32);
931
932 lo = result1 | (result2 << 32);
933 hi = (result3 & 0xFFFFFFFF) | (result4 << 32);
934
935 //printf("TRACE: dmultu %8x%8x %8x%8x\n",(int)reg[HIREG],(int)(reg[HIREG]>>32)
936 // ,(int)reg[LOREG],(int)(reg[LOREG]>>32));
937}
938
939uint64_t ldl_merge(uint64_t original,uint64_t loaded,u_int bits)
940{
941 if(bits) {
942 original<<=64-bits;
943 original>>=64-bits;
944 loaded<<=bits;
945 original|=loaded;
946 }
947 else original=loaded;
948 return original;
949}
950uint64_t ldr_merge(uint64_t original,uint64_t loaded,u_int bits)
951{
952 if(bits^56) {
953 original>>=64-(bits^56);
954 original<<=64-(bits^56);
955 loaded>>=bits^56;
956 original|=loaded;
957 }
958 else original=loaded;
959 return original;
960}
4600ba03 961#endif
57871462 962
963#ifdef __i386__
964#include "assem_x86.c"
965#endif
966#ifdef __x86_64__
967#include "assem_x64.c"
968#endif
969#ifdef __arm__
970#include "assem_arm.c"
971#endif
972
973// Add virtual address mapping to linked list
974void ll_add(struct ll_entry **head,int vaddr,void *addr)
975{
976 struct ll_entry *new_entry;
977 new_entry=malloc(sizeof(struct ll_entry));
978 assert(new_entry!=NULL);
979 new_entry->vaddr=vaddr;
980 new_entry->reg32=0;
981 new_entry->addr=addr;
982 new_entry->next=*head;
983 *head=new_entry;
984}
985
986// Add virtual address mapping for 32-bit compiled block
987void ll_add_32(struct ll_entry **head,int vaddr,u_int reg32,void *addr)
988{
7139f3c8 989 ll_add(head,vaddr,addr);
990#ifndef FORCE32
991 (*head)->reg32=reg32;
992#endif
57871462 993}
994
995// Check if an address is already compiled
996// but don't return addresses which are about to expire from the cache
997void *check_addr(u_int vaddr)
998{
999 u_int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
1000 if(ht_bin[0]==vaddr) {
1001 if(((ht_bin[1]-MAX_OUTPUT_BLOCK_SIZE-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
1002 if(isclean(ht_bin[1])) return (void *)ht_bin[1];
1003 }
1004 if(ht_bin[2]==vaddr) {
1005 if(((ht_bin[3]-MAX_OUTPUT_BLOCK_SIZE-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
1006 if(isclean(ht_bin[3])) return (void *)ht_bin[3];
1007 }
94d23bb9 1008 u_int page=get_page(vaddr);
57871462 1009 struct ll_entry *head;
1010 head=jump_in[page];
1011 while(head!=NULL) {
1012 if(head->vaddr==vaddr&&head->reg32==0) {
1013 if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2))) {
1014 // Update existing entry with current address
1015 if(ht_bin[0]==vaddr) {
1016 ht_bin[1]=(int)head->addr;
1017 return head->addr;
1018 }
1019 if(ht_bin[2]==vaddr) {
1020 ht_bin[3]=(int)head->addr;
1021 return head->addr;
1022 }
1023 // Insert into hash table with low priority.
1024 // Don't evict existing entries, as they are probably
1025 // addresses that are being accessed frequently.
1026 if(ht_bin[0]==-1) {
1027 ht_bin[1]=(int)head->addr;
1028 ht_bin[0]=vaddr;
1029 }else if(ht_bin[2]==-1) {
1030 ht_bin[3]=(int)head->addr;
1031 ht_bin[2]=vaddr;
1032 }
1033 return head->addr;
1034 }
1035 }
1036 head=head->next;
1037 }
1038 return 0;
1039}
1040
1041void remove_hash(int vaddr)
1042{
1043 //printf("remove hash: %x\n",vaddr);
1044 int *ht_bin=hash_table[(((vaddr)>>16)^vaddr)&0xFFFF];
1045 if(ht_bin[2]==vaddr) {
1046 ht_bin[2]=ht_bin[3]=-1;
1047 }
1048 if(ht_bin[0]==vaddr) {
1049 ht_bin[0]=ht_bin[2];
1050 ht_bin[1]=ht_bin[3];
1051 ht_bin[2]=ht_bin[3]=-1;
1052 }
1053}
1054
1055void ll_remove_matching_addrs(struct ll_entry **head,int addr,int shift)
1056{
1057 struct ll_entry *next;
1058 while(*head) {
1059 if(((u_int)((*head)->addr)>>shift)==(addr>>shift) ||
1060 ((u_int)((*head)->addr-MAX_OUTPUT_BLOCK_SIZE)>>shift)==(addr>>shift))
1061 {
1062 inv_debug("EXP: Remove pointer to %x (%x)\n",(int)(*head)->addr,(*head)->vaddr);
1063 remove_hash((*head)->vaddr);
1064 next=(*head)->next;
1065 free(*head);
1066 *head=next;
1067 }
1068 else
1069 {
1070 head=&((*head)->next);
1071 }
1072 }
1073}
1074
1075// Remove all entries from linked list
1076void ll_clear(struct ll_entry **head)
1077{
1078 struct ll_entry *cur;
1079 struct ll_entry *next;
1080 if(cur=*head) {
1081 *head=0;
1082 while(cur) {
1083 next=cur->next;
1084 free(cur);
1085 cur=next;
1086 }
1087 }
1088}
1089
1090// Dereference the pointers and remove if it matches
1091void ll_kill_pointers(struct ll_entry *head,int addr,int shift)
1092{
1093 while(head) {
1094 int ptr=get_pointer(head->addr);
1095 inv_debug("EXP: Lookup pointer to %x at %x (%x)\n",(int)ptr,(int)head->addr,head->vaddr);
1096 if(((ptr>>shift)==(addr>>shift)) ||
1097 (((ptr-MAX_OUTPUT_BLOCK_SIZE)>>shift)==(addr>>shift)))
1098 {
5088bb70 1099 inv_debug("EXP: Kill pointer at %x (%x)\n",(int)head->addr,head->vaddr);
f76eeef9 1100 u_int host_addr=(u_int)kill_pointer(head->addr);
dd3a91a1 1101 #ifdef __arm__
1102 needs_clear_cache[(host_addr-(u_int)BASE_ADDR)>>17]|=1<<(((host_addr-(u_int)BASE_ADDR)>>12)&31);
1103 #endif
57871462 1104 }
1105 head=head->next;
1106 }
1107}
1108
1109// This is called when we write to a compiled block (see do_invstub)
f76eeef9 1110void invalidate_page(u_int page)
57871462 1111{
57871462 1112 struct ll_entry *head;
1113 struct ll_entry *next;
1114 head=jump_in[page];
1115 jump_in[page]=0;
1116 while(head!=NULL) {
1117 inv_debug("INVALIDATE: %x\n",head->vaddr);
1118 remove_hash(head->vaddr);
1119 next=head->next;
1120 free(head);
1121 head=next;
1122 }
1123 head=jump_out[page];
1124 jump_out[page]=0;
1125 while(head!=NULL) {
1126 inv_debug("INVALIDATE: kill pointer to %x (%x)\n",head->vaddr,(int)head->addr);
f76eeef9 1127 u_int host_addr=(u_int)kill_pointer(head->addr);
dd3a91a1 1128 #ifdef __arm__
1129 needs_clear_cache[(host_addr-(u_int)BASE_ADDR)>>17]|=1<<(((host_addr-(u_int)BASE_ADDR)>>12)&31);
1130 #endif
57871462 1131 next=head->next;
1132 free(head);
1133 head=next;
1134 }
57871462 1135}
9be4ba64 1136
1137static void invalidate_block_range(u_int block, u_int first, u_int last)
57871462 1138{
94d23bb9 1139 u_int page=get_page(block<<12);
57871462 1140 //printf("first=%d last=%d\n",first,last);
f76eeef9 1141 invalidate_page(page);
57871462 1142 assert(first+5>page); // NB: this assumes MAXBLOCK<=4096 (4 pages)
1143 assert(last<page+5);
1144 // Invalidate the adjacent pages if a block crosses a 4K boundary
1145 while(first<page) {
1146 invalidate_page(first);
1147 first++;
1148 }
1149 for(first=page+1;first<last;first++) {
1150 invalidate_page(first);
1151 }
dd3a91a1 1152 #ifdef __arm__
1153 do_clear_cache();
1154 #endif
57871462 1155
1156 // Don't trap writes
1157 invalid_code[block]=1;
94d23bb9 1158#ifndef DISABLE_TLB
57871462 1159 // If there is a valid TLB entry for this page, remove write protect
1160 if(tlb_LUT_w[block]) {
1161 assert(tlb_LUT_r[block]==tlb_LUT_w[block]);
1162 // CHECK: Is this right?
1163 memory_map[block]=((tlb_LUT_w[block]&0xFFFFF000)-(block<<12)+(unsigned int)rdram-0x80000000)>>2;
1164 u_int real_block=tlb_LUT_w[block]>>12;
1165 invalid_code[real_block]=1;
1166 if(real_block>=0x80000&&real_block<0x80800) memory_map[real_block]=((u_int)rdram-0x80000000)>>2;
1167 }
1168 else if(block>=0x80000&&block<0x80800) memory_map[block]=((u_int)rdram-0x80000000)>>2;
94d23bb9 1169#endif
f76eeef9 1170
57871462 1171 #ifdef USE_MINI_HT
1172 memset(mini_ht,-1,sizeof(mini_ht));
1173 #endif
1174}
9be4ba64 1175
1176void invalidate_block(u_int block)
1177{
1178 u_int page=get_page(block<<12);
1179 u_int vpage=get_vpage(block<<12);
1180 inv_debug("INVALIDATE: %x (%d)\n",block<<12,page);
1181 //inv_debug("invalid_code[block]=%d\n",invalid_code[block]);
1182 u_int first,last;
1183 first=last=page;
1184 struct ll_entry *head;
1185 head=jump_dirty[vpage];
1186 //printf("page=%d vpage=%d\n",page,vpage);
1187 while(head!=NULL) {
1188 u_int start,end;
1189 if(vpage>2047||(head->vaddr>>12)==block) { // Ignore vaddr hash collision
1190 get_bounds((int)head->addr,&start,&end);
1191 //printf("start: %x end: %x\n",start,end);
1192 if(page<2048&&start>=0x80000000&&end<0x80000000+RAM_SIZE) {
1193 if(((start-(u_int)rdram)>>12)<=page&&((end-1-(u_int)rdram)>>12)>=page) {
1194 if((((start-(u_int)rdram)>>12)&2047)<first) first=((start-(u_int)rdram)>>12)&2047;
1195 if((((end-1-(u_int)rdram)>>12)&2047)>last) last=((end-1-(u_int)rdram)>>12)&2047;
1196 }
1197 }
1198#ifndef DISABLE_TLB
1199 if(page<2048&&(signed int)start>=(signed int)0xC0000000&&(signed int)end>=(signed int)0xC0000000) {
1200 if(((start+memory_map[start>>12]-(u_int)rdram)>>12)<=page&&((end-1+memory_map[(end-1)>>12]-(u_int)rdram)>>12)>=page) {
1201 if((((start+memory_map[start>>12]-(u_int)rdram)>>12)&2047)<first) first=((start+memory_map[start>>12]-(u_int)rdram)>>12)&2047;
1202 if((((end-1+memory_map[(end-1)>>12]-(u_int)rdram)>>12)&2047)>last) last=((end-1+memory_map[(end-1)>>12]-(u_int)rdram)>>12)&2047;
1203 }
1204 }
1205#endif
1206 }
1207 head=head->next;
1208 }
1209 invalidate_block_range(block,first,last);
1210}
1211
57871462 1212void invalidate_addr(u_int addr)
1213{
9be4ba64 1214#ifdef PCSX
1215 //static int rhits;
1216 // this check is done by the caller
1217 //if (inv_code_start<=addr&&addr<=inv_code_end) { rhits++; return; }
1218 u_int page=get_page(addr);
1219 if(page<2048) { // RAM
1220 struct ll_entry *head;
1221 u_int addr_min=~0, addr_max=0;
1222 int mask=RAM_SIZE-1;
1223 int pg1;
1224 inv_code_start=addr&~0xfff;
1225 inv_code_end=addr|0xfff;
1226 pg1=page;
1227 if (pg1>0) {
1228 // must check previous page too because of spans..
1229 pg1--;
1230 inv_code_start-=0x1000;
1231 }
1232 for(;pg1<=page;pg1++) {
1233 for(head=jump_dirty[pg1];head!=NULL;head=head->next) {
1234 u_int start,end;
1235 get_bounds((int)head->addr,&start,&end);
1236 if((start&mask)<=(addr&mask)&&(addr&mask)<(end&mask)) {
1237 if(start<addr_min) addr_min=start;
1238 if(end>addr_max) addr_max=end;
1239 }
1240 else if(addr<start) {
1241 if(start<inv_code_end)
1242 inv_code_end=start-1;
1243 }
1244 else {
1245 if(end>inv_code_start)
1246 inv_code_start=end;
1247 }
1248 }
1249 }
1250 if (addr_min!=~0) {
1251 inv_debug("INV ADDR: %08x hit %08x-%08x\n", addr, addr_min, addr_max);
1252 inv_code_start=inv_code_end=~0;
1253 invalidate_block_range(addr>>12,(addr_min&mask)>>12,(addr_max&mask)>>12);
1254 return;
1255 }
1256 else {
1257 inv_debug("INV ADDR: %08x miss, inv %08x-%08x, sk %d\n", addr, inv_code_start, inv_code_end, 0);//rhits);
1258 }
1259 //rhits=0;
1260 if(page!=0) // FIXME: don't know what's up with page 0 (Klonoa)
1261 return;
1262 }
1263#endif
57871462 1264 invalidate_block(addr>>12);
1265}
9be4ba64 1266
dd3a91a1 1267// This is called when loading a save state.
1268// Anything could have changed, so invalidate everything.
57871462 1269void invalidate_all_pages()
1270{
1271 u_int page,n;
1272 for(page=0;page<4096;page++)
1273 invalidate_page(page);
1274 for(page=0;page<1048576;page++)
1275 if(!invalid_code[page]) {
1276 restore_candidate[(page&2047)>>3]|=1<<(page&7);
1277 restore_candidate[((page&2047)>>3)+256]|=1<<(page&7);
1278 }
1279 #ifdef __arm__
1280 __clear_cache((void *)BASE_ADDR,(void *)BASE_ADDR+(1<<TARGET_SIZE_2));
1281 #endif
1282 #ifdef USE_MINI_HT
1283 memset(mini_ht,-1,sizeof(mini_ht));
1284 #endif
94d23bb9 1285 #ifndef DISABLE_TLB
57871462 1286 // TLB
1287 for(page=0;page<0x100000;page++) {
1288 if(tlb_LUT_r[page]) {
1289 memory_map[page]=((tlb_LUT_r[page]&0xFFFFF000)-(page<<12)+(unsigned int)rdram-0x80000000)>>2;
1290 if(!tlb_LUT_w[page]||!invalid_code[page])
1291 memory_map[page]|=0x40000000; // Write protect
1292 }
1293 else memory_map[page]=-1;
1294 if(page==0x80000) page=0xC0000;
1295 }
1296 tlb_hacks();
94d23bb9 1297 #endif
57871462 1298}
1299
1300// Add an entry to jump_out after making a link
1301void add_link(u_int vaddr,void *src)
1302{
94d23bb9 1303 u_int page=get_page(vaddr);
57871462 1304 inv_debug("add_link: %x -> %x (%d)\n",(int)src,vaddr,page);
76f71c27 1305 int *ptr=(int *)(src+4);
1306 assert((*ptr&0x0fff0000)==0x059f0000);
57871462 1307 ll_add(jump_out+page,vaddr,src);
1308 //int ptr=get_pointer(src);
1309 //inv_debug("add_link: Pointer is to %x\n",(int)ptr);
1310}
1311
1312// If a code block was found to be unmodified (bit was set in
1313// restore_candidate) and it remains unmodified (bit is clear
1314// in invalid_code) then move the entries for that 4K page from
1315// the dirty list to the clean list.
1316void clean_blocks(u_int page)
1317{
1318 struct ll_entry *head;
1319 inv_debug("INV: clean_blocks page=%d\n",page);
1320 head=jump_dirty[page];
1321 while(head!=NULL) {
1322 if(!invalid_code[head->vaddr>>12]) {
1323 // Don't restore blocks which are about to expire from the cache
1324 if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2))) {
1325 u_int start,end;
1326 if(verify_dirty((int)head->addr)) {
1327 //printf("Possibly Restore %x (%x)\n",head->vaddr, (int)head->addr);
1328 u_int i;
1329 u_int inv=0;
1330 get_bounds((int)head->addr,&start,&end);
4cb76aa4 1331 if(start-(u_int)rdram<RAM_SIZE) {
57871462 1332 for(i=(start-(u_int)rdram+0x80000000)>>12;i<=(end-1-(u_int)rdram+0x80000000)>>12;i++) {
1333 inv|=invalid_code[i];
1334 }
1335 }
1336 if((signed int)head->vaddr>=(signed int)0xC0000000) {
1337 u_int addr = (head->vaddr+(memory_map[head->vaddr>>12]<<2));
1338 //printf("addr=%x start=%x end=%x\n",addr,start,end);
1339 if(addr<start||addr>=end) inv=1;
1340 }
4cb76aa4 1341 else if((signed int)head->vaddr>=(signed int)0x80000000+RAM_SIZE) {
57871462 1342 inv=1;
1343 }
1344 if(!inv) {
1345 void * clean_addr=(void *)get_clean_addr((int)head->addr);
1346 if((((u_int)clean_addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2))) {
1347 u_int ppage=page;
94d23bb9 1348#ifndef DISABLE_TLB
57871462 1349 if(page<2048&&tlb_LUT_r[head->vaddr>>12]) ppage=(tlb_LUT_r[head->vaddr>>12]^0x80000000)>>12;
94d23bb9 1350#endif
57871462 1351 inv_debug("INV: Restored %x (%x/%x)\n",head->vaddr, (int)head->addr, (int)clean_addr);
1352 //printf("page=%x, addr=%x\n",page,head->vaddr);
1353 //assert(head->vaddr>>12==(page|0x80000));
1354 ll_add_32(jump_in+ppage,head->vaddr,head->reg32,clean_addr);
1355 int *ht_bin=hash_table[((head->vaddr>>16)^head->vaddr)&0xFFFF];
1356 if(!head->reg32) {
1357 if(ht_bin[0]==head->vaddr) {
1358 ht_bin[1]=(int)clean_addr; // Replace existing entry
1359 }
1360 if(ht_bin[2]==head->vaddr) {
1361 ht_bin[3]=(int)clean_addr; // Replace existing entry
1362 }
1363 }
1364 }
1365 }
1366 }
1367 }
1368 }
1369 head=head->next;
1370 }
1371}
1372
1373
1374void mov_alloc(struct regstat *current,int i)
1375{
1376 // Note: Don't need to actually alloc the source registers
1377 if((~current->is32>>rs1[i])&1) {
1378 //alloc_reg64(current,i,rs1[i]);
1379 alloc_reg64(current,i,rt1[i]);
1380 current->is32&=~(1LL<<rt1[i]);
1381 } else {
1382 //alloc_reg(current,i,rs1[i]);
1383 alloc_reg(current,i,rt1[i]);
1384 current->is32|=(1LL<<rt1[i]);
1385 }
1386 clear_const(current,rs1[i]);
1387 clear_const(current,rt1[i]);
1388 dirty_reg(current,rt1[i]);
1389}
1390
1391void shiftimm_alloc(struct regstat *current,int i)
1392{
1393 clear_const(current,rs1[i]);
1394 clear_const(current,rt1[i]);
1395 if(opcode2[i]<=0x3) // SLL/SRL/SRA
1396 {
1397 if(rt1[i]) {
1398 if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1399 else lt1[i]=rs1[i];
1400 alloc_reg(current,i,rt1[i]);
1401 current->is32|=1LL<<rt1[i];
1402 dirty_reg(current,rt1[i]);
1403 }
1404 }
1405 if(opcode2[i]>=0x38&&opcode2[i]<=0x3b) // DSLL/DSRL/DSRA
1406 {
1407 if(rt1[i]) {
1408 if(rs1[i]) alloc_reg64(current,i,rs1[i]);
1409 alloc_reg64(current,i,rt1[i]);
1410 current->is32&=~(1LL<<rt1[i]);
1411 dirty_reg(current,rt1[i]);
1412 }
1413 }
1414 if(opcode2[i]==0x3c) // DSLL32
1415 {
1416 if(rt1[i]) {
1417 if(rs1[i]) alloc_reg(current,i,rs1[i]);
1418 alloc_reg64(current,i,rt1[i]);
1419 current->is32&=~(1LL<<rt1[i]);
1420 dirty_reg(current,rt1[i]);
1421 }
1422 }
1423 if(opcode2[i]==0x3e) // DSRL32
1424 {
1425 if(rt1[i]) {
1426 alloc_reg64(current,i,rs1[i]);
1427 if(imm[i]==32) {
1428 alloc_reg64(current,i,rt1[i]);
1429 current->is32&=~(1LL<<rt1[i]);
1430 } else {
1431 alloc_reg(current,i,rt1[i]);
1432 current->is32|=1LL<<rt1[i];
1433 }
1434 dirty_reg(current,rt1[i]);
1435 }
1436 }
1437 if(opcode2[i]==0x3f) // DSRA32
1438 {
1439 if(rt1[i]) {
1440 alloc_reg64(current,i,rs1[i]);
1441 alloc_reg(current,i,rt1[i]);
1442 current->is32|=1LL<<rt1[i];
1443 dirty_reg(current,rt1[i]);
1444 }
1445 }
1446}
1447
1448void shift_alloc(struct regstat *current,int i)
1449{
1450 if(rt1[i]) {
1451 if(opcode2[i]<=0x07) // SLLV/SRLV/SRAV
1452 {
1453 if(rs1[i]) alloc_reg(current,i,rs1[i]);
1454 if(rs2[i]) alloc_reg(current,i,rs2[i]);
1455 alloc_reg(current,i,rt1[i]);
e1190b87 1456 if(rt1[i]==rs2[i]) {
1457 alloc_reg_temp(current,i,-1);
1458 minimum_free_regs[i]=1;
1459 }
57871462 1460 current->is32|=1LL<<rt1[i];
1461 } else { // DSLLV/DSRLV/DSRAV
1462 if(rs1[i]) alloc_reg64(current,i,rs1[i]);
1463 if(rs2[i]) alloc_reg(current,i,rs2[i]);
1464 alloc_reg64(current,i,rt1[i]);
1465 current->is32&=~(1LL<<rt1[i]);
1466 if(opcode2[i]==0x16||opcode2[i]==0x17) // DSRLV and DSRAV need a temporary register
e1190b87 1467 {
57871462 1468 alloc_reg_temp(current,i,-1);
e1190b87 1469 minimum_free_regs[i]=1;
1470 }
57871462 1471 }
1472 clear_const(current,rs1[i]);
1473 clear_const(current,rs2[i]);
1474 clear_const(current,rt1[i]);
1475 dirty_reg(current,rt1[i]);
1476 }
1477}
1478
1479void alu_alloc(struct regstat *current,int i)
1480{
1481 if(opcode2[i]>=0x20&&opcode2[i]<=0x23) { // ADD/ADDU/SUB/SUBU
1482 if(rt1[i]) {
1483 if(rs1[i]&&rs2[i]) {
1484 alloc_reg(current,i,rs1[i]);
1485 alloc_reg(current,i,rs2[i]);
1486 }
1487 else {
1488 if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1489 if(rs2[i]&&needed_again(rs2[i],i)) alloc_reg(current,i,rs2[i]);
1490 }
1491 alloc_reg(current,i,rt1[i]);
1492 }
1493 current->is32|=1LL<<rt1[i];
1494 }
1495 if(opcode2[i]==0x2a||opcode2[i]==0x2b) { // SLT/SLTU
1496 if(rt1[i]) {
1497 if(!((current->is32>>rs1[i])&(current->is32>>rs2[i])&1))
1498 {
1499 alloc_reg64(current,i,rs1[i]);
1500 alloc_reg64(current,i,rs2[i]);
1501 alloc_reg(current,i,rt1[i]);
1502 } else {
1503 alloc_reg(current,i,rs1[i]);
1504 alloc_reg(current,i,rs2[i]);
1505 alloc_reg(current,i,rt1[i]);
1506 }
1507 }
1508 current->is32|=1LL<<rt1[i];
1509 }
1510 if(opcode2[i]>=0x24&&opcode2[i]<=0x27) { // AND/OR/XOR/NOR
1511 if(rt1[i]) {
1512 if(rs1[i]&&rs2[i]) {
1513 alloc_reg(current,i,rs1[i]);
1514 alloc_reg(current,i,rs2[i]);
1515 }
1516 else
1517 {
1518 if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1519 if(rs2[i]&&needed_again(rs2[i],i)) alloc_reg(current,i,rs2[i]);
1520 }
1521 alloc_reg(current,i,rt1[i]);
1522 if(!((current->is32>>rs1[i])&(current->is32>>rs2[i])&1))
1523 {
1524 if(!((current->uu>>rt1[i])&1)) {
1525 alloc_reg64(current,i,rt1[i]);
1526 }
1527 if(get_reg(current->regmap,rt1[i]|64)>=0) {
1528 if(rs1[i]&&rs2[i]) {
1529 alloc_reg64(current,i,rs1[i]);
1530 alloc_reg64(current,i,rs2[i]);
1531 }
1532 else
1533 {
1534 // Is is really worth it to keep 64-bit values in registers?
1535 #ifdef NATIVE_64BIT
1536 if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg64(current,i,rs1[i]);
1537 if(rs2[i]&&needed_again(rs2[i],i)) alloc_reg64(current,i,rs2[i]);
1538 #endif
1539 }
1540 }
1541 current->is32&=~(1LL<<rt1[i]);
1542 } else {
1543 current->is32|=1LL<<rt1[i];
1544 }
1545 }
1546 }
1547 if(opcode2[i]>=0x2c&&opcode2[i]<=0x2f) { // DADD/DADDU/DSUB/DSUBU
1548 if(rt1[i]) {
1549 if(rs1[i]&&rs2[i]) {
1550 if(!((current->uu>>rt1[i])&1)||get_reg(current->regmap,rt1[i]|64)>=0) {
1551 alloc_reg64(current,i,rs1[i]);
1552 alloc_reg64(current,i,rs2[i]);
1553 alloc_reg64(current,i,rt1[i]);
1554 } else {
1555 alloc_reg(current,i,rs1[i]);
1556 alloc_reg(current,i,rs2[i]);
1557 alloc_reg(current,i,rt1[i]);
1558 }
1559 }
1560 else {
1561 alloc_reg(current,i,rt1[i]);
1562 if(!((current->uu>>rt1[i])&1)||get_reg(current->regmap,rt1[i]|64)>=0) {
1563 // DADD used as move, or zeroing
1564 // If we have a 64-bit source, then make the target 64 bits too
1565 if(rs1[i]&&!((current->is32>>rs1[i])&1)) {
1566 if(get_reg(current->regmap,rs1[i])>=0) alloc_reg64(current,i,rs1[i]);
1567 alloc_reg64(current,i,rt1[i]);
1568 } else if(rs2[i]&&!((current->is32>>rs2[i])&1)) {
1569 if(get_reg(current->regmap,rs2[i])>=0) alloc_reg64(current,i,rs2[i]);
1570 alloc_reg64(current,i,rt1[i]);
1571 }
1572 if(opcode2[i]>=0x2e&&rs2[i]) {
1573 // DSUB used as negation - 64-bit result
1574 // If we have a 32-bit register, extend it to 64 bits
1575 if(get_reg(current->regmap,rs2[i])>=0) alloc_reg64(current,i,rs2[i]);
1576 alloc_reg64(current,i,rt1[i]);
1577 }
1578 }
1579 }
1580 if(rs1[i]&&rs2[i]) {
1581 current->is32&=~(1LL<<rt1[i]);
1582 } else if(rs1[i]) {
1583 current->is32&=~(1LL<<rt1[i]);
1584 if((current->is32>>rs1[i])&1)
1585 current->is32|=1LL<<rt1[i];
1586 } else if(rs2[i]) {
1587 current->is32&=~(1LL<<rt1[i]);
1588 if((current->is32>>rs2[i])&1)
1589 current->is32|=1LL<<rt1[i];
1590 } else {
1591 current->is32|=1LL<<rt1[i];
1592 }
1593 }
1594 }
1595 clear_const(current,rs1[i]);
1596 clear_const(current,rs2[i]);
1597 clear_const(current,rt1[i]);
1598 dirty_reg(current,rt1[i]);
1599}
1600
1601void imm16_alloc(struct regstat *current,int i)
1602{
1603 if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1604 else lt1[i]=rs1[i];
1605 if(rt1[i]) alloc_reg(current,i,rt1[i]);
1606 if(opcode[i]==0x18||opcode[i]==0x19) { // DADDI/DADDIU
1607 current->is32&=~(1LL<<rt1[i]);
1608 if(!((current->uu>>rt1[i])&1)||get_reg(current->regmap,rt1[i]|64)>=0) {
1609 // TODO: Could preserve the 32-bit flag if the immediate is zero
1610 alloc_reg64(current,i,rt1[i]);
1611 alloc_reg64(current,i,rs1[i]);
1612 }
1613 clear_const(current,rs1[i]);
1614 clear_const(current,rt1[i]);
1615 }
1616 else if(opcode[i]==0x0a||opcode[i]==0x0b) { // SLTI/SLTIU
1617 if((~current->is32>>rs1[i])&1) alloc_reg64(current,i,rs1[i]);
1618 current->is32|=1LL<<rt1[i];
1619 clear_const(current,rs1[i]);
1620 clear_const(current,rt1[i]);
1621 }
1622 else if(opcode[i]>=0x0c&&opcode[i]<=0x0e) { // ANDI/ORI/XORI
1623 if(((~current->is32>>rs1[i])&1)&&opcode[i]>0x0c) {
1624 if(rs1[i]!=rt1[i]) {
1625 if(needed_again(rs1[i],i)) alloc_reg64(current,i,rs1[i]);
1626 alloc_reg64(current,i,rt1[i]);
1627 current->is32&=~(1LL<<rt1[i]);
1628 }
1629 }
1630 else current->is32|=1LL<<rt1[i]; // ANDI clears upper bits
1631 if(is_const(current,rs1[i])) {
1632 int v=get_const(current,rs1[i]);
1633 if(opcode[i]==0x0c) set_const(current,rt1[i],v&imm[i]);
1634 if(opcode[i]==0x0d) set_const(current,rt1[i],v|imm[i]);
1635 if(opcode[i]==0x0e) set_const(current,rt1[i],v^imm[i]);
1636 }
1637 else clear_const(current,rt1[i]);
1638 }
1639 else if(opcode[i]==0x08||opcode[i]==0x09) { // ADDI/ADDIU
1640 if(is_const(current,rs1[i])) {
1641 int v=get_const(current,rs1[i]);
1642 set_const(current,rt1[i],v+imm[i]);
1643 }
1644 else clear_const(current,rt1[i]);
1645 current->is32|=1LL<<rt1[i];
1646 }
1647 else {
1648 set_const(current,rt1[i],((long long)((short)imm[i]))<<16); // LUI
1649 current->is32|=1LL<<rt1[i];
1650 }
1651 dirty_reg(current,rt1[i]);
1652}
1653
1654void load_alloc(struct regstat *current,int i)
1655{
1656 clear_const(current,rt1[i]);
1657 //if(rs1[i]!=rt1[i]&&needed_again(rs1[i],i)) clear_const(current,rs1[i]); // Does this help or hurt?
1658 if(!rs1[i]) current->u&=~1LL; // Allow allocating r0 if it's the source register
1659 if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
373d1d07 1660 if(rt1[i]&&!((current->u>>rt1[i])&1)) {
57871462 1661 alloc_reg(current,i,rt1[i]);
373d1d07 1662 assert(get_reg(current->regmap,rt1[i])>=0);
57871462 1663 if(opcode[i]==0x27||opcode[i]==0x37) // LWU/LD
1664 {
1665 current->is32&=~(1LL<<rt1[i]);
1666 alloc_reg64(current,i,rt1[i]);
1667 }
1668 else if(opcode[i]==0x1A||opcode[i]==0x1B) // LDL/LDR
1669 {
1670 current->is32&=~(1LL<<rt1[i]);
1671 alloc_reg64(current,i,rt1[i]);
1672 alloc_all(current,i);
1673 alloc_reg64(current,i,FTEMP);
e1190b87 1674 minimum_free_regs[i]=HOST_REGS;
57871462 1675 }
1676 else current->is32|=1LL<<rt1[i];
1677 dirty_reg(current,rt1[i]);
1678 // If using TLB, need a register for pointer to the mapping table
1679 if(using_tlb) alloc_reg(current,i,TLREG);
1680 // LWL/LWR need a temporary register for the old value
1681 if(opcode[i]==0x22||opcode[i]==0x26)
1682 {
1683 alloc_reg(current,i,FTEMP);
1684 alloc_reg_temp(current,i,-1);
e1190b87 1685 minimum_free_regs[i]=1;
57871462 1686 }
1687 }
1688 else
1689 {
373d1d07 1690 // Load to r0 or unneeded register (dummy load)
57871462 1691 // but we still need a register to calculate the address
535d208a 1692 if(opcode[i]==0x22||opcode[i]==0x26)
1693 {
1694 alloc_reg(current,i,FTEMP); // LWL/LWR need another temporary
1695 }
373d1d07 1696 // If using TLB, need a register for pointer to the mapping table
1697 if(using_tlb) alloc_reg(current,i,TLREG);
57871462 1698 alloc_reg_temp(current,i,-1);
e1190b87 1699 minimum_free_regs[i]=1;
535d208a 1700 if(opcode[i]==0x1A||opcode[i]==0x1B) // LDL/LDR
1701 {
1702 alloc_all(current,i);
1703 alloc_reg64(current,i,FTEMP);
e1190b87 1704 minimum_free_regs[i]=HOST_REGS;
535d208a 1705 }
57871462 1706 }
1707}
1708
1709void store_alloc(struct regstat *current,int i)
1710{
1711 clear_const(current,rs2[i]);
1712 if(!(rs2[i])) current->u&=~1LL; // Allow allocating r0 if necessary
1713 if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1714 alloc_reg(current,i,rs2[i]);
1715 if(opcode[i]==0x2c||opcode[i]==0x2d||opcode[i]==0x3f) { // 64-bit SDL/SDR/SD
1716 alloc_reg64(current,i,rs2[i]);
1717 if(rs2[i]) alloc_reg(current,i,FTEMP);
1718 }
1719 // If using TLB, need a register for pointer to the mapping table
1720 if(using_tlb) alloc_reg(current,i,TLREG);
1721 #if defined(HOST_IMM8)
1722 // On CPUs without 32-bit immediates we need a pointer to invalid_code
1723 else alloc_reg(current,i,INVCP);
1724 #endif
b7918751 1725 if(opcode[i]==0x2a||opcode[i]==0x2e||opcode[i]==0x2c||opcode[i]==0x2d) { // SWL/SWL/SDL/SDR
57871462 1726 alloc_reg(current,i,FTEMP);
1727 }
1728 // We need a temporary register for address generation
1729 alloc_reg_temp(current,i,-1);
e1190b87 1730 minimum_free_regs[i]=1;
57871462 1731}
1732
1733void c1ls_alloc(struct regstat *current,int i)
1734{
1735 //clear_const(current,rs1[i]); // FIXME
1736 clear_const(current,rt1[i]);
1737 if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1738 alloc_reg(current,i,CSREG); // Status
1739 alloc_reg(current,i,FTEMP);
1740 if(opcode[i]==0x35||opcode[i]==0x3d) { // 64-bit LDC1/SDC1
1741 alloc_reg64(current,i,FTEMP);
1742 }
1743 // If using TLB, need a register for pointer to the mapping table
1744 if(using_tlb) alloc_reg(current,i,TLREG);
1745 #if defined(HOST_IMM8)
1746 // On CPUs without 32-bit immediates we need a pointer to invalid_code
1747 else if((opcode[i]&0x3b)==0x39) // SWC1/SDC1
1748 alloc_reg(current,i,INVCP);
1749 #endif
1750 // We need a temporary register for address generation
1751 alloc_reg_temp(current,i,-1);
1752}
1753
b9b61529 1754void c2ls_alloc(struct regstat *current,int i)
1755{
1756 clear_const(current,rt1[i]);
1757 if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1758 alloc_reg(current,i,FTEMP);
1759 // If using TLB, need a register for pointer to the mapping table
1760 if(using_tlb) alloc_reg(current,i,TLREG);
1761 #if defined(HOST_IMM8)
1762 // On CPUs without 32-bit immediates we need a pointer to invalid_code
1763 else if((opcode[i]&0x3b)==0x3a) // SWC2/SDC2
1764 alloc_reg(current,i,INVCP);
1765 #endif
1766 // We need a temporary register for address generation
1767 alloc_reg_temp(current,i,-1);
e1190b87 1768 minimum_free_regs[i]=1;
b9b61529 1769}
1770
57871462 1771#ifndef multdiv_alloc
1772void multdiv_alloc(struct regstat *current,int i)
1773{
1774 // case 0x18: MULT
1775 // case 0x19: MULTU
1776 // case 0x1A: DIV
1777 // case 0x1B: DIVU
1778 // case 0x1C: DMULT
1779 // case 0x1D: DMULTU
1780 // case 0x1E: DDIV
1781 // case 0x1F: DDIVU
1782 clear_const(current,rs1[i]);
1783 clear_const(current,rs2[i]);
1784 if(rs1[i]&&rs2[i])
1785 {
1786 if((opcode2[i]&4)==0) // 32-bit
1787 {
1788 current->u&=~(1LL<<HIREG);
1789 current->u&=~(1LL<<LOREG);
1790 alloc_reg(current,i,HIREG);
1791 alloc_reg(current,i,LOREG);
1792 alloc_reg(current,i,rs1[i]);
1793 alloc_reg(current,i,rs2[i]);
1794 current->is32|=1LL<<HIREG;
1795 current->is32|=1LL<<LOREG;
1796 dirty_reg(current,HIREG);
1797 dirty_reg(current,LOREG);
1798 }
1799 else // 64-bit
1800 {
1801 current->u&=~(1LL<<HIREG);
1802 current->u&=~(1LL<<LOREG);
1803 current->uu&=~(1LL<<HIREG);
1804 current->uu&=~(1LL<<LOREG);
1805 alloc_reg64(current,i,HIREG);
1806 //if(HOST_REGS>10) alloc_reg64(current,i,LOREG);
1807 alloc_reg64(current,i,rs1[i]);
1808 alloc_reg64(current,i,rs2[i]);
1809 alloc_all(current,i);
1810 current->is32&=~(1LL<<HIREG);
1811 current->is32&=~(1LL<<LOREG);
1812 dirty_reg(current,HIREG);
1813 dirty_reg(current,LOREG);
e1190b87 1814 minimum_free_regs[i]=HOST_REGS;
57871462 1815 }
1816 }
1817 else
1818 {
1819 // Multiply by zero is zero.
1820 // MIPS does not have a divide by zero exception.
1821 // The result is undefined, we return zero.
1822 alloc_reg(current,i,HIREG);
1823 alloc_reg(current,i,LOREG);
1824 current->is32|=1LL<<HIREG;
1825 current->is32|=1LL<<LOREG;
1826 dirty_reg(current,HIREG);
1827 dirty_reg(current,LOREG);
1828 }
1829}
1830#endif
1831
1832void cop0_alloc(struct regstat *current,int i)
1833{
1834 if(opcode2[i]==0) // MFC0
1835 {
1836 if(rt1[i]) {
1837 clear_const(current,rt1[i]);
1838 alloc_all(current,i);
1839 alloc_reg(current,i,rt1[i]);
1840 current->is32|=1LL<<rt1[i];
1841 dirty_reg(current,rt1[i]);
1842 }
1843 }
1844 else if(opcode2[i]==4) // MTC0
1845 {
1846 if(rs1[i]){
1847 clear_const(current,rs1[i]);
1848 alloc_reg(current,i,rs1[i]);
1849 alloc_all(current,i);
1850 }
1851 else {
1852 alloc_all(current,i); // FIXME: Keep r0
1853 current->u&=~1LL;
1854 alloc_reg(current,i,0);
1855 }
1856 }
1857 else
1858 {
1859 // TLBR/TLBWI/TLBWR/TLBP/ERET
1860 assert(opcode2[i]==0x10);
1861 alloc_all(current,i);
1862 }
e1190b87 1863 minimum_free_regs[i]=HOST_REGS;
57871462 1864}
1865
1866void cop1_alloc(struct regstat *current,int i)
1867{
1868 alloc_reg(current,i,CSREG); // Load status
1869 if(opcode2[i]<3) // MFC1/DMFC1/CFC1
1870 {
7de557a6 1871 if(rt1[i]){
1872 clear_const(current,rt1[i]);
1873 if(opcode2[i]==1) {
1874 alloc_reg64(current,i,rt1[i]); // DMFC1
1875 current->is32&=~(1LL<<rt1[i]);
1876 }else{
1877 alloc_reg(current,i,rt1[i]); // MFC1/CFC1
1878 current->is32|=1LL<<rt1[i];
1879 }
1880 dirty_reg(current,rt1[i]);
57871462 1881 }
57871462 1882 alloc_reg_temp(current,i,-1);
1883 }
1884 else if(opcode2[i]>3) // MTC1/DMTC1/CTC1
1885 {
1886 if(rs1[i]){
1887 clear_const(current,rs1[i]);
1888 if(opcode2[i]==5)
1889 alloc_reg64(current,i,rs1[i]); // DMTC1
1890 else
1891 alloc_reg(current,i,rs1[i]); // MTC1/CTC1
1892 alloc_reg_temp(current,i,-1);
1893 }
1894 else {
1895 current->u&=~1LL;
1896 alloc_reg(current,i,0);
1897 alloc_reg_temp(current,i,-1);
1898 }
1899 }
e1190b87 1900 minimum_free_regs[i]=1;
57871462 1901}
1902void fconv_alloc(struct regstat *current,int i)
1903{
1904 alloc_reg(current,i,CSREG); // Load status
1905 alloc_reg_temp(current,i,-1);
e1190b87 1906 minimum_free_regs[i]=1;
57871462 1907}
1908void float_alloc(struct regstat *current,int i)
1909{
1910 alloc_reg(current,i,CSREG); // Load status
1911 alloc_reg_temp(current,i,-1);
e1190b87 1912 minimum_free_regs[i]=1;
57871462 1913}
b9b61529 1914void c2op_alloc(struct regstat *current,int i)
1915{
1916 alloc_reg_temp(current,i,-1);
1917}
57871462 1918void fcomp_alloc(struct regstat *current,int i)
1919{
1920 alloc_reg(current,i,CSREG); // Load status
1921 alloc_reg(current,i,FSREG); // Load flags
1922 dirty_reg(current,FSREG); // Flag will be modified
1923 alloc_reg_temp(current,i,-1);
e1190b87 1924 minimum_free_regs[i]=1;
57871462 1925}
1926
1927void syscall_alloc(struct regstat *current,int i)
1928{
1929 alloc_cc(current,i);
1930 dirty_reg(current,CCREG);
1931 alloc_all(current,i);
e1190b87 1932 minimum_free_regs[i]=HOST_REGS;
57871462 1933 current->isconst=0;
1934}
1935
1936void delayslot_alloc(struct regstat *current,int i)
1937{
1938 switch(itype[i]) {
1939 case UJUMP:
1940 case CJUMP:
1941 case SJUMP:
1942 case RJUMP:
1943 case FJUMP:
1944 case SYSCALL:
7139f3c8 1945 case HLECALL:
57871462 1946 case SPAN:
1947 assem_debug("jump in the delay slot. this shouldn't happen.\n");//exit(1);
1948 printf("Disabled speculative precompilation\n");
1949 stop_after_jal=1;
1950 break;
1951 case IMM16:
1952 imm16_alloc(current,i);
1953 break;
1954 case LOAD:
1955 case LOADLR:
1956 load_alloc(current,i);
1957 break;
1958 case STORE:
1959 case STORELR:
1960 store_alloc(current,i);
1961 break;
1962 case ALU:
1963 alu_alloc(current,i);
1964 break;
1965 case SHIFT:
1966 shift_alloc(current,i);
1967 break;
1968 case MULTDIV:
1969 multdiv_alloc(current,i);
1970 break;
1971 case SHIFTIMM:
1972 shiftimm_alloc(current,i);
1973 break;
1974 case MOV:
1975 mov_alloc(current,i);
1976 break;
1977 case COP0:
1978 cop0_alloc(current,i);
1979 break;
1980 case COP1:
b9b61529 1981 case COP2:
57871462 1982 cop1_alloc(current,i);
1983 break;
1984 case C1LS:
1985 c1ls_alloc(current,i);
1986 break;
b9b61529 1987 case C2LS:
1988 c2ls_alloc(current,i);
1989 break;
57871462 1990 case FCONV:
1991 fconv_alloc(current,i);
1992 break;
1993 case FLOAT:
1994 float_alloc(current,i);
1995 break;
1996 case FCOMP:
1997 fcomp_alloc(current,i);
1998 break;
b9b61529 1999 case C2OP:
2000 c2op_alloc(current,i);
2001 break;
57871462 2002 }
2003}
2004
2005// Special case where a branch and delay slot span two pages in virtual memory
2006static void pagespan_alloc(struct regstat *current,int i)
2007{
2008 current->isconst=0;
2009 current->wasconst=0;
2010 regs[i].wasconst=0;
e1190b87 2011 minimum_free_regs[i]=HOST_REGS;
57871462 2012 alloc_all(current,i);
2013 alloc_cc(current,i);
2014 dirty_reg(current,CCREG);
2015 if(opcode[i]==3) // JAL
2016 {
2017 alloc_reg(current,i,31);
2018 dirty_reg(current,31);
2019 }
2020 if(opcode[i]==0&&(opcode2[i]&0x3E)==8) // JR/JALR
2021 {
2022 alloc_reg(current,i,rs1[i]);
5067f341 2023 if (rt1[i]!=0) {
2024 alloc_reg(current,i,rt1[i]);
2025 dirty_reg(current,rt1[i]);
57871462 2026 }
2027 }
2028 if((opcode[i]&0x2E)==4) // BEQ/BNE/BEQL/BNEL
2029 {
2030 if(rs1[i]) alloc_reg(current,i,rs1[i]);
2031 if(rs2[i]) alloc_reg(current,i,rs2[i]);
2032 if(!((current->is32>>rs1[i])&(current->is32>>rs2[i])&1))
2033 {
2034 if(rs1[i]) alloc_reg64(current,i,rs1[i]);
2035 if(rs2[i]) alloc_reg64(current,i,rs2[i]);
2036 }
2037 }
2038 else
2039 if((opcode[i]&0x2E)==6) // BLEZ/BGTZ/BLEZL/BGTZL
2040 {
2041 if(rs1[i]) alloc_reg(current,i,rs1[i]);
2042 if(!((current->is32>>rs1[i])&1))
2043 {
2044 if(rs1[i]) alloc_reg64(current,i,rs1[i]);
2045 }
2046 }
2047 else
2048 if(opcode[i]==0x11) // BC1
2049 {
2050 alloc_reg(current,i,FSREG);
2051 alloc_reg(current,i,CSREG);
2052 }
2053 //else ...
2054}
2055
2056add_stub(int type,int addr,int retaddr,int a,int b,int c,int d,int e)
2057{
2058 stubs[stubcount][0]=type;
2059 stubs[stubcount][1]=addr;
2060 stubs[stubcount][2]=retaddr;
2061 stubs[stubcount][3]=a;
2062 stubs[stubcount][4]=b;
2063 stubs[stubcount][5]=c;
2064 stubs[stubcount][6]=d;
2065 stubs[stubcount][7]=e;
2066 stubcount++;
2067}
2068
2069// Write out a single register
2070void wb_register(signed char r,signed char regmap[],uint64_t dirty,uint64_t is32)
2071{
2072 int hr;
2073 for(hr=0;hr<HOST_REGS;hr++) {
2074 if(hr!=EXCLUDE_REG) {
2075 if((regmap[hr]&63)==r) {
2076 if((dirty>>hr)&1) {
2077 if(regmap[hr]<64) {
2078 emit_storereg(r,hr);
24385cae 2079#ifndef FORCE32
57871462 2080 if((is32>>regmap[hr])&1) {
2081 emit_sarimm(hr,31,hr);
2082 emit_storereg(r|64,hr);
2083 }
24385cae 2084#endif
57871462 2085 }else{
2086 emit_storereg(r|64,hr);
2087 }
2088 }
2089 }
2090 }
2091 }
2092}
2093
2094int mchecksum()
2095{
2096 //if(!tracedebug) return 0;
2097 int i;
2098 int sum=0;
2099 for(i=0;i<2097152;i++) {
2100 unsigned int temp=sum;
2101 sum<<=1;
2102 sum|=(~temp)>>31;
2103 sum^=((u_int *)rdram)[i];
2104 }
2105 return sum;
2106}
2107int rchecksum()
2108{
2109 int i;
2110 int sum=0;
2111 for(i=0;i<64;i++)
2112 sum^=((u_int *)reg)[i];
2113 return sum;
2114}
57871462 2115void rlist()
2116{
2117 int i;
2118 printf("TRACE: ");
2119 for(i=0;i<32;i++)
2120 printf("r%d:%8x%8x ",i,((int *)(reg+i))[1],((int *)(reg+i))[0]);
2121 printf("\n");
3d624f89 2122#ifndef DISABLE_COP1
57871462 2123 printf("TRACE: ");
2124 for(i=0;i<32;i++)
2125 printf("f%d:%8x%8x ",i,((int*)reg_cop1_simple[i])[1],*((int*)reg_cop1_simple[i]));
2126 printf("\n");
3d624f89 2127#endif
57871462 2128}
2129
2130void enabletrace()
2131{
2132 tracedebug=1;
2133}
2134
2135void memdebug(int i)
2136{
2137 //printf("TRACE: count=%d next=%d (checksum %x) lo=%8x%8x\n",Count,next_interupt,mchecksum(),(int)(reg[LOREG]>>32),(int)reg[LOREG]);
2138 //printf("TRACE: count=%d next=%d (rchecksum %x)\n",Count,next_interupt,rchecksum());
2139 //rlist();
2140 //if(tracedebug) {
2141 //if(Count>=-2084597794) {
2142 if((signed int)Count>=-2084597794&&(signed int)Count<0) {
2143 //if(0) {
2144 printf("TRACE: count=%d next=%d (checksum %x)\n",Count,next_interupt,mchecksum());
2145 //printf("TRACE: count=%d next=%d (checksum %x) Status=%x\n",Count,next_interupt,mchecksum(),Status);
2146 //printf("TRACE: count=%d next=%d (checksum %x) hi=%8x%8x\n",Count,next_interupt,mchecksum(),(int)(reg[HIREG]>>32),(int)reg[HIREG]);
2147 rlist();
2148 #ifdef __i386__
2149 printf("TRACE: %x\n",(&i)[-1]);
2150 #endif
2151 #ifdef __arm__
2152 int j;
2153 printf("TRACE: %x \n",(&j)[10]);
2154 printf("TRACE: %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x\n",(&j)[1],(&j)[2],(&j)[3],(&j)[4],(&j)[5],(&j)[6],(&j)[7],(&j)[8],(&j)[9],(&j)[10],(&j)[11],(&j)[12],(&j)[13],(&j)[14],(&j)[15],(&j)[16],(&j)[17],(&j)[18],(&j)[19],(&j)[20]);
2155 #endif
2156 //fflush(stdout);
2157 }
2158 //printf("TRACE: %x\n",(&i)[-1]);
2159}
2160
2161void tlb_debug(u_int cause, u_int addr, u_int iaddr)
2162{
2163 printf("TLB Exception: instruction=%x addr=%x cause=%x\n",iaddr, addr, cause);
2164}
2165
2166void alu_assemble(int i,struct regstat *i_regs)
2167{
2168 if(opcode2[i]>=0x20&&opcode2[i]<=0x23) { // ADD/ADDU/SUB/SUBU
2169 if(rt1[i]) {
2170 signed char s1,s2,t;
2171 t=get_reg(i_regs->regmap,rt1[i]);
2172 if(t>=0) {
2173 s1=get_reg(i_regs->regmap,rs1[i]);
2174 s2=get_reg(i_regs->regmap,rs2[i]);
2175 if(rs1[i]&&rs2[i]) {
2176 assert(s1>=0);
2177 assert(s2>=0);
2178 if(opcode2[i]&2) emit_sub(s1,s2,t);
2179 else emit_add(s1,s2,t);
2180 }
2181 else if(rs1[i]) {
2182 if(s1>=0) emit_mov(s1,t);
2183 else emit_loadreg(rs1[i],t);
2184 }
2185 else if(rs2[i]) {
2186 if(s2>=0) {
2187 if(opcode2[i]&2) emit_neg(s2,t);
2188 else emit_mov(s2,t);
2189 }
2190 else {
2191 emit_loadreg(rs2[i],t);
2192 if(opcode2[i]&2) emit_neg(t,t);
2193 }
2194 }
2195 else emit_zeroreg(t);
2196 }
2197 }
2198 }
2199 if(opcode2[i]>=0x2c&&opcode2[i]<=0x2f) { // DADD/DADDU/DSUB/DSUBU
2200 if(rt1[i]) {
2201 signed char s1l,s2l,s1h,s2h,tl,th;
2202 tl=get_reg(i_regs->regmap,rt1[i]);
2203 th=get_reg(i_regs->regmap,rt1[i]|64);
2204 if(tl>=0) {
2205 s1l=get_reg(i_regs->regmap,rs1[i]);
2206 s2l=get_reg(i_regs->regmap,rs2[i]);
2207 s1h=get_reg(i_regs->regmap,rs1[i]|64);
2208 s2h=get_reg(i_regs->regmap,rs2[i]|64);
2209 if(rs1[i]&&rs2[i]) {
2210 assert(s1l>=0);
2211 assert(s2l>=0);
2212 if(opcode2[i]&2) emit_subs(s1l,s2l,tl);
2213 else emit_adds(s1l,s2l,tl);
2214 if(th>=0) {
2215 #ifdef INVERTED_CARRY
2216 if(opcode2[i]&2) {if(s1h!=th) emit_mov(s1h,th);emit_sbb(th,s2h);}
2217 #else
2218 if(opcode2[i]&2) emit_sbc(s1h,s2h,th);
2219 #endif
2220 else emit_add(s1h,s2h,th);
2221 }
2222 }
2223 else if(rs1[i]) {
2224 if(s1l>=0) emit_mov(s1l,tl);
2225 else emit_loadreg(rs1[i],tl);
2226 if(th>=0) {
2227 if(s1h>=0) emit_mov(s1h,th);
2228 else emit_loadreg(rs1[i]|64,th);
2229 }
2230 }
2231 else if(rs2[i]) {
2232 if(s2l>=0) {
2233 if(opcode2[i]&2) emit_negs(s2l,tl);
2234 else emit_mov(s2l,tl);
2235 }
2236 else {
2237 emit_loadreg(rs2[i],tl);
2238 if(opcode2[i]&2) emit_negs(tl,tl);
2239 }
2240 if(th>=0) {
2241 #ifdef INVERTED_CARRY
2242 if(s2h>=0) emit_mov(s2h,th);
2243 else emit_loadreg(rs2[i]|64,th);
2244 if(opcode2[i]&2) {
2245 emit_adcimm(-1,th); // x86 has inverted carry flag
2246 emit_not(th,th);
2247 }
2248 #else
2249 if(opcode2[i]&2) {
2250 if(s2h>=0) emit_rscimm(s2h,0,th);
2251 else {
2252 emit_loadreg(rs2[i]|64,th);
2253 emit_rscimm(th,0,th);
2254 }
2255 }else{
2256 if(s2h>=0) emit_mov(s2h,th);
2257 else emit_loadreg(rs2[i]|64,th);
2258 }
2259 #endif
2260 }
2261 }
2262 else {
2263 emit_zeroreg(tl);
2264 if(th>=0) emit_zeroreg(th);
2265 }
2266 }
2267 }
2268 }
2269 if(opcode2[i]==0x2a||opcode2[i]==0x2b) { // SLT/SLTU
2270 if(rt1[i]) {
2271 signed char s1l,s1h,s2l,s2h,t;
2272 if(!((i_regs->was32>>rs1[i])&(i_regs->was32>>rs2[i])&1))
2273 {
2274 t=get_reg(i_regs->regmap,rt1[i]);
2275 //assert(t>=0);
2276 if(t>=0) {
2277 s1l=get_reg(i_regs->regmap,rs1[i]);
2278 s1h=get_reg(i_regs->regmap,rs1[i]|64);
2279 s2l=get_reg(i_regs->regmap,rs2[i]);
2280 s2h=get_reg(i_regs->regmap,rs2[i]|64);
2281 if(rs2[i]==0) // rx<r0
2282 {
2283 assert(s1h>=0);
2284 if(opcode2[i]==0x2a) // SLT
2285 emit_shrimm(s1h,31,t);
2286 else // SLTU (unsigned can not be less than zero)
2287 emit_zeroreg(t);
2288 }
2289 else if(rs1[i]==0) // r0<rx
2290 {
2291 assert(s2h>=0);
2292 if(opcode2[i]==0x2a) // SLT
2293 emit_set_gz64_32(s2h,s2l,t);
2294 else // SLTU (set if not zero)
2295 emit_set_nz64_32(s2h,s2l,t);
2296 }
2297 else {
2298 assert(s1l>=0);assert(s1h>=0);
2299 assert(s2l>=0);assert(s2h>=0);
2300 if(opcode2[i]==0x2a) // SLT
2301 emit_set_if_less64_32(s1h,s1l,s2h,s2l,t);
2302 else // SLTU
2303 emit_set_if_carry64_32(s1h,s1l,s2h,s2l,t);
2304 }
2305 }
2306 } else {
2307 t=get_reg(i_regs->regmap,rt1[i]);
2308 //assert(t>=0);
2309 if(t>=0) {
2310 s1l=get_reg(i_regs->regmap,rs1[i]);
2311 s2l=get_reg(i_regs->regmap,rs2[i]);
2312 if(rs2[i]==0) // rx<r0
2313 {
2314 assert(s1l>=0);
2315 if(opcode2[i]==0x2a) // SLT
2316 emit_shrimm(s1l,31,t);
2317 else // SLTU (unsigned can not be less than zero)
2318 emit_zeroreg(t);
2319 }
2320 else if(rs1[i]==0) // r0<rx
2321 {
2322 assert(s2l>=0);
2323 if(opcode2[i]==0x2a) // SLT
2324 emit_set_gz32(s2l,t);
2325 else // SLTU (set if not zero)
2326 emit_set_nz32(s2l,t);
2327 }
2328 else{
2329 assert(s1l>=0);assert(s2l>=0);
2330 if(opcode2[i]==0x2a) // SLT
2331 emit_set_if_less32(s1l,s2l,t);
2332 else // SLTU
2333 emit_set_if_carry32(s1l,s2l,t);
2334 }
2335 }
2336 }
2337 }
2338 }
2339 if(opcode2[i]>=0x24&&opcode2[i]<=0x27) { // AND/OR/XOR/NOR
2340 if(rt1[i]) {
2341 signed char s1l,s1h,s2l,s2h,th,tl;
2342 tl=get_reg(i_regs->regmap,rt1[i]);
2343 th=get_reg(i_regs->regmap,rt1[i]|64);
2344 if(!((i_regs->was32>>rs1[i])&(i_regs->was32>>rs2[i])&1)&&th>=0)
2345 {
2346 assert(tl>=0);
2347 if(tl>=0) {
2348 s1l=get_reg(i_regs->regmap,rs1[i]);
2349 s1h=get_reg(i_regs->regmap,rs1[i]|64);
2350 s2l=get_reg(i_regs->regmap,rs2[i]);
2351 s2h=get_reg(i_regs->regmap,rs2[i]|64);
2352 if(rs1[i]&&rs2[i]) {
2353 assert(s1l>=0);assert(s1h>=0);
2354 assert(s2l>=0);assert(s2h>=0);
2355 if(opcode2[i]==0x24) { // AND
2356 emit_and(s1l,s2l,tl);
2357 emit_and(s1h,s2h,th);
2358 } else
2359 if(opcode2[i]==0x25) { // OR
2360 emit_or(s1l,s2l,tl);
2361 emit_or(s1h,s2h,th);
2362 } else
2363 if(opcode2[i]==0x26) { // XOR
2364 emit_xor(s1l,s2l,tl);
2365 emit_xor(s1h,s2h,th);
2366 } else
2367 if(opcode2[i]==0x27) { // NOR
2368 emit_or(s1l,s2l,tl);
2369 emit_or(s1h,s2h,th);
2370 emit_not(tl,tl);
2371 emit_not(th,th);
2372 }
2373 }
2374 else
2375 {
2376 if(opcode2[i]==0x24) { // AND
2377 emit_zeroreg(tl);
2378 emit_zeroreg(th);
2379 } else
2380 if(opcode2[i]==0x25||opcode2[i]==0x26) { // OR/XOR
2381 if(rs1[i]){
2382 if(s1l>=0) emit_mov(s1l,tl);
2383 else emit_loadreg(rs1[i],tl);
2384 if(s1h>=0) emit_mov(s1h,th);
2385 else emit_loadreg(rs1[i]|64,th);
2386 }
2387 else
2388 if(rs2[i]){
2389 if(s2l>=0) emit_mov(s2l,tl);
2390 else emit_loadreg(rs2[i],tl);
2391 if(s2h>=0) emit_mov(s2h,th);
2392 else emit_loadreg(rs2[i]|64,th);
2393 }
2394 else{
2395 emit_zeroreg(tl);
2396 emit_zeroreg(th);
2397 }
2398 } else
2399 if(opcode2[i]==0x27) { // NOR
2400 if(rs1[i]){
2401 if(s1l>=0) emit_not(s1l,tl);
2402 else{
2403 emit_loadreg(rs1[i],tl);
2404 emit_not(tl,tl);
2405 }
2406 if(s1h>=0) emit_not(s1h,th);
2407 else{
2408 emit_loadreg(rs1[i]|64,th);
2409 emit_not(th,th);
2410 }
2411 }
2412 else
2413 if(rs2[i]){
2414 if(s2l>=0) emit_not(s2l,tl);
2415 else{
2416 emit_loadreg(rs2[i],tl);
2417 emit_not(tl,tl);
2418 }
2419 if(s2h>=0) emit_not(s2h,th);
2420 else{
2421 emit_loadreg(rs2[i]|64,th);
2422 emit_not(th,th);
2423 }
2424 }
2425 else {
2426 emit_movimm(-1,tl);
2427 emit_movimm(-1,th);
2428 }
2429 }
2430 }
2431 }
2432 }
2433 else
2434 {
2435 // 32 bit
2436 if(tl>=0) {
2437 s1l=get_reg(i_regs->regmap,rs1[i]);
2438 s2l=get_reg(i_regs->regmap,rs2[i]);
2439 if(rs1[i]&&rs2[i]) {
2440 assert(s1l>=0);
2441 assert(s2l>=0);
2442 if(opcode2[i]==0x24) { // AND
2443 emit_and(s1l,s2l,tl);
2444 } else
2445 if(opcode2[i]==0x25) { // OR
2446 emit_or(s1l,s2l,tl);
2447 } else
2448 if(opcode2[i]==0x26) { // XOR
2449 emit_xor(s1l,s2l,tl);
2450 } else
2451 if(opcode2[i]==0x27) { // NOR
2452 emit_or(s1l,s2l,tl);
2453 emit_not(tl,tl);
2454 }
2455 }
2456 else
2457 {
2458 if(opcode2[i]==0x24) { // AND
2459 emit_zeroreg(tl);
2460 } else
2461 if(opcode2[i]==0x25||opcode2[i]==0x26) { // OR/XOR
2462 if(rs1[i]){
2463 if(s1l>=0) emit_mov(s1l,tl);
2464 else emit_loadreg(rs1[i],tl); // CHECK: regmap_entry?
2465 }
2466 else
2467 if(rs2[i]){
2468 if(s2l>=0) emit_mov(s2l,tl);
2469 else emit_loadreg(rs2[i],tl); // CHECK: regmap_entry?
2470 }
2471 else emit_zeroreg(tl);
2472 } else
2473 if(opcode2[i]==0x27) { // NOR
2474 if(rs1[i]){
2475 if(s1l>=0) emit_not(s1l,tl);
2476 else {
2477 emit_loadreg(rs1[i],tl);
2478 emit_not(tl,tl);
2479 }
2480 }
2481 else
2482 if(rs2[i]){
2483 if(s2l>=0) emit_not(s2l,tl);
2484 else {
2485 emit_loadreg(rs2[i],tl);
2486 emit_not(tl,tl);
2487 }
2488 }
2489 else emit_movimm(-1,tl);
2490 }
2491 }
2492 }
2493 }
2494 }
2495 }
2496}
2497
2498void imm16_assemble(int i,struct regstat *i_regs)
2499{
2500 if (opcode[i]==0x0f) { // LUI
2501 if(rt1[i]) {
2502 signed char t;
2503 t=get_reg(i_regs->regmap,rt1[i]);
2504 //assert(t>=0);
2505 if(t>=0) {
2506 if(!((i_regs->isconst>>t)&1))
2507 emit_movimm(imm[i]<<16,t);
2508 }
2509 }
2510 }
2511 if(opcode[i]==0x08||opcode[i]==0x09) { // ADDI/ADDIU
2512 if(rt1[i]) {
2513 signed char s,t;
2514 t=get_reg(i_regs->regmap,rt1[i]);
2515 s=get_reg(i_regs->regmap,rs1[i]);
2516 if(rs1[i]) {
2517 //assert(t>=0);
2518 //assert(s>=0);
2519 if(t>=0) {
2520 if(!((i_regs->isconst>>t)&1)) {
2521 if(s<0) {
2522 if(i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2523 emit_addimm(t,imm[i],t);
2524 }else{
2525 if(!((i_regs->wasconst>>s)&1))
2526 emit_addimm(s,imm[i],t);
2527 else
2528 emit_movimm(constmap[i][s]+imm[i],t);
2529 }
2530 }
2531 }
2532 } else {
2533 if(t>=0) {
2534 if(!((i_regs->isconst>>t)&1))
2535 emit_movimm(imm[i],t);
2536 }
2537 }
2538 }
2539 }
2540 if(opcode[i]==0x18||opcode[i]==0x19) { // DADDI/DADDIU
2541 if(rt1[i]) {
2542 signed char sh,sl,th,tl;
2543 th=get_reg(i_regs->regmap,rt1[i]|64);
2544 tl=get_reg(i_regs->regmap,rt1[i]);
2545 sh=get_reg(i_regs->regmap,rs1[i]|64);
2546 sl=get_reg(i_regs->regmap,rs1[i]);
2547 if(tl>=0) {
2548 if(rs1[i]) {
2549 assert(sh>=0);
2550 assert(sl>=0);
2551 if(th>=0) {
2552 emit_addimm64_32(sh,sl,imm[i],th,tl);
2553 }
2554 else {
2555 emit_addimm(sl,imm[i],tl);
2556 }
2557 } else {
2558 emit_movimm(imm[i],tl);
2559 if(th>=0) emit_movimm(((signed int)imm[i])>>31,th);
2560 }
2561 }
2562 }
2563 }
2564 else if(opcode[i]==0x0a||opcode[i]==0x0b) { // SLTI/SLTIU
2565 if(rt1[i]) {
2566 //assert(rs1[i]!=0); // r0 might be valid, but it's probably a bug
2567 signed char sh,sl,t;
2568 t=get_reg(i_regs->regmap,rt1[i]);
2569 sh=get_reg(i_regs->regmap,rs1[i]|64);
2570 sl=get_reg(i_regs->regmap,rs1[i]);
2571 //assert(t>=0);
2572 if(t>=0) {
2573 if(rs1[i]>0) {
2574 if(sh<0) assert((i_regs->was32>>rs1[i])&1);
2575 if(sh<0||((i_regs->was32>>rs1[i])&1)) {
2576 if(opcode[i]==0x0a) { // SLTI
2577 if(sl<0) {
2578 if(i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2579 emit_slti32(t,imm[i],t);
2580 }else{
2581 emit_slti32(sl,imm[i],t);
2582 }
2583 }
2584 else { // SLTIU
2585 if(sl<0) {
2586 if(i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2587 emit_sltiu32(t,imm[i],t);
2588 }else{
2589 emit_sltiu32(sl,imm[i],t);
2590 }
2591 }
2592 }else{ // 64-bit
2593 assert(sl>=0);
2594 if(opcode[i]==0x0a) // SLTI
2595 emit_slti64_32(sh,sl,imm[i],t);
2596 else // SLTIU
2597 emit_sltiu64_32(sh,sl,imm[i],t);
2598 }
2599 }else{
2600 // SLTI(U) with r0 is just stupid,
2601 // nonetheless examples can be found
2602 if(opcode[i]==0x0a) // SLTI
2603 if(0<imm[i]) emit_movimm(1,t);
2604 else emit_zeroreg(t);
2605 else // SLTIU
2606 {
2607 if(imm[i]) emit_movimm(1,t);
2608 else emit_zeroreg(t);
2609 }
2610 }
2611 }
2612 }
2613 }
2614 else if(opcode[i]>=0x0c&&opcode[i]<=0x0e) { // ANDI/ORI/XORI
2615 if(rt1[i]) {
2616 signed char sh,sl,th,tl;
2617 th=get_reg(i_regs->regmap,rt1[i]|64);
2618 tl=get_reg(i_regs->regmap,rt1[i]);
2619 sh=get_reg(i_regs->regmap,rs1[i]|64);
2620 sl=get_reg(i_regs->regmap,rs1[i]);
2621 if(tl>=0 && !((i_regs->isconst>>tl)&1)) {
2622 if(opcode[i]==0x0c) //ANDI
2623 {
2624 if(rs1[i]) {
2625 if(sl<0) {
2626 if(i_regs->regmap_entry[tl]!=rs1[i]) emit_loadreg(rs1[i],tl);
2627 emit_andimm(tl,imm[i],tl);
2628 }else{
2629 if(!((i_regs->wasconst>>sl)&1))
2630 emit_andimm(sl,imm[i],tl);
2631 else
2632 emit_movimm(constmap[i][sl]&imm[i],tl);
2633 }
2634 }
2635 else
2636 emit_zeroreg(tl);
2637 if(th>=0) emit_zeroreg(th);
2638 }
2639 else
2640 {
2641 if(rs1[i]) {
2642 if(sl<0) {
2643 if(i_regs->regmap_entry[tl]!=rs1[i]) emit_loadreg(rs1[i],tl);
2644 }
2645 if(th>=0) {
2646 if(sh<0) {
2647 emit_loadreg(rs1[i]|64,th);
2648 }else{
2649 emit_mov(sh,th);
2650 }
2651 }
2652 if(opcode[i]==0x0d) //ORI
2653 if(sl<0) {
2654 emit_orimm(tl,imm[i],tl);
2655 }else{
2656 if(!((i_regs->wasconst>>sl)&1))
2657 emit_orimm(sl,imm[i],tl);
2658 else
2659 emit_movimm(constmap[i][sl]|imm[i],tl);
2660 }
2661 if(opcode[i]==0x0e) //XORI
2662 if(sl<0) {
2663 emit_xorimm(tl,imm[i],tl);
2664 }else{
2665 if(!((i_regs->wasconst>>sl)&1))
2666 emit_xorimm(sl,imm[i],tl);
2667 else
2668 emit_movimm(constmap[i][sl]^imm[i],tl);
2669 }
2670 }
2671 else {
2672 emit_movimm(imm[i],tl);
2673 if(th>=0) emit_zeroreg(th);
2674 }
2675 }
2676 }
2677 }
2678 }
2679}
2680
2681void shiftimm_assemble(int i,struct regstat *i_regs)
2682{
2683 if(opcode2[i]<=0x3) // SLL/SRL/SRA
2684 {
2685 if(rt1[i]) {
2686 signed char s,t;
2687 t=get_reg(i_regs->regmap,rt1[i]);
2688 s=get_reg(i_regs->regmap,rs1[i]);
2689 //assert(t>=0);
2690 if(t>=0){
2691 if(rs1[i]==0)
2692 {
2693 emit_zeroreg(t);
2694 }
2695 else
2696 {
2697 if(s<0&&i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2698 if(imm[i]) {
2699 if(opcode2[i]==0) // SLL
2700 {
2701 emit_shlimm(s<0?t:s,imm[i],t);
2702 }
2703 if(opcode2[i]==2) // SRL
2704 {
2705 emit_shrimm(s<0?t:s,imm[i],t);
2706 }
2707 if(opcode2[i]==3) // SRA
2708 {
2709 emit_sarimm(s<0?t:s,imm[i],t);
2710 }
2711 }else{
2712 // Shift by zero
2713 if(s>=0 && s!=t) emit_mov(s,t);
2714 }
2715 }
2716 }
2717 //emit_storereg(rt1[i],t); //DEBUG
2718 }
2719 }
2720 if(opcode2[i]>=0x38&&opcode2[i]<=0x3b) // DSLL/DSRL/DSRA
2721 {
2722 if(rt1[i]) {
2723 signed char sh,sl,th,tl;
2724 th=get_reg(i_regs->regmap,rt1[i]|64);
2725 tl=get_reg(i_regs->regmap,rt1[i]);
2726 sh=get_reg(i_regs->regmap,rs1[i]|64);
2727 sl=get_reg(i_regs->regmap,rs1[i]);
2728 if(tl>=0) {
2729 if(rs1[i]==0)
2730 {
2731 emit_zeroreg(tl);
2732 if(th>=0) emit_zeroreg(th);
2733 }
2734 else
2735 {
2736 assert(sl>=0);
2737 assert(sh>=0);
2738 if(imm[i]) {
2739 if(opcode2[i]==0x38) // DSLL
2740 {
2741 if(th>=0) emit_shldimm(sh,sl,imm[i],th);
2742 emit_shlimm(sl,imm[i],tl);
2743 }
2744 if(opcode2[i]==0x3a) // DSRL
2745 {
2746 emit_shrdimm(sl,sh,imm[i],tl);
2747 if(th>=0) emit_shrimm(sh,imm[i],th);
2748 }
2749 if(opcode2[i]==0x3b) // DSRA
2750 {
2751 emit_shrdimm(sl,sh,imm[i],tl);
2752 if(th>=0) emit_sarimm(sh,imm[i],th);
2753 }
2754 }else{
2755 // Shift by zero
2756 if(sl!=tl) emit_mov(sl,tl);
2757 if(th>=0&&sh!=th) emit_mov(sh,th);
2758 }
2759 }
2760 }
2761 }
2762 }
2763 if(opcode2[i]==0x3c) // DSLL32
2764 {
2765 if(rt1[i]) {
2766 signed char sl,tl,th;
2767 tl=get_reg(i_regs->regmap,rt1[i]);
2768 th=get_reg(i_regs->regmap,rt1[i]|64);
2769 sl=get_reg(i_regs->regmap,rs1[i]);
2770 if(th>=0||tl>=0){
2771 assert(tl>=0);
2772 assert(th>=0);
2773 assert(sl>=0);
2774 emit_mov(sl,th);
2775 emit_zeroreg(tl);
2776 if(imm[i]>32)
2777 {
2778 emit_shlimm(th,imm[i]&31,th);
2779 }
2780 }
2781 }
2782 }
2783 if(opcode2[i]==0x3e) // DSRL32
2784 {
2785 if(rt1[i]) {
2786 signed char sh,tl,th;
2787 tl=get_reg(i_regs->regmap,rt1[i]);
2788 th=get_reg(i_regs->regmap,rt1[i]|64);
2789 sh=get_reg(i_regs->regmap,rs1[i]|64);
2790 if(tl>=0){
2791 assert(sh>=0);
2792 emit_mov(sh,tl);
2793 if(th>=0) emit_zeroreg(th);
2794 if(imm[i]>32)
2795 {
2796 emit_shrimm(tl,imm[i]&31,tl);
2797 }
2798 }
2799 }
2800 }
2801 if(opcode2[i]==0x3f) // DSRA32
2802 {
2803 if(rt1[i]) {
2804 signed char sh,tl;
2805 tl=get_reg(i_regs->regmap,rt1[i]);
2806 sh=get_reg(i_regs->regmap,rs1[i]|64);
2807 if(tl>=0){
2808 assert(sh>=0);
2809 emit_mov(sh,tl);
2810 if(imm[i]>32)
2811 {
2812 emit_sarimm(tl,imm[i]&31,tl);
2813 }
2814 }
2815 }
2816 }
2817}
2818
2819#ifndef shift_assemble
2820void shift_assemble(int i,struct regstat *i_regs)
2821{
2822 printf("Need shift_assemble for this architecture.\n");
2823 exit(1);
2824}
2825#endif
2826
2827void load_assemble(int i,struct regstat *i_regs)
2828{
2829 int s,th,tl,addr,map=-1;
2830 int offset;
2831 int jaddr=0;
5bf843dc 2832 int memtarget=0,c=0;
b1570849 2833 int fastload_reg_override=0;
57871462 2834 u_int hr,reglist=0;
2835 th=get_reg(i_regs->regmap,rt1[i]|64);
2836 tl=get_reg(i_regs->regmap,rt1[i]);
2837 s=get_reg(i_regs->regmap,rs1[i]);
2838 offset=imm[i];
2839 for(hr=0;hr<HOST_REGS;hr++) {
2840 if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
2841 }
2842 if(i_regs->regmap[HOST_CCREG]==CCREG) reglist&=~(1<<HOST_CCREG);
2843 if(s>=0) {
2844 c=(i_regs->wasconst>>s)&1;
af4ee1fe 2845 if (c) {
2846 memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
2847 if(using_tlb&&((signed int)(constmap[i][s]+offset))>=(signed int)0xC0000000) memtarget=1;
2848 }
57871462 2849 }
57871462 2850 //printf("load_assemble: c=%d\n",c);
2851 //if(c) printf("load_assemble: const=%x\n",(int)constmap[i][s]+offset);
2852 // FIXME: Even if the load is a NOP, we should check for pagefaults...
5bf843dc 2853#ifdef PCSX
f18c0f46 2854 if(tl<0&&(!c||(((u_int)constmap[i][s]+offset)>>16)==0x1f80)
2855 ||rt1[i]==0) {
5bf843dc 2856 // could be FIFO, must perform the read
f18c0f46 2857 // ||dummy read
5bf843dc 2858 assem_debug("(forced read)\n");
2859 tl=get_reg(i_regs->regmap,-1);
2860 assert(tl>=0);
5bf843dc 2861 }
f18c0f46 2862#endif
5bf843dc 2863 if(offset||s<0||c) addr=tl;
2864 else addr=s;
535d208a 2865 //if(tl<0) tl=get_reg(i_regs->regmap,-1);
2866 if(tl>=0) {
2867 //printf("load_assemble: c=%d\n",c);
2868 //if(c) printf("load_assemble: const=%x\n",(int)constmap[i][s]+offset);
2869 assert(tl>=0); // Even if the load is a NOP, we must check for pagefaults and I/O
2870 reglist&=~(1<<tl);
2871 if(th>=0) reglist&=~(1<<th);
2872 if(!using_tlb) {
2873 if(!c) {
2874 #ifdef RAM_OFFSET
2875 map=get_reg(i_regs->regmap,ROREG);
2876 if(map<0) emit_loadreg(ROREG,map=HOST_TEMPREG);
2877 #endif
57871462 2878//#define R29_HACK 1
535d208a 2879 #ifdef R29_HACK
2880 // Strmnnrmn's speed hack
2881 if(rs1[i]!=29||start<0x80001000||start>=0x80000000+RAM_SIZE)
2882 #endif
2883 {
dadf55f2 2884 #ifdef PCSX
2885 if(sp_in_mirror&&rs1[i]==29) {
2886 emit_andimm(addr,~0x00e00000,HOST_TEMPREG);
2887 emit_cmpimm(HOST_TEMPREG,RAM_SIZE);
b1570849 2888 fastload_reg_override=HOST_TEMPREG;
dadf55f2 2889 }
2890 else
2891 #endif
535d208a 2892 emit_cmpimm(addr,RAM_SIZE);
2893 jaddr=(int)out;
2894 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
2895 // Hint to branch predictor that the branch is unlikely to be taken
2896 if(rs1[i]>=28)
2897 emit_jno_unlikely(0);
2898 else
57871462 2899 #endif
535d208a 2900 emit_jno(0);
57871462 2901 }
535d208a 2902 }
2903 }else{ // using tlb
2904 int x=0;
2905 if (opcode[i]==0x20||opcode[i]==0x24) x=3; // LB/LBU
2906 if (opcode[i]==0x21||opcode[i]==0x25) x=2; // LH/LHU
2907 map=get_reg(i_regs->regmap,TLREG);
2908 assert(map>=0);
ea3d2e6e 2909 reglist&=~(1<<map);
535d208a 2910 map=do_tlb_r(addr,tl,map,x,-1,-1,c,constmap[i][s]+offset);
2911 do_tlb_r_branch(map,c,constmap[i][s]+offset,&jaddr);
2912 }
2913 int dummy=(rt1[i]==0)||(tl!=get_reg(i_regs->regmap,rt1[i])); // ignore loads to r0 and unneeded reg
2914 if (opcode[i]==0x20) { // LB
2915 if(!c||memtarget) {
2916 if(!dummy) {
57871462 2917 #ifdef HOST_IMM_ADDR32
2918 if(c)
2919 emit_movsbl_tlb((constmap[i][s]+offset)^3,map,tl);
2920 else
2921 #endif
2922 {
2923 //emit_xorimm(addr,3,tl);
2924 //gen_tlb_addr_r(tl,map);
2925 //emit_movsbl_indexed((int)rdram-0x80000000,tl,tl);
535d208a 2926 int x=0,a=tl;
2002a1db 2927#ifdef BIG_ENDIAN_MIPS
57871462 2928 if(!c) emit_xorimm(addr,3,tl);
2929 else x=((constmap[i][s]+offset)^3)-(constmap[i][s]+offset);
2002a1db 2930#else
535d208a 2931 if(!c) a=addr;
dadf55f2 2932#endif
b1570849 2933 if(fastload_reg_override) a=fastload_reg_override;
2934
535d208a 2935 emit_movsbl_indexed_tlb(x,a,map,tl);
57871462 2936 }
57871462 2937 }
535d208a 2938 if(jaddr)
2939 add_stub(LOADB_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
57871462 2940 }
535d208a 2941 else
2942 inline_readstub(LOADB_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2943 }
2944 if (opcode[i]==0x21) { // LH
2945 if(!c||memtarget) {
2946 if(!dummy) {
57871462 2947 #ifdef HOST_IMM_ADDR32
2948 if(c)
2949 emit_movswl_tlb((constmap[i][s]+offset)^2,map,tl);
2950 else
2951 #endif
2952 {
535d208a 2953 int x=0,a=tl;
2002a1db 2954#ifdef BIG_ENDIAN_MIPS
57871462 2955 if(!c) emit_xorimm(addr,2,tl);
2956 else x=((constmap[i][s]+offset)^2)-(constmap[i][s]+offset);
2002a1db 2957#else
535d208a 2958 if(!c) a=addr;
dadf55f2 2959#endif
b1570849 2960 if(fastload_reg_override) a=fastload_reg_override;
57871462 2961 //#ifdef
2962 //emit_movswl_indexed_tlb(x,tl,map,tl);
2963 //else
2964 if(map>=0) {
535d208a 2965 gen_tlb_addr_r(a,map);
2966 emit_movswl_indexed(x,a,tl);
2967 }else{
2968 #ifdef RAM_OFFSET
2969 emit_movswl_indexed(x,a,tl);
2970 #else
2971 emit_movswl_indexed((int)rdram-0x80000000+x,a,tl);
2972 #endif
2973 }
57871462 2974 }
57871462 2975 }
535d208a 2976 if(jaddr)
2977 add_stub(LOADH_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
57871462 2978 }
535d208a 2979 else
2980 inline_readstub(LOADH_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2981 }
2982 if (opcode[i]==0x23) { // LW
2983 if(!c||memtarget) {
2984 if(!dummy) {
dadf55f2 2985 int a=addr;
b1570849 2986 if(fastload_reg_override) a=fastload_reg_override;
57871462 2987 //emit_readword_indexed((int)rdram-0x80000000,addr,tl);
2988 #ifdef HOST_IMM_ADDR32
2989 if(c)
2990 emit_readword_tlb(constmap[i][s]+offset,map,tl);
2991 else
2992 #endif
dadf55f2 2993 emit_readword_indexed_tlb(0,a,map,tl);
57871462 2994 }
535d208a 2995 if(jaddr)
2996 add_stub(LOADW_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
57871462 2997 }
535d208a 2998 else
2999 inline_readstub(LOADW_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
3000 }
3001 if (opcode[i]==0x24) { // LBU
3002 if(!c||memtarget) {
3003 if(!dummy) {
57871462 3004 #ifdef HOST_IMM_ADDR32
3005 if(c)
3006 emit_movzbl_tlb((constmap[i][s]+offset)^3,map,tl);
3007 else
3008 #endif
3009 {
3010 //emit_xorimm(addr,3,tl);
3011 //gen_tlb_addr_r(tl,map);
3012 //emit_movzbl_indexed((int)rdram-0x80000000,tl,tl);
535d208a 3013 int x=0,a=tl;
2002a1db 3014#ifdef BIG_ENDIAN_MIPS
57871462 3015 if(!c) emit_xorimm(addr,3,tl);
3016 else x=((constmap[i][s]+offset)^3)-(constmap[i][s]+offset);
2002a1db 3017#else
535d208a 3018 if(!c) a=addr;
dadf55f2 3019#endif
b1570849 3020 if(fastload_reg_override) a=fastload_reg_override;
3021
535d208a 3022 emit_movzbl_indexed_tlb(x,a,map,tl);
57871462 3023 }
57871462 3024 }
535d208a 3025 if(jaddr)
3026 add_stub(LOADBU_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
57871462 3027 }
535d208a 3028 else
3029 inline_readstub(LOADBU_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
3030 }
3031 if (opcode[i]==0x25) { // LHU
3032 if(!c||memtarget) {
3033 if(!dummy) {
57871462 3034 #ifdef HOST_IMM_ADDR32
3035 if(c)
3036 emit_movzwl_tlb((constmap[i][s]+offset)^2,map,tl);
3037 else
3038 #endif
3039 {
535d208a 3040 int x=0,a=tl;
2002a1db 3041#ifdef BIG_ENDIAN_MIPS
57871462 3042 if(!c) emit_xorimm(addr,2,tl);
3043 else x=((constmap[i][s]+offset)^2)-(constmap[i][s]+offset);
2002a1db 3044#else
535d208a 3045 if(!c) a=addr;
dadf55f2 3046#endif
b1570849 3047 if(fastload_reg_override) a=fastload_reg_override;
57871462 3048 //#ifdef
3049 //emit_movzwl_indexed_tlb(x,tl,map,tl);
3050 //#else
3051 if(map>=0) {
535d208a 3052 gen_tlb_addr_r(a,map);
3053 emit_movzwl_indexed(x,a,tl);
3054 }else{
3055 #ifdef RAM_OFFSET
3056 emit_movzwl_indexed(x,a,tl);
3057 #else
3058 emit_movzwl_indexed((int)rdram-0x80000000+x,a,tl);
3059 #endif
3060 }
57871462 3061 }
3062 }
535d208a 3063 if(jaddr)
3064 add_stub(LOADHU_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
57871462 3065 }
535d208a 3066 else
3067 inline_readstub(LOADHU_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
3068 }
3069 if (opcode[i]==0x27) { // LWU
3070 assert(th>=0);
3071 if(!c||memtarget) {
3072 if(!dummy) {
dadf55f2 3073 int a=addr;
b1570849 3074 if(fastload_reg_override) a=fastload_reg_override;
57871462 3075 //emit_readword_indexed((int)rdram-0x80000000,addr,tl);
3076 #ifdef HOST_IMM_ADDR32
3077 if(c)
3078 emit_readword_tlb(constmap[i][s]+offset,map,tl);
3079 else
3080 #endif
dadf55f2 3081 emit_readword_indexed_tlb(0,a,map,tl);
57871462 3082 }
535d208a 3083 if(jaddr)
3084 add_stub(LOADW_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
3085 }
3086 else {
3087 inline_readstub(LOADW_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
57871462 3088 }
535d208a 3089 emit_zeroreg(th);
3090 }
3091 if (opcode[i]==0x37) { // LD
3092 if(!c||memtarget) {
3093 if(!dummy) {
dadf55f2 3094 int a=addr;
b1570849 3095 if(fastload_reg_override) a=fastload_reg_override;
57871462 3096 //gen_tlb_addr_r(tl,map);
3097 //if(th>=0) emit_readword_indexed((int)rdram-0x80000000,addr,th);
3098 //emit_readword_indexed((int)rdram-0x7FFFFFFC,addr,tl);
3099 #ifdef HOST_IMM_ADDR32
3100 if(c)
3101 emit_readdword_tlb(constmap[i][s]+offset,map,th,tl);
3102 else
3103 #endif
dadf55f2 3104 emit_readdword_indexed_tlb(0,a,map,th,tl);
57871462 3105 }
535d208a 3106 if(jaddr)
3107 add_stub(LOADD_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
57871462 3108 }
535d208a 3109 else
3110 inline_readstub(LOADD_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
57871462 3111 }
535d208a 3112 }
3113 //emit_storereg(rt1[i],tl); // DEBUG
57871462 3114 //if(opcode[i]==0x23)
3115 //if(opcode[i]==0x24)
3116 //if(opcode[i]==0x23||opcode[i]==0x24)
3117 /*if(opcode[i]==0x21||opcode[i]==0x23||opcode[i]==0x24)
3118 {
3119 //emit_pusha();
3120 save_regs(0x100f);
3121 emit_readword((int)&last_count,ECX);
3122 #ifdef __i386__
3123 if(get_reg(i_regs->regmap,CCREG)<0)
3124 emit_loadreg(CCREG,HOST_CCREG);
3125 emit_add(HOST_CCREG,ECX,HOST_CCREG);
3126 emit_addimm(HOST_CCREG,2*ccadj[i],HOST_CCREG);
3127 emit_writeword(HOST_CCREG,(int)&Count);
3128 #endif
3129 #ifdef __arm__
3130 if(get_reg(i_regs->regmap,CCREG)<0)
3131 emit_loadreg(CCREG,0);
3132 else
3133 emit_mov(HOST_CCREG,0);
3134 emit_add(0,ECX,0);
3135 emit_addimm(0,2*ccadj[i],0);
3136 emit_writeword(0,(int)&Count);
3137 #endif
3138 emit_call((int)memdebug);
3139 //emit_popa();
3140 restore_regs(0x100f);
3141 }/**/
3142}
3143
3144#ifndef loadlr_assemble
3145void loadlr_assemble(int i,struct regstat *i_regs)
3146{
3147 printf("Need loadlr_assemble for this architecture.\n");
3148 exit(1);
3149}
3150#endif
3151
3152void store_assemble(int i,struct regstat *i_regs)
3153{
3154 int s,th,tl,map=-1;
3155 int addr,temp;
3156 int offset;
3157 int jaddr=0,jaddr2,type;
666a299d 3158 int memtarget=0,c=0;
57871462 3159 int agr=AGEN1+(i&1);
b1570849 3160 int faststore_reg_override=0;
57871462 3161 u_int hr,reglist=0;
3162 th=get_reg(i_regs->regmap,rs2[i]|64);
3163 tl=get_reg(i_regs->regmap,rs2[i]);
3164 s=get_reg(i_regs->regmap,rs1[i]);
3165 temp=get_reg(i_regs->regmap,agr);
3166 if(temp<0) temp=get_reg(i_regs->regmap,-1);
3167 offset=imm[i];
3168 if(s>=0) {
3169 c=(i_regs->wasconst>>s)&1;
af4ee1fe 3170 if(c) {
3171 memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
3172 if(using_tlb&&((signed int)(constmap[i][s]+offset))>=(signed int)0xC0000000) memtarget=1;
3173 }
57871462 3174 }
3175 assert(tl>=0);
3176 assert(temp>=0);
3177 for(hr=0;hr<HOST_REGS;hr++) {
3178 if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
3179 }
3180 if(i_regs->regmap[HOST_CCREG]==CCREG) reglist&=~(1<<HOST_CCREG);
3181 if(offset||s<0||c) addr=temp;
3182 else addr=s;
3183 if(!using_tlb) {
3184 if(!c) {
dadf55f2 3185 #ifdef PCSX
3186 if(sp_in_mirror&&rs1[i]==29) {
3187 emit_andimm(addr,~0x00e00000,HOST_TEMPREG);
3188 emit_cmpimm(HOST_TEMPREG,RAM_SIZE);
b1570849 3189 faststore_reg_override=HOST_TEMPREG;
dadf55f2 3190 }
3191 else
3192 #endif
57871462 3193 #ifdef R29_HACK
3194 // Strmnnrmn's speed hack
4cb76aa4 3195 if(rs1[i]!=29||start<0x80001000||start>=0x80000000+RAM_SIZE)
57871462 3196 #endif
4cb76aa4 3197 emit_cmpimm(addr,RAM_SIZE);
57871462 3198 #ifdef DESTRUCTIVE_SHIFT
3199 if(s==addr) emit_mov(s,temp);
3200 #endif
3201 #ifdef R29_HACK
dadf55f2 3202 memtarget=1;
4cb76aa4 3203 if(rs1[i]!=29||start<0x80001000||start>=0x80000000+RAM_SIZE)
57871462 3204 #endif
3205 {
3206 jaddr=(int)out;
3207 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
3208 // Hint to branch predictor that the branch is unlikely to be taken
3209 if(rs1[i]>=28)
3210 emit_jno_unlikely(0);
3211 else
3212 #endif
3213 emit_jno(0);
3214 }
3215 }
3216 }else{ // using tlb
3217 int x=0;
3218 if (opcode[i]==0x28) x=3; // SB
3219 if (opcode[i]==0x29) x=2; // SH
3220 map=get_reg(i_regs->regmap,TLREG);
3221 assert(map>=0);
ea3d2e6e 3222 reglist&=~(1<<map);
57871462 3223 map=do_tlb_w(addr,temp,map,x,c,constmap[i][s]+offset);
3224 do_tlb_w_branch(map,c,constmap[i][s]+offset,&jaddr);
3225 }
3226
3227 if (opcode[i]==0x28) { // SB
3228 if(!c||memtarget) {
97a238a6 3229 int x=0,a=temp;
2002a1db 3230#ifdef BIG_ENDIAN_MIPS
57871462 3231 if(!c) emit_xorimm(addr,3,temp);
3232 else x=((constmap[i][s]+offset)^3)-(constmap[i][s]+offset);
2002a1db 3233#else
97a238a6 3234 if(!c) a=addr;
dadf55f2 3235#endif
b1570849 3236 if(faststore_reg_override) a=faststore_reg_override;
57871462 3237 //gen_tlb_addr_w(temp,map);
3238 //emit_writebyte_indexed(tl,(int)rdram-0x80000000,temp);
97a238a6 3239 emit_writebyte_indexed_tlb(tl,x,a,map,a);
57871462 3240 }
3241 type=STOREB_STUB;
3242 }
3243 if (opcode[i]==0x29) { // SH
3244 if(!c||memtarget) {
97a238a6 3245 int x=0,a=temp;
2002a1db 3246#ifdef BIG_ENDIAN_MIPS
57871462 3247 if(!c) emit_xorimm(addr,2,temp);
3248 else x=((constmap[i][s]+offset)^2)-(constmap[i][s]+offset);
2002a1db 3249#else
97a238a6 3250 if(!c) a=addr;
dadf55f2 3251#endif
b1570849 3252 if(faststore_reg_override) a=faststore_reg_override;
57871462 3253 //#ifdef
3254 //emit_writehword_indexed_tlb(tl,x,temp,map,temp);
3255 //#else
3256 if(map>=0) {
97a238a6 3257 gen_tlb_addr_w(a,map);
3258 emit_writehword_indexed(tl,x,a);
57871462 3259 }else
97a238a6 3260 emit_writehword_indexed(tl,(int)rdram-0x80000000+x,a);
57871462 3261 }
3262 type=STOREH_STUB;
3263 }
3264 if (opcode[i]==0x2B) { // SW
dadf55f2 3265 if(!c||memtarget) {
3266 int a=addr;
b1570849 3267 if(faststore_reg_override) a=faststore_reg_override;
57871462 3268 //emit_writeword_indexed(tl,(int)rdram-0x80000000,addr);
dadf55f2 3269 emit_writeword_indexed_tlb(tl,0,a,map,temp);
3270 }
57871462 3271 type=STOREW_STUB;
3272 }
3273 if (opcode[i]==0x3F) { // SD
3274 if(!c||memtarget) {
dadf55f2 3275 int a=addr;
b1570849 3276 if(faststore_reg_override) a=faststore_reg_override;
57871462 3277 if(rs2[i]) {
3278 assert(th>=0);
3279 //emit_writeword_indexed(th,(int)rdram-0x80000000,addr);
3280 //emit_writeword_indexed(tl,(int)rdram-0x7FFFFFFC,addr);
dadf55f2 3281 emit_writedword_indexed_tlb(th,tl,0,a,map,temp);
57871462 3282 }else{
3283 // Store zero
3284 //emit_writeword_indexed(tl,(int)rdram-0x80000000,temp);
3285 //emit_writeword_indexed(tl,(int)rdram-0x7FFFFFFC,temp);
dadf55f2 3286 emit_writedword_indexed_tlb(tl,tl,0,a,map,temp);
57871462 3287 }
3288 }
3289 type=STORED_STUB;
3290 }
b96d3df7 3291#ifdef PCSX
3292 if(jaddr) {
3293 // PCSX store handlers don't check invcode again
3294 reglist|=1<<addr;
3295 add_stub(type,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
3296 jaddr=0;
3297 }
3298#endif
57871462 3299 if(!using_tlb) {
3300 if(!c||memtarget) {
3301 #ifdef DESTRUCTIVE_SHIFT
3302 // The x86 shift operation is 'destructive'; it overwrites the
3303 // source register, so we need to make a copy first and use that.
3304