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57871462 | 1 | /* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * |
2 | * Mupen64plus - new_dynarec.c * | |
20d507ba | 3 | * Copyright (C) 2009-2011 Ari64 * |
57871462 | 4 | * * |
5 | * This program is free software; you can redistribute it and/or modify * | |
6 | * it under the terms of the GNU General Public License as published by * | |
7 | * the Free Software Foundation; either version 2 of the License, or * | |
8 | * (at your option) any later version. * | |
9 | * * | |
10 | * This program is distributed in the hope that it will be useful, * | |
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of * | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * | |
13 | * GNU General Public License for more details. * | |
14 | * * | |
15 | * You should have received a copy of the GNU General Public License * | |
16 | * along with this program; if not, write to the * | |
17 | * Free Software Foundation, Inc., * | |
18 | * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * | |
19 | * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */ | |
20 | ||
21 | #include <stdlib.h> | |
22 | #include <stdint.h> //include for uint64_t | |
23 | #include <assert.h> | |
d848b60a | 24 | #include <errno.h> |
4600ba03 | 25 | #include <sys/mman.h> |
7ef2f1f7 | 26 | #include <unistd.h> |
d148d265 | 27 | #ifdef __MACH__ |
28 | #include <libkern/OSCacheControl.h> | |
29 | #endif | |
1e212a25 | 30 | #ifdef _3DS |
31 | #include <3ds_utils.h> | |
32 | #endif | |
7c404fb9 | 33 | #ifdef HAVE_LIBNX |
34 | #include <switch.h> | |
35 | static Jit g_jit; | |
36 | #endif | |
57871462 | 37 | |
d148d265 | 38 | #include "new_dynarec_config.h" |
630b122b | 39 | #include "../psxhle.h" |
40 | #include "../psxinterpreter.h" | |
584fc319 | 41 | #include "../psxcounters.h" |
630b122b | 42 | #include "../gte.h" |
43 | #include "emu_if.h" // emulator interface | |
f2e25348 | 44 | #include "linkage_offsets.h" |
45 | #include "compiler_features.h" | |
9a6c6e37 | 46 | #include "arm_features.h" |
630b122b | 47 | |
630b122b | 48 | #ifndef ARRAY_SIZE |
49 | #define ARRAY_SIZE(x) (sizeof(x) / sizeof(x[0])) | |
50 | #endif | |
51 | #ifndef min | |
52 | #define min(a, b) ((b) < (a) ? (b) : (a)) | |
53 | #endif | |
54 | #ifndef max | |
55 | #define max(a, b) ((b) > (a) ? (b) : (a)) | |
56 | #endif | |
57871462 | 57 | |
4600ba03 | 58 | //#define DISASM |
630b122b | 59 | //#define ASSEM_PRINT |
f2e25348 | 60 | //#define REGMAP_PRINT // with DISASM only |
bdbf4466 | 61 | //#define INV_DEBUG_W |
55cadc36 | 62 | //#define STAT_PRINT |
630b122b | 63 | |
64 | #ifdef ASSEM_PRINT | |
65 | #define assem_debug printf | |
66 | #else | |
4600ba03 | 67 | #define assem_debug(...) |
630b122b | 68 | #endif |
69 | //#define inv_debug printf | |
4600ba03 | 70 | #define inv_debug(...) |
57871462 | 71 | |
72 | #ifdef __i386__ | |
630b122b | 73 | #include "assem_x86.h" |
57871462 | 74 | #endif |
75 | #ifdef __x86_64__ | |
630b122b | 76 | #include "assem_x64.h" |
57871462 | 77 | #endif |
78 | #ifdef __arm__ | |
630b122b | 79 | #include "assem_arm.h" |
57871462 | 80 | #endif |
630b122b | 81 | #ifdef __aarch64__ |
82 | #include "assem_arm64.h" | |
73081f23 FJGG |
83 | #endif |
84 | ||
630b122b | 85 | #define RAM_SIZE 0x200000 |
ee8d7dfd | 86 | #define MAXBLOCK 2048 |
57871462 | 87 | #define MAX_OUTPUT_BLOCK_SIZE 262144 |
432435ea | 88 | #define EXPIRITY_OFFSET (MAX_OUTPUT_BLOCK_SIZE * 2) |
89 | #define PAGE_COUNT 1024 | |
2573466a | 90 | |
b9e27215 | 91 | #if defined(HAVE_CONDITIONAL_CALL) && !defined(DESTRUCTIVE_SHIFT) |
92 | #define INVALIDATE_USE_COND_CALL | |
93 | #endif | |
94 | ||
ab51e9e2 | 95 | #ifdef VITA |
96 | // apparently Vita has a 16MB limit, so either we cut tc in half, | |
97 | // or use this hack (it's a hack because tc size was designed to be power-of-2) | |
98 | #define TC_REDUCE_BYTES 4096 | |
99 | #else | |
100 | #define TC_REDUCE_BYTES 0 | |
101 | #endif | |
102 | ||
7f9e081d | 103 | struct ndrc_tramp |
104 | { | |
105 | struct tramp_insns ops[2048 / sizeof(struct tramp_insns)]; | |
106 | const void *f[2048 / sizeof(void *)]; | |
107 | }; | |
108 | ||
630b122b | 109 | struct ndrc_mem |
110 | { | |
ab51e9e2 | 111 | u_char translation_cache[(1 << TARGET_SIZE_2) - TC_REDUCE_BYTES]; |
7f9e081d | 112 | struct ndrc_tramp tramp; |
630b122b | 113 | }; |
114 | ||
630b122b | 115 | static struct ndrc_mem *ndrc; |
7ef2f1f7 | 116 | #ifndef BASE_ADDR_DYNAMIC |
117 | // reserve .bss space with upto 64k page size in mind | |
118 | static char ndrc_bss[((sizeof(*ndrc) + 65535) & ~65535) + 65536]; | |
630b122b | 119 | #endif |
7f9e081d | 120 | #ifdef TC_WRITE_OFFSET |
7c404fb9 | 121 | # ifdef __GLIBC__ |
122 | # include <sys/types.h> | |
123 | # include <sys/stat.h> | |
124 | # include <fcntl.h> | |
7c404fb9 | 125 | # endif |
126 | static long ndrc_write_ofs; | |
7f9e081d | 127 | #define NDRC_WRITE_OFFSET(x) (void *)((char *)(x) + ndrc_write_ofs) |
7c404fb9 | 128 | #else |
7f9e081d | 129 | #define NDRC_WRITE_OFFSET(x) (x) |
7c404fb9 | 130 | #endif |
630b122b | 131 | |
132 | // stubs | |
133 | enum stub_type { | |
134 | CC_STUB = 1, | |
f2e25348 | 135 | //FP_STUB = 2, |
630b122b | 136 | LOADB_STUB = 3, |
137 | LOADH_STUB = 4, | |
138 | LOADW_STUB = 5, | |
f2e25348 | 139 | //LOADD_STUB = 6, |
630b122b | 140 | LOADBU_STUB = 7, |
141 | LOADHU_STUB = 8, | |
142 | STOREB_STUB = 9, | |
143 | STOREH_STUB = 10, | |
144 | STOREW_STUB = 11, | |
f2e25348 | 145 | //STORED_STUB = 12, |
630b122b | 146 | STORELR_STUB = 13, |
147 | INVCODE_STUB = 14, | |
f2e25348 | 148 | OVERFLOW_STUB = 15, |
259dbd60 | 149 | ALIGNMENT_STUB = 16, |
630b122b | 150 | }; |
151 | ||
b15d122e | 152 | // regmap_pre[i] - regs before [i] insn starts; dirty things here that |
153 | // don't match .regmap will be written back | |
154 | // [i].regmap_entry - regs that must be set up if someone jumps here | |
155 | // [i].regmap - regs [i] insn will read/(over)write | |
fdf33825 | 156 | // branch_regs[i].* - same as above but for branches, takes delay slot into account |
57871462 | 157 | struct regstat |
158 | { | |
b15d122e | 159 | signed char regmap_entry[HOST_REGS]; |
57871462 | 160 | signed char regmap[HOST_REGS]; |
a3c5fc39 | 161 | u_int wasdirty; |
162 | u_int dirty; | |
630b122b | 163 | u_int wasconst; // before; for example 'lw r2, (r2)' wasconst is true |
f2e25348 | 164 | u_int isconst; // ... but isconst is false when r2 is known (hr) |
8575a877 | 165 | u_int loadedconst; // host regs that have constants loaded |
b4661440 | 166 | u_int noevict; // can't evict this hr (alloced by current op) |
bdbf4466 | 167 | //u_int waswritten; // MIPS regs that were used as store base before |
a3c5fc39 | 168 | uint64_t u; |
57871462 | 169 | }; |
170 | ||
630b122b | 171 | struct ht_entry |
172 | { | |
173 | u_int vaddr[2]; | |
174 | void *tcaddr[2]; | |
175 | }; | |
176 | ||
177 | struct code_stub | |
178 | { | |
179 | enum stub_type type; | |
180 | void *addr; | |
181 | void *retaddr; | |
182 | u_int a; | |
183 | uintptr_t b; | |
184 | uintptr_t c; | |
185 | u_int d; | |
186 | u_int e; | |
187 | }; | |
188 | ||
189 | struct link_entry | |
190 | { | |
191 | void *addr; | |
192 | u_int target; | |
048fcced | 193 | u_int internal; |
194 | }; | |
195 | ||
196 | struct block_info | |
197 | { | |
198 | struct block_info *next; | |
199 | const void *source; | |
200 | const void *copy; | |
201 | u_int start; // vaddr of the block start | |
202 | u_int len; // of the whole block source | |
203 | u_int tc_offs; | |
204 | //u_int tc_len; | |
205 | u_int reg_sv_flags; | |
11eca54f | 206 | u_char is_dirty; |
207 | u_char inv_near_misses; | |
048fcced | 208 | u_short jump_in_cnt; |
209 | struct { | |
210 | u_int vaddr; | |
211 | void *addr; | |
212 | } jump_in[0]; | |
630b122b | 213 | }; |
214 | ||
366d1d2b | 215 | struct jump_info |
216 | { | |
217 | int alloc; | |
218 | int count; | |
219 | struct { | |
220 | u_int target_vaddr; | |
221 | void *stub; | |
222 | } e[0]; | |
223 | }; | |
224 | ||
630b122b | 225 | static struct decoded_insn |
226 | { | |
227 | u_char itype; | |
f2e25348 | 228 | u_char opcode; // bits 31-26 |
229 | u_char opcode2; // (depends on opcode) | |
630b122b | 230 | u_char rs1; |
231 | u_char rs2; | |
232 | u_char rt1; | |
233 | u_char rt2; | |
ed14d777 | 234 | u_char use_lt1:1; |
630b122b | 235 | u_char bt:1; |
236 | u_char ooo:1; | |
237 | u_char is_ds:1; | |
238 | u_char is_jump:1; | |
239 | u_char is_ujump:1; | |
240 | u_char is_load:1; | |
241 | u_char is_store:1; | |
f2e25348 | 242 | u_char is_delay_load:1; // is_load + MFC/CFC |
243 | u_char is_exception:1; // unconditional, also interp. fallback | |
244 | u_char may_except:1; // might generate an exception | |
59dd5faf | 245 | u_char ls_type:2; // load/store type (ls_width_type) |
630b122b | 246 | } dops[MAXBLOCK]; |
247 | ||
59dd5faf | 248 | enum ls_width_type { |
249 | LS_8 = 0, LS_16, LS_32, LS_LR | |
250 | }; | |
251 | ||
259dbd60 | 252 | static struct compile_info |
253 | { | |
254 | int imm; | |
255 | u_int ba; | |
256 | int ccadj; | |
257 | signed char min_free_regs; | |
258 | signed char addr; | |
259 | signed char reserved[2]; | |
260 | } cinfo[MAXBLOCK]; | |
261 | ||
bfdecce3 | 262 | static u_char *out; |
6c62131f | 263 | static char invalid_code[0x100000]; |
048fcced | 264 | static struct ht_entry hash_table[65536]; |
432435ea | 265 | static struct block_info *blocks[PAGE_COUNT]; |
366d1d2b | 266 | static struct jump_info *jumps[PAGE_COUNT]; |
e2b5e7aa | 267 | static u_int start; |
268 | static u_int *source; | |
bedfea38 | 269 | static uint64_t gte_rs[MAXBLOCK]; // gte: 32 data and 32 ctl regs |
270 | static uint64_t gte_rt[MAXBLOCK]; | |
271 | static uint64_t gte_unneeded[MAXBLOCK]; | |
ffb0b9e0 | 272 | static u_int smrv[32]; // speculated MIPS register values |
273 | static u_int smrv_strong; // mask or regs that are likely to have correct values | |
274 | static u_int smrv_weak; // same, but somewhat less likely | |
275 | static u_int smrv_strong_next; // same, but after current insn executes | |
276 | static u_int smrv_weak_next; | |
e2b5e7aa | 277 | static uint64_t unneeded_reg[MAXBLOCK]; |
e2b5e7aa | 278 | static uint64_t branch_unneeded_reg[MAXBLOCK]; |
b15d122e | 279 | // see 'struct regstat' for a description |
e2b5e7aa | 280 | static signed char regmap_pre[MAXBLOCK][HOST_REGS]; |
630b122b | 281 | // contains 'real' consts at [i] insn, but may differ from what's actually |
282 | // loaded in host reg as 'final' value is always loaded, see get_final_value() | |
283 | static uint32_t current_constmap[HOST_REGS]; | |
284 | static uint32_t constmap[MAXBLOCK][HOST_REGS]; | |
956f3129 | 285 | static struct regstat regs[MAXBLOCK]; |
286 | static struct regstat branch_regs[MAXBLOCK]; | |
e2b5e7aa | 287 | static int slen; |
630b122b | 288 | static void *instr_addr[MAXBLOCK]; |
289 | static struct link_entry link_addr[MAXBLOCK]; | |
e2b5e7aa | 290 | static int linkcount; |
630b122b | 291 | static struct code_stub stubs[MAXBLOCK*3]; |
e2b5e7aa | 292 | static int stubcount; |
293 | static u_int literals[1024][2]; | |
294 | static int literalcount; | |
295 | static int is_delayslot; | |
e2b5e7aa | 296 | static char shadow[1048576] __attribute__((aligned(16))); |
297 | static void *copy; | |
432435ea | 298 | static u_int expirep; |
e2b5e7aa | 299 | static u_int stop_after_jal; |
7c8454e3 | 300 | static u_int f1_hack; |
55cadc36 | 301 | #ifdef STAT_PRINT |
302 | static int stat_bc_direct; | |
303 | static int stat_bc_pre; | |
304 | static int stat_bc_restore; | |
048fcced | 305 | static int stat_ht_lookups; |
55cadc36 | 306 | static int stat_jump_in_lookups; |
307 | static int stat_restore_tries; | |
308 | static int stat_restore_compares; | |
309 | static int stat_inv_addr_calls; | |
310 | static int stat_inv_hits; | |
048fcced | 311 | static int stat_blocks; |
312 | static int stat_links; | |
55cadc36 | 313 | #define stat_inc(s) s++ |
048fcced | 314 | #define stat_dec(s) s-- |
315 | #define stat_clear(s) s = 0 | |
55cadc36 | 316 | #else |
317 | #define stat_inc(s) | |
048fcced | 318 | #define stat_dec(s) |
319 | #define stat_clear(s) | |
55cadc36 | 320 | #endif |
e2b5e7aa | 321 | |
322 | int new_dynarec_hacks; | |
630b122b | 323 | int new_dynarec_hacks_pergame; |
324 | int new_dynarec_hacks_old; | |
e2b5e7aa | 325 | int new_dynarec_did_compile; |
630b122b | 326 | |
327 | #define HACK_ENABLED(x) ((new_dynarec_hacks | new_dynarec_hacks_pergame) & (x)) | |
328 | ||
5753f874 | 329 | extern int cycle_count; // ... until end of the timeslice, counts -N -> 0 (CCREG) |
630b122b | 330 | extern int last_count; // last absolute target, often = next_interupt |
331 | extern int pcaddr; | |
332 | extern int pending_exception; | |
333 | extern int branch_target; | |
334 | extern uintptr_t ram_offset; | |
335 | extern uintptr_t mini_ht[32][2]; | |
57871462 | 336 | |
337 | /* registers that may be allocated */ | |
338 | /* 1-31 gpr */ | |
630b122b | 339 | #define LOREG 32 // lo |
340 | #define HIREG 33 // hi | |
341 | //#define FSREG 34 // FPU status (FCSR) | |
5753f874 | 342 | //#define CSREG 35 // Coprocessor status |
57871462 | 343 | #define CCREG 36 // Cycle count |
344 | #define INVCP 37 // Pointer to invalid_code | |
1edfcc68 | 345 | //#define MMREG 38 // Pointer to memory_map |
e6e590d3 | 346 | #define ROREG 39 // ram offset (if psxM != 0x80000000) |
619e5ded | 347 | #define TEMPREG 40 |
e6e590d3 | 348 | #define FTEMP 40 // Load/store temporary register (was fpu) |
619e5ded | 349 | #define PTEMP 41 // Prefetch temporary register |
1edfcc68 | 350 | //#define TLREG 42 // TLB mapping offset |
619e5ded | 351 | #define RHASH 43 // Return address hash |
352 | #define RHTBL 44 // Return address hash table address | |
353 | #define RTEMP 45 // JR/JALR address register | |
354 | #define MAXREG 45 | |
259dbd60 | 355 | #define AGEN1 46 // Address generation temporary register (pass5b_preallocate2) |
1edfcc68 | 356 | //#define AGEN2 47 // Address generation temporary register |
57871462 | 357 | |
358 | /* instruction types */ | |
359 | #define NOP 0 // No operation | |
360 | #define LOAD 1 // Load | |
361 | #define STORE 2 // Store | |
362 | #define LOADLR 3 // Unaligned load | |
363 | #define STORELR 4 // Unaligned store | |
f2e25348 | 364 | #define MOV 5 // Move (hi/lo only) |
57871462 | 365 | #define ALU 6 // Arithmetic/logic |
366 | #define MULTDIV 7 // Multiply/divide | |
367 | #define SHIFT 8 // Shift by register | |
368 | #define SHIFTIMM 9// Shift by immediate | |
369 | #define IMM16 10 // 16-bit immediate | |
370 | #define RJUMP 11 // Unconditional jump to register | |
371 | #define UJUMP 12 // Unconditional jump | |
372 | #define CJUMP 13 // Conditional branch (BEQ/BNE/BGTZ/BLEZ) | |
373 | #define SJUMP 14 // Conditional branch (regimm format) | |
374 | #define COP0 15 // Coprocessor 0 | |
f2e25348 | 375 | #define RFE 16 |
467357cc | 376 | #define SYSCALL 22// SYSCALL,BREAK |
f2e25348 | 377 | #define OTHER 23 // Other/unknown - do nothing |
7139f3c8 | 378 | #define HLECALL 26// PCSX fake opcodes for HLE |
b9b61529 | 379 | #define COP2 27 // Coprocessor 2 move |
380 | #define C2LS 28 // Coprocessor 2 load/store | |
381 | #define C2OP 29 // Coprocessor 2 operation | |
1e973cb0 | 382 | #define INTCALL 30// Call interpreter to handle rare corner cases |
57871462 | 383 | |
57871462 | 384 | /* branch codes */ |
385 | #define TAKEN 1 | |
386 | #define NOTTAKEN 2 | |
57871462 | 387 | |
630b122b | 388 | #define DJT_1 (void *)1l // no function, just a label in assem_debug log |
389 | #define DJT_2 (void *)2l | |
390 | ||
57871462 | 391 | // asm linkage |
57871462 | 392 | void dyna_linker(); |
57871462 | 393 | void cc_interrupt(); |
467357cc | 394 | void jump_syscall (u_int u0, u_int u1, u_int pc); |
395 | void jump_syscall_ds(u_int u0, u_int u1, u_int pc); | |
396 | void jump_break (u_int u0, u_int u1, u_int pc); | |
397 | void jump_break_ds(u_int u0, u_int u1, u_int pc); | |
f2e25348 | 398 | void jump_overflow (u_int u0, u_int u1, u_int pc); |
399 | void jump_overflow_ds(u_int u0, u_int u1, u_int pc); | |
259dbd60 | 400 | void jump_addrerror (u_int cause, u_int addr, u_int pc); |
401 | void jump_addrerror_ds(u_int cause, u_int addr, u_int pc); | |
630b122b | 402 | void jump_to_new_pc(); |
403 | void call_gteStall(); | |
7139f3c8 | 404 | void new_dyna_leave(); |
57871462 | 405 | |
048fcced | 406 | void *ndrc_get_addr_ht_param(u_int vaddr, int can_compile); |
407 | void *ndrc_get_addr_ht(u_int vaddr); | |
048fcced | 408 | void ndrc_add_jump_out(u_int vaddr, void *src); |
bdbf4466 | 409 | void ndrc_write_invalidate_one(u_int addr); |
410 | static void ndrc_write_invalidate_many(u_int addr, u_int end); | |
048fcced | 411 | |
412 | static int new_recompile_block(u_int addr); | |
413 | static void invalidate_block(struct block_info *block); | |
f2e25348 | 414 | static void exception_assemble(int i, const struct regstat *i_regs, int ccadj_); |
bfdecce3 | 415 | |
57871462 | 416 | // Needed by assembler |
a3c5fc39 | 417 | static void wb_register(signed char r, const signed char regmap[], u_int dirty); |
418 | static void wb_dirtys(const signed char i_regmap[], u_int i_dirty); | |
419 | static void wb_needed_dirtys(const signed char i_regmap[], u_int i_dirty, int addr); | |
630b122b | 420 | static void load_all_regs(const signed char i_regmap[]); |
421 | static void load_needed_regs(const signed char i_regmap[], const signed char next_regmap[]); | |
e2b5e7aa | 422 | static void load_regs_entry(int t); |
630b122b | 423 | static void load_all_consts(const signed char regmap[], u_int dirty, int i); |
424 | static u_int get_host_reglist(const signed char *regmap); | |
e2b5e7aa | 425 | |
5753f874 | 426 | static int get_final_value(int hr, int i, u_int *value); |
630b122b | 427 | static void add_stub(enum stub_type type, void *addr, void *retaddr, |
428 | u_int a, uintptr_t b, uintptr_t c, u_int d, u_int e); | |
429 | static void add_stub_r(enum stub_type type, void *addr, void *retaddr, | |
430 | int i, int addr_reg, const struct regstat *i_regs, int ccadj, u_int reglist); | |
431 | static void add_to_linker(void *addr, u_int target, int ext); | |
630b122b | 432 | static void *get_direct_memhandler(void *table, u_int addr, |
433 | enum stub_type type, uintptr_t *addr_host); | |
434 | static void cop2_do_stall_check(u_int op, int i, const struct regstat *i_regs, u_int reglist); | |
435 | static void pass_args(int a0, int a1); | |
436 | static void emit_far_jump(const void *f); | |
437 | static void emit_far_call(const void *f); | |
57871462 | 438 | |
af4a16ff | 439 | #ifdef VITA |
440 | #include <psp2/kernel/sysmem.h> | |
441 | static int sceBlock; | |
442 | // note: this interacts with RetroArch's Vita bootstrap code: bootstrap/vita/sbrk.c | |
443 | extern int getVMBlock(); | |
444 | int _newlib_vm_size_user = sizeof(*ndrc); | |
445 | #endif | |
446 | ||
d148d265 | 447 | static void mprotect_w_x(void *start, void *end, int is_x) |
448 | { | |
449 | #ifdef NO_WRITE_EXEC | |
1e212a25 | 450 | #if defined(VITA) |
451 | // *Open* enables write on all memory that was | |
452 | // allocated by sceKernelAllocMemBlockForVM()? | |
453 | if (is_x) | |
454 | sceKernelCloseVMDomain(); | |
455 | else | |
456 | sceKernelOpenVMDomain(); | |
7c404fb9 | 457 | #elif defined(HAVE_LIBNX) |
458 | Result rc; | |
7f9e081d | 459 | // check to avoid the full flush in jitTransitionToExecutable() |
460 | if (g_jit.type != JitType_CodeMemory) { | |
461 | if (is_x) | |
462 | rc = jitTransitionToExecutable(&g_jit); | |
463 | else | |
464 | rc = jitTransitionToWritable(&g_jit); | |
465 | if (R_FAILED(rc)) | |
466 | ;//SysPrintf("jitTransition %d %08x\n", is_x, rc); | |
467 | } | |
468 | #elif defined(TC_WRITE_OFFSET) | |
7c404fb9 | 469 | // separated rx and rw areas are always available |
1e212a25 | 470 | #else |
d148d265 | 471 | u_long mstart = (u_long)start & ~4095ul; |
472 | u_long mend = (u_long)end; | |
473 | if (mprotect((void *)mstart, mend - mstart, | |
474 | PROT_READ | (is_x ? PROT_EXEC : PROT_WRITE)) != 0) | |
475 | SysPrintf("mprotect(%c) failed: %s\n", is_x ? 'x' : 'w', strerror(errno)); | |
1e212a25 | 476 | #endif |
d148d265 | 477 | #endif |
478 | } | |
479 | ||
7f9e081d | 480 | static void start_tcache_write(void *start, void *end) |
d148d265 | 481 | { |
482 | mprotect_w_x(start, end, 0); | |
483 | } | |
484 | ||
485 | static void end_tcache_write(void *start, void *end) | |
486 | { | |
630b122b | 487 | #if defined(__arm__) || defined(__aarch64__) |
d148d265 | 488 | size_t len = (char *)end - (char *)start; |
489 | #if defined(__BLACKBERRY_QNX__) | |
490 | msync(start, len, MS_SYNC | MS_CACHE_ONLY | MS_INVALIDATE_ICACHE); | |
491 | #elif defined(__MACH__) | |
492 | sys_cache_control(kCacheFunctionPrepareForExecution, start, len); | |
493 | #elif defined(VITA) | |
1e212a25 | 494 | sceKernelSyncVMDomain(sceBlock, start, len); |
495 | #elif defined(_3DS) | |
496 | ctr_flush_invalidate_cache(); | |
7c404fb9 | 497 | #elif defined(HAVE_LIBNX) |
7f9e081d | 498 | if (g_jit.type == JitType_CodeMemory) { |
499 | armDCacheClean(start, len); | |
500 | armICacheInvalidate((char *)start - ndrc_write_ofs, len); | |
0739265d | 501 | // as of v4.2.1 libnx lacks isb |
502 | __asm__ volatile("isb" ::: "memory"); | |
7f9e081d | 503 | } |
630b122b | 504 | #elif defined(__aarch64__) |
505 | // as of 2021, __clear_cache() is still broken on arm64 | |
506 | // so here is a custom one :( | |
507 | clear_cache_arm64(start, end); | |
d148d265 | 508 | #else |
509 | __clear_cache(start, end); | |
510 | #endif | |
511 | (void)len; | |
512 | #endif | |
513 | ||
514 | mprotect_w_x(start, end, 1); | |
515 | } | |
516 | ||
517 | static void *start_block(void) | |
518 | { | |
519 | u_char *end = out + MAX_OUTPUT_BLOCK_SIZE; | |
630b122b | 520 | if (end > ndrc->translation_cache + sizeof(ndrc->translation_cache)) |
521 | end = ndrc->translation_cache + sizeof(ndrc->translation_cache); | |
7f9e081d | 522 | start_tcache_write(NDRC_WRITE_OFFSET(out), NDRC_WRITE_OFFSET(end)); |
d148d265 | 523 | return out; |
524 | } | |
525 | ||
526 | static void end_block(void *start) | |
527 | { | |
7f9e081d | 528 | end_tcache_write(NDRC_WRITE_OFFSET(start), NDRC_WRITE_OFFSET(out)); |
d148d265 | 529 | } |
530 | ||
8b7cb447 | 531 | #ifdef NDRC_CACHE_FLUSH_ALL |
532 | ||
533 | static int needs_clear_cache; | |
534 | ||
535 | static void mark_clear_cache(void *target) | |
536 | { | |
537 | if (!needs_clear_cache) { | |
7f9e081d | 538 | start_tcache_write(NDRC_WRITE_OFFSET(ndrc), NDRC_WRITE_OFFSET(ndrc + 1)); |
8b7cb447 | 539 | needs_clear_cache = 1; |
540 | } | |
541 | } | |
542 | ||
543 | static void do_clear_cache(void) | |
544 | { | |
545 | if (needs_clear_cache) { | |
7f9e081d | 546 | end_tcache_write(NDRC_WRITE_OFFSET(ndrc), NDRC_WRITE_OFFSET(ndrc + 1)); |
8b7cb447 | 547 | needs_clear_cache = 0; |
548 | } | |
549 | } | |
550 | ||
551 | #else | |
552 | ||
630b122b | 553 | // also takes care of w^x mappings when patching code |
554 | static u_int needs_clear_cache[1<<(TARGET_SIZE_2-17)]; | |
555 | ||
556 | static void mark_clear_cache(void *target) | |
557 | { | |
558 | uintptr_t offset = (u_char *)target - ndrc->translation_cache; | |
559 | u_int mask = 1u << ((offset >> 12) & 31); | |
560 | if (!(needs_clear_cache[offset >> 17] & mask)) { | |
7f9e081d | 561 | char *start = (char *)NDRC_WRITE_OFFSET((uintptr_t)target & ~4095l); |
630b122b | 562 | start_tcache_write(start, start + 4095); |
563 | needs_clear_cache[offset >> 17] |= mask; | |
564 | } | |
565 | } | |
566 | ||
567 | // Clearing the cache is rather slow on ARM Linux, so mark the areas | |
568 | // that need to be cleared, and then only clear these areas once. | |
569 | static void do_clear_cache(void) | |
570 | { | |
571 | int i, j; | |
572 | for (i = 0; i < (1<<(TARGET_SIZE_2-17)); i++) | |
573 | { | |
574 | u_int bitmap = needs_clear_cache[i]; | |
575 | if (!bitmap) | |
576 | continue; | |
577 | for (j = 0; j < 32; j++) | |
578 | { | |
579 | u_char *start, *end; | |
432435ea | 580 | if (!(bitmap & (1u << j))) |
630b122b | 581 | continue; |
582 | ||
583 | start = ndrc->translation_cache + i*131072 + j*4096; | |
584 | end = start + 4095; | |
585 | for (j++; j < 32; j++) { | |
432435ea | 586 | if (!(bitmap & (1u << j))) |
630b122b | 587 | break; |
588 | end += 4096; | |
589 | } | |
7f9e081d | 590 | end_tcache_write(NDRC_WRITE_OFFSET(start), NDRC_WRITE_OFFSET(end)); |
630b122b | 591 | } |
592 | needs_clear_cache[i] = 0; | |
593 | } | |
594 | } | |
595 | ||
8b7cb447 | 596 | #endif // NDRC_CACHE_FLUSH_ALL |
57871462 | 597 | |
b6e87b2b | 598 | #define NO_CYCLE_PENALTY_THR 12 |
599 | ||
630b122b | 600 | int cycle_multiplier_old; |
601 | static int cycle_multiplier_active; | |
4e9dcd7f | 602 | |
603 | static int CLOCK_ADJUST(int x) | |
604 | { | |
630b122b | 605 | int m = cycle_multiplier_active; |
606 | int s = (x >> 31) | 1; | |
607 | return (x * m + s * 50) / 100; | |
608 | } | |
609 | ||
610 | static int ds_writes_rjump_rs(int i) | |
611 | { | |
3a64d2f7 | 612 | return dops[i].rs1 != 0 |
613 | && (dops[i].rs1 == dops[i+1].rt1 || dops[i].rs1 == dops[i+1].rt2 | |
614 | || dops[i].rs1 == dops[i].rt1); // overwrites itself - same effect | |
4e9dcd7f | 615 | } |
616 | ||
048fcced | 617 | // psx addr mirror masking (for invalidation) |
618 | static u_int pmmask(u_int vaddr) | |
619 | { | |
620 | vaddr &= ~0xe0000000; | |
621 | if (vaddr < 0x01000000) | |
622 | vaddr &= ~0x00e00000; // RAM mirrors | |
623 | return vaddr; | |
624 | } | |
625 | ||
94d23bb9 | 626 | static u_int get_page(u_int vaddr) |
57871462 | 627 | { |
048fcced | 628 | u_int page = pmmask(vaddr) >> 12; |
432435ea | 629 | if (page >= PAGE_COUNT / 2) |
630 | page = PAGE_COUNT / 2 + (page & (PAGE_COUNT / 2 - 1)); | |
94d23bb9 | 631 | return page; |
632 | } | |
633 | ||
048fcced | 634 | // get a page for looking for a block that has vaddr |
635 | // (needed because the block may start in previous page) | |
636 | static u_int get_page_prev(u_int vaddr) | |
d25604ca | 637 | { |
048fcced | 638 | assert(MAXBLOCK <= (1 << 12)); |
639 | u_int page = get_page(vaddr); | |
640 | if (page & 511) | |
641 | page--; | |
642 | return page; | |
d25604ca | 643 | } |
94d23bb9 | 644 | |
630b122b | 645 | static struct ht_entry *hash_table_get(u_int vaddr) |
646 | { | |
647 | return &hash_table[((vaddr>>16)^vaddr)&0xFFFF]; | |
648 | } | |
649 | ||
c980be0e | 650 | #define HASH_TABLE_BAD 0xbac |
651 | ||
652 | static void hash_table_clear(void) | |
653 | { | |
654 | struct ht_entry *ht_bin; | |
655 | int i, j; | |
656 | for (i = 0; i < ARRAY_SIZE(hash_table); i++) { | |
657 | for (j = 0; j < ARRAY_SIZE(hash_table[i].vaddr); j++) { | |
658 | hash_table[i].vaddr[j] = ~0; | |
659 | hash_table[i].tcaddr[j] = (void *)(uintptr_t)HASH_TABLE_BAD; | |
660 | } | |
661 | } | |
662 | // don't allow ~0 to hit | |
663 | ht_bin = hash_table_get(~0); | |
664 | for (j = 0; j < ARRAY_SIZE(ht_bin->vaddr); j++) | |
665 | ht_bin->vaddr[j] = 1; | |
666 | } | |
667 | ||
048fcced | 668 | static void hash_table_add(u_int vaddr, void *tcaddr) |
630b122b | 669 | { |
048fcced | 670 | struct ht_entry *ht_bin = hash_table_get(vaddr); |
671 | assert(tcaddr); | |
630b122b | 672 | ht_bin->vaddr[1] = ht_bin->vaddr[0]; |
673 | ht_bin->tcaddr[1] = ht_bin->tcaddr[0]; | |
674 | ht_bin->vaddr[0] = vaddr; | |
675 | ht_bin->tcaddr[0] = tcaddr; | |
676 | } | |
677 | ||
048fcced | 678 | static void hash_table_remove(int vaddr) |
679 | { | |
680 | //printf("remove hash: %x\n",vaddr); | |
681 | struct ht_entry *ht_bin = hash_table_get(vaddr); | |
682 | if (ht_bin->vaddr[1] == vaddr) { | |
c980be0e | 683 | ht_bin->vaddr[1] = ~0; |
684 | ht_bin->tcaddr[1] = (void *)(uintptr_t)HASH_TABLE_BAD; | |
048fcced | 685 | } |
686 | if (ht_bin->vaddr[0] == vaddr) { | |
687 | ht_bin->vaddr[0] = ht_bin->vaddr[1]; | |
688 | ht_bin->tcaddr[0] = ht_bin->tcaddr[1]; | |
c980be0e | 689 | ht_bin->vaddr[1] = ~0; |
690 | ht_bin->tcaddr[1] = (void *)(uintptr_t)HASH_TABLE_BAD; | |
048fcced | 691 | } |
692 | } | |
693 | ||
c980be0e | 694 | static void mini_ht_clear(void) |
695 | { | |
696 | #ifdef USE_MINI_HT | |
697 | int i; | |
698 | for (i = 0; i < ARRAY_SIZE(mini_ht) - 1; i++) { | |
699 | mini_ht[i][0] = ~0; | |
700 | mini_ht[i][1] = HASH_TABLE_BAD; | |
701 | } | |
702 | mini_ht[i][0] = 1; | |
703 | mini_ht[i][1] = HASH_TABLE_BAD; | |
704 | #endif | |
705 | } | |
706 | ||
048fcced | 707 | static void mark_invalid_code(u_int vaddr, u_int len, char invalid) |
bfdecce3 | 708 | { |
40b19b53 | 709 | u_int vaddr_m = vaddr & 0x1fffffff; |
bfdecce3 | 710 | u_int i, j; |
40b19b53 | 711 | for (i = vaddr_m & ~0xfff; i < vaddr_m + len; i += 0x1000) { |
bfdecce3 | 712 | // ram mirrors, but should not hurt bios |
713 | for (j = 0; j < 0x800000; j += 0x200000) { | |
714 | invalid_code[(i|j) >> 12] = | |
715 | invalid_code[(i|j|0x80000000u) >> 12] = | |
048fcced | 716 | invalid_code[(i|j|0xa0000000u) >> 12] = invalid; |
bfdecce3 | 717 | } |
718 | } | |
b9e27215 | 719 | if (!invalid && vaddr + len > inv_code_start && vaddr <= inv_code_end) |
048fcced | 720 | inv_code_start = inv_code_end = ~0; |
bfdecce3 | 721 | } |
722 | ||
432435ea | 723 | static int doesnt_expire_soon(u_char *tcaddr) |
630b122b | 724 | { |
432435ea | 725 | u_int diff = (u_int)(tcaddr - out) & ((1u << TARGET_SIZE_2) - 1u); |
726 | return diff > EXPIRITY_OFFSET + MAX_OUTPUT_BLOCK_SIZE; | |
630b122b | 727 | } |
728 | ||
bdbf4466 | 729 | static unused void check_for_block_changes(u_int start, u_int end) |
730 | { | |
731 | u_int start_page = get_page_prev(start); | |
732 | u_int end_page = get_page(end - 1); | |
733 | u_int page; | |
734 | ||
735 | for (page = start_page; page <= end_page; page++) { | |
736 | struct block_info *block; | |
737 | for (block = blocks[page]; block != NULL; block = block->next) { | |
738 | if (block->is_dirty) | |
739 | continue; | |
740 | if (memcmp(block->source, block->copy, block->len)) { | |
741 | printf("bad block %08x-%08x %016llx %016llx @%08x\n", | |
742 | block->start, block->start + block->len, | |
743 | *(long long *)block->source, *(long long *)block->copy, psxRegs.pc); | |
744 | fflush(stdout); | |
745 | abort(); | |
746 | } | |
747 | } | |
748 | } | |
749 | } | |
750 | ||
048fcced | 751 | static void *try_restore_block(u_int vaddr, u_int start_page, u_int end_page) |
bfdecce3 | 752 | { |
048fcced | 753 | void *found_clean = NULL; |
754 | u_int i, page; | |
bfdecce3 | 755 | |
55cadc36 | 756 | stat_inc(stat_restore_tries); |
048fcced | 757 | for (page = start_page; page <= end_page; page++) { |
758 | struct block_info *block; | |
759 | for (block = blocks[page]; block != NULL; block = block->next) { | |
760 | if (vaddr < block->start) | |
761 | break; | |
762 | if (!block->is_dirty || vaddr >= block->start + block->len) | |
763 | continue; | |
764 | for (i = 0; i < block->jump_in_cnt; i++) | |
765 | if (block->jump_in[i].vaddr == vaddr) | |
766 | break; | |
767 | if (i == block->jump_in_cnt) | |
768 | continue; | |
769 | assert(block->source && block->copy); | |
770 | stat_inc(stat_restore_compares); | |
771 | if (memcmp(block->source, block->copy, block->len)) | |
772 | continue; | |
bfdecce3 | 773 | |
11eca54f | 774 | block->is_dirty = block->inv_near_misses = 0; |
048fcced | 775 | found_clean = block->jump_in[i].addr; |
776 | hash_table_add(vaddr, found_clean); | |
777 | mark_invalid_code(block->start, block->len, 0); | |
778 | stat_inc(stat_bc_restore); | |
779 | inv_debug("INV: restored %08x %p (%d)\n", vaddr, found_clean, block->jump_in_cnt); | |
780 | return found_clean; | |
bfdecce3 | 781 | } |
bfdecce3 | 782 | } |
048fcced | 783 | return NULL; |
bfdecce3 | 784 | } |
785 | ||
5753f874 | 786 | // this doesn't normally happen |
787 | static noinline u_int generate_exception(u_int pc) | |
788 | { | |
789 | //if (execBreakCheck(&psxRegs, pc)) | |
790 | // return psxRegs.pc; | |
791 | ||
792 | // generate an address or bus error | |
793 | psxRegs.CP0.n.Cause &= 0x300; | |
794 | psxRegs.CP0.n.EPC = pc; | |
795 | if (pc & 3) { | |
796 | psxRegs.CP0.n.Cause |= R3000E_AdEL << 2; | |
797 | psxRegs.CP0.n.BadVAddr = pc; | |
798 | #ifdef DRC_DBG | |
799 | last_count -= 2; | |
800 | #endif | |
801 | } else | |
802 | psxRegs.CP0.n.Cause |= R3000E_IBE << 2; | |
803 | return (psxRegs.pc = 0x80000080); | |
804 | } | |
805 | ||
94d23bb9 | 806 | // Get address from virtual address |
807 | // This is called from the recompiled JR/JALR instructions | |
048fcced | 808 | static void noinline *get_addr(u_int vaddr, int can_compile) |
94d23bb9 | 809 | { |
048fcced | 810 | u_int start_page = get_page_prev(vaddr); |
811 | u_int i, page, end_page = get_page(vaddr); | |
812 | void *found_clean = NULL; | |
bfdecce3 | 813 | |
55cadc36 | 814 | stat_inc(stat_jump_in_lookups); |
048fcced | 815 | for (page = start_page; page <= end_page; page++) { |
816 | const struct block_info *block; | |
817 | for (block = blocks[page]; block != NULL; block = block->next) { | |
818 | if (vaddr < block->start) | |
819 | break; | |
820 | if (block->is_dirty || vaddr >= block->start + block->len) | |
821 | continue; | |
822 | for (i = 0; i < block->jump_in_cnt; i++) | |
823 | if (block->jump_in[i].vaddr == vaddr) | |
824 | break; | |
825 | if (i == block->jump_in_cnt) | |
826 | continue; | |
827 | found_clean = block->jump_in[i].addr; | |
828 | hash_table_add(vaddr, found_clean); | |
829 | return found_clean; | |
57871462 | 830 | } |
57871462 | 831 | } |
048fcced | 832 | found_clean = try_restore_block(vaddr, start_page, end_page); |
833 | if (found_clean) | |
834 | return found_clean; | |
835 | ||
836 | if (!can_compile) | |
837 | return NULL; | |
bfdecce3 | 838 | |
839 | int r = new_recompile_block(vaddr); | |
5753f874 | 840 | if (likely(r == 0)) |
048fcced | 841 | return ndrc_get_addr_ht(vaddr); |
0bfdd1aa | 842 | |
5753f874 | 843 | return ndrc_get_addr_ht(generate_exception(vaddr)); |
57871462 | 844 | } |
048fcced | 845 | |
57871462 | 846 | // Look up address in hash table first |
048fcced | 847 | void *ndrc_get_addr_ht_param(u_int vaddr, int can_compile) |
57871462 | 848 | { |
bdbf4466 | 849 | //check_for_block_changes(vaddr, vaddr + MAXBLOCK); |
630b122b | 850 | const struct ht_entry *ht_bin = hash_table_get(vaddr); |
259dbd60 | 851 | u_int vaddr_a = vaddr & ~3; |
048fcced | 852 | stat_inc(stat_ht_lookups); |
259dbd60 | 853 | if (ht_bin->vaddr[0] == vaddr_a) return ht_bin->tcaddr[0]; |
854 | if (ht_bin->vaddr[1] == vaddr_a) return ht_bin->tcaddr[1]; | |
048fcced | 855 | return get_addr(vaddr, can_compile); |
856 | } | |
857 | ||
858 | void *ndrc_get_addr_ht(u_int vaddr) | |
859 | { | |
860 | return ndrc_get_addr_ht_param(vaddr, 1); | |
57871462 | 861 | } |
862 | ||
b15d122e | 863 | static void clear_all_regs(signed char regmap[]) |
57871462 | 864 | { |
b15d122e | 865 | memset(regmap, -1, sizeof(regmap[0]) * HOST_REGS); |
57871462 | 866 | } |
867 | ||
e912c27d | 868 | // get_reg: get allocated host reg from mips reg |
869 | // returns -1 if no such mips reg was allocated | |
9a6c6e37 | 870 | #if defined(__arm__) && defined(HAVE_ARMV6) && HOST_REGS == 13 && EXCLUDE_REG == 11 |
871 | ||
872 | extern signed char get_reg(const signed char regmap[], signed char r); | |
873 | ||
874 | #else | |
875 | ||
91af94f0 | 876 | static signed char get_reg(const signed char regmap[], signed char r) |
57871462 | 877 | { |
878 | int hr; | |
91af94f0 | 879 | for (hr = 0; hr < HOST_REGS; hr++) { |
880 | if (hr == EXCLUDE_REG) | |
881 | continue; | |
882 | if (regmap[hr] == r) | |
883 | return hr; | |
884 | } | |
885 | return -1; | |
886 | } | |
887 | ||
9a6c6e37 | 888 | #endif |
889 | ||
f2e25348 | 890 | // get reg suitable for writing |
891 | static signed char get_reg_w(const signed char regmap[], signed char r) | |
892 | { | |
893 | return r == 0 ? -1 : get_reg(regmap, r); | |
894 | } | |
895 | ||
e912c27d | 896 | // get reg as mask bit (1 << hr) |
897 | static u_int get_regm(const signed char regmap[], signed char r) | |
898 | { | |
899 | return (1u << (get_reg(regmap, r) & 31)) & ~(1u << 31); | |
900 | } | |
901 | ||
91af94f0 | 902 | static signed char get_reg_temp(const signed char regmap[]) |
903 | { | |
904 | int hr; | |
905 | for (hr = 0; hr < HOST_REGS; hr++) { | |
906 | if (hr == EXCLUDE_REG) | |
907 | continue; | |
908 | if (regmap[hr] == (signed char)-1) | |
909 | return hr; | |
910 | } | |
57871462 | 911 | return -1; |
912 | } | |
913 | ||
914 | // Find a register that is available for two consecutive cycles | |
630b122b | 915 | static signed char get_reg2(signed char regmap1[], const signed char regmap2[], int r) |
57871462 | 916 | { |
917 | int hr; | |
918 | for (hr=0;hr<HOST_REGS;hr++) if(hr!=EXCLUDE_REG&®map1[hr]==r&®map2[hr]==r) return hr; | |
919 | return -1; | |
920 | } | |
921 | ||
ed14d777 | 922 | // reverse reg map: mips -> host |
923 | #define RRMAP_SIZE 64 | |
924 | static void make_rregs(const signed char regmap[], signed char rrmap[RRMAP_SIZE], | |
925 | u_int *regs_can_change) | |
926 | { | |
927 | u_int r, hr, hr_can_change = 0; | |
928 | memset(rrmap, -1, RRMAP_SIZE); | |
929 | for (hr = 0; hr < HOST_REGS; ) | |
930 | { | |
931 | r = regmap[hr]; | |
932 | rrmap[r & (RRMAP_SIZE - 1)] = hr; | |
933 | // only add mips $1-$31+$lo, others shifted out | |
934 | hr_can_change |= (uint64_t)1 << (hr + ((r - 1) & 32)); | |
935 | hr++; | |
936 | if (hr == EXCLUDE_REG) | |
937 | hr++; | |
938 | } | |
939 | hr_can_change |= 1u << (rrmap[33] & 31); | |
940 | hr_can_change |= 1u << (rrmap[CCREG] & 31); | |
941 | hr_can_change &= ~(1u << 31); | |
942 | *regs_can_change = hr_can_change; | |
943 | } | |
944 | ||
945 | // same as get_reg, but takes rrmap | |
946 | static signed char get_rreg(signed char rrmap[RRMAP_SIZE], signed char r) | |
947 | { | |
948 | assert(0 <= r && r < RRMAP_SIZE); | |
949 | return rrmap[r]; | |
950 | } | |
951 | ||
91af94f0 | 952 | static int count_free_regs(const signed char regmap[]) |
57871462 | 953 | { |
954 | int count=0; | |
955 | int hr; | |
956 | for(hr=0;hr<HOST_REGS;hr++) | |
957 | { | |
958 | if(hr!=EXCLUDE_REG) { | |
959 | if(regmap[hr]<0) count++; | |
960 | } | |
961 | } | |
962 | return count; | |
963 | } | |
964 | ||
91af94f0 | 965 | static void dirty_reg(struct regstat *cur, signed char reg) |
57871462 | 966 | { |
967 | int hr; | |
91af94f0 | 968 | if (!reg) return; |
969 | hr = get_reg(cur->regmap, reg); | |
970 | if (hr >= 0) | |
971 | cur->dirty |= 1<<hr; | |
57871462 | 972 | } |
973 | ||
630b122b | 974 | static void set_const(struct regstat *cur, signed char reg, uint32_t value) |
57871462 | 975 | { |
976 | int hr; | |
91af94f0 | 977 | if (!reg) return; |
978 | hr = get_reg(cur->regmap, reg); | |
979 | if (hr >= 0) { | |
980 | cur->isconst |= 1<<hr; | |
981 | current_constmap[hr] = value; | |
57871462 | 982 | } |
983 | } | |
984 | ||
630b122b | 985 | static void clear_const(struct regstat *cur, signed char reg) |
57871462 | 986 | { |
987 | int hr; | |
91af94f0 | 988 | if (!reg) return; |
989 | hr = get_reg(cur->regmap, reg); | |
990 | if (hr >= 0) | |
991 | cur->isconst &= ~(1<<hr); | |
57871462 | 992 | } |
993 | ||
91af94f0 | 994 | static int is_const(const struct regstat *cur, signed char reg) |
57871462 | 995 | { |
996 | int hr; | |
91af94f0 | 997 | if (reg < 0) return 0; |
998 | if (!reg) return 1; | |
999 | hr = get_reg(cur->regmap, reg); | |
1000 | if (hr >= 0) | |
1001 | return (cur->isconst>>hr)&1; | |
57871462 | 1002 | return 0; |
1003 | } | |
630b122b | 1004 | |
91af94f0 | 1005 | static uint32_t get_const(const struct regstat *cur, signed char reg) |
57871462 | 1006 | { |
1007 | int hr; | |
91af94f0 | 1008 | if (!reg) return 0; |
1009 | hr = get_reg(cur->regmap, reg); | |
1010 | if (hr >= 0) | |
1011 | return current_constmap[hr]; | |
1012 | ||
1013 | SysPrintf("Unknown constant in r%d\n", reg); | |
630b122b | 1014 | abort(); |
57871462 | 1015 | } |
1016 | ||
1017 | // Least soon needed registers | |
1018 | // Look at the next ten instructions and see which registers | |
1019 | // will be used. Try not to reallocate these. | |
b4661440 | 1020 | static void lsn(u_char hsn[], int i) |
57871462 | 1021 | { |
1022 | int j; | |
1023 | int b=-1; | |
1024 | for(j=0;j<9;j++) | |
1025 | { | |
1026 | if(i+j>=slen) { | |
1027 | j=slen-i-1; | |
1028 | break; | |
1029 | } | |
630b122b | 1030 | if (dops[i+j].is_ujump) |
57871462 | 1031 | { |
1032 | // Don't go past an unconditonal jump | |
1033 | j++; | |
1034 | break; | |
1035 | } | |
1036 | } | |
1037 | for(;j>=0;j--) | |
1038 | { | |
630b122b | 1039 | if(dops[i+j].rs1) hsn[dops[i+j].rs1]=j; |
1040 | if(dops[i+j].rs2) hsn[dops[i+j].rs2]=j; | |
1041 | if(dops[i+j].rt1) hsn[dops[i+j].rt1]=j; | |
1042 | if(dops[i+j].rt2) hsn[dops[i+j].rt2]=j; | |
1043 | if(dops[i+j].itype==STORE || dops[i+j].itype==STORELR) { | |
57871462 | 1044 | // Stores can allocate zero |
630b122b | 1045 | hsn[dops[i+j].rs1]=j; |
1046 | hsn[dops[i+j].rs2]=j; | |
57871462 | 1047 | } |
630b122b | 1048 | if (ram_offset && (dops[i+j].is_load || dops[i+j].is_store)) |
1049 | hsn[ROREG] = j; | |
57871462 | 1050 | // On some architectures stores need invc_ptr |
1051 | #if defined(HOST_IMM8) | |
630b122b | 1052 | if (dops[i+j].is_store) |
1053 | hsn[INVCP] = j; | |
57871462 | 1054 | #endif |
630b122b | 1055 | if(i+j>=0&&(dops[i+j].itype==UJUMP||dops[i+j].itype==CJUMP||dops[i+j].itype==SJUMP)) |
57871462 | 1056 | { |
1057 | hsn[CCREG]=j; | |
1058 | b=j; | |
1059 | } | |
1060 | } | |
1061 | if(b>=0) | |
1062 | { | |
259dbd60 | 1063 | if(cinfo[i+b].ba>=start && cinfo[i+b].ba<(start+slen*4)) |
57871462 | 1064 | { |
1065 | // Follow first branch | |
259dbd60 | 1066 | int t=(cinfo[i+b].ba-start)>>2; |
57871462 | 1067 | j=7-b;if(t+j>=slen) j=slen-t-1; |
1068 | for(;j>=0;j--) | |
1069 | { | |
630b122b | 1070 | if(dops[t+j].rs1) if(hsn[dops[t+j].rs1]>j+b+2) hsn[dops[t+j].rs1]=j+b+2; |
1071 | if(dops[t+j].rs2) if(hsn[dops[t+j].rs2]>j+b+2) hsn[dops[t+j].rs2]=j+b+2; | |
1072 | //if(dops[t+j].rt1) if(hsn[dops[t+j].rt1]>j+b+2) hsn[dops[t+j].rt1]=j+b+2; | |
1073 | //if(dops[t+j].rt2) if(hsn[dops[t+j].rt2]>j+b+2) hsn[dops[t+j].rt2]=j+b+2; | |
57871462 | 1074 | } |
1075 | } | |
1076 | // TODO: preferred register based on backward branch | |
1077 | } | |
1078 | // Delay slot should preferably not overwrite branch conditions or cycle count | |
630b122b | 1079 | if (i > 0 && dops[i-1].is_jump) { |
1080 | if(dops[i-1].rs1) if(hsn[dops[i-1].rs1]>1) hsn[dops[i-1].rs1]=1; | |
1081 | if(dops[i-1].rs2) if(hsn[dops[i-1].rs2]>1) hsn[dops[i-1].rs2]=1; | |
57871462 | 1082 | hsn[CCREG]=1; |
1083 | // ...or hash tables | |
1084 | hsn[RHASH]=1; | |
1085 | hsn[RHTBL]=1; | |
1086 | } | |
1087 | // Coprocessor load/store needs FTEMP, even if not declared | |
630b122b | 1088 | if(dops[i].itype==C2LS) { |
57871462 | 1089 | hsn[FTEMP]=0; |
1090 | } | |
e6e590d3 | 1091 | // Load/store L/R also uses FTEMP as a temporary register |
1092 | if (dops[i].itype == LOADLR || dops[i].itype == STORELR) { | |
57871462 | 1093 | hsn[FTEMP]=0; |
1094 | } | |
57871462 | 1095 | // Don't remove the miniht registers |
630b122b | 1096 | if(dops[i].itype==UJUMP||dops[i].itype==RJUMP) |
57871462 | 1097 | { |
1098 | hsn[RHASH]=0; | |
1099 | hsn[RHTBL]=0; | |
1100 | } | |
1101 | } | |
1102 | ||
1103 | // We only want to allocate registers if we're going to use them again soon | |
94061aa5 | 1104 | static int needed_again(int r, int i) |
57871462 | 1105 | { |
1106 | int j; | |
1107 | int b=-1; | |
1108 | int rn=10; | |
9f51b4b9 | 1109 | |
630b122b | 1110 | if (i > 0 && dops[i-1].is_ujump) |
57871462 | 1111 | { |
259dbd60 | 1112 | if(cinfo[i-1].ba<start || cinfo[i-1].ba>start+slen*4-4) |
57871462 | 1113 | return 0; // Don't need any registers if exiting the block |
1114 | } | |
1115 | for(j=0;j<9;j++) | |
1116 | { | |
1117 | if(i+j>=slen) { | |
1118 | j=slen-i-1; | |
1119 | break; | |
1120 | } | |
630b122b | 1121 | if (dops[i+j].is_ujump) |
57871462 | 1122 | { |
1123 | // Don't go past an unconditonal jump | |
1124 | j++; | |
1125 | break; | |
1126 | } | |
f2e25348 | 1127 | if (dops[i+j].is_exception) |
57871462 | 1128 | { |
1129 | break; | |
1130 | } | |
1131 | } | |
1132 | for(;j>=1;j--) | |
1133 | { | |
630b122b | 1134 | if(dops[i+j].rs1==r) rn=j; |
1135 | if(dops[i+j].rs2==r) rn=j; | |
57871462 | 1136 | if((unneeded_reg[i+j]>>r)&1) rn=10; |
630b122b | 1137 | if(i+j>=0&&(dops[i+j].itype==UJUMP||dops[i+j].itype==CJUMP||dops[i+j].itype==SJUMP)) |
57871462 | 1138 | { |
1139 | b=j; | |
1140 | } | |
1141 | } | |
b7217e13 | 1142 | if(rn<10) return 1; |
581335b0 | 1143 | (void)b; |
57871462 | 1144 | return 0; |
1145 | } | |
1146 | ||
1147 | // Try to match register allocations at the end of a loop with those | |
1148 | // at the beginning | |
94061aa5 | 1149 | static int loop_reg(int i, int r, int hr) |
57871462 | 1150 | { |
1151 | int j,k; | |
1152 | for(j=0;j<9;j++) | |
1153 | { | |
1154 | if(i+j>=slen) { | |
1155 | j=slen-i-1; | |
1156 | break; | |
1157 | } | |
630b122b | 1158 | if (dops[i+j].is_ujump) |
57871462 | 1159 | { |
1160 | // Don't go past an unconditonal jump | |
1161 | j++; | |
1162 | break; | |
1163 | } | |
1164 | } | |
1165 | k=0; | |
1166 | if(i>0){ | |
630b122b | 1167 | if(dops[i-1].itype==UJUMP||dops[i-1].itype==CJUMP||dops[i-1].itype==SJUMP) |
57871462 | 1168 | k--; |
1169 | } | |
1170 | for(;k<j;k++) | |
1171 | { | |
630b122b | 1172 | assert(r < 64); |
1173 | if((unneeded_reg[i+k]>>r)&1) return hr; | |
1174 | if(i+k>=0&&(dops[i+k].itype==UJUMP||dops[i+k].itype==CJUMP||dops[i+k].itype==SJUMP)) | |
57871462 | 1175 | { |
259dbd60 | 1176 | if(cinfo[i+k].ba>=start && cinfo[i+k].ba<(start+i*4)) |
57871462 | 1177 | { |
259dbd60 | 1178 | int t=(cinfo[i+k].ba-start)>>2; |
57871462 | 1179 | int reg=get_reg(regs[t].regmap_entry,r); |
1180 | if(reg>=0) return reg; | |
1181 | //reg=get_reg(regs[t+1].regmap_entry,r); | |
1182 | //if(reg>=0) return reg; | |
1183 | } | |
1184 | } | |
1185 | } | |
1186 | return hr; | |
1187 | } | |
1188 | ||
1189 | ||
1190 | // Allocate every register, preserving source/target regs | |
94061aa5 | 1191 | static void alloc_all(struct regstat *cur,int i) |
57871462 | 1192 | { |
1193 | int hr; | |
9f51b4b9 | 1194 | |
57871462 | 1195 | for(hr=0;hr<HOST_REGS;hr++) { |
1196 | if(hr!=EXCLUDE_REG) { | |
91af94f0 | 1197 | if((cur->regmap[hr]!=dops[i].rs1)&&(cur->regmap[hr]!=dops[i].rs2)&& |
1198 | (cur->regmap[hr]!=dops[i].rt1)&&(cur->regmap[hr]!=dops[i].rt2)) | |
57871462 | 1199 | { |
1200 | cur->regmap[hr]=-1; | |
1201 | cur->dirty&=~(1<<hr); | |
1202 | } | |
1203 | // Don't need zeros | |
91af94f0 | 1204 | if(cur->regmap[hr]==0) |
57871462 | 1205 | { |
1206 | cur->regmap[hr]=-1; | |
1207 | cur->dirty&=~(1<<hr); | |
1208 | } | |
1209 | } | |
1210 | } | |
1211 | } | |
1212 | ||
630b122b | 1213 | #ifndef NDEBUG |
1214 | static int host_tempreg_in_use; | |
1215 | ||
1216 | static void host_tempreg_acquire(void) | |
1217 | { | |
1218 | assert(!host_tempreg_in_use); | |
1219 | host_tempreg_in_use = 1; | |
1220 | } | |
1221 | ||
1222 | static void host_tempreg_release(void) | |
1223 | { | |
1224 | host_tempreg_in_use = 0; | |
1225 | } | |
1226 | #else | |
1227 | static void host_tempreg_acquire(void) {} | |
1228 | static void host_tempreg_release(void) {} | |
1229 | #endif | |
1230 | ||
1231 | #ifdef ASSEM_PRINT | |
1232 | extern void gen_interupt(); | |
1233 | extern void do_insn_cmp(); | |
1234 | #define FUNCNAME(f) { f, " " #f } | |
1235 | static const struct { | |
1236 | void *addr; | |
1237 | const char *name; | |
1238 | } function_names[] = { | |
1239 | FUNCNAME(cc_interrupt), | |
1240 | FUNCNAME(gen_interupt), | |
048fcced | 1241 | FUNCNAME(ndrc_get_addr_ht), |
630b122b | 1242 | FUNCNAME(jump_handler_read8), |
1243 | FUNCNAME(jump_handler_read16), | |
1244 | FUNCNAME(jump_handler_read32), | |
1245 | FUNCNAME(jump_handler_write8), | |
1246 | FUNCNAME(jump_handler_write16), | |
1247 | FUNCNAME(jump_handler_write32), | |
bdbf4466 | 1248 | FUNCNAME(ndrc_write_invalidate_one), |
1249 | FUNCNAME(ndrc_write_invalidate_many), | |
630b122b | 1250 | FUNCNAME(jump_to_new_pc), |
467357cc | 1251 | FUNCNAME(jump_break), |
1252 | FUNCNAME(jump_break_ds), | |
1253 | FUNCNAME(jump_syscall), | |
1254 | FUNCNAME(jump_syscall_ds), | |
f2e25348 | 1255 | FUNCNAME(jump_overflow), |
1256 | FUNCNAME(jump_overflow_ds), | |
259dbd60 | 1257 | FUNCNAME(jump_addrerror), |
1258 | FUNCNAME(jump_addrerror_ds), | |
630b122b | 1259 | FUNCNAME(call_gteStall), |
1260 | FUNCNAME(new_dyna_leave), | |
1261 | FUNCNAME(pcsx_mtc0), | |
1262 | FUNCNAME(pcsx_mtc0_ds), | |
259dbd60 | 1263 | FUNCNAME(execI), |
1264 | #ifdef __aarch64__ | |
1265 | FUNCNAME(do_memhandler_pre), | |
1266 | FUNCNAME(do_memhandler_post), | |
1267 | #endif | |
630b122b | 1268 | #ifdef DRC_DBG |
e6e590d3 | 1269 | # ifdef __aarch64__ |
1270 | FUNCNAME(do_insn_cmp_arm64), | |
1271 | # else | |
630b122b | 1272 | FUNCNAME(do_insn_cmp), |
e6e590d3 | 1273 | # endif |
630b122b | 1274 | #endif |
630b122b | 1275 | }; |
1276 | ||
1277 | static const char *func_name(const void *a) | |
1278 | { | |
1279 | int i; | |
1280 | for (i = 0; i < sizeof(function_names)/sizeof(function_names[0]); i++) | |
1281 | if (function_names[i].addr == a) | |
1282 | return function_names[i].name; | |
1283 | return ""; | |
1284 | } | |
f2e25348 | 1285 | |
1286 | static const char *fpofs_name(u_int ofs) | |
1287 | { | |
1288 | u_int *p = (u_int *)&dynarec_local + ofs/sizeof(u_int); | |
1289 | static char buf[64]; | |
1290 | switch (ofs) { | |
1291 | #define ofscase(x) case LO_##x: return " ; " #x | |
1292 | ofscase(next_interupt); | |
5753f874 | 1293 | ofscase(cycle_count); |
f2e25348 | 1294 | ofscase(last_count); |
1295 | ofscase(pending_exception); | |
1296 | ofscase(stop); | |
1297 | ofscase(address); | |
1298 | ofscase(lo); | |
1299 | ofscase(hi); | |
1300 | ofscase(PC); | |
1301 | ofscase(cycle); | |
1302 | ofscase(mem_rtab); | |
1303 | ofscase(mem_wtab); | |
1304 | ofscase(psxH_ptr); | |
1305 | ofscase(invc_ptr); | |
1306 | ofscase(ram_offset); | |
1307 | #undef ofscase | |
1308 | } | |
1309 | buf[0] = 0; | |
1310 | if (psxRegs.GPR.r <= p && p < &psxRegs.GPR.r[32]) | |
1311 | snprintf(buf, sizeof(buf), " ; r%d", (int)(p - psxRegs.GPR.r)); | |
1312 | else if (psxRegs.CP0.r <= p && p < &psxRegs.CP0.r[32]) | |
1313 | snprintf(buf, sizeof(buf), " ; cp0 $%d", (int)(p - psxRegs.CP0.r)); | |
1314 | else if (psxRegs.CP2D.r <= p && p < &psxRegs.CP2D.r[32]) | |
1315 | snprintf(buf, sizeof(buf), " ; cp2d $%d", (int)(p - psxRegs.CP2D.r)); | |
1316 | else if (psxRegs.CP2C.r <= p && p < &psxRegs.CP2C.r[32]) | |
1317 | snprintf(buf, sizeof(buf), " ; cp2c $%d", (int)(p - psxRegs.CP2C.r)); | |
1318 | return buf; | |
1319 | } | |
630b122b | 1320 | #else |
1321 | #define func_name(x) "" | |
f2e25348 | 1322 | #define fpofs_name(x) "" |
630b122b | 1323 | #endif |
1324 | ||
57871462 | 1325 | #ifdef __i386__ |
630b122b | 1326 | #include "assem_x86.c" |
57871462 | 1327 | #endif |
1328 | #ifdef __x86_64__ | |
630b122b | 1329 | #include "assem_x64.c" |
57871462 | 1330 | #endif |
1331 | #ifdef __arm__ | |
630b122b | 1332 | #include "assem_arm.c" |
1333 | #endif | |
1334 | #ifdef __aarch64__ | |
1335 | #include "assem_arm64.c" | |
57871462 | 1336 | #endif |
1337 | ||
630b122b | 1338 | static void *get_trampoline(const void *f) |
1339 | { | |
7f9e081d | 1340 | struct ndrc_tramp *tramp = NDRC_WRITE_OFFSET(&ndrc->tramp); |
630b122b | 1341 | size_t i; |
1342 | ||
7f9e081d | 1343 | for (i = 0; i < ARRAY_SIZE(tramp->f); i++) { |
1344 | if (tramp->f[i] == f || tramp->f[i] == NULL) | |
630b122b | 1345 | break; |
1346 | } | |
7f9e081d | 1347 | if (i == ARRAY_SIZE(tramp->f)) { |
630b122b | 1348 | SysPrintf("trampoline table is full, last func %p\n", f); |
1349 | abort(); | |
1350 | } | |
7f9e081d | 1351 | if (tramp->f[i] == NULL) { |
1352 | start_tcache_write(&tramp->f[i], &tramp->f[i + 1]); | |
1353 | tramp->f[i] = f; | |
1354 | end_tcache_write(&tramp->f[i], &tramp->f[i + 1]); | |
1355 | #ifdef HAVE_LIBNX | |
1356 | // invalidate the RX mirror (unsure if necessary, but just in case...) | |
1357 | armDCacheFlush(&ndrc->tramp.f[i], sizeof(ndrc->tramp.f[i])); | |
1358 | #endif | |
630b122b | 1359 | } |
1360 | return &ndrc->tramp.ops[i]; | |
1361 | } | |
1362 | ||
1363 | static void emit_far_jump(const void *f) | |
1364 | { | |
1365 | if (can_jump_or_call(f)) { | |
1366 | emit_jmp(f); | |
1367 | return; | |
1368 | } | |
1369 | ||
1370 | f = get_trampoline(f); | |
1371 | emit_jmp(f); | |
1372 | } | |
1373 | ||
1374 | static void emit_far_call(const void *f) | |
1375 | { | |
1376 | if (can_jump_or_call(f)) { | |
1377 | emit_call(f); | |
1378 | return; | |
1379 | } | |
1380 | ||
1381 | f = get_trampoline(f); | |
1382 | emit_call(f); | |
1383 | } | |
1384 | ||
57871462 | 1385 | // Check if an address is already compiled |
1386 | // but don't return addresses which are about to expire from the cache | |
94061aa5 | 1387 | static void *check_addr(u_int vaddr) |
57871462 | 1388 | { |
630b122b | 1389 | struct ht_entry *ht_bin = hash_table_get(vaddr); |
1390 | size_t i; | |
1391 | for (i = 0; i < ARRAY_SIZE(ht_bin->vaddr); i++) { | |
1392 | if (ht_bin->vaddr[i] == vaddr) | |
432435ea | 1393 | if (doesnt_expire_soon(ht_bin->tcaddr[i])) |
048fcced | 1394 | return ht_bin->tcaddr[i]; |
57871462 | 1395 | } |
048fcced | 1396 | |
1397 | // refactor to get_addr_nocompile? | |
1398 | u_int start_page = get_page_prev(vaddr); | |
1399 | u_int page, end_page = get_page(vaddr); | |
1400 | ||
1401 | stat_inc(stat_jump_in_lookups); | |
1402 | for (page = start_page; page <= end_page; page++) { | |
1403 | const struct block_info *block; | |
1404 | for (block = blocks[page]; block != NULL; block = block->next) { | |
1405 | if (vaddr < block->start) | |
1406 | break; | |
1407 | if (block->is_dirty || vaddr >= block->start + block->len) | |
1408 | continue; | |
1409 | if (!doesnt_expire_soon(ndrc->translation_cache + block->tc_offs)) | |
1410 | continue; | |
1411 | for (i = 0; i < block->jump_in_cnt; i++) | |
1412 | if (block->jump_in[i].vaddr == vaddr) | |
1413 | break; | |
1414 | if (i == block->jump_in_cnt) | |
1415 | continue; | |
1416 | ||
1417 | // Update existing entry with current address | |
1418 | void *addr = block->jump_in[i].addr; | |
1419 | if (ht_bin->vaddr[0] == vaddr) { | |
1420 | ht_bin->tcaddr[0] = addr; | |
1421 | return addr; | |
1422 | } | |
1423 | if (ht_bin->vaddr[1] == vaddr) { | |
1424 | ht_bin->tcaddr[1] = addr; | |
1425 | return addr; | |
1426 | } | |
1427 | // Insert into hash table with low priority. | |
1428 | // Don't evict existing entries, as they are probably | |
1429 | // addresses that are being accessed frequently. | |
1430 | if (ht_bin->vaddr[0] == -1) { | |
1431 | ht_bin->vaddr[0] = vaddr; | |
1432 | ht_bin->tcaddr[0] = addr; | |
57871462 | 1433 | } |
048fcced | 1434 | else if (ht_bin->vaddr[1] == -1) { |
1435 | ht_bin->vaddr[1] = vaddr; | |
1436 | ht_bin->tcaddr[1] = addr; | |
1437 | } | |
1438 | return addr; | |
57871462 | 1439 | } |
57871462 | 1440 | } |
048fcced | 1441 | return NULL; |
57871462 | 1442 | } |
1443 | ||
048fcced | 1444 | static void blocks_clear(struct block_info **head) |
1445 | { | |
1446 | struct block_info *cur, *next; | |
1447 | ||
1448 | if ((cur = *head)) { | |
1449 | *head = NULL; | |
1450 | while (cur) { | |
1451 | next = cur->next; | |
1452 | free(cur); | |
1453 | cur = next; | |
1454 | } | |
1455 | } | |
1456 | } | |
1457 | ||
432435ea | 1458 | static int blocks_remove_matching_addrs(struct block_info **head, |
1459 | u_int base_offs, int shift) | |
048fcced | 1460 | { |
1461 | struct block_info *next; | |
432435ea | 1462 | int hit = 0; |
048fcced | 1463 | while (*head) { |
432435ea | 1464 | if ((((*head)->tc_offs ^ base_offs) >> shift) == 0) { |
bdbf4466 | 1465 | inv_debug("EXP: rm block %08x (tc_offs %x)\n", (*head)->start, (*head)->tc_offs); |
048fcced | 1466 | invalidate_block(*head); |
1467 | next = (*head)->next; | |
1468 | free(*head); | |
1469 | *head = next; | |
1470 | stat_dec(stat_blocks); | |
432435ea | 1471 | hit = 1; |
048fcced | 1472 | } |
1473 | else | |
1474 | { | |
1475 | head = &((*head)->next); | |
1476 | } | |
1477 | } | |
432435ea | 1478 | return hit; |
048fcced | 1479 | } |
57871462 | 1480 | |
1481 | // This is called when we write to a compiled block (see do_invstub) | |
366d1d2b | 1482 | static void unlink_jumps_vaddr_range(u_int start, u_int end) |
57871462 | 1483 | { |
048fcced | 1484 | u_int page, start_page = get_page(start), end_page = get_page(end - 1); |
366d1d2b | 1485 | int i; |
048fcced | 1486 | |
1487 | for (page = start_page; page <= end_page; page++) { | |
366d1d2b | 1488 | struct jump_info *ji = jumps[page]; |
1489 | if (ji == NULL) | |
1490 | continue; | |
1491 | for (i = 0; i < ji->count; ) { | |
1492 | if (ji->e[i].target_vaddr < start || ji->e[i].target_vaddr >= end) { | |
1493 | i++; | |
048fcced | 1494 | continue; |
1495 | } | |
366d1d2b | 1496 | |
1497 | inv_debug("INV: rm link to %08x (tc_offs %zx)\n", ji->e[i].target_vaddr, | |
1498 | (u_char *)ji->e[i].stub - ndrc->translation_cache); | |
1499 | void *host_addr = find_extjump_insn(ji->e[i].stub); | |
048fcced | 1500 | mark_clear_cache(host_addr); |
366d1d2b | 1501 | set_jump_target(host_addr, ji->e[i].stub); // point back to dyna_linker stub |
048fcced | 1502 | |
048fcced | 1503 | stat_dec(stat_links); |
366d1d2b | 1504 | ji->count--; |
1505 | if (i < ji->count) { | |
1506 | ji->e[i] = ji->e[ji->count]; | |
1507 | continue; | |
1508 | } | |
1509 | i++; | |
1510 | } | |
1511 | } | |
1512 | } | |
1513 | ||
1514 | static void unlink_jumps_tc_range(struct jump_info *ji, u_int base_offs, int shift) | |
1515 | { | |
1516 | int i; | |
1517 | if (ji == NULL) | |
1518 | return; | |
1519 | for (i = 0; i < ji->count; ) { | |
1520 | u_int tc_offs = (u_char *)ji->e[i].stub - ndrc->translation_cache; | |
1521 | if (((tc_offs ^ base_offs) >> shift) != 0) { | |
1522 | i++; | |
1523 | continue; | |
1524 | } | |
1525 | ||
bdbf4466 | 1526 | inv_debug("EXP: rm link to %08x (tc_offs %x)\n", ji->e[i].target_vaddr, tc_offs); |
366d1d2b | 1527 | stat_dec(stat_links); |
1528 | ji->count--; | |
1529 | if (i < ji->count) { | |
1530 | ji->e[i] = ji->e[ji->count]; | |
1531 | continue; | |
048fcced | 1532 | } |
366d1d2b | 1533 | i++; |
57871462 | 1534 | } |
048fcced | 1535 | } |
9f51b4b9 | 1536 | |
048fcced | 1537 | static void invalidate_block(struct block_info *block) |
1538 | { | |
1539 | u_int i; | |
f76eeef9 | 1540 | |
048fcced | 1541 | block->is_dirty = 1; |
366d1d2b | 1542 | unlink_jumps_vaddr_range(block->start, block->start + block->len); |
048fcced | 1543 | for (i = 0; i < block->jump_in_cnt; i++) |
1544 | hash_table_remove(block->jump_in[i].vaddr); | |
57871462 | 1545 | } |
9be4ba64 | 1546 | |
048fcced | 1547 | static int invalidate_range(u_int start, u_int end, |
1548 | u32 *inv_start_ret, u32 *inv_end_ret) | |
9be4ba64 | 1549 | { |
11eca54f | 1550 | struct block_info *last_block = NULL; |
048fcced | 1551 | u_int start_page = get_page_prev(start); |
1552 | u_int end_page = get_page(end - 1); | |
1553 | u_int start_m = pmmask(start); | |
40b19b53 | 1554 | u_int end_m = pmmask(end - 1); |
048fcced | 1555 | u_int inv_start, inv_end; |
1556 | u_int blk_start_m, blk_end_m; | |
1557 | u_int page; | |
1558 | int hit = 0; | |
1559 | ||
1560 | // additional area without code (to supplement invalid_code[]), [start, end) | |
bdbf4466 | 1561 | // avoids excessive ndrc_write_invalidate*() calls |
048fcced | 1562 | inv_start = start_m & ~0xfff; |
1563 | inv_end = end_m | 0xfff; | |
1564 | ||
1565 | for (page = start_page; page <= end_page; page++) { | |
1566 | struct block_info *block; | |
1567 | for (block = blocks[page]; block != NULL; block = block->next) { | |
1568 | if (block->is_dirty) | |
1569 | continue; | |
11eca54f | 1570 | last_block = block; |
048fcced | 1571 | blk_end_m = pmmask(block->start + block->len); |
1572 | if (blk_end_m <= start_m) { | |
1573 | inv_start = max(inv_start, blk_end_m); | |
1574 | continue; | |
1575 | } | |
1576 | blk_start_m = pmmask(block->start); | |
1577 | if (end_m <= blk_start_m) { | |
1578 | inv_end = min(inv_end, blk_start_m - 1); | |
1579 | continue; | |
9be4ba64 | 1580 | } |
048fcced | 1581 | if (!block->source) // "hack" block - leave it alone |
1582 | continue; | |
1583 | ||
1584 | hit++; | |
1585 | invalidate_block(block); | |
1586 | stat_inc(stat_inv_hits); | |
9be4ba64 | 1587 | } |
9be4ba64 | 1588 | } |
048fcced | 1589 | |
11eca54f | 1590 | if (!hit && last_block && last_block->source) { |
1591 | // could be some leftover unused block, uselessly trapping writes | |
1592 | last_block->inv_near_misses++; | |
1593 | if (last_block->inv_near_misses > 128) { | |
1594 | invalidate_block(last_block); | |
1595 | stat_inc(stat_inv_hits); | |
1596 | hit++; | |
1597 | } | |
1598 | } | |
048fcced | 1599 | if (hit) { |
1600 | do_clear_cache(); | |
c980be0e | 1601 | mini_ht_clear(); |
048fcced | 1602 | } |
11eca54f | 1603 | |
048fcced | 1604 | if (inv_start <= (start_m & ~0xfff) && inv_end >= (start_m | 0xfff)) |
1605 | // the whole page is empty now | |
1606 | mark_invalid_code(start, 1, 1); | |
1607 | ||
1608 | if (inv_start_ret) *inv_start_ret = inv_start | (start & 0xe0000000); | |
1609 | if (inv_end_ret) *inv_end_ret = inv_end | (end & 0xe0000000); | |
1610 | return hit; | |
9be4ba64 | 1611 | } |
1612 | ||
048fcced | 1613 | void new_dynarec_invalidate_range(unsigned int start, unsigned int end) |
1614 | { | |
1615 | invalidate_range(start, end, NULL, NULL); | |
1616 | } | |
1617 | ||
bdbf4466 | 1618 | static void ndrc_write_invalidate_many(u_int start, u_int end) |
57871462 | 1619 | { |
9be4ba64 | 1620 | // this check is done by the caller |
1621 | //if (inv_code_start<=addr&&addr<=inv_code_end) { rhits++; return; } | |
bdbf4466 | 1622 | int ret = invalidate_range(start, end, &inv_code_start, &inv_code_end); |
1623 | #ifdef INV_DEBUG_W | |
1624 | int invc = invalid_code[start >> 12]; | |
1625 | u_int len = end - start; | |
048fcced | 1626 | if (ret) |
bdbf4466 | 1627 | printf("INV ADDR: %08x/%02x hit %d blocks\n", start, len, ret); |
048fcced | 1628 | else |
bdbf4466 | 1629 | printf("INV ADDR: %08x/%02x miss, inv %08x-%08x invc %d->%d\n", start, len, |
1630 | inv_code_start, inv_code_end, invc, invalid_code[start >> 12]); | |
1631 | check_for_block_changes(start, end); | |
1632 | #endif | |
55cadc36 | 1633 | stat_inc(stat_inv_addr_calls); |
bdbf4466 | 1634 | (void)ret; |
1635 | } | |
1636 | ||
1637 | void ndrc_write_invalidate_one(u_int addr) | |
1638 | { | |
1639 | ndrc_write_invalidate_many(addr, addr + 4); | |
57871462 | 1640 | } |
9be4ba64 | 1641 | |
dd3a91a1 | 1642 | // This is called when loading a save state. |
1643 | // Anything could have changed, so invalidate everything. | |
048fcced | 1644 | void new_dynarec_invalidate_all_pages(void) |
57871462 | 1645 | { |
048fcced | 1646 | struct block_info *block; |
581335b0 | 1647 | u_int page; |
048fcced | 1648 | for (page = 0; page < ARRAY_SIZE(blocks); page++) { |
1649 | for (block = blocks[page]; block != NULL; block = block->next) { | |
1650 | if (block->is_dirty) | |
1651 | continue; | |
1652 | if (!block->source) // hack block? | |
1653 | continue; | |
1654 | invalidate_block(block); | |
1655 | } | |
1656 | } | |
1657 | ||
630b122b | 1658 | do_clear_cache(); |
c980be0e | 1659 | mini_ht_clear(); |
630b122b | 1660 | } |
1661 | ||
57871462 | 1662 | // Add an entry to jump_out after making a link |
048fcced | 1663 | // src should point to code by emit_extjump() |
366d1d2b | 1664 | void ndrc_add_jump_out(u_int vaddr, void *src) |
57871462 | 1665 | { |
366d1d2b | 1666 | inv_debug("ndrc_add_jump_out: %p -> %x\n", src, vaddr); |
1667 | u_int page = get_page(vaddr); | |
1668 | struct jump_info *ji; | |
1669 | ||
048fcced | 1670 | stat_inc(stat_links); |
366d1d2b | 1671 | check_extjump2(src); |
1672 | ji = jumps[page]; | |
1673 | if (ji == NULL) { | |
1674 | ji = malloc(sizeof(*ji) + sizeof(ji->e[0]) * 16); | |
1675 | ji->alloc = 16; | |
1676 | ji->count = 0; | |
1677 | } | |
1678 | else if (ji->count >= ji->alloc) { | |
1679 | ji->alloc += 16; | |
1680 | ji = realloc(ji, sizeof(*ji) + sizeof(ji->e[0]) * ji->alloc); | |
1681 | } | |
1682 | jumps[page] = ji; | |
1683 | ji->e[ji->count].target_vaddr = vaddr; | |
1684 | ji->e[ji->count].stub = src; | |
1685 | ji->count++; | |
57871462 | 1686 | } |
1687 | ||
630b122b | 1688 | /* Register allocation */ |
1689 | ||
b4661440 | 1690 | static void alloc_set(struct regstat *cur, int reg, int hr) |
1691 | { | |
1692 | cur->regmap[hr] = reg; | |
1693 | cur->dirty &= ~(1u << hr); | |
1694 | cur->isconst &= ~(1u << hr); | |
1695 | cur->noevict |= 1u << hr; | |
1696 | } | |
1697 | ||
1698 | static void evict_alloc_reg(struct regstat *cur, int i, int reg, int preferred_hr) | |
1699 | { | |
1700 | u_char hsn[MAXREG+1]; | |
1701 | int j, r, hr; | |
1702 | memset(hsn, 10, sizeof(hsn)); | |
1703 | lsn(hsn, i); | |
1704 | //printf("hsn(%x): %d %d %d %d %d %d %d\n",start+i*4,hsn[cur->regmap[0]&63],hsn[cur->regmap[1]&63],hsn[cur->regmap[2]&63],hsn[cur->regmap[3]&63],hsn[cur->regmap[5]&63],hsn[cur->regmap[6]&63],hsn[cur->regmap[7]&63]); | |
1705 | if(i>0) { | |
1706 | // Don't evict the cycle count at entry points, otherwise the entry | |
1707 | // stub will have to write it. | |
1708 | if(dops[i].bt&&hsn[CCREG]>2) hsn[CCREG]=2; | |
1709 | if (i>1 && hsn[CCREG] > 2 && dops[i-2].is_jump) hsn[CCREG]=2; | |
1710 | for(j=10;j>=3;j--) | |
1711 | { | |
1712 | // Alloc preferred register if available | |
1713 | if (!((cur->noevict >> preferred_hr) & 1) | |
1714 | && hsn[cur->regmap[preferred_hr]] == j) | |
1715 | { | |
1716 | alloc_set(cur, reg, preferred_hr); | |
1717 | return; | |
1718 | } | |
1719 | for(r=1;r<=MAXREG;r++) | |
1720 | { | |
1721 | if(hsn[r]==j&&r!=dops[i-1].rs1&&r!=dops[i-1].rs2&&r!=dops[i-1].rt1&&r!=dops[i-1].rt2) { | |
1722 | for(hr=0;hr<HOST_REGS;hr++) { | |
1723 | if (hr == EXCLUDE_REG || ((cur->noevict >> hr) & 1)) | |
1724 | continue; | |
1725 | if(hr!=HOST_CCREG||j<hsn[CCREG]) { | |
1726 | if(cur->regmap[hr]==r) { | |
1727 | alloc_set(cur, reg, hr); | |
1728 | return; | |
1729 | } | |
1730 | } | |
1731 | } | |
1732 | } | |
1733 | } | |
1734 | } | |
1735 | } | |
1736 | for(j=10;j>=0;j--) | |
1737 | { | |
1738 | for(r=1;r<=MAXREG;r++) | |
1739 | { | |
1740 | if(hsn[r]==j) { | |
1741 | for(hr=0;hr<HOST_REGS;hr++) { | |
1742 | if (hr == EXCLUDE_REG || ((cur->noevict >> hr) & 1)) | |
1743 | continue; | |
1744 | if(cur->regmap[hr]==r) { | |
1745 | alloc_set(cur, reg, hr); | |
1746 | return; | |
1747 | } | |
1748 | } | |
1749 | } | |
1750 | } | |
1751 | } | |
1752 | SysPrintf("This shouldn't happen (evict_alloc_reg)\n"); | |
1753 | abort(); | |
1754 | } | |
1755 | ||
630b122b | 1756 | // Note: registers are allocated clean (unmodified state) |
1757 | // if you intend to modify the register, you must call dirty_reg(). | |
1758 | static void alloc_reg(struct regstat *cur,int i,signed char reg) | |
57871462 | 1759 | { |
630b122b | 1760 | int r,hr; |
1761 | int preferred_reg = PREFERRED_REG_FIRST | |
1762 | + reg % (PREFERRED_REG_LAST - PREFERRED_REG_FIRST + 1); | |
1763 | if (reg == CCREG) preferred_reg = HOST_CCREG; | |
1764 | if (reg == PTEMP || reg == FTEMP) preferred_reg = 12; | |
1765 | assert(PREFERRED_REG_FIRST != EXCLUDE_REG && EXCLUDE_REG != HOST_REGS); | |
e912c27d | 1766 | assert(reg >= 0); |
630b122b | 1767 | |
1768 | // Don't allocate unused registers | |
1769 | if((cur->u>>reg)&1) return; | |
1770 | ||
1771 | // see if it's already allocated | |
b4661440 | 1772 | if ((hr = get_reg(cur->regmap, reg)) >= 0) { |
1773 | cur->noevict |= 1u << hr; | |
e912c27d | 1774 | return; |
b4661440 | 1775 | } |
630b122b | 1776 | |
1777 | // Keep the same mapping if the register was already allocated in a loop | |
1778 | preferred_reg = loop_reg(i,reg,preferred_reg); | |
1779 | ||
1780 | // Try to allocate the preferred register | |
b4661440 | 1781 | if (cur->regmap[preferred_reg] == -1) { |
1782 | alloc_set(cur, reg, preferred_reg); | |
630b122b | 1783 | return; |
1784 | } | |
1785 | r=cur->regmap[preferred_reg]; | |
1786 | assert(r < 64); | |
1787 | if((cur->u>>r)&1) { | |
b4661440 | 1788 | alloc_set(cur, reg, preferred_reg); |
630b122b | 1789 | return; |
1790 | } | |
1791 | ||
1792 | // Clear any unneeded registers | |
1793 | // We try to keep the mapping consistent, if possible, because it | |
1794 | // makes branches easier (especially loops). So we try to allocate | |
1795 | // first (see above) before removing old mappings. If this is not | |
1796 | // possible then go ahead and clear out the registers that are no | |
1797 | // longer needed. | |
1798 | for(hr=0;hr<HOST_REGS;hr++) | |
0bfdd1aa | 1799 | { |
630b122b | 1800 | r=cur->regmap[hr]; |
1801 | if(r>=0) { | |
1802 | assert(r < 64); | |
1803 | if((cur->u>>r)&1) {cur->regmap[hr]=-1;break;} | |
1804 | } | |
57871462 | 1805 | } |
57871462 | 1806 | |
630b122b | 1807 | // Try to allocate any available register, but prefer |
1808 | // registers that have not been used recently. | |
1809 | if (i > 0) { | |
1810 | for (hr = PREFERRED_REG_FIRST; ; ) { | |
1811 | if (cur->regmap[hr] < 0) { | |
1812 | int oldreg = regs[i-1].regmap[hr]; | |
1813 | if (oldreg < 0 || (oldreg != dops[i-1].rs1 && oldreg != dops[i-1].rs2 | |
1814 | && oldreg != dops[i-1].rt1 && oldreg != dops[i-1].rt2)) | |
1815 | { | |
b4661440 | 1816 | alloc_set(cur, reg, hr); |
630b122b | 1817 | return; |
1818 | } | |
dc49e339 | 1819 | } |
630b122b | 1820 | hr++; |
1821 | if (hr == EXCLUDE_REG) | |
1822 | hr++; | |
1823 | if (hr == HOST_REGS) | |
1824 | hr = 0; | |
1825 | if (hr == PREFERRED_REG_FIRST) | |
1826 | break; | |
57871462 | 1827 | } |
1828 | } | |
dc49e339 | 1829 | |
630b122b | 1830 | // Try to allocate any available register |
1831 | for (hr = PREFERRED_REG_FIRST; ; ) { | |
1832 | if (cur->regmap[hr] < 0) { | |
b4661440 | 1833 | alloc_set(cur, reg, hr); |
630b122b | 1834 | return; |
57871462 | 1835 | } |
630b122b | 1836 | hr++; |
1837 | if (hr == EXCLUDE_REG) | |
1838 | hr++; | |
1839 | if (hr == HOST_REGS) | |
1840 | hr = 0; | |
1841 | if (hr == PREFERRED_REG_FIRST) | |
1842 | break; | |
57871462 | 1843 | } |
630b122b | 1844 | |
1845 | // Ok, now we have to evict someone | |
1846 | // Pick a register we hopefully won't need soon | |
b4661440 | 1847 | evict_alloc_reg(cur, i, reg, preferred_reg); |
630b122b | 1848 | } |
1849 | ||
1850 | // Allocate a temporary register. This is done without regard to | |
1851 | // dirty status or whether the register we request is on the unneeded list | |
1852 | // Note: This will only allocate one register, even if called multiple times | |
1853 | static void alloc_reg_temp(struct regstat *cur,int i,signed char reg) | |
1854 | { | |
1855 | int r,hr; | |
630b122b | 1856 | |
1857 | // see if it's already allocated | |
b4661440 | 1858 | for (hr = 0; hr < HOST_REGS; hr++) |
630b122b | 1859 | { |
b4661440 | 1860 | if (hr != EXCLUDE_REG && cur->regmap[hr] == reg) { |
1861 | cur->noevict |= 1u << hr; | |
1862 | return; | |
1863 | } | |
630b122b | 1864 | } |
1865 | ||
1866 | // Try to allocate any available register | |
1867 | for(hr=HOST_REGS-1;hr>=0;hr--) { | |
1868 | if(hr!=EXCLUDE_REG&&cur->regmap[hr]==-1) { | |
b4661440 | 1869 | alloc_set(cur, reg, hr); |
630b122b | 1870 | return; |
1871 | } | |
1872 | } | |
1873 | ||
1874 | // Find an unneeded register | |
1875 | for(hr=HOST_REGS-1;hr>=0;hr--) | |
1876 | { | |
1877 | r=cur->regmap[hr]; | |
1878 | if(r>=0) { | |
1879 | assert(r < 64); | |
1880 | if((cur->u>>r)&1) { | |
1881 | if(i==0||((unneeded_reg[i-1]>>r)&1)) { | |
b4661440 | 1882 | alloc_set(cur, reg, hr); |
630b122b | 1883 | return; |
1884 | } | |
1885 | } | |
1886 | } | |
1887 | } | |
1888 | ||
1889 | // Ok, now we have to evict someone | |
1890 | // Pick a register we hopefully won't need soon | |
b4661440 | 1891 | evict_alloc_reg(cur, i, reg, 0); |
630b122b | 1892 | } |
1893 | ||
1894 | static void mov_alloc(struct regstat *current,int i) | |
1895 | { | |
1896 | if (dops[i].rs1 == HIREG || dops[i].rs1 == LOREG) { | |
1897 | alloc_cc(current,i); // for stalls | |
1898 | dirty_reg(current,CCREG); | |
1899 | } | |
1900 | ||
1901 | // Note: Don't need to actually alloc the source registers | |
1902 | //alloc_reg(current,i,dops[i].rs1); | |
1903 | alloc_reg(current,i,dops[i].rt1); | |
1904 | ||
1905 | clear_const(current,dops[i].rs1); | |
1906 | clear_const(current,dops[i].rt1); | |
1907 | dirty_reg(current,dops[i].rt1); | |
1908 | } | |
1909 | ||
1910 | static void shiftimm_alloc(struct regstat *current,int i) | |
1911 | { | |
1912 | if(dops[i].opcode2<=0x3) // SLL/SRL/SRA | |
1913 | { | |
1914 | if(dops[i].rt1) { | |
1915 | if(dops[i].rs1&&needed_again(dops[i].rs1,i)) alloc_reg(current,i,dops[i].rs1); | |
ed14d777 | 1916 | else dops[i].use_lt1=!!dops[i].rs1; |
630b122b | 1917 | alloc_reg(current,i,dops[i].rt1); |
1918 | dirty_reg(current,dops[i].rt1); | |
1919 | if(is_const(current,dops[i].rs1)) { | |
1920 | int v=get_const(current,dops[i].rs1); | |
259dbd60 | 1921 | if(dops[i].opcode2==0x00) set_const(current,dops[i].rt1,v<<cinfo[i].imm); |
1922 | if(dops[i].opcode2==0x02) set_const(current,dops[i].rt1,(u_int)v>>cinfo[i].imm); | |
1923 | if(dops[i].opcode2==0x03) set_const(current,dops[i].rt1,v>>cinfo[i].imm); | |
630b122b | 1924 | } |
1925 | else clear_const(current,dops[i].rt1); | |
1926 | } | |
1927 | } | |
1928 | else | |
1929 | { | |
1930 | clear_const(current,dops[i].rs1); | |
1931 | clear_const(current,dops[i].rt1); | |
1932 | } | |
1933 | ||
1934 | if(dops[i].opcode2>=0x38&&dops[i].opcode2<=0x3b) // DSLL/DSRL/DSRA | |
1935 | { | |
1936 | assert(0); | |
1937 | } | |
1938 | if(dops[i].opcode2==0x3c) // DSLL32 | |
1939 | { | |
1940 | assert(0); | |
1941 | } | |
1942 | if(dops[i].opcode2==0x3e) // DSRL32 | |
1943 | { | |
1944 | assert(0); | |
1945 | } | |
1946 | if(dops[i].opcode2==0x3f) // DSRA32 | |
1947 | { | |
1948 | assert(0); | |
57871462 | 1949 | } |
1950 | } | |
1951 | ||
630b122b | 1952 | static void shift_alloc(struct regstat *current,int i) |
57871462 | 1953 | { |
630b122b | 1954 | if(dops[i].rt1) { |
630b122b | 1955 | if(dops[i].rs1) alloc_reg(current,i,dops[i].rs1); |
1956 | if(dops[i].rs2) alloc_reg(current,i,dops[i].rs2); | |
1957 | alloc_reg(current,i,dops[i].rt1); | |
1958 | if(dops[i].rt1==dops[i].rs2) { | |
e1190b87 | 1959 | alloc_reg_temp(current,i,-1); |
259dbd60 | 1960 | cinfo[i].min_free_regs=1; |
e1190b87 | 1961 | } |
630b122b | 1962 | clear_const(current,dops[i].rs1); |
1963 | clear_const(current,dops[i].rs2); | |
1964 | clear_const(current,dops[i].rt1); | |
1965 | dirty_reg(current,dops[i].rt1); | |
57871462 | 1966 | } |
1967 | } | |
1968 | ||
630b122b | 1969 | static void alu_alloc(struct regstat *current,int i) |
57871462 | 1970 | { |
630b122b | 1971 | if(dops[i].opcode2>=0x20&&dops[i].opcode2<=0x23) { // ADD/ADDU/SUB/SUBU |
1972 | if(dops[i].rt1) { | |
1973 | if(dops[i].rs1&&dops[i].rs2) { | |
1974 | alloc_reg(current,i,dops[i].rs1); | |
1975 | alloc_reg(current,i,dops[i].rs2); | |
57871462 | 1976 | } |
1977 | else { | |
630b122b | 1978 | if(dops[i].rs1&&needed_again(dops[i].rs1,i)) alloc_reg(current,i,dops[i].rs1); |
1979 | if(dops[i].rs2&&needed_again(dops[i].rs2,i)) alloc_reg(current,i,dops[i].rs2); | |
57871462 | 1980 | } |
630b122b | 1981 | alloc_reg(current,i,dops[i].rt1); |
57871462 | 1982 | } |
259dbd60 | 1983 | if (dops[i].may_except) { |
b4661440 | 1984 | alloc_cc_optional(current, i); // for exceptions |
259dbd60 | 1985 | alloc_reg_temp(current, i, -1); |
1986 | cinfo[i].min_free_regs = 1; | |
f2e25348 | 1987 | } |
57871462 | 1988 | } |
259dbd60 | 1989 | else if(dops[i].opcode2==0x2a||dops[i].opcode2==0x2b) { // SLT/SLTU |
630b122b | 1990 | if(dops[i].rt1) { |
1991 | alloc_reg(current,i,dops[i].rs1); | |
1992 | alloc_reg(current,i,dops[i].rs2); | |
1993 | alloc_reg(current,i,dops[i].rt1); | |
57871462 | 1994 | } |
57871462 | 1995 | } |
259dbd60 | 1996 | else if(dops[i].opcode2>=0x24&&dops[i].opcode2<=0x27) { // AND/OR/XOR/NOR |
630b122b | 1997 | if(dops[i].rt1) { |
1998 | if(dops[i].rs1&&dops[i].rs2) { | |
1999 | alloc_reg(current,i,dops[i].rs1); | |
2000 | alloc_reg(current,i,dops[i].rs2); | |
57871462 | 2001 | } |
2002 | else | |
2003 | { | |
630b122b | 2004 | if(dops[i].rs1&&needed_again(dops[i].rs1,i)) alloc_reg(current,i,dops[i].rs1); |
2005 | if(dops[i].rs2&&needed_again(dops[i].rs2,i)) alloc_reg(current,i,dops[i].rs2); | |
57871462 | 2006 | } |
630b122b | 2007 | alloc_reg(current,i,dops[i].rt1); |
57871462 | 2008 | } |
2009 | } | |
630b122b | 2010 | clear_const(current,dops[i].rs1); |
2011 | clear_const(current,dops[i].rs2); | |
2012 | clear_const(current,dops[i].rt1); | |
2013 | dirty_reg(current,dops[i].rt1); | |
57871462 | 2014 | } |
2015 | ||
630b122b | 2016 | static void imm16_alloc(struct regstat *current,int i) |
57871462 | 2017 | { |
630b122b | 2018 | if(dops[i].rs1&&needed_again(dops[i].rs1,i)) alloc_reg(current,i,dops[i].rs1); |
ed14d777 | 2019 | else dops[i].use_lt1=!!dops[i].rs1; |
630b122b | 2020 | if(dops[i].rt1) alloc_reg(current,i,dops[i].rt1); |
f2e25348 | 2021 | if(dops[i].opcode==0x0a||dops[i].opcode==0x0b) { // SLTI/SLTIU |
630b122b | 2022 | clear_const(current,dops[i].rs1); |
2023 | clear_const(current,dops[i].rt1); | |
57871462 | 2024 | } |
630b122b | 2025 | else if(dops[i].opcode>=0x0c&&dops[i].opcode<=0x0e) { // ANDI/ORI/XORI |
2026 | if(is_const(current,dops[i].rs1)) { | |
2027 | int v=get_const(current,dops[i].rs1); | |
259dbd60 | 2028 | if(dops[i].opcode==0x0c) set_const(current,dops[i].rt1,v&cinfo[i].imm); |
2029 | if(dops[i].opcode==0x0d) set_const(current,dops[i].rt1,v|cinfo[i].imm); | |
2030 | if(dops[i].opcode==0x0e) set_const(current,dops[i].rt1,v^cinfo[i].imm); | |
57871462 | 2031 | } |
630b122b | 2032 | else clear_const(current,dops[i].rt1); |
57871462 | 2033 | } |
630b122b | 2034 | else if(dops[i].opcode==0x08||dops[i].opcode==0x09) { // ADDI/ADDIU |
2035 | if(is_const(current,dops[i].rs1)) { | |
2036 | int v=get_const(current,dops[i].rs1); | |
259dbd60 | 2037 | set_const(current,dops[i].rt1,v+cinfo[i].imm); |
57871462 | 2038 | } |
630b122b | 2039 | else clear_const(current,dops[i].rt1); |
259dbd60 | 2040 | if (dops[i].may_except) { |
b4661440 | 2041 | alloc_cc_optional(current, i); // for exceptions |
259dbd60 | 2042 | alloc_reg_temp(current, i, -1); |
2043 | cinfo[i].min_free_regs = 1; | |
f2e25348 | 2044 | } |
57871462 | 2045 | } |
2046 | else { | |
259dbd60 | 2047 | set_const(current,dops[i].rt1,cinfo[i].imm<<16); // LUI |
57871462 | 2048 | } |
630b122b | 2049 | dirty_reg(current,dops[i].rt1); |
57871462 | 2050 | } |
2051 | ||
630b122b | 2052 | static void load_alloc(struct regstat *current,int i) |
57871462 | 2053 | { |
259dbd60 | 2054 | int need_temp = 0; |
630b122b | 2055 | clear_const(current,dops[i].rt1); |
2056 | //if(dops[i].rs1!=dops[i].rt1&&needed_again(dops[i].rs1,i)) clear_const(current,dops[i].rs1); // Does this help or hurt? | |
2057 | if(!dops[i].rs1) current->u&=~1LL; // Allow allocating r0 if it's the source register | |
2058 | if (needed_again(dops[i].rs1, i)) | |
2059 | alloc_reg(current, i, dops[i].rs1); | |
2060 | if (ram_offset) | |
2061 | alloc_reg(current, i, ROREG); | |
259dbd60 | 2062 | if (dops[i].may_except) { |
b4661440 | 2063 | alloc_cc_optional(current, i); // for exceptions |
259dbd60 | 2064 | need_temp = 1; |
2065 | } | |
630b122b | 2066 | if(dops[i].rt1&&!((current->u>>dops[i].rt1)&1)) { |
2067 | alloc_reg(current,i,dops[i].rt1); | |
f2e25348 | 2068 | assert(get_reg_w(current->regmap, dops[i].rt1)>=0); |
630b122b | 2069 | dirty_reg(current,dops[i].rt1); |
57871462 | 2070 | // LWL/LWR need a temporary register for the old value |
630b122b | 2071 | if(dops[i].opcode==0x22||dops[i].opcode==0x26) |
57871462 | 2072 | { |
2073 | alloc_reg(current,i,FTEMP); | |
259dbd60 | 2074 | need_temp = 1; |
57871462 | 2075 | } |
2076 | } | |
2077 | else | |
2078 | { | |
373d1d07 | 2079 | // Load to r0 or unneeded register (dummy load) |
57871462 | 2080 | // but we still need a register to calculate the address |
630b122b | 2081 | if(dops[i].opcode==0x22||dops[i].opcode==0x26) |
535d208a | 2082 | alloc_reg(current,i,FTEMP); // LWL/LWR need another temporary |
259dbd60 | 2083 | need_temp = 1; |
2084 | } | |
2085 | if (need_temp) { | |
2086 | alloc_reg_temp(current, i, -1); | |
2087 | cinfo[i].min_free_regs = 1; | |
57871462 | 2088 | } |
2089 | } | |
2090 | ||
b4661440 | 2091 | // this may eat up to 7 registers |
2092 | static void store_alloc(struct regstat *current, int i) | |
57871462 | 2093 | { |
630b122b | 2094 | clear_const(current,dops[i].rs2); |
2095 | if(!(dops[i].rs2)) current->u&=~1LL; // Allow allocating r0 if necessary | |
2096 | if(needed_again(dops[i].rs1,i)) alloc_reg(current,i,dops[i].rs1); | |
2097 | alloc_reg(current,i,dops[i].rs2); | |
630b122b | 2098 | if (ram_offset) |
2099 | alloc_reg(current, i, ROREG); | |
57871462 | 2100 | #if defined(HOST_IMM8) |
2101 | // On CPUs without 32-bit immediates we need a pointer to invalid_code | |
630b122b | 2102 | alloc_reg(current, i, INVCP); |
57871462 | 2103 | #endif |
259dbd60 | 2104 | if (dops[i].opcode == 0x2a || dops[i].opcode == 0x2e) { // SWL/SWL |
57871462 | 2105 | alloc_reg(current,i,FTEMP); |
2106 | } | |
b4661440 | 2107 | if (dops[i].may_except) |
2108 | alloc_cc_optional(current, i); // for exceptions | |
57871462 | 2109 | // We need a temporary register for address generation |
2110 | alloc_reg_temp(current,i,-1); | |
259dbd60 | 2111 | cinfo[i].min_free_regs=1; |
57871462 | 2112 | } |
2113 | ||
b4661440 | 2114 | static void c2ls_alloc(struct regstat *current, int i) |
b9b61529 | 2115 | { |
630b122b | 2116 | clear_const(current,dops[i].rt1); |
2117 | if(needed_again(dops[i].rs1,i)) alloc_reg(current,i,dops[i].rs1); | |
b9b61529 | 2118 | alloc_reg(current,i,FTEMP); |
630b122b | 2119 | if (ram_offset) |
2120 | alloc_reg(current, i, ROREG); | |
b9b61529 | 2121 | #if defined(HOST_IMM8) |
2122 | // On CPUs without 32-bit immediates we need a pointer to invalid_code | |
630b122b | 2123 | if (dops[i].opcode == 0x3a) // SWC2 |
b9b61529 | 2124 | alloc_reg(current,i,INVCP); |
2125 | #endif | |
b4661440 | 2126 | if (dops[i].may_except) |
2127 | alloc_cc_optional(current, i); // for exceptions | |
b9b61529 | 2128 | // We need a temporary register for address generation |
2129 | alloc_reg_temp(current,i,-1); | |
259dbd60 | 2130 | cinfo[i].min_free_regs=1; |
b9b61529 | 2131 | } |
2132 | ||
57871462 | 2133 | #ifndef multdiv_alloc |
94061aa5 | 2134 | static void multdiv_alloc(struct regstat *current,int i) |
57871462 | 2135 | { |
2136 | // case 0x18: MULT | |
2137 | // case 0x19: MULTU | |
2138 | // case 0x1A: DIV | |
2139 | // case 0x1B: DIVU | |
630b122b | 2140 | clear_const(current,dops[i].rs1); |
2141 | clear_const(current,dops[i].rs2); | |
2142 | alloc_cc(current,i); // for stalls | |
b4661440 | 2143 | dirty_reg(current,CCREG); |
2f0488ff | 2144 | current->u &= ~(1ull << HIREG); |
2145 | current->u &= ~(1ull << LOREG); | |
2146 | alloc_reg(current, i, HIREG); | |
2147 | alloc_reg(current, i, LOREG); | |
2148 | dirty_reg(current, HIREG); | |
2149 | dirty_reg(current, LOREG); | |
2150 | if ((dops[i].opcode2 & 0x3e) == 0x1a || (dops[i].rs1 && dops[i].rs2)) // div(u) | |
57871462 | 2151 | { |
2f0488ff | 2152 | alloc_reg(current, i, dops[i].rs1); |
2153 | alloc_reg(current, i, dops[i].rs2); | |
57871462 | 2154 | } |
2f0488ff | 2155 | // else multiply by zero is zero |
57871462 | 2156 | } |
2157 | #endif | |
2158 | ||
94061aa5 | 2159 | static void cop0_alloc(struct regstat *current,int i) |
57871462 | 2160 | { |
630b122b | 2161 | if(dops[i].opcode2==0) // MFC0 |
57871462 | 2162 | { |
630b122b | 2163 | if(dops[i].rt1) { |
2164 | clear_const(current,dops[i].rt1); | |
630b122b | 2165 | alloc_reg(current,i,dops[i].rt1); |
2166 | dirty_reg(current,dops[i].rt1); | |
57871462 | 2167 | } |
2168 | } | |
630b122b | 2169 | else if(dops[i].opcode2==4) // MTC0 |
57871462 | 2170 | { |
5753f874 | 2171 | if (((source[i]>>11)&0x1e) == 12) { |
2172 | alloc_cc(current, i); | |
2173 | dirty_reg(current, CCREG); | |
2174 | } | |
630b122b | 2175 | if(dops[i].rs1){ |
2176 | clear_const(current,dops[i].rs1); | |
2177 | alloc_reg(current,i,dops[i].rs1); | |
57871462 | 2178 | alloc_all(current,i); |
2179 | } | |
2180 | else { | |
2181 | alloc_all(current,i); // FIXME: Keep r0 | |
2182 | current->u&=~1LL; | |
2183 | alloc_reg(current,i,0); | |
2184 | } | |
259dbd60 | 2185 | cinfo[i].min_free_regs = HOST_REGS; |
57871462 | 2186 | } |
f2e25348 | 2187 | } |
2188 | ||
2189 | static void rfe_alloc(struct regstat *current, int i) | |
2190 | { | |
2191 | alloc_all(current, i); | |
259dbd60 | 2192 | cinfo[i].min_free_regs = HOST_REGS; |
57871462 | 2193 | } |
2194 | ||
630b122b | 2195 | static void cop2_alloc(struct regstat *current,int i) |
57871462 | 2196 | { |
630b122b | 2197 | if (dops[i].opcode2 < 3) // MFC2/CFC2 |
57871462 | 2198 | { |
630b122b | 2199 | alloc_cc(current,i); // for stalls |
2200 | dirty_reg(current,CCREG); | |
2201 | if(dops[i].rt1){ | |
2202 | clear_const(current,dops[i].rt1); | |
2203 | alloc_reg(current,i,dops[i].rt1); | |
2204 | dirty_reg(current,dops[i].rt1); | |
57871462 | 2205 | } |
57871462 | 2206 | } |
630b122b | 2207 | else if (dops[i].opcode2 > 3) // MTC2/CTC2 |
57871462 | 2208 | { |
630b122b | 2209 | if(dops[i].rs1){ |
2210 | clear_const(current,dops[i].rs1); | |
2211 | alloc_reg(current,i,dops[i].rs1); | |
57871462 | 2212 | } |
2213 | else { | |
2214 | current->u&=~1LL; | |
2215 | alloc_reg(current,i,0); | |
57871462 | 2216 | } |
2217 | } | |
57871462 | 2218 | alloc_reg_temp(current,i,-1); |
259dbd60 | 2219 | cinfo[i].min_free_regs=1; |
57871462 | 2220 | } |
630b122b | 2221 | |
94061aa5 | 2222 | static void c2op_alloc(struct regstat *current,int i) |
b9b61529 | 2223 | { |
630b122b | 2224 | alloc_cc(current,i); // for stalls |
2225 | dirty_reg(current,CCREG); | |
b9b61529 | 2226 | alloc_reg_temp(current,i,-1); |
2227 | } | |
57871462 | 2228 | |
94061aa5 | 2229 | static void syscall_alloc(struct regstat *current,int i) |
57871462 | 2230 | { |
2231 | alloc_cc(current,i); | |
2232 | dirty_reg(current,CCREG); | |
2233 | alloc_all(current,i); | |
259dbd60 | 2234 | cinfo[i].min_free_regs=HOST_REGS; |
57871462 | 2235 | current->isconst=0; |
2236 | } | |
2237 | ||
94061aa5 | 2238 | static void delayslot_alloc(struct regstat *current,int i) |
57871462 | 2239 | { |
630b122b | 2240 | switch(dops[i].itype) { |
57871462 | 2241 | case UJUMP: |
2242 | case CJUMP: | |
2243 | case SJUMP: | |
2244 | case RJUMP: | |
57871462 | 2245 | case SYSCALL: |
7139f3c8 | 2246 | case HLECALL: |
57871462 | 2247 | case IMM16: |
2248 | imm16_alloc(current,i); | |
2249 | break; | |
2250 | case LOAD: | |
2251 | case LOADLR: | |
2252 | load_alloc(current,i); | |
2253 | break; | |
2254 | case STORE: | |
2255 | case STORELR: | |
2256 | store_alloc(current,i); | |
2257 | break; | |
2258 | case ALU: | |
2259 | alu_alloc(current,i); | |
2260 | break; | |
2261 | case SHIFT: | |
2262 | shift_alloc(current,i); | |
2263 | break; | |
2264 | case MULTDIV: | |
2265 | multdiv_alloc(current,i); | |
2266 | break; | |
2267 | case SHIFTIMM: | |
2268 | shiftimm_alloc(current,i); | |
2269 | break; | |
2270 | case MOV: | |
2271 | mov_alloc(current,i); | |
2272 | break; | |
2273 | case COP0: | |
2274 | cop0_alloc(current,i); | |
2275 | break; | |
f2e25348 | 2276 | case RFE: |
2277 | rfe_alloc(current,i); | |
630b122b | 2278 | break; |
b9b61529 | 2279 | case COP2: |
630b122b | 2280 | cop2_alloc(current,i); |
57871462 | 2281 | break; |
b9b61529 | 2282 | case C2LS: |
2283 | c2ls_alloc(current,i); | |
2284 | break; | |
b9b61529 | 2285 | case C2OP: |
2286 | c2op_alloc(current,i); | |
2287 | break; | |
57871462 | 2288 | } |
2289 | } | |
2290 | ||
630b122b | 2291 | static void add_stub(enum stub_type type, void *addr, void *retaddr, |
2292 | u_int a, uintptr_t b, uintptr_t c, u_int d, u_int e) | |
57871462 | 2293 | { |
630b122b | 2294 | assert(stubcount < ARRAY_SIZE(stubs)); |
2295 | stubs[stubcount].type = type; | |
2296 | stubs[stubcount].addr = addr; | |
2297 | stubs[stubcount].retaddr = retaddr; | |
2298 | stubs[stubcount].a = a; | |
2299 | stubs[stubcount].b = b; | |
2300 | stubs[stubcount].c = c; | |
2301 | stubs[stubcount].d = d; | |
2302 | stubs[stubcount].e = e; | |
57871462 | 2303 | stubcount++; |
2304 | } | |
2305 | ||
630b122b | 2306 | static void add_stub_r(enum stub_type type, void *addr, void *retaddr, |
2307 | int i, int addr_reg, const struct regstat *i_regs, int ccadj, u_int reglist) | |
2308 | { | |
2309 | add_stub(type, addr, retaddr, i, addr_reg, (uintptr_t)i_regs, ccadj, reglist); | |
2310 | } | |
2311 | ||
57871462 | 2312 | // Write out a single register |
a3c5fc39 | 2313 | static void wb_register(signed char r, const signed char regmap[], u_int dirty) |
57871462 | 2314 | { |
2315 | int hr; | |
2316 | for(hr=0;hr<HOST_REGS;hr++) { | |
2317 | if(hr!=EXCLUDE_REG) { | |
91af94f0 | 2318 | if(regmap[hr]==r) { |
57871462 | 2319 | if((dirty>>hr)&1) { |
630b122b | 2320 | assert(regmap[hr]<64); |
2321 | emit_storereg(r,hr); | |
57871462 | 2322 | } |
a3c5fc39 | 2323 | break; |
57871462 | 2324 | } |
2325 | } | |
2326 | } | |
2327 | } | |
2328 | ||
630b122b | 2329 | static void wb_valid(signed char pre[],signed char entry[],u_int dirty_pre,u_int dirty,uint64_t u) |
57871462 | 2330 | { |
630b122b | 2331 | //if(dirty_pre==dirty) return; |
e912c27d | 2332 | int hr, r; |
2333 | for (hr = 0; hr < HOST_REGS; hr++) { | |
2334 | r = pre[hr]; | |
2335 | if (r < 1 || r > 33 || ((u >> r) & 1)) | |
2336 | continue; | |
2337 | if (((dirty_pre & ~dirty) >> hr) & 1) | |
2338 | emit_storereg(r, hr); | |
57871462 | 2339 | } |
57871462 | 2340 | } |
2341 | ||
630b122b | 2342 | // trashes r2 |
2343 | static void pass_args(int a0, int a1) | |
57871462 | 2344 | { |
630b122b | 2345 | if(a0==1&&a1==0) { |
2346 | // must swap | |
2347 | emit_mov(a0,2); emit_mov(a1,1); emit_mov(2,0); | |
2348 | } | |
2349 | else if(a0!=0&&a1==0) { | |
2350 | emit_mov(a1,1); | |
2351 | if (a0>=0) emit_mov(a0,0); | |
2352 | } | |
2353 | else { | |
2354 | if(a0>=0&&a0!=0) emit_mov(a0,0); | |
2355 | if(a1>=0&&a1!=1) emit_mov(a1,1); | |
57871462 | 2356 | } |
57871462 | 2357 | } |
2358 | ||
f2e25348 | 2359 | static void alu_assemble(int i, const struct regstat *i_regs, int ccadj_) |
57871462 | 2360 | { |
630b122b | 2361 | if(dops[i].opcode2>=0x20&&dops[i].opcode2<=0x23) { // ADD/ADDU/SUB/SUBU |
f2e25348 | 2362 | int do_oflow = dops[i].may_except; // ADD/SUB with exceptions enabled |
2363 | if (dops[i].rt1 || do_oflow) { | |
2364 | int do_exception_check = 0; | |
2365 | signed char s1, s2, t, tmp; | |
2366 | t = get_reg_w(i_regs->regmap, dops[i].rt1); | |
2367 | tmp = get_reg_temp(i_regs->regmap); | |
259dbd60 | 2368 | if (do_oflow) |
2369 | assert(tmp >= 0); | |
b4661440 | 2370 | if (t < 0 && do_oflow) |
2371 | t = tmp; | |
f2e25348 | 2372 | if (t >= 0) { |
2373 | s1 = get_reg(i_regs->regmap, dops[i].rs1); | |
2374 | s2 = get_reg(i_regs->regmap, dops[i].rs2); | |
2375 | if (dops[i].rs1 && dops[i].rs2) { | |
57871462 | 2376 | assert(s1>=0); |
2377 | assert(s2>=0); | |
f2e25348 | 2378 | if (dops[i].opcode2 & 2) { |
2379 | if (do_oflow) { | |
2380 | emit_subs(s1, s2, tmp); | |
2381 | do_exception_check = 1; | |
2382 | } | |
2383 | else | |
2384 | emit_sub(s1,s2,t); | |
2385 | } | |
2386 | else { | |
2387 | if (do_oflow) { | |
2388 | emit_adds(s1, s2, tmp); | |
2389 | do_exception_check = 1; | |
2390 | } | |
2391 | else | |
2392 | emit_add(s1,s2,t); | |
2393 | } | |
57871462 | 2394 | } |
630b122b | 2395 | else if(dops[i].rs1) { |
57871462 | 2396 | if(s1>=0) emit_mov(s1,t); |
630b122b | 2397 | else emit_loadreg(dops[i].rs1,t); |
57871462 | 2398 | } |
630b122b | 2399 | else if(dops[i].rs2) { |
f2e25348 | 2400 | if (s2 < 0) { |
2401 | emit_loadreg(dops[i].rs2, t); | |
2402 | s2 = t; | |
57871462 | 2403 | } |
f2e25348 | 2404 | if (dops[i].opcode2 & 2) { |
2405 | if (do_oflow) { | |
2406 | emit_negs(s2, tmp); | |
2407 | do_exception_check = 1; | |
2408 | } | |
2409 | else | |
2410 | emit_neg(s2, t); | |
57871462 | 2411 | } |
f2e25348 | 2412 | else if (s2 != t) |
2413 | emit_mov(s2, t); | |
57871462 | 2414 | } |
f2e25348 | 2415 | else |
2416 | emit_zeroreg(t); | |
2417 | } | |
2418 | if (do_exception_check) { | |
2419 | void *jaddr = out; | |
2420 | emit_jo(0); | |
2421 | if (t >= 0 && tmp != t) | |
2422 | emit_mov(tmp, t); | |
2423 | add_stub_r(OVERFLOW_STUB, jaddr, out, i, 0, i_regs, ccadj_, 0); | |
57871462 | 2424 | } |
2425 | } | |
2426 | } | |
f2e25348 | 2427 | else if(dops[i].opcode2==0x2a||dops[i].opcode2==0x2b) { // SLT/SLTU |
630b122b | 2428 | if(dops[i].rt1) { |
2429 | signed char s1l,s2l,t; | |
57871462 | 2430 | { |
f2e25348 | 2431 | t=get_reg_w(i_regs->regmap, dops[i].rt1); |
57871462 | 2432 | //assert(t>=0); |
2433 | if(t>=0) { | |
630b122b | 2434 | s1l=get_reg(i_regs->regmap,dops[i].rs1); |
2435 | s2l=get_reg(i_regs->regmap,dops[i].rs2); | |
2436 | if(dops[i].rs2==0) // rx<r0 | |
57871462 | 2437 | { |
630b122b | 2438 | if(dops[i].opcode2==0x2a&&dops[i].rs1!=0) { // SLT |
2439 | assert(s1l>=0); | |
57871462 | 2440 | emit_shrimm(s1l,31,t); |
630b122b | 2441 | } |
2442 | else // SLTU (unsigned can not be less than zero, 0<0) | |
57871462 | 2443 | emit_zeroreg(t); |
2444 | } | |
630b122b | 2445 | else if(dops[i].rs1==0) // r0<rx |
57871462 | 2446 | { |
2447 | assert(s2l>=0); | |
630b122b | 2448 | if(dops[i].opcode2==0x2a) // SLT |
57871462 | 2449 | emit_set_gz32(s2l,t); |
2450 | else // SLTU (set if not zero) | |
2451 | emit_set_nz32(s2l,t); | |
2452 | } | |
2453 | else{ | |
2454 | assert(s1l>=0);assert(s2l>=0); | |
630b122b | 2455 | if(dops[i].opcode2==0x2a) // SLT |
57871462 | 2456 | emit_set_if_less32(s1l,s2l,t); |
2457 | else // SLTU | |
2458 | emit_set_if_carry32(s1l,s2l,t); | |
2459 | } | |
2460 | } | |
2461 | } | |
2462 | } | |
2463 | } | |
f2e25348 | 2464 | else if(dops[i].opcode2>=0x24&&dops[i].opcode2<=0x27) { // AND/OR/XOR/NOR |
630b122b | 2465 | if(dops[i].rt1) { |
2466 | signed char s1l,s2l,tl; | |
f2e25348 | 2467 | tl=get_reg_w(i_regs->regmap, dops[i].rt1); |
57871462 | 2468 | { |
57871462 | 2469 | if(tl>=0) { |
630b122b | 2470 | s1l=get_reg(i_regs->regmap,dops[i].rs1); |
2471 | s2l=get_reg(i_regs->regmap,dops[i].rs2); | |
2472 | if(dops[i].rs1&&dops[i].rs2) { | |
57871462 | 2473 | assert(s1l>=0); |
2474 | assert(s2l>=0); | |
630b122b | 2475 | if(dops[i].opcode2==0x24) { // AND |
57871462 | 2476 | emit_and(s1l,s2l,tl); |
2477 | } else | |
630b122b | 2478 | if(dops[i].opcode2==0x25) { // OR |
57871462 | 2479 | emit_or(s1l,s2l,tl); |
2480 | } else | |
630b122b | 2481 | if(dops[i].opcode2==0x26) { // XOR |
57871462 | 2482 | emit_xor(s1l,s2l,tl); |
2483 | } else | |
630b122b | 2484 | if(dops[i].opcode2==0x27) { // NOR |
57871462 | 2485 | emit_or(s1l,s2l,tl); |
2486 | emit_not(tl,tl); | |
2487 | } | |
2488 | } | |
2489 | else | |
2490 | { | |
630b122b | 2491 | if(dops[i].opcode2==0x24) { // AND |
57871462 | 2492 | emit_zeroreg(tl); |
2493 | } else | |
630b122b | 2494 | if(dops[i].opcode2==0x25||dops[i].opcode2==0x26) { // OR/XOR |
2495 | if(dops[i].rs1){ | |
57871462 | 2496 | if(s1l>=0) emit_mov(s1l,tl); |
630b122b | 2497 | else emit_loadreg(dops[i].rs1,tl); // CHECK: regmap_entry? |
57871462 | 2498 | } |
2499 | else | |
630b122b | 2500 | if(dops[i].rs2){ |
57871462 | 2501 | if(s2l>=0) emit_mov(s2l,tl); |
630b122b | 2502 | else emit_loadreg(dops[i].rs2,tl); // CHECK: regmap_entry? |
57871462 | 2503 | } |
2504 | else emit_zeroreg(tl); | |
2505 | } else | |
630b122b | 2506 | if(dops[i].opcode2==0x27) { // NOR |
2507 | if(dops[i].rs1){ | |
57871462 | 2508 | if(s1l>=0) emit_not(s1l,tl); |
2509 | else { | |
630b122b | 2510 | emit_loadreg(dops[i].rs1,tl); |
57871462 | 2511 | emit_not(tl,tl); |
2512 | } | |
2513 | } | |
2514 | else | |
630b122b | 2515 | if(dops[i].rs2){ |
57871462 | 2516 | if(s2l>=0) emit_not(s2l,tl); |
2517 | else { | |
630b122b | 2518 | emit_loadreg(dops[i].rs2,tl); |
57871462 | 2519 | emit_not(tl,tl); |
2520 | } | |
2521 | } | |
2522 | else emit_movimm(-1,tl); | |
2523 | } | |
2524 | } | |
2525 | } | |
2526 | } | |
2527 | } | |
2528 | } | |
2529 | } | |
2530 | ||
f2e25348 | 2531 | static void imm16_assemble(int i, const struct regstat *i_regs, int ccadj_) |
57871462 | 2532 | { |
630b122b | 2533 | if (dops[i].opcode==0x0f) { // LUI |
2534 | if(dops[i].rt1) { | |
57871462 | 2535 | signed char t; |
f2e25348 | 2536 | t=get_reg_w(i_regs->regmap, dops[i].rt1); |
57871462 | 2537 | //assert(t>=0); |
2538 | if(t>=0) { | |
2539 | if(!((i_regs->isconst>>t)&1)) | |
259dbd60 | 2540 | emit_movimm(cinfo[i].imm<<16,t); |
57871462 | 2541 | } |
2542 | } | |
2543 | } | |
630b122b | 2544 | if(dops[i].opcode==0x08||dops[i].opcode==0x09) { // ADDI/ADDIU |
259dbd60 | 2545 | int is_addi = dops[i].may_except; |
f2e25348 | 2546 | if (dops[i].rt1 || is_addi) { |
2547 | signed char s, t, tmp; | |
2548 | t=get_reg_w(i_regs->regmap, dops[i].rt1); | |
630b122b | 2549 | s=get_reg(i_regs->regmap,dops[i].rs1); |
2550 | if(dops[i].rs1) { | |
f2e25348 | 2551 | tmp = get_reg_temp(i_regs->regmap); |
2552 | if (is_addi) { | |
2553 | assert(tmp >= 0); | |
2554 | if (t < 0) t = tmp; | |
2555 | } | |
57871462 | 2556 | if(t>=0) { |
2557 | if(!((i_regs->isconst>>t)&1)) { | |
f2e25348 | 2558 | int sum, do_exception_check = 0; |
2559 | if (s < 0) { | |
630b122b | 2560 | if(i_regs->regmap_entry[t]!=dops[i].rs1) emit_loadreg(dops[i].rs1,t); |
f2e25348 | 2561 | if (is_addi) { |
259dbd60 | 2562 | emit_addimm_and_set_flags3(t, cinfo[i].imm, tmp); |
f2e25348 | 2563 | do_exception_check = 1; |
2564 | } | |
57871462 | 2565 | else |
259dbd60 | 2566 | emit_addimm(t, cinfo[i].imm, t); |
f2e25348 | 2567 | } else { |
2568 | if (!((i_regs->wasconst >> s) & 1)) { | |
2569 | if (is_addi) { | |
259dbd60 | 2570 | emit_addimm_and_set_flags3(s, cinfo[i].imm, tmp); |
f2e25348 | 2571 | do_exception_check = 1; |
2572 | } | |
2573 | else | |
259dbd60 | 2574 | emit_addimm(s, cinfo[i].imm, t); |
f2e25348 | 2575 | } |
2576 | else { | |
259dbd60 | 2577 | int oflow = add_overflow(constmap[i][s], cinfo[i].imm, sum); |
f2e25348 | 2578 | if (is_addi && oflow) |
2579 | do_exception_check = 2; | |
2580 | else | |
2581 | emit_movimm(sum, t); | |
2582 | } | |
2583 | } | |
2584 | if (do_exception_check) { | |
2585 | void *jaddr = out; | |
2586 | if (do_exception_check == 2) | |
2587 | emit_jmp(0); | |
2588 | else { | |
2589 | emit_jo(0); | |
2590 | if (tmp != t) | |
2591 | emit_mov(tmp, t); | |
2592 | } | |
2593 | add_stub_r(OVERFLOW_STUB, jaddr, out, i, 0, i_regs, ccadj_, 0); | |
57871462 | 2594 | } |
2595 | } | |
2596 | } | |
2597 | } else { | |
2598 | if(t>=0) { | |
2599 | if(!((i_regs->isconst>>t)&1)) | |
259dbd60 | 2600 | emit_movimm(cinfo[i].imm,t); |
57871462 | 2601 | } |
2602 | } | |
2603 | } | |
2604 | } | |
630b122b | 2605 | else if(dops[i].opcode==0x0a||dops[i].opcode==0x0b) { // SLTI/SLTIU |
2606 | if(dops[i].rt1) { | |
2607 | //assert(dops[i].rs1!=0); // r0 might be valid, but it's probably a bug | |
2608 | signed char sl,t; | |
f2e25348 | 2609 | t=get_reg_w(i_regs->regmap, dops[i].rt1); |
630b122b | 2610 | sl=get_reg(i_regs->regmap,dops[i].rs1); |
57871462 | 2611 | //assert(t>=0); |
2612 | if(t>=0) { | |
630b122b | 2613 | if(dops[i].rs1>0) { |
2614 | if(dops[i].opcode==0x0a) { // SLTI | |
57871462 | 2615 | if(sl<0) { |
630b122b | 2616 | if(i_regs->regmap_entry[t]!=dops[i].rs1) emit_loadreg(dops[i].rs1,t); |
259dbd60 | 2617 | emit_slti32(t,cinfo[i].imm,t); |
57871462 | 2618 | }else{ |
259dbd60 | 2619 | emit_slti32(sl,cinfo[i].imm,t); |
57871462 | 2620 | } |
2621 | } | |
2622 | else { // SLTIU | |
2623 | if(sl<0) { | |
630b122b | 2624 | if(i_regs->regmap_entry[t]!=dops[i].rs1) emit_loadreg(dops[i].rs1,t); |
259dbd60 | 2625 | emit_sltiu32(t,cinfo[i].imm,t); |
57871462 | 2626 | }else{ |
259dbd60 | 2627 | emit_sltiu32(sl,cinfo[i].imm,t); |
57871462 | 2628 | } |
2629 | } | |
57871462 | 2630 | }else{ |
2631 | // SLTI(U) with r0 is just stupid, | |
2632 | // nonetheless examples can be found | |
630b122b | 2633 | if(dops[i].opcode==0x0a) // SLTI |
259dbd60 | 2634 | if(0<cinfo[i].imm) emit_movimm(1,t); |
57871462 | 2635 | else emit_zeroreg(t); |
2636 | else // SLTIU | |
2637 | { | |
259dbd60 | 2638 | if(cinfo[i].imm) emit_movimm(1,t); |
57871462 | 2639 | else emit_zeroreg(t); |
2640 | } | |
2641 | } | |
2642 | } | |
2643 | } | |
2644 | } | |
630b122b | 2645 | else if(dops[i].opcode>=0x0c&&dops[i].opcode<=0x0e) { // ANDI/ORI/XORI |
2646 | if(dops[i].rt1) { | |
2647 | signed char sl,tl; | |
f2e25348 | 2648 | tl=get_reg_w(i_regs->regmap, dops[i].rt1); |
630b122b | 2649 | sl=get_reg(i_regs->regmap,dops[i].rs1); |
57871462 | 2650 | if(tl>=0 && !((i_regs->isconst>>tl)&1)) { |
630b122b | 2651 | if(dops[i].opcode==0x0c) //ANDI |
57871462 | 2652 | { |
630b122b | 2653 | if(dops[i].rs1) { |
57871462 | 2654 | if(sl<0) { |
630b122b | 2655 | if(i_regs->regmap_entry[tl]!=dops[i].rs1) emit_loadreg(dops[i].rs1,tl); |
259dbd60 | 2656 | emit_andimm(tl,cinfo[i].imm,tl); |
57871462 | 2657 | }else{ |
2658 | if(!((i_regs->wasconst>>sl)&1)) | |
259dbd60 | 2659 | emit_andimm(sl,cinfo[i].imm,tl); |
57871462 | 2660 | else |
259dbd60 | 2661 | emit_movimm(constmap[i][sl]&cinfo[i].imm,tl); |
57871462 | 2662 | } |
2663 | } | |
2664 | else | |
2665 | emit_zeroreg(tl); | |
57871462 | 2666 | } |
2667 | else | |
2668 | { | |
630b122b | 2669 | if(dops[i].rs1) { |
57871462 | 2670 | if(sl<0) { |
630b122b | 2671 | if(i_regs->regmap_entry[tl]!=dops[i].rs1) emit_loadreg(dops[i].rs1,tl); |
57871462 | 2672 | } |
630b122b | 2673 | if(dops[i].opcode==0x0d) { // ORI |
581335b0 | 2674 | if(sl<0) { |
259dbd60 | 2675 | emit_orimm(tl,cinfo[i].imm,tl); |
581335b0 | 2676 | }else{ |
2677 | if(!((i_regs->wasconst>>sl)&1)) | |
259dbd60 | 2678 | emit_orimm(sl,cinfo[i].imm,tl); |
581335b0 | 2679 | else |
259dbd60 | 2680 | emit_movimm(constmap[i][sl]|cinfo[i].imm,tl); |
581335b0 | 2681 | } |
57871462 | 2682 | } |
630b122b | 2683 | if(dops[i].opcode==0x0e) { // XORI |
581335b0 | 2684 | if(sl<0) { |
259dbd60 | 2685 | emit_xorimm(tl,cinfo[i].imm,tl); |
581335b0 | 2686 | }else{ |
2687 | if(!((i_regs->wasconst>>sl)&1)) | |
259dbd60 | 2688 | emit_xorimm(sl,cinfo[i].imm,tl); |
581335b0 | 2689 | else |
259dbd60 | 2690 | emit_movimm(constmap[i][sl]^cinfo[i].imm,tl); |
581335b0 | 2691 | } |
57871462 | 2692 | } |
2693 | } | |
2694 | else { | |
259dbd60 | 2695 | emit_movimm(cinfo[i].imm,tl); |
57871462 | 2696 | } |
2697 | } | |
2698 | } | |
2699 | } | |
2700 | } | |
2701 | } | |
2702 | ||
630b122b | 2703 | static void shiftimm_assemble(int i, const struct regstat *i_regs) |
57871462 | 2704 | { |
630b122b | 2705 | if(dops[i].opcode2<=0x3) // SLL/SRL/SRA |
57871462 | 2706 | { |
630b122b | 2707 | if(dops[i].rt1) { |
57871462 | 2708 | signed char s,t; |
f2e25348 | 2709 | t=get_reg_w(i_regs->regmap, dops[i].rt1); |
630b122b | 2710 | s=get_reg(i_regs->regmap,dops[i].rs1); |
57871462 | 2711 | //assert(t>=0); |
dc49e339 | 2712 | if(t>=0&&!((i_regs->isconst>>t)&1)){ |
630b122b | 2713 | if(dops[i].rs1==0) |
57871462 | 2714 | { |
2715 | emit_zeroreg(t); | |
2716 | } | |
2717 | else | |
2718 | { | |
630b122b | 2719 | if(s<0&&i_regs->regmap_entry[t]!=dops[i].rs1) emit_loadreg(dops[i].rs1,t); |
259dbd60 | 2720 | if(cinfo[i].imm) { |
630b122b | 2721 | if(dops[i].opcode2==0) // SLL |
57871462 | 2722 | { |
259dbd60 | 2723 | emit_shlimm(s<0?t:s,cinfo[i].imm,t); |
57871462 | 2724 | } |
630b122b | 2725 | if(dops[i].opcode2==2) // SRL |
57871462 | 2726 | { |
259dbd60 | 2727 | emit_shrimm(s<0?t:s,cinfo[i].imm,t); |
57871462 | 2728 | } |
630b122b | 2729 | if(dops[i].opcode2==3) // SRA |
57871462 | 2730 | { |
259dbd60 | 2731 | emit_sarimm(s<0?t:s,cinfo[i].imm,t); |
57871462 | 2732 | } |
2733 | }else{ | |
2734 | // Shift by zero | |
2735 | if(s>=0 && s!=t) emit_mov(s,t); | |
2736 | } | |
2737 | } | |
2738 | } | |
630b122b | 2739 | //emit_storereg(dops[i].rt1,t); //DEBUG |
57871462 | 2740 | } |
2741 | } | |
630b122b | 2742 | if(dops[i].opcode2>=0x38&&dops[i].opcode2<=0x3b) // DSLL/DSRL/DSRA |
57871462 | 2743 | { |
630b122b | 2744 | assert(0); |
57871462 | 2745 | } |
630b122b | 2746 | if(dops[i].opcode2==0x3c) // DSLL32 |
57871462 | 2747 | { |
630b122b | 2748 | assert(0); |
57871462 | 2749 | } |
630b122b | 2750 | if(dops[i].opcode2==0x3e) // DSRL32 |
57871462 | 2751 | { |
630b122b | 2752 | assert(0); |
57871462 | 2753 | } |
630b122b | 2754 | if(dops[i].opcode2==0x3f) // DSRA32 |
57871462 | 2755 | { |
630b122b | 2756 | assert(0); |
57871462 | 2757 | } |
2758 | } | |
2759 | ||
2760 | #ifndef shift_assemble | |
630b122b | 2761 | static void shift_assemble(int i, const struct regstat *i_regs) |
57871462 | 2762 | { |
630b122b | 2763 | signed char s,t,shift; |
2764 | if (dops[i].rt1 == 0) | |
2765 | return; | |
2766 | assert(dops[i].opcode2<=0x07); // SLLV/SRLV/SRAV | |
2767 | t = get_reg(i_regs->regmap, dops[i].rt1); | |
2768 | s = get_reg(i_regs->regmap, dops[i].rs1); | |
2769 | shift = get_reg(i_regs->regmap, dops[i].rs2); | |
2770 | if (t < 0) | |
2771 | return; | |
2772 | ||
2773 | if(dops[i].rs1==0) | |
2774 | emit_zeroreg(t); | |
2775 | else if(dops[i].rs2==0) { | |
2776 | assert(s>=0); | |
2777 | if(s!=t) emit_mov(s,t); | |
2778 | } | |
2779 | else { | |
2780 | host_tempreg_acquire(); | |
2781 | emit_andimm(shift,31,HOST_TEMPREG); | |
2782 | switch(dops[i].opcode2) { | |
2783 | case 4: // SLLV | |
2784 | emit_shl(s,HOST_TEMPREG,t); | |
2785 | break; | |
2786 | case 6: // SRLV | |
2787 | emit_shr(s,HOST_TEMPREG,t); | |
2788 | break; | |
2789 | case 7: // SRAV | |
2790 | emit_sar(s,HOST_TEMPREG,t); | |
2791 | break; | |
2792 | default: | |
2793 | assert(0); | |
2794 | } | |
2795 | host_tempreg_release(); | |
2796 | } | |
57871462 | 2797 | } |
630b122b | 2798 | |
57871462 | 2799 | #endif |
2800 | ||
630b122b | 2801 | enum { |
2802 | MTYPE_8000 = 0, | |
2803 | MTYPE_8020, | |
2804 | MTYPE_0000, | |
2805 | MTYPE_A000, | |
2806 | MTYPE_1F80, | |
2807 | }; | |
2808 | ||
2809 | static int get_ptr_mem_type(u_int a) | |
2810 | { | |
2811 | if(a < 0x00200000) { | |
2812 | if(a<0x1000&&((start>>20)==0xbfc||(start>>24)==0xa0)) | |
2813 | // return wrong, must use memhandler for BIOS self-test to pass | |
2814 | // 007 does similar stuff from a00 mirror, weird stuff | |
2815 | return MTYPE_8000; | |
2816 | return MTYPE_0000; | |
2817 | } | |
2818 | if(0x1f800000 <= a && a < 0x1f801000) | |
2819 | return MTYPE_1F80; | |
2820 | if(0x80200000 <= a && a < 0x80800000) | |
2821 | return MTYPE_8020; | |
2822 | if(0xa0000000 <= a && a < 0xa0200000) | |
2823 | return MTYPE_A000; | |
2824 | return MTYPE_8000; | |
2825 | } | |
2826 | ||
2827 | static int get_ro_reg(const struct regstat *i_regs, int host_tempreg_free) | |
2828 | { | |
2829 | int r = get_reg(i_regs->regmap, ROREG); | |
2830 | if (r < 0 && host_tempreg_free) { | |
2831 | host_tempreg_acquire(); | |
2832 | emit_loadreg(ROREG, r = HOST_TEMPREG); | |
2833 | } | |
2834 | if (r < 0) | |
2835 | abort(); | |
2836 | return r; | |
2837 | } | |
2838 | ||
2839 | static void *emit_fastpath_cmp_jump(int i, const struct regstat *i_regs, | |
259dbd60 | 2840 | int addr, int *offset_reg, int *addr_reg_override, int ccadj_) |
630b122b | 2841 | { |
2842 | void *jaddr = NULL; | |
2843 | int type = 0; | |
2844 | int mr = dops[i].rs1; | |
259dbd60 | 2845 | assert(addr >= 0); |
630b122b | 2846 | *offset_reg = -1; |
2847 | if(((smrv_strong|smrv_weak)>>mr)&1) { | |
2848 | type=get_ptr_mem_type(smrv[mr]); | |
2849 | //printf("set %08x @%08x r%d %d\n", smrv[mr], start+i*4, mr, type); | |
2850 | } | |
2851 | else { | |
2852 | // use the mirror we are running on | |
2853 | type=get_ptr_mem_type(start); | |
2854 | //printf("set nospec @%08x r%d %d\n", start+i*4, mr, type); | |
2855 | } | |
2856 | ||
259dbd60 | 2857 | if (dops[i].may_except) { |
2858 | // alignment check | |
2859 | u_int op = dops[i].opcode; | |
2860 | int mask = ((op & 0x37) == 0x21 || op == 0x25) ? 1 : 3; // LH/SH/LHU | |
e6e590d3 | 2861 | void *jaddr2; |
259dbd60 | 2862 | emit_testimm(addr, mask); |
e6e590d3 | 2863 | jaddr2 = out; |
259dbd60 | 2864 | emit_jne(0); |
e6e590d3 | 2865 | add_stub_r(ALIGNMENT_STUB, jaddr2, out, i, addr, i_regs, ccadj_, 0); |
259dbd60 | 2866 | } |
2867 | ||
630b122b | 2868 | if(type==MTYPE_8020) { // RAM 80200000+ mirror |
2869 | host_tempreg_acquire(); | |
2870 | emit_andimm(addr,~0x00e00000,HOST_TEMPREG); | |
2871 | addr=*addr_reg_override=HOST_TEMPREG; | |
2872 | type=0; | |
2873 | } | |
2874 | else if(type==MTYPE_0000) { // RAM 0 mirror | |
2875 | host_tempreg_acquire(); | |
2876 | emit_orimm(addr,0x80000000,HOST_TEMPREG); | |
2877 | addr=*addr_reg_override=HOST_TEMPREG; | |
2878 | type=0; | |
2879 | } | |
2880 | else if(type==MTYPE_A000) { // RAM A mirror | |
2881 | host_tempreg_acquire(); | |
2882 | emit_andimm(addr,~0x20000000,HOST_TEMPREG); | |
2883 | addr=*addr_reg_override=HOST_TEMPREG; | |
2884 | type=0; | |
2885 | } | |
2886 | else if(type==MTYPE_1F80) { // scratchpad | |
2887 | if (psxH == (void *)0x1f800000) { | |
2888 | host_tempreg_acquire(); | |
2889 | emit_xorimm(addr,0x1f800000,HOST_TEMPREG); | |
2890 | emit_cmpimm(HOST_TEMPREG,0x1000); | |
2891 | host_tempreg_release(); | |
2892 | jaddr=out; | |
2893 | emit_jc(0); | |
2894 | } | |
2895 | else { | |
2896 | // do the usual RAM check, jump will go to the right handler | |
2897 | type=0; | |
2898 | } | |
2899 | } | |
2900 | ||
2901 | if (type == 0) // need ram check | |
2902 | { | |
2903 | emit_cmpimm(addr,RAM_SIZE); | |
2904 | jaddr = out; | |
2905 | #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK | |
2906 | // Hint to branch predictor that the branch is unlikely to be taken | |
2907 | if (dops[i].rs1 >= 28) | |
2908 | emit_jno_unlikely(0); | |
2909 | else | |
2910 | #endif | |
2911 | emit_jno(0); | |
2912 | if (ram_offset != 0) | |
2913 | *offset_reg = get_ro_reg(i_regs, 0); | |
2914 | } | |
2915 | ||
2916 | return jaddr; | |
2917 | } | |
2918 | ||
2919 | // return memhandler, or get directly accessable address and return 0 | |
2920 | static void *get_direct_memhandler(void *table, u_int addr, | |
2921 | enum stub_type type, uintptr_t *addr_host) | |
2922 | { | |
2923 | uintptr_t msb = 1ull << (sizeof(uintptr_t)*8 - 1); | |
2924 | uintptr_t l1, l2 = 0; | |
2925 | l1 = ((uintptr_t *)table)[addr>>12]; | |
2926 | if (!(l1 & msb)) { | |
2927 | uintptr_t v = l1 << 1; | |
2928 | *addr_host = v + addr; | |
2929 | return NULL; | |
2930 | } | |
2931 | else { | |
2932 | l1 <<= 1; | |
2933 | if (type == LOADB_STUB || type == LOADBU_STUB || type == STOREB_STUB) | |
2934 | l2 = ((uintptr_t *)l1)[0x1000/4 + 0x1000/2 + (addr&0xfff)]; | |
2935 | else if (type == LOADH_STUB || type == LOADHU_STUB || type == STOREH_STUB) | |
2936 | l2 = ((uintptr_t *)l1)[0x1000/4 + (addr&0xfff)/2]; | |
2937 | else | |
2938 | l2 = ((uintptr_t *)l1)[(addr&0xfff)/4]; | |
2939 | if (!(l2 & msb)) { | |
2940 | uintptr_t v = l2 << 1; | |
2941 | *addr_host = v + (addr&0xfff); | |
2942 | return NULL; | |
2943 | } | |
2944 | return (void *)(l2 << 1); | |
2945 | } | |
2946 | } | |
2947 | ||
2948 | static u_int get_host_reglist(const signed char *regmap) | |
2949 | { | |
2950 | u_int reglist = 0, hr; | |
2951 | for (hr = 0; hr < HOST_REGS; hr++) { | |
2952 | if (hr != EXCLUDE_REG && regmap[hr] >= 0) | |
2953 | reglist |= 1 << hr; | |
2954 | } | |
2955 | return reglist; | |
2956 | } | |
2957 | ||
2958 | static u_int reglist_exclude(u_int reglist, int r1, int r2) | |
2959 | { | |
2960 | if (r1 >= 0) | |
2961 | reglist &= ~(1u << r1); | |
2962 | if (r2 >= 0) | |
2963 | reglist &= ~(1u << r2); | |
2964 | return reglist; | |
2965 | } | |
2966 | ||
2967 | // find a temp caller-saved register not in reglist (so assumed to be free) | |
2968 | static int reglist_find_free(u_int reglist) | |
2969 | { | |
2970 | u_int free_regs = ~reglist & CALLER_SAVE_REGS; | |
2971 | if (free_regs == 0) | |
2972 | return -1; | |
2973 | return __builtin_ctz(free_regs); | |
2974 | } | |
2975 | ||
2976 | static void do_load_word(int a, int rt, int offset_reg) | |
2977 | { | |
2978 | if (offset_reg >= 0) | |
2979 | emit_ldr_dualindexed(offset_reg, a, rt); | |
2980 | else | |
2981 | emit_readword_indexed(0, a, rt); | |
2982 | } | |
2983 | ||
2984 | static void do_store_word(int a, int ofs, int rt, int offset_reg, int preseve_a) | |
2985 | { | |
2986 | if (offset_reg < 0) { | |
2987 | emit_writeword_indexed(rt, ofs, a); | |
2988 | return; | |
2989 | } | |
2990 | if (ofs != 0) | |
2991 | emit_addimm(a, ofs, a); | |
2992 | emit_str_dualindexed(offset_reg, a, rt); | |
2993 | if (ofs != 0 && preseve_a) | |
2994 | emit_addimm(a, -ofs, a); | |
2995 | } | |
2996 | ||
2997 | static void do_store_hword(int a, int ofs, int rt, int offset_reg, int preseve_a) | |
2998 | { | |
2999 | if (offset_reg < 0) { | |
3000 | emit_writehword_indexed(rt, ofs, a); | |
3001 | return; | |
3002 | } | |
3003 | if (ofs != 0) | |
3004 | emit_addimm(a, ofs, a); | |
3005 | emit_strh_dualindexed(offset_reg, a, rt); | |
3006 | if (ofs != 0 && preseve_a) | |
3007 | emit_addimm(a, -ofs, a); | |
3008 | } | |
3009 | ||
3010 | static void do_store_byte(int a, int rt, int offset_reg) | |
3011 | { | |
3012 | if (offset_reg >= 0) | |
3013 | emit_strb_dualindexed(offset_reg, a, rt); | |
3014 | else | |
3015 | emit_writebyte_indexed(rt, 0, a); | |
3016 | } | |
3017 | ||
3018 | static void load_assemble(int i, const struct regstat *i_regs, int ccadj_) | |
57871462 | 3019 | { |
259dbd60 | 3020 | int addr = cinfo[i].addr; |
3021 | int s,tl; | |
57871462 | 3022 | int offset; |
630b122b | 3023 | void *jaddr=0; |
5bf843dc | 3024 | int memtarget=0,c=0; |
630b122b | 3025 | int offset_reg = -1; |
3026 | int fastio_reg_override = -1; | |
3027 | u_int reglist=get_host_reglist(i_regs->regmap); | |
f2e25348 | 3028 | tl=get_reg_w(i_regs->regmap, dops[i].rt1); |
630b122b | 3029 | s=get_reg(i_regs->regmap,dops[i].rs1); |
259dbd60 | 3030 | offset=cinfo[i].imm; |
57871462 | 3031 | if(i_regs->regmap[HOST_CCREG]==CCREG) reglist&=~(1<<HOST_CCREG); |
3032 | if(s>=0) { | |
3033 | c=(i_regs->wasconst>>s)&1; | |
af4ee1fe | 3034 | if (c) { |
3035 | memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE; | |
af4ee1fe | 3036 | } |
57871462 | 3037 | } |
57871462 | 3038 | //printf("load_assemble: c=%d\n",c); |
630b122b | 3039 | //if(c) printf("load_assemble: const=%lx\n",(long)constmap[i][s]+offset); |
f2e25348 | 3040 | if(tl<0 && ((!c||(((u_int)constmap[i][s]+offset)>>16)==0x1f80) || dops[i].rt1==0)) { |
5bf843dc | 3041 | // could be FIFO, must perform the read |
f18c0f46 | 3042 | // ||dummy read |
5bf843dc | 3043 | assem_debug("(forced read)\n"); |
259dbd60 | 3044 | tl = get_reg_temp(i_regs->regmap); // may be == addr |
5bf843dc | 3045 | assert(tl>=0); |
5bf843dc | 3046 | } |
259dbd60 | 3047 | assert(addr >= 0); |
535d208a | 3048 | if(tl>=0) { |
3049 | //printf("load_assemble: c=%d\n",c); | |
630b122b | 3050 | //if(c) printf("load_assemble: const=%lx\n",(long)constmap[i][s]+offset); |
535d208a | 3051 | reglist&=~(1<<tl); |
1edfcc68 | 3052 | if(!c) { |
1edfcc68 | 3053 | #ifdef R29_HACK |
3054 | // Strmnnrmn's speed hack | |
630b122b | 3055 | if(dops[i].rs1!=29||start<0x80001000||start>=0x80000000+RAM_SIZE) |
1edfcc68 | 3056 | #endif |
3057 | { | |
630b122b | 3058 | jaddr = emit_fastpath_cmp_jump(i, i_regs, addr, |
259dbd60 | 3059 | &offset_reg, &fastio_reg_override, ccadj_); |
535d208a | 3060 | } |
1edfcc68 | 3061 | } |
630b122b | 3062 | else if (ram_offset && memtarget) { |
3063 | offset_reg = get_ro_reg(i_regs, 0); | |
535d208a | 3064 | } |
f2e25348 | 3065 | int dummy=(dops[i].rt1==0)||(tl!=get_reg_w(i_regs->regmap, dops[i].rt1)); // ignore loads to r0 and unneeded reg |
630b122b | 3066 | switch (dops[i].opcode) { |
3067 | case 0x20: // LB | |
535d208a | 3068 | if(!c||memtarget) { |
3069 | if(!dummy) { | |
259dbd60 | 3070 | int a = addr; |
630b122b | 3071 | if (fastio_reg_override >= 0) |
3072 | a = fastio_reg_override; | |
b1570849 | 3073 | |
630b122b | 3074 | if (offset_reg >= 0) |
3075 | emit_ldrsb_dualindexed(offset_reg, a, tl); | |
3076 | else | |
3077 | emit_movsbl_indexed(0, a, tl); | |
57871462 | 3078 | } |
535d208a | 3079 | if(jaddr) |
630b122b | 3080 | add_stub_r(LOADB_STUB,jaddr,out,i,addr,i_regs,ccadj_,reglist); |
57871462 | 3081 | } |
535d208a | 3082 | else |
630b122b | 3083 | inline_readstub(LOADB_STUB,i,constmap[i][s]+offset,i_regs->regmap,dops[i].rt1,ccadj_,reglist); |
3084 | break; | |
3085 | case 0x21: // LH | |
535d208a | 3086 | if(!c||memtarget) { |
3087 | if(!dummy) { | |
259dbd60 | 3088 | int a = addr; |
630b122b | 3089 | if (fastio_reg_override >= 0) |
3090 | a = fastio_reg_override; | |
3091 | if (offset_reg >= 0) | |
3092 | emit_ldrsh_dualindexed(offset_reg, a, tl); | |
57871462 | 3093 | else |
630b122b | 3094 | emit_movswl_indexed(0, a, tl); |
57871462 | 3095 | } |
535d208a | 3096 | if(jaddr) |
630b122b | 3097 | add_stub_r(LOADH_STUB,jaddr,out,i,addr,i_regs,ccadj_,reglist); |
57871462 | 3098 | } |
535d208a | 3099 | else |
630b122b | 3100 | inline_readstub(LOADH_STUB,i,constmap[i][s]+offset,i_regs->regmap,dops[i].rt1,ccadj_,reglist); |
3101 | break; | |
3102 | case 0x23: // LW | |
535d208a | 3103 | if(!c||memtarget) { |
3104 | if(!dummy) { | |
630b122b | 3105 | int a = addr; |
3106 | if (fastio_reg_override >= 0) | |
3107 | a = fastio_reg_override; | |
3108 | do_load_word(a, tl, offset_reg); | |
57871462 | 3109 | } |
535d208a | 3110 | if(jaddr) |
630b122b | 3111 | add_stub_r(LOADW_STUB,jaddr,out,i,addr,i_regs,ccadj_,reglist); |
57871462 | 3112 | } |
535d208a | 3113 | else |
630b122b | 3114 | inline_readstub(LOADW_STUB,i,constmap[i][s]+offset,i_regs->regmap,dops[i].rt1,ccadj_,reglist); |
3115 | break; | |
3116 | case 0x24: // LBU | |
535d208a | 3117 | if(!c||memtarget) { |
3118 | if(!dummy) { | |
259dbd60 | 3119 | int a = addr; |
630b122b | 3120 | if (fastio_reg_override >= 0) |
3121 | a = fastio_reg_override; | |
b1570849 | 3122 | |
630b122b | 3123 | if (offset_reg >= 0) |
3124 | emit_ldrb_dualindexed(offset_reg, a, tl); | |
3125 | else | |
3126 | emit_movzbl_indexed(0, a, tl); | |
57871462 | 3127 | } |
535d208a | 3128 | if(jaddr) |
630b122b | 3129 | add_stub_r(LOADBU_STUB,jaddr,out,i,addr,i_regs,ccadj_,reglist); |
57871462 | 3130 | } |
535d208a | 3131 | else |
630b122b | 3132 | inline_readstub(LOADBU_STUB,i,constmap[i][s]+offset,i_regs->regmap,dops[i].rt1,ccadj_,reglist); |
3133 | break; | |
3134 | case 0x25: // LHU | |
535d208a | 3135 | if(!c||memtarget) { |
3136 | if(!dummy) { | |
259dbd60 | 3137 | int a = addr; |
630b122b | 3138 | if (fastio_reg_override >= 0) |
3139 | a = fastio_reg_override; | |
3140 | if (offset_reg >= 0) | |
3141 | emit_ldrh_dualindexed(offset_reg, a, tl); | |
57871462 | 3142 | else |
630b122b | 3143 | emit_movzwl_indexed(0, a, tl); |
57871462 | 3144 | } |
535d208a | 3145 | if(jaddr) |
630b122b | 3146 | add_stub_r(LOADHU_STUB,jaddr,out,i,addr,i_regs,ccadj_,reglist); |
57871462 | 3147 | } |
535d208a | 3148 | else |
630b122b | 3149 | inline_readstub(LOADHU_STUB,i,constmap[i][s]+offset,i_regs->regmap,dops[i].rt1,ccadj_,reglist); |
3150 | break; | |
630b122b | 3151 | default: |
3152 | assert(0); | |
535d208a | 3153 | } |
f2e25348 | 3154 | } // tl >= 0 |
630b122b | 3155 | if (fastio_reg_override == HOST_TEMPREG || offset_reg == HOST_TEMPREG) |
3156 | host_tempreg_release(); | |
3157 | } | |
3158 | ||
3159 | #ifndef loadlr_assemble | |
3160 | static void loadlr_assemble(int i, const struct regstat *i_regs, int ccadj_) | |
3161 | { | |
259dbd60 | 3162 | int addr = cinfo[i].addr; |
3163 | int s,tl,temp,temp2; | |
630b122b | 3164 | int offset; |
3165 | void *jaddr=0; | |
3166 | int memtarget=0,c=0; | |
3167 | int offset_reg = -1; | |
3168 | int fastio_reg_override = -1; | |
3169 | u_int reglist=get_host_reglist(i_regs->regmap); | |
f2e25348 | 3170 | tl=get_reg_w(i_regs->regmap, dops[i].rt1); |
630b122b | 3171 | s=get_reg(i_regs->regmap,dops[i].rs1); |
91af94f0 | 3172 | temp=get_reg_temp(i_regs->regmap); |
630b122b | 3173 | temp2=get_reg(i_regs->regmap,FTEMP); |
259dbd60 | 3174 | offset=cinfo[i].imm; |
630b122b | 3175 | reglist|=1<<temp; |
259dbd60 | 3176 | assert(addr >= 0); |
630b122b | 3177 | if(s>=0) { |
3178 | c=(i_regs->wasconst>>s)&1; | |
3179 | if(c) { | |
3180 | memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE; | |
535d208a | 3181 | } |
630b122b | 3182 | } |
3183 | if(!c) { | |
3184 | emit_shlimm(addr,3,temp); | |
3185 | if (dops[i].opcode==0x22||dops[i].opcode==0x26) { | |
3186 | emit_andimm(addr,0xFFFFFFFC,temp2); // LWL/LWR | |
3187 | }else{ | |
3188 | emit_andimm(addr,0xFFFFFFF8,temp2); // LDL/LDR | |
3189 | } | |
3190 | jaddr = emit_fastpath_cmp_jump(i, i_regs, temp2, | |
259dbd60 | 3191 | &offset_reg, &fastio_reg_override, ccadj_); |
630b122b | 3192 | } |
3193 | else { | |
3194 | if (ram_offset && memtarget) { | |
3195 | offset_reg = get_ro_reg(i_regs, 0); | |
3196 | } | |
3197 | if (dops[i].opcode==0x22||dops[i].opcode==0x26) { | |
3198 | emit_movimm(((constmap[i][s]+offset)<<3)&24,temp); // LWL/LWR | |
3199 | }else{ | |
3200 | emit_movimm(((constmap[i][s]+offset)<<3)&56,temp); // LDL/LDR | |
57871462 | 3201 | } |
535d208a | 3202 | } |
630b122b | 3203 | if (dops[i].opcode==0x22||dops[i].opcode==0x26) { // LWL/LWR |
535d208a | 3204 | if(!c||memtarget) { |
630b122b | 3205 | int a = temp2; |
3206 | if (fastio_reg_override >= 0) | |
3207 | a = fastio_reg_override; | |
3208 | do_load_word(a, temp2, offset_reg); | |
3209 | if (fastio_reg_override == HOST_TEMPREG || offset_reg == HOST_TEMPREG) | |
3210 | host_tempreg_release(); | |
3211 | if(jaddr) add_stub_r(LOADW_STUB,jaddr,out,i,temp2,i_regs,ccadj_,reglist); | |
57871462 | 3212 | } |
535d208a | 3213 | else |
630b122b | 3214 | inline_readstub(LOADW_STUB,i,(constmap[i][s]+offset)&0xFFFFFFFC,i_regs->regmap,FTEMP,ccadj_,reglist); |
3215 | if(dops[i].rt1) { | |
3216 | assert(tl>=0); | |
3217 | emit_andimm(temp,24,temp); | |
3218 | if (dops[i].opcode==0x22) // LWL | |
3219 | emit_xorimm(temp,24,temp); | |
3220 | host_tempreg_acquire(); | |
3221 | emit_movimm(-1,HOST_TEMPREG); | |
3222 | if (dops[i].opcode==0x26) { | |
3223 | emit_shr(temp2,temp,temp2); | |
3224 | emit_bic_lsr(tl,HOST_TEMPREG,temp,tl); | |
3225 | }else{ | |
3226 | emit_shl(temp2,temp,temp2); | |
3227 | emit_bic_lsl(tl,HOST_TEMPREG,temp,tl); | |
3228 | } | |
3229 | host_tempreg_release(); | |
3230 | emit_or(temp2,tl,tl); | |
3231 | } | |
3232 | //emit_storereg(dops[i].rt1,tl); // DEBUG | |
3233 | } | |
3234 | if (dops[i].opcode==0x1A||dops[i].opcode==0x1B) { // LDL/LDR | |
3235 | assert(0); | |
57871462 | 3236 | } |
57871462 | 3237 | } |
3238 | #endif | |
3239 | ||
bdbf4466 | 3240 | static void do_invstub(int n) |
3241 | { | |
3242 | literal_pool(20); | |
cb13640b | 3243 | assem_debug("do_invstub %x\n", start + stubs[n].e*4); |
bdbf4466 | 3244 | u_int reglist = stubs[n].a; |
3245 | u_int addrr = stubs[n].b; | |
3246 | int ofs_start = stubs[n].c; | |
3247 | int ofs_end = stubs[n].d; | |
3248 | int len = ofs_end - ofs_start; | |
3249 | u_int rightr = 0; | |
3250 | ||
3251 | set_jump_target(stubs[n].addr, out); | |
3252 | save_regs(reglist); | |
bdbf4466 | 3253 | if (addrr != 0 || ofs_start != 0) |
3254 | emit_addimm(addrr, ofs_start, 0); | |
90c6c862 | 3255 | emit_readword(&inv_code_start, 2); |
3256 | emit_readword(&inv_code_end, 3); | |
bdbf4466 | 3257 | if (len != 0) |
3258 | emit_addimm(0, len + 4, (rightr = 1)); | |
3259 | emit_cmp(0, 2); | |
3260 | emit_cmpcs(3, rightr); | |
3261 | void *jaddr = out; | |
3262 | emit_jc(0); | |
3263 | void *func = (len != 0) | |
3264 | ? (void *)ndrc_write_invalidate_many | |
3265 | : (void *)ndrc_write_invalidate_one; | |
3266 | emit_far_call(func); | |
3267 | set_jump_target(jaddr, out); | |
3268 | restore_regs(reglist); | |
3269 | emit_jmp(stubs[n].retaddr); | |
3270 | } | |
3271 | ||
3272 | static void do_store_smc_check(int i, const struct regstat *i_regs, u_int reglist, int addr) | |
3273 | { | |
3274 | if (HACK_ENABLED(NDHACK_NO_SMC_CHECK)) | |
3275 | return; | |
3276 | // this can't be used any more since we started to check exact | |
3277 | // block boundaries in invalidate_range() | |
3278 | //if (i_regs->waswritten & (1<<dops[i].rs1)) | |
3279 | // return; | |
3280 | // (naively) assume nobody will run code from stack | |
3281 | if (dops[i].rs1 == 29) | |
3282 | return; | |
3283 | ||
259dbd60 | 3284 | int j, imm_maxdiff = 32, imm_min = cinfo[i].imm, imm_max = cinfo[i].imm, count = 1; |
bdbf4466 | 3285 | if (i < slen - 1 && dops[i+1].is_store && dops[i+1].rs1 == dops[i].rs1 |
259dbd60 | 3286 | && abs(cinfo[i+1].imm - cinfo[i].imm) <= imm_maxdiff) |
bdbf4466 | 3287 | return; |
3288 | for (j = i - 1; j >= 0; j--) { | |
3289 | if (!dops[j].is_store || dops[j].rs1 != dops[i].rs1 | |
259dbd60 | 3290 | || abs(cinfo[j].imm - cinfo[j+1].imm) > imm_maxdiff) |
bdbf4466 | 3291 | break; |
3292 | count++; | |
259dbd60 | 3293 | if (imm_min > cinfo[j].imm) |
3294 | imm_min = cinfo[j].imm; | |
3295 | if (imm_max < cinfo[j].imm) | |
3296 | imm_max = cinfo[j].imm; | |
bdbf4466 | 3297 | } |
3298 | #if defined(HOST_IMM8) | |
3299 | int ir = get_reg(i_regs->regmap, INVCP); | |
3300 | assert(ir >= 0); | |
3301 | host_tempreg_acquire(); | |
3302 | emit_ldrb_indexedsr12_reg(ir, addr, HOST_TEMPREG); | |
3303 | #else | |
3304 | emit_cmpmem_indexedsr12_imm(invalid_code, addr, 1); | |
3305 | #error not handled | |
3306 | #endif | |
3307 | #ifdef INVALIDATE_USE_COND_CALL | |
3308 | if (count == 1) { | |
3309 | emit_cmpimm(HOST_TEMPREG, 1); | |
3310 | emit_callne(invalidate_addr_reg[addr]); | |
3311 | host_tempreg_release(); | |
3312 | return; | |
3313 | } | |
3314 | #endif | |
3315 | void *jaddr = emit_cbz(HOST_TEMPREG, 0); | |
3316 | host_tempreg_release(); | |
259dbd60 | 3317 | imm_min -= cinfo[i].imm; |
3318 | imm_max -= cinfo[i].imm; | |
bdbf4466 | 3319 | add_stub(INVCODE_STUB, jaddr, out, reglist|(1<<HOST_CCREG), |
cb13640b | 3320 | addr, imm_min, imm_max, i); |
bdbf4466 | 3321 | } |
3322 | ||
cb13640b | 3323 | // determines if code overwrite checking is needed only |
3324 | // (also true non-existent 0x20000000 mirror that shouldn't matter) | |
3325 | #define is_ram_addr(a) !((a) & 0x5f800000) | |
3326 | ||
630b122b | 3327 | static void store_assemble(int i, const struct regstat *i_regs, int ccadj_) |
57871462 | 3328 | { |
630b122b | 3329 | int s,tl; |
259dbd60 | 3330 | int addr = cinfo[i].addr; |
57871462 | 3331 | int offset; |
630b122b | 3332 | void *jaddr=0; |
3333 | enum stub_type type=0; | |
666a299d | 3334 | int memtarget=0,c=0; |
630b122b | 3335 | int offset_reg = -1; |
3336 | int fastio_reg_override = -1; | |
cb13640b | 3337 | u_int addr_const = ~0; |
630b122b | 3338 | u_int reglist=get_host_reglist(i_regs->regmap); |
3339 | tl=get_reg(i_regs->regmap,dops[i].rs2); | |
3340 | s=get_reg(i_regs->regmap,dops[i].rs1); | |
259dbd60 | 3341 | offset=cinfo[i].imm; |
57871462 | 3342 | if(s>=0) { |
3343 | c=(i_regs->wasconst>>s)&1; | |
cb13640b | 3344 | if (c) { |
3345 | addr_const = constmap[i][s] + offset; | |
3346 | memtarget = ((signed int)addr_const) < (signed int)(0x80000000 + RAM_SIZE); | |
af4ee1fe | 3347 | } |
57871462 | 3348 | } |
3349 | assert(tl>=0); | |
259dbd60 | 3350 | assert(addr >= 0); |
57871462 | 3351 | if(i_regs->regmap[HOST_CCREG]==CCREG) reglist&=~(1<<HOST_CCREG); |
cb13640b | 3352 | reglist |= 1u << addr; |
630b122b | 3353 | if (!c) { |
3354 | jaddr = emit_fastpath_cmp_jump(i, i_regs, addr, | |
259dbd60 | 3355 | &offset_reg, &fastio_reg_override, ccadj_); |
1edfcc68 | 3356 | } |
630b122b | 3357 | else if (ram_offset && memtarget) { |
3358 | offset_reg = get_ro_reg(i_regs, 0); | |
57871462 | 3359 | } |
3360 | ||
630b122b | 3361 | switch (dops[i].opcode) { |
3362 | case 0x28: // SB | |
57871462 | 3363 | if(!c||memtarget) { |
259dbd60 | 3364 | int a = addr; |
630b122b | 3365 | if (fastio_reg_override >= 0) |
3366 | a = fastio_reg_override; | |
3367 | do_store_byte(a, tl, offset_reg); | |
3368 | } | |
3369 | type = STOREB_STUB; | |
3370 | break; | |
3371 | case 0x29: // SH | |
dadf55f2 | 3372 | if(!c||memtarget) { |
259dbd60 | 3373 | int a = addr; |
630b122b | 3374 | if (fastio_reg_override >= 0) |
3375 | a = fastio_reg_override; | |
3376 | do_store_hword(a, 0, tl, offset_reg, 1); | |
3377 | } | |
3378 | type = STOREH_STUB; | |
3379 | break; | |
3380 | case 0x2B: // SW | |
57871462 | 3381 | if(!c||memtarget) { |
630b122b | 3382 | int a = addr; |
3383 | if (fastio_reg_override >= 0) | |
3384 | a = fastio_reg_override; | |
3385 | do_store_word(a, 0, tl, offset_reg, 1); | |
3386 | } | |
3387 | type = STOREW_STUB; | |
3388 | break; | |
630b122b | 3389 | default: |
3390 | assert(0); | |
3391 | } | |
3392 | if (fastio_reg_override == HOST_TEMPREG || offset_reg == HOST_TEMPREG) | |
3393 | host_tempreg_release(); | |
cb13640b | 3394 | if (jaddr) { |
b96d3df7 | 3395 | // PCSX store handlers don't check invcode again |
630b122b | 3396 | add_stub_r(type,jaddr,out,i,addr,i_regs,ccadj_,reglist); |
7a518516 | 3397 | } |
cb13640b | 3398 | if (!c || is_ram_addr(addr_const)) |
3399 | do_store_smc_check(i, i_regs, reglist, addr); | |
3400 | if (c && !memtarget) | |
3401 | inline_writestub(type, i, addr_const, i_regs->regmap, dops[i].rs2, ccadj_, reglist); | |
7a518516 | 3402 | // basic current block modification detection.. |
3403 | // not looking back as that should be in mips cache already | |
630b122b | 3404 | // (see Spyro2 title->attract mode) |
cb13640b | 3405 | if (start + i*4 < addr_const && addr_const < start + slen*4) { |
3406 | SysPrintf("write to %08x hits block %08x, pc=%08x\n", addr_const, start, start+i*4); | |
7a518516 | 3407 | assert(i_regs->regmap==regs[i].regmap); // not delay slot |
3408 | if(i_regs->regmap==regs[i].regmap) { | |
630b122b | 3409 | load_all_consts(regs[i].regmap_entry,regs[i].wasdirty,i); |
3410 | wb_dirtys(regs[i].regmap_entry,regs[i].wasdirty); | |
7a518516 | 3411 | emit_movimm(start+i*4+4,0); |
630b122b | 3412 | emit_writeword(0,&pcaddr); |
3413 | emit_addimm(HOST_CCREG,2,HOST_CCREG); | |
048fcced | 3414 | emit_far_call(ndrc_get_addr_ht); |
630b122b | 3415 | emit_jmpreg(0); |
7a518516 | 3416 | } |
3eaa7048 | 3417 | } |
57871462 | 3418 | } |
3419 | ||
630b122b | 3420 | static void storelr_assemble(int i, const struct regstat *i_regs, int ccadj_) |
57871462 | 3421 | { |
259dbd60 | 3422 | int addr = cinfo[i].addr; |
630b122b | 3423 | int s,tl; |
57871462 | 3424 | int offset; |
630b122b | 3425 | void *jaddr=0; |
3426 | void *case1, *case23, *case3; | |
3427 | void *done0, *done1, *done2; | |
af4ee1fe | 3428 | int memtarget=0,c=0; |
630b122b | 3429 | int offset_reg = -1; |
cb13640b | 3430 | u_int addr_const = ~0; |
3431 | u_int reglist = get_host_reglist(i_regs->regmap); | |
630b122b | 3432 | tl=get_reg(i_regs->regmap,dops[i].rs2); |
3433 | s=get_reg(i_regs->regmap,dops[i].rs1); | |
259dbd60 | 3434 | offset=cinfo[i].imm; |
57871462 | 3435 | if(s>=0) { |
cb13640b | 3436 | c = (i_regs->isconst >> s) & 1; |
3437 | if (c) { | |
3438 | addr_const = constmap[i][s] + offset; | |
3439 | memtarget = ((signed int)addr_const) < (signed int)(0x80000000 + RAM_SIZE); | |
af4ee1fe | 3440 | } |
57871462 | 3441 | } |
3442 | assert(tl>=0); | |
259dbd60 | 3443 | assert(addr >= 0); |
cb13640b | 3444 | reglist |= 1u << addr; |
1edfcc68 | 3445 | if(!c) { |
259dbd60 | 3446 | emit_cmpimm(addr, RAM_SIZE); |
630b122b | 3447 | jaddr=out; |
1edfcc68 | 3448 | emit_jno(0); |
3449 | } | |
3450 | else | |
3451 | { | |
630b122b | 3452 | if(!memtarget||!dops[i].rs1) { |
3453 | jaddr=out; | |
535d208a | 3454 | emit_jmp(0); |
57871462 | 3455 | } |
535d208a | 3456 | } |
630b122b | 3457 | if (ram_offset) |
3458 | offset_reg = get_ro_reg(i_regs, 0); | |
535d208a | 3459 | |
259dbd60 | 3460 | emit_testimm(addr,2); |
630b122b | 3461 | case23=out; |
535d208a | 3462 | emit_jne(0); |
259dbd60 | 3463 | emit_testimm(addr,1); |
630b122b | 3464 | case1=out; |
535d208a | 3465 | emit_jne(0); |
3466 | // 0 | |
630b122b | 3467 | if (dops[i].opcode == 0x2A) { // SWL |
3468 | // Write msb into least significant byte | |
3469 | if (dops[i].rs2) emit_rorimm(tl, 24, tl); | |
259dbd60 | 3470 | do_store_byte(addr, tl, offset_reg); |
630b122b | 3471 | if (dops[i].rs2) emit_rorimm(tl, 8, tl); |
535d208a | 3472 | } |
630b122b | 3473 | else if (dops[i].opcode == 0x2E) { // SWR |
3474 | // Write entire word | |
259dbd60 | 3475 | do_store_word(addr, 0, tl, offset_reg, 1); |
535d208a | 3476 | } |
630b122b | 3477 | done0 = out; |
535d208a | 3478 | emit_jmp(0); |
3479 | // 1 | |
630b122b | 3480 | set_jump_target(case1, out); |
3481 | if (dops[i].opcode == 0x2A) { // SWL | |
3482 | // Write two msb into two least significant bytes | |
3483 | if (dops[i].rs2) emit_rorimm(tl, 16, tl); | |
cb13640b | 3484 | do_store_hword(addr, -1, tl, offset_reg, 1); |
630b122b | 3485 | if (dops[i].rs2) emit_rorimm(tl, 16, tl); |
535d208a | 3486 | } |
630b122b | 3487 | else if (dops[i].opcode == 0x2E) { // SWR |
3488 | // Write 3 lsb into three most significant bytes | |
259dbd60 | 3489 | do_store_byte(addr, tl, offset_reg); |
630b122b | 3490 | if (dops[i].rs2) emit_rorimm(tl, 8, tl); |
cb13640b | 3491 | do_store_hword(addr, 1, tl, offset_reg, 1); |
630b122b | 3492 | if (dops[i].rs2) emit_rorimm(tl, 24, tl); |
535d208a | 3493 | } |
630b122b | 3494 | done1=out; |
535d208a | 3495 | emit_jmp(0); |
630b122b | 3496 | // 2,3 |
3497 | set_jump_target(case23, out); | |
259dbd60 | 3498 | emit_testimm(addr,1); |
630b122b | 3499 | case3 = out; |
535d208a | 3500 | emit_jne(0); |
630b122b | 3501 | // 2 |
3502 | if (dops[i].opcode==0x2A) { // SWL | |
3503 | // Write 3 msb into three least significant bytes | |
3504 | if (dops[i].rs2) emit_rorimm(tl, 8, tl); | |
259dbd60 | 3505 | do_store_hword(addr, -2, tl, offset_reg, 1); |
630b122b | 3506 | if (dops[i].rs2) emit_rorimm(tl, 16, tl); |
259dbd60 | 3507 | do_store_byte(addr, tl, offset_reg); |
630b122b | 3508 | if (dops[i].rs2) emit_rorimm(tl, 8, tl); |
535d208a | 3509 | } |
630b122b | 3510 | else if (dops[i].opcode == 0x2E) { // SWR |
3511 | // Write two lsb into two most significant bytes | |
259dbd60 | 3512 | do_store_hword(addr, 0, tl, offset_reg, 1); |
535d208a | 3513 | } |
630b122b | 3514 | done2 = out; |
535d208a | 3515 | emit_jmp(0); |
3516 | // 3 | |
630b122b | 3517 | set_jump_target(case3, out); |
3518 | if (dops[i].opcode == 0x2A) { // SWL | |
cb13640b | 3519 | do_store_word(addr, -3, tl, offset_reg, 1); |
630b122b | 3520 | } |
3521 | else if (dops[i].opcode == 0x2E) { // SWR | |
259dbd60 | 3522 | do_store_byte(addr, tl, offset_reg); |
630b122b | 3523 | } |
3524 | set_jump_target(done0, out); | |
3525 | set_jump_target(done1, out); | |
3526 | set_jump_target(done2, out); | |
3527 | if (offset_reg == HOST_TEMPREG) | |
3528 | host_tempreg_release(); | |
cb13640b | 3529 | if (!c || !memtarget) |
259dbd60 | 3530 | add_stub_r(STORELR_STUB,jaddr,out,i,addr,i_regs,ccadj_,reglist); |
cb13640b | 3531 | if (!c || is_ram_addr(addr_const)) |
3532 | do_store_smc_check(i, i_regs, reglist, addr); | |
57871462 | 3533 | } |
3534 | ||
630b122b | 3535 | static void cop0_assemble(int i, const struct regstat *i_regs, int ccadj_) |
3536 | { | |
3537 | if(dops[i].opcode2==0) // MFC0 | |
3538 | { | |
f2e25348 | 3539 | signed char t=get_reg_w(i_regs->regmap, dops[i].rt1); |
630b122b | 3540 | u_int copr=(source[i]>>11)&0x1f; |
630b122b | 3541 | if(t>=0&&dops[i].rt1!=0) { |
3542 | emit_readword(®_cop0[copr],t); | |
3543 | } | |
3544 | } | |
3545 | else if(dops[i].opcode2==4) // MTC0 | |
3546 | { | |
5753f874 | 3547 | int s = get_reg(i_regs->regmap, dops[i].rs1); |
3548 | int cc = get_reg(i_regs->regmap, CCREG); | |
630b122b | 3549 | char copr=(source[i]>>11)&0x1f; |
3550 | assert(s>=0); | |
3551 | wb_register(dops[i].rs1,i_regs->regmap,i_regs->dirty); | |
5753f874 | 3552 | if (copr == 12 || copr == 13) { |
630b122b | 3553 | emit_readword(&last_count,HOST_TEMPREG); |
5753f874 | 3554 | if (cc != HOST_CCREG) |
3555 | emit_loadreg(CCREG, HOST_CCREG); | |
3556 | emit_add(HOST_CCREG, HOST_TEMPREG, HOST_CCREG); | |
3557 | emit_addimm(HOST_CCREG, ccadj_ + 2, HOST_CCREG); | |
3558 | emit_writeword(HOST_CCREG, &psxRegs.cycle); | |
630b122b | 3559 | if (is_delayslot) { |
3560 | // burn cycles to cause cc_interrupt, which will | |
3561 | // reschedule next_interupt. Relies on CCREG from above. | |
3562 | assem_debug("MTC0 DS %d\n", copr); | |
3563 | emit_writeword(HOST_CCREG,&last_count); | |
3564 | emit_movimm(0,HOST_CCREG); | |
3565 | emit_storereg(CCREG,HOST_CCREG); | |
3566 | emit_loadreg(dops[i].rs1,1); | |
3567 | emit_movimm(copr,0); | |
3568 | emit_far_call(pcsx_mtc0_ds); | |
3569 | emit_loadreg(dops[i].rs1,s); | |
3570 | return; | |
3571 | } | |
3572 | emit_movimm(start+i*4+4,HOST_TEMPREG); | |
3573 | emit_writeword(HOST_TEMPREG,&pcaddr); | |
3574 | emit_movimm(0,HOST_TEMPREG); | |
3575 | emit_writeword(HOST_TEMPREG,&pending_exception); | |
3576 | } | |
5753f874 | 3577 | if( s != 1) |
3578 | emit_mov(s, 1); | |
3579 | emit_movimm(copr, 0); | |
630b122b | 3580 | emit_far_call(pcsx_mtc0); |
5753f874 | 3581 | if (copr == 12 || copr == 13) { |
a1c43985 | 3582 | emit_readword(&psxRegs.cycle,HOST_CCREG); |
5753f874 | 3583 | emit_readword(&last_count,HOST_TEMPREG); |
630b122b | 3584 | emit_sub(HOST_CCREG,HOST_TEMPREG,HOST_CCREG); |
5753f874 | 3585 | //emit_writeword(HOST_TEMPREG,&last_count); |
630b122b | 3586 | assert(!is_delayslot); |
bdbf4466 | 3587 | emit_readword(&pending_exception,HOST_TEMPREG); |
3588 | emit_test(HOST_TEMPREG,HOST_TEMPREG); | |
630b122b | 3589 | void *jaddr = out; |
3590 | emit_jeq(0); | |
3591 | emit_readword(&pcaddr, 0); | |
048fcced | 3592 | emit_far_call(ndrc_get_addr_ht); |
630b122b | 3593 | emit_jmpreg(0); |
3594 | set_jump_target(jaddr, out); | |
5753f874 | 3595 | emit_addimm(HOST_CCREG, -ccadj_ - 2, HOST_CCREG); |
3596 | if (cc != HOST_CCREG) | |
3597 | emit_storereg(CCREG, HOST_CCREG); | |
630b122b | 3598 | } |
3599 | emit_loadreg(dops[i].rs1,s); | |
3600 | } | |
630b122b | 3601 | } |
3602 | ||
259dbd60 | 3603 | static void rfe_assemble(int i, const struct regstat *i_regs) |
57871462 | 3604 | { |
f2e25348 | 3605 | emit_readword(&psxRegs.CP0.n.SR, 0); |
3606 | emit_andimm(0, 0x3c, 1); | |
3607 | emit_andimm(0, ~0xf, 0); | |
3608 | emit_orrshr_imm(1, 2, 0); | |
3609 | emit_writeword(0, &psxRegs.CP0.n.SR); | |
630b122b | 3610 | } |
3611 | ||
3612 | static int cop2_is_stalling_op(int i, int *cycles) | |
3613 | { | |
3614 | if (dops[i].opcode == 0x3a) { // SWC2 | |
3615 | *cycles = 0; | |
3616 | return 1; | |
3617 | } | |
3618 | if (dops[i].itype == COP2 && (dops[i].opcode2 == 0 || dops[i].opcode2 == 2)) { // MFC2/CFC2 | |
3619 | *cycles = 0; | |
3620 | return 1; | |
3621 | } | |
3622 | if (dops[i].itype == C2OP) { | |
3623 | *cycles = gte_cycletab[source[i] & 0x3f]; | |
3624 | return 1; | |
3625 | } | |
3626 | // ... what about MTC2/CTC2/LWC2? | |
3627 | return 0; | |
3628 | } | |
3629 | ||
3630 | #if 0 | |
3631 | static void log_gte_stall(int stall, u_int cycle) | |
3632 | { | |
3633 | if ((u_int)stall <= 44) | |
3634 | printf("x stall %2d %u\n", stall, cycle + last_count); | |
3635 | } | |
3636 | ||
3637 | static void emit_log_gte_stall(int i, int stall, u_int reglist) | |
3638 | { | |
3639 | save_regs(reglist); | |
3640 | if (stall > 0) | |
3641 | emit_movimm(stall, 0); | |
3642 | else | |
3643 | emit_mov(HOST_TEMPREG, 0); | |
259dbd60 | 3644 | emit_addimm(HOST_CCREG, cinfo[i].ccadj, 1); |
630b122b | 3645 | emit_far_call(log_gte_stall); |
3646 | restore_regs(reglist); | |
3647 | } | |
3648 | #endif | |
3649 | ||
3650 | static void cop2_do_stall_check(u_int op, int i, const struct regstat *i_regs, u_int reglist) | |
3651 | { | |
3652 | int j = i, other_gte_op_cycles = -1, stall = -MAXBLOCK, cycles_passed; | |
3653 | int rtmp = reglist_find_free(reglist); | |
3654 | ||
3655 | if (HACK_ENABLED(NDHACK_NO_STALLS)) | |
3656 | return; | |
3657 | if (get_reg(i_regs->regmap, CCREG) != HOST_CCREG) { | |
3658 | // happens occasionally... cc evicted? Don't bother then | |
3659 | //printf("no cc %08x\n", start + i*4); | |
3660 | return; | |
3661 | } | |
3662 | if (!dops[i].bt) { | |
3663 | for (j = i - 1; j >= 0; j--) { | |
3664 | //if (dops[j].is_ds) break; | |
3665 | if (cop2_is_stalling_op(j, &other_gte_op_cycles) || dops[j].bt) | |
3666 | break; | |
259dbd60 | 3667 | if (j > 0 && cinfo[j - 1].ccadj > cinfo[j].ccadj) |
630b122b | 3668 | break; |
3669 | } | |
3670 | j = max(j, 0); | |
3671 | } | |
259dbd60 | 3672 | cycles_passed = cinfo[i].ccadj - cinfo[j].ccadj; |
630b122b | 3673 | if (other_gte_op_cycles >= 0) |
3674 | stall = other_gte_op_cycles - cycles_passed; | |
3675 | else if (cycles_passed >= 44) | |
3676 | stall = 0; // can't stall | |
3677 | if (stall == -MAXBLOCK && rtmp >= 0) { | |
3678 | // unknown stall, do the expensive runtime check | |
3679 | assem_debug("; cop2_do_stall_check\n"); | |
3680 | #if 0 // too slow | |
3681 | save_regs(reglist); | |
3682 | emit_movimm(gte_cycletab[op], 0); | |
259dbd60 | 3683 | emit_addimm(HOST_CCREG, cinfo[i].ccadj, 1); |
630b122b | 3684 | emit_far_call(call_gteStall); |
3685 | restore_regs(reglist); | |
3686 | #else | |
3687 | host_tempreg_acquire(); | |
3688 | emit_readword(&psxRegs.gteBusyCycle, rtmp); | |
259dbd60 | 3689 | emit_addimm(rtmp, -cinfo[i].ccadj, rtmp); |
630b122b | 3690 | emit_sub(rtmp, HOST_CCREG, HOST_TEMPREG); |
3691 | emit_cmpimm(HOST_TEMPREG, 44); | |
3692 | emit_cmovb_reg(rtmp, HOST_CCREG); | |
3693 | //emit_log_gte_stall(i, 0, reglist); | |
3694 | host_tempreg_release(); | |
3695 | #endif | |
3696 | } | |
3697 | else if (stall > 0) { | |
3698 | //emit_log_gte_stall(i, stall, reglist); | |
3699 | emit_addimm(HOST_CCREG, stall, HOST_CCREG); | |
3700 | } | |
3701 | ||
3702 | // save gteBusyCycle, if needed | |
3703 | if (gte_cycletab[op] == 0) | |
3704 | return; | |
3705 | other_gte_op_cycles = -1; | |
3706 | for (j = i + 1; j < slen; j++) { | |
3707 | if (cop2_is_stalling_op(j, &other_gte_op_cycles)) | |
3708 | break; | |
3709 | if (dops[j].is_jump) { | |
3710 | // check ds | |
3711 | if (j + 1 < slen && cop2_is_stalling_op(j + 1, &other_gte_op_cycles)) | |
3712 | j++; | |
3713 | break; | |
3714 | } | |
3715 | } | |
3716 | if (other_gte_op_cycles >= 0) | |
3717 | // will handle stall when assembling that op | |
3718 | return; | |
259dbd60 | 3719 | cycles_passed = cinfo[min(j, slen -1)].ccadj - cinfo[i].ccadj; |
630b122b | 3720 | if (cycles_passed >= 44) |
3721 | return; | |
3722 | assem_debug("; save gteBusyCycle\n"); | |
3723 | host_tempreg_acquire(); | |
3724 | #if 0 | |
3725 | emit_readword(&last_count, HOST_TEMPREG); | |
3726 | emit_add(HOST_TEMPREG, HOST_CCREG, HOST_TEMPREG); | |
259dbd60 | 3727 | emit_addimm(HOST_TEMPREG, cinfo[i].ccadj, HOST_TEMPREG); |
630b122b | 3728 | emit_addimm(HOST_TEMPREG, gte_cycletab[op]), HOST_TEMPREG); |
3729 | emit_writeword(HOST_TEMPREG, &psxRegs.gteBusyCycle); | |
3730 | #else | |
259dbd60 | 3731 | emit_addimm(HOST_CCREG, cinfo[i].ccadj + gte_cycletab[op], HOST_TEMPREG); |
630b122b | 3732 | emit_writeword(HOST_TEMPREG, &psxRegs.gteBusyCycle); |
3733 | #endif | |
3734 | host_tempreg_release(); | |
3735 | } | |
3736 | ||
3737 | static int is_mflohi(int i) | |
3738 | { | |
3739 | return (dops[i].itype == MOV && (dops[i].rs1 == HIREG || dops[i].rs1 == LOREG)); | |
3740 | } | |
3741 | ||
3742 | static int check_multdiv(int i, int *cycles) | |
3743 | { | |
3744 | if (dops[i].itype != MULTDIV) | |
3745 | return 0; | |
3746 | if (dops[i].opcode2 == 0x18 || dops[i].opcode2 == 0x19) // MULT(U) | |
3747 | *cycles = 11; // approx from 7 11 14 | |
3748 | else | |
3749 | *cycles = 37; | |
3750 | return 1; | |
3751 | } | |
3752 | ||
3753 | static void multdiv_prepare_stall(int i, const struct regstat *i_regs, int ccadj_) | |
3754 | { | |
3755 | int j, found = 0, c = 0; | |
3756 | if (HACK_ENABLED(NDHACK_NO_STALLS)) | |
3757 | return; | |
3758 | if (get_reg(i_regs->regmap, CCREG) != HOST_CCREG) { | |
3759 | // happens occasionally... cc evicted? Don't bother then | |
3760 | return; | |
3761 | } | |
3762 | for (j = i + 1; j < slen; j++) { | |
3763 | if (dops[j].bt) | |
3764 | break; | |
3765 | if ((found = is_mflohi(j))) | |
3766 | break; | |
3767 | if (dops[j].is_jump) { | |
3768 | // check ds | |
3769 | if (j + 1 < slen && (found = is_mflohi(j + 1))) | |
3770 | j++; | |
3771 | break; | |
3772 | } | |
3773 | } | |
3774 | if (found) | |
3775 | // handle all in multdiv_do_stall() | |
3776 | return; | |
3777 | check_multdiv(i, &c); | |
3778 | assert(c > 0); | |
3779 | assem_debug("; muldiv prepare stall %d\n", c); | |
3780 | host_tempreg_acquire(); | |
3781 | emit_addimm(HOST_CCREG, ccadj_ + c, HOST_TEMPREG); | |
3782 | emit_writeword(HOST_TEMPREG, &psxRegs.muldivBusyCycle); | |
3783 | host_tempreg_release(); | |
3784 | } | |
3785 | ||
3786 | static void multdiv_do_stall(int i, const struct regstat *i_regs) | |
3787 | { | |
3788 | int j, known_cycles = 0; | |
3789 | u_int reglist = get_host_reglist(i_regs->regmap); | |
91af94f0 | 3790 | int rtmp = get_reg_temp(i_regs->regmap); |
630b122b | 3791 | if (rtmp < 0) |
3792 | rtmp = reglist_find_free(reglist); | |
3793 | if (HACK_ENABLED(NDHACK_NO_STALLS)) | |
3794 | return; | |
3795 | if (get_reg(i_regs->regmap, CCREG) != HOST_CCREG || rtmp < 0) { | |
3796 | // happens occasionally... cc evicted? Don't bother then | |
3797 | //printf("no cc/rtmp %08x\n", start + i*4); | |
3798 | return; | |
3799 | } | |
3800 | if (!dops[i].bt) { | |
3801 | for (j = i - 1; j >= 0; j--) { | |
3802 | if (dops[j].is_ds) break; | |
3803 | if (check_multdiv(j, &known_cycles)) | |
3804 | break; | |
3805 | if (is_mflohi(j)) | |
3806 | // already handled by this op | |
3807 | return; | |
259dbd60 | 3808 | if (dops[j].bt || (j > 0 && cinfo[j - 1].ccadj > cinfo[j].ccadj)) |
630b122b | 3809 | break; |
3810 | } | |
3811 | j = max(j, 0); | |
3812 | } | |
3813 | if (known_cycles > 0) { | |
259dbd60 | 3814 | known_cycles -= cinfo[i].ccadj - cinfo[j].ccadj; |
630b122b | 3815 | assem_debug("; muldiv stall resolved %d\n", known_cycles); |
3816 | if (known_cycles > 0) | |
3817 | emit_addimm(HOST_CCREG, known_cycles, HOST_CCREG); | |
3818 | return; | |
3819 | } | |
3820 | assem_debug("; muldiv stall unresolved\n"); | |
3821 | host_tempreg_acquire(); | |
3822 | emit_readword(&psxRegs.muldivBusyCycle, rtmp); | |
259dbd60 | 3823 | emit_addimm(rtmp, -cinfo[i].ccadj, rtmp); |
630b122b | 3824 | emit_sub(rtmp, HOST_CCREG, HOST_TEMPREG); |
3825 | emit_cmpimm(HOST_TEMPREG, 37); | |
3826 | emit_cmovb_reg(rtmp, HOST_CCREG); | |
3827 | //emit_log_gte_stall(i, 0, reglist); | |
3828 | host_tempreg_release(); | |
3829 | } | |
3830 | ||
3831 | static void cop2_get_dreg(u_int copr,signed char tl,signed char temp) | |
3832 | { | |
3833 | switch (copr) { | |
3834 | case 1: | |
3835 | case 3: | |
3836 | case 5: | |
3837 | case 8: | |
3838 | case 9: | |
3839 | case 10: | |
3840 | case 11: | |
3841 | emit_readword(®_cop2d[copr],tl); | |
3842 | emit_signextend16(tl,tl); | |
3843 | emit_writeword(tl,®_cop2d[copr]); // hmh | |
3844 | break; | |
3845 | case 7: | |
3846 | case 16: | |
3847 | case 17: | |
3848 | case 18: | |
3849 | case 19: | |
3850 | emit_readword(®_cop2d[copr],tl); | |
3851 | emit_andimm(tl,0xffff,tl); | |
3852 | emit_writeword(tl,®_cop2d[copr]); | |
3853 | break; | |
3854 | case 15: | |
3855 | emit_readword(®_cop2d[14],tl); // SXY2 | |
3856 | emit_writeword(tl,®_cop2d[copr]); | |
3857 | break; | |
3858 | case 28: | |
3859 | case 29: | |
3860 | c2op_mfc2_29_assemble(tl,temp); | |
3861 | break; | |
3862 | default: | |
3863 | emit_readword(®_cop2d[copr],tl); | |
3864 | break; | |
3865 | } | |
3866 | } | |
3867 | ||
3868 | static void cop2_put_dreg(u_int copr,signed char sl,signed char temp) | |
3869 | { | |
3870 | switch (copr) { | |
3871 | case 15: | |
3872 | emit_readword(®_cop2d[13],temp); // SXY1 | |
3873 | emit_writeword(sl,®_cop2d[copr]); | |
3874 | emit_writeword(temp,®_cop2d[12]); // SXY0 | |
3875 | emit_readword(®_cop2d[14],temp); // SXY2 | |
3876 | emit_writeword(sl,®_cop2d[14]); | |
3877 | emit_writeword(temp,®_cop2d[13]); // SXY1 | |
3878 | break; | |
3879 | case 28: | |
3880 | emit_andimm(sl,0x001f,temp); | |
3881 | emit_shlimm(temp,7,temp); | |
3882 | emit_writeword(temp,®_cop2d[9]); | |
3883 | emit_andimm(sl,0x03e0,temp); | |
3884 | emit_shlimm(temp,2,temp); | |
3885 | emit_writeword(temp,®_cop2d[10]); | |
3886 | emit_andimm(sl,0x7c00,temp); | |
3887 | emit_shrimm(temp,3,temp); | |
3888 | emit_writeword(temp,®_cop2d[11]); | |
3889 | emit_writeword(sl,®_cop2d[28]); | |
3890 | break; | |
3891 | case 30: | |
3892 | emit_xorsar_imm(sl,sl,31,temp); | |
3893 | #if defined(HAVE_ARMV5) || defined(__aarch64__) | |
3894 | emit_clz(temp,temp); | |
3895 | #else | |
3896 | emit_movs(temp,HOST_TEMPREG); | |
3897 | emit_movimm(0,temp); | |
3898 | emit_jeq((int)out+4*4); | |
3899 | emit_addpl_imm(temp,1,temp); | |
3900 | emit_lslpls_imm(HOST_TEMPREG,1,HOST_TEMPREG); | |
3901 | emit_jns((int)out-2*4); | |
3902 | #endif | |
3903 | emit_writeword(sl,®_cop2d[30]); | |
3904 | emit_writeword(temp,®_cop2d[31]); | |
3905 | break; | |
3906 | case 31: | |
3907 | break; | |
3908 | default: | |
3909 | emit_writeword(sl,®_cop2d[copr]); | |
3910 | break; | |
3911 | } | |
3912 | } | |
3913 | ||
3914 | static void c2ls_assemble(int i, const struct regstat *i_regs, int ccadj_) | |
b9b61529 | 3915 | { |
3916 | int s,tl; | |
3917 | int ar; | |
3918 | int offset; | |
1fd1aceb | 3919 | int memtarget=0,c=0; |
630b122b | 3920 | void *jaddr2=NULL; |
3921 | enum stub_type type; | |
630b122b | 3922 | int offset_reg = -1; |
3923 | int fastio_reg_override = -1; | |
cb13640b | 3924 | u_int addr_const = ~0; |
630b122b | 3925 | u_int reglist=get_host_reglist(i_regs->regmap); |
b9b61529 | 3926 | u_int copr=(source[i]>>16)&0x1f; |
630b122b | 3927 | s=get_reg(i_regs->regmap,dops[i].rs1); |
b9b61529 | 3928 | tl=get_reg(i_regs->regmap,FTEMP); |
259dbd60 | 3929 | offset=cinfo[i].imm; |
b9b61529 | 3930 | assert(tl>=0); |
b9b61529 | 3931 | |
b9b61529 | 3932 | if(i_regs->regmap[HOST_CCREG]==CCREG) |
3933 | reglist&=~(1<<HOST_CCREG); | |
3934 | ||
3935 | // get the address | |
259dbd60 | 3936 | ar = cinfo[i].addr; |
3937 | assert(ar >= 0); | |
630b122b | 3938 | if (dops[i].opcode==0x3a) { // SWC2 |
259dbd60 | 3939 | reglist |= 1<<ar; |
b9b61529 | 3940 | } |
cb13640b | 3941 | if (s >= 0) { |
3942 | c = (i_regs->isconst >> s) & 1; | |
3943 | if (c) { | |
3944 | addr_const = constmap[i][s] + offset; | |
3945 | memtarget = ((signed int)addr_const) < (signed int)(0x80000000 + RAM_SIZE); | |
3946 | } | |
3947 | } | |
b9b61529 | 3948 | |
630b122b | 3949 | cop2_do_stall_check(0, i, i_regs, reglist); |
3950 | ||
3951 | if (dops[i].opcode==0x3a) { // SWC2 | |
3952 | cop2_get_dreg(copr,tl,-1); | |
1fd1aceb | 3953 | type=STOREW_STUB; |
b9b61529 | 3954 | } |
1fd1aceb | 3955 | else |
b9b61529 | 3956 | type=LOADW_STUB; |
1fd1aceb | 3957 | |
3958 | if(c&&!memtarget) { | |
630b122b | 3959 | jaddr2=out; |
1fd1aceb | 3960 | emit_jmp(0); // inline_readstub/inline_writestub? |
b9b61529 | 3961 | } |
1fd1aceb | 3962 | else { |
3963 | if(!c) { | |
630b122b | 3964 | jaddr2 = emit_fastpath_cmp_jump(i, i_regs, ar, |
259dbd60 | 3965 | &offset_reg, &fastio_reg_override, ccadj_); |
630b122b | 3966 | } |
3967 | else if (ram_offset && memtarget) { | |
3968 | offset_reg = get_ro_reg(i_regs, 0); | |
3969 | } | |
3970 | switch (dops[i].opcode) { | |
3971 | case 0x32: { // LWC2 | |
3972 | int a = ar; | |
3973 | if (fastio_reg_override >= 0) | |
3974 | a = fastio_reg_override; | |
3975 | do_load_word(a, tl, offset_reg); | |
3976 | break; | |
1fd1aceb | 3977 | } |
630b122b | 3978 | case 0x3a: { // SWC2 |
1fd1aceb | 3979 | #ifdef DESTRUCTIVE_SHIFT |
3980 | if(!offset&&!c&&s>=0) emit_mov(s,ar); | |
3981 | #endif | |
630b122b | 3982 | int a = ar; |
3983 | if (fastio_reg_override >= 0) | |
3984 | a = fastio_reg_override; | |
3985 | do_store_word(a, 0, tl, offset_reg, 1); | |
3986 | break; | |
3987 | } | |
3988 | default: | |
3989 | assert(0); | |
1fd1aceb | 3990 | } |
b9b61529 | 3991 | } |
630b122b | 3992 | if (fastio_reg_override == HOST_TEMPREG || offset_reg == HOST_TEMPREG) |
3993 | host_tempreg_release(); | |
b9b61529 | 3994 | if(jaddr2) |
630b122b | 3995 | add_stub_r(type,jaddr2,out,i,ar,i_regs,ccadj_,reglist); |
cb13640b | 3996 | if (dops[i].opcode == 0x3a && (!c || is_ram_addr(addr_const))) // SWC2 |
bdbf4466 | 3997 | do_store_smc_check(i, i_regs, reglist, ar); |
cb13640b | 3998 | if (dops[i].opcode == 0x32) { // LWC2 |
630b122b | 3999 | host_tempreg_acquire(); |
4000 | cop2_put_dreg(copr,tl,HOST_TEMPREG); | |
4001 | host_tempreg_release(); | |
4002 | } | |
4003 | } | |
4004 | ||
4005 | static void cop2_assemble(int i, const struct regstat *i_regs) | |
4006 | { | |
4007 | u_int copr = (source[i]>>11) & 0x1f; | |
91af94f0 | 4008 | signed char temp = get_reg_temp(i_regs->regmap); |
630b122b | 4009 | |
4010 | if (!HACK_ENABLED(NDHACK_NO_STALLS)) { | |
4011 | u_int reglist = reglist_exclude(get_host_reglist(i_regs->regmap), temp, -1); | |
4012 | if (dops[i].opcode2 == 0 || dops[i].opcode2 == 2) { // MFC2/CFC2 | |
4013 | signed char tl = get_reg(i_regs->regmap, dops[i].rt1); | |
4014 | reglist = reglist_exclude(reglist, tl, -1); | |
4015 | } | |
4016 | cop2_do_stall_check(0, i, i_regs, reglist); | |
4017 | } | |
4018 | if (dops[i].opcode2==0) { // MFC2 | |
f2e25348 | 4019 | signed char tl=get_reg_w(i_regs->regmap, dops[i].rt1); |
630b122b | 4020 | if(tl>=0&&dops[i].rt1!=0) |
4021 | cop2_get_dreg(copr,tl,temp); | |
4022 | } | |
4023 | else if (dops[i].opcode2==4) { // MTC2 | |
4024 | signed char sl=get_reg(i_regs->regmap,dops[i].rs1); | |
4025 | cop2_put_dreg(copr,sl,temp); | |
4026 | } | |
4027 | else if (dops[i].opcode2==2) // CFC2 | |
4028 | { | |
f2e25348 | 4029 | signed char tl=get_reg_w(i_regs->regmap, dops[i].rt1); |
630b122b | 4030 | if(tl>=0&&dops[i].rt1!=0) |
4031 | emit_readword(®_cop2c[copr],tl); | |
b9b61529 | 4032 | } |
630b122b | 4033 | else if (dops[i].opcode2==6) // CTC2 |
4034 | { | |
4035 | signed char sl=get_reg(i_regs->regmap,dops[i].rs1); | |
4036 | switch(copr) { | |
4037 | case 4: | |
4038 | case 12: | |
4039 | case 20: | |
4040 | case 26: | |
4041 | case 27: | |
4042 | case 29: | |
4043 | case 30: | |
4044 | emit_signextend16(sl,temp); | |
4045 | break; | |
4046 | case 31: | |
4047 | c2op_ctc2_31_assemble(sl,temp); | |
4048 | break; | |
4049 | default: | |
4050 | temp=sl; | |
4051 | break; | |
4052 | } | |
4053 | emit_writeword(temp,®_cop2c[copr]); | |
4054 | assert(sl>=0); | |
4055 | } | |
4056 | } | |
4057 | ||
4058 | static void do_unalignedwritestub(int n) | |
4059 | { | |
4060 | assem_debug("do_unalignedwritestub %x\n",start+stubs[n].a*4); | |
4061 | literal_pool(256); | |
4062 | set_jump_target(stubs[n].addr, out); | |
4063 | ||
4064 | int i=stubs[n].a; | |
4065 | struct regstat *i_regs=(struct regstat *)stubs[n].c; | |
4066 | int addr=stubs[n].b; | |
4067 | u_int reglist=stubs[n].e; | |
4068 | signed char *i_regmap=i_regs->regmap; | |
4069 | int temp2=get_reg(i_regmap,FTEMP); | |
4070 | int rt; | |
4071 | rt=get_reg(i_regmap,dops[i].rs2); | |
4072 | assert(rt>=0); | |
4073 | assert(addr>=0); | |
4074 | assert(dops[i].opcode==0x2a||dops[i].opcode==0x2e); // SWL/SWR only implemented | |
4075 | reglist|=(1<<addr); | |
4076 | reglist&=~(1<<temp2); | |
4077 | ||
4078 | // don't bother with it and call write handler | |
4079 | save_regs(reglist); | |
4080 | pass_args(addr,rt); | |
4081 | int cc=get_reg(i_regmap,CCREG); | |
4082 | if(cc<0) | |
4083 | emit_loadreg(CCREG,2); | |
4084 | emit_addimm(cc<0?2:cc,(int)stubs[n].d+1,2); | |
5753f874 | 4085 | emit_movimm(start + i*4,3); |
4086 | emit_writeword(3,&psxRegs.pc); | |
630b122b | 4087 | emit_far_call((dops[i].opcode==0x2a?jump_handle_swl:jump_handle_swr)); |
4088 | emit_addimm(0,-((int)stubs[n].d+1),cc<0?2:cc); | |
4089 | if(cc<0) | |
4090 | emit_storereg(CCREG,2); | |
4091 | restore_regs(reglist); | |
4092 | emit_jmp(stubs[n].retaddr); // return address | |
b9b61529 | 4093 | } |
4094 | ||
f2e25348 | 4095 | static void do_overflowstub(int n) |
4096 | { | |
4097 | assem_debug("do_overflowstub %x\n", start + (u_int)stubs[n].a * 4); | |
4098 | literal_pool(24); | |
4099 | int i = stubs[n].a; | |
4100 | struct regstat *i_regs = (struct regstat *)stubs[n].c; | |
4101 | int ccadj = stubs[n].d; | |
4102 | set_jump_target(stubs[n].addr, out); | |
4103 | wb_dirtys(regs[i].regmap, regs[i].dirty); | |
4104 | exception_assemble(i, i_regs, ccadj); | |
4105 | } | |
4106 | ||
259dbd60 | 4107 | static void do_alignmentstub(int n) |
4108 | { | |
4109 | assem_debug("do_alignmentstub %x\n", start + (u_int)stubs[n].a * 4); | |
4110 | literal_pool(24); | |
4111 | int i = stubs[n].a; | |
4112 | struct regstat *i_regs = (struct regstat *)stubs[n].c; | |
4113 | int ccadj = stubs[n].d; | |
4114 | int is_store = dops[i].itype == STORE || dops[i].opcode == 0x3A; // SWC2 | |
4115 | int cause = (dops[i].opcode & 3) << 28; | |
4116 | cause |= is_store ? (R3000E_AdES << 2) : (R3000E_AdEL << 2); | |
4117 | set_jump_target(stubs[n].addr, out); | |
4118 | wb_dirtys(regs[i].regmap, regs[i].dirty); | |
4119 | if (stubs[n].b != 1) | |
4120 | emit_mov(stubs[n].b, 1); // faulting address | |
4121 | emit_movimm(cause, 0); | |
4122 | exception_assemble(i, i_regs, ccadj); | |
4123 | } | |
4124 | ||
57871462 | 4125 | #ifndef multdiv_assemble |
4126 | void multdiv_assemble(int i,struct regstat *i_regs) | |
4127 | { | |
4128 | printf("Need multdiv_assemble for this architecture.\n"); | |
630b122b | 4129 | abort(); |
57871462 | 4130 | } |
4131 | #endif | |
4132 | ||
630b122b | 4133 | static void mov_assemble(int i, const struct regstat *i_regs) |
57871462 | 4134 | { |
630b122b | 4135 | //if(dops[i].opcode2==0x10||dops[i].opcode2==0x12) { // MFHI/MFLO |
4136 | //if(dops[i].opcode2==0x11||dops[i].opcode2==0x13) { // MTHI/MTLO | |
4137 | if(dops[i].rt1) { | |
4138 | signed char sl,tl; | |
f2e25348 | 4139 | tl=get_reg_w(i_regs->regmap, dops[i].rt1); |
57871462 | 4140 | //assert(tl>=0); |
4141 | if(tl>=0) { | |
630b122b | 4142 | sl=get_reg(i_regs->regmap,dops[i].rs1); |
57871462 | 4143 | if(sl>=0) emit_mov(sl,tl); |
630b122b | 4144 | else emit_loadreg(dops[i].rs1,tl); |
57871462 | 4145 | } |
4146 | } | |
630b122b | 4147 | if (dops[i].rs1 == HIREG || dops[i].rs1 == LOREG) // MFHI/MFLO |
4148 | multdiv_do_stall(i, i_regs); | |
57871462 | 4149 | } |
4150 | ||
630b122b | 4151 | // call interpreter, exception handler, things that change pc/regs/cycles ... |
4152 | static void call_c_cpu_handler(int i, const struct regstat *i_regs, int ccadj_, u_int pc, void *func) | |
57871462 | 4153 | { |
630b122b | 4154 | signed char ccreg=get_reg(i_regs->regmap,CCREG); |
4155 | assert(ccreg==HOST_CCREG); | |
4156 | assert(!is_delayslot); | |
4157 | (void)ccreg; | |
4158 | ||
4159 | emit_movimm(pc,3); // Get PC | |
4160 | emit_readword(&last_count,2); | |
4161 | emit_writeword(3,&psxRegs.pc); | |
4162 | emit_addimm(HOST_CCREG,ccadj_,HOST_CCREG); | |
4163 | emit_add(2,HOST_CCREG,2); | |
4164 | emit_writeword(2,&psxRegs.cycle); | |
6d79a06f | 4165 | emit_addimm_ptr(FP,(u_char *)&psxRegs - (u_char *)&dynarec_local,0); |
630b122b | 4166 | emit_far_call(func); |
4167 | emit_far_jump(jump_to_new_pc); | |
57871462 | 4168 | } |
57871462 | 4169 | |
f2e25348 | 4170 | static void exception_assemble(int i, const struct regstat *i_regs, int ccadj_) |
57871462 | 4171 | { |
467357cc | 4172 | // 'break' tends to be littered around to catch things like |
4173 | // division by 0 and is almost never executed, so don't emit much code here | |
f2e25348 | 4174 | void *func; |
4175 | if (dops[i].itype == ALU || dops[i].itype == IMM16) | |
4176 | func = is_delayslot ? jump_overflow_ds : jump_overflow; | |
259dbd60 | 4177 | else if (dops[i].itype == LOAD || dops[i].itype == STORE) |
4178 | func = is_delayslot ? jump_addrerror_ds : jump_addrerror; | |
f2e25348 | 4179 | else if (dops[i].opcode2 == 0x0C) |
4180 | func = is_delayslot ? jump_syscall_ds : jump_syscall; | |
4181 | else | |
4182 | func = is_delayslot ? jump_break_ds : jump_break; | |
259dbd60 | 4183 | if (get_reg(i_regs->regmap, CCREG) != HOST_CCREG) // evicted |
4184 | emit_loadreg(CCREG, HOST_CCREG); | |
467357cc | 4185 | emit_movimm(start + i*4, 2); // pc |
4186 | emit_addimm(HOST_CCREG, ccadj_ + CLOCK_ADJUST(1), HOST_CCREG); | |
4187 | emit_far_jump(func); | |
57871462 | 4188 | } |
57871462 | 4189 | |
6d79a06f | 4190 | static void hlecall_bad() |
4191 | { | |
f2e25348 | 4192 | assert(0); |
6d79a06f | 4193 | } |
4194 | ||
630b122b | 4195 | static void hlecall_assemble(int i, const struct regstat *i_regs, int ccadj_) |
57871462 | 4196 | { |
6d79a06f | 4197 | void *hlefunc = hlecall_bad; |
630b122b | 4198 | uint32_t hleCode = source[i] & 0x03ffffff; |
4199 | if (hleCode < ARRAY_SIZE(psxHLEt)) | |
4200 | hlefunc = psxHLEt[hleCode]; | |
4201 | ||
4202 | call_c_cpu_handler(i, i_regs, ccadj_, start + i*4+4, hlefunc); | |
7139f3c8 | 4203 | } |
4204 | ||
630b122b | 4205 | static void intcall_assemble(int i, const struct regstat *i_regs, int ccadj_) |
7139f3c8 | 4206 | { |
630b122b | 4207 | call_c_cpu_handler(i, i_regs, ccadj_, start + i*4, execI); |
57871462 | 4208 | } |
4209 | ||
630b122b | 4210 | static void speculate_mov(int rs,int rt) |
1e973cb0 | 4211 | { |
630b122b | 4212 | if(rt!=0) { |
4213 | smrv_strong_next|=1<<rt; | |
4214 | smrv[rt]=smrv[rs]; | |
4215 | } | |
1e973cb0 | 4216 | } |
4217 | ||
630b122b | 4218 | static void speculate_mov_weak(int rs,int rt) |
57871462 | 4219 | { |
630b122b | 4220 | if(rt!=0) { |
4221 | smrv_weak_next|=1<<rt; | |
4222 | smrv[rt]=smrv[rs]; | |
4223 | } | |
4224 | } | |
4225 | ||
4226 | static void speculate_register_values(int i) | |
4227 | { | |
4228 | if(i==0) { | |
4229 | memcpy(smrv,psxRegs.GPR.r,sizeof(smrv)); | |
4230 | // gp,sp are likely to stay the same throughout the block | |
4231 | smrv_strong_next=(1<<28)|(1<<29)|(1<<30); | |
4232 | smrv_weak_next=~smrv_strong_next; | |
4233 | //printf(" llr %08x\n", smrv[4]); | |
4234 | } | |
4235 | smrv_strong=smrv_strong_next; | |
4236 | smrv_weak=smrv_weak_next; | |
4237 | switch(dops[i].itype) { | |
4238 | case ALU: | |
4239 | if ((smrv_strong>>dops[i].rs1)&1) speculate_mov(dops[i].rs1,dops[i].rt1); | |
4240 | else if((smrv_strong>>dops[i].rs2)&1) speculate_mov(dops[i].rs2,dops[i].rt1); | |
4241 | else if((smrv_weak>>dops[i].rs1)&1) speculate_mov_weak(dops[i].rs1,dops[i].rt1); | |
4242 | else if((smrv_weak>>dops[i].rs2)&1) speculate_mov_weak(dops[i].rs2,dops[i].rt1); | |
4243 | else { | |
4244 | smrv_strong_next&=~(1<<dops[i].rt1); | |
4245 | smrv_weak_next&=~(1<<dops[i].rt1); | |
4246 | } | |
4247 | break; | |
4248 | case SHIFTIMM: | |
4249 | smrv_strong_next&=~(1<<dops[i].rt1); | |
4250 | smrv_weak_next&=~(1<<dops[i].rt1); | |
4251 | // fallthrough | |
4252 | case IMM16: | |
4253 | if(dops[i].rt1&&is_const(®s[i],dops[i].rt1)) { | |
5753f874 | 4254 | int hr = get_reg_w(regs[i].regmap, dops[i].rt1); |
4255 | u_int value; | |
630b122b | 4256 | if(hr>=0) { |
4257 | if(get_final_value(hr,i,&value)) | |
4258 | smrv[dops[i].rt1]=value; | |
4259 | else smrv[dops[i].rt1]=constmap[i][hr]; | |
4260 | smrv_strong_next|=1<<dops[i].rt1; | |
4261 | } | |
4262 | } | |
4263 | else { | |
4264 | if ((smrv_strong>>dops[i].rs1)&1) speculate_mov(dops[i].rs1,dops[i].rt1); | |
4265 | else if((smrv_weak>>dops[i].rs1)&1) speculate_mov_weak(dops[i].rs1,dops[i].rt1); | |
4266 | } | |
4267 | break; | |
4268 | case LOAD: | |
4269 | if(start<0x2000&&(dops[i].rt1==26||(smrv[dops[i].rt1]>>24)==0xa0)) { | |
4270 | // special case for BIOS | |
4271 | smrv[dops[i].rt1]=0xa0000000; | |
4272 | smrv_strong_next|=1<<dops[i].rt1; | |
4273 | break; | |
4274 | } | |
4275 | // fallthrough | |
4276 | case SHIFT: | |
4277 | case LOADLR: | |
4278 | case MOV: | |
4279 | smrv_strong_next&=~(1<<dops[i].rt1); | |
4280 | smrv_weak_next&=~(1<<dops[i].rt1); | |
4281 | break; | |
4282 | case COP0: | |
4283 | case COP2: | |
4284 | if(dops[i].opcode2==0||dops[i].opcode2==2) { // MFC/CFC | |
4285 | smrv_strong_next&=~(1<<dops[i].rt1); | |
4286 | smrv_weak_next&=~(1<<dops[i].rt1); | |
4287 | } | |
4288 | break; | |
4289 | case C2LS: | |
4290 | if (dops[i].opcode==0x32) { // LWC2 | |
4291 | smrv_strong_next&=~(1<<dops[i].rt1); | |
4292 | smrv_weak_next&=~(1<<dops[i].rt1); | |
4293 | } | |
4294 | break; | |
4295 | } | |
4296 | #if 0 | |
4297 | int r=4; | |
4298 | printf("x %08x %08x %d %d c %08x %08x\n",smrv[r],start+i*4, | |
4299 | ((smrv_strong>>r)&1),(smrv_weak>>r)&1,regs[i].isconst,regs[i].wasconst); | |
4300 | #endif | |
4301 | } | |
4302 | ||
4303 | static void ujump_assemble(int i, const struct regstat *i_regs); | |
4304 | static void rjump_assemble(int i, const struct regstat *i_regs); | |
4305 | static void cjump_assemble(int i, const struct regstat *i_regs); | |
4306 | static void sjump_assemble(int i, const struct regstat *i_regs); | |
630b122b | 4307 | |
4308 | static int assemble(int i, const struct regstat *i_regs, int ccadj_) | |
4309 | { | |
4310 | int ds = 0; | |
4311 | switch (dops[i].itype) { | |
57871462 | 4312 | case ALU: |
f2e25348 | 4313 | alu_assemble(i, i_regs, ccadj_); |
630b122b | 4314 | break; |
57871462 | 4315 | case IMM16: |
f2e25348 | 4316 | imm16_assemble(i, i_regs, ccadj_); |
630b122b | 4317 | break; |
57871462 | 4318 | case SHIFT: |
630b122b | 4319 | shift_assemble(i, i_regs); |
4320 | break; | |
57871462 | 4321 | case SHIFTIMM: |
630b122b | 4322 | shiftimm_assemble(i, i_regs); |
4323 | break; | |
57871462 | 4324 | case LOAD: |
630b122b | 4325 | load_assemble(i, i_regs, ccadj_); |
4326 | break; | |
57871462 | 4327 | case LOADLR: |
630b122b | 4328 | loadlr_assemble(i, i_regs, ccadj_); |
4329 | break; | |
57871462 | 4330 | case STORE: |
630b122b | 4331 | store_assemble(i, i_regs, ccadj_); |
4332 | break; | |
57871462 | 4333 | case STORELR: |
630b122b | 4334 | storelr_assemble(i, i_regs, ccadj_); |
4335 | break; | |
57871462 | 4336 | case COP0: |
630b122b | 4337 | cop0_assemble(i, i_regs, ccadj_); |
4338 | break; | |
f2e25348 | 4339 | case RFE: |
259dbd60 | 4340 | rfe_assemble(i, i_regs); |
630b122b | 4341 | break; |
b9b61529 | 4342 | case COP2: |
630b122b | 4343 | cop2_assemble(i, i_regs); |
4344 | break; | |
b9b61529 | 4345 | case C2LS: |
630b122b | 4346 | c2ls_assemble(i, i_regs, ccadj_); |
4347 | break; | |
b9b61529 | 4348 | case C2OP: |
630b122b | 4349 | c2op_assemble(i, i_regs); |
4350 | break; | |
57871462 | 4351 | case MULTDIV: |
630b122b | 4352 | multdiv_assemble(i, i_regs); |
4353 | multdiv_prepare_stall(i, i_regs, ccadj_); | |
4354 | break; | |
57871462 | 4355 | case MOV: |
630b122b | 4356 | mov_assemble(i, i_regs); |
4357 | break; | |
4358 | case SYSCALL: | |
f2e25348 | 4359 | exception_assemble(i, i_regs, ccadj_); |
630b122b | 4360 | break; |
4361 | case HLECALL: | |
4362 | hlecall_assemble(i, i_regs, ccadj_); | |
4363 | break; | |
4364 | case INTCALL: | |
4365 | intcall_assemble(i, i_regs, ccadj_); | |
4366 | break; | |
4367 | case UJUMP: | |
4368 | ujump_assemble(i, i_regs); | |
4369 | ds = 1; | |
4370 | break; | |
4371 | case RJUMP: | |
4372 | rjump_assemble(i, i_regs); | |
4373 | ds = 1; | |
4374 | break; | |
4375 | case CJUMP: | |
4376 | cjump_assemble(i, i_regs); | |
4377 | ds = 1; | |
4378 | break; | |
4379 | case SJUMP: | |
4380 | sjump_assemble(i, i_regs); | |
4381 | ds = 1; | |
4382 | break; | |
630b122b | 4383 | case NOP: |
4384 | case OTHER: | |
630b122b | 4385 | // not handled, just skip |
4386 | break; | |
4387 | default: | |
4388 | assert(0); | |
4389 | } | |
4390 | return ds; | |
4391 | } | |
4392 | ||
4393 | static void ds_assemble(int i, const struct regstat *i_regs) | |
4394 | { | |
4395 | speculate_register_values(i); | |
4396 | is_delayslot = 1; | |
4397 | switch (dops[i].itype) { | |
57871462 | 4398 | case SYSCALL: |
7139f3c8 | 4399 | case HLECALL: |
1e973cb0 | 4400 | case INTCALL: |
57871462 | 4401 | case UJUMP: |
4402 | case RJUMP: | |
4403 | case CJUMP: | |
4404 | case SJUMP: | |
c43b5311 | 4405 | SysPrintf("Jump in the delay slot. This is probably a bug.\n"); |
630b122b | 4406 | break; |
4407 | default: | |
259dbd60 | 4408 | assemble(i, i_regs, cinfo[i].ccadj); |
57871462 | 4409 | } |
630b122b | 4410 | is_delayslot = 0; |
57871462 | 4411 | } |
4412 | ||
4413 | // Is the branch target a valid internal jump? | |
630b122b | 4414 | static int internal_branch(int addr) |
57871462 | 4415 | { |
4416 | if(addr&1) return 0; // Indirect (register) jump | |
4417 | if(addr>=start && addr<start+slen*4-4) | |
4418 | { | |
71e490c5 | 4419 | return 1; |
57871462 | 4420 | } |
4421 | return 0; | |
4422 | } | |
4423 | ||
630b122b | 4424 | static void wb_invalidate(signed char pre[],signed char entry[],uint64_t dirty,uint64_t u) |
57871462 | 4425 | { |
4426 | int hr; | |
4427 | for(hr=0;hr<HOST_REGS;hr++) { | |
4428 | if(hr!=EXCLUDE_REG) { | |
4429 | if(pre[hr]!=entry[hr]) { | |
4430 | if(pre[hr]>=0) { | |
4431 | if((dirty>>hr)&1) { | |
4432 | if(get_reg(entry,pre[hr])<0) { | |
630b122b | 4433 | assert(pre[hr]<64); |
4434 | if(!((u>>pre[hr])&1)) | |
4435 | emit_storereg(pre[hr],hr); | |
57871462 | 4436 | } |
4437 | } | |
4438 | } | |
4439 | } | |
4440 | } | |
4441 | } | |
4442 | // Move from one register to another (no writeback) | |
4443 | for(hr=0;hr<HOST_REGS;hr++) { | |
4444 | if(hr!=EXCLUDE_REG) { | |
4445 | if(pre[hr]!=entry[hr]) { | |
91af94f0 | 4446 | if(pre[hr]>=0&&pre[hr]<TEMPREG) { |
57871462 | 4447 | int nr; |
4448 | if((nr=get_reg(entry,pre[hr]))>=0) { | |
4449 | emit_mov(hr,nr); | |
4450 | } | |
4451 | } | |
4452 | } | |
4453 | } | |
4454 | } | |
4455 | } | |
57871462 | 4456 | |
4457 | // Load the specified registers | |
4458 | // This only loads the registers given as arguments because | |
4459 | // we don't want to load things that will be overwritten | |
e912c27d | 4460 | static inline void load_reg(signed char entry[], signed char regmap[], int rs) |
57871462 | 4461 | { |
e912c27d | 4462 | int hr = get_reg(regmap, rs); |
4463 | if (hr >= 0 && entry[hr] != regmap[hr]) | |
4464 | emit_loadreg(regmap[hr], hr); | |
4465 | } | |
4466 | ||
4467 | static void load_regs(signed char entry[], signed char regmap[], int rs1, int rs2) | |
4468 | { | |
4469 | load_reg(entry, regmap, rs1); | |
4470 | if (rs1 != rs2) | |
4471 | load_reg(entry, regmap, rs2); | |
57871462 | 4472 | } |
4473 | ||
4474 | // Load registers prior to the start of a loop | |
4475 | // so that they are not loaded within the loop | |
4476 | static void loop_preload(signed char pre[],signed char entry[]) | |
4477 | { | |
4478 | int hr; | |
e912c27d | 4479 | for (hr = 0; hr < HOST_REGS; hr++) { |
4480 | int r = entry[hr]; | |
4481 | if (r >= 0 && pre[hr] != r && get_reg(pre, r) < 0) { | |
4482 | assem_debug("loop preload:\n"); | |
4483 | if (r < TEMPREG) | |
4484 | emit_loadreg(r, hr); | |
57871462 | 4485 | } |
4486 | } | |
4487 | } | |
4488 | ||
4489 | // Generate address for load/store instruction | |
259dbd60 | 4490 | // goes to AGEN (or temp) for writes, FTEMP for LOADLR and cop1/2 loads |
4491 | // AGEN is assigned by pass5b_preallocate2 | |
94061aa5 | 4492 | static void address_generation(int i, const struct regstat *i_regs, signed char entry[]) |
57871462 | 4493 | { |
630b122b | 4494 | if (dops[i].is_load || dops[i].is_store) { |
259dbd60 | 4495 | int ra = -1; |
4496 | int agr = AGEN1 + (i&1); | |
630b122b | 4497 | if(dops[i].itype==LOAD) { |
259dbd60 | 4498 | if (!dops[i].may_except) |
4499 | ra = get_reg_w(i_regs->regmap, dops[i].rt1); // reuse dest for agen | |
4500 | if (ra < 0) | |
4501 | ra = get_reg_temp(i_regs->regmap); | |
57871462 | 4502 | } |
630b122b | 4503 | if(dops[i].itype==LOADLR) { |
57871462 | 4504 | ra=get_reg(i_regs->regmap,FTEMP); |
4505 | } | |
630b122b | 4506 | if(dops[i].itype==STORE||dops[i].itype==STORELR) { |
57871462 | 4507 | ra=get_reg(i_regs->regmap,agr); |
91af94f0 | 4508 | if(ra<0) ra=get_reg_temp(i_regs->regmap); |
57871462 | 4509 | } |
630b122b | 4510 | if(dops[i].itype==C2LS) { |
259dbd60 | 4511 | if (dops[i].opcode == 0x32) // LWC2 |
57871462 | 4512 | ra=get_reg(i_regs->regmap,FTEMP); |
259dbd60 | 4513 | else { // SWC2 |
57871462 | 4514 | ra=get_reg(i_regs->regmap,agr); |
91af94f0 | 4515 | if(ra<0) ra=get_reg_temp(i_regs->regmap); |
57871462 | 4516 | } |
4517 | } | |
259dbd60 | 4518 | int rs = get_reg(i_regs->regmap, dops[i].rs1); |
4519 | //if(ra>=0) | |
4520 | { | |
4521 | int offset = cinfo[i].imm; | |
4522 | int add_offset = offset != 0; | |
e6e590d3 | 4523 | int c = rs >= 0 && ((i_regs->wasconst >> rs) & 1); |
630b122b | 4524 | if(dops[i].rs1==0) { |
57871462 | 4525 | // Using r0 as a base address |
259dbd60 | 4526 | assert(ra >= 0); |
57871462 | 4527 | if(!entry||entry[ra]!=agr) { |
630b122b | 4528 | if (dops[i].opcode==0x22||dops[i].opcode==0x26) { |
57871462 | 4529 | emit_movimm(offset&0xFFFFFFFC,ra); // LWL/LWR |
57871462 | 4530 | }else{ |
4531 | emit_movimm(offset,ra); | |
4532 | } | |
4533 | } // else did it in the previous cycle | |
259dbd60 | 4534 | cinfo[i].addr = ra; |
4535 | add_offset = 0; | |
4536 | } | |
4537 | else if (rs < 0) { | |
4538 | assert(ra >= 0); | |
4539 | if (!entry || entry[ra] != dops[i].rs1) | |
4540 | emit_loadreg(dops[i].rs1, ra); | |
4541 | cinfo[i].addr = ra; | |
630b122b | 4542 | //if(!entry||entry[ra]!=dops[i].rs1) |
57871462 | 4543 | // printf("poor load scheduling!\n"); |
4544 | } | |
4545 | else if(c) { | |
630b122b | 4546 | if(dops[i].rs1!=dops[i].rt1||dops[i].itype!=LOAD) { |
259dbd60 | 4547 | assert(ra >= 0); |
57871462 | 4548 | if(!entry||entry[ra]!=agr) { |
630b122b | 4549 | if (dops[i].opcode==0x22||dops[i].opcode==0x26) { |
57871462 | 4550 | emit_movimm((constmap[i][rs]+offset)&0xFFFFFFFC,ra); // LWL/LWR |
57871462 | 4551 | }else{ |
57871462 | 4552 | emit_movimm(constmap[i][rs]+offset,ra); |
8575a877 | 4553 | regs[i].loadedconst|=1<<ra; |
57871462 | 4554 | } |
4555 | } // else did it in the previous cycle | |
259dbd60 | 4556 | cinfo[i].addr = ra; |
4557 | } | |
4558 | else // else load_consts already did it | |
4559 | cinfo[i].addr = rs; | |
4560 | add_offset = 0; | |
57871462 | 4561 | } |
259dbd60 | 4562 | else |
4563 | cinfo[i].addr = rs; | |
4564 | if (add_offset) { | |
4565 | assert(ra >= 0); | |
57871462 | 4566 | if(rs>=0) { |
4567 | emit_addimm(rs,offset,ra); | |
4568 | }else{ | |
4569 | emit_addimm(ra,offset,ra); | |
4570 | } | |
259dbd60 | 4571 | cinfo[i].addr = ra; |
57871462 | 4572 | } |
4573 | } | |
259dbd60 | 4574 | assert(cinfo[i].addr >= 0); |
57871462 | 4575 | } |
4576 | // Preload constants for next instruction | |
630b122b | 4577 | if (dops[i+1].is_load || dops[i+1].is_store) { |
57871462 | 4578 | int agr,ra; |
57871462 | 4579 | // Actual address |
4580 | agr=AGEN1+((i+1)&1); | |
4581 | ra=get_reg(i_regs->regmap,agr); | |
4582 | if(ra>=0) { | |
630b122b | 4583 | int rs=get_reg(regs[i+1].regmap,dops[i+1].rs1); |
259dbd60 | 4584 | int offset=cinfo[i+1].imm; |
57871462 | 4585 | int c=(regs[i+1].wasconst>>rs)&1; |
630b122b | 4586 | if(c&&(dops[i+1].rs1!=dops[i+1].rt1||dops[i+1].itype!=LOAD)) { |
4587 | if (dops[i+1].opcode==0x22||dops[i+1].opcode==0x26) { | |
57871462 | 4588 | emit_movimm((constmap[i+1][rs]+offset)&0xFFFFFFFC,ra); // LWL/LWR |
630b122b | 4589 | }else if (dops[i+1].opcode==0x1a||dops[i+1].opcode==0x1b) { |
57871462 | 4590 | emit_movimm((constmap[i+1][rs]+offset)&0xFFFFFFF8,ra); // LDL/LDR |
4591 | }else{ | |
57871462 | 4592 | emit_movimm(constmap[i+1][rs]+offset,ra); |
8575a877 | 4593 | regs[i+1].loadedconst|=1<<ra; |
57871462 | 4594 | } |
4595 | } | |
630b122b | 4596 | else if(dops[i+1].rs1==0) { |
57871462 | 4597 | // Using r0 as a base address |
630b122b | 4598 | if (dops[i+1].opcode==0x22||dops[i+1].opcode==0x26) { |
57871462 | 4599 | emit_movimm(offset&0xFFFFFFFC,ra); // LWL/LWR |
630b122b | 4600 | }else if (dops[i+1].opcode==0x1a||dops[i+1].opcode==0x1b) { |
57871462 | 4601 | emit_movimm(offset&0xFFFFFFF8,ra); // LDL/LDR |
4602 | }else{ | |
4603 | emit_movimm(offset,ra); | |
4604 | } | |
4605 | } | |
4606 | } | |
4607 | } | |
4608 | } | |
4609 | ||
5753f874 | 4610 | static int get_final_value(int hr, int i, u_int *value) |
57871462 | 4611 | { |
4612 | int reg=regs[i].regmap[hr]; | |
4613 | while(i<slen-1) { | |
4614 | if(regs[i+1].regmap[hr]!=reg) break; | |
4615 | if(!((regs[i+1].isconst>>hr)&1)) break; | |
630b122b | 4616 | if(dops[i+1].bt) break; |
57871462 | 4617 | i++; |
4618 | } | |
4619 | if(i<slen-1) { | |
630b122b | 4620 | if (dops[i].is_jump) { |
57871462 | 4621 | *value=constmap[i][hr]; |
4622 | return 1; | |
4623 | } | |
630b122b | 4624 | if(!dops[i+1].bt) { |
4625 | if (dops[i+1].is_jump) { | |
57871462 | 4626 | // Load in delay slot, out-of-order execution |
630b122b | 4627 | if(dops[i+2].itype==LOAD&&dops[i+2].rs1==reg&&dops[i+2].rt1==reg&&((regs[i+1].wasconst>>hr)&1)) |
57871462 | 4628 | { |
57871462 | 4629 | // Precompute load address |
259dbd60 | 4630 | *value=constmap[i][hr]+cinfo[i+2].imm; |
57871462 | 4631 | return 1; |
4632 | } | |
4633 | } | |
630b122b | 4634 | if(dops[i+1].itype==LOAD&&dops[i+1].rs1==reg&&dops[i+1].rt1==reg) |
57871462 | 4635 | { |
57871462 | 4636 | // Precompute load address |
259dbd60 | 4637 | *value=constmap[i][hr]+cinfo[i+1].imm; |
4638 | //printf("c=%x imm=%lx\n",(long)constmap[i][hr],cinfo[i+1].imm); | |
57871462 | 4639 | return 1; |
4640 | } | |
4641 | } | |
4642 | } | |
4643 | *value=constmap[i][hr]; | |
630b122b | 4644 | //printf("c=%lx\n",(long)constmap[i][hr]); |
57871462 | 4645 | if(i==slen-1) return 1; |
630b122b | 4646 | assert(reg < 64); |
4647 | return !((unneeded_reg[i+1]>>reg)&1); | |
57871462 | 4648 | } |
4649 | ||
4650 | // Load registers with known constants | |
630b122b | 4651 | static void load_consts(signed char pre[],signed char regmap[],int i) |
57871462 | 4652 | { |
8575a877 | 4653 | int hr,hr2; |
4654 | // propagate loaded constant flags | |
630b122b | 4655 | if(i==0||dops[i].bt) |
8575a877 | 4656 | regs[i].loadedconst=0; |
4657 | else { | |
cb13640b | 4658 | for (hr = 0; hr < HOST_REGS; hr++) { |
4659 | if (hr == EXCLUDE_REG || regmap[hr] < 0 || pre[hr] != regmap[hr]) | |
4660 | continue; | |
4661 | if ((((regs[i-1].isconst & regs[i-1].loadedconst) >> hr) & 1) | |
4662 | && regmap[hr] == regs[i-1].regmap[hr]) | |
8575a877 | 4663 | { |
cb13640b | 4664 | regs[i].loadedconst |= 1u << hr; |
8575a877 | 4665 | } |
4666 | } | |
4667 | } | |
57871462 | 4668 | // Load 32-bit regs |
4669 | for(hr=0;hr<HOST_REGS;hr++) { | |
4670 | if(hr!=EXCLUDE_REG&®map[hr]>=0) { | |
4671 | //if(entry[hr]!=regmap[hr]) { | |
8575a877 | 4672 | if(!((regs[i].loadedconst>>hr)&1)) { |
630b122b | 4673 | assert(regmap[hr]<64); |
4674 | if(((regs[i].isconst>>hr)&1)&®map[hr]>0) { | |
5753f874 | 4675 | u_int value, similar=0; |
57871462 | 4676 | if(get_final_value(hr,i,&value)) { |
8575a877 | 4677 | // see if some other register has similar value |
4678 | for(hr2=0;hr2<HOST_REGS;hr2++) { | |
4679 | if(hr2!=EXCLUDE_REG&&((regs[i].loadedconst>>hr2)&1)) { | |
4680 | if(is_similar_value(value,constmap[i][hr2])) { | |
4681 | similar=1; | |
4682 | break; | |
4683 | } | |
4684 | } | |
4685 | } | |
4686 | if(similar) { | |
5753f874 | 4687 | u_int value2; |
8575a877 | 4688 | if(get_final_value(hr2,i,&value2)) // is this needed? |
4689 | emit_movimm_from(value2,hr2,value,hr); | |
4690 | else | |
4691 | emit_movimm(value,hr); | |
4692 | } | |
4693 | else if(value==0) { | |
57871462 | 4694 | emit_zeroreg(hr); |
4695 | } | |
4696 | else { | |
4697 | emit_movimm(value,hr); | |
4698 | } | |
4699 | } | |
8575a877 | 4700 | regs[i].loadedconst|=1<<hr; |
57871462 | 4701 | } |
4702 | } | |
4703 | } | |
4704 | } | |
57871462 | 4705 | } |
630b122b | 4706 | |
4707 | static void load_all_consts(const signed char regmap[], u_int dirty, int i) | |
57871462 | 4708 | { |
4709 | int hr; | |
4710 | // Load 32-bit regs | |
4711 | for(hr=0;hr<HOST_REGS;hr++) { | |
4712 | if(hr!=EXCLUDE_REG&®map[hr]>=0&&((dirty>>hr)&1)) { | |
630b122b | 4713 | assert(regmap[hr] < 64); |
4714 | if(((regs[i].isconst>>hr)&1)&®map[hr]>0) { | |
57871462 | 4715 | int value=constmap[i][hr]; |
4716 | if(value==0) { | |
4717 | emit_zeroreg(hr); | |
4718 | } | |
4719 | else { | |
4720 | emit_movimm(value,hr); | |
4721 | } | |
4722 | } | |
4723 | } | |
4724 | } | |
57871462 | 4725 | } |
4726 | ||
4727 | // Write out all dirty registers (except cycle count) | |
a3c5fc39 | 4728 | #ifndef wb_dirtys |
4729 | static void wb_dirtys(const signed char i_regmap[], u_int i_dirty) | |
57871462 | 4730 | { |
4731 | int hr; | |
4732 | for(hr=0;hr<HOST_REGS;hr++) { | |
4733 | if(hr!=EXCLUDE_REG) { | |
4734 | if(i_regmap[hr]>0) { | |
4735 | if(i_regmap[hr]!=CCREG) { | |
4736 | if((i_dirty>>hr)&1) { | |
630b122b | 4737 | assert(i_regmap[hr]<64); |
4738 | emit_storereg(i_regmap[hr],hr); | |
57871462 | 4739 | } |
4740 | } | |
4741 | } | |
4742 | } | |
4743 | } | |
4744 | } | |
a3c5fc39 | 4745 | #endif |
630b122b | 4746 | |
57871462 | 4747 | // Write out dirty registers that we need to reload (pair with load_needed_regs) |
4748 | // This writes the registers not written by store_regs_bt | |
a3c5fc39 | 4749 | static void wb_needed_dirtys(const signed char i_regmap[], u_int i_dirty, int addr) |
57871462 | 4750 | { |
4751 | int hr; | |
4752 | int t=(addr-start)>>2; | |
4753 | for(hr=0;hr<HOST_REGS;hr++) { | |
4754 | if(hr!=EXCLUDE_REG) { | |
4755 | if(i_regmap[hr]>0) { | |
4756 | if(i_regmap[hr]!=CCREG) { | |
630b122b | 4757 | if(i_regmap[hr]==regs[t].regmap_entry[hr] && ((regs[t].dirty>>hr)&1)) { |
57871462 | 4758 | if((i_dirty>>hr)&1) { |
630b122b | 4759 | assert(i_regmap[hr]<64); |
4760 | emit_storereg(i_regmap[hr],hr); | |
57871462 | 4761 | } |
4762 | } | |
4763 | } | |
4764 | } | |
4765 | } | |
4766 | } | |
4767 | } | |
4768 | ||
4769 | // Load all registers (except cycle count) | |
a3c5fc39 | 4770 | #ifndef load_all_regs |
630b122b | 4771 | static void load_all_regs(const signed char i_regmap[]) |
57871462 | 4772 | { |
4773 | int hr; | |
4774 | for(hr=0;hr<HOST_REGS;hr++) { | |
4775 | if(hr!=EXCLUDE_REG) { | |
4776 | if(i_regmap[hr]==0) { | |
4777 | emit_zeroreg(hr); | |
4778 | } | |
4779 | else | |
91af94f0 | 4780 | if(i_regmap[hr]>0 && i_regmap[hr]<TEMPREG && i_regmap[hr]!=CCREG) |
57871462 | 4781 | { |
4782 | emit_loadreg(i_regmap[hr],hr); | |
4783 | } | |
4784 | } | |
4785 | } | |
4786 | } | |
a3c5fc39 | 4787 | #endif |
57871462 | 4788 | |
4789 | // Load all current registers also needed by next instruction | |
630b122b | 4790 | static void load_needed_regs(const signed char i_regmap[], const signed char next_regmap[]) |
57871462 | 4791 | { |
a3c5fc39 | 4792 | signed char regmap_sel[HOST_REGS]; |
57871462 | 4793 | int hr; |
a3c5fc39 | 4794 | for (hr = 0; hr < HOST_REGS; hr++) { |
4795 | regmap_sel[hr] = -1; | |
4796 | if (hr != EXCLUDE_REG) | |
4797 | if (next_regmap[hr] == i_regmap[hr] || get_reg(next_regmap, i_regmap[hr]) >= 0) | |
4798 | regmap_sel[hr] = i_regmap[hr]; | |
57871462 | 4799 | } |
a3c5fc39 | 4800 | load_all_regs(regmap_sel); |
57871462 | 4801 | } |
4802 | ||
4803 | // Load all regs, storing cycle count if necessary | |
630b122b | 4804 | static void load_regs_entry(int t) |
57871462 | 4805 | { |
630b122b | 4806 | if(dops[t].is_ds) emit_addimm(HOST_CCREG,CLOCK_ADJUST(1),HOST_CCREG); |
259dbd60 | 4807 | else if(cinfo[t].ccadj) emit_addimm(HOST_CCREG,-cinfo[t].ccadj,HOST_CCREG); |
57871462 | 4808 | if(regs[t].regmap_entry[HOST_CCREG]!=CCREG) { |
4809 | emit_storereg(CCREG,HOST_CCREG); | |
4810 | } | |
a3c5fc39 | 4811 | load_all_regs(regs[t].regmap_entry); |
57871462 | 4812 | } |
4813 | ||
4814 | // Store dirty registers prior to branch | |
94061aa5 | 4815 | static void store_regs_bt(signed char i_regmap[],uint64_t i_dirty,int addr) |
57871462 | 4816 | { |
630b122b | 4817 | if(internal_branch(addr)) |
57871462 | 4818 | { |
4819 | int t=(addr-start)>>2; | |
4820 | int hr; | |
4821 | for(hr=0;hr<HOST_REGS;hr++) { | |
4822 | if(hr!=EXCLUDE_REG) { | |
4823 | if(i_regmap[hr]>0 && i_regmap[hr]!=CCREG) { | |
630b122b | 4824 | if(i_regmap[hr]!=regs[t].regmap_entry[hr] || !((regs[t].dirty>>hr)&1)) { |
57871462 | 4825 | if((i_dirty>>hr)&1) { |
630b122b | 4826 | assert(i_regmap[hr]<64); |
4827 | if(!((unneeded_reg[t]>>i_regmap[hr])&1)) | |
4828 | emit_storereg(i_regmap[hr],hr); | |
57871462 | 4829 | } |
4830 | } | |
4831 | } | |
4832 | } | |
4833 | } | |
4834 | } | |
4835 | else | |
4836 | { | |
4837 | // Branch out of this block, write out all dirty regs | |
630b122b | 4838 | wb_dirtys(i_regmap,i_dirty); |
57871462 | 4839 | } |
4840 | } | |
4841 | ||
4842 | // Load all needed registers for branch target | |
630b122b | 4843 | static void load_regs_bt(signed char i_regmap[],uint64_t i_dirty,int addr) |
57871462 | 4844 | { |
4845 | //if(addr>=start && addr<(start+slen*4)) | |
630b122b | 4846 | if(internal_branch(addr)) |
57871462 | 4847 | { |
4848 | int t=(addr-start)>>2; | |
4849 | int hr; | |
4850 | // Store the cycle count before loading something else | |
4851 | if(i_regmap[HOST_CCREG]!=CCREG) { | |
4852 | assert(i_regmap[HOST_CCREG]==-1); | |
4853 | } | |
4854 | if(regs[t].regmap_entry[HOST_CCREG]!=CCREG) { | |
4855 | emit_storereg(CCREG,HOST_CCREG); | |
4856 | } | |
4857 | // Load 32-bit regs | |
4858 | for(hr=0;hr<HOST_REGS;hr++) { | |
ea3d2e6e | 4859 | if(hr!=EXCLUDE_REG&®s[t].regmap_entry[hr]>=0&®s[t].regmap_entry[hr]<TEMPREG) { |
630b122b | 4860 | if(i_regmap[hr]!=regs[t].regmap_entry[hr]) { |
57871462 | 4861 | if(regs[t].regmap_entry[hr]==0) { |
4862 | emit_zeroreg(hr); | |
4863 | } | |
4864 | else if(regs[t].regmap_entry[hr]!=CCREG) | |
4865 | { | |
4866 | emit_loadreg(regs[t].regmap_entry[hr],hr); | |
4867 | } | |
4868 | } | |
4869 | } | |
4870 | } | |
57871462 | 4871 | } |
4872 | } | |
4873 | ||
630b122b | 4874 | static int match_bt(signed char i_regmap[],uint64_t i_dirty,int addr) |
57871462 | 4875 | { |
4876 | if(addr>=start && addr<start+slen*4-4) | |
4877 | { | |
4878 | int t=(addr-start)>>2; | |
4879 | int hr; | |
4880 | if(regs[t].regmap_entry[HOST_CCREG]!=CCREG) return 0; | |
4881 | for(hr=0;hr<HOST_REGS;hr++) | |
4882 | { | |
4883 | if(hr!=EXCLUDE_REG) | |
4884 | { | |
4885 | if(i_regmap[hr]!=regs[t].regmap_entry[hr]) | |
4886 | { | |
ea3d2e6e | 4887 | if(regs[t].regmap_entry[hr]>=0&&(regs[t].regmap_entry[hr]|64)<TEMPREG+64) |
57871462 | 4888 | { |
4889 | return 0; | |
4890 | } | |
9f51b4b9 | 4891 | else |
57871462 | 4892 | if((i_dirty>>hr)&1) |
4893 | { | |
ea3d2e6e | 4894 | if(i_regmap[hr]<TEMPREG) |
57871462 | 4895 | { |
4896 | if(!((unneeded_reg[t]>>i_regmap[hr])&1)) | |
4897 | return 0; | |
4898 | } | |
ea3d2e6e | 4899 | else if(i_regmap[hr]>=64&&i_regmap[hr]<TEMPREG+64) |
57871462 | 4900 | { |
630b122b | 4901 | assert(0); |
57871462 | 4902 | } |
4903 | } | |
4904 | } | |
4905 | else // Same register but is it 32-bit or dirty? | |
4906 | if(i_regmap[hr]>=0) | |
4907 | { | |
4908 | if(!((regs[t].dirty>>hr)&1)) | |
4909 | { | |
4910 | if((i_dirty>>hr)&1) | |
4911 | { | |
4912 | if(!((unneeded_reg[t]>>i_regmap[hr])&1)) | |
4913 | { | |
4914 | //printf("%x: dirty no match\n",addr); | |
4915 | return 0; | |
4916 | } | |
4917 | } | |
4918 | } | |
57871462 | 4919 | } |
4920 | } | |
4921 | } | |
57871462 | 4922 | // Delay slots are not valid branch targets |
630b122b | 4923 | //if(t>0&&(dops[t-1].is_jump) return 0; |
57871462 | 4924 | // Delay slots require additional processing, so do not match |
630b122b | 4925 | if(dops[t].is_ds) return 0; |
57871462 | 4926 | } |
4927 | else | |
4928 | { | |
4929 | int hr; | |
4930 | for(hr=0;hr<HOST_REGS;hr++) | |
4931 | { | |
4932 | if(hr!=EXCLUDE_REG) | |
4933 | { | |
4934 | if(i_regmap[hr]>=0) | |
4935 | { | |
4936 | if(hr!=HOST_CCREG||i_regmap[hr]!=CCREG) | |
4937 | { | |
4938 | if((i_dirty>>hr)&1) | |
4939 | { | |
4940 | return 0; | |
4941 | } | |
4942 | } | |
4943 | } | |
4944 | } | |
4945 | } | |
4946 | } | |
4947 | return 1; | |
4948 | } | |
4949 | ||
630b122b | 4950 | #ifdef DRC_DBG |
4951 | static void drc_dbg_emit_do_cmp(int i, int ccadj_) | |
57871462 | 4952 | { |
630b122b | 4953 | extern void do_insn_cmp(); |
4954 | //extern int cycle; | |
4955 | u_int hr, reglist = get_host_reglist(regs[i].regmap); | |
e6e590d3 | 4956 | reglist |= get_host_reglist(regs[i].regmap_entry); |
4957 | reglist &= DRC_DBG_REGMASK; | |
630b122b | 4958 | |
4959 | assem_debug("//do_insn_cmp %08x\n", start+i*4); | |
4960 | save_regs(reglist); | |
4961 | // write out changed consts to match the interpreter | |
4962 | if (i > 0 && !dops[i].bt) { | |
4963 | for (hr = 0; hr < HOST_REGS; hr++) { | |
4964 | int reg = regs[i].regmap_entry[hr]; // regs[i-1].regmap[hr]; | |
259dbd60 | 4965 | if (hr == EXCLUDE_REG || reg <= 0) |
630b122b | 4966 | continue; |
4967 | if (!((regs[i-1].isconst >> hr) & 1)) | |
4968 | continue; | |
4969 | if (i > 1 && reg == regs[i-2].regmap[hr] && constmap[i-1][hr] == constmap[i-2][hr]) | |
4970 | continue; | |
4971 | emit_movimm(constmap[i-1][hr],0); | |
4972 | emit_storereg(reg, 0); | |
4973 | } | |
4974 | } | |
40190245 | 4975 | if (dops[i].opcode == 0x0f) { // LUI |
4976 | emit_movimm(cinfo[i].imm << 16, 0); | |
4977 | emit_storereg(dops[i].rt1, 0); | |
4978 | } | |
630b122b | 4979 | emit_movimm(start+i*4,0); |
4980 | emit_writeword(0,&pcaddr); | |
4981 | int cc = get_reg(regs[i].regmap_entry, CCREG); | |
4982 | if (cc < 0) | |
4983 | emit_loadreg(CCREG, cc = 0); | |
4984 | emit_addimm(cc, ccadj_, 0); | |
4985 | emit_writeword(0, &psxRegs.cycle); | |
4986 | emit_far_call(do_insn_cmp); | |
4987 | //emit_readword(&cycle,0); | |
4988 | //emit_addimm(0,2,0); | |
4989 | //emit_writeword(0,&cycle); | |
4990 | (void)get_reg2; | |
4991 | restore_regs(reglist); | |
4992 | assem_debug("\\\\do_insn_cmp\n"); | |
4993 | } | |
40190245 | 4994 | static void drc_dbg_emit_wb_dirtys(int i, const struct regstat *i_regs) |
4995 | { | |
4996 | // write-out non-consts, consts are likely different because of get_final_value() | |
4997 | if (i_regs->dirty & ~i_regs->loadedconst) { | |
4998 | assem_debug("/ drc_dbg_wb\n"); | |
4999 | wb_dirtys(i_regs->regmap, i_regs->dirty & ~i_regs->loadedconst); | |
5000 | assem_debug("\\ drc_dbg_wb\n"); | |
5001 | } | |
5002 | } | |
630b122b | 5003 | #else |
5004 | #define drc_dbg_emit_do_cmp(x,y) | |
40190245 | 5005 | #define drc_dbg_emit_wb_dirtys(x,y) |
630b122b | 5006 | #endif |
5007 | ||
5008 | // Used when a branch jumps into the delay slot of another branch | |
5009 | static void ds_assemble_entry(int i) | |
5010 | { | |
259dbd60 | 5011 | int t = (cinfo[i].ba - start) >> 2; |
630b122b | 5012 | int ccadj_ = -CLOCK_ADJUST(1); |
5013 | if (!instr_addr[t]) | |
5014 | instr_addr[t] = out; | |
259dbd60 | 5015 | assem_debug("Assemble delay slot at %x\n",cinfo[i].ba); |
630b122b | 5016 | assem_debug("<->\n"); |
5017 | drc_dbg_emit_do_cmp(t, ccadj_); | |
5018 | if(regs[t].regmap_entry[HOST_CCREG]==CCREG&®s[t].regmap[HOST_CCREG]!=CCREG) | |
5019 | wb_register(CCREG,regs[t].regmap_entry,regs[t].wasdirty); | |
5020 | load_regs(regs[t].regmap_entry,regs[t].regmap,dops[t].rs1,dops[t].rs2); | |
5021 | address_generation(t,®s[t],regs[t].regmap_entry); | |
5022 | if (ram_offset && (dops[t].is_load || dops[t].is_store)) | |
e912c27d | 5023 | load_reg(regs[t].regmap_entry,regs[t].regmap,ROREG); |
630b122b | 5024 | if (dops[t].is_store) |
e912c27d | 5025 | load_reg(regs[t].regmap_entry,regs[t].regmap,INVCP); |
630b122b | 5026 | is_delayslot=0; |
5027 | switch (dops[t].itype) { | |
57871462 | 5028 | case SYSCALL: |
7139f3c8 | 5029 | case HLECALL: |
1e973cb0 | 5030 | case INTCALL: |
57871462 | 5031 | case UJUMP: |
5032 | case RJUMP: | |
5033 | case CJUMP: | |
5034 | case SJUMP: | |
c43b5311 | 5035 | SysPrintf("Jump in the delay slot. This is probably a bug.\n"); |
630b122b | 5036 | break; |
5037 | default: | |
5038 | assemble(t, ®s[t], ccadj_); | |
57871462 | 5039 | } |
259dbd60 | 5040 | store_regs_bt(regs[t].regmap,regs[t].dirty,cinfo[i].ba+4); |
5041 | load_regs_bt(regs[t].regmap,regs[t].dirty,cinfo[i].ba+4); | |
5042 | if(internal_branch(cinfo[i].ba+4)) | |
57871462 | 5043 | assem_debug("branch: internal\n"); |
5044 | else | |
5045 | assem_debug("branch: external\n"); | |
259dbd60 | 5046 | assert(internal_branch(cinfo[i].ba+4)); |
5047 | add_to_linker(out,cinfo[i].ba+4,internal_branch(cinfo[i].ba+4)); | |
57871462 | 5048 | emit_jmp(0); |
5049 | } | |
5050 | ||
630b122b | 5051 | // Load 2 immediates optimizing for small code size |
5052 | static void emit_mov2imm_compact(int imm1,u_int rt1,int imm2,u_int rt2) | |
57871462 | 5053 | { |
630b122b | 5054 | emit_movimm(imm1,rt1); |
5055 | emit_movimm_from(imm1,rt1,imm2,rt2); | |
5056 | } | |
5057 | ||
5058 | static void do_cc(int i, const signed char i_regmap[], int *adj, | |
5059 | int addr, int taken, int invert) | |
5060 | { | |
5061 | int count, count_plus2; | |
5062 | void *jaddr; | |
5063 | void *idle=NULL; | |
b6e87b2b | 5064 | int t=0; |
630b122b | 5065 | if(dops[i].itype==RJUMP) |
57871462 | 5066 | { |
5067 | *adj=0; | |
5068 | } | |
259dbd60 | 5069 | //if(cinfo[i].ba>=start && cinfo[i].ba<(start+slen*4)) |
5070 | if(internal_branch(cinfo[i].ba)) | |
57871462 | 5071 | { |
259dbd60 | 5072 | t=(cinfo[i].ba-start)>>2; |
630b122b | 5073 | if(dops[t].is_ds) *adj=-CLOCK_ADJUST(1); // Branch into delay slot adds an extra cycle |
259dbd60 | 5074 | else *adj=cinfo[t].ccadj; |
57871462 | 5075 | } |
5076 | else | |
5077 | { | |
5078 | *adj=0; | |
5079 | } | |
259dbd60 | 5080 | count = cinfo[i].ccadj; |
630b122b | 5081 | count_plus2 = count + CLOCK_ADJUST(2); |
259dbd60 | 5082 | if(taken==TAKEN && i==(cinfo[i].ba-start)>>2 && source[i+1]==0) { |
57871462 | 5083 | // Idle loop |
5084 | if(count&1) emit_addimm_and_set_flags(2*(count+2),HOST_CCREG); | |
630b122b | 5085 | idle=out; |
57871462 | 5086 | //emit_subfrommem(&idlecount,HOST_CCREG); // Count idle cycles |
5087 | emit_andimm(HOST_CCREG,3,HOST_CCREG); | |
630b122b | 5088 | jaddr=out; |
57871462 | 5089 | emit_jmp(0); |
5090 | } | |
5091 | else if(*adj==0||invert) { | |
630b122b | 5092 | int cycles = count_plus2; |
b6e87b2b | 5093 | // faster loop HACK |
630b122b | 5094 | #if 0 |
b6e87b2b | 5095 | if (t&&*adj) { |
5096 | int rel=t-i; | |
5097 | if(-NO_CYCLE_PENALTY_THR<rel&&rel<0) | |
630b122b | 5098 | cycles=*adj+count+2-*adj; |
b6e87b2b | 5099 | } |
630b122b | 5100 | #endif |
5101 | emit_addimm_and_set_flags(cycles, HOST_CCREG); | |
5102 | jaddr = out; | |
57871462 | 5103 | emit_jns(0); |
5104 | } | |
5105 | else | |
5106 | { | |
630b122b | 5107 | emit_cmpimm(HOST_CCREG, -count_plus2); |
5108 | jaddr = out; | |
57871462 | 5109 | emit_jns(0); |
5110 | } | |
630b122b | 5111 | add_stub(CC_STUB,jaddr,idle?idle:out,(*adj==0||invert||idle)?0:count_plus2,i,addr,taken,0); |
57871462 | 5112 | } |
5113 | ||
630b122b | 5114 | static void do_ccstub(int n) |
57871462 | 5115 | { |
5116 | literal_pool(256); | |
630b122b | 5117 | assem_debug("do_ccstub %x\n",start+(u_int)stubs[n].b*4); |
5118 | set_jump_target(stubs[n].addr, out); | |
5119 | int i=stubs[n].b; | |
e6e590d3 | 5120 | if (stubs[n].d != TAKEN) { |
630b122b | 5121 | wb_dirtys(branch_regs[i].regmap,branch_regs[i].dirty); |
57871462 | 5122 | } |
5123 | else { | |
259dbd60 | 5124 | if(internal_branch(cinfo[i].ba)) |
5125 | wb_needed_dirtys(branch_regs[i].regmap,branch_regs[i].dirty,cinfo[i].ba); | |
57871462 | 5126 | } |
630b122b | 5127 | if(stubs[n].c!=-1) |
57871462 | 5128 | { |
5129 | // Save PC as return address | |
6c62131f | 5130 | emit_movimm(stubs[n].c,0); |
5131 | emit_writeword(0,&pcaddr); | |
57871462 | 5132 | } |
5133 | else | |
5134 | { | |
5135 | // Return address depends on which way the branch goes | |
630b122b | 5136 | if(dops[i].itype==CJUMP||dops[i].itype==SJUMP) |
57871462 | 5137 | { |
630b122b | 5138 | int s1l=get_reg(branch_regs[i].regmap,dops[i].rs1); |
5139 | int s2l=get_reg(branch_regs[i].regmap,dops[i].rs2); | |
5140 | if(dops[i].rs1==0) | |
57871462 | 5141 | { |
630b122b | 5142 | s1l=s2l; |
5143 | s2l=-1; | |
57871462 | 5144 | } |
630b122b | 5145 | else if(dops[i].rs2==0) |
57871462 | 5146 | { |
630b122b | 5147 | s2l=-1; |
57871462 | 5148 | } |
5149 | assert(s1l>=0); | |
5150 | #ifdef DESTRUCTIVE_WRITEBACK | |
630b122b | 5151 | if(dops[i].rs1) { |
5152 | if((branch_regs[i].dirty>>s1l)&&1) | |
5153 | emit_loadreg(dops[i].rs1,s1l); | |
9f51b4b9 | 5154 | } |
57871462 | 5155 | else { |
630b122b | 5156 | if((branch_regs[i].dirty>>s1l)&1) |
5157 | emit_loadreg(dops[i].rs2,s1l); | |
57871462 | 5158 | } |
5159 | if(s2l>=0) | |
630b122b | 5160 | if((branch_regs[i].dirty>>s2l)&1) |
5161 | emit_loadreg(dops[i].rs2,s2l); | |
57871462 | 5162 | #endif |
5163 | int hr=0; | |
5194fb95 | 5164 | int addr=-1,alt=-1,ntaddr=-1; |
57871462 | 5165 | while(hr<HOST_REGS) |
5166 | { | |
5167 | if(hr!=EXCLUDE_REG && hr!=HOST_CCREG && | |
91af94f0 | 5168 | branch_regs[i].regmap[hr]!=dops[i].rs1 && |
5169 | branch_regs[i].regmap[hr]!=dops[i].rs2 ) | |
57871462 | 5170 | { |
5171 | addr=hr++;break; | |
5172 | } | |
5173 | hr++; | |
5174 | } | |
5175 | while(hr<HOST_REGS) | |
5176 | { | |
5177 | if(hr!=EXCLUDE_REG && hr!=HOST_CCREG && | |
91af94f0 | 5178 | branch_regs[i].regmap[hr]!=dops[i].rs1 && |
5179 | branch_regs[i].regmap[hr]!=dops[i].rs2 ) | |
57871462 | 5180 | { |
5181 | alt=hr++;break; | |
5182 | } | |
5183 | hr++; | |
5184 | } | |
3a64d2f7 | 5185 | if ((dops[i].opcode & 0x3e) == 6) // BLEZ/BGTZ needs another register |
57871462 | 5186 | { |
5187 | while(hr<HOST_REGS) | |
5188 | { | |
5189 | if(hr!=EXCLUDE_REG && hr!=HOST_CCREG && | |
91af94f0 | 5190 | branch_regs[i].regmap[hr]!=dops[i].rs1 && |
5191 | branch_regs[i].regmap[hr]!=dops[i].rs2 ) | |
57871462 | 5192 | { |
5193 | ntaddr=hr;break; | |
5194 | } | |
5195 | hr++; | |
5196 | } | |
5197 | assert(hr<HOST_REGS); | |
5198 | } | |
3a64d2f7 | 5199 | if (dops[i].opcode == 4) // BEQ |
57871462 | 5200 | { |
5201 | #ifdef HAVE_CMOV_IMM | |
630b122b | 5202 | if(s2l>=0) emit_cmp(s1l,s2l); |
5203 | else emit_test(s1l,s1l); | |
259dbd60 | 5204 | emit_cmov2imm_e_ne_compact(cinfo[i].ba,start+i*4+8,addr); |
630b122b | 5205 | #else |
259dbd60 | 5206 | emit_mov2imm_compact(cinfo[i].ba,addr,start+i*4+8,alt); |
630b122b | 5207 | if(s2l>=0) emit_cmp(s1l,s2l); |
5208 | else emit_test(s1l,s1l); | |
5209 | emit_cmovne_reg(alt,addr); | |
57871462 | 5210 | #endif |
57871462 | 5211 | } |
3a64d2f7 | 5212 | else if (dops[i].opcode == 5) // BNE |
57871462 | 5213 | { |
5214 | #ifdef HAVE_CMOV_IMM | |
630b122b | 5215 | if(s2l>=0) emit_cmp(s1l,s2l); |
5216 | else emit_test(s1l,s1l); | |
259dbd60 | 5217 | emit_cmov2imm_e_ne_compact(start+i*4+8,cinfo[i].ba,addr); |
630b122b | 5218 | #else |
259dbd60 | 5219 | emit_mov2imm_compact(start+i*4+8,addr,cinfo[i].ba,alt); |
630b122b | 5220 | if(s2l>=0) emit_cmp(s1l,s2l); |
5221 | else emit_test(s1l,s1l); | |
5222 | emit_cmovne_reg(alt,addr); | |
57871462 | 5223 | #endif |
57871462 | 5224 | } |
3a64d2f7 | 5225 | else if (dops[i].opcode == 6) // BLEZ |
57871462 | 5226 | { |
259dbd60 | 5227 | //emit_movimm(cinfo[i].ba,alt); |
57871462 | 5228 | //emit_movimm(start+i*4+8,addr); |
259dbd60 | 5229 | emit_mov2imm_compact(cinfo[i].ba,alt,start+i*4+8,addr); |
57871462 | 5230 | emit_cmpimm(s1l,1); |
57871462 | 5231 | emit_cmovl_reg(alt,addr); |
57871462 | 5232 | } |
3a64d2f7 | 5233 | else if (dops[i].opcode == 7) // BGTZ |
57871462 | 5234 | { |
259dbd60 | 5235 | //emit_movimm(cinfo[i].ba,addr); |
57871462 | 5236 | //emit_movimm(start+i*4+8,ntaddr); |
259dbd60 | 5237 | emit_mov2imm_compact(cinfo[i].ba,addr,start+i*4+8,ntaddr); |
57871462 | 5238 | emit_cmpimm(s1l,1); |
57871462 | 5239 | emit_cmovl_reg(ntaddr,addr); |
57871462 | 5240 | } |
3a64d2f7 | 5241 | else if (dops[i].itype == SJUMP) // BLTZ/BGEZ |
57871462 | 5242 | { |
259dbd60 | 5243 | //emit_movimm(cinfo[i].ba,alt); |
57871462 | 5244 | //emit_movimm(start+i*4+8,addr); |
5753f874 | 5245 | if (dops[i].rs1) { |
5246 | emit_mov2imm_compact(cinfo[i].ba, | |
5247 | (dops[i].opcode2 & 1) ? addr : alt, start + i*4 + 8, | |
5248 | (dops[i].opcode2 & 1) ? alt : addr); | |
5249 | emit_test(s1l,s1l); | |
5250 | emit_cmovs_reg(alt,addr); | |
5251 | } | |
5252 | else | |
5253 | emit_movimm((dops[i].opcode2 & 1) ? cinfo[i].ba : start + i*4 + 8, addr); | |
57871462 | 5254 | } |
3a64d2f7 | 5255 | emit_writeword(addr, &pcaddr); |
57871462 | 5256 | } |
5257 | else | |
630b122b | 5258 | if(dops[i].itype==RJUMP) |
57871462 | 5259 | { |
630b122b | 5260 | int r=get_reg(branch_regs[i].regmap,dops[i].rs1); |
5261 | if (ds_writes_rjump_rs(i)) { | |
57871462 | 5262 | r=get_reg(branch_regs[i].regmap,RTEMP); |
5263 | } | |
630b122b | 5264 | emit_writeword(r,&pcaddr); |
57871462 | 5265 | } |
630b122b | 5266 | else {SysPrintf("Unknown branch type in do_ccstub\n");abort();} |
57871462 | 5267 | } |
5268 | // Update cycle count | |
5269 | assert(branch_regs[i].regmap[HOST_CCREG]==CCREG||branch_regs[i].regmap[HOST_CCREG]==-1); | |
630b122b | 5270 | if(stubs[n].a) emit_addimm(HOST_CCREG,(int)stubs[n].a,HOST_CCREG); |
5271 | emit_far_call(cc_interrupt); | |
5272 | if(stubs[n].a) emit_addimm(HOST_CCREG,-(int)stubs[n].a,HOST_CCREG); | |
5273 | if(stubs[n].d==TAKEN) { | |
259dbd60 | 5274 | if(internal_branch(cinfo[i].ba)) |
5275 | load_needed_regs(branch_regs[i].regmap,regs[(cinfo[i].ba-start)>>2].regmap_entry); | |
630b122b | 5276 | else if(dops[i].itype==RJUMP) { |
57871462 | 5277 | if(get_reg(branch_regs[i].regmap,RTEMP)>=0) |
630b122b | 5278 | emit_readword(&pcaddr,get_reg(branch_regs[i].regmap,RTEMP)); |
57871462 | 5279 | else |
630b122b | 5280 | emit_loadreg(dops[i].rs1,get_reg(branch_regs[i].regmap,dops[i].rs1)); |
57871462 | 5281 | } |
630b122b | 5282 | }else if(stubs[n].d==NOTTAKEN) { |
57871462 | 5283 | if(i<slen-2) load_needed_regs(branch_regs[i].regmap,regmap_pre[i+2]); |
5284 | else load_all_regs(branch_regs[i].regmap); | |
57871462 | 5285 | }else{ |
5286 | load_all_regs(branch_regs[i].regmap); | |
5287 | } | |
630b122b | 5288 | if (stubs[n].retaddr) |
5289 | emit_jmp(stubs[n].retaddr); | |
5290 | else | |
5291 | do_jump_vaddr(stubs[n].e); | |
5292 | } | |
5293 | ||
048fcced | 5294 | static void add_to_linker(void *addr, u_int target, int is_internal) |
630b122b | 5295 | { |
5296 | assert(linkcount < ARRAY_SIZE(link_addr)); | |
5297 | link_addr[linkcount].addr = addr; | |
5298 | link_addr[linkcount].target = target; | |
048fcced | 5299 | link_addr[linkcount].internal = is_internal; |
57871462 | 5300 | linkcount++; |
5301 | } | |
5302 | ||
eba830cd | 5303 | static void ujump_assemble_write_ra(int i) |
5304 | { | |
5305 | int rt; | |
5306 | unsigned int return_address; | |
5307 | rt=get_reg(branch_regs[i].regmap,31); | |
5753f874 | 5308 | //assem_debug("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]); |
eba830cd | 5309 | //assert(rt>=0); |
5310 | return_address=start+i*4+8; | |
5311 | if(rt>=0) { | |
5312 | #ifdef USE_MINI_HT | |
630b122b | 5313 | if(internal_branch(return_address)&&dops[i+1].rt1!=31) { |
eba830cd | 5314 | int temp=-1; // note: must be ds-safe |
5315 | #ifdef HOST_TEMPREG | |
5316 | temp=HOST_TEMPREG; | |
5317 | #endif | |
5318 | if(temp>=0) do_miniht_insert(return_address,rt,temp); | |
5319 | else emit_movimm(return_address,rt); | |
5320 | } | |
5321 | else | |
5322 | #endif | |
5323 | { | |
5324 | #ifdef REG_PREFETCH | |
9f51b4b9 | 5325 | if(temp>=0) |
eba830cd | 5326 | { |
630b122b | 5327 | if(i_regmap[temp]!=PTEMP) emit_movimm((uintptr_t)hash_table_get(return_address),temp); |
eba830cd | 5328 | } |
5329 | #endif | |
5753f874 | 5330 | if (!((regs[i].loadedconst >> rt) & 1)) |
5331 | emit_movimm(return_address, rt); // PC into link register | |
eba830cd | 5332 | #ifdef IMM_PREFETCH |
630b122b | 5333 | emit_prefetch(hash_table_get(return_address)); |
eba830cd | 5334 | #endif |
5335 | } | |
5336 | } | |
5337 | } | |
5338 | ||
630b122b | 5339 | static void ujump_assemble(int i, const struct regstat *i_regs) |
57871462 | 5340 | { |
259dbd60 | 5341 | if(i==(cinfo[i].ba-start)>>2) assem_debug("idle loop\n"); |
57871462 | 5342 | address_generation(i+1,i_regs,regs[i].regmap_entry); |
5343 | #ifdef REG_PREFETCH | |
5344 | int temp=get_reg(branch_regs[i].regmap,PTEMP); | |
630b122b | 5345 | if(dops[i].rt1==31&&temp>=0) |
57871462 | 5346 | { |
581335b0 | 5347 | signed char *i_regmap=i_regs->regmap; |
57871462 | 5348 | int return_address=start+i*4+8; |
9f51b4b9 | 5349 | if(get_reg(branch_regs[i].regmap,31)>0) |
630b122b | 5350 | if(i_regmap[temp]==PTEMP) emit_movimm((uintptr_t)hash_table_get(return_address),temp); |
57871462 | 5351 | } |
5352 | #endif | |
5753f874 | 5353 | if (dops[i].rt1 == 31) |
eba830cd | 5354 | ujump_assemble_write_ra(i); // writeback ra for DS |
4ef8f67d | 5355 | ds_assemble(i+1,i_regs); |
5356 | uint64_t bc_unneeded=branch_regs[i].u; | |
630b122b | 5357 | bc_unneeded|=1|(1LL<<dops[i].rt1); |
5358 | wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,bc_unneeded); | |
e912c27d | 5359 | load_reg(regs[i].regmap,branch_regs[i].regmap,CCREG); |
57871462 | 5360 | int cc,adj; |
5361 | cc=get_reg(branch_regs[i].regmap,CCREG); | |
5362 | assert(cc==HOST_CCREG); | |
259dbd60 | 5363 | store_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,cinfo[i].ba); |
57871462 | 5364 | #ifdef REG_PREFETCH |
630b122b | 5365 | if(dops[i].rt1==31&&temp>=0) emit_prefetchreg(temp); |
57871462 | 5366 | #endif |
259dbd60 | 5367 | do_cc(i,branch_regs[i].regmap,&adj,cinfo[i].ba,TAKEN,0); |
5368 | if(adj) emit_addimm(cc, cinfo[i].ccadj + CLOCK_ADJUST(2) - adj, cc); | |
5369 | load_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,cinfo[i].ba); | |
5370 | if(internal_branch(cinfo[i].ba)) | |
57871462 | 5371 | assem_debug("branch: internal\n"); |
5372 | else | |
5373 | assem_debug("branch: external\n"); | |
259dbd60 | 5374 | if (internal_branch(cinfo[i].ba) && dops[(cinfo[i].ba-start)>>2].is_ds) { |
57871462 | 5375 | ds_assemble_entry(i); |
5376 | } | |
5377 | else { | |
259dbd60 | 5378 | add_to_linker(out,cinfo[i].ba,internal_branch(cinfo[i].ba)); |
57871462 | 5379 | emit_jmp(0); |
5380 | } | |
5381 | } | |
5382 | ||
eba830cd | 5383 | static void rjump_assemble_write_ra(int i) |
5384 | { | |
5385 | int rt,return_address; | |
f2e25348 | 5386 | rt=get_reg_w(branch_regs[i].regmap, dops[i].rt1); |
5753f874 | 5387 | //assem_debug("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]); |
eba830cd | 5388 | assert(rt>=0); |
5389 | return_address=start+i*4+8; | |
5390 | #ifdef REG_PREFETCH | |
9f51b4b9 | 5391 | if(temp>=0) |
eba830cd | 5392 | { |
630b122b | 5393 | if(i_regmap[temp]!=PTEMP) emit_movimm((uintptr_t)hash_table_get(return_address),temp); |
eba830cd | 5394 | } |
5395 | #endif | |
5753f874 | 5396 | if (!((regs[i].loadedconst >> rt) & 1)) |
5397 | emit_movimm(return_address, rt); // PC into link register | |
eba830cd | 5398 | #ifdef IMM_PREFETCH |
630b122b | 5399 | emit_prefetch(hash_table_get(return_address)); |
eba830cd | 5400 | #endif |
5401 | } | |
5402 | ||
630b122b | 5403 | static void rjump_assemble(int i, const struct regstat *i_regs) |
57871462 | 5404 | { |
57871462 | 5405 | int temp; |
581335b0 | 5406 | int rs,cc; |
630b122b | 5407 | rs=get_reg(branch_regs[i].regmap,dops[i].rs1); |
57871462 | 5408 | assert(rs>=0); |
630b122b | 5409 | if (ds_writes_rjump_rs(i)) { |
57871462 | 5410 | // Delay slot abuse, make a copy of the branch address register |
5411 | temp=get_reg(branch_regs[i].regmap,RTEMP); | |
5412 | assert(temp>=0); | |
5413 | assert(regs[i].regmap[temp]==RTEMP); | |
5414 | emit_mov(rs,temp); | |
5415 | rs=temp; | |
5416 | } | |
5417 | address_generation(i+1,i_regs,regs[i].regmap_entry); | |
5418 | #ifdef REG_PREFETCH | |
630b122b | 5419 | if(dops[i].rt1==31) |
57871462 | 5420 | { |
5421 | if((temp=get_reg(branch_regs[i].regmap,PTEMP))>=0) { | |
581335b0 | 5422 | signed char *i_regmap=i_regs->regmap; |
57871462 | 5423 | int return_address=start+i*4+8; |
630b122b | 5424 | if(i_regmap[temp]==PTEMP) emit_movimm((uintptr_t)hash_table_get(return_address),temp); |
57871462 | 5425 | } |
5426 | } | |
5427 | #endif | |
5428 | #ifdef USE_MINI_HT | |
630b122b | 5429 | if(dops[i].rs1==31) { |
57871462 | 5430 | int rh=get_reg(regs[i].regmap,RHASH); |
5431 | if(rh>=0) do_preload_rhash(rh); | |
5432 | } | |
5433 | #endif | |
5753f874 | 5434 | if (dops[i].rt1 != 0) |
eba830cd | 5435 | rjump_assemble_write_ra(i); |
d5910d5d | 5436 | ds_assemble(i+1,i_regs); |
5437 | uint64_t bc_unneeded=branch_regs[i].u; | |
630b122b | 5438 | bc_unneeded|=1|(1LL<<dops[i].rt1); |
5439 | bc_unneeded&=~(1LL<<dops[i].rs1); | |
5440 | wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,bc_unneeded); | |
5441 | load_regs(regs[i].regmap,branch_regs[i].regmap,dops[i].rs1,CCREG); | |
57871462 | 5442 | cc=get_reg(branch_regs[i].regmap,CCREG); |
5443 | assert(cc==HOST_CCREG); | |
581335b0 | 5444 | (void)cc; |
57871462 | 5445 | #ifdef USE_MINI_HT |
5446 | int rh=get_reg(branch_regs[i].regmap,RHASH); | |
5447 | int ht=get_reg(branch_regs[i].regmap,RHTBL); | |
630b122b | 5448 | if(dops[i].rs1==31) { |
57871462 | 5449 | if(regs[i].regmap[rh]!=RHASH) do_preload_rhash(rh); |
5450 | do_preload_rhtbl(ht); | |
5451 | do_rhash(rs,rh); | |
5452 | } | |
5453 | #endif | |
630b122b | 5454 | store_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,-1); |
57871462 | 5455 | #ifdef DESTRUCTIVE_WRITEBACK |
630b122b | 5456 | if((branch_regs[i].dirty>>rs)&1) { |
5457 | if(dops[i].rs1!=dops[i+1].rt1&&dops[i].rs1!=dops[i+1].rt2) { | |
5458 | emit_loadreg(dops[i].rs1,rs); | |
57871462 | 5459 | } |
5460 | } | |
5461 | #endif | |
5462 | #ifdef REG_PREFETCH | |
630b122b | 5463 | if(dops[i].rt1==31&&temp>=0) emit_prefetchreg(temp); |
57871462 | 5464 | #endif |
5465 | #ifdef USE_MINI_HT | |
630b122b | 5466 | if(dops[i].rs1==31) { |
57871462 | 5467 | do_miniht_load(ht,rh); |
5468 | } | |
5469 | #endif | |
5470 | //do_cc(i,branch_regs[i].regmap,&adj,-1,TAKEN); | |
259dbd60 | 5471 | //if(adj) emit_addimm(cc,2*(cinfo[i].ccadj+2-adj),cc); // ??? - Shouldn't happen |
57871462 | 5472 | //assert(adj==0); |
259dbd60 | 5473 | emit_addimm_and_set_flags(cinfo[i].ccadj + CLOCK_ADJUST(2), HOST_CCREG); |
630b122b | 5474 | add_stub(CC_STUB,out,NULL,0,i,-1,TAKEN,rs); |
f2e25348 | 5475 | if (dops[i+1].itype == RFE) |
911f2d55 | 5476 | // special case for RFE |
5477 | emit_jmp(0); | |
5478 | else | |
71e490c5 | 5479 | emit_jns(0); |
630b122b | 5480 | //load_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,-1); |
57871462 | 5481 | #ifdef USE_MINI_HT |
630b122b | 5482 | if(dops[i].rs1==31) { |
57871462 | 5483 | do_miniht_jump(rs,rh,ht); |
5484 | } | |
5485 | else | |
5486 | #endif | |
5487 | { | |
630b122b | 5488 | do_jump_vaddr(rs); |
5489 | } | |
57871462 | 5490 | #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK |
630b122b | 5491 | if(dops[i].rt1!=31&&i<slen-2&&(((u_int)out)&7)) emit_mov(13,13); |
57871462 | 5492 | #endif |
5493 | } | |
5494 | ||
630b122b | 5495 | static void cjump_assemble(int i, const struct regstat *i_regs) |
57871462 | 5496 | { |
630b122b | 5497 | const signed char *i_regmap = i_regs->regmap; |
57871462 | 5498 | int cc; |
5499 | int match; | |
259dbd60 | 5500 | match=match_bt(branch_regs[i].regmap,branch_regs[i].dirty,cinfo[i].ba); |
57871462 | 5501 | assem_debug("match=%d\n",match); |
630b122b | 5502 | int s1l,s2l; |
57871462 | 5503 | int unconditional=0,nop=0; |
57871462 | 5504 | int invert=0; |
259dbd60 | 5505 | int internal=internal_branch(cinfo[i].ba); |
5506 | if(i==(cinfo[i].ba-start)>>2) assem_debug("idle loop\n"); | |
57871462 | 5507 | if(!match) invert=1; |
5508 | #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK | |
259dbd60 | 5509 | if(i>(cinfo[i].ba-start)>>2) invert=1; |
57871462 | 5510 | #endif |
630b122b | 5511 | #ifdef __aarch64__ |
5512 | invert=1; // because of near cond. branches | |
5513 | #endif | |
9f51b4b9 | 5514 | |
630b122b | 5515 | if(dops[i].ooo) { |
5516 | s1l=get_reg(branch_regs[i].regmap,dops[i].rs1); | |
5517 | s2l=get_reg(branch_regs[i].regmap,dops[i].rs2); | |
57871462 | 5518 | } |
5519 | else { | |
630b122b | 5520 | s1l=get_reg(i_regmap,dops[i].rs1); |
5521 | s2l=get_reg(i_regmap,dops[i].rs2); | |
57871462 | 5522 | } |
630b122b | 5523 | if(dops[i].rs1==0&&dops[i].rs2==0) |
57871462 | 5524 | { |
630b122b | 5525 | if(dops[i].opcode&1) nop=1; |
57871462 | 5526 | else unconditional=1; |
630b122b | 5527 | //assert(dops[i].opcode!=5); |
5528 | //assert(dops[i].opcode!=7); | |
5529 | //assert(dops[i].opcode!=0x15); | |
5530 | //assert(dops[i].opcode!=0x17); | |
57871462 | 5531 | } |
630b122b | 5532 | else if(dops[i].rs1==0) |
57871462 | 5533 | { |
630b122b | 5534 | s1l=s2l; |
5535 | s2l=-1; | |
57871462 | 5536 | } |
630b122b | 5537 | else if(dops[i].rs2==0) |
57871462 | 5538 | { |
630b122b | 5539 | s2l=-1; |
57871462 | 5540 | } |
5541 | ||
630b122b | 5542 | if(dops[i].ooo) { |
57871462 | 5543 | // Out of order execution (delay slot first) |
5544 | //printf("OOOE\n"); | |
5545 | address_generation(i+1,i_regs,regs[i].regmap_entry); | |
5546 | ds_assemble(i+1,i_regs); | |
5547 | int adj; | |
5548 | uint64_t bc_unneeded=branch_regs[i].u; | |
630b122b | 5549 | bc_unneeded&=~((1LL<<dops[i].rs1)|(1LL<<dops[i].rs2)); |
57871462 | 5550 | bc_unneeded|=1; |
630b122b | 5551 | wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,bc_unneeded); |
5552 | load_regs(regs[i].regmap,branch_regs[i].regmap,dops[i].rs1,dops[i].rs2); | |
e912c27d | 5553 | load_reg(regs[i].regmap,branch_regs[i].regmap,CCREG); |
57871462 | 5554 | cc=get_reg(branch_regs[i].regmap,CCREG); |
5555 | assert(cc==HOST_CCREG); | |
9f51b4b9 | 5556 | if(unconditional) |
259dbd60 | 5557 | store_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,cinfo[i].ba); |
5558 | //do_cc(i,branch_regs[i].regmap,&adj,unconditional?cinfo[i].ba:-1,unconditional); | |
57871462 | 5559 | //assem_debug("cycle count (adj)\n"); |
5560 | if(unconditional) { | |
259dbd60 | 5561 | do_cc(i,branch_regs[i].regmap,&adj,cinfo[i].ba,TAKEN,0); |
5562 | if(i!=(cinfo[i].ba-start)>>2 || source[i+1]!=0) { | |
5563 | if(adj) emit_addimm(cc, cinfo[i].ccadj + CLOCK_ADJUST(2) - adj, cc); | |
5564 | load_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,cinfo[i].ba); | |
57871462 | 5565 | if(internal) |
5566 | assem_debug("branch: internal\n"); | |
5567 | else | |
5568 | assem_debug("branch: external\n"); | |
259dbd60 | 5569 | if (internal && dops[(cinfo[i].ba-start)>>2].is_ds) { |
57871462 | 5570 | ds_assemble_entry(i); |
5571 | } | |
5572 | else { | |
259dbd60 | 5573 | add_to_linker(out,cinfo[i].ba,internal); |
57871462 | 5574 | emit_jmp(0); |
5575 | } | |
5576 | #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK | |
5577 | if(((u_int)out)&7) emit_addnop(0); | |
5578 | #endif | |
5579 | } | |
5580 | } | |
5581 | else if(nop) { | |
259dbd60 | 5582 | emit_addimm_and_set_flags(cinfo[i].ccadj + CLOCK_ADJUST(2), cc); |
630b122b | 5583 | void *jaddr=out; |
57871462 | 5584 | emit_jns(0); |
630b122b | 5585 | add_stub(CC_STUB,jaddr,out,0,i,start+i*4+8,NOTTAKEN,0); |
57871462 | 5586 | } |
5587 | else { | |
630b122b | 5588 | void *taken = NULL, *nottaken = NULL, *nottaken1 = NULL; |
57871462 | 5589 | do_cc(i,branch_regs[i].regmap,&adj,-1,0,invert); |
259dbd60 | 5590 | if(adj&&!invert) emit_addimm(cc, cinfo[i].ccadj + CLOCK_ADJUST(2) - adj, cc); |
9f51b4b9 | 5591 | |
57871462 | 5592 | //printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]); |
5593 | assert(s1l>=0); | |
630b122b | 5594 | if(dops[i].opcode==4) // BEQ |
57871462 | 5595 | { |
5596 | if(s2l>=0) emit_cmp(s1l,s2l); | |
5597 | else emit_test(s1l,s1l); | |
5598 | if(invert){ | |
630b122b | 5599 | nottaken=out; |
5600 | emit_jne(DJT_1); | |
57871462 | 5601 | }else{ |
259dbd60 | 5602 | add_to_linker(out,cinfo[i].ba,internal); |
57871462 | 5603 | emit_jeq(0); |
5604 | } | |
5605 | } | |
630b122b | 5606 | if(dops[i].opcode==5) // BNE |
57871462 | 5607 | { |
5608 | if(s2l>=0) emit_cmp(s1l,s2l); | |
5609 | else emit_test(s1l,s1l); | |
5610 | if(invert){ | |
630b122b | 5611 | nottaken=out; |
5612 | emit_jeq(DJT_1); | |
57871462 | 5613 | }else{ |
259dbd60 | 5614 | add_to_linker(out,cinfo[i].ba,internal); |
57871462 | 5615 | emit_jne(0); |
5616 | } | |
5617 | } | |
630b122b | 5618 | if(dops[i].opcode==6) // BLEZ |
57871462 | 5619 | { |
5620 | emit_cmpimm(s1l,1); | |
5621 | if(invert){ | |
630b122b | 5622 | nottaken=out; |
5623 | emit_jge(DJT_1); | |
57871462 | 5624 | }else{ |
259dbd60 | 5625 | add_to_linker(out,cinfo[i].ba,internal); |
57871462 | 5626 | emit_jl(0); |
5627 | } | |
5628 | } | |
630b122b | 5629 | if(dops[i].opcode==7) // BGTZ |
57871462 | 5630 | { |
5631 | emit_cmpimm(s1l,1); | |
5632 | if(invert){ | |
630b122b | 5633 | nottaken=out; |
5634 | emit_jl(DJT_1); | |
57871462 | 5635 | }else{ |
259dbd60 | 5636 | add_to_linker(out,cinfo[i].ba,internal); |
57871462 | 5637 | emit_jge(0); |
5638 | } | |
5639 | } | |
5640 | if(invert) { | |
630b122b | 5641 | if(taken) set_jump_target(taken, out); |
57871462 | 5642 | #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK |
259dbd60 | 5643 | if (match && (!internal || !dops[(cinfo[i].ba-start)>>2].is_ds)) { |
57871462 | 5644 | if(adj) { |
630b122b | 5645 | emit_addimm(cc,-adj,cc); |
259dbd60 | 5646 | add_to_linker(out,cinfo[i].ba,internal); |
57871462 | 5647 | }else{ |
5648 | emit_addnop(13); | |
259dbd60 | 5649 | add_to_linker(out,cinfo[i].ba,internal*2); |
57871462 | 5650 | } |
5651 | emit_jmp(0); | |
5652 | }else | |
5653 | #endif | |
5654 | { | |
630b122b | 5655 | if(adj) emit_addimm(cc,-adj,cc); |
259dbd60 | 5656 | store_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,cinfo[i].ba); |
5657 | load_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,cinfo[i].ba); | |
57871462 | 5658 | if(internal) |
5659 | assem_debug("branch: internal\n"); | |
5660 | else | |
5661 | assem_debug("branch: external\n"); | |
259dbd60 | 5662 | if (internal && dops[(cinfo[i].ba - start) >> 2].is_ds) { |
57871462 | 5663 | ds_assemble_entry(i); |
5664 | } | |
5665 | else { | |
259dbd60 | 5666 | add_to_linker(out,cinfo[i].ba,internal); |
57871462 | 5667 | emit_jmp(0); |
5668 | } | |
5669 | } | |
630b122b | 5670 | set_jump_target(nottaken, out); |
57871462 | 5671 | } |
5672 | ||
630b122b | 5673 | if(nottaken1) set_jump_target(nottaken1, out); |
57871462 | 5674 | if(adj) { |
630b122b | 5675 | if(!invert) emit_addimm(cc,adj,cc); |
57871462 | 5676 | } |
5677 | } // (!unconditional) | |
5678 | } // if(ooo) | |
5679 | else | |
5680 | { | |
5681 | // In-order execution (branch first) | |
630b122b | 5682 | void *taken = NULL, *nottaken = NULL, *nottaken1 = NULL; |
57871462 | 5683 | if(!unconditional&&!nop) { |
57871462 | 5684 | //printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]); |
5685 | assert(s1l>=0); | |
630b122b | 5686 | if((dops[i].opcode&0x2f)==4) // BEQ |
57871462 | 5687 | { |
5688 | if(s2l>=0) emit_cmp(s1l,s2l); | |
5689 | else emit_test(s1l,s1l); | |
630b122b | 5690 | nottaken=out; |
5691 | emit_jne(DJT_2); | |
57871462 | 5692 | } |
630b122b | 5693 | if((dops[i].opcode&0x2f)==5) // BNE |
57871462 | 5694 | { |
5695 | if(s2l>=0) emit_cmp(s1l,s2l); | |
5696 | else emit_test(s1l,s1l); | |
630b122b | 5697 | nottaken=out; |
5698 | emit_jeq(DJT_2); | |
57871462 | 5699 | } |
630b122b | 5700 | if((dops[i].opcode&0x2f)==6) // BLEZ |
57871462 | 5701 | { |
5702 | emit_cmpimm(s1l,1); | |
630b122b | 5703 | nottaken=out; |
5704 | emit_jge(DJT_2); | |
57871462 | 5705 | } |
630b122b | 5706 | if((dops[i].opcode&0x2f)==7) // BGTZ |
57871462 | 5707 | { |
5708 | emit_cmpimm(s1l,1); | |
630b122b | 5709 | nottaken=out; |
5710 | emit_jl(DJT_2); | |
57871462 | 5711 | } |
5712 | } // if(!unconditional) | |
5713 | int adj; | |
5714 | uint64_t ds_unneeded=branch_regs[i].u; | |
630b122b | 5715 | ds_unneeded&=~((1LL<<dops[i+1].rs1)|(1LL<<dops[i+1].rs2)); |
57871462 | 5716 | ds_unneeded|=1; |
57871462 | 5717 | // branch taken |
5718 | if(!nop) { | |
630b122b | 5719 | if(taken) set_jump_target(taken, out); |
57871462 | 5720 | assem_debug("1:\n"); |
630b122b | 5721 | wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,ds_unneeded); |
57871462 | 5722 | // load regs |
630b122b | 5723 | load_regs(regs[i].regmap,branch_regs[i].regmap,dops[i+1].rs1,dops[i+1].rs2); |
57871462 | 5724 | address_generation(i+1,&branch_regs[i],0); |
630b122b | 5725 | if (ram_offset) |
e912c27d | 5726 | load_reg(regs[i].regmap,branch_regs[i].regmap,ROREG); |
630b122b | 5727 | load_regs(regs[i].regmap,branch_regs[i].regmap,CCREG,INVCP); |
57871462 | 5728 | ds_assemble(i+1,&branch_regs[i]); |
40190245 | 5729 | drc_dbg_emit_wb_dirtys(i+1, &branch_regs[i]); |
57871462 | 5730 | cc=get_reg(branch_regs[i].regmap,CCREG); |
5731 | if(cc==-1) { | |
5732 | emit_loadreg(CCREG,cc=HOST_CCREG); | |
5733 | // CHECK: Is the following instruction (fall thru) allocated ok? | |
5734 | } | |
5735 | assert(cc==HOST_CCREG); | |
259dbd60 | 5736 | store_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,cinfo[i].ba); |
5737 | do_cc(i,i_regmap,&adj,cinfo[i].ba,TAKEN,0); | |
57871462 | 5738 | assem_debug("cycle count (adj)\n"); |
259dbd60 | 5739 | if(adj) emit_addimm(cc, cinfo[i].ccadj + CLOCK_ADJUST(2) - adj, cc); |
5740 | load_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,cinfo[i].ba); | |
57871462 | 5741 | if(internal) |
5742 | assem_debug("branch: internal\n"); | |
5743 | else | |
5744 | assem_debug("branch: external\n"); | |
259dbd60 | 5745 | if (internal && dops[(cinfo[i].ba - start) >> 2].is_ds) { |
57871462 | 5746 | ds_assemble_entry(i); |
5747 | } | |
5748 | else { | |
259dbd60 | 5749 | add_to_linker(out,cinfo[i].ba,internal); |
57871462 | 5750 | emit_jmp(0); |
5751 | } | |
5752 | } | |
5753 | // branch not taken | |
57871462 | 5754 | if(!unconditional) { |
630b122b | 5755 | if(nottaken1) set_jump_target(nottaken1, out); |
5756 | set_jump_target(nottaken, out); | |
57871462 | 5757 | assem_debug("2:\n"); |
630b122b | 5758 | wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,ds_unneeded); |
5759 | // load regs | |
5760 | load_regs(regs[i].regmap,branch_regs[i].regmap,dops[i+1].rs1,dops[i+1].rs2); | |
5761 | address_generation(i+1,&branch_regs[i],0); | |
5762 | if (ram_offset) | |
e912c27d | 5763 | load_reg(regs[i].regmap,branch_regs[i].regmap,ROREG); |
630b122b | 5764 | load_regs(regs[i].regmap,branch_regs[i].regmap,CCREG,INVCP); |
5765 | ds_assemble(i+1,&branch_regs[i]); | |
57871462 | 5766 | cc=get_reg(branch_regs[i].regmap,CCREG); |
630b122b | 5767 | if (cc == -1) { |
57871462 | 5768 | // Cycle count isn't in a register, temporarily load it then write it out |
5769 | emit_loadreg(CCREG,HOST_CCREG); | |
259dbd60 | 5770 | emit_addimm_and_set_flags(cinfo[i].ccadj + CLOCK_ADJUST(2), HOST_CCREG); |
630b122b | 5771 | void *jaddr=out; |
57871462 | 5772 | emit_jns(0); |
630b122b | 5773 | add_stub(CC_STUB,jaddr,out,0,i,start+i*4+8,NOTTAKEN,0); |
57871462 | 5774 | emit_storereg(CCREG,HOST_CCREG); |
5775 | } | |
5776 | else{ | |
5777 | cc=get_reg(i_regmap,CCREG); | |
5778 | assert(cc==HOST_CCREG); | |
259dbd60 | 5779 | emit_addimm_and_set_flags(cinfo[i].ccadj + CLOCK_ADJUST(2), cc); |
630b122b | 5780 | void *jaddr=out; |
57871462 | 5781 | emit_jns(0); |
630b122b | 5782 | add_stub(CC_STUB,jaddr,out,0,i,start+i*4+8,NOTTAKEN,0); |
57871462 | 5783 | } |
5784 | } | |
5785 | } | |
5786 | } | |
5787 | ||
630b122b | 5788 | static void sjump_assemble(int i, const struct regstat *i_regs) |
57871462 | 5789 | { |
630b122b | 5790 | const signed char *i_regmap = i_regs->regmap; |
57871462 | 5791 | int cc; |
5792 | int match; | |
259dbd60 | 5793 | match=match_bt(branch_regs[i].regmap,branch_regs[i].dirty,cinfo[i].ba); |
fdf33825 | 5794 | assem_debug("smatch=%d ooo=%d\n", match, dops[i].ooo); |
630b122b | 5795 | int s1l; |
57871462 | 5796 | int unconditional=0,nevertaken=0; |
57871462 | 5797 | int invert=0; |
259dbd60 | 5798 | int internal=internal_branch(cinfo[i].ba); |
5799 | if(i==(cinfo[i].ba-start)>>2) assem_debug("idle loop\n"); | |
57871462 | 5800 | if(!match) invert=1; |
5801 | #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK | |
259dbd60 | 5802 | if(i>(cinfo[i].ba-start)>>2) invert=1; |
57871462 | 5803 | #endif |
630b122b | 5804 | #ifdef __aarch64__ |
5805 | invert=1; // because of near cond. branches | |
5806 | #endif | |
57871462 | 5807 | |
630b122b | 5808 | //if(dops[i].opcode2>=0x10) return; // FIXME (BxxZAL) |
5809 | //assert(dops[i].opcode2<0x10||dops[i].rs1==0); // FIXME (BxxZAL) | |
57871462 | 5810 | |
630b122b | 5811 | if(dops[i].ooo) { |
5812 | s1l=get_reg(branch_regs[i].regmap,dops[i].rs1); | |
57871462 | 5813 | } |
5814 | else { | |
630b122b | 5815 | s1l=get_reg(i_regmap,dops[i].rs1); |
57871462 | 5816 | } |
630b122b | 5817 | if(dops[i].rs1==0) |
57871462 | 5818 | { |
630b122b | 5819 | if(dops[i].opcode2&1) unconditional=1; |
57871462 | 5820 | else nevertaken=1; |
5821 | // These are never taken (r0 is never less than zero) | |
630b122b | 5822 | //assert(dops[i].opcode2!=0); |
5823 | //assert(dops[i].opcode2!=2); | |
5824 | //assert(dops[i].opcode2!=0x10); | |
5825 | //assert(dops[i].opcode2!=0x12); | |
57871462 | 5826 | } |
5827 | ||
630b122b | 5828 | if(dops[i].ooo) { |
57871462 | 5829 | // Out of order execution (delay slot first) |
5830 | //printf("OOOE\n"); | |
5831 | address_generation(i+1,i_regs,regs[i].regmap_entry); | |
5832 | ds_assemble(i+1,i_regs); | |
5833 | int adj; | |
5834 | uint64_t bc_unneeded=branch_regs[i].u; | |
630b122b | 5835 | bc_unneeded&=~((1LL<<dops[i].rs1)|(1LL<<dops[i].rs2)); |
57871462 | 5836 | bc_unneeded|=1; |
630b122b | 5837 | wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,bc_unneeded); |
5838 | load_regs(regs[i].regmap,branch_regs[i].regmap,dops[i].rs1,dops[i].rs1); | |
e912c27d | 5839 | load_reg(regs[i].regmap,branch_regs[i].regmap,CCREG); |
630b122b | 5840 | if(dops[i].rt1==31) { |
57871462 | 5841 | int rt,return_address; |
57871462 | 5842 | rt=get_reg(branch_regs[i].regmap,31); |
5753f874 | 5843 | //assem_debug("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]); |
57871462 | 5844 | if(rt>=0) { |
5845 | // Save the PC even if the branch is not taken | |
5846 | return_address=start+i*4+8; | |
5847 | emit_movimm(return_address,rt); // PC into link register | |
5848 | #ifdef IMM_PREFETCH | |
630b122b | 5849 | if(!nevertaken) emit_prefetch(hash_table_get(return_address)); |
57871462 | 5850 | #endif |
5851 | } | |
5852 | } | |
5853 | cc=get_reg(branch_regs[i].regmap,CCREG); | |
5854 | assert(cc==HOST_CCREG); | |
9f51b4b9 | 5855 | if(unconditional) |
259dbd60 | 5856 | store_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,cinfo[i].ba); |
5857 | //do_cc(i,branch_regs[i].regmap,&adj,unconditional?cinfo[i].ba:-1,unconditional); | |
57871462 | 5858 | assem_debug("cycle count (adj)\n"); |
5859 | if(unconditional) { | |
259dbd60 | 5860 | do_cc(i,branch_regs[i].regmap,&adj,cinfo[i].ba,TAKEN,0); |
5861 | if(i!=(cinfo[i].ba-start)>>2 || source[i+1]!=0) { | |
5862 | if(adj) emit_addimm(cc, cinfo[i].ccadj + CLOCK_ADJUST(2) - adj, cc); | |
5863 | load_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,cinfo[i].ba); | |
57871462 | 5864 | if(internal) |
5865 | assem_debug("branch: internal\n"); | |
5866 | else | |
5867 | assem_debug("branch: external\n"); | |
259dbd60 | 5868 | if (internal && dops[(cinfo[i].ba - start) >> 2].is_ds) { |
57871462 | 5869 | ds_assemble_entry(i); |
5870 | } | |
5871 | else { | |
259dbd60 | 5872 | add_to_linker(out,cinfo[i].ba,internal); |
57871462 | 5873 | emit_jmp(0); |
5874 | } | |
5875 | #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK | |
5876 | if(((u_int)out)&7) emit_addnop(0); | |
5877 | #endif | |
5878 | } | |
5879 | } | |
5880 | else if(nevertaken) { | |
259dbd60 | 5881 | emit_addimm_and_set_flags(cinfo[i].ccadj + CLOCK_ADJUST(2), cc); |
630b122b | 5882 | void *jaddr=out; |
57871462 | 5883 | emit_jns(0); |
630b122b | 5884 | add_stub(CC_STUB,jaddr,out,0,i,start+i*4+8,NOTTAKEN,0); |
57871462 | 5885 | } |
5886 | else { | |
630b122b | 5887 | void *nottaken = NULL; |
57871462 | 5888 | do_cc(i,branch_regs[i].regmap,&adj,-1,0,invert); |
259dbd60 | 5889 | if(adj&&!invert) emit_addimm(cc, cinfo[i].ccadj + CLOCK_ADJUST(2) - adj, cc); |
57871462 | 5890 | { |
5891 | assert(s1l>=0); | |
3a64d2f7 | 5892 | if ((dops[i].opcode2 & 1) == 0) // BLTZ/BLTZAL |
57871462 | 5893 | { |
5894 | emit_test(s1l,s1l); | |
5895 | if(invert){ | |
630b122b | 5896 | nottaken=out; |
5897 | emit_jns(DJT_1); | |
57871462 | 5898 | }else{ |
259dbd60 | 5899 | add_to_linker(out,cinfo[i].ba,internal); |
57871462 | 5900 | emit_js(0); |
5901 | } | |
5902 | } | |
3a64d2f7 | 5903 | else // BGEZ/BGEZAL |
57871462 | 5904 | { |
5905 | emit_test(s1l,s1l); | |
5906 | if(invert){ | |
630b122b | 5907 | nottaken=out; |
5908 | emit_js(DJT_1); | |
57871462 | 5909 | }else{ |
259dbd60 | 5910 | add_to_linker(out,cinfo[i].ba,internal); |
57871462 | 5911 | emit_jns(0); |
5912 | } | |
5913 | } | |
57871462 | 5914 | } |
9f51b4b9 | 5915 | |
57871462 | 5916 | if(invert) { |
57871462 | 5917 | #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK |
259dbd60 | 5918 | if (match && (!internal || !dops[(cinfo[i].ba - start) >> 2].is_ds)) { |
630b122b | 5919 | if(adj) { |
5920 | emit_addimm(cc,-adj,cc); | |
259dbd60 | 5921 | add_to_linker(out,cinfo[i].ba,internal); |
630b122b | 5922 | }else{ |
5923 | emit_addnop(13); | |
259dbd60 | 5924 | add_to_linker(out,cinfo[i].ba,internal*2); |
630b122b | 5925 | } |
57871462 | 5926 | emit_jmp(0); |
630b122b | 5927 | }else |
5928 | #endif | |
5929 | { | |
5930 | if(adj) emit_addimm(cc,-adj,cc); | |
259dbd60 | 5931 | store_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,cinfo[i].ba); |
5932 | load_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,cinfo[i].ba); | |
630b122b | 5933 | if(internal) |
5934 | assem_debug("branch: internal\n"); | |
5935 | else | |
5936 | assem_debug("branch: external\n"); | |
259dbd60 | 5937 | if (internal && dops[(cinfo[i].ba - start) >> 2].is_ds) { |
630b122b | 5938 | ds_assemble_entry(i); |
5939 | } | |
5940 | else { | |
259dbd60 | 5941 | add_to_linker(out,cinfo[i].ba,internal); |
630b122b | 5942 | emit_jmp(0); |
5943 | } | |
57871462 | 5944 | } |
630b122b | 5945 | set_jump_target(nottaken, out); |
57871462 | 5946 | } |
5947 | ||
5948 | if(adj) { | |
630b122b | 5949 | if(!invert) emit_addimm(cc,adj,cc); |
57871462 | 5950 | } |
5951 | } // (!unconditional) | |
5952 | } // if(ooo) | |
5953 | else | |
5954 | { | |
5955 | // In-order execution (branch first) | |
5956 | //printf("IOE\n"); | |
630b122b | 5957 | void *nottaken = NULL; |
5753f874 | 5958 | if (!unconditional && !nevertaken) { |
3a64d2f7 | 5959 | assert(s1l >= 0); |
5960 | emit_test(s1l, s1l); | |
5961 | } | |
5962 | if (dops[i].rt1 == 31) { | |
5963 | int rt, return_address; | |
5964 | rt = get_reg(branch_regs[i].regmap,31); | |
5965 | if(rt >= 0) { | |
630b122b | 5966 | // Save the PC even if the branch is not taken |
3a64d2f7 | 5967 | return_address = start + i*4+8; |
5968 | emit_movimm(return_address, rt); // PC into link register | |
630b122b | 5969 | #ifdef IMM_PREFETCH |
5970 | emit_prefetch(hash_table_get(return_address)); | |
5971 | #endif | |
5972 | } | |
5973 | } | |
5753f874 | 5974 | if (!unconditional && !nevertaken) { |
3a64d2f7 | 5975 | nottaken = out; |
5976 | if (!(dops[i].opcode2 & 1)) // BLTZ/BLTZAL | |
5977 | emit_jns(DJT_1); | |
5978 | else // BGEZ/BGEZAL | |
5979 | emit_js(DJT_1); | |
5980 | } | |
57871462 | 5981 | int adj; |
5982 | uint64_t ds_unneeded=branch_regs[i].u; | |
630b122b | 5983 | ds_unneeded&=~((1LL<<dops[i+1].rs1)|(1LL<<dops[i+1].rs2)); |
57871462 | 5984 | ds_unneeded|=1; |
57871462 | 5985 | // branch taken |
630b122b | 5986 | if(!nevertaken) { |
5987 | //assem_debug("1:\n"); | |
5988 | wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,ds_unneeded); | |
5989 | // load regs | |
5990 | load_regs(regs[i].regmap,branch_regs[i].regmap,dops[i+1].rs1,dops[i+1].rs2); | |
5991 | address_generation(i+1,&branch_regs[i],0); | |
5992 | if (ram_offset) | |
e912c27d | 5993 | load_reg(regs[i].regmap,branch_regs[i].regmap,ROREG); |
630b122b | 5994 | load_regs(regs[i].regmap,branch_regs[i].regmap,CCREG,INVCP); |
5995 | ds_assemble(i+1,&branch_regs[i]); | |
5996 | cc=get_reg(branch_regs[i].regmap,CCREG); | |
5997 | if(cc==-1) { | |
5998 | emit_loadreg(CCREG,cc=HOST_CCREG); | |
5999 | // CHECK: Is the following instruction (fall thru) allocated ok? | |
6000 | } | |
6001 | assert(cc==HOST_CCREG); | |
259dbd60 | 6002 | store_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,cinfo[i].ba); |
6003 | do_cc(i,i_regmap,&adj,cinfo[i].ba,TAKEN,0); | |
630b122b | 6004 | assem_debug("cycle count (adj)\n"); |
259dbd60 | 6005 | if(adj) emit_addimm(cc, cinfo[i].ccadj + CLOCK_ADJUST(2) - adj, cc); |
6006 | load_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,cinfo[i].ba); | |
630b122b | 6007 | if(internal) |
6008 | assem_debug("branch: internal\n"); | |
6009 | else | |
6010 | assem_debug("branch: external\n"); | |
259dbd60 | 6011 | if (internal && dops[(cinfo[i].ba - start) >> 2].is_ds) { |
630b122b | 6012 | ds_assemble_entry(i); |
6013 | } | |
6014 | else { | |
259dbd60 | 6015 | add_to_linker(out,cinfo[i].ba,internal); |
630b122b | 6016 | emit_jmp(0); |
6017 | } | |
57871462 | 6018 | } |
57871462 | 6019 | // branch not taken |
630b122b | 6020 | if(!unconditional) { |
5753f874 | 6021 | if (!nevertaken) { |
6022 | assert(nottaken); | |
6023 | set_jump_target(nottaken, out); | |
6024 | } | |
57871462 | 6025 | assem_debug("1:\n"); |
630b122b | 6026 | wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,ds_unneeded); |
6027 | load_regs(regs[i].regmap,branch_regs[i].regmap,dops[i+1].rs1,dops[i+1].rs2); | |
6028 | address_generation(i+1,&branch_regs[i],0); | |
dfe6947f | 6029 | if (ram_offset) |
e912c27d | 6030 | load_reg(regs[i].regmap,branch_regs[i].regmap,ROREG); |
dfe6947f | 6031 | load_regs(regs[i].regmap,branch_regs[i].regmap,CCREG,INVCP); |
630b122b | 6032 | ds_assemble(i+1,&branch_regs[i]); |
57871462 | 6033 | cc=get_reg(branch_regs[i].regmap,CCREG); |
630b122b | 6034 | if (cc == -1) { |
57871462 | 6035 | // Cycle count isn't in a register, temporarily load it then write it out |
6036 | emit_loadreg(CCREG,HOST_CCREG); | |
259dbd60 | 6037 | emit_addimm_and_set_flags(cinfo[i].ccadj + CLOCK_ADJUST(2), HOST_CCREG); |
630b122b | 6038 | void *jaddr=out; |
57871462 | 6039 | emit_jns(0); |
630b122b | 6040 | add_stub(CC_STUB,jaddr,out,0,i,start+i*4+8,NOTTAKEN,0); |
57871462 | 6041 | emit_storereg(CCREG,HOST_CCREG); |
6042 | } | |
6043 | else{ | |
6044 | cc=get_reg(i_regmap,CCREG); | |
6045 | assert(cc==HOST_CCREG); | |
259dbd60 | 6046 | emit_addimm_and_set_flags(cinfo[i].ccadj + CLOCK_ADJUST(2), cc); |
630b122b | 6047 | void *jaddr=out; |
57871462 | 6048 | emit_jns(0); |
630b122b | 6049 | add_stub(CC_STUB,jaddr,out,0,i,start+i*4+8,NOTTAKEN,0); |
57871462 | 6050 | } |
6051 | } | |
6052 | } | |
6053 | } | |
6054 | ||
648d9448 | 6055 | static void check_regmap(signed char *regmap) |
6056 | { | |
6057 | #ifndef NDEBUG | |
6058 | int i,j; | |
6059 | for (i = 0; i < HOST_REGS; i++) { | |
6060 | if (regmap[i] < 0) | |
6061 | continue; | |
6062 | for (j = i + 1; j < HOST_REGS; j++) | |
6063 | assert(regmap[i] != regmap[j]); | |
6064 | } | |
6065 | #endif | |
6066 | } | |
6067 | ||
4600ba03 | 6068 | #ifdef DISASM |
fdf33825 | 6069 | #include <inttypes.h> |
ed14d777 | 6070 | static char insn[MAXBLOCK][10]; |
6071 | ||
6072 | #define set_mnemonic(i_, n_) \ | |
6073 | strcpy(insn[i_], n_) | |
6074 | ||
fdf33825 | 6075 | void print_regmap(const char *name, const signed char *regmap) |
6076 | { | |
6077 | char buf[5]; | |
6078 | int i, l; | |
6079 | fputs(name, stdout); | |
6080 | for (i = 0; i < HOST_REGS; i++) { | |
6081 | l = 0; | |
6082 | if (regmap[i] >= 0) | |
6083 | l = snprintf(buf, sizeof(buf), "$%d", regmap[i]); | |
6084 | for (; l < 3; l++) | |
6085 | buf[l] = ' '; | |
6086 | buf[l] = 0; | |
6087 | printf(" r%d=%s", i, buf); | |
6088 | } | |
6089 | fputs("\n", stdout); | |
6090 | } | |
6091 | ||
57871462 | 6092 | /* disassembly */ |
6093 | void disassemble_inst(int i) | |
6094 | { | |
630b122b | 6095 | if (dops[i].bt) printf("*"); else printf(" "); |
6096 | switch(dops[i].itype) { | |
57871462 | 6097 | case UJUMP: |
259dbd60 | 6098 | printf (" %x: %s %8x\n",start+i*4,insn[i],cinfo[i].ba);break; |
57871462 | 6099 | case CJUMP: |
259dbd60 | 6100 | printf (" %x: %s r%d,r%d,%8x\n",start+i*4,insn[i],dops[i].rs1,dops[i].rs2,i?start+i*4+4+((signed int)((unsigned int)source[i]<<16)>>14):cinfo[i].ba);break; |
57871462 | 6101 | case SJUMP: |
630b122b | 6102 | printf (" %x: %s r%d,%8x\n",start+i*4,insn[i],dops[i].rs1,start+i*4+4+((signed int)((unsigned int)source[i]<<16)>>14));break; |
57871462 | 6103 | case RJUMP: |
3a64d2f7 | 6104 | if (dops[i].opcode2 == 9 && dops[i].rt1 != 31) |
630b122b | 6105 | printf (" %x: %s r%d,r%d\n",start+i*4,insn[i],dops[i].rt1,dops[i].rs1); |
5067f341 | 6106 | else |
630b122b | 6107 | printf (" %x: %s r%d\n",start+i*4,insn[i],dops[i].rs1); |
5067f341 | 6108 | break; |
57871462 | 6109 | case IMM16: |
630b122b | 6110 | if(dops[i].opcode==0xf) //LUI |
259dbd60 | 6111 | printf (" %x: %s r%d,%4x0000\n",start+i*4,insn[i],dops[i].rt1,cinfo[i].imm&0xffff); |
57871462 | 6112 | else |
259dbd60 | 6113 | printf (" %x: %s r%d,r%d,%d\n",start+i*4,insn[i],dops[i].rt1,dops[i].rs1,cinfo[i].imm); |
57871462 | 6114 | break; |
6115 | case LOAD: | |
6116 | case LOADLR: | |
259dbd60 | 6117 | printf (" %x: %s r%d,r%d+%x\n",start+i*4,insn[i],dops[i].rt1,dops[i].rs1,cinfo[i].imm); |
57871462 | 6118 | break; |
6119 | case STORE: | |
6120 | case STORELR: | |
259dbd60 | 6121 | printf (" %x: %s r%d,r%d+%x\n",start+i*4,insn[i],dops[i].rs2,dops[i].rs1,cinfo[i].imm); |
57871462 | 6122 | break; |
6123 | case ALU: | |
6124 | case SHIFT: | |
630b122b | 6125 | printf (" %x: %s r%d,r%d,r%d\n",start+i*4,insn[i],dops[i].rt1,dops[i].rs1,dops[i].rs2); |
57871462 | 6126 | break; |
6127 | case MULTDIV: | |
630b122b | 6128 | printf (" %x: %s r%d,r%d\n",start+i*4,insn[i],dops[i].rs1,dops[i].rs2); |
57871462 | 6129 | break; |
6130 | case SHIFTIMM: | |
259dbd60 | 6131 | printf (" %x: %s r%d,r%d,%d\n",start+i*4,insn[i],dops[i].rt1,dops[i].rs1,cinfo[i].imm); |
57871462 | 6132 | break; |
6133 | case MOV: | |
630b122b | 6134 | if((dops[i].opcode2&0x1d)==0x10) |
6135 | printf (" %x: %s r%d\n",start+i*4,insn[i],dops[i].rt1); | |
6136 | else if((dops[i].opcode2&0x1d)==0x11) | |
6137 | printf (" %x: %s r%d\n",start+i*4,insn[i],dops[i].rs1); | |
57871462 | 6138 | else |
6139 | printf (" %x: %s\n",start+i*4,insn[i]); | |
6140 | break; | |
6141 | case COP0: | |
630b122b | 6142 | if(dops[i].opcode2==0) |
6143 | printf (" %x: %s r%d,cpr0[%d]\n",start+i*4,insn[i],dops[i].rt1,(source[i]>>11)&0x1f); // MFC0 | |
6144 | else if(dops[i].opcode2==4) | |
6145 | printf (" %x: %s r%d,cpr0[%d]\n",start+i*4,insn[i],dops[i].rs1,(source[i]>>11)&0x1f); // MTC0 | |
57871462 | 6146 | else printf (" %x: %s\n",start+i*4,insn[i]); |
6147 | break; | |
b9b61529 | 6148 | case COP2: |
630b122b | 6149 | if(dops[i].opcode2<3) |
6150 | printf (" %x: %s r%d,cpr2[%d]\n",start+i*4,insn[i],dops[i].rt1,(source[i]>>11)&0x1f); // MFC2 | |
6151 | else if(dops[i].opcode2>3) | |
6152 | printf (" %x: %s r%d,cpr2[%d]\n",start+i*4,insn[i],dops[i].rs1,(source[i]>>11)&0x1f); // MTC2 | |
b9b61529 | 6153 | else printf (" %x: %s\n",start+i*4,insn[i]); |
6154 | break; | |
b9b61529 | 6155 | case C2LS: |
259dbd60 | 6156 | printf (" %x: %s cpr2[%d],r%d+%x\n",start+i*4,insn[i],(source[i]>>16)&0x1f,dops[i].rs1,cinfo[i].imm); |
b9b61529 | 6157 | break; |
1e973cb0 | 6158 | case INTCALL: |
6159 | printf (" %x: %s (INTCALL)\n",start+i*4,insn[i]); | |
6160 | break; | |
57871462 | 6161 | default: |
6162 | //printf (" %s %8x\n",insn[i],source[i]); | |
6163 | printf (" %x: %s\n",start+i*4,insn[i]); | |
6164 | } | |
f2e25348 | 6165 | #ifndef REGMAP_PRINT |
fdf33825 | 6166 | return; |
f2e25348 | 6167 | #endif |
e6e590d3 | 6168 | printf("D: %x WD: %x U: %"PRIx64" hC: %x hWC: %x hLC: %x\n", |
f2e25348 | 6169 | regs[i].dirty, regs[i].wasdirty, unneeded_reg[i], |
6170 | regs[i].isconst, regs[i].wasconst, regs[i].loadedconst); | |
fdf33825 | 6171 | print_regmap("pre: ", regmap_pre[i]); |
6172 | print_regmap("entry: ", regs[i].regmap_entry); | |
6173 | print_regmap("map: ", regs[i].regmap); | |
6174 | if (dops[i].is_jump) { | |
6175 | print_regmap("bentry:", branch_regs[i].regmap_entry); | |
6176 | print_regmap("bmap: ", branch_regs[i].regmap); | |
6177 | } | |
57871462 | 6178 | } |
4600ba03 | 6179 | #else |
ed14d777 | 6180 | #define set_mnemonic(i_, n_) |
4600ba03 | 6181 | static void disassemble_inst(int i) {} |
6182 | #endif // DISASM | |
57871462 | 6183 | |
d848b60a | 6184 | #define DRC_TEST_VAL 0x74657374 |
6185 | ||
7f9e081d | 6186 | static noinline void new_dynarec_test(void) |
d848b60a | 6187 | { |
630b122b | 6188 | int (*testfunc)(void); |
d148d265 | 6189 | void *beginning; |
630b122b | 6190 | int ret[2]; |
6191 | size_t i; | |
d148d265 | 6192 | |
630b122b | 6193 | // check structure linkage |
6194 | if ((u_char *)rcnts - (u_char *)&psxRegs != sizeof(psxRegs)) | |
6195 | { | |
6196 | SysPrintf("linkage_arm* miscompilation/breakage detected.\n"); | |
6197 | } | |
6198 | ||
7f9e081d | 6199 | SysPrintf("(%p) testing if we can run recompiled code @%p...\n", |
6200 | new_dynarec_test, out); | |
6201 | ((volatile u_int *)NDRC_WRITE_OFFSET(out))[0]++; // make the cache dirty | |
630b122b | 6202 | |
6203 | for (i = 0; i < ARRAY_SIZE(ret); i++) { | |
6204 | out = ndrc->translation_cache; | |
6205 | beginning = start_block(); | |
6206 | emit_movimm(DRC_TEST_VAL + i, 0); // test | |
6207 | emit_ret(); | |
6208 | literal_pool(0); | |
6209 | end_block(beginning); | |
6210 | testfunc = beginning; | |
6211 | ret[i] = testfunc(); | |
6212 | } | |
6213 | ||
6214 | if (ret[0] == DRC_TEST_VAL && ret[1] == DRC_TEST_VAL + 1) | |
d848b60a | 6215 | SysPrintf("test passed.\n"); |
6216 | else | |
630b122b | 6217 | SysPrintf("test failed, will likely crash soon (r=%08x %08x)\n", ret[0], ret[1]); |
6218 | out = ndrc->translation_cache; | |
d848b60a | 6219 | } |
6220 | ||
b6cd25ed | 6221 | static int get_cycle_multiplier(void) |
6222 | { | |
6223 | return Config.cycle_multiplier_override && Config.cycle_multiplier == CYCLE_MULT_DEFAULT | |
6224 | ? Config.cycle_multiplier_override : Config.cycle_multiplier; | |
6225 | } | |
6226 | ||
dc990066 | 6227 | // clear the state completely, instead of just marking |
6228 | // things invalid like invalidate_all_pages() does | |
92d79826 | 6229 | void new_dynarec_clear_full(void) |
57871462 | 6230 | { |
57871462 | 6231 | int n; |
630b122b | 6232 | out = ndrc->translation_cache; |
35775df7 | 6233 | memset(invalid_code,1,sizeof(invalid_code)); |
dc990066 | 6234 | memset(shadow,0,sizeof(shadow)); |
c980be0e | 6235 | hash_table_clear(); |
6236 | mini_ht_clear(); | |
57871462 | 6237 | copy=shadow; |
432435ea | 6238 | expirep = EXPIRITY_OFFSET; |
57871462 | 6239 | pending_exception=0; |
6240 | literalcount=0; | |
57871462 | 6241 | stop_after_jal=0; |
9be4ba64 | 6242 | inv_code_start=inv_code_end=~0; |
7c8454e3 | 6243 | hack_addr=0; |
630b122b | 6244 | f1_hack=0; |
432435ea | 6245 | for (n = 0; n < ARRAY_SIZE(blocks); n++) |
6246 | blocks_clear(&blocks[n]); | |
366d1d2b | 6247 | for (n = 0; n < ARRAY_SIZE(jumps); n++) { |
6248 | free(jumps[n]); | |
6249 | jumps[n] = NULL; | |
6250 | } | |
048fcced | 6251 | stat_clear(stat_blocks); |
6252 | stat_clear(stat_links); | |
630b122b | 6253 | |
b6cd25ed | 6254 | if (cycle_multiplier_old != Config.cycle_multiplier |
6255 | || new_dynarec_hacks_old != new_dynarec_hacks) | |
6256 | { | |
6257 | SysPrintf("ndrc config: mul=%d, ha=%x, pex=%d\n", | |
6258 | get_cycle_multiplier(), new_dynarec_hacks, Config.PreciseExceptions); | |
6259 | } | |
1562ed57 | 6260 | cycle_multiplier_old = Config.cycle_multiplier; |
630b122b | 6261 | new_dynarec_hacks_old = new_dynarec_hacks; |
dc990066 | 6262 | } |
6263 | ||
7ef2f1f7 | 6264 | static int pgsize(void) |
6265 | { | |
dcbfae8a | 6266 | long ret = -1; |
7ef2f1f7 | 6267 | #ifdef _SC_PAGESIZE |
dcbfae8a | 6268 | ret = sysconf(_SC_PAGESIZE); |
7ef2f1f7 | 6269 | #endif |
dcbfae8a | 6270 | if (ret < 1) |
6271 | ret = 4096; | |
6272 | return ret; | |
7ef2f1f7 | 6273 | } |
6274 | ||
92d79826 | 6275 | void new_dynarec_init(void) |
dc990066 | 6276 | { |
7ef2f1f7 | 6277 | int align = pgsize() - 1; |
6278 | SysPrintf("Init new dynarec, ndrc size %x, pgsize %d\n", | |
6279 | (int)sizeof(*ndrc), align + 1); | |
1e212a25 | 6280 | |
4666f75d | 6281 | #ifdef _3DS |
6282 | check_rosalina(); | |
6283 | #endif | |
630b122b | 6284 | #ifdef BASE_ADDR_DYNAMIC |
6285 | #ifdef VITA | |
4666f75d | 6286 | sceBlock = getVMBlock(); //sceKernelAllocMemBlockForVM("code", sizeof(*ndrc)); |
ab51e9e2 | 6287 | if (sceBlock <= 0) |
6288 | SysPrintf("sceKernelAllocMemBlockForVM failed: %x\n", sceBlock); | |
630b122b | 6289 | int ret = sceKernelGetMemBlockBase(sceBlock, (void **)&ndrc); |
1e212a25 | 6290 | if (ret < 0) |
ab51e9e2 | 6291 | SysPrintf("sceKernelGetMemBlockBase failed: %x\n", ret); |
4666f75d | 6292 | sceKernelOpenVMDomain(); |
6293 | sceClibPrintf("translation_cache = 0x%08lx\n ", (long)ndrc->translation_cache); | |
6294 | #elif defined(_MSC_VER) | |
6295 | ndrc = VirtualAlloc(NULL, sizeof(*ndrc), MEM_COMMIT | MEM_RESERVE, | |
6296 | PAGE_EXECUTE_READWRITE); | |
7c404fb9 | 6297 | #elif defined(HAVE_LIBNX) |
6298 | Result rc = jitCreate(&g_jit, sizeof(*ndrc)); | |
6299 | if (R_FAILED(rc)) | |
6300 | SysPrintf("jitCreate failed: %08x\n", rc); | |
6301 | SysPrintf("jitCreate: RX: %p RW: %p type: %d\n", g_jit.rx_addr, g_jit.rw_addr, g_jit.type); | |
7f9e081d | 6302 | jitTransitionToWritable(&g_jit); |
7c404fb9 | 6303 | ndrc = g_jit.rx_addr; |
6304 | ndrc_write_ofs = (char *)g_jit.rw_addr - (char *)ndrc; | |
7f9e081d | 6305 | memset(NDRC_WRITE_OFFSET(&ndrc->tramp), 0, sizeof(ndrc->tramp)); |
630b122b | 6306 | #else |
6307 | uintptr_t desired_addr = 0; | |
7c404fb9 | 6308 | int prot = PROT_READ | PROT_WRITE | PROT_EXEC; |
6309 | int flags = MAP_PRIVATE | MAP_ANONYMOUS; | |
6310 | int fd = -1; | |
630b122b | 6311 | #ifdef __ELF__ |
6312 | extern char _end; | |
6313 | desired_addr = ((uintptr_t)&_end + 0xffffff) & ~0xffffffl; | |
6314 | #endif | |
7f9e081d | 6315 | #ifdef TC_WRITE_OFFSET |
7c404fb9 | 6316 | // mostly for testing |
6317 | fd = open("/dev/shm/pcsxr", O_CREAT | O_RDWR, 0600); | |
6318 | ftruncate(fd, sizeof(*ndrc)); | |
6319 | void *mw = mmap(NULL, sizeof(*ndrc), PROT_READ | PROT_WRITE, | |
6320 | (flags = MAP_SHARED), fd, 0); | |
6321 | assert(mw != MAP_FAILED); | |
6322 | prot = PROT_READ | PROT_EXEC; | |
6323 | #endif | |
6324 | ndrc = mmap((void *)desired_addr, sizeof(*ndrc), prot, flags, fd, 0); | |
630b122b | 6325 | if (ndrc == MAP_FAILED) { |
d848b60a | 6326 | SysPrintf("mmap() failed: %s\n", strerror(errno)); |
1e212a25 | 6327 | abort(); |
d848b60a | 6328 | } |
7f9e081d | 6329 | #ifdef TC_WRITE_OFFSET |
7c404fb9 | 6330 | ndrc_write_ofs = (char *)mw - (char *)ndrc; |
6331 | #endif | |
630b122b | 6332 | #endif |
1e212a25 | 6333 | #else |
630b122b | 6334 | #ifndef NO_WRITE_EXEC |
7ef2f1f7 | 6335 | ndrc = (struct ndrc_mem *)((size_t)(ndrc_bss + align) & ~align); |
bdeade46 | 6336 | // not all systems allow execute in data segment by default |
f8a8da84 | 6337 | // size must be 4K aligned for 3DS? |
6338 | if (mprotect(ndrc, sizeof(*ndrc), | |
630b122b | 6339 | PROT_READ | PROT_WRITE | PROT_EXEC) != 0) |
7ef2f1f7 | 6340 | SysPrintf("mprotect(%p) failed: %s\n", ndrc, strerror(errno)); |
630b122b | 6341 | #endif |
dc990066 | 6342 | #endif |
630b122b | 6343 | out = ndrc->translation_cache; |
dc990066 | 6344 | new_dynarec_clear_full(); |
6345 | #ifdef HOST_IMM8 | |
6346 | // Copy this into local area so we don't have to put it in every literal pool | |
6347 | invc_ptr=invalid_code; | |
6348 | #endif | |
57871462 | 6349 | arch_init(); |
d848b60a | 6350 | new_dynarec_test(); |
e6e590d3 | 6351 | ram_offset = (uintptr_t)psxM - 0x80000000; |
b105cf4f | 6352 | if (ram_offset!=0) |
c43b5311 | 6353 | SysPrintf("warning: RAM is not directly mapped, performance will suffer\n"); |
bfdecce3 | 6354 | SysPrintf("Mapped (RAM/scrp/ROM/LUTs/TC):\n"); |
6355 | SysPrintf("%p/%p/%p/%p/%p\n", psxM, psxH, psxR, mem_rtab, out); | |
57871462 | 6356 | } |
6357 | ||
92d79826 | 6358 | void new_dynarec_cleanup(void) |
57871462 | 6359 | { |
6360 | int n; | |
630b122b | 6361 | #ifdef BASE_ADDR_DYNAMIC |
6362 | #ifdef VITA | |
ab51e9e2 | 6363 | // sceBlock is managed by retroarch's bootstrap code |
af4a16ff | 6364 | //sceKernelFreeMemBlock(sceBlock); |
6365 | //sceBlock = -1; | |
7c404fb9 | 6366 | #elif defined(HAVE_LIBNX) |
6367 | jitClose(&g_jit); | |
6368 | ndrc = NULL; | |
630b122b | 6369 | #else |
6370 | if (munmap(ndrc, sizeof(*ndrc)) < 0) | |
1e212a25 | 6371 | SysPrintf("munmap() failed\n"); |
7c404fb9 | 6372 | ndrc = NULL; |
630b122b | 6373 | #endif |
1e212a25 | 6374 | #endif |
432435ea | 6375 | for (n = 0; n < ARRAY_SIZE(blocks); n++) |
6376 | blocks_clear(&blocks[n]); | |
366d1d2b | 6377 | for (n = 0; n < ARRAY_SIZE(jumps); n++) { |
6378 | free(jumps[n]); | |
6379 | jumps[n] = NULL; | |
6380 | } | |
048fcced | 6381 | stat_clear(stat_blocks); |
6382 | stat_clear(stat_links); | |
55cadc36 | 6383 | new_dynarec_print_stats(); |
57871462 | 6384 | } |
6385 | ||
03f55e6b | 6386 | static u_int *get_source_start(u_int addr, u_int *limit) |
57871462 | 6387 | { |
e6e590d3 | 6388 | if (addr < 0x00800000 |
6389 | || (0x80000000 <= addr && addr < 0x80800000) | |
6390 | || (0xa0000000 <= addr && addr < 0xa0800000)) | |
630b122b | 6391 | { |
03f55e6b | 6392 | // used for BIOS calls mostly? |
e6e590d3 | 6393 | *limit = (addr & 0xa0600000) + 0x00200000; |
6394 | return (u_int *)(psxM + (addr & 0x1fffff)); | |
03f55e6b | 6395 | } |
ab12e5dc | 6396 | else if ( |
03f55e6b | 6397 | /* (0x9fc00000 <= addr && addr < 0x9fc80000) ||*/ |
ab12e5dc | 6398 | (0xbfc00000 <= addr && addr < 0xbfc80000)) |
630b122b | 6399 | { |
6400 | // BIOS. The multiplier should be much higher as it's uncached 8bit mem, | |
1562ed57 | 6401 | // but timings in PCSX are too tied to the interpreter's 2-per-insn assumption |
630b122b | 6402 | if (!HACK_ENABLED(NDHACK_OVERRIDE_CYCLE_M)) |
6403 | cycle_multiplier_active = 200; | |
6404 | ||
03f55e6b | 6405 | *limit = (addr & 0xfff00000) | 0x80000; |
630b122b | 6406 | return (u_int *)((u_char *)psxR + (addr&0x7ffff)); |
03f55e6b | 6407 | } |
581335b0 | 6408 | return NULL; |
03f55e6b | 6409 | } |
6410 | ||
6411 | static u_int scan_for_ret(u_int addr) | |
6412 | { | |
6413 | u_int limit = 0; | |
6414 | u_int *mem; | |
6415 | ||
6416 | mem = get_source_start(addr, &limit); | |
6417 | if (mem == NULL) | |
6418 | return addr; | |
6419 | ||
6420 | if (limit > addr + 0x1000) | |
6421 | limit = addr + 0x1000; | |
6422 | for (; addr < limit; addr += 4, mem++) { | |
6423 | if (*mem == 0x03e00008) // jr $ra | |
6424 | return addr + 8; | |
57871462 | 6425 | } |
581335b0 | 6426 | return addr; |
03f55e6b | 6427 | } |
6428 | ||
6429 | struct savestate_block { | |
6430 | uint32_t addr; | |
6431 | uint32_t regflags; | |
6432 | }; | |
6433 | ||
6434 | static int addr_cmp(const void *p1_, const void *p2_) | |
6435 | { | |
6436 | const struct savestate_block *p1 = p1_, *p2 = p2_; | |
6437 | return p1->addr - p2->addr; | |
6438 | } | |
6439 | ||
6440 | int new_dynarec_save_blocks(void *save, int size) | |
6441 | { | |
048fcced | 6442 | struct savestate_block *sblocks = save; |
6443 | int maxcount = size / sizeof(sblocks[0]); | |
03f55e6b | 6444 | struct savestate_block tmp_blocks[1024]; |
048fcced | 6445 | struct block_info *block; |
03f55e6b | 6446 | int p, s, d, o, bcnt; |
6447 | u_int addr; | |
6448 | ||
6449 | o = 0; | |
048fcced | 6450 | for (p = 0; p < ARRAY_SIZE(blocks); p++) { |
03f55e6b | 6451 | bcnt = 0; |
048fcced | 6452 | for (block = blocks[p]; block != NULL; block = block->next) { |
6453 | if (block->is_dirty) | |
6454 | continue; | |
6455 | tmp_blocks[bcnt].addr = block->start; | |
6456 | tmp_blocks[bcnt].regflags = block->reg_sv_flags; | |
03f55e6b | 6457 | bcnt++; |
6458 | } | |
6459 | if (bcnt < 1) | |
6460 | continue; | |
6461 | qsort(tmp_blocks, bcnt, sizeof(tmp_blocks[0]), addr_cmp); | |
6462 | ||
6463 | addr = tmp_blocks[0].addr; | |
6464 | for (s = d = 0; s < bcnt; s++) { | |
6465 | if (tmp_blocks[s].addr < addr) | |
6466 | continue; | |
6467 | if (d == 0 || tmp_blocks[d-1].addr != tmp_blocks[s].addr) | |
6468 | tmp_blocks[d++] = tmp_blocks[s]; | |
6469 | addr = scan_for_ret(tmp_blocks[s].addr); | |
6470 | } | |
6471 | ||
6472 | if (o + d > maxcount) | |
6473 | d = maxcount - o; | |
048fcced | 6474 | memcpy(&sblocks[o], tmp_blocks, d * sizeof(sblocks[0])); |
03f55e6b | 6475 | o += d; |
6476 | } | |
6477 | ||
048fcced | 6478 | return o * sizeof(sblocks[0]); |
03f55e6b | 6479 | } |
6480 | ||
6481 | void new_dynarec_load_blocks(const void *save, int size) | |
6482 | { | |
048fcced | 6483 | const struct savestate_block *sblocks = save; |
6484 | int count = size / sizeof(sblocks[0]); | |
6485 | struct block_info *block; | |
03f55e6b | 6486 | u_int regs_save[32]; |
048fcced | 6487 | u_int page; |
03f55e6b | 6488 | uint32_t f; |
6489 | int i, b; | |
6490 | ||
048fcced | 6491 | // restore clean blocks, if any |
6492 | for (page = 0, b = i = 0; page < ARRAY_SIZE(blocks); page++) { | |
6493 | for (block = blocks[page]; block != NULL; block = block->next, b++) { | |
6494 | if (!block->is_dirty) | |
6495 | continue; | |
6496 | assert(block->source && block->copy); | |
6497 | if (memcmp(block->source, block->copy, block->len)) | |
6498 | continue; | |
6499 | ||
6500 | // see try_restore_block | |
6501 | block->is_dirty = 0; | |
6502 | mark_invalid_code(block->start, block->len, 0); | |
6503 | i++; | |
6504 | } | |
6505 | } | |
6506 | inv_debug("load_blocks: %d/%d clean blocks\n", i, b); | |
03f55e6b | 6507 | |
6508 | // change GPRs for speculation to at least partially work.. | |
6509 | memcpy(regs_save, &psxRegs.GPR, sizeof(regs_save)); | |
6510 | for (i = 1; i < 32; i++) | |
6511 | psxRegs.GPR.r[i] = 0x80000000; | |
6512 | ||
6513 | for (b = 0; b < count; b++) { | |
048fcced | 6514 | for (f = sblocks[b].regflags, i = 0; f; f >>= 1, i++) { |
03f55e6b | 6515 | if (f & 1) |
6516 | psxRegs.GPR.r[i] = 0x1f800000; | |
6517 | } | |
6518 | ||
048fcced | 6519 | ndrc_get_addr_ht(sblocks[b].addr); |
03f55e6b | 6520 | |
048fcced | 6521 | for (f = sblocks[b].regflags, i = 0; f; f >>= 1, i++) { |
03f55e6b | 6522 | if (f & 1) |
6523 | psxRegs.GPR.r[i] = 0x80000000; | |
6524 | } | |
6525 | } | |
6526 | ||
6527 | memcpy(&psxRegs.GPR, regs_save, sizeof(regs_save)); | |
6528 | } | |
6529 | ||
55cadc36 | 6530 | void new_dynarec_print_stats(void) |
6531 | { | |
6532 | #ifdef STAT_PRINT | |
048fcced | 6533 | printf("cc %3d,%3d,%3d lu%6d,%3d,%3d c%3d inv%3d,%3d tc_offs %zu b %u,%u\n", |
55cadc36 | 6534 | stat_bc_pre, stat_bc_direct, stat_bc_restore, |
048fcced | 6535 | stat_ht_lookups, stat_jump_in_lookups, stat_restore_tries, |
6536 | stat_restore_compares, stat_inv_addr_calls, stat_inv_hits, | |
6537 | out - ndrc->translation_cache, stat_blocks, stat_links); | |
55cadc36 | 6538 | stat_bc_direct = stat_bc_pre = stat_bc_restore = |
048fcced | 6539 | stat_ht_lookups = stat_jump_in_lookups = stat_restore_tries = |
6540 | stat_restore_compares = stat_inv_addr_calls = stat_inv_hits = 0; | |
55cadc36 | 6541 | #endif |
6542 | } | |
6543 | ||
584fc319 | 6544 | static void force_intcall(int i) |
6545 | { | |
6546 | memset(&dops[i], 0, sizeof(dops[i])); | |
6547 | dops[i].itype = INTCALL; | |
6548 | dops[i].rs1 = CCREG; | |
6549 | dops[i].is_exception = 1; | |
6550 | cinfo[i].ba = -1; | |
6551 | } | |
6552 | ||
7c8454e3 | 6553 | static int apply_hacks(void) |
630b122b | 6554 | { |
6555 | int i; | |
6556 | if (HACK_ENABLED(NDHACK_NO_COMPAT_HACKS)) | |
7c8454e3 | 6557 | return 0; |
630b122b | 6558 | /* special hack(s) */ |
6559 | for (i = 0; i < slen - 4; i++) | |
6560 | { | |
6561 | // lui a4, 0xf200; jal <rcnt_read>; addu a0, 2; slti v0, 28224 | |
6562 | if (source[i] == 0x3c04f200 && dops[i+1].itype == UJUMP | |
6563 | && source[i+2] == 0x34840002 && dops[i+3].opcode == 0x0a | |
259dbd60 | 6564 | && cinfo[i+3].imm == 0x6e40 && dops[i+3].rs1 == 2) |
630b122b | 6565 | { |
6566 | SysPrintf("PE2 hack @%08x\n", start + (i+3)*4); | |
6567 | dops[i + 3].itype = NOP; | |
6568 | } | |
6569 | } | |
6570 | i = slen; | |
6571 | if (i > 10 && source[i-1] == 0 && source[i-2] == 0x03e00008 | |
6572 | && source[i-4] == 0x8fbf0018 && source[i-6] == 0x00c0f809 | |
6573 | && dops[i-7].itype == STORE) | |
6574 | { | |
6575 | i = i-8; | |
6576 | if (dops[i].itype == IMM16) | |
6577 | i--; | |
6578 | // swl r2, 15(r6); swr r2, 12(r6); sw r6, *; jalr r6 | |
6579 | if (dops[i].itype == STORELR && dops[i].rs1 == 6 | |
6580 | && dops[i-1].itype == STORELR && dops[i-1].rs1 == 6) | |
6581 | { | |
7c8454e3 | 6582 | SysPrintf("F1 hack from %08x, old dst %08x\n", start, hack_addr); |
6583 | f1_hack = 1; | |
6584 | return 1; | |
630b122b | 6585 | } |
6586 | } | |
584fc319 | 6587 | if (Config.HLE) |
6588 | { | |
6589 | if (start <= psxRegs.biosBranchCheck && psxRegs.biosBranchCheck < start + i*4) | |
6590 | { | |
6591 | i = (psxRegs.biosBranchCheck - start) / 4u + 23; | |
6592 | if (dops[i].is_jump && !dops[i+1].bt) | |
6593 | { | |
6594 | force_intcall(i); | |
6595 | dops[i+1].is_ds = 0; | |
6596 | } | |
6597 | } | |
6598 | } | |
7c8454e3 | 6599 | return 0; |
630b122b | 6600 | } |
6601 | ||
06d32d29 | 6602 | static int is_ld_use_hazard(const struct decoded_insn *op_ld, |
6603 | const struct decoded_insn *op) | |
03f55e6b | 6604 | { |
06d32d29 | 6605 | if (op_ld->rt1 == 0 || (op_ld->rt1 != op->rs1 && op_ld->rt1 != op->rs2)) |
6606 | return 0; | |
6607 | if (op_ld->itype == LOADLR && op->itype == LOADLR) | |
6608 | return op_ld->rt1 == op_ld->rs1; | |
6609 | return op->itype != CJUMP && op->itype != SJUMP; | |
5753f874 | 6610 | } |
57871462 | 6611 | |
5753f874 | 6612 | static void disassemble_one(int i, u_int src) |
6613 | { | |
6614 | unsigned int type, op, op2, op3; | |
a3c5fc39 | 6615 | enum ls_width_type ls_type = LS_32; |
447f5a1d | 6616 | memset(&dops[i], 0, sizeof(dops[i])); |
259dbd60 | 6617 | memset(&cinfo[i], 0, sizeof(cinfo[i])); |
6618 | cinfo[i].ba = -1; | |
6619 | cinfo[i].addr = -1; | |
5753f874 | 6620 | dops[i].opcode = op = src >> 26; |
259dbd60 | 6621 | op2 = 0; |
f2e25348 | 6622 | type = INTCALL; |
6623 | set_mnemonic(i, "???"); | |
57871462 | 6624 | switch(op) |
6625 | { | |
f2e25348 | 6626 | case 0x00: set_mnemonic(i, "special"); |
5753f874 | 6627 | op2 = src & 0x3f; |
57871462 | 6628 | switch(op2) |
6629 | { | |
ed14d777 | 6630 | case 0x00: set_mnemonic(i, "SLL"); type=SHIFTIMM; break; |
6631 | case 0x02: set_mnemonic(i, "SRL"); type=SHIFTIMM; break; | |
6632 | case 0x03: set_mnemonic(i, "SRA"); type=SHIFTIMM; break; | |
6633 | case 0x04: set_mnemonic(i, "SLLV"); type=SHIFT; break; | |
6634 | case 0x06: set_mnemonic(i, "SRLV"); type=SHIFT; break; | |
6635 | case 0x07: set_mnemonic(i, "SRAV"); type=SHIFT; break; | |
6636 | case 0x08: set_mnemonic(i, "JR"); type=RJUMP; break; | |
6637 | case 0x09: set_mnemonic(i, "JALR"); type=RJUMP; break; | |
6638 | case 0x0C: set_mnemonic(i, "SYSCALL"); type=SYSCALL; break; | |
6639 | case 0x0D: set_mnemonic(i, "BREAK"); type=SYSCALL; break; | |
ed14d777 | 6640 | case 0x10: set_mnemonic(i, "MFHI"); type=MOV; break; |
6641 | case 0x11: set_mnemonic(i, "MTHI"); type=MOV; break; | |
6642 | case 0x12: set_mnemonic(i, "MFLO"); type=MOV; break; | |
6643 | case 0x13: set_mnemonic(i, "MTLO"); type=MOV; break; | |
6644 | case 0x18: set_mnemonic(i, "MULT"); type=MULTDIV; break; | |
6645 | case 0x19: set_mnemonic(i, "MULTU"); type=MULTDIV; break; | |
6646 | case 0x1A: set_mnemonic(i, "DIV"); type=MULTDIV; break; | |
6647 | case 0x1B: set_mnemonic(i, "DIVU"); type=MULTDIV; break; | |
6648 | case 0x20: set_mnemonic(i, "ADD"); type=ALU; break; | |
6649 | case 0x21: set_mnemonic(i, "ADDU"); type=ALU; break; | |
6650 | case 0x22: set_mnemonic(i, "SUB"); type=ALU; break; | |
6651 | case 0x23: set_mnemonic(i, "SUBU"); type=ALU; break; | |
6652 | case 0x24: set_mnemonic(i, "AND"); type=ALU; break; | |
6653 | case 0x25: set_mnemonic(i, "OR"); type=ALU; break; | |
6654 | case 0x26: set_mnemonic(i, "XOR"); type=ALU; break; | |
6655 | case 0x27: set_mnemonic(i, "NOR"); type=ALU; break; | |
6656 | case 0x2A: set_mnemonic(i, "SLT"); type=ALU; break; | |
6657 | case 0x2B: set_mnemonic(i, "SLTU"); type=ALU; break; | |
57871462 | 6658 | } |
6659 | break; | |
f2e25348 | 6660 | case 0x01: set_mnemonic(i, "regimm"); |
6661 | type = SJUMP; | |
5753f874 | 6662 | op2 = (src >> 16) & 0x1f; |
57871462 | 6663 | switch(op2) |
6664 | { | |
f2e25348 | 6665 | case 0x10: set_mnemonic(i, "BLTZAL"); break; |
6666 | case 0x11: set_mnemonic(i, "BGEZAL"); break; | |
6667 | default: | |
6668 | if (op2 & 1) | |
6669 | set_mnemonic(i, "BGEZ"); | |
6670 | else | |
6671 | set_mnemonic(i, "BLTZ"); | |
57871462 | 6672 | } |
6673 | break; | |
ed14d777 | 6674 | case 0x02: set_mnemonic(i, "J"); type=UJUMP; break; |
6675 | case 0x03: set_mnemonic(i, "JAL"); type=UJUMP; break; | |
6676 | case 0x04: set_mnemonic(i, "BEQ"); type=CJUMP; break; | |
6677 | case 0x05: set_mnemonic(i, "BNE"); type=CJUMP; break; | |
6678 | case 0x06: set_mnemonic(i, "BLEZ"); type=CJUMP; break; | |
6679 | case 0x07: set_mnemonic(i, "BGTZ"); type=CJUMP; break; | |
6680 | case 0x08: set_mnemonic(i, "ADDI"); type=IMM16; break; | |
6681 | case 0x09: set_mnemonic(i, "ADDIU"); type=IMM16; break; | |
6682 | case 0x0A: set_mnemonic(i, "SLTI"); type=IMM16; break; | |
6683 | case 0x0B: set_mnemonic(i, "SLTIU"); type=IMM16; break; | |
6684 | case 0x0C: set_mnemonic(i, "ANDI"); type=IMM16; break; | |
6685 | case 0x0D: set_mnemonic(i, "ORI"); type=IMM16; break; | |
6686 | case 0x0E: set_mnemonic(i, "XORI"); type=IMM16; break; | |
6687 | case 0x0F: set_mnemonic(i, "LUI"); type=IMM16; break; | |
f2e25348 | 6688 | case 0x10: set_mnemonic(i, "COP0"); |
5753f874 | 6689 | op2 = (src >> 21) & 0x1f; |
f2e25348 | 6690 | if (op2 & 0x10) { |
5753f874 | 6691 | op3 = src & 0x1f; |
f2e25348 | 6692 | switch (op3) |
6693 | { | |
6694 | case 0x01: case 0x02: case 0x06: case 0x08: type = INTCALL; break; | |
6695 | case 0x10: set_mnemonic(i, "RFE"); type=RFE; break; | |
6696 | default: type = OTHER; break; | |
6697 | } | |
6698 | break; | |
6699 | } | |
57871462 | 6700 | switch(op2) |
6701 | { | |
f2e25348 | 6702 | u32 rd; |
6703 | case 0x00: | |
6704 | set_mnemonic(i, "MFC0"); | |
5753f874 | 6705 | rd = (src >> 11) & 0x1F; |
f2e25348 | 6706 | if (!(0x00000417u & (1u << rd))) |
6707 | type = COP0; | |
6708 | break; | |
ed14d777 | 6709 | case 0x04: set_mnemonic(i, "MTC0"); type=COP0; break; |
f2e25348 | 6710 | case 0x02: |
6711 | case 0x06: type = INTCALL; break; | |
6712 | default: type = OTHER; break; | |
57871462 | 6713 | } |
6714 | break; | |
f2e25348 | 6715 | case 0x11: set_mnemonic(i, "COP1"); |
5753f874 | 6716 | op2 = (src >> 21) & 0x1f; |
57871462 | 6717 | break; |
f2e25348 | 6718 | case 0x12: set_mnemonic(i, "COP2"); |
5753f874 | 6719 | op2 = (src >> 21) & 0x1f; |
f2e25348 | 6720 | if (op2 & 0x10) { |
6721 | type = OTHER; | |
5753f874 | 6722 | if (gte_handlers[src & 0x3f] != NULL) { |
ed14d777 | 6723 | #ifdef DISASM |
5753f874 | 6724 | if (gte_regnames[src & 0x3f] != NULL) |
6725 | strcpy(insn[i], gte_regnames[src & 0x3f]); | |
bedfea38 | 6726 | else |
5753f874 | 6727 | snprintf(insn[i], sizeof(insn[i]), "COP2 %x", src & 0x3f); |
ed14d777 | 6728 | #endif |
f2e25348 | 6729 | type = C2OP; |
c7abc864 | 6730 | } |
6731 | } | |
6732 | else switch(op2) | |
b9b61529 | 6733 | { |
ed14d777 | 6734 | case 0x00: set_mnemonic(i, "MFC2"); type=COP2; break; |
6735 | case 0x02: set_mnemonic(i, "CFC2"); type=COP2; break; | |
6736 | case 0x04: set_mnemonic(i, "MTC2"); type=COP2; break; | |
6737 | case 0x06: set_mnemonic(i, "CTC2"); type=COP2; break; | |
b9b61529 | 6738 | } |
6739 | break; | |
f2e25348 | 6740 | case 0x13: set_mnemonic(i, "COP3"); |
5753f874 | 6741 | op2 = (src >> 21) & 0x1f; |
f2e25348 | 6742 | break; |
59dd5faf | 6743 | case 0x20: set_mnemonic(i, "LB"); type=LOAD; ls_type = LS_8; break; |
6744 | case 0x21: set_mnemonic(i, "LH"); type=LOAD; ls_type = LS_16; break; | |
6745 | case 0x22: set_mnemonic(i, "LWL"); type=LOADLR; ls_type = LS_LR; break; | |
6746 | case 0x23: set_mnemonic(i, "LW"); type=LOAD; ls_type = LS_32; break; | |
6747 | case 0x24: set_mnemonic(i, "LBU"); type=LOAD; ls_type = LS_8; break; | |
6748 | case 0x25: set_mnemonic(i, "LHU"); type=LOAD; ls_type = LS_16; break; | |
6749 | case 0x26: set_mnemonic(i, "LWR"); type=LOADLR; ls_type = LS_LR; break; | |
6750 | case 0x28: set_mnemonic(i, "SB"); type=STORE; ls_type = LS_8; break; | |
6751 | case 0x29: set_mnemonic(i, "SH"); type=STORE; ls_type = LS_16; break; | |
6752 | case 0x2A: set_mnemonic(i, "SWL"); type=STORELR; ls_type = LS_LR; break; | |
6753 | case 0x2B: set_mnemonic(i, "SW"); type=STORE; ls_type = LS_32; break; | |
6754 | case 0x2E: set_mnemonic(i, "SWR"); type=STORELR; ls_type = LS_LR; break; | |
6755 | case 0x32: set_mnemonic(i, "LWC2"); type=C2LS; ls_type = LS_32; break; | |
6756 | case 0x3A: set_mnemonic(i, "SWC2"); type=C2LS; ls_type = LS_32; break; | |
f2e25348 | 6757 | case 0x3B: |
5753f874 | 6758 | if (Config.HLE && (src & 0x03ffffff) < ARRAY_SIZE(psxHLEt)) { |
f2e25348 | 6759 | set_mnemonic(i, "HLECALL"); |
6760 | type = HLECALL; | |
6761 | } | |
6762 | break; | |
6763 | default: | |
90ae6d4e | 6764 | break; |
57871462 | 6765 | } |
f2e25348 | 6766 | if (type == INTCALL) |
5753f874 | 6767 | SysPrintf("NI %08x @%08x (%08x)\n", src, start + i*4, start); |
59dd5faf | 6768 | dops[i].itype = type; |
6769 | dops[i].opcode2 = op2; | |
6770 | dops[i].ls_type = ls_type; | |
57871462 | 6771 | /* Get registers/immediates */ |
ed14d777 | 6772 | dops[i].use_lt1=0; |
bedfea38 | 6773 | gte_rs[i]=gte_rt[i]=0; |
f2e25348 | 6774 | dops[i].rs1 = 0; |
6775 | dops[i].rs2 = 0; | |
6776 | dops[i].rt1 = 0; | |
6777 | dops[i].rt2 = 0; | |
57871462 | 6778 | switch(type) { |
6779 | case LOAD: | |
5753f874 | 6780 | dops[i].rs1 = (src >> 21) & 0x1f; |
6781 | dops[i].rt1 = (src >> 16) & 0x1f; | |
6782 | cinfo[i].imm = (short)src; | |
57871462 | 6783 | break; |
6784 | case STORE: | |
6785 | case STORELR: | |
5753f874 | 6786 | dops[i].rs1 = (src >> 21) & 0x1f; |
6787 | dops[i].rs2 = (src >> 16) & 0x1f; | |
6788 | cinfo[i].imm = (short)src; | |
57871462 | 6789 | break; |
6790 | case LOADLR: | |
6791 | // LWL/LWR only load part of the register, | |
6792 | // therefore the target register must be treated as a source too | |
5753f874 | 6793 | dops[i].rs1 = (src >> 21) & 0x1f; |
6794 | dops[i].rs2 = (src >> 16) & 0x1f; | |
6795 | dops[i].rt1 = (src >> 16) & 0x1f; | |
6796 | cinfo[i].imm = (short)src; | |
57871462 | 6797 | break; |
6798 | case IMM16: | |
630b122b | 6799 | if (op==0x0f) dops[i].rs1=0; // LUI instruction has no source register |
5753f874 | 6800 | else dops[i].rs1 = (src >> 21) & 0x1f; |
6801 | dops[i].rs2 = 0; | |
6802 | dops[i].rt1 = (src >> 16) & 0x1f; | |
57871462 | 6803 | if(op>=0x0c&&op<=0x0e) { // ANDI/ORI/XORI |
5753f874 | 6804 | cinfo[i].imm = (unsigned short)src; |
57871462 | 6805 | }else{ |
5753f874 | 6806 | cinfo[i].imm = (short)src; |
57871462 | 6807 | } |
57871462 | 6808 | break; |
6809 | case UJUMP: | |
57871462 | 6810 | // The JAL instruction writes to r31. |
6811 | if (op&1) { | |
630b122b | 6812 | dops[i].rt1=31; |
57871462 | 6813 | } |
630b122b | 6814 | dops[i].rs2=CCREG; |
57871462 | 6815 | break; |
6816 | case RJUMP: | |
5753f874 | 6817 | dops[i].rs1 = (src >> 21) & 0x1f; |
5067f341 | 6818 | // The JALR instruction writes to rd. |
57871462 | 6819 | if (op2&1) { |
5753f874 | 6820 | dops[i].rt1 = (src >> 11) & 0x1f; |
57871462 | 6821 | } |
630b122b | 6822 | dops[i].rs2=CCREG; |
57871462 | 6823 | break; |
6824 | case CJUMP: | |
5753f874 | 6825 | dops[i].rs1 = (src >> 21) & 0x1f; |
6826 | dops[i].rs2 = (src >> 16) & 0x1f; | |
57871462 | 6827 | if(op&2) { // BGTZ/BLEZ |
630b122b | 6828 | dops[i].rs2=0; |
57871462 | 6829 | } |
57871462 | 6830 | break; |
6831 | case SJUMP: | |
5753f874 | 6832 | dops[i].rs1 = (src >> 21) & 0x1f; |
6833 | dops[i].rs2 = CCREG; | |
f2e25348 | 6834 | if (op2 == 0x10 || op2 == 0x11) { // BxxAL |
6835 | dops[i].rt1 = 31; | |
57871462 | 6836 | // NOTE: If the branch is not taken, r31 is still overwritten |
6837 | } | |
57871462 | 6838 | break; |
6839 | case ALU: | |
5753f874 | 6840 | dops[i].rs1=(src>>21)&0x1f; // source |
6841 | dops[i].rs2=(src>>16)&0x1f; // subtract amount | |
6842 | dops[i].rt1=(src>>11)&0x1f; // destination | |
57871462 | 6843 | break; |
6844 | case MULTDIV: | |
5753f874 | 6845 | dops[i].rs1=(src>>21)&0x1f; // source |
6846 | dops[i].rs2=(src>>16)&0x1f; // divisor | |
630b122b | 6847 | dops[i].rt1=HIREG; |
6848 | dops[i].rt2=LOREG; | |
57871462 | 6849 | break; |
6850 | case MOV: | |
630b122b | 6851 | if(op2==0x10) dops[i].rs1=HIREG; // MFHI |
6852 | if(op2==0x11) dops[i].rt1=HIREG; // MTHI | |
6853 | if(op2==0x12) dops[i].rs1=LOREG; // MFLO | |
6854 | if(op2==0x13) dops[i].rt1=LOREG; // MTLO | |
5753f874 | 6855 | if((op2&0x1d)==0x10) dops[i].rt1=(src>>11)&0x1f; // MFxx |
6856 | if((op2&0x1d)==0x11) dops[i].rs1=(src>>21)&0x1f; // MTxx | |
57871462 | 6857 | break; |
6858 | case SHIFT: | |
5753f874 | 6859 | dops[i].rs1=(src>>16)&0x1f; // target of shift |
6860 | dops[i].rs2=(src>>21)&0x1f; // shift amount | |
6861 | dops[i].rt1=(src>>11)&0x1f; // destination | |
57871462 | 6862 | break; |
6863 | case SHIFTIMM: | |
5753f874 | 6864 | dops[i].rs1=(src>>16)&0x1f; |
630b122b | 6865 | dops[i].rs2=0; |
5753f874 | 6866 | dops[i].rt1=(src>>11)&0x1f; |
6867 | cinfo[i].imm=(src>>6)&0x1f; | |
57871462 | 6868 | break; |
6869 | case COP0: | |
5753f874 | 6870 | if(op2==0) dops[i].rt1=(src>>16)&0x1F; // MFC0 |
6871 | if(op2==4) dops[i].rs1=(src>>16)&0x1F; // MTC0 | |
6872 | if(op2==4&&((src>>11)&0x1e)==12) dops[i].rs2=CCREG; | |
57871462 | 6873 | break; |
bedfea38 | 6874 | case COP2: |
5753f874 | 6875 | if(op2<3) dops[i].rt1=(src>>16)&0x1F; // MFC2/CFC2 |
6876 | if(op2>3) dops[i].rs1=(src>>16)&0x1F; // MTC2/CTC2 | |
6877 | int gr=(src>>11)&0x1F; | |
bedfea38 | 6878 | switch(op2) |
6879 | { | |
6880 | case 0x00: gte_rs[i]=1ll<<gr; break; // MFC2 | |
6881 | case 0x04: gte_rt[i]=1ll<<gr; break; // MTC2 | |
0ff8c62c | 6882 | case 0x02: gte_rs[i]=1ll<<(gr+32); break; // CFC2 |
bedfea38 | 6883 | case 0x06: gte_rt[i]=1ll<<(gr+32); break; // CTC2 |
6884 | } | |
6885 | break; | |
b9b61529 | 6886 | case C2LS: |
5753f874 | 6887 | dops[i].rs1=(src>>21)&0x1F; |
6888 | cinfo[i].imm=(short)src; | |
6889 | if(op==0x32) gte_rt[i]=1ll<<((src>>16)&0x1F); // LWC2 | |
6890 | else gte_rs[i]=1ll<<((src>>16)&0x1F); // SWC2 | |
bedfea38 | 6891 | break; |
6892 | case C2OP: | |
5753f874 | 6893 | gte_rs[i]=gte_reg_reads[src&0x3f]; |
6894 | gte_rt[i]=gte_reg_writes[src&0x3f]; | |
2167bef6 | 6895 | gte_rt[i]|=1ll<<63; // every op changes flags |
5753f874 | 6896 | if((src&0x3f)==GTE_MVMVA) { |
6897 | int v = (src >> 15) & 3; | |
587a5b1c | 6898 | gte_rs[i]&=~0xe3fll; |
6899 | if(v==3) gte_rs[i]|=0xe00ll; | |
6900 | else gte_rs[i]|=3ll<<(v*2); | |
6901 | } | |
b9b61529 | 6902 | break; |
57871462 | 6903 | case SYSCALL: |
7139f3c8 | 6904 | case HLECALL: |
1e973cb0 | 6905 | case INTCALL: |
630b122b | 6906 | dops[i].rs1=CCREG; |
57871462 | 6907 | break; |
6908 | default: | |
f2e25348 | 6909 | break; |
57871462 | 6910 | } |
5753f874 | 6911 | } |
6912 | ||
6913 | static noinline void pass1_disassemble(u_int pagelimit) | |
6914 | { | |
6915 | int i, j, done = 0, ni_count = 0; | |
59dd5faf | 6916 | int ds_next = 0; |
5753f874 | 6917 | |
6918 | for (i = 0; !done; i++) | |
6919 | { | |
6920 | int force_j_to_interpreter = 0; | |
6921 | unsigned int type, op, op2; | |
6922 | ||
6923 | disassemble_one(i, source[i]); | |
59dd5faf | 6924 | dops[i].is_ds = ds_next; ds_next = 0; |
5753f874 | 6925 | type = dops[i].itype; |
6926 | op = dops[i].opcode; | |
6927 | op2 = dops[i].opcode2; | |
6928 | ||
57871462 | 6929 | /* Calculate branch target addresses */ |
6930 | if(type==UJUMP) | |
259dbd60 | 6931 | cinfo[i].ba=((start+i*4+4)&0xF0000000)|(((unsigned int)source[i]<<6)>>4); |
630b122b | 6932 | else if(type==CJUMP&&dops[i].rs1==dops[i].rs2&&(op&1)) |
259dbd60 | 6933 | cinfo[i].ba=start+i*4+8; // Ignore never taken branch |
630b122b | 6934 | else if(type==SJUMP&&dops[i].rs1==0&&!(op2&1)) |
259dbd60 | 6935 | cinfo[i].ba=start+i*4+8; // Ignore never taken branch |
630b122b | 6936 | else if(type==CJUMP||type==SJUMP) |
259dbd60 | 6937 | cinfo[i].ba=start+i*4+4+((signed int)((unsigned int)source[i]<<16)>>14); |
630b122b | 6938 | |
6939 | /* simplify always (not)taken branches */ | |
6940 | if (type == CJUMP && dops[i].rs1 == dops[i].rs2) { | |
6941 | dops[i].rs1 = dops[i].rs2 = 0; | |
6942 | if (!(op & 1)) { | |
6943 | dops[i].itype = type = UJUMP; | |
6944 | dops[i].rs2 = CCREG; | |
6945 | } | |
6946 | } | |
6947 | else if (type == SJUMP && dops[i].rs1 == 0 && (op2 & 1)) | |
6948 | dops[i].itype = type = UJUMP; | |
6949 | ||
259dbd60 | 6950 | dops[i].is_jump = type == RJUMP || type == UJUMP || type == CJUMP || type == SJUMP; |
6951 | dops[i].is_ujump = type == RJUMP || type == UJUMP; | |
6952 | dops[i].is_load = type == LOAD || type == LOADLR || op == 0x32; // LWC2 | |
f2e25348 | 6953 | dops[i].is_delay_load = (dops[i].is_load || (source[i] & 0xf3d00000) == 0x40000000); // MFC/CFC |
259dbd60 | 6954 | dops[i].is_store = type == STORE || type == STORELR || op == 0x3a; // SWC2 |
6955 | dops[i].is_exception = type == SYSCALL || type == HLECALL || type == INTCALL; | |
6956 | dops[i].may_except = dops[i].is_exception || (type == ALU && (op2 == 0x20 || op2 == 0x22)) || op == 8; | |
59dd5faf | 6957 | ds_next = dops[i].is_jump; |
259dbd60 | 6958 | |
6959 | if (((op & 0x37) == 0x21 || op == 0x25) // LH/SH/LHU | |
6960 | && ((cinfo[i].imm & 1) || Config.PreciseExceptions)) | |
6961 | dops[i].may_except = 1; | |
6962 | if (((op & 0x37) == 0x23 || (op & 0x37) == 0x32) // LW/SW/LWC2/SWC2 | |
6963 | && ((cinfo[i].imm & 3) || Config.PreciseExceptions)) | |
6964 | dops[i].may_except = 1; | |
630b122b | 6965 | |
f2e25348 | 6966 | /* rare messy cases to just pass over to the interpreter */ |
630b122b | 6967 | if (i > 0 && dops[i-1].is_jump) { |
3a64d2f7 | 6968 | j = i - 1; |
3e535354 | 6969 | // branch in delay slot? |
630b122b | 6970 | if (dops[i].is_jump) { |
3e535354 | 6971 | // don't handle first branch and call interpreter if it's hit |
f2e25348 | 6972 | SysPrintf("branch in DS @%08x (%08x)\n", start + i*4, start); |
3a64d2f7 | 6973 | force_j_to_interpreter = 1; |
3e535354 | 6974 | } |
5753f874 | 6975 | // load delay detection through a branch |
f2e25348 | 6976 | else if (dops[i].is_delay_load && dops[i].rt1 != 0) { |
5753f874 | 6977 | const struct decoded_insn *dop = NULL; |
6978 | int t = -1; | |
6979 | if (cinfo[i-1].ba != -1) { | |
6980 | t = (cinfo[i-1].ba - start) / 4; | |
6981 | if (t < 0 || t > i) { | |
6982 | u_int limit = 0; | |
6983 | u_int *mem = get_source_start(cinfo[i-1].ba, &limit); | |
6984 | if (mem != NULL) { | |
6985 | disassemble_one(MAXBLOCK - 1, mem[0]); | |
6986 | dop = &dops[MAXBLOCK - 1]; | |
6987 | } | |
6988 | } | |
6989 | else | |
6990 | dop = &dops[t]; | |
6991 | } | |
06d32d29 | 6992 | if ((dop && is_ld_use_hazard(&dops[i], dop)) |
5753f874 | 6993 | || (!dop && Config.PreciseExceptions)) { |
3e535354 | 6994 | // jump target wants DS result - potential load delay effect |
f2e25348 | 6995 | SysPrintf("load delay in DS @%08x (%08x)\n", start + i*4, start); |
3a64d2f7 | 6996 | force_j_to_interpreter = 1; |
5753f874 | 6997 | if (0 <= t && t < i) |
6998 | dops[t + 1].bt = 1; // expected return from interpreter | |
3e535354 | 6999 | } |
630b122b | 7000 | else if(i>=2&&dops[i-2].rt1==2&&dops[i].rt1==2&&dops[i].rs1!=2&&dops[i].rs2!=2&&dops[i-1].rs1!=2&&dops[i-1].rs2!=2&& |
7001 | !(i>=3&&dops[i-3].is_jump)) { | |
3e535354 | 7002 | // v0 overwrite like this is a sign of trouble, bail out |
94061aa5 | 7003 | SysPrintf("v0 overwrite @%08x (%08x)\n", start + i*4, start); |
3a64d2f7 | 7004 | force_j_to_interpreter = 1; |
3e535354 | 7005 | } |
7006 | } | |
f2e25348 | 7007 | } |
5753f874 | 7008 | else if (i > 0 && dops[i-1].is_delay_load |
06d32d29 | 7009 | && is_ld_use_hazard(&dops[i-1], &dops[i]) |
5753f874 | 7010 | && (i < 2 || !dops[i-2].is_ujump)) { |
f2e25348 | 7011 | SysPrintf("load delay @%08x (%08x)\n", start + i*4, start); |
3a64d2f7 | 7012 | for (j = i - 1; j > 0 && dops[j-1].is_delay_load; j--) |
7013 | if (dops[j-1].rt1 != dops[i-1].rt1) | |
7014 | break; | |
7015 | force_j_to_interpreter = 1; | |
f2e25348 | 7016 | } |
3a64d2f7 | 7017 | if (force_j_to_interpreter) { |
5753f874 | 7018 | force_intcall(j); |
f2e25348 | 7019 | done = 2; |
3a64d2f7 | 7020 | i = j; // don't compile the problematic branch/load/etc |
3e535354 | 7021 | } |
5753f874 | 7022 | if (dops[i].is_exception && i > 0 && dops[i-1].is_jump) { |
7023 | SysPrintf("exception in DS @%08x (%08x)\n", start + i*4, start); | |
7024 | i--; | |
7025 | force_intcall(i); | |
7026 | done = 2; | |
7027 | } | |
7028 | if (i >= 2 && (source[i-2] & 0xffe0f800) == 0x40806000) // MTC0 $12 | |
7029 | dops[i].bt = 1; | |
7030 | if (i >= 1 && (source[i-1] & 0xffe0f800) == 0x40806800) // MTC0 $13 | |
7031 | dops[i].bt = 1; | |
630b122b | 7032 | |
3e535354 | 7033 | /* Is this the end of the block? */ |
630b122b | 7034 | if (i > 0 && dops[i-1].is_ujump) { |
a46de547 | 7035 | if (dops[i-1].rt1 == 0) { // not jal |
259dbd60 | 7036 | int found_bbranch = 0, t = (cinfo[i-1].ba - start) / 4; |
a46de547 | 7037 | if ((u_int)(t - i) < 64 && start + (t+64)*4 < pagelimit) { |
7038 | // scan for a branch back to i+1 | |
7039 | for (j = t; j < t + 64; j++) { | |
7040 | int tmpop = source[j] >> 26; | |
7041 | if (tmpop == 1 || ((tmpop & ~3) == 4)) { | |
7042 | int t2 = j + 1 + (int)(signed short)source[j]; | |
7043 | if (t2 == i + 1) { | |
7044 | //printf("blk expand %08x<-%08x\n", start + (i+1)*4, start + j*4); | |
7045 | found_bbranch = 1; | |
7046 | break; | |
7047 | } | |
7048 | } | |
7049 | } | |
7050 | } | |
7051 | if (!found_bbranch) | |
7052 | done = 2; | |
57871462 | 7053 | } |
7054 | else { | |
7055 | if(stop_after_jal) done=1; | |
7056 | // Stop on BREAK | |
7057 | if((source[i+1]&0xfc00003f)==0x0d) done=1; | |
7058 | } | |
7059 | // Don't recompile stuff that's already compiled | |
7060 | if(check_addr(start+i*4+4)) done=1; | |
7061 | // Don't get too close to the limit | |
ee8d7dfd | 7062 | if (i > MAXBLOCK - 64) |
7063 | done = 1; | |
57871462 | 7064 | } |
f2e25348 | 7065 | if (dops[i].itype == HLECALL) |
9415f066 | 7066 | done = 1; |
f2e25348 | 7067 | else if (dops[i].itype == INTCALL) |
9415f066 | 7068 | done = 2; |
f2e25348 | 7069 | else if (dops[i].is_exception) |
467357cc | 7070 | done = stop_after_jal ? 1 : 2; |
7071 | if (done == 2) { | |
1e973cb0 | 7072 | // Does the block continue due to a branch? |
7073 | for(j=i-1;j>=0;j--) | |
7074 | { | |
259dbd60 | 7075 | if(cinfo[j].ba==start+i*4) done=j=0; // Branch into delay slot |
7076 | if(cinfo[j].ba==start+i*4+4) done=j=0; | |
7077 | if(cinfo[j].ba==start+i*4+8) done=j=0; | |
1e973cb0 | 7078 | } |
7079 | } | |
75dec299 | 7080 | //assert(i<MAXBLOCK-1); |
57871462 | 7081 | if(start+i*4==pagelimit-4) done=1; |
7082 | assert(start+i*4<pagelimit); | |
ee8d7dfd | 7083 | if (i == MAXBLOCK - 2) |
7084 | done = 1; | |
57871462 | 7085 | // Stop if we're compiling junk |
f2e25348 | 7086 | if (dops[i].itype == INTCALL && (++ni_count > 8 || dops[i].opcode == 0x11)) { |
57871462 | 7087 | done=stop_after_jal=1; |
c43b5311 | 7088 | SysPrintf("Disabled speculative precompilation\n"); |
57871462 | 7089 | } |
7090 | } | |
f9e37973 | 7091 | while (i > 0 && dops[i-1].is_jump) |
7092 | i--; | |
7093 | assert(i > 0); | |
7094 | assert(!dops[i-1].is_jump); | |
7095 | slen = i; | |
94061aa5 | 7096 | } |
7097 | ||
7098 | // Basic liveness analysis for MIPS registers | |
7099 | static noinline void pass2_unneeded_regs(int istart,int iend,int r) | |
7100 | { | |
7101 | int i; | |
7102 | uint64_t u,gte_u,b,gte_b; | |
7103 | uint64_t temp_u,temp_gte_u=0; | |
7104 | uint64_t gte_u_unknown=0; | |
7105 | if (HACK_ENABLED(NDHACK_GTE_UNNEEDED)) | |
7106 | gte_u_unknown=~0ll; | |
7107 | if(iend==slen-1) { | |
7108 | u=1; | |
7109 | gte_u=gte_u_unknown; | |
7110 | }else{ | |
7111 | //u=unneeded_reg[iend+1]; | |
7112 | u=1; | |
7113 | gte_u=gte_unneeded[iend+1]; | |
7114 | } | |
7115 | ||
7116 | for (i=iend;i>=istart;i--) | |
7117 | { | |
7118 | //printf("unneeded registers i=%d (%d,%d) r=%d\n",i,istart,iend,r); | |
7119 | if(dops[i].is_jump) | |
7120 | { | |
7121 | // If subroutine call, flag return address as a possible branch target | |
7122 | if(dops[i].rt1==31 && i<slen-2) dops[i+2].bt=1; | |
7123 | ||
259dbd60 | 7124 | if(cinfo[i].ba<start || cinfo[i].ba>=(start+slen*4)) |
94061aa5 | 7125 | { |
7126 | // Branch out of this block, flush all regs | |
7127 | u=1; | |
7128 | gte_u=gte_u_unknown; | |
7129 | branch_unneeded_reg[i]=u; | |
7130 | // Merge in delay slot | |
7131 | u|=(1LL<<dops[i+1].rt1)|(1LL<<dops[i+1].rt2); | |
7132 | u&=~((1LL<<dops[i+1].rs1)|(1LL<<dops[i+1].rs2)); | |
7133 | u|=1; | |
7134 | gte_u|=gte_rt[i+1]; | |
7135 | gte_u&=~gte_rs[i+1]; | |
7136 | } | |
7137 | else | |
7138 | { | |
7139 | // Internal branch, flag target | |
259dbd60 | 7140 | dops[(cinfo[i].ba-start)>>2].bt=1; |
7141 | if(cinfo[i].ba<=start+i*4) { | |
94061aa5 | 7142 | // Backward branch |
7143 | if(dops[i].is_ujump) | |
7144 | { | |
7145 | // Unconditional branch | |
7146 | temp_u=1; | |
7147 | temp_gte_u=0; | |
7148 | } else { | |
7149 | // Conditional branch (not taken case) | |
7150 | temp_u=unneeded_reg[i+2]; | |
7151 | temp_gte_u&=gte_unneeded[i+2]; | |
7152 | } | |
7153 | // Merge in delay slot | |
7154 | temp_u|=(1LL<<dops[i+1].rt1)|(1LL<<dops[i+1].rt2); | |
7155 | temp_u&=~((1LL<<dops[i+1].rs1)|(1LL<<dops[i+1].rs2)); | |
7156 | temp_u|=1; | |
7157 | temp_gte_u|=gte_rt[i+1]; | |
7158 | temp_gte_u&=~gte_rs[i+1]; | |
7159 | temp_u|=(1LL<<dops[i].rt1)|(1LL<<dops[i].rt2); | |
7160 | temp_u&=~((1LL<<dops[i].rs1)|(1LL<<dops[i].rs2)); | |
7161 | temp_u|=1; | |
7162 | temp_gte_u|=gte_rt[i]; | |
7163 | temp_gte_u&=~gte_rs[i]; | |
7164 | unneeded_reg[i]=temp_u; | |
7165 | gte_unneeded[i]=temp_gte_u; | |
7166 | // Only go three levels deep. This recursion can take an | |
7167 | // excessive amount of time if there are a lot of nested loops. | |
7168 | if(r<2) { | |
259dbd60 | 7169 | pass2_unneeded_regs((cinfo[i].ba-start)>>2,i-1,r+1); |
94061aa5 | 7170 | }else{ |
259dbd60 | 7171 | unneeded_reg[(cinfo[i].ba-start)>>2]=1; |
7172 | gte_unneeded[(cinfo[i].ba-start)>>2]=gte_u_unknown; | |
94061aa5 | 7173 | } |
7174 | } /*else*/ if(1) { | |
7175 | if (dops[i].is_ujump) | |
7176 | { | |
7177 | // Unconditional branch | |
259dbd60 | 7178 | u=unneeded_reg[(cinfo[i].ba-start)>>2]; |
7179 | gte_u=gte_unneeded[(cinfo[i].ba-start)>>2]; | |
94061aa5 | 7180 | branch_unneeded_reg[i]=u; |
7181 | // Merge in delay slot | |
7182 | u|=(1LL<<dops[i+1].rt1)|(1LL<<dops[i+1].rt2); | |
7183 | u&=~((1LL<<dops[i+1].rs1)|(1LL<<dops[i+1].rs2)); | |
7184 | u|=1; | |
7185 | gte_u|=gte_rt[i+1]; | |
7186 | gte_u&=~gte_rs[i+1]; | |
7187 | } else { | |
7188 | // Conditional branch | |
259dbd60 | 7189 | b=unneeded_reg[(cinfo[i].ba-start)>>2]; |
7190 | gte_b=gte_unneeded[(cinfo[i].ba-start)>>2]; | |
94061aa5 | 7191 | branch_unneeded_reg[i]=b; |
7192 | // Branch delay slot | |
7193 | b|=(1LL<<dops[i+1].rt1)|(1LL<<dops[i+1].rt2); | |
7194 | b&=~((1LL<<dops[i+1].rs1)|(1LL<<dops[i+1].rs2)); | |
7195 | b|=1; | |
7196 | gte_b|=gte_rt[i+1]; | |
7197 | gte_b&=~gte_rs[i+1]; | |
7198 | u&=b; | |
7199 | gte_u&=gte_b; | |
7200 | if(i<slen-1) { | |
7201 | branch_unneeded_reg[i]&=unneeded_reg[i+2]; | |
7202 | } else { | |
7203 | branch_unneeded_reg[i]=1; | |
7204 | } | |
7205 | } | |
7206 | } | |
7207 | } | |
7208 | } | |
94061aa5 | 7209 | //u=1; // DEBUG |
7210 | // Written registers are unneeded | |
7211 | u|=1LL<<dops[i].rt1; | |
7212 | u|=1LL<<dops[i].rt2; | |
7213 | gte_u|=gte_rt[i]; | |
7214 | // Accessed registers are needed | |
7215 | u&=~(1LL<<dops[i].rs1); | |
7216 | u&=~(1LL<<dops[i].rs2); | |
7217 | gte_u&=~gte_rs[i]; | |
7218 | if(gte_rs[i]&&dops[i].rt1&&(unneeded_reg[i+1]&(1ll<<dops[i].rt1))) | |
7219 | gte_u|=gte_rs[i]>e_unneeded[i+1]; // MFC2/CFC2 to dead register, unneeded | |
b4661440 | 7220 | if (dops[i].may_except || dops[i].itype == RFE) |
7221 | { | |
7222 | // SYSCALL instruction, etc or conditional exception | |
7223 | u=1; | |
7224 | } | |
94061aa5 | 7225 | // Source-target dependencies |
7226 | // R0 is always unneeded | |
7227 | u|=1; | |
7228 | // Save it | |
7229 | unneeded_reg[i]=u; | |
7230 | gte_unneeded[i]=gte_u; | |
7231 | /* | |
7232 | printf("ur (%d,%d) %x: ",istart,iend,start+i*4); | |
7233 | printf("U:"); | |
7234 | int r; | |
7235 | for(r=1;r<=CCREG;r++) { | |
7236 | if((unneeded_reg[i]>>r)&1) { | |
7237 | if(r==HIREG) printf(" HI"); | |
7238 | else if(r==LOREG) printf(" LO"); | |
7239 | else printf(" r%d",r); | |
7240 | } | |
7241 | } | |
7242 | printf("\n"); | |
7243 | */ | |
7244 | } | |
7245 | } | |
57871462 | 7246 | |
59dd5faf | 7247 | static noinline void pass2a_unneeded_other(void) |
7248 | { | |
7249 | int i, j; | |
7250 | for (i = 0; i < slen; i++) | |
7251 | { | |
7252 | // remove redundant alignment checks | |
7253 | if (dops[i].may_except && (dops[i].is_load || dops[i].is_store) | |
7254 | && dops[i].rt1 != dops[i].rs1 && !dops[i].is_ds) | |
7255 | { | |
7256 | int base = dops[i].rs1, lsb = cinfo[i].imm, ls_type = dops[i].ls_type; | |
7257 | int mask = ls_type == LS_32 ? 3 : 1; | |
7258 | lsb &= mask; | |
7259 | for (j = i + 1; j < slen; j++) { | |
7260 | if (dops[j].bt || dops[j].is_jump) | |
7261 | break; | |
7262 | if ((dops[j].is_load || dops[j].is_store) && dops[j].rs1 == base | |
7263 | && dops[j].ls_type == ls_type && (cinfo[j].imm & mask) == lsb) | |
7264 | dops[j].may_except = 0; | |
7265 | if (dops[j].rt1 == base) | |
7266 | break; | |
7267 | } | |
7268 | } | |
7269 | } | |
7270 | } | |
7271 | ||
94061aa5 | 7272 | static noinline void pass3_register_alloc(u_int addr) |
7273 | { | |
57871462 | 7274 | struct regstat current; // Current register allocations/status |
b15d122e | 7275 | clear_all_regs(current.regmap_entry); |
57871462 | 7276 | clear_all_regs(current.regmap); |
b15d122e | 7277 | current.wasdirty = current.dirty = 0; |
7278 | current.u = unneeded_reg[0]; | |
7279 | alloc_reg(¤t, 0, CCREG); | |
7280 | dirty_reg(¤t, CCREG); | |
7281 | current.wasconst = 0; | |
7282 | current.isconst = 0; | |
7283 | current.loadedconst = 0; | |
b4661440 | 7284 | current.noevict = 0; |
bdbf4466 | 7285 | //current.waswritten = 0; |
57871462 | 7286 | int ds=0; |
7287 | int cc=0; | |
94061aa5 | 7288 | int hr; |
7289 | int i, j; | |
6ebf4adf | 7290 | |
94061aa5 | 7291 | if (addr & 1) { |
57871462 | 7292 | // First instruction is delay slot |
7293 | cc=-1; | |
630b122b | 7294 | dops[1].bt=1; |
57871462 | 7295 | ds=1; |
7296 | unneeded_reg[0]=1; | |
57871462 | 7297 | } |
9f51b4b9 | 7298 | |
57871462 | 7299 | for(i=0;i<slen;i++) |
7300 | { | |
630b122b | 7301 | if(dops[i].bt) |
57871462 | 7302 | { |
57871462 | 7303 | for(hr=0;hr<HOST_REGS;hr++) |
7304 | { | |
7305 | // Is this really necessary? | |
7306 | if(current.regmap[hr]==0) current.regmap[hr]=-1; | |
7307 | } | |
7308 | current.isconst=0; | |
bdbf4466 | 7309 | //current.waswritten=0; |
57871462 | 7310 | } |
24385cae | 7311 | |
57871462 | 7312 | memcpy(regmap_pre[i],current.regmap,sizeof(current.regmap)); |
7313 | regs[i].wasconst=current.isconst; | |
57871462 | 7314 | regs[i].wasdirty=current.dirty; |
b15d122e | 7315 | regs[i].dirty=0; |
7316 | regs[i].u=0; | |
7317 | regs[i].isconst=0; | |
8575a877 | 7318 | regs[i].loadedconst=0; |
630b122b | 7319 | if (!dops[i].is_jump) { |
57871462 | 7320 | if(i+1<slen) { |
630b122b | 7321 | current.u=unneeded_reg[i+1]&~((1LL<<dops[i].rs1)|(1LL<<dops[i].rs2)); |
57871462 | 7322 | current.u|=1; |
57871462 | 7323 | } else { |
7324 | current.u=1; | |
57871462 | 7325 | } |
7326 | } else { | |
7327 | if(i+1<slen) { | |
630b122b | 7328 | current.u=branch_unneeded_reg[i]&~((1LL<<dops[i+1].rs1)|(1LL<<dops[i+1].rs2)); |
7329 | current.u&=~((1LL<<dops[i].rs1)|(1LL<<dops[i].rs2)); | |
57871462 | 7330 | current.u|=1; |
447f5a1d | 7331 | } else { |
7332 | SysPrintf("oops, branch at end of block with no delay slot @%08x\n", start + i*4); | |
7333 | abort(); | |
7334 | } | |
57871462 | 7335 | } |
59dd5faf | 7336 | assert(dops[i].is_ds == ds); |
57871462 | 7337 | if(ds) { |
7338 | ds=0; // Skip delay slot, already allocated as part of branch | |
7339 | // ...but we need to alloc it in case something jumps here | |
7340 | if(i+1<slen) { | |
7341 | current.u=branch_unneeded_reg[i-1]&unneeded_reg[i+1]; | |
57871462 | 7342 | }else{ |
7343 | current.u=branch_unneeded_reg[i-1]; | |
57871462 | 7344 | } |
630b122b | 7345 | current.u&=~((1LL<<dops[i].rs1)|(1LL<<dops[i].rs2)); |
57871462 | 7346 | current.u|=1; |
57871462 | 7347 | struct regstat temp; |
7348 | memcpy(&temp,¤t,sizeof(current)); | |
7349 | temp.wasdirty=temp.dirty; | |
57871462 | 7350 | // TODO: Take into account unconditional branches, as below |
7351 | delayslot_alloc(&temp,i); | |
7352 | memcpy(regs[i].regmap,temp.regmap,sizeof(temp.regmap)); | |
7353 | regs[i].wasdirty=temp.wasdirty; | |
57871462 | 7354 | regs[i].dirty=temp.dirty; |
57871462 | 7355 | regs[i].isconst=0; |
7356 | regs[i].wasconst=0; | |
7357 | current.isconst=0; | |
7358 | // Create entry (branch target) regmap | |
7359 | for(hr=0;hr<HOST_REGS;hr++) | |
7360 | { | |
7361 | int r=temp.regmap[hr]; | |
7362 | if(r>=0) { | |
7363 | if(r!=regmap_pre[i][hr]) { | |
7364 | regs[i].regmap_entry[hr]=-1; | |
7365 | } | |
7366 | else | |
7367 | { | |
630b122b | 7368 | assert(r < 64); |
57871462 | 7369 | if((current.u>>r)&1) { |
7370 | regs[i].regmap_entry[hr]=-1; | |
7371 | regs[i].regmap[hr]=-1; | |
7372 | //Don't clear regs in the delay slot as the branch might need them | |
7373 | //current.regmap[hr]=-1; | |
7374 | }else | |
7375 | regs[i].regmap_entry[hr]=r; | |
57871462 | 7376 | } |
7377 | } else { | |
7378 | // First instruction expects CCREG to be allocated | |
9f51b4b9 | 7379 | if(i==0&&hr==HOST_CCREG) |
57871462 | 7380 | regs[i].regmap_entry[hr]=CCREG; |
7381 | else | |
7382 | regs[i].regmap_entry[hr]=-1; | |
7383 | } | |
7384 | } | |
7385 | } | |
7386 | else { // Not delay slot | |
b4661440 | 7387 | current.noevict = 0; |
630b122b | 7388 | switch(dops[i].itype) { |
57871462 | 7389 | case UJUMP: |
7390 | //current.isconst=0; // DEBUG | |
7391 | //current.wasconst=0; // DEBUG | |
7392 | //regs[i].wasconst=0; // DEBUG | |
630b122b | 7393 | clear_const(¤t,dops[i].rt1); |
57871462 | 7394 | alloc_cc(¤t,i); |
7395 | dirty_reg(¤t,CCREG); | |
630b122b | 7396 | if (dops[i].rt1==31) { |
57871462 | 7397 | alloc_reg(¤t,i,31); |
7398 | dirty_reg(¤t,31); | |
630b122b | 7399 | //assert(dops[i+1].rs1!=31&&dops[i+1].rs2!=31); |
7400 | //assert(dops[i+1].rt1!=dops[i].rt1); | |
57871462 | 7401 | #ifdef REG_PREFETCH |
7402 | alloc_reg(¤t,i,PTEMP); | |
7403 | #endif | |
57871462 | 7404 | } |
630b122b | 7405 | dops[i].ooo=1; |
269bb29a | 7406 | delayslot_alloc(¤t,i+1); |
57871462 | 7407 | //current.isconst=0; // DEBUG |
7408 | ds=1; | |
57871462 | 7409 | break; |
7410 | case RJUMP: | |
7411 | //current.isconst=0; | |
7412 | //current.wasconst=0; | |
7413 | //regs[i].wasconst=0; | |
630b122b | 7414 | clear_const(¤t,dops[i].rs1); |
7415 | clear_const(¤t,dops[i].rt1); | |
57871462 | 7416 | alloc_cc(¤t,i); |
7417 | dirty_reg(¤t,CCREG); | |
630b122b | 7418 | if (!ds_writes_rjump_rs(i)) { |
7419 | alloc_reg(¤t,i,dops[i].rs1); | |
7420 | if (dops[i].rt1!=0) { | |
7421 | alloc_reg(¤t,i,dops[i].rt1); | |
7422 | dirty_reg(¤t,dops[i].rt1); | |
57871462 | 7423 | #ifdef REG_PREFETCH |
7424 | alloc_reg(¤t,i,PTEMP); | |
7425 | #endif | |
7426 | } | |
7427 | #ifdef USE_MINI_HT | |
630b122b | 7428 | if(dops[i].rs1==31) { // JALR |
57871462 | 7429 | alloc_reg(¤t,i,RHASH); |
57871462 | 7430 | alloc_reg(¤t,i,RHTBL); |
57871462 | 7431 | } |
7432 | #endif | |
7433 | delayslot_alloc(¤t,i+1); | |
7434 | } else { | |
7435 | // The delay slot overwrites our source register, | |
7436 | // allocate a temporary register to hold the old value. | |
7437 | current.isconst=0; | |
7438 | current.wasconst=0; | |
7439 | regs[i].wasconst=0; | |
7440 | delayslot_alloc(¤t,i+1); | |
7441 | current.isconst=0; | |
7442 | alloc_reg(¤t,i,RTEMP); | |
7443 | } | |
7444 | //current.isconst=0; // DEBUG | |
630b122b | 7445 | dops[i].ooo=1; |
57871462 | 7446 | ds=1; |
7447 | break; | |
7448 | case CJUMP: | |
7449 | //current.isconst=0; | |
7450 | //current.wasconst=0; | |
7451 | //regs[i].wasconst=0; | |
630b122b | 7452 | clear_const(¤t,dops[i].rs1); |
7453 | clear_const(¤t,dops[i].rs2); | |
7454 | if((dops[i].opcode&0x3E)==4) // BEQ/BNE | |
57871462 | 7455 | { |
7456 | alloc_cc(¤t,i); | |
7457 | dirty_reg(¤t,CCREG); | |
630b122b | 7458 | if(dops[i].rs1) alloc_reg(¤t,i,dops[i].rs1); |
7459 | if(dops[i].rs2) alloc_reg(¤t,i,dops[i].rs2); | |
7460 | if((dops[i].rs1&&(dops[i].rs1==dops[i+1].rt1||dops[i].rs1==dops[i+1].rt2))|| | |
7461 | (dops[i].rs2&&(dops[i].rs2==dops[i+1].rt1||dops[i].rs2==dops[i+1].rt2))) { | |
57871462 | 7462 | // The delay slot overwrites one of our conditions. |
7463 | // Allocate the branch condition registers instead. | |
57871462 | 7464 | current.isconst=0; |
7465 | current.wasconst=0; | |
7466 | regs[i].wasconst=0; | |
630b122b | 7467 | if(dops[i].rs1) alloc_reg(¤t,i,dops[i].rs1); |
7468 | if(dops[i].rs2) alloc_reg(¤t,i,dops[i].rs2); | |
57871462 | 7469 | } |
e1190b87 | 7470 | else |
7471 | { | |
630b122b | 7472 | dops[i].ooo=1; |
e1190b87 | 7473 | delayslot_alloc(¤t,i+1); |
7474 | } | |
57871462 | 7475 | } |
7476 | else | |
630b122b | 7477 | if((dops[i].opcode&0x3E)==6) // BLEZ/BGTZ |
57871462 | 7478 | { |
7479 | alloc_cc(¤t,i); | |
7480 | dirty_reg(¤t,CCREG); | |
630b122b | 7481 | alloc_reg(¤t,i,dops[i].rs1); |
7482 | if(dops[i].rs1&&(dops[i].rs1==dops[i+1].rt1||dops[i].rs1==dops[i+1].rt2)) { | |
57871462 | 7483 | // The delay slot overwrites one of our conditions. |
7484 | // Allocate the branch condition registers instead. | |
57871462 | 7485 | current.isconst=0; |
7486 | current.wasconst=0; | |
7487 | regs[i].wasconst=0; | |
630b122b | 7488 | if(dops[i].rs1) alloc_reg(¤t,i,dops[i].rs1); |
57871462 | 7489 | } |
e1190b87 | 7490 | else |
7491 | { | |
630b122b | 7492 | dops[i].ooo=1; |
e1190b87 | 7493 | delayslot_alloc(¤t,i+1); |
7494 | } | |
57871462 | 7495 | } |
7496 | else | |
7497 | // Don't alloc the delay slot yet because we might not execute it | |
630b122b | 7498 | if((dops[i].opcode&0x3E)==0x14) // BEQL/BNEL |
57871462 | 7499 | { |
7500 | current.isconst=0; | |
7501 | current.wasconst=0; | |
7502 | regs[i].wasconst=0; | |
7503 | alloc_cc(¤t,i); | |
7504 | dirty_reg(¤t,CCREG); | |
630b122b | 7505 | alloc_reg(¤t,i,dops[i].rs1); |
7506 | alloc_reg(¤t,i,dops[i].rs2); | |
57871462 | 7507 | } |
7508 | else | |
630b122b | 7509 | if((dops[i].opcode&0x3E)==0x16) // BLEZL/BGTZL |
57871462 | 7510 | { |
7511 | current.isconst=0; | |
7512 | current.wasconst=0; | |
7513 | regs[i].wasconst=0; | |
7514 | alloc_cc(¤t,i); | |
7515 | dirty_reg(¤t,CCREG); | |
630b122b | 7516 | alloc_reg(¤t,i,dops[i].rs1); |
57871462 | 7517 | } |
7518 | ds=1; | |
7519 | //current.isconst=0; | |
7520 | break; | |
7521 | case SJUMP: | |
630b122b | 7522 | clear_const(¤t,dops[i].rs1); |
7523 | clear_const(¤t,dops[i].rt1); | |
57871462 | 7524 | { |
7525 | alloc_cc(¤t,i); | |
7526 | dirty_reg(¤t,CCREG); | |
630b122b | 7527 | alloc_reg(¤t,i,dops[i].rs1); |
3a64d2f7 | 7528 | if (dops[i].rt1 == 31) { // BLTZAL/BGEZAL |
57871462 | 7529 | alloc_reg(¤t,i,31); |
7530 | dirty_reg(¤t,31); | |
57871462 | 7531 | } |
3a64d2f7 | 7532 | if ((dops[i].rs1 && |
7533 | (dops[i].rs1==dops[i+1].rt1||dops[i].rs1==dops[i+1].rt2)) // The delay slot overwrites the branch condition. | |
7534 | ||(dops[i].rt1 == 31 && dops[i].rs1 == 31) // overwrites it's own condition | |
630b122b | 7535 | ||(dops[i].rt1==31&&(dops[i+1].rs1==31||dops[i+1].rs2==31||dops[i+1].rt1==31||dops[i+1].rt2==31))) { // DS touches $ra |
57871462 | 7536 | // Allocate the branch condition registers instead. |
57871462 | 7537 | current.isconst=0; |
7538 | current.wasconst=0; | |
7539 | regs[i].wasconst=0; | |
630b122b | 7540 | if(dops[i].rs1) alloc_reg(¤t,i,dops[i].rs1); |
57871462 | 7541 | } |
e1190b87 | 7542 | else |
7543 | { | |
630b122b | 7544 | dops[i].ooo=1; |
e1190b87 | 7545 | delayslot_alloc(¤t,i+1); |
7546 | } | |
57871462 | 7547 | } |
57871462 | 7548 | ds=1; |
7549 | //current.isconst=0; | |
7550 | break; | |
57871462 | 7551 | case IMM16: |
7552 | imm16_alloc(¤t,i); | |
7553 | break; | |
7554 | case LOAD: | |
7555 | case LOADLR: | |
7556 | load_alloc(¤t,i); | |
7557 | break; | |
7558 | case STORE: | |
7559 | case STORELR: | |
7560 | store_alloc(¤t,i); | |
7561 | break; | |
7562 | case ALU: | |
7563 | alu_alloc(¤t,i); | |
7564 | break; | |
7565 | case SHIFT: | |
7566 | shift_alloc(¤t,i); | |
7567 | break; | |
7568 | case MULTDIV: | |
7569 | multdiv_alloc(¤t,i); | |
7570 | break; | |
7571 | case SHIFTIMM: | |
7572 | shiftimm_alloc(¤t,i); | |
7573 | break; | |
7574 | case MOV: | |
7575 | mov_alloc(¤t,i); | |
7576 | break; | |
7577 | case COP0: | |
7578 | cop0_alloc(¤t,i); | |
7579 | break; | |
f2e25348 | 7580 | case RFE: |
7581 | rfe_alloc(¤t,i); | |
630b122b | 7582 | break; |
b9b61529 | 7583 | case COP2: |
630b122b | 7584 | cop2_alloc(¤t,i); |
57871462 | 7585 | break; |
b9b61529 | 7586 | case C2LS: |
7587 | c2ls_alloc(¤t,i); | |
7588 | break; | |
7589 | case C2OP: | |
7590 | c2op_alloc(¤t,i); | |
7591 | break; | |
57871462 | 7592 | case SYSCALL: |
7139f3c8 | 7593 | case HLECALL: |
1e973cb0 | 7594 | case INTCALL: |
57871462 | 7595 | syscall_alloc(¤t,i); |
7596 | break; | |
57871462 | 7597 | } |
9f51b4b9 | 7598 | |
57871462 | 7599 | // Create entry (branch target) regmap |
7600 | for(hr=0;hr<HOST_REGS;hr++) | |
7601 | { | |
581335b0 | 7602 | int r,or; |
57871462 | 7603 | r=current.regmap[hr]; |
7604 | if(r>=0) { | |
7605 | if(r!=regmap_pre[i][hr]) { | |
7606 | // TODO: delay slot (?) | |
7607 | or=get_reg(regmap_pre[i],r); // Get old mapping for this register | |
91af94f0 | 7608 | if(or<0||r>=TEMPREG){ |
57871462 | 7609 | regs[i].regmap_entry[hr]=-1; |
7610 | } | |
7611 | else | |
7612 | { | |
7613 | // Just move it to a different register | |
7614 | regs[i].regmap_entry[hr]=r; | |
7615 | // If it was dirty before, it's still dirty | |
91af94f0 | 7616 | if((regs[i].wasdirty>>or)&1) dirty_reg(¤t,r); |
57871462 | 7617 | } |
7618 | } | |
7619 | else | |
7620 | { | |
7621 | // Unneeded | |
7622 | if(r==0){ | |
7623 | regs[i].regmap_entry[hr]=0; | |
7624 | } | |
7625 | else | |
630b122b | 7626 | { |
7627 | assert(r<64); | |
57871462 | 7628 | if((current.u>>r)&1) { |
7629 | regs[i].regmap_entry[hr]=-1; | |
7630 | //regs[i].regmap[hr]=-1; | |
7631 | current.regmap[hr]=-1; | |
7632 | }else | |
7633 | regs[i].regmap_entry[hr]=r; | |
7634 | } | |
57871462 | 7635 | } |
7636 | } else { | |
7637 | // Branches expect CCREG to be allocated at the target | |
9f51b4b9 | 7638 | if(regmap_pre[i][hr]==CCREG) |
57871462 | 7639 | regs[i].regmap_entry[hr]=CCREG; |
7640 | else | |
7641 | regs[i].regmap_entry[hr]=-1; | |
7642 | } | |
7643 | } | |
7644 | memcpy(regs[i].regmap,current.regmap,sizeof(current.regmap)); | |
7645 | } | |
27727b63 | 7646 | |
bdbf4466 | 7647 | #if 0 // see do_store_smc_check() |
259dbd60 | 7648 | if(i>0&&(dops[i-1].itype==STORE||dops[i-1].itype==STORELR||(dops[i-1].itype==C2LS&&dops[i-1].opcode==0x3a))&&(u_int)cinfo[i-1].imm<0x800) |
630b122b | 7649 | current.waswritten|=1<<dops[i-1].rs1; |
7650 | current.waswritten&=~(1<<dops[i].rt1); | |
7651 | current.waswritten&=~(1<<dops[i].rt2); | |
259dbd60 | 7652 | if((dops[i].itype==STORE||dops[i].itype==STORELR||(dops[i].itype==C2LS&&dops[i].opcode==0x3a))&&(u_int)cinfo[i].imm>=0x800) |
630b122b | 7653 | current.waswritten&=~(1<<dops[i].rs1); |
bdbf4466 | 7654 | #endif |
27727b63 | 7655 | |
57871462 | 7656 | /* Branch post-alloc */ |
7657 | if(i>0) | |
7658 | { | |
57871462 | 7659 | current.wasdirty=current.dirty; |
630b122b | 7660 | switch(dops[i-1].itype) { |
57871462 | 7661 | case UJUMP: |
7662 | memcpy(&branch_regs[i-1],¤t,sizeof(current)); | |
7663 | branch_regs[i-1].isconst=0; | |
7664 | branch_regs[i-1].wasconst=0; | |
630b122b | 7665 | branch_regs[i-1].u=branch_unneeded_reg[i-1]&~((1LL<<dops[i-1].rs1)|(1LL<<dops[i-1].rs2)); |
57871462 | 7666 | alloc_cc(&branch_regs[i-1],i-1); |
7667 | dirty_reg(&branch_regs[i-1],CCREG); | |
630b122b | 7668 | if(dops[i-1].rt1==31) { // JAL |
57871462 | 7669 | alloc_reg(&branch_regs[i-1],i-1,31); |
7670 | dirty_reg(&branch_regs[i-1],31); | |
57871462 | 7671 | } |
7672 | memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap)); | |
630b122b | 7673 | memcpy(constmap[i],constmap[i-1],sizeof(constmap[i])); |
57871462 | 7674 | break; |
7675 | case RJUMP: | |
7676 | memcpy(&branch_regs[i-1],¤t,sizeof(current)); | |
7677 | branch_regs[i-1].isconst=0; | |
7678 | branch_regs[i-1].wasconst=0; | |
630b122b | 7679 | branch_regs[i-1].u=branch_unneeded_reg[i-1]&~((1LL<<dops[i-1].rs1)|(1LL<<dops[i-1].rs2)); |
57871462 | 7680 | alloc_cc(&branch_regs[i-1],i-1); |
7681 | dirty_reg(&branch_regs[i-1],CCREG); | |
630b122b | 7682 | alloc_reg(&branch_regs[i-1],i-1,dops[i-1].rs1); |
7683 | if(dops[i-1].rt1!=0) { // JALR | |
7684 | alloc_reg(&branch_regs[i-1],i-1,dops[i-1].rt1); | |
7685 | dirty_reg(&branch_regs[i-1],dops[i-1].rt1); | |
57871462 | 7686 | } |
7687 | #ifdef USE_MINI_HT | |
630b122b | 7688 | if(dops[i-1].rs1==31) { // JALR |
57871462 | 7689 | alloc_reg(&branch_regs[i-1],i-1,RHASH); |
57871462 | 7690 | alloc_reg(&branch_regs[i-1],i-1,RHTBL); |
57871462 | 7691 | } |
7692 | #endif | |
7693 | memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap)); | |
630b122b | 7694 | memcpy(constmap[i],constmap[i-1],sizeof(constmap[i])); |
57871462 | 7695 | break; |
7696 | case CJUMP: | |
630b122b | 7697 | if((dops[i-1].opcode&0x3E)==4) // BEQ/BNE |
57871462 | 7698 | { |
7699 | alloc_cc(¤t,i-1); | |
7700 | dirty_reg(¤t,CCREG); | |
630b122b | 7701 | if((dops[i-1].rs1&&(dops[i-1].rs1==dops[i].rt1||dops[i-1].rs1==dops[i].rt2))|| |
7702 | (dops[i-1].rs2&&(dops[i-1].rs2==dops[i].rt1||dops[i-1].rs2==dops[i].rt2))) { | |
57871462 | 7703 | // The delay slot overwrote one of our conditions |
7704 | // Delay slot goes after the test (in order) | |
630b122b | 7705 | current.u=branch_unneeded_reg[i-1]&~((1LL<<dops[i].rs1)|(1LL<<dops[i].rs2)); |
57871462 | 7706 | current.u|=1; |
57871462 | 7707 | delayslot_alloc(¤t,i); |
7708 | current.isconst=0; | |
7709 | } | |
7710 | else | |
7711 | { | |
630b122b | 7712 | current.u=branch_unneeded_reg[i-1]&~((1LL<<dops[i-1].rs1)|(1LL<<dops[i-1].rs2)); |
57871462 | 7713 | // Alloc the branch condition registers |
630b122b | 7714 | if(dops[i-1].rs1) alloc_reg(¤t,i-1,dops[i-1].rs1); |
7715 | if(dops[i-1].rs2) alloc_reg(¤t,i-1,dops[i-1].rs2); | |
57871462 | 7716 | } |
7717 | memcpy(&branch_regs[i-1],¤t,sizeof(current)); | |
7718 | branch_regs[i-1].isconst=0; | |
7719 | branch_regs[i-1].wasconst=0; | |
7720 | memcpy(&branch_regs[i-1].regmap_entry,¤t.regmap,sizeof(current.regmap)); | |
630b122b | 7721 | memcpy(constmap[i],constmap[i-1],sizeof(constmap[i])); |
57871462 | 7722 | } |
7723 | else | |
630b122b | 7724 | if((dops[i-1].opcode&0x3E)==6) // BLEZ/BGTZ |
57871462 | 7725 | { |
7726 | alloc_cc(¤t,i-1); | |
7727 | dirty_reg(¤t,CCREG); | |
630b122b | 7728 | if(dops[i-1].rs1==dops[i].rt1||dops[i-1].rs1==dops[i].rt2) { |
57871462 | 7729 | // The delay slot overwrote the branch condition |
7730 | // Delay slot goes after the test (in order) | |
630b122b | 7731 | current.u=branch_unneeded_reg[i-1]&~((1LL<<dops[i].rs1)|(1LL<<dops[i].rs2)); |
57871462 | 7732 | current.u|=1; |
57871462 | 7733 | delayslot_alloc(¤t,i); |
7734 | current.isconst=0; | |
7735 | } | |
7736 | else | |
7737 | { | |
630b122b | 7738 | current.u=branch_unneeded_reg[i-1]&~(1LL<<dops[i-1].rs1); |
57871462 | 7739 | // Alloc the branch condition register |
630b122b | 7740 | alloc_reg(¤t,i-1,dops[i-1].rs1); |
57871462 | 7741 | } |
7742 | memcpy(&branch_regs[i-1],¤t,sizeof(current)); | |
7743 | branch_regs[i-1].isconst=0; | |
7744 | branch_regs[i-1].wasconst=0; | |
7745 | memcpy(&branch_regs[i-1].regmap_entry,¤t.regmap,sizeof(current.regmap)); | |
630b122b | 7746 | memcpy(constmap[i],constmap[i-1],sizeof(constmap[i])); |
57871462 | 7747 | } |
57871462 | 7748 | break; |
7749 | case SJUMP: | |
57871462 | 7750 | { |
7751 | alloc_cc(¤t,i-1); | |
7752 | dirty_reg(¤t,CCREG); | |
630b122b | 7753 | if(dops[i-1].rs1==dops[i].rt1||dops[i-1].rs1==dops[i].rt2) { |
57871462 | 7754 | // The delay slot overwrote the branch condition |
7755 | // Delay slot goes after the test (in order) | |
630b122b | 7756 | current.u=branch_unneeded_reg[i-1]&~((1LL<<dops[i].rs1)|(1LL<<dops[i].rs2)); |
57871462 | 7757 | current.u|=1; |
57871462 | 7758 | delayslot_alloc(¤t,i); |
7759 | current.isconst=0; | |
7760 | } | |
7761 | else | |
7762 | { | |
630b122b | 7763 | current.u=branch_unneeded_reg[i-1]&~(1LL<<dops[i-1].rs1); |
57871462 | 7764 | // Alloc the branch condition register |
630b122b | 7765 | alloc_reg(¤t,i-1,dops[i-1].rs1); |
57871462 | 7766 | } |
7767 | memcpy(&branch_regs[i-1],¤t,sizeof(current)); | |
7768 | branch_regs[i-1].isconst=0; | |
7769 | branch_regs[i-1].wasconst=0; | |
7770 | memcpy(&branch_regs[i-1].regmap_entry,¤t.regmap,sizeof(current.regmap)); | |
630b122b | 7771 | memcpy(constmap[i],constmap[i-1],sizeof(constmap[i])); |
57871462 | 7772 | } |
57871462 | 7773 | break; |
7774 | } | |
7775 | ||
630b122b | 7776 | if (dops[i-1].is_ujump) |
57871462 | 7777 | { |
630b122b | 7778 | if(dops[i-1].rt1==31) // JAL/JALR |
57871462 | 7779 | { |
7780 | // Subroutine call will return here, don't alloc any registers | |
57871462 | 7781 | current.dirty=0; |
7782 | clear_all_regs(current.regmap); | |
7783 | alloc_reg(¤t,i,CCREG); | |
7784 | dirty_reg(¤t,CCREG); | |
7785 | } | |
7786 | else if(i+1<slen) | |
7787 | { | |
7788 | // Internal branch will jump here, match registers to caller | |
57871462 | 7789 | current.dirty=0; |
7790 | clear_all_regs(current.regmap); | |
7791 | alloc_reg(¤t,i,CCREG); | |
7792 | dirty_reg(¤t,CCREG); | |
7793 | for(j=i-1;j>=0;j--) | |
7794 | { | |
259dbd60 | 7795 | if(cinfo[j].ba==start+i*4+4) { |
57871462 | 7796 | memcpy(current.regmap,branch_regs[j].regmap,sizeof(current.regmap)); |
57871462 | 7797 | current.dirty=branch_regs[j].dirty; |
7798 | break; | |
7799 | } | |
7800 | } | |
7801 | while(j>=0) { | |
259dbd60 | 7802 | if(cinfo[j].ba==start+i*4+4) { |
57871462 | 7803 | for(hr=0;hr<HOST_REGS;hr++) { |
7804 | if(current.regmap[hr]!=branch_regs[j].regmap[hr]) { | |
7805 | current.regmap[hr]=-1; | |
7806 | } | |
57871462 | 7807 | current.dirty&=branch_regs[j].dirty; |
7808 | } | |
7809 | } | |
7810 | j--; | |
7811 | } | |
7812 | } | |
7813 | } | |
7814 | } | |
7815 | ||
7816 | // Count cycles in between branches | |
259dbd60 | 7817 | cinfo[i].ccadj = CLOCK_ADJUST(cc); |
f2e25348 | 7818 | if (i > 0 && (dops[i-1].is_jump || dops[i].is_exception)) |
57871462 | 7819 | { |
7820 | cc=0; | |
7821 | } | |
71e490c5 | 7822 | #if !defined(DRC_DBG) |
630b122b | 7823 | else if(dops[i].itype==C2OP&>e_cycletab[source[i]&0x3f]>2) |
fb407447 | 7824 | { |
630b122b | 7825 | // this should really be removed since the real stalls have been implemented, |
7826 | // but doing so causes sizeable perf regression against the older version | |
7827 | u_int gtec = gte_cycletab[source[i] & 0x3f]; | |
7828 | cc += HACK_ENABLED(NDHACK_NO_STALLS) ? gtec/2 : 2; | |
fb407447 | 7829 | } |
630b122b | 7830 | else if(i>1&&dops[i].itype==STORE&&dops[i-1].itype==STORE&&dops[i-2].itype==STORE&&!dops[i].bt) |
5fdcbb5a | 7831 | { |
7832 | cc+=4; | |
7833 | } | |
630b122b | 7834 | else if(dops[i].itype==C2LS) |
fb407447 | 7835 | { |
630b122b | 7836 | // same as with C2OP |
7837 | cc += HACK_ENABLED(NDHACK_NO_STALLS) ? 4 : 2; | |
fb407447 | 7838 | } |
7839 | #endif | |
57871462 | 7840 | else |
7841 | { | |
7842 | cc++; | |
7843 | } | |
7844 | ||
630b122b | 7845 | if(!dops[i].is_ds) { |
57871462 | 7846 | regs[i].dirty=current.dirty; |
7847 | regs[i].isconst=current.isconst; | |
630b122b | 7848 | memcpy(constmap[i],current_constmap,sizeof(constmap[i])); |
57871462 | 7849 | } |
7850 | for(hr=0;hr<HOST_REGS;hr++) { | |
7851 | if(hr!=EXCLUDE_REG&®s[i].regmap[hr]>=0) { | |
7852 | if(regmap_pre[i][hr]!=regs[i].regmap[hr]) { | |
7853 | regs[i].wasconst&=~(1<<hr); | |
7854 | } | |
7855 | } | |
7856 | } | |
bdbf4466 | 7857 | //regs[i].waswritten=current.waswritten; |
57871462 | 7858 | } |
94061aa5 | 7859 | } |
9f51b4b9 | 7860 | |
94061aa5 | 7861 | static noinline void pass4_cull_unused_regs(void) |
7862 | { | |
e912c27d | 7863 | u_int last_needed_regs[4] = {0,0,0,0}; |
94061aa5 | 7864 | u_int nr=0; |
7865 | int i; | |
9f51b4b9 | 7866 | |
57871462 | 7867 | for (i=slen-1;i>=0;i--) |
7868 | { | |
7869 | int hr; | |
e912c27d | 7870 | __builtin_prefetch(regs[i-2].regmap); |
630b122b | 7871 | if(dops[i].is_jump) |
57871462 | 7872 | { |
259dbd60 | 7873 | if(cinfo[i].ba<start || cinfo[i].ba>=(start+slen*4)) |
57871462 | 7874 | { |
7875 | // Branch out of this block, don't need anything | |
7876 | nr=0; | |
7877 | } | |
7878 | else | |
7879 | { | |
7880 | // Internal branch | |
7881 | // Need whatever matches the target | |
7882 | nr=0; | |
259dbd60 | 7883 | int t=(cinfo[i].ba-start)>>2; |
57871462 | 7884 | for(hr=0;hr<HOST_REGS;hr++) |
7885 | { | |
7886 | if(regs[i].regmap_entry[hr]>=0) { | |
7887 | if(regs[i].regmap_entry[hr]==regs[t].regmap_entry[hr]) nr|=1<<hr; | |
7888 | } | |
7889 | } | |
7890 | } | |
7891 | // Conditional branch may need registers for following instructions | |
630b122b | 7892 | if (!dops[i].is_ujump) |
57871462 | 7893 | { |
7894 | if(i<slen-2) { | |
e912c27d | 7895 | nr |= last_needed_regs[(i+2) & 3]; |
57871462 | 7896 | for(hr=0;hr<HOST_REGS;hr++) |
7897 | { | |
7898 | if(regmap_pre[i+2][hr]>=0&&get_reg(regs[i+2].regmap_entry,regmap_pre[i+2][hr])<0) nr&=~(1<<hr); | |
7899 | //if((regmap_entry[i+2][hr])>=0) if(!((nr>>hr)&1)) printf("%x-bogus(%d=%d)\n",start+i*4,hr,regmap_entry[i+2][hr]); | |
7900 | } | |
7901 | } | |
7902 | } | |
7903 | // Don't need stuff which is overwritten | |
f5955059 | 7904 | //if(regs[i].regmap[hr]!=regmap_pre[i][hr]) nr&=~(1<<hr); |
7905 | //if(regs[i].regmap[hr]<0) nr&=~(1<<hr); | |
57871462 | 7906 | // Merge in delay slot |
e912c27d | 7907 | if (dops[i+1].rt1) nr &= ~get_regm(regs[i].regmap, dops[i+1].rt1); |
7908 | if (dops[i+1].rt2) nr &= ~get_regm(regs[i].regmap, dops[i+1].rt2); | |
7909 | nr |= get_regm(regmap_pre[i], dops[i+1].rs1); | |
7910 | nr |= get_regm(regmap_pre[i], dops[i+1].rs2); | |
7911 | nr |= get_regm(regs[i].regmap_entry, dops[i+1].rs1); | |
7912 | nr |= get_regm(regs[i].regmap_entry, dops[i+1].rs2); | |
7913 | if (ram_offset && (dops[i+1].is_load || dops[i+1].is_store)) { | |
7914 | nr |= get_regm(regmap_pre[i], ROREG); | |
7915 | nr |= get_regm(regs[i].regmap_entry, ROREG); | |
7916 | } | |
7917 | if (dops[i+1].is_store) { | |
7918 | nr |= get_regm(regmap_pre[i], INVCP); | |
7919 | nr |= get_regm(regs[i].regmap_entry, INVCP); | |
57871462 | 7920 | } |
7921 | } | |
259dbd60 | 7922 | else if (dops[i].is_exception) |
57871462 | 7923 | { |
259dbd60 | 7924 | // SYSCALL instruction, etc |
57871462 | 7925 | nr=0; |
7926 | } | |
7927 | else // Non-branch | |
7928 | { | |
7929 | if(i<slen-1) { | |
7930 | for(hr=0;hr<HOST_REGS;hr++) { | |
7931 | if(regmap_pre[i+1][hr]>=0&&get_reg(regs[i+1].regmap_entry,regmap_pre[i+1][hr])<0) nr&=~(1<<hr); | |
7932 | if(regs[i].regmap[hr]!=regmap_pre[i+1][hr]) nr&=~(1<<hr); | |
7933 | if(regs[i].regmap[hr]!=regmap_pre[i][hr]) nr&=~(1<<hr); | |
7934 | if(regs[i].regmap[hr]<0) nr&=~(1<<hr); | |
7935 | } | |
7936 | } | |
7937 | } | |
e912c27d | 7938 | // Overwritten registers are not needed |
7939 | if (dops[i].rt1) nr &= ~get_regm(regs[i].regmap, dops[i].rt1); | |
7940 | if (dops[i].rt2) nr &= ~get_regm(regs[i].regmap, dops[i].rt2); | |
7941 | nr &= ~get_regm(regs[i].regmap, FTEMP); | |
7942 | // Source registers are needed | |
7943 | nr |= get_regm(regmap_pre[i], dops[i].rs1); | |
7944 | nr |= get_regm(regmap_pre[i], dops[i].rs2); | |
7945 | nr |= get_regm(regs[i].regmap_entry, dops[i].rs1); | |
7946 | nr |= get_regm(regs[i].regmap_entry, dops[i].rs2); | |
7947 | if (ram_offset && (dops[i].is_load || dops[i].is_store)) { | |
7948 | nr |= get_regm(regmap_pre[i], ROREG); | |
7949 | nr |= get_regm(regs[i].regmap_entry, ROREG); | |
7950 | } | |
7951 | if (dops[i].is_store) { | |
7952 | nr |= get_regm(regmap_pre[i], INVCP); | |
7953 | nr |= get_regm(regs[i].regmap_entry, INVCP); | |
7954 | } | |
7955 | ||
7956 | if (i > 0 && !dops[i].bt && regs[i].wasdirty) | |
57871462 | 7957 | for(hr=0;hr<HOST_REGS;hr++) |
7958 | { | |
57871462 | 7959 | // Don't store a register immediately after writing it, |
7960 | // may prevent dual-issue. | |
7961 | // But do so if this is a branch target, otherwise we | |
7962 | // might have to load the register before the branch. | |
e912c27d | 7963 | if((regs[i].wasdirty>>hr)&1) { |
630b122b | 7964 | if((regmap_pre[i][hr]>0&&!((unneeded_reg[i]>>regmap_pre[i][hr])&1))) { |
91af94f0 | 7965 | if(dops[i-1].rt1==regmap_pre[i][hr]) nr|=1<<hr; |
7966 | if(dops[i-1].rt2==regmap_pre[i][hr]) nr|=1<<hr; | |
57871462 | 7967 | } |
630b122b | 7968 | if((regs[i].regmap_entry[hr]>0&&!((unneeded_reg[i]>>regs[i].regmap_entry[hr])&1))) { |
91af94f0 | 7969 | if(dops[i-1].rt1==regs[i].regmap_entry[hr]) nr|=1<<hr; |
7970 | if(dops[i-1].rt2==regs[i].regmap_entry[hr]) nr|=1<<hr; | |
57871462 | 7971 | } |
7972 | } | |
7973 | } | |
7974 | // Cycle count is needed at branches. Assume it is needed at the target too. | |
5753f874 | 7975 | if (i == 0 || dops[i].bt || dops[i].may_except || dops[i].itype == CJUMP) { |
57871462 | 7976 | if(regmap_pre[i][HOST_CCREG]==CCREG) nr|=1<<HOST_CCREG; |
7977 | if(regs[i].regmap_entry[HOST_CCREG]==CCREG) nr|=1<<HOST_CCREG; | |
7978 | } | |
7979 | // Save it | |
e912c27d | 7980 | last_needed_regs[i & 3] = nr; |
9f51b4b9 | 7981 | |
57871462 | 7982 | // Deallocate unneeded registers |
7983 | for(hr=0;hr<HOST_REGS;hr++) | |
7984 | { | |
7985 | if(!((nr>>hr)&1)) { | |
7986 | if(regs[i].regmap_entry[hr]!=CCREG) regs[i].regmap_entry[hr]=-1; | |
630b122b | 7987 | if(dops[i].is_jump) |
57871462 | 7988 | { |
630b122b | 7989 | int map1 = 0, map2 = 0, temp = 0; // or -1 ?? |
7990 | if (dops[i+1].is_load || dops[i+1].is_store) | |
7991 | map1 = ROREG; | |
7992 | if (dops[i+1].is_store) | |
7993 | map2 = INVCP; | |
7994 | if(dops[i+1].itype==LOADLR || dops[i+1].itype==STORELR || dops[i+1].itype==C2LS) | |
7995 | temp = FTEMP; | |
91af94f0 | 7996 | if(regs[i].regmap[hr]!=dops[i].rs1 && regs[i].regmap[hr]!=dops[i].rs2 && |
7997 | regs[i].regmap[hr]!=dops[i].rt1 && regs[i].regmap[hr]!=dops[i].rt2 && | |
7998 | regs[i].regmap[hr]!=dops[i+1].rt1 && regs[i].regmap[hr]!=dops[i+1].rt2 && | |
630b122b | 7999 | regs[i].regmap[hr]!=dops[i+1].rs1 && regs[i].regmap[hr]!=dops[i+1].rs2 && |
91af94f0 | 8000 | regs[i].regmap[hr]!=temp && regs[i].regmap[hr]!=PTEMP && |
57871462 | 8001 | regs[i].regmap[hr]!=RHASH && regs[i].regmap[hr]!=RHTBL && |
8002 | regs[i].regmap[hr]!=RTEMP && regs[i].regmap[hr]!=CCREG && | |
630b122b | 8003 | regs[i].regmap[hr]!=map1 && regs[i].regmap[hr]!=map2) |
57871462 | 8004 | { |
8005 | regs[i].regmap[hr]=-1; | |
8006 | regs[i].isconst&=~(1<<hr); | |
214f6f35 | 8007 | regs[i].dirty&=~(1<<hr); |
8008 | regs[i+1].wasdirty&=~(1<<hr); | |
91af94f0 | 8009 | if(branch_regs[i].regmap[hr]!=dops[i].rs1 && branch_regs[i].regmap[hr]!=dops[i].rs2 && |
8010 | branch_regs[i].regmap[hr]!=dops[i].rt1 && branch_regs[i].regmap[hr]!=dops[i].rt2 && | |
8011 | branch_regs[i].regmap[hr]!=dops[i+1].rt1 && branch_regs[i].regmap[hr]!=dops[i+1].rt2 && | |
630b122b | 8012 | branch_regs[i].regmap[hr]!=dops[i+1].rs1 && branch_regs[i].regmap[hr]!=dops[i+1].rs2 && |
91af94f0 | 8013 | branch_regs[i].regmap[hr]!=temp && branch_regs[i].regmap[hr]!=PTEMP && |
57871462 | 8014 | branch_regs[i].regmap[hr]!=RHASH && branch_regs[i].regmap[hr]!=RHTBL && |
8015 | branch_regs[i].regmap[hr]!=RTEMP && branch_regs[i].regmap[hr]!=CCREG && | |
630b122b | 8016 | branch_regs[i].regmap[hr]!=map1 && branch_regs[i].regmap[hr]!=map2) |
57871462 | 8017 | { |
8018 | branch_regs[i].regmap[hr]=-1; | |
8019 | branch_regs[i].regmap_entry[hr]=-1; | |
630b122b | 8020 | if (!dops[i].is_ujump) |
57871462 | 8021 | { |
630b122b | 8022 | if (i < slen-2) { |
57871462 | 8023 | regmap_pre[i+2][hr]=-1; |
79c75f1b | 8024 | regs[i+2].wasconst&=~(1<<hr); |
57871462 | 8025 | } |
8026 | } | |
8027 | } | |
8028 | } | |
8029 | } | |
8030 | else | |
8031 | { | |
8032 | // Non-branch | |
8033 | if(i>0) | |
8034 | { | |
630b122b | 8035 | int map1 = -1, map2 = -1, temp=-1; |
8036 | if (dops[i].is_load || dops[i].is_store) | |
8037 | map1 = ROREG; | |
8038 | if (dops[i].is_store) | |
8039 | map2 = INVCP; | |
8040 | if (dops[i].itype==LOADLR || dops[i].itype==STORELR || dops[i].itype==C2LS) | |
8041 | temp = FTEMP; | |
91af94f0 | 8042 | if(regs[i].regmap[hr]!=dops[i].rt1 && regs[i].regmap[hr]!=dops[i].rt2 && |
630b122b | 8043 | regs[i].regmap[hr]!=dops[i].rs1 && regs[i].regmap[hr]!=dops[i].rs2 && |
91af94f0 | 8044 | regs[i].regmap[hr]!=temp && regs[i].regmap[hr]!=map1 && regs[i].regmap[hr]!=map2 && |
630b122b | 8045 | //(dops[i].itype!=SPAN||regs[i].regmap[hr]!=CCREG) |
8046 | regs[i].regmap[hr] != CCREG) | |
57871462 | 8047 | { |
630b122b | 8048 | if(i<slen-1&&!dops[i].is_ds) { |
8049 | assert(regs[i].regmap[hr]<64); | |
8050 | if(regmap_pre[i+1][hr]!=-1 || regs[i].regmap[hr]>0) | |
57871462 | 8051 | if(regmap_pre[i+1][hr]!=regs[i].regmap[hr]) |
57871462 | 8052 | { |
c43b5311 | 8053 | SysPrintf("fail: %x (%d %d!=%d)\n",start+i*4,hr,regmap_pre[i+1][hr],regs[i].regmap[hr]); |
57871462 | 8054 | assert(regmap_pre[i+1][hr]==regs[i].regmap[hr]); |
8055 | } | |
8056 | regmap_pre[i+1][hr]=-1; | |
8057 | if(regs[i+1].regmap_entry[hr]==CCREG) regs[i+1].regmap_entry[hr]=-1; | |
79c75f1b | 8058 | regs[i+1].wasconst&=~(1<<hr); |
57871462 | 8059 | } |
8060 | regs[i].regmap[hr]=-1; | |
8061 | regs[i].isconst&=~(1<<hr); | |
214f6f35 | 8062 | regs[i].dirty&=~(1<<hr); |
8063 | regs[i+1].wasdirty&=~(1<<hr); | |
57871462 | 8064 | } |
8065 | } | |
8066 | } | |
630b122b | 8067 | } // if needed |
8068 | } // for hr | |
57871462 | 8069 | } |
94061aa5 | 8070 | } |
9f51b4b9 | 8071 | |
94061aa5 | 8072 | // If a register is allocated during a loop, try to allocate it for the |
8073 | // entire loop, if possible. This avoids loading/storing registers | |
8074 | // inside of the loop. | |
8075 | static noinline void pass5a_preallocate1(void) | |
8076 | { | |
8077 | int i, j, hr; | |
57871462 | 8078 | signed char f_regmap[HOST_REGS]; |
8079 | clear_all_regs(f_regmap); | |
8080 | for(i=0;i<slen-1;i++) | |
8081 | { | |
630b122b | 8082 | if(dops[i].itype==UJUMP||dops[i].itype==CJUMP||dops[i].itype==SJUMP) |
57871462 | 8083 | { |
259dbd60 | 8084 | if(cinfo[i].ba>=start && cinfo[i].ba<(start+i*4)) |
630b122b | 8085 | if(dops[i+1].itype==NOP||dops[i+1].itype==MOV||dops[i+1].itype==ALU |
8086 | ||dops[i+1].itype==SHIFTIMM||dops[i+1].itype==IMM16||dops[i+1].itype==LOAD | |
f2e25348 | 8087 | ||dops[i+1].itype==STORE||dops[i+1].itype==STORELR |
8088 | ||dops[i+1].itype==SHIFT | |
630b122b | 8089 | ||dops[i+1].itype==COP2||dops[i+1].itype==C2LS||dops[i+1].itype==C2OP) |
57871462 | 8090 | { |
259dbd60 | 8091 | int t=(cinfo[i].ba-start)>>2; |
630b122b | 8092 | if(t > 0 && !dops[t-1].is_jump) // loop_preload can't handle jumps into delay slots |
8093 | if(t<2||(dops[t-2].itype!=UJUMP&&dops[t-2].itype!=RJUMP)||dops[t-2].rt1!=31) // call/ret assumes no registers allocated | |
57871462 | 8094 | for(hr=0;hr<HOST_REGS;hr++) |
8095 | { | |
630b122b | 8096 | if(regs[i].regmap[hr]>=0) { |
b372a952 | 8097 | if(f_regmap[hr]!=regs[i].regmap[hr]) { |
8098 | // dealloc old register | |
8099 | int n; | |
8100 | for(n=0;n<HOST_REGS;n++) | |
8101 | { | |
8102 | if(f_regmap[n]==regs[i].regmap[hr]) {f_regmap[n]=-1;} | |
8103 | } | |
8104 | // and alloc new one | |
8105 | f_regmap[hr]=regs[i].regmap[hr]; | |
8106 | } | |
8107 | } | |
630b122b | 8108 | if(branch_regs[i].regmap[hr]>=0) { |
b372a952 | 8109 | if(f_regmap[hr]!=branch_regs[i].regmap[hr]) { |
8110 | // dealloc old register | |
8111 | int n; | |
8112 | for(n=0;n<HOST_REGS;n++) | |
8113 | { | |
8114 | if(f_regmap[n]==branch_regs[i].regmap[hr]) {f_regmap[n]=-1;} | |
8115 | } | |
8116 | // and alloc new one | |
8117 | f_regmap[hr]=branch_regs[i].regmap[hr]; | |
8118 | } | |
8119 | } | |
630b122b | 8120 | if(dops[i].ooo) { |
259dbd60 | 8121 | if(count_free_regs(regs[i].regmap)<=cinfo[i+1].min_free_regs) |
e1190b87 | 8122 | f_regmap[hr]=branch_regs[i].regmap[hr]; |
8123 | }else{ | |
259dbd60 | 8124 | if(count_free_regs(branch_regs[i].regmap)<=cinfo[i+1].min_free_regs) |
57871462 | 8125 | f_regmap[hr]=branch_regs[i].regmap[hr]; |
8126 | } | |
8127 | // Avoid dirty->clean transition | |
e1190b87 | 8128 | #ifdef DESTRUCTIVE_WRITEBACK |
57871462 | 8129 | if(t>0) if(get_reg(regmap_pre[t],f_regmap[hr])>=0) if((regs[t].wasdirty>>get_reg(regmap_pre[t],f_regmap[hr]))&1) f_regmap[hr]=-1; |
e1190b87 | 8130 | #endif |
8131 | // This check is only strictly required in the DESTRUCTIVE_WRITEBACK | |
8132 | // case above, however it's always a good idea. We can't hoist the | |
8133 | // load if the register was already allocated, so there's no point | |
8134 | // wasting time analyzing most of these cases. It only "succeeds" | |
8135 | // when the mapping was different and the load can be replaced with | |
8136 | // a mov, which is of negligible benefit. So such cases are | |
8137 | // skipped below. | |
57871462 | 8138 | if(f_regmap[hr]>0) { |
198df76f | 8139 | if(regs[t].regmap[hr]==f_regmap[hr]||(regs[t].regmap_entry[hr]<0&&get_reg(regmap_pre[t],f_regmap[hr])<0)) { |
57871462 | 8140 | int r=f_regmap[hr]; |
8141 | for(j=t;j<=i;j++) | |
8142 | { | |
259dbd60 | 8143 | //printf("Test %x -> %x, %x %d/%d\n",start+i*4,cinfo[i].ba,start+j*4,hr,r); |
57871462 | 8144 | if(r<34&&((unneeded_reg[j]>>r)&1)) break; |
630b122b | 8145 | assert(r < 64); |
91af94f0 | 8146 | if(regs[j].regmap[hr]==f_regmap[hr]&&f_regmap[hr]<TEMPREG) { |
259dbd60 | 8147 | //printf("Hit %x -> %x, %x %d/%d\n",start+i*4,cinfo[i].ba,start+j*4,hr,r); |
57871462 | 8148 | int k; |
8149 | if(regs[i].regmap[hr]==-1&&branch_regs[i].regmap[hr]==-1) { | |
648d9448 | 8150 | if(get_reg(regs[i].regmap,f_regmap[hr])>=0) break; |
57871462 | 8151 | if(get_reg(regs[i+2].regmap,f_regmap[hr])>=0) break; |
57871462 | 8152 | k=i; |
8153 | while(k>1&®s[k-1].regmap[hr]==-1) { | |
259dbd60 | 8154 | if(count_free_regs(regs[k-1].regmap)<=cinfo[k-1].min_free_regs) { |
e1190b87 | 8155 | //printf("no free regs for store %x\n",start+(k-1)*4); |
8156 | break; | |
57871462 | 8157 | } |
57871462 | 8158 | if(get_reg(regs[k-1].regmap,f_regmap[hr])>=0) { |
8159 | //printf("no-match due to different register\n"); | |
8160 | break; | |
8161 | } | |
630b122b | 8162 | if (dops[k-2].is_jump) { |
57871462 | 8163 | //printf("no-match due to branch\n"); |
8164 | break; | |
8165 | } | |
8166 | // call/ret fast path assumes no registers allocated | |
630b122b | 8167 | if(k>2&&(dops[k-3].itype==UJUMP||dops[k-3].itype==RJUMP)&&dops[k-3].rt1==31) { |
57871462 | 8168 | break; |
8169 | } | |
57871462 | 8170 | k--; |
8171 | } | |
57871462 | 8172 | if(regs[k-1].regmap[hr]==f_regmap[hr]&®map_pre[k][hr]==f_regmap[hr]) { |
8173 | //printf("Extend r%d, %x ->\n",hr,start+k*4); | |
8174 | while(k<i) { | |
8175 | regs[k].regmap_entry[hr]=f_regmap[hr]; | |
8176 | regs[k].regmap[hr]=f_regmap[hr]; | |
8177 | regmap_pre[k+1][hr]=f_regmap[hr]; | |
8178 | regs[k].wasdirty&=~(1<<hr); | |
8179 | regs[k].dirty&=~(1<<hr); | |
8180 | regs[k].wasdirty|=(1<<hr)®s[k-1].dirty; | |
8181 | regs[k].dirty|=(1<<hr)®s[k].wasdirty; | |
8182 | regs[k].wasconst&=~(1<<hr); | |
8183 | regs[k].isconst&=~(1<<hr); | |
8184 | k++; | |
8185 | } | |
8186 | } | |
8187 | else { | |
8188 | //printf("Fail Extend r%d, %x ->\n",hr,start+k*4); | |
8189 | break; | |
8190 | } | |
8191 | assert(regs[i-1].regmap[hr]==f_regmap[hr]); | |
8192 | if(regs[i-1].regmap[hr]==f_regmap[hr]&®map_pre[i][hr]==f_regmap[hr]) { | |
8193 | //printf("OK fill %x (r%d)\n",start+i*4,hr); | |
8194 | regs[i].regmap_entry[hr]=f_regmap[hr]; | |
8195 | regs[i].regmap[hr]=f_regmap[hr]; | |
8196 | regs[i].wasdirty&=~(1<<hr); | |
8197 | regs[i].dirty&=~(1<<hr); | |
8198 | regs[i].wasdirty|=(1<<hr)®s[i-1].dirty; | |
8199 | regs[i].dirty|=(1<<hr)®s[i-1].dirty; | |
8200 | regs[i].wasconst&=~(1<<hr); | |
8201 | regs[i].isconst&=~(1<<hr); | |
8202 | branch_regs[i].regmap_entry[hr]=f_regmap[hr]; | |
8203 | branch_regs[i].wasdirty&=~(1<<hr); | |
8204 | branch_regs[i].wasdirty|=(1<<hr)®s[i].dirty; | |
8205 | branch_regs[i].regmap[hr]=f_regmap[hr]; | |
8206 | branch_regs[i].dirty&=~(1<<hr); | |
8207 | branch_regs[i].dirty|=(1<<hr)®s[i].dirty; | |
8208 | branch_regs[i].wasconst&=~(1<<hr); | |
8209 | branch_regs[i].isconst&=~(1<<hr); | |
630b122b | 8210 | if (!dops[i].is_ujump) { |
57871462 | 8211 | regmap_pre[i+2][hr]=f_regmap[hr]; |
8212 | regs[i+2].wasdirty&=~(1<<hr); | |
8213 | regs[i+2].wasdirty|=(1<<hr)®s[i].dirty; | |
57871462 | 8214 | } |
8215 | } | |
8216 | } | |
8217 | for(k=t;k<j;k++) { | |
e1190b87 | 8218 | // Alloc register clean at beginning of loop, |
8219 | // but may dirty it in pass 6 | |
57871462 | 8220 | regs[k].regmap_entry[hr]=f_regmap[hr]; |
8221 | regs[k].regmap[hr]=f_regmap[hr]; | |
57871462 | 8222 | regs[k].dirty&=~(1<<hr); |
8223 | regs[k].wasconst&=~(1<<hr); | |
8224 | regs[k].isconst&=~(1<<hr); | |
630b122b | 8225 | if (dops[k].is_jump) { |
e1190b87 | 8226 | branch_regs[k].regmap_entry[hr]=f_regmap[hr]; |
8227 | branch_regs[k].regmap[hr]=f_regmap[hr]; | |
8228 | branch_regs[k].dirty&=~(1<<hr); | |
8229 | branch_regs[k].wasconst&=~(1<<hr); | |
8230 | branch_regs[k].isconst&=~(1<<hr); | |
630b122b | 8231 | if (!dops[k].is_ujump) { |
e1190b87 | 8232 | regmap_pre[k+2][hr]=f_regmap[hr]; |
8233 | regs[k+2].wasdirty&=~(1<<hr); | |
e1190b87 | 8234 | } |
8235 | } | |
8236 | else | |
8237 | { | |
8238 | regmap_pre[k+1][hr]=f_regmap[hr]; | |
8239 | regs[k+1].wasdirty&=~(1<<hr); | |
8240 | } | |
57871462 | 8241 | } |
8242 | if(regs[j].regmap[hr]==f_regmap[hr]) | |
8243 | regs[j].regmap_entry[hr]=f_regmap[hr]; | |
8244 | break; | |
8245 | } | |
8246 | if(j==i) break; | |
8247 | if(regs[j].regmap[hr]>=0) | |
8248 | break; | |
8249 | if(get_reg(regs[j].regmap,f_regmap[hr])>=0) { | |
8250 | //printf("no-match due to different register\n"); | |
8251 | break; | |
8252 | } | |
630b122b | 8253 | if (dops[j].is_ujump) |
e1190b87 | 8254 | { |
8255 | // Stop on unconditional branch | |
8256 | break; | |
8257 | } | |
630b122b | 8258 | if(dops[j].itype==CJUMP||dops[j].itype==SJUMP) |
e1190b87 | 8259 | { |
630b122b | 8260 | if(dops[j].ooo) { |
259dbd60 | 8261 | if(count_free_regs(regs[j].regmap)<=cinfo[j+1].min_free_regs) |
e1190b87 | 8262 | break; |
8263 | }else{ | |
259dbd60 | 8264 | if(count_free_regs(branch_regs[j].regmap)<=cinfo[j+1].min_free_regs) |
e1190b87 | 8265 | break; |
8266 | } | |
8267 | if(get_reg(branch_regs[j].regmap,f_regmap[hr])>=0) { | |
8268 | //printf("no-match due to different register (branch)\n"); | |
57871462 | 8269 | break; |
8270 | } | |
8271 | } | |
259dbd60 | 8272 | if(count_free_regs(regs[j].regmap)<=cinfo[j].min_free_regs) { |
e1190b87 | 8273 | //printf("No free regs for store %x\n",start+j*4); |
8274 | break; | |
8275 | } | |
630b122b | 8276 | assert(f_regmap[hr]<64); |
57871462 | 8277 | } |
8278 | } | |
8279 | } | |
8280 | } | |
8281 | } | |
8282 | }else{ | |
198df76f | 8283 | // Non branch or undetermined branch target |
57871462 | 8284 | for(hr=0;hr<HOST_REGS;hr++) |
8285 | { | |
8286 | if(hr!=EXCLUDE_REG) { | |
630b122b | 8287 | if(regs[i].regmap[hr]>=0) { |
b372a952 | 8288 | if(f_regmap[hr]!=regs[i].regmap[hr]) { |
8289 | // dealloc old register | |
8290 | int n; | |
8291 | for(n=0;n<HOST_REGS;n++) | |
8292 | { | |
8293 | if(f_regmap[n]==regs[i].regmap[hr]) {f_regmap[n]=-1;} | |
8294 | } | |
94061aa5 | 8295 | // and alloc new one |
8296 | f_regmap[hr]=regs[i].regmap[hr]; | |
8297 | } | |
8298 | } | |
8299 | } | |
8300 | } | |
8301 | // Try to restore cycle count at branch targets | |
8302 | if(dops[i].bt) { | |
8303 | for(j=i;j<slen-1;j++) { | |
8304 | if(regs[j].regmap[HOST_CCREG]!=-1) break; | |
259dbd60 | 8305 | if(count_free_regs(regs[j].regmap)<=cinfo[j].min_free_regs) { |
94061aa5 | 8306 | //printf("no free regs for store %x\n",start+j*4); |
8307 | break; | |
8308 | } | |
8309 | } | |
8310 | if(regs[j].regmap[HOST_CCREG]==CCREG) { | |
8311 | int k=i; | |
8312 | //printf("Extend CC, %x -> %x\n",start+k*4,start+j*4); | |
8313 | while(k<j) { | |
8314 | regs[k].regmap_entry[HOST_CCREG]=CCREG; | |
8315 | regs[k].regmap[HOST_CCREG]=CCREG; | |
8316 | regmap_pre[k+1][HOST_CCREG]=CCREG; | |
8317 | regs[k+1].wasdirty|=1<<HOST_CCREG; | |
8318 | regs[k].dirty|=1<<HOST_CCREG; | |
8319 | regs[k].wasconst&=~(1<<HOST_CCREG); | |
8320 | regs[k].isconst&=~(1<<HOST_CCREG); | |
8321 | k++; | |
8322 | } | |
8323 | regs[j].regmap_entry[HOST_CCREG]=CCREG; | |
8324 | } | |
8325 | // Work backwards from the branch target | |
8326 | if(j>i&&f_regmap[HOST_CCREG]==CCREG) | |
8327 | { | |
8328 | //printf("Extend backwards\n"); | |
8329 | int k; | |
8330 | k=i; | |
8331 | while(regs[k-1].regmap[HOST_CCREG]==-1) { | |
259dbd60 | 8332 | if(count_free_regs(regs[k-1].regmap)<=cinfo[k-1].min_free_regs) { |
94061aa5 | 8333 | //printf("no free regs for store %x\n",start+(k-1)*4); |
8334 | break; | |
8335 | } | |
8336 | k--; | |
8337 | } | |
8338 | if(regs[k-1].regmap[HOST_CCREG]==CCREG) { | |
8339 | //printf("Extend CC, %x ->\n",start+k*4); | |
8340 | while(k<=i) { | |
8341 | regs[k].regmap_entry[HOST_CCREG]=CCREG; | |
8342 | regs[k].regmap[HOST_CCREG]=CCREG; | |
8343 | regmap_pre[k+1][HOST_CCREG]=CCREG; | |
8344 | regs[k+1].wasdirty|=1<<HOST_CCREG; | |
8345 | regs[k].dirty|=1<<HOST_CCREG; | |
8346 | regs[k].wasconst&=~(1<<HOST_CCREG); | |
8347 | regs[k].isconst&=~(1<<HOST_CCREG); | |
8348 | k++; | |
8349 | } | |
8350 | } | |
8351 | else { | |
8352 | //printf("Fail Extend CC, %x ->\n",start+k*4); | |
8353 | } | |
8354 | } | |
8355 | } | |
f2e25348 | 8356 | if(dops[i].itype!=STORE&&dops[i].itype!=STORELR&&dops[i].itype!=SHIFT&& |
94061aa5 | 8357 | dops[i].itype!=NOP&&dops[i].itype!=MOV&&dops[i].itype!=ALU&&dops[i].itype!=SHIFTIMM&& |
f2e25348 | 8358 | dops[i].itype!=IMM16&&dops[i].itype!=LOAD) |
94061aa5 | 8359 | { |
8360 | memcpy(f_regmap,regs[i].regmap,sizeof(f_regmap)); | |
8361 | } | |
8362 | } | |
8363 | } | |
8364 | } | |
8365 | ||
8366 | // This allocates registers (if possible) one instruction prior | |
8367 | // to use, which can avoid a load-use penalty on certain CPUs. | |
8368 | static noinline void pass5b_preallocate2(void) | |
8369 | { | |
8370 | int i, hr; | |
8371 | for(i=0;i<slen-1;i++) | |
8372 | { | |
8373 | if (!i || !dops[i-1].is_jump) | |
8374 | { | |
8375 | if(!dops[i+1].bt) | |
8376 | { | |
259dbd60 | 8377 | int j, can_steal = 1; |
8378 | for (j = i; j < i + 2; j++) { | |
8379 | int free_regs = 0; | |
8380 | if (cinfo[j].min_free_regs == 0) | |
8381 | continue; | |
8382 | for (hr = 0; hr < HOST_REGS; hr++) | |
8383 | if (hr != EXCLUDE_REG && regs[j].regmap[hr] < 0) | |
8384 | free_regs++; | |
8385 | if (free_regs <= cinfo[j].min_free_regs) { | |
8386 | can_steal = 0; | |
8387 | break; | |
8388 | } | |
8389 | } | |
8390 | if (!can_steal) | |
8391 | continue; | |
94061aa5 | 8392 | if(dops[i].itype==ALU||dops[i].itype==MOV||dops[i].itype==LOAD||dops[i].itype==SHIFTIMM||dops[i].itype==IMM16 |
f2e25348 | 8393 | ||(dops[i].itype==COP2&&dops[i].opcode2<3)) |
94061aa5 | 8394 | { |
8395 | if(dops[i+1].rs1) { | |
8396 | if((hr=get_reg(regs[i+1].regmap,dops[i+1].rs1))>=0) | |
8397 | { | |
8398 | if(regs[i].regmap[hr]<0&®s[i+1].regmap_entry[hr]<0) | |
8399 | { | |
8400 | regs[i].regmap[hr]=regs[i+1].regmap[hr]; | |
8401 | regmap_pre[i+1][hr]=regs[i+1].regmap[hr]; | |
8402 | regs[i+1].regmap_entry[hr]=regs[i+1].regmap[hr]; | |
8403 | regs[i].isconst&=~(1<<hr); | |
8404 | regs[i].isconst|=regs[i+1].isconst&(1<<hr); | |
8405 | constmap[i][hr]=constmap[i+1][hr]; | |
8406 | regs[i+1].wasdirty&=~(1<<hr); | |
8407 | regs[i].dirty&=~(1<<hr); | |
8408 | } | |
8409 | } | |
8410 | } | |
8411 | if(dops[i+1].rs2) { | |
8412 | if((hr=get_reg(regs[i+1].regmap,dops[i+1].rs2))>=0) | |
8413 | { | |
8414 | if(regs[i].regmap[hr]<0&®s[i+1].regmap_entry[hr]<0) | |
8415 | { | |
8416 | regs[i].regmap[hr]=regs[i+1].regmap[hr]; | |
8417 | regmap_pre[i+1][hr]=regs[i+1].regmap[hr]; | |
8418 | regs[i+1].regmap_entry[hr]=regs[i+1].regmap[hr]; | |
8419 | regs[i].isconst&=~(1<<hr); | |
8420 | regs[i].isconst|=regs[i+1].isconst&(1<<hr); | |
8421 | constmap[i][hr]=constmap[i+1][hr]; | |
8422 | regs[i+1].wasdirty&=~(1<<hr); | |
8423 | regs[i].dirty&=~(1<<hr); | |
8424 | } | |
8425 | } | |
8426 | } | |
8427 | // Preload target address for load instruction (non-constant) | |
8428 | if(dops[i+1].itype==LOAD&&dops[i+1].rs1&&get_reg(regs[i+1].regmap,dops[i+1].rs1)<0) { | |
f2e25348 | 8429 | if((hr=get_reg_w(regs[i+1].regmap, dops[i+1].rt1))>=0) |
94061aa5 | 8430 | { |
8431 | if(regs[i].regmap[hr]<0&®s[i+1].regmap_entry[hr]<0) | |
8432 | { | |
8433 | regs[i].regmap[hr]=dops[i+1].rs1; | |
8434 | regmap_pre[i+1][hr]=dops[i+1].rs1; | |
8435 | regs[i+1].regmap_entry[hr]=dops[i+1].rs1; | |
8436 | regs[i].isconst&=~(1<<hr); | |
8437 | regs[i].isconst|=regs[i+1].isconst&(1<<hr); | |
8438 | constmap[i][hr]=constmap[i+1][hr]; | |
8439 | regs[i+1].wasdirty&=~(1<<hr); | |
8440 | regs[i].dirty&=~(1<<hr); | |
8441 | } | |
8442 | } | |
8443 | } | |
8444 | // Load source into target register | |
8445 | if(dops[i+1].use_lt1&&get_reg(regs[i+1].regmap,dops[i+1].rs1)<0) { | |
f2e25348 | 8446 | if((hr=get_reg_w(regs[i+1].regmap, dops[i+1].rt1))>=0) |
94061aa5 | 8447 | { |
8448 | if(regs[i].regmap[hr]<0&®s[i+1].regmap_entry[hr]<0) | |
8449 | { | |
8450 | regs[i].regmap[hr]=dops[i+1].rs1; | |
8451 | regmap_pre[i+1][hr]=dops[i+1].rs1; | |
8452 | regs[i+1].regmap_entry[hr]=dops[i+1].rs1; | |
8453 | regs[i].isconst&=~(1<<hr); | |
8454 | regs[i].isconst|=regs[i+1].isconst&(1<<hr); | |
8455 | constmap[i][hr]=constmap[i+1][hr]; | |
8456 | regs[i+1].wasdirty&=~(1<<hr); | |
8457 | regs[i].dirty&=~(1<<hr); | |
8458 | } | |
8459 | } | |
8460 | } | |
8461 | // Address for store instruction (non-constant) | |
259dbd60 | 8462 | if (dops[i+1].is_store) { // SB/SH/SW/SWC2 |
94061aa5 | 8463 | if(get_reg(regs[i+1].regmap,dops[i+1].rs1)<0) { |
8464 | hr=get_reg2(regs[i].regmap,regs[i+1].regmap,-1); | |
8465 | if(hr<0) hr=get_reg_temp(regs[i+1].regmap); | |
8466 | else { | |
8467 | regs[i+1].regmap[hr]=AGEN1+((i+1)&1); | |
8468 | regs[i+1].isconst&=~(1<<hr); | |
259dbd60 | 8469 | regs[i+1].dirty&=~(1<<hr); |
8470 | regs[i+2].wasdirty&=~(1<<hr); | |
94061aa5 | 8471 | } |
8472 | assert(hr>=0); | |
f628e7fd | 8473 | #if 0 // what is this for? double allocs $0 in ps1_rom.bin |
94061aa5 | 8474 | if(regs[i].regmap[hr]<0&®s[i+1].regmap_entry[hr]<0) |
8475 | { | |
8476 | regs[i].regmap[hr]=dops[i+1].rs1; | |
8477 | regmap_pre[i+1][hr]=dops[i+1].rs1; | |
8478 | regs[i+1].regmap_entry[hr]=dops[i+1].rs1; | |
8479 | regs[i].isconst&=~(1<<hr); | |
8480 | regs[i].isconst|=regs[i+1].isconst&(1<<hr); | |
8481 | constmap[i][hr]=constmap[i+1][hr]; | |
8482 | regs[i+1].wasdirty&=~(1<<hr); | |
8483 | regs[i].dirty&=~(1<<hr); | |
8484 | } | |
f628e7fd | 8485 | #endif |
94061aa5 | 8486 | } |
8487 | } | |
259dbd60 | 8488 | if (dops[i+1].itype == LOADLR || dops[i+1].opcode == 0x32) { // LWC2 |
94061aa5 | 8489 | if(get_reg(regs[i+1].regmap,dops[i+1].rs1)<0) { |
8490 | int nr; | |
8491 | hr=get_reg(regs[i+1].regmap,FTEMP); | |
8492 | assert(hr>=0); | |
8493 | if(regs[i].regmap[hr]<0&®s[i+1].regmap_entry[hr]<0) | |
8494 | { | |
8495 | regs[i].regmap[hr]=dops[i+1].rs1; | |
8496 | regmap_pre[i+1][hr]=dops[i+1].rs1; | |
8497 | regs[i+1].regmap_entry[hr]=dops[i+1].rs1; | |
8498 | regs[i].isconst&=~(1<<hr); | |
8499 | regs[i].isconst|=regs[i+1].isconst&(1<<hr); | |
8500 | constmap[i][hr]=constmap[i+1][hr]; | |
8501 | regs[i+1].wasdirty&=~(1<<hr); | |
8502 | regs[i].dirty&=~(1<<hr); | |
8503 | } | |
8504 | else if((nr=get_reg2(regs[i].regmap,regs[i+1].regmap,-1))>=0) | |
8505 | { | |
8506 | // move it to another register | |
8507 | regs[i+1].regmap[hr]=-1; | |
8508 | regmap_pre[i+2][hr]=-1; | |
8509 | regs[i+1].regmap[nr]=FTEMP; | |
8510 | regmap_pre[i+2][nr]=FTEMP; | |
8511 | regs[i].regmap[nr]=dops[i+1].rs1; | |
8512 | regmap_pre[i+1][nr]=dops[i+1].rs1; | |
8513 | regs[i+1].regmap_entry[nr]=dops[i+1].rs1; | |
8514 | regs[i].isconst&=~(1<<nr); | |
8515 | regs[i+1].isconst&=~(1<<nr); | |
8516 | regs[i].dirty&=~(1<<nr); | |
8517 | regs[i+1].wasdirty&=~(1<<nr); | |
8518 | regs[i+1].dirty&=~(1<<nr); | |
8519 | regs[i+2].wasdirty&=~(1<<nr); | |
8520 | } | |
8521 | } | |
8522 | } | |
f2e25348 | 8523 | if(dops[i+1].itype==LOAD||dops[i+1].itype==LOADLR||dops[i+1].itype==STORE||dops[i+1].itype==STORELR/*||dops[i+1].itype==C2LS*/) { |
94061aa5 | 8524 | hr = -1; |
8525 | if(dops[i+1].itype==LOAD) | |
f2e25348 | 8526 | hr=get_reg_w(regs[i+1].regmap, dops[i+1].rt1); |
259dbd60 | 8527 | if (dops[i+1].itype == LOADLR || dops[i+1].opcode == 0x32) // LWC2 |
94061aa5 | 8528 | hr=get_reg(regs[i+1].regmap,FTEMP); |
259dbd60 | 8529 | if (dops[i+1].is_store) { |
94061aa5 | 8530 | hr=get_reg(regs[i+1].regmap,AGEN1+((i+1)&1)); |
8531 | if(hr<0) hr=get_reg_temp(regs[i+1].regmap); | |
8532 | } | |
8533 | if(hr>=0&®s[i].regmap[hr]<0) { | |
8534 | int rs=get_reg(regs[i+1].regmap,dops[i+1].rs1); | |
8535 | if(rs>=0&&((regs[i+1].wasconst>>rs)&1)) { | |
8536 | regs[i].regmap[hr]=AGEN1+((i+1)&1); | |
8537 | regmap_pre[i+1][hr]=AGEN1+((i+1)&1); | |
8538 | regs[i+1].regmap_entry[hr]=AGEN1+((i+1)&1); | |
8539 | regs[i].isconst&=~(1<<hr); | |
8540 | regs[i+1].wasdirty&=~(1<<hr); | |
8541 | regs[i].dirty&=~(1<<hr); | |
8542 | } | |
b372a952 | 8543 | } |
8544 | } | |
57871462 | 8545 | } |
8546 | } | |
94061aa5 | 8547 | } |
8548 | } | |
8549 | } | |
8550 | ||
8551 | // Write back dirty registers as soon as we will no longer modify them, | |
8552 | // so that we don't end up with lots of writes at the branches. | |
8553 | static noinline void pass6_clean_registers(int istart, int iend, int wr) | |
8554 | { | |
e912c27d | 8555 | static u_int wont_dirty[MAXBLOCK]; |
8556 | static u_int will_dirty[MAXBLOCK]; | |
94061aa5 | 8557 | int i; |
8558 | int r; | |
8559 | u_int will_dirty_i,will_dirty_next,temp_will_dirty; | |
8560 | u_int wont_dirty_i,wont_dirty_next,temp_wont_dirty; | |
8561 | if(iend==slen-1) { | |
8562 | will_dirty_i=will_dirty_next=0; | |
8563 | wont_dirty_i=wont_dirty_next=0; | |
8564 | }else{ | |
8565 | will_dirty_i=will_dirty_next=will_dirty[iend+1]; | |
8566 | wont_dirty_i=wont_dirty_next=wont_dirty[iend+1]; | |
8567 | } | |
8568 | for (i=iend;i>=istart;i--) | |
8569 | { | |
8570 | signed char rregmap_i[RRMAP_SIZE]; | |
8571 | u_int hr_candirty = 0; | |
8572 | assert(HOST_REGS < 32); | |
8573 | make_rregs(regs[i].regmap, rregmap_i, &hr_candirty); | |
8574 | __builtin_prefetch(regs[i-1].regmap); | |
8575 | if(dops[i].is_jump) | |
8576 | { | |
8577 | signed char branch_rregmap_i[RRMAP_SIZE]; | |
8578 | u_int branch_hr_candirty = 0; | |
8579 | make_rregs(branch_regs[i].regmap, branch_rregmap_i, &branch_hr_candirty); | |
259dbd60 | 8580 | if(cinfo[i].ba<start || cinfo[i].ba>=(start+slen*4)) |
94061aa5 | 8581 | { |
8582 | // Branch out of this block, flush all regs | |
8583 | will_dirty_i = 0; | |
8584 | will_dirty_i |= 1u << (get_rreg(branch_rregmap_i, dops[i].rt1) & 31); | |
8585 | will_dirty_i |= 1u << (get_rreg(branch_rregmap_i, dops[i].rt2) & 31); | |
8586 | will_dirty_i |= 1u << (get_rreg(branch_rregmap_i, dops[i+1].rt1) & 31); | |
8587 | will_dirty_i |= 1u << (get_rreg(branch_rregmap_i, dops[i+1].rt2) & 31); | |
8588 | will_dirty_i |= 1u << (get_rreg(branch_rregmap_i, CCREG) & 31); | |
8589 | will_dirty_i &= branch_hr_candirty; | |
8590 | if (dops[i].is_ujump) | |
8591 | { | |
8592 | // Unconditional branch | |
8593 | wont_dirty_i = 0; | |
8594 | // Merge in delay slot (will dirty) | |
8595 | will_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i].rt1) & 31); | |
8596 | will_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i].rt2) & 31); | |
8597 | will_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i+1].rt1) & 31); | |
8598 | will_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i+1].rt2) & 31); | |
8599 | will_dirty_i |= 1u << (get_rreg(rregmap_i, CCREG) & 31); | |
8600 | will_dirty_i &= hr_candirty; | |
57871462 | 8601 | } |
94061aa5 | 8602 | else |
8603 | { | |
8604 | // Conditional branch | |
8605 | wont_dirty_i = wont_dirty_next; | |
8606 | // Merge in delay slot (will dirty) | |
8607 | // (the original code had no explanation why these 2 are commented out) | |
8608 | //will_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i].rt1) & 31); | |
8609 | //will_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i].rt2) & 31); | |
8610 | will_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i+1].rt1) & 31); | |
8611 | will_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i+1].rt2) & 31); | |
8612 | will_dirty_i |= 1u << (get_rreg(rregmap_i, CCREG) & 31); | |
8613 | will_dirty_i &= hr_candirty; | |
8614 | } | |
8615 | // Merge in delay slot (wont dirty) | |
8616 | wont_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i].rt1) & 31); | |
8617 | wont_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i].rt2) & 31); | |
8618 | wont_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i+1].rt1) & 31); | |
8619 | wont_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i+1].rt2) & 31); | |
8620 | wont_dirty_i |= 1u << (get_rreg(rregmap_i, CCREG) & 31); | |
8621 | wont_dirty_i |= 1u << (get_rreg(branch_rregmap_i, dops[i].rt1) & 31); | |
8622 | wont_dirty_i |= 1u << (get_rreg(branch_rregmap_i, dops[i].rt2) & 31); | |
8623 | wont_dirty_i |= 1u << (get_rreg(branch_rregmap_i, dops[i+1].rt1) & 31); | |
8624 | wont_dirty_i |= 1u << (get_rreg(branch_rregmap_i, dops[i+1].rt2) & 31); | |
8625 | wont_dirty_i |= 1u << (get_rreg(branch_rregmap_i, CCREG) & 31); | |
8626 | wont_dirty_i &= ~(1u << 31); | |
8627 | if(wr) { | |
8628 | #ifndef DESTRUCTIVE_WRITEBACK | |
8629 | branch_regs[i].dirty&=wont_dirty_i; | |
8630 | #endif | |
8631 | branch_regs[i].dirty|=will_dirty_i; | |
8632 | } | |
8633 | } | |
8634 | else | |
8635 | { | |
8636 | // Internal branch | |
259dbd60 | 8637 | if(cinfo[i].ba<=start+i*4) { |
94061aa5 | 8638 | // Backward branch |
8639 | if (dops[i].is_ujump) | |
8640 | { | |
8641 | // Unconditional branch | |
8642 | temp_will_dirty=0; | |
8643 | temp_wont_dirty=0; | |
8644 | // Merge in delay slot (will dirty) | |
8645 | temp_will_dirty |= 1u << (get_rreg(branch_rregmap_i, dops[i].rt1) & 31); | |
8646 | temp_will_dirty |= 1u << (get_rreg(branch_rregmap_i, dops[i].rt2) & 31); | |
8647 | temp_will_dirty |= 1u << (get_rreg(branch_rregmap_i, dops[i+1].rt1) & 31); | |
8648 | temp_will_dirty |= 1u << (get_rreg(branch_rregmap_i, dops[i+1].rt2) & 31); | |
8649 | temp_will_dirty |= 1u << (get_rreg(branch_rregmap_i, CCREG) & 31); | |
8650 | temp_will_dirty &= branch_hr_candirty; | |
8651 | temp_will_dirty |= 1u << (get_rreg(rregmap_i, dops[i].rt1) & 31); | |
8652 | temp_will_dirty |= 1u << (get_rreg(rregmap_i, dops[i].rt2) & 31); | |
8653 | temp_will_dirty |= 1u << (get_rreg(rregmap_i, dops[i+1].rt1) & 31); | |
8654 | temp_will_dirty |= 1u << (get_rreg(rregmap_i, dops[i+1].rt2) & 31); | |
8655 | temp_will_dirty |= 1u << (get_rreg(rregmap_i, CCREG) & 31); | |
8656 | temp_will_dirty &= hr_candirty; | |
8657 | } else { | |
8658 | // Conditional branch (not taken case) | |
8659 | temp_will_dirty=will_dirty_next; | |
8660 | temp_wont_dirty=wont_dirty_next; | |
8661 | // Merge in delay slot (will dirty) | |
8662 | temp_will_dirty |= 1u << (get_rreg(branch_rregmap_i, dops[i].rt1) & 31); | |
8663 | temp_will_dirty |= 1u << (get_rreg(branch_rregmap_i, dops[i].rt2) & 31); | |
8664 | temp_will_dirty |= 1u << (get_rreg(branch_rregmap_i, dops[i+1].rt1) & 31); | |
8665 | temp_will_dirty |= 1u << (get_rreg(branch_rregmap_i, dops[i+1].rt2) & 31); | |
8666 | temp_will_dirty |= 1u << (get_rreg(branch_rregmap_i, CCREG) & 31); | |
8667 | temp_will_dirty &= branch_hr_candirty; | |
8668 | //temp_will_dirty |= 1u << (get_rreg(rregmap_i, dops[i].rt1) & 31); | |
8669 | //temp_will_dirty |= 1u << (get_rreg(rregmap_i, dops[i].rt2) & 31); | |
8670 | temp_will_dirty |= 1u << (get_rreg(rregmap_i, dops[i+1].rt1) & 31); | |
8671 | temp_will_dirty |= 1u << (get_rreg(rregmap_i, dops[i+1].rt2) & 31); | |
8672 | temp_will_dirty |= 1u << (get_rreg(rregmap_i, CCREG) & 31); | |
8673 | temp_will_dirty &= hr_candirty; | |
8674 | } | |
8675 | // Merge in delay slot (wont dirty) | |
8676 | temp_wont_dirty |= 1u << (get_rreg(rregmap_i, dops[i].rt1) & 31); | |
8677 | temp_wont_dirty |= 1u << (get_rreg(rregmap_i, dops[i].rt2) & 31); | |
8678 | temp_wont_dirty |= 1u << (get_rreg(rregmap_i, dops[i+1].rt1) & 31); | |
8679 | temp_wont_dirty |= 1u << (get_rreg(rregmap_i, dops[i+1].rt2) & 31); | |
8680 | temp_wont_dirty |= 1u << (get_rreg(rregmap_i, CCREG) & 31); | |
8681 | temp_wont_dirty |= 1u << (get_rreg(branch_rregmap_i, dops[i].rt1) & 31); | |
8682 | temp_wont_dirty |= 1u << (get_rreg(branch_rregmap_i, dops[i].rt2) & 31); | |
8683 | temp_wont_dirty |= 1u << (get_rreg(branch_rregmap_i, dops[i+1].rt1) & 31); | |
8684 | temp_wont_dirty |= 1u << (get_rreg(branch_rregmap_i, dops[i+1].rt2) & 31); | |
8685 | temp_wont_dirty |= 1u << (get_rreg(branch_rregmap_i, CCREG) & 31); | |
8686 | temp_wont_dirty &= ~(1u << 31); | |
8687 | // Deal with changed mappings | |
8688 | if(i<iend) { | |
8689 | for(r=0;r<HOST_REGS;r++) { | |
8690 | if(r!=EXCLUDE_REG) { | |
8691 | if(regs[i].regmap[r]!=regmap_pre[i][r]) { | |
8692 | temp_will_dirty&=~(1<<r); | |
8693 | temp_wont_dirty&=~(1<<r); | |
8694 | if(regmap_pre[i][r]>0 && regmap_pre[i][r]<34) { | |
8695 | temp_will_dirty|=((unneeded_reg[i]>>regmap_pre[i][r])&1)<<r; | |
8696 | temp_wont_dirty|=((unneeded_reg[i]>>regmap_pre[i][r])&1)<<r; | |
8697 | } else { | |
8698 | temp_will_dirty|=1<<r; | |
8699 | temp_wont_dirty|=1<<r; | |
8700 | } | |
8701 | } | |
8702 | } | |
8703 | } | |
8704 | } | |
8705 | if(wr) { | |
8706 | will_dirty[i]=temp_will_dirty; | |
8707 | wont_dirty[i]=temp_wont_dirty; | |
259dbd60 | 8708 | pass6_clean_registers((cinfo[i].ba-start)>>2,i-1,0); |
94061aa5 | 8709 | }else{ |
8710 | // Limit recursion. It can take an excessive amount | |
8711 | // of time if there are a lot of nested loops. | |
259dbd60 | 8712 | will_dirty[(cinfo[i].ba-start)>>2]=0; |
8713 | wont_dirty[(cinfo[i].ba-start)>>2]=-1; | |
57871462 | 8714 | } |
57871462 | 8715 | } |
94061aa5 | 8716 | /*else*/ if(1) |
57871462 | 8717 | { |
94061aa5 | 8718 | if (dops[i].is_ujump) |
8719 | { | |
8720 | // Unconditional branch | |
8721 | will_dirty_i=0; | |
8722 | wont_dirty_i=0; | |
259dbd60 | 8723 | //if(cinfo[i].ba>start+i*4) { // Disable recursion (for debugging) |
94061aa5 | 8724 | for(r=0;r<HOST_REGS;r++) { |
8725 | if(r!=EXCLUDE_REG) { | |
259dbd60 | 8726 | if(branch_regs[i].regmap[r]==regs[(cinfo[i].ba-start)>>2].regmap_entry[r]) { |
8727 | will_dirty_i|=will_dirty[(cinfo[i].ba-start)>>2]&(1<<r); | |
8728 | wont_dirty_i|=wont_dirty[(cinfo[i].ba-start)>>2]&(1<<r); | |
94061aa5 | 8729 | } |
8730 | if(branch_regs[i].regmap[r]>=0) { | |
259dbd60 | 8731 | will_dirty_i|=((unneeded_reg[(cinfo[i].ba-start)>>2]>>branch_regs[i].regmap[r])&1)<<r; |
8732 | wont_dirty_i|=((unneeded_reg[(cinfo[i].ba-start)>>2]>>branch_regs[i].regmap[r])&1)<<r; | |
94061aa5 | 8733 | } |
8734 | } | |
57871462 | 8735 | } |
94061aa5 | 8736 | //} |
8737 | // Merge in delay slot | |
8738 | will_dirty_i |= 1u << (get_rreg(branch_rregmap_i, dops[i].rt1) & 31); | |
8739 | will_dirty_i |= 1u << (get_rreg(branch_rregmap_i, dops[i].rt2) & 31); | |
8740 | will_dirty_i |= 1u << (get_rreg(branch_rregmap_i, dops[i+1].rt1) & 31); | |
8741 | will_dirty_i |= 1u << (get_rreg(branch_rregmap_i, dops[i+1].rt2) & 31); | |
8742 | will_dirty_i |= 1u << (get_rreg(branch_rregmap_i, CCREG) & 31); | |
8743 | will_dirty_i &= branch_hr_candirty; | |
8744 | will_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i].rt1) & 31); | |
8745 | will_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i].rt2) & 31); | |
8746 | will_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i+1].rt1) & 31); | |
8747 | will_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i+1].rt2) & 31); | |
8748 | will_dirty_i |= 1u << (get_rreg(rregmap_i, CCREG) & 31); | |
8749 | will_dirty_i &= hr_candirty; | |
8750 | } else { | |
8751 | // Conditional branch | |
8752 | will_dirty_i=will_dirty_next; | |
8753 | wont_dirty_i=wont_dirty_next; | |
259dbd60 | 8754 | //if(cinfo[i].ba>start+i*4) // Disable recursion (for debugging) |
94061aa5 | 8755 | for(r=0;r<HOST_REGS;r++) { |
8756 | if(r!=EXCLUDE_REG) { | |
8757 | signed char target_reg=branch_regs[i].regmap[r]; | |
259dbd60 | 8758 | if(target_reg==regs[(cinfo[i].ba-start)>>2].regmap_entry[r]) { |
8759 | will_dirty_i&=will_dirty[(cinfo[i].ba-start)>>2]&(1<<r); | |
8760 | wont_dirty_i|=wont_dirty[(cinfo[i].ba-start)>>2]&(1<<r); | |
94061aa5 | 8761 | } |
8762 | else if(target_reg>=0) { | |
259dbd60 | 8763 | will_dirty_i&=((unneeded_reg[(cinfo[i].ba-start)>>2]>>target_reg)&1)<<r; |
8764 | wont_dirty_i|=((unneeded_reg[(cinfo[i].ba-start)>>2]>>target_reg)&1)<<r; | |
94061aa5 | 8765 | } |
8766 | } | |
57871462 | 8767 | } |
94061aa5 | 8768 | // Merge in delay slot |
8769 | will_dirty_i |= 1u << (get_rreg(branch_rregmap_i, dops[i].rt1) & 31); | |
8770 | will_dirty_i |= 1u << (get_rreg(branch_rregmap_i, dops[i].rt2) & 31); | |
8771 | will_dirty_i |= 1u << (get_rreg(branch_rregmap_i, dops[i+1].rt1) & 31); | |
8772 | will_dirty_i |= 1u << (get_rreg(branch_rregmap_i, dops[i+1].rt2) & 31); | |
8773 | will_dirty_i |= 1u << (get_rreg(branch_rregmap_i, CCREG) & 31); | |
8774 | will_dirty_i &= branch_hr_candirty; | |
8775 | //will_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i].rt1) & 31); | |
8776 | //will_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i].rt2) & 31); | |
8777 | will_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i+1].rt1) & 31); | |
8778 | will_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i+1].rt2) & 31); | |
8779 | will_dirty_i |= 1u << (get_rreg(rregmap_i, CCREG) & 31); | |
8780 | will_dirty_i &= hr_candirty; | |
57871462 | 8781 | } |
94061aa5 | 8782 | // Merge in delay slot (won't dirty) |
8783 | wont_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i].rt1) & 31); | |
8784 | wont_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i].rt2) & 31); | |
8785 | wont_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i+1].rt1) & 31); | |
8786 | wont_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i+1].rt2) & 31); | |
8787 | wont_dirty_i |= 1u << (get_rreg(rregmap_i, CCREG) & 31); | |
8788 | wont_dirty_i |= 1u << (get_rreg(branch_rregmap_i, dops[i].rt1) & 31); | |
8789 | wont_dirty_i |= 1u << (get_rreg(branch_rregmap_i, dops[i].rt2) & 31); | |
8790 | wont_dirty_i |= 1u << (get_rreg(branch_rregmap_i, dops[i+1].rt1) & 31); | |
8791 | wont_dirty_i |= 1u << (get_rreg(branch_rregmap_i, dops[i+1].rt2) & 31); | |
8792 | wont_dirty_i |= 1u << (get_rreg(branch_rregmap_i, CCREG) & 31); | |
8793 | wont_dirty_i &= ~(1u << 31); | |
8794 | if(wr) { | |
8795 | #ifndef DESTRUCTIVE_WRITEBACK | |
8796 | branch_regs[i].dirty&=wont_dirty_i; | |
8797 | #endif | |
8798 | branch_regs[i].dirty|=will_dirty_i; | |
57871462 | 8799 | } |
8800 | } | |
8801 | } | |
57871462 | 8802 | } |
259dbd60 | 8803 | else if (dops[i].is_exception) |
94061aa5 | 8804 | { |
259dbd60 | 8805 | // SYSCALL instruction, etc |
94061aa5 | 8806 | will_dirty_i=0; |
8807 | wont_dirty_i=0; | |
8808 | } | |
8809 | will_dirty_next=will_dirty_i; | |
8810 | wont_dirty_next=wont_dirty_i; | |
8811 | will_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i].rt1) & 31); | |
8812 | will_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i].rt2) & 31); | |
8813 | will_dirty_i |= 1u << (get_rreg(rregmap_i, CCREG) & 31); | |
8814 | will_dirty_i &= hr_candirty; | |
8815 | wont_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i].rt1) & 31); | |
8816 | wont_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i].rt2) & 31); | |
8817 | wont_dirty_i |= 1u << (get_rreg(rregmap_i, CCREG) & 31); | |
8818 | wont_dirty_i &= ~(1u << 31); | |
8819 | if (i > istart && !dops[i].is_jump) { | |
8820 | // Don't store a register immediately after writing it, | |
8821 | // may prevent dual-issue. | |
8822 | wont_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i-1].rt1) & 31); | |
8823 | wont_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i-1].rt2) & 31); | |
8824 | } | |
8825 | // Save it | |
8826 | will_dirty[i]=will_dirty_i; | |
8827 | wont_dirty[i]=wont_dirty_i; | |
8828 | // Mark registers that won't be dirtied as not dirty | |
8829 | if(wr) { | |
8830 | regs[i].dirty|=will_dirty_i; | |
8831 | #ifndef DESTRUCTIVE_WRITEBACK | |
8832 | regs[i].dirty&=wont_dirty_i; | |
8833 | if(dops[i].is_jump) | |
57871462 | 8834 | { |
94061aa5 | 8835 | if (i < iend-1 && !dops[i].is_ujump) { |
8836 | for(r=0;r<HOST_REGS;r++) { | |
8837 | if(r!=EXCLUDE_REG) { | |
8838 | if(regs[i].regmap[r]==regmap_pre[i+2][r]) { | |
8839 | regs[i+2].wasdirty&=wont_dirty_i|~(1<<r); | |
8840 | }else {/*printf("i: %x (%d) mismatch(+2): %d\n",start+i*4,i,r);assert(!((wont_dirty_i>>r)&1));*/} | |
57871462 | 8841 | } |
8842 | } | |
8843 | } | |
94061aa5 | 8844 | } |
8845 | else | |
8846 | { | |
8847 | if(i<iend) { | |
8848 | for(r=0;r<HOST_REGS;r++) { | |
8849 | if(r!=EXCLUDE_REG) { | |
8850 | if(regs[i].regmap[r]==regmap_pre[i+1][r]) { | |
8851 | regs[i+1].wasdirty&=wont_dirty_i|~(1<<r); | |
8852 | }else {/*printf("i: %x (%d) mismatch(+1): %d\n",start+i*4,i,r);assert(!((wont_dirty_i>>r)&1));*/} | |
57871462 | 8853 | } |
8854 | } | |
8855 | } | |
94061aa5 | 8856 | } |
8857 | #endif | |
8858 | } | |
8859 | // Deal with changed mappings | |
8860 | temp_will_dirty=will_dirty_i; | |
8861 | temp_wont_dirty=wont_dirty_i; | |
8862 | for(r=0;r<HOST_REGS;r++) { | |
8863 | if(r!=EXCLUDE_REG) { | |
8864 | int nr; | |
8865 | if(regs[i].regmap[r]==regmap_pre[i][r]) { | |
8866 | if(wr) { | |
8867 | #ifndef DESTRUCTIVE_WRITEBACK | |
8868 | regs[i].wasdirty&=wont_dirty_i|~(1<<r); | |
8869 | #endif | |
8870 | regs[i].wasdirty|=will_dirty_i&(1<<r); | |
57871462 | 8871 | } |
94061aa5 | 8872 | } |
8873 | else if(regmap_pre[i][r]>=0&&(nr=get_rreg(rregmap_i,regmap_pre[i][r]))>=0) { | |
8874 | // Register moved to a different register | |
8875 | will_dirty_i&=~(1<<r); | |
8876 | wont_dirty_i&=~(1<<r); | |
8877 | will_dirty_i|=((temp_will_dirty>>nr)&1)<<r; | |
8878 | wont_dirty_i|=((temp_wont_dirty>>nr)&1)<<r; | |
8879 | if(wr) { | |
8880 | #ifndef DESTRUCTIVE_WRITEBACK | |
8881 | regs[i].wasdirty&=wont_dirty_i|~(1<<r); | |
8882 | #endif | |
8883 | regs[i].wasdirty|=will_dirty_i&(1<<r); | |
8884 | } | |
8885 | } | |
8886 | else { | |
8887 | will_dirty_i&=~(1<<r); | |
8888 | wont_dirty_i&=~(1<<r); | |
8889 | if(regmap_pre[i][r]>0 && regmap_pre[i][r]<34) { | |
8890 | will_dirty_i|=((unneeded_reg[i]>>regmap_pre[i][r])&1)<<r; | |
8891 | wont_dirty_i|=((unneeded_reg[i]>>regmap_pre[i][r])&1)<<r; | |
8892 | } else { | |
8893 | wont_dirty_i|=1<<r; | |
8894 | /*printf("i: %x (%d) mismatch: %d\n",start+i*4,i,r);assert(!((will_dirty>>r)&1));*/ | |
57871462 | 8895 | } |
8896 | } | |
8897 | } | |
8898 | } | |
8899 | } | |
94061aa5 | 8900 | } |
8901 | ||
8902 | static noinline void pass10_expire_blocks(void) | |
8903 | { | |
432435ea | 8904 | u_int step = MAX_OUTPUT_BLOCK_SIZE / PAGE_COUNT / 2; |
8905 | // not sizeof(ndrc->translation_cache) due to vita hack | |
8906 | u_int step_mask = ((1u << TARGET_SIZE_2) - 1u) & ~(step - 1u); | |
8907 | u_int end = (out - ndrc->translation_cache + EXPIRITY_OFFSET) & step_mask; | |
8908 | u_int base_shift = __builtin_ctz(MAX_OUTPUT_BLOCK_SIZE); | |
8909 | int hit; | |
8910 | ||
8911 | for (; expirep != end; expirep = ((expirep + step) & step_mask)) | |
94061aa5 | 8912 | { |
432435ea | 8913 | u_int base_offs = expirep & ~(MAX_OUTPUT_BLOCK_SIZE - 1); |
8914 | u_int block_i = expirep / step & (PAGE_COUNT - 1); | |
8915 | u_int phase = (expirep >> (base_shift - 1)) & 1u; | |
8916 | if (!(expirep & (MAX_OUTPUT_BLOCK_SIZE / 2 - 1))) { | |
bdbf4466 | 8917 | inv_debug("EXP: base_offs %x/%lx phase %u\n", base_offs, |
8918 | (long)(out - ndrc->translation_cache), phase); | |
432435ea | 8919 | } |
8920 | ||
8921 | if (!phase) { | |
8922 | hit = blocks_remove_matching_addrs(&blocks[block_i], base_offs, base_shift); | |
8923 | if (hit) { | |
8924 | do_clear_cache(); | |
c980be0e | 8925 | mini_ht_clear(); |
432435ea | 8926 | } |
94061aa5 | 8927 | } |
432435ea | 8928 | else |
366d1d2b | 8929 | unlink_jumps_tc_range(jumps[block_i], base_offs, base_shift); |
94061aa5 | 8930 | } |
8931 | } | |
8932 | ||
048fcced | 8933 | static struct block_info *new_block_info(u_int start, u_int len, |
8934 | const void *source, const void *copy, u_char *beginning, u_short jump_in_count) | |
8935 | { | |
8936 | struct block_info **b_pptr; | |
8937 | struct block_info *block; | |
8938 | u_int page = get_page(start); | |
8939 | ||
8940 | block = malloc(sizeof(*block) + jump_in_count * sizeof(block->jump_in[0])); | |
8941 | assert(block); | |
8942 | assert(jump_in_count > 0); | |
8943 | block->source = source; | |
8944 | block->copy = copy; | |
8945 | block->start = start; | |
8946 | block->len = len; | |
8947 | block->reg_sv_flags = 0; | |
8948 | block->tc_offs = beginning - ndrc->translation_cache; | |
8949 | //block->tc_len = out - beginning; | |
8950 | block->is_dirty = 0; | |
11eca54f | 8951 | block->inv_near_misses = 0; |
048fcced | 8952 | block->jump_in_cnt = jump_in_count; |
8953 | ||
432435ea | 8954 | // insert sorted by start mirror-unmasked vaddr |
048fcced | 8955 | for (b_pptr = &blocks[page]; ; b_pptr = &((*b_pptr)->next)) { |
8956 | if (*b_pptr == NULL || (*b_pptr)->start >= start) { | |
8957 | block->next = *b_pptr; | |
8958 | *b_pptr = block; | |
8959 | break; | |
8960 | } | |
8961 | } | |
8962 | stat_inc(stat_blocks); | |
8963 | return block; | |
8964 | } | |
8965 | ||
8966 | static int new_recompile_block(u_int addr) | |
94061aa5 | 8967 | { |
8968 | u_int pagelimit = 0; | |
8969 | u_int state_rflags = 0; | |
8970 | int i; | |
8971 | ||
8972 | assem_debug("NOTCOMPILED: addr = %x -> %p\n", addr, out); | |
8973 | ||
f2e25348 | 8974 | if (addr & 3) { |
8975 | if (addr != hack_addr) { | |
8976 | SysPrintf("game crash @%08x, ra=%08x\n", addr, psxRegs.GPR.n.ra); | |
8977 | hack_addr = addr; | |
8978 | } | |
8979 | return -1; | |
8980 | } | |
8981 | ||
94061aa5 | 8982 | // this is just for speculation |
8983 | for (i = 1; i < 32; i++) { | |
8984 | if ((psxRegs.GPR.r[i] & 0xffff0000) == 0x1f800000) | |
8985 | state_rflags |= 1 << i; | |
8986 | } | |
8987 | ||
f2e25348 | 8988 | start = addr; |
94061aa5 | 8989 | new_dynarec_did_compile=1; |
8990 | if (Config.HLE && start == 0x80001000) // hlecall | |
8991 | { | |
048fcced | 8992 | void *beginning = start_block(); |
94061aa5 | 8993 | |
94061aa5 | 8994 | emit_movimm(start,0); |
8995 | emit_writeword(0,&pcaddr); | |
8996 | emit_far_jump(new_dyna_leave); | |
8997 | literal_pool(0); | |
8998 | end_block(beginning); | |
048fcced | 8999 | struct block_info *block = new_block_info(start, 4, NULL, NULL, beginning, 1); |
9000 | block->jump_in[0].vaddr = start; | |
9001 | block->jump_in[0].addr = beginning; | |
94061aa5 | 9002 | return 0; |
9003 | } | |
9004 | else if (f1_hack && hack_addr == 0) { | |
9005 | void *beginning = start_block(); | |
94061aa5 | 9006 | emit_movimm(start, 0); |
9007 | emit_writeword(0, &hack_addr); | |
9008 | emit_readword(&psxRegs.GPR.n.sp, 0); | |
9009 | emit_readptr(&mem_rtab, 1); | |
9010 | emit_shrimm(0, 12, 2); | |
9011 | emit_readptr_dualindexedx_ptrlen(1, 2, 1); | |
9012 | emit_addimm(0, 0x18, 0); | |
9013 | emit_adds_ptr(1, 1, 1); | |
9014 | emit_ldr_dualindexed(1, 0, 0); | |
9015 | emit_writeword(0, &psxRegs.GPR.r[26]); // lw k0, 0x18(sp) | |
048fcced | 9016 | emit_far_call(ndrc_get_addr_ht); |
94061aa5 | 9017 | emit_jmpreg(0); // jr k0 |
9018 | literal_pool(0); | |
9019 | end_block(beginning); | |
9020 | ||
048fcced | 9021 | struct block_info *block = new_block_info(start, 4, NULL, NULL, beginning, 1); |
9022 | block->jump_in[0].vaddr = start; | |
9023 | block->jump_in[0].addr = beginning; | |
94061aa5 | 9024 | SysPrintf("F1 hack to %08x\n", start); |
9025 | return 0; | |
9026 | } | |
9027 | ||
b6cd25ed | 9028 | cycle_multiplier_active = get_cycle_multiplier(); |
94061aa5 | 9029 | |
9030 | source = get_source_start(start, &pagelimit); | |
9031 | if (source == NULL) { | |
9032 | if (addr != hack_addr) { | |
b6cd25ed | 9033 | SysPrintf("Compile at bogus memory address: %08x, ra=%x\n", |
9034 | addr, psxRegs.GPR.n.ra); | |
94061aa5 | 9035 | hack_addr = addr; |
9036 | } | |
9037 | //abort(); | |
9038 | return -1; | |
9039 | } | |
9040 | ||
9041 | /* Pass 1: disassemble */ | |
9042 | /* Pass 2: register dependencies, branch targets */ | |
9043 | /* Pass 3: register allocation */ | |
9044 | /* Pass 4: branch dependencies */ | |
9045 | /* Pass 5: pre-alloc */ | |
9046 | /* Pass 6: optimize clean/dirty state */ | |
9047 | /* Pass 7: flag 32-bit registers */ | |
9048 | /* Pass 8: assembly */ | |
9049 | /* Pass 9: linker */ | |
9050 | /* Pass 10: garbage collection / free memory */ | |
9051 | ||
9052 | /* Pass 1 disassembly */ | |
9053 | ||
9054 | pass1_disassemble(pagelimit); | |
9055 | ||
9056 | int clear_hack_addr = apply_hacks(); | |
9057 | ||
9058 | /* Pass 2 - Register dependencies and branch targets */ | |
9059 | ||
9060 | pass2_unneeded_regs(0,slen-1,0); | |
9061 | ||
59dd5faf | 9062 | pass2a_unneeded_other(); |
9063 | ||
94061aa5 | 9064 | /* Pass 3 - Register allocation */ |
9065 | ||
9066 | pass3_register_alloc(addr); | |
9067 | ||
9068 | /* Pass 4 - Cull unused host registers */ | |
9069 | ||
9070 | pass4_cull_unused_regs(); | |
9071 | ||
9072 | /* Pass 5 - Pre-allocate registers */ | |
9073 | ||
9074 | pass5a_preallocate1(); | |
9075 | pass5b_preallocate2(); | |
9f51b4b9 | 9076 | |
57871462 | 9077 | /* Pass 6 - Optimize clean/dirty state */ |
94061aa5 | 9078 | pass6_clean_registers(0, slen-1, 1); |
9f51b4b9 | 9079 | |
e6e590d3 | 9080 | /* Pass 7 */ |
04fd948a | 9081 | for (i=slen-1;i>=0;i--) |
9082 | { | |
630b122b | 9083 | if(dops[i].itype==CJUMP||dops[i].itype==SJUMP) |
04fd948a | 9084 | { |
9085 | // Conditional branch | |
9086 | if((source[i]>>16)!=0x1000&&i<slen-2) { | |
9087 | // Mark this address as a branch target since it may be called | |
9088 | // upon return from interrupt | |
630b122b | 9089 | dops[i+2].bt=1; |
04fd948a | 9090 | } |
9091 | } | |
9092 | } | |
57871462 | 9093 | |
57871462 | 9094 | /* Pass 8 - Assembly */ |
9095 | linkcount=0;stubcount=0; | |
94061aa5 | 9096 | is_delayslot=0; |
57871462 | 9097 | u_int dirty_pre=0; |
d148d265 | 9098 | void *beginning=start_block(); |
630b122b | 9099 | void *instr_addr0_override = NULL; |
f9e37973 | 9100 | int ds = 0; |
9ad4d757 | 9101 | |
85d4a839 | 9102 | if ((Config.HLE && start == 0x80000080) || start == 0x80030000) { |
630b122b | 9103 | instr_addr0_override = out; |
85d4a839 | 9104 | emit_movimm(start, 0); |
9105 | if (start == 0x80030000) { | |
9106 | // for BiosBootBypass() to work | |
9107 | // io address var abused as a "already been here" flag | |
9108 | emit_readword(&address, 1); | |
9109 | emit_writeword(0, &pcaddr); | |
9110 | emit_writeword(0, &address); | |
9111 | emit_cmp(0, 1); | |
9112 | } | |
9113 | else { | |
9114 | emit_readword(&psxRegs.cpuInRecursion, 1); | |
9115 | emit_writeword(0, &pcaddr); | |
9116 | emit_test(1, 1); | |
9117 | } | |
630b122b | 9118 | #ifdef __aarch64__ |
9119 | emit_jeq(out + 4*2); | |
9120 | emit_far_jump(new_dyna_leave); | |
9121 | #else | |
9122 | emit_jne(new_dyna_leave); | |
9123 | #endif | |
9ad4d757 | 9124 | } |
57871462 | 9125 | for(i=0;i<slen;i++) |
9126 | { | |
91af94f0 | 9127 | __builtin_prefetch(regs[i+1].regmap); |
648d9448 | 9128 | check_regmap(regmap_pre[i]); |
9129 | check_regmap(regs[i].regmap_entry); | |
9130 | check_regmap(regs[i].regmap); | |
57871462 | 9131 | //if(ds) printf("ds: "); |
4600ba03 | 9132 | disassemble_inst(i); |
57871462 | 9133 | if(ds) { |
9134 | ds=0; // Skip delay slot | |
630b122b | 9135 | if(dops[i].bt) assem_debug("OOPS - branch into delay slot\n"); |
9136 | instr_addr[i] = NULL; | |
57871462 | 9137 | } else { |
ffb0b9e0 | 9138 | speculate_register_values(i); |
57871462 | 9139 | #ifndef DESTRUCTIVE_WRITEBACK |
630b122b | 9140 | if (i < 2 || !dops[i-2].is_ujump) |
57871462 | 9141 | { |
630b122b | 9142 | wb_valid(regmap_pre[i],regs[i].regmap_entry,dirty_pre,regs[i].wasdirty,unneeded_reg[i]); |
57871462 | 9143 | } |
630b122b | 9144 | if((dops[i].itype==CJUMP||dops[i].itype==SJUMP)) { |
f776eb14 | 9145 | dirty_pre=branch_regs[i].dirty; |
9146 | }else{ | |
f776eb14 | 9147 | dirty_pre=regs[i].dirty; |
9148 | } | |
57871462 | 9149 | #endif |
9150 | // write back | |
630b122b | 9151 | if (i < 2 || !dops[i-2].is_ujump) |
57871462 | 9152 | { |
630b122b | 9153 | wb_invalidate(regmap_pre[i],regs[i].regmap_entry,regs[i].wasdirty,unneeded_reg[i]); |
57871462 | 9154 | loop_preload(regmap_pre[i],regs[i].regmap_entry); |
9155 | } | |
9156 | // branch target entry point | |
630b122b | 9157 | instr_addr[i] = out; |
57871462 | 9158 | assem_debug("<->\n"); |
259dbd60 | 9159 | drc_dbg_emit_do_cmp(i, cinfo[i].ccadj); |
7c8454e3 | 9160 | if (clear_hack_addr) { |
9161 | emit_movimm(0, 0); | |
9162 | emit_writeword(0, &hack_addr); | |
9163 | clear_hack_addr = 0; | |
9164 | } | |
630b122b | 9165 | |
57871462 | 9166 | // load regs |
9167 | if(regs[i].regmap_entry[HOST_CCREG]==CCREG&®s[i].regmap[HOST_CCREG]!=CCREG) | |
630b122b | 9168 | wb_register(CCREG,regs[i].regmap_entry,regs[i].wasdirty); |
9169 | load_regs(regs[i].regmap_entry,regs[i].regmap,dops[i].rs1,dops[i].rs2); | |
57871462 | 9170 | address_generation(i,®s[i],regs[i].regmap_entry); |
630b122b | 9171 | load_consts(regmap_pre[i],regs[i].regmap,i); |
9172 | if(dops[i].is_jump) | |
57871462 | 9173 | { |
9174 | // Load the delay slot registers if necessary | |
630b122b | 9175 | if(dops[i+1].rs1!=dops[i].rs1&&dops[i+1].rs1!=dops[i].rs2&&(dops[i+1].rs1!=dops[i].rt1||dops[i].rt1==0)) |
9176 | load_regs(regs[i].regmap_entry,regs[i].regmap,dops[i+1].rs1,dops[i+1].rs1); | |
9177 | if(dops[i+1].rs2!=dops[i+1].rs1&&dops[i+1].rs2!=dops[i].rs1&&dops[i+1].rs2!=dops[i].rs2&&(dops[i+1].rs2!=dops[i].rt1||dops[i].rt1==0)) | |
9178 | load_regs(regs[i].regmap_entry,regs[i].regmap,dops[i+1].rs2,dops[i+1].rs2); | |
9179 | if (ram_offset && (dops[i+1].is_load || dops[i+1].is_store)) | |
e912c27d | 9180 | load_reg(regs[i].regmap_entry,regs[i].regmap,ROREG); |
630b122b | 9181 | if (dops[i+1].is_store) |
e912c27d | 9182 | load_reg(regs[i].regmap_entry,regs[i].regmap,INVCP); |
57871462 | 9183 | } |
9184 | else if(i+1<slen) | |
9185 | { | |
9186 | // Preload registers for following instruction | |
630b122b | 9187 | if(dops[i+1].rs1!=dops[i].rs1&&dops[i+1].rs1!=dops[i].rs2) |
9188 | if(dops[i+1].rs1!=dops[i].rt1&&dops[i+1].rs1!=dops[i].rt2) | |
9189 | load_regs(regs[i].regmap_entry,regs[i].regmap,dops[i+1].rs1,dops[i+1].rs1); | |
9190 | if(dops[i+1].rs2!=dops[i+1].rs1&&dops[i+1].rs2!=dops[i].rs1&&dops[i+1].rs2!=dops[i].rs2) | |
9191 | if(dops[i+1].rs2!=dops[i].rt1&&dops[i+1].rs2!=dops[i].rt2) | |
9192 | load_regs(regs[i].regmap_entry,regs[i].regmap,dops[i+1].rs2,dops[i+1].rs2); | |
57871462 | 9193 | } |
9194 | // TODO: if(is_ooo(i)) address_generation(i+1); | |
630b122b | 9195 | if (!dops[i].is_jump || dops[i].itype == CJUMP) |
e912c27d | 9196 | load_reg(regs[i].regmap_entry,regs[i].regmap,CCREG); |
630b122b | 9197 | if (ram_offset && (dops[i].is_load || dops[i].is_store)) |
e912c27d | 9198 | load_reg(regs[i].regmap_entry,regs[i].regmap,ROREG); |
630b122b | 9199 | if (dops[i].is_store) |
e912c27d | 9200 | load_reg(regs[i].regmap_entry,regs[i].regmap,INVCP); |
630b122b | 9201 | |
259dbd60 | 9202 | ds = assemble(i, ®s[i], cinfo[i].ccadj); |
630b122b | 9203 | |
40190245 | 9204 | drc_dbg_emit_wb_dirtys(i, ®s[i]); |
630b122b | 9205 | if (dops[i].is_ujump) |
57871462 | 9206 | literal_pool(1024); |
9207 | else | |
9208 | literal_pool_jumpover(256); | |
9209 | } | |
9210 | } | |
630b122b | 9211 | |
9212 | assert(slen > 0); | |
9213 | if (slen > 0 && dops[slen-1].itype == INTCALL) { | |
9214 | // no ending needed for this block since INTCALL never returns | |
9215 | } | |
57871462 | 9216 | // If the block did not end with an unconditional branch, |
9217 | // add a jump to the next instruction. | |
630b122b | 9218 | else if (i > 1) { |
f9e37973 | 9219 | if (!dops[i-2].is_ujump) { |
630b122b | 9220 | assert(!dops[i-1].is_jump); |
57871462 | 9221 | assert(i==slen); |
630b122b | 9222 | if(dops[i-2].itype!=CJUMP&&dops[i-2].itype!=SJUMP) { |
9223 | store_regs_bt(regs[i-1].regmap,regs[i-1].dirty,start+i*4); | |
57871462 | 9224 | if(regs[i-1].regmap[HOST_CCREG]!=CCREG) |
9225 | emit_loadreg(CCREG,HOST_CCREG); | |
259dbd60 | 9226 | emit_addimm(HOST_CCREG, cinfo[i-1].ccadj + CLOCK_ADJUST(1), HOST_CCREG); |
57871462 | 9227 | } |
9228 | else | |
9229 | { | |
630b122b | 9230 | store_regs_bt(branch_regs[i-2].regmap,branch_regs[i-2].dirty,start+i*4); |
9231 | assert(branch_regs[i-2].regmap[HOST_CCREG]==CCREG); | |
57871462 | 9232 | } |
630b122b | 9233 | add_to_linker(out,start+i*4,0); |
57871462 | 9234 | emit_jmp(0); |
9235 | } | |
9236 | } | |
9237 | else | |
9238 | { | |
9239 | assert(i>0); | |
630b122b | 9240 | assert(!dops[i-1].is_jump); |
9241 | store_regs_bt(regs[i-1].regmap,regs[i-1].dirty,start+i*4); | |
57871462 | 9242 | if(regs[i-1].regmap[HOST_CCREG]!=CCREG) |
9243 | emit_loadreg(CCREG,HOST_CCREG); | |
259dbd60 | 9244 | emit_addimm(HOST_CCREG, cinfo[i-1].ccadj + CLOCK_ADJUST(1), HOST_CCREG); |
630b122b | 9245 | add_to_linker(out,start+i*4,0); |
57871462 | 9246 | emit_jmp(0); |
9247 | } | |
9248 | ||
57871462 | 9249 | // Stubs |
f2e25348 | 9250 | for(i = 0; i < stubcount; i++) |
57871462 | 9251 | { |
630b122b | 9252 | switch(stubs[i].type) |
57871462 | 9253 | { |
9254 | case LOADB_STUB: | |
9255 | case LOADH_STUB: | |
9256 | case LOADW_STUB: | |
57871462 | 9257 | case LOADBU_STUB: |
9258 | case LOADHU_STUB: | |
9259 | do_readstub(i);break; | |
9260 | case STOREB_STUB: | |
9261 | case STOREH_STUB: | |
9262 | case STOREW_STUB: | |
57871462 | 9263 | do_writestub(i);break; |
9264 | case CC_STUB: | |
9265 | do_ccstub(i);break; | |
9266 | case INVCODE_STUB: | |
9267 | do_invstub(i);break; | |
57871462 | 9268 | case STORELR_STUB: |
9269 | do_unalignedwritestub(i);break; | |
f2e25348 | 9270 | case OVERFLOW_STUB: |
9271 | do_overflowstub(i); break; | |
259dbd60 | 9272 | case ALIGNMENT_STUB: |
9273 | do_alignmentstub(i); break; | |
f2e25348 | 9274 | default: |
9275 | assert(0); | |
57871462 | 9276 | } |
9277 | } | |
9278 | ||
9ad4d757 | 9279 | if (instr_addr0_override) |
9280 | instr_addr[0] = instr_addr0_override; | |
9281 | ||
432435ea | 9282 | #if 0 |
9283 | /* check for improper expiration */ | |
9284 | for (i = 0; i < ARRAY_SIZE(jumps); i++) { | |
9285 | int j; | |
9286 | if (!jumps[i]) | |
9287 | continue; | |
9288 | for (j = 0; j < jumps[i]->count; j++) | |
9289 | assert(jumps[i]->e[j].stub < beginning || (u_char *)jumps[i]->e[j].stub > out); | |
9290 | } | |
9291 | #endif | |
9292 | ||
57871462 | 9293 | /* Pass 9 - Linker */ |
9294 | for(i=0;i<linkcount;i++) | |
9295 | { | |
630b122b | 9296 | assem_debug("%p -> %8x\n",link_addr[i].addr,link_addr[i].target); |
57871462 | 9297 | literal_pool(64); |
048fcced | 9298 | if (!link_addr[i].internal) |
57871462 | 9299 | { |
630b122b | 9300 | void *stub = out; |
9301 | void *addr = check_addr(link_addr[i].target); | |
9302 | emit_extjump(link_addr[i].addr, link_addr[i].target); | |
9303 | if (addr) { | |
9304 | set_jump_target(link_addr[i].addr, addr); | |
048fcced | 9305 | ndrc_add_jump_out(link_addr[i].target,stub); |
57871462 | 9306 | } |
630b122b | 9307 | else |
9308 | set_jump_target(link_addr[i].addr, stub); | |
57871462 | 9309 | } |
9310 | else | |
9311 | { | |
9312 | // Internal branch | |
630b122b | 9313 | int target=(link_addr[i].target-start)>>2; |
57871462 | 9314 | assert(target>=0&&target<slen); |
9315 | assert(instr_addr[target]); | |
9316 | //#ifdef CORTEX_A8_BRANCH_PREDICTION_HACK | |
630b122b | 9317 | //set_jump_target_fillslot(link_addr[i].addr,instr_addr[target],link_addr[i].ext>>1); |
57871462 | 9318 | //#else |
630b122b | 9319 | set_jump_target(link_addr[i].addr, instr_addr[target]); |
57871462 | 9320 | //#endif |
9321 | } | |
9322 | } | |
630b122b | 9323 | |
9324 | u_int source_len = slen*4; | |
9325 | if (dops[slen-1].itype == INTCALL && source_len > 4) | |
9326 | // no need to treat the last instruction as compiled | |
9327 | // as interpreter fully handles it | |
9328 | source_len -= 4; | |
9329 | ||
9330 | if ((u_char *)copy + source_len > (u_char *)shadow + sizeof(shadow)) | |
9331 | copy = shadow; | |
9332 | ||
57871462 | 9333 | // External Branch Targets (jump_in) |
048fcced | 9334 | int jump_in_count = 1; |
9335 | assert(instr_addr[0]); | |
9336 | for (i = 1; i < slen; i++) | |
9337 | { | |
9338 | if (dops[i].bt && instr_addr[i]) | |
9339 | jump_in_count++; | |
9340 | } | |
9341 | ||
9342 | struct block_info *block = | |
9343 | new_block_info(start, slen * 4, source, copy, beginning, jump_in_count); | |
9344 | block->reg_sv_flags = state_rflags; | |
9345 | ||
9346 | int jump_in_i = 0; | |
9347 | for (i = 0; i < slen; i++) | |
57871462 | 9348 | { |
048fcced | 9349 | if ((i == 0 || dops[i].bt) && instr_addr[i]) |
57871462 | 9350 | { |
048fcced | 9351 | assem_debug("%p (%d) <- %8x\n", instr_addr[i], i, start + i*4); |
9352 | u_int vaddr = start + i*4; | |
9353 | ||
9354 | literal_pool(256); | |
9355 | void *entry = out; | |
9356 | load_regs_entry(i); | |
9357 | if (entry == out) | |
9358 | entry = instr_addr[i]; | |
9359 | else | |
9360 | emit_jmp(instr_addr[i]); | |
9361 | ||
9362 | block->jump_in[jump_in_i].vaddr = vaddr; | |
9363 | block->jump_in[jump_in_i].addr = entry; | |
9364 | jump_in_i++; | |
57871462 | 9365 | } |
9366 | } | |
048fcced | 9367 | assert(jump_in_i == jump_in_count); |
9368 | hash_table_add(block->jump_in[0].vaddr, block->jump_in[0].addr); | |
57871462 | 9369 | // Write out the literal pool if necessary |
9370 | literal_pool(0); | |
9371 | #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK | |
9372 | // Align code | |
9373 | if(((u_int)out)&7) emit_addnop(13); | |
9374 | #endif | |
630b122b | 9375 | assert(out - (u_char *)beginning < MAX_OUTPUT_BLOCK_SIZE); |
9376 | //printf("shadow buffer: %p-%p\n",copy,(u_char *)copy+slen*4); | |
9377 | memcpy(copy, source, source_len); | |
9378 | copy += source_len; | |
9f51b4b9 | 9379 | |
d148d265 | 9380 | end_block(beginning); |
9f51b4b9 | 9381 | |
57871462 | 9382 | // If we're within 256K of the end of the buffer, |
9383 | // start over from the beginning. (Is 256K enough?) | |
630b122b | 9384 | if (out > ndrc->translation_cache + sizeof(ndrc->translation_cache) - MAX_OUTPUT_BLOCK_SIZE) |
9385 | out = ndrc->translation_cache; | |
9f51b4b9 | 9386 | |
57871462 | 9387 | // Trap writes to any of the pages we compiled |
048fcced | 9388 | mark_invalid_code(start, slen*4, 0); |
9f51b4b9 | 9389 | |
57871462 | 9390 | /* Pass 10 - Free memory by expiring oldest blocks */ |
9f51b4b9 | 9391 | |
94061aa5 | 9392 | pass10_expire_blocks(); |
9393 | ||
630b122b | 9394 | #ifdef ASSEM_PRINT |
9395 | fflush(stdout); | |
9396 | #endif | |
55cadc36 | 9397 | stat_inc(stat_bc_direct); |
57871462 | 9398 | return 0; |
9399 | } | |
b9b61529 | 9400 | |
9401 | // vim:shiftwidth=2:expandtab |