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[pcsx_rearmed.git] / libpcsxcore / new_dynarec / new_dynarec.c
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57871462 1/* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
2 * Mupen64plus - new_dynarec.c *
20d507ba 3 * Copyright (C) 2009-2011 Ari64 *
57871462 4 * *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
9 * *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
14 * *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. *
19 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */
20
21#include <stdlib.h>
22#include <stdint.h> //include for uint64_t
23#include <assert.h>
d848b60a 24#include <errno.h>
4600ba03 25#include <sys/mman.h>
57871462 26
3d624f89 27#include "emu_if.h" //emulator interface
57871462 28
4600ba03 29//#define DISASM
30//#define assem_debug printf
31//#define inv_debug printf
32#define assem_debug(...)
33#define inv_debug(...)
57871462 34
35#ifdef __i386__
36#include "assem_x86.h"
37#endif
38#ifdef __x86_64__
39#include "assem_x64.h"
40#endif
41#ifdef __arm__
42#include "assem_arm.h"
43#endif
44
f23d3386 45#ifdef __BLACKBERRY_QNX__
a4874585
C		 46#undef __clear_cache
47#define __clear_cache(start,end) msync(start, (size_t)((void*)end - (void*)start), MS_SYNC | MS_CACHE_ONLY | MS_INVALIDATE_ICACHE);
c7b746f0 48#elif defined(__MACH__)
49#include <libkern/OSCacheControl.h>
50#define __clear_cache mach_clear_cache
51static void __clear_cache(void *start, void *end) {
52 size_t len = (char *)end - (char *)start;
53 sys_dcache_flush(start, len);
54 sys_icache_invalidate(start, len);
55}
f23d3386 56#endif
a4874585 57
57871462 58#define MAXBLOCK 4096
59#define MAX_OUTPUT_BLOCK_SIZE 262144
2573466a 60
57871462 61struct regstat
62{
63 signed char regmap_entry[HOST_REGS];
64 signed char regmap[HOST_REGS];
65 uint64_t was32;
66 uint64_t is32;
67 uint64_t wasdirty;
68 uint64_t dirty;
69 uint64_t u;
70 uint64_t uu;
71 u_int wasconst;
72 u_int isconst;
8575a877 73 u_int loadedconst; // host regs that have constants loaded
74 u_int waswritten; // MIPS regs that were used as store base before
57871462 75};
76
de5a60c3 77// note: asm depends on this layout
57871462 78struct ll_entry
79{
80 u_int vaddr;
de5a60c3 81 u_int reg_sv_flags;
57871462 82 void *addr;
83 struct ll_entry *next;
84};
85
86 u_int start;
87 u_int *source;
57871462 88 char insn[MAXBLOCK][10];
89 u_char itype[MAXBLOCK];
90 u_char opcode[MAXBLOCK];
91 u_char opcode2[MAXBLOCK];
92 u_char bt[MAXBLOCK];
93 u_char rs1[MAXBLOCK];
94 u_char rs2[MAXBLOCK];
95 u_char rt1[MAXBLOCK];
96 u_char rt2[MAXBLOCK];
97 u_char us1[MAXBLOCK];
98 u_char us2[MAXBLOCK];
99 u_char dep1[MAXBLOCK];
100 u_char dep2[MAXBLOCK];
101 u_char lt1[MAXBLOCK];
bedfea38 102 static uint64_t gte_rs[MAXBLOCK]; // gte: 32 data and 32 ctl regs
103 static uint64_t gte_rt[MAXBLOCK];
104 static uint64_t gte_unneeded[MAXBLOCK];
ffb0b9e0 105 static u_int smrv[32]; // speculated MIPS register values
106 static u_int smrv_strong; // mask or regs that are likely to have correct values
107 static u_int smrv_weak; // same, but somewhat less likely
108 static u_int smrv_strong_next; // same, but after current insn executes
109 static u_int smrv_weak_next;
57871462 110 int imm[MAXBLOCK];
111 u_int ba[MAXBLOCK];
112 char likely[MAXBLOCK];
113 char is_ds[MAXBLOCK];
e1190b87 114 char ooo[MAXBLOCK];
57871462 115 uint64_t unneeded_reg[MAXBLOCK];
116 uint64_t unneeded_reg_upper[MAXBLOCK];
117 uint64_t branch_unneeded_reg[MAXBLOCK];
118 uint64_t branch_unneeded_reg_upper[MAXBLOCK];
57871462 119 uint64_t pr32[MAXBLOCK];
120 signed char regmap_pre[MAXBLOCK][HOST_REGS];
956f3129 121 static uint64_t current_constmap[HOST_REGS];
122 static uint64_t constmap[MAXBLOCK][HOST_REGS];
123 static struct regstat regs[MAXBLOCK];
124 static struct regstat branch_regs[MAXBLOCK];
e1190b87 125 signed char minimum_free_regs[MAXBLOCK];
57871462 126 u_int needed_reg[MAXBLOCK];
57871462 127 u_int wont_dirty[MAXBLOCK];
128 u_int will_dirty[MAXBLOCK];
129 int ccadj[MAXBLOCK];
130 int slen;
131 u_int instr_addr[MAXBLOCK];
132 u_int link_addr[MAXBLOCK][3];
133 int linkcount;
134 u_int stubs[MAXBLOCK*3][8];
135 int stubcount;
136 u_int literals[1024][2];
137 int literalcount;
138 int is_delayslot;
139 int cop1_usable;
140 u_char *out;
de5a60c3 141 struct ll_entry *jump_in[4096] __attribute__((aligned(16)));
57871462 142 struct ll_entry *jump_out[4096];
143 struct ll_entry *jump_dirty[4096];
144 u_int hash_table[65536][4] __attribute__((aligned(16)));
145 char shadow[1048576] __attribute__((aligned(16)));
146 void *copy;
147 int expirep;
2f546f9a 148 int new_dynarec_did_compile;
0ff8c62c 149 int new_dynarec_hacks;
57871462 150 u_int stop_after_jal;
a327ad27 151#ifndef RAM_FIXED
152 static u_int ram_offset;
153#else
154 static const u_int ram_offset=0;
155#endif
57871462 156 extern u_char restore_candidate[512];
157 extern int cycle_count;
158
159 /* registers that may be allocated */
160 /* 1-31 gpr */
161#define HIREG 32 // hi
162#define LOREG 33 // lo
163#define FSREG 34 // FPU status (FCSR)
164#define CSREG 35 // Coprocessor status
165#define CCREG 36 // Cycle count
166#define INVCP 37 // Pointer to invalid_code
1edfcc68 167//#define MMREG 38 // Pointer to memory_map
619e5ded 168#define ROREG 39 // ram offset (if rdram!=0x80000000)
169#define TEMPREG 40
170#define FTEMP 40 // FPU temporary register
171#define PTEMP 41 // Prefetch temporary register
1edfcc68 172//#define TLREG 42 // TLB mapping offset
619e5ded 173#define RHASH 43 // Return address hash
174#define RHTBL 44 // Return address hash table address
175#define RTEMP 45 // JR/JALR address register
176#define MAXREG 45
177#define AGEN1 46 // Address generation temporary register
1edfcc68 178//#define AGEN2 47 // Address generation temporary register
179//#define MGEN1 48 // Maptable address generation temporary register
180//#define MGEN2 49 // Maptable address generation temporary register
619e5ded 181#define BTREG 50 // Branch target temporary register
57871462 182
183 /* instruction types */
184#define NOP 0 // No operation
185#define LOAD 1 // Load
186#define STORE 2 // Store
187#define LOADLR 3 // Unaligned load
188#define STORELR 4 // Unaligned store
9f51b4b9 189#define MOV 5 // Move
57871462 190#define ALU 6 // Arithmetic/logic
191#define MULTDIV 7 // Multiply/divide
192#define SHIFT 8 // Shift by register
193#define SHIFTIMM 9// Shift by immediate
194#define IMM16 10 // 16-bit immediate
195#define RJUMP 11 // Unconditional jump to register
196#define UJUMP 12 // Unconditional jump
197#define CJUMP 13 // Conditional branch (BEQ/BNE/BGTZ/BLEZ)
198#define SJUMP 14 // Conditional branch (regimm format)
199#define COP0 15 // Coprocessor 0
200#define COP1 16 // Coprocessor 1
201#define C1LS 17 // Coprocessor 1 load/store
202#define FJUMP 18 // Conditional branch (floating point)
203#define FLOAT 19 // Floating point unit
204#define FCONV 20 // Convert integer to float
205#define FCOMP 21 // Floating point compare (sets FSREG)
206#define SYSCALL 22// SYSCALL
207#define OTHER 23 // Other
208#define SPAN 24 // Branch/delay slot spans 2 pages
209#define NI 25 // Not implemented
7139f3c8 210#define HLECALL 26// PCSX fake opcodes for HLE
b9b61529 211#define COP2 27 // Coprocessor 2 move
212#define C2LS 28 // Coprocessor 2 load/store
213#define C2OP 29 // Coprocessor 2 operation
1e973cb0 214#define INTCALL 30// Call interpreter to handle rare corner cases
57871462 215
216 /* stubs */
217#define CC_STUB 1
218#define FP_STUB 2
219#define LOADB_STUB 3
220#define LOADH_STUB 4
221#define LOADW_STUB 5
222#define LOADD_STUB 6
223#define LOADBU_STUB 7
224#define LOADHU_STUB 8
225#define STOREB_STUB 9
226#define STOREH_STUB 10
227#define STOREW_STUB 11
228#define STORED_STUB 12
229#define STORELR_STUB 13
230#define INVCODE_STUB 14
231
232 /* branch codes */
233#define TAKEN 1
234#define NOTTAKEN 2
235#define NULLDS 3
236
237// asm linkage
238int new_recompile_block(int addr);
239void *get_addr_ht(u_int vaddr);
240void invalidate_block(u_int block);
241void invalidate_addr(u_int addr);
242void remove_hash(int vaddr);
57871462 243void dyna_linker();
244void dyna_linker_ds();
245void verify_code();
246void verify_code_vm();
247void verify_code_ds();
248void cc_interrupt();
249void fp_exception();
250void fp_exception_ds();
7139f3c8 251void jump_syscall_hle();
7139f3c8 252void jump_hlecall();
1e973cb0 253void jump_intcall();
7139f3c8 254void new_dyna_leave();
57871462 255
57871462 256// Needed by assembler
257void wb_register(signed char r,signed char regmap[],uint64_t dirty,uint64_t is32);
258void wb_dirtys(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty);
259void wb_needed_dirtys(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr);
260void load_all_regs(signed char i_regmap[]);
261void load_needed_regs(signed char i_regmap[],signed char next_regmap[]);
262void load_regs_entry(int t);
263void load_all_consts(signed char regmap[],int is32,u_int dirty,int i);
264
265int tracedebug=0;
266
267//#define DEBUG_CYCLE_COUNT 1
268
b6e87b2b 269#define NO_CYCLE_PENALTY_THR 12
270
4e9dcd7f 271int cycle_multiplier; // 100 for 1.0
272
273static int CLOCK_ADJUST(int x)
274{
275 int s=(x>>31)|1;
276 return (x * cycle_multiplier + s * 50) / 100;
277}
278
94d23bb9 279static u_int get_page(u_int vaddr)
57871462 280{
0ce47d46 281 u_int page=vaddr&~0xe0000000;
282 if (page < 0x1000000)
283 page &= ~0x0e00000; // RAM mirrors
284 page>>=12;
57871462 285 if(page>2048) page=2048+(page&2047);
94d23bb9 286 return page;
287}
288
d25604ca 289// no virtual mem in PCSX
290static u_int get_vpage(u_int vaddr)
291{
292 return get_page(vaddr);
293}
94d23bb9 294
295// Get address from virtual address
296// This is called from the recompiled JR/JALR instructions
297void *get_addr(u_int vaddr)
298{
299 u_int page=get_page(vaddr);
300 u_int vpage=get_vpage(vaddr);
57871462 301 struct ll_entry *head;
302 //printf("TRACE: count=%d next=%d (get_addr %x,page %d)\n",Count,next_interupt,vaddr,page);
303 head=jump_in[page];
304 while(head!=NULL) {
de5a60c3 305 if(head->vaddr==vaddr) {
57871462 306 //printf("TRACE: count=%d next=%d (get_addr match %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr);
307 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
308 ht_bin[3]=ht_bin[1];
309 ht_bin[2]=ht_bin[0];
310 ht_bin[1]=(int)head->addr;
311 ht_bin[0]=vaddr;
312 return head->addr;
313 }
314 head=head->next;
315 }
316 head=jump_dirty[vpage];
317 while(head!=NULL) {
de5a60c3 318 if(head->vaddr==vaddr) {
57871462 319 //printf("TRACE: count=%d next=%d (get_addr match dirty %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr);
320 // Don't restore blocks which are about to expire from the cache
321 if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
322 if(verify_dirty(head->addr)) {
323 //printf("restore candidate: %x (%d) d=%d\n",vaddr,page,invalid_code[vaddr>>12]);
324 invalid_code[vaddr>>12]=0;
9be4ba64 325 inv_code_start=inv_code_end=~0;
57871462 326 if(vpage<2048) {
57871462 327 restore_candidate[vpage>>3]|=1<<(vpage&7);
328 }
329 else restore_candidate[page>>3]|=1<<(page&7);
330 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
331 if(ht_bin[0]==vaddr) {
332 ht_bin[1]=(int)head->addr; // Replace existing entry
333 }
334 else
335 {
336 ht_bin[3]=ht_bin[1];
337 ht_bin[2]=ht_bin[0];
338 ht_bin[1]=(int)head->addr;
339 ht_bin[0]=vaddr;
340 }
341 return head->addr;
342 }
343 }
344 head=head->next;
345 }
346 //printf("TRACE: count=%d next=%d (get_addr no-match %x)\n",Count,next_interupt,vaddr);
347 int r=new_recompile_block(vaddr);
348 if(r==0) return get_addr(vaddr);
349 // Execute in unmapped page, generate pagefault execption
350 Status|=2;
351 Cause=(vaddr<<31)|0x8;
352 EPC=(vaddr&1)?vaddr-5:vaddr;
353 BadVAddr=(vaddr&~1);
354 Context=(Context&0xFF80000F)|((BadVAddr>>9)&0x007FFFF0);
355 EntryHi=BadVAddr&0xFFFFE000;
356 return get_addr_ht(0x80000000);
357}
358// Look up address in hash table first
359void *get_addr_ht(u_int vaddr)
360{
361 //printf("TRACE: count=%d next=%d (get_addr_ht %x)\n",Count,next_interupt,vaddr);
362 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
363 if(ht_bin[0]==vaddr) return (void *)ht_bin[1];
364 if(ht_bin[2]==vaddr) return (void *)ht_bin[3];
365 return get_addr(vaddr);
366}
367
57871462 368void clear_all_regs(signed char regmap[])
369{
370 int hr;
371 for (hr=0;hr<HOST_REGS;hr++) regmap[hr]=-1;
372}
373
374signed char get_reg(signed char regmap[],int r)
375{
376 int hr;
377 for (hr=0;hr<HOST_REGS;hr++) if(hr!=EXCLUDE_REG&&regmap[hr]==r) return hr;
378 return -1;
379}
380
381// Find a register that is available for two consecutive cycles
382signed char get_reg2(signed char regmap1[],signed char regmap2[],int r)
383{
384 int hr;
385 for (hr=0;hr<HOST_REGS;hr++) if(hr!=EXCLUDE_REG&&regmap1[hr]==r&&regmap2[hr]==r) return hr;
386 return -1;
387}
388
389int count_free_regs(signed char regmap[])
390{
391 int count=0;
392 int hr;
393 for(hr=0;hr<HOST_REGS;hr++)
394 {
395 if(hr!=EXCLUDE_REG) {
396 if(regmap[hr]<0) count++;
397 }
398 }
399 return count;
400}
401
402void dirty_reg(struct regstat *cur,signed char reg)
403{
404 int hr;
405 if(!reg) return;
406 for (hr=0;hr<HOST_REGS;hr++) {
407 if((cur->regmap[hr]&63)==reg) {
408 cur->dirty|=1<<hr;
409 }
410 }
411}
412
413// If we dirty the lower half of a 64 bit register which is now being
414// sign-extended, we need to dump the upper half.
415// Note: Do this only after completion of the instruction, because
416// some instructions may need to read the full 64-bit value even if
417// overwriting it (eg SLTI, DSRA32).
418static void flush_dirty_uppers(struct regstat *cur)
419{
420 int hr,reg;
421 for (hr=0;hr<HOST_REGS;hr++) {
422 if((cur->dirty>>hr)&1) {
423 reg=cur->regmap[hr];
9f51b4b9 424 if(reg>=64)
57871462 425 if((cur->is32>>(reg&63))&1) cur->regmap[hr]=-1;
426 }
427 }
428}
429
430void set_const(struct regstat *cur,signed char reg,uint64_t value)
431{
432 int hr;
433 if(!reg) return;
434 for (hr=0;hr<HOST_REGS;hr++) {
435 if(cur->regmap[hr]==reg) {
436 cur->isconst|=1<<hr;
956f3129 437 current_constmap[hr]=value;
57871462 438 }
439 else if((cur->regmap[hr]^64)==reg) {
440 cur->isconst|=1<<hr;
956f3129 441 current_constmap[hr]=value>>32;
57871462 442 }
443 }
444}
445
446void clear_const(struct regstat *cur,signed char reg)
447{
448 int hr;
449 if(!reg) return;
450 for (hr=0;hr<HOST_REGS;hr++) {
451 if((cur->regmap[hr]&63)==reg) {
452 cur->isconst&=~(1<<hr);
453 }
454 }
455}
456
457int is_const(struct regstat *cur,signed char reg)
458{
459 int hr;
79c75f1b 460 if(reg<0) return 0;
57871462 461 if(!reg) return 1;
462 for (hr=0;hr<HOST_REGS;hr++) {
463 if((cur->regmap[hr]&63)==reg) {
464 return (cur->isconst>>hr)&1;
465 }
466 }
467 return 0;
468}
469uint64_t get_const(struct regstat *cur,signed char reg)
470{
471 int hr;
472 if(!reg) return 0;
473 for (hr=0;hr<HOST_REGS;hr++) {
474 if(cur->regmap[hr]==reg) {
956f3129 475 return current_constmap[hr];
57871462 476 }
477 }
c43b5311 478 SysPrintf("Unknown constant in r%d\n",reg);
57871462 479 exit(1);
480}
481
482// Least soon needed registers
483// Look at the next ten instructions and see which registers
484// will be used. Try not to reallocate these.
485void lsn(u_char hsn[], int i, int *preferred_reg)
486{
487 int j;
488 int b=-1;
489 for(j=0;j<9;j++)
490 {
491 if(i+j>=slen) {
492 j=slen-i-1;
493 break;
494 }
495 if(itype[i+j]==UJUMP||itype[i+j]==RJUMP||(source[i+j]>>16)==0x1000)
496 {
497 // Don't go past an unconditonal jump
498 j++;
499 break;
500 }
501 }
502 for(;j>=0;j--)
503 {
504 if(rs1[i+j]) hsn[rs1[i+j]]=j;
505 if(rs2[i+j]) hsn[rs2[i+j]]=j;
506 if(rt1[i+j]) hsn[rt1[i+j]]=j;
507 if(rt2[i+j]) hsn[rt2[i+j]]=j;
508 if(itype[i+j]==STORE || itype[i+j]==STORELR) {
509 // Stores can allocate zero
510 hsn[rs1[i+j]]=j;
511 hsn[rs2[i+j]]=j;
512 }
513 // On some architectures stores need invc_ptr
514 #if defined(HOST_IMM8)
b9b61529 515 if(itype[i+j]==STORE || itype[i+j]==STORELR || (opcode[i+j]&0x3b)==0x39 || (opcode[i+j]&0x3b)==0x3a) {
57871462 516 hsn[INVCP]=j;
517 }
518 #endif
519 if(i+j>=0&&(itype[i+j]==UJUMP||itype[i+j]==CJUMP||itype[i+j]==SJUMP||itype[i+j]==FJUMP))
520 {
521 hsn[CCREG]=j;
522 b=j;
523 }
524 }
525 if(b>=0)
526 {
527 if(ba[i+b]>=start && ba[i+b]<(start+slen*4))
528 {
529 // Follow first branch
530 int t=(ba[i+b]-start)>>2;
531 j=7-b;if(t+j>=slen) j=slen-t-1;
532 for(;j>=0;j--)
533 {
534 if(rs1[t+j]) if(hsn[rs1[t+j]]>j+b+2) hsn[rs1[t+j]]=j+b+2;
535 if(rs2[t+j]) if(hsn[rs2[t+j]]>j+b+2) hsn[rs2[t+j]]=j+b+2;
536 //if(rt1[t+j]) if(hsn[rt1[t+j]]>j+b+2) hsn[rt1[t+j]]=j+b+2;
537 //if(rt2[t+j]) if(hsn[rt2[t+j]]>j+b+2) hsn[rt2[t+j]]=j+b+2;
538 }
539 }
540 // TODO: preferred register based on backward branch
541 }
542 // Delay slot should preferably not overwrite branch conditions or cycle count
543 if(i>0&&(itype[i-1]==RJUMP||itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP)) {
544 if(rs1[i-1]) if(hsn[rs1[i-1]]>1) hsn[rs1[i-1]]=1;
545 if(rs2[i-1]) if(hsn[rs2[i-1]]>1) hsn[rs2[i-1]]=1;
546 hsn[CCREG]=1;
547 // ...or hash tables
548 hsn[RHASH]=1;
549 hsn[RHTBL]=1;
550 }
551 // Coprocessor load/store needs FTEMP, even if not declared
b9b61529 552 if(itype[i]==C1LS||itype[i]==C2LS) {
57871462 553 hsn[FTEMP]=0;
554 }
555 // Load L/R also uses FTEMP as a temporary register
556 if(itype[i]==LOADLR) {
557 hsn[FTEMP]=0;
558 }
b7918751 559 // Also SWL/SWR/SDL/SDR
560 if(opcode[i]==0x2a||opcode[i]==0x2e||opcode[i]==0x2c||opcode[i]==0x2d) {
57871462 561 hsn[FTEMP]=0;
562 }
57871462 563 // Don't remove the miniht registers
564 if(itype[i]==UJUMP||itype[i]==RJUMP)
565 {
566 hsn[RHASH]=0;
567 hsn[RHTBL]=0;
568 }
569}
570
571// We only want to allocate registers if we're going to use them again soon
572int needed_again(int r, int i)
573{
574 int j;
575 int b=-1;
576 int rn=10;
9f51b4b9 577
57871462 578 if(i>0&&(itype[i-1]==UJUMP||itype[i-1]==RJUMP||(source[i-1]>>16)==0x1000))
579 {
580 if(ba[i-1]<start || ba[i-1]>start+slen*4-4)
581 return 0; // Don't need any registers if exiting the block
582 }
583 for(j=0;j<9;j++)
584 {
585 if(i+j>=slen) {
586 j=slen-i-1;
587 break;
588 }
589 if(itype[i+j]==UJUMP||itype[i+j]==RJUMP||(source[i+j]>>16)==0x1000)
590 {
591 // Don't go past an unconditonal jump
592 j++;
593 break;
594 }
1e973cb0 595 if(itype[i+j]==SYSCALL||itype[i+j]==HLECALL||itype[i+j]==INTCALL||((source[i+j]&0xfc00003f)==0x0d))
57871462 596 {
597 break;
598 }
599 }
600 for(;j>=1;j--)
601 {
602 if(rs1[i+j]==r) rn=j;
603 if(rs2[i+j]==r) rn=j;
604 if((unneeded_reg[i+j]>>r)&1) rn=10;
605 if(i+j>=0&&(itype[i+j]==UJUMP||itype[i+j]==CJUMP||itype[i+j]==SJUMP||itype[i+j]==FJUMP))
606 {
607 b=j;
608 }
609 }
610 /*
611 if(b>=0)
612 {
613 if(ba[i+b]>=start && ba[i+b]<(start+slen*4))
614 {
615 // Follow first branch
616 int o=rn;
617 int t=(ba[i+b]-start)>>2;
618 j=7-b;if(t+j>=slen) j=slen-t-1;
619 for(;j>=0;j--)
620 {
621 if(!((unneeded_reg[t+j]>>r)&1)) {
622 if(rs1[t+j]==r) if(rn>j+b+2) rn=j+b+2;
623 if(rs2[t+j]==r) if(rn>j+b+2) rn=j+b+2;
624 }
625 else rn=o;
626 }
627 }
628 }*/
b7217e13 629 if(rn<10) return 1;
57871462 630 return 0;
631}
632
633// Try to match register allocations at the end of a loop with those
634// at the beginning
635int loop_reg(int i, int r, int hr)
636{
637 int j,k;
638 for(j=0;j<9;j++)
639 {
640 if(i+j>=slen) {
641 j=slen-i-1;
642 break;
643 }
644 if(itype[i+j]==UJUMP||itype[i+j]==RJUMP||(source[i+j]>>16)==0x1000)
645 {
646 // Don't go past an unconditonal jump
647 j++;
648 break;
649 }
650 }
651 k=0;
652 if(i>0){
653 if(itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP)
654 k--;
655 }
656 for(;k<j;k++)
657 {
658 if(r<64&&((unneeded_reg[i+k]>>r)&1)) return hr;
659 if(r>64&&((unneeded_reg_upper[i+k]>>r)&1)) return hr;
660 if(i+k>=0&&(itype[i+k]==UJUMP||itype[i+k]==CJUMP||itype[i+k]==SJUMP||itype[i+k]==FJUMP))
661 {
662 if(ba[i+k]>=start && ba[i+k]<(start+i*4))
663 {
664 int t=(ba[i+k]-start)>>2;
665 int reg=get_reg(regs[t].regmap_entry,r);
666 if(reg>=0) return reg;
667 //reg=get_reg(regs[t+1].regmap_entry,r);
668 //if(reg>=0) return reg;
669 }
670 }
671 }
672 return hr;
673}
674
675
676// Allocate every register, preserving source/target regs
677void alloc_all(struct regstat *cur,int i)
678{
679 int hr;
9f51b4b9 680
57871462 681 for(hr=0;hr<HOST_REGS;hr++) {
682 if(hr!=EXCLUDE_REG) {
683 if(((cur->regmap[hr]&63)!=rs1[i])&&((cur->regmap[hr]&63)!=rs2[i])&&
684 ((cur->regmap[hr]&63)!=rt1[i])&&((cur->regmap[hr]&63)!=rt2[i]))
685 {
686 cur->regmap[hr]=-1;
687 cur->dirty&=~(1<<hr);
688 }
689 // Don't need zeros
690 if((cur->regmap[hr]&63)==0)
691 {
692 cur->regmap[hr]=-1;
693 cur->dirty&=~(1<<hr);
694 }
695 }
696 }
697}
698
57871462 699#ifdef __i386__
700#include "assem_x86.c"
701#endif
702#ifdef __x86_64__
703#include "assem_x64.c"
704#endif
705#ifdef __arm__
706#include "assem_arm.c"
707#endif
708
709// Add virtual address mapping to linked list
710void ll_add(struct ll_entry **head,int vaddr,void *addr)
711{
712 struct ll_entry *new_entry;
713 new_entry=malloc(sizeof(struct ll_entry));
714 assert(new_entry!=NULL);
715 new_entry->vaddr=vaddr;
de5a60c3 716 new_entry->reg_sv_flags=0;
57871462 717 new_entry->addr=addr;
718 new_entry->next=*head;
719 *head=new_entry;
720}
721
de5a60c3 722void ll_add_flags(struct ll_entry **head,int vaddr,u_int reg_sv_flags,void *addr)
57871462 723{
7139f3c8 724 ll_add(head,vaddr,addr);
de5a60c3 725 (*head)->reg_sv_flags=reg_sv_flags;
57871462 726}
727
728// Check if an address is already compiled
729// but don't return addresses which are about to expire from the cache
730void *check_addr(u_int vaddr)
731{
732 u_int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
733 if(ht_bin[0]==vaddr) {
734 if(((ht_bin[1]-MAX_OUTPUT_BLOCK_SIZE-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
735 if(isclean(ht_bin[1])) return (void *)ht_bin[1];
736 }
737 if(ht_bin[2]==vaddr) {
738 if(((ht_bin[3]-MAX_OUTPUT_BLOCK_SIZE-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
739 if(isclean(ht_bin[3])) return (void *)ht_bin[3];
740 }
94d23bb9 741 u_int page=get_page(vaddr);
57871462 742 struct ll_entry *head;
743 head=jump_in[page];
744 while(head!=NULL) {
de5a60c3 745 if(head->vaddr==vaddr) {
57871462 746 if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2))) {
747 // Update existing entry with current address
748 if(ht_bin[0]==vaddr) {
749 ht_bin[1]=(int)head->addr;
750 return head->addr;
751 }
752 if(ht_bin[2]==vaddr) {
753 ht_bin[3]=(int)head->addr;
754 return head->addr;
755 }
756 // Insert into hash table with low priority.
757 // Don't evict existing entries, as they are probably
758 // addresses that are being accessed frequently.
759 if(ht_bin[0]==-1) {
760 ht_bin[1]=(int)head->addr;
761 ht_bin[0]=vaddr;
762 }else if(ht_bin[2]==-1) {
763 ht_bin[3]=(int)head->addr;
764 ht_bin[2]=vaddr;
765 }
766 return head->addr;
767 }
768 }
769 head=head->next;
770 }
771 return 0;
772}
773
774void remove_hash(int vaddr)
775{
776 //printf("remove hash: %x\n",vaddr);
777 int *ht_bin=hash_table[(((vaddr)>>16)^vaddr)&0xFFFF];
778 if(ht_bin[2]==vaddr) {
779 ht_bin[2]=ht_bin[3]=-1;
780 }
781 if(ht_bin[0]==vaddr) {
782 ht_bin[0]=ht_bin[2];
783 ht_bin[1]=ht_bin[3];
784 ht_bin[2]=ht_bin[3]=-1;
785 }
786}
787
788void ll_remove_matching_addrs(struct ll_entry **head,int addr,int shift)
789{
790 struct ll_entry *next;
791 while(*head) {
9f51b4b9 792 if(((u_int)((*head)->addr)>>shift)==(addr>>shift) ||
57871462 793 ((u_int)((*head)->addr-MAX_OUTPUT_BLOCK_SIZE)>>shift)==(addr>>shift))
794 {
795 inv_debug("EXP: Remove pointer to %x (%x)\n",(int)(*head)->addr,(*head)->vaddr);
796 remove_hash((*head)->vaddr);
797 next=(*head)->next;
798 free(*head);
799 *head=next;
800 }
801 else
802 {
803 head=&((*head)->next);
804 }
805 }
806}
807
808// Remove all entries from linked list
809void ll_clear(struct ll_entry **head)
810{
811 struct ll_entry *cur;
812 struct ll_entry *next;
813 if(cur=*head) {
814 *head=0;
815 while(cur) {
816 next=cur->next;
817 free(cur);
818 cur=next;
819 }
820 }
821}
822
823// Dereference the pointers and remove if it matches
824void ll_kill_pointers(struct ll_entry *head,int addr,int shift)
825{
826 while(head) {
827 int ptr=get_pointer(head->addr);
828 inv_debug("EXP: Lookup pointer to %x at %x (%x)\n",(int)ptr,(int)head->addr,head->vaddr);
829 if(((ptr>>shift)==(addr>>shift)) ||
830 (((ptr-MAX_OUTPUT_BLOCK_SIZE)>>shift)==(addr>>shift)))
831 {
5088bb70 832 inv_debug("EXP: Kill pointer at %x (%x)\n",(int)head->addr,head->vaddr);
f76eeef9 833 u_int host_addr=(u_int)kill_pointer(head->addr);
dd3a91a1 834 #ifdef __arm__
835 needs_clear_cache[(host_addr-(u_int)BASE_ADDR)>>17]|=1<<(((host_addr-(u_int)BASE_ADDR)>>12)&31);
836 #endif
57871462 837 }
838 head=head->next;
839 }
840}
841
842// This is called when we write to a compiled block (see do_invstub)
f76eeef9 843void invalidate_page(u_int page)
57871462 844{
57871462 845 struct ll_entry *head;
846 struct ll_entry *next;
847 head=jump_in[page];
848 jump_in[page]=0;
849 while(head!=NULL) {
850 inv_debug("INVALIDATE: %x\n",head->vaddr);
851 remove_hash(head->vaddr);
852 next=head->next;
853 free(head);
854 head=next;
855 }
856 head=jump_out[page];
857 jump_out[page]=0;
858 while(head!=NULL) {
859 inv_debug("INVALIDATE: kill pointer to %x (%x)\n",head->vaddr,(int)head->addr);
f76eeef9 860 u_int host_addr=(u_int)kill_pointer(head->addr);
dd3a91a1 861 #ifdef __arm__
862 needs_clear_cache[(host_addr-(u_int)BASE_ADDR)>>17]|=1<<(((host_addr-(u_int)BASE_ADDR)>>12)&31);
863 #endif
57871462 864 next=head->next;
865 free(head);
866 head=next;
867 }
57871462 868}
9be4ba64 869
870static void invalidate_block_range(u_int block, u_int first, u_int last)
57871462 871{
94d23bb9 872 u_int page=get_page(block<<12);
57871462 873 //printf("first=%d last=%d\n",first,last);
f76eeef9 874 invalidate_page(page);
57871462 875 assert(first+5>page); // NB: this assumes MAXBLOCK<=4096 (4 pages)
876 assert(last<page+5);
877 // Invalidate the adjacent pages if a block crosses a 4K boundary
878 while(first<page) {
879 invalidate_page(first);
880 first++;
881 }
882 for(first=page+1;first<last;first++) {
883 invalidate_page(first);
884 }
dd3a91a1 885 #ifdef __arm__
886 do_clear_cache();
887 #endif
9f51b4b9 888
57871462 889 // Don't trap writes
890 invalid_code[block]=1;
f76eeef9 891
57871462 892 #ifdef USE_MINI_HT
893 memset(mini_ht,-1,sizeof(mini_ht));
894 #endif
895}
9be4ba64 896
897void invalidate_block(u_int block)
898{
899 u_int page=get_page(block<<12);
900 u_int vpage=get_vpage(block<<12);
901 inv_debug("INVALIDATE: %x (%d)\n",block<<12,page);
902 //inv_debug("invalid_code[block]=%d\n",invalid_code[block]);
903 u_int first,last;
904 first=last=page;
905 struct ll_entry *head;
906 head=jump_dirty[vpage];
907 //printf("page=%d vpage=%d\n",page,vpage);
908 while(head!=NULL) {
909 u_int start,end;
910 if(vpage>2047||(head->vaddr>>12)==block) { // Ignore vaddr hash collision
911 get_bounds((int)head->addr,&start,&end);
912 //printf("start: %x end: %x\n",start,end);
4a35de07 913 if(page<2048&&start>=(u_int)rdram&&end<(u_int)rdram+RAM_SIZE) {
9be4ba64 914 if(((start-(u_int)rdram)>>12)<=page&&((end-1-(u_int)rdram)>>12)>=page) {
915 if((((start-(u_int)rdram)>>12)&2047)<first) first=((start-(u_int)rdram)>>12)&2047;
916 if((((end-1-(u_int)rdram)>>12)&2047)>last) last=((end-1-(u_int)rdram)>>12)&2047;
917 }
918 }
9be4ba64 919 }
920 head=head->next;
921 }
922 invalidate_block_range(block,first,last);
923}
924
57871462 925void invalidate_addr(u_int addr)
926{
9be4ba64 927 //static int rhits;
928 // this check is done by the caller
929 //if (inv_code_start<=addr&&addr<=inv_code_end) { rhits++; return; }
d25604ca 930 u_int page=get_vpage(addr);
9be4ba64 931 if(page<2048) { // RAM
932 struct ll_entry *head;
933 u_int addr_min=~0, addr_max=0;
4a35de07 934 u_int mask=RAM_SIZE-1;
935 u_int addr_main=0x80000000|(addr&mask);
9be4ba64 936 int pg1;
4a35de07 937 inv_code_start=addr_main&~0xfff;
938 inv_code_end=addr_main|0xfff;
9be4ba64 939 pg1=page;
940 if (pg1>0) {
941 // must check previous page too because of spans..
942 pg1--;
943 inv_code_start-=0x1000;
944 }
945 for(;pg1<=page;pg1++) {
946 for(head=jump_dirty[pg1];head!=NULL;head=head->next) {
947 u_int start,end;
948 get_bounds((int)head->addr,&start,&end);
4a35de07 949 if(ram_offset) {
950 start-=ram_offset;
951 end-=ram_offset;
952 }
953 if(start<=addr_main&&addr_main<end) {
9be4ba64 954 if(start<addr_min) addr_min=start;
955 if(end>addr_max) addr_max=end;
956 }
4a35de07 957 else if(addr_main<start) {
9be4ba64 958 if(start<inv_code_end)
959 inv_code_end=start-1;
960 }
961 else {
962 if(end>inv_code_start)
963 inv_code_start=end;
964 }
965 }
966 }
967 if (addr_min!=~0) {
968 inv_debug("INV ADDR: %08x hit %08x-%08x\n", addr, addr_min, addr_max);
969 inv_code_start=inv_code_end=~0;
970 invalidate_block_range(addr>>12,(addr_min&mask)>>12,(addr_max&mask)>>12);
971 return;
972 }
973 else {
4a35de07 974 inv_code_start=(addr&~mask)|(inv_code_start&mask);
975 inv_code_end=(addr&~mask)|(inv_code_end&mask);
d25604ca 976 inv_debug("INV ADDR: %08x miss, inv %08x-%08x, sk %d\n", addr, inv_code_start, inv_code_end, 0);
9be4ba64 977 return;
d25604ca 978 }
9be4ba64 979 }
57871462 980 invalidate_block(addr>>12);
981}
9be4ba64 982
dd3a91a1 983// This is called when loading a save state.
984// Anything could have changed, so invalidate everything.
57871462 985void invalidate_all_pages()
986{
987 u_int page,n;
988 for(page=0;page<4096;page++)
989 invalidate_page(page);
990 for(page=0;page<1048576;page++)
991 if(!invalid_code[page]) {
992 restore_candidate[(page&2047)>>3]|=1<<(page&7);
993 restore_candidate[((page&2047)>>3)+256]|=1<<(page&7);
994 }
995 #ifdef __arm__
996 __clear_cache((void *)BASE_ADDR,(void *)BASE_ADDR+(1<<TARGET_SIZE_2));
997 #endif
998 #ifdef USE_MINI_HT
999 memset(mini_ht,-1,sizeof(mini_ht));
1000 #endif
57871462 1001}
1002
1003// Add an entry to jump_out after making a link
1004void add_link(u_int vaddr,void *src)
1005{
94d23bb9 1006 u_int page=get_page(vaddr);
57871462 1007 inv_debug("add_link: %x -> %x (%d)\n",(int)src,vaddr,page);
76f71c27 1008 int *ptr=(int *)(src+4);
1009 assert((*ptr&0x0fff0000)==0x059f0000);
57871462 1010 ll_add(jump_out+page,vaddr,src);
1011 //int ptr=get_pointer(src);
1012 //inv_debug("add_link: Pointer is to %x\n",(int)ptr);
1013}
1014
1015// If a code block was found to be unmodified (bit was set in
1016// restore_candidate) and it remains unmodified (bit is clear
1017// in invalid_code) then move the entries for that 4K page from
1018// the dirty list to the clean list.
1019void clean_blocks(u_int page)
1020{
1021 struct ll_entry *head;
1022 inv_debug("INV: clean_blocks page=%d\n",page);
1023 head=jump_dirty[page];
1024 while(head!=NULL) {
1025 if(!invalid_code[head->vaddr>>12]) {
1026 // Don't restore blocks which are about to expire from the cache
1027 if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2))) {
1028 u_int start,end;
1029 if(verify_dirty((int)head->addr)) {
1030 //printf("Possibly Restore %x (%x)\n",head->vaddr, (int)head->addr);
1031 u_int i;
1032 u_int inv=0;
1033 get_bounds((int)head->addr,&start,&end);
4cb76aa4 1034 if(start-(u_int)rdram<RAM_SIZE) {
57871462 1035 for(i=(start-(u_int)rdram+0x80000000)>>12;i<=(end-1-(u_int)rdram+0x80000000)>>12;i++) {
1036 inv|=invalid_code[i];
1037 }
1038 }
4cb76aa4 1039 else if((signed int)head->vaddr>=(signed int)0x80000000+RAM_SIZE) {
57871462 1040 inv=1;
1041 }
1042 if(!inv) {
1043 void * clean_addr=(void *)get_clean_addr((int)head->addr);
1044 if((((u_int)clean_addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2))) {
1045 u_int ppage=page;
57871462 1046 inv_debug("INV: Restored %x (%x/%x)\n",head->vaddr, (int)head->addr, (int)clean_addr);
1047 //printf("page=%x, addr=%x\n",page,head->vaddr);
1048 //assert(head->vaddr>>12==(page|0x80000));
de5a60c3 1049 ll_add_flags(jump_in+ppage,head->vaddr,head->reg_sv_flags,clean_addr);
57871462 1050 int *ht_bin=hash_table[((head->vaddr>>16)^head->vaddr)&0xFFFF];
de5a60c3 1051 if(ht_bin[0]==head->vaddr) {
1052 ht_bin[1]=(int)clean_addr; // Replace existing entry
1053 }
1054 if(ht_bin[2]==head->vaddr) {
1055 ht_bin[3]=(int)clean_addr; // Replace existing entry
57871462 1056 }
1057 }
1058 }
1059 }
1060 }
1061 }
1062 head=head->next;
1063 }
1064}
1065
1066
1067void mov_alloc(struct regstat *current,int i)
1068{
1069 // Note: Don't need to actually alloc the source registers
1070 if((~current->is32>>rs1[i])&1) {
1071 //alloc_reg64(current,i,rs1[i]);
1072 alloc_reg64(current,i,rt1[i]);
1073 current->is32&=~(1LL<<rt1[i]);
1074 } else {
1075 //alloc_reg(current,i,rs1[i]);
1076 alloc_reg(current,i,rt1[i]);
1077 current->is32|=(1LL<<rt1[i]);
1078 }
1079 clear_const(current,rs1[i]);
1080 clear_const(current,rt1[i]);
1081 dirty_reg(current,rt1[i]);
1082}
1083
1084void shiftimm_alloc(struct regstat *current,int i)
1085{
57871462 1086 if(opcode2[i]<=0x3) // SLL/SRL/SRA
1087 {
1088 if(rt1[i]) {
1089 if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1090 else lt1[i]=rs1[i];
1091 alloc_reg(current,i,rt1[i]);
1092 current->is32|=1LL<<rt1[i];
1093 dirty_reg(current,rt1[i]);
dc49e339 1094 if(is_const(current,rs1[i])) {
1095 int v=get_const(current,rs1[i]);
1096 if(opcode2[i]==0x00) set_const(current,rt1[i],v<<imm[i]);
1097 if(opcode2[i]==0x02) set_const(current,rt1[i],(u_int)v>>imm[i]);
1098 if(opcode2[i]==0x03) set_const(current,rt1[i],v>>imm[i]);
1099 }
1100 else clear_const(current,rt1[i]);
57871462 1101 }
1102 }
dc49e339 1103 else
1104 {
1105 clear_const(current,rs1[i]);
1106 clear_const(current,rt1[i]);
1107 }
1108
57871462 1109 if(opcode2[i]>=0x38&&opcode2[i]<=0x3b) // DSLL/DSRL/DSRA
1110 {
1111 if(rt1[i]) {
1112 if(rs1[i]) alloc_reg64(current,i,rs1[i]);
1113 alloc_reg64(current,i,rt1[i]);
1114 current->is32&=~(1LL<<rt1[i]);
1115 dirty_reg(current,rt1[i]);
1116 }
1117 }
1118 if(opcode2[i]==0x3c) // DSLL32
1119 {
1120 if(rt1[i]) {
1121 if(rs1[i]) alloc_reg(current,i,rs1[i]);
1122 alloc_reg64(current,i,rt1[i]);
1123 current->is32&=~(1LL<<rt1[i]);
1124 dirty_reg(current,rt1[i]);
1125 }
1126 }
1127 if(opcode2[i]==0x3e) // DSRL32
1128 {
1129 if(rt1[i]) {
1130 alloc_reg64(current,i,rs1[i]);
1131 if(imm[i]==32) {
1132 alloc_reg64(current,i,rt1[i]);
1133 current->is32&=~(1LL<<rt1[i]);
1134 } else {
1135 alloc_reg(current,i,rt1[i]);
1136 current->is32|=1LL<<rt1[i];
1137 }
1138 dirty_reg(current,rt1[i]);
1139 }
1140 }
1141 if(opcode2[i]==0x3f) // DSRA32
1142 {
1143 if(rt1[i]) {
1144 alloc_reg64(current,i,rs1[i]);
1145 alloc_reg(current,i,rt1[i]);
1146 current->is32|=1LL<<rt1[i];
1147 dirty_reg(current,rt1[i]);
1148 }
1149 }
1150}
1151
1152void shift_alloc(struct regstat *current,int i)
1153{
1154 if(rt1[i]) {
1155 if(opcode2[i]<=0x07) // SLLV/SRLV/SRAV
1156 {
1157 if(rs1[i]) alloc_reg(current,i,rs1[i]);
1158 if(rs2[i]) alloc_reg(current,i,rs2[i]);
1159 alloc_reg(current,i,rt1[i]);
e1190b87 1160 if(rt1[i]==rs2[i]) {
1161 alloc_reg_temp(current,i,-1);
1162 minimum_free_regs[i]=1;
1163 }
57871462 1164 current->is32|=1LL<<rt1[i];
1165 } else { // DSLLV/DSRLV/DSRAV
1166 if(rs1[i]) alloc_reg64(current,i,rs1[i]);
1167 if(rs2[i]) alloc_reg(current,i,rs2[i]);
1168 alloc_reg64(current,i,rt1[i]);
1169 current->is32&=~(1LL<<rt1[i]);
1170 if(opcode2[i]==0x16||opcode2[i]==0x17) // DSRLV and DSRAV need a temporary register
e1190b87 1171 {
57871462 1172 alloc_reg_temp(current,i,-1);
e1190b87 1173 minimum_free_regs[i]=1;
1174 }
57871462 1175 }
1176 clear_const(current,rs1[i]);
1177 clear_const(current,rs2[i]);
1178 clear_const(current,rt1[i]);
1179 dirty_reg(current,rt1[i]);
1180 }
1181}
1182
1183void alu_alloc(struct regstat *current,int i)
1184{
1185 if(opcode2[i]>=0x20&&opcode2[i]<=0x23) { // ADD/ADDU/SUB/SUBU
1186 if(rt1[i]) {
1187 if(rs1[i]&&rs2[i]) {
1188 alloc_reg(current,i,rs1[i]);
1189 alloc_reg(current,i,rs2[i]);
1190 }
1191 else {
1192 if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1193 if(rs2[i]&&needed_again(rs2[i],i)) alloc_reg(current,i,rs2[i]);
1194 }
1195 alloc_reg(current,i,rt1[i]);
1196 }
1197 current->is32|=1LL<<rt1[i];
1198 }
1199 if(opcode2[i]==0x2a||opcode2[i]==0x2b) { // SLT/SLTU
1200 if(rt1[i]) {
1201 if(!((current->is32>>rs1[i])&(current->is32>>rs2[i])&1))
1202 {
1203 alloc_reg64(current,i,rs1[i]);
1204 alloc_reg64(current,i,rs2[i]);
1205 alloc_reg(current,i,rt1[i]);
1206 } else {
1207 alloc_reg(current,i,rs1[i]);
1208 alloc_reg(current,i,rs2[i]);
1209 alloc_reg(current,i,rt1[i]);
1210 }
1211 }
1212 current->is32|=1LL<<rt1[i];
1213 }
1214 if(opcode2[i]>=0x24&&opcode2[i]<=0x27) { // AND/OR/XOR/NOR
1215 if(rt1[i]) {
1216 if(rs1[i]&&rs2[i]) {
1217 alloc_reg(current,i,rs1[i]);
1218 alloc_reg(current,i,rs2[i]);
1219 }
1220 else
1221 {
1222 if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1223 if(rs2[i]&&needed_again(rs2[i],i)) alloc_reg(current,i,rs2[i]);
1224 }
1225 alloc_reg(current,i,rt1[i]);
1226 if(!((current->is32>>rs1[i])&(current->is32>>rs2[i])&1))
1227 {
1228 if(!((current->uu>>rt1[i])&1)) {
1229 alloc_reg64(current,i,rt1[i]);
1230 }
1231 if(get_reg(current->regmap,rt1[i]|64)>=0) {
1232 if(rs1[i]&&rs2[i]) {
1233 alloc_reg64(current,i,rs1[i]);
1234 alloc_reg64(current,i,rs2[i]);
1235 }
1236 else
1237 {
1238 // Is is really worth it to keep 64-bit values in registers?
1239 #ifdef NATIVE_64BIT
1240 if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg64(current,i,rs1[i]);
1241 if(rs2[i]&&needed_again(rs2[i],i)) alloc_reg64(current,i,rs2[i]);
1242 #endif
1243 }
1244 }
1245 current->is32&=~(1LL<<rt1[i]);
1246 } else {
1247 current->is32|=1LL<<rt1[i];
1248 }
1249 }
1250 }
1251 if(opcode2[i]>=0x2c&&opcode2[i]<=0x2f) { // DADD/DADDU/DSUB/DSUBU
1252 if(rt1[i]) {
1253 if(rs1[i]&&rs2[i]) {
1254 if(!((current->uu>>rt1[i])&1)||get_reg(current->regmap,rt1[i]|64)>=0) {
1255 alloc_reg64(current,i,rs1[i]);
1256 alloc_reg64(current,i,rs2[i]);
1257 alloc_reg64(current,i,rt1[i]);
1258 } else {
1259 alloc_reg(current,i,rs1[i]);
1260 alloc_reg(current,i,rs2[i]);
1261 alloc_reg(current,i,rt1[i]);
1262 }
1263 }
1264 else {
1265 alloc_reg(current,i,rt1[i]);
1266 if(!((current->uu>>rt1[i])&1)||get_reg(current->regmap,rt1[i]|64)>=0) {
1267 // DADD used as move, or zeroing
1268 // If we have a 64-bit source, then make the target 64 bits too
1269 if(rs1[i]&&!((current->is32>>rs1[i])&1)) {
1270 if(get_reg(current->regmap,rs1[i])>=0) alloc_reg64(current,i,rs1[i]);
1271 alloc_reg64(current,i,rt1[i]);
1272 } else if(rs2[i]&&!((current->is32>>rs2[i])&1)) {
1273 if(get_reg(current->regmap,rs2[i])>=0) alloc_reg64(current,i,rs2[i]);
1274 alloc_reg64(current,i,rt1[i]);
1275 }
1276 if(opcode2[i]>=0x2e&&rs2[i]) {
1277 // DSUB used as negation - 64-bit result
1278 // If we have a 32-bit register, extend it to 64 bits
1279 if(get_reg(current->regmap,rs2[i])>=0) alloc_reg64(current,i,rs2[i]);
1280 alloc_reg64(current,i,rt1[i]);
1281 }
1282 }
1283 }
1284 if(rs1[i]&&rs2[i]) {
1285 current->is32&=~(1LL<<rt1[i]);
1286 } else if(rs1[i]) {
1287 current->is32&=~(1LL<<rt1[i]);
1288 if((current->is32>>rs1[i])&1)
1289 current->is32|=1LL<<rt1[i];
1290 } else if(rs2[i]) {
1291 current->is32&=~(1LL<<rt1[i]);
1292 if((current->is32>>rs2[i])&1)
1293 current->is32|=1LL<<rt1[i];
1294 } else {
1295 current->is32|=1LL<<rt1[i];
1296 }
1297 }
1298 }
1299 clear_const(current,rs1[i]);
1300 clear_const(current,rs2[i]);
1301 clear_const(current,rt1[i]);
1302 dirty_reg(current,rt1[i]);
1303}
1304
1305void imm16_alloc(struct regstat *current,int i)
1306{
1307 if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1308 else lt1[i]=rs1[i];
1309 if(rt1[i]) alloc_reg(current,i,rt1[i]);
1310 if(opcode[i]==0x18||opcode[i]==0x19) { // DADDI/DADDIU
1311 current->is32&=~(1LL<<rt1[i]);
1312 if(!((current->uu>>rt1[i])&1)||get_reg(current->regmap,rt1[i]|64)>=0) {
1313 // TODO: Could preserve the 32-bit flag if the immediate is zero
1314 alloc_reg64(current,i,rt1[i]);
1315 alloc_reg64(current,i,rs1[i]);
1316 }
1317 clear_const(current,rs1[i]);
1318 clear_const(current,rt1[i]);
1319 }
1320 else if(opcode[i]==0x0a||opcode[i]==0x0b) { // SLTI/SLTIU
1321 if((~current->is32>>rs1[i])&1) alloc_reg64(current,i,rs1[i]);
1322 current->is32|=1LL<<rt1[i];
1323 clear_const(current,rs1[i]);
1324 clear_const(current,rt1[i]);
1325 }
1326 else if(opcode[i]>=0x0c&&opcode[i]<=0x0e) { // ANDI/ORI/XORI
1327 if(((~current->is32>>rs1[i])&1)&&opcode[i]>0x0c) {
1328 if(rs1[i]!=rt1[i]) {
1329 if(needed_again(rs1[i],i)) alloc_reg64(current,i,rs1[i]);
1330 alloc_reg64(current,i,rt1[i]);
1331 current->is32&=~(1LL<<rt1[i]);
1332 }
1333 }
1334 else current->is32|=1LL<<rt1[i]; // ANDI clears upper bits
1335 if(is_const(current,rs1[i])) {
1336 int v=get_const(current,rs1[i]);
1337 if(opcode[i]==0x0c) set_const(current,rt1[i],v&imm[i]);
1338 if(opcode[i]==0x0d) set_const(current,rt1[i],v|imm[i]);
1339 if(opcode[i]==0x0e) set_const(current,rt1[i],v^imm[i]);
1340 }
1341 else clear_const(current,rt1[i]);
1342 }
1343 else if(opcode[i]==0x08||opcode[i]==0x09) { // ADDI/ADDIU
1344 if(is_const(current,rs1[i])) {
1345 int v=get_const(current,rs1[i]);
1346 set_const(current,rt1[i],v+imm[i]);
1347 }
1348 else clear_const(current,rt1[i]);
1349 current->is32|=1LL<<rt1[i];
1350 }
1351 else {
1352 set_const(current,rt1[i],((long long)((short)imm[i]))<<16); // LUI
1353 current->is32|=1LL<<rt1[i];
1354 }
1355 dirty_reg(current,rt1[i]);
1356}
1357
1358void load_alloc(struct regstat *current,int i)
1359{
1360 clear_const(current,rt1[i]);
1361 //if(rs1[i]!=rt1[i]&&needed_again(rs1[i],i)) clear_const(current,rs1[i]); // Does this help or hurt?
1362 if(!rs1[i]) current->u&=~1LL; // Allow allocating r0 if it's the source register
1363 if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
373d1d07 1364 if(rt1[i]&&!((current->u>>rt1[i])&1)) {
57871462 1365 alloc_reg(current,i,rt1[i]);
373d1d07 1366 assert(get_reg(current->regmap,rt1[i])>=0);
57871462 1367 if(opcode[i]==0x27||opcode[i]==0x37) // LWU/LD
1368 {
1369 current->is32&=~(1LL<<rt1[i]);
1370 alloc_reg64(current,i,rt1[i]);
1371 }
1372 else if(opcode[i]==0x1A||opcode[i]==0x1B) // LDL/LDR
1373 {
1374 current->is32&=~(1LL<<rt1[i]);
1375 alloc_reg64(current,i,rt1[i]);
1376 alloc_all(current,i);
1377 alloc_reg64(current,i,FTEMP);
e1190b87 1378 minimum_free_regs[i]=HOST_REGS;
57871462 1379 }
1380 else current->is32|=1LL<<rt1[i];
1381 dirty_reg(current,rt1[i]);
57871462 1382 // LWL/LWR need a temporary register for the old value
1383 if(opcode[i]==0x22||opcode[i]==0x26)
1384 {
1385 alloc_reg(current,i,FTEMP);
1386 alloc_reg_temp(current,i,-1);
e1190b87 1387 minimum_free_regs[i]=1;
57871462 1388 }
1389 }
1390 else
1391 {
373d1d07 1392 // Load to r0 or unneeded register (dummy load)
57871462 1393 // but we still need a register to calculate the address
535d208a 1394 if(opcode[i]==0x22||opcode[i]==0x26)
1395 {
1396 alloc_reg(current,i,FTEMP); // LWL/LWR need another temporary
1397 }
57871462 1398 alloc_reg_temp(current,i,-1);
e1190b87 1399 minimum_free_regs[i]=1;
535d208a 1400 if(opcode[i]==0x1A||opcode[i]==0x1B) // LDL/LDR
1401 {
1402 alloc_all(current,i);
1403 alloc_reg64(current,i,FTEMP);
e1190b87 1404 minimum_free_regs[i]=HOST_REGS;
535d208a 1405 }
57871462 1406 }
1407}
1408
1409void store_alloc(struct regstat *current,int i)
1410{
1411 clear_const(current,rs2[i]);
1412 if(!(rs2[i])) current->u&=~1LL; // Allow allocating r0 if necessary
1413 if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1414 alloc_reg(current,i,rs2[i]);
1415 if(opcode[i]==0x2c||opcode[i]==0x2d||opcode[i]==0x3f) { // 64-bit SDL/SDR/SD
1416 alloc_reg64(current,i,rs2[i]);
1417 if(rs2[i]) alloc_reg(current,i,FTEMP);
1418 }
57871462 1419 #if defined(HOST_IMM8)
1420 // On CPUs without 32-bit immediates we need a pointer to invalid_code
1421 else alloc_reg(current,i,INVCP);
1422 #endif
b7918751 1423 if(opcode[i]==0x2a||opcode[i]==0x2e||opcode[i]==0x2c||opcode[i]==0x2d) { // SWL/SWL/SDL/SDR
57871462 1424 alloc_reg(current,i,FTEMP);
1425 }
1426 // We need a temporary register for address generation
1427 alloc_reg_temp(current,i,-1);
e1190b87 1428 minimum_free_regs[i]=1;
57871462 1429}
1430
1431void c1ls_alloc(struct regstat *current,int i)
1432{
1433 //clear_const(current,rs1[i]); // FIXME
1434 clear_const(current,rt1[i]);
1435 if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1436 alloc_reg(current,i,CSREG); // Status
1437 alloc_reg(current,i,FTEMP);
1438 if(opcode[i]==0x35||opcode[i]==0x3d) { // 64-bit LDC1/SDC1
1439 alloc_reg64(current,i,FTEMP);
1440 }
57871462 1441 #if defined(HOST_IMM8)
1442 // On CPUs without 32-bit immediates we need a pointer to invalid_code
1443 else if((opcode[i]&0x3b)==0x39) // SWC1/SDC1
1444 alloc_reg(current,i,INVCP);
1445 #endif
1446 // We need a temporary register for address generation
1447 alloc_reg_temp(current,i,-1);
1448}
1449
b9b61529 1450void c2ls_alloc(struct regstat *current,int i)
1451{
1452 clear_const(current,rt1[i]);
1453 if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1454 alloc_reg(current,i,FTEMP);
b9b61529 1455 #if defined(HOST_IMM8)
1456 // On CPUs without 32-bit immediates we need a pointer to invalid_code
1edfcc68 1457 if((opcode[i]&0x3b)==0x3a) // SWC2/SDC2
b9b61529 1458 alloc_reg(current,i,INVCP);
1459 #endif
1460 // We need a temporary register for address generation
1461 alloc_reg_temp(current,i,-1);
e1190b87 1462 minimum_free_regs[i]=1;
b9b61529 1463}
1464
57871462 1465#ifndef multdiv_alloc
1466void multdiv_alloc(struct regstat *current,int i)
1467{
1468 // case 0x18: MULT
1469 // case 0x19: MULTU
1470 // case 0x1A: DIV
1471 // case 0x1B: DIVU
1472 // case 0x1C: DMULT
1473 // case 0x1D: DMULTU
1474 // case 0x1E: DDIV
1475 // case 0x1F: DDIVU
1476 clear_const(current,rs1[i]);
1477 clear_const(current,rs2[i]);
1478 if(rs1[i]&&rs2[i])
1479 {
1480 if((opcode2[i]&4)==0) // 32-bit
1481 {
1482 current->u&=~(1LL<<HIREG);
1483 current->u&=~(1LL<<LOREG);
1484 alloc_reg(current,i,HIREG);
1485 alloc_reg(current,i,LOREG);
1486 alloc_reg(current,i,rs1[i]);
1487 alloc_reg(current,i,rs2[i]);
1488 current->is32|=1LL<<HIREG;
1489 current->is32|=1LL<<LOREG;
1490 dirty_reg(current,HIREG);
1491 dirty_reg(current,LOREG);
1492 }
1493 else // 64-bit
1494 {
1495 current->u&=~(1LL<<HIREG);
1496 current->u&=~(1LL<<LOREG);
1497 current->uu&=~(1LL<<HIREG);
1498 current->uu&=~(1LL<<LOREG);
1499 alloc_reg64(current,i,HIREG);
1500 //if(HOST_REGS>10) alloc_reg64(current,i,LOREG);
1501 alloc_reg64(current,i,rs1[i]);
1502 alloc_reg64(current,i,rs2[i]);
1503 alloc_all(current,i);
1504 current->is32&=~(1LL<<HIREG);
1505 current->is32&=~(1LL<<LOREG);
1506 dirty_reg(current,HIREG);
1507 dirty_reg(current,LOREG);
e1190b87 1508 minimum_free_regs[i]=HOST_REGS;
57871462 1509 }
1510 }
1511 else
1512 {
1513 // Multiply by zero is zero.
1514 // MIPS does not have a divide by zero exception.
1515 // The result is undefined, we return zero.
1516 alloc_reg(current,i,HIREG);
1517 alloc_reg(current,i,LOREG);
1518 current->is32|=1LL<<HIREG;
1519 current->is32|=1LL<<LOREG;
1520 dirty_reg(current,HIREG);
1521 dirty_reg(current,LOREG);
1522 }
1523}
1524#endif
1525
1526void cop0_alloc(struct regstat *current,int i)
1527{
1528 if(opcode2[i]==0) // MFC0
1529 {
1530 if(rt1[i]) {
1531 clear_const(current,rt1[i]);
1532 alloc_all(current,i);
1533 alloc_reg(current,i,rt1[i]);
1534 current->is32|=1LL<<rt1[i];
1535 dirty_reg(current,rt1[i]);
1536 }
1537 }
1538 else if(opcode2[i]==4) // MTC0
1539 {
1540 if(rs1[i]){
1541 clear_const(current,rs1[i]);
1542 alloc_reg(current,i,rs1[i]);
1543 alloc_all(current,i);
1544 }
1545 else {
1546 alloc_all(current,i); // FIXME: Keep r0
1547 current->u&=~1LL;
1548 alloc_reg(current,i,0);
1549 }
1550 }
1551 else
1552 {
1553 // TLBR/TLBWI/TLBWR/TLBP/ERET
1554 assert(opcode2[i]==0x10);
1555 alloc_all(current,i);
1556 }
e1190b87 1557 minimum_free_regs[i]=HOST_REGS;
57871462 1558}
1559
1560void cop1_alloc(struct regstat *current,int i)
1561{
1562 alloc_reg(current,i,CSREG); // Load status
1563 if(opcode2[i]<3) // MFC1/DMFC1/CFC1
1564 {
7de557a6 1565 if(rt1[i]){
1566 clear_const(current,rt1[i]);
1567 if(opcode2[i]==1) {
1568 alloc_reg64(current,i,rt1[i]); // DMFC1
1569 current->is32&=~(1LL<<rt1[i]);
1570 }else{
1571 alloc_reg(current,i,rt1[i]); // MFC1/CFC1
1572 current->is32|=1LL<<rt1[i];
1573 }
1574 dirty_reg(current,rt1[i]);
57871462 1575 }
57871462 1576 alloc_reg_temp(current,i,-1);
1577 }
1578 else if(opcode2[i]>3) // MTC1/DMTC1/CTC1
1579 {
1580 if(rs1[i]){
1581 clear_const(current,rs1[i]);
1582 if(opcode2[i]==5)
1583 alloc_reg64(current,i,rs1[i]); // DMTC1
1584 else
1585 alloc_reg(current,i,rs1[i]); // MTC1/CTC1
1586 alloc_reg_temp(current,i,-1);
1587 }
1588 else {
1589 current->u&=~1LL;
1590 alloc_reg(current,i,0);
1591 alloc_reg_temp(current,i,-1);
1592 }
1593 }
e1190b87 1594 minimum_free_regs[i]=1;
57871462 1595}
1596void fconv_alloc(struct regstat *current,int i)
1597{
1598 alloc_reg(current,i,CSREG); // Load status
1599 alloc_reg_temp(current,i,-1);
e1190b87 1600 minimum_free_regs[i]=1;
57871462 1601}
1602void float_alloc(struct regstat *current,int i)
1603{
1604 alloc_reg(current,i,CSREG); // Load status
1605 alloc_reg_temp(current,i,-1);
e1190b87 1606 minimum_free_regs[i]=1;
57871462 1607}
b9b61529 1608void c2op_alloc(struct regstat *current,int i)
1609{
1610 alloc_reg_temp(current,i,-1);
1611}
57871462 1612void fcomp_alloc(struct regstat *current,int i)
1613{
1614 alloc_reg(current,i,CSREG); // Load status
1615 alloc_reg(current,i,FSREG); // Load flags
1616 dirty_reg(current,FSREG); // Flag will be modified
1617 alloc_reg_temp(current,i,-1);
e1190b87 1618 minimum_free_regs[i]=1;
57871462 1619}
1620
1621void syscall_alloc(struct regstat *current,int i)
1622{
1623 alloc_cc(current,i);
1624 dirty_reg(current,CCREG);
1625 alloc_all(current,i);
e1190b87 1626 minimum_free_regs[i]=HOST_REGS;
57871462 1627 current->isconst=0;
1628}
1629
1630void delayslot_alloc(struct regstat *current,int i)
1631{
1632 switch(itype[i]) {
1633 case UJUMP:
1634 case CJUMP:
1635 case SJUMP:
1636 case RJUMP:
1637 case FJUMP:
1638 case SYSCALL:
7139f3c8 1639 case HLECALL:
57871462 1640 case SPAN:
1641 assem_debug("jump in the delay slot. this shouldn't happen.\n");//exit(1);
c43b5311 1642 SysPrintf("Disabled speculative precompilation\n");
57871462 1643 stop_after_jal=1;
1644 break;
1645 case IMM16:
1646 imm16_alloc(current,i);
1647 break;
1648 case LOAD:
1649 case LOADLR:
1650 load_alloc(current,i);
1651 break;
1652 case STORE:
1653 case STORELR:
1654 store_alloc(current,i);
1655 break;
1656 case ALU:
1657 alu_alloc(current,i);
1658 break;
1659 case SHIFT:
1660 shift_alloc(current,i);
1661 break;
1662 case MULTDIV:
1663 multdiv_alloc(current,i);
1664 break;
1665 case SHIFTIMM:
1666 shiftimm_alloc(current,i);
1667 break;
1668 case MOV:
1669 mov_alloc(current,i);
1670 break;
1671 case COP0:
1672 cop0_alloc(current,i);
1673 break;
1674 case COP1:
b9b61529 1675 case COP2:
57871462 1676 cop1_alloc(current,i);
1677 break;
1678 case C1LS:
1679 c1ls_alloc(current,i);
1680 break;
b9b61529 1681 case C2LS:
1682 c2ls_alloc(current,i);
1683 break;
57871462 1684 case FCONV:
1685 fconv_alloc(current,i);
1686 break;
1687 case FLOAT:
1688 float_alloc(current,i);
1689 break;
1690 case FCOMP:
1691 fcomp_alloc(current,i);
1692 break;
b9b61529 1693 case C2OP:
1694 c2op_alloc(current,i);
1695 break;
57871462 1696 }
1697}
1698
1699// Special case where a branch and delay slot span two pages in virtual memory
1700static void pagespan_alloc(struct regstat *current,int i)
1701{
1702 current->isconst=0;
1703 current->wasconst=0;
1704 regs[i].wasconst=0;
e1190b87 1705 minimum_free_regs[i]=HOST_REGS;
57871462 1706 alloc_all(current,i);
1707 alloc_cc(current,i);
1708 dirty_reg(current,CCREG);
1709 if(opcode[i]==3) // JAL
1710 {
1711 alloc_reg(current,i,31);
1712 dirty_reg(current,31);
1713 }
1714 if(opcode[i]==0&&(opcode2[i]&0x3E)==8) // JR/JALR
1715 {
1716 alloc_reg(current,i,rs1[i]);
5067f341 1717 if (rt1[i]!=0) {
1718 alloc_reg(current,i,rt1[i]);
1719 dirty_reg(current,rt1[i]);
57871462 1720 }
1721 }
1722 if((opcode[i]&0x2E)==4) // BEQ/BNE/BEQL/BNEL
1723 {
1724 if(rs1[i]) alloc_reg(current,i,rs1[i]);
1725 if(rs2[i]) alloc_reg(current,i,rs2[i]);
1726 if(!((current->is32>>rs1[i])&(current->is32>>rs2[i])&1))
1727 {
1728 if(rs1[i]) alloc_reg64(current,i,rs1[i]);
1729 if(rs2[i]) alloc_reg64(current,i,rs2[i]);
1730 }
1731 }
1732 else
1733 if((opcode[i]&0x2E)==6) // BLEZ/BGTZ/BLEZL/BGTZL
1734 {
1735 if(rs1[i]) alloc_reg(current,i,rs1[i]);
1736 if(!((current->is32>>rs1[i])&1))
1737 {
1738 if(rs1[i]) alloc_reg64(current,i,rs1[i]);
1739 }
1740 }
1741 else
1742 if(opcode[i]==0x11) // BC1
1743 {
1744 alloc_reg(current,i,FSREG);
1745 alloc_reg(current,i,CSREG);
1746 }
1747 //else ...
1748}
1749
1750add_stub(int type,int addr,int retaddr,int a,int b,int c,int d,int e)
1751{
1752 stubs[stubcount][0]=type;
1753 stubs[stubcount][1]=addr;
1754 stubs[stubcount][2]=retaddr;
1755 stubs[stubcount][3]=a;
1756 stubs[stubcount][4]=b;
1757 stubs[stubcount][5]=c;
1758 stubs[stubcount][6]=d;
1759 stubs[stubcount][7]=e;
1760 stubcount++;
1761}
1762
1763// Write out a single register
1764void wb_register(signed char r,signed char regmap[],uint64_t dirty,uint64_t is32)
1765{
1766 int hr;
1767 for(hr=0;hr<HOST_REGS;hr++) {
1768 if(hr!=EXCLUDE_REG) {
1769 if((regmap[hr]&63)==r) {
1770 if((dirty>>hr)&1) {
1771 if(regmap[hr]<64) {
1772 emit_storereg(r,hr);
57871462 1773 }else{
1774 emit_storereg(r|64,hr);
1775 }
1776 }
1777 }
1778 }
1779 }
1780}
1781
1782int mchecksum()
1783{
1784 //if(!tracedebug) return 0;
1785 int i;
1786 int sum=0;
1787 for(i=0;i<2097152;i++) {
1788 unsigned int temp=sum;
1789 sum<<=1;
1790 sum|=(~temp)>>31;
1791 sum^=((u_int *)rdram)[i];
1792 }
1793 return sum;
1794}
1795int rchecksum()
1796{
1797 int i;
1798 int sum=0;
1799 for(i=0;i<64;i++)
1800 sum^=((u_int *)reg)[i];
1801 return sum;
1802}
57871462 1803void rlist()
1804{
1805 int i;
1806 printf("TRACE: ");
1807 for(i=0;i<32;i++)
1808 printf("r%d:%8x%8x ",i,((int *)(reg+i))[1],((int *)(reg+i))[0]);
1809 printf("\n");
57871462 1810}
1811
1812void enabletrace()
1813{
1814 tracedebug=1;
1815}
1816
1817void memdebug(int i)
1818{
1819 //printf("TRACE: count=%d next=%d (checksum %x) lo=%8x%8x\n",Count,next_interupt,mchecksum(),(int)(reg[LOREG]>>32),(int)reg[LOREG]);
1820 //printf("TRACE: count=%d next=%d (rchecksum %x)\n",Count,next_interupt,rchecksum());
1821 //rlist();
1822 //if(tracedebug) {
1823 //if(Count>=-2084597794) {
1824 if((signed int)Count>=-2084597794&&(signed int)Count<0) {
1825 //if(0) {
1826 printf("TRACE: count=%d next=%d (checksum %x)\n",Count,next_interupt,mchecksum());
1827 //printf("TRACE: count=%d next=%d (checksum %x) Status=%x\n",Count,next_interupt,mchecksum(),Status);
1828 //printf("TRACE: count=%d next=%d (checksum %x) hi=%8x%8x\n",Count,next_interupt,mchecksum(),(int)(reg[HIREG]>>32),(int)reg[HIREG]);
1829 rlist();
1830 #ifdef __i386__
1831 printf("TRACE: %x\n",(&i)[-1]);
1832 #endif
1833 #ifdef __arm__
1834 int j;
1835 printf("TRACE: %x \n",(&j)[10]);
1836 printf("TRACE: %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x\n",(&j)[1],(&j)[2],(&j)[3],(&j)[4],(&j)[5],(&j)[6],(&j)[7],(&j)[8],(&j)[9],(&j)[10],(&j)[11],(&j)[12],(&j)[13],(&j)[14],(&j)[15],(&j)[16],(&j)[17],(&j)[18],(&j)[19],(&j)[20]);
1837 #endif
1838 //fflush(stdout);
1839 }
1840 //printf("TRACE: %x\n",(&i)[-1]);
1841}
1842
57871462 1843void alu_assemble(int i,struct regstat *i_regs)
1844{
1845 if(opcode2[i]>=0x20&&opcode2[i]<=0x23) { // ADD/ADDU/SUB/SUBU
1846 if(rt1[i]) {
1847 signed char s1,s2,t;
1848 t=get_reg(i_regs->regmap,rt1[i]);
1849 if(t>=0) {
1850 s1=get_reg(i_regs->regmap,rs1[i]);
1851 s2=get_reg(i_regs->regmap,rs2[i]);
1852 if(rs1[i]&&rs2[i]) {
1853 assert(s1>=0);
1854 assert(s2>=0);
1855 if(opcode2[i]&2) emit_sub(s1,s2,t);
1856 else emit_add(s1,s2,t);
1857 }
1858 else if(rs1[i]) {
1859 if(s1>=0) emit_mov(s1,t);
1860 else emit_loadreg(rs1[i],t);
1861 }
1862 else if(rs2[i]) {
1863 if(s2>=0) {
1864 if(opcode2[i]&2) emit_neg(s2,t);
1865 else emit_mov(s2,t);
1866 }
1867 else {
1868 emit_loadreg(rs2[i],t);
1869 if(opcode2[i]&2) emit_neg(t,t);
1870 }
1871 }
1872 else emit_zeroreg(t);
1873 }
1874 }
1875 }
1876 if(opcode2[i]>=0x2c&&opcode2[i]<=0x2f) { // DADD/DADDU/DSUB/DSUBU
1877 if(rt1[i]) {
1878 signed char s1l,s2l,s1h,s2h,tl,th;
1879 tl=get_reg(i_regs->regmap,rt1[i]);
1880 th=get_reg(i_regs->regmap,rt1[i]|64);
1881 if(tl>=0) {
1882 s1l=get_reg(i_regs->regmap,rs1[i]);
1883 s2l=get_reg(i_regs->regmap,rs2[i]);
1884 s1h=get_reg(i_regs->regmap,rs1[i]|64);
1885 s2h=get_reg(i_regs->regmap,rs2[i]|64);
1886 if(rs1[i]&&rs2[i]) {
1887 assert(s1l>=0);
1888 assert(s2l>=0);
1889 if(opcode2[i]&2) emit_subs(s1l,s2l,tl);
1890 else emit_adds(s1l,s2l,tl);
1891 if(th>=0) {
1892 #ifdef INVERTED_CARRY
1893 if(opcode2[i]&2) {if(s1h!=th) emit_mov(s1h,th);emit_sbb(th,s2h);}
1894 #else
1895 if(opcode2[i]&2) emit_sbc(s1h,s2h,th);
1896 #endif
1897 else emit_add(s1h,s2h,th);
1898 }
1899 }
1900 else if(rs1[i]) {
1901 if(s1l>=0) emit_mov(s1l,tl);
1902 else emit_loadreg(rs1[i],tl);
1903 if(th>=0) {
1904 if(s1h>=0) emit_mov(s1h,th);
1905 else emit_loadreg(rs1[i]|64,th);
1906 }
1907 }
1908 else if(rs2[i]) {
1909 if(s2l>=0) {
1910 if(opcode2[i]&2) emit_negs(s2l,tl);
1911 else emit_mov(s2l,tl);
1912 }
1913 else {
1914 emit_loadreg(rs2[i],tl);
1915 if(opcode2[i]&2) emit_negs(tl,tl);
1916 }
1917 if(th>=0) {
1918 #ifdef INVERTED_CARRY
1919 if(s2h>=0) emit_mov(s2h,th);
1920 else emit_loadreg(rs2[i]|64,th);
1921 if(opcode2[i]&2) {
1922 emit_adcimm(-1,th); // x86 has inverted carry flag
1923 emit_not(th,th);
1924 }
1925 #else
1926 if(opcode2[i]&2) {
1927 if(s2h>=0) emit_rscimm(s2h,0,th);
1928 else {
1929 emit_loadreg(rs2[i]|64,th);
1930 emit_rscimm(th,0,th);
1931 }
1932 }else{
1933 if(s2h>=0) emit_mov(s2h,th);
1934 else emit_loadreg(rs2[i]|64,th);
1935 }
1936 #endif
1937 }
1938 }
1939 else {
1940 emit_zeroreg(tl);
1941 if(th>=0) emit_zeroreg(th);
1942 }
1943 }
1944 }
1945 }
1946 if(opcode2[i]==0x2a||opcode2[i]==0x2b) { // SLT/SLTU
1947 if(rt1[i]) {
1948 signed char s1l,s1h,s2l,s2h,t;
1949 if(!((i_regs->was32>>rs1[i])&(i_regs->was32>>rs2[i])&1))
1950 {
1951 t=get_reg(i_regs->regmap,rt1[i]);
1952 //assert(t>=0);
1953 if(t>=0) {
1954 s1l=get_reg(i_regs->regmap,rs1[i]);
1955 s1h=get_reg(i_regs->regmap,rs1[i]|64);
1956 s2l=get_reg(i_regs->regmap,rs2[i]);
1957 s2h=get_reg(i_regs->regmap,rs2[i]|64);
1958 if(rs2[i]==0) // rx<r0
1959 {
1960 assert(s1h>=0);
1961 if(opcode2[i]==0x2a) // SLT
1962 emit_shrimm(s1h,31,t);
1963 else // SLTU (unsigned can not be less than zero)
1964 emit_zeroreg(t);
1965 }
1966 else if(rs1[i]==0) // r0<rx
1967 {
1968 assert(s2h>=0);
1969 if(opcode2[i]==0x2a) // SLT
1970 emit_set_gz64_32(s2h,s2l,t);
1971 else // SLTU (set if not zero)
1972 emit_set_nz64_32(s2h,s2l,t);
1973 }
1974 else {
1975 assert(s1l>=0);assert(s1h>=0);
1976 assert(s2l>=0);assert(s2h>=0);
1977 if(opcode2[i]==0x2a) // SLT
1978 emit_set_if_less64_32(s1h,s1l,s2h,s2l,t);
1979 else // SLTU
1980 emit_set_if_carry64_32(s1h,s1l,s2h,s2l,t);
1981 }
1982 }
1983 } else {
1984 t=get_reg(i_regs->regmap,rt1[i]);
1985 //assert(t>=0);
1986 if(t>=0) {
1987 s1l=get_reg(i_regs->regmap,rs1[i]);
1988 s2l=get_reg(i_regs->regmap,rs2[i]);
1989 if(rs2[i]==0) // rx<r0
1990 {
1991 assert(s1l>=0);
1992 if(opcode2[i]==0x2a) // SLT
1993 emit_shrimm(s1l,31,t);
1994 else // SLTU (unsigned can not be less than zero)
1995 emit_zeroreg(t);
1996 }
1997 else if(rs1[i]==0) // r0<rx
1998 {
1999 assert(s2l>=0);
2000 if(opcode2[i]==0x2a) // SLT
2001 emit_set_gz32(s2l,t);
2002 else // SLTU (set if not zero)
2003 emit_set_nz32(s2l,t);
2004 }
2005 else{
2006 assert(s1l>=0);assert(s2l>=0);
2007 if(opcode2[i]==0x2a) // SLT
2008 emit_set_if_less32(s1l,s2l,t);
2009 else // SLTU
2010 emit_set_if_carry32(s1l,s2l,t);
2011 }
2012 }
2013 }
2014 }
2015 }
2016 if(opcode2[i]>=0x24&&opcode2[i]<=0x27) { // AND/OR/XOR/NOR
2017 if(rt1[i]) {
2018 signed char s1l,s1h,s2l,s2h,th,tl;
2019 tl=get_reg(i_regs->regmap,rt1[i]);
2020 th=get_reg(i_regs->regmap,rt1[i]|64);
2021 if(!((i_regs->was32>>rs1[i])&(i_regs->was32>>rs2[i])&1)&&th>=0)
2022 {
2023 assert(tl>=0);
2024 if(tl>=0) {
2025 s1l=get_reg(i_regs->regmap,rs1[i]);
2026 s1h=get_reg(i_regs->regmap,rs1[i]|64);
2027 s2l=get_reg(i_regs->regmap,rs2[i]);
2028 s2h=get_reg(i_regs->regmap,rs2[i]|64);
2029 if(rs1[i]&&rs2[i]) {
2030 assert(s1l>=0);assert(s1h>=0);
2031 assert(s2l>=0);assert(s2h>=0);
2032 if(opcode2[i]==0x24) { // AND
2033 emit_and(s1l,s2l,tl);
2034 emit_and(s1h,s2h,th);
2035 } else
2036 if(opcode2[i]==0x25) { // OR
2037 emit_or(s1l,s2l,tl);
2038 emit_or(s1h,s2h,th);
2039 } else
2040 if(opcode2[i]==0x26) { // XOR
2041 emit_xor(s1l,s2l,tl);
2042 emit_xor(s1h,s2h,th);
2043 } else
2044 if(opcode2[i]==0x27) { // NOR
2045 emit_or(s1l,s2l,tl);
2046 emit_or(s1h,s2h,th);
2047 emit_not(tl,tl);
2048 emit_not(th,th);
2049 }
2050 }
2051 else
2052 {
2053 if(opcode2[i]==0x24) { // AND
2054 emit_zeroreg(tl);
2055 emit_zeroreg(th);
2056 } else
2057 if(opcode2[i]==0x25||opcode2[i]==0x26) { // OR/XOR
2058 if(rs1[i]){
2059 if(s1l>=0) emit_mov(s1l,tl);
2060 else emit_loadreg(rs1[i],tl);
2061 if(s1h>=0) emit_mov(s1h,th);
2062 else emit_loadreg(rs1[i]|64,th);
2063 }
2064 else
2065 if(rs2[i]){
2066 if(s2l>=0) emit_mov(s2l,tl);
2067 else emit_loadreg(rs2[i],tl);
2068 if(s2h>=0) emit_mov(s2h,th);
2069 else emit_loadreg(rs2[i]|64,th);
2070 }
2071 else{
2072 emit_zeroreg(tl);
2073 emit_zeroreg(th);
2074 }
2075 } else
2076 if(opcode2[i]==0x27) { // NOR
2077 if(rs1[i]){
2078 if(s1l>=0) emit_not(s1l,tl);
2079 else{
2080 emit_loadreg(rs1[i],tl);
2081 emit_not(tl,tl);
2082 }
2083 if(s1h>=0) emit_not(s1h,th);
2084 else{
2085 emit_loadreg(rs1[i]|64,th);
2086 emit_not(th,th);
2087 }
2088 }
2089 else
2090 if(rs2[i]){
2091 if(s2l>=0) emit_not(s2l,tl);
2092 else{
2093 emit_loadreg(rs2[i],tl);
2094 emit_not(tl,tl);
2095 }
2096 if(s2h>=0) emit_not(s2h,th);
2097 else{
2098 emit_loadreg(rs2[i]|64,th);
2099 emit_not(th,th);
2100 }
2101 }
2102 else {
2103 emit_movimm(-1,tl);
2104 emit_movimm(-1,th);
2105 }
2106 }
2107 }
2108 }
2109 }
2110 else
2111 {
2112 // 32 bit
2113 if(tl>=0) {
2114 s1l=get_reg(i_regs->regmap,rs1[i]);
2115 s2l=get_reg(i_regs->regmap,rs2[i]);
2116 if(rs1[i]&&rs2[i]) {
2117 assert(s1l>=0);
2118 assert(s2l>=0);
2119 if(opcode2[i]==0x24) { // AND
2120 emit_and(s1l,s2l,tl);
2121 } else
2122 if(opcode2[i]==0x25) { // OR
2123 emit_or(s1l,s2l,tl);
2124 } else
2125 if(opcode2[i]==0x26) { // XOR
2126 emit_xor(s1l,s2l,tl);
2127 } else
2128 if(opcode2[i]==0x27) { // NOR
2129 emit_or(s1l,s2l,tl);
2130 emit_not(tl,tl);
2131 }
2132 }
2133 else
2134 {
2135 if(opcode2[i]==0x24) { // AND
2136 emit_zeroreg(tl);
2137 } else
2138 if(opcode2[i]==0x25||opcode2[i]==0x26) { // OR/XOR
2139 if(rs1[i]){
2140 if(s1l>=0) emit_mov(s1l,tl);
2141 else emit_loadreg(rs1[i],tl); // CHECK: regmap_entry?
2142 }
2143 else
2144 if(rs2[i]){
2145 if(s2l>=0) emit_mov(s2l,tl);
2146 else emit_loadreg(rs2[i],tl); // CHECK: regmap_entry?
2147 }
2148 else emit_zeroreg(tl);
2149 } else
2150 if(opcode2[i]==0x27) { // NOR
2151 if(rs1[i]){
2152 if(s1l>=0) emit_not(s1l,tl);
2153 else {
2154 emit_loadreg(rs1[i],tl);
2155 emit_not(tl,tl);
2156 }
2157 }
2158 else
2159 if(rs2[i]){
2160 if(s2l>=0) emit_not(s2l,tl);
2161 else {
2162 emit_loadreg(rs2[i],tl);
2163 emit_not(tl,tl);
2164 }
2165 }
2166 else emit_movimm(-1,tl);
2167 }
2168 }
2169 }
2170 }
2171 }
2172 }
2173}
2174
2175void imm16_assemble(int i,struct regstat *i_regs)
2176{
2177 if (opcode[i]==0x0f) { // LUI
2178 if(rt1[i]) {
2179 signed char t;
2180 t=get_reg(i_regs->regmap,rt1[i]);
2181 //assert(t>=0);
2182 if(t>=0) {
2183 if(!((i_regs->isconst>>t)&1))
2184 emit_movimm(imm[i]<<16,t);
2185 }
2186 }
2187 }
2188 if(opcode[i]==0x08||opcode[i]==0x09) { // ADDI/ADDIU
2189 if(rt1[i]) {
2190 signed char s,t;
2191 t=get_reg(i_regs->regmap,rt1[i]);
2192 s=get_reg(i_regs->regmap,rs1[i]);
2193 if(rs1[i]) {
2194 //assert(t>=0);
2195 //assert(s>=0);
2196 if(t>=0) {
2197 if(!((i_regs->isconst>>t)&1)) {
2198 if(s<0) {
2199 if(i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2200 emit_addimm(t,imm[i],t);
2201 }else{
2202 if(!((i_regs->wasconst>>s)&1))
2203 emit_addimm(s,imm[i],t);
2204 else
2205 emit_movimm(constmap[i][s]+imm[i],t);
2206 }
2207 }
2208 }
2209 } else {
2210 if(t>=0) {
2211 if(!((i_regs->isconst>>t)&1))
2212 emit_movimm(imm[i],t);
2213 }
2214 }
2215 }
2216 }
2217 if(opcode[i]==0x18||opcode[i]==0x19) { // DADDI/DADDIU
2218 if(rt1[i]) {
2219 signed char sh,sl,th,tl;
2220 th=get_reg(i_regs->regmap,rt1[i]|64);
2221 tl=get_reg(i_regs->regmap,rt1[i]);
2222 sh=get_reg(i_regs->regmap,rs1[i]|64);
2223 sl=get_reg(i_regs->regmap,rs1[i]);
2224 if(tl>=0) {
2225 if(rs1[i]) {
2226 assert(sh>=0);
2227 assert(sl>=0);
2228 if(th>=0) {
2229 emit_addimm64_32(sh,sl,imm[i],th,tl);
2230 }
2231 else {
2232 emit_addimm(sl,imm[i],tl);
2233 }
2234 } else {
2235 emit_movimm(imm[i],tl);
2236 if(th>=0) emit_movimm(((signed int)imm[i])>>31,th);
2237 }
2238 }
2239 }
2240 }
2241 else if(opcode[i]==0x0a||opcode[i]==0x0b) { // SLTI/SLTIU
2242 if(rt1[i]) {
2243 //assert(rs1[i]!=0); // r0 might be valid, but it's probably a bug
2244 signed char sh,sl,t;
2245 t=get_reg(i_regs->regmap,rt1[i]);
2246 sh=get_reg(i_regs->regmap,rs1[i]|64);
2247 sl=get_reg(i_regs->regmap,rs1[i]);
2248 //assert(t>=0);
2249 if(t>=0) {
2250 if(rs1[i]>0) {
2251 if(sh<0) assert((i_regs->was32>>rs1[i])&1);
2252 if(sh<0||((i_regs->was32>>rs1[i])&1)) {
2253 if(opcode[i]==0x0a) { // SLTI
2254 if(sl<0) {
2255 if(i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2256 emit_slti32(t,imm[i],t);
2257 }else{
2258 emit_slti32(sl,imm[i],t);
2259 }
2260 }
2261 else { // SLTIU
2262 if(sl<0) {
2263 if(i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2264 emit_sltiu32(t,imm[i],t);
2265 }else{
2266 emit_sltiu32(sl,imm[i],t);
2267 }
2268 }
2269 }else{ // 64-bit
2270 assert(sl>=0);
2271 if(opcode[i]==0x0a) // SLTI
2272 emit_slti64_32(sh,sl,imm[i],t);
2273 else // SLTIU
2274 emit_sltiu64_32(sh,sl,imm[i],t);
2275 }
2276 }else{
2277 // SLTI(U) with r0 is just stupid,
2278 // nonetheless examples can be found
2279 if(opcode[i]==0x0a) // SLTI
2280 if(0<imm[i]) emit_movimm(1,t);
2281 else emit_zeroreg(t);
2282 else // SLTIU
2283 {
2284 if(imm[i]) emit_movimm(1,t);
2285 else emit_zeroreg(t);
2286 }
2287 }
2288 }
2289 }
2290 }
2291 else if(opcode[i]>=0x0c&&opcode[i]<=0x0e) { // ANDI/ORI/XORI
2292 if(rt1[i]) {
2293 signed char sh,sl,th,tl;
2294 th=get_reg(i_regs->regmap,rt1[i]|64);
2295 tl=get_reg(i_regs->regmap,rt1[i]);
2296 sh=get_reg(i_regs->regmap,rs1[i]|64);
2297 sl=get_reg(i_regs->regmap,rs1[i]);
2298 if(tl>=0 && !((i_regs->isconst>>tl)&1)) {
2299 if(opcode[i]==0x0c) //ANDI
2300 {
2301 if(rs1[i]) {
2302 if(sl<0) {
2303 if(i_regs->regmap_entry[tl]!=rs1[i]) emit_loadreg(rs1[i],tl);
2304 emit_andimm(tl,imm[i],tl);
2305 }else{
2306 if(!((i_regs->wasconst>>sl)&1))
2307 emit_andimm(sl,imm[i],tl);
2308 else
2309 emit_movimm(constmap[i][sl]&imm[i],tl);
2310 }
2311 }
2312 else
2313 emit_zeroreg(tl);
2314 if(th>=0) emit_zeroreg(th);
2315 }
2316 else
2317 {
2318 if(rs1[i]) {
2319 if(sl<0) {
2320 if(i_regs->regmap_entry[tl]!=rs1[i]) emit_loadreg(rs1[i],tl);
2321 }
2322 if(th>=0) {
2323 if(sh<0) {
2324 emit_loadreg(rs1[i]|64,th);
2325 }else{
2326 emit_mov(sh,th);
2327 }
2328 }
2329 if(opcode[i]==0x0d) //ORI
2330 if(sl<0) {
2331 emit_orimm(tl,imm[i],tl);
2332 }else{
2333 if(!((i_regs->wasconst>>sl)&1))
2334 emit_orimm(sl,imm[i],tl);
2335 else
2336 emit_movimm(constmap[i][sl]|imm[i],tl);
2337 }
2338 if(opcode[i]==0x0e) //XORI
2339 if(sl<0) {
2340 emit_xorimm(tl,imm[i],tl);
2341 }else{
2342 if(!((i_regs->wasconst>>sl)&1))
2343 emit_xorimm(sl,imm[i],tl);
2344 else
2345 emit_movimm(constmap[i][sl]^imm[i],tl);
2346 }
2347 }
2348 else {
2349 emit_movimm(imm[i],tl);
2350 if(th>=0) emit_zeroreg(th);
2351 }
2352 }
2353 }
2354 }
2355 }
2356}
2357
2358void shiftimm_assemble(int i,struct regstat *i_regs)
2359{
2360 if(opcode2[i]<=0x3) // SLL/SRL/SRA
2361 {
2362 if(rt1[i]) {
2363 signed char s,t;
2364 t=get_reg(i_regs->regmap,rt1[i]);
2365 s=get_reg(i_regs->regmap,rs1[i]);
2366 //assert(t>=0);
dc49e339 2367 if(t>=0&&!((i_regs->isconst>>t)&1)){
57871462 2368 if(rs1[i]==0)
2369 {
2370 emit_zeroreg(t);
2371 }
2372 else
2373 {
2374 if(s<0&&i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2375 if(imm[i]) {
2376 if(opcode2[i]==0) // SLL
2377 {
2378 emit_shlimm(s<0?t:s,imm[i],t);
2379 }
2380 if(opcode2[i]==2) // SRL
2381 {
2382 emit_shrimm(s<0?t:s,imm[i],t);
2383 }
2384 if(opcode2[i]==3) // SRA
2385 {
2386 emit_sarimm(s<0?t:s,imm[i],t);
2387 }
2388 }else{
2389 // Shift by zero
2390 if(s>=0 && s!=t) emit_mov(s,t);
2391 }
2392 }
2393 }
2394 //emit_storereg(rt1[i],t); //DEBUG
2395 }
2396 }
2397 if(opcode2[i]>=0x38&&opcode2[i]<=0x3b) // DSLL/DSRL/DSRA
2398 {
2399 if(rt1[i]) {
2400 signed char sh,sl,th,tl;
2401 th=get_reg(i_regs->regmap,rt1[i]|64);
2402 tl=get_reg(i_regs->regmap,rt1[i]);
2403 sh=get_reg(i_regs->regmap,rs1[i]|64);
2404 sl=get_reg(i_regs->regmap,rs1[i]);
2405 if(tl>=0) {
2406 if(rs1[i]==0)
2407 {
2408 emit_zeroreg(tl);
2409 if(th>=0) emit_zeroreg(th);
2410 }
2411 else
2412 {
2413 assert(sl>=0);
2414 assert(sh>=0);
2415 if(imm[i]) {
2416 if(opcode2[i]==0x38) // DSLL
2417 {
2418 if(th>=0) emit_shldimm(sh,sl,imm[i],th);
2419 emit_shlimm(sl,imm[i],tl);
2420 }
2421 if(opcode2[i]==0x3a) // DSRL
2422 {
2423 emit_shrdimm(sl,sh,imm[i],tl);
2424 if(th>=0) emit_shrimm(sh,imm[i],th);
2425 }
2426 if(opcode2[i]==0x3b) // DSRA
2427 {
2428 emit_shrdimm(sl,sh,imm[i],tl);
2429 if(th>=0) emit_sarimm(sh,imm[i],th);
2430 }
2431 }else{
2432 // Shift by zero
2433 if(sl!=tl) emit_mov(sl,tl);
2434 if(th>=0&&sh!=th) emit_mov(sh,th);
2435 }
2436 }
2437 }
2438 }
2439 }
2440 if(opcode2[i]==0x3c) // DSLL32
2441 {
2442 if(rt1[i]) {
2443 signed char sl,tl,th;
2444 tl=get_reg(i_regs->regmap,rt1[i]);
2445 th=get_reg(i_regs->regmap,rt1[i]|64);
2446 sl=get_reg(i_regs->regmap,rs1[i]);
2447 if(th>=0||tl>=0){
2448 assert(tl>=0);
2449 assert(th>=0);
2450 assert(sl>=0);
2451 emit_mov(sl,th);
2452 emit_zeroreg(tl);
2453 if(imm[i]>32)
2454 {
2455 emit_shlimm(th,imm[i]&31,th);
2456 }
2457 }
2458 }
2459 }
2460 if(opcode2[i]==0x3e) // DSRL32
2461 {
2462 if(rt1[i]) {
2463 signed char sh,tl,th;
2464 tl=get_reg(i_regs->regmap,rt1[i]);
2465 th=get_reg(i_regs->regmap,rt1[i]|64);
2466 sh=get_reg(i_regs->regmap,rs1[i]|64);
2467 if(tl>=0){
2468 assert(sh>=0);
2469 emit_mov(sh,tl);
2470 if(th>=0) emit_zeroreg(th);
2471 if(imm[i]>32)
2472 {
2473 emit_shrimm(tl,imm[i]&31,tl);
2474 }
2475 }
2476 }
2477 }
2478 if(opcode2[i]==0x3f) // DSRA32
2479 {
2480 if(rt1[i]) {
2481 signed char sh,tl;
2482 tl=get_reg(i_regs->regmap,rt1[i]);
2483 sh=get_reg(i_regs->regmap,rs1[i]|64);
2484 if(tl>=0){
2485 assert(sh>=0);
2486 emit_mov(sh,tl);
2487 if(imm[i]>32)
2488 {
2489 emit_sarimm(tl,imm[i]&31,tl);
2490 }
2491 }
2492 }
2493 }
2494}
2495
2496#ifndef shift_assemble
2497void shift_assemble(int i,struct regstat *i_regs)
2498{
2499 printf("Need shift_assemble for this architecture.\n");
2500 exit(1);
2501}
2502#endif
2503
2504void load_assemble(int i,struct regstat *i_regs)
2505{
2506 int s,th,tl,addr,map=-1;
2507 int offset;
2508 int jaddr=0;
5bf843dc 2509 int memtarget=0,c=0;
b1570849 2510 int fastload_reg_override=0;
57871462 2511 u_int hr,reglist=0;
2512 th=get_reg(i_regs->regmap,rt1[i]|64);
2513 tl=get_reg(i_regs->regmap,rt1[i]);
2514 s=get_reg(i_regs->regmap,rs1[i]);
2515 offset=imm[i];
2516 for(hr=0;hr<HOST_REGS;hr++) {
2517 if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
2518 }
2519 if(i_regs->regmap[HOST_CCREG]==CCREG) reglist&=~(1<<HOST_CCREG);
2520 if(s>=0) {
2521 c=(i_regs->wasconst>>s)&1;
af4ee1fe 2522 if (c) {
2523 memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
af4ee1fe 2524 }
57871462 2525 }
57871462 2526 //printf("load_assemble: c=%d\n",c);
2527 //if(c) printf("load_assemble: const=%x\n",(int)constmap[i][s]+offset);
2528 // FIXME: Even if the load is a NOP, we should check for pagefaults...
f18c0f46 2529 if(tl<0&&(!c||(((u_int)constmap[i][s]+offset)>>16)==0x1f80)
2530 ||rt1[i]==0) {
5bf843dc 2531 // could be FIFO, must perform the read
f18c0f46 2532 // ||dummy read
5bf843dc 2533 assem_debug("(forced read)\n");
2534 tl=get_reg(i_regs->regmap,-1);
2535 assert(tl>=0);
5bf843dc 2536 }
2537 if(offset||s<0||c) addr=tl;
2538 else addr=s;
535d208a 2539 //if(tl<0) tl=get_reg(i_regs->regmap,-1);
2540 if(tl>=0) {
2541 //printf("load_assemble: c=%d\n",c);
2542 //if(c) printf("load_assemble: const=%x\n",(int)constmap[i][s]+offset);
2543 assert(tl>=0); // Even if the load is a NOP, we must check for pagefaults and I/O
2544 reglist&=~(1<<tl);
2545 if(th>=0) reglist&=~(1<<th);
1edfcc68 2546 if(!c) {
2547 #ifdef RAM_OFFSET
2548 map=get_reg(i_regs->regmap,ROREG);
2549 if(map<0) emit_loadreg(ROREG,map=HOST_TEMPREG);
2550 #endif
2551 #ifdef R29_HACK
2552 // Strmnnrmn's speed hack
2553 if(rs1[i]!=29||start<0x80001000||start>=0x80000000+RAM_SIZE)
2554 #endif
2555 {
2556 jaddr=emit_fastpath_cmp_jump(i,addr,&fastload_reg_override);
535d208a 2557 }
1edfcc68 2558 }
2559 else if(ram_offset&&memtarget) {
2560 emit_addimm(addr,ram_offset,HOST_TEMPREG);
2561 fastload_reg_override=HOST_TEMPREG;
535d208a 2562 }
2563 int dummy=(rt1[i]==0)||(tl!=get_reg(i_regs->regmap,rt1[i])); // ignore loads to r0 and unneeded reg
2564 if (opcode[i]==0x20) { // LB
2565 if(!c||memtarget) {
2566 if(!dummy) {
57871462 2567 #ifdef HOST_IMM_ADDR32
2568 if(c)
2569 emit_movsbl_tlb((constmap[i][s]+offset)^3,map,tl);
2570 else
2571 #endif
2572 {
2573 //emit_xorimm(addr,3,tl);
57871462 2574 //emit_movsbl_indexed((int)rdram-0x80000000,tl,tl);
535d208a 2575 int x=0,a=tl;
2002a1db 2576#ifdef BIG_ENDIAN_MIPS
57871462 2577 if(!c) emit_xorimm(addr,3,tl);
2578 else x=((constmap[i][s]+offset)^3)-(constmap[i][s]+offset);
2002a1db 2579#else
535d208a 2580 if(!c) a=addr;
dadf55f2 2581#endif
b1570849 2582 if(fastload_reg_override) a=fastload_reg_override;
2583
535d208a 2584 emit_movsbl_indexed_tlb(x,a,map,tl);
57871462 2585 }
57871462 2586 }
535d208a 2587 if(jaddr)
2588 add_stub(LOADB_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
57871462 2589 }
535d208a 2590 else
2591 inline_readstub(LOADB_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2592 }
2593 if (opcode[i]==0x21) { // LH
2594 if(!c||memtarget) {
2595 if(!dummy) {
57871462 2596 #ifdef HOST_IMM_ADDR32
2597 if(c)
2598 emit_movswl_tlb((constmap[i][s]+offset)^2,map,tl);
2599 else
2600 #endif
2601 {
535d208a 2602 int x=0,a=tl;
2002a1db 2603#ifdef BIG_ENDIAN_MIPS
57871462 2604 if(!c) emit_xorimm(addr,2,tl);
2605 else x=((constmap[i][s]+offset)^2)-(constmap[i][s]+offset);
2002a1db 2606#else
535d208a 2607 if(!c) a=addr;
dadf55f2 2608#endif
b1570849 2609 if(fastload_reg_override) a=fastload_reg_override;
57871462 2610 //#ifdef
2611 //emit_movswl_indexed_tlb(x,tl,map,tl);
2612 //else
2613 if(map>=0) {
535d208a 2614 emit_movswl_indexed(x,a,tl);
2615 }else{
a327ad27 2616 #if 1 //def RAM_OFFSET
535d208a 2617 emit_movswl_indexed(x,a,tl);
2618 #else
2619 emit_movswl_indexed((int)rdram-0x80000000+x,a,tl);
2620 #endif
2621 }
57871462 2622 }
57871462 2623 }
535d208a 2624 if(jaddr)
2625 add_stub(LOADH_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
57871462 2626 }
535d208a 2627 else
2628 inline_readstub(LOADH_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2629 }
2630 if (opcode[i]==0x23) { // LW
2631 if(!c||memtarget) {
2632 if(!dummy) {
dadf55f2 2633 int a=addr;
b1570849 2634 if(fastload_reg_override) a=fastload_reg_override;
57871462 2635 //emit_readword_indexed((int)rdram-0x80000000,addr,tl);
2636 #ifdef HOST_IMM_ADDR32
2637 if(c)
2638 emit_readword_tlb(constmap[i][s]+offset,map,tl);
2639 else
2640 #endif
dadf55f2 2641 emit_readword_indexed_tlb(0,a,map,tl);
57871462 2642 }
535d208a 2643 if(jaddr)
2644 add_stub(LOADW_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
57871462 2645 }
535d208a 2646 else
2647 inline_readstub(LOADW_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2648 }
2649 if (opcode[i]==0x24) { // LBU
2650 if(!c||memtarget) {
2651 if(!dummy) {
57871462 2652 #ifdef HOST_IMM_ADDR32
2653 if(c)
2654 emit_movzbl_tlb((constmap[i][s]+offset)^3,map,tl);
2655 else
2656 #endif
2657 {
2658 //emit_xorimm(addr,3,tl);
57871462 2659 //emit_movzbl_indexed((int)rdram-0x80000000,tl,tl);
535d208a 2660 int x=0,a=tl;
2002a1db 2661#ifdef BIG_ENDIAN_MIPS
57871462 2662 if(!c) emit_xorimm(addr,3,tl);
2663 else x=((constmap[i][s]+offset)^3)-(constmap[i][s]+offset);
2002a1db 2664#else
535d208a 2665 if(!c) a=addr;
dadf55f2 2666#endif
b1570849 2667 if(fastload_reg_override) a=fastload_reg_override;
2668
535d208a 2669 emit_movzbl_indexed_tlb(x,a,map,tl);
57871462 2670 }
57871462 2671 }
535d208a 2672 if(jaddr)
2673 add_stub(LOADBU_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
57871462 2674 }
535d208a 2675 else
2676 inline_readstub(LOADBU_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2677 }
2678 if (opcode[i]==0x25) { // LHU
2679 if(!c||memtarget) {
2680 if(!dummy) {
57871462 2681 #ifdef HOST_IMM_ADDR32
2682 if(c)
2683 emit_movzwl_tlb((constmap[i][s]+offset)^2,map,tl);
2684 else
2685 #endif
2686 {
535d208a 2687 int x=0,a=tl;
2002a1db 2688#ifdef BIG_ENDIAN_MIPS
57871462 2689 if(!c) emit_xorimm(addr,2,tl);
2690 else x=((constmap[i][s]+offset)^2)-(constmap[i][s]+offset);
2002a1db 2691#else
535d208a 2692 if(!c) a=addr;
dadf55f2 2693#endif
b1570849 2694 if(fastload_reg_override) a=fastload_reg_override;
57871462 2695 //#ifdef
2696 //emit_movzwl_indexed_tlb(x,tl,map,tl);
2697 //#else
2698 if(map>=0) {
535d208a 2699 emit_movzwl_indexed(x,a,tl);
2700 }else{
a327ad27 2701 #if 1 //def RAM_OFFSET
535d208a 2702 emit_movzwl_indexed(x,a,tl);
2703 #else
2704 emit_movzwl_indexed((int)rdram-0x80000000+x,a,tl);
2705 #endif
2706 }
57871462 2707 }
2708 }
535d208a 2709 if(jaddr)
2710 add_stub(LOADHU_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
57871462 2711 }
535d208a 2712 else
2713 inline_readstub(LOADHU_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2714 }
2715 if (opcode[i]==0x27) { // LWU
2716 assert(th>=0);
2717 if(!c||memtarget) {
2718 if(!dummy) {
dadf55f2 2719 int a=addr;
b1570849 2720 if(fastload_reg_override) a=fastload_reg_override;
57871462 2721 //emit_readword_indexed((int)rdram-0x80000000,addr,tl);
2722 #ifdef HOST_IMM_ADDR32
2723 if(c)
2724 emit_readword_tlb(constmap[i][s]+offset,map,tl);
2725 else
2726 #endif
dadf55f2 2727 emit_readword_indexed_tlb(0,a,map,tl);
57871462 2728 }
535d208a 2729 if(jaddr)
2730 add_stub(LOADW_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
2731 }
2732 else {
2733 inline_readstub(LOADW_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
57871462 2734 }
535d208a 2735 emit_zeroreg(th);
2736 }
2737 if (opcode[i]==0x37) { // LD
2738 if(!c||memtarget) {
2739 if(!dummy) {
dadf55f2 2740 int a=addr;
b1570849 2741 if(fastload_reg_override) a=fastload_reg_override;
57871462 2742 //if(th>=0) emit_readword_indexed((int)rdram-0x80000000,addr,th);
2743 //emit_readword_indexed((int)rdram-0x7FFFFFFC,addr,tl);
2744 #ifdef HOST_IMM_ADDR32
2745 if(c)
2746 emit_readdword_tlb(constmap[i][s]+offset,map,th,tl);
2747 else
2748 #endif
dadf55f2 2749 emit_readdword_indexed_tlb(0,a,map,th,tl);
57871462 2750 }
535d208a 2751 if(jaddr)
2752 add_stub(LOADD_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
57871462 2753 }
535d208a 2754 else
2755 inline_readstub(LOADD_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
57871462 2756 }
535d208a 2757 }
2758 //emit_storereg(rt1[i],tl); // DEBUG
57871462 2759 //if(opcode[i]==0x23)
2760 //if(opcode[i]==0x24)
2761 //if(opcode[i]==0x23||opcode[i]==0x24)
2762 /*if(opcode[i]==0x21||opcode[i]==0x23||opcode[i]==0x24)
2763 {
2764 //emit_pusha();
2765 save_regs(0x100f);
2766 emit_readword((int)&last_count,ECX);
2767 #ifdef __i386__
2768 if(get_reg(i_regs->regmap,CCREG)<0)
2769 emit_loadreg(CCREG,HOST_CCREG);
2770 emit_add(HOST_CCREG,ECX,HOST_CCREG);
2771 emit_addimm(HOST_CCREG,2*ccadj[i],HOST_CCREG);
2772 emit_writeword(HOST_CCREG,(int)&Count);
2773 #endif
2774 #ifdef __arm__
2775 if(get_reg(i_regs->regmap,CCREG)<0)
2776 emit_loadreg(CCREG,0);
2777 else
2778 emit_mov(HOST_CCREG,0);
2779 emit_add(0,ECX,0);
2780 emit_addimm(0,2*ccadj[i],0);
2781 emit_writeword(0,(int)&Count);
2782 #endif
2783 emit_call((int)memdebug);
2784 //emit_popa();
2785 restore_regs(0x100f);
2786 }/**/
2787}
2788
2789#ifndef loadlr_assemble
2790void loadlr_assemble(int i,struct regstat *i_regs)
2791{
2792 printf("Need loadlr_assemble for this architecture.\n");
2793 exit(1);
2794}
2795#endif
2796
2797void store_assemble(int i,struct regstat *i_regs)
2798{
2799 int s,th,tl,map=-1;
2800 int addr,temp;
2801 int offset;
2802 int jaddr=0,jaddr2,type;
666a299d 2803 int memtarget=0,c=0;
57871462 2804 int agr=AGEN1+(i&1);
b1570849 2805 int faststore_reg_override=0;
57871462 2806 u_int hr,reglist=0;
2807 th=get_reg(i_regs->regmap,rs2[i]|64);
2808 tl=get_reg(i_regs->regmap,rs2[i]);
2809 s=get_reg(i_regs->regmap,rs1[i]);
2810 temp=get_reg(i_regs->regmap,agr);
2811 if(temp<0) temp=get_reg(i_regs->regmap,-1);
2812 offset=imm[i];
2813 if(s>=0) {
2814 c=(i_regs->wasconst>>s)&1;
af4ee1fe 2815 if(c) {
2816 memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
af4ee1fe 2817 }
57871462 2818 }
2819 assert(tl>=0);
2820 assert(temp>=0);
2821 for(hr=0;hr<HOST_REGS;hr++) {
2822 if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
2823 }
2824 if(i_regs->regmap[HOST_CCREG]==CCREG) reglist&=~(1<<HOST_CCREG);
2825 if(offset||s<0||c) addr=temp;
2826 else addr=s;
1edfcc68 2827 if(!c) {
2828 jaddr=emit_fastpath_cmp_jump(i,addr,&faststore_reg_override);
2829 }
2830 else if(ram_offset&&memtarget) {
2831 emit_addimm(addr,ram_offset,HOST_TEMPREG);
2832 faststore_reg_override=HOST_TEMPREG;
57871462 2833 }
2834
2835 if (opcode[i]==0x28) { // SB
2836 if(!c||memtarget) {
97a238a6 2837 int x=0,a=temp;
2002a1db 2838#ifdef BIG_ENDIAN_MIPS
57871462 2839 if(!c) emit_xorimm(addr,3,temp);
2840 else x=((constmap[i][s]+offset)^3)-(constmap[i][s]+offset);
2002a1db 2841#else
97a238a6 2842 if(!c) a=addr;
dadf55f2 2843#endif
b1570849 2844 if(faststore_reg_override) a=faststore_reg_override;
57871462 2845 //emit_writebyte_indexed(tl,(int)rdram-0x80000000,temp);
97a238a6 2846 emit_writebyte_indexed_tlb(tl,x,a,map,a);
57871462 2847 }
2848 type=STOREB_STUB;
2849 }
2850 if (opcode[i]==0x29) { // SH
2851 if(!c||memtarget) {
97a238a6 2852 int x=0,a=temp;
2002a1db 2853#ifdef BIG_ENDIAN_MIPS
57871462 2854 if(!c) emit_xorimm(addr,2,temp);
2855 else x=((constmap[i][s]+offset)^2)-(constmap[i][s]+offset);
2002a1db 2856#else
97a238a6 2857 if(!c) a=addr;
dadf55f2 2858#endif
b1570849 2859 if(faststore_reg_override) a=faststore_reg_override;
57871462 2860 //#ifdef
2861 //emit_writehword_indexed_tlb(tl,x,temp,map,temp);
2862 //#else
2863 if(map>=0) {
97a238a6 2864 emit_writehword_indexed(tl,x,a);
57871462 2865 }else
a327ad27 2866 //emit_writehword_indexed(tl,(int)rdram-0x80000000+x,a);
2867 emit_writehword_indexed(tl,x,a);
57871462 2868 }
2869 type=STOREH_STUB;
2870 }
2871 if (opcode[i]==0x2B) { // SW
dadf55f2 2872 if(!c||memtarget) {
2873 int a=addr;
b1570849 2874 if(faststore_reg_override) a=faststore_reg_override;
57871462 2875 //emit_writeword_indexed(tl,(int)rdram-0x80000000,addr);
dadf55f2 2876 emit_writeword_indexed_tlb(tl,0,a,map,temp);
2877 }
57871462 2878 type=STOREW_STUB;
2879 }
2880 if (opcode[i]==0x3F) { // SD
2881 if(!c||memtarget) {
dadf55f2 2882 int a=addr;
b1570849 2883 if(faststore_reg_override) a=faststore_reg_override;
57871462 2884 if(rs2[i]) {
2885 assert(th>=0);
2886 //emit_writeword_indexed(th,(int)rdram-0x80000000,addr);
2887 //emit_writeword_indexed(tl,(int)rdram-0x7FFFFFFC,addr);
dadf55f2 2888 emit_writedword_indexed_tlb(th,tl,0,a,map,temp);
57871462 2889 }else{
2890 // Store zero
2891 //emit_writeword_indexed(tl,(int)rdram-0x80000000,temp);
2892 //emit_writeword_indexed(tl,(int)rdram-0x7FFFFFFC,temp);
dadf55f2 2893 emit_writedword_indexed_tlb(tl,tl,0,a,map,temp);
57871462 2894 }
2895 }
2896 type=STORED_STUB;
2897 }
b96d3df7 2898 if(jaddr) {
2899 // PCSX store handlers don't check invcode again
2900 reglist|=1<<addr;
2901 add_stub(type,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
2902 jaddr=0;
2903 }
1edfcc68 2904 if(!(i_regs->waswritten&(1<<rs1[i]))&&!(new_dynarec_hacks&NDHACK_NO_SMC_CHECK)) {
57871462 2905 if(!c||memtarget) {
2906 #ifdef DESTRUCTIVE_SHIFT
2907 // The x86 shift operation is 'destructive'; it overwrites the
2908 // source register, so we need to make a copy first and use that.
2909 addr=temp;
2910 #endif
2911 #if defined(HOST_IMM8)
2912 int ir=get_reg(i_regs->regmap,INVCP);
2913 assert(ir>=0);
2914 emit_cmpmem_indexedsr12_reg(ir,addr,1);
2915 #else
2916 emit_cmpmem_indexedsr12_imm((int)invalid_code,addr,1);
2917 #endif
0bbd1454 2918 #if defined(HAVE_CONDITIONAL_CALL) && !defined(DESTRUCTIVE_SHIFT)
2919 emit_callne(invalidate_addr_reg[addr]);
2920 #else
57871462 2921 jaddr2=(int)out;
2922 emit_jne(0);
2923 add_stub(INVCODE_STUB,jaddr2,(int)out,reglist|(1<<HOST_CCREG),addr,0,0,0);
0bbd1454 2924 #endif
57871462 2925 }
2926 }
7a518516 2927 u_int addr_val=constmap[i][s]+offset;
3eaa7048 2928 if(jaddr) {
2929 add_stub(type,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
2930 } else if(c&&!memtarget) {
7a518516 2931 inline_writestub(type,i,addr_val,i_regs->regmap,rs2[i],ccadj[i],reglist);
2932 }
2933 // basic current block modification detection..
2934 // not looking back as that should be in mips cache already
2935 if(c&&start+i*4<addr_val&&addr_val<start+slen*4) {
c43b5311 2936 SysPrintf("write to %08x hits block %08x, pc=%08x\n",addr_val,start,start+i*4);
7a518516 2937 assert(i_regs->regmap==regs[i].regmap); // not delay slot
2938 if(i_regs->regmap==regs[i].regmap) {
2939 load_all_consts(regs[i].regmap_entry,regs[i].was32,regs[i].wasdirty,i);
2940 wb_dirtys(regs[i].regmap_entry,regs[i].was32,regs[i].wasdirty);
2941 emit_movimm(start+i*4+4,0);
2942 emit_writeword(0,(int)&pcaddr);
2943 emit_jmp((int)do_interrupt);
2944 }
3eaa7048 2945 }
57871462 2946 //if(opcode[i]==0x2B || opcode[i]==0x3F)
2947 //if(opcode[i]==0x2B || opcode[i]==0x28)
2948 //if(opcode[i]==0x2B || opcode[i]==0x29)
2949 //if(opcode[i]==0x2B)
2950 /*if(opcode[i]==0x2B || opcode[i]==0x28 || opcode[i]==0x29 || opcode[i]==0x3F)
2951 {
28d74ee8 2952 #ifdef __i386__
2953 emit_pusha();
2954 #endif
2955 #ifdef __arm__
57871462 2956 save_regs(0x100f);
28d74ee8 2957 #endif
57871462 2958 emit_readword((int)&last_count,ECX);
2959 #ifdef __i386__
2960 if(get_reg(i_regs->regmap,CCREG)<0)
2961 emit_loadreg(CCREG,HOST_CCREG);
2962 emit_add(HOST_CCREG,ECX,HOST_CCREG);
2963 emit_addimm(HOST_CCREG,2*ccadj[i],HOST_CCREG);
2964 emit_writeword(HOST_CCREG,(int)&Count);
2965 #endif
2966 #ifdef __arm__
2967 if(get_reg(i_regs->regmap,CCREG)<0)
2968 emit_loadreg(CCREG,0);
2969 else
2970 emit_mov(HOST_CCREG,0);
2971 emit_add(0,ECX,0);
2972 emit_addimm(0,2*ccadj[i],0);
2973 emit_writeword(0,(int)&Count);
2974 #endif
2975 emit_call((int)memdebug);
28d74ee8 2976 #ifdef __i386__
2977 emit_popa();
2978 #endif
2979 #ifdef __arm__
57871462 2980 restore_regs(0x100f);
28d74ee8 2981 #endif
57871462 2982 }/**/
2983}
2984
2985void storelr_assemble(int i,struct regstat *i_regs)
2986{
2987 int s,th,tl;
2988 int temp;
2989 int temp2;
2990 int offset;
2991 int jaddr=0,jaddr2;
2992 int case1,case2,case3;
2993 int done0,done1,done2;
af4ee1fe 2994 int memtarget=0,c=0;
fab5d06d 2995 int agr=AGEN1+(i&1);
57871462 2996 u_int hr,reglist=0;
2997 th=get_reg(i_regs->regmap,rs2[i]|64);
2998 tl=get_reg(i_regs->regmap,rs2[i]);
2999 s=get_reg(i_regs->regmap,rs1[i]);
fab5d06d 3000 temp=get_reg(i_regs->regmap,agr);
3001 if(temp<0) temp=get_reg(i_regs->regmap,-1);
57871462 3002 offset=imm[i];
3003 if(s>=0) {
3004 c=(i_regs->isconst>>s)&1;
af4ee1fe 3005 if(c) {
3006 memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
af4ee1fe 3007 }
57871462 3008 }
3009 assert(tl>=0);
3010 for(hr=0;hr<HOST_REGS;hr++) {
3011 if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
3012 }
535d208a 3013 assert(temp>=0);
1edfcc68 3014 if(!c) {
3015 emit_cmpimm(s<0||offset?temp:s,RAM_SIZE);
3016 if(!offset&&s!=temp) emit_mov(s,temp);
3017 jaddr=(int)out;
3018 emit_jno(0);
3019 }
3020 else
3021 {
3022 if(!memtarget||!rs1[i]) {
535d208a 3023 jaddr=(int)out;
3024 emit_jmp(0);
57871462 3025 }
535d208a 3026 }
1edfcc68 3027 #ifdef RAM_OFFSET
3028 int map=get_reg(i_regs->regmap,ROREG);
3029 if(map<0) emit_loadreg(ROREG,map=HOST_TEMPREG);
3030 #else
9f51b4b9 3031 if((u_int)rdram!=0x80000000)
1edfcc68 3032 emit_addimm_no_flags((u_int)rdram-(u_int)0x80000000,temp);
3033 #endif
535d208a 3034
3035 if (opcode[i]==0x2C||opcode[i]==0x2D) { // SDL/SDR
3036 temp2=get_reg(i_regs->regmap,FTEMP);
3037 if(!rs2[i]) temp2=th=tl;
3038 }
57871462 3039
2002a1db 3040#ifndef BIG_ENDIAN_MIPS
3041 emit_xorimm(temp,3,temp);
3042#endif
535d208a 3043 emit_testimm(temp,2);
3044 case2=(int)out;
3045 emit_jne(0);
3046 emit_testimm(temp,1);
3047 case1=(int)out;
3048 emit_jne(0);
3049 // 0
3050 if (opcode[i]==0x2A) { // SWL
3051 emit_writeword_indexed(tl,0,temp);
3052 }
3053 if (opcode[i]==0x2E) { // SWR
3054 emit_writebyte_indexed(tl,3,temp);
3055 }
3056 if (opcode[i]==0x2C) { // SDL
3057 emit_writeword_indexed(th,0,temp);
3058 if(rs2[i]) emit_mov(tl,temp2);
3059 }
3060 if (opcode[i]==0x2D) { // SDR
3061 emit_writebyte_indexed(tl,3,temp);
3062 if(rs2[i]) emit_shldimm(th,tl,24,temp2);
3063 }
3064 done0=(int)out;
3065 emit_jmp(0);
3066 // 1
3067 set_jump_target(case1,(int)out);
3068 if (opcode[i]==0x2A) { // SWL
3069 // Write 3 msb into three least significant bytes
3070 if(rs2[i]) emit_rorimm(tl,8,tl);
3071 emit_writehword_indexed(tl,-1,temp);
3072 if(rs2[i]) emit_rorimm(tl,16,tl);
3073 emit_writebyte_indexed(tl,1,temp);
3074 if(rs2[i]) emit_rorimm(tl,8,tl);
3075 }
3076 if (opcode[i]==0x2E) { // SWR
3077 // Write two lsb into two most significant bytes
3078 emit_writehword_indexed(tl,1,temp);
3079 }
3080 if (opcode[i]==0x2C) { // SDL
3081 if(rs2[i]) emit_shrdimm(tl,th,8,temp2);
3082 // Write 3 msb into three least significant bytes
3083 if(rs2[i]) emit_rorimm(th,8,th);
3084 emit_writehword_indexed(th,-1,temp);
3085 if(rs2[i]) emit_rorimm(th,16,th);
3086 emit_writebyte_indexed(th,1,temp);
3087 if(rs2[i]) emit_rorimm(th,8,th);
3088 }
3089 if (opcode[i]==0x2D) { // SDR
3090 if(rs2[i]) emit_shldimm(th,tl,16,temp2);
3091 // Write two lsb into two most significant bytes
3092 emit_writehword_indexed(tl,1,temp);
3093 }
3094 done1=(int)out;
3095 emit_jmp(0);
3096 // 2
3097 set_jump_target(case2,(int)out);
3098 emit_testimm(temp,1);
3099 case3=(int)out;
3100 emit_jne(0);
3101 if (opcode[i]==0x2A) { // SWL
3102 // Write two msb into two least significant bytes
3103 if(rs2[i]) emit_rorimm(tl,16,tl);
3104 emit_writehword_indexed(tl,-2,temp);
3105 if(rs2[i]) emit_rorimm(tl,16,tl);
3106 }
3107 if (opcode[i]==0x2E) { // SWR
3108 // Write 3 lsb into three most significant bytes
3109 emit_writebyte_indexed(tl,-1,temp);
3110 if(rs2[i]) emit_rorimm(tl,8,tl);
3111 emit_writehword_indexed(tl,0,temp);
3112 if(rs2[i]) emit_rorimm(tl,24,tl);
3113 }
3114 if (opcode[i]==0x2C) { // SDL
3115 if(rs2[i]) emit_shrdimm(tl,th,16,temp2);
3116 // Write two msb into two least significant bytes
3117 if(rs2[i]) emit_rorimm(th,16,th);
3118 emit_writehword_indexed(th,-2,temp);
3119 if(rs2[i]) emit_rorimm(th,16,th);
3120 }
3121 if (opcode[i]==0x2D) { // SDR
3122 if(rs2[i]) emit_shldimm(th,tl,8,temp2);
3123 // Write 3 lsb into three most significant bytes
3124 emit_writebyte_indexed(tl,-1,temp);
3125 if(rs2[i]) emit_rorimm(tl,8,tl);
3126 emit_writehword_indexed(tl,0,temp);
3127 if(rs2[i]) emit_rorimm(tl,24,tl);
3128 }
3129 done2=(int)out;
3130 emit_jmp(0);
3131 // 3
3132 set_jump_target(case3,(int)out);
3133 if (opcode[i]==0x2A) { // SWL
3134 // Write msb into least significant byte
3135 if(rs2[i]) emit_rorimm(tl,24,tl);
3136 emit_writebyte_indexed(tl,-3,temp);
3137 if(rs2[i]) emit_rorimm(tl,8,tl);
3138 }
3139 if (opcode[i]==0x2E) { // SWR
3140 // Write entire word
3141 emit_writeword_indexed(tl,-3,temp);
3142 }
3143 if (opcode[i]==0x2C) { // SDL
3144 if(rs2[i]) emit_shrdimm(tl,th,24,temp2);
3145 // Write msb into least significant byte
3146 if(rs2[i]) emit_rorimm(th,24,th);
3147 emit_writebyte_indexed(th,-3,temp);
3148 if(rs2[i]) emit_rorimm(th,8,th);
3149 }
3150 if (opcode[i]==0x2D) { // SDR
3151 if(rs2[i]) emit_mov(th,temp2);
3152 // Write entire word
3153 emit_writeword_indexed(tl,-3,temp);
3154 }
3155 set_jump_target(done0,(int)out);
3156 set_jump_target(done1,(int)out);
3157 set_jump_target(done2,(int)out);
3158 if (opcode[i]==0x2C) { // SDL
3159 emit_testimm(temp,4);
57871462 3160 done0=(int)out;
57871462 3161 emit_jne(0);
535d208a 3162 emit_andimm(temp,~3,temp);
3163 emit_writeword_indexed(temp2,4,temp);
3164 set_jump_target(done0,(int)out);
3165 }
3166 if (opcode[i]==0x2D) { // SDR
3167 emit_testimm(temp,4);
3168 done0=(int)out;
3169 emit_jeq(0);
3170 emit_andimm(temp,~3,temp);
3171 emit_writeword_indexed(temp2,-4,temp);
57871462 3172 set_jump_target(done0,(int)out);
57871462 3173 }
535d208a 3174 if(!c||!memtarget)
3175 add_stub(STORELR_STUB,jaddr,(int)out,i,(int)i_regs,temp,ccadj[i],reglist);
1edfcc68 3176 if(!(i_regs->waswritten&(1<<rs1[i]))&&!(new_dynarec_hacks&NDHACK_NO_SMC_CHECK)) {
535d208a 3177 #ifdef RAM_OFFSET
3178 int map=get_reg(i_regs->regmap,ROREG);
3179 if(map<0) map=HOST_TEMPREG;
3180 gen_orig_addr_w(temp,map);
3181 #else
57871462 3182 emit_addimm_no_flags((u_int)0x80000000-(u_int)rdram,temp);
535d208a 3183 #endif
57871462 3184 #if defined(HOST_IMM8)
3185 int ir=get_reg(i_regs->regmap,INVCP);
3186 assert(ir>=0);
3187 emit_cmpmem_indexedsr12_reg(ir,temp,1);
3188 #else
3189 emit_cmpmem_indexedsr12_imm((int)invalid_code,temp,1);
3190 #endif
535d208a 3191 #if defined(HAVE_CONDITIONAL_CALL) && !defined(DESTRUCTIVE_SHIFT)
3192 emit_callne(invalidate_addr_reg[temp]);
3193 #else
57871462 3194 jaddr2=(int)out;
3195 emit_jne(0);
3196 add_stub(INVCODE_STUB,jaddr2,(int)out,reglist|(1<<HOST_CCREG),temp,0,0,0);
535d208a 3197 #endif
57871462 3198 }
3199 /*
3200 emit_pusha();
3201 //save_regs(0x100f);
3202 emit_readword((int)&last_count,ECX);
3203 if(get_reg(i_regs->regmap,CCREG)<0)
3204 emit_loadreg(CCREG,HOST_CCREG);
3205 emit_add(HOST_CCREG,ECX,HOST_CCREG);
3206 emit_addimm(HOST_CCREG,2*ccadj[i],HOST_CCREG);
3207 emit_writeword(HOST_CCREG,(int)&Count);
3208 emit_call((int)memdebug);
3209 emit_popa();
3210 //restore_regs(0x100f);
3211 /**/
3212}
3213
3214void c1ls_assemble(int i,struct regstat *i_regs)
3215{
3d624f89 3216 cop1_unusable(i, i_regs);
57871462 3217}
3218
b9b61529 3219void c2ls_assemble(int i,struct regstat *i_regs)
3220{
3221 int s,tl;
3222 int ar;
3223 int offset;
1fd1aceb 3224 int memtarget=0,c=0;
c2e3bd42 3225 int jaddr2=0,jaddr3,type;
b9b61529 3226 int agr=AGEN1+(i&1);
ffb0b9e0 3227 int fastio_reg_override=0;
b9b61529 3228 u_int hr,reglist=0;
3229 u_int copr=(source[i]>>16)&0x1f;
3230 s=get_reg(i_regs->regmap,rs1[i]);
3231 tl=get_reg(i_regs->regmap,FTEMP);
3232 offset=imm[i];
3233 assert(rs1[i]>0);
3234 assert(tl>=0);
b9b61529 3235
3236 for(hr=0;hr<HOST_REGS;hr++) {
3237 if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
3238 }
3239 if(i_regs->regmap[HOST_CCREG]==CCREG)
3240 reglist&=~(1<<HOST_CCREG);
3241