notaz.gp2x.de / pcsx_rearmed.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
drc: drop heaps of dead code
[pcsx_rearmed.git] / libpcsxcore / new_dynarec / new_dynarec.c
CommitLineData
57871462 1/* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
2 * Mupen64plus - new_dynarec.c *
20d507ba 3 * Copyright (C) 2009-2011 Ari64 *
57871462 4 * *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
9 * *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
14 * *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. *
19 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */
20
21#include <stdlib.h>
22#include <stdint.h> //include for uint64_t
23#include <assert.h>
d848b60a 24#include <errno.h>
4600ba03 25#include <sys/mman.h>
57871462 26
3d624f89 27#include "emu_if.h" //emulator interface
57871462 28
4600ba03 29//#define DISASM
30//#define assem_debug printf
31//#define inv_debug printf
32#define assem_debug(...)
33#define inv_debug(...)
57871462 34
35#ifdef __i386__
36#include "assem_x86.h"
37#endif
38#ifdef __x86_64__
39#include "assem_x64.h"
40#endif
41#ifdef __arm__
42#include "assem_arm.h"
43#endif
44
f23d3386 45#ifdef __BLACKBERRY_QNX__
a4874585
C		 46#undef __clear_cache
47#define __clear_cache(start,end) msync(start, (size_t)((void*)end - (void*)start), MS_SYNC | MS_CACHE_ONLY | MS_INVALIDATE_ICACHE);
c7b746f0 48#elif defined(__MACH__)
49#include <libkern/OSCacheControl.h>
50#define __clear_cache mach_clear_cache
51static void __clear_cache(void *start, void *end) {
52 size_t len = (char *)end - (char *)start;
53 sys_dcache_flush(start, len);
54 sys_icache_invalidate(start, len);
55}
f23d3386 56#endif
a4874585 57
57871462 58#define MAXBLOCK 4096
59#define MAX_OUTPUT_BLOCK_SIZE 262144
2573466a 60
57871462 61struct regstat
62{
63 signed char regmap_entry[HOST_REGS];
64 signed char regmap[HOST_REGS];
65 uint64_t was32;
66 uint64_t is32;
67 uint64_t wasdirty;
68 uint64_t dirty;
69 uint64_t u;
70 uint64_t uu;
71 u_int wasconst;
72 u_int isconst;
8575a877 73 u_int loadedconst; // host regs that have constants loaded
74 u_int waswritten; // MIPS regs that were used as store base before
57871462 75};
76
de5a60c3 77// note: asm depends on this layout
57871462 78struct ll_entry
79{
80 u_int vaddr;
de5a60c3 81 u_int reg_sv_flags;
57871462 82 void *addr;
83 struct ll_entry *next;
84};
85
86 u_int start;
87 u_int *source;
57871462 88 char insn[MAXBLOCK][10];
89 u_char itype[MAXBLOCK];
90 u_char opcode[MAXBLOCK];
91 u_char opcode2[MAXBLOCK];
92 u_char bt[MAXBLOCK];
93 u_char rs1[MAXBLOCK];
94 u_char rs2[MAXBLOCK];
95 u_char rt1[MAXBLOCK];
96 u_char rt2[MAXBLOCK];
97 u_char us1[MAXBLOCK];
98 u_char us2[MAXBLOCK];
99 u_char dep1[MAXBLOCK];
100 u_char dep2[MAXBLOCK];
101 u_char lt1[MAXBLOCK];
bedfea38 102 static uint64_t gte_rs[MAXBLOCK]; // gte: 32 data and 32 ctl regs
103 static uint64_t gte_rt[MAXBLOCK];
104 static uint64_t gte_unneeded[MAXBLOCK];
ffb0b9e0 105 static u_int smrv[32]; // speculated MIPS register values
106 static u_int smrv_strong; // mask or regs that are likely to have correct values
107 static u_int smrv_weak; // same, but somewhat less likely
108 static u_int smrv_strong_next; // same, but after current insn executes
109 static u_int smrv_weak_next;
57871462 110 int imm[MAXBLOCK];
111 u_int ba[MAXBLOCK];
112 char likely[MAXBLOCK];
113 char is_ds[MAXBLOCK];
e1190b87 114 char ooo[MAXBLOCK];
57871462 115 uint64_t unneeded_reg[MAXBLOCK];
116 uint64_t unneeded_reg_upper[MAXBLOCK];
117 uint64_t branch_unneeded_reg[MAXBLOCK];
118 uint64_t branch_unneeded_reg_upper[MAXBLOCK];
119 uint64_t p32[MAXBLOCK];
120 uint64_t pr32[MAXBLOCK];
121 signed char regmap_pre[MAXBLOCK][HOST_REGS];
956f3129 122 static uint64_t current_constmap[HOST_REGS];
123 static uint64_t constmap[MAXBLOCK][HOST_REGS];
124 static struct regstat regs[MAXBLOCK];
125 static struct regstat branch_regs[MAXBLOCK];
e1190b87 126 signed char minimum_free_regs[MAXBLOCK];
57871462 127 u_int needed_reg[MAXBLOCK];
128 uint64_t requires_32bit[MAXBLOCK];
129 u_int wont_dirty[MAXBLOCK];
130 u_int will_dirty[MAXBLOCK];
131 int ccadj[MAXBLOCK];
132 int slen;
133 u_int instr_addr[MAXBLOCK];
134 u_int link_addr[MAXBLOCK][3];
135 int linkcount;
136 u_int stubs[MAXBLOCK*3][8];
137 int stubcount;
138 u_int literals[1024][2];
139 int literalcount;
140 int is_delayslot;
141 int cop1_usable;
142 u_char *out;
de5a60c3 143 struct ll_entry *jump_in[4096] __attribute__((aligned(16)));
57871462 144 struct ll_entry *jump_out[4096];
145 struct ll_entry *jump_dirty[4096];
146 u_int hash_table[65536][4] __attribute__((aligned(16)));
147 char shadow[1048576] __attribute__((aligned(16)));
148 void *copy;
149 int expirep;
af4ee1fe 150 static const u_int using_tlb=0;
2f546f9a 151 int new_dynarec_did_compile;
0ff8c62c 152 int new_dynarec_hacks;
57871462 153 u_int stop_after_jal;
a327ad27 154#ifndef RAM_FIXED
155 static u_int ram_offset;
156#else
157 static const u_int ram_offset=0;
158#endif
57871462 159 extern u_char restore_candidate[512];
160 extern int cycle_count;
161
162 /* registers that may be allocated */
163 /* 1-31 gpr */
164#define HIREG 32 // hi
165#define LOREG 33 // lo
166#define FSREG 34 // FPU status (FCSR)
167#define CSREG 35 // Coprocessor status
168#define CCREG 36 // Cycle count
169#define INVCP 37 // Pointer to invalid_code
619e5ded 170#define MMREG 38 // Pointer to memory_map
171#define ROREG 39 // ram offset (if rdram!=0x80000000)
172#define TEMPREG 40
173#define FTEMP 40 // FPU temporary register
174#define PTEMP 41 // Prefetch temporary register
175#define TLREG 42 // TLB mapping offset
176#define RHASH 43 // Return address hash
177#define RHTBL 44 // Return address hash table address
178#define RTEMP 45 // JR/JALR address register
179#define MAXREG 45
180#define AGEN1 46 // Address generation temporary register
181#define AGEN2 47 // Address generation temporary register
182#define MGEN1 48 // Maptable address generation temporary register
183#define MGEN2 49 // Maptable address generation temporary register
184#define BTREG 50 // Branch target temporary register
57871462 185
186 /* instruction types */
187#define NOP 0 // No operation
188#define LOAD 1 // Load
189#define STORE 2 // Store
190#define LOADLR 3 // Unaligned load
191#define STORELR 4 // Unaligned store
192#define MOV 5 // Move
193#define ALU 6 // Arithmetic/logic
194#define MULTDIV 7 // Multiply/divide
195#define SHIFT 8 // Shift by register
196#define SHIFTIMM 9// Shift by immediate
197#define IMM16 10 // 16-bit immediate
198#define RJUMP 11 // Unconditional jump to register
199#define UJUMP 12 // Unconditional jump
200#define CJUMP 13 // Conditional branch (BEQ/BNE/BGTZ/BLEZ)
201#define SJUMP 14 // Conditional branch (regimm format)
202#define COP0 15 // Coprocessor 0
203#define COP1 16 // Coprocessor 1
204#define C1LS 17 // Coprocessor 1 load/store
205#define FJUMP 18 // Conditional branch (floating point)
206#define FLOAT 19 // Floating point unit
207#define FCONV 20 // Convert integer to float
208#define FCOMP 21 // Floating point compare (sets FSREG)
209#define SYSCALL 22// SYSCALL
210#define OTHER 23 // Other
211#define SPAN 24 // Branch/delay slot spans 2 pages
212#define NI 25 // Not implemented
7139f3c8 213#define HLECALL 26// PCSX fake opcodes for HLE
b9b61529 214#define COP2 27 // Coprocessor 2 move
215#define C2LS 28 // Coprocessor 2 load/store
216#define C2OP 29 // Coprocessor 2 operation
1e973cb0 217#define INTCALL 30// Call interpreter to handle rare corner cases
57871462 218
219 /* stubs */
220#define CC_STUB 1
221#define FP_STUB 2
222#define LOADB_STUB 3
223#define LOADH_STUB 4
224#define LOADW_STUB 5
225#define LOADD_STUB 6
226#define LOADBU_STUB 7
227#define LOADHU_STUB 8
228#define STOREB_STUB 9
229#define STOREH_STUB 10
230#define STOREW_STUB 11
231#define STORED_STUB 12
232#define STORELR_STUB 13
233#define INVCODE_STUB 14
234
235 /* branch codes */
236#define TAKEN 1
237#define NOTTAKEN 2
238#define NULLDS 3
239
240// asm linkage
241int new_recompile_block(int addr);
242void *get_addr_ht(u_int vaddr);
243void invalidate_block(u_int block);
244void invalidate_addr(u_int addr);
245void remove_hash(int vaddr);
246void jump_vaddr();
247void dyna_linker();
248void dyna_linker_ds();
249void verify_code();
250void verify_code_vm();
251void verify_code_ds();
252void cc_interrupt();
253void fp_exception();
254void fp_exception_ds();
255void jump_syscall();
7139f3c8 256void jump_syscall_hle();
57871462 257void jump_eret();
7139f3c8 258void jump_hlecall();
1e973cb0 259void jump_intcall();
7139f3c8 260void new_dyna_leave();
57871462 261
262// TLB
263void TLBWI_new();
264void TLBWR_new();
265void read_nomem_new();
266void read_nomemb_new();
267void read_nomemh_new();
268void read_nomemd_new();
269void write_nomem_new();
270void write_nomemb_new();
271void write_nomemh_new();
272void write_nomemd_new();
273void write_rdram_new();
274void write_rdramb_new();
275void write_rdramh_new();
276void write_rdramd_new();
277extern u_int memory_map[1048576];
278
279// Needed by assembler
280void wb_register(signed char r,signed char regmap[],uint64_t dirty,uint64_t is32);
281void wb_dirtys(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty);
282void wb_needed_dirtys(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr);
283void load_all_regs(signed char i_regmap[]);
284void load_needed_regs(signed char i_regmap[],signed char next_regmap[]);
285void load_regs_entry(int t);
286void load_all_consts(signed char regmap[],int is32,u_int dirty,int i);
287
288int tracedebug=0;
289
290//#define DEBUG_CYCLE_COUNT 1
291
b6e87b2b 292#define NO_CYCLE_PENALTY_THR 12
293
4e9dcd7f 294int cycle_multiplier; // 100 for 1.0
295
296static int CLOCK_ADJUST(int x)
297{
298 int s=(x>>31)|1;
299 return (x * cycle_multiplier + s * 50) / 100;
300}
301
94d23bb9 302static u_int get_page(u_int vaddr)
57871462 303{
0ce47d46 304 u_int page=vaddr&~0xe0000000;
305 if (page < 0x1000000)
306 page &= ~0x0e00000; // RAM mirrors
307 page>>=12;
57871462 308 if(page>2048) page=2048+(page&2047);
94d23bb9 309 return page;
310}
311
d25604ca 312// no virtual mem in PCSX
313static u_int get_vpage(u_int vaddr)
314{
315 return get_page(vaddr);
316}
94d23bb9 317
318// Get address from virtual address
319// This is called from the recompiled JR/JALR instructions
320void *get_addr(u_int vaddr)
321{
322 u_int page=get_page(vaddr);
323 u_int vpage=get_vpage(vaddr);
57871462 324 struct ll_entry *head;
325 //printf("TRACE: count=%d next=%d (get_addr %x,page %d)\n",Count,next_interupt,vaddr,page);
326 head=jump_in[page];
327 while(head!=NULL) {
de5a60c3 328 if(head->vaddr==vaddr) {
57871462 329 //printf("TRACE: count=%d next=%d (get_addr match %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr);
330 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
331 ht_bin[3]=ht_bin[1];
332 ht_bin[2]=ht_bin[0];
333 ht_bin[1]=(int)head->addr;
334 ht_bin[0]=vaddr;
335 return head->addr;
336 }
337 head=head->next;
338 }
339 head=jump_dirty[vpage];
340 while(head!=NULL) {
de5a60c3 341 if(head->vaddr==vaddr) {
57871462 342 //printf("TRACE: count=%d next=%d (get_addr match dirty %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr);
343 // Don't restore blocks which are about to expire from the cache
344 if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
345 if(verify_dirty(head->addr)) {
346 //printf("restore candidate: %x (%d) d=%d\n",vaddr,page,invalid_code[vaddr>>12]);
347 invalid_code[vaddr>>12]=0;
9be4ba64 348 inv_code_start=inv_code_end=~0;
57871462 349 if(vpage<2048) {
57871462 350 restore_candidate[vpage>>3]|=1<<(vpage&7);
351 }
352 else restore_candidate[page>>3]|=1<<(page&7);
353 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
354 if(ht_bin[0]==vaddr) {
355 ht_bin[1]=(int)head->addr; // Replace existing entry
356 }
357 else
358 {
359 ht_bin[3]=ht_bin[1];
360 ht_bin[2]=ht_bin[0];
361 ht_bin[1]=(int)head->addr;
362 ht_bin[0]=vaddr;
363 }
364 return head->addr;
365 }
366 }
367 head=head->next;
368 }
369 //printf("TRACE: count=%d next=%d (get_addr no-match %x)\n",Count,next_interupt,vaddr);
370 int r=new_recompile_block(vaddr);
371 if(r==0) return get_addr(vaddr);
372 // Execute in unmapped page, generate pagefault execption
373 Status|=2;
374 Cause=(vaddr<<31)|0x8;
375 EPC=(vaddr&1)?vaddr-5:vaddr;
376 BadVAddr=(vaddr&~1);
377 Context=(Context&0xFF80000F)|((BadVAddr>>9)&0x007FFFF0);
378 EntryHi=BadVAddr&0xFFFFE000;
379 return get_addr_ht(0x80000000);
380}
381// Look up address in hash table first
382void *get_addr_ht(u_int vaddr)
383{
384 //printf("TRACE: count=%d next=%d (get_addr_ht %x)\n",Count,next_interupt,vaddr);
385 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
386 if(ht_bin[0]==vaddr) return (void *)ht_bin[1];
387 if(ht_bin[2]==vaddr) return (void *)ht_bin[3];
388 return get_addr(vaddr);
389}
390
57871462 391void clear_all_regs(signed char regmap[])
392{
393 int hr;
394 for (hr=0;hr<HOST_REGS;hr++) regmap[hr]=-1;
395}
396
397signed char get_reg(signed char regmap[],int r)
398{
399 int hr;
400 for (hr=0;hr<HOST_REGS;hr++) if(hr!=EXCLUDE_REG&&regmap[hr]==r) return hr;
401 return -1;
402}
403
404// Find a register that is available for two consecutive cycles
405signed char get_reg2(signed char regmap1[],signed char regmap2[],int r)
406{
407 int hr;
408 for (hr=0;hr<HOST_REGS;hr++) if(hr!=EXCLUDE_REG&&regmap1[hr]==r&&regmap2[hr]==r) return hr;
409 return -1;
410}
411
412int count_free_regs(signed char regmap[])
413{
414 int count=0;
415 int hr;
416 for(hr=0;hr<HOST_REGS;hr++)
417 {
418 if(hr!=EXCLUDE_REG) {
419 if(regmap[hr]<0) count++;
420 }
421 }
422 return count;
423}
424
425void dirty_reg(struct regstat *cur,signed char reg)
426{
427 int hr;
428 if(!reg) return;
429 for (hr=0;hr<HOST_REGS;hr++) {
430 if((cur->regmap[hr]&63)==reg) {
431 cur->dirty|=1<<hr;
432 }
433 }
434}
435
436// If we dirty the lower half of a 64 bit register which is now being
437// sign-extended, we need to dump the upper half.
438// Note: Do this only after completion of the instruction, because
439// some instructions may need to read the full 64-bit value even if
440// overwriting it (eg SLTI, DSRA32).
441static void flush_dirty_uppers(struct regstat *cur)
442{
443 int hr,reg;
444 for (hr=0;hr<HOST_REGS;hr++) {
445 if((cur->dirty>>hr)&1) {
446 reg=cur->regmap[hr];
447 if(reg>=64)
448 if((cur->is32>>(reg&63))&1) cur->regmap[hr]=-1;
449 }
450 }
451}
452
453void set_const(struct regstat *cur,signed char reg,uint64_t value)
454{
455 int hr;
456 if(!reg) return;
457 for (hr=0;hr<HOST_REGS;hr++) {
458 if(cur->regmap[hr]==reg) {
459 cur->isconst|=1<<hr;
956f3129 460 current_constmap[hr]=value;
57871462 461 }
462 else if((cur->regmap[hr]^64)==reg) {
463 cur->isconst|=1<<hr;
956f3129 464 current_constmap[hr]=value>>32;
57871462 465 }
466 }
467}
468
469void clear_const(struct regstat *cur,signed char reg)
470{
471 int hr;
472 if(!reg) return;
473 for (hr=0;hr<HOST_REGS;hr++) {
474 if((cur->regmap[hr]&63)==reg) {
475 cur->isconst&=~(1<<hr);
476 }
477 }
478}
479
480int is_const(struct regstat *cur,signed char reg)
481{
482 int hr;
79c75f1b 483 if(reg<0) return 0;
57871462 484 if(!reg) return 1;
485 for (hr=0;hr<HOST_REGS;hr++) {
486 if((cur->regmap[hr]&63)==reg) {
487 return (cur->isconst>>hr)&1;
488 }
489 }
490 return 0;
491}
492uint64_t get_const(struct regstat *cur,signed char reg)
493{
494 int hr;
495 if(!reg) return 0;
496 for (hr=0;hr<HOST_REGS;hr++) {
497 if(cur->regmap[hr]==reg) {
956f3129 498 return current_constmap[hr];
57871462 499 }
500 }
c43b5311 501 SysPrintf("Unknown constant in r%d\n",reg);
57871462 502 exit(1);
503}
504
505// Least soon needed registers
506// Look at the next ten instructions and see which registers
507// will be used. Try not to reallocate these.
508void lsn(u_char hsn[], int i, int *preferred_reg)
509{
510 int j;
511 int b=-1;
512 for(j=0;j<9;j++)
513 {
514 if(i+j>=slen) {
515 j=slen-i-1;
516 break;
517 }
518 if(itype[i+j]==UJUMP||itype[i+j]==RJUMP||(source[i+j]>>16)==0x1000)
519 {
520 // Don't go past an unconditonal jump
521 j++;
522 break;
523 }
524 }
525 for(;j>=0;j--)
526 {
527 if(rs1[i+j]) hsn[rs1[i+j]]=j;
528 if(rs2[i+j]) hsn[rs2[i+j]]=j;
529 if(rt1[i+j]) hsn[rt1[i+j]]=j;
530 if(rt2[i+j]) hsn[rt2[i+j]]=j;
531 if(itype[i+j]==STORE || itype[i+j]==STORELR) {
532 // Stores can allocate zero
533 hsn[rs1[i+j]]=j;
534 hsn[rs2[i+j]]=j;
535 }
536 // On some architectures stores need invc_ptr
537 #if defined(HOST_IMM8)
b9b61529 538 if(itype[i+j]==STORE || itype[i+j]==STORELR || (opcode[i+j]&0x3b)==0x39 || (opcode[i+j]&0x3b)==0x3a) {
57871462 539 hsn[INVCP]=j;
540 }
541 #endif
542 if(i+j>=0&&(itype[i+j]==UJUMP||itype[i+j]==CJUMP||itype[i+j]==SJUMP||itype[i+j]==FJUMP))
543 {
544 hsn[CCREG]=j;
545 b=j;
546 }
547 }
548 if(b>=0)
549 {
550 if(ba[i+b]>=start && ba[i+b]<(start+slen*4))
551 {
552 // Follow first branch
553 int t=(ba[i+b]-start)>>2;
554 j=7-b;if(t+j>=slen) j=slen-t-1;
555 for(;j>=0;j--)
556 {
557 if(rs1[t+j]) if(hsn[rs1[t+j]]>j+b+2) hsn[rs1[t+j]]=j+b+2;
558 if(rs2[t+j]) if(hsn[rs2[t+j]]>j+b+2) hsn[rs2[t+j]]=j+b+2;
559 //if(rt1[t+j]) if(hsn[rt1[t+j]]>j+b+2) hsn[rt1[t+j]]=j+b+2;
560 //if(rt2[t+j]) if(hsn[rt2[t+j]]>j+b+2) hsn[rt2[t+j]]=j+b+2;
561 }
562 }
563 // TODO: preferred register based on backward branch
564 }
565 // Delay slot should preferably not overwrite branch conditions or cycle count
566 if(i>0&&(itype[i-1]==RJUMP||itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP)) {
567 if(rs1[i-1]) if(hsn[rs1[i-1]]>1) hsn[rs1[i-1]]=1;
568 if(rs2[i-1]) if(hsn[rs2[i-1]]>1) hsn[rs2[i-1]]=1;
569 hsn[CCREG]=1;
570 // ...or hash tables
571 hsn[RHASH]=1;
572 hsn[RHTBL]=1;
573 }
574 // Coprocessor load/store needs FTEMP, even if not declared
b9b61529 575 if(itype[i]==C1LS||itype[i]==C2LS) {
57871462 576 hsn[FTEMP]=0;
577 }
578 // Load L/R also uses FTEMP as a temporary register
579 if(itype[i]==LOADLR) {
580 hsn[FTEMP]=0;
581 }
b7918751 582 // Also SWL/SWR/SDL/SDR
583 if(opcode[i]==0x2a||opcode[i]==0x2e||opcode[i]==0x2c||opcode[i]==0x2d) {
57871462 584 hsn[FTEMP]=0;
585 }
586 // Don't remove the TLB registers either
b9b61529 587 if(itype[i]==LOAD || itype[i]==LOADLR || itype[i]==STORE || itype[i]==STORELR || itype[i]==C1LS || itype[i]==C2LS) {
57871462 588 hsn[TLREG]=0;
589 }
590 // Don't remove the miniht registers
591 if(itype[i]==UJUMP||itype[i]==RJUMP)
592 {
593 hsn[RHASH]=0;
594 hsn[RHTBL]=0;
595 }
596}
597
598// We only want to allocate registers if we're going to use them again soon
599int needed_again(int r, int i)
600{
601 int j;
602 int b=-1;
603 int rn=10;
57871462 604
605 if(i>0&&(itype[i-1]==UJUMP||itype[i-1]==RJUMP||(source[i-1]>>16)==0x1000))
606 {
607 if(ba[i-1]<start || ba[i-1]>start+slen*4-4)
608 return 0; // Don't need any registers if exiting the block
609 }
610 for(j=0;j<9;j++)
611 {
612 if(i+j>=slen) {
613 j=slen-i-1;
614 break;
615 }
616 if(itype[i+j]==UJUMP||itype[i+j]==RJUMP||(source[i+j]>>16)==0x1000)
617 {
618 // Don't go past an unconditonal jump
619 j++;
620 break;
621 }
1e973cb0 622 if(itype[i+j]==SYSCALL||itype[i+j]==HLECALL||itype[i+j]==INTCALL||((source[i+j]&0xfc00003f)==0x0d))
57871462 623 {
624 break;
625 }
626 }
627 for(;j>=1;j--)
628 {
629 if(rs1[i+j]==r) rn=j;
630 if(rs2[i+j]==r) rn=j;
631 if((unneeded_reg[i+j]>>r)&1) rn=10;
632 if(i+j>=0&&(itype[i+j]==UJUMP||itype[i+j]==CJUMP||itype[i+j]==SJUMP||itype[i+j]==FJUMP))
633 {
634 b=j;
635 }
636 }
637 /*
638 if(b>=0)
639 {
640 if(ba[i+b]>=start && ba[i+b]<(start+slen*4))
641 {
642 // Follow first branch
643 int o=rn;
644 int t=(ba[i+b]-start)>>2;
645 j=7-b;if(t+j>=slen) j=slen-t-1;
646 for(;j>=0;j--)
647 {
648 if(!((unneeded_reg[t+j]>>r)&1)) {
649 if(rs1[t+j]==r) if(rn>j+b+2) rn=j+b+2;
650 if(rs2[t+j]==r) if(rn>j+b+2) rn=j+b+2;
651 }
652 else rn=o;
653 }
654 }
655 }*/
b7217e13 656 if(rn<10) return 1;
57871462 657 return 0;
658}
659
660// Try to match register allocations at the end of a loop with those
661// at the beginning
662int loop_reg(int i, int r, int hr)
663{
664 int j,k;
665 for(j=0;j<9;j++)
666 {
667 if(i+j>=slen) {
668 j=slen-i-1;
669 break;
670 }
671 if(itype[i+j]==UJUMP||itype[i+j]==RJUMP||(source[i+j]>>16)==0x1000)
672 {
673 // Don't go past an unconditonal jump
674 j++;
675 break;
676 }
677 }
678 k=0;
679 if(i>0){
680 if(itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP)
681 k--;
682 }
683 for(;k<j;k++)
684 {
685 if(r<64&&((unneeded_reg[i+k]>>r)&1)) return hr;
686 if(r>64&&((unneeded_reg_upper[i+k]>>r)&1)) return hr;
687 if(i+k>=0&&(itype[i+k]==UJUMP||itype[i+k]==CJUMP||itype[i+k]==SJUMP||itype[i+k]==FJUMP))
688 {
689 if(ba[i+k]>=start && ba[i+k]<(start+i*4))
690 {
691 int t=(ba[i+k]-start)>>2;
692 int reg=get_reg(regs[t].regmap_entry,r);
693 if(reg>=0) return reg;
694 //reg=get_reg(regs[t+1].regmap_entry,r);
695 //if(reg>=0) return reg;
696 }
697 }
698 }
699 return hr;
700}
701
702
703// Allocate every register, preserving source/target regs
704void alloc_all(struct regstat *cur,int i)
705{
706 int hr;
707
708 for(hr=0;hr<HOST_REGS;hr++) {
709 if(hr!=EXCLUDE_REG) {
710 if(((cur->regmap[hr]&63)!=rs1[i])&&((cur->regmap[hr]&63)!=rs2[i])&&
711 ((cur->regmap[hr]&63)!=rt1[i])&&((cur->regmap[hr]&63)!=rt2[i]))
712 {
713 cur->regmap[hr]=-1;
714 cur->dirty&=~(1<<hr);
715 }
716 // Don't need zeros
717 if((cur->regmap[hr]&63)==0)
718 {
719 cur->regmap[hr]=-1;
720 cur->dirty&=~(1<<hr);
721 }
722 }
723 }
724}
725
57871462 726#ifdef __i386__
727#include "assem_x86.c"
728#endif
729#ifdef __x86_64__
730#include "assem_x64.c"
731#endif
732#ifdef __arm__
733#include "assem_arm.c"
734#endif
735
736// Add virtual address mapping to linked list
737void ll_add(struct ll_entry **head,int vaddr,void *addr)
738{
739 struct ll_entry *new_entry;
740 new_entry=malloc(sizeof(struct ll_entry));
741 assert(new_entry!=NULL);
742 new_entry->vaddr=vaddr;
de5a60c3 743 new_entry->reg_sv_flags=0;
57871462 744 new_entry->addr=addr;
745 new_entry->next=*head;
746 *head=new_entry;
747}
748
de5a60c3 749void ll_add_flags(struct ll_entry **head,int vaddr,u_int reg_sv_flags,void *addr)
57871462 750{
7139f3c8 751 ll_add(head,vaddr,addr);
de5a60c3 752 (*head)->reg_sv_flags=reg_sv_flags;
57871462 753}
754
755// Check if an address is already compiled
756// but don't return addresses which are about to expire from the cache
757void *check_addr(u_int vaddr)
758{
759 u_int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
760 if(ht_bin[0]==vaddr) {
761 if(((ht_bin[1]-MAX_OUTPUT_BLOCK_SIZE-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
762 if(isclean(ht_bin[1])) return (void *)ht_bin[1];
763 }
764 if(ht_bin[2]==vaddr) {
765 if(((ht_bin[3]-MAX_OUTPUT_BLOCK_SIZE-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
766 if(isclean(ht_bin[3])) return (void *)ht_bin[3];
767 }
94d23bb9 768 u_int page=get_page(vaddr);
57871462 769 struct ll_entry *head;
770 head=jump_in[page];
771 while(head!=NULL) {
de5a60c3 772 if(head->vaddr==vaddr) {
57871462 773 if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2))) {
774 // Update existing entry with current address
775 if(ht_bin[0]==vaddr) {
776 ht_bin[1]=(int)head->addr;
777 return head->addr;
778 }
779 if(ht_bin[2]==vaddr) {
780 ht_bin[3]=(int)head->addr;
781 return head->addr;
782 }
783 // Insert into hash table with low priority.
784 // Don't evict existing entries, as they are probably
785 // addresses that are being accessed frequently.
786 if(ht_bin[0]==-1) {
787 ht_bin[1]=(int)head->addr;
788 ht_bin[0]=vaddr;
789 }else if(ht_bin[2]==-1) {
790 ht_bin[3]=(int)head->addr;
791 ht_bin[2]=vaddr;
792 }
793 return head->addr;
794 }
795 }
796 head=head->next;
797 }
798 return 0;
799}
800
801void remove_hash(int vaddr)
802{
803 //printf("remove hash: %x\n",vaddr);
804 int *ht_bin=hash_table[(((vaddr)>>16)^vaddr)&0xFFFF];
805 if(ht_bin[2]==vaddr) {
806 ht_bin[2]=ht_bin[3]=-1;
807 }
808 if(ht_bin[0]==vaddr) {
809 ht_bin[0]=ht_bin[2];
810 ht_bin[1]=ht_bin[3];
811 ht_bin[2]=ht_bin[3]=-1;
812 }
813}
814
815void ll_remove_matching_addrs(struct ll_entry **head,int addr,int shift)
816{
817 struct ll_entry *next;
818 while(*head) {
819 if(((u_int)((*head)->addr)>>shift)==(addr>>shift) ||
820 ((u_int)((*head)->addr-MAX_OUTPUT_BLOCK_SIZE)>>shift)==(addr>>shift))
821 {
822 inv_debug("EXP: Remove pointer to %x (%x)\n",(int)(*head)->addr,(*head)->vaddr);
823 remove_hash((*head)->vaddr);
824 next=(*head)->next;
825 free(*head);
826 *head=next;
827 }
828 else
829 {
830 head=&((*head)->next);
831 }
832 }
833}
834
835// Remove all entries from linked list
836void ll_clear(struct ll_entry **head)
837{
838 struct ll_entry *cur;
839 struct ll_entry *next;
840 if(cur=*head) {
841 *head=0;
842 while(cur) {
843 next=cur->next;
844 free(cur);
845 cur=next;
846 }
847 }
848}
849
850// Dereference the pointers and remove if it matches
851void ll_kill_pointers(struct ll_entry *head,int addr,int shift)
852{
853 while(head) {
854 int ptr=get_pointer(head->addr);
855 inv_debug("EXP: Lookup pointer to %x at %x (%x)\n",(int)ptr,(int)head->addr,head->vaddr);
856 if(((ptr>>shift)==(addr>>shift)) ||
857 (((ptr-MAX_OUTPUT_BLOCK_SIZE)>>shift)==(addr>>shift)))
858 {
5088bb70 859 inv_debug("EXP: Kill pointer at %x (%x)\n",(int)head->addr,head->vaddr);
f76eeef9 860 u_int host_addr=(u_int)kill_pointer(head->addr);
dd3a91a1 861 #ifdef __arm__
862 needs_clear_cache[(host_addr-(u_int)BASE_ADDR)>>17]|=1<<(((host_addr-(u_int)BASE_ADDR)>>12)&31);
863 #endif
57871462 864 }
865 head=head->next;
866 }
867}
868
869// This is called when we write to a compiled block (see do_invstub)
f76eeef9 870void invalidate_page(u_int page)
57871462 871{
57871462 872 struct ll_entry *head;
873 struct ll_entry *next;
874 head=jump_in[page];
875 jump_in[page]=0;
876 while(head!=NULL) {
877 inv_debug("INVALIDATE: %x\n",head->vaddr);
878 remove_hash(head->vaddr);
879 next=head->next;
880 free(head);
881 head=next;
882 }
883 head=jump_out[page];
884 jump_out[page]=0;
885 while(head!=NULL) {
886 inv_debug("INVALIDATE: kill pointer to %x (%x)\n",head->vaddr,(int)head->addr);
f76eeef9 887 u_int host_addr=(u_int)kill_pointer(head->addr);
dd3a91a1 888 #ifdef __arm__
889 needs_clear_cache[(host_addr-(u_int)BASE_ADDR)>>17]|=1<<(((host_addr-(u_int)BASE_ADDR)>>12)&31);
890 #endif
57871462 891 next=head->next;
892 free(head);
893 head=next;
894 }
57871462 895}
9be4ba64 896
897static void invalidate_block_range(u_int block, u_int first, u_int last)
57871462 898{
94d23bb9 899 u_int page=get_page(block<<12);
57871462 900 //printf("first=%d last=%d\n",first,last);
f76eeef9 901 invalidate_page(page);
57871462 902 assert(first+5>page); // NB: this assumes MAXBLOCK<=4096 (4 pages)
903 assert(last<page+5);
904 // Invalidate the adjacent pages if a block crosses a 4K boundary
905 while(first<page) {
906 invalidate_page(first);
907 first++;
908 }
909 for(first=page+1;first<last;first++) {
910 invalidate_page(first);
911 }
dd3a91a1 912 #ifdef __arm__
913 do_clear_cache();
914 #endif
57871462 915
916 // Don't trap writes
917 invalid_code[block]=1;
f76eeef9 918
57871462 919 #ifdef USE_MINI_HT
920 memset(mini_ht,-1,sizeof(mini_ht));
921 #endif
922}
9be4ba64 923
924void invalidate_block(u_int block)
925{
926 u_int page=get_page(block<<12);
927 u_int vpage=get_vpage(block<<12);
928 inv_debug("INVALIDATE: %x (%d)\n",block<<12,page);
929 //inv_debug("invalid_code[block]=%d\n",invalid_code[block]);
930 u_int first,last;
931 first=last=page;
932 struct ll_entry *head;
933 head=jump_dirty[vpage];
934 //printf("page=%d vpage=%d\n",page,vpage);
935 while(head!=NULL) {
936 u_int start,end;
937 if(vpage>2047||(head->vaddr>>12)==block) { // Ignore vaddr hash collision
938 get_bounds((int)head->addr,&start,&end);
939 //printf("start: %x end: %x\n",start,end);
4a35de07 940 if(page<2048&&start>=(u_int)rdram&&end<(u_int)rdram+RAM_SIZE) {
9be4ba64 941 if(((start-(u_int)rdram)>>12)<=page&&((end-1-(u_int)rdram)>>12)>=page) {
942 if((((start-(u_int)rdram)>>12)&2047)<first) first=((start-(u_int)rdram)>>12)&2047;
943 if((((end-1-(u_int)rdram)>>12)&2047)>last) last=((end-1-(u_int)rdram)>>12)&2047;
944 }
945 }
9be4ba64 946 }
947 head=head->next;
948 }
949 invalidate_block_range(block,first,last);
950}
951
57871462 952void invalidate_addr(u_int addr)
953{
9be4ba64 954 //static int rhits;
955 // this check is done by the caller
956 //if (inv_code_start<=addr&&addr<=inv_code_end) { rhits++; return; }
d25604ca 957 u_int page=get_vpage(addr);
9be4ba64 958 if(page<2048) { // RAM
959 struct ll_entry *head;
960 u_int addr_min=~0, addr_max=0;
4a35de07 961 u_int mask=RAM_SIZE-1;
962 u_int addr_main=0x80000000|(addr&mask);
9be4ba64 963 int pg1;
4a35de07 964 inv_code_start=addr_main&~0xfff;
965 inv_code_end=addr_main|0xfff;
9be4ba64 966 pg1=page;
967 if (pg1>0) {
968 // must check previous page too because of spans..
969 pg1--;
970 inv_code_start-=0x1000;
971 }
972 for(;pg1<=page;pg1++) {
973 for(head=jump_dirty[pg1];head!=NULL;head=head->next) {
974 u_int start,end;
975 get_bounds((int)head->addr,&start,&end);
4a35de07 976 if(ram_offset) {
977 start-=ram_offset;
978 end-=ram_offset;
979 }
980 if(start<=addr_main&&addr_main<end) {
9be4ba64 981 if(start<addr_min) addr_min=start;
982 if(end>addr_max) addr_max=end;
983 }
4a35de07 984 else if(addr_main<start) {
9be4ba64 985 if(start<inv_code_end)
986 inv_code_end=start-1;
987 }
988 else {
989 if(end>inv_code_start)
990 inv_code_start=end;
991 }
992 }
993 }
994 if (addr_min!=~0) {
995 inv_debug("INV ADDR: %08x hit %08x-%08x\n", addr, addr_min, addr_max);
996 inv_code_start=inv_code_end=~0;
997 invalidate_block_range(addr>>12,(addr_min&mask)>>12,(addr_max&mask)>>12);
998 return;
999 }
1000 else {
4a35de07 1001 inv_code_start=(addr&~mask)|(inv_code_start&mask);
1002 inv_code_end=(addr&~mask)|(inv_code_end&mask);
d25604ca 1003 inv_debug("INV ADDR: %08x miss, inv %08x-%08x, sk %d\n", addr, inv_code_start, inv_code_end, 0);
9be4ba64 1004 return;
d25604ca 1005 }
9be4ba64 1006 }
57871462 1007 invalidate_block(addr>>12);
1008}
9be4ba64 1009
dd3a91a1 1010// This is called when loading a save state.
1011// Anything could have changed, so invalidate everything.
57871462 1012void invalidate_all_pages()
1013{
1014 u_int page,n;
1015 for(page=0;page<4096;page++)
1016 invalidate_page(page);
1017 for(page=0;page<1048576;page++)
1018 if(!invalid_code[page]) {
1019 restore_candidate[(page&2047)>>3]|=1<<(page&7);
1020 restore_candidate[((page&2047)>>3)+256]|=1<<(page&7);
1021 }
1022 #ifdef __arm__
1023 __clear_cache((void *)BASE_ADDR,(void *)BASE_ADDR+(1<<TARGET_SIZE_2));
1024 #endif
1025 #ifdef USE_MINI_HT
1026 memset(mini_ht,-1,sizeof(mini_ht));
1027 #endif
57871462 1028}
1029
1030// Add an entry to jump_out after making a link
1031void add_link(u_int vaddr,void *src)
1032{
94d23bb9 1033 u_int page=get_page(vaddr);
57871462 1034 inv_debug("add_link: %x -> %x (%d)\n",(int)src,vaddr,page);
76f71c27 1035 int *ptr=(int *)(src+4);
1036 assert((*ptr&0x0fff0000)==0x059f0000);
57871462 1037 ll_add(jump_out+page,vaddr,src);
1038 //int ptr=get_pointer(src);
1039 //inv_debug("add_link: Pointer is to %x\n",(int)ptr);
1040}
1041
1042// If a code block was found to be unmodified (bit was set in
1043// restore_candidate) and it remains unmodified (bit is clear
1044// in invalid_code) then move the entries for that 4K page from
1045// the dirty list to the clean list.
1046void clean_blocks(u_int page)
1047{
1048 struct ll_entry *head;
1049 inv_debug("INV: clean_blocks page=%d\n",page);
1050 head=jump_dirty[page];
1051 while(head!=NULL) {
1052 if(!invalid_code[head->vaddr>>12]) {
1053 // Don't restore blocks which are about to expire from the cache
1054 if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2))) {
1055 u_int start,end;
1056 if(verify_dirty((int)head->addr)) {
1057 //printf("Possibly Restore %x (%x)\n",head->vaddr, (int)head->addr);
1058 u_int i;
1059 u_int inv=0;
1060 get_bounds((int)head->addr,&start,&end);
4cb76aa4 1061 if(start-(u_int)rdram<RAM_SIZE) {
57871462 1062 for(i=(start-(u_int)rdram+0x80000000)>>12;i<=(end-1-(u_int)rdram+0x80000000)>>12;i++) {
1063 inv|=invalid_code[i];
1064 }
1065 }
4cb76aa4 1066 else if((signed int)head->vaddr>=(signed int)0x80000000+RAM_SIZE) {
57871462 1067 inv=1;
1068 }
1069 if(!inv) {
1070 void * clean_addr=(void *)get_clean_addr((int)head->addr);
1071 if((((u_int)clean_addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2))) {
1072 u_int ppage=page;
57871462 1073 inv_debug("INV: Restored %x (%x/%x)\n",head->vaddr, (int)head->addr, (int)clean_addr);
1074 //printf("page=%x, addr=%x\n",page,head->vaddr);
1075 //assert(head->vaddr>>12==(page|0x80000));
de5a60c3 1076 ll_add_flags(jump_in+ppage,head->vaddr,head->reg_sv_flags,clean_addr);
57871462 1077 int *ht_bin=hash_table[((head->vaddr>>16)^head->vaddr)&0xFFFF];
de5a60c3 1078 if(ht_bin[0]==head->vaddr) {
1079 ht_bin[1]=(int)clean_addr; // Replace existing entry
1080 }
1081 if(ht_bin[2]==head->vaddr) {
1082 ht_bin[3]=(int)clean_addr; // Replace existing entry
57871462 1083 }
1084 }
1085 }
1086 }
1087 }
1088 }
1089 head=head->next;
1090 }
1091}
1092
1093
1094void mov_alloc(struct regstat *current,int i)
1095{
1096 // Note: Don't need to actually alloc the source registers
1097 if((~current->is32>>rs1[i])&1) {
1098 //alloc_reg64(current,i,rs1[i]);
1099 alloc_reg64(current,i,rt1[i]);
1100 current->is32&=~(1LL<<rt1[i]);
1101 } else {
1102 //alloc_reg(current,i,rs1[i]);
1103 alloc_reg(current,i,rt1[i]);
1104 current->is32|=(1LL<<rt1[i]);
1105 }
1106 clear_const(current,rs1[i]);
1107 clear_const(current,rt1[i]);
1108 dirty_reg(current,rt1[i]);
1109}
1110
1111void shiftimm_alloc(struct regstat *current,int i)
1112{
57871462 1113 if(opcode2[i]<=0x3) // SLL/SRL/SRA
1114 {
1115 if(rt1[i]) {
1116 if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1117 else lt1[i]=rs1[i];
1118 alloc_reg(current,i,rt1[i]);
1119 current->is32|=1LL<<rt1[i];
1120 dirty_reg(current,rt1[i]);
dc49e339 1121 if(is_const(current,rs1[i])) {
1122 int v=get_const(current,rs1[i]);
1123 if(opcode2[i]==0x00) set_const(current,rt1[i],v<<imm[i]);
1124 if(opcode2[i]==0x02) set_const(current,rt1[i],(u_int)v>>imm[i]);
1125 if(opcode2[i]==0x03) set_const(current,rt1[i],v>>imm[i]);
1126 }
1127 else clear_const(current,rt1[i]);
57871462 1128 }
1129 }
dc49e339 1130 else
1131 {
1132 clear_const(current,rs1[i]);
1133 clear_const(current,rt1[i]);
1134 }
1135
57871462 1136 if(opcode2[i]>=0x38&&opcode2[i]<=0x3b) // DSLL/DSRL/DSRA
1137 {
1138 if(rt1[i]) {
1139 if(rs1[i]) alloc_reg64(current,i,rs1[i]);
1140 alloc_reg64(current,i,rt1[i]);
1141 current->is32&=~(1LL<<rt1[i]);
1142 dirty_reg(current,rt1[i]);
1143 }
1144 }
1145 if(opcode2[i]==0x3c) // DSLL32
1146 {
1147 if(rt1[i]) {
1148 if(rs1[i]) alloc_reg(current,i,rs1[i]);
1149 alloc_reg64(current,i,rt1[i]);
1150 current->is32&=~(1LL<<rt1[i]);
1151 dirty_reg(current,rt1[i]);
1152 }
1153 }
1154 if(opcode2[i]==0x3e) // DSRL32
1155 {
1156 if(rt1[i]) {
1157 alloc_reg64(current,i,rs1[i]);
1158 if(imm[i]==32) {
1159 alloc_reg64(current,i,rt1[i]);
1160 current->is32&=~(1LL<<rt1[i]);
1161 } else {
1162 alloc_reg(current,i,rt1[i]);
1163 current->is32|=1LL<<rt1[i];
1164 }
1165 dirty_reg(current,rt1[i]);
1166 }
1167 }
1168 if(opcode2[i]==0x3f) // DSRA32
1169 {
1170 if(rt1[i]) {
1171 alloc_reg64(current,i,rs1[i]);
1172 alloc_reg(current,i,rt1[i]);
1173 current->is32|=1LL<<rt1[i];
1174 dirty_reg(current,rt1[i]);
1175 }
1176 }
1177}
1178
1179void shift_alloc(struct regstat *current,int i)
1180{
1181 if(rt1[i]) {
1182 if(opcode2[i]<=0x07) // SLLV/SRLV/SRAV
1183 {
1184 if(rs1[i]) alloc_reg(current,i,rs1[i]);
1185 if(rs2[i]) alloc_reg(current,i,rs2[i]);
1186 alloc_reg(current,i,rt1[i]);
e1190b87 1187 if(rt1[i]==rs2[i]) {
1188 alloc_reg_temp(current,i,-1);
1189 minimum_free_regs[i]=1;
1190 }
57871462 1191 current->is32|=1LL<<rt1[i];
1192 } else { // DSLLV/DSRLV/DSRAV
1193 if(rs1[i]) alloc_reg64(current,i,rs1[i]);
1194 if(rs2[i]) alloc_reg(current,i,rs2[i]);
1195 alloc_reg64(current,i,rt1[i]);
1196 current->is32&=~(1LL<<rt1[i]);
1197 if(opcode2[i]==0x16||opcode2[i]==0x17) // DSRLV and DSRAV need a temporary register
e1190b87 1198 {
57871462 1199 alloc_reg_temp(current,i,-1);
e1190b87 1200 minimum_free_regs[i]=1;
1201 }
57871462 1202 }
1203 clear_const(current,rs1[i]);
1204 clear_const(current,rs2[i]);
1205 clear_const(current,rt1[i]);
1206 dirty_reg(current,rt1[i]);
1207 }
1208}
1209
1210void alu_alloc(struct regstat *current,int i)
1211{
1212 if(opcode2[i]>=0x20&&opcode2[i]<=0x23) { // ADD/ADDU/SUB/SUBU
1213 if(rt1[i]) {
1214 if(rs1[i]&&rs2[i]) {
1215 alloc_reg(current,i,rs1[i]);
1216 alloc_reg(current,i,rs2[i]);
1217 }
1218 else {
1219 if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1220 if(rs2[i]&&needed_again(rs2[i],i)) alloc_reg(current,i,rs2[i]);
1221 }
1222 alloc_reg(current,i,rt1[i]);
1223 }
1224 current->is32|=1LL<<rt1[i];
1225 }
1226 if(opcode2[i]==0x2a||opcode2[i]==0x2b) { // SLT/SLTU
1227 if(rt1[i]) {
1228 if(!((current->is32>>rs1[i])&(current->is32>>rs2[i])&1))
1229 {
1230 alloc_reg64(current,i,rs1[i]);
1231 alloc_reg64(current,i,rs2[i]);
1232 alloc_reg(current,i,rt1[i]);
1233 } else {
1234 alloc_reg(current,i,rs1[i]);
1235 alloc_reg(current,i,rs2[i]);
1236 alloc_reg(current,i,rt1[i]);
1237 }
1238 }
1239 current->is32|=1LL<<rt1[i];
1240 }
1241 if(opcode2[i]>=0x24&&opcode2[i]<=0x27) { // AND/OR/XOR/NOR
1242 if(rt1[i]) {
1243 if(rs1[i]&&rs2[i]) {
1244 alloc_reg(current,i,rs1[i]);
1245 alloc_reg(current,i,rs2[i]);
1246 }
1247 else
1248 {
1249 if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1250 if(rs2[i]&&needed_again(rs2[i],i)) alloc_reg(current,i,rs2[i]);
1251 }
1252 alloc_reg(current,i,rt1[i]);
1253 if(!((current->is32>>rs1[i])&(current->is32>>rs2[i])&1))
1254 {
1255 if(!((current->uu>>rt1[i])&1)) {
1256 alloc_reg64(current,i,rt1[i]);
1257 }
1258 if(get_reg(current->regmap,rt1[i]|64)>=0) {
1259 if(rs1[i]&&rs2[i]) {
1260 alloc_reg64(current,i,rs1[i]);
1261 alloc_reg64(current,i,rs2[i]);
1262 }
1263 else
1264 {
1265 // Is is really worth it to keep 64-bit values in registers?
1266 #ifdef NATIVE_64BIT
1267 if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg64(current,i,rs1[i]);
1268 if(rs2[i]&&needed_again(rs2[i],i)) alloc_reg64(current,i,rs2[i]);
1269 #endif
1270 }
1271 }
1272 current->is32&=~(1LL<<rt1[i]);
1273 } else {
1274 current->is32|=1LL<<rt1[i];
1275 }
1276 }
1277 }
1278 if(opcode2[i]>=0x2c&&opcode2[i]<=0x2f) { // DADD/DADDU/DSUB/DSUBU
1279 if(rt1[i]) {
1280 if(rs1[i]&&rs2[i]) {
1281 if(!((current->uu>>rt1[i])&1)||get_reg(current->regmap,rt1[i]|64)>=0) {
1282 alloc_reg64(current,i,rs1[i]);
1283 alloc_reg64(current,i,rs2[i]);
1284 alloc_reg64(current,i,rt1[i]);
1285 } else {
1286 alloc_reg(current,i,rs1[i]);
1287 alloc_reg(current,i,rs2[i]);
1288 alloc_reg(current,i,rt1[i]);
1289 }
1290 }
1291 else {
1292 alloc_reg(current,i,rt1[i]);
1293 if(!((current->uu>>rt1[i])&1)||get_reg(current->regmap,rt1[i]|64)>=0) {
1294 // DADD used as move, or zeroing
1295 // If we have a 64-bit source, then make the target 64 bits too
1296 if(rs1[i]&&!((current->is32>>rs1[i])&1)) {
1297 if(get_reg(current->regmap,rs1[i])>=0) alloc_reg64(current,i,rs1[i]);
1298 alloc_reg64(current,i,rt1[i]);
1299 } else if(rs2[i]&&!((current->is32>>rs2[i])&1)) {
1300 if(get_reg(current->regmap,rs2[i])>=0) alloc_reg64(current,i,rs2[i]);
1301 alloc_reg64(current,i,rt1[i]);
1302 }
1303 if(opcode2[i]>=0x2e&&rs2[i]) {
1304 // DSUB used as negation - 64-bit result
1305 // If we have a 32-bit register, extend it to 64 bits
1306 if(get_reg(current->regmap,rs2[i])>=0) alloc_reg64(current,i,rs2[i]);
1307 alloc_reg64(current,i,rt1[i]);
1308 }
1309 }
1310 }
1311 if(rs1[i]&&rs2[i]) {
1312 current->is32&=~(1LL<<rt1[i]);
1313 } else if(rs1[i]) {
1314 current->is32&=~(1LL<<rt1[i]);
1315 if((current->is32>>rs1[i])&1)
1316 current->is32|=1LL<<rt1[i];
1317 } else if(rs2[i]) {
1318 current->is32&=~(1LL<<rt1[i]);
1319 if((current->is32>>rs2[i])&1)
1320 current->is32|=1LL<<rt1[i];
1321 } else {
1322 current->is32|=1LL<<rt1[i];
1323 }
1324 }
1325 }
1326 clear_const(current,rs1[i]);
1327 clear_const(current,rs2[i]);
1328 clear_const(current,rt1[i]);
1329 dirty_reg(current,rt1[i]);
1330}
1331
1332void imm16_alloc(struct regstat *current,int i)
1333{
1334 if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1335 else lt1[i]=rs1[i];
1336 if(rt1[i]) alloc_reg(current,i,rt1[i]);
1337 if(opcode[i]==0x18||opcode[i]==0x19) { // DADDI/DADDIU
1338 current->is32&=~(1LL<<rt1[i]);
1339 if(!((current->uu>>rt1[i])&1)||get_reg(current->regmap,rt1[i]|64)>=0) {
1340 // TODO: Could preserve the 32-bit flag if the immediate is zero
1341 alloc_reg64(current,i,rt1[i]);
1342 alloc_reg64(current,i,rs1[i]);
1343 }
1344 clear_const(current,rs1[i]);
1345 clear_const(current,rt1[i]);
1346 }
1347 else if(opcode[i]==0x0a||opcode[i]==0x0b) { // SLTI/SLTIU
1348 if((~current->is32>>rs1[i])&1) alloc_reg64(current,i,rs1[i]);
1349 current->is32|=1LL<<rt1[i];
1350 clear_const(current,rs1[i]);
1351 clear_const(current,rt1[i]);
1352 }
1353 else if(opcode[i]>=0x0c&&opcode[i]<=0x0e) { // ANDI/ORI/XORI
1354 if(((~current->is32>>rs1[i])&1)&&opcode[i]>0x0c) {
1355 if(rs1[i]!=rt1[i]) {
1356 if(needed_again(rs1[i],i)) alloc_reg64(current,i,rs1[i]);
1357 alloc_reg64(current,i,rt1[i]);
1358 current->is32&=~(1LL<<rt1[i]);
1359 }
1360 }
1361 else current->is32|=1LL<<rt1[i]; // ANDI clears upper bits
1362 if(is_const(current,rs1[i])) {
1363 int v=get_const(current,rs1[i]);
1364 if(opcode[i]==0x0c) set_const(current,rt1[i],v&imm[i]);
1365 if(opcode[i]==0x0d) set_const(current,rt1[i],v|imm[i]);
1366 if(opcode[i]==0x0e) set_const(current,rt1[i],v^imm[i]);
1367 }
1368 else clear_const(current,rt1[i]);
1369 }
1370 else if(opcode[i]==0x08||opcode[i]==0x09) { // ADDI/ADDIU
1371 if(is_const(current,rs1[i])) {
1372 int v=get_const(current,rs1[i]);
1373 set_const(current,rt1[i],v+imm[i]);
1374 }
1375 else clear_const(current,rt1[i]);
1376 current->is32|=1LL<<rt1[i];
1377 }
1378 else {
1379 set_const(current,rt1[i],((long long)((short)imm[i]))<<16); // LUI
1380 current->is32|=1LL<<rt1[i];
1381 }
1382 dirty_reg(current,rt1[i]);
1383}
1384
1385void load_alloc(struct regstat *current,int i)
1386{
1387 clear_const(current,rt1[i]);
1388 //if(rs1[i]!=rt1[i]&&needed_again(rs1[i],i)) clear_const(current,rs1[i]); // Does this help or hurt?
1389 if(!rs1[i]) current->u&=~1LL; // Allow allocating r0 if it's the source register
1390 if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
373d1d07 1391 if(rt1[i]&&!((current->u>>rt1[i])&1)) {
57871462 1392 alloc_reg(current,i,rt1[i]);
373d1d07 1393 assert(get_reg(current->regmap,rt1[i])>=0);
57871462 1394 if(opcode[i]==0x27||opcode[i]==0x37) // LWU/LD
1395 {
1396 current->is32&=~(1LL<<rt1[i]);
1397 alloc_reg64(current,i,rt1[i]);
1398 }
1399 else if(opcode[i]==0x1A||opcode[i]==0x1B) // LDL/LDR
1400 {
1401 current->is32&=~(1LL<<rt1[i]);
1402 alloc_reg64(current,i,rt1[i]);
1403 alloc_all(current,i);
1404 alloc_reg64(current,i,FTEMP);
e1190b87 1405 minimum_free_regs[i]=HOST_REGS;
57871462 1406 }
1407 else current->is32|=1LL<<rt1[i];
1408 dirty_reg(current,rt1[i]);
1409 // If using TLB, need a register for pointer to the mapping table
1410 if(using_tlb) alloc_reg(current,i,TLREG);
1411 // LWL/LWR need a temporary register for the old value
1412 if(opcode[i]==0x22||opcode[i]==0x26)
1413 {
1414 alloc_reg(current,i,FTEMP);
1415 alloc_reg_temp(current,i,-1);
e1190b87 1416 minimum_free_regs[i]=1;
57871462 1417 }
1418 }
1419 else
1420 {
373d1d07 1421 // Load to r0 or unneeded register (dummy load)
57871462 1422 // but we still need a register to calculate the address
535d208a 1423 if(opcode[i]==0x22||opcode[i]==0x26)
1424 {
1425 alloc_reg(current,i,FTEMP); // LWL/LWR need another temporary
1426 }
373d1d07 1427 // If using TLB, need a register for pointer to the mapping table
1428 if(using_tlb) alloc_reg(current,i,TLREG);
57871462 1429 alloc_reg_temp(current,i,-1);
e1190b87 1430 minimum_free_regs[i]=1;
535d208a 1431 if(opcode[i]==0x1A||opcode[i]==0x1B) // LDL/LDR
1432 {
1433 alloc_all(current,i);
1434 alloc_reg64(current,i,FTEMP);
e1190b87 1435 minimum_free_regs[i]=HOST_REGS;
535d208a 1436 }
57871462 1437 }
1438}
1439
1440void store_alloc(struct regstat *current,int i)
1441{
1442 clear_const(current,rs2[i]);
1443 if(!(rs2[i])) current->u&=~1LL; // Allow allocating r0 if necessary
1444 if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1445 alloc_reg(current,i,rs2[i]);
1446 if(opcode[i]==0x2c||opcode[i]==0x2d||opcode[i]==0x3f) { // 64-bit SDL/SDR/SD
1447 alloc_reg64(current,i,rs2[i]);
1448 if(rs2[i]) alloc_reg(current,i,FTEMP);
1449 }
1450 // If using TLB, need a register for pointer to the mapping table
1451 if(using_tlb) alloc_reg(current,i,TLREG);
1452 #if defined(HOST_IMM8)
1453 // On CPUs without 32-bit immediates we need a pointer to invalid_code
1454 else alloc_reg(current,i,INVCP);
1455 #endif
b7918751 1456 if(opcode[i]==0x2a||opcode[i]==0x2e||opcode[i]==0x2c||opcode[i]==0x2d) { // SWL/SWL/SDL/SDR
57871462 1457 alloc_reg(current,i,FTEMP);
1458 }
1459 // We need a temporary register for address generation
1460 alloc_reg_temp(current,i,-1);
e1190b87 1461 minimum_free_regs[i]=1;
57871462 1462}
1463
1464void c1ls_alloc(struct regstat *current,int i)
1465{
1466 //clear_const(current,rs1[i]); // FIXME
1467 clear_const(current,rt1[i]);
1468 if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1469 alloc_reg(current,i,CSREG); // Status
1470 alloc_reg(current,i,FTEMP);
1471 if(opcode[i]==0x35||opcode[i]==0x3d) { // 64-bit LDC1/SDC1
1472 alloc_reg64(current,i,FTEMP);
1473 }
1474 // If using TLB, need a register for pointer to the mapping table
1475 if(using_tlb) alloc_reg(current,i,TLREG);
1476 #if defined(HOST_IMM8)
1477 // On CPUs without 32-bit immediates we need a pointer to invalid_code
1478 else if((opcode[i]&0x3b)==0x39) // SWC1/SDC1
1479 alloc_reg(current,i,INVCP);
1480 #endif
1481 // We need a temporary register for address generation
1482 alloc_reg_temp(current,i,-1);
1483}
1484
b9b61529 1485void c2ls_alloc(struct regstat *current,int i)
1486{
1487 clear_const(current,rt1[i]);
1488 if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1489 alloc_reg(current,i,FTEMP);
1490 // If using TLB, need a register for pointer to the mapping table
1491 if(using_tlb) alloc_reg(current,i,TLREG);
1492 #if defined(HOST_IMM8)
1493 // On CPUs without 32-bit immediates we need a pointer to invalid_code
1494 else if((opcode[i]&0x3b)==0x3a) // SWC2/SDC2
1495 alloc_reg(current,i,INVCP);
1496 #endif
1497 // We need a temporary register for address generation
1498 alloc_reg_temp(current,i,-1);
e1190b87 1499 minimum_free_regs[i]=1;
b9b61529 1500}
1501
57871462 1502#ifndef multdiv_alloc
1503void multdiv_alloc(struct regstat *current,int i)
1504{
1505 // case 0x18: MULT
1506 // case 0x19: MULTU
1507 // case 0x1A: DIV
1508 // case 0x1B: DIVU
1509 // case 0x1C: DMULT
1510 // case 0x1D: DMULTU
1511 // case 0x1E: DDIV
1512 // case 0x1F: DDIVU
1513 clear_const(current,rs1[i]);
1514 clear_const(current,rs2[i]);
1515 if(rs1[i]&&rs2[i])
1516 {
1517 if((opcode2[i]&4)==0) // 32-bit
1518 {
1519 current->u&=~(1LL<<HIREG);
1520 current->u&=~(1LL<<LOREG);
1521 alloc_reg(current,i,HIREG);
1522 alloc_reg(current,i,LOREG);
1523 alloc_reg(current,i,rs1[i]);
1524 alloc_reg(current,i,rs2[i]);
1525 current->is32|=1LL<<HIREG;
1526 current->is32|=1LL<<LOREG;
1527 dirty_reg(current,HIREG);
1528 dirty_reg(current,LOREG);
1529 }
1530 else // 64-bit
1531 {
1532 current->u&=~(1LL<<HIREG);
1533 current->u&=~(1LL<<LOREG);
1534 current->uu&=~(1LL<<HIREG);
1535 current->uu&=~(1LL<<LOREG);
1536 alloc_reg64(current,i,HIREG);
1537 //if(HOST_REGS>10) alloc_reg64(current,i,LOREG);
1538 alloc_reg64(current,i,rs1[i]);
1539 alloc_reg64(current,i,rs2[i]);
1540 alloc_all(current,i);
1541 current->is32&=~(1LL<<HIREG);
1542 current->is32&=~(1LL<<LOREG);
1543 dirty_reg(current,HIREG);
1544 dirty_reg(current,LOREG);
e1190b87 1545 minimum_free_regs[i]=HOST_REGS;
57871462 1546 }
1547 }
1548 else
1549 {
1550 // Multiply by zero is zero.
1551 // MIPS does not have a divide by zero exception.
1552 // The result is undefined, we return zero.
1553 alloc_reg(current,i,HIREG);
1554 alloc_reg(current,i,LOREG);
1555 current->is32|=1LL<<HIREG;
1556 current->is32|=1LL<<LOREG;
1557 dirty_reg(current,HIREG);
1558 dirty_reg(current,LOREG);
1559 }
1560}
1561#endif
1562
1563void cop0_alloc(struct regstat *current,int i)
1564{
1565 if(opcode2[i]==0) // MFC0
1566 {
1567 if(rt1[i]) {
1568 clear_const(current,rt1[i]);
1569 alloc_all(current,i);
1570 alloc_reg(current,i,rt1[i]);
1571 current->is32|=1LL<<rt1[i];
1572 dirty_reg(current,rt1[i]);
1573 }
1574 }
1575 else if(opcode2[i]==4) // MTC0
1576 {
1577 if(rs1[i]){
1578 clear_const(current,rs1[i]);
1579 alloc_reg(current,i,rs1[i]);
1580 alloc_all(current,i);
1581 }
1582 else {
1583 alloc_all(current,i); // FIXME: Keep r0
1584 current->u&=~1LL;
1585 alloc_reg(current,i,0);
1586 }
1587 }
1588 else
1589 {
1590 // TLBR/TLBWI/TLBWR/TLBP/ERET
1591 assert(opcode2[i]==0x10);
1592 alloc_all(current,i);
1593 }
e1190b87 1594 minimum_free_regs[i]=HOST_REGS;
57871462 1595}
1596
1597void cop1_alloc(struct regstat *current,int i)
1598{
1599 alloc_reg(current,i,CSREG); // Load status
1600 if(opcode2[i]<3) // MFC1/DMFC1/CFC1
1601 {
7de557a6 1602 if(rt1[i]){
1603 clear_const(current,rt1[i]);
1604 if(opcode2[i]==1) {
1605 alloc_reg64(current,i,rt1[i]); // DMFC1
1606 current->is32&=~(1LL<<rt1[i]);
1607 }else{
1608 alloc_reg(current,i,rt1[i]); // MFC1/CFC1
1609 current->is32|=1LL<<rt1[i];
1610 }
1611 dirty_reg(current,rt1[i]);
57871462 1612 }
57871462 1613 alloc_reg_temp(current,i,-1);
1614 }
1615 else if(opcode2[i]>3) // MTC1/DMTC1/CTC1
1616 {
1617 if(rs1[i]){
1618 clear_const(current,rs1[i]);
1619 if(opcode2[i]==5)
1620 alloc_reg64(current,i,rs1[i]); // DMTC1
1621 else
1622 alloc_reg(current,i,rs1[i]); // MTC1/CTC1
1623 alloc_reg_temp(current,i,-1);
1624 }
1625 else {
1626 current->u&=~1LL;
1627 alloc_reg(current,i,0);
1628 alloc_reg_temp(current,i,-1);
1629 }
1630 }
e1190b87 1631 minimum_free_regs[i]=1;
57871462 1632}
1633void fconv_alloc(struct regstat *current,int i)
1634{
1635 alloc_reg(current,i,CSREG); // Load status
1636 alloc_reg_temp(current,i,-1);
e1190b87 1637 minimum_free_regs[i]=1;
57871462 1638}
1639void float_alloc(struct regstat *current,int i)
1640{
1641 alloc_reg(current,i,CSREG); // Load status
1642 alloc_reg_temp(current,i,-1);
e1190b87 1643 minimum_free_regs[i]=1;
57871462 1644}
b9b61529 1645void c2op_alloc(struct regstat *current,int i)
1646{
1647 alloc_reg_temp(current,i,-1);
1648}
57871462 1649void fcomp_alloc(struct regstat *current,int i)
1650{
1651 alloc_reg(current,i,CSREG); // Load status
1652 alloc_reg(current,i,FSREG); // Load flags
1653 dirty_reg(current,FSREG); // Flag will be modified
1654 alloc_reg_temp(current,i,-1);
e1190b87 1655 minimum_free_regs[i]=1;
57871462 1656}
1657
1658void syscall_alloc(struct regstat *current,int i)
1659{
1660 alloc_cc(current,i);
1661 dirty_reg(current,CCREG);
1662 alloc_all(current,i);
e1190b87 1663 minimum_free_regs[i]=HOST_REGS;
57871462 1664 current->isconst=0;
1665}
1666
1667void delayslot_alloc(struct regstat *current,int i)
1668{
1669 switch(itype[i]) {
1670 case UJUMP:
1671 case CJUMP:
1672 case SJUMP:
1673 case RJUMP:
1674 case FJUMP:
1675 case SYSCALL:
7139f3c8 1676 case HLECALL:
57871462 1677 case SPAN:
1678 assem_debug("jump in the delay slot. this shouldn't happen.\n");//exit(1);
c43b5311 1679 SysPrintf("Disabled speculative precompilation\n");
57871462 1680 stop_after_jal=1;
1681 break;
1682 case IMM16:
1683 imm16_alloc(current,i);
1684 break;
1685 case LOAD:
1686 case LOADLR:
1687 load_alloc(current,i);
1688 break;
1689 case STORE:
1690 case STORELR:
1691 store_alloc(current,i);
1692 break;
1693 case ALU:
1694 alu_alloc(current,i);
1695 break;
1696 case SHIFT:
1697 shift_alloc(current,i);
1698 break;
1699 case MULTDIV:
1700 multdiv_alloc(current,i);
1701 break;
1702 case SHIFTIMM:
1703 shiftimm_alloc(current,i);
1704 break;
1705 case MOV:
1706 mov_alloc(current,i);
1707 break;
1708 case COP0:
1709 cop0_alloc(current,i);
1710 break;
1711 case COP1:
b9b61529 1712 case COP2:
57871462 1713 cop1_alloc(current,i);
1714 break;
1715 case C1LS:
1716 c1ls_alloc(current,i);
1717 break;
b9b61529 1718 case C2LS:
1719 c2ls_alloc(current,i);
1720 break;
57871462 1721 case FCONV:
1722 fconv_alloc(current,i);
1723 break;
1724 case FLOAT:
1725 float_alloc(current,i);
1726 break;
1727 case FCOMP:
1728 fcomp_alloc(current,i);
1729 break;
b9b61529 1730 case C2OP:
1731 c2op_alloc(current,i);
1732 break;
57871462 1733 }
1734}
1735
1736// Special case where a branch and delay slot span two pages in virtual memory
1737static void pagespan_alloc(struct regstat *current,int i)
1738{
1739 current->isconst=0;
1740 current->wasconst=0;
1741 regs[i].wasconst=0;
e1190b87 1742 minimum_free_regs[i]=HOST_REGS;
57871462 1743 alloc_all(current,i);
1744 alloc_cc(current,i);
1745 dirty_reg(current,CCREG);
1746 if(opcode[i]==3) // JAL
1747 {
1748 alloc_reg(current,i,31);
1749 dirty_reg(current,31);
1750 }
1751 if(opcode[i]==0&&(opcode2[i]&0x3E)==8) // JR/JALR
1752 {
1753 alloc_reg(current,i,rs1[i]);
5067f341 1754 if (rt1[i]!=0) {
1755 alloc_reg(current,i,rt1[i]);
1756 dirty_reg(current,rt1[i]);
57871462 1757 }
1758 }
1759 if((opcode[i]&0x2E)==4) // BEQ/BNE/BEQL/BNEL
1760 {
1761 if(rs1[i]) alloc_reg(current,i,rs1[i]);
1762 if(rs2[i]) alloc_reg(current,i,rs2[i]);
1763 if(!((current->is32>>rs1[i])&(current->is32>>rs2[i])&1))
1764 {
1765 if(rs1[i]) alloc_reg64(current,i,rs1[i]);
1766 if(rs2[i]) alloc_reg64(current,i,rs2[i]);
1767 }
1768 }
1769 else
1770 if((opcode[i]&0x2E)==6) // BLEZ/BGTZ/BLEZL/BGTZL
1771 {
1772 if(rs1[i]) alloc_reg(current,i,rs1[i]);
1773 if(!((current->is32>>rs1[i])&1))
1774 {
1775 if(rs1[i]) alloc_reg64(current,i,rs1[i]);
1776 }
1777 }
1778 else
1779 if(opcode[i]==0x11) // BC1
1780 {
1781 alloc_reg(current,i,FSREG);
1782 alloc_reg(current,i,CSREG);
1783 }
1784 //else ...
1785}
1786
1787add_stub(int type,int addr,int retaddr,int a,int b,int c,int d,int e)
1788{
1789 stubs[stubcount][0]=type;
1790 stubs[stubcount][1]=addr;
1791 stubs[stubcount][2]=retaddr;
1792 stubs[stubcount][3]=a;
1793 stubs[stubcount][4]=b;
1794 stubs[stubcount][5]=c;
1795 stubs[stubcount][6]=d;
1796 stubs[stubcount][7]=e;
1797 stubcount++;
1798}
1799
1800// Write out a single register
1801void wb_register(signed char r,signed char regmap[],uint64_t dirty,uint64_t is32)
1802{
1803 int hr;
1804 for(hr=0;hr<HOST_REGS;hr++) {
1805 if(hr!=EXCLUDE_REG) {
1806 if((regmap[hr]&63)==r) {
1807 if((dirty>>hr)&1) {
1808 if(regmap[hr]<64) {
1809 emit_storereg(r,hr);
57871462 1810 }else{
1811 emit_storereg(r|64,hr);
1812 }
1813 }
1814 }
1815 }
1816 }
1817}
1818
1819int mchecksum()
1820{
1821 //if(!tracedebug) return 0;
1822 int i;
1823 int sum=0;
1824 for(i=0;i<2097152;i++) {
1825 unsigned int temp=sum;
1826 sum<<=1;
1827 sum|=(~temp)>>31;
1828 sum^=((u_int *)rdram)[i];
1829 }
1830 return sum;
1831}
1832int rchecksum()
1833{
1834 int i;
1835 int sum=0;
1836 for(i=0;i<64;i++)
1837 sum^=((u_int *)reg)[i];
1838 return sum;
1839}
57871462 1840void rlist()
1841{
1842 int i;
1843 printf("TRACE: ");
1844 for(i=0;i<32;i++)
1845 printf("r%d:%8x%8x ",i,((int *)(reg+i))[1],((int *)(reg+i))[0]);
1846 printf("\n");
57871462 1847}
1848
1849void enabletrace()
1850{
1851 tracedebug=1;
1852}
1853
1854void memdebug(int i)
1855{
1856 //printf("TRACE: count=%d next=%d (checksum %x) lo=%8x%8x\n",Count,next_interupt,mchecksum(),(int)(reg[LOREG]>>32),(int)reg[LOREG]);
1857 //printf("TRACE: count=%d next=%d (rchecksum %x)\n",Count,next_interupt,rchecksum());
1858 //rlist();
1859 //if(tracedebug) {
1860 //if(Count>=-2084597794) {
1861 if((signed int)Count>=-2084597794&&(signed int)Count<0) {
1862 //if(0) {
1863 printf("TRACE: count=%d next=%d (checksum %x)\n",Count,next_interupt,mchecksum());
1864 //printf("TRACE: count=%d next=%d (checksum %x) Status=%x\n",Count,next_interupt,mchecksum(),Status);
1865 //printf("TRACE: count=%d next=%d (checksum %x) hi=%8x%8x\n",Count,next_interupt,mchecksum(),(int)(reg[HIREG]>>32),(int)reg[HIREG]);
1866 rlist();
1867 #ifdef __i386__
1868 printf("TRACE: %x\n",(&i)[-1]);
1869 #endif
1870 #ifdef __arm__
1871 int j;
1872 printf("TRACE: %x \n",(&j)[10]);
1873 printf("TRACE: %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x\n",(&j)[1],(&j)[2],(&j)[3],(&j)[4],(&j)[5],(&j)[6],(&j)[7],(&j)[8],(&j)[9],(&j)[10],(&j)[11],(&j)[12],(&j)[13],(&j)[14],(&j)[15],(&j)[16],(&j)[17],(&j)[18],(&j)[19],(&j)[20]);
1874 #endif
1875 //fflush(stdout);
1876 }
1877 //printf("TRACE: %x\n",(&i)[-1]);
1878}
1879
1880void tlb_debug(u_int cause, u_int addr, u_int iaddr)
1881{
1882 printf("TLB Exception: instruction=%x addr=%x cause=%x\n",iaddr, addr, cause);
1883}
1884
1885void alu_assemble(int i,struct regstat *i_regs)
1886{
1887 if(opcode2[i]>=0x20&&opcode2[i]<=0x23) { // ADD/ADDU/SUB/SUBU
1888 if(rt1[i]) {
1889 signed char s1,s2,t;
1890 t=get_reg(i_regs->regmap,rt1[i]);
1891 if(t>=0) {
1892 s1=get_reg(i_regs->regmap,rs1[i]);
1893 s2=get_reg(i_regs->regmap,rs2[i]);
1894 if(rs1[i]&&rs2[i]) {
1895 assert(s1>=0);
1896 assert(s2>=0);
1897 if(opcode2[i]&2) emit_sub(s1,s2,t);
1898 else emit_add(s1,s2,t);
1899 }
1900 else if(rs1[i]) {
1901 if(s1>=0) emit_mov(s1,t);
1902 else emit_loadreg(rs1[i],t);
1903 }
1904 else if(rs2[i]) {
1905 if(s2>=0) {
1906 if(opcode2[i]&2) emit_neg(s2,t);
1907 else emit_mov(s2,t);
1908 }
1909 else {
1910 emit_loadreg(rs2[i],t);
1911 if(opcode2[i]&2) emit_neg(t,t);
1912 }
1913 }
1914 else emit_zeroreg(t);
1915 }
1916 }
1917 }
1918 if(opcode2[i]>=0x2c&&opcode2[i]<=0x2f) { // DADD/DADDU/DSUB/DSUBU
1919 if(rt1[i]) {
1920 signed char s1l,s2l,s1h,s2h,tl,th;
1921 tl=get_reg(i_regs->regmap,rt1[i]);
1922 th=get_reg(i_regs->regmap,rt1[i]|64);
1923 if(tl>=0) {
1924 s1l=get_reg(i_regs->regmap,rs1[i]);
1925 s2l=get_reg(i_regs->regmap,rs2[i]);
1926 s1h=get_reg(i_regs->regmap,rs1[i]|64);
1927 s2h=get_reg(i_regs->regmap,rs2[i]|64);
1928 if(rs1[i]&&rs2[i]) {
1929 assert(s1l>=0);
1930 assert(s2l>=0);
1931 if(opcode2[i]&2) emit_subs(s1l,s2l,tl);
1932 else emit_adds(s1l,s2l,tl);
1933 if(th>=0) {
1934 #ifdef INVERTED_CARRY
1935 if(opcode2[i]&2) {if(s1h!=th) emit_mov(s1h,th);emit_sbb(th,s2h);}
1936 #else
1937 if(opcode2[i]&2) emit_sbc(s1h,s2h,th);
1938 #endif
1939 else emit_add(s1h,s2h,th);
1940 }
1941 }
1942 else if(rs1[i]) {
1943 if(s1l>=0) emit_mov(s1l,tl);
1944 else emit_loadreg(rs1[i],tl);
1945 if(th>=0) {
1946 if(s1h>=0) emit_mov(s1h,th);
1947 else emit_loadreg(rs1[i]|64,th);
1948 }
1949 }
1950 else if(rs2[i]) {
1951 if(s2l>=0) {
1952 if(opcode2[i]&2) emit_negs(s2l,tl);
1953 else emit_mov(s2l,tl);
1954 }
1955 else {
1956 emit_loadreg(rs2[i],tl);
1957 if(opcode2[i]&2) emit_negs(tl,tl);
1958 }
1959 if(th>=0) {
1960 #ifdef INVERTED_CARRY
1961 if(s2h>=0) emit_mov(s2h,th);
1962 else emit_loadreg(rs2[i]|64,th);
1963 if(opcode2[i]&2) {
1964 emit_adcimm(-1,th); // x86 has inverted carry flag
1965 emit_not(th,th);
1966 }
1967 #else
1968 if(opcode2[i]&2) {
1969 if(s2h>=0) emit_rscimm(s2h,0,th);
1970 else {
1971 emit_loadreg(rs2[i]|64,th);
1972 emit_rscimm(th,0,th);
1973 }
1974 }else{
1975 if(s2h>=0) emit_mov(s2h,th);
1976 else emit_loadreg(rs2[i]|64,th);
1977 }
1978 #endif
1979 }
1980 }
1981 else {
1982 emit_zeroreg(tl);
1983 if(th>=0) emit_zeroreg(th);
1984 }
1985 }
1986 }
1987 }
1988 if(opcode2[i]==0x2a||opcode2[i]==0x2b) { // SLT/SLTU
1989 if(rt1[i]) {
1990 signed char s1l,s1h,s2l,s2h,t;
1991 if(!((i_regs->was32>>rs1[i])&(i_regs->was32>>rs2[i])&1))
1992 {
1993 t=get_reg(i_regs->regmap,rt1[i]);
1994 //assert(t>=0);
1995 if(t>=0) {
1996 s1l=get_reg(i_regs->regmap,rs1[i]);
1997 s1h=get_reg(i_regs->regmap,rs1[i]|64);
1998 s2l=get_reg(i_regs->regmap,rs2[i]);
1999 s2h=get_reg(i_regs->regmap,rs2[i]|64);
2000 if(rs2[i]==0) // rx<r0
2001 {
2002 assert(s1h>=0);
2003 if(opcode2[i]==0x2a) // SLT
2004 emit_shrimm(s1h,31,t);
2005 else // SLTU (unsigned can not be less than zero)
2006 emit_zeroreg(t);
2007 }
2008 else if(rs1[i]==0) // r0<rx
2009 {
2010 assert(s2h>=0);
2011 if(opcode2[i]==0x2a) // SLT
2012 emit_set_gz64_32(s2h,s2l,t);
2013 else // SLTU (set if not zero)
2014 emit_set_nz64_32(s2h,s2l,t);
2015 }
2016 else {
2017 assert(s1l>=0);assert(s1h>=0);
2018 assert(s2l>=0);assert(s2h>=0);
2019 if(opcode2[i]==0x2a) // SLT
2020 emit_set_if_less64_32(s1h,s1l,s2h,s2l,t);
2021 else // SLTU
2022 emit_set_if_carry64_32(s1h,s1l,s2h,s2l,t);
2023 }
2024 }
2025 } else {
2026 t=get_reg(i_regs->regmap,rt1[i]);
2027 //assert(t>=0);
2028 if(t>=0) {
2029 s1l=get_reg(i_regs->regmap,rs1[i]);
2030 s2l=get_reg(i_regs->regmap,rs2[i]);
2031 if(rs2[i]==0) // rx<r0
2032 {
2033 assert(s1l>=0);
2034 if(opcode2[i]==0x2a) // SLT
2035 emit_shrimm(s1l,31,t);
2036 else // SLTU (unsigned can not be less than zero)
2037 emit_zeroreg(t);
2038 }
2039 else if(rs1[i]==0) // r0<rx
2040 {
2041 assert(s2l>=0);
2042 if(opcode2[i]==0x2a) // SLT
2043 emit_set_gz32(s2l,t);
2044 else // SLTU (set if not zero)
2045 emit_set_nz32(s2l,t);
2046 }
2047 else{
2048 assert(s1l>=0);assert(s2l>=0);
2049 if(opcode2[i]==0x2a) // SLT
2050 emit_set_if_less32(s1l,s2l,t);
2051 else // SLTU
2052 emit_set_if_carry32(s1l,s2l,t);
2053 }
2054 }
2055 }
2056 }
2057 }
2058 if(opcode2[i]>=0x24&&opcode2[i]<=0x27) { // AND/OR/XOR/NOR
2059 if(rt1[i]) {
2060 signed char s1l,s1h,s2l,s2h,th,tl;
2061 tl=get_reg(i_regs->regmap,rt1[i]);
2062 th=get_reg(i_regs->regmap,rt1[i]|64);
2063 if(!((i_regs->was32>>rs1[i])&(i_regs->was32>>rs2[i])&1)&&th>=0)
2064 {
2065 assert(tl>=0);
2066 if(tl>=0) {
2067 s1l=get_reg(i_regs->regmap,rs1[i]);
2068 s1h=get_reg(i_regs->regmap,rs1[i]|64);
2069 s2l=get_reg(i_regs->regmap,rs2[i]);
2070 s2h=get_reg(i_regs->regmap,rs2[i]|64);
2071 if(rs1[i]&&rs2[i]) {
2072 assert(s1l>=0);assert(s1h>=0);
2073 assert(s2l>=0);assert(s2h>=0);
2074 if(opcode2[i]==0x24) { // AND
2075 emit_and(s1l,s2l,tl);
2076 emit_and(s1h,s2h,th);
2077 } else
2078 if(opcode2[i]==0x25) { // OR
2079 emit_or(s1l,s2l,tl);
2080 emit_or(s1h,s2h,th);
2081 } else
2082 if(opcode2[i]==0x26) { // XOR
2083 emit_xor(s1l,s2l,tl);
2084 emit_xor(s1h,s2h,th);
2085 } else
2086 if(opcode2[i]==0x27) { // NOR
2087 emit_or(s1l,s2l,tl);
2088 emit_or(s1h,s2h,th);
2089 emit_not(tl,tl);
2090 emit_not(th,th);
2091 }
2092 }
2093 else
2094 {
2095 if(opcode2[i]==0x24) { // AND
2096 emit_zeroreg(tl);
2097 emit_zeroreg(th);
2098 } else
2099 if(opcode2[i]==0x25||opcode2[i]==0x26) { // OR/XOR
2100 if(rs1[i]){
2101 if(s1l>=0) emit_mov(s1l,tl);
2102 else emit_loadreg(rs1[i],tl);
2103 if(s1h>=0) emit_mov(s1h,th);
2104 else emit_loadreg(rs1[i]|64,th);
2105 }
2106 else
2107 if(rs2[i]){
2108 if(s2l>=0) emit_mov(s2l,tl);
2109 else emit_loadreg(rs2[i],tl);
2110 if(s2h>=0) emit_mov(s2h,th);
2111 else emit_loadreg(rs2[i]|64,th);
2112 }
2113 else{
2114 emit_zeroreg(tl);
2115 emit_zeroreg(th);
2116 }
2117 } else
2118 if(opcode2[i]==0x27) { // NOR
2119 if(rs1[i]){
2120 if(s1l>=0) emit_not(s1l,tl);
2121 else{
2122 emit_loadreg(rs1[i],tl);
2123 emit_not(tl,tl);
2124 }
2125 if(s1h>=0) emit_not(s1h,th);
2126 else{
2127 emit_loadreg(rs1[i]|64,th);
2128 emit_not(th,th);
2129 }
2130 }
2131 else
2132 if(rs2[i]){
2133 if(s2l>=0) emit_not(s2l,tl);
2134 else{
2135 emit_loadreg(rs2[i],tl);
2136 emit_not(tl,tl);
2137 }
2138 if(s2h>=0) emit_not(s2h,th);
2139 else{
2140 emit_loadreg(rs2[i]|64,th);
2141 emit_not(th,th);
2142 }
2143 }
2144 else {
2145 emit_movimm(-1,tl);
2146 emit_movimm(-1,th);
2147 }
2148 }
2149 }
2150 }
2151 }
2152 else
2153 {
2154 // 32 bit
2155 if(tl>=0) {
2156 s1l=get_reg(i_regs->regmap,rs1[i]);
2157 s2l=get_reg(i_regs->regmap,rs2[i]);
2158 if(rs1[i]&&rs2[i]) {
2159 assert(s1l>=0);
2160 assert(s2l>=0);
2161 if(opcode2[i]==0x24) { // AND
2162 emit_and(s1l,s2l,tl);
2163 } else
2164 if(opcode2[i]==0x25) { // OR
2165 emit_or(s1l,s2l,tl);
2166 } else
2167 if(opcode2[i]==0x26) { // XOR
2168 emit_xor(s1l,s2l,tl);
2169 } else
2170 if(opcode2[i]==0x27) { // NOR
2171 emit_or(s1l,s2l,tl);
2172 emit_not(tl,tl);
2173 }
2174 }
2175 else
2176 {
2177 if(opcode2[i]==0x24) { // AND
2178 emit_zeroreg(tl);
2179 } else
2180 if(opcode2[i]==0x25||opcode2[i]==0x26) { // OR/XOR
2181 if(rs1[i]){
2182 if(s1l>=0) emit_mov(s1l,tl);
2183 else emit_loadreg(rs1[i],tl); // CHECK: regmap_entry?
2184 }
2185 else
2186 if(rs2[i]){
2187 if(s2l>=0) emit_mov(s2l,tl);
2188 else emit_loadreg(rs2[i],tl); // CHECK: regmap_entry?
2189 }
2190 else emit_zeroreg(tl);
2191 } else
2192 if(opcode2[i]==0x27) { // NOR
2193 if(rs1[i]){
2194 if(s1l>=0) emit_not(s1l,tl);
2195 else {
2196 emit_loadreg(rs1[i],tl);
2197 emit_not(tl,tl);
2198 }
2199 }
2200 else
2201 if(rs2[i]){
2202 if(s2l>=0) emit_not(s2l,tl);
2203 else {
2204 emit_loadreg(rs2[i],tl);
2205 emit_not(tl,tl);
2206 }
2207 }
2208 else emit_movimm(-1,tl);
2209 }
2210 }
2211 }
2212 }
2213 }
2214 }
2215}
2216
2217void imm16_assemble(int i,struct regstat *i_regs)
2218{
2219 if (opcode[i]==0x0f) { // LUI
2220 if(rt1[i]) {
2221 signed char t;
2222 t=get_reg(i_regs->regmap,rt1[i]);
2223 //assert(t>=0);
2224 if(t>=0) {
2225 if(!((i_regs->isconst>>t)&1))
2226 emit_movimm(imm[i]<<16,t);
2227 }
2228 }
2229 }
2230 if(opcode[i]==0x08||opcode[i]==0x09) { // ADDI/ADDIU
2231 if(rt1[i]) {
2232 signed char s,t;
2233 t=get_reg(i_regs->regmap,rt1[i]);
2234 s=get_reg(i_regs->regmap,rs1[i]);
2235 if(rs1[i]) {
2236 //assert(t>=0);
2237 //assert(s>=0);
2238 if(t>=0) {
2239 if(!((i_regs->isconst>>t)&1)) {
2240 if(s<0) {
2241 if(i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2242 emit_addimm(t,imm[i],t);
2243 }else{
2244 if(!((i_regs->wasconst>>s)&1))
2245 emit_addimm(s,imm[i],t);
2246 else
2247 emit_movimm(constmap[i][s]+imm[i],t);
2248 }
2249 }
2250 }
2251 } else {
2252 if(t>=0) {
2253 if(!((i_regs->isconst>>t)&1))
2254 emit_movimm(imm[i],t);
2255 }
2256 }
2257 }
2258 }
2259 if(opcode[i]==0x18||opcode[i]==0x19) { // DADDI/DADDIU
2260 if(rt1[i]) {
2261 signed char sh,sl,th,tl;
2262 th=get_reg(i_regs->regmap,rt1[i]|64);
2263 tl=get_reg(i_regs->regmap,rt1[i]);
2264 sh=get_reg(i_regs->regmap,rs1[i]|64);
2265 sl=get_reg(i_regs->regmap,rs1[i]);
2266 if(tl>=0) {
2267 if(rs1[i]) {
2268 assert(sh>=0);
2269 assert(sl>=0);
2270 if(th>=0) {
2271 emit_addimm64_32(sh,sl,imm[i],th,tl);
2272 }
2273 else {
2274 emit_addimm(sl,imm[i],tl);
2275 }
2276 } else {
2277 emit_movimm(imm[i],tl);
2278 if(th>=0) emit_movimm(((signed int)imm[i])>>31,th);
2279 }
2280 }
2281 }
2282 }
2283 else if(opcode[i]==0x0a||opcode[i]==0x0b) { // SLTI/SLTIU
2284 if(rt1[i]) {
2285 //assert(rs1[i]!=0); // r0 might be valid, but it's probably a bug
2286 signed char sh,sl,t;
2287 t=get_reg(i_regs->regmap,rt1[i]);
2288 sh=get_reg(i_regs->regmap,rs1[i]|64);
2289 sl=get_reg(i_regs->regmap,rs1[i]);
2290 //assert(t>=0);
2291 if(t>=0) {
2292 if(rs1[i]>0) {
2293 if(sh<0) assert((i_regs->was32>>rs1[i])&1);
2294 if(sh<0||((i_regs->was32>>rs1[i])&1)) {
2295 if(opcode[i]==0x0a) { // SLTI
2296 if(sl<0) {
2297 if(i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2298 emit_slti32(t,imm[i],t);
2299 }else{
2300 emit_slti32(sl,imm[i],t);
2301 }
2302 }
2303 else { // SLTIU
2304 if(sl<0) {
2305 if(i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2306 emit_sltiu32(t,imm[i],t);
2307 }else{
2308 emit_sltiu32(sl,imm[i],t);
2309 }
2310 }
2311 }else{ // 64-bit
2312 assert(sl>=0);
2313 if(opcode[i]==0x0a) // SLTI
2314 emit_slti64_32(sh,sl,imm[i],t);
2315 else // SLTIU
2316 emit_sltiu64_32(sh,sl,imm[i],t);
2317 }
2318 }else{
2319 // SLTI(U) with r0 is just stupid,
2320 // nonetheless examples can be found
2321 if(opcode[i]==0x0a) // SLTI
2322 if(0<imm[i]) emit_movimm(1,t);
2323 else emit_zeroreg(t);
2324 else // SLTIU
2325 {
2326 if(imm[i]) emit_movimm(1,t);
2327 else emit_zeroreg(t);
2328 }
2329 }
2330 }
2331 }
2332 }
2333 else if(opcode[i]>=0x0c&&opcode[i]<=0x0e) { // ANDI/ORI/XORI
2334 if(rt1[i]) {
2335 signed char sh,sl,th,tl;
2336 th=get_reg(i_regs->regmap,rt1[i]|64);
2337 tl=get_reg(i_regs->regmap,rt1[i]);
2338 sh=get_reg(i_regs->regmap,rs1[i]|64);
2339 sl=get_reg(i_regs->regmap,rs1[i]);
2340 if(tl>=0 && !((i_regs->isconst>>tl)&1)) {
2341 if(opcode[i]==0x0c) //ANDI
2342 {
2343 if(rs1[i]) {
2344 if(sl<0) {
2345 if(i_regs->regmap_entry[tl]!=rs1[i]) emit_loadreg(rs1[i],tl);
2346 emit_andimm(tl,imm[i],tl);
2347 }else{
2348 if(!((i_regs->wasconst>>sl)&1))
2349 emit_andimm(sl,imm[i],tl);
2350 else
2351 emit_movimm(constmap[i][sl]&imm[i],tl);
2352 }
2353 }
2354 else
2355 emit_zeroreg(tl);
2356 if(th>=0) emit_zeroreg(th);
2357 }
2358 else
2359 {
2360 if(rs1[i]) {
2361 if(sl<0) {
2362 if(i_regs->regmap_entry[tl]!=rs1[i]) emit_loadreg(rs1[i],tl);
2363 }
2364 if(th>=0) {
2365 if(sh<0) {
2366 emit_loadreg(rs1[i]|64,th);
2367 }else{
2368 emit_mov(sh,th);
2369 }
2370 }
2371 if(opcode[i]==0x0d) //ORI
2372 if(sl<0) {
2373 emit_orimm(tl,imm[i],tl);
2374 }else{
2375 if(!((i_regs->wasconst>>sl)&1))
2376 emit_orimm(sl,imm[i],tl);
2377 else
2378 emit_movimm(constmap[i][sl]|imm[i],tl);
2379 }
2380 if(opcode[i]==0x0e) //XORI
2381 if(sl<0) {
2382 emit_xorimm(tl,imm[i],tl);
2383 }else{
2384 if(!((i_regs->wasconst>>sl)&1))
2385 emit_xorimm(sl,imm[i],tl);
2386 else
2387 emit_movimm(constmap[i][sl]^imm[i],tl);
2388 }
2389 }
2390 else {
2391 emit_movimm(imm[i],tl);
2392 if(th>=0) emit_zeroreg(th);
2393 }
2394 }
2395 }
2396 }
2397 }
2398}
2399
2400void shiftimm_assemble(int i,struct regstat *i_regs)
2401{
2402 if(opcode2[i]<=0x3) // SLL/SRL/SRA
2403 {
2404 if(rt1[i]) {
2405 signed char s,t;
2406 t=get_reg(i_regs->regmap,rt1[i]);
2407 s=get_reg(i_regs->regmap,rs1[i]);
2408 //assert(t>=0);
dc49e339 2409 if(t>=0&&!((i_regs->isconst>>t)&1)){
57871462 2410 if(rs1[i]==0)
2411 {
2412 emit_zeroreg(t);
2413 }
2414 else
2415 {
2416 if(s<0&&i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2417 if(imm[i]) {
2418 if(opcode2[i]==0) // SLL
2419 {
2420 emit_shlimm(s<0?t:s,imm[i],t);
2421 }
2422 if(opcode2[i]==2) // SRL
2423 {
2424 emit_shrimm(s<0?t:s,imm[i],t);
2425 }
2426 if(opcode2[i]==3) // SRA
2427 {
2428 emit_sarimm(s<0?t:s,imm[i],t);
2429 }
2430 }else{
2431 // Shift by zero
2432 if(s>=0 && s!=t) emit_mov(s,t);
2433 }
2434 }
2435 }
2436 //emit_storereg(rt1[i],t); //DEBUG
2437 }
2438 }
2439 if(opcode2[i]>=0x38&&opcode2[i]<=0x3b) // DSLL/DSRL/DSRA
2440 {
2441 if(rt1[i]) {
2442 signed char sh,sl,th,tl;
2443 th=get_reg(i_regs->regmap,rt1[i]|64);
2444 tl=get_reg(i_regs->regmap,rt1[i]);
2445 sh=get_reg(i_regs->regmap,rs1[i]|64);
2446 sl=get_reg(i_regs->regmap,rs1[i]);
2447 if(tl>=0) {
2448 if(rs1[i]==0)
2449 {
2450 emit_zeroreg(tl);
2451 if(th>=0) emit_zeroreg(th);
2452 }
2453 else
2454 {
2455 assert(sl>=0);
2456 assert(sh>=0);
2457 if(imm[i]) {
2458 if(opcode2[i]==0x38) // DSLL
2459 {
2460 if(th>=0) emit_shldimm(sh,sl,imm[i],th);
2461 emit_shlimm(sl,imm[i],tl);
2462 }
2463 if(opcode2[i]==0x3a) // DSRL
2464 {
2465 emit_shrdimm(sl,sh,imm[i],tl);
2466 if(th>=0) emit_shrimm(sh,imm[i],th);
2467 }
2468 if(opcode2[i]==0x3b) // DSRA
2469 {
2470 emit_shrdimm(sl,sh,imm[i],tl);
2471 if(th>=0) emit_sarimm(sh,imm[i],th);
2472 }
2473 }else{
2474 // Shift by zero
2475 if(sl!=tl) emit_mov(sl,tl);
2476 if(th>=0&&sh!=th) emit_mov(sh,th);
2477 }
2478 }
2479 }
2480 }
2481 }
2482 if(opcode2[i]==0x3c) // DSLL32
2483 {
2484 if(rt1[i]) {
2485 signed char sl,tl,th;
2486 tl=get_reg(i_regs->regmap,rt1[i]);
2487 th=get_reg(i_regs->regmap,rt1[i]|64);
2488 sl=get_reg(i_regs->regmap,rs1[i]);
2489 if(th>=0||tl>=0){
2490 assert(tl>=0);
2491 assert(th>=0);
2492 assert(sl>=0);
2493 emit_mov(sl,th);
2494 emit_zeroreg(tl);
2495 if(imm[i]>32)
2496 {
2497 emit_shlimm(th,imm[i]&31,th);
2498 }
2499 }
2500 }
2501 }
2502 if(opcode2[i]==0x3e) // DSRL32
2503 {
2504 if(rt1[i]) {
2505 signed char sh,tl,th;
2506 tl=get_reg(i_regs->regmap,rt1[i]);
2507 th=get_reg(i_regs->regmap,rt1[i]|64);
2508 sh=get_reg(i_regs->regmap,rs1[i]|64);
2509 if(tl>=0){
2510 assert(sh>=0);
2511 emit_mov(sh,tl);
2512 if(th>=0) emit_zeroreg(th);
2513 if(imm[i]>32)
2514 {
2515 emit_shrimm(tl,imm[i]&31,tl);
2516 }
2517 }
2518 }
2519 }
2520 if(opcode2[i]==0x3f) // DSRA32
2521 {
2522 if(rt1[i]) {
2523 signed char sh,tl;
2524 tl=get_reg(i_regs->regmap,rt1[i]);
2525 sh=get_reg(i_regs->regmap,rs1[i]|64);
2526 if(tl>=0){
2527 assert(sh>=0);
2528 emit_mov(sh,tl);
2529 if(imm[i]>32)
2530 {
2531 emit_sarimm(tl,imm[i]&31,tl);
2532 }
2533 }
2534 }
2535 }
2536}
2537
2538#ifndef shift_assemble
2539void shift_assemble(int i,struct regstat *i_regs)
2540{
2541 printf("Need shift_assemble for this architecture.\n");
2542 exit(1);
2543}
2544#endif
2545
2546void load_assemble(int i,struct regstat *i_regs)
2547{
2548 int s,th,tl,addr,map=-1;
2549 int offset;
2550 int jaddr=0;
5bf843dc 2551 int memtarget=0,c=0;
b1570849 2552 int fastload_reg_override=0;
57871462 2553 u_int hr,reglist=0;
2554 th=get_reg(i_regs->regmap,rt1[i]|64);
2555 tl=get_reg(i_regs->regmap,rt1[i]);
2556 s=get_reg(i_regs->regmap,rs1[i]);
2557 offset=imm[i];
2558 for(hr=0;hr<HOST_REGS;hr++) {
2559 if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
2560 }
2561 if(i_regs->regmap[HOST_CCREG]==CCREG) reglist&=~(1<<HOST_CCREG);
2562 if(s>=0) {
2563 c=(i_regs->wasconst>>s)&1;
af4ee1fe 2564 if (c) {
2565 memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
2566 if(using_tlb&&((signed int)(constmap[i][s]+offset))>=(signed int)0xC0000000) memtarget=1;
2567 }
57871462 2568 }
57871462 2569 //printf("load_assemble: c=%d\n",c);
2570 //if(c) printf("load_assemble: const=%x\n",(int)constmap[i][s]+offset);
2571 // FIXME: Even if the load is a NOP, we should check for pagefaults...
f18c0f46 2572 if(tl<0&&(!c||(((u_int)constmap[i][s]+offset)>>16)==0x1f80)
2573 ||rt1[i]==0) {
5bf843dc 2574 // could be FIFO, must perform the read
f18c0f46 2575 // ||dummy read
5bf843dc 2576 assem_debug("(forced read)\n");
2577 tl=get_reg(i_regs->regmap,-1);
2578 assert(tl>=0);
5bf843dc 2579 }
2580 if(offset||s<0||c) addr=tl;
2581 else addr=s;
535d208a 2582 //if(tl<0) tl=get_reg(i_regs->regmap,-1);
2583 if(tl>=0) {
2584 //printf("load_assemble: c=%d\n",c);
2585 //if(c) printf("load_assemble: const=%x\n",(int)constmap[i][s]+offset);
2586 assert(tl>=0); // Even if the load is a NOP, we must check for pagefaults and I/O
2587 reglist&=~(1<<tl);
2588 if(th>=0) reglist&=~(1<<th);
2589 if(!using_tlb) {
2590 if(!c) {
2591 #ifdef RAM_OFFSET
2592 map=get_reg(i_regs->regmap,ROREG);
2593 if(map<0) emit_loadreg(ROREG,map=HOST_TEMPREG);
2594 #endif
57871462 2595//#define R29_HACK 1
535d208a 2596 #ifdef R29_HACK
2597 // Strmnnrmn's speed hack
2598 if(rs1[i]!=29||start<0x80001000||start>=0x80000000+RAM_SIZE)
2599 #endif
2600 {
ffb0b9e0 2601 jaddr=emit_fastpath_cmp_jump(i,addr,&fastload_reg_override);
57871462 2602 }
535d208a 2603 }
a327ad27 2604 else if(ram_offset&&memtarget) {
2605 emit_addimm(addr,ram_offset,HOST_TEMPREG);
2606 fastload_reg_override=HOST_TEMPREG;
2607 }
535d208a 2608 }else{ // using tlb
2609 int x=0;
2610 if (opcode[i]==0x20||opcode[i]==0x24) x=3; // LB/LBU
2611 if (opcode[i]==0x21||opcode[i]==0x25) x=2; // LH/LHU
2612 map=get_reg(i_regs->regmap,TLREG);
2613 assert(map>=0);
ea3d2e6e 2614 reglist&=~(1<<map);
535d208a 2615 map=do_tlb_r(addr,tl,map,x,-1,-1,c,constmap[i][s]+offset);
2616 do_tlb_r_branch(map,c,constmap[i][s]+offset,&jaddr);
2617 }
2618 int dummy=(rt1[i]==0)||(tl!=get_reg(i_regs->regmap,rt1[i])); // ignore loads to r0 and unneeded reg
2619 if (opcode[i]==0x20) { // LB
2620 if(!c||memtarget) {
2621 if(!dummy) {
57871462 2622 #ifdef HOST_IMM_ADDR32
2623 if(c)
2624 emit_movsbl_tlb((constmap[i][s]+offset)^3,map,tl);
2625 else
2626 #endif
2627 {
2628 //emit_xorimm(addr,3,tl);
2629 //gen_tlb_addr_r(tl,map);
2630 //emit_movsbl_indexed((int)rdram-0x80000000,tl,tl);
535d208a 2631 int x=0,a=tl;
2002a1db 2632#ifdef BIG_ENDIAN_MIPS
57871462 2633 if(!c) emit_xorimm(addr,3,tl);
2634 else x=((constmap[i][s]+offset)^3)-(constmap[i][s]+offset);
2002a1db 2635#else
535d208a 2636 if(!c) a=addr;
dadf55f2 2637#endif
b1570849 2638 if(fastload_reg_override) a=fastload_reg_override;
2639
535d208a 2640 emit_movsbl_indexed_tlb(x,a,map,tl);
57871462 2641 }
57871462 2642 }
535d208a 2643 if(jaddr)
2644 add_stub(LOADB_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
57871462 2645 }
535d208a 2646 else
2647 inline_readstub(LOADB_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2648 }
2649 if (opcode[i]==0x21) { // LH
2650 if(!c||memtarget) {
2651 if(!dummy) {
57871462 2652 #ifdef HOST_IMM_ADDR32
2653 if(c)
2654 emit_movswl_tlb((constmap[i][s]+offset)^2,map,tl);
2655 else
2656 #endif
2657 {
535d208a 2658 int x=0,a=tl;
2002a1db 2659#ifdef BIG_ENDIAN_MIPS
57871462 2660 if(!c) emit_xorimm(addr,2,tl);
2661 else x=((constmap[i][s]+offset)^2)-(constmap[i][s]+offset);
2002a1db 2662#else
535d208a 2663 if(!c) a=addr;
dadf55f2 2664#endif
b1570849 2665 if(fastload_reg_override) a=fastload_reg_override;
57871462 2666 //#ifdef
2667 //emit_movswl_indexed_tlb(x,tl,map,tl);
2668 //else
2669 if(map>=0) {
535d208a 2670 gen_tlb_addr_r(a,map);
2671 emit_movswl_indexed(x,a,tl);
2672 }else{
a327ad27 2673 #if 1 //def RAM_OFFSET
535d208a 2674 emit_movswl_indexed(x,a,tl);
2675 #else
2676 emit_movswl_indexed((int)rdram-0x80000000+x,a,tl);
2677 #endif
2678 }
57871462 2679 }
57871462 2680 }
535d208a 2681 if(jaddr)
2682 add_stub(LOADH_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
57871462 2683 }
535d208a 2684 else
2685 inline_readstub(LOADH_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2686 }
2687 if (opcode[i]==0x23) { // LW
2688 if(!c||memtarget) {
2689 if(!dummy) {
dadf55f2 2690 int a=addr;
b1570849 2691 if(fastload_reg_override) a=fastload_reg_override;
57871462 2692 //emit_readword_indexed((int)rdram-0x80000000,addr,tl);
2693 #ifdef HOST_IMM_ADDR32
2694 if(c)
2695 emit_readword_tlb(constmap[i][s]+offset,map,tl);
2696 else
2697 #endif
dadf55f2 2698 emit_readword_indexed_tlb(0,a,map,tl);
57871462 2699 }
535d208a 2700 if(jaddr)
2701 add_stub(LOADW_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
57871462 2702 }
535d208a 2703 else
2704 inline_readstub(LOADW_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2705 }
2706 if (opcode[i]==0x24) { // LBU
2707 if(!c||memtarget) {
2708 if(!dummy) {
57871462 2709 #ifdef HOST_IMM_ADDR32
2710 if(c)
2711 emit_movzbl_tlb((constmap[i][s]+offset)^3,map,tl);
2712 else
2713 #endif
2714 {
2715 //emit_xorimm(addr,3,tl);
2716 //gen_tlb_addr_r(tl,map);
2717 //emit_movzbl_indexed((int)rdram-0x80000000,tl,tl);
535d208a 2718 int x=0,a=tl;
2002a1db 2719#ifdef BIG_ENDIAN_MIPS
57871462 2720 if(!c) emit_xorimm(addr,3,tl);
2721 else x=((constmap[i][s]+offset)^3)-(constmap[i][s]+offset);
2002a1db 2722#else
535d208a 2723 if(!c) a=addr;
dadf55f2 2724#endif
b1570849 2725 if(fastload_reg_override) a=fastload_reg_override;
2726
535d208a 2727 emit_movzbl_indexed_tlb(x,a,map,tl);
57871462 2728 }
57871462 2729 }
535d208a 2730 if(jaddr)
2731 add_stub(LOADBU_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
57871462 2732 }
535d208a 2733 else
2734 inline_readstub(LOADBU_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2735 }
2736 if (opcode[i]==0x25) { // LHU
2737 if(!c||memtarget) {
2738 if(!dummy) {
57871462 2739 #ifdef HOST_IMM_ADDR32
2740 if(c)
2741 emit_movzwl_tlb((constmap[i][s]+offset)^2,map,tl);
2742 else
2743 #endif
2744 {
535d208a 2745 int x=0,a=tl;
2002a1db 2746#ifdef BIG_ENDIAN_MIPS
57871462 2747 if(!c) emit_xorimm(addr,2,tl);
2748 else x=((constmap[i][s]+offset)^2)-(constmap[i][s]+offset);
2002a1db 2749#else
535d208a 2750 if(!c) a=addr;
dadf55f2 2751#endif
b1570849 2752 if(fastload_reg_override) a=fastload_reg_override;
57871462 2753 //#ifdef
2754 //emit_movzwl_indexed_tlb(x,tl,map,tl);
2755 //#else
2756 if(map>=0) {
535d208a 2757 gen_tlb_addr_r(a,map);
2758 emit_movzwl_indexed(x,a,tl);
2759 }else{
a327ad27 2760 #if 1 //def RAM_OFFSET
535d208a 2761 emit_movzwl_indexed(x,a,tl);
2762 #else
2763 emit_movzwl_indexed((int)rdram-0x80000000+x,a,tl);
2764 #endif
2765 }
57871462 2766 }
2767 }
535d208a 2768 if(jaddr)
2769 add_stub(LOADHU_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
57871462 2770 }
535d208a 2771 else
2772 inline_readstub(LOADHU_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2773 }
2774 if (opcode[i]==0x27) { // LWU
2775 assert(th>=0);
2776 if(!c||memtarget) {
2777 if(!dummy) {
dadf55f2 2778 int a=addr;
b1570849 2779 if(fastload_reg_override) a=fastload_reg_override;
57871462 2780 //emit_readword_indexed((int)rdram-0x80000000,addr,tl);
2781 #ifdef HOST_IMM_ADDR32
2782 if(c)
2783 emit_readword_tlb(constmap[i][s]+offset,map,tl);
2784 else
2785 #endif
dadf55f2 2786 emit_readword_indexed_tlb(0,a,map,tl);
57871462 2787 }
535d208a 2788 if(jaddr)
2789 add_stub(LOADW_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
2790 }
2791 else {
2792 inline_readstub(LOADW_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
57871462 2793 }
535d208a 2794 emit_zeroreg(th);
2795 }
2796 if (opcode[i]==0x37) { // LD
2797 if(!c||memtarget) {
2798 if(!dummy) {
dadf55f2 2799 int a=addr;
b1570849 2800 if(fastload_reg_override) a=fastload_reg_override;
57871462 2801 //gen_tlb_addr_r(tl,map);
2802 //if(th>=0) emit_readword_indexed((int)rdram-0x80000000,addr,th);
2803 //emit_readword_indexed((int)rdram-0x7FFFFFFC,addr,tl);
2804 #ifdef HOST_IMM_ADDR32
2805 if(c)
2806 emit_readdword_tlb(constmap[i][s]+offset,map,th,tl);
2807 else
2808 #endif
dadf55f2 2809 emit_readdword_indexed_tlb(0,a,map,th,tl);
57871462 2810 }
535d208a 2811 if(jaddr)
2812 add_stub(LOADD_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
57871462 2813 }
535d208a 2814 else
2815 inline_readstub(LOADD_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
57871462 2816 }
535d208a 2817 }
2818 //emit_storereg(rt1[i],tl); // DEBUG
57871462 2819 //if(opcode[i]==0x23)
2820 //if(opcode[i]==0x24)
2821 //if(opcode[i]==0x23||opcode[i]==0x24)
2822 /*if(opcode[i]==0x21||opcode[i]==0x23||opcode[i]==0x24)
2823 {
2824 //emit_pusha();
2825 save_regs(0x100f);
2826 emit_readword((int)&last_count,ECX);
2827 #ifdef __i386__
2828 if(get_reg(i_regs->regmap,CCREG)<0)
2829 emit_loadreg(CCREG,HOST_CCREG);
2830 emit_add(HOST_CCREG,ECX,HOST_CCREG);
2831 emit_addimm(HOST_CCREG,2*ccadj[i],HOST_CCREG);
2832 emit_writeword(HOST_CCREG,(int)&Count);
2833 #endif
2834 #ifdef __arm__
2835 if(get_reg(i_regs->regmap,CCREG)<0)
2836 emit_loadreg(CCREG,0);
2837 else
2838 emit_mov(HOST_CCREG,0);
2839 emit_add(0,ECX,0);
2840 emit_addimm(0,2*ccadj[i],0);
2841 emit_writeword(0,(int)&Count);
2842 #endif
2843 emit_call((int)memdebug);
2844 //emit_popa();
2845 restore_regs(0x100f);
2846 }/**/
2847}
2848
2849#ifndef loadlr_assemble
2850void loadlr_assemble(int i,struct regstat *i_regs)
2851{
2852 printf("Need loadlr_assemble for this architecture.\n");
2853 exit(1);
2854}
2855#endif
2856
2857void store_assemble(int i,struct regstat *i_regs)
2858{
2859 int s,th,tl,map=-1;
2860 int addr,temp;
2861 int offset;
2862 int jaddr=0,jaddr2,type;
666a299d 2863 int memtarget=0,c=0;
57871462 2864 int agr=AGEN1+(i&1);
b1570849 2865 int faststore_reg_override=0;
57871462 2866 u_int hr,reglist=0;
2867 th=get_reg(i_regs->regmap,rs2[i]|64);
2868 tl=get_reg(i_regs->regmap,rs2[i]);
2869 s=get_reg(i_regs->regmap,rs1[i]);
2870 temp=get_reg(i_regs->regmap,agr);
2871 if(temp<0) temp=get_reg(i_regs->regmap,-1);
2872 offset=imm[i];
2873 if(s>=0) {
2874 c=(i_regs->wasconst>>s)&1;
af4ee1fe 2875 if(c) {
2876 memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
2877 if(using_tlb&&((signed int)(constmap[i][s]+offset))>=(signed int)0xC0000000) memtarget=1;
2878 }
57871462 2879 }
2880 assert(tl>=0);
2881 assert(temp>=0);
2882 for(hr=0;hr<HOST_REGS;hr++) {
2883 if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
2884 }
2885 if(i_regs->regmap[HOST_CCREG]==CCREG) reglist&=~(1<<HOST_CCREG);
2886 if(offset||s<0||c) addr=temp;
2887 else addr=s;
2888 if(!using_tlb) {
2889 if(!c) {
71e490c5 2890 jaddr=emit_fastpath_cmp_jump(i,addr,&faststore_reg_override);
57871462 2891 }
a327ad27 2892 else if(ram_offset&&memtarget) {
2893 emit_addimm(addr,ram_offset,HOST_TEMPREG);
2894 faststore_reg_override=HOST_TEMPREG;
2895 }
57871462 2896 }else{ // using tlb
2897 int x=0;
2898 if (opcode[i]==0x28) x=3; // SB
2899 if (opcode[i]==0x29) x=2; // SH
2900 map=get_reg(i_regs->regmap,TLREG);
2901 assert(map>=0);
ea3d2e6e 2902 reglist&=~(1<<map);
57871462 2903 map=do_tlb_w(addr,temp,map,x,c,constmap[i][s]+offset);
2904 do_tlb_w_branch(map,c,constmap[i][s]+offset,&jaddr);
2905 }
2906
2907 if (opcode[i]==0x28) { // SB
2908 if(!c||memtarget) {
97a238a6 2909 int x=0,a=temp;
2002a1db 2910#ifdef BIG_ENDIAN_MIPS
57871462 2911 if(!c) emit_xorimm(addr,3,temp);
2912 else x=((constmap[i][s]+offset)^3)-(constmap[i][s]+offset);
2002a1db 2913#else
97a238a6 2914 if(!c) a=addr;
dadf55f2 2915#endif
b1570849 2916 if(faststore_reg_override) a=faststore_reg_override;
57871462 2917 //gen_tlb_addr_w(temp,map);
2918 //emit_writebyte_indexed(tl,(int)rdram-0x80000000,temp);
97a238a6 2919 emit_writebyte_indexed_tlb(tl,x,a,map,a);
57871462 2920 }
2921 type=STOREB_STUB;
2922 }
2923 if (opcode[i]==0x29) { // SH
2924 if(!c||memtarget) {
97a238a6 2925 int x=0,a=temp;
2002a1db 2926#ifdef BIG_ENDIAN_MIPS
57871462 2927 if(!c) emit_xorimm(addr,2,temp);
2928 else x=((constmap[i][s]+offset)^2)-(constmap[i][s]+offset);
2002a1db 2929#else
97a238a6 2930 if(!c) a=addr;
dadf55f2 2931#endif
b1570849 2932 if(faststore_reg_override) a=faststore_reg_override;
57871462 2933 //#ifdef
2934 //emit_writehword_indexed_tlb(tl,x,temp,map,temp);
2935 //#else
2936 if(map>=0) {
97a238a6 2937 gen_tlb_addr_w(a,map);
2938 emit_writehword_indexed(tl,x,a);
57871462 2939 }else
a327ad27 2940 //emit_writehword_indexed(tl,(int)rdram-0x80000000+x,a);
2941 emit_writehword_indexed(tl,x,a);
57871462 2942 }
2943 type=STOREH_STUB;
2944 }
2945 if (opcode[i]==0x2B) { // SW
dadf55f2 2946 if(!c||memtarget) {
2947 int a=addr;
b1570849 2948 if(faststore_reg_override) a=faststore_reg_override;
57871462 2949 //emit_writeword_indexed(tl,(int)rdram-0x80000000,addr);
dadf55f2 2950 emit_writeword_indexed_tlb(tl,0,a,map,temp);
2951 }
57871462 2952 type=STOREW_STUB;
2953 }
2954 if (opcode[i]==0x3F) { // SD
2955 if(!c||memtarget) {
dadf55f2 2956 int a=addr;
b1570849 2957 if(faststore_reg_override) a=faststore_reg_override;
57871462 2958 if(rs2[i]) {
2959 assert(th>=0);
2960 //emit_writeword_indexed(th,(int)rdram-0x80000000,addr);
2961 //emit_writeword_indexed(tl,(int)rdram-0x7FFFFFFC,addr);
dadf55f2 2962 emit_writedword_indexed_tlb(th,tl,0,a,map,temp);
57871462 2963 }else{
2964 // Store zero
2965 //emit_writeword_indexed(tl,(int)rdram-0x80000000,temp);
2966 //emit_writeword_indexed(tl,(int)rdram-0x7FFFFFFC,temp);
dadf55f2 2967 emit_writedword_indexed_tlb(tl,tl,0,a,map,temp);
57871462 2968 }
2969 }
2970 type=STORED_STUB;
2971 }
b96d3df7 2972 if(jaddr) {
2973 // PCSX store handlers don't check invcode again
2974 reglist|=1<<addr;
2975 add_stub(type,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
2976 jaddr=0;
2977 }
0ff8c62c 2978 if(!using_tlb&&!(i_regs->waswritten&(1<<rs1[i]))&&!(new_dynarec_hacks&NDHACK_NO_SMC_CHECK)) {
57871462 2979 if(!c||memtarget) {
2980 #ifdef DESTRUCTIVE_SHIFT
2981 // The x86 shift operation is 'destructive'; it overwrites the
2982 // source register, so we need to make a copy first and use that.
2983 addr=temp;
2984 #endif
2985 #if defined(HOST_IMM8)
2986 int ir=get_reg(i_regs->regmap,INVCP);
2987 assert(ir>=0);
2988 emit_cmpmem_indexedsr12_reg(ir,addr,1);
2989 #else
2990 emit_cmpmem_indexedsr12_imm((int)invalid_code,addr,1);
2991 #endif
0bbd1454 2992 #if defined(HAVE_CONDITIONAL_CALL) && !defined(DESTRUCTIVE_SHIFT)
2993 emit_callne(invalidate_addr_reg[addr]);
2994 #else
57871462 2995 jaddr2=(int)out;
2996 emit_jne(0);
2997 add_stub(INVCODE_STUB,jaddr2,(int)out,reglist|(1<<HOST_CCREG),addr,0,0,0);
0bbd1454 2998 #endif
57871462 2999 }
3000 }
7a518516 3001 u_int addr_val=constmap[i][s]+offset;
3eaa7048 3002 if(jaddr) {
3003 add_stub(type,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
3004 } else if(c&&!memtarget) {
7a518516 3005 inline_writestub(type,i,addr_val,i_regs->regmap,rs2[i],ccadj[i],reglist);
3006 }
3007 // basic current block modification detection..
3008 // not looking back as that should be in mips cache already
3009 if(c&&start+i*4<addr_val&&addr_val<start+slen*4) {
c43b5311 3010 SysPrintf("write to %08x hits block %08x, pc=%08x\n",addr_val,start,start+i*4);
7a518516 3011 assert(i_regs->regmap==regs[i].regmap); // not delay slot
3012 if(i_regs->regmap==regs[i].regmap) {
3013 load_all_consts(regs[i].regmap_entry,regs[i].was32,regs[i].wasdirty,i);
3014 wb_dirtys(regs[i].regmap_entry,regs[i].was32,regs[i].wasdirty);
3015 emit_movimm(start+i*4+4,0);
3016 emit_writeword(0,(int)&pcaddr);
3017 emit_jmp((int)do_interrupt);
3018 }
3eaa7048 3019 }
57871462 3020 //if(opcode[i]==0x2B || opcode[i]==0x3F)
3021 //if(opcode[i]==0x2B || opcode[i]==0x28)
3022 //if(opcode[i]==0x2B || opcode[i]==0x29)
3023 //if(opcode[i]==0x2B)
3024 /*if(opcode[i]==0x2B || opcode[i]==0x28 || opcode[i]==0x29 || opcode[i]==0x3F)
3025 {
28d74ee8 3026 #ifdef __i386__
3027 emit_pusha();
3028 #endif
3029 #ifdef __arm__
57871462 3030 save_regs(0x100f);
28d74ee8 3031 #endif
57871462 3032 emit_readword((int)&last_count,ECX);
3033 #ifdef __i386__
3034 if(get_reg(i_regs->regmap,CCREG)<0)
3035 emit_loadreg(CCREG,HOST_CCREG);
3036 emit_add(HOST_CCREG,ECX,HOST_CCREG);
3037 emit_addimm(HOST_CCREG,2*ccadj[i],HOST_CCREG);
3038 emit_writeword(HOST_CCREG,(int)&Count);
3039 #endif
3040 #ifdef __arm__
3041 if(get_reg(i_regs->regmap,CCREG)<0)
3042 emit_loadreg(CCREG,0);
3043 else
3044 emit_mov(HOST_CCREG,0);
3045 emit_add(0,ECX,0);
3046 emit_addimm(0,2*ccadj[i],0);
3047 emit_writeword(0,(int)&Count);
3048 #endif
3049 emit_call((int)memdebug);
28d74ee8 3050 #ifdef __i386__
3051 emit_popa();
3052 #endif
3053 #ifdef __arm__
57871462 3054 restore_regs(0x100f);
28d74ee8 3055 #endif
57871462 3056 }/**/
3057}
3058
3059void storelr_assemble(int i,struct regstat *i_regs)
3060{
3061 int s,th,tl;
3062 int temp;
3063 int temp2;
3064 int offset;
3065 int jaddr=0,jaddr2;
3066 int case1,case2,case3;
3067 int done0,done1,done2;
af4ee1fe 3068 int memtarget=0,c=0;
fab5d06d 3069 int agr=AGEN1+(i&1);
57871462 3070 u_int hr,reglist=0;
3071 th=get_reg(i_regs->regmap,rs2[i]|64);
3072 tl=get_reg(i_regs->regmap,rs2[i]);
3073 s=get_reg(i_regs->regmap,rs1[i]);
fab5d06d 3074 temp=get_reg(i_regs->regmap,agr);
3075 if(temp<0) temp=get_reg(i_regs->regmap,-1);
57871462 3076 offset=imm[i];
3077 if(s>=0) {
3078 c=(i_regs->isconst>>s)&1;
af4ee1fe 3079 if(c) {
3080 memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
3081 if(using_tlb&&((signed int)(constmap[i][s]+offset))>=(signed int)0xC0000000) memtarget=1;
3082 }
57871462 3083 }
3084 assert(tl>=0);
3085 for(hr=0;hr<HOST_REGS;hr++) {
3086 if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
3087 }
535d208a 3088 assert(temp>=0);
3089 if(!using_tlb) {
3090 if(!c) {
3091 emit_cmpimm(s<0||offset?temp:s,RAM_SIZE);
3092 if(!offset&&s!=temp) emit_mov(s,temp);
3093 jaddr=(int)out;
3094 emit_jno(0);
3095 }
3096 else
3097 {
3098 if(!memtarget||!rs1[i]) {
57871462 3099 jaddr=(int)out;
3100 emit_jmp(0);
3101 }
57871462 3102 }
535d208a 3103 #ifdef RAM_OFFSET
3104 int map=get_reg(i_regs->regmap,ROREG);
3105 if(map<0) emit_loadreg(ROREG,map=HOST_TEMPREG);
3106 gen_tlb_addr_w(temp,map);
3107 #else
3108 if((u_int)rdram!=0x80000000)
3109 emit_addimm_no_flags((u_int)rdram-(u_int)0x80000000,temp);
3110 #endif
3111 }else{ // using tlb
3112 int map=get_reg(i_regs->regmap,TLREG);
3113 assert(map>=0);
ea3d2e6e 3114 reglist&=~(1<<map);
535d208a 3115 map=do_tlb_w(c||s<0||offset?temp:s,temp,map,0,c,constmap[i][s]+offset);
3116 if(!c&&!offset&&s>=0) emit_mov(s,temp);
3117 do_tlb_w_branch(map,c,constmap[i][s]+offset,&jaddr);
3118 if(!jaddr&&!memtarget) {
3119 jaddr=(int)out;
3120 emit_jmp(0);
57871462 3121 }
535d208a 3122 gen_tlb_addr_w(temp,map);
3123 }
3124
3125 if (opcode[i]==0x2C||opcode[i]==0x2D) { // SDL/SDR
3126 temp2=get_reg(i_regs->regmap,FTEMP);
3127 if(!rs2[i]) temp2=th=tl;
3128 }
57871462 3129
2002a1db 3130#ifndef BIG_ENDIAN_MIPS
3131 emit_xorimm(temp,3,temp);
3132#endif
535d208a 3133 emit_testimm(temp,2);
3134 case2=(int)out;
3135 emit_jne(0);
3136 emit_testimm(temp,1);
3137 case1=(int)out;
3138 emit_jne(0);
3139 // 0
3140 if (opcode[i]==0x2A) { // SWL
3141 emit_writeword_indexed(tl,0,temp);
3142 }
3143 if (opcode[i]==0x2E) { // SWR
3144 emit_writebyte_indexed(tl,3,temp);
3145 }
3146 if (opcode[i]==0x2C) { // SDL
3147 emit_writeword_indexed(th,0,temp);
3148 if(rs2[i]) emit_mov(tl,temp2);
3149 }
3150 if (opcode[i]==0x2D) { // SDR
3151 emit_writebyte_indexed(tl,3,temp);
3152 if(rs2[i]) emit_shldimm(th,tl,24,temp2);
3153 }
3154 done0=(int)out;
3155 emit_jmp(0);
3156 // 1
3157 set_jump_target(case1,(int)out);
3158 if (opcode[i]==0x2A) { // SWL
3159 // Write 3 msb into three least significant bytes
3160 if(rs2[i]) emit_rorimm(tl,8,tl);
3161 emit_writehword_indexed(tl,-1,temp);
3162 if(rs2[i]) emit_rorimm(tl,16,tl);
3163 emit_writebyte_indexed(tl,1,temp);
3164 if(rs2[i]) emit_rorimm(tl,8,tl);
3165 }
3166 if (opcode[i]==0x2E) { // SWR
3167 // Write two lsb into two most significant bytes
3168 emit_writehword_indexed(tl,1,temp);
3169 }
3170 if (opcode[i]==0x2C) { // SDL
3171 if(rs2[i]) emit_shrdimm(tl,th,8,temp2);
3172 // Write 3 msb into three least significant bytes
3173 if(rs2[i]) emit_rorimm(th,8,th);
3174 emit_writehword_indexed(th,-1,temp);
3175 if(rs2[i]) emit_rorimm(th,16,th);
3176 emit_writebyte_indexed(th,1,temp);
3177 if(rs2[i]) emit_rorimm(th,8,th);
3178 }
3179 if (opcode[i]==0x2D) { // SDR
3180 if(rs2[i]) emit_shldimm(th,tl,16,temp2);
3181 // Write two lsb into two most significant bytes
3182 emit_writehword_indexed(tl,1,temp);
3183 }
3184 done1=(int)out;
3185 emit_jmp(0);
3186 // 2
3187 set_jump_target(case2,(int)out);
3188 emit_testimm(temp,1);
3189 case3=(int)out;
3190 emit_jne(0);
3191 if (opcode[i]==0x2A) { // SWL
3192 // Write two msb into two least significant bytes
3193 if(rs2[i]) emit_rorimm(tl,16,tl);
3194 emit_writehword_indexed(tl,-2,temp);
3195 if(rs2[i]) emit_rorimm(tl,16,tl);
3196 }
3197 if (opcode[i]==0x2E) { // SWR
3198 // Write 3 lsb into three most significant bytes
3199 emit_writebyte_indexed(tl,-1,temp);
3200 if(rs2[i]) emit_rorimm(tl,8,tl);
3201 emit_writehword_indexed(tl,0,temp);
3202 if(rs2[i]) emit_rorimm(tl,24,tl);
3203 }
3204 if (opcode[i]==0x2C) { // SDL
3205 if(rs2[i]) emit_shrdimm(tl,th,16,temp2);
3206 // Write two msb into two least significant bytes
3207 if(rs2[i]) emit_rorimm(th,16,th);
3208 emit_writehword_indexed(th,-2,temp);
3209 if(rs2[i]) emit_rorimm(th,16,th);
3210 }
3211 if (opcode[i]==0x2D) { // SDR
3212 if(rs2[i]) emit_shldimm(th,tl,8,temp2);
3213 // Write 3 lsb into three most significant bytes
3214 emit_writebyte_indexed(tl,-1,temp);
3215 if(rs2[i]) emit_rorimm(tl,8,tl);
3216 emit_writehword_indexed(tl,0,temp);
3217 if(rs2[i]) emit_rorimm(tl,24,tl);
3218 }
3219 done2=(int)out;
3220 emit_jmp(0);
3221 // 3
3222 set_jump_target(case3,(int)out);
3223 if (opcode[i]==0x2A) { // SWL
3224 // Write msb into least significant byte
3225 if(rs2[i]) emit_rorimm(tl,24,tl);
3226 emit_writebyte_indexed(tl,-3,temp);
3227 if(rs2[i]) emit_rorimm(tl,8,tl);
3228 }
3229 if (opcode[i]==0x2E) { // SWR
3230 // Write entire word
3231 emit_writeword_indexed(tl,-3,temp);
3232 }
3233 if (opcode[i]==0x2C) { // SDL
3234 if(rs2[i]) emit_shrdimm(tl,th,24,temp2);
3235 // Write msb into least significant byte
3236 if(rs2[i]) emit_rorimm(th,24,th);
3237 emit_writebyte_indexed(th,-3,temp);
3238 if(rs2[i]) emit_rorimm(th,8,th);
3239 }
3240 if (opcode[i]==0x2D) { // SDR
3241 if(rs2[i]) emit_mov(th,temp2);
3242 // Write entire word
3243 emit_writeword_indexed(tl,-3,temp);
3244 }
3245 set_jump_target(done0,(int)out);
3246 set_jump_target(done1,(int)out);
3247 set_jump_target(done2,(int)out);
3248 if (opcode[i]==0x2C) { // SDL
3249 emit_testimm(temp,4);
57871462 3250 done0=(int)out;
57871462 3251 emit_jne(0);
535d208a 3252 emit_andimm(temp,~3,temp);
3253 emit_writeword_indexed(temp2,4,temp);
3254 set_jump_target(done0,(int)out);
3255 }
3256 if (opcode[i]==0x2D) { // SDR
3257 emit_testimm(temp,4);
3258 done0=(int)out;
3259 emit_jeq(0);
3260 emit_andimm(temp,~3,temp);
3261 emit_writeword_indexed(temp2,-4,temp);
57871462 3262 set_jump_target(done0,(int)out);
57871462 3263 }
535d208a 3264 if(!c||!memtarget)
3265 add_stub(STORELR_STUB,jaddr,(int)out,i,(int)i_regs,temp,ccadj[i],reglist);
0ff8c62c 3266 if(!using_tlb&&!(i_regs->waswritten&(1<<rs1[i]))&&!(new_dynarec_hacks&NDHACK_NO_SMC_CHECK)) {
535d208a 3267 #ifdef RAM_OFFSET
3268 int map=get_reg(i_regs->regmap,ROREG);
3269 if(map<0) map=HOST_TEMPREG;
3270 gen_orig_addr_w(temp,map);
3271 #else
57871462 3272 emit_addimm_no_flags((u_int)0x80000000-(u_int)rdram,temp);
535d208a 3273 #endif
57871462 3274 #if defined(HOST_IMM8)
3275 int ir=get_reg(i_regs->regmap,INVCP);
3276 assert(ir>=0);
3277 emit_cmpmem_indexedsr12_reg(ir,temp,1);
3278 #else
3279 emit_cmpmem_indexedsr12_imm((int)invalid_code,temp,1);
3280 #endif
535d208a 3281 #if defined(HAVE_CONDITIONAL_CALL) && !defined(DESTRUCTIVE_SHIFT)
3282 emit_callne(invalidate_addr_reg[temp]);
3283 #else
57871462 3284 jaddr2=(int)out;
3285 emit_jne(0);
3286 add_stub(INVCODE_STUB,jaddr2,(int)out,reglist|(1<<HOST_CCREG),temp,0,0,0);
535d208a 3287 #endif
57871462 3288 }
3289 /*
3290 emit_pusha();
3291 //save_regs(0x100f);
3292 emit_readword((int)&last_count,ECX);
3293 if(get_reg(i_regs->regmap,CCREG)<0)
3294 emit_loadreg(CCREG,HOST_CCREG);
3295 emit_add(HOST_CCREG,ECX,HOST_CCREG);
3296 emit_addimm(HOST_CCREG,2*ccadj[i],HOST_CCREG);
3297 emit_writeword(HOST_CCREG,(int)&Count);
3298 emit_call((int)memdebug);
3299 emit_popa();
3300 //restore_regs(0x100f);
3301 /**/
3302}
3303
3304void c1ls_assemble(int i,struct regstat *i_regs)
3305{
3d624f89 3306 cop1_unusable(i, i_regs);
57871462 3307}
3308
b9b61529 3309void c2ls_assemble(int i,struct regstat *i_regs)
3310{
3311 int s,tl;
3312 int ar;
3313 int offset;
1fd1aceb 3314 int memtarget=0,c=0;
c2e3bd42 3315 int jaddr2=0,jaddr3,type;
b9b61529 3316 int agr=AGEN1+(i&1);
ffb0b9e0 3317 int fastio_reg_override=0;
b9b61529 3318 u_int hr,reglist=0;
3319 u_int copr=(source[i]>>16)&0x1f;
3320 s=get_reg(i_regs->regmap,rs1[i]);
3321 tl=get_reg(i_regs->regmap,FTEMP);
3322 offset=imm[i];
3323 assert(rs1[i]>0);
3324 assert(tl>=0);
3325 assert(!using_tlb);
3326
3327 for(hr=0;hr<HOST_REGS;hr++) {
3328 if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
3329 }
3330 if(i_regs->regmap[HOST_CCREG]==CCREG)
3331 reglist&=~(1<<HOST_CCREG);
3332
3333 // get the address
3334 if (opcode[i]==0x3a) { // SWC2
3335 ar=get_reg(i_regs->regmap,agr);
3336 if(ar<0) ar=get_reg(i_regs->regmap,-1);
3337 reglist|=1<<ar;
3338 } else { // LWC2
3339 ar=tl;
3340 }
1fd1aceb 3341 if(s>=0) c=(i_regs->wasconst>>s)&1;
3342 memtarget=c&&(((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE);
b9b61529 3343 if (!offset&&!c&&s>=0) ar=s;
3344 assert(ar>=0);
3345
3346 if (opcode[i]==0x3a) { // SWC2
3347 cop2_get_dreg(copr,tl,HOST_TEMPREG);
1fd1aceb 3348 type=STOREW_STUB;
b9b61529 3349 }
1fd1aceb 3350 else
b9b61529 3351 type=LOADW_STUB;
1fd1aceb 3352
3353 if(c&&!memtarget) {
3354 jaddr2=(int)out;
3355 emit_jmp(0); // inline_readstub/inline_writestub?
b9b61529 3356 }
1fd1aceb 3357 else {
3358 if(!c) {
ffb0b9e0 3359 jaddr2=emit_fastpath_cmp_jump(i,ar,&fastio_reg_override);
1fd1aceb 3360 }
a327ad27 3361 else if(ram_offset&&memtarget) {
3362 emit_addimm(ar,ram_offset,HOST_TEMPREG);
3363 fastio_reg_override=HOST_TEMPREG;
3364 }
1fd1aceb 3365 if (opcode[i]==0x32) { // LWC2
3366 #ifdef HOST_IMM_ADDR32
3367 if(c) emit_readword_tlb(constmap[i][s]+offset,-1,tl);
3368 else
3369 #endif
ffb0b9e0 3370 int a=ar;
3371 if(fastio_reg_override) a=fastio_reg_override;
3372 emit_readword_indexed(0,a,tl);
1fd1aceb 3373 }
3374 if (opcode[i]==0x3a) { // SWC2
3375 #ifdef DESTRUCTIVE_SHIFT
3376 if(!offset&&!c&&s>=0) emit_mov(s,ar);
3377 #endif
ffb0b9e0 3378 int a=ar;
3379 if(fastio_reg_override) a=fastio_reg_override;
3380 emit_writeword_indexed(tl,0,a);
1fd1aceb 3381 }
b9b61529 3382 }
3383 if(jaddr2)
3384 add_stub(type,jaddr2,(int)out,i,ar,(int)i_regs,ccadj[i],reglist);
0ff8c62c 3385 if(opcode[i]==0x3a) // SWC2
3386 if(!(i_regs->waswritten&(1<<rs1[i]))&&!(new_dynarec_hacks&NDHACK_NO_SMC_CHECK)) {
b9b61529 3387#if defined(HOST_IMM8)
3388 int ir=get_reg(i_regs->regmap,INVCP);
3389 assert(ir>=0);
3390 emit_cmpmem_indexedsr12_reg(ir,ar,1);
3391#else
3392 emit_cmpmem_indexedsr12_imm((int)invalid_code,ar,1);
3393#endif
0bbd1454 3394 #if defined(HAVE_CONDITIONAL_CALL) && !defined(DESTRUCTIVE_SHIFT)
3395 emit_callne(invalidate_addr_reg[ar]);
3396 #else
b9b61529 3397 jaddr3=(int)out;
3398 emit_jne(0);
3399 add_stub(INVCODE_STUB,jaddr3,(int)out,reglist|(1<<HOST_CCREG),ar,0,0,0);
0bbd1454 3400 #endif
b9b61529 3401 }
3402 if (opcode[i]==0x32) { // LWC2
3403 cop2_put_dreg(copr,tl,HOST_TEMPREG);
3404 }
3405}
3406
57871462 3407#ifndef multdiv_assemble
3408void multdiv_assemble(int i,struct regstat *i_regs)
3409{
3410 printf("Need multdiv_assemble for this architecture.\n");
3411 exit(1);
3412}
3413#endif
3414
3415void mov_assemble(int i,struct regstat *i_regs)
3416{
3417 //if(opcode2[i]==0x10||opcode2[i]==0x12) { // MFHI/MFLO
3418 //if(opcode2[i]==0x11||opcode2[i]==0x13) { // MTHI/MTLO
57871462 3419 if(rt1[i]) {
3420 signed char sh,sl,th,tl;
3421 th=get_reg(i_regs->regmap,rt1[i]|64);
3422 tl=get_reg(i_regs->regmap,rt1[i]);
3423 //assert(tl>=0);
3424 if(tl>=0) {
3425 sh=get_reg(i_regs->regmap,rs1[i]|64);
3426 sl=get_reg(i_regs->regmap,rs1[i]);
3427 if(sl>=0) emit_mov(sl,tl);
3428 else emit_loadreg(rs1[i],tl);
3429 if(th>=0) {
3430 if(sh>=0) emit_mov(sh,th);
3431 else emit_loadreg(rs1[i]|64,th);
3432 }
3433 }
3434 }
3435}
3436
3437#ifndef fconv_assemble
3438void fconv_assemble(int i,struct regstat *i_regs)
3439{
3440 printf("Need fconv_assemble for this architecture.\n");
3441 exit(1);
3442}
3443#endif
3444
3445#if 0
3446void float_assemble(int i,struct regstat *i_regs)
3447{
3448 printf("Need float_assemble for this architecture.\n");
3449 exit(1);
3450}
3451#endif
3452
3453void syscall_assemble(int i,struct regstat *i_regs)
3454{
3455 signed char ccreg=get_reg(i_regs->regmap,CCREG);
3456 assert(ccreg==HOST_CCREG);
3457 assert(!is_delayslot);
3458 emit_movimm(start+i*4,EAX); // Get PC
2573466a 3459 emit_addimm(HOST_CCREG,CLOCK_ADJUST(ccadj[i]),HOST_CCREG); // CHECK: is this right? There should probably be an extra cycle...
7139f3c8 3460 emit_jmp((int)jump_syscall_hle); // XXX
3461}
3462
3463void hlecall_assemble(int i,struct regstat *i_regs)
3464{
3465 signed char ccreg=get_reg(i_regs->regmap,CCREG);
3466 assert(ccreg==HOST_CCREG);
3467 assert(!is_delayslot);
3468 emit_movimm(start+i*4+4,0); // Get PC
67ba0fb4 3469 emit_movimm((int)psxHLEt[source[i]&7],1);
2573466a 3470 emit_addimm(HOST_CCREG,CLOCK_ADJUST(ccadj[i]),HOST_CCREG); // XXX
67ba0fb4 3471 emit_jmp((int)jump_hlecall);
57871462 3472}
3473
1e973cb0 3474void intcall_assemble(int i,struct regstat *i_regs)
3475{
3476 signed char ccreg=get_reg(i_regs->regmap,CCREG);
3477 assert(ccreg==HOST_CCREG);
3478 assert(!is_delayslot);
3479 emit_movimm(start+i*4,0); // Get PC
2573466a 3480 emit_addimm(HOST_CCREG,CLOCK_ADJUST(ccadj[i]),HOST_CCREG);
1e973cb0 3481 emit_jmp((int)jump_intcall);
3482}
3483
57871462 3484void ds_assemble(int i,struct regstat *i_regs)
3485{
ffb0b9e0 3486 speculate_register_values(i);
57871462 3487 is_delayslot=1;
3488 switch(itype[i]) {
3489 case ALU:
3490 alu_assemble(i,i_regs);break;
3491 case IMM16:
3492 imm16_assemble(i,i_regs);break;
3493 case SHIFT:
3494 shift_assemble(i,i_regs);break;
3495 case SHIFTIMM:
3496 shiftimm_assemble(i,i_regs);break;
3497 case LOAD:
3498 load_assemble(i,i_regs);break;
3499 case LOADLR:
3500 loadlr_assemble(i,i_regs);break;
3501 case STORE:
3502 store_assemble(i,i_regs);break;
3503 case STORELR:
3504 storelr_assemble(i,i_regs);break;
3505 case COP0:
3506 cop0_assemble(i,i_regs);break;
3507 case COP1:
3508 cop1_assemble(i,i_regs);break;
3509 case C1LS:
3510 c1ls_assemble(i,i_regs);break;
b9b61529 3511 case COP2:
3512 cop2_assemble(i,i_regs);break;
3513 case C2LS:
3514 c2ls_assemble(i,i_regs);break;
3515 case C2OP:
3516 c2op_assemble(i,i_regs);break;
57871462 3517 case FCONV:
3518 fconv_assemble(i,i_regs);break;
3519 case FLOAT:
3520 float_assemble(i,i_regs);break;
3521 case FCOMP:
3522 fcomp_assemble(i,i_regs);break;
3523 case MULTDIV:
3524 multdiv_assemble(i,i_regs);break;
3525 case MOV:
3526 mov_assemble(i,i_regs);break;
3527 case SYSCALL:
7139f3c8 3528 case HLECALL:
1e973cb0 3529 case INTCALL:
57871462 3530 case SPAN:
3531 case UJUMP:
3532 case RJUMP:
3533 case CJUMP:
3534 case SJUMP:
3535 case FJUMP:
c43b5311 3536 SysPrintf("Jump in the delay slot. This is probably a bug.\n");
57871462 3537 }
3538 is_delayslot=0;
3539}
3540
3541// Is the branch target a valid internal jump?
3542int internal_branch(uint64_t i_is32,int addr)
3543{
3544 if(addr&1) return 0; // Indirect (register) jump
3545 if(addr>=start && addr<start+slen*4-4)
3546 {
71e490c5 3547 //int t=(addr-start)>>2;
57871462 3548 // Delay slots are not valid branch targets
3549 //if(t>0&&(itype[t-1]==RJUMP||itype[t-1]==UJUMP||itype[t-1]==CJUMP||itype[t-1]==SJUMP||itype[t-1]==FJUMP)) return 0;
3550 // 64 -> 32 bit transition requires a recompile
3551 /*if(is32[t]&~unneeded_reg_upper[t]&~i_is32)
3552 {
3553 if(requires_32bit[t]&~i_is32) printf("optimizable: no\n");
3554 else printf("optimizable: yes\n");
3555 }*/
3556 //if(is32[t]&~unneeded_reg_upper[t]&~i_is32) return 0;
71e490c5 3557 return 1;
57871462 3558 }
3559 return 0;
3560}
3561
3562#ifndef wb_invalidate
3563void wb_invalidate(signed char pre[],signed char entry[],uint64_t dirty,uint64_t is32,
3564 uint64_t u,uint64_t uu)
3565{
3566 int hr;
3567 for(hr=0;hr<HOST_REGS;hr++) {
3568 if(hr!=EXCLUDE_REG) {
3569 if(pre[hr]!=entry[hr]) {
3570 if(pre[hr]>=0) {
3571 if((dirty>>hr)&1) {
3572 if(get_reg(entry,pre[hr])<0) {
3573 if(pre[hr]<64) {
3574 if(!((u>>pre[hr])&1)) {
3575 emit_storereg(pre[hr],hr);
3576 if( ((is32>>pre[hr])&1) && !((uu>>pre[hr])&1) ) {
3577 emit_sarimm(hr,31,hr);
3578 emit_storereg(pre[hr]|64,hr);
3579 }
3580 }
3581 }else{
3582 if(!((uu>>(pre[hr]&63))&1) && !((is32>>(pre[hr]&63))&1)) {
3583 emit_storereg(pre[hr],hr);
3584 }
3585 }
3586 }
3587 }
3588 }
3589 }
3590 }
3591 }
3592 // Move from one register to another (no writeback)
3593 for(hr=0;hr<HOST_REGS;hr++) {
3594 if(hr!=EXCLUDE_REG) {
3595 if(pre[hr]!=entry[hr]) {
3596 if(pre[hr]>=0&&(pre[hr]&63)<TEMPREG) {
3597 int nr;
3598 if((nr=get_reg(entry,pre[hr]))>=0) {
3599 emit_mov(hr,nr);
3600 }
3601 }
3602 }
3603 }
3604 }
3605}
3606#endif
3607
3608// Load the specified registers
3609// This only loads the registers given as arguments because
3610// we don't want to load things that will be overwritten
3611void load_regs(signed char entry[],signed char regmap[],int is32,int rs1,int rs2)
3612{
3613 int hr;
3614 // Load 32-bit regs
3615 for(hr=0;hr<HOST_REGS;hr++) {
3616 if(hr!=EXCLUDE_REG&&regmap[hr]>=0) {
3617 if(entry[hr]!=regmap[hr]) {
3618 if(regmap[hr]==rs1||regmap[hr]==rs2)
3619 {
3620 if(regmap[hr]==0) {
3621 emit_zeroreg(hr);
3622 }
3623 else
3624 {
3625 emit_loadreg(regmap[hr],hr);
3626 }
3627 }
3628 }
3629 }
3630 }
3631 //Load 64-bit regs
3632 for(hr=0;hr<HOST_REGS;hr++) {
3633 if(hr!=EXCLUDE_REG&&regmap[hr]>=0) {
3634 if(entry[hr]!=regmap[hr]) {
3635 if(regmap[hr]-64==rs1||regmap[hr]-64==rs2)
3636 {
3637 assert(regmap[hr]!=64);
3638 if((is32>>(regmap[hr]&63))&1) {
3639 int lr=get_reg(regmap,regmap[hr]-64);
3640 if(lr>=0)
3641 emit_sarimm(lr,31,hr);
3642 else
3643 emit_loadreg(regmap[hr],hr);
3644 }
3645 else
3646 {
3647 emit_loadreg(regmap[hr],hr);
3648 }
3649 }
3650 }
3651 }
3652 }
3653}
3654
3655// Load registers prior to the start of a loop
3656// so that they are not loaded within the loop
3657static void loop_preload(signed char pre[],signed char entry[])
3658{
3659 int hr;
3660 for(hr=0;hr<HOST_REGS;hr++) {
3661 if(hr!=EXCLUDE_REG) {
3662 if(pre[hr]!=entry[hr]) {
3663 if(entry[hr]>=0) {
3664 if(get_reg(pre,entry[hr])<0) {
3665 assem_debug("loop preload:\n");
3666 //printf("loop preload: %d\n",hr);
3667 if(entry[hr]==0) {
3668 emit_zeroreg(hr);
3669 }
3670 else if(entry[hr]<TEMPREG)
3671 {
3672 emit_loadreg(entry[hr],hr);
3673 }
3674 else if(entry[hr]-64<TEMPREG)
3675 {
3676 emit_loadreg(entry[hr],hr);
3677 }
3678 }
3679 }
3680 }
3681 }
3682 }
3683}
3684
3685// Generate address for load/store instruction
b9b61529 3686// goes to AGEN for writes, FTEMP for LOADLR and cop1/2 loads
57871462 3687void address_generation(int i,struct regstat *i_regs,signed char entry[])
3688{
b9b61529 3689 if(itype[i]==LOAD||itype[i]==LOADLR||itype[i]==STORE||itype[i]==STORELR||itype[i]==C1LS||itype[i]==C2LS) {
5194fb95 3690 int ra=-1;
57871462 3691 int agr=AGEN1+(i&1);
3692 int mgr=MGEN1+(i&1);
3693 if(itype[i]==LOAD) {
3694 ra=get_reg(i_regs->regmap,rt1[i]);
535d208a 3695 if(ra<0) ra=get_reg(i_regs->regmap,-1);
3696 assert(ra>=0);
57871462 3697 }
3698 if(itype[i]==LOADLR) {
3699 ra=get_reg(i_regs->regmap,FTEMP);
3700 }
3701 if(itype[i]==STORE||itype[i]==STORELR) {
3702 ra=get_reg(i_regs->regmap,agr);
3703 if(ra<0) ra=get_reg(i_regs->regmap,-1);
3704 }
b9b61529 3705 if(itype[i]==C1LS||itype[i]==C2LS) {
3706 if ((opcode[i]&0x3b)==0x31||(opcode[i]&0x3b)==0x32) // LWC1/LDC1/LWC2/LDC2
57871462 3707 ra=get_reg(i_regs->regmap,FTEMP);
1fd1aceb 3708 else { // SWC1/SDC1/SWC2/SDC2
57871462 3709 ra=get_reg(i_regs->regmap,agr);
3710 if(ra<0) ra=get_reg(i_regs->regmap,-1);
3711 }
3712 }
3713 int rs=get_reg(i_regs->regmap,rs1[i]);
3714 int rm=get_reg(i_regs->regmap,TLREG);
3715 if(ra>=0) {
3716 int offset=imm[i];
3717 int c=(i_regs->wasconst>>rs)&1;
3718 if(rs1[i]==0) {
3719 // Using r0 as a base address
3720 /*if(rm>=0) {
3721 if(!entry||entry[rm]!=mgr) {
3722 generate_map_const(offset,rm);
3723 } // else did it in the previous cycle
3724 }*/
3725 if(!entry||entry[ra]!=agr) {
3726 if (opcode[i]==0x22||opcode[i]==0x26) {
3727 emit_movimm(offset&0xFFFFFFFC,ra); // LWL/LWR
3728 }else if (opcode[i]==0x1a||opcode[i]==0x1b) {
3729 emit_movimm(offset&0xFFFFFFF8,ra); // LDL/LDR
3730 }else{
3731 emit_movimm(offset,ra);
3732 }
3733 } // else did it in the previous cycle
3734 }
3735 else if(rs<0) {
3736 if(!entry||entry[ra]!=rs1[i])
3737 emit_loadreg(rs1[i],ra);
3738 //if(!entry||entry[ra]!=rs1[i])
3739 // printf("poor load scheduling!\n");
3740 }
3741 else if(c) {
57871462 3742 if(rs1[i]!=rt1[i]||itype[i]!=LOAD) {
3743 if(!entry||entry[ra]!=agr) {
3744 if (opcode[i]==0x22||opcode[i]==0x26) {
3745 emit_movimm((constmap[i][rs]+offset)&0xFFFFFFFC,ra); // LWL/LWR
3746 }else if (opcode[i]==0x1a||opcode[i]==0x1b) {
3747 emit_movimm((constmap[i][rs]+offset)&0xFFFFFFF8,ra); // LDL/LDR
3748 }else{
3749 #ifdef HOST_IMM_ADDR32
b9b61529 3750 if((itype[i]!=LOAD&&(opcode[i]&0x3b)!=0x31&&(opcode[i]&0x3b)!=0x32) || // LWC1/LDC1/LWC2/LDC2
57871462 3751 (using_tlb&&((signed int)constmap[i][rs]+offset)>=(signed int)0xC0000000))
3752 #endif
3753 emit_movimm(constmap[i][rs]+offset,ra);
8575a877 3754 regs[i].loadedconst|=1<<ra;
57871462 3755 }
3756 } // else did it in the previous cycle
3757 } // else load_consts already did it
3758 }
3759 if(offset&&!c&&rs1[i]) {
3760 if(rs>=0) {
3761 emit_addimm(rs,offset,ra);
3762 }else{
3763 emit_addimm(ra,offset,ra);
3764 }
3765 }
3766 }
3767 }
3768 // Preload constants for next instruction
b9b61529 3769 if(itype[i+1]==LOAD||itype[i+1]==LOADLR||itype[i+1]==STORE||itype[i+1]==STORELR||itype[i+1]==C1LS||itype[i+1]==C2LS) {
57871462 3770 int agr,ra;
57871462 3771 // Actual address
3772 agr=AGEN1+((i+1)&1);
3773 ra=get_reg(i_regs->regmap,agr);
3774 if(ra>=0) {
3775 int rs=get_reg(regs[i+1].regmap,rs1[i+1]);
3776 int offset=imm[i+1];
3777 int c=(regs[i+1].wasconst>>rs)&1;
3778 if(c&&(rs1[i+1]!=rt1[i+1]||itype[i+1]!=LOAD)) {
3779 if (opcode[i+1]==0x22||opcode[i+1]==0x26) {
3780 emit_movimm((constmap[i+1][rs]+offset)&0xFFFFFFFC,ra); // LWL/LWR
3781 }else if (opcode[i+1]==0x1a||opcode[i+1]==0x1b) {
3782 emit_movimm((constmap[i+1][rs]+offset)&0xFFFFFFF8,ra); // LDL/LDR
3783 }else{
3784 #ifdef HOST_IMM_ADDR32
b9b61529 3785 if((itype[i+1]!=LOAD&&(opcode[i+1]&0x3b)!=0x31&&(opcode[i+1]&0x3b)!=0x32) || // LWC1/LDC1/LWC2/LDC2
57871462 3786 (using_tlb&&((signed int)constmap[i+1][rs]+offset)>=(signed int)0xC0000000))
3787 #endif
3788 emit_movimm(constmap[i+1][rs]+offset,ra);
8575a877 3789 regs[i+1].loadedconst|=1<<ra;
57871462 3790 }
3791 }
3792 else if(rs1[i+1]==0) {
3793 // Using r0 as a base address
3794 if (opcode[i+1]==0x22||opcode[i+1]==0x26) {
3795 emit_movimm(offset&0xFFFFFFFC,ra); // LWL/LWR
3796 }else if (opcode[i+1]==0x1a||opcode[i+1]==0x1b) {
3797 emit_movimm(offset&0xFFFFFFF8,ra); // LDL/LDR
3798 }else{
3799 emit_movimm(offset,ra);
3800 }
3801 }
3802 }
3803 }
3804}
3805
3806int get_final_value(int hr, int i, int *value)
3807{
3808 int reg=regs[i].regmap[hr];
3809 while(i<slen-1) {
3810 if(regs[i+1].regmap[hr]!=reg) break;
3811 if(!((regs[i+1].isconst>>hr)&1)) break;
3812 if(bt[i+1]) break;
3813 i++;
3814 }
3815 if(i<slen-1) {
3816 if(itype[i]==UJUMP||itype[i]==RJUMP||itype[i]==CJUMP||itype[i]==SJUMP) {
3817 *value=constmap[i][hr];
3818 return 1;
3819 }
3820 if(!bt[i+1]) {
3821 if(itype[i+1]==UJUMP||itype[i+1]==RJUMP||itype[i+1]==CJUMP||itype[i+1]==SJUMP) {
3822 // Load in delay slot, out-of-order execution
3823 if(itype[i+2]==LOAD&&rs1[i+2]==reg&&rt1[i+2]==reg&&((regs[i+1].wasconst>>hr)&1))
3824 {
3825 #ifdef HOST_IMM_ADDR32
3826 if(!using_tlb||((signed int)constmap[i][hr]+imm[i+2])<(signed int)0xC0000000) return 0;
3827 #endif
3828 // Precompute load address
3829 *value=constmap[i][hr]+imm[i+2];
3830 return 1;
3831 }
3832 }
3833 if(itype[i+1]==LOAD&&rs1[i+1]==reg&&rt1[i+1]==reg)
3834 {
3835 #ifdef HOST_IMM_ADDR32
3836 if(!using_tlb||((signed int)constmap[i][hr]+imm[i+1])<(signed int)0xC0000000) return 0;
3837 #endif
3838 // Precompute load address
3839 *value=constmap[i][hr]+imm[i+1];
3840 //printf("c=%x imm=%x\n",(int)constmap[i][hr],imm[i+1]);
3841 return 1;
3842 }
3843 }
3844 }
3845 *value=constmap[i][hr];
3846 //printf("c=%x\n",(int)constmap[i][hr]);
3847 if(i==slen-1) return 1;
3848 if(reg<64) {
3849 return !((unneeded_reg[i+1]>>reg)&1);
3850 }else{
3851 return !((unneeded_reg_upper[i+1]>>reg)&1);
3852 }
3853}
3854
3855// Load registers with known constants
3856void load_consts(signed char pre[],signed char regmap[],int is32,int i)
3857{
8575a877 3858 int hr,hr2;
3859 // propagate loaded constant flags
3860 if(i==0||bt[i])
3861 regs[i].loadedconst=0;
3862 else {
3863 for(hr=0;hr<HOST_REGS;hr++) {
3864 if(hr!=EXCLUDE_REG&&regmap[hr]>=0&&((regs[i-1].isconst>>hr)&1)&&pre[hr]==regmap[hr]
3865 &&regmap[hr]==regs[i-1].regmap[hr]&&((regs[i-1].loadedconst>>hr)&1))
3866 {
3867 regs[i].loadedconst|=1<<hr;
3868 }
3869 }
3870 }
57871462 3871 // Load 32-bit regs
3872 for(hr=0;hr<HOST_REGS;hr++) {
3873 if(hr!=EXCLUDE_REG&&regmap[hr]>=0) {
3874 //if(entry[hr]!=regmap[hr]) {
8575a877 3875 if(!((regs[i].loadedconst>>hr)&1)) {
57871462 3876 if(((regs[i].isconst>>hr)&1)&&regmap[hr]<64&&regmap[hr]>0) {
8575a877 3877 int value,similar=0;
57871462 3878 if(get_final_value(hr,i,&value)) {
8575a877 3879 // see if some other register has similar value
3880 for(hr2=0;hr2<HOST_REGS;hr2++) {
3881 if(hr2!=EXCLUDE_REG&&((regs[i].loadedconst>>hr2)&1)) {
3882 if(is_similar_value(value,constmap[i][hr2])) {
3883 similar=1;
3884 break;
3885 }
3886 }
3887 }
3888 if(similar) {
3889 int value2;
3890 if(get_final_value(hr2,i,&value2)) // is this needed?
3891 emit_movimm_from(value2,hr2,value,hr);
3892 else
3893 emit_movimm(value,hr);
3894 }
3895 else if(value==0) {
57871462 3896 emit_zeroreg(hr);
3897 }
3898 else {
3899 emit_movimm(value,hr);
3900 }
3901 }
8575a877 3902 regs[i].loadedconst|=1<<hr;
57871462 3903 }
3904 }
3905 }
3906 }
3907 // Load 64-bit regs
3908 for(hr=0;hr<HOST_REGS;hr++) {
3909 if(hr!=EXCLUDE_REG&&regmap[hr]>=0) {
3910 //if(entry[hr]!=regmap[hr]) {
3911 if(i==0||!((regs[i-1].isconst>>hr)&1)||pre[hr]!=regmap[hr]||bt[i]) {
3912 if(((regs[i].isconst>>hr)&1)&&regmap[hr]>64) {
3913 if((is32>>(regmap[hr]&63))&1) {
3914 int lr=get_reg(regmap,regmap[hr]-64);
3915 assert(lr>=0);
3916 emit_sarimm(lr,31,hr);
3917 }
3918 else
3919 {
3920 int value;
3921 if(get_final_value(hr,i,&value)) {
3922 if(value==0) {
3923 emit_zeroreg(hr);
3924 }
3925 else {
3926 emit_movimm(value,hr);
3927 }
3928 }
3929 }
3930 }
3931 }
3932 }
3933 }
3934}
3935void load_all_consts(signed char regmap[],int is32,u_int dirty,int i)
3936{
3937 int hr;
3938 // Load 32-bit regs
3939 for(hr=0;hr<HOST_REGS;hr++) {
3940 if(hr!=EXCLUDE_REG&&regmap[hr]>=0&&((dirty>>hr)&1)) {
3941 if(((regs[i].isconst>>hr)&1)&&regmap[hr]<64&&regmap[hr]>0) {
3942 int value=constmap[i][hr];
3943 if(value==0) {
3944 emit_zeroreg(hr);
3945 }
3946 else {
3947 emit_movimm(value,hr);
3948 }
3949 }
3950 }
3951 }
3952 // Load 64-bit regs
3953 for(hr=0;hr<HOST_REGS;hr++) {
3954 if(hr!=EXCLUDE_REG&&regmap[hr]>=0&&((dirty>>hr)&1)) {
3955 if(((regs[i].isconst>>hr)&1)&&regmap[hr]>64) {
3956 if((is32>>(regmap[hr]&63))&1) {
3957 int lr=get_reg(regmap,regmap[hr]-64);
3958 assert(lr>=0);
3959 emit_sarimm(lr,31,hr);
3960 }
3961 else
3962 {
3963 int value=constmap[i][hr];
3964 if(value==0) {
3965 emit_zeroreg(hr);
3966 }
3967 else {
3968 emit_movimm(value,hr);
3969 }
3970 }
3971 }
3972 }
3973 }
3974}
3975
3976// Write out all dirty registers (except cycle count)
3977void wb_dirtys(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty)
3978{
3979 int hr;
3980 for(hr=0;hr<HOST_REGS;hr++) {
3981 if(hr!=EXCLUDE_REG) {
3982 if(i_regmap[hr]>0) {
3983 if(i_regmap[hr]!=CCREG) {
3984 if((i_dirty>>hr)&1) {
3985 if(i_regmap[hr]<64) {
3986 emit_storereg(i_regmap[hr],hr);
57871462 3987 }else{
3988 if( !((i_is32>>(i_regmap[hr]&63))&1) ) {
3989 emit_storereg(i_regmap[hr],hr);
3990 }
3991 }
3992 }
3993 }
3994 }
3995 }
3996 }
3997}
3998// Write out dirty registers that we need to reload (pair with load_needed_regs)
3999// This writes the registers not written by store_regs_bt
4000void wb_needed_dirtys(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr)
4001{
4002 int hr;
4003 int t=(addr-start)>>2;
4004 for(hr=0;hr<HOST_REGS;hr++) {
4005 if(hr!=EXCLUDE_REG) {
4006 if(i_regmap[hr]>0) {
4007 if(i_regmap[hr]!=CCREG) {
4008 if(i_regmap[hr]==regs[t].regmap_entry[hr] && ((regs[t].dirty>>hr)&1) && !(((i_is32&~regs[t].was32&~unneeded_reg_upper[t])>>(i_regmap[hr]&63))&1)) {
4009 if((i_dirty>>hr)&1) {
4010 if(i_regmap[hr]<64) {
4011 emit_storereg(i_regmap[hr],hr);
57871462 4012 }else{
4013 if( !((i_is32>>(i_regmap[hr]&63))&1) ) {
4014 emit_storereg(i_regmap[hr],hr);
4015 }
4016 }
4017 }
4018 }
4019 }
4020 }
4021 }
4022 }
4023}
4024
4025// Load all registers (except cycle count)
4026void load_all_regs(signed char i_regmap[])
4027{
4028 int hr;
4029 for(hr=0;hr<HOST_REGS;hr++) {
4030 if(hr!=EXCLUDE_REG) {
4031 if(i_regmap[hr]==0) {
4032 emit_zeroreg(hr);
4033 }
4034 else
ea3d2e6e 4035 if(i_regmap[hr]>0 && (i_regmap[hr]&63)<TEMPREG && i_regmap[hr]!=CCREG)
57871462 4036 {
4037 emit_loadreg(i_regmap[hr],hr);
4038 }
4039 }
4040 }
4041}
4042
4043// Load all current registers also needed by next instruction
4044void load_needed_regs(signed char i_regmap[],signed char next_regmap[])
4045{
4046 int hr;
4047 for(hr=0;hr<HOST_REGS;hr++) {
4048 if(hr!=EXCLUDE_REG) {
4049 if(get_reg(next_regmap,i_regmap[hr])>=0) {
4050 if(i_regmap[hr]==0) {
4051 emit_zeroreg(hr);
4052 }
4053 else
ea3d2e6e 4054 if(i_regmap[hr]>0 && (i_regmap[hr]&63)<TEMPREG && i_regmap[hr]!=CCREG)
57871462 4055 {
4056 emit_loadreg(i_regmap[hr],hr);
4057 }
4058 }
4059 }
4060 }
4061}
4062
4063// Load all regs, storing cycle count if necessary
4064void load_regs_entry(int t)
4065{
4066 int hr;
2573466a 4067 if(is_ds[t]) emit_addimm(HOST_CCREG,CLOCK_ADJUST(1),HOST_CCREG);
4068 else if(ccadj[t]) emit_addimm(HOST_CCREG,-CLOCK_ADJUST(ccadj[t]),HOST_CCREG);
57871462 4069 if(regs[t].regmap_entry[HOST_CCREG]!=CCREG) {
4070 emit_storereg(CCREG,HOST_CCREG);
4071 }
4072 // Load 32-bit regs
4073 for(hr=0;hr<HOST_REGS;hr++) {
ea3d2e6e 4074 if(regs[t].regmap_entry[hr]>=0&&regs[t].regmap_entry[hr]<TEMPREG) {
57871462 4075 if(regs[t].regmap_entry[hr]==0) {
4076 emit_zeroreg(hr);
4077 }
4078 else if(regs[t].regmap_entry[hr]!=CCREG)
4079 {
4080 emit_loadreg(regs[t].regmap_entry[hr],hr);
4081 }
4082 }
4083 }
4084 // Load 64-bit regs
4085 for(hr=0;hr<HOST_REGS;hr++) {
ea3d2e6e 4086 if(regs[t].regmap_entry[hr]>=64&&regs[t].regmap_entry[hr]<TEMPREG+64) {
57871462 4087 assert(regs[t].regmap_entry[hr]!=64);
4088 if((regs[t].was32>>(regs[t].regmap_entry[hr]&63))&1) {
4089 int lr=get_reg(regs[t].regmap_entry,regs[t].regmap_entry[hr]-64);
4090 if(lr<0) {
4091 emit_loadreg(regs[t].regmap_entry[hr],hr);
4092 }
4093 else
4094 {
4095 emit_sarimm(lr,31,hr);
4096 }
4097 }
4098 else
4099 {
4100 emit_loadreg(regs[t].regmap_entry[hr],hr);
4101 }
4102 }
4103 }
4104}
4105
4106// Store dirty registers prior to branch
4107void store_regs_bt(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr)
4108{
4109 if(internal_branch(i_is32,addr))
4110 {
4111 int t=(addr-start)>>2;
4112 int hr;
4113 for(hr=0;hr<HOST_REGS;hr++) {
4114 if(hr!=EXCLUDE_REG) {
4115 if(i_regmap[hr]>0 && i_regmap[hr]!=CCREG) {
4116 if(i_regmap[hr]!=regs[t].regmap_entry[hr] || !((regs[t].dirty>>hr)&1) || (((i_is32&~regs[t].was32&~unneeded_reg_upper[t])>>(i_regmap[hr]&63))&1)) {
4117 if((i_dirty>>hr)&1) {
4118 if(i_regmap[hr]<64) {
4119 if(!((unneeded_reg[t]>>i_regmap[hr])&1)) {
4120 emit_storereg(i_regmap[hr],hr);
4121 if( ((i_is32>>i_regmap[hr])&1) && !((unneeded_reg_upper[t]>>i_regmap[hr])&1) ) {
4122 #ifdef DESTRUCTIVE_WRITEBACK
4123 emit_sarimm(hr,31,hr);
4124 emit_storereg(i_regmap[hr]|64,hr);
4125 #else
4126 emit_sarimm(hr,31,HOST_TEMPREG);
4127 emit_storereg(i_regmap[hr]|64,HOST_TEMPREG);
4128 #endif
4129 }
4130 }
4131 }else{
4132 if( !((i_is32>>(i_regmap[hr]&63))&1) && !((unneeded_reg_upper[t]>>(i_regmap[hr]&63))&1) ) {
4133 emit_storereg(i_regmap[hr],hr);
4134 }
4135 }
4136 }
4137 }
4138 }
4139 }
4140 }
4141 }
4142 else
4143 {
4144 // Branch out of this block, write out all dirty regs
4145 wb_dirtys(i_regmap,i_is32,i_dirty);
4146 }
4147}
4148
4149// Load all needed registers for branch target
4150void load_regs_bt(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr)
4151{
4152 //if(addr>=start && addr<(start+slen*4))
4153 if(internal_branch(i_is32,addr))
4154 {
4155 int t=(addr-start)>>2;
4156 int hr;
4157 // Store the cycle count before loading something else
4158 if(i_regmap[HOST_CCREG]!=CCREG) {
4159 assert(i_regmap[HOST_CCREG]==-1);
4160 }
4161 if(regs[t].regmap_entry[HOST_CCREG]!=CCREG) {
4162 emit_storereg(CCREG,HOST_CCREG);
4163 }
4164 // Load 32-bit regs
4165 for(hr=0;hr<HOST_REGS;hr++) {
ea3d2e6e 4166 if(hr!=EXCLUDE_REG&&regs[t].regmap_entry[hr]>=0&&regs[t].regmap_entry[hr]<TEMPREG) {
57871462 4167 #ifdef DESTRUCTIVE_WRITEBACK
4168 if(i_regmap[hr]!=regs[t].regmap_entry[hr] || ( !((regs[t].dirty>>hr)&1) && ((i_dirty>>hr)&1) && (((i_is32&~unneeded_reg_upper[t])>>i_regmap[hr])&1) ) || (((i_is32&~regs[t].was32&~unneeded_reg_upper[t])>>(i_regmap[hr]&63))&1)) {
4169 #else
4170 if(i_regmap[hr]!=regs[t].regmap_entry[hr] ) {
4171 #endif
4172 if(regs[t].regmap_entry[hr]==0) {
4173 emit_zeroreg(hr);
4174 }
4175 else if(regs[t].regmap_entry[hr]!=CCREG)
4176 {
4177 emit_loadreg(regs[t].regmap_entry[hr],hr);
4178 }
4179 }
4180 }
4181 }
4182 //Load 64-bit regs
4183 for(hr=0;hr<HOST_REGS;hr++) {
ea3d2e6e 4184 if(hr!=EXCLUDE_REG&&regs[t].regmap_entry[hr]>=64&&regs[t].regmap_entry[hr]<TEMPREG+64) {
57871462 4185 if(i_regmap[hr]!=regs[t].regmap_entry[hr]) {
4186 assert(regs[t].regmap_entry[hr]!=64);
4187 if((i_is32>>(regs[t].regmap_entry[hr]&63))&1) {
4188 int lr=get_reg(regs[t].regmap_entry,regs[t].regmap_entry[hr]-64);
4189 if(lr<0) {
4190 emit_loadreg(regs[t].regmap_entry[hr],hr);
4191 }
4192 else
4193 {
4194 emit_sarimm(lr,31,hr);
4195 }
4196 }
4197 else
4198 {
4199 emit_loadreg(regs[t].regmap_entry[hr],hr);
4200 }
4201 }
4202 else if((i_is32>>(regs[t].regmap_entry[hr]&63))&1) {
4203 int lr=get_reg(regs[t].regmap_entry,regs[t].regmap_entry[hr]-64);
4204 assert(lr>=0);
4205 emit_sarimm(lr,31,hr);
4206 }
4207 }
4208 }
4209 }
4210}
4211
4212int match_bt(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr)
4213{
4214 if(addr>=start && addr<start+slen*4-4)
4215 {
4216 int t=(addr-start)>>2;
4217 int hr;
4218 if(regs[t].regmap_entry[HOST_CCREG]!=CCREG) return 0;
4219 for(hr=0;hr<HOST_REGS;hr++)
4220 {
4221 if(hr!=EXCLUDE_REG)
4222 {
4223 if(i_regmap[hr]!=regs[t].regmap_entry[hr])
4224 {
ea3d2e6e 4225 if(regs[t].regmap_entry[hr]>=0&&(regs[t].regmap_entry[hr]|64)<TEMPREG+64)
57871462 4226 {
4227 return 0;
4228 }
4229 else
4230 if((i_dirty>>hr)&1)
4231 {
ea3d2e6e 4232 if(i_regmap[hr]<TEMPREG)
57871462 4233 {
4234 if(!((unneeded_reg[t]>>i_regmap[hr])&1))
4235 return 0;
4236 }
ea3d2e6e 4237 else if(i_regmap[hr]>=64&&i_regmap[hr]<TEMPREG+64)
57871462 4238 {
4239 if(!((unneeded_reg_upper[t]>>(i_regmap[hr]&63))&1))
4240 return 0;
4241 }
4242 }
4243 }
4244 else // Same register but is it 32-bit or dirty?
4245 if(i_regmap[hr]>=0)
4246 {
4247 if(!((regs[t].dirty>>hr)&1))
4248 {
4249 if((i_dirty>>hr)&1)
4250 {
4251 if(!((unneeded_reg[t]>>i_regmap[hr])&1))
4252 {
4253 //printf("%x: dirty no match\n",addr);
4254 return 0;
4255 }
4256 }
4257 }
4258 if((((regs[t].was32^i_is32)&~unneeded_reg_upper[t])>>(i_regmap[hr]&63))&1)
4259 {
4260 //printf("%x: is32 no match\n",addr);
4261 return 0;
4262 }
4263 }
4264 }
4265 }
4266 //if(is32[t]&~unneeded_reg_upper[t]&~i_is32) return 0;
57871462 4267 // Delay slots are not valid branch targets
4268 //if(t>0&&(itype[t-1]==RJUMP||itype[t-1]==UJUMP||itype[t-1]==CJUMP||itype[t-1]==SJUMP||itype[t-1]==FJUMP)) return 0;
4269 // Delay slots require additional processing, so do not match
4270 if(is_ds[t]) return 0;
4271 }
4272 else
4273 {
4274 int hr;
4275 for(hr=0;hr<HOST_REGS;hr++)
4276 {
4277 if(hr!=EXCLUDE_REG)
4278 {
4279 if(i_regmap[hr]>=0)
4280 {
4281 if(hr!=HOST_CCREG||i_regmap[hr]!=CCREG)
4282 {
4283 if((i_dirty>>hr)&1)
4284 {
4285 return 0;
4286 }
4287 }
4288 }
4289 }
4290 }
4291 }
4292 return 1;
4293}
4294
4295// Used when a branch jumps into the delay slot of another branch
4296void ds_assemble_entry(int i)
4297{
4298 int t=(ba[i]-start)>>2;
4299 if(!instr_addr[t]) instr_addr[t]=(u_int)out;
4300 assem_debug("Assemble delay slot at %x\n",ba[i]);
4301 assem_debug("<->\n");
4302 if(regs[t].regmap_entry[HOST_CCREG]==CCREG&&regs[t].regmap[HOST_CCREG]!=CCREG)
4303 wb_register(CCREG,regs[t].regmap_entry,regs[t].wasdirty,regs[t].was32);
4304 load_regs(regs[t].regmap_entry,regs[t].regmap,regs[t].was32,rs1[t],rs2[t]);
4305 address_generation(t,&regs[t],regs[t].regmap_entry);
b9b61529 4306 if(itype[t]==STORE||itype[t]==STORELR||(opcode[t]&0x3b)==0x39||(opcode[t]&0x3b)==0x3a)
57871462 4307 load_regs(regs[t].regmap_entry,regs[t].regmap,regs[t].was32,INVCP,INVCP);
4308 cop1_usable=0;
4309 is_delayslot=0;
4310 switch(itype[t]) {
4311 case ALU:
4312 alu_assemble(t,&regs[t]);break;
4313 case IMM16:
4314 imm16_assemble(t,&regs[t]);break;
4315 case SHIFT:
4316 shift_assemble(t,&regs[t]);break;
4317 case SHIFTIMM:
4318 shiftimm_assemble(t,&regs[t]);break;
4319 case LOAD:
4320 load_assemble(t,&regs[t]);break;
4321 case LOADLR:
4322 loadlr_assemble(t,&regs[t]);break;
4323 case STORE:
4324 store_assemble(t,&regs[t]);break;
4325 case STORELR:
4326 storelr_assemble(t,&regs[t]);break;
4327 case COP0:
4328 cop0_assemble(t,&regs[t]);break;
4329 case COP1:
4330 cop1_assemble(t,&regs[t]);break;
4331 case C1LS:
4332 c1ls_assemble(t,&regs[t]);break;
b9b61529 4333 case COP2:
4334 cop2_assemble(t,&regs[t]);break;
4335 case C2LS:
4336 c2ls_assemble(t,&regs[t]);break;
4337 case C2OP:
4338 c2op_assemble(t,&regs[t]);break;
57871462 4339 case FCONV:
4340 fconv_assemble(t,&regs[t]);break;
4341 case FLOAT:
4342 float_assemble(t,&regs[t]);break;
4343 case FCOMP:
4344 fcomp_assemble(t,&regs[t]);break;
4345 case MULTDIV:
4346 multdiv_assemble(t,&regs[t]);break;
4347 case MOV:
4348 mov_assemble(t,&regs[t]);break;
4349 case SYSCALL:
7139f3c8 4350 case HLECALL:
1e973cb0 4351 case INTCALL:
57871462 4352 case SPAN:
4353 case UJUMP:
4354 case RJUMP:
4355 case CJUMP:
4356 case SJUMP:
4357 case FJUMP:
c43b5311 4358 SysPrintf("Jump in the delay slot. This is probably a bug.\n");
57871462 4359 }
4360 store_regs_bt(regs[t].regmap,regs[t].is32,regs[t].dirty,ba[i]+4);
4361 load_regs_bt(regs[t].regmap,regs[t].is32,regs[t].dirty,ba[i]+4);
4362 if(internal_branch(regs[t].is32,ba[i]+4))
4363 assem_debug("branch: internal\n");
4364 else
4365 assem_debug("branch: external\n");
4366 assert(internal_branch(regs[t].is32,ba[i]+4));
4367 add_to_linker((int)out,ba[i]+4,internal_branch(regs[t].is32,ba[i]+4));
4368 emit_jmp(0);
4369}
4370
4371void do_cc(int i,signed char i_regmap[],int *adj,int addr,int taken,int invert)
4372{
4373 int count;
4374 int jaddr;
4375 int idle=0;
b6e87b2b 4376 int t=0;
57871462 4377 if(itype[i]==RJUMP)
4378 {
4379 *adj=0;
4380 }
4381 //if(ba[i]>=start && ba[i]<(start+slen*4))
4382 if(internal_branch(branch_regs[i].is32,ba[i]))
4383 {
b6e87b2b 4384 t=(ba[i]-start)>>2;
57871462 4385 if(is_ds[t]) *adj=-1; // Branch into delay slot adds an extra cycle
4386 else *adj=ccadj[t];
4387 }
4388 else
4389 {
4390 *adj=0;
4391 }
4392 count=ccadj[i];
4393 if(taken==TAKEN && i==(ba[i]-start)>>2 && source[i+1]==0) {
4394 // Idle loop
4395 if(count&1) emit_addimm_and_set_flags(2*(count+2),HOST_CCREG);
4396 idle=(int)out;
4397 //emit_subfrommem(&idlecount,HOST_CCREG); // Count idle cycles
4398 emit_andimm(HOST_CCREG,3,HOST_CCREG);
4399 jaddr=(int)out;
4400 emit_jmp(0);
4401 }
4402 else if(*adj==0||invert) {
b6e87b2b 4403 int cycles=CLOCK_ADJUST(count+2);
4404 // faster loop HACK
4405 if (t&&*adj) {
4406 int rel=t-i;
4407 if(-NO_CYCLE_PENALTY_THR<rel&&rel<0)
4408 cycles=CLOCK_ADJUST(*adj)+count+2-*adj;
4409 }
4410 emit_addimm_and_set_flags(cycles,HOST_CCREG);
57871462 4411 jaddr=(int)out;
4412 emit_jns(0);
4413 }
4414 else
4415 {
2573466a 4416 emit_cmpimm(HOST_CCREG,-CLOCK_ADJUST(count+2));
57871462 4417 jaddr=(int)out;
4418 emit_jns(0);
4419 }
4420 add_stub(CC_STUB,jaddr,idle?idle:(int)out,(*adj==0||invert||idle)?0:(count+2),i,addr,taken,0);
4421}
4422
4423void do_ccstub(int n)
4424{
4425 literal_pool(256);
4426 assem_debug("do_ccstub %x\n",start+stubs[n][4]*4);
4427 set_jump_target(stubs[n][1],(int)out);
4428 int i=stubs[n][4];
4429 if(stubs[n][6]==NULLDS) {
4430 // Delay slot instruction is nullified ("likely" branch)
4431 wb_dirtys(regs[i].regmap,regs[i].is32,regs[i].dirty);
4432 }
4433 else if(stubs[n][6]!=TAKEN) {
4434 wb_dirtys(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty);
4435 }
4436 else {
4437 if(internal_branch(branch_regs[i].is32,ba[i]))
4438 wb_needed_dirtys(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
4439 }
4440 if(stubs[n][5]!=-1)
4441 {
4442 // Save PC as return address
4443 emit_movimm(stubs[n][5],EAX);
4444 emit_writeword(EAX,(int)&pcaddr);
4445 }
4446 else
4447 {
4448 // Return address depends on which way the branch goes
4449 if(itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
4450 {
4451 int s1l=get_reg(branch_regs[i].regmap,rs1[i]);
4452 int s1h=get_reg(branch_regs[i].regmap,rs1[i]|64);
4453 int s2l=get_reg(branch_regs[i].regmap,rs2[i]);
4454 int s2h=get_reg(branch_regs[i].regmap,rs2[i]|64);
4455 if(rs1[i]==0)
4456 {
4457 s1l=s2l;s1h=s2h;
4458 s2l=s2h=-1;
4459 }
4460 else if(rs2[i]==0)
4461 {
4462 s2l=s2h=-1;
4463 }
4464 if((branch_regs[i].is32>>rs1[i])&(branch_regs[i].is32>>rs2[i])&1) {
4465 s1h=s2h=-1;
4466 }
4467 assert(s1l>=0);
4468 #ifdef DESTRUCTIVE_WRITEBACK
4469 if(rs1[i]) {
4470 if((branch_regs[i].dirty>>s1l)&(branch_regs[i].is32>>rs1[i])&1)
4471 emit_loadreg(rs1[i],s1l);
4472 }
4473 else {
4474 if((branch_regs[i].dirty>>s1l)&(branch_regs[i].is32>>rs2[i])&1)
4475 emit_loadreg(rs2[i],s1l);
4476 }
4477 if(s2l>=0)
4478 if((branch_regs[i].dirty>>s2l)&(branch_regs[i].is32>>rs2[i])&1)
4479 emit_loadreg(rs2[i],s2l);
4480 #endif
4481 int hr=0;
5194fb95 4482 int addr=-1,alt=-1,ntaddr=-1;
57871462 4483 while(hr<HOST_REGS)
4484 {
4485 if(hr!=EXCLUDE_REG && hr!=HOST_CCREG &&
4486 (branch_regs[i].regmap[hr]&63)!=rs1[i] &&
4487 (branch_regs[i].regmap[hr]&63)!=rs2[i] )
4488 {
4489 addr=hr++;break;
4490 }
4491 hr++;
4492 }
4493 while(hr<HOST_REGS)
4494 {
4495 if(hr!=EXCLUDE_REG && hr!=HOST_CCREG &&
4496 (branch_regs[i].regmap[hr]&63)!=rs1[i] &&
4497 (branch_regs[i].regmap[hr]&63)!=rs2[i] )
4498 {
4499 alt=hr++;break;
4500 }
4501 hr++;
4502 }
4503 if((opcode[i]&0x2E)==6) // BLEZ/BGTZ needs another register
4504 {
4505 while(hr<HOST_REGS)
4506 {
4507 if(hr!=EXCLUDE_REG && hr!=HOST_CCREG &&
4508 (branch_regs[i].regmap[hr]&63)!=rs1[i] &&
4509 (branch_regs[i].regmap[hr]&63)!=rs2[i] )
4510 {
4511 ntaddr=hr;break;
4512 }
4513 hr++;
4514 }
4515 assert(hr<HOST_REGS);
4516 }
4517 if((opcode[i]&0x2f)==4) // BEQ
4518 {
4519 #ifdef HAVE_CMOV_IMM
4520 if(s1h<0) {
4521 if(s2l>=0) emit_cmp(s1l,s2l);
4522 else emit_test(s1l,s1l);
4523 emit_cmov2imm_e_ne_compact(ba[i],start+i*4+8,addr);
4524 }
4525 else
4526 #endif
4527 {
4528 emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
4529 if(s1h>=0) {
4530 if(s2h>=0) emit_cmp(s1h,s2h);
4531 else emit_test(s1h,s1h);
4532 emit_cmovne_reg(alt,addr);
4533 }
4534 if(s2l>=0) emit_cmp(s1l,s2l);
4535 else emit_test(s1l,s1l);
4536 emit_cmovne_reg(alt,addr);
4537 }
4538 }
4539 if((opcode[i]&0x2f)==5) // BNE
4540 {
4541 #ifdef HAVE_CMOV_IMM
4542 if(s1h<0) {
4543 if(s2l>=0) emit_cmp(s1l,s2l);
4544 else emit_test(s1l,s1l);
4545 emit_cmov2imm_e_ne_compact(start+i*4+8,ba[i],addr);
4546 }
4547 else
4548 #endif
4549 {
4550 emit_mov2imm_compact(start+i*4+8,addr,ba[i],alt);
4551 if(s1h>=0) {
4552 if(s2h>=0) emit_cmp(s1h,s2h);
4553 else emit_test(s1h,s1h);
4554 emit_cmovne_reg(alt,addr);
4555 }
4556 if(s2l>=0) emit_cmp(s1l,s2l);
4557 else emit_test(s1l,s1l);
4558 emit_cmovne_reg(alt,addr);
4559 }
4560 }
4561 if((opcode[i]&0x2f)==6) // BLEZ
4562 {
4563 //emit_movimm(ba[i],alt);
4564 //emit_movimm(start+i*4+8,addr);
4565 emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
4566 emit_cmpimm(s1l,1);
4567 if(s1h>=0) emit_mov(addr,ntaddr);
4568 emit_cmovl_reg(alt,addr);
4569 if(s1h>=0) {
4570 emit_test(s1h,s1h);
4571 emit_cmovne_reg(ntaddr,addr);
4572 emit_cmovs_reg(alt,addr);
4573 }
4574 }
4575 if((opcode[i]&0x2f)==7) // BGTZ
4576 {
4577 //emit_movimm(ba[i],addr);
4578 //emit_movimm(start+i*4+8,ntaddr);
4579 emit_mov2imm_compact(ba[i],addr,start+i*4+8,ntaddr);
4580 emit_cmpimm(s1l,1);
4581 if(s1h>=0) emit_mov(addr,alt);
4582 emit_cmovl_reg(ntaddr,addr);
4583 if(s1h>=0) {
4584 emit_test(s1h,s1h);
4585 emit_cmovne_reg(alt,addr);
4586 emit_cmovs_reg(ntaddr,addr);
4587 }
4588 }
4589 if((opcode[i]==1)&&(opcode2[i]&0x2D)==0) // BLTZ
4590 {
4591 //emit_movimm(ba[i],alt);
4592 //emit_movimm(start+i*4+8,addr);
4593 emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
4594 if(s1h>=0) emit_test(s1h,s1h);
4595 else emit_test(s1l,s1l);
4596 emit_cmovs_reg(alt,addr);
4597 }
4598 if((opcode[i]==1)&&(opcode2[i]&0x2D)==1) // BGEZ
4599 {
4600 //emit_movimm(ba[i],addr);
4601 //emit_movimm(start+i*4+8,alt);
4602 emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
4603 if(s1h>=0) emit_test(s1h,s1h);
4604 else emit_test(s1l,s1l);
4605 emit_cmovs_reg(alt,addr);
4606 }
4607 if(opcode[i]==0x11 && opcode2[i]==0x08 ) {
4608 if(source[i]&0x10000) // BC1T
4609 {
4610 //emit_movimm(ba[i],alt);
4611 //emit_movimm(start+i*4+8,addr);
4612 emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
4613 emit_testimm(s1l,0x800000);
4614 emit_cmovne_reg(alt,addr);
4615 }
4616 else // BC1F
4617 {
4618 //emit_movimm(ba[i],addr);
4619 //emit_movimm(start+i*4+8,alt);
4620 emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
4621 emit_testimm(s1l,0x800000);
4622 emit_cmovne_reg(alt,addr);
4623 }
4624 }
4625 emit_writeword(addr,(int)&pcaddr);
4626 }
4627 else
4628 if(itype[i]==RJUMP)
4629 {
4630 int r=get_reg(branch_regs[i].regmap,rs1[i]);
4631 if(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1]) {
4632 r=get_reg(branch_regs[i].regmap,RTEMP);
4633 }
4634 emit_writeword(r,(int)&pcaddr);
4635 }
c43b5311 4636 else {SysPrintf("Unknown branch type in do_ccstub\n");exit(1);}
57871462 4637 }
4638 // Update cycle count
4639 assert(branch_regs[i].regmap[HOST_CCREG]==CCREG||branch_regs[i].regmap[HOST_CCREG]==-1);
2573466a 4640 if(stubs[n][3]) emit_addimm(HOST_CCREG,CLOCK_ADJUST((int)stubs[n][3]),HOST_CCREG);
57871462 4641 emit_call((int)cc_interrupt);
2573466a 4642 if(stubs[n][3]) emit_addimm(HOST_CCREG,-CLOCK_ADJUST((int)stubs[n][3]),HOST_CCREG);
57871462 4643 if(stubs[n][6]==TAKEN) {
4644 if(internal_branch(branch_regs[i].is32,ba[i]))
4645 load_needed_regs(branch_regs[i].regmap,regs[(ba[i]-start)>>2].regmap_entry);
4646 else if(itype[i]==RJUMP) {
4647 if(get_reg(branch_regs[i].regmap,RTEMP)>=0)
4648 emit_readword((int)&pcaddr,get_reg(branch_regs[i].regmap,RTEMP));
4649 else
4650 emit_loadreg(rs1[i],get_reg(branch_regs[i].regmap,rs1[i]));
4651 }
4652 }else if(stubs[n][6]==NOTTAKEN) {
4653 if(i<slen-2) load_needed_regs(branch_regs[i].regmap,regmap_pre[i+2]);
4654 else load_all_regs(branch_regs[i].regmap);
4655 }else if(stubs[n][6]==NULLDS) {
4656 // Delay slot instruction is nullified ("likely" branch)
4657 if(i<slen-2) load_needed_regs(regs[i].regmap,regmap_pre[i+2]);
4658 else load_all_regs(regs[i].regmap);
4659 }else{
4660 load_all_regs(branch_regs[i].regmap);
4661 }
4662 emit_jmp(stubs[n][2]); // return address
4663
4664 /* This works but uses a lot of memory...
4665 emit_readword((int)&last_count,ECX);
4666 emit_add(HOST_CCREG,ECX,EAX);
4667 emit_writeword(EAX,(int)&Count);
4668 emit_call((int)gen_interupt);
4669 emit_readword((int)&Count,HOST_CCREG);
4670 emit_readword((int)&next_interupt,EAX);
4671 emit_readword((int)&pending_exception,EBX);
4672 emit_writeword(EAX,(int)&last_count);
4673 emit_sub(HOST_CCREG,EAX,HOST_CCREG);
4674 emit_test(EBX,EBX);
4675 int jne_instr=(int)out;
4676 emit_jne(0);
4677 if(stubs[n][3]) emit_addimm(HOST_CCREG,-2*stubs[n][3],HOST_CCREG);
4678 load_all_regs(branch_regs[i].regmap);
4679 emit_jmp(stubs[n][2]); // return address
4680 set_jump_target(jne_instr,(int)out);
4681 emit_readword((int)&pcaddr,EAX);
4682 // Call get_addr_ht instead of doing the hash table here.
4683 // This code is executed infrequently and takes up a lot of space
4684 // so smaller is better.
4685 emit_storereg(CCREG,HOST_CCREG);
4686 emit_pushreg(EAX);
4687 emit_call((int)get_addr_ht);
4688 emit_loadreg(CCREG,HOST_CCREG);
4689 emit_addimm(ESP,4,ESP);
4690 emit_jmpreg(EAX);*/
4691}
4692
4693add_to_linker(int addr,int target,int ext)
4694{
4695 link_addr[linkcount][0]=addr;
4696 link_addr[linkcount][1]=target;
4697 link_addr[linkcount][2]=ext;
4698 linkcount++;
4699}
4700
eba830cd 4701static void ujump_assemble_write_ra(int i)
4702{
4703 int rt;
4704 unsigned int return_address;
4705 rt=get_reg(branch_regs[i].regmap,31);
4706 assem_debug("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
4707 //assert(rt>=0);
4708 return_address=start+i*4+8;
4709 if(rt>=0) {
4710 #ifdef USE_MINI_HT
4711 if(internal_branch(branch_regs[i].is32,return_address)&&rt1[i+1]!=31) {
4712 int temp=-1; // note: must be ds-safe
4713 #ifdef HOST_TEMPREG
4714 temp=HOST_TEMPREG;
4715 #endif
4716 if(temp>=0) do_miniht_insert(return_address,rt,temp);
4717 else emit_movimm(return_address,rt);
4718 }
4719 else
4720 #endif
4721 {
4722 #ifdef REG_PREFETCH
4723 if(temp>=0)
4724 {
4725 if(i_regmap[temp]!=PTEMP) emit_movimm((int)hash_table[((return_address>>16)^return_address)&0xFFFF],temp);
4726 }
4727 #endif
4728 emit_movimm(return_address,rt); // PC into link register
4729 #ifdef IMM_PREFETCH
4730 emit_prefetch(hash_table[((return_address>>16)^return_address)&0xFFFF]);
4731 #endif
4732 }
4733 }
4734}
4735
57871462 4736void ujump_assemble(int i,struct regstat *i_regs)
4737{
4738 signed char *i_regmap=i_regs->regmap;
eba830cd 4739 int ra_done=0;
57871462 4740 if(i==(ba[i]-start)>>2) assem_debug("idle loop\n");
4741 address_generation(i+1,i_regs,regs[i].regmap_entry);
4742 #ifdef REG_PREFETCH
4743 int temp=get_reg(branch_regs[i].regmap,PTEMP);
4744 if(rt1[i]==31&&temp>=0)
4745 {
4746 int return_address=start+i*4+8;
4747 if(get_reg(branch_regs[i].regmap,31)>0)
4748 if(i_regmap[temp]==PTEMP) emit_movimm((int)hash_table[((return_address>>16)^return_address)&0xFFFF],temp);
4749 }
4750 #endif
eba830cd 4751 if(rt1[i]==31&&(rt1[i]==rs1[i+1]||rt1[i]==rs2[i+1])) {
4752 ujump_assemble_write_ra(i); // writeback ra for DS
4753 ra_done=1;
57871462 4754 }
4ef8f67d 4755 ds_assemble(i+1,i_regs);
4756 uint64_t bc_unneeded=branch_regs[i].u;
4757 uint64_t bc_unneeded_upper=branch_regs[i].uu;
4758 bc_unneeded|=1|(1LL<<rt1[i]);
4759 bc_unneeded_upper|=1|(1LL<<rt1[i]);
4760 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
4761 bc_unneeded,bc_unneeded_upper);
4762 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
eba830cd 4763 if(!ra_done&&rt1[i]==31)
4764 ujump_assemble_write_ra(i);
57871462 4765 int cc,adj;
4766 cc=get_reg(branch_regs[i].regmap,CCREG);
4767 assert(cc==HOST_CCREG);
4768 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
4769 #ifdef REG_PREFETCH
4770 if(rt1[i]==31&&temp>=0) emit_prefetchreg(temp);
4771 #endif
4772 do_cc(i,branch_regs[i].regmap,&adj,ba[i],TAKEN,0);
2573466a 4773 if(adj) emit_addimm(cc,CLOCK_ADJUST(ccadj[i]+2-adj),cc);
57871462 4774 load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
4775 if(internal_branch(branch_regs[i].is32,ba[i]))
4776 assem_debug("branch: internal\n");
4777 else
4778 assem_debug("branch: external\n");
4779 if(internal_branch(branch_regs[i].is32,ba[i])&&is_ds[(ba[i]-start)>>2]) {
4780 ds_assemble_entry(i);
4781 }
4782 else {
4783 add_to_linker((int)out,ba[i],internal_branch(branch_regs[i].is32,ba[i]));
4784 emit_jmp(0);
4785 }
4786}
4787
eba830cd 4788static void rjump_assemble_write_ra(int i)
4789{
4790 int rt,return_address;
4791 assert(rt1[i+1]!=rt1[i]);
4792 assert(rt2[i+1]!=rt1[i]);
4793 rt=get_reg(branch_regs[i].regmap,rt1[i]);
4794 assem_debug("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
4795 assert(rt>=0);
4796 return_address=start+i*4+8;
4797 #ifdef REG_PREFETCH
4798 if(temp>=0)
4799 {
4800 if(i_regmap[temp]!=PTEMP) emit_movimm((int)hash_table[((return_address>>16)^return_address)&0xFFFF],temp);
4801 }
4802 #endif
4803 emit_movimm(return_address,rt); // PC into link register
4804 #ifdef IMM_PREFETCH
4805 emit_prefetch(hash_table[((return_address>>16)^return_address)&0xFFFF]);
4806 #endif
4807}
4808
57871462 4809void rjump_assemble(int i,struct regstat *i_regs)
4810{
4811 signed char *i_regmap=i_regs->regmap;
4812 int temp;
4813 int rs,cc,adj;
eba830cd 4814 int ra_done=0;
57871462 4815 rs=get_reg(branch_regs[i].regmap,rs1[i]);
4816 assert(rs>=0);
4817 if(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1]) {
4818 // Delay slot abuse, make a copy of the branch address register
4819 temp=get_reg(branch_regs[i].regmap,RTEMP);
4820 assert(temp>=0);
4821 assert(regs[i].regmap[temp]==RTEMP);
4822 emit_mov(rs,temp);
4823 rs=temp;
4824 }
4825 address_generation(i+1,i_regs,regs[i].regmap_entry);
4826 #ifdef REG_PREFETCH
4827 if(rt1[i]==31)
4828 {
4829 if((temp=get_reg(branch_regs[i].regmap,PTEMP))>=0) {
4830 int return_address=start+i*4+8;
4831 if(i_regmap[temp]==PTEMP) emit_movimm((int)hash_table[((return_address>>16)^return_address)&0xFFFF],temp);
4832 }
4833 }
4834 #endif
4835 #ifdef USE_MINI_HT
4836 if(rs1[i]==31) {
4837 int rh=get_reg(regs[i].regmap,RHASH);
4838 if(rh>=0) do_preload_rhash(rh);
4839 }
4840 #endif
eba830cd 4841 if(rt1[i]!=0&&(rt1[i]==rs1[i+1]||rt1[i]==rs2[i+1])) {
4842 rjump_assemble_write_ra(i);
4843 ra_done=1;
57871462 4844 }
d5910d5d 4845 ds_assemble(i+1,i_regs);
4846 uint64_t bc_unneeded=branch_regs[i].u;
4847 uint64_t bc_unneeded_upper=branch_regs[i].uu;
4848 bc_unneeded|=1|(1LL<<rt1[i]);
4849 bc_unneeded_upper|=1|(1LL<<rt1[i]);
4850 bc_unneeded&=~(1LL<<rs1[i]);
4851 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
4852 bc_unneeded,bc_unneeded_upper);
4853 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i],CCREG);
eba830cd 4854 if(!ra_done&&rt1[i]!=0)
4855 rjump_assemble_write_ra(i);
57871462 4856 cc=get_reg(branch_regs[i].regmap,CCREG);
4857 assert(cc==HOST_CCREG);
4858 #ifdef USE_MINI_HT
4859 int rh=get_reg(branch_regs[i].regmap,RHASH);
4860 int ht=get_reg(branch_regs[i].regmap,RHTBL);
4861 if(rs1[i]==31) {
4862 if(regs[i].regmap[rh]!=RHASH) do_preload_rhash(rh);
4863 do_preload_rhtbl(ht);
4864 do_rhash(rs,rh);
4865 }
4866 #endif
4867 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,-1);
4868 #ifdef DESTRUCTIVE_WRITEBACK
4869 if((branch_regs[i].dirty>>rs)&(branch_regs[i].is32>>rs1[i])&1) {
4870 if(rs1[i]!=rt1[i+1]&&rs1[i]!=rt2[i+1]) {
4871 emit_loadreg(rs1[i],rs);
4872 }
4873 }
4874 #endif
4875 #ifdef REG_PREFETCH
4876 if(rt1[i]==31&&temp>=0) emit_prefetchreg(temp);
4877 #endif
4878 #ifdef USE_MINI_HT
4879 if(rs1[i]==31) {
4880 do_miniht_load(ht,rh);
4881 }
4882 #endif
4883 //do_cc(i,branch_regs[i].regmap,&adj,-1,TAKEN);
4884 //if(adj) emit_addimm(cc,2*(ccadj[i]+2-adj),cc); // ??? - Shouldn't happen
4885 //assert(adj==0);
2573466a 4886 emit_addimm_and_set_flags(CLOCK_ADJUST(ccadj[i]+2),HOST_CCREG);
57871462 4887 add_stub(CC_STUB,(int)out,jump_vaddr_reg[rs],0,i,-1,TAKEN,0);
911f2d55 4888 if(itype[i+1]==COP0&&(source[i+1]&0x3f)==0x10)
4889 // special case for RFE
4890 emit_jmp(0);
4891 else
71e490c5 4892 emit_jns(0);
57871462 4893 //load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,-1);
4894 #ifdef USE_MINI_HT
4895 if(rs1[i]==31) {
4896 do_miniht_jump(rs,rh,ht);
4897 }
4898 else
4899 #endif
4900 {
4901 //if(rs!=EAX) emit_mov(rs,EAX);
4902 //emit_jmp((int)jump_vaddr_eax);
4903 emit_jmp(jump_vaddr_reg[rs]);
4904 }
4905 /* Check hash table
4906 temp=!rs;
4907 emit_mov(rs,temp);
4908 emit_shrimm(rs,16,rs);
4909 emit_xor(temp,rs,rs);
4910 emit_movzwl_reg(rs,rs);
4911 emit_shlimm(rs,4,rs);
4912 emit_cmpmem_indexed((int)hash_table,rs,temp);
4913 emit_jne((int)out+14);
4914 emit_readword_indexed((int)hash_table+4,rs,rs);
4915 emit_jmpreg(rs);
4916 emit_cmpmem_indexed((int)hash_table+8,rs,temp);
4917 emit_addimm_no_flags(8,rs);
4918 emit_jeq((int)out-17);
4919 // No hit on hash table, call compiler
4920 emit_pushreg(temp);
4921//DEBUG >
4922#ifdef DEBUG_CYCLE_COUNT
4923 emit_readword((int)&last_count,ECX);
4924 emit_add(HOST_CCREG,ECX,HOST_CCREG);
4925 emit_readword((int)&next_interupt,ECX);
4926 emit_writeword(HOST_CCREG,(int)&Count);
4927 emit_sub(HOST_CCREG,ECX,HOST_CCREG);
4928 emit_writeword(ECX,(int)&last_count);
4929#endif
4930//DEBUG <
4931 emit_storereg(CCREG,HOST_CCREG);
4932 emit_call((int)get_addr);
4933 emit_loadreg(CCREG,HOST_CCREG);
4934 emit_addimm(ESP,4,ESP);
4935 emit_jmpreg(EAX);*/
4936 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
4937 if(rt1[i]!=31&&i<slen-2&&(((u_int)out)&7)) emit_mov(13,13);
4938 #endif
4939}
4940
4941void cjump_assemble(int i,struct regstat *i_regs)
4942{
4943 signed char *i_regmap=i_regs->regmap;
4944 int cc;
4945 int match;
4946 match=match_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
4947 assem_debug("match=%d\n",match);
4948 int s1h,s1l,s2h,s2l;
4949 int prev_cop1_usable=cop1_usable;
4950 int unconditional=0,nop=0;
4951 int only32=0;
57871462 4952 int invert=0;
4953 int internal=internal_branch(branch_regs[i].is32,ba[i]);
4954 if(i==(ba[i]-start)>>2) assem_debug("idle loop\n");
57871462 4955 if(!match) invert=1;
4956 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
4957 if(i>(ba[i]-start)>>2) invert=1;
4958 #endif
e1190b87 4959
4960 if(ooo[i]) {
57871462 4961 s1l=get_reg(branch_regs[i].regmap,rs1[i]);
4962 s1h=get_reg(branch_regs[i].regmap,rs1[i]|64);
4963 s2l=get_reg(branch_regs[i].regmap,rs2[i]);
4964 s2h=get_reg(branch_regs[i].regmap,rs2[i]|64);
4965 }
4966 else {
4967 s1l=get_reg(i_regmap,rs1[i]);
4968 s1h=get_reg(i_regmap,rs1[i]|64);
4969 s2l=get_reg(i_regmap,rs2[i]);
4970 s2h=get_reg(i_regmap,rs2[i]|64);
4971 }
4972 if(rs1[i]==0&&rs2[i]==0)
4973 {
4974 if(opcode[i]&1) nop=1;
4975 else unconditional=1;
4976 //assert(opcode[i]!=5);
4977 //assert(opcode[i]!=7);
4978 //assert(opcode[i]!=0x15);
4979 //assert(opcode[i]!=0x17);
4980 }
4981 else if(rs1[i]==0)
4982 {
4983 s1l=s2l;s1h=s2h;
4984 s2l=s2h=-1;
4985 only32=(regs[i].was32>>rs2[i])&1;
4986 }
4987 else if(rs2[i]==0)
4988 {
4989 s2l=s2h=-1;
4990 only32=(regs[i].was32>>rs1[i])&1;
4991 }
4992 else {
4993 only32=(regs[i].was32>>rs1[i])&(regs[i].was32>>rs2[i])&1;
4994 }
4995
e1190b87 4996 if(ooo[i]) {
57871462 4997 // Out of order execution (delay slot first)
4998 //printf("OOOE\n");
4999 address_generation(i+1,i_regs,regs[i].regmap_entry);
5000 ds_assemble(i+1,i_regs);
5001 int adj;
5002 uint64_t bc_unneeded=branch_regs[i].u;
5003 uint64_t bc_unneeded_upper=branch_regs[i].uu;
5004 bc_unneeded&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
5005 bc_unneeded_upper&=~((1LL<<us1[i])|(1LL<<us2[i]));
5006 bc_unneeded|=1;
5007 bc_unneeded_upper|=1;
5008 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5009 bc_unneeded,bc_unneeded_upper);
5010 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i],rs2[i]);
5011 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
5012 cc=get_reg(branch_regs[i].regmap,CCREG);
5013 assert(cc==HOST_CCREG);
5014 if(unconditional)
5015 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5016 //do_cc(i,branch_regs[i].regmap,&adj,unconditional?ba[i]:-1,unconditional);
5017 //assem_debug("cycle count (adj)\n");
5018 if(unconditional) {
5019 do_cc(i,branch_regs[i].regmap,&adj,ba[i],TAKEN,0);
5020 if(i!=(ba[i]-start)>>2 || source[i+1]!=0) {
2573466a 5021 if(adj) emit_addimm(cc,CLOCK_ADJUST(ccadj[i]+2-adj),cc);
57871462 5022 load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5023 if(internal)
5024 assem_debug("branch: internal\n");
5025 else
5026 assem_debug("branch: external\n");
5027 if(internal&&is_ds[(ba[i]-start)>>2]) {
5028 ds_assemble_entry(i);
5029 }
5030 else {
5031 add_to_linker((int)out,ba[i],internal);
5032 emit_jmp(0);
5033 }
5034 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5035 if(((u_int)out)&7) emit_addnop(0);
5036 #endif
5037 }
5038 }
5039 else if(nop) {
2573466a 5040 emit_addimm_and_set_flags(CLOCK_ADJUST(ccadj[i]+2),cc);
57871462 5041 int jaddr=(int)out;
5042 emit_jns(0);
5043 add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,NOTTAKEN,0);
5044 }
5045 else {
5046 int taken=0,nottaken=0,nottaken1=0;
5047 do_cc(i,branch_regs[i].regmap,&adj,-1,0,invert);
2573466a 5048 if(adj&&!invert) emit_addimm(cc,CLOCK_ADJUST(ccadj[i]+2-adj),cc);
57871462 5049 if(!only32)
5050 {
5051 assert(s1h>=0);
5052 if(opcode[i]==4) // BEQ
5053 {
5054 if(s2h>=0) emit_cmp(s1h,s2h);
5055 else emit_test(s1h,s1h);
5056 nottaken1=(int)out;
5057 emit_jne(1);
5058 }
5059 if(opcode[i]==5) // BNE
5060 {
5061 if(s2h>=0) emit_cmp(s1h,s2h);
5062 else emit_test(s1h,s1h);
5063 if(invert) taken=(int)out;
5064 else add_to_linker((int)out,ba[i],internal);
5065 emit_jne(0);
5066 }
5067 if(opcode[i]==6) // BLEZ
5068 {
5069 emit_test(s1h,s1h);
5070 if(invert) taken=(int)out;
5071 else add_to_linker((int)out,ba[i],internal);
5072 emit_js(0);
5073 nottaken1=(int)out;
5074 emit_jne(1);
5075 }
5076 if(opcode[i]==7) // BGTZ
5077 {
5078 emit_test(s1h,s1h);
5079 nottaken1=(int)out;
5080 emit_js(1);
5081 if(invert) taken=(int)out;
5082 else add_to_linker((int)out,ba[i],internal);
5083 emit_jne(0);
5084 }
5085 } // if(!only32)
5086
5087 //printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5088 assert(s1l>=0);
5089 if(opcode[i]==4) // BEQ
5090 {
5091 if(s2l>=0) emit_cmp(s1l,s2l);
5092 else emit_test(s1l,s1l);
5093 if(invert){
5094 nottaken=(int)out;
5095 emit_jne(1);
5096 }else{
5097 add_to_linker((int)out,ba[i],internal);
5098 emit_jeq(0);
5099 }
5100 }
5101 if(opcode[i]==5) // BNE
5102 {
5103 if(s2l>=0) emit_cmp(s1l,s2l);
5104 else emit_test(s1l,s1l);
5105 if(invert){
5106 nottaken=(int)out;
5107 emit_jeq(1);
5108 }else{
5109 add_to_linker((int)out,ba[i],internal);
5110 emit_jne(0);
5111 }
5112 }
5113 if(opcode[i]==6) // BLEZ
5114 {
5115 emit_cmpimm(s1l,1);
5116 if(invert){
5117 nottaken=(int)out;
5118 emit_jge(1);
5119 }else{
5120 add_to_linker((int)out,ba[i],internal);
5121 emit_jl(0);
5122 }
5123 }
5124 if(opcode[i]==7) // BGTZ
5125 {
5126 emit_cmpimm(s1l,1);
5127 if(invert){
5128 nottaken=(int)out;
5129 emit_jl(1);
5130 }else{
5131 add_to_linker((int)out,ba[i],internal);
5132 emit_jge(0);
5133 }
5134 }
5135 if(invert) {
5136 if(taken) set_jump_target(taken,(int)out);
5137 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5138 if(match&&(!internal||!is_ds[(ba[i]-start)>>2])) {
5139 if(adj) {
2573466a 5140 emit_addimm(cc,-CLOCK_ADJUST(adj),cc);
57871462 5141 add_to_linker((int)out,ba[i],internal);
5142 }else{
5143 emit_addnop(13);
5144 add_to_linker((int)out,ba[i],internal*2);
5145 }
5146 emit_jmp(0);
5147 }else
5148 #endif
5149 {
2573466a 5150 if(adj) emit_addimm(cc,-CLOCK_ADJUST(adj),cc);
57871462 5151 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5152 load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5153 if(internal)
5154 assem_debug("branch: internal\n");
5155 else
5156 assem_debug("branch: external\n");
5157 if(internal&&is_ds[(ba[i]-start)>>2]) {
5158 ds_assemble_entry(i);
5159 }
5160 else {
5161 add_to_linker((int)out,ba[i],internal);
5162 emit_jmp(0);
5163 }
5164 }
5165 set_jump_target(nottaken,(int)out);
5166 }
5167
5168 if(nottaken1) set_jump_target(nottaken1,(int)out);
5169 if(adj) {
2573466a 5170 if(!invert) emit_addimm(cc,CLOCK_ADJUST(adj),cc);
57871462 5171 }
5172 } // (!unconditional)
5173 } // if(ooo)
5174 else
5175 {
5176 // In-order execution (branch first)
5177 //if(likely[i]) printf("IOL\n");
5178 //else
5179 //printf("IOE\n");
5180 int taken=0,nottaken=0,nottaken1=0;
5181 if(!unconditional&&!nop) {
5182 if(!only32)
5183 {
5184 assert(s1h>=0);
5185 if((opcode[i]&0x2f)==4) // BEQ
5186 {
5187 if(s2h>=0) emit_cmp(s1h,s2h);
5188 else emit_test(s1h,s1h);
5189 nottaken1=(int)out;
5190 emit_jne(2);
5191 }
5192 if((opcode[i]&0x2f)==5) // BNE
5193 {
5194 if(s2h>=0) emit_cmp(s1h,s2h);
5195 else emit_test(s1h,s1h);
5196 taken=(int)out;
5197 emit_jne(1);
5198 }
5199 if((opcode[i]&0x2f)==6) // BLEZ
5200 {
5201 emit_test(s1h,s1h);
5202 taken=(int)out;
5203 emit_js(1);
5204 nottaken1=(int)out;
5205 emit_jne(2);
5206 }
5207 if((opcode[i]&0x2f)==7) // BGTZ
5208 {
5209 emit_test(s1h,s1h);
5210 nottaken1=(int)out;
5211 emit_js(2);
5212 taken=(int)out;
5213 emit_jne(1);
5214 }
5215 } // if(!only32)
5216
5217 //printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5218 assert(s1l>=0);
5219 if((opcode[i]&0x2f)==4) // BEQ
5220 {
5221 if(s2l>=0) emit_cmp(s1l,s2l);
5222 else emit_test(s1l,s1l);
5223 nottaken=(int)out;
5224 emit_jne(2);
5225 }
5226 if((opcode[i]&0x2f)==5) // BNE
5227 {
5228 if(s2l>=0) emit_cmp(s1l,s2l);
5229 else emit_test(s1l,s1l);
5230 nottaken=(int)out;
5231 emit_jeq(2);
5232 }
5233 if((opcode[i]&0x2f)==6) // BLEZ
5234 {
5235 emit_cmpimm(s1l,1);
5236 nottaken=(int)out;
5237 emit_jge(2);
5238 }
5239 if((opcode[i]&0x2f)==7) // BGTZ
5240 {
5241 emit_cmpimm(s1l,1);
5242 nottaken=(int)out;
5243 emit_jl(2);
5244 }
5245 } // if(!unconditional)
5246 int adj;
5247 uint64_t ds_unneeded=branch_regs[i].u;
5248 uint64_t ds_unneeded_upper=branch_regs[i].uu;
5249 ds_unneeded&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
5250 ds_unneeded_upper&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
5251 if((~ds_unneeded_upper>>rt1[i+1])&1) ds_unneeded_upper&=~((1LL<<dep1[i+1])|(1LL<<dep2[i+1]));
5252 ds_unneeded|=1;
5253 ds_unneeded_upper|=1;
5254 // branch taken
5255 if(!nop) {
5256 if(taken) set_jump_target(taken,(int)out);
5257 assem_debug("1:\n");
5258 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5259 ds_unneeded,ds_unneeded_upper);
5260 // load regs
5261 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
5262 address_generation(i+1,&branch_regs[i],0);
5263 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,INVCP);
5264 ds_assemble(i+1,&branch_regs[i]);
5265 cc=get_reg(branch_regs[i].regmap,CCREG);
5266 if(cc==-1) {
5267 emit_loadreg(CCREG,cc=HOST_CCREG);
5268 // CHECK: Is the following instruction (fall thru) allocated ok?
5269 }
5270 assert(cc==HOST_CCREG);
5271 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5272 do_cc(i,i_regmap,&adj,ba[i],TAKEN,0);
5273 assem_debug("cycle count (adj)\n");
2573466a 5274 if(adj) emit_addimm(cc,CLOCK_ADJUST(ccadj[i]+2-adj),cc);
57871462 5275 load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5276 if(internal)
5277 assem_debug("branch: internal\n");
5278 else
5279 assem_debug("branch: external\n");
5280 if(internal&&is_ds[(ba[i]-start)>>2]) {
5281 ds_assemble_entry(i);
5282 }
5283 else {
5284 add_to_linker((int)out,ba[i],internal);
5285 emit_jmp(0);
5286 }
5287 }
5288 // branch not taken
5289 cop1_usable=prev_cop1_usable;
5290 if(!unconditional) {
5291 if(nottaken1) set_jump_target(nottaken1,(int)out);
5292 set_jump_target(nottaken,(int)out);
5293 assem_debug("2:\n");
5294 if(!likely[i]) {
5295 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5296 ds_unneeded,ds_unneeded_upper);
5297 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
5298 address_generation(i+1,&branch_regs[i],0);
5299 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
5300 ds_assemble(i+1,&branch_regs[i]);
5301 }
5302 cc=get_reg(branch_regs[i].regmap,CCREG);
5303 if(cc==-1&&!likely[i]) {
5304 // Cycle count isn't in a register, temporarily load it then write it out
5305 emit_loadreg(CCREG,HOST_CCREG);
2573466a 5306 emit_addimm_and_set_flags(CLOCK_ADJUST(ccadj[i]+2),HOST_CCREG);
57871462 5307 int jaddr=(int)out;
5308 emit_jns(0);
5309 add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,NOTTAKEN,0);
5310 emit_storereg(CCREG,HOST_CCREG);
5311 }
5312 else{
5313 cc=get_reg(i_regmap,CCREG);
5314 assert(cc==HOST_CCREG);
2573466a 5315 emit_addimm_and_set_flags(CLOCK_ADJUST(ccadj[i]+2),cc);
57871462 5316 int jaddr=(int)out;
5317 emit_jns(0);
5318 add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,likely[i]?NULLDS:NOTTAKEN,0);
5319 }
5320 }
5321 }
5322}
5323
5324void sjump_assemble(int i,struct regstat *i_regs)
5325{
5326 signed char *i_regmap=i_regs->regmap;
5327 int cc;
5328 int match;
5329 match=match_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5330 assem_debug("smatch=%d\n",match);
5331 int s1h,s1l;
5332 int prev_cop1_usable=cop1_usable;
5333 int unconditional=0,nevertaken=0;
5334 int only32=0;
57871462 5335 int invert=0;
5336 int internal=internal_branch(branch_regs[i].is32,ba[i]);
5337 if(i==(ba[i]-start)>>2) assem_debug("idle loop\n");
57871462 5338 if(!match) invert=1;
5339 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5340 if(i>(ba[i]-start)>>2) invert=1;
5341 #endif
5342
5343 //if(opcode2[i]>=0x10) return; // FIXME (BxxZAL)
df894a3a 5344 //assert(opcode2[i]<0x10||rs1[i]==0); // FIXME (BxxZAL)
57871462 5345
e1190b87 5346 if(ooo[i]) {
57871462 5347 s1l=get_reg(branch_regs[i].regmap,rs1[i]);
5348 s1h=get_reg(branch_regs[i].regmap,rs1[i]|64);
5349 }
5350 else {
5351 s1l=get_reg(i_regmap,rs1[i]);
5352 s1h=get_reg(i_regmap,rs1[i]|64);
5353 }
5354 if(rs1[i]==0)
5355 {
5356 if(opcode2[i]&1) unconditional=1;
5357 else nevertaken=1;
5358 // These are never taken (r0 is never less than zero)
5359 //assert(opcode2[i]!=0);
5360 //assert(opcode2[i]!=2);
5361 //assert(opcode2[i]!=0x10);
5362 //assert(opcode2[i]!=0x12);
5363 }
5364 else {
5365 only32=(regs[i].was32>>rs1[i])&1;
5366 }
5367
e1190b87 5368 if(ooo[i]) {
57871462 5369 // Out of order execution (delay slot first)
5370 //printf("OOOE\n");
5371 address_generation(i+1,i_regs,regs[i].regmap_entry);
5372 ds_assemble(i+1,i_regs);
5373 int adj;
5374 uint64_t bc_unneeded=branch_regs[i].u;
5375 uint64_t bc_unneeded_upper=branch_regs[i].uu;
5376 bc_unneeded&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
5377 bc_unneeded_upper&=~((1LL<<us1[i])|(1LL<<us2[i]));
5378 bc_unneeded|=1;
5379 bc_unneeded_upper|=1;
5380 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5381 bc_unneeded,bc_unneeded_upper);
5382 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i],rs1[i]);
5383 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
5384 if(rt1[i]==31) {
5385 int rt,return_address;
57871462 5386 rt=get_reg(branch_regs[i].regmap,31);
5387 assem_debug("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5388 if(rt>=0) {
5389 // Save the PC even if the branch is not taken
5390 return_address=start+i*4+8;
5391 emit_movimm(return_address,rt); // PC into link register
5392 #ifdef IMM_PREFETCH
5393 if(!nevertaken) emit_prefetch(hash_table[((return_address>>16)^return_address)&0xFFFF]);
5394 #endif
5395 }
5396 }
5397 cc=get_reg(branch_regs[i].regmap,CCREG);
5398 assert(cc==HOST_CCREG);
5399 if(unconditional)
5400 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5401 //do_cc(i,branch_regs[i].regmap,&adj,unconditional?ba[i]:-1,unconditional);
5402 assem_debug("cycle count (adj)\n");
5403 if(unconditional) {
5404 do_cc(i,branch_regs[i].regmap,&adj,ba[i],TAKEN,0);
5405 if(i!=(ba[i]-start)>>2 || source[i+1]!=0) {
2573466a 5406 if(adj) emit_addimm(cc,CLOCK_ADJUST(ccadj[i]+2-adj),cc);
57871462 5407 load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5408 if(internal)
5409 assem_debug("branch: internal\n");
5410 else
5411 assem_debug("branch: external\n");
5412 if(internal&&is_ds[(ba[i]-start)>>2]) {
5413 ds_assemble_entry(i);
5414 }
5415 else {
5416 add_to_linker((int)out,ba[i],internal);
5417 emit_jmp(0);
5418 }
5419 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5420 if(((u_int)out)&7) emit_addnop(0);
5421 #endif
5422 }
5423 }
5424 else if(nevertaken) {
2573466a 5425 emit_addimm_and_set_flags(CLOCK_ADJUST(ccadj[i]+2),cc);
57871462 5426 int jaddr=(int)out;
5427 emit_jns(0);
5428 add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,NOTTAKEN,0);
5429 }
5430 else {
5431 int nottaken=0;
5432 do_cc(i,branch_regs[i].regmap,&adj,-1,0,invert);
2573466a 5433 if(adj&&!invert) emit_addimm(cc,CLOCK_ADJUST(ccadj[i]+2-adj),cc);
57871462 5434 if(!only32)
5435 {
5436 assert(s1h>=0);
df894a3a 5437 if((opcode2[i]&0xf)==0) // BLTZ/BLTZAL
57871462 5438 {
5439 emit_test(s1h,s1h);
5440 if(invert){
5441 nottaken=(int)out;
5442 emit_jns(1);
5443 }else{
5444 add_to_linker((int)out,ba[i],internal);
5445 emit_js(0);
5446 }
5447 }
df894a3a 5448 if((opcode2[i]&0xf)==1) // BGEZ/BLTZAL
57871462 5449 {
5450 emit_test(s1h,s1h);
5451 if(invert){
5452 nottaken=(int)out;
5453 emit_js(1);
5454 }else{
5455 add_to_linker((int)out,ba[i],internal);
5456 emit_jns(0);
5457 }
5458 }
5459 } // if(!only32)
5460 else
5461 {
5462 assert(s1l>=0);
df894a3a 5463 if((opcode2[i]&0xf)==0) // BLTZ/BLTZAL
57871462 5464 {
5465 emit_test(s1l,s1l);
5466 if(invert){
5467 nottaken=(int)out;
5468 emit_jns(1);
5469 }else{
5470 add_to_linker((int)out,ba[i],internal);
5471 emit_js(0);
5472 }
5473 }
df894a3a 5474 if((opcode2[i]&0xf)==1) // BGEZ/BLTZAL
57871462 5475 {
5476 emit_test(s1l,s1l);
5477 if(invert){
5478 nottaken=(int)out;
5479 emit_js(1);
5480 }else{
5481 add_to_linker((int)out,ba[i],internal);
5482 emit_jns(0);
5483 }
5484 }
5485 } // if(!only32)
5486
5487 if(invert) {
5488 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5489 if(match&&(!internal||!is_ds[(ba[i]-start)>>2])) {
5490 if(adj) {
2573466a 5491 emit_addimm(cc,-CLOCK_ADJUST(adj),cc);
57871462 5492 add_to_linker((int)out,ba[i],internal);
5493 }else{
5494 emit_addnop(13);
5495 add_to_linker((int)out,ba[i],internal*2);
5496 }
5497 emit_jmp(0);
5498 }else
5499 #endif
5500 {
2573466a 5501 if(adj) emit_addimm(cc,-CLOCK_ADJUST(adj),cc);
57871462 5502 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5503 load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5504 if(internal)
5505 assem_debug("branch: internal\n");
5506 else
5507 assem_debug("branch: external\n");
5508 if(internal&&is_ds[(ba[i]-start)>>2]) {
5509 ds_assemble_entry(i);
5510 }
5511 else {
5512 add_to_linker((int)out,ba[i],internal);
5513 emit_jmp(0);
5514 }
5515 }
5516 set_jump_target(nottaken,(int)out);
5517 }
5518
5519 if(adj) {
2573466a 5520 if(!invert) emit_addimm(cc,CLOCK_ADJUST(adj),cc);
57871462 5521 }
5522 } // (!unconditional)
5523 } // if(ooo)
5524 else
5525 {
5526 // In-order execution (branch first)
5527 //printf("IOE\n");
5528 int nottaken=0;
a6491170 5529 if(rt1[i]==31) {
5530 int rt,return_address;
a6491170 5531 rt=get_reg(branch_regs[i].regmap,31);
5532 if(rt>=0) {
5533 // Save the PC even if the branch is not taken
5534 return_address=start+i*4+8;
5535 emit_movimm(return_address,rt); // PC into link register
5536 #ifdef IMM_PREFETCH
5537 emit_prefetch(hash_table[((return_address>>16)^return_address)&0xFFFF]);
5538 #endif
5539 }
5540 }
57871462 5541 if(!unconditional) {
5542 //printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5543 if(!only32)
5544 {
5545 assert(s1h>=0);
a6491170 5546 if((opcode2[i]&0x0d)==0) // BLTZ/BLTZL/BLTZAL/BLTZALL
57871462 5547 {
5548 emit_test(s1h,s1h);
5549 nottaken=(int)out;
5550 emit_jns(1);
5551 }
a6491170 5552 if((opcode2[i]&0x0d)==1) // BGEZ/BGEZL/BGEZAL/BGEZALL
57871462 5553 {
5554 emit_test(s1h,s1h);
5555 nottaken=(int)out;
5556 emit_js(1);
5557 }
5558 } // if(!only32)
5559 else
5560 {
5561 assert(s1l>=0);
a6491170 5562 if((opcode2[i]&0x0d)==0) // BLTZ/BLTZL/BLTZAL/BLTZALL
57871462 5563 {
5564 emit_test(s1l,s1l);
5565 nottaken=(int)out;
5566 emit_jns(1);
5567 }
a6491170 5568 if((opcode2[i]&0x0d)==1) // BGEZ/BGEZL/BGEZAL/BGEZALL
57871462 5569 {
5570 emit_test(s1l,s1l);
5571 nottaken=(int)out;
5572 emit_js(1);
5573 }
5574 }
5575 } // if(!unconditional)
5576 int adj;
5577 uint64_t ds_unneeded=branch_regs[i].u;
5578 uint64_t ds_unneeded_upper=branch_regs[i].uu;
5579 ds_unneeded&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
5580 ds_unneeded_upper&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
5581 if((~ds_unneeded_upper>>rt1[i+1])&1) ds_unneeded_upper&=~((1LL<<dep1[i+1])|(1LL<<dep2[i+1]));
5582 ds_unneeded|=1;
5583 ds_unneeded_upper|=1;
5584 // branch taken
5585 if(!nevertaken) {
5586 //assem_debug("1:\n");
5587 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5588 ds_unneeded,ds_unneeded_upper);
5589 // load regs
5590 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
5591 address_generation(i+1,&branch_regs[i],0);
5592 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,INVCP);
5593 ds_assemble(i+1,&branch_regs[i]);
5594 cc=get_reg(branch_regs[i].regmap,CCREG);
5595 if(cc==-1) {
5596 emit_loadreg(CCREG,cc=HOST_CCREG);
5597 // CHECK: Is the following instruction (fall thru) allocated ok?
5598 }
5599 assert(cc==HOST_CCREG);
5600 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5601 do_cc(i,i_regmap,&adj,ba[i],TAKEN,0);
5602 assem_debug("cycle count (adj)\n");
2573466a 5603 if(adj) emit_addimm(cc,CLOCK_ADJUST(ccadj[i]+2-adj),cc);
57871462 5604 load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5605 if(internal)
5606 assem_debug("branch: internal\n");
5607 else
5608 assem_debug("branch: external\n");
5609 if(internal&&is_ds[(ba[i]-start)>>2]) {
5610 ds_assemble_entry(i);
5611 }
5612 else {
5613 add_to_linker((int)out,ba[i],internal);
5614 emit_jmp(0);
5615 }
5616 }
5617 // branch not taken
5618 cop1_usable=prev_cop1_usable;
5619 if(!unconditional) {
5620 set_jump_target(nottaken,(int)out);
5621 assem_debug("1:\n");
5622 if(!likely[i]) {
5623 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5624 ds_unneeded,ds_unneeded_upper);
5625 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
5626 address_generation(i+1,&branch_regs[i],0);
5627 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
5628 ds_assemble(i+1,&branch_regs[i]);
5629 }
5630 cc=get_reg(branch_regs[i].regmap,CCREG);
5631 if(cc==-1&&!likely[i]) {
5632 // Cycle count isn't in a register, temporarily load it then write it out
5633 emit_loadreg(CCREG,HOST_CCREG);
2573466a 5634 emit_addimm_and_set_flags(CLOCK_ADJUST(ccadj[i]+2),HOST_CCREG);
57871462 5635 int jaddr=(int)out;
5636 emit_jns(0);
5637 add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,NOTTAKEN,0);
5638 emit_storereg(CCREG,HOST_CCREG);
5639 }
5640 else{
5641 cc=get_reg(i_regmap,CCREG);
5642 assert(cc==HOST_CCREG);
2573466a 5643 emit_addimm_and_set_flags(CLOCK_ADJUST(ccadj[i]+2),cc);
57871462 5644 int jaddr=(int)out;
5645 emit_jns(0);
5646 add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,likely[i]?NULLDS:NOTTAKEN,0);
5647 }
5648 }
5649 }
5650}
5651
5652void fjump_assemble(int i,struct regstat *i_regs)
5653{
5654 signed char *i_regmap=i_regs->regmap;
5655 int cc;
5656 int match;
5657 match=match_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5658 assem_debug("fmatch=%d\n",match);
5659 int fs,cs;
5660 int eaddr;
57871462 5661 int invert=0;
5662 int internal=internal_branch(branch_regs[i].is32,ba[i]);
5663 if(i==(ba[i]-start)>>2) assem_debug("idle loop\n");
57871462 5664 if(!match) invert=1;
5665 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5666 if(i>(ba[i]-start)>>2) invert=1;
5667 #endif
5668
e1190b87 5669 if(ooo[i]) {
57871462 5670 fs=get_reg(branch_regs[i].regmap,FSREG);
5671 address_generation(i+1,i_regs,regs[i].regmap_entry); // Is this okay?
5672 }
5673 else {
5674 fs=get_reg(i_regmap,FSREG);
5675 }
5676
5677 // Check cop1 unusable
5678 if(!cop1_usable) {
5679 cs=get_reg(i_regmap,CSREG);
5680 assert(cs>=0);
5681 emit_testimm(cs,0x20000000);
5682 eaddr=(int)out;
5683 emit_jeq(0);
5684 add_stub(FP_STUB,eaddr,(int)out,i,cs,(int)i_regs,0,0);
5685 cop1_usable=1;
5686 }
5687
e1190b87 5688 if(ooo[i]) {
57871462 5689 // Out of order execution (delay slot first)
5690 //printf("OOOE\n");
5691 ds_assemble(i+1,i_regs);
5692 int adj;
5693 uint64_t bc_unneeded=branch_regs[i].u;
5694 uint64_t bc_unneeded_upper=branch_regs[i].uu;
5695 bc_unneeded&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
5696 bc_unneeded_upper&=~((1LL<<us1[i])|(1LL<<us2[i]));
5697 bc_unneeded|=1;
5698 bc_unneeded_upper|=1;
5699 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5700 bc_unneeded,bc_unneeded_upper);
5701 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i],rs1[i]);
5702 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
5703 cc=get_reg(branch_regs[i].regmap,CCREG);
5704 assert(cc==HOST_CCREG);
5705 do_cc(i,branch_regs[i].regmap,&adj,-1,0,invert);
5706 assem_debug("cycle count (adj)\n");
5707 if(1) {
5708 int nottaken=0;
2573466a 5709 if(adj&&!invert) emit_addimm(cc,CLOCK_ADJUST(ccadj[i]+2-adj),cc);
57871462 5710 if(1) {
5711 assert(fs>=0);
5712 emit_testimm(fs,0x800000);
5713 if(source[i]&0x10000) // BC1T
5714 {
5715 if(invert){
5716 nottaken=(int)out;
5717 emit_jeq(1);
5718 }else{
5719 add_to_linker((int)out,ba[i],internal);
5720 emit_jne(0);
5721 }
5722 }
5723 else // BC1F
5724 if(invert){
5725 nottaken=(int)out;
5726 emit_jne(1);
5727 }else{
5728 add_to_linker((int)out,ba[i],internal);
5729 emit_jeq(0);
5730 }
5731 {
5732 }
5733 } // if(!only32)
5734
5735 if(invert) {
2573466a 5736 if(adj) emit_addimm(cc,-CLOCK_ADJUST(adj),cc);
57871462 5737 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5738 else if(match) emit_addnop(13);
5739 #endif
5740 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5741 load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5742 if(internal)
5743 assem_debug("branch: internal\n");
5744 else
5745 assem_debug("branch: external\n");
5746 if(internal&&is_ds[(ba[i]-start)>>2]) {
5747 ds_assemble_entry(i);
5748 }
5749 else {
5750 add_to_linker((int)out,ba[i],internal);
5751 emit_jmp(0);
5752 }
5753 set_jump_target(nottaken,(int)out);
5754 }
5755
5756 if(adj) {
2573466a 5757 if(!invert) emit_addimm(cc,CLOCK_ADJUST(adj),cc);
57871462 5758 }
5759 } // (!unconditional)
5760 } // if(ooo)
5761 else
5762 {
5763 // In-order execution (branch first)
5764 //printf("IOE\n");
5765 int nottaken=0;
5766 if(1) {
5767 //printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5768 if(1) {
5769 assert(fs>=0);
5770 emit_testimm(fs,0x800000);
5771 if(source[i]&0x10000) // BC1T
5772 {
5773 nottaken=(int)out;
5774 emit_jeq(1);
5775 }
5776 else // BC1F
5777 {
5778 nottaken=(int)out;
5779 emit_jne(1);
5780 }
5781 }
5782 } // if(!unconditional)
5783 int adj;
5784 uint64_t ds_unneeded=branch_regs[i].u;
5785 uint64_t ds_unneeded_upper=branch_regs[i].uu;
5786 ds_unneeded&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
5787 ds_unneeded_upper&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
5788 if((~ds_unneeded_upper>>rt1[i+1])&1) ds_unneeded_upper&=~((1LL<<dep1[i+1])|(1LL<<dep2[i+1]));
5789 ds_unneeded|=1;
5790 ds_unneeded_upper|=1;
5791 // branch taken
5792 //assem_debug("1:\n");
5793 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5794 ds_unneeded,ds_unneeded_upper);
5795 // load regs
5796 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
5797 address_generation(i+1,&branch_regs[i],0);
5798 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,INVCP);
5799 ds_assemble(i+1,&branch_regs[i]);
5800 cc=get_reg(branch_regs[i].regmap,CCREG);
5801 if(cc==-1) {
5802 emit_loadreg(CCREG,cc=HOST_CCREG);
5803 // CHECK: Is the following instruction (fall thru) allocated ok?
5804 }
5805 assert(cc==HOST_CCREG);
5806 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5807 do_cc(i,i_regmap,&adj,ba[i],TAKEN,0);
5808 assem_debug("cycle count (adj)\n");
2573466a 5809 if(adj) emit_addimm(cc,CLOCK_ADJUST(ccadj[i]+2-adj),cc);
57871462 5810 load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5811 if(internal)
5812 assem_debug("branch: internal\n");
5813 else
5814 assem_debug("branch: external\n");
5815 if(internal&&is_ds[(ba[i]-start)>>2]) {
5816 ds_assemble_entry(i);
5817 }
5818 else {
5819 add_to_linker((int)out,ba[i],internal);
5820 emit_jmp(0);
5821 }
5822
5823 // branch not taken
5824 if(1) { // <- FIXME (don't need this)
5825 set_jump_target(nottaken,(int)out);
5826 assem_debug("1:\n");
5827 if(!likely[i]) {
5828 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5829 ds_unneeded,ds_unneeded_upper);
5830 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
5831 address_generation(i+1,&branch_regs[i],0);
5832 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
5833 ds_assemble(i+1,&branch_regs[i]);
5834 }
5835 cc=get_reg(branch_regs[i].regmap,CCREG);
5836 if(cc==-1&&!likely[i]) {
5837 // Cycle count isn't in a register, temporarily load it then write it out
5838 emit_loadreg(CCREG,HOST_CCREG);
2573466a 5839 emit_addimm_and_set_flags(CLOCK_ADJUST(ccadj[i]+2),HOST_CCREG);
57871462 5840 int jaddr=(int)out;
5841 emit_jns(0);
5842 add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,NOTTAKEN,0);
5843 emit_storereg(CCREG,HOST_CCREG);
5844 }
5845 else{
5846 cc=get_reg(i_regmap,CCREG);
5847 assert(cc==HOST_CCREG);
2573466a 5848 emit_addimm_and_set_flags(CLOCK_ADJUST(ccadj[i]+2),cc);
57871462 5849 int jaddr=(int)out;
5850 emit_jns(0);
5851 add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,likely[i]?NULLDS:NOTTAKEN,0);
5852 }
5853 }
5854 }
5855}
5856
5857static void pagespan_assemble(int i,struct regstat *i_regs)
5858{
5859 int s1l=get_reg(i_regs->regmap,rs1[i]);
5860 int s1h=get_reg(i_regs->regmap,rs1[i]|64);
5861 int s2l=get_reg(i_regs->regmap,rs2[i]);
5862 int s2h=get_reg(i_regs->regmap,rs2[i]|64);
5863 void *nt_branch=NULL;
5864 int taken=0;
5865 int nottaken=0;
5866 int unconditional=0;
5867 if(rs1[i]==0)
5868 {
5869 s1l=s2l;s1h=s2h;
5870 s2l=s2h=-1;
5871 }
5872 else if(rs2[i]==0)
5873 {
5874 s2l=s2h=-1;
5875 }
5876 if((i_regs->is32>>rs1[i])&(i_regs->is32>>rs2[i])&1) {
5877 s1h=s2h=-1;
5878 }
5879 int hr=0;
5880 int addr,alt,ntaddr;
5881 if(i_regs->regmap[HOST_BTREG]<0) {addr=HOST_BTREG;}
5882 else {
5883 while(hr<HOST_REGS)
5884 {
5885 if(hr!=EXCLUDE_REG && hr!=HOST_CCREG &&
5886 (i_regs->regmap[hr]&63)!=rs1[i] &&
5887 (i_regs->regmap[hr]&63)!=rs2[i] )
5888 {
5889 addr=hr++;break;
5890 }
5891 hr++;
5892 }
5893 }
5894 while(hr<HOST_REGS)
5895 {
5896 if(hr!=EXCLUDE_REG && hr!=HOST_CCREG && hr!=HOST_BTREG &&
5897 (i_regs->regmap[hr]&63)!=rs1[i] &&
5898 (i_regs->regmap[hr]&63)!=rs2[i] )
5899 {
5900 alt=hr++;break;
5901 }
5902 hr++;
5903 }
5904 if((opcode[i]&0x2E)==6) // BLEZ/BGTZ needs another register
5905 {
5906 while(hr<HOST_REGS)
5907 {
5908 if(hr!=EXCLUDE_REG && hr!=HOST_CCREG && hr!=HOST_BTREG &&
5909 (i_regs->regmap[hr]&63)!=rs1[i] &&
5910 (i_regs->regmap[hr]&63)!=rs2[i] )
5911 {
5912 ntaddr=hr;break;
5913 }
5914 hr++;
5915 }
5916 }
5917 assert(hr<HOST_REGS);
5918 if((opcode[i]&0x2e)==4||opcode[i]==0x11) { // BEQ/BNE/BEQL/BNEL/BC1
5919 load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,CCREG,CCREG);
5920 }
2573466a 5921 emit_addimm(HOST_CCREG,CLOCK_ADJUST(ccadj[i]+2),HOST_CCREG);
57871462 5922 if(opcode[i]==2) // J
5923 {
5924 unconditional=1;
5925 }
5926 if(opcode[i]==3) // JAL
5927 {
5928 // TODO: mini_ht
5929 int rt=get_reg(i_regs->regmap,31);
5930 emit_movimm(start+i*4+8,rt);
5931 unconditional=1;
5932 }
5933 if(opcode[i]==0&&(opcode2[i]&0x3E)==8) // JR/JALR
5934 {
5935 emit_mov(s1l,addr);
5936 if(opcode2[i]==9) // JALR
5937 {
5067f341 5938 int rt=get_reg(i_regs->regmap,rt1[i]);
57871462 5939 emit_movimm(start+i*4+8,rt);
5940 }
5941 }
5942 if((opcode[i]&0x3f)==4) // BEQ
5943 {
5944 if(rs1[i]==rs2[i])
5945 {
5946 unconditional=1;
5947 }
5948 else
5949 #ifdef HAVE_CMOV_IMM
5950 if(s1h<0) {
5951 if(s2l>=0) emit_cmp(s1l,s2l);
5952 else emit_test(s1l,s1l);
5953 emit_cmov2imm_e_ne_compact(ba[i],start+i*4+8,addr);
5954 }
5955 else
5956 #endif
5957 {
5958 assert(s1l>=0);
5959 emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
5960 if(s1h>=0) {
5961 if(s2h>=0) emit_cmp(s1h,s2h);
5962 else emit_test(s1h,s1h);
5963 emit_cmovne_reg(alt,addr);
5964 }
5965 if(s2l>=0) emit_cmp(s1l,s2l);
5966 else emit_test(s1l,s1l);
5967 emit_cmovne_reg(alt,addr);
5968 }
5969 }
5970 if((opcode[i]&0x3f)==5) // BNE
5971 {
5972 #ifdef HAVE_CMOV_IMM
5973 if(s1h<0) {
5974 if(s2l>=0) emit_cmp(s1l,s2l);
5975 else emit_test(s1l,s1l);
5976 emit_cmov2imm_e_ne_compact(start+i*4+8,ba[i],addr);
5977 }
5978 else
5979 #endif
5980 {
5981 assert(s1l>=0);
5982 emit_mov2imm_compact(start+i*4+8,addr,ba[i],alt);
5983 if(s1h>=0) {
5984 if(s2h>=0) emit_cmp(s1h,s2h);
5985 else emit_test(s1h,s1h);
5986 emit_cmovne_reg(alt,addr);
5987 }
5988 if(s2l>=0) emit_cmp(s1l,s2l);
5989 else emit_test(s1l,s1l);
5990 emit_cmovne_reg(alt,addr);
5991 }
5992 }
5993 if((opcode[i]&0x3f)==0x14) // BEQL
5994 {
5995 if(s1h>=0) {
5996 if(s2h>=0) emit_cmp(s1h,s2h);
5997 else emit_test(s1h,s1h);
5998 nottaken=(int)out;
5999 emit_jne(0);
6000 }
6001 if(s2l>=0) emit_cmp(s1l,s2l);
6002 else emit_test(s1l,s1l);
6003 if(nottaken) set_jump_target(nottaken,(int)out);
6004 nottaken=(int)out;
6005 emit_jne(0);
6006 }
6007 if((opcode[i]&0x3f)==0x15) // BNEL
6008 {
6009 if(s1h>=0) {
6010 if(s2h>=0) emit_cmp(s1h,s2h);
6011 else emit_test(s1h,s1h);
6012 taken=(int)out;
6013 emit_jne(0);
6014 }
6015 if(s2l>=0) emit_cmp(s1l,s2l);
6016 else emit_test(s1l,s1l);
6017 nottaken=(int)out;
6018 emit_jeq(0);
6019 if(taken) set_jump_target(taken,(int)out);
6020 }
6021 if((opcode[i]&0x3f)==6) // BLEZ
6022 {
6023 emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
6024 emit_cmpimm(s1l,1);
6025 if(s1h>=0) emit_mov(addr,ntaddr);
6026 emit_cmovl_reg(alt,addr);
6027 if(s1h>=0) {
6028 emit_test(s1h,s1h);
6029 emit_cmovne_reg(ntaddr,addr);
6030 emit_cmovs_reg(alt,addr);
6031 }
6032 }
6033 if((opcode[i]&0x3f)==7) // BGTZ
6034 {
6035 emit_mov2imm_compact(ba[i],addr,start+i*4+8,ntaddr);
6036 emit_cmpimm(s1l,1);
6037 if(s1h>=0) emit_mov(addr,alt);
6038 emit_cmovl_reg(ntaddr,addr);
6039 if(s1h>=0) {
6040 emit_test(s1h,s1h);
6041 emit_cmovne_reg(alt,addr);
6042 emit_cmovs_reg(ntaddr,addr);
6043 }
6044 }
6045 if((opcode[i]&0x3f)==0x16) // BLEZL
6046 {
6047 assert((opcode[i]&0x3f)!=0x16);
6048 }
6049 if((opcode[i]&0x3f)==0x17) // BGTZL
6050 {
6051 assert((opcode[i]&0x3f)!=0x17);
6052 }
6053 assert(opcode[i]!=1); // BLTZ/BGEZ
6054
6055 //FIXME: Check CSREG
6056 if(opcode[i]==0x11 && opcode2[i]==0x08 ) {
6057 if((source[i]&0x30000)==0) // BC1F
6058 {
6059 emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
6060 emit_testimm(s1l,0x800000);
6061 emit_cmovne_reg(alt,addr);
6062 }
6063 if((source[i]&0x30000)==0x10000) // BC1T
6064 {
6065 emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
6066 emit_testimm(s1l,0x800000);
6067 emit_cmovne_reg(alt,addr);
6068 }
6069 if((source[i]&0x30000)==0x20000) // BC1FL
6070 {
6071 emit_testimm(s1l,0x800000);
6072 nottaken=(int)out;
6073 emit_jne(0);
6074 }
6075 if((source[i]&0x30000)==0x30000) // BC1TL
6076 {
6077 emit_testimm(s1l,0x800000);
6078 nottaken=(int)out;
6079 emit_jeq(0);
6080 }
6081 }
6082
6083 assert(i_regs->regmap[HOST_CCREG]==CCREG);
6084 wb_dirtys(regs[i].regmap,regs[i].is32,regs[i].dirty);
6085 if(likely[i]||unconditional)
6086 {
6087 emit_movimm(ba[i],HOST_BTREG);
6088 }
6089 else if(addr!=HOST_BTREG)
6090 {
6091 emit_mov(addr,HOST_BTREG);
6092 }
6093 void *branch_addr=out;
6094 emit_jmp(0);
6095 int target_addr=start+i*4+5;
6096 void *stub=out;
6097 void *compiled_target_addr=check_addr(target_addr);
6098 emit_extjump_ds((int)branch_addr,target_addr);
6099 if(compiled_target_addr) {
6100 set_jump_target((int)branch_addr,(int)compiled_target_addr);
6101 add_link(target_addr,stub);
6102 }
6103 else set_jump_target((int)branch_addr,(int)stub);
6104 if(likely[i]) {
6105 // Not-taken path
6106 set_jump_target((int)nottaken,(int)out);
6107 wb_dirtys(regs[i].regmap,regs[i].is32,regs[i].dirty);
6108 void *branch_addr=out;
6109 emit_jmp(0);
6110 int target_addr=start+i*4+8;
6111 void *stub=out;
6112 void *compiled_target_addr=check_addr(target_addr);
6113 emit_extjump_ds((int)branch_addr,target_addr);
6114 if(compiled_target_addr) {
6115 set_jump_target((int)branch_addr,(int)compiled_target_addr);
6116 add_link(target_addr,stub);
6117 }
6118 else set_jump_target((int)branch_addr,(int)stub);
6119 }
6120}
6121
6122// Assemble the delay slot for the above
6123static void pagespan_ds()
6124{
6125 assem_debug("initial delay slot:\n");
6126 u_int vaddr=start+1;
94d23bb9 6127 u_int page=get_page(vaddr);
6128 u_int vpage=get_vpage(vaddr);
57871462 6129 ll_add(jump_dirty+vpage,vaddr,(void *)out);
6130 do_dirty_stub_ds();
6131 ll_add(jump_in+page,vaddr,(void *)out);
6132 assert(regs[0].regmap_entry[HOST_CCREG]==CCREG);
6133 if(regs[0].regmap[HOST_CCREG]!=CCREG)
6134 wb_register(CCREG,regs[0].regmap_entry,regs[0].wasdirty,regs[0].was32);
6135 if(regs[0].regmap[HOST_BTREG]!=BTREG)
6136 emit_writeword(HOST_BTREG,(int)&branch_target);
6137 load_regs(regs[0].regmap_entry,regs[0].regmap,regs[0].was32,rs1[0],rs2[0]);
6138 address_generation(0,&regs[0],regs[0].regmap_entry);
b9b61529 6139 if(itype[0]==STORE||itype[0]==STORELR||(opcode[0]&0x3b)==0x39||(opcode[0]&0x3b)==0x3a)
57871462 6140 load_regs(regs[0].regmap_entry,regs[0].regmap,regs[0].was32,INVCP,INVCP);
6141 cop1_usable=0;
6142 is_delayslot=0;
6143 switch(itype[0]) {
6144 case ALU:
6145 alu_assemble(0,&regs[0]);break;
6146 case IMM16:
6147 imm16_assemble(0,&regs[0]);break;
6148 case SHIFT:
6149 shift_assemble(0,&regs[0]);break;
6150 case SHIFTIMM:
6151 shiftimm_assemble(0,&regs[0]);break;
6152 case LOAD:
6153 load_assemble(0,&regs[0]);break;
6154 case LOADLR:
6155 loadlr_assemble(0,&regs[0]);break;
6156 case STORE:
6157 store_assemble(0,&regs[0]);break;
6158 case STORELR:
6159 storelr_assemble(0,&regs[0]);break;
6160 case COP0:
6161 cop0_assemble(0,&regs[0]);break;
6162 case COP1:
6163 cop1_assemble(0,&regs[0]);break;
6164 case C1LS:
6165 c1ls_assemble(0,&regs[0]);break;
b9b61529 6166 case COP2:
6167 cop2_assemble(0,&regs[0]);break;
6168 case C2LS:
6169 c2ls_assemble(0,&regs[0]);break;
6170 case C2OP:
6171 c2op_assemble(0,&regs[0]);break;
57871462 6172 case FCONV:
6173 fconv_assemble(0,&regs[0]);break;
6174 case FLOAT:
6175 float_assemble(0,&regs[0]);break;
6176 case FCOMP:
6177 fcomp_assemble(0,&regs[0]);break;
6178 case MULTDIV:
6179 multdiv_assemble(0,&regs[0]);break;
6180 case MOV:
6181 mov_assemble(0,&regs[0]);break;
6182 case SYSCALL:
7139f3c8 6183 case HLECALL:
1e973cb0 6184 case INTCALL:
57871462 6185 case SPAN:
6186 case UJUMP:
6187 case RJUMP:
6188 case CJUMP:
6189 case SJUMP:
6190 case FJUMP:
c43b5311 6191 SysPrintf("Jump in the delay slot. This is probably a bug.\n");
57871462 6192 }
6193 int btaddr=get_reg(regs[0].regmap,BTREG);
6194 if(btaddr<0) {
6195 btaddr=get_reg(regs[0].regmap,-1);
6196 emit_readword((int)&branch_target,btaddr);
6197 }
6198 assert(btaddr!=HOST_CCREG);
6199 if(regs[0].regmap[HOST_CCREG]!=CCREG) emit_loadreg(CCREG,HOST_CCREG);
6200#ifdef HOST_IMM8
6201 emit_movimm(start+4,HOST_TEMPREG);
6202 emit_cmp(btaddr,HOST_TEMPREG);
6203#else
6204 emit_cmpimm(btaddr,start+4);
6205#endif
6206 int branch=(int)out;
6207 emit_jeq(0);
6208 store_regs_bt(regs[0].regmap,regs[0].is32,regs[0].dirty,-1);
6209 emit_jmp(jump_vaddr_reg[btaddr]);
6210 set_jump_target(branch,(int)out);
6211 store_regs_bt(regs[0].regmap,regs[0].is32,regs[0].dirty,start+4);
6212 load_regs_bt(regs[0].regmap,regs[0].is32,regs[0].dirty,start+4);
6213}
6214
6215// Basic liveness analysis for MIPS registers
6216void unneeded_registers(int istart,int iend,int r)
6217{
6218 int i;
bedfea38 6219 uint64_t u,uu,gte_u,b,bu,gte_bu;
0ff8c62c 6220 uint64_t temp_u,temp_uu,temp_gte_u=0;
57871462 6221 uint64_t tdep;
0ff8c62c 6222 uint64_t gte_u_unknown=0;
6223 if(new_dynarec_hacks&NDHACK_GTE_UNNEEDED)
6224 gte_u_unknown=~0ll;
57871462 6225 if(iend==slen-1) {
6226 u=1;uu=1;
0ff8c62c 6227 gte_u=gte_u_unknown;
57871462 6228 }else{
6229 u=unneeded_reg[iend+1];
6230 uu=unneeded_reg_upper[iend+1];
6231 u=1;uu=1;
0ff8c62c 6232 gte_u=gte_unneeded[iend+1];
57871462 6233 }
bedfea38 6234
57871462 6235 for (i=iend;i>=istart;i--)
6236 {
6237 //printf("unneeded registers i=%d (%d,%d) r=%d\n",i,istart,iend,r);
6238 if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
6239 {
6240 // If subroutine call, flag return address as a possible branch target
6241 if(rt1[i]==31 && i<slen-2) bt[i+2]=1;
6242
6243 if(ba[i]<start || ba[i]>=(start+slen*4))
6244 {
6245 // Branch out of this block, flush all regs
6246 u=1;
6247 uu=1;
0ff8c62c 6248 gte_u=gte_u_unknown;
57871462 6249 /* Hexagon hack
6250 if(itype[i]==UJUMP&&rt1[i]==31)
6251 {
6252 uu=u=0x300C00F; // Discard at, v0-v1, t6-t9
6253 }
6254 if(itype[i]==RJUMP&&rs1[i]==31)
6255 {
6256 uu=u=0x300C0F3; // Discard at, a0-a3, t6-t9
6257 }
4cb76aa4 6258 if(start>0x80000400&&start<0x80000000+RAM_SIZE) {
57871462 6259 if(itype[i]==UJUMP&&rt1[i]==31)
6260 {
6261 //uu=u=0x30300FF0FLL; // Discard at, v0-v1, t0-t9, lo, hi
6262 uu=u=0x300FF0F; // Discard at, v0-v1, t0-t9
6263 }
6264 if(itype[i]==RJUMP&&rs1[i]==31)
6265 {
6266 //uu=u=0x30300FFF3LL; // Discard at, a0-a3, t0-t9, lo, hi
6267 uu=u=0x300FFF3; // Discard at, a0-a3, t0-t9
6268 }
6269 }*/
6270 branch_unneeded_reg[i]=u;
6271 branch_unneeded_reg_upper[i]=uu;
6272 // Merge in delay slot
6273 tdep=(~uu>>rt1[i+1])&1;
6274 u|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6275 uu|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6276 u&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
6277 uu&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
6278 uu&=~((tdep<<dep1[i+1])|(tdep<<dep2[i+1]));
6279 u|=1;uu|=1;
bedfea38 6280 gte_u|=gte_rt[i+1];
6281 gte_u&=~gte_rs[i+1];
57871462 6282 // If branch is "likely" (and conditional)
6283 // then we skip the delay slot on the fall-thru path
6284 if(likely[i]) {
6285 if(i<slen-1) {
6286 u&=unneeded_reg[i+2];
6287 uu&=unneeded_reg_upper[i+2];
bedfea38 6288 gte_u&=gte_unneeded[i+2];
57871462 6289 }
6290 else
6291 {
6292 u=1;
6293 uu=1;
0ff8c62c 6294 gte_u=gte_u_unknown;
57871462 6295 }
6296 }
6297 }
6298 else
6299 {
6300 // Internal branch, flag target
6301 bt[(ba[i]-start)>>2]=1;
6302 if(ba[i]<=start+i*4) {
6303 // Backward branch
6304 if(itype[i]==RJUMP||itype[i]==UJUMP||(source[i]>>16)==0x1000)
6305 {
6306 // Unconditional branch
6307 temp_u=1;temp_uu=1;
bedfea38 6308 temp_gte_u=0;
57871462 6309 } else {
6310 // Conditional branch (not taken case)
6311 temp_u=unneeded_reg[i+2];
6312 temp_uu=unneeded_reg_upper[i+2];
bedfea38 6313 temp_gte_u&=gte_unneeded[i+2];
57871462 6314 }
6315 // Merge in delay slot
6316 tdep=(~temp_uu>>rt1[i+1])&1;
6317 temp_u|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6318 temp_uu|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6319 temp_u&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
6320 temp_uu&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
6321 temp_uu&=~((tdep<<dep1[i+1])|(tdep<<dep2[i+1]));
6322 temp_u|=1;temp_uu|=1;
bedfea38 6323 temp_gte_u|=gte_rt[i+1];
6324 temp_gte_u&=~gte_rs[i+1];
57871462 6325 // If branch is "likely" (and conditional)
6326 // then we skip the delay slot on the fall-thru path
6327 if(likely[i]) {
6328 if(i<slen-1) {
6329 temp_u&=unneeded_reg[i+2];
6330 temp_uu&=unneeded_reg_upper[i+2];
bedfea38 6331 temp_gte_u&=gte_unneeded[i+2];
57871462 6332 }
6333 else
6334 {
6335 temp_u=1;
6336 temp_uu=1;
0ff8c62c 6337 temp_gte_u=gte_u_unknown;
57871462 6338 }
6339 }
6340 tdep=(~temp_uu>>rt1[i])&1;
6341 temp_u|=(1LL<<rt1[i])|(1LL<<rt2[i]);
6342 temp_uu|=(1LL<<rt1[i])|(1LL<<rt2[i]);
6343 temp_u&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
6344 temp_uu&=~((1LL<<us1[i])|(1LL<<us2[i]));
6345 temp_uu&=~((tdep<<dep1[i])|(tdep<<dep2[i]));
6346 temp_u|=1;temp_uu|=1;
bedfea38 6347 temp_gte_u|=gte_rt[i];
6348 temp_gte_u&=~gte_rs[i];
57871462 6349 unneeded_reg[i]=temp_u;
6350 unneeded_reg_upper[i]=temp_uu;
bedfea38 6351 gte_unneeded[i]=temp_gte_u;
57871462 6352 // Only go three levels deep. This recursion can take an
6353 // excessive amount of time if there are a lot of nested loops.
6354 if(r<2) {
6355 unneeded_registers((ba[i]-start)>>2,i-1,r+1);
6356 }else{
6357 unneeded_reg[(ba[i]-start)>>2]=1;
6358 unneeded_reg_upper[(ba[i]-start)>>2]=1;
0ff8c62c 6359 gte_unneeded[(ba[i]-start)>>2]=gte_u_unknown;
57871462 6360 }
6361 } /*else*/ if(1) {
6362 if(itype[i]==RJUMP||itype[i]==UJUMP||(source[i]>>16)==0x1000)
6363 {
6364 // Unconditional branch
6365 u=unneeded_reg[(ba[i]-start)>>2];
6366 uu=unneeded_reg_upper[(ba[i]-start)>>2];
bedfea38 6367 gte_u=gte_unneeded[(ba[i]-start)>>2];
57871462 6368 branch_unneeded_reg[i]=u;
6369 branch_unneeded_reg_upper[i]=uu;
6370 //u=1;
6371 //uu=1;
6372 //branch_unneeded_reg[i]=u;
6373 //branch_unneeded_reg_upper[i]=uu;
6374 // Merge in delay slot
6375 tdep=(~uu>>rt1[i+1])&1;
6376 u|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6377 uu|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6378 u&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
6379 uu&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
6380 uu&=~((tdep<<dep1[i+1])|(tdep<<dep2[i+1]));
6381 u|=1;uu|=1;
bedfea38 6382 gte_u|=gte_rt[i+1];
6383 gte_u&=~gte_rs[i+1];
57871462 6384 } else {
6385 // Conditional branch
6386 b=unneeded_reg[(ba[i]-start)>>2];
6387 bu=unneeded_reg_upper[(ba[i]-start)>>2];
bedfea38 6388 gte_bu=gte_unneeded[(ba[i]-start)>>2];
57871462 6389 branch_unneeded_reg[i]=b;
6390 branch_unneeded_reg_upper[i]=bu;
6391 //b=1;
6392 //bu=1;
6393 //branch_unneeded_reg[i]=b;
6394 //branch_unneeded_reg_upper[i]=bu;
6395 // Branch delay slot
6396 tdep=(~uu>>rt1[i+1])&1;
6397 b|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6398 bu|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6399 b&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
6400 bu&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
6401 bu&=~((tdep<<dep1[i+1])|(tdep<<dep2[i+1]));
6402 b|=1;bu|=1;
bedfea38 6403 gte_bu|=gte_rt[i+1];
6404 gte_bu&=~gte_rs[i+1];
57871462 6405 // If branch is "likely" then we skip the
6406 // delay slot on the fall-thru path
6407 if(likely[i]) {
6408 u=b;
6409 uu=bu;
bedfea38 6410 gte_u=gte_bu;
57871462 6411 if(i<slen-1) {
6412 u&=unneeded_reg[i+2];
6413 uu&=unneeded_reg_upper[i+2];
bedfea38 6414 gte_u&=gte_unneeded[i+2];
57871462 6415 //u=1;
6416 //uu=1;
6417 }
6418 } else {
6419 u&=b;
6420 uu&=bu;
bedfea38 6421 gte_u&=gte_bu;
57871462 6422 //u=1;
6423 //uu=1;
6424 }
6425 if(i<slen-1) {
6426 branch_unneeded_reg[i]&=unneeded_reg[i+2];
6427 branch_unneeded_reg_upper[i]&=unneeded_reg_upper[i+2];
6428 //branch_unneeded_reg[i]=1;
6429 //branch_unneeded_reg_upper[i]=1;
6430 } else {
6431 branch_unneeded_reg[i]=1;
6432 branch_unneeded_reg_upper[i]=1;
6433 }
6434 }
6435 }
6436 }
6437 }
1e973cb0 6438 else if(itype[i]==SYSCALL||itype[i]==HLECALL||itype[i]==INTCALL)
57871462 6439 {
6440 // SYSCALL instruction (software interrupt)
6441 u=1;
6442 uu=1;
6443 }
6444 else if(itype[i]==COP0 && (source[i]&0x3f)==0x18)
6445 {
6446 // ERET instruction (return from interrupt)
6447 u=1;
6448 uu=1;
6449 }
6450 //u=uu=1; // DEBUG
6451 tdep=(~uu>>rt1[i])&1;
6452 // Written registers are unneeded
6453 u|=1LL<<rt1[i];
6454 u|=1LL<<rt2[i];
6455 uu|=1LL<<rt1[i];
6456 uu|=1LL<<rt2[i];
bedfea38 6457 gte_u|=gte_rt[i];
57871462 6458 // Accessed registers are needed
6459 u&=~(1LL<<rs1[i]);
6460 u&=~(1LL<<rs2[i]);
6461 uu&=~(1LL<<us1[i]);
6462 uu&=~(1LL<<us2[i]);
bedfea38 6463 gte_u&=~gte_rs[i];
eaa11918 6464 if(gte_rs[i]&&rt1[i]&&(unneeded_reg[i+1]&(1ll<<rt1[i])))
cbbd8dd7 6465 gte_u|=gte_rs[i]&gte_unneeded[i+1]; // MFC2/CFC2 to dead register, unneeded
57871462 6466 // Source-target dependencies
6467 uu&=~(tdep<<dep1[i]);
6468 uu&=~(tdep<<dep2[i]);
6469 // R0 is always unneeded
6470 u|=1;uu|=1;
6471 // Save it
6472 unneeded_reg[i]=u;
6473 unneeded_reg_upper[i]=uu;
bedfea38 6474 gte_unneeded[i]=gte_u;
57871462 6475 /*
6476 printf("ur (%d,%d) %x: ",istart,iend,start+i*4);
6477 printf("U:");
6478 int r;
6479 for(r=1;r<=CCREG;r++) {
6480 if((unneeded_reg[i]>>r)&1) {
6481 if(r==HIREG) printf(" HI");
6482 else if(r==LOREG) printf(" LO");
6483 else printf(" r%d",r);
6484 }
6485 }
6486 printf(" UU:");
6487 for(r=1;r<=CCREG;r++) {
6488 if(((unneeded_reg_upper[i]&~unneeded_reg[i])>>r)&1) {
6489 if(r==HIREG) printf(" HI");
6490 else if(r==LOREG) printf(" LO");
6491 else printf(" r%d",r);
6492 }
6493 }
6494 printf("\n");*/
6495 }
252c20fc 6496 for (i=iend;i>=istart;i--)
6497 {
6498 unneeded_reg_upper[i]=branch_unneeded_reg_upper[i]=-1LL;
6499 }
57871462 6500}
6501
71e490c5 6502// Write back dirty registers as soon as we will no longer modify them,
6503// so that we don't end up with lots of writes at the branches.
6504void clean_registers(int istart,int iend,int wr)
57871462 6505{
71e490c5 6506 int i;
6507 int r;
6508 u_int will_dirty_i,will_dirty_next,temp_will_dirty;
6509 u_int wont_dirty_i,wont_dirty_next,temp_wont_dirty;
6510 if(iend==slen-1) {
6511 will_dirty_i=will_dirty_next=0;
6512 wont_dirty_i=wont_dirty_next=0;
6513 }else{
6514 will_dirty_i=will_dirty_next=will_dirty[iend+1];
6515 wont_dirty_i=wont_dirty_next=wont_dirty[iend+1];
6516 }
6517 for (i=iend;i>=istart;i--)
57871462 6518 {
71e490c5 6519 if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
57871462 6520 {
71e490c5 6521 if(ba[i]<start || ba[i]>=(start+slen*4))
57871462 6522 {
71e490c5 6523 // Branch out of this block, flush all regs
6524 if(itype[i]==RJUMP||itype[i]==UJUMP||(source[i]>>16)==0x1000)
57871462 6525 {
6526 // Unconditional branch
6527 will_dirty_i=0;
6528 wont_dirty_i=0;
6529 // Merge in delay slot (will dirty)
6530 for(r=0;r<HOST_REGS;r++) {
6531 if(r!=EXCLUDE_REG) {
6532 if((branch_regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
6533 if((branch_regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
6534 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
6535 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
6536 if((branch_regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
6537 if(branch_regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
6538 if(branch_regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
6539 if((regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
6540 if((regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
6541 if((regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
6542 if((regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
6543 if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
6544 if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
6545 if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
6546 }
6547 }
6548 }
6549 else
6550 {
6551 // Conditional branch
6552 will_dirty_i=0;
6553 wont_dirty_i=wont_dirty_next;
6554 // Merge in delay slot (will dirty)
6555 for(r=0;r<HOST_REGS;r++) {
6556 if(r!=EXCLUDE_REG) {
6557 if(!likely[i]) {
6558 // Might not dirty if likely branch is not taken
6559 if((branch_regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
6560 if((branch_regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
6561 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
6562 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
6563 if((branch_regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
6564 if(branch_regs[i].regmap[r]==0) will_dirty_i&=~(1<<r);
6565 if(branch_regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
6566 //if((regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
6567 //if((regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
6568 if((regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
6569 if((regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
6570 if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
6571 if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
6572 if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
6573 }
6574 }
6575 }
6576 }
6577 // Merge in delay slot (wont dirty)
6578 for(r=0;r<HOST_REGS;r++) {
6579 if(r!=EXCLUDE_REG) {
6580 if((regs[i].regmap[r]&63)==rt1[i]) wont_dirty_i|=1<<r;
6581 if((regs[i].regmap[r]&63)==rt2[i]) wont_dirty_i|=1<<r;
6582 if((regs[i].regmap[r]&63)==rt1[i+1]) wont_dirty_i|=1<<r;
6583 if((regs[i].regmap[r]&63)==rt2[i+1]) wont_dirty_i|=1<<r;
6584 if(regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
6585 if((branch_regs[i].regmap[r]&63)==rt1[i]) wont_dirty_i|=1<<r;
6586 if((branch_regs[i].regmap[r]&63)==rt2[i]) wont_dirty_i|=1<<r;
6587 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) wont_dirty_i|=1<<r;
6588 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) wont_dirty_i|=1<<r;
6589 if(branch_regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
6590 }
6591 }
6592 if(wr) {
6593 #ifndef DESTRUCTIVE_WRITEBACK
6594 branch_regs[i].dirty&=wont_dirty_i;
6595 #endif
6596 branch_regs[i].dirty|=will_dirty_i;
6597 }
6598 }
6599 else
6600 {
6601 // Internal branch
6602 if(ba[i]<=start+i*4) {
6603 // Backward branch
6604 if(itype[i]==RJUMP||itype[i]==UJUMP||(source[i]>>16)==0x1000)
6605 {
6606 // Unconditional branch
6607 temp_will_dirty=0;
6608 temp_wont_dirty=0;
6609 // Merge in delay slot (will dirty)
6610 for(r=0;r<HOST_REGS;r++) {
6611 if(r!=EXCLUDE_REG) {
6612 if((branch_regs[i].regmap[r]&63)==rt1[i]) temp_will_dirty|=1<<r;
6613 if((branch_regs[i].regmap[r]&63)==rt2[i]) temp_will_dirty|=1<<r;
6614 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) temp_will_dirty|=1<<r;
6615 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) temp_will_dirty|=1<<r;
6616 if((branch_regs[i].regmap[r]&63)>33) temp_will_dirty&=~(1<<r);
6617 if(branch_regs[i].regmap[r]<=0) temp_will_dirty&=~(1<<r);
6618 if(branch_regs[i].regmap[r]==CCREG) temp_will_dirty|=1<<r;
6619 if((regs[i].regmap[r]&63)==rt1[i]) temp_will_dirty|=1<<r;
6620 if((regs[i].regmap[r]&63)==rt2[i]) temp_will_dirty|=1<<r;
6621 if((regs[i].regmap[r]&63)==rt1[i+1]) temp_will_dirty|=1<<r;
6622 if((regs[i].regmap[r]&63)==rt2[i+1]) temp_will_dirty|=1<<r;
6623 if((regs[i].regmap[r]&63)>33) temp_will_dirty&=~(1<<r);
6624 if(regs[i].regmap[r]<=0) temp_will_dirty&=~(1<<r);
6625 if(regs[i].regmap[r]==CCREG) temp_will_dirty|=1<<r;
6626 }
6627 }
6628 } else {
6629 // Conditional branch (not taken case)
6630 temp_will_dirty=will_dirty_next;
6631 temp_wont_dirty=wont_dirty_next;
6632 // Merge in delay slot (will dirty)
6633 for(r=0;r<HOST_REGS;r++) {
6634 if(r!=EXCLUDE_REG) {
6635 if(!likely[i]) {
6636 // Will not dirty if likely branch is not taken
6637 if((branch_regs[i].regmap[r]&63)==rt1[i]) temp_will_dirty|=1<<r;
6638 if((branch_regs[i].regmap[r]&63)==rt2[i]) temp_will_dirty|=1<<r;
6639 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) temp_will_dirty|=1<<r;
6640 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) temp_will_dirty|=1<<r;
6641 if((branch_regs[i].regmap[r]&63)>33) temp_will_dirty&=~(1<<r);
6642 if(branch_regs[i].regmap[r]==0) temp_will_dirty&=~(1<<r);
6643 if(branch_regs[i].regmap[r]==CCREG) temp_will_dirty|=1<<r;
6644 //if((regs[i].regmap[r]&63)==rt1[i]) temp_will_dirty|=1<<r;
6645 //if((regs[i].regmap[r]&63)==rt2[i]) temp_will_dirty|=1<<r;
6646 if((regs[i].regmap[r]&63)==rt1[i+1]) temp_will_dirty|=1<<r;
6647 if((regs[i].regmap[r]&63)==rt2[i+1]) temp_will_dirty|=1<<r;
6648 if((regs[i].regmap[r]&63)>33) temp_will_dirty&=~(1<<r);
6649 if(regs[i].regmap[r]<=0) temp_will_dirty&=~(1<<r);
6650 if(regs[i].regmap[r]==CCREG) temp_will_dirty|=1<<r;
6651 }
6652 }
6653 }
6654 }
6655 // Merge in delay slot (wont dirty)
6656 for(r=0;r<HOST_REGS;r++) {
6657 if(r!=EXCLUDE_REG) {
6658 if((regs[i].regmap[r]&63)==rt1[i]) temp_wont_dirty|=1<<r;
6659 if((regs[i].regmap[r]&63)==rt2[i]) temp_wont_dirty|=1<<r;
6660 if((regs[i].regmap[r]&63)==rt1[i+1]) temp_wont_dirty|=1<<r;
6661 if((regs[i].regmap[r]&63)==rt2[i+1]) temp_wont_dirty|=1<<r;
6662 if(regs[i].regmap[r]==CCREG) temp_wont_dirty|=1<<r;
6663 if((branch_regs[i].regmap[r]&63)==rt1[i]) temp_wont_dirty|=1<<r;
6664 if((branch_regs[i].regmap[r]&63)==rt2[i]) temp_wont_dirty|=1<<r;
6665 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) temp_wont_dirty|=1<<r;
6666 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) temp_wont_dirty|=1<<r;
6667 if(branch_regs[i].regmap[r]==CCREG) temp_wont_dirty|=1<<r;
6668 }
6669 }
6670 // Deal with changed mappings
6671 if(i<iend) {
6672 for(r=0;r<HOST_REGS;r++) {
6673 if(r!=EXCLUDE_REG) {
6674 if(regs[i].regmap[r]!=regmap_pre[i][r]) {
6675 temp_will_dirty&=~(1<<r);
6676 temp_wont_dirty&=~(1<<r);
6677 if((regmap_pre[i][r]&63)>0 && (regmap_pre[i][r]&63)<34) {
6678 temp_will_dirty|=((unneeded_reg[i]>>(regmap_pre[i][r]&63))&1)<<r;
6679 temp_wont_dirty|=((unneeded_reg[i]>>(regmap_pre[i][r]&63))&1)<<r;
6680 } else {
6681 temp_will_dirty|=1<<r;
6682 temp_wont_dirty|=1<<r;
6683 }
6684 }
6685 }
6686 }
6687 }
6688 if(wr) {
6689 will_dirty[i]=temp_will_dirty;
6690 wont_dirty[i]=temp_wont_dirty;
6691 clean_registers((ba[i]-start)>>2,i-1,0);
6692 }else{
6693 // Limit recursion. It can take an excessive amount
6694 // of time if there are a lot of nested loops.
6695 will_dirty[(ba[i]-start)>>2]=0;
6696 wont_dirty[(ba[i]-start)>>2]=-1;
6697 }
6698 }
6699 /*else*/ if(1)
6700 {
6701 if(itype[i]==RJUMP||itype[i]==UJUMP||(source[i]>>16)==0x1000)
6702 {
6703 // Unconditional branch
6704 will_dirty_i=0;
6705 wont_dirty_i=0;
6706 //if(ba[i]>start+i*4) { // Disable recursion (for debugging)
6707 for(r=0;r<HOST_REGS;r++) {
6708 if(r!=EXCLUDE_REG) {
6709 if(branch_regs[i].regmap[r]==regs[(ba[i]-start)>>2].regmap_entry[r]) {
6710 will_dirty_i|=will_dirty[(ba[i]-start)>>2]&(1<<r);
6711 wont_dirty_i|=wont_dirty[(ba[i]-start)>>2]&(1<<r);
6712 }
e3234ecf 6713 if(branch_regs[i].regmap[r]>=0) {
6714 will_dirty_i|=((unneeded_reg[(ba[i]-start)>>2]>>(branch_regs[i].regmap[r]&63))&1)<<r;
6715 wont_dirty_i|=((unneeded_reg[(ba[i]-start)>>2]>>(branch_regs[i].regmap[r]&63))&1)<<r;
6716 }
57871462 6717 }
6718 }
6719 //}
6720 // Merge in delay slot
6721 for(r=0;r<HOST_REGS;r++) {
6722 if(r!=EXCLUDE_REG) {
6723 if((branch_regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
6724 if((branch_regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
6725 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
6726 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
6727 if((branch_regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
6728 if(branch_regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
6729 if(branch_regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
6730 if((regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
6731 if((regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
6732 if((regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
6733 if((regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
6734 if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
6735 if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
6736 if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
6737 }
6738 }
6739 } else {
6740 // Conditional branch
6741 will_dirty_i=will_dirty_next;
6742 wont_dirty_i=wont_dirty_next;
6743 //if(ba[i]>start+i*4) { // Disable recursion (for debugging)
6744 for(r=0;r<HOST_REGS;r++) {
6745 if(r!=EXCLUDE_REG) {
e3234ecf 6746 signed char target_reg=branch_regs[i].regmap[r];
6747 if(target_reg==regs[(ba[i]-start)>>2].regmap_entry[r]) {
57871462 6748 will_dirty_i&=will_dirty[(ba[i]-start)>>2]&(1<<r);
6749 wont_dirty_i|=wont_dirty[(ba[i]-start)>>2]&(1<<r);
6750 }
e3234ecf 6751 else if(target_reg>=0) {
6752 will_dirty_i&=((unneeded_reg[(ba[i]-start)>>2]>>(target_reg&63))&1)<<r;
6753 wont_dirty_i|=((unneeded_reg[(ba[i]-start)>>2]>>(target_reg&63))&1)<<r;
57871462 6754 }
6755 // Treat delay slot as part of branch too
6756 /*if(regs[i+1].regmap[r]==regs[(ba[i]-start)>>2].regmap_entry[r]) {
6757 will_dirty[i+1]&=will_dirty[(ba[i]-start)>>2]&(1<<r);
6758 wont_dirty[i+1]|=wont_dirty[(ba[i]-start)>>2]&(1<<r);
6759 }
6760 else
6761 {
6762 will_dirty[i+1]&=~(1<<r);
6763 }*/
6764 }
6765 }
6766 //}
6767 // Merge in delay slot
6768 for(r=0;r<HOST_REGS;r++) {
6769 if(r!=EXCLUDE_REG) {
6770 if(!likely[i]) {
6771 // Might not dirty if likely branch is not taken
6772 if((branch_regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
6773 if((branch_regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
6774 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
6775 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
6776 if((branch_regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
6777 if(branch_regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
6778 if(branch_regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
6779 //if((regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
6780 //if((regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
6781 if((regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
6782 if((regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
6783 if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
6784 if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
6785 if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
6786 }
6787 }
6788 }
6789 }
e3234ecf 6790 // Merge in delay slot (won't dirty)
57871462 6791 for(r=0;r<HOST_REGS;r++) {
6792 if(r!=EXCLUDE_REG) {
6793 if((regs[i].regmap[r]&63)==rt1[i]) wont_dirty_i|=1<<r;
6794 if((regs[i].regmap[r]&63)==rt2[i]) wont_dirty_i|=1<<r;
6795 if((regs[i].regmap[r]&63)==rt1[i+1]) wont_dirty_i|=1<<r;
6796 if((regs[i].regmap[r]&63)==rt2[i+1]) wont_dirty_i|=1<<r;
6797 if(regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
6798 if((branch_regs[i].regmap[r]&63)==rt1[i]) wont_dirty_i|=1<<r;
6799 if((branch_regs[i].regmap[r]&63)==rt2[i]) wont_dirty_i|=1<<r;
6800 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) wont_dirty_i|=1<<r;
6801 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) wont_dirty_i|=1<<r;
6802 if(branch_regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
6803 }
6804 }
6805 if(wr) {
6806 #ifndef DESTRUCTIVE_WRITEBACK
6807 branch_regs[i].dirty&=wont_dirty_i;
6808 #endif
6809 branch_regs[i].dirty|=will_dirty_i;
6810 }
6811 }
6812 }
6813 }
1e973cb0 6814 else if(itype[i]==SYSCALL||itype[i]==HLECALL||itype[i]==INTCALL)
57871462 6815 {
6816 // SYSCALL instruction (software interrupt)
6817 will_dirty_i=0;
6818 wont_dirty_i=0;
6819 }
6820 else if(itype[i]==COP0 && (source[i]&0x3f)==0x18)
6821 {
6822 // ERET instruction (return from interrupt)
6823 will_dirty_i=0;
6824 wont_dirty_i=0;
6825 }
6826 will_dirty_next=will_dirty_i;
6827 wont_dirty_next=wont_dirty_i;
6828 for(r=0;r<HOST_REGS;r++) {
6829 if(r!=EXCLUDE_REG) {
6830 if((regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
6831 if((regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
6832 if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
6833 if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
6834 if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
6835 if((regs[i].regmap[r]&63)==rt1[i]) wont_dirty_i|=1<<r;
6836 if((regs[i].regmap[r]&63)==rt2[i]) wont_dirty_i|=1<<r;
6837 if(regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
6838 if(i>istart) {
6839 if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&itype[i]!=CJUMP&&itype[i]!=SJUMP&&itype[i]!=FJUMP)
6840 {
6841 // Don't store a register immediately after writing it,
6842 // may prevent dual-issue.
6843 if((regs[i].regmap[r]&63)==rt1[i-1]) wont_dirty_i|=1<<r;
6844 if((regs[i].regmap[r]&63)==rt2[i-1]) wont_dirty_i|=1<<r;
6845 }
6846 }
6847 }
6848 }
6849 // Save it
6850 will_dirty[i]=will_dirty_i;
6851 wont_dirty[i]=wont_dirty_i;
6852 // Mark registers that won't be dirtied as not dirty
6853 if(wr) {
6854 /*printf("wr (%d,%d) %x will:",istart,iend,start+i*4);
6855 for(r=0;r<HOST_REGS;r++) {
6856 if((will_dirty_i>>r)&1) {
6857 printf(" r%d",r);
6858 }
6859 }
6860 printf("\n");*/
6861
6862 //if(i==istart||(itype[i-1]!=RJUMP&&itype[i-1]!=UJUMP&&itype[i-1]!=CJUMP&&itype[i-1]!=SJUMP&&itype[i-1]!=FJUMP)) {
6863 regs[i].dirty|=will_dirty_i;
6864 #ifndef DESTRUCTIVE_WRITEBACK
6865 regs[i].dirty&=wont_dirty_i;
6866 if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
6867 {
6868 if(i<iend-1&&itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000) {
6869 for(r=0;r<HOST_REGS;r++) {
6870 if(r!=EXCLUDE_REG) {
6871 if(regs[i].regmap[r]==regmap_pre[i+2][r]) {
6872 regs[i+2].wasdirty&=wont_dirty_i|~(1<<r);
6873 }else {/*printf("i: %x (%d) mismatch(+2): %d\n",start+i*4,i,r);/*assert(!((wont_dirty_i>>r)&1));*/}
6874 }
6875 }
6876 }
6877 }
6878 else
6879 {
6880 if(i<iend) {
6881 for(r=0;r<HOST_REGS;r++) {
6882 if(r!=EXCLUDE_REG) {
6883 if(regs[i].regmap[r]==regmap_pre[i+1][r]) {
6884 regs[i+1].wasdirty&=wont_dirty_i|~(1<<r);
6885 }else {/*printf("i: %x (%d) mismatch(+1): %d\n",start+i*4,i,r);/*assert(!((wont_dirty_i>>r)&1));*/}
6886 }
6887 }
6888 }
6889 }
6890 #endif
6891 //}
6892 }
6893 // Deal with changed mappings
6894 temp_will_dirty=will_dirty_i;
6895 temp_wont_dirty=wont_dirty_i;
6896 for(r=0;r<HOST_REGS;r++) {
6897 if(r!=EXCLUDE_REG) {
6898 int nr;
6899 if(regs[i].regmap[r]==regmap_pre[i][r]) {
6900 if(wr) {
6901 #ifndef DESTRUCTIVE_WRITEBACK
6902 regs[i].wasdirty&=wont_dirty_i|~(1<<r);
6903 #endif
6904 regs[i].wasdirty|=will_dirty_i&(1<<r);
6905 }
6906 }
f776eb14 6907 else if(regmap_pre[i][r]>=0&&(nr=get_reg(regs[i].regmap,regmap_pre[i][r]))>=0) {
57871462 6908 // Register moved to a different register
6909 will_dirty_i&=~(1<<r);
6910 wont_dirty_i&=~(1<<r);
6911 will_dirty_i|=((temp_will_dirty>>nr)&1)<<r;
6912 wont_dirty_i|=((temp_wont_dirty>>nr)&1)<<r;
6913 if(wr) {
6914 #ifndef DESTRUCTIVE_WRITEBACK
6915 regs[i].wasdirty&=wont_dirty_i|~(1<<r);
6916 #endif
6917 regs[i].wasdirty|=will_dirty_i&(1<<r);
6918 }
6919 }
6920 else {
6921 will_dirty_i&=~(1<<r);
6922 wont_dirty_i&=~(1<<r);
6923 if((regmap_pre[i][r]&63)>0 && (regmap_pre[i][r]&63)<34) {
6924 will_dirty_i|=((unneeded_reg[i]>>(regmap_pre[i][r]&63))&1)<<r;
6925 wont_dirty_i|=((unneeded_reg[i]>>(regmap_pre[i][r]&63))&1)<<r;
6926 } else {
6927 wont_dirty_i|=1<<r;
6928 /*printf("i: %x (%d) mismatch: %d\n",start+i*4,i,r);/*assert(!((will_dirty>>r)&1));*/
6929 }
6930 }
6931 }
6932 }
6933 }
6934}
6935
4600ba03 6936#ifdef DISASM
57871462 6937 /* disassembly */
6938void disassemble_inst(int i)
6939{
6940 if (bt[i]) printf("*"); else printf(" ");
6941 switch(itype[i]) {
6942 case UJUMP:
6943 printf (" %x: %s %8x\n",start+i*4,insn[i],ba[i]);break;
6944 case CJUMP:
6945 printf (" %x: %s r%d,r%d,%8x\n",start+i*4,insn[i],rs1[i],rs2[i],i?start+i*4+4+((signed int)((unsigned int)source[i]<<16)>>14):*ba);break;
6946 case SJUMP:
6947 printf (" %x: %s r%d,%8x\n",start+i*4,insn[i],rs1[i],start+i*4+4+((signed int)((unsigned int)source[i]<<16)>>14));break;
6948 case FJUMP:
6949 printf (" %x: %s %8x\n",start+i*4,insn[i],ba[i]);break;
6950 case RJUMP:
74426039 6951 if (opcode[i]==0x9&&rt1[i]!=31)
5067f341 6952 printf (" %x: %s r%d,r%d\n",start+i*4,insn[i],rt1[i],rs1[i]);
6953 else
6954 printf (" %x: %s r%d\n",start+i*4,insn[i],rs1[i]);
6955 break;
57871462 6956 case SPAN:
6957 printf (" %x: %s (pagespan) r%d,r%d,%8x\n",start+i*4,insn[i],rs1[i],rs2[i],ba[i]);break;
6958 case IMM16:
6959 if(opcode[i]==0xf) //LUI
6960 printf (" %x: %s r%d,%4x0000\n",start+i*4,insn[i],rt1[i],imm[i]&0xffff);
6961 else
6962 printf (" %x: %s r%d,r%d,%d\n",start+i*4,insn[i],rt1[i],rs1[i],imm[i]);
6963 break;
6964 case LOAD:
6965 case LOADLR:
6966 printf (" %x: %s r%d,r%d+%x\n",start+i*4,insn[i],rt1[i],rs1[i],imm[i]);
6967 break;
6968 case STORE:
6969 case STORELR:
6970 printf (" %x: %s r%d,r%d+%x\n",start+i*4,insn[i],rs2[i],rs1[i],imm[i]);
6971 break;
6972 case ALU:
6973 case SHIFT:
6974 printf (" %x: %s r%d,r%d,r%d\n",start+i*4,insn[i],rt1[i],rs1[i],rs2[i]);
6975 break;
6976 case MULTDIV:
6977 printf (" %x: %s r%d,r%d\n",start+i*4,insn[i],rs1[i],rs2[i]);
6978 break;
6979 case SHIFTIMM:
6980 printf (" %x: %s r%d,r%d,%d\n",start+i*4,insn[i],rt1[i],rs1[i],imm[i]);
6981 break;
6982 case MOV:
6983 if((opcode2[i]&0x1d)==0x10)
6984 printf (" %x: %s r%d\n",start+i*4,insn[i],rt1[i]);
6985 else if((opcode2[i]&0x1d)==0x11)
6986 printf (" %x: %s r%d\n",start+i*4,insn[i],rs1[i]);
6987 else
6988 printf (" %x: %s\n",start+i*4,insn[i]);
6989 break;
6990 case COP0:
6991 if(opcode2[i]==0)
6992 printf (" %x: %s r%d,cpr0[%d]\n",start+i*4,insn[i],rt1[i],(source[i]>>11)&0x1f); // MFC0
6993 else if(opcode2[i]==4)
6994 printf (" %x: %s r%d,cpr0[%d]\n",start+i*4,insn[i],rs1[i],(source[i]>>11)&0x1f); // MTC0
6995 else printf (" %x: %s\n",start+i*4,insn[i]);
6996 break;
6997 case COP1:
6998 if(opcode2[i]<3)
6999 printf (" %x: %s r%d,cpr1[%d]\n",start+i*4,insn[i],rt1[i],(source[i]>>11)&0x1f); // MFC1
7000 else if(opcode2[i]>3)
7001 printf (" %x: %s r%d,cpr1[%d]\n",start+i*4,insn[i],rs1[i],(source[i]>>11)&0x1f); // MTC1
7002 else printf (" %x: %s\n",start+i*4,insn[i]);
7003 break;
b9b61529 7004 case COP2:
7005 if(opcode2[i]<3)
7006 printf (" %x: %s r%d,cpr2[%d]\n",start+i*4,insn[i],rt1[i],(source[i]>>11)&0x1f); // MFC2
7007 else if(opcode2[i]>3)
7008 printf (" %x: %s r%d,cpr2[%d]\n",start+i*4,insn[i],rs1[i],(source[i]>>11)&0x1f); // MTC2
7009 else printf (" %x: %s\n",start+i*4,insn[i]);
7010 break;
57871462 7011 case C1LS:
7012 printf (" %x: %s cpr1[%d],r%d+%x\n",start+i*4,insn[i],(source[i]>>16)&0x1f,rs1[i],imm[i]);
7013 break;
b9b61529 7014 case C2LS:
7015 printf (" %x: %s cpr2[%d],r%d+%x\n",start+i*4,insn[i],(source[i]>>16)&0x1f,rs1[i],imm[i]);
7016 break;
1e973cb0 7017 case INTCALL:
7018 printf (" %x: %s (INTCALL)\n",start+i*4,insn[i]);
7019 break;
57871462 7020 default:
7021 //printf (" %s %8x\n",insn[i],source[i]);
7022 printf (" %x: %s\n",start+i*4,insn[i]);
7023 }
7024}
4600ba03 7025#else
7026static void disassemble_inst(int i) {}
7027#endif // DISASM
57871462 7028
d848b60a 7029#define DRC_TEST_VAL 0x74657374
7030
7031static int new_dynarec_test(void)
7032{
7033 int (*testfunc)(void) = (void *)out;
7034 int ret;
7035 emit_movimm(DRC_TEST_VAL,0); // test
7036 emit_jmpreg(14);
7037 literal_pool(0);
7038#ifdef __arm__
7039 __clear_cache((void *)testfunc, out);
7040#endif
7041 SysPrintf("testing if we can run recompiled code..\n");
7042 ret = testfunc();
7043 if (ret == DRC_TEST_VAL)
7044 SysPrintf("test passed.\n");
7045 else
7046 SysPrintf("test failed: %08x\n", ret);
7047 out=(u_char *)BASE_ADDR;
7048 return ret == DRC_TEST_VAL;
7049}
7050
dc990066 7051// clear the state completely, instead of just marking
7052// things invalid like invalidate_all_pages() does
7053void new_dynarec_clear_full()
57871462 7054{
57871462 7055 int n;
35775df7 7056 out=(u_char *)BASE_ADDR;
7057 memset(invalid_code,1,sizeof(invalid_code));
7058 memset(hash_table,0xff,sizeof(hash_table));
57871462 7059 memset(mini_ht,-1,sizeof(mini_ht));
7060 memset(restore_candidate,0,sizeof(restore_candidate));
dc990066 7061 memset(shadow,0,sizeof(shadow));
57871462 7062 copy=shadow;
7063 expirep=16384; // Expiry pointer, +2 blocks
7064 pending_exception=0;
7065 literalcount=0;
57871462 7066 stop_after_jal=0;
9be4ba64 7067 inv_code_start=inv_code_end=~0;
57871462 7068 // TLB
dc990066 7069 for(n=0;n<4096;n++) ll_clear(jump_in+n);
7070 for(n=0;n<4096;n++) ll_clear(jump_out+n);
7071 for(n=0;n<4096;n++) ll_clear(jump_dirty+n);
7072}
7073
7074void new_dynarec_init()
7075{
d848b60a 7076 SysPrintf("Init new dynarec\n");
dc990066 7077 out=(u_char *)BASE_ADDR;
a327ad27 7078#if BASE_ADDR_FIXED
dc990066 7079 if (mmap (out, 1<<TARGET_SIZE_2,
7080 PROT_READ | PROT_WRITE | PROT_EXEC,
7081 MAP_FIXED | MAP_PRIVATE | MAP_ANONYMOUS,
d848b60a 7082 -1, 0) <= 0) {
7083 SysPrintf("mmap() failed: %s\n", strerror(errno));
7084 }
bdeade46 7085#else
7086 // not all systems allow execute in data segment by default
7087 if (mprotect(out, 1<<TARGET_SIZE_2, PROT_READ | PROT_WRITE | PROT_EXEC) != 0)
d848b60a 7088 SysPrintf("mprotect() failed: %s\n", strerror(errno));
dc990066 7089#endif
7090 int n;
2573466a 7091 cycle_multiplier=200;
dc990066 7092 new_dynarec_clear_full();
7093#ifdef HOST_IMM8
7094 // Copy this into local area so we don't have to put it in every literal pool
7095 invc_ptr=invalid_code;
7096#endif
57871462 7097 arch_init();
d848b60a 7098 new_dynarec_test();
a327ad27 7099#ifndef RAM_FIXED
7100 ram_offset=(u_int)rdram-0x80000000;
7101#endif
b105cf4f 7102 if (ram_offset!=0)
c43b5311 7103 SysPrintf("warning: RAM is not directly mapped, performance will suffer\n");
57871462 7104}
7105
7106void new_dynarec_cleanup()
7107{
7108 int n;
a327ad27 7109 #if BASE_ADDR_FIXED
c43b5311 7110 if (munmap ((void *)BASE_ADDR, 1<<TARGET_SIZE_2) < 0) {SysPrintf("munmap() failed\n");}
bdeade46 7111 #endif
57871462 7112 for(n=0;n<4096;n++) ll_clear(jump_in+n);
7113 for(n=0;n<4096;n++) ll_clear(jump_out+n);
7114 for(n=0;n<4096;n++) ll_clear(jump_dirty+n);
7115 #ifdef ROM_COPY
c43b5311 7116 if (munmap (ROM_COPY, 67108864) < 0) {SysPrintf("munmap() failed\n");}
57871462 7117 #endif
7118}
7119
03f55e6b 7120static u_int *get_source_start(u_int addr, u_int *limit)
57871462 7121{
03f55e6b 7122 if (addr < 0x00200000 ||
7123 (0xa0000000 <= addr && addr < 0xa0200000)) {
7124 // used for BIOS calls mostly?
7125 *limit = (addr&0xa0000000)|0x00200000;
7126 return (u_int *)((u_int)rdram + (addr&0x1fffff));
7127 }
7128 else if (!Config.HLE && (
7129 /* (0x9fc00000 <= addr && addr < 0x9fc80000) ||*/
7130 (0xbfc00000 <= addr && addr < 0xbfc80000))) {
7131 // BIOS
7132 *limit = (addr & 0xfff00000) | 0x80000;
7133 return (u_int *)((u_int)psxR + (addr&0x7ffff));
7134 }
7135 else if (addr >= 0x80000000 && addr < 0x80000000+RAM_SIZE) {
7136 *limit = (addr & 0x80600000) + 0x00200000;
7137 return (u_int *)((u_int)rdram + (addr&0x1fffff));
7138 }
7139}
7140
7141static u_int scan_for_ret(u_int addr)
7142{
7143 u_int limit = 0;
7144 u_int *mem;
7145
7146 mem = get_source_start(addr, &limit);
7147 if (mem == NULL)
7148 return addr;
7149
7150 if (limit > addr + 0x1000)
7151 limit = addr + 0x1000;
7152 for (; addr < limit; addr += 4, mem++) {
7153 if (*mem == 0x03e00008) // jr $ra
7154 return addr + 8;
57871462 7155 }
03f55e6b 7156}
7157
7158struct savestate_block {
7159 uint32_t addr;
7160 uint32_t regflags;
7161};
7162
7163static int addr_cmp(const void *p1_, const void *p2_)
7164{
7165 const struct savestate_block *p1 = p1_, *p2 = p2_;
7166 return p1->addr - p2->addr;
7167}
7168
7169int new_dynarec_save_blocks(void *save, int size)
7170{
7171 struct savestate_block *blocks = save;
7172 int maxcount = size / sizeof(blocks[0]);
7173 struct savestate_block tmp_blocks[1024];
7174 struct ll_entry *head;
7175 int p, s, d, o, bcnt;
7176 u_int addr;
7177
7178 o = 0;
7179 for (p = 0; p < sizeof(jump_in) / sizeof(jump_in[0]); p++) {
7180 bcnt = 0;
7181 for (head = jump_in[p]; head != NULL; head = head->next) {
7182 tmp_blocks[bcnt].addr = head->vaddr;
7183 tmp_blocks[bcnt].regflags = head->reg_sv_flags;
7184 bcnt++;
7185 }
7186 if (bcnt < 1)
7187 continue;
7188 qsort(tmp_blocks, bcnt, sizeof(tmp_blocks[0]), addr_cmp);
7189
7190 addr = tmp_blocks[0].addr;
7191 for (s = d = 0; s < bcnt; s++) {
7192 if (tmp_blocks[s].addr < addr)
7193 continue;
7194 if (d == 0 || tmp_blocks[d-1].addr != tmp_blocks[s].addr)
7195 tmp_blocks[d++] = tmp_blocks[s];
7196 addr = scan_for_ret(tmp_blocks[s].addr);
7197 }
7198
7199 if (o + d > maxcount)
7200 d = maxcount - o;
7201 memcpy(&blocks[o], tmp_blocks, d * sizeof(blocks[0]));
7202 o += d;
7203 }
7204
7205 return o * sizeof(blocks[0]);
7206}
7207
7208void new_dynarec_load_blocks(const void *save, int size)
7209{
7210 const struct savestate_block *blocks = save;
7211 int count = size / sizeof(blocks[0]);
7212 u_int regs_save[32];
7213 uint32_t f;
7214 int i, b;
7215
7216 get_addr(psxRegs.pc);
7217
7218 // change GPRs for speculation to at least partially work..
7219 memcpy(regs_save, &psxRegs.GPR, sizeof(regs_save));
7220 for (i = 1; i < 32; i++)
7221 psxRegs.GPR.r[i] = 0x80000000;
7222
7223 for (b = 0; b < count; b++) {
7224 for (f = blocks[b].regflags, i = 0; f; f >>= 1, i++) {
7225 if (f & 1)
7226 psxRegs.GPR.r[i] = 0x1f800000;
7227 }
7228
7229 get_addr(blocks[b].addr);
7230
7231 for (f = blocks[b].regflags, i = 0; f; f >>= 1, i++) {
7232 if (f & 1)
7233 psxRegs.GPR.r[i] = 0x80000000;
7234 }
7235 }
7236
7237 memcpy(&psxRegs.GPR, regs_save, sizeof(regs_save));
7238}
7239
7240int new_recompile_block(int addr)
7241{
7242 u_int pagelimit = 0;
7243 u_int state_rflags = 0;
7244 int i;
7245
57871462 7246 assem_debug("NOTCOMPILED: addr = %x -> %x\n", (int)addr, (int)out);
7247 //printf("NOTCOMPILED: addr = %x -> %x\n", (int)addr, (int)out);
7248 //printf("TRACE: count=%d next=%d (compile %x)\n",Count,next_interupt,addr);
7249 //if(debug)
7250 //printf("TRACE: count=%d next=%d (checksum %x)\n",Count,next_interupt,mchecksum());
7251 //printf("fpu mapping=%x enabled=%x\n",(Status & 0x04000000)>>26,(Status & 0x20000000)>>29);
7252 /*if(Count>=312978186) {
7253 rlist();
7254 }*/
7255 //rlist();
03f55e6b 7256
7257 // this is just for speculation
7258 for (i = 1; i < 32; i++) {
7259 if ((psxRegs.GPR.r[i] & 0xffff0000) == 0x1f800000)
7260 state_rflags |= 1 << i;
7261 }
7262
57871462 7263 start = (u_int)addr&~3;
7264 //assert(((u_int)addr&1)==0);
2f546f9a 7265 new_dynarec_did_compile=1;
9ad4d757 7266 if (Config.HLE && start == 0x80001000) // hlecall
560e4a12 7267 {
7139f3c8 7268 // XXX: is this enough? Maybe check hleSoftCall?
bb5285ef 7269 u_int beginning=(u_int)out;
7139f3c8 7270 u_int page=get_page(start);
7139f3c8 7271 invalid_code[start>>12]=0;
7272 emit_movimm(start,0);
7273 emit_writeword(0,(int)&pcaddr);
bb5285ef 7274 emit_jmp((int)new_dyna_leave);
15776b68 7275 literal_pool(0);
bb5285ef 7276#ifdef __arm__
7277 __clear_cache((void *)beginning,out);
7278#endif
03f55e6b 7279 ll_add_flags(jump_in+page,start,state_rflags,(void *)beginning);
7139f3c8 7280 return 0;
7281 }
03f55e6b 7282
7283 source = get_source_start(start, &pagelimit);
7284 if (source == NULL) {
7285 SysPrintf("Compile at bogus memory address: %08x\n", addr);
57871462 7286 exit(1);
7287 }
7288
7289 /* Pass 1: disassemble */
7290 /* Pass 2: register dependencies, branch targets */
7291 /* Pass 3: register allocation */
7292 /* Pass 4: branch dependencies */
7293 /* Pass 5: pre-alloc */
7294 /* Pass 6: optimize clean/dirty state */
7295 /* Pass 7: flag 32-bit registers */
7296 /* Pass 8: assembly */
7297 /* Pass 9: linker */
7298 /* Pass 10: garbage collection / free memory */
7299
03f55e6b 7300 int j;
57871462 7301 int done=0;
7302 unsigned int type,op,op2;
7303
7304 //printf("addr = %x source = %x %x\n", addr,source,source[0]);
7305
7306 /* Pass 1 disassembly */
7307
7308 for(i=0;!done;i++) {
e1190b87 7309 bt[i]=0;likely[i]=0;ooo[i]=0;op2=0;
7310 minimum_free_regs[i]=0;
57871462 7311 opcode[i]=op=source[i]>>26;
7312 switch(op)
7313 {
7314 case 0x00: strcpy(insn[i],"special"); type=NI;
7315 op2=source[i]&0x3f;
7316 switch(op2)
7317 {
7318 case 0x00: strcpy(insn[i],"SLL"); type=SHIFTIMM; break;
7319 case 0x02: strcpy(insn[i],"SRL"); type=SHIFTIMM; break;
7320 case 0x03: strcpy(insn[i],"SRA"); type=SHIFTIMM; break;
7321 case 0x04: strcpy(insn[i],"SLLV"); type=SHIFT; break;
7322 case 0x06: strcpy(insn[i],"SRLV"); type=SHIFT; break;
7323 case 0x07: strcpy(insn[i],"SRAV"); type=SHIFT; break;
7324 case 0x08: strcpy(insn[i],"JR"); type=RJUMP; break;
7325 case 0x09: strcpy(insn[i],"JALR"); type=RJUMP; break;
7326 case 0x0C: strcpy(insn[i],"SYSCALL"); type=SYSCALL; break;
7327 case 0x0D: strcpy(insn[i],"BREAK"); type=OTHER; break;
7328 case 0x0F: strcpy(insn[i],"SYNC"); type=OTHER; break;
7329 case 0x10: strcpy(insn[i],"MFHI"); type=MOV; break;
7330 case 0x11: strcpy(insn[i],"MTHI"); type=MOV; break;
7331 case 0x12: strcpy(insn[i],"MFLO"); type=MOV; break;
7332 case 0x13: strcpy(insn[i],"MTLO"); type=MOV; break;
57871462 7333 case 0x18: strcpy(insn[i],"MULT"); type=MULTDIV; break;
7334 case 0x19: strcpy(insn[i],"MULTU"); type=MULTDIV; break;
7335 case 0x1A: strcpy(insn[i],"DIV"); type=MULTDIV; break;
7336 case 0x1B: strcpy(insn[i],"DIVU"); type=MULTDIV; break;
57871462 7337 case 0x20: strcpy(insn[i],"ADD"); type=ALU; break;
7338 case 0x21: strcpy(insn[i],"ADDU"); type=ALU; break;
7339 case 0x22: strcpy(insn[i],"SUB"); type=ALU; break;
7340 case 0x23: strcpy(insn[i],"SUBU"); type=ALU; break;
7341 case 0x24: strcpy(insn[i],"AND"); type=ALU; break;
7342 case 0x25: strcpy(insn[i],"OR"); type=ALU; break;
7343 case 0x26: strcpy(insn[i],"XOR"); type=ALU; break;
7344 case 0x27: strcpy(insn[i],"NOR"); type=ALU; break;
7345 case 0x2A: strcpy(insn[i],"SLT"); type=ALU; break;
7346 case 0x2B: strcpy(insn[i],"SLTU"); type=ALU; break;
57871462 7347 case 0x30: strcpy(insn[i],"TGE"); type=NI; break;
7348 case 0x31: strcpy(insn[i],"TGEU"); type=NI; break;
7349 case 0x32: strcpy(insn[i],"TLT"); type=NI; break;
7350 case 0x33: strcpy(insn[i],"TLTU"); type=NI; break;
7351 case 0x34: strcpy(insn[i],"TEQ"); type=NI; break;
7352 case 0x36: strcpy(insn[i],"TNE"); type=NI; break;
71e490c5 7353#if 0
7f2607ea 7354 case 0x14: strcpy(insn[i],"DSLLV"); type=SHIFT; break;
7355 case 0x16: strcpy(insn[i],"DSRLV"); type=SHIFT; break;
7356 case 0x17: strcpy(insn[i],"DSRAV"); type=SHIFT; break;
7357 case 0x1C: strcpy(insn[i],"DMULT"); type=MULTDIV; break;
7358 case 0x1D: strcpy(insn[i],"DMULTU"); type=MULTDIV; break;
7359 case 0x1E: strcpy(insn[i],"DDIV"); type=MULTDIV; break;
7360 case 0x1F: strcpy(insn[i],"DDIVU"); type=MULTDIV; break;
7361 case 0x2C: strcpy(insn[i],"DADD"); type=ALU; break;
7362 case 0x2D: strcpy(insn[i],"DADDU"); type=ALU; break;
7363 case 0x2E: strcpy(insn[i],"DSUB"); type=ALU; break;
7364 case 0x2F: strcpy(insn[i],"DSUBU"); type=ALU; break;
57871462 7365 case 0x38: strcpy(insn[i],"DSLL"); type=SHIFTIMM; break;
7366 case 0x3A: strcpy(insn[i],"DSRL"); type=SHIFTIMM; break;
7367 case 0x3B: strcpy(insn[i],"DSRA"); type=SHIFTIMM; break;
7368 case 0x3C: strcpy(insn[i],"DSLL32"); type=SHIFTIMM; break;
7369 case 0x3E: strcpy(insn[i],"DSRL32"); type=SHIFTIMM; break;
7370 case 0x3F: strcpy(insn[i],"DSRA32"); type=SHIFTIMM; break;
7f2607ea 7371#endif
57871462 7372 }
7373 break;
7374 case 0x01: strcpy(insn[i],"regimm"); type=NI;
7375 op2=(source[i]>>16)&0x1f;
7376 switch(op2)
7377 {
7378 case 0x00: strcpy(insn[i],"BLTZ"); type=SJUMP; break;
7379 case 0x01: strcpy(insn[i],"BGEZ"); type=SJUMP; break;
7380 case 0x02: strcpy(insn[i],"BLTZL"); type=SJUMP; break;
7381 case 0x03: strcpy(insn[i],"BGEZL"); type=SJUMP; break;
7382 case 0x08: strcpy(insn[i],"TGEI"); type=NI; break;
7383 case 0x09: strcpy(insn[i],"TGEIU"); type=NI; break;
7384 case 0x0A: strcpy(insn[i],"TLTI"); type=NI; break;
7385 case 0x0B: strcpy(insn[i],"TLTIU"); type=NI; break;
7386 case 0x0C: strcpy(insn[i],"TEQI"); type=NI; break;
7387 case 0x0E: strcpy(insn[i],"TNEI"); type=NI; break;
7388 case 0x10: strcpy(insn[i],"BLTZAL"); type=SJUMP; break;
7389 case 0x11: strcpy(insn[i],"BGEZAL"); type=SJUMP; break;
7390 case 0x12: strcpy(insn[i],"BLTZALL"); type=SJUMP; break;
7391 case 0x13: strcpy(insn[i],"BGEZALL"); type=SJUMP; break;
7392 }
7393 break;
7394 case 0x02: strcpy(insn[i],"J"); type=UJUMP; break;
7395 case 0x03: strcpy(insn[i],"JAL"); type=UJUMP; break;
7396 case 0x04: strcpy(insn[i],"BEQ"); type=CJUMP; break;
7397 case 0x05: strcpy(insn[i],"BNE"); type=CJUMP; break;
7398 case 0x06: strcpy(insn[i],"BLEZ"); type=CJUMP; break;
7399 case 0x07: strcpy(insn[i],"BGTZ"); type=CJUMP; break;
7400 case 0x08: strcpy(insn[i],"ADDI"); type=IMM16; break;
7401 case 0x09: strcpy(insn[i],"ADDIU"); type=IMM16; break;
7402 case 0x0A: strcpy(insn[i],"SLTI"); type=IMM16; break;
7403 case 0x0B: strcpy(insn[i],"SLTIU"); type=IMM16; break;
7404 case 0x0C: strcpy(insn[i],"ANDI"); type=IMM16; break;
7405 case 0x0D: strcpy(insn[i],"ORI"); type=IMM16; break;
7406 case 0x0E: strcpy(insn[i],"XORI"); type=IMM16; break;
7407 case 0x0F: strcpy(insn[i],"LUI"); type=IMM16; break;
7408 case 0x10: strcpy(insn[i],"cop0"); type=NI;
7409 op2=(source[i]>>21)&0x1f;
7410 switch(op2)
7411 {
7412 case 0x00: strcpy(insn[i],"MFC0"); type=COP0; break;
7413 case 0x04: strcpy(insn[i],"MTC0"); type=COP0; break;
7414 case 0x10: strcpy(insn[i],"tlb"); type=NI;
7415 switch(source[i]&0x3f)
7416 {
7417 case 0x01: strcpy(insn[i],"TLBR"); type=COP0; break;
7418 case 0x02: strcpy(insn[i],"TLBWI"); type=COP0; break;
7419 case 0x06: strcpy(insn[i],"TLBWR"); type=COP0; break;
7420 case 0x08: strcpy(insn[i],"TLBP"); type=COP0; break;
576bbd8f 7421 case 0x10: strcpy(insn[i],"RFE"); type=COP0; break;
71e490c5 7422 //case 0x18: strcpy(insn[i],"ERET"); type=COP0; break;
57871462 7423 }
7424 }
7425 break;
7426 case 0x11: strcpy(insn[i],"cop1"); type=NI;
7427 op2=(source[i]>>21)&0x1f;
7428 switch(op2)
7429 {
7430 case 0x00: strcpy(insn[i],"MFC1"); type=COP1; break;
7431 case 0x01: strcpy(insn[i],"DMFC1"); type=COP1; break;
7432 case 0x02: strcpy(insn[i],"CFC1"); type=COP1; break;
7433 case 0x04: strcpy(insn[i],"MTC1"); type=COP1; break;
7434 case 0x05: strcpy(insn[i],"DMTC1"); type=COP1; break;
7435 case 0x06: strcpy(insn[i],"CTC1"); type=COP1; break;
7436 case 0x08: strcpy(insn[i],"BC1"); type=FJUMP;
7437 switch((source[i]>>16)&0x3)
7438 {
7439 case 0x00: strcpy(insn[i],"BC1F"); break;
7440 case 0x01: strcpy(insn[i],"BC1T"); break;
7441 case 0x02: strcpy(insn[i],"BC1FL"); break;
7442 case 0x03: strcpy(insn[i],"BC1TL"); break;
7443 }
7444 break;
7445 case 0x10: strcpy(insn[i],"C1.S"); type=NI;
7446 switch(source[i]&0x3f)
7447 {
7448 case 0x00: strcpy(insn[i],"ADD.S"); type=FLOAT; break;
7449 case 0x01: strcpy(insn[i],"SUB.S"); type=FLOAT; break;
7450 case 0x02: strcpy(insn[i],"MUL.S"); type=FLOAT; break;
7451 case 0x03: strcpy(insn[i],"DIV.S"); type=FLOAT; break;
7452 case 0x04: strcpy(insn[i],"SQRT.S"); type=FLOAT; break;
7453 case 0x05: strcpy(insn[i],"ABS.S"); type=FLOAT; break;
7454 case 0x06: strcpy(insn[i],"MOV.S"); type=FLOAT; break;
7455 case 0x07: strcpy(insn[i],"NEG.S"); type=FLOAT; break;
7456 case 0x08: strcpy(insn[i],"ROUND.L.S"); type=FCONV; break;
7457 case 0x09: strcpy(insn[i],"TRUNC.L.S"); type=FCONV; break;
7458 case 0x0A: strcpy(insn[i],"CEIL.L.S"); type=FCONV; break;
7459 case 0x0B: strcpy(insn[i],"FLOOR.L.S"); type=FCONV; break;
7460 case 0x0C: strcpy(insn[i],"ROUND.W.S"); type=FCONV; break;
7461 case 0x0D: strcpy(insn[i],"TRUNC.W.S"); type=FCONV; break;
7462 case 0x0E: strcpy(insn[i],"CEIL.W.S"); type=FCONV; break;
7463 case 0x0F: strcpy(insn[i],"FLOOR.W.S"); type=FCONV; break;
7464 case 0x21: strcpy(insn[i],"CVT.D.S"); type=FCONV; break;
7465 case 0x24: strcpy(insn[i],"CVT.W.S"); type=FCONV; break;
7466 case 0x25: strcpy(insn[i],"CVT.L.S"); type=FCONV; break;
7467 case 0x30: strcpy(insn[i],"C.F.S"); type=FCOMP; break;
7468 case 0x31: strcpy(insn[i],"C.UN.S"); type=FCOMP; break;
7469 case 0x32: strcpy(insn[i],"C.EQ.S"); type=FCOMP; break;
7470 case 0x33: strcpy(insn[i],"C.UEQ.S"); type=FCOMP; break;
7471 case 0x34: strcpy(insn[i],"C.OLT.S"); type=FCOMP; break;
7472 case 0x35: strcpy(insn[i],"C.ULT.S"); type=FCOMP; break;
7473 case 0x36: strcpy(insn[i],"C.OLE.S"); type=FCOMP; break;
7474 case 0x37: strcpy(insn[i],"C.ULE.S"); type=FCOMP; break;
7475 case 0x38: strcpy(insn[i],"C.SF.S"); type=FCOMP; break;
7476 case 0x39: strcpy(insn[i],"C.NGLE.S"); type=FCOMP; break;
7477 case 0x3A: strcpy(insn[i],"C.SEQ.S"); type=FCOMP; break;
7478 case 0x3B: strcpy(insn[i],"C.NGL.S"); type=FCOMP; break;
7479 case 0x3C: strcpy(insn[i],"C.LT.S"); type=FCOMP; break;
7480 case 0x3D: strcpy(insn[i],"C.NGE.S"); type=FCOMP; break;
7481 case 0x3E: strcpy(insn[i],"C.LE.S"); type=FCOMP; break;
7482 case 0x3F: strcpy(insn[i],"C.NGT.S"); type=FCOMP; break;
7483 }
7484 break;
7485 case 0x11: strcpy(insn[i],"C1.D"); type=NI;
7486 switch(source[i]&0x3f)
7487 {
7488 case 0x00: strcpy(insn[i],"ADD.D"); type=FLOAT; break;
7489 case 0x01: strcpy(insn[i],"SUB.D"); type=FLOAT; break;
7490 case 0x02: strcpy(insn[i],"MUL.D"); type=FLOAT; break;
7491 case 0x03: strcpy(insn[i],"DIV.D"); type=FLOAT; break;
7492 case 0x04: strcpy(insn[i],"SQRT.D"); type=FLOAT; break;
7493 case 0x05: strcpy(insn[i],"ABS.D"); type=FLOAT; break;
7494 case 0x06: strcpy(insn[i],"MOV.D"); type=FLOAT; break;
7495 case 0x07: strcpy(insn[i],"NEG.D"); type=FLOAT; break;
7496 case 0x08: strcpy(insn[i],"ROUND.L.D"); type=FCONV; break;
7497 case 0x09: strcpy(insn[i],"TRUNC.L.D"); type=FCONV; break;
7498 case 0x0A: strcpy(insn[i],"CEIL.L.D"); type=FCONV; break;
7499 case 0x0B: strcpy(insn[i],"FLOOR.L.D"); type=FCONV; break;
7500 case 0x0C: strcpy(insn[i],"ROUND.W.D"); type=FCONV; break;
7501 case 0x0D: strcpy(insn[i],"TRUNC.W.D"); type=FCONV; break;
7502 case 0x0E: strcpy(insn[i],"CEIL.W.D"); type=FCONV; break;
7503 case 0x0F: strcpy(insn[i],"FLOOR.W.D"); type=FCONV; break;
7504 case 0x20: strcpy(insn[i],"CVT.S.D"); type=FCONV; break;
7505 case 0x24: strcpy(insn[i],"CVT.W.D"); type=FCONV; break;
7506 case 0x25: strcpy(insn[i],"CVT.L.D"); type=FCONV; break;
7507 case 0x30: strcpy(insn[i],"C.F.D"); type=FCOMP; break;
7508 case 0x31: strcpy(insn[i],"C.UN.D"); type=FCOMP; break;
7509 case 0x32: strcpy(insn[i],"C.EQ.D"); type=FCOMP; break;
7510 case 0x33: strcpy(insn[i],"C.UEQ.D"); type=FCOMP; break;
7511 case 0x34: strcpy(insn[i],"C.OLT.D"); type=FCOMP; break;
7512 case 0x35: strcpy(insn[i],"C.ULT.D"); type=FCOMP; break;
7513 case 0x36: strcpy(insn[i],"C.OLE.D"); type=FCOMP; break;
7514 case 0x37: strcpy(insn[i],"C.ULE.D"); type=FCOMP; break;
7515 case 0x38: strcpy(insn[i],"C.SF.D"); type=FCOMP; break;
7516 case 0x39: strcpy(insn[i],"C.NGLE.D"); type=FCOMP; break;
7517 case 0x3A: strcpy(insn[i],"C.SEQ.D"); type=FCOMP; break;
7518 case 0x3B: strcpy(insn[i],"C.NGL.D"); type=FCOMP; break;
7519 case 0x3C: strcpy(insn[i],"C.LT.D"); type=FCOMP; break;
7520 case 0x3D: strcpy(insn[i],"C.NGE.D"); type=FCOMP; break;
7521 case 0x3E: strcpy(insn[i],"C.LE.D"); type=FCOMP; break;
7522 case 0x3F: strcpy(insn[i],"C.NGT.D"); type=FCOMP; break;
7523 }
7524 break;
7525 case 0x14: strcpy(insn[i],"C1.W"); type=NI;
7526 switch(source[i]&0x3f)
7527 {
7528 case 0x20: strcpy(insn[i],"CVT.S.W"); type=FCONV; break;
7529 case 0x21: strcpy(insn[i],"CVT.D.W"); type=FCONV; break;
7530 }
7531 break;
7532 case 0x15: strcpy(insn[i],"C1.L"); type=NI;
7533 switch(source[i]&0x3f)
7534 {
7535 case 0x20: strcpy(insn[i],"CVT.S.L"); type=FCONV; break;
7536 case 0x21: strcpy(insn[i],"CVT.D.L"); type=FCONV; break;
7537 }
7538 break;
7539 }
7540 break;
71e490c5 7541#if 0
57871462 7542 case 0x14: strcpy(insn[i],"BEQL"); type=CJUMP; break;
7543 case 0x15: strcpy(insn[i],"BNEL"); type=CJUMP; break;
7544 case 0x16: strcpy(insn[i],"BLEZL"); type=CJUMP; break;
7545 case 0x17: strcpy(insn[i],"BGTZL"); type=CJUMP; break;
7546 case 0x18: strcpy(insn[i],"DADDI"); type=IMM16; break;
7547 case 0x19: strcpy(insn[i],"DADDIU"); type=IMM16; break;
7548 case 0x1A: strcpy(insn[i],"LDL"); type=LOADLR; break;
7549 case 0x1B: strcpy(insn[i],"LDR"); type=LOADLR; break;
996cc15d 7550#endif
57871462 7551 case 0x20: strcpy(insn[i],"LB"); type=LOAD; break;
7552 case 0x21: strcpy(insn[i],"LH"); type=LOAD; break;
7553 case 0x22: strcpy(insn[i],"LWL"); type=LOADLR; break;
7554 case 0x23: strcpy(insn[i],"LW"); type=LOAD; break;
7555 case 0x24: strcpy(insn[i],"LBU"); type=LOAD; break;
7556 case 0x25: strcpy(insn[i],"LHU"); type=LOAD; break;
7557 case 0x26: strcpy(insn[i],"LWR"); type=LOADLR; break;
71e490c5 7558#if 0
57871462 7559 case 0x27: strcpy(insn[i],"LWU"); type=LOAD; break;
64bd6f82 7560#endif
57871462 7561 case 0x28: strcpy(insn[i],"SB"); type=STORE; break;
7562 case 0x29: strcpy(insn[i],"SH"); type=STORE; break;
7563 case 0x2A: strcpy(insn[i],"SWL"); type=STORELR; break;
7564 case 0x2B: strcpy(insn[i],"SW"); type=STORE; break;
71e490c5 7565#if 0
57871462 7566 case 0x2C: strcpy(insn[i],"SDL"); type=STORELR; break;
7567 case 0x2D: strcpy(insn[i],"SDR"); type=STORELR; break;
996cc15d 7568#endif
57871462 7569 case 0x2E: strcpy(insn[i],"SWR"); type=STORELR; break;
7570 case 0x2F: strcpy(insn[i],"CACHE"); type=NOP; break;
7571 case 0x30: strcpy(insn[i],"LL"); type=NI; break;
7572 case 0x31: strcpy(insn[i],"LWC1"); type=C1LS; break;
71e490c5 7573#if 0
57871462 7574 case 0x34: strcpy(insn[i],"LLD"); type=NI; break;
7575 case 0x35: strcpy(insn[i],"LDC1"); type=C1LS; break;
7576 case 0x37: strcpy(insn[i],"LD"); type=LOAD; break;
996cc15d 7577#endif
57871462 7578 case 0x38: strcpy(insn[i],"SC"); type=NI; break;
7579 case 0x39: strcpy(insn[i],"SWC1"); type=C1LS; break;
71e490c5 7580#if 0
57871462 7581 case 0x3C: strcpy(insn[i],"SCD"); type=NI; break;
7582 case 0x3D: strcpy(insn[i],"SDC1"); type=C1LS; break;
7583 case 0x3F: strcpy(insn[i],"SD"); type=STORE; break;
996cc15d 7584#endif
b9b61529 7585 case 0x12: strcpy(insn[i],"COP2"); type=NI;
7586 op2=(source[i]>>21)&0x1f;
bedfea38 7587 //if (op2 & 0x10) {
7588 if (source[i]&0x3f) { // use this hack to support old savestates with patched gte insns
c7abc864 7589 if (gte_handlers[source[i]&0x3f]!=NULL) {
bedfea38 7590 if (gte_regnames[source[i]&0x3f]!=NULL)
7591 strcpy(insn[i],gte_regnames[source[i]&0x3f]);
7592 else
7593 snprintf(insn[i], sizeof(insn[i]), "COP2 %x", source[i]&0x3f);
c7abc864 7594 type=C2OP;
7595 }
7596 }
7597 else switch(op2)
b9b61529 7598 {
7599 case 0x00: strcpy(insn[i],"MFC2"); type=COP2; break;
7600 case 0x02: strcpy(insn[i],"CFC2"); type=COP2; break;
7601 case 0x04: strcpy(insn[i],"MTC2"); type=COP2; break;
7602 case 0x06: strcpy(insn[i],"CTC2"); type=COP2; break;
b9b61529 7603 }
7604 break;
7605 case 0x32: strcpy(insn[i],"LWC2"); type=C2LS; break;
7606 case 0x3A: strcpy(insn[i],"SWC2"); type=C2LS; break;
7607 case 0x3B: strcpy(insn[i],"HLECALL"); type=HLECALL; break;
90ae6d4e 7608 default: strcpy(insn[i],"???"); type=NI;
c43b5311 7609 SysPrintf("NI %08x @%08x (%08x)\n", source[i], addr + i*4, addr);
90ae6d4e 7610 break;
57871462 7611 }
7612 itype[i]=type;
7613 opcode2[i]=op2;
7614 /* Get registers/immediates */
7615 lt1[i]=0;
7616 us1[i]=0;
7617 us2[i]=0;
7618 dep1[i]=0;
7619 dep2[i]=0;
bedfea38 7620 gte_rs[i]=gte_rt[i]=0;
57871462 7621 switch(type) {
7622 case LOAD:
7623 rs1[i]=(source[i]>>21)&0x1f;
7624 rs2[i]=0;
7625 rt1[i]=(source[i]>>16)&0x1f;
7626 rt2[i]=0;
7627 imm[i]=(short)source[i];
7628 break;
7629 case STORE:
7630 case STORELR:
7631 rs1[i]=(source[i]>>21)&0x1f;
7632 rs2[i]=(source[i]>>16)&0x1f;
7633 rt1[i]=0;
7634 rt2[i]=0;
7635 imm[i]=(short)source[i];
7636 if(op==0x2c||op==0x2d||op==0x3f) us1[i]=rs2[i]; // 64-bit SDL/SDR/SD
7637 break;
7638 case LOADLR:
7639 // LWL/LWR only load part of the register,
7640 // therefore the target register must be treated as a source too
7641 rs1[i]=(source[i]>>21)&0x1f;
7642 rs2[i]=(source[i]>>16)&0x1f;
7643 rt1[i]=(source[i]>>16)&0x1f;
7644 rt2[i]=0;
7645 imm[i]=(short)source[i];
7646 if(op==0x1a||op==0x1b) us1[i]=rs2[i]; // LDR/LDL
7647 if(op==0x26) dep1[i]=rt1[i]; // LWR
7648 break;
7649 case IMM16:
7650 if (op==0x0f) rs1[i]=0; // LUI instruction has no source register
7651 else rs1[i]=(source[i]>>21)&0x1f;
7652 rs2[i]=0;
7653 rt1[i]=(source[i]>>16)&0x1f;
7654 rt2[i]=0;
7655 if(op>=0x0c&&op<=0x0e) { // ANDI/ORI/XORI
7656 imm[i]=(unsigned short)source[i];
7657 }else{
7658 imm[i]=(short)source[i];
7659 }
7660 if(op==0x18||op==0x19) us1[i]=rs1[i]; // DADDI/DADDIU
7661 if(op==0x0a||op==0x0b) us1[i]=rs1[i]; // SLTI/SLTIU
7662 if(op==0x0d||op==0x0e) dep1[i]=rs1[i]; // ORI/XORI
7663 break;
7664 case UJUMP:
7665 rs1[i]=0;
7666 rs2[i]=0;
7667 rt1[i]=0;
7668 rt2[i]=0;
7669 // The JAL instruction writes to r31.
7670 if (op&1) {
7671 rt1[i]=31;
7672 }
7673 rs2[i]=CCREG;
7674 break;
7675 case RJUMP:
7676 rs1[i]=(source[i]>>21)&0x1f;
7677 rs2[i]=0;
7678 rt1[i]=0;
7679 rt2[i]=0;
5067f341 7680 // The JALR instruction writes to rd.
57871462 7681 if (op2&1) {
5067f341 7682 rt1[i]=(source[i]>>11)&0x1f;
57871462 7683 }
7684 rs2[i]=CCREG;
7685 break;
7686 case CJUMP:
7687 rs1[i]=(source[i]>>21)&0x1f;
7688 rs2[i]=(source[i]>>16)&0x1f;
7689 rt1[i]=0;
7690 rt2[i]=0;
7691 if(op&2) { // BGTZ/BLEZ
7692 rs2[i]=0;
7693 }
7694 us1[i]=rs1[i];
7695 us2[i]=rs2[i];
7696 likely[i]=op>>4;
7697 break;
7698 case SJUMP:
7699 rs1[i]=(source[i]>>21)&0x1f;
7700 rs2[i]=CCREG;
7701 rt1[i]=0;
7702 rt2[i]=0;
7703 us1[i]=rs1[i];
7704 if(op2&0x10) { // BxxAL
7705 rt1[i]=31;
7706 // NOTE: If the branch is not taken, r31 is still overwritten
7707 }
7708 likely[i]=(op2&2)>>1;
7709 break;
7710 case FJUMP:
7711 rs1[i]=FSREG;
7712 rs2[i]=CSREG;
7713 rt1[i]=0;
7714 rt2[i]=0;
7715 likely[i]=((source[i])>>17)&1;
7716 break;
7717 case ALU:
7718 rs1[i]=(source[i]>>21)&0x1f; // source
7719 rs2[i]=(source[i]>>16)&0x1f; // subtract amount
7720 rt1[i]=(source[i]>>11)&0x1f; // destination
7721 rt2[i]=0;
7722 if(op2==0x2a||op2==0x2b) { // SLT/SLTU
7723 us1[i]=rs1[i];us2[i]=rs2[i];
7724 }
7725 else if(op2>=0x24&&op2<=0x27) { // AND/OR/XOR/NOR
7726 dep1[i]=rs1[i];dep2[i]=rs2[i];
7727 }
7728 else if(op2>=0x2c&&op2<=0x2f) { // DADD/DSUB
7729 dep1[i]=rs1[i];dep2[i]=rs2[i];
7730 }
7731 break;
7732 case MULTDIV:
7733 rs1[i]=(source[i]>>21)&0x1f; // source
7734 rs2[i]=(source[i]>>16)&0x1f; // divisor
7735 rt1[i]=HIREG;
7736 rt2[i]=LOREG;
7737 if (op2>=0x1c&&op2<=0x1f) { // DMULT/DMULTU/DDIV/DDIVU
7738 us1[i]=rs1[i];us2[i]=rs2[i];
7739 }
7740 break;
7741 case MOV:
7742 rs1[i]=0;
7743 rs2[i]=0;
7744 rt1[i]=0;
7745 rt2[i]=0;
7746 if(op2==0x10) rs1[i]=HIREG; // MFHI
7747 if(op2==0x11) rt1[i]=HIREG; // MTHI
7748 if(op2==0x12) rs1[i]=LOREG; // MFLO
7749 if(op2==0x13) rt1[i]=LOREG; // MTLO
7750 if((op2&0x1d)==0x10) rt1[i]=(source[i]>>11)&0x1f; // MFxx
7751 if((op2&0x1d)==0x11) rs1[i]=(source[i]>>21)&0x1f; // MTxx
7752 dep1[i]=rs1[i];
7753 break;
7754 case SHIFT:
7755 rs1[i]=(source[i]>>16)&0x1f; // target of shift
7756 rs2[i]=(source[i]>>21)&0x1f; // shift amount
7757 rt1[i]=(source[i]>>11)&0x1f; // destination
7758 rt2[i]=0;
7759 // DSLLV/DSRLV/DSRAV are 64-bit
7760 if(op2>=0x14&&op2<=0x17) us1[i]=rs1[i];
7761 break;
7762 case SHIFTIMM:
7763 rs1[i]=(source[i]>>16)&0x1f;
7764 rs2[i]=0;
7765 rt1[i]=(source[i]>>11)&0x1f;
7766 rt2[i]=0;
7767 imm[i]=(source[i]>>6)&0x1f;
7768 // DSxx32 instructions
7769 if(op2>=0x3c) imm[i]|=0x20;
7770 // DSLL/DSRL/DSRA/DSRA32/DSRL32 but not DSLL32 require 64-bit source
7771 if(op2>=0x38&&op2!=0x3c) us1[i]=rs1[i];
7772 break;
7773 case COP0:
7774 rs1[i]=0;
7775 rs2[i]=0;
7776 rt1[i]=0;
7777 rt2[i]=0;
7778 if(op2==0) rt1[i]=(source[i]>>16)&0x1F; // MFC0
7779 if(op2==4) rs1[i]=(source[i]>>16)&0x1F; // MTC0
7780 if(op2==4&&((source[i]>>11)&0x1f)==12) rt2[i]=CSREG; // Status
7781 if(op2==16) if((source[i]&0x3f)==0x18) rs2[i]=CCREG; // ERET
7782 break;
7783 case COP1:
7784 rs1[i]=0;
7785 rs2[i]=0;
7786 rt1[i]=0;
7787 rt2[i]=0;
7788 if(op2<3) rt1[i]=(source[i]>>16)&0x1F; // MFC1/DMFC1/CFC1
7789 if(op2>3) rs1[i]=(source[i]>>16)&0x1F; // MTC1/DMTC1/CTC1
7790 if(op2==5) us1[i]=rs1[i]; // DMTC1
7791 rs2[i]=CSREG;
7792 break;
bedfea38 7793 case COP2:
7794 rs1[i]=0;
7795 rs2[i]=0;
7796 rt1[i]=0;
7797 rt2[i]=0;
7798 if(op2<3) rt1[i]=(source[i]>>16)&0x1F; // MFC2/CFC2
7799 if(op2>3) rs1[i]=(source[i]>>16)&0x1F; // MTC2/CTC2
7800 rs2[i]=CSREG;
7801 int gr=(source[i]>>11)&0x1F;
7802 switch(op2)
7803 {
7804 case 0x00: gte_rs[i]=1ll<<gr; break; // MFC2
7805 case 0x04: gte_rt[i]=1ll<<gr; break; // MTC2
0ff8c62c 7806 case 0x02: gte_rs[i]=1ll<<(gr+32); break; // CFC2
bedfea38 7807 case 0x06: gte_rt[i]=1ll<<(gr+32); break; // CTC2
7808 }
7809 break;
57871462 7810 case C1LS:
7811 rs1[i]=(source[i]>>21)&0x1F;
7812 rs2[i]=CSREG;
7813 rt1[i]=0;
7814 rt2[i]=0;
7815 imm[i]=(short)source[i];
7816 break;
b9b61529 7817 case C2LS:
7818 rs1[i]=(source[i]>>21)&0x1F;
7819 rs2[i]=0;
7820 rt1[i]=0;
7821 rt2[i]=0;
7822 imm[i]=(short)source[i];
bedfea38 7823 if(op==0x32) gte_rt[i]=1ll<<((source[i]>>16)&0x1F); // LWC2
7824 else gte_rs[i]=1ll<<((source[i]>>16)&0x1F); // SWC2
7825 break;
7826 case C2OP:
7827 rs1[i]=0;
7828 rs2[i]=0;
7829 rt1[i]=0;
7830 rt2[i]=0;
2167bef6 7831 gte_rs[i]=gte_reg_reads[source[i]&0x3f];
7832 gte_rt[i]=gte_reg_writes[source[i]&0x3f];
7833 gte_rt[i]|=1ll<<63; // every op changes flags
587a5b1c 7834 if((source[i]&0x3f)==GTE_MVMVA) {
7835 int v = (source[i] >> 15) & 3;
7836 gte_rs[i]&=~0xe3fll;
7837 if(v==3) gte_rs[i]|=0xe00ll;
7838 else gte_rs[i]|=3ll<<(v*2);
7839 }
b9b61529 7840 break;
57871462 7841 case FLOAT:
7842 case FCONV:
7843 rs1[i]=0;
7844 rs2[i]=CSREG;
7845 rt1[i]=0;
7846 rt2[i]=0;
7847 break;
7848 case FCOMP:
7849 rs1[i]=FSREG;
7850 rs2[i]=CSREG;
7851 rt1[i]=FSREG;
7852 rt2[i]=0;
7853 break;
7854 case SYSCALL:
7139f3c8 7855 case HLECALL:
1e973cb0 7856 case INTCALL:
57871462 7857 rs1[i]=CCREG;
7858 rs2[i]=0;
7859 rt1[i]=0;
7860 rt2[i]=0;
7861 break;
7862 default:
7863 rs1[i]=0;
7864 rs2[i]=0;
7865 rt1[i]=0;
7866 rt2[i]=0;
7867 }
7868 /* Calculate branch target addresses */
7869 if(type==UJUMP)
7870 ba[i]=((start+i*4+4)&0xF0000000)|(((unsigned int)source[i]<<6)>>4);
7871 else if(type==CJUMP&&rs1[i]==rs2[i]&&(op&1))
7872 ba[i]=start+i*4+8; // Ignore never taken branch
7873 else if(type==SJUMP&&rs1[i]==0&&!(op2&1))
7874 ba[i]=start+i*4+8; // Ignore never taken branch
7875 else if(type==CJUMP||type==SJUMP||type==FJUMP)
7876 ba[i]=start+i*4+4+((signed int)((unsigned int)source[i]<<16)>>14);
7877 else ba[i]=-1;
3e535354 7878 if(i>0&&(itype[i-1]==RJUMP||itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP)) {
7879 int do_in_intrp=0;
7880 // branch in delay slot?
7881 if(type==RJUMP||type==UJUMP||type==CJUMP||type==SJUMP||type==FJUMP) {
7882 // don't handle first branch and call interpreter if it's hit
c43b5311 7883 SysPrintf("branch in delay slot @%08x (%08x)\n", addr + i*4, addr);
3e535354 7884 do_in_intrp=1;
7885 }
7886 // basic load delay detection
7887 else if((type==LOAD||type==LOADLR||type==COP0||type==COP2||type==C2LS)&&rt1[i]!=0) {
7888 int t=(ba[i-1]-start)/4;
7889 if(0 <= t && t < i &&(rt1[i]==rs1[t]||rt1[i]==rs2[t])&&itype[t]!=CJUMP&&itype[t]!=SJUMP) {
7890 // jump target wants DS result - potential load delay effect
c43b5311 7891 SysPrintf("load delay @%08x (%08x)\n", addr + i*4, addr);
3e535354 7892 do_in_intrp=1;
7893 bt[t+1]=1; // expected return from interpreter
7894 }
7895 else if(i>=2&&rt1[i-2]==2&&rt1[i]==2&&rs1[i]!=2&&rs2[i]!=2&&rs1[i-1]!=2&&rs2[i-1]!=2&&
7896 !(i>=3&&(itype[i-3]==RJUMP||itype[i-3]==UJUMP||itype[i-3]==CJUMP||itype[i-3]==SJUMP))) {
7897 // v0 overwrite like this is a sign of trouble, bail out
c43b5311 7898 SysPrintf("v0 overwrite @%08x (%08x)\n", addr + i*4, addr);
3e535354 7899 do_in_intrp=1;
7900 }
7901 }
3e535354 7902 if(do_in_intrp) {
7903 rs1[i-1]=CCREG;
7904 rs2[i-1]=rt1[i-1]=rt2[i-1]=0;
26869094 7905 ba[i-1]=-1;
7906 itype[i-1]=INTCALL;
7907 done=2;
3e535354 7908 i--; // don't compile the DS
26869094 7909 }
3e535354 7910 }
3e535354 7911 /* Is this the end of the block? */
7912 if(i>0&&(itype[i-1]==UJUMP||itype[i-1]==RJUMP||(source[i-1]>>16)==0x1000)) {
5067f341 7913 if(rt1[i-1]==0) { // Continue past subroutine call (JAL)
1e973cb0 7914 done=2;
57871462 7915 }
7916 else {
7917 if(stop_after_jal) done=1;
7918 // Stop on BREAK
7919 if((source[i+1]&0xfc00003f)==0x0d) done=1;
7920 }
7921 // Don't recompile stuff that's already compiled
7922 if(check_addr(start+i*4+4)) done=1;
7923 // Don't get too close to the limit
7924 if(i>MAXBLOCK/2) done=1;
7925 }
75dec299 7926 if(itype[i]==SYSCALL&&stop_after_jal) done=1;
1e973cb0 7927 if(itype[i]==HLECALL||itype[i]==INTCALL) done=2;
7928 if(done==2) {
7929 // Does the block continue due to a branch?
7930 for(j=i-1;j>=0;j--)
7931 {
2a706964 7932 if(ba[j]==start+i*4) done=j=0; // Branch into delay slot
1e973cb0 7933 if(ba[j]==start+i*4+4) done=j=0;
7934 if(ba[j]==start+i*4+8) done=j=0;
7935 }
7936 }
75dec299 7937 //assert(i<MAXBLOCK-1);
57871462 7938 if(start+i*4==pagelimit-4) done=1;
7939 assert(start+i*4<pagelimit);
7940 if (i==MAXBLOCK-1) done=1;
7941 // Stop if we're compiling junk
7942 if(itype[i]==NI&&opcode[i]==0x11) {
7943 done=stop_after_jal=1;
c43b5311 7944 SysPrintf("Disabled speculative precompilation\n");
57871462 7945 }
7946 }
7947 slen=i;
7948 if(itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==RJUMP||itype[i-1]==FJUMP) {
7949 if(start+i*4==pagelimit) {
7950 itype[i-1]=SPAN;
7951 }
7952 }
7953 assert(slen>0);
7954
7955 /* Pass 2 - Register dependencies and branch targets */
7956
7957 unneeded_registers(0,slen-1,0);
7958
7959 /* Pass 3 - Register allocation */
7960
7961 struct regstat current; // Current register allocations/status
7962 current.is32=1;
7963 current.dirty=0;
7964 current.u=unneeded_reg[0];
7965 current.uu=unneeded_reg_upper[0];
7966 clear_all_regs(current.regmap);
7967 alloc_reg(&current,0,CCREG);
7968 dirty_reg(&current,CCREG);
7969 current.isconst=0;
7970 current.wasconst=0;
27727b63 7971 current.waswritten=0;
57871462 7972 int ds=0;
7973 int cc=0;
5194fb95 7974 int hr=-1;
6ebf4adf 7975
57871462 7976 if((u_int)addr&1) {
7977 // First instruction is delay slot
7978 cc=-1;
7979 bt[1]=1;
7980 ds=1;
7981 unneeded_reg[0]=1;
7982 unneeded_reg_upper[0]=1;
7983 current.regmap[HOST_BTREG]=BTREG;
7984 }
7985
7986 for(i=0;i<slen;i++)
7987 {
7988 if(bt[i])
7989 {
7990 int hr;
7991 for(hr=0;hr<HOST_REGS;hr++)
7992 {
7993 // Is this really necessary?
7994 if(current.regmap[hr]==0) current.regmap[hr]=-1;
7995 }
7996 current.isconst=0;
27727b63 7997 current.waswritten=0;
57871462 7998 }
7999 if(i>1)
8000 {
8001 if((opcode[i-2]&0x2f)==0x05) // BNE/BNEL
8002 {
8003 if(rs1[i-2]==0||rs2[i-2]==0)
8004 {
8005 if(rs1[i-2]) {
8006 current.is32|=1LL<<rs1[i-2];
8007 int hr=get_reg(current.regmap,rs1[i-2]|64);
8008 if(hr>=0) current.regmap[hr]=-1;
8009 }
8010 if(rs2[i-2]) {
8011 current.is32|=1LL<<rs2[i-2];
8012 int hr=get_reg(current.regmap,rs2[i-2]|64);
8013 if(hr>=0) current.regmap[hr]=-1;
8014 }
8015 }
8016 }
8017 }
24385cae 8018 current.is32=-1LL;
24385cae 8019
57871462 8020 memcpy(regmap_pre[i],current.regmap,sizeof(current.regmap));
8021 regs[i].wasconst=current.isconst;
8022 regs[i].was32=current.is32;
8023 regs[i].wasdirty=current.dirty;
8575a877 8024 regs[i].loadedconst=0;
57871462 8025 if(itype[i]!=UJUMP&&itype[i]!=CJUMP&&itype[i]!=SJUMP&&itype[i]!=RJUMP&&itype[i]!=FJUMP) {
8026 if(i+1<slen) {
8027 current.u=unneeded_reg[i+1]&~((1LL<<rs1[i])|(1LL<<rs2[i]));
8028 current.uu=unneeded_reg_upper[i+1]&~((1LL<<us1[i])|(1LL<<us2[i]));
8029 if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
8030 current.u|=1;
8031 current.uu|=1;
8032 } else {
8033 current.u=1;
8034 current.uu=1;
8035 }
8036 } else {
8037 if(i+1<slen) {
8038 current.u=branch_unneeded_reg[i]&~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
8039 current.uu=branch_unneeded_reg_upper[i]&~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
8040 if((~current.uu>>rt1[i+1])&1) current.uu&=~((1LL<<dep1[i+1])|(1LL<<dep2[i+1]));
8041 current.u&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
8042 current.uu&=~((1LL<<us1[i])|(1LL<<us2[i]));
8043 current.u|=1;
8044 current.uu|=1;
c43b5311 8045 } else { SysPrintf("oops, branch at end of block with no delay slot\n");exit(1); }
57871462 8046 }
8047 is_ds[i]=ds;
8048 if(ds) {
8049 ds=0; // Skip delay slot, already allocated as part of branch
8050 // ...but we need to alloc it in case something jumps here
8051 if(i+1<slen) {
8052 current.u=branch_unneeded_reg[i-1]&unneeded_reg[i+1];
8053 current.uu=branch_unneeded_reg_upper[i-1]&unneeded_reg_upper[i+1];
8054 }else{
8055 current.u=branch_unneeded_reg[i-1];
8056 current.uu=branch_unneeded_reg_upper[i-1];
8057 }
8058 current.u&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
8059 current.uu&=~((1LL<<us1[i])|(1LL<<us2[i]));
8060 if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
8061 current.u|=1;
8062 current.uu|=1;
8063 struct regstat temp;
8064 memcpy(&temp,&current,sizeof(current));
8065 temp.wasdirty=temp.dirty;
8066 temp.was32=temp.is32;
8067 // TODO: Take into account unconditional branches, as below
8068 delayslot_alloc(&temp,i);
8069 memcpy(regs[i].regmap,temp.regmap,sizeof(temp.regmap));
8070 regs[i].wasdirty=temp.wasdirty;
8071 regs[i].was32=temp.was32;
8072 regs[i].dirty=temp.dirty;
8073 regs[i].is32=temp.is32;
8074 regs[i].isconst=0;
8075 regs[i].wasconst=0;
8076 current.isconst=0;
8077 // Create entry (branch target) regmap
8078 for(hr=0;hr<HOST_REGS;hr++)
8079 {
8080 int r=temp.regmap[hr];
8081 if(r>=0) {
8082 if(r!=regmap_pre[i][hr]) {
8083 regs[i].regmap_entry[hr]=-1;
8084 }
8085 else
8086 {
8087 if(r<64){
8088 if((current.u>>r)&1) {
8089 regs[i].regmap_entry[hr]=-1;
8090 regs[i].regmap[hr]=-1;
8091 //Don't clear regs in the delay slot as the branch might need them
8092 //current.regmap[hr]=-1;
8093 }else
8094 regs[i].regmap_entry[hr]=r;
8095 }
8096 else {
8097 if((current.uu>>(r&63))&1) {
8098 regs[i].regmap_entry[hr]=-1;
8099 regs[i].regmap[hr]=-1;
8100 //Don't clear regs in the delay slot as the branch might need them
8101 //current.regmap[hr]=-1;
8102 }else
8103 regs[i].regmap_entry[hr]=r;
8104 }
8105 }
8106 } else {
8107 // First instruction expects CCREG to be allocated
8108 if(i==0&&hr==HOST_CCREG)
8109 regs[i].regmap_entry[hr]=CCREG;
8110 else
8111 regs[i].regmap_entry[hr]=-1;
8112 }
8113 }
8114 }
8115 else { // Not delay slot
8116 switch(itype[i]) {
8117 case UJUMP:
8118 //current.isconst=0; // DEBUG
8119 //current.wasconst=0; // DEBUG
8120 //regs[i].wasconst=0; // DEBUG
8121 clear_const(&current,rt1[i]);
8122 alloc_cc(&current,i);
8123 dirty_reg(&current,CCREG);
8124 if (rt1[i]==31) {
8125 alloc_reg(&current,i,31);
8126 dirty_reg(&current,31);
4ef8f67d 8127 //assert(rs1[i+1]!=31&&rs2[i+1]!=31);
8128 //assert(rt1[i+1]!=rt1[i]);
57871462 8129 #ifdef REG_PREFETCH
8130 alloc_reg(&current,i,PTEMP);
8131 #endif
8132 //current.is32|=1LL<<rt1[i];
8133 }
269bb29a 8134 ooo[i]=1;
8135 delayslot_alloc(&current,i+1);
57871462 8136 //current.isconst=0; // DEBUG
8137 ds=1;
8138 //printf("i=%d, isconst=%x\n",i,current.isconst);
8139 break;
8140 case RJUMP:
8141 //current.isconst=0;
8142 //current.wasconst=0;
8143 //regs[i].wasconst=0;
8144 clear_const(&current,rs1[i]);
8145 clear_const(&current,rt1[i]);
8146 alloc_cc(&current,i);
8147 dirty_reg(&current,CCREG);
8148 if(rs1[i]!=rt1[i+1]&&rs1[i]!=rt2[i+1]) {
8149 alloc_reg(&current,i,rs1[i]);
5067f341 8150 if (rt1[i]!=0) {
8151 alloc_reg(&current,i,rt1[i]);
8152 dirty_reg(&current,rt1[i]);
68b3faee 8153 assert(rs1[i+1]!=rt1[i]&&rs2[i+1]!=rt1[i]);
076655d1 8154 assert(rt1[i+1]!=rt1[i]);
57871462 8155 #ifdef REG_PREFETCH
8156 alloc_reg(&current,i,PTEMP);
8157 #endif
8158 }
8159 #ifdef USE_MINI_HT
8160 if(rs1[i]==31) { // JALR
8161 alloc_reg(&current,i,RHASH);
8162 #ifndef HOST_IMM_ADDR32
8163 alloc_reg(&current,i,RHTBL);
8164 #endif
8165 }
8166 #endif
8167 delayslot_alloc(&current,i+1);
8168 } else {
8169 // The delay slot overwrites our source register,
8170 // allocate a temporary register to hold the old value.
8171 current.isconst=0;
8172 current.wasconst=0;
8173 regs[i].wasconst=0;
8174 delayslot_alloc(&current,i+1);
8175 current.isconst=0;
8176 alloc_reg(&current,i,RTEMP);
8177 }
8178 //current.isconst=0; // DEBUG
e1190b87 8179 ooo[i]=1;
57871462 8180 ds=1;
8181 break;
8182 case CJUMP:
8183 //current.isconst=0;
8184 //current.wasconst=0;
8185 //regs[i].wasconst=0;
8186 clear_const(&current,rs1[i]);
8187 clear_const(&current,rs2[i]);
8188 if((opcode[i]&0x3E)==4) // BEQ/BNE
8189 {
8190 alloc_cc(&current,i);
8191 dirty_reg(&current,CCREG);
8192 if(rs1[i]) alloc_reg(&current,i,rs1[i]);
8193 if(rs2[i]) alloc_reg(&current,i,rs2[i]);
8194 if(!((current.is32>>rs1[i])&(current.is32>>rs2[i])&1))
8195 {
8196 if(rs1[i]) alloc_reg64(&current,i,rs1[i]);
8197 if(rs2[i]) alloc_reg64(&current,i,rs2[i]);
8198 }
8199 if((rs1[i]&&(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1]))||
8200 (rs2[i]&&(rs2[i]==rt1[i+1]||rs2[i]==rt2[i+1]))) {
8201 // The delay slot overwrites one of our conditions.
8202 // Allocate the branch condition registers instead.
57871462 8203 current.isconst=0;
8204 current.wasconst=0;
8205 regs[i].wasconst=0;
8206 if(rs1[i]) alloc_reg(&current,i,rs1[i]);
8207 if(rs2[i]) alloc_reg(&current,i,rs2[i]);
8208 if(!((current.is32>>rs1[i])&(current.is32>>rs2[i])&1))
8209 {
8210 if(rs1[i]) alloc_reg64(&current,i,rs1[i]);
8211 if(rs2[i]) alloc_reg64(&current,i,rs2[i]);
8212 }
8213 }
e1190b87 8214 else
8215 {
8216 ooo[i]=1;
8217 delayslot_alloc(&current,i+1);
8218 }
57871462 8219 }
8220 else
8221 if((opcode[i]&0x3E)==6) // BLEZ/BGTZ
8222 {
8223 alloc_cc(&current,i);
8224 dirty_reg(&current,CCREG);
8225 alloc_reg(&current,i,rs1[i]);
8226 if(!(current.is32>>rs1[i]&1))
8227 {
8228 alloc_reg64(&current,i,rs1[i]);
8229 }
8230 if(rs1[i]&&(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1])) {
8231 // The delay slot overwrites one of our conditions.
8232 // Allocate the branch condition registers instead.
57871462 8233 current.isconst=0;
8234 current.wasconst=0;
8235 regs[i].wasconst=0;
8236 if(rs1[i]) alloc_reg(&current,i,rs1[i]);
8237 if(!((current.is32>>rs1[i])&1))
8238 {
8239 if(rs1[i]) alloc_reg64(&current,i,rs1[i]);
8240 }
8241 }
e1190b87 8242 else
8243 {
8244 ooo[i]=1;
8245 delayslot_alloc(&current,i+1);
8246 }
57871462 8247 }
8248 else
8249 // Don't alloc the delay slot yet because we might not execute it
8250 if((opcode[i]&0x3E)==0x14) // BEQL/BNEL
8251 {
8252 current.isconst=0;
8253 current.wasconst=0;
8254 regs[i].wasconst=0;
8255 alloc_cc(&current,i);
8256 dirty_reg(&current,CCREG);
8257 alloc_reg(&current,i,rs1[i]);
8258 alloc_reg(&current,i,rs2[i]);
8259 if(!((current.is32>>rs1[i])&(current.is32>>rs2[i])&1))
8260 {
8261 alloc_reg64(&current,i,rs1[i]);
8262 alloc_reg64(&current,i,rs2[i]);
8263 }
8264 }
8265 else
8266 if((opcode[i]&0x3E)==0x16) // BLEZL/BGTZL
8267 {
8268 current.isconst=0;
8269 current.wasconst=0;
8270 regs[i].wasconst=0;
8271 alloc_cc(&current,i);
8272 dirty_reg(&current,CCREG);
8273 alloc_reg(&current,i,rs1[i]);
8274 if(!(current.is32>>rs1[i]&1))
8275 {
8276 alloc_reg64(&current,i,rs1[i]);
8277 }
8278 }
8279 ds=1;
8280 //current.isconst=0;
8281 break;
8282 case SJUMP:
8283 //current.isconst=0;
8284 //current.wasconst=0;
8285 //regs[i].wasconst=0;
8286 clear_const(&current,rs1[i]);
8287 clear_const(&current,rt1[i]);
8288 //if((opcode2[i]&0x1E)==0x0) // BLTZ/BGEZ
8289 if((opcode2[i]&0x0E)==0x0) // BLTZ/BGEZ
8290 {
8291 alloc_cc(&current,i);
8292 dirty_reg(&current,CCREG);
8293 alloc_reg(&current,i,rs1[i]);
8294 if(!(current.is32>>rs1[i]&1))
8295 {
8296 alloc_reg64(&current,i,rs1[i]);
8297 }
8298 if (rt1[i]==31) { // BLTZAL/BGEZAL
8299 alloc_reg(&current,i,31);
8300 dirty_reg(&current,31);
57871462 8301 //#ifdef REG_PREFETCH
8302 //alloc_reg(&current,i,PTEMP);
8303 //#endif
8304 //current.is32|=1LL<<rt1[i];
8305 }
e1190b87 8306 if((rs1[i]&&(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1])) // The delay slot overwrites the branch condition.
8307 ||(rt1[i]==31&&(rs1[i+1]==31||rs2[i+1]==31||rt1[i+1]==31||rt2[i+1]==31))) { // DS touches $ra
57871462 8308 // Allocate the branch condition registers instead.
57871462 8309 current.isconst=0;
8310 current.wasconst=0;
8311 regs[i].wasconst=0;
8312 if(rs1[i]) alloc_reg(&current,i,rs1[i]);
8313 if(!((current.is32>>rs1[i])&1))
8314 {
8315 if(rs1[i]) alloc_reg64(&current,i,rs1[i]);
8316 }
8317 }
e1190b87 8318 else
8319 {
8320 ooo[i]=1;
8321 delayslot_alloc(&current,i+1);
8322 }
57871462 8323 }
8324 else
8325 // Don't alloc the delay slot yet because we might not execute it
8326 if((opcode2[i]&0x1E)==0x2) // BLTZL/BGEZL
8327 {
8328 current.isconst=0;
8329 current.wasconst=0;
8330 regs[i].wasconst=0;
8331 alloc_cc(&current,i);
8332 dirty_reg(&current,CCREG);
8333 alloc_reg(&current,i,rs1[i]);
8334 if(!(current.is32>>rs1[i]&1))
8335 {
8336 alloc_reg64(&current,i,rs1[i]);
8337 }
8338 }
8339 ds=1;
8340 //current.isconst=0;
8341 break;
8342 case FJUMP:
8343 current.isconst=0;
8344 current.wasconst=0;
8345 regs[i].wasconst=0;
8346 if(likely[i]==0) // BC1F/BC1T
8347 {
8348 // TODO: Theoretically we can run out of registers here on x86.
8349 // The delay slot can allocate up to six, and we need to check
8350 // CSREG before executing the delay slot. Possibly we can drop
8351 // the cycle count and then reload it after checking that the
8352 // FPU is in a usable state, or don't do out-of-order execution.
8353 alloc_cc(&current,i);
8354 dirty_reg(&current,CCREG);
8355 alloc_reg(&current,i,FSREG);
8356 alloc_reg(&current,i,CSREG);
8357 if(itype[i+1]==FCOMP) {
8358 // The delay slot overwrites the branch condition.
8359 // Allocate the branch condition registers instead.
57871462 8360 alloc_cc(&current,i);
8361 dirty_reg(&current,CCREG);
8362 alloc_reg(&current,i,CSREG);
8363 alloc_reg(&current,i,FSREG);
8364 }
8365 else {
e1190b87 8366 ooo[i]=1;
57871462 8367 delayslot_alloc(&current,i+1);
8368 alloc_reg(&current,i+1,CSREG);
8369 }
8370 }
8371 else
8372 // Don't alloc the delay slot yet because we might not execute it
8373 if(likely[i]) // BC1FL/BC1TL
8374 {
8375 alloc_cc(&current,i);
8376 dirty_reg(&current,CCREG);
8377 alloc_reg(&current,i,CSREG);
8378 alloc_reg(&current,i,FSREG);
8379 }
8380 ds=1;
8381 current.isconst=0;
8382 break;
8383 case IMM16:
8384 imm16_alloc(&current,i);
8385 break;
8386 case LOAD:
8387 case LOADLR:
8388 load_alloc(&current,i);
8389 break;
8390 case STORE:
8391 case STORELR:
8392 store_alloc(&current,i);
8393 break;
8394 case ALU:
8395 alu_alloc(&current,i);
8396 break;
8397 case SHIFT:
8398 shift_alloc(&current,i);
8399 break;
8400 case MULTDIV:
8401 multdiv_alloc(&current,i);
8402 break;
8403 case SHIFTIMM:
8404 shiftimm_alloc(&current,i);
8405 break;
8406 case MOV:
8407 mov_alloc(&current,i);
8408 break;
8409 case COP0:
8410 cop0_alloc(&current,i);
8411 break;
8412 case COP1:
b9b61529 8413 case COP2:
57871462 8414 cop1_alloc(&current,i);
8415 break;
8416 case C1LS:
8417 c1ls_alloc(&current,i);
8418 break;
b9b61529 8419 case C2LS:
8420 c2ls_alloc(&current,i);
8421 break;
8422 case C2OP:
8423 c2op_alloc(&current,i);
8424 break;
57871462 8425 case FCONV:
8426 fconv_alloc(&current,i);
8427 break;
8428 case FLOAT:
8429 float_alloc(&current,i);
8430 break;
8431 case FCOMP:
8432 fcomp_alloc(&current,i);
8433 break;
8434 case SYSCALL:
7139f3c8 8435 case HLECALL:
1e973cb0 8436 case INTCALL:
57871462 8437 syscall_alloc(&current,i);
8438 break;
8439 case SPAN:
8440 pagespan_alloc(&current,i);
8441 break;
8442 }
8443
8444 // Drop the upper half of registers that have become 32-bit
8445 current.uu|=current.is32&((1LL<<rt1[i])|(1LL<<rt2[i]));
8446 if(itype[i]!=UJUMP&&itype[i]!=CJUMP&&itype[i]!=SJUMP&&itype[i]!=RJUMP&&itype[i]!=FJUMP) {
8447 current.uu&=~((1LL<<us1[i])|(1LL<<us2[i]));
8448 if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
8449 current.uu|=1;
8450 } else {
8451 current.uu|=current.is32&((1LL<<rt1[i+1])|(1LL<<rt2[i+1]));
8452 current.uu&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
8453 if((~current.uu>>rt1[i+1])&1) current.uu&=~((1LL<<dep1[i+1])|(1LL<<dep2[i+1]));
8454 current.uu&=~((1LL<<us1[i])|(1LL<<us2[i]));
8455 current.uu|=1;
8456 }
8457
8458 // Create entry (branch target) regmap
8459 for(hr=0;hr<HOST_REGS;hr++)
8460 {
8461 int r,or,er;
8462 r=current.regmap[hr];
8463 if(r>=0) {
8464 if(r!=regmap_pre[i][hr]) {
8465 // TODO: delay slot (?)
8466 or=get_reg(regmap_pre[i],r); // Get old mapping for this register
8467 if(or<0||(r&63)>=TEMPREG){
8468 regs[i].regmap_entry[hr]=-1;
8469 }
8470 else
8471 {
8472 // Just move it to a different register
8473 regs[i].regmap_entry[hr]=r;
8474 // If it was dirty before, it's still dirty
8475 if((regs[i].wasdirty>>or)&1) dirty_reg(&current,r&63);
8476 }
8477 }
8478 else
8479 {
8480 // Unneeded
8481 if(r==0){
8482 regs[i].regmap_entry[hr]=0;
8483 }
8484 else
8485 if(r<64){
8486 if((current.u>>r)&1) {
8487 regs[i].regmap_entry[hr]=-1;
8488 //regs[i].regmap[hr]=-1;
8489 current.regmap[hr]=-1;
8490 }else
8491 regs[i].regmap_entry[hr]=r;
8492 }
8493 else {
8494 if((current.uu>>(r&63))&1) {
8495 regs[i].regmap_entry[hr]=-1;
8496 //regs[i].regmap[hr]=-1;
8497 current.regmap[hr]=-1;
8498 }else
8499 regs[i].regmap_entry[hr]=r;
8500 }
8501 }
8502 } else {
8503 // Branches expect CCREG to be allocated at the target
8504 if(regmap_pre[i][hr]==CCREG)
8505 regs[i].regmap_entry[hr]=CCREG;
8506 else
8507 regs[i].regmap_entry[hr]=-1;
8508 }
8509 }
8510 memcpy(regs[i].regmap,current.regmap,sizeof(current.regmap));
8511 }
27727b63 8512
8513 if(i>0&&(itype[i-1]==STORE||itype[i-1]==STORELR||(itype[i-1]==C2LS&&opcode[i-1]==0x3a))&&(u_int)imm[i-1]<0x800)
8514 current.waswritten|=1<<rs1[i-1];
8515 current.waswritten&=~(1<<rt1[i]);
8516 current.waswritten&=~(1<<rt2[i]);
8517 if((itype[i]==STORE||itype[i]==STORELR||(itype[i]==C2LS&&opcode[i]==0x3a))&&(u_int)imm[i]>=0x800)
8518 current.waswritten&=~(1<<rs1[i]);
8519
57871462 8520 /* Branch post-alloc */
8521 if(i>0)
8522 {
8523 current.was32=current.is32;
8524 current.wasdirty=current.dirty;
8525 switch(itype[i-1]) {
8526 case UJUMP:
8527 memcpy(&branch_regs[i-1],&current,sizeof(current));
8528 branch_regs[i-1].isconst=0;
8529 branch_regs[i-1].wasconst=0;
8530 branch_regs[i-1].u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i-1])|(1LL<<rs2[i-1]));
8531 branch_regs[i-1].uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i-1])|(1LL<<us2[i-1]));
8532 alloc_cc(&branch_regs[i-1],i-1);
8533 dirty_reg(&branch_regs[i-1],CCREG);
8534 if(rt1[i-1]==31) { // JAL
8535 alloc_reg(&branch_regs[i-1],i-1,31);
8536 dirty_reg(&branch_regs[i-1],31);
8537 branch_regs[i-1].is32|=1LL<<31;
8538 }
8539 memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
956f3129 8540 memcpy(constmap[i],constmap[i-1],sizeof(current_constmap));
57871462 8541 break;
8542 case RJUMP:
8543 memcpy(&branch_regs[i-1],&current,sizeof(current));
8544 branch_regs[i-1].isconst=0;
8545 branch_regs[i-1].wasconst=0;
8546 branch_regs[i-1].u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i-1])|(1LL<<rs2[i-1]));
8547 branch_regs[i-1].uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i-1])|(1LL<<us2[i-1]));
8548 alloc_cc(&branch_regs[i-1],i-1);
8549 dirty_reg(&branch_regs[i-1],CCREG);
8550 alloc_reg(&branch_regs[i-1],i-1,rs1[i-1]);
5067f341 8551 if(rt1[i-1]!=0) { // JALR
8552 alloc_reg(&branch_regs[i-1],i-1,rt1[i-1]);
8553 dirty_reg(&branch_regs[i-1],rt1[i-1]);
8554 branch_regs[i-1].is32|=1LL<<rt1[i-1];
57871462 8555 }
8556 #ifdef USE_MINI_HT
8557 if(rs1[i-1]==31) { // JALR
8558 alloc_reg(&branch_regs[i-1],i-1,RHASH);
8559 #ifndef HOST_IMM_ADDR32
8560 alloc_reg(&branch_regs[i-1],i-1,RHTBL);
8561 #endif
8562 }
8563 #endif
8564 memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
956f3129 8565 memcpy(constmap[i],constmap[i-1],sizeof(current_constmap));
57871462 8566 break;
8567 case CJUMP:
8568 if((opcode[i-1]&0x3E)==4) // BEQ/BNE
8569 {
8570 alloc_cc(&current,i-1);
8571 dirty_reg(&current,CCREG);
8572 if((rs1[i-1]&&(rs1[i-1]==rt1[i]||rs1[i-1]==rt2[i]))||
8573 (rs2[i-1]&&(rs2[i-1]==rt1[i]||rs2[i-1]==rt2[i]))) {
8574 // The delay slot overwrote one of our conditions
8575 // Delay slot goes after the test (in order)
8576 current.u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i]));
8577 current.uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i]));
8578 if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
8579 current.u|=1;
8580 current.uu|=1;
8581 delayslot_alloc(&current,i);
8582 current.isconst=0;
8583 }
8584 else
8585 {
8586 current.u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i-1])|(1LL<<rs2[i-1]));
8587 current.uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i-1])|(1LL<<us2[i-1]));
8588 // Alloc the branch condition registers
8589 if(rs1[i-1]) alloc_reg(&current,i-1,rs1[i-1]);
8590 if(rs2[i-1]) alloc_reg(&current,i-1,rs2[i-1]);
8591 if(!((current.is32>>rs1[i-1])&(current.is32>>rs2[i-1])&1))
8592 {
8593 if(rs1[i-1]) alloc_reg64(&current,i-1,rs1[i-1]);
8594 if(rs2[i-1]) alloc_reg64(&current,i-1,rs2[i-1]);
8595 }
8596 }
8597 memcpy(&branch_regs[i-1],&current,sizeof(current));
8598 branch_regs[i-1].isconst=0;
8599 branch_regs[i-1].wasconst=0;
8600 memcpy(&branch_regs[i-1].regmap_entry,&current.regmap,sizeof(current.regmap));
956f3129 8601 memcpy(constmap[i],constmap[i-1],sizeof(current_constmap));
57871462 8602 }
8603 else
8604 if((opcode[i-1]&0x3E)==6) // BLEZ/BGTZ
8605 {
8606 alloc_cc(&current,i-1);
8607 dirty_reg(&current,CCREG);
8608 if(rs1[i-1]==rt1[i]||rs1[i-1]==rt2[i]) {
8609 // The delay slot overwrote the branch condition
8610 // Delay slot goes after the test (in order)
8611 current.u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i]));
8612 current.uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i]));
8613 if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
8614 current.u|=1;
8615 current.uu|=1;
8616 delayslot_alloc(&current,i);
8617 current.isconst=0;
8618 }
8619 else
8620 {
8621 current.u=branch_unneeded_reg[i-1]&~(1LL<<rs1[i-1]);
8622 current.uu=branch_unneeded_reg_upper[i-1]&~(1LL<<us1[i-1]);
8623 // Alloc the branch condition register
8624 alloc_reg(&current,i-1,rs1[i-1]);
8625 if(!(current.is32>>rs1[i-1]&1))
8626 {
8627 alloc_reg64(&current,i-1,rs1[i-1]);
8628 }
8629 }
8630 memcpy(&branch_regs[i-1],&current,sizeof(current));
8631 branch_regs[i-1].isconst=0;
8632 branch_regs[i-1].wasconst=0;
8633 memcpy(&branch_regs[i-1].regmap_entry,&current.regmap,sizeof(current.regmap));
956f3129 8634 memcpy(constmap[i],constmap[i-1],sizeof(current_constmap));
57871462 8635 }
8636 else
8637 // Alloc the delay slot in case the branch is taken
8638 if((opcode[i-1]&0x3E)==0x14) // BEQL/BNEL
8639 {
8640 memcpy(&branch_regs[i-1],&current,sizeof(current));
8641 branch_regs[i-1].u=(branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
8642 branch_regs[i-1].uu=(branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
8643 if((~branch_regs[i-1].uu>>rt1[i])&1) branch_regs[i-1].uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]))|1;
8644 alloc_cc(&branch_regs[i-1],i);
8645 dirty_reg(&branch_regs[i-1],CCREG);
8646 delayslot_alloc(&branch_regs[i-1],i);
8647 branch_regs[i-1].isconst=0;
8648 alloc_reg(&current,i,CCREG); // Not taken path
8649 dirty_reg(&current,CCREG);
8650 memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
8651 }
8652 else
8653 if((opcode[i-1]&0x3E)==0x16) // BLEZL/BGTZL
8654 {
8655 memcpy(&branch_regs[i-1],&current,sizeof(current));
8656 branch_regs[i-1].u=(branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
8657 branch_regs[i-1].uu=(branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
8658 if((~branch_regs[i-1].uu>>rt1[i])&1) branch_regs[i-1].uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]))|1;
8659 alloc_cc(&branch_regs[i-1],i);
8660 dirty_reg(&branch_regs[i-1],CCREG);
8661 delayslot_alloc(&branch_regs[i-1],i);
8662 branch_regs[i-1].isconst=0;
8663 alloc_reg(&current,i,CCREG); // Not taken path
8664 dirty_reg(&current,CCREG);
8665 memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
8666 }
8667 break;
8668 case SJUMP:
8669 //if((opcode2[i-1]&0x1E)==0) // BLTZ/BGEZ
8670 if((opcode2[i-1]&0x0E)==0) // BLTZ/BGEZ
8671 {
8672 alloc_cc(&current,i-1);
8673 dirty_reg(&current,CCREG);
8674 if(rs1[i-1]==rt1[i]||rs1[i-1]==rt2[i]) {
8675 // The delay slot overwrote the branch condition
8676 // Delay slot goes after the test (in order)
8677 current.u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i]));
8678 current.uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i]));
8679 if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
8680 current.u|=1;
8681 current.uu|=1;
8682 delayslot_alloc(&current,i);
8683 current.isconst=0;
8684 }
8685 else
8686 {
8687 current.u=branch_unneeded_reg[i-1]&~(1LL<<rs1[i-1]);
8688 current.uu=branch_unneeded_reg_upper[i-1]&~(1LL<<us1[i-1]);
8689 // Alloc the branch condition register
8690 alloc_reg(&current,i-1,rs1[i-1]);
8691 if(!(current.is32>>rs1[i-1]&1))
8692 {
8693 alloc_reg64(&current,i-1,rs1[i-1]);
8694 }
8695 }
8696 memcpy(&branch_regs[i-1],&current,sizeof(current));
8697 branch_regs[i-1].isconst=0;
8698 branch_regs[i-1].wasconst=0;
8699 memcpy(&branch_regs[i-1].regmap_entry,&current.regmap,sizeof(current.regmap));
956f3129 8700 memcpy(constmap[i],constmap[i-1],sizeof(current_constmap));
57871462 8701 }
8702 else
8703 // Alloc the delay slot in case the branch is taken
8704 if((opcode2[i-1]&0x1E)==2) // BLTZL/BGEZL
8705 {
8706 memcpy(&branch_regs[i-1],&current,sizeof(current));
8707 branch_regs[i-1].u=(branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
8708 branch_regs[i-1].uu=(branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
8709 if((~branch_regs[i-1].uu>>rt1[i])&1) branch_regs[i-1].uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]))|1;
8710 alloc_cc(&branch_regs[i-1],i);
8711 dirty_reg(&branch_regs[i-1],CCREG);
8712 delayslot_alloc(&branch_regs[i-1],i);
8713 branch_regs[i-1].isconst=0;
8714 alloc_reg(&current,i,CCREG); // Not taken path
8715 dirty_reg(&current,CCREG);
8716 memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
8717 }
8718 // FIXME: BLTZAL/BGEZAL
8719 if(opcode2[i-1]&0x10) { // BxxZAL
8720 alloc_reg(&branch_regs[i-1],i-1,31);
8721 dirty_reg(&branch_regs[i-1],31);
8722 branch_regs[i-1].is32|=1LL<<31;
8723 }
8724 break;
8725 case FJUMP:
8726 if(likely[i-1]==0) // BC1F/BC1T
8727 {
8728 alloc_cc(&current,i-1);
8729 dirty_reg(&current,CCREG);
8730 if(itype[i]==FCOMP) {
8731 // The delay slot overwrote the branch condition
8732 // Delay slot goes after the test (in order)
8733 delayslot_alloc(&current,i);
8734 current.isconst=0;
8735 }
8736 else
8737 {
8738 current.u=branch_unneeded_reg[i-1]&~(1LL<<rs1[i-1]);
8739 current.uu=branch_unneeded_reg_upper[i-1]&~(1LL<<us1[i-1]);
8740 // Alloc the branch condition register
8741 alloc_reg(&current,i-1,FSREG);
8742 }
8743 memcpy(&branch_regs[i-1],&current,sizeof(current));
8744 memcpy(&branch_regs[i-1].regmap_entry,&current.regmap,sizeof(current.regmap));
8745 }
8746 else // BC1FL/BC1TL
8747 {
8748 // Alloc the delay slot in case the branch is taken
8749 memcpy(&branch_regs[i-1],&current,sizeof(current));
8750 branch_regs[i-1].u=(branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
8751 branch_regs[i-1].uu=(branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
8752 if((~branch_regs[i-1].uu>>rt1[i])&1) branch_regs[i-1].uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]))|1;
8753 alloc_cc(&branch_regs[i-1],i);
8754 dirty_reg(&branch_regs[i-1],CCREG);
8755 delayslot_alloc(&branch_regs[i-1],i);
8756 branch_regs[i-1].isconst=0;
8757 alloc_reg(&current,i,CCREG); // Not taken path
8758 dirty_reg(&current,CCREG);
8759 memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
8760 }
8761 break;
8762 }
8763
8764 if(itype[i-1]==UJUMP||itype[i-1]==RJUMP||(source[i-1]>>16)==0x1000)
8765 {
8766 if(rt1[i-1]==31) // JAL/JALR
8767 {
8768 // Subroutine call will return here, don't alloc any registers
8769 current.is32=1;
8770 current.dirty=0;
8771 clear_all_regs(current.regmap);
8772 alloc_reg(&current,i,CCREG);
8773 dirty_reg(&current,CCREG);
8774 }
8775 else if(i+1<slen)
8776 {
8777 // Internal branch will jump here, match registers to caller
8778 current.is32=0x3FFFFFFFFLL;
8779 current.dirty=0;
8780 clear_all_regs(current.regmap);
8781 alloc_reg(&current,i,CCREG);
8782 dirty_reg(&current,CCREG);
8783 for(j=i-1;j>=0;j--)
8784 {
8785 if(ba[j]==start+i*4+4) {
8786 memcpy(current.regmap,branch_regs[j].regmap,sizeof(current.regmap));
8787 current.is32=branch_regs[j].is32;
8788 current.dirty=branch_regs[j].dirty;
8789 break;
8790 }
8791 }
8792 while(j>=0) {
8793 if(ba[j]==start+i*4+4) {
8794 for(hr=0;hr<HOST_REGS;hr++) {
8795 if(current.regmap[hr]!=branch_regs[j].regmap[hr]) {
8796 current.regmap[hr]=-1;
8797 }
8798 current.is32&=branch_regs[j].is32;
8799 current.dirty&=branch_regs[j].dirty;
8800 }
8801 }
8802 j--;
8803 }
8804 }
8805 }
8806 }
8807
8808 // Count cycles in between branches
8809 ccadj[i]=cc;
7139f3c8 8810 if(i>0&&(itype[i-1]==RJUMP||itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP||itype[i]==SYSCALL||itype[i]==HLECALL))
57871462 8811 {
8812 cc=0;
8813 }
71e490c5 8814#if !defined(DRC_DBG)
054175e9 8815 else if(itype[i]==C2OP&&gte_cycletab[source[i]&0x3f]>2)
8816 {
8817 // GTE runs in parallel until accessed, divide by 2 for a rough guess
8818 cc+=gte_cycletab[source[i]&0x3f]/2;
8819 }
b6e87b2b 8820 else if(/*itype[i]==LOAD||itype[i]==STORE||*/itype[i]==C1LS) // load,store causes weird timing issues
fb407447 8821 {
8822 cc+=2; // 2 cycle penalty (after CLOCK_DIVIDER)
8823 }
5fdcbb5a 8824 else if(i>1&&itype[i]==STORE&&itype[i-1]==STORE&&itype[i-2]==STORE&&!bt[i])
8825 {
8826 cc+=4;
8827 }
fb407447 8828 else if(itype[i]==C2LS)
8829 {
8830 cc+=4;
8831 }
8832#endif
57871462 8833 else
8834 {
8835 cc++;
8836 }
8837
8838 flush_dirty_uppers(&current);
8839 if(!is_ds[i]) {
8840 regs[i].is32=current.is32;
8841 regs[i].dirty=current.dirty;
8842 regs[i].isconst=current.isconst;
956f3129 8843 memcpy(constmap[i],current_constmap,sizeof(current_constmap));
57871462 8844 }
8845 for(hr=0;hr<HOST_REGS;hr++) {
8846 if(hr!=EXCLUDE_REG&&regs[i].regmap[hr]>=0) {
8847 if(regmap_pre[i][hr]!=regs[i].regmap[hr]) {
8848 regs[i].wasconst&=~(1<<hr);
8849 }
8850 }
8851 }
8852 if(current.regmap[HOST_BTREG]==BTREG) current.regmap[HOST_BTREG]=-1;
27727b63 8853 regs[i].waswritten=current.waswritten;
57871462 8854 }
8855
8856 /* Pass 4 - Cull unused host registers */
8857
8858 uint64_t nr=0;
8859
8860 for (i=slen-1;i>=0;i--)
8861 {
8862 int hr;
8863 if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
8864 {
8865 if(ba[i]<start || ba[i]>=(start+slen*4))
8866 {
8867 // Branch out of this block, don't need anything
8868 nr=0;
8869 }
8870 else
8871 {
8872 // Internal branch
8873 // Need whatever matches the target
8874 nr=0;
8875 int t=(ba[i]-start)>>2;
8876 for(hr=0;hr<HOST_REGS;hr++)
8877 {
8878 if(regs[i].regmap_entry[hr]>=0) {
8879 if(regs[i].regmap_entry[hr]==regs[t].regmap_entry[hr]) nr|=1<<hr;
8880 }
8881 }
8882 }
8883 // Conditional branch may need registers for following instructions
8884 if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000)
8885 {
8886 if(i<slen-2) {
8887 nr|=needed_reg[i+2];
8888 for(hr=0;hr<HOST_REGS;hr++)
8889 {
8890 if(regmap_pre[i+2][hr]>=0&&get_reg(regs[i+2].regmap_entry,regmap_pre[i+2][hr])<0) nr&=~(1<<hr);
8891 //if((regmap_entry[i+2][hr])>=0) if(!((nr>>hr)&1)) printf("%x-bogus(%d=%d)\n",start+i*4,hr,regmap_entry[i+2][hr]);
8892 }
8893 }
8894 }
8895 // Don't need stuff which is overwritten
f5955059 8896 //if(regs[i].regmap[hr]!=regmap_pre[i][hr]) nr&=~(1<<hr);
8897 //if(regs[i].regmap[hr]<0) nr&=~(1<<hr);
57871462 8898 // Merge in delay slot
8899 for(hr=0;hr<HOST_REGS;hr++)
8900 {
8901 if(!likely[i]) {
8902 // These are overwritten unless the branch is "likely"
8903 // and the delay slot is nullified if not taken
8904 if(rt1[i+1]&&rt1[i+1]==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
8905 if(rt2[i+1]&&rt2[i+1]==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
8906 }
8907 if(us1[i+1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
8908 if(us2[i+1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
8909 if(rs1[i+1]==regmap_pre[i][hr]) nr|=1<<hr;
8910 if(rs2[i+1]==regmap_pre[i][hr]) nr|=1<<hr;
8911 if(us1[i+1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
8912 if(us2[i+1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
8913 if(rs1[i+1]==regs[i].regmap_entry[hr]) nr|=1<<hr;
8914 if(rs2[i+1]==regs[i].regmap_entry[hr]) nr|=1<<hr;
8915 if(dep1[i+1]&&!((unneeded_reg_upper[i]>>dep1[i+1])&1)) {
8916 if(dep1[i+1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
8917 if(dep2[i+1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
8918 }
8919 if(dep2[i+1]&&!((unneeded_reg_upper[i]>>dep2[i+1])&1)) {
8920 if(dep1[i+1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
8921 if(dep2[i+1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
8922 }
b9b61529 8923 if(itype[i+1]==STORE || itype[i+1]==STORELR || (opcode[i+1]&0x3b)==0x39 || (opcode[i+1]&0x3b)==0x3a) {
57871462 8924 if(regmap_pre[i][hr]==INVCP) nr|=1<<hr;
8925 if(regs[i].regmap_entry[hr]==INVCP) nr|=1<<hr;
8926 }
8927 }
8928 }
1e973cb0 8929 else if(itype[i]==SYSCALL||itype[i]==HLECALL||itype[i]==INTCALL)
57871462 8930 {
8931 // SYSCALL instruction (software interrupt)
8932 nr=0;
8933 }
8934 else if(itype[i]==COP0 && (source[i]&0x3f)==0x18)
8935 {
8936 // ERET instruction (return from interrupt)
8937 nr=0;
8938 }
8939 else // Non-branch
8940 {
8941 if(i<slen-1) {
8942 for(hr=0;hr<HOST_REGS;hr++) {
8943 if(regmap_pre[i+1][hr]>=0&&get_reg(regs[i+1].regmap_entry,regmap_pre[i+1][hr])<0) nr&=~(1<<hr);
8944 if(regs[i].regmap[hr]!=regmap_pre[i+1][hr]) nr&=~(1<<hr);
8945 if(regs[i].regmap[hr]!=regmap_pre[i][hr]) nr&=~(1<<hr);
8946 if(regs[i].regmap[hr]<0) nr&=~(1<<hr);
8947 }
8948 }
8949 }
8950 for(hr=0;hr<HOST_REGS;hr++)
8951 {
8952 // Overwritten registers are not needed
8953 if(rt1[i]&&rt1[i]==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
8954 if(rt2[i]&&rt2[i]==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
8955 if(FTEMP==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
8956 // Source registers are needed
8957 if(us1[i]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
8958 if(us2[i]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
8959 if(rs1[i]==regmap_pre[i][hr]) nr|=1<<hr;
8960 if(rs2[i]==regmap_pre[i][hr]) nr|=1<<hr;
8961 if(us1[i]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
8962 if(us2[i]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
8963 if(rs1[i]==regs[i].regmap_entry[hr]) nr|=1<<hr;
8964 if(rs2[i]==regs[i].regmap_entry[hr]) nr|=1<<hr;
8965 if(dep1[i]&&!((unneeded_reg_upper[i]>>dep1[i])&1)) {
8966 if(dep1[i]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
8967 if(dep1[i]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
8968 }
8969 if(dep2[i]&&!((unneeded_reg_upper[i]>>dep2[i])&1)) {
8970 if(dep2[i]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
8971 if(dep2[i]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
8972 }
b9b61529 8973 if(itype[i]==STORE || itype[i]==STORELR || (opcode[i]&0x3b)==0x39 || (opcode[i]&0x3b)==0x3a) {
57871462 8974 if(regmap_pre[i][hr]==INVCP) nr|=1<<hr;
8975 if(regs[i].regmap_entry[hr]==INVCP) nr|=1<<hr;
8976 }
8977 // Don't store a register immediately after writing it,
8978 // may prevent dual-issue.
8979 // But do so if this is a branch target, otherwise we
8980 // might have to load the register before the branch.
8981 if(i>0&&!bt[i]&&((regs[i].wasdirty>>hr)&1)) {
8982 if((regmap_pre[i][hr]>0&&regmap_pre[i][hr]<64&&!((unneeded_reg[i]>>regmap_pre[i][hr])&1)) ||
8983 (regmap_pre[i][hr]>64&&!((unneeded_reg_upper[i]>>(regmap_pre[i][hr]&63))&1)) ) {
8984 if(rt1[i-1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
8985 if(rt2[i-1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
8986 }
8987 if((regs[i].regmap_entry[hr]>0&&regs[i].regmap_entry[hr]<64&&!((unneeded_reg[i]>>regs[i].regmap_entry[hr])&1)) ||
8988 (regs[i].regmap_entry[hr]>64&&!((unneeded_reg_upper[i]>>(regs[i].regmap_entry[hr]&63))&1)) ) {
8989 if(rt1[i-1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
8990 if(rt2[i-1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
8991 }
8992 }
8993 }
8994 // Cycle count is needed at branches. Assume it is needed at the target too.
8995 if(i==0||bt[i]||itype[i]==CJUMP||itype[i]==FJUMP||itype[i]==SPAN) {
8996 if(regmap_pre[i][HOST_CCREG]==CCREG) nr|=1<<HOST_CCREG;
8997 if(regs[i].regmap_entry[HOST_CCREG]==CCREG) nr|=1<<HOST_CCREG;
8998 }
8999 // Save it
9000 needed_reg[i]=nr;
9001
9002 // Deallocate unneeded registers
9003 for(hr=0;hr<HOST_REGS;hr++)
9004 {
9005 if(!((nr>>hr)&1)) {
9006 if(regs[i].regmap_entry[hr]!=CCREG) regs[i].regmap_entry[hr]=-1;
9007 if((regs[i].regmap[hr]&63)!=rs1[i] && (regs[i].regmap[hr]&63)!=rs2[i] &&
9008 (regs[i].regmap[hr]&63)!=rt1[i] && (regs[i].regmap[hr]&63)!=rt2[i] &&
9009 (regs[i].regmap[hr]&63)!=PTEMP && (regs[i].regmap[hr]&63)!=CCREG)
9010 {
9011 if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000)
9012 {
9013 if(likely[i]) {
9014 regs[i].regmap[hr]=-1;
9015 regs[i].isconst&=~(1<<hr);
79c75f1b 9016 if(i<slen-2) {
9017 regmap_pre[i+2][hr]=-1;
9018 regs[i+2].wasconst&=~(1<<hr);
9019 }
57871462 9020 }
9021 }
9022 }
9023 if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
9024 {
9025 int d1=0,d2=0,map=0,temp=0;
9026 if(get_reg(regs[i].regmap,rt1[i+1]|64)>=0||get_reg(branch_regs[i].regmap,rt1[i+1]|64)>=0)
9027 {
9028 d1=dep1[i+1];
9029 d2=dep2[i+1];
9030 }
9031 if(using_tlb) {
9032 if(itype[i+1]==LOAD || itype[i+1]==LOADLR ||
9033 itype[i+1]==STORE || itype[i+1]==STORELR ||
b9b61529 9034 itype[i+1]==C1LS || itype[i+1]==C2LS)
57871462 9035 map=TLREG;
9036 } else
b9b61529 9037 if(itype[i+1]==STORE || itype[i+1]==STORELR ||
9038 (opcode[i+1]&0x3b)==0x39 || (opcode[i+1]&0x3b)==0x3a) { // SWC1/SDC1 || SWC2/SDC2
57871462 9039 map=INVCP;
9040 }
9041 if(itype[i+1]==LOADLR || itype[i+1]==STORELR ||
b9b61529 9042 itype[i+1]==C1LS || itype[i+1]==C2LS)
57871462 9043 temp=FTEMP;
9044 if((regs[i].regmap[hr]&63)!=rs1[i] && (regs[i].regmap[hr]&63)!=rs2[i] &&
9045 (regs[i].regmap[hr]&63)!=rt1[i] && (regs[i].regmap[hr]&63)!=rt2[i] &&
9046 (regs[i].regmap[hr]&63)!=rt1[i+1] && (regs[i].regmap[hr]&63)!=rt2[i+1] &&
9047 (regs[i].regmap[hr]^64)!=us1[i+1] && (regs[i].regmap[hr]^64)!=us2[i+1] &&
9048 (regs[i].regmap[hr]^64)!=d1 && (regs[i].regmap[hr]^64)!=d2 &&
9049 regs[i].regmap[hr]!=rs1[i+1] && regs[i].regmap[hr]!=rs2[i+1] &&
9050 (regs[i].regmap[hr]&63)!=temp && regs[i].regmap[hr]!=PTEMP &&
9051 regs[i].regmap[hr]!=RHASH && regs[i].regmap[hr]!=RHTBL &&
9052 regs[i].regmap[hr]!=RTEMP && regs[i].regmap[hr]!=CCREG &&
9053 regs[i].regmap[hr]!=map )
9054 {
9055 regs[i].regmap[hr]=-1;
9056 regs[i].isconst&=~(1<<hr);
9057 if((branch_regs[i].regmap[hr]&63)!=rs1[i] && (branch_regs[i].regmap[hr]&63)!=rs2[i] &&
9058 (branch_regs[i].regmap[hr]&63)!=rt1[i] && (branch_regs[i].regmap[hr]&63)!=rt2[i] &&
9059 (branch_regs[i].regmap[hr]&63)!=rt1[i+1] && (branch_regs[i].regmap[hr]&63)!=rt2[i+1] &&
9060 (branch_regs[i].regmap[hr]^64)!=us1[i+1] && (branch_regs[i].regmap[hr]^64)!=us2[i+1] &&
9061 (branch_regs[i].regmap[hr]^64)!=d1 && (branch_regs[i].regmap[hr]^64)!=d2 &&
9062 branch_regs[i].regmap[hr]!=rs1[i+1] && branch_regs[i].regmap[hr]!=rs2[i+1] &&
9063 (branch_regs[i].regmap[hr]&63)!=temp && branch_regs[i].regmap[hr]!=PTEMP &&
9064 branch_regs[i].regmap[hr]!=RHASH && branch_regs[i].regmap[hr]!=RHTBL &&
9065 branch_regs[i].regmap[hr]!=RTEMP && branch_regs[i].regmap[hr]!=CCREG &&
9066 branch_regs[i].regmap[hr]!=map)
9067 {
9068 branch_regs[i].regmap[hr]=-1;
9069 branch_regs[i].regmap_entry[hr]=-1;
9070 if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000)
9071 {
9072 if(!likely[i]&&i<slen-2) {
9073 regmap_pre[i+2][hr]=-1;
79c75f1b 9074 regs[i+2].wasconst&=~(1<<hr);
57871462 9075 }
9076 }
9077 }
9078 }
9079 }
9080 else
9081 {
9082 // Non-branch
9083 if(i>0)
9084 {
9085 int d1=0,d2=0,map=-1,temp=-1;
9086 if(get_reg(regs[i].regmap,rt1[i]|64)>=0)
9087 {
9088 d1=dep1[i];
9089 d2=dep2[i];
9090 }
9091 if(using_tlb) {
9092 if(itype[i]==LOAD || itype[i]==LOADLR ||
9093 itype[i]==STORE || itype[i]==STORELR ||
b9b61529 9094 itype[i]==C1LS || itype[i]==C2LS)
57871462 9095 map=TLREG;
b9b61529 9096 } else if(itype[i]==STORE || itype[i]==STORELR ||
9097 (opcode[i]&0x3b)==0x39 || (opcode[i]&0x3b)==0x3a) { // SWC1/SDC1 || SWC2/SDC2
57871462 9098 map=INVCP;
9099 }
9100 if(itype[i]==LOADLR || itype[i]==STORELR ||
b9b61529 9101 itype[i]==C1LS || itype[i]==C2LS)
57871462 9102 temp=FTEMP;
9103 if((regs[i].regmap[hr]&63)!=rt1[i] && (regs[i].regmap[hr]&63)!=rt2[i] &&
9104 (regs[i].regmap[hr]^64)!=us1[i] && (regs[i].regmap[hr]^64)!=us2[i] &&
9105 (regs[i].regmap[hr]^64)!=d1 && (regs[i].regmap[hr]^64)!=d2 &&
9106 regs[i].regmap[hr]!=rs1[i] && regs[i].regmap[hr]!=rs2[i] &&
9107 (regs[i].regmap[hr]&63)!=temp && regs[i].regmap[hr]!=map &&
9108 (itype[i]!=SPAN||regs[i].regmap[hr]!=CCREG))
9109 {
9110 if(i<slen-1&&!is_ds[i]) {
9111 if(regmap_pre[i+1][hr]!=-1 || regs[i].regmap[hr]!=-1)
9112 if(regmap_pre[i+1][hr]!=regs[i].regmap[hr])
9113 if(regs[i].regmap[hr]<64||!((regs[i].was32>>(regs[i].regmap[hr]&63))&1))
9114 {
c43b5311 9115 SysPrintf("fail: %x (%d %d!=%d)\n",start+i*4,hr,regmap_pre[i+1][hr],regs[i].regmap[hr]);
57871462 9116 assert(regmap_pre[i+1][hr]==regs[i].regmap[hr]);
9117 }
9118 regmap_pre[i+1][hr]=-1;
9119 if(regs[i+1].regmap_entry[hr]==CCREG) regs[i+1].regmap_entry[hr]=-1;
79c75f1b 9120 regs[i+1].wasconst&=~(1<<hr);
57871462 9121 }
9122 regs[i].regmap[hr]=-1;
9123 regs[i].isconst&=~(1<<hr);
9124 }
9125 }
9126 }
9127 }
9128 }
9129 }
9130
9131 /* Pass 5 - Pre-allocate registers */
9132
9133 // If a register is allocated during a loop, try to allocate it for the
9134 // entire loop, if possible. This avoids loading/storing registers
9135 // inside of the loop.
198df76f 9136
57871462 9137 signed char f_regmap[HOST_REGS];
9138 clear_all_regs(f_regmap);
9139 for(i=0;i<slen-1;i++)
9140 {
9141 if(itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
9142 {
9143 if(ba[i]>=start && ba[i]<(start+i*4))
9144 if(itype[i+1]==NOP||itype[i+1]==MOV||itype[i+1]==ALU
9145 ||itype[i+1]==SHIFTIMM||itype[i+1]==IMM16||itype[i+1]==LOAD
9146 ||itype[i+1]==STORE||itype[i+1]==STORELR||itype[i+1]==C1LS
9147 ||itype[i+1]==SHIFT||itype[i+1]==COP1||itype[i+1]==FLOAT
b9b61529 9148 ||itype[i+1]==FCOMP||itype[i+1]==FCONV
9149 ||itype[i+1]==COP2||itype[i+1]==C2LS||itype[i+1]==C2OP)
57871462 9150 {
9151 int t=(ba[i]-start)>>2;
9152 if(t>0&&(itype[t-1]!=UJUMP&&itype[t-1]!=RJUMP&&itype[t-1]!=CJUMP&&itype[t-1]!=SJUMP&&itype[t-1]!=FJUMP)) // loop_preload can't handle jumps into delay slots
198df76f 9153 if(t<2||(itype[t-2]!=UJUMP&&itype[t-2]!=RJUMP)||rt1[t-2]!=31) // call/ret assumes no registers allocated
57871462 9154 for(hr=0;hr<HOST_REGS;hr++)
9155 {
9156 if(regs[i].regmap[hr]>64) {
9157 if(!((regs[i].dirty>>hr)&1))
9158 f_regmap[hr]=regs[i].regmap[hr];
9159 else f_regmap[hr]=-1;
9160 }
b372a952 9161 else if(regs[i].regmap[hr]>=0) {
9162 if(f_regmap[hr]!=regs[i].regmap[hr]) {
9163 // dealloc old register
9164 int n;
9165 for(n=0;n<HOST_REGS;n++)
9166 {
9167 if(f_regmap[n]==regs[i].regmap[hr]) {f_regmap[n]=-1;}
9168 }
9169 // and alloc new one
9170 f_regmap[hr]=regs[i].regmap[hr];
9171 }
9172 }
57871462 9173 if(branch_regs[i].regmap[hr]>64) {
9174 if(!((branch_regs[i].dirty>>hr)&1))
9175 f_regmap[hr]=branch_regs[i].regmap[hr];
9176 else f_regmap[hr]=-1;
9177 }
b372a952 9178 else if(branch_regs[i].regmap[hr]>=0) {
9179 if(f_regmap[hr]!=branch_regs[i].regmap[hr]) {
9180 // dealloc old register
9181 int n;
9182 for(n=0;n<HOST_REGS;n++)
9183 {
9184 if(f_regmap[n]==branch_regs[i].regmap[hr]) {f_regmap[n]=-1;}
9185 }
9186 // and alloc new one
9187 f_regmap[hr]=branch_regs[i].regmap[hr];
9188 }
9189 }
e1190b87 9190 if(ooo[i]) {
9191 if(count_free_regs(regs[i].regmap)<=minimum_free_regs[i+1])
9192 f_regmap[hr]=branch_regs[i].regmap[hr];
9193 }else{
9194 if(count_free_regs(branch_regs[i].regmap)<=minimum_free_regs[i+1])
57871462 9195 f_regmap[hr]=branch_regs[i].regmap[hr];
9196 }
9197 // Avoid dirty->clean transition
e1190b87 9198 #ifdef DESTRUCTIVE_WRITEBACK
57871462 9199 if(t>0) if(get_reg(regmap_pre[t],f_regmap[hr])>=0) if((regs[t].wasdirty>>get_reg(regmap_pre[t],f_regmap[hr]))&1) f_regmap[hr]=-1;
e1190b87 9200 #endif
9201 // This check is only strictly required in the DESTRUCTIVE_WRITEBACK
9202 // case above, however it's always a good idea. We can't hoist the
9203 // load if the register was already allocated, so there's no point
9204 // wasting time analyzing most of these cases. It only "succeeds"
9205 // when the mapping was different and the load can be replaced with
9206 // a mov, which is of negligible benefit. So such cases are
9207 // skipped below.
57871462 9208 if(f_regmap[hr]>0) {
198df76f 9209 if(regs[t].regmap[hr]==f_regmap[hr]||(regs[t].regmap_entry[hr]<0&&get_reg(regmap_pre[t],f_regmap[hr])<0)) {
57871462 9210 int r=f_regmap[hr];
9211 for(j=t;j<=i;j++)
9212 {
9213 //printf("Test %x -> %x, %x %d/%d\n",start+i*4,ba[i],start+j*4,hr,r);
9214 if(r<34&&((unneeded_reg[j]>>r)&1)) break;
9215 if(r>63&&((unneeded_reg_upper[j]>>(r&63))&1)) break;
9216 if(r>63) {
9217 // NB This can exclude the case where the upper-half
9218 // register is lower numbered than the lower-half
9219 // register. Not sure if it's worth fixing...
9220 if(get_reg(regs[j].regmap,r&63)<0) break;
e1190b87 9221 if(get_reg(regs[j].regmap_entry,r&63)<0) break;
57871462 9222 if(regs[j].is32&(1LL<<(r&63))) break;
9223 }
9224 if(regs[j].regmap[hr]==f_regmap[hr]&&(f_regmap[hr]&63)<TEMPREG) {
9225 //printf("Hit %x -> %x, %x %d/%d\n",start+i*4,ba[i],start+j*4,hr,r);
9226 int k;
9227 if(regs[i].regmap[hr]==-1&&branch_regs[i].regmap[hr]==-1) {
9228 if(get_reg(regs[i+2].regmap,f_regmap[hr])>=0) break;
9229 if(r>63) {
9230 if(get_reg(regs[i].regmap,r&63)<0) break;
9231 if(get_reg(branch_regs[i].regmap,r&63)<0) break;
9232 }
9233 k=i;
9234 while(k>1&&regs[k-1].regmap[hr]==-1) {
e1190b87 9235 if(count_free_regs(regs[k-1].regmap)<=minimum_free_regs[k-1]) {
9236 //printf("no free regs for store %x\n",start+(k-1)*4);
9237 break;
57871462 9238 }
57871462 9239 if(get_reg(regs[k-1].regmap,f_regmap[hr])>=0) {
9240 //printf("no-match due to different register\n");
9241 break;
9242 }
9243 if(itype[k-2]==UJUMP||itype[k-2]==RJUMP||itype[k-2]==CJUMP||itype[k-2]==SJUMP||itype[k-2]==FJUMP) {
9244 //printf("no-match due to branch\n");
9245 break;
9246 }
9247 // call/ret fast path assumes no registers allocated
198df76f 9248 if(k>2&&(itype[k-3]==UJUMP||itype[k-3]==RJUMP)&&rt1[k-3]==31) {
57871462 9249 break;
9250 }
9251 if(r>63) {
9252 // NB This can exclude the case where the upper-half
9253 // register is lower numbered than the lower-half
9254 // register. Not sure if it's worth fixing...
9255 if(get_reg(regs[k-1].regmap,r&63)<0) break;
9256 if(regs[k-1].is32&(1LL<<(r&63))) break;
9257 }
9258 k--;
9259 }
9260 if(i<slen-1) {
9261 if((regs[k].is32&(1LL<<f_regmap[hr]))!=
9262 (regs[i+2].was32&(1LL<<f_regmap[hr]))) {
9263 //printf("bad match after branch\n");
9264 break;
9265 }
9266 }
9267 if(regs[k-1].regmap[hr]==f_regmap[hr]&&regmap_pre[k][hr]==f_regmap[hr]) {
9268 //printf("Extend r%d, %x ->\n",hr,start+k*4);
9269 while(k<i) {
9270 regs[k].regmap_entry[hr]=f_regmap[hr];
9271 regs[k].regmap[hr]=f_regmap[hr];
9272 regmap_pre[k+1][hr]=f_regmap[hr];
9273 regs[k].wasdirty&=~(1<<hr);
9274 regs[k].dirty&=~(1<<hr);
9275 regs[k].wasdirty|=(1<<hr)&regs[k-1].dirty;
9276 regs[k].dirty|=(1<<hr)&regs[k].wasdirty;
9277 regs[k].wasconst&=~(1<<hr);
9278 regs[k].isconst&=~(1<<hr);
9279 k++;
9280 }
9281 }
9282 else {
9283 //printf("Fail Extend r%d, %x ->\n",hr,start+k*4);
9284 break;
9285 }
9286 assert(regs[i-1].regmap[hr]==f_regmap[hr]);
9287 if(regs[i-1].regmap[hr]==f_regmap[hr]&&regmap_pre[i][hr]==f_regmap[hr]) {
9288 //printf("OK fill %x (r%d)\n",start+i*4,hr);
9289 regs[i].regmap_entry[hr]=f_regmap[hr];
9290 regs[i].regmap[hr]=f_regmap[hr];
9291 regs[i].wasdirty&=~(1<<hr);
9292 regs[i].dirty&=~(1<<hr);
9293 regs[i].wasdirty|=(1<<hr)&regs[i-1].dirty;
9294 regs[i].dirty|=(1<<hr)&regs[i-1].dirty;
9295 regs[i].wasconst&=~(1<<hr);
9296 regs[i].isconst&=~(1<<hr);
9297 branch_regs[i].regmap_entry[hr]=f_regmap[hr];
9298 branch_regs[i].wasdirty&=~(1<<hr);
9299 branch_regs[i].wasdirty|=(1<<hr)&regs[i].dirty;
9300 branch_regs[i].regmap[hr]=f_regmap[hr];
9301 branch_regs[i].dirty&=~(1<<hr);
9302 branch_regs[i].dirty|=(1<<hr)&regs[i].dirty;
9303 branch_regs[i].wasconst&=~(1<<hr);
9304 branch_regs[i].isconst&=~(1<<hr);
9305 if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000) {
9306 regmap_pre[i+2][hr]=f_regmap[hr];
9307 regs[i+2].wasdirty&=~(1<<hr);
9308 regs[i+2].wasdirty|=(1<<hr)&regs[i].dirty;
9309 assert((branch_regs[i].is32&(1LL<<f_regmap[hr]))==
9310 (regs[i+2].was32&(1LL<<f_regmap[hr])));
9311 }
9312 }
9313 }
9314 for(k=t;k<j;k++) {
e1190b87 9315 // Alloc register clean at beginning of loop,
9316 // but may dirty it in pass 6
57871462 9317 regs[k].regmap_entry[hr]=f_regmap[hr];
9318 regs[k].regmap[hr]=f_regmap[hr];
57871462 9319 regs[k].dirty&=~(1<<hr);
9320 regs[k].wasconst&=~(1<<hr);
9321 regs[k].isconst&=~(1<<hr);
e1190b87 9322 if(itype[k]==UJUMP||itype[k]==RJUMP||itype[k]==CJUMP||itype[k]==SJUMP||itype[k]==FJUMP) {
9323 branch_regs[k].regmap_entry[hr]=f_regmap[hr];
9324 branch_regs[k].regmap[hr]=f_regmap[hr];
9325 branch_regs[k].dirty&=~(1<<hr);
9326 branch_regs[k].wasconst&=~(1<<hr);
9327 branch_regs[k].isconst&=~(1<<hr);
9328 if(itype[k]!=RJUMP&&itype[k]!=UJUMP&&(source[k]>>16)!=0x1000) {
9329 regmap_pre[k+2][hr]=f_regmap[hr];
9330 regs[k+2].wasdirty&=~(1<<hr);
9331 assert((branch_regs[k].is32&(1LL<<f_regmap[hr]))==
9332 (regs[k+2].was32&(1LL<<f_regmap[hr])));
9333 }
9334 }
9335 else
9336 {
9337 regmap_pre[k+1][hr]=f_regmap[hr];
9338 regs[k+1].wasdirty&=~(1<<hr);
9339 }
57871462 9340 }
9341 if(regs[j].regmap[hr]==f_regmap[hr])
9342 regs[j].regmap_entry[hr]=f_regmap[hr];
9343 break;
9344 }
9345 if(j==i) break;
9346 if(regs[j].regmap[hr]>=0)
9347 break;
9348 if(get_reg(regs[j].regmap,f_regmap[hr])>=0) {
9349 //printf("no-match due to different register\n");
9350 break;
9351 }
9352 if((regs[j+1].is32&(1LL<<f_regmap[hr]))!=(regs[j].is32&(1LL<<f_regmap[hr]))) {
9353 //printf("32/64 mismatch %x %d\n",start+j*4,hr);
9354 break;
9355 }
e1190b87 9356 if(itype[j]==UJUMP||itype[j]==RJUMP||(source[j]>>16)==0x1000)
9357 {
9358 // Stop on unconditional branch
9359 break;
9360 }
9361 if(itype[j]==CJUMP||itype[j]==SJUMP||itype[j]==FJUMP)
9362 {
9363 if(ooo[j]) {
9364 if(count_free_regs(regs[j].regmap)<=minimum_free_regs[j+1])
9365 break;
9366 }else{
9367 if(count_free_regs(branch_regs[j].regmap)<=minimum_free_regs[j+1])
9368 break;
9369 }
9370 if(get_reg(branch_regs[j].regmap,f_regmap[hr])>=0) {
9371 //printf("no-match due to different register (branch)\n");
57871462 9372 break;
9373 }
9374 }
e1190b87 9375 if(count_free_regs(regs[j].regmap)<=minimum_free_regs[j]) {
9376 //printf("No free regs for store %x\n",start+j*4);
9377 break;
9378 }
57871462 9379 if(f_regmap[hr]>=64) {
9380 if(regs[j].is32&(1LL<<(f_regmap[hr]&63))) {
9381 break;
9382 }
9383 else
9384 {
9385 if(get_reg(regs[j].regmap,f_regmap[hr]&63)<0) {
9386 break;
9387 }
9388 }
9389 }
9390 }
9391 }
9392 }
9393 }
9394 }
9395 }else{
198df76f 9396 // Non branch or undetermined branch target
57871462 9397 for(hr=0;hr<HOST_REGS;hr++)
9398 {
9399 if(hr!=EXCLUDE_REG) {
9400 if(regs[i].regmap[hr]>64) {
9401 if(!((regs[i].dirty>>hr)&1))
9402 f_regmap[hr]=regs[i].regmap[hr];
9403 }
b372a952 9404 else if(regs[i].regmap[hr]>=0) {
9405 if(f_regmap[hr]!=regs[i].regmap[hr]) {
9406 // dealloc old register
9407 int n;
9408 for(n=0;n<HOST_REGS;n++)
9409 {
9410 if(f_regmap[n]==regs[i].regmap[hr]) {f_regmap[n]=-1;}
9411 }
9412 // and alloc new one
9413 f_regmap[hr]=regs[i].regmap[hr];
9414 }
9415 }
57871462 9416 }
9417 }
9418 // Try to restore cycle count at branch targets
9419 if(bt[i]) {
9420 for(j=i;j<slen-1;j++) {
9421 if(regs[j].regmap[HOST_CCREG]!=-1) break;
e1190b87 9422 if(count_free_regs(regs[j].regmap)<=minimum_free_regs[j]) {
9423 //printf("no free regs for store %x\n",start+j*4);
9424 break;
57871462 9425 }
57871462 9426 }
9427 if(regs[j].regmap[HOST_CCREG]==CCREG) {
9428 int k=i;
9429 //printf("Extend CC, %x -> %x\n",start+k*4,start+j*4);
9430 while(k<j) {
9431 regs[k].regmap_entry[HOST_CCREG]=CCREG;
9432 regs[k].regmap[HOST_CCREG]=CCREG;
9433 regmap_pre[k+1][HOST_CCREG]=CCREG;
9434 regs[k+1].wasdirty|=1<<HOST_CCREG;
9435 regs[k].dirty|=1<<HOST_CCREG;
9436 regs[k].wasconst&=~(1<<HOST_CCREG);
9437 regs[k].isconst&=~(1<<HOST_CCREG);
9438 k++;
9439 }
9440 regs[j].regmap_entry[HOST_CCREG]=CCREG;
9441 }
9442 // Work backwards from the branch target
9443 if(j>i&&f_regmap[HOST_CCREG]==CCREG)
9444 {
9445 //printf("Extend backwards\n");
9446 int k;
9447 k=i;
9448 while(regs[k-1].regmap[HOST_CCREG]==-1) {
e1190b87 9449 if(count_free_regs(regs[k-1].regmap)<=minimum_free_regs[k-1]) {
9450 //printf("no free regs for store %x\n",start+(k-1)*4);
9451 break;
57871462 9452 }
57871462 9453 k--;
9454 }
9455 if(regs[k-1].regmap[HOST_CCREG]==CCREG) {
9456 //printf("Extend CC, %x ->\n",start+k*4);
9457 while(k<=i) {
9458 regs[k].regmap_entry[HOST_CCREG]=CCREG;
9459 regs[k].regmap[HOST_CCREG]=CCREG;
9460 regmap_pre[k+1][HOST_CCREG]=CCREG;
9461 regs[k+1].wasdirty|=1<<HOST_CCREG;
9462 regs[k].dirty|=1<<HOST_CCREG;
9463 regs[k].wasconst&=~(1<<HOST_CCREG);
9464 regs[k].isconst&=~(1<<HOST_CCREG);
9465 k++;
9466 }
9467 }
9468 else {
9469 //printf("Fail Extend CC, %x ->\n",start+k*4);
9470 }
9471 }
9472 }
9473 if(itype[i]!=STORE&&itype[i]!=STORELR&&itype[i]!=C1LS&&itype[i]!=SHIFT&&
9474 itype[i]!=NOP&&itype[i]!=MOV&&itype[i]!=ALU&&itype[i]!=SHIFTIMM&&
9475 itype[i]!=IMM16&&itype[i]!=LOAD&&itype[i]!=COP1&&itype[i]!=FLOAT&&
e1190b87 9476 itype[i]!=FCONV&&itype[i]!=FCOMP)
57871462 9477 {
9478 memcpy(f_regmap,regs[i].regmap,sizeof(f_regmap));
9479 }
9480 }
9481 }
9482
d61de97e 9483 // Cache memory offset or tlb map pointer if a register is available
9484 #ifndef HOST_IMM_ADDR32
9485 #ifndef RAM_OFFSET
9486 if(using_tlb)
9487 #endif
9488 {
9489 int earliest_available[HOST_REGS];
9490 int loop_start[HOST_REGS];
9491 int score[HOST_REGS];
9492 int end[HOST_REGS];
9493 int reg=using_tlb?MMREG:ROREG;
9494
9495 // Init
9496 for(hr=0;hr<HOST_REGS;hr++) {
9497 score[hr]=0;earliest_available[hr]=0;
9498 loop_start[hr]=MAXBLOCK;
9499 }
9500 for(i=0;i<slen-1;i++)
9501 {
9502 // Can't do anything if no registers are available
9503 if(count_free_regs(regs[i].regmap)<=minimum_free_regs[i]) {
9504 for(hr=0;hr<HOST_REGS;hr++) {
9505 score[hr]=0;earliest_available[hr]=i+1;
9506 loop_start[hr]=MAXBLOCK;
9507 }
9508 }
9509 if(itype[i]==UJUMP||itype[i]==RJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP) {
9510 if(!ooo[i]) {
9511 if(count_free_regs(branch_regs[i].regmap)<=minimum_free_regs[i+1]) {
9512 for(hr=0;hr<HOST_REGS;hr++) {
9513 score[hr]=0;earliest_available[hr]=i+1;
9514 loop_start[hr]=MAXBLOCK;
9515 }
9516 }
198df76f 9517 }else{
9518 if(count_free_regs(regs[i].regmap)<=minimum_free_regs[i+1]) {
9519 for(hr=0;hr<HOST_REGS;hr++) {
9520 score[hr]=0;earliest_available[hr]=i+1;
9521 loop_start[hr]=MAXBLOCK;
9522 }
9523 }
d61de97e 9524 }
9525 }
9526 // Mark unavailable registers
9527 for(hr=0;hr<HOST_REGS;hr++) {
9528 if(regs[i].regmap[hr]>=0) {
9529 score[hr]=0;earliest_available[hr]=i+1;
9530 loop_start[hr]=MAXBLOCK;
9531 }
9532 if(itype[i]==UJUMP||itype[i]==RJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP) {
9533 if(branch_regs[i].regmap[hr]>=0) {
9534 score[hr]=0;earliest_available[hr]=i+2;
9535 loop_start[hr]=MAXBLOCK;
9536 }
9537 }
9538 }
9539 // No register allocations after unconditional jumps
9540 if(itype[i]==UJUMP||itype[i]==RJUMP||(source[i]>>16)==0x1000)
9541 {
9542 for(hr=0;hr<HOST_REGS;hr++) {
9543 score[hr]=0;earliest_available[hr]=i+2;
9544 loop_start[hr]=MAXBLOCK;
9545 }
9546 i++; // Skip delay slot too
9547 //printf("skip delay slot: %x\n",start+i*4);
9548 }
9549 else
9550 // Possible match
9551 if(itype[i]==LOAD||itype[i]==LOADLR||
9552 itype[i]==STORE||itype[i]==STORELR||itype[i]==C1LS) {
9553 for(hr=0;hr<HOST_REGS;hr++) {
9554 if(hr!=EXCLUDE_REG) {
9555 end[hr]=i-1;
9556 for(j=i;j<slen-1;j++) {
9557 if(regs[j].regmap[hr]>=0) break;
9558 if(itype[j]==UJUMP||itype[j]==RJUMP||itype[j]==CJUMP||itype[j]==SJUMP||itype[j]==FJUMP) {
9559 if(branch_regs[j].regmap[hr]>=0) break;
9560 if(ooo[j]) {
9561 if(count_free_regs(regs[j].regmap)<=minimum_free_regs[j+1]) break;
9562 }else{
9563 if(count_free_regs(branch_regs[j].regmap)<=minimum_free_regs[j+1]) break;
9564 }
9565 }
9566 else if(count_free_regs(regs[j].regmap)<=minimum_free_regs[j]) break;
9567 if(itype[j]==UJUMP||itype[j]==RJUMP||itype[j]==CJUMP||itype[j]==SJUMP||itype[j]==FJUMP) {
9568 int t=(ba[j]-start)>>2;
9569 if(t<j&&t>=earliest_available[hr]) {
198df76f 9570 if(t==1||(t>1&&itype[t-2]!=UJUMP&&itype[t-2]!=RJUMP)||(t>1&&rt1[t-2]!=31)) { // call/ret assumes no registers allocated
9571 // Score a point for hoisting loop invariant
9572 if(t<loop_start[hr]) loop_start[hr]=t;
9573 //printf("set loop_start: i=%x j=%x (%x)\n",start+i*4,start+j*4,start+t*4);
9574 score[hr]++;
9575 end[hr]=j;
9576 }
d61de97e 9577 }
9578 else if(t<j) {
9579 if(regs[t].regmap[hr]==reg) {
9580 // Score a point if the branch target matches this register
9581 score[hr]++;
9582 end[hr]=j;
9583 }
9584 }
9585 if(itype[j+1]==LOAD||itype[j+1]==LOADLR||
9586 itype[j+1]==STORE||itype[j+1]==STORELR||itype[j+1]==C1LS) {
9587 score[hr]++;
9588 end[hr]=j;
9589 }
9590 }
9591 if(itype[j]==UJUMP||itype[j]==RJUMP||(source[j]>>16)==0x1000)
9592 {
9593 // Stop on unconditional branch
9594 break;
9595 }
9596 else
9597 if(itype[j]==LOAD||itype[j]==LOADLR||
9598 itype[j]==STORE||itype[j]==STORELR||itype[j]==C1LS) {
9599 score[hr]++;
9600 end[hr]=j;
9601 }
9602 }
9603 }
9604 }
9605 // Find highest score and allocate that register
9606 int maxscore=0;
9607 for(hr=0;hr<HOST_REGS;hr++) {
9608 if(hr!=EXCLUDE_REG) {
9609 if(score[hr]>score[maxscore]) {
9610 maxscore=hr;
9611 //printf("highest score: %d %d (%x->%x)\n",score[hr],hr,start+i*4,start+end[hr]*4);
9612 }
9613 }
9614 }
9615 if(score[maxscore]>1)
9616 {
9617 if(i<loop_start[maxscore]) loop_start[maxscore]=i;
9618 for(j=loop_start[maxscore];j<slen&&j<=end[maxscore];j++) {
9619 //if(regs[j].regmap[maxscore]>=0) {printf("oops: %x %x was %d=%d\n",loop_start[maxscore]*4+start,j*4+start,maxscore,regs[j].regmap[maxscore]);}
9620 assert(regs[j].regmap[maxscore]<0);
9621 if(j>loop_start[maxscore]) regs[j].regmap_entry[maxscore]=reg;
9622 regs[j].regmap[maxscore]=reg;
9623 regs[j].dirty&=~(1<<maxscore);
9624 regs[j].wasconst&=~(1<<maxscore);
9625 regs[j].isconst&=~(1<<maxscore);
9626 if(itype[j]==UJUMP||itype[j]==RJUMP||itype[j]==CJUMP||itype[j]==SJUMP||itype[j]==FJUMP) {
9627 branch_regs[j].regmap[maxscore]=reg;
9628 branch_regs[j].wasdirty&=~(1<<maxscore);
9629 branch_regs[j].dirty&=~(1<<maxscore);
9630 branch_regs[j].wasconst&=~(1<<maxscore);
9631 branch_regs[j].isconst&=~(1<<maxscore);
9632 if(itype[j]!=RJUMP&&itype[j]!=UJUMP&&(source[j]>>16)!=0x1000) {
9633 regmap_pre[j+2][maxscore]=reg;
9634 regs[j+2].wasdirty&=~(1<<maxscore);
9635 }
9636 // loop optimization (loop_preload)
9637 int t=(ba[j]-start)>>2;
198df76f 9638 if(t==loop_start[maxscore]) {
9639 if(t==1||(t>1&&itype[t-2]!=UJUMP&&itype[t-2]!=RJUMP)||(t>1&&rt1[t-2]!=31)) // call/ret assumes no registers allocated
9640 regs[t].regmap_entry[maxscore]=reg;
9641 }
d61de97e 9642 }
9643 else
9644 {
9645 if(j<1||(itype[j-1]!=RJUMP&&itype[j-1]!=UJUMP&&itype[j-1]!=CJUMP&&itype[j-1]!=SJUMP&&itype[j-1]!=FJUMP)) {
9646 regmap_pre[j+1][maxscore]=reg;
9647 regs[j+1].wasdirty&=~(1<<maxscore);
9648 }
9649 }
9650 }
9651 i=j-1;
9652 if(itype[j-1]==RJUMP||itype[j-1]==UJUMP||itype[j-1]==CJUMP||itype[j-1]==SJUMP||itype[j-1]==FJUMP) i++; // skip delay slot
9653 for(hr=0;hr<HOST_REGS;hr++) {
9654 score[hr]=0;earliest_available[hr]=i+i;
9655 loop_start[hr]=MAXBLOCK;
9656 }
9657 }
9658 }
9659 }
9660 }
9661 #endif
9662
57871462 9663 // This allocates registers (if possible) one instruction prior
9664 // to use, which can avoid a load-use penalty on certain CPUs.
9665 for(i=0;i<slen-1;i++)
9666 {
9667 if(!i||(itype[i-1]!=UJUMP&&itype[i-1]!=CJUMP&&itype[i-1]!=SJUMP&&itype[i-1]!=RJUMP&&itype[i-1]!=FJUMP))
9668 {
9669 if(!bt[i+1])
9670 {
b9b61529 9671 if(itype[i]==ALU||itype[i]==MOV||itype[i]==LOAD||itype[i]==SHIFTIMM||itype[i]==IMM16
9672 ||((itype[i]==COP1||itype[i]==COP2)&&opcode2[i]<3))
57871462 9673 {
9674 if(rs1[i+1]) {
9675 if((hr=get_reg(regs[i+1].regmap,rs1[i+1]))>=0)
9676 {
9677 if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
9678 {
9679 regs[i].regmap[hr]=regs[i+1].regmap[hr];
9680 regmap_pre[i+1][hr]=regs[i+1].regmap[hr];
9681 regs[i+1].regmap_entry[hr]=regs[i+1].regmap[hr];
9682 regs[i].isconst&=~(1<<hr);
9683 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
9684 constmap[i][hr]=constmap[i+1][hr];
9685 regs[i+1].wasdirty&=~(1<<hr);
9686 regs[i].dirty&=~(1<<hr);
9687 }
9688 }
9689 }
9690 if(rs2[i+1]) {
9691 if((hr=get_reg(regs[i+1].regmap,rs2[i+1]))>=0)
9692 {
9693 if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
9694 {
9695 regs[i].regmap[hr]=regs[i+1].regmap[hr];
9696 regmap_pre[i+1][hr]=regs[i+1].regmap[hr];
9697 regs[i+1].regmap_entry[hr]=regs[i+1].regmap[hr];
9698 regs[i].isconst&=~(1<<hr);
9699 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
9700 constmap[i][hr]=constmap[i+1][hr];
9701 regs[i+1].wasdirty&=~(1<<hr);
9702 regs[i].dirty&=~(1<<hr);
9703 }
9704 }
9705 }
198df76f 9706 // Preload target address for load instruction (non-constant)
57871462 9707 if(itype[i+1]==LOAD&&rs1[i+1]&&get_reg(regs[i+1].regmap,rs1[i+1])<0) {
9708 if((hr=get_reg(regs[i+1].regmap,rt1[i+1]))>=0)
9709 {
9710 if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
9711 {
9712 regs[i].regmap[hr]=rs1[i+1];
9713 regmap_pre[i+1][hr]=rs1[i+1];
9714 regs[i+1].regmap_entry[hr]=rs1[i+1];
9715 regs[i].isconst&=~(1<<hr);
9716 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
9717 constmap[i][hr]=constmap[i+1][hr];
9718 regs[i+1].wasdirty&=~(1<<hr);
9719 regs[i].dirty&=~(1<<hr);
9720 }
9721 }
9722 }
198df76f 9723 // Load source into target register
57871462 9724 if(lt1[i+1]&&get_reg(regs[i+1].regmap,rs1[i+1])<0) {
9725 if((hr=get_reg(regs[i+1].regmap,rt1[i+1]))>=0)
9726 {
9727 if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
9728 {
9729 regs[i].regmap[hr]=rs1[i+1];
9730 regmap_pre[i+1][hr]=rs1[i+1];
9731 regs[i+1].regmap_entry[hr]=rs1[i+1];
9732 regs[i].isconst&=~(1<<hr);
9733 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
9734 constmap[i][hr]=constmap[i+1][hr];
9735 regs[i+1].wasdirty&=~(1<<hr);
9736 regs[i].dirty&=~(1<<hr);
9737 }
9738 }
9739 }
198df76f 9740 // Preload map address
57871462 9741 #ifndef HOST_IMM_ADDR32
b9b61529 9742 if(itype[i+1]==LOAD||itype[i+1]==LOADLR||itype[i+1]==STORE||itype[i+1]==STORELR||itype[i+1]==C1LS||itype[i+1]==C2LS) {
57871462 9743 hr=get_reg(regs[i+1].regmap,TLREG);
9744 if(hr>=0) {
9745 int sr=get_reg(regs[i+1].regmap,rs1[i+1]);
9746 if(sr>=0&&((regs[i+1].wasconst>>sr)&1)) {
9747 int nr;
9748 if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
9749 {
9750 regs[i].regmap[hr]=MGEN1+((i+1)&1);
9751 regmap_pre[i+1][hr]=MGEN1+((i+1)&1);
9752 regs[i+1].regmap_entry[hr]=MGEN1+((i+1)&1);
9753 regs[i].isconst&=~(1<<hr);
9754 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
9755 constmap[i][hr]=constmap[i+1][hr];
9756 regs[i+1].wasdirty&=~(1<<hr);
9757 regs[i].dirty&=~(1<<hr);
9758 }
9759 else if((nr=get_reg2(regs[i].regmap,regs[i+1].regmap,-1))>=0)
9760 {
9761 // move it to another register
9762 regs[i+1].regmap[hr]=-1;
9763 regmap_pre[i+2][hr]=-1;
9764 regs[i+1].regmap[nr]=TLREG;
9765 regmap_pre[i+2][nr]=TLREG;
9766 regs[i].regmap[nr]=MGEN1+((i+1)&1);
9767 regmap_pre[i+1][nr]=MGEN1+((i+1)&1);
9768 regs[i+1].regmap_entry[nr]=MGEN1+((i+1)&1);
9769 regs[i].isconst&=~(1<<nr);
9770 regs[i+1].isconst&=~(1<<nr);
9771 regs[i].dirty&=~(1<<nr);
9772 regs[i+1].wasdirty&=~(1<<nr);
9773 regs[i+1].dirty&=~(1<<nr);
9774 regs[i+2].wasdirty&=~(1<<nr);
9775 }
9776 }
9777 }
9778 }
9779 #endif
198df76f 9780 // Address for store instruction (non-constant)
b9b61529 9781 if(itype[i+1]==STORE||itype[i+1]==STORELR
9782 ||(opcode[i+1]&0x3b)==0x39||(opcode[i+1]&0x3b)==0x3a) { // SB/SH/SW/SD/SWC1/SDC1/SWC2/SDC2
57871462 9783 if(get_reg(regs[i+1].regmap,rs1[i+1])<0) {
9784 hr=get_reg2(regs[i].regmap,regs[i+1].regmap,-1);
9785 if(hr<0) hr=get_reg(regs[i+1].regmap,-1);
9786 else {regs[i+1].regmap[hr]=AGEN1+((i+1)&1);regs[i+1].isconst&=~(1<<hr);}
9787 assert(hr>=0);
9788 if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
9789 {
9790 regs[i].regmap[hr]=rs1[i+1];
9791 regmap_pre[i+1][hr]=rs1[i+1];
9792 regs[i+1].regmap_entry[hr]=rs1[i+1];
9793 regs[i].isconst&=~(1<<hr);
9794 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
9795 constmap[i][hr]=constmap[i+1][hr];
9796 regs[i+1].wasdirty&=~(1<<hr);
9797 regs[i].dirty&=~(1<<hr);
9798 }
9799 }
9800 }
b9b61529 9801 if(itype[i+1]==LOADLR||(opcode[i+1]&0x3b)==0x31||(opcode[i+1]&0x3b)==0x32) { // LWC1/LDC1, LWC2/LDC2
57871462 9802 if(get_reg(regs[i+1].regmap,rs1[i+1])<0) {
9803 int nr;
9804 hr=get_reg(regs[i+1].regmap,FTEMP);
9805 assert(hr>=0);
9806 if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
9807 {
9808 regs[i].regmap[hr]=rs1[i+1];
9809 regmap_pre[i+1][hr]=rs1[i+1];
9810 regs[i+1].regmap_entry[hr]=rs1[i+1];
9811 regs[i].isconst&=~(1<<hr);
9812 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
9813 constmap[i][hr]=constmap[i+1][hr];
9814 regs[i+1].wasdirty&=~(1<<hr);
9815 regs[i].dirty&=~(1<<hr);
9816 }
9817 else if((nr=get_reg2(regs[i].regmap,regs[i+1].regmap,-1))>=0)
9818 {
9819 // move it to another register
9820 regs[i+1].regmap[hr]=-1;
9821 regmap_pre[i+2][hr]=-1;
9822 regs[i+1].regmap[nr]=FTEMP;
9823 regmap_pre[i+2][nr]=FTEMP;
9824 regs[i].regmap[nr]=rs1[i+1];
9825 regmap_pre[i+1][nr]=rs1[i+1];
9826 regs[i+1].regmap_entry[nr]=rs1[i+1];
9827 regs[i].isconst&=~(1<<nr);
9828 regs[i+1].isconst&=~(1<<nr);
9829 regs[i].dirty&=~(1<<nr);
9830 regs[i+1].wasdirty&=~(1<<nr);
9831 regs[i+1].dirty&=~(1<<nr);
9832 regs[i+2].wasdirty&=~(1<<nr);
9833 }
9834 }
9835 }
b9b61529 9836 if(itype[i+1]==LOAD||itype[i+1]==LOADLR||itype[i+1]==STORE||itype[i+1]==STORELR/*||itype[i+1]==C1LS||||itype[i+1]==C2LS*/) {
57871462 9837 if(itype[i+1]==LOAD)
9838 hr=get_reg(regs[i+1].regmap,rt1[i+1]);
b9b61529 9839 if(itype[i+1]==LOADLR||(opcode[i+1]&0x3b)==0x31||(opcode[i+1]&0x3b)==0x32) // LWC1/LDC1, LWC2/LDC2
57871462 9840 hr=get_reg(regs[i+1].regmap,FTEMP);
b9b61529 9841 if(itype[i+1]==STORE||itype[i+1]==STORELR||(opcode[i+1]&0x3b)==0x39||(opcode[i+1]&0x3b)==0x3a) { // SWC1/SDC1/SWC2/SDC2
57871462 9842 hr=get_reg(regs[i+1].regmap,AGEN1+((i+1)&1));
9843 if(hr<0) hr=get_reg(regs[i+1].regmap,-1);
9844 }
9845 if(hr>=0&&regs[i].regmap[hr]<0) {
9846 int rs=get_reg(regs[i+1].regmap,rs1[i+1]);
9847 if(rs>=0&&((regs[i+1].wasconst>>rs)&1)) {
9848 regs[i].regmap[hr]=AGEN1+((i+1)&1);
9849 regmap_pre[i+1][hr]=AGEN1+((i+1)&1);
9850 regs[i+1].regmap_entry[hr]=AGEN1+((i+1)&1);
9851 regs[i].isconst&=~(1<<hr);
9852 regs[i+1].wasdirty&=~(1<<hr);
9853 regs[i].dirty&=~(1<<hr);
9854 }
9855 }
9856 }
9857 }
9858 }
9859 }
9860 }
9861
9862 /* Pass 6 - Optimize clean/dirty state */
9863 clean_registers(0,slen-1,1);
9864
9865 /* Pass 7 - Identify 32-bit registers */
04fd948a 9866 for (i=slen-1;i>=0;i--)
9867 {
9868 if(itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
9869 {
9870 // Conditional branch
9871 if((source[i]>>16)!=0x1000&&i<slen-2) {
9872 // Mark this address as a branch target since it may be called
9873 // upon return from interrupt
9874 bt[i+2]=1;
9875 }
9876 }
9877 }
57871462 9878
9879 if(itype[slen-1]==SPAN) {
9880 bt[slen-1]=1; // Mark as a branch target so instruction can restart after exception
9881 }
4600ba03 9882
9883#ifdef DISASM
57871462 9884 /* Debug/disassembly */
57871462 9885 for(i=0;i<slen;i++)
9886 {
9887 printf("U:");
9888 int r;
9889 for(r=1;r<=CCREG;r++) {
9890 if((unneeded_reg[i]>>r)&1) {
9891 if(r==HIREG) printf(" HI");
9892 else if(r==LOREG) printf(" LO");
9893 else printf(" r%d",r);
9894 }
9895 }
57871462 9896 printf("\n");
9897 #if defined(__i386__) || defined(__x86_64__)
9898 printf("pre: eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",regmap_pre[i][0],regmap_pre[i][1],regmap_pre[i][2],regmap_pre[i][3],regmap_pre[i][5],regmap_pre[i][6],regmap_pre[i][7]);
9899 #endif
9900 #ifdef __arm__
9901 printf("pre: r0=%d r1=%d r2=%d r3=%d r4=%d r5=%d r6=%d r7=%d r8=%d r9=%d r10=%d r12=%d\n",regmap_pre[i][0],regmap_pre[i][1],regmap_pre[i][2],regmap_pre[i][3],regmap_pre[i][4],regmap_pre[i][5],regmap_pre[i][6],regmap_pre[i][7],regmap_pre[i][8],regmap_pre[i][9],regmap_pre[i][10],regmap_pre[i][12]);
9902 #endif
9903 printf("needs: ");
9904 if(needed_reg[i]&1) printf("eax ");
9905 if((needed_reg[i]>>1)&1) printf("ecx ");
9906 if((needed_reg[i]>>2)&1) printf("edx ");
9907 if((needed_reg[i]>>3)&1) printf("ebx ");
9908 if((needed_reg[i]>>5)&1) printf("ebp ");
9909 if((needed_reg[i]>>6)&1) printf("esi ");
9910 if((needed_reg[i]>>7)&1) printf("edi ");
9911 printf("r:");
9912 for(r=0;r<=CCREG;r++) {
9913 //if(((requires_32bit[i]>>r)&(~unneeded_reg[i]>>r))&1) {
9914 if((requires_32bit[i]>>r)&1) {
9915 if(r==CCREG) printf(" CC");
9916 else if(r==HIREG) printf(" HI");
9917 else if(r==LOREG) printf(" LO");
9918 else printf(" r%d",r);
9919 }
9920 }
9921 printf("\n");
9922 /*printf("pr:");
9923 for(r=0;r<=CCREG;r++) {
9924 //if(((requires_32bit[i]>>r)&(~unneeded_reg[i]>>r))&1) {
9925 if((pr32[i]>>r)&1) {
9926 if(r==CCREG) printf(" CC");
9927 else if(r==HIREG) printf(" HI");
9928 else if(r==LOREG) printf(" LO");
9929 else printf(" r%d",r);
9930 }
9931 }
9932 if(pr32[i]!=requires_32bit[i]) printf(" OOPS");
9933 printf("\n");*/
9934 #if defined(__i386__) || defined(__x86_64__)
9935 printf("entry: eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",regs[i].regmap_entry[0],regs[i].regmap_entry[1],regs[i].regmap_entry[2],regs[i].regmap_entry[3],regs[i].regmap_entry[5],regs[i].regmap_entry[6],regs[i].regmap_entry[7]);
9936 printf("dirty: ");
9937 if(regs[i].wasdirty&1) printf("eax ");
9938 if((regs[i].wasdirty>>1)&1) printf("ecx ");
9939 if((regs[i].wasdirty>>2)&1) printf("edx ");
9940 if((regs[i].wasdirty>>3)&1) printf("ebx ");
9941 if((regs[i].wasdirty>>5)&1) printf("ebp ");
9942 if((regs[i].wasdirty>>6)&1) printf("esi ");
9943 if((regs[i].wasdirty>>7)&1) printf("edi ");
9944 #endif
9945 #ifdef __arm__
9946 printf("entry: r0=%d r1=%d r2=%d r3=%d r4=%d r5=%d r6=%d r7=%d r8=%d r9=%d r10=%d r12=%d\n",regs[i].regmap_entry[0],regs[i].regmap_entry[1],regs[i].regmap_entry[2],regs[i].regmap_entry[3],regs[i].regmap_entry[4],regs[i].regmap_entry[5],regs[i].regmap_entry[6],regs[i].regmap_entry[7],regs[i].regmap_entry[8],regs[i].regmap_entry[9],regs[i].regmap_entry[10],regs[i].regmap_entry[12]);
9947 printf("dirty: ");
9948 if(regs[i].wasdirty&1) printf("r0 ");
9949 if((regs[i].wasdirty>>1)&1) printf("r1 ");
9950 if((regs[i].wasdirty>>2)&1) printf("r2 ");
9951 if((regs[i].wasdirty>>3)&1) printf("r3 ");
9952 if((regs[i].wasdirty>>4)&1) printf("r4 ");
9953 if((regs[i].wasdirty>>5)&1) printf("r5 ");
9954 if((regs[i].wasdirty>>6)&1) printf("r6 ");
9955 if((regs[i].wasdirty>>7)&1) printf("r7 ");
9956 if((regs[i].wasdirty>>8)&1) printf("r8 ");
9957 if((regs[i].wasdirty>>9)&1) printf("r9 ");
9958 if((regs[i].wasdirty>>10)&1) printf("r10 ");
9959 if((regs[i].wasdirty>>12)&1) printf("r12 ");
9960 #endif
9961 printf("\n");
9962 disassemble_inst(i);
9963 //printf ("ccadj[%d] = %d\n",i,ccadj[i]);
9964 #if defined(__i386__) || defined(__x86_64__)
9965 printf("eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d dirty: ",regs[i].regmap[0],regs[i].regmap[1],regs[i].regmap[2],regs[i].regmap[3],regs[i].regmap[5],regs[i].regmap[6],regs[i].regmap[7]);
9966 if(regs[i].dirty&1) printf("eax ");
9967 if((regs[i].dirty>>1)&1) printf("ecx ");
9968 if((regs[i].dirty>>2)&1) printf("edx ");
9969 if((regs[i].dirty>>3)&1) printf("ebx ");
9970 if((regs[i].dirty>>5)&1) printf("ebp ");
9971 if((regs[i].dirty>>6)&1) printf("esi ");
9972 if((regs[i].dirty>>7)&1) printf("edi ");
9973 #endif
9974 #ifdef __arm__
9975 printf("r0=%d r1=%d r2=%d r3=%d r4=%d r5=%d r6=%d r7=%d r8=%d r9=%d r10=%d r12=%d dirty: ",regs[i].regmap[0],regs[i].regmap[1],regs[i].regmap[2],regs[i].regmap[3],regs[i].regmap[4],regs[i].regmap[5],regs[i].regmap[6],regs[i].regmap[7],regs[i].regmap[8],regs[i].regmap[9],regs[i].regmap[10],regs[i].regmap[12]);
9976 if(regs[i].dirty&1) printf("r0 ");
9977 if((regs[i].dirty>>1)&1) printf("r1 ");
9978 if((regs[i].dirty>>2)&1) printf("r2 ");
9979 if((regs[i].dirty>>3)&1) printf("r3 ");
9980 if((regs[i].dirty>>4)&1) printf("r4 ");
9981 if((regs[i].dirty>>5)&1) printf("r5 ");
9982 if((regs[i].dirty>>6)&1) printf("r6 ");
9983 if((regs[i].dirty>>7)&1) printf("r7 ");
9984 if((regs[i].dirty>>8)&1) printf("r8 ");
9985 if((regs[i].dirty>>9)&1) printf("r9 ");
9986 if((regs[i].dirty>>10)&1) printf("r10 ");
9987 if((regs[i].dirty>>12)&1) printf("r12 ");
9988 #endif
9989 printf("\n");
9990 if(regs[i].isconst) {
9991 printf("constants: ");
9992 #if defined(__i386__) || defined(__x86_64__)
9993 if(regs[i].isconst&1) printf("eax=%x ",(int)constmap[i][0]);
9994 if((regs[i].isconst>>1)&1) printf("ecx=%x ",(int)constmap[i][1]);
9995 if((regs[i].isconst>>2)&1) printf("edx=%x ",(int)constmap[i][2]);
9996 if((regs[i].isconst>>3)&1) printf("ebx=%x ",(int)constmap[i][3]);
9997 if((regs[i].isconst>>5)&1) printf("ebp=%x ",(int)constmap[i][5]);
9998 if((regs[i].isconst>>6)&1) printf("esi=%x ",(int)constmap[i][6]);
9999 if((regs[i].isconst>>7)&1) printf("edi=%x ",(int)constmap[i][7]);
10000 #endif
10001 #ifdef __arm__
10002 if(regs[i].isconst&1) printf("r0=%x ",(int)constmap[i][0]);
10003 if((regs[i].isconst>>1)&1) printf("r1=%x ",(int)constmap[i][1]);
10004 if((regs[i].isconst>>2)&1) printf("r2=%x ",(int)constmap[i][2]);
10005 if((regs[i].isconst>>3)&1) printf("r3=%x ",(int)constmap[i][3]);
10006 if((regs[i].isconst>>4)&1) printf("r4=%x ",(int)constmap[i][4]);
10007 if((regs[i].isconst>>5)&1) printf("r5=%x ",(int)constmap[i][5]);
10008 if((regs[i].isconst>>6)&1) printf("r6=%x ",(int)constmap[i][6]);
10009 if((regs[i].isconst>>7)&1) printf("r7=%x ",(int)constmap[i][7]);
10010 if((regs[i].isconst>>8)&1) printf("r8=%x ",(int)constmap[i][8]);
10011 if((regs[i].isconst>>9)&1) printf("r9=%x ",(int)constmap[i][9]);
10012 if((regs[i].isconst>>10)&1) printf("r10=%x ",(int)constmap[i][10]);
10013 if((regs[i].isconst>>12)&1) printf("r12=%x ",(int)constmap[i][12]);
10014 #endif
10015 printf("\n");
10016 }
57871462 10017 /*printf(" p32:");
10018 for(r=0;r<=CCREG;r++) {
10019 if((p32[i]>>r)&1) {
10020 if(r==CCREG) printf(" CC");
10021 else if(r==HIREG) printf(" HI");
10022 else if(r==LOREG) printf(" LO");
10023 else printf(" r%d",r);
10024 }
10025 }
10026 if(p32[i]!=regs[i].is32) printf(" NO MATCH\n");
10027 else printf("\n");*/
10028 if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP) {
10029 #if defined(__i386__) || defined(__x86_64__)
10030 printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d dirty: ",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
10031 if(branch_regs[i].dirty&1) printf("eax ");
10032 if((branch_regs[i].dirty>>1)&1) printf("ecx ");
10033 if((branch_regs[i].dirty>>2)&1) printf("edx ");
10034 if((branch_regs[i].dirty>>3)&1) printf("ebx ");
10035 if((branch_regs[i].dirty>>5)&1) printf("ebp ");
10036 if((branch_regs[i].dirty>>6)&1) printf("esi ");
10037 if((branch_regs[i].dirty>>7)&1) printf("edi ");
10038 #endif
10039 #ifdef __arm__
10040 printf("branch(%d): r0=%d r1=%d r2=%d r3=%d r4=%d r5=%d r6=%d r7=%d r8=%d r9=%d r10=%d r12=%d dirty: ",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[4],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7],branch_regs[i].regmap[8],branch_regs[i].regmap[9],branch_regs[i].regmap[10],branch_regs[i].regmap[12]);
10041 if(branch_regs[i].dirty&1) printf("r0 ");
10042 if((branch_regs[i].dirty>>1)&1) printf("r1 ");
10043 if((branch_regs[i].dirty>>2)&1) printf("r2 ");
10044 if((branch_regs[i].dirty>>3)&1) printf("r3 ");
10045 if((branch_regs[i].dirty>>4)&1) printf("r4 ");
10046 if((branch_regs[i].dirty>>5)&1) printf("r5 ");
10047 if((branch_regs[i].dirty>>6)&1) printf("r6 ");
10048 if((branch_regs[i].dirty>>7)&1) printf("r7 ");
10049 if((branch_regs[i].dirty>>8)&1) printf("r8 ");
10050 if((branch_regs[i].dirty>>9)&1) printf("r9 ");
10051 if((branch_regs[i].dirty>>10)&1) printf("r10 ");
10052 if((branch_regs[i].dirty>>12)&1) printf("r12 ");
10053 #endif
57871462 10054 }
10055 }
4600ba03 10056#endif // DISASM
57871462 10057
10058 /* Pass 8 - Assembly */
10059 linkcount=0;stubcount=0;
10060 ds=0;is_delayslot=0;
10061 cop1_usable=0;
10062 uint64_t is32_pre=0;
10063 u_int dirty_pre=0;
10064 u_int beginning=(u_int)out;
10065 if((u_int)addr&1) {
10066 ds=1;
10067 pagespan_ds();
10068 }
9ad4d757 10069 u_int instr_addr0_override=0;
10070
9ad4d757 10071 if (start == 0x80030000) {
10072 // nasty hack for fastbios thing
96186eba 10073 // override block entry to this code
9ad4d757 10074 instr_addr0_override=(u_int)out;
10075 emit_movimm(start,0);
96186eba 10076 // abuse io address var as a flag that we
10077 // have already returned here once
10078 emit_readword((int)&address,1);
9ad4d757 10079 emit_writeword(0,(int)&pcaddr);
96186eba 10080 emit_writeword(0,(int)&address);
9ad4d757 10081 emit_cmp(0,1);
10082 emit_jne((int)new_dyna_leave);
10083 }
57871462 10084 for(i=0;i<slen;i++)
10085 {
10086 //if(ds) printf("ds: ");
4600ba03 10087 disassemble_inst(i);
57871462 10088 if(ds) {
10089 ds=0; // Skip delay slot
10090 if(bt[i]) assem_debug("OOPS - branch into delay slot\n");
10091 instr_addr[i]=0;
10092 } else {
ffb0b9e0 10093 speculate_register_values(i);
57871462 10094 #ifndef DESTRUCTIVE_WRITEBACK
10095 if(i<2||(itype[i-2]!=UJUMP&&itype[i-2]!=RJUMP&&(source[i-2]>>16)!=0x1000))
10096 {
57871462 10097 wb_valid(regmap_pre[i],regs[i].regmap_entry,dirty_pre,regs[i].wasdirty,is32_pre,
10098 unneeded_reg[i],unneeded_reg_upper[i]);
10099 }
f776eb14 10100 if((itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)&&!likely[i]) {
10101 is32_pre=branch_regs[i].is32;
10102 dirty_pre=branch_regs[i].dirty;
10103 }else{
10104 is32_pre=regs[i].is32;
10105 dirty_pre=regs[i].dirty;
10106 }
57871462 10107 #endif
10108 // write back
10109 if(i<2||(itype[i-2]!=UJUMP&&itype[i-2]!=RJUMP&&(source[i-2]>>16)!=0x1000))
10110 {
10111 wb_invalidate(regmap_pre[i],regs[i].regmap_entry,regs[i].wasdirty,regs[i].was32,
10112 unneeded_reg[i],unneeded_reg_upper[i]);
10113 loop_preload(regmap_pre[i],regs[i].regmap_entry);
10114 }
10115 // branch target entry point
10116 instr_addr[i]=(u_int)out;
10117 assem_debug("<->\n");
10118 // load regs
10119 if(regs[i].regmap_entry[HOST_CCREG]==CCREG&&regs[i].regmap[HOST_CCREG]!=CCREG)
10120 wb_register(CCREG,regs[i].regmap_entry,regs[i].wasdirty,regs[i].was32);
10121 load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,rs1[i],rs2[i]);
10122 address_generation(i,&regs[i],regs[i].regmap_entry);
10123 load_consts(regmap_pre[i],regs[i].regmap,regs[i].was32,i);
10124 if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
10125 {
10126 // Load the delay slot registers if necessary
4ef8f67d 10127 if(rs1[i+1]!=rs1[i]&&rs1[i+1]!=rs2[i]&&(rs1[i+1]!=rt1[i]||rt1[i]==0))
57871462 10128 load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,rs1[i+1],rs1[i+1]);
4ef8f67d 10129 if(rs2[i+1]!=rs1[i+1]&&rs2[i+1]!=rs1[i]&&rs2[i+1]!=rs2[i]&&(rs2[i+1]!=rt1[i]||rt1[i]==0))
57871462 10130 load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,rs2[i+1],rs2[i+1]);
b9b61529 10131 if(itype[i+1]==STORE||itype[i+1]==STORELR||(opcode[i+1]&0x3b)==0x39||(opcode[i+1]&0x3b)==0x3a)
57871462 10132 load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,INVCP,INVCP);
10133 }
10134 else if(i+1<slen)
10135 {
10136 // Preload registers for following instruction
10137 if(rs1[i+1]!=rs1[i]&&rs1[i+1]!=rs2[i])
10138 if(rs1[i+1]!=rt1[i]&&rs1[i+1]!=rt2[i])
10139 load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,rs1[i+1],rs1[i+1]);
10140 if(rs2[i+1]!=rs1[i+1]&&rs2[i+1]!=rs1[i]&&rs2[i+1]!=rs2[i])
10141 if(rs2[i+1]!=rt1[i]&&rs2[i+1]!=rt2[i])
10142 load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,rs2[i+1],rs2[i+1]);
10143 }
10144 // TODO: if(is_ooo(i)) address_generation(i+1);
10145 if(itype[i]==CJUMP||itype[i]==FJUMP)
10146 load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,CCREG,CCREG);
b9b61529 10147 if(itype[i]==STORE||itype[i]==STORELR||(opcode[i]&0x3b)==0x39||(opcode[i]&0x3b)==0x3a)
57871462 10148 load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,INVCP,INVCP);
10149 if(bt[i]) cop1_usable=0;
10150 // assemble
10151 switch(itype[i]) {
10152 case ALU:
10153 alu_assemble(i,&regs[i]);break;
10154 case IMM16:
10155 imm16_assemble(i,&regs[i]);break;
10156 case SHIFT:
10157 shift_assemble(i,&regs[i]);break;
10158 case SHIFTIMM:
10159 shiftimm_assemble(i,&regs[i]);break;
10160 case LOAD:
10161 load_assemble(i,&regs[i]);break;
10162 case LOADLR:
10163 loadlr_assemble(i,&regs[i]);break;
10164 case STORE:
10165 store_assemble(i,&regs[i]);break;
10166 case STORELR:
10167 storelr_assemble(i,&regs[i]);break;
10168 case COP0:
10169 cop0_assemble(i,&regs[i]);break;
10170 case COP1:
10171 cop1_assemble(i,&regs[i]);break;
10172 case C1LS:
10173 c1ls_assemble(i,&regs[i]);break;
b9b61529 10174 case COP2:
10175 cop2_assemble(i,&regs[i]);break;
10176 case C2LS:
10177 c2ls_assemble(i,&regs[i]);break;
10178 case C2OP:
10179 c2op_assemble(i,&regs[i]);break;
57871462 10180 case FCONV:
10181 fconv_assemble(i,&regs[i]);break;
10182 case FLOAT:
10183 float_assemble(i,&regs[i]);break;
10184 case FCOMP:
10185 fcomp_assemble(i,&regs[i]);break;
10186 case MULTDIV:
10187 multdiv_assemble(i,&regs[i]);break;
10188 case MOV:
10189 mov_assemble(i,&regs[i]);break;
10190 case SYSCALL:
10191 syscall_assemble(i,&regs[i]);break;
7139f3c8 10192 case HLECALL:
10193 hlecall_assemble(i,&regs[i]);break;
1e973cb0 10194 case INTCALL:
10195 intcall_assemble(i,&regs[i]);break;
57871462 10196 case UJUMP:
10197 ujump_assemble(i,&regs[i]);ds=1;break;
10198 case RJUMP:
10199 rjump_assemble(i,&regs[i]);ds=1;break;
10200 case CJUMP:
10201 cjump_assemble(i,&regs[i]);ds=1;break;
10202 case SJUMP:
10203 sjump_assemble(i,&regs[i]);ds=1;break;
10204 case FJUMP:
10205 fjump_assemble(i,&regs[i]);ds=1;break;
10206 case SPAN:
10207 pagespan_assemble(i,&regs[i]);break;
10208 }
10209 if(itype[i]==UJUMP||itype[i]==RJUMP||(source[i]>>16)==0x1000)
10210 literal_pool(1024);
10211 else
10212 literal_pool_jumpover(256);
10213 }
10214 }
10215 //assert(itype[i-2]==UJUMP||itype[i-2]==RJUMP||(source[i-2]>>16)==0x1000);
10216 // If the block did not end with an unconditional branch,
10217 // add a jump to the next instruction.
10218 if(i>1) {
10219 if(itype[i-2]!=UJUMP&&itype[i-2]!=RJUMP&&(source[i-2]>>16)!=0x1000&&itype[i-1]!=SPAN) {
10220 assert(itype[i-1]!=UJUMP&&itype[i-1]!=CJUMP&&itype[i-1]!=SJUMP&&itype[i-1]!=RJUMP&&itype[i-1]!=FJUMP);
10221 assert(i==slen);
10222 if(itype[i-2]!=CJUMP&&itype[i-2]!=SJUMP&&itype[i-2]!=FJUMP) {
10223 store_regs_bt(regs[i-1].regmap,regs[i-1].is32,regs[i-1].dirty,start+i*4);
10224 if(regs[i-1].regmap[HOST_CCREG]!=CCREG)
10225 emit_loadreg(CCREG,HOST_CCREG);
2573466a 10226 emit_addimm(HOST_CCREG,CLOCK_ADJUST(ccadj[i-1]+1),HOST_CCREG);
57871462 10227 }
10228 else if(!likely[i-2])
10229 {
10230 store_regs_bt(branch_regs[i-2].regmap,branch_regs[i-2].is32,branch_regs[i-2].dirty,start+i*4);
10231 assert(branch_regs[i-2].regmap[HOST_CCREG]==CCREG);
10232 }
10233 else
10234 {
10235 store_regs_bt(regs[i-2].regmap,regs[i-2].is32,regs[i-2].dirty,start+i*4);
10236 assert(regs[i-2].regmap[HOST_CCREG]==CCREG);
10237 }
10238 add_to_linker((int)out,start+i*4,0);
10239 emit_jmp(0);
10240 }
10241 }
10242 else
10243 {
10244 assert(i>0);
10245 assert(itype[i-1]!=UJUMP&&itype[i-1]!=CJUMP&&itype[i-1]!=SJUMP&&itype[i-1]!=RJUMP&&itype[i-1]!=FJUMP);
10246 store_regs_bt(regs[i-1].regmap,regs[i-1].is32,regs[i-1].dirty,start+i*4);
10247 if(regs[i-1].regmap[HOST_CCREG]!=CCREG)
10248 emit_loadreg(CCREG,HOST_CCREG);
2573466a 10249 emit_addimm(HOST_CCREG,CLOCK_ADJUST(ccadj[i-1]+1),HOST_CCREG);
57871462 10250 add_to_linker((int)out,start+i*4,0);
10251 emit_jmp(0);
10252 }
10253
10254 // TODO: delay slot stubs?
10255 // Stubs
10256 for(i=0;i<stubcount;i++)
10257 {
10258 switch(stubs[i][0])
10259 {
10260 case LOADB_STUB:
10261 case LOADH_STUB:
10262 case LOADW_STUB:
10263 case LOADD_STUB:
10264 case LOADBU_STUB:
10265 case LOADHU_STUB:
10266 do_readstub(i);break;
10267 case STOREB_STUB:
10268 case STOREH_STUB:
10269 case STOREW_STUB:
10270 case STORED_STUB:
10271 do_writestub(i);break;
10272 case CC_STUB:
10273 do_ccstub(i);break;
10274 case INVCODE_STUB:
10275 do_invstub(i);break;
10276 case FP_STUB:
10277 do_cop1stub(i);break;
10278 case STORELR_STUB:
10279 do_unalignedwritestub(i);break;
10280 }
10281 }
10282
9ad4d757 10283 if (instr_addr0_override)
10284 instr_addr[0] = instr_addr0_override;
10285
57871462 10286 /* Pass 9 - Linker */
10287 for(i=0;i<linkcount;i++)
10288 {
10289 assem_debug("%8x -> %8x\n",link_addr[i][0],link_addr[i][1]);
10290 literal_pool(64);
10291 if(!link_addr[i][2])
10292 {
10293 void *stub=out;
10294 void *addr=check_addr(link_addr[i][1]);
10295 emit_extjump(link_addr[i][0],link_addr[i][1]);
10296 if(addr) {
10297 set_jump_target(link_addr[i][0],(int)addr);
10298 add_link(link_addr[i][1],stub);
10299 }
10300 else set_jump_target(link_addr[i][0],(int)stub);
10301 }
10302 else
10303 {
10304 // Internal branch
10305 int target=(link_addr[i][1]-start)>>2;
10306 assert(target>=0&&target<slen);
10307 assert(instr_addr[target]);
10308 //#ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
10309 //set_jump_target_fillslot(link_addr[i][0],instr_addr[target],link_addr[i][2]>>1);
10310 //#else
10311 set_jump_target(link_addr[i][0],instr_addr[target]);
10312 //#endif
10313 }
10314 }
10315 // External Branch Targets (jump_in)
10316 if(copy+slen*4>(void *)shadow+sizeof(shadow)) copy=shadow;
10317 for(i=0;i<slen;i++)
10318 {
10319 if(bt[i]||i==0)
10320 {
10321 if(instr_addr[i]) // TODO - delay slots (=null)
10322 {
10323 u_int vaddr=start+i*4;
94d23bb9 10324 u_int page=get_page(vaddr);
10325 u_int vpage=get_vpage(vaddr);
57871462 10326 literal_pool(256);
57871462 10327 {
10328 assem_debug("%8x (%d) <- %8x\n",instr_addr[i],i,start+i*4);
10329 assem_debug("jump_in: %x\n",start+i*4);
10330 ll_add(jump_dirty+vpage,vaddr,(void *)out);
10331 int entry_point=do_dirty_stub(i);
03f55e6b 10332 ll_add_flags(jump_in+page,vaddr,state_rflags,(void *)entry_point);
57871462 10333 // If there was an existing entry in the hash table,
10334 // replace it with the new address.
10335 // Don't add new entries. We'll insert the
10336 // ones that actually get used in check_addr().
10337 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
10338 if(ht_bin[0]==vaddr) {
10339 ht_bin[1]=entry_point;
10340 }
10341 if(ht_bin[2]==vaddr) {
10342 ht_bin[3]=entry_point;
10343 }
10344 }
57871462 10345 }
10346 }
10347 }
10348 // Write out the literal pool if necessary
10349 literal_pool(0);
10350 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
10351 // Align code
10352 if(((u_int)out)&7) emit_addnop(13);
10353 #endif
10354 assert((u_int)out-beginning<MAX_OUTPUT_BLOCK_SIZE);
10355 //printf("shadow buffer: %x-%x\n",(int)copy,(int)copy+slen*4);
10356 memcpy(copy,source,slen*4);
10357 copy+=slen*4;
10358
10359 #ifdef __arm__
10360 __clear_cache((void *)beginning,out);
10361 #endif
10362
10363 // If we're within 256K of the end of the buffer,
10364 // start over from the beginning. (Is 256K enough?)
bdeade46 10365 if((u_int)out>(u_int)BASE_ADDR+(1<<TARGET_SIZE_2)-MAX_OUTPUT_BLOCK_SIZE) out=(u_char *)BASE_ADDR;
57871462 10366
10367 // Trap writes to any of the pages we compiled
10368 for(i=start>>12;i<=(start+slen*4)>>12;i++) {
10369 invalid_code[i]=0;
57871462 10370 }
9be4ba64 10371 inv_code_start=inv_code_end=~0;
71e490c5 10372
b96d3df7 10373 // for PCSX we need to mark all mirrors too
b12c9fb8 10374 if(get_page(start)<(RAM_SIZE>>12))
10375 for(i=start>>12;i<=(start+slen*4)>>12;i++)
b96d3df7 10376 invalid_code[((u_int)0x00000000>>12)|(i&0x1ff)]=
10377 invalid_code[((u_int)0x80000000>>12)|(i&0x1ff)]=
10378 invalid_code[((u_int)0xa0000000>>12)|(i&0x1ff)]=0;
57871462 10379
10380 /* Pass 10 - Free memory by expiring oldest blocks */
10381
bdeade46 10382 int end=((((int)out-(int)BASE_ADDR)>>(TARGET_SIZE_2-16))+16384)&65535;
57871462 10383 while(expirep!=end)
10384 {
10385 int shift=TARGET_SIZE_2-3; // Divide into 8 blocks
bdeade46 10386 int base=(int)BASE_ADDR+((expirep>>13)<<shift); // Base address of this block
57871462 10387 inv_debug("EXP: Phase %d\n",expirep);
10388 switch((expirep>>11)&3)
10389 {
10390 case 0:
10391 // Clear jump_in and jump_dirty
10392 ll_remove_matching_addrs(jump_in+(expirep&2047),base,shift);
10393 ll_remove_matching_addrs(jump_dirty+(expirep&2047),base,shift);
10394 ll_remove_matching_addrs(jump_in+2048+(expirep&2047),base,shift);
10395 ll_remove_matching_addrs(jump_dirty+2048+(expirep&2047),base,shift);
10396 break;
10397 case 1:
10398 // Clear pointers
10399 ll_kill_pointers(jump_out[expirep&2047],base,shift);
10400 ll_kill_pointers(jump_out[(expirep&2047)+2048],base,shift);
10401 break;
10402 case 2:
10403 // Clear hash table
10404 for(i=0;i<32;i++) {
10405 int *ht_bin=hash_table[((expirep&2047)<<5)+i];
10406 if((ht_bin[3]>>shift)==(base>>shift) ||
10407 ((ht_bin[3]-MAX_OUTPUT_BLOCK_SIZE)>>shift)==(base>>shift)) {
10408 inv_debug("EXP: Remove hash %x -> %x\n",ht_bin[2],ht_bin[3]);
10409 ht_bin[2]=ht_bin[3]=-1;
10410 }
10411 if((ht_bin[1]>>shift)==(base>>shift) ||
10412 ((ht_bin[1]-MAX_OUTPUT_BLOCK_SIZE)>>shift)==(base>>shift)) {
10413 inv_debug("EXP: Remove hash %x -> %x\n",ht_bin[0],ht_bin[1]);
10414 ht_bin[0]=ht_bin[2];
10415 ht_bin[1]=ht_bin[3];
10416 ht_bin[2]=ht_bin[3]=-1;
10417 }
10418 }
10419 break;
10420 case 3:
10421 // Clear jump_out
dd3a91a1 10422 #ifdef __arm__
10423 if((expirep&2047)==0)
10424 do_clear_cache();
10425 #endif
57871462 10426 ll_remove_matching_addrs(jump_out+(expirep&2047),base,shift);
10427 ll_remove_matching_addrs(jump_out+2048+(expirep&2047),base,shift);
10428 break;
10429 }
10430 expirep=(expirep+1)&65535;
10431 }
10432 return 0;
10433}
b9b61529 10434
10435// vim:shiftwidth=2:expandtab
ARM optimized PCSX fork