drc: mark things static
[pcsx_rearmed.git] / libpcsxcore / new_dynarec / new_dynarec.c
CommitLineData
57871462 1/* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
2 * Mupen64plus - new_dynarec.c *
20d507ba 3 * Copyright (C) 2009-2011 Ari64 *
57871462 4 * *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
9 * *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
14 * *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. *
19 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */
20
21#include <stdlib.h>
22#include <stdint.h> //include for uint64_t
23#include <assert.h>
d848b60a 24#include <errno.h>
4600ba03 25#include <sys/mman.h>
57871462 26
3d624f89 27#include "emu_if.h" //emulator interface
57871462 28
4600ba03 29//#define DISASM
30//#define assem_debug printf
31//#define inv_debug printf
32#define assem_debug(...)
33#define inv_debug(...)
57871462 34
35#ifdef __i386__
36#include "assem_x86.h"
37#endif
38#ifdef __x86_64__
39#include "assem_x64.h"
40#endif
41#ifdef __arm__
42#include "assem_arm.h"
43#endif
44
f23d3386 45#ifdef __BLACKBERRY_QNX__
a4874585
C
46#undef __clear_cache
47#define __clear_cache(start,end) msync(start, (size_t)((void*)end - (void*)start), MS_SYNC | MS_CACHE_ONLY | MS_INVALIDATE_ICACHE);
c7b746f0 48#elif defined(__MACH__)
49#include <libkern/OSCacheControl.h>
50#define __clear_cache mach_clear_cache
51static void __clear_cache(void *start, void *end) {
52 size_t len = (char *)end - (char *)start;
53 sys_dcache_flush(start, len);
54 sys_icache_invalidate(start, len);
55}
f23d3386 56#endif
a4874585 57
57871462 58#define MAXBLOCK 4096
59#define MAX_OUTPUT_BLOCK_SIZE 262144
2573466a 60
57871462 61struct regstat
62{
63 signed char regmap_entry[HOST_REGS];
64 signed char regmap[HOST_REGS];
65 uint64_t was32;
66 uint64_t is32;
67 uint64_t wasdirty;
68 uint64_t dirty;
69 uint64_t u;
70 uint64_t uu;
71 u_int wasconst;
72 u_int isconst;
8575a877 73 u_int loadedconst; // host regs that have constants loaded
74 u_int waswritten; // MIPS regs that were used as store base before
57871462 75};
76
de5a60c3 77// note: asm depends on this layout
57871462 78struct ll_entry
79{
80 u_int vaddr;
de5a60c3 81 u_int reg_sv_flags;
57871462 82 void *addr;
83 struct ll_entry *next;
84};
85
e2b5e7aa 86 // used by asm:
87 u_char *out;
88 u_int hash_table[65536][4] __attribute__((aligned(16)));
89 struct ll_entry *jump_in[4096] __attribute__((aligned(16)));
90 struct ll_entry *jump_dirty[4096];
91
92 static struct ll_entry *jump_out[4096];
93 static u_int start;
94 static u_int *source;
95 static char insn[MAXBLOCK][10];
96 static u_char itype[MAXBLOCK];
97 static u_char opcode[MAXBLOCK];
98 static u_char opcode2[MAXBLOCK];
99 static u_char bt[MAXBLOCK];
100 static u_char rs1[MAXBLOCK];
101 static u_char rs2[MAXBLOCK];
102 static u_char rt1[MAXBLOCK];
103 static u_char rt2[MAXBLOCK];
104 static u_char us1[MAXBLOCK];
105 static u_char us2[MAXBLOCK];
106 static u_char dep1[MAXBLOCK];
107 static u_char dep2[MAXBLOCK];
108 static u_char lt1[MAXBLOCK];
bedfea38 109 static uint64_t gte_rs[MAXBLOCK]; // gte: 32 data and 32 ctl regs
110 static uint64_t gte_rt[MAXBLOCK];
111 static uint64_t gte_unneeded[MAXBLOCK];
ffb0b9e0 112 static u_int smrv[32]; // speculated MIPS register values
113 static u_int smrv_strong; // mask or regs that are likely to have correct values
114 static u_int smrv_weak; // same, but somewhat less likely
115 static u_int smrv_strong_next; // same, but after current insn executes
116 static u_int smrv_weak_next;
e2b5e7aa 117 static int imm[MAXBLOCK];
118 static u_int ba[MAXBLOCK];
119 static char likely[MAXBLOCK];
120 static char is_ds[MAXBLOCK];
121 static char ooo[MAXBLOCK];
122 static uint64_t unneeded_reg[MAXBLOCK];
123 static uint64_t unneeded_reg_upper[MAXBLOCK];
124 static uint64_t branch_unneeded_reg[MAXBLOCK];
125 static uint64_t branch_unneeded_reg_upper[MAXBLOCK];
126 static signed char regmap_pre[MAXBLOCK][HOST_REGS];
956f3129 127 static uint64_t current_constmap[HOST_REGS];
128 static uint64_t constmap[MAXBLOCK][HOST_REGS];
129 static struct regstat regs[MAXBLOCK];
130 static struct regstat branch_regs[MAXBLOCK];
e2b5e7aa 131 static signed char minimum_free_regs[MAXBLOCK];
132 static u_int needed_reg[MAXBLOCK];
133 static u_int wont_dirty[MAXBLOCK];
134 static u_int will_dirty[MAXBLOCK];
135 static int ccadj[MAXBLOCK];
136 static int slen;
137 static u_int instr_addr[MAXBLOCK];
138 static u_int link_addr[MAXBLOCK][3];
139 static int linkcount;
140 static u_int stubs[MAXBLOCK*3][8];
141 static int stubcount;
142 static u_int literals[1024][2];
143 static int literalcount;
144 static int is_delayslot;
145 static int cop1_usable;
146 static char shadow[1048576] __attribute__((aligned(16)));
147 static void *copy;
148 static int expirep;
149 static u_int stop_after_jal;
a327ad27 150#ifndef RAM_FIXED
151 static u_int ram_offset;
152#else
153 static const u_int ram_offset=0;
154#endif
e2b5e7aa 155
156 int new_dynarec_hacks;
157 int new_dynarec_did_compile;
57871462 158 extern u_char restore_candidate[512];
159 extern int cycle_count;
160
161 /* registers that may be allocated */
162 /* 1-31 gpr */
163#define HIREG 32 // hi
164#define LOREG 33 // lo
165#define FSREG 34 // FPU status (FCSR)
166#define CSREG 35 // Coprocessor status
167#define CCREG 36 // Cycle count
168#define INVCP 37 // Pointer to invalid_code
1edfcc68 169//#define MMREG 38 // Pointer to memory_map
619e5ded 170#define ROREG 39 // ram offset (if rdram!=0x80000000)
171#define TEMPREG 40
172#define FTEMP 40 // FPU temporary register
173#define PTEMP 41 // Prefetch temporary register
1edfcc68 174//#define TLREG 42 // TLB mapping offset
619e5ded 175#define RHASH 43 // Return address hash
176#define RHTBL 44 // Return address hash table address
177#define RTEMP 45 // JR/JALR address register
178#define MAXREG 45
179#define AGEN1 46 // Address generation temporary register
1edfcc68 180//#define AGEN2 47 // Address generation temporary register
181//#define MGEN1 48 // Maptable address generation temporary register
182//#define MGEN2 49 // Maptable address generation temporary register
619e5ded 183#define BTREG 50 // Branch target temporary register
57871462 184
185 /* instruction types */
186#define NOP 0 // No operation
187#define LOAD 1 // Load
188#define STORE 2 // Store
189#define LOADLR 3 // Unaligned load
190#define STORELR 4 // Unaligned store
9f51b4b9 191#define MOV 5 // Move
57871462 192#define ALU 6 // Arithmetic/logic
193#define MULTDIV 7 // Multiply/divide
194#define SHIFT 8 // Shift by register
195#define SHIFTIMM 9// Shift by immediate
196#define IMM16 10 // 16-bit immediate
197#define RJUMP 11 // Unconditional jump to register
198#define UJUMP 12 // Unconditional jump
199#define CJUMP 13 // Conditional branch (BEQ/BNE/BGTZ/BLEZ)
200#define SJUMP 14 // Conditional branch (regimm format)
201#define COP0 15 // Coprocessor 0
202#define COP1 16 // Coprocessor 1
203#define C1LS 17 // Coprocessor 1 load/store
204#define FJUMP 18 // Conditional branch (floating point)
205#define FLOAT 19 // Floating point unit
206#define FCONV 20 // Convert integer to float
207#define FCOMP 21 // Floating point compare (sets FSREG)
208#define SYSCALL 22// SYSCALL
209#define OTHER 23 // Other
210#define SPAN 24 // Branch/delay slot spans 2 pages
211#define NI 25 // Not implemented
7139f3c8 212#define HLECALL 26// PCSX fake opcodes for HLE
b9b61529 213#define COP2 27 // Coprocessor 2 move
214#define C2LS 28 // Coprocessor 2 load/store
215#define C2OP 29 // Coprocessor 2 operation
1e973cb0 216#define INTCALL 30// Call interpreter to handle rare corner cases
57871462 217
218 /* stubs */
219#define CC_STUB 1
220#define FP_STUB 2
221#define LOADB_STUB 3
222#define LOADH_STUB 4
223#define LOADW_STUB 5
224#define LOADD_STUB 6
225#define LOADBU_STUB 7
226#define LOADHU_STUB 8
227#define STOREB_STUB 9
228#define STOREH_STUB 10
229#define STOREW_STUB 11
230#define STORED_STUB 12
231#define STORELR_STUB 13
232#define INVCODE_STUB 14
233
234 /* branch codes */
235#define TAKEN 1
236#define NOTTAKEN 2
237#define NULLDS 3
238
239// asm linkage
240int new_recompile_block(int addr);
241void *get_addr_ht(u_int vaddr);
242void invalidate_block(u_int block);
243void invalidate_addr(u_int addr);
244void remove_hash(int vaddr);
57871462 245void dyna_linker();
246void dyna_linker_ds();
247void verify_code();
248void verify_code_vm();
249void verify_code_ds();
250void cc_interrupt();
251void fp_exception();
252void fp_exception_ds();
7139f3c8 253void jump_syscall_hle();
7139f3c8 254void jump_hlecall();
1e973cb0 255void jump_intcall();
7139f3c8 256void new_dyna_leave();
57871462 257
57871462 258// Needed by assembler
e2b5e7aa 259static void wb_register(signed char r,signed char regmap[],uint64_t dirty,uint64_t is32);
260static void wb_dirtys(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty);
261static void wb_needed_dirtys(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr);
262static void load_all_regs(signed char i_regmap[]);
263static void load_needed_regs(signed char i_regmap[],signed char next_regmap[]);
264static void load_regs_entry(int t);
265static void load_all_consts(signed char regmap[],int is32,u_int dirty,int i);
266
267static int verify_dirty(u_int *ptr);
268static int get_final_value(int hr, int i, int *value);
269static void add_stub(int type,int addr,int retaddr,int a,int b,int c,int d,int e);
270static void add_to_linker(int addr,int target,int ext);
57871462 271
e2b5e7aa 272static int tracedebug=0;
57871462 273
274//#define DEBUG_CYCLE_COUNT 1
275
b6e87b2b 276#define NO_CYCLE_PENALTY_THR 12
277
4e9dcd7f 278int cycle_multiplier; // 100 for 1.0
279
280static int CLOCK_ADJUST(int x)
281{
282 int s=(x>>31)|1;
283 return (x * cycle_multiplier + s * 50) / 100;
284}
285
94d23bb9 286static u_int get_page(u_int vaddr)
57871462 287{
0ce47d46 288 u_int page=vaddr&~0xe0000000;
289 if (page < 0x1000000)
290 page &= ~0x0e00000; // RAM mirrors
291 page>>=12;
57871462 292 if(page>2048) page=2048+(page&2047);
94d23bb9 293 return page;
294}
295
d25604ca 296// no virtual mem in PCSX
297static u_int get_vpage(u_int vaddr)
298{
299 return get_page(vaddr);
300}
94d23bb9 301
302// Get address from virtual address
303// This is called from the recompiled JR/JALR instructions
304void *get_addr(u_int vaddr)
305{
306 u_int page=get_page(vaddr);
307 u_int vpage=get_vpage(vaddr);
57871462 308 struct ll_entry *head;
309 //printf("TRACE: count=%d next=%d (get_addr %x,page %d)\n",Count,next_interupt,vaddr,page);
310 head=jump_in[page];
311 while(head!=NULL) {
de5a60c3 312 if(head->vaddr==vaddr) {
57871462 313 //printf("TRACE: count=%d next=%d (get_addr match %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr);
314 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
315 ht_bin[3]=ht_bin[1];
316 ht_bin[2]=ht_bin[0];
317 ht_bin[1]=(int)head->addr;
318 ht_bin[0]=vaddr;
319 return head->addr;
320 }
321 head=head->next;
322 }
323 head=jump_dirty[vpage];
324 while(head!=NULL) {
de5a60c3 325 if(head->vaddr==vaddr) {
57871462 326 //printf("TRACE: count=%d next=%d (get_addr match dirty %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr);
327 // Don't restore blocks which are about to expire from the cache
328 if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
329 if(verify_dirty(head->addr)) {
330 //printf("restore candidate: %x (%d) d=%d\n",vaddr,page,invalid_code[vaddr>>12]);
331 invalid_code[vaddr>>12]=0;
9be4ba64 332 inv_code_start=inv_code_end=~0;
57871462 333 if(vpage<2048) {
57871462 334 restore_candidate[vpage>>3]|=1<<(vpage&7);
335 }
336 else restore_candidate[page>>3]|=1<<(page&7);
337 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
338 if(ht_bin[0]==vaddr) {
339 ht_bin[1]=(int)head->addr; // Replace existing entry
340 }
341 else
342 {
343 ht_bin[3]=ht_bin[1];
344 ht_bin[2]=ht_bin[0];
345 ht_bin[1]=(int)head->addr;
346 ht_bin[0]=vaddr;
347 }
348 return head->addr;
349 }
350 }
351 head=head->next;
352 }
353 //printf("TRACE: count=%d next=%d (get_addr no-match %x)\n",Count,next_interupt,vaddr);
354 int r=new_recompile_block(vaddr);
355 if(r==0) return get_addr(vaddr);
356 // Execute in unmapped page, generate pagefault execption
357 Status|=2;
358 Cause=(vaddr<<31)|0x8;
359 EPC=(vaddr&1)?vaddr-5:vaddr;
360 BadVAddr=(vaddr&~1);
361 Context=(Context&0xFF80000F)|((BadVAddr>>9)&0x007FFFF0);
362 EntryHi=BadVAddr&0xFFFFE000;
363 return get_addr_ht(0x80000000);
364}
365// Look up address in hash table first
366void *get_addr_ht(u_int vaddr)
367{
368 //printf("TRACE: count=%d next=%d (get_addr_ht %x)\n",Count,next_interupt,vaddr);
369 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
370 if(ht_bin[0]==vaddr) return (void *)ht_bin[1];
371 if(ht_bin[2]==vaddr) return (void *)ht_bin[3];
372 return get_addr(vaddr);
373}
374
57871462 375void clear_all_regs(signed char regmap[])
376{
377 int hr;
378 for (hr=0;hr<HOST_REGS;hr++) regmap[hr]=-1;
379}
380
381signed char get_reg(signed char regmap[],int r)
382{
383 int hr;
384 for (hr=0;hr<HOST_REGS;hr++) if(hr!=EXCLUDE_REG&&regmap[hr]==r) return hr;
385 return -1;
386}
387
388// Find a register that is available for two consecutive cycles
389signed char get_reg2(signed char regmap1[],signed char regmap2[],int r)
390{
391 int hr;
392 for (hr=0;hr<HOST_REGS;hr++) if(hr!=EXCLUDE_REG&&regmap1[hr]==r&&regmap2[hr]==r) return hr;
393 return -1;
394}
395
396int count_free_regs(signed char regmap[])
397{
398 int count=0;
399 int hr;
400 for(hr=0;hr<HOST_REGS;hr++)
401 {
402 if(hr!=EXCLUDE_REG) {
403 if(regmap[hr]<0) count++;
404 }
405 }
406 return count;
407}
408
409void dirty_reg(struct regstat *cur,signed char reg)
410{
411 int hr;
412 if(!reg) return;
413 for (hr=0;hr<HOST_REGS;hr++) {
414 if((cur->regmap[hr]&63)==reg) {
415 cur->dirty|=1<<hr;
416 }
417 }
418}
419
420// If we dirty the lower half of a 64 bit register which is now being
421// sign-extended, we need to dump the upper half.
422// Note: Do this only after completion of the instruction, because
423// some instructions may need to read the full 64-bit value even if
424// overwriting it (eg SLTI, DSRA32).
425static void flush_dirty_uppers(struct regstat *cur)
426{
427 int hr,reg;
428 for (hr=0;hr<HOST_REGS;hr++) {
429 if((cur->dirty>>hr)&1) {
430 reg=cur->regmap[hr];
9f51b4b9 431 if(reg>=64)
57871462 432 if((cur->is32>>(reg&63))&1) cur->regmap[hr]=-1;
433 }
434 }
435}
436
437void set_const(struct regstat *cur,signed char reg,uint64_t value)
438{
439 int hr;
440 if(!reg) return;
441 for (hr=0;hr<HOST_REGS;hr++) {
442 if(cur->regmap[hr]==reg) {
443 cur->isconst|=1<<hr;
956f3129 444 current_constmap[hr]=value;
57871462 445 }
446 else if((cur->regmap[hr]^64)==reg) {
447 cur->isconst|=1<<hr;
956f3129 448 current_constmap[hr]=value>>32;
57871462 449 }
450 }
451}
452
453void clear_const(struct regstat *cur,signed char reg)
454{
455 int hr;
456 if(!reg) return;
457 for (hr=0;hr<HOST_REGS;hr++) {
458 if((cur->regmap[hr]&63)==reg) {
459 cur->isconst&=~(1<<hr);
460 }
461 }
462}
463
464int is_const(struct regstat *cur,signed char reg)
465{
466 int hr;
79c75f1b 467 if(reg<0) return 0;
57871462 468 if(!reg) return 1;
469 for (hr=0;hr<HOST_REGS;hr++) {
470 if((cur->regmap[hr]&63)==reg) {
471 return (cur->isconst>>hr)&1;
472 }
473 }
474 return 0;
475}
476uint64_t get_const(struct regstat *cur,signed char reg)
477{
478 int hr;
479 if(!reg) return 0;
480 for (hr=0;hr<HOST_REGS;hr++) {
481 if(cur->regmap[hr]==reg) {
956f3129 482 return current_constmap[hr];
57871462 483 }
484 }
c43b5311 485 SysPrintf("Unknown constant in r%d\n",reg);
57871462 486 exit(1);
487}
488
489// Least soon needed registers
490// Look at the next ten instructions and see which registers
491// will be used. Try not to reallocate these.
492void lsn(u_char hsn[], int i, int *preferred_reg)
493{
494 int j;
495 int b=-1;
496 for(j=0;j<9;j++)
497 {
498 if(i+j>=slen) {
499 j=slen-i-1;
500 break;
501 }
502 if(itype[i+j]==UJUMP||itype[i+j]==RJUMP||(source[i+j]>>16)==0x1000)
503 {
504 // Don't go past an unconditonal jump
505 j++;
506 break;
507 }
508 }
509 for(;j>=0;j--)
510 {
511 if(rs1[i+j]) hsn[rs1[i+j]]=j;
512 if(rs2[i+j]) hsn[rs2[i+j]]=j;
513 if(rt1[i+j]) hsn[rt1[i+j]]=j;
514 if(rt2[i+j]) hsn[rt2[i+j]]=j;
515 if(itype[i+j]==STORE || itype[i+j]==STORELR) {
516 // Stores can allocate zero
517 hsn[rs1[i+j]]=j;
518 hsn[rs2[i+j]]=j;
519 }
520 // On some architectures stores need invc_ptr
521 #if defined(HOST_IMM8)
b9b61529 522 if(itype[i+j]==STORE || itype[i+j]==STORELR || (opcode[i+j]&0x3b)==0x39 || (opcode[i+j]&0x3b)==0x3a) {
57871462 523 hsn[INVCP]=j;
524 }
525 #endif
526 if(i+j>=0&&(itype[i+j]==UJUMP||itype[i+j]==CJUMP||itype[i+j]==SJUMP||itype[i+j]==FJUMP))
527 {
528 hsn[CCREG]=j;
529 b=j;
530 }
531 }
532 if(b>=0)
533 {
534 if(ba[i+b]>=start && ba[i+b]<(start+slen*4))
535 {
536 // Follow first branch
537 int t=(ba[i+b]-start)>>2;
538 j=7-b;if(t+j>=slen) j=slen-t-1;
539 for(;j>=0;j--)
540 {
541 if(rs1[t+j]) if(hsn[rs1[t+j]]>j+b+2) hsn[rs1[t+j]]=j+b+2;
542 if(rs2[t+j]) if(hsn[rs2[t+j]]>j+b+2) hsn[rs2[t+j]]=j+b+2;
543 //if(rt1[t+j]) if(hsn[rt1[t+j]]>j+b+2) hsn[rt1[t+j]]=j+b+2;
544 //if(rt2[t+j]) if(hsn[rt2[t+j]]>j+b+2) hsn[rt2[t+j]]=j+b+2;
545 }
546 }
547 // TODO: preferred register based on backward branch
548 }
549 // Delay slot should preferably not overwrite branch conditions or cycle count
550 if(i>0&&(itype[i-1]==RJUMP||itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP)) {
551 if(rs1[i-1]) if(hsn[rs1[i-1]]>1) hsn[rs1[i-1]]=1;
552 if(rs2[i-1]) if(hsn[rs2[i-1]]>1) hsn[rs2[i-1]]=1;
553 hsn[CCREG]=1;
554 // ...or hash tables
555 hsn[RHASH]=1;
556 hsn[RHTBL]=1;
557 }
558 // Coprocessor load/store needs FTEMP, even if not declared
b9b61529 559 if(itype[i]==C1LS||itype[i]==C2LS) {
57871462 560 hsn[FTEMP]=0;
561 }
562 // Load L/R also uses FTEMP as a temporary register
563 if(itype[i]==LOADLR) {
564 hsn[FTEMP]=0;
565 }
b7918751 566 // Also SWL/SWR/SDL/SDR
567 if(opcode[i]==0x2a||opcode[i]==0x2e||opcode[i]==0x2c||opcode[i]==0x2d) {
57871462 568 hsn[FTEMP]=0;
569 }
57871462 570 // Don't remove the miniht registers
571 if(itype[i]==UJUMP||itype[i]==RJUMP)
572 {
573 hsn[RHASH]=0;
574 hsn[RHTBL]=0;
575 }
576}
577
578// We only want to allocate registers if we're going to use them again soon
579int needed_again(int r, int i)
580{
581 int j;
582 int b=-1;
583 int rn=10;
9f51b4b9 584
57871462 585 if(i>0&&(itype[i-1]==UJUMP||itype[i-1]==RJUMP||(source[i-1]>>16)==0x1000))
586 {
587 if(ba[i-1]<start || ba[i-1]>start+slen*4-4)
588 return 0; // Don't need any registers if exiting the block
589 }
590 for(j=0;j<9;j++)
591 {
592 if(i+j>=slen) {
593 j=slen-i-1;
594 break;
595 }
596 if(itype[i+j]==UJUMP||itype[i+j]==RJUMP||(source[i+j]>>16)==0x1000)
597 {
598 // Don't go past an unconditonal jump
599 j++;
600 break;
601 }
1e973cb0 602 if(itype[i+j]==SYSCALL||itype[i+j]==HLECALL||itype[i+j]==INTCALL||((source[i+j]&0xfc00003f)==0x0d))
57871462 603 {
604 break;
605 }
606 }
607 for(;j>=1;j--)
608 {
609 if(rs1[i+j]==r) rn=j;
610 if(rs2[i+j]==r) rn=j;
611 if((unneeded_reg[i+j]>>r)&1) rn=10;
612 if(i+j>=0&&(itype[i+j]==UJUMP||itype[i+j]==CJUMP||itype[i+j]==SJUMP||itype[i+j]==FJUMP))
613 {
614 b=j;
615 }
616 }
617 /*
618 if(b>=0)
619 {
620 if(ba[i+b]>=start && ba[i+b]<(start+slen*4))
621 {
622 // Follow first branch
623 int o=rn;
624 int t=(ba[i+b]-start)>>2;
625 j=7-b;if(t+j>=slen) j=slen-t-1;
626 for(;j>=0;j--)
627 {
628 if(!((unneeded_reg[t+j]>>r)&1)) {
629 if(rs1[t+j]==r) if(rn>j+b+2) rn=j+b+2;
630 if(rs2[t+j]==r) if(rn>j+b+2) rn=j+b+2;
631 }
632 else rn=o;
633 }
634 }
635 }*/
b7217e13 636 if(rn<10) return 1;
57871462 637 return 0;
638}
639
640// Try to match register allocations at the end of a loop with those
641// at the beginning
642int loop_reg(int i, int r, int hr)
643{
644 int j,k;
645 for(j=0;j<9;j++)
646 {
647 if(i+j>=slen) {
648 j=slen-i-1;
649 break;
650 }
651 if(itype[i+j]==UJUMP||itype[i+j]==RJUMP||(source[i+j]>>16)==0x1000)
652 {
653 // Don't go past an unconditonal jump
654 j++;
655 break;
656 }
657 }
658 k=0;
659 if(i>0){
660 if(itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP)
661 k--;
662 }
663 for(;k<j;k++)
664 {
665 if(r<64&&((unneeded_reg[i+k]>>r)&1)) return hr;
666 if(r>64&&((unneeded_reg_upper[i+k]>>r)&1)) return hr;
667 if(i+k>=0&&(itype[i+k]==UJUMP||itype[i+k]==CJUMP||itype[i+k]==SJUMP||itype[i+k]==FJUMP))
668 {
669 if(ba[i+k]>=start && ba[i+k]<(start+i*4))
670 {
671 int t=(ba[i+k]-start)>>2;
672 int reg=get_reg(regs[t].regmap_entry,r);
673 if(reg>=0) return reg;
674 //reg=get_reg(regs[t+1].regmap_entry,r);
675 //if(reg>=0) return reg;
676 }
677 }
678 }
679 return hr;
680}
681
682
683// Allocate every register, preserving source/target regs
684void alloc_all(struct regstat *cur,int i)
685{
686 int hr;
9f51b4b9 687
57871462 688 for(hr=0;hr<HOST_REGS;hr++) {
689 if(hr!=EXCLUDE_REG) {
690 if(((cur->regmap[hr]&63)!=rs1[i])&&((cur->regmap[hr]&63)!=rs2[i])&&
691 ((cur->regmap[hr]&63)!=rt1[i])&&((cur->regmap[hr]&63)!=rt2[i]))
692 {
693 cur->regmap[hr]=-1;
694 cur->dirty&=~(1<<hr);
695 }
696 // Don't need zeros
697 if((cur->regmap[hr]&63)==0)
698 {
699 cur->regmap[hr]=-1;
700 cur->dirty&=~(1<<hr);
701 }
702 }
703 }
704}
705
57871462 706#ifdef __i386__
707#include "assem_x86.c"
708#endif
709#ifdef __x86_64__
710#include "assem_x64.c"
711#endif
712#ifdef __arm__
713#include "assem_arm.c"
714#endif
715
716// Add virtual address mapping to linked list
717void ll_add(struct ll_entry **head,int vaddr,void *addr)
718{
719 struct ll_entry *new_entry;
720 new_entry=malloc(sizeof(struct ll_entry));
721 assert(new_entry!=NULL);
722 new_entry->vaddr=vaddr;
de5a60c3 723 new_entry->reg_sv_flags=0;
57871462 724 new_entry->addr=addr;
725 new_entry->next=*head;
726 *head=new_entry;
727}
728
de5a60c3 729void ll_add_flags(struct ll_entry **head,int vaddr,u_int reg_sv_flags,void *addr)
57871462 730{
7139f3c8 731 ll_add(head,vaddr,addr);
de5a60c3 732 (*head)->reg_sv_flags=reg_sv_flags;
57871462 733}
734
735// Check if an address is already compiled
736// but don't return addresses which are about to expire from the cache
737void *check_addr(u_int vaddr)
738{
739 u_int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
740 if(ht_bin[0]==vaddr) {
741 if(((ht_bin[1]-MAX_OUTPUT_BLOCK_SIZE-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
742 if(isclean(ht_bin[1])) return (void *)ht_bin[1];
743 }
744 if(ht_bin[2]==vaddr) {
745 if(((ht_bin[3]-MAX_OUTPUT_BLOCK_SIZE-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
746 if(isclean(ht_bin[3])) return (void *)ht_bin[3];
747 }
94d23bb9 748 u_int page=get_page(vaddr);
57871462 749 struct ll_entry *head;
750 head=jump_in[page];
751 while(head!=NULL) {
de5a60c3 752 if(head->vaddr==vaddr) {
57871462 753 if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2))) {
754 // Update existing entry with current address
755 if(ht_bin[0]==vaddr) {
756 ht_bin[1]=(int)head->addr;
757 return head->addr;
758 }
759 if(ht_bin[2]==vaddr) {
760 ht_bin[3]=(int)head->addr;
761 return head->addr;
762 }
763 // Insert into hash table with low priority.
764 // Don't evict existing entries, as they are probably
765 // addresses that are being accessed frequently.
766 if(ht_bin[0]==-1) {
767 ht_bin[1]=(int)head->addr;
768 ht_bin[0]=vaddr;
769 }else if(ht_bin[2]==-1) {
770 ht_bin[3]=(int)head->addr;
771 ht_bin[2]=vaddr;
772 }
773 return head->addr;
774 }
775 }
776 head=head->next;
777 }
778 return 0;
779}
780
781void remove_hash(int vaddr)
782{
783 //printf("remove hash: %x\n",vaddr);
784 int *ht_bin=hash_table[(((vaddr)>>16)^vaddr)&0xFFFF];
785 if(ht_bin[2]==vaddr) {
786 ht_bin[2]=ht_bin[3]=-1;
787 }
788 if(ht_bin[0]==vaddr) {
789 ht_bin[0]=ht_bin[2];
790 ht_bin[1]=ht_bin[3];
791 ht_bin[2]=ht_bin[3]=-1;
792 }
793}
794
795void ll_remove_matching_addrs(struct ll_entry **head,int addr,int shift)
796{
797 struct ll_entry *next;
798 while(*head) {
9f51b4b9 799 if(((u_int)((*head)->addr)>>shift)==(addr>>shift) ||
57871462 800 ((u_int)((*head)->addr-MAX_OUTPUT_BLOCK_SIZE)>>shift)==(addr>>shift))
801 {
802 inv_debug("EXP: Remove pointer to %x (%x)\n",(int)(*head)->addr,(*head)->vaddr);
803 remove_hash((*head)->vaddr);
804 next=(*head)->next;
805 free(*head);
806 *head=next;
807 }
808 else
809 {
810 head=&((*head)->next);
811 }
812 }
813}
814
815// Remove all entries from linked list
816void ll_clear(struct ll_entry **head)
817{
818 struct ll_entry *cur;
819 struct ll_entry *next;
820 if(cur=*head) {
821 *head=0;
822 while(cur) {
823 next=cur->next;
824 free(cur);
825 cur=next;
826 }
827 }
828}
829
830// Dereference the pointers and remove if it matches
831void ll_kill_pointers(struct ll_entry *head,int addr,int shift)
832{
833 while(head) {
834 int ptr=get_pointer(head->addr);
835 inv_debug("EXP: Lookup pointer to %x at %x (%x)\n",(int)ptr,(int)head->addr,head->vaddr);
836 if(((ptr>>shift)==(addr>>shift)) ||
837 (((ptr-MAX_OUTPUT_BLOCK_SIZE)>>shift)==(addr>>shift)))
838 {
5088bb70 839 inv_debug("EXP: Kill pointer at %x (%x)\n",(int)head->addr,head->vaddr);
f76eeef9 840 u_int host_addr=(u_int)kill_pointer(head->addr);
dd3a91a1 841 #ifdef __arm__
842 needs_clear_cache[(host_addr-(u_int)BASE_ADDR)>>17]|=1<<(((host_addr-(u_int)BASE_ADDR)>>12)&31);
843 #endif
57871462 844 }
845 head=head->next;
846 }
847}
848
849// This is called when we write to a compiled block (see do_invstub)
f76eeef9 850void invalidate_page(u_int page)
57871462 851{
57871462 852 struct ll_entry *head;
853 struct ll_entry *next;
854 head=jump_in[page];
855 jump_in[page]=0;
856 while(head!=NULL) {
857 inv_debug("INVALIDATE: %x\n",head->vaddr);
858 remove_hash(head->vaddr);
859 next=head->next;
860 free(head);
861 head=next;
862 }
863 head=jump_out[page];
864 jump_out[page]=0;
865 while(head!=NULL) {
866 inv_debug("INVALIDATE: kill pointer to %x (%x)\n",head->vaddr,(int)head->addr);
f76eeef9 867 u_int host_addr=(u_int)kill_pointer(head->addr);
dd3a91a1 868 #ifdef __arm__
869 needs_clear_cache[(host_addr-(u_int)BASE_ADDR)>>17]|=1<<(((host_addr-(u_int)BASE_ADDR)>>12)&31);
870 #endif
57871462 871 next=head->next;
872 free(head);
873 head=next;
874 }
57871462 875}
9be4ba64 876
877static void invalidate_block_range(u_int block, u_int first, u_int last)
57871462 878{
94d23bb9 879 u_int page=get_page(block<<12);
57871462 880 //printf("first=%d last=%d\n",first,last);
f76eeef9 881 invalidate_page(page);
57871462 882 assert(first+5>page); // NB: this assumes MAXBLOCK<=4096 (4 pages)
883 assert(last<page+5);
884 // Invalidate the adjacent pages if a block crosses a 4K boundary
885 while(first<page) {
886 invalidate_page(first);
887 first++;
888 }
889 for(first=page+1;first<last;first++) {
890 invalidate_page(first);
891 }
dd3a91a1 892 #ifdef __arm__
893 do_clear_cache();
894 #endif
9f51b4b9 895
57871462 896 // Don't trap writes
897 invalid_code[block]=1;
f76eeef9 898
57871462 899 #ifdef USE_MINI_HT
900 memset(mini_ht,-1,sizeof(mini_ht));
901 #endif
902}
9be4ba64 903
904void invalidate_block(u_int block)
905{
906 u_int page=get_page(block<<12);
907 u_int vpage=get_vpage(block<<12);
908 inv_debug("INVALIDATE: %x (%d)\n",block<<12,page);
909 //inv_debug("invalid_code[block]=%d\n",invalid_code[block]);
910 u_int first,last;
911 first=last=page;
912 struct ll_entry *head;
913 head=jump_dirty[vpage];
914 //printf("page=%d vpage=%d\n",page,vpage);
915 while(head!=NULL) {
916 u_int start,end;
917 if(vpage>2047||(head->vaddr>>12)==block) { // Ignore vaddr hash collision
918 get_bounds((int)head->addr,&start,&end);
919 //printf("start: %x end: %x\n",start,end);
4a35de07 920 if(page<2048&&start>=(u_int)rdram&&end<(u_int)rdram+RAM_SIZE) {
9be4ba64 921 if(((start-(u_int)rdram)>>12)<=page&&((end-1-(u_int)rdram)>>12)>=page) {
922 if((((start-(u_int)rdram)>>12)&2047)<first) first=((start-(u_int)rdram)>>12)&2047;
923 if((((end-1-(u_int)rdram)>>12)&2047)>last) last=((end-1-(u_int)rdram)>>12)&2047;
924 }
925 }
9be4ba64 926 }
927 head=head->next;
928 }
929 invalidate_block_range(block,first,last);
930}
931
57871462 932void invalidate_addr(u_int addr)
933{
9be4ba64 934 //static int rhits;
935 // this check is done by the caller
936 //if (inv_code_start<=addr&&addr<=inv_code_end) { rhits++; return; }
d25604ca 937 u_int page=get_vpage(addr);
9be4ba64 938 if(page<2048) { // RAM
939 struct ll_entry *head;
940 u_int addr_min=~0, addr_max=0;
4a35de07 941 u_int mask=RAM_SIZE-1;
942 u_int addr_main=0x80000000|(addr&mask);
9be4ba64 943 int pg1;
4a35de07 944 inv_code_start=addr_main&~0xfff;
945 inv_code_end=addr_main|0xfff;
9be4ba64 946 pg1=page;
947 if (pg1>0) {
948 // must check previous page too because of spans..
949 pg1--;
950 inv_code_start-=0x1000;
951 }
952 for(;pg1<=page;pg1++) {
953 for(head=jump_dirty[pg1];head!=NULL;head=head->next) {
954 u_int start,end;
955 get_bounds((int)head->addr,&start,&end);
4a35de07 956 if(ram_offset) {
957 start-=ram_offset;
958 end-=ram_offset;
959 }
960 if(start<=addr_main&&addr_main<end) {
9be4ba64 961 if(start<addr_min) addr_min=start;
962 if(end>addr_max) addr_max=end;
963 }
4a35de07 964 else if(addr_main<start) {
9be4ba64 965 if(start<inv_code_end)
966 inv_code_end=start-1;
967 }
968 else {
969 if(end>inv_code_start)
970 inv_code_start=end;
971 }
972 }
973 }
974 if (addr_min!=~0) {
975 inv_debug("INV ADDR: %08x hit %08x-%08x\n", addr, addr_min, addr_max);
976 inv_code_start=inv_code_end=~0;
977 invalidate_block_range(addr>>12,(addr_min&mask)>>12,(addr_max&mask)>>12);
978 return;
979 }
980 else {
4a35de07 981 inv_code_start=(addr&~mask)|(inv_code_start&mask);
982 inv_code_end=(addr&~mask)|(inv_code_end&mask);
d25604ca 983 inv_debug("INV ADDR: %08x miss, inv %08x-%08x, sk %d\n", addr, inv_code_start, inv_code_end, 0);
9be4ba64 984 return;
d25604ca 985 }
9be4ba64 986 }
57871462 987 invalidate_block(addr>>12);
988}
9be4ba64 989
dd3a91a1 990// This is called when loading a save state.
991// Anything could have changed, so invalidate everything.
57871462 992void invalidate_all_pages()
993{
994 u_int page,n;
995 for(page=0;page<4096;page++)
996 invalidate_page(page);
997 for(page=0;page<1048576;page++)
998 if(!invalid_code[page]) {
999 restore_candidate[(page&2047)>>3]|=1<<(page&7);
1000 restore_candidate[((page&2047)>>3)+256]|=1<<(page&7);
1001 }
1002 #ifdef __arm__
1003 __clear_cache((void *)BASE_ADDR,(void *)BASE_ADDR+(1<<TARGET_SIZE_2));
1004 #endif
1005 #ifdef USE_MINI_HT
1006 memset(mini_ht,-1,sizeof(mini_ht));
1007 #endif
57871462 1008}
1009
1010// Add an entry to jump_out after making a link
1011void add_link(u_int vaddr,void *src)
1012{
94d23bb9 1013 u_int page=get_page(vaddr);
57871462 1014 inv_debug("add_link: %x -> %x (%d)\n",(int)src,vaddr,page);
76f71c27 1015 int *ptr=(int *)(src+4);
1016 assert((*ptr&0x0fff0000)==0x059f0000);
57871462 1017 ll_add(jump_out+page,vaddr,src);
1018 //int ptr=get_pointer(src);
1019 //inv_debug("add_link: Pointer is to %x\n",(int)ptr);
1020}
1021
1022// If a code block was found to be unmodified (bit was set in
1023// restore_candidate) and it remains unmodified (bit is clear
1024// in invalid_code) then move the entries for that 4K page from
1025// the dirty list to the clean list.
1026void clean_blocks(u_int page)
1027{
1028 struct ll_entry *head;
1029 inv_debug("INV: clean_blocks page=%d\n",page);
1030 head=jump_dirty[page];
1031 while(head!=NULL) {
1032 if(!invalid_code[head->vaddr>>12]) {
1033 // Don't restore blocks which are about to expire from the cache
1034 if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2))) {
1035 u_int start,end;
1036 if(verify_dirty((int)head->addr)) {
1037 //printf("Possibly Restore %x (%x)\n",head->vaddr, (int)head->addr);
1038 u_int i;
1039 u_int inv=0;
1040 get_bounds((int)head->addr,&start,&end);
4cb76aa4 1041 if(start-(u_int)rdram<RAM_SIZE) {
57871462 1042 for(i=(start-(u_int)rdram+0x80000000)>>12;i<=(end-1-(u_int)rdram+0x80000000)>>12;i++) {
1043 inv|=invalid_code[i];
1044 }
1045 }
4cb76aa4 1046 else if((signed int)head->vaddr>=(signed int)0x80000000+RAM_SIZE) {
57871462 1047 inv=1;
1048 }
1049 if(!inv) {
1050 void * clean_addr=(void *)get_clean_addr((int)head->addr);
1051 if((((u_int)clean_addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2))) {
1052 u_int ppage=page;
57871462 1053 inv_debug("INV: Restored %x (%x/%x)\n",head->vaddr, (int)head->addr, (int)clean_addr);
1054 //printf("page=%x, addr=%x\n",page,head->vaddr);
1055 //assert(head->vaddr>>12==(page|0x80000));
de5a60c3 1056 ll_add_flags(jump_in+ppage,head->vaddr,head->reg_sv_flags,clean_addr);
57871462 1057 int *ht_bin=hash_table[((head->vaddr>>16)^head->vaddr)&0xFFFF];
de5a60c3 1058 if(ht_bin[0]==head->vaddr) {
1059 ht_bin[1]=(int)clean_addr; // Replace existing entry
1060 }
1061 if(ht_bin[2]==head->vaddr) {
1062 ht_bin[3]=(int)clean_addr; // Replace existing entry
57871462 1063 }
1064 }
1065 }
1066 }
1067 }
1068 }
1069 head=head->next;
1070 }
1071}
1072
1073
1074void mov_alloc(struct regstat *current,int i)
1075{
1076 // Note: Don't need to actually alloc the source registers
1077 if((~current->is32>>rs1[i])&1) {
1078 //alloc_reg64(current,i,rs1[i]);
1079 alloc_reg64(current,i,rt1[i]);
1080 current->is32&=~(1LL<<rt1[i]);
1081 } else {
1082 //alloc_reg(current,i,rs1[i]);
1083 alloc_reg(current,i,rt1[i]);
1084 current->is32|=(1LL<<rt1[i]);
1085 }
1086 clear_const(current,rs1[i]);
1087 clear_const(current,rt1[i]);
1088 dirty_reg(current,rt1[i]);
1089}
1090
1091void shiftimm_alloc(struct regstat *current,int i)
1092{
57871462 1093 if(opcode2[i]<=0x3) // SLL/SRL/SRA
1094 {
1095 if(rt1[i]) {
1096 if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1097 else lt1[i]=rs1[i];
1098 alloc_reg(current,i,rt1[i]);
1099 current->is32|=1LL<<rt1[i];
1100 dirty_reg(current,rt1[i]);
dc49e339 1101 if(is_const(current,rs1[i])) {
1102 int v=get_const(current,rs1[i]);
1103 if(opcode2[i]==0x00) set_const(current,rt1[i],v<<imm[i]);
1104 if(opcode2[i]==0x02) set_const(current,rt1[i],(u_int)v>>imm[i]);
1105 if(opcode2[i]==0x03) set_const(current,rt1[i],v>>imm[i]);
1106 }
1107 else clear_const(current,rt1[i]);
57871462 1108 }
1109 }
dc49e339 1110 else
1111 {
1112 clear_const(current,rs1[i]);
1113 clear_const(current,rt1[i]);
1114 }
1115
57871462 1116 if(opcode2[i]>=0x38&&opcode2[i]<=0x3b) // DSLL/DSRL/DSRA
1117 {
1118 if(rt1[i]) {
1119 if(rs1[i]) alloc_reg64(current,i,rs1[i]);
1120 alloc_reg64(current,i,rt1[i]);
1121 current->is32&=~(1LL<<rt1[i]);
1122 dirty_reg(current,rt1[i]);
1123 }
1124 }
1125 if(opcode2[i]==0x3c) // DSLL32
1126 {
1127 if(rt1[i]) {
1128 if(rs1[i]) alloc_reg(current,i,rs1[i]);
1129 alloc_reg64(current,i,rt1[i]);
1130 current->is32&=~(1LL<<rt1[i]);
1131 dirty_reg(current,rt1[i]);
1132 }
1133 }
1134 if(opcode2[i]==0x3e) // DSRL32
1135 {
1136 if(rt1[i]) {
1137 alloc_reg64(current,i,rs1[i]);
1138 if(imm[i]==32) {
1139 alloc_reg64(current,i,rt1[i]);
1140 current->is32&=~(1LL<<rt1[i]);
1141 } else {
1142 alloc_reg(current,i,rt1[i]);
1143 current->is32|=1LL<<rt1[i];
1144 }
1145 dirty_reg(current,rt1[i]);
1146 }
1147 }
1148 if(opcode2[i]==0x3f) // DSRA32
1149 {
1150 if(rt1[i]) {
1151 alloc_reg64(current,i,rs1[i]);
1152 alloc_reg(current,i,rt1[i]);
1153 current->is32|=1LL<<rt1[i];
1154 dirty_reg(current,rt1[i]);
1155 }
1156 }
1157}
1158
1159void shift_alloc(struct regstat *current,int i)
1160{
1161 if(rt1[i]) {
1162 if(opcode2[i]<=0x07) // SLLV/SRLV/SRAV
1163 {
1164 if(rs1[i]) alloc_reg(current,i,rs1[i]);
1165 if(rs2[i]) alloc_reg(current,i,rs2[i]);
1166 alloc_reg(current,i,rt1[i]);
e1190b87 1167 if(rt1[i]==rs2[i]) {
1168 alloc_reg_temp(current,i,-1);
1169 minimum_free_regs[i]=1;
1170 }
57871462 1171 current->is32|=1LL<<rt1[i];
1172 } else { // DSLLV/DSRLV/DSRAV
1173 if(rs1[i]) alloc_reg64(current,i,rs1[i]);
1174 if(rs2[i]) alloc_reg(current,i,rs2[i]);
1175 alloc_reg64(current,i,rt1[i]);
1176 current->is32&=~(1LL<<rt1[i]);
1177 if(opcode2[i]==0x16||opcode2[i]==0x17) // DSRLV and DSRAV need a temporary register
e1190b87 1178 {
57871462 1179 alloc_reg_temp(current,i,-1);
e1190b87 1180 minimum_free_regs[i]=1;
1181 }
57871462 1182 }
1183 clear_const(current,rs1[i]);
1184 clear_const(current,rs2[i]);
1185 clear_const(current,rt1[i]);
1186 dirty_reg(current,rt1[i]);
1187 }
1188}
1189
1190void alu_alloc(struct regstat *current,int i)
1191{
1192 if(opcode2[i]>=0x20&&opcode2[i]<=0x23) { // ADD/ADDU/SUB/SUBU
1193 if(rt1[i]) {
1194 if(rs1[i]&&rs2[i]) {
1195 alloc_reg(current,i,rs1[i]);
1196 alloc_reg(current,i,rs2[i]);
1197 }
1198 else {
1199 if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1200 if(rs2[i]&&needed_again(rs2[i],i)) alloc_reg(current,i,rs2[i]);
1201 }
1202 alloc_reg(current,i,rt1[i]);
1203 }
1204 current->is32|=1LL<<rt1[i];
1205 }
1206 if(opcode2[i]==0x2a||opcode2[i]==0x2b) { // SLT/SLTU
1207 if(rt1[i]) {
1208 if(!((current->is32>>rs1[i])&(current->is32>>rs2[i])&1))
1209 {
1210 alloc_reg64(current,i,rs1[i]);
1211 alloc_reg64(current,i,rs2[i]);
1212 alloc_reg(current,i,rt1[i]);
1213 } else {
1214 alloc_reg(current,i,rs1[i]);
1215 alloc_reg(current,i,rs2[i]);
1216 alloc_reg(current,i,rt1[i]);
1217 }
1218 }
1219 current->is32|=1LL<<rt1[i];
1220 }
1221 if(opcode2[i]>=0x24&&opcode2[i]<=0x27) { // AND/OR/XOR/NOR
1222 if(rt1[i]) {
1223 if(rs1[i]&&rs2[i]) {
1224 alloc_reg(current,i,rs1[i]);
1225 alloc_reg(current,i,rs2[i]);
1226 }
1227 else
1228 {
1229 if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1230 if(rs2[i]&&needed_again(rs2[i],i)) alloc_reg(current,i,rs2[i]);
1231 }
1232 alloc_reg(current,i,rt1[i]);
1233 if(!((current->is32>>rs1[i])&(current->is32>>rs2[i])&1))
1234 {
1235 if(!((current->uu>>rt1[i])&1)) {
1236 alloc_reg64(current,i,rt1[i]);
1237 }
1238 if(get_reg(current->regmap,rt1[i]|64)>=0) {
1239 if(rs1[i]&&rs2[i]) {
1240 alloc_reg64(current,i,rs1[i]);
1241 alloc_reg64(current,i,rs2[i]);
1242 }
1243 else
1244 {
1245 // Is is really worth it to keep 64-bit values in registers?
1246 #ifdef NATIVE_64BIT
1247 if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg64(current,i,rs1[i]);
1248 if(rs2[i]&&needed_again(rs2[i],i)) alloc_reg64(current,i,rs2[i]);
1249 #endif
1250 }
1251 }
1252 current->is32&=~(1LL<<rt1[i]);
1253 } else {
1254 current->is32|=1LL<<rt1[i];
1255 }
1256 }
1257 }
1258 if(opcode2[i]>=0x2c&&opcode2[i]<=0x2f) { // DADD/DADDU/DSUB/DSUBU
1259 if(rt1[i]) {
1260 if(rs1[i]&&rs2[i]) {
1261 if(!((current->uu>>rt1[i])&1)||get_reg(current->regmap,rt1[i]|64)>=0) {
1262 alloc_reg64(current,i,rs1[i]);
1263 alloc_reg64(current,i,rs2[i]);
1264 alloc_reg64(current,i,rt1[i]);
1265 } else {
1266 alloc_reg(current,i,rs1[i]);
1267 alloc_reg(current,i,rs2[i]);
1268 alloc_reg(current,i,rt1[i]);
1269 }
1270 }
1271 else {
1272 alloc_reg(current,i,rt1[i]);
1273 if(!((current->uu>>rt1[i])&1)||get_reg(current->regmap,rt1[i]|64)>=0) {
1274 // DADD used as move, or zeroing
1275 // If we have a 64-bit source, then make the target 64 bits too
1276 if(rs1[i]&&!((current->is32>>rs1[i])&1)) {
1277 if(get_reg(current->regmap,rs1[i])>=0) alloc_reg64(current,i,rs1[i]);
1278 alloc_reg64(current,i,rt1[i]);
1279 } else if(rs2[i]&&!((current->is32>>rs2[i])&1)) {
1280 if(get_reg(current->regmap,rs2[i])>=0) alloc_reg64(current,i,rs2[i]);
1281 alloc_reg64(current,i,rt1[i]);
1282 }
1283 if(opcode2[i]>=0x2e&&rs2[i]) {
1284 // DSUB used as negation - 64-bit result
1285 // If we have a 32-bit register, extend it to 64 bits
1286 if(get_reg(current->regmap,rs2[i])>=0) alloc_reg64(current,i,rs2[i]);
1287 alloc_reg64(current,i,rt1[i]);
1288 }
1289 }
1290 }
1291 if(rs1[i]&&rs2[i]) {
1292 current->is32&=~(1LL<<rt1[i]);
1293 } else if(rs1[i]) {
1294 current->is32&=~(1LL<<rt1[i]);
1295 if((current->is32>>rs1[i])&1)
1296 current->is32|=1LL<<rt1[i];
1297 } else if(rs2[i]) {
1298 current->is32&=~(1LL<<rt1[i]);
1299 if((current->is32>>rs2[i])&1)
1300 current->is32|=1LL<<rt1[i];
1301 } else {
1302 current->is32|=1LL<<rt1[i];
1303 }
1304 }
1305 }
1306 clear_const(current,rs1[i]);
1307 clear_const(current,rs2[i]);
1308 clear_const(current,rt1[i]);
1309 dirty_reg(current,rt1[i]);
1310}
1311
1312void imm16_alloc(struct regstat *current,int i)
1313{
1314 if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1315 else lt1[i]=rs1[i];
1316 if(rt1[i]) alloc_reg(current,i,rt1[i]);
1317 if(opcode[i]==0x18||opcode[i]==0x19) { // DADDI/DADDIU
1318 current->is32&=~(1LL<<rt1[i]);
1319 if(!((current->uu>>rt1[i])&1)||get_reg(current->regmap,rt1[i]|64)>=0) {
1320 // TODO: Could preserve the 32-bit flag if the immediate is zero
1321 alloc_reg64(current,i,rt1[i]);
1322 alloc_reg64(current,i,rs1[i]);
1323 }
1324 clear_const(current,rs1[i]);
1325 clear_const(current,rt1[i]);
1326 }
1327 else if(opcode[i]==0x0a||opcode[i]==0x0b) { // SLTI/SLTIU
1328 if((~current->is32>>rs1[i])&1) alloc_reg64(current,i,rs1[i]);
1329 current->is32|=1LL<<rt1[i];
1330 clear_const(current,rs1[i]);
1331 clear_const(current,rt1[i]);
1332 }
1333 else if(opcode[i]>=0x0c&&opcode[i]<=0x0e) { // ANDI/ORI/XORI
1334 if(((~current->is32>>rs1[i])&1)&&opcode[i]>0x0c) {
1335 if(rs1[i]!=rt1[i]) {
1336 if(needed_again(rs1[i],i)) alloc_reg64(current,i,rs1[i]);
1337 alloc_reg64(current,i,rt1[i]);
1338 current->is32&=~(1LL<<rt1[i]);
1339 }
1340 }
1341 else current->is32|=1LL<<rt1[i]; // ANDI clears upper bits
1342 if(is_const(current,rs1[i])) {
1343 int v=get_const(current,rs1[i]);
1344 if(opcode[i]==0x0c) set_const(current,rt1[i],v&imm[i]);
1345 if(opcode[i]==0x0d) set_const(current,rt1[i],v|imm[i]);
1346 if(opcode[i]==0x0e) set_const(current,rt1[i],v^imm[i]);
1347 }
1348 else clear_const(current,rt1[i]);
1349 }
1350 else if(opcode[i]==0x08||opcode[i]==0x09) { // ADDI/ADDIU
1351 if(is_const(current,rs1[i])) {
1352 int v=get_const(current,rs1[i]);
1353 set_const(current,rt1[i],v+imm[i]);
1354 }
1355 else clear_const(current,rt1[i]);
1356 current->is32|=1LL<<rt1[i];
1357 }
1358 else {
1359 set_const(current,rt1[i],((long long)((short)imm[i]))<<16); // LUI
1360 current->is32|=1LL<<rt1[i];
1361 }
1362 dirty_reg(current,rt1[i]);
1363}
1364
1365void load_alloc(struct regstat *current,int i)
1366{
1367 clear_const(current,rt1[i]);
1368 //if(rs1[i]!=rt1[i]&&needed_again(rs1[i],i)) clear_const(current,rs1[i]); // Does this help or hurt?
1369 if(!rs1[i]) current->u&=~1LL; // Allow allocating r0 if it's the source register
1370 if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
373d1d07 1371 if(rt1[i]&&!((current->u>>rt1[i])&1)) {
57871462 1372 alloc_reg(current,i,rt1[i]);
373d1d07 1373 assert(get_reg(current->regmap,rt1[i])>=0);
57871462 1374 if(opcode[i]==0x27||opcode[i]==0x37) // LWU/LD
1375 {
1376 current->is32&=~(1LL<<rt1[i]);
1377 alloc_reg64(current,i,rt1[i]);
1378 }
1379 else if(opcode[i]==0x1A||opcode[i]==0x1B) // LDL/LDR
1380 {
1381 current->is32&=~(1LL<<rt1[i]);
1382 alloc_reg64(current,i,rt1[i]);
1383 alloc_all(current,i);
1384 alloc_reg64(current,i,FTEMP);
e1190b87 1385 minimum_free_regs[i]=HOST_REGS;
57871462 1386 }
1387 else current->is32|=1LL<<rt1[i];
1388 dirty_reg(current,rt1[i]);
57871462 1389 // LWL/LWR need a temporary register for the old value
1390 if(opcode[i]==0x22||opcode[i]==0x26)
1391 {
1392 alloc_reg(current,i,FTEMP);
1393 alloc_reg_temp(current,i,-1);
e1190b87 1394 minimum_free_regs[i]=1;
57871462 1395 }
1396 }
1397 else
1398 {
373d1d07 1399 // Load to r0 or unneeded register (dummy load)
57871462 1400 // but we still need a register to calculate the address
535d208a 1401 if(opcode[i]==0x22||opcode[i]==0x26)
1402 {
1403 alloc_reg(current,i,FTEMP); // LWL/LWR need another temporary
1404 }
57871462 1405 alloc_reg_temp(current,i,-1);
e1190b87 1406 minimum_free_regs[i]=1;
535d208a 1407 if(opcode[i]==0x1A||opcode[i]==0x1B) // LDL/LDR
1408 {
1409 alloc_all(current,i);
1410 alloc_reg64(current,i,FTEMP);
e1190b87 1411 minimum_free_regs[i]=HOST_REGS;
535d208a 1412 }
57871462 1413 }
1414}
1415
1416void store_alloc(struct regstat *current,int i)
1417{
1418 clear_const(current,rs2[i]);
1419 if(!(rs2[i])) current->u&=~1LL; // Allow allocating r0 if necessary
1420 if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1421 alloc_reg(current,i,rs2[i]);
1422 if(opcode[i]==0x2c||opcode[i]==0x2d||opcode[i]==0x3f) { // 64-bit SDL/SDR/SD
1423 alloc_reg64(current,i,rs2[i]);
1424 if(rs2[i]) alloc_reg(current,i,FTEMP);
1425 }
57871462 1426 #if defined(HOST_IMM8)
1427 // On CPUs without 32-bit immediates we need a pointer to invalid_code
1428 else alloc_reg(current,i,INVCP);
1429 #endif
b7918751 1430 if(opcode[i]==0x2a||opcode[i]==0x2e||opcode[i]==0x2c||opcode[i]==0x2d) { // SWL/SWL/SDL/SDR
57871462 1431 alloc_reg(current,i,FTEMP);
1432 }
1433 // We need a temporary register for address generation
1434 alloc_reg_temp(current,i,-1);
e1190b87 1435 minimum_free_regs[i]=1;
57871462 1436}
1437
1438void c1ls_alloc(struct regstat *current,int i)
1439{
1440 //clear_const(current,rs1[i]); // FIXME
1441 clear_const(current,rt1[i]);
1442 if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1443 alloc_reg(current,i,CSREG); // Status
1444 alloc_reg(current,i,FTEMP);
1445 if(opcode[i]==0x35||opcode[i]==0x3d) { // 64-bit LDC1/SDC1
1446 alloc_reg64(current,i,FTEMP);
1447 }
57871462 1448 #if defined(HOST_IMM8)
1449 // On CPUs without 32-bit immediates we need a pointer to invalid_code
1450 else if((opcode[i]&0x3b)==0x39) // SWC1/SDC1
1451 alloc_reg(current,i,INVCP);
1452 #endif
1453 // We need a temporary register for address generation
1454 alloc_reg_temp(current,i,-1);
1455}
1456
b9b61529 1457void c2ls_alloc(struct regstat *current,int i)
1458{
1459 clear_const(current,rt1[i]);
1460 if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1461 alloc_reg(current,i,FTEMP);
b9b61529 1462 #if defined(HOST_IMM8)
1463 // On CPUs without 32-bit immediates we need a pointer to invalid_code
1edfcc68 1464 if((opcode[i]&0x3b)==0x3a) // SWC2/SDC2
b9b61529 1465 alloc_reg(current,i,INVCP);
1466 #endif
1467 // We need a temporary register for address generation
1468 alloc_reg_temp(current,i,-1);
e1190b87 1469 minimum_free_regs[i]=1;
b9b61529 1470}
1471
57871462 1472#ifndef multdiv_alloc
1473void multdiv_alloc(struct regstat *current,int i)
1474{
1475 // case 0x18: MULT
1476 // case 0x19: MULTU
1477 // case 0x1A: DIV
1478 // case 0x1B: DIVU
1479 // case 0x1C: DMULT
1480 // case 0x1D: DMULTU
1481 // case 0x1E: DDIV
1482 // case 0x1F: DDIVU
1483 clear_const(current,rs1[i]);
1484 clear_const(current,rs2[i]);
1485 if(rs1[i]&&rs2[i])
1486 {
1487 if((opcode2[i]&4)==0) // 32-bit
1488 {
1489 current->u&=~(1LL<<HIREG);
1490 current->u&=~(1LL<<LOREG);
1491 alloc_reg(current,i,HIREG);
1492 alloc_reg(current,i,LOREG);
1493 alloc_reg(current,i,rs1[i]);
1494 alloc_reg(current,i,rs2[i]);
1495 current->is32|=1LL<<HIREG;
1496 current->is32|=1LL<<LOREG;
1497 dirty_reg(current,HIREG);
1498 dirty_reg(current,LOREG);
1499 }
1500 else // 64-bit
1501 {
1502 current->u&=~(1LL<<HIREG);
1503 current->u&=~(1LL<<LOREG);
1504 current->uu&=~(1LL<<HIREG);
1505 current->uu&=~(1LL<<LOREG);
1506 alloc_reg64(current,i,HIREG);
1507 //if(HOST_REGS>10) alloc_reg64(current,i,LOREG);
1508 alloc_reg64(current,i,rs1[i]);
1509 alloc_reg64(current,i,rs2[i]);
1510 alloc_all(current,i);
1511 current->is32&=~(1LL<<HIREG);
1512 current->is32&=~(1LL<<LOREG);
1513 dirty_reg(current,HIREG);
1514 dirty_reg(current,LOREG);
e1190b87 1515 minimum_free_regs[i]=HOST_REGS;
57871462 1516 }
1517 }
1518 else
1519 {
1520 // Multiply by zero is zero.
1521 // MIPS does not have a divide by zero exception.
1522 // The result is undefined, we return zero.
1523 alloc_reg(current,i,HIREG);
1524 alloc_reg(current,i,LOREG);
1525 current->is32|=1LL<<HIREG;
1526 current->is32|=1LL<<LOREG;
1527 dirty_reg(current,HIREG);
1528 dirty_reg(current,LOREG);
1529 }
1530}
1531#endif
1532
1533void cop0_alloc(struct regstat *current,int i)
1534{
1535 if(opcode2[i]==0) // MFC0
1536 {
1537 if(rt1[i]) {
1538 clear_const(current,rt1[i]);
1539 alloc_all(current,i);
1540 alloc_reg(current,i,rt1[i]);
1541 current->is32|=1LL<<rt1[i];
1542 dirty_reg(current,rt1[i]);
1543 }
1544 }
1545 else if(opcode2[i]==4) // MTC0
1546 {
1547 if(rs1[i]){
1548 clear_const(current,rs1[i]);
1549 alloc_reg(current,i,rs1[i]);
1550 alloc_all(current,i);
1551 }
1552 else {
1553 alloc_all(current,i); // FIXME: Keep r0
1554 current->u&=~1LL;
1555 alloc_reg(current,i,0);
1556 }
1557 }
1558 else
1559 {
1560 // TLBR/TLBWI/TLBWR/TLBP/ERET
1561 assert(opcode2[i]==0x10);
1562 alloc_all(current,i);
1563 }
e1190b87 1564 minimum_free_regs[i]=HOST_REGS;
57871462 1565}
1566
1567void cop1_alloc(struct regstat *current,int i)
1568{
1569 alloc_reg(current,i,CSREG); // Load status
1570 if(opcode2[i]<3) // MFC1/DMFC1/CFC1
1571 {
7de557a6 1572 if(rt1[i]){
1573 clear_const(current,rt1[i]);
1574 if(opcode2[i]==1) {
1575 alloc_reg64(current,i,rt1[i]); // DMFC1
1576 current->is32&=~(1LL<<rt1[i]);
1577 }else{
1578 alloc_reg(current,i,rt1[i]); // MFC1/CFC1
1579 current->is32|=1LL<<rt1[i];
1580 }
1581 dirty_reg(current,rt1[i]);
57871462 1582 }
57871462 1583 alloc_reg_temp(current,i,-1);
1584 }
1585 else if(opcode2[i]>3) // MTC1/DMTC1/CTC1
1586 {
1587 if(rs1[i]){
1588 clear_const(current,rs1[i]);
1589 if(opcode2[i]==5)
1590 alloc_reg64(current,i,rs1[i]); // DMTC1
1591 else
1592 alloc_reg(current,i,rs1[i]); // MTC1/CTC1
1593 alloc_reg_temp(current,i,-1);
1594 }
1595 else {
1596 current->u&=~1LL;
1597 alloc_reg(current,i,0);
1598 alloc_reg_temp(current,i,-1);
1599 }
1600 }
e1190b87 1601 minimum_free_regs[i]=1;
57871462 1602}
1603void fconv_alloc(struct regstat *current,int i)
1604{
1605 alloc_reg(current,i,CSREG); // Load status
1606 alloc_reg_temp(current,i,-1);
e1190b87 1607 minimum_free_regs[i]=1;
57871462 1608}
1609void float_alloc(struct regstat *current,int i)
1610{
1611 alloc_reg(current,i,CSREG); // Load status
1612 alloc_reg_temp(current,i,-1);
e1190b87 1613 minimum_free_regs[i]=1;
57871462 1614}
b9b61529 1615void c2op_alloc(struct regstat *current,int i)
1616{
1617 alloc_reg_temp(current,i,-1);
1618}
57871462 1619void fcomp_alloc(struct regstat *current,int i)
1620{
1621 alloc_reg(current,i,CSREG); // Load status
1622 alloc_reg(current,i,FSREG); // Load flags
1623 dirty_reg(current,FSREG); // Flag will be modified
1624 alloc_reg_temp(current,i,-1);
e1190b87 1625 minimum_free_regs[i]=1;
57871462 1626}
1627
1628void syscall_alloc(struct regstat *current,int i)
1629{
1630 alloc_cc(current,i);
1631 dirty_reg(current,CCREG);
1632 alloc_all(current,i);
e1190b87 1633 minimum_free_regs[i]=HOST_REGS;
57871462 1634 current->isconst=0;
1635}
1636
1637void delayslot_alloc(struct regstat *current,int i)
1638{
1639 switch(itype[i]) {
1640 case UJUMP:
1641 case CJUMP:
1642 case SJUMP:
1643 case RJUMP:
1644 case FJUMP:
1645 case SYSCALL:
7139f3c8 1646 case HLECALL:
57871462 1647 case SPAN:
1648 assem_debug("jump in the delay slot. this shouldn't happen.\n");//exit(1);
c43b5311 1649 SysPrintf("Disabled speculative precompilation\n");
57871462 1650 stop_after_jal=1;
1651 break;
1652 case IMM16:
1653 imm16_alloc(current,i);
1654 break;
1655 case LOAD:
1656 case LOADLR:
1657 load_alloc(current,i);
1658 break;
1659 case STORE:
1660 case STORELR:
1661 store_alloc(current,i);
1662 break;
1663 case ALU:
1664 alu_alloc(current,i);
1665 break;
1666 case SHIFT:
1667 shift_alloc(current,i);
1668 break;
1669 case MULTDIV:
1670 multdiv_alloc(current,i);
1671 break;
1672 case SHIFTIMM:
1673 shiftimm_alloc(current,i);
1674 break;
1675 case MOV:
1676 mov_alloc(current,i);
1677 break;
1678 case COP0:
1679 cop0_alloc(current,i);
1680 break;
1681 case COP1:
b9b61529 1682 case COP2:
57871462 1683 cop1_alloc(current,i);
1684 break;
1685 case C1LS:
1686 c1ls_alloc(current,i);
1687 break;
b9b61529 1688 case C2LS:
1689 c2ls_alloc(current,i);
1690 break;
57871462 1691 case FCONV:
1692 fconv_alloc(current,i);
1693 break;
1694 case FLOAT:
1695 float_alloc(current,i);
1696 break;
1697 case FCOMP:
1698 fcomp_alloc(current,i);
1699 break;
b9b61529 1700 case C2OP:
1701 c2op_alloc(current,i);
1702 break;
57871462 1703 }
1704}
1705
1706// Special case where a branch and delay slot span two pages in virtual memory
1707static void pagespan_alloc(struct regstat *current,int i)
1708{
1709 current->isconst=0;
1710 current->wasconst=0;
1711 regs[i].wasconst=0;
e1190b87 1712 minimum_free_regs[i]=HOST_REGS;
57871462 1713 alloc_all(current,i);
1714 alloc_cc(current,i);
1715 dirty_reg(current,CCREG);
1716 if(opcode[i]==3) // JAL
1717 {
1718 alloc_reg(current,i,31);
1719 dirty_reg(current,31);
1720 }
1721 if(opcode[i]==0&&(opcode2[i]&0x3E)==8) // JR/JALR
1722 {
1723 alloc_reg(current,i,rs1[i]);
5067f341 1724 if (rt1[i]!=0) {
1725 alloc_reg(current,i,rt1[i]);
1726 dirty_reg(current,rt1[i]);
57871462 1727 }
1728 }
1729 if((opcode[i]&0x2E)==4) // BEQ/BNE/BEQL/BNEL
1730 {
1731 if(rs1[i]) alloc_reg(current,i,rs1[i]);
1732 if(rs2[i]) alloc_reg(current,i,rs2[i]);
1733 if(!((current->is32>>rs1[i])&(current->is32>>rs2[i])&1))
1734 {
1735 if(rs1[i]) alloc_reg64(current,i,rs1[i]);
1736 if(rs2[i]) alloc_reg64(current,i,rs2[i]);
1737 }
1738 }
1739 else
1740 if((opcode[i]&0x2E)==6) // BLEZ/BGTZ/BLEZL/BGTZL
1741 {
1742 if(rs1[i]) alloc_reg(current,i,rs1[i]);
1743 if(!((current->is32>>rs1[i])&1))
1744 {
1745 if(rs1[i]) alloc_reg64(current,i,rs1[i]);
1746 }
1747 }
1748 else
1749 if(opcode[i]==0x11) // BC1
1750 {
1751 alloc_reg(current,i,FSREG);
1752 alloc_reg(current,i,CSREG);
1753 }
1754 //else ...
1755}
1756
e2b5e7aa 1757static void add_stub(int type,int addr,int retaddr,int a,int b,int c,int d,int e)
57871462 1758{
1759 stubs[stubcount][0]=type;
1760 stubs[stubcount][1]=addr;
1761 stubs[stubcount][2]=retaddr;
1762 stubs[stubcount][3]=a;
1763 stubs[stubcount][4]=b;
1764 stubs[stubcount][5]=c;
1765 stubs[stubcount][6]=d;
1766 stubs[stubcount][7]=e;
1767 stubcount++;
1768}
1769
1770// Write out a single register
1771void wb_register(signed char r,signed char regmap[],uint64_t dirty,uint64_t is32)
1772{
1773 int hr;
1774 for(hr=0;hr<HOST_REGS;hr++) {
1775 if(hr!=EXCLUDE_REG) {
1776 if((regmap[hr]&63)==r) {
1777 if((dirty>>hr)&1) {
1778 if(regmap[hr]<64) {
1779 emit_storereg(r,hr);
57871462 1780 }else{
1781 emit_storereg(r|64,hr);
1782 }
1783 }
1784 }
1785 }
1786 }
1787}
1788
1789int mchecksum()
1790{
1791 //if(!tracedebug) return 0;
1792 int i;
1793 int sum=0;
1794 for(i=0;i<2097152;i++) {
1795 unsigned int temp=sum;
1796 sum<<=1;
1797 sum|=(~temp)>>31;
1798 sum^=((u_int *)rdram)[i];
1799 }
1800 return sum;
1801}
1802int rchecksum()
1803{
1804 int i;
1805 int sum=0;
1806 for(i=0;i<64;i++)
1807 sum^=((u_int *)reg)[i];
1808 return sum;
1809}
57871462 1810void rlist()
1811{
1812 int i;
1813 printf("TRACE: ");
1814 for(i=0;i<32;i++)
1815 printf("r%d:%8x%8x ",i,((int *)(reg+i))[1],((int *)(reg+i))[0]);
1816 printf("\n");
57871462 1817}
1818
1819void enabletrace()
1820{
1821 tracedebug=1;
1822}
1823
1824void memdebug(int i)
1825{
1826 //printf("TRACE: count=%d next=%d (checksum %x) lo=%8x%8x\n",Count,next_interupt,mchecksum(),(int)(reg[LOREG]>>32),(int)reg[LOREG]);
1827 //printf("TRACE: count=%d next=%d (rchecksum %x)\n",Count,next_interupt,rchecksum());
1828 //rlist();
1829 //if(tracedebug) {
1830 //if(Count>=-2084597794) {
1831 if((signed int)Count>=-2084597794&&(signed int)Count<0) {
1832 //if(0) {
1833 printf("TRACE: count=%d next=%d (checksum %x)\n",Count,next_interupt,mchecksum());
1834 //printf("TRACE: count=%d next=%d (checksum %x) Status=%x\n",Count,next_interupt,mchecksum(),Status);
1835 //printf("TRACE: count=%d next=%d (checksum %x) hi=%8x%8x\n",Count,next_interupt,mchecksum(),(int)(reg[HIREG]>>32),(int)reg[HIREG]);
1836 rlist();
1837 #ifdef __i386__
1838 printf("TRACE: %x\n",(&i)[-1]);
1839 #endif
1840 #ifdef __arm__
1841 int j;
1842 printf("TRACE: %x \n",(&j)[10]);
1843 printf("TRACE: %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x\n",(&j)[1],(&j)[2],(&j)[3],(&j)[4],(&j)[5],(&j)[6],(&j)[7],(&j)[8],(&j)[9],(&j)[10],(&j)[11],(&j)[12],(&j)[13],(&j)[14],(&j)[15],(&j)[16],(&j)[17],(&j)[18],(&j)[19],(&j)[20]);
1844 #endif
1845 //fflush(stdout);
1846 }
1847 //printf("TRACE: %x\n",(&i)[-1]);
1848}
1849
57871462 1850void alu_assemble(int i,struct regstat *i_regs)
1851{
1852 if(opcode2[i]>=0x20&&opcode2[i]<=0x23) { // ADD/ADDU/SUB/SUBU
1853 if(rt1[i]) {
1854 signed char s1,s2,t;
1855 t=get_reg(i_regs->regmap,rt1[i]);
1856 if(t>=0) {
1857 s1=get_reg(i_regs->regmap,rs1[i]);
1858 s2=get_reg(i_regs->regmap,rs2[i]);
1859 if(rs1[i]&&rs2[i]) {
1860 assert(s1>=0);
1861 assert(s2>=0);
1862 if(opcode2[i]&2) emit_sub(s1,s2,t);
1863 else emit_add(s1,s2,t);
1864 }
1865 else if(rs1[i]) {
1866 if(s1>=0) emit_mov(s1,t);
1867 else emit_loadreg(rs1[i],t);
1868 }
1869 else if(rs2[i]) {
1870 if(s2>=0) {
1871 if(opcode2[i]&2) emit_neg(s2,t);
1872 else emit_mov(s2,t);
1873 }
1874 else {
1875 emit_loadreg(rs2[i],t);
1876 if(opcode2[i]&2) emit_neg(t,t);
1877 }
1878 }
1879 else emit_zeroreg(t);
1880 }
1881 }
1882 }
1883 if(opcode2[i]>=0x2c&&opcode2[i]<=0x2f) { // DADD/DADDU/DSUB/DSUBU
1884 if(rt1[i]) {
1885 signed char s1l,s2l,s1h,s2h,tl,th;
1886 tl=get_reg(i_regs->regmap,rt1[i]);
1887 th=get_reg(i_regs->regmap,rt1[i]|64);
1888 if(tl>=0) {
1889 s1l=get_reg(i_regs->regmap,rs1[i]);
1890 s2l=get_reg(i_regs->regmap,rs2[i]);
1891 s1h=get_reg(i_regs->regmap,rs1[i]|64);
1892 s2h=get_reg(i_regs->regmap,rs2[i]|64);
1893 if(rs1[i]&&rs2[i]) {
1894 assert(s1l>=0);
1895 assert(s2l>=0);
1896 if(opcode2[i]&2) emit_subs(s1l,s2l,tl);
1897 else emit_adds(s1l,s2l,tl);
1898 if(th>=0) {
1899 #ifdef INVERTED_CARRY
1900 if(opcode2[i]&2) {if(s1h!=th) emit_mov(s1h,th);emit_sbb(th,s2h);}
1901 #else
1902 if(opcode2[i]&2) emit_sbc(s1h,s2h,th);
1903 #endif
1904 else emit_add(s1h,s2h,th);
1905 }
1906 }
1907 else if(rs1[i]) {
1908 if(s1l>=0) emit_mov(s1l,tl);
1909 else emit_loadreg(rs1[i],tl);
1910 if(th>=0) {
1911 if(s1h>=0) emit_mov(s1h,th);
1912 else emit_loadreg(rs1[i]|64,th);
1913 }
1914 }
1915 else if(rs2[i]) {
1916 if(s2l>=0) {
1917 if(opcode2[i]&2) emit_negs(s2l,tl);
1918 else emit_mov(s2l,tl);
1919 }
1920 else {
1921 emit_loadreg(rs2[i],tl);
1922 if(opcode2[i]&2) emit_negs(tl,tl);
1923 }
1924 if(th>=0) {
1925 #ifdef INVERTED_CARRY
1926 if(s2h>=0) emit_mov(s2h,th);
1927 else emit_loadreg(rs2[i]|64,th);
1928 if(opcode2[i]&2) {
1929 emit_adcimm(-1,th); // x86 has inverted carry flag
1930 emit_not(th,th);
1931 }
1932 #else
1933 if(opcode2[i]&2) {
1934 if(s2h>=0) emit_rscimm(s2h,0,th);
1935 else {
1936 emit_loadreg(rs2[i]|64,th);
1937 emit_rscimm(th,0,th);
1938 }
1939 }else{
1940 if(s2h>=0) emit_mov(s2h,th);
1941 else emit_loadreg(rs2[i]|64,th);
1942 }
1943 #endif
1944 }
1945 }
1946 else {
1947 emit_zeroreg(tl);
1948 if(th>=0) emit_zeroreg(th);
1949 }
1950 }
1951 }
1952 }
1953 if(opcode2[i]==0x2a||opcode2[i]==0x2b) { // SLT/SLTU
1954 if(rt1[i]) {
1955 signed char s1l,s1h,s2l,s2h,t;
1956 if(!((i_regs->was32>>rs1[i])&(i_regs->was32>>rs2[i])&1))
1957 {
1958 t=get_reg(i_regs->regmap,rt1[i]);
1959 //assert(t>=0);
1960 if(t>=0) {
1961 s1l=get_reg(i_regs->regmap,rs1[i]);
1962 s1h=get_reg(i_regs->regmap,rs1[i]|64);
1963 s2l=get_reg(i_regs->regmap,rs2[i]);
1964 s2h=get_reg(i_regs->regmap,rs2[i]|64);
1965 if(rs2[i]==0) // rx<r0
1966 {
1967 assert(s1h>=0);
1968 if(opcode2[i]==0x2a) // SLT
1969 emit_shrimm(s1h,31,t);
1970 else // SLTU (unsigned can not be less than zero)
1971 emit_zeroreg(t);
1972 }
1973 else if(rs1[i]==0) // r0<rx
1974 {
1975 assert(s2h>=0);
1976 if(opcode2[i]==0x2a) // SLT
1977 emit_set_gz64_32(s2h,s2l,t);
1978 else // SLTU (set if not zero)
1979 emit_set_nz64_32(s2h,s2l,t);
1980 }
1981 else {
1982 assert(s1l>=0);assert(s1h>=0);
1983 assert(s2l>=0);assert(s2h>=0);
1984 if(opcode2[i]==0x2a) // SLT
1985 emit_set_if_less64_32(s1h,s1l,s2h,s2l,t);
1986 else // SLTU
1987 emit_set_if_carry64_32(s1h,s1l,s2h,s2l,t);
1988 }
1989 }
1990 } else {
1991 t=get_reg(i_regs->regmap,rt1[i]);
1992 //assert(t>=0);
1993 if(t>=0) {
1994 s1l=get_reg(i_regs->regmap,rs1[i]);
1995 s2l=get_reg(i_regs->regmap,rs2[i]);
1996 if(rs2[i]==0) // rx<r0
1997 {
1998 assert(s1l>=0);
1999 if(opcode2[i]==0x2a) // SLT
2000 emit_shrimm(s1l,31,t);
2001 else // SLTU (unsigned can not be less than zero)
2002 emit_zeroreg(t);
2003 }
2004 else if(rs1[i]==0) // r0<rx
2005 {
2006 assert(s2l>=0);
2007 if(opcode2[i]==0x2a) // SLT
2008 emit_set_gz32(s2l,t);
2009 else // SLTU (set if not zero)
2010 emit_set_nz32(s2l,t);
2011 }
2012 else{
2013 assert(s1l>=0);assert(s2l>=0);
2014 if(opcode2[i]==0x2a) // SLT
2015 emit_set_if_less32(s1l,s2l,t);
2016 else // SLTU
2017 emit_set_if_carry32(s1l,s2l,t);
2018 }
2019 }
2020 }
2021 }
2022 }
2023 if(opcode2[i]>=0x24&&opcode2[i]<=0x27) { // AND/OR/XOR/NOR
2024 if(rt1[i]) {
2025 signed char s1l,s1h,s2l,s2h,th,tl;
2026 tl=get_reg(i_regs->regmap,rt1[i]);
2027 th=get_reg(i_regs->regmap,rt1[i]|64);
2028 if(!((i_regs->was32>>rs1[i])&(i_regs->was32>>rs2[i])&1)&&th>=0)
2029 {
2030 assert(tl>=0);
2031 if(tl>=0) {
2032 s1l=get_reg(i_regs->regmap,rs1[i]);
2033 s1h=get_reg(i_regs->regmap,rs1[i]|64);
2034 s2l=get_reg(i_regs->regmap,rs2[i]);
2035 s2h=get_reg(i_regs->regmap,rs2[i]|64);
2036 if(rs1[i]&&rs2[i]) {
2037 assert(s1l>=0);assert(s1h>=0);
2038 assert(s2l>=0);assert(s2h>=0);
2039 if(opcode2[i]==0x24) { // AND
2040 emit_and(s1l,s2l,tl);
2041 emit_and(s1h,s2h,th);
2042 } else
2043 if(opcode2[i]==0x25) { // OR
2044 emit_or(s1l,s2l,tl);
2045 emit_or(s1h,s2h,th);
2046 } else
2047 if(opcode2[i]==0x26) { // XOR
2048 emit_xor(s1l,s2l,tl);
2049 emit_xor(s1h,s2h,th);
2050 } else
2051 if(opcode2[i]==0x27) { // NOR
2052 emit_or(s1l,s2l,tl);
2053 emit_or(s1h,s2h,th);
2054 emit_not(tl,tl);
2055 emit_not(th,th);
2056 }
2057 }
2058 else
2059 {
2060 if(opcode2[i]==0x24) { // AND
2061 emit_zeroreg(tl);
2062 emit_zeroreg(th);
2063 } else
2064 if(opcode2[i]==0x25||opcode2[i]==0x26) { // OR/XOR
2065 if(rs1[i]){
2066 if(s1l>=0) emit_mov(s1l,tl);
2067 else emit_loadreg(rs1[i],tl);
2068 if(s1h>=0) emit_mov(s1h,th);
2069 else emit_loadreg(rs1[i]|64,th);
2070 }
2071 else
2072 if(rs2[i]){
2073 if(s2l>=0) emit_mov(s2l,tl);
2074 else emit_loadreg(rs2[i],tl);
2075 if(s2h>=0) emit_mov(s2h,th);
2076 else emit_loadreg(rs2[i]|64,th);
2077 }
2078 else{
2079 emit_zeroreg(tl);
2080 emit_zeroreg(th);
2081 }
2082 } else
2083 if(opcode2[i]==0x27) { // NOR
2084 if(rs1[i]){
2085 if(s1l>=0) emit_not(s1l,tl);
2086 else{
2087 emit_loadreg(rs1[i],tl);
2088 emit_not(tl,tl);
2089 }
2090 if(s1h>=0) emit_not(s1h,th);
2091 else{
2092 emit_loadreg(rs1[i]|64,th);
2093 emit_not(th,th);
2094 }
2095 }
2096 else
2097 if(rs2[i]){
2098 if(s2l>=0) emit_not(s2l,tl);
2099 else{
2100 emit_loadreg(rs2[i],tl);
2101 emit_not(tl,tl);
2102 }
2103 if(s2h>=0) emit_not(s2h,th);
2104 else{
2105 emit_loadreg(rs2[i]|64,th);
2106 emit_not(th,th);
2107 }
2108 }
2109 else {
2110 emit_movimm(-1,tl);
2111 emit_movimm(-1,th);
2112 }
2113 }
2114 }
2115 }
2116 }
2117 else
2118 {
2119 // 32 bit
2120 if(tl>=0) {
2121 s1l=get_reg(i_regs->regmap,rs1[i]);
2122 s2l=get_reg(i_regs->regmap,rs2[i]);
2123 if(rs1[i]&&rs2[i]) {
2124 assert(s1l>=0);
2125 assert(s2l>=0);
2126 if(opcode2[i]==0x24) { // AND
2127 emit_and(s1l,s2l,tl);
2128 } else
2129 if(opcode2[i]==0x25) { // OR
2130 emit_or(s1l,s2l,tl);
2131 } else
2132 if(opcode2[i]==0x26) { // XOR
2133 emit_xor(s1l,s2l,tl);
2134 } else
2135 if(opcode2[i]==0x27) { // NOR
2136 emit_or(s1l,s2l,tl);
2137 emit_not(tl,tl);
2138 }
2139 }
2140 else
2141 {
2142 if(opcode2[i]==0x24) { // AND
2143 emit_zeroreg(tl);
2144 } else
2145 if(opcode2[i]==0x25||opcode2[i]==0x26) { // OR/XOR
2146 if(rs1[i]){
2147 if(s1l>=0) emit_mov(s1l,tl);
2148 else emit_loadreg(rs1[i],tl); // CHECK: regmap_entry?
2149 }
2150 else
2151 if(rs2[i]){
2152 if(s2l>=0) emit_mov(s2l,tl);
2153 else emit_loadreg(rs2[i],tl); // CHECK: regmap_entry?
2154 }
2155 else emit_zeroreg(tl);
2156 } else
2157 if(opcode2[i]==0x27) { // NOR
2158 if(rs1[i]){
2159 if(s1l>=0) emit_not(s1l,tl);
2160 else {
2161 emit_loadreg(rs1[i],tl);
2162 emit_not(tl,tl);
2163 }
2164 }
2165 else
2166 if(rs2[i]){
2167 if(s2l>=0) emit_not(s2l,tl);
2168 else {
2169 emit_loadreg(rs2[i],tl);
2170 emit_not(tl,tl);
2171 }
2172 }
2173 else emit_movimm(-1,tl);
2174 }
2175 }
2176 }
2177 }
2178 }
2179 }
2180}
2181
2182void imm16_assemble(int i,struct regstat *i_regs)
2183{
2184 if (opcode[i]==0x0f) { // LUI
2185 if(rt1[i]) {
2186 signed char t;
2187 t=get_reg(i_regs->regmap,rt1[i]);
2188 //assert(t>=0);
2189 if(t>=0) {
2190 if(!((i_regs->isconst>>t)&1))
2191 emit_movimm(imm[i]<<16,t);
2192 }
2193 }
2194 }
2195 if(opcode[i]==0x08||opcode[i]==0x09) { // ADDI/ADDIU
2196 if(rt1[i]) {
2197 signed char s,t;
2198 t=get_reg(i_regs->regmap,rt1[i]);
2199 s=get_reg(i_regs->regmap,rs1[i]);
2200 if(rs1[i]) {
2201 //assert(t>=0);
2202 //assert(s>=0);
2203 if(t>=0) {
2204 if(!((i_regs->isconst>>t)&1)) {
2205 if(s<0) {
2206 if(i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2207 emit_addimm(t,imm[i],t);
2208 }else{
2209 if(!((i_regs->wasconst>>s)&1))
2210 emit_addimm(s,imm[i],t);
2211 else
2212 emit_movimm(constmap[i][s]+imm[i],t);
2213 }
2214 }
2215 }
2216 } else {
2217 if(t>=0) {
2218 if(!((i_regs->isconst>>t)&1))
2219 emit_movimm(imm[i],t);
2220 }
2221 }
2222 }
2223 }
2224 if(opcode[i]==0x18||opcode[i]==0x19) { // DADDI/DADDIU
2225 if(rt1[i]) {
2226 signed char sh,sl,th,tl;
2227 th=get_reg(i_regs->regmap,rt1[i]|64);
2228 tl=get_reg(i_regs->regmap,rt1[i]);
2229 sh=get_reg(i_regs->regmap,rs1[i]|64);
2230 sl=get_reg(i_regs->regmap,rs1[i]);
2231 if(tl>=0) {
2232 if(rs1[i]) {
2233 assert(sh>=0);
2234 assert(sl>=0);
2235 if(th>=0) {
2236 emit_addimm64_32(sh,sl,imm[i],th,tl);
2237 }
2238 else {
2239 emit_addimm(sl,imm[i],tl);
2240 }
2241 } else {
2242 emit_movimm(imm[i],tl);
2243 if(th>=0) emit_movimm(((signed int)imm[i])>>31,th);
2244 }
2245 }
2246 }
2247 }
2248 else if(opcode[i]==0x0a||opcode[i]==0x0b) { // SLTI/SLTIU
2249 if(rt1[i]) {
2250 //assert(rs1[i]!=0); // r0 might be valid, but it's probably a bug
2251 signed char sh,sl,t;
2252 t=get_reg(i_regs->regmap,rt1[i]);
2253 sh=get_reg(i_regs->regmap,rs1[i]|64);
2254 sl=get_reg(i_regs->regmap,rs1[i]);
2255 //assert(t>=0);
2256 if(t>=0) {
2257 if(rs1[i]>0) {
2258 if(sh<0) assert((i_regs->was32>>rs1[i])&1);
2259 if(sh<0||((i_regs->was32>>rs1[i])&1)) {
2260 if(opcode[i]==0x0a) { // SLTI
2261 if(sl<0) {
2262 if(i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2263 emit_slti32(t,imm[i],t);
2264 }else{
2265 emit_slti32(sl,imm[i],t);
2266 }
2267 }
2268 else { // SLTIU
2269 if(sl<0) {
2270 if(i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2271 emit_sltiu32(t,imm[i],t);
2272 }else{
2273 emit_sltiu32(sl,imm[i],t);
2274 }
2275 }
2276 }else{ // 64-bit
2277 assert(sl>=0);
2278 if(opcode[i]==0x0a) // SLTI
2279 emit_slti64_32(sh,sl,imm[i],t);
2280 else // SLTIU
2281 emit_sltiu64_32(sh,sl,imm[i],t);
2282 }
2283 }else{
2284 // SLTI(U) with r0 is just stupid,
2285 // nonetheless examples can be found
2286 if(opcode[i]==0x0a) // SLTI
2287 if(0<imm[i]) emit_movimm(1,t);
2288 else emit_zeroreg(t);
2289 else // SLTIU
2290 {
2291 if(imm[i]) emit_movimm(1,t);
2292 else emit_zeroreg(t);
2293 }
2294 }
2295 }
2296 }
2297 }
2298 else if(opcode[i]>=0x0c&&opcode[i]<=0x0e) { // ANDI/ORI/XORI
2299 if(rt1[i]) {
2300 signed char sh,sl,th,tl;
2301 th=get_reg(i_regs->regmap,rt1[i]|64);
2302 tl=get_reg(i_regs->regmap,rt1[i]);
2303 sh=get_reg(i_regs->regmap,rs1[i]|64);
2304 sl=get_reg(i_regs->regmap,rs1[i]);
2305 if(tl>=0 && !((i_regs->isconst>>tl)&1)) {
2306 if(opcode[i]==0x0c) //ANDI
2307 {
2308 if(rs1[i]) {
2309 if(sl<0) {
2310 if(i_regs->regmap_entry[tl]!=rs1[i]) emit_loadreg(rs1[i],tl);
2311 emit_andimm(tl,imm[i],tl);
2312 }else{
2313 if(!((i_regs->wasconst>>sl)&1))
2314 emit_andimm(sl,imm[i],tl);
2315 else
2316 emit_movimm(constmap[i][sl]&imm[i],tl);
2317 }
2318 }
2319 else
2320 emit_zeroreg(tl);
2321 if(th>=0) emit_zeroreg(th);
2322 }
2323 else
2324 {
2325 if(rs1[i]) {
2326 if(sl<0) {
2327 if(i_regs->regmap_entry[tl]!=rs1[i]) emit_loadreg(rs1[i],tl);
2328 }
2329 if(th>=0) {
2330 if(sh<0) {
2331 emit_loadreg(rs1[i]|64,th);
2332 }else{
2333 emit_mov(sh,th);
2334 }
2335 }
2336 if(opcode[i]==0x0d) //ORI
2337 if(sl<0) {
2338 emit_orimm(tl,imm[i],tl);
2339 }else{
2340 if(!((i_regs->wasconst>>sl)&1))
2341 emit_orimm(sl,imm[i],tl);
2342 else
2343 emit_movimm(constmap[i][sl]|imm[i],tl);
2344 }
2345 if(opcode[i]==0x0e) //XORI
2346 if(sl<0) {
2347 emit_xorimm(tl,imm[i],tl);
2348 }else{
2349 if(!((i_regs->wasconst>>sl)&1))
2350 emit_xorimm(sl,imm[i],tl);
2351 else
2352 emit_movimm(constmap[i][sl]^imm[i],tl);
2353 }
2354 }
2355 else {
2356 emit_movimm(imm[i],tl);
2357 if(th>=0) emit_zeroreg(th);
2358 }
2359 }
2360 }
2361 }
2362 }
2363}
2364
2365void shiftimm_assemble(int i,struct regstat *i_regs)
2366{
2367 if(opcode2[i]<=0x3) // SLL/SRL/SRA
2368 {
2369 if(rt1[i]) {
2370 signed char s,t;
2371 t=get_reg(i_regs->regmap,rt1[i]);
2372 s=get_reg(i_regs->regmap,rs1[i]);
2373 //assert(t>=0);
dc49e339 2374 if(t>=0&&!((i_regs->isconst>>t)&1)){
57871462 2375 if(rs1[i]==0)
2376 {
2377 emit_zeroreg(t);
2378 }
2379 else
2380 {
2381 if(s<0&&i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2382 if(imm[i]) {
2383 if(opcode2[i]==0) // SLL
2384 {
2385 emit_shlimm(s<0?t:s,imm[i],t);
2386 }
2387 if(opcode2[i]==2) // SRL
2388 {
2389 emit_shrimm(s<0?t:s,imm[i],t);
2390 }
2391 if(opcode2[i]==3) // SRA
2392 {
2393 emit_sarimm(s<0?t:s,imm[i],t);
2394 }
2395 }else{
2396 // Shift by zero
2397 if(s>=0 && s!=t) emit_mov(s,t);
2398 }
2399 }
2400 }
2401 //emit_storereg(rt1[i],t); //DEBUG
2402 }
2403 }
2404 if(opcode2[i]>=0x38&&opcode2[i]<=0x3b) // DSLL/DSRL/DSRA
2405 {
2406 if(rt1[i]) {
2407 signed char sh,sl,th,tl;
2408 th=get_reg(i_regs->regmap,rt1[i]|64);
2409 tl=get_reg(i_regs->regmap,rt1[i]);
2410 sh=get_reg(i_regs->regmap,rs1[i]|64);
2411 sl=get_reg(i_regs->regmap,rs1[i]);
2412 if(tl>=0) {
2413 if(rs1[i]==0)
2414 {
2415 emit_zeroreg(tl);
2416 if(th>=0) emit_zeroreg(th);
2417 }
2418 else
2419 {
2420 assert(sl>=0);
2421 assert(sh>=0);
2422 if(imm[i]) {
2423 if(opcode2[i]==0x38) // DSLL
2424 {
2425 if(th>=0) emit_shldimm(sh,sl,imm[i],th);
2426 emit_shlimm(sl,imm[i],tl);
2427 }
2428 if(opcode2[i]==0x3a) // DSRL
2429 {
2430 emit_shrdimm(sl,sh,imm[i],tl);
2431 if(th>=0) emit_shrimm(sh,imm[i],th);
2432 }
2433 if(opcode2[i]==0x3b) // DSRA
2434 {
2435 emit_shrdimm(sl,sh,imm[i],tl);
2436 if(th>=0) emit_sarimm(sh,imm[i],th);
2437 }
2438 }else{
2439 // Shift by zero
2440 if(sl!=tl) emit_mov(sl,tl);
2441 if(th>=0&&sh!=th) emit_mov(sh,th);
2442 }
2443 }
2444 }
2445 }
2446 }
2447 if(opcode2[i]==0x3c) // DSLL32
2448 {
2449 if(rt1[i]) {
2450 signed char sl,tl,th;
2451 tl=get_reg(i_regs->regmap,rt1[i]);
2452 th=get_reg(i_regs->regmap,rt1[i]|64);
2453 sl=get_reg(i_regs->regmap,rs1[i]);
2454 if(th>=0||tl>=0){
2455 assert(tl>=0);
2456 assert(th>=0);
2457 assert(sl>=0);
2458 emit_mov(sl,th);
2459 emit_zeroreg(tl);
2460 if(imm[i]>32)
2461 {
2462 emit_shlimm(th,imm[i]&31,th);
2463 }
2464 }
2465 }
2466 }
2467 if(opcode2[i]==0x3e) // DSRL32
2468 {
2469 if(rt1[i]) {
2470 signed char sh,tl,th;
2471 tl=get_reg(i_regs->regmap,rt1[i]);
2472 th=get_reg(i_regs->regmap,rt1[i]|64);
2473 sh=get_reg(i_regs->regmap,rs1[i]|64);
2474 if(tl>=0){
2475 assert(sh>=0);
2476 emit_mov(sh,tl);
2477 if(th>=0) emit_zeroreg(th);
2478 if(imm[i]>32)
2479 {
2480 emit_shrimm(tl,imm[i]&31,tl);
2481 }
2482 }
2483 }
2484 }
2485 if(opcode2[i]==0x3f) // DSRA32
2486 {
2487 if(rt1[i]) {
2488 signed char sh,tl;
2489 tl=get_reg(i_regs->regmap,rt1[i]);
2490 sh=get_reg(i_regs->regmap,rs1[i]|64);
2491 if(tl>=0){
2492 assert(sh>=0);
2493 emit_mov(sh,tl);
2494 if(imm[i]>32)
2495 {
2496 emit_sarimm(tl,imm[i]&31,tl);
2497 }
2498 }
2499 }
2500 }
2501}
2502
2503#ifndef shift_assemble
2504void shift_assemble(int i,struct regstat *i_regs)
2505{
2506 printf("Need shift_assemble for this architecture.\n");
2507 exit(1);
2508}
2509#endif
2510
2511void load_assemble(int i,struct regstat *i_regs)
2512{
2513 int s,th,tl,addr,map=-1;
2514 int offset;
2515 int jaddr=0;
5bf843dc 2516 int memtarget=0,c=0;
b1570849 2517 int fastload_reg_override=0;
57871462 2518 u_int hr,reglist=0;
2519 th=get_reg(i_regs->regmap,rt1[i]|64);
2520 tl=get_reg(i_regs->regmap,rt1[i]);
2521 s=get_reg(i_regs->regmap,rs1[i]);
2522 offset=imm[i];
2523 for(hr=0;hr<HOST_REGS;hr++) {
2524 if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
2525 }
2526 if(i_regs->regmap[HOST_CCREG]==CCREG) reglist&=~(1<<HOST_CCREG);
2527 if(s>=0) {
2528 c=(i_regs->wasconst>>s)&1;
af4ee1fe 2529 if (c) {
2530 memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
af4ee1fe 2531 }
57871462 2532 }
57871462 2533 //printf("load_assemble: c=%d\n",c);
2534 //if(c) printf("load_assemble: const=%x\n",(int)constmap[i][s]+offset);
2535 // FIXME: Even if the load is a NOP, we should check for pagefaults...
f18c0f46 2536 if(tl<0&&(!c||(((u_int)constmap[i][s]+offset)>>16)==0x1f80)
2537 ||rt1[i]==0) {
5bf843dc 2538 // could be FIFO, must perform the read
f18c0f46 2539 // ||dummy read
5bf843dc 2540 assem_debug("(forced read)\n");
2541 tl=get_reg(i_regs->regmap,-1);
2542 assert(tl>=0);
5bf843dc 2543 }
2544 if(offset||s<0||c) addr=tl;
2545 else addr=s;
535d208a 2546 //if(tl<0) tl=get_reg(i_regs->regmap,-1);
2547 if(tl>=0) {
2548 //printf("load_assemble: c=%d\n",c);
2549 //if(c) printf("load_assemble: const=%x\n",(int)constmap[i][s]+offset);
2550 assert(tl>=0); // Even if the load is a NOP, we must check for pagefaults and I/O
2551 reglist&=~(1<<tl);
2552 if(th>=0) reglist&=~(1<<th);
1edfcc68 2553 if(!c) {
2554 #ifdef RAM_OFFSET
2555 map=get_reg(i_regs->regmap,ROREG);
2556 if(map<0) emit_loadreg(ROREG,map=HOST_TEMPREG);
2557 #endif
2558 #ifdef R29_HACK
2559 // Strmnnrmn's speed hack
2560 if(rs1[i]!=29||start<0x80001000||start>=0x80000000+RAM_SIZE)
2561 #endif
2562 {
2563 jaddr=emit_fastpath_cmp_jump(i,addr,&fastload_reg_override);
535d208a 2564 }
1edfcc68 2565 }
2566 else if(ram_offset&&memtarget) {
2567 emit_addimm(addr,ram_offset,HOST_TEMPREG);
2568 fastload_reg_override=HOST_TEMPREG;
535d208a 2569 }
2570 int dummy=(rt1[i]==0)||(tl!=get_reg(i_regs->regmap,rt1[i])); // ignore loads to r0 and unneeded reg
2571 if (opcode[i]==0x20) { // LB
2572 if(!c||memtarget) {
2573 if(!dummy) {
57871462 2574 #ifdef HOST_IMM_ADDR32
2575 if(c)
2576 emit_movsbl_tlb((constmap[i][s]+offset)^3,map,tl);
2577 else
2578 #endif
2579 {
2580 //emit_xorimm(addr,3,tl);
57871462 2581 //emit_movsbl_indexed((int)rdram-0x80000000,tl,tl);
535d208a 2582 int x=0,a=tl;
2002a1db 2583#ifdef BIG_ENDIAN_MIPS
57871462 2584 if(!c) emit_xorimm(addr,3,tl);
2585 else x=((constmap[i][s]+offset)^3)-(constmap[i][s]+offset);
2002a1db 2586#else
535d208a 2587 if(!c) a=addr;
dadf55f2 2588#endif
b1570849 2589 if(fastload_reg_override) a=fastload_reg_override;
2590
535d208a 2591 emit_movsbl_indexed_tlb(x,a,map,tl);
57871462 2592 }
57871462 2593 }
535d208a 2594 if(jaddr)
2595 add_stub(LOADB_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
57871462 2596 }
535d208a 2597 else
2598 inline_readstub(LOADB_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2599 }
2600 if (opcode[i]==0x21) { // LH
2601 if(!c||memtarget) {
2602 if(!dummy) {
57871462 2603 #ifdef HOST_IMM_ADDR32
2604 if(c)
2605 emit_movswl_tlb((constmap[i][s]+offset)^2,map,tl);
2606 else
2607 #endif
2608 {
535d208a 2609 int x=0,a=tl;
2002a1db 2610#ifdef BIG_ENDIAN_MIPS
57871462 2611 if(!c) emit_xorimm(addr,2,tl);
2612 else x=((constmap[i][s]+offset)^2)-(constmap[i][s]+offset);
2002a1db 2613#else
535d208a 2614 if(!c) a=addr;
dadf55f2 2615#endif
b1570849 2616 if(fastload_reg_override) a=fastload_reg_override;
57871462 2617 //#ifdef
2618 //emit_movswl_indexed_tlb(x,tl,map,tl);
2619 //else
2620 if(map>=0) {
535d208a 2621 emit_movswl_indexed(x,a,tl);
2622 }else{
a327ad27 2623 #if 1 //def RAM_OFFSET
535d208a 2624 emit_movswl_indexed(x,a,tl);
2625 #else
2626 emit_movswl_indexed((int)rdram-0x80000000+x,a,tl);
2627 #endif
2628 }
57871462 2629 }
57871462 2630 }
535d208a 2631 if(jaddr)
2632 add_stub(LOADH_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
57871462 2633 }
535d208a 2634 else
2635 inline_readstub(LOADH_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2636 }
2637 if (opcode[i]==0x23) { // LW
2638 if(!c||memtarget) {
2639 if(!dummy) {
dadf55f2 2640 int a=addr;
b1570849 2641 if(fastload_reg_override) a=fastload_reg_override;
57871462 2642 //emit_readword_indexed((int)rdram-0x80000000,addr,tl);
2643 #ifdef HOST_IMM_ADDR32
2644 if(c)
2645 emit_readword_tlb(constmap[i][s]+offset,map,tl);
2646 else
2647 #endif
dadf55f2 2648 emit_readword_indexed_tlb(0,a,map,tl);
57871462 2649 }
535d208a 2650 if(jaddr)
2651 add_stub(LOADW_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
57871462 2652 }
535d208a 2653 else
2654 inline_readstub(LOADW_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2655 }
2656 if (opcode[i]==0x24) { // LBU
2657 if(!c||memtarget) {
2658 if(!dummy) {
57871462 2659 #ifdef HOST_IMM_ADDR32
2660 if(c)
2661 emit_movzbl_tlb((constmap[i][s]+offset)^3,map,tl);
2662 else
2663 #endif
2664 {
2665 //emit_xorimm(addr,3,tl);
57871462 2666 //emit_movzbl_indexed((int)rdram-0x80000000,tl,tl);
535d208a 2667 int x=0,a=tl;
2002a1db 2668#ifdef BIG_ENDIAN_MIPS
57871462 2669 if(!c) emit_xorimm(addr,3,tl);
2670 else x=((constmap[i][s]+offset)^3)-(constmap[i][s]+offset);
2002a1db 2671#else
535d208a 2672 if(!c) a=addr;
dadf55f2 2673#endif
b1570849 2674 if(fastload_reg_override) a=fastload_reg_override;
2675
535d208a 2676 emit_movzbl_indexed_tlb(x,a,map,tl);
57871462 2677 }
57871462 2678 }
535d208a 2679 if(jaddr)
2680 add_stub(LOADBU_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
57871462 2681 }
535d208a 2682 else
2683 inline_readstub(LOADBU_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2684 }
2685 if (opcode[i]==0x25) { // LHU
2686 if(!c||memtarget) {
2687 if(!dummy) {
57871462 2688 #ifdef HOST_IMM_ADDR32
2689 if(c)
2690 emit_movzwl_tlb((constmap[i][s]+offset)^2,map,tl);
2691 else
2692 #endif
2693 {
535d208a 2694 int x=0,a=tl;
2002a1db 2695#ifdef BIG_ENDIAN_MIPS
57871462 2696 if(!c) emit_xorimm(addr,2,tl);
2697 else x=((constmap[i][s]+offset)^2)-(constmap[i][s]+offset);
2002a1db 2698#else
535d208a 2699 if(!c) a=addr;
dadf55f2 2700#endif
b1570849 2701 if(fastload_reg_override) a=fastload_reg_override;
57871462 2702 //#ifdef
2703 //emit_movzwl_indexed_tlb(x,tl,map,tl);
2704 //#else
2705 if(map>=0) {
535d208a 2706 emit_movzwl_indexed(x,a,tl);
2707 }else{
a327ad27 2708 #if 1 //def RAM_OFFSET
535d208a 2709 emit_movzwl_indexed(x,a,tl);
2710 #else
2711 emit_movzwl_indexed((int)rdram-0x80000000+x,a,tl);
2712 #endif
2713 }
57871462 2714 }
2715 }
535d208a 2716 if(jaddr)
2717 add_stub(LOADHU_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
57871462 2718 }
535d208a 2719 else
2720 inline_readstub(LOADHU_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2721 }
2722 if (opcode[i]==0x27) { // LWU
2723 assert(th>=0);
2724 if(!c||memtarget) {
2725 if(!dummy) {
dadf55f2 2726 int a=addr;
b1570849 2727 if(fastload_reg_override) a=fastload_reg_override;
57871462 2728 //emit_readword_indexed((int)rdram-0x80000000,addr,tl);
2729 #ifdef HOST_IMM_ADDR32
2730 if(c)
2731 emit_readword_tlb(constmap[i][s]+offset,map,tl);
2732 else
2733 #endif
dadf55f2 2734 emit_readword_indexed_tlb(0,a,map,tl);
57871462 2735 }
535d208a 2736 if(jaddr)
2737 add_stub(LOADW_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
2738 }
2739 else {
2740 inline_readstub(LOADW_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
57871462 2741 }
535d208a 2742 emit_zeroreg(th);
2743 }
2744 if (opcode[i]==0x37) { // LD
2745 if(!c||memtarget) {
2746 if(!dummy) {
dadf55f2 2747 int a=addr;
b1570849 2748 if(fastload_reg_override) a=fastload_reg_override;
57871462 2749 //if(th>=0) emit_readword_indexed((int)rdram-0x80000000,addr,th);
2750 //emit_readword_indexed((int)rdram-0x7FFFFFFC,addr,tl);
2751 #ifdef HOST_IMM_ADDR32
2752 if(c)
2753 emit_readdword_tlb(constmap[i][s]+offset,map,th,tl);
2754 else
2755 #endif
dadf55f2 2756 emit_readdword_indexed_tlb(0,a,map,th,tl);
57871462 2757 }
535d208a 2758 if(jaddr)
2759 add_stub(LOADD_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
57871462 2760 }
535d208a 2761 else
2762 inline_readstub(LOADD_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
57871462 2763 }
535d208a 2764 }
2765 //emit_storereg(rt1[i],tl); // DEBUG
57871462 2766 //if(opcode[i]==0x23)
2767 //if(opcode[i]==0x24)
2768 //if(opcode[i]==0x23||opcode[i]==0x24)
2769 /*if(opcode[i]==0x21||opcode[i]==0x23||opcode[i]==0x24)
2770 {
2771 //emit_pusha();
2772 save_regs(0x100f);
2773 emit_readword((int)&last_count,ECX);
2774 #ifdef __i386__
2775 if(get_reg(i_regs->regmap,CCREG)<0)
2776 emit_loadreg(CCREG,HOST_CCREG);
2777 emit_add(HOST_CCREG,ECX,HOST_CCREG);
2778 emit_addimm(HOST_CCREG,2*ccadj[i],HOST_CCREG);
2779 emit_writeword(HOST_CCREG,(int)&Count);
2780 #endif
2781 #ifdef __arm__
2782 if(get_reg(i_regs->regmap,CCREG)<0)
2783 emit_loadreg(CCREG,0);
2784 else
2785 emit_mov(HOST_CCREG,0);
2786 emit_add(0,ECX,0);
2787 emit_addimm(0,2*ccadj[i],0);
2788 emit_writeword(0,(int)&Count);
2789 #endif
2790 emit_call((int)memdebug);
2791 //emit_popa();
2792 restore_regs(0x100f);
2793 }/**/
2794}
2795
2796#ifndef loadlr_assemble
2797void loadlr_assemble(int i,struct regstat *i_regs)
2798{
2799 printf("Need loadlr_assemble for this architecture.\n");
2800 exit(1);
2801}
2802#endif
2803
2804void store_assemble(int i,struct regstat *i_regs)
2805{
2806 int s,th,tl,map=-1;
2807 int addr,temp;
2808 int offset;
2809 int jaddr=0,jaddr2,type;
666a299d 2810 int memtarget=0,c=0;
57871462 2811 int agr=AGEN1+(i&1);
b1570849 2812 int faststore_reg_override=0;
57871462 2813 u_int hr,reglist=0;
2814 th=get_reg(i_regs->regmap,rs2[i]|64);
2815 tl=get_reg(i_regs->regmap,rs2[i]);
2816 s=get_reg(i_regs->regmap,rs1[i]);
2817 temp=get_reg(i_regs->regmap,agr);
2818 if(temp<0) temp=get_reg(i_regs->regmap,-1);
2819 offset=imm[i];
2820 if(s>=0) {
2821 c=(i_regs->wasconst>>s)&1;
af4ee1fe 2822 if(c) {
2823 memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
af4ee1fe 2824 }
57871462 2825 }
2826 assert(tl>=0);
2827 assert(temp>=0);
2828 for(hr=0;hr<HOST_REGS;hr++) {
2829 if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
2830 }
2831 if(i_regs->regmap[HOST_CCREG]==CCREG) reglist&=~(1<<HOST_CCREG);
2832 if(offset||s<0||c) addr=temp;
2833 else addr=s;
1edfcc68 2834 if(!c) {
2835 jaddr=emit_fastpath_cmp_jump(i,addr,&faststore_reg_override);
2836 }
2837 else if(ram_offset&&memtarget) {
2838 emit_addimm(addr,ram_offset,HOST_TEMPREG);
2839 faststore_reg_override=HOST_TEMPREG;
57871462 2840 }
2841
2842 if (opcode[i]==0x28) { // SB
2843 if(!c||memtarget) {
97a238a6 2844 int x=0,a=temp;
2002a1db 2845#ifdef BIG_ENDIAN_MIPS
57871462 2846 if(!c) emit_xorimm(addr,3,temp);
2847 else x=((constmap[i][s]+offset)^3)-(constmap[i][s]+offset);
2002a1db 2848#else
97a238a6 2849 if(!c) a=addr;
dadf55f2 2850#endif
b1570849 2851 if(faststore_reg_override) a=faststore_reg_override;
57871462 2852 //emit_writebyte_indexed(tl,(int)rdram-0x80000000,temp);
97a238a6 2853 emit_writebyte_indexed_tlb(tl,x,a,map,a);
57871462 2854 }
2855 type=STOREB_STUB;
2856 }
2857 if (opcode[i]==0x29) { // SH
2858 if(!c||memtarget) {
97a238a6 2859 int x=0,a=temp;
2002a1db 2860#ifdef BIG_ENDIAN_MIPS
57871462 2861 if(!c) emit_xorimm(addr,2,temp);
2862 else x=((constmap[i][s]+offset)^2)-(constmap[i][s]+offset);
2002a1db 2863#else
97a238a6 2864 if(!c) a=addr;
dadf55f2 2865#endif
b1570849 2866 if(faststore_reg_override) a=faststore_reg_override;
57871462 2867 //#ifdef
2868 //emit_writehword_indexed_tlb(tl,x,temp,map,temp);
2869 //#else
2870 if(map>=0) {
97a238a6 2871 emit_writehword_indexed(tl,x,a);
57871462 2872 }else
a327ad27 2873 //emit_writehword_indexed(tl,(int)rdram-0x80000000+x,a);
2874 emit_writehword_indexed(tl,x,a);
57871462 2875 }
2876 type=STOREH_STUB;
2877 }
2878 if (opcode[i]==0x2B) { // SW
dadf55f2 2879 if(!c||memtarget) {
2880 int a=addr;
b1570849 2881 if(faststore_reg_override) a=faststore_reg_override;
57871462 2882 //emit_writeword_indexed(tl,(int)rdram-0x80000000,addr);
dadf55f2 2883 emit_writeword_indexed_tlb(tl,0,a,map,temp);
2884 }
57871462 2885 type=STOREW_STUB;
2886 }
2887 if (opcode[i]==0x3F) { // SD
2888 if(!c||memtarget) {
dadf55f2 2889 int a=addr;
b1570849 2890 if(faststore_reg_override) a=faststore_reg_override;
57871462 2891 if(rs2[i]) {
2892 assert(th>=0);
2893 //emit_writeword_indexed(th,(int)rdram-0x80000000,addr);
2894 //emit_writeword_indexed(tl,(int)rdram-0x7FFFFFFC,addr);
dadf55f2 2895 emit_writedword_indexed_tlb(th,tl,0,a,map,temp);
57871462 2896 }else{
2897 // Store zero
2898 //emit_writeword_indexed(tl,(int)rdram-0x80000000,temp);
2899 //emit_writeword_indexed(tl,(int)rdram-0x7FFFFFFC,temp);
dadf55f2 2900 emit_writedword_indexed_tlb(tl,tl,0,a,map,temp);
57871462 2901 }
2902 }
2903 type=STORED_STUB;
2904 }
b96d3df7 2905 if(jaddr) {
2906 // PCSX store handlers don't check invcode again
2907 reglist|=1<<addr;
2908 add_stub(type,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
2909 jaddr=0;
2910 }
1edfcc68 2911 if(!(i_regs->waswritten&(1<<rs1[i]))&&!(new_dynarec_hacks&NDHACK_NO_SMC_CHECK)) {
57871462 2912 if(!c||memtarget) {
2913 #ifdef DESTRUCTIVE_SHIFT
2914 // The x86 shift operation is 'destructive'; it overwrites the
2915 // source register, so we need to make a copy first and use that.
2916 addr=temp;
2917 #endif
2918 #if defined(HOST_IMM8)
2919 int ir=get_reg(i_regs->regmap,INVCP);
2920 assert(ir>=0);
2921 emit_cmpmem_indexedsr12_reg(ir,addr,1);
2922 #else
2923 emit_cmpmem_indexedsr12_imm((int)invalid_code,addr,1);
2924 #endif
0bbd1454 2925 #if defined(HAVE_CONDITIONAL_CALL) && !defined(DESTRUCTIVE_SHIFT)
2926 emit_callne(invalidate_addr_reg[addr]);
2927 #else
57871462 2928 jaddr2=(int)out;
2929 emit_jne(0);
2930 add_stub(INVCODE_STUB,jaddr2,(int)out,reglist|(1<<HOST_CCREG),addr,0,0,0);
0bbd1454 2931 #endif
57871462 2932 }
2933 }
7a518516 2934 u_int addr_val=constmap[i][s]+offset;
3eaa7048 2935 if(jaddr) {
2936 add_stub(type,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
2937 } else if(c&&!memtarget) {
7a518516 2938 inline_writestub(type,i,addr_val,i_regs->regmap,rs2[i],ccadj[i],reglist);
2939 }
2940 // basic current block modification detection..
2941 // not looking back as that should be in mips cache already
2942 if(c&&start+i*4<addr_val&&addr_val<start+slen*4) {
c43b5311 2943 SysPrintf("write to %08x hits block %08x, pc=%08x\n",addr_val,start,start+i*4);
7a518516 2944 assert(i_regs->regmap==regs[i].regmap); // not delay slot
2945 if(i_regs->regmap==regs[i].regmap) {
2946 load_all_consts(regs[i].regmap_entry,regs[i].was32,regs[i].wasdirty,i);
2947 wb_dirtys(regs[i].regmap_entry,regs[i].was32,regs[i].wasdirty);
2948 emit_movimm(start+i*4+4,0);
2949 emit_writeword(0,(int)&pcaddr);
2950 emit_jmp((int)do_interrupt);
2951 }
3eaa7048 2952 }
57871462 2953 //if(opcode[i]==0x2B || opcode[i]==0x3F)
2954 //if(opcode[i]==0x2B || opcode[i]==0x28)
2955 //if(opcode[i]==0x2B || opcode[i]==0x29)
2956 //if(opcode[i]==0x2B)
2957 /*if(opcode[i]==0x2B || opcode[i]==0x28 || opcode[i]==0x29 || opcode[i]==0x3F)
2958 {
28d74ee8 2959 #ifdef __i386__
2960 emit_pusha();
2961 #endif
2962 #ifdef __arm__
57871462 2963 save_regs(0x100f);
28d74ee8 2964 #endif
57871462 2965 emit_readword((int)&last_count,ECX);
2966 #ifdef __i386__
2967 if(get_reg(i_regs->regmap,CCREG)<0)
2968 emit_loadreg(CCREG,HOST_CCREG);
2969 emit_add(HOST_CCREG,ECX,HOST_CCREG);
2970 emit_addimm(HOST_CCREG,2*ccadj[i],HOST_CCREG);
2971 emit_writeword(HOST_CCREG,(int)&Count);
2972 #endif
2973 #ifdef __arm__
2974 if(get_reg(i_regs->regmap,CCREG)<0)
2975 emit_loadreg(CCREG,0);
2976 else
2977 emit_mov(HOST_CCREG,0);
2978 emit_add(0,ECX,0);
2979 emit_addimm(0,2*ccadj[i],0);
2980 emit_writeword(0,(int)&Count);
2981 #endif
2982 emit_call((int)memdebug);
28d74ee8 2983 #ifdef __i386__
2984 emit_popa();
2985 #endif
2986 #ifdef __arm__
57871462 2987 restore_regs(0x100f);
28d74ee8 2988 #endif
57871462 2989 }/**/
2990}
2991
2992void storelr_assemble(int i,struct regstat *i_regs)
2993{
2994 int s,th,tl;
2995 int temp;
2996 int temp2;
2997 int offset;
2998 int jaddr=0,jaddr2;
2999 int case1,case2,case3;
3000 int done0,done1,done2;
af4ee1fe 3001 int memtarget=0,c=0;
fab5d06d 3002 int agr=AGEN1+(i&1);
57871462 3003 u_int hr,reglist=0;
3004 th=get_reg(i_regs->regmap,rs2[i]|64);
3005 tl=get_reg(i_regs->regmap,rs2[i]);
3006 s=get_reg(i_regs->regmap,rs1[i]);
fab5d06d 3007 temp=get_reg(i_regs->regmap,agr);
3008 if(temp<0) temp=get_reg(i_regs->regmap,-1);
57871462 3009 offset=imm[i];
3010 if(s>=0) {
3011 c=(i_regs->isconst>>s)&1;
af4ee1fe 3012 if(c) {
3013 memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
af4ee1fe 3014 }
57871462 3015 }
3016 assert(tl>=0);
3017 for(hr=0;hr<HOST_REGS;hr++) {
3018 if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
3019 }
535d208a 3020 assert(temp>=0);
1edfcc68 3021 if(!c) {
3022 emit_cmpimm(s<0||offset?temp:s,RAM_SIZE);
3023 if(!offset&&s!=temp) emit_mov(s,temp);
3024 jaddr=(int)out;
3025 emit_jno(0);
3026 }
3027 else
3028 {
3029 if(!memtarget||!rs1[i]) {
535d208a 3030 jaddr=(int)out;
3031 emit_jmp(0);
57871462 3032 }
535d208a 3033 }
1edfcc68 3034 #ifdef RAM_OFFSET
3035 int map=get_reg(i_regs->regmap,ROREG);
3036 if(map<0) emit_loadreg(ROREG,map=HOST_TEMPREG);
3037 #else
9f51b4b9 3038 if((u_int)rdram!=0x80000000)
1edfcc68 3039 emit_addimm_no_flags((u_int)rdram-(u_int)0x80000000,temp);
3040 #endif
535d208a 3041
3042 if (opcode[i]==0x2C||opcode[i]==0x2D) { // SDL/SDR
3043 temp2=get_reg(i_regs->regmap,FTEMP);
3044 if(!rs2[i]) temp2=th=tl;
3045 }
57871462 3046
2002a1db 3047#ifndef BIG_ENDIAN_MIPS
3048 emit_xorimm(temp,3,temp);
3049#endif
535d208a 3050 emit_testimm(temp,2);
3051 case2=(int)out;
3052 emit_jne(0);
3053 emit_testimm(temp,1);
3054 case1=(int)out;
3055 emit_jne(0);
3056 // 0
3057 if (opcode[i]==0x2A) { // SWL
3058 emit_writeword_indexed(tl,0,temp);
3059 }
3060 if (opcode[i]==0x2E) { // SWR
3061 emit_writebyte_indexed(tl,3,temp);
3062 }
3063 if (opcode[i]==0x2C) { // SDL
3064 emit_writeword_indexed(th,0,temp);
3065 if(rs2[i]) emit_mov(tl,temp2);
3066 }
3067 if (opcode[i]==0x2D) { // SDR
3068 emit_writebyte_indexed(tl,3,temp);
3069 if(rs2[i]) emit_shldimm(th,tl,24,temp2);
3070 }
3071 done0=(int)out;
3072 emit_jmp(0);
3073 // 1
3074 set_jump_target(case1,(int)out);
3075 if (opcode[i]==0x2A) { // SWL
3076 // Write 3 msb into three least significant bytes
3077 if(rs2[i]) emit_rorimm(tl,8,tl);
3078 emit_writehword_indexed(tl,-1,temp);
3079 if(rs2[i]) emit_rorimm(tl,16,tl);
3080 emit_writebyte_indexed(tl,1,temp);
3081 if(rs2[i]) emit_rorimm(tl,8,tl);
3082 }
3083 if (opcode[i]==0x2E) { // SWR
3084 // Write two lsb into two most significant bytes
3085 emit_writehword_indexed(tl,1,temp);
3086 }
3087 if (opcode[i]==0x2C) { // SDL
3088 if(rs2[i]) emit_shrdimm(tl,th,8,temp2);
3089 // Write 3 msb into three least significant bytes
3090 if(rs2[i]) emit_rorimm(th,8,th);
3091 emit_writehword_indexed(th,-1,temp);
3092 if(rs2[i]) emit_rorimm(th,16,th);
3093 emit_writebyte_indexed(th,1,temp);
3094 if(rs2[i]) emit_rorimm(th,8,th);
3095 }
3096 if (opcode[i]==0x2D) { // SDR
3097 if(rs2[i]) emit_shldimm(th,tl,16,temp2);
3098 // Write two lsb into two most significant bytes
3099 emit_writehword_indexed(tl,1,temp);
3100 }
3101 done1=(int)out;
3102 emit_jmp(0);
3103 // 2
3104 set_jump_target(case2,(int)out);
3105 emit_testimm(temp,1);
3106 case3=(int)out;
3107 emit_jne(0);
3108 if (opcode[i]==0x2A) { // SWL
3109 // Write two msb into two least significant bytes
3110 if(rs2[i]) emit_rorimm(tl,16,tl);
3111 emit_writehword_indexed(tl,-2,temp);
3112 if(rs2[i]) emit_rorimm(tl,16,tl);
3113 }
3114 if (opcode[i]==0x2E) { // SWR
3115 // Write 3 lsb into three most significant bytes
3116 emit_writebyte_indexed(tl,-1,temp);
3117 if(rs2[i]) emit_rorimm(tl,8,tl);
3118 emit_writehword_indexed(tl,0,temp);
3119 if(rs2[i]) emit_rorimm(tl,24,tl);
3120 }
3121 if (opcode[i]==0x2C) { // SDL
3122 if(rs2[i]) emit_shrdimm(tl,th,16,temp2);
3123 // Write two msb into two least significant bytes
3124 if(rs2[i]) emit_rorimm(th,16,th);
3125 emit_writehword_indexed(th,-2,temp);
3126 if(rs2[i]) emit_rorimm(th,16,th);
3127 }
3128 if (opcode[i]==0x2D) { // SDR
3129 if(rs2[i]) emit_shldimm(th,tl,8,temp2);
3130 // Write 3 lsb into three most significant bytes
3131 emit_writebyte_indexed(tl,-1,temp);
3132 if(rs2[i]) emit_rorimm(tl,8,tl);
3133 emit_writehword_indexed(tl,0,temp);
3134 if(rs2[i]) emit_rorimm(tl,24,tl);
3135 }
3136 done2=(int)out;
3137 emit_jmp(0);
3138 // 3
3139 set_jump_target(case3,(int)out);
3140 if (opcode[i]==0x2A) { // SWL
3141 // Write msb into least significant byte
3142 if(rs2[i]) emit_rorimm(tl,24,tl);
3143 emit_writebyte_indexed(tl,-3,temp);
3144 if(rs2[i]) emit_rorimm(tl,8,tl);
3145 }
3146 if (opcode[i]==0x2E) { // SWR
3147 // Write entire word
3148 emit_writeword_indexed(tl,-3,temp);
3149 }
3150 if (opcode[i]==0x2C) { // SDL
3151 if(rs2[i]) emit_shrdimm(tl,th,24,temp2);
3152 // Write msb into least significant byte
3153 if(rs2[i]) emit_rorimm(th,24,th);
3154 emit_writebyte_indexed(th,-3,temp);
3155 if(rs2[i]) emit_rorimm(th,8,th);
3156 }
3157 if (opcode[i]==0x2D) { // SDR
3158 if(rs2[i]) emit_mov(th,temp2);
3159 // Write entire word
3160 emit_writeword_indexed(tl,-3,temp);
3161 }
3162 set_jump_target(done0,(int)out);
3163 set_jump_target(done1,(int)out);
3164 set_jump_target(done2,(int)out);
3165 if (opcode[i]==0x2C) { // SDL
3166 emit_testimm(temp,4);
57871462 3167 done0=(int)out;
57871462 3168 emit_jne(0);
535d208a 3169 emit_andimm(temp,~3,temp);
3170 emit_writeword_indexed(temp2,4,temp);
3171 set_jump_target(done0,(int)out);
3172 }
3173 if (opcode[i]==0x2D) { // SDR
3174 emit_testimm(temp,4);
3175 done0=(int)out;
3176 emit_jeq(0);
3177 emit_andimm(temp,~3,temp);
3178 emit_writeword_indexed(temp2,-4,temp);
57871462 3179 set_jump_target(done0,(int)out);
57871462 3180 }
535d208a 3181 if(!c||!memtarget)
3182 add_stub(STORELR_STUB,jaddr,(int)out,i,(int)i_regs,temp,ccadj[i],reglist);
1edfcc68 3183 if(!(i_regs->waswritten&(1<<rs1[i]))&&!(new_dynarec_hacks&NDHACK_NO_SMC_CHECK)) {
535d208a 3184 #ifdef RAM_OFFSET
3185 int map=get_reg(i_regs->regmap,ROREG);
3186 if(map<0) map=HOST_TEMPREG;
3187 gen_orig_addr_w(temp,map);
3188 #else
57871462 3189 emit_addimm_no_flags((u_int)0x80000000-(u_int)rdram,temp);
535d208a 3190 #endif
57871462 3191 #if defined(HOST_IMM8)
3192 int ir=get_reg(i_regs->regmap,INVCP);
3193 assert(ir>=0);
3194 emit_cmpmem_indexedsr12_reg(ir,temp,1);
3195 #else
3196 emit_cmpmem_indexedsr12_imm((int)invalid_code,temp,1);
3197 #endif
535d208a 3198 #if defined(HAVE_CONDITIONAL_CALL) && !defined(DESTRUCTIVE_SHIFT)
3199 emit_callne(invalidate_addr_reg[temp]);
3200 #else
57871462 3201 jaddr2=(int)out;
3202 emit_jne(0);
3203 add_stub(INVCODE_STUB,jaddr2,(int)out,reglist|(1<<HOST_CCREG),temp,0,0,0);
535d208a 3204 #endif
57871462 3205 }
3206 /*
3207 emit_pusha();
3208 //save_regs(0x100f);
3209 emit_readword((int)&last_count,ECX);
3210 if(get_reg(i_regs->regmap,CCREG)<0)
3211 emit_loadreg(CCREG,HOST_CCREG);
3212 emit_add(HOST_CCREG,ECX,HOST_CCREG);
3213 emit_addimm(HOST_CCREG,2*ccadj[i],HOST_CCREG);
3214 emit_writeword(HOST_CCREG,(int)&Count);
3215 emit_call((int)memdebug);
3216 emit_popa();
3217 //restore_regs(0x100f);
3218 /**/
3219}
3220
3221void c1ls_assemble(int i,struct regstat *i_regs)
3222{
3d624f89 3223 cop1_unusable(i, i_regs);
57871462 3224}
3225
b9b61529 3226void c2ls_assemble(int i,struct regstat *i_regs)
3227{
3228 int s,tl;
3229 int ar;
3230 int offset;
1fd1aceb 3231 int memtarget=0,c=0;
c2e3bd42 3232 int jaddr2=0,jaddr3,type;
b9b61529 3233 int agr=AGEN1+(i&1);
ffb0b9e0 3234 int fastio_reg_override=0;
b9b61529 3235 u_int hr,reglist=0;
3236 u_int copr=(source[i]>>16)&0x1f;
3237 s=get_reg(i_regs->regmap,rs1[i]);
3238 tl=get_reg(i_regs->regmap,FTEMP);
3239 offset=imm[i];
3240 assert(rs1[i]>0);
3241 assert(tl>=0);