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drc: add some hack options
[pcsx_rearmed.git] / libpcsxcore / new_dynarec / new_dynarec.c
CommitLineData
57871462 1/* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
2 * Mupen64plus - new_dynarec.c *
20d507ba 3 * Copyright (C) 2009-2011 Ari64 *
57871462 4 * *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
9 * *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
14 * *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. *
19 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */
20
21#include <stdlib.h>
22#include <stdint.h> //include for uint64_t
23#include <assert.h>
4600ba03 24#include <sys/mman.h>
57871462 25
3d624f89 26#include "emu_if.h" //emulator interface
57871462 27
4600ba03 28//#define DISASM
29//#define assem_debug printf
30//#define inv_debug printf
31#define assem_debug(...)
32#define inv_debug(...)
57871462 33
34#ifdef __i386__
35#include "assem_x86.h"
36#endif
37#ifdef __x86_64__
38#include "assem_x64.h"
39#endif
40#ifdef __arm__
41#include "assem_arm.h"
42#endif
43
44#define MAXBLOCK 4096
45#define MAX_OUTPUT_BLOCK_SIZE 262144
2573466a 46
47int cycle_multiplier; // 100 for 1.0
48#define CLOCK_ADJUST(x) (((x) * cycle_multiplier + 50) / 100)
57871462 49
50struct regstat
51{
52 signed char regmap_entry[HOST_REGS];
53 signed char regmap[HOST_REGS];
54 uint64_t was32;
55 uint64_t is32;
56 uint64_t wasdirty;
57 uint64_t dirty;
58 uint64_t u;
59 uint64_t uu;
60 u_int wasconst;
61 u_int isconst;
8575a877 62 u_int loadedconst; // host regs that have constants loaded
63 u_int waswritten; // MIPS regs that were used as store base before
57871462 64 uint64_t constmap[HOST_REGS];
65};
66
67struct ll_entry
68{
69 u_int vaddr;
70 u_int reg32;
71 void *addr;
72 struct ll_entry *next;
73};
74
75 u_int start;
76 u_int *source;
77 u_int pagelimit;
78 char insn[MAXBLOCK][10];
79 u_char itype[MAXBLOCK];
80 u_char opcode[MAXBLOCK];
81 u_char opcode2[MAXBLOCK];
82 u_char bt[MAXBLOCK];
83 u_char rs1[MAXBLOCK];
84 u_char rs2[MAXBLOCK];
85 u_char rt1[MAXBLOCK];
86 u_char rt2[MAXBLOCK];
87 u_char us1[MAXBLOCK];
88 u_char us2[MAXBLOCK];
89 u_char dep1[MAXBLOCK];
90 u_char dep2[MAXBLOCK];
91 u_char lt1[MAXBLOCK];
bedfea38 92 static uint64_t gte_rs[MAXBLOCK]; // gte: 32 data and 32 ctl regs
93 static uint64_t gte_rt[MAXBLOCK];
94 static uint64_t gte_unneeded[MAXBLOCK];
ffb0b9e0 95 static u_int smrv[32]; // speculated MIPS register values
96 static u_int smrv_strong; // mask or regs that are likely to have correct values
97 static u_int smrv_weak; // same, but somewhat less likely
98 static u_int smrv_strong_next; // same, but after current insn executes
99 static u_int smrv_weak_next;
57871462 100 int imm[MAXBLOCK];
101 u_int ba[MAXBLOCK];
102 char likely[MAXBLOCK];
103 char is_ds[MAXBLOCK];
e1190b87 104 char ooo[MAXBLOCK];
57871462 105 uint64_t unneeded_reg[MAXBLOCK];
106 uint64_t unneeded_reg_upper[MAXBLOCK];
107 uint64_t branch_unneeded_reg[MAXBLOCK];
108 uint64_t branch_unneeded_reg_upper[MAXBLOCK];
109 uint64_t p32[MAXBLOCK];
110 uint64_t pr32[MAXBLOCK];
111 signed char regmap_pre[MAXBLOCK][HOST_REGS];
112 signed char regmap[MAXBLOCK][HOST_REGS];
113 signed char regmap_entry[MAXBLOCK][HOST_REGS];
114 uint64_t constmap[MAXBLOCK][HOST_REGS];
57871462 115 struct regstat regs[MAXBLOCK];
116 struct regstat branch_regs[MAXBLOCK];
e1190b87 117 signed char minimum_free_regs[MAXBLOCK];
57871462 118 u_int needed_reg[MAXBLOCK];
119 uint64_t requires_32bit[MAXBLOCK];
120 u_int wont_dirty[MAXBLOCK];
121 u_int will_dirty[MAXBLOCK];
122 int ccadj[MAXBLOCK];
123 int slen;
124 u_int instr_addr[MAXBLOCK];
125 u_int link_addr[MAXBLOCK][3];
126 int linkcount;
127 u_int stubs[MAXBLOCK*3][8];
128 int stubcount;
129 u_int literals[1024][2];
130 int literalcount;
131 int is_delayslot;
132 int cop1_usable;
133 u_char *out;
134 struct ll_entry *jump_in[4096];
135 struct ll_entry *jump_out[4096];
136 struct ll_entry *jump_dirty[4096];
137 u_int hash_table[65536][4] __attribute__((aligned(16)));
138 char shadow[1048576] __attribute__((aligned(16)));
139 void *copy;
140 int expirep;
af4ee1fe 141#ifndef PCSX
57871462 142 u_int using_tlb;
af4ee1fe 143#else
144 static const u_int using_tlb=0;
145#endif
2f546f9a 146 int new_dynarec_did_compile;
0ff8c62c 147 int new_dynarec_hacks;
57871462 148 u_int stop_after_jal;
149 extern u_char restore_candidate[512];
150 extern int cycle_count;
151
152 /* registers that may be allocated */
153 /* 1-31 gpr */
154#define HIREG 32 // hi
155#define LOREG 33 // lo
156#define FSREG 34 // FPU status (FCSR)
157#define CSREG 35 // Coprocessor status
158#define CCREG 36 // Cycle count
159#define INVCP 37 // Pointer to invalid_code
619e5ded 160#define MMREG 38 // Pointer to memory_map
161#define ROREG 39 // ram offset (if rdram!=0x80000000)
162#define TEMPREG 40
163#define FTEMP 40 // FPU temporary register
164#define PTEMP 41 // Prefetch temporary register
165#define TLREG 42 // TLB mapping offset
166#define RHASH 43 // Return address hash
167#define RHTBL 44 // Return address hash table address
168#define RTEMP 45 // JR/JALR address register
169#define MAXREG 45
170#define AGEN1 46 // Address generation temporary register
171#define AGEN2 47 // Address generation temporary register
172#define MGEN1 48 // Maptable address generation temporary register
173#define MGEN2 49 // Maptable address generation temporary register
174#define BTREG 50 // Branch target temporary register
57871462 175
176 /* instruction types */
177#define NOP 0 // No operation
178#define LOAD 1 // Load
179#define STORE 2 // Store
180#define LOADLR 3 // Unaligned load
181#define STORELR 4 // Unaligned store
182#define MOV 5 // Move
183#define ALU 6 // Arithmetic/logic
184#define MULTDIV 7 // Multiply/divide
185#define SHIFT 8 // Shift by register
186#define SHIFTIMM 9// Shift by immediate
187#define IMM16 10 // 16-bit immediate
188#define RJUMP 11 // Unconditional jump to register
189#define UJUMP 12 // Unconditional jump
190#define CJUMP 13 // Conditional branch (BEQ/BNE/BGTZ/BLEZ)
191#define SJUMP 14 // Conditional branch (regimm format)
192#define COP0 15 // Coprocessor 0
193#define COP1 16 // Coprocessor 1
194#define C1LS 17 // Coprocessor 1 load/store
195#define FJUMP 18 // Conditional branch (floating point)
196#define FLOAT 19 // Floating point unit
197#define FCONV 20 // Convert integer to float
198#define FCOMP 21 // Floating point compare (sets FSREG)
199#define SYSCALL 22// SYSCALL
200#define OTHER 23 // Other
201#define SPAN 24 // Branch/delay slot spans 2 pages
202#define NI 25 // Not implemented
7139f3c8 203#define HLECALL 26// PCSX fake opcodes for HLE
b9b61529 204#define COP2 27 // Coprocessor 2 move
205#define C2LS 28 // Coprocessor 2 load/store
206#define C2OP 29 // Coprocessor 2 operation
1e973cb0 207#define INTCALL 30// Call interpreter to handle rare corner cases
57871462 208
209 /* stubs */
210#define CC_STUB 1
211#define FP_STUB 2
212#define LOADB_STUB 3
213#define LOADH_STUB 4
214#define LOADW_STUB 5
215#define LOADD_STUB 6
216#define LOADBU_STUB 7
217#define LOADHU_STUB 8
218#define STOREB_STUB 9
219#define STOREH_STUB 10
220#define STOREW_STUB 11
221#define STORED_STUB 12
222#define STORELR_STUB 13
223#define INVCODE_STUB 14
224
225 /* branch codes */
226#define TAKEN 1
227#define NOTTAKEN 2
228#define NULLDS 3
229
230// asm linkage
231int new_recompile_block(int addr);
232void *get_addr_ht(u_int vaddr);
233void invalidate_block(u_int block);
234void invalidate_addr(u_int addr);
235void remove_hash(int vaddr);
236void jump_vaddr();
237void dyna_linker();
238void dyna_linker_ds();
239void verify_code();
240void verify_code_vm();
241void verify_code_ds();
242void cc_interrupt();
243void fp_exception();
244void fp_exception_ds();
245void jump_syscall();
7139f3c8 246void jump_syscall_hle();
57871462 247void jump_eret();
7139f3c8 248void jump_hlecall();
1e973cb0 249void jump_intcall();
7139f3c8 250void new_dyna_leave();
57871462 251
252// TLB
253void TLBWI_new();
254void TLBWR_new();
255void read_nomem_new();
256void read_nomemb_new();
257void read_nomemh_new();
258void read_nomemd_new();
259void write_nomem_new();
260void write_nomemb_new();
261void write_nomemh_new();
262void write_nomemd_new();
263void write_rdram_new();
264void write_rdramb_new();
265void write_rdramh_new();
266void write_rdramd_new();
267extern u_int memory_map[1048576];
268
269// Needed by assembler
270void wb_register(signed char r,signed char regmap[],uint64_t dirty,uint64_t is32);
271void wb_dirtys(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty);
272void wb_needed_dirtys(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr);
273void load_all_regs(signed char i_regmap[]);
274void load_needed_regs(signed char i_regmap[],signed char next_regmap[]);
275void load_regs_entry(int t);
276void load_all_consts(signed char regmap[],int is32,u_int dirty,int i);
277
278int tracedebug=0;
279
280//#define DEBUG_CYCLE_COUNT 1
281
94d23bb9 282static void tlb_hacks()
57871462 283{
94d23bb9 284#ifndef DISABLE_TLB
57871462 285 // Goldeneye hack
286 if (strncmp((char *) ROM_HEADER->nom, "GOLDENEYE",9) == 0)
287 {
288 u_int addr;
289 int n;
290 switch (ROM_HEADER->Country_code&0xFF)
291 {
292 case 0x45: // U
293 addr=0x34b30;
294 break;
295 case 0x4A: // J
296 addr=0x34b70;
297 break;
298 case 0x50: // E
299 addr=0x329f0;
300 break;
301 default:
302 // Unknown country code
303 addr=0;
304 break;
305 }
306 u_int rom_addr=(u_int)rom;
307 #ifdef ROM_COPY
308 // Since memory_map is 32-bit, on 64-bit systems the rom needs to be
309 // in the lower 4G of memory to use this hack. Copy it if necessary.
310 if((void *)rom>(void *)0xffffffff) {
311 munmap(ROM_COPY, 67108864);
312 if(mmap(ROM_COPY, 12582912,
313 PROT_READ | PROT_WRITE,
314 MAP_FIXED | MAP_PRIVATE | MAP_ANONYMOUS,
315 -1, 0) <= 0) {printf("mmap() failed\n");}
316 memcpy(ROM_COPY,rom,12582912);
317 rom_addr=(u_int)ROM_COPY;
318 }
319 #endif
320 if(addr) {
321 for(n=0x7F000;n<0x80000;n++) {
322 memory_map[n]=(((u_int)(rom_addr+addr-0x7F000000))>>2)|0x40000000;
323 }
324 }
325 }
94d23bb9 326#endif
57871462 327}
328
94d23bb9 329static u_int get_page(u_int vaddr)
57871462 330{
0ce47d46 331#ifndef PCSX
57871462 332 u_int page=(vaddr^0x80000000)>>12;
0ce47d46 333#else
334 u_int page=vaddr&~0xe0000000;
335 if (page < 0x1000000)
336 page &= ~0x0e00000; // RAM mirrors
337 page>>=12;
338#endif
94d23bb9 339#ifndef DISABLE_TLB
57871462 340 if(page>262143&&tlb_LUT_r[vaddr>>12]) page=(tlb_LUT_r[vaddr>>12]^0x80000000)>>12;
94d23bb9 341#endif
57871462 342 if(page>2048) page=2048+(page&2047);
94d23bb9 343 return page;
344}
345
346static u_int get_vpage(u_int vaddr)
347{
348 u_int vpage=(vaddr^0x80000000)>>12;
349#ifndef DISABLE_TLB
57871462 350 if(vpage>262143&&tlb_LUT_r[vaddr>>12]) vpage&=2047; // jump_dirty uses a hash of the virtual address instead
94d23bb9 351#endif
57871462 352 if(vpage>2048) vpage=2048+(vpage&2047);
94d23bb9 353 return vpage;
354}
355
356// Get address from virtual address
357// This is called from the recompiled JR/JALR instructions
358void *get_addr(u_int vaddr)
359{
360 u_int page=get_page(vaddr);
361 u_int vpage=get_vpage(vaddr);
57871462 362 struct ll_entry *head;
363 //printf("TRACE: count=%d next=%d (get_addr %x,page %d)\n",Count,next_interupt,vaddr,page);
364 head=jump_in[page];
365 while(head!=NULL) {
366 if(head->vaddr==vaddr&&head->reg32==0) {
367 //printf("TRACE: count=%d next=%d (get_addr match %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr);
368 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
369 ht_bin[3]=ht_bin[1];
370 ht_bin[2]=ht_bin[0];
371 ht_bin[1]=(int)head->addr;
372 ht_bin[0]=vaddr;
373 return head->addr;
374 }
375 head=head->next;
376 }
377 head=jump_dirty[vpage];
378 while(head!=NULL) {
379 if(head->vaddr==vaddr&&head->reg32==0) {
380 //printf("TRACE: count=%d next=%d (get_addr match dirty %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr);
381 // Don't restore blocks which are about to expire from the cache
382 if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
383 if(verify_dirty(head->addr)) {
384 //printf("restore candidate: %x (%d) d=%d\n",vaddr,page,invalid_code[vaddr>>12]);
385 invalid_code[vaddr>>12]=0;
9be4ba64 386 inv_code_start=inv_code_end=~0;
63cb0298 387#ifndef DISABLE_TLB
57871462 388 memory_map[vaddr>>12]|=0x40000000;
63cb0298 389#endif
57871462 390 if(vpage<2048) {
94d23bb9 391#ifndef DISABLE_TLB
57871462 392 if(tlb_LUT_r[vaddr>>12]) {
393 invalid_code[tlb_LUT_r[vaddr>>12]>>12]=0;
394 memory_map[tlb_LUT_r[vaddr>>12]>>12]|=0x40000000;
395 }
94d23bb9 396#endif
57871462 397 restore_candidate[vpage>>3]|=1<<(vpage&7);
398 }
399 else restore_candidate[page>>3]|=1<<(page&7);
400 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
401 if(ht_bin[0]==vaddr) {
402 ht_bin[1]=(int)head->addr; // Replace existing entry
403 }
404 else
405 {
406 ht_bin[3]=ht_bin[1];
407 ht_bin[2]=ht_bin[0];
408 ht_bin[1]=(int)head->addr;
409 ht_bin[0]=vaddr;
410 }
411 return head->addr;
412 }
413 }
414 head=head->next;
415 }
416 //printf("TRACE: count=%d next=%d (get_addr no-match %x)\n",Count,next_interupt,vaddr);
417 int r=new_recompile_block(vaddr);
418 if(r==0) return get_addr(vaddr);
419 // Execute in unmapped page, generate pagefault execption
420 Status|=2;
421 Cause=(vaddr<<31)|0x8;
422 EPC=(vaddr&1)?vaddr-5:vaddr;
423 BadVAddr=(vaddr&~1);
424 Context=(Context&0xFF80000F)|((BadVAddr>>9)&0x007FFFF0);
425 EntryHi=BadVAddr&0xFFFFE000;
426 return get_addr_ht(0x80000000);
427}
428// Look up address in hash table first
429void *get_addr_ht(u_int vaddr)
430{
431 //printf("TRACE: count=%d next=%d (get_addr_ht %x)\n",Count,next_interupt,vaddr);
432 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
433 if(ht_bin[0]==vaddr) return (void *)ht_bin[1];
434 if(ht_bin[2]==vaddr) return (void *)ht_bin[3];
435 return get_addr(vaddr);
436}
437
438void *get_addr_32(u_int vaddr,u_int flags)
439{
7139f3c8 440#ifdef FORCE32
441 return get_addr(vaddr);
560e4a12 442#else
57871462 443 //printf("TRACE: count=%d next=%d (get_addr_32 %x,flags %x)\n",Count,next_interupt,vaddr,flags);
444 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
445 if(ht_bin[0]==vaddr) return (void *)ht_bin[1];
446 if(ht_bin[2]==vaddr) return (void *)ht_bin[3];
94d23bb9 447 u_int page=get_page(vaddr);
448 u_int vpage=get_vpage(vaddr);
57871462 449 struct ll_entry *head;
450 head=jump_in[page];
451 while(head!=NULL) {
452 if(head->vaddr==vaddr&&(head->reg32&flags)==0) {
453 //printf("TRACE: count=%d next=%d (get_addr_32 match %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr);
454 if(head->reg32==0) {
455 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
456 if(ht_bin[0]==-1) {
457 ht_bin[1]=(int)head->addr;
458 ht_bin[0]=vaddr;
459 }else if(ht_bin[2]==-1) {
460 ht_bin[3]=(int)head->addr;
461 ht_bin[2]=vaddr;
462 }
463 //ht_bin[3]=ht_bin[1];
464 //ht_bin[2]=ht_bin[0];
465 //ht_bin[1]=(int)head->addr;
466 //ht_bin[0]=vaddr;
467 }
468 return head->addr;
469 }
470 head=head->next;
471 }
472 head=jump_dirty[vpage];
473 while(head!=NULL) {
474 if(head->vaddr==vaddr&&(head->reg32&flags)==0) {
475 //printf("TRACE: count=%d next=%d (get_addr_32 match dirty %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr);
476 // Don't restore blocks which are about to expire from the cache
477 if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
478 if(verify_dirty(head->addr)) {
479 //printf("restore candidate: %x (%d) d=%d\n",vaddr,page,invalid_code[vaddr>>12]);
480 invalid_code[vaddr>>12]=0;
9be4ba64 481 inv_code_start=inv_code_end=~0;
57871462 482 memory_map[vaddr>>12]|=0x40000000;
483 if(vpage<2048) {
94d23bb9 484#ifndef DISABLE_TLB
57871462 485 if(tlb_LUT_r[vaddr>>12]) {
486 invalid_code[tlb_LUT_r[vaddr>>12]>>12]=0;
487 memory_map[tlb_LUT_r[vaddr>>12]>>12]|=0x40000000;
488 }
94d23bb9 489#endif
57871462 490 restore_candidate[vpage>>3]|=1<<(vpage&7);
491 }
492 else restore_candidate[page>>3]|=1<<(page&7);
493 if(head->reg32==0) {
494 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
495 if(ht_bin[0]==-1) {
496 ht_bin[1]=(int)head->addr;
497 ht_bin[0]=vaddr;
498 }else if(ht_bin[2]==-1) {
499 ht_bin[3]=(int)head->addr;
500 ht_bin[2]=vaddr;
501 }
502 //ht_bin[3]=ht_bin[1];
503 //ht_bin[2]=ht_bin[0];
504 //ht_bin[1]=(int)head->addr;
505 //ht_bin[0]=vaddr;
506 }
507 return head->addr;
508 }
509 }
510 head=head->next;
511 }
512 //printf("TRACE: count=%d next=%d (get_addr_32 no-match %x,flags %x)\n",Count,next_interupt,vaddr,flags);
513 int r=new_recompile_block(vaddr);
514 if(r==0) return get_addr(vaddr);
515 // Execute in unmapped page, generate pagefault execption
516 Status|=2;
517 Cause=(vaddr<<31)|0x8;
518 EPC=(vaddr&1)?vaddr-5:vaddr;
519 BadVAddr=(vaddr&~1);
520 Context=(Context&0xFF80000F)|((BadVAddr>>9)&0x007FFFF0);
521 EntryHi=BadVAddr&0xFFFFE000;
522 return get_addr_ht(0x80000000);
560e4a12 523#endif
57871462 524}
525
526void clear_all_regs(signed char regmap[])
527{
528 int hr;
529 for (hr=0;hr<HOST_REGS;hr++) regmap[hr]=-1;
530}
531
532signed char get_reg(signed char regmap[],int r)
533{
534 int hr;
535 for (hr=0;hr<HOST_REGS;hr++) if(hr!=EXCLUDE_REG&&regmap[hr]==r) return hr;
536 return -1;
537}
538
539// Find a register that is available for two consecutive cycles
540signed char get_reg2(signed char regmap1[],signed char regmap2[],int r)
541{
542 int hr;
543 for (hr=0;hr<HOST_REGS;hr++) if(hr!=EXCLUDE_REG&&regmap1[hr]==r&&regmap2[hr]==r) return hr;
544 return -1;
545}
546
547int count_free_regs(signed char regmap[])
548{
549 int count=0;
550 int hr;
551 for(hr=0;hr<HOST_REGS;hr++)
552 {
553 if(hr!=EXCLUDE_REG) {
554 if(regmap[hr]<0) count++;
555 }
556 }
557 return count;
558}
559
560void dirty_reg(struct regstat *cur,signed char reg)
561{
562 int hr;
563 if(!reg) return;
564 for (hr=0;hr<HOST_REGS;hr++) {
565 if((cur->regmap[hr]&63)==reg) {
566 cur->dirty|=1<<hr;
567 }
568 }
569}
570
571// If we dirty the lower half of a 64 bit register which is now being
572// sign-extended, we need to dump the upper half.
573// Note: Do this only after completion of the instruction, because
574// some instructions may need to read the full 64-bit value even if
575// overwriting it (eg SLTI, DSRA32).
576static void flush_dirty_uppers(struct regstat *cur)
577{
578 int hr,reg;
579 for (hr=0;hr<HOST_REGS;hr++) {
580 if((cur->dirty>>hr)&1) {
581 reg=cur->regmap[hr];
582 if(reg>=64)
583 if((cur->is32>>(reg&63))&1) cur->regmap[hr]=-1;
584 }
585 }
586}
587
588void set_const(struct regstat *cur,signed char reg,uint64_t value)
589{
590 int hr;
591 if(!reg) return;
592 for (hr=0;hr<HOST_REGS;hr++) {
593 if(cur->regmap[hr]==reg) {
594 cur->isconst|=1<<hr;
595 cur->constmap[hr]=value;
596 }
597 else if((cur->regmap[hr]^64)==reg) {
598 cur->isconst|=1<<hr;
599 cur->constmap[hr]=value>>32;
600 }
601 }
602}
603
604void clear_const(struct regstat *cur,signed char reg)
605{
606 int hr;
607 if(!reg) return;
608 for (hr=0;hr<HOST_REGS;hr++) {
609 if((cur->regmap[hr]&63)==reg) {
610 cur->isconst&=~(1<<hr);
611 }
612 }
613}
614
615int is_const(struct regstat *cur,signed char reg)
616{
617 int hr;
79c75f1b 618 if(reg<0) return 0;
57871462 619 if(!reg) return 1;
620 for (hr=0;hr<HOST_REGS;hr++) {
621 if((cur->regmap[hr]&63)==reg) {
622 return (cur->isconst>>hr)&1;
623 }
624 }
625 return 0;
626}
627uint64_t get_const(struct regstat *cur,signed char reg)
628{
629 int hr;
630 if(!reg) return 0;
631 for (hr=0;hr<HOST_REGS;hr++) {
632 if(cur->regmap[hr]==reg) {
633 return cur->constmap[hr];
634 }
635 }
636 printf("Unknown constant in r%d\n",reg);
637 exit(1);
638}
639
640// Least soon needed registers
641// Look at the next ten instructions and see which registers
642// will be used. Try not to reallocate these.
643void lsn(u_char hsn[], int i, int *preferred_reg)
644{
645 int j;
646 int b=-1;
647 for(j=0;j<9;j++)
648 {
649 if(i+j>=slen) {
650 j=slen-i-1;
651 break;
652 }
653 if(itype[i+j]==UJUMP||itype[i+j]==RJUMP||(source[i+j]>>16)==0x1000)
654 {
655 // Don't go past an unconditonal jump
656 j++;
657 break;
658 }
659 }
660 for(;j>=0;j--)
661 {
662 if(rs1[i+j]) hsn[rs1[i+j]]=j;
663 if(rs2[i+j]) hsn[rs2[i+j]]=j;
664 if(rt1[i+j]) hsn[rt1[i+j]]=j;
665 if(rt2[i+j]) hsn[rt2[i+j]]=j;
666 if(itype[i+j]==STORE || itype[i+j]==STORELR) {
667 // Stores can allocate zero
668 hsn[rs1[i+j]]=j;
669 hsn[rs2[i+j]]=j;
670 }
671 // On some architectures stores need invc_ptr
672 #if defined(HOST_IMM8)
b9b61529 673 if(itype[i+j]==STORE || itype[i+j]==STORELR || (opcode[i+j]&0x3b)==0x39 || (opcode[i+j]&0x3b)==0x3a) {
57871462 674 hsn[INVCP]=j;
675 }
676 #endif
677 if(i+j>=0&&(itype[i+j]==UJUMP||itype[i+j]==CJUMP||itype[i+j]==SJUMP||itype[i+j]==FJUMP))
678 {
679 hsn[CCREG]=j;
680 b=j;
681 }
682 }
683 if(b>=0)
684 {
685 if(ba[i+b]>=start && ba[i+b]<(start+slen*4))
686 {
687 // Follow first branch
688 int t=(ba[i+b]-start)>>2;
689 j=7-b;if(t+j>=slen) j=slen-t-1;
690 for(;j>=0;j--)
691 {
692 if(rs1[t+j]) if(hsn[rs1[t+j]]>j+b+2) hsn[rs1[t+j]]=j+b+2;
693 if(rs2[t+j]) if(hsn[rs2[t+j]]>j+b+2) hsn[rs2[t+j]]=j+b+2;
694 //if(rt1[t+j]) if(hsn[rt1[t+j]]>j+b+2) hsn[rt1[t+j]]=j+b+2;
695 //if(rt2[t+j]) if(hsn[rt2[t+j]]>j+b+2) hsn[rt2[t+j]]=j+b+2;
696 }
697 }
698 // TODO: preferred register based on backward branch
699 }
700 // Delay slot should preferably not overwrite branch conditions or cycle count
701 if(i>0&&(itype[i-1]==RJUMP||itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP)) {
702 if(rs1[i-1]) if(hsn[rs1[i-1]]>1) hsn[rs1[i-1]]=1;
703 if(rs2[i-1]) if(hsn[rs2[i-1]]>1) hsn[rs2[i-1]]=1;
704 hsn[CCREG]=1;
705 // ...or hash tables
706 hsn[RHASH]=1;
707 hsn[RHTBL]=1;
708 }
709 // Coprocessor load/store needs FTEMP, even if not declared
b9b61529 710 if(itype[i]==C1LS||itype[i]==C2LS) {
57871462 711 hsn[FTEMP]=0;
712 }
713 // Load L/R also uses FTEMP as a temporary register
714 if(itype[i]==LOADLR) {
715 hsn[FTEMP]=0;
716 }
b7918751 717 // Also SWL/SWR/SDL/SDR
718 if(opcode[i]==0x2a||opcode[i]==0x2e||opcode[i]==0x2c||opcode[i]==0x2d) {
57871462 719 hsn[FTEMP]=0;
720 }
721 // Don't remove the TLB registers either
b9b61529 722 if(itype[i]==LOAD || itype[i]==LOADLR || itype[i]==STORE || itype[i]==STORELR || itype[i]==C1LS || itype[i]==C2LS) {
57871462 723 hsn[TLREG]=0;
724 }
725 // Don't remove the miniht registers
726 if(itype[i]==UJUMP||itype[i]==RJUMP)
727 {
728 hsn[RHASH]=0;
729 hsn[RHTBL]=0;
730 }
731}
732
733// We only want to allocate registers if we're going to use them again soon
734int needed_again(int r, int i)
735{
736 int j;
737 int b=-1;
738 int rn=10;
57871462 739
740 if(i>0&&(itype[i-1]==UJUMP||itype[i-1]==RJUMP||(source[i-1]>>16)==0x1000))
741 {
742 if(ba[i-1]<start || ba[i-1]>start+slen*4-4)
743 return 0; // Don't need any registers if exiting the block
744 }
745 for(j=0;j<9;j++)
746 {
747 if(i+j>=slen) {
748 j=slen-i-1;
749 break;
750 }
751 if(itype[i+j]==UJUMP||itype[i+j]==RJUMP||(source[i+j]>>16)==0x1000)
752 {
753 // Don't go past an unconditonal jump
754 j++;
755 break;
756 }
1e973cb0 757 if(itype[i+j]==SYSCALL||itype[i+j]==HLECALL||itype[i+j]==INTCALL||((source[i+j]&0xfc00003f)==0x0d))
57871462 758 {
759 break;
760 }
761 }
762 for(;j>=1;j--)
763 {
764 if(rs1[i+j]==r) rn=j;
765 if(rs2[i+j]==r) rn=j;
766 if((unneeded_reg[i+j]>>r)&1) rn=10;
767 if(i+j>=0&&(itype[i+j]==UJUMP||itype[i+j]==CJUMP||itype[i+j]==SJUMP||itype[i+j]==FJUMP))
768 {
769 b=j;
770 }
771 }
772 /*
773 if(b>=0)
774 {
775 if(ba[i+b]>=start && ba[i+b]<(start+slen*4))
776 {
777 // Follow first branch
778 int o=rn;
779 int t=(ba[i+b]-start)>>2;
780 j=7-b;if(t+j>=slen) j=slen-t-1;
781 for(;j>=0;j--)
782 {
783 if(!((unneeded_reg[t+j]>>r)&1)) {
784 if(rs1[t+j]==r) if(rn>j+b+2) rn=j+b+2;
785 if(rs2[t+j]==r) if(rn>j+b+2) rn=j+b+2;
786 }
787 else rn=o;
788 }
789 }
790 }*/
b7217e13 791 if(rn<10) return 1;
57871462 792 return 0;
793}
794
795// Try to match register allocations at the end of a loop with those
796// at the beginning
797int loop_reg(int i, int r, int hr)
798{
799 int j,k;
800 for(j=0;j<9;j++)
801 {
802 if(i+j>=slen) {
803 j=slen-i-1;
804 break;
805 }
806 if(itype[i+j]==UJUMP||itype[i+j]==RJUMP||(source[i+j]>>16)==0x1000)
807 {
808 // Don't go past an unconditonal jump
809 j++;
810 break;
811 }
812 }
813 k=0;
814 if(i>0){
815 if(itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP)
816 k--;
817 }
818 for(;k<j;k++)
819 {
820 if(r<64&&((unneeded_reg[i+k]>>r)&1)) return hr;
821 if(r>64&&((unneeded_reg_upper[i+k]>>r)&1)) return hr;
822 if(i+k>=0&&(itype[i+k]==UJUMP||itype[i+k]==CJUMP||itype[i+k]==SJUMP||itype[i+k]==FJUMP))
823 {
824 if(ba[i+k]>=start && ba[i+k]<(start+i*4))
825 {
826 int t=(ba[i+k]-start)>>2;
827 int reg=get_reg(regs[t].regmap_entry,r);
828 if(reg>=0) return reg;
829 //reg=get_reg(regs[t+1].regmap_entry,r);
830 //if(reg>=0) return reg;
831 }
832 }
833 }
834 return hr;
835}
836
837
838// Allocate every register, preserving source/target regs
839void alloc_all(struct regstat *cur,int i)
840{
841 int hr;
842
843 for(hr=0;hr<HOST_REGS;hr++) {
844 if(hr!=EXCLUDE_REG) {
845 if(((cur->regmap[hr]&63)!=rs1[i])&&((cur->regmap[hr]&63)!=rs2[i])&&
846 ((cur->regmap[hr]&63)!=rt1[i])&&((cur->regmap[hr]&63)!=rt2[i]))
847 {
848 cur->regmap[hr]=-1;
849 cur->dirty&=~(1<<hr);
850 }
851 // Don't need zeros
852 if((cur->regmap[hr]&63)==0)
853 {
854 cur->regmap[hr]=-1;
855 cur->dirty&=~(1<<hr);
856 }
857 }
858 }
859}
860
4600ba03 861#ifndef FORCE32
57871462 862void div64(int64_t dividend,int64_t divisor)
863{
864 lo=dividend/divisor;
865 hi=dividend%divisor;
866 //printf("TRACE: ddiv %8x%8x %8x%8x\n" ,(int)reg[HIREG],(int)(reg[HIREG]>>32)
867 // ,(int)reg[LOREG],(int)(reg[LOREG]>>32));
868}
869void divu64(uint64_t dividend,uint64_t divisor)
870{
871 lo=dividend/divisor;
872 hi=dividend%divisor;
873 //printf("TRACE: ddivu %8x%8x %8x%8x\n",(int)reg[HIREG],(int)(reg[HIREG]>>32)
874 // ,(int)reg[LOREG],(int)(reg[LOREG]>>32));
875}
876
877void mult64(uint64_t m1,uint64_t m2)
878{
879 unsigned long long int op1, op2, op3, op4;
880 unsigned long long int result1, result2, result3, result4;
881 unsigned long long int temp1, temp2, temp3, temp4;
882 int sign = 0;
883
884 if (m1 < 0)
885 {
886 op2 = -m1;
887 sign = 1 - sign;
888 }
889 else op2 = m1;
890 if (m2 < 0)
891 {
892 op4 = -m2;
893 sign = 1 - sign;
894 }
895 else op4 = m2;
896
897 op1 = op2 & 0xFFFFFFFF;
898 op2 = (op2 >> 32) & 0xFFFFFFFF;
899 op3 = op4 & 0xFFFFFFFF;
900 op4 = (op4 >> 32) & 0xFFFFFFFF;
901
902 temp1 = op1 * op3;
903 temp2 = (temp1 >> 32) + op1 * op4;
904 temp3 = op2 * op3;
905 temp4 = (temp3 >> 32) + op2 * op4;
906
907 result1 = temp1 & 0xFFFFFFFF;
908 result2 = temp2 + (temp3 & 0xFFFFFFFF);
909 result3 = (result2 >> 32) + temp4;
910 result4 = (result3 >> 32);
911
912 lo = result1 | (result2 << 32);
913 hi = (result3 & 0xFFFFFFFF) | (result4 << 32);
914 if (sign)
915 {
916 hi = ~hi;
917 if (!lo) hi++;
918 else lo = ~lo + 1;
919 }
920}
921
922void multu64(uint64_t m1,uint64_t m2)
923{
924 unsigned long long int op1, op2, op3, op4;
925 unsigned long long int result1, result2, result3, result4;
926 unsigned long long int temp1, temp2, temp3, temp4;
927
928 op1 = m1 & 0xFFFFFFFF;
929 op2 = (m1 >> 32) & 0xFFFFFFFF;
930 op3 = m2 & 0xFFFFFFFF;
931 op4 = (m2 >> 32) & 0xFFFFFFFF;
932
933 temp1 = op1 * op3;
934 temp2 = (temp1 >> 32) + op1 * op4;
935 temp3 = op2 * op3;
936 temp4 = (temp3 >> 32) + op2 * op4;
937
938 result1 = temp1 & 0xFFFFFFFF;
939 result2 = temp2 + (temp3 & 0xFFFFFFFF);
940 result3 = (result2 >> 32) + temp4;
941 result4 = (result3 >> 32);
942
943 lo = result1 | (result2 << 32);
944 hi = (result3 & 0xFFFFFFFF) | (result4 << 32);
945
946 //printf("TRACE: dmultu %8x%8x %8x%8x\n",(int)reg[HIREG],(int)(reg[HIREG]>>32)
947 // ,(int)reg[LOREG],(int)(reg[LOREG]>>32));
948}
949
950uint64_t ldl_merge(uint64_t original,uint64_t loaded,u_int bits)
951{
952 if(bits) {
953 original<<=64-bits;
954 original>>=64-bits;
955 loaded<<=bits;
956 original|=loaded;
957 }
958 else original=loaded;
959 return original;
960}
961uint64_t ldr_merge(uint64_t original,uint64_t loaded,u_int bits)
962{
963 if(bits^56) {
964 original>>=64-(bits^56);
965 original<<=64-(bits^56);
966 loaded>>=bits^56;
967 original|=loaded;
968 }
969 else original=loaded;
970 return original;
971}
4600ba03 972#endif
57871462 973
974#ifdef __i386__
975#include "assem_x86.c"
976#endif
977#ifdef __x86_64__
978#include "assem_x64.c"
979#endif
980#ifdef __arm__
981#include "assem_arm.c"
982#endif
983
984// Add virtual address mapping to linked list
985void ll_add(struct ll_entry **head,int vaddr,void *addr)
986{
987 struct ll_entry *new_entry;
988 new_entry=malloc(sizeof(struct ll_entry));
989 assert(new_entry!=NULL);
990 new_entry->vaddr=vaddr;
991 new_entry->reg32=0;
992 new_entry->addr=addr;
993 new_entry->next=*head;
994 *head=new_entry;
995}
996
997// Add virtual address mapping for 32-bit compiled block
998void ll_add_32(struct ll_entry **head,int vaddr,u_int reg32,void *addr)
999{
7139f3c8 1000 ll_add(head,vaddr,addr);
1001#ifndef FORCE32
1002 (*head)->reg32=reg32;
1003#endif
57871462 1004}
1005
1006// Check if an address is already compiled
1007// but don't return addresses which are about to expire from the cache
1008void *check_addr(u_int vaddr)
1009{
1010 u_int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
1011 if(ht_bin[0]==vaddr) {
1012 if(((ht_bin[1]-MAX_OUTPUT_BLOCK_SIZE-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
1013 if(isclean(ht_bin[1])) return (void *)ht_bin[1];
1014 }
1015 if(ht_bin[2]==vaddr) {
1016 if(((ht_bin[3]-MAX_OUTPUT_BLOCK_SIZE-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
1017 if(isclean(ht_bin[3])) return (void *)ht_bin[3];
1018 }
94d23bb9 1019 u_int page=get_page(vaddr);
57871462 1020 struct ll_entry *head;
1021 head=jump_in[page];
1022 while(head!=NULL) {
1023 if(head->vaddr==vaddr&&head->reg32==0) {
1024 if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2))) {
1025 // Update existing entry with current address
1026 if(ht_bin[0]==vaddr) {
1027 ht_bin[1]=(int)head->addr;
1028 return head->addr;
1029 }
1030 if(ht_bin[2]==vaddr) {
1031 ht_bin[3]=(int)head->addr;
1032 return head->addr;
1033 }
1034 // Insert into hash table with low priority.
1035 // Don't evict existing entries, as they are probably
1036 // addresses that are being accessed frequently.
1037 if(ht_bin[0]==-1) {
1038 ht_bin[1]=(int)head->addr;
1039 ht_bin[0]=vaddr;
1040 }else if(ht_bin[2]==-1) {
1041 ht_bin[3]=(int)head->addr;
1042 ht_bin[2]=vaddr;
1043 }
1044 return head->addr;
1045 }
1046 }
1047 head=head->next;
1048 }
1049 return 0;
1050}
1051
1052void remove_hash(int vaddr)
1053{
1054 //printf("remove hash: %x\n",vaddr);
1055 int *ht_bin=hash_table[(((vaddr)>>16)^vaddr)&0xFFFF];
1056 if(ht_bin[2]==vaddr) {
1057 ht_bin[2]=ht_bin[3]=-1;
1058 }
1059 if(ht_bin[0]==vaddr) {
1060 ht_bin[0]=ht_bin[2];
1061 ht_bin[1]=ht_bin[3];
1062 ht_bin[2]=ht_bin[3]=-1;
1063 }
1064}
1065
1066void ll_remove_matching_addrs(struct ll_entry **head,int addr,int shift)
1067{
1068 struct ll_entry *next;
1069 while(*head) {
1070 if(((u_int)((*head)->addr)>>shift)==(addr>>shift) ||
1071 ((u_int)((*head)->addr-MAX_OUTPUT_BLOCK_SIZE)>>shift)==(addr>>shift))
1072 {
1073 inv_debug("EXP: Remove pointer to %x (%x)\n",(int)(*head)->addr,(*head)->vaddr);
1074 remove_hash((*head)->vaddr);
1075 next=(*head)->next;
1076 free(*head);
1077 *head=next;
1078 }
1079 else
1080 {
1081 head=&((*head)->next);
1082 }
1083 }
1084}
1085
1086// Remove all entries from linked list
1087void ll_clear(struct ll_entry **head)
1088{
1089 struct ll_entry *cur;
1090 struct ll_entry *next;
1091 if(cur=*head) {
1092 *head=0;
1093 while(cur) {
1094 next=cur->next;
1095 free(cur);
1096 cur=next;
1097 }
1098 }
1099}
1100
1101// Dereference the pointers and remove if it matches
1102void ll_kill_pointers(struct ll_entry *head,int addr,int shift)
1103{
1104 while(head) {
1105 int ptr=get_pointer(head->addr);
1106 inv_debug("EXP: Lookup pointer to %x at %x (%x)\n",(int)ptr,(int)head->addr,head->vaddr);
1107 if(((ptr>>shift)==(addr>>shift)) ||
1108 (((ptr-MAX_OUTPUT_BLOCK_SIZE)>>shift)==(addr>>shift)))
1109 {
5088bb70 1110 inv_debug("EXP: Kill pointer at %x (%x)\n",(int)head->addr,head->vaddr);
f76eeef9 1111 u_int host_addr=(u_int)kill_pointer(head->addr);
dd3a91a1 1112 #ifdef __arm__
1113 needs_clear_cache[(host_addr-(u_int)BASE_ADDR)>>17]|=1<<(((host_addr-(u_int)BASE_ADDR)>>12)&31);
1114 #endif
57871462 1115 }
1116 head=head->next;
1117 }
1118}
1119
1120// This is called when we write to a compiled block (see do_invstub)
f76eeef9 1121void invalidate_page(u_int page)
57871462 1122{
57871462 1123 struct ll_entry *head;
1124 struct ll_entry *next;
1125 head=jump_in[page];
1126 jump_in[page]=0;
1127 while(head!=NULL) {
1128 inv_debug("INVALIDATE: %x\n",head->vaddr);
1129 remove_hash(head->vaddr);
1130 next=head->next;
1131 free(head);
1132 head=next;
1133 }
1134 head=jump_out[page];
1135 jump_out[page]=0;
1136 while(head!=NULL) {
1137 inv_debug("INVALIDATE: kill pointer to %x (%x)\n",head->vaddr,(int)head->addr);
f76eeef9 1138 u_int host_addr=(u_int)kill_pointer(head->addr);
dd3a91a1 1139 #ifdef __arm__
1140 needs_clear_cache[(host_addr-(u_int)BASE_ADDR)>>17]|=1<<(((host_addr-(u_int)BASE_ADDR)>>12)&31);
1141 #endif
57871462 1142 next=head->next;
1143 free(head);
1144 head=next;
1145 }
57871462 1146}
9be4ba64 1147
1148static void invalidate_block_range(u_int block, u_int first, u_int last)
57871462 1149{
94d23bb9 1150 u_int page=get_page(block<<12);
57871462 1151 //printf("first=%d last=%d\n",first,last);
f76eeef9 1152 invalidate_page(page);
57871462 1153 assert(first+5>page); // NB: this assumes MAXBLOCK<=4096 (4 pages)
1154 assert(last<page+5);
1155 // Invalidate the adjacent pages if a block crosses a 4K boundary
1156 while(first<page) {
1157 invalidate_page(first);
1158 first++;
1159 }
1160 for(first=page+1;first<last;first++) {
1161 invalidate_page(first);
1162 }
dd3a91a1 1163 #ifdef __arm__
1164 do_clear_cache();
1165 #endif
57871462 1166
1167 // Don't trap writes
1168 invalid_code[block]=1;
94d23bb9 1169#ifndef DISABLE_TLB
57871462 1170 // If there is a valid TLB entry for this page, remove write protect
1171 if(tlb_LUT_w[block]) {
1172 assert(tlb_LUT_r[block]==tlb_LUT_w[block]);
1173 // CHECK: Is this right?
1174 memory_map[block]=((tlb_LUT_w[block]&0xFFFFF000)-(block<<12)+(unsigned int)rdram-0x80000000)>>2;
1175 u_int real_block=tlb_LUT_w[block]>>12;
1176 invalid_code[real_block]=1;
1177 if(real_block>=0x80000&&real_block<0x80800) memory_map[real_block]=((u_int)rdram-0x80000000)>>2;
1178 }
1179 else if(block>=0x80000&&block<0x80800) memory_map[block]=((u_int)rdram-0x80000000)>>2;
94d23bb9 1180#endif
f76eeef9 1181
57871462 1182 #ifdef USE_MINI_HT
1183 memset(mini_ht,-1,sizeof(mini_ht));
1184 #endif
1185}
9be4ba64 1186
1187void invalidate_block(u_int block)
1188{
1189 u_int page=get_page(block<<12);
1190 u_int vpage=get_vpage(block<<12);
1191 inv_debug("INVALIDATE: %x (%d)\n",block<<12,page);
1192 //inv_debug("invalid_code[block]=%d\n",invalid_code[block]);
1193 u_int first,last;
1194 first=last=page;
1195 struct ll_entry *head;
1196 head=jump_dirty[vpage];
1197 //printf("page=%d vpage=%d\n",page,vpage);
1198 while(head!=NULL) {
1199 u_int start,end;
1200 if(vpage>2047||(head->vaddr>>12)==block) { // Ignore vaddr hash collision
1201 get_bounds((int)head->addr,&start,&end);
1202 //printf("start: %x end: %x\n",start,end);
1203 if(page<2048&&start>=0x80000000&&end<0x80000000+RAM_SIZE) {
1204 if(((start-(u_int)rdram)>>12)<=page&&((end-1-(u_int)rdram)>>12)>=page) {
1205 if((((start-(u_int)rdram)>>12)&2047)<first) first=((start-(u_int)rdram)>>12)&2047;
1206 if((((end-1-(u_int)rdram)>>12)&2047)>last) last=((end-1-(u_int)rdram)>>12)&2047;
1207 }
1208 }
1209#ifndef DISABLE_TLB
1210 if(page<2048&&(signed int)start>=(signed int)0xC0000000&&(signed int)end>=(signed int)0xC0000000) {
1211 if(((start+memory_map[start>>12]-(u_int)rdram)>>12)<=page&&((end-1+memory_map[(end-1)>>12]-(u_int)rdram)>>12)>=page) {
1212 if((((start+memory_map[start>>12]-(u_int)rdram)>>12)&2047)<first) first=((start+memory_map[start>>12]-(u_int)rdram)>>12)&2047;
1213 if((((end-1+memory_map[(end-1)>>12]-(u_int)rdram)>>12)&2047)>last) last=((end-1+memory_map[(end-1)>>12]-(u_int)rdram)>>12)&2047;
1214 }
1215 }
1216#endif
1217 }
1218 head=head->next;
1219 }
1220 invalidate_block_range(block,first,last);
1221}
1222
57871462 1223void invalidate_addr(u_int addr)
1224{
9be4ba64 1225#ifdef PCSX
1226 //static int rhits;
1227 // this check is done by the caller
1228 //if (inv_code_start<=addr&&addr<=inv_code_end) { rhits++; return; }
1229 u_int page=get_page(addr);
1230 if(page<2048) { // RAM
1231 struct ll_entry *head;
1232 u_int addr_min=~0, addr_max=0;
1233 int mask=RAM_SIZE-1;
1234 int pg1;
1235 inv_code_start=addr&~0xfff;
1236 inv_code_end=addr|0xfff;
1237 pg1=page;
1238 if (pg1>0) {
1239 // must check previous page too because of spans..
1240 pg1--;
1241 inv_code_start-=0x1000;
1242 }
1243 for(;pg1<=page;pg1++) {
1244 for(head=jump_dirty[pg1];head!=NULL;head=head->next) {
1245 u_int start,end;
1246 get_bounds((int)head->addr,&start,&end);
1247 if((start&mask)<=(addr&mask)&&(addr&mask)<(end&mask)) {
1248 if(start<addr_min) addr_min=start;
1249 if(end>addr_max) addr_max=end;
1250 }
1251 else if(addr<start) {
1252 if(start<inv_code_end)
1253 inv_code_end=start-1;
1254 }
1255 else {
1256 if(end>inv_code_start)
1257 inv_code_start=end;
1258 }
1259 }
1260 }
1261 if (addr_min!=~0) {
1262 inv_debug("INV ADDR: %08x hit %08x-%08x\n", addr, addr_min, addr_max);
1263 inv_code_start=inv_code_end=~0;
1264 invalidate_block_range(addr>>12,(addr_min&mask)>>12,(addr_max&mask)>>12);
1265 return;
1266 }
1267 else {
1268 inv_debug("INV ADDR: %08x miss, inv %08x-%08x, sk %d\n", addr, inv_code_start, inv_code_end, 0);//rhits);
1269 }
1270 //rhits=0;
1271 if(page!=0) // FIXME: don't know what's up with page 0 (Klonoa)
1272 return;
1273 }
1274#endif
57871462 1275 invalidate_block(addr>>12);
1276}
9be4ba64 1277
dd3a91a1 1278// This is called when loading a save state.
1279// Anything could have changed, so invalidate everything.
57871462 1280void invalidate_all_pages()
1281{
1282 u_int page,n;
1283 for(page=0;page<4096;page++)
1284 invalidate_page(page);
1285 for(page=0;page<1048576;page++)
1286 if(!invalid_code[page]) {
1287 restore_candidate[(page&2047)>>3]|=1<<(page&7);
1288 restore_candidate[((page&2047)>>3)+256]|=1<<(page&7);
1289 }
1290 #ifdef __arm__
1291 __clear_cache((void *)BASE_ADDR,(void *)BASE_ADDR+(1<<TARGET_SIZE_2));
1292 #endif
1293 #ifdef USE_MINI_HT
1294 memset(mini_ht,-1,sizeof(mini_ht));
1295 #endif
94d23bb9 1296 #ifndef DISABLE_TLB
57871462 1297 // TLB
1298 for(page=0;page<0x100000;page++) {
1299 if(tlb_LUT_r[page]) {
1300 memory_map[page]=((tlb_LUT_r[page]&0xFFFFF000)-(page<<12)+(unsigned int)rdram-0x80000000)>>2;
1301 if(!tlb_LUT_w[page]||!invalid_code[page])
1302 memory_map[page]|=0x40000000; // Write protect
1303 }
1304 else memory_map[page]=-1;
1305 if(page==0x80000) page=0xC0000;
1306 }
1307 tlb_hacks();
94d23bb9 1308 #endif
57871462 1309}
1310
1311// Add an entry to jump_out after making a link
1312void add_link(u_int vaddr,void *src)
1313{
94d23bb9 1314 u_int page=get_page(vaddr);
57871462 1315 inv_debug("add_link: %x -> %x (%d)\n",(int)src,vaddr,page);
76f71c27 1316 int *ptr=(int *)(src+4);
1317 assert((*ptr&0x0fff0000)==0x059f0000);
57871462 1318 ll_add(jump_out+page,vaddr,src);
1319 //int ptr=get_pointer(src);
1320 //inv_debug("add_link: Pointer is to %x\n",(int)ptr);
1321}
1322
1323// If a code block was found to be unmodified (bit was set in
1324// restore_candidate) and it remains unmodified (bit is clear
1325// in invalid_code) then move the entries for that 4K page from
1326// the dirty list to the clean list.
1327void clean_blocks(u_int page)
1328{
1329 struct ll_entry *head;
1330 inv_debug("INV: clean_blocks page=%d\n",page);
1331 head=jump_dirty[page];
1332 while(head!=NULL) {
1333 if(!invalid_code[head->vaddr>>12]) {
1334 // Don't restore blocks which are about to expire from the cache
1335 if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2))) {
1336 u_int start,end;
1337 if(verify_dirty((int)head->addr)) {
1338 //printf("Possibly Restore %x (%x)\n",head->vaddr, (int)head->addr);
1339 u_int i;
1340 u_int inv=0;
1341 get_bounds((int)head->addr,&start,&end);
4cb76aa4 1342 if(start-(u_int)rdram<RAM_SIZE) {
57871462 1343 for(i=(start-(u_int)rdram+0x80000000)>>12;i<=(end-1-(u_int)rdram+0x80000000)>>12;i++) {
1344 inv|=invalid_code[i];
1345 }
1346 }
63cb0298 1347#ifndef DISABLE_TLB
57871462 1348 if((signed int)head->vaddr>=(signed int)0xC0000000) {
1349 u_int addr = (head->vaddr+(memory_map[head->vaddr>>12]<<2));
1350 //printf("addr=%x start=%x end=%x\n",addr,start,end);
1351 if(addr<start||addr>=end) inv=1;
1352 }
63cb0298 1353#endif
4cb76aa4 1354 else if((signed int)head->vaddr>=(signed int)0x80000000+RAM_SIZE) {
57871462 1355 inv=1;
1356 }
1357 if(!inv) {
1358 void * clean_addr=(void *)get_clean_addr((int)head->addr);
1359 if((((u_int)clean_addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2))) {
1360 u_int ppage=page;
94d23bb9 1361#ifndef DISABLE_TLB
57871462 1362 if(page<2048&&tlb_LUT_r[head->vaddr>>12]) ppage=(tlb_LUT_r[head->vaddr>>12]^0x80000000)>>12;
94d23bb9 1363#endif
57871462 1364 inv_debug("INV: Restored %x (%x/%x)\n",head->vaddr, (int)head->addr, (int)clean_addr);
1365 //printf("page=%x, addr=%x\n",page,head->vaddr);
1366 //assert(head->vaddr>>12==(page|0x80000));
1367 ll_add_32(jump_in+ppage,head->vaddr,head->reg32,clean_addr);
1368 int *ht_bin=hash_table[((head->vaddr>>16)^head->vaddr)&0xFFFF];
1369 if(!head->reg32) {
1370 if(ht_bin[0]==head->vaddr) {
1371 ht_bin[1]=(int)clean_addr; // Replace existing entry
1372 }
1373 if(ht_bin[2]==head->vaddr) {
1374 ht_bin[3]=(int)clean_addr; // Replace existing entry
1375 }
1376 }
1377 }
1378 }
1379 }
1380 }
1381 }
1382 head=head->next;
1383 }
1384}
1385
1386
1387void mov_alloc(struct regstat *current,int i)
1388{
1389 // Note: Don't need to actually alloc the source registers
1390 if((~current->is32>>rs1[i])&1) {
1391 //alloc_reg64(current,i,rs1[i]);
1392 alloc_reg64(current,i,rt1[i]);
1393 current->is32&=~(1LL<<rt1[i]);
1394 } else {
1395 //alloc_reg(current,i,rs1[i]);
1396 alloc_reg(current,i,rt1[i]);
1397 current->is32|=(1LL<<rt1[i]);
1398 }
1399 clear_const(current,rs1[i]);
1400 clear_const(current,rt1[i]);
1401 dirty_reg(current,rt1[i]);
1402}
1403
1404void shiftimm_alloc(struct regstat *current,int i)
1405{
57871462 1406 if(opcode2[i]<=0x3) // SLL/SRL/SRA
1407 {
1408 if(rt1[i]) {
1409 if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1410 else lt1[i]=rs1[i];
1411 alloc_reg(current,i,rt1[i]);
1412 current->is32|=1LL<<rt1[i];
1413 dirty_reg(current,rt1[i]);
dc49e339 1414 if(is_const(current,rs1[i])) {
1415 int v=get_const(current,rs1[i]);
1416 if(opcode2[i]==0x00) set_const(current,rt1[i],v<<imm[i]);
1417 if(opcode2[i]==0x02) set_const(current,rt1[i],(u_int)v>>imm[i]);
1418 if(opcode2[i]==0x03) set_const(current,rt1[i],v>>imm[i]);
1419 }
1420 else clear_const(current,rt1[i]);
57871462 1421 }
1422 }
dc49e339 1423 else
1424 {
1425 clear_const(current,rs1[i]);
1426 clear_const(current,rt1[i]);
1427 }
1428
57871462 1429 if(opcode2[i]>=0x38&&opcode2[i]<=0x3b) // DSLL/DSRL/DSRA
1430 {
1431 if(rt1[i]) {
1432 if(rs1[i]) alloc_reg64(current,i,rs1[i]);
1433 alloc_reg64(current,i,rt1[i]);
1434 current->is32&=~(1LL<<rt1[i]);
1435 dirty_reg(current,rt1[i]);
1436 }
1437 }
1438 if(opcode2[i]==0x3c) // DSLL32
1439 {
1440 if(rt1[i]) {
1441 if(rs1[i]) alloc_reg(current,i,rs1[i]);
1442 alloc_reg64(current,i,rt1[i]);
1443 current->is32&=~(1LL<<rt1[i]);
1444 dirty_reg(current,rt1[i]);
1445 }
1446 }
1447 if(opcode2[i]==0x3e) // DSRL32
1448 {
1449 if(rt1[i]) {
1450 alloc_reg64(current,i,rs1[i]);
1451 if(imm[i]==32) {
1452 alloc_reg64(current,i,rt1[i]);
1453 current->is32&=~(1LL<<rt1[i]);
1454 } else {
1455 alloc_reg(current,i,rt1[i]);
1456 current->is32|=1LL<<rt1[i];
1457 }
1458 dirty_reg(current,rt1[i]);
1459 }
1460 }
1461 if(opcode2[i]==0x3f) // DSRA32
1462 {
1463 if(rt1[i]) {
1464 alloc_reg64(current,i,rs1[i]);
1465 alloc_reg(current,i,rt1[i]);
1466 current->is32|=1LL<<rt1[i];
1467 dirty_reg(current,rt1[i]);
1468 }
1469 }
1470}
1471
1472void shift_alloc(struct regstat *current,int i)
1473{
1474 if(rt1[i]) {
1475 if(opcode2[i]<=0x07) // SLLV/SRLV/SRAV
1476 {
1477 if(rs1[i]) alloc_reg(current,i,rs1[i]);
1478 if(rs2[i]) alloc_reg(current,i,rs2[i]);
1479 alloc_reg(current,i,rt1[i]);
e1190b87 1480 if(rt1[i]==rs2[i]) {
1481 alloc_reg_temp(current,i,-1);
1482 minimum_free_regs[i]=1;
1483 }
57871462 1484 current->is32|=1LL<<rt1[i];
1485 } else { // DSLLV/DSRLV/DSRAV
1486 if(rs1[i]) alloc_reg64(current,i,rs1[i]);
1487 if(rs2[i]) alloc_reg(current,i,rs2[i]);
1488 alloc_reg64(current,i,rt1[i]);
1489 current->is32&=~(1LL<<rt1[i]);
1490 if(opcode2[i]==0x16||opcode2[i]==0x17) // DSRLV and DSRAV need a temporary register
e1190b87 1491 {
57871462 1492 alloc_reg_temp(current,i,-1);
e1190b87 1493 minimum_free_regs[i]=1;
1494 }
57871462 1495 }
1496 clear_const(current,rs1[i]);
1497 clear_const(current,rs2[i]);
1498 clear_const(current,rt1[i]);
1499 dirty_reg(current,rt1[i]);
1500 }
1501}
1502
1503void alu_alloc(struct regstat *current,int i)
1504{
1505 if(opcode2[i]>=0x20&&opcode2[i]<=0x23) { // ADD/ADDU/SUB/SUBU
1506 if(rt1[i]) {
1507 if(rs1[i]&&rs2[i]) {
1508 alloc_reg(current,i,rs1[i]);
1509 alloc_reg(current,i,rs2[i]);
1510 }
1511 else {
1512 if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1513 if(rs2[i]&&needed_again(rs2[i],i)) alloc_reg(current,i,rs2[i]);
1514 }
1515 alloc_reg(current,i,rt1[i]);
1516 }
1517 current->is32|=1LL<<rt1[i];
1518 }
1519 if(opcode2[i]==0x2a||opcode2[i]==0x2b) { // SLT/SLTU
1520 if(rt1[i]) {
1521 if(!((current->is32>>rs1[i])&(current->is32>>rs2[i])&1))
1522 {
1523 alloc_reg64(current,i,rs1[i]);
1524 alloc_reg64(current,i,rs2[i]);
1525 alloc_reg(current,i,rt1[i]);
1526 } else {
1527 alloc_reg(current,i,rs1[i]);
1528 alloc_reg(current,i,rs2[i]);
1529 alloc_reg(current,i,rt1[i]);
1530 }
1531 }
1532 current->is32|=1LL<<rt1[i];
1533 }
1534 if(opcode2[i]>=0x24&&opcode2[i]<=0x27) { // AND/OR/XOR/NOR
1535 if(rt1[i]) {
1536 if(rs1[i]&&rs2[i]) {
1537 alloc_reg(current,i,rs1[i]);
1538 alloc_reg(current,i,rs2[i]);
1539 }
1540 else
1541 {
1542 if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1543 if(rs2[i]&&needed_again(rs2[i],i)) alloc_reg(current,i,rs2[i]);
1544 }
1545 alloc_reg(current,i,rt1[i]);
1546 if(!((current->is32>>rs1[i])&(current->is32>>rs2[i])&1))
1547 {
1548 if(!((current->uu>>rt1[i])&1)) {
1549 alloc_reg64(current,i,rt1[i]);
1550 }
1551 if(get_reg(current->regmap,rt1[i]|64)>=0) {
1552 if(rs1[i]&&rs2[i]) {
1553 alloc_reg64(current,i,rs1[i]);
1554 alloc_reg64(current,i,rs2[i]);
1555 }
1556 else
1557 {
1558 // Is is really worth it to keep 64-bit values in registers?
1559 #ifdef NATIVE_64BIT
1560 if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg64(current,i,rs1[i]);
1561 if(rs2[i]&&needed_again(rs2[i],i)) alloc_reg64(current,i,rs2[i]);
1562 #endif
1563 }
1564 }
1565 current->is32&=~(1LL<<rt1[i]);
1566 } else {
1567 current->is32|=1LL<<rt1[i];
1568 }
1569 }
1570 }
1571 if(opcode2[i]>=0x2c&&opcode2[i]<=0x2f) { // DADD/DADDU/DSUB/DSUBU
1572 if(rt1[i]) {
1573 if(rs1[i]&&rs2[i]) {
1574 if(!((current->uu>>rt1[i])&1)||get_reg(current->regmap,rt1[i]|64)>=0) {
1575 alloc_reg64(current,i,rs1[i]);
1576 alloc_reg64(current,i,rs2[i]);
1577 alloc_reg64(current,i,rt1[i]);
1578 } else {
1579 alloc_reg(current,i,rs1[i]);
1580 alloc_reg(current,i,rs2[i]);
1581 alloc_reg(current,i,rt1[i]);
1582 }
1583 }
1584 else {
1585 alloc_reg(current,i,rt1[i]);
1586 if(!((current->uu>>rt1[i])&1)||get_reg(current->regmap,rt1[i]|64)>=0) {
1587 // DADD used as move, or zeroing
1588 // If we have a 64-bit source, then make the target 64 bits too
1589 if(rs1[i]&&!((current->is32>>rs1[i])&1)) {
1590 if(get_reg(current->regmap,rs1[i])>=0) alloc_reg64(current,i,rs1[i]);
1591 alloc_reg64(current,i,rt1[i]);
1592 } else if(rs2[i]&&!((current->is32>>rs2[i])&1)) {
1593 if(get_reg(current->regmap,rs2[i])>=0) alloc_reg64(current,i,rs2[i]);
1594 alloc_reg64(current,i,rt1[i]);
1595 }
1596 if(opcode2[i]>=0x2e&&rs2[i]) {
1597 // DSUB used as negation - 64-bit result
1598 // If we have a 32-bit register, extend it to 64 bits
1599 if(get_reg(current->regmap,rs2[i])>=0) alloc_reg64(current,i,rs2[i]);
1600 alloc_reg64(current,i,rt1[i]);
1601 }
1602 }
1603 }
1604 if(rs1[i]&&rs2[i]) {
1605 current->is32&=~(1LL<<rt1[i]);
1606 } else if(rs1[i]) {
1607 current->is32&=~(1LL<<rt1[i]);
1608 if((current->is32>>rs1[i])&1)
1609 current->is32|=1LL<<rt1[i];
1610 } else if(rs2[i]) {
1611 current->is32&=~(1LL<<rt1[i]);
1612 if((current->is32>>rs2[i])&1)
1613 current->is32|=1LL<<rt1[i];
1614 } else {
1615 current->is32|=1LL<<rt1[i];
1616 }
1617 }
1618 }
1619 clear_const(current,rs1[i]);
1620 clear_const(current,rs2[i]);
1621 clear_const(current,rt1[i]);
1622 dirty_reg(current,rt1[i]);
1623}
1624
1625void imm16_alloc(struct regstat *current,int i)
1626{
1627 if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1628 else lt1[i]=rs1[i];
1629 if(rt1[i]) alloc_reg(current,i,rt1[i]);
1630 if(opcode[i]==0x18||opcode[i]==0x19) { // DADDI/DADDIU
1631 current->is32&=~(1LL<<rt1[i]);
1632 if(!((current->uu>>rt1[i])&1)||get_reg(current->regmap,rt1[i]|64)>=0) {
1633 // TODO: Could preserve the 32-bit flag if the immediate is zero
1634 alloc_reg64(current,i,rt1[i]);
1635 alloc_reg64(current,i,rs1[i]);
1636 }
1637 clear_const(current,rs1[i]);
1638 clear_const(current,rt1[i]);
1639 }
1640 else if(opcode[i]==0x0a||opcode[i]==0x0b) { // SLTI/SLTIU
1641 if((~current->is32>>rs1[i])&1) alloc_reg64(current,i,rs1[i]);
1642 current->is32|=1LL<<rt1[i];
1643 clear_const(current,rs1[i]);
1644 clear_const(current,rt1[i]);
1645 }
1646 else if(opcode[i]>=0x0c&&opcode[i]<=0x0e) { // ANDI/ORI/XORI
1647 if(((~current->is32>>rs1[i])&1)&&opcode[i]>0x0c) {
1648 if(rs1[i]!=rt1[i]) {
1649 if(needed_again(rs1[i],i)) alloc_reg64(current,i,rs1[i]);
1650 alloc_reg64(current,i,rt1[i]);
1651 current->is32&=~(1LL<<rt1[i]);
1652 }
1653 }
1654 else current->is32|=1LL<<rt1[i]; // ANDI clears upper bits
1655 if(is_const(current,rs1[i])) {
1656 int v=get_const(current,rs1[i]);
1657 if(opcode[i]==0x0c) set_const(current,rt1[i],v&imm[i]);
1658 if(opcode[i]==0x0d) set_const(current,rt1[i],v|imm[i]);
1659 if(opcode[i]==0x0e) set_const(current,rt1[i],v^imm[i]);
1660 }
1661 else clear_const(current,rt1[i]);
1662 }
1663 else if(opcode[i]==0x08||opcode[i]==0x09) { // ADDI/ADDIU
1664 if(is_const(current,rs1[i])) {
1665 int v=get_const(current,rs1[i]);
1666 set_const(current,rt1[i],v+imm[i]);
1667 }
1668 else clear_const(current,rt1[i]);
1669 current->is32|=1LL<<rt1[i];
1670 }
1671 else {
1672 set_const(current,rt1[i],((long long)((short)imm[i]))<<16); // LUI
1673 current->is32|=1LL<<rt1[i];
1674 }
1675 dirty_reg(current,rt1[i]);
1676}
1677
1678void load_alloc(struct regstat *current,int i)
1679{
1680 clear_const(current,rt1[i]);
1681 //if(rs1[i]!=rt1[i]&&needed_again(rs1[i],i)) clear_const(current,rs1[i]); // Does this help or hurt?
1682 if(!rs1[i]) current->u&=~1LL; // Allow allocating r0 if it's the source register
1683 if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
373d1d07 1684 if(rt1[i]&&!((current->u>>rt1[i])&1)) {
57871462 1685 alloc_reg(current,i,rt1[i]);
373d1d07 1686 assert(get_reg(current->regmap,rt1[i])>=0);
57871462 1687 if(opcode[i]==0x27||opcode[i]==0x37) // LWU/LD
1688 {
1689 current->is32&=~(1LL<<rt1[i]);
1690 alloc_reg64(current,i,rt1[i]);
1691 }
1692 else if(opcode[i]==0x1A||opcode[i]==0x1B) // LDL/LDR
1693 {
1694 current->is32&=~(1LL<<rt1[i]);
1695 alloc_reg64(current,i,rt1[i]);
1696 alloc_all(current,i);
1697 alloc_reg64(current,i,FTEMP);
e1190b87 1698 minimum_free_regs[i]=HOST_REGS;
57871462 1699 }
1700 else current->is32|=1LL<<rt1[i];
1701 dirty_reg(current,rt1[i]);
1702 // If using TLB, need a register for pointer to the mapping table
1703 if(using_tlb) alloc_reg(current,i,TLREG);
1704 // LWL/LWR need a temporary register for the old value
1705 if(opcode[i]==0x22||opcode[i]==0x26)
1706 {
1707 alloc_reg(current,i,FTEMP);
1708 alloc_reg_temp(current,i,-1);
e1190b87 1709 minimum_free_regs[i]=1;
57871462 1710 }
1711 }
1712 else
1713 {
373d1d07 1714 // Load to r0 or unneeded register (dummy load)
57871462 1715 // but we still need a register to calculate the address
535d208a 1716 if(opcode[i]==0x22||opcode[i]==0x26)
1717 {
1718 alloc_reg(current,i,FTEMP); // LWL/LWR need another temporary
1719 }
373d1d07 1720 // If using TLB, need a register for pointer to the mapping table
1721 if(using_tlb) alloc_reg(current,i,TLREG);
57871462 1722 alloc_reg_temp(current,i,-1);
e1190b87 1723 minimum_free_regs[i]=1;
535d208a 1724 if(opcode[i]==0x1A||opcode[i]==0x1B) // LDL/LDR
1725 {
1726 alloc_all(current,i);
1727 alloc_reg64(current,i,FTEMP);
e1190b87 1728 minimum_free_regs[i]=HOST_REGS;
535d208a 1729 }
57871462 1730 }
1731}
1732
1733void store_alloc(struct regstat *current,int i)
1734{
1735 clear_const(current,rs2[i]);
1736 if(!(rs2[i])) current->u&=~1LL; // Allow allocating r0 if necessary
1737 if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1738 alloc_reg(current,i,rs2[i]);
1739 if(opcode[i]==0x2c||opcode[i]==0x2d||opcode[i]==0x3f) { // 64-bit SDL/SDR/SD
1740 alloc_reg64(current,i,rs2[i]);
1741 if(rs2[i]) alloc_reg(current,i,FTEMP);
1742 }
1743 // If using TLB, need a register for pointer to the mapping table
1744 if(using_tlb) alloc_reg(current,i,TLREG);
1745 #if defined(HOST_IMM8)
1746 // On CPUs without 32-bit immediates we need a pointer to invalid_code
1747 else alloc_reg(current,i,INVCP);
1748 #endif
b7918751 1749 if(opcode[i]==0x2a||opcode[i]==0x2e||opcode[i]==0x2c||opcode[i]==0x2d) { // SWL/SWL/SDL/SDR
57871462 1750 alloc_reg(current,i,FTEMP);
1751 }
1752 // We need a temporary register for address generation
1753 alloc_reg_temp(current,i,-1);
e1190b87 1754 minimum_free_regs[i]=1;
57871462 1755}
1756
1757void c1ls_alloc(struct regstat *current,int i)
1758{
1759 //clear_const(current,rs1[i]); // FIXME
1760 clear_const(current,rt1[i]);
1761 if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1762 alloc_reg(current,i,CSREG); // Status
1763 alloc_reg(current,i,FTEMP);
1764 if(opcode[i]==0x35||opcode[i]==0x3d) { // 64-bit LDC1/SDC1
1765 alloc_reg64(current,i,FTEMP);
1766 }
1767 // If using TLB, need a register for pointer to the mapping table
1768 if(using_tlb) alloc_reg(current,i,TLREG);
1769 #if defined(HOST_IMM8)
1770 // On CPUs without 32-bit immediates we need a pointer to invalid_code
1771 else if((opcode[i]&0x3b)==0x39) // SWC1/SDC1
1772 alloc_reg(current,i,INVCP);
1773 #endif
1774 // We need a temporary register for address generation
1775 alloc_reg_temp(current,i,-1);
1776}
1777
b9b61529 1778void c2ls_alloc(struct regstat *current,int i)
1779{
1780 clear_const(current,rt1[i]);
1781 if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1782 alloc_reg(current,i,FTEMP);
1783 // If using TLB, need a register for pointer to the mapping table
1784 if(using_tlb) alloc_reg(current,i,TLREG);
1785 #if defined(HOST_IMM8)
1786 // On CPUs without 32-bit immediates we need a pointer to invalid_code
1787 else if((opcode[i]&0x3b)==0x3a) // SWC2/SDC2
1788 alloc_reg(current,i,INVCP);
1789 #endif
1790 // We need a temporary register for address generation
1791 alloc_reg_temp(current,i,-1);
e1190b87 1792 minimum_free_regs[i]=1;
b9b61529 1793}
1794
57871462 1795#ifndef multdiv_alloc
1796void multdiv_alloc(struct regstat *current,int i)
1797{
1798 // case 0x18: MULT
1799 // case 0x19: MULTU
1800 // case 0x1A: DIV
1801 // case 0x1B: DIVU
1802 // case 0x1C: DMULT
1803 // case 0x1D: DMULTU
1804 // case 0x1E: DDIV
1805 // case 0x1F: DDIVU
1806 clear_const(current,rs1[i]);
1807 clear_const(current,rs2[i]);
1808 if(rs1[i]&&rs2[i])
1809 {
1810 if((opcode2[i]&4)==0) // 32-bit
1811 {
1812 current->u&=~(1LL<<HIREG);
1813 current->u&=~(1LL<<LOREG);
1814 alloc_reg(current,i,HIREG);
1815 alloc_reg(current,i,LOREG);
1816 alloc_reg(current,i,rs1[i]);
1817 alloc_reg(current,i,rs2[i]);
1818 current->is32|=1LL<<HIREG;
1819 current->is32|=1LL<<LOREG;
1820 dirty_reg(current,HIREG);
1821 dirty_reg(current,LOREG);
1822 }
1823 else // 64-bit
1824 {
1825 current->u&=~(1LL<<HIREG);
1826 current->u&=~(1LL<<LOREG);
1827 current->uu&=~(1LL<<HIREG);
1828 current->uu&=~(1LL<<LOREG);
1829 alloc_reg64(current,i,HIREG);
1830 //if(HOST_REGS>10) alloc_reg64(current,i,LOREG);
1831 alloc_reg64(current,i,rs1[i]);
1832 alloc_reg64(current,i,rs2[i]);
1833 alloc_all(current,i);
1834 current->is32&=~(1LL<<HIREG);
1835 current->is32&=~(1LL<<LOREG);
1836 dirty_reg(current,HIREG);
1837 dirty_reg(current,LOREG);
e1190b87 1838 minimum_free_regs[i]=HOST_REGS;
57871462 1839 }
1840 }
1841 else
1842 {
1843 // Multiply by zero is zero.
1844 // MIPS does not have a divide by zero exception.
1845 // The result is undefined, we return zero.
1846 alloc_reg(current,i,HIREG);
1847 alloc_reg(current,i,LOREG);
1848 current->is32|=1LL<<HIREG;
1849 current->is32|=1LL<<LOREG;
1850 dirty_reg(current,HIREG);
1851 dirty_reg(current,LOREG);
1852 }
1853}
1854#endif
1855
1856void cop0_alloc(struct regstat *current,int i)
1857{
1858 if(opcode2[i]==0) // MFC0
1859 {
1860 if(rt1[i]) {
1861 clear_const(current,rt1[i]);
1862 alloc_all(current,i);
1863 alloc_reg(current,i,rt1[i]);
1864 current->is32|=1LL<<rt1[i];
1865 dirty_reg(current,rt1[i]);
1866 }
1867 }
1868 else if(opcode2[i]==4) // MTC0
1869 {
1870 if(rs1[i]){
1871 clear_const(current,rs1[i]);
1872 alloc_reg(current,i,rs1[i]);
1873 alloc_all(current,i);
1874 }
1875 else {
1876 alloc_all(current,i); // FIXME: Keep r0
1877 current->u&=~1LL;
1878 alloc_reg(current,i,0);
1879 }
1880 }
1881 else
1882 {
1883 // TLBR/TLBWI/TLBWR/TLBP/ERET
1884 assert(opcode2[i]==0x10);
1885 alloc_all(current,i);
1886 }
e1190b87 1887 minimum_free_regs[i]=HOST_REGS;
57871462 1888}
1889
1890void cop1_alloc(struct regstat *current,int i)
1891{
1892 alloc_reg(current,i,CSREG); // Load status
1893 if(opcode2[i]<3) // MFC1/DMFC1/CFC1
1894 {
7de557a6 1895 if(rt1[i]){
1896 clear_const(current,rt1[i]);
1897 if(opcode2[i]==1) {
1898 alloc_reg64(current,i,rt1[i]); // DMFC1
1899 current->is32&=~(1LL<<rt1[i]);
1900 }else{
1901 alloc_reg(current,i,rt1[i]); // MFC1/CFC1
1902 current->is32|=1LL<<rt1[i];
1903 }
1904 dirty_reg(current,rt1[i]);
57871462 1905 }
57871462 1906 alloc_reg_temp(current,i,-1);
1907 }
1908 else if(opcode2[i]>3) // MTC1/DMTC1/CTC1
1909 {
1910 if(rs1[i]){
1911 clear_const(current,rs1[i]);
1912 if(opcode2[i]==5)
1913 alloc_reg64(current,i,rs1[i]); // DMTC1
1914 else
1915 alloc_reg(current,i,rs1[i]); // MTC1/CTC1
1916 alloc_reg_temp(current,i,-1);
1917 }
1918 else {
1919 current->u&=~1LL;
1920 alloc_reg(current,i,0);
1921 alloc_reg_temp(current,i,-1);
1922 }
1923 }
e1190b87 1924 minimum_free_regs[i]=1;
57871462 1925}
1926void fconv_alloc(struct regstat *current,int i)
1927{
1928 alloc_reg(current,i,CSREG); // Load status
1929 alloc_reg_temp(current,i,-1);
e1190b87 1930 minimum_free_regs[i]=1;
57871462 1931}
1932void float_alloc(struct regstat *current,int i)
1933{
1934 alloc_reg(current,i,CSREG); // Load status
1935 alloc_reg_temp(current,i,-1);
e1190b87 1936 minimum_free_regs[i]=1;
57871462 1937}
b9b61529 1938void c2op_alloc(struct regstat *current,int i)
1939{
1940 alloc_reg_temp(current,i,-1);
1941}
57871462 1942void fcomp_alloc(struct regstat *current,int i)
1943{
1944 alloc_reg(current,i,CSREG); // Load status
1945 alloc_reg(current,i,FSREG); // Load flags
1946 dirty_reg(current,FSREG); // Flag will be modified
1947 alloc_reg_temp(current,i,-1);
e1190b87 1948 minimum_free_regs[i]=1;
57871462 1949}
1950
1951void syscall_alloc(struct regstat *current,int i)
1952{
1953 alloc_cc(current,i);
1954 dirty_reg(current,CCREG);
1955 alloc_all(current,i);
e1190b87 1956 minimum_free_regs[i]=HOST_REGS;
57871462 1957 current->isconst=0;
1958}
1959
1960void delayslot_alloc(struct regstat *current,int i)
1961{
1962 switch(itype[i]) {
1963 case UJUMP:
1964 case CJUMP:
1965 case SJUMP:
1966 case RJUMP:
1967 case FJUMP:
1968 case SYSCALL:
7139f3c8 1969 case HLECALL:
57871462 1970 case SPAN:
1971 assem_debug("jump in the delay slot. this shouldn't happen.\n");//exit(1);
1972 printf("Disabled speculative precompilation\n");
1973 stop_after_jal=1;
1974 break;
1975 case IMM16:
1976 imm16_alloc(current,i);
1977 break;
1978 case LOAD:
1979 case LOADLR:
1980 load_alloc(current,i);
1981 break;
1982 case STORE:
1983 case STORELR:
1984 store_alloc(current,i);
1985 break;
1986 case ALU:
1987 alu_alloc(current,i);
1988 break;
1989 case SHIFT:
1990 shift_alloc(current,i);
1991 break;
1992 case MULTDIV:
1993 multdiv_alloc(current,i);
1994 break;
1995 case SHIFTIMM:
1996 shiftimm_alloc(current,i);
1997 break;
1998 case MOV:
1999 mov_alloc(current,i);
2000 break;
2001 case COP0:
2002 cop0_alloc(current,i);
2003 break;
2004 case COP1:
b9b61529 2005 case COP2:
57871462 2006 cop1_alloc(current,i);
2007 break;
2008 case C1LS:
2009 c1ls_alloc(current,i);
2010 break;
b9b61529 2011 case C2LS:
2012 c2ls_alloc(current,i);
2013 break;
57871462 2014 case FCONV:
2015 fconv_alloc(current,i);
2016 break;
2017 case FLOAT:
2018 float_alloc(current,i);
2019 break;
2020 case FCOMP:
2021 fcomp_alloc(current,i);
2022 break;
b9b61529 2023 case C2OP:
2024 c2op_alloc(current,i);
2025 break;
57871462 2026 }
2027}
2028
2029// Special case where a branch and delay slot span two pages in virtual memory
2030static void pagespan_alloc(struct regstat *current,int i)
2031{
2032 current->isconst=0;
2033 current->wasconst=0;
2034 regs[i].wasconst=0;
e1190b87 2035 minimum_free_regs[i]=HOST_REGS;
57871462 2036 alloc_all(current,i);
2037 alloc_cc(current,i);
2038 dirty_reg(current,CCREG);
2039 if(opcode[i]==3) // JAL
2040 {
2041 alloc_reg(current,i,31);
2042 dirty_reg(current,31);
2043 }
2044 if(opcode[i]==0&&(opcode2[i]&0x3E)==8) // JR/JALR
2045 {
2046 alloc_reg(current,i,rs1[i]);
5067f341 2047 if (rt1[i]!=0) {
2048 alloc_reg(current,i,rt1[i]);
2049 dirty_reg(current,rt1[i]);
57871462 2050 }
2051 }
2052 if((opcode[i]&0x2E)==4) // BEQ/BNE/BEQL/BNEL
2053 {
2054 if(rs1[i]) alloc_reg(current,i,rs1[i]);
2055 if(rs2[i]) alloc_reg(current,i,rs2[i]);
2056 if(!((current->is32>>rs1[i])&(current->is32>>rs2[i])&1))
2057 {
2058 if(rs1[i]) alloc_reg64(current,i,rs1[i]);
2059 if(rs2[i]) alloc_reg64(current,i,rs2[i]);
2060 }
2061 }
2062 else
2063 if((opcode[i]&0x2E)==6) // BLEZ/BGTZ/BLEZL/BGTZL
2064 {
2065 if(rs1[i]) alloc_reg(current,i,rs1[i]);
2066 if(!((current->is32>>rs1[i])&1))
2067 {
2068 if(rs1[i]) alloc_reg64(current,i,rs1[i]);
2069 }
2070 }
2071 else
2072 if(opcode[i]==0x11) // BC1
2073 {
2074 alloc_reg(current,i,FSREG);
2075 alloc_reg(current,i,CSREG);
2076 }
2077 //else ...
2078}
2079
2080add_stub(int type,int addr,int retaddr,int a,int b,int c,int d,int e)
2081{
2082 stubs[stubcount][0]=type;
2083 stubs[stubcount][1]=addr;
2084 stubs[stubcount][2]=retaddr;
2085 stubs[stubcount][3]=a;
2086 stubs[stubcount][4]=b;
2087 stubs[stubcount][5]=c;
2088 stubs[stubcount][6]=d;
2089 stubs[stubcount][7]=e;
2090 stubcount++;
2091}
2092
2093// Write out a single register
2094void wb_register(signed char r,signed char regmap[],uint64_t dirty,uint64_t is32)
2095{
2096 int hr;
2097 for(hr=0;hr<HOST_REGS;hr++) {
2098 if(hr!=EXCLUDE_REG) {
2099 if((regmap[hr]&63)==r) {
2100 if((dirty>>hr)&1) {
2101 if(regmap[hr]<64) {
2102 emit_storereg(r,hr);
24385cae 2103#ifndef FORCE32
57871462 2104 if((is32>>regmap[hr])&1) {
2105 emit_sarimm(hr,31,hr);
2106 emit_storereg(r|64,hr);
2107 }
24385cae 2108#endif
57871462 2109 }else{
2110 emit_storereg(r|64,hr);
2111 }
2112 }
2113 }
2114 }
2115 }
2116}
2117
2118int mchecksum()
2119{
2120 //if(!tracedebug) return 0;
2121 int i;
2122 int sum=0;
2123 for(i=0;i<2097152;i++) {
2124 unsigned int temp=sum;
2125 sum<<=1;
2126 sum|=(~temp)>>31;
2127 sum^=((u_int *)rdram)[i];
2128 }
2129 return sum;
2130}
2131int rchecksum()
2132{
2133 int i;
2134 int sum=0;
2135 for(i=0;i<64;i++)
2136 sum^=((u_int *)reg)[i];
2137 return sum;
2138}
57871462 2139void rlist()
2140{
2141 int i;
2142 printf("TRACE: ");
2143 for(i=0;i<32;i++)
2144 printf("r%d:%8x%8x ",i,((int *)(reg+i))[1],((int *)(reg+i))[0]);
2145 printf("\n");
3d624f89 2146#ifndef DISABLE_COP1
57871462 2147 printf("TRACE: ");
2148 for(i=0;i<32;i++)
2149 printf("f%d:%8x%8x ",i,((int*)reg_cop1_simple[i])[1],*((int*)reg_cop1_simple[i]));
2150 printf("\n");
3d624f89 2151#endif
57871462 2152}
2153
2154void enabletrace()
2155{
2156 tracedebug=1;
2157}
2158
2159void memdebug(int i)
2160{
2161 //printf("TRACE: count=%d next=%d (checksum %x) lo=%8x%8x\n",Count,next_interupt,mchecksum(),(int)(reg[LOREG]>>32),(int)reg[LOREG]);
2162 //printf("TRACE: count=%d next=%d (rchecksum %x)\n",Count,next_interupt,rchecksum());
2163 //rlist();
2164 //if(tracedebug) {
2165 //if(Count>=-2084597794) {
2166 if((signed int)Count>=-2084597794&&(signed int)Count<0) {
2167 //if(0) {
2168 printf("TRACE: count=%d next=%d (checksum %x)\n",Count,next_interupt,mchecksum());
2169 //printf("TRACE: count=%d next=%d (checksum %x) Status=%x\n",Count,next_interupt,mchecksum(),Status);
2170 //printf("TRACE: count=%d next=%d (checksum %x) hi=%8x%8x\n",Count,next_interupt,mchecksum(),(int)(reg[HIREG]>>32),(int)reg[HIREG]);
2171 rlist();
2172 #ifdef __i386__
2173 printf("TRACE: %x\n",(&i)[-1]);
2174 #endif
2175 #ifdef __arm__
2176 int j;
2177 printf("TRACE: %x \n",(&j)[10]);
2178 printf("TRACE: %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x\n",(&j)[1],(&j)[2],(&j)[3],(&j)[4],(&j)[5],(&j)[6],(&j)[7],(&j)[8],(&j)[9],(&j)[10],(&j)[11],(&j)[12],(&j)[13],(&j)[14],(&j)[15],(&j)[16],(&j)[17],(&j)[18],(&j)[19],(&j)[20]);
2179 #endif
2180 //fflush(stdout);
2181 }
2182 //printf("TRACE: %x\n",(&i)[-1]);
2183}
2184
2185void tlb_debug(u_int cause, u_int addr, u_int iaddr)
2186{
2187 printf("TLB Exception: instruction=%x addr=%x cause=%x\n",iaddr, addr, cause);
2188}
2189
2190void alu_assemble(int i,struct regstat *i_regs)
2191{
2192 if(opcode2[i]>=0x20&&opcode2[i]<=0x23) { // ADD/ADDU/SUB/SUBU
2193 if(rt1[i]) {
2194 signed char s1,s2,t;
2195 t=get_reg(i_regs->regmap,rt1[i]);
2196 if(t>=0) {
2197 s1=get_reg(i_regs->regmap,rs1[i]);
2198 s2=get_reg(i_regs->regmap,rs2[i]);
2199 if(rs1[i]&&rs2[i]) {
2200 assert(s1>=0);
2201 assert(s2>=0);
2202 if(opcode2[i]&2) emit_sub(s1,s2,t);
2203 else emit_add(s1,s2,t);
2204 }
2205 else if(rs1[i]) {
2206 if(s1>=0) emit_mov(s1,t);
2207 else emit_loadreg(rs1[i],t);
2208 }
2209 else if(rs2[i]) {
2210 if(s2>=0) {
2211 if(opcode2[i]&2) emit_neg(s2,t);
2212 else emit_mov(s2,t);
2213 }
2214 else {
2215 emit_loadreg(rs2[i],t);
2216 if(opcode2[i]&2) emit_neg(t,t);
2217 }
2218 }
2219 else emit_zeroreg(t);
2220 }
2221 }
2222 }
2223 if(opcode2[i]>=0x2c&&opcode2[i]<=0x2f) { // DADD/DADDU/DSUB/DSUBU
2224 if(rt1[i]) {
2225 signed char s1l,s2l,s1h,s2h,tl,th;
2226 tl=get_reg(i_regs->regmap,rt1[i]);
2227 th=get_reg(i_regs->regmap,rt1[i]|64);
2228 if(tl>=0) {
2229 s1l=get_reg(i_regs->regmap,rs1[i]);
2230 s2l=get_reg(i_regs->regmap,rs2[i]);
2231 s1h=get_reg(i_regs->regmap,rs1[i]|64);
2232 s2h=get_reg(i_regs->regmap,rs2[i]|64);
2233 if(rs1[i]&&rs2[i]) {
2234 assert(s1l>=0);
2235 assert(s2l>=0);
2236 if(opcode2[i]&2) emit_subs(s1l,s2l,tl);
2237 else emit_adds(s1l,s2l,tl);
2238 if(th>=0) {
2239 #ifdef INVERTED_CARRY
2240 if(opcode2[i]&2) {if(s1h!=th) emit_mov(s1h,th);emit_sbb(th,s2h);}
2241 #else
2242 if(opcode2[i]&2) emit_sbc(s1h,s2h,th);
2243 #endif
2244 else emit_add(s1h,s2h,th);
2245 }
2246 }
2247 else if(rs1[i]) {
2248 if(s1l>=0) emit_mov(s1l,tl);
2249 else emit_loadreg(rs1[i],tl);
2250 if(th>=0) {
2251 if(s1h>=0) emit_mov(s1h,th);
2252 else emit_loadreg(rs1[i]|64,th);
2253 }
2254 }
2255 else if(rs2[i]) {
2256 if(s2l>=0) {
2257 if(opcode2[i]&2) emit_negs(s2l,tl);
2258 else emit_mov(s2l,tl);
2259 }
2260 else {
2261 emit_loadreg(rs2[i],tl);
2262 if(opcode2[i]&2) emit_negs(tl,tl);
2263 }
2264 if(th>=0) {
2265 #ifdef INVERTED_CARRY
2266 if(s2h>=0) emit_mov(s2h,th);
2267 else emit_loadreg(rs2[i]|64,th);
2268 if(opcode2[i]&2) {
2269 emit_adcimm(-1,th); // x86 has inverted carry flag
2270 emit_not(th,th);
2271 }
2272 #else
2273 if(opcode2[i]&2) {
2274 if(s2h>=0) emit_rscimm(s2h,0,th);
2275 else {
2276 emit_loadreg(rs2[i]|64,th);
2277 emit_rscimm(th,0,th);
2278 }
2279 }else{
2280 if(s2h>=0) emit_mov(s2h,th);
2281 else emit_loadreg(rs2[i]|64,th);
2282 }
2283 #endif
2284 }
2285 }
2286 else {
2287 emit_zeroreg(tl);
2288 if(th>=0) emit_zeroreg(th);
2289 }
2290 }
2291 }
2292 }
2293 if(opcode2[i]==0x2a||opcode2[i]==0x2b) { // SLT/SLTU
2294 if(rt1[i]) {
2295 signed char s1l,s1h,s2l,s2h,t;
2296 if(!((i_regs->was32>>rs1[i])&(i_regs->was32>>rs2[i])&1))
2297 {
2298 t=get_reg(i_regs->regmap,rt1[i]);
2299 //assert(t>=0);
2300 if(t>=0) {
2301 s1l=get_reg(i_regs->regmap,rs1[i]);
2302 s1h=get_reg(i_regs->regmap,rs1[i]|64);
2303 s2l=get_reg(i_regs->regmap,rs2[i]);
2304 s2h=get_reg(i_regs->regmap,rs2[i]|64);
2305 if(rs2[i]==0) // rx<r0
2306 {
2307 assert(s1h>=0);
2308 if(opcode2[i]==0x2a) // SLT
2309 emit_shrimm(s1h,31,t);
2310 else // SLTU (unsigned can not be less than zero)
2311 emit_zeroreg(t);
2312 }
2313 else if(rs1[i]==0) // r0<rx
2314 {
2315 assert(s2h>=0);
2316 if(opcode2[i]==0x2a) // SLT
2317 emit_set_gz64_32(s2h,s2l,t);
2318 else // SLTU (set if not zero)
2319 emit_set_nz64_32(s2h,s2l,t);
2320 }
2321 else {
2322 assert(s1l>=0);assert(s1h>=0);
2323 assert(s2l>=0);assert(s2h>=0);
2324 if(opcode2[i]==0x2a) // SLT
2325 emit_set_if_less64_32(s1h,s1l,s2h,s2l,t);
2326 else // SLTU
2327 emit_set_if_carry64_32(s1h,s1l,s2h,s2l,t);
2328 }
2329 }
2330 } else {
2331 t=get_reg(i_regs->regmap,rt1[i]);
2332 //assert(t>=0);
2333 if(t>=0) {
2334 s1l=get_reg(i_regs->regmap,rs1[i]);
2335 s2l=get_reg(i_regs->regmap,rs2[i]);
2336 if(rs2[i]==0) // rx<r0
2337 {
2338 assert(s1l>=0);
2339 if(opcode2[i]==0x2a) // SLT
2340 emit_shrimm(s1l,31,t);
2341 else // SLTU (unsigned can not be less than zero)
2342 emit_zeroreg(t);
2343 }
2344 else if(rs1[i]==0) // r0<rx
2345 {
2346 assert(s2l>=0);
2347 if(opcode2[i]==0x2a) // SLT
2348 emit_set_gz32(s2l,t);
2349 else // SLTU (set if not zero)
2350 emit_set_nz32(s2l,t);
2351 }
2352 else{
2353 assert(s1l>=0);assert(s2l>=0);
2354 if(opcode2[i]==0x2a) // SLT
2355 emit_set_if_less32(s1l,s2l,t);
2356 else // SLTU
2357 emit_set_if_carry32(s1l,s2l,t);
2358 }
2359 }
2360 }
2361 }
2362 }
2363 if(opcode2[i]>=0x24&&opcode2[i]<=0x27) { // AND/OR/XOR/NOR
2364 if(rt1[i]) {
2365 signed char s1l,s1h,s2l,s2h,th,tl;
2366 tl=get_reg(i_regs->regmap,rt1[i]);
2367 th=get_reg(i_regs->regmap,rt1[i]|64);
2368 if(!((i_regs->was32>>rs1[i])&(i_regs->was32>>rs2[i])&1)&&th>=0)
2369 {
2370 assert(tl>=0);
2371 if(tl>=0) {
2372 s1l=get_reg(i_regs->regmap,rs1[i]);
2373 s1h=get_reg(i_regs->regmap,rs1[i]|64);
2374 s2l=get_reg(i_regs->regmap,rs2[i]);
2375 s2h=get_reg(i_regs->regmap,rs2[i]|64);
2376 if(rs1[i]&&rs2[i]) {
2377 assert(s1l>=0);assert(s1h>=0);
2378 assert(s2l>=0);assert(s2h>=0);
2379 if(opcode2[i]==0x24) { // AND
2380 emit_and(s1l,s2l,tl);
2381 emit_and(s1h,s2h,th);
2382 } else
2383 if(opcode2[i]==0x25) { // OR
2384 emit_or(s1l,s2l,tl);
2385 emit_or(s1h,s2h,th);
2386 } else
2387 if(opcode2[i]==0x26) { // XOR
2388 emit_xor(s1l,s2l,tl);
2389 emit_xor(s1h,s2h,th);
2390 } else
2391 if(opcode2[i]==0x27) { // NOR
2392 emit_or(s1l,s2l,tl);
2393 emit_or(s1h,s2h,th);
2394 emit_not(tl,tl);
2395 emit_not(th,th);
2396 }
2397 }
2398 else
2399 {
2400 if(opcode2[i]==0x24) { // AND
2401 emit_zeroreg(tl);
2402 emit_zeroreg(th);
2403 } else
2404 if(opcode2[i]==0x25||opcode2[i]==0x26) { // OR/XOR
2405 if(rs1[i]){
2406 if(s1l>=0) emit_mov(s1l,tl);
2407 else emit_loadreg(rs1[i],tl);
2408 if(s1h>=0) emit_mov(s1h,th);
2409 else emit_loadreg(rs1[i]|64,th);
2410 }
2411 else
2412 if(rs2[i]){
2413 if(s2l>=0) emit_mov(s2l,tl);
2414 else emit_loadreg(rs2[i],tl);
2415 if(s2h>=0) emit_mov(s2h,th);
2416 else emit_loadreg(rs2[i]|64,th);
2417 }
2418 else{
2419 emit_zeroreg(tl);
2420 emit_zeroreg(th);
2421 }
2422 } else
2423 if(opcode2[i]==0x27) { // NOR
2424 if(rs1[i]){
2425 if(s1l>=0) emit_not(s1l,tl);
2426 else{
2427 emit_loadreg(rs1[i],tl);
2428 emit_not(tl,tl);
2429 }
2430 if(s1h>=0) emit_not(s1h,th);
2431 else{
2432 emit_loadreg(rs1[i]|64,th);
2433 emit_not(th,th);
2434 }
2435 }
2436 else
2437 if(rs2[i]){
2438 if(s2l>=0) emit_not(s2l,tl);
2439 else{
2440 emit_loadreg(rs2[i],tl);
2441 emit_not(tl,tl);
2442 }
2443 if(s2h>=0) emit_not(s2h,th);
2444 else{
2445 emit_loadreg(rs2[i]|64,th);
2446 emit_not(th,th);
2447 }
2448 }
2449 else {
2450 emit_movimm(-1,tl);
2451 emit_movimm(-1,th);
2452 }
2453 }
2454 }
2455 }
2456 }
2457 else
2458 {
2459 // 32 bit
2460 if(tl>=0) {
2461 s1l=get_reg(i_regs->regmap,rs1[i]);
2462 s2l=get_reg(i_regs->regmap,rs2[i]);
2463 if(rs1[i]&&rs2[i]) {
2464 assert(s1l>=0);
2465 assert(s2l>=0);
2466 if(opcode2[i]==0x24) { // AND
2467 emit_and(s1l,s2l,tl);
2468 } else
2469 if(opcode2[i]==0x25) { // OR
2470 emit_or(s1l,s2l,tl);
2471 } else
2472 if(opcode2[i]==0x26) { // XOR
2473 emit_xor(s1l,s2l,tl);
2474 } else
2475 if(opcode2[i]==0x27) { // NOR
2476 emit_or(s1l,s2l,tl);
2477 emit_not(tl,tl);
2478 }
2479 }
2480 else
2481 {
2482 if(opcode2[i]==0x24) { // AND
2483 emit_zeroreg(tl);
2484 } else
2485 if(opcode2[i]==0x25||opcode2[i]==0x26) { // OR/XOR
2486 if(rs1[i]){
2487 if(s1l>=0) emit_mov(s1l,tl);
2488 else emit_loadreg(rs1[i],tl); // CHECK: regmap_entry?
2489 }
2490 else
2491 if(rs2[i]){
2492 if(s2l>=0) emit_mov(s2l,tl);
2493 else emit_loadreg(rs2[i],tl); // CHECK: regmap_entry?
2494 }
2495 else emit_zeroreg(tl);
2496 } else
2497 if(opcode2[i]==0x27) { // NOR
2498 if(rs1[i]){
2499 if(s1l>=0) emit_not(s1l,tl);
2500 else {
2501 emit_loadreg(rs1[i],tl);
2502 emit_not(tl,tl);
2503 }
2504 }
2505 else
2506 if(rs2[i]){
2507 if(s2l>=0) emit_not(s2l,tl);
2508 else {
2509 emit_loadreg(rs2[i],tl);
2510 emit_not(tl,tl);
2511 }
2512 }
2513 else emit_movimm(-1,tl);
2514 }
2515 }
2516 }
2517 }
2518 }
2519 }
2520}
2521
2522void imm16_assemble(int i,struct regstat *i_regs)
2523{
2524 if (opcode[i]==0x0f) { // LUI
2525 if(rt1[i]) {
2526 signed char t;
2527 t=get_reg(i_regs->regmap,rt1[i]);
2528 //assert(t>=0);
2529 if(t>=0) {
2530 if(!((i_regs->isconst>>t)&1))
2531 emit_movimm(imm[i]<<16,t);
2532 }
2533 }
2534 }
2535 if(opcode[i]==0x08||opcode[i]==0x09) { // ADDI/ADDIU
2536 if(rt1[i]) {
2537 signed char s,t;
2538 t=get_reg(i_regs->regmap,rt1[i]);
2539 s=get_reg(i_regs->regmap,rs1[i]);
2540 if(rs1[i]) {
2541 //assert(t>=0);
2542 //assert(s>=0);
2543 if(t>=0) {
2544 if(!((i_regs->isconst>>t)&1)) {
2545 if(s<0) {
2546 if(i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2547 emit_addimm(t,imm[i],t);
2548 }else{
2549 if(!((i_regs->wasconst>>s)&1))
2550 emit_addimm(s,imm[i],t);
2551 else
2552 emit_movimm(constmap[i][s]+imm[i],t);
2553 }
2554 }
2555 }
2556 } else {
2557 if(t>=0) {
2558 if(!((i_regs->isconst>>t)&1))
2559 emit_movimm(imm[i],t);
2560 }
2561 }
2562 }
2563 }
2564 if(opcode[i]==0x18||opcode[i]==0x19) { // DADDI/DADDIU
2565 if(rt1[i]) {
2566 signed char sh,sl,th,tl;
2567 th=get_reg(i_regs->regmap,rt1[i]|64);
2568 tl=get_reg(i_regs->regmap,rt1[i]);
2569 sh=get_reg(i_regs->regmap,rs1[i]|64);
2570 sl=get_reg(i_regs->regmap,rs1[i]);
2571 if(tl>=0) {
2572 if(rs1[i]) {
2573 assert(sh>=0);
2574 assert(sl>=0);
2575 if(th>=0) {
2576 emit_addimm64_32(sh,sl,imm[i],th,tl);
2577 }
2578 else {
2579 emit_addimm(sl,imm[i],tl);
2580 }
2581 } else {
2582 emit_movimm(imm[i],tl);
2583 if(th>=0) emit_movimm(((signed int)imm[i])>>31,th);
2584 }
2585 }
2586 }
2587 }
2588 else if(opcode[i]==0x0a||opcode[i]==0x0b) { // SLTI/SLTIU
2589 if(rt1[i]) {
2590 //assert(rs1[i]!=0); // r0 might be valid, but it's probably a bug
2591 signed char sh,sl,t;
2592 t=get_reg(i_regs->regmap,rt1[i]);
2593 sh=get_reg(i_regs->regmap,rs1[i]|64);
2594 sl=get_reg(i_regs->regmap,rs1[i]);
2595 //assert(t>=0);
2596 if(t>=0) {
2597 if(rs1[i]>0) {
2598 if(sh<0) assert((i_regs->was32>>rs1[i])&1);
2599 if(sh<0||((i_regs->was32>>rs1[i])&1)) {
2600 if(opcode[i]==0x0a) { // SLTI
2601 if(sl<0) {
2602 if(i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2603 emit_slti32(t,imm[i],t);
2604 }else{
2605 emit_slti32(sl,imm[i],t);
2606 }
2607 }
2608 else { // SLTIU
2609 if(sl<0) {
2610 if(i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2611 emit_sltiu32(t,imm[i],t);
2612 }else{
2613 emit_sltiu32(sl,imm[i],t);
2614 }
2615 }
2616 }else{ // 64-bit
2617 assert(sl>=0);
2618 if(opcode[i]==0x0a) // SLTI
2619 emit_slti64_32(sh,sl,imm[i],t);
2620 else // SLTIU
2621 emit_sltiu64_32(sh,sl,imm[i],t);
2622 }
2623 }else{
2624 // SLTI(U) with r0 is just stupid,
2625 // nonetheless examples can be found
2626 if(opcode[i]==0x0a) // SLTI
2627 if(0<imm[i]) emit_movimm(1,t);
2628 else emit_zeroreg(t);
2629 else // SLTIU
2630 {
2631 if(imm[i]) emit_movimm(1,t);
2632 else emit_zeroreg(t);
2633 }
2634 }
2635 }
2636 }
2637 }
2638 else if(opcode[i]>=0x0c&&opcode[i]<=0x0e) { // ANDI/ORI/XORI
2639 if(rt1[i]) {
2640 signed char sh,sl,th,tl;
2641 th=get_reg(i_regs->regmap,rt1[i]|64);
2642 tl=get_reg(i_regs->regmap,rt1[i]);
2643 sh=get_reg(i_regs->regmap,rs1[i]|64);
2644 sl=get_reg(i_regs->regmap,rs1[i]);
2645 if(tl>=0 && !((i_regs->isconst>>tl)&1)) {
2646 if(opcode[i]==0x0c) //ANDI
2647 {
2648 if(rs1[i]) {
2649 if(sl<0) {
2650 if(i_regs->regmap_entry[tl]!=rs1[i]) emit_loadreg(rs1[i],tl);
2651 emit_andimm(tl,imm[i],tl);
2652 }else{
2653 if(!((i_regs->wasconst>>sl)&1))
2654 emit_andimm(sl,imm[i],tl);
2655 else
2656 emit_movimm(constmap[i][sl]&imm[i],tl);
2657 }
2658 }
2659 else
2660 emit_zeroreg(tl);
2661 if(th>=0) emit_zeroreg(th);
2662 }
2663 else
2664 {
2665 if(rs1[i]) {
2666 if(sl<0) {
2667 if(i_regs->regmap_entry[tl]!=rs1[i]) emit_loadreg(rs1[i],tl);
2668 }
2669 if(th>=0) {
2670 if(sh<0) {
2671 emit_loadreg(rs1[i]|64,th);
2672 }else{
2673 emit_mov(sh,th);
2674 }
2675 }
2676 if(opcode[i]==0x0d) //ORI
2677 if(sl<0) {
2678 emit_orimm(tl,imm[i],tl);
2679 }else{
2680 if(!((i_regs->wasconst>>sl)&1))
2681 emit_orimm(sl,imm[i],tl);
2682 else
2683 emit_movimm(constmap[i][sl]|imm[i],tl);
2684 }
2685 if(opcode[i]==0x0e) //XORI
2686 if(sl<0) {
2687 emit_xorimm(tl,imm[i],tl);
2688 }else{
2689 if(!((i_regs->wasconst>>sl)&1))
2690 emit_xorimm(sl,imm[i],tl);
2691 else
2692 emit_movimm(constmap[i][sl]^imm[i],tl);
2693 }
2694 }
2695 else {
2696 emit_movimm(imm[i],tl);
2697 if(th>=0) emit_zeroreg(th);
2698 }
2699 }
2700 }
2701 }
2702 }
2703}
2704
2705void shiftimm_assemble(int i,struct regstat *i_regs)
2706{
2707 if(opcode2[i]<=0x3) // SLL/SRL/SRA
2708 {
2709 if(rt1[i]) {
2710 signed char s,t;
2711 t=get_reg(i_regs->regmap,rt1[i]);
2712 s=get_reg(i_regs->regmap,rs1[i]);
2713 //assert(t>=0);
dc49e339 2714 if(t>=0&&!((i_regs->isconst>>t)&1)){
57871462 2715 if(rs1[i]==0)
2716 {
2717 emit_zeroreg(t);
2718 }
2719 else
2720 {
2721 if(s<0&&i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2722 if(imm[i]) {
2723 if(opcode2[i]==0) // SLL
2724 {
2725 emit_shlimm(s<0?t:s,imm[i],t);
2726 }
2727 if(opcode2[i]==2) // SRL
2728 {
2729 emit_shrimm(s<0?t:s,imm[i],t);
2730 }
2731 if(opcode2[i]==3) // SRA
2732 {
2733 emit_sarimm(s<0?t:s,imm[i],t);
2734 }
2735 }else{
2736 // Shift by zero
2737 if(s>=0 && s!=t) emit_mov(s,t);
2738 }
2739 }
2740 }
2741 //emit_storereg(rt1[i],t); //DEBUG
2742 }
2743 }
2744 if(opcode2[i]>=0x38&&opcode2[i]<=0x3b) // DSLL/DSRL/DSRA
2745 {
2746 if(rt1[i]) {
2747 signed char sh,sl,th,tl;
2748 th=get_reg(i_regs->regmap,rt1[i]|64);
2749 tl=get_reg(i_regs->regmap,rt1[i]);
2750 sh=get_reg(i_regs->regmap,rs1[i]|64);
2751 sl=get_reg(i_regs->regmap,rs1[i]);
2752 if(tl>=0) {
2753 if(rs1[i]==0)
2754 {
2755 emit_zeroreg(tl);
2756 if(th>=0) emit_zeroreg(th);
2757 }
2758 else
2759 {
2760 assert(sl>=0);
2761 assert(sh>=0);
2762 if(imm[i]) {
2763 if(opcode2[i]==0x38) // DSLL
2764 {
2765 if(th>=0) emit_shldimm(sh,sl,imm[i],th);
2766 emit_shlimm(sl,imm[i],tl);
2767 }
2768 if(opcode2[i]==0x3a) // DSRL
2769 {
2770 emit_shrdimm(sl,sh,imm[i],tl);
2771 if(th>=0) emit_shrimm(sh,imm[i],th);
2772 }
2773 if(opcode2[i]==0x3b) // DSRA
2774 {
2775 emit_shrdimm(sl,sh,imm[i],tl);
2776 if(th>=0) emit_sarimm(sh,imm[i],th);
2777 }
2778 }else{
2779 // Shift by zero
2780 if(sl!=tl) emit_mov(sl,tl);
2781 if(th>=0&&sh!=th) emit_mov(sh,th);
2782 }
2783 }
2784 }
2785 }
2786 }
2787 if(opcode2[i]==0x3c) // DSLL32
2788 {
2789 if(rt1[i]) {
2790 signed char sl,tl,th;
2791 tl=get_reg(i_regs->regmap,rt1[i]);
2792 th=get_reg(i_regs->regmap,rt1[i]|64);
2793 sl=get_reg(i_regs->regmap,rs1[i]);
2794 if(th>=0||tl>=0){
2795 assert(tl>=0);
2796 assert(th>=0);
2797 assert(sl>=0);
2798 emit_mov(sl,th);
2799 emit_zeroreg(tl);
2800 if(imm[i]>32)
2801 {
2802 emit_shlimm(th,imm[i]&31,th);
2803 }
2804 }
2805 }
2806 }
2807 if(opcode2[i]==0x3e) // DSRL32
2808 {
2809 if(rt1[i]) {
2810 signed char sh,tl,th;
2811 tl=get_reg(i_regs->regmap,rt1[i]);
2812 th=get_reg(i_regs->regmap,rt1[i]|64);
2813 sh=get_reg(i_regs->regmap,rs1[i]|64);
2814 if(tl>=0){
2815 assert(sh>=0);
2816 emit_mov(sh,tl);
2817 if(th>=0) emit_zeroreg(th);
2818 if(imm[i]>32)
2819 {
2820 emit_shrimm(tl,imm[i]&31,tl);
2821 }
2822 }
2823 }
2824 }
2825 if(opcode2[i]==0x3f) // DSRA32
2826 {
2827 if(rt1[i]) {
2828 signed char sh,tl;
2829 tl=get_reg(i_regs->regmap,rt1[i]);
2830 sh=get_reg(i_regs->regmap,rs1[i]|64);
2831 if(tl>=0){
2832 assert(sh>=0);
2833 emit_mov(sh,tl);
2834 if(imm[i]>32)
2835 {
2836 emit_sarimm(tl,imm[i]&31,tl);
2837 }
2838 }
2839 }
2840 }
2841}
2842
2843#ifndef shift_assemble
2844void shift_assemble(int i,struct regstat *i_regs)
2845{
2846 printf("Need shift_assemble for this architecture.\n");
2847 exit(1);
2848}
2849#endif
2850
2851void load_assemble(int i,struct regstat *i_regs)
2852{
2853 int s,th,tl,addr,map=-1;
2854 int offset;
2855 int jaddr=0;
5bf843dc 2856 int memtarget=0,c=0;
b1570849 2857 int fastload_reg_override=0;
57871462 2858 u_int hr,reglist=0;
2859 th=get_reg(i_regs->regmap,rt1[i]|64);
2860 tl=get_reg(i_regs->regmap,rt1[i]);
2861 s=get_reg(i_regs->regmap,rs1[i]);
2862 offset=imm[i];
2863 for(hr=0;hr<HOST_REGS;hr++) {
2864 if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
2865 }
2866 if(i_regs->regmap[HOST_CCREG]==CCREG) reglist&=~(1<<HOST_CCREG);
2867 if(s>=0) {
2868 c=(i_regs->wasconst>>s)&1;
af4ee1fe 2869 if (c) {
2870 memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
2871 if(using_tlb&&((signed int)(constmap[i][s]+offset))>=(signed int)0xC0000000) memtarget=1;
2872 }
57871462 2873 }
57871462 2874 //printf("load_assemble: c=%d\n",c);
2875 //if(c) printf("load_assemble: const=%x\n",(int)constmap[i][s]+offset);
2876 // FIXME: Even if the load is a NOP, we should check for pagefaults...
5bf843dc 2877#ifdef PCSX
f18c0f46 2878 if(tl<0&&(!c||(((u_int)constmap[i][s]+offset)>>16)==0x1f80)
2879 ||rt1[i]==0) {
5bf843dc 2880 // could be FIFO, must perform the read
f18c0f46 2881 // ||dummy read
5bf843dc 2882 assem_debug("(forced read)\n");
2883 tl=get_reg(i_regs->regmap,-1);
2884 assert(tl>=0);
5bf843dc 2885 }
f18c0f46 2886#endif
5bf843dc 2887 if(offset||s<0||c) addr=tl;
2888 else addr=s;
535d208a 2889 //if(tl<0) tl=get_reg(i_regs->regmap,-1);
2890 if(tl>=0) {
2891 //printf("load_assemble: c=%d\n",c);
2892 //if(c) printf("load_assemble: const=%x\n",(int)constmap[i][s]+offset);
2893 assert(tl>=0); // Even if the load is a NOP, we must check for pagefaults and I/O
2894 reglist&=~(1<<tl);
2895 if(th>=0) reglist&=~(1<<th);
2896 if(!using_tlb) {
2897 if(!c) {
2898 #ifdef RAM_OFFSET
2899 map=get_reg(i_regs->regmap,ROREG);
2900 if(map<0) emit_loadreg(ROREG,map=HOST_TEMPREG);
2901 #endif
57871462 2902//#define R29_HACK 1
535d208a 2903 #ifdef R29_HACK
2904 // Strmnnrmn's speed hack
2905 if(rs1[i]!=29||start<0x80001000||start>=0x80000000+RAM_SIZE)
2906 #endif
2907 {
ffb0b9e0 2908 jaddr=emit_fastpath_cmp_jump(i,addr,&fastload_reg_override);
57871462 2909 }
535d208a 2910 }
2911 }else{ // using tlb
2912 int x=0;
2913 if (opcode[i]==0x20||opcode[i]==0x24) x=3; // LB/LBU
2914 if (opcode[i]==0x21||opcode[i]==0x25) x=2; // LH/LHU
2915 map=get_reg(i_regs->regmap,TLREG);
2916 assert(map>=0);
ea3d2e6e 2917 reglist&=~(1<<map);
535d208a 2918 map=do_tlb_r(addr,tl,map,x,-1,-1,c,constmap[i][s]+offset);
2919 do_tlb_r_branch(map,c,constmap[i][s]+offset,&jaddr);
2920 }
2921 int dummy=(rt1[i]==0)||(tl!=get_reg(i_regs->regmap,rt1[i])); // ignore loads to r0 and unneeded reg
2922 if (opcode[i]==0x20) { // LB
2923 if(!c||memtarget) {
2924 if(!dummy) {
57871462 2925 #ifdef HOST_IMM_ADDR32
2926 if(c)
2927 emit_movsbl_tlb((constmap[i][s]+offset)^3,map,tl);
2928 else
2929 #endif
2930 {
2931 //emit_xorimm(addr,3,tl);
2932 //gen_tlb_addr_r(tl,map);
2933 //emit_movsbl_indexed((int)rdram-0x80000000,tl,tl);
535d208a 2934 int x=0,a=tl;
2002a1db 2935#ifdef BIG_ENDIAN_MIPS
57871462 2936 if(!c) emit_xorimm(addr,3,tl);
2937 else x=((constmap[i][s]+offset)^3)-(constmap[i][s]+offset);
2002a1db 2938#else
535d208a 2939 if(!c) a=addr;
dadf55f2 2940#endif
b1570849 2941 if(fastload_reg_override) a=fastload_reg_override;
2942
535d208a 2943 emit_movsbl_indexed_tlb(x,a,map,tl);
57871462 2944 }
57871462 2945 }
535d208a 2946 if(jaddr)
2947 add_stub(LOADB_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
57871462 2948 }
535d208a 2949 else
2950 inline_readstub(LOADB_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2951 }
2952 if (opcode[i]==0x21) { // LH
2953 if(!c||memtarget) {
2954 if(!dummy) {
57871462 2955 #ifdef HOST_IMM_ADDR32
2956 if(c)
2957 emit_movswl_tlb((constmap[i][s]+offset)^2,map,tl);
2958 else
2959 #endif
2960 {
535d208a 2961 int x=0,a=tl;
2002a1db 2962#ifdef BIG_ENDIAN_MIPS
57871462 2963 if(!c) emit_xorimm(addr,2,tl);
2964 else x=((constmap[i][s]+offset)^2)-(constmap[i][s]+offset);
2002a1db 2965#else
535d208a 2966 if(!c) a=addr;
dadf55f2 2967#endif
b1570849 2968 if(fastload_reg_override) a=fastload_reg_override;
57871462 2969 //#ifdef
2970 //emit_movswl_indexed_tlb(x,tl,map,tl);
2971 //else
2972 if(map>=0) {
535d208a 2973 gen_tlb_addr_r(a,map);
2974 emit_movswl_indexed(x,a,tl);
2975 }else{
2976 #ifdef RAM_OFFSET
2977 emit_movswl_indexed(x,a,tl);
2978 #else
2979 emit_movswl_indexed((int)rdram-0x80000000+x,a,tl);
2980 #endif
2981 }
57871462 2982 }
57871462 2983 }
535d208a 2984 if(jaddr)
2985 add_stub(LOADH_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
57871462 2986 }
535d208a 2987 else
2988 inline_readstub(LOADH_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2989 }
2990 if (opcode[i]==0x23) { // LW
2991 if(!c||memtarget) {
2992 if(!dummy) {
dadf55f2 2993 int a=addr;
b1570849 2994 if(fastload_reg_override) a=fastload_reg_override;
57871462 2995 //emit_readword_indexed((int)rdram-0x80000000,addr,tl);
2996 #ifdef HOST_IMM_ADDR32
2997 if(c)
2998 emit_readword_tlb(constmap[i][s]+offset,map,tl);
2999 else
3000 #endif
dadf55f2 3001 emit_readword_indexed_tlb(0,a,map,tl);
57871462 3002 }
535d208a 3003 if(jaddr)
3004 add_stub(LOADW_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
57871462 3005 }
535d208a 3006 else
3007 inline_readstub(LOADW_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
3008 }
3009 if (opcode[i]==0x24) { // LBU
3010 if(!c||memtarget) {
3011 if(!dummy) {
57871462 3012 #ifdef HOST_IMM_ADDR32
3013 if(c)
3014 emit_movzbl_tlb((constmap[i][s]+offset)^3,map,tl);
3015 else
3016 #endif
3017 {
3018 //emit_xorimm(addr,3,tl);
3019 //gen_tlb_addr_r(tl,map);
3020 //emit_movzbl_indexed((int)rdram-0x80000000,tl,tl);
535d208a 3021 int x=0,a=tl;
2002a1db 3022#ifdef BIG_ENDIAN_MIPS
57871462 3023 if(!c) emit_xorimm(addr,3,tl);
3024 else x=((constmap[i][s]+offset)^3)-(constmap[i][s]+offset);
2002a1db 3025#else
535d208a 3026 if(!c) a=addr;
dadf55f2 3027#endif
b1570849 3028 if(fastload_reg_override) a=fastload_reg_override;
3029
535d208a 3030 emit_movzbl_indexed_tlb(x,a,map,tl);
57871462 3031 }
57871462 3032 }
535d208a 3033 if(jaddr)
3034 add_stub(LOADBU_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
57871462 3035 }
535d208a 3036 else
3037 inline_readstub(LOADBU_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
3038 }
3039 if (opcode[i]==0x25) { // LHU
3040 if(!c||memtarget) {
3041 if(!dummy) {
57871462 3042 #ifdef HOST_IMM_ADDR32
3043 if(c)
3044 emit_movzwl_tlb((constmap[i][s]+offset)^2,map,tl);
3045 else
3046 #endif
3047 {
535d208a 3048 int x=0,a=tl;
2002a1db 3049#ifdef BIG_ENDIAN_MIPS
57871462 3050 if(!c) emit_xorimm(addr,2,tl);
3051 else x=((constmap[i][s]+offset)^2)-(constmap[i][s]+offset);
2002a1db 3052#else
535d208a 3053 if(!c) a=addr;
dadf55f2 3054#endif
b1570849 3055 if(fastload_reg_override) a=fastload_reg_override;
57871462 3056 //#ifdef
3057 //emit_movzwl_indexed_tlb(x,tl,map,tl);
3058 //#else
3059 if(map>=0) {
535d208a 3060 gen_tlb_addr_r(a,map);
3061 emit_movzwl_indexed(x,a,tl);
3062 }else{
3063 #ifdef RAM_OFFSET
3064 emit_movzwl_indexed(x,a,tl);
3065 #else
3066 emit_movzwl_indexed((int)rdram-0x80000000+x,a,tl);
3067 #endif
3068 }
57871462 3069 }
3070 }
535d208a 3071 if(jaddr)
3072 add_stub(LOADHU_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
57871462 3073 }
535d208a 3074 else
3075 inline_readstub(LOADHU_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
3076 }
3077 if (opcode[i]==0x27) { // LWU
3078 assert(th>=0);
3079 if(!c||memtarget) {
3080 if(!dummy) {
dadf55f2 3081 int a=addr;
b1570849 3082 if(fastload_reg_override) a=fastload_reg_override;
57871462 3083 //emit_readword_indexed((int)rdram-0x80000000,addr,tl);
3084 #ifdef HOST_IMM_ADDR32
3085 if(c)
3086 emit_readword_tlb(constmap[i][s]+offset,map,tl);
3087 else
3088 #endif
dadf55f2 3089 emit_readword_indexed_tlb(0,a,map,tl);
57871462 3090 }
535d208a 3091 if(jaddr)
3092 add_stub(LOADW_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
3093 }
3094 else {
3095 inline_readstub(LOADW_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
57871462 3096 }
535d208a 3097 emit_zeroreg(th);
3098 }
3099 if (opcode[i]==0x37) { // LD
3100 if(!c||memtarget) {
3101 if(!dummy) {
dadf55f2 3102 int a=addr;
b1570849 3103 if(fastload_reg_override) a=fastload_reg_override;
57871462 3104 //gen_tlb_addr_r(tl,map);
3105 //if(th>=0) emit_readword_indexed((int)rdram-0x80000000,addr,th);
3106 //emit_readword_indexed((int)rdram-0x7FFFFFFC,addr,tl);
3107 #ifdef HOST_IMM_ADDR32
3108 if(c)
3109 emit_readdword_tlb(constmap[i][s]+offset,map,th,tl);
3110 else
3111 #endif
dadf55f2 3112 emit_readdword_indexed_tlb(0,a,map,th,tl);
57871462 3113 }
535d208a 3114 if(jaddr)
3115 add_stub(LOADD_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
57871462 3116 }
535d208a 3117 else
3118 inline_readstub(LOADD_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
57871462 3119 }
535d208a 3120 }
3121 //emit_storereg(rt1[i],tl); // DEBUG
57871462 3122 //if(opcode[i]==0x23)
3123 //if(opcode[i]==0x24)
3124 //if(opcode[i]==0x23||opcode[i]==0x24)
3125 /*if(opcode[i]==0x21||opcode[i]==0x23||opcode[i]==0x24)
3126 {
3127 //emit_pusha();
3128 save_regs(0x100f);
3129 emit_readword((int)&last_count,ECX);
3130 #ifdef __i386__
3131 if(get_reg(i_regs->regmap,CCREG)<0)
3132 emit_loadreg(CCREG,HOST_CCREG);
3133 emit_add(HOST_CCREG,ECX,HOST_CCREG);
3134 emit_addimm(HOST_CCREG,2*ccadj[i],HOST_CCREG);
3135 emit_writeword(HOST_CCREG,(int)&Count);
3136 #endif
3137 #ifdef __arm__
3138 if(get_reg(i_regs->regmap,CCREG)<0)
3139 emit_loadreg(CCREG,0);
3140 else
3141 emit_mov(HOST_CCREG,0);
3142 emit_add(0,ECX,0);
3143 emit_addimm(0,2*ccadj[i],0);
3144 emit_writeword(0,(int)&Count);
3145 #endif
3146 emit_call((int)memdebug);
3147 //emit_popa();
3148 restore_regs(0x100f);
3149 }/**/
3150}
3151
3152#ifndef loadlr_assemble
3153void loadlr_assemble(int i,struct regstat *i_regs)
3154{
3155 printf("Need loadlr_assemble for this architecture.\n");
3156 exit(1);
3157}
3158#endif
3159
3160void store_assemble(int i,struct regstat *i_regs)
3161{
3162 int s,th,tl,map=-1;
3163 int addr,temp;
3164 int offset;
3165 int jaddr=0,jaddr2,type;
666a299d 3166 int memtarget=0,c=0;
57871462 3167 int agr=AGEN1+(i&1);
b1570849 3168 int faststore_reg_override=0;
57871462 3169 u_int hr,reglist=0;
3170 th=get_reg(i_regs->regmap,rs2[i]|64);
3171 tl=get_reg(i_regs->regmap,rs2[i]);
3172 s=get_reg(i_regs->regmap,rs1[i]);
3173 temp=get_reg(i_regs->regmap,agr);
3174 if(temp<0) temp=get_reg(i_regs->regmap,-1);
3175 offset=imm[i];
3176 if(s>=0) {
3177 c=(i_regs->wasconst>>s)&1;
af4ee1fe 3178 if(c) {
3179 memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
3180 if(using_tlb&&((signed int)(constmap[i][s]+offset))>=(signed int)0xC0000000) memtarget=1;
3181 }
57871462 3182 }
3183 assert(tl>=0);
3184 assert(temp>=0);
3185 for(hr=0;hr<HOST_REGS;hr++) {
3186 if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
3187 }
3188 if(i_regs->regmap[HOST_CCREG]==CCREG) reglist&=~(1<<HOST_CCREG);
3189 if(offset||s<0||c) addr=temp;
3190 else addr=s;
3191 if(!using_tlb) {
3192 if(!c) {
ffb0b9e0 3193 #ifndef PCSX
57871462 3194 #ifdef R29_HACK
3195 // Strmnnrmn's speed hack
4cb76aa4 3196 if(rs1[i]!=29||start<0x80001000||start>=0x80000000+RAM_SIZE)
57871462 3197 #endif
4cb76aa4 3198 emit_cmpimm(addr,RAM_SIZE);
57871462 3199 #ifdef DESTRUCTIVE_SHIFT
3200 if(s==addr) emit_mov(s,temp);
3201 #endif
3202 #ifdef R29_HACK
dadf55f2 3203 memtarget=1;
4cb76aa4 3204 if(rs1[i]!=29||start<0x80001000||start>=0x80000000+RAM_SIZE)
57871462 3205 #endif
3206 {
3207 jaddr=(int)out;
3208 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
3209 // Hint to branch predictor that the branch is unlikely to be taken
3210 if(rs1[i]>=28)
3211 emit_jno_unlikely(0);
3212 else
3213 #endif
3214 emit_jno(0);
3215 }
ffb0b9e0 3216 #else
3217 jaddr=emit_fastpath_cmp_jump(i,addr,&faststore_reg_override);
3218 #endif
57871462 3219 }
3220 }else{ // using tlb
3221 int x=0;
3222 if (opcode[i]==0x28) x=3; // SB
3223 if (opcode[i]==0x29) x=2; // SH
3224 map=get_reg(i_regs->regmap,TLREG);
3225 assert(map>=0);
ea3d2e6e 3226 reglist&=~(1<<map);
57871462 3227 map=do_tlb_w(addr,temp,map,x,c,constmap[i][s]+offset);
3228 do_tlb_w_branch(map,c,constmap[i][s]+offset,&jaddr);
3229 }
3230
3231 if (opcode[i]==0x28) { // SB
3232 if(!c||memtarget) {
97a238a6 3233 int x=0,a=temp;
2002a1db 3234#ifdef BIG_ENDIAN_MIPS
57871462 3235 if(!c) emit_xorimm(addr,3,temp);
3236 else x=((constmap[i][s]+offset)^3)-(constmap[i][s]+offset);
2002a1db 3237#else
97a238a6 3238 if(!c) a=addr;
dadf55f2 3239#endif
b1570849 3240 if(faststore_reg_override) a=faststore_reg_override;
57871462 3241 //gen_tlb_addr_w(temp,map);
3242 //emit_writebyte_indexed(tl,(int)rdram-0x80000000,temp);
97a238a6 3243 emit_writebyte_indexed_tlb(tl,x,a,map,a);
57871462 3244 }
3245 type=STOREB_STUB;
3246 }
3247 if (opcode[i]==0x29) { // SH
3248 if(!c||memtarget) {
97a238a6 3249 int x=0,a=temp;
2002a1db 3250#ifdef BIG_ENDIAN_MIPS
57871462 3251 if(!c) emit_xorimm(addr,2,temp);
3252 else x=((constmap[i][s]+offset)^2)-(constmap[i][s]+offset);
2002a1db 3253#else
97a238a6 3254 if(!c) a=addr;
dadf55f2 3255#endif
b1570849 3256 if(faststore_reg_override) a=faststore_reg_override;
57871462 3257 //#ifdef
3258 //emit_writehword_indexed_tlb(tl,x,temp,map,temp);
3259 //#else
3260 if(map>=0) {
97a238a6 3261 gen_tlb_addr_w(a,map);
3262 emit_writehword_indexed(tl,x,a);
57871462 3263 }else
97a238a6 3264 emit_writehword_indexed(tl,(int)rdram-0x80000000+x,a);
57871462 3265 }
3266 type=STOREH_STUB;
3267 }
3268 if (opcode[i]==0x2B) { // SW
dadf55f2 3269 if(!c||memtarget) {
3270 int a=addr;
b1570849 3271 if(faststore_reg_override) a=faststore_reg_override;
57871462 3272 //emit_writeword_indexed(tl,(int)rdram-0x80000000,addr);
dadf55f2 3273 emit_writeword_indexed_tlb(tl,0,a,map,temp);
3274 }
57871462 3275 type=STOREW_STUB;
3276 }
3277 if (opcode[i]==0x3F) { // SD
3278 if(!c||memtarget) {
dadf55f2 3279 int a=addr;
b1570849 3280 if(faststore_reg_override) a=faststore_reg_override;
57871462 3281 if(rs2[i]) {
3282 assert(th>=0);
3283 //emit_writeword_indexed(th,(int)rdram-0x80000000,addr);
3284 //emit_writeword_indexed(tl,(int)rdram-0x7FFFFFFC,addr);
dadf55f2 3285 emit_writedword_indexed_tlb(th,tl,0,a,map,temp);
57871462 3286 }else{
3287 // Store zero
3288 //emit_writeword_indexed(tl,(int)rdram-0x80000000,temp);
3289 //emit_writeword_indexed(tl,(int)rdram-0x7FFFFFFC,temp);
dadf55f2 3290 emit_writedword_indexed_tlb(tl,tl,0,a,map,temp);
57871462