bugfix

[picodrive.git] / pico / pico_int.h

// Pico Library - Internal Header File\r
\r
// (c) Copyright 2004 Dave, All rights reserved.\r
// (c) Copyright 2006-2009 Grazvydas "notaz" Ignotas, all rights reserved.\r
// Free for non-commercial use.\r
\r
// For commercial use, separate licencing terms must be obtained.\r
\r
#ifndef PICO_INTERNAL_INCLUDED\r
#define PICO_INTERNAL_INCLUDED\r
\r
#include <stdio.h>\r
#include <stdlib.h>\r
#include <string.h>\r
#include "pico.h"\r
#include "carthw/carthw.h"\r
\r
//\r
#define USE_POLL_DETECT\r
\r
#ifndef PICO_INTERNAL\r
#define PICO_INTERNAL\r
#endif\r
#ifndef PICO_INTERNAL_ASM\r
#define PICO_INTERNAL_ASM\r
#endif\r
\r
// to select core, define EMU_C68K, EMU_M68K or EMU_F68K in your makefile or project\r
\r
#ifdef __cplusplus\r
extern "C" {\r
#endif\r
\r
\r
// ----------------------- 68000 CPU -----------------------\r
#ifdef EMU_C68K\r
#include "../cpu/Cyclone/Cyclone.h"\r
extern struct Cyclone PicoCpuCM68k, PicoCpuCS68k;\r
#define SekCyclesLeftNoMCD PicoCpuCM68k.cycles // cycles left for this run\r
#define SekCyclesLeft \\r
	(((PicoAHW&1) && (PicoOpt & POPT_EN_MCD_PSYNC)) ? (SekCycleAim-SekCycleCnt) : SekCyclesLeftNoMCD)\r
#define SekCyclesLeftS68k \\r
	((PicoOpt & POPT_EN_MCD_PSYNC) ? (SekCycleAimS68k-SekCycleCntS68k) : PicoCpuCS68k.cycles)\r
#define SekEndTimeslice(after) PicoCpuCM68k.cycles=after\r
#define SekEndTimesliceS68k(after) PicoCpuCS68k.cycles=after\r
#define SekPc (PicoCpuCM68k.pc-PicoCpuCM68k.membase)\r
#define SekPcS68k (PicoCpuCS68k.pc-PicoCpuCS68k.membase)\r
#define SekDar(x) PicoCpuCM68k.d[x]\r
#define SekSr     CycloneGetSr(&PicoCpuCM68k)\r
#define SekSetStop(x) { PicoCpuCM68k.state_flags&=~1; if (x) { PicoCpuCM68k.state_flags|=1; PicoCpuCM68k.cycles=0; } }\r
#define SekSetStopS68k(x) { PicoCpuCS68k.state_flags&=~1; if (x) { PicoCpuCS68k.state_flags|=1; PicoCpuCS68k.cycles=0; } }\r
#define SekIsStoppedS68k() (PicoCpuCS68k.state_flags&1)\r
#define SekShouldInterrupt (PicoCpuCM68k.irq > (PicoCpuCM68k.srh&7))\r
\r
#define SekInterrupt(i) PicoCpuCM68k.irq=i\r
#define SekIrqLevel     PicoCpuCM68k.irq\r
\r
#ifdef EMU_M68K\r
#define EMU_CORE_DEBUG\r
#endif\r
#endif\r
\r
#ifdef EMU_F68K\r
#include "../cpu/fame/fame.h"\r
extern M68K_CONTEXT PicoCpuFM68k, PicoCpuFS68k;\r
#define SekCyclesLeftNoMCD PicoCpuFM68k.io_cycle_counter\r
#define SekCyclesLeft \\r
	(((PicoAHW&1) && (PicoOpt & POPT_EN_MCD_PSYNC)) ? (SekCycleAim-SekCycleCnt) : SekCyclesLeftNoMCD)\r
#define SekCyclesLeftS68k \\r
	((PicoOpt & POPT_EN_MCD_PSYNC) ? (SekCycleAimS68k-SekCycleCntS68k) : PicoCpuFS68k.io_cycle_counter)\r
#define SekEndTimeslice(after) PicoCpuFM68k.io_cycle_counter=after\r
#define SekEndTimesliceS68k(after) PicoCpuFS68k.io_cycle_counter=after\r
#define SekPc     fm68k_get_pc(&PicoCpuFM68k)\r
#define SekPcS68k fm68k_get_pc(&PicoCpuFS68k)\r
#define SekDar(x) PicoCpuFM68k.dreg[x].D\r
#define SekSr     PicoCpuFM68k.sr\r
#define SekSetStop(x) { \\r
	PicoCpuFM68k.execinfo &= ~FM68K_HALTED; \\r
	if (x) { PicoCpuFM68k.execinfo |= FM68K_HALTED; PicoCpuFM68k.io_cycle_counter = 0; } \\r
}\r
#define SekSetStopS68k(x) { \\r
	PicoCpuFS68k.execinfo &= ~FM68K_HALTED; \\r
	if (x) { PicoCpuFS68k.execinfo |= FM68K_HALTED; PicoCpuFS68k.io_cycle_counter = 0; } \\r
}\r
#define SekIsStoppedS68k() (PicoCpuFS68k.execinfo&FM68K_HALTED)\r
#define SekShouldInterrupt fm68k_would_interrupt()\r
\r
#define SekInterrupt(irq) PicoCpuFM68k.interrupts[0]=irq\r
#define SekIrqLevel       PicoCpuFM68k.interrupts[0]\r
\r
#ifdef EMU_M68K\r
#define EMU_CORE_DEBUG\r
#endif\r
#endif\r
\r
#ifdef EMU_M68K\r
#include "../cpu/musashi/m68kcpu.h"\r
extern m68ki_cpu_core PicoCpuMM68k, PicoCpuMS68k;\r
#ifndef SekCyclesLeft\r
#define SekCyclesLeftNoMCD PicoCpuMM68k.cyc_remaining_cycles\r
#define SekCyclesLeft \\r
	(((PicoAHW&1) && (PicoOpt & POPT_EN_MCD_PSYNC)) ? (SekCycleAim-SekCycleCnt) : SekCyclesLeftNoMCD)\r
#define SekCyclesLeftS68k \\r
	((PicoOpt & POPT_EN_MCD_PSYNC) ? (SekCycleAimS68k-SekCycleCntS68k) : PicoCpuMS68k.cyc_remaining_cycles)\r
#define SekEndTimeslice(after) SET_CYCLES(after)\r
#define SekEndTimesliceS68k(after) PicoCpuMS68k.cyc_remaining_cycles=after\r
#define SekPc m68k_get_reg(&PicoCpuMM68k, M68K_REG_PC)\r
#define SekPcS68k m68k_get_reg(&PicoCpuMS68k, M68K_REG_PC)\r
#define SekDar(x) PicoCpuMM68k.dar[x]\r
#define SekSr m68k_get_reg(&PicoCpuMM68k, M68K_REG_SR)\r
#define SekSetStop(x) { \\r
	if(x) { SET_CYCLES(0); PicoCpuMM68k.stopped=STOP_LEVEL_STOP; } \\r
	else PicoCpuMM68k.stopped=0; \\r
}\r
#define SekSetStopS68k(x) { \\r
	if(x) { SET_CYCLES(0); PicoCpuMS68k.stopped=STOP_LEVEL_STOP; } \\r
	else PicoCpuMS68k.stopped=0; \\r
}\r
#define SekIsStoppedS68k() (PicoCpuMS68k.stopped==STOP_LEVEL_STOP)\r
#define SekShouldInterrupt (CPU_INT_LEVEL > FLAG_INT_MASK)\r
\r
#define SekInterrupt(irq) { \\r
	void *oldcontext = m68ki_cpu_p; \\r
	m68k_set_context(&PicoCpuMM68k); \\r
	m68k_set_irq(irq); \\r
	m68k_set_context(oldcontext); \\r
}\r
#define SekIrqLevel (PicoCpuMM68k.int_level >> 8)\r
\r
#endif\r
#endif // EMU_M68K\r
\r
extern int SekCycleCnt; // cycles done in this frame\r
extern int SekCycleAim; // cycle aim\r
extern unsigned int SekCycleCntT; // total cycle counter, updated once per frame\r
\r
#define SekCyclesReset() { \\r
	SekCycleCntT+=SekCycleAim; \\r
	SekCycleCnt-=SekCycleAim; \\r
	SekCycleAim=0; \\r
}\r
#define SekCyclesBurn(c)  SekCycleCnt+=c\r
#define SekCyclesDone()  (SekCycleAim-SekCyclesLeft)    // number of cycles done in this frame (can be checked anywhere)\r
#define SekCyclesDoneT() (SekCycleCntT+SekCyclesDone()) // total nuber of cycles done for this rom\r
\r
#define SekEndRun(after) { \\r
	SekCycleCnt -= SekCyclesLeft - (after); \\r
	if (SekCycleCnt < 0) SekCycleCnt = 0; \\r
	SekEndTimeslice(after); \\r
}\r
\r
#define SekEndRunS68k(after) { \\r
	SekCycleCntS68k -= SekCyclesLeftS68k - (after); \\r
	if (SekCycleCntS68k < 0) SekCycleCntS68k = 0; \\r
	SekEndTimesliceS68k(after); \\r
}\r
\r
extern int SekCycleCntS68k;\r
extern int SekCycleAimS68k;\r
\r
#define SekCyclesResetS68k() { \\r
	SekCycleCntS68k-=SekCycleAimS68k; \\r
	SekCycleAimS68k=0; \\r
}\r
#define SekCyclesDoneS68k()  (SekCycleAimS68k-SekCyclesLeftS68k)\r
\r
#ifdef EMU_CORE_DEBUG\r
extern int dbg_irq_level;\r
#undef SekEndTimeslice\r
#undef SekCyclesBurn\r
#undef SekEndRun\r
#undef SekInterrupt\r
#define SekEndTimeslice(c)\r
#define SekCyclesBurn(c) c\r
#define SekEndRun(c)\r
#define SekInterrupt(irq) dbg_irq_level=irq\r
#endif\r
\r
// ----------------------- Z80 CPU -----------------------\r
\r
#if defined(_USE_MZ80)\r
#include "../cpu/mz80/mz80.h"\r
\r
#define z80_run(cycles)    { mz80GetElapsedTicks(1); mz80_run(cycles) }\r
#define z80_run_nr(cycles) mz80_run(cycles)\r
#define z80_int()          mz80int(0)\r
\r
#elif defined(_USE_DRZ80)\r
#include "../cpu/DrZ80/drz80.h"\r
\r
extern struct DrZ80 drZ80;\r
\r
#define z80_run(cycles)    ((cycles) - DrZ80Run(&drZ80, cycles))\r
#define z80_run_nr(cycles) DrZ80Run(&drZ80, cycles)\r
#define z80_int()          drZ80.Z80_IRQ = 1\r
\r
#define z80_cyclesLeft     drZ80.cycles\r
#define z80_pc()           (drZ80.Z80PC - drZ80.Z80PC_BASE)\r
\r
#elif defined(_USE_CZ80)\r
#include "../cpu/cz80/cz80.h"\r
\r
#define z80_run(cycles)    Cz80_Exec(&CZ80, cycles)\r
#define z80_run_nr(cycles) Cz80_Exec(&CZ80, cycles)\r
#define z80_int()          Cz80_Set_IRQ(&CZ80, 0, HOLD_LINE)\r
\r
#define z80_cyclesLeft     (CZ80.ICount - CZ80.ExtraCycles)\r
#define z80_pc()           Cz80_Get_Reg(&CZ80, CZ80_PC)\r
\r
#else\r
\r
#define z80_run(cycles)    (cycles)\r
#define z80_run_nr(cycles)\r
#define z80_int()\r
\r
#endif\r
\r
extern int z80stopCycle;         /* in 68k cycles */\r
extern int z80_cycle_cnt;        /* 'done' z80 cycles before z80_run() */\r
extern int z80_cycle_aim;\r
extern int z80_scanline;\r
extern int z80_scanline_cycles;  /* cycles done until z80_scanline */\r
\r
#define z80_resetCycles() \\r
  z80_cycle_cnt = z80_cycle_aim = z80_scanline = z80_scanline_cycles = 0;\r
\r
#define z80_cyclesDone() \\r
  (z80_cycle_aim - z80_cyclesLeft)\r
\r
#define cycles_68k_to_z80(x) ((x)*957 >> 11)\r
\r
#define Z80_MEM_SHIFT 13\r
extern unsigned long z80_read_map [0x10000 >> Z80_MEM_SHIFT];\r
extern unsigned long z80_write_map[0x10000 >> Z80_MEM_SHIFT];\r
typedef unsigned char (z80_read_f)(unsigned short a);\r
typedef void (z80_write_f)(unsigned int a, unsigned char data);\r
\r
// ----------------------- SH2 CPU -----------------------\r
\r
#include "cpu/sh2/sh2.h"\r
\r
extern SH2 sh2s[2];\r
#define msh2 sh2s[0]\r
#define ssh2 sh2s[1]\r
\r
#define ash2_end_run(after) if (sh2->icount > (after)) sh2->icount = after\r
#define ash2_cycles_done() (sh2->cycles_aim - sh2->icount)\r
\r
#define sh2_pc(c)     (c) ? ssh2.ppc : msh2.ppc\r
#define sh2_reg(c, x) (c) ? ssh2.r[x] : msh2.r[x]\r
#define sh2_gbr(c)    (c) ? ssh2.gbr : msh2.gbr\r
#define sh2_vbr(c)    (c) ? ssh2.vbr : msh2.vbr\r
#define sh2_sr(c)     (c) ? ssh2.sr : msh2.sr\r
\r
#define sh2_set_gbr(c, v) \\r
  { if (c) ssh2.gbr = v; else msh2.gbr = v; }\r
#define sh2_set_vbr(c, v) \\r
  { if (c) ssh2.vbr = v; else msh2.vbr = v; }\r
\r
// ---------------------------------------------------------\r
\r
// main oscillator clock which controls timing\r
#define OSC_NTSC 53693100\r
#define OSC_PAL  53203424\r
\r
struct PicoVideo\r
{\r
  unsigned char reg[0x20];\r
  unsigned int command;       // 32-bit Command\r
  unsigned char pending;      // 1 if waiting for second half of 32-bit command\r
  unsigned char type;         // Command type (v/c/vsram read/write)\r
  unsigned short addr;        // Read/Write address\r
  int status;                 // Status bits\r
  unsigned char pending_ints; // pending interrupts: ??VH????\r
  signed char lwrite_cnt;     // VDP write count during active display line\r
  unsigned short v_counter;   // V-counter\r
  unsigned char pad[0x10];\r
};\r
\r
struct PicoMisc\r
{\r
  unsigned char rotate;\r
  unsigned char z80Run;\r
  unsigned char padTHPhase[2]; // 02 phase of gamepad TH switches\r
  unsigned short scanline;     // 04 0 to 261||311\r
  char dirtyPal;               // 06 Is the palette dirty (1 - change @ this frame, 2 - some time before)\r
  unsigned char hardware;      // 07 Hardware value for country\r
  unsigned char pal;           // 08 1=PAL 0=NTSC\r
  unsigned char sram_reg;      // 09 SRAM reg. See SRR_* below\r
  unsigned short z80_bank68k;  // 0a\r
  unsigned short pad0;\r
  unsigned char  pad1;\r
  unsigned char  z80_reset;    // 0f z80 reset held\r
  unsigned char  padDelay[2];  // 10 gamepad phase time outs, so we count a delay\r
  unsigned short eeprom_addr;  // EEPROM address register\r
  unsigned char  eeprom_cycle; // EEPROM cycle number\r
  unsigned char  eeprom_slave; // EEPROM slave word for X24C02 and better SRAMs\r
  unsigned char  eeprom_status;\r
  unsigned char  pad2;\r
  unsigned short dma_xfers;    // 18\r
  unsigned char  eeprom_wb[2]; // EEPROM latch/write buffer\r
  unsigned int  frame_count;   // 1c for movies and idle det\r
};\r
\r
// some assembly stuff depend on these, do not touch!\r
struct Pico\r
{\r
  unsigned char ram[0x10000];  // 0x00000 scratch ram\r
  union {                      // vram is byteswapped for easier reads when drawing\r
    unsigned short vram[0x8000];  // 0x10000\r
    unsigned char  vramb[0x4000]; // VRAM in SMS mode\r
  };\r
  unsigned char zram[0x2000];  // 0x20000 Z80 ram\r
  unsigned char ioports[0x10];\r
  unsigned char sms_io_ctl;\r
  unsigned char pad[0xef];     // unused\r
  unsigned short cram[0x40];   // 0x22100\r
  unsigned short vsram[0x40];  // 0x22180\r
\r
  unsigned char *rom;          // 0x22200\r
  unsigned int romsize;        // 0x22204\r
\r
  struct PicoMisc m;\r
  struct PicoVideo video;\r
};\r
\r
// sram\r
#define SRR_MAPPED   (1 << 0)\r
#define SRR_READONLY (1 << 1)\r
\r
#define SRF_ENABLED  (1 << 0)\r
#define SRF_EEPROM   (1 << 1)\r
\r
struct PicoSRAM\r
{\r
  unsigned char *data;		// actual data\r
  unsigned int start;		// start address in 68k address space\r
  unsigned int end;\r
  unsigned char flags;		// 0c: SRF_*\r
  unsigned char unused2;\r
  unsigned char changed;\r
  unsigned char eeprom_type;    // eeprom type: 0: 7bit (24C01), 2: 2 addr words (X24C02+), 3: 3 addr words\r
  unsigned char unused3;\r
  unsigned char eeprom_bit_cl;	// bit number for cl\r
  unsigned char eeprom_bit_in;  // bit number for in\r
  unsigned char eeprom_bit_out; // bit number for out\r
  unsigned int size;\r
};\r
\r
// MCD\r
#include "cd/cd_sys.h"\r
#include "cd/LC89510.h"\r
#include "cd/gfx_cd.h"\r
\r
struct mcd_pcm\r
{\r
	unsigned char control; // reg7\r
	unsigned char enabled; // reg8\r
	unsigned char cur_ch;\r
	unsigned char bank;\r
	int pad1;\r
\r
	struct pcm_chan			// 08, size 0x10\r
	{\r
		unsigned char regs[8];\r
		unsigned int  addr;	// .08: played sample address\r
		int pad;\r
	} ch[8];\r
};\r
\r
struct mcd_misc\r
{\r
	unsigned short hint_vector;\r
	unsigned char  busreq;\r
	unsigned char  s68k_pend_ints;\r
	unsigned int   state_flags;	// 04: emu state: reset_pending\r
	unsigned int   counter75hz;\r
	unsigned int   pad0;\r
	int            timer_int3;	// 10\r
	unsigned int   timer_stopwatch;\r
	unsigned char  bcram_reg;	// 18: battery-backed RAM cart register\r
	unsigned char  pad2;\r
	unsigned short pad3;\r
	int pad[9];\r
};\r
\r
typedef struct\r
{\r
	unsigned char bios[0x20000];			// 000000: 128K\r
	union {						// 020000: 512K\r
		unsigned char prg_ram[0x80000];\r
		unsigned char prg_ram_b[4][0x20000];\r
	};\r
	union {						// 0a0000: 256K\r
		struct {\r
			unsigned char word_ram2M[0x40000];\r
			unsigned char unused0[0x20000];\r
		};\r
		struct {\r
			unsigned char unused1[0x20000];\r
			unsigned char word_ram1M[2][0x20000];\r
		};\r
	};\r
	union {						// 100000: 64K\r
		unsigned char pcm_ram[0x10000];\r
		unsigned char pcm_ram_b[0x10][0x1000];\r
	};\r
	unsigned char s68k_regs[0x200];			// 110000: GA, not CPU regs\r
	unsigned char bram[0x2000];			// 110200: 8K\r
	struct mcd_misc m;				// 112200: misc\r
	struct mcd_pcm pcm;				// 112240:\r
	_scd_toc TOC;					// not to be saved\r
	CDD  cdd;\r
	CDC  cdc;\r
	_scd scd;\r
	Rot_Comp rot_comp;\r
} mcd_state;\r
\r
// XXX: this will need to be reworked for cart+cd support.\r
#define Pico_mcd ((mcd_state *)Pico.rom)\r
\r
// 32X\r
#define P32XS_FM    (1<<15)\r
#define P32XS_REN   (1<< 7)\r
#define P32XS_nRES  (1<< 1)\r
#define P32XS_ADEN  (1<< 0)\r
#define P32XS2_ADEN (1<< 9)\r
#define P32XS_FULL  (1<< 7) // DREQ FIFO full\r
#define P32XS_68S   (1<< 2)\r
#define P32XS_DMA   (1<< 1)\r
#define P32XS_RV    (1<< 0)\r
\r
#define P32XV_nPAL  (1<<15) // VDP\r
#define P32XV_PRI   (1<< 7)\r
#define P32XV_Mx    (3<< 0) // display mode mask\r
\r
#define P32XV_VBLK  (1<<15)\r
#define P32XV_HBLK  (1<<14)\r
#define P32XV_PEN   (1<<13)\r
#define P32XV_nFEN  (1<< 1)\r
#define P32XV_FS    (1<< 0)\r
\r
#define P32XP_FULL  (1<<15) // PWM\r
#define P32XP_EMPTY (1<<14)\r
\r
#define P32XF_68KPOLL   (1 << 0)\r
#define P32XF_MSH2POLL  (1 << 1)\r
#define P32XF_SSH2POLL  (1 << 2)\r
#define P32XF_68KVPOLL  (1 << 3)\r
#define P32XF_MSH2VPOLL (1 << 4)\r
#define P32XF_SSH2VPOLL (1 << 5)\r
\r
#define P32XI_VRES (1 << 14/2) // IRL/2\r
#define P32XI_VINT (1 << 12/2)\r
#define P32XI_HINT (1 << 10/2)\r
#define P32XI_CMD  (1 <<  8/2)\r
#define P32XI_PWM  (1 <<  6/2)\r
\r
// peripheral reg access\r
#define PREG8(regs,offs) ((unsigned char *)regs)[offs ^ 3]\r
\r
// real one is 4*2, but we use more because we don't lockstep\r
#define DMAC_FIFO_LEN (4*4)\r
#define PWM_BUFF_LEN 1024 // in one channel samples\r
\r
struct Pico32x\r
{\r
  unsigned short regs[0x20];\r
  unsigned short vdp_regs[0x10];\r
  unsigned short sh2_regs[3];\r
  unsigned char pending_fb;\r
  unsigned char dirty_pal;\r
  unsigned int emu_flags;\r
  unsigned char sh2irq_mask[2];\r
  unsigned char sh2irqi[2];      // individual\r
  unsigned int sh2irqs;          // common irqs\r
  unsigned short dmac_fifo[DMAC_FIFO_LEN];\r
  unsigned int dmac_ptr;\r
  unsigned int pwm_irq_sample_cnt;\r
};\r
\r
struct Pico32xMem\r
{\r
  unsigned char  sdram[0x40000];\r
  unsigned short dram[2][0x20000/2];    // AKA fb\r
  unsigned char  m68k_rom[0x10000];     // 0x100; using M68K_BANK_SIZE\r
  unsigned char  data_array[2][0x1000]; // cache in SH2s (can be used as RAM)\r
  unsigned char  sh2_rom_m[0x800];\r
  unsigned char  sh2_rom_s[0x400];\r
  unsigned short pal[0x100];\r
  unsigned short pal_native[0x100];     // converted to native (for renderer)\r
  unsigned int   sh2_peri_regs[2][0x200/4]; // periphereal regs of SH2s\r
  signed short   pwm[2*PWM_BUFF_LEN];   // PWM buffer for current frame\r
};\r
\r
// area.c\r
PICO_INTERNAL void PicoAreaPackCpu(unsigned char *cpu, int is_sub);\r
PICO_INTERNAL void PicoAreaUnpackCpu(unsigned char *cpu, int is_sub);\r
extern void (*PicoLoadStateHook)(void);\r
\r
// cd/area.c\r
PICO_INTERNAL int PicoCdSaveState(void *file);\r
PICO_INTERNAL int PicoCdLoadState(void *file);\r
\r
typedef struct {\r
	int chunk;\r
	int size;\r
	void *ptr;\r
} carthw_state_chunk;\r
extern carthw_state_chunk *carthw_chunks;\r
#define CHUNK_CARTHW 64\r
\r
// area.c\r
typedef size_t (arearw)(void *p, size_t _size, size_t _n, void *file);\r
typedef size_t (areaeof)(void *file);\r
typedef int    (areaseek)(void *file, long offset, int whence);\r
typedef int    (areaclose)(void *file);\r
extern arearw  *areaRead;  // external read and write function pointers for\r
extern arearw  *areaWrite; // gzip save state ability\r
extern areaeof *areaEof;\r
extern areaseek *areaSeek;\r
extern areaclose *areaClose;\r
\r
// cart.c\r
void Byteswap(void *dst, const void *src, int len);\r
extern void (*PicoCartMemSetup)(void);\r
extern void (*PicoCartUnloadHook)(void);\r
\r
// debug.c\r
int CM_compareRun(int cyc, int is_sub);\r
\r
// draw.c\r
PICO_INTERNAL void PicoFrameStart(void);\r
void PicoDrawSync(int to, int blank_last_line);\r
void BackFill(int reg7, int sh);\r
void FinalizeLineRGB555(int sh, int line);\r
extern int DrawScanline;\r
#define MAX_LINE_SPRITES 29\r
extern unsigned char HighLnSpr[240][3 + MAX_LINE_SPRITES];\r
\r
// draw2.c\r
PICO_INTERNAL void PicoFrameFull();\r
\r
// mode4.c\r
void PicoFrameStartMode4(void);\r
void PicoLineMode4(int line);\r
void PicoDoHighPal555M4(void);\r
void PicoDrawSetColorFormatMode4(int which);\r
\r
// memory.c\r
PICO_INTERNAL void PicoMemSetup(void);\r
unsigned int PicoRead8_io(unsigned int a);\r
unsigned int PicoRead16_io(unsigned int a);\r
void PicoWrite8_io(unsigned int a, unsigned int d);\r
void PicoWrite16_io(unsigned int a, unsigned int d);\r
\r
// pico/memory.c\r
PICO_INTERNAL void PicoMemSetupPico(void);\r
\r
// cd/memory.c\r
PICO_INTERNAL void PicoMemSetupCD(void);\r
void PicoMemStateLoaded(void);\r
\r
// pico.c\r
extern struct Pico Pico;\r
extern struct PicoSRAM SRam;\r
extern int PicoPadInt[2];\r
extern int emustatus;\r
extern int scanlines_total;\r
extern void (*PicoResetHook)(void);\r
extern void (*PicoLineHook)(void);\r
PICO_INTERNAL int  CheckDMA(void);\r
PICO_INTERNAL void PicoDetectRegion(void);\r
PICO_INTERNAL void PicoSyncZ80(int m68k_cycles_done);\r
\r
// cd/pico.c\r
PICO_INTERNAL void PicoInitMCD(void);\r
PICO_INTERNAL void PicoExitMCD(void);\r
PICO_INTERNAL void PicoPowerMCD(void);\r
PICO_INTERNAL int  PicoResetMCD(void);\r
PICO_INTERNAL void PicoFrameMCD(void);\r
\r
// pico/pico.c\r
PICO_INTERNAL void PicoInitPico(void);\r
PICO_INTERNAL void PicoReratePico(void);\r
\r
// pico/xpcm.c\r
PICO_INTERNAL void PicoPicoPCMUpdate(short *buffer, int length, int stereo);\r
PICO_INTERNAL void PicoPicoPCMReset(void);\r
PICO_INTERNAL void PicoPicoPCMRerate(int xpcm_rate);\r
\r
// sek.c\r
PICO_INTERNAL void SekInit(void);\r
PICO_INTERNAL int  SekReset(void);\r
PICO_INTERNAL void SekState(int *data);\r
PICO_INTERNAL void SekSetRealTAS(int use_real);\r
void SekStepM68k(void);\r
void SekInitIdleDet(void);\r
void SekFinishIdleDet(void);\r
\r
// cd/sek.c\r
PICO_INTERNAL void SekInitS68k(void);\r
PICO_INTERNAL int  SekResetS68k(void);\r
PICO_INTERNAL int  SekInterruptS68k(int irq);\r
\r
// sound/sound.c\r
PICO_INTERNAL void cdda_start_play();\r
extern short cdda_out_buffer[2*1152];\r
extern int PsndLen_exc_cnt;\r
extern int PsndLen_exc_add;\r
extern int timer_a_next_oflow, timer_a_step; // in z80 cycles\r
extern int timer_b_next_oflow, timer_b_step;\r
\r
void ym2612_sync_timers(int z80_cycles, int mode_old, int mode_new);\r
void ym2612_pack_state(void);\r
void ym2612_unpack_state(void);\r
\r
#define TIMER_NO_OFLOW 0x70000000\r
// tA =   72 * (1024 - NA) / M\r
#define TIMER_A_TICK_ZCYCLES  17203\r
// tB = 1152 * (256 - NA) / M\r
#define TIMER_B_TICK_ZCYCLES 262800 // 275251 broken, see Dai Makaimura\r
\r
#define timers_cycle() \\r
  if (timer_a_next_oflow > 0 && timer_a_next_oflow < TIMER_NO_OFLOW) \\r
    timer_a_next_oflow -= Pico.m.pal ? 70938*256 : 59659*256; \\r
  if (timer_b_next_oflow > 0 && timer_b_next_oflow < TIMER_NO_OFLOW) \\r
    timer_b_next_oflow -= Pico.m.pal ? 70938*256 : 59659*256; \\r
  ym2612_sync_timers(0, ym2612.OPN.ST.mode, ym2612.OPN.ST.mode);\r
\r
#define timers_reset() \\r
  timer_a_next_oflow = timer_b_next_oflow = TIMER_NO_OFLOW; \\r
  timer_a_step = TIMER_A_TICK_ZCYCLES * 1024; \\r
  timer_b_step = TIMER_B_TICK_ZCYCLES * 256;\r
\r
\r
// videoport.c\r
PICO_INTERNAL_ASM void PicoVideoWrite(unsigned int a,unsigned short d);\r
PICO_INTERNAL_ASM unsigned int PicoVideoRead(unsigned int a);\r
PICO_INTERNAL_ASM unsigned int PicoVideoRead8(unsigned int a);\r
extern int (*PicoDmaHook)(unsigned int source, int len, unsigned short **srcp, unsigned short **limitp);\r
\r
// misc.c\r
PICO_INTERNAL_ASM void memcpy16(unsigned short *dest, unsigned short *src, int count);\r
PICO_INTERNAL_ASM void memcpy16bswap(unsigned short *dest, void *src, int count);\r
PICO_INTERNAL_ASM void memcpy32(int *dest, int *src, int count); // 32bit word count\r
PICO_INTERNAL_ASM void memset32(int *dest, int c, int count);\r
\r
// eeprom.c\r
void EEPROM_write8(unsigned int a, unsigned int d);\r
void EEPROM_write16(unsigned int d);\r
unsigned int EEPROM_read(void);\r
\r
// z80 functionality wrappers\r
PICO_INTERNAL void z80_init(void);\r
PICO_INTERNAL void z80_pack(unsigned char *data);\r
PICO_INTERNAL void z80_unpack(unsigned char *data);\r
PICO_INTERNAL void z80_reset(void);\r
PICO_INTERNAL void z80_exit(void);\r
\r
// cd/misc.c\r
PICO_INTERNAL_ASM void wram_2M_to_1M(unsigned char *m);\r
PICO_INTERNAL_ASM void wram_1M_to_2M(unsigned char *m);\r
\r
// cd/buffering.c\r
PICO_INTERNAL void PicoCDBufferRead(void *dest, int lba);\r
\r
// sound/sound.c\r
PICO_INTERNAL void PsndReset(void);\r
PICO_INTERNAL void PsndDoDAC(int line_to);\r
PICO_INTERNAL void PsndClear(void);\r
PICO_INTERNAL void PsndGetSamples(int y);\r
PICO_INTERNAL void PsndGetSamplesMS(void);\r
extern int PsndDacLine;\r
\r
// sms.c\r
void PicoPowerMS(void);\r
void PicoResetMS(void);\r
void PicoMemSetupMS(void);\r
void PicoFrameMS(void);\r
void PicoFrameDrawOnlyMS(void);\r
\r
// 32x/32x.c\r
extern struct Pico32x Pico32x;\r
void Pico32xInit(void);\r
void PicoPower32x(void);\r
void PicoReset32x(void);\r
void Pico32xStartup(void);\r
void PicoUnload32x(void);\r
void PicoFrame32x(void);\r
void p32x_update_irls(void);\r
void p32x_reset_sh2s(void);\r
\r
// 32x/memory.c\r
struct Pico32xMem *Pico32xMem;\r
unsigned int PicoRead8_32x(unsigned int a);\r
unsigned int PicoRead16_32x(unsigned int a);\r
void PicoWrite8_32x(unsigned int a, unsigned int d);\r
void PicoWrite16_32x(unsigned int a, unsigned int d);\r
void PicoMemSetup32x(void);\r
void Pico32xSwapDRAM(int b);\r
void p32x_poll_event(int cpu_mask, int is_vdp);\r
\r
// 32x/draw.c\r
void FinalizeLine32xRGB555(int sh, int line);\r
\r
// 32x/pwm.c\r
unsigned int p32x_pwm_read16(unsigned int a);\r
void p32x_pwm_write16(unsigned int a, unsigned int d);\r
void p32x_pwm_update(int *buf32, int length, int stereo);\r
void p32x_timers_do(int new_line);\r
void p32x_timers_recalc(void);\r
extern int pwm_frame_smp_cnt;\r
\r
/* avoid dependency on newer glibc */\r
static __inline int isspace_(int c)\r
{\r
	return (0x09 <= c && c <= 0x0d) || c == ' ';\r
}\r
\r
// emulation event logging\r
#ifndef EL_LOGMASK\r
#define EL_LOGMASK 0\r
#endif\r
\r
#define EL_HVCNT   0x00000001 /* hv counter reads */\r
#define EL_SR      0x00000002 /* SR reads */\r
#define EL_INTS    0x00000004 /* ints and acks */\r
#define EL_YMTIMER 0x00000008 /* ym2612 timer stuff */\r
#define EL_INTSW   0x00000010 /* log irq switching on/off */\r
#define EL_ASVDP   0x00000020 /* VDP accesses during active scan */\r
#define EL_VDPDMA  0x00000040 /* VDP DMA transfers and their timing */\r
#define EL_BUSREQ  0x00000080 /* z80 busreq r/w or reset w */\r
#define EL_Z80BNK  0x00000100 /* z80 i/o through bank area */\r
#define EL_SRAMIO  0x00000200 /* sram i/o */\r
#define EL_EEPROM  0x00000400 /* eeprom debug */\r
#define EL_UIO     0x00000800 /* unmapped i/o */\r
#define EL_IO      0x00001000 /* all i/o */\r
#define EL_CDPOLL  0x00002000 /* MCD: log poll detection */\r
#define EL_SVP     0x00004000 /* SVP stuff */\r
#define EL_PICOHW  0x00008000 /* Pico stuff */\r
#define EL_IDLE    0x00010000 /* idle loop det. */\r
#define EL_CDREGS  0x00020000 /* MCD: register access */\r
#define EL_CDREG3  0x00040000 /* MCD: register 3 only */\r
#define EL_32X     0x00080000\r
#define EL_PWM     0x00100000 /* 32X PWM stuff (LOTS of output) */\r
\r
#define EL_STATUS  0x40000000 /* status messages */\r
#define EL_ANOMALY 0x80000000 /* some unexpected conditions (during emulation) */\r
\r
#if EL_LOGMASK\r
extern void lprintf(const char *fmt, ...);\r
#define elprintf(w,f,...) \\r
{ \\r
	if ((w) & EL_LOGMASK) \\r
		lprintf("%05i:%03i: " f "\n",Pico.m.frame_count,Pico.m.scanline,##__VA_ARGS__); \\r
}\r
#elif defined(_MSC_VER)\r
#define elprintf\r
#else\r
#define elprintf(w,f,...)\r
#endif\r
\r
#ifdef _MSC_VER\r
#define cdprintf\r
#else\r
#define cdprintf(x...)\r
#endif\r
\r
#if defined(__GNUC__) && __GNUC__ >= 4 && __GNUC_MINOR__ >= 3\r
#define MEMH_FUNC __attribute__((aligned(4)))\r
#else\r
#define MEMH_FUNC\r
#endif\r
\r
#ifdef __GNUC__\r
#define NOINLINE __attribute__((noinline))\r
#else\r
#define NOINLINE\r
#endif\r
\r
#ifdef __cplusplus\r
} // End of extern "C"\r
#endif\r
\r
#endif // PICO_INTERNAL_INCLUDED\r
\r