| eff55556 |
1 | // Pico Library - Internal Header File\r |
| cc68a136 |
2 | \r |
| 3 | // (c) Copyright 2004 Dave, All rights reserved.\r |
| db1d3564 |
4 | // (c) Copyright 2006-2009 Grazvydas "notaz" Ignotas, all rights reserved.\r |
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5 | // Free for non-commercial use.\r |
| 6 | \r |
| 7 | // For commercial use, separate licencing terms must be obtained.\r |
| 8 | \r |
| eff55556 |
9 | #ifndef PICO_INTERNAL_INCLUDED\r |
| 10 | #define PICO_INTERNAL_INCLUDED\r |
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11 | \r |
| 12 | #include <stdio.h>\r |
| 13 | #include <stdlib.h>\r |
| 14 | #include <string.h>\r |
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15 | #include "pico.h"\r |
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16 | #include "carthw/carthw.h"\r |
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17 | \r |
| 89fa852d |
18 | //\r |
| 19 | #define USE_POLL_DETECT\r |
| 20 | \r |
| eff55556 |
21 | #ifndef PICO_INTERNAL\r |
| 22 | #define PICO_INTERNAL\r |
| 23 | #endif\r |
| 24 | #ifndef PICO_INTERNAL_ASM\r |
| 25 | #define PICO_INTERNAL_ASM\r |
| 26 | #endif\r |
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27 | \r |
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28 | // to select core, define EMU_C68K, EMU_M68K or EMU_F68K in your makefile or project\r |
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29 | \r |
| 30 | #ifdef __cplusplus\r |
| 31 | extern "C" {\r |
| 32 | #endif\r |
| 33 | \r |
| 34 | \r |
| 35 | // ----------------------- 68000 CPU -----------------------\r |
| 36 | #ifdef EMU_C68K\r |
| 37 | #include "../cpu/Cyclone/Cyclone.h"\r |
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38 | extern struct Cyclone PicoCpuCM68k, PicoCpuCS68k;\r |
| 39 | #define SekCyclesLeftNoMCD PicoCpuCM68k.cycles // cycles left for this run\r |
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40 | #define SekCyclesLeft \\r |
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41 | (((PicoAHW&1) && (PicoOpt & POPT_EN_MCD_PSYNC)) ? (SekCycleAim-SekCycleCnt) : SekCyclesLeftNoMCD)\r |
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42 | #define SekCyclesLeftS68k \\r |
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43 | ((PicoOpt & POPT_EN_MCD_PSYNC) ? (SekCycleAimS68k-SekCycleCntS68k) : PicoCpuCS68k.cycles)\r |
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44 | #define SekEndTimeslice(after) PicoCpuCM68k.cycles=after\r |
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45 | #define SekEndTimesliceS68k(after) PicoCpuCS68k.cycles=after\r |
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46 | #define SekPc (PicoCpuCM68k.pc-PicoCpuCM68k.membase)\r |
| 47 | #define SekPcS68k (PicoCpuCS68k.pc-PicoCpuCS68k.membase)\r |
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48 | #define SekDar(x) PicoCpuCM68k.d[x]\r |
| 49 | #define SekSr CycloneGetSr(&PicoCpuCM68k)\r |
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50 | #define SekSetStop(x) { PicoCpuCM68k.state_flags&=~1; if (x) { PicoCpuCM68k.state_flags|=1; PicoCpuCM68k.cycles=0; } }\r |
| 51 | #define SekSetStopS68k(x) { PicoCpuCS68k.state_flags&=~1; if (x) { PicoCpuCS68k.state_flags|=1; PicoCpuCS68k.cycles=0; } }\r |
| ca61ee42 |
52 | #define SekIsStoppedS68k() (PicoCpuCS68k.state_flags&1)\r |
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53 | #define SekShouldInterrupt (PicoCpuCM68k.irq > (PicoCpuCM68k.srh&7))\r |
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54 | \r |
| 55 | #define SekInterrupt(i) PicoCpuCM68k.irq=i\r |
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56 | #define SekIrqLevel PicoCpuCM68k.irq\r |
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57 | \r |
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58 | #ifdef EMU_M68K\r |
| 59 | #define EMU_CORE_DEBUG\r |
| 60 | #endif\r |
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61 | #endif\r |
| 62 | \r |
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63 | #ifdef EMU_F68K\r |
| 64 | #include "../cpu/fame/fame.h"\r |
| b542be46 |
65 | extern M68K_CONTEXT PicoCpuFM68k, PicoCpuFS68k;\r |
| 3aa1e148 |
66 | #define SekCyclesLeftNoMCD PicoCpuFM68k.io_cycle_counter\r |
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67 | #define SekCyclesLeft \\r |
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68 | (((PicoAHW&1) && (PicoOpt & POPT_EN_MCD_PSYNC)) ? (SekCycleAim-SekCycleCnt) : SekCyclesLeftNoMCD)\r |
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69 | #define SekCyclesLeftS68k \\r |
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70 | ((PicoOpt & POPT_EN_MCD_PSYNC) ? (SekCycleAimS68k-SekCycleCntS68k) : PicoCpuFS68k.io_cycle_counter)\r |
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71 | #define SekEndTimeslice(after) PicoCpuFM68k.io_cycle_counter=after\r |
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72 | #define SekEndTimesliceS68k(after) PicoCpuFS68k.io_cycle_counter=after\r |
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73 | #define SekPc fm68k_get_pc(&PicoCpuFM68k)\r |
| 74 | #define SekPcS68k fm68k_get_pc(&PicoCpuFS68k)\r |
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75 | #define SekDar(x) PicoCpuFM68k.dreg[x].D\r |
| 76 | #define SekSr PicoCpuFM68k.sr\r |
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77 | #define SekSetStop(x) { \\r |
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78 | PicoCpuFM68k.execinfo &= ~FM68K_HALTED; \\r |
| 79 | if (x) { PicoCpuFM68k.execinfo |= FM68K_HALTED; PicoCpuFM68k.io_cycle_counter = 0; } \\r |
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80 | }\r |
| 81 | #define SekSetStopS68k(x) { \\r |
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82 | PicoCpuFS68k.execinfo &= ~FM68K_HALTED; \\r |
| 83 | if (x) { PicoCpuFS68k.execinfo |= FM68K_HALTED; PicoCpuFS68k.io_cycle_counter = 0; } \\r |
| 70357ce5 |
84 | }\r |
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85 | #define SekIsStoppedS68k() (PicoCpuFS68k.execinfo&FM68K_HALTED)\r |
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86 | #define SekShouldInterrupt fm68k_would_interrupt()\r |
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87 | \r |
| 88 | #define SekInterrupt(irq) PicoCpuFM68k.interrupts[0]=irq\r |
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89 | #define SekIrqLevel PicoCpuFM68k.interrupts[0]\r |
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90 | \r |
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91 | #ifdef EMU_M68K\r |
| 92 | #define EMU_CORE_DEBUG\r |
| 93 | #endif\r |
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94 | #endif\r |
| 95 | \r |
| 96 | #ifdef EMU_M68K\r |
| 97 | #include "../cpu/musashi/m68kcpu.h"\r |
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98 | extern m68ki_cpu_core PicoCpuMM68k, PicoCpuMS68k;\r |
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99 | #ifndef SekCyclesLeft\r |
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100 | #define SekCyclesLeftNoMCD PicoCpuMM68k.cyc_remaining_cycles\r |
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101 | #define SekCyclesLeft \\r |
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102 | (((PicoAHW&1) && (PicoOpt & POPT_EN_MCD_PSYNC)) ? (SekCycleAim-SekCycleCnt) : SekCyclesLeftNoMCD)\r |
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103 | #define SekCyclesLeftS68k \\r |
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104 | ((PicoOpt & POPT_EN_MCD_PSYNC) ? (SekCycleAimS68k-SekCycleCntS68k) : PicoCpuMS68k.cyc_remaining_cycles)\r |
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105 | #define SekEndTimeslice(after) SET_CYCLES(after)\r |
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106 | #define SekEndTimesliceS68k(after) PicoCpuMS68k.cyc_remaining_cycles=after\r |
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107 | #define SekPc m68k_get_reg(&PicoCpuMM68k, M68K_REG_PC)\r |
| 108 | #define SekPcS68k m68k_get_reg(&PicoCpuMS68k, M68K_REG_PC)\r |
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109 | #define SekDar(x) PicoCpuMM68k.dar[x]\r |
| 110 | #define SekSr m68k_get_reg(&PicoCpuMM68k, M68K_REG_SR)\r |
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111 | #define SekSetStop(x) { \\r |
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112 | if(x) { SET_CYCLES(0); PicoCpuMM68k.stopped=STOP_LEVEL_STOP; } \\r |
| 113 | else PicoCpuMM68k.stopped=0; \\r |
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114 | }\r |
| 115 | #define SekSetStopS68k(x) { \\r |
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116 | if(x) { SET_CYCLES(0); PicoCpuMS68k.stopped=STOP_LEVEL_STOP; } \\r |
| 117 | else PicoCpuMS68k.stopped=0; \\r |
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118 | }\r |
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119 | #define SekIsStoppedS68k() (PicoCpuMS68k.stopped==STOP_LEVEL_STOP)\r |
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120 | #define SekShouldInterrupt (CPU_INT_LEVEL > FLAG_INT_MASK)\r |
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121 | \r |
| 71de3cd9 |
122 | #define SekInterrupt(irq) { \\r |
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123 | void *oldcontext = m68ki_cpu_p; \\r |
| 124 | m68k_set_context(&PicoCpuMM68k); \\r |
| 125 | m68k_set_irq(irq); \\r |
| 126 | m68k_set_context(oldcontext); \\r |
| 127 | }\r |
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128 | #define SekIrqLevel (PicoCpuMM68k.int_level >> 8)\r |
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129 | \r |
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130 | #endif\r |
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131 | #endif // EMU_M68K\r |
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132 | \r |
| 133 | extern int SekCycleCnt; // cycles done in this frame\r |
| 134 | extern int SekCycleAim; // cycle aim\r |
| 135 | extern unsigned int SekCycleCntT; // total cycle counter, updated once per frame\r |
| 136 | \r |
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137 | #define SekCyclesReset() { \\r |
| 138 | SekCycleCntT+=SekCycleAim; \\r |
| 139 | SekCycleCnt-=SekCycleAim; \\r |
| 140 | SekCycleAim=0; \\r |
| 141 | }\r |
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142 | #define SekCyclesBurn(c) SekCycleCnt+=c\r |
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143 | #define SekCyclesDone() (SekCycleAim-SekCyclesLeft) // number of cycles done in this frame (can be checked anywhere)\r |
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144 | #define SekCyclesDoneT() (SekCycleCntT+SekCyclesDone()) // total nuber of cycles done for this rom\r |
| 145 | \r |
| 146 | #define SekEndRun(after) { \\r |
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147 | SekCycleCnt -= SekCyclesLeft - (after); \\r |
| 148 | if (SekCycleCnt < 0) SekCycleCnt = 0; \\r |
| 149 | SekEndTimeslice(after); \\r |
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150 | }\r |
| 151 | \r |
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152 | #define SekEndRunS68k(after) { \\r |
| 153 | SekCycleCntS68k -= SekCyclesLeftS68k - (after); \\r |
| 154 | if (SekCycleCntS68k < 0) SekCycleCntS68k = 0; \\r |
| 155 | SekEndTimesliceS68k(after); \\r |
| 156 | }\r |
| 157 | \r |
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158 | extern int SekCycleCntS68k;\r |
| 159 | extern int SekCycleAimS68k;\r |
| 160 | \r |
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161 | #define SekCyclesResetS68k() { \\r |
| 162 | SekCycleCntS68k-=SekCycleAimS68k; \\r |
| 163 | SekCycleAimS68k=0; \\r |
| 164 | }\r |
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165 | #define SekCyclesDoneS68k() (SekCycleAimS68k-SekCyclesLeftS68k)\r |
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166 | \r |
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167 | #ifdef EMU_CORE_DEBUG\r |
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168 | extern int dbg_irq_level;\r |
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169 | #undef SekEndTimeslice\r |
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170 | #undef SekCyclesBurn\r |
| 171 | #undef SekEndRun\r |
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172 | #undef SekInterrupt\r |
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173 | #define SekEndTimeslice(c)\r |
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174 | #define SekCyclesBurn(c) c\r |
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175 | #define SekEndRun(c)\r |
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176 | #define SekInterrupt(irq) dbg_irq_level=irq\r |
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177 | #endif\r |
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178 | \r |
| b542be46 |
179 | // ----------------------- Z80 CPU -----------------------\r |
| 180 | \r |
| 181 | #if defined(_USE_MZ80)\r |
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182 | #include "../cpu/mz80/mz80.h"\r |
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183 | \r |
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184 | #define z80_run(cycles) { mz80GetElapsedTicks(1); mz80_run(cycles) }\r |
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185 | #define z80_run_nr(cycles) mz80_run(cycles)\r |
| 186 | #define z80_int() mz80int(0)\r |
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187 | \r |
| 188 | #elif defined(_USE_DRZ80)\r |
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189 | #include "../cpu/DrZ80/drz80.h"\r |
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190 | \r |
| 191 | extern struct DrZ80 drZ80;\r |
| 192 | \r |
| 193 | #define z80_run(cycles) ((cycles) - DrZ80Run(&drZ80, cycles))\r |
| 194 | #define z80_run_nr(cycles) DrZ80Run(&drZ80, cycles)\r |
| 4936aac1 |
195 | #define z80_int() drZ80.Z80_IRQ = 1\r |
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196 | \r |
| 197 | #define z80_cyclesLeft drZ80.cycles\r |
| 19954be1 |
198 | #define z80_pc() (drZ80.Z80PC - drZ80.Z80PC_BASE)\r |
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199 | \r |
| 200 | #elif defined(_USE_CZ80)\r |
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201 | #include "../cpu/cz80/cz80.h"\r |
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202 | \r |
| 203 | #define z80_run(cycles) Cz80_Exec(&CZ80, cycles)\r |
| 204 | #define z80_run_nr(cycles) Cz80_Exec(&CZ80, cycles)\r |
| 205 | #define z80_int() Cz80_Set_IRQ(&CZ80, 0, HOLD_LINE)\r |
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206 | \r |
| 207 | #define z80_cyclesLeft (CZ80.ICount - CZ80.ExtraCycles)\r |
| 19954be1 |
208 | #define z80_pc() Cz80_Get_Reg(&CZ80, CZ80_PC)\r |
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209 | \r |
| 210 | #else\r |
| 211 | \r |
| 212 | #define z80_run(cycles) (cycles)\r |
| 213 | #define z80_run_nr(cycles)\r |
| 214 | #define z80_int()\r |
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215 | \r |
| 216 | #endif\r |
| 217 | \r |
| 4b9c5888 |
218 | extern int z80stopCycle; /* in 68k cycles */\r |
| 219 | extern int z80_cycle_cnt; /* 'done' z80 cycles before z80_run() */\r |
| 220 | extern int z80_cycle_aim;\r |
| 221 | extern int z80_scanline;\r |
| 222 | extern int z80_scanline_cycles; /* cycles done until z80_scanline */\r |
| 223 | \r |
| 224 | #define z80_resetCycles() \\r |
| 225 | z80_cycle_cnt = z80_cycle_aim = z80_scanline = z80_scanline_cycles = 0;\r |
| 226 | \r |
| 227 | #define z80_cyclesDone() \\r |
| 228 | (z80_cycle_aim - z80_cyclesLeft)\r |
| 229 | \r |
| 230 | #define cycles_68k_to_z80(x) ((x)*957 >> 11)\r |
| 231 | \r |
| c8d1e9b6 |
232 | #define Z80_MEM_SHIFT 13\r |
| 233 | extern unsigned long z80_read_map [0x10000 >> Z80_MEM_SHIFT];\r |
| 234 | extern unsigned long z80_write_map[0x10000 >> Z80_MEM_SHIFT];\r |
| 235 | typedef unsigned char (z80_read_f)(unsigned short a);\r |
| 236 | typedef void (z80_write_f)(unsigned int a, unsigned char data);\r |
| 237 | \r |
| acd35d4c |
238 | // ----------------------- SH2 CPU -----------------------\r |
| 239 | \r |
| 41397701 |
240 | #include "cpu/sh2/sh2.h"\r |
| acd35d4c |
241 | \r |
| 1d7a28a7 |
242 | extern SH2 sh2s[2];\r |
| 243 | #define msh2 sh2s[0]\r |
| 244 | #define ssh2 sh2s[1]\r |
| 245 | \r |
| 679af8a3 |
246 | #ifndef DRC_SH2\r |
| 247 | # define ash2_end_run(after) if (sh2->icount > (after)) sh2->icount = after\r |
| 248 | # define ash2_cycles_done() (sh2->cycles_aim - sh2->icount)\r |
| 249 | #else\r |
| 250 | # define ash2_end_run(after) { \\r |
| 251 | if ((sh2->sr >> 12) > (after)) \\r |
| 252 | { sh2->sr &= 0xfff; sh2->sr |= (after) << 12; } \\r |
| 253 | }\r |
| 254 | # define ash2_cycles_done() (sh2->cycles_aim - (sh2->sr >> 12))\r |
| 255 | #endif\r |
| 266c6afa |
256 | \r |
| 679af8a3 |
257 | //#define sh2_pc(c) (c) ? ssh2.ppc : msh2.ppc\r |
| 258 | #define sh2_pc(c) (c) ? ssh2.pc : msh2.pc\r |
| 4ea707e1 |
259 | #define sh2_reg(c, x) (c) ? ssh2.r[x] : msh2.r[x]\r |
| 260 | #define sh2_gbr(c) (c) ? ssh2.gbr : msh2.gbr\r |
| 261 | #define sh2_vbr(c) (c) ? ssh2.vbr : msh2.vbr\r |
| 6add7875 |
262 | #define sh2_sr(c) (((c) ? ssh2.sr : msh2.sr) & 0xfff)\r |
| acd35d4c |
263 | \r |
| 83ff19ec |
264 | #define sh2_set_gbr(c, v) \\r |
| 265 | { if (c) ssh2.gbr = v; else msh2.gbr = v; }\r |
| 266 | #define sh2_set_vbr(c, v) \\r |
| 267 | { if (c) ssh2.vbr = v; else msh2.vbr = v; }\r |
| 268 | \r |
| cc68a136 |
269 | // ---------------------------------------------------------\r |
| 270 | \r |
| 271 | // main oscillator clock which controls timing\r |
| 272 | #define OSC_NTSC 53693100\r |
| b8cbd802 |
273 | #define OSC_PAL 53203424\r |
| cc68a136 |
274 | \r |
| 275 | struct PicoVideo\r |
| 276 | {\r |
| 277 | unsigned char reg[0x20];\r |
| b8cbd802 |
278 | unsigned int command; // 32-bit Command\r |
| 279 | unsigned char pending; // 1 if waiting for second half of 32-bit command\r |
| 280 | unsigned char type; // Command type (v/c/vsram read/write)\r |
| 281 | unsigned short addr; // Read/Write address\r |
| 282 | int status; // Status bits\r |
| cc68a136 |
283 | unsigned char pending_ints; // pending interrupts: ??VH????\r |
| b8cbd802 |
284 | signed char lwrite_cnt; // VDP write count during active display line\r |
| 9761a7d0 |
285 | unsigned short v_counter; // V-counter\r |
| 286 | unsigned char pad[0x10];\r |
| cc68a136 |
287 | };\r |
| 288 | \r |
| 289 | struct PicoMisc\r |
| 290 | {\r |
| 291 | unsigned char rotate;\r |
| 292 | unsigned char z80Run;\r |
| e5503e2f |
293 | unsigned char padTHPhase[2]; // 02 phase of gamepad TH switches\r |
| 2aa27095 |
294 | unsigned short scanline; // 04 0 to 261||311\r |
| e5503e2f |
295 | char dirtyPal; // 06 Is the palette dirty (1 - change @ this frame, 2 - some time before)\r |
| 296 | unsigned char hardware; // 07 Hardware value for country\r |
| 297 | unsigned char pal; // 08 1=PAL 0=NTSC\r |
| 45f2f245 |
298 | unsigned char sram_reg; // 09 SRAM reg. See SRR_* below\r |
| e5503e2f |
299 | unsigned short z80_bank68k; // 0a\r |
| be2c4208 |
300 | unsigned short pad0;\r |
| 301 | unsigned char pad1;\r |
| 0ace9b9a |
302 | unsigned char z80_reset; // 0f z80 reset held\r |
| e5503e2f |
303 | unsigned char padDelay[2]; // 10 gamepad phase time outs, so we count a delay\r |
| 1dceadae |
304 | unsigned short eeprom_addr; // EEPROM address register\r |
| 45f2f245 |
305 | unsigned char eeprom_cycle; // EEPROM cycle number\r |
| 1dceadae |
306 | unsigned char eeprom_slave; // EEPROM slave word for X24C02 and better SRAMs\r |
| 45f2f245 |
307 | unsigned char eeprom_status;\r |
| be2c4208 |
308 | unsigned char pad2;\r |
| 053fd9b4 |
309 | unsigned short dma_xfers; // 18\r |
| 45f2f245 |
310 | unsigned char eeprom_wb[2]; // EEPROM latch/write buffer\r |
| 053fd9b4 |
311 | unsigned int frame_count; // 1c for movies and idle det\r |
| cc68a136 |
312 | };\r |
| 313 | \r |
| 314 | // some assembly stuff depend on these, do not touch!\r |
| 315 | struct Pico\r |
| 316 | {\r |
| 317 | unsigned char ram[0x10000]; // 0x00000 scratch ram\r |
| 200772b7 |
318 | union { // vram is byteswapped for easier reads when drawing\r |
| 2ec9bec5 |
319 | unsigned short vram[0x8000]; // 0x10000\r |
| 320 | unsigned char vramb[0x4000]; // VRAM in SMS mode\r |
| 321 | };\r |
| cc68a136 |
322 | unsigned char zram[0x2000]; // 0x20000 Z80 ram\r |
| 323 | unsigned char ioports[0x10];\r |
| 2ec9bec5 |
324 | unsigned char sms_io_ctl;\r |
| 325 | unsigned char pad[0xef]; // unused\r |
| cc68a136 |
326 | unsigned short cram[0x40]; // 0x22100\r |
| 327 | unsigned short vsram[0x40]; // 0x22180\r |
| 328 | \r |
| 329 | unsigned char *rom; // 0x22200\r |
| 330 | unsigned int romsize; // 0x22204\r |
| 331 | \r |
| 332 | struct PicoMisc m;\r |
| 333 | struct PicoVideo video;\r |
| 334 | };\r |
| 335 | \r |
| 336 | // sram\r |
| 45f2f245 |
337 | #define SRR_MAPPED (1 << 0)\r |
| 338 | #define SRR_READONLY (1 << 1)\r |
| 339 | \r |
| 340 | #define SRF_ENABLED (1 << 0)\r |
| 341 | #define SRF_EEPROM (1 << 1)\r |
| af37bca8 |
342 | \r |
| cc68a136 |
343 | struct PicoSRAM\r |
| 344 | {\r |
| 4ff2d527 |
345 | unsigned char *data; // actual data\r |
| 346 | unsigned int start; // start address in 68k address space\r |
| cc68a136 |
347 | unsigned int end;\r |
| 45f2f245 |
348 | unsigned char flags; // 0c: SRF_*\r |
| 1dceadae |
349 | unsigned char unused2;\r |
| cc68a136 |
350 | unsigned char changed;\r |
| 45f2f245 |
351 | unsigned char eeprom_type; // eeprom type: 0: 7bit (24C01), 2: 2 addr words (X24C02+), 3: 3 addr words\r |
| 352 | unsigned char unused3;\r |
| 1dceadae |
353 | unsigned char eeprom_bit_cl; // bit number for cl\r |
| 354 | unsigned char eeprom_bit_in; // bit number for in\r |
| 355 | unsigned char eeprom_bit_out; // bit number for out\r |
| 45f2f245 |
356 | unsigned int size;\r |
| cc68a136 |
357 | };\r |
| 358 | \r |
| 359 | // MCD\r |
| 360 | #include "cd/cd_sys.h"\r |
| 361 | #include "cd/LC89510.h"\r |
| d1df8786 |
362 | #include "cd/gfx_cd.h"\r |
| cc68a136 |
363 | \r |
| 4f265db7 |
364 | struct mcd_pcm\r |
| 365 | {\r |
| 366 | unsigned char control; // reg7\r |
| 367 | unsigned char enabled; // reg8\r |
| 368 | unsigned char cur_ch;\r |
| 369 | unsigned char bank;\r |
| 370 | int pad1;\r |
| 371 | \r |
| 4ff2d527 |
372 | struct pcm_chan // 08, size 0x10\r |
| 4f265db7 |
373 | {\r |
| 374 | unsigned char regs[8];\r |
| 4ff2d527 |
375 | unsigned int addr; // .08: played sample address\r |
| 4f265db7 |
376 | int pad;\r |
| 377 | } ch[8];\r |
| 378 | };\r |
| 379 | \r |
| c459aefd |
380 | struct mcd_misc\r |
| 381 | {\r |
| 382 | unsigned short hint_vector;\r |
| 383 | unsigned char busreq;\r |
| 51a902ae |
384 | unsigned char s68k_pend_ints;\r |
| ef090115 |
385 | unsigned int state_flags; // 04: emu state: reset_pending\r |
| 51a902ae |
386 | unsigned int counter75hz;\r |
| c9e1affc |
387 | unsigned int pad0;\r |
| 4ff2d527 |
388 | int timer_int3; // 10\r |
| 4f265db7 |
389 | unsigned int timer_stopwatch;\r |
| 6cadc2da |
390 | unsigned char bcram_reg; // 18: battery-backed RAM cart register\r |
| 391 | unsigned char pad2;\r |
| 392 | unsigned short pad3;\r |
| 393 | int pad[9];\r |
| c459aefd |
394 | };\r |
| 395 | \r |
| cc68a136 |
396 | typedef struct\r |
| 397 | {\r |
| 4ff2d527 |
398 | unsigned char bios[0x20000]; // 000000: 128K\r |
| 399 | union { // 020000: 512K\r |
| fa1e5e29 |
400 | unsigned char prg_ram[0x80000];\r |
| cc68a136 |
401 | unsigned char prg_ram_b[4][0x20000];\r |
| 402 | };\r |
| 4ff2d527 |
403 | union { // 0a0000: 256K\r |
| fa1e5e29 |
404 | struct {\r |
| 405 | unsigned char word_ram2M[0x40000];\r |
| dca310c4 |
406 | unsigned char unused0[0x20000];\r |
| fa1e5e29 |
407 | };\r |
| 408 | struct {\r |
| dca310c4 |
409 | unsigned char unused1[0x20000];\r |
| fa1e5e29 |
410 | unsigned char word_ram1M[2][0x20000];\r |
| 411 | };\r |
| 412 | };\r |
| 4ff2d527 |
413 | union { // 100000: 64K\r |
| fa1e5e29 |
414 | unsigned char pcm_ram[0x10000];\r |
| 4f265db7 |
415 | unsigned char pcm_ram_b[0x10][0x1000];\r |
| 416 | };\r |
| 4ff2d527 |
417 | unsigned char s68k_regs[0x200]; // 110000: GA, not CPU regs\r |
| 418 | unsigned char bram[0x2000]; // 110200: 8K\r |
| 419 | struct mcd_misc m; // 112200: misc\r |
| 420 | struct mcd_pcm pcm; // 112240:\r |
| 75736070 |
421 | _scd_toc TOC; // not to be saved\r |
| cc68a136 |
422 | CDD cdd;\r |
| 423 | CDC cdc;\r |
| 424 | _scd scd;\r |
| d1df8786 |
425 | Rot_Comp rot_comp;\r |
| cc68a136 |
426 | } mcd_state;\r |
| 427 | \r |
| be2c4208 |
428 | // XXX: this will need to be reworked for cart+cd support.\r |
| cc68a136 |
429 | #define Pico_mcd ((mcd_state *)Pico.rom)\r |
| 430 | \r |
| be2c4208 |
431 | // 32X\r |
| acd35d4c |
432 | #define P32XS_FM (1<<15)\r |
| 83ff19ec |
433 | #define P32XS_REN (1<< 7)\r |
| 434 | #define P32XS_nRES (1<< 1)\r |
| 435 | #define P32XS_ADEN (1<< 0)\r |
| acd35d4c |
436 | #define P32XS2_ADEN (1<< 9)\r |
| 5e128c6d |
437 | #define P32XS_FULL (1<< 7) // DREQ FIFO full\r |
| 4ea707e1 |
438 | #define P32XS_68S (1<< 2)\r |
| 97d3f47f |
439 | #define P32XS_DMA (1<< 1)\r |
| 4ea707e1 |
440 | #define P32XS_RV (1<< 0)\r |
| acd35d4c |
441 | \r |
| 5e128c6d |
442 | #define P32XV_nPAL (1<<15) // VDP\r |
| acd35d4c |
443 | #define P32XV_PRI (1<< 7)\r |
| 4ea707e1 |
444 | #define P32XV_Mx (3<< 0) // display mode mask\r |
| 974fdb5b |
445 | \r |
| acd35d4c |
446 | #define P32XV_VBLK (1<<15)\r |
| 447 | #define P32XV_HBLK (1<<14)\r |
| 448 | #define P32XV_PEN (1<<13)\r |
| 449 | #define P32XV_nFEN (1<< 1)\r |
| 450 | #define P32XV_FS (1<< 0)\r |
| 974fdb5b |
451 | \r |
| db1d3564 |
452 | #define P32XP_FULL (1<<15) // PWM\r |
| 453 | #define P32XP_EMPTY (1<<14)\r |
| 454 | \r |
| 4ea707e1 |
455 | #define P32XF_68KPOLL (1 << 0)\r |
| 456 | #define P32XF_MSH2POLL (1 << 1)\r |
| 457 | #define P32XF_SSH2POLL (1 << 2)\r |
| 458 | #define P32XF_68KVPOLL (1 << 3)\r |
| 459 | #define P32XF_MSH2VPOLL (1 << 4)\r |
| 460 | #define P32XF_SSH2VPOLL (1 << 5)\r |
| 461 | \r |
| 462 | #define P32XI_VRES (1 << 14/2) // IRL/2\r |
| 463 | #define P32XI_VINT (1 << 12/2)\r |
| 464 | #define P32XI_HINT (1 << 10/2)\r |
| 465 | #define P32XI_CMD (1 << 8/2)\r |
| 466 | #define P32XI_PWM (1 << 6/2)\r |
| 467 | \r |
| 1d7a28a7 |
468 | // peripheral reg access\r |
| 469 | #define PREG8(regs,offs) ((unsigned char *)regs)[offs ^ 3]\r |
| 470 | \r |
| 4ea707e1 |
471 | // real one is 4*2, but we use more because we don't lockstep\r |
| 472 | #define DMAC_FIFO_LEN (4*4)\r |
| db1d3564 |
473 | #define PWM_BUFF_LEN 1024 // in one channel samples\r |
| 266c6afa |
474 | \r |
| f4bb5d6b |
475 | #define SH2_DRCBLK_RAM_SHIFT 1\r |
| 476 | #define SH2_DRCBLK_DA_SHIFT 1\r |
| 477 | \r |
| be2c4208 |
478 | struct Pico32x\r |
| 479 | {\r |
| 480 | unsigned short regs[0x20];\r |
| 481 | unsigned short vdp_regs[0x10];\r |
| 87accdf7 |
482 | unsigned short sh2_regs[3];\r |
| be2c4208 |
483 | unsigned char pending_fb;\r |
| 974fdb5b |
484 | unsigned char dirty_pal;\r |
| 266c6afa |
485 | unsigned int emu_flags;\r |
| 4ea707e1 |
486 | unsigned char sh2irq_mask[2];\r |
| 487 | unsigned char sh2irqi[2]; // individual\r |
| 488 | unsigned int sh2irqs; // common irqs\r |
| 489 | unsigned short dmac_fifo[DMAC_FIFO_LEN];\r |
| 490 | unsigned int dmac_ptr;\r |
| db1d3564 |
491 | unsigned int pwm_irq_sample_cnt;\r |
| 974fdb5b |
492 | };\r |
| 493 | \r |
| 494 | struct Pico32xMem\r |
| 495 | {\r |
| 496 | unsigned char sdram[0x40000];\r |
| f4bb5d6b |
497 | #ifdef DRC_SH2\r |
| 498 | unsigned short drcblk_ram[1 << (18 - SH2_DRCBLK_RAM_SHIFT)];\r |
| 499 | #endif\r |
| b78efee2 |
500 | unsigned short dram[2][0x20000/2]; // AKA fb\r |
| 501 | unsigned char m68k_rom[0x10000]; // 0x100; using M68K_BANK_SIZE\r |
| 502 | unsigned char data_array[2][0x1000]; // cache in SH2s (can be used as RAM)\r |
| f4bb5d6b |
503 | #ifdef DRC_SH2\r |
| 504 | unsigned short drcblk_da[2][1 << (12 - SH2_DRCBLK_DA_SHIFT)];\r |
| 505 | #endif\r |
| acd35d4c |
506 | unsigned char sh2_rom_m[0x800];\r |
| 507 | unsigned char sh2_rom_s[0x400];\r |
| 974fdb5b |
508 | unsigned short pal[0x100];\r |
| 5e128c6d |
509 | unsigned short pal_native[0x100]; // converted to native (for renderer)\r |
| 4ea707e1 |
510 | unsigned int sh2_peri_regs[2][0x200/4]; // periphereal regs of SH2s\r |
| db1d3564 |
511 | signed short pwm[2*PWM_BUFF_LEN]; // PWM buffer for current frame\r |
| be2c4208 |
512 | };\r |
| d49b10c2 |
513 | \r |
| c8d1e9b6 |
514 | // area.c\r |
| 2aa27095 |
515 | PICO_INTERNAL void PicoAreaPackCpu(unsigned char *cpu, int is_sub);\r |
| 516 | PICO_INTERNAL void PicoAreaUnpackCpu(unsigned char *cpu, int is_sub);\r |
| fad24893 |
517 | extern void (*PicoLoadStateHook)(void);\r |
| 51a902ae |
518 | \r |
| c8d1e9b6 |
519 | // cd/area.c\r |
| eff55556 |
520 | PICO_INTERNAL int PicoCdSaveState(void *file);\r |
| 521 | PICO_INTERNAL int PicoCdLoadState(void *file);\r |
| cc68a136 |
522 | \r |
| 945c2fdc |
523 | typedef struct {\r |
| 524 | int chunk;\r |
| 525 | int size;\r |
| 526 | void *ptr;\r |
| 527 | } carthw_state_chunk;\r |
| 528 | extern carthw_state_chunk *carthw_chunks;\r |
| 529 | #define CHUNK_CARTHW 64\r |
| 530 | \r |
| bcc9eda0 |
531 | // area.c\r |
| 532 | typedef size_t (arearw)(void *p, size_t _size, size_t _n, void *file);\r |
| 533 | typedef size_t (areaeof)(void *file);\r |
| 534 | typedef int (areaseek)(void *file, long offset, int whence);\r |
| 535 | typedef int (areaclose)(void *file);\r |
| 536 | extern arearw *areaRead; // external read and write function pointers for\r |
| 537 | extern arearw *areaWrite; // gzip save state ability\r |
| 538 | extern areaeof *areaEof;\r |
| 539 | extern areaseek *areaSeek;\r |
| 540 | extern areaclose *areaClose;\r |
| 541 | \r |
| c8d1e9b6 |
542 | // cart.c\r |
| 83ff19ec |
543 | void Byteswap(void *dst, const void *src, int len);\r |
| 45f2f245 |
544 | extern void (*PicoCartMemSetup)(void);\r |
| e807ac75 |
545 | extern void (*PicoCartUnloadHook)(void);\r |
| 1dceadae |
546 | \r |
| c8d1e9b6 |
547 | // debug.c\r |
| b5e5172d |
548 | int CM_compareRun(int cyc, int is_sub);\r |
| 03e4f2a3 |
549 | \r |
| c8d1e9b6 |
550 | // draw.c\r |
| eff55556 |
551 | PICO_INTERNAL void PicoFrameStart(void);\r |
| b6d7ac70 |
552 | void PicoDrawSync(int to, int blank_last_line);\r |
| 200772b7 |
553 | void BackFill(int reg7, int sh);\r |
| 974fdb5b |
554 | void FinalizeLineRGB555(int sh, int line);\r |
| b6d7ac70 |
555 | extern int DrawScanline;\r |
| f579f7b8 |
556 | #define MAX_LINE_SPRITES 29\r |
| 557 | extern unsigned char HighLnSpr[240][3 + MAX_LINE_SPRITES];\r |
| cc68a136 |
558 | \r |
| c8d1e9b6 |
559 | // draw2.c\r |
| eff55556 |
560 | PICO_INTERNAL void PicoFrameFull();\r |
| cc68a136 |
561 | \r |
| 200772b7 |
562 | // mode4.c\r |
| 563 | void PicoFrameStartMode4(void);\r |
| 564 | void PicoLineMode4(int line);\r |
| 565 | void PicoDoHighPal555M4(void);\r |
| 87b0845f |
566 | void PicoDrawSetColorFormatMode4(int which);\r |
| 200772b7 |
567 | \r |
| c8d1e9b6 |
568 | // memory.c\r |
| eff55556 |
569 | PICO_INTERNAL void PicoMemSetup(void);\r |
| af37bca8 |
570 | unsigned int PicoRead8_io(unsigned int a);\r |
| 571 | unsigned int PicoRead16_io(unsigned int a);\r |
| 572 | void PicoWrite8_io(unsigned int a, unsigned int d);\r |
| 573 | void PicoWrite16_io(unsigned int a, unsigned int d);\r |
| 574 | \r |
| 575 | // pico/memory.c\r |
| 576 | PICO_INTERNAL void PicoMemSetupPico(void);\r |
| cc68a136 |
577 | \r |
| c8d1e9b6 |
578 | // cd/memory.c\r |
| eff55556 |
579 | PICO_INTERNAL void PicoMemSetupCD(void);\r |
| 0ace9b9a |
580 | void PicoMemStateLoaded(void);\r |
| cc68a136 |
581 | \r |
| c8d1e9b6 |
582 | // pico.c\r |
| cc68a136 |
583 | extern struct Pico Pico;\r |
| 584 | extern struct PicoSRAM SRam;\r |
| 5f9a0d16 |
585 | extern int PicoPadInt[2];\r |
| cc68a136 |
586 | extern int emustatus;\r |
| 5e128c6d |
587 | extern int scanlines_total;\r |
| f8ef8ff7 |
588 | extern void (*PicoResetHook)(void);\r |
| b0677887 |
589 | extern void (*PicoLineHook)(void);\r |
| 1e6b5e39 |
590 | PICO_INTERNAL int CheckDMA(void);\r |
| 591 | PICO_INTERNAL void PicoDetectRegion(void);\r |
| 4b9c5888 |
592 | PICO_INTERNAL void PicoSyncZ80(int m68k_cycles_done);\r |
| cc68a136 |
593 | \r |
| c8d1e9b6 |
594 | // cd/pico.c\r |
| 2aa27095 |
595 | PICO_INTERNAL void PicoInitMCD(void);\r |
| e5f426aa |
596 | PICO_INTERNAL void PicoExitMCD(void);\r |
| 1cb1584b |
597 | PICO_INTERNAL void PicoPowerMCD(void);\r |
| 2aa27095 |
598 | PICO_INTERNAL int PicoResetMCD(void);\r |
| 599 | PICO_INTERNAL void PicoFrameMCD(void);\r |
| cc68a136 |
600 | \r |
| c8d1e9b6 |
601 | // pico/pico.c\r |
| 2aa27095 |
602 | PICO_INTERNAL void PicoInitPico(void);\r |
| ed367a3f |
603 | PICO_INTERNAL void PicoReratePico(void);\r |
| 9037e45d |
604 | \r |
| c8d1e9b6 |
605 | // pico/xpcm.c\r |
| ef4eb506 |
606 | PICO_INTERNAL void PicoPicoPCMUpdate(short *buffer, int length, int stereo);\r |
| 607 | PICO_INTERNAL void PicoPicoPCMReset(void);\r |
| 213c16ad |
608 | PICO_INTERNAL void PicoPicoPCMRerate(int xpcm_rate);\r |
| ef4eb506 |
609 | \r |
| c8d1e9b6 |
610 | // sek.c\r |
| 2aa27095 |
611 | PICO_INTERNAL void SekInit(void);\r |
| 612 | PICO_INTERNAL int SekReset(void);\r |
| 3aa1e148 |
613 | PICO_INTERNAL void SekState(int *data);\r |
| eff55556 |
614 | PICO_INTERNAL void SekSetRealTAS(int use_real);\r |
| 5f9a0d16 |
615 | void SekStepM68k(void);\r |
| 053fd9b4 |
616 | void SekInitIdleDet(void);\r |
| 617 | void SekFinishIdleDet(void);\r |
| cc68a136 |
618 | \r |
| c8d1e9b6 |
619 | // cd/sek.c\r |
| 2aa27095 |
620 | PICO_INTERNAL void SekInitS68k(void);\r |
| 621 | PICO_INTERNAL int SekResetS68k(void);\r |
| 622 | PICO_INTERNAL int SekInterruptS68k(int irq);\r |
| cc68a136 |
623 | \r |
| 7a93adeb |
624 | // sound/sound.c\r |
| c9e1affc |
625 | PICO_INTERNAL void cdda_start_play();\r |
| 626 | extern short cdda_out_buffer[2*1152];\r |
| 7a93adeb |
627 | extern int PsndLen_exc_cnt;\r |
| 628 | extern int PsndLen_exc_add;\r |
| 48dc74f2 |
629 | extern int timer_a_next_oflow, timer_a_step; // in z80 cycles\r |
| 630 | extern int timer_b_next_oflow, timer_b_step;\r |
| 43e6eaad |
631 | \r |
| 632 | void ym2612_sync_timers(int z80_cycles, int mode_old, int mode_new);\r |
| d2721b08 |
633 | void ym2612_pack_state(void);\r |
| 453d2a6e |
634 | void ym2612_unpack_state(void);\r |
| 4b9c5888 |
635 | \r |
| e53704e6 |
636 | #define TIMER_NO_OFLOW 0x70000000\r |
| 45a1ef71 |
637 | // tA = 72 * (1024 - NA) / M\r |
| 638 | #define TIMER_A_TICK_ZCYCLES 17203\r |
| 639 | // tB = 1152 * (256 - NA) / M\r |
| 640 | #define TIMER_B_TICK_ZCYCLES 262800 // 275251 broken, see Dai Makaimura\r |
| e53704e6 |
641 | \r |
| 4b9c5888 |
642 | #define timers_cycle() \\r |
| e53704e6 |
643 | if (timer_a_next_oflow > 0 && timer_a_next_oflow < TIMER_NO_OFLOW) \\r |
| 43e6eaad |
644 | timer_a_next_oflow -= Pico.m.pal ? 70938*256 : 59659*256; \\r |
| e53704e6 |
645 | if (timer_b_next_oflow > 0 && timer_b_next_oflow < TIMER_NO_OFLOW) \\r |
| 43e6eaad |
646 | timer_b_next_oflow -= Pico.m.pal ? 70938*256 : 59659*256; \\r |
| 647 | ym2612_sync_timers(0, ym2612.OPN.ST.mode, ym2612.OPN.ST.mode);\r |
| 4b9c5888 |
648 | \r |
| 649 | #define timers_reset() \\r |
| e53704e6 |
650 | timer_a_next_oflow = timer_b_next_oflow = TIMER_NO_OFLOW; \\r |
| 48dc74f2 |
651 | timer_a_step = TIMER_A_TICK_ZCYCLES * 1024; \\r |
| 652 | timer_b_step = TIMER_B_TICK_ZCYCLES * 256;\r |
| 43e6eaad |
653 | \r |
| 7a93adeb |
654 | \r |
| c8d1e9b6 |
655 | // videoport.c\r |
| eff55556 |
656 | PICO_INTERNAL_ASM void PicoVideoWrite(unsigned int a,unsigned short d);\r |
| 657 | PICO_INTERNAL_ASM unsigned int PicoVideoRead(unsigned int a);\r |
| 9761a7d0 |
658 | PICO_INTERNAL_ASM unsigned int PicoVideoRead8(unsigned int a);\r |
| 5de27868 |
659 | extern int (*PicoDmaHook)(unsigned int source, int len, unsigned short **srcp, unsigned short **limitp);\r |
| cc68a136 |
660 | \r |
| c8d1e9b6 |
661 | // misc.c\r |
| eff55556 |
662 | PICO_INTERNAL_ASM void memcpy16(unsigned short *dest, unsigned short *src, int count);\r |
| 663 | PICO_INTERNAL_ASM void memcpy16bswap(unsigned short *dest, void *src, int count);\r |
| 664 | PICO_INTERNAL_ASM void memcpy32(int *dest, int *src, int count); // 32bit word count\r |
| 665 | PICO_INTERNAL_ASM void memset32(int *dest, int c, int count);\r |
| cc68a136 |
666 | \r |
| 45f2f245 |
667 | // eeprom.c\r |
| 668 | void EEPROM_write8(unsigned int a, unsigned int d);\r |
| 669 | void EEPROM_write16(unsigned int d);\r |
| 670 | unsigned int EEPROM_read(void);\r |
| 671 | \r |
| c8d1e9b6 |
672 | // z80 functionality wrappers\r |
| 673 | PICO_INTERNAL void z80_init(void);\r |
| 674 | PICO_INTERNAL void z80_pack(unsigned char *data);\r |
| 675 | PICO_INTERNAL void z80_unpack(unsigned char *data);\r |
| 676 | PICO_INTERNAL void z80_reset(void);\r |
| 677 | PICO_INTERNAL void z80_exit(void);\r |
| c8d1e9b6 |
678 | \r |
| 679 | // cd/misc.c\r |
| eff55556 |
680 | PICO_INTERNAL_ASM void wram_2M_to_1M(unsigned char *m);\r |
| 681 | PICO_INTERNAL_ASM void wram_1M_to_2M(unsigned char *m);\r |
| 682 | \r |
| 683 | // cd/buffering.c\r |
| 684 | PICO_INTERNAL void PicoCDBufferRead(void *dest, int lba);\r |
| 685 | \r |
| 686 | // sound/sound.c\r |
| 9d917eea |
687 | PICO_INTERNAL void PsndReset(void);\r |
| 4b9c5888 |
688 | PICO_INTERNAL void PsndDoDAC(int line_to);\r |
| 9d917eea |
689 | PICO_INTERNAL void PsndClear(void);\r |
| 7b3f44c6 |
690 | PICO_INTERNAL void PsndGetSamples(int y);\r |
| 2ec9bec5 |
691 | PICO_INTERNAL void PsndGetSamplesMS(void);\r |
| 4b9c5888 |
692 | extern int PsndDacLine;\r |
| cc68a136 |
693 | \r |
| 3e49ffd0 |
694 | // sms.c\r |
| 695 | void PicoPowerMS(void);\r |
| 2ec9bec5 |
696 | void PicoResetMS(void);\r |
| 3e49ffd0 |
697 | void PicoMemSetupMS(void);\r |
| 698 | void PicoFrameMS(void);\r |
| 87b0845f |
699 | void PicoFrameDrawOnlyMS(void);\r |
| 3e49ffd0 |
700 | \r |
| be2c4208 |
701 | // 32x/32x.c\r |
| 702 | extern struct Pico32x Pico32x;\r |
| 703 | void Pico32xInit(void);\r |
| 974fdb5b |
704 | void PicoPower32x(void);\r |
| be2c4208 |
705 | void PicoReset32x(void);\r |
| 974fdb5b |
706 | void Pico32xStartup(void);\r |
| 5e49c3a8 |
707 | void PicoUnload32x(void);\r |
| 974fdb5b |
708 | void PicoFrame32x(void);\r |
| 4ea707e1 |
709 | void p32x_update_irls(void);\r |
| 83ff19ec |
710 | void p32x_reset_sh2s(void);\r |
| be2c4208 |
711 | \r |
| 712 | // 32x/memory.c\r |
| 974fdb5b |
713 | struct Pico32xMem *Pico32xMem;\r |
| be2c4208 |
714 | unsigned int PicoRead8_32x(unsigned int a);\r |
| 715 | unsigned int PicoRead16_32x(unsigned int a);\r |
| 716 | void PicoWrite8_32x(unsigned int a, unsigned int d);\r |
| 717 | void PicoWrite16_32x(unsigned int a, unsigned int d);\r |
| 718 | void PicoMemSetup32x(void);\r |
| 974fdb5b |
719 | void Pico32xSwapDRAM(int b);\r |
| 87accdf7 |
720 | void p32x_poll_event(int cpu_mask, int is_vdp);\r |
| 974fdb5b |
721 | \r |
| 722 | // 32x/draw.c\r |
| 723 | void FinalizeLine32xRGB555(int sh, int line);\r |
| be2c4208 |
724 | \r |
| db1d3564 |
725 | // 32x/pwm.c\r |
| 726 | unsigned int p32x_pwm_read16(unsigned int a);\r |
| 727 | void p32x_pwm_write16(unsigned int a, unsigned int d);\r |
| db1d3564 |
728 | void p32x_pwm_update(int *buf32, int length, int stereo);\r |
| 1d7a28a7 |
729 | void p32x_timers_do(int new_line);\r |
| 730 | void p32x_timers_recalc(void);\r |
| db1d3564 |
731 | extern int pwm_frame_smp_cnt;\r |
| 732 | \r |
| 45f2f245 |
733 | /* avoid dependency on newer glibc */\r |
| 734 | static __inline int isspace_(int c)\r |
| 735 | {\r |
| 736 | return (0x09 <= c && c <= 0x0d) || c == ' ';\r |
| 737 | }\r |
| 738 | \r |
| f4bb5d6b |
739 | #ifndef ARRAY_SIZE\r |
| 740 | #define ARRAY_SIZE(x) (sizeof(x) / sizeof(x[0]))\r |
| 741 | #endif\r |
| 742 | \r |
| b8cbd802 |
743 | // emulation event logging\r |
| 744 | #ifndef EL_LOGMASK\r |
| 745 | #define EL_LOGMASK 0\r |
| 746 | #endif\r |
| 747 | \r |
| 017512f2 |
748 | #define EL_HVCNT 0x00000001 /* hv counter reads */\r |
| 749 | #define EL_SR 0x00000002 /* SR reads */\r |
| 750 | #define EL_INTS 0x00000004 /* ints and acks */\r |
| 43e6eaad |
751 | #define EL_YMTIMER 0x00000008 /* ym2612 timer stuff */\r |
| 017512f2 |
752 | #define EL_INTSW 0x00000010 /* log irq switching on/off */\r |
| 753 | #define EL_ASVDP 0x00000020 /* VDP accesses during active scan */\r |
| 754 | #define EL_VDPDMA 0x00000040 /* VDP DMA transfers and their timing */\r |
| 755 | #define EL_BUSREQ 0x00000080 /* z80 busreq r/w or reset w */\r |
| 756 | #define EL_Z80BNK 0x00000100 /* z80 i/o through bank area */\r |
| 757 | #define EL_SRAMIO 0x00000200 /* sram i/o */\r |
| 758 | #define EL_EEPROM 0x00000400 /* eeprom debug */\r |
| 759 | #define EL_UIO 0x00000800 /* unmapped i/o */\r |
| 760 | #define EL_IO 0x00001000 /* all i/o */\r |
| 761 | #define EL_CDPOLL 0x00002000 /* MCD: log poll detection */\r |
| 762 | #define EL_SVP 0x00004000 /* SVP stuff */\r |
| fa22af4c |
763 | #define EL_PICOHW 0x00008000 /* Pico stuff */\r |
| 053fd9b4 |
764 | #define EL_IDLE 0x00010000 /* idle loop det. */\r |
| af37bca8 |
765 | #define EL_CDREGS 0x00020000 /* MCD: register access */\r |
| 766 | #define EL_CDREG3 0x00040000 /* MCD: register 3 only */\r |
| be2c4208 |
767 | #define EL_32X 0x00080000\r |
| 1b3f5844 |
768 | #define EL_PWM 0x00100000 /* 32X PWM stuff (LOTS of output) */\r |
| 017512f2 |
769 | \r |
| 770 | #define EL_STATUS 0x40000000 /* status messages */\r |
| 771 | #define EL_ANOMALY 0x80000000 /* some unexpected conditions (during emulation) */\r |
| b8cbd802 |
772 | \r |
| 773 | #if EL_LOGMASK\r |
| 7d0143a2 |
774 | extern void lprintf(const char *fmt, ...);\r |
| b8cbd802 |
775 | #define elprintf(w,f,...) \\r |
| 776 | { \\r |
| 777 | if ((w) & EL_LOGMASK) \\r |
| 7d0143a2 |
778 | lprintf("%05i:%03i: " f "\n",Pico.m.frame_count,Pico.m.scanline,##__VA_ARGS__); \\r |
| b8cbd802 |
779 | }\r |
| dca310c4 |
780 | #elif defined(_MSC_VER)\r |
| 781 | #define elprintf\r |
| b8cbd802 |
782 | #else\r |
| 783 | #define elprintf(w,f,...)\r |
| 784 | #endif\r |
| 785 | \r |
| dca310c4 |
786 | #ifdef _MSC_VER\r |
| 787 | #define cdprintf\r |
| 788 | #else\r |
| 789 | #define cdprintf(x...)\r |
| 790 | #endif\r |
| 791 | \r |
| 3e49ffd0 |
792 | #if defined(__GNUC__) && __GNUC__ >= 4 && __GNUC_MINOR__ >= 3\r |
| c8d1e9b6 |
793 | #define MEMH_FUNC __attribute__((aligned(4)))\r |
| 794 | #else\r |
| 795 | #define MEMH_FUNC\r |
| 796 | #endif\r |
| 797 | \r |
| 5e89f0f5 |
798 | #ifdef __GNUC__\r |
| 799 | #define NOINLINE __attribute__((noinline))\r |
| 800 | #else\r |
| 801 | #define NOINLINE\r |
| 802 | #endif\r |
| 803 | \r |
| f8af9634 |
804 | #ifdef __cplusplus\r |
| 805 | } // End of extern "C"\r |
| 806 | #endif\r |
| 807 | \r |
| eff55556 |
808 | #endif // PICO_INTERNAL_INCLUDED\r |
| 809 | \r |
notaz.gp2x.de / picodrive.git / blame