eff55556 |
1 | // Pico Library - Internal Header File\r |
cc68a136 |
2 | \r |
3 | // (c) Copyright 2004 Dave, All rights reserved.\r |
db1d3564 |
4 | // (c) Copyright 2006-2009 Grazvydas "notaz" Ignotas, all rights reserved.\r |
cc68a136 |
5 | // Free for non-commercial use.\r |
6 | \r |
7 | // For commercial use, separate licencing terms must be obtained.\r |
8 | \r |
eff55556 |
9 | #ifndef PICO_INTERNAL_INCLUDED\r |
10 | #define PICO_INTERNAL_INCLUDED\r |
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11 | \r |
12 | #include <stdio.h>\r |
13 | #include <stdlib.h>\r |
14 | #include <string.h>\r |
efcba75f |
15 | #include "pico.h"\r |
f53f286a |
16 | #include "carthw/carthw.h"\r |
cc68a136 |
17 | \r |
89fa852d |
18 | //\r |
19 | #define USE_POLL_DETECT\r |
20 | \r |
eff55556 |
21 | #ifndef PICO_INTERNAL\r |
22 | #define PICO_INTERNAL\r |
23 | #endif\r |
24 | #ifndef PICO_INTERNAL_ASM\r |
25 | #define PICO_INTERNAL_ASM\r |
26 | #endif\r |
cc68a136 |
27 | \r |
70357ce5 |
28 | // to select core, define EMU_C68K, EMU_M68K or EMU_F68K in your makefile or project\r |
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29 | \r |
30 | #ifdef __cplusplus\r |
31 | extern "C" {\r |
32 | #endif\r |
33 | \r |
34 | \r |
35 | // ----------------------- 68000 CPU -----------------------\r |
36 | #ifdef EMU_C68K\r |
37 | #include "../cpu/Cyclone/Cyclone.h"\r |
3aa1e148 |
38 | extern struct Cyclone PicoCpuCM68k, PicoCpuCS68k;\r |
39 | #define SekCyclesLeftNoMCD PicoCpuCM68k.cycles // cycles left for this run\r |
7336a99a |
40 | #define SekCyclesLeft \\r |
602133e1 |
41 | (((PicoAHW&1) && (PicoOpt & POPT_EN_MCD_PSYNC)) ? (SekCycleAim-SekCycleCnt) : SekCyclesLeftNoMCD)\r |
7a1f6e45 |
42 | #define SekCyclesLeftS68k \\r |
602133e1 |
43 | ((PicoOpt & POPT_EN_MCD_PSYNC) ? (SekCycleAimS68k-SekCycleCntS68k) : PicoCpuCS68k.cycles)\r |
ef090115 |
44 | #define SekEndTimeslice(after) PicoCpuCM68k.cycles=after\r |
07ceafdb |
45 | #define SekEndTimesliceS68k(after) PicoCpuCS68k.cycles=after\r |
3aa1e148 |
46 | #define SekPc (PicoCpuCM68k.pc-PicoCpuCM68k.membase)\r |
47 | #define SekPcS68k (PicoCpuCS68k.pc-PicoCpuCS68k.membase)\r |
5fadfb1c |
48 | #define SekDar(x) PicoCpuCM68k.d[x]\r |
49 | #define SekSr CycloneGetSr(&PicoCpuCM68k)\r |
3aa1e148 |
50 | #define SekSetStop(x) { PicoCpuCM68k.state_flags&=~1; if (x) { PicoCpuCM68k.state_flags|=1; PicoCpuCM68k.cycles=0; } }\r |
51 | #define SekSetStopS68k(x) { PicoCpuCS68k.state_flags&=~1; if (x) { PicoCpuCS68k.state_flags|=1; PicoCpuCS68k.cycles=0; } }\r |
ca61ee42 |
52 | #define SekIsStoppedS68k() (PicoCpuCS68k.state_flags&1)\r |
03e4f2a3 |
53 | #define SekShouldInterrupt (PicoCpuCM68k.irq > (PicoCpuCM68k.srh&7))\r |
b542be46 |
54 | \r |
55 | #define SekInterrupt(i) PicoCpuCM68k.irq=i\r |
5fadfb1c |
56 | #define SekIrqLevel PicoCpuCM68k.irq\r |
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57 | \r |
03e4f2a3 |
58 | #ifdef EMU_M68K\r |
59 | #define EMU_CORE_DEBUG\r |
60 | #endif\r |
cc68a136 |
61 | #endif\r |
62 | \r |
70357ce5 |
63 | #ifdef EMU_F68K\r |
64 | #include "../cpu/fame/fame.h"\r |
b542be46 |
65 | extern M68K_CONTEXT PicoCpuFM68k, PicoCpuFS68k;\r |
3aa1e148 |
66 | #define SekCyclesLeftNoMCD PicoCpuFM68k.io_cycle_counter\r |
70357ce5 |
67 | #define SekCyclesLeft \\r |
602133e1 |
68 | (((PicoAHW&1) && (PicoOpt & POPT_EN_MCD_PSYNC)) ? (SekCycleAim-SekCycleCnt) : SekCyclesLeftNoMCD)\r |
70357ce5 |
69 | #define SekCyclesLeftS68k \\r |
602133e1 |
70 | ((PicoOpt & POPT_EN_MCD_PSYNC) ? (SekCycleAimS68k-SekCycleCntS68k) : PicoCpuFS68k.io_cycle_counter)\r |
ef090115 |
71 | #define SekEndTimeslice(after) PicoCpuFM68k.io_cycle_counter=after\r |
07ceafdb |
72 | #define SekEndTimesliceS68k(after) PicoCpuFS68k.io_cycle_counter=after\r |
03e4f2a3 |
73 | #define SekPc fm68k_get_pc(&PicoCpuFM68k)\r |
74 | #define SekPcS68k fm68k_get_pc(&PicoCpuFS68k)\r |
5fadfb1c |
75 | #define SekDar(x) PicoCpuFM68k.dreg[x].D\r |
76 | #define SekSr PicoCpuFM68k.sr\r |
70357ce5 |
77 | #define SekSetStop(x) { \\r |
03e4f2a3 |
78 | PicoCpuFM68k.execinfo &= ~FM68K_HALTED; \\r |
79 | if (x) { PicoCpuFM68k.execinfo |= FM68K_HALTED; PicoCpuFM68k.io_cycle_counter = 0; } \\r |
70357ce5 |
80 | }\r |
81 | #define SekSetStopS68k(x) { \\r |
03e4f2a3 |
82 | PicoCpuFS68k.execinfo &= ~FM68K_HALTED; \\r |
83 | if (x) { PicoCpuFS68k.execinfo |= FM68K_HALTED; PicoCpuFS68k.io_cycle_counter = 0; } \\r |
70357ce5 |
84 | }\r |
ca61ee42 |
85 | #define SekIsStoppedS68k() (PicoCpuFS68k.execinfo&FM68K_HALTED)\r |
03e4f2a3 |
86 | #define SekShouldInterrupt fm68k_would_interrupt()\r |
b542be46 |
87 | \r |
88 | #define SekInterrupt(irq) PicoCpuFM68k.interrupts[0]=irq\r |
5fadfb1c |
89 | #define SekIrqLevel PicoCpuFM68k.interrupts[0]\r |
b542be46 |
90 | \r |
03e4f2a3 |
91 | #ifdef EMU_M68K\r |
92 | #define EMU_CORE_DEBUG\r |
93 | #endif\r |
cc68a136 |
94 | #endif\r |
95 | \r |
96 | #ifdef EMU_M68K\r |
97 | #include "../cpu/musashi/m68kcpu.h"\r |
3aa1e148 |
98 | extern m68ki_cpu_core PicoCpuMM68k, PicoCpuMS68k;\r |
cc68a136 |
99 | #ifndef SekCyclesLeft\r |
3aa1e148 |
100 | #define SekCyclesLeftNoMCD PicoCpuMM68k.cyc_remaining_cycles\r |
7336a99a |
101 | #define SekCyclesLeft \\r |
602133e1 |
102 | (((PicoAHW&1) && (PicoOpt & POPT_EN_MCD_PSYNC)) ? (SekCycleAim-SekCycleCnt) : SekCyclesLeftNoMCD)\r |
7a1f6e45 |
103 | #define SekCyclesLeftS68k \\r |
602133e1 |
104 | ((PicoOpt & POPT_EN_MCD_PSYNC) ? (SekCycleAimS68k-SekCycleCntS68k) : PicoCpuMS68k.cyc_remaining_cycles)\r |
ef090115 |
105 | #define SekEndTimeslice(after) SET_CYCLES(after)\r |
07ceafdb |
106 | #define SekEndTimesliceS68k(after) PicoCpuMS68k.cyc_remaining_cycles=after\r |
3aa1e148 |
107 | #define SekPc m68k_get_reg(&PicoCpuMM68k, M68K_REG_PC)\r |
108 | #define SekPcS68k m68k_get_reg(&PicoCpuMS68k, M68K_REG_PC)\r |
5fadfb1c |
109 | #define SekDar(x) PicoCpuMM68k.dar[x]\r |
110 | #define SekSr m68k_get_reg(&PicoCpuMM68k, M68K_REG_SR)\r |
7a1f6e45 |
111 | #define SekSetStop(x) { \\r |
3aa1e148 |
112 | if(x) { SET_CYCLES(0); PicoCpuMM68k.stopped=STOP_LEVEL_STOP; } \\r |
113 | else PicoCpuMM68k.stopped=0; \\r |
7a1f6e45 |
114 | }\r |
115 | #define SekSetStopS68k(x) { \\r |
3aa1e148 |
116 | if(x) { SET_CYCLES(0); PicoCpuMS68k.stopped=STOP_LEVEL_STOP; } \\r |
117 | else PicoCpuMS68k.stopped=0; \\r |
7a1f6e45 |
118 | }\r |
ca61ee42 |
119 | #define SekIsStoppedS68k() (PicoCpuMS68k.stopped==STOP_LEVEL_STOP)\r |
03e4f2a3 |
120 | #define SekShouldInterrupt (CPU_INT_LEVEL > FLAG_INT_MASK)\r |
b542be46 |
121 | \r |
71de3cd9 |
122 | #define SekInterrupt(irq) { \\r |
b542be46 |
123 | void *oldcontext = m68ki_cpu_p; \\r |
124 | m68k_set_context(&PicoCpuMM68k); \\r |
125 | m68k_set_irq(irq); \\r |
126 | m68k_set_context(oldcontext); \\r |
127 | }\r |
5fadfb1c |
128 | #define SekIrqLevel (PicoCpuMM68k.int_level >> 8)\r |
b542be46 |
129 | \r |
cc68a136 |
130 | #endif\r |
ef090115 |
131 | #endif // EMU_M68K\r |
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132 | \r |
133 | extern int SekCycleCnt; // cycles done in this frame\r |
134 | extern int SekCycleAim; // cycle aim\r |
135 | extern unsigned int SekCycleCntT; // total cycle counter, updated once per frame\r |
136 | \r |
b8cbd802 |
137 | #define SekCyclesReset() { \\r |
138 | SekCycleCntT+=SekCycleAim; \\r |
139 | SekCycleCnt-=SekCycleAim; \\r |
140 | SekCycleAim=0; \\r |
141 | }\r |
cc68a136 |
142 | #define SekCyclesBurn(c) SekCycleCnt+=c\r |
4b9c5888 |
143 | #define SekCyclesDone() (SekCycleAim-SekCyclesLeft) // number of cycles done in this frame (can be checked anywhere)\r |
cc68a136 |
144 | #define SekCyclesDoneT() (SekCycleCntT+SekCyclesDone()) // total nuber of cycles done for this rom\r |
145 | \r |
146 | #define SekEndRun(after) { \\r |
ef090115 |
147 | SekCycleCnt -= SekCyclesLeft - (after); \\r |
148 | if (SekCycleCnt < 0) SekCycleCnt = 0; \\r |
149 | SekEndTimeslice(after); \\r |
cc68a136 |
150 | }\r |
151 | \r |
07ceafdb |
152 | #define SekEndRunS68k(after) { \\r |
153 | SekCycleCntS68k -= SekCyclesLeftS68k - (after); \\r |
154 | if (SekCycleCntS68k < 0) SekCycleCntS68k = 0; \\r |
155 | SekEndTimesliceS68k(after); \\r |
156 | }\r |
157 | \r |
cc68a136 |
158 | extern int SekCycleCntS68k;\r |
159 | extern int SekCycleAimS68k;\r |
160 | \r |
bf5fbbb4 |
161 | #define SekCyclesResetS68k() { \\r |
162 | SekCycleCntS68k-=SekCycleAimS68k; \\r |
163 | SekCycleAimS68k=0; \\r |
164 | }\r |
7a1f6e45 |
165 | #define SekCyclesDoneS68k() (SekCycleAimS68k-SekCyclesLeftS68k)\r |
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166 | \r |
03e4f2a3 |
167 | #ifdef EMU_CORE_DEBUG\r |
99464b62 |
168 | extern int dbg_irq_level;\r |
ef090115 |
169 | #undef SekEndTimeslice\r |
2d0b15bb |
170 | #undef SekCyclesBurn\r |
171 | #undef SekEndRun\r |
99464b62 |
172 | #undef SekInterrupt\r |
ef090115 |
173 | #define SekEndTimeslice(c)\r |
2270612a |
174 | #define SekCyclesBurn(c) c\r |
2d0b15bb |
175 | #define SekEndRun(c)\r |
99464b62 |
176 | #define SekInterrupt(irq) dbg_irq_level=irq\r |
2d0b15bb |
177 | #endif\r |
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178 | \r |
b542be46 |
179 | // ----------------------- Z80 CPU -----------------------\r |
180 | \r |
181 | #if defined(_USE_MZ80)\r |
dca310c4 |
182 | #include "../cpu/mz80/mz80.h"\r |
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183 | \r |
4b9c5888 |
184 | #define z80_run(cycles) { mz80GetElapsedTicks(1); mz80_run(cycles) }\r |
b542be46 |
185 | #define z80_run_nr(cycles) mz80_run(cycles)\r |
186 | #define z80_int() mz80int(0)\r |
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187 | \r |
188 | #elif defined(_USE_DRZ80)\r |
dca310c4 |
189 | #include "../cpu/DrZ80/drz80.h"\r |
b542be46 |
190 | \r |
191 | extern struct DrZ80 drZ80;\r |
192 | \r |
193 | #define z80_run(cycles) ((cycles) - DrZ80Run(&drZ80, cycles))\r |
194 | #define z80_run_nr(cycles) DrZ80Run(&drZ80, cycles)\r |
4936aac1 |
195 | #define z80_int() drZ80.Z80_IRQ = 1\r |
4b9c5888 |
196 | \r |
197 | #define z80_cyclesLeft drZ80.cycles\r |
19954be1 |
198 | #define z80_pc() (drZ80.Z80PC - drZ80.Z80PC_BASE)\r |
b542be46 |
199 | \r |
200 | #elif defined(_USE_CZ80)\r |
dca310c4 |
201 | #include "../cpu/cz80/cz80.h"\r |
b542be46 |
202 | \r |
203 | #define z80_run(cycles) Cz80_Exec(&CZ80, cycles)\r |
204 | #define z80_run_nr(cycles) Cz80_Exec(&CZ80, cycles)\r |
205 | #define z80_int() Cz80_Set_IRQ(&CZ80, 0, HOLD_LINE)\r |
4b9c5888 |
206 | \r |
207 | #define z80_cyclesLeft (CZ80.ICount - CZ80.ExtraCycles)\r |
19954be1 |
208 | #define z80_pc() Cz80_Get_Reg(&CZ80, CZ80_PC)\r |
b542be46 |
209 | \r |
210 | #else\r |
211 | \r |
212 | #define z80_run(cycles) (cycles)\r |
213 | #define z80_run_nr(cycles)\r |
214 | #define z80_int()\r |
b542be46 |
215 | \r |
216 | #endif\r |
217 | \r |
4b9c5888 |
218 | extern int z80stopCycle; /* in 68k cycles */\r |
219 | extern int z80_cycle_cnt; /* 'done' z80 cycles before z80_run() */\r |
220 | extern int z80_cycle_aim;\r |
221 | extern int z80_scanline;\r |
222 | extern int z80_scanline_cycles; /* cycles done until z80_scanline */\r |
223 | \r |
224 | #define z80_resetCycles() \\r |
225 | z80_cycle_cnt = z80_cycle_aim = z80_scanline = z80_scanline_cycles = 0;\r |
226 | \r |
227 | #define z80_cyclesDone() \\r |
228 | (z80_cycle_aim - z80_cyclesLeft)\r |
229 | \r |
230 | #define cycles_68k_to_z80(x) ((x)*957 >> 11)\r |
231 | \r |
acd35d4c |
232 | // ----------------------- SH2 CPU -----------------------\r |
233 | \r |
41397701 |
234 | #include "cpu/sh2/sh2.h"\r |
acd35d4c |
235 | \r |
1d7a28a7 |
236 | extern SH2 sh2s[2];\r |
237 | #define msh2 sh2s[0]\r |
238 | #define ssh2 sh2s[1]\r |
239 | \r |
679af8a3 |
240 | #ifndef DRC_SH2\r |
241 | # define ash2_end_run(after) if (sh2->icount > (after)) sh2->icount = after\r |
242 | # define ash2_cycles_done() (sh2->cycles_aim - sh2->icount)\r |
243 | #else\r |
244 | # define ash2_end_run(after) { \\r |
245 | if ((sh2->sr >> 12) > (after)) \\r |
246 | { sh2->sr &= 0xfff; sh2->sr |= (after) << 12; } \\r |
247 | }\r |
248 | # define ash2_cycles_done() (sh2->cycles_aim - (sh2->sr >> 12))\r |
249 | #endif\r |
266c6afa |
250 | \r |
679af8a3 |
251 | //#define sh2_pc(c) (c) ? ssh2.ppc : msh2.ppc\r |
252 | #define sh2_pc(c) (c) ? ssh2.pc : msh2.pc\r |
4ea707e1 |
253 | #define sh2_reg(c, x) (c) ? ssh2.r[x] : msh2.r[x]\r |
254 | #define sh2_gbr(c) (c) ? ssh2.gbr : msh2.gbr\r |
255 | #define sh2_vbr(c) (c) ? ssh2.vbr : msh2.vbr\r |
6add7875 |
256 | #define sh2_sr(c) (((c) ? ssh2.sr : msh2.sr) & 0xfff)\r |
acd35d4c |
257 | \r |
83ff19ec |
258 | #define sh2_set_gbr(c, v) \\r |
259 | { if (c) ssh2.gbr = v; else msh2.gbr = v; }\r |
260 | #define sh2_set_vbr(c, v) \\r |
261 | { if (c) ssh2.vbr = v; else msh2.vbr = v; }\r |
262 | \r |
cc68a136 |
263 | // ---------------------------------------------------------\r |
264 | \r |
265 | // main oscillator clock which controls timing\r |
266 | #define OSC_NTSC 53693100\r |
b8cbd802 |
267 | #define OSC_PAL 53203424\r |
cc68a136 |
268 | \r |
269 | struct PicoVideo\r |
270 | {\r |
271 | unsigned char reg[0x20];\r |
b8cbd802 |
272 | unsigned int command; // 32-bit Command\r |
273 | unsigned char pending; // 1 if waiting for second half of 32-bit command\r |
274 | unsigned char type; // Command type (v/c/vsram read/write)\r |
275 | unsigned short addr; // Read/Write address\r |
276 | int status; // Status bits\r |
cc68a136 |
277 | unsigned char pending_ints; // pending interrupts: ??VH????\r |
b8cbd802 |
278 | signed char lwrite_cnt; // VDP write count during active display line\r |
9761a7d0 |
279 | unsigned short v_counter; // V-counter\r |
280 | unsigned char pad[0x10];\r |
cc68a136 |
281 | };\r |
282 | \r |
283 | struct PicoMisc\r |
284 | {\r |
285 | unsigned char rotate;\r |
286 | unsigned char z80Run;\r |
e5503e2f |
287 | unsigned char padTHPhase[2]; // 02 phase of gamepad TH switches\r |
2aa27095 |
288 | unsigned short scanline; // 04 0 to 261||311\r |
e5503e2f |
289 | char dirtyPal; // 06 Is the palette dirty (1 - change @ this frame, 2 - some time before)\r |
290 | unsigned char hardware; // 07 Hardware value for country\r |
291 | unsigned char pal; // 08 1=PAL 0=NTSC\r |
45f2f245 |
292 | unsigned char sram_reg; // 09 SRAM reg. See SRR_* below\r |
e5503e2f |
293 | unsigned short z80_bank68k; // 0a\r |
be2c4208 |
294 | unsigned short pad0;\r |
295 | unsigned char pad1;\r |
0ace9b9a |
296 | unsigned char z80_reset; // 0f z80 reset held\r |
e5503e2f |
297 | unsigned char padDelay[2]; // 10 gamepad phase time outs, so we count a delay\r |
1dceadae |
298 | unsigned short eeprom_addr; // EEPROM address register\r |
45f2f245 |
299 | unsigned char eeprom_cycle; // EEPROM cycle number\r |
1dceadae |
300 | unsigned char eeprom_slave; // EEPROM slave word for X24C02 and better SRAMs\r |
45f2f245 |
301 | unsigned char eeprom_status;\r |
be2c4208 |
302 | unsigned char pad2;\r |
053fd9b4 |
303 | unsigned short dma_xfers; // 18\r |
45f2f245 |
304 | unsigned char eeprom_wb[2]; // EEPROM latch/write buffer\r |
053fd9b4 |
305 | unsigned int frame_count; // 1c for movies and idle det\r |
cc68a136 |
306 | };\r |
307 | \r |
308 | // some assembly stuff depend on these, do not touch!\r |
309 | struct Pico\r |
310 | {\r |
311 | unsigned char ram[0x10000]; // 0x00000 scratch ram\r |
200772b7 |
312 | union { // vram is byteswapped for easier reads when drawing\r |
2ec9bec5 |
313 | unsigned short vram[0x8000]; // 0x10000\r |
314 | unsigned char vramb[0x4000]; // VRAM in SMS mode\r |
315 | };\r |
cc68a136 |
316 | unsigned char zram[0x2000]; // 0x20000 Z80 ram\r |
317 | unsigned char ioports[0x10];\r |
2ec9bec5 |
318 | unsigned char sms_io_ctl;\r |
319 | unsigned char pad[0xef]; // unused\r |
cc68a136 |
320 | unsigned short cram[0x40]; // 0x22100\r |
321 | unsigned short vsram[0x40]; // 0x22180\r |
322 | \r |
323 | unsigned char *rom; // 0x22200\r |
324 | unsigned int romsize; // 0x22204\r |
325 | \r |
326 | struct PicoMisc m;\r |
327 | struct PicoVideo video;\r |
328 | };\r |
329 | \r |
330 | // sram\r |
45f2f245 |
331 | #define SRR_MAPPED (1 << 0)\r |
332 | #define SRR_READONLY (1 << 1)\r |
333 | \r |
334 | #define SRF_ENABLED (1 << 0)\r |
335 | #define SRF_EEPROM (1 << 1)\r |
af37bca8 |
336 | \r |
cc68a136 |
337 | struct PicoSRAM\r |
338 | {\r |
4ff2d527 |
339 | unsigned char *data; // actual data\r |
340 | unsigned int start; // start address in 68k address space\r |
cc68a136 |
341 | unsigned int end;\r |
45f2f245 |
342 | unsigned char flags; // 0c: SRF_*\r |
1dceadae |
343 | unsigned char unused2;\r |
cc68a136 |
344 | unsigned char changed;\r |
45f2f245 |
345 | unsigned char eeprom_type; // eeprom type: 0: 7bit (24C01), 2: 2 addr words (X24C02+), 3: 3 addr words\r |
346 | unsigned char unused3;\r |
1dceadae |
347 | unsigned char eeprom_bit_cl; // bit number for cl\r |
348 | unsigned char eeprom_bit_in; // bit number for in\r |
349 | unsigned char eeprom_bit_out; // bit number for out\r |
45f2f245 |
350 | unsigned int size;\r |
cc68a136 |
351 | };\r |
352 | \r |
353 | // MCD\r |
354 | #include "cd/cd_sys.h"\r |
355 | #include "cd/LC89510.h"\r |
d1df8786 |
356 | #include "cd/gfx_cd.h"\r |
cc68a136 |
357 | \r |
4f265db7 |
358 | struct mcd_pcm\r |
359 | {\r |
360 | unsigned char control; // reg7\r |
361 | unsigned char enabled; // reg8\r |
362 | unsigned char cur_ch;\r |
363 | unsigned char bank;\r |
364 | int pad1;\r |
365 | \r |
4ff2d527 |
366 | struct pcm_chan // 08, size 0x10\r |
4f265db7 |
367 | {\r |
368 | unsigned char regs[8];\r |
4ff2d527 |
369 | unsigned int addr; // .08: played sample address\r |
4f265db7 |
370 | int pad;\r |
371 | } ch[8];\r |
372 | };\r |
373 | \r |
c459aefd |
374 | struct mcd_misc\r |
375 | {\r |
376 | unsigned short hint_vector;\r |
377 | unsigned char busreq;\r |
51a902ae |
378 | unsigned char s68k_pend_ints;\r |
ef090115 |
379 | unsigned int state_flags; // 04: emu state: reset_pending\r |
51a902ae |
380 | unsigned int counter75hz;\r |
c9e1affc |
381 | unsigned int pad0;\r |
4ff2d527 |
382 | int timer_int3; // 10\r |
4f265db7 |
383 | unsigned int timer_stopwatch;\r |
6cadc2da |
384 | unsigned char bcram_reg; // 18: battery-backed RAM cart register\r |
385 | unsigned char pad2;\r |
386 | unsigned short pad3;\r |
387 | int pad[9];\r |
c459aefd |
388 | };\r |
389 | \r |
cc68a136 |
390 | typedef struct\r |
391 | {\r |
4ff2d527 |
392 | unsigned char bios[0x20000]; // 000000: 128K\r |
393 | union { // 020000: 512K\r |
fa1e5e29 |
394 | unsigned char prg_ram[0x80000];\r |
cc68a136 |
395 | unsigned char prg_ram_b[4][0x20000];\r |
396 | };\r |
4ff2d527 |
397 | union { // 0a0000: 256K\r |
fa1e5e29 |
398 | struct {\r |
399 | unsigned char word_ram2M[0x40000];\r |
dca310c4 |
400 | unsigned char unused0[0x20000];\r |
fa1e5e29 |
401 | };\r |
402 | struct {\r |
dca310c4 |
403 | unsigned char unused1[0x20000];\r |
fa1e5e29 |
404 | unsigned char word_ram1M[2][0x20000];\r |
405 | };\r |
406 | };\r |
4ff2d527 |
407 | union { // 100000: 64K\r |
fa1e5e29 |
408 | unsigned char pcm_ram[0x10000];\r |
4f265db7 |
409 | unsigned char pcm_ram_b[0x10][0x1000];\r |
410 | };\r |
4ff2d527 |
411 | unsigned char s68k_regs[0x200]; // 110000: GA, not CPU regs\r |
412 | unsigned char bram[0x2000]; // 110200: 8K\r |
413 | struct mcd_misc m; // 112200: misc\r |
414 | struct mcd_pcm pcm; // 112240:\r |
75736070 |
415 | _scd_toc TOC; // not to be saved\r |
cc68a136 |
416 | CDD cdd;\r |
417 | CDC cdc;\r |
418 | _scd scd;\r |
d1df8786 |
419 | Rot_Comp rot_comp;\r |
cc68a136 |
420 | } mcd_state;\r |
421 | \r |
be2c4208 |
422 | // XXX: this will need to be reworked for cart+cd support.\r |
cc68a136 |
423 | #define Pico_mcd ((mcd_state *)Pico.rom)\r |
424 | \r |
be2c4208 |
425 | // 32X\r |
acd35d4c |
426 | #define P32XS_FM (1<<15)\r |
83ff19ec |
427 | #define P32XS_REN (1<< 7)\r |
428 | #define P32XS_nRES (1<< 1)\r |
429 | #define P32XS_ADEN (1<< 0)\r |
acd35d4c |
430 | #define P32XS2_ADEN (1<< 9)\r |
5e128c6d |
431 | #define P32XS_FULL (1<< 7) // DREQ FIFO full\r |
4ea707e1 |
432 | #define P32XS_68S (1<< 2)\r |
97d3f47f |
433 | #define P32XS_DMA (1<< 1)\r |
4ea707e1 |
434 | #define P32XS_RV (1<< 0)\r |
acd35d4c |
435 | \r |
5e128c6d |
436 | #define P32XV_nPAL (1<<15) // VDP\r |
acd35d4c |
437 | #define P32XV_PRI (1<< 7)\r |
4ea707e1 |
438 | #define P32XV_Mx (3<< 0) // display mode mask\r |
974fdb5b |
439 | \r |
acd35d4c |
440 | #define P32XV_VBLK (1<<15)\r |
441 | #define P32XV_HBLK (1<<14)\r |
442 | #define P32XV_PEN (1<<13)\r |
443 | #define P32XV_nFEN (1<< 1)\r |
444 | #define P32XV_FS (1<< 0)\r |
974fdb5b |
445 | \r |
db1d3564 |
446 | #define P32XP_FULL (1<<15) // PWM\r |
447 | #define P32XP_EMPTY (1<<14)\r |
448 | \r |
4ea707e1 |
449 | #define P32XF_68KPOLL (1 << 0)\r |
450 | #define P32XF_MSH2POLL (1 << 1)\r |
451 | #define P32XF_SSH2POLL (1 << 2)\r |
452 | #define P32XF_68KVPOLL (1 << 3)\r |
453 | #define P32XF_MSH2VPOLL (1 << 4)\r |
454 | #define P32XF_SSH2VPOLL (1 << 5)\r |
455 | \r |
456 | #define P32XI_VRES (1 << 14/2) // IRL/2\r |
457 | #define P32XI_VINT (1 << 12/2)\r |
458 | #define P32XI_HINT (1 << 10/2)\r |
459 | #define P32XI_CMD (1 << 8/2)\r |
460 | #define P32XI_PWM (1 << 6/2)\r |
461 | \r |
1d7a28a7 |
462 | // peripheral reg access\r |
463 | #define PREG8(regs,offs) ((unsigned char *)regs)[offs ^ 3]\r |
464 | \r |
4ea707e1 |
465 | // real one is 4*2, but we use more because we don't lockstep\r |
466 | #define DMAC_FIFO_LEN (4*4)\r |
db1d3564 |
467 | #define PWM_BUFF_LEN 1024 // in one channel samples\r |
266c6afa |
468 | \r |
f4bb5d6b |
469 | #define SH2_DRCBLK_RAM_SHIFT 1\r |
470 | #define SH2_DRCBLK_DA_SHIFT 1\r |
471 | \r |
e05b81fc |
472 | #define SH2_WRITE_SHIFT 25\r |
473 | \r |
be2c4208 |
474 | struct Pico32x\r |
475 | {\r |
476 | unsigned short regs[0x20];\r |
477 | unsigned short vdp_regs[0x10];\r |
87accdf7 |
478 | unsigned short sh2_regs[3];\r |
be2c4208 |
479 | unsigned char pending_fb;\r |
974fdb5b |
480 | unsigned char dirty_pal;\r |
266c6afa |
481 | unsigned int emu_flags;\r |
4ea707e1 |
482 | unsigned char sh2irq_mask[2];\r |
483 | unsigned char sh2irqi[2]; // individual\r |
484 | unsigned int sh2irqs; // common irqs\r |
485 | unsigned short dmac_fifo[DMAC_FIFO_LEN];\r |
486 | unsigned int dmac_ptr;\r |
db1d3564 |
487 | unsigned int pwm_irq_sample_cnt;\r |
974fdb5b |
488 | };\r |
489 | \r |
490 | struct Pico32xMem\r |
491 | {\r |
492 | unsigned char sdram[0x40000];\r |
f4bb5d6b |
493 | #ifdef DRC_SH2\r |
494 | unsigned short drcblk_ram[1 << (18 - SH2_DRCBLK_RAM_SHIFT)];\r |
495 | #endif\r |
b78efee2 |
496 | unsigned short dram[2][0x20000/2]; // AKA fb\r |
497 | unsigned char m68k_rom[0x10000]; // 0x100; using M68K_BANK_SIZE\r |
498 | unsigned char data_array[2][0x1000]; // cache in SH2s (can be used as RAM)\r |
f4bb5d6b |
499 | #ifdef DRC_SH2\r |
500 | unsigned short drcblk_da[2][1 << (12 - SH2_DRCBLK_DA_SHIFT)];\r |
501 | #endif\r |
acd35d4c |
502 | unsigned char sh2_rom_m[0x800];\r |
503 | unsigned char sh2_rom_s[0x400];\r |
974fdb5b |
504 | unsigned short pal[0x100];\r |
5e128c6d |
505 | unsigned short pal_native[0x100]; // converted to native (for renderer)\r |
4ea707e1 |
506 | unsigned int sh2_peri_regs[2][0x200/4]; // periphereal regs of SH2s\r |
db1d3564 |
507 | signed short pwm[2*PWM_BUFF_LEN]; // PWM buffer for current frame\r |
be2c4208 |
508 | };\r |
d49b10c2 |
509 | \r |
c8d1e9b6 |
510 | // area.c\r |
2aa27095 |
511 | PICO_INTERNAL void PicoAreaPackCpu(unsigned char *cpu, int is_sub);\r |
512 | PICO_INTERNAL void PicoAreaUnpackCpu(unsigned char *cpu, int is_sub);\r |
fad24893 |
513 | extern void (*PicoLoadStateHook)(void);\r |
51a902ae |
514 | \r |
c8d1e9b6 |
515 | // cd/area.c\r |
eff55556 |
516 | PICO_INTERNAL int PicoCdSaveState(void *file);\r |
517 | PICO_INTERNAL int PicoCdLoadState(void *file);\r |
cc68a136 |
518 | \r |
945c2fdc |
519 | typedef struct {\r |
520 | int chunk;\r |
521 | int size;\r |
522 | void *ptr;\r |
523 | } carthw_state_chunk;\r |
524 | extern carthw_state_chunk *carthw_chunks;\r |
525 | #define CHUNK_CARTHW 64\r |
526 | \r |
bcc9eda0 |
527 | // area.c\r |
528 | typedef size_t (arearw)(void *p, size_t _size, size_t _n, void *file);\r |
529 | typedef size_t (areaeof)(void *file);\r |
530 | typedef int (areaseek)(void *file, long offset, int whence);\r |
531 | typedef int (areaclose)(void *file);\r |
532 | extern arearw *areaRead; // external read and write function pointers for\r |
533 | extern arearw *areaWrite; // gzip save state ability\r |
534 | extern areaeof *areaEof;\r |
535 | extern areaseek *areaSeek;\r |
536 | extern areaclose *areaClose;\r |
537 | \r |
c8d1e9b6 |
538 | // cart.c\r |
83ff19ec |
539 | void Byteswap(void *dst, const void *src, int len);\r |
45f2f245 |
540 | extern void (*PicoCartMemSetup)(void);\r |
e807ac75 |
541 | extern void (*PicoCartUnloadHook)(void);\r |
1dceadae |
542 | \r |
c8d1e9b6 |
543 | // debug.c\r |
b5e5172d |
544 | int CM_compareRun(int cyc, int is_sub);\r |
03e4f2a3 |
545 | \r |
c8d1e9b6 |
546 | // draw.c\r |
eff55556 |
547 | PICO_INTERNAL void PicoFrameStart(void);\r |
b6d7ac70 |
548 | void PicoDrawSync(int to, int blank_last_line);\r |
200772b7 |
549 | void BackFill(int reg7, int sh);\r |
974fdb5b |
550 | void FinalizeLineRGB555(int sh, int line);\r |
b6d7ac70 |
551 | extern int DrawScanline;\r |
f579f7b8 |
552 | #define MAX_LINE_SPRITES 29\r |
553 | extern unsigned char HighLnSpr[240][3 + MAX_LINE_SPRITES];\r |
cc68a136 |
554 | \r |
c8d1e9b6 |
555 | // draw2.c\r |
eff55556 |
556 | PICO_INTERNAL void PicoFrameFull();\r |
cc68a136 |
557 | \r |
200772b7 |
558 | // mode4.c\r |
559 | void PicoFrameStartMode4(void);\r |
560 | void PicoLineMode4(int line);\r |
561 | void PicoDoHighPal555M4(void);\r |
87b0845f |
562 | void PicoDrawSetColorFormatMode4(int which);\r |
200772b7 |
563 | \r |
c8d1e9b6 |
564 | // memory.c\r |
eff55556 |
565 | PICO_INTERNAL void PicoMemSetup(void);\r |
af37bca8 |
566 | unsigned int PicoRead8_io(unsigned int a);\r |
567 | unsigned int PicoRead16_io(unsigned int a);\r |
568 | void PicoWrite8_io(unsigned int a, unsigned int d);\r |
569 | void PicoWrite16_io(unsigned int a, unsigned int d);\r |
570 | \r |
571 | // pico/memory.c\r |
572 | PICO_INTERNAL void PicoMemSetupPico(void);\r |
cc68a136 |
573 | \r |
c8d1e9b6 |
574 | // cd/memory.c\r |
eff55556 |
575 | PICO_INTERNAL void PicoMemSetupCD(void);\r |
0ace9b9a |
576 | void PicoMemStateLoaded(void);\r |
cc68a136 |
577 | \r |
c8d1e9b6 |
578 | // pico.c\r |
cc68a136 |
579 | extern struct Pico Pico;\r |
580 | extern struct PicoSRAM SRam;\r |
5f9a0d16 |
581 | extern int PicoPadInt[2];\r |
cc68a136 |
582 | extern int emustatus;\r |
5e128c6d |
583 | extern int scanlines_total;\r |
f8ef8ff7 |
584 | extern void (*PicoResetHook)(void);\r |
b0677887 |
585 | extern void (*PicoLineHook)(void);\r |
1e6b5e39 |
586 | PICO_INTERNAL int CheckDMA(void);\r |
587 | PICO_INTERNAL void PicoDetectRegion(void);\r |
4b9c5888 |
588 | PICO_INTERNAL void PicoSyncZ80(int m68k_cycles_done);\r |
cc68a136 |
589 | \r |
c8d1e9b6 |
590 | // cd/pico.c\r |
2aa27095 |
591 | PICO_INTERNAL void PicoInitMCD(void);\r |
e5f426aa |
592 | PICO_INTERNAL void PicoExitMCD(void);\r |
1cb1584b |
593 | PICO_INTERNAL void PicoPowerMCD(void);\r |
2aa27095 |
594 | PICO_INTERNAL int PicoResetMCD(void);\r |
595 | PICO_INTERNAL void PicoFrameMCD(void);\r |
cc68a136 |
596 | \r |
c8d1e9b6 |
597 | // pico/pico.c\r |
2aa27095 |
598 | PICO_INTERNAL void PicoInitPico(void);\r |
ed367a3f |
599 | PICO_INTERNAL void PicoReratePico(void);\r |
9037e45d |
600 | \r |
c8d1e9b6 |
601 | // pico/xpcm.c\r |
ef4eb506 |
602 | PICO_INTERNAL void PicoPicoPCMUpdate(short *buffer, int length, int stereo);\r |
603 | PICO_INTERNAL void PicoPicoPCMReset(void);\r |
213c16ad |
604 | PICO_INTERNAL void PicoPicoPCMRerate(int xpcm_rate);\r |
ef4eb506 |
605 | \r |
c8d1e9b6 |
606 | // sek.c\r |
2aa27095 |
607 | PICO_INTERNAL void SekInit(void);\r |
608 | PICO_INTERNAL int SekReset(void);\r |
3aa1e148 |
609 | PICO_INTERNAL void SekState(int *data);\r |
eff55556 |
610 | PICO_INTERNAL void SekSetRealTAS(int use_real);\r |
5f9a0d16 |
611 | void SekStepM68k(void);\r |
053fd9b4 |
612 | void SekInitIdleDet(void);\r |
613 | void SekFinishIdleDet(void);\r |
cc68a136 |
614 | \r |
c8d1e9b6 |
615 | // cd/sek.c\r |
2aa27095 |
616 | PICO_INTERNAL void SekInitS68k(void);\r |
617 | PICO_INTERNAL int SekResetS68k(void);\r |
618 | PICO_INTERNAL int SekInterruptS68k(int irq);\r |
cc68a136 |
619 | \r |
7a93adeb |
620 | // sound/sound.c\r |
c9e1affc |
621 | PICO_INTERNAL void cdda_start_play();\r |
622 | extern short cdda_out_buffer[2*1152];\r |
7a93adeb |
623 | extern int PsndLen_exc_cnt;\r |
624 | extern int PsndLen_exc_add;\r |
48dc74f2 |
625 | extern int timer_a_next_oflow, timer_a_step; // in z80 cycles\r |
626 | extern int timer_b_next_oflow, timer_b_step;\r |
43e6eaad |
627 | \r |
628 | void ym2612_sync_timers(int z80_cycles, int mode_old, int mode_new);\r |
d2721b08 |
629 | void ym2612_pack_state(void);\r |
453d2a6e |
630 | void ym2612_unpack_state(void);\r |
4b9c5888 |
631 | \r |
e53704e6 |
632 | #define TIMER_NO_OFLOW 0x70000000\r |
45a1ef71 |
633 | // tA = 72 * (1024 - NA) / M\r |
634 | #define TIMER_A_TICK_ZCYCLES 17203\r |
635 | // tB = 1152 * (256 - NA) / M\r |
636 | #define TIMER_B_TICK_ZCYCLES 262800 // 275251 broken, see Dai Makaimura\r |
e53704e6 |
637 | \r |
4b9c5888 |
638 | #define timers_cycle() \\r |
e53704e6 |
639 | if (timer_a_next_oflow > 0 && timer_a_next_oflow < TIMER_NO_OFLOW) \\r |
43e6eaad |
640 | timer_a_next_oflow -= Pico.m.pal ? 70938*256 : 59659*256; \\r |
e53704e6 |
641 | if (timer_b_next_oflow > 0 && timer_b_next_oflow < TIMER_NO_OFLOW) \\r |
43e6eaad |
642 | timer_b_next_oflow -= Pico.m.pal ? 70938*256 : 59659*256; \\r |
643 | ym2612_sync_timers(0, ym2612.OPN.ST.mode, ym2612.OPN.ST.mode);\r |
4b9c5888 |
644 | \r |
645 | #define timers_reset() \\r |
e53704e6 |
646 | timer_a_next_oflow = timer_b_next_oflow = TIMER_NO_OFLOW; \\r |
48dc74f2 |
647 | timer_a_step = TIMER_A_TICK_ZCYCLES * 1024; \\r |
648 | timer_b_step = TIMER_B_TICK_ZCYCLES * 256;\r |
43e6eaad |
649 | \r |
7a93adeb |
650 | \r |
c8d1e9b6 |
651 | // videoport.c\r |
eff55556 |
652 | PICO_INTERNAL_ASM void PicoVideoWrite(unsigned int a,unsigned short d);\r |
653 | PICO_INTERNAL_ASM unsigned int PicoVideoRead(unsigned int a);\r |
9761a7d0 |
654 | PICO_INTERNAL_ASM unsigned int PicoVideoRead8(unsigned int a);\r |
5de27868 |
655 | extern int (*PicoDmaHook)(unsigned int source, int len, unsigned short **srcp, unsigned short **limitp);\r |
cc68a136 |
656 | \r |
c8d1e9b6 |
657 | // misc.c\r |
eff55556 |
658 | PICO_INTERNAL_ASM void memcpy16(unsigned short *dest, unsigned short *src, int count);\r |
659 | PICO_INTERNAL_ASM void memcpy16bswap(unsigned short *dest, void *src, int count);\r |
660 | PICO_INTERNAL_ASM void memcpy32(int *dest, int *src, int count); // 32bit word count\r |
661 | PICO_INTERNAL_ASM void memset32(int *dest, int c, int count);\r |
cc68a136 |
662 | \r |
45f2f245 |
663 | // eeprom.c\r |
664 | void EEPROM_write8(unsigned int a, unsigned int d);\r |
665 | void EEPROM_write16(unsigned int d);\r |
666 | unsigned int EEPROM_read(void);\r |
667 | \r |
c8d1e9b6 |
668 | // z80 functionality wrappers\r |
669 | PICO_INTERNAL void z80_init(void);\r |
670 | PICO_INTERNAL void z80_pack(unsigned char *data);\r |
671 | PICO_INTERNAL void z80_unpack(unsigned char *data);\r |
672 | PICO_INTERNAL void z80_reset(void);\r |
673 | PICO_INTERNAL void z80_exit(void);\r |
c8d1e9b6 |
674 | \r |
675 | // cd/misc.c\r |
eff55556 |
676 | PICO_INTERNAL_ASM void wram_2M_to_1M(unsigned char *m);\r |
677 | PICO_INTERNAL_ASM void wram_1M_to_2M(unsigned char *m);\r |
678 | \r |
679 | // cd/buffering.c\r |
680 | PICO_INTERNAL void PicoCDBufferRead(void *dest, int lba);\r |
681 | \r |
682 | // sound/sound.c\r |
9d917eea |
683 | PICO_INTERNAL void PsndReset(void);\r |
4b9c5888 |
684 | PICO_INTERNAL void PsndDoDAC(int line_to);\r |
9d917eea |
685 | PICO_INTERNAL void PsndClear(void);\r |
7b3f44c6 |
686 | PICO_INTERNAL void PsndGetSamples(int y);\r |
2ec9bec5 |
687 | PICO_INTERNAL void PsndGetSamplesMS(void);\r |
4b9c5888 |
688 | extern int PsndDacLine;\r |
cc68a136 |
689 | \r |
3e49ffd0 |
690 | // sms.c\r |
691 | void PicoPowerMS(void);\r |
2ec9bec5 |
692 | void PicoResetMS(void);\r |
3e49ffd0 |
693 | void PicoMemSetupMS(void);\r |
694 | void PicoFrameMS(void);\r |
87b0845f |
695 | void PicoFrameDrawOnlyMS(void);\r |
3e49ffd0 |
696 | \r |
be2c4208 |
697 | // 32x/32x.c\r |
698 | extern struct Pico32x Pico32x;\r |
699 | void Pico32xInit(void);\r |
974fdb5b |
700 | void PicoPower32x(void);\r |
be2c4208 |
701 | void PicoReset32x(void);\r |
974fdb5b |
702 | void Pico32xStartup(void);\r |
5e49c3a8 |
703 | void PicoUnload32x(void);\r |
974fdb5b |
704 | void PicoFrame32x(void);\r |
4ea707e1 |
705 | void p32x_update_irls(void);\r |
83ff19ec |
706 | void p32x_reset_sh2s(void);\r |
be2c4208 |
707 | \r |
708 | // 32x/memory.c\r |
974fdb5b |
709 | struct Pico32xMem *Pico32xMem;\r |
be2c4208 |
710 | unsigned int PicoRead8_32x(unsigned int a);\r |
711 | unsigned int PicoRead16_32x(unsigned int a);\r |
712 | void PicoWrite8_32x(unsigned int a, unsigned int d);\r |
713 | void PicoWrite16_32x(unsigned int a, unsigned int d);\r |
714 | void PicoMemSetup32x(void);\r |
974fdb5b |
715 | void Pico32xSwapDRAM(int b);\r |
87accdf7 |
716 | void p32x_poll_event(int cpu_mask, int is_vdp);\r |
974fdb5b |
717 | \r |
718 | // 32x/draw.c\r |
719 | void FinalizeLine32xRGB555(int sh, int line);\r |
be2c4208 |
720 | \r |
db1d3564 |
721 | // 32x/pwm.c\r |
722 | unsigned int p32x_pwm_read16(unsigned int a);\r |
723 | void p32x_pwm_write16(unsigned int a, unsigned int d);\r |
db1d3564 |
724 | void p32x_pwm_update(int *buf32, int length, int stereo);\r |
1d7a28a7 |
725 | void p32x_timers_do(int new_line);\r |
726 | void p32x_timers_recalc(void);\r |
db1d3564 |
727 | extern int pwm_frame_smp_cnt;\r |
728 | \r |
45f2f245 |
729 | /* avoid dependency on newer glibc */\r |
730 | static __inline int isspace_(int c)\r |
731 | {\r |
732 | return (0x09 <= c && c <= 0x0d) || c == ' ';\r |
733 | }\r |
734 | \r |
f4bb5d6b |
735 | #ifndef ARRAY_SIZE\r |
736 | #define ARRAY_SIZE(x) (sizeof(x) / sizeof(x[0]))\r |
737 | #endif\r |
738 | \r |
b8cbd802 |
739 | // emulation event logging\r |
740 | #ifndef EL_LOGMASK\r |
741 | #define EL_LOGMASK 0\r |
742 | #endif\r |
743 | \r |
017512f2 |
744 | #define EL_HVCNT 0x00000001 /* hv counter reads */\r |
745 | #define EL_SR 0x00000002 /* SR reads */\r |
746 | #define EL_INTS 0x00000004 /* ints and acks */\r |
43e6eaad |
747 | #define EL_YMTIMER 0x00000008 /* ym2612 timer stuff */\r |
017512f2 |
748 | #define EL_INTSW 0x00000010 /* log irq switching on/off */\r |
749 | #define EL_ASVDP 0x00000020 /* VDP accesses during active scan */\r |
750 | #define EL_VDPDMA 0x00000040 /* VDP DMA transfers and their timing */\r |
751 | #define EL_BUSREQ 0x00000080 /* z80 busreq r/w or reset w */\r |
752 | #define EL_Z80BNK 0x00000100 /* z80 i/o through bank area */\r |
753 | #define EL_SRAMIO 0x00000200 /* sram i/o */\r |
754 | #define EL_EEPROM 0x00000400 /* eeprom debug */\r |
755 | #define EL_UIO 0x00000800 /* unmapped i/o */\r |
756 | #define EL_IO 0x00001000 /* all i/o */\r |
757 | #define EL_CDPOLL 0x00002000 /* MCD: log poll detection */\r |
758 | #define EL_SVP 0x00004000 /* SVP stuff */\r |
fa22af4c |
759 | #define EL_PICOHW 0x00008000 /* Pico stuff */\r |
053fd9b4 |
760 | #define EL_IDLE 0x00010000 /* idle loop det. */\r |
af37bca8 |
761 | #define EL_CDREGS 0x00020000 /* MCD: register access */\r |
762 | #define EL_CDREG3 0x00040000 /* MCD: register 3 only */\r |
be2c4208 |
763 | #define EL_32X 0x00080000\r |
1b3f5844 |
764 | #define EL_PWM 0x00100000 /* 32X PWM stuff (LOTS of output) */\r |
017512f2 |
765 | \r |
766 | #define EL_STATUS 0x40000000 /* status messages */\r |
767 | #define EL_ANOMALY 0x80000000 /* some unexpected conditions (during emulation) */\r |
b8cbd802 |
768 | \r |
769 | #if EL_LOGMASK\r |
7d0143a2 |
770 | extern void lprintf(const char *fmt, ...);\r |
b8cbd802 |
771 | #define elprintf(w,f,...) \\r |
772 | { \\r |
773 | if ((w) & EL_LOGMASK) \\r |
7d0143a2 |
774 | lprintf("%05i:%03i: " f "\n",Pico.m.frame_count,Pico.m.scanline,##__VA_ARGS__); \\r |
b8cbd802 |
775 | }\r |
dca310c4 |
776 | #elif defined(_MSC_VER)\r |
777 | #define elprintf\r |
b8cbd802 |
778 | #else\r |
779 | #define elprintf(w,f,...)\r |
780 | #endif\r |
781 | \r |
f6c49d38 |
782 | // profiling\r |
783 | #ifdef PPROF\r |
784 | #include <platform/linux/pprof.h>\r |
785 | #else\r |
786 | #define pprof_init()\r |
787 | #define pprof_finish()\r |
788 | #define pprof_start(x)\r |
789 | #define pprof_end(...)\r |
790 | #define pprof_end_sub(...)\r |
791 | #endif\r |
792 | \r |
793 | // misc\r |
dca310c4 |
794 | #ifdef _MSC_VER\r |
795 | #define cdprintf\r |
796 | #else\r |
797 | #define cdprintf(x...)\r |
798 | #endif\r |
799 | \r |
553c3eaa |
800 | #ifdef __i386__\r |
801 | #define REGPARM(x) __attribute__((regparm(x)))\r |
c8d1e9b6 |
802 | #else\r |
553c3eaa |
803 | #define REGPARM(x)\r |
c8d1e9b6 |
804 | #endif\r |
805 | \r |
5e89f0f5 |
806 | #ifdef __GNUC__\r |
807 | #define NOINLINE __attribute__((noinline))\r |
808 | #else\r |
809 | #define NOINLINE\r |
810 | #endif\r |
811 | \r |
f8af9634 |
812 | #ifdef __cplusplus\r |
813 | } // End of extern "C"\r |
814 | #endif\r |
815 | \r |
eff55556 |
816 | #endif // PICO_INTERNAL_INCLUDED\r |
817 | \r |