drc: inv: fix ram ofset and mirror handling
[pcsx_rearmed.git] / libpcsxcore / new_dynarec / new_dynarec.c
CommitLineData
57871462 1/* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
2 * Mupen64plus - new_dynarec.c *
20d507ba 3 * Copyright (C) 2009-2011 Ari64 *
57871462 4 * *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
9 * *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
14 * *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. *
19 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */
20
21#include <stdlib.h>
22#include <stdint.h> //include for uint64_t
23#include <assert.h>
4600ba03 24#include <sys/mman.h>
57871462 25
3d624f89 26#include "emu_if.h" //emulator interface
57871462 27
4600ba03 28//#define DISASM
29//#define assem_debug printf
30//#define inv_debug printf
31#define assem_debug(...)
32#define inv_debug(...)
57871462 33
34#ifdef __i386__
35#include "assem_x86.h"
36#endif
37#ifdef __x86_64__
38#include "assem_x64.h"
39#endif
40#ifdef __arm__
41#include "assem_arm.h"
42#endif
43
44#define MAXBLOCK 4096
45#define MAX_OUTPUT_BLOCK_SIZE 262144
2573466a 46
57871462 47struct regstat
48{
49 signed char regmap_entry[HOST_REGS];
50 signed char regmap[HOST_REGS];
51 uint64_t was32;
52 uint64_t is32;
53 uint64_t wasdirty;
54 uint64_t dirty;
55 uint64_t u;
56 uint64_t uu;
57 u_int wasconst;
58 u_int isconst;
8575a877 59 u_int loadedconst; // host regs that have constants loaded
60 u_int waswritten; // MIPS regs that were used as store base before
57871462 61};
62
63struct ll_entry
64{
65 u_int vaddr;
66 u_int reg32;
67 void *addr;
68 struct ll_entry *next;
69};
70
71 u_int start;
72 u_int *source;
73 u_int pagelimit;
74 char insn[MAXBLOCK][10];
75 u_char itype[MAXBLOCK];
76 u_char opcode[MAXBLOCK];
77 u_char opcode2[MAXBLOCK];
78 u_char bt[MAXBLOCK];
79 u_char rs1[MAXBLOCK];
80 u_char rs2[MAXBLOCK];
81 u_char rt1[MAXBLOCK];
82 u_char rt2[MAXBLOCK];
83 u_char us1[MAXBLOCK];
84 u_char us2[MAXBLOCK];
85 u_char dep1[MAXBLOCK];
86 u_char dep2[MAXBLOCK];
87 u_char lt1[MAXBLOCK];
bedfea38 88 static uint64_t gte_rs[MAXBLOCK]; // gte: 32 data and 32 ctl regs
89 static uint64_t gte_rt[MAXBLOCK];
90 static uint64_t gte_unneeded[MAXBLOCK];
ffb0b9e0 91 static u_int smrv[32]; // speculated MIPS register values
92 static u_int smrv_strong; // mask or regs that are likely to have correct values
93 static u_int smrv_weak; // same, but somewhat less likely
94 static u_int smrv_strong_next; // same, but after current insn executes
95 static u_int smrv_weak_next;
57871462 96 int imm[MAXBLOCK];
97 u_int ba[MAXBLOCK];
98 char likely[MAXBLOCK];
99 char is_ds[MAXBLOCK];
e1190b87 100 char ooo[MAXBLOCK];
57871462 101 uint64_t unneeded_reg[MAXBLOCK];
102 uint64_t unneeded_reg_upper[MAXBLOCK];
103 uint64_t branch_unneeded_reg[MAXBLOCK];
104 uint64_t branch_unneeded_reg_upper[MAXBLOCK];
105 uint64_t p32[MAXBLOCK];
106 uint64_t pr32[MAXBLOCK];
107 signed char regmap_pre[MAXBLOCK][HOST_REGS];
956f3129 108 static uint64_t current_constmap[HOST_REGS];
109 static uint64_t constmap[MAXBLOCK][HOST_REGS];
110 static struct regstat regs[MAXBLOCK];
111 static struct regstat branch_regs[MAXBLOCK];
e1190b87 112 signed char minimum_free_regs[MAXBLOCK];
57871462 113 u_int needed_reg[MAXBLOCK];
114 uint64_t requires_32bit[MAXBLOCK];
115 u_int wont_dirty[MAXBLOCK];
116 u_int will_dirty[MAXBLOCK];
117 int ccadj[MAXBLOCK];
118 int slen;
119 u_int instr_addr[MAXBLOCK];
120 u_int link_addr[MAXBLOCK][3];
121 int linkcount;
122 u_int stubs[MAXBLOCK*3][8];
123 int stubcount;
124 u_int literals[1024][2];
125 int literalcount;
126 int is_delayslot;
127 int cop1_usable;
128 u_char *out;
129 struct ll_entry *jump_in[4096];
130 struct ll_entry *jump_out[4096];
131 struct ll_entry *jump_dirty[4096];
132 u_int hash_table[65536][4] __attribute__((aligned(16)));
133 char shadow[1048576] __attribute__((aligned(16)));
134 void *copy;
135 int expirep;
af4ee1fe 136#ifndef PCSX
57871462 137 u_int using_tlb;
af4ee1fe 138#else
139 static const u_int using_tlb=0;
140#endif
2f546f9a 141 int new_dynarec_did_compile;
0ff8c62c 142 int new_dynarec_hacks;
57871462 143 u_int stop_after_jal;
a327ad27 144#ifndef RAM_FIXED
145 static u_int ram_offset;
146#else
147 static const u_int ram_offset=0;
148#endif
57871462 149 extern u_char restore_candidate[512];
150 extern int cycle_count;
151
152 /* registers that may be allocated */
153 /* 1-31 gpr */
154#define HIREG 32 // hi
155#define LOREG 33 // lo
156#define FSREG 34 // FPU status (FCSR)
157#define CSREG 35 // Coprocessor status
158#define CCREG 36 // Cycle count
159#define INVCP 37 // Pointer to invalid_code
619e5ded 160#define MMREG 38 // Pointer to memory_map
161#define ROREG 39 // ram offset (if rdram!=0x80000000)
162#define TEMPREG 40
163#define FTEMP 40 // FPU temporary register
164#define PTEMP 41 // Prefetch temporary register
165#define TLREG 42 // TLB mapping offset
166#define RHASH 43 // Return address hash
167#define RHTBL 44 // Return address hash table address
168#define RTEMP 45 // JR/JALR address register
169#define MAXREG 45
170#define AGEN1 46 // Address generation temporary register
171#define AGEN2 47 // Address generation temporary register
172#define MGEN1 48 // Maptable address generation temporary register
173#define MGEN2 49 // Maptable address generation temporary register
174#define BTREG 50 // Branch target temporary register
57871462 175
176 /* instruction types */
177#define NOP 0 // No operation
178#define LOAD 1 // Load
179#define STORE 2 // Store
180#define LOADLR 3 // Unaligned load
181#define STORELR 4 // Unaligned store
182#define MOV 5 // Move
183#define ALU 6 // Arithmetic/logic
184#define MULTDIV 7 // Multiply/divide
185#define SHIFT 8 // Shift by register
186#define SHIFTIMM 9// Shift by immediate
187#define IMM16 10 // 16-bit immediate
188#define RJUMP 11 // Unconditional jump to register
189#define UJUMP 12 // Unconditional jump
190#define CJUMP 13 // Conditional branch (BEQ/BNE/BGTZ/BLEZ)
191#define SJUMP 14 // Conditional branch (regimm format)
192#define COP0 15 // Coprocessor 0
193#define COP1 16 // Coprocessor 1
194#define C1LS 17 // Coprocessor 1 load/store
195#define FJUMP 18 // Conditional branch (floating point)
196#define FLOAT 19 // Floating point unit
197#define FCONV 20 // Convert integer to float
198#define FCOMP 21 // Floating point compare (sets FSREG)
199#define SYSCALL 22// SYSCALL
200#define OTHER 23 // Other
201#define SPAN 24 // Branch/delay slot spans 2 pages
202#define NI 25 // Not implemented
7139f3c8 203#define HLECALL 26// PCSX fake opcodes for HLE
b9b61529 204#define COP2 27 // Coprocessor 2 move
205#define C2LS 28 // Coprocessor 2 load/store
206#define C2OP 29 // Coprocessor 2 operation
1e973cb0 207#define INTCALL 30// Call interpreter to handle rare corner cases
57871462 208
209 /* stubs */
210#define CC_STUB 1
211#define FP_STUB 2
212#define LOADB_STUB 3
213#define LOADH_STUB 4
214#define LOADW_STUB 5
215#define LOADD_STUB 6
216#define LOADBU_STUB 7
217#define LOADHU_STUB 8
218#define STOREB_STUB 9
219#define STOREH_STUB 10
220#define STOREW_STUB 11
221#define STORED_STUB 12
222#define STORELR_STUB 13
223#define INVCODE_STUB 14
224
225 /* branch codes */
226#define TAKEN 1
227#define NOTTAKEN 2
228#define NULLDS 3
229
230// asm linkage
231int new_recompile_block(int addr);
232void *get_addr_ht(u_int vaddr);
233void invalidate_block(u_int block);
234void invalidate_addr(u_int addr);
235void remove_hash(int vaddr);
236void jump_vaddr();
237void dyna_linker();
238void dyna_linker_ds();
239void verify_code();
240void verify_code_vm();
241void verify_code_ds();
242void cc_interrupt();
243void fp_exception();
244void fp_exception_ds();
245void jump_syscall();
7139f3c8 246void jump_syscall_hle();
57871462 247void jump_eret();
7139f3c8 248void jump_hlecall();
1e973cb0 249void jump_intcall();
7139f3c8 250void new_dyna_leave();
57871462 251
252// TLB
253void TLBWI_new();
254void TLBWR_new();
255void read_nomem_new();
256void read_nomemb_new();
257void read_nomemh_new();
258void read_nomemd_new();
259void write_nomem_new();
260void write_nomemb_new();
261void write_nomemh_new();
262void write_nomemd_new();
263void write_rdram_new();
264void write_rdramb_new();
265void write_rdramh_new();
266void write_rdramd_new();
267extern u_int memory_map[1048576];
268
269// Needed by assembler
270void wb_register(signed char r,signed char regmap[],uint64_t dirty,uint64_t is32);
271void wb_dirtys(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty);
272void wb_needed_dirtys(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr);
273void load_all_regs(signed char i_regmap[]);
274void load_needed_regs(signed char i_regmap[],signed char next_regmap[]);
275void load_regs_entry(int t);
276void load_all_consts(signed char regmap[],int is32,u_int dirty,int i);
277
278int tracedebug=0;
279
280//#define DEBUG_CYCLE_COUNT 1
281
4e9dcd7f 282int cycle_multiplier; // 100 for 1.0
283
284static int CLOCK_ADJUST(int x)
285{
286 int s=(x>>31)|1;
287 return (x * cycle_multiplier + s * 50) / 100;
288}
289
94d23bb9 290static void tlb_hacks()
57871462 291{
94d23bb9 292#ifndef DISABLE_TLB
57871462 293 // Goldeneye hack
294 if (strncmp((char *) ROM_HEADER->nom, "GOLDENEYE",9) == 0)
295 {
296 u_int addr;
297 int n;
298 switch (ROM_HEADER->Country_code&0xFF)
299 {
300 case 0x45: // U
301 addr=0x34b30;
302 break;
303 case 0x4A: // J
304 addr=0x34b70;
305 break;
306 case 0x50: // E
307 addr=0x329f0;
308 break;
309 default:
310 // Unknown country code
311 addr=0;
312 break;
313 }
314 u_int rom_addr=(u_int)rom;
315 #ifdef ROM_COPY
316 // Since memory_map is 32-bit, on 64-bit systems the rom needs to be
317 // in the lower 4G of memory to use this hack. Copy it if necessary.
318 if((void *)rom>(void *)0xffffffff) {
319 munmap(ROM_COPY, 67108864);
320 if(mmap(ROM_COPY, 12582912,
321 PROT_READ | PROT_WRITE,
322 MAP_FIXED | MAP_PRIVATE | MAP_ANONYMOUS,
323 -1, 0) <= 0) {printf("mmap() failed\n");}
324 memcpy(ROM_COPY,rom,12582912);
325 rom_addr=(u_int)ROM_COPY;
326 }
327 #endif
328 if(addr) {
329 for(n=0x7F000;n<0x80000;n++) {
330 memory_map[n]=(((u_int)(rom_addr+addr-0x7F000000))>>2)|0x40000000;
331 }
332 }
333 }
94d23bb9 334#endif
57871462 335}
336
94d23bb9 337static u_int get_page(u_int vaddr)
57871462 338{
0ce47d46 339#ifndef PCSX
57871462 340 u_int page=(vaddr^0x80000000)>>12;
0ce47d46 341#else
342 u_int page=vaddr&~0xe0000000;
343 if (page < 0x1000000)
344 page &= ~0x0e00000; // RAM mirrors
345 page>>=12;
346#endif
94d23bb9 347#ifndef DISABLE_TLB
57871462 348 if(page>262143&&tlb_LUT_r[vaddr>>12]) page=(tlb_LUT_r[vaddr>>12]^0x80000000)>>12;
94d23bb9 349#endif
57871462 350 if(page>2048) page=2048+(page&2047);
94d23bb9 351 return page;
352}
353
d25604ca 354#ifndef PCSX
94d23bb9 355static u_int get_vpage(u_int vaddr)
356{
357 u_int vpage=(vaddr^0x80000000)>>12;
358#ifndef DISABLE_TLB
57871462 359 if(vpage>262143&&tlb_LUT_r[vaddr>>12]) vpage&=2047; // jump_dirty uses a hash of the virtual address instead
94d23bb9 360#endif
57871462 361 if(vpage>2048) vpage=2048+(vpage&2047);
94d23bb9 362 return vpage;
363}
d25604ca 364#else
365// no virtual mem in PCSX
366static u_int get_vpage(u_int vaddr)
367{
368 return get_page(vaddr);
369}
370#endif
94d23bb9 371
372// Get address from virtual address
373// This is called from the recompiled JR/JALR instructions
374void *get_addr(u_int vaddr)
375{
376 u_int page=get_page(vaddr);
377 u_int vpage=get_vpage(vaddr);
57871462 378 struct ll_entry *head;
379 //printf("TRACE: count=%d next=%d (get_addr %x,page %d)\n",Count,next_interupt,vaddr,page);
380 head=jump_in[page];
381 while(head!=NULL) {
382 if(head->vaddr==vaddr&&head->reg32==0) {
383 //printf("TRACE: count=%d next=%d (get_addr match %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr);
384 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
385 ht_bin[3]=ht_bin[1];
386 ht_bin[2]=ht_bin[0];
387 ht_bin[1]=(int)head->addr;
388 ht_bin[0]=vaddr;
389 return head->addr;
390 }
391 head=head->next;
392 }
393 head=jump_dirty[vpage];
394 while(head!=NULL) {
395 if(head->vaddr==vaddr&&head->reg32==0) {
396 //printf("TRACE: count=%d next=%d (get_addr match dirty %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr);
397 // Don't restore blocks which are about to expire from the cache
398 if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
399 if(verify_dirty(head->addr)) {
400 //printf("restore candidate: %x (%d) d=%d\n",vaddr,page,invalid_code[vaddr>>12]);
401 invalid_code[vaddr>>12]=0;
9be4ba64 402 inv_code_start=inv_code_end=~0;
63cb0298 403#ifndef DISABLE_TLB
57871462 404 memory_map[vaddr>>12]|=0x40000000;
63cb0298 405#endif
57871462 406 if(vpage<2048) {
94d23bb9 407#ifndef DISABLE_TLB
57871462 408 if(tlb_LUT_r[vaddr>>12]) {
409 invalid_code[tlb_LUT_r[vaddr>>12]>>12]=0;
410 memory_map[tlb_LUT_r[vaddr>>12]>>12]|=0x40000000;
411 }
94d23bb9 412#endif
57871462 413 restore_candidate[vpage>>3]|=1<<(vpage&7);
414 }
415 else restore_candidate[page>>3]|=1<<(page&7);
416 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
417 if(ht_bin[0]==vaddr) {
418 ht_bin[1]=(int)head->addr; // Replace existing entry
419 }
420 else
421 {
422 ht_bin[3]=ht_bin[1];
423 ht_bin[2]=ht_bin[0];
424 ht_bin[1]=(int)head->addr;
425 ht_bin[0]=vaddr;
426 }
427 return head->addr;
428 }
429 }
430 head=head->next;
431 }
432 //printf("TRACE: count=%d next=%d (get_addr no-match %x)\n",Count,next_interupt,vaddr);
433 int r=new_recompile_block(vaddr);
434 if(r==0) return get_addr(vaddr);
435 // Execute in unmapped page, generate pagefault execption
436 Status|=2;
437 Cause=(vaddr<<31)|0x8;
438 EPC=(vaddr&1)?vaddr-5:vaddr;
439 BadVAddr=(vaddr&~1);
440 Context=(Context&0xFF80000F)|((BadVAddr>>9)&0x007FFFF0);
441 EntryHi=BadVAddr&0xFFFFE000;
442 return get_addr_ht(0x80000000);
443}
444// Look up address in hash table first
445void *get_addr_ht(u_int vaddr)
446{
447 //printf("TRACE: count=%d next=%d (get_addr_ht %x)\n",Count,next_interupt,vaddr);
448 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
449 if(ht_bin[0]==vaddr) return (void *)ht_bin[1];
450 if(ht_bin[2]==vaddr) return (void *)ht_bin[3];
451 return get_addr(vaddr);
452}
453
454void *get_addr_32(u_int vaddr,u_int flags)
455{
7139f3c8 456#ifdef FORCE32
457 return get_addr(vaddr);
560e4a12 458#else
57871462 459 //printf("TRACE: count=%d next=%d (get_addr_32 %x,flags %x)\n",Count,next_interupt,vaddr,flags);
460 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
461 if(ht_bin[0]==vaddr) return (void *)ht_bin[1];
462 if(ht_bin[2]==vaddr) return (void *)ht_bin[3];
94d23bb9 463 u_int page=get_page(vaddr);
464 u_int vpage=get_vpage(vaddr);
57871462 465 struct ll_entry *head;
466 head=jump_in[page];
467 while(head!=NULL) {
468 if(head->vaddr==vaddr&&(head->reg32&flags)==0) {
469 //printf("TRACE: count=%d next=%d (get_addr_32 match %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr);
470 if(head->reg32==0) {
471 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
472 if(ht_bin[0]==-1) {
473 ht_bin[1]=(int)head->addr;
474 ht_bin[0]=vaddr;
475 }else if(ht_bin[2]==-1) {
476 ht_bin[3]=(int)head->addr;
477 ht_bin[2]=vaddr;
478 }
479 //ht_bin[3]=ht_bin[1];
480 //ht_bin[2]=ht_bin[0];
481 //ht_bin[1]=(int)head->addr;
482 //ht_bin[0]=vaddr;
483 }
484 return head->addr;
485 }
486 head=head->next;
487 }
488 head=jump_dirty[vpage];
489 while(head!=NULL) {
490 if(head->vaddr==vaddr&&(head->reg32&flags)==0) {
491 //printf("TRACE: count=%d next=%d (get_addr_32 match dirty %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr);
492 // Don't restore blocks which are about to expire from the cache
493 if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
494 if(verify_dirty(head->addr)) {
495 //printf("restore candidate: %x (%d) d=%d\n",vaddr,page,invalid_code[vaddr>>12]);
496 invalid_code[vaddr>>12]=0;
9be4ba64 497 inv_code_start=inv_code_end=~0;
57871462 498 memory_map[vaddr>>12]|=0x40000000;
499 if(vpage<2048) {
94d23bb9 500#ifndef DISABLE_TLB
57871462 501 if(tlb_LUT_r[vaddr>>12]) {
502 invalid_code[tlb_LUT_r[vaddr>>12]>>12]=0;
503 memory_map[tlb_LUT_r[vaddr>>12]>>12]|=0x40000000;
504 }
94d23bb9 505#endif
57871462 506 restore_candidate[vpage>>3]|=1<<(vpage&7);
507 }
508 else restore_candidate[page>>3]|=1<<(page&7);
509 if(head->reg32==0) {
510 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
511 if(ht_bin[0]==-1) {
512 ht_bin[1]=(int)head->addr;
513 ht_bin[0]=vaddr;
514 }else if(ht_bin[2]==-1) {
515 ht_bin[3]=(int)head->addr;
516 ht_bin[2]=vaddr;
517 }
518 //ht_bin[3]=ht_bin[1];
519 //ht_bin[2]=ht_bin[0];
520 //ht_bin[1]=(int)head->addr;
521 //ht_bin[0]=vaddr;
522 }
523 return head->addr;
524 }
525 }
526 head=head->next;
527 }
528 //printf("TRACE: count=%d next=%d (get_addr_32 no-match %x,flags %x)\n",Count,next_interupt,vaddr,flags);
529 int r=new_recompile_block(vaddr);
530 if(r==0) return get_addr(vaddr);
531 // Execute in unmapped page, generate pagefault execption
532 Status|=2;
533 Cause=(vaddr<<31)|0x8;
534 EPC=(vaddr&1)?vaddr-5:vaddr;
535 BadVAddr=(vaddr&~1);
536 Context=(Context&0xFF80000F)|((BadVAddr>>9)&0x007FFFF0);
537 EntryHi=BadVAddr&0xFFFFE000;
538 return get_addr_ht(0x80000000);
560e4a12 539#endif
57871462 540}
541
542void clear_all_regs(signed char regmap[])
543{
544 int hr;
545 for (hr=0;hr<HOST_REGS;hr++) regmap[hr]=-1;
546}
547
548signed char get_reg(signed char regmap[],int r)
549{
550 int hr;
551 for (hr=0;hr<HOST_REGS;hr++) if(hr!=EXCLUDE_REG&&regmap[hr]==r) return hr;
552 return -1;
553}
554
555// Find a register that is available for two consecutive cycles
556signed char get_reg2(signed char regmap1[],signed char regmap2[],int r)
557{
558 int hr;
559 for (hr=0;hr<HOST_REGS;hr++) if(hr!=EXCLUDE_REG&&regmap1[hr]==r&&regmap2[hr]==r) return hr;
560 return -1;
561}
562
563int count_free_regs(signed char regmap[])
564{
565 int count=0;
566 int hr;
567 for(hr=0;hr<HOST_REGS;hr++)
568 {
569 if(hr!=EXCLUDE_REG) {
570 if(regmap[hr]<0) count++;
571 }
572 }
573 return count;
574}
575
576void dirty_reg(struct regstat *cur,signed char reg)
577{
578 int hr;
579 if(!reg) return;
580 for (hr=0;hr<HOST_REGS;hr++) {
581 if((cur->regmap[hr]&63)==reg) {
582 cur->dirty|=1<<hr;
583 }
584 }
585}
586
587// If we dirty the lower half of a 64 bit register which is now being
588// sign-extended, we need to dump the upper half.
589// Note: Do this only after completion of the instruction, because
590// some instructions may need to read the full 64-bit value even if
591// overwriting it (eg SLTI, DSRA32).
592static void flush_dirty_uppers(struct regstat *cur)
593{
594 int hr,reg;
595 for (hr=0;hr<HOST_REGS;hr++) {
596 if((cur->dirty>>hr)&1) {
597 reg=cur->regmap[hr];
598 if(reg>=64)
599 if((cur->is32>>(reg&63))&1) cur->regmap[hr]=-1;
600 }
601 }
602}
603
604void set_const(struct regstat *cur,signed char reg,uint64_t value)
605{
606 int hr;
607 if(!reg) return;
608 for (hr=0;hr<HOST_REGS;hr++) {
609 if(cur->regmap[hr]==reg) {
610 cur->isconst|=1<<hr;
956f3129 611 current_constmap[hr]=value;
57871462 612 }
613 else if((cur->regmap[hr]^64)==reg) {
614 cur->isconst|=1<<hr;
956f3129 615 current_constmap[hr]=value>>32;
57871462 616 }
617 }
618}
619
620void clear_const(struct regstat *cur,signed char reg)
621{
622 int hr;
623 if(!reg) return;
624 for (hr=0;hr<HOST_REGS;hr++) {
625 if((cur->regmap[hr]&63)==reg) {
626 cur->isconst&=~(1<<hr);
627 }
628 }
629}
630
631int is_const(struct regstat *cur,signed char reg)
632{
633 int hr;
79c75f1b 634 if(reg<0) return 0;
57871462 635 if(!reg) return 1;
636 for (hr=0;hr<HOST_REGS;hr++) {
637 if((cur->regmap[hr]&63)==reg) {
638 return (cur->isconst>>hr)&1;
639 }
640 }
641 return 0;
642}
643uint64_t get_const(struct regstat *cur,signed char reg)
644{
645 int hr;
646 if(!reg) return 0;
647 for (hr=0;hr<HOST_REGS;hr++) {
648 if(cur->regmap[hr]==reg) {
956f3129 649 return current_constmap[hr];
57871462 650 }
651 }
652 printf("Unknown constant in r%d\n",reg);
653 exit(1);
654}
655
656// Least soon needed registers
657// Look at the next ten instructions and see which registers
658// will be used. Try not to reallocate these.
659void lsn(u_char hsn[], int i, int *preferred_reg)
660{
661 int j;
662 int b=-1;
663 for(j=0;j<9;j++)
664 {
665 if(i+j>=slen) {
666 j=slen-i-1;
667 break;
668 }
669 if(itype[i+j]==UJUMP||itype[i+j]==RJUMP||(source[i+j]>>16)==0x1000)
670 {
671 // Don't go past an unconditonal jump
672 j++;
673 break;
674 }
675 }
676 for(;j>=0;j--)
677 {
678 if(rs1[i+j]) hsn[rs1[i+j]]=j;
679 if(rs2[i+j]) hsn[rs2[i+j]]=j;
680 if(rt1[i+j]) hsn[rt1[i+j]]=j;
681 if(rt2[i+j]) hsn[rt2[i+j]]=j;
682 if(itype[i+j]==STORE || itype[i+j]==STORELR) {
683 // Stores can allocate zero
684 hsn[rs1[i+j]]=j;
685 hsn[rs2[i+j]]=j;
686 }
687 // On some architectures stores need invc_ptr
688 #if defined(HOST_IMM8)
b9b61529 689 if(itype[i+j]==STORE || itype[i+j]==STORELR || (opcode[i+j]&0x3b)==0x39 || (opcode[i+j]&0x3b)==0x3a) {
57871462 690 hsn[INVCP]=j;
691 }
692 #endif
693 if(i+j>=0&&(itype[i+j]==UJUMP||itype[i+j]==CJUMP||itype[i+j]==SJUMP||itype[i+j]==FJUMP))
694 {
695 hsn[CCREG]=j;
696 b=j;
697 }
698 }
699 if(b>=0)
700 {
701 if(ba[i+b]>=start && ba[i+b]<(start+slen*4))
702 {
703 // Follow first branch
704 int t=(ba[i+b]-start)>>2;
705 j=7-b;if(t+j>=slen) j=slen-t-1;
706 for(;j>=0;j--)
707 {
708 if(rs1[t+j]) if(hsn[rs1[t+j]]>j+b+2) hsn[rs1[t+j]]=j+b+2;
709 if(rs2[t+j]) if(hsn[rs2[t+j]]>j+b+2) hsn[rs2[t+j]]=j+b+2;
710 //if(rt1[t+j]) if(hsn[rt1[t+j]]>j+b+2) hsn[rt1[t+j]]=j+b+2;
711 //if(rt2[t+j]) if(hsn[rt2[t+j]]>j+b+2) hsn[rt2[t+j]]=j+b+2;
712 }
713 }
714 // TODO: preferred register based on backward branch
715 }
716 // Delay slot should preferably not overwrite branch conditions or cycle count
717 if(i>0&&(itype[i-1]==RJUMP||itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP)) {
718 if(rs1[i-1]) if(hsn[rs1[i-1]]>1) hsn[rs1[i-1]]=1;
719 if(rs2[i-1]) if(hsn[rs2[i-1]]>1) hsn[rs2[i-1]]=1;
720 hsn[CCREG]=1;
721 // ...or hash tables
722 hsn[RHASH]=1;
723 hsn[RHTBL]=1;
724 }
725 // Coprocessor load/store needs FTEMP, even if not declared
b9b61529 726 if(itype[i]==C1LS||itype[i]==C2LS) {
57871462 727 hsn[FTEMP]=0;
728 }
729 // Load L/R also uses FTEMP as a temporary register
730 if(itype[i]==LOADLR) {
731 hsn[FTEMP]=0;
732 }
b7918751 733 // Also SWL/SWR/SDL/SDR
734 if(opcode[i]==0x2a||opcode[i]==0x2e||opcode[i]==0x2c||opcode[i]==0x2d) {
57871462 735 hsn[FTEMP]=0;
736 }
737 // Don't remove the TLB registers either
b9b61529 738 if(itype[i]==LOAD || itype[i]==LOADLR || itype[i]==STORE || itype[i]==STORELR || itype[i]==C1LS || itype[i]==C2LS) {
57871462 739 hsn[TLREG]=0;
740 }
741 // Don't remove the miniht registers
742 if(itype[i]==UJUMP||itype[i]==RJUMP)
743 {
744 hsn[RHASH]=0;
745 hsn[RHTBL]=0;
746 }
747}
748
749// We only want to allocate registers if we're going to use them again soon
750int needed_again(int r, int i)
751{
752 int j;
753 int b=-1;
754 int rn=10;
57871462 755
756 if(i>0&&(itype[i-1]==UJUMP||itype[i-1]==RJUMP||(source[i-1]>>16)==0x1000))
757 {
758 if(ba[i-1]<start || ba[i-1]>start+slen*4-4)
759 return 0; // Don't need any registers if exiting the block
760 }
761 for(j=0;j<9;j++)
762 {
763 if(i+j>=slen) {
764 j=slen-i-1;
765 break;
766 }
767 if(itype[i+j]==UJUMP||itype[i+j]==RJUMP||(source[i+j]>>16)==0x1000)
768 {
769 // Don't go past an unconditonal jump
770 j++;
771 break;
772 }
1e973cb0 773 if(itype[i+j]==SYSCALL||itype[i+j]==HLECALL||itype[i+j]==INTCALL||((source[i+j]&0xfc00003f)==0x0d))
57871462 774 {
775 break;
776 }
777 }
778 for(;j>=1;j--)
779 {
780 if(rs1[i+j]==r) rn=j;
781 if(rs2[i+j]==r) rn=j;
782 if((unneeded_reg[i+j]>>r)&1) rn=10;
783 if(i+j>=0&&(itype[i+j]==UJUMP||itype[i+j]==CJUMP||itype[i+j]==SJUMP||itype[i+j]==FJUMP))
784 {
785 b=j;
786 }
787 }
788 /*
789 if(b>=0)
790 {
791 if(ba[i+b]>=start && ba[i+b]<(start+slen*4))
792 {
793 // Follow first branch
794 int o=rn;
795 int t=(ba[i+b]-start)>>2;
796 j=7-b;if(t+j>=slen) j=slen-t-1;
797 for(;j>=0;j--)
798 {
799 if(!((unneeded_reg[t+j]>>r)&1)) {
800 if(rs1[t+j]==r) if(rn>j+b+2) rn=j+b+2;
801 if(rs2[t+j]==r) if(rn>j+b+2) rn=j+b+2;
802 }
803 else rn=o;
804 }
805 }
806 }*/
b7217e13 807 if(rn<10) return 1;
57871462 808 return 0;
809}
810
811// Try to match register allocations at the end of a loop with those
812// at the beginning
813int loop_reg(int i, int r, int hr)
814{
815 int j,k;
816 for(j=0;j<9;j++)
817 {
818 if(i+j>=slen) {
819 j=slen-i-1;
820 break;
821 }
822 if(itype[i+j]==UJUMP||itype[i+j]==RJUMP||(source[i+j]>>16)==0x1000)
823 {
824 // Don't go past an unconditonal jump
825 j++;
826 break;
827 }
828 }
829 k=0;
830 if(i>0){
831 if(itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP)
832 k--;
833 }
834 for(;k<j;k++)
835 {
836 if(r<64&&((unneeded_reg[i+k]>>r)&1)) return hr;
837 if(r>64&&((unneeded_reg_upper[i+k]>>r)&1)) return hr;
838 if(i+k>=0&&(itype[i+k]==UJUMP||itype[i+k]==CJUMP||itype[i+k]==SJUMP||itype[i+k]==FJUMP))
839 {
840 if(ba[i+k]>=start && ba[i+k]<(start+i*4))
841 {
842 int t=(ba[i+k]-start)>>2;
843 int reg=get_reg(regs[t].regmap_entry,r);
844 if(reg>=0) return reg;
845 //reg=get_reg(regs[t+1].regmap_entry,r);
846 //if(reg>=0) return reg;
847 }
848 }
849 }
850 return hr;
851}
852
853
854// Allocate every register, preserving source/target regs
855void alloc_all(struct regstat *cur,int i)
856{
857 int hr;
858
859 for(hr=0;hr<HOST_REGS;hr++) {
860 if(hr!=EXCLUDE_REG) {
861 if(((cur->regmap[hr]&63)!=rs1[i])&&((cur->regmap[hr]&63)!=rs2[i])&&
862 ((cur->regmap[hr]&63)!=rt1[i])&&((cur->regmap[hr]&63)!=rt2[i]))
863 {
864 cur->regmap[hr]=-1;
865 cur->dirty&=~(1<<hr);
866 }
867 // Don't need zeros
868 if((cur->regmap[hr]&63)==0)
869 {
870 cur->regmap[hr]=-1;
871 cur->dirty&=~(1<<hr);
872 }
873 }
874 }
875}
876
4600ba03 877#ifndef FORCE32
57871462 878void div64(int64_t dividend,int64_t divisor)
879{
880 lo=dividend/divisor;
881 hi=dividend%divisor;
882 //printf("TRACE: ddiv %8x%8x %8x%8x\n" ,(int)reg[HIREG],(int)(reg[HIREG]>>32)
883 // ,(int)reg[LOREG],(int)(reg[LOREG]>>32));
884}
885void divu64(uint64_t dividend,uint64_t divisor)
886{
887 lo=dividend/divisor;
888 hi=dividend%divisor;
889 //printf("TRACE: ddivu %8x%8x %8x%8x\n",(int)reg[HIREG],(int)(reg[HIREG]>>32)
890 // ,(int)reg[LOREG],(int)(reg[LOREG]>>32));
891}
892
893void mult64(uint64_t m1,uint64_t m2)
894{
895 unsigned long long int op1, op2, op3, op4;
896 unsigned long long int result1, result2, result3, result4;
897 unsigned long long int temp1, temp2, temp3, temp4;
898 int sign = 0;
899
900 if (m1 < 0)
901 {
902 op2 = -m1;
903 sign = 1 - sign;
904 }
905 else op2 = m1;
906 if (m2 < 0)
907 {
908 op4 = -m2;
909 sign = 1 - sign;
910 }
911 else op4 = m2;
912
913 op1 = op2 & 0xFFFFFFFF;
914 op2 = (op2 >> 32) & 0xFFFFFFFF;
915 op3 = op4 & 0xFFFFFFFF;
916 op4 = (op4 >> 32) & 0xFFFFFFFF;
917
918 temp1 = op1 * op3;
919 temp2 = (temp1 >> 32) + op1 * op4;
920 temp3 = op2 * op3;
921 temp4 = (temp3 >> 32) + op2 * op4;
922
923 result1 = temp1 & 0xFFFFFFFF;
924 result2 = temp2 + (temp3 & 0xFFFFFFFF);
925 result3 = (result2 >> 32) + temp4;
926 result4 = (result3 >> 32);
927
928 lo = result1 | (result2 << 32);
929 hi = (result3 & 0xFFFFFFFF) | (result4 << 32);
930 if (sign)
931 {
932 hi = ~hi;
933 if (!lo) hi++;
934 else lo = ~lo + 1;
935 }
936}
937
938void multu64(uint64_t m1,uint64_t m2)
939{
940 unsigned long long int op1, op2, op3, op4;
941 unsigned long long int result1, result2, result3, result4;
942 unsigned long long int temp1, temp2, temp3, temp4;
943
944 op1 = m1 & 0xFFFFFFFF;
945 op2 = (m1 >> 32) & 0xFFFFFFFF;
946 op3 = m2 & 0xFFFFFFFF;
947 op4 = (m2 >> 32) & 0xFFFFFFFF;
948
949 temp1 = op1 * op3;
950 temp2 = (temp1 >> 32) + op1 * op4;
951 temp3 = op2 * op3;
952 temp4 = (temp3 >> 32) + op2 * op4;
953
954 result1 = temp1 & 0xFFFFFFFF;
955 result2 = temp2 + (temp3 & 0xFFFFFFFF);
956 result3 = (result2 >> 32) + temp4;
957 result4 = (result3 >> 32);
958
959 lo = result1 | (result2 << 32);
960 hi = (result3 & 0xFFFFFFFF) | (result4 << 32);
961
962 //printf("TRACE: dmultu %8x%8x %8x%8x\n",(int)reg[HIREG],(int)(reg[HIREG]>>32)
963 // ,(int)reg[LOREG],(int)(reg[LOREG]>>32));
964}
965
966uint64_t ldl_merge(uint64_t original,uint64_t loaded,u_int bits)
967{
968 if(bits) {
969 original<<=64-bits;
970 original>>=64-bits;
971 loaded<<=bits;
972 original|=loaded;
973 }
974 else original=loaded;
975 return original;
976}
977uint64_t ldr_merge(uint64_t original,uint64_t loaded,u_int bits)
978{
979 if(bits^56) {
980 original>>=64-(bits^56);
981 original<<=64-(bits^56);
982 loaded>>=bits^56;
983 original|=loaded;
984 }
985 else original=loaded;
986 return original;
987}
4600ba03 988#endif
57871462 989
990#ifdef __i386__
991#include "assem_x86.c"
992#endif
993#ifdef __x86_64__
994#include "assem_x64.c"
995#endif
996#ifdef __arm__
997#include "assem_arm.c"
998#endif
999
1000// Add virtual address mapping to linked list
1001void ll_add(struct ll_entry **head,int vaddr,void *addr)
1002{
1003 struct ll_entry *new_entry;
1004 new_entry=malloc(sizeof(struct ll_entry));
1005 assert(new_entry!=NULL);
1006 new_entry->vaddr=vaddr;
1007 new_entry->reg32=0;
1008 new_entry->addr=addr;
1009 new_entry->next=*head;
1010 *head=new_entry;
1011}
1012
1013// Add virtual address mapping for 32-bit compiled block
1014void ll_add_32(struct ll_entry **head,int vaddr,u_int reg32,void *addr)
1015{
7139f3c8 1016 ll_add(head,vaddr,addr);
1017#ifndef FORCE32
1018 (*head)->reg32=reg32;
1019#endif
57871462 1020}
1021
1022// Check if an address is already compiled
1023// but don't return addresses which are about to expire from the cache
1024void *check_addr(u_int vaddr)
1025{
1026 u_int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
1027 if(ht_bin[0]==vaddr) {
1028 if(((ht_bin[1]-MAX_OUTPUT_BLOCK_SIZE-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
1029 if(isclean(ht_bin[1])) return (void *)ht_bin[1];
1030 }
1031 if(ht_bin[2]==vaddr) {
1032 if(((ht_bin[3]-MAX_OUTPUT_BLOCK_SIZE-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
1033 if(isclean(ht_bin[3])) return (void *)ht_bin[3];
1034 }
94d23bb9 1035 u_int page=get_page(vaddr);
57871462 1036 struct ll_entry *head;
1037 head=jump_in[page];
1038 while(head!=NULL) {
1039 if(head->vaddr==vaddr&&head->reg32==0) {
1040 if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2))) {
1041 // Update existing entry with current address
1042 if(ht_bin[0]==vaddr) {
1043 ht_bin[1]=(int)head->addr;
1044 return head->addr;
1045 }
1046 if(ht_bin[2]==vaddr) {
1047 ht_bin[3]=(int)head->addr;
1048 return head->addr;
1049 }
1050 // Insert into hash table with low priority.
1051 // Don't evict existing entries, as they are probably
1052 // addresses that are being accessed frequently.
1053 if(ht_bin[0]==-1) {
1054 ht_bin[1]=(int)head->addr;
1055 ht_bin[0]=vaddr;
1056 }else if(ht_bin[2]==-1) {
1057 ht_bin[3]=(int)head->addr;
1058 ht_bin[2]=vaddr;
1059 }
1060 return head->addr;
1061 }
1062 }
1063 head=head->next;
1064 }
1065 return 0;
1066}
1067
1068void remove_hash(int vaddr)
1069{
1070 //printf("remove hash: %x\n",vaddr);
1071 int *ht_bin=hash_table[(((vaddr)>>16)^vaddr)&0xFFFF];
1072 if(ht_bin[2]==vaddr) {
1073 ht_bin[2]=ht_bin[3]=-1;
1074 }
1075 if(ht_bin[0]==vaddr) {
1076 ht_bin[0]=ht_bin[2];
1077 ht_bin[1]=ht_bin[3];
1078 ht_bin[2]=ht_bin[3]=-1;
1079 }
1080}
1081
1082void ll_remove_matching_addrs(struct ll_entry **head,int addr,int shift)
1083{
1084 struct ll_entry *next;
1085 while(*head) {
1086 if(((u_int)((*head)->addr)>>shift)==(addr>>shift) ||
1087 ((u_int)((*head)->addr-MAX_OUTPUT_BLOCK_SIZE)>>shift)==(addr>>shift))
1088 {
1089 inv_debug("EXP: Remove pointer to %x (%x)\n",(int)(*head)->addr,(*head)->vaddr);
1090 remove_hash((*head)->vaddr);
1091 next=(*head)->next;
1092 free(*head);
1093 *head=next;
1094 }
1095 else
1096 {
1097 head=&((*head)->next);
1098 }
1099 }
1100}
1101
1102// Remove all entries from linked list
1103void ll_clear(struct ll_entry **head)
1104{
1105 struct ll_entry *cur;
1106 struct ll_entry *next;
1107 if(cur=*head) {
1108 *head=0;
1109 while(cur) {
1110 next=cur->next;
1111 free(cur);
1112 cur=next;
1113 }
1114 }
1115}
1116
1117// Dereference the pointers and remove if it matches
1118void ll_kill_pointers(struct ll_entry *head,int addr,int shift)
1119{
1120 while(head) {
1121 int ptr=get_pointer(head->addr);
1122 inv_debug("EXP: Lookup pointer to %x at %x (%x)\n",(int)ptr,(int)head->addr,head->vaddr);
1123 if(((ptr>>shift)==(addr>>shift)) ||
1124 (((ptr-MAX_OUTPUT_BLOCK_SIZE)>>shift)==(addr>>shift)))
1125 {
5088bb70 1126 inv_debug("EXP: Kill pointer at %x (%x)\n",(int)head->addr,head->vaddr);
f76eeef9 1127 u_int host_addr=(u_int)kill_pointer(head->addr);
dd3a91a1 1128 #ifdef __arm__
1129 needs_clear_cache[(host_addr-(u_int)BASE_ADDR)>>17]|=1<<(((host_addr-(u_int)BASE_ADDR)>>12)&31);
1130 #endif
57871462 1131 }
1132 head=head->next;
1133 }
1134}
1135
1136// This is called when we write to a compiled block (see do_invstub)
f76eeef9 1137void invalidate_page(u_int page)
57871462 1138{
57871462 1139 struct ll_entry *head;
1140 struct ll_entry *next;
1141 head=jump_in[page];
1142 jump_in[page]=0;
1143 while(head!=NULL) {
1144 inv_debug("INVALIDATE: %x\n",head->vaddr);
1145 remove_hash(head->vaddr);
1146 next=head->next;
1147 free(head);
1148 head=next;
1149 }
1150 head=jump_out[page];
1151 jump_out[page]=0;
1152 while(head!=NULL) {
1153 inv_debug("INVALIDATE: kill pointer to %x (%x)\n",head->vaddr,(int)head->addr);
f76eeef9 1154 u_int host_addr=(u_int)kill_pointer(head->addr);
dd3a91a1 1155 #ifdef __arm__
1156 needs_clear_cache[(host_addr-(u_int)BASE_ADDR)>>17]|=1<<(((host_addr-(u_int)BASE_ADDR)>>12)&31);
1157 #endif
57871462 1158 next=head->next;
1159 free(head);
1160 head=next;
1161 }
57871462 1162}
9be4ba64 1163
1164static void invalidate_block_range(u_int block, u_int first, u_int last)
57871462 1165{
94d23bb9 1166 u_int page=get_page(block<<12);
57871462 1167 //printf("first=%d last=%d\n",first,last);
f76eeef9 1168 invalidate_page(page);
57871462 1169 assert(first+5>page); // NB: this assumes MAXBLOCK<=4096 (4 pages)
1170 assert(last<page+5);
1171 // Invalidate the adjacent pages if a block crosses a 4K boundary
1172 while(first<page) {
1173 invalidate_page(first);
1174 first++;
1175 }
1176 for(first=page+1;first<last;first++) {
1177 invalidate_page(first);
1178 }
dd3a91a1 1179 #ifdef __arm__
1180 do_clear_cache();
1181 #endif
57871462 1182
1183 // Don't trap writes
1184 invalid_code[block]=1;
94d23bb9 1185#ifndef DISABLE_TLB
57871462 1186 // If there is a valid TLB entry for this page, remove write protect
1187 if(tlb_LUT_w[block]) {
1188 assert(tlb_LUT_r[block]==tlb_LUT_w[block]);
1189 // CHECK: Is this right?
1190 memory_map[block]=((tlb_LUT_w[block]&0xFFFFF000)-(block<<12)+(unsigned int)rdram-0x80000000)>>2;
1191 u_int real_block=tlb_LUT_w[block]>>12;
1192 invalid_code[real_block]=1;
1193 if(real_block>=0x80000&&real_block<0x80800) memory_map[real_block]=((u_int)rdram-0x80000000)>>2;
1194 }
1195 else if(block>=0x80000&&block<0x80800) memory_map[block]=((u_int)rdram-0x80000000)>>2;
94d23bb9 1196#endif
f76eeef9 1197
57871462 1198 #ifdef USE_MINI_HT
1199 memset(mini_ht,-1,sizeof(mini_ht));
1200 #endif
1201}
9be4ba64 1202
1203void invalidate_block(u_int block)
1204{
1205 u_int page=get_page(block<<12);
1206 u_int vpage=get_vpage(block<<12);
1207 inv_debug("INVALIDATE: %x (%d)\n",block<<12,page);
1208 //inv_debug("invalid_code[block]=%d\n",invalid_code[block]);
1209 u_int first,last;
1210 first=last=page;
1211 struct ll_entry *head;
1212 head=jump_dirty[vpage];
1213 //printf("page=%d vpage=%d\n",page,vpage);
1214 while(head!=NULL) {
1215 u_int start,end;
1216 if(vpage>2047||(head->vaddr>>12)==block) { // Ignore vaddr hash collision
1217 get_bounds((int)head->addr,&start,&end);
1218 //printf("start: %x end: %x\n",start,end);
4a35de07 1219 if(page<2048&&start>=(u_int)rdram&&end<(u_int)rdram+RAM_SIZE) {
9be4ba64 1220 if(((start-(u_int)rdram)>>12)<=page&&((end-1-(u_int)rdram)>>12)>=page) {
1221 if((((start-(u_int)rdram)>>12)&2047)<first) first=((start-(u_int)rdram)>>12)&2047;
1222 if((((end-1-(u_int)rdram)>>12)&2047)>last) last=((end-1-(u_int)rdram)>>12)&2047;
1223 }
1224 }
1225#ifndef DISABLE_TLB
1226 if(page<2048&&(signed int)start>=(signed int)0xC0000000&&(signed int)end>=(signed int)0xC0000000) {
1227 if(((start+memory_map[start>>12]-(u_int)rdram)>>12)<=page&&((end-1+memory_map[(end-1)>>12]-(u_int)rdram)>>12)>=page) {
1228 if((((start+memory_map[start>>12]-(u_int)rdram)>>12)&2047)<first) first=((start+memory_map[start>>12]-(u_int)rdram)>>12)&2047;
1229 if((((end-1+memory_map[(end-1)>>12]-(u_int)rdram)>>12)&2047)>last) last=((end-1+memory_map[(end-1)>>12]-(u_int)rdram)>>12)&2047;
1230 }
1231 }
1232#endif
1233 }
1234 head=head->next;
1235 }
1236 invalidate_block_range(block,first,last);
1237}
1238
57871462 1239void invalidate_addr(u_int addr)
1240{
9be4ba64 1241#ifdef PCSX
1242 //static int rhits;
1243 // this check is done by the caller
1244 //if (inv_code_start<=addr&&addr<=inv_code_end) { rhits++; return; }
d25604ca 1245 u_int page=get_vpage(addr);
9be4ba64 1246 if(page<2048) { // RAM
1247 struct ll_entry *head;
1248 u_int addr_min=~0, addr_max=0;
4a35de07 1249 u_int mask=RAM_SIZE-1;
1250 u_int addr_main=0x80000000|(addr&mask);
9be4ba64 1251 int pg1;
4a35de07 1252 inv_code_start=addr_main&~0xfff;
1253 inv_code_end=addr_main|0xfff;
9be4ba64 1254 pg1=page;
1255 if (pg1>0) {
1256 // must check previous page too because of spans..
1257 pg1--;
1258 inv_code_start-=0x1000;
1259 }
1260 for(;pg1<=page;pg1++) {
1261 for(head=jump_dirty[pg1];head!=NULL;head=head->next) {
1262 u_int start,end;
1263 get_bounds((int)head->addr,&start,&end);
4a35de07 1264 if(ram_offset) {
1265 start-=ram_offset;
1266 end-=ram_offset;
1267 }
1268 if(start<=addr_main&&addr_main<end) {
9be4ba64 1269 if(start<addr_min) addr_min=start;
1270 if(end>addr_max) addr_max=end;
1271 }
4a35de07 1272 else if(addr_main<start) {
9be4ba64 1273 if(start<inv_code_end)
1274 inv_code_end=start-1;
1275 }
1276 else {
1277 if(end>inv_code_start)
1278 inv_code_start=end;
1279 }
1280 }
1281 }
1282 if (addr_min!=~0) {
1283 inv_debug("INV ADDR: %08x hit %08x-%08x\n", addr, addr_min, addr_max);
1284 inv_code_start=inv_code_end=~0;
1285 invalidate_block_range(addr>>12,(addr_min&mask)>>12,(addr_max&mask)>>12);
1286 return;
1287 }
1288 else {
4a35de07 1289 inv_code_start=(addr&~mask)|(inv_code_start&mask);
1290 inv_code_end=(addr&~mask)|(inv_code_end&mask);
d25604ca 1291 inv_debug("INV ADDR: %08x miss, inv %08x-%08x, sk %d\n", addr, inv_code_start, inv_code_end, 0);
9be4ba64 1292 return;
d25604ca 1293 }
9be4ba64 1294 }
1295#endif
57871462 1296 invalidate_block(addr>>12);
1297}
9be4ba64 1298
dd3a91a1 1299// This is called when loading a save state.
1300// Anything could have changed, so invalidate everything.
57871462 1301void invalidate_all_pages()
1302{
1303 u_int page,n;
1304 for(page=0;page<4096;page++)
1305 invalidate_page(page);
1306 for(page=0;page<1048576;page++)
1307 if(!invalid_code[page]) {
1308 restore_candidate[(page&2047)>>3]|=1<<(page&7);
1309 restore_candidate[((page&2047)>>3)+256]|=1<<(page&7);
1310 }
1311 #ifdef __arm__
1312 __clear_cache((void *)BASE_ADDR,(void *)BASE_ADDR+(1<<TARGET_SIZE_2));
1313 #endif
1314 #ifdef USE_MINI_HT
1315 memset(mini_ht,-1,sizeof(mini_ht));
1316 #endif
94d23bb9 1317 #ifndef DISABLE_TLB
57871462 1318 // TLB
1319 for(page=0;page<0x100000;page++) {
1320 if(tlb_LUT_r[page]) {
1321 memory_map[page]=((tlb_LUT_r[page]&0xFFFFF000)-(page<<12)+(unsigned int)rdram-0x80000000)>>2;
1322 if(!tlb_LUT_w[page]||!invalid_code[page])
1323 memory_map[page]|=0x40000000; // Write protect
1324 }
1325 else memory_map[page]=-1;
1326 if(page==0x80000) page=0xC0000;
1327 }
1328 tlb_hacks();
94d23bb9 1329 #endif
57871462 1330}
1331
1332// Add an entry to jump_out after making a link
1333void add_link(u_int vaddr,void *src)
1334{
94d23bb9 1335 u_int page=get_page(vaddr);
57871462 1336 inv_debug("add_link: %x -> %x (%d)\n",(int)src,vaddr,page);
76f71c27 1337 int *ptr=(int *)(src+4);
1338 assert((*ptr&0x0fff0000)==0x059f0000);
57871462 1339 ll_add(jump_out+page,vaddr,src);
1340 //int ptr=get_pointer(src);
1341 //inv_debug("add_link: Pointer is to %x\n",(int)ptr);
1342}
1343
1344// If a code block was found to be unmodified (bit was set in
1345// restore_candidate) and it remains unmodified (bit is clear
1346// in invalid_code) then move the entries for that 4K page from
1347// the dirty list to the clean list.
1348void clean_blocks(u_int page)
1349{
1350 struct ll_entry *head;
1351 inv_debug("INV: clean_blocks page=%d\n",page);
1352 head=jump_dirty[page];
1353 while(head!=NULL) {
1354 if(!invalid_code[head->vaddr>>12]) {
1355 // Don't restore blocks which are about to expire from the cache
1356 if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2))) {
1357 u_int start,end;
1358 if(verify_dirty((int)head->addr)) {
1359 //printf("Possibly Restore %x (%x)\n",head->vaddr, (int)head->addr);
1360 u_int i;
1361 u_int inv=0;
1362 get_bounds((int)head->addr,&start,&end);
4cb76aa4 1363 if(start-(u_int)rdram<RAM_SIZE) {
57871462 1364 for(i=(start-(u_int)rdram+0x80000000)>>12;i<=(end-1-(u_int)rdram+0x80000000)>>12;i++) {
1365 inv|=invalid_code[i];
1366 }
1367 }
63cb0298 1368#ifndef DISABLE_TLB
57871462 1369 if((signed int)head->vaddr>=(signed int)0xC0000000) {
1370 u_int addr = (head->vaddr+(memory_map[head->vaddr>>12]<<2));
1371 //printf("addr=%x start=%x end=%x\n",addr,start,end);
1372 if(addr<start||addr>=end) inv=1;
1373 }
63cb0298 1374#endif
4cb76aa4 1375 else if((signed int)head->vaddr>=(signed int)0x80000000+RAM_SIZE) {
57871462 1376 inv=1;
1377 }
1378 if(!inv) {
1379 void * clean_addr=(void *)get_clean_addr((int)head->addr);
1380 if((((u_int)clean_addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2))) {
1381 u_int ppage=page;
94d23bb9 1382#ifndef DISABLE_TLB
57871462 1383 if(page<2048&&tlb_LUT_r[head->vaddr>>12]) ppage=(tlb_LUT_r[head->vaddr>>12]^0x80000000)>>12;
94d23bb9 1384#endif
57871462 1385 inv_debug("INV: Restored %x (%x/%x)\n",head->vaddr, (int)head->addr, (int)clean_addr);
1386 //printf("page=%x, addr=%x\n",page,head->vaddr);
1387 //assert(head->vaddr>>12==(page|0x80000));
1388 ll_add_32(jump_in+ppage,head->vaddr,head->reg32,clean_addr);
1389 int *ht_bin=hash_table[((head->vaddr>>16)^head->vaddr)&0xFFFF];
1390 if(!head->reg32) {
1391 if(ht_bin[0]==head->vaddr) {
1392 ht_bin[1]=(int)clean_addr; // Replace existing entry
1393 }
1394 if(ht_bin[2]==head->vaddr) {
1395 ht_bin[3]=(int)clean_addr; // Replace existing entry
1396 }
1397 }
1398 }
1399 }
1400 }
1401 }
1402 }
1403 head=head->next;
1404 }
1405}
1406
1407
1408void mov_alloc(struct regstat *current,int i)
1409{
1410 // Note: Don't need to actually alloc the source registers
1411 if((~current->is32>>rs1[i])&1) {
1412 //alloc_reg64(current,i,rs1[i]);
1413 alloc_reg64(current,i,rt1[i]);
1414 current->is32&=~(1LL<<rt1[i]);
1415 } else {
1416 //alloc_reg(current,i,rs1[i]);
1417 alloc_reg(current,i,rt1[i]);
1418 current->is32|=(1LL<<rt1[i]);
1419 }
1420 clear_const(current,rs1[i]);
1421 clear_const(current,rt1[i]);
1422 dirty_reg(current,rt1[i]);
1423}
1424
1425void shiftimm_alloc(struct regstat *current,int i)
1426{
57871462 1427 if(opcode2[i]<=0x3) // SLL/SRL/SRA
1428 {
1429 if(rt1[i]) {
1430 if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1431 else lt1[i]=rs1[i];
1432 alloc_reg(current,i,rt1[i]);
1433 current->is32|=1LL<<rt1[i];
1434 dirty_reg(current,rt1[i]);
dc49e339 1435 if(is_const(current,rs1[i])) {
1436 int v=get_const(current,rs1[i]);
1437 if(opcode2[i]==0x00) set_const(current,rt1[i],v<<imm[i]);
1438 if(opcode2[i]==0x02) set_const(current,rt1[i],(u_int)v>>imm[i]);
1439 if(opcode2[i]==0x03) set_const(current,rt1[i],v>>imm[i]);
1440 }
1441 else clear_const(current,rt1[i]);
57871462 1442 }
1443 }
dc49e339 1444 else
1445 {
1446 clear_const(current,rs1[i]);
1447 clear_const(current,rt1[i]);
1448 }
1449
57871462 1450 if(opcode2[i]>=0x38&&opcode2[i]<=0x3b) // DSLL/DSRL/DSRA
1451 {
1452 if(rt1[i]) {
1453 if(rs1[i]) alloc_reg64(current,i,rs1[i]);
1454 alloc_reg64(current,i,rt1[i]);
1455 current->is32&=~(1LL<<rt1[i]);
1456 dirty_reg(current,rt1[i]);
1457 }
1458 }
1459 if(opcode2[i]==0x3c) // DSLL32
1460 {
1461 if(rt1[i]) {
1462 if(rs1[i]) alloc_reg(current,i,rs1[i]);
1463 alloc_reg64(current,i,rt1[i]);
1464 current->is32&=~(1LL<<rt1[i]);
1465 dirty_reg(current,rt1[i]);
1466 }
1467 }
1468 if(opcode2[i]==0x3e) // DSRL32
1469 {
1470 if(rt1[i]) {
1471 alloc_reg64(current,i,rs1[i]);
1472 if(imm[i]==32) {
1473 alloc_reg64(current,i,rt1[i]);
1474 current->is32&=~(1LL<<rt1[i]);
1475 } else {
1476 alloc_reg(current,i,rt1[i]);
1477 current->is32|=1LL<<rt1[i];
1478 }
1479 dirty_reg(current,rt1[i]);
1480 }
1481 }
1482 if(opcode2[i]==0x3f) // DSRA32
1483 {
1484 if(rt1[i]) {
1485 alloc_reg64(current,i,rs1[i]);
1486 alloc_reg(current,i,rt1[i]);
1487 current->is32|=1LL<<rt1[i];
1488 dirty_reg(current,rt1[i]);
1489 }
1490 }
1491}
1492
1493void shift_alloc(struct regstat *current,int i)
1494{
1495 if(rt1[i]) {
1496 if(opcode2[i]<=0x07) // SLLV/SRLV/SRAV
1497 {
1498 if(rs1[i]) alloc_reg(current,i,rs1[i]);
1499 if(rs2[i]) alloc_reg(current,i,rs2[i]);
1500 alloc_reg(current,i,rt1[i]);
e1190b87 1501 if(rt1[i]==rs2[i]) {
1502 alloc_reg_temp(current,i,-1);
1503 minimum_free_regs[i]=1;
1504 }
57871462 1505 current->is32|=1LL<<rt1[i];
1506 } else { // DSLLV/DSRLV/DSRAV
1507 if(rs1[i]) alloc_reg64(current,i,rs1[i]);
1508 if(rs2[i]) alloc_reg(current,i,rs2[i]);
1509 alloc_reg64(current,i,rt1[i]);
1510 current->is32&=~(1LL<<rt1[i]);
1511 if(opcode2[i]==0x16||opcode2[i]==0x17) // DSRLV and DSRAV need a temporary register
e1190b87 1512 {
57871462 1513 alloc_reg_temp(current,i,-1);
e1190b87 1514 minimum_free_regs[i]=1;
1515 }
57871462 1516 }
1517 clear_const(current,rs1[i]);
1518 clear_const(current,rs2[i]);
1519 clear_const(current,rt1[i]);
1520 dirty_reg(current,rt1[i]);
1521 }
1522}
1523
1524void alu_alloc(struct regstat *current,int i)
1525{
1526 if(opcode2[i]>=0x20&&opcode2[i]<=0x23) { // ADD/ADDU/SUB/SUBU
1527 if(rt1[i]) {
1528 if(rs1[i]&&rs2[i]) {
1529 alloc_reg(current,i,rs1[i]);
1530 alloc_reg(current,i,rs2[i]);
1531 }
1532 else {
1533 if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1534 if(rs2[i]&&needed_again(rs2[i],i)) alloc_reg(current,i,rs2[i]);
1535 }
1536 alloc_reg(current,i,rt1[i]);
1537 }
1538 current->is32|=1LL<<rt1[i];
1539 }
1540 if(opcode2[i]==0x2a||opcode2[i]==0x2b) { // SLT/SLTU
1541 if(rt1[i]) {
1542 if(!((current->is32>>rs1[i])&(current->is32>>rs2[i])&1))
1543 {
1544 alloc_reg64(current,i,rs1[i]);
1545 alloc_reg64(current,i,rs2[i]);
1546 alloc_reg(current,i,rt1[i]);
1547 } else {
1548 alloc_reg(current,i,rs1[i]);
1549 alloc_reg(current,i,rs2[i]);
1550 alloc_reg(current,i,rt1[i]);
1551 }
1552 }
1553 current->is32|=1LL<<rt1[i];
1554 }
1555 if(opcode2[i]>=0x24&&opcode2[i]<=0x27) { // AND/OR/XOR/NOR
1556 if(rt1[i]) {
1557 if(rs1[i]&&rs2[i]) {
1558 alloc_reg(current,i,rs1[i]);
1559 alloc_reg(current,i,rs2[i]);
1560 }
1561 else
1562 {
1563 if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1564 if(rs2[i]&&needed_again(rs2[i],i)) alloc_reg(current,i,rs2[i]);
1565 }
1566 alloc_reg(current,i,rt1[i]);
1567 if(!((current->is32>>rs1[i])&(current->is32>>rs2[i])&1))
1568 {
1569 if(!((current->uu>>rt1[i])&1)) {
1570 alloc_reg64(current,i,rt1[i]);
1571 }
1572 if(get_reg(current->regmap,rt1[i]|64)>=0) {
1573 if(rs1[i]&&rs2[i]) {
1574 alloc_reg64(current,i,rs1[i]);
1575 alloc_reg64(current,i,rs2[i]);
1576 }
1577 else
1578 {
1579 // Is is really worth it to keep 64-bit values in registers?
1580 #ifdef NATIVE_64BIT
1581 if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg64(current,i,rs1[i]);
1582 if(rs2[i]&&needed_again(rs2[i],i)) alloc_reg64(current,i,rs2[i]);
1583 #endif
1584 }
1585 }
1586 current->is32&=~(1LL<<rt1[i]);
1587 } else {
1588 current->is32|=1LL<<rt1[i];
1589 }
1590 }
1591 }
1592 if(opcode2[i]>=0x2c&&opcode2[i]<=0x2f) { // DADD/DADDU/DSUB/DSUBU
1593 if(rt1[i]) {
1594 if(rs1[i]&&rs2[i]) {
1595 if(!((current->uu>>rt1[i])&1)||get_reg(current->regmap,rt1[i]|64)>=0) {
1596 alloc_reg64(current,i,rs1[i]);
1597 alloc_reg64(current,i,rs2[i]);
1598 alloc_reg64(current,i,rt1[i]);
1599 } else {
1600 alloc_reg(current,i,rs1[i]);
1601 alloc_reg(current,i,rs2[i]);
1602 alloc_reg(current,i,rt1[i]);
1603 }
1604 }
1605 else {
1606 alloc_reg(current,i,rt1[i]);
1607 if(!((current->uu>>rt1[i])&1)||get_reg(current->regmap,rt1[i]|64)>=0) {
1608 // DADD used as move, or zeroing
1609 // If we have a 64-bit source, then make the target 64 bits too
1610 if(rs1[i]&&!((current->is32>>rs1[i])&1)) {
1611 if(get_reg(current->regmap,rs1[i])>=0) alloc_reg64(current,i,rs1[i]);
1612 alloc_reg64(current,i,rt1[i]);
1613 } else if(rs2[i]&&!((current->is32>>rs2[i])&1)) {
1614 if(get_reg(current->regmap,rs2[i])>=0) alloc_reg64(current,i,rs2[i]);
1615 alloc_reg64(current,i,rt1[i]);
1616 }
1617 if(opcode2[i]>=0x2e&&rs2[i]) {
1618 // DSUB used as negation - 64-bit result
1619 // If we have a 32-bit register, extend it to 64 bits
1620 if(get_reg(current->regmap,rs2[i])>=0) alloc_reg64(current,i,rs2[i]);
1621 alloc_reg64(current,i,rt1[i]);
1622 }
1623 }
1624 }
1625 if(rs1[i]&&rs2[i]) {
1626 current->is32&=~(1LL<<rt1[i]);
1627 } else if(rs1[i]) {
1628 current->is32&=~(1LL<<rt1[i]);
1629 if((current->is32>>rs1[i])&1)
1630 current->is32|=1LL<<rt1[i];
1631 } else if(rs2[i]) {
1632 current->is32&=~(1LL<<rt1[i]);
1633 if((current->is32>>rs2[i])&1)
1634 current->is32|=1LL<<rt1[i];
1635 } else {
1636 current->is32|=1LL<<rt1[i];
1637 }
1638 }
1639 }
1640 clear_const(current,rs1[i]);
1641 clear_const(current,rs2[i]);
1642 clear_const(current,rt1[i]);
1643 dirty_reg(current,rt1[i]);
1644}
1645
1646void imm16_alloc(struct regstat *current,int i)
1647{
1648 if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1649 else lt1[i]=rs1[i];
1650 if(rt1[i]) alloc_reg(current,i,rt1[i]);
1651 if(opcode[i]==0x18||opcode[i]==0x19) { // DADDI/DADDIU
1652 current->is32&=~(1LL<<rt1[i]);
1653 if(!((current->uu>>rt1[i])&1)||get_reg(current->regmap,rt1[i]|64)>=0) {
1654 // TODO: Could preserve the 32-bit flag if the immediate is zero
1655 alloc_reg64(current,i,rt1[i]);
1656 alloc_reg64(current,i,rs1[i]);
1657 }
1658 clear_const(current,rs1[i]);
1659 clear_const(current,rt1[i]);
1660 }
1661 else if(opcode[i]==0x0a||opcode[i]==0x0b) { // SLTI/SLTIU
1662 if((~current->is32>>rs1[i])&1) alloc_reg64(current,i,rs1[i]);
1663 current->is32|=1LL<<rt1[i];
1664 clear_const(current,rs1[i]);
1665 clear_const(current,rt1[i]);
1666 }
1667 else if(opcode[i]>=0x0c&&opcode[i]<=0x0e) { // ANDI/ORI/XORI
1668 if(((~current->is32>>rs1[i])&1)&&opcode[i]>0x0c) {
1669 if(rs1[i]!=rt1[i]) {
1670 if(needed_again(rs1[i],i)) alloc_reg64(current,i,rs1[i]);
1671 alloc_reg64(current,i,rt1[i]);
1672 current->is32&=~(1LL<<rt1[i]);
1673 }
1674 }
1675 else current->is32|=1LL<<rt1[i]; // ANDI clears upper bits
1676 if(is_const(current,rs1[i])) {
1677 int v=get_const(current,rs1[i]);
1678 if(opcode[i]==0x0c) set_const(current,rt1[i],v&imm[i]);
1679 if(opcode[i]==0x0d) set_const(current,rt1[i],v|imm[i]);
1680 if(opcode[i]==0x0e) set_const(current,rt1[i],v^imm[i]);
1681 }
1682 else clear_const(current,rt1[i]);
1683 }
1684 else if(opcode[i]==0x08||opcode[i]==0x09) { // ADDI/ADDIU
1685 if(is_const(current,rs1[i])) {
1686 int v=get_const(current,rs1[i]);
1687 set_const(current,rt1[i],v+imm[i]);
1688 }
1689 else clear_const(current,rt1[i]);
1690 current->is32|=1LL<<rt1[i];
1691 }
1692 else {
1693 set_const(current,rt1[i],((long long)((short)imm[i]))<<16); // LUI
1694 current->is32|=1LL<<rt1[i];
1695 }
1696 dirty_reg(current,rt1[i]);
1697}
1698
1699void load_alloc(struct regstat *current,int i)
1700{
1701 clear_const(current,rt1[i]);
1702 //if(rs1[i]!=rt1[i]&&needed_again(rs1[i],i)) clear_const(current,rs1[i]); // Does this help or hurt?
1703 if(!rs1[i]) current->u&=~1LL; // Allow allocating r0 if it's the source register
1704 if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
373d1d07 1705 if(rt1[i]&&!((current->u>>rt1[i])&1)) {
57871462 1706 alloc_reg(current,i,rt1[i]);
373d1d07 1707 assert(get_reg(current->regmap,rt1[i])>=0);
57871462 1708 if(opcode[i]==0x27||opcode[i]==0x37) // LWU/LD
1709 {
1710 current->is32&=~(1LL<<rt1[i]);
1711 alloc_reg64(current,i,rt1[i]);
1712 }
1713 else if(opcode[i]==0x1A||opcode[i]==0x1B) // LDL/LDR
1714 {
1715 current->is32&=~(1LL<<rt1[i]);
1716 alloc_reg64(current,i,rt1[i]);
1717 alloc_all(current,i);
1718 alloc_reg64(current,i,FTEMP);
e1190b87 1719 minimum_free_regs[i]=HOST_REGS;
57871462 1720 }
1721 else current->is32|=1LL<<rt1[i];
1722 dirty_reg(current,rt1[i]);
1723 // If using TLB, need a register for pointer to the mapping table
1724 if(using_tlb) alloc_reg(current,i,TLREG);
1725 // LWL/LWR need a temporary register for the old value
1726 if(opcode[i]==0x22||opcode[i]==0x26)
1727 {
1728 alloc_reg(current,i,FTEMP);
1729 alloc_reg_temp(current,i,-1);
e1190b87 1730 minimum_free_regs[i]=1;
57871462 1731 }
1732 }
1733 else
1734 {
373d1d07 1735 // Load to r0 or unneeded register (dummy load)
57871462 1736 // but we still need a register to calculate the address
535d208a 1737 if(opcode[i]==0x22||opcode[i]==0x26)
1738 {
1739 alloc_reg(current,i,FTEMP); // LWL/LWR need another temporary
1740 }
373d1d07 1741 // If using TLB, need a register for pointer to the mapping table
1742 if(using_tlb) alloc_reg(current,i,TLREG);
57871462 1743 alloc_reg_temp(current,i,-1);
e1190b87 1744 minimum_free_regs[i]=1;
535d208a 1745 if(opcode[i]==0x1A||opcode[i]==0x1B) // LDL/LDR
1746 {
1747 alloc_all(current,i);
1748 alloc_reg64(current,i,FTEMP);
e1190b87 1749 minimum_free_regs[i]=HOST_REGS;
535d208a 1750 }
57871462 1751 }
1752}
1753
1754void store_alloc(struct regstat *current,int i)
1755{
1756 clear_const(current,rs2[i]);
1757 if(!(rs2[i])) current->u&=~1LL; // Allow allocating r0 if necessary
1758 if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1759 alloc_reg(current,i,rs2[i]);
1760 if(opcode[i]==0x2c||opcode[i]==0x2d||opcode[i]==0x3f) { // 64-bit SDL/SDR/SD
1761 alloc_reg64(current,i,rs2[i]);
1762 if(rs2[i]) alloc_reg(current,i,FTEMP);
1763 }
1764 // If using TLB, need a register for pointer to the mapping table
1765 if(using_tlb) alloc_reg(current,i,TLREG);
1766 #if defined(HOST_IMM8)
1767 // On CPUs without 32-bit immediates we need a pointer to invalid_code
1768 else alloc_reg(current,i,INVCP);
1769 #endif
b7918751 1770 if(opcode[i]==0x2a||opcode[i]==0x2e||opcode[i]==0x2c||opcode[i]==0x2d) { // SWL/SWL/SDL/SDR
57871462 1771 alloc_reg(current,i,FTEMP);
1772 }
1773 // We need a temporary register for address generation
1774 alloc_reg_temp(current,i,-1);
e1190b87 1775 minimum_free_regs[i]=1;
57871462 1776}
1777
1778void c1ls_alloc(struct regstat *current,int i)
1779{
1780 //clear_const(current,rs1[i]); // FIXME
1781 clear_const(current,rt1[i]);
1782 if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1783 alloc_reg(current,i,CSREG); // Status
1784 alloc_reg(current,i,FTEMP);
1785 if(opcode[i]==0x35||opcode[i]==0x3d) { // 64-bit LDC1/SDC1
1786 alloc_reg64(current,i,FTEMP);
1787 }
1788 // If using TLB, need a register for pointer to the mapping table
1789 if(using_tlb) alloc_reg(current,i,TLREG);
1790 #if defined(HOST_IMM8)
1791 // On CPUs without 32-bit immediates we need a pointer to invalid_code
1792 else if((opcode[i]&0x3b)==0x39) // SWC1/SDC1
1793 alloc_reg(current,i,INVCP);
1794 #endif
1795 // We need a temporary register for address generation
1796 alloc_reg_temp(current,i,-1);
1797}
1798
b9b61529 1799void c2ls_alloc(struct regstat *current,int i)
1800{
1801 clear_const(current,rt1[i]);
1802 if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1803 alloc_reg(current,i,FTEMP);
1804 // If using TLB, need a register for pointer to the mapping table
1805 if(using_tlb) alloc_reg(current,i,TLREG);
1806 #if defined(HOST_IMM8)
1807 // On CPUs without 32-bit immediates we need a pointer to invalid_code
1808 else if((opcode[i]&0x3b)==0x3a) // SWC2/SDC2
1809 alloc_reg(current,i,INVCP);
1810 #endif
1811 // We need a temporary register for address generation
1812 alloc_reg_temp(current,i,-1);
e1190b87 1813 minimum_free_regs[i]=1;
b9b61529 1814}
1815
57871462 1816#ifndef multdiv_alloc
1817void multdiv_alloc(struct regstat *current,int i)
1818{
1819 // case 0x18: MULT
1820 // case 0x19: MULTU
1821 // case 0x1A: DIV
1822 // case 0x1B: DIVU
1823 // case 0x1C: DMULT
1824 // case 0x1D: DMULTU
1825 // case 0x1E: DDIV
1826 // case 0x1F: DDIVU
1827 clear_const(current,rs1[i]);
1828 clear_const(current,rs2[i]);
1829 if(rs1[i]&&rs2[i])
1830 {
1831 if((opcode2[i]&4)==0) // 32-bit
1832 {
1833 current->u&=~(1LL<<HIREG);
1834 current->u&=~(1LL<<LOREG);
1835 alloc_reg(current,i,HIREG);
1836 alloc_reg(current,i,LOREG);
1837 alloc_reg(current,i,rs1[i]);
1838 alloc_reg(current,i,rs2[i]);
1839 current->is32|=1LL<<HIREG;
1840 current->is32|=1LL<<LOREG;
1841 dirty_reg(current,HIREG);
1842 dirty_reg(current,LOREG);
1843 }
1844 else // 64-bit
1845 {
1846 current->u&=~(1LL<<HIREG);
1847 current->u&=~(1LL<<LOREG);
1848 current->uu&=~(1LL<<HIREG);
1849 current->uu&=~(1LL<<LOREG);
1850 alloc_reg64(current,i,HIREG);
1851 //if(HOST_REGS>10) alloc_reg64(current,i,LOREG);
1852 alloc_reg64(current,i,rs1[i]);
1853 alloc_reg64(current,i,rs2[i]);
1854 alloc_all(current,i);
1855 current->is32&=~(1LL<<HIREG);
1856 current->is32&=~(1LL<<LOREG);
1857 dirty_reg(current,HIREG);
1858 dirty_reg(current,LOREG);
e1190b87 1859 minimum_free_regs[i]=HOST_REGS;
57871462 1860 }
1861 }
1862 else
1863 {
1864 // Multiply by zero is zero.
1865 // MIPS does not have a divide by zero exception.
1866 // The result is undefined, we return zero.
1867 alloc_reg(current,i,HIREG);
1868 alloc_reg(current,i,LOREG);
1869 current->is32|=1LL<<HIREG;
1870 current->is32|=1LL<<LOREG;
1871 dirty_reg(current,HIREG);
1872 dirty_reg(current,LOREG);
1873 }
1874}
1875#endif
1876
1877void cop0_alloc(struct regstat *current,int i)
1878{
1879 if(opcode2[i]==0) // MFC0
1880 {
1881 if(rt1[i]) {
1882 clear_const(current,rt1[i]);
1883 alloc_all(current,i);
1884 alloc_reg(current,i,rt1[i]);
1885 current->is32|=1LL<<rt1[i];
1886 dirty_reg(current,rt1[i]);
1887 }
1888 }
1889 else if(opcode2[i]==4) // MTC0
1890 {
1891 if(rs1[i]){
1892 clear_const(current,rs1[i]);
1893 alloc_reg(current,i,rs1[i]);
1894 alloc_all(current,i);
1895 }
1896 else {
1897 alloc_all(current,i); // FIXME: Keep r0
1898 current->u&=~1LL;
1899 alloc_reg(current,i,0);
1900 }
1901 }
1902 else
1903 {
1904 // TLBR/TLBWI/TLBWR/TLBP/ERET
1905 assert(opcode2[i]==0x10);
1906 alloc_all(current,i);
1907 }
e1190b87 1908 minimum_free_regs[i]=HOST_REGS;
57871462 1909}
1910
1911void cop1_alloc(struct regstat *current,int i)
1912{
1913 alloc_reg(current,i,CSREG); // Load status
1914 if(opcode2[i]<3) // MFC1/DMFC1/CFC1
1915 {
7de557a6 1916 if(rt1[i]){
1917 clear_const(current,rt1[i]);
1918 if(opcode2[i]==1) {
1919 alloc_reg64(current,i,rt1[i]); // DMFC1
1920 current->is32&=~(1LL<<rt1[i]);
1921 }else{
1922 alloc_reg(current,i,rt1[i]); // MFC1/CFC1
1923 current->is32|=1LL<<rt1[i];
1924 }
1925 dirty_reg(current,rt1[i]);
57871462 1926 }
57871462 1927 alloc_reg_temp(current,i,-1);
1928 }
1929 else if(opcode2[i]>3) // MTC1/DMTC1/CTC1
1930 {
1931 if(rs1[i]){
1932 clear_const(current,rs1[i]);
1933 if(opcode2[i]==5)
1934 alloc_reg64(current,i,rs1[i]); // DMTC1
1935 else
1936 alloc_reg(current,i,rs1[i]); // MTC1/CTC1
1937 alloc_reg_temp(current,i,-1);
1938 }
1939 else {
1940 current->u&=~1LL;
1941 alloc_reg(current,i,0);
1942 alloc_reg_temp(current,i,-1);
1943 }
1944 }
e1190b87 1945 minimum_free_regs[i]=1;
57871462 1946}
1947void fconv_alloc(struct regstat *current,int i)
1948{
1949 alloc_reg(current,i,CSREG); // Load status
1950 alloc_reg_temp(current,i,-1);
e1190b87 1951 minimum_free_regs[i]=1;
57871462 1952}
1953void float_alloc(struct regstat *current,int i)
1954{
1955 alloc_reg(current,i,CSREG); // Load status
1956 alloc_reg_temp(current,i,-1);
e1190b87 1957 minimum_free_regs[i]=1;
57871462 1958}
b9b61529 1959void c2op_alloc(struct regstat *current,int i)
1960{
1961 alloc_reg_temp(current,i,-1);
1962}
57871462 1963void fcomp_alloc(struct regstat *current,int i)
1964{
1965 alloc_reg(current,i,CSREG); // Load status
1966 alloc_reg(current,i,FSREG); // Load flags
1967 dirty_reg(current,FSREG); // Flag will be modified
1968 alloc_reg_temp(current,i,-1);
e1190b87 1969 minimum_free_regs[i]=1;
57871462 1970}
1971
1972void syscall_alloc(struct regstat *current,int i)
1973{
1974 alloc_cc(current,i);
1975 dirty_reg(current,CCREG);
1976 alloc_all(current,i);
e1190b87 1977 minimum_free_regs[i]=HOST_REGS;
57871462 1978 current->isconst=0;
1979}
1980
1981void delayslot_alloc(struct regstat *current,int i)
1982{
1983 switch(itype[i]) {
1984 case UJUMP:
1985 case CJUMP:
1986 case SJUMP:
1987 case RJUMP:
1988 case FJUMP:
1989 case SYSCALL:
7139f3c8 1990 case HLECALL:
57871462 1991 case SPAN:
1992 assem_debug("jump in the delay slot. this shouldn't happen.\n");//exit(1);
1993 printf("Disabled speculative precompilation\n");
1994 stop_after_jal=1;
1995 break;
1996 case IMM16:
1997 imm16_alloc(current,i);
1998 break;
1999 case LOAD:
2000 case LOADLR:
2001 load_alloc(current,i);
2002 break;
2003 case STORE:
2004 case STORELR:
2005 store_alloc(current,i);
2006 break;
2007 case ALU:
2008 alu_alloc(current,i);
2009 break;
2010 case SHIFT:
2011 shift_alloc(current,i);
2012 break;
2013 case MULTDIV:
2014 multdiv_alloc(current,i);
2015 break;
2016 case SHIFTIMM:
2017 shiftimm_alloc(current,i);
2018 break;
2019 case MOV:
2020 mov_alloc(current,i);
2021 break;
2022 case COP0:
2023 cop0_alloc(current,i);
2024 break;
2025 case COP1:
b9b61529 2026 case COP2:
57871462 2027 cop1_alloc(current,i);
2028 break;
2029 case C1LS:
2030 c1ls_alloc(current,i);
2031 break;
b9b61529 2032 case C2LS:
2033 c2ls_alloc(current,i);
2034 break;
57871462 2035 case FCONV:
2036 fconv_alloc(current,i);
2037 break;
2038 case FLOAT:
2039 float_alloc(current,i);
2040 break;
2041 case FCOMP:
2042 fcomp_alloc(current,i);
2043 break;
b9b61529 2044 case C2OP:
2045 c2op_alloc(current,i);
2046 break;
57871462 2047 }
2048}
2049
2050// Special case where a branch and delay slot span two pages in virtual memory
2051static void pagespan_alloc(struct regstat *current,int i)
2052{
2053 current->isconst=0;
2054 current->wasconst=0;
2055 regs[i].wasconst=0;
e1190b87 2056 minimum_free_regs[i]=HOST_REGS;
57871462 2057 alloc_all(current,i);
2058 alloc_cc(current,i);
2059 dirty_reg(current,CCREG);
2060 if(opcode[i]==3) // JAL
2061 {
2062 alloc_reg(current,i,31);
2063 dirty_reg(current,31);
2064 }
2065 if(opcode[i]==0&&(opcode2[i]&0x3E)==8) // JR/JALR
2066 {
2067 alloc_reg(current,i,rs1[i]);
5067f341 2068 if (rt1[i]!=0) {
2069 alloc_reg(current,i,rt1[i]);
2070 dirty_reg(current,rt1[i]);
57871462 2071 }
2072 }
2073 if((opcode[i]&0x2E)==4) // BEQ/BNE/BEQL/BNEL
2074 {
2075 if(rs1[i]) alloc_reg(current,i,rs1[i]);
2076 if(rs2[i]) alloc_reg(current,i,rs2[i]);
2077 if(!((current->is32>>rs1[i])&(current->is32>>rs2[i])&1))
2078 {
2079 if(rs1[i]) alloc_reg64(current,i,rs1[i]);
2080 if(rs2[i]) alloc_reg64(current,i,rs2[i]);
2081 }
2082 }
2083 else
2084 if((opcode[i]&0x2E)==6) // BLEZ/BGTZ/BLEZL/BGTZL
2085 {
2086 if(rs1[i]) alloc_reg(current,i,rs1[i]);
2087 if(!((current->is32>>rs1[i])&1))
2088 {
2089 if(rs1[i]) alloc_reg64(current,i,rs1[i]);
2090 }
2091 }
2092 else
2093 if(opcode[i]==0x11) // BC1
2094 {
2095 alloc_reg(current,i,FSREG);
2096 alloc_reg(current,i,CSREG);
2097 }
2098 //else ...
2099}
2100
2101add_stub(int type,int addr,int retaddr,int a,int b,int c,int d,int e)
2102{
2103 stubs[stubcount][0]=type;
2104 stubs[stubcount][1]=addr;
2105 stubs[stubcount][2]=retaddr;
2106 stubs[stubcount][3]=a;
2107 stubs[stubcount][4]=b;
2108 stubs[stubcount][5]=c;
2109 stubs[stubcount][6]=d;
2110 stubs[stubcount][7]=e;
2111 stubcount++;
2112}
2113
2114// Write out a single register
2115void wb_register(signed char r,signed char regmap[],uint64_t dirty,uint64_t is32)
2116{
2117 int hr;
2118 for(hr=0;hr<HOST_REGS;hr++) {
2119 if(hr!=EXCLUDE_REG) {
2120 if((regmap[hr]&63)==r) {
2121 if((dirty>>hr)&1) {
2122 if(regmap[hr]<64) {
2123 emit_storereg(r,hr);
24385cae 2124#ifndef FORCE32
57871462 2125 if((is32>>regmap[hr])&1) {
2126 emit_sarimm(hr,31,hr);
2127 emit_storereg(r|64,hr);
2128 }
24385cae 2129#endif
57871462 2130 }else{
2131 emit_storereg(r|64,hr);
2132 }
2133 }
2134 }
2135 }
2136 }
2137}
2138
2139int mchecksum()
2140{
2141 //if(!tracedebug) return 0;
2142 int i;
2143 int sum=0;
2144 for(i=0;i<2097152;i++) {
2145 unsigned int temp=sum;
2146 sum<<=1;
2147 sum|=(~temp)>>31;
2148 sum^=((u_int *)rdram)[i];
2149 }
2150 return sum;
2151}
2152int rchecksum()
2153{
2154 int i;
2155 int sum=0;
2156 for(i=0;i<64;i++)
2157 sum^=((u_int *)reg)[i];
2158 return sum;
2159}
57871462 2160void rlist()
2161{
2162 int i;
2163 printf("TRACE: ");
2164 for(i=0;i<32;i++)
2165 printf("r%d:%8x%8x ",i,((int *)(reg+i))[1],((int *)(reg+i))[0]);
2166 printf("\n");
3d624f89 2167#ifndef DISABLE_COP1
57871462 2168 printf("TRACE: ");
2169 for(i=0;i<32;i++)
2170 printf("f%d:%8x%8x ",i,((int*)reg_cop1_simple[i])[1],*((int*)reg_cop1_simple[i]));
2171 printf("\n");
3d624f89 2172#endif
57871462 2173}
2174
2175void enabletrace()
2176{
2177 tracedebug=1;
2178}
2179
2180void memdebug(int i)
2181{
2182 //printf("TRACE: count=%d next=%d (checksum %x) lo=%8x%8x\n",Count,next_interupt,mchecksum(),(int)(reg[LOREG]>>32),(int)reg[LOREG]);
2183 //printf("TRACE: count=%d next=%d (rchecksum %x)\n",Count,next_interupt,rchecksum());
2184 //rlist();
2185 //if(tracedebug) {
2186 //if(Count>=-2084597794) {
2187 if((signed int)Count>=-2084597794&&(signed int)Count<0) {
2188 //if(0) {
2189 printf("TRACE: count=%d next=%d (checksum %x)\n",Count,next_interupt,mchecksum());
2190 //printf("TRACE: count=%d next=%d (checksum %x) Status=%x\n",Count,next_interupt,mchecksum(),Status);
2191 //printf("TRACE: count=%d next=%d (checksum %x) hi=%8x%8x\n",Count,next_interupt,mchecksum(),(int)(reg[HIREG]>>32),(int)reg[HIREG]);
2192 rlist();
2193 #ifdef __i386__
2194 printf("TRACE: %x\n",(&i)[-1]);
2195 #endif
2196 #ifdef __arm__
2197 int j;
2198 printf("TRACE: %x \n",(&j)[10]);
2199 printf("TRACE: %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x\n",(&j)[1],(&j)[2],(&j)[3],(&j)[4],(&j)[5],(&j)[6],(&j)[7],(&j)[8],(&j)[9],(&j)[10],(&j)[11],(&j)[12],(&j)[13],(&j)[14],(&j)[15],(&j)[16],(&j)[17],(&j)[18],(&j)[19],(&j)[20]);
2200 #endif
2201 //fflush(stdout);
2202 }
2203 //printf("TRACE: %x\n",(&i)[-1]);
2204}
2205
2206void tlb_debug(u_int cause, u_int addr, u_int iaddr)
2207{
2208 printf("TLB Exception: instruction=%x addr=%x cause=%x\n",iaddr, addr, cause);
2209}
2210
2211void alu_assemble(int i,struct regstat *i_regs)
2212{
2213 if(opcode2[i]>=0x20&&opcode2[i]<=0x23) { // ADD/ADDU/SUB/SUBU
2214 if(rt1[i]) {
2215 signed char s1,s2,t;
2216 t=get_reg(i_regs->regmap,rt1[i]);
2217 if(t>=0) {
2218 s1=get_reg(i_regs->regmap,rs1[i]);
2219 s2=get_reg(i_regs->regmap,rs2[i]);
2220 if(rs1[i]&&rs2[i]) {
2221 assert(s1>=0);
2222 assert(s2>=0);
2223 if(opcode2[i]&2) emit_sub(s1,s2,t);
2224 else emit_add(s1,s2,t);
2225 }
2226 else if(rs1[i]) {
2227 if(s1>=0) emit_mov(s1,t);
2228 else emit_loadreg(rs1[i],t);
2229 }
2230 else if(rs2[i]) {
2231 if(s2>=0) {
2232 if(opcode2[i]&2) emit_neg(s2,t);
2233 else emit_mov(s2,t);
2234 }
2235 else {
2236 emit_loadreg(rs2[i],t);
2237 if(opcode2[i]&2) emit_neg(t,t);
2238 }
2239 }
2240 else emit_zeroreg(t);
2241 }
2242 }
2243 }
2244 if(opcode2[i]>=0x2c&&opcode2[i]<=0x2f) { // DADD/DADDU/DSUB/DSUBU
2245 if(rt1[i]) {
2246 signed char s1l,s2l,s1h,s2h,tl,th;
2247 tl=get_reg(i_regs->regmap,rt1[i]);
2248 th=get_reg(i_regs->regmap,rt1[i]|64);
2249 if(tl>=0) {
2250 s1l=get_reg(i_regs->regmap,rs1[i]);
2251 s2l=get_reg(i_regs->regmap,rs2[i]);
2252 s1h=get_reg(i_regs->regmap,rs1[i]|64);
2253 s2h=get_reg(i_regs->regmap,rs2[i]|64);
2254 if(rs1[i]&&rs2[i]) {
2255 assert(s1l>=0);
2256 assert(s2l>=0);
2257 if(opcode2[i]&2) emit_subs(s1l,s2l,tl);
2258 else emit_adds(s1l,s2l,tl);
2259 if(th>=0) {
2260 #ifdef INVERTED_CARRY
2261 if(opcode2[i]&2) {if(s1h!=th) emit_mov(s1h,th);emit_sbb(th,s2h);}
2262 #else
2263 if(opcode2[i]&2) emit_sbc(s1h,s2h,th);
2264 #endif
2265 else emit_add(s1h,s2h,th);
2266 }
2267 }
2268 else if(rs1[i]) {
2269 if(s1l>=0) emit_mov(s1l,tl);
2270 else emit_loadreg(rs1[i],tl);
2271 if(th>=0) {
2272 if(s1h>=0) emit_mov(s1h,th);
2273 else emit_loadreg(rs1[i]|64,th);
2274 }
2275 }
2276 else if(rs2[i]) {
2277 if(s2l>=0) {
2278 if(opcode2[i]&2) emit_negs(s2l,tl);
2279 else emit_mov(s2l,tl);
2280 }
2281 else {
2282 emit_loadreg(rs2[i],tl);
2283 if(opcode2[i]&2) emit_negs(tl,tl);
2284 }
2285 if(th>=0) {
2286 #ifdef INVERTED_CARRY
2287 if(s2h>=0) emit_mov(s2h,th);
2288 else emit_loadreg(rs2[i]|64,th);
2289 if(opcode2[i]&2) {
2290 emit_adcimm(-1,th); // x86 has inverted carry flag
2291 emit_not(th,th);
2292 }
2293 #else
2294 if(opcode2[i]&2) {
2295 if(s2h>=0) emit_rscimm(s2h,0,th);
2296 else {
2297 emit_loadreg(rs2[i]|64,th);
2298 emit_rscimm(th,0,th);
2299 }
2300 }else{
2301 if(s2h>=0) emit_mov(s2h,th);
2302 else emit_loadreg(rs2[i]|64,th);
2303 }
2304 #endif
2305 }
2306 }
2307 else {
2308 emit_zeroreg(tl);
2309 if(th>=0) emit_zeroreg(th);
2310 }
2311 }
2312 }
2313 }
2314 if(opcode2[i]==0x2a||opcode2[i]==0x2b) { // SLT/SLTU
2315 if(rt1[i]) {
2316 signed char s1l,s1h,s2l,s2h,t;
2317 if(!((i_regs->was32>>rs1[i])&(i_regs->was32>>rs2[i])&1))
2318 {
2319 t=get_reg(i_regs->regmap,rt1[i]);
2320 //assert(t>=0);
2321 if(t>=0) {
2322 s1l=get_reg(i_regs->regmap,rs1[i]);
2323 s1h=get_reg(i_regs->regmap,rs1[i]|64);
2324 s2l=get_reg(i_regs->regmap,rs2[i]);
2325 s2h=get_reg(i_regs->regmap,rs2[i]|64);
2326 if(rs2[i]==0) // rx<r0
2327 {
2328 assert(s1h>=0);
2329 if(opcode2[i]==0x2a) // SLT
2330 emit_shrimm(s1h,31,t);
2331 else // SLTU (unsigned can not be less than zero)
2332 emit_zeroreg(t);
2333 }
2334 else if(rs1[i]==0) // r0<rx
2335 {
2336 assert(s2h>=0);
2337 if(opcode2[i]==0x2a) // SLT
2338 emit_set_gz64_32(s2h,s2l,t);
2339 else // SLTU (set if not zero)
2340 emit_set_nz64_32(s2h,s2l,t);
2341 }
2342 else {
2343 assert(s1l>=0);assert(s1h>=0);
2344 assert(s2l>=0);assert(s2h>=0);
2345 if(opcode2[i]==0x2a) // SLT
2346 emit_set_if_less64_32(s1h,s1l,s2h,s2l,t);
2347 else // SLTU
2348 emit_set_if_carry64_32(s1h,s1l,s2h,s2l,t);
2349 }
2350 }
2351 } else {
2352 t=get_reg(i_regs->regmap,rt1[i]);
2353 //assert(t>=0);
2354 if(t>=0) {
2355 s1l=get_reg(i_regs->regmap,rs1[i]);
2356 s2l=get_reg(i_regs->regmap,rs2[i]);
2357 if(rs2[i]==0) // rx<r0
2358 {
2359 assert(s1l>=0);
2360 if(opcode2[i]==0x2a) // SLT
2361 emit_shrimm(s1l,31,t);
2362 else // SLTU (unsigned can not be less than zero)
2363 emit_zeroreg(t);
2364 }
2365 else if(rs1[i]==0) // r0<rx
2366 {
2367 assert(s2l>=0);
2368 if(opcode2[i]==0x2a) // SLT
2369 emit_set_gz32(s2l,t);
2370 else // SLTU (set if not zero)
2371 emit_set_nz32(s2l,t);
2372 }
2373 else{
2374 assert(s1l>=0);assert(s2l>=0);
2375 if(opcode2[i]==0x2a) // SLT
2376 emit_set_if_less32(s1l,s2l,t);
2377 else // SLTU
2378 emit_set_if_carry32(s1l,s2l,t);
2379 }
2380 }
2381 }
2382 }
2383 }
2384 if(opcode2[i]>=0x24&&opcode2[i]<=0x27) { // AND/OR/XOR/NOR
2385 if(rt1[i]) {
2386 signed char s1l,s1h,s2l,s2h,th,tl;
2387 tl=get_reg(i_regs->regmap,rt1[i]);
2388 th=get_reg(i_regs->regmap,rt1[i]|64);
2389 if(!((i_regs->was32>>rs1[i])&(i_regs->was32>>rs2[i])&1)&&th>=0)
2390 {
2391 assert(tl>=0);
2392 if(tl>=0) {
2393 s1l=get_reg(i_regs->regmap,rs1[i]);
2394 s1h=get_reg(i_regs->regmap,rs1[i]|64);
2395 s2l=get_reg(i_regs->regmap,rs2[i]);
2396 s2h=get_reg(i_regs->regmap,rs2[i]|64);
2397 if(rs1[i]&&rs2[i]) {
2398 assert(s1l>=0);assert(s1h>=0);
2399 assert(s2l>=0);assert(s2h>=0);
2400 if(opcode2[i]==0x24) { // AND
2401 emit_and(s1l,s2l,tl);
2402 emit_and(s1h,s2h,th);
2403 } else
2404 if(opcode2[i]==0x25) { // OR
2405 emit_or(s1l,s2l,tl);
2406 emit_or(s1h,s2h,th);
2407 } else
2408 if(opcode2[i]==0x26) { // XOR
2409 emit_xor(s1l,s2l,tl);
2410 emit_xor(s1h,s2h,th);
2411 } else
2412 if(opcode2[i]==0x27) { // NOR
2413 emit_or(s1l,s2l,tl);
2414 emit_or(s1h,s2h,th);
2415 emit_not(tl,tl);
2416 emit_not(th,th);
2417 }
2418 }
2419 else
2420 {
2421 if(opcode2[i]==0x24) { // AND
2422 emit_zeroreg(tl);
2423 emit_zeroreg(th);
2424 } else
2425 if(opcode2[i]==0x25||opcode2[i]==0x26) { // OR/XOR
2426 if(rs1[i]){
2427 if(s1l>=0) emit_mov(s1l,tl);
2428 else emit_loadreg(rs1[i],tl);
2429 if(s1h>=0) emit_mov(s1h,th);
2430 else emit_loadreg(rs1[i]|64,th);
2431 }
2432 else
2433 if(rs2[i]){
2434 if(s2l>=0) emit_mov(s2l,tl);
2435 else emit_loadreg(rs2[i],tl);
2436 if(s2h>=0) emit_mov(s2h,th);
2437 else emit_loadreg(rs2[i]|64,th);
2438 }
2439 else{
2440 emit_zeroreg(tl);
2441 emit_zeroreg(th);
2442 }
2443 } else
2444 if(opcode2[i]==0x27) { // NOR
2445 if(rs1[i]){
2446 if(s1l>=0) emit_not(s1l,tl);
2447 else{
2448 emit_loadreg(rs1[i],tl);
2449 emit_not(tl,tl);
2450 }
2451 if(s1h>=0) emit_not(s1h,th);
2452 else{
2453 emit_loadreg(rs1[i]|64,th);
2454 emit_not(th,th);
2455 }
2456 }
2457 else
2458 if(rs2[i]){
2459 if(s2l>=0) emit_not(s2l,tl);
2460 else{
2461 emit_loadreg(rs2[i],tl);
2462 emit_not(tl,tl);
2463 }
2464 if(s2h>=0) emit_not(s2h,th);
2465 else{
2466 emit_loadreg(rs2[i]|64,th);
2467 emit_not(th,th);
2468 }
2469 }
2470 else {
2471 emit_movimm(-1,tl);
2472 emit_movimm(-1,th);
2473 }
2474 }
2475 }
2476 }
2477 }
2478 else
2479 {
2480 // 32 bit
2481 if(tl>=0) {
2482 s1l=get_reg(i_regs->regmap,rs1[i]);
2483 s2l=get_reg(i_regs->regmap,rs2[i]);
2484 if(rs1[i]&&rs2[i]) {
2485 assert(s1l>=0);
2486 assert(s2l>=0);
2487 if(opcode2[i]==0x24) { // AND
2488 emit_and(s1l,s2l,tl);
2489 } else
2490 if(opcode2[i]==0x25) { // OR
2491 emit_or(s1l,s2l,tl);
2492 } else
2493 if(opcode2[i]==0x26) { // XOR
2494 emit_xor(s1l,s2l,tl);
2495 } else
2496 if(opcode2[i]==0x27) { // NOR
2497 emit_or(s1l,s2l,tl);
2498 emit_not(tl,tl);
2499 }
2500 }
2501 else
2502 {
2503 if(opcode2[i]==0x24) { // AND
2504 emit_zeroreg(tl);
2505 } else
2506 if(opcode2[i]==0x25||opcode2[i]==0x26) { // OR/XOR
2507 if(rs1[i]){
2508 if(s1l>=0) emit_mov(s1l,tl);
2509 else emit_loadreg(rs1[i],tl); // CHECK: regmap_entry?
2510 }
2511 else
2512 if(rs2[i]){
2513 if(s2l>=0) emit_mov(s2l,tl);
2514 else emit_loadreg(rs2[i],tl); // CHECK: regmap_entry?
2515 }
2516 else emit_zeroreg(tl);
2517 } else
2518 if(opcode2[i]==0x27) { // NOR
2519 if(rs1[i]){
2520 if(s1l>=0) emit_not(s1l,tl);
2521 else {
2522 emit_loadreg(rs1[i],tl);
2523 emit_not(tl,tl);
2524 }
2525 }
2526 else
2527 if(rs2[i]){
2528 if(s2l>=0) emit_not(s2l,tl);
2529 else {
2530 emit_loadreg(rs2[i],tl);
2531 emit_not(tl,tl);
2532 }
2533 }
2534 else emit_movimm(-1,tl);
2535 }
2536 }
2537 }
2538 }
2539 }
2540 }
2541}
2542
2543void imm16_assemble(int i,struct regstat *i_regs)
2544{
2545 if (opcode[i]==0x0f) { // LUI
2546 if(rt1[i]) {
2547 signed char t;
2548 t=get_reg(i_regs->regmap,rt1[i]);
2549 //assert(t>=0);
2550 if(t>=0) {
2551 if(!((i_regs->isconst>>t)&1))
2552 emit_movimm(imm[i]<<16,t);
2553 }
2554 }
2555 }
2556 if(opcode[i]==0x08||opcode[i]==0x09) { // ADDI/ADDIU
2557 if(rt1[i]) {
2558 signed char s,t;
2559 t=get_reg(i_regs->regmap,rt1[i]);
2560 s=get_reg(i_regs->regmap,rs1[i]);
2561 if(rs1[i]) {
2562 //assert(t>=0);
2563 //assert(s>=0);
2564 if(t>=0) {
2565 if(!((i_regs->isconst>>t)&1)) {
2566 if(s<0) {
2567 if(i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2568 emit_addimm(t,imm[i],t);
2569 }else{
2570 if(!((i_regs->wasconst>>s)&1))
2571 emit_addimm(s,imm[i],t);
2572 else
2573 emit_movimm(constmap[i][s]+imm[i],t);
2574 }
2575 }
2576 }
2577 } else {
2578 if(t>=0) {
2579 if(!((i_regs->isconst>>t)&1))
2580 emit_movimm(imm[i],t);
2581 }
2582 }
2583 }
2584 }
2585 if(opcode[i]==0x18||opcode[i]==0x19) { // DADDI/DADDIU
2586 if(rt1[i]) {
2587 signed char sh,sl,th,tl;
2588 th=get_reg(i_regs->regmap,rt1[i]|64);
2589 tl=get_reg(i_regs->regmap,rt1[i]);
2590 sh=get_reg(i_regs->regmap,rs1[i]|64);
2591 sl=get_reg(i_regs->regmap,rs1[i]);
2592 if(tl>=0) {
2593 if(rs1[i]) {
2594 assert(sh>=0);
2595 assert(sl>=0);
2596 if(th>=0) {
2597 emit_addimm64_32(sh,sl,imm[i],th,tl);
2598 }
2599 else {
2600 emit_addimm(sl,imm[i],tl);
2601 }
2602 } else {
2603 emit_movimm(imm[i],tl);
2604 if(th>=0) emit_movimm(((signed int)imm[i])>>31,th);
2605 }
2606 }
2607 }
2608 }
2609 else if(opcode[i]==0x0a||opcode[i]==0x0b) { // SLTI/SLTIU
2610 if(rt1[i]) {
2611 //assert(rs1[i]!=0); // r0 might be valid, but it's probably a bug
2612 signed char sh,sl,t;
2613 t=get_reg(i_regs->regmap,rt1[i]);
2614 sh=get_reg(i_regs->regmap,rs1[i]|64);
2615 sl=get_reg(i_regs->regmap,rs1[i]);
2616 //assert(t>=0);
2617 if(t>=0) {
2618 if(rs1[i]>0) {
2619 if(sh<0) assert((i_regs->was32>>rs1[i])&1);
2620 if(sh<0||((i_regs->was32>>rs1[i])&1)) {
2621 if(opcode[i]==0x0a) { // SLTI
2622 if(sl<0) {
2623 if(i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2624 emit_slti32(t,imm[i],t);
2625 }else{
2626 emit_slti32(sl,imm[i],t);
2627 }
2628 }
2629 else { // SLTIU
2630 if(sl<0) {
2631 if(i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2632 emit_sltiu32(t,imm[i],t);
2633 }else{
2634 emit_sltiu32(sl,imm[i],t);
2635 }
2636 }
2637 }else{ // 64-bit
2638 assert(sl>=0);
2639 if(opcode[i]==0x0a) // SLTI
2640 emit_slti64_32(sh,sl,imm[i],t);
2641 else // SLTIU
2642 emit_sltiu64_32(sh,sl,imm[i],t);
2643 }
2644 }else{
2645 // SLTI(U) with r0 is just stupid,
2646 // nonetheless examples can be found
2647 if(opcode[i]==0x0a) // SLTI
2648 if(0<imm[i]) emit_movimm(1,t);
2649 else emit_zeroreg(t);
2650 else // SLTIU
2651 {
2652 if(imm[i]) emit_movimm(1,t);
2653 else emit_zeroreg(t);
2654 }
2655 }
2656 }
2657 }
2658 }
2659 else if(opcode[i]>=0x0c&&opcode[i]<=0x0e) { // ANDI/ORI/XORI
2660 if(rt1[i]) {
2661 signed char sh,sl,th,tl;
2662 th=get_reg(i_regs->regmap,rt1[i]|64);
2663 tl=get_reg(i_regs->regmap,rt1[i]);
2664 sh=get_reg(i_regs->regmap,rs1[i]|64);
2665 sl=get_reg(i_regs->regmap,rs1[i]);
2666 if(tl>=0 && !((i_regs->isconst>>tl)&1)) {
2667 if(opcode[i]==0x0c) //ANDI
2668 {
2669 if(rs1[i]) {
2670 if(sl<0) {
2671 if(i_regs->regmap_entry[tl]!=rs1[i]) emit_loadreg(rs1[i],tl);
2672 emit_andimm(tl,imm[i],tl);
2673 }else{
2674 if(!((i_regs->wasconst>>sl)&1))
2675 emit_andimm(sl,imm[i],tl);
2676 else
2677 emit_movimm(constmap[i][sl]&imm[i],tl);
2678 }
2679 }
2680 else
2681 emit_zeroreg(tl);
2682 if(th>=0) emit_zeroreg(th);
2683 }
2684 else
2685 {
2686 if(rs1[i]) {
2687 if(sl<0) {
2688 if(i_regs->regmap_entry[tl]!=rs1[i]) emit_loadreg(rs1[i],tl);
2689 }
2690 if(th>=0) {
2691 if(sh<0) {
2692 emit_loadreg(rs1[i]|64,th);
2693 }else{
2694 emit_mov(sh,th);
2695 }
2696 }
2697 if(opcode[i]==0x0d) //ORI
2698 if(sl<0) {
2699 emit_orimm(tl,imm[i],tl);
2700 }else{
2701 if(!((i_regs->wasconst>>sl)&1))
2702 emit_orimm(sl,imm[i],tl);
2703 else
2704 emit_movimm(constmap[i][sl]|imm[i],tl);
2705 }
2706 if(opcode[i]==0x0e) //XORI
2707 if(sl<0) {
2708 emit_xorimm(tl,imm[i],tl);
2709 }else{
2710 if(!((i_regs->wasconst>>sl)&1))
2711 emit_xorimm(sl,imm[i],tl);
2712 else
2713 emit_movimm(constmap[i][sl]^imm[i],tl);
2714 }
2715 }
2716 else {
2717 emit_movimm(imm[i],tl);
2718 if(th>=0) emit_zeroreg(th);
2719 }
2720 }
2721 }
2722 }
2723 }
2724}
2725
2726void shiftimm_assemble(int i,struct regstat *i_regs)
2727{
2728 if(opcode2[i]<=0x3) // SLL/SRL/SRA
2729 {
2730 if(rt1[i]) {
2731 signed char s,t;
2732 t=get_reg(i_regs->regmap,rt1[i]);
2733 s=get_reg(i_regs->regmap,rs1[i]);
2734 //assert(t>=0);
dc49e339 2735 if(t>=0&&!((i_regs->isconst>>t)&1)){
57871462 2736 if(rs1[i]==0)
2737 {
2738 emit_zeroreg(t);
2739 }
2740 else
2741 {
2742 if(s<0&&i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2743 if(imm[i]) {
2744 if(opcode2[i]==0) // SLL
2745 {
2746 emit_shlimm(s<0?t:s,imm[i],t);
2747 }
2748 if(opcode2[i]==2) // SRL
2749 {
2750 emit_shrimm(s<0?t:s,imm[i],t);
2751 }
2752 if(opcode2[i]==3) // SRA
2753 {
2754 emit_sarimm(s<0?t:s,imm[i],t);
2755 }
2756 }else{
2757 // Shift by zero
2758 if(s>=0 && s!=t) emit_mov(s,t);
2759 }
2760 }
2761 }
2762 //emit_storereg(rt1[i],t); //DEBUG
2763 }
2764 }
2765 if(opcode2[i]>=0x38&&opcode2[i]<=0x3b) // DSLL/DSRL/DSRA
2766 {
2767 if(rt1[i]) {
2768 signed char sh,sl,th,tl;
2769 th=get_reg(i_regs->regmap,rt1[i]|64);
2770 tl=get_reg(i_regs->regmap,rt1[i]);
2771 sh=get_reg(i_regs->regmap,rs1[i]|64);
2772 sl=get_reg(i_regs->regmap,rs1[i]);
2773 if(tl>=0) {
2774 if(rs1[i]==0)
2775 {
2776 emit_zeroreg(tl);
2777 if(th>=0) emit_zeroreg(th);
2778 }
2779 else
2780 {
2781 assert(sl>=0);
2782 assert(sh>=0);
2783 if(imm[i]) {
2784 if(opcode2[i]==0x38) // DSLL
2785 {
2786 if(th>=0) emit_shldimm(sh,sl,imm[i],th);
2787 emit_shlimm(sl,imm[i],tl);
2788 }
2789 if(opcode2[i]==0x3a) // DSRL
2790 {
2791 emit_shrdimm(sl,sh,imm[i],tl);
2792 if(th>=0) emit_shrimm(sh,imm[i],th);
2793 }
2794 if(opcode2[i]==0x3b) // DSRA
2795 {
2796 emit_shrdimm(sl,sh,imm[i],tl);
2797 if(th>=0) emit_sarimm(sh,imm[i],th);
2798 }
2799 }else{
2800 // Shift by zero
2801 if(sl!=tl) emit_mov(sl,tl);
2802 if(th>=0&&sh!=th) emit_mov(sh,th);
2803 }
2804 }
2805 }
2806 }
2807 }
2808 if(opcode2[i]==0x3c) // DSLL32
2809 {
2810 if(rt1[i]) {
2811 signed char sl,tl,th;
2812 tl=get_reg(i_regs->regmap,rt1[i]);
2813 th=get_reg(i_regs->regmap,rt1[i]|64);
2814 sl=get_reg(i_regs->regmap,rs1[i]);
2815 if(th>=0||tl>=0){
2816 assert(tl>=0);
2817 assert(th>=0);
2818 assert(sl>=0);
2819 emit_mov(sl,th);
2820 emit_zeroreg(tl);
2821 if(imm[i]>32)
2822 {
2823 emit_shlimm(th,imm[i]&31,th);
2824 }
2825 }
2826 }
2827 }
2828 if(opcode2[i]==0x3e) // DSRL32
2829 {
2830 if(rt1[i]) {
2831 signed char sh,tl,th;
2832 tl=get_reg(i_regs->regmap,rt1[i]);
2833 th=get_reg(i_regs->regmap,rt1[i]|64);
2834 sh=get_reg(i_regs->regmap,rs1[i]|64);
2835 if(tl>=0){
2836 assert(sh>=0);
2837 emit_mov(sh,tl);
2838 if(th>=0) emit_zeroreg(th);
2839 if(imm[i]>32)
2840 {
2841 emit_shrimm(tl,imm[i]&31,tl);
2842 }
2843 }
2844 }
2845 }
2846 if(opcode2[i]==0x3f) // DSRA32
2847 {
2848 if(rt1[i]) {
2849 signed char sh,tl;
2850 tl=get_reg(i_regs->regmap,rt1[i]);
2851 sh=get_reg(i_regs->regmap,rs1[i]|64);
2852 if(tl>=0){
2853 assert(sh>=0);
2854 emit_mov(sh,tl);
2855 if(imm[i]>32)
2856 {
2857 emit_sarimm(tl,imm[i]&31,tl);
2858 }
2859 }
2860 }
2861 }
2862}
2863
2864#ifndef shift_assemble
2865void shift_assemble(int i,struct regstat *i_regs)
2866{
2867 printf("Need shift_assemble for this architecture.\n");
2868 exit(1);
2869}
2870#endif
2871
2872void load_assemble(int i,struct regstat *i_regs)
2873{
2874 int s,th,tl,addr,map=-1;
2875 int offset;
2876 int jaddr=0;
5bf843dc 2877 int memtarget=0,c=0;
b1570849 2878 int fastload_reg_override=0;
57871462 2879 u_int hr,reglist=0;
2880 th=get_reg(i_regs->regmap,rt1[i]|64);
2881 tl=get_reg(i_regs->regmap,rt1[i]);
2882 s=get_reg(i_regs->regmap,rs1[i]);
2883 offset=imm[i];
2884 for(hr=0;hr<HOST_REGS;hr++) {
2885 if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
2886 }
2887 if(i_regs->regmap[HOST_CCREG]==CCREG) reglist&=~(1<<HOST_CCREG);
2888 if(s>=0) {
2889 c=(i_regs->wasconst>>s)&1;
af4ee1fe 2890 if (c) {
2891 memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
2892 if(using_tlb&&((signed int)(constmap[i][s]+offset))>=(signed int)0xC0000000) memtarget=1;
2893 }
57871462 2894 }
57871462 2895 //printf("load_assemble: c=%d\n",c);
2896 //if(c) printf("load_assemble: const=%x\n",(int)constmap[i][s]+offset);
2897 // FIXME: Even if the load is a NOP, we should check for pagefaults...
5bf843dc 2898#ifdef PCSX
f18c0f46 2899 if(tl<0&&(!c||(((u_int)constmap[i][s]+offset)>>16)==0x1f80)
2900 ||rt1[i]==0) {
5bf843dc 2901 // could be FIFO, must perform the read
f18c0f46 2902 // ||dummy read
5bf843dc 2903 assem_debug("(forced read)\n");
2904 tl=get_reg(i_regs->regmap,-1);
2905 assert(tl>=0);
5bf843dc 2906 }
f18c0f46 2907#endif
5bf843dc 2908 if(offset||s<0||c) addr=tl;
2909 else addr=s;
535d208a 2910 //if(tl<0) tl=get_reg(i_regs->regmap,-1);
2911 if(tl>=0) {
2912 //printf("load_assemble: c=%d\n",c);
2913 //if(c) printf("load_assemble: const=%x\n",(int)constmap[i][s]+offset);
2914 assert(tl>=0); // Even if the load is a NOP, we must check for pagefaults and I/O
2915 reglist&=~(1<<tl);
2916 if(th>=0) reglist&=~(1<<th);
2917 if(!using_tlb) {
2918 if(!c) {
2919 #ifdef RAM_OFFSET
2920 map=get_reg(i_regs->regmap,ROREG);
2921 if(map<0) emit_loadreg(ROREG,map=HOST_TEMPREG);
2922 #endif
57871462 2923//#define R29_HACK 1
535d208a 2924 #ifdef R29_HACK
2925 // Strmnnrmn's speed hack
2926 if(rs1[i]!=29||start<0x80001000||start>=0x80000000+RAM_SIZE)
2927 #endif
2928 {
ffb0b9e0 2929 jaddr=emit_fastpath_cmp_jump(i,addr,&fastload_reg_override);
57871462 2930 }
535d208a 2931 }
a327ad27 2932 else if(ram_offset&&memtarget) {
2933 emit_addimm(addr,ram_offset,HOST_TEMPREG);
2934 fastload_reg_override=HOST_TEMPREG;
2935 }
535d208a 2936 }else{ // using tlb
2937 int x=0;
2938 if (opcode[i]==0x20||opcode[i]==0x24) x=3; // LB/LBU
2939 if (opcode[i]==0x21||opcode[i]==0x25) x=2; // LH/LHU
2940 map=get_reg(i_regs->regmap,TLREG);
2941 assert(map>=0);
ea3d2e6e 2942 reglist&=~(1<<map);
535d208a 2943 map=do_tlb_r(addr,tl,map,x,-1,-1,c,constmap[i][s]+offset);
2944 do_tlb_r_branch(map,c,constmap[i][s]+offset,&jaddr);
2945 }
2946 int dummy=(rt1[i]==0)||(tl!=get_reg(i_regs->regmap,rt1[i])); // ignore loads to r0 and unneeded reg
2947 if (opcode[i]==0x20) { // LB
2948 if(!c||memtarget) {
2949 if(!dummy) {
57871462 2950 #ifdef HOST_IMM_ADDR32
2951 if(c)
2952 emit_movsbl_tlb((constmap[i][s]+offset)^3,map,tl);
2953 else
2954 #endif
2955 {
2956 //emit_xorimm(addr,3,tl);
2957 //gen_tlb_addr_r(tl,map);
2958 //emit_movsbl_indexed((int)rdram-0x80000000,tl,tl);
535d208a 2959 int x=0,a=tl;
2002a1db 2960#ifdef BIG_ENDIAN_MIPS
57871462 2961 if(!c) emit_xorimm(addr,3,tl);
2962 else x=((constmap[i][s]+offset)^3)-(constmap[i][s]+offset);
2002a1db 2963#else
535d208a 2964 if(!c) a=addr;
dadf55f2 2965#endif
b1570849 2966 if(fastload_reg_override) a=fastload_reg_override;
2967
535d208a 2968 emit_movsbl_indexed_tlb(x,a,map,tl);
57871462 2969 }
57871462 2970 }
535d208a 2971 if(jaddr)
2972 add_stub(LOADB_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
57871462 2973 }
535d208a 2974 else
2975 inline_readstub(LOADB_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2976 }
2977 if (opcode[i]==0x21) { // LH
2978 if(!c||memtarget) {
2979 if(!dummy) {
57871462 2980 #ifdef HOST_IMM_ADDR32
2981 if(c)
2982 emit_movswl_tlb((constmap[i][s]+offset)^2,map,tl);
2983 else
2984 #endif
2985 {
535d208a 2986 int x=0,a=tl;
2002a1db 2987#ifdef BIG_ENDIAN_MIPS
57871462 2988 if(!c) emit_xorimm(addr,2,tl);
2989 else x=((constmap[i][s]+offset)^2)-(constmap[i][s]+offset);
2002a1db 2990#else
535d208a 2991 if(!c) a=addr;
dadf55f2 2992#endif
b1570849 2993 if(fastload_reg_override) a=fastload_reg_override;
57871462 2994 //#ifdef
2995 //emit_movswl_indexed_tlb(x,tl,map,tl);
2996 //else
2997 if(map>=0) {
535d208a 2998 gen_tlb_addr_r(a,map);
2999 emit_movswl_indexed(x,a,tl);
3000 }else{
a327ad27 3001 #if 1 //def RAM_OFFSET
535d208a 3002 emit_movswl_indexed(x,a,tl);
3003 #else
3004 emit_movswl_indexed((int)rdram-0x80000000+x,a,tl);
3005 #endif
3006 }
57871462 3007 }
57871462 3008 }
535d208a 3009 if(jaddr)
3010 add_stub(LOADH_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
57871462 3011 }
535d208a 3012 else
3013 inline_readstub(LOADH_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
3014 }
3015 if (opcode[i]==0x23) { // LW
3016 if(!c||memtarget) {
3017 if(!dummy) {
dadf55f2 3018 int a=addr;
b1570849 3019 if(fastload_reg_override) a=fastload_reg_override;
57871462 3020 //emit_readword_indexed((int)rdram-0x80000000,addr,tl);
3021 #ifdef HOST_IMM_ADDR32
3022 if(c)
3023 emit_readword_tlb(constmap[i][s]+offset,map,tl);
3024 else
3025 #endif
dadf55f2 3026 emit_readword_indexed_tlb(0,a,map,tl);
57871462 3027 }
535d208a 3028 if(jaddr)
3029 add_stub(LOADW_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
57871462 3030 }
535d208a 3031 else
3032 inline_readstub(LOADW_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
3033 }
3034 if (opcode[i]==0x24) { // LBU
3035 if(!c||memtarget) {
3036 if(!dummy) {
57871462 3037 #ifdef HOST_IMM_ADDR32
3038 if(c)
3039 emit_movzbl_tlb((constmap[i][s]+offset)^3,map,tl);
3040 else
3041 #endif
3042 {
3043 //emit_xorimm(addr,3,tl);
3044 //gen_tlb_addr_r(tl,map);
3045 //emit_movzbl_indexed((int)rdram-0x80000000,tl,tl);
535d208a 3046 int x=0,a=tl;
2002a1db 3047#ifdef BIG_ENDIAN_MIPS
57871462 3048 if(!c) emit_xorimm(addr,3,tl);
3049 else x=((constmap[i][s]+offset)^3)-(constmap[i][s]+offset);
2002a1db 3050#else
535d208a 3051 if(!c) a=addr;
dadf55f2 3052#endif
b1570849 3053 if(fastload_reg_override) a=fastload_reg_override;
3054
535d208a 3055 emit_movzbl_indexed_tlb(x,a,map,tl);
57871462 3056 }
57871462 3057 }
535d208a 3058 if(jaddr)
3059 add_stub(LOADBU_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
57871462 3060 }
535d208a 3061 else
3062 inline_readstub(LOADBU_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
3063 }
3064 if (opcode[i]==0x25) { // LHU
3065 if(!c||memtarget) {
3066 if(!dummy) {
57871462 3067 #ifdef HOST_IMM_ADDR32
3068 if(c)
3069 emit_movzwl_tlb((constmap[i][s]+offset)^2,map,tl);
3070 else
3071 #endif
3072 {
535d208a 3073 int x=0,a=tl;
2002a1db 3074#ifdef BIG_ENDIAN_MIPS
57871462 3075 if(!c) emit_xorimm(addr,2,tl);
3076 else x=((constmap[i][s]+offset)^2)-(constmap[i][s]+offset);
2002a1db 3077#else
535d208a 3078 if(!c) a=addr;
dadf55f2 3079#endif
b1570849 3080 if(fastload_reg_override) a=fastload_reg_override;
57871462 3081 //#ifdef
3082 //emit_movzwl_indexed_tlb(x,tl,map,tl);
3083 //#else
3084 if(map>=0) {
535d208a 3085 gen_tlb_addr_r(a,map);
3086 emit_movzwl_indexed(x,a,tl);
3087 }else{
a327ad27 3088 #if 1 //def RAM_OFFSET
535d208a 3089 emit_movzwl_indexed(x,a,tl);
3090 #else
3091 emit_movzwl_indexed((int)rdram-0x80000000+x,a,tl);
3092 #endif
3093 }
57871462 3094 }
3095 }
535d208a 3096 if(jaddr)
3097 add_stub(LOADHU_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
57871462 3098 }
535d208a 3099 else
3100 inline_readstub(LOADHU_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
3101 }
3102 if (opcode[i]==0x27) { // LWU
3103 assert(th>=0);
3104 if(!c||memtarget) {
3105 if(!dummy) {
dadf55f2 3106 int a=addr;
b1570849 3107 if(fastload_reg_override) a=fastload_reg_override;
57871462 3108 //emit_readword_indexed((int)rdram-0x80000000,addr,tl);
3109 #ifdef HOST_IMM_ADDR32
3110 if(c)
3111 emit_readword_tlb(constmap[i][s]+offset,map,tl);
3112 else
3113 #endif
dadf55f2 3114 emit_readword_indexed_tlb(0,a,map,tl);
57871462 3115 }
535d208a 3116 if(jaddr)
3117 add_stub(LOADW_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
3118 }
3119 else {
3120 inline_readstub(LOADW_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
57871462 3121 }
535d208a 3122 emit_zeroreg(th);
3123 }
3124 if (opcode[i]==0x37) { // LD
3125 if(!c||memtarget) {
3126 if(!dummy) {
dadf55f2 3127 int a=addr;
b1570849 3128 if(fastload_reg_override) a=fastload_reg_override;
57871462 3129 //gen_tlb_addr_r(tl,map);
3130 //if(th>=0) emit_readword_indexed((int)rdram-0x80000000,addr,th);
3131 //emit_readword_indexed((int)rdram-0x7FFFFFFC,addr,tl);
3132 #ifdef HOST_IMM_ADDR32
3133 if(c)
3134 emit_readdword_tlb(constmap[i][s]+offset,map,th,tl);
3135 else
3136 #endif
dadf55f2 3137 emit_readdword_indexed_tlb(0,a,map,th,tl);
57871462 3138 }
535d208a 3139 if(jaddr)
3140 add_stub(LOADD_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
57871462 3141 }
535d208a 3142 else
3143 inline_readstub(LOADD_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
57871462 3144 }
535d208a 3145 }
3146 //emit_storereg(rt1[i],tl); // DEBUG
57871462 3147 //if(opcode[i]==0x23)
3148 //if(opcode[i]==0x24)
3149 //if(opcode[i]==0x23||opcode[i]==0x24)
3150 /*if(opcode[i]==0x21||opcode[i]==0x23||opcode[i]==0x24)
3151 {
3152 //emit_pusha();
3153 save_regs(0x100f);
3154 emit_readword((int)&last_count,ECX);
3155 #ifdef __i386__
3156 if(get_reg(i_regs->regmap,CCREG)<0)
3157 emit_loadreg(CCREG,HOST_CCREG);
3158 emit_add(HOST_CCREG,ECX,HOST_CCREG);
3159 emit_addimm(HOST_CCREG,2*ccadj[i],HOST_CCREG);
3160 emit_writeword(HOST_CCREG,(int)&Count);
3161 #endif
3162 #ifdef __arm__
3163 if(get_reg(i_regs->regmap,CCREG)<0)
3164 emit_loadreg(CCREG,0);
3165 else
3166 emit_mov(HOST_CCREG,0);
3167 emit_add(0,ECX,0);
3168 emit_addimm(0,2*ccadj[i],0);
3169 emit_writeword(0,(int)&Count);
3170 #endif
3171 emit_call((int)memdebug);
3172 //emit_popa();
3173 restore_regs(0x100f);
3174 }/**/
3175}
3176
3177#ifndef loadlr_assemble
3178void loadlr_assemble(int i,struct regstat *i_regs)
3179{
3180 printf("Need loadlr_assemble for this architecture.\n");
3181 exit(1);
3182}
3183#endif
3184
3185void store_assemble(int i,struct regstat *i_regs)
3186{
3187 int s,th,tl,map=-1;
3188 int addr,temp;
3189 int offset;
3190 int jaddr=0,jaddr2,type;
666a299d 3191 int memtarget=0,c=0;
57871462 3192 int agr=AGEN1+(i&1);
b1570849 3193 int faststore_reg_override=0;
57871462 3194 u_int hr,reglist=0;
3195 th=get_reg(i_regs->regmap,rs2[i]|64);
3196 tl=get_reg(i_regs->regmap,rs2[i]);
3197 s=get_reg(i_regs->regmap,rs1[i]);
3198 temp=get_reg(i_regs->regmap,agr);
3199 if(temp<0) temp=get_reg(i_regs->regmap,-1);
3200 offset=imm[i];
3201 if(s>=0) {
3202 c=(i_regs->wasconst>>s)&1;
af4ee1fe 3203 if(c) {
3204 memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
3205 if(using_tlb&&((signed int)(constmap[i][s]+offset))>=(signed int)0xC0000000) memtarget=1;
3206 }
57871462 3207 }
3208 assert(tl>=0);
3209 assert(temp>=0);
3210 for(hr=0;hr<HOST_REGS;hr++) {
3211 if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
3212 }
3213 if(i_regs->regmap[HOST_CCREG]==CCREG) reglist&=~(1<<HOST_CCREG);
3214 if(offset||s<0||c) addr=temp;
3215 else addr=s;
3216 if(!using_tlb) {
3217 if(!c) {
ffb0b9e0 3218 #ifndef PCSX
57871462 3219 #ifdef R29_HACK
3220 // Strmnnrmn's speed hack
4cb76aa4 3221 if(rs1[i]!=29||start<0x80001000||start>=0x80000000+RAM_SIZE)
57871462 3222 #endif
4cb76aa4 3223 emit_cmpimm(addr,RAM_SIZE);
57871462 3224 #ifdef DESTRUCTIVE_SHIFT
3225 if(s==addr) emit_mov(s,temp);
3226 #endif
3227 #ifdef R29_HACK
dadf55f2 3228 memtarget=1;
4cb76aa4 3229 if(rs1[i]!=29||start<0x80001000||start>=0x80000000+RAM_SIZE)
57871462 3230 #endif
3231 {
3232 jaddr=(int)out;
3233 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
3234 // Hint to branch predictor that the branch is unlikely to be taken
3235 if(rs1[i]>=28)
3236 emit_jno_unlikely(0);
3237 else
3238 #endif
3239 emit_jno(0);
3240 }
ffb0b9e0 3241 #else
3242 jaddr=emit_fastpath_cmp_jump(i,addr,&faststore_reg_override);
3243 #endif
57871462 3244 }
a327ad27 3245 else if(ram_offset&&memtarget) {
3246 emit_addimm(addr,ram_offset,HOST_TEMPREG);
3247 faststore_reg_override=HOST_TEMPREG;
3248 }
57871462 3249 }else{ // using tlb
3250 int x=0;
3251 if (opcode[i]==0x28) x=3; // SB
3252 if (opcode[i]==0x29) x=2; // SH
3253 map=get_reg(i_regs->regmap,TLREG);
3254 assert(map>=0);
ea3d2e6e 3255 reglist&=~(1<<map);
57871462 3256 map=do_tlb_w(addr,temp,map,x,c,constmap[i][s]+offset);
3257 do_tlb_w_branch(map,c,constmap[i][s]+offset,&jaddr);
3258 }
3259
3260 if (opcode[i]==0x28) { // SB
3261 if(!c||memtarget) {
97a238a6 3262 int x=0,a=temp;
2002a1db 3263#ifdef BIG_ENDIAN_MIPS
57871462 3264 if(!c) emit_xorimm(addr,3,temp);
3265 else x=((constmap[i][s]+offset)^3)-(constmap[i][s]+offset);
2002a1db 3266#else
97a238a6 3267 if(!c) a=addr;
dadf55f2 3268#endif
b1570849 3269 if(faststore_reg_override) a=faststore_reg_override;
57871462 3270 //gen_tlb_addr_w(temp,map);
3271 //emit_writebyte_indexed(tl,(int)rdram-0x80000000,temp);
97a238a6 3272 emit_writebyte_indexed_tlb(tl,x,a,map,a);
57871462 3273 }
3274 type=STOREB_STUB;
3275 }
3276 if (opcode[i]==0x29) { // SH
3277 if(!c||memtarget) {
97a238a6 3278 int x=0,a=temp;
2002a1db 3279#ifdef BIG_ENDIAN_MIPS
57871462