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don't crash on bad timing
[picodrive.git] / pico / pico_int.h
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cff531af 1/*\r
2 * PicoDrive - Internal Header File\r
3 * (c) Copyright Dave, 2004\r
4 * (C) notaz, 2006-2010\r
5 *\r
6 * This work is licensed under the terms of MAME license.\r
7 * See COPYING file in the top-level directory.\r
8 */\r
cc68a136 9\r
eff55556 10#ifndef PICO_INTERNAL_INCLUDED\r
11#define PICO_INTERNAL_INCLUDED\r
cc68a136 12\r
13#include <stdio.h>\r
14#include <stdlib.h>\r
15#include <string.h>\r
efcba75f 16#include "pico.h"\r
f53f286a 17#include "carthw/carthw.h"\r
cc68a136 18\r
89fa852d 19//\r
20#define USE_POLL_DETECT\r
21\r
eff55556 22#ifndef PICO_INTERNAL\r
23#define PICO_INTERNAL\r
24#endif\r
25#ifndef PICO_INTERNAL_ASM\r
26#define PICO_INTERNAL_ASM\r
27#endif\r
cc68a136 28\r
70357ce5 29// to select core, define EMU_C68K, EMU_M68K or EMU_F68K in your makefile or project\r
cc68a136 30\r
31#ifdef __cplusplus\r
32extern "C" {\r
33#endif\r
34\r
35\r
36// ----------------------- 68000 CPU -----------------------\r
37#ifdef EMU_C68K\r
d4d62665 38#include "../cpu/cyclone/Cyclone.h"\r
3aa1e148 39extern struct Cyclone PicoCpuCM68k, PicoCpuCS68k;\r
40#define SekCyclesLeftNoMCD PicoCpuCM68k.cycles // cycles left for this run\r
7336a99a 41#define SekCyclesLeft \\r
602133e1 42 (((PicoAHW&1) && (PicoOpt & POPT_EN_MCD_PSYNC)) ? (SekCycleAim-SekCycleCnt) : SekCyclesLeftNoMCD)\r
7a1f6e45 43#define SekCyclesLeftS68k \\r
602133e1 44 ((PicoOpt & POPT_EN_MCD_PSYNC) ? (SekCycleAimS68k-SekCycleCntS68k) : PicoCpuCS68k.cycles)\r
ef090115 45#define SekEndTimeslice(after) PicoCpuCM68k.cycles=after\r
07ceafdb 46#define SekEndTimesliceS68k(after) PicoCpuCS68k.cycles=after\r
3aa1e148 47#define SekPc (PicoCpuCM68k.pc-PicoCpuCM68k.membase)\r
48#define SekPcS68k (PicoCpuCS68k.pc-PicoCpuCS68k.membase)\r
d4d62665 49#define SekDar(x) (x < 8 ? PicoCpuCM68k.d[x] : PicoCpuCM68k.a[x - 8])\r
5fadfb1c 50#define SekSr CycloneGetSr(&PicoCpuCM68k)\r
3aa1e148 51#define SekSetStop(x) { PicoCpuCM68k.state_flags&=~1; if (x) { PicoCpuCM68k.state_flags|=1; PicoCpuCM68k.cycles=0; } }\r
52#define SekSetStopS68k(x) { PicoCpuCS68k.state_flags&=~1; if (x) { PicoCpuCS68k.state_flags|=1; PicoCpuCS68k.cycles=0; } }\r
ca61ee42 53#define SekIsStoppedS68k() (PicoCpuCS68k.state_flags&1)\r
03e4f2a3 54#define SekShouldInterrupt (PicoCpuCM68k.irq > (PicoCpuCM68k.srh&7))\r
b542be46 55\r
56#define SekInterrupt(i) PicoCpuCM68k.irq=i\r
5fadfb1c 57#define SekIrqLevel PicoCpuCM68k.irq\r
b542be46 58\r
03e4f2a3 59#ifdef EMU_M68K\r
60#define EMU_CORE_DEBUG\r
61#endif\r
cc68a136 62#endif\r
63\r
70357ce5 64#ifdef EMU_F68K\r
65#include "../cpu/fame/fame.h"\r
b542be46 66extern M68K_CONTEXT PicoCpuFM68k, PicoCpuFS68k;\r
3aa1e148 67#define SekCyclesLeftNoMCD PicoCpuFM68k.io_cycle_counter\r
70357ce5 68#define SekCyclesLeft \\r
602133e1 69 (((PicoAHW&1) && (PicoOpt & POPT_EN_MCD_PSYNC)) ? (SekCycleAim-SekCycleCnt) : SekCyclesLeftNoMCD)\r
70357ce5 70#define SekCyclesLeftS68k \\r
602133e1 71 ((PicoOpt & POPT_EN_MCD_PSYNC) ? (SekCycleAimS68k-SekCycleCntS68k) : PicoCpuFS68k.io_cycle_counter)\r
ef090115 72#define SekEndTimeslice(after) PicoCpuFM68k.io_cycle_counter=after\r
07ceafdb 73#define SekEndTimesliceS68k(after) PicoCpuFS68k.io_cycle_counter=after\r
03e4f2a3 74#define SekPc fm68k_get_pc(&PicoCpuFM68k)\r
75#define SekPcS68k fm68k_get_pc(&PicoCpuFS68k)\r
d4d62665 76#define SekDar(x) (x < 8 ? PicoCpuFM68k.dreg[x].D : PicoCpuFM68k.areg[x - 8].D)\r
5fadfb1c 77#define SekSr PicoCpuFM68k.sr\r
70357ce5 78#define SekSetStop(x) { \\r
03e4f2a3 79 PicoCpuFM68k.execinfo &= ~FM68K_HALTED; \\r
80 if (x) { PicoCpuFM68k.execinfo |= FM68K_HALTED; PicoCpuFM68k.io_cycle_counter = 0; } \\r
70357ce5 81}\r
82#define SekSetStopS68k(x) { \\r
03e4f2a3 83 PicoCpuFS68k.execinfo &= ~FM68K_HALTED; \\r
84 if (x) { PicoCpuFS68k.execinfo |= FM68K_HALTED; PicoCpuFS68k.io_cycle_counter = 0; } \\r
70357ce5 85}\r
ca61ee42 86#define SekIsStoppedS68k() (PicoCpuFS68k.execinfo&FM68K_HALTED)\r
03e4f2a3 87#define SekShouldInterrupt fm68k_would_interrupt()\r
b542be46 88\r
89#define SekInterrupt(irq) PicoCpuFM68k.interrupts[0]=irq\r
5fadfb1c 90#define SekIrqLevel PicoCpuFM68k.interrupts[0]\r
b542be46 91\r
03e4f2a3 92#ifdef EMU_M68K\r
93#define EMU_CORE_DEBUG\r
94#endif\r
cc68a136 95#endif\r
96\r
97#ifdef EMU_M68K\r
98#include "../cpu/musashi/m68kcpu.h"\r
3aa1e148 99extern m68ki_cpu_core PicoCpuMM68k, PicoCpuMS68k;\r
cc68a136 100#ifndef SekCyclesLeft\r
3aa1e148 101#define SekCyclesLeftNoMCD PicoCpuMM68k.cyc_remaining_cycles\r
7336a99a 102#define SekCyclesLeft \\r
602133e1 103 (((PicoAHW&1) && (PicoOpt & POPT_EN_MCD_PSYNC)) ? (SekCycleAim-SekCycleCnt) : SekCyclesLeftNoMCD)\r
7a1f6e45 104#define SekCyclesLeftS68k \\r
602133e1 105 ((PicoOpt & POPT_EN_MCD_PSYNC) ? (SekCycleAimS68k-SekCycleCntS68k) : PicoCpuMS68k.cyc_remaining_cycles)\r
ef090115 106#define SekEndTimeslice(after) SET_CYCLES(after)\r
07ceafdb 107#define SekEndTimesliceS68k(after) PicoCpuMS68k.cyc_remaining_cycles=after\r
3aa1e148 108#define SekPc m68k_get_reg(&PicoCpuMM68k, M68K_REG_PC)\r
109#define SekPcS68k m68k_get_reg(&PicoCpuMS68k, M68K_REG_PC)\r
5fadfb1c 110#define SekDar(x) PicoCpuMM68k.dar[x]\r
111#define SekSr m68k_get_reg(&PicoCpuMM68k, M68K_REG_SR)\r
7a1f6e45 112#define SekSetStop(x) { \\r
3aa1e148 113 if(x) { SET_CYCLES(0); PicoCpuMM68k.stopped=STOP_LEVEL_STOP; } \\r
114 else PicoCpuMM68k.stopped=0; \\r
7a1f6e45 115}\r
116#define SekSetStopS68k(x) { \\r
3aa1e148 117 if(x) { SET_CYCLES(0); PicoCpuMS68k.stopped=STOP_LEVEL_STOP; } \\r
118 else PicoCpuMS68k.stopped=0; \\r
7a1f6e45 119}\r
ca61ee42 120#define SekIsStoppedS68k() (PicoCpuMS68k.stopped==STOP_LEVEL_STOP)\r
03e4f2a3 121#define SekShouldInterrupt (CPU_INT_LEVEL > FLAG_INT_MASK)\r
b542be46 122\r
71de3cd9 123#define SekInterrupt(irq) { \\r
b542be46 124 void *oldcontext = m68ki_cpu_p; \\r
125 m68k_set_context(&PicoCpuMM68k); \\r
126 m68k_set_irq(irq); \\r
127 m68k_set_context(oldcontext); \\r
128}\r
5fadfb1c 129#define SekIrqLevel (PicoCpuMM68k.int_level >> 8)\r
b542be46 130\r
cc68a136 131#endif\r
ef090115 132#endif // EMU_M68K\r
cc68a136 133\r
134extern int SekCycleCnt; // cycles done in this frame\r
135extern int SekCycleAim; // cycle aim\r
136extern unsigned int SekCycleCntT; // total cycle counter, updated once per frame\r
137\r
b8cbd802 138#define SekCyclesReset() { \\r
139 SekCycleCntT+=SekCycleAim; \\r
140 SekCycleCnt-=SekCycleAim; \\r
141 SekCycleAim=0; \\r
142}\r
cc68a136 143#define SekCyclesBurn(c) SekCycleCnt+=c\r
4b9c5888 144#define SekCyclesDone() (SekCycleAim-SekCyclesLeft) // number of cycles done in this frame (can be checked anywhere)\r
cc68a136 145#define SekCyclesDoneT() (SekCycleCntT+SekCyclesDone()) // total nuber of cycles done for this rom\r
146\r
147#define SekEndRun(after) { \\r
ef090115 148 SekCycleCnt -= SekCyclesLeft - (after); \\r
149 if (SekCycleCnt < 0) SekCycleCnt = 0; \\r
150 SekEndTimeslice(after); \\r
cc68a136 151}\r
152\r
07ceafdb 153#define SekEndRunS68k(after) { \\r
154 SekCycleCntS68k -= SekCyclesLeftS68k - (after); \\r
155 if (SekCycleCntS68k < 0) SekCycleCntS68k = 0; \\r
156 SekEndTimesliceS68k(after); \\r
157}\r
158\r
cc68a136 159extern int SekCycleCntS68k;\r
160extern int SekCycleAimS68k;\r
161\r
bf5fbbb4 162#define SekCyclesResetS68k() { \\r
163 SekCycleCntS68k-=SekCycleAimS68k; \\r
164 SekCycleAimS68k=0; \\r
165}\r
7a1f6e45 166#define SekCyclesDoneS68k() (SekCycleAimS68k-SekCyclesLeftS68k)\r
cc68a136 167\r
03e4f2a3 168#ifdef EMU_CORE_DEBUG\r
99464b62 169extern int dbg_irq_level;\r
ef090115 170#undef SekEndTimeslice\r
2d0b15bb 171#undef SekCyclesBurn\r
172#undef SekEndRun\r
99464b62 173#undef SekInterrupt\r
ef090115 174#define SekEndTimeslice(c)\r
2270612a 175#define SekCyclesBurn(c) c\r
2d0b15bb 176#define SekEndRun(c)\r
99464b62 177#define SekInterrupt(irq) dbg_irq_level=irq\r
2d0b15bb 178#endif\r
cc68a136 179\r
b542be46 180// ----------------------- Z80 CPU -----------------------\r
181\r
b4db550e 182#if defined(_USE_DRZ80)\r
dca310c4 183#include "../cpu/DrZ80/drz80.h"\r
b542be46 184\r
185extern struct DrZ80 drZ80;\r
186\r
187#define z80_run(cycles) ((cycles) - DrZ80Run(&drZ80, cycles))\r
188#define z80_run_nr(cycles) DrZ80Run(&drZ80, cycles)\r
4936aac1 189#define z80_int() drZ80.Z80_IRQ = 1\r
4b9c5888 190\r
191#define z80_cyclesLeft drZ80.cycles\r
19954be1 192#define z80_pc() (drZ80.Z80PC - drZ80.Z80PC_BASE)\r
b542be46 193\r
194#elif defined(_USE_CZ80)\r
dca310c4 195#include "../cpu/cz80/cz80.h"\r
b542be46 196\r
197#define z80_run(cycles) Cz80_Exec(&CZ80, cycles)\r
198#define z80_run_nr(cycles) Cz80_Exec(&CZ80, cycles)\r
199#define z80_int() Cz80_Set_IRQ(&CZ80, 0, HOLD_LINE)\r
4b9c5888 200\r
201#define z80_cyclesLeft (CZ80.ICount - CZ80.ExtraCycles)\r
19954be1 202#define z80_pc() Cz80_Get_Reg(&CZ80, CZ80_PC)\r
b542be46 203\r
204#else\r
205\r
206#define z80_run(cycles) (cycles)\r
207#define z80_run_nr(cycles)\r
208#define z80_int()\r
b542be46 209\r
210#endif\r
211\r
b4db550e 212#define Z80_STATE_SIZE 0x60\r
213\r
4b9c5888 214extern int z80stopCycle; /* in 68k cycles */\r
215extern int z80_cycle_cnt; /* 'done' z80 cycles before z80_run() */\r
216extern int z80_cycle_aim;\r
217extern int z80_scanline;\r
218extern int z80_scanline_cycles; /* cycles done until z80_scanline */\r
219\r
220#define z80_resetCycles() \\r
221 z80_cycle_cnt = z80_cycle_aim = z80_scanline = z80_scanline_cycles = 0;\r
222\r
223#define z80_cyclesDone() \\r
224 (z80_cycle_aim - z80_cyclesLeft)\r
225\r
226#define cycles_68k_to_z80(x) ((x)*957 >> 11)\r
227\r
acd35d4c 228// ----------------------- SH2 CPU -----------------------\r
229\r
41397701 230#include "cpu/sh2/sh2.h"\r
acd35d4c 231\r
1d7a28a7 232extern SH2 sh2s[2];\r
233#define msh2 sh2s[0]\r
234#define ssh2 sh2s[1]\r
235\r
679af8a3 236#ifndef DRC_SH2\r
237# define ash2_end_run(after) if (sh2->icount > (after)) sh2->icount = after\r
238# define ash2_cycles_done() (sh2->cycles_aim - sh2->icount)\r
239#else\r
240# define ash2_end_run(after) { \\r
241 if ((sh2->sr >> 12) > (after)) \\r
242 { sh2->sr &= 0xfff; sh2->sr |= (after) << 12; } \\r
243}\r
244# define ash2_cycles_done() (sh2->cycles_aim - (sh2->sr >> 12))\r
245#endif\r
266c6afa 246\r
679af8a3 247//#define sh2_pc(c) (c) ? ssh2.ppc : msh2.ppc\r
248#define sh2_pc(c) (c) ? ssh2.pc : msh2.pc\r
4ea707e1 249#define sh2_reg(c, x) (c) ? ssh2.r[x] : msh2.r[x]\r
250#define sh2_gbr(c) (c) ? ssh2.gbr : msh2.gbr\r
251#define sh2_vbr(c) (c) ? ssh2.vbr : msh2.vbr\r
6add7875 252#define sh2_sr(c) (((c) ? ssh2.sr : msh2.sr) & 0xfff)\r
acd35d4c 253\r
83ff19ec 254#define sh2_set_gbr(c, v) \\r
255 { if (c) ssh2.gbr = v; else msh2.gbr = v; }\r
256#define sh2_set_vbr(c, v) \\r
257 { if (c) ssh2.vbr = v; else msh2.vbr = v; }\r
258\r
cc68a136 259// ---------------------------------------------------------\r
260\r
261// main oscillator clock which controls timing\r
262#define OSC_NTSC 53693100\r
b8cbd802 263#define OSC_PAL 53203424\r
cc68a136 264\r
265struct PicoVideo\r
266{\r
267 unsigned char reg[0x20];\r
b8cbd802 268 unsigned int command; // 32-bit Command\r
269 unsigned char pending; // 1 if waiting for second half of 32-bit command\r
270 unsigned char type; // Command type (v/c/vsram read/write)\r
271 unsigned short addr; // Read/Write address\r
272 int status; // Status bits\r
cc68a136 273 unsigned char pending_ints; // pending interrupts: ??VH????\r
b8cbd802 274 signed char lwrite_cnt; // VDP write count during active display line\r
9761a7d0 275 unsigned short v_counter; // V-counter\r
276 unsigned char pad[0x10];\r
cc68a136 277};\r
278\r
279struct PicoMisc\r
280{\r
281 unsigned char rotate;\r
282 unsigned char z80Run;\r
e5503e2f 283 unsigned char padTHPhase[2]; // 02 phase of gamepad TH switches\r
2aa27095 284 unsigned short scanline; // 04 0 to 261||311\r
e5503e2f 285 char dirtyPal; // 06 Is the palette dirty (1 - change @ this frame, 2 - some time before)\r
286 unsigned char hardware; // 07 Hardware value for country\r
287 unsigned char pal; // 08 1=PAL 0=NTSC\r
45f2f245 288 unsigned char sram_reg; // 09 SRAM reg. See SRR_* below\r
e5503e2f 289 unsigned short z80_bank68k; // 0a\r
be2c4208 290 unsigned short pad0;\r
291 unsigned char pad1;\r
0ace9b9a 292 unsigned char z80_reset; // 0f z80 reset held\r
e5503e2f 293 unsigned char padDelay[2]; // 10 gamepad phase time outs, so we count a delay\r
1dceadae 294 unsigned short eeprom_addr; // EEPROM address register\r
45f2f245 295 unsigned char eeprom_cycle; // EEPROM cycle number\r
1dceadae 296 unsigned char eeprom_slave; // EEPROM slave word for X24C02 and better SRAMs\r
45f2f245 297 unsigned char eeprom_status;\r
be2c4208 298 unsigned char pad2;\r
053fd9b4 299 unsigned short dma_xfers; // 18\r
45f2f245 300 unsigned char eeprom_wb[2]; // EEPROM latch/write buffer\r
053fd9b4 301 unsigned int frame_count; // 1c for movies and idle det\r
cc68a136 302};\r
303\r
b4db550e 304struct PicoMS\r
305{\r
306 unsigned char carthw[0x10];\r
307 unsigned char io_ctl;\r
308 unsigned char pad[0x4f];\r
309};\r
310\r
cc68a136 311// some assembly stuff depend on these, do not touch!\r
312struct Pico\r
313{\r
314 unsigned char ram[0x10000]; // 0x00000 scratch ram\r
200772b7 315 union { // vram is byteswapped for easier reads when drawing\r
2ec9bec5 316 unsigned short vram[0x8000]; // 0x10000\r
317 unsigned char vramb[0x4000]; // VRAM in SMS mode\r
318 };\r
cc68a136 319 unsigned char zram[0x2000]; // 0x20000 Z80 ram\r
b4db550e 320 unsigned char ioports[0x10]; // XXX: fix asm and mv\r
321 unsigned char pad[0xf0]; // unused\r
cc68a136 322 unsigned short cram[0x40]; // 0x22100\r
323 unsigned short vsram[0x40]; // 0x22180\r
324\r
325 unsigned char *rom; // 0x22200\r
326 unsigned int romsize; // 0x22204\r
327\r
328 struct PicoMisc m;\r
329 struct PicoVideo video;\r
b4db550e 330 struct PicoMS ms;\r
cc68a136 331};\r
332\r
333// sram\r
45f2f245 334#define SRR_MAPPED (1 << 0)\r
335#define SRR_READONLY (1 << 1)\r
336\r
337#define SRF_ENABLED (1 << 0)\r
338#define SRF_EEPROM (1 << 1)\r
af37bca8 339\r
cc68a136 340struct PicoSRAM\r
341{\r
4ff2d527 342 unsigned char *data; // actual data\r
343 unsigned int start; // start address in 68k address space\r
cc68a136 344 unsigned int end;\r
45f2f245 345 unsigned char flags; // 0c: SRF_*\r
1dceadae 346 unsigned char unused2;\r
cc68a136 347 unsigned char changed;\r
45f2f245 348 unsigned char eeprom_type; // eeprom type: 0: 7bit (24C01), 2: 2 addr words (X24C02+), 3: 3 addr words\r
349 unsigned char unused3;\r
1dceadae 350 unsigned char eeprom_bit_cl; // bit number for cl\r
351 unsigned char eeprom_bit_in; // bit number for in\r
352 unsigned char eeprom_bit_out; // bit number for out\r
45f2f245 353 unsigned int size;\r
cc68a136 354};\r
355\r
356// MCD\r
357#include "cd/cd_sys.h"\r
358#include "cd/LC89510.h"\r
d1df8786 359#include "cd/gfx_cd.h"\r
cc68a136 360\r
4f265db7 361struct mcd_pcm\r
362{\r
363 unsigned char control; // reg7\r
364 unsigned char enabled; // reg8\r
365 unsigned char cur_ch;\r
366 unsigned char bank;\r
367 int pad1;\r
368\r
4ff2d527 369 struct pcm_chan // 08, size 0x10\r
4f265db7 370 {\r
371 unsigned char regs[8];\r
4ff2d527 372 unsigned int addr; // .08: played sample address\r
4f265db7 373 int pad;\r
374 } ch[8];\r
375};\r
376\r
c459aefd 377struct mcd_misc\r
378{\r
379 unsigned short hint_vector;\r
380 unsigned char busreq;\r
51a902ae 381 unsigned char s68k_pend_ints;\r
ef090115 382 unsigned int state_flags; // 04: emu state: reset_pending\r
51a902ae 383 unsigned int counter75hz;\r
c9e1affc 384 unsigned int pad0;\r
4ff2d527 385 int timer_int3; // 10\r
4f265db7 386 unsigned int timer_stopwatch;\r
6cadc2da 387 unsigned char bcram_reg; // 18: battery-backed RAM cart register\r
388 unsigned char pad2;\r
389 unsigned short pad3;\r
390 int pad[9];\r
c459aefd 391};\r
392\r
cc68a136 393typedef struct\r
394{\r
4ff2d527 395 unsigned char bios[0x20000]; // 000000: 128K\r
396 union { // 020000: 512K\r
fa1e5e29 397 unsigned char prg_ram[0x80000];\r
cc68a136 398 unsigned char prg_ram_b[4][0x20000];\r
399 };\r
4ff2d527 400 union { // 0a0000: 256K\r
fa1e5e29 401 struct {\r
402 unsigned char word_ram2M[0x40000];\r
dca310c4 403 unsigned char unused0[0x20000];\r
fa1e5e29 404 };\r
405 struct {\r
dca310c4 406 unsigned char unused1[0x20000];\r
fa1e5e29 407 unsigned char word_ram1M[2][0x20000];\r
408 };\r
409 };\r
4ff2d527 410 union { // 100000: 64K\r
fa1e5e29 411 unsigned char pcm_ram[0x10000];\r
4f265db7 412 unsigned char pcm_ram_b[0x10][0x1000];\r
413 };\r
4ff2d527 414 unsigned char s68k_regs[0x200]; // 110000: GA, not CPU regs\r
415 unsigned char bram[0x2000]; // 110200: 8K\r
416 struct mcd_misc m; // 112200: misc\r
417 struct mcd_pcm pcm; // 112240:\r
75736070 418 _scd_toc TOC; // not to be saved\r
cc68a136 419 CDD cdd;\r
420 CDC cdc;\r
421 _scd scd;\r
d1df8786 422 Rot_Comp rot_comp;\r
cc68a136 423} mcd_state;\r
424\r
be2c4208 425// XXX: this will need to be reworked for cart+cd support.\r
cc68a136 426#define Pico_mcd ((mcd_state *)Pico.rom)\r
427\r
be2c4208 428// 32X\r
acd35d4c 429#define P32XS_FM (1<<15)\r
83ff19ec 430#define P32XS_REN (1<< 7)\r
431#define P32XS_nRES (1<< 1)\r
432#define P32XS_ADEN (1<< 0)\r
acd35d4c 433#define P32XS2_ADEN (1<< 9)\r
5e128c6d 434#define P32XS_FULL (1<< 7) // DREQ FIFO full\r
4ea707e1 435#define P32XS_68S (1<< 2)\r
97d3f47f 436#define P32XS_DMA (1<< 1)\r
4ea707e1 437#define P32XS_RV (1<< 0)\r
acd35d4c 438\r
5e128c6d 439#define P32XV_nPAL (1<<15) // VDP\r
acd35d4c 440#define P32XV_PRI (1<< 7)\r
4ea707e1 441#define P32XV_Mx (3<< 0) // display mode mask\r
974fdb5b 442\r
e51e5983 443#define P32XV_SFT (1<< 0)\r
444\r
acd35d4c 445#define P32XV_VBLK (1<<15)\r
446#define P32XV_HBLK (1<<14)\r
447#define P32XV_PEN (1<<13)\r
448#define P32XV_nFEN (1<< 1)\r
449#define P32XV_FS (1<< 0)\r
974fdb5b 450\r
db1d3564 451#define P32XP_FULL (1<<15) // PWM\r
452#define P32XP_EMPTY (1<<14)\r
453\r
4ea707e1 454#define P32XF_68KPOLL (1 << 0)\r
455#define P32XF_MSH2POLL (1 << 1)\r
456#define P32XF_SSH2POLL (1 << 2)\r
457#define P32XF_68KVPOLL (1 << 3)\r
458#define P32XF_MSH2VPOLL (1 << 4)\r
459#define P32XF_SSH2VPOLL (1 << 5)\r
460\r
461#define P32XI_VRES (1 << 14/2) // IRL/2\r
462#define P32XI_VINT (1 << 12/2)\r
463#define P32XI_HINT (1 << 10/2)\r
464#define P32XI_CMD (1 << 8/2)\r
465#define P32XI_PWM (1 << 6/2)\r
466\r
1d7a28a7 467// peripheral reg access\r
468#define PREG8(regs,offs) ((unsigned char *)regs)[offs ^ 3]\r
469\r
4ea707e1 470// real one is 4*2, but we use more because we don't lockstep\r
471#define DMAC_FIFO_LEN (4*4)\r
db1d3564 472#define PWM_BUFF_LEN 1024 // in one channel samples\r
266c6afa 473\r
f4bb5d6b 474#define SH2_DRCBLK_RAM_SHIFT 1\r
475#define SH2_DRCBLK_DA_SHIFT 1\r
476\r
e05b81fc 477#define SH2_WRITE_SHIFT 25\r
478\r
be2c4208 479struct Pico32x\r
480{\r
481 unsigned short regs[0x20];\r
5a681086 482 unsigned short vdp_regs[0x10]; // 0x40\r
483 unsigned short sh2_regs[3]; // 0x60\r
be2c4208 484 unsigned char pending_fb;\r
974fdb5b 485 unsigned char dirty_pal;\r
266c6afa 486 unsigned int emu_flags;\r
4ea707e1 487 unsigned char sh2irq_mask[2];\r
488 unsigned char sh2irqi[2]; // individual\r
489 unsigned int sh2irqs; // common irqs\r
490 unsigned short dmac_fifo[DMAC_FIFO_LEN];\r
491 unsigned int dmac_ptr;\r
db1d3564 492 unsigned int pwm_irq_sample_cnt;\r
b4db550e 493 unsigned int reserved[9];\r
974fdb5b 494};\r
495\r
496struct Pico32xMem\r
497{\r
498 unsigned char sdram[0x40000];\r
f4bb5d6b 499#ifdef DRC_SH2\r
500 unsigned short drcblk_ram[1 << (18 - SH2_DRCBLK_RAM_SHIFT)];\r
501#endif\r
b78efee2 502 unsigned short dram[2][0x20000/2]; // AKA fb\r
b4db550e 503 union {\r
504 unsigned char m68k_rom[0x100];\r
505 unsigned char m68k_rom_bank[0x10000]; // M68K_BANK_SIZE\r
506 };\r
b78efee2 507 unsigned char data_array[2][0x1000]; // cache in SH2s (can be used as RAM)\r
f4bb5d6b 508#ifdef DRC_SH2\r
509 unsigned short drcblk_da[2][1 << (12 - SH2_DRCBLK_DA_SHIFT)];\r
510#endif\r
acd35d4c 511 unsigned char sh2_rom_m[0x800];\r
512 unsigned char sh2_rom_s[0x400];\r
974fdb5b 513 unsigned short pal[0x100];\r
5e128c6d 514 unsigned short pal_native[0x100]; // converted to native (for renderer)\r
4ea707e1 515 unsigned int sh2_peri_regs[2][0x200/4]; // periphereal regs of SH2s\r
db1d3564 516 signed short pwm[2*PWM_BUFF_LEN]; // PWM buffer for current frame\r
be2c4208 517};\r
d49b10c2 518\r
c8d1e9b6 519// area.c\r
fad24893 520extern void (*PicoLoadStateHook)(void);\r
51a902ae 521\r
945c2fdc 522typedef struct {\r
523 int chunk;\r
524 int size;\r
525 void *ptr;\r
526} carthw_state_chunk;\r
527extern carthw_state_chunk *carthw_chunks;\r
528#define CHUNK_CARTHW 64\r
529\r
c8d1e9b6 530// cart.c\r
b4db550e 531extern int PicoCartResize(int newsize);\r
532extern void Byteswap(void *dst, const void *src, int len);\r
45f2f245 533extern void (*PicoCartMemSetup)(void);\r
e807ac75 534extern void (*PicoCartUnloadHook)(void);\r
1dceadae 535\r
c8d1e9b6 536// debug.c\r
b5e5172d 537int CM_compareRun(int cyc, int is_sub);\r
03e4f2a3 538\r
c8d1e9b6 539// draw.c\r
eff55556 540PICO_INTERNAL void PicoFrameStart(void);\r
b6d7ac70 541void PicoDrawSync(int to, int blank_last_line);\r
200772b7 542void BackFill(int reg7, int sh);\r
5a681086 543void FinalizeLine555(int sh, int line);\r
f4750ee0 544extern int (*PicoScanBegin)(unsigned int num);\r
545extern int (*PicoScanEnd)(unsigned int num);\r
b6d7ac70 546extern int DrawScanline;\r
f579f7b8 547#define MAX_LINE_SPRITES 29\r
548extern unsigned char HighLnSpr[240][3 + MAX_LINE_SPRITES];\r
5a681086 549extern void *DrawLineDestBase;\r
550extern int DrawLineDestIncrement;\r
cc68a136 551\r
c8d1e9b6 552// draw2.c\r
eff55556 553PICO_INTERNAL void PicoFrameFull();\r
cc68a136 554\r
200772b7 555// mode4.c\r
556void PicoFrameStartMode4(void);\r
557void PicoLineMode4(int line);\r
558void PicoDoHighPal555M4(void);\r
5a681086 559void PicoDrawSetOutputMode4(pdso_t which);\r
200772b7 560\r
c8d1e9b6 561// memory.c\r
eff55556 562PICO_INTERNAL void PicoMemSetup(void);\r
af37bca8 563unsigned int PicoRead8_io(unsigned int a);\r
564unsigned int PicoRead16_io(unsigned int a);\r
565void PicoWrite8_io(unsigned int a, unsigned int d);\r
566void PicoWrite16_io(unsigned int a, unsigned int d);\r
567\r
568// pico/memory.c\r
569PICO_INTERNAL void PicoMemSetupPico(void);\r
cc68a136 570\r
c8d1e9b6 571// cd/memory.c\r
eff55556 572PICO_INTERNAL void PicoMemSetupCD(void);\r
0ace9b9a 573void PicoMemStateLoaded(void);\r
cc68a136 574\r
c8d1e9b6 575// pico.c\r
cc68a136 576extern struct Pico Pico;\r
577extern struct PicoSRAM SRam;\r
5f9a0d16 578extern int PicoPadInt[2];\r
cc68a136 579extern int emustatus;\r
5e128c6d 580extern int scanlines_total;\r
f8ef8ff7 581extern void (*PicoResetHook)(void);\r
b0677887 582extern void (*PicoLineHook)(void);\r
1e6b5e39 583PICO_INTERNAL int CheckDMA(void);\r
584PICO_INTERNAL void PicoDetectRegion(void);\r
4b9c5888 585PICO_INTERNAL void PicoSyncZ80(int m68k_cycles_done);\r
cc68a136 586\r
c8d1e9b6 587// cd/pico.c\r
2aa27095 588PICO_INTERNAL void PicoInitMCD(void);\r
e5f426aa 589PICO_INTERNAL void PicoExitMCD(void);\r
1cb1584b 590PICO_INTERNAL void PicoPowerMCD(void);\r
2aa27095 591PICO_INTERNAL int PicoResetMCD(void);\r
592PICO_INTERNAL void PicoFrameMCD(void);\r
cc68a136 593\r
c8d1e9b6 594// pico/pico.c\r
2aa27095 595PICO_INTERNAL void PicoInitPico(void);\r
ed367a3f 596PICO_INTERNAL void PicoReratePico(void);\r
9037e45d 597\r
c8d1e9b6 598// pico/xpcm.c\r
ef4eb506 599PICO_INTERNAL void PicoPicoPCMUpdate(short *buffer, int length, int stereo);\r
600PICO_INTERNAL void PicoPicoPCMReset(void);\r
213c16ad 601PICO_INTERNAL void PicoPicoPCMRerate(int xpcm_rate);\r
ef4eb506 602\r
c8d1e9b6 603// sek.c\r
2aa27095 604PICO_INTERNAL void SekInit(void);\r
605PICO_INTERNAL int SekReset(void);\r
3aa1e148 606PICO_INTERNAL void SekState(int *data);\r
eff55556 607PICO_INTERNAL void SekSetRealTAS(int use_real);\r
b4db550e 608PICO_INTERNAL void SekPackCpu(unsigned char *cpu, int is_sub);\r
609PICO_INTERNAL void SekUnpackCpu(const unsigned char *cpu, int is_sub);\r
5f9a0d16 610void SekStepM68k(void);\r
053fd9b4 611void SekInitIdleDet(void);\r
612void SekFinishIdleDet(void);\r
cc68a136 613\r
c8d1e9b6 614// cd/sek.c\r
2aa27095 615PICO_INTERNAL void SekInitS68k(void);\r
616PICO_INTERNAL int SekResetS68k(void);\r
617PICO_INTERNAL int SekInterruptS68k(int irq);\r
cc68a136 618\r
7a93adeb 619// sound/sound.c\r
c9e1affc 620PICO_INTERNAL void cdda_start_play();\r
621extern short cdda_out_buffer[2*1152];\r
7a93adeb 622extern int PsndLen_exc_cnt;\r
623extern int PsndLen_exc_add;\r
48dc74f2 624extern int timer_a_next_oflow, timer_a_step; // in z80 cycles\r
625extern int timer_b_next_oflow, timer_b_step;\r
43e6eaad 626\r
627void ym2612_sync_timers(int z80_cycles, int mode_old, int mode_new);\r
d2721b08 628void ym2612_pack_state(void);\r
453d2a6e 629void ym2612_unpack_state(void);\r
4b9c5888 630\r
e53704e6 631#define TIMER_NO_OFLOW 0x70000000\r
45a1ef71 632// tA = 72 * (1024 - NA) / M\r
633#define TIMER_A_TICK_ZCYCLES 17203\r
634// tB = 1152 * (256 - NA) / M\r
635#define TIMER_B_TICK_ZCYCLES 262800 // 275251 broken, see Dai Makaimura\r
e53704e6 636\r
4b9c5888 637#define timers_cycle() \\r
e53704e6 638 if (timer_a_next_oflow > 0 && timer_a_next_oflow < TIMER_NO_OFLOW) \\r
43e6eaad 639 timer_a_next_oflow -= Pico.m.pal ? 70938*256 : 59659*256; \\r
e53704e6 640 if (timer_b_next_oflow > 0 && timer_b_next_oflow < TIMER_NO_OFLOW) \\r
43e6eaad 641 timer_b_next_oflow -= Pico.m.pal ? 70938*256 : 59659*256; \\r
642 ym2612_sync_timers(0, ym2612.OPN.ST.mode, ym2612.OPN.ST.mode);\r
4b9c5888 643\r
644#define timers_reset() \\r
e53704e6 645 timer_a_next_oflow = timer_b_next_oflow = TIMER_NO_OFLOW; \\r
48dc74f2 646 timer_a_step = TIMER_A_TICK_ZCYCLES * 1024; \\r
647 timer_b_step = TIMER_B_TICK_ZCYCLES * 256;\r
43e6eaad 648\r
7a93adeb 649\r
c8d1e9b6 650// videoport.c\r
eff55556 651PICO_INTERNAL_ASM void PicoVideoWrite(unsigned int a,unsigned short d);\r
652PICO_INTERNAL_ASM unsigned int PicoVideoRead(unsigned int a);\r
9761a7d0 653PICO_INTERNAL_ASM unsigned int PicoVideoRead8(unsigned int a);\r
5de27868 654extern int (*PicoDmaHook)(unsigned int source, int len, unsigned short **srcp, unsigned short **limitp);\r
cc68a136 655\r
c8d1e9b6 656// misc.c\r
eff55556 657PICO_INTERNAL_ASM void memcpy16(unsigned short *dest, unsigned short *src, int count);\r
658PICO_INTERNAL_ASM void memcpy16bswap(unsigned short *dest, void *src, int count);\r
659PICO_INTERNAL_ASM void memcpy32(int *dest, int *src, int count); // 32bit word count\r
660PICO_INTERNAL_ASM void memset32(int *dest, int c, int count);\r
cc68a136 661\r
45f2f245 662// eeprom.c\r
663void EEPROM_write8(unsigned int a, unsigned int d);\r
664void EEPROM_write16(unsigned int d);\r
665unsigned int EEPROM_read(void);\r
666\r
c8d1e9b6 667// z80 functionality wrappers\r
668PICO_INTERNAL void z80_init(void);\r
b4db550e 669PICO_INTERNAL void z80_pack(void *data);\r
670PICO_INTERNAL int z80_unpack(const void *data);\r
c8d1e9b6 671PICO_INTERNAL void z80_reset(void);\r
672PICO_INTERNAL void z80_exit(void);\r
c8d1e9b6 673\r
674// cd/misc.c\r
eff55556 675PICO_INTERNAL_ASM void wram_2M_to_1M(unsigned char *m);\r
676PICO_INTERNAL_ASM void wram_1M_to_2M(unsigned char *m);\r
677\r
678// cd/buffering.c\r
679PICO_INTERNAL void PicoCDBufferRead(void *dest, int lba);\r
680\r
681// sound/sound.c\r
9d917eea 682PICO_INTERNAL void PsndReset(void);\r
4b9c5888 683PICO_INTERNAL void PsndDoDAC(int line_to);\r
9d917eea 684PICO_INTERNAL void PsndClear(void);\r
7b3f44c6 685PICO_INTERNAL void PsndGetSamples(int y);\r
2ec9bec5 686PICO_INTERNAL void PsndGetSamplesMS(void);\r
4b9c5888 687extern int PsndDacLine;\r
cc68a136 688\r
3e49ffd0 689// sms.c\r
f3a57b2d 690#ifndef NO_SMS\r
3e49ffd0 691void PicoPowerMS(void);\r
2ec9bec5 692void PicoResetMS(void);\r
3e49ffd0 693void PicoMemSetupMS(void);\r
b4db550e 694void PicoStateLoadedMS(void);\r
3e49ffd0 695void PicoFrameMS(void);\r
87b0845f 696void PicoFrameDrawOnlyMS(void);\r
f3a57b2d 697#else\r
698#define PicoPowerMS()\r
699#define PicoResetMS()\r
700#define PicoMemSetupMS()\r
701#define PicoStateLoadedMS()\r
702#define PicoFrameMS()\r
703#define PicoFrameDrawOnlyMS()\r
704#endif\r
3e49ffd0 705\r
be2c4208 706// 32x/32x.c\r
f3a57b2d 707#ifndef NO_32X\r
be2c4208 708extern struct Pico32x Pico32x;\r
709void Pico32xInit(void);\r
974fdb5b 710void PicoPower32x(void);\r
be2c4208 711void PicoReset32x(void);\r
974fdb5b 712void Pico32xStartup(void);\r
5e49c3a8 713void PicoUnload32x(void);\r
974fdb5b 714void PicoFrame32x(void);\r
1f1ff763 715void p32x_update_irls(int nested_call);\r
83ff19ec 716void p32x_reset_sh2s(void);\r
be2c4208 717\r
718// 32x/memory.c\r
974fdb5b 719struct Pico32xMem *Pico32xMem;\r
be2c4208 720unsigned int PicoRead8_32x(unsigned int a);\r
721unsigned int PicoRead16_32x(unsigned int a);\r
722void PicoWrite8_32x(unsigned int a, unsigned int d);\r
723void PicoWrite16_32x(unsigned int a, unsigned int d);\r
724void PicoMemSetup32x(void);\r
974fdb5b 725void Pico32xSwapDRAM(int b);\r
b4db550e 726void Pico32xStateLoaded(void);\r
87accdf7 727void p32x_poll_event(int cpu_mask, int is_vdp);\r
974fdb5b 728\r
729// 32x/draw.c\r
730void FinalizeLine32xRGB555(int sh, int line);\r
5a681086 731void PicoDraw32xLayer(int offs, int lines, int mdbg);\r
7a961c19 732void PicoDraw32xLayerMdOnly(int offs, int lines);\r
f4750ee0 733extern int (*PicoScan32xBegin)(unsigned int num);\r
734extern int (*PicoScan32xEnd)(unsigned int num);\r
7a961c19 735enum {\r
736 PDM32X_OFF,\r
737 PDM32X_32X_ONLY,\r
738 PDM32X_BOTH,\r
739};\r
5a681086 740extern int Pico32xDrawMode;\r
be2c4208 741\r
db1d3564 742// 32x/pwm.c\r
743unsigned int p32x_pwm_read16(unsigned int a);\r
744void p32x_pwm_write16(unsigned int a, unsigned int d);\r
db1d3564 745void p32x_pwm_update(int *buf32, int length, int stereo);\r
1f1ff763 746void p32x_timers_do(int line_call);\r
1d7a28a7 747void p32x_timers_recalc(void);\r
db1d3564 748extern int pwm_frame_smp_cnt;\r
f3a57b2d 749#else\r
750#define Pico32xInit()\r
751#define PicoPower32x()\r
752#define PicoReset32x()\r
753#define PicoFrame32x()\r
754#define PicoUnload32x()\r
755#define Pico32xStateLoaded()\r
756#define PicoDraw32xSetFrameMode(...)\r
757#define FinalizeLine32xRGB555 NULL\r
758#define p32x_pwm_update(...)\r
759#define p32x_timers_recalc()\r
760#endif\r
db1d3564 761\r
45f2f245 762/* avoid dependency on newer glibc */\r
763static __inline int isspace_(int c)\r
764{\r
765 return (0x09 <= c && c <= 0x0d) || c == ' ';\r
766}\r
767\r
f4bb5d6b 768#ifndef ARRAY_SIZE\r
769#define ARRAY_SIZE(x) (sizeof(x) / sizeof(x[0]))\r
770#endif\r
771\r
b8cbd802 772// emulation event logging\r
773#ifndef EL_LOGMASK\r
774#define EL_LOGMASK 0\r
775#endif\r
776\r
017512f2 777#define EL_HVCNT 0x00000001 /* hv counter reads */\r
778#define EL_SR 0x00000002 /* SR reads */\r
779#define EL_INTS 0x00000004 /* ints and acks */\r
43e6eaad 780#define EL_YMTIMER 0x00000008 /* ym2612 timer stuff */\r
017512f2 781#define EL_INTSW 0x00000010 /* log irq switching on/off */\r
782#define EL_ASVDP 0x00000020 /* VDP accesses during active scan */\r
783#define EL_VDPDMA 0x00000040 /* VDP DMA transfers and their timing */\r
784#define EL_BUSREQ 0x00000080 /* z80 busreq r/w or reset w */\r
785#define EL_Z80BNK 0x00000100 /* z80 i/o through bank area */\r
786#define EL_SRAMIO 0x00000200 /* sram i/o */\r
787#define EL_EEPROM 0x00000400 /* eeprom debug */\r
788#define EL_UIO 0x00000800 /* unmapped i/o */\r
789#define EL_IO 0x00001000 /* all i/o */\r
790#define EL_CDPOLL 0x00002000 /* MCD: log poll detection */\r
791#define EL_SVP 0x00004000 /* SVP stuff */\r
fa22af4c 792#define EL_PICOHW 0x00008000 /* Pico stuff */\r
053fd9b4 793#define EL_IDLE 0x00010000 /* idle loop det. */\r
af37bca8 794#define EL_CDREGS 0x00020000 /* MCD: register access */\r
795#define EL_CDREG3 0x00040000 /* MCD: register 3 only */\r
be2c4208 796#define EL_32X 0x00080000\r
1b3f5844 797#define EL_PWM 0x00100000 /* 32X PWM stuff (LOTS of output) */\r
017512f2 798\r
799#define EL_STATUS 0x40000000 /* status messages */\r
800#define EL_ANOMALY 0x80000000 /* some unexpected conditions (during emulation) */\r
b8cbd802 801\r
802#if EL_LOGMASK\r
803#define elprintf(w,f,...) \\r
804{ \\r
805 if ((w) & EL_LOGMASK) \\r
7d0143a2 806 lprintf("%05i:%03i: " f "\n",Pico.m.frame_count,Pico.m.scanline,##__VA_ARGS__); \\r
b8cbd802 807}\r
dca310c4 808#elif defined(_MSC_VER)\r
809#define elprintf\r
b8cbd802 810#else\r
811#define elprintf(w,f,...)\r
812#endif\r
813\r
f6c49d38 814// profiling\r
815#ifdef PPROF\r
816#include <platform/linux/pprof.h>\r
817#else\r
818#define pprof_init()\r
819#define pprof_finish()\r
820#define pprof_start(x)\r
821#define pprof_end(...)\r
822#define pprof_end_sub(...)\r
823#endif\r
824\r
825// misc\r
dca310c4 826#ifdef _MSC_VER\r
827#define cdprintf\r
828#else\r
829#define cdprintf(x...)\r
830#endif\r
831\r
553c3eaa 832#ifdef __i386__\r
833#define REGPARM(x) __attribute__((regparm(x)))\r
c8d1e9b6 834#else\r
553c3eaa 835#define REGPARM(x)\r
c8d1e9b6 836#endif\r
837\r
5e89f0f5 838#ifdef __GNUC__\r
839#define NOINLINE __attribute__((noinline))\r
840#else\r
841#define NOINLINE\r
842#endif\r
843\r
f8af9634 844#ifdef __cplusplus\r
845} // End of extern "C"\r
846#endif\r
847\r
eff55556 848#endif // PICO_INTERNAL_INCLUDED\r
849\r
fast MegaDrive/MegaCD/32X emulator