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57871462 | 1 | /* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * |
2 | * Mupen64plus - new_dynarec.c * | |
20d507ba | 3 | * Copyright (C) 2009-2011 Ari64 * |
57871462 | 4 | * * |
5 | * This program is free software; you can redistribute it and/or modify * | |
6 | * it under the terms of the GNU General Public License as published by * | |
7 | * the Free Software Foundation; either version 2 of the License, or * | |
8 | * (at your option) any later version. * | |
9 | * * | |
10 | * This program is distributed in the hope that it will be useful, * | |
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of * | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * | |
13 | * GNU General Public License for more details. * | |
14 | * * | |
15 | * You should have received a copy of the GNU General Public License * | |
16 | * along with this program; if not, write to the * | |
17 | * Free Software Foundation, Inc., * | |
18 | * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * | |
19 | * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */ | |
20 | ||
21 | #include <stdlib.h> | |
22 | #include <stdint.h> //include for uint64_t | |
23 | #include <assert.h> | |
d848b60a | 24 | #include <errno.h> |
4600ba03 | 25 | #include <sys/mman.h> |
d148d265 | 26 | #ifdef __MACH__ |
27 | #include <libkern/OSCacheControl.h> | |
28 | #endif | |
1e212a25 | 29 | #ifdef _3DS |
30 | #include <3ds_utils.h> | |
31 | #endif | |
32 | #ifdef VITA | |
33 | #include <psp2/kernel/sysmem.h> | |
34 | static int sceBlock; | |
35 | #endif | |
57871462 | 36 | |
d148d265 | 37 | #include "new_dynarec_config.h" |
630b122b | 38 | #include "../psxhle.h" |
39 | #include "../psxinterpreter.h" | |
40 | #include "../gte.h" | |
41 | #include "emu_if.h" // emulator interface | |
42 | ||
43 | #define noinline __attribute__((noinline,noclone)) | |
44 | #ifndef ARRAY_SIZE | |
45 | #define ARRAY_SIZE(x) (sizeof(x) / sizeof(x[0])) | |
46 | #endif | |
47 | #ifndef min | |
48 | #define min(a, b) ((b) < (a) ? (b) : (a)) | |
49 | #endif | |
50 | #ifndef max | |
51 | #define max(a, b) ((b) > (a) ? (b) : (a)) | |
52 | #endif | |
57871462 | 53 | |
4600ba03 | 54 | //#define DISASM |
630b122b | 55 | //#define ASSEM_PRINT |
56 | ||
57 | #ifdef ASSEM_PRINT | |
58 | #define assem_debug printf | |
59 | #else | |
4600ba03 | 60 | #define assem_debug(...) |
630b122b | 61 | #endif |
62 | //#define inv_debug printf | |
4600ba03 | 63 | #define inv_debug(...) |
57871462 | 64 | |
65 | #ifdef __i386__ | |
630b122b | 66 | #include "assem_x86.h" |
57871462 | 67 | #endif |
68 | #ifdef __x86_64__ | |
630b122b | 69 | #include "assem_x64.h" |
57871462 | 70 | #endif |
71 | #ifdef __arm__ | |
630b122b | 72 | #include "assem_arm.h" |
57871462 | 73 | #endif |
630b122b | 74 | #ifdef __aarch64__ |
75 | #include "assem_arm64.h" | |
73081f23 FJGG |
76 | #endif |
77 | ||
630b122b | 78 | #define RAM_SIZE 0x200000 |
57871462 | 79 | #define MAXBLOCK 4096 |
80 | #define MAX_OUTPUT_BLOCK_SIZE 262144 | |
2573466a | 81 | |
630b122b | 82 | struct ndrc_mem |
83 | { | |
84 | u_char translation_cache[1 << TARGET_SIZE_2]; | |
85 | struct | |
86 | { | |
87 | struct tramp_insns ops[2048 / sizeof(struct tramp_insns)]; | |
88 | const void *f[2048 / sizeof(void *)]; | |
89 | } tramp; | |
90 | }; | |
91 | ||
92 | #ifdef BASE_ADDR_DYNAMIC | |
93 | static struct ndrc_mem *ndrc; | |
94 | #else | |
95 | static struct ndrc_mem ndrc_ __attribute__((aligned(4096))); | |
96 | static struct ndrc_mem *ndrc = &ndrc_; | |
97 | #endif | |
98 | ||
99 | // stubs | |
100 | enum stub_type { | |
101 | CC_STUB = 1, | |
102 | FP_STUB = 2, | |
103 | LOADB_STUB = 3, | |
104 | LOADH_STUB = 4, | |
105 | LOADW_STUB = 5, | |
106 | LOADD_STUB = 6, | |
107 | LOADBU_STUB = 7, | |
108 | LOADHU_STUB = 8, | |
109 | STOREB_STUB = 9, | |
110 | STOREH_STUB = 10, | |
111 | STOREW_STUB = 11, | |
112 | STORED_STUB = 12, | |
113 | STORELR_STUB = 13, | |
114 | INVCODE_STUB = 14, | |
115 | }; | |
116 | ||
57871462 | 117 | struct regstat |
118 | { | |
630b122b | 119 | signed char regmap_entry[HOST_REGS]; // pre-insn + loop preloaded regs? |
57871462 | 120 | signed char regmap[HOST_REGS]; |
57871462 | 121 | uint64_t wasdirty; |
122 | uint64_t dirty; | |
123 | uint64_t u; | |
630b122b | 124 | u_int wasconst; // before; for example 'lw r2, (r2)' wasconst is true |
125 | u_int isconst; // ... but isconst is false when r2 is known | |
8575a877 | 126 | u_int loadedconst; // host regs that have constants loaded |
127 | u_int waswritten; // MIPS regs that were used as store base before | |
57871462 | 128 | }; |
129 | ||
de5a60c3 | 130 | // note: asm depends on this layout |
57871462 | 131 | struct ll_entry |
132 | { | |
133 | u_int vaddr; | |
de5a60c3 | 134 | u_int reg_sv_flags; |
57871462 | 135 | void *addr; |
136 | struct ll_entry *next; | |
137 | }; | |
138 | ||
630b122b | 139 | struct ht_entry |
140 | { | |
141 | u_int vaddr[2]; | |
142 | void *tcaddr[2]; | |
143 | }; | |
144 | ||
145 | struct code_stub | |
146 | { | |
147 | enum stub_type type; | |
148 | void *addr; | |
149 | void *retaddr; | |
150 | u_int a; | |
151 | uintptr_t b; | |
152 | uintptr_t c; | |
153 | u_int d; | |
154 | u_int e; | |
155 | }; | |
156 | ||
157 | struct link_entry | |
158 | { | |
159 | void *addr; | |
160 | u_int target; | |
161 | u_int ext; | |
162 | }; | |
163 | ||
164 | static struct decoded_insn | |
165 | { | |
166 | u_char itype; | |
167 | u_char opcode; | |
168 | u_char opcode2; | |
169 | u_char rs1; | |
170 | u_char rs2; | |
171 | u_char rt1; | |
172 | u_char rt2; | |
173 | u_char lt1; | |
174 | u_char bt:1; | |
175 | u_char ooo:1; | |
176 | u_char is_ds:1; | |
177 | u_char is_jump:1; | |
178 | u_char is_ujump:1; | |
179 | u_char is_load:1; | |
180 | u_char is_store:1; | |
181 | } dops[MAXBLOCK]; | |
182 | ||
e2b5e7aa | 183 | // used by asm: |
184 | u_char *out; | |
630b122b | 185 | struct ht_entry hash_table[65536] __attribute__((aligned(16))); |
e2b5e7aa | 186 | struct ll_entry *jump_in[4096] __attribute__((aligned(16))); |
187 | struct ll_entry *jump_dirty[4096]; | |
188 | ||
189 | static struct ll_entry *jump_out[4096]; | |
190 | static u_int start; | |
191 | static u_int *source; | |
192 | static char insn[MAXBLOCK][10]; | |
bedfea38 | 193 | static uint64_t gte_rs[MAXBLOCK]; // gte: 32 data and 32 ctl regs |
194 | static uint64_t gte_rt[MAXBLOCK]; | |
195 | static uint64_t gte_unneeded[MAXBLOCK]; | |
ffb0b9e0 | 196 | static u_int smrv[32]; // speculated MIPS register values |
197 | static u_int smrv_strong; // mask or regs that are likely to have correct values | |
198 | static u_int smrv_weak; // same, but somewhat less likely | |
199 | static u_int smrv_strong_next; // same, but after current insn executes | |
200 | static u_int smrv_weak_next; | |
e2b5e7aa | 201 | static int imm[MAXBLOCK]; |
202 | static u_int ba[MAXBLOCK]; | |
e2b5e7aa | 203 | static uint64_t unneeded_reg[MAXBLOCK]; |
e2b5e7aa | 204 | static uint64_t branch_unneeded_reg[MAXBLOCK]; |
630b122b | 205 | // pre-instruction [i], excluding loop-preload regs? |
e2b5e7aa | 206 | static signed char regmap_pre[MAXBLOCK][HOST_REGS]; |
630b122b | 207 | // contains 'real' consts at [i] insn, but may differ from what's actually |
208 | // loaded in host reg as 'final' value is always loaded, see get_final_value() | |
209 | static uint32_t current_constmap[HOST_REGS]; | |
210 | static uint32_t constmap[MAXBLOCK][HOST_REGS]; | |
956f3129 | 211 | static struct regstat regs[MAXBLOCK]; |
212 | static struct regstat branch_regs[MAXBLOCK]; | |
e2b5e7aa | 213 | static signed char minimum_free_regs[MAXBLOCK]; |
214 | static u_int needed_reg[MAXBLOCK]; | |
215 | static u_int wont_dirty[MAXBLOCK]; | |
216 | static u_int will_dirty[MAXBLOCK]; | |
217 | static int ccadj[MAXBLOCK]; | |
218 | static int slen; | |
630b122b | 219 | static void *instr_addr[MAXBLOCK]; |
220 | static struct link_entry link_addr[MAXBLOCK]; | |
e2b5e7aa | 221 | static int linkcount; |
630b122b | 222 | static struct code_stub stubs[MAXBLOCK*3]; |
e2b5e7aa | 223 | static int stubcount; |
224 | static u_int literals[1024][2]; | |
225 | static int literalcount; | |
226 | static int is_delayslot; | |
e2b5e7aa | 227 | static char shadow[1048576] __attribute__((aligned(16))); |
228 | static void *copy; | |
229 | static int expirep; | |
230 | static u_int stop_after_jal; | |
630b122b | 231 | static u_int f1_hack; // 0 - off, ~0 - capture address, else addr |
e2b5e7aa | 232 | |
233 | int new_dynarec_hacks; | |
630b122b | 234 | int new_dynarec_hacks_pergame; |
235 | int new_dynarec_hacks_old; | |
e2b5e7aa | 236 | int new_dynarec_did_compile; |
630b122b | 237 | |
238 | #define HACK_ENABLED(x) ((new_dynarec_hacks | new_dynarec_hacks_pergame) & (x)) | |
239 | ||
240 | extern int cycle_count; // ... until end of the timeslice, counts -N -> 0 | |
241 | extern int last_count; // last absolute target, often = next_interupt | |
242 | extern int pcaddr; | |
243 | extern int pending_exception; | |
244 | extern int branch_target; | |
245 | extern uintptr_t ram_offset; | |
246 | extern uintptr_t mini_ht[32][2]; | |
57871462 | 247 | extern u_char restore_candidate[512]; |
57871462 | 248 | |
249 | /* registers that may be allocated */ | |
250 | /* 1-31 gpr */ | |
630b122b | 251 | #define LOREG 32 // lo |
252 | #define HIREG 33 // hi | |
253 | //#define FSREG 34 // FPU status (FCSR) | |
57871462 | 254 | #define CSREG 35 // Coprocessor status |
255 | #define CCREG 36 // Cycle count | |
256 | #define INVCP 37 // Pointer to invalid_code | |
1edfcc68 | 257 | //#define MMREG 38 // Pointer to memory_map |
619e5ded | 258 | #define ROREG 39 // ram offset (if rdram!=0x80000000) |
259 | #define TEMPREG 40 | |
260 | #define FTEMP 40 // FPU temporary register | |
261 | #define PTEMP 41 // Prefetch temporary register | |
1edfcc68 | 262 | //#define TLREG 42 // TLB mapping offset |
619e5ded | 263 | #define RHASH 43 // Return address hash |
264 | #define RHTBL 44 // Return address hash table address | |
265 | #define RTEMP 45 // JR/JALR address register | |
266 | #define MAXREG 45 | |
267 | #define AGEN1 46 // Address generation temporary register | |
1edfcc68 | 268 | //#define AGEN2 47 // Address generation temporary register |
269 | //#define MGEN1 48 // Maptable address generation temporary register | |
270 | //#define MGEN2 49 // Maptable address generation temporary register | |
619e5ded | 271 | #define BTREG 50 // Branch target temporary register |
57871462 | 272 | |
273 | /* instruction types */ | |
274 | #define NOP 0 // No operation | |
275 | #define LOAD 1 // Load | |
276 | #define STORE 2 // Store | |
277 | #define LOADLR 3 // Unaligned load | |
278 | #define STORELR 4 // Unaligned store | |
9f51b4b9 | 279 | #define MOV 5 // Move |
57871462 | 280 | #define ALU 6 // Arithmetic/logic |
281 | #define MULTDIV 7 // Multiply/divide | |
282 | #define SHIFT 8 // Shift by register | |
283 | #define SHIFTIMM 9// Shift by immediate | |
284 | #define IMM16 10 // 16-bit immediate | |
285 | #define RJUMP 11 // Unconditional jump to register | |
286 | #define UJUMP 12 // Unconditional jump | |
287 | #define CJUMP 13 // Conditional branch (BEQ/BNE/BGTZ/BLEZ) | |
288 | #define SJUMP 14 // Conditional branch (regimm format) | |
289 | #define COP0 15 // Coprocessor 0 | |
290 | #define COP1 16 // Coprocessor 1 | |
291 | #define C1LS 17 // Coprocessor 1 load/store | |
630b122b | 292 | //#define FJUMP 18 // Conditional branch (floating point) |
293 | //#define FLOAT 19 // Floating point unit | |
294 | //#define FCONV 20 // Convert integer to float | |
295 | //#define FCOMP 21 // Floating point compare (sets FSREG) | |
57871462 | 296 | #define SYSCALL 22// SYSCALL |
297 | #define OTHER 23 // Other | |
298 | #define SPAN 24 // Branch/delay slot spans 2 pages | |
299 | #define NI 25 // Not implemented | |
7139f3c8 | 300 | #define HLECALL 26// PCSX fake opcodes for HLE |
b9b61529 | 301 | #define COP2 27 // Coprocessor 2 move |
302 | #define C2LS 28 // Coprocessor 2 load/store | |
303 | #define C2OP 29 // Coprocessor 2 operation | |
1e973cb0 | 304 | #define INTCALL 30// Call interpreter to handle rare corner cases |
57871462 | 305 | |
57871462 | 306 | /* branch codes */ |
307 | #define TAKEN 1 | |
308 | #define NOTTAKEN 2 | |
309 | #define NULLDS 3 | |
310 | ||
630b122b | 311 | #define DJT_1 (void *)1l // no function, just a label in assem_debug log |
312 | #define DJT_2 (void *)2l | |
313 | ||
57871462 | 314 | // asm linkage |
630b122b | 315 | int new_recompile_block(u_int addr); |
57871462 | 316 | void *get_addr_ht(u_int vaddr); |
317 | void invalidate_block(u_int block); | |
318 | void invalidate_addr(u_int addr); | |
319 | void remove_hash(int vaddr); | |
57871462 | 320 | void dyna_linker(); |
321 | void dyna_linker_ds(); | |
322 | void verify_code(); | |
57871462 | 323 | void verify_code_ds(); |
324 | void cc_interrupt(); | |
325 | void fp_exception(); | |
326 | void fp_exception_ds(); | |
630b122b | 327 | void jump_to_new_pc(); |
328 | void call_gteStall(); | |
7139f3c8 | 329 | void new_dyna_leave(); |
57871462 | 330 | |
57871462 | 331 | // Needed by assembler |
630b122b | 332 | static void wb_register(signed char r, const signed char regmap[], uint64_t dirty); |
333 | static void wb_dirtys(const signed char i_regmap[], uint64_t i_dirty); | |
334 | static void wb_needed_dirtys(const signed char i_regmap[], uint64_t i_dirty, int addr); | |
335 | static void load_all_regs(const signed char i_regmap[]); | |
336 | static void load_needed_regs(const signed char i_regmap[], const signed char next_regmap[]); | |
e2b5e7aa | 337 | static void load_regs_entry(int t); |
630b122b | 338 | static void load_all_consts(const signed char regmap[], u_int dirty, int i); |
339 | static u_int get_host_reglist(const signed char *regmap); | |
e2b5e7aa | 340 | |
630b122b | 341 | static int verify_dirty(const u_int *ptr); |
e2b5e7aa | 342 | static int get_final_value(int hr, int i, int *value); |
630b122b | 343 | static void add_stub(enum stub_type type, void *addr, void *retaddr, |
344 | u_int a, uintptr_t b, uintptr_t c, u_int d, u_int e); | |
345 | static void add_stub_r(enum stub_type type, void *addr, void *retaddr, | |
346 | int i, int addr_reg, const struct regstat *i_regs, int ccadj, u_int reglist); | |
347 | static void add_to_linker(void *addr, u_int target, int ext); | |
348 | static void *emit_fastpath_cmp_jump(int i, const struct regstat *i_regs, | |
349 | int addr, int *offset_reg, int *addr_reg_override); | |
350 | static void *get_direct_memhandler(void *table, u_int addr, | |
351 | enum stub_type type, uintptr_t *addr_host); | |
352 | static void cop2_do_stall_check(u_int op, int i, const struct regstat *i_regs, u_int reglist); | |
353 | static void pass_args(int a0, int a1); | |
354 | static void emit_far_jump(const void *f); | |
355 | static void emit_far_call(const void *f); | |
57871462 | 356 | |
d148d265 | 357 | static void mprotect_w_x(void *start, void *end, int is_x) |
358 | { | |
359 | #ifdef NO_WRITE_EXEC | |
1e212a25 | 360 | #if defined(VITA) |
361 | // *Open* enables write on all memory that was | |
362 | // allocated by sceKernelAllocMemBlockForVM()? | |
363 | if (is_x) | |
364 | sceKernelCloseVMDomain(); | |
365 | else | |
366 | sceKernelOpenVMDomain(); | |
367 | #else | |
d148d265 | 368 | u_long mstart = (u_long)start & ~4095ul; |
369 | u_long mend = (u_long)end; | |
370 | if (mprotect((void *)mstart, mend - mstart, | |
371 | PROT_READ | (is_x ? PROT_EXEC : PROT_WRITE)) != 0) | |
372 | SysPrintf("mprotect(%c) failed: %s\n", is_x ? 'x' : 'w', strerror(errno)); | |
1e212a25 | 373 | #endif |
d148d265 | 374 | #endif |
375 | } | |
376 | ||
377 | static void start_tcache_write(void *start, void *end) | |
378 | { | |
379 | mprotect_w_x(start, end, 0); | |
380 | } | |
381 | ||
382 | static void end_tcache_write(void *start, void *end) | |
383 | { | |
630b122b | 384 | #if defined(__arm__) || defined(__aarch64__) |
d148d265 | 385 | size_t len = (char *)end - (char *)start; |
386 | #if defined(__BLACKBERRY_QNX__) | |
387 | msync(start, len, MS_SYNC | MS_CACHE_ONLY | MS_INVALIDATE_ICACHE); | |
388 | #elif defined(__MACH__) | |
389 | sys_cache_control(kCacheFunctionPrepareForExecution, start, len); | |
390 | #elif defined(VITA) | |
1e212a25 | 391 | sceKernelSyncVMDomain(sceBlock, start, len); |
392 | #elif defined(_3DS) | |
393 | ctr_flush_invalidate_cache(); | |
630b122b | 394 | #elif defined(__aarch64__) |
395 | // as of 2021, __clear_cache() is still broken on arm64 | |
396 | // so here is a custom one :( | |
397 | clear_cache_arm64(start, end); | |
d148d265 | 398 | #else |
399 | __clear_cache(start, end); | |
400 | #endif | |
401 | (void)len; | |
402 | #endif | |
403 | ||
404 | mprotect_w_x(start, end, 1); | |
405 | } | |
406 | ||
407 | static void *start_block(void) | |
408 | { | |
409 | u_char *end = out + MAX_OUTPUT_BLOCK_SIZE; | |
630b122b | 410 | if (end > ndrc->translation_cache + sizeof(ndrc->translation_cache)) |
411 | end = ndrc->translation_cache + sizeof(ndrc->translation_cache); | |
d148d265 | 412 | start_tcache_write(out, end); |
413 | return out; | |
414 | } | |
415 | ||
416 | static void end_block(void *start) | |
417 | { | |
418 | end_tcache_write(start, out); | |
419 | } | |
420 | ||
630b122b | 421 | // also takes care of w^x mappings when patching code |
422 | static u_int needs_clear_cache[1<<(TARGET_SIZE_2-17)]; | |
423 | ||
424 | static void mark_clear_cache(void *target) | |
425 | { | |
426 | uintptr_t offset = (u_char *)target - ndrc->translation_cache; | |
427 | u_int mask = 1u << ((offset >> 12) & 31); | |
428 | if (!(needs_clear_cache[offset >> 17] & mask)) { | |
429 | char *start = (char *)((uintptr_t)target & ~4095l); | |
430 | start_tcache_write(start, start + 4095); | |
431 | needs_clear_cache[offset >> 17] |= mask; | |
432 | } | |
433 | } | |
434 | ||
435 | // Clearing the cache is rather slow on ARM Linux, so mark the areas | |
436 | // that need to be cleared, and then only clear these areas once. | |
437 | static void do_clear_cache(void) | |
438 | { | |
439 | int i, j; | |
440 | for (i = 0; i < (1<<(TARGET_SIZE_2-17)); i++) | |
441 | { | |
442 | u_int bitmap = needs_clear_cache[i]; | |
443 | if (!bitmap) | |
444 | continue; | |
445 | for (j = 0; j < 32; j++) | |
446 | { | |
447 | u_char *start, *end; | |
448 | if (!(bitmap & (1<<j))) | |
449 | continue; | |
450 | ||
451 | start = ndrc->translation_cache + i*131072 + j*4096; | |
452 | end = start + 4095; | |
453 | for (j++; j < 32; j++) { | |
454 | if (!(bitmap & (1<<j))) | |
455 | break; | |
456 | end += 4096; | |
457 | } | |
458 | end_tcache_write(start, end); | |
459 | } | |
460 | needs_clear_cache[i] = 0; | |
461 | } | |
462 | } | |
463 | ||
57871462 | 464 | //#define DEBUG_CYCLE_COUNT 1 |
465 | ||
b6e87b2b | 466 | #define NO_CYCLE_PENALTY_THR 12 |
467 | ||
630b122b | 468 | int cycle_multiplier = CYCLE_MULT_DEFAULT; // 100 for 1.0 |
469 | int cycle_multiplier_override; | |
470 | int cycle_multiplier_old; | |
471 | static int cycle_multiplier_active; | |
4e9dcd7f | 472 | |
473 | static int CLOCK_ADJUST(int x) | |
474 | { | |
630b122b | 475 | int m = cycle_multiplier_active; |
476 | int s = (x >> 31) | 1; | |
477 | return (x * m + s * 50) / 100; | |
478 | } | |
479 | ||
480 | static int ds_writes_rjump_rs(int i) | |
481 | { | |
482 | return dops[i].rs1 != 0 && (dops[i].rs1 == dops[i+1].rt1 || dops[i].rs1 == dops[i+1].rt2); | |
4e9dcd7f | 483 | } |
484 | ||
94d23bb9 | 485 | static u_int get_page(u_int vaddr) |
57871462 | 486 | { |
0ce47d46 | 487 | u_int page=vaddr&~0xe0000000; |
488 | if (page < 0x1000000) | |
489 | page &= ~0x0e00000; // RAM mirrors | |
490 | page>>=12; | |
57871462 | 491 | if(page>2048) page=2048+(page&2047); |
94d23bb9 | 492 | return page; |
493 | } | |
494 | ||
d25604ca | 495 | // no virtual mem in PCSX |
496 | static u_int get_vpage(u_int vaddr) | |
497 | { | |
498 | return get_page(vaddr); | |
499 | } | |
94d23bb9 | 500 | |
630b122b | 501 | static struct ht_entry *hash_table_get(u_int vaddr) |
502 | { | |
503 | return &hash_table[((vaddr>>16)^vaddr)&0xFFFF]; | |
504 | } | |
505 | ||
506 | static void hash_table_add(struct ht_entry *ht_bin, u_int vaddr, void *tcaddr) | |
507 | { | |
508 | ht_bin->vaddr[1] = ht_bin->vaddr[0]; | |
509 | ht_bin->tcaddr[1] = ht_bin->tcaddr[0]; | |
510 | ht_bin->vaddr[0] = vaddr; | |
511 | ht_bin->tcaddr[0] = tcaddr; | |
512 | } | |
513 | ||
514 | // some messy ari64's code, seems to rely on unsigned 32bit overflow | |
515 | static int doesnt_expire_soon(void *tcaddr) | |
516 | { | |
517 | u_int diff = (u_int)((u_char *)tcaddr - out) << (32-TARGET_SIZE_2); | |
518 | return diff > (u_int)(0x60000000 + (MAX_OUTPUT_BLOCK_SIZE << (32-TARGET_SIZE_2))); | |
519 | } | |
520 | ||
94d23bb9 | 521 | // Get address from virtual address |
522 | // This is called from the recompiled JR/JALR instructions | |
630b122b | 523 | void noinline *get_addr(u_int vaddr) |
94d23bb9 | 524 | { |
630b122b | 525 | u_int page=get_page(vaddr); |
526 | u_int vpage=get_vpage(vaddr); | |
527 | struct ll_entry *head; | |
57871462 | 528 | //printf("TRACE: count=%d next=%d (get_addr %x,page %d)\n",Count,next_interupt,vaddr,page); |
529 | head=jump_in[page]; | |
630b122b | 530 | while(head!=NULL) { |
531 | if(head->vaddr==vaddr) { | |
532 | //printf("TRACE: count=%d next=%d (get_addr match %x: %p)\n",Count,next_interupt,vaddr,head->addr); | |
533 | hash_table_add(hash_table_get(vaddr), vaddr, head->addr); | |
57871462 | 534 | return head->addr; |
535 | } | |
536 | head=head->next; | |
537 | } | |
538 | head=jump_dirty[vpage]; | |
630b122b | 539 | while(head!=NULL) { |
540 | if(head->vaddr==vaddr) { | |
541 | //printf("TRACE: count=%d next=%d (get_addr match dirty %x: %p)\n",Count,next_interupt,vaddr,head->addr); | |
57871462 | 542 | // Don't restore blocks which are about to expire from the cache |
630b122b | 543 | if (doesnt_expire_soon(head->addr)) |
544 | if (verify_dirty(head->addr)) { | |
545 | //printf("restore candidate: %x (%d) d=%d\n",vaddr,page,invalid_code[vaddr>>12]); | |
546 | invalid_code[vaddr>>12]=0; | |
547 | inv_code_start=inv_code_end=~0; | |
548 | if(vpage<2048) { | |
549 | restore_candidate[vpage>>3]|=1<<(vpage&7); | |
550 | } | |
551 | else restore_candidate[page>>3]|=1<<(page&7); | |
552 | struct ht_entry *ht_bin = hash_table_get(vaddr); | |
553 | if (ht_bin->vaddr[0] == vaddr) | |
554 | ht_bin->tcaddr[0] = head->addr; // Replace existing entry | |
555 | else | |
556 | hash_table_add(ht_bin, vaddr, head->addr); | |
0bfdd1aa | 557 | |
630b122b | 558 | return head->addr; |
559 | } | |
57871462 | 560 | } |
561 | head=head->next; | |
562 | } | |
563 | //printf("TRACE: count=%d next=%d (get_addr no-match %x)\n",Count,next_interupt,vaddr); | |
564 | int r=new_recompile_block(vaddr); | |
630b122b | 565 | if(r==0) return get_addr(vaddr); |
566 | // Execute in unmapped page, generate pagefault execption | |
57871462 | 567 | Status|=2; |
568 | Cause=(vaddr<<31)|0x8; | |
569 | EPC=(vaddr&1)?vaddr-5:vaddr; | |
570 | BadVAddr=(vaddr&~1); | |
571 | Context=(Context&0xFF80000F)|((BadVAddr>>9)&0x007FFFF0); | |
572 | EntryHi=BadVAddr&0xFFFFE000; | |
573 | return get_addr_ht(0x80000000); | |
574 | } | |
575 | // Look up address in hash table first | |
576 | void *get_addr_ht(u_int vaddr) | |
577 | { | |
578 | //printf("TRACE: count=%d next=%d (get_addr_ht %x)\n",Count,next_interupt,vaddr); | |
630b122b | 579 | const struct ht_entry *ht_bin = hash_table_get(vaddr); |
580 | if (ht_bin->vaddr[0] == vaddr) return ht_bin->tcaddr[0]; | |
581 | if (ht_bin->vaddr[1] == vaddr) return ht_bin->tcaddr[1]; | |
57871462 | 582 | return get_addr(vaddr); |
583 | } | |
584 | ||
57871462 | 585 | void clear_all_regs(signed char regmap[]) |
586 | { | |
587 | int hr; | |
588 | for (hr=0;hr<HOST_REGS;hr++) regmap[hr]=-1; | |
589 | } | |
590 | ||
630b122b | 591 | static signed char get_reg(const signed char regmap[],int r) |
57871462 | 592 | { |
593 | int hr; | |
594 | for (hr=0;hr<HOST_REGS;hr++) if(hr!=EXCLUDE_REG&®map[hr]==r) return hr; | |
595 | return -1; | |
596 | } | |
597 | ||
598 | // Find a register that is available for two consecutive cycles | |
630b122b | 599 | static signed char get_reg2(signed char regmap1[], const signed char regmap2[], int r) |
57871462 | 600 | { |
601 | int hr; | |
602 | for (hr=0;hr<HOST_REGS;hr++) if(hr!=EXCLUDE_REG&®map1[hr]==r&®map2[hr]==r) return hr; | |
603 | return -1; | |
604 | } | |
605 | ||
606 | int count_free_regs(signed char regmap[]) | |
607 | { | |
608 | int count=0; | |
609 | int hr; | |
610 | for(hr=0;hr<HOST_REGS;hr++) | |
611 | { | |
612 | if(hr!=EXCLUDE_REG) { | |
613 | if(regmap[hr]<0) count++; | |
614 | } | |
615 | } | |
616 | return count; | |
617 | } | |
618 | ||
619 | void dirty_reg(struct regstat *cur,signed char reg) | |
620 | { | |
621 | int hr; | |
622 | if(!reg) return; | |
623 | for (hr=0;hr<HOST_REGS;hr++) { | |
624 | if((cur->regmap[hr]&63)==reg) { | |
625 | cur->dirty|=1<<hr; | |
626 | } | |
627 | } | |
628 | } | |
629 | ||
630b122b | 630 | static void set_const(struct regstat *cur, signed char reg, uint32_t value) |
57871462 | 631 | { |
632 | int hr; | |
633 | if(!reg) return; | |
634 | for (hr=0;hr<HOST_REGS;hr++) { | |
635 | if(cur->regmap[hr]==reg) { | |
636 | cur->isconst|=1<<hr; | |
956f3129 | 637 | current_constmap[hr]=value; |
57871462 | 638 | } |
57871462 | 639 | } |
640 | } | |
641 | ||
630b122b | 642 | static void clear_const(struct regstat *cur, signed char reg) |
57871462 | 643 | { |
644 | int hr; | |
645 | if(!reg) return; | |
646 | for (hr=0;hr<HOST_REGS;hr++) { | |
647 | if((cur->regmap[hr]&63)==reg) { | |
648 | cur->isconst&=~(1<<hr); | |
649 | } | |
650 | } | |
651 | } | |
652 | ||
630b122b | 653 | static int is_const(struct regstat *cur, signed char reg) |
57871462 | 654 | { |
655 | int hr; | |
79c75f1b | 656 | if(reg<0) return 0; |
57871462 | 657 | if(!reg) return 1; |
658 | for (hr=0;hr<HOST_REGS;hr++) { | |
659 | if((cur->regmap[hr]&63)==reg) { | |
660 | return (cur->isconst>>hr)&1; | |
661 | } | |
662 | } | |
663 | return 0; | |
664 | } | |
630b122b | 665 | |
666 | static uint32_t get_const(struct regstat *cur, signed char reg) | |
57871462 | 667 | { |
668 | int hr; | |
669 | if(!reg) return 0; | |
670 | for (hr=0;hr<HOST_REGS;hr++) { | |
671 | if(cur->regmap[hr]==reg) { | |
956f3129 | 672 | return current_constmap[hr]; |
57871462 | 673 | } |
674 | } | |
c43b5311 | 675 | SysPrintf("Unknown constant in r%d\n",reg); |
630b122b | 676 | abort(); |
57871462 | 677 | } |
678 | ||
679 | // Least soon needed registers | |
680 | // Look at the next ten instructions and see which registers | |
681 | // will be used. Try not to reallocate these. | |
682 | void lsn(u_char hsn[], int i, int *preferred_reg) | |
683 | { | |
684 | int j; | |
685 | int b=-1; | |
686 | for(j=0;j<9;j++) | |
687 | { | |
688 | if(i+j>=slen) { | |
689 | j=slen-i-1; | |
690 | break; | |
691 | } | |
630b122b | 692 | if (dops[i+j].is_ujump) |
57871462 | 693 | { |
694 | // Don't go past an unconditonal jump | |
695 | j++; | |
696 | break; | |
697 | } | |
698 | } | |
699 | for(;j>=0;j--) | |
700 | { | |
630b122b | 701 | if(dops[i+j].rs1) hsn[dops[i+j].rs1]=j; |
702 | if(dops[i+j].rs2) hsn[dops[i+j].rs2]=j; | |
703 | if(dops[i+j].rt1) hsn[dops[i+j].rt1]=j; | |
704 | if(dops[i+j].rt2) hsn[dops[i+j].rt2]=j; | |
705 | if(dops[i+j].itype==STORE || dops[i+j].itype==STORELR) { | |
57871462 | 706 | // Stores can allocate zero |
630b122b | 707 | hsn[dops[i+j].rs1]=j; |
708 | hsn[dops[i+j].rs2]=j; | |
57871462 | 709 | } |
630b122b | 710 | if (ram_offset && (dops[i+j].is_load || dops[i+j].is_store)) |
711 | hsn[ROREG] = j; | |
57871462 | 712 | // On some architectures stores need invc_ptr |
713 | #if defined(HOST_IMM8) | |
630b122b | 714 | if (dops[i+j].is_store) |
715 | hsn[INVCP] = j; | |
57871462 | 716 | #endif |
630b122b | 717 | if(i+j>=0&&(dops[i+j].itype==UJUMP||dops[i+j].itype==CJUMP||dops[i+j].itype==SJUMP)) |
57871462 | 718 | { |
719 | hsn[CCREG]=j; | |
720 | b=j; | |
721 | } | |
722 | } | |
723 | if(b>=0) | |
724 | { | |
725 | if(ba[i+b]>=start && ba[i+b]<(start+slen*4)) | |
726 | { | |
727 | // Follow first branch | |
728 | int t=(ba[i+b]-start)>>2; | |
729 | j=7-b;if(t+j>=slen) j=slen-t-1; | |
730 | for(;j>=0;j--) | |
731 | { | |
630b122b | 732 | if(dops[t+j].rs1) if(hsn[dops[t+j].rs1]>j+b+2) hsn[dops[t+j].rs1]=j+b+2; |
733 | if(dops[t+j].rs2) if(hsn[dops[t+j].rs2]>j+b+2) hsn[dops[t+j].rs2]=j+b+2; | |
734 | //if(dops[t+j].rt1) if(hsn[dops[t+j].rt1]>j+b+2) hsn[dops[t+j].rt1]=j+b+2; | |
735 | //if(dops[t+j].rt2) if(hsn[dops[t+j].rt2]>j+b+2) hsn[dops[t+j].rt2]=j+b+2; | |
57871462 | 736 | } |
737 | } | |
738 | // TODO: preferred register based on backward branch | |
739 | } | |
740 | // Delay slot should preferably not overwrite branch conditions or cycle count | |
630b122b | 741 | if (i > 0 && dops[i-1].is_jump) { |
742 | if(dops[i-1].rs1) if(hsn[dops[i-1].rs1]>1) hsn[dops[i-1].rs1]=1; | |
743 | if(dops[i-1].rs2) if(hsn[dops[i-1].rs2]>1) hsn[dops[i-1].rs2]=1; | |
57871462 | 744 | hsn[CCREG]=1; |
745 | // ...or hash tables | |
746 | hsn[RHASH]=1; | |
747 | hsn[RHTBL]=1; | |
748 | } | |
749 | // Coprocessor load/store needs FTEMP, even if not declared | |
630b122b | 750 | if(dops[i].itype==C2LS) { |
57871462 | 751 | hsn[FTEMP]=0; |
752 | } | |
753 | // Load L/R also uses FTEMP as a temporary register | |
630b122b | 754 | if(dops[i].itype==LOADLR) { |
57871462 | 755 | hsn[FTEMP]=0; |
756 | } | |
b7918751 | 757 | // Also SWL/SWR/SDL/SDR |
630b122b | 758 | if(dops[i].opcode==0x2a||dops[i].opcode==0x2e||dops[i].opcode==0x2c||dops[i].opcode==0x2d) { |
57871462 | 759 | hsn[FTEMP]=0; |
760 | } | |
57871462 | 761 | // Don't remove the miniht registers |
630b122b | 762 | if(dops[i].itype==UJUMP||dops[i].itype==RJUMP) |
57871462 | 763 | { |
764 | hsn[RHASH]=0; | |
765 | hsn[RHTBL]=0; | |
766 | } | |
767 | } | |
768 | ||
769 | // We only want to allocate registers if we're going to use them again soon | |
770 | int needed_again(int r, int i) | |
771 | { | |
772 | int j; | |
773 | int b=-1; | |
774 | int rn=10; | |
9f51b4b9 | 775 | |
630b122b | 776 | if (i > 0 && dops[i-1].is_ujump) |
57871462 | 777 | { |
778 | if(ba[i-1]<start || ba[i-1]>start+slen*4-4) | |
779 | return 0; // Don't need any registers if exiting the block | |
780 | } | |
781 | for(j=0;j<9;j++) | |
782 | { | |
783 | if(i+j>=slen) { | |
784 | j=slen-i-1; | |
785 | break; | |
786 | } | |
630b122b | 787 | if (dops[i+j].is_ujump) |
57871462 | 788 | { |
789 | // Don't go past an unconditonal jump | |
790 | j++; | |
791 | break; | |
792 | } | |
630b122b | 793 | if(dops[i+j].itype==SYSCALL||dops[i+j].itype==HLECALL||dops[i+j].itype==INTCALL||((source[i+j]&0xfc00003f)==0x0d)) |
57871462 | 794 | { |
795 | break; | |
796 | } | |
797 | } | |
798 | for(;j>=1;j--) | |
799 | { | |
630b122b | 800 | if(dops[i+j].rs1==r) rn=j; |
801 | if(dops[i+j].rs2==r) rn=j; | |
57871462 | 802 | if((unneeded_reg[i+j]>>r)&1) rn=10; |
630b122b | 803 | if(i+j>=0&&(dops[i+j].itype==UJUMP||dops[i+j].itype==CJUMP||dops[i+j].itype==SJUMP)) |
57871462 | 804 | { |
805 | b=j; | |
806 | } | |
807 | } | |
b7217e13 | 808 | if(rn<10) return 1; |
581335b0 | 809 | (void)b; |
57871462 | 810 | return 0; |
811 | } | |
812 | ||
813 | // Try to match register allocations at the end of a loop with those | |
814 | // at the beginning | |
815 | int loop_reg(int i, int r, int hr) | |
816 | { | |
817 | int j,k; | |
818 | for(j=0;j<9;j++) | |
819 | { | |
820 | if(i+j>=slen) { | |
821 | j=slen-i-1; | |
822 | break; | |
823 | } | |
630b122b | 824 | if (dops[i+j].is_ujump) |
57871462 | 825 | { |
826 | // Don't go past an unconditonal jump | |
827 | j++; | |
828 | break; | |
829 | } | |
830 | } | |
831 | k=0; | |
832 | if(i>0){ | |
630b122b | 833 | if(dops[i-1].itype==UJUMP||dops[i-1].itype==CJUMP||dops[i-1].itype==SJUMP) |
57871462 | 834 | k--; |
835 | } | |
836 | for(;k<j;k++) | |
837 | { | |
630b122b | 838 | assert(r < 64); |
839 | if((unneeded_reg[i+k]>>r)&1) return hr; | |
840 | if(i+k>=0&&(dops[i+k].itype==UJUMP||dops[i+k].itype==CJUMP||dops[i+k].itype==SJUMP)) | |
57871462 | 841 | { |
842 | if(ba[i+k]>=start && ba[i+k]<(start+i*4)) | |
843 | { | |
844 | int t=(ba[i+k]-start)>>2; | |
845 | int reg=get_reg(regs[t].regmap_entry,r); | |
846 | if(reg>=0) return reg; | |
847 | //reg=get_reg(regs[t+1].regmap_entry,r); | |
848 | //if(reg>=0) return reg; | |
849 | } | |
850 | } | |
851 | } | |
852 | return hr; | |
853 | } | |
854 | ||
855 | ||
856 | // Allocate every register, preserving source/target regs | |
857 | void alloc_all(struct regstat *cur,int i) | |
858 | { | |
859 | int hr; | |
9f51b4b9 | 860 | |
57871462 | 861 | for(hr=0;hr<HOST_REGS;hr++) { |
862 | if(hr!=EXCLUDE_REG) { | |
630b122b | 863 | if(((cur->regmap[hr]&63)!=dops[i].rs1)&&((cur->regmap[hr]&63)!=dops[i].rs2)&& |
864 | ((cur->regmap[hr]&63)!=dops[i].rt1)&&((cur->regmap[hr]&63)!=dops[i].rt2)) | |
57871462 | 865 | { |
866 | cur->regmap[hr]=-1; | |
867 | cur->dirty&=~(1<<hr); | |
868 | } | |
869 | // Don't need zeros | |
870 | if((cur->regmap[hr]&63)==0) | |
871 | { | |
872 | cur->regmap[hr]=-1; | |
873 | cur->dirty&=~(1<<hr); | |
874 | } | |
875 | } | |
876 | } | |
877 | } | |
878 | ||
630b122b | 879 | #ifndef NDEBUG |
880 | static int host_tempreg_in_use; | |
881 | ||
882 | static void host_tempreg_acquire(void) | |
883 | { | |
884 | assert(!host_tempreg_in_use); | |
885 | host_tempreg_in_use = 1; | |
886 | } | |
887 | ||
888 | static void host_tempreg_release(void) | |
889 | { | |
890 | host_tempreg_in_use = 0; | |
891 | } | |
892 | #else | |
893 | static void host_tempreg_acquire(void) {} | |
894 | static void host_tempreg_release(void) {} | |
895 | #endif | |
896 | ||
897 | #ifdef ASSEM_PRINT | |
898 | extern void gen_interupt(); | |
899 | extern void do_insn_cmp(); | |
900 | #define FUNCNAME(f) { f, " " #f } | |
901 | static const struct { | |
902 | void *addr; | |
903 | const char *name; | |
904 | } function_names[] = { | |
905 | FUNCNAME(cc_interrupt), | |
906 | FUNCNAME(gen_interupt), | |
907 | FUNCNAME(get_addr_ht), | |
908 | FUNCNAME(get_addr), | |
909 | FUNCNAME(jump_handler_read8), | |
910 | FUNCNAME(jump_handler_read16), | |
911 | FUNCNAME(jump_handler_read32), | |
912 | FUNCNAME(jump_handler_write8), | |
913 | FUNCNAME(jump_handler_write16), | |
914 | FUNCNAME(jump_handler_write32), | |
915 | FUNCNAME(invalidate_addr), | |
916 | FUNCNAME(jump_to_new_pc), | |
917 | FUNCNAME(call_gteStall), | |
918 | FUNCNAME(new_dyna_leave), | |
919 | FUNCNAME(pcsx_mtc0), | |
920 | FUNCNAME(pcsx_mtc0_ds), | |
921 | #ifdef DRC_DBG | |
922 | FUNCNAME(do_insn_cmp), | |
923 | #endif | |
924 | #ifdef __arm__ | |
925 | FUNCNAME(verify_code), | |
926 | #endif | |
927 | }; | |
928 | ||
929 | static const char *func_name(const void *a) | |
930 | { | |
931 | int i; | |
932 | for (i = 0; i < sizeof(function_names)/sizeof(function_names[0]); i++) | |
933 | if (function_names[i].addr == a) | |
934 | return function_names[i].name; | |
935 | return ""; | |
936 | } | |
937 | #else | |
938 | #define func_name(x) "" | |
939 | #endif | |
940 | ||
57871462 | 941 | #ifdef __i386__ |
630b122b | 942 | #include "assem_x86.c" |
57871462 | 943 | #endif |
944 | #ifdef __x86_64__ | |
630b122b | 945 | #include "assem_x64.c" |
57871462 | 946 | #endif |
947 | #ifdef __arm__ | |
630b122b | 948 | #include "assem_arm.c" |
949 | #endif | |
950 | #ifdef __aarch64__ | |
951 | #include "assem_arm64.c" | |
57871462 | 952 | #endif |
953 | ||
630b122b | 954 | static void *get_trampoline(const void *f) |
955 | { | |
956 | size_t i; | |
957 | ||
958 | for (i = 0; i < ARRAY_SIZE(ndrc->tramp.f); i++) { | |
959 | if (ndrc->tramp.f[i] == f || ndrc->tramp.f[i] == NULL) | |
960 | break; | |
961 | } | |
962 | if (i == ARRAY_SIZE(ndrc->tramp.f)) { | |
963 | SysPrintf("trampoline table is full, last func %p\n", f); | |
964 | abort(); | |
965 | } | |
966 | if (ndrc->tramp.f[i] == NULL) { | |
967 | start_tcache_write(&ndrc->tramp.f[i], &ndrc->tramp.f[i + 1]); | |
968 | ndrc->tramp.f[i] = f; | |
969 | end_tcache_write(&ndrc->tramp.f[i], &ndrc->tramp.f[i + 1]); | |
970 | } | |
971 | return &ndrc->tramp.ops[i]; | |
972 | } | |
973 | ||
974 | static void emit_far_jump(const void *f) | |
975 | { | |
976 | if (can_jump_or_call(f)) { | |
977 | emit_jmp(f); | |
978 | return; | |
979 | } | |
980 | ||
981 | f = get_trampoline(f); | |
982 | emit_jmp(f); | |
983 | } | |
984 | ||
985 | static void emit_far_call(const void *f) | |
986 | { | |
987 | if (can_jump_or_call(f)) { | |
988 | emit_call(f); | |
989 | return; | |
990 | } | |
991 | ||
992 | f = get_trampoline(f); | |
993 | emit_call(f); | |
994 | } | |
995 | ||
57871462 | 996 | // Add virtual address mapping to linked list |
997 | void ll_add(struct ll_entry **head,int vaddr,void *addr) | |
998 | { | |
999 | struct ll_entry *new_entry; | |
1000 | new_entry=malloc(sizeof(struct ll_entry)); | |
1001 | assert(new_entry!=NULL); | |
1002 | new_entry->vaddr=vaddr; | |
de5a60c3 | 1003 | new_entry->reg_sv_flags=0; |
57871462 | 1004 | new_entry->addr=addr; |
1005 | new_entry->next=*head; | |
1006 | *head=new_entry; | |
1007 | } | |
1008 | ||
de5a60c3 | 1009 | void ll_add_flags(struct ll_entry **head,int vaddr,u_int reg_sv_flags,void *addr) |
57871462 | 1010 | { |
7139f3c8 | 1011 | ll_add(head,vaddr,addr); |
de5a60c3 | 1012 | (*head)->reg_sv_flags=reg_sv_flags; |
57871462 | 1013 | } |
1014 | ||
1015 | // Check if an address is already compiled | |
1016 | // but don't return addresses which are about to expire from the cache | |
1017 | void *check_addr(u_int vaddr) | |
1018 | { | |
630b122b | 1019 | struct ht_entry *ht_bin = hash_table_get(vaddr); |
1020 | size_t i; | |
1021 | for (i = 0; i < ARRAY_SIZE(ht_bin->vaddr); i++) { | |
1022 | if (ht_bin->vaddr[i] == vaddr) | |
1023 | if (doesnt_expire_soon((u_char *)ht_bin->tcaddr[i] - MAX_OUTPUT_BLOCK_SIZE)) | |
1024 | if (isclean(ht_bin->tcaddr[i])) | |
1025 | return ht_bin->tcaddr[i]; | |
57871462 | 1026 | } |
94d23bb9 | 1027 | u_int page=get_page(vaddr); |
57871462 | 1028 | struct ll_entry *head; |
1029 | head=jump_in[page]; | |
630b122b | 1030 | while (head != NULL) { |
1031 | if (head->vaddr == vaddr) { | |
1032 | if (doesnt_expire_soon(head->addr)) { | |
57871462 | 1033 | // Update existing entry with current address |
630b122b | 1034 | if (ht_bin->vaddr[0] == vaddr) { |
1035 | ht_bin->tcaddr[0] = head->addr; | |
57871462 | 1036 | return head->addr; |
1037 | } | |
630b122b | 1038 | if (ht_bin->vaddr[1] == vaddr) { |
1039 | ht_bin->tcaddr[1] = head->addr; | |
57871462 | 1040 | return head->addr; |
1041 | } | |
1042 | // Insert into hash table with low priority. | |
1043 | // Don't evict existing entries, as they are probably | |
1044 | // addresses that are being accessed frequently. | |
630b122b | 1045 | if (ht_bin->vaddr[0] == -1) { |
1046 | ht_bin->vaddr[0] = vaddr; | |
1047 | ht_bin->tcaddr[0] = head->addr; | |
1048 | } | |
1049 | else if (ht_bin->vaddr[1] == -1) { | |
1050 | ht_bin->vaddr[1] = vaddr; | |
1051 | ht_bin->tcaddr[1] = head->addr; | |
57871462 | 1052 | } |
1053 | return head->addr; | |
1054 | } | |
1055 | } | |
1056 | head=head->next; | |
1057 | } | |
1058 | return 0; | |
1059 | } | |
1060 | ||
1061 | void remove_hash(int vaddr) | |
1062 | { | |
1063 | //printf("remove hash: %x\n",vaddr); | |
630b122b | 1064 | struct ht_entry *ht_bin = hash_table_get(vaddr); |
1065 | if (ht_bin->vaddr[1] == vaddr) { | |
1066 | ht_bin->vaddr[1] = -1; | |
1067 | ht_bin->tcaddr[1] = NULL; | |
57871462 | 1068 | } |
630b122b | 1069 | if (ht_bin->vaddr[0] == vaddr) { |
1070 | ht_bin->vaddr[0] = ht_bin->vaddr[1]; | |
1071 | ht_bin->tcaddr[0] = ht_bin->tcaddr[1]; | |
1072 | ht_bin->vaddr[1] = -1; | |
1073 | ht_bin->tcaddr[1] = NULL; | |
57871462 | 1074 | } |
1075 | } | |
1076 | ||
630b122b | 1077 | static void ll_remove_matching_addrs(struct ll_entry **head, |
1078 | uintptr_t base_offs_s, int shift) | |
57871462 | 1079 | { |
1080 | struct ll_entry *next; | |
1081 | while(*head) { | |
630b122b | 1082 | uintptr_t o1 = (u_char *)(*head)->addr - ndrc->translation_cache; |
1083 | uintptr_t o2 = o1 - MAX_OUTPUT_BLOCK_SIZE; | |
1084 | if ((o1 >> shift) == base_offs_s || (o2 >> shift) == base_offs_s) | |
57871462 | 1085 | { |
630b122b | 1086 | inv_debug("EXP: Remove pointer to %p (%x)\n",(*head)->addr,(*head)->vaddr); |
57871462 | 1087 | remove_hash((*head)->vaddr); |
1088 | next=(*head)->next; | |
1089 | free(*head); | |
1090 | *head=next; | |
1091 | } | |
1092 | else | |
1093 | { | |
1094 | head=&((*head)->next); | |
1095 | } | |
1096 | } | |
1097 | } | |
1098 | ||
1099 | // Remove all entries from linked list | |
1100 | void ll_clear(struct ll_entry **head) | |
1101 | { | |
1102 | struct ll_entry *cur; | |
1103 | struct ll_entry *next; | |
581335b0 | 1104 | if((cur=*head)) { |
57871462 | 1105 | *head=0; |
1106 | while(cur) { | |
1107 | next=cur->next; | |
1108 | free(cur); | |
1109 | cur=next; | |
1110 | } | |
1111 | } | |
1112 | } | |
1113 | ||
1114 | // Dereference the pointers and remove if it matches | |
630b122b | 1115 | static void ll_kill_pointers(struct ll_entry *head, |
1116 | uintptr_t base_offs_s, int shift) | |
57871462 | 1117 | { |
1118 | while(head) { | |
630b122b | 1119 | u_char *ptr = get_pointer(head->addr); |
1120 | uintptr_t o1 = ptr - ndrc->translation_cache; | |
1121 | uintptr_t o2 = o1 - MAX_OUTPUT_BLOCK_SIZE; | |
1122 | inv_debug("EXP: Lookup pointer to %p at %p (%x)\n",ptr,head->addr,head->vaddr); | |
1123 | if ((o1 >> shift) == base_offs_s || (o2 >> shift) == base_offs_s) | |
57871462 | 1124 | { |
630b122b | 1125 | inv_debug("EXP: Kill pointer at %p (%x)\n",head->addr,head->vaddr); |
d148d265 | 1126 | void *host_addr=find_extjump_insn(head->addr); |
630b122b | 1127 | mark_clear_cache(host_addr); |
1128 | set_jump_target(host_addr, head->addr); | |
57871462 | 1129 | } |
1130 | head=head->next; | |
1131 | } | |
1132 | } | |
1133 | ||
1134 | // This is called when we write to a compiled block (see do_invstub) | |
630b122b | 1135 | static void invalidate_page(u_int page) |
57871462 | 1136 | { |
57871462 | 1137 | struct ll_entry *head; |
1138 | struct ll_entry *next; | |
1139 | head=jump_in[page]; | |
1140 | jump_in[page]=0; | |
1141 | while(head!=NULL) { | |
1142 | inv_debug("INVALIDATE: %x\n",head->vaddr); | |
1143 | remove_hash(head->vaddr); | |
1144 | next=head->next; | |
1145 | free(head); | |
1146 | head=next; | |
1147 | } | |
1148 | head=jump_out[page]; | |
1149 | jump_out[page]=0; | |
1150 | while(head!=NULL) { | |
630b122b | 1151 | inv_debug("INVALIDATE: kill pointer to %x (%p)\n",head->vaddr,head->addr); |
d148d265 | 1152 | void *host_addr=find_extjump_insn(head->addr); |
630b122b | 1153 | mark_clear_cache(host_addr); |
1154 | set_jump_target(host_addr, head->addr); // point back to dyna_linker | |
57871462 | 1155 | next=head->next; |
1156 | free(head); | |
1157 | head=next; | |
1158 | } | |
57871462 | 1159 | } |
9be4ba64 | 1160 | |
1161 | static void invalidate_block_range(u_int block, u_int first, u_int last) | |
57871462 | 1162 | { |
94d23bb9 | 1163 | u_int page=get_page(block<<12); |
57871462 | 1164 | //printf("first=%d last=%d\n",first,last); |
f76eeef9 | 1165 | invalidate_page(page); |
57871462 | 1166 | assert(first+5>page); // NB: this assumes MAXBLOCK<=4096 (4 pages) |
1167 | assert(last<page+5); | |
1168 | // Invalidate the adjacent pages if a block crosses a 4K boundary | |
630b122b | 1169 | while(first<page) { |
57871462 | 1170 | invalidate_page(first); |
1171 | first++; | |
1172 | } | |
630b122b | 1173 | for(first=page+1;first<last;first++) { |
57871462 | 1174 | invalidate_page(first); |
1175 | } | |
0bfdd1aa | 1176 | do_clear_cache(); |
9f51b4b9 | 1177 | |
57871462 | 1178 | // Don't trap writes |
1179 | invalid_code[block]=1; | |
f76eeef9 | 1180 | |
630b122b | 1181 | #ifdef USE_MINI_HT |
57871462 | 1182 | memset(mini_ht,-1,sizeof(mini_ht)); |
630b122b | 1183 | #endif |
57871462 | 1184 | } |
9be4ba64 | 1185 | |
1186 | void invalidate_block(u_int block) | |
1187 | { | |
1188 | u_int page=get_page(block<<12); | |
1189 | u_int vpage=get_vpage(block<<12); | |
1190 | inv_debug("INVALIDATE: %x (%d)\n",block<<12,page); | |
630b122b | 1191 | //inv_debug("invalid_code[block]=%d\n",invalid_code[block]); |
9be4ba64 | 1192 | u_int first,last; |
1193 | first=last=page; | |
1194 | struct ll_entry *head; | |
1195 | head=jump_dirty[vpage]; | |
1196 | //printf("page=%d vpage=%d\n",page,vpage); | |
630b122b | 1197 | while(head!=NULL) { |
1198 | if(vpage>2047||(head->vaddr>>12)==block) { // Ignore vaddr hash collision | |
1199 | u_char *start, *end; | |
1200 | get_bounds(head->addr, &start, &end); | |
1201 | //printf("start: %p end: %p\n", start, end); | |
1202 | if (page < 2048 && start >= rdram && end < rdram+RAM_SIZE) { | |
1203 | if (((start-rdram)>>12) <= page && ((end-1-rdram)>>12) >= page) { | |
1204 | if ((((start-rdram)>>12)&2047) < first) first = ((start-rdram)>>12)&2047; | |
1205 | if ((((end-1-rdram)>>12)&2047) > last) last = ((end-1-rdram)>>12)&2047; | |
9be4ba64 | 1206 | } |
1207 | } | |
9be4ba64 | 1208 | } |
1209 | head=head->next; | |
1210 | } | |
1211 | invalidate_block_range(block,first,last); | |
1212 | } | |
1213 | ||
57871462 | 1214 | void invalidate_addr(u_int addr) |
1215 | { | |
9be4ba64 | 1216 | //static int rhits; |
1217 | // this check is done by the caller | |
1218 | //if (inv_code_start<=addr&&addr<=inv_code_end) { rhits++; return; } | |
d25604ca | 1219 | u_int page=get_vpage(addr); |
9be4ba64 | 1220 | if(page<2048) { // RAM |
1221 | struct ll_entry *head; | |
1222 | u_int addr_min=~0, addr_max=0; | |
4a35de07 | 1223 | u_int mask=RAM_SIZE-1; |
1224 | u_int addr_main=0x80000000|(addr&mask); | |
9be4ba64 | 1225 | int pg1; |
4a35de07 | 1226 | inv_code_start=addr_main&~0xfff; |
1227 | inv_code_end=addr_main|0xfff; | |
9be4ba64 | 1228 | pg1=page; |
1229 | if (pg1>0) { | |
1230 | // must check previous page too because of spans.. | |
1231 | pg1--; | |
1232 | inv_code_start-=0x1000; | |
1233 | } | |
1234 | for(;pg1<=page;pg1++) { | |
1235 | for(head=jump_dirty[pg1];head!=NULL;head=head->next) { | |
630b122b | 1236 | u_char *start_h, *end_h; |
1237 | u_int start, end; | |
1238 | get_bounds(head->addr, &start_h, &end_h); | |
1239 | start = (uintptr_t)start_h - ram_offset; | |
1240 | end = (uintptr_t)end_h - ram_offset; | |
4a35de07 | 1241 | if(start<=addr_main&&addr_main<end) { |
9be4ba64 | 1242 | if(start<addr_min) addr_min=start; |
1243 | if(end>addr_max) addr_max=end; | |
1244 | } | |
4a35de07 | 1245 | else if(addr_main<start) { |
9be4ba64 | 1246 | if(start<inv_code_end) |
1247 | inv_code_end=start-1; | |
1248 | } | |
1249 | else { | |
1250 | if(end>inv_code_start) | |
1251 | inv_code_start=end; | |
1252 | } | |
1253 | } | |
1254 | } | |
1255 | if (addr_min!=~0) { | |
1256 | inv_debug("INV ADDR: %08x hit %08x-%08x\n", addr, addr_min, addr_max); | |
1257 | inv_code_start=inv_code_end=~0; | |
1258 | invalidate_block_range(addr>>12,(addr_min&mask)>>12,(addr_max&mask)>>12); | |
1259 | return; | |
1260 | } | |
1261 | else { | |
4a35de07 | 1262 | inv_code_start=(addr&~mask)|(inv_code_start&mask); |
1263 | inv_code_end=(addr&~mask)|(inv_code_end&mask); | |
d25604ca | 1264 | inv_debug("INV ADDR: %08x miss, inv %08x-%08x, sk %d\n", addr, inv_code_start, inv_code_end, 0); |
9be4ba64 | 1265 | return; |
d25604ca | 1266 | } |
9be4ba64 | 1267 | } |
57871462 | 1268 | invalidate_block(addr>>12); |
1269 | } | |
9be4ba64 | 1270 | |
dd3a91a1 | 1271 | // This is called when loading a save state. |
1272 | // Anything could have changed, so invalidate everything. | |
92d79826 | 1273 | void invalidate_all_pages(void) |
57871462 | 1274 | { |
581335b0 | 1275 | u_int page; |
57871462 | 1276 | for(page=0;page<4096;page++) |
1277 | invalidate_page(page); | |
1278 | for(page=0;page<1048576;page++) | |
630b122b | 1279 | if(!invalid_code[page]) { |
57871462 | 1280 | restore_candidate[(page&2047)>>3]|=1<<(page&7); |
1281 | restore_candidate[((page&2047)>>3)+256]|=1<<(page&7); | |
1282 | } | |
630b122b | 1283 | #ifdef USE_MINI_HT |
57871462 | 1284 | memset(mini_ht,-1,sizeof(mini_ht)); |
630b122b | 1285 | #endif |
1286 | do_clear_cache(); | |
1287 | } | |
1288 | ||
1289 | static void do_invstub(int n) | |
1290 | { | |
1291 | literal_pool(20); | |
1292 | u_int reglist=stubs[n].a; | |
1293 | set_jump_target(stubs[n].addr, out); | |
1294 | save_regs(reglist); | |
1295 | if(stubs[n].b!=0) emit_mov(stubs[n].b,0); | |
1296 | emit_far_call(invalidate_addr); | |
1297 | restore_regs(reglist); | |
1298 | emit_jmp(stubs[n].retaddr); // return address | |
57871462 | 1299 | } |
1300 | ||
1301 | // Add an entry to jump_out after making a link | |
630b122b | 1302 | // src should point to code by emit_extjump2() |
1303 | void add_jump_out(u_int vaddr,void *src) | |
57871462 | 1304 | { |
94d23bb9 | 1305 | u_int page=get_page(vaddr); |
630b122b | 1306 | inv_debug("add_jump_out: %p -> %x (%d)\n",src,vaddr,page); |
1307 | check_extjump2(src); | |
57871462 | 1308 | ll_add(jump_out+page,vaddr,src); |
630b122b | 1309 | //inv_debug("add_jump_out: to %p\n",get_pointer(src)); |
57871462 | 1310 | } |
1311 | ||
1312 | // If a code block was found to be unmodified (bit was set in | |
1313 | // restore_candidate) and it remains unmodified (bit is clear | |
1314 | // in invalid_code) then move the entries for that 4K page from | |
1315 | // the dirty list to the clean list. | |
1316 | void clean_blocks(u_int page) | |
1317 | { | |
1318 | struct ll_entry *head; | |
1319 | inv_debug("INV: clean_blocks page=%d\n",page); | |
1320 | head=jump_dirty[page]; | |
630b122b | 1321 | while(head!=NULL) { |
1322 | if(!invalid_code[head->vaddr>>12]) { | |
57871462 | 1323 | // Don't restore blocks which are about to expire from the cache |
630b122b | 1324 | if (doesnt_expire_soon(head->addr)) { |
1325 | if(verify_dirty(head->addr)) { | |
1326 | u_char *start, *end; | |
1327 | //printf("Possibly Restore %x (%p)\n",head->vaddr, head->addr); | |
57871462 | 1328 | u_int i; |
1329 | u_int inv=0; | |
630b122b | 1330 | get_bounds(head->addr, &start, &end); |
1331 | if (start - rdram < RAM_SIZE) { | |
1332 | for (i = (start-rdram+0x80000000)>>12; i <= (end-1-rdram+0x80000000)>>12; i++) { | |
57871462 | 1333 | inv|=invalid_code[i]; |
1334 | } | |
1335 | } | |
630b122b | 1336 | else if((signed int)head->vaddr>=(signed int)0x80000000+RAM_SIZE) { |
57871462 | 1337 | inv=1; |
1338 | } | |
630b122b | 1339 | if(!inv) { |
1340 | void *clean_addr = get_clean_addr(head->addr); | |
1341 | if (doesnt_expire_soon(clean_addr)) { | |
57871462 | 1342 | u_int ppage=page; |
630b122b | 1343 | inv_debug("INV: Restored %x (%p/%p)\n",head->vaddr, head->addr, clean_addr); |
57871462 | 1344 | //printf("page=%x, addr=%x\n",page,head->vaddr); |
1345 | //assert(head->vaddr>>12==(page|0x80000)); | |
de5a60c3 | 1346 | ll_add_flags(jump_in+ppage,head->vaddr,head->reg_sv_flags,clean_addr); |
630b122b | 1347 | struct ht_entry *ht_bin = hash_table_get(head->vaddr); |
1348 | if (ht_bin->vaddr[0] == head->vaddr) | |
1349 | ht_bin->tcaddr[0] = clean_addr; // Replace existing entry | |
1350 | if (ht_bin->vaddr[1] == head->vaddr) | |
1351 | ht_bin->tcaddr[1] = clean_addr; // Replace existing entry | |
57871462 | 1352 | } |
1353 | } | |
1354 | } | |
1355 | } | |
1356 | } | |
1357 | head=head->next; | |
1358 | } | |
1359 | } | |
1360 | ||
630b122b | 1361 | /* Register allocation */ |
1362 | ||
1363 | // Note: registers are allocated clean (unmodified state) | |
1364 | // if you intend to modify the register, you must call dirty_reg(). | |
1365 | static void alloc_reg(struct regstat *cur,int i,signed char reg) | |
57871462 | 1366 | { |
630b122b | 1367 | int r,hr; |
1368 | int preferred_reg = PREFERRED_REG_FIRST | |
1369 | + reg % (PREFERRED_REG_LAST - PREFERRED_REG_FIRST + 1); | |
1370 | if (reg == CCREG) preferred_reg = HOST_CCREG; | |
1371 | if (reg == PTEMP || reg == FTEMP) preferred_reg = 12; | |
1372 | assert(PREFERRED_REG_FIRST != EXCLUDE_REG && EXCLUDE_REG != HOST_REGS); | |
1373 | ||
1374 | // Don't allocate unused registers | |
1375 | if((cur->u>>reg)&1) return; | |
1376 | ||
1377 | // see if it's already allocated | |
1378 | for(hr=0;hr<HOST_REGS;hr++) | |
0bfdd1aa | 1379 | { |
630b122b | 1380 | if(cur->regmap[hr]==reg) return; |
1381 | } | |
1382 | ||
1383 | // Keep the same mapping if the register was already allocated in a loop | |
1384 | preferred_reg = loop_reg(i,reg,preferred_reg); | |
1385 | ||
1386 | // Try to allocate the preferred register | |
1387 | if(cur->regmap[preferred_reg]==-1) { | |
1388 | cur->regmap[preferred_reg]=reg; | |
1389 | cur->dirty&=~(1<<preferred_reg); | |
1390 | cur->isconst&=~(1<<preferred_reg); | |
1391 | return; | |
1392 | } | |
1393 | r=cur->regmap[preferred_reg]; | |
1394 | assert(r < 64); | |
1395 | if((cur->u>>r)&1) { | |
1396 | cur->regmap[preferred_reg]=reg; | |
1397 | cur->dirty&=~(1<<preferred_reg); | |
1398 | cur->isconst&=~(1<<preferred_reg); | |
1399 | return; | |
1400 | } | |
1401 | ||
1402 | // Clear any unneeded registers | |
1403 | // We try to keep the mapping consistent, if possible, because it | |
1404 | // makes branches easier (especially loops). So we try to allocate | |
1405 | // first (see above) before removing old mappings. If this is not | |
1406 | // possible then go ahead and clear out the registers that are no | |
1407 | // longer needed. | |
1408 | for(hr=0;hr<HOST_REGS;hr++) | |
0bfdd1aa | 1409 | { |
630b122b | 1410 | r=cur->regmap[hr]; |
1411 | if(r>=0) { | |
1412 | assert(r < 64); | |
1413 | if((cur->u>>r)&1) {cur->regmap[hr]=-1;break;} | |
1414 | } | |
57871462 | 1415 | } |
57871462 | 1416 | |
630b122b | 1417 | // Try to allocate any available register, but prefer |
1418 | // registers that have not been used recently. | |
1419 | if (i > 0) { | |
1420 | for (hr = PREFERRED_REG_FIRST; ; ) { | |
1421 | if (cur->regmap[hr] < 0) { | |
1422 | int oldreg = regs[i-1].regmap[hr]; | |
1423 | if (oldreg < 0 || (oldreg != dops[i-1].rs1 && oldreg != dops[i-1].rs2 | |
1424 | && oldreg != dops[i-1].rt1 && oldreg != dops[i-1].rt2)) | |
1425 | { | |
1426 | cur->regmap[hr]=reg; | |
1427 | cur->dirty&=~(1<<hr); | |
1428 | cur->isconst&=~(1<<hr); | |
1429 | return; | |
1430 | } | |
dc49e339 | 1431 | } |
630b122b | 1432 | hr++; |
1433 | if (hr == EXCLUDE_REG) | |
1434 | hr++; | |
1435 | if (hr == HOST_REGS) | |
1436 | hr = 0; | |
1437 | if (hr == PREFERRED_REG_FIRST) | |
1438 | break; | |
57871462 | 1439 | } |
1440 | } | |
dc49e339 | 1441 | |
630b122b | 1442 | // Try to allocate any available register |
1443 | for (hr = PREFERRED_REG_FIRST; ; ) { | |
1444 | if (cur->regmap[hr] < 0) { | |
1445 | cur->regmap[hr]=reg; | |
1446 | cur->dirty&=~(1<<hr); | |
1447 | cur->isconst&=~(1<<hr); | |
1448 | return; | |
57871462 | 1449 | } |
630b122b | 1450 | hr++; |
1451 | if (hr == EXCLUDE_REG) | |
1452 | hr++; | |
1453 | if (hr == HOST_REGS) | |
1454 | hr = 0; | |
1455 | if (hr == PREFERRED_REG_FIRST) | |
1456 | break; | |
57871462 | 1457 | } |
630b122b | 1458 | |
1459 | // Ok, now we have to evict someone | |
1460 | // Pick a register we hopefully won't need soon | |
1461 | u_char hsn[MAXREG+1]; | |
1462 | memset(hsn,10,sizeof(hsn)); | |
1463 | int j; | |
1464 | lsn(hsn,i,&preferred_reg); | |
1465 | //printf("eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",cur->regmap[0],cur->regmap[1],cur->regmap[2],cur->regmap[3],cur->regmap[5],cur->regmap[6],cur->regmap[7]); | |
1466 | //printf("hsn(%x): %d %d %d %d %d %d %d\n",start+i*4,hsn[cur->regmap[0]&63],hsn[cur->regmap[1]&63],hsn[cur->regmap[2]&63],hsn[cur->regmap[3]&63],hsn[cur->regmap[5]&63],hsn[cur->regmap[6]&63],hsn[cur->regmap[7]&63]); | |
1467 | if(i>0) { | |
1468 | // Don't evict the cycle count at entry points, otherwise the entry | |
1469 | // stub will have to write it. | |
1470 | if(dops[i].bt&&hsn[CCREG]>2) hsn[CCREG]=2; | |
1471 | if (i>1 && hsn[CCREG] > 2 && dops[i-2].is_jump) hsn[CCREG]=2; | |
1472 | for(j=10;j>=3;j--) | |
1473 | { | |
1474 | // Alloc preferred register if available | |
1475 | if(hsn[r=cur->regmap[preferred_reg]&63]==j) { | |
1476 | for(hr=0;hr<HOST_REGS;hr++) { | |
1477 | // Evict both parts of a 64-bit register | |
1478 | if((cur->regmap[hr]&63)==r) { | |
1479 | cur->regmap[hr]=-1; | |
1480 | cur->dirty&=~(1<<hr); | |
1481 | cur->isconst&=~(1<<hr); | |
1482 | } | |
1483 | } | |
1484 | cur->regmap[preferred_reg]=reg; | |
1485 | return; | |
1486 | } | |
1487 | for(r=1;r<=MAXREG;r++) | |
1488 | { | |
1489 | if(hsn[r]==j&&r!=dops[i-1].rs1&&r!=dops[i-1].rs2&&r!=dops[i-1].rt1&&r!=dops[i-1].rt2) { | |
1490 | for(hr=0;hr<HOST_REGS;hr++) { | |
1491 | if(hr!=HOST_CCREG||j<hsn[CCREG]) { | |
1492 | if(cur->regmap[hr]==r) { | |
1493 | cur->regmap[hr]=reg; | |
1494 | cur->dirty&=~(1<<hr); | |
1495 | cur->isconst&=~(1<<hr); | |
1496 | return; | |
1497 | } | |
1498 | } | |
1499 | } | |
1500 | } | |
1501 | } | |
57871462 | 1502 | } |
1503 | } | |
630b122b | 1504 | for(j=10;j>=0;j--) |
57871462 | 1505 | { |
630b122b | 1506 | for(r=1;r<=MAXREG;r++) |
1507 | { | |
1508 | if(hsn[r]==j) { | |
1509 | for(hr=0;hr<HOST_REGS;hr++) { | |
1510 | if(cur->regmap[hr]==r) { | |
1511 | cur->regmap[hr]=reg; | |
1512 | cur->dirty&=~(1<<hr); | |
1513 | cur->isconst&=~(1<<hr); | |
1514 | return; | |
1515 | } | |
1516 | } | |
57871462 | 1517 | } |
57871462 | 1518 | } |
1519 | } | |
630b122b | 1520 | SysPrintf("This shouldn't happen (alloc_reg)");abort(); |
1521 | } | |
1522 | ||
1523 | // Allocate a temporary register. This is done without regard to | |
1524 | // dirty status or whether the register we request is on the unneeded list | |
1525 | // Note: This will only allocate one register, even if called multiple times | |
1526 | static void alloc_reg_temp(struct regstat *cur,int i,signed char reg) | |
1527 | { | |
1528 | int r,hr; | |
1529 | int preferred_reg = -1; | |
1530 | ||
1531 | // see if it's already allocated | |
1532 | for(hr=0;hr<HOST_REGS;hr++) | |
1533 | { | |
1534 | if(hr!=EXCLUDE_REG&&cur->regmap[hr]==reg) return; | |
1535 | } | |
1536 | ||
1537 | // Try to allocate any available register | |
1538 | for(hr=HOST_REGS-1;hr>=0;hr--) { | |
1539 | if(hr!=EXCLUDE_REG&&cur->regmap[hr]==-1) { | |
1540 | cur->regmap[hr]=reg; | |
1541 | cur->dirty&=~(1<<hr); | |
1542 | cur->isconst&=~(1<<hr); | |
1543 | return; | |
1544 | } | |
1545 | } | |
1546 | ||
1547 | // Find an unneeded register | |
1548 | for(hr=HOST_REGS-1;hr>=0;hr--) | |
1549 | { | |
1550 | r=cur->regmap[hr]; | |
1551 | if(r>=0) { | |
1552 | assert(r < 64); | |
1553 | if((cur->u>>r)&1) { | |
1554 | if(i==0||((unneeded_reg[i-1]>>r)&1)) { | |
1555 | cur->regmap[hr]=reg; | |
1556 | cur->dirty&=~(1<<hr); | |
1557 | cur->isconst&=~(1<<hr); | |
1558 | return; | |
1559 | } | |
1560 | } | |
1561 | } | |
1562 | } | |
1563 | ||
1564 | // Ok, now we have to evict someone | |
1565 | // Pick a register we hopefully won't need soon | |
1566 | // TODO: we might want to follow unconditional jumps here | |
1567 | // TODO: get rid of dupe code and make this into a function | |
1568 | u_char hsn[MAXREG+1]; | |
1569 | memset(hsn,10,sizeof(hsn)); | |
1570 | int j; | |
1571 | lsn(hsn,i,&preferred_reg); | |
1572 | //printf("hsn: %d %d %d %d %d %d %d\n",hsn[cur->regmap[0]&63],hsn[cur->regmap[1]&63],hsn[cur->regmap[2]&63],hsn[cur->regmap[3]&63],hsn[cur->regmap[5]&63],hsn[cur->regmap[6]&63],hsn[cur->regmap[7]&63]); | |
1573 | if(i>0) { | |
1574 | // Don't evict the cycle count at entry points, otherwise the entry | |
1575 | // stub will have to write it. | |
1576 | if(dops[i].bt&&hsn[CCREG]>2) hsn[CCREG]=2; | |
1577 | if (i>1 && hsn[CCREG] > 2 && dops[i-2].is_jump) hsn[CCREG]=2; | |
1578 | for(j=10;j>=3;j--) | |
1579 | { | |
1580 | for(r=1;r<=MAXREG;r++) | |
1581 | { | |
1582 | if(hsn[r]==j&&r!=dops[i-1].rs1&&r!=dops[i-1].rs2&&r!=dops[i-1].rt1&&r!=dops[i-1].rt2) { | |
1583 | for(hr=0;hr<HOST_REGS;hr++) { | |
1584 | if(hr!=HOST_CCREG||hsn[CCREG]>2) { | |
1585 | if(cur->regmap[hr]==r) { | |
1586 | cur->regmap[hr]=reg; | |
1587 | cur->dirty&=~(1<<hr); | |
1588 | cur->isconst&=~(1<<hr); | |
1589 | return; | |
1590 | } | |
1591 | } | |
1592 | } | |
1593 | } | |
1594 | } | |
1595 | } | |
1596 | } | |
1597 | for(j=10;j>=0;j--) | |
1598 | { | |
1599 | for(r=1;r<=MAXREG;r++) | |
1600 | { | |
1601 | if(hsn[r]==j) { | |
1602 | for(hr=0;hr<HOST_REGS;hr++) { | |
1603 | if(cur->regmap[hr]==r) { | |
1604 | cur->regmap[hr]=reg; | |
1605 | cur->dirty&=~(1<<hr); | |
1606 | cur->isconst&=~(1<<hr); | |
1607 | return; | |
1608 | } | |
1609 | } | |
1610 | } | |
1611 | } | |
1612 | } | |
1613 | SysPrintf("This shouldn't happen");abort(); | |
1614 | } | |
1615 | ||
1616 | static void mov_alloc(struct regstat *current,int i) | |
1617 | { | |
1618 | if (dops[i].rs1 == HIREG || dops[i].rs1 == LOREG) { | |
1619 | alloc_cc(current,i); // for stalls | |
1620 | dirty_reg(current,CCREG); | |
1621 | } | |
1622 | ||
1623 | // Note: Don't need to actually alloc the source registers | |
1624 | //alloc_reg(current,i,dops[i].rs1); | |
1625 | alloc_reg(current,i,dops[i].rt1); | |
1626 | ||
1627 | clear_const(current,dops[i].rs1); | |
1628 | clear_const(current,dops[i].rt1); | |
1629 | dirty_reg(current,dops[i].rt1); | |
1630 | } | |
1631 | ||
1632 | static void shiftimm_alloc(struct regstat *current,int i) | |
1633 | { | |
1634 | if(dops[i].opcode2<=0x3) // SLL/SRL/SRA | |
1635 | { | |
1636 | if(dops[i].rt1) { | |
1637 | if(dops[i].rs1&&needed_again(dops[i].rs1,i)) alloc_reg(current,i,dops[i].rs1); | |
1638 | else dops[i].lt1=dops[i].rs1; | |
1639 | alloc_reg(current,i,dops[i].rt1); | |
1640 | dirty_reg(current,dops[i].rt1); | |
1641 | if(is_const(current,dops[i].rs1)) { | |
1642 | int v=get_const(current,dops[i].rs1); | |
1643 | if(dops[i].opcode2==0x00) set_const(current,dops[i].rt1,v<<imm[i]); | |
1644 | if(dops[i].opcode2==0x02) set_const(current,dops[i].rt1,(u_int)v>>imm[i]); | |
1645 | if(dops[i].opcode2==0x03) set_const(current,dops[i].rt1,v>>imm[i]); | |
1646 | } | |
1647 | else clear_const(current,dops[i].rt1); | |
1648 | } | |
1649 | } | |
1650 | else | |
1651 | { | |
1652 | clear_const(current,dops[i].rs1); | |
1653 | clear_const(current,dops[i].rt1); | |
1654 | } | |
1655 | ||
1656 | if(dops[i].opcode2>=0x38&&dops[i].opcode2<=0x3b) // DSLL/DSRL/DSRA | |
1657 | { | |
1658 | assert(0); | |
1659 | } | |
1660 | if(dops[i].opcode2==0x3c) // DSLL32 | |
1661 | { | |
1662 | assert(0); | |
1663 | } | |
1664 | if(dops[i].opcode2==0x3e) // DSRL32 | |
1665 | { | |
1666 | assert(0); | |
1667 | } | |
1668 | if(dops[i].opcode2==0x3f) // DSRA32 | |
1669 | { | |
1670 | assert(0); | |
57871462 | 1671 | } |
1672 | } | |
1673 | ||
630b122b | 1674 | static void shift_alloc(struct regstat *current,int i) |
57871462 | 1675 | { |
630b122b | 1676 | if(dops[i].rt1) { |
1677 | if(dops[i].opcode2<=0x07) // SLLV/SRLV/SRAV | |
57871462 | 1678 | { |
630b122b | 1679 | if(dops[i].rs1) alloc_reg(current,i,dops[i].rs1); |
1680 | if(dops[i].rs2) alloc_reg(current,i,dops[i].rs2); | |
1681 | alloc_reg(current,i,dops[i].rt1); | |
1682 | if(dops[i].rt1==dops[i].rs2) { | |
e1190b87 | 1683 | alloc_reg_temp(current,i,-1); |
1684 | minimum_free_regs[i]=1; | |
1685 | } | |
57871462 | 1686 | } else { // DSLLV/DSRLV/DSRAV |
630b122b | 1687 | assert(0); |
57871462 | 1688 | } |
630b122b | 1689 | clear_const(current,dops[i].rs1); |
1690 | clear_const(current,dops[i].rs2); | |
1691 | clear_const(current,dops[i].rt1); | |
1692 | dirty_reg(current,dops[i].rt1); | |
57871462 | 1693 | } |
1694 | } | |
1695 | ||
630b122b | 1696 | static void alu_alloc(struct regstat *current,int i) |
57871462 | 1697 | { |
630b122b | 1698 | if(dops[i].opcode2>=0x20&&dops[i].opcode2<=0x23) { // ADD/ADDU/SUB/SUBU |
1699 | if(dops[i].rt1) { | |
1700 | if(dops[i].rs1&&dops[i].rs2) { | |
1701 | alloc_reg(current,i,dops[i].rs1); | |
1702 | alloc_reg(current,i,dops[i].rs2); | |
57871462 | 1703 | } |
1704 | else { | |
630b122b | 1705 | if(dops[i].rs1&&needed_again(dops[i].rs1,i)) alloc_reg(current,i,dops[i].rs1); |
1706 | if(dops[i].rs2&&needed_again(dops[i].rs2,i)) alloc_reg(current,i,dops[i].rs2); | |
57871462 | 1707 | } |
630b122b | 1708 | alloc_reg(current,i,dops[i].rt1); |
57871462 | 1709 | } |
57871462 | 1710 | } |
630b122b | 1711 | if(dops[i].opcode2==0x2a||dops[i].opcode2==0x2b) { // SLT/SLTU |
1712 | if(dops[i].rt1) { | |
1713 | alloc_reg(current,i,dops[i].rs1); | |
1714 | alloc_reg(current,i,dops[i].rs2); | |
1715 | alloc_reg(current,i,dops[i].rt1); | |
57871462 | 1716 | } |
57871462 | 1717 | } |
630b122b | 1718 | if(dops[i].opcode2>=0x24&&dops[i].opcode2<=0x27) { // AND/OR/XOR/NOR |
1719 | if(dops[i].rt1) { | |
1720 | if(dops[i].rs1&&dops[i].rs2) { | |
1721 | alloc_reg(current,i,dops[i].rs1); | |
1722 | alloc_reg(current,i,dops[i].rs2); | |
57871462 | 1723 | } |
1724 | else | |
1725 | { | |
630b122b | 1726 | if(dops[i].rs1&&needed_again(dops[i].rs1,i)) alloc_reg(current,i,dops[i].rs1); |
1727 | if(dops[i].rs2&&needed_again(dops[i].rs2,i)) alloc_reg(current,i,dops[i].rs2); | |
57871462 | 1728 | } |
630b122b | 1729 | alloc_reg(current,i,dops[i].rt1); |
57871462 | 1730 | } |
1731 | } | |
630b122b | 1732 | if(dops[i].opcode2>=0x2c&&dops[i].opcode2<=0x2f) { // DADD/DADDU/DSUB/DSUBU |
1733 | assert(0); | |
57871462 | 1734 | } |
630b122b | 1735 | clear_const(current,dops[i].rs1); |
1736 | clear_const(current,dops[i].rs2); | |
1737 | clear_const(current,dops[i].rt1); | |
1738 | dirty_reg(current,dops[i].rt1); | |
57871462 | 1739 | } |
1740 | ||
630b122b | 1741 | static void imm16_alloc(struct regstat *current,int i) |
57871462 | 1742 | { |
630b122b | 1743 | if(dops[i].rs1&&needed_again(dops[i].rs1,i)) alloc_reg(current,i,dops[i].rs1); |
1744 | else dops[i].lt1=dops[i].rs1; | |
1745 | if(dops[i].rt1) alloc_reg(current,i,dops[i].rt1); | |
1746 | if(dops[i].opcode==0x18||dops[i].opcode==0x19) { // DADDI/DADDIU | |
1747 | assert(0); | |
57871462 | 1748 | } |
630b122b | 1749 | else if(dops[i].opcode==0x0a||dops[i].opcode==0x0b) { // SLTI/SLTIU |
1750 | clear_const(current,dops[i].rs1); | |
1751 | clear_const(current,dops[i].rt1); | |
57871462 | 1752 | } |
630b122b | 1753 | else if(dops[i].opcode>=0x0c&&dops[i].opcode<=0x0e) { // ANDI/ORI/XORI |
1754 | if(is_const(current,dops[i].rs1)) { | |
1755 | int v=get_const(current,dops[i].rs1); | |
1756 | if(dops[i].opcode==0x0c) set_const(current,dops[i].rt1,v&imm[i]); | |
1757 | if(dops[i].opcode==0x0d) set_const(current,dops[i].rt1,v|imm[i]); | |
1758 | if(dops[i].opcode==0x0e) set_const(current,dops[i].rt1,v^imm[i]); | |
57871462 | 1759 | } |
630b122b | 1760 | else clear_const(current,dops[i].rt1); |
57871462 | 1761 | } |
630b122b | 1762 | else if(dops[i].opcode==0x08||dops[i].opcode==0x09) { // ADDI/ADDIU |
1763 | if(is_const(current,dops[i].rs1)) { | |
1764 | int v=get_const(current,dops[i].rs1); | |
1765 | set_const(current,dops[i].rt1,v+imm[i]); | |
57871462 | 1766 | } |
630b122b | 1767 | else clear_const(current,dops[i].rt1); |
57871462 | 1768 | } |
1769 | else { | |
630b122b | 1770 | set_const(current,dops[i].rt1,imm[i]<<16); // LUI |
57871462 | 1771 | } |
630b122b | 1772 | dirty_reg(current,dops[i].rt1); |
57871462 | 1773 | } |
1774 | ||
630b122b | 1775 | static void load_alloc(struct regstat *current,int i) |
57871462 | 1776 | { |
630b122b | 1777 | clear_const(current,dops[i].rt1); |
1778 | //if(dops[i].rs1!=dops[i].rt1&&needed_again(dops[i].rs1,i)) clear_const(current,dops[i].rs1); // Does this help or hurt? | |
1779 | if(!dops[i].rs1) current->u&=~1LL; // Allow allocating r0 if it's the source register | |
1780 | if (needed_again(dops[i].rs1, i)) | |
1781 | alloc_reg(current, i, dops[i].rs1); | |
1782 | if (ram_offset) | |
1783 | alloc_reg(current, i, ROREG); | |
1784 | if(dops[i].rt1&&!((current->u>>dops[i].rt1)&1)) { | |
1785 | alloc_reg(current,i,dops[i].rt1); | |
1786 | assert(get_reg(current->regmap,dops[i].rt1)>=0); | |
1787 | if(dops[i].opcode==0x27||dops[i].opcode==0x37) // LWU/LD | |
57871462 | 1788 | { |
630b122b | 1789 | assert(0); |
57871462 | 1790 | } |
630b122b | 1791 | else if(dops[i].opcode==0x1A||dops[i].opcode==0x1B) // LDL/LDR |
57871462 | 1792 | { |
630b122b | 1793 | assert(0); |
57871462 | 1794 | } |
630b122b | 1795 | dirty_reg(current,dops[i].rt1); |
57871462 | 1796 | // LWL/LWR need a temporary register for the old value |
630b122b | 1797 | if(dops[i].opcode==0x22||dops[i].opcode==0x26) |
57871462 | 1798 | { |
1799 | alloc_reg(current,i,FTEMP); | |
1800 | alloc_reg_temp(current,i,-1); | |
e1190b87 | 1801 | minimum_free_regs[i]=1; |
57871462 | 1802 | } |
1803 | } | |
1804 | else | |
1805 | { | |
373d1d07 | 1806 | // Load to r0 or unneeded register (dummy load) |
57871462 | 1807 | // but we still need a register to calculate the address |
630b122b | 1808 | if(dops[i].opcode==0x22||dops[i].opcode==0x26) |
535d208a | 1809 | { |
1810 | alloc_reg(current,i,FTEMP); // LWL/LWR need another temporary | |
1811 | } | |
57871462 | 1812 | alloc_reg_temp(current,i,-1); |
e1190b87 | 1813 | minimum_free_regs[i]=1; |
630b122b | 1814 | if(dops[i].opcode==0x1A||dops[i].opcode==0x1B) // LDL/LDR |
535d208a | 1815 | { |
630b122b | 1816 | assert(0); |
535d208a | 1817 | } |
57871462 | 1818 | } |
1819 | } | |
1820 | ||
1821 | void store_alloc(struct regstat *current,int i) | |
1822 | { | |
630b122b | 1823 | clear_const(current,dops[i].rs2); |
1824 | if(!(dops[i].rs2)) current->u&=~1LL; // Allow allocating r0 if necessary | |
1825 | if(needed_again(dops[i].rs1,i)) alloc_reg(current,i,dops[i].rs1); | |
1826 | alloc_reg(current,i,dops[i].rs2); | |
1827 | if(dops[i].opcode==0x2c||dops[i].opcode==0x2d||dops[i].opcode==0x3f) { // 64-bit SDL/SDR/SD | |
1828 | assert(0); | |
1829 | } | |
1830 | if (ram_offset) | |
1831 | alloc_reg(current, i, ROREG); | |
57871462 | 1832 | #if defined(HOST_IMM8) |
1833 | // On CPUs without 32-bit immediates we need a pointer to invalid_code | |
630b122b | 1834 | alloc_reg(current, i, INVCP); |
57871462 | 1835 | #endif |
630b122b | 1836 | if(dops[i].opcode==0x2a||dops[i].opcode==0x2e||dops[i].opcode==0x2c||dops[i].opcode==0x2d) { // SWL/SWL/SDL/SDR |
57871462 | 1837 | alloc_reg(current,i,FTEMP); |
1838 | } | |
1839 | // We need a temporary register for address generation | |
1840 | alloc_reg_temp(current,i,-1); | |
e1190b87 | 1841 | minimum_free_regs[i]=1; |
57871462 | 1842 | } |
1843 | ||
1844 | void c1ls_alloc(struct regstat *current,int i) | |
1845 | { | |
630b122b | 1846 | clear_const(current,dops[i].rt1); |
57871462 | 1847 | alloc_reg(current,i,CSREG); // Status |
57871462 | 1848 | } |
1849 | ||
b9b61529 | 1850 | void c2ls_alloc(struct regstat *current,int i) |
1851 | { | |
630b122b | 1852 | clear_const(current,dops[i].rt1); |
1853 | if(needed_again(dops[i].rs1,i)) alloc_reg(current,i,dops[i].rs1); | |
b9b61529 | 1854 | alloc_reg(current,i,FTEMP); |
630b122b | 1855 | if (ram_offset) |
1856 | alloc_reg(current, i, ROREG); | |
b9b61529 | 1857 | #if defined(HOST_IMM8) |
1858 | // On CPUs without 32-bit immediates we need a pointer to invalid_code | |
630b122b | 1859 | if (dops[i].opcode == 0x3a) // SWC2 |
b9b61529 | 1860 | alloc_reg(current,i,INVCP); |
1861 | #endif | |
1862 | // We need a temporary register for address generation | |
1863 | alloc_reg_temp(current,i,-1); | |
e1190b87 | 1864 | minimum_free_regs[i]=1; |
b9b61529 | 1865 | } |
1866 | ||
57871462 | 1867 | #ifndef multdiv_alloc |
1868 | void multdiv_alloc(struct regstat *current,int i) | |
1869 | { | |
1870 | // case 0x18: MULT | |
1871 | // case 0x19: MULTU | |
1872 | // case 0x1A: DIV | |
1873 | // case 0x1B: DIVU | |
1874 | // case 0x1C: DMULT | |
1875 | // case 0x1D: DMULTU | |
1876 | // case 0x1E: DDIV | |
1877 | // case 0x1F: DDIVU | |
630b122b | 1878 | clear_const(current,dops[i].rs1); |
1879 | clear_const(current,dops[i].rs2); | |
1880 | alloc_cc(current,i); // for stalls | |
1881 | if(dops[i].rs1&&dops[i].rs2) | |
57871462 | 1882 | { |
630b122b | 1883 | if((dops[i].opcode2&4)==0) // 32-bit |
57871462 | 1884 | { |
1885 | current->u&=~(1LL<<HIREG); | |
1886 | current->u&=~(1LL<<LOREG); | |
1887 | alloc_reg(current,i,HIREG); | |
1888 | alloc_reg(current,i,LOREG); | |
630b122b | 1889 | alloc_reg(current,i,dops[i].rs1); |
1890 | alloc_reg(current,i,dops[i].rs2); | |
57871462 | 1891 | dirty_reg(current,HIREG); |
1892 | dirty_reg(current,LOREG); | |
1893 | } | |
1894 | else // 64-bit | |
1895 | { | |
630b122b | 1896 | assert(0); |
57871462 | 1897 | } |
1898 | } | |
1899 | else | |
1900 | { | |
1901 | // Multiply by zero is zero. | |
1902 | // MIPS does not have a divide by zero exception. | |
1903 | // The result is undefined, we return zero. | |
1904 | alloc_reg(current,i,HIREG); | |
1905 | alloc_reg(current,i,LOREG); | |
57871462 | 1906 | dirty_reg(current,HIREG); |
1907 | dirty_reg(current,LOREG); | |
1908 | } | |
1909 | } | |
1910 | #endif | |
1911 | ||
1912 | void cop0_alloc(struct regstat *current,int i) | |
1913 | { | |
630b122b | 1914 | if(dops[i].opcode2==0) // MFC0 |
57871462 | 1915 | { |
630b122b | 1916 | if(dops[i].rt1) { |
1917 | clear_const(current,dops[i].rt1); | |
57871462 | 1918 | alloc_all(current,i); |
630b122b | 1919 | alloc_reg(current,i,dops[i].rt1); |
1920 | dirty_reg(current,dops[i].rt1); | |
57871462 | 1921 | } |
1922 | } | |
630b122b | 1923 | else if(dops[i].opcode2==4) // MTC0 |
57871462 | 1924 | { |
630b122b | 1925 | if(dops[i].rs1){ |
1926 | clear_const(current,dops[i].rs1); | |
1927 | alloc_reg(current,i,dops[i].rs1); | |
57871462 | 1928 | alloc_all(current,i); |
1929 | } | |
1930 | else { | |
1931 | alloc_all(current,i); // FIXME: Keep r0 | |
1932 | current->u&=~1LL; | |
1933 | alloc_reg(current,i,0); | |
1934 | } | |
1935 | } | |
1936 | else | |
1937 | { | |
1938 | // TLBR/TLBWI/TLBWR/TLBP/ERET | |
630b122b | 1939 | assert(dops[i].opcode2==0x10); |
57871462 | 1940 | alloc_all(current,i); |
1941 | } | |
e1190b87 | 1942 | minimum_free_regs[i]=HOST_REGS; |
57871462 | 1943 | } |
1944 | ||
630b122b | 1945 | static void cop2_alloc(struct regstat *current,int i) |
57871462 | 1946 | { |
630b122b | 1947 | if (dops[i].opcode2 < 3) // MFC2/CFC2 |
57871462 | 1948 | { |
630b122b | 1949 | alloc_cc(current,i); // for stalls |
1950 | dirty_reg(current,CCREG); | |
1951 | if(dops[i].rt1){ | |
1952 | clear_const(current,dops[i].rt1); | |
1953 | alloc_reg(current,i,dops[i].rt1); | |
1954 | dirty_reg(current,dops[i].rt1); | |
57871462 | 1955 | } |
57871462 | 1956 | } |
630b122b | 1957 | else if (dops[i].opcode2 > 3) // MTC2/CTC2 |
57871462 | 1958 | { |
630b122b | 1959 | if(dops[i].rs1){ |
1960 | clear_const(current,dops[i].rs1); | |
1961 | alloc_reg(current,i,dops[i].rs1); | |
57871462 | 1962 | } |
1963 | else { | |
1964 | current->u&=~1LL; | |
1965 | alloc_reg(current,i,0); | |
57871462 | 1966 | } |
1967 | } | |
57871462 | 1968 | alloc_reg_temp(current,i,-1); |
e1190b87 | 1969 | minimum_free_regs[i]=1; |
57871462 | 1970 | } |
630b122b | 1971 | |
b9b61529 | 1972 | void c2op_alloc(struct regstat *current,int i) |
1973 | { | |
630b122b | 1974 | alloc_cc(current,i); // for stalls |
1975 | dirty_reg(current,CCREG); | |
b9b61529 | 1976 | alloc_reg_temp(current,i,-1); |
1977 | } | |
57871462 | 1978 | |
1979 | void syscall_alloc(struct regstat *current,int i) | |
1980 | { | |
1981 | alloc_cc(current,i); | |
1982 | dirty_reg(current,CCREG); | |
1983 | alloc_all(current,i); | |
e1190b87 | 1984 | minimum_free_regs[i]=HOST_REGS; |
57871462 | 1985 | current->isconst=0; |
1986 | } | |
1987 | ||
1988 | void delayslot_alloc(struct regstat *current,int i) | |
1989 | { | |
630b122b | 1990 | switch(dops[i].itype) { |
57871462 | 1991 | case UJUMP: |
1992 | case CJUMP: | |
1993 | case SJUMP: | |
1994 | case RJUMP: | |
57871462 | 1995 | case SYSCALL: |
7139f3c8 | 1996 | case HLECALL: |
57871462 | 1997 | case SPAN: |
630b122b | 1998 | assem_debug("jump in the delay slot. this shouldn't happen.\n");//abort(); |
c43b5311 | 1999 | SysPrintf("Disabled speculative precompilation\n"); |
57871462 | 2000 | stop_after_jal=1; |
2001 | break; | |
2002 | case IMM16: | |
2003 | imm16_alloc(current,i); | |
2004 | break; | |
2005 | case LOAD: | |
2006 | case LOADLR: | |
2007 | load_alloc(current,i); | |
2008 | break; | |
2009 | case STORE: | |
2010 | case STORELR: | |
2011 | store_alloc(current,i); | |
2012 | break; | |
2013 | case ALU: | |
2014 | alu_alloc(current,i); | |
2015 | break; | |
2016 | case SHIFT: | |
2017 | shift_alloc(current,i); | |
2018 | break; | |
2019 | case MULTDIV: | |
2020 | multdiv_alloc(current,i); | |
2021 | break; | |
2022 | case SHIFTIMM: | |
2023 | shiftimm_alloc(current,i); | |
2024 | break; | |
2025 | case MOV: | |
2026 | mov_alloc(current,i); | |
2027 | break; | |
2028 | case COP0: | |
2029 | cop0_alloc(current,i); | |
2030 | break; | |
2031 | case COP1: | |
630b122b | 2032 | break; |
b9b61529 | 2033 | case COP2: |
630b122b | 2034 | cop2_alloc(current,i); |
57871462 | 2035 | break; |
2036 | case C1LS: | |
2037 | c1ls_alloc(current,i); | |
2038 | break; | |
b9b61529 | 2039 | case C2LS: |
2040 | c2ls_alloc(current,i); | |
2041 | break; | |
b9b61529 | 2042 | case C2OP: |
2043 | c2op_alloc(current,i); | |
2044 | break; | |
57871462 | 2045 | } |
2046 | } | |
2047 | ||
2048 | // Special case where a branch and delay slot span two pages in virtual memory | |
2049 | static void pagespan_alloc(struct regstat *current,int i) | |
2050 | { | |
2051 | current->isconst=0; | |
2052 | current->wasconst=0; | |
2053 | regs[i].wasconst=0; | |
e1190b87 | 2054 | minimum_free_regs[i]=HOST_REGS; |
57871462 | 2055 | alloc_all(current,i); |
2056 | alloc_cc(current,i); | |
2057 | dirty_reg(current,CCREG); | |
630b122b | 2058 | if(dops[i].opcode==3) // JAL |
57871462 | 2059 | { |
2060 | alloc_reg(current,i,31); | |
2061 | dirty_reg(current,31); | |
2062 | } | |
630b122b | 2063 | if(dops[i].opcode==0&&(dops[i].opcode2&0x3E)==8) // JR/JALR |
57871462 | 2064 | { |
630b122b | 2065 | alloc_reg(current,i,dops[i].rs1); |
2066 | if (dops[i].rt1!=0) { | |
2067 | alloc_reg(current,i,dops[i].rt1); | |
2068 | dirty_reg(current,dops[i].rt1); | |
57871462 | 2069 | } |
2070 | } | |
630b122b | 2071 | if((dops[i].opcode&0x2E)==4) // BEQ/BNE/BEQL/BNEL |
57871462 | 2072 | { |
630b122b | 2073 | if(dops[i].rs1) alloc_reg(current,i,dops[i].rs1); |
2074 | if(dops[i].rs2) alloc_reg(current,i,dops[i].rs2); | |
57871462 | 2075 | } |
2076 | else | |
630b122b | 2077 | if((dops[i].opcode&0x2E)==6) // BLEZ/BGTZ/BLEZL/BGTZL |
57871462 | 2078 | { |
630b122b | 2079 | if(dops[i].rs1) alloc_reg(current,i,dops[i].rs1); |
57871462 | 2080 | } |
2081 | //else ... | |
2082 | } | |
2083 | ||
630b122b | 2084 | static void add_stub(enum stub_type type, void *addr, void *retaddr, |
2085 | u_int a, uintptr_t b, uintptr_t c, u_int d, u_int e) | |
57871462 | 2086 | { |
630b122b | 2087 | assert(stubcount < ARRAY_SIZE(stubs)); |
2088 | stubs[stubcount].type = type; | |
2089 | stubs[stubcount].addr = addr; | |
2090 | stubs[stubcount].retaddr = retaddr; | |
2091 | stubs[stubcount].a = a; | |
2092 | stubs[stubcount].b = b; | |
2093 | stubs[stubcount].c = c; | |
2094 | stubs[stubcount].d = d; | |
2095 | stubs[stubcount].e = e; | |
57871462 | 2096 | stubcount++; |
2097 | } | |
2098 | ||
630b122b | 2099 | static void add_stub_r(enum stub_type type, void *addr, void *retaddr, |
2100 | int i, int addr_reg, const struct regstat *i_regs, int ccadj, u_int reglist) | |
2101 | { | |
2102 | add_stub(type, addr, retaddr, i, addr_reg, (uintptr_t)i_regs, ccadj, reglist); | |
2103 | } | |
2104 | ||
57871462 | 2105 | // Write out a single register |
630b122b | 2106 | static void wb_register(signed char r, const signed char regmap[], uint64_t dirty) |
57871462 | 2107 | { |
2108 | int hr; | |
2109 | for(hr=0;hr<HOST_REGS;hr++) { | |
2110 | if(hr!=EXCLUDE_REG) { | |
2111 | if((regmap[hr]&63)==r) { | |
2112 | if((dirty>>hr)&1) { | |
630b122b | 2113 | assert(regmap[hr]<64); |
2114 | emit_storereg(r,hr); | |
57871462 | 2115 | } |
2116 | } | |
2117 | } | |
2118 | } | |
2119 | } | |
2120 | ||
630b122b | 2121 | static void wb_valid(signed char pre[],signed char entry[],u_int dirty_pre,u_int dirty,uint64_t u) |
57871462 | 2122 | { |
630b122b | 2123 | //if(dirty_pre==dirty) return; |
2124 | int hr,reg; | |
2125 | for(hr=0;hr<HOST_REGS;hr++) { | |
2126 | if(hr!=EXCLUDE_REG) { | |
2127 | reg=pre[hr]; | |
2128 | if(((~u)>>(reg&63))&1) { | |
2129 | if(reg>0) { | |
2130 | if(((dirty_pre&~dirty)>>hr)&1) { | |
2131 | if(reg>0&®<34) { | |
2132 | emit_storereg(reg,hr); | |
2133 | } | |
2134 | else if(reg>=64) { | |
2135 | assert(0); | |
2136 | } | |
2137 | } | |
2138 | } | |
2139 | } | |
2140 | } | |
57871462 | 2141 | } |
57871462 | 2142 | } |
2143 | ||
630b122b | 2144 | // trashes r2 |
2145 | static void pass_args(int a0, int a1) | |
57871462 | 2146 | { |
630b122b | 2147 | if(a0==1&&a1==0) { |
2148 | // must swap | |
2149 | emit_mov(a0,2); emit_mov(a1,1); emit_mov(2,0); | |
2150 | } | |
2151 | else if(a0!=0&&a1==0) { | |
2152 | emit_mov(a1,1); | |
2153 | if (a0>=0) emit_mov(a0,0); | |
2154 | } | |
2155 | else { | |
2156 | if(a0>=0&&a0!=0) emit_mov(a0,0); | |
2157 | if(a1>=0&&a1!=1) emit_mov(a1,1); | |
57871462 | 2158 | } |
57871462 | 2159 | } |
2160 | ||
630b122b | 2161 | static void alu_assemble(int i, const struct regstat *i_regs) |
57871462 | 2162 | { |
630b122b | 2163 | if(dops[i].opcode2>=0x20&&dops[i].opcode2<=0x23) { // ADD/ADDU/SUB/SUBU |
2164 | if(dops[i].rt1) { | |
57871462 | 2165 | signed char s1,s2,t; |
630b122b | 2166 | t=get_reg(i_regs->regmap,dops[i].rt1); |
57871462 | 2167 | if(t>=0) { |
630b122b | 2168 | s1=get_reg(i_regs->regmap,dops[i].rs1); |
2169 | s2=get_reg(i_regs->regmap,dops[i].rs2); | |
2170 | if(dops[i].rs1&&dops[i].rs2) { | |
57871462 | 2171 | assert(s1>=0); |
2172 | assert(s2>=0); | |
630b122b | 2173 | if(dops[i].opcode2&2) emit_sub(s1,s2,t); |
57871462 | 2174 | else emit_add(s1,s2,t); |
2175 | } | |
630b122b | 2176 | else if(dops[i].rs1) { |
57871462 | 2177 | if(s1>=0) emit_mov(s1,t); |
630b122b | 2178 | else emit_loadreg(dops[i].rs1,t); |
57871462 | 2179 | } |
630b122b | 2180 | else if(dops[i].rs2) { |
57871462 | 2181 | if(s2>=0) { |
630b122b | 2182 | if(dops[i].opcode2&2) emit_neg(s2,t); |
57871462 | 2183 | else emit_mov(s2,t); |
2184 | } | |
2185 | else { | |
630b122b | 2186 | emit_loadreg(dops[i].rs2,t); |
2187 | if(dops[i].opcode2&2) emit_neg(t,t); | |
57871462 | 2188 | } |
2189 | } | |
2190 | else emit_zeroreg(t); | |
2191 | } | |
2192 | } | |
2193 | } | |
630b122b | 2194 | if(dops[i].opcode2>=0x2c&&dops[i].opcode2<=0x2f) { // DADD/DADDU/DSUB/DSUBU |
2195 | assert(0); | |
57871462 | 2196 | } |
630b122b | 2197 | if(dops[i].opcode2==0x2a||dops[i].opcode2==0x2b) { // SLT/SLTU |
2198 | if(dops[i].rt1) { | |
2199 | signed char s1l,s2l,t; | |
57871462 | 2200 | { |
630b122b | 2201 | t=get_reg(i_regs->regmap,dops[i].rt1); |
57871462 | 2202 | //assert(t>=0); |
2203 | if(t>=0) { | |
630b122b | 2204 | s1l=get_reg(i_regs->regmap,dops[i].rs1); |
2205 | s2l=get_reg(i_regs->regmap,dops[i].rs2); | |
2206 | if(dops[i].rs2==0) // rx<r0 | |
57871462 | 2207 | { |
630b122b | 2208 | if(dops[i].opcode2==0x2a&&dops[i].rs1!=0) { // SLT |
2209 | assert(s1l>=0); | |
57871462 | 2210 | emit_shrimm(s1l,31,t); |
630b122b | 2211 | } |
2212 | else // SLTU (unsigned can not be less than zero, 0<0) | |
57871462 | 2213 | emit_zeroreg(t); |
2214 | } | |
630b122b | 2215 | else if(dops[i].rs1==0) // r0<rx |
57871462 | 2216 | { |
2217 | assert(s2l>=0); | |
630b122b | 2218 | if(dops[i].opcode2==0x2a) // SLT |
57871462 | 2219 | emit_set_gz32(s2l,t); |
2220 | else // SLTU (set if not zero) | |
2221 | emit_set_nz32(s2l,t); | |
2222 | } | |
2223 | else{ | |
2224 | assert(s1l>=0);assert(s2l>=0); | |
630b122b | 2225 | if(dops[i].opcode2==0x2a) // SLT |
57871462 | 2226 | emit_set_if_less32(s1l,s2l,t); |
2227 | else // SLTU | |
2228 | emit_set_if_carry32(s1l,s2l,t); | |
2229 | } | |
2230 | } | |
2231 | } | |
2232 | } | |
2233 | } | |
630b122b | 2234 | if(dops[i].opcode2>=0x24&&dops[i].opcode2<=0x27) { // AND/OR/XOR/NOR |
2235 | if(dops[i].rt1) { | |
2236 | signed char s1l,s2l,tl; | |
2237 | tl=get_reg(i_regs->regmap,dops[i].rt1); | |
57871462 | 2238 | { |
57871462 | 2239 | if(tl>=0) { |
630b122b | 2240 | s1l=get_reg(i_regs->regmap,dops[i].rs1); |
2241 | s2l=get_reg(i_regs->regmap,dops[i].rs2); | |
2242 | if(dops[i].rs1&&dops[i].rs2) { | |
57871462 | 2243 | assert(s1l>=0); |
2244 | assert(s2l>=0); | |
630b122b | 2245 | if(dops[i].opcode2==0x24) { // AND |
57871462 | 2246 | emit_and(s1l,s2l,tl); |
2247 | } else | |
630b122b | 2248 | if(dops[i].opcode2==0x25) { // OR |
57871462 | 2249 | emit_or(s1l,s2l,tl); |
2250 | } else | |
630b122b | 2251 | if(dops[i].opcode2==0x26) { // XOR |
57871462 | 2252 | emit_xor(s1l,s2l,tl); |
2253 | } else | |
630b122b | 2254 | if(dops[i].opcode2==0x27) { // NOR |
57871462 | 2255 | emit_or(s1l,s2l,tl); |
2256 | emit_not(tl,tl); | |
2257 | } | |
2258 | } | |
2259 | else | |
2260 | { | |
630b122b | 2261 | if(dops[i].opcode2==0x24) { // AND |
57871462 | 2262 | emit_zeroreg(tl); |
2263 | } else | |
630b122b | 2264 | if(dops[i].opcode2==0x25||dops[i].opcode2==0x26) { // OR/XOR |
2265 | if(dops[i].rs1){ | |
57871462 | 2266 | if(s1l>=0) emit_mov(s1l,tl); |
630b122b | 2267 | else emit_loadreg(dops[i].rs1,tl); // CHECK: regmap_entry? |
57871462 | 2268 | } |
2269 | else | |
630b122b | 2270 | if(dops[i].rs2){ |
57871462 | 2271 | if(s2l>=0) emit_mov(s2l,tl); |
630b122b | 2272 | else emit_loadreg(dops[i].rs2,tl); // CHECK: regmap_entry? |
57871462 | 2273 | } |
2274 | else emit_zeroreg(tl); | |
2275 | } else | |
630b122b | 2276 | if(dops[i].opcode2==0x27) { // NOR |
2277 | if(dops[i].rs1){ | |
57871462 | 2278 | if(s1l>=0) emit_not(s1l,tl); |
2279 | else { | |
630b122b | 2280 | emit_loadreg(dops[i].rs1,tl); |
57871462 | 2281 | emit_not(tl,tl); |
2282 | } | |
2283 | } | |
2284 | else | |
630b122b | 2285 | if(dops[i].rs2){ |
57871462 | 2286 | if(s2l>=0) emit_not(s2l,tl); |
2287 | else { | |
630b122b | 2288 | emit_loadreg(dops[i].rs2,tl); |
57871462 | 2289 | emit_not(tl,tl); |
2290 | } | |
2291 | } | |
2292 | else emit_movimm(-1,tl); | |
2293 | } | |
2294 | } | |
2295 | } | |
2296 | } | |
2297 | } | |
2298 | } | |
2299 | } | |
2300 | ||
630b122b | 2301 | static void imm16_assemble(int i, const struct regstat *i_regs) |
57871462 | 2302 | { |
630b122b | 2303 | if (dops[i].opcode==0x0f) { // LUI |
2304 | if(dops[i].rt1) { | |
57871462 | 2305 | signed char t; |
630b122b | 2306 | t=get_reg(i_regs->regmap,dops[i].rt1); |
57871462 | 2307 | //assert(t>=0); |
2308 | if(t>=0) { | |
2309 | if(!((i_regs->isconst>>t)&1)) | |
2310 | emit_movimm(imm[i]<<16,t); | |
2311 | } | |
2312 | } | |
2313 | } | |
630b122b | 2314 | if(dops[i].opcode==0x08||dops[i].opcode==0x09) { // ADDI/ADDIU |
2315 | if(dops[i].rt1) { | |
57871462 | 2316 | signed char s,t; |
630b122b | 2317 | t=get_reg(i_regs->regmap,dops[i].rt1); |
2318 | s=get_reg(i_regs->regmap,dops[i].rs1); | |
2319 | if(dops[i].rs1) { | |
57871462 | 2320 | //assert(t>=0); |
2321 | //assert(s>=0); | |
2322 | if(t>=0) { | |
2323 | if(!((i_regs->isconst>>t)&1)) { | |
2324 | if(s<0) { | |
630b122b | 2325 | if(i_regs->regmap_entry[t]!=dops[i].rs1) emit_loadreg(dops[i].rs1,t); |
57871462 | 2326 | emit_addimm(t,imm[i],t); |
2327 | }else{ | |
2328 | if(!((i_regs->wasconst>>s)&1)) | |
2329 | emit_addimm(s,imm[i],t); | |
2330 | else | |
2331 | emit_movimm(constmap[i][s]+imm[i],t); | |
2332 | } | |
2333 | } | |
2334 | } | |
2335 | } else { | |
2336 | if(t>=0) { | |
2337 | if(!((i_regs->isconst>>t)&1)) | |
2338 | emit_movimm(imm[i],t); | |
2339 | } | |
2340 | } | |
2341 | } | |
2342 | } | |
630b122b | 2343 | if(dops[i].opcode==0x18||dops[i].opcode==0x19) { // DADDI/DADDIU |
2344 | if(dops[i].rt1) { | |
2345 | signed char sl,tl; | |
2346 | tl=get_reg(i_regs->regmap,dops[i].rt1); | |
2347 | sl=get_reg(i_regs->regmap,dops[i].rs1); | |
57871462 | 2348 | if(tl>=0) { |
630b122b | 2349 | if(dops[i].rs1) { |
57871462 | 2350 | assert(sl>=0); |
630b122b | 2351 | emit_addimm(sl,imm[i],tl); |
57871462 | 2352 | } else { |
2353 | emit_movimm(imm[i],tl); | |
57871462 | 2354 | } |
2355 | } | |
2356 | } | |
2357 | } | |
630b122b | 2358 | else if(dops[i].opcode==0x0a||dops[i].opcode==0x0b) { // SLTI/SLTIU |
2359 | if(dops[i].rt1) { | |
2360 | //assert(dops[i].rs1!=0); // r0 might be valid, but it's probably a bug | |
2361 | signed char sl,t; | |
2362 | t=get_reg(i_regs->regmap,dops[i].rt1); | |
2363 | sl=get_reg(i_regs->regmap,dops[i].rs1); | |
57871462 | 2364 | //assert(t>=0); |
2365 | if(t>=0) { | |
630b122b | 2366 | if(dops[i].rs1>0) { |
2367 | if(dops[i].opcode==0x0a) { // SLTI | |
57871462 | 2368 | if(sl<0) { |
630b122b | 2369 | if(i_regs->regmap_entry[t]!=dops[i].rs1) emit_loadreg(dops[i].rs1,t); |
57871462 | 2370 | emit_slti32(t,imm[i],t); |
2371 | }else{ | |
2372 | emit_slti32(sl,imm[i],t); | |
2373 | } | |
2374 | } | |
2375 | else { // SLTIU | |
2376 | if(sl<0) { | |
630b122b | 2377 | if(i_regs->regmap_entry[t]!=dops[i].rs1) emit_loadreg(dops[i].rs1,t); |
57871462 | 2378 | emit_sltiu32(t,imm[i],t); |
2379 | }else{ | |
2380 | emit_sltiu32(sl,imm[i],t); | |
2381 | } | |
2382 | } | |
57871462 | 2383 | }else{ |
2384 | // SLTI(U) with r0 is just stupid, | |
2385 | // nonetheless examples can be found | |
630b122b | 2386 | if(dops[i].opcode==0x0a) // SLTI |
57871462 | 2387 | if(0<imm[i]) emit_movimm(1,t); |
2388 | else emit_zeroreg(t); | |
2389 | else // SLTIU | |
2390 | { | |
2391 | if(imm[i]) emit_movimm(1,t); | |
2392 | else emit_zeroreg(t); | |
2393 | } | |
2394 | } | |
2395 | } | |
2396 | } | |
2397 | } | |
630b122b | 2398 | else if(dops[i].opcode>=0x0c&&dops[i].opcode<=0x0e) { // ANDI/ORI/XORI |
2399 | if(dops[i].rt1) { | |
2400 | signed char sl,tl; | |
2401 | tl=get_reg(i_regs->regmap,dops[i].rt1); | |
2402 | sl=get_reg(i_regs->regmap,dops[i].rs1); | |
57871462 | 2403 | if(tl>=0 && !((i_regs->isconst>>tl)&1)) { |
630b122b | 2404 | if(dops[i].opcode==0x0c) //ANDI |
57871462 | 2405 | { |
630b122b | 2406 | if(dops[i].rs1) { |
57871462 | 2407 | if(sl<0) { |
630b122b | 2408 | if(i_regs->regmap_entry[tl]!=dops[i].rs1) emit_loadreg(dops[i].rs1,tl); |
57871462 | 2409 | emit_andimm(tl,imm[i],tl); |
2410 | }else{ | |
2411 | if(!((i_regs->wasconst>>sl)&1)) | |
2412 | emit_andimm(sl,imm[i],tl); | |
2413 | else | |
2414 | emit_movimm(constmap[i][sl]&imm[i],tl); | |
2415 | } | |
2416 | } | |
2417 | else | |
2418 | emit_zeroreg(tl); | |
57871462 | 2419 | } |
2420 | else | |
2421 | { | |
630b122b | 2422 | if(dops[i].rs1) { |
57871462 | 2423 | if(sl<0) { |
630b122b | 2424 | if(i_regs->regmap_entry[tl]!=dops[i].rs1) emit_loadreg(dops[i].rs1,tl); |
57871462 | 2425 | } |
630b122b | 2426 | if(dops[i].opcode==0x0d) { // ORI |
581335b0 | 2427 | if(sl<0) { |
2428 | emit_orimm(tl,imm[i],tl); | |
2429 | }else{ | |
2430 | if(!((i_regs->wasconst>>sl)&1)) | |
2431 | emit_orimm(sl,imm[i],tl); | |
2432 | else | |
2433 | emit_movimm(constmap[i][sl]|imm[i],tl); | |
2434 | } | |
57871462 | 2435 | } |
630b122b | 2436 | if(dops[i].opcode==0x0e) { // XORI |
581335b0 | 2437 | if(sl<0) { |
2438 | emit_xorimm(tl,imm[i],tl); | |
2439 | }else{ | |
2440 | if(!((i_regs->wasconst>>sl)&1)) | |
2441 | emit_xorimm(sl,imm[i],tl); | |
2442 | else | |
2443 | emit_movimm(constmap[i][sl]^imm[i],tl); | |
2444 | } | |
57871462 | 2445 | } |
2446 | } | |
2447 | else { | |
2448 | emit_movimm(imm[i],tl); | |
57871462 | 2449 | } |
2450 | } | |
2451 | } | |
2452 | } | |
2453 | } | |
2454 | } | |
2455 | ||
630b122b | 2456 | static void shiftimm_assemble(int i, const struct regstat *i_regs) |
57871462 | 2457 | { |
630b122b | 2458 | if(dops[i].opcode2<=0x3) // SLL/SRL/SRA |
57871462 | 2459 | { |
630b122b | 2460 | if(dops[i].rt1) { |
57871462 | 2461 | signed char s,t; |
630b122b | 2462 | t=get_reg(i_regs->regmap,dops[i].rt1); |
2463 | s=get_reg(i_regs->regmap,dops[i].rs1); | |
57871462 | 2464 | //assert(t>=0); |
dc49e339 | 2465 | if(t>=0&&!((i_regs->isconst>>t)&1)){ |
630b122b | 2466 | if(dops[i].rs1==0) |
57871462 | 2467 | { |
2468 | emit_zeroreg(t); | |
2469 | } | |
2470 | else | |
2471 | { | |
630b122b | 2472 | if(s<0&&i_regs->regmap_entry[t]!=dops[i].rs1) emit_loadreg(dops[i].rs1,t); |
57871462 | 2473 | if(imm[i]) { |
630b122b | 2474 | if(dops[i].opcode2==0) // SLL |
57871462 | 2475 | { |
2476 | emit_shlimm(s<0?t:s,imm[i],t); | |
2477 | } | |
630b122b | 2478 | if(dops[i].opcode2==2) // SRL |
57871462 | 2479 | { |
2480 | emit_shrimm(s<0?t:s,imm[i],t); | |
2481 | } | |
630b122b | 2482 | if(dops[i].opcode2==3) // SRA |
57871462 | 2483 | { |
2484 | emit_sarimm(s<0?t:s,imm[i],t); | |
2485 | } | |
2486 | }else{ | |
2487 | // Shift by zero | |
2488 | if(s>=0 && s!=t) emit_mov(s,t); | |
2489 | } | |
2490 | } | |
2491 | } | |
630b122b | 2492 | //emit_storereg(dops[i].rt1,t); //DEBUG |
57871462 | 2493 | } |
2494 | } | |
630b122b | 2495 | if(dops[i].opcode2>=0x38&&dops[i].opcode2<=0x3b) // DSLL/DSRL/DSRA |
57871462 | 2496 | { |
630b122b | 2497 | assert(0); |
57871462 | 2498 | } |
630b122b | 2499 | if(dops[i].opcode2==0x3c) // DSLL32 |
57871462 | 2500 | { |
630b122b | 2501 | assert(0); |
57871462 | 2502 | } |
630b122b | 2503 | if(dops[i].opcode2==0x3e) // DSRL32 |
57871462 | 2504 | { |
630b122b | 2505 | assert(0); |
57871462 | 2506 | } |
630b122b | 2507 | if(dops[i].opcode2==0x3f) // DSRA32 |
57871462 | 2508 | { |
630b122b | 2509 | assert(0); |
57871462 | 2510 | } |
2511 | } | |
2512 | ||
2513 | #ifndef shift_assemble | |
630b122b | 2514 | static void shift_assemble(int i, const struct regstat *i_regs) |
57871462 | 2515 | { |
630b122b | 2516 | signed char s,t,shift; |
2517 | if (dops[i].rt1 == 0) | |
2518 | return; | |
2519 | assert(dops[i].opcode2<=0x07); // SLLV/SRLV/SRAV | |
2520 | t = get_reg(i_regs->regmap, dops[i].rt1); | |
2521 | s = get_reg(i_regs->regmap, dops[i].rs1); | |
2522 | shift = get_reg(i_regs->regmap, dops[i].rs2); | |
2523 | if (t < 0) | |
2524 | return; | |
2525 | ||
2526 | if(dops[i].rs1==0) | |
2527 | emit_zeroreg(t); | |
2528 | else if(dops[i].rs2==0) { | |
2529 | assert(s>=0); | |
2530 | if(s!=t) emit_mov(s,t); | |
2531 | } | |
2532 | else { | |
2533 | host_tempreg_acquire(); | |
2534 | emit_andimm(shift,31,HOST_TEMPREG); | |
2535 | switch(dops[i].opcode2) { | |
2536 | case 4: // SLLV | |
2537 | emit_shl(s,HOST_TEMPREG,t); | |
2538 | break; | |
2539 | case 6: // SRLV | |
2540 | emit_shr(s,HOST_TEMPREG,t); | |
2541 | break; | |
2542 | case 7: // SRAV | |
2543 | emit_sar(s,HOST_TEMPREG,t); | |
2544 | break; | |
2545 | default: | |
2546 | assert(0); | |
2547 | } | |
2548 | host_tempreg_release(); | |
2549 | } | |
57871462 | 2550 | } |
630b122b | 2551 | |
57871462 | 2552 | #endif |
2553 | ||
630b122b | 2554 | enum { |
2555 | MTYPE_8000 = 0, | |
2556 | MTYPE_8020, | |
2557 | MTYPE_0000, | |
2558 | MTYPE_A000, | |
2559 | MTYPE_1F80, | |
2560 | }; | |
2561 | ||
2562 | static int get_ptr_mem_type(u_int a) | |
2563 | { | |
2564 | if(a < 0x00200000) { | |
2565 | if(a<0x1000&&((start>>20)==0xbfc||(start>>24)==0xa0)) | |
2566 | // return wrong, must use memhandler for BIOS self-test to pass | |
2567 | // 007 does similar stuff from a00 mirror, weird stuff | |
2568 | return MTYPE_8000; | |
2569 | return MTYPE_0000; | |
2570 | } | |
2571 | if(0x1f800000 <= a && a < 0x1f801000) | |
2572 | return MTYPE_1F80; | |
2573 | if(0x80200000 <= a && a < 0x80800000) | |
2574 | return MTYPE_8020; | |
2575 | if(0xa0000000 <= a && a < 0xa0200000) | |
2576 | return MTYPE_A000; | |
2577 | return MTYPE_8000; | |
2578 | } | |
2579 | ||
2580 | static int get_ro_reg(const struct regstat *i_regs, int host_tempreg_free) | |
2581 | { | |
2582 | int r = get_reg(i_regs->regmap, ROREG); | |
2583 | if (r < 0 && host_tempreg_free) { | |
2584 | host_tempreg_acquire(); | |
2585 | emit_loadreg(ROREG, r = HOST_TEMPREG); | |
2586 | } | |
2587 | if (r < 0) | |
2588 | abort(); | |
2589 | return r; | |
2590 | } | |
2591 | ||
2592 | static void *emit_fastpath_cmp_jump(int i, const struct regstat *i_regs, | |
2593 | int addr, int *offset_reg, int *addr_reg_override) | |
2594 | { | |
2595 | void *jaddr = NULL; | |
2596 | int type = 0; | |
2597 | int mr = dops[i].rs1; | |
2598 | *offset_reg = -1; | |
2599 | if(((smrv_strong|smrv_weak)>>mr)&1) { | |
2600 | type=get_ptr_mem_type(smrv[mr]); | |
2601 | //printf("set %08x @%08x r%d %d\n", smrv[mr], start+i*4, mr, type); | |
2602 | } | |
2603 | else { | |
2604 | // use the mirror we are running on | |
2605 | type=get_ptr_mem_type(start); | |
2606 | //printf("set nospec @%08x r%d %d\n", start+i*4, mr, type); | |
2607 | } | |
2608 | ||
2609 | if(type==MTYPE_8020) { // RAM 80200000+ mirror | |
2610 | host_tempreg_acquire(); | |
2611 | emit_andimm(addr,~0x00e00000,HOST_TEMPREG); | |
2612 | addr=*addr_reg_override=HOST_TEMPREG; | |
2613 | type=0; | |
2614 | } | |
2615 | else if(type==MTYPE_0000) { // RAM 0 mirror | |
2616 | host_tempreg_acquire(); | |
2617 | emit_orimm(addr,0x80000000,HOST_TEMPREG); | |
2618 | addr=*addr_reg_override=HOST_TEMPREG; | |
2619 | type=0; | |
2620 | } | |
2621 | else if(type==MTYPE_A000) { // RAM A mirror | |
2622 | host_tempreg_acquire(); | |
2623 | emit_andimm(addr,~0x20000000,HOST_TEMPREG); | |
2624 | addr=*addr_reg_override=HOST_TEMPREG; | |
2625 | type=0; | |
2626 | } | |
2627 | else if(type==MTYPE_1F80) { // scratchpad | |
2628 | if (psxH == (void *)0x1f800000) { | |
2629 | host_tempreg_acquire(); | |
2630 | emit_xorimm(addr,0x1f800000,HOST_TEMPREG); | |
2631 | emit_cmpimm(HOST_TEMPREG,0x1000); | |
2632 | host_tempreg_release(); | |
2633 | jaddr=out; | |
2634 | emit_jc(0); | |
2635 | } | |
2636 | else { | |
2637 | // do the usual RAM check, jump will go to the right handler | |
2638 | type=0; | |
2639 | } | |
2640 | } | |
2641 | ||
2642 | if (type == 0) // need ram check | |
2643 | { | |
2644 | emit_cmpimm(addr,RAM_SIZE); | |
2645 | jaddr = out; | |
2646 | #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK | |
2647 | // Hint to branch predictor that the branch is unlikely to be taken | |
2648 | if (dops[i].rs1 >= 28) | |
2649 | emit_jno_unlikely(0); | |
2650 | else | |
2651 | #endif | |
2652 | emit_jno(0); | |
2653 | if (ram_offset != 0) | |
2654 | *offset_reg = get_ro_reg(i_regs, 0); | |
2655 | } | |
2656 | ||
2657 | return jaddr; | |
2658 | } | |
2659 | ||
2660 | // return memhandler, or get directly accessable address and return 0 | |
2661 | static void *get_direct_memhandler(void *table, u_int addr, | |
2662 | enum stub_type type, uintptr_t *addr_host) | |
2663 | { | |
2664 | uintptr_t msb = 1ull << (sizeof(uintptr_t)*8 - 1); | |
2665 | uintptr_t l1, l2 = 0; | |
2666 | l1 = ((uintptr_t *)table)[addr>>12]; | |
2667 | if (!(l1 & msb)) { | |
2668 | uintptr_t v = l1 << 1; | |
2669 | *addr_host = v + addr; | |
2670 | return NULL; | |
2671 | } | |
2672 | else { | |
2673 | l1 <<= 1; | |
2674 | if (type == LOADB_STUB || type == LOADBU_STUB || type == STOREB_STUB) | |
2675 | l2 = ((uintptr_t *)l1)[0x1000/4 + 0x1000/2 + (addr&0xfff)]; | |
2676 | else if (type == LOADH_STUB || type == LOADHU_STUB || type == STOREH_STUB) | |
2677 | l2 = ((uintptr_t *)l1)[0x1000/4 + (addr&0xfff)/2]; | |
2678 | else | |
2679 | l2 = ((uintptr_t *)l1)[(addr&0xfff)/4]; | |
2680 | if (!(l2 & msb)) { | |
2681 | uintptr_t v = l2 << 1; | |
2682 | *addr_host = v + (addr&0xfff); | |
2683 | return NULL; | |
2684 | } | |
2685 | return (void *)(l2 << 1); | |
2686 | } | |
2687 | } | |
2688 | ||
2689 | static u_int get_host_reglist(const signed char *regmap) | |
2690 | { | |
2691 | u_int reglist = 0, hr; | |
2692 | for (hr = 0; hr < HOST_REGS; hr++) { | |
2693 | if (hr != EXCLUDE_REG && regmap[hr] >= 0) | |
2694 | reglist |= 1 << hr; | |
2695 | } | |
2696 | return reglist; | |
2697 | } | |
2698 | ||
2699 | static u_int reglist_exclude(u_int reglist, int r1, int r2) | |
2700 | { | |
2701 | if (r1 >= 0) | |
2702 | reglist &= ~(1u << r1); | |
2703 | if (r2 >= 0) | |
2704 | reglist &= ~(1u << r2); | |
2705 | return reglist; | |
2706 | } | |
2707 | ||
2708 | // find a temp caller-saved register not in reglist (so assumed to be free) | |
2709 | static int reglist_find_free(u_int reglist) | |
2710 | { | |
2711 | u_int free_regs = ~reglist & CALLER_SAVE_REGS; | |
2712 | if (free_regs == 0) | |
2713 | return -1; | |
2714 | return __builtin_ctz(free_regs); | |
2715 | } | |
2716 | ||
2717 | static void do_load_word(int a, int rt, int offset_reg) | |
2718 | { | |
2719 | if (offset_reg >= 0) | |
2720 | emit_ldr_dualindexed(offset_reg, a, rt); | |
2721 | else | |
2722 | emit_readword_indexed(0, a, rt); | |
2723 | } | |
2724 | ||
2725 | static void do_store_word(int a, int ofs, int rt, int offset_reg, int preseve_a) | |
2726 | { | |
2727 | if (offset_reg < 0) { | |
2728 | emit_writeword_indexed(rt, ofs, a); | |
2729 | return; | |
2730 | } | |
2731 | if (ofs != 0) | |
2732 | emit_addimm(a, ofs, a); | |
2733 | emit_str_dualindexed(offset_reg, a, rt); | |
2734 | if (ofs != 0 && preseve_a) | |
2735 | emit_addimm(a, -ofs, a); | |
2736 | } | |
2737 | ||
2738 | static void do_store_hword(int a, int ofs, int rt, int offset_reg, int preseve_a) | |
2739 | { | |
2740 | if (offset_reg < 0) { | |
2741 | emit_writehword_indexed(rt, ofs, a); | |
2742 | return; | |
2743 | } | |
2744 | if (ofs != 0) | |
2745 | emit_addimm(a, ofs, a); | |
2746 | emit_strh_dualindexed(offset_reg, a, rt); | |
2747 | if (ofs != 0 && preseve_a) | |
2748 | emit_addimm(a, -ofs, a); | |
2749 | } | |
2750 | ||
2751 | static void do_store_byte(int a, int rt, int offset_reg) | |
2752 | { | |
2753 | if (offset_reg >= 0) | |
2754 | emit_strb_dualindexed(offset_reg, a, rt); | |
2755 | else | |
2756 | emit_writebyte_indexed(rt, 0, a); | |
2757 | } | |
2758 | ||
2759 | static void load_assemble(int i, const struct regstat *i_regs, int ccadj_) | |
57871462 | 2760 | { |
630b122b | 2761 | int s,tl,addr; |
57871462 | 2762 | int offset; |
630b122b | 2763 | void *jaddr=0; |
5bf843dc | 2764 | int memtarget=0,c=0; |
630b122b | 2765 | int offset_reg = -1; |
2766 | int fastio_reg_override = -1; | |
2767 | u_int reglist=get_host_reglist(i_regs->regmap); | |
2768 | tl=get_reg(i_regs->regmap,dops[i].rt1); | |
2769 | s=get_reg(i_regs->regmap,dops[i].rs1); | |
57871462 | 2770 | offset=imm[i]; |
57871462 | 2771 | if(i_regs->regmap[HOST_CCREG]==CCREG) reglist&=~(1<<HOST_CCREG); |
2772 | if(s>=0) { | |
2773 | c=(i_regs->wasconst>>s)&1; | |
af4ee1fe | 2774 | if (c) { |
2775 | memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE; | |
af4ee1fe | 2776 | } |
57871462 | 2777 | } |
57871462 | 2778 | //printf("load_assemble: c=%d\n",c); |
630b122b | 2779 | //if(c) printf("load_assemble: const=%lx\n",(long)constmap[i][s]+offset); |
57871462 | 2780 | // FIXME: Even if the load is a NOP, we should check for pagefaults... |
581335b0 | 2781 | if((tl<0&&(!c||(((u_int)constmap[i][s]+offset)>>16)==0x1f80)) |
630b122b | 2782 | ||dops[i].rt1==0) { |
5bf843dc | 2783 | // could be FIFO, must perform the read |
f18c0f46 | 2784 | // ||dummy read |
5bf843dc | 2785 | assem_debug("(forced read)\n"); |
2786 | tl=get_reg(i_regs->regmap,-1); | |
2787 | assert(tl>=0); | |
5bf843dc | 2788 | } |
2789 | if(offset||s<0||c) addr=tl; | |
2790 | else addr=s; | |
535d208a | 2791 | //if(tl<0) tl=get_reg(i_regs->regmap,-1); |
2792 | if(tl>=0) { | |
2793 | //printf("load_assemble: c=%d\n",c); | |
630b122b | 2794 | //if(c) printf("load_assemble: const=%lx\n",(long)constmap[i][s]+offset); |
535d208a | 2795 | assert(tl>=0); // Even if the load is a NOP, we must check for pagefaults and I/O |
2796 | reglist&=~(1<<tl); | |
1edfcc68 | 2797 | if(!c) { |
1edfcc68 | 2798 | #ifdef R29_HACK |
2799 | // Strmnnrmn's speed hack | |
630b122b | 2800 | if(dops[i].rs1!=29||start<0x80001000||start>=0x80000000+RAM_SIZE) |
1edfcc68 | 2801 | #endif |
2802 | { | |
630b122b | 2803 | jaddr = emit_fastpath_cmp_jump(i, i_regs, addr, |
2804 | &offset_reg, &fastio_reg_override); | |
535d208a | 2805 | } |
1edfcc68 | 2806 | } |
630b122b | 2807 | else if (ram_offset && memtarget) { |
2808 | offset_reg = get_ro_reg(i_regs, 0); | |
535d208a | 2809 | } |
630b122b | 2810 | int dummy=(dops[i].rt1==0)||(tl!=get_reg(i_regs->regmap,dops[i].rt1)); // ignore loads to r0 and unneeded reg |
2811 | switch (dops[i].opcode) { | |
2812 | case 0x20: // LB | |
535d208a | 2813 | if(!c||memtarget) { |
2814 | if(!dummy) { | |
630b122b | 2815 | int a = tl; |
2816 | if (!c) a = addr; | |
2817 | if (fastio_reg_override >= 0) | |
2818 | a = fastio_reg_override; | |
b1570849 | 2819 | |
630b122b | 2820 | if (offset_reg >= 0) |
2821 | emit_ldrsb_dualindexed(offset_reg, a, tl); | |
2822 | else | |
2823 | emit_movsbl_indexed(0, a, tl); | |
57871462 | 2824 | } |
535d208a | 2825 | if(jaddr) |
630b122b | 2826 | add_stub_r(LOADB_STUB,jaddr,out,i,addr,i_regs,ccadj_,reglist); |
57871462 | 2827 | } |
535d208a | 2828 | else |
630b122b | 2829 | inline_readstub(LOADB_STUB,i,constmap[i][s]+offset,i_regs->regmap,dops[i].rt1,ccadj_,reglist); |
2830 | break; | |
2831 | case 0x21: // LH | |
535d208a | 2832 | if(!c||memtarget) { |
2833 | if(!dummy) { | |
630b122b | 2834 | int a = tl; |
2835 | if (!c) a = addr; | |
2836 | if (fastio_reg_override >= 0) | |
2837 | a = fastio_reg_override; | |
2838 | if (offset_reg >= 0) | |
2839 | emit_ldrsh_dualindexed(offset_reg, a, tl); | |
57871462 | 2840 | else |
630b122b | 2841 | emit_movswl_indexed(0, a, tl); |
57871462 | 2842 | } |
535d208a | 2843 | if(jaddr) |
630b122b | 2844 | add_stub_r(LOADH_STUB,jaddr,out,i,addr,i_regs,ccadj_,reglist); |
57871462 | 2845 | } |
535d208a | 2846 | else |
630b122b | 2847 | inline_readstub(LOADH_STUB,i,constmap[i][s]+offset,i_regs->regmap,dops[i].rt1,ccadj_,reglist); |
2848 | break; | |
2849 | case 0x23: // LW | |
535d208a | 2850 | if(!c||memtarget) { |
2851 | if(!dummy) { | |
630b122b | 2852 | int a = addr; |
2853 | if (fastio_reg_override >= 0) | |
2854 | a = fastio_reg_override; | |
2855 | do_load_word(a, tl, offset_reg); | |
57871462 | 2856 | } |
535d208a | 2857 | if(jaddr) |
630b122b | 2858 | add_stub_r(LOADW_STUB,jaddr,out,i,addr,i_regs,ccadj_,reglist); |
57871462 | 2859 | } |
535d208a | 2860 | else |
630b122b | 2861 | inline_readstub(LOADW_STUB,i,constmap[i][s]+offset,i_regs->regmap,dops[i].rt1,ccadj_,reglist); |
2862 | break; | |
2863 | case 0x24: // LBU | |
535d208a | 2864 | if(!c||memtarget) { |
2865 | if(!dummy) { | |
630b122b | 2866 | int a = tl; |
2867 | if (!c) a = addr; | |
2868 | if (fastio_reg_override >= 0) | |
2869 | a = fastio_reg_override; | |
b1570849 | 2870 | |
630b122b | 2871 | if (offset_reg >= 0) |
2872 | emit_ldrb_dualindexed(offset_reg, a, tl); | |
2873 | else | |
2874 | emit_movzbl_indexed(0, a, tl); | |
57871462 | 2875 | } |
535d208a | 2876 | if(jaddr) |
630b122b | 2877 | add_stub_r(LOADBU_STUB,jaddr,out,i,addr,i_regs,ccadj_,reglist); |
57871462 | 2878 | } |
535d208a | 2879 | else |
630b122b | 2880 | inline_readstub(LOADBU_STUB,i,constmap[i][s]+offset,i_regs->regmap,dops[i].rt1,ccadj_,reglist); |
2881 | break; | |
2882 | case 0x25: // LHU | |
535d208a | 2883 | if(!c||memtarget) { |
2884 | if(!dummy) { | |
630b122b | 2885 | int a = tl; |
2886 | if(!c) a = addr; | |
2887 | if (fastio_reg_override >= 0) | |
2888 | a = fastio_reg_override; | |
2889 | if (offset_reg >= 0) | |
2890 | emit_ldrh_dualindexed(offset_reg, a, tl); | |
57871462 | 2891 | else |
630b122b | 2892 | emit_movzwl_indexed(0, a, tl); |
57871462 | 2893 | } |
535d208a | 2894 | if(jaddr) |
630b122b | 2895 | add_stub_r(LOADHU_STUB,jaddr,out,i,addr,i_regs,ccadj_,reglist); |
57871462 | 2896 | } |
535d208a | 2897 | else |
630b122b | 2898 | inline_readstub(LOADHU_STUB,i,constmap[i][s]+offset,i_regs->regmap,dops[i].rt1,ccadj_,reglist); |
2899 | break; | |
2900 | case 0x27: // LWU | |
2901 | case 0x37: // LD | |
2902 | default: | |
2903 | assert(0); | |
535d208a | 2904 | } |
630b122b | 2905 | } |
2906 | if (fastio_reg_override == HOST_TEMPREG || offset_reg == HOST_TEMPREG) | |
2907 | host_tempreg_release(); | |
2908 | } | |
2909 | ||
2910 | #ifndef loadlr_assemble | |
2911 | static void loadlr_assemble(int i, const struct regstat *i_regs, int ccadj_) | |
2912 | { | |
2913 | int s,tl,temp,temp2,addr; | |
2914 | int offset; | |
2915 | void *jaddr=0; | |
2916 | int memtarget=0,c=0; | |
2917 | int offset_reg = -1; | |
2918 | int fastio_reg_override = -1; | |
2919 | u_int reglist=get_host_reglist(i_regs->regmap); | |
2920 | tl=get_reg(i_regs->regmap,dops[i].rt1); | |
2921 | s=get_reg(i_regs->regmap,dops[i].rs1); | |
2922 | temp=get_reg(i_regs->regmap,-1); | |
2923 | temp2=get_reg(i_regs->regmap,FTEMP); | |
2924 | addr=get_reg(i_regs->regmap,AGEN1+(i&1)); | |
2925 | assert(addr<0); | |
2926 | offset=imm[i]; | |
2927 | reglist|=1<<temp; | |
2928 | if(offset||s<0||c) addr=temp2; | |
2929 | else addr=s; | |
2930 | if(s>=0) { | |
2931 | c=(i_regs->wasconst>>s)&1; | |
2932 | if(c) { | |
2933 | memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE; | |
535d208a | 2934 | } |
630b122b | 2935 | } |
2936 | if(!c) { | |
2937 | emit_shlimm(addr,3,temp); | |
2938 | if (dops[i].opcode==0x22||dops[i].opcode==0x26) { | |
2939 | emit_andimm(addr,0xFFFFFFFC,temp2); // LWL/LWR | |
2940 | }else{ | |
2941 | emit_andimm(addr,0xFFFFFFF8,temp2); // LDL/LDR | |
2942 | } | |
2943 | jaddr = emit_fastpath_cmp_jump(i, i_regs, temp2, | |
2944 | &offset_reg, &fastio_reg_override); | |
2945 | } | |
2946 | else { | |
2947 | if (ram_offset && memtarget) { | |
2948 | offset_reg = get_ro_reg(i_regs, 0); | |
2949 | } | |
2950 | if (dops[i].opcode==0x22||dops[i].opcode==0x26) { | |
2951 | emit_movimm(((constmap[i][s]+offset)<<3)&24,temp); // LWL/LWR | |
2952 | }else{ | |
2953 | emit_movimm(((constmap[i][s]+offset)<<3)&56,temp); // LDL/LDR | |
57871462 | 2954 | } |
535d208a | 2955 | } |
630b122b | 2956 | if (dops[i].opcode==0x22||dops[i].opcode==0x26) { // LWL/LWR |
535d208a | 2957 | if(!c||memtarget) { |
630b122b | 2958 | int a = temp2; |
2959 | if (fastio_reg_override >= 0) | |
2960 | a = fastio_reg_override; | |
2961 | do_load_word(a, temp2, offset_reg); | |
2962 | if (fastio_reg_override == HOST_TEMPREG || offset_reg == HOST_TEMPREG) | |
2963 | host_tempreg_release(); | |
2964 | if(jaddr) add_stub_r(LOADW_STUB,jaddr,out,i,temp2,i_regs,ccadj_,reglist); | |
57871462 | 2965 | } |
535d208a | 2966 | else |
630b122b | 2967 | inline_readstub(LOADW_STUB,i,(constmap[i][s]+offset)&0xFFFFFFFC,i_regs->regmap,FTEMP,ccadj_,reglist); |
2968 | if(dops[i].rt1) { | |
2969 | assert(tl>=0); | |
2970 | emit_andimm(temp,24,temp); | |
2971 | if (dops[i].opcode==0x22) // LWL | |
2972 | emit_xorimm(temp,24,temp); | |
2973 | host_tempreg_acquire(); | |
2974 | emit_movimm(-1,HOST_TEMPREG); | |
2975 | if (dops[i].opcode==0x26) { | |
2976 | emit_shr(temp2,temp,temp2); | |
2977 | emit_bic_lsr(tl,HOST_TEMPREG,temp,tl); | |
2978 | }else{ | |
2979 | emit_shl(temp2,temp,temp2); | |
2980 | emit_bic_lsl(tl,HOST_TEMPREG,temp,tl); | |
2981 | } | |
2982 | host_tempreg_release(); | |
2983 | emit_or(temp2,tl,tl); | |
2984 | } | |
2985 | //emit_storereg(dops[i].rt1,tl); // DEBUG | |
2986 | } | |
2987 | if (dops[i].opcode==0x1A||dops[i].opcode==0x1B) { // LDL/LDR | |
2988 | assert(0); | |
57871462 | 2989 | } |
57871462 | 2990 | } |
2991 | #endif | |
2992 | ||
630b122b | 2993 | static void store_assemble(int i, const struct regstat *i_regs, int ccadj_) |
57871462 | 2994 | { |
630b122b | 2995 | int s,tl; |
57871462 | 2996 | int addr,temp; |
2997 | int offset; | |
630b122b | 2998 | void *jaddr=0; |
2999 | enum stub_type type=0; | |
666a299d | 3000 | int memtarget=0,c=0; |
57871462 | 3001 | int agr=AGEN1+(i&1); |
630b122b | 3002 | int offset_reg = -1; |
3003 | int fastio_reg_override = -1; | |
3004 | u_int reglist=get_host_reglist(i_regs->regmap); | |
3005 | tl=get_reg(i_regs->regmap,dops[i].rs2); | |
3006 | s=get_reg(i_regs->regmap,dops[i].rs1); | |
57871462 | 3007 | temp=get_reg(i_regs->regmap,agr); |
3008 | if(temp<0) temp=get_reg(i_regs->regmap,-1); | |
3009 | offset=imm[i]; | |
3010 | if(s>=0) { | |
3011 | c=(i_regs->wasconst>>s)&1; | |
af4ee1fe | 3012 | if(c) { |
3013 | memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE; | |
af4ee1fe | 3014 | } |
57871462 | 3015 | } |
3016 | assert(tl>=0); | |
3017 | assert(temp>=0); | |
57871462 | 3018 | if(i_regs->regmap[HOST_CCREG]==CCREG) reglist&=~(1<<HOST_CCREG); |
3019 | if(offset||s<0||c) addr=temp; | |
3020 | else addr=s; | |
630b122b | 3021 | if (!c) { |
3022 | jaddr = emit_fastpath_cmp_jump(i, i_regs, addr, | |
3023 | &offset_reg, &fastio_reg_override); | |
1edfcc68 | 3024 | } |
630b122b | 3025 | else if (ram_offset && memtarget) { |
3026 | offset_reg = get_ro_reg(i_regs, 0); | |
57871462 | 3027 | } |
3028 | ||
630b122b | 3029 | switch (dops[i].opcode) { |
3030 | case 0x28: // SB | |
57871462 | 3031 | if(!c||memtarget) { |
630b122b | 3032 | int a = temp; |
3033 | if (!c) a = addr; | |
3034 | if (fastio_reg_override >= 0) | |
3035 | a = fastio_reg_override; | |
3036 | do_store_byte(a, tl, offset_reg); | |
3037 | } | |
3038 | type = STOREB_STUB; | |
3039 | break; | |
3040 | case 0x29: // SH | |
dadf55f2 | 3041 | if(!c||memtarget) { |
630b122b | 3042 | int a = temp; |
3043 | if (!c) a = addr; | |
3044 | if (fastio_reg_override >= 0) | |
3045 | a = fastio_reg_override; | |
3046 | do_store_hword(a, 0, tl, offset_reg, 1); | |
3047 | } | |
3048 | type = STOREH_STUB; | |
3049 | break; | |
3050 | case 0x2B: // SW | |
57871462 | 3051 | if(!c||memtarget) { |
630b122b | 3052 | int a = addr; |
3053 | if (fastio_reg_override >= 0) | |
3054 | a = fastio_reg_override; | |
3055 | do_store_word(a, 0, tl, offset_reg, 1); | |
3056 | } | |
3057 | type = STOREW_STUB; | |
3058 | break; | |
3059 | case 0x3F: // SD | |
3060 | default: | |
3061 | assert(0); | |
3062 | } | |
3063 | if (fastio_reg_override == HOST_TEMPREG || offset_reg == HOST_TEMPREG) | |
3064 | host_tempreg_release(); | |
b96d3df7 | 3065 | if(jaddr) { |
3066 | // PCSX store handlers don't check invcode again | |
3067 | reglist|=1<<addr; | |
630b122b | 3068 | add_stub_r(type,jaddr,out,i,addr,i_regs,ccadj_,reglist); |
b96d3df7 | 3069 | jaddr=0; |
3070 | } | |
630b122b | 3071 | if(!(i_regs->waswritten&(1<<dops[i].rs1)) && !HACK_ENABLED(NDHACK_NO_SMC_CHECK)) { |
57871462 | 3072 | if(!c||memtarget) { |
3073 | #ifdef DESTRUCTIVE_SHIFT | |
3074 | // The x86 shift operation is 'destructive'; it overwrites the | |
3075 | // source register, so we need to make a copy first and use that. | |
3076 | addr=temp; | |
3077 | #endif | |
3078 | #if defined(HOST_IMM8) | |
3079 | int ir=get_reg(i_regs->regmap,INVCP); | |
3080 | assert(ir>=0); | |
3081 | emit_cmpmem_indexedsr12_reg(ir,addr,1); | |
3082 | #else | |
630b122b | 3083 | emit_cmpmem_indexedsr12_imm(invalid_code,addr,1); |
57871462 | 3084 | #endif |
0bbd1454 | 3085 | #if defined(HAVE_CONDITIONAL_CALL) && !defined(DESTRUCTIVE_SHIFT) |
3086 | emit_callne(invalidate_addr_reg[addr]); | |
3087 | #else | |
630b122b | 3088 | void *jaddr2 = out; |
57871462 | 3089 | emit_jne(0); |
630b122b | 3090 | add_stub(INVCODE_STUB,jaddr2,out,reglist|(1<<HOST_CCREG),addr,0,0,0); |
0bbd1454 | 3091 | #endif |
57871462 | 3092 | } |
3093 | } | |
7a518516 | 3094 | u_int addr_val=constmap[i][s]+offset; |
3eaa7048 | 3095 | if(jaddr) { |
630b122b | 3096 | add_stub_r(type,jaddr,out,i,addr,i_regs,ccadj_,reglist); |
3eaa7048 | 3097 | } else if(c&&!memtarget) { |
630b122b | 3098 | inline_writestub(type,i,addr_val,i_regs->regmap,dops[i].rs2,ccadj_,reglist); |
7a518516 | 3099 | } |
3100 | // basic current block modification detection.. | |
3101 | // not looking back as that should be in mips cache already | |
630b122b | 3102 | // (see Spyro2 title->attract mode) |
7a518516 | 3103 | if(c&&start+i*4<addr_val&&addr_val<start+slen*4) { |
c43b5311 | 3104 | SysPrintf("write to %08x hits block %08x, pc=%08x\n",addr_val,start,start+i*4); |
7a518516 | 3105 | assert(i_regs->regmap==regs[i].regmap); // not delay slot |
3106 | if(i_regs->regmap==regs[i].regmap) { | |
630b122b | 3107 | load_all_consts(regs[i].regmap_entry,regs[i].wasdirty,i); |
3108 | wb_dirtys(regs[i].regmap_entry,regs[i].wasdirty); | |
7a518516 | 3109 | emit_movimm(start+i*4+4,0); |
630b122b | 3110 | emit_writeword(0,&pcaddr); |
3111 | emit_addimm(HOST_CCREG,2,HOST_CCREG); | |
3112 | emit_far_call(get_addr_ht); | |
3113 | emit_jmpreg(0); | |
7a518516 | 3114 | } |
3eaa7048 | 3115 | } |
57871462 | 3116 | } |
3117 | ||
630b122b | 3118 | static void storelr_assemble(int i, const struct regstat *i_regs, int ccadj_) |
57871462 | 3119 | { |
630b122b | 3120 | int s,tl; |
57871462 | 3121 | int temp; |
57871462 | 3122 | int offset; |
630b122b | 3123 | void *jaddr=0; |
3124 | void *case1, *case23, *case3; | |
3125 | void *done0, *done1, *done2; | |
af4ee1fe | 3126 | int memtarget=0,c=0; |
fab5d06d | 3127 | int agr=AGEN1+(i&1); |
630b122b | 3128 | int offset_reg = -1; |
3129 | u_int reglist=get_host_reglist(i_regs->regmap); | |
3130 | tl=get_reg(i_regs->regmap,dops[i].rs2); | |
3131 | s=get_reg(i_regs->regmap,dops[i].rs1); | |
fab5d06d | 3132 | temp=get_reg(i_regs->regmap,agr); |
3133 | if(temp<0) temp=get_reg(i_regs->regmap,-1); | |
57871462 | 3134 | offset=imm[i]; |
3135 | if(s>=0) { | |
3136 | c=(i_regs->isconst>>s)&1; | |
af4ee1fe | 3137 | if(c) { |
3138 | memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE; | |
af4ee1fe | 3139 | } |
57871462 | 3140 | } |
3141 | assert(tl>=0); | |
535d208a | 3142 | assert(temp>=0); |
1edfcc68 | 3143 | if(!c) { |
3144 | emit_cmpimm(s<0||offset?temp:s,RAM_SIZE); | |
3145 | if(!offset&&s!=temp) emit_mov(s,temp); | |
630b122b | 3146 | jaddr=out; |
1edfcc68 | 3147 | emit_jno(0); |
3148 | } | |
3149 | else | |
3150 | { | |
630b122b | 3151 | if(!memtarget||!dops[i].rs1) { |
3152 | jaddr=out; | |
535d208a | 3153 | emit_jmp(0); |
57871462 | 3154 | } |
535d208a | 3155 | } |
630b122b | 3156 | if (ram_offset) |
3157 | offset_reg = get_ro_reg(i_regs, 0); | |
535d208a | 3158 | |
630b122b | 3159 | if (dops[i].opcode==0x2C||dops[i].opcode==0x2D) { // SDL/SDR |
3160 | assert(0); | |
535d208a | 3161 | } |
57871462 | 3162 | |
535d208a | 3163 | emit_testimm(temp,2); |
630b122b | 3164 | case23=out; |
535d208a | 3165 | emit_jne(0); |
3166 | emit_testimm(temp,1); | |
630b122b | 3167 | case1=out; |
535d208a | 3168 | emit_jne(0); |
3169 | // 0 | |
630b122b | 3170 | if (dops[i].opcode == 0x2A) { // SWL |
3171 | // Write msb into least significant byte | |
3172 | if (dops[i].rs2) emit_rorimm(tl, 24, tl); | |
3173 | do_store_byte(temp, tl, offset_reg); | |
3174 | if (dops[i].rs2) emit_rorimm(tl, 8, tl); | |
535d208a | 3175 | } |
630b122b | 3176 | else if (dops[i].opcode == 0x2E) { // SWR |
3177 | // Write entire word | |
3178 | do_store_word(temp, 0, tl, offset_reg, 1); | |
535d208a | 3179 | } |
630b122b | 3180 | done0 = out; |
535d208a | 3181 | emit_jmp(0); |
3182 | // 1 | |
630b122b | 3183 | set_jump_target(case1, out); |
3184 | if (dops[i].opcode == 0x2A) { // SWL | |
3185 | // Write two msb into two least significant bytes | |
3186 | if (dops[i].rs2) emit_rorimm(tl, 16, tl); | |
3187 | do_store_hword(temp, -1, tl, offset_reg, 0); | |
3188 | if (dops[i].rs2) emit_rorimm(tl, 16, tl); | |
535d208a | 3189 | } |
630b122b | 3190 | else if (dops[i].opcode == 0x2E) { // SWR |
3191 | // Write 3 lsb into three most significant bytes | |
3192 | do_store_byte(temp, tl, offset_reg); | |
3193 | if (dops[i].rs2) emit_rorimm(tl, 8, tl); | |
3194 | do_store_hword(temp, 1, tl, offset_reg, 0); | |
3195 | if (dops[i].rs2) emit_rorimm(tl, 24, tl); | |
535d208a | 3196 | } |
630b122b | 3197 | done1=out; |
535d208a | 3198 | emit_jmp(0); |
630b122b | 3199 | // 2,3 |
3200 | set_jump_target(case23, out); | |
535d208a | 3201 | emit_testimm(temp,1); |
630b122b | 3202 | case3 = out; |
535d208a | 3203 | emit_jne(0); |
630b122b | 3204 | // 2 |
3205 | if (dops[i].opcode==0x2A) { // SWL | |
3206 | // Write 3 msb into three least significant bytes | |
3207 | if (dops[i].rs2) emit_rorimm(tl, 8, tl); | |
3208 | do_store_hword(temp, -2, tl, offset_reg, 1); | |
3209 | if (dops[i].rs2) emit_rorimm(tl, 16, tl); | |
3210 | do_store_byte(temp, tl, offset_reg); | |
3211 | if (dops[i].rs2) emit_rorimm(tl, 8, tl); | |
535d208a | 3212 | } |
630b122b | 3213 | else if (dops[i].opcode == 0x2E) { // SWR |
3214 | // Write two lsb into two most significant bytes | |
3215 | do_store_hword(temp, 0, tl, offset_reg, 1); | |
535d208a | 3216 | } |
630b122b | 3217 | done2 = out; |
535d208a | 3218 | emit_jmp(0); |
3219 | // 3 | |
630b122b | 3220 | set_jump_target(case3, out); |
3221 | if (dops[i].opcode == 0x2A) { // SWL | |
3222 | do_store_word(temp, -3, tl, offset_reg, 0); | |
3223 | } | |
3224 | else if (dops[i].opcode == 0x2E) { // SWR | |
3225 | do_store_byte(temp, tl, offset_reg); | |
3226 | } | |
3227 | set_jump_target(done0, out); | |
3228 | set_jump_target(done1, out); | |
3229 | set_jump_target(done2, out); | |
3230 | if (offset_reg == HOST_TEMPREG) | |
3231 | host_tempreg_release(); | |
535d208a | 3232 | if(!c||!memtarget) |
630b122b | 3233 | add_stub_r(STORELR_STUB,jaddr,out,i,temp,i_regs,ccadj_,reglist); |
3234 | if(!(i_regs->waswritten&(1<<dops[i].rs1)) && !HACK_ENABLED(NDHACK_NO_SMC_CHECK)) { | |
57871462 | 3235 | #if defined(HOST_IMM8) |
3236 | int ir=get_reg(i_regs->regmap,INVCP); | |
3237 | assert(ir>=0); | |
3238 | emit_cmpmem_indexedsr12_reg(ir,temp,1); | |
3239 | #else | |
630b122b | 3240 | emit_cmpmem_indexedsr12_imm(invalid_code,temp,1); |
57871462 | 3241 | #endif |
535d208a | 3242 | #if defined(HAVE_CONDITIONAL_CALL) && !defined(DESTRUCTIVE_SHIFT) |
3243 | emit_callne(invalidate_addr_reg[temp]); | |
3244 | #else | |
630b122b | 3245 | void *jaddr2 = out; |
57871462 | 3246 | emit_jne(0); |
630b122b | 3247 | add_stub(INVCODE_STUB,jaddr2,out,reglist|(1<<HOST_CCREG),temp,0,0,0); |
535d208a | 3248 | #endif |
57871462 | 3249 | } |
57871462 | 3250 | } |
3251 | ||
630b122b | 3252 | static void cop0_assemble(int i, const struct regstat *i_regs, int ccadj_) |
3253 | { | |
3254 | if(dops[i].opcode2==0) // MFC0 | |
3255 | { | |
3256 | signed char t=get_reg(i_regs->regmap,dops[i].rt1); | |
3257 | u_int copr=(source[i]>>11)&0x1f; | |
3258 | //assert(t>=0); // Why does this happen? OOT is weird | |
3259 | if(t>=0&&dops[i].rt1!=0) { | |
3260 | emit_readword(®_cop0[copr],t); | |
3261 | } | |
3262 | } | |
3263 | else if(dops[i].opcode2==4) // MTC0 | |
3264 | { | |
3265 | signed char s=get_reg(i_regs->regmap,dops[i].rs1); | |
3266 | char copr=(source[i]>>11)&0x1f; | |
3267 | assert(s>=0); | |
3268 | wb_register(dops[i].rs1,i_regs->regmap,i_regs->dirty); | |
3269 | if(copr==9||copr==11||copr==12||copr==13) { | |
3270 | emit_readword(&last_count,HOST_TEMPREG); | |
3271 | emit_loadreg(CCREG,HOST_CCREG); // TODO: do proper reg alloc | |
3272 | emit_add(HOST_CCREG,HOST_TEMPREG,HOST_CCREG); | |
3273 | emit_addimm(HOST_CCREG,ccadj_,HOST_CCREG); | |
3274 | emit_writeword(HOST_CCREG,&Count); | |
3275 | } | |
3276 | // What a mess. The status register (12) can enable interrupts, | |
3277 | // so needs a special case to handle a pending interrupt. | |
3278 | // The interrupt must be taken immediately, because a subsequent | |
3279 | // instruction might disable interrupts again. | |
3280 | if(copr==12||copr==13) { | |
3281 | if (is_delayslot) { | |
3282 | // burn cycles to cause cc_interrupt, which will | |
3283 | // reschedule next_interupt. Relies on CCREG from above. | |
3284 | assem_debug("MTC0 DS %d\n", copr); | |
3285 | emit_writeword(HOST_CCREG,&last_count); | |
3286 | emit_movimm(0,HOST_CCREG); | |
3287 | emit_storereg(CCREG,HOST_CCREG); | |
3288 | emit_loadreg(dops[i].rs1,1); | |
3289 | emit_movimm(copr,0); | |
3290 | emit_far_call(pcsx_mtc0_ds); | |
3291 | emit_loadreg(dops[i].rs1,s); | |
3292 | return; | |
3293 | } | |
3294 | emit_movimm(start+i*4+4,HOST_TEMPREG); | |
3295 | emit_writeword(HOST_TEMPREG,&pcaddr); | |
3296 | emit_movimm(0,HOST_TEMPREG); | |
3297 | emit_writeword(HOST_TEMPREG,&pending_exception); | |
3298 | } | |
3299 | if(s==HOST_CCREG) | |
3300 | emit_loadreg(dops[i].rs1,1); | |
3301 | else if(s!=1) | |
3302 | emit_mov(s,1); | |
3303 | emit_movimm(copr,0); | |
3304 | emit_far_call(pcsx_mtc0); | |
3305 | if(copr==9||copr==11||copr==12||copr==13) { | |
3306 | emit_readword(&Count,HOST_CCREG); | |
3307 | emit_readword(&next_interupt,HOST_TEMPREG); | |
3308 | emit_addimm(HOST_CCREG,-ccadj_,HOST_CCREG); | |
3309 | emit_sub(HOST_CCREG,HOST_TEMPREG,HOST_CCREG); | |
3310 | emit_writeword(HOST_TEMPREG,&last_count); | |
3311 | emit_storereg(CCREG,HOST_CCREG); | |
3312 | } | |
3313 | if(copr==12||copr==13) { | |
3314 | assert(!is_delayslot); | |
3315 | emit_readword(&pending_exception,14); | |
3316 | emit_test(14,14); | |
3317 | void *jaddr = out; | |
3318 | emit_jeq(0); | |
3319 | emit_readword(&pcaddr, 0); | |
3320 | emit_addimm(HOST_CCREG,2,HOST_CCREG); | |
3321 | emit_far_call(get_addr_ht); | |
3322 | emit_jmpreg(0); | |
3323 | set_jump_target(jaddr, out); | |
3324 | } | |
3325 | emit_loadreg(dops[i].rs1,s); | |
3326 | } | |
3327 | else | |
3328 | { | |
3329 | assert(dops[i].opcode2==0x10); | |
3330 | //if((source[i]&0x3f)==0x10) // RFE | |
3331 | { | |
3332 | emit_readword(&Status,0); | |
3333 | emit_andimm(0,0x3c,1); | |
3334 | emit_andimm(0,~0xf,0); | |
3335 | emit_orrshr_imm(1,2,0); | |
3336 | emit_writeword(0,&Status); | |
3337 | } | |
3338 | } | |
3339 | } | |
3340 | ||
3341 | static void cop1_unusable(int i, const struct regstat *i_regs) | |
3342 | { | |
3343 | // XXX: should just just do the exception instead | |
3344 | //if(!cop1_usable) | |
3345 | { | |
3346 | void *jaddr=out; | |
3347 | emit_jmp(0); | |
3348 | add_stub_r(FP_STUB,jaddr,out,i,0,i_regs,is_delayslot,0); | |
3349 | } | |
3350 | } | |
3351 | ||
3352 | static void cop1_assemble(int i, const struct regstat *i_regs) | |
57871462 | 3353 | { |
3d624f89 | 3354 | cop1_unusable(i, i_regs); |
57871462 | 3355 | } |
3356 | ||
630b122b | 3357 | static void c1ls_assemble(int i, const struct regstat *i_regs) |
3358 | { | |
3359 | cop1_unusable(i, i_regs); | |
3360 | } | |
3361 | ||
3362 | // FP_STUB | |
3363 | static void do_cop1stub(int n) | |
3364 | { | |
3365 | literal_pool(256); | |
3366 | assem_debug("do_cop1stub %x\n",start+stubs[n].a*4); | |
3367 | set_jump_target(stubs[n].addr, out); | |
3368 | int i=stubs[n].a; | |
3369 | // int rs=stubs[n].b; | |
3370 | struct regstat *i_regs=(struct regstat *)stubs[n].c; | |
3371 | int ds=stubs[n].d; | |
3372 | if(!ds) { | |
3373 | load_all_consts(regs[i].regmap_entry,regs[i].wasdirty,i); | |
3374 | //if(i_regs!=®s[i]) printf("oops: regs[i]=%x i_regs=%x",(int)®s[i],(int)i_regs); | |
3375 | } | |
3376 | //else {printf("fp exception in delay slot\n");} | |
3377 | wb_dirtys(i_regs->regmap_entry,i_regs->wasdirty); | |
3378 | if(regs[i].regmap_entry[HOST_CCREG]!=CCREG) emit_loadreg(CCREG,HOST_CCREG); | |
3379 | emit_movimm(start+(i-ds)*4,EAX); // Get PC | |
3380 | emit_addimm(HOST_CCREG,ccadj[i],HOST_CCREG); // CHECK: is this right? There should probably be an extra cycle... | |
3381 | emit_far_jump(ds?fp_exception_ds:fp_exception); | |
3382 | } | |
3383 | ||
3384 | static int cop2_is_stalling_op(int i, int *cycles) | |
3385 | { | |
3386 | if (dops[i].opcode == 0x3a) { // SWC2 | |
3387 | *cycles = 0; | |
3388 | return 1; | |
3389 | } | |
3390 | if (dops[i].itype == COP2 && (dops[i].opcode2 == 0 || dops[i].opcode2 == 2)) { // MFC2/CFC2 | |
3391 | *cycles = 0; | |
3392 | return 1; | |
3393 | } | |
3394 | if (dops[i].itype == C2OP) { | |
3395 | *cycles = gte_cycletab[source[i] & 0x3f]; | |
3396 | return 1; | |
3397 | } | |
3398 | // ... what about MTC2/CTC2/LWC2? | |
3399 | return 0; | |
3400 | } | |
3401 | ||
3402 | #if 0 | |
3403 | static void log_gte_stall(int stall, u_int cycle) | |
3404 | { | |
3405 | if ((u_int)stall <= 44) | |
3406 | printf("x stall %2d %u\n", stall, cycle + last_count); | |
3407 | } | |
3408 | ||
3409 | static void emit_log_gte_stall(int i, int stall, u_int reglist) | |
3410 | { | |
3411 | save_regs(reglist); | |
3412 | if (stall > 0) | |
3413 | emit_movimm(stall, 0); | |
3414 | else | |
3415 | emit_mov(HOST_TEMPREG, 0); | |
3416 | emit_addimm(HOST_CCREG, ccadj[i], 1); | |
3417 | emit_far_call(log_gte_stall); | |
3418 | restore_regs(reglist); | |
3419 | } | |
3420 | #endif | |
3421 | ||
3422 | static void cop2_do_stall_check(u_int op, int i, const struct regstat *i_regs, u_int reglist) | |
3423 | { | |
3424 | int j = i, other_gte_op_cycles = -1, stall = -MAXBLOCK, cycles_passed; | |
3425 | int rtmp = reglist_find_free(reglist); | |
3426 | ||
3427 | if (HACK_ENABLED(NDHACK_NO_STALLS)) | |
3428 | return; | |
3429 | if (get_reg(i_regs->regmap, CCREG) != HOST_CCREG) { | |
3430 | // happens occasionally... cc evicted? Don't bother then | |
3431 | //printf("no cc %08x\n", start + i*4); | |
3432 | return; | |
3433 | } | |
3434 | if (!dops[i].bt) { | |
3435 | for (j = i - 1; j >= 0; j--) { | |
3436 | //if (dops[j].is_ds) break; | |
3437 | if (cop2_is_stalling_op(j, &other_gte_op_cycles) || dops[j].bt) | |
3438 | break; | |
3439 | if (j > 0 && ccadj[j - 1] > ccadj[j]) | |
3440 | break; | |
3441 | } | |
3442 | j = max(j, 0); | |
3443 | } | |
3444 | cycles_passed = ccadj[i] - ccadj[j]; | |
3445 | if (other_gte_op_cycles >= 0) | |
3446 | stall = other_gte_op_cycles - cycles_passed; | |
3447 | else if (cycles_passed >= 44) | |
3448 | stall = 0; // can't stall | |
3449 | if (stall == -MAXBLOCK && rtmp >= 0) { | |
3450 | // unknown stall, do the expensive runtime check | |
3451 | assem_debug("; cop2_do_stall_check\n"); | |
3452 | #if 0 // too slow | |
3453 | save_regs(reglist); | |
3454 | emit_movimm(gte_cycletab[op], 0); | |
3455 | emit_addimm(HOST_CCREG, ccadj[i], 1); | |
3456 | emit_far_call(call_gteStall); | |
3457 | restore_regs(reglist); | |
3458 | #else | |
3459 | host_tempreg_acquire(); | |
3460 | emit_readword(&psxRegs.gteBusyCycle, rtmp); | |
3461 | emit_addimm(rtmp, -ccadj[i], rtmp); | |
3462 | emit_sub(rtmp, HOST_CCREG, HOST_TEMPREG); | |
3463 | emit_cmpimm(HOST_TEMPREG, 44); | |
3464 | emit_cmovb_reg(rtmp, HOST_CCREG); | |
3465 | //emit_log_gte_stall(i, 0, reglist); | |
3466 | host_tempreg_release(); | |
3467 | #endif | |
3468 | } | |
3469 | else if (stall > 0) { | |
3470 | //emit_log_gte_stall(i, stall, reglist); | |
3471 | emit_addimm(HOST_CCREG, stall, HOST_CCREG); | |
3472 | } | |
3473 | ||
3474 | // save gteBusyCycle, if needed | |
3475 | if (gte_cycletab[op] == 0) | |
3476 | return; | |
3477 | other_gte_op_cycles = -1; | |
3478 | for (j = i + 1; j < slen; j++) { | |
3479 | if (cop2_is_stalling_op(j, &other_gte_op_cycles)) | |
3480 | break; | |
3481 | if (dops[j].is_jump) { | |
3482 | // check ds | |
3483 | if (j + 1 < slen && cop2_is_stalling_op(j + 1, &other_gte_op_cycles)) | |
3484 | j++; | |
3485 | break; | |
3486 | } | |
3487 | } | |
3488 | if (other_gte_op_cycles >= 0) | |
3489 | // will handle stall when assembling that op | |
3490 | return; | |
3491 | cycles_passed = ccadj[min(j, slen -1)] - ccadj[i]; | |
3492 | if (cycles_passed >= 44) | |
3493 | return; | |
3494 | assem_debug("; save gteBusyCycle\n"); | |
3495 | host_tempreg_acquire(); | |
3496 | #if 0 | |
3497 | emit_readword(&last_count, HOST_TEMPREG); | |
3498 | emit_add(HOST_TEMPREG, HOST_CCREG, HOST_TEMPREG); | |
3499 | emit_addimm(HOST_TEMPREG, ccadj[i], HOST_TEMPREG); | |
3500 | emit_addimm(HOST_TEMPREG, gte_cycletab[op]), HOST_TEMPREG); | |
3501 | emit_writeword(HOST_TEMPREG, &psxRegs.gteBusyCycle); | |
3502 | #else | |
3503 | emit_addimm(HOST_CCREG, ccadj[i] + gte_cycletab[op], HOST_TEMPREG); | |
3504 | emit_writeword(HOST_TEMPREG, &psxRegs.gteBusyCycle); | |
3505 | #endif | |
3506 | host_tempreg_release(); | |
3507 | } | |
3508 | ||
3509 | static int is_mflohi(int i) | |
3510 | { | |
3511 | return (dops[i].itype == MOV && (dops[i].rs1 == HIREG || dops[i].rs1 == LOREG)); | |
3512 | } | |
3513 | ||
3514 | static int check_multdiv(int i, int *cycles) | |
3515 | { | |
3516 | if (dops[i].itype != MULTDIV) | |
3517 | return 0; | |
3518 | if (dops[i].opcode2 == 0x18 || dops[i].opcode2 == 0x19) // MULT(U) | |
3519 | *cycles = 11; // approx from 7 11 14 | |
3520 | else | |
3521 | *cycles = 37; | |
3522 | return 1; | |
3523 | } | |
3524 | ||
3525 | static void multdiv_prepare_stall(int i, const struct regstat *i_regs, int ccadj_) | |
3526 | { | |
3527 | int j, found = 0, c = 0; | |
3528 | if (HACK_ENABLED(NDHACK_NO_STALLS)) | |
3529 | return; | |
3530 | if (get_reg(i_regs->regmap, CCREG) != HOST_CCREG) { | |
3531 | // happens occasionally... cc evicted? Don't bother then | |
3532 | return; | |
3533 | } | |
3534 | for (j = i + 1; j < slen; j++) { | |
3535 | if (dops[j].bt) | |
3536 | break; | |
3537 | if ((found = is_mflohi(j))) | |
3538 | break; | |
3539 | if (dops[j].is_jump) { | |
3540 | // check ds | |
3541 | if (j + 1 < slen && (found = is_mflohi(j + 1))) | |
3542 | j++; | |
3543 | break; | |
3544 | } | |
3545 | } | |
3546 | if (found) | |
3547 | // handle all in multdiv_do_stall() | |
3548 | return; | |
3549 | check_multdiv(i, &c); | |
3550 | assert(c > 0); | |
3551 | assem_debug("; muldiv prepare stall %d\n", c); | |
3552 | host_tempreg_acquire(); | |
3553 | emit_addimm(HOST_CCREG, ccadj_ + c, HOST_TEMPREG); | |
3554 | emit_writeword(HOST_TEMPREG, &psxRegs.muldivBusyCycle); | |
3555 | host_tempreg_release(); | |
3556 | } | |
3557 | ||
3558 | static void multdiv_do_stall(int i, const struct regstat *i_regs) | |
3559 | { | |
3560 | int j, known_cycles = 0; | |
3561 | u_int reglist = get_host_reglist(i_regs->regmap); | |
3562 | int rtmp = get_reg(i_regs->regmap, -1); | |
3563 | if (rtmp < 0) | |
3564 | rtmp = reglist_find_free(reglist); | |
3565 | if (HACK_ENABLED(NDHACK_NO_STALLS)) | |
3566 | return; | |
3567 | if (get_reg(i_regs->regmap, CCREG) != HOST_CCREG || rtmp < 0) { | |
3568 | // happens occasionally... cc evicted? Don't bother then | |
3569 | //printf("no cc/rtmp %08x\n", start + i*4); | |
3570 | return; | |
3571 | } | |
3572 | if (!dops[i].bt) { | |
3573 | for (j = i - 1; j >= 0; j--) { | |
3574 | if (dops[j].is_ds) break; | |
3575 | if (check_multdiv(j, &known_cycles)) | |
3576 | break; | |
3577 | if (is_mflohi(j)) | |
3578 | // already handled by this op | |
3579 | return; | |
3580 | if (dops[j].bt || (j > 0 && ccadj[j - 1] > ccadj[j])) | |
3581 | break; | |
3582 | } | |
3583 | j = max(j, 0); | |
3584 | } | |
3585 | if (known_cycles > 0) { | |
3586 | known_cycles -= ccadj[i] - ccadj[j]; | |
3587 | assem_debug("; muldiv stall resolved %d\n", known_cycles); | |
3588 | if (known_cycles > 0) | |
3589 | emit_addimm(HOST_CCREG, known_cycles, HOST_CCREG); | |
3590 | return; | |
3591 | } | |
3592 | assem_debug("; muldiv stall unresolved\n"); | |
3593 | host_tempreg_acquire(); | |
3594 | emit_readword(&psxRegs.muldivBusyCycle, rtmp); | |
3595 | emit_addimm(rtmp, -ccadj[i], rtmp); | |
3596 | emit_sub(rtmp, HOST_CCREG, HOST_TEMPREG); | |
3597 | emit_cmpimm(HOST_TEMPREG, 37); | |
3598 | emit_cmovb_reg(rtmp, HOST_CCREG); | |
3599 | //emit_log_gte_stall(i, 0, reglist); | |
3600 | host_tempreg_release(); | |
3601 | } | |
3602 | ||
3603 | static void cop2_get_dreg(u_int copr,signed char tl,signed char temp) | |
3604 | { | |
3605 | switch (copr) { | |
3606 | case 1: | |
3607 | case 3: | |
3608 | case 5: | |
3609 | case 8: | |
3610 | case 9: | |
3611 | case 10: | |
3612 | case 11: | |
3613 | emit_readword(®_cop2d[copr],tl); | |
3614 | emit_signextend16(tl,tl); | |
3615 | emit_writeword(tl,®_cop2d[copr]); // hmh | |
3616 | break; | |
3617 | case 7: | |
3618 | case 16: | |
3619 | case 17: | |
3620 | case 18: | |
3621 | case 19: | |
3622 | emit_readword(®_cop2d[copr],tl); | |
3623 | emit_andimm(tl,0xffff,tl); | |
3624 | emit_writeword(tl,®_cop2d[copr]); | |
3625 | break; | |
3626 | case 15: | |
3627 | emit_readword(®_cop2d[14],tl); // SXY2 | |
3628 | emit_writeword(tl,®_cop2d[copr]); | |
3629 | break; | |
3630 | case 28: | |
3631 | case 29: | |
3632 | c2op_mfc2_29_assemble(tl,temp); | |
3633 | break; | |
3634 | default: | |
3635 | emit_readword(®_cop2d[copr],tl); | |
3636 | break; | |
3637 | } | |
3638 | } | |
3639 | ||
3640 | static void cop2_put_dreg(u_int copr,signed char sl,signed char temp) | |
3641 | { | |
3642 | switch (copr) { | |
3643 | case 15: | |
3644 | emit_readword(®_cop2d[13],temp); // SXY1 | |
3645 | emit_writeword(sl,®_cop2d[copr]); | |
3646 | emit_writeword(temp,®_cop2d[12]); // SXY0 | |
3647 | emit_readword(®_cop2d[14],temp); // SXY2 | |
3648 | emit_writeword(sl,®_cop2d[14]); | |
3649 | emit_writeword(temp,®_cop2d[13]); // SXY1 | |
3650 | break; | |
3651 | case 28: | |
3652 | emit_andimm(sl,0x001f,temp); | |
3653 | emit_shlimm(temp,7,temp); | |
3654 | emit_writeword(temp,®_cop2d[9]); | |
3655 | emit_andimm(sl,0x03e0,temp); | |
3656 | emit_shlimm(temp,2,temp); | |
3657 | emit_writeword(temp,®_cop2d[10]); | |
3658 | emit_andimm(sl,0x7c00,temp); | |
3659 | emit_shrimm(temp,3,temp); | |
3660 | emit_writeword(temp,®_cop2d[11]); | |
3661 | emit_writeword(sl,®_cop2d[28]); | |
3662 | break; | |
3663 | case 30: | |
3664 | emit_xorsar_imm(sl,sl,31,temp); | |
3665 | #if defined(HAVE_ARMV5) || defined(__aarch64__) | |
3666 | emit_clz(temp,temp); | |
3667 | #else | |
3668 | emit_movs(temp,HOST_TEMPREG); | |
3669 | emit_movimm(0,temp); | |
3670 | emit_jeq((int)out+4*4); | |
3671 | emit_addpl_imm(temp,1,temp); | |
3672 | emit_lslpls_imm(HOST_TEMPREG,1,HOST_TEMPREG); | |
3673 | emit_jns((int)out-2*4); | |
3674 | #endif | |
3675 | emit_writeword(sl,®_cop2d[30]); | |
3676 | emit_writeword(temp,®_cop2d[31]); | |
3677 | break; | |
3678 | case 31: | |
3679 | break; | |
3680 | default: | |
3681 | emit_writeword(sl,®_cop2d[copr]); | |
3682 | break; | |
3683 | } | |
3684 | } | |
3685 | ||
3686 | static void c2ls_assemble(int i, const struct regstat *i_regs, int ccadj_) | |
b9b61529 | 3687 | { |
3688 | int s,tl; | |
3689 | int ar; | |
3690 | int offset; | |
1fd1aceb | 3691 | int memtarget=0,c=0; |
630b122b | 3692 | void *jaddr2=NULL; |
3693 | enum stub_type type; | |
b9b61529 | 3694 | int agr=AGEN1+(i&1); |
630b122b | 3695 | int offset_reg = -1; |
3696 | int fastio_reg_override = -1; | |
3697 | u_int reglist=get_host_reglist(i_regs->regmap); | |
b9b61529 | 3698 | u_int copr=(source[i]>>16)&0x1f; |
630b122b | 3699 | s=get_reg(i_regs->regmap,dops[i].rs1); |
b9b61529 | 3700 | tl=get_reg(i_regs->regmap,FTEMP); |
3701 | offset=imm[i]; | |
630b122b | 3702 | assert(dops[i].rs1>0); |
b9b61529 | 3703 | assert(tl>=0); |
b9b61529 | 3704 | |
b9b61529 | 3705 | if(i_regs->regmap[HOST_CCREG]==CCREG) |
3706 | reglist&=~(1<<HOST_CCREG); | |
3707 | ||
3708 | // get the address | |
630b122b | 3709 | if (dops[i].opcode==0x3a) { // SWC2 |
b9b61529 | 3710 | ar=get_reg(i_regs->regmap,agr); |
3711 | if(ar<0) ar=get_reg(i_regs->regmap,-1); | |
3712 | reglist|=1<<ar; | |
3713 | } else { // LWC2 | |
3714 | ar=tl; | |
3715 | } | |
1fd1aceb | 3716 | if(s>=0) c=(i_regs->wasconst>>s)&1; |
3717 | memtarget=c&&(((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE); | |
b9b61529 | 3718 | if (!offset&&!c&&s>=0) ar=s; |
3719 | assert(ar>=0); | |
3720 | ||
630b122b | 3721 | cop2_do_stall_check(0, i, i_regs, reglist); |
3722 | ||
3723 | if (dops[i].opcode==0x3a) { // SWC2 | |
3724 | cop2_get_dreg(copr,tl,-1); | |
1fd1aceb | 3725 | type=STOREW_STUB; |
b9b61529 | 3726 | } |
1fd1aceb | 3727 | else |
b9b61529 | 3728 | type=LOADW_STUB; |
1fd1aceb | 3729 | |
3730 | if(c&&!memtarget) { | |
630b122b | 3731 | jaddr2=out; |
1fd1aceb | 3732 | emit_jmp(0); // inline_readstub/inline_writestub? |
b9b61529 | 3733 | } |
1fd1aceb | 3734 | else { |
3735 | if(!c) { | |
630b122b | 3736 | jaddr2 = emit_fastpath_cmp_jump(i, i_regs, ar, |
3737 | &offset_reg, &fastio_reg_override); | |
3738 | } | |
3739 | else if (ram_offset && memtarget) { | |
3740 | offset_reg = get_ro_reg(i_regs, 0); | |
3741 | } | |
3742 | switch (dops[i].opcode) { | |
3743 | case 0x32: { // LWC2 | |
3744 | int a = ar; | |
3745 | if (fastio_reg_override >= 0) | |
3746 | a = fastio_reg_override; | |
3747 | do_load_word(a, tl, offset_reg); | |
3748 | break; | |
1fd1aceb | 3749 | } |
630b122b | 3750 | case 0x3a: { // SWC2 |
1fd1aceb | 3751 | #ifdef DESTRUCTIVE_SHIFT |
3752 | if(!offset&&!c&&s>=0) emit_mov(s,ar); | |
3753 | #endif | |
630b122b | 3754 | int a = ar; |
3755 | if (fastio_reg_override >= 0) | |
3756 | a = fastio_reg_override; | |
3757 | do_store_word(a, 0, tl, offset_reg, 1); | |
3758 | break; | |
3759 | } | |
3760 | default: | |
3761 | assert(0); | |
1fd1aceb | 3762 | } |
b9b61529 | 3763 | } |
630b122b | 3764 | if (fastio_reg_override == HOST_TEMPREG || offset_reg == HOST_TEMPREG) |
3765 | host_tempreg_release(); | |
b9b61529 | 3766 | if(jaddr2) |
630b122b | 3767 | add_stub_r(type,jaddr2,out,i,ar,i_regs,ccadj_,reglist); |
3768 | if(dops[i].opcode==0x3a) // SWC2 | |
3769 | if(!(i_regs->waswritten&(1<<dops[i].rs1)) && !HACK_ENABLED(NDHACK_NO_SMC_CHECK)) { | |
b9b61529 | 3770 | #if defined(HOST_IMM8) |
3771 | int ir=get_reg(i_regs->regmap,INVCP); | |
3772 | assert(ir>=0); | |
3773 | emit_cmpmem_indexedsr12_reg(ir,ar,1); | |
3774 | #else | |
630b122b | 3775 | emit_cmpmem_indexedsr12_imm(invalid_code,ar,1); |
b9b61529 | 3776 | #endif |
0bbd1454 | 3777 | #if defined(HAVE_CONDITIONAL_CALL) && !defined(DESTRUCTIVE_SHIFT) |
3778 | emit_callne(invalidate_addr_reg[ar]); | |
3779 | #else | |
630b122b | 3780 | void *jaddr3 = out; |
b9b61529 | 3781 | emit_jne(0); |
630b122b | 3782 | add_stub(INVCODE_STUB,jaddr3,out,reglist|(1<<HOST_CCREG),ar,0,0,0); |
0bbd1454 | 3783 | #endif |
b9b61529 | 3784 | } |
630b122b | 3785 | if (dops[i].opcode==0x32) { // LWC2 |
3786 | host_tempreg_acquire(); | |
3787 | cop2_put_dreg(copr,tl,HOST_TEMPREG); | |
3788 | host_tempreg_release(); | |
3789 | } | |
3790 | } | |
3791 | ||
3792 | static void cop2_assemble(int i, const struct regstat *i_regs) | |
3793 | { | |
3794 | u_int copr = (source[i]>>11) & 0x1f; | |
3795 | signed char temp = get_reg(i_regs->regmap, -1); | |
3796 | ||
3797 | if (!HACK_ENABLED(NDHACK_NO_STALLS)) { | |
3798 | u_int reglist = reglist_exclude(get_host_reglist(i_regs->regmap), temp, -1); | |
3799 | if (dops[i].opcode2 == 0 || dops[i].opcode2 == 2) { // MFC2/CFC2 | |
3800 | signed char tl = get_reg(i_regs->regmap, dops[i].rt1); | |
3801 | reglist = reglist_exclude(reglist, tl, -1); | |
3802 | } | |
3803 | cop2_do_stall_check(0, i, i_regs, reglist); | |
3804 | } | |
3805 | if (dops[i].opcode2==0) { // MFC2 | |
3806 | signed char tl=get_reg(i_regs->regmap,dops[i].rt1); | |
3807 | if(tl>=0&&dops[i].rt1!=0) | |
3808 | cop2_get_dreg(copr,tl,temp); | |
3809 | } | |
3810 | else if (dops[i].opcode2==4) { // MTC2 | |
3811 | signed char sl=get_reg(i_regs->regmap,dops[i].rs1); | |
3812 | cop2_put_dreg(copr,sl,temp); | |
3813 | } | |
3814 | else if (dops[i].opcode2==2) // CFC2 | |
3815 | { | |
3816 | signed char tl=get_reg(i_regs->regmap,dops[i].rt1); | |
3817 | if(tl>=0&&dops[i].rt1!=0) | |
3818 | emit_readword(®_cop2c[copr],tl); | |
b9b61529 | 3819 | } |
630b122b | 3820 | else if (dops[i].opcode2==6) // CTC2 |
3821 | { | |
3822 | signed char sl=get_reg(i_regs->regmap,dops[i].rs1); | |
3823 | switch(copr) { | |
3824 | case 4: | |
3825 | case 12: | |
3826 | case 20: | |
3827 | case 26: | |
3828 | case 27: | |
3829 | case 29: | |
3830 | case 30: | |
3831 | emit_signextend16(sl,temp); | |
3832 | break; | |
3833 | case 31: | |
3834 | c2op_ctc2_31_assemble(sl,temp); | |
3835 | break; | |
3836 | default: | |
3837 | temp=sl; | |
3838 | break; | |
3839 | } | |
3840 | emit_writeword(temp,®_cop2c[copr]); | |
3841 | assert(sl>=0); | |
3842 | } | |
3843 | } | |
3844 | ||
3845 | static void do_unalignedwritestub(int n) | |
3846 | { | |
3847 | assem_debug("do_unalignedwritestub %x\n",start+stubs[n].a*4); | |
3848 | literal_pool(256); | |
3849 | set_jump_target(stubs[n].addr, out); | |
3850 | ||
3851 | int i=stubs[n].a; | |
3852 | struct regstat *i_regs=(struct regstat *)stubs[n].c; | |
3853 | int addr=stubs[n].b; | |
3854 | u_int reglist=stubs[n].e; | |
3855 | signed char *i_regmap=i_regs->regmap; | |
3856 | int temp2=get_reg(i_regmap,FTEMP); | |
3857 | int rt; | |
3858 | rt=get_reg(i_regmap,dops[i].rs2); | |
3859 | assert(rt>=0); | |
3860 | assert(addr>=0); | |
3861 | assert(dops[i].opcode==0x2a||dops[i].opcode==0x2e); // SWL/SWR only implemented | |
3862 | reglist|=(1<<addr); | |
3863 | reglist&=~(1<<temp2); | |
3864 | ||
3865 | // don't bother with it and call write handler | |
3866 | save_regs(reglist); | |
3867 | pass_args(addr,rt); | |
3868 | int cc=get_reg(i_regmap,CCREG); | |
3869 | if(cc<0) | |
3870 | emit_loadreg(CCREG,2); | |
3871 | emit_addimm(cc<0?2:cc,(int)stubs[n].d+1,2); | |
3872 | emit_far_call((dops[i].opcode==0x2a?jump_handle_swl:jump_handle_swr)); | |
3873 | emit_addimm(0,-((int)stubs[n].d+1),cc<0?2:cc); | |
3874 | if(cc<0) | |
3875 | emit_storereg(CCREG,2); | |
3876 | restore_regs(reglist); | |
3877 | emit_jmp(stubs[n].retaddr); // return address | |
b9b61529 | 3878 | } |
3879 | ||
57871462 | 3880 | #ifndef multdiv_assemble |
3881 | void multdiv_assemble(int i,struct regstat *i_regs) | |
3882 | { | |
3883 | printf("Need multdiv_assemble for this architecture.\n"); | |
630b122b | 3884 | abort(); |
57871462 | 3885 | } |
3886 | #endif | |
3887 | ||
630b122b | 3888 | static void mov_assemble(int i, const struct regstat *i_regs) |
57871462 | 3889 | { |
630b122b | 3890 | //if(dops[i].opcode2==0x10||dops[i].opcode2==0x12) { // MFHI/MFLO |
3891 | //if(dops[i].opcode2==0x11||dops[i].opcode2==0x13) { // MTHI/MTLO | |
3892 | if(dops[i].rt1) { | |
3893 | signed char sl,tl; | |
3894 | tl=get_reg(i_regs->regmap,dops[i].rt1); | |
57871462 | 3895 | //assert(tl>=0); |
3896 | if(tl>=0) { | |
630b122b | 3897 | sl=get_reg(i_regs->regmap,dops[i].rs1); |
57871462 | 3898 | if(sl>=0) emit_mov(sl,tl); |
630b122b | 3899 | else emit_loadreg(dops[i].rs1,tl); |
57871462 | 3900 | } |
3901 | } | |
630b122b | 3902 | if (dops[i].rs1 == HIREG || dops[i].rs1 == LOREG) // MFHI/MFLO |
3903 | multdiv_do_stall(i, i_regs); | |
57871462 | 3904 | } |
3905 | ||
630b122b | 3906 | // call interpreter, exception handler, things that change pc/regs/cycles ... |
3907 | static void call_c_cpu_handler(int i, const struct regstat *i_regs, int ccadj_, u_int pc, void *func) | |
57871462 | 3908 | { |
630b122b | 3909 | signed char ccreg=get_reg(i_regs->regmap,CCREG); |
3910 | assert(ccreg==HOST_CCREG); | |
3911 | assert(!is_delayslot); | |
3912 | (void)ccreg; | |
3913 | ||
3914 | emit_movimm(pc,3); // Get PC | |
3915 | emit_readword(&last_count,2); | |
3916 | emit_writeword(3,&psxRegs.pc); | |
3917 | emit_addimm(HOST_CCREG,ccadj_,HOST_CCREG); | |
3918 | emit_add(2,HOST_CCREG,2); | |
3919 | emit_writeword(2,&psxRegs.cycle); | |
3920 | emit_far_call(func); | |
3921 | emit_far_jump(jump_to_new_pc); | |
57871462 | 3922 | } |
57871462 | 3923 | |
630b122b | 3924 | static void syscall_assemble(int i, const struct regstat *i_regs, int ccadj_) |
57871462 | 3925 | { |
630b122b | 3926 | emit_movimm(0x20,0); // cause code |
3927 | emit_movimm(0,1); // not in delay slot | |
3928 | call_c_cpu_handler(i, i_regs, ccadj_, start+i*4, psxException); | |
57871462 | 3929 | } |
57871462 | 3930 | |
630b122b | 3931 | static void hlecall_assemble(int i, const struct regstat *i_regs, int ccadj_) |
57871462 | 3932 | { |
630b122b | 3933 | void *hlefunc = psxNULL; |
3934 | uint32_t hleCode = source[i] & 0x03ffffff; | |
3935 | if (hleCode < ARRAY_SIZE(psxHLEt)) | |
3936 | hlefunc = psxHLEt[hleCode]; | |
3937 | ||
3938 | call_c_cpu_handler(i, i_regs, ccadj_, start + i*4+4, hlefunc); | |
7139f3c8 | 3939 | } |
3940 | ||
630b122b | 3941 | static void intcall_assemble(int i, const struct regstat *i_regs, int ccadj_) |
7139f3c8 | 3942 | { |
630b122b | 3943 | call_c_cpu_handler(i, i_regs, ccadj_, start + i*4, execI); |
57871462 | 3944 | } |
3945 | ||
630b122b | 3946 | static void speculate_mov(int rs,int rt) |
1e973cb0 | 3947 | { |
630b122b | 3948 | if(rt!=0) { |
3949 | smrv_strong_next|=1<<rt; | |
3950 | smrv[rt]=smrv[rs]; | |
3951 | } | |
1e973cb0 | 3952 | } |
3953 | ||
630b122b | 3954 | static void speculate_mov_weak(int rs,int rt) |
57871462 | 3955 | { |
630b122b | 3956 | if(rt!=0) { |
3957 | smrv_weak_next|=1<<rt; | |
3958 | smrv[rt]=smrv[rs]; | |
3959 | } | |
3960 | } | |
3961 | ||
3962 | static void speculate_register_values(int i) | |
3963 | { | |
3964 | if(i==0) { | |
3965 | memcpy(smrv,psxRegs.GPR.r,sizeof(smrv)); | |
3966 | // gp,sp are likely to stay the same throughout the block | |
3967 | smrv_strong_next=(1<<28)|(1<<29)|(1<<30); | |
3968 | smrv_weak_next=~smrv_strong_next; | |
3969 | //printf(" llr %08x\n", smrv[4]); | |
3970 | } | |
3971 | smrv_strong=smrv_strong_next; | |
3972 | smrv_weak=smrv_weak_next; | |
3973 | switch(dops[i].itype) { | |
3974 | case ALU: | |
3975 | if ((smrv_strong>>dops[i].rs1)&1) speculate_mov(dops[i].rs1,dops[i].rt1); | |
3976 | else if((smrv_strong>>dops[i].rs2)&1) speculate_mov(dops[i].rs2,dops[i].rt1); | |
3977 | else if((smrv_weak>>dops[i].rs1)&1) speculate_mov_weak(dops[i].rs1,dops[i].rt1); | |
3978 | else if((smrv_weak>>dops[i].rs2)&1) speculate_mov_weak(dops[i].rs2,dops[i].rt1); | |
3979 | else { | |
3980 | smrv_strong_next&=~(1<<dops[i].rt1); | |
3981 | smrv_weak_next&=~(1<<dops[i].rt1); | |
3982 | } | |
3983 | break; | |
3984 | case SHIFTIMM: | |
3985 | smrv_strong_next&=~(1<<dops[i].rt1); | |
3986 | smrv_weak_next&=~(1<<dops[i].rt1); | |
3987 | // fallthrough | |
3988 | case IMM16: | |
3989 | if(dops[i].rt1&&is_const(®s[i],dops[i].rt1)) { | |
3990 | int value,hr=get_reg(regs[i].regmap,dops[i].rt1); | |
3991 | if(hr>=0) { | |
3992 | if(get_final_value(hr,i,&value)) | |
3993 | smrv[dops[i].rt1]=value; | |
3994 | else smrv[dops[i].rt1]=constmap[i][hr]; | |
3995 | smrv_strong_next|=1<<dops[i].rt1; | |
3996 | } | |
3997 | } | |
3998 | else { | |
3999 | if ((smrv_strong>>dops[i].rs1)&1) speculate_mov(dops[i].rs1,dops[i].rt1); | |
4000 | else if((smrv_weak>>dops[i].rs1)&1) speculate_mov_weak(dops[i].rs1,dops[i].rt1); | |
4001 | } | |
4002 | break; | |
4003 | case LOAD: | |
4004 | if(start<0x2000&&(dops[i].rt1==26||(smrv[dops[i].rt1]>>24)==0xa0)) { | |
4005 | // special case for BIOS | |
4006 | smrv[dops[i].rt1]=0xa0000000; | |
4007 | smrv_strong_next|=1<<dops[i].rt1; | |
4008 | break; | |
4009 | } | |
4010 | // fallthrough | |
4011 | case SHIFT: | |
4012 | case LOADLR: | |
4013 | case MOV: | |
4014 | smrv_strong_next&=~(1<<dops[i].rt1); | |
4015 | smrv_weak_next&=~(1<<dops[i].rt1); | |
4016 | break; | |
4017 | case COP0: | |
4018 | case COP2: | |
4019 | if(dops[i].opcode2==0||dops[i].opcode2==2) { // MFC/CFC | |
4020 | smrv_strong_next&=~(1<<dops[i].rt1); | |
4021 | smrv_weak_next&=~(1<<dops[i].rt1); | |
4022 | } | |
4023 | break; | |
4024 | case C2LS: | |
4025 | if (dops[i].opcode==0x32) { // LWC2 | |
4026 | smrv_strong_next&=~(1<<dops[i].rt1); | |
4027 | smrv_weak_next&=~(1<<dops[i].rt1); | |
4028 | } | |
4029 | break; | |
4030 | } | |
4031 | #if 0 | |
4032 | int r=4; | |
4033 | printf("x %08x %08x %d %d c %08x %08x\n",smrv[r],start+i*4, | |
4034 | ((smrv_strong>>r)&1),(smrv_weak>>r)&1,regs[i].isconst,regs[i].wasconst); | |
4035 | #endif | |
4036 | } | |
4037 | ||
4038 | static void ujump_assemble(int i, const struct regstat *i_regs); | |
4039 | static void rjump_assemble(int i, const struct regstat *i_regs); | |
4040 | static void cjump_assemble(int i, const struct regstat *i_regs); | |
4041 | static void sjump_assemble(int i, const struct regstat *i_regs); | |
4042 | static void pagespan_assemble(int i, const struct regstat *i_regs); | |
4043 | ||
4044 | static int assemble(int i, const struct regstat *i_regs, int ccadj_) | |
4045 | { | |
4046 | int ds = 0; | |
4047 | switch (dops[i].itype) { | |
57871462 | 4048 | case ALU: |
630b122b | 4049 | alu_assemble(i, i_regs); |
4050 | break; | |
57871462 | 4051 | case IMM16: |
630b122b | 4052 | imm16_assemble(i, i_regs); |
4053 | break; | |
57871462 | 4054 | case SHIFT: |
630b122b | 4055 | shift_assemble(i, i_regs); |
4056 | break; | |
57871462 | 4057 | case SHIFTIMM: |
630b122b | 4058 | shiftimm_assemble(i, i_regs); |
4059 | break; | |
57871462 | 4060 | case LOAD: |
630b122b | 4061 | load_assemble(i, i_regs, ccadj_); |
4062 | break; | |
57871462 | 4063 | case LOADLR: |
630b122b | 4064 | loadlr_assemble(i, i_regs, ccadj_); |
4065 | break; | |
57871462 | 4066 | case STORE: |
630b122b | 4067 | store_assemble(i, i_regs, ccadj_); |
4068 | break; | |
57871462 | 4069 | case STORELR: |
630b122b | 4070 | storelr_assemble(i, i_regs, ccadj_); |
4071 | break; | |
57871462 | 4072 | case COP0: |
630b122b | 4073 | cop0_assemble(i, i_regs, ccadj_); |
4074 | break; | |
57871462 | 4075 | case COP1: |
630b122b | 4076 | cop1_assemble(i, i_regs); |
4077 | break; | |
57871462 | 4078 | case C1LS: |
630b122b | 4079 | c1ls_assemble(i, i_regs); |
4080 | break; | |
b9b61529 | 4081 | case COP2: |
630b122b | 4082 | cop2_assemble(i, i_regs); |
4083 | break; | |
b9b61529 | 4084 | case C2LS: |
630b122b | 4085 | c2ls_assemble(i, i_regs, ccadj_); |
4086 | break; | |
b9b61529 | 4087 | case C2OP: |
630b122b | 4088 | c2op_assemble(i, i_regs); |
4089 | break; | |
57871462 | 4090 | case MULTDIV: |
630b122b | 4091 | multdiv_assemble(i, i_regs); |
4092 | multdiv_prepare_stall(i, i_regs, ccadj_); | |
4093 | break; | |
57871462 | 4094 | case MOV: |
630b122b | 4095 | mov_assemble(i, i_regs); |
4096 | break; | |
4097 | case SYSCALL: | |
4098 | syscall_assemble(i, i_regs, ccadj_); | |
4099 | break; | |
4100 | case HLECALL: | |
4101 | hlecall_assemble(i, i_regs, ccadj_); | |
4102 | break; | |
4103 | case INTCALL: | |
4104 | intcall_assemble(i, i_regs, ccadj_); | |
4105 | break; | |
4106 | case UJUMP: | |
4107 | ujump_assemble(i, i_regs); | |
4108 | ds = 1; | |
4109 | break; | |
4110 | case RJUMP: | |
4111 | rjump_assemble(i, i_regs); | |
4112 | ds = 1; | |
4113 | break; | |
4114 | case CJUMP: | |
4115 | cjump_assemble(i, i_regs); | |
4116 | ds = 1; | |
4117 | break; | |
4118 | case SJUMP: | |
4119 | sjump_assemble(i, i_regs); | |
4120 | ds = 1; | |
4121 | break; | |
4122 | case SPAN: | |
4123 | pagespan_assemble(i, i_regs); | |
4124 | break; | |
4125 | case NOP: | |
4126 | case OTHER: | |
4127 | case NI: | |
4128 | // not handled, just skip | |
4129 | break; | |
4130 | default: | |
4131 | assert(0); | |
4132 | } | |
4133 | return ds; | |
4134 | } | |
4135 | ||
4136 | static void ds_assemble(int i, const struct regstat *i_regs) | |
4137 | { | |
4138 | speculate_register_values(i); | |
4139 | is_delayslot = 1; | |
4140 | switch (dops[i].itype) { | |
57871462 | 4141 | case SYSCALL: |
7139f3c8 | 4142 | case HLECALL: |
1e973cb0 | 4143 | case INTCALL: |
57871462 | 4144 | case SPAN: |
4145 | case UJUMP: | |
4146 | case RJUMP: | |
4147 | case CJUMP: | |
4148 | case SJUMP: | |
c43b5311 | 4149 | SysPrintf("Jump in the delay slot. This is probably a bug.\n"); |
630b122b | 4150 | break; |
4151 | default: | |
4152 | assemble(i, i_regs, ccadj[i]); | |
57871462 | 4153 | } |
630b122b | 4154 | is_delayslot = 0; |
57871462 | 4155 | } |
4156 | ||
4157 | // Is the branch target a valid internal jump? | |
630b122b | 4158 | static int internal_branch(int addr) |
57871462 | 4159 | { |
4160 | if(addr&1) return 0; // Indirect (register) jump | |
4161 | if(addr>=start && addr<start+slen*4-4) | |
4162 | { | |
71e490c5 | 4163 | return 1; |
57871462 | 4164 | } |
4165 | return 0; | |
4166 | } | |
4167 | ||
630b122b | 4168 | static void wb_invalidate(signed char pre[],signed char entry[],uint64_t dirty,uint64_t u) |
57871462 | 4169 | { |
4170 | int hr; | |
4171 | for(hr=0;hr<HOST_REGS;hr++) { | |
4172 | if(hr!=EXCLUDE_REG) { | |
4173 | if(pre[hr]!=entry[hr]) { | |
4174 | if(pre[hr]>=0) { | |
4175 | if((dirty>>hr)&1) { | |
4176 | if(get_reg(entry,pre[hr])<0) { | |
630b122b | 4177 | assert(pre[hr]<64); |
4178 | if(!((u>>pre[hr])&1)) | |
4179 | emit_storereg(pre[hr],hr); | |
57871462 | 4180 | } |
4181 | } | |
4182 | } | |
4183 | } | |
4184 | } | |
4185 | } | |
4186 | // Move from one register to another (no writeback) | |
4187 | for(hr=0;hr<HOST_REGS;hr++) { | |
4188 | if(hr!=EXCLUDE_REG) { | |
4189 | if(pre[hr]!=entry[hr]) { | |
4190 | if(pre[hr]>=0&&(pre[hr]&63)<TEMPREG) { | |
4191 | int nr; | |
4192 | if((nr=get_reg(entry,pre[hr]))>=0) { | |
4193 | emit_mov(hr,nr); | |
4194 | } | |
4195 | } | |
4196 | } | |
4197 | } | |
4198 | } | |
4199 | } | |
57871462 | 4200 | |
4201 | // Load the specified registers | |
4202 | // This only loads the registers given as arguments because | |
4203 | // we don't want to load things that will be overwritten | |
630b122b | 4204 | static void load_regs(signed char entry[],signed char regmap[],int rs1,int rs2) |
57871462 | 4205 | { |
4206 | int hr; | |
4207 | // Load 32-bit regs | |
4208 | for(hr=0;hr<HOST_REGS;hr++) { | |
4209 | if(hr!=EXCLUDE_REG&®map[hr]>=0) { | |
4210 | if(entry[hr]!=regmap[hr]) { | |
4211 | if(regmap[hr]==rs1||regmap[hr]==rs2) | |
4212 | { | |
4213 | if(regmap[hr]==0) { | |
4214 | emit_zeroreg(hr); | |
4215 | } | |
4216 | else | |
4217 | { | |
4218 | emit_loadreg(regmap[hr],hr); | |
4219 | } | |
4220 | } | |
4221 | } | |
4222 | } | |
4223 | } | |
57871462 | 4224 | } |
4225 | ||
4226 | // Load registers prior to the start of a loop | |
4227 | // so that they are not loaded within the loop | |
4228 | static void loop_preload(signed char pre[],signed char entry[]) | |
4229 | { | |
4230 | int hr; | |
4231 | for(hr=0;hr<HOST_REGS;hr++) { | |
4232 | if(hr!=EXCLUDE_REG) { | |
4233 | if(pre[hr]!=entry[hr]) { | |
4234 | if(entry[hr]>=0) { | |
4235 | if(get_reg(pre,entry[hr])<0) { | |
4236 | assem_debug("loop preload:\n"); | |
4237 | //printf("loop preload: %d\n",hr); | |
4238 | if(entry[hr]==0) { | |
4239 | emit_zeroreg(hr); | |
4240 | } | |
4241 | else if(entry[hr]<TEMPREG) | |
4242 | { | |
4243 | emit_loadreg(entry[hr],hr); | |
4244 | } | |
4245 | else if(entry[hr]-64<TEMPREG) | |
4246 | { | |
4247 | emit_loadreg(entry[hr],hr); | |
4248 | } | |
4249 | } | |
4250 | } | |
4251 | } | |
4252 | } | |
4253 | } | |
4254 | } | |
4255 | ||
4256 | // Generate address for load/store instruction | |
b9b61529 | 4257 | // goes to AGEN for writes, FTEMP for LOADLR and cop1/2 loads |
630b122b | 4258 | void address_generation(int i, const struct regstat *i_regs, signed char entry[]) |
57871462 | 4259 | { |
630b122b | 4260 | if (dops[i].is_load || dops[i].is_store) { |
5194fb95 | 4261 | int ra=-1; |
57871462 | 4262 | int agr=AGEN1+(i&1); |
630b122b | 4263 | if(dops[i].itype==LOAD) { |
4264 | ra=get_reg(i_regs->regmap,dops[i].rt1); | |
9f51b4b9 | 4265 | if(ra<0) ra=get_reg(i_regs->regmap,-1); |
535d208a | 4266 | assert(ra>=0); |
57871462 | 4267 | } |
630b122b | 4268 | if(dops[i].itype==LOADLR) { |
57871462 | 4269 | ra=get_reg(i_regs->regmap,FTEMP); |
4270 | } | |
630b122b | 4271 | if(dops[i].itype==STORE||dops[i].itype==STORELR) { |
57871462 | 4272 | ra=get_reg(i_regs->regmap,agr); |
4273 | if(ra<0) ra=get_reg(i_regs->regmap,-1); | |
4274 | } | |
630b122b | 4275 | if(dops[i].itype==C2LS) { |
4276 | if ((dops[i].opcode&0x3b)==0x31||(dops[i].opcode&0x3b)==0x32) // LWC1/LDC1/LWC2/LDC2 | |
57871462 | 4277 | ra=get_reg(i_regs->regmap,FTEMP); |
1fd1aceb | 4278 | else { // SWC1/SDC1/SWC2/SDC2 |
57871462 | 4279 | ra=get_reg(i_regs->regmap,agr); |
4280 | if(ra<0) ra=get_reg(i_regs->regmap,-1); | |
4281 | } | |
4282 | } | |
630b122b | 4283 | int rs=get_reg(i_regs->regmap,dops[i].rs1); |
57871462 | 4284 | if(ra>=0) { |
4285 | int offset=imm[i]; | |
4286 | int c=(i_regs->wasconst>>rs)&1; | |
630b122b | 4287 | if(dops[i].rs1==0) { |
57871462 | 4288 | // Using r0 as a base address |
57871462 | 4289 | if(!entry||entry[ra]!=agr) { |
630b122b | 4290 | if (dops[i].opcode==0x22||dops[i].opcode==0x26) { |
57871462 | 4291 | emit_movimm(offset&0xFFFFFFFC,ra); // LWL/LWR |
630b122b | 4292 | }else if (dops[i].opcode==0x1a||dops[i].opcode==0x1b) { |
57871462 | 4293 | emit_movimm(offset&0xFFFFFFF8,ra); // LDL/LDR |
4294 | }else{ | |
4295 | emit_movimm(offset,ra); | |
4296 | } | |
4297 | } // else did it in the previous cycle | |
4298 | } | |
4299 | else if(rs<0) { | |
630b122b | 4300 | if(!entry||entry[ra]!=dops[i].rs1) |
4301 | emit_loadreg(dops[i].rs1,ra); | |
4302 | //if(!entry||entry[ra]!=dops[i].rs1) | |
57871462 | 4303 | // printf("poor load scheduling!\n"); |
4304 | } | |
4305 | else if(c) { | |
630b122b | 4306 | if(dops[i].rs1!=dops[i].rt1||dops[i].itype!=LOAD) { |
57871462 | 4307 | if(!entry||entry[ra]!=agr) { |
630b122b | 4308 | if (dops[i].opcode==0x22||dops[i].opcode==0x26) { |
57871462 | 4309 | emit_movimm((constmap[i][rs]+offset)&0xFFFFFFFC,ra); // LWL/LWR |
630b122b | 4310 | }else if (dops[i].opcode==0x1a||dops[i].opcode==0x1b) { |
57871462 | 4311 | emit_movimm((constmap[i][rs]+offset)&0xFFFFFFF8,ra); // LDL/LDR |
4312 | }else{ | |
57871462 | 4313 | emit_movimm(constmap[i][rs]+offset,ra); |
8575a877 | 4314 | regs[i].loadedconst|=1<<ra; |
57871462 | 4315 | } |
4316 | } // else did it in the previous cycle | |
4317 | } // else load_consts already did it | |
4318 | } | |
630b122b | 4319 | if(offset&&!c&&dops[i].rs1) { |
57871462 | 4320 | if(rs>=0) { |
4321 | emit_addimm(rs,offset,ra); | |
4322 | }else{ | |
4323 | emit_addimm(ra,offset,ra); | |
4324 | } | |
4325 | } | |
4326 | } | |
4327 | } | |
4328 | // Preload constants for next instruction | |
630b122b | 4329 | if (dops[i+1].is_load || dops[i+1].is_store) { |
57871462 | 4330 | int agr,ra; |
57871462 | 4331 | // Actual address |
4332 | agr=AGEN1+((i+1)&1); | |
4333 | ra=get_reg(i_regs->regmap,agr); | |
4334 | if(ra>=0) { | |
630b122b | 4335 | int rs=get_reg(regs[i+1].regmap,dops[i+1].rs1); |
57871462 | 4336 | int offset=imm[i+1]; |
4337 | int c=(regs[i+1].wasconst>>rs)&1; | |
630b122b | 4338 | if(c&&(dops[i+1].rs1!=dops[i+1].rt1||dops[i+1].itype!=LOAD)) { |
4339 | if (dops[i+1].opcode==0x22||dops[i+1].opcode==0x26) { | |
57871462 | 4340 | emit_movimm((constmap[i+1][rs]+offset)&0xFFFFFFFC,ra); // LWL/LWR |
630b122b | 4341 | }else if (dops[i+1].opcode==0x1a||dops[i+1].opcode==0x1b) { |
57871462 | 4342 | emit_movimm((constmap[i+1][rs]+offset)&0xFFFFFFF8,ra); // LDL/LDR |
4343 | }else{ | |
57871462 | 4344 | emit_movimm(constmap[i+1][rs]+offset,ra); |
8575a877 | 4345 | regs[i+1].loadedconst|=1<<ra; |
57871462 | 4346 | } |
4347 | } | |
630b122b | 4348 | else if(dops[i+1].rs1==0) { |
57871462 | 4349 | // Using r0 as a base address |
630b122b | 4350 | if (dops[i+1].opcode==0x22||dops[i+1].opcode==0x26) { |
57871462 | 4351 | emit_movimm(offset&0xFFFFFFFC,ra); // LWL/LWR |
630b122b | 4352 | }else if (dops[i+1].opcode==0x1a||dops[i+1].opcode==0x1b) { |
57871462 | 4353 | emit_movimm(offset&0xFFFFFFF8,ra); // LDL/LDR |
4354 | }else{ | |
4355 | emit_movimm(offset,ra); | |
4356 | } | |
4357 | } | |
4358 | } | |
4359 | } | |
4360 | } | |
4361 | ||
e2b5e7aa | 4362 | static int get_final_value(int hr, int i, int *value) |
57871462 | 4363 | { |
4364 | int reg=regs[i].regmap[hr]; | |
4365 | while(i<slen-1) { | |
4366 | if(regs[i+1].regmap[hr]!=reg) break; | |
4367 | if(!((regs[i+1].isconst>>hr)&1)) break; | |
630b122b | 4368 | if(dops[i+1].bt) break; |
57871462 | 4369 | i++; |
4370 | } | |
4371 | if(i<slen-1) { | |
630b122b | 4372 | if (dops[i].is_jump) { |
57871462 | 4373 | *value=constmap[i][hr]; |
4374 | return 1; | |
4375 | } | |
630b122b | 4376 | if(!dops[i+1].bt) { |
4377 | if (dops[i+1].is_jump) { | |
57871462 | 4378 | // Load in delay slot, out-of-order execution |
630b122b | 4379 | if(dops[i+2].itype==LOAD&&dops[i+2].rs1==reg&&dops[i+2].rt1==reg&&((regs[i+1].wasconst>>hr)&1)) |
57871462 | 4380 | { |
57871462 | 4381 | // Precompute load address |
4382 | *value=constmap[i][hr]+imm[i+2]; | |
4383 | return 1; | |
4384 | } | |
4385 | } | |
630b122b | 4386 | if(dops[i+1].itype==LOAD&&dops[i+1].rs1==reg&&dops[i+1].rt1==reg) |
57871462 | 4387 | { |
57871462 | 4388 | // Precompute load address |
4389 | *value=constmap[i][hr]+imm[i+1]; | |
630b122b | 4390 | //printf("c=%x imm=%lx\n",(long)constmap[i][hr],imm[i+1]); |
57871462 | 4391 | return 1; |
4392 | } | |
4393 | } | |
4394 | } | |
4395 | *value=constmap[i][hr]; | |
630b122b | 4396 | //printf("c=%lx\n",(long)constmap[i][hr]); |
57871462 | 4397 | if(i==slen-1) return 1; |
630b122b | 4398 | assert(reg < 64); |
4399 | return !((unneeded_reg[i+1]>>reg)&1); | |
57871462 | 4400 | } |
4401 | ||
4402 | // Load registers with known constants | |
630b122b | 4403 | static void load_consts(signed char pre[],signed char regmap[],int i) |
57871462 | 4404 | { |
8575a877 | 4405 | int hr,hr2; |
4406 | // propagate loaded constant flags | |
630b122b | 4407 | if(i==0||dops[i].bt) |
8575a877 | 4408 | regs[i].loadedconst=0; |
4409 | else { | |
4410 | for(hr=0;hr<HOST_REGS;hr++) { | |
4411 | if(hr!=EXCLUDE_REG&®map[hr]>=0&&((regs[i-1].isconst>>hr)&1)&&pre[hr]==regmap[hr] | |
4412 | &®map[hr]==regs[i-1].regmap[hr]&&((regs[i-1].loadedconst>>hr)&1)) | |
4413 | { | |
4414 | regs[i].loadedconst|=1<<hr; | |
4415 | } | |
4416 | } | |
4417 | } | |
57871462 | 4418 | // Load 32-bit regs |
4419 | for(hr=0;hr<HOST_REGS;hr++) { | |
4420 | if(hr!=EXCLUDE_REG&®map[hr]>=0) { | |
4421 | //if(entry[hr]!=regmap[hr]) { | |
8575a877 | 4422 | if(!((regs[i].loadedconst>>hr)&1)) { |
630b122b | 4423 | assert(regmap[hr]<64); |
4424 | if(((regs[i].isconst>>hr)&1)&®map[hr]>0) { | |
8575a877 | 4425 | int value,similar=0; |
57871462 | 4426 | if(get_final_value(hr,i,&value)) { |
8575a877 | 4427 | // see if some other register has similar value |
4428 | for(hr2=0;hr2<HOST_REGS;hr2++) { | |
4429 | if(hr2!=EXCLUDE_REG&&((regs[i].loadedconst>>hr2)&1)) { | |
4430 | if(is_similar_value(value,constmap[i][hr2])) { | |
4431 | similar=1; | |
4432 | break; | |
4433 | } | |
4434 | } | |
4435 | } | |
4436 | if(similar) { | |
4437 | int value2; | |
4438 | if(get_final_value(hr2,i,&value2)) // is this needed? | |
4439 | emit_movimm_from(value2,hr2,value,hr); | |
4440 | else | |
4441 | emit_movimm(value,hr); | |
4442 | } | |
4443 | else if(value==0) { | |
57871462 | 4444 | emit_zeroreg(hr); |
4445 | } | |
4446 | else { | |
4447 | emit_movimm(value,hr); | |
4448 | } | |
4449 | } | |
8575a877 | 4450 | regs[i].loadedconst|=1<<hr; |
57871462 | 4451 | } |
4452 | } | |
4453 | } | |
4454 | } | |
57871462 | 4455 | } |
630b122b | 4456 | |
4457 | static void load_all_consts(const signed char regmap[], u_int dirty, int i) | |
57871462 | 4458 | { |
4459 | int hr; | |
4460 | // Load 32-bit regs | |
4461 | for(hr=0;hr<HOST_REGS;hr++) { | |
4462 | if(hr!=EXCLUDE_REG&®map[hr]>=0&&((dirty>>hr)&1)) { | |
630b122b | 4463 | assert(regmap[hr] < 64); |
4464 | if(((regs[i].isconst>>hr)&1)&®map[hr]>0) { | |
57871462 | 4465 | int value=constmap[i][hr]; |
4466 | if(value==0) { | |
4467 | emit_zeroreg(hr); | |
4468 | } | |
4469 | else { | |
4470 | emit_movimm(value,hr); | |
4471 | } | |
4472 | } | |
4473 | } | |
4474 | } | |
57871462 | 4475 | } |
4476 | ||
4477 | // Write out all dirty registers (except cycle count) | |
630b122b | 4478 | static void wb_dirtys(const signed char i_regmap[], uint64_t i_dirty) |
57871462 | 4479 | { |
4480 | int hr; | |
4481 | for(hr=0;hr<HOST_REGS;hr++) { | |
4482 | if(hr!=EXCLUDE_REG) { | |
4483 | if(i_regmap[hr]>0) { | |
4484 | if(i_regmap[hr]!=CCREG) { | |
4485 | if((i_dirty>>hr)&1) { | |
630b122b | 4486 | assert(i_regmap[hr]<64); |
4487 | emit_storereg(i_regmap[hr],hr); | |
57871462 | 4488 | } |
4489 | } | |
4490 | } | |
4491 | } | |
4492 | } | |
4493 | } | |
630b122b | 4494 | |
57871462 | 4495 | // Write out dirty registers that we need to reload (pair with load_needed_regs) |
4496 | // This writes the registers not written by store_regs_bt | |
630b122b | 4497 | static void wb_needed_dirtys(const signed char i_regmap[], uint64_t i_dirty, int addr) |
57871462 | 4498 | { |
4499 | int hr; | |
4500 | int t=(addr-start)>>2; | |
4501 | for(hr=0;hr<HOST_REGS;hr++) { | |
4502 | if(hr!=EXCLUDE_REG) { | |
4503 | if(i_regmap[hr]>0) { | |
4504 | if(i_regmap[hr]!=CCREG) { | |
630b122b | 4505 | if(i_regmap[hr]==regs[t].regmap_entry[hr] && ((regs[t].dirty>>hr)&1)) { |
57871462 | 4506 | if((i_dirty>>hr)&1) { |
630b122b | 4507 | assert(i_regmap[hr]<64); |
4508 | emit_storereg(i_regmap[hr],hr); | |
57871462 | 4509 | } |
4510 | } | |
4511 | } | |
4512 | } | |
4513 | } | |
4514 | } | |
4515 | } | |
4516 | ||
4517 | // Load all registers (except cycle count) | |
630b122b | 4518 | static void load_all_regs(const signed char i_regmap[]) |
57871462 | 4519 | { |
4520 | int hr; | |
4521 | for(hr=0;hr<HOST_REGS;hr++) { | |
4522 | if(hr!=EXCLUDE_REG) { | |
4523 | if(i_regmap[hr]==0) { | |
4524 | emit_zeroreg(hr); | |
4525 | } | |
4526 | else | |
ea3d2e6e | 4527 | if(i_regmap[hr]>0 && (i_regmap[hr]&63)<TEMPREG && i_regmap[hr]!=CCREG) |
57871462 | 4528 | { |
4529 | emit_loadreg(i_regmap[hr],hr); | |
4530 | } | |
4531 | } | |
4532 | } | |
4533 | } | |
4534 | ||
4535 | // Load all current registers also needed by next instruction | |
630b122b | 4536 | static void load_needed_regs(const signed char i_regmap[], const signed char next_regmap[]) |
57871462 | 4537 | { |
4538 | int hr; | |
4539 | for(hr=0;hr<HOST_REGS;hr++) { | |
4540 | if(hr!=EXCLUDE_REG) { | |
4541 | if(get_reg(next_regmap,i_regmap[hr])>=0) { | |
4542 | if(i_regmap[hr]==0) { | |
4543 | emit_zeroreg(hr); | |
4544 | } | |
4545 | else | |
ea3d2e6e | 4546 | if(i_regmap[hr]>0 && (i_regmap[hr]&63)<TEMPREG && i_regmap[hr]!=CCREG) |
57871462 | 4547 | { |
4548 | emit_loadreg(i_regmap[hr],hr); | |
4549 | } | |
4550 | } | |
4551 | } | |
4552 | } | |
4553 | } | |
4554 | ||
4555 | // Load all regs, storing cycle count if necessary | |
630b122b | 4556 | static void load_regs_entry(int t) |
57871462 | 4557 | { |
4558 | int hr; | |
630b122b | 4559 | if(dops[t].is_ds) emit_addimm(HOST_CCREG,CLOCK_ADJUST(1),HOST_CCREG); |
4560 | else if(ccadj[t]) emit_addimm(HOST_CCREG,-ccadj[t],HOST_CCREG); | |
57871462 | 4561 | if(regs[t].regmap_entry[HOST_CCREG]!=CCREG) { |
4562 | emit_storereg(CCREG,HOST_CCREG); | |
4563 | } | |
4564 | // Load 32-bit regs | |
4565 | for(hr=0;hr<HOST_REGS;hr++) { | |
ea3d2e6e | 4566 | if(regs[t].regmap_entry[hr]>=0&®s[t].regmap_entry[hr]<TEMPREG) { |
57871462 | 4567 | if(regs[t].regmap_entry[hr]==0) { |
4568 | emit_zeroreg(hr); | |
4569 | } | |
4570 | else if(regs[t].regmap_entry[hr]!=CCREG) | |
4571 | { | |
4572 | emit_loadreg(regs[t].regmap_entry[hr],hr); | |
4573 | } | |
4574 | } | |
4575 | } | |
57871462 | 4576 | } |
4577 | ||
4578 | // Store dirty registers prior to branch | |
630b122b | 4579 | void store_regs_bt(signed char i_regmap[],uint64_t i_dirty,int addr) |
57871462 | 4580 | { |
630b122b | 4581 | if(internal_branch(addr)) |
57871462 | 4582 | { |
4583 | int t=(addr-start)>>2; | |
4584 | int hr; | |
4585 | for(hr=0;hr<HOST_REGS;hr++) { | |
4586 | if(hr!=EXCLUDE_REG) { | |
4587 | if(i_regmap[hr]>0 && i_regmap[hr]!=CCREG) { | |
630b122b | 4588 | if(i_regmap[hr]!=regs[t].regmap_entry[hr] || !((regs[t].dirty>>hr)&1)) { |
57871462 | 4589 | if((i_dirty>>hr)&1) { |
630b122b | 4590 | assert(i_regmap[hr]<64); |
4591 | if(!((unneeded_reg[t]>>i_regmap[hr])&1)) | |
4592 | emit_storereg(i_regmap[hr],hr); | |
57871462 | 4593 | } |
4594 | } | |
4595 | } | |
4596 | } | |
4597 | } | |
4598 | } | |
4599 | else | |
4600 | { | |
4601 | // Branch out of this block, write out all dirty regs | |
630b122b | 4602 | wb_dirtys(i_regmap,i_dirty); |
57871462 | 4603 | } |
4604 | } | |
4605 | ||
4606 | // Load all needed registers for branch target | |
630b122b | 4607 | static void load_regs_bt(signed char i_regmap[],uint64_t i_dirty,int addr) |
57871462 | 4608 | { |
4609 | //if(addr>=start && addr<(start+slen*4)) | |
630b122b | 4610 | if(internal_branch(addr)) |
57871462 | 4611 | { |
4612 | int t=(addr-start)>>2; | |
4613 | int hr; | |
4614 | // Store the cycle count before loading something else | |
4615 | if(i_regmap[HOST_CCREG]!=CCREG) { | |
4616 | assert(i_regmap[HOST_CCREG]==-1); | |
4617 | } | |
4618 | if(regs[t].regmap_entry[HOST_CCREG]!=CCREG) { | |
4619 | emit_storereg(CCREG,HOST_CCREG); | |
4620 | } | |
4621 | // Load 32-bit regs | |
4622 | for(hr=0;hr<HOST_REGS;hr++) { | |
ea3d2e6e | 4623 | if(hr!=EXCLUDE_REG&®s[t].regmap_entry[hr]>=0&®s[t].regmap_entry[hr]<TEMPREG) { |
630b122b | 4624 | if(i_regmap[hr]!=regs[t].regmap_entry[hr]) { |
57871462 | 4625 | if(regs[t].regmap_entry[hr]==0) { |
4626 | emit_zeroreg(hr); | |
4627 | } | |
4628 | else if(regs[t].regmap_entry[hr]!=CCREG) | |
4629 | { | |
4630 | emit_loadreg(regs[t].regmap_entry[hr],hr); | |
4631 | } | |
4632 | } | |
4633 | } | |
4634 | } | |
57871462 | 4635 | } |
4636 | } | |
4637 | ||
630b122b | 4638 | static int match_bt(signed char i_regmap[],uint64_t i_dirty,int addr) |
57871462 | 4639 | { |
4640 | if(addr>=start && addr<start+slen*4-4) | |
4641 | { | |
4642 | int t=(addr-start)>>2; | |
4643 | int hr; | |
4644 | if(regs[t].regmap_entry[HOST_CCREG]!=CCREG) return 0; | |
4645 | for(hr=0;hr<HOST_REGS;hr++) | |
4646 | { | |
4647 | if(hr!=EXCLUDE_REG) | |
4648 | { | |
4649 | if(i_regmap[hr]!=regs[t].regmap_entry[hr]) | |
4650 | { | |
ea3d2e6e | 4651 | if(regs[t].regmap_entry[hr]>=0&&(regs[t].regmap_entry[hr]|64)<TEMPREG+64) |
57871462 | 4652 | { |
4653 | return 0; | |
4654 | } | |
9f51b4b9 | 4655 | else |
57871462 | 4656 | if((i_dirty>>hr)&1) |
4657 | { | |
ea3d2e6e | 4658 | if(i_regmap[hr]<TEMPREG) |
57871462 | 4659 | { |
4660 | if(!((unneeded_reg[t]>>i_regmap[hr])&1)) | |
4661 | return 0; | |
4662 | } | |
ea3d2e6e | 4663 | else if(i_regmap[hr]>=64&&i_regmap[hr]<TEMPREG+64) |
57871462 | 4664 | { |
630b122b | 4665 | assert(0); |
57871462 | 4666 | } |
4667 | } | |
4668 | } | |
4669 | else // Same register but is it 32-bit or dirty? | |
4670 | if(i_regmap[hr]>=0) | |
4671 | { | |
4672 | if(!((regs[t].dirty>>hr)&1)) | |
4673 | { | |
4674 | if((i_dirty>>hr)&1) | |
4675 | { | |
4676 | if(!((unneeded_reg[t]>>i_regmap[hr])&1)) | |
4677 | { | |
4678 | //printf("%x: dirty no match\n",addr); | |
4679 | return 0; | |
4680 | } | |
4681 | } | |
4682 | } | |
57871462 | 4683 | } |
4684 | } | |
4685 | } | |
57871462 | 4686 | // Delay slots are not valid branch targets |
630b122b | 4687 | //if(t>0&&(dops[t-1].is_jump) return 0; |
57871462 | 4688 | // Delay slots require additional processing, so do not match |
630b122b | 4689 | if(dops[t].is_ds) return 0; |
57871462 | 4690 | } |
4691 | else | |
4692 | { | |
4693 | int hr; | |
4694 | for(hr=0;hr<HOST_REGS;hr++) | |
4695 | { | |
4696 | if(hr!=EXCLUDE_REG) | |
4697 | { | |
4698 | if(i_regmap[hr]>=0) | |
4699 | { | |
4700 | if(hr!=HOST_CCREG||i_regmap[hr]!=CCREG) | |
4701 | { | |
4702 | if((i_dirty>>hr)&1) | |
4703 | { | |
4704 | return 0; | |
4705 | } | |
4706 | } | |
4707 | } | |
4708 | } | |
4709 | } | |
4710 | } | |
4711 | return 1; | |
4712 | } | |
4713 | ||
630b122b | 4714 | #ifdef DRC_DBG |
4715 | static void drc_dbg_emit_do_cmp(int i, int ccadj_) | |
57871462 | 4716 | { |
630b122b | 4717 | extern void do_insn_cmp(); |
4718 | //extern int cycle; | |
4719 | u_int hr, reglist = get_host_reglist(regs[i].regmap); | |
4720 | ||
4721 | assem_debug("//do_insn_cmp %08x\n", start+i*4); | |
4722 | save_regs(reglist); | |
4723 | // write out changed consts to match the interpreter | |
4724 | if (i > 0 && !dops[i].bt) { | |
4725 | for (hr = 0; hr < HOST_REGS; hr++) { | |
4726 | int reg = regs[i].regmap_entry[hr]; // regs[i-1].regmap[hr]; | |
4727 | if (hr == EXCLUDE_REG || reg < 0) | |
4728 | continue; | |
4729 | if (!((regs[i-1].isconst >> hr) & 1)) | |
4730 | continue; | |
4731 | if (i > 1 && reg == regs[i-2].regmap[hr] && constmap[i-1][hr] == constmap[i-2][hr]) | |
4732 | continue; | |
4733 | emit_movimm(constmap[i-1][hr],0); | |
4734 | emit_storereg(reg, 0); | |
4735 | } | |
4736 | } | |
4737 | emit_movimm(start+i*4,0); | |
4738 | emit_writeword(0,&pcaddr); | |
4739 | int cc = get_reg(regs[i].regmap_entry, CCREG); | |
4740 | if (cc < 0) | |
4741 | emit_loadreg(CCREG, cc = 0); | |
4742 | emit_addimm(cc, ccadj_, 0); | |
4743 | emit_writeword(0, &psxRegs.cycle); | |
4744 | emit_far_call(do_insn_cmp); | |
4745 | //emit_readword(&cycle,0); | |
4746 | //emit_addimm(0,2,0); | |
4747 | //emit_writeword(0,&cycle); | |
4748 | (void)get_reg2; | |
4749 | restore_regs(reglist); | |
4750 | assem_debug("\\\\do_insn_cmp\n"); | |
4751 | } | |
4752 | #else | |
4753 | #define drc_dbg_emit_do_cmp(x,y) | |
4754 | #endif | |
4755 | ||
4756 | // Used when a branch jumps into the delay slot of another branch | |
4757 | static void ds_assemble_entry(int i) | |
4758 | { | |
4759 | int t = (ba[i] - start) >> 2; | |
4760 | int ccadj_ = -CLOCK_ADJUST(1); | |
4761 | if (!instr_addr[t]) | |
4762 | instr_addr[t] = out; | |
4763 | assem_debug("Assemble delay slot at %x\n",ba[i]); | |
4764 | assem_debug("<->\n"); | |
4765 | drc_dbg_emit_do_cmp(t, ccadj_); | |
4766 | if(regs[t].regmap_entry[HOST_CCREG]==CCREG&®s[t].regmap[HOST_CCREG]!=CCREG) | |
4767 | wb_register(CCREG,regs[t].regmap_entry,regs[t].wasdirty); | |
4768 | load_regs(regs[t].regmap_entry,regs[t].regmap,dops[t].rs1,dops[t].rs2); | |
4769 | address_generation(t,®s[t],regs[t].regmap_entry); | |
4770 | if (ram_offset && (dops[t].is_load || dops[t].is_store)) | |
4771 | load_regs(regs[t].regmap_entry,regs[t].regmap,ROREG,ROREG); | |
4772 | if (dops[t].is_store) | |
4773 | load_regs(regs[t].regmap_entry,regs[t].regmap,INVCP,INVCP); | |
4774 | is_delayslot=0; | |
4775 | switch (dops[t].itype) { | |
57871462 | 4776 | case SYSCALL: |
7139f3c8 | 4777 | case HLECALL: |
1e973cb0 | 4778 | case INTCALL: |
57871462 | 4779 | case SPAN: |
4780 | case UJUMP: | |
4781 | case RJUMP: | |
4782 | case CJUMP: | |
4783 | case SJUMP: | |
c43b5311 | 4784 | SysPrintf("Jump in the delay slot. This is probably a bug.\n"); |
630b122b | 4785 | break; |
4786 | default: | |
4787 | assemble(t, ®s[t], ccadj_); | |
57871462 | 4788 | } |
630b122b | 4789 | store_regs_bt(regs[t].regmap,regs[t].dirty,ba[i]+4); |
4790 | load_regs_bt(regs[t].regmap,regs[t].dirty,ba[i]+4); | |
4791 | if(internal_branch(ba[i]+4)) | |
57871462 | 4792 | assem_debug("branch: internal\n"); |
4793 | else | |
4794 | assem_debug("branch: external\n"); | |
630b122b | 4795 | assert(internal_branch(ba[i]+4)); |
4796 | add_to_linker(out,ba[i]+4,internal_branch(ba[i]+4)); | |
57871462 | 4797 | emit_jmp(0); |
4798 | } | |
4799 | ||
630b122b | 4800 | static void emit_extjump(void *addr, u_int target) |
4801 | { | |
4802 | emit_extjump2(addr, target, dyna_linker); | |
4803 | } | |
4804 | ||
4805 | static void emit_extjump_ds(void *addr, u_int target) | |
4806 | { | |
4807 | emit_extjump2(addr, target, dyna_linker_ds); | |
4808 | } | |
4809 | ||
4810 | // Load 2 immediates optimizing for small code size | |
4811 | static void emit_mov2imm_compact(int imm1,u_int rt1,int imm2,u_int rt2) | |
57871462 | 4812 | { |
630b122b | 4813 | emit_movimm(imm1,rt1); |
4814 | emit_movimm_from(imm1,rt1,imm2,rt2); | |
4815 | } | |
4816 | ||
4817 | static void do_cc(int i, const signed char i_regmap[], int *adj, | |
4818 | int addr, int taken, int invert) | |
4819 | { | |
4820 | int count, count_plus2; | |
4821 | void *jaddr; | |
4822 | void *idle=NULL; | |
b6e87b2b | 4823 | int t=0; |
630b122b | 4824 | if(dops[i].itype==RJUMP) |
57871462 | 4825 | { |
4826 | *adj=0; | |
4827 | } | |
4828 | //if(ba[i]>=start && ba[i]<(start+slen*4)) | |
630b122b | 4829 | if(internal_branch(ba[i])) |
57871462 | 4830 | { |
b6e87b2b | 4831 | t=(ba[i]-start)>>2; |
630b122b | 4832 | if(dops[t].is_ds) *adj=-CLOCK_ADJUST(1); // Branch into delay slot adds an extra cycle |
57871462 | 4833 | else *adj=ccadj[t]; |
4834 | } | |
4835 | else | |
4836 | { | |
4837 | *adj=0; | |
4838 | } | |
630b122b | 4839 | count = ccadj[i]; |
4840 | count_plus2 = count + CLOCK_ADJUST(2); | |
57871462 | 4841 | if(taken==TAKEN && i==(ba[i]-start)>>2 && source[i+1]==0) { |
4842 | // Idle loop | |
4843 | if(count&1) emit_addimm_and_set_flags(2*(count+2),HOST_CCREG); | |
630b122b | 4844 | idle=out; |
57871462 | 4845 | //emit_subfrommem(&idlecount,HOST_CCREG); // Count idle cycles |
4846 | emit_andimm(HOST_CCREG,3,HOST_CCREG); | |
630b122b | 4847 | jaddr=out; |
57871462 | 4848 | emit_jmp(0); |
4849 | } | |
4850 | else if(*adj==0||invert) { | |
630b122b | 4851 | int cycles = count_plus2; |
b6e87b2b | 4852 | // faster loop HACK |
630b122b | 4853 | #if 0 |
b6e87b2b | 4854 | if (t&&*adj) { |
4855 | int rel=t-i; | |
4856 | if(-NO_CYCLE_PENALTY_THR<rel&&rel<0) | |
630b122b | 4857 | cycles=*adj+count+2-*adj; |
b6e87b2b | 4858 | } |
630b122b | 4859 | #endif |
4860 | emit_addimm_and_set_flags(cycles, HOST_CCREG); | |
4861 | jaddr = out; | |
57871462 | 4862 | emit_jns(0); |
4863 | } | |
4864 | else | |
4865 | { | |
630b122b | 4866 | emit_cmpimm(HOST_CCREG, -count_plus2); |
4867 | jaddr = out; | |
57871462 | 4868 | emit_jns(0); |
4869 | } | |
630b122b | 4870 | add_stub(CC_STUB,jaddr,idle?idle:out,(*adj==0||invert||idle)?0:count_plus2,i,addr,taken,0); |
57871462 | 4871 | } |
4872 | ||
630b122b | 4873 | static void do_ccstub(int n) |
57871462 | 4874 | { |
4875 | literal_pool(256); | |
630b122b | 4876 | assem_debug("do_ccstub %x\n",start+(u_int)stubs[n].b*4); |
4877 | set_jump_target(stubs[n].addr, out); | |
4878 | int i=stubs[n].b; | |
4879 | if(stubs[n].d==NULLDS) { | |
57871462 | 4880 | // Delay slot instruction is nullified ("likely" branch) |
630b122b | 4881 | wb_dirtys(regs[i].regmap,regs[i].dirty); |
57871462 | 4882 | } |
630b122b | 4883 | else if(stubs[n].d!=TAKEN) { |
4884 | wb_dirtys(branch_regs[i].regmap,branch_regs[i].dirty); | |
57871462 | 4885 | } |
4886 | else { | |
630b122b | 4887 | if(internal_branch(ba[i])) |
4888 | wb_needed_dirtys(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]); | |
57871462 | 4889 | } |
630b122b | 4890 | if(stubs[n].c!=-1) |
57871462 | 4891 | { |
4892 | // Save PC as return address | |
630b122b | 4893 | emit_movimm(stubs[n].c,EAX); |
4894 | emit_writeword(EAX,&pcaddr); | |
57871462 | 4895 | } |
4896 | else | |
4897 | { | |
4898 | // Return address depends on which way the branch goes | |
630b122b | 4899 | if(dops[i].itype==CJUMP||dops[i].itype==SJUMP) |
57871462 | 4900 | { |
630b122b | 4901 | int s1l=get_reg(branch_regs[i].regmap,dops[i].rs1); |
4902 | int s2l=get_reg(branch_regs[i].regmap,dops[i].rs2); | |
4903 | if(dops[i].rs1==0) | |
57871462 | 4904 | { |
630b122b | 4905 | s1l=s2l; |
4906 | s2l=-1; | |
57871462 | 4907 | } |
630b122b | 4908 | else if(dops[i].rs2==0) |
57871462 | 4909 | { |
630b122b | 4910 | s2l=-1; |
57871462 | 4911 | } |
4912 | assert(s1l>=0); | |
4913 | #ifdef DESTRUCTIVE_WRITEBACK | |
630b122b | 4914 | if(dops[i].rs1) { |
4915 | if((branch_regs[i].dirty>>s1l)&&1) | |
4916 | emit_loadreg(dops[i].rs1,s1l); | |
9f51b4b9 | 4917 | } |
57871462 | 4918 | else { |
630b122b | 4919 | if((branch_regs[i].dirty>>s1l)&1) |
4920 | emit_loadreg(dops[i].rs2,s1l); | |
57871462 | 4921 | } |
4922 | if(s2l>=0) | |
630b122b | 4923 | if((branch_regs[i].dirty>>s2l)&1) |
4924 | emit_loadreg(dops[i].rs2,s2l); | |
57871462 | 4925 | #endif |
4926 | int hr=0; | |
5194fb95 | 4927 | int addr=-1,alt=-1,ntaddr=-1; |
57871462 | 4928 | while(hr<HOST_REGS) |
4929 | { | |
4930 | if(hr!=EXCLUDE_REG && hr!=HOST_CCREG && | |
630b122b | 4931 | (branch_regs[i].regmap[hr]&63)!=dops[i].rs1 && |
4932 | (branch_regs[i].regmap[hr]&63)!=dops[i].rs2 ) | |
57871462 | 4933 | { |
4934 | addr=hr++;break; | |
4935 | } | |
4936 | hr++; | |
4937 | } | |
4938 | while(hr<HOST_REGS) | |
4939 | { | |
4940 | if(hr!=EXCLUDE_REG && hr!=HOST_CCREG && | |
630b122b | 4941 | (branch_regs[i].regmap[hr]&63)!=dops[i].rs1 && |
4942 | (branch_regs[i].regmap[hr]&63)!=dops[i].rs2 ) | |
57871462 | 4943 | { |
4944 | alt=hr++;break; | |
4945 | } | |
4946 | hr++; | |
4947 | } | |
630b122b | 4948 | if((dops[i].opcode&0x2E)==6) // BLEZ/BGTZ needs another register |
57871462 | 4949 | { |
4950 | while(hr<HOST_REGS) | |
4951 | { | |
4952 | if(hr!=EXCLUDE_REG && hr!=HOST_CCREG && | |
630b122b | 4953 | (branch_regs[i].regmap[hr]&63)!=dops[i].rs1 && |
4954 | (branch_regs[i].regmap[hr]&63)!=dops[i].rs2 ) | |
57871462 | 4955 | { |
4956 | ntaddr=hr;break; | |
4957 | } | |
4958 | hr++; | |
4959 | } | |
4960 | assert(hr<HOST_REGS); | |
4961 | } | |
630b122b | 4962 | if((dops[i].opcode&0x2f)==4) // BEQ |
57871462 | 4963 | { |
4964 | #ifdef HAVE_CMOV_IMM | |
630b122b | 4965 | if(s2l>=0) emit_cmp(s1l,s2l); |
4966 | else emit_test(s1l,s1l); | |
4967 | emit_cmov2imm_e_ne_compact(ba[i],start+i*4+8,addr); | |
4968 | #else | |
4969 | emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt); | |
4970 | if(s2l>=0) emit_cmp(s1l,s2l); | |
4971 | else emit_test(s1l,s1l); | |
4972 | emit_cmovne_reg(alt,addr); | |
57871462 | 4973 | #endif |
57871462 | 4974 | } |
630b122b | 4975 | if((dops[i].opcode&0x2f)==5) // BNE |
57871462 | 4976 | { |
4977 | #ifdef HAVE_CMOV_IMM | |
630b122b | 4978 | if(s2l>=0) emit_cmp(s1l,s2l); |
4979 | else emit_test(s1l,s1l); | |
4980 | emit_cmov2imm_e_ne_compact(start+i*4+8,ba[i],addr); | |
4981 | #else | |
4982 | emit_mov2imm_compact(start+i*4+8,addr,ba[i],alt); | |
4983 | if(s2l>=0) emit_cmp(s1l,s2l); | |
4984 | else emit_test(s1l,s1l); | |
4985 | emit_cmovne_reg(alt,addr); | |
57871462 | 4986 | #endif |
57871462 | 4987 | } |
630b122b | 4988 | if((dops[i].opcode&0x2f)==6) // BLEZ |
57871462 | 4989 | { |
4990 | //emit_movimm(ba[i],alt); | |
4991 | //emit_movimm(start+i*4+8,addr); | |
4992 | emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr); | |
4993 | emit_cmpimm(s1l,1); | |
57871462 | 4994 | emit_cmovl_reg(alt,addr); |
57871462 | 4995 | } |
630b122b | 4996 | if((dops[i].opcode&0x2f)==7) // BGTZ |
57871462 | 4997 | { |
4998 | //emit_movimm(ba[i],addr); | |
4999 | //emit_movimm(start+i*4+8,ntaddr); | |
5000 | emit_mov2imm_compact(ba[i],addr,start+i*4+8,ntaddr); | |
5001 | emit_cmpimm(s1l,1); | |
57871462 | 5002 | emit_cmovl_reg(ntaddr,addr); |
57871462 | 5003 | } |
630b122b | 5004 | if((dops[i].opcode==1)&&(dops[i].opcode2&0x2D)==0) // BLTZ |
57871462 | 5005 | { |
5006 | //emit_movimm(ba[i],alt); | |
5007 | //emit_movimm(start+i*4+8,addr); | |
5008 | emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr); | |
630b122b | 5009 | emit_test(s1l,s1l); |
57871462 | 5010 | emit_cmovs_reg(alt,addr); |
5011 | } | |
630b122b | 5012 | if((dops[i].opcode==1)&&(dops[i].opcode2&0x2D)==1) // BGEZ |
57871462 | 5013 | { |
5014 | //emit_movimm(ba[i],addr); | |
5015 | //emit_movimm(start+i*4+8,alt); | |
5016 | emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt); | |
630b122b | 5017 | emit_test(s1l,s1l); |
57871462 | 5018 | emit_cmovs_reg(alt,addr); |
5019 | } | |
630b122b | 5020 | if(dops[i].opcode==0x11 && dops[i].opcode2==0x08 ) { |
57871462 | 5021 | if(source[i]&0x10000) // BC1T |
5022 | { | |
5023 | //emit_movimm(ba[i],alt); | |
5024 | //emit_movimm(start+i*4+8,addr); | |
5025 | emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr); | |
5026 | emit_testimm(s1l,0x800000); | |
5027 | emit_cmovne_reg(alt,addr); | |
5028 | } | |
5029 | else // BC1F | |
5030 | { | |
5031 | //emit_movimm(ba[i],addr); | |
5032 | //emit_movimm(start+i*4+8,alt); | |
5033 | emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt); | |
5034 | emit_testimm(s1l,0x800000); | |
5035 | emit_cmovne_reg(alt,addr); | |
5036 | } | |
5037 | } | |
630b122b | 5038 | emit_writeword(addr,&pcaddr); |
57871462 | 5039 | } |
5040 | else | |
630b122b | 5041 | if(dops[i].itype==RJUMP) |
57871462 | 5042 | { |
630b122b | 5043 | int r=get_reg(branch_regs[i].regmap,dops[i].rs1); |
5044 | if (ds_writes_rjump_rs(i)) { | |
57871462 | 5045 | r=get_reg(branch_regs[i].regmap,RTEMP); |
5046 | } | |
630b122b | 5047 | emit_writeword(r,&pcaddr); |
57871462 | 5048 | } |
630b122b | 5049 | else {SysPrintf("Unknown branch type in do_ccstub\n");abort();} |
57871462 | 5050 | } |
5051 | // Update cycle count | |
5052 | assert(branch_regs[i].regmap[HOST_CCREG]==CCREG||branch_regs[i].regmap[HOST_CCREG]==-1); | |
630b122b | 5053 | if(stubs[n].a) emit_addimm(HOST_CCREG,(int)stubs[n].a,HOST_CCREG); |
5054 | emit_far_call(cc_interrupt); | |
5055 | if(stubs[n].a) emit_addimm(HOST_CCREG,-(int)stubs[n].a,HOST_CCREG); | |
5056 | if(stubs[n].d==TAKEN) { | |
5057 | if(internal_branch(ba[i])) | |
57871462 | 5058 | load_needed_regs(branch_regs[i].regmap,regs[(ba[i]-start)>>2].regmap_entry); |
630b122b | 5059 | else if(dops[i].itype==RJUMP) { |
57871462 | 5060 | if(get_reg(branch_regs[i].regmap,RTEMP)>=0) |
630b122b | 5061 | emit_readword(&pcaddr,get_reg(branch_regs[i].regmap,RTEMP)); |
57871462 | 5062 | else |
630b122b | 5063 | emit_loadreg(dops[i].rs1,get_reg(branch_regs[i].regmap,dops[i].rs1)); |
57871462 | 5064 | } |
630b122b | 5065 | }else if(stubs[n].d==NOTTAKEN) { |
57871462 | 5066 | if(i<slen-2) load_needed_regs(branch_regs[i].regmap,regmap_pre[i+2]); |
5067 | else load_all_regs(branch_regs[i].regmap); | |
630b122b | 5068 | }else if(stubs[n].d==NULLDS) { |
57871462 | 5069 | // Delay slot instruction is nullified ("likely" branch) |
5070 | if(i<slen-2) load_needed_regs(regs[i].regmap,regmap_pre[i+2]); | |
5071 | else load_all_regs(regs[i].regmap); | |
5072 | }else{ | |
5073 | load_all_regs(branch_regs[i].regmap); | |
5074 | } | |
630b122b | 5075 | if (stubs[n].retaddr) |
5076 | emit_jmp(stubs[n].retaddr); | |
5077 | else | |
5078 | do_jump_vaddr(stubs[n].e); | |
5079 | } | |
5080 | ||
5081 | static void add_to_linker(void *addr, u_int target, int ext) | |
5082 | { | |
5083 | assert(linkcount < ARRAY_SIZE(link_addr)); | |
5084 | link_addr[linkcount].addr = addr; | |
5085 | link_addr[linkcount].target = target; | |
5086 | link_addr[linkcount].ext = ext; | |
57871462 | 5087 | linkcount++; |
5088 | } | |
5089 | ||
eba830cd | 5090 | static void ujump_assemble_write_ra(int i) |
5091 | { | |
5092 | int rt; | |
5093 | unsigned int return_address; | |
5094 | rt=get_reg(branch_regs[i].regmap,31); | |
5095 | assem_debug("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]); | |
5096 | //assert(rt>=0); | |
5097 | return_address=start+i*4+8; | |
5098 | if(rt>=0) { | |
5099 | #ifdef USE_MINI_HT | |
630b122b | 5100 | if(internal_branch(return_address)&&dops[i+1].rt1!=31) { |
eba830cd | 5101 | int temp=-1; // note: must be ds-safe |
5102 | #ifdef HOST_TEMPREG | |
5103 | temp=HOST_TEMPREG; | |
5104 | #endif | |
5105 | if(temp>=0) do_miniht_insert(return_address,rt,temp); | |
5106 | else emit_movimm(return_address,rt); | |
5107 | } | |
5108 | else | |
5109 | #endif | |
5110 | { | |
5111 | #ifdef REG_PREFETCH | |
9f51b4b9 | 5112 | if(temp>=0) |
eba830cd | 5113 | { |
630b122b | 5114 | if(i_regmap[temp]!=PTEMP) emit_movimm((uintptr_t)hash_table_get(return_address),temp); |
eba830cd | 5115 | } |
5116 | #endif | |
5117 | emit_movimm(return_address,rt); // PC into link register | |
5118 | #ifdef IMM_PREFETCH | |
630b122b | 5119 | emit_prefetch(hash_table_get(return_address)); |
eba830cd | 5120 | #endif |
5121 | } | |
5122 | } | |
5123 | } | |
5124 | ||
630b122b | 5125 | static void ujump_assemble(int i, const struct regstat *i_regs) |
57871462 | 5126 | { |
eba830cd | 5127 | int ra_done=0; |
57871462 | 5128 | if(i==(ba[i]-start)>>2) assem_debug("idle loop\n"); |
5129 | address_generation(i+1,i_regs,regs[i].regmap_entry); | |
5130 | #ifdef REG_PREFETCH | |
5131 | int temp=get_reg(branch_regs[i].regmap,PTEMP); | |
630b122b | 5132 | if(dops[i].rt1==31&&temp>=0) |
57871462 | 5133 | { |
581335b0 | 5134 | signed char *i_regmap=i_regs->regmap; |
57871462 | 5135 | int return_address=start+i*4+8; |
9f51b4b9 | 5136 | if(get_reg(branch_regs[i].regmap,31)>0) |
630b122b | 5137 | if(i_regmap[temp]==PTEMP) emit_movimm((uintptr_t)hash_table_get(return_address),temp); |
57871462 | 5138 | } |
5139 | #endif | |
630b122b | 5140 | if(dops[i].rt1==31&&(dops[i].rt1==dops[i+1].rs1||dops[i].rt1==dops[i+1].rs2)) { |
eba830cd | 5141 | ujump_assemble_write_ra(i); // writeback ra for DS |
5142 | ra_done=1; | |
57871462 | 5143 | } |
4ef8f67d | 5144 | ds_assemble(i+1,i_regs); |
5145 | uint64_t bc_unneeded=branch_regs[i].u; | |
630b122b | 5146 | bc_unneeded|=1|(1LL<<dops[i].rt1); |
5147 | wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,bc_unneeded); | |
5148 | load_regs(regs[i].regmap,branch_regs[i].regmap,CCREG,CCREG); | |
5149 | if(!ra_done&&dops[i].rt1==31) | |
eba830cd | 5150 | ujump_assemble_write_ra(i); |
57871462 | 5151 | int cc,adj; |
5152 | cc=get_reg(branch_regs[i].regmap,CCREG); | |
5153 | assert(cc==HOST_CCREG); | |
630b122b | 5154 | store_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]); |
57871462 | 5155 | #ifdef REG_PREFETCH |
630b122b | 5156 | if(dops[i].rt1==31&&temp>=0) emit_prefetchreg(temp); |
57871462 | 5157 | #endif |
5158 | do_cc(i,branch_regs[i].regmap,&adj,ba[i],TAKEN,0); | |
630b122b | 5159 | if(adj) emit_addimm(cc, ccadj[i] + CLOCK_ADJUST(2) - adj, cc); |
5160 | load_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]); | |
5161 | if(internal_branch(ba[i])) | |
57871462 | 5162 | assem_debug("branch: internal\n"); |
5163 | else | |
5164 | assem_debug("branch: external\n"); | |
630b122b | 5165 | if (internal_branch(ba[i]) && dops[(ba[i]-start)>>2].is_ds) { |
57871462 | 5166 | ds_assemble_entry(i); |
5167 | } | |
5168 | else { | |
630b122b | 5169 | add_to_linker(out,ba[i],internal_branch(ba[i])); |
57871462 | 5170 | emit_jmp(0); |
5171 | } | |
5172 | } | |
5173 | ||
eba830cd | 5174 | static void rjump_assemble_write_ra(int i) |
5175 | { | |
5176 | int rt,return_address; | |
630b122b | 5177 | assert(dops[i+1].rt1!=dops[i].rt1); |
5178 | assert(dops[i+1].rt2!=dops[i].rt1); | |
5179 | rt=get_reg(branch_regs[i].regmap,dops[i].rt1); | |
eba830cd | 5180 | assem_debug("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]); |
5181 | assert(rt>=0); | |
5182 | return_address=start+i*4+8; | |
5183 | #ifdef REG_PREFETCH | |
9f51b4b9 | 5184 | if(temp>=0) |
eba830cd | 5185 | { |
630b122b | 5186 | if(i_regmap[temp]!=PTEMP) emit_movimm((uintptr_t)hash_table_get(return_address),temp); |
eba830cd | 5187 | } |
5188 | #endif | |
5189 | emit_movimm(return_address,rt); // PC into link register | |
5190 | #ifdef IMM_PREFETCH | |
630b122b | 5191 | emit_prefetch(hash_table_get(return_address)); |
eba830cd | 5192 | #endif |
5193 | } | |
5194 | ||
630b122b | 5195 | static void rjump_assemble(int i, const struct regstat *i_regs) |
57871462 | 5196 | { |
57871462 | 5197 | int temp; |
581335b0 | 5198 | int rs,cc; |
eba830cd | 5199 | int ra_done=0; |
630b122b | 5200 | rs=get_reg(branch_regs[i].regmap,dops[i].rs1); |
57871462 | 5201 | assert(rs>=0); |
630b122b | 5202 | if (ds_writes_rjump_rs(i)) { |
57871462 | 5203 | // Delay slot abuse, make a copy of the branch address register |
5204 | temp=get_reg(branch_regs[i].regmap,RTEMP); | |
5205 | assert(temp>=0); | |
5206 | assert(regs[i].regmap[temp]==RTEMP); | |
5207 | emit_mov(rs,temp); | |
5208 | rs=temp; | |
5209 | } | |
5210 | address_generation(i+1,i_regs,regs[i].regmap_entry); | |
5211 | #ifdef REG_PREFETCH | |
630b122b | 5212 | if(dops[i].rt1==31) |
57871462 | 5213 | { |
5214 | if((temp=get_reg(branch_regs[i].regmap,PTEMP))>=0) { | |
581335b0 | 5215 | signed char *i_regmap=i_regs->regmap; |
57871462 | 5216 | int return_address=start+i*4+8; |
630b122b | 5217 | if(i_regmap[temp]==PTEMP) emit_movimm((uintptr_t)hash_table_get(return_address),temp); |
57871462 | 5218 | } |
5219 | } | |
5220 | #endif | |
5221 | #ifdef USE_MINI_HT | |
630b122b | 5222 | if(dops[i].rs1==31) { |
57871462 | 5223 | int rh=get_reg(regs[i].regmap,RHASH); |
5224 | if(rh>=0) do_preload_rhash(rh); | |
5225 | } | |
5226 | #endif | |
630b122b | 5227 | if(dops[i].rt1!=0&&(dops[i].rt1==dops[i+1].rs1||dops[i].rt1==dops[i+1].rs2)) { |
eba830cd | 5228 | rjump_assemble_write_ra(i); |
5229 | ra_done=1; | |
57871462 | 5230 | } |
d5910d5d | 5231 | ds_assemble(i+1,i_regs); |
5232 | uint64_t bc_unneeded=branch_regs[i].u; | |
630b122b | 5233 | bc_unneeded|=1|(1LL<<dops[i].rt1); |
5234 | bc_unneeded&=~(1LL<<dops[i].rs1); | |
5235 | wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,bc_unneeded); | |
5236 | load_regs(regs[i].regmap,branch_regs[i].regmap,dops[i].rs1,CCREG); | |
5237 | if(!ra_done&&dops[i].rt1!=0) | |
eba830cd | 5238 | rjump_assemble_write_ra(i); |
57871462 | 5239 | cc=get_reg(branch_regs[i].regmap,CCREG); |
5240 | assert(cc==HOST_CCREG); | |
581335b0 | 5241 | (void)cc; |
57871462 | 5242 | #ifdef USE_MINI_HT |
5243 | int rh=get_reg(branch_regs[i].regmap,RHASH); | |
5244 | int ht=get_reg(branch_regs[i].regmap,RHTBL); | |
630b122b | 5245 | if(dops[i].rs1==31) { |
57871462 | 5246 | if(regs[i].regmap[rh]!=RHASH) do_preload_rhash(rh); |
5247 | do_preload_rhtbl(ht); | |
5248 | do_rhash(rs,rh); | |
5249 | } | |
5250 | #endif | |
630b122b | 5251 | store_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,-1); |
57871462 | 5252 | #ifdef DESTRUCTIVE_WRITEBACK |
630b122b | 5253 | if((branch_regs[i].dirty>>rs)&1) { |
5254 | if(dops[i].rs1!=dops[i+1].rt1&&dops[i].rs1!=dops[i+1].rt2) { | |
5255 | emit_loadreg(dops[i].rs1,rs); | |
57871462 | 5256 | } |
5257 | } | |
5258 | #endif | |
5259 | #ifdef REG_PREFETCH | |
630b122b | 5260 | if(dops[i].rt1==31&&temp>=0) emit_prefetchreg(temp); |
57871462 | 5261 | #endif |
5262 | #ifdef USE_MINI_HT | |
630b122b | 5263 | if(dops[i].rs1==31) { |
57871462 | 5264 | do_miniht_load(ht,rh); |
5265 | } | |
5266 | #endif | |
5267 | //do_cc(i,branch_regs[i].regmap,&adj,-1,TAKEN); | |
5268 | //if(adj) emit_addimm(cc,2*(ccadj[i]+2-adj),cc); // ??? - Shouldn't happen | |
5269 | //assert(adj==0); | |
630b122b | 5270 | emit_addimm_and_set_flags(ccadj[i] + CLOCK_ADJUST(2), HOST_CCREG); |
5271 | add_stub(CC_STUB,out,NULL,0,i,-1,TAKEN,rs); | |
5272 | if(dops[i+1].itype==COP0&&(source[i+1]&0x3f)==0x10) | |
911f2d55 | 5273 | // special case for RFE |
5274 | emit_jmp(0); | |
5275 | else | |
71e490c5 | 5276 | emit_jns(0); |
630b122b | 5277 | //load_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,-1); |
57871462 | 5278 | #ifdef USE_MINI_HT |
630b122b | 5279 | if(dops[i].rs1==31) { |
57871462 | 5280 | do_miniht_jump(rs,rh,ht); |
5281 | } | |
5282 | else | |
5283 | #endif | |
5284 | { | |
630b122b | 5285 | do_jump_vaddr(rs); |
5286 | } | |
57871462 | 5287 | #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK |
630b122b | 5288 | if(dops[i].rt1!=31&&i<slen-2&&(((u_int)out)&7)) emit_mov(13,13); |
57871462 | 5289 | #endif |
5290 | } | |
5291 | ||
630b122b | 5292 | static void cjump_assemble(int i, const struct regstat *i_regs) |
57871462 | 5293 | { |
630b122b | 5294 | const signed char *i_regmap = i_regs->regmap; |
57871462 | 5295 | int cc; |
5296 | int match; | |
630b122b | 5297 | match=match_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]); |
57871462 | 5298 | assem_debug("match=%d\n",match); |
630b122b | 5299 | int s1l,s2l; |
57871462 | 5300 | int unconditional=0,nop=0; |
57871462 | 5301 | int invert=0; |
630b122b | 5302 | int internal=internal_branch(ba[i]); |
57871462 | 5303 | if(i==(ba[i]-start)>>2) assem_debug("idle loop\n"); |
57871462 | 5304 | if(!match) invert=1; |
5305 | #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK | |
5306 | if(i>(ba[i]-start)>>2) invert=1; | |
5307 | #endif | |
630b122b | 5308 | #ifdef __aarch64__ |
5309 | invert=1; // because of near cond. branches | |
5310 | #endif | |
9f51b4b9 | 5311 | |
630b122b | 5312 | if(dops[i].ooo) { |
5313 | s1l=get_reg(branch_regs[i].regmap,dops[i].rs1); | |
5314 | s2l=get_reg(branch_regs[i].regmap,dops[i].rs2); | |
57871462 | 5315 | } |
5316 | else { | |
630b122b | 5317 | s1l=get_reg(i_regmap,dops[i].rs1); |
5318 | s2l=get_reg(i_regmap,dops[i].rs2); | |
57871462 | 5319 | } |
630b122b | 5320 | if(dops[i].rs1==0&&dops[i].rs2==0) |
57871462 | 5321 | { |
630b122b | 5322 | if(dops[i].opcode&1) nop=1; |
57871462 | 5323 | else unconditional=1; |
630b122b | 5324 | //assert(dops[i].opcode!=5); |
5325 | //assert(dops[i].opcode!=7); | |
5326 | //assert(dops[i].opcode!=0x15); | |
5327 | //assert(dops[i].opcode!=0x17); | |
57871462 | 5328 | } |
630b122b | 5329 | else if(dops[i].rs1==0) |
57871462 | 5330 | { |
630b122b | 5331 | s1l=s2l; |
5332 | s2l=-1; | |
57871462 | 5333 | } |
630b122b | 5334 | else if(dops[i].rs2==0) |
57871462 | 5335 | { |
630b122b | 5336 | s2l=-1; |
57871462 | 5337 | } |
5338 | ||
630b122b | 5339 | if(dops[i].ooo) { |
57871462 | 5340 | // Out of order execution (delay slot first) |
5341 | //printf("OOOE\n"); | |
5342 | address_generation(i+1,i_regs,regs[i].regmap_entry); | |
5343 | ds_assemble(i+1,i_regs); | |
5344 | int adj; | |
5345 | uint64_t bc_unneeded=branch_regs[i].u; | |
630b122b | 5346 | bc_unneeded&=~((1LL<<dops[i].rs1)|(1LL<<dops[i].rs2)); |
57871462 | 5347 | bc_unneeded|=1; |
630b122b | 5348 | wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,bc_unneeded); |
5349 | load_regs(regs[i].regmap,branch_regs[i].regmap,dops[i].rs1,dops[i].rs2); | |
5350 | load_regs(regs[i].regmap,branch_regs[i].regmap,CCREG,CCREG); | |
57871462 | 5351 | cc=get_reg(branch_regs[i].regmap,CCREG); |
5352 | assert(cc==HOST_CCREG); | |
9f51b4b9 | 5353 | if(unconditional) |
630b122b | 5354 | store_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]); |
57871462 | 5355 | //do_cc(i,branch_regs[i].regmap,&adj,unconditional?ba[i]:-1,unconditional); |
5356 | //assem_debug("cycle count (adj)\n"); | |
5357 | if(unconditional) { | |
5358 | do_cc(i,branch_regs[i].regmap,&adj,ba[i],TAKEN,0); | |
5359 | if(i!=(ba[i]-start)>>2 || source[i+1]!=0) { | |
630b122b | 5360 | if(adj) emit_addimm(cc, ccadj[i] + CLOCK_ADJUST(2) - adj, cc); |
5361 | load_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]); | |
57871462 | 5362 | if(internal) |
5363 | assem_debug("branch: internal\n"); | |
5364 | else | |
5365 | assem_debug("branch: external\n"); | |
630b122b | 5366 | if (internal && dops[(ba[i]-start)>>2].is_ds) { |
57871462 | 5367 | ds_assemble_entry(i); |
5368 | } | |
5369 | else { | |
630b122b | 5370 | add_to_linker(out,ba[i],internal); |
57871462 | 5371 | emit_jmp(0); |
5372 | } | |
5373 | #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK | |
5374 | if(((u_int)out)&7) emit_addnop(0); | |
5375 | #endif | |
5376 | } | |
5377 | } | |
5378 | else if(nop) { | |
630b122b | 5379 | emit_addimm_and_set_flags(ccadj[i] + CLOCK_ADJUST(2), cc); |
5380 | void *jaddr=out; | |
57871462 | 5381 | emit_jns(0); |
630b122b | 5382 | add_stub(CC_STUB,jaddr,out,0,i,start+i*4+8,NOTTAKEN,0); |
57871462 | 5383 | } |
5384 | else { | |
630b122b | 5385 | void *taken = NULL, *nottaken = NULL, *nottaken1 = NULL; |
57871462 | 5386 | do_cc(i,branch_regs[i].regmap,&adj,-1,0,invert); |
630b122b | 5387 | if(adj&&!invert) emit_addimm(cc, ccadj[i] + CLOCK_ADJUST(2) - adj, cc); |
9f51b4b9 | 5388 | |
57871462 | 5389 | //printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]); |
5390 | assert(s1l>=0); | |
630b122b | 5391 | if(dops[i].opcode==4) // BEQ |
57871462 | 5392 | { |
5393 | if(s2l>=0) emit_cmp(s1l,s2l); | |
5394 | else emit_test(s1l,s1l); | |
5395 | if(invert){ | |
630b122b | 5396 | nottaken=out; |
5397 | emit_jne(DJT_1); | |
57871462 | 5398 | }else{ |
630b122b | 5399 | add_to_linker(out,ba[i],internal); |
57871462 | 5400 | emit_jeq(0); |
5401 | } | |
5402 | } | |
630b122b | 5403 | if(dops[i].opcode==5) // BNE |
57871462 | 5404 | { |
5405 | if(s2l>=0) emit_cmp(s1l,s2l); | |
5406 | else emit_test(s1l,s1l); | |
5407 | if(invert){ | |
630b122b | 5408 | nottaken=out; |
5409 | emit_jeq(DJT_1); | |
57871462 | 5410 | }else{ |
630b122b | 5411 | add_to_linker(out,ba[i],internal); |
57871462 | 5412 | emit_jne(0); |
5413 | } | |
5414 | } | |
630b122b | 5415 | if(dops[i].opcode==6) // BLEZ |
57871462 | 5416 | { |
5417 | emit_cmpimm(s1l,1); | |
5418 | if(invert){ | |
630b122b | 5419 | nottaken=out; |
5420 | emit_jge(DJT_1); | |
57871462 | 5421 | }else{ |
630b122b | 5422 | add_to_linker(out,ba[i],internal); |
57871462 | 5423 | emit_jl(0); |
5424 | } | |
5425 | } | |
630b122b | 5426 | if(dops[i].opcode==7) // BGTZ |
57871462 | 5427 | { |
5428 | emit_cmpimm(s1l,1); | |
5429 | if(invert){ | |
630b122b | 5430 | nottaken=out; |
5431 | emit_jl(DJT_1); | |
57871462 | 5432 | }else{ |
630b122b | 5433 | add_to_linker(out,ba[i],internal); |
57871462 | 5434 | emit_jge(0); |
5435 | } | |
5436 | } | |
5437 | if(invert) { | |
630b122b | 5438 | if(taken) set_jump_target(taken, out); |
57871462 | 5439 | #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK |
630b122b | 5440 | if (match && (!internal || !dops[(ba[i]-start)>>2].is_ds)) { |
57871462 | 5441 | if(adj) { |
630b122b | 5442 | emit_addimm(cc,-adj,cc); |
5443 | add_to_linker(out,ba[i],internal); | |
57871462 | 5444 | }else{ |
5445 | emit_addnop(13); | |
630b122b | 5446 | add_to_linker(out,ba[i],internal*2); |
57871462 | 5447 | } |
5448 | emit_jmp(0); | |
5449 | }else | |
5450 | #endif | |
5451 | { | |
630b122b | 5452 | if(adj) emit_addimm(cc,-adj,cc); |
5453 | store_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]); | |
5454 | load_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]); | |
57871462 | 5455 | if(internal) |
5456 | assem_debug("branch: internal\n"); | |
5457 | else | |
5458 | assem_debug("branch: external\n"); | |
630b122b | 5459 | if (internal && dops[(ba[i] - start) >> 2].is_ds) { |
57871462 | 5460 | ds_assemble_entry(i); |
5461 | } | |
5462 | else { | |
630b122b | 5463 | add_to_linker(out,ba[i],internal); |
57871462 | 5464 | emit_jmp(0); |
5465 | } | |
5466 | } | |
630b122b | 5467 | set_jump_target(nottaken, out); |
57871462 | 5468 | } |
5469 | ||
630b122b | 5470 | if(nottaken1) set_jump_target(nottaken1, out); |
57871462 | 5471 | if(adj) { |
630b122b | 5472 | if(!invert) emit_addimm(cc,adj,cc); |
57871462 | 5473 | } |
5474 | } // (!unconditional) | |
5475 | } // if(ooo) | |
5476 | else | |
5477 | { | |
5478 | // In-order execution (branch first) | |
630b122b | 5479 | void *taken = NULL, *nottaken = NULL, *nottaken1 = NULL; |
57871462 | 5480 | if(!unconditional&&!nop) { |
57871462 | 5481 | //printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]); |
5482 | assert(s1l>=0); | |
630b122b | 5483 | if((dops[i].opcode&0x2f)==4) // BEQ |
57871462 | 5484 | { |
5485 | if(s2l>=0) emit_cmp(s1l,s2l); | |
5486 | else emit_test(s1l,s1l); | |
630b122b | 5487 | nottaken=out; |
5488 | emit_jne(DJT_2); | |
57871462 | 5489 | } |
630b122b | 5490 | if((dops[i].opcode&0x2f)==5) // BNE |
57871462 | 5491 | { |
5492 | if(s2l>=0) emit_cmp(s1l,s2l); | |
5493 | else emit_test(s1l,s1l); | |
630b122b | 5494 | nottaken=out; |
5495 | emit_jeq(DJT_2); | |
57871462 | 5496 | } |
630b122b | 5497 | if((dops[i].opcode&0x2f)==6) // BLEZ |
57871462 | 5498 | { |
5499 | emit_cmpimm(s1l,1); | |
630b122b | 5500 | nottaken=out; |
5501 | emit_jge(DJT_2); | |
57871462 | 5502 | } |
630b122b | 5503 | if((dops[i].opcode&0x2f)==7) // BGTZ |
57871462 | 5504 | { |
5505 | emit_cmpimm(s1l,1); | |
630b122b | 5506 | nottaken=out; |
5507 | emit_jl(DJT_2); | |
57871462 | 5508 | } |
5509 | } // if(!unconditional) | |
5510 | int adj; | |
5511 | uint64_t ds_unneeded=branch_regs[i].u; | |
630b122b | 5512 | ds_unneeded&=~((1LL<<dops[i+1].rs1)|(1LL<<dops[i+1].rs2)); |
57871462 | 5513 | ds_unneeded|=1; |
57871462 | 5514 | // branch taken |
5515 | if(!nop) { | |
630b122b | 5516 | if(taken) set_jump_target(taken, out); |
57871462 | 5517 | assem_debug("1:\n"); |
630b122b | 5518 | wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,ds_unneeded); |
57871462 | 5519 | // load regs |
630b122b | 5520 | load_regs(regs[i].regmap,branch_regs[i].regmap,dops[i+1].rs1,dops[i+1].rs2); |
57871462 | 5521 | address_generation(i+1,&branch_regs[i],0); |
630b122b | 5522 | if (ram_offset) |
5523 | load_regs(regs[i].regmap,branch_regs[i].regmap,ROREG,ROREG); | |
5524 | load_regs(regs[i].regmap,branch_regs[i].regmap,CCREG,INVCP); | |
57871462 | 5525 | ds_assemble(i+1,&branch_regs[i]); |
5526 | cc=get_reg(branch_regs[i].regmap,CCREG); | |
5527 | if(cc==-1) { | |
5528 | emit_loadreg(CCREG,cc=HOST_CCREG); | |
5529 | // CHECK: Is the following instruction (fall thru) allocated ok? | |
5530 | } | |
5531 | assert(cc==HOST_CCREG); | |
630b122b | 5532 | store_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]); |
57871462 | 5533 | do_cc(i,i_regmap,&adj,ba[i],TAKEN,0); |
5534 | assem_debug("cycle count (adj)\n"); | |
630b122b | 5535 | if(adj) emit_addimm(cc, ccadj[i] + CLOCK_ADJUST(2) - adj, cc); |
5536 | load_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]); | |
57871462 | 5537 | if(internal) |
5538 | assem_debug("branch: internal\n"); | |
5539 | else | |
5540 | assem_debug("branch: external\n"); | |
630b122b | 5541 | if (internal && dops[(ba[i] - start) >> 2].is_ds) { |
57871462 | 5542 | ds_assemble_entry(i); |
5543 | } | |
5544 | else { | |
630b122b | 5545 | add_to_linker(out,ba[i],internal); |
57871462 | 5546 | emit_jmp(0); |
5547 | } | |
5548 | } | |
5549 | // branch not taken | |
57871462 | 5550 | if(!unconditional) { |
630b122b | 5551 | if(nottaken1) set_jump_target(nottaken1, out); |
5552 | set_jump_target(nottaken, out); | |
57871462 | 5553 | assem_debug("2:\n"); |
630b122b | 5554 | wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,ds_unneeded); |
5555 | // load regs | |
5556 | load_regs(regs[i].regmap,branch_regs[i].regmap,dops[i+1].rs1,dops[i+1].rs2); | |
5557 | address_generation(i+1,&branch_regs[i],0); | |
5558 | if (ram_offset) | |
5559 | load_regs(regs[i].regmap,branch_regs[i].regmap,ROREG,ROREG); | |
5560 | load_regs(regs[i].regmap,branch_regs[i].regmap,CCREG,INVCP); | |
5561 | ds_assemble(i+1,&branch_regs[i]); | |
57871462 | 5562 | cc=get_reg(branch_regs[i].regmap,CCREG); |
630b122b | 5563 | if (cc == -1) { |
57871462 | 5564 | // Cycle count isn't in a register, temporarily load it then write it out |
5565 | emit_loadreg(CCREG,HOST_CCREG); | |
630b122b | 5566 | emit_addimm_and_set_flags(ccadj[i] + CLOCK_ADJUST(2), HOST_CCREG); |
5567 | void *jaddr=out; | |
57871462 | 5568 | emit_jns(0); |
630b122b | 5569 | add_stub(CC_STUB,jaddr,out,0,i,start+i*4+8,NOTTAKEN,0); |
57871462 | 5570 | emit_storereg(CCREG,HOST_CCREG); |
5571 | } | |
5572 | else{ | |
5573 | cc=get_reg(i_regmap,CCREG); | |
5574 | assert(cc==HOST_CCREG); | |
630b122b | 5575 | emit_addimm_and_set_flags(ccadj[i] + CLOCK_ADJUST(2), cc); |
5576 | void *jaddr=out; | |
57871462 | 5577 | emit_jns(0); |
630b122b | 5578 | add_stub(CC_STUB,jaddr,out,0,i,start+i*4+8,NOTTAKEN,0); |
57871462 | 5579 | } |
5580 | } | |
5581 | } | |
5582 | } | |
5583 | ||
630b122b | 5584 | static void sjump_assemble(int i, const struct regstat *i_regs) |
57871462 | 5585 | { |
630b122b | 5586 | const signed char *i_regmap = i_regs->regmap; |
57871462 | 5587 | int cc; |
5588 | int match; | |
630b122b | 5589 | match=match_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]); |
57871462 | 5590 | assem_debug("smatch=%d\n",match); |
630b122b | 5591 | int s1l; |
57871462 | 5592 | int unconditional=0,nevertaken=0; |
57871462 | 5593 | int invert=0; |
630b122b | 5594 | int internal=internal_branch(ba[i]); |
57871462 | 5595 | if(i==(ba[i]-start)>>2) assem_debug("idle loop\n"); |
57871462 | 5596 | if(!match) invert=1; |
5597 | #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK | |
5598 | if(i>(ba[i]-start)>>2) invert=1; | |
5599 | #endif | |
630b122b | 5600 | #ifdef __aarch64__ |
5601 | invert=1; // because of near cond. branches | |
5602 | #endif | |
57871462 | 5603 | |
630b122b | 5604 | //if(dops[i].opcode2>=0x10) return; // FIXME (BxxZAL) |
5605 | //assert(dops[i].opcode2<0x10||dops[i].rs1==0); // FIXME (BxxZAL) | |
57871462 | 5606 | |
630b122b | 5607 | if(dops[i].ooo) { |
5608 | s1l=get_reg(branch_regs[i].regmap,dops[i].rs1); | |
57871462 | 5609 | } |
5610 | else { | |
630b122b | 5611 | s1l=get_reg(i_regmap,dops[i].rs1); |
57871462 | 5612 | } |
630b122b | 5613 | if(dops[i].rs1==0) |
57871462 | 5614 | { |
630b122b | 5615 | if(dops[i].opcode2&1) unconditional=1; |
57871462 | 5616 | else nevertaken=1; |
5617 | // These are never taken (r0 is never less than zero) | |
630b122b | 5618 | //assert(dops[i].opcode2!=0); |
5619 | //assert(dops[i].opcode2!=2); | |
5620 | //assert(dops[i].opcode2!=0x10); | |
5621 | //assert(dops[i].opcode2!=0x12); | |
57871462 | 5622 | } |
5623 | ||
630b122b | 5624 | if(dops[i].ooo) { |
57871462 | 5625 | // Out of order execution (delay slot first) |
5626 | //printf("OOOE\n"); | |
5627 | address_generation(i+1,i_regs,regs[i].regmap_entry); | |
5628 | ds_assemble(i+1,i_regs); | |
5629 | int adj; | |
5630 | uint64_t bc_unneeded=branch_regs[i].u; | |
630b122b | 5631 | bc_unneeded&=~((1LL<<dops[i].rs1)|(1LL<<dops[i].rs2)); |
57871462 | 5632 | bc_unneeded|=1; |
630b122b | 5633 | wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,bc_unneeded); |
5634 | load_regs(regs[i].regmap,branch_regs[i].regmap,dops[i].rs1,dops[i].rs1); | |
5635 | load_regs(regs[i].regmap,branch_regs[i].regmap,CCREG,CCREG); | |
5636 | if(dops[i].rt1==31) { | |
57871462 | 5637 | int rt,return_address; |
57871462 | 5638 | rt=get_reg(branch_regs[i].regmap,31); |
5639 | assem_debug("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]); | |
5640 | if(rt>=0) { | |
5641 | // Save the PC even if the branch is not taken | |
5642 | return_address=start+i*4+8; | |
5643 | emit_movimm(return_address,rt); // PC into link register | |
5644 | #ifdef IMM_PREFETCH | |
630b122b | 5645 | if(!nevertaken) emit_prefetch(hash_table_get(return_address)); |
57871462 | 5646 | #endif |
5647 | } | |
5648 | } | |
5649 | cc=get_reg(branch_regs[i].regmap,CCREG); | |
5650 | assert(cc==HOST_CCREG); | |
9f51b4b9 | 5651 | if(unconditional) |
630b122b | 5652 | store_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]); |
57871462 | 5653 | //do_cc(i,branch_regs[i].regmap,&adj,unconditional?ba[i]:-1,unconditional); |
5654 | assem_debug("cycle count (adj)\n"); | |
5655 | if(unconditional) { | |
5656 | do_cc(i,branch_regs[i].regmap,&adj,ba[i],TAKEN,0); | |
5657 | if(i!=(ba[i]-start)>>2 || source[i+1]!=0) { | |
630b122b | 5658 | if(adj) emit_addimm(cc, ccadj[i] + CLOCK_ADJUST(2) - adj, cc); |
5659 | load_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]); | |
57871462 | 5660 | if(internal) |
5661 | assem_debug("branch: internal\n"); | |
5662 | else | |
5663 | assem_debug("branch: external\n"); | |
630b122b | 5664 | if (internal && dops[(ba[i] - start) >> 2].is_ds) { |
57871462 | 5665 | ds_assemble_entry(i); |
5666 | } | |
5667 | else { | |
630b122b | 5668 | add_to_linker(out,ba[i],internal); |
57871462 | 5669 | emit_jmp(0); |
5670 | } | |
5671 | #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK | |
5672 | if(((u_int)out)&7) emit_addnop(0); | |
5673 | #endif | |
5674 | } | |
5675 | } | |
5676 | else if(nevertaken) { | |
630b122b | 5677 | emit_addimm_and_set_flags(ccadj[i] + CLOCK_ADJUST(2), cc); |
5678 | void *jaddr=out; | |
57871462 | 5679 | emit_jns(0); |
630b122b | 5680 | add_stub(CC_STUB,jaddr,out,0,i,start+i*4+8,NOTTAKEN,0); |
57871462 | 5681 | } |
5682 | else { | |
630b122b | 5683 | void *nottaken = NULL; |
57871462 | 5684 | do_cc(i,branch_regs[i].regmap,&adj,-1,0,invert); |
630b122b | 5685 | if(adj&&!invert) emit_addimm(cc, ccadj[i] + CLOCK_ADJUST(2) - adj, cc); |
57871462 | 5686 | { |
5687 | assert(s1l>=0); | |
630b122b | 5688 | if((dops[i].opcode2&0xf)==0) // BLTZ/BLTZAL |
57871462 | 5689 | { |
5690 | emit_test(s1l,s1l); | |
5691 | if(invert){ | |
630b122b | 5692 | nottaken=out; |
5693 | emit_jns(DJT_1); | |
57871462 | 5694 | }else{ |
630b122b | 5695 | add_to_linker(out,ba[i],internal); |
57871462 | 5696 | emit_js(0); |
5697 | } | |
5698 | } | |
630b122b | 5699 | if((dops[i].opcode2&0xf)==1) // BGEZ/BLTZAL |
57871462 | 5700 | { |
5701 | emit_test(s1l,s1l); | |
5702 | if(invert){ | |
630b122b | 5703 | nottaken=out; |
5704 | emit_js(DJT_1); | |
57871462 | 5705 | }else{ |
630b122b | 5706 | add_to_linker(out,ba[i],internal); |
57871462 | 5707 | emit_jns(0); |
5708 | } | |
5709 | } | |
57871462 | 5710 | } |
9f51b4b9 | 5711 | |
57871462 | 5712 | if(invert) { |
57871462 | 5713 | #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK |
630b122b | 5714 | if (match && (!internal || !dops[(ba[i] - start) >> 2].is_ds)) { |
5715 | if(adj) { | |
5716 | emit_addimm(cc,-adj,cc); | |
5717 | add_to_linker(out,ba[i],internal); | |
5718 | }else{ | |
5719 | emit_addnop(13); | |
5720 | add_to_linker(out,ba[i],internal*2); | |
5721 | } | |
57871462 | 5722 | emit_jmp(0); |
630b122b | 5723 | }else |
5724 | #endif | |
5725 | { | |
5726 | if(adj) emit_addimm(cc,-adj,cc); | |
5727 | store_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]); | |
5728 | load_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]); | |
5729 | if(internal) | |
5730 | assem_debug("branch: internal\n"); | |
5731 | else | |
5732 | assem_debug("branch: external\n"); | |
5733 | if (internal && dops[(ba[i] - start) >> 2].is_ds) { | |
5734 | ds_assemble_entry(i); | |
5735 | } | |
5736 | else { | |
5737 | add_to_linker(out,ba[i],internal); | |
5738 | emit_jmp(0); | |
5739 | } | |
57871462 | 5740 | } |
630b122b | 5741 | set_jump_target(nottaken, out); |
57871462 | 5742 | } |
5743 | ||
5744 | if(adj) { | |
630b122b | 5745 | if(!invert) emit_addimm(cc,adj,cc); |
57871462 | 5746 | } |
5747 | } // (!unconditional) | |
5748 | } // if(ooo) | |
5749 | else | |
5750 | { | |
5751 | // In-order execution (branch first) | |
5752 | //printf("IOE\n"); | |
630b122b | 5753 | void *nottaken = NULL; |
5754 | if(dops[i].rt1==31) { | |
5755 | int rt,return_address; | |
5756 | rt=get_reg(branch_regs[i].regmap,31); | |
5757 | if(rt>=0) { | |
5758 | // Save the PC even if the branch is not taken | |
5759 | return_address=start+i*4+8; | |
5760 | emit_movimm(return_address,rt); // PC into link register | |
5761 | #ifdef IMM_PREFETCH | |
5762 | emit_prefetch(hash_table_get(return_address)); | |
5763 | #endif | |
5764 | } | |
5765 | } | |
5766 | if(!unconditional) { | |
57871462 | 5767 | //printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]); |
630b122b | 5768 | assert(s1l>=0); |
5769 | if((dops[i].opcode2&0x0d)==0) // BLTZ/BLTZL/BLTZAL/BLTZALL | |
57871462 | 5770 | { |
630b122b | 5771 | emit_test(s1l,s1l); |
5772 | nottaken=out; | |
5773 | emit_jns(DJT_1); | |
57871462 | 5774 | } |
630b122b | 5775 | if((dops[i].opcode2&0x0d)==1) // BGEZ/BGEZL/BGEZAL/BGEZALL |
57871462 | 5776 | { |
630b122b | 5777 | emit_test(s1l,s1l); |
5778 | nottaken=out; | |
5779 | emit_js(DJT_1); | |
57871462 | 5780 | } |
57871462 | 5781 | } // if(!unconditional) |
5782 | int adj; | |
5783 | uint64_t ds_unneeded=branch_regs[i].u; | |
630b122b | 5784 | ds_unneeded&=~((1LL<<dops[i+1].rs1)|(1LL<<dops[i+1].rs2)); |
57871462 | 5785 | ds_unneeded|=1; |
57871462 | 5786 | // branch taken |
630b122b | 5787 | if(!nevertaken) { |
5788 | //assem_debug("1:\n"); | |
5789 | wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,ds_unneeded); | |
5790 | // load regs | |
5791 | load_regs(regs[i].regmap,branch_regs[i].regmap,dops[i+1].rs1,dops[i+1].rs2); | |
5792 | address_generation(i+1,&branch_regs[i],0); | |
5793 | if (ram_offset) | |
5794 | load_regs(regs[i].regmap,branch_regs[i].regmap,ROREG,ROREG); | |
5795 | load_regs(regs[i].regmap,branch_regs[i].regmap,CCREG,INVCP); | |
5796 | ds_assemble(i+1,&branch_regs[i]); | |
5797 | cc=get_reg(branch_regs[i].regmap,CCREG); | |
5798 | if(cc==-1) { | |
5799 | emit_loadreg(CCREG,cc=HOST_CCREG); | |
5800 | // CHECK: Is the following instruction (fall thru) allocated ok? | |
5801 | } | |
5802 | assert(cc==HOST_CCREG); | |
5803 | store_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]); | |
5804 | do_cc(i,i_regmap,&adj,ba[i],TAKEN,0); | |
5805 | assem_debug("cycle count (adj)\n"); | |
5806 | if(adj) emit_addimm(cc, ccadj[i] + CLOCK_ADJUST(2) - adj, cc); | |
5807 | load_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]); | |
5808 | if(internal) | |
5809 | assem_debug("branch: internal\n"); | |
5810 | else | |
5811 | assem_debug("branch: external\n"); | |
5812 | if (internal && dops[(ba[i] - start) >> 2].is_ds) { | |
5813 | ds_assemble_entry(i); | |
5814 | } | |
5815 | else { | |
5816 | add_to_linker(out,ba[i],internal); | |
5817 | emit_jmp(0); | |
5818 | } | |
57871462 | 5819 | } |
57871462 | 5820 | // branch not taken |
630b122b | 5821 | if(!unconditional) { |
5822 | set_jump_target(nottaken, out); | |
57871462 | 5823 | assem_debug("1:\n"); |
630b122b | 5824 | wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,ds_unneeded); |
5825 | load_regs(regs[i].regmap,branch_regs[i].regmap,dops[i+1].rs1,dops[i+1].rs2); | |
5826 | address_generation(i+1,&branch_regs[i],0); | |
5827 | load_regs(regs[i].regmap,branch_regs[i].regmap,CCREG,CCREG); | |
5828 | ds_assemble(i+1,&branch_regs[i]); | |
57871462 | 5829 | cc=get_reg(branch_regs[i].regmap,CCREG); |
630b122b | 5830 | if (cc == -1) { |
57871462 | 5831 | // Cycle count isn't in a register, temporarily load it then write it out |
5832 | emit_loadreg(CCREG,HOST_CCREG); | |
630b122b | 5833 | emit_addimm_and_set_flags(ccadj[i] + CLOCK_ADJUST(2), HOST_CCREG); |
5834 | void *jaddr=out; | |
57871462 | 5835 | emit_jns(0); |
630b122b | 5836 | add_stub(CC_STUB,jaddr,out,0,i,start+i*4+8,NOTTAKEN,0); |
57871462 | 5837 | emit_storereg(CCREG,HOST_CCREG); |
5838 | } | |
5839 | else{ | |
5840 | cc=get_reg(i_regmap,CCREG); | |
5841 | assert(cc==HOST_CCREG); | |
630b122b | 5842 | emit_addimm_and_set_flags(ccadj[i] + CLOCK_ADJUST(2), cc); |
5843 | void *jaddr=out; | |
57871462 | 5844 | emit_jns(0); |
630b122b | 5845 | add_stub(CC_STUB,jaddr,out,0,i,start+i*4+8,NOTTAKEN,0); |
57871462 | 5846 | } |
5847 | } | |
5848 | } | |
5849 | } | |
5850 | ||
630b122b | 5851 | static void pagespan_assemble(int i, const struct regstat *i_regs) |
57871462 | 5852 | { |
630b122b | 5853 | int s1l=get_reg(i_regs->regmap,dops[i].rs1); |
5854 | int s2l=get_reg(i_regs->regmap,dops[i].rs2); | |
5855 | void *taken = NULL; | |
5856 | void *nottaken = NULL; | |
57871462 | 5857 | int unconditional=0; |
630b122b | 5858 | if(dops[i].rs1==0) |
57871462 | 5859 | { |
630b122b | 5860 | s1l=s2l; |
5861 | s2l=-1; | |
57871462 | 5862 | } |
630b122b | 5863 | else if(dops[i].rs2==0) |
57871462 | 5864 | { |
630b122b | 5865 | s2l=-1; |
57871462 | 5866 | } |
5867 | int hr=0; | |
581335b0 | 5868 | int addr=-1,alt=-1,ntaddr=-1; |
57871462 | 5869 | if(i_regs->regmap[HOST_BTREG]<0) {addr=HOST_BTREG;} |
5870 | else { | |
5871 | while(hr<HOST_REGS) | |
5872 | { | |
5873 | if(hr!=EXCLUDE_REG && hr!=HOST_CCREG && | |
630b122b | 5874 | (i_regs->regmap[hr]&63)!=dops[i].rs1 && |
5875 | (i_regs->regmap[hr]&63)!=dops[i].rs2 ) | |
57871462 | 5876 | { |
5877 | addr=hr++;break; | |
5878 | } | |
5879 | hr++; | |
5880 | } | |
5881 | } | |
5882 | while(hr<HOST_REGS) | |
5883 | { | |
5884 | if(hr!=EXCLUDE_REG && hr!=HOST_CCREG && hr!=HOST_BTREG && | |
630b122b | 5885 | (i_regs->regmap[hr]&63)!=dops[i].rs1 && |
5886 | (i_regs->regmap[hr]&63)!=dops[i].rs2 ) | |
57871462 | 5887 | { |
5888 | alt=hr++;break; | |
5889 | } | |
5890 | hr++; | |
5891 | } | |
630b122b | 5892 | if((dops[i].opcode&0x2E)==6) // BLEZ/BGTZ needs another register |
57871462 | 5893 | { |
5894 | while(hr<HOST_REGS) | |
5895 | { | |
5896 | if(hr!=EXCLUDE_REG && hr!=HOST_CCREG && hr!=HOST_BTREG && | |
630b122b | 5897 | (i_regs->regmap[hr]&63)!=dops[i].rs1 && |
5898 | (i_regs->regmap[hr]&63)!=dops[i].rs2 ) | |
57871462 | 5899 | { |
5900 | ntaddr=hr;break; | |
5901 | } | |
5902 | hr++; | |
5903 | } | |
5904 | } | |
5905 | assert(hr<HOST_REGS); | |
630b122b | 5906 | if((dops[i].opcode&0x2e)==4||dops[i].opcode==0x11) { // BEQ/BNE/BEQL/BNEL/BC1 |
5907 | load_regs(regs[i].regmap_entry,regs[i].regmap,CCREG,CCREG); | |
57871462 | 5908 | } |
630b122b | 5909 | emit_addimm(HOST_CCREG, ccadj[i] + CLOCK_ADJUST(2), HOST_CCREG); |
5910 | if(dops[i].opcode==2) // J | |
57871462 | 5911 | { |
5912 | unconditional=1; | |
5913 | } | |
630b122b | 5914 | if(dops[i].opcode==3) // JAL |
57871462 | 5915 | { |
5916 | // TODO: mini_ht | |
5917 | int rt=get_reg(i_regs->regmap,31); | |
5918 | emit_movimm(start+i*4+8,rt); | |
5919 | unconditional=1; | |
5920 | } | |
630b122b | 5921 | if(dops[i].opcode==0&&(dops[i].opcode2&0x3E)==8) // JR/JALR |
57871462 | 5922 | { |
5923 | emit_mov(s1l,addr); | |
630b122b | 5924 | if(dops[i].opcode2==9) // JALR |
57871462 | 5925 | { |
630b122b | 5926 | int rt=get_reg(i_regs->regmap,dops[i].rt1); |
57871462 | 5927 | emit_movimm(start+i*4+8,rt); |
5928 | } | |
5929 | } | |
630b122b | 5930 | if((dops[i].opcode&0x3f)==4) // BEQ |
57871462 | 5931 | { |
630b122b | 5932 | if(dops[i].rs1==dops[i].rs2) |
57871462 | 5933 | { |
5934 | unconditional=1; | |
5935 | } | |
5936 | else | |
5937 | #ifdef HAVE_CMOV_IMM | |
630b122b | 5938 | if(1) { |
57871462 | 5939 | if(s2l>=0) emit_cmp(s1l,s2l); |
5940 | else emit_test(s1l,s1l); | |
5941 | emit_cmov2imm_e_ne_compact(ba[i],start+i*4+8,addr); | |
5942 | } | |
5943 | else | |
5944 | #endif | |
5945 | { | |
5946 | assert(s1l>=0); | |
5947 | emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt); | |
57871462 | 5948 | if(s2l>=0) emit_cmp(s1l,s2l); |
5949 | else emit_test(s1l,s1l); | |
5950 | emit_cmovne_reg(alt,addr); | |
5951 | } | |
5952 | } | |
630b122b | 5953 | if((dops[i].opcode&0x3f)==5) // BNE |
57871462 | 5954 | { |
5955 | #ifdef HAVE_CMOV_IMM | |
630b122b | 5956 | if(s2l>=0) emit_cmp(s1l,s2l); |
5957 | else emit_test(s1l,s1l); | |
5958 | emit_cmov2imm_e_ne_compact(start+i*4+8,ba[i],addr); | |
5959 | #else | |
5960 | assert(s1l>=0); | |
5961 | emit_mov2imm_compact(start+i*4+8,addr,ba[i],alt); | |
5962 | if(s2l>=0) emit_cmp(s1l,s2l); | |
5963 | else emit_test(s1l,s1l); | |
5964 | emit_cmovne_reg(alt,addr); | |
57871462 | 5965 | #endif |
57871462 | 5966 | } |
630b122b | 5967 | if((dops[i].opcode&0x3f)==0x14) // BEQL |
57871462 | 5968 | { |
57871462 | 5969 | if(s2l>=0) emit_cmp(s1l,s2l); |
5970 | else emit_test(s1l,s1l); | |
630b122b | 5971 | if(nottaken) set_jump_target(nottaken, out); |
5972 | nottaken=out; | |
57871462 | 5973 | emit_jne(0); |
5974 | } | |
630b122b | 5975 | if((dops[i].opcode&0x3f)==0x15) // BNEL |
57871462 | 5976 | { |
57871462 | 5977 | if(s2l>=0) emit_cmp(s1l,s2l); |
5978 | else emit_test(s1l,s1l); | |
630b122b | 5979 | nottaken=out; |
57871462 | 5980 | emit_jeq(0); |
630b122b | 5981 | if(taken) set_jump_target(taken, out); |
57871462 | 5982 | } |
630b122b | 5983 | if((dops[i].opcode&0x3f)==6) // BLEZ |
57871462 | 5984 | { |
5985 | emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr); | |
5986 | emit_cmpimm(s1l,1); | |
57871462 | 5987 | emit_cmovl_reg(alt,addr); |
57871462 | 5988 | } |
630b122b | 5989 | if((dops[i].opcode&0x3f)==7) // BGTZ |
57871462 | 5990 | { |
5991 | emit_mov2imm_compact(ba[i],addr,start+i*4+8,ntaddr); | |
5992 | emit_cmpimm(s1l,1); | |
57871462 | 5993 | emit_cmovl_reg(ntaddr,addr); |
57871462 | 5994 | } |
630b122b | 5995 | if((dops[i].opcode&0x3f)==0x16) // BLEZL |
57871462 | 5996 | { |
630b122b | 5997 | assert((dops[i].opcode&0x3f)!=0x16); |
57871462 | 5998 | } |
630b122b | 5999 | if((dops[i].opcode&0x3f)==0x17) // BGTZL |
57871462 | 6000 | { |
630b122b | 6001 | assert((dops[i].opcode&0x3f)!=0x17); |
57871462 | 6002 | } |
630b122b | 6003 | assert(dops[i].opcode!=1); // BLTZ/BGEZ |
57871462 | 6004 | |
6005 | //FIXME: Check CSREG | |
630b122b | 6006 | if(dops[i].opcode==0x11 && dops[i].opcode2==0x08 ) { |
57871462 | 6007 | if((source[i]&0x30000)==0) // BC1F |
6008 | { | |
6009 | emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt); | |
6010 | emit_testimm(s1l,0x800000); | |
6011 | emit_cmovne_reg(alt,addr); | |
6012 | } | |
6013 | if((source[i]&0x30000)==0x10000) // BC1T | |
6014 | { | |
6015 | emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr); | |
6016 | emit_testimm(s1l,0x800000); | |
6017 | emit_cmovne_reg(alt,addr); | |
6018 | } | |
6019 | if((source[i]&0x30000)==0x20000) // BC1FL | |
6020 | { | |
6021 | emit_testimm(s1l,0x800000); | |
630b122b | 6022 | nottaken=out; |
57871462 | 6023 | emit_jne(0); |
6024 | } | |
6025 | if((source[i]&0x30000)==0x30000) // BC1TL | |
6026 | { | |
6027 | emit_testimm(s1l,0x800000); | |
630b122b | 6028 | nottaken=out; |
57871462 | 6029 | emit_jeq(0); |
6030 | } | |
6031 | } | |
6032 | ||
6033 | assert(i_regs->regmap[HOST_CCREG]==CCREG); | |
630b122b | 6034 | wb_dirtys(regs[i].regmap,regs[i].dirty); |
6035 | if(unconditional) | |
57871462 | 6036 | { |
6037 | emit_movimm(ba[i],HOST_BTREG); | |
6038 | } | |
6039 | else if(addr!=HOST_BTREG) | |
6040 | { | |
6041 | emit_mov(addr,HOST_BTREG); | |
6042 | } | |
6043 | void *branch_addr=out; | |
6044 | emit_jmp(0); | |
6045 | int target_addr=start+i*4+5; | |
6046 | void *stub=out; | |
6047 | void *compiled_target_addr=check_addr(target_addr); | |
630b122b | 6048 | emit_extjump_ds(branch_addr, target_addr); |
57871462 | 6049 | if(compiled_target_addr) { |
630b122b | 6050 | set_jump_target(branch_addr, compiled_target_addr); |
6051 | add_jump_out(target_addr,stub); | |
57871462 | 6052 | } |
630b122b | 6053 | else set_jump_target(branch_addr, stub); |
57871462 | 6054 | } |
6055 | ||
6056 | // Assemble the delay slot for the above | |
6057 | static void pagespan_ds() | |
6058 | { | |
6059 | assem_debug("initial delay slot:\n"); | |
6060 | u_int vaddr=start+1; | |
94d23bb9 | 6061 | u_int page=get_page(vaddr); |
6062 | u_int vpage=get_vpage(vaddr); | |
57871462 | 6063 | ll_add(jump_dirty+vpage,vaddr,(void *)out); |
630b122b | 6064 | do_dirty_stub_ds(slen*4); |
57871462 | 6065 | ll_add(jump_in+page,vaddr,(void *)out); |
6066 | assert(regs[0].regmap_entry[HOST_CCREG]==CCREG); | |
6067 | if(regs[0].regmap[HOST_CCREG]!=CCREG) | |
630b122b | 6068 | wb_register(CCREG,regs[0].regmap_entry,regs[0].wasdirty); |
57871462 | 6069 | if(regs[0].regmap[HOST_BTREG]!=BTREG) |
630b122b | 6070 | emit_writeword(HOST_BTREG,&branch_target); |
6071 | load_regs(regs[0].regmap_entry,regs[0].regmap,dops[0].rs1,dops[0].rs2); | |
57871462 | 6072 | address_generation(0,®s[0],regs[0].regmap_entry); |
630b122b | 6073 | if (ram_offset && (dops[0].is_load || dops[0].is_store)) |
6074 | load_regs(regs[0].regmap_entry,regs[0].regmap,ROREG,ROREG); | |
6075 | if (dops[0].is_store) | |
6076 | load_regs(regs[0].regmap_entry,regs[0].regmap,INVCP,INVCP); | |
57871462 | 6077 | is_delayslot=0; |
630b122b | 6078 | switch (dops[0].itype) { |
57871462 | 6079 | case SYSCALL: |
7139f3c8 | 6080 | case HLECALL: |
1e973cb0 | 6081 | case INTCALL: |
57871462 | 6082 | case SPAN: |
6083 | case UJUMP: | |
6084 | case RJUMP: | |
6085 | case CJUMP: | |
6086 | case SJUMP: | |
c43b5311 | 6087 | SysPrintf("Jump in the delay slot. This is probably a bug.\n"); |
630b122b | 6088 | break; |
6089 | default: | |
6090 | assemble(0, ®s[0], 0); | |
57871462 | 6091 | } |
6092 | int btaddr=get_reg(regs[0].regmap,BTREG); | |
6093 | if(btaddr<0) { | |
6094 | btaddr=get_reg(regs[0].regmap,-1); | |
630b122b | 6095 | emit_readword(&branch_target,btaddr); |
57871462 | 6096 | } |
6097 | assert(btaddr!=HOST_CCREG); | |
6098 | if(regs[0].regmap[HOST_CCREG]!=CCREG) emit_loadreg(CCREG,HOST_CCREG); | |
6099 | #ifdef HOST_IMM8 | |
630b122b | 6100 | host_tempreg_acquire(); |
57871462 | 6101 | emit_movimm(start+4,HOST_TEMPREG); |
6102 | emit_cmp(btaddr,HOST_TEMPREG); | |
630b122b | 6103 | host_tempreg_release(); |
57871462 | 6104 | #else |
6105 | emit_cmpimm(btaddr,start+4); | |
6106 | #endif | |
630b122b | 6107 | void *branch = out; |
57871462 | 6108 | emit_jeq(0); |
630b122b | 6109 | store_regs_bt(regs[0].regmap,regs[0].dirty,-1); |
6110 | do_jump_vaddr(btaddr); | |
6111 | set_jump_target(branch, out); | |
6112 | store_regs_bt(regs[0].regmap,regs[0].dirty,start+4); | |
6113 | load_regs_bt(regs[0].regmap,regs[0].dirty,start+4); | |
57871462 | 6114 | } |
6115 | ||
6116 | // Basic liveness analysis for MIPS registers | |
6117 | void unneeded_registers(int istart,int iend,int r) | |
6118 | { | |
6119 | int i; | |
630b122b | 6120 | uint64_t u,gte_u,b,gte_b; |
6121 | uint64_t temp_u,temp_gte_u=0; | |
0ff8c62c | 6122 | uint64_t gte_u_unknown=0; |
630b122b | 6123 | if (HACK_ENABLED(NDHACK_GTE_UNNEEDED)) |
0ff8c62c | 6124 | gte_u_unknown=~0ll; |
57871462 | 6125 | if(iend==slen-1) { |
630b122b | 6126 | u=1; |
0ff8c62c | 6127 | gte_u=gte_u_unknown; |
57871462 | 6128 | }else{ |
630b122b | 6129 | //u=unneeded_reg[iend+1]; |
6130 | u=1; | |
0ff8c62c | 6131 | gte_u=gte_unneeded[iend+1]; |
57871462 | 6132 | } |
bedfea38 | 6133 | |
57871462 | 6134 | for (i=iend;i>=istart;i--) |
6135 | { | |
6136 | //printf("unneeded registers i=%d (%d,%d) r=%d\n",i,istart,iend,r); | |
630b122b | 6137 | if(dops[i].is_jump) |
57871462 | 6138 | { |
6139 | // If subroutine call, flag return address as a possible branch target | |
630b122b | 6140 | if(dops[i].rt1==31 && i<slen-2) dops[i+2].bt=1; |
9f51b4b9 | 6141 | |
57871462 | 6142 | if(ba[i]<start || ba[i]>=(start+slen*4)) |
6143 | { | |
6144 | // Branch out of this block, flush all regs | |
6145 | u=1; | |
0ff8c62c | 6146 | gte_u=gte_u_unknown; |
57871462 | 6147 | branch_unneeded_reg[i]=u; |
57871462 | 6148 | // Merge in delay slot |
630b122b | 6149 | u|=(1LL<<dops[i+1].rt1)|(1LL<<dops[i+1].rt2); |
6150 | u&=~((1LL<<dops[i+1].rs1)|(1LL<<dops[i+1].rs2)); | |
6151 | u|=1; | |
bedfea38 | 6152 | gte_u|=gte_rt[i+1]; |
6153 | gte_u&=~gte_rs[i+1]; | |
57871462 | 6154 | } |
6155 | else | |
6156 | { | |
6157 | // Internal branch, flag target | |
630b122b | 6158 | dops[(ba[i]-start)>>2].bt=1; |
57871462 | 6159 | if(ba[i]<=start+i*4) { |
6160 | // Backward branch | |
630b122b | 6161 | if(dops[i].is_ujump) |
57871462 | 6162 | { |
6163 | // Unconditional branch | |
630b122b | 6164 | temp_u=1; |
bedfea38 | 6165 | temp_gte_u=0; |
57871462 | 6166 | } else { |
6167 | // Conditional branch (not taken case) | |
6168 | temp_u=unneeded_reg[i+2]; | |
bedfea38 | 6169 | temp_gte_u&=gte_unneeded[i+2]; |
57871462 | 6170 | } |
6171 | // Merge in delay slot | |
630b122b | 6172 | temp_u|=(1LL<<dops[i+1].rt1)|(1LL<<dops[i+1].rt2); |
6173 | temp_u&=~((1LL<<dops[i+1].rs1)|(1LL<<dops[i+1].rs2)); | |
6174 | temp_u|=1; | |
bedfea38 | 6175 | temp_gte_u|=gte_rt[i+1]; |
6176 | temp_gte_u&=~gte_rs[i+1]; | |
630b122b | 6177 | temp_u|=(1LL<<dops[i].rt1)|(1LL<<dops[i].rt2); |
6178 | temp_u&=~((1LL<<dops[i].rs1)|(1LL<<dops[i].rs2)); | |
6179 | temp_u|=1; | |
bedfea38 | 6180 | temp_gte_u|=gte_rt[i]; |
6181 | temp_gte_u&=~gte_rs[i]; | |
57871462 | 6182 | unneeded_reg[i]=temp_u; |
bedfea38 | 6183 | gte_unneeded[i]=temp_gte_u; |
57871462 | 6184 | // Only go three levels deep. This recursion can take an |
6185 | // excessive amount of time if there are a lot of nested loops. | |
6186 | if(r<2) { | |
6187 | unneeded_registers((ba[i]-start)>>2,i-1,r+1); | |
6188 | }else{ | |
6189 | unneeded_reg[(ba[i]-start)>>2]=1; | |
0ff8c62c | 6190 | gte_unneeded[(ba[i]-start)>>2]=gte_u_unknown; |
57871462 | 6191 | } |
6192 | } /*else*/ if(1) { | |
630b122b | 6193 | if (dops[i].is_ujump) |
57871462 | 6194 | { |
6195 | // Unconditional branch | |
6196 | u=unneeded_reg[(ba[i]-start)>>2]; | |
bedfea38 | 6197 | gte_u=gte_unneeded[(ba[i]-start)>>2]; |
57871462 | 6198 | branch_unneeded_reg[i]=u; |
57871462 | 6199 | // Merge in delay slot |
630b122b | 6200 | u|=(1LL<<dops[i+1].rt1)|(1LL<<dops[i+1].rt2); |
6201 | u&=~((1LL<<dops[i+1].rs1)|(1LL<<dops[i+1].rs2)); | |
6202 | u|=1; | |
bedfea38 | 6203 | gte_u|=gte_rt[i+1]; |
6204 | gte_u&=~gte_rs[i+1]; | |
57871462 | 6205 | } else { |
6206 | // Conditional branch | |
6207 | b=unneeded_reg[(ba[i]-start)>>2]; | |
630b122b | 6208 | gte_b=gte_unneeded[(ba[i]-start)>>2]; |
57871462 | 6209 | branch_unneeded_reg[i]=b; |
57871462 | 6210 | // Branch delay slot |
630b122b | 6211 | b|=(1LL<<dops[i+1].rt1)|(1LL<<dops[i+1].rt2); |
6212 | b&=~((1LL<<dops[i+1].rs1)|(1LL<<dops[i+1].rs2)); | |
6213 | b|=1; | |
6214 | gte_b|=gte_rt[i+1]; | |
6215 | gte_b&=~gte_rs[i+1]; | |
6216 | u&=b; | |
6217 | gte_u&=gte_b; | |
57871462 | 6218 | if(i<slen-1) { |
6219 | branch_unneeded_reg[i]&=unneeded_reg[i+2]; | |
57871462 | 6220 | } else { |
6221 | branch_unneeded_reg[i]=1; | |
57871462 | 6222 | } |
6223 | } | |
6224 | } | |
6225 | } | |
6226 | } | |
630b122b | 6227 | else if(dops[i].itype==SYSCALL||dops[i].itype==HLECALL||dops[i].itype==INTCALL) |
57871462 | 6228 | { |
6229 | // SYSCALL instruction (software interrupt) | |
6230 | u=1; | |
57871462 | 6231 | } |
630b122b | 6232 | else if(dops[i].itype==COP0 && (source[i]&0x3f)==0x18) |
57871462 | 6233 | { |
6234 | // ERET instruction (return from interrupt) | |
6235 | u=1; | |
57871462 | 6236 | } |
630b122b | 6237 | //u=1; // DEBUG |
57871462 | 6238 | // Written registers are unneeded |
630b122b | 6239 | u|=1LL<<dops[i].rt1; |
6240 | u|=1LL<<dops[i].rt2; | |
bedfea38 | 6241 | gte_u|=gte_rt[i]; |
57871462 | 6242 | // Accessed registers are needed |
630b122b | 6243 | u&=~(1LL<<dops[i].rs1); |
6244 | u&=~(1LL<<dops[i].rs2); | |
bedfea38 | 6245 | gte_u&=~gte_rs[i]; |
630b122b | 6246 | if(gte_rs[i]&&dops[i].rt1&&(unneeded_reg[i+1]&(1ll<<dops[i].rt1))) |
cbbd8dd7 | 6247 | gte_u|=gte_rs[i]>e_unneeded[i+1]; // MFC2/CFC2 to dead register, unneeded |
57871462 | 6248 | // Source-target dependencies |
57871462 | 6249 | // R0 is always unneeded |
630b122b | 6250 | u|=1; |
57871462 | 6251 | // Save it |
6252 | unneeded_reg[i]=u; | |
bedfea38 | 6253 | gte_unneeded[i]=gte_u; |
57871462 | 6254 | /* |
6255 | printf("ur (%d,%d) %x: ",istart,iend,start+i*4); | |
6256 | printf("U:"); | |
6257 | int r; | |
6258 | for(r=1;r<=CCREG;r++) { | |
6259 | if((unneeded_reg[i]>>r)&1) { | |
6260 | if(r==HIREG) printf(" HI"); | |
6261 | else if(r==LOREG) printf(" LO"); | |
6262 | else printf(" r%d",r); | |
6263 | } | |
6264 | } | |
630b122b | 6265 | printf("\n"); |
6266 | */ | |
252c20fc | 6267 | } |
57871462 | 6268 | } |
6269 | ||
71e490c5 | 6270 | // Write back dirty registers as soon as we will no longer modify them, |
6271 | // so that we don't end up with lots of writes at the branches. | |
6272 | void clean_registers(int istart,int iend,int wr) | |
57871462 | 6273 | { |
71e490c5 | 6274 | int i; |
6275 | int r; | |
6276 | u_int will_dirty_i,will_dirty_next,temp_will_dirty; | |
6277 | u_int wont_dirty_i,wont_dirty_next,temp_wont_dirty; | |
6278 | if(iend==slen-1) { | |
6279 | will_dirty_i=will_dirty_next=0; | |
6280 | wont_dirty_i=wont_dirty_next=0; | |
6281 | }else{ | |
6282 | will_dirty_i=will_dirty_next=will_dirty[iend+1]; | |
6283 | wont_dirty_i=wont_dirty_next=wont_dirty[iend+1]; | |
6284 | } | |
6285 | for (i=iend;i>=istart;i--) | |
57871462 | 6286 | { |
630b122b | 6287 | if(dops[i].is_jump) |
57871462 | 6288 | { |
71e490c5 | 6289 | if(ba[i]<start || ba[i]>=(start+slen*4)) |
57871462 | 6290 | { |
71e490c5 | 6291 | // Branch out of this block, flush all regs |
630b122b | 6292 | if (dops[i].is_ujump) |
57871462 | 6293 | { |
6294 | // Unconditional branch | |
6295 | will_dirty_i=0; | |
6296 | wont_dirty_i=0; | |
6297 | // Merge in delay slot (will dirty) | |
6298 | for(r=0;r<HOST_REGS;r++) { | |
6299 | if(r!=EXCLUDE_REG) { | |
630b122b | 6300 | if((branch_regs[i].regmap[r]&63)==dops[i].rt1) will_dirty_i|=1<<r; |
6301 | if((branch_regs[i].regmap[r]&63)==dops[i].rt2) will_dirty_i|=1<<r; | |
6302 | if((branch_regs[i].regmap[r]&63)==dops[i+1].rt1) will_dirty_i|=1<<r; | |
6303 | if((branch_regs[i].regmap[r]&63)==dops[i+1].rt2) will_dirty_i|=1<<r; | |
57871462 | 6304 | if((branch_regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r); |
6305 | if(branch_regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r); | |
6306 | if(branch_regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r; | |
630b122b | 6307 | if((regs[i].regmap[r]&63)==dops[i].rt1) will_dirty_i|=1<<r; |
6308 | if((regs[i].regmap[r]&63)==dops[i].rt2) will_dirty_i|=1<<r; | |
6309 | if((regs[i].regmap[r]&63)==dops[i+1].rt1) will_dirty_i|=1<<r; | |
6310 | if((regs[i].regmap[r]&63)==dops[i+1].rt2) will_dirty_i|=1<<r; | |
57871462 | 6311 | if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r); |
6312 | if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r); | |
6313 | if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r; | |
6314 | } | |
6315 | } | |
6316 | } | |
6317 | else | |
6318 | { | |
6319 | // Conditional branch | |
6320 | will_dirty_i=0; | |
6321 | wont_dirty_i=wont_dirty_next; | |
6322 | // Merge in delay slot (will dirty) | |
6323 | for(r=0;r<HOST_REGS;r++) { | |
6324 | if(r!=EXCLUDE_REG) { | |
630b122b | 6325 | if (1) { // !dops[i].likely) { |
57871462 | 6326 | // Might not dirty if likely branch is not taken |
630b122b | 6327 | if((branch_regs[i].regmap[r]&63)==dops[i].rt1) will_dirty_i|=1<<r; |
6328 | if((branch_regs[i].regmap[r]&63)==dops[i].rt2) will_dirty_i|=1<<r; | |
6329 | if((branch_regs[i].regmap[r]&63)==dops[i+1].rt1) will_dirty_i|=1<<r; | |
6330 | if((branch_regs[i].regmap[r]&63)==dops[i+1].rt2) will_dirty_i|=1<<r; | |
57871462 | 6331 | if((branch_regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r); |
6332 | if(branch_regs[i].regmap[r]==0) will_dirty_i&=~(1<<r); | |
6333 | if(branch_regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r; | |
630b122b | 6334 | //if((regs[i].regmap[r]&63)==dops[i].rt1) will_dirty_i|=1<<r; |
6335 | //if((regs[i].regmap[r]&63)==dops[i].rt2) will_dirty_i|=1<<r; | |
6336 | if((regs[i].regmap[r]&63)==dops[i+1].rt1) will_dirty_i|=1<<r; | |
6337 | if((regs[i].regmap[r]&63)==dops[i+1].rt2) will_dirty_i|=1<<r; | |
57871462 | 6338 | if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r); |
6339 | if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r); | |
6340 | if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r; | |
6341 | } | |
6342 | } | |
6343 | } | |
6344 | } | |
6345 | // Merge in delay slot (wont dirty) | |
6346 | for(r=0;r<HOST_REGS;r++) { | |
6347 | if(r!=EXCLUDE_REG) { | |
630b122b | 6348 | if((regs[i].regmap[r]&63)==dops[i].rt1) wont_dirty_i|=1<<r; |
6349 | if((regs[i].regmap[r]&63)==dops[i].rt2) wont_dirty_i|=1<<r; | |
6350 | if((regs[i].regmap[r]&63)==dops[i+1].rt1) wont_dirty_i|=1<<r; | |
6351 | if((regs[i].regmap[r]&63)==dops[i+1].rt2) wont_dirty_i|=1<<r; | |
57871462 | 6352 | if(regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r; |
630b122b | 6353 | if((branch_regs[i].regmap[r]&63)==dops[i].rt1) wont_dirty_i|=1<<r; |
6354 | if((branch_regs[i].regmap[r]&63)==dops[i].rt2) wont_dirty_i|=1<<r; | |
6355 | if((branch_regs[i].regmap[r]&63)==dops[i+1].rt1) wont_dirty_i|=1<<r; | |
6356 | if((branch_regs[i].regmap[r]&63)==dops[i+1].rt2) wont_dirty_i|=1<<r; | |
57871462 | 6357 | if(branch_regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r; |
6358 | } | |
6359 | } | |
6360 | if(wr) { | |
6361 | #ifndef DESTRUCTIVE_WRITEBACK | |
6362 | branch_regs[i].dirty&=wont_dirty_i; | |
6363 | #endif | |
6364 | branch_regs[i].dirty|=will_dirty_i; | |
6365 | } | |
6366 | } | |
6367 | else | |
6368 | { | |
6369 | // Internal branch | |
6370 | if(ba[i]<=start+i*4) { | |
6371 | // Backward branch | |
630b122b | 6372 | if (dops[i].is_ujump) |
57871462 | 6373 | { |
6374 | // Unconditional branch | |
6375 | temp_will_dirty=0; | |
6376 | temp_wont_dirty=0; | |
6377 | // Merge in delay slot (will dirty) | |
6378 | for(r=0;r<HOST_REGS;r++) { | |
6379 | if(r!=EXCLUDE_REG) { | |
630b122b | 6380 | if((branch_regs[i].regmap[r]&63)==dops[i].rt1) temp_will_dirty|=1<<r; |
6381 | if((branch_regs[i].regmap[r]&63)==dops[i].rt2) temp_will_dirty|=1<<r; | |
6382 | if((branch_regs[i].regmap[r]&63)==dops[i+1].rt1) temp_will_dirty|=1<<r; | |
6383 | if((branch_regs[i].regmap[r]&63)==dops[i+1].rt2) temp_will_dirty|=1<<r; | |
57871462 | 6384 | if((branch_regs[i].regmap[r]&63)>33) temp_will_dirty&=~(1<<r); |
6385 | if(branch_regs[i].regmap[r]<=0) temp_will_dirty&=~(1<<r); | |
6386 | if(branch_regs[i].regmap[r]==CCREG) temp_will_dirty|=1<<r; | |
630b122b | 6387 | if((regs[i].regmap[r]&63)==dops[i].rt1) temp_will_dirty|=1<<r; |
6388 | if((regs[i].regmap[r]&63)==dops[i].rt2) temp_will_dirty|=1<<r; | |
6389 | if((regs[i].regmap[r]&63)==dops[i+1].rt1) temp_will_dirty|=1<<r; | |
6390 | if((regs[i].regmap[r]&63)==dops[i+1].rt2) temp_will_dirty|=1<<r; | |
57871462 | 6391 | if((regs[i].regmap[r]&63)>33) temp_will_dirty&=~(1<<r); |
6392 | if(regs[i].regmap[r]<=0) temp_will_dirty&=~(1<<r); | |
6393 | if(regs[i].regmap[r]==CCREG) temp_will_dirty|=1<<r; | |
6394 | } | |
6395 | } | |
6396 | } else { | |
6397 | // Conditional branch (not taken case) | |
6398 | temp_will_dirty=will_dirty_next; | |
6399 | temp_wont_dirty=wont_dirty_next; | |
6400 | // Merge in delay slot (will dirty) | |
6401 | for(r=0;r<HOST_REGS;r++) { | |
6402 | if(r!=EXCLUDE_REG) { | |
630b122b | 6403 | if (1) { // !dops[i].likely) { |
57871462 | 6404 | // Will not dirty if likely branch is not taken |
630b122b | 6405 | if((branch_regs[i].regmap[r]&63)==dops[i].rt1) temp_will_dirty|=1<<r; |
6406 | if((branch_regs[i].regmap[r]&63)==dops[i].rt2) temp_will_dirty|=1<<r; | |
6407 | if((branch_regs[i].regmap[r]&63)==dops[i+1].rt1) temp_will_dirty|=1<<r; | |
6408 | if((branch_regs[i].regmap[r]&63)==dops[i+1].rt2) temp_will_dirty|=1<<r; | |
57871462 | 6409 | if((branch_regs[i].regmap[r]&63)>33) temp_will_dirty&=~(1<<r); |
6410 | if(branch_regs[i].regmap[r]==0) temp_will_dirty&=~(1<<r); | |
6411 | if(branch_regs[i].regmap[r]==CCREG) temp_will_dirty|=1<<r; | |
630b122b | 6412 | //if((regs[i].regmap[r]&63)==dops[i].rt1) temp_will_dirty|=1<<r; |
6413 | //if((regs[i].regmap[r]&63)==dops[i].rt2) temp_will_dirty|=1<<r; | |
6414 | if((regs[i].regmap[r]&63)==dops[i+1].rt1) temp_will_dirty|=1<<r; | |
6415 | if((regs[i].regmap[r]&63)==dops[i+1].rt2) temp_will_dirty|=1<<r; | |
57871462 | 6416 | if((regs[i].regmap[r]&63)>33) temp_will_dirty&=~(1<<r); |
6417 | if(regs[i].regmap[r]<=0) temp_will_dirty&=~(1<<r); | |
6418 | if(regs[i].regmap[r]==CCREG) temp_will_dirty|=1<<r; | |
6419 | } | |
6420 | } | |
6421 | } | |
6422 | } | |
6423 | // Merge in delay slot (wont dirty) | |
6424 | for(r=0;r<HOST_REGS;r++) { | |
6425 | if(r!=EXCLUDE_REG) { | |
630b122b | 6426 | if((regs[i].regmap[r]&63)==dops[i].rt1) temp_wont_dirty|=1<<r; |
6427 | if((regs[i].regmap[r]&63)==dops[i].rt2) temp_wont_dirty|=1<<r; | |
6428 | if((regs[i].regmap[r]&63)==dops[i+1].rt1) temp_wont_dirty|=1<<r; | |
6429 | if((regs[i].regmap[r]&63)==dops[i+1].rt2) temp_wont_dirty|=1<<r; | |
57871462 | 6430 | if(regs[i].regmap[r]==CCREG) temp_wont_dirty|=1<<r; |
630b122b | 6431 | if((branch_regs[i].regmap[r]&63)==dops[i].rt1) temp_wont_dirty|=1<<r; |
6432 | if((branch_regs[i].regmap[r]&63)==dops[i].rt2) temp_wont_dirty|=1<<r; | |
6433 | if((branch_regs[i].regmap[r]&63)==dops[i+1].rt1) temp_wont_dirty|=1<<r; | |
6434 | if((branch_regs[i].regmap[r]&63)==dops[i+1].rt2) temp_wont_dirty|=1<<r; | |
57871462 | 6435 | if(branch_regs[i].regmap[r]==CCREG) temp_wont_dirty|=1<<r; |
6436 | } | |
6437 | } | |
6438 | // Deal with changed mappings | |
6439 | if(i<iend) { | |
6440 | for(r=0;r<HOST_REGS;r++) { | |
6441 | if(r!=EXCLUDE_REG) { | |
6442 | if(regs[i].regmap[r]!=regmap_pre[i][r]) { | |
6443 | temp_will_dirty&=~(1<<r); | |
6444 | temp_wont_dirty&=~(1<<r); | |
6445 | if((regmap_pre[i][r]&63)>0 && (regmap_pre[i][r]&63)<34) { | |
6446 | temp_will_dirty|=((unneeded_reg[i]>>(regmap_pre[i][r]&63))&1)<<r; | |
6447 | temp_wont_dirty|=((unneeded_reg[i]>>(regmap_pre[i][r]&63))&1)<<r; | |
6448 | } else { | |
6449 | temp_will_dirty|=1<<r; | |
6450 | temp_wont_dirty|=1<<r; | |
6451 | } | |
6452 | } | |
6453 | } | |
6454 | } | |
6455 | } | |
6456 | if(wr) { | |
6457 | will_dirty[i]=temp_will_dirty; | |
6458 | wont_dirty[i]=temp_wont_dirty; | |
6459 | clean_registers((ba[i]-start)>>2,i-1,0); | |
6460 | }else{ | |
6461 | // Limit recursion. It can take an excessive amount | |
6462 | // of time if there are a lot of nested loops. | |
6463 | will_dirty[(ba[i]-start)>>2]=0; | |
6464 | wont_dirty[(ba[i]-start)>>2]=-1; | |
6465 | } | |
6466 | } | |
6467 | /*else*/ if(1) | |
6468 | { | |
630b122b | 6469 | if (dops[i].is_ujump) |
57871462 | 6470 | { |
6471 | // Unconditional branch | |
6472 | will_dirty_i=0; | |
6473 | wont_dirty_i=0; | |
6474 | //if(ba[i]>start+i*4) { // Disable recursion (for debugging) | |
6475 | for(r=0;r<HOST_REGS;r++) { | |
6476 | if(r!=EXCLUDE_REG) { | |
6477 | if(branch_regs[i].regmap[r]==regs[(ba[i]-start)>>2].regmap_entry[r]) { | |
6478 | will_dirty_i|=will_dirty[(ba[i]-start)>>2]&(1<<r); | |
6479 | wont_dirty_i|=wont_dirty[(ba[i]-start)>>2]&(1<<r); | |
6480 | } | |
e3234ecf | 6481 | if(branch_regs[i].regmap[r]>=0) { |
6482 | will_dirty_i|=((unneeded_reg[(ba[i]-start)>>2]>>(branch_regs[i].regmap[r]&63))&1)<<r; | |
6483 | wont_dirty_i|=((unneeded_reg[(ba[i]-start)>>2]>>(branch_regs[i].regmap[r]&63))&1)<<r; | |
6484 | } | |
57871462 | 6485 | } |
6486 | } | |
6487 | //} | |
6488 | // Merge in delay slot | |
6489 | for(r=0;r<HOST_REGS;r++) { | |
6490 | if(r!=EXCLUDE_REG) { | |
630b122b | 6491 | if((branch_regs[i].regmap[r]&63)==dops[i].rt1) will_dirty_i|=1<<r; |
6492 | if((branch_regs[i].regmap[r]&63)==dops[i].rt2) will_dirty_i|=1<<r; | |
6493 | if((branch_regs[i].regmap[r]&63)==dops[i+1].rt1) will_dirty_i|=1<<r; | |
6494 | if((branch_regs[i].regmap[r]&63)==dops[i+1].rt2) will_dirty_i|=1<<r; | |
57871462 | 6495 | if((branch_regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r); |
6496 | if(branch_regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r); | |
6497 | if(branch_regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r; | |
630b122b | 6498 | if((regs[i].regmap[r]&63)==dops[i].rt1) will_dirty_i|=1<<r; |
6499 | if((regs[i].regmap[r]&63)==dops[i].rt2) will_dirty_i|=1<<r; | |
6500 | if((regs[i].regmap[r]&63)==dops[i+1].rt1) will_dirty_i|=1<<r; | |
6501 | if((regs[i].regmap[r]&63)==dops[i+1].rt2) will_dirty_i|=1<<r; | |
57871462 | 6502 | if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r); |
6503 | if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r); | |
6504 | if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r; | |
6505 | } | |
6506 | } | |
6507 | } else { | |
6508 | // Conditional branch | |
6509 | will_dirty_i=will_dirty_next; | |
6510 | wont_dirty_i=wont_dirty_next; | |
6511 | //if(ba[i]>start+i*4) { // Disable recursion (for debugging) | |
6512 | for(r=0;r<HOST_REGS;r++) { | |
6513 | if(r!=EXCLUDE_REG) { | |
e3234ecf | 6514 | signed char target_reg=branch_regs[i].regmap[r]; |
6515 | if(target_reg==regs[(ba[i]-start)>>2].regmap_entry[r]) { | |
57871462 | 6516 | will_dirty_i&=will_dirty[(ba[i]-start)>>2]&(1<<r); |
6517 | wont_dirty_i|=wont_dirty[(ba[i]-start)>>2]&(1<<r); | |
6518 | } | |
e3234ecf | 6519 | else if(target_reg>=0) { |
6520 | will_dirty_i&=((unneeded_reg[(ba[i]-start)>>2]>>(target_reg&63))&1)<<r; | |
6521 | wont_dirty_i|=((unneeded_reg[(ba[i]-start)>>2]>>(target_reg&63))&1)<<r; | |
57871462 | 6522 | } |
57871462 | 6523 | } |
6524 | } | |
6525 | //} | |
6526 | // Merge in delay slot | |
6527 | for(r=0;r<HOST_REGS;r++) { | |
6528 | if(r!=EXCLUDE_REG) { | |
630b122b | 6529 | if (1) { // !dops[i].likely) { |
57871462 | 6530 | // Might not dirty if likely branch is not taken |
630b122b | 6531 | if((branch_regs[i].regmap[r]&63)==dops[i].rt1) will_dirty_i|=1<<r; |
6532 | if((branch_regs[i].regmap[r]&63)==dops[i].rt2) will_dirty_i|=1<<r; | |
6533 | if((branch_regs[i].regmap[r]&63)==dops[i+1].rt1) will_dirty_i|=1<<r; | |
6534 | if((branch_regs[i].regmap[r]&63)==dops[i+1].rt2) will_dirty_i|=1<<r; | |
57871462 | 6535 | if((branch_regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r); |
6536 | if(branch_regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r); | |
6537 | if(branch_regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r; | |
630b122b | 6538 | //if((regs[i].regmap[r]&63)==dops[i].rt1) will_dirty_i|=1<<r; |
6539 | //if((regs[i].regmap[r]&63)==dops[i].rt2) will_dirty_i|=1<<r; | |
6540 | if((regs[i].regmap[r]&63)==dops[i+1].rt1) will_dirty_i|=1<<r; | |
6541 | if((regs[i].regmap[r]&63)==dops[i+1].rt2) will_dirty_i|=1<<r; | |
57871462 | 6542 | if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r); |
6543 | if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r); | |
6544 | if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r; | |
6545 | } | |
6546 | } | |
6547 | } | |
6548 | } | |
e3234ecf | 6549 | // Merge in delay slot (won't dirty) |
57871462 | 6550 | for(r=0;r<HOST_REGS;r++) { |
6551 | if(r!=EXCLUDE_REG) { | |
630b122b | 6552 | if((regs[i].regmap[r]&63)==dops[i].rt1) wont_dirty_i|=1<<r; |
6553 | if((regs[i].regmap[r]&63)==dops[i].rt2) wont_dirty_i|=1<<r; | |
6554 | if((regs[i].regmap[r]&63)==dops[i+1].rt1) wont_dirty_i|=1<<r; | |
6555 | if((regs[i].regmap[r]&63)==dops[i+1].rt2) wont_dirty_i|=1<<r; | |
57871462 | 6556 | if(regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r; |
630b122b | 6557 | if((branch_regs[i].regmap[r]&63)==dops[i].rt1) wont_dirty_i|=1<<r; |
6558 | if((branch_regs[i].regmap[r]&63)==dops[i].rt2) wont_dirty_i|=1<<r; | |
6559 | if((branch_regs[i].regmap[r]&63)==dops[i+1].rt1) wont_dirty_i|=1<<r; | |
6560 | if((branch_regs[i].regmap[r]&63)==dops[i+1].rt2) wont_dirty_i|=1<<r; | |
57871462 | 6561 | if(branch_regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r; |
6562 | } | |
6563 | } | |
6564 | if(wr) { | |
6565 | #ifndef DESTRUCTIVE_WRITEBACK | |
6566 | branch_regs[i].dirty&=wont_dirty_i; | |
6567 | #endif | |
6568 | branch_regs[i].dirty|=will_dirty_i; | |
6569 | } | |
6570 | } | |
6571 | } | |
6572 | } | |
630b122b | 6573 | else if(dops[i].itype==SYSCALL||dops[i].itype==HLECALL||dops[i].itype==INTCALL) |
57871462 | 6574 | { |
6575 | // SYSCALL instruction (software interrupt) | |
6576 | will_dirty_i=0; | |
6577 | wont_dirty_i=0; | |
6578 | } | |
630b122b | 6579 | else if(dops[i].itype==COP0 && (source[i]&0x3f)==0x18) |
57871462 | 6580 | { |
6581 | // ERET instruction (return from interrupt) | |
6582 | will_dirty_i=0; | |
6583 | wont_dirty_i=0; | |
6584 | } | |
6585 | will_dirty_next=will_dirty_i; | |
6586 | wont_dirty_next=wont_dirty_i; | |
6587 | for(r=0;r<HOST_REGS;r++) { | |
6588 | if(r!=EXCLUDE_REG) { | |
630b122b | 6589 | if((regs[i].regmap[r]&63)==dops[i].rt1) will_dirty_i|=1<<r; |
6590 | if((regs[i].regmap[r]&63)==dops[i].rt2) will_dirty_i|=1<<r; | |
57871462 | 6591 | if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r); |
6592 | if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r); | |
6593 | if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r; | |
630b122b | 6594 | if((regs[i].regmap[r]&63)==dops[i].rt1) wont_dirty_i|=1<<r; |
6595 | if((regs[i].regmap[r]&63)==dops[i].rt2) wont_dirty_i|=1<<r; | |
57871462 | 6596 | if(regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r; |
6597 | if(i>istart) { | |
630b122b | 6598 | if (!dops[i].is_jump) |
57871462 | 6599 | { |
6600 | // Don't store a register immediately after writing it, | |
6601 | // may prevent dual-issue. | |
630b122b | 6602 | if((regs[i].regmap[r]&63)==dops[i-1].rt1) wont_dirty_i|=1<<r; |
6603 | if((regs[i].regmap[r]&63)==dops[i-1].rt2) wont_dirty_i|=1<<r; | |
57871462 | 6604 | } |
6605 | } | |
6606 | } | |
6607 | } | |
6608 | // Save it | |
6609 | will_dirty[i]=will_dirty_i; | |
6610 | wont_dirty[i]=wont_dirty_i; | |
6611 | // Mark registers that won't be dirtied as not dirty | |
6612 | if(wr) { | |
57871462 | 6613 | regs[i].dirty|=will_dirty_i; |
6614 | #ifndef DESTRUCTIVE_WRITEBACK | |
6615 | regs[i].dirty&=wont_dirty_i; | |
630b122b | 6616 | if(dops[i].is_jump) |
57871462 | 6617 | { |
630b122b | 6618 | if (i < iend-1 && !dops[i].is_ujump) { |
57871462 | 6619 | for(r=0;r<HOST_REGS;r++) { |
6620 | if(r!=EXCLUDE_REG) { | |
6621 | if(regs[i].regmap[r]==regmap_pre[i+2][r]) { | |
6622 | regs[i+2].wasdirty&=wont_dirty_i|~(1<<r); | |
581335b0 | 6623 | }else {/*printf("i: %x (%d) mismatch(+2): %d\n",start+i*4,i,r);assert(!((wont_dirty_i>>r)&1));*/} |
57871462 | 6624 | } |
6625 | } | |
6626 | } | |
6627 | } | |
6628 | else | |
6629 | { | |
6630 | if(i<iend) { | |
6631 | for(r=0;r<HOST_REGS;r++) { | |
6632 | if(r!=EXCLUDE_REG) { | |
6633 | if(regs[i].regmap[r]==regmap_pre[i+1][r]) { | |
6634 | regs[i+1].wasdirty&=wont_dirty_i|~(1<<r); | |
581335b0 | 6635 | }else {/*printf("i: %x (%d) mismatch(+1): %d\n",start+i*4,i,r);assert(!((wont_dirty_i>>r)&1));*/} |
57871462 | 6636 | } |
6637 | } | |
6638 | } | |
6639 | } | |
6640 | #endif | |
6641 | //} | |
6642 | } | |
6643 | // Deal with changed mappings | |
6644 | temp_will_dirty=will_dirty_i; | |
6645 | temp_wont_dirty=wont_dirty_i; | |
6646 | for(r=0;r<HOST_REGS;r++) { | |
6647 | if(r!=EXCLUDE_REG) { | |
6648 | int nr; | |
6649 | if(regs[i].regmap[r]==regmap_pre[i][r]) { | |
6650 | if(wr) { | |
6651 | #ifndef DESTRUCTIVE_WRITEBACK | |
6652 | regs[i].wasdirty&=wont_dirty_i|~(1<<r); | |
6653 | #endif | |
6654 | regs[i].wasdirty|=will_dirty_i&(1<<r); | |
6655 | } | |
6656 | } | |
f776eb14 | 6657 | else if(regmap_pre[i][r]>=0&&(nr=get_reg(regs[i].regmap,regmap_pre[i][r]))>=0) { |
57871462 | 6658 | // Register moved to a different register |
6659 | will_dirty_i&=~(1<<r); | |
6660 | wont_dirty_i&=~(1<<r); | |
6661 | will_dirty_i|=((temp_will_dirty>>nr)&1)<<r; | |
6662 | wont_dirty_i|=((temp_wont_dirty>>nr)&1)<<r; | |
6663 | if(wr) { | |
6664 | #ifndef DESTRUCTIVE_WRITEBACK | |
6665 | regs[i].wasdirty&=wont_dirty_i|~(1<<r); | |
6666 | #endif | |
6667 | regs[i].wasdirty|=will_dirty_i&(1<<r); | |
6668 | } | |
6669 | } | |
6670 | else { | |
6671 | will_dirty_i&=~(1<<r); | |
6672 | wont_dirty_i&=~(1<<r); | |
6673 | if((regmap_pre[i][r]&63)>0 && (regmap_pre[i][r]&63)<34) { | |
6674 | will_dirty_i|=((unneeded_reg[i]>>(regmap_pre[i][r]&63))&1)<<r; | |
6675 | wont_dirty_i|=((unneeded_reg[i]>>(regmap_pre[i][r]&63))&1)<<r; | |
6676 | } else { | |
6677 | wont_dirty_i|=1<<r; | |
581335b0 | 6678 | /*printf("i: %x (%d) mismatch: %d\n",start+i*4,i,r);assert(!((will_dirty>>r)&1));*/ |
57871462 | 6679 | } |
6680 | } | |
6681 | } | |
6682 | } | |
6683 | } | |
6684 | } | |
6685 | ||
4600ba03 | 6686 | #ifdef DISASM |
57871462 | 6687 | /* disassembly */ |
6688 | void disassemble_inst(int i) | |
6689 | { | |
630b122b | 6690 | if (dops[i].bt) printf("*"); else printf(" "); |
6691 | switch(dops[i].itype) { | |
57871462 | 6692 | case UJUMP: |
6693 | printf (" %x: %s %8x\n",start+i*4,insn[i],ba[i]);break; | |
6694 | case CJUMP: | |
630b122b | 6695 | printf (" %x: %s r%d,r%d,%8x\n",start+i*4,insn[i],dops[i].rs1,dops[i].rs2,i?start+i*4+4+((signed int)((unsigned int)source[i]<<16)>>14):*ba);break; |
57871462 | 6696 | case SJUMP: |
630b122b | 6697 | printf (" %x: %s r%d,%8x\n",start+i*4,insn[i],dops[i].rs1,start+i*4+4+((signed int)((unsigned int)source[i]<<16)>>14));break; |
57871462 | 6698 | case RJUMP: |
630b122b | 6699 | if (dops[i].opcode==0x9&&dops[i].rt1!=31) |
6700 | printf (" %x: %s r%d,r%d\n",start+i*4,insn[i],dops[i].rt1,dops[i].rs1); | |
5067f341 | 6701 | else |
630b122b | 6702 | printf (" %x: %s r%d\n",start+i*4,insn[i],dops[i].rs1); |
5067f341 | 6703 | break; |
57871462 | 6704 | case SPAN: |
630b122b | 6705 | printf (" %x: %s (pagespan) r%d,r%d,%8x\n",start+i*4,insn[i],dops[i].rs1,dops[i].rs2,ba[i]);break; |
57871462 | 6706 | case IMM16: |
630b122b | 6707 | if(dops[i].opcode==0xf) //LUI |
6708 | printf (" %x: %s r%d,%4x0000\n",start+i*4,insn[i],dops[i].rt1,imm[i]&0xffff); | |
57871462 | 6709 | else |
630b122b | 6710 | printf (" %x: %s r%d,r%d,%d\n",start+i*4,insn[i],dops[i].rt1,dops[i].rs1,imm[i]); |
57871462 | 6711 | break; |
6712 | case LOAD: | |
6713 | case LOADLR: | |
630b122b | 6714 | printf (" %x: %s r%d,r%d+%x\n",start+i*4,insn[i],dops[i].rt1,dops[i].rs1,imm[i]); |
57871462 | 6715 | break; |
6716 | case STORE: | |
6717 | case STORELR: | |
630b122b | 6718 | printf (" %x: %s r%d,r%d+%x\n",start+i*4,insn[i],dops[i].rs2,dops[i].rs1,imm[i]); |
57871462 | 6719 | break; |
6720 | case ALU: | |
6721 | case SHIFT: | |
630b122b | 6722 | printf (" %x: %s r%d,r%d,r%d\n",start+i*4,insn[i],dops[i].rt1,dops[i].rs1,dops[i].rs2); |
57871462 | 6723 | break; |
6724 | case MULTDIV: | |
630b122b | 6725 | printf (" %x: %s r%d,r%d\n",start+i*4,insn[i],dops[i].rs1,dops[i].rs2); |
57871462 | 6726 | break; |
6727 | case SHIFTIMM: | |
630b122b | 6728 | printf (" %x: %s r%d,r%d,%d\n",start+i*4,insn[i],dops[i].rt1,dops[i].rs1,imm[i]); |
57871462 | 6729 | break; |
6730 | case MOV: | |
630b122b | 6731 | if((dops[i].opcode2&0x1d)==0x10) |
6732 | printf (" %x: %s r%d\n",start+i*4,insn[i],dops[i].rt1); | |
6733 | else if((dops[i].opcode2&0x1d)==0x11) | |
6734 | printf (" %x: %s r%d\n",start+i*4,insn[i],dops[i].rs1); | |
57871462 | 6735 | else |
6736 | printf (" %x: %s\n",start+i*4,insn[i]); | |
6737 | break; | |
6738 | case COP0: | |
630b122b | 6739 | if(dops[i].opcode2==0) |
6740 | printf (" %x: %s r%d,cpr0[%d]\n",start+i*4,insn[i],dops[i].rt1,(source[i]>>11)&0x1f); // MFC0 | |
6741 | else if(dops[i].opcode2==4) | |
6742 | printf (" %x: %s r%d,cpr0[%d]\n",start+i*4,insn[i],dops[i].rs1,(source[i]>>11)&0x1f); // MTC0 | |
57871462 | 6743 | else printf (" %x: %s\n",start+i*4,insn[i]); |
6744 | break; | |
6745 | case COP1: | |
630b122b | 6746 | if(dops[i].opcode2<3) |
6747 | printf (" %x: %s r%d,cpr1[%d]\n",start+i*4,insn[i],dops[i].rt1,(source[i]>>11)&0x1f); // MFC1 | |
6748 | else if(dops[i].opcode2>3) | |
6749 | printf (" %x: %s r%d,cpr1[%d]\n",start+i*4,insn[i],dops[i].rs1,(source[i]>>11)&0x1f); // MTC1 | |
57871462 | 6750 | else printf (" %x: %s\n",start+i*4,insn[i]); |
6751 | break; | |
b9b61529 | 6752 | case COP2: |
630b122b | 6753 | if(dops[i].opcode2<3) |
6754 | printf (" %x: %s r%d,cpr2[%d]\n",start+i*4,insn[i],dops[i].rt1,(source[i]>>11)&0x1f); // MFC2 | |
6755 | else if(dops[i].opcode2>3) | |
6756 | printf (" %x: %s r%d,cpr2[%d]\n",start+i*4,insn[i],dops[i].rs1,(source[i]>>11)&0x1f); // MTC2 | |
b9b61529 | 6757 | else printf (" %x: %s\n",start+i*4,insn[i]); |
6758 | break; | |
57871462 | 6759 | case C1LS: |
630b122b | 6760 | printf (" %x: %s cpr1[%d],r%d+%x\n",start+i*4,insn[i],(source[i]>>16)&0x1f,dops[i].rs1,imm[i]); |
57871462 | 6761 | break; |
b9b61529 | 6762 | case C2LS: |
630b122b | 6763 | printf (" %x: %s cpr2[%d],r%d+%x\n",start+i*4,insn[i],(source[i]>>16)&0x1f,dops[i].rs1,imm[i]); |
b9b61529 | 6764 | break; |
1e973cb0 | 6765 | case INTCALL: |
6766 | printf (" %x: %s (INTCALL)\n",start+i*4,insn[i]); | |
6767 | break; | |
57871462 | 6768 | default: |
6769 | //printf (" %s %8x\n",insn[i],source[i]); | |
6770 | printf (" %x: %s\n",start+i*4,insn[i]); | |
6771 | } | |
6772 | } | |
4600ba03 | 6773 | #else |
6774 | static void disassemble_inst(int i) {} | |
6775 | #endif // DISASM | |
57871462 | 6776 | |
d848b60a | 6777 | #define DRC_TEST_VAL 0x74657374 |
6778 | ||
630b122b | 6779 | static void new_dynarec_test(void) |
d848b60a | 6780 | { |
630b122b | 6781 | int (*testfunc)(void); |
d148d265 | 6782 | void *beginning; |
630b122b | 6783 | int ret[2]; |
6784 | size_t i; | |
d148d265 | 6785 | |
630b122b | 6786 | // check structure linkage |
6787 | if ((u_char *)rcnts - (u_char *)&psxRegs != sizeof(psxRegs)) | |
6788 | { | |
6789 | SysPrintf("linkage_arm* miscompilation/breakage detected.\n"); | |
6790 | } | |
6791 | ||
6792 | SysPrintf("testing if we can run recompiled code...\n"); | |
6793 | ((volatile u_int *)out)[0]++; // make cache dirty | |
6794 | ||
6795 | for (i = 0; i < ARRAY_SIZE(ret); i++) { | |
6796 | out = ndrc->translation_cache; | |
6797 | beginning = start_block(); | |
6798 | emit_movimm(DRC_TEST_VAL + i, 0); // test | |
6799 | emit_ret(); | |
6800 | literal_pool(0); | |
6801 | end_block(beginning); | |
6802 | testfunc = beginning; | |
6803 | ret[i] = testfunc(); | |
6804 | } | |
6805 | ||
6806 | if (ret[0] == DRC_TEST_VAL && ret[1] == DRC_TEST_VAL + 1) | |
d848b60a | 6807 | SysPrintf("test passed.\n"); |
6808 | else | |
630b122b | 6809 | SysPrintf("test failed, will likely crash soon (r=%08x %08x)\n", ret[0], ret[1]); |
6810 | out = ndrc->translation_cache; | |
d848b60a | 6811 | } |
6812 | ||
dc990066 | 6813 | // clear the state completely, instead of just marking |
6814 | // things invalid like invalidate_all_pages() does | |
92d79826 | 6815 | void new_dynarec_clear_full(void) |
57871462 | 6816 | { |
57871462 | 6817 | int n; |
630b122b | 6818 | out = ndrc->translation_cache; |
35775df7 | 6819 | memset(invalid_code,1,sizeof(invalid_code)); |
6820 | memset(hash_table,0xff,sizeof(hash_table)); | |
57871462 | 6821 | memset(mini_ht,-1,sizeof(mini_ht)); |
6822 | memset(restore_candidate,0,sizeof(restore_candidate)); | |
dc990066 | 6823 | memset(shadow,0,sizeof(shadow)); |
57871462 | 6824 | copy=shadow; |
6825 | expirep=16384; // Expiry pointer, +2 blocks | |
6826 | pending_exception=0; | |
6827 | literalcount=0; | |
57871462 | 6828 | stop_after_jal=0; |
9be4ba64 | 6829 | inv_code_start=inv_code_end=~0; |
630b122b | 6830 | f1_hack=0; |
57871462 | 6831 | // TLB |
dc990066 | 6832 | for(n=0;n<4096;n++) ll_clear(jump_in+n); |
6833 | for(n=0;n<4096;n++) ll_clear(jump_out+n); | |
6834 | for(n=0;n<4096;n++) ll_clear(jump_dirty+n); | |
630b122b | 6835 | |
6836 | cycle_multiplier_old = cycle_multiplier; | |
6837 | new_dynarec_hacks_old = new_dynarec_hacks; | |
dc990066 | 6838 | } |
6839 | ||
92d79826 | 6840 | void new_dynarec_init(void) |
dc990066 | 6841 | { |
d848b60a | 6842 | SysPrintf("Init new dynarec\n"); |
1e212a25 | 6843 | |
4666f75d | 6844 | #ifdef _3DS |
6845 | check_rosalina(); | |
6846 | #endif | |
630b122b | 6847 | #ifdef BASE_ADDR_DYNAMIC |
6848 | #ifdef VITA | |
4666f75d | 6849 | sceBlock = getVMBlock(); //sceKernelAllocMemBlockForVM("code", sizeof(*ndrc)); |
1e212a25 | 6850 | if (sceBlock < 0) |
6851 | SysPrintf("sceKernelAllocMemBlockForVM failed\n"); | |
630b122b | 6852 | int ret = sceKernelGetMemBlockBase(sceBlock, (void **)&ndrc); |
1e212a25 | 6853 | if (ret < 0) |
6854 | SysPrintf("sceKernelGetMemBlockBase failed\n"); | |
4666f75d | 6855 | sceKernelOpenVMDomain(); |
6856 | sceClibPrintf("translation_cache = 0x%08lx\n ", (long)ndrc->translation_cache); | |
6857 | #elif defined(_MSC_VER) | |
6858 | ndrc = VirtualAlloc(NULL, sizeof(*ndrc), MEM_COMMIT | MEM_RESERVE, | |
6859 | PAGE_EXECUTE_READWRITE); | |
630b122b | 6860 | #else |
6861 | uintptr_t desired_addr = 0; | |
6862 | #ifdef __ELF__ | |
6863 | extern char _end; | |
6864 | desired_addr = ((uintptr_t)&_end + 0xffffff) & ~0xffffffl; | |
6865 | #endif | |
6866 | ndrc = mmap((void *)desired_addr, sizeof(*ndrc), | |
6867 | PROT_READ | PROT_WRITE | PROT_EXEC, | |
6868 | MAP_PRIVATE | MAP_ANONYMOUS, -1, 0); | |
6869 | if (ndrc == MAP_FAILED) { | |
d848b60a | 6870 | SysPrintf("mmap() failed: %s\n", strerror(errno)); |
1e212a25 | 6871 | abort(); |
d848b60a | 6872 | } |
630b122b | 6873 | #endif |
1e212a25 | 6874 | #else |
630b122b | 6875 | #ifndef NO_WRITE_EXEC |
bdeade46 | 6876 | // not all systems allow execute in data segment by default |
630b122b | 6877 | if (mprotect(ndrc, sizeof(ndrc->translation_cache) + sizeof(ndrc->tramp.ops), |
6878 | PROT_READ | PROT_WRITE | PROT_EXEC) != 0) | |
d848b60a | 6879 | SysPrintf("mprotect() failed: %s\n", strerror(errno)); |
630b122b | 6880 | #endif |
dc990066 | 6881 | #endif |
630b122b | 6882 | out = ndrc->translation_cache; |
2573466a | 6883 | cycle_multiplier=200; |
dc990066 | 6884 | new_dynarec_clear_full(); |
6885 | #ifdef HOST_IMM8 | |
6886 | // Copy this into local area so we don't have to put it in every literal pool | |
6887 | invc_ptr=invalid_code; | |
6888 | #endif | |
57871462 | 6889 | arch_init(); |
d848b60a | 6890 | new_dynarec_test(); |
630b122b | 6891 | ram_offset=(uintptr_t)rdram-0x80000000; |
b105cf4f | 6892 | if (ram_offset!=0) |
c43b5311 | 6893 | SysPrintf("warning: RAM is not directly mapped, performance will suffer\n"); |
57871462 | 6894 | } |
6895 | ||
92d79826 | 6896 | void new_dynarec_cleanup(void) |
57871462 | 6897 | { |
6898 | int n; | |
630b122b | 6899 | #ifdef BASE_ADDR_DYNAMIC |
6900 | #ifdef VITA | |
6901 | sceKernelFreeMemBlock(sceBlock); | |
6902 | sceBlock = -1; | |
6903 | #else | |
6904 | if (munmap(ndrc, sizeof(*ndrc)) < 0) | |
1e212a25 | 6905 | SysPrintf("munmap() failed\n"); |
630b122b | 6906 | #endif |
1e212a25 | 6907 | #endif |
630b122b | 6908 | for(n=0;n<4096;n++) ll_clear(jump_in+n); |
6909 | for(n=0;n<4096;n++) ll_clear(jump_out+n); | |
6910 | for(n=0;n<4096;n++) ll_clear(jump_dirty+n); | |
6911 | #ifdef ROM_COPY | |
c43b5311 | 6912 | if (munmap (ROM_COPY, 67108864) < 0) {SysPrintf("munmap() failed\n");} |
630b122b | 6913 | #endif |
57871462 | 6914 | } |
6915 | ||
03f55e6b | 6916 | static u_int *get_source_start(u_int addr, u_int *limit) |
57871462 | 6917 | { |
03f55e6b | 6918 | if (addr < 0x00200000 || |
630b122b | 6919 | (0xa0000000 <= addr && addr < 0xa0200000)) |
6920 | { | |
03f55e6b | 6921 | // used for BIOS calls mostly? |
6922 | *limit = (addr&0xa0000000)|0x00200000; | |
630b122b | 6923 | return (u_int *)(rdram + (addr&0x1fffff)); |
03f55e6b | 6924 | } |
6925 | else if (!Config.HLE && ( | |
6926 | /* (0x9fc00000 <= addr && addr < 0x9fc80000) ||*/ | |
630b122b | 6927 | (0xbfc00000 <= addr && addr < 0xbfc80000))) |
6928 | { | |
6929 | // BIOS. The multiplier should be much higher as it's uncached 8bit mem, | |
6930 | // but timings in PCSX are too tied to the interpreter's BIAS | |
6931 | if (!HACK_ENABLED(NDHACK_OVERRIDE_CYCLE_M)) | |
6932 | cycle_multiplier_active = 200; | |
6933 | ||
03f55e6b | 6934 | *limit = (addr & 0xfff00000) | 0x80000; |
630b122b | 6935 | return (u_int *)((u_char *)psxR + (addr&0x7ffff)); |
03f55e6b | 6936 | } |
6937 | else if (addr >= 0x80000000 && addr < 0x80000000+RAM_SIZE) { | |
6938 | *limit = (addr & 0x80600000) + 0x00200000; | |
630b122b | 6939 | return (u_int *)(rdram + (addr&0x1fffff)); |
03f55e6b | 6940 | } |
581335b0 | 6941 | return NULL; |
03f55e6b | 6942 | } |
6943 | ||
6944 | static u_int scan_for_ret(u_int addr) | |
6945 | { | |
6946 | u_int limit = 0; | |
6947 | u_int *mem; | |
6948 | ||
6949 | mem = get_source_start(addr, &limit); | |
6950 | if (mem == NULL) | |
6951 | return addr; | |
6952 | ||
6953 | if (limit > addr + 0x1000) | |
6954 | limit = addr + 0x1000; | |
6955 | for (; addr < limit; addr += 4, mem++) { | |
6956 | if (*mem == 0x03e00008) // jr $ra | |
6957 | return addr + 8; | |
57871462 | 6958 | } |
581335b0 | 6959 | return addr; |
03f55e6b | 6960 | } |
6961 | ||
6962 | struct savestate_block { | |
6963 | uint32_t addr; | |
6964 | uint32_t regflags; | |
6965 | }; | |
6966 | ||
6967 | static int addr_cmp(const void *p1_, const void *p2_) | |
6968 | { | |
6969 | const struct savestate_block *p1 = p1_, *p2 = p2_; | |
6970 | return p1->addr - p2->addr; | |
6971 | } | |
6972 | ||
6973 | int new_dynarec_save_blocks(void *save, int size) | |
6974 | { | |
6975 | struct savestate_block *blocks = save; | |
6976 | int maxcount = size / sizeof(blocks[0]); | |
6977 | struct savestate_block tmp_blocks[1024]; | |
6978 | struct ll_entry *head; | |
6979 | int p, s, d, o, bcnt; | |
6980 | u_int addr; | |
6981 | ||
6982 | o = 0; | |
630b122b | 6983 | for (p = 0; p < ARRAY_SIZE(jump_in); p++) { |
03f55e6b | 6984 | bcnt = 0; |
6985 | for (head = jump_in[p]; head != NULL; head = head->next) { | |
6986 | tmp_blocks[bcnt].addr = head->vaddr; | |
6987 | tmp_blocks[bcnt].regflags = head->reg_sv_flags; | |
6988 | bcnt++; | |
6989 | } | |
6990 | if (bcnt < 1) | |
6991 | continue; | |
6992 | qsort(tmp_blocks, bcnt, sizeof(tmp_blocks[0]), addr_cmp); | |
6993 | ||
6994 | addr = tmp_blocks[0].addr; | |
6995 | for (s = d = 0; s < bcnt; s++) { | |
6996 | if (tmp_blocks[s].addr < addr) | |
6997 | continue; | |
6998 | if (d == 0 || tmp_blocks[d-1].addr != tmp_blocks[s].addr) | |
6999 | tmp_blocks[d++] = tmp_blocks[s]; | |
7000 | addr = scan_for_ret(tmp_blocks[s].addr); | |
7001 | } | |
7002 | ||
7003 | if (o + d > maxcount) | |
7004 | d = maxcount - o; | |
7005 | memcpy(&blocks[o], tmp_blocks, d * sizeof(blocks[0])); | |
7006 | o += d; | |
7007 | } | |
7008 | ||
7009 | return o * sizeof(blocks[0]); | |
7010 | } | |
7011 | ||
7012 | void new_dynarec_load_blocks(const void *save, int size) | |
7013 | { | |
7014 | const struct savestate_block *blocks = save; | |
7015 | int count = size / sizeof(blocks[0]); | |
7016 | u_int regs_save[32]; | |
7017 | uint32_t f; | |
7018 | int i, b; | |
7019 | ||
7020 | get_addr(psxRegs.pc); | |
7021 | ||
7022 | // change GPRs for speculation to at least partially work.. | |
7023 | memcpy(regs_save, &psxRegs.GPR, sizeof(regs_save)); | |
7024 | for (i = 1; i < 32; i++) | |
7025 | psxRegs.GPR.r[i] = 0x80000000; | |
7026 | ||
7027 | for (b = 0; b < count; b++) { | |
7028 | for (f = blocks[b].regflags, i = 0; f; f >>= 1, i++) { | |
7029 | if (f & 1) | |
7030 | psxRegs.GPR.r[i] = 0x1f800000; | |
7031 | } | |
7032 | ||
7033 | get_addr(blocks[b].addr); | |
7034 | ||
7035 | for (f = blocks[b].regflags, i = 0; f; f >>= 1, i++) { | |
7036 | if (f & 1) | |
7037 | psxRegs.GPR.r[i] = 0x80000000; | |
7038 | } | |
7039 | } | |
7040 | ||
7041 | memcpy(&psxRegs.GPR, regs_save, sizeof(regs_save)); | |
7042 | } | |
7043 | ||
630b122b | 7044 | static void apply_hacks(void) |
7045 | { | |
7046 | int i; | |
7047 | if (HACK_ENABLED(NDHACK_NO_COMPAT_HACKS)) | |
7048 | return; | |
7049 | /* special hack(s) */ | |
7050 | for (i = 0; i < slen - 4; i++) | |
7051 | { | |
7052 | // lui a4, 0xf200; jal <rcnt_read>; addu a0, 2; slti v0, 28224 | |
7053 | if (source[i] == 0x3c04f200 && dops[i+1].itype == UJUMP | |
7054 | && source[i+2] == 0x34840002 && dops[i+3].opcode == 0x0a | |
7055 | && imm[i+3] == 0x6e40 && dops[i+3].rs1 == 2) | |
7056 | { | |
7057 | SysPrintf("PE2 hack @%08x\n", start + (i+3)*4); | |
7058 | dops[i + 3].itype = NOP; | |
7059 | } | |
7060 | } | |
7061 | i = slen; | |
7062 | if (i > 10 && source[i-1] == 0 && source[i-2] == 0x03e00008 | |
7063 | && source[i-4] == 0x8fbf0018 && source[i-6] == 0x00c0f809 | |
7064 | && dops[i-7].itype == STORE) | |
7065 | { | |
7066 | i = i-8; | |
7067 | if (dops[i].itype == IMM16) | |
7068 | i--; | |
7069 | // swl r2, 15(r6); swr r2, 12(r6); sw r6, *; jalr r6 | |
7070 | if (dops[i].itype == STORELR && dops[i].rs1 == 6 | |
7071 | && dops[i-1].itype == STORELR && dops[i-1].rs1 == 6) | |
7072 | { | |
7073 | SysPrintf("F1 hack from %08x\n", start); | |
7074 | if (f1_hack == 0) | |
7075 | f1_hack = ~0u; | |
7076 | } | |
7077 | } | |
7078 | } | |
7079 | ||
7080 | int new_recompile_block(u_int addr) | |
03f55e6b | 7081 | { |
7082 | u_int pagelimit = 0; | |
7083 | u_int state_rflags = 0; | |
7084 | int i; | |
7085 | ||
630b122b | 7086 | assem_debug("NOTCOMPILED: addr = %x -> %p\n", addr, out); |
57871462 | 7087 | //printf("TRACE: count=%d next=%d (compile %x)\n",Count,next_interupt,addr); |
9f51b4b9 | 7088 | //if(debug) |
57871462 | 7089 | //printf("fpu mapping=%x enabled=%x\n",(Status & 0x04000000)>>26,(Status & 0x20000000)>>29); |
03f55e6b | 7090 | |
7091 | // this is just for speculation | |
7092 | for (i = 1; i < 32; i++) { | |
7093 | if ((psxRegs.GPR.r[i] & 0xffff0000) == 0x1f800000) | |
7094 | state_rflags |= 1 << i; | |
7095 | } | |
7096 | ||
57871462 | 7097 | start = (u_int)addr&~3; |
630b122b | 7098 | //assert(((u_int)addr&1)==0); // start-in-delay-slot flag |
2f546f9a | 7099 | new_dynarec_did_compile=1; |
9ad4d757 | 7100 | if (Config.HLE && start == 0x80001000) // hlecall |
560e4a12 | 7101 | { |
7139f3c8 | 7102 | // XXX: is this enough? Maybe check hleSoftCall? |
d148d265 | 7103 | void *beginning=start_block(); |
7139f3c8 | 7104 | u_int page=get_page(start); |
d148d265 | 7105 | |
7139f3c8 | 7106 | invalid_code[start>>12]=0; |
7107 | emit_movimm(start,0); | |
630b122b | 7108 | emit_writeword(0,&pcaddr); |
7109 | emit_far_jump(new_dyna_leave); | |
15776b68 | 7110 | literal_pool(0); |
d148d265 | 7111 | end_block(beginning); |
03f55e6b | 7112 | ll_add_flags(jump_in+page,start,state_rflags,(void *)beginning); |
7139f3c8 | 7113 | return 0; |
7114 | } | |
630b122b | 7115 | else if (f1_hack == ~0u || (f1_hack != 0 && start == f1_hack)) { |
7116 | void *beginning = start_block(); | |
7117 | u_int page = get_page(start); | |
7118 | emit_readword(&psxRegs.GPR.n.sp, 0); | |
7119 | emit_readptr(&mem_rtab, 1); | |
7120 | emit_shrimm(0, 12, 2); | |
7121 | emit_readptr_dualindexedx_ptrlen(1, 2, 1); | |
7122 | emit_addimm(0, 0x18, 0); | |
7123 | emit_adds_ptr(1, 1, 1); | |
7124 | emit_ldr_dualindexed(1, 0, 0); | |
7125 | emit_writeword(0, &psxRegs.GPR.r[26]); // lw k0, 0x18(sp) | |
7126 | emit_far_call(get_addr_ht); | |
7127 | emit_jmpreg(0); // jr k0 | |
7128 | literal_pool(0); | |
7129 | end_block(beginning); | |
7130 | ||
7131 | ll_add_flags(jump_in + page, start, state_rflags, beginning); | |
7132 | SysPrintf("F1 hack to %08x\n", start); | |
7133 | f1_hack = start; | |
7134 | return 0; | |
7135 | } | |
7136 | ||
7137 | cycle_multiplier_active = cycle_multiplier_override && cycle_multiplier == CYCLE_MULT_DEFAULT | |
7138 | ? cycle_multiplier_override : cycle_multiplier; | |
03f55e6b | 7139 | |
7140 | source = get_source_start(start, &pagelimit); | |
7141 | if (source == NULL) { | |
7142 | SysPrintf("Compile at bogus memory address: %08x\n", addr); | |
630b122b | 7143 | abort(); |
57871462 | 7144 | } |
7145 | ||
7146 | /* Pass 1: disassemble */ | |
7147 | /* Pass 2: register dependencies, branch targets */ | |
7148 | /* Pass 3: register allocation */ | |
7149 | /* Pass 4: branch dependencies */ | |
7150 | /* Pass 5: pre-alloc */ | |
7151 | /* Pass 6: optimize clean/dirty state */ | |
7152 | /* Pass 7: flag 32-bit registers */ | |
7153 | /* Pass 8: assembly */ | |
7154 | /* Pass 9: linker */ | |
7155 | /* Pass 10: garbage collection / free memory */ | |
7156 | ||
03f55e6b | 7157 | int j; |
57871462 | 7158 | int done=0; |
7159 | unsigned int type,op,op2; | |
7160 | ||
7161 | //printf("addr = %x source = %x %x\n", addr,source,source[0]); | |
9f51b4b9 | 7162 | |
57871462 | 7163 | /* Pass 1 disassembly */ |
7164 | ||
7165 | for(i=0;!done;i++) { | |
630b122b | 7166 | dops[i].bt=0; |
7167 | dops[i].ooo=0; | |
7168 | op2=0; | |
e1190b87 | 7169 | minimum_free_regs[i]=0; |
630b122b | 7170 | dops[i].opcode=op=source[i]>>26; |
57871462 | 7171 | switch(op) |
7172 | { | |
7173 | case 0x00: strcpy(insn[i],"special"); type=NI; | |
7174 | op2=source[i]&0x3f; | |
7175 | switch(op2) | |
7176 | { | |
7177 | case 0x00: strcpy(insn[i],"SLL"); type=SHIFTIMM; break; | |
7178 | case 0x02: strcpy(insn[i],"SRL"); type=SHIFTIMM; break; | |
7179 | case 0x03: strcpy(insn[i],"SRA"); type=SHIFTIMM; break; | |
7180 | case 0x04: strcpy(insn[i],"SLLV"); type=SHIFT; break; | |
7181 | case 0x06: strcpy(insn[i],"SRLV"); type=SHIFT; break; | |
7182 | case 0x07: strcpy(insn[i],"SRAV"); type=SHIFT; break; | |
7183 | case 0x08: strcpy(insn[i],"JR"); type=RJUMP; break; | |
7184 | case 0x09: strcpy(insn[i],"JALR"); type=RJUMP; break; | |
7185 | case 0x0C: strcpy(insn[i],"SYSCALL"); type=SYSCALL; break; | |
7186 | case 0x0D: strcpy(insn[i],"BREAK"); type=OTHER; break; | |
7187 | case 0x0F: strcpy(insn[i],"SYNC"); type=OTHER; break; | |
7188 | case 0x10: strcpy(insn[i],"MFHI"); type=MOV; break; | |
7189 | case 0x11: strcpy(insn[i],"MTHI"); type=MOV; break; | |
7190 | case 0x12: strcpy(insn[i],"MFLO"); type=MOV; break; | |
7191 | case 0x13: strcpy(insn[i],"MTLO"); type=MOV; break; | |
57871462 | 7192 | case 0x18: strcpy(insn[i],"MULT"); type=MULTDIV; break; |
7193 | case 0x19: strcpy(insn[i],"MULTU"); type=MULTDIV; break; | |
7194 | case 0x1A: strcpy(insn[i],"DIV"); type=MULTDIV; break; | |
7195 | case 0x1B: strcpy(insn[i],"DIVU"); type=MULTDIV; break; | |
57871462 | 7196 | case 0x20: strcpy(insn[i],"ADD"); type=ALU; break; |
7197 | case 0x21: strcpy(insn[i],"ADDU"); type=ALU; break; | |
7198 | case 0x22: strcpy(insn[i],"SUB"); type=ALU; break; | |
7199 | case 0x23: strcpy(insn[i],"SUBU"); type=ALU; break; | |
7200 | case 0x24: strcpy(insn[i],"AND"); type=ALU; break; | |
7201 | case 0x25: strcpy(insn[i],"OR"); type=ALU; break; | |
7202 | case 0x26: strcpy(insn[i],"XOR"); type=ALU; break; | |
7203 | case 0x27: strcpy(insn[i],"NOR"); type=ALU; break; | |
7204 | case 0x2A: strcpy(insn[i],"SLT"); type=ALU; break; | |
7205 | case 0x2B: strcpy(insn[i],"SLTU"); type=ALU; break; | |
57871462 | 7206 | case 0x30: strcpy(insn[i],"TGE"); type=NI; break; |
7207 | case 0x31: strcpy(insn[i],"TGEU"); type=NI; break; | |
7208 | case 0x32: strcpy(insn[i],"TLT"); type=NI; break; | |
7209 | case 0x33: strcpy(insn[i],"TLTU"); type=NI; break; | |
7210 | case 0x34: strcpy(insn[i],"TEQ"); type=NI; break; | |
7211 | case 0x36: strcpy(insn[i],"TNE"); type=NI; break; | |
71e490c5 | 7212 | #if 0 |
7f2607ea | 7213 | case 0x14: strcpy(insn[i],"DSLLV"); type=SHIFT; break; |
7214 | case 0x16: strcpy(insn[i],"DSRLV"); type=SHIFT; break; | |
7215 | case 0x17: strcpy(insn[i],"DSRAV"); type=SHIFT; break; | |
7216 | case 0x1C: strcpy(insn[i],"DMULT"); type=MULTDIV; break; | |
7217 | case 0x1D: strcpy(insn[i],"DMULTU"); type=MULTDIV; break; | |
7218 | case 0x1E: strcpy(insn[i],"DDIV"); type=MULTDIV; break; | |
7219 | case 0x1F: strcpy(insn[i],"DDIVU"); type=MULTDIV; break; | |
7220 | case 0x2C: strcpy(insn[i],"DADD"); type=ALU; break; | |
7221 | case 0x2D: strcpy(insn[i],"DADDU"); type=ALU; break; | |
7222 | case 0x2E: strcpy(insn[i],"DSUB"); type=ALU; break; | |
7223 | case 0x2F: strcpy(insn[i],"DSUBU"); type=ALU; break; | |
57871462 | 7224 | case 0x38: strcpy(insn[i],"DSLL"); type=SHIFTIMM; break; |
7225 | case 0x3A: strcpy(insn[i],"DSRL"); type=SHIFTIMM; break; | |
7226 | case 0x3B: strcpy(insn[i],"DSRA"); type=SHIFTIMM; break; | |
7227 | case 0x3C: strcpy(insn[i],"DSLL32"); type=SHIFTIMM; break; | |
7228 | case 0x3E: strcpy(insn[i],"DSRL32"); type=SHIFTIMM; break; | |
7229 | case 0x3F: strcpy(insn[i],"DSRA32"); type=SHIFTIMM; break; | |
7f2607ea | 7230 | #endif |
57871462 | 7231 | } |
7232 | break; | |
7233 | case 0x01: strcpy(insn[i],"regimm"); type=NI; | |
7234 | op2=(source[i]>>16)&0x1f; | |
7235 | switch(op2) | |
7236 | { | |
7237 | case 0x00: strcpy(insn[i],"BLTZ"); type=SJUMP; break; | |
7238 | case 0x01: strcpy(insn[i],"BGEZ"); type=SJUMP; break; | |
630b122b | 7239 | //case 0x02: strcpy(insn[i],"BLTZL"); type=SJUMP; break; |
7240 | //case 0x03: strcpy(insn[i],"BGEZL"); type=SJUMP; break; | |
7241 | //case 0x08: strcpy(insn[i],"TGEI"); type=NI; break; | |
7242 | //case 0x09: strcpy(insn[i],"TGEIU"); type=NI; break; | |
7243 | //case 0x0A: strcpy(insn[i],"TLTI"); type=NI; break; | |
7244 | //case 0x0B: strcpy(insn[i],"TLTIU"); type=NI; break; | |
7245 | //case 0x0C: strcpy(insn[i],"TEQI"); type=NI; break; | |
7246 | //case 0x0E: strcpy(insn[i],"TNEI"); type=NI; break; | |
57871462 | 7247 | case 0x10: strcpy(insn[i],"BLTZAL"); type=SJUMP; break; |
7248 | case 0x11: strcpy(insn[i],"BGEZAL"); type=SJUMP; break; | |
630b122b | 7249 | //case 0x12: strcpy(insn[i],"BLTZALL"); type=SJUMP; break; |
7250 | //case 0x13: strcpy(insn[i],"BGEZALL"); type=SJUMP; break; | |
57871462 | 7251 | } |
7252 | break; | |
7253 | case 0x02: strcpy(insn[i],"J"); type=UJUMP; break; | |
7254 | case 0x03: strcpy(insn[i],"JAL"); type=UJUMP; break; | |
7255 | case 0x04: strcpy(insn[i],"BEQ"); type=CJUMP; break; | |
7256 | case 0x05: strcpy(insn[i],"BNE"); type=CJUMP; break; | |
7257 | case 0x06: strcpy(insn[i],"BLEZ"); type=CJUMP; break; | |
7258 | case 0x07: strcpy(insn[i],"BGTZ"); type=CJUMP; break; | |
7259 | case 0x08: strcpy(insn[i],"ADDI"); type=IMM16; break; | |
7260 | case 0x09: strcpy(insn[i],"ADDIU"); type=IMM16; break; | |
7261 | case 0x0A: strcpy(insn[i],"SLTI"); type=IMM16; break; | |
7262 | case 0x0B: strcpy(insn[i],"SLTIU"); type=IMM16; break; | |
7263 | case 0x0C: strcpy(insn[i],"ANDI"); type=IMM16; break; | |
7264 | case 0x0D: strcpy(insn[i],"ORI"); type=IMM16; break; | |
7265 | case 0x0E: strcpy(insn[i],"XORI"); type=IMM16; break; | |
7266 | case 0x0F: strcpy(insn[i],"LUI"); type=IMM16; break; | |
7267 | case 0x10: strcpy(insn[i],"cop0"); type=NI; | |
7268 | op2=(source[i]>>21)&0x1f; | |
7269 | switch(op2) | |
7270 | { | |
7271 | case 0x00: strcpy(insn[i],"MFC0"); type=COP0; break; | |
630b122b | 7272 | case 0x02: strcpy(insn[i],"CFC0"); type=COP0; break; |
57871462 | 7273 | case 0x04: strcpy(insn[i],"MTC0"); type=COP0; break; |
630b122b | 7274 | case 0x06: strcpy(insn[i],"CTC0"); type=COP0; break; |
7275 | case 0x10: strcpy(insn[i],"RFE"); type=COP0; break; | |
57871462 | 7276 | } |
7277 | break; | |
630b122b | 7278 | case 0x11: strcpy(insn[i],"cop1"); type=COP1; |
57871462 | 7279 | op2=(source[i]>>21)&0x1f; |
57871462 | 7280 | break; |
71e490c5 | 7281 | #if 0 |
57871462 | 7282 | case 0x14: strcpy(insn[i],"BEQL"); type=CJUMP; break; |
7283 | case 0x15: strcpy(insn[i],"BNEL"); type=CJUMP; break; | |
7284 | case 0x16: strcpy(insn[i],"BLEZL"); type=CJUMP; break; | |
7285 | case 0x17: strcpy(insn[i],"BGTZL"); type=CJUMP; break; | |
7286 | case 0x18: strcpy(insn[i],"DADDI"); type=IMM16; break; | |
7287 | case 0x19: strcpy(insn[i],"DADDIU"); type=IMM16; break; | |
7288 | case 0x1A: strcpy(insn[i],"LDL"); type=LOADLR; break; | |
7289 | case 0x1B: strcpy(insn[i],"LDR"); type=LOADLR; break; | |
996cc15d | 7290 | #endif |
57871462 | 7291 | case 0x20: strcpy(insn[i],"LB"); type=LOAD; break; |
7292 | case 0x21: strcpy(insn[i],"LH"); type=LOAD; break; | |
7293 | case 0x22: strcpy(insn[i],"LWL"); type=LOADLR; break; | |
7294 | case 0x23: strcpy(insn[i],"LW"); type=LOAD; break; | |
7295 | case 0x24: strcpy(insn[i],"LBU"); type=LOAD; break; | |
7296 | case 0x25: strcpy(insn[i],"LHU"); type=LOAD; break; | |
7297 | case 0x26: strcpy(insn[i],"LWR"); type=LOADLR; break; | |
71e490c5 | 7298 | #if 0 |
57871462 | 7299 | case 0x27: strcpy(insn[i],"LWU"); type=LOAD; break; |
64bd6f82 | 7300 | #endif |
57871462 | 7301 | case 0x28: strcpy(insn[i],"SB"); type=STORE; break; |
7302 | case 0x29: strcpy(insn[i],"SH"); type=STORE; break; | |
7303 | case 0x2A: strcpy(insn[i],"SWL"); type=STORELR; break; | |
7304 | case 0x2B: strcpy(insn[i],"SW"); type=STORE; break; | |
71e490c5 | 7305 | #if 0 |
57871462 | 7306 | case 0x2C: strcpy(insn[i],"SDL"); type=STORELR; break; |
7307 | case 0x2D: strcpy(insn[i],"SDR"); type=STORELR; break; | |
996cc15d | 7308 | #endif |
57871462 | 7309 | case 0x2E: strcpy(insn[i],"SWR"); type=STORELR; break; |
7310 | case 0x2F: strcpy(insn[i],"CACHE"); type=NOP; break; | |
7311 | case 0x30: strcpy(insn[i],"LL"); type=NI; break; | |
7312 | case 0x31: strcpy(insn[i],"LWC1"); type=C1LS; break; | |
71e490c5 | 7313 | #if 0 |
57871462 | 7314 | case 0x34: strcpy(insn[i],"LLD"); type=NI; break; |
7315 | case 0x35: strcpy(insn[i],"LDC1"); type=C1LS; break; | |
7316 | case 0x37: strcpy(insn[i],"LD"); type=LOAD; break; | |
996cc15d | 7317 | #endif |
57871462 | 7318 | case 0x38: strcpy(insn[i],"SC"); type=NI; break; |
7319 | case 0x39: strcpy(insn[i],"SWC1"); type=C1LS; break; | |
71e490c5 | 7320 | #if 0 |
57871462 | 7321 | case 0x3C: strcpy(insn[i],"SCD"); type=NI; break; |
7322 | case 0x3D: strcpy(insn[i],"SDC1"); type=C1LS; break; | |
7323 | case 0x3F: strcpy(insn[i],"SD"); type=STORE; break; | |
996cc15d | 7324 | #endif |
b9b61529 | 7325 | case 0x12: strcpy(insn[i],"COP2"); type=NI; |
7326 | op2=(source[i]>>21)&0x1f; | |
630b122b | 7327 | //if (op2 & 0x10) |
bedfea38 | 7328 | if (source[i]&0x3f) { // use this hack to support old savestates with patched gte insns |
c7abc864 | 7329 | if (gte_handlers[source[i]&0x3f]!=NULL) { |
bedfea38 | 7330 | if (gte_regnames[source[i]&0x3f]!=NULL) |
7331 | strcpy(insn[i],gte_regnames[source[i]&0x3f]); | |
7332 | else | |
7333 | snprintf(insn[i], sizeof(insn[i]), "COP2 %x", source[i]&0x3f); | |
c7abc864 | 7334 | type=C2OP; |
7335 | } | |
7336 | } | |
7337 | else switch(op2) | |
b9b61529 | 7338 | { |
7339 | case 0x00: strcpy(insn[i],"MFC2"); type=COP2; break; | |
7340 | case 0x02: strcpy(insn[i],"CFC2"); type=COP2; break; | |
7341 | case 0x04: strcpy(insn[i],"MTC2"); type=COP2; break; | |
7342 | case 0x06: strcpy(insn[i],"CTC2"); type=COP2; break; | |
b9b61529 | 7343 | } |
7344 | break; | |
7345 | case 0x32: strcpy(insn[i],"LWC2"); type=C2LS; break; | |
7346 | case 0x3A: strcpy(insn[i],"SWC2"); type=C2LS; break; | |
7347 | case 0x3B: strcpy(insn[i],"HLECALL"); type=HLECALL; break; | |
90ae6d4e | 7348 | default: strcpy(insn[i],"???"); type=NI; |
c43b5311 | 7349 | SysPrintf("NI %08x @%08x (%08x)\n", source[i], addr + i*4, addr); |
90ae6d4e | 7350 | break; |
57871462 | 7351 | } |
630b122b | 7352 | dops[i].itype=type; |
7353 | dops[i].opcode2=op2; | |
57871462 | 7354 | /* Get registers/immediates */ |
630b122b | 7355 | dops[i].lt1=0; |
bedfea38 | 7356 | gte_rs[i]=gte_rt[i]=0; |
57871462 | 7357 | switch(type) { |
7358 | case LOAD: | |
630b122b | 7359 | dops[i].rs1=(source[i]>>21)&0x1f; |
7360 | dops[i].rs2=0; | |
7361 | dops[i].rt1=(source[i]>>16)&0x1f; | |
7362 | dops[i].rt2=0; | |
57871462 | 7363 | imm[i]=(short)source[i]; |
7364 | break; | |
7365 | case STORE: | |
7366 | case STORELR: | |
630b122b | 7367 | dops[i].rs1=(source[i]>>21)&0x1f; |
7368 | dops[i].rs2=(source[i]>>16)&0x1f; | |
7369 | dops[i].rt1=0; | |
7370 | dops[i].rt2=0; | |
57871462 | 7371 | imm[i]=(short)source[i]; |
57871462 | 7372 | break; |
7373 | case LOADLR: | |
7374 | // LWL/LWR only load part of the register, | |
7375 | // therefore the target register must be treated as a source too | |
630b122b | 7376 | dops[i].rs1=(source[i]>>21)&0x1f; |
7377 | dops[i].rs2=(source[i]>>16)&0x1f; | |
7378 | dops[i].rt1=(source[i]>>16)&0x1f; | |
7379 | dops[i].rt2=0; | |
57871462 | 7380 | imm[i]=(short)source[i]; |
57871462 | 7381 | break; |
7382 | case IMM16: | |
630b122b | 7383 | if (op==0x0f) dops[i].rs1=0; // LUI instruction has no source register |
7384 | else dops[i].rs1=(source[i]>>21)&0x1f; | |
7385 | dops[i].rs2=0; | |
7386 | dops[i].rt1=(source[i]>>16)&0x1f; | |
7387 | dops[i].rt2=0; | |
57871462 | 7388 | if(op>=0x0c&&op<=0x0e) { // ANDI/ORI/XORI |
7389 | imm[i]=(unsigned short)source[i]; | |
7390 | }else{ | |
7391 | imm[i]=(short)source[i]; | |
7392 | } | |
57871462 | 7393 | break; |
7394 | case UJUMP: | |
630b122b | 7395 | dops[i].rs1=0; |
7396 | dops[i].rs2=0; | |
7397 | dops[i].rt1=0; | |
7398 | dops[i].rt2=0; | |
57871462 | 7399 | // The JAL instruction writes to r31. |
7400 | if (op&1) { | |
630b122b | 7401 | dops[i].rt1=31; |
57871462 | 7402 | } |
630b122b | 7403 | dops[i].rs2=CCREG; |
57871462 | 7404 | break; |
7405 | case RJUMP: | |
630b122b | 7406 | dops[i].rs1=(source[i]>>21)&0x1f; |
7407 | dops[i].rs2=0; | |
7408 | dops[i].rt1=0; | |
7409 | dops[i].rt2=0; | |
5067f341 | 7410 | // The JALR instruction writes to rd. |
57871462 | 7411 | if (op2&1) { |
630b122b | 7412 | dops[i].rt1=(source[i]>>11)&0x1f; |
57871462 | 7413 | } |
630b122b | 7414 | dops[i].rs2=CCREG; |
57871462 | 7415 | break; |
7416 | case CJUMP: | |
630b122b | 7417 | dops[i].rs1=(source[i]>>21)&0x1f; |
7418 | dops[i].rs2=(source[i]>>16)&0x1f; | |
7419 | dops[i].rt1=0; | |
7420 | dops[i].rt2=0; | |
57871462 | 7421 | if(op&2) { // BGTZ/BLEZ |
630b122b | 7422 | dops[i].rs2=0; |
57871462 | 7423 | } |
57871462 | 7424 | break; |
7425 | case SJUMP: | |
630b122b | 7426 | dops[i].rs1=(source[i]>>21)&0x1f; |
7427 | dops[i].rs2=CCREG; | |
7428 | dops[i].rt1=0; | |
7429 | dops[i].rt2=0; | |
57871462 | 7430 | if(op2&0x10) { // BxxAL |
630b122b | 7431 | dops[i].rt1=31; |
57871462 | 7432 | // NOTE: If the branch is not taken, r31 is still overwritten |
7433 | } | |
57871462 | 7434 | break; |
7435 | case ALU: | |
630b122b | 7436 | dops[i].rs1=(source[i]>>21)&0x1f; // source |
7437 | dops[i].rs2=(source[i]>>16)&0x1f; // subtract amount | |
7438 | dops[i].rt1=(source[i]>>11)&0x1f; // destination | |
7439 | dops[i].rt2=0; | |
57871462 | 7440 | break; |
7441 | case MULTDIV: | |
630b122b | 7442 | dops[i].rs1=(source[i]>>21)&0x1f; // source |
7443 | dops[i].rs2=(source[i]>>16)&0x1f; // divisor | |
7444 | dops[i].rt1=HIREG; | |
7445 | dops[i].rt2=LOREG; | |
57871462 | 7446 | break; |
7447 | case MOV: | |
630b122b | 7448 | dops[i].rs1=0; |
7449 | dops[i].rs2=0; | |
7450 | dops[i].rt1=0; | |
7451 | dops[i].rt2=0; | |
7452 | if(op2==0x10) dops[i].rs1=HIREG; // MFHI | |
7453 | if(op2==0x11) dops[i].rt1=HIREG; // MTHI | |
7454 | if(op2==0x12) dops[i].rs1=LOREG; // MFLO | |
7455 | if(op2==0x13) dops[i].rt1=LOREG; // MTLO | |
7456 | if((op2&0x1d)==0x10) dops[i].rt1=(source[i]>>11)&0x1f; // MFxx | |
7457 | if((op2&0x1d)==0x11) dops[i].rs1=(source[i]>>21)&0x1f; // MTxx | |
57871462 | 7458 | break; |
7459 | case SHIFT: | |
630b122b | 7460 | dops[i].rs1=(source[i]>>16)&0x1f; // target of shift |
7461 | dops[i].rs2=(source[i]>>21)&0x1f; // shift amount | |
7462 | dops[i].rt1=(source[i]>>11)&0x1f; // destination | |
7463 | dops[i].rt2=0; | |
57871462 | 7464 | break; |
7465 | case SHIFTIMM: | |
630b122b | 7466 | dops[i].rs1=(source[i]>>16)&0x1f; |
7467 | dops[i].rs2=0; | |
7468 | dops[i].rt1=(source[i]>>11)&0x1f; | |
7469 | dops[i].rt2=0; | |
57871462 | 7470 | imm[i]=(source[i]>>6)&0x1f; |
7471 | // DSxx32 instructions | |
7472 | if(op2>=0x3c) imm[i]|=0x20; | |
57871462 | 7473 | break; |
7474 | case COP0: | |
630b122b | 7475 | dops[i].rs1=0; |
7476 | dops[i].rs2=0; | |
7477 | dops[i].rt1=0; | |
7478 | dops[i].rt2=0; | |
7479 | if(op2==0||op2==2) dops[i].rt1=(source[i]>>16)&0x1F; // MFC0/CFC0 | |
7480 | if(op2==4||op2==6) dops[i].rs1=(source[i]>>16)&0x1F; // MTC0/CTC0 | |
7481 | if(op2==4&&((source[i]>>11)&0x1f)==12) dops[i].rt2=CSREG; // Status | |
7482 | if(op2==16) if((source[i]&0x3f)==0x18) dops[i].rs2=CCREG; // ERET | |
57871462 | 7483 | break; |
7484 | case COP1: | |
630b122b | 7485 | dops[i].rs1=0; |
7486 | dops[i].rs2=0; | |
7487 | dops[i].rt1=0; | |
7488 | dops[i].rt2=0; | |
7489 | if(op2<3) dops[i].rt1=(source[i]>>16)&0x1F; // MFC1/DMFC1/CFC1 | |
7490 | if(op2>3) dops[i].rs1=(source[i]>>16)&0x1F; // MTC1/DMTC1/CTC1 | |
7491 | dops[i].rs2=CSREG; | |
57871462 | 7492 | break; |
bedfea38 | 7493 | case COP2: |
630b122b | 7494 | dops[i].rs1=0; |
7495 | dops[i].rs2=0; | |
7496 | dops[i].rt1=0; | |
7497 | dops[i].rt2=0; | |
7498 | if(op2<3) dops[i].rt1=(source[i]>>16)&0x1F; // MFC2/CFC2 | |
7499 | if(op2>3) dops[i].rs1=(source[i]>>16)&0x1F; // MTC2/CTC2 | |
7500 | dops[i].rs2=CSREG; | |
bedfea38 | 7501 | int gr=(source[i]>>11)&0x1F; |
7502 | switch(op2) | |
7503 | { | |
7504 | case 0x00: gte_rs[i]=1ll<<gr; break; // MFC2 | |
7505 | case 0x04: gte_rt[i]=1ll<<gr; break; // MTC2 | |
0ff8c62c | 7506 | case 0x02: gte_rs[i]=1ll<<(gr+32); break; // CFC2 |
bedfea38 | 7507 | case 0x06: gte_rt[i]=1ll<<(gr+32); break; // CTC2 |
7508 | } | |
7509 | break; | |
57871462 | 7510 | case C1LS: |
630b122b | 7511 | dops[i].rs1=(source[i]>>21)&0x1F; |
7512 | dops[i].rs2=CSREG; | |
7513 | dops[i].rt1=0; | |
7514 | dops[i].rt2=0; | |
57871462 | 7515 | imm[i]=(short)source[i]; |
7516 | break; | |
b9b61529 | 7517 | case C2LS: |
630b122b | 7518 | dops[i].rs1=(source[i]>>21)&0x1F; |
7519 | dops[i].rs2=0; | |
7520 | dops[i].rt1=0; | |
7521 | dops[i].rt2=0; | |
b9b61529 | 7522 | imm[i]=(short)source[i]; |
bedfea38 | 7523 | if(op==0x32) gte_rt[i]=1ll<<((source[i]>>16)&0x1F); // LWC2 |
7524 | else gte_rs[i]=1ll<<((source[i]>>16)&0x1F); // SWC2 | |
7525 | break; | |
7526 | case C2OP: | |
630b122b | 7527 | dops[i].rs1=0; |
7528 | dops[i].rs2=0; | |
7529 | dops[i].rt1=0; | |
7530 | dops[i].rt2=0; | |
2167bef6 | 7531 | gte_rs[i]=gte_reg_reads[source[i]&0x3f]; |
7532 | gte_rt[i]=gte_reg_writes[source[i]&0x3f]; | |
7533 | gte_rt[i]|=1ll<<63; // every op changes flags | |
587a5b1c | 7534 | if((source[i]&0x3f)==GTE_MVMVA) { |
7535 | int v = (source[i] >> 15) & 3; | |
7536 | gte_rs[i]&=~0xe3fll; | |
7537 | if(v==3) gte_rs[i]|=0xe00ll; | |
7538 | else gte_rs[i]|=3ll<<(v*2); | |
7539 | } | |
b9b61529 | 7540 | break; |
57871462 | 7541 | case SYSCALL: |
7139f3c8 | 7542 | case HLECALL: |
1e973cb0 | 7543 | case INTCALL: |
630b122b | 7544 | dops[i].rs1=CCREG; |
7545 | dops[i].rs2=0; | |
7546 | dops[i].rt1=0; | |
7547 | dops[i].rt2=0; | |
57871462 | 7548 | break; |
7549 | default: | |
630b122b | 7550 | dops[i].rs1=0; |
7551 | dops[i].rs2=0; | |
7552 | dops[i].rt1=0; | |
7553 | dops[i].rt2=0; | |
57871462 | 7554 | } |
7555 | /* Calculate branch target addresses */ | |
7556 | if(type==UJUMP) | |
7557 | ba[i]=((start+i*4+4)&0xF0000000)|(((unsigned int)source[i]<<6)>>4); | |
630b122b | 7558 | else if(type==CJUMP&&dops[i].rs1==dops[i].rs2&&(op&1)) |
57871462 | 7559 | ba[i]=start+i*4+8; // Ignore never taken branch |
630b122b | 7560 | else if(type==SJUMP&&dops[i].rs1==0&&!(op2&1)) |
57871462 | 7561 | ba[i]=start+i*4+8; // Ignore never taken branch |
630b122b | 7562 | else if(type==CJUMP||type==SJUMP) |
57871462 | 7563 | ba[i]=start+i*4+4+((signed int)((unsigned int)source[i]<<16)>>14); |
7564 | else ba[i]=-1; | |
630b122b | 7565 | |
7566 | /* simplify always (not)taken branches */ | |
7567 | if (type == CJUMP && dops[i].rs1 == dops[i].rs2) { | |
7568 | dops[i].rs1 = dops[i].rs2 = 0; | |
7569 | if (!(op & 1)) { | |
7570 | dops[i].itype = type = UJUMP; | |
7571 | dops[i].rs2 = CCREG; | |
7572 | } | |
7573 | } | |
7574 | else if (type == SJUMP && dops[i].rs1 == 0 && (op2 & 1)) | |
7575 | dops[i].itype = type = UJUMP; | |
7576 | ||
7577 | dops[i].is_jump = (dops[i].itype == RJUMP || dops[i].itype == UJUMP || dops[i].itype == CJUMP || dops[i].itype == SJUMP); | |
7578 | dops[i].is_ujump = (dops[i].itype == RJUMP || dops[i].itype == UJUMP); // || (source[i] >> 16) == 0x1000 // beq r0,r0 | |
7579 | dops[i].is_load = (dops[i].itype == LOAD || dops[i].itype == LOADLR || op == 0x32); // LWC2 | |
7580 | dops[i].is_store = (dops[i].itype == STORE || dops[i].itype == STORELR || op == 0x3a); // SWC2 | |
7581 | ||
7582 | /* messy cases to just pass over to the interpreter */ | |
7583 | if (i > 0 && dops[i-1].is_jump) { | |
3e535354 | 7584 | int do_in_intrp=0; |
7585 | // branch in delay slot? | |
630b122b | 7586 | if (dops[i].is_jump) { |
3e535354 | 7587 | // don't handle first branch and call interpreter if it's hit |
c43b5311 | 7588 | SysPrintf("branch in delay slot @%08x (%08x)\n", addr + i*4, addr); |
3e535354 | 7589 | do_in_intrp=1; |
7590 | } | |
7591 | // basic load delay detection | |
630b122b | 7592 | else if((type==LOAD||type==LOADLR||type==COP0||type==COP2||type==C2LS)&&dops[i].rt1!=0) { |
3e535354 | 7593 | int t=(ba[i-1]-start)/4; |
630b122b | 7594 | if(0 <= t && t < i &&(dops[i].rt1==dops[t].rs1||dops[i].rt1==dops[t].rs2)&&dops[t].itype!=CJUMP&&dops[t].itype!=SJUMP) { |
3e535354 | 7595 | // jump target wants DS result - potential load delay effect |
c43b5311 | 7596 | SysPrintf("load delay @%08x (%08x)\n", addr + i*4, addr); |
3e535354 | 7597 | do_in_intrp=1; |
630b122b | 7598 | dops[t+1].bt=1; // expected return from interpreter |
3e535354 | 7599 | } |
630b122b | 7600 | else if(i>=2&&dops[i-2].rt1==2&&dops[i].rt1==2&&dops[i].rs1!=2&&dops[i].rs2!=2&&dops[i-1].rs1!=2&&dops[i-1].rs2!=2&& |
7601 | !(i>=3&&dops[i-3].is_jump)) { | |
3e535354 | 7602 | // v0 overwrite like this is a sign of trouble, bail out |
c43b5311 | 7603 | SysPrintf("v0 overwrite @%08x (%08x)\n", addr + i*4, addr); |
3e535354 | 7604 | do_in_intrp=1; |
7605 | } | |
7606 | } | |
3e535354 | 7607 | if(do_in_intrp) { |
630b122b | 7608 | dops[i-1].rs1=CCREG; |
7609 | dops[i-1].rs2=dops[i-1].rt1=dops[i-1].rt2=0; | |
26869094 | 7610 | ba[i-1]=-1; |
630b122b | 7611 | dops[i-1].itype=INTCALL; |
26869094 | 7612 | done=2; |
3e535354 | 7613 | i--; // don't compile the DS |
26869094 | 7614 | } |
3e535354 | 7615 | } |
630b122b | 7616 | |
3e535354 | 7617 | /* Is this the end of the block? */ |
630b122b | 7618 | if (i > 0 && dops[i-1].is_ujump) { |
7619 | if(dops[i-1].rt1==0) { // Continue past subroutine call (JAL) | |
1e973cb0 | 7620 | done=2; |
57871462 | 7621 | } |
7622 | else { | |
7623 | if(stop_after_jal) done=1; | |
7624 | // Stop on BREAK | |
7625 | if((source[i+1]&0xfc00003f)==0x0d) done=1; | |
7626 | } | |
7627 | // Don't recompile stuff that's already compiled | |
7628 | if(check_addr(start+i*4+4)) done=1; | |
7629 | // Don't get too close to the limit | |
7630 | if(i>MAXBLOCK/2) done=1; | |
7631 | } | |
630b122b | 7632 | if(dops[i].itype==SYSCALL&&stop_after_jal) done=1; |
7633 | if(dops[i].itype==HLECALL||dops[i].itype==INTCALL) done=2; | |
1e973cb0 | 7634 | if(done==2) { |
7635 | // Does the block continue due to a branch? | |
7636 | for(j=i-1;j>=0;j--) | |
7637 | { | |
2a706964 | 7638 | if(ba[j]==start+i*4) done=j=0; // Branch into delay slot |
1e973cb0 | 7639 | if(ba[j]==start+i*4+4) done=j=0; |
7640 | if(ba[j]==start+i*4+8) done=j=0; | |
7641 | } | |
7642 | } | |
75dec299 | 7643 | //assert(i<MAXBLOCK-1); |
57871462 | 7644 | if(start+i*4==pagelimit-4) done=1; |
7645 | assert(start+i*4<pagelimit); | |
7646 | if (i==MAXBLOCK-1) done=1; | |
7647 | // Stop if we're compiling junk | |
630b122b | 7648 | if(dops[i].itype==NI&&dops[i].opcode==0x11) { |
57871462 | 7649 | done=stop_after_jal=1; |
c43b5311 | 7650 | SysPrintf("Disabled speculative precompilation\n"); |
57871462 | 7651 | } |
7652 | } | |
7653 | slen=i; | |
630b122b | 7654 | if (dops[i-1].is_jump) { |
57871462 | 7655 | if(start+i*4==pagelimit) { |
630b122b | 7656 | dops[i-1].itype=SPAN; |
57871462 | 7657 | } |
7658 | } | |
7659 | assert(slen>0); | |
7660 | ||
630b122b | 7661 | apply_hacks(); |
7662 | ||
57871462 | 7663 | /* Pass 2 - Register dependencies and branch targets */ |
7664 | ||
7665 | unneeded_registers(0,slen-1,0); | |
9f51b4b9 | 7666 | |
57871462 | 7667 | /* Pass 3 - Register allocation */ |
7668 | ||
7669 | struct regstat current; // Current register allocations/status | |
57871462 | 7670 | current.dirty=0; |
7671 | current.u=unneeded_reg[0]; | |
57871462 | 7672 | clear_all_regs(current.regmap); |
7673 | alloc_reg(¤t,0,CCREG); | |
7674 | dirty_reg(¤t,CCREG); | |
7675 | current.isconst=0; | |
7676 | current.wasconst=0; | |
27727b63 | 7677 | current.waswritten=0; |
57871462 | 7678 | int ds=0; |
7679 | int cc=0; | |
5194fb95 | 7680 | int hr=-1; |
6ebf4adf | 7681 | |
57871462 | 7682 | if((u_int)addr&1) { |
7683 | // First instruction is delay slot | |
7684 | cc=-1; | |
630b122b | 7685 | dops[1].bt=1; |
57871462 | 7686 | ds=1; |
7687 | unneeded_reg[0]=1; | |
57871462 | 7688 | current.regmap[HOST_BTREG]=BTREG; |
7689 | } | |
9f51b4b9 | 7690 | |
57871462 | 7691 | for(i=0;i<slen;i++) |
7692 | { | |
630b122b | 7693 | if(dops[i].bt) |
57871462 | 7694 | { |
7695 | int hr; | |
7696 | for(hr=0;hr<HOST_REGS;hr++) | |
7697 | { | |
7698 | // Is this really necessary? | |
7699 | if(current.regmap[hr]==0) current.regmap[hr]=-1; | |
7700 | } | |
7701 | current.isconst=0; | |
27727b63 | 7702 | current.waswritten=0; |
57871462 | 7703 | } |
24385cae | 7704 | |
57871462 | 7705 | memcpy(regmap_pre[i],current.regmap,sizeof(current.regmap)); |
7706 | regs[i].wasconst=current.isconst; | |
57871462 | 7707 | regs[i].wasdirty=current.dirty; |
8575a877 | 7708 | regs[i].loadedconst=0; |
630b122b | 7709 | if (!dops[i].is_jump) { |
57871462 | 7710 | if(i+1<slen) { |
630b122b | 7711 | current.u=unneeded_reg[i+1]&~((1LL<<dops[i].rs1)|(1LL<<dops[i].rs2)); |
57871462 | 7712 | current.u|=1; |
57871462 | 7713 | } else { |
7714 | current.u=1; | |
57871462 | 7715 | } |
7716 | } else { | |
7717 | if(i+1<slen) { | |
630b122b | 7718 | current.u=branch_unneeded_reg[i]&~((1LL<<dops[i+1].rs1)|(1LL<<dops[i+1].rs2)); |
7719 | current.u&=~((1LL<<dops[i].rs1)|(1LL<<dops[i].rs2)); | |
57871462 | 7720 | current.u|=1; |
630b122b | 7721 | } else { SysPrintf("oops, branch at end of block with no delay slot\n");abort(); } |
57871462 | 7722 | } |
630b122b | 7723 | dops[i].is_ds=ds; |
57871462 | 7724 | if(ds) { |
7725 | ds=0; // Skip delay slot, already allocated as part of branch | |
7726 | // ...but we need to alloc it in case something jumps here | |
7727 | if(i+1<slen) { | |
7728 | current.u=branch_unneeded_reg[i-1]&unneeded_reg[i+1]; | |
57871462 | 7729 | }else{ |
7730 | current.u=branch_unneeded_reg[i-1]; | |
57871462 | 7731 | } |
630b122b | 7732 | current.u&=~((1LL<<dops[i].rs1)|(1LL<<dops[i].rs2)); |
57871462 | 7733 | current.u|=1; |
57871462 | 7734 | struct regstat temp; |
7735 | memcpy(&temp,¤t,sizeof(current)); | |
7736 | temp.wasdirty=temp.dirty; | |
57871462 | 7737 | // TODO: Take into account unconditional branches, as below |
7738 | delayslot_alloc(&temp,i); | |
7739 | memcpy(regs[i].regmap,temp.regmap,sizeof(temp.regmap)); | |
7740 | regs[i].wasdirty=temp.wasdirty; | |
57871462 | 7741 | regs[i].dirty=temp.dirty; |
57871462 | 7742 | regs[i].isconst=0; |
7743 | regs[i].wasconst=0; | |
7744 | current.isconst=0; | |
7745 | // Create entry (branch target) regmap | |
7746 | for(hr=0;hr<HOST_REGS;hr++) | |
7747 | { | |
7748 | int r=temp.regmap[hr]; | |
7749 | if(r>=0) { | |
7750 | if(r!=regmap_pre[i][hr]) { | |
7751 | regs[i].regmap_entry[hr]=-1; | |
7752 | } | |
7753 | else | |
7754 | { | |
630b122b | 7755 | assert(r < 64); |
57871462 | 7756 | if((current.u>>r)&1) { |
7757 | regs[i].regmap_entry[hr]=-1; | |
7758 | regs[i].regmap[hr]=-1; | |
7759 | //Don't clear regs in the delay slot as the branch might need them | |
7760 | //current.regmap[hr]=-1; | |
7761 | }else | |
7762 | regs[i].regmap_entry[hr]=r; | |
57871462 | 7763 | } |
7764 | } else { | |
7765 | // First instruction expects CCREG to be allocated | |
9f51b4b9 | 7766 | if(i==0&&hr==HOST_CCREG) |
57871462 | 7767 | regs[i].regmap_entry[hr]=CCREG; |
7768 | else | |
7769 | regs[i].regmap_entry[hr]=-1; | |
7770 | } | |
7771 | } | |
7772 | } | |
7773 | else { // Not delay slot | |
630b122b | 7774 | switch(dops[i].itype) { |
57871462 | 7775 | case UJUMP: |
7776 | //current.isconst=0; // DEBUG | |
7777 | //current.wasconst=0; // DEBUG | |
7778 | //regs[i].wasconst=0; // DEBUG | |
630b122b | 7779 | clear_const(¤t,dops[i].rt1); |
57871462 | 7780 | alloc_cc(¤t,i); |
7781 | dirty_reg(¤t,CCREG); | |
630b122b | 7782 | if (dops[i].rt1==31) { |
57871462 | 7783 | alloc_reg(¤t,i,31); |
7784 | dirty_reg(¤t,31); | |
630b122b | 7785 | //assert(dops[i+1].rs1!=31&&dops[i+1].rs2!=31); |
7786 | //assert(dops[i+1].rt1!=dops[i].rt1); | |
57871462 | 7787 | #ifdef REG_PREFETCH |
7788 | alloc_reg(¤t,i,PTEMP); | |
7789 | #endif | |
57871462 | 7790 | } |
630b122b | 7791 | dops[i].ooo=1; |
269bb29a | 7792 | delayslot_alloc(¤t,i+1); |
57871462 | 7793 | //current.isconst=0; // DEBUG |
7794 | ds=1; | |
7795 | //printf("i=%d, isconst=%x\n",i,current.isconst); | |
7796 | break; | |
7797 | case RJUMP: | |
7798 | //current.isconst=0; | |
7799 | //current.wasconst=0; | |
7800 | //regs[i].wasconst=0; | |
630b122b | 7801 | clear_const(¤t,dops[i].rs1); |
7802 | clear_const(¤t,dops[i].rt1); | |
57871462 | 7803 | alloc_cc(¤t,i); |
7804 | dirty_reg(¤t,CCREG); | |
630b122b | 7805 | if (!ds_writes_rjump_rs(i)) { |
7806 | alloc_reg(¤t,i,dops[i].rs1); | |
7807 | if (dops[i].rt1!=0) { | |
7808 | alloc_reg(¤t,i,dops[i].rt1); | |
7809 | dirty_reg(¤t,dops[i].rt1); | |
7810 | assert(dops[i+1].rs1!=dops[i].rt1&&dops[i+1].rs2!=dops[i].rt1); | |
7811 | assert(dops[i+1].rt1!=dops[i].rt1); | |
57871462 | 7812 | #ifdef REG_PREFETCH |
7813 | alloc_reg(¤t,i,PTEMP); | |
7814 | #endif | |
7815 | } | |
7816 | #ifdef USE_MINI_HT | |
630b122b | 7817 | if(dops[i].rs1==31) { // JALR |
57871462 | 7818 | alloc_reg(¤t,i,RHASH); |
57871462 | 7819 | alloc_reg(¤t,i,RHTBL); |
57871462 | 7820 | } |
7821 | #endif | |
7822 | delayslot_alloc(¤t,i+1); | |
7823 | } else { | |
7824 | // The delay slot overwrites our source register, | |
7825 | // allocate a temporary register to hold the old value. | |
7826 | current.isconst=0; | |
7827 | current.wasconst=0; | |
7828 | regs[i].wasconst=0; | |
7829 | delayslot_alloc(¤t,i+1); | |
7830 | current.isconst=0; | |
7831 | alloc_reg(¤t,i,RTEMP); | |
7832 | } | |
7833 | //current.isconst=0; // DEBUG | |
630b122b | 7834 | dops[i].ooo=1; |
57871462 | 7835 | ds=1; |
7836 | break; | |
7837 | case CJUMP: | |
7838 | //current.isconst=0; | |
7839 | //current.wasconst=0; | |
7840 | //regs[i].wasconst=0; | |
630b122b | 7841 | clear_const(¤t,dops[i].rs1); |
7842 | clear_const(¤t,dops[i].rs2); | |
7843 | if((dops[i].opcode&0x3E)==4) // BEQ/BNE | |
57871462 | 7844 | { |
7845 | alloc_cc(¤t,i); | |
7846 | dirty_reg(¤t,CCREG); | |
630b122b | 7847 | if(dops[i].rs1) alloc_reg(¤t,i,dops[i].rs1); |
7848 | if(dops[i].rs2) alloc_reg(¤t,i,dops[i].rs2); | |
7849 | if((dops[i].rs1&&(dops[i].rs1==dops[i+1].rt1||dops[i].rs1==dops[i+1].rt2))|| | |
7850 | (dops[i].rs2&&(dops[i].rs2==dops[i+1].rt1||dops[i].rs2==dops[i+1].rt2))) { | |
57871462 | 7851 | // The delay slot overwrites one of our conditions. |
7852 | // Allocate the branch condition registers instead. | |
57871462 | 7853 | current.isconst=0; |
7854 | current.wasconst=0; | |
7855 | regs[i].wasconst=0; | |
630b122b | 7856 | if(dops[i].rs1) alloc_reg(¤t,i,dops[i].rs1); |
7857 | if(dops[i].rs2) alloc_reg(¤t,i,dops[i].rs2); | |
57871462 | 7858 | } |
e1190b87 | 7859 | else |
7860 | { | |
630b122b | 7861 | dops[i].ooo=1; |
e1190b87 | 7862 | delayslot_alloc(¤t,i+1); |
7863 | } | |
57871462 | 7864 | } |
7865 | else | |
630b122b | 7866 | if((dops[i].opcode&0x3E)==6) // BLEZ/BGTZ |
57871462 | 7867 | { |
7868 | alloc_cc(¤t,i); | |
7869 | dirty_reg(¤t,CCREG); | |
630b122b | 7870 | alloc_reg(¤t,i,dops[i].rs1); |
7871 | if(dops[i].rs1&&(dops[i].rs1==dops[i+1].rt1||dops[i].rs1==dops[i+1].rt2)) { | |
57871462 | 7872 | // The delay slot overwrites one of our conditions. |
7873 | // Allocate the branch condition registers instead. | |
57871462 | 7874 | current.isconst=0; |
7875 | current.wasconst=0; | |
7876 | regs[i].wasconst=0; | |
630b122b | 7877 | if(dops[i].rs1) alloc_reg(¤t,i,dops[i].rs1); |
57871462 | 7878 | } |
e1190b87 | 7879 | else |
7880 | { | |
630b122b | 7881 | dops[i].ooo=1; |
e1190b87 | 7882 | delayslot_alloc(¤t,i+1); |
7883 | } | |
57871462 | 7884 | } |
7885 | else | |
7886 | // Don't alloc the delay slot yet because we might not execute it | |
630b122b | 7887 | if((dops[i].opcode&0x3E)==0x14) // BEQL/BNEL |
57871462 | 7888 | { |
7889 | current.isconst=0; | |
7890 | current.wasconst=0; | |
7891 | regs[i].wasconst=0; | |
7892 | alloc_cc(¤t,i); | |
7893 | dirty_reg(¤t,CCREG); | |
630b122b | 7894 | alloc_reg(¤t,i,dops[i].rs1); |
7895 | alloc_reg(¤t,i,dops[i].rs2); | |
57871462 | 7896 | } |
7897 | else | |
630b122b | 7898 | if((dops[i].opcode&0x3E)==0x16) // BLEZL/BGTZL |
57871462 | 7899 | { |
7900 | current.isconst=0; | |
7901 | current.wasconst=0; | |
7902 | regs[i].wasconst=0; | |
7903 | alloc_cc(¤t,i); | |
7904 | dirty_reg(¤t,CCREG); | |
630b122b | 7905 | alloc_reg(¤t,i,dops[i].rs1); |
57871462 | 7906 | } |
7907 | ds=1; | |
7908 | //current.isconst=0; | |
7909 | break; | |
7910 | case SJUMP: | |
7911 | //current.isconst=0; | |
7912 | //current.wasconst=0; | |
7913 | //regs[i].wasconst=0; | |
630b122b | 7914 | clear_const(¤t,dops[i].rs1); |
7915 | clear_const(¤t,dops[i].rt1); | |
7916 | //if((dops[i].opcode2&0x1E)==0x0) // BLTZ/BGEZ | |
7917 | if((dops[i].opcode2&0x0E)==0x0) // BLTZ/BGEZ | |
57871462 | 7918 | { |
7919 | alloc_cc(¤t,i); | |
7920 | dirty_reg(¤t,CCREG); | |
630b122b | 7921 | alloc_reg(¤t,i,dops[i].rs1); |
7922 | if (dops[i].rt1==31) { // BLTZAL/BGEZAL | |
57871462 | 7923 | alloc_reg(¤t,i,31); |
7924 | dirty_reg(¤t,31); | |
57871462 | 7925 | //#ifdef REG_PREFETCH |
7926 | //alloc_reg(¤t,i,PTEMP); | |
7927 | //#endif | |
57871462 | 7928 | } |
630b122b | 7929 | if((dops[i].rs1&&(dops[i].rs1==dops[i+1].rt1||dops[i].rs1==dops[i+1].rt2)) // The delay slot overwrites the branch condition. |
7930 | ||(dops[i].rt1==31&&(dops[i+1].rs1==31||dops[i+1].rs2==31||dops[i+1].rt1==31||dops[i+1].rt2==31))) { // DS touches $ra | |
57871462 | 7931 | // Allocate the branch condition registers instead. |
57871462 | 7932 | current.isconst=0; |
7933 | current.wasconst=0; | |
7934 | regs[i].wasconst=0; | |
630b122b | 7935 | if(dops[i].rs1) alloc_reg(¤t,i,dops[i].rs1); |
57871462 | 7936 | } |
e1190b87 | 7937 | else |
7938 | { | |
630b122b | 7939 | dops[i].ooo=1; |
e1190b87 | 7940 | delayslot_alloc(¤t,i+1); |
7941 | } | |
57871462 | 7942 | } |
7943 | else | |
7944 | // Don't alloc the delay slot yet because we might not execute it | |
630b122b | 7945 | if((dops[i].opcode2&0x1E)==0x2) // BLTZL/BGEZL |
57871462 | 7946 | { |
7947 | current.isconst=0; | |
7948 | current.wasconst=0; | |
7949 | regs[i].wasconst=0; | |
7950 | alloc_cc(¤t,i); | |
7951 | dirty_reg(¤t,CCREG); | |
630b122b | 7952 | alloc_reg(¤t,i,dops[i].rs1); |
57871462 | 7953 | } |
7954 | ds=1; | |
7955 | //current.isconst=0; | |
7956 | break; | |
57871462 | 7957 | case IMM16: |
7958 | imm16_alloc(¤t,i); | |
7959 | break; | |
7960 | case LOAD: | |
7961 | case LOADLR: | |
7962 | load_alloc(¤t,i); | |
7963 | break; | |
7964 | case STORE: | |
7965 | case STORELR: | |
7966 | store_alloc(¤t,i); | |
7967 | break; | |
7968 | case ALU: | |
7969 | alu_alloc(¤t,i); | |
7970 | break; | |
7971 | case SHIFT: | |
7972 | shift_alloc(¤t,i); | |
7973 | break; | |
7974 | case MULTDIV: | |
7975 | multdiv_alloc(¤t,i); | |
7976 | break; | |
7977 | case SHIFTIMM: | |
7978 | shiftimm_alloc(¤t,i); | |
7979 | break; | |
7980 | case MOV: | |
7981 | mov_alloc(¤t,i); | |
7982 | break; | |
7983 | case COP0: | |
7984 | cop0_alloc(¤t,i); | |
7985 | break; | |
7986 | case COP1: | |
630b122b | 7987 | break; |
b9b61529 | 7988 | case COP2: |
630b122b | 7989 | cop2_alloc(¤t,i); |
57871462 | 7990 | break; |
7991 | case C1LS: | |
7992 | c1ls_alloc(¤t,i); | |
7993 | break; | |
b9b61529 | 7994 | case C2LS: |
7995 | c2ls_alloc(¤t,i); | |
7996 | break; | |
7997 | case C2OP: | |
7998 | c2op_alloc(¤t,i); | |
7999 | break; | |
57871462 | 8000 | case SYSCALL: |
7139f3c8 | 8001 | case HLECALL: |
1e973cb0 | 8002 | case INTCALL: |
57871462 | 8003 | syscall_alloc(¤t,i); |
8004 | break; | |
8005 | case SPAN: | |
8006 | pagespan_alloc(¤t,i); | |
8007 | break; | |
8008 | } | |
9f51b4b9 | 8009 | |
57871462 | 8010 | // Create entry (branch target) regmap |
8011 | for(hr=0;hr<HOST_REGS;hr++) | |
8012 | { | |
581335b0 | 8013 | int r,or; |
57871462 | 8014 | r=current.regmap[hr]; |
8015 | if(r>=0) { | |
8016 | if(r!=regmap_pre[i][hr]) { | |
8017 | // TODO: delay slot (?) | |
8018 | or=get_reg(regmap_pre[i],r); // Get old mapping for this register | |
8019 | if(or<0||(r&63)>=TEMPREG){ | |
8020 | regs[i].regmap_entry[hr]=-1; | |
8021 | } | |
8022 | else | |
8023 | { | |
8024 | // Just move it to a different register | |
8025 | regs[i].regmap_entry[hr]=r; | |
8026 | // If it was dirty before, it's still dirty | |
8027 | if((regs[i].wasdirty>>or)&1) dirty_reg(¤t,r&63); | |
8028 | } | |
8029 | } | |
8030 | else | |
8031 | { | |
8032 | // Unneeded | |
8033 | if(r==0){ | |
8034 | regs[i].regmap_entry[hr]=0; | |
8035 | } | |
8036 | else | |
630b122b | 8037 | { |
8038 | assert(r<64); | |
57871462 | 8039 | if((current.u>>r)&1) { |
8040 | regs[i].regmap_entry[hr]=-1; | |
8041 | //regs[i].regmap[hr]=-1; | |
8042 | current.regmap[hr]=-1; | |
8043 | }else | |
8044 | regs[i].regmap_entry[hr]=r; | |
8045 | } | |
57871462 | 8046 | } |
8047 | } else { | |
8048 | // Branches expect CCREG to be allocated at the target | |
9f51b4b9 | 8049 | if(regmap_pre[i][hr]==CCREG) |
57871462 | 8050 | regs[i].regmap_entry[hr]=CCREG; |
8051 | else | |
8052 | regs[i].regmap_entry[hr]=-1; | |
8053 | } | |
8054 | } | |
8055 | memcpy(regs[i].regmap,current.regmap,sizeof(current.regmap)); | |
8056 | } | |
27727b63 | 8057 | |
630b122b | 8058 | if(i>0&&(dops[i-1].itype==STORE||dops[i-1].itype==STORELR||(dops[i-1].itype==C2LS&&dops[i-1].opcode==0x3a))&&(u_int)imm[i-1]<0x800) |
8059 | current.waswritten|=1<<dops[i-1].rs1; | |
8060 | current.waswritten&=~(1<<dops[i].rt1); | |
8061 | current.waswritten&=~(1<<dops[i].rt2); | |
8062 | if((dops[i].itype==STORE||dops[i].itype==STORELR||(dops[i].itype==C2LS&&dops[i].opcode==0x3a))&&(u_int)imm[i]>=0x800) | |
8063 | current.waswritten&=~(1<<dops[i].rs1); | |
27727b63 | 8064 | |
57871462 | 8065 | /* Branch post-alloc */ |
8066 | if(i>0) | |
8067 | { | |
57871462 | 8068 | current.wasdirty=current.dirty; |
630b122b | 8069 | switch(dops[i-1].itype) { |
57871462 | 8070 | case UJUMP: |
8071 | memcpy(&branch_regs[i-1],¤t,sizeof(current)); | |
8072 | branch_regs[i-1].isconst=0; | |
8073 | branch_regs[i-1].wasconst=0; | |
630b122b | 8074 | branch_regs[i-1].u=branch_unneeded_reg[i-1]&~((1LL<<dops[i-1].rs1)|(1LL<<dops[i-1].rs2)); |
57871462 | 8075 | alloc_cc(&branch_regs[i-1],i-1); |
8076 | dirty_reg(&branch_regs[i-1],CCREG); | |
630b122b | 8077 | if(dops[i-1].rt1==31) { // JAL |
57871462 | 8078 | alloc_reg(&branch_regs[i-1],i-1,31); |
8079 | dirty_reg(&branch_regs[i-1],31); | |
57871462 | 8080 | } |
8081 | memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap)); | |
630b122b | 8082 | memcpy(constmap[i],constmap[i-1],sizeof(constmap[i])); |
57871462 | 8083 | break; |
8084 | case RJUMP: | |
8085 | memcpy(&branch_regs[i-1],¤t,sizeof(current)); | |
8086 | branch_regs[i-1].isconst=0; | |
8087 | branch_regs[i-1].wasconst=0; | |
630b122b | 8088 | branch_regs[i-1].u=branch_unneeded_reg[i-1]&~((1LL<<dops[i-1].rs1)|(1LL<<dops[i-1].rs2)); |
57871462 | 8089 | alloc_cc(&branch_regs[i-1],i-1); |
8090 | dirty_reg(&branch_regs[i-1],CCREG); | |
630b122b | 8091 | alloc_reg(&branch_regs[i-1],i-1,dops[i-1].rs1); |
8092 | if(dops[i-1].rt1!=0) { // JALR | |
8093 | alloc_reg(&branch_regs[i-1],i-1,dops[i-1].rt1); | |
8094 | dirty_reg(&branch_regs[i-1],dops[i-1].rt1); | |
57871462 | 8095 | } |
8096 | #ifdef USE_MINI_HT | |
630b122b | 8097 | if(dops[i-1].rs1==31) { // JALR |
57871462 | 8098 | alloc_reg(&branch_regs[i-1],i-1,RHASH); |
57871462 | 8099 | alloc_reg(&branch_regs[i-1],i-1,RHTBL); |
57871462 | 8100 | } |
8101 | #endif | |
8102 | memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap)); | |
630b122b | 8103 | memcpy(constmap[i],constmap[i-1],sizeof(constmap[i])); |
57871462 | 8104 | break; |
8105 | case CJUMP: | |
630b122b | 8106 | if((dops[i-1].opcode&0x3E)==4) // BEQ/BNE |
57871462 | 8107 | { |
8108 | alloc_cc(¤t,i-1); | |
8109 | dirty_reg(¤t,CCREG); | |
630b122b | 8110 | if((dops[i-1].rs1&&(dops[i-1].rs1==dops[i].rt1||dops[i-1].rs1==dops[i].rt2))|| |
8111 | (dops[i-1].rs2&&(dops[i-1].rs2==dops[i].rt1||dops[i-1].rs2==dops[i].rt2))) { | |
57871462 | 8112 | // The delay slot overwrote one of our conditions |
8113 | // Delay slot goes after the test (in order) | |
630b122b | 8114 | current.u=branch_unneeded_reg[i-1]&~((1LL<<dops[i].rs1)|(1LL<<dops[i].rs2)); |
57871462 | 8115 | current.u|=1; |
57871462 | 8116 | delayslot_alloc(¤t,i); |
8117 | current.isconst=0; | |
8118 | } | |
8119 | else | |
8120 | { | |
630b122b | 8121 | current.u=branch_unneeded_reg[i-1]&~((1LL<<dops[i-1].rs1)|(1LL<<dops[i-1].rs2)); |
57871462 | 8122 | // Alloc the branch condition registers |
630b122b | 8123 | if(dops[i-1].rs1) alloc_reg(¤t,i-1,dops[i-1].rs1); |
8124 | if(dops[i-1].rs2) alloc_reg(¤t,i-1,dops[i-1].rs2); | |
57871462 | 8125 | } |
8126 | memcpy(&branch_regs[i-1],¤t,sizeof(current)); | |
8127 | branch_regs[i-1].isconst=0; | |
8128 | branch_regs[i-1].wasconst=0; | |
8129 | memcpy(&branch_regs[i-1].regmap_entry,¤t.regmap,sizeof(current.regmap)); | |
630b122b | 8130 | memcpy(constmap[i],constmap[i-1],sizeof(constmap[i])); |
57871462 | 8131 | } |
8132 | else | |
630b122b | 8133 | if((dops[i-1].opcode&0x3E)==6) // BLEZ/BGTZ |
57871462 | 8134 | { |
8135 | alloc_cc(¤t,i-1); | |
8136 | dirty_reg(¤t,CCREG); | |
630b122b | 8137 | if(dops[i-1].rs1==dops[i].rt1||dops[i-1].rs1==dops[i].rt2) { |
57871462 | 8138 | // The delay slot overwrote the branch condition |
8139 | // Delay slot goes after the test (in order) | |
630b122b | 8140 | current.u=branch_unneeded_reg[i-1]&~((1LL<<dops[i].rs1)|(1LL<<dops[i].rs2)); |
57871462 | 8141 | current.u|=1; |
57871462 | 8142 | delayslot_alloc(¤t,i); |
8143 | current.isconst=0; | |
8144 | } | |
8145 | else | |
8146 | { | |
630b122b | 8147 | current.u=branch_unneeded_reg[i-1]&~(1LL<<dops[i-1].rs1); |
57871462 | 8148 | // Alloc the branch condition register |
630b122b | 8149 | alloc_reg(¤t,i-1,dops[i-1].rs1); |
57871462 | 8150 | } |
8151 | memcpy(&branch_regs[i-1],¤t,sizeof(current)); | |
8152 | branch_regs[i-1].isconst=0; | |
8153 | branch_regs[i-1].wasconst=0; | |
8154 | memcpy(&branch_regs[i-1].regmap_entry,¤t.regmap,sizeof(current.regmap)); | |
630b122b | 8155 | memcpy(constmap[i],constmap[i-1],sizeof(constmap[i])); |
57871462 | 8156 | } |
8157 | else | |
8158 | // Alloc the delay slot in case the branch is taken | |
630b122b | 8159 | if((dops[i-1].opcode&0x3E)==0x14) // BEQL/BNEL |
57871462 | 8160 | { |
8161 | memcpy(&branch_regs[i-1],¤t,sizeof(current)); | |
630b122b | 8162 | branch_regs[i-1].u=(branch_unneeded_reg[i-1]&~((1LL<<dops[i].rs1)|(1LL<<dops[i].rs2)|(1LL<<dops[i].rt1)|(1LL<<dops[i].rt2)))|1; |
57871462 | 8163 | alloc_cc(&branch_regs[i-1],i); |
8164 | dirty_reg(&branch_regs[i-1],CCREG); | |
8165 | delayslot_alloc(&branch_regs[i-1],i); | |
8166 | branch_regs[i-1].isconst=0; | |
8167 | alloc_reg(¤t,i,CCREG); // Not taken path | |
8168 | dirty_reg(¤t,CCREG); | |
8169 | memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap)); | |
8170 | } | |
8171 | else | |
630b122b | 8172 | if((dops[i-1].opcode&0x3E)==0x16) // BLEZL/BGTZL |
57871462 | 8173 | { |
8174 | memcpy(&branch_regs[i-1],¤t,sizeof(current)); | |
630b122b | 8175 | branch_regs[i-1].u=(branch_unneeded_reg[i-1]&~((1LL<<dops[i].rs1)|(1LL<<dops[i].rs2)|(1LL<<dops[i].rt1)|(1LL<<dops[i].rt2)))|1; |
57871462 | 8176 | alloc_cc(&branch_regs[i-1],i); |
8177 | dirty_reg(&branch_regs[i-1],CCREG); | |
8178 | delayslot_alloc(&branch_regs[i-1],i); | |
8179 | branch_regs[i-1].isconst=0; | |
8180 | alloc_reg(¤t,i,CCREG); // Not taken path | |
8181 | dirty_reg(¤t,CCREG); | |
8182 | memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap)); | |
8183 | } | |
8184 | break; | |
8185 | case SJUMP: | |
630b122b | 8186 | //if((dops[i-1].opcode2&0x1E)==0) // BLTZ/BGEZ |
8187 | if((dops[i-1].opcode2&0x0E)==0) // BLTZ/BGEZ | |
57871462 | 8188 | { |
8189 | alloc_cc(¤t,i-1); | |
8190 | dirty_reg(¤t,CCREG); | |
630b122b | 8191 | if(dops[i-1].rs1==dops[i].rt1||dops[i-1].rs1==dops[i].rt2) { |
57871462 | 8192 | // The delay slot overwrote the branch condition |
8193 | // Delay slot goes after the test (in order) | |
630b122b | 8194 | current.u=branch_unneeded_reg[i-1]&~((1LL<<dops[i].rs1)|(1LL<<dops[i].rs2)); |
57871462 | 8195 | current.u|=1; |
57871462 | 8196 | delayslot_alloc(¤t,i); |
8197 | current.isconst=0; | |
8198 | } | |
8199 | else | |
8200 | { | |
630b122b | 8201 | current.u=branch_unneeded_reg[i-1]&~(1LL<<dops[i-1].rs1); |
57871462 | 8202 | // Alloc the branch condition register |
630b122b | 8203 | alloc_reg(¤t,i-1,dops[i-1].rs1); |
57871462 | 8204 | } |
8205 | memcpy(&branch_regs[i-1],¤t,sizeof(current)); | |
8206 | branch_regs[i-1].isconst=0; | |
8207 | branch_regs[i-1].wasconst=0; | |
8208 | memcpy(&branch_regs[i-1].regmap_entry,¤t.regmap,sizeof(current.regmap)); | |
630b122b | 8209 | memcpy(constmap[i],constmap[i-1],sizeof(constmap[i])); |
57871462 | 8210 | } |
8211 | else | |
8212 | // Alloc the delay slot in case the branch is taken | |
630b122b | 8213 | if((dops[i-1].opcode2&0x1E)==2) // BLTZL/BGEZL |
57871462 | 8214 | { |
8215 | memcpy(&branch_regs[i-1],¤t,sizeof(current)); | |
630b122b | 8216 | branch_regs[i-1].u=(branch_unneeded_reg[i-1]&~((1LL<<dops[i].rs1)|(1LL<<dops[i].rs2)|(1LL<<dops[i].rt1)|(1LL<<dops[i].rt2)))|1; |
57871462 | 8217 | alloc_cc(&branch_regs[i-1],i); |
8218 | dirty_reg(&branch_regs[i-1],CCREG); | |
8219 | delayslot_alloc(&branch_regs[i-1],i); | |
8220 | branch_regs[i-1].isconst=0; | |
8221 | alloc_reg(¤t,i,CCREG); // Not taken path | |
8222 | dirty_reg(¤t,CCREG); | |
8223 | memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap)); | |
8224 | } | |
8225 | // FIXME: BLTZAL/BGEZAL | |
630b122b | 8226 | if(dops[i-1].opcode2&0x10) { // BxxZAL |
57871462 | 8227 | alloc_reg(&branch_regs[i-1],i-1,31); |
8228 | dirty_reg(&branch_regs[i-1],31); | |
57871462 | 8229 | } |
8230 | break; | |
8231 | } | |
8232 | ||
630b122b | 8233 | if (dops[i-1].is_ujump) |
57871462 | 8234 | { |
630b122b | 8235 | if(dops[i-1].rt1==31) // JAL/JALR |
57871462 | 8236 | { |
8237 | // Subroutine call will return here, don't alloc any registers | |
57871462 | 8238 | current.dirty=0; |
8239 | clear_all_regs(current.regmap); | |
8240 | alloc_reg(¤t,i,CCREG); | |
8241 | dirty_reg(¤t,CCREG); | |
8242 | } | |
8243 | else if(i+1<slen) | |
8244 | { | |
8245 | // Internal branch will jump here, match registers to caller | |
57871462 | 8246 | current.dirty=0; |
8247 | clear_all_regs(current.regmap); | |
8248 | alloc_reg(¤t,i,CCREG); | |
8249 | dirty_reg(¤t,CCREG); | |
8250 | for(j=i-1;j>=0;j--) | |
8251 | { | |
8252 | if(ba[j]==start+i*4+4) { | |
8253 | memcpy(current.regmap,branch_regs[j].regmap,sizeof(current.regmap)); | |
57871462 | 8254 | current.dirty=branch_regs[j].dirty; |
8255 | break; | |
8256 | } | |
8257 | } | |
8258 | while(j>=0) { | |
8259 | if(ba[j]==start+i*4+4) { | |
8260 | for(hr=0;hr<HOST_REGS;hr++) { | |
8261 | if(current.regmap[hr]!=branch_regs[j].regmap[hr]) { | |
8262 | current.regmap[hr]=-1; | |
8263 | } | |
57871462 | 8264 | current.dirty&=branch_regs[j].dirty; |
8265 | } | |
8266 | } | |
8267 | j--; | |
8268 | } | |
8269 | } | |
8270 | } | |
8271 | } | |
8272 | ||
8273 | // Count cycles in between branches | |
630b122b | 8274 | ccadj[i] = CLOCK_ADJUST(cc); |
8275 | if (i > 0 && (dops[i-1].is_jump || dops[i].itype == SYSCALL || dops[i].itype == HLECALL)) | |
57871462 | 8276 | { |
8277 | cc=0; | |
8278 | } | |
71e490c5 | 8279 | #if !defined(DRC_DBG) |
630b122b | 8280 | else if(dops[i].itype==C2OP&>e_cycletab[source[i]&0x3f]>2) |
fb407447 | 8281 | { |
630b122b | 8282 | // this should really be removed since the real stalls have been implemented, |
8283 | // but doing so causes sizeable perf regression against the older version | |
8284 | u_int gtec = gte_cycletab[source[i] & 0x3f]; | |
8285 | cc += HACK_ENABLED(NDHACK_NO_STALLS) ? gtec/2 : 2; | |
fb407447 | 8286 | } |
630b122b | 8287 | else if(i>1&&dops[i].itype==STORE&&dops[i-1].itype==STORE&&dops[i-2].itype==STORE&&!dops[i].bt) |
5fdcbb5a | 8288 | { |
8289 | cc+=4; | |
8290 | } | |
630b122b | 8291 | else if(dops[i].itype==C2LS) |
fb407447 | 8292 | { |
630b122b | 8293 | // same as with C2OP |
8294 | cc += HACK_ENABLED(NDHACK_NO_STALLS) ? 4 : 2; | |
fb407447 | 8295 | } |
8296 | #endif | |
57871462 | 8297 | else |
8298 | { | |
8299 | cc++; | |
8300 | } | |
8301 | ||
630b122b | 8302 | if(!dops[i].is_ds) { |
57871462 | 8303 | regs[i].dirty=current.dirty; |
8304 | regs[i].isconst=current.isconst; | |
630b122b | 8305 | memcpy(constmap[i],current_constmap,sizeof(constmap[i])); |
57871462 | 8306 | } |
8307 | for(hr=0;hr<HOST_REGS;hr++) { | |
8308 | if(hr!=EXCLUDE_REG&®s[i].regmap[hr]>=0) { | |
8309 | if(regmap_pre[i][hr]!=regs[i].regmap[hr]) { | |
8310 | regs[i].wasconst&=~(1<<hr); | |
8311 | } | |
8312 | } | |
8313 | } | |
8314 | if(current.regmap[HOST_BTREG]==BTREG) current.regmap[HOST_BTREG]=-1; | |
27727b63 | 8315 | regs[i].waswritten=current.waswritten; |
57871462 | 8316 | } |
9f51b4b9 | 8317 | |
57871462 | 8318 | /* Pass 4 - Cull unused host registers */ |
9f51b4b9 | 8319 | |
57871462 | 8320 | uint64_t nr=0; |
9f51b4b9 | 8321 | |
57871462 | 8322 | for (i=slen-1;i>=0;i--) |
8323 | { | |
8324 | int hr; | |
630b122b | 8325 | if(dops[i].is_jump) |
57871462 | 8326 | { |
8327 | if(ba[i]<start || ba[i]>=(start+slen*4)) | |
8328 | { | |
8329 | // Branch out of this block, don't need anything | |
8330 | nr=0; | |
8331 | } | |
8332 | else | |
8333 | { | |
8334 | // Internal branch | |
8335 | // Need whatever matches the target | |
8336 | nr=0; | |
8337 | int t=(ba[i]-start)>>2; | |
8338 | for(hr=0;hr<HOST_REGS;hr++) | |
8339 | { | |
8340 | if(regs[i].regmap_entry[hr]>=0) { | |
8341 | if(regs[i].regmap_entry[hr]==regs[t].regmap_entry[hr]) nr|=1<<hr; | |
8342 | } | |
8343 | } | |
8344 | } | |
8345 | // Conditional branch may need registers for following instructions | |
630b122b | 8346 | if (!dops[i].is_ujump) |
57871462 | 8347 | { |
8348 | if(i<slen-2) { | |
8349 | nr|=needed_reg[i+2]; | |
8350 | for(hr=0;hr<HOST_REGS;hr++) | |
8351 | { | |
8352 | if(regmap_pre[i+2][hr]>=0&&get_reg(regs[i+2].regmap_entry,regmap_pre[i+2][hr])<0) nr&=~(1<<hr); | |
8353 | //if((regmap_entry[i+2][hr])>=0) if(!((nr>>hr)&1)) printf("%x-bogus(%d=%d)\n",start+i*4,hr,regmap_entry[i+2][hr]); | |
8354 | } | |
8355 | } | |
8356 | } | |
8357 | // Don't need stuff which is overwritten | |
f5955059 | 8358 | //if(regs[i].regmap[hr]!=regmap_pre[i][hr]) nr&=~(1<<hr); |
8359 | //if(regs[i].regmap[hr]<0) nr&=~(1<<hr); | |
57871462 | 8360 | // Merge in delay slot |
8361 | for(hr=0;hr<HOST_REGS;hr++) | |
8362 | { | |
630b122b | 8363 | if(dops[i+1].rt1&&dops[i+1].rt1==(regs[i].regmap[hr]&63)) nr&=~(1<<hr); |
8364 | if(dops[i+1].rt2&&dops[i+1].rt2==(regs[i].regmap[hr]&63)) nr&=~(1<<hr); | |
8365 | if(dops[i+1].rs1==regmap_pre[i][hr]) nr|=1<<hr; | |
8366 | if(dops[i+1].rs2==regmap_pre[i][hr]) nr|=1<<hr; | |
8367 | if(dops[i+1].rs1==regs[i].regmap_entry[hr]) nr|=1<<hr; | |
8368 | if(dops[i+1].rs2==regs[i].regmap_entry[hr]) nr|=1<<hr; | |
8369 | if(ram_offset && (dops[i+1].is_load || dops[i+1].is_store)) { | |
8370 | if(regmap_pre[i][hr]==ROREG) nr|=1<<hr; | |
8371 | if(regs[i].regmap_entry[hr]==ROREG) nr|=1<<hr; | |
8372 | } | |
8373 | if(dops[i+1].is_store) { | |
57871462 | 8374 | if(regmap_pre[i][hr]==INVCP) nr|=1<<hr; |
8375 | if(regs[i].regmap_entry[hr]==INVCP) nr|=1<<hr; | |
8376 | } | |
8377 | } | |
8378 | } | |
630b122b | 8379 | else if(dops[i].itype==SYSCALL||dops[i].itype==HLECALL||dops[i].itype==INTCALL) |
57871462 | 8380 | { |
8381 | // SYSCALL instruction (software interrupt) | |
8382 | nr=0; | |
8383 | } | |
630b122b | 8384 | else if(dops[i].itype==COP0 && (source[i]&0x3f)==0x18) |
57871462 | 8385 | { |
8386 | // ERET instruction (return from interrupt) | |
8387 | nr=0; | |
8388 | } | |
8389 | else // Non-branch | |
8390 | { | |
8391 | if(i<slen-1) { | |
8392 | for(hr=0;hr<HOST_REGS;hr++) { | |
8393 | if(regmap_pre[i+1][hr]>=0&&get_reg(regs[i+1].regmap_entry,regmap_pre[i+1][hr])<0) nr&=~(1<<hr); | |
8394 | if(regs[i].regmap[hr]!=regmap_pre[i+1][hr]) nr&=~(1<<hr); | |
8395 | if(regs[i].regmap[hr]!=regmap_pre[i][hr]) nr&=~(1<<hr); | |
8396 | if(regs[i].regmap[hr]<0) nr&=~(1<<hr); | |
8397 | } | |
8398 | } | |
8399 | } | |
8400 | for(hr=0;hr<HOST_REGS;hr++) | |
8401 | { | |
8402 | // Overwritten registers are not needed | |
630b122b | 8403 | if(dops[i].rt1&&dops[i].rt1==(regs[i].regmap[hr]&63)) nr&=~(1<<hr); |
8404 | if(dops[i].rt2&&dops[i].rt2==(regs[i].regmap[hr]&63)) nr&=~(1<<hr); | |
57871462 | 8405 | if(FTEMP==(regs[i].regmap[hr]&63)) nr&=~(1<<hr); |
8406 | // Source registers are needed | |
630b122b | 8407 | if(dops[i].rs1==regmap_pre[i][hr]) nr|=1<<hr; |
8408 | if(dops[i].rs2==regmap_pre[i][hr]) nr|=1<<hr; | |
8409 | if(dops[i].rs1==regs[i].regmap_entry[hr]) nr|=1<<hr; | |
8410 | if(dops[i].rs2==regs[i].regmap_entry[hr]) nr|=1<<hr; | |
8411 | if(ram_offset && (dops[i].is_load || dops[i].is_store)) { | |
8412 | if(regmap_pre[i][hr]==ROREG) nr|=1<<hr; | |
8413 | if(regs[i].regmap_entry[hr]==ROREG) nr|=1<<hr; | |
8414 | } | |
8415 | if(dops[i].is_store) { | |
57871462 | 8416 | if(regmap_pre[i][hr]==INVCP) nr|=1<<hr; |
8417 | if(regs[i].regmap_entry[hr]==INVCP) nr|=1<<hr; | |
8418 | } | |
8419 | // Don't store a register immediately after writing it, | |
8420 | // may prevent dual-issue. | |
8421 | // But do so if this is a branch target, otherwise we | |
8422 | // might have to load the register before the branch. | |
630b122b | 8423 | if(i>0&&!dops[i].bt&&((regs[i].wasdirty>>hr)&1)) { |
8424 | if((regmap_pre[i][hr]>0&&!((unneeded_reg[i]>>regmap_pre[i][hr])&1))) { | |
8425 | if(dops[i-1].rt1==(regmap_pre[i][hr]&63)) nr|=1<<hr; | |
8426 | if(dops[i-1].rt2==(regmap_pre[i][hr]&63)) nr|=1<<hr; | |
57871462 | 8427 | } |
630b122b | 8428 | if((regs[i].regmap_entry[hr]>0&&!((unneeded_reg[i]>>regs[i].regmap_entry[hr])&1))) { |
8429 | if(dops[i-1].rt1==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr; | |
8430 | if(dops[i-1].rt2==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr; | |
57871462 | 8431 | } |
8432 | } | |
8433 | } | |
8434 | // Cycle count is needed at branches. Assume it is needed at the target too. | |
630b122b | 8435 | if(i==0||dops[i].bt||dops[i].itype==CJUMP||dops[i].itype==SPAN) { |
57871462 | 8436 | if(regmap_pre[i][HOST_CCREG]==CCREG) nr|=1<<HOST_CCREG; |
8437 | if(regs[i].regmap_entry[HOST_CCREG]==CCREG) nr|=1<<HOST_CCREG; | |
8438 | } | |
8439 | // Save it | |
8440 | needed_reg[i]=nr; | |
9f51b4b9 | 8441 | |
57871462 | 8442 | // Deallocate unneeded registers |
8443 | for(hr=0;hr<HOST_REGS;hr++) | |
8444 | { | |
8445 | if(!((nr>>hr)&1)) { | |
8446 | if(regs[i].regmap_entry[hr]!=CCREG) regs[i].regmap_entry[hr]=-1; | |
630b122b | 8447 | if(dops[i].is_jump) |
57871462 | 8448 | { |
630b122b | 8449 | int map1 = 0, map2 = 0, temp = 0; // or -1 ?? |
8450 | if (dops[i+1].is_load || dops[i+1].is_store) | |
8451 | map1 = ROREG; | |
8452 | if (dops[i+1].is_store) | |
8453 | map2 = INVCP; | |
8454 | if(dops[i+1].itype==LOADLR || dops[i+1].itype==STORELR || dops[i+1].itype==C2LS) | |
8455 | temp = FTEMP; | |
8456 | if((regs[i].regmap[hr]&63)!=dops[i].rs1 && (regs[i].regmap[hr]&63)!=dops[i].rs2 && | |
8457 | (regs[i].regmap[hr]&63)!=dops[i].rt1 && (regs[i].regmap[hr]&63)!=dops[i].rt2 && | |
8458 | (regs[i].regmap[hr]&63)!=dops[i+1].rt1 && (regs[i].regmap[hr]&63)!=dops[i+1].rt2 && | |
8459 | regs[i].regmap[hr]!=dops[i+1].rs1 && regs[i].regmap[hr]!=dops[i+1].rs2 && | |
57871462 | 8460 | (regs[i].regmap[hr]&63)!=temp && regs[i].regmap[hr]!=PTEMP && |
8461 | regs[i].regmap[hr]!=RHASH && regs[i].regmap[hr]!=RHTBL && | |
8462 | regs[i].regmap[hr]!=RTEMP && regs[i].regmap[hr]!=CCREG && | |
630b122b | 8463 | regs[i].regmap[hr]!=map1 && regs[i].regmap[hr]!=map2) |
57871462 | 8464 | { |
8465 | regs[i].regmap[hr]=-1; | |
8466 | regs[i].isconst&=~(1<<hr); | |
630b122b | 8467 | if((branch_regs[i].regmap[hr]&63)!=dops[i].rs1 && (branch_regs[i].regmap[hr]&63)!=dops[i].rs2 && |
8468 | (branch_regs[i].regmap[hr]&63)!=dops[i].rt1 && (branch_regs[i].regmap[hr]&63)!=dops[i].rt2 && | |
8469 | (branch_regs[i].regmap[hr]&63)!=dops[i+1].rt1 && (branch_regs[i].regmap[hr]&63)!=dops[i+1].rt2 && | |
8470 | branch_regs[i].regmap[hr]!=dops[i+1].rs1 && branch_regs[i].regmap[hr]!=dops[i+1].rs2 && | |
57871462 | 8471 | (branch_regs[i].regmap[hr]&63)!=temp && branch_regs[i].regmap[hr]!=PTEMP && |
8472 | branch_regs[i].regmap[hr]!=RHASH && branch_regs[i].regmap[hr]!=RHTBL && | |
8473 | branch_regs[i].regmap[hr]!=RTEMP && branch_regs[i].regmap[hr]!=CCREG && | |
630b122b | 8474 | branch_regs[i].regmap[hr]!=map1 && branch_regs[i].regmap[hr]!=map2) |
57871462 | 8475 | { |
8476 | branch_regs[i].regmap[hr]=-1; | |
8477 | branch_regs[i].regmap_entry[hr]=-1; | |
630b122b | 8478 | if (!dops[i].is_ujump) |
57871462 | 8479 | { |
630b122b | 8480 | if (i < slen-2) { |
57871462 | 8481 | regmap_pre[i+2][hr]=-1; |
79c75f1b | 8482 | regs[i+2].wasconst&=~(1<<hr); |
57871462 | 8483 | } |
8484 | } | |
8485 | } | |
8486 | } | |
8487 | } | |
8488 | else | |
8489 | { | |
8490 | // Non-branch | |
8491 | if(i>0) | |
8492 | { | |
630b122b | 8493 | int map1 = -1, map2 = -1, temp=-1; |
8494 | if (dops[i].is_load || dops[i].is_store) | |
8495 | map1 = ROREG; | |
8496 | if (dops[i].is_store) | |
8497 | map2 = INVCP; | |
8498 | if (dops[i].itype==LOADLR || dops[i].itype==STORELR || dops[i].itype==C2LS) | |
8499 | temp = FTEMP; | |
8500 | if((regs[i].regmap[hr]&63)!=dops[i].rt1 && (regs[i].regmap[hr]&63)!=dops[i].rt2 && | |
8501 | regs[i].regmap[hr]!=dops[i].rs1 && regs[i].regmap[hr]!=dops[i].rs2 && | |
8502 | (regs[i].regmap[hr]&63)!=temp && regs[i].regmap[hr]!=map1 && regs[i].regmap[hr]!=map2 && | |
8503 | //(dops[i].itype!=SPAN||regs[i].regmap[hr]!=CCREG) | |
8504 | regs[i].regmap[hr] != CCREG) | |
57871462 | 8505 | { |
630b122b | 8506 | if(i<slen-1&&!dops[i].is_ds) { |
8507 | assert(regs[i].regmap[hr]<64); | |
8508 | if(regmap_pre[i+1][hr]!=-1 || regs[i].regmap[hr]>0) | |
57871462 | 8509 | if(regmap_pre[i+1][hr]!=regs[i].regmap[hr]) |
57871462 | 8510 | { |
c43b5311 | 8511 | SysPrintf("fail: %x (%d %d!=%d)\n",start+i*4,hr,regmap_pre[i+1][hr],regs[i].regmap[hr]); |
57871462 | 8512 | assert(regmap_pre[i+1][hr]==regs[i].regmap[hr]); |
8513 | } | |
8514 | regmap_pre[i+1][hr]=-1; | |
8515 | if(regs[i+1].regmap_entry[hr]==CCREG) regs[i+1].regmap_entry[hr]=-1; | |
79c75f1b | 8516 | regs[i+1].wasconst&=~(1<<hr); |
57871462 | 8517 | } |
8518 | regs[i].regmap[hr]=-1; | |
8519 | regs[i].isconst&=~(1<<hr); | |
8520 | } | |
8521 | } | |
8522 | } | |
630b122b | 8523 | } // if needed |
8524 | } // for hr | |
57871462 | 8525 | } |
9f51b4b9 | 8526 | |
57871462 | 8527 | /* Pass 5 - Pre-allocate registers */ |
9f51b4b9 | 8528 | |
57871462 | 8529 | // If a register is allocated during a loop, try to allocate it for the |
8530 | // entire loop, if possible. This avoids loading/storing registers | |
8531 | // inside of the loop. | |
9f51b4b9 | 8532 | |
57871462 | 8533 | signed char f_regmap[HOST_REGS]; |
8534 | clear_all_regs(f_regmap); | |
8535 | for(i=0;i<slen-1;i++) | |
8536 | { | |
630b122b | 8537 | if(dops[i].itype==UJUMP||dops[i].itype==CJUMP||dops[i].itype==SJUMP) |
57871462 | 8538 | { |
9f51b4b9 | 8539 | if(ba[i]>=start && ba[i]<(start+i*4)) |
630b122b | 8540 | if(dops[i+1].itype==NOP||dops[i+1].itype==MOV||dops[i+1].itype==ALU |
8541 | ||dops[i+1].itype==SHIFTIMM||dops[i+1].itype==IMM16||dops[i+1].itype==LOAD | |
8542 | ||dops[i+1].itype==STORE||dops[i+1].itype==STORELR||dops[i+1].itype==C1LS | |
8543 | ||dops[i+1].itype==SHIFT||dops[i+1].itype==COP1 | |
8544 | ||dops[i+1].itype==COP2||dops[i+1].itype==C2LS||dops[i+1].itype==C2OP) | |
57871462 | 8545 | { |
8546 | int t=(ba[i]-start)>>2; | |
630b122b | 8547 | if(t > 0 && !dops[t-1].is_jump) // loop_preload can't handle jumps into delay slots |
8548 | if(t<2||(dops[t-2].itype!=UJUMP&&dops[t-2].itype!=RJUMP)||dops[t-2].rt1!=31) // call/ret assumes no registers allocated | |
57871462 | 8549 | for(hr=0;hr<HOST_REGS;hr++) |
8550 | { | |
630b122b | 8551 | if(regs[i].regmap[hr]>=0) { |
b372a952 | 8552 | if(f_regmap[hr]!=regs[i].regmap[hr]) { |
8553 | // dealloc old register | |
8554 | int n; | |
8555 | for(n=0;n<HOST_REGS;n++) | |
8556 | { | |
8557 | if(f_regmap[n]==regs[i].regmap[hr]) {f_regmap[n]=-1;} | |
8558 | } | |
8559 | // and alloc new one | |
8560 | f_regmap[hr]=regs[i].regmap[hr]; | |
8561 | } | |
8562 | } | |
630b122b | 8563 | if(branch_regs[i].regmap[hr]>=0) { |
b372a952 | 8564 | if(f_regmap[hr]!=branch_regs[i].regmap[hr]) { |
8565 | // dealloc old register | |
8566 | int n; | |
8567 | for(n=0;n<HOST_REGS;n++) | |
8568 | { | |
8569 | if(f_regmap[n]==branch_regs[i].regmap[hr]) {f_regmap[n]=-1;} | |
8570 | } | |
8571 | // and alloc new one | |
8572 | f_regmap[hr]=branch_regs[i].regmap[hr]; | |
8573 | } | |
8574 | } | |
630b122b | 8575 | if(dops[i].ooo) { |
9f51b4b9 | 8576 | if(count_free_regs(regs[i].regmap)<=minimum_free_regs[i+1]) |
e1190b87 | 8577 | f_regmap[hr]=branch_regs[i].regmap[hr]; |
8578 | }else{ | |
9f51b4b9 | 8579 | if(count_free_regs(branch_regs[i].regmap)<=minimum_free_regs[i+1]) |
57871462 | 8580 | f_regmap[hr]=branch_regs[i].regmap[hr]; |
8581 | } | |
8582 | // Avoid dirty->clean transition | |
e1190b87 | 8583 | #ifdef DESTRUCTIVE_WRITEBACK |
57871462 | 8584 | if(t>0) if(get_reg(regmap_pre[t],f_regmap[hr])>=0) if((regs[t].wasdirty>>get_reg(regmap_pre[t],f_regmap[hr]))&1) f_regmap[hr]=-1; |
e1190b87 | 8585 | #endif |
8586 | // This check is only strictly required in the DESTRUCTIVE_WRITEBACK | |
8587 | // case above, however it's always a good idea. We can't hoist the | |
8588 | // load if the register was already allocated, so there's no point | |
8589 | // wasting time analyzing most of these cases. It only "succeeds" | |
8590 | // when the mapping was different and the load can be replaced with | |
8591 | // a mov, which is of negligible benefit. So such cases are | |
8592 | // skipped below. | |
57871462 | 8593 | if(f_regmap[hr]>0) { |
198df76f | 8594 | if(regs[t].regmap[hr]==f_regmap[hr]||(regs[t].regmap_entry[hr]<0&&get_reg(regmap_pre[t],f_regmap[hr])<0)) { |
57871462 | 8595 | int r=f_regmap[hr]; |
8596 | for(j=t;j<=i;j++) | |
8597 | { | |
8598 | //printf("Test %x -> %x, %x %d/%d\n",start+i*4,ba[i],start+j*4,hr,r); | |
8599 | if(r<34&&((unneeded_reg[j]>>r)&1)) break; | |
630b122b | 8600 | assert(r < 64); |
57871462 | 8601 | if(regs[j].regmap[hr]==f_regmap[hr]&&(f_regmap[hr]&63)<TEMPREG) { |
8602 | //printf("Hit %x -> %x, %x %d/%d\n",start+i*4,ba[i],start+j*4,hr,r); | |
8603 | int k; | |
8604 | if(regs[i].regmap[hr]==-1&&branch_regs[i].regmap[hr]==-1) { | |
8605 | if(get_reg(regs[i+2].regmap,f_regmap[hr])>=0) break; | |
8606 | if(r>63) { | |
8607 | if(get_reg(regs[i].regmap,r&63)<0) break; | |
8608 | if(get_reg(branch_regs[i].regmap,r&63)<0) break; | |
8609 | } | |
8610 | k=i; | |
8611 | while(k>1&®s[k-1].regmap[hr]==-1) { | |
e1190b87 | 8612 | if(count_free_regs(regs[k-1].regmap)<=minimum_free_regs[k-1]) { |
8613 | //printf("no free regs for store %x\n",start+(k-1)*4); | |
8614 | break; | |
57871462 | 8615 | } |
57871462 | 8616 | if(get_reg(regs[k-1].regmap,f_regmap[hr])>=0) { |
8617 | //printf("no-match due to different register\n"); | |
8618 | break; | |
8619 | } | |
630b122b | 8620 | if (dops[k-2].is_jump) { |
57871462 | 8621 | //printf("no-match due to branch\n"); |
8622 | break; | |
8623 | } | |
8624 | // call/ret fast path assumes no registers allocated | |
630b122b | 8625 | if(k>2&&(dops[k-3].itype==UJUMP||dops[k-3].itype==RJUMP)&&dops[k-3].rt1==31) { |
57871462 | 8626 | break; |
8627 | } | |
630b122b | 8628 | assert(r < 64); |
57871462 | 8629 | k--; |
8630 | } | |
57871462 | 8631 | if(regs[k-1].regmap[hr]==f_regmap[hr]&®map_pre[k][hr]==f_regmap[hr]) { |
8632 | //printf("Extend r%d, %x ->\n",hr,start+k*4); | |
8633 | while(k<i) { | |
8634 | regs[k].regmap_entry[hr]=f_regmap[hr]; | |
8635 | regs[k].regmap[hr]=f_regmap[hr]; | |
8636 | regmap_pre[k+1][hr]=f_regmap[hr]; | |
8637 | regs[k].wasdirty&=~(1<<hr); | |
8638 | regs[k].dirty&=~(1<<hr); | |
8639 | regs[k].wasdirty|=(1<<hr)®s[k-1].dirty; | |
8640 | regs[k].dirty|=(1<<hr)®s[k].wasdirty; | |
8641 | regs[k].wasconst&=~(1<<hr); | |
8642 | regs[k].isconst&=~(1<<hr); | |
8643 | k++; | |
8644 | } | |
8645 | } | |
8646 | else { | |
8647 | //printf("Fail Extend r%d, %x ->\n",hr,start+k*4); | |
8648 | break; | |
8649 | } | |
8650 | assert(regs[i-1].regmap[hr]==f_regmap[hr]); | |
8651 | if(regs[i-1].regmap[hr]==f_regmap[hr]&®map_pre[i][hr]==f_regmap[hr]) { | |
8652 | //printf("OK fill %x (r%d)\n",start+i*4,hr); | |
8653 | regs[i].regmap_entry[hr]=f_regmap[hr]; | |
8654 | regs[i].regmap[hr]=f_regmap[hr]; | |
8655 | regs[i].wasdirty&=~(1<<hr); | |
8656 | regs[i].dirty&=~(1<<hr); | |
8657 | regs[i].wasdirty|=(1<<hr)®s[i-1].dirty; | |
8658 | regs[i].dirty|=(1<<hr)®s[i-1].dirty; | |
8659 | regs[i].wasconst&=~(1<<hr); | |
8660 | regs[i].isconst&=~(1<<hr); | |
8661 | branch_regs[i].regmap_entry[hr]=f_regmap[hr]; | |
8662 | branch_regs[i].wasdirty&=~(1<<hr); | |
8663 | branch_regs[i].wasdirty|=(1<<hr)®s[i].dirty; | |
8664 | branch_regs[i].regmap[hr]=f_regmap[hr]; | |
8665 | branch_regs[i].dirty&=~(1<<hr); | |
8666 | branch_regs[i].dirty|=(1<<hr)®s[i].dirty; | |
8667 | branch_regs[i].wasconst&=~(1<<hr); | |
8668 | branch_regs[i].isconst&=~(1<<hr); | |
630b122b | 8669 | if (!dops[i].is_ujump) { |
57871462 | 8670 | regmap_pre[i+2][hr]=f_regmap[hr]; |
8671 | regs[i+2].wasdirty&=~(1<<hr); | |
8672 | regs[i+2].wasdirty|=(1<<hr)®s[i].dirty; | |
57871462 | 8673 | } |
8674 | } | |
8675 | } | |
8676 | for(k=t;k<j;k++) { | |
e1190b87 | 8677 | // Alloc register clean at beginning of loop, |
8678 | // but may dirty it in pass 6 | |
57871462 | 8679 | regs[k].regmap_entry[hr]=f_regmap[hr]; |
8680 | regs[k].regmap[hr]=f_regmap[hr]; | |
57871462 | 8681 | regs[k].dirty&=~(1<<hr); |
8682 | regs[k].wasconst&=~(1<<hr); | |
8683 | regs[k].isconst&=~(1<<hr); | |
630b122b | 8684 | if (dops[k].is_jump) { |
e1190b87 | 8685 | branch_regs[k].regmap_entry[hr]=f_regmap[hr]; |
8686 | branch_regs[k].regmap[hr]=f_regmap[hr]; | |
8687 | branch_regs[k].dirty&=~(1<<hr); | |
8688 | branch_regs[k].wasconst&=~(1<<hr); | |
8689 | branch_regs[k].isconst&=~(1<<hr); | |
630b122b | 8690 | if (!dops[k].is_ujump) { |
e1190b87 | 8691 | regmap_pre[k+2][hr]=f_regmap[hr]; |
8692 | regs[k+2].wasdirty&=~(1<<hr); | |
e1190b87 | 8693 | } |
8694 | } | |
8695 | else | |
8696 | { | |
8697 | regmap_pre[k+1][hr]=f_regmap[hr]; | |
8698 | regs[k+1].wasdirty&=~(1<<hr); | |
8699 | } | |
57871462 | 8700 | } |
8701 | if(regs[j].regmap[hr]==f_regmap[hr]) | |
8702 | regs[j].regmap_entry[hr]=f_regmap[hr]; | |
8703 | break; | |
8704 | } | |
8705 | if(j==i) break; | |
8706 | if(regs[j].regmap[hr]>=0) | |
8707 | break; | |
8708 | if(get_reg(regs[j].regmap,f_regmap[hr])>=0) { | |
8709 | //printf("no-match due to different register\n"); | |
8710 | break; | |
8711 | } | |
630b122b | 8712 | if (dops[j].is_ujump) |
e1190b87 | 8713 | { |
8714 | // Stop on unconditional branch | |
8715 | break; | |
8716 | } | |
630b122b | 8717 | if(dops[j].itype==CJUMP||dops[j].itype==SJUMP) |
e1190b87 | 8718 | { |
630b122b | 8719 | if(dops[j].ooo) { |
9f51b4b9 | 8720 | if(count_free_regs(regs[j].regmap)<=minimum_free_regs[j+1]) |
e1190b87 | 8721 | break; |
8722 | }else{ | |
9f51b4b9 | 8723 | if(count_free_regs(branch_regs[j].regmap)<=minimum_free_regs[j+1]) |
e1190b87 | 8724 | break; |
8725 | } | |
8726 | if(get_reg(branch_regs[j].regmap,f_regmap[hr])>=0) { | |
8727 | //printf("no-match due to different register (branch)\n"); | |
57871462 | 8728 | break; |
8729 | } | |
8730 | } | |
e1190b87 | 8731 | if(count_free_regs(regs[j].regmap)<=minimum_free_regs[j]) { |
8732 | //printf("No free regs for store %x\n",start+j*4); | |
8733 | break; | |
8734 | } | |
630b122b | 8735 | assert(f_regmap[hr]<64); |
57871462 | 8736 | } |
8737 | } | |
8738 | } | |
8739 | } | |
8740 | } | |
8741 | }else{ | |
198df76f | 8742 | // Non branch or undetermined branch target |
57871462 | 8743 | for(hr=0;hr<HOST_REGS;hr++) |
8744 | { | |
8745 | if(hr!=EXCLUDE_REG) { | |
630b122b | 8746 | if(regs[i].regmap[hr]>=0) { |
b372a952 | 8747 | if(f_regmap[hr]!=regs[i].regmap[hr]) { |
8748 | // dealloc old register | |
8749 | int n; | |
8750 | for(n=0;n<HOST_REGS;n++) | |
8751 | { | |
8752 | if(f_regmap[n]==regs[i].regmap[hr]) {f_regmap[n]=-1;} | |
8753 | } | |
8754 | // and alloc new one | |
8755 | f_regmap[hr]=regs[i].regmap[hr]; | |
8756 | } | |
8757 | } | |
57871462 | 8758 | } |
8759 | } | |
8760 | // Try to restore cycle count at branch targets | |
630b122b | 8761 | if(dops[i].bt) { |
57871462 | 8762 | for(j=i;j<slen-1;j++) { |
8763 | if(regs[j].regmap[HOST_CCREG]!=-1) break; | |
e1190b87 | 8764 | if(count_free_regs(regs[j].regmap)<=minimum_free_regs[j]) { |
8765 | //printf("no free regs for store %x\n",start+j*4); | |
8766 | break; | |
57871462 | 8767 | } |
57871462 | 8768 | } |
8769 | if(regs[j].regmap[HOST_CCREG]==CCREG) { | |
8770 | int k=i; | |
8771 | //printf("Extend CC, %x -> %x\n",start+k*4,start+j*4); | |
8772 | while(k<j) { | |
8773 | regs[k].regmap_entry[HOST_CCREG]=CCREG; | |
8774 | regs[k].regmap[HOST_CCREG]=CCREG; | |
8775 | regmap_pre[k+1][HOST_CCREG]=CCREG; | |
8776 | regs[k+1].wasdirty|=1<<HOST_CCREG; | |
8777 | regs[k].dirty|=1<<HOST_CCREG; | |
8778 | regs[k].wasconst&=~(1<<HOST_CCREG); | |
8779 | regs[k].isconst&=~(1<<HOST_CCREG); | |
8780 | k++; | |
8781 | } | |
9f51b4b9 | 8782 | regs[j].regmap_entry[HOST_CCREG]=CCREG; |
57871462 | 8783 | } |
8784 | // Work backwards from the branch target | |
8785 | if(j>i&&f_regmap[HOST_CCREG]==CCREG) | |
8786 | { | |
8787 | //printf("Extend backwards\n"); | |
8788 | int k; | |
8789 | k=i; | |
8790 | while(regs[k-1].regmap[HOST_CCREG]==-1) { | |
e1190b87 | 8791 | if(count_free_regs(regs[k-1].regmap)<=minimum_free_regs[k-1]) { |
8792 | //printf("no free regs for store %x\n",start+(k-1)*4); | |
8793 | break; | |
57871462 | 8794 | } |
57871462 | 8795 | k--; |
8796 | } | |
8797 | if(regs[k-1].regmap[HOST_CCREG]==CCREG) { | |
8798 | //printf("Extend CC, %x ->\n",start+k*4); | |
8799 | while(k<=i) { | |
8800 | regs[k].regmap_entry[HOST_CCREG]=CCREG; | |
8801 | regs[k].regmap[HOST_CCREG]=CCREG; | |
8802 | regmap_pre[k+1][HOST_CCREG]=CCREG; | |
8803 | regs[k+1].wasdirty|=1<<HOST_CCREG; | |
8804 | regs[k].dirty|=1<<HOST_CCREG; | |
8805 | regs[k].wasconst&=~(1<<HOST_CCREG); | |
8806 | regs[k].isconst&=~(1<<HOST_CCREG); | |
8807 | k++; | |
8808 | } | |
8809 | } | |
8810 | else { | |
8811 | //printf("Fail Extend CC, %x ->\n",start+k*4); | |
8812 | } | |
8813 | } | |
8814 | } | |
630b122b | 8815 | if(dops[i].itype!=STORE&&dops[i].itype!=STORELR&&dops[i].itype!=C1LS&&dops[i].itype!=SHIFT&& |
8816 | dops[i].itype!=NOP&&dops[i].itype!=MOV&&dops[i].itype!=ALU&&dops[i].itype!=SHIFTIMM&& | |
8817 | dops[i].itype!=IMM16&&dops[i].itype!=LOAD&&dops[i].itype!=COP1) | |
57871462 | 8818 | { |
8819 | memcpy(f_regmap,regs[i].regmap,sizeof(f_regmap)); | |
8820 | } | |
8821 | } | |
8822 | } | |
9f51b4b9 | 8823 | |
57871462 | 8824 | // This allocates registers (if possible) one instruction prior |
8825 | // to use, which can avoid a load-use penalty on certain CPUs. | |
8826 | for(i=0;i<slen-1;i++) | |
8827 | { | |
630b122b | 8828 | if (!i || !dops[i-1].is_jump) |
57871462 | 8829 | { |
630b122b | 8830 | if(!dops[i+1].bt) |
57871462 | 8831 | { |
630b122b | 8832 | if(dops[i].itype==ALU||dops[i].itype==MOV||dops[i].itype==LOAD||dops[i].itype==SHIFTIMM||dops[i].itype==IMM16 |
8833 | ||((dops[i].itype==COP1||dops[i].itype==COP2)&&dops[i].opcode2<3)) | |
57871462 | 8834 | { |
630b122b | 8835 | if(dops[i+1].rs1) { |
8836 | if((hr=get_reg(regs[i+1].regmap,dops[i+1].rs1))>=0) | |
57871462 | 8837 | { |
8838 | if(regs[i].regmap[hr]<0&®s[i+1].regmap_entry[hr]<0) | |
8839 | { | |
8840 | regs[i].regmap[hr]=regs[i+1].regmap[hr]; | |
8841 | regmap_pre[i+1][hr]=regs[i+1].regmap[hr]; | |
8842 | regs[i+1].regmap_entry[hr]=regs[i+1].regmap[hr]; | |
8843 | regs[i].isconst&=~(1<<hr); | |
8844 | regs[i].isconst|=regs[i+1].isconst&(1<<hr); | |
8845 | constmap[i][hr]=constmap[i+1][hr]; | |
8846 | regs[i+1].wasdirty&=~(1<<hr); | |
8847 | regs[i].dirty&=~(1<<hr); | |
8848 | } | |
8849 | } | |
8850 | } | |
630b122b | 8851 | if(dops[i+1].rs2) { |
8852 | if((hr=get_reg(regs[i+1].regmap,dops[i+1].rs2))>=0) | |
57871462 | 8853 | { |
8854 | if(regs[i].regmap[hr]<0&®s[i+1].regmap_entry[hr]<0) | |
8855 | { | |
8856 | regs[i].regmap[hr]=regs[i+1].regmap[hr]; | |
8857 | regmap_pre[i+1][hr]=regs[i+1].regmap[hr]; | |
8858 | regs[i+1].regmap_entry[hr]=regs[i+1].regmap[hr]; | |
8859 | regs[i].isconst&=~(1<<hr); | |
8860 | regs[i].isconst|=regs[i+1].isconst&(1<<hr); | |
8861 | constmap[i][hr]=constmap[i+1][hr]; | |
8862 | regs[i+1].wasdirty&=~(1<<hr); | |
8863 | regs[i].dirty&=~(1<<hr); | |
8864 | } | |
8865 | } | |
8866 | } | |
198df76f | 8867 | // Preload target address for load instruction (non-constant) |
630b122b | 8868 | if(dops[i+1].itype==LOAD&&dops[i+1].rs1&&get_reg(regs[i+1].regmap,dops[i+1].rs1)<0) { |
8869 | if((hr=get_reg(regs[i+1].regmap,dops[i+1].rt1))>=0) | |
57871462 | 8870 | { |
8871 | if(regs[i].regmap[hr]<0&®s[i+1].regmap_entry[hr]<0) | |
8872 | { | |
630b122b | 8873 | regs[i].regmap[hr]=dops[i+1].rs1; |
8874 | regmap_pre[i+1][hr]=dops[i+1].rs1; | |
8875 | regs[i+1].regmap_entry[hr]=dops[i+1].rs1; | |
57871462 | 8876 | regs[i].isconst&=~(1<<hr); |
8877 | regs[i].isconst|=regs[i+1].isconst&(1<<hr); | |
8878 | constmap[i][hr]=constmap[i+1][hr]; | |
8879 | regs[i+1].wasdirty&=~(1<<hr); | |
8880 | regs[i].dirty&=~(1<<hr); | |
8881 | } | |
8882 | } | |
8883 | } | |
9f51b4b9 | 8884 | // Load source into target register |
630b122b | 8885 | if(dops[i+1].lt1&&get_reg(regs[i+1].regmap,dops[i+1].rs1)<0) { |
8886 | if((hr=get_reg(regs[i+1].regmap,dops[i+1].rt1))>=0) | |
57871462 | 8887 | { |
8888 | if(regs[i].regmap[hr]<0&®s[i+1].regmap_entry[hr]<0) | |
8889 | { | |
630b122b | 8890 | regs[i].regmap[hr]=dops[i+1].rs1; |
8891 | regmap_pre[i+1][hr]=dops[i+1].rs1; | |
8892 | regs[i+1].regmap_entry[hr]=dops[i+1].rs1; | |
57871462 | 8893 | regs[i].isconst&=~(1<<hr); |
8894 | regs[i].isconst|=regs[i+1].isconst&(1<<hr); | |
8895 | constmap[i][hr]=constmap[i+1][hr]; | |
8896 | regs[i+1].wasdirty&=~(1<<hr); | |
8897 | regs[i].dirty&=~(1<<hr); | |
8898 | } | |
8899 | } | |
8900 | } | |
198df76f | 8901 | // Address for store instruction (non-constant) |
630b122b | 8902 | if(dops[i+1].itype==STORE||dops[i+1].itype==STORELR |
8903 | ||(dops[i+1].opcode&0x3b)==0x39||(dops[i+1].opcode&0x3b)==0x3a) { // SB/SH/SW/SD/SWC1/SDC1/SWC2/SDC2 | |
8904 | if(get_reg(regs[i+1].regmap,dops[i+1].rs1)<0) { | |
57871462 | 8905 | hr=get_reg2(regs[i].regmap,regs[i+1].regmap,-1); |
8906 | if(hr<0) hr=get_reg(regs[i+1].regmap,-1); | |
8907 | else {regs[i+1].regmap[hr]=AGEN1+((i+1)&1);regs[i+1].isconst&=~(1<<hr);} | |
8908 | assert(hr>=0); | |
8909 | if(regs[i].regmap[hr]<0&®s[i+1].regmap_entry[hr]<0) | |
8910 | { | |
630b122b | 8911 | regs[i].regmap[hr]=dops[i+1].rs1; |
8912 | regmap_pre[i+1][hr]=dops[i+1].rs1; | |
8913 | regs[i+1].regmap_entry[hr]=dops[i+1].rs1; | |
57871462 | 8914 | regs[i].isconst&=~(1<<hr); |
8915 | regs[i].isconst|=regs[i+1].isconst&(1<<hr); | |
8916 | constmap[i][hr]=constmap[i+1][hr]; | |
8917 | regs[i+1].wasdirty&=~(1<<hr); | |
8918 | regs[i].dirty&=~(1<<hr); | |
8919 | } | |
8920 | } | |
8921 | } | |
630b122b | 8922 | if(dops[i+1].itype==LOADLR||(dops[i+1].opcode&0x3b)==0x31||(dops[i+1].opcode&0x3b)==0x32) { // LWC1/LDC1, LWC2/LDC2 |
8923 | if(get_reg(regs[i+1].regmap,dops[i+1].rs1)<0) { | |
57871462 | 8924 | int nr; |
8925 | hr=get_reg(regs[i+1].regmap,FTEMP); | |
8926 | assert(hr>=0); | |
8927 | if(regs[i].regmap[hr]<0&®s[i+1].regmap_entry[hr]<0) | |
8928 | { | |
630b122b | 8929 | regs[i].regmap[hr]=dops[i+1].rs1; |
8930 | regmap_pre[i+1][hr]=dops[i+1].rs1; | |
8931 | regs[i+1].regmap_entry[hr]=dops[i+1].rs1; | |
57871462 | 8932 | regs[i].isconst&=~(1<<hr); |
8933 | regs[i].isconst|=regs[i+1].isconst&(1<<hr); | |
8934 | constmap[i][hr]=constmap[i+1][hr]; | |
8935 | regs[i+1].wasdirty&=~(1<<hr); | |
8936 | regs[i].dirty&=~(1<<hr); | |
8937 | } | |
8938 | else if((nr=get_reg2(regs[i].regmap,regs[i+1].regmap,-1))>=0) | |
8939 | { | |
8940 | // move it to another register | |
8941 | regs[i+1].regmap[hr]=-1; | |
8942 | regmap_pre[i+2][hr]=-1; | |
8943 | regs[i+1].regmap[nr]=FTEMP; | |
8944 | regmap_pre[i+2][nr]=FTEMP; | |
630b122b | 8945 | regs[i].regmap[nr]=dops[i+1].rs1; |
8946 | regmap_pre[i+1][nr]=dops[i+1].rs1; | |
8947 | regs[i+1].regmap_entry[nr]=dops[i+1].rs1; | |
57871462 | 8948 | regs[i].isconst&=~(1<<nr); |
8949 | regs[i+1].isconst&=~(1<<nr); | |
8950 | regs[i].dirty&=~(1<<nr); | |
8951 | regs[i+1].wasdirty&=~(1<<nr); | |
8952 | regs[i+1].dirty&=~(1<<nr); | |
8953 | regs[i+2].wasdirty&=~(1<<nr); | |
8954 | } | |
8955 | } | |
8956 | } | |
630b122b | 8957 | if(dops[i+1].itype==LOAD||dops[i+1].itype==LOADLR||dops[i+1].itype==STORE||dops[i+1].itype==STORELR/*||dops[i+1].itype==C1LS||||dops[i+1].itype==C2LS*/) { |
8958 | if(dops[i+1].itype==LOAD) | |
8959 | hr=get_reg(regs[i+1].regmap,dops[i+1].rt1); | |
8960 | if(dops[i+1].itype==LOADLR||(dops[i+1].opcode&0x3b)==0x31||(dops[i+1].opcode&0x3b)==0x32) // LWC1/LDC1, LWC2/LDC2 | |
57871462 | 8961 | hr=get_reg(regs[i+1].regmap,FTEMP); |
630b122b | 8962 | if(dops[i+1].itype==STORE||dops[i+1].itype==STORELR||(dops[i+1].opcode&0x3b)==0x39||(dops[i+1].opcode&0x3b)==0x3a) { // SWC1/SDC1/SWC2/SDC2 |
57871462 | 8963 | hr=get_reg(regs[i+1].regmap,AGEN1+((i+1)&1)); |
8964 | if(hr<0) hr=get_reg(regs[i+1].regmap,-1); | |
8965 | } | |
8966 | if(hr>=0&®s[i].regmap[hr]<0) { | |
630b122b | 8967 | int rs=get_reg(regs[i+1].regmap,dops[i+1].rs1); |
57871462 | 8968 | if(rs>=0&&((regs[i+1].wasconst>>rs)&1)) { |
8969 | regs[i].regmap[hr]=AGEN1+((i+1)&1); | |
8970 | regmap_pre[i+1][hr]=AGEN1+((i+1)&1); | |
8971 | regs[i+1].regmap_entry[hr]=AGEN1+((i+1)&1); | |
8972 | regs[i].isconst&=~(1<<hr); | |
8973 | regs[i+1].wasdirty&=~(1<<hr); | |
8974 | regs[i].dirty&=~(1<<hr); | |
8975 | } | |
8976 | } | |
8977 | } | |
8978 | } | |
8979 | } | |
8980 | } | |
8981 | } | |
9f51b4b9 | 8982 | |
57871462 | 8983 | /* Pass 6 - Optimize clean/dirty state */ |
8984 | clean_registers(0,slen-1,1); | |
9f51b4b9 | 8985 | |
57871462 | 8986 | /* Pass 7 - Identify 32-bit registers */ |
04fd948a | 8987 | for (i=slen-1;i>=0;i--) |
8988 | { | |
630b122b | 8989 | if(dops[i].itype==CJUMP||dops[i].itype==SJUMP) |
04fd948a | 8990 | { |
8991 | // Conditional branch | |
8992 | if((source[i]>>16)!=0x1000&&i<slen-2) { | |
8993 | // Mark this address as a branch target since it may be called | |
8994 | // upon return from interrupt | |
630b122b | 8995 | dops[i+2].bt=1; |
04fd948a | 8996 | } |
8997 | } | |
8998 | } | |
57871462 | 8999 | |
630b122b | 9000 | if(dops[slen-1].itype==SPAN) { |
9001 | dops[slen-1].bt=1; // Mark as a branch target so instruction can restart after exception | |
57871462 | 9002 | } |
4600ba03 | 9003 | |
9004 | #ifdef DISASM | |
57871462 | 9005 | /* Debug/disassembly */ |
57871462 | 9006 | for(i=0;i<slen;i++) |
9007 | { | |
9008 | printf("U:"); | |
9009 | int r; | |
9010 | for(r=1;r<=CCREG;r++) { | |
9011 | if((unneeded_reg[i]>>r)&1) { | |
9012 | if(r==HIREG) printf(" HI"); | |
9013 | else if(r==LOREG) printf(" LO"); | |
9014 | else printf(" r%d",r); | |
9015 | } | |
9016 | } | |
57871462 | 9017 | printf("\n"); |
9018 | #if defined(__i386__) || defined(__x86_64__) | |
9019 | printf("pre: eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",regmap_pre[i][0],regmap_pre[i][1],regmap_pre[i][2],regmap_pre[i][3],regmap_pre[i][5],regmap_pre[i][6],regmap_pre[i][7]); | |
9020 | #endif | |
9021 | #ifdef __arm__ | |
9022 | printf("pre: r0=%d r1=%d r2=%d r3=%d r4=%d r5=%d r6=%d r7=%d r8=%d r9=%d r10=%d r12=%d\n",regmap_pre[i][0],regmap_pre[i][1],regmap_pre[i][2],regmap_pre[i][3],regmap_pre[i][4],regmap_pre[i][5],regmap_pre[i][6],regmap_pre[i][7],regmap_pre[i][8],regmap_pre[i][9],regmap_pre[i][10],regmap_pre[i][12]); | |
9023 | #endif | |
630b122b | 9024 | #if defined(__i386__) || defined(__x86_64__) |
57871462 | 9025 | printf("needs: "); |
9026 | if(needed_reg[i]&1) printf("eax "); | |
9027 | if((needed_reg[i]>>1)&1) printf("ecx "); | |
9028 | if((needed_reg[i]>>2)&1) printf("edx "); | |
9029 | if((needed_reg[i]>>3)&1) printf("ebx "); | |
9030 | if((needed_reg[i]>>5)&1) printf("ebp "); | |
9031 | if((needed_reg[i]>>6)&1) printf("esi "); | |
9032 | if((needed_reg[i]>>7)&1) printf("edi "); | |
57871462 | 9033 | printf("\n"); |
57871462 | 9034 | printf("entry: eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",regs[i].regmap_entry[0],regs[i].regmap_entry[1],regs[i].regmap_entry[2],regs[i].regmap_entry[3],regs[i].regmap_entry[5],regs[i].regmap_entry[6],regs[i].regmap_entry[7]); |
9035 | printf("dirty: "); | |
9036 | if(regs[i].wasdirty&1) printf("eax "); | |
9037 | if((regs[i].wasdirty>>1)&1) printf("ecx "); | |
9038 | if((regs[i].wasdirty>>2)&1) printf("edx "); | |
9039 | if((regs[i].wasdirty>>3)&1) printf("ebx "); | |
9040 | if((regs[i].wasdirty>>5)&1) printf("ebp "); | |
9041 | if((regs[i].wasdirty>>6)&1) printf("esi "); | |
9042 | if((regs[i].wasdirty>>7)&1) printf("edi "); | |
9043 | #endif | |
9044 | #ifdef __arm__ | |
9045 | printf("entry: r0=%d r1=%d r2=%d r3=%d r4=%d r5=%d r6=%d r7=%d r8=%d r9=%d r10=%d r12=%d\n",regs[i].regmap_entry[0],regs[i].regmap_entry[1],regs[i].regmap_entry[2],regs[i].regmap_entry[3],regs[i].regmap_entry[4],regs[i].regmap_entry[5],regs[i].regmap_entry[6],regs[i].regmap_entry[7],regs[i].regmap_entry[8],regs[i].regmap_entry[9],regs[i].regmap_entry[10],regs[i].regmap_entry[12]); | |
9046 | printf("dirty: "); | |
9047 | if(regs[i].wasdirty&1) printf("r0 "); | |
9048 | if((regs[i].wasdirty>>1)&1) printf("r1 "); | |
9049 | if((regs[i].wasdirty>>2)&1) printf("r2 "); | |
9050 | if((regs[i].wasdirty>>3)&1) printf("r3 "); | |
9051 | if((regs[i].wasdirty>>4)&1) printf("r4 "); | |
9052 | if((regs[i].wasdirty>>5)&1) printf("r5 "); | |
9053 | if((regs[i].wasdirty>>6)&1) printf("r6 "); | |
9054 | if((regs[i].wasdirty>>7)&1) printf("r7 "); | |
9055 | if((regs[i].wasdirty>>8)&1) printf("r8 "); | |
9056 | if((regs[i].wasdirty>>9)&1) printf("r9 "); | |
9057 | if((regs[i].wasdirty>>10)&1) printf("r10 "); | |
9058 | if((regs[i].wasdirty>>12)&1) printf("r12 "); | |
9059 | #endif | |
9060 | printf("\n"); | |
9061 | disassemble_inst(i); | |
9062 | //printf ("ccadj[%d] = %d\n",i,ccadj[i]); | |
9063 | #if defined(__i386__) || defined(__x86_64__) | |
9064 | printf("eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d dirty: ",regs[i].regmap[0],regs[i].regmap[1],regs[i].regmap[2],regs[i].regmap[3],regs[i].regmap[5],regs[i].regmap[6],regs[i].regmap[7]); | |
9065 | if(regs[i].dirty&1) printf("eax "); | |
9066 | if((regs[i].dirty>>1)&1) printf("ecx "); | |
9067 | if((regs[i].dirty>>2)&1) printf("edx "); | |
9068 | if((regs[i].dirty>>3)&1) printf("ebx "); | |
9069 | if((regs[i].dirty>>5)&1) printf("ebp "); | |
9070 | if((regs[i].dirty>>6)&1) printf("esi "); | |
9071 | if((regs[i].dirty>>7)&1) printf("edi "); | |
9072 | #endif | |
9073 | #ifdef __arm__ | |
9074 | printf("r0=%d r1=%d r2=%d r3=%d r4=%d r5=%d r6=%d r7=%d r8=%d r9=%d r10=%d r12=%d dirty: ",regs[i].regmap[0],regs[i].regmap[1],regs[i].regmap[2],regs[i].regmap[3],regs[i].regmap[4],regs[i].regmap[5],regs[i].regmap[6],regs[i].regmap[7],regs[i].regmap[8],regs[i].regmap[9],regs[i].regmap[10],regs[i].regmap[12]); | |
9075 | if(regs[i].dirty&1) printf("r0 "); | |
9076 | if((regs[i].dirty>>1)&1) printf("r1 "); | |
9077 | if((regs[i].dirty>>2)&1) printf("r2 "); | |
9078 | if((regs[i].dirty>>3)&1) printf("r3 "); | |
9079 | if((regs[i].dirty>>4)&1) printf("r4 "); | |
9080 | if((regs[i].dirty>>5)&1) printf("r5 "); | |
9081 | if((regs[i].dirty>>6)&1) printf("r6 "); | |
9082 | if((regs[i].dirty>>7)&1) printf("r7 "); | |
9083 | if((regs[i].dirty>>8)&1) printf("r8 "); | |
9084 | if((regs[i].dirty>>9)&1) printf("r9 "); | |
9085 | if((regs[i].dirty>>10)&1) printf("r10 "); | |
9086 | if((regs[i].dirty>>12)&1) printf("r12 "); | |
9087 | #endif | |
9088 | printf("\n"); | |
9089 | if(regs[i].isconst) { | |
9090 | printf("constants: "); | |
9091 | #if defined(__i386__) || defined(__x86_64__) | |
630b122b | 9092 | if(regs[i].isconst&1) printf("eax=%x ",(u_int)constmap[i][0]); |
9093 | if((regs[i].isconst>>1)&1) printf("ecx=%x ",(u_int)constmap[i][1]); | |
9094 | if((regs[i].isconst>>2)&1) printf("edx=%x ",(u_int)constmap[i][2]); | |
9095 | if((regs[i].isconst>>3)&1) printf("ebx=%x ",(u_int)constmap[i][3]); | |
9096 | if((regs[i].isconst>>5)&1) printf("ebp=%x ",(u_int)constmap[i][5]); | |
9097 | if((regs[i].isconst>>6)&1) printf("esi=%x ",(u_int)constmap[i][6]); | |
9098 | if((regs[i].isconst>>7)&1) printf("edi=%x ",(u_int)constmap[i][7]); | |
57871462 | 9099 | #endif |
630b122b | 9100 | #if defined(__arm__) || defined(__aarch64__) |
9101 | int r; | |
9102 | for (r = 0; r < ARRAY_SIZE(constmap[i]); r++) | |
9103 | if ((regs[i].isconst >> r) & 1) | |
9104 | printf(" r%d=%x", r, (u_int)constmap[i][r]); | |
57871462 | 9105 | #endif |
9106 | printf("\n"); | |
9107 | } | |
630b122b | 9108 | if(dops[i].is_jump) { |
57871462 | 9109 | #if defined(__i386__) || defined(__x86_64__) |
9110 | printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d dirty: ",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]); | |
9111 | if(branch_regs[i].dirty&1) printf("eax "); | |
9112 | if((branch_regs[i].dirty>>1)&1) printf("ecx "); | |
9113 | if((branch_regs[i].dirty>>2)&1) printf("edx "); | |
9114 | if((branch_regs[i].dirty>>3)&1) printf("ebx "); | |
9115 | if((branch_regs[i].dirty>>5)&1) printf("ebp "); | |
9116 | if((branch_regs[i].dirty>>6)&1) printf("esi "); | |
9117 | if((branch_regs[i].dirty>>7)&1) printf("edi "); | |
9118 | #endif | |
9119 | #ifdef __arm__ | |
9120 | printf("branch(%d): r0=%d r1=%d r2=%d r3=%d r4=%d r5=%d r6=%d r7=%d r8=%d r9=%d r10=%d r12=%d dirty: ",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[4],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7],branch_regs[i].regmap[8],branch_regs[i].regmap[9],branch_regs[i].regmap[10],branch_regs[i].regmap[12]); | |
9121 | if(branch_regs[i].dirty&1) printf("r0 "); | |
9122 | if((branch_regs[i].dirty>>1)&1) printf("r1 "); | |
9123 | if((branch_regs[i].dirty>>2)&1) printf("r2 "); | |
9124 | if((branch_regs[i].dirty>>3)&1) printf("r3 "); | |
9125 | if((branch_regs[i].dirty>>4)&1) printf("r4 "); | |
9126 | if((branch_regs[i].dirty>>5)&1) printf("r5 "); | |
9127 | if((branch_regs[i].dirty>>6)&1) printf("r6 "); | |
9128 | if((branch_regs[i].dirty>>7)&1) printf("r7 "); | |
9129 | if((branch_regs[i].dirty>>8)&1) printf("r8 "); | |
9130 | if((branch_regs[i].dirty>>9)&1) printf("r9 "); | |
9131 | if((branch_regs[i].dirty>>10)&1) printf("r10 "); | |
9132 | if((branch_regs[i].dirty>>12)&1) printf("r12 "); | |
9133 | #endif | |
57871462 | 9134 | } |
9135 | } | |
4600ba03 | 9136 | #endif // DISASM |
57871462 | 9137 | |
9138 | /* Pass 8 - Assembly */ | |
9139 | linkcount=0;stubcount=0; | |
9140 | ds=0;is_delayslot=0; | |
57871462 | 9141 | u_int dirty_pre=0; |
d148d265 | 9142 | void *beginning=start_block(); |
57871462 | 9143 | if((u_int)addr&1) { |
9144 | ds=1; | |
9145 | pagespan_ds(); | |
9146 | } | |
630b122b | 9147 | void *instr_addr0_override = NULL; |
9ad4d757 | 9148 | |
9ad4d757 | 9149 | if (start == 0x80030000) { |
630b122b | 9150 | // nasty hack for the fastbios thing |
96186eba | 9151 | // override block entry to this code |
630b122b | 9152 | instr_addr0_override = out; |
9ad4d757 | 9153 | emit_movimm(start,0); |
96186eba | 9154 | // abuse io address var as a flag that we |
9155 | // have already returned here once | |
630b122b | 9156 | emit_readword(&address,1); |
9157 | emit_writeword(0,&pcaddr); | |
9158 | emit_writeword(0,&address); | |
9ad4d757 | 9159 | emit_cmp(0,1); |
630b122b | 9160 | #ifdef __aarch64__ |
9161 | emit_jeq(out + 4*2); | |
9162 | emit_far_jump(new_dyna_leave); | |
9163 | #else | |
9164 | emit_jne(new_dyna_leave); | |
9165 | #endif | |
9ad4d757 | 9166 | } |
57871462 | 9167 | for(i=0;i<slen;i++) |
9168 | { | |
9169 | //if(ds) printf("ds: "); | |
4600ba03 | 9170 | disassemble_inst(i); |
57871462 | 9171 | if(ds) { |
9172 | ds=0; // Skip delay slot | |
630b122b | 9173 | if(dops[i].bt) assem_debug("OOPS - branch into delay slot\n"); |
9174 | instr_addr[i] = NULL; | |
57871462 | 9175 | } else { |
ffb0b9e0 | 9176 | speculate_register_values(i); |
57871462 | 9177 | #ifndef DESTRUCTIVE_WRITEBACK |
630b122b | 9178 | if (i < 2 || !dops[i-2].is_ujump) |
57871462 | 9179 | { |
630b122b | 9180 | wb_valid(regmap_pre[i],regs[i].regmap_entry,dirty_pre,regs[i].wasdirty,unneeded_reg[i]); |
57871462 | 9181 | } |
630b122b | 9182 | if((dops[i].itype==CJUMP||dops[i].itype==SJUMP)) { |
f776eb14 | 9183 | dirty_pre=branch_regs[i].dirty; |
9184 | }else{ | |
f776eb14 | 9185 | dirty_pre=regs[i].dirty; |
9186 | } | |
57871462 | 9187 | #endif |
9188 | // write back | |
630b122b | 9189 | if (i < 2 || !dops[i-2].is_ujump) |
57871462 | 9190 | { |
630b122b | 9191 | wb_invalidate(regmap_pre[i],regs[i].regmap_entry,regs[i].wasdirty,unneeded_reg[i]); |
57871462 | 9192 | loop_preload(regmap_pre[i],regs[i].regmap_entry); |
9193 | } | |
9194 | // branch target entry point | |
630b122b | 9195 | instr_addr[i] = out; |
57871462 | 9196 | assem_debug("<->\n"); |
630b122b | 9197 | drc_dbg_emit_do_cmp(i, ccadj[i]); |
9198 | ||
57871462 | 9199 | // load regs |
9200 | if(regs[i].regmap_entry[HOST_CCREG]==CCREG&®s[i].regmap[HOST_CCREG]!=CCREG) | |
630b122b | 9201 | wb_register(CCREG,regs[i].regmap_entry,regs[i].wasdirty); |
9202 | load_regs(regs[i].regmap_entry,regs[i].regmap,dops[i].rs1,dops[i].rs2); | |
57871462 | 9203 | address_generation(i,®s[i],regs[i].regmap_entry); |
630b122b | 9204 | load_consts(regmap_pre[i],regs[i].regmap,i); |
9205 | if(dops[i].is_jump) | |
57871462 | 9206 | { |
9207 | // Load the delay slot registers if necessary | |
630b122b | 9208 | if(dops[i+1].rs1!=dops[i].rs1&&dops[i+1].rs1!=dops[i].rs2&&(dops[i+1].rs1!=dops[i].rt1||dops[i].rt1==0)) |
9209 | load_regs(regs[i].regmap_entry,regs[i].regmap,dops[i+1].rs1,dops[i+1].rs1); | |
9210 | if(dops[i+1].rs2!=dops[i+1].rs1&&dops[i+1].rs2!=dops[i].rs1&&dops[i+1].rs2!=dops[i].rs2&&(dops[i+1].rs2!=dops[i].rt1||dops[i].rt1==0)) | |
9211 | load_regs(regs[i].regmap_entry,regs[i].regmap,dops[i+1].rs2,dops[i+1].rs2); | |
9212 | if (ram_offset && (dops[i+1].is_load || dops[i+1].is_store)) | |
9213 | load_regs(regs[i].regmap_entry,regs[i].regmap,ROREG,ROREG); | |
9214 | if (dops[i+1].is_store) | |
9215 | load_regs(regs[i].regmap_entry,regs[i].regmap,INVCP,INVCP); | |
57871462 | 9216 | } |
9217 | else if(i+1<slen) | |
9218 | { | |
9219 | // Preload registers for following instruction | |
630b122b | 9220 | if(dops[i+1].rs1!=dops[i].rs1&&dops[i+1].rs1!=dops[i].rs2) |
9221 | if(dops[i+1].rs1!=dops[i].rt1&&dops[i+1].rs1!=dops[i].rt2) | |
9222 | load_regs(regs[i].regmap_entry,regs[i].regmap,dops[i+1].rs1,dops[i+1].rs1); | |
9223 | if(dops[i+1].rs2!=dops[i+1].rs1&&dops[i+1].rs2!=dops[i].rs1&&dops[i+1].rs2!=dops[i].rs2) | |
9224 | if(dops[i+1].rs2!=dops[i].rt1&&dops[i+1].rs2!=dops[i].rt2) | |
9225 | load_regs(regs[i].regmap_entry,regs[i].regmap,dops[i+1].rs2,dops[i+1].rs2); | |
57871462 | 9226 | } |
9227 | // TODO: if(is_ooo(i)) address_generation(i+1); | |
630b122b | 9228 | if (!dops[i].is_jump || dops[i].itype == CJUMP) |
9229 | load_regs(regs[i].regmap_entry,regs[i].regmap,CCREG,CCREG); | |
9230 | if (ram_offset && (dops[i].is_load || dops[i].is_store)) | |
9231 | load_regs(regs[i].regmap_entry,regs[i].regmap,ROREG,ROREG); | |
9232 | if (dops[i].is_store) | |
9233 | load_regs(regs[i].regmap_entry,regs[i].regmap,INVCP,INVCP); | |
9234 | ||
9235 | ds = assemble(i, ®s[i], ccadj[i]); | |
9236 | ||
9237 | if (dops[i].is_ujump) | |
57871462 | 9238 | literal_pool(1024); |
9239 | else | |
9240 | literal_pool_jumpover(256); | |
9241 | } | |
9242 | } | |
630b122b | 9243 | |
9244 | assert(slen > 0); | |
9245 | if (slen > 0 && dops[slen-1].itype == INTCALL) { | |
9246 | // no ending needed for this block since INTCALL never returns | |
9247 | } | |
57871462 | 9248 | // If the block did not end with an unconditional branch, |
9249 | // add a jump to the next instruction. | |
630b122b | 9250 | else if (i > 1) { |
9251 | if (!dops[i-2].is_ujump && dops[i-1].itype != SPAN) { | |
9252 | assert(!dops[i-1].is_jump); | |
57871462 | 9253 | assert(i==slen); |
630b122b | 9254 | if(dops[i-2].itype!=CJUMP&&dops[i-2].itype!=SJUMP) { |
9255 | store_regs_bt(regs[i-1].regmap,regs[i-1].dirty,start+i*4); | |
57871462 | 9256 | if(regs[i-1].regmap[HOST_CCREG]!=CCREG) |
9257 | emit_loadreg(CCREG,HOST_CCREG); | |
630b122b | 9258 | emit_addimm(HOST_CCREG, ccadj[i-1] + CLOCK_ADJUST(1), HOST_CCREG); |
57871462 | 9259 | } |
9260 | else | |
9261 | { | |
630b122b | 9262 | store_regs_bt(branch_regs[i-2].regmap,branch_regs[i-2].dirty,start+i*4); |
9263 | assert(branch_regs[i-2].regmap[HOST_CCREG]==CCREG); | |
57871462 | 9264 | } |
630b122b | 9265 | add_to_linker(out,start+i*4,0); |
57871462 | 9266 | emit_jmp(0); |
9267 | } | |
9268 | } | |
9269 | else | |
9270 | { | |
9271 | assert(i>0); | |
630b122b | 9272 | assert(!dops[i-1].is_jump); |
9273 | store_regs_bt(regs[i-1].regmap,regs[i-1].dirty,start+i*4); | |
57871462 | 9274 | if(regs[i-1].regmap[HOST_CCREG]!=CCREG) |
9275 | emit_loadreg(CCREG,HOST_CCREG); | |
630b122b | 9276 | emit_addimm(HOST_CCREG, ccadj[i-1] + CLOCK_ADJUST(1), HOST_CCREG); |
9277 | add_to_linker(out,start+i*4,0); | |
57871462 | 9278 | emit_jmp(0); |
9279 | } | |
9280 | ||
9281 | // TODO: delay slot stubs? | |
9282 | // Stubs | |
9283 | for(i=0;i<stubcount;i++) | |
9284 | { | |
630b122b | 9285 | switch(stubs[i].type) |
57871462 | 9286 | { |
9287 | case LOADB_STUB: | |
9288 | case LOADH_STUB: | |
9289 | case LOADW_STUB: | |
9290 | case LOADD_STUB: | |
9291 | case LOADBU_STUB: | |
9292 | case LOADHU_STUB: | |
9293 | do_readstub(i);break; | |
9294 | case STOREB_STUB: | |
9295 | case STOREH_STUB: | |
9296 | case STOREW_STUB: | |
9297 | case STORED_STUB: | |
9298 | do_writestub(i);break; | |
9299 | case CC_STUB: | |
9300 | do_ccstub(i);break; | |
9301 | case INVCODE_STUB: | |
9302 | do_invstub(i);break; | |
9303 | case FP_STUB: | |
9304 | do_cop1stub(i);break; | |
9305 | case STORELR_STUB: | |
9306 | do_unalignedwritestub(i);break; | |
9307 | } | |
9308 | } | |
9309 | ||
9ad4d757 | 9310 | if (instr_addr0_override) |
9311 | instr_addr[0] = instr_addr0_override; | |
9312 | ||
57871462 | 9313 | /* Pass 9 - Linker */ |
9314 | for(i=0;i<linkcount;i++) | |
9315 | { | |
630b122b | 9316 | assem_debug("%p -> %8x\n",link_addr[i].addr,link_addr[i].target); |
57871462 | 9317 | literal_pool(64); |
630b122b | 9318 | if (!link_addr[i].ext) |
57871462 | 9319 | { |
630b122b | 9320 | void *stub = out; |
9321 | void *addr = check_addr(link_addr[i].target); | |
9322 | emit_extjump(link_addr[i].addr, link_addr[i].target); | |
9323 | if (addr) { | |
9324 | set_jump_target(link_addr[i].addr, addr); | |
9325 | add_jump_out(link_addr[i].target,stub); | |
57871462 | 9326 | } |
630b122b | 9327 | else |
9328 | set_jump_target(link_addr[i].addr, stub); | |
57871462 | 9329 | } |
9330 | else | |
9331 | { | |
9332 | // Internal branch | |
630b122b | 9333 | int target=(link_addr[i].target-start)>>2; |
57871462 | 9334 | assert(target>=0&&target<slen); |
9335 | assert(instr_addr[target]); | |
9336 | //#ifdef CORTEX_A8_BRANCH_PREDICTION_HACK | |
630b122b | 9337 | //set_jump_target_fillslot(link_addr[i].addr,instr_addr[target],link_addr[i].ext>>1); |
57871462 | 9338 | //#else |
630b122b | 9339 | set_jump_target(link_addr[i].addr, instr_addr[target]); |
57871462 | 9340 | //#endif |
9341 | } | |
9342 | } | |
630b122b | 9343 | |
9344 | u_int source_len = slen*4; | |
9345 | if (dops[slen-1].itype == INTCALL && source_len > 4) | |
9346 | // no need to treat the last instruction as compiled | |
9347 | // as interpreter fully handles it | |
9348 | source_len -= 4; | |
9349 | ||
9350 | if ((u_char *)copy + source_len > (u_char *)shadow + sizeof(shadow)) | |
9351 | copy = shadow; | |
9352 | ||
57871462 | 9353 | // External Branch Targets (jump_in) |
57871462 | 9354 | for(i=0;i<slen;i++) |
9355 | { | |
630b122b | 9356 | if(dops[i].bt||i==0) |
57871462 | 9357 | { |
9358 | if(instr_addr[i]) // TODO - delay slots (=null) | |
9359 | { | |
9360 | u_int vaddr=start+i*4; | |
94d23bb9 | 9361 | u_int page=get_page(vaddr); |
9362 | u_int vpage=get_vpage(vaddr); | |
57871462 | 9363 | literal_pool(256); |
57871462 | 9364 | { |
630b122b | 9365 | assem_debug("%p (%d) <- %8x\n",instr_addr[i],i,start+i*4); |
57871462 | 9366 | assem_debug("jump_in: %x\n",start+i*4); |
630b122b | 9367 | ll_add(jump_dirty+vpage,vaddr,out); |
9368 | void *entry_point = do_dirty_stub(i, source_len); | |
9369 | ll_add_flags(jump_in+page,vaddr,state_rflags,entry_point); | |
57871462 | 9370 | // If there was an existing entry in the hash table, |
9371 | // replace it with the new address. | |
9372 | // Don't add new entries. We'll insert the | |
9373 | // ones that actually get used in check_addr(). | |
630b122b | 9374 | struct ht_entry *ht_bin = hash_table_get(vaddr); |
9375 | if (ht_bin->vaddr[0] == vaddr) | |
9376 | ht_bin->tcaddr[0] = entry_point; | |
9377 | if (ht_bin->vaddr[1] == vaddr) | |
9378 | ht_bin->tcaddr[1] = entry_point; | |
57871462 | 9379 | } |
57871462 | 9380 | } |
9381 | } | |
9382 | } | |
9383 | // Write out the literal pool if necessary | |
9384 | literal_pool(0); | |
9385 | #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK | |
9386 | // Align code | |
9387 | if(((u_int)out)&7) emit_addnop(13); | |
9388 | #endif | |
630b122b | 9389 | assert(out - (u_char *)beginning < MAX_OUTPUT_BLOCK_SIZE); |
9390 | //printf("shadow buffer: %p-%p\n",copy,(u_char *)copy+slen*4); | |
9391 | memcpy(copy, source, source_len); | |
9392 | copy += source_len; | |
9f51b4b9 | 9393 | |
d148d265 | 9394 | end_block(beginning); |
9f51b4b9 | 9395 | |
57871462 | 9396 | // If we're within 256K of the end of the buffer, |
9397 | // start over from the beginning. (Is 256K enough?) | |
630b122b | 9398 | if (out > ndrc->translation_cache + sizeof(ndrc->translation_cache) - MAX_OUTPUT_BLOCK_SIZE) |
9399 | out = ndrc->translation_cache; | |
9f51b4b9 | 9400 | |
57871462 | 9401 | // Trap writes to any of the pages we compiled |
9402 | for(i=start>>12;i<=(start+slen*4)>>12;i++) { | |
9403 | invalid_code[i]=0; | |
57871462 | 9404 | } |
9be4ba64 | 9405 | inv_code_start=inv_code_end=~0; |
71e490c5 | 9406 | |
b96d3df7 | 9407 | // for PCSX we need to mark all mirrors too |
b12c9fb8 | 9408 | if(get_page(start)<(RAM_SIZE>>12)) |
9409 | for(i=start>>12;i<=(start+slen*4)>>12;i++) | |
b96d3df7 | 9410 | invalid_code[((u_int)0x00000000>>12)|(i&0x1ff)]= |
9411 | invalid_code[((u_int)0x80000000>>12)|(i&0x1ff)]= | |
9412 | invalid_code[((u_int)0xa0000000>>12)|(i&0x1ff)]=0; | |
9f51b4b9 | 9413 | |
57871462 | 9414 | /* Pass 10 - Free memory by expiring oldest blocks */ |
9f51b4b9 | 9415 | |
630b122b | 9416 | int end=(((out-ndrc->translation_cache)>>(TARGET_SIZE_2-16))+16384)&65535; |
57871462 | 9417 | while(expirep!=end) |
9418 | { | |
9419 | int shift=TARGET_SIZE_2-3; // Divide into 8 blocks | |
630b122b | 9420 | uintptr_t base_offs = ((uintptr_t)(expirep >> 13) << shift); // Base offset of this block |
9421 | uintptr_t base_offs_s = base_offs >> shift; | |
57871462 | 9422 | inv_debug("EXP: Phase %d\n",expirep); |
9423 | switch((expirep>>11)&3) | |
9424 | { | |
9425 | case 0: | |
9426 | // Clear jump_in and jump_dirty | |
630b122b | 9427 | ll_remove_matching_addrs(jump_in+(expirep&2047),base_offs_s,shift); |
9428 | ll_remove_matching_addrs(jump_dirty+(expirep&2047),base_offs_s,shift); | |
9429 | ll_remove_matching_addrs(jump_in+2048+(expirep&2047),base_offs_s,shift); | |
9430 | ll_remove_matching_addrs(jump_dirty+2048+(expirep&2047),base_offs_s,shift); | |
57871462 | 9431 | break; |
9432 | case 1: | |
9433 | // Clear pointers | |
630b122b | 9434 | ll_kill_pointers(jump_out[expirep&2047],base_offs_s,shift); |
9435 | ll_kill_pointers(jump_out[(expirep&2047)+2048],base_offs_s,shift); | |
57871462 | 9436 | break; |
9437 | case 2: | |
9438 | // Clear hash table | |
9439 | for(i=0;i<32;i++) { | |
630b122b | 9440 | struct ht_entry *ht_bin = &hash_table[((expirep&2047)<<5)+i]; |
9441 | uintptr_t o1 = (u_char *)ht_bin->tcaddr[1] - ndrc->translation_cache; | |
9442 | uintptr_t o2 = o1 - MAX_OUTPUT_BLOCK_SIZE; | |
9443 | if ((o1 >> shift) == base_offs_s || (o2 >> shift) == base_offs_s) { | |
9444 | inv_debug("EXP: Remove hash %x -> %p\n",ht_bin->vaddr[1],ht_bin->tcaddr[1]); | |
9445 | ht_bin->vaddr[1] = -1; | |
9446 | ht_bin->tcaddr[1] = NULL; | |
9447 | } | |
9448 | o1 = (u_char *)ht_bin->tcaddr[0] - ndrc->translation_cache; | |
9449 | o2 = o1 - MAX_OUTPUT_BLOCK_SIZE; | |
9450 | if ((o1 >> shift) == base_offs_s || (o2 >> shift) == base_offs_s) { | |
9451 | inv_debug("EXP: Remove hash %x -> %p\n",ht_bin->vaddr[0],ht_bin->tcaddr[0]); | |
9452 | ht_bin->vaddr[0] = ht_bin->vaddr[1]; | |
9453 | ht_bin->tcaddr[0] = ht_bin->tcaddr[1]; | |
9454 | ht_bin->vaddr[1] = -1; | |
9455 | ht_bin->tcaddr[1] = NULL; | |
57871462 | 9456 | } |
9457 | } | |
9458 | break; | |
9459 | case 3: | |
9460 | // Clear jump_out | |
9f51b4b9 | 9461 | if((expirep&2047)==0) |
dd3a91a1 | 9462 | do_clear_cache(); |
630b122b | 9463 | ll_remove_matching_addrs(jump_out+(expirep&2047),base_offs_s,shift); |
9464 | ll_remove_matching_addrs(jump_out+2048+(expirep&2047),base_offs_s,shift); | |
57871462 | 9465 | break; |
9466 | } | |
9467 | expirep=(expirep+1)&65535; | |
9468 | } | |
630b122b | 9469 | #ifdef ASSEM_PRINT |
9470 | fflush(stdout); | |
9471 | #endif | |
57871462 | 9472 | return 0; |
9473 | } | |
b9b61529 | 9474 | |
9475 | // vim:shiftwidth=2:expandtab |