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[pcsx_rearmed.git] / libpcsxcore / new_dynarec / new_dynarec.c
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57871462 1/* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
2 * Mupen64plus - new_dynarec.c *
20d507ba 3 * Copyright (C) 2009-2011 Ari64 *
57871462 4 * *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
9 * *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
14 * *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. *
19 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */
20
21#include <stdlib.h>
22#include <stdint.h> //include for uint64_t
23#include <assert.h>
4600ba03 24#include <sys/mman.h>
57871462 25
3d624f89 26#include "emu_if.h" //emulator interface
57871462 27
4600ba03 28//#define DISASM
29//#define assem_debug printf
30//#define inv_debug printf
31#define assem_debug(...)
32#define inv_debug(...)
57871462 33
34#ifdef __i386__
35#include "assem_x86.h"
36#endif
37#ifdef __x86_64__
38#include "assem_x64.h"
39#endif
40#ifdef __arm__
41#include "assem_arm.h"
42#endif
43
44#define MAXBLOCK 4096
45#define MAX_OUTPUT_BLOCK_SIZE 262144
2573466a 46
57871462 47struct regstat
48{
49 signed char regmap_entry[HOST_REGS];
50 signed char regmap[HOST_REGS];
51 uint64_t was32;
52 uint64_t is32;
53 uint64_t wasdirty;
54 uint64_t dirty;
55 uint64_t u;
56 uint64_t uu;
57 u_int wasconst;
58 u_int isconst;
8575a877 59 u_int loadedconst; // host regs that have constants loaded
60 u_int waswritten; // MIPS regs that were used as store base before
57871462 61};
62
63struct ll_entry
64{
65 u_int vaddr;
66 u_int reg32;
67 void *addr;
68 struct ll_entry *next;
69};
70
71 u_int start;
72 u_int *source;
73 u_int pagelimit;
74 char insn[MAXBLOCK][10];
75 u_char itype[MAXBLOCK];
76 u_char opcode[MAXBLOCK];
77 u_char opcode2[MAXBLOCK];
78 u_char bt[MAXBLOCK];
79 u_char rs1[MAXBLOCK];
80 u_char rs2[MAXBLOCK];
81 u_char rt1[MAXBLOCK];
82 u_char rt2[MAXBLOCK];
83 u_char us1[MAXBLOCK];
84 u_char us2[MAXBLOCK];
85 u_char dep1[MAXBLOCK];
86 u_char dep2[MAXBLOCK];
87 u_char lt1[MAXBLOCK];
bedfea38 88 static uint64_t gte_rs[MAXBLOCK]; // gte: 32 data and 32 ctl regs
89 static uint64_t gte_rt[MAXBLOCK];
90 static uint64_t gte_unneeded[MAXBLOCK];
ffb0b9e0 91 static u_int smrv[32]; // speculated MIPS register values
92 static u_int smrv_strong; // mask or regs that are likely to have correct values
93 static u_int smrv_weak; // same, but somewhat less likely
94 static u_int smrv_strong_next; // same, but after current insn executes
95 static u_int smrv_weak_next;
57871462 96 int imm[MAXBLOCK];
97 u_int ba[MAXBLOCK];
98 char likely[MAXBLOCK];
99 char is_ds[MAXBLOCK];
e1190b87 100 char ooo[MAXBLOCK];
57871462 101 uint64_t unneeded_reg[MAXBLOCK];
102 uint64_t unneeded_reg_upper[MAXBLOCK];
103 uint64_t branch_unneeded_reg[MAXBLOCK];
104 uint64_t branch_unneeded_reg_upper[MAXBLOCK];
105 uint64_t p32[MAXBLOCK];
106 uint64_t pr32[MAXBLOCK];
107 signed char regmap_pre[MAXBLOCK][HOST_REGS];
956f3129 108 static uint64_t current_constmap[HOST_REGS];
109 static uint64_t constmap[MAXBLOCK][HOST_REGS];
110 static struct regstat regs[MAXBLOCK];
111 static struct regstat branch_regs[MAXBLOCK];
e1190b87 112 signed char minimum_free_regs[MAXBLOCK];
57871462 113 u_int needed_reg[MAXBLOCK];
114 uint64_t requires_32bit[MAXBLOCK];
115 u_int wont_dirty[MAXBLOCK];
116 u_int will_dirty[MAXBLOCK];
117 int ccadj[MAXBLOCK];
118 int slen;
119 u_int instr_addr[MAXBLOCK];
120 u_int link_addr[MAXBLOCK][3];
121 int linkcount;
122 u_int stubs[MAXBLOCK*3][8];
123 int stubcount;
124 u_int literals[1024][2];
125 int literalcount;
126 int is_delayslot;
127 int cop1_usable;
128 u_char *out;
129 struct ll_entry *jump_in[4096];
130 struct ll_entry *jump_out[4096];
131 struct ll_entry *jump_dirty[4096];
132 u_int hash_table[65536][4] __attribute__((aligned(16)));
133 char shadow[1048576] __attribute__((aligned(16)));
134 void *copy;
135 int expirep;
af4ee1fe 136#ifndef PCSX
57871462 137 u_int using_tlb;
af4ee1fe 138#else
139 static const u_int using_tlb=0;
140#endif
2f546f9a 141 int new_dynarec_did_compile;
0ff8c62c 142 int new_dynarec_hacks;
57871462 143 u_int stop_after_jal;
a327ad27 144#ifndef RAM_FIXED
145 static u_int ram_offset;
146#else
147 static const u_int ram_offset=0;
148#endif
57871462 149 extern u_char restore_candidate[512];
150 extern int cycle_count;
151
152 /* registers that may be allocated */
153 /* 1-31 gpr */
154#define HIREG 32 // hi
155#define LOREG 33 // lo
156#define FSREG 34 // FPU status (FCSR)
157#define CSREG 35 // Coprocessor status
158#define CCREG 36 // Cycle count
159#define INVCP 37 // Pointer to invalid_code
619e5ded 160#define MMREG 38 // Pointer to memory_map
161#define ROREG 39 // ram offset (if rdram!=0x80000000)
162#define TEMPREG 40
163#define FTEMP 40 // FPU temporary register
164#define PTEMP 41 // Prefetch temporary register
165#define TLREG 42 // TLB mapping offset
166#define RHASH 43 // Return address hash
167#define RHTBL 44 // Return address hash table address
168#define RTEMP 45 // JR/JALR address register
169#define MAXREG 45
170#define AGEN1 46 // Address generation temporary register
171#define AGEN2 47 // Address generation temporary register
172#define MGEN1 48 // Maptable address generation temporary register
173#define MGEN2 49 // Maptable address generation temporary register
174#define BTREG 50 // Branch target temporary register
57871462 175
176 /* instruction types */
177#define NOP 0 // No operation
178#define LOAD 1 // Load
179#define STORE 2 // Store
180#define LOADLR 3 // Unaligned load
181#define STORELR 4 // Unaligned store
182#define MOV 5 // Move
183#define ALU 6 // Arithmetic/logic
184#define MULTDIV 7 // Multiply/divide
185#define SHIFT 8 // Shift by register
186#define SHIFTIMM 9// Shift by immediate
187#define IMM16 10 // 16-bit immediate
188#define RJUMP 11 // Unconditional jump to register
189#define UJUMP 12 // Unconditional jump
190#define CJUMP 13 // Conditional branch (BEQ/BNE/BGTZ/BLEZ)
191#define SJUMP 14 // Conditional branch (regimm format)
192#define COP0 15 // Coprocessor 0
193#define COP1 16 // Coprocessor 1
194#define C1LS 17 // Coprocessor 1 load/store
195#define FJUMP 18 // Conditional branch (floating point)
196#define FLOAT 19 // Floating point unit
197#define FCONV 20 // Convert integer to float
198#define FCOMP 21 // Floating point compare (sets FSREG)
199#define SYSCALL 22// SYSCALL
200#define OTHER 23 // Other
201#define SPAN 24 // Branch/delay slot spans 2 pages
202#define NI 25 // Not implemented
7139f3c8 203#define HLECALL 26// PCSX fake opcodes for HLE
b9b61529 204#define COP2 27 // Coprocessor 2 move
205#define C2LS 28 // Coprocessor 2 load/store
206#define C2OP 29 // Coprocessor 2 operation
1e973cb0 207#define INTCALL 30// Call interpreter to handle rare corner cases
57871462 208
209 /* stubs */
210#define CC_STUB 1
211#define FP_STUB 2
212#define LOADB_STUB 3
213#define LOADH_STUB 4
214#define LOADW_STUB 5
215#define LOADD_STUB 6
216#define LOADBU_STUB 7
217#define LOADHU_STUB 8
218#define STOREB_STUB 9
219#define STOREH_STUB 10
220#define STOREW_STUB 11
221#define STORED_STUB 12
222#define STORELR_STUB 13
223#define INVCODE_STUB 14
224
225 /* branch codes */
226#define TAKEN 1
227#define NOTTAKEN 2
228#define NULLDS 3
229
230// asm linkage
231int new_recompile_block(int addr);
232void *get_addr_ht(u_int vaddr);
233void invalidate_block(u_int block);
234void invalidate_addr(u_int addr);
235void remove_hash(int vaddr);
236void jump_vaddr();
237void dyna_linker();
238void dyna_linker_ds();
239void verify_code();
240void verify_code_vm();
241void verify_code_ds();
242void cc_interrupt();
243void fp_exception();
244void fp_exception_ds();
245void jump_syscall();
7139f3c8 246void jump_syscall_hle();
57871462 247void jump_eret();
7139f3c8 248void jump_hlecall();
1e973cb0 249void jump_intcall();
7139f3c8 250void new_dyna_leave();
57871462 251
252// TLB
253void TLBWI_new();
254void TLBWR_new();
255void read_nomem_new();
256void read_nomemb_new();
257void read_nomemh_new();
258void read_nomemd_new();
259void write_nomem_new();
260void write_nomemb_new();
261void write_nomemh_new();
262void write_nomemd_new();
263void write_rdram_new();
264void write_rdramb_new();
265void write_rdramh_new();
266void write_rdramd_new();
267extern u_int memory_map[1048576];
268
269// Needed by assembler
270void wb_register(signed char r,signed char regmap[],uint64_t dirty,uint64_t is32);
271void wb_dirtys(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty);
272void wb_needed_dirtys(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr);
273void load_all_regs(signed char i_regmap[]);
274void load_needed_regs(signed char i_regmap[],signed char next_regmap[]);
275void load_regs_entry(int t);
276void load_all_consts(signed char regmap[],int is32,u_int dirty,int i);
277
278int tracedebug=0;
279
280//#define DEBUG_CYCLE_COUNT 1
281
b6e87b2b 282#define NO_CYCLE_PENALTY_THR 12
283
4e9dcd7f 284int cycle_multiplier; // 100 for 1.0
285
286static int CLOCK_ADJUST(int x)
287{
288 int s=(x>>31)|1;
289 return (x * cycle_multiplier + s * 50) / 100;
290}
291
94d23bb9 292static void tlb_hacks()
57871462 293{
94d23bb9 294#ifndef DISABLE_TLB
57871462 295 // Goldeneye hack
296 if (strncmp((char *) ROM_HEADER->nom, "GOLDENEYE",9) == 0)
297 {
298 u_int addr;
299 int n;
300 switch (ROM_HEADER->Country_code&0xFF)
301 {
302 case 0x45: // U
303 addr=0x34b30;
304 break;
305 case 0x4A: // J
306 addr=0x34b70;
307 break;
308 case 0x50: // E
309 addr=0x329f0;
310 break;
311 default:
312 // Unknown country code
313 addr=0;
314 break;
315 }
316 u_int rom_addr=(u_int)rom;
317 #ifdef ROM_COPY
318 // Since memory_map is 32-bit, on 64-bit systems the rom needs to be
319 // in the lower 4G of memory to use this hack. Copy it if necessary.
320 if((void *)rom>(void *)0xffffffff) {
321 munmap(ROM_COPY, 67108864);
322 if(mmap(ROM_COPY, 12582912,
323 PROT_READ | PROT_WRITE,
324 MAP_FIXED | MAP_PRIVATE | MAP_ANONYMOUS,
325 -1, 0) <= 0) {printf("mmap() failed\n");}
326 memcpy(ROM_COPY,rom,12582912);
327 rom_addr=(u_int)ROM_COPY;
328 }
329 #endif
330 if(addr) {
331 for(n=0x7F000;n<0x80000;n++) {
332 memory_map[n]=(((u_int)(rom_addr+addr-0x7F000000))>>2)|0x40000000;
333 }
334 }
335 }
94d23bb9 336#endif
57871462 337}
338
94d23bb9 339static u_int get_page(u_int vaddr)
57871462 340{
0ce47d46 341#ifndef PCSX
57871462 342 u_int page=(vaddr^0x80000000)>>12;
0ce47d46 343#else
344 u_int page=vaddr&~0xe0000000;
345 if (page < 0x1000000)
346 page &= ~0x0e00000; // RAM mirrors
347 page>>=12;
348#endif
94d23bb9 349#ifndef DISABLE_TLB
57871462 350 if(page>262143&&tlb_LUT_r[vaddr>>12]) page=(tlb_LUT_r[vaddr>>12]^0x80000000)>>12;
94d23bb9 351#endif
57871462 352 if(page>2048) page=2048+(page&2047);
94d23bb9 353 return page;
354}
355
d25604ca 356#ifndef PCSX
94d23bb9 357static u_int get_vpage(u_int vaddr)
358{
359 u_int vpage=(vaddr^0x80000000)>>12;
360#ifndef DISABLE_TLB
57871462 361 if(vpage>262143&&tlb_LUT_r[vaddr>>12]) vpage&=2047; // jump_dirty uses a hash of the virtual address instead
94d23bb9 362#endif
57871462 363 if(vpage>2048) vpage=2048+(vpage&2047);
94d23bb9 364 return vpage;
365}
d25604ca 366#else
367// no virtual mem in PCSX
368static u_int get_vpage(u_int vaddr)
369{
370 return get_page(vaddr);
371}
372#endif
94d23bb9 373
374// Get address from virtual address
375// This is called from the recompiled JR/JALR instructions
376void *get_addr(u_int vaddr)
377{
378 u_int page=get_page(vaddr);
379 u_int vpage=get_vpage(vaddr);
57871462 380 struct ll_entry *head;
381 //printf("TRACE: count=%d next=%d (get_addr %x,page %d)\n",Count,next_interupt,vaddr,page);
382 head=jump_in[page];
383 while(head!=NULL) {
384 if(head->vaddr==vaddr&&head->reg32==0) {
385 //printf("TRACE: count=%d next=%d (get_addr match %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr);
386 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
387 ht_bin[3]=ht_bin[1];
388 ht_bin[2]=ht_bin[0];
389 ht_bin[1]=(int)head->addr;
390 ht_bin[0]=vaddr;
391 return head->addr;
392 }
393 head=head->next;
394 }
395 head=jump_dirty[vpage];
396 while(head!=NULL) {
397 if(head->vaddr==vaddr&&head->reg32==0) {
398 //printf("TRACE: count=%d next=%d (get_addr match dirty %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr);
399 // Don't restore blocks which are about to expire from the cache
400 if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
401 if(verify_dirty(head->addr)) {
402 //printf("restore candidate: %x (%d) d=%d\n",vaddr,page,invalid_code[vaddr>>12]);
403 invalid_code[vaddr>>12]=0;
9be4ba64 404 inv_code_start=inv_code_end=~0;
63cb0298 405#ifndef DISABLE_TLB
57871462 406 memory_map[vaddr>>12]|=0x40000000;
63cb0298 407#endif
57871462 408 if(vpage<2048) {
94d23bb9 409#ifndef DISABLE_TLB
57871462 410 if(tlb_LUT_r[vaddr>>12]) {
411 invalid_code[tlb_LUT_r[vaddr>>12]>>12]=0;
412 memory_map[tlb_LUT_r[vaddr>>12]>>12]|=0x40000000;
413 }
94d23bb9 414#endif
57871462 415 restore_candidate[vpage>>3]|=1<<(vpage&7);
416 }
417 else restore_candidate[page>>3]|=1<<(page&7);
418 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
419 if(ht_bin[0]==vaddr) {
420 ht_bin[1]=(int)head->addr; // Replace existing entry
421 }
422 else
423 {
424 ht_bin[3]=ht_bin[1];
425 ht_bin[2]=ht_bin[0];
426 ht_bin[1]=(int)head->addr;
427 ht_bin[0]=vaddr;
428 }
429 return head->addr;
430 }
431 }
432 head=head->next;
433 }
434 //printf("TRACE: count=%d next=%d (get_addr no-match %x)\n",Count,next_interupt,vaddr);
435 int r=new_recompile_block(vaddr);
436 if(r==0) return get_addr(vaddr);
437 // Execute in unmapped page, generate pagefault execption
438 Status|=2;
439 Cause=(vaddr<<31)|0x8;
440 EPC=(vaddr&1)?vaddr-5:vaddr;
441 BadVAddr=(vaddr&~1);
442 Context=(Context&0xFF80000F)|((BadVAddr>>9)&0x007FFFF0);
443 EntryHi=BadVAddr&0xFFFFE000;
444 return get_addr_ht(0x80000000);
445}
446// Look up address in hash table first
447void *get_addr_ht(u_int vaddr)
448{
449 //printf("TRACE: count=%d next=%d (get_addr_ht %x)\n",Count,next_interupt,vaddr);
450 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
451 if(ht_bin[0]==vaddr) return (void *)ht_bin[1];
452 if(ht_bin[2]==vaddr) return (void *)ht_bin[3];
453 return get_addr(vaddr);
454}
455
456void *get_addr_32(u_int vaddr,u_int flags)
457{
7139f3c8 458#ifdef FORCE32
459 return get_addr(vaddr);
560e4a12 460#else
57871462 461 //printf("TRACE: count=%d next=%d (get_addr_32 %x,flags %x)\n",Count,next_interupt,vaddr,flags);
462 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
463 if(ht_bin[0]==vaddr) return (void *)ht_bin[1];
464 if(ht_bin[2]==vaddr) return (void *)ht_bin[3];
94d23bb9 465 u_int page=get_page(vaddr);
466 u_int vpage=get_vpage(vaddr);
57871462 467 struct ll_entry *head;
468 head=jump_in[page];
469 while(head!=NULL) {
470 if(head->vaddr==vaddr&&(head->reg32&flags)==0) {
471 //printf("TRACE: count=%d next=%d (get_addr_32 match %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr);
472 if(head->reg32==0) {
473 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
474 if(ht_bin[0]==-1) {
475 ht_bin[1]=(int)head->addr;
476 ht_bin[0]=vaddr;
477 }else if(ht_bin[2]==-1) {
478 ht_bin[3]=(int)head->addr;
479 ht_bin[2]=vaddr;
480 }
481 //ht_bin[3]=ht_bin[1];
482 //ht_bin[2]=ht_bin[0];
483 //ht_bin[1]=(int)head->addr;
484 //ht_bin[0]=vaddr;
485 }
486 return head->addr;
487 }
488 head=head->next;
489 }
490 head=jump_dirty[vpage];
491 while(head!=NULL) {
492 if(head->vaddr==vaddr&&(head->reg32&flags)==0) {
493 //printf("TRACE: count=%d next=%d (get_addr_32 match dirty %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr);
494 // Don't restore blocks which are about to expire from the cache
495 if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
496 if(verify_dirty(head->addr)) {
497 //printf("restore candidate: %x (%d) d=%d\n",vaddr,page,invalid_code[vaddr>>12]);
498 invalid_code[vaddr>>12]=0;
9be4ba64 499 inv_code_start=inv_code_end=~0;
57871462 500 memory_map[vaddr>>12]|=0x40000000;
501 if(vpage<2048) {
94d23bb9 502#ifndef DISABLE_TLB
57871462 503 if(tlb_LUT_r[vaddr>>12]) {
504 invalid_code[tlb_LUT_r[vaddr>>12]>>12]=0;
505 memory_map[tlb_LUT_r[vaddr>>12]>>12]|=0x40000000;
506 }
94d23bb9 507#endif
57871462 508 restore_candidate[vpage>>3]|=1<<(vpage&7);
509 }
510 else restore_candidate[page>>3]|=1<<(page&7);
511 if(head->reg32==0) {
512 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
513 if(ht_bin[0]==-1) {
514 ht_bin[1]=(int)head->addr;
515 ht_bin[0]=vaddr;
516 }else if(ht_bin[2]==-1) {
517 ht_bin[3]=(int)head->addr;
518 ht_bin[2]=vaddr;
519 }
520 //ht_bin[3]=ht_bin[1];
521 //ht_bin[2]=ht_bin[0];
522 //ht_bin[1]=(int)head->addr;
523 //ht_bin[0]=vaddr;
524 }
525 return head->addr;
526 }
527 }
528 head=head->next;
529 }
530 //printf("TRACE: count=%d next=%d (get_addr_32 no-match %x,flags %x)\n",Count,next_interupt,vaddr,flags);
531 int r=new_recompile_block(vaddr);
532 if(r==0) return get_addr(vaddr);
533 // Execute in unmapped page, generate pagefault execption
534 Status|=2;
535 Cause=(vaddr<<31)|0x8;
536 EPC=(vaddr&1)?vaddr-5:vaddr;
537 BadVAddr=(vaddr&~1);
538 Context=(Context&0xFF80000F)|((BadVAddr>>9)&0x007FFFF0);
539 EntryHi=BadVAddr&0xFFFFE000;
540 return get_addr_ht(0x80000000);
560e4a12 541#endif
57871462 542}
543
544void clear_all_regs(signed char regmap[])
545{
546 int hr;
547 for (hr=0;hr<HOST_REGS;hr++) regmap[hr]=-1;
548}
549
550signed char get_reg(signed char regmap[],int r)
551{
552 int hr;
553 for (hr=0;hr<HOST_REGS;hr++) if(hr!=EXCLUDE_REG&&regmap[hr]==r) return hr;
554 return -1;
555}
556
557// Find a register that is available for two consecutive cycles
558signed char get_reg2(signed char regmap1[],signed char regmap2[],int r)
559{
560 int hr;
561 for (hr=0;hr<HOST_REGS;hr++) if(hr!=EXCLUDE_REG&&regmap1[hr]==r&&regmap2[hr]==r) return hr;
562 return -1;
563}
564
565int count_free_regs(signed char regmap[])
566{
567 int count=0;
568 int hr;
569 for(hr=0;hr<HOST_REGS;hr++)
570 {
571 if(hr!=EXCLUDE_REG) {
572 if(regmap[hr]<0) count++;
573 }
574 }
575 return count;
576}
577
578void dirty_reg(struct regstat *cur,signed char reg)
579{
580 int hr;
581 if(!reg) return;
582 for (hr=0;hr<HOST_REGS;hr++) {
583 if((cur->regmap[hr]&63)==reg) {
584 cur->dirty|=1<<hr;
585 }
586 }
587}
588
589// If we dirty the lower half of a 64 bit register which is now being
590// sign-extended, we need to dump the upper half.
591// Note: Do this only after completion of the instruction, because
592// some instructions may need to read the full 64-bit value even if
593// overwriting it (eg SLTI, DSRA32).
594static void flush_dirty_uppers(struct regstat *cur)
595{
596 int hr,reg;
597 for (hr=0;hr<HOST_REGS;hr++) {
598 if((cur->dirty>>hr)&1) {
599 reg=cur->regmap[hr];
600 if(reg>=64)
601 if((cur->is32>>(reg&63))&1) cur->regmap[hr]=-1;
602 }
603 }
604}
605
606void set_const(struct regstat *cur,signed char reg,uint64_t value)
607{
608 int hr;
609 if(!reg) return;
610 for (hr=0;hr<HOST_REGS;hr++) {
611 if(cur->regmap[hr]==reg) {
612 cur->isconst|=1<<hr;
956f3129 613 current_constmap[hr]=value;
57871462 614 }
615 else if((cur->regmap[hr]^64)==reg) {
616 cur->isconst|=1<<hr;
956f3129 617 current_constmap[hr]=value>>32;
57871462 618 }
619 }
620}
621
622void clear_const(struct regstat *cur,signed char reg)
623{
624 int hr;
625 if(!reg) return;
626 for (hr=0;hr<HOST_REGS;hr++) {
627 if((cur->regmap[hr]&63)==reg) {
628 cur->isconst&=~(1<<hr);
629 }
630 }
631}
632
633int is_const(struct regstat *cur,signed char reg)
634{
635 int hr;
79c75f1b 636 if(reg<0) return 0;
57871462 637 if(!reg) return 1;
638 for (hr=0;hr<HOST_REGS;hr++) {
639 if((cur->regmap[hr]&63)==reg) {
640 return (cur->isconst>>hr)&1;
641 }
642 }
643 return 0;
644}
645uint64_t get_const(struct regstat *cur,signed char reg)
646{
647 int hr;
648 if(!reg) return 0;
649 for (hr=0;hr<HOST_REGS;hr++) {
650 if(cur->regmap[hr]==reg) {
956f3129 651 return current_constmap[hr];
57871462 652 }
653 }
654 printf("Unknown constant in r%d\n",reg);
655 exit(1);
656}
657
658// Least soon needed registers
659// Look at the next ten instructions and see which registers
660// will be used. Try not to reallocate these.
661void lsn(u_char hsn[], int i, int *preferred_reg)
662{
663 int j;
664 int b=-1;
665 for(j=0;j<9;j++)
666 {
667 if(i+j>=slen) {
668 j=slen-i-1;
669 break;
670 }
671 if(itype[i+j]==UJUMP||itype[i+j]==RJUMP||(source[i+j]>>16)==0x1000)
672 {
673 // Don't go past an unconditonal jump
674 j++;
675 break;
676 }
677 }
678 for(;j>=0;j--)
679 {
680 if(rs1[i+j]) hsn[rs1[i+j]]=j;
681 if(rs2[i+j]) hsn[rs2[i+j]]=j;
682 if(rt1[i+j]) hsn[rt1[i+j]]=j;
683 if(rt2[i+j]) hsn[rt2[i+j]]=j;
684 if(itype[i+j]==STORE || itype[i+j]==STORELR) {
685 // Stores can allocate zero
686 hsn[rs1[i+j]]=j;
687 hsn[rs2[i+j]]=j;
688 }
689 // On some architectures stores need invc_ptr
690 #if defined(HOST_IMM8)
b9b61529 691 if(itype[i+j]==STORE || itype[i+j]==STORELR || (opcode[i+j]&0x3b)==0x39 || (opcode[i+j]&0x3b)==0x3a) {
57871462 692 hsn[INVCP]=j;
693 }
694 #endif
695 if(i+j>=0&&(itype[i+j]==UJUMP||itype[i+j]==CJUMP||itype[i+j]==SJUMP||itype[i+j]==FJUMP))
696 {
697 hsn[CCREG]=j;
698 b=j;
699 }
700 }
701 if(b>=0)
702 {
703 if(ba[i+b]>=start && ba[i+b]<(start+slen*4))
704 {
705 // Follow first branch
706 int t=(ba[i+b]-start)>>2;
707 j=7-b;if(t+j>=slen) j=slen-t-1;
708 for(;j>=0;j--)
709 {
710 if(rs1[t+j]) if(hsn[rs1[t+j]]>j+b+2) hsn[rs1[t+j]]=j+b+2;
711 if(rs2[t+j]) if(hsn[rs2[t+j]]>j+b+2) hsn[rs2[t+j]]=j+b+2;
712 //if(rt1[t+j]) if(hsn[rt1[t+j]]>j+b+2) hsn[rt1[t+j]]=j+b+2;
713 //if(rt2[t+j]) if(hsn[rt2[t+j]]>j+b+2) hsn[rt2[t+j]]=j+b+2;
714 }
715 }
716 // TODO: preferred register based on backward branch
717 }
718 // Delay slot should preferably not overwrite branch conditions or cycle count
719 if(i>0&&(itype[i-1]==RJUMP||itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP)) {
720 if(rs1[i-1]) if(hsn[rs1[i-1]]>1) hsn[rs1[i-1]]=1;
721 if(rs2[i-1]) if(hsn[rs2[i-1]]>1) hsn[rs2[i-1]]=1;
722 hsn[CCREG]=1;
723 // ...or hash tables
724 hsn[RHASH]=1;
725 hsn[RHTBL]=1;
726 }
727 // Coprocessor load/store needs FTEMP, even if not declared
b9b61529 728 if(itype[i]==C1LS||itype[i]==C2LS) {
57871462 729 hsn[FTEMP]=0;
730 }
731 // Load L/R also uses FTEMP as a temporary register
732 if(itype[i]==LOADLR) {
733 hsn[FTEMP]=0;
734 }
b7918751 735 // Also SWL/SWR/SDL/SDR
736 if(opcode[i]==0x2a||opcode[i]==0x2e||opcode[i]==0x2c||opcode[i]==0x2d) {
57871462 737 hsn[FTEMP]=0;
738 }
739 // Don't remove the TLB registers either
b9b61529 740 if(itype[i]==LOAD || itype[i]==LOADLR || itype[i]==STORE || itype[i]==STORELR || itype[i]==C1LS || itype[i]==C2LS) {
57871462 741 hsn[TLREG]=0;
742 }
743 // Don't remove the miniht registers
744 if(itype[i]==UJUMP||itype[i]==RJUMP)
745 {
746 hsn[RHASH]=0;
747 hsn[RHTBL]=0;
748 }
749}
750
751// We only want to allocate registers if we're going to use them again soon
752int needed_again(int r, int i)
753{
754 int j;
755 int b=-1;
756 int rn=10;
57871462 757
758 if(i>0&&(itype[i-1]==UJUMP||itype[i-1]==RJUMP||(source[i-1]>>16)==0x1000))
759 {
760 if(ba[i-1]<start || ba[i-1]>start+slen*4-4)
761 return 0; // Don't need any registers if exiting the block
762 }
763 for(j=0;j<9;j++)
764 {
765 if(i+j>=slen) {
766 j=slen-i-1;
767 break;
768 }
769 if(itype[i+j]==UJUMP||itype[i+j]==RJUMP||(source[i+j]>>16)==0x1000)
770 {
771 // Don't go past an unconditonal jump
772 j++;
773 break;
774 }
1e973cb0 775 if(itype[i+j]==SYSCALL||itype[i+j]==HLECALL||itype[i+j]==INTCALL||((source[i+j]&0xfc00003f)==0x0d))
57871462 776 {
777 break;
778 }
779 }
780 for(;j>=1;j--)
781 {
782 if(rs1[i+j]==r) rn=j;
783 if(rs2[i+j]==r) rn=j;
784 if((unneeded_reg[i+j]>>r)&1) rn=10;
785 if(i+j>=0&&(itype[i+j]==UJUMP||itype[i+j]==CJUMP||itype[i+j]==SJUMP||itype[i+j]==FJUMP))
786 {
787 b=j;
788 }
789 }
790 /*
791 if(b>=0)
792 {
793 if(ba[i+b]>=start && ba[i+b]<(start+slen*4))
794 {
795 // Follow first branch
796 int o=rn;
797 int t=(ba[i+b]-start)>>2;
798 j=7-b;if(t+j>=slen) j=slen-t-1;
799 for(;j>=0;j--)
800 {
801 if(!((unneeded_reg[t+j]>>r)&1)) {
802 if(rs1[t+j]==r) if(rn>j+b+2) rn=j+b+2;
803 if(rs2[t+j]==r) if(rn>j+b+2) rn=j+b+2;
804 }
805 else rn=o;
806 }
807 }
808 }*/
b7217e13 809 if(rn<10) return 1;
57871462 810 return 0;
811}
812
813// Try to match register allocations at the end of a loop with those
814// at the beginning
815int loop_reg(int i, int r, int hr)
816{
817 int j,k;
818 for(j=0;j<9;j++)
819 {
820 if(i+j>=slen) {
821 j=slen-i-1;
822 break;
823 }
824 if(itype[i+j]==UJUMP||itype[i+j]==RJUMP||(source[i+j]>>16)==0x1000)
825 {
826 // Don't go past an unconditonal jump
827 j++;
828 break;
829 }
830 }
831 k=0;
832 if(i>0){
833 if(itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP)
834 k--;
835 }
836 for(;k<j;k++)
837 {
838 if(r<64&&((unneeded_reg[i+k]>>r)&1)) return hr;
839 if(r>64&&((unneeded_reg_upper[i+k]>>r)&1)) return hr;
840 if(i+k>=0&&(itype[i+k]==UJUMP||itype[i+k]==CJUMP||itype[i+k]==SJUMP||itype[i+k]==FJUMP))
841 {
842 if(ba[i+k]>=start && ba[i+k]<(start+i*4))
843 {
844 int t=(ba[i+k]-start)>>2;
845 int reg=get_reg(regs[t].regmap_entry,r);
846 if(reg>=0) return reg;
847 //reg=get_reg(regs[t+1].regmap_entry,r);
848 //if(reg>=0) return reg;
849 }
850 }
851 }
852 return hr;
853}
854
855
856// Allocate every register, preserving source/target regs
857void alloc_all(struct regstat *cur,int i)
858{
859 int hr;
860
861 for(hr=0;hr<HOST_REGS;hr++) {
862 if(hr!=EXCLUDE_REG) {
863 if(((cur->regmap[hr]&63)!=rs1[i])&&((cur->regmap[hr]&63)!=rs2[i])&&
864 ((cur->regmap[hr]&63)!=rt1[i])&&((cur->regmap[hr]&63)!=rt2[i]))
865 {
866 cur->regmap[hr]=-1;
867 cur->dirty&=~(1<<hr);
868 }
869 // Don't need zeros
870 if((cur->regmap[hr]&63)==0)
871 {
872 cur->regmap[hr]=-1;
873 cur->dirty&=~(1<<hr);
874 }
875 }
876 }
877}
878
4600ba03 879#ifndef FORCE32
57871462 880void div64(int64_t dividend,int64_t divisor)
881{
882 lo=dividend/divisor;
883 hi=dividend%divisor;
884 //printf("TRACE: ddiv %8x%8x %8x%8x\n" ,(int)reg[HIREG],(int)(reg[HIREG]>>32)
885 // ,(int)reg[LOREG],(int)(reg[LOREG]>>32));
886}
887void divu64(uint64_t dividend,uint64_t divisor)
888{
889 lo=dividend/divisor;
890 hi=dividend%divisor;
891 //printf("TRACE: ddivu %8x%8x %8x%8x\n",(int)reg[HIREG],(int)(reg[HIREG]>>32)
892 // ,(int)reg[LOREG],(int)(reg[LOREG]>>32));
893}
894
895void mult64(uint64_t m1,uint64_t m2)
896{
897 unsigned long long int op1, op2, op3, op4;
898 unsigned long long int result1, result2, result3, result4;
899 unsigned long long int temp1, temp2, temp3, temp4;
900 int sign = 0;
901
902 if (m1 < 0)
903 {
904 op2 = -m1;
905 sign = 1 - sign;
906 }
907 else op2 = m1;
908 if (m2 < 0)
909 {
910 op4 = -m2;
911 sign = 1 - sign;
912 }
913 else op4 = m2;
914
915 op1 = op2 & 0xFFFFFFFF;
916 op2 = (op2 >> 32) & 0xFFFFFFFF;
917 op3 = op4 & 0xFFFFFFFF;
918 op4 = (op4 >> 32) & 0xFFFFFFFF;
919
920 temp1 = op1 * op3;
921 temp2 = (temp1 >> 32) + op1 * op4;
922 temp3 = op2 * op3;
923 temp4 = (temp3 >> 32) + op2 * op4;
924
925 result1 = temp1 & 0xFFFFFFFF;
926 result2 = temp2 + (temp3 & 0xFFFFFFFF);
927 result3 = (result2 >> 32) + temp4;
928 result4 = (result3 >> 32);
929
930 lo = result1 | (result2 << 32);
931 hi = (result3 & 0xFFFFFFFF) | (result4 << 32);
932 if (sign)
933 {
934 hi = ~hi;
935 if (!lo) hi++;
936 else lo = ~lo + 1;
937 }
938}
939
940void multu64(uint64_t m1,uint64_t m2)
941{
942 unsigned long long int op1, op2, op3, op4;
943 unsigned long long int result1, result2, result3, result4;
944 unsigned long long int temp1, temp2, temp3, temp4;
945
946 op1 = m1 & 0xFFFFFFFF;
947 op2 = (m1 >> 32) & 0xFFFFFFFF;
948 op3 = m2 & 0xFFFFFFFF;
949 op4 = (m2 >> 32) & 0xFFFFFFFF;
950
951 temp1 = op1 * op3;
952 temp2 = (temp1 >> 32) + op1 * op4;
953 temp3 = op2 * op3;
954 temp4 = (temp3 >> 32) + op2 * op4;
955
956 result1 = temp1 & 0xFFFFFFFF;
957 result2 = temp2 + (temp3 & 0xFFFFFFFF);
958 result3 = (result2 >> 32) + temp4;
959 result4 = (result3 >> 32);
960
961 lo = result1 | (result2 << 32);
962 hi = (result3 & 0xFFFFFFFF) | (result4 << 32);
963
964 //printf("TRACE: dmultu %8x%8x %8x%8x\n",(int)reg[HIREG],(int)(reg[HIREG]>>32)
965 // ,(int)reg[LOREG],(int)(reg[LOREG]>>32));
966}
967
968uint64_t ldl_merge(uint64_t original,uint64_t loaded,u_int bits)
969{
970 if(bits) {
971 original<<=64-bits;
972 original>>=64-bits;
973 loaded<<=bits;
974 original|=loaded;
975 }
976 else original=loaded;
977 return original;
978}
979uint64_t ldr_merge(uint64_t original,uint64_t loaded,u_int bits)
980{
981 if(bits^56) {
982 original>>=64-(bits^56);
983 original<<=64-(bits^56);
984 loaded>>=bits^56;
985 original|=loaded;
986 }
987 else original=loaded;
988 return original;
989}
4600ba03 990#endif
57871462 991
992#ifdef __i386__
993#include "assem_x86.c"
994#endif
995#ifdef __x86_64__
996#include "assem_x64.c"
997#endif
998#ifdef __arm__
999#include "assem_arm.c"
1000#endif
1001
1002// Add virtual address mapping to linked list
1003void ll_add(struct ll_entry **head,int vaddr,void *addr)
1004{
1005 struct ll_entry *new_entry;
1006 new_entry=malloc(sizeof(struct ll_entry));
1007 assert(new_entry!=NULL);
1008 new_entry->vaddr=vaddr;
1009 new_entry->reg32=0;
1010 new_entry->addr=addr;
1011 new_entry->next=*head;
1012 *head=new_entry;
1013}
1014
1015// Add virtual address mapping for 32-bit compiled block
1016void ll_add_32(struct ll_entry **head,int vaddr,u_int reg32,void *addr)
1017{
7139f3c8 1018 ll_add(head,vaddr,addr);
1019#ifndef FORCE32
1020 (*head)->reg32=reg32;
1021#endif
57871462 1022}
1023
1024// Check if an address is already compiled
1025// but don't return addresses which are about to expire from the cache
1026void *check_addr(u_int vaddr)
1027{
1028 u_int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
1029 if(ht_bin[0]==vaddr) {
1030 if(((ht_bin[1]-MAX_OUTPUT_BLOCK_SIZE-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
1031 if(isclean(ht_bin[1])) return (void *)ht_bin[1];
1032 }
1033 if(ht_bin[2]==vaddr) {
1034 if(((ht_bin[3]-MAX_OUTPUT_BLOCK_SIZE-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
1035 if(isclean(ht_bin[3])) return (void *)ht_bin[3];
1036 }
94d23bb9 1037 u_int page=get_page(vaddr);
57871462 1038 struct ll_entry *head;
1039 head=jump_in[page];
1040 while(head!=NULL) {
1041 if(head->vaddr==vaddr&&head->reg32==0) {
1042 if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2))) {
1043 // Update existing entry with current address
1044 if(ht_bin[0]==vaddr) {
1045 ht_bin[1]=(int)head->addr;
1046 return head->addr;
1047 }
1048 if(ht_bin[2]==vaddr) {
1049 ht_bin[3]=(int)head->addr;
1050 return head->addr;
1051 }
1052 // Insert into hash table with low priority.
1053 // Don't evict existing entries, as they are probably
1054 // addresses that are being accessed frequently.
1055 if(ht_bin[0]==-1) {
1056 ht_bin[1]=(int)head->addr;
1057 ht_bin[0]=vaddr;
1058 }else if(ht_bin[2]==-1) {
1059 ht_bin[3]=(int)head->addr;
1060 ht_bin[2]=vaddr;
1061 }
1062 return head->addr;
1063 }
1064 }
1065 head=head->next;
1066 }
1067 return 0;
1068}
1069
1070void remove_hash(int vaddr)
1071{
1072 //printf("remove hash: %x\n",vaddr);
1073 int *ht_bin=hash_table[(((vaddr)>>16)^vaddr)&0xFFFF];
1074 if(ht_bin[2]==vaddr) {
1075 ht_bin[2]=ht_bin[3]=-1;
1076 }
1077 if(ht_bin[0]==vaddr) {
1078 ht_bin[0]=ht_bin[2];
1079 ht_bin[1]=ht_bin[3];
1080 ht_bin[2]=ht_bin[3]=-1;
1081 }
1082}
1083
1084void ll_remove_matching_addrs(struct ll_entry **head,int addr,int shift)
1085{
1086 struct ll_entry *next;
1087 while(*head) {
1088 if(((u_int)((*head)->addr)>>shift)==(addr>>shift) ||
1089 ((u_int)((*head)->addr-MAX_OUTPUT_BLOCK_SIZE)>>shift)==(addr>>shift))
1090 {
1091 inv_debug("EXP: Remove pointer to %x (%x)\n",(int)(*head)->addr,(*head)->vaddr);
1092 remove_hash((*head)->vaddr);
1093 next=(*head)->next;
1094 free(*head);
1095 *head=next;
1096 }
1097 else
1098 {
1099 head=&((*head)->next);
1100 }
1101 }
1102}
1103
1104// Remove all entries from linked list
1105void ll_clear(struct ll_entry **head)
1106{
1107 struct ll_entry *cur;
1108 struct ll_entry *next;
1109 if(cur=*head) {
1110 *head=0;
1111 while(cur) {
1112 next=cur->next;
1113 free(cur);
1114 cur=next;
1115 }
1116 }
1117}
1118
1119// Dereference the pointers and remove if it matches
1120void ll_kill_pointers(struct ll_entry *head,int addr,int shift)
1121{
1122 while(head) {
1123 int ptr=get_pointer(head->addr);
1124 inv_debug("EXP: Lookup pointer to %x at %x (%x)\n",(int)ptr,(int)head->addr,head->vaddr);
1125 if(((ptr>>shift)==(addr>>shift)) ||
1126 (((ptr-MAX_OUTPUT_BLOCK_SIZE)>>shift)==(addr>>shift)))
1127 {
5088bb70 1128 inv_debug("EXP: Kill pointer at %x (%x)\n",(int)head->addr,head->vaddr);
f76eeef9 1129 u_int host_addr=(u_int)kill_pointer(head->addr);
dd3a91a1 1130 #ifdef __arm__
1131 needs_clear_cache[(host_addr-(u_int)BASE_ADDR)>>17]|=1<<(((host_addr-(u_int)BASE_ADDR)>>12)&31);
1132 #endif
57871462 1133 }
1134 head=head->next;
1135 }
1136}
1137
1138// This is called when we write to a compiled block (see do_invstub)
f76eeef9 1139void invalidate_page(u_int page)
57871462 1140{
57871462 1141 struct ll_entry *head;
1142 struct ll_entry *next;
1143 head=jump_in[page];
1144 jump_in[page]=0;
1145 while(head!=NULL) {
1146 inv_debug("INVALIDATE: %x\n",head->vaddr);
1147 remove_hash(head->vaddr);
1148 next=head->next;
1149 free(head);
1150 head=next;
1151 }
1152 head=jump_out[page];
1153 jump_out[page]=0;
1154 while(head!=NULL) {
1155 inv_debug("INVALIDATE: kill pointer to %x (%x)\n",head->vaddr,(int)head->addr);
f76eeef9 1156 u_int host_addr=(u_int)kill_pointer(head->addr);
dd3a91a1 1157 #ifdef __arm__
1158 needs_clear_cache[(host_addr-(u_int)BASE_ADDR)>>17]|=1<<(((host_addr-(u_int)BASE_ADDR)>>12)&31);
1159 #endif
57871462 1160 next=head->next;
1161 free(head);
1162 head=next;
1163 }
57871462 1164}
9be4ba64 1165
1166static void invalidate_block_range(u_int block, u_int first, u_int last)
57871462 1167{
94d23bb9 1168 u_int page=get_page(block<<12);
57871462 1169 //printf("first=%d last=%d\n",first,last);
f76eeef9 1170 invalidate_page(page);
57871462 1171 assert(first+5>page); // NB: this assumes MAXBLOCK<=4096 (4 pages)
1172 assert(last<page+5);
1173 // Invalidate the adjacent pages if a block crosses a 4K boundary
1174 while(first<page) {
1175 invalidate_page(first);
1176 first++;
1177 }
1178 for(first=page+1;first<last;first++) {
1179 invalidate_page(first);
1180 }
dd3a91a1 1181 #ifdef __arm__
1182 do_clear_cache();
1183 #endif
57871462 1184
1185 // Don't trap writes
1186 invalid_code[block]=1;
94d23bb9 1187#ifndef DISABLE_TLB
57871462 1188 // If there is a valid TLB entry for this page, remove write protect
1189 if(tlb_LUT_w[block]) {
1190 assert(tlb_LUT_r[block]==tlb_LUT_w[block]);
1191 // CHECK: Is this right?
1192 memory_map[block]=((tlb_LUT_w[block]&0xFFFFF000)-(block<<12)+(unsigned int)rdram-0x80000000)>>2;
1193 u_int real_block=tlb_LUT_w[block]>>12;
1194 invalid_code[real_block]=1;
1195 if(real_block>=0x80000&&real_block<0x80800) memory_map[real_block]=((u_int)rdram-0x80000000)>>2;
1196 }
1197 else if(block>=0x80000&&block<0x80800) memory_map[block]=((u_int)rdram-0x80000000)>>2;
94d23bb9 1198#endif
f76eeef9 1199
57871462 1200 #ifdef USE_MINI_HT
1201 memset(mini_ht,-1,sizeof(mini_ht));
1202 #endif
1203}
9be4ba64 1204
1205void invalidate_block(u_int block)
1206{
1207 u_int page=get_page(block<<12);
1208 u_int vpage=get_vpage(block<<12);
1209 inv_debug("INVALIDATE: %x (%d)\n",block<<12,page);
1210 //inv_debug("invalid_code[block]=%d\n",invalid_code[block]);
1211 u_int first,last;
1212 first=last=page;
1213 struct ll_entry *head;
1214 head=jump_dirty[vpage];
1215 //printf("page=%d vpage=%d\n",page,vpage);
1216 while(head!=NULL) {
1217 u_int start,end;
1218 if(vpage>2047||(head->vaddr>>12)==block) { // Ignore vaddr hash collision
1219 get_bounds((int)head->addr,&start,&end);
1220 //printf("start: %x end: %x\n",start,end);
4a35de07 1221 if(page<2048&&start>=(u_int)rdram&&end<(u_int)rdram+RAM_SIZE) {
9be4ba64 1222 if(((start-(u_int)rdram)>>12)<=page&&((end-1-(u_int)rdram)>>12)>=page) {
1223 if((((start-(u_int)rdram)>>12)&2047)<first) first=((start-(u_int)rdram)>>12)&2047;
1224 if((((end-1-(u_int)rdram)>>12)&2047)>last) last=((end-1-(u_int)rdram)>>12)&2047;
1225 }
1226 }
1227#ifndef DISABLE_TLB
1228 if(page<2048&&(signed int)start>=(signed int)0xC0000000&&(signed int)end>=(signed int)0xC0000000) {
1229 if(((start+memory_map[start>>12]-(u_int)rdram)>>12)<=page&&((end-1+memory_map[(end-1)>>12]-(u_int)rdram)>>12)>=page) {
1230 if((((start+memory_map[start>>12]-(u_int)rdram)>>12)&2047)<first) first=((start+memory_map[start>>12]-(u_int)rdram)>>12)&2047;
1231 if((((end-1+memory_map[(end-1)>>12]-(u_int)rdram)>>12)&2047)>last) last=((end-1+memory_map[(end-1)>>12]-(u_int)rdram)>>12)&2047;
1232 }
1233 }
1234#endif
1235 }
1236 head=head->next;
1237 }
1238 invalidate_block_range(block,first,last);
1239}
1240
57871462 1241void invalidate_addr(u_int addr)
1242{
9be4ba64 1243#ifdef PCSX
1244 //static int rhits;
1245 // this check is done by the caller
1246 //if (inv_code_start<=addr&&addr<=inv_code_end) { rhits++; return; }
d25604ca 1247 u_int page=get_vpage(addr);
9be4ba64 1248 if(page<2048) { // RAM
1249 struct ll_entry *head;
1250 u_int addr_min=~0, addr_max=0;
4a35de07 1251 u_int mask=RAM_SIZE-1;
1252 u_int addr_main=0x80000000|(addr&mask);
9be4ba64 1253 int pg1;
4a35de07 1254 inv_code_start=addr_main&~0xfff;
1255 inv_code_end=addr_main|0xfff;
9be4ba64 1256 pg1=page;
1257 if (pg1>0) {
1258 // must check previous page too because of spans..
1259 pg1--;
1260 inv_code_start-=0x1000;
1261 }
1262 for(;pg1<=page;pg1++) {
1263 for(head=jump_dirty[pg1];head!=NULL;head=head->next) {
1264 u_int start,end;
1265 get_bounds((int)head->addr,&start,&end);
4a35de07 1266 if(ram_offset) {
1267 start-=ram_offset;
1268 end-=ram_offset;
1269 }
1270 if(start<=addr_main&&addr_main<end) {
9be4ba64 1271 if(start<addr_min) addr_min=start;
1272 if(end>addr_max) addr_max=end;
1273 }
4a35de07 1274 else if(addr_main<start) {
9be4ba64 1275 if(start<inv_code_end)
1276 inv_code_end=start-1;
1277 }
1278 else {
1279 if(end>inv_code_start)
1280 inv_code_start=end;
1281 }
1282 }
1283 }
1284 if (addr_min!=~0) {
1285 inv_debug("INV ADDR: %08x hit %08x-%08x\n", addr, addr_min, addr_max);
1286 inv_code_start=inv_code_end=~0;
1287 invalidate_block_range(addr>>12,(addr_min&mask)>>12,(addr_max&mask)>>12);
1288 return;
1289 }
1290 else {
4a35de07 1291 inv_code_start=(addr&~mask)|(inv_code_start&mask);
1292 inv_code_end=(addr&~mask)|(inv_code_end&mask);
d25604ca 1293 inv_debug("INV ADDR: %08x miss, inv %08x-%08x, sk %d\n", addr, inv_code_start, inv_code_end, 0);
9be4ba64 1294 return;
d25604ca 1295 }
9be4ba64 1296 }
1297#endif
57871462 1298 invalidate_block(addr>>12);
1299}
9be4ba64 1300
dd3a91a1 1301// This is called when loading a save state.
1302// Anything could have changed, so invalidate everything.
57871462 1303void invalidate_all_pages()
1304{
1305 u_int page,n;
1306 for(page=0;page<4096;page++)
1307 invalidate_page(page);
1308 for(page=0;page<1048576;page++)
1309 if(!invalid_code[page]) {
1310 restore_candidate[(page&2047)>>3]|=1<<(page&7);
1311 restore_candidate[((page&2047)>>3)+256]|=1<<(page&7);
1312 }
1313 #ifdef __arm__
1314 __clear_cache((void *)BASE_ADDR,(void *)BASE_ADDR+(1<<TARGET_SIZE_2));
1315 #endif
1316 #ifdef USE_MINI_HT
1317 memset(mini_ht,-1,sizeof(mini_ht));
1318 #endif
94d23bb9 1319 #ifndef DISABLE_TLB
57871462 1320 // TLB
1321 for(page=0;page<0x100000;page++) {
1322 if(tlb_LUT_r[page]) {
1323 memory_map[page]=((tlb_LUT_r[page]&0xFFFFF000)-(page<<12)+(unsigned int)rdram-0x80000000)>>2;
1324 if(!tlb_LUT_w[page]||!invalid_code[page])
1325 memory_map[page]|=0x40000000; // Write protect
1326 }
1327 else memory_map[page]=-1;
1328 if(page==0x80000) page=0xC0000;
1329 }
1330 tlb_hacks();
94d23bb9 1331 #endif
57871462 1332}
1333
1334// Add an entry to jump_out after making a link
1335void add_link(u_int vaddr,void *src)
1336{
94d23bb9 1337 u_int page=get_page(vaddr);
57871462 1338 inv_debug("add_link: %x -> %x (%d)\n",(int)src,vaddr,page);
76f71c27 1339 int *ptr=(int *)(src+4);
1340 assert((*ptr&0x0fff0000)==0x059f0000);
57871462 1341 ll_add(jump_out+page,vaddr,src);
1342 //int ptr=get_pointer(src);
1343 //inv_debug("add_link: Pointer is to %x\n",(int)ptr);
1344}
1345
1346// If a code block was found to be unmodified (bit was set in
1347// restore_candidate) and it remains unmodified (bit is clear
1348// in invalid_code) then move the entries for that 4K page from
1349// the dirty list to the clean list.
1350void clean_blocks(u_int page)
1351{
1352 struct ll_entry *head;
1353 inv_debug("INV: clean_blocks page=%d\n",page);
1354 head=jump_dirty[page];
1355 while(head!=NULL) {
1356 if(!invalid_code[head->vaddr>>12]) {
1357 // Don't restore blocks which are about to expire from the cache
1358 if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2))) {
1359 u_int start,end;
1360 if(verify_dirty((int)head->addr)) {
1361 //printf("Possibly Restore %x (%x)\n",head->vaddr, (int)head->addr);
1362 u_int i;
1363 u_int inv=0;
1364 get_bounds((int)head->addr,&start,&end);
4cb76aa4 1365 if(start-(u_int)rdram<RAM_SIZE) {
57871462 1366 for(i=(start-(u_int)rdram+0x80000000)>>12;i<=(end-1-(u_int)rdram+0x80000000)>>12;i++) {
1367 inv|=invalid_code[i];
1368 }
1369 }
63cb0298 1370#ifndef DISABLE_TLB
57871462 1371 if((signed int)head->vaddr>=(signed int)0xC0000000) {
1372 u_int addr = (head->vaddr+(memory_map[head->vaddr>>12]<<2));
1373 //printf("addr=%x start=%x end=%x\n",addr,start,end);
1374 if(addr<start||addr>=end) inv=1;
1375 }
63cb0298 1376#endif
4cb76aa4 1377 else if((signed int)head->vaddr>=(signed int)0x80000000+RAM_SIZE) {
57871462 1378 inv=1;
1379 }
1380 if(!inv) {
1381 void * clean_addr=(void *)get_clean_addr((int)head->addr);
1382 if((((u_int)clean_addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2))) {
1383 u_int ppage=page;
94d23bb9 1384#ifndef DISABLE_TLB
57871462 1385 if(page<2048&&tlb_LUT_r[head->vaddr>>12]) ppage=(tlb_LUT_r[head->vaddr>>12]^0x80000000)>>12;
94d23bb9 1386#endif
57871462 1387 inv_debug("INV: Restored %x (%x/%x)\n",head->vaddr, (int)head->addr, (int)clean_addr);
1388 //printf("page=%x, addr=%x\n",page,head->vaddr);
1389 //assert(head->vaddr>>12==(page|0x80000));
1390 ll_add_32(jump_in+ppage,head->vaddr,head->reg32,clean_addr);
1391 int *ht_bin=hash_table[((head->vaddr>>16)^head->vaddr)&0xFFFF];
1392 if(!head->reg32) {
1393 if(ht_bin[0]==head->vaddr) {
1394 ht_bin[1]=(int)clean_addr; // Replace existing entry
1395 }
1396 if(ht_bin[2]==head->vaddr) {
1397 ht_bin[3]=(int)clean_addr; // Replace existing entry
1398 }
1399 }
1400 }
1401 }
1402 }
1403 }
1404 }
1405 head=head->next;
1406 }
1407}
1408
1409
1410void mov_alloc(struct regstat *current,int i)
1411{
1412 // Note: Don't need to actually alloc the source registers
1413 if((~current->is32>>rs1[i])&1) {
1414 //alloc_reg64(current,i,rs1[i]);
1415 alloc_reg64(current,i,rt1[i]);
1416 current->is32&=~(1LL<<rt1[i]);
1417 } else {
1418 //alloc_reg(current,i,rs1[i]);
1419 alloc_reg(current,i,rt1[i]);
1420 current->is32|=(1LL<<rt1[i]);
1421 }
1422 clear_const(current,rs1[i]);
1423 clear_const(current,rt1[i]);
1424 dirty_reg(current,rt1[i]);
1425}
1426
1427void shiftimm_alloc(struct regstat *current,int i)
1428{
57871462 1429 if(opcode2[i]<=0x3) // SLL/SRL/SRA
1430 {
1431 if(rt1[i]) {
1432 if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1433 else lt1[i]=rs1[i];
1434 alloc_reg(current,i,rt1[i]);
1435 current->is32|=1LL<<rt1[i];
1436 dirty_reg(current,rt1[i]);
dc49e339 1437 if(is_const(current,rs1[i])) {
1438 int v=get_const(current,rs1[i]);
1439 if(opcode2[i]==0x00) set_const(current,rt1[i],v<<imm[i]);
1440 if(opcode2[i]==0x02) set_const(current,rt1[i],(u_int)v>>imm[i]);
1441 if(opcode2[i]==0x03) set_const(current,rt1[i],v>>imm[i]);
1442 }
1443 else clear_const(current,rt1[i]);
57871462 1444 }
1445 }
dc49e339 1446 else
1447 {
1448 clear_const(current,rs1[i]);
1449 clear_const(current,rt1[i]);
1450 }
1451
57871462 1452 if(opcode2[i]>=0x38&&opcode2[i]<=0x3b) // DSLL/DSRL/DSRA
1453 {
1454 if(rt1[i]) {
1455 if(rs1[i]) alloc_reg64(current,i,rs1[i]);
1456 alloc_reg64(current,i,rt1[i]);
1457 current->is32&=~(1LL<<rt1[i]);
1458 dirty_reg(current,rt1[i]);
1459 }
1460 }
1461 if(opcode2[i]==0x3c) // DSLL32
1462 {
1463 if(rt1[i]) {
1464 if(rs1[i]) alloc_reg(current,i,rs1[i]);
1465 alloc_reg64(current,i,rt1[i]);
1466 current->is32&=~(1LL<<rt1[i]);
1467 dirty_reg(current,rt1[i]);
1468 }
1469 }
1470 if(opcode2[i]==0x3e) // DSRL32
1471 {
1472 if(rt1[i]) {
1473 alloc_reg64(current,i,rs1[i]);
1474 if(imm[i]==32) {
1475 alloc_reg64(current,i,rt1[i]);
1476 current->is32&=~(1LL<<rt1[i]);
1477 } else {
1478 alloc_reg(current,i,rt1[i]);
1479 current->is32|=1LL<<rt1[i];
1480 }
1481 dirty_reg(current,rt1[i]);
1482 }
1483 }
1484 if(opcode2[i]==0x3f) // DSRA32
1485 {
1486 if(rt1[i]) {
1487 alloc_reg64(current,i,rs1[i]);
1488 alloc_reg(current,i,rt1[i]);
1489 current->is32|=1LL<<rt1[i];
1490 dirty_reg(current,rt1[i]);
1491 }
1492 }
1493}
1494
1495void shift_alloc(struct regstat *current,int i)
1496{
1497 if(rt1[i]) {
1498 if(opcode2[i]<=0x07) // SLLV/SRLV/SRAV
1499 {
1500 if(rs1[i]) alloc_reg(current,i,rs1[i]);
1501 if(rs2[i]) alloc_reg(current,i,rs2[i]);
1502 alloc_reg(current,i,rt1[i]);
e1190b87 1503 if(rt1[i]==rs2[i]) {
1504 alloc_reg_temp(current,i,-1);
1505 minimum_free_regs[i]=1;
1506 }
57871462 1507 current->is32|=1LL<<rt1[i];
1508 } else { // DSLLV/DSRLV/DSRAV
1509 if(rs1[i]) alloc_reg64(current,i,rs1[i]);
1510 if(rs2[i]) alloc_reg(current,i,rs2[i]);
1511 alloc_reg64(current,i,rt1[i]);
1512 current->is32&=~(1LL<<rt1[i]);
1513 if(opcode2[i]==0x16||opcode2[i]==0x17) // DSRLV and DSRAV need a temporary register
e1190b87 1514 {
57871462 1515 alloc_reg_temp(current,i,-1);
e1190b87 1516 minimum_free_regs[i]=1;
1517 }
57871462 1518 }
1519 clear_const(current,rs1[i]);
1520 clear_const(current,rs2[i]);
1521 clear_const(current,rt1[i]);
1522 dirty_reg(current,rt1[i]);
1523 }
1524}
1525
1526void alu_alloc(struct regstat *current,int i)
1527{
1528 if(opcode2[i]>=0x20&&opcode2[i]<=0x23) { // ADD/ADDU/SUB/SUBU
1529 if(rt1[i]) {
1530 if(rs1[i]&&rs2[i]) {
1531 alloc_reg(current,i,rs1[i]);
1532 alloc_reg(current,i,rs2[i]);
1533 }
1534 else {
1535 if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1536 if(rs2[i]&&needed_again(rs2[i],i)) alloc_reg(current,i,rs2[i]);
1537 }
1538 alloc_reg(current,i,rt1[i]);
1539 }
1540 current->is32|=1LL<<rt1[i];
1541 }
1542 if(opcode2[i]==0x2a||opcode2[i]==0x2b) { // SLT/SLTU
1543 if(rt1[i]) {
1544 if(!((current->is32>>rs1[i])&(current->is32>>rs2[i])&1))
1545 {
1546 alloc_reg64(current,i,rs1[i]);
1547 alloc_reg64(current,i,rs2[i]);
1548 alloc_reg(current,i,rt1[i]);
1549 } else {
1550 alloc_reg(current,i,rs1[i]);
1551 alloc_reg(current,i,rs2[i]);
1552 alloc_reg(current,i,rt1[i]);
1553 }
1554 }
1555 current->is32|=1LL<<rt1[i];
1556 }
1557 if(opcode2[i]>=0x24&&opcode2[i]<=0x27) { // AND/OR/XOR/NOR
1558 if(rt1[i]) {
1559 if(rs1[i]&&rs2[i]) {
1560 alloc_reg(current,i,rs1[i]);
1561 alloc_reg(current,i,rs2[i]);
1562 }
1563 else
1564 {
1565 if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1566 if(rs2[i]&&needed_again(rs2[i],i)) alloc_reg(current,i,rs2[i]);
1567 }
1568 alloc_reg(current,i,rt1[i]);
1569 if(!((current->is32>>rs1[i])&(current->is32>>rs2[i])&1))
1570 {
1571 if(!((current->uu>>rt1[i])&1)) {
1572 alloc_reg64(current,i,rt1[i]);
1573 }
1574 if(get_reg(current->regmap,rt1[i]|64)>=0) {
1575 if(rs1[i]&&rs2[i]) {
1576 alloc_reg64(current,i,rs1[i]);
1577 alloc_reg64(current,i,rs2[i]);
1578 }
1579 else
1580 {
1581 // Is is really worth it to keep 64-bit values in registers?
1582 #ifdef NATIVE_64BIT
1583 if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg64(current,i,rs1[i]);
1584 if(rs2[i]&&needed_again(rs2[i],i)) alloc_reg64(current,i,rs2[i]);
1585 #endif
1586 }
1587 }
1588 current->is32&=~(1LL<<rt1[i]);
1589 } else {
1590 current->is32|=1LL<<rt1[i];
1591 }
1592 }
1593 }
1594 if(opcode2[i]>=0x2c&&opcode2[i]<=0x2f) { // DADD/DADDU/DSUB/DSUBU
1595 if(rt1[i]) {
1596 if(rs1[i]&&rs2[i]) {
1597 if(!((current->uu>>rt1[i])&1)||get_reg(current->regmap,rt1[i]|64)>=0) {
1598 alloc_reg64(current,i,rs1[i]);
1599 alloc_reg64(current,i,rs2[i]);
1600 alloc_reg64(current,i,rt1[i]);
1601 } else {
1602 alloc_reg(current,i,rs1[i]);
1603 alloc_reg(current,i,rs2[i]);
1604 alloc_reg(current,i,rt1[i]);
1605 }
1606 }
1607 else {
1608 alloc_reg(current,i,rt1[i]);
1609 if(!((current->uu>>rt1[i])&1)||get_reg(current->regmap,rt1[i]|64)>=0) {
1610 // DADD used as move, or zeroing
1611 // If we have a 64-bit source, then make the target 64 bits too
1612 if(rs1[i]&&!((current->is32>>rs1[i])&1)) {
1613 if(get_reg(current->regmap,rs1[i])>=0) alloc_reg64(current,i,rs1[i]);
1614 alloc_reg64(current,i,rt1[i]);
1615 } else if(rs2[i]&&!((current->is32>>rs2[i])&1)) {
1616 if(get_reg(current->regmap,rs2[i])>=0) alloc_reg64(current,i,rs2[i]);
1617 alloc_reg64(current,i,rt1[i]);
1618 }
1619 if(opcode2[i]>=0x2e&&rs2[i]) {
1620 // DSUB used as negation - 64-bit result
1621 // If we have a 32-bit register, extend it to 64 bits
1622 if(get_reg(current->regmap,rs2[i])>=0) alloc_reg64(current,i,rs2[i]);
1623 alloc_reg64(current,i,rt1[i]);
1624 }
1625 }
1626 }
1627 if(rs1[i]&&rs2[i]) {
1628 current->is32&=~(1LL<<rt1[i]);
1629 } else if(rs1[i]) {
1630 current->is32&=~(1LL<<rt1[i]);
1631 if((current->is32>>rs1[i])&1)
1632 current->is32|=1LL<<rt1[i];
1633 } else if(rs2[i]) {
1634 current->is32&=~(1LL<<rt1[i]);
1635 if((current->is32>>rs2[i])&1)
1636 current->is32|=1LL<<rt1[i];
1637 } else {
1638 current->is32|=1LL<<rt1[i];
1639 }
1640 }
1641 }
1642 clear_const(current,rs1[i]);
1643 clear_const(current,rs2[i]);
1644 clear_const(current,rt1[i]);
1645 dirty_reg(current,rt1[i]);
1646}
1647
1648void imm16_alloc(struct regstat *current,int i)
1649{
1650 if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1651 else lt1[i]=rs1[i];
1652 if(rt1[i]) alloc_reg(current,i,rt1[i]);
1653 if(opcode[i]==0x18||opcode[i]==0x19) { // DADDI/DADDIU
1654 current->is32&=~(1LL<<rt1[i]);
1655 if(!((current->uu>>rt1[i])&1)||get_reg(current->regmap,rt1[i]|64)>=0) {
1656 // TODO: Could preserve the 32-bit flag if the immediate is zero
1657 alloc_reg64(current,i,rt1[i]);
1658 alloc_reg64(current,i,rs1[i]);
1659 }
1660 clear_const(current,rs1[i]);
1661 clear_const(current,rt1[i]);
1662 }
1663 else if(opcode[i]==0x0a||opcode[i]==0x0b) { // SLTI/SLTIU
1664 if((~current->is32>>rs1[i])&1) alloc_reg64(current,i,rs1[i]);
1665 current->is32|=1LL<<rt1[i];
1666 clear_const(current,rs1[i]);
1667 clear_const(current,rt1[i]);
1668 }
1669 else if(opcode[i]>=0x0c&&opcode[i]<=0x0e) { // ANDI/ORI/XORI
1670 if(((~current->is32>>rs1[i])&1)&&opcode[i]>0x0c) {
1671 if(rs1[i]!=rt1[i]) {
1672 if(needed_again(rs1[i],i)) alloc_reg64(current,i,rs1[i]);
1673 alloc_reg64(current,i,rt1[i]);
1674 current->is32&=~(1LL<<rt1[i]);
1675 }
1676 }
1677 else current->is32|=1LL<<rt1[i]; // ANDI clears upper bits
1678 if(is_const(current,rs1[i])) {
1679 int v=get_const(current,rs1[i]);
1680 if(opcode[i]==0x0c) set_const(current,rt1[i],v&imm[i]);
1681 if(opcode[i]==0x0d) set_const(current,rt1[i],v|imm[i]);
1682 if(opcode[i]==0x0e) set_const(current,rt1[i],v^imm[i]);
1683 }
1684 else clear_const(current,rt1[i]);
1685 }
1686 else if(opcode[i]==0x08||opcode[i]==0x09) { // ADDI/ADDIU
1687 if(is_const(current,rs1[i])) {
1688 int v=get_const(current,rs1[i]);
1689 set_const(current,rt1[i],v+imm[i]);
1690 }
1691 else clear_const(current,rt1[i]);
1692 current->is32|=1LL<<rt1[i];
1693 }
1694 else {
1695 set_const(current,rt1[i],((long long)((short)imm[i]))<<16); // LUI
1696 current->is32|=1LL<<rt1[i];
1697 }
1698 dirty_reg(current,rt1[i]);
1699}
1700
1701void load_alloc(struct regstat *current,int i)
1702{
1703 clear_const(current,rt1[i]);
1704 //if(rs1[i]!=rt1[i]&&needed_again(rs1[i],i)) clear_const(current,rs1[i]); // Does this help or hurt?
1705 if(!rs1[i]) current->u&=~1LL; // Allow allocating r0 if it's the source register
1706 if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
373d1d07 1707 if(rt1[i]&&!((current->u>>rt1[i])&1)) {
57871462 1708 alloc_reg(current,i,rt1[i]);
373d1d07 1709 assert(get_reg(current->regmap,rt1[i])>=0);
57871462 1710 if(opcode[i]==0x27||opcode[i]==0x37) // LWU/LD
1711 {
1712 current->is32&=~(1LL<<rt1[i]);
1713 alloc_reg64(current,i,rt1[i]);
1714 }
1715 else if(opcode[i]==0x1A||opcode[i]==0x1B) // LDL/LDR
1716 {
1717 current->is32&=~(1LL<<rt1[i]);
1718 alloc_reg64(current,i,rt1[i]);
1719 alloc_all(current,i);
1720 alloc_reg64(current,i,FTEMP);
e1190b87 1721 minimum_free_regs[i]=HOST_REGS;
57871462 1722 }
1723 else current->is32|=1LL<<rt1[i];
1724 dirty_reg(current,rt1[i]);
1725 // If using TLB, need a register for pointer to the mapping table
1726 if(using_tlb) alloc_reg(current,i,TLREG);
1727 // LWL/LWR need a temporary register for the old value
1728 if(opcode[i]==0x22||opcode[i]==0x26)
1729 {
1730 alloc_reg(current,i,FTEMP);
1731 alloc_reg_temp(current,i,-1);
e1190b87 1732 minimum_free_regs[i]=1;
57871462 1733 }
1734 }
1735 else
1736 {
373d1d07 1737 // Load to r0 or unneeded register (dummy load)
57871462 1738 // but we still need a register to calculate the address
535d208a 1739 if(opcode[i]==0x22||opcode[i]==0x26)
1740 {
1741 alloc_reg(current,i,FTEMP); // LWL/LWR need another temporary
1742 }
373d1d07 1743 // If using TLB, need a register for pointer to the mapping table
1744 if(using_tlb) alloc_reg(current,i,TLREG);
57871462 1745 alloc_reg_temp(current,i,-1);
e1190b87 1746 minimum_free_regs[i]=1;
535d208a 1747 if(opcode[i]==0x1A||opcode[i]==0x1B) // LDL/LDR
1748 {
1749 alloc_all(current,i);
1750 alloc_reg64(current,i,FTEMP);
e1190b87 1751 minimum_free_regs[i]=HOST_REGS;
535d208a 1752 }
57871462 1753 }
1754}
1755
1756void store_alloc(struct regstat *current,int i)
1757{
1758 clear_const(current,rs2[i]);
1759 if(!(rs2[i])) current->u&=~1LL; // Allow allocating r0 if necessary
1760 if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1761 alloc_reg(current,i,rs2[i]);
1762 if(opcode[i]==0x2c||opcode[i]==0x2d||opcode[i]==0x3f) { // 64-bit SDL/SDR/SD
1763 alloc_reg64(current,i,rs2[i]);
1764 if(rs2[i]) alloc_reg(current,i,FTEMP);
1765 }
1766 // If using TLB, need a register for pointer to the mapping table
1767 if(using_tlb) alloc_reg(current,i,TLREG);
1768 #if defined(HOST_IMM8)
1769 // On CPUs without 32-bit immediates we need a pointer to invalid_code
1770 else alloc_reg(current,i,INVCP);
1771 #endif
b7918751 1772 if(opcode[i]==0x2a||opcode[i]==0x2e||opcode[i]==0x2c||opcode[i]==0x2d) { // SWL/SWL/SDL/SDR
57871462 1773 alloc_reg(current,i,FTEMP);
1774 }
1775 // We need a temporary register for address generation
1776 alloc_reg_temp(current,i,-1);
e1190b87 1777 minimum_free_regs[i]=1;
57871462 1778}
1779
1780void c1ls_alloc(struct regstat *current,int i)
1781{
1782 //clear_const(current,rs1[i]); // FIXME
1783 clear_const(current,rt1[i]);
1784 if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1785 alloc_reg(current,i,CSREG); // Status
1786 alloc_reg(current,i,FTEMP);
1787 if(opcode[i]==0x35||opcode[i]==0x3d) { // 64-bit LDC1/SDC1
1788 alloc_reg64(current,i,FTEMP);
1789 }
1790 // If using TLB, need a register for pointer to the mapping table
1791 if(using_tlb) alloc_reg(current,i,TLREG);
1792 #if defined(HOST_IMM8)
1793 // On CPUs without 32-bit immediates we need a pointer to invalid_code
1794 else if((opcode[i]&0x3b)==0x39) // SWC1/SDC1
1795 alloc_reg(current,i,INVCP);
1796 #endif
1797 // We need a temporary register for address generation
1798 alloc_reg_temp(current,i,-1);
1799}
1800
b9b61529 1801void c2ls_alloc(struct regstat *current,int i)
1802{
1803 clear_const(current,rt1[i]);
1804 if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1805 alloc_reg(current,i,FTEMP);
1806 // If using TLB, need a register for pointer to the mapping table
1807 if(using_tlb) alloc_reg(current,i,TLREG);
1808 #if defined(HOST_IMM8)
1809 // On CPUs without 32-bit immediates we need a pointer to invalid_code
1810 else if((opcode[i]&0x3b)==0x3a) // SWC2/SDC2
1811 alloc_reg(current,i,INVCP);
1812 #endif
1813 // We need a temporary register for address generation
1814 alloc_reg_temp(current,i,-1);
e1190b87 1815 minimum_free_regs[i]=1;
b9b61529 1816}
1817
57871462 1818#ifndef multdiv_alloc
1819void multdiv_alloc(struct regstat *current,int i)
1820{
1821 // case 0x18: MULT
1822 // case 0x19: MULTU
1823 // case 0x1A: DIV
1824 // case 0x1B: DIVU
1825 // case 0x1C: DMULT
1826 // case 0x1D: DMULTU
1827 // case 0x1E: DDIV
1828 // case 0x1F: DDIVU
1829 clear_const(current,rs1[i]);
1830 clear_const(current,rs2[i]);
1831 if(rs1[i]&&rs2[i])
1832 {
1833 if((opcode2[i]&4)==0) // 32-bit
1834 {
1835 current->u&=~(1LL<<HIREG);
1836 current->u&=~(1LL<<LOREG);
1837 alloc_reg(current,i,HIREG);
1838 alloc_reg(current,i,LOREG);
1839 alloc_reg(current,i,rs1[i]);
1840 alloc_reg(current,i,rs2[i]);
1841 current->is32|=1LL<<HIREG;
1842 current->is32|=1LL<<LOREG;
1843 dirty_reg(current,HIREG);
1844 dirty_reg(current,LOREG);
1845 }
1846 else // 64-bit
1847 {
1848 current->u&=~(1LL<<HIREG);
1849 current->u&=~(1LL<<LOREG);
1850 current->uu&=~(1LL<<HIREG);
1851 current->uu&=~(1LL<<LOREG);
1852 alloc_reg64(current,i,HIREG);
1853 //if(HOST_REGS>10) alloc_reg64(current,i,LOREG);
1854 alloc_reg64(current,i,rs1[i]);
1855 alloc_reg64(current,i,rs2[i]);
1856 alloc_all(current,i);
1857 current->is32&=~(1LL<<HIREG);
1858 current->is32&=~(1LL<<LOREG);
1859 dirty_reg(current,HIREG);
1860 dirty_reg(current,LOREG);
e1190b87 1861 minimum_free_regs[i]=HOST_REGS;
57871462 1862 }
1863 }
1864 else
1865 {
1866 // Multiply by zero is zero.
1867 // MIPS does not have a divide by zero exception.
1868 // The result is undefined, we return zero.
1869 alloc_reg(current,i,HIREG);
1870 alloc_reg(current,i,LOREG);
1871 current->is32|=1LL<<HIREG;
1872 current->is32|=1LL<<LOREG;
1873 dirty_reg(current,HIREG);
1874 dirty_reg(current,LOREG);
1875 }
1876}
1877#endif
1878
1879void cop0_alloc(struct regstat *current,int i)
1880{
1881 if(opcode2[i]==0) // MFC0
1882 {
1883 if(rt1[i]) {
1884 clear_const(current,rt1[i]);
1885 alloc_all(current,i);
1886 alloc_reg(current,i,rt1[i]);
1887 current->is32|=1LL<<rt1[i];
1888 dirty_reg(current,rt1[i]);
1889 }
1890 }
1891 else if(opcode2[i]==4) // MTC0
1892 {
1893 if(rs1[i]){
1894 clear_const(current,rs1[i]);
1895 alloc_reg(current,i,rs1[i]);
1896 alloc_all(current,i);
1897 }
1898 else {
1899 alloc_all(current,i); // FIXME: Keep r0
1900 current->u&=~1LL;
1901 alloc_reg(current,i,0);
1902 }
1903 }
1904 else
1905 {
1906 // TLBR/TLBWI/TLBWR/TLBP/ERET
1907 assert(opcode2[i]==0x10);
1908 alloc_all(current,i);
1909 }
e1190b87 1910 minimum_free_regs[i]=HOST_REGS;
57871462 1911}
1912
1913void cop1_alloc(struct regstat *current,int i)
1914{
1915 alloc_reg(current,i,CSREG); // Load status
1916 if(opcode2[i]<3) // MFC1/DMFC1/CFC1
1917 {
7de557a6 1918 if(rt1[i]){
1919 clear_const(current,rt1[i]);
1920 if(opcode2[i]==1) {
1921 alloc_reg64(current,i,rt1[i]); // DMFC1
1922 current->is32&=~(1LL<<rt1[i]);
1923 }else{
1924 alloc_reg(current,i,rt1[i]); // MFC1/CFC1
1925 current->is32|=1LL<<rt1[i];
1926 }
1927 dirty_reg(current,rt1[i]);
57871462 1928 }
57871462 1929 alloc_reg_temp(current,i,-1);
1930 }
1931 else if(opcode2[i]>3) // MTC1/DMTC1/CTC1
1932 {
1933 if(rs1[i]){
1934 clear_const(current,rs1[i]);
1935 if(opcode2[i]==5)
1936 alloc_reg64(current,i,rs1[i]); // DMTC1
1937 else
1938 alloc_reg(current,i,rs1[i]); // MTC1/CTC1
1939 alloc_reg_temp(current,i,-1);
1940 }
1941 else {
1942 current->u&=~1LL;
1943 alloc_reg(current,i,0);
1944 alloc_reg_temp(current,i,-1);
1945 }
1946 }
e1190b87 1947 minimum_free_regs[i]=1;
57871462 1948}
1949void fconv_alloc(struct regstat *current,int i)
1950{
1951 alloc_reg(current,i,CSREG); // Load status
1952 alloc_reg_temp(current,i,-1);
e1190b87 1953 minimum_free_regs[i]=1;
57871462 1954}
1955void float_alloc(struct regstat *current,int i)
1956{
1957 alloc_reg(current,i,CSREG); // Load status
1958 alloc_reg_temp(current,i,-1);
e1190b87 1959 minimum_free_regs[i]=1;
57871462 1960}
b9b61529 1961void c2op_alloc(struct regstat *current,int i)
1962{
1963 alloc_reg_temp(current,i,-1);
1964}
57871462 1965void fcomp_alloc(struct regstat *current,int i)
1966{
1967 alloc_reg(current,i,CSREG); // Load status
1968 alloc_reg(current,i,FSREG); // Load flags
1969 dirty_reg(current,FSREG); // Flag will be modified
1970 alloc_reg_temp(current,i,-1);
e1190b87 1971 minimum_free_regs[i]=1;
57871462 1972}
1973
1974void syscall_alloc(struct regstat *current,int i)
1975{
1976 alloc_cc(current,i);
1977 dirty_reg(current,CCREG);
1978 alloc_all(current,i);
e1190b87 1979 minimum_free_regs[i]=HOST_REGS;
57871462 1980 current->isconst=0;
1981}
1982
1983void delayslot_alloc(struct regstat *current,int i)
1984{
1985 switch(itype[i]) {
1986 case UJUMP:
1987 case CJUMP:
1988 case SJUMP:
1989 case RJUMP:
1990 case FJUMP:
1991 case SYSCALL:
7139f3c8 1992 case HLECALL:
57871462 1993 case SPAN:
1994 assem_debug("jump in the delay slot. this shouldn't happen.\n");//exit(1);
1995 printf("Disabled speculative precompilation\n");
1996 stop_after_jal=1;
1997 break;
1998 case IMM16:
1999 imm16_alloc(current,i);
2000 break;
2001 case LOAD:
2002 case LOADLR:
2003 load_alloc(current,i);
2004 break;
2005 case STORE:
2006 case STORELR:
2007 store_alloc(current,i);
2008 break;
2009 case ALU:
2010 alu_alloc(current,i);
2011 break;
2012 case SHIFT:
2013 shift_alloc(current,i);
2014 break;
2015 case MULTDIV:
2016 multdiv_alloc(current,i);
2017 break;
2018 case SHIFTIMM:
2019 shiftimm_alloc(current,i);
2020 break;
2021 case MOV:
2022 mov_alloc(current,i);
2023 break;
2024 case COP0:
2025 cop0_alloc(current,i);
2026 break;
2027 case COP1:
b9b61529 2028 case COP2:
57871462 2029 cop1_alloc(current,i);
2030 break;
2031 case C1LS:
2032 c1ls_alloc(current,i);
2033 break;
b9b61529 2034 case C2LS:
2035 c2ls_alloc(current,i);
2036 break;
57871462 2037 case FCONV:
2038 fconv_alloc(current,i);
2039 break;
2040 case FLOAT:
2041 float_alloc(current,i);
2042 break;
2043 case FCOMP:
2044 fcomp_alloc(current,i);
2045 break;
b9b61529 2046 case C2OP:
2047 c2op_alloc(current,i);
2048 break;
57871462 2049 }
2050}
2051
2052// Special case where a branch and delay slot span two pages in virtual memory
2053static void pagespan_alloc(struct regstat *current,int i)
2054{
2055 current->isconst=0;
2056 current->wasconst=0;
2057 regs[i].wasconst=0;
e1190b87 2058 minimum_free_regs[i]=HOST_REGS;
57871462 2059 alloc_all(current,i);
2060 alloc_cc(current,i);
2061 dirty_reg(current,CCREG);
2062 if(opcode[i]==3) // JAL
2063 {
2064 alloc_reg(current,i,31);
2065 dirty_reg(current,31);
2066 }
2067 if(opcode[i]==0&&(opcode2[i]&0x3E)==8) // JR/JALR
2068 {
2069 alloc_reg(current,i,rs1[i]);
5067f341 2070 if (rt1[i]!=0) {
2071 alloc_reg(current,i,rt1[i]);
2072 dirty_reg(current,rt1[i]);
57871462 2073 }
2074 }
2075 if((opcode[i]&0x2E)==4) // BEQ/BNE/BEQL/BNEL
2076 {
2077 if(rs1[i]) alloc_reg(current,i,rs1[i]);
2078 if(rs2[i]) alloc_reg(current,i,rs2[i]);
2079 if(!((current->is32>>rs1[i])&(current->is32>>rs2[i])&1))
2080 {
2081 if(rs1[i]) alloc_reg64(current,i,rs1[i]);
2082 if(rs2[i]) alloc_reg64(current,i,rs2[i]);
2083 }
2084 }
2085 else
2086 if((opcode[i]&0x2E)==6) // BLEZ/BGTZ/BLEZL/BGTZL
2087 {
2088 if(rs1[i]) alloc_reg(current,i,rs1[i]);
2089 if(!((current->is32>>rs1[i])&1))
2090 {
2091 if(rs1[i]) alloc_reg64(current,i,rs1[i]);
2092 }
2093 }
2094 else
2095 if(opcode[i]==0x11) // BC1
2096 {
2097 alloc_reg(current,i,FSREG);
2098 alloc_reg(current,i,CSREG);
2099 }
2100 //else ...
2101}
2102
2103add_stub(int type,int addr,int retaddr,int a,int b,int c,int d,int e)
2104{
2105 stubs[stubcount][0]=type;
2106 stubs[stubcount][1]=addr;
2107 stubs[stubcount][2]=retaddr;
2108 stubs[stubcount][3]=a;
2109 stubs[stubcount][4]=b;
2110 stubs[stubcount][5]=c;
2111 stubs[stubcount][6]=d;
2112 stubs[stubcount][7]=e;
2113 stubcount++;
2114}
2115
2116// Write out a single register
2117void wb_register(signed char r,signed char regmap[],uint64_t dirty,uint64_t is32)
2118{
2119 int hr;
2120 for(hr=0;hr<HOST_REGS;hr++) {
2121 if(hr!=EXCLUDE_REG) {
2122 if((regmap[hr]&63)==r) {
2123 if((dirty>>hr)&1) {
2124 if(regmap[hr]<64) {
2125 emit_storereg(r,hr);
24385cae 2126#ifndef FORCE32
57871462 2127 if((is32>>regmap[hr])&1) {
2128 emit_sarimm(hr,31,hr);
2129 emit_storereg(r|64,hr);
2130 }
24385cae 2131#endif
57871462 2132 }else{
2133 emit_storereg(r|64,hr);
2134 }
2135 }
2136 }
2137 }
2138 }
2139}
2140
2141int mchecksum()
2142{
2143 //if(!tracedebug) return 0;
2144 int i;
2145 int sum=0;
2146 for(i=0;i<2097152;i++) {
2147 unsigned int temp=sum;
2148 sum<<=1;
2149 sum|=(~temp)>>31;
2150 sum^=((u_int *)rdram)[i];
2151 }
2152 return sum;
2153}
2154int rchecksum()
2155{
2156 int i;
2157 int sum=0;
2158 for(i=0;i<64;i++)
2159 sum^=((u_int *)reg)[i];
2160 return sum;
2161}
57871462 2162void rlist()
2163{
2164 int i;
2165 printf("TRACE: ");
2166 for(i=0;i<32;i++)
2167 printf("r%d:%8x%8x ",i,((int *)(reg+i))[1],((int *)(reg+i))[0]);
2168 printf("\n");
3d624f89 2169#ifndef DISABLE_COP1
57871462 2170 printf("TRACE: ");
2171 for(i=0;i<32;i++)
2172 printf("f%d:%8x%8x ",i,((int*)reg_cop1_simple[i])[1],*((int*)reg_cop1_simple[i]));
2173 printf("\n");
3d624f89 2174#endif
57871462 2175}
2176
2177void enabletrace()
2178{
2179 tracedebug=1;
2180}
2181
2182void memdebug(int i)
2183{
2184 //printf("TRACE: count=%d next=%d (checksum %x) lo=%8x%8x\n",Count,next_interupt,mchecksum(),(int)(reg[LOREG]>>32),(int)reg[LOREG]);
2185 //printf("TRACE: count=%d next=%d (rchecksum %x)\n",Count,next_interupt,rchecksum());
2186 //rlist();
2187 //if(tracedebug) {
2188 //if(Count>=-2084597794) {
2189 if((signed int)Count>=-2084597794&&(signed int)Count<0) {
2190 //if(0) {
2191 printf("TRACE: count=%d next=%d (checksum %x)\n",Count,next_interupt,mchecksum());
2192 //printf("TRACE: count=%d next=%d (checksum %x) Status=%x\n",Count,next_interupt,mchecksum(),Status);
2193 //printf("TRACE: count=%d next=%d (checksum %x) hi=%8x%8x\n",Count,next_interupt,mchecksum(),(int)(reg[HIREG]>>32),(int)reg[HIREG]);
2194 rlist();
2195 #ifdef __i386__
2196 printf("TRACE: %x\n",(&i)[-1]);
2197 #endif
2198 #ifdef __arm__
2199 int j;
2200 printf("TRACE: %x \n",(&j)[10]);
2201 printf("TRACE: %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x\n",(&j)[1],(&j)[2],(&j)[3],(&j)[4],(&j)[5],(&j)[6],(&j)[7],(&j)[8],(&j)[9],(&j)[10],(&j)[11],(&j)[12],(&j)[13],(&j)[14],(&j)[15],(&j)[16],(&j)[17],(&j)[18],(&j)[19],(&j)[20]);
2202 #endif
2203 //fflush(stdout);
2204 }
2205 //printf("TRACE: %x\n",(&i)[-1]);
2206}
2207
2208void tlb_debug(u_int cause, u_int addr, u_int iaddr)
2209{
2210 printf("TLB Exception: instruction=%x addr=%x cause=%x\n",iaddr, addr, cause);
2211}
2212
2213void alu_assemble(int i,struct regstat *i_regs)
2214{
2215 if(opcode2[i]>=0x20&&opcode2[i]<=0x23) { // ADD/ADDU/SUB/SUBU
2216 if(rt1[i]) {
2217 signed char s1,s2,t;
2218 t=get_reg(i_regs->regmap,rt1[i]);
2219 if(t>=0) {
2220 s1=get_reg(i_regs->regmap,rs1[i]);
2221 s2=get_reg(i_regs->regmap,rs2[i]);
2222 if(rs1[i]&&rs2[i]) {
2223 assert(s1>=0);
2224 assert(s2>=0);
2225 if(opcode2[i]&2) emit_sub(s1,s2,t);
2226 else emit_add(s1,s2,t);
2227 }
2228 else if(rs1[i]) {
2229 if(s1>=0) emit_mov(s1,t);
2230 else emit_loadreg(rs1[i],t);
2231 }
2232 else if(rs2[i]) {
2233 if(s2>=0) {
2234 if(opcode2[i]&2) emit_neg(s2,t);
2235 else emit_mov(s2,t);
2236 }
2237 else {
2238 emit_loadreg(rs2[i],t);
2239 if(opcode2[i]&2) emit_neg(t,t);
2240 }
2241 }
2242 else emit_zeroreg(t);
2243 }
2244 }
2245 }
2246 if(opcode2[i]>=0x2c&&opcode2[i]<=0x2f) { // DADD/DADDU/DSUB/DSUBU
2247 if(rt1[i]) {
2248 signed char s1l,s2l,s1h,s2h,tl,th;
2249 tl=get_reg(i_regs->regmap,rt1[i]);
2250 th=get_reg(i_regs->regmap,rt1[i]|64);
2251 if(tl>=0) {
2252 s1l=get_reg(i_regs->regmap,rs1[i]);
2253 s2l=get_reg(i_regs->regmap,rs2[i]);
2254 s1h=get_reg(i_regs->regmap,rs1[i]|64);
2255 s2h=get_reg(i_regs->regmap,rs2[i]|64);
2256 if(rs1[i]&&rs2[i]) {
2257 assert(s1l>=0);
2258 assert(s2l>=0);
2259 if(opcode2[i]&2) emit_subs(s1l,s2l,tl);
2260 else emit_adds(s1l,s2l,tl);
2261 if(th>=0) {
2262 #ifdef INVERTED_CARRY
2263 if(opcode2[i]&2) {if(s1h!=th) emit_mov(s1h,th);emit_sbb(th,s2h);}
2264 #else
2265 if(opcode2[i]&2) emit_sbc(s1h,s2h,th);
2266 #endif
2267 else emit_add(s1h,s2h,th);
2268 }
2269 }
2270 else if(rs1[i]) {
2271 if(s1l>=0) emit_mov(s1l,tl);
2272 else emit_loadreg(rs1[i],tl);
2273 if(th>=0) {
2274 if(s1h>=0) emit_mov(s1h,th);
2275 else emit_loadreg(rs1[i]|64,th);
2276 }
2277 }
2278 else if(rs2[i]) {
2279 if(s2l>=0) {
2280 if(opcode2[i]&2) emit_negs(s2l,tl);
2281 else emit_mov(s2l,tl);
2282 }
2283 else {
2284 emit_loadreg(rs2[i],tl);
2285 if(opcode2[i]&2) emit_negs(tl,tl);
2286 }
2287 if(th>=0) {
2288 #ifdef INVERTED_CARRY
2289 if(s2h>=0) emit_mov(s2h,th);
2290 else emit_loadreg(rs2[i]|64,th);
2291 if(opcode2[i]&2) {
2292 emit_adcimm(-1,th); // x86 has inverted carry flag
2293 emit_not(th,th);
2294 }
2295 #else
2296 if(opcode2[i]&2) {
2297 if(s2h>=0) emit_rscimm(s2h,0,th);
2298 else {
2299 emit_loadreg(rs2[i]|64,th);
2300 emit_rscimm(th,0,th);
2301 }
2302 }else{
2303 if(s2h>=0) emit_mov(s2h,th);
2304 else emit_loadreg(rs2[i]|64,th);
2305 }
2306 #endif
2307 }
2308 }
2309 else {
2310 emit_zeroreg(tl);
2311 if(th>=0) emit_zeroreg(th);
2312 }
2313 }
2314 }
2315 }
2316 if(opcode2[i]==0x2a||opcode2[i]==0x2b) { // SLT/SLTU
2317 if(rt1[i]) {
2318 signed char s1l,s1h,s2l,s2h,t;
2319 if(!((i_regs->was32>>rs1[i])&(i_regs->was32>>rs2[i])&1))
2320 {
2321 t=get_reg(i_regs->regmap,rt1[i]);
2322 //assert(t>=0);
2323 if(t>=0) {
2324 s1l=get_reg(i_regs->regmap,rs1[i]);
2325 s1h=get_reg(i_regs->regmap,rs1[i]|64);
2326 s2l=get_reg(i_regs->regmap,rs2[i]);
2327 s2h=get_reg(i_regs->regmap,rs2[i]|64);
2328 if(rs2[i]==0) // rx<r0
2329 {
2330 assert(s1h>=0);
2331 if(opcode2[i]==0x2a) // SLT
2332 emit_shrimm(s1h,31,t);
2333 else // SLTU (unsigned can not be less than zero)
2334 emit_zeroreg(t);
2335 }
2336 else if(rs1[i]==0) // r0<rx
2337 {
2338 assert(s2h>=0);
2339 if(opcode2[i]==0x2a) // SLT
2340 emit_set_gz64_32(s2h,s2l,t);
2341 else // SLTU (set if not zero)
2342 emit_set_nz64_32(s2h,s2l,t);
2343 }
2344 else {
2345 assert(s1l>=0);assert(s1h>=0);
2346 assert(s2l>=0);assert(s2h>=0);
2347 if(opcode2[i]==0x2a) // SLT
2348 emit_set_if_less64_32(s1h,s1l,s2h,s2l,t);
2349 else // SLTU
2350 emit_set_if_carry64_32(s1h,s1l,s2h,s2l,t);
2351 }
2352 }
2353 } else {
2354 t=get_reg(i_regs->regmap,rt1[i]);
2355 //assert(t>=0);
2356 if(t>=0) {
2357 s1l=get_reg(i_regs->regmap,rs1[i]);
2358 s2l=get_reg(i_regs->regmap,rs2[i]);
2359 if(rs2[i]==0) // rx<r0
2360 {
2361 assert(s1l>=0);
2362 if(opcode2[i]==0x2a) // SLT
2363 emit_shrimm(s1l,31,t);
2364 else // SLTU (unsigned can not be less than zero)
2365 emit_zeroreg(t);
2366 }
2367 else if(rs1[i]==0) // r0<rx
2368 {
2369 assert(s2l>=0);
2370 if(opcode2[i]==0x2a) // SLT
2371 emit_set_gz32(s2l,t);
2372 else // SLTU (set if not zero)
2373 emit_set_nz32(s2l,t);
2374 }
2375 else{
2376 assert(s1l>=0);assert(s2l>=0);
2377 if(opcode2[i]==0x2a) // SLT
2378 emit_set_if_less32(s1l,s2l,t);
2379 else // SLTU
2380 emit_set_if_carry32(s1l,s2l,t);
2381 }
2382 }
2383 }
2384 }
2385 }
2386 if(opcode2[i]>=0x24&&opcode2[i]<=0x27) { // AND/OR/XOR/NOR
2387 if(rt1[i]) {
2388 signed char s1l,s1h,s2l,s2h,th,tl;
2389 tl=get_reg(i_regs->regmap,rt1[i]);
2390 th=get_reg(i_regs->regmap,rt1[i]|64);
2391 if(!((i_regs->was32>>rs1[i])&(i_regs->was32>>rs2[i])&1)&&th>=0)
2392 {
2393 assert(tl>=0);
2394 if(tl>=0) {
2395 s1l=get_reg(i_regs->regmap,rs1[i]);
2396 s1h=get_reg(i_regs->regmap,rs1[i]|64);
2397 s2l=get_reg(i_regs->regmap,rs2[i]);
2398 s2h=get_reg(i_regs->regmap,rs2[i]|64);
2399 if(rs1[i]&&rs2[i]) {
2400 assert(s1l>=0);assert(s1h>=0);
2401 assert(s2l>=0);assert(s2h>=0);
2402 if(opcode2[i]==0x24) { // AND
2403 emit_and(s1l,s2l,tl);
2404 emit_and(s1h,s2h,th);
2405 } else
2406 if(opcode2[i]==0x25) { // OR
2407 emit_or(s1l,s2l,tl);
2408 emit_or(s1h,s2h,th);
2409 } else
2410 if(opcode2[i]==0x26) { // XOR
2411 emit_xor(s1l,s2l,tl);
2412 emit_xor(s1h,s2h,th);
2413 } else
2414 if(opcode2[i]==0x27) { // NOR
2415 emit_or(s1l,s2l,tl);
2416 emit_or(s1h,s2h,th);
2417 emit_not(tl,tl);
2418 emit_not(th,th);
2419 }
2420 }
2421 else
2422 {
2423 if(opcode2[i]==0x24) { // AND
2424 emit_zeroreg(tl);
2425 emit_zeroreg(th);
2426 } else
2427 if(opcode2[i]==0x25||opcode2[i]==0x26) { // OR/XOR
2428 if(rs1[i]){
2429 if(s1l>=0) emit_mov(s1l,tl);
2430 else emit_loadreg(rs1[i],tl);
2431 if(s1h>=0) emit_mov(s1h,th);
2432 else emit_loadreg(rs1[i]|64,th);
2433 }
2434 else
2435 if(rs2[i]){
2436 if(s2l>=0) emit_mov(s2l,tl);
2437 else emit_loadreg(rs2[i],tl);
2438 if(s2h>=0) emit_mov(s2h,th);
2439 else emit_loadreg(rs2[i]|64,th);
2440 }
2441 else{
2442 emit_zeroreg(tl);
2443 emit_zeroreg(th);
2444 }
2445 } else
2446 if(opcode2[i]==0x27) { // NOR
2447 if(rs1[i]){
2448 if(s1l>=0) emit_not(s1l,tl);
2449 else{
2450 emit_loadreg(rs1[i],tl);
2451 emit_not(tl,tl);
2452 }
2453 if(s1h>=0) emit_not(s1h,th);
2454 else{
2455 emit_loadreg(rs1[i]|64,th);
2456 emit_not(th,th);
2457 }
2458 }
2459 else
2460 if(rs2[i]){
2461 if(s2l>=0) emit_not(s2l,tl);
2462 else{
2463 emit_loadreg(rs2[i],tl);
2464 emit_not(tl,tl);
2465 }
2466 if(s2h>=0) emit_not(s2h,th);
2467 else{
2468 emit_loadreg(rs2[i]|64,th);
2469 emit_not(th,th);
2470 }
2471 }
2472 else {
2473 emit_movimm(-1,tl);
2474 emit_movimm(-1,th);
2475 }
2476 }
2477 }
2478 }
2479 }
2480 else
2481 {
2482 // 32 bit
2483 if(tl>=0) {
2484 s1l=get_reg(i_regs->regmap,rs1[i]);
2485 s2l=get_reg(i_regs->regmap,rs2[i]);
2486 if(rs1[i]&&rs2[i]) {
2487 assert(s1l>=0);
2488 assert(s2l>=0);
2489 if(opcode2[i]==0x24) { // AND
2490 emit_and(s1l,s2l,tl);
2491 } else
2492 if(opcode2[i]==0x25) { // OR
2493 emit_or(s1l,s2l,tl);
2494 } else
2495 if(opcode2[i]==0x26) { // XOR
2496 emit_xor(s1l,s2l,tl);
2497 } else
2498 if(opcode2[i]==0x27) { // NOR
2499 emit_or(s1l,s2l,tl);
2500 emit_not(tl,tl);
2501 }
2502 }
2503 else
2504 {
2505 if(opcode2[i]==0x24) { // AND
2506 emit_zeroreg(tl);
2507 } else
2508 if(opcode2[i]==0x25||opcode2[i]==0x26) { // OR/XOR
2509 if(rs1[i]){
2510 if(s1l>=0) emit_mov(s1l,tl);
2511 else emit_loadreg(rs1[i],tl); // CHECK: regmap_entry?
2512 }
2513 else
2514 if(rs2[i]){
2515 if(s2l>=0) emit_mov(s2l,tl);
2516 else emit_loadreg(rs2[i],tl); // CHECK: regmap_entry?
2517 }
2518 else emit_zeroreg(tl);
2519 } else
2520 if(opcode2[i]==0x27) { // NOR
2521 if(rs1[i]){
2522 if(s1l>=0) emit_not(s1l,tl);
2523 else {
2524 emit_loadreg(rs1[i],tl);
2525 emit_not(tl,tl);
2526 }
2527 }
2528 else
2529 if(rs2[i]){
2530 if(s2l>=0) emit_not(s2l,tl);
2531 else {
2532 emit_loadreg(rs2[i],tl);
2533 emit_not(tl,tl);
2534 }
2535 }
2536 else emit_movimm(-1,tl);
2537 }
2538 }
2539 }
2540 }
2541 }
2542 }
2543}
2544
2545void imm16_assemble(int i,struct regstat *i_regs)
2546{
2547 if (opcode[i]==0x0f) { // LUI
2548 if(rt1[i]) {
2549 signed char t;
2550 t=get_reg(i_regs->regmap,rt1[i]);
2551 //assert(t>=0);
2552 if(t>=0) {
2553 if(!((i_regs->isconst>>t)&1))
2554 emit_movimm(imm[i]<<16,t);
2555 }
2556 }
2557 }
2558 if(opcode[i]==0x08||opcode[i]==0x09) { // ADDI/ADDIU
2559 if(rt1[i]) {
2560 signed char s,t;
2561 t=get_reg(i_regs->regmap,rt1[i]);
2562 s=get_reg(i_regs->regmap,rs1[i]);
2563 if(rs1[i]) {
2564 //assert(t>=0);
2565 //assert(s>=0);
2566 if(t>=0) {
2567 if(!((i_regs->isconst>>t)&1)) {
2568 if(s<0) {
2569 if(i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2570 emit_addimm(t,imm[i],t);
2571 }else{
2572 if(!((i_regs->wasconst>>s)&1))
2573 emit_addimm(s,imm[i],t);
2574 else
2575 emit_movimm(constmap[i][s]+imm[i],t);
2576 }
2577 }
2578 }
2579 } else {
2580 if(t>=0) {
2581 if(!((i_regs->isconst>>t)&1))
2582 emit_movimm(imm[i],t);
2583 }
2584 }
2585 }
2586 }
2587 if(opcode[i]==0x18||opcode[i]==0x19) { // DADDI/DADDIU
2588 if(rt1[i]) {
2589 signed char sh,sl,th,tl;
2590 th=get_reg(i_regs->regmap,rt1[i]|64);
2591 tl=get_reg(i_regs->regmap,rt1[i]);
2592 sh=get_reg(i_regs->regmap,rs1[i]|64);
2593 sl=get_reg(i_regs->regmap,rs1[i]);
2594 if(tl>=0) {
2595 if(rs1[i]) {
2596 assert(sh>=0);
2597 assert(sl>=0);
2598 if(th>=0) {
2599 emit_addimm64_32(sh,sl,imm[i],th,tl);
2600 }
2601 else {
2602 emit_addimm(sl,imm[i],tl);
2603 }
2604 } else {
2605 emit_movimm(imm[i],tl);
2606 if(th>=0) emit_movimm(((signed int)imm[i])>>31,th);
2607 }
2608 }
2609 }
2610 }
2611 else if(opcode[i]==0x0a||opcode[i]==0x0b) { // SLTI/SLTIU
2612 if(rt1[i]) {
2613 //assert(rs1[i]!=0); // r0 might be valid, but it's probably a bug
2614 signed char sh,sl,t;
2615 t=get_reg(i_regs->regmap,rt1[i]);
2616 sh=get_reg(i_regs->regmap,rs1[i]|64);
2617 sl=get_reg(i_regs->regmap,rs1[i]);
2618 //assert(t>=0);
2619 if(t>=0) {
2620 if(rs1[i]>0) {
2621 if(sh<0) assert((i_regs->was32>>rs1[i])&1);
2622 if(sh<0||((i_regs->was32>>rs1[i])&1)) {
2623 if(opcode[i]==0x0a) { // SLTI
2624 if(sl<0) {
2625 if(i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2626 emit_slti32(t,imm[i],t);
2627 }else{
2628 emit_slti32(sl,imm[i],t);
2629 }
2630 }
2631 else { // SLTIU
2632 if(sl<0) {
2633 if(i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2634 emit_sltiu32(t,imm[i],t);
2635 }else{
2636 emit_sltiu32(sl,imm[i],t);
2637 }
2638 }
2639 }else{ // 64-bit
2640 assert(sl>=0);
2641 if(opcode[i]==0x0a) // SLTI
2642 emit_slti64_32(sh,sl,imm[i],t);
2643 else // SLTIU
2644 emit_sltiu64_32(sh,sl,imm[i],t);
2645 }
2646 }else{
2647 // SLTI(U) with r0 is just stupid,
2648 // nonetheless examples can be found
2649 if(opcode[i]==0x0a) // SLTI
2650 if(0<imm[i]) emit_movimm(1,t);
2651 else emit_zeroreg(t);
2652 else // SLTIU
2653 {
2654 if(imm[i]) emit_movimm(1,t);
2655 else emit_zeroreg(t);
2656 }
2657 }
2658 }
2659 }
2660 }
2661 else if(opcode[i]>=0x0c&&opcode[i]<=0x0e) { // ANDI/ORI/XORI
2662 if(rt1[i]) {
2663 signed char sh,sl,th,tl;
2664 th=get_reg(i_regs->regmap,rt1[i]|64);
2665 tl=get_reg(i_regs->regmap,rt1[i]);
2666 sh=get_reg(i_regs->regmap,rs1[i]|64);
2667 sl=get_reg(i_regs->regmap,rs1[i]);
2668 if(tl>=0 && !((i_regs->isconst>>tl)&1)) {
2669 if(opcode[i]==0x0c) //ANDI
2670 {
2671 if(rs1[i]) {
2672 if(sl<0) {
2673 if(i_regs->regmap_entry[tl]!=rs1[i]) emit_loadreg(rs1[i],tl);
2674 emit_andimm(tl,imm[i],tl);
2675 }else{
2676 if(!((i_regs->wasconst>>sl)&1))
2677 emit_andimm(sl,imm[i],tl);
2678 else
2679 emit_movimm(constmap[i][sl]&imm[i],tl);
2680 }
2681 }
2682 else
2683 emit_zeroreg(tl);
2684 if(th>=0) emit_zeroreg(th);
2685 }
2686 else
2687 {
2688 if(rs1[i]) {
2689 if(sl<0) {
2690 if(i_regs->regmap_entry[tl]!=rs1[i]) emit_loadreg(rs1[i],tl);
2691 }
2692 if(th>=0) {
2693 if(sh<0) {
2694 emit_loadreg(rs1[i]|64,th);
2695 }else{
2696 emit_mov(sh,th);
2697 }
2698 }
2699 if(opcode[i]==0x0d) //ORI
2700 if(sl<0) {
2701 emit_orimm(tl,imm[i],tl);
2702 }else{
2703 if(!((i_regs->wasconst>>sl)&1))
2704 emit_orimm(sl,imm[i],tl);
2705 else
2706 emit_movimm(constmap[i][sl]|imm[i],tl);
2707 }
2708 if(opcode[i]==0x0e) //XORI
2709 if(sl<0) {
2710 emit_xorimm(tl,imm[i],tl);
2711 }else{
2712 if(!((i_regs->wasconst>>sl)&1))
2713 emit_xorimm(sl,imm[i],tl);
2714 else
2715 emit_movimm(constmap[i][sl]^imm[i],tl);
2716 }
2717 }
2718 else {
2719 emit_movimm(imm[i],tl);
2720 if(th>=0) emit_zeroreg(th);
2721 }
2722 }
2723 }
2724 }
2725 }
2726}
2727
2728void shiftimm_assemble(int i,struct regstat *i_regs)
2729{
2730 if(opcode2[i]<=0x3) // SLL/SRL/SRA
2731 {
2732 if(rt1[i]) {
2733 signed char s,t;
2734 t=get_reg(i_regs->regmap,rt1[i]);
2735 s=get_reg(i_regs->regmap,rs1[i]);
2736 //assert(t>=0);
dc49e339 2737 if(t>=0&&!((i_regs->isconst>>t)&1)){
57871462 2738 if(rs1[i]==0)
2739 {
2740 emit_zeroreg(t);
2741 }
2742 else
2743 {
2744 if(s<0&&i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2745 if(imm[i]) {
2746 if(opcode2[i]==0) // SLL
2747 {
2748 emit_shlimm(s<0?t:s,imm[i],t);
2749 }
2750 if(opcode2[i]==2) // SRL
2751 {
2752 emit_shrimm(s<0?t:s,imm[i],t);
2753 }
2754 if(opcode2[i]==3) // SRA
2755 {
2756 emit_sarimm(s<0?t:s,imm[i],t);
2757 }
2758 }else{
2759 // Shift by zero
2760 if(s>=0 && s!=t) emit_mov(s,t);
2761 }
2762 }
2763 }
2764 //emit_storereg(rt1[i],t); //DEBUG
2765 }
2766 }
2767 if(opcode2[i]>=0x38&&opcode2[i]<=0x3b) // DSLL/DSRL/DSRA
2768 {
2769 if(rt1[i]) {
2770 signed char sh,sl,th,tl;
2771 th=get_reg(i_regs->regmap,rt1[i]|64);
2772 tl=get_reg(i_regs->regmap,rt1[i]);
2773 sh=get_reg(i_regs->regmap,rs1[i]|64);
2774 sl=get_reg(i_regs->regmap,rs1[i]);
2775 if(tl>=0) {
2776 if(rs1[i]==0)
2777 {
2778 emit_zeroreg(tl);
2779 if(th>=0) emit_zeroreg(th);
2780 }
2781 else
2782 {
2783 assert(sl>=0);
2784 assert(sh>=0);
2785 if(imm[i]) {
2786 if(opcode2[i]==0x38) // DSLL
2787 {
2788 if(th>=0) emit_shldimm(sh,sl,imm[i],th);
2789 emit_shlimm(sl,imm[i],tl);
2790 }
2791 if(opcode2[i]==0x3a) // DSRL
2792 {
2793 emit_shrdimm(sl,sh,imm[i],tl);
2794 if(th>=0) emit_shrimm(sh,imm[i],th);
2795 }
2796 if(opcode2[i]==0x3b) // DSRA
2797 {
2798 emit_shrdimm(sl,sh,imm[i],tl);
2799 if(th>=0) emit_sarimm(sh,imm[i],th);
2800 }
2801 }else{
2802 // Shift by zero
2803 if(sl!=tl) emit_mov(sl,tl);
2804 if(th>=0&&sh!=th) emit_mov(sh,th);
2805 }
2806 }
2807 }
2808 }
2809 }
2810 if(opcode2[i]==0x3c) // DSLL32
2811 {
2812 if(rt1[i]) {
2813 signed char sl,tl,th;
2814 tl=get_reg(i_regs->regmap,rt1[i]);
2815 th=get_reg(i_regs->regmap,rt1[i]|64);
2816 sl=get_reg(i_regs->regmap,rs1[i]);
2817 if(th>=0||tl>=0){
2818 assert(tl>=0);
2819 assert(th>=0);
2820 assert(sl>=0);
2821 emit_mov(sl,th);
2822 emit_zeroreg(tl);
2823 if(imm[i]>32)
2824 {
2825 emit_shlimm(th,imm[i]&31,th);
2826 }
2827 }
2828 }
2829 }
2830 if(opcode2[i]==0x3e) // DSRL32
2831 {
2832 if(rt1[i]) {
2833 signed char sh,tl,th;
2834 tl=get_reg(i_regs->regmap,rt1[i]);
2835 th=get_reg(i_regs->regmap,rt1[i]|64);
2836 sh=get_reg(i_regs->regmap,rs1[i]|64);
2837 if(tl>=0){
2838 assert(sh>=0);
2839 emit_mov(sh,tl);
2840 if(th>=0) emit_zeroreg(th);
2841 if(imm[i]>32)
2842 {
2843 emit_shrimm(tl,imm[i]&31,tl);
2844 }
2845 }
2846 }
2847 }
2848 if(opcode2[i]==0x3f) // DSRA32
2849 {
2850 if(rt1[i]) {
2851 signed char sh,tl;
2852 tl=get_reg(i_regs->regmap,rt1[i]);
2853 sh=get_reg(i_regs->regmap,rs1[i]|64);
2854 if(tl>=0){
2855 assert(sh>=0);
2856 emit_mov(sh,tl);
2857 if(imm[i]>32)
2858 {
2859 emit_sarimm(tl,imm[i]&31,tl);
2860 }
2861 }
2862 }
2863 }
2864}
2865
2866#ifndef shift_assemble
2867void shift_assemble(int i,struct regstat *i_regs)
2868{
2869 printf("Need shift_assemble for this architecture.\n");
2870 exit(1);
2871}
2872#endif
2873
2874void load_assemble(int i,struct regstat *i_regs)
2875{
2876 int s,th,tl,addr,map=-1;
2877 int offset;
2878 int jaddr=0;
5bf843dc 2879 int memtarget=0,c=0;
b1570849 2880 int fastload_reg_override=0;
57871462 2881 u_int hr,reglist=0;
2882 th=get_reg(i_regs->regmap,rt1[i]|64);
2883 tl=get_reg(i_regs->regmap,rt1[i]);
2884 s=get_reg(i_regs->regmap,rs1[i]);
2885 offset=imm[i];
2886 for(hr=0;hr<HOST_REGS;hr++) {
2887 if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
2888 }
2889 if(i_regs->regmap[HOST_CCREG]==CCREG) reglist&=~(1<<HOST_CCREG);
2890 if(s>=0) {
2891 c=(i_regs->wasconst>>s)&1;
af4ee1fe 2892 if (c) {
2893 memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
2894 if(using_tlb&&((signed int)(constmap[i][s]+offset))>=(signed int)0xC0000000) memtarget=1;
2895 }
57871462 2896 }
57871462 2897 //printf("load_assemble: c=%d\n",c);
2898 //if(c) printf("load_assemble: const=%x\n",(int)constmap[i][s]+offset);
2899 // FIXME: Even if the load is a NOP, we should check for pagefaults...
5bf843dc 2900#ifdef PCSX
f18c0f46 2901 if(tl<0&&(!c||(((u_int)constmap[i][s]+offset)>>16)==0x1f80)
2902 ||rt1[i]==0) {
5bf843dc 2903 // could be FIFO, must perform the read
f18c0f46 2904 // ||dummy read
5bf843dc 2905 assem_debug("(forced read)\n");
2906 tl=get_reg(i_regs->regmap,-1);
2907 assert(tl>=0);
5bf843dc 2908 }
f18c0f46 2909#endif
5bf843dc 2910 if(offset||s<0||c) addr=tl;
2911 else addr=s;
535d208a 2912 //if(tl<0) tl=get_reg(i_regs->regmap,-1);
2913 if(tl>=0) {
2914 //printf("load_assemble: c=%d\n",c);
2915 //if(c) printf("load_assemble: const=%x\n",(int)constmap[i][s]+offset);
2916 assert(tl>=0); // Even if the load is a NOP, we must check for pagefaults and I/O
2917 reglist&=~(1<<tl);
2918 if(th>=0) reglist&=~(1<<th);
2919 if(!using_tlb) {
2920 if(!c) {
2921 #ifdef RAM_OFFSET
2922 map=get_reg(i_regs->regmap,ROREG);
2923 if(map<0) emit_loadreg(ROREG,map=HOST_TEMPREG);
2924 #endif
57871462 2925//#define R29_HACK 1
535d208a 2926 #ifdef R29_HACK
2927 // Strmnnrmn's speed hack
2928 if(rs1[i]!=29||start<0x80001000||start>=0x80000000+RAM_SIZE)
2929 #endif
2930 {
ffb0b9e0 2931 jaddr=emit_fastpath_cmp_jump(i,addr,&fastload_reg_override);
57871462 2932 }
535d208a 2933 }
a327ad27 2934 else if(ram_offset&&memtarget) {
2935 emit_addimm(addr,ram_offset,HOST_TEMPREG);
2936 fastload_reg_override=HOST_TEMPREG;
2937 }
535d208a 2938 }else{ // using tlb
2939 int x=0;
2940 if (opcode[i]==0x20||opcode[i]==0x24) x=3; // LB/LBU
2941 if (opcode[i]==0x21||opcode[i]==0x25) x=2; // LH/LHU
2942 map=get_reg(i_regs->regmap,TLREG);
2943 assert(map>=0);
ea3d2e6e 2944 reglist&=~(1<<map);
535d208a 2945 map=do_tlb_r(addr,tl,map,x,-1,-1,c,constmap[i][s]+offset);
2946 do_tlb_r_branch(map,c,constmap[i][s]+offset,&jaddr);
2947 }
2948 int dummy=(rt1[i]==0)||(tl!=get_reg(i_regs->regmap,rt1[i])); // ignore loads to r0 and unneeded reg
2949 if (opcode[i]==0x20) { // LB
2950 if(!c||memtarget) {
2951 if(!dummy) {
57871462 2952 #ifdef HOST_IMM_ADDR32
2953 if(c)
2954 emit_movsbl_tlb((constmap[i][s]+offset)^3,map,tl);
2955 else
2956 #endif
2957 {
2958 //emit_xorimm(addr,3,tl);
2959 //gen_tlb_addr_r(tl,map);
2960 //emit_movsbl_indexed((int)rdram-0x80000000,tl,tl);
535d208a 2961 int x=0,a=tl;
2002a1db 2962#ifdef BIG_ENDIAN_MIPS
57871462 2963 if(!c) emit_xorimm(addr,3,tl);
2964 else x=((constmap[i][s]+offset)^3)-(constmap[i][s]+offset);
2002a1db 2965#else
535d208a 2966 if(!c) a=addr;
dadf55f2 2967#endif
b1570849 2968 if(fastload_reg_override) a=fastload_reg_override;
2969
535d208a 2970 emit_movsbl_indexed_tlb(x,a,map,tl);
57871462 2971 }
57871462 2972 }
535d208a 2973 if(jaddr)
2974 add_stub(LOADB_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
57871462 2975 }
535d208a 2976 else
2977 inline_readstub(LOADB_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2978 }
2979 if (opcode[i]==0x21) { // LH
2980 if(!c||memtarget) {
2981 if(!dummy) {
57871462 2982 #ifdef HOST_IMM_ADDR32
2983 if(c)
2984 emit_movswl_tlb((constmap[i][s]+offset)^2,map,tl);
2985 else
2986 #endif
2987 {
535d208a 2988 int x=0,a=tl;
2002a1db 2989#ifdef BIG_ENDIAN_MIPS
57871462 2990 if(!c) emit_xorimm(addr,2,tl);
2991 else x=((constmap[i][s]+offset)^2)-(constmap[i][s]+offset);
2002a1db 2992#else
535d208a 2993 if(!c) a=addr;
dadf55f2 2994#endif
b1570849 2995 if(fastload_reg_override) a=fastload_reg_override;
57871462 2996 //#ifdef
2997 //emit_movswl_indexed_tlb(x,tl,map,tl);
2998 //else
2999 if(map>=0) {
535d208a 3000 gen_tlb_addr_r(a,map);
3001 emit_movswl_indexed(x,a,tl);
3002 }else{
a327ad27 3003 #if 1 //def RAM_OFFSET
535d208a 3004 emit_movswl_indexed(x,a,tl);
3005 #else
3006 emit_movswl_indexed((int)rdram-0x80000000+x,a,tl);
3007 #endif
3008 }
57871462 3009 }
57871462 3010 }
535d208a 3011 if(jaddr)
3012 add_stub(LOADH_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
57871462 3013 }
535d208a 3014 else
3015 inline_readstub(LOADH_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
3016 }
3017 if (opcode[i]==0x23) { // LW
3018 if(!c||memtarget) {
3019 if(!dummy) {
dadf55f2 3020 int a=addr;
b1570849 3021 if(fastload_reg_override) a=fastload_reg_override;
57871462 3022 //emit_readword_indexed((int)rdram-0x80000000,addr,tl);
3023 #ifdef HOST_IMM_ADDR32
3024 if(c)
3025 emit_readword_tlb(constmap[i][s]+offset,map,tl);
3026 else
3027 #endif
dadf55f2 3028 emit_readword_indexed_tlb(0,a,map,tl);
57871462 3029 }
535d208a 3030 if(jaddr)
3031 add_stub(LOADW_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
57871462 3032 }
535d208a 3033 else
3034 inline_readstub(LOADW_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
3035 }
3036 if (opcode[i]==0x24) { // LBU
3037 if(!c||memtarget) {
3038 if(!dummy) {
57871462 3039 #ifdef HOST_IMM_ADDR32
3040 if(c)
3041 emit_movzbl_tlb((constmap[i][s]+offset)^3,map,tl);
3042 else
3043 #endif
3044 {
3045 //emit_xorimm(addr,3,tl);
3046 //gen_tlb_addr_r(tl,map);
3047 //emit_movzbl_indexed((int)rdram-0x80000000,tl,tl);
535d208a 3048 int x=0,a=tl;
2002a1db 3049#ifdef BIG_ENDIAN_MIPS
57871462 3050 if(!c) emit_xorimm(addr,3,tl);
3051 else x=((constmap[i][s]+offset)^3)-(constmap[i][s]+offset);
2002a1db 3052#else
535d208a 3053 if(!c) a=addr;
dadf55f2 3054#endif
b1570849 3055 if(fastload_reg_override) a=fastload_reg_override;
3056
535d208a 3057 emit_movzbl_indexed_tlb(x,a,map,tl);
57871462 3058 }
57871462 3059 }
535d208a 3060 if(jaddr)
3061 add_stub(LOADBU_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
57871462 3062 }
535d208a 3063 else
3064 inline_readstub(LOADBU_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
3065 }
3066 if (opcode[i]==0x25) { // LHU
3067 if(!c||memtarget) {
3068 if(!dummy) {
57871462 3069 #ifdef HOST_IMM_ADDR32
3070 if(c)
3071 emit_movzwl_tlb((constmap[i][s]+offset)^2,map,tl);
3072 else
3073 #endif
3074 {
535d208a 3075 int x=0,a=tl;
2002a1db 3076#ifdef BIG_ENDIAN_MIPS
57871462 3077 if(!c) emit_xorimm(addr,2,tl);
3078 else x=((constmap[i][s]+offset)^2)-(constmap[i][s]+offset);
2002a1db 3079#else
535d208a 3080 if(!c) a=addr;
dadf55f2 3081#endif
b1570849 3082 if(fastload_reg_override) a=fastload_reg_override;
57871462 3083 //#ifdef
3084 //emit_movzwl_indexed_tlb(x,tl,map,tl);
3085 //#else
3086 if(map>=0) {
535d208a 3087 gen_tlb_addr_r(a,map);
3088 emit_movzwl_indexed(x,a,tl);
3089 }else{
a327ad27 3090 #if 1 //def RAM_OFFSET
535d208a 3091 emit_movzwl_indexed(x,a,tl);
3092 #else
3093 emit_movzwl_indexed((int)rdram-0x80000000+x,a,tl);
3094 #endif
3095 }
57871462 3096 }
3097 }
535d208a 3098 if(jaddr)
3099 add_stub(LOADHU_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
57871462 3100 }
535d208a 3101 else
3102 inline_readstub(LOADHU_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
3103 }
3104 if (opcode[i]==0x27) { // LWU
3105 assert(th>=0);
3106 if(!c||memtarget) {
3107 if(!dummy) {
dadf55f2 3108 int a=addr;
b1570849 3109 if(fastload_reg_override) a=fastload_reg_override;
57871462 3110 //emit_readword_indexed((int)rdram-0x80000000,addr,tl);
3111 #ifdef HOST_IMM_ADDR32
3112 if(c)
3113 emit_readword_tlb(constmap[i][s]+offset,map,tl);
3114 else
3115 #endif
dadf55f2 3116 emit_readword_indexed_tlb(0,a,map,tl);
57871462 3117 }
535d208a 3118 if(jaddr)
3119 add_stub(LOADW_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
3120 }
3121 else {
3122 inline_readstub(LOADW_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
57871462 3123 }
535d208a 3124 emit_zeroreg(th);
3125 }
3126 if (opcode[i]==0x37) { // LD
3127 if(!c||memtarget) {
3128 if(!dummy) {
dadf55f2 3129 int a=addr;
b1570849 3130 if(fastload_reg_override) a=fastload_reg_override;
57871462 3131 //gen_tlb_addr_r(tl,map);
3132 //if(th>=0) emit_readword_indexed((int)rdram-0x80000000,addr,th);
3133 //emit_readword_indexed((int)rdram-0x7FFFFFFC,addr,tl);
3134 #ifdef HOST_IMM_ADDR32
3135 if(c)
3136 emit_readdword_tlb(constmap[i][s]+offset,map,th,tl);
3137 else
3138 #endif
dadf55f2 3139 emit_readdword_indexed_tlb(0,a,map,th,tl);
57871462 3140 }
535d208a 3141 if(jaddr)
3142 add_stub(LOADD_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
57871462 3143 }
535d208a 3144 else
3145 inline_readstub(LOADD_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
57871462 3146 }
535d208a 3147 }
3148 //emit_storereg(rt1[i],tl); // DEBUG
57871462 3149 //if(opcode[i]==0x23)
3150 //if(opcode[i]==0x24)
3151 //if(opcode[i]==0x23||opcode[i]==0x24)
3152 /*if(opcode[i]==0x21||opcode[i]==0x23||opcode[i]==0x24)
3153 {
3154 //emit_pusha();
3155 save_regs(0x100f);
3156 emit_readword((int)&last_count,ECX);
3157 #ifdef __i386__
3158 if(get_reg(i_regs->regmap,CCREG)<0)
3159 emit_loadreg(CCREG,HOST_CCREG);
3160 emit_add(HOST_CCREG,ECX,HOST_CCREG);
3161 emit_addimm(HOST_CCREG,2*ccadj[i],HOST_CCREG);
3162 emit_writeword(HOST_CCREG,(int)&Count);
3163 #endif
3164 #ifdef __arm__
3165 if(get_reg(i_regs->regmap,CCREG)<0)
3166 emit_loadreg(CCREG,0);
3167 else
3168 emit_mov(HOST_CCREG,0);
3169 emit_add(0,ECX,0);
3170 emit_addimm(0,2*ccadj[i],0);
3171 emit_writeword(0,(int)&Count);
3172 #endif
3173 emit_call((int)memdebug);
3174 //emit_popa();
3175 restore_regs(0x100f);
3176 }/**/
3177}
3178
3179#ifndef loadlr_assemble
3180void loadlr_assemble(int i,struct regstat *i_regs)
3181{
3182 printf("Need loadlr_assemble for this architecture.\n");
3183 exit(1);
3184}
3185#endif
3186
3187void store_assemble(int i,struct regstat *i_regs)
3188{
3189 int s,th,tl,map=-1;
3190 int addr,temp;
3191 int offset;
3192 int jaddr=0,jaddr2,type;
666a299d 3193 int memtarget=0,c=0;
57871462 3194 int agr=AGEN1+(i&1);
b1570849 3195 int faststore_reg_override=0;
57871462 3196 u_int hr,reglist=0;
3197 th=get_reg(i_regs->regmap,rs2[i]|64);
3198 tl=get_reg(i_regs->regmap,rs2[i]);
3199 s=get_reg(i_regs->regmap,rs1[i]);
3200 temp=get_reg(i_regs->regmap,agr);
3201 if(temp<0) temp=get_reg(i_regs->regmap,-1);
3202 offset=imm[i];
3203 if(s>=0) {
3204 c=(i_regs->wasconst>>s)&1;
af4ee1fe 3205 if(c) {
3206 memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
3207 if(using_tlb&&((signed int)(constmap[i][s]+offset))>=(signed int)0xC0000000) memtarget=1;
3208 }
57871462 3209 }
3210 assert(tl>=0);
3211 assert(temp>=0);
3212 for(hr=0;hr<HOST_REGS;hr++) {
3213 if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
3214 }
3215 if(i_regs->regmap[HOST_CCREG]==CCREG) reglist&=~(1<<HOST_CCREG);
3216 if(offset||s<0||c) addr=temp;
3217 else addr=s;
3218 if(!using_tlb) {
3219 if(!c) {
ffb0b9e0 3220 #ifndef PCSX
57871462 3221 #ifdef R29_HACK
3222 // Strmnnrmn's speed hack
4cb76aa4 3223 if(rs1[i]!=29||start<0x80001000||start>=0x80000000+RAM_SIZE)
57871462 3224 #endif
4cb76aa4 3225 emit_cmpimm(addr,RAM_SIZE);
57871462 3226 #ifdef DESTRUCTIVE_SHIFT
3227 if(s==addr) emit_mov(s,temp);
3228 #endif
3229 #ifdef R29_HACK
dadf55f2 3230 memtarget=1;
4cb76aa4 3231 if(rs1[i]!=29||start<0x80001000||start>=0x80000000+RAM_SIZE)
57871462 3232 #endif
3233 {
3234 jaddr=(int)out;
3235 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
3236 // Hint to branch predictor that the branch is unlikely to be taken
3237 if(rs1[i]>=28)
3238 emit_jno_unlikely(0);
3239 else
3240 #endif
3241 emit_jno(0);
3242 }
ffb0b9e0 3243 #else
3244 jaddr=emit_fastpath_cmp_jump(i,addr,&faststore_reg_override);
3245 #endif
57871462 3246 }
a327ad27 3247 else if(ram_offset&&memtarget) {
3248 emit_addimm(addr,ram_offset,HOST_TEMPREG);
3249 faststore_reg_override=HOST_TEMPREG;
3250 }
57871462 3251 }else{ // using tlb
3252 int x=0;
3253 if (opcode[i]==0x28) x=3; // SB
3254 if (opcode[i]==0x29) x=2; // SH
3255 map=get_reg(i_regs->regmap,TLREG);
3256 assert(map>=0);
ea3d2e6e 3257 reglist&=~(1<<map);
57871462 3258 map=do_tlb_w(addr,temp,map,x,c,constmap[i][s]+offset);
3259 do_tlb_w_branch(map,c,constmap[i][s]+offset,&jaddr);
3260 }
3261
3262 if (opcode[i]==0x28) { // SB
3263 if(!c||memtarget) {
97a238a6 3264 int x=0,a=temp;
2002a1db 3265#ifdef BIG_ENDIAN_MIPS
57871462 3266 if(!c) emit_xorimm(addr,3,temp);
3267 else x=((constmap[i][s]+offset)^3)-(constmap[i][s]+offset);
2002a1db 3268#else
97a238a6 3269 if(!c) a=addr;
dadf55f2 3270#endif
b1570849 3271 if(faststore_reg_override) a=faststore_reg_override;
57871462 3272 //gen_tlb_addr_w(temp,map);
3273 //emit_writebyte_indexed(tl,(int)rdram-0x80000000,temp);
97a238a6 3274 emit_writebyte_indexed_tlb(tl,x,a,map,a);
57871462 3275 }
3276 type=STOREB_STUB;
3277 }
3278 if (opcode[i]==0x29) { // SH
3279 if(!c||memtarget) {
97a238a6 3280 int x=0,a=temp;
2002a1db 3281#ifdef BIG_ENDIAN_MIPS
57871462 3282 if(!c) emit_xorimm(addr,2,temp);
3283 else x=((constmap[i][s]+offset)^2)-(constmap[i][s]+offset);
2002a1db 3284#else
97a238a6 3285 if(!c) a=addr;
dadf55f2 3286#endif
b1570849 3287 if(faststore_reg_override) a=faststore_reg_override;
57871462 3288 //#ifdef
3289 //emit_writehword_indexed_tlb(tl,x,temp,map,temp);
3290 //#else
3291 if(map>=0) {
97a238a6 3292 gen_tlb_addr_w(a,map);
3293 emit_writehword_indexed(tl,x,a);
57871462 3294 }else
a327ad27 3295 //emit_writehword_indexed(tl,(int)rdram-0x80000000+x,a);
3296 emit_writehword_indexed(tl,x,a);
57871462 3297 }
3298 type=STOREH_STUB;
3299 }
3300 if (opcode[i]==0x2B) { // SW
dadf55f2 3301 if(!c||memtarget) {
3302 int a=addr;
b1570849 3303 if(faststore_reg_override) a=faststore_reg_override;
57871462 3304 //emit_writeword_indexed(tl,(int)rdram-0x80000000,addr);
dadf55f2 3305 emit_writeword_indexed_tlb(tl,0,a,map,temp);
3306 }
57871462 3307 type=STOREW_STUB;
3308 }
3309 if (opcode[i]==0x3F) { // SD
3310 if(!c||memtarget) {
dadf55f2 3311 int a=addr;
b1570849 3312 if(faststore_reg_override) a=faststore_reg_override;
57871462 3313 if(rs2[i]) {
3314 assert(th>=0);
3315 //emit_writeword_indexed(th,(int)rdram-0x80000000,addr);
3316 //emit_writeword_indexed(tl,(int)rdram-0x7FFFFFFC,addr);
dadf55f2 3317 emit_writedword_indexed_tlb(th,tl,0,a,map,temp);
57871462 3318 }else{
3319 // Store zero
3320 //emit_writeword_indexed(tl,(int)rdram-0x80000000,temp);
3321 //emit_writeword_indexed(tl,(int)rdram-0x7FFFFFFC,temp);
dadf55f2 3322 emit_writedword_indexed_tlb(tl,tl,0,a,map,temp);
57871462 3323 }
3324 }
3325 type=STORED_STUB;
3326 }
b96d3df7 3327#ifdef PCSX
3328 if(jaddr) {
3329 // PCSX store handlers don't check invcode again
3330 reglist|=1<<addr;
3331 add_stub(type,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
3332 jaddr=0;
3333 }
3334#endif
0ff8c62c 3335 if(!using_tlb&&!(i_regs->waswritten&(1<<rs1[i]))&&!(new_dynarec_hacks&NDHACK_NO_SMC_CHECK)) {
57871462 3336 if(!c||memtarget) {
3337 #ifdef DESTRUCTIVE_SHIFT
3338 // The x86 shift operation is 'destructive'; it overwrites the
3339 // source register, so we need to make a copy first and use that.
3340 addr=temp;
3341 #endif
3342 #if defined(HOST_IMM8)
3343 int ir=get_reg(i_regs->regmap,INVCP);
3344 assert(ir>=0);
3345 emit_cmpmem_indexedsr12_reg(ir,addr,1);
3346 #else
3347 emit_cmpmem_indexedsr12_imm((int)invalid_code,addr,1);
3348 #endif
0bbd1454 3349 #if defined(HAVE_CONDITIONAL_CALL) && !defined(DESTRUCTIVE_SHIFT)
3350 emit_callne(invalidate_addr_reg[addr]);
3351 #else
57871462 3352 jaddr2=(int)out;
3353 emit_jne(0);
3354 add_stub(INVCODE_STUB,jaddr2,(int)out,reglist|(1<<HOST_CCREG),addr,0,0,0);
0bbd1454 3355 #endif
57871462 3356 }
3357 }
7a518516 3358 u_int addr_val=constmap[i][s]+offset;
3eaa7048 3359 if(jaddr) {
3360 add_stub(type,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
3361 } else if(c&&!memtarget) {
7a518516 3362 inline_writestub(type,i,addr_val,i_regs->regmap,rs2[i],ccadj[i],reglist);
3363 }
3364 // basic current block modification detection..
3365 // not looking back as that should be in mips cache already
3366 if(c&&start+i*4<addr_val&&addr_val<start+slen*4) {
3367 printf("write to %08x hits block %08x, pc=%08x\n",addr_val,start,start+i*4);
3368 assert(i_regs->regmap==regs[i].regmap); // not delay slot
3369 if(i_regs->regmap==regs[i].regmap) {
3370 load_all_consts(regs[i].regmap_entry,regs[i].was32,regs[i].wasdirty,i);
3371 wb_dirtys(regs[i].regmap_entry,regs[i].was32,regs[i].wasdirty);
3372 emit_movimm(start+i*4+4,0);
3373 emit_writeword(0,(int)&pcaddr);
3374 emit_jmp((int)do_interrupt);
3375 }
3eaa7048 3376 }
57871462 3377 //if(opcode[i]==0x2B || opcode[i]==0x3F)
3378 //if(opcode[i]==0x2B || opcode[i]==0x28)
3379 //if(opcode[i]==0x2B || opcode[i]==0x29)
3380 //if(opcode[i]==0x2B)
3381 /*if(opcode[i]==0x2B || opcode[i]==0x28 || opcode[i]==0x29 || opcode[i]==0x3F)
3382 {
28d74ee8 3383 #ifdef __i386__
3384 emit_pusha();
3385 #endif
3386 #ifdef __arm__
57871462 3387 save_regs(0x100f);
28d74ee8 3388 #endif
57871462 3389 emit_readword((int)&last_count,ECX);
3390 #ifdef __i386__
3391 if(get_reg(i_regs->regmap,CCREG)<0)
3392 emit_loadreg(CCREG,HOST_CCREG);
3393 emit_add(HOST_CCREG,ECX,HOST_CCREG);
3394 emit_addimm(HOST_CCREG,2*ccadj[i],HOST_CCREG);
3395 emit_writeword(HOST_CCREG,(int)&Count);
3396 #endif
3397 #ifdef __arm__
3398 if(get_reg(i_regs->regmap,CCREG)<0)
3399 emit_loadreg(CCREG,0);
3400 else
3401 emit_mov(HOST_CCREG,0);
3402 emit_add(0,ECX,0);
3403 emit_addimm(0,2*ccadj[i],0);
3404 emit_writeword(0,(int)&Count);
3405 #endif
3406 emit_call((int)memdebug);
28d74ee8 3407 #ifdef __i386__
3408 emit_popa();
3409 #endif
3410 #ifdef __arm__
57871462 3411 restore_regs(0x100f);
28d74ee8 3412 #endif
57871462 3413 }/**/
3414}
3415
3416void storelr_assemble(int i,struct regstat *i_regs)
3417{
3418 int s,th,tl;
3419 int temp;
3420 int temp2;
3421 int offset;
3422 int jaddr=0,jaddr2;
3423 int case1,case2,case3;
3424 int done0,done1,done2;
af4ee1fe 3425 int memtarget=0,c=0;
fab5d06d 3426 int agr=AGEN1+(i&1);
57871462 3427 u_int hr,reglist=0;
3428 th=get_reg(i_regs->regmap,rs2[i]|64);
3429 tl=get_reg(i_regs->regmap,rs2[i]);
3430 s=get_reg(i_regs->regmap,rs1[i]);
fab5d06d 3431 temp=get_reg(i_regs->regmap,agr);
3432 if(temp<0) temp=get_reg(i_regs->regmap,-1);
57871462 3433 offset=imm[i];
3434 if(s>=0) {
3435 c=(i_regs->isconst>>s)&1;
af4ee1fe 3436 if(c) {
3437 memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
3438 if(using_tlb&&((signed int)(constmap[i][s]+offset))>=(signed int)0xC0000000) memtarget=1;
3439 }
57871462 3440 }
3441 assert(tl>=0);
3442 for(hr=0;hr<HOST_REGS;hr++) {
3443 if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
3444 }
535d208a 3445 assert(temp>=0);
3446 if(!using_tlb) {
3447 if(!c) {
3448 emit_cmpimm(s<0||offset?temp:s,RAM_SIZE);
3449 if(!offset&&s!=temp) emit_mov(s,temp);
3450 jaddr=(int)out;
3451 emit_jno(0);
3452 }
3453 else
3454 {
3455 if(!memtarget||!rs1[i]) {
57871462 3456 jaddr=(int)out;
3457 emit_jmp(0);
3458 }
57871462 3459 }
535d208a 3460 #ifdef RAM_OFFSET
3461 int map=get_reg(i_regs->regmap,ROREG);
3462 if(map<0) emit_loadreg(ROREG,map=HOST_TEMPREG);
3463 gen_tlb_addr_w(temp,map);
3464 #else
3465 if((u_int)rdram!=0x80000000)
3466 emit_addimm_no_flags((u_int)rdram-(u_int)0x80000000,temp);
3467 #endif
3468 }else{ // using tlb
3469 int map=get_reg(i_regs->regmap,TLREG);
3470 assert(map>=0);
ea3d2e6e 3471 reglist&=~(1<<map);
535d208a 3472 map=do_tlb_w(c||s<0||offset?temp:s,temp,map,0,c,constmap[i][s]+offset);
3473 if(!c&&!offset&&s>=0) emit_mov(s,temp);
3474 do_tlb_w_branch(map,c,constmap[i][s]+offset,&jaddr);
3475 if(!jaddr&&!memtarget) {
3476 jaddr=(int)out;
3477 emit_jmp(0);
57871462 3478 }
535d208a 3479 gen_tlb_addr_w(temp,map);
3480 }
3481
3482 if (opcode[i]==0x2C||opcode[i]==0x2D) { // SDL/SDR
3483 temp2=get_reg(i_regs->regmap,FTEMP);
3484 if(!rs2[i]) temp2=th=tl;
3485 }
57871462 3486
2002a1db 3487#ifndef BIG_ENDIAN_MIPS
3488 emit_xorimm(temp,3,temp);
3489#endif
535d208a 3490 emit_testimm(temp,2);
3491 case2=(int)out;
3492 emit_jne(0);
3493 emit_testimm(temp,1);
3494 case1=(int)out;
3495 emit_jne(0);
3496 // 0
3497 if (opcode[i]==0x2A) { // SWL
3498 emit_writeword_indexed(tl,0,temp);
3499 }
3500 if (opcode[i]==0x2E) { // SWR
3501 emit_writebyte_indexed(tl,3,temp);
3502 }
3503 if (opcode[i]==0x2C) { // SDL
3504 emit_writeword_indexed(th,0,temp);
3505 if(rs2[i]) emit_mov(tl,temp2);
3506 }
3507 if (opcode[i]==0x2D) { // SDR
3508 emit_writebyte_indexed(tl,3,temp);
3509 if(rs2[i]) emit_shldimm(th,tl,24,temp2);
3510 }
3511 done0=(int)out;
3512 emit_jmp(0);
3513 // 1
3514 set_jump_target(case1,(int)out);
3515 if (opcode[i]==0x2A) { // SWL
3516 // Write 3 msb into three least significant bytes
3517 if(rs2[i]) emit_rorimm(tl,8,tl);
3518 emit_writehword_indexed(tl,-1,temp);
3519 if(rs2[i]) emit_rorimm(tl,16,tl);
3520 emit_writebyte_indexed(tl,1,temp);
3521 if(rs2[i]) emit_rorimm(tl,8,tl);
3522 }
3523 if (opcode[i]==0x2E) { // SWR
3524 // Write two lsb into two most significant bytes
3525 emit_writehword_indexed(tl,1,temp);
3526 }
3527 if (opcode[i]==0x2C) { // SDL
3528 if(rs2[i]) emit_shrdimm(tl,th,8,temp2);
3529 // Write 3 msb into three least significant bytes
3530 if(rs2[i]) emit_rorimm(th,8,th);
3531 emit_writehword_indexed(th,-1,temp);
3532 if(rs2[i]) emit_rorimm(th,16,th);
3533 emit_writebyte_indexed(th,1,temp);
3534 if(rs2[i]) emit_rorimm(th,8,th);
3535 }
3536 if (opcode[i]==0x2D) { // SDR
3537 if(rs2[i]) emit_shldimm(th,tl,16,temp2);
3538 // Write two lsb into two most significant bytes
3539 emit_writehword_indexed(tl,1,temp);
3540 }
3541 done1=(int)out;
3542 emit_jmp(0);
3543 // 2
3544 set_jump_target(case2,(int)out);
3545 emit_testimm(temp,1);
3546 case3=(int)out;
3547 emit_jne(0);
3548 if (opcode[i]==0x2A) { // SWL
3549 // Write two msb into two least significant bytes
3550 if(rs2[i]) emit_rorimm(tl,16,tl);
3551 emit_writehword_indexed(tl,-2,temp);
3552 if(rs2[i]) emit_rorimm(tl,16,tl);
3553 }
3554 if (opcode[i]==0x2E) { // SWR
3555 // Write 3 lsb into three most significant bytes
3556 emit_writebyte_indexed(tl,-1,temp);
3557 if(rs2[i]) emit_rorimm(tl,8,tl);
3558 emit_writehword_indexed(tl,0,temp);
3559 if(rs2[i]) emit_rorimm(tl,24,tl);
3560 }
3561 if (opcode[i]==0x2C) { // SDL
3562 if(rs2[i]) emit_shrdimm(tl,th,16,temp2);
3563 // Write two msb into two least significant bytes
3564 if(rs2[i]) emit_rorimm(th,16,th);
3565 emit_writehword_indexed(th,-2,temp);
3566 if(rs2[i]) emit_rorimm(th,16,th);
3567 }
3568 if (opcode[i]==0x2D) { // SDR
3569 if(rs2[i]) emit_shldimm(th,tl,8,temp2);
3570 // Write 3 lsb into three most significant bytes
3571 emit_writebyte_indexed(tl,-1,temp);
3572 if(rs2[i]) emit_rorimm(tl,8,tl);
3573 emit_writehword_indexed(tl,0,temp);
3574 if(rs2[i]) emit_rorimm(tl,24,tl);
3575 }
3576 done2=(int)out;
3577 emit_jmp(0);
3578 // 3
3579 set_jump_target(case3,(int)out);
3580 if (opcode[i]==0x2A) { // SWL
3581 // Write msb into least significant byte
3582 if(rs2[i]) emit_rorimm(tl,24,tl);
3583 emit_writebyte_indexed(tl,-3,temp);
3584 if(rs2[i]) emit_rorimm(tl,8,tl);
3585 }
3586 if (opcode[i]==0x2E) { // SWR
3587 // Write entire word
3588 emit_writeword_indexed(tl,-3,temp);
3589 }
3590 if (opcode[i]==0x2C) { // SDL
3591 if(rs2[i]) emit_shrdimm(tl,th,24,temp2);
3592 // Write msb into least significant byte
3593 if(rs2[i]) emit_rorimm(th,24,th);
3594 emit_writebyte_indexed(th,-3,temp);
3595 if(rs2[i]) emit_rorimm(th,8,th);
3596 }
3597 if (opcode[i]==0x2D) { // SDR
3598 if(rs2[i]) emit_mov(th,temp2);
3599 // Write entire word
3600 emit_writeword_indexed(tl,-3,temp);
3601 }
3602 set_jump_target(done0,(int)out);
3603 set_jump_target(done1,(int)out);
3604 set_jump_target(done2,(int)out);
3605 if (opcode[i]==0x2C) { // SDL
3606 emit_testimm(temp,4);
57871462 3607 done0=(int)out;
57871462 3608 emit_jne(0);
535d208a 3609 emit_andimm(temp,~3,temp);
3610 emit_writeword_indexed(temp2,4,temp);
3611 set_jump_target(done0,(int)out);
3612 }
3613 if (opcode[i]==0x2D) { // SDR
3614 emit_testimm(temp,4);
3615 done0=(int)out;
3616 emit_jeq(0);
3617 emit_andimm(temp,~3,temp);
3618 emit_writeword_indexed(temp2,-4,temp);
57871462 3619 set_jump_target(done0,(int)out);
57871462 3620 }
535d208a 3621 if(!c||!memtarget)
3622 add_stub(STORELR_STUB,jaddr,(int)out,i,(int)i_regs,temp,ccadj[i],reglist);
0ff8c62c 3623 if(!using_tlb&&!(i_regs->waswritten&(1<<rs1[i]))&&!(new_dynarec_hacks&NDHACK_NO_SMC_CHECK)) {
535d208a 3624 #ifdef RAM_OFFSET
3625 int map=get_reg(i_regs->regmap,ROREG);
3626 if(map<0) map=HOST_TEMPREG;
3627 gen_orig_addr_w(temp,map);
3628 #else
57871462 3629 emit_addimm_no_flags((u_int)0x80000000-(u_int)rdram,temp);
535d208a 3630 #endif
57871462 3631 #if defined(HOST_IMM8)
3632 int ir=get_reg(i_regs->regmap,INVCP);
3633 assert(ir>=0);
3634 emit_cmpmem_indexedsr12_reg(ir,temp,1);
3635 #else
3636 emit_cmpmem_indexedsr12_imm((int)invalid_code,temp,1);
3637 #endif
535d208a 3638 #if defined(HAVE_CONDITIONAL_CALL) && !defined(DESTRUCTIVE_SHIFT)
3639 emit_callne(invalidate_addr_reg[temp]);
3640 #else
57871462 3641 jaddr2=(int)out;
3642 emit_jne(0);
3643 add_stub(INVCODE_STUB,jaddr2,(int)out,reglist|(1<<HOST_CCREG),temp,0,0,0);
535d208a 3644 #endif
57871462 3645 }
3646 /*
3647 emit_pusha();
3648 //save_regs(0x100f);
3649 emit_readword((int)&last_count,ECX);
3650 if(get_reg(i_regs->regmap,CCREG)<0)
3651 emit_loadreg(CCREG,HOST_CCREG);
3652 emit_add(HOST_CCREG,ECX,HOST_CCREG);
3653 emit_addimm(HOST_CCREG,2*ccadj[i],HOST_CCREG);
3654 emit_writeword(HOST_CCREG,(int)&Count);
3655 emit_call((int)memdebug);
3656 emit_popa();
3657 //restore_regs(0x100f);
3658 /**/
3659}
3660
3661void c1ls_assemble(int i,struct regstat *i_regs)
3662{
3d624f89 3663#ifndef DISABLE_COP1
57871462 3664 int s,th,tl;
3665 int temp,ar;
3666 int map=-1;
3667 int offset;
3668 int c=0;
3669 int jaddr,jaddr2=0,jaddr3,type;
3670 int agr=AGEN1+(i&1);
3671 u_int hr,reglist=0;
3672 th=get_reg(i_regs->regmap,FTEMP|64);
3673 tl=get_reg(i_regs->regmap,FTEMP);
3674 s=get_reg(i_regs->regmap,rs1[i]);
3675 temp=get_reg(i_regs->regmap,agr);
3676 if(temp<0) temp=get_reg(i_regs->regmap,-1);
3677 offset=imm[i];
3678 assert(tl>=0);
3679 assert(rs1[i]>0);
3680 assert(temp>=0);
3681 for(hr=0;hr<HOST_REGS;hr++) {
3682 if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
3683 }
3684 if(i_regs->regmap[HOST_CCREG]==CCREG) reglist&=~(1<<HOST_CCREG);
3685 if (opcode[i]==0x31||opcode[i]==0x35) // LWC1/LDC1
3686 {
3687 // Loads use a temporary register which we need to save
3688 reglist|=1<<temp;
3689 }
3690 if (opcode[i]==0x39||opcode[i]==0x3D) // SWC1/SDC1
3691 ar=temp;
3692 else // LWC1/LDC1
3693 ar=tl;
3694 //if(s<0) emit_loadreg(rs1[i],ar); //address_generation does this now
3695 //else c=(i_regs->wasconst>>s)&1;
3696 if(s>=0) c=(i_regs->wasconst>>s)&1;
3697 // Check cop1 unusable
3698 if(!cop1_usable) {
3699 signed char rs=get_reg(i_regs->regmap,CSREG);
3700 assert(rs>=0);
3701 emit_testimm(rs,0x20000000);
3702 jaddr=(int)out;
3703 emit_jeq(0);
3704 add_stub(FP_STUB,jaddr,(int)out,i,rs,(int)i_regs,is_delayslot,0);
3705 cop1_usable=1;
3706 }
3707 if (opcode[i]==0x39) { // SWC1 (get float address)
3708 emit_readword((int)&reg_cop1_simple[(source[i]>>16)&0x1f],tl);
3709 }
3710 if (opcode[i]==0x3D) { // SDC1 (get double address)
3711 emit_readword((int)&reg_cop1_double[(source[i]>>16)&0x1f],tl);
3712 }
3713 // Generate address + offset
3714 if(!using_tlb) {
3715 if(!c)
4cb76aa4 3716 emit_cmpimm(offset||c||s<0?ar:s,RAM_SIZE);
57871462 3717 }
3718 else
3719 {
3720 map=get_reg(i_regs->regmap,TLREG);
3721 assert(map>=0);
ea3d2e6e 3722 reglist&=~(1<<map);
57871462 3723 if (opcode[i]==0x31||opcode[i]==0x35) { // LWC1/LDC1
3724 map=do_tlb_r(offset||c||s<0?ar:s,ar,map,0,-1,-1,c,constmap[i][s]+offset);
3725 }
3726 if (opcode[i]==0x39||opcode[i]==0x3D) { // SWC1/SDC1
3727 map=do_tlb_w(offset||c||s<0?ar:s,ar,map,0,c,constmap[i][s]+offset);
3728 }
3729 }
3730 if (opcode[i]==0x39) { // SWC1 (read float)
3731 emit_readword_indexed(0,tl,tl);
3732 }
3733 if (opcode[i]==0x3D) { // SDC1 (read double)
3734 emit_readword_indexed(4,tl,th);
3735 emit_readword_indexed(0,tl,tl);
3736 }
3737 if (opcode[i]==0x31) { // LWC1 (get target address)
3738 emit_readword((int)&reg_cop1_simple[(source[i]>>16)&0x1f],temp);
3739 }
3740 if (opcode[i]==0x35) { // LDC1 (get target address)
3741 emit_readword((int)&reg_cop1_double[(source[i]>>16)&0x1f],temp);
3742 }
3743 if(!using_tlb) {
3744 if(!c) {
3745 jaddr2=(int)out;
3746 emit_jno(0);
3747 }
4cb76aa4 3748 else if(((signed int)(constmap[i][s]+offset))>=(signed int)0x80000000+RAM_SIZE) {
57871462 3749 jaddr2=(int)out;
3750 emit_jmp(0); // inline_readstub/inline_writestub? Very rare case
3751 }
3752 #ifdef DESTRUCTIVE_SHIFT
3753 if (opcode[i]==0x39||opcode[i]==0x3D) { // SWC1/SDC1
3754 if(!offset&&!c&&s>=0) emit_mov(s,ar);
3755 }
3756 #endif
3757 }else{
3758 if (opcode[i]==0x31||opcode[i]==0x35) { // LWC1/LDC1
3759 do_tlb_r_branch(map,c,constmap[i][s]+offset,&jaddr2);
3760 }
3761 if (opcode[i]==0x39||opcode[i]==0x3D) { // SWC1/SDC1
3762 do_tlb_w_branch(map,c,constmap[i][s]+offset,&jaddr2);
3763 }
3764 }
3765 if (opcode[i]==0x31) { // LWC1
3766 //if(s>=0&&!c&&!offset) emit_mov(s,tl);
3767 //gen_tlb_addr_r(ar,map);
3768 //emit_readword_indexed((int)rdram-0x80000000,tl,tl);
3769 #ifdef HOST_IMM_ADDR32
3770 if(c) emit_readword_tlb(constmap[i][s]+offset,map,tl);
3771 else
3772 #endif
3773 emit_readword_indexed_tlb(0,offset||c||s<0?tl:s,map,tl);
3774 type=LOADW_STUB;
3775 }
3776 if (opcode[i]==0x35) { // LDC1
3777 assert(th>=0);
3778 //if(s>=0&&!c&&!offset) emit_mov(s,tl);
3779 //gen_tlb_addr_r(ar,map);
3780 //emit_readword_indexed((int)rdram-0x80000000,tl,th);
3781 //emit_readword_indexed((int)rdram-0x7FFFFFFC,tl,tl);
3782 #ifdef HOST_IMM_ADDR32
3783 if(c) emit_readdword_tlb(constmap[i][s]+offset,map,th,tl);
3784 else
3785 #endif
3786 emit_readdword_indexed_tlb(0,offset||c||s<0?tl:s,map,th,tl);
3787 type=LOADD_STUB;
3788 }
3789 if (opcode[i]==0x39) { // SWC1
3790 //emit_writeword_indexed(tl,(int)rdram-0x80000000,temp);
3791 emit_writeword_indexed_tlb(tl,0,offset||c||s<0?temp:s,map,temp);
3792 type=STOREW_STUB;
3793 }
3794 if (opcode[i]==0x3D) { // SDC1
3795 assert(th>=0);
3796 //emit_writeword_indexed(th,(int)rdram-0x80000000,temp);
3797 //emit_writeword_indexed(tl,(int)rdram-0x7FFFFFFC,temp);
3798 emit_writedword_indexed_tlb(th,tl,0,offset||c||s<0?temp:s,map,temp);
3799 type=STORED_STUB;
3800 }
0ff8c62c 3801 if(!using_tlb&&!(i_regs->waswritten&(1<<rs1[i]))&&!(new_dynarec_hacks&NDHACK_NO_SMC_CHECK)) {
57871462 3802 if (opcode[i]==0x39||opcode[i]==0x3D) { // SWC1/SDC1
3803 #ifndef DESTRUCTIVE_SHIFT
3804 temp=offset||c||s<0?ar:s;
3805 #endif
3806 #if defined(HOST_IMM8)
3807 int ir=get_reg(i_regs->regmap,INVCP);
3808 assert(ir>=0);
3809 emit_cmpmem_indexedsr12_reg(ir,temp,1);
3810 #else
3811 emit_cmpmem_indexedsr12_imm((int)invalid_code,temp,1);
3812 #endif
0bbd1454 3813 #if defined(HAVE_CONDITIONAL_CALL) && !defined(DESTRUCTIVE_SHIFT)
3814 emit_callne(invalidate_addr_reg[temp]);
3815 #else
57871462 3816 jaddr3=(int)out;
3817 emit_jne(0);
3818 add_stub(INVCODE_STUB,jaddr3,(int)out,reglist|(1<<HOST_CCREG),temp,0,0,0);
0bbd1454 3819 #endif
57871462 3820 }
3821 }
3822 if(jaddr2) add_stub(type,jaddr2,(int)out,i,offset||c||s<0?ar:s,(int)i_regs,ccadj[i],reglist);
3823 if (opcode[i]==0x31) { // LWC1 (write float)
3824 emit_writeword_indexed(tl,0,temp);
3825 }
3826 if (opcode[i]==0x35) { // LDC1 (write double)
3827 emit_writeword_indexed(th,4,temp);
3828 emit_writeword_indexed(tl,0,temp);
3829 }
3830 //if(opcode[i]==0x39)
3831 /*if(opcode[i]==0x39||opcode[i]==0x31)
3832 {
3833 emit_pusha();
3834 emit_readword((int)&last_count,ECX);
3835 if(get_reg(i_regs->regmap,CCREG)<0)
3836 emit_loadreg(CCREG,HOST_CCREG);
3837 emit_add(HOST_CCREG,ECX,HOST_CCREG);
3838 emit_addimm(HOST_CCREG,2*ccadj[i],HOST_CCREG);
3839 emit_writeword(HOST_CCREG,(int)&Count);
3840 emit_call((int)memdebug);
3841 emit_popa();
3842 }/**/
3d624f89 3843#else
3844 cop1_unusable(i, i_regs);
3845#endif
57871462 3846}
3847
b9b61529 3848void c2ls_assemble(int i,struct regstat *i_regs)
3849{
3850 int s,tl;
3851 int ar;
3852 int offset;
1fd1aceb 3853 int memtarget=0,c=0;
c2e3bd42 3854 int jaddr2=0,jaddr3,type;
b9b61529 3855 int agr=AGEN1+(i&1);
ffb0b9e0 3856 int fastio_reg_override=0;
b9b61529 3857 u_int hr,reglist=0;
3858 u_int copr=(source[i]>>16)&0x1f;
3859 s=get_reg(i_regs->regmap,rs1[i]);
3860 tl=get_reg(i_regs->regmap,FTEMP);
3861 offset=imm[i];
3862 assert(rs1[i]>0);
3863 assert(tl>=0);
3864 assert(!using_tlb);
3865
3866 for(hr=0;hr<HOST_REGS;hr++) {
3867 if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
3868 }
3869 if(i_regs->regmap[HOST_CCREG]==CCREG)
3870 reglist&=~(1<<HOST_CCREG);
3871
3872 // get the address
3873 if (opcode[i]==0x3a) { // SWC2
3874 ar=get_reg(i_regs->regmap,agr);
3875 if(ar<0) ar=get_reg(i_regs->regmap,-1);
3876 reglist|=1<<ar;
3877 } else { // LWC2
3878 ar=tl;
3879 }
1fd1aceb 3880 if(s>=0) c=(i_regs->wasconst>>s)&1;
3881 memtarget=c&&(((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE);
b9b61529 3882 if (!offset&&!c&&s>=0) ar=s;
3883 assert(ar>=0);
3884
3885 if (opcode[i]==0x3a) { // SWC2
3886 cop2_get_dreg(copr,tl,HOST_TEMPREG);
1fd1aceb 3887 type=STOREW_STUB;
b9b61529 3888 }
1fd1aceb 3889 else
b9b61529 3890 type=LOADW_STUB;
1fd1aceb 3891
3892 if(c&&!memtarget) {
3893 jaddr2=(int)out;
3894 emit_jmp(0); // inline_readstub/inline_writestub?
b9b61529 3895 }
1fd1aceb 3896 else {
3897 if(!c) {
ffb0b9e0 3898 jaddr2=emit_fastpath_cmp_jump(i,ar,&fastio_reg_override);
1fd1aceb 3899 }
a327ad27 3900 else if(ram_offset&&memtarget) {
3901 emit_addimm(ar,ram_offset,HOST_TEMPREG);
3902 fastio_reg_override=HOST_TEMPREG;
3903 }
1fd1aceb 3904 if (opcode[i]==0x32) { // LWC2
3905 #ifdef HOST_IMM_ADDR32
3906 if(c) emit_readword_tlb(constmap[i][s]+offset,-1,tl);
3907 else
3908 #endif
ffb0b9e0 3909 int a=ar;
3910 if(fastio_reg_override) a=fastio_reg_override;
3911 emit_readword_indexed(0,a,tl);
1fd1aceb 3912 }
3913 if (opcode[i]==0x3a) { // SWC2
3914 #ifdef DESTRUCTIVE_SHIFT
3915 if(!offset&&!c&&s>=0) emit_mov(s,ar);
3916 #endif
ffb0b9e0 3917 int a=ar;
3918 if(fastio_reg_override) a=fastio_reg_override;
3919 emit_writeword_indexed(tl,0,a);
1fd1aceb 3920 }
b9b61529 3921 }
3922 if(jaddr2)
3923 add_stub(type,jaddr2,(int)out,i,ar,(int)i_regs,ccadj[i],reglist);
0ff8c62c 3924 if(opcode[i]==0x3a) // SWC2
3925 if(!(i_regs->waswritten&(1<<rs1[i]))&&!(new_dynarec_hacks&NDHACK_NO_SMC_CHECK)) {
b9b61529 3926#if defined(HOST_IMM8)
3927 int ir=get_reg(i_regs->regmap,INVCP);
3928 assert(ir>=0);
3929 emit_cmpmem_indexedsr12_reg(ir,ar,1);
3930#else
3931 emit_cmpmem_indexedsr12_imm((int)invalid_code,ar,1);
3932#endif
0bbd1454 3933 #if defined(HAVE_CONDITIONAL_CALL) && !defined(DESTRUCTIVE_SHIFT)
3934 emit_callne(invalidate_addr_reg[ar]);
3935 #else
b9b61529 3936 jaddr3=(int)out;
3937 emit_jne(0);
3938 add_stub(INVCODE_STUB,jaddr3,(int)out,reglist|(1<<HOST_CCREG),ar,0,0,0);
0bbd1454 3939 #endif
b9b61529 3940 }
3941 if (opcode[i]==0x32) { // LWC2
3942 cop2_put_dreg(copr,tl,HOST_TEMPREG);
3943 }
3944}
3945
57871462 3946#ifndef multdiv_assemble
3947void multdiv_assemble(int i,struct regstat *i_regs)
3948{
3949 printf("Need multdiv_assemble for this architecture.\n");
3950 exit(1);
3951}
3952#endif
3953
3954void mov_assemble(int i,struct regstat *i_regs)
3955{
3956 //if(opcode2[i]==0x10||opcode2[i]==0x12) { // MFHI/MFLO
3957 //if(opcode2[i]==0x11||opcode2[i]==0x13) { // MTHI/MTLO
57871462 3958 if(rt1[i]) {
3959 signed char sh,sl,th,tl;
3960 th=get_reg(i_regs->regmap,rt1[i]|64);
3961 tl=get_reg(i_regs->regmap,rt1[i]);
3962 //assert(tl>=0);
3963 if(tl>=0) {
3964 sh=get_reg(i_regs->regmap,rs1[i]|64);
3965 sl=get_reg(i_regs->regmap,rs1[i]);
3966 if(sl>=0) emit_mov(sl,tl);
3967 else emit_loadreg(rs1[i],tl);
3968 if(th>=0) {
3969 if(sh>=0) emit_mov(sh,th);
3970 else emit_loadreg(rs1[i]|64,th);
3971 }
3972 }
3973 }
3974}
3975
3976#ifndef fconv_assemble
3977void fconv_assemble(int i,struct regstat *i_regs)
3978{
3979 printf("Need fconv_assemble for this architecture.\n");
3980 exit(1);
3981}
3982#endif
3983
3984#if 0
3985void float_assemble(int i,struct regstat *i_regs)
3986{
3987 printf("Need float_assemble for this architecture.\n");
3988 exit(1);
3989}
3990#endif
3991
3992void syscall_assemble(int i,struct regstat *i_regs)
3993{
3994 signed char ccreg=get_reg(i_regs->regmap,CCREG);
3995 assert(ccreg==HOST_CCREG);
3996 assert(!is_delayslot);
3997 emit_movimm(start+i*4,EAX); // Get PC
2573466a 3998 emit_addimm(HOST_CCREG,CLOCK_ADJUST(ccadj[i]),HOST_CCREG); // CHECK: is this right? There should probably be an extra cycle...
7139f3c8 3999 emit_jmp((int)jump_syscall_hle); // XXX
4000}
4001
4002void hlecall_assemble(int i,struct regstat *i_regs)
4003{
4004 signed char ccreg=get_reg(i_regs->regmap,CCREG);
4005 assert(ccreg==HOST_CCREG);
4006 assert(!is_delayslot);
4007 emit_movimm(start+i*4+4,0); // Get PC
67ba0fb4 4008 emit_movimm((int)psxHLEt[source[i]&7],1);
2573466a 4009 emit_addimm(HOST_CCREG,CLOCK_ADJUST(ccadj[i]),HOST_CCREG); // XXX
67ba0fb4 4010 emit_jmp((int)jump_hlecall);
57871462 4011}
4012
1e973cb0 4013void intcall_assemble(int i,struct regstat *i_regs)
4014{
4015 signed char ccreg=get_reg(i_regs->regmap,CCREG);
4016 assert(ccreg==HOST_CCREG);
4017 assert(!is_delayslot);
4018 emit_movimm(start+i*4,0); // Get PC
2573466a 4019 emit_addimm(HOST_CCREG,CLOCK_ADJUST(ccadj[i]),HOST_CCREG);
1e973cb0 4020 emit_jmp((int)jump_intcall);
4021}
4022
57871462 4023void ds_assemble(int i,struct regstat *i_regs)
4024{
ffb0b9e0 4025 speculate_register_values(i);
57871462 4026 is_delayslot=1;
4027 switch(itype[i]) {
4028 case ALU:
4029 alu_assemble(i,i_regs);break;
4030 case IMM16:
4031 imm16_assemble(i,i_regs);break;
4032 case SHIFT:
4033 shift_assemble(i,i_regs);break;
4034 case SHIFTIMM:
4035 shiftimm_assemble(i,i_regs);break;
4036 case LOAD:
4037 load_assemble(i,i_regs);break;
4038 case LOADLR:
4039 loadlr_assemble(i,i_regs);break;
4040 case STORE:
4041 store_assemble(i,i_regs);break;
4042 case STORELR:
4043 storelr_assemble(i,i_regs);break;
4044 case COP0:
4045 cop0_assemble(i,i_regs);break;
4046 case COP1:
4047 cop1_assemble(i,i_regs);break;
4048 case C1LS:
4049 c1ls_assemble(i,i_regs);break;
b9b61529 4050 case COP2:
4051 cop2_assemble(i,i_regs);break;
4052 case C2LS:
4053 c2ls_assemble(i,i_regs);break;
4054 case C2OP:
4055 c2op_assemble(i,i_regs);break;
57871462 4056 case FCONV:
4057 fconv_assemble(i,i_regs);break;
4058 case FLOAT:
4059 float_assemble(i,i_regs);break;
4060 case FCOMP:
4061 fcomp_assemble(i,i_regs);break;
4062 case MULTDIV:
4063 multdiv_assemble(i,i_regs);break;
4064 case MOV:
4065 mov_assemble(i,i_regs);break;
4066 case SYSCALL:
7139f3c8 4067 case HLECALL:
1e973cb0 4068 case INTCALL:
57871462 4069 case SPAN:
4070 case UJUMP:
4071 case RJUMP:
4072 case CJUMP:
4073 case SJUMP:
4074 case FJUMP:
4075 printf("Jump in the delay slot. This is probably a bug.\n");
4076 }
4077 is_delayslot=0;
4078}
4079
4080// Is the branch target a valid internal jump?
4081int internal_branch(uint64_t i_is32,int addr)
4082{
4083 if(addr&1) return 0; // Indirect (register) jump
4084 if(addr>=start && addr<start+slen*4-4)
4085 {
4086 int t=(addr-start)>>2;
4087 // Delay slots are not valid branch targets
4088 //if(t>0&&(itype[t-1]==RJUMP||itype[t-1]==UJUMP||itype[t-1]==CJUMP||itype[t-1]==SJUMP||itype[t-1]==FJUMP)) return 0;
4089 // 64 -> 32 bit transition requires a recompile
4090 /*if(is32[t]&~unneeded_reg_upper[t]&~i_is32)
4091 {
4092 if(requires_32bit[t]&~i_is32) printf("optimizable: no\n");
4093 else printf("optimizable: yes\n");
4094 }*/
4095 //if(is32[t]&~unneeded_reg_upper[t]&~i_is32) return 0;
a28c6ce8 4096#ifndef FORCE32
57871462 4097 if(requires_32bit[t]&~i_is32) return 0;
a28c6ce8 4098 else
4099#endif
4100 return 1;
57871462 4101 }
4102 return 0;
4103}
4104
4105#ifndef wb_invalidate
4106void wb_invalidate(signed char pre[],signed char entry[],uint64_t dirty,uint64_t is32,
4107 uint64_t u,uint64_t uu)
4108{
4109 int hr;
4110 for(hr=0;hr<HOST_REGS;hr++) {
4111 if(hr!=EXCLUDE_REG) {
4112 if(pre[hr]!=entry[hr]) {
4113 if(pre[hr]>=0) {
4114 if((dirty>>hr)&1) {
4115 if(get_reg(entry,pre[hr])<0) {
4116 if(pre[hr]<64) {
4117 if(!((u>>pre[hr])&1)) {
4118 emit_storereg(pre[hr],hr);
4119 if( ((is32>>pre[hr])&1) && !((uu>>pre[hr])&1) ) {
4120 emit_sarimm(hr,31,hr);
4121 emit_storereg(pre[hr]|64,hr);
4122 }
4123 }
4124 }else{
4125 if(!((uu>>(pre[hr]&63))&1) && !((is32>>(pre[hr]&63))&1)) {
4126 emit_storereg(pre[hr],hr);
4127 }
4128 }
4129 }
4130 }
4131 }
4132 }
4133 }
4134 }
4135 // Move from one register to another (no writeback)
4136 for(hr=0;hr<HOST_REGS;hr++) {
4137 if(hr!=EXCLUDE_REG) {
4138 if(pre[hr]!=entry[hr]) {
4139 if(pre[hr]>=0&&(pre[hr]&63)<TEMPREG) {
4140 int nr;
4141 if((nr=get_reg(entry,pre[hr]))>=0) {
4142 emit_mov(hr,nr);
4143 }
4144 }
4145 }
4146 }
4147 }
4148}
4149#endif
4150
4151// Load the specified registers
4152// This only loads the registers given as arguments because
4153// we don't want to load things that will be overwritten
4154void load_regs(signed char entry[],signed char regmap[],int is32,int rs1,int rs2)
4155{
4156 int hr;
4157 // Load 32-bit regs
4158 for(hr=0;hr<HOST_REGS;hr++) {
4159 if(hr!=EXCLUDE_REG&&regmap[hr]>=0) {
4160 if(entry[hr]!=regmap[hr]) {
4161 if(regmap[hr]==rs1||regmap[hr]==rs2)
4162 {
4163 if(regmap[hr]==0) {
4164 emit_zeroreg(hr);
4165 }
4166 else
4167 {
4168 emit_loadreg(regmap[hr],hr);
4169 }
4170 }
4171 }
4172 }
4173 }
4174 //Load 64-bit regs
4175 for(hr=0;hr<HOST_REGS;hr++) {
4176 if(hr!=EXCLUDE_REG&&regmap[hr]>=0) {
4177 if(entry[hr]!=regmap[hr]) {
4178 if(regmap[hr]-64==rs1||regmap[hr]-64==rs2)
4179 {
4180 assert(regmap[hr]!=64);
4181 if((is32>>(regmap[hr]&63))&1) {
4182 int lr=get_reg(regmap,regmap[hr]-64);
4183 if(lr>=0)
4184 emit_sarimm(lr,31,hr);
4185 else
4186 emit_loadreg(regmap[hr],hr);
4187 }
4188 else
4189 {
4190 emit_loadreg(regmap[hr],hr);
4191 }
4192 }
4193 }
4194 }
4195 }
4196}
4197
4198// Load registers prior to the start of a loop
4199// so that they are not loaded within the loop
4200static void loop_preload(signed char pre[],signed char entry[])
4201{
4202 int hr;
4203 for(hr=0;hr<HOST_REGS;hr++) {
4204 if(hr!=EXCLUDE_REG) {
4205 if(pre[hr]!=entry[hr]) {
4206 if(entry[hr]>=0) {
4207 if(get_reg(pre,entry[hr])<0) {
4208 assem_debug("loop preload:\n");
4209 //printf("loop preload: %d\n",hr);
4210 if(entry[hr]==0) {
4211 emit_zeroreg(hr);
4212 }
4213 else if(entry[hr]<TEMPREG)
4214 {
4215 emit_loadreg(entry[hr],hr);
4216 }
4217 else if(entry[hr]-64<TEMPREG)
4218 {
4219 emit_loadreg(entry[hr],hr);
4220 }
4221 }
4222 }
4223 }
4224 }
4225 }
4226}
4227
4228// Generate address for load/store instruction
b9b61529 4229// goes to AGEN for writes, FTEMP for LOADLR and cop1/2 loads
57871462 4230void address_generation(int i,struct regstat *i_regs,signed char entry[])
4231{
b9b61529 4232 if(itype[i]==LOAD||itype[i]==LOADLR||itype[i]==STORE||itype[i]==STORELR||itype[i]==C1LS||itype[i]==C2LS) {
5194fb95 4233 int ra=-1;
57871462 4234 int agr=AGEN1+(i&1);
4235 int mgr=MGEN1+(i&1);
4236 if(itype[i]==LOAD) {
4237 ra=get_reg(i_regs->regmap,rt1[i]);
535d208a 4238 if(ra<0) ra=get_reg(i_regs->regmap,-1);
4239 assert(ra>=0);
57871462 4240 }
4241 if(itype[i]==LOADLR) {
4242 ra=get_reg(i_regs->regmap,FTEMP);
4243 }
4244 if(itype[i]==STORE||itype[i]==STORELR) {
4245 ra=get_reg(i_regs->regmap,agr);
4246 if(ra<0) ra=get_reg(i_regs->regmap,-1);
4247 }
b9b61529 4248 if(itype[i]==C1LS||itype[i]==C2LS) {
4249 if ((opcode[i]&0x3b)==0x31||(opcode[i]&0x3b)==0x32) // LWC1/LDC1/LWC2/LDC2
57871462 4250 ra=get_reg(i_regs->regmap,FTEMP);
1fd1aceb 4251 else { // SWC1/SDC1/SWC2/SDC2
57871462 4252 ra=get_reg(i_regs->regmap,agr);
4253 if(ra<0) ra=get_reg(i_regs->regmap,-1);
4254 }
4255 }
4256 int rs=get_reg(i_regs->regmap,rs1[i]);
4257 int rm=get_reg(i_regs->regmap,TLREG);
4258 if(ra>=0) {
4259 int offset=imm[i];
4260 int c=(i_regs->wasconst>>rs)&1;
4261 if(rs1[i]==0) {
4262 // Using r0 as a base address
4263 /*if(rm>=0) {
4264 if(!entry||entry[rm]!=mgr) {
4265 generate_map_const(offset,rm);
4266 } // else did it in the previous cycle
4267 }*/
4268 if(!entry||entry[ra]!=agr) {
4269 if (opcode[i]==0x22||opcode[i]==0x26) {
4270 emit_movimm(offset&0xFFFFFFFC,ra); // LWL/LWR
4271 }else if (opcode[i]==0x1a||opcode[i]==0x1b) {
4272 emit_movimm(offset&0xFFFFFFF8,ra); // LDL/LDR
4273 }else{
4274 emit_movimm(offset,ra);
4275 }
4276 } // else did it in the previous cycle
4277 }
4278 else if(rs<0) {
4279 if(!entry||entry[ra]!=rs1[i])
4280 emit_loadreg(rs1[i],ra);
4281 //if(!entry||entry[ra]!=rs1[i])
4282 // printf("poor load scheduling!\n");
4283 }
4284 else if(c) {
63cb0298 4285#ifndef DISABLE_TLB
57871462 4286 if(rm>=0) {
4287 if(!entry||entry[rm]!=mgr) {
b9b61529 4288 if(itype[i]==STORE||itype[i]==STORELR||(opcode[i]&0x3b)==0x39||(opcode[i]&0x3b)==0x3a) {
57871462 4289 // Stores to memory go thru the mapper to detect self-modifying
4290 // code, loads don't.
4291 if((unsigned int)(constmap[i][rs]+offset)>=0xC0000000 ||
4cb76aa4 4292 (unsigned int)(constmap[i][rs]+offset)<0x80000000+RAM_SIZE )
57871462 4293 generate_map_const(constmap[i][rs]+offset,rm);
4294 }else{
4295 if((signed int)(constmap[i][rs]+offset)>=(signed int)0xC0000000)
4296 generate_map_const(constmap[i][rs]+offset,rm);
4297 }
4298 }
4299 }
63cb0298 4300#endif
57871462 4301 if(rs1[i]!=rt1[i]||itype[i]!=LOAD) {
4302 if(!entry||entry[ra]!=agr) {
4303 if (opcode[i]==0x22||opcode[i]==0x26) {
4304 emit_movimm((constmap[i][rs]+offset)&0xFFFFFFFC,ra); // LWL/LWR
4305 }else if (opcode[i]==0x1a||opcode[i]==0x1b) {
4306 emit_movimm((constmap[i][rs]+offset)&0xFFFFFFF8,ra); // LDL/LDR
4307 }else{
4308 #ifdef HOST_IMM_ADDR32
b9b61529 4309 if((itype[i]!=LOAD&&(opcode[i]&0x3b)!=0x31&&(opcode[i]&0x3b)!=0x32) || // LWC1/LDC1/LWC2/LDC2
57871462 4310 (using_tlb&&((signed int)constmap[i][rs]+offset)>=(signed int)0xC0000000))
4311 #endif
4312 emit_movimm(constmap[i][rs]+offset,ra);
8575a877 4313 regs[i].loadedconst|=1<<ra;
57871462 4314 }
4315 } // else did it in the previous cycle
4316 } // else load_consts already did it
4317 }
4318 if(offset&&!c&&rs1[i]) {
4319 if(rs>=0) {
4320 emit_addimm(rs,offset,ra);
4321 }else{
4322 emit_addimm(ra,offset,ra);
4323 }
4324 }
4325 }
4326 }
4327 // Preload constants for next instruction
b9b61529 4328 if(itype[i+1]==LOAD||itype[i+1]==LOADLR||itype[i+1]==STORE||itype[i+1]==STORELR||itype[i+1]==C1LS||itype[i+1]==C2LS) {
57871462 4329 int agr,ra;
63cb0298 4330 #if !defined(HOST_IMM_ADDR32) && !defined(DISABLE_TLB)
57871462 4331 // Mapper entry
4332 agr=MGEN1+((i+1)&1);
4333 ra=get_reg(i_regs->regmap,agr);
4334 if(ra>=0) {
4335 int rs=get_reg(regs[i+1].regmap,rs1[i+1]);
4336 int offset=imm[i+1];
4337 int c=(regs[i+1].wasconst>>rs)&1;
4338 if(c) {
b9b61529 4339 if(itype[i+1]==STORE||itype[i+1]==STORELR
4340 ||(opcode[i+1]&0x3b)==0x39||(opcode[i+1]&0x3b)==0x3a) { // SWC1/SDC1, SWC2/SDC2
57871462 4341 // Stores to memory go thru the mapper to detect self-modifying
4342 // code, loads don't.
4343 if((unsigned int)(constmap[i+1][rs]+offset)>=0xC0000000 ||
4cb76aa4 4344 (unsigned int)(constmap[i+1][rs]+offset)<0x80000000+RAM_SIZE )
57871462 4345 generate_map_const(constmap[i+1][rs]+offset,ra);
4346 }else{
4347 if((signed int)(constmap[i+1][rs]+offset)>=(signed int)0xC0000000)
4348 generate_map_const(constmap[i+1][rs]+offset,ra);
4349 }
4350 }
4351 /*else if(rs1[i]==0) {
4352 generate_map_const(offset,ra);
4353 }*/
4354 }
4355 #endif
4356 // Actual address
4357 agr=AGEN1+((i+1)&1);
4358 ra=get_reg(i_regs->regmap,agr);
4359 if(ra>=0) {
4360 int rs=get_reg(regs[i+1].regmap,rs1[i+1]);
4361 int offset=imm[i+1];
4362 int c=(regs[i+1].wasconst>>rs)&1;
4363 if(c&&(rs1[i+1]!=rt1[i+1]||itype[i+1]!=LOAD)) {
4364 if (opcode[i+1]==0x22||opcode[i+1]==0x26) {
4365 emit_movimm((constmap[i+1][rs]+offset)&0xFFFFFFFC,ra); // LWL/LWR
4366 }else if (opcode[i+1]==0x1a||opcode[i+1]==0x1b) {
4367 emit_movimm((constmap[i+1][rs]+offset)&0xFFFFFFF8,ra); // LDL/LDR
4368 }else{
4369 #ifdef HOST_IMM_ADDR32
b9b61529 4370 if((itype[i+1]!=LOAD&&(opcode[i+1]&0x3b)!=0x31&&(opcode[i+1]&0x3b)!=0x32) || // LWC1/LDC1/LWC2/LDC2
57871462 4371 (using_tlb&&((signed int)constmap[i+1][rs]+offset)>=(signed int)0xC0000000))
4372 #endif
4373 emit_movimm(constmap[i+1][rs]+offset,ra);
8575a877 4374 regs[i+1].loadedconst|=1<<ra;
57871462 4375 }
4376 }
4377 else if(rs1[i+1]==0) {
4378 // Using r0 as a base address
4379 if (opcode[i+1]==0x22||opcode[i+1]==0x26) {
4380 emit_movimm(offset&0xFFFFFFFC,ra); // LWL/LWR
4381 }else if (opcode[i+1]==0x1a||opcode[i+1]==0x1b) {
4382 emit_movimm(offset&0xFFFFFFF8,ra); // LDL/LDR
4383 }else{
4384 emit_movimm(offset,ra);
4385 }
4386 }
4387 }
4388 }
4389}
4390
4391int get_final_value(int hr, int i, int *value)
4392{
4393 int reg=regs[i].regmap[hr];
4394 while(i<slen-1) {
4395 if(regs[i+1].regmap[hr]!=reg) break;
4396 if(!((regs[i+1].isconst>>hr)&1)) break;
4397 if(bt[i+1]) break;
4398 i++;
4399 }
4400 if(i<slen-1) {
4401 if(itype[i]==UJUMP||itype[i]==RJUMP||itype[i]==CJUMP||itype[i]==SJUMP) {
4402 *value=constmap[i][hr];
4403 return 1;
4404 }
4405 if(!bt[i+1]) {
4406 if(itype[i+1]==UJUMP||itype[i+1]==RJUMP||itype[i+1]==CJUMP||itype[i+1]==SJUMP) {
4407 // Load in delay slot, out-of-order execution
4408 if(itype[i+2]==LOAD&&rs1[i+2]==reg&&rt1[i+2]==reg&&((regs[i+1].wasconst>>hr)&1))
4409 {
4410 #ifdef HOST_IMM_ADDR32
4411 if(!using_tlb||((signed int)constmap[i][hr]+imm[i+2])<(signed int)0xC0000000) return 0;
4412 #endif
4413 // Precompute load address
4414 *value=constmap[i][hr]+imm[i+2];
4415 return 1;
4416 }
4417 }
4418 if(itype[i+1]==LOAD&&rs1[i+1]==reg&&rt1[i+1]==reg)
4419 {
4420 #ifdef HOST_IMM_ADDR32
4421 if(!using_tlb||((signed int)constmap[i][hr]+imm[i+1])<(signed int)0xC0000000) return 0;
4422 #endif
4423 // Precompute load address
4424 *value=constmap[i][hr]+imm[i+1];
4425 //printf("c=%x imm=%x\n",(int)constmap[i][hr],imm[i+1]);
4426 return 1;
4427 }
4428 }
4429 }
4430 *value=constmap[i][hr];
4431 //printf("c=%x\n",(int)constmap[i][hr]);
4432 if(i==slen-1) return 1;
4433 if(reg<64) {
4434 return !((unneeded_reg[i+1]>>reg)&1);
4435 }else{
4436 return !((unneeded_reg_upper[i+1]>>reg)&1);
4437 }
4438}
4439
4440// Load registers with known constants
4441void load_consts(signed char pre[],signed char regmap[],int is32,int i)
4442{
8575a877 4443 int hr,hr2;
4444 // propagate loaded constant flags
4445 if(i==0||bt[i])
4446 regs[i].loadedconst=0;
4447 else {
4448 for(hr=0;hr<HOST_REGS;hr++) {
4449 if(hr!=EXCLUDE_REG&&regmap[hr]>=0&&((regs[i-1].isconst>>hr)&1)&&pre[hr]==regmap[hr]
4450 &&regmap[hr]==regs[i-1].regmap[hr]&&((regs[i-1].loadedconst>>hr)&1))
4451 {
4452 regs[i].loadedconst|=1<<hr;
4453 }
4454 }
4455 }
57871462 4456 // Load 32-bit regs
4457 for(hr=0;hr<HOST_REGS;hr++) {
4458 if(hr!=EXCLUDE_REG&&regmap[hr]>=0) {
4459 //if(entry[hr]!=regmap[hr]) {
8575a877 4460 if(!((regs[i].loadedconst>>hr)&1)) {
57871462 4461 if(((regs[i].isconst>>hr)&1)&&regmap[hr]<64&&regmap[hr]>0) {
8575a877 4462 int value,similar=0;
57871462 4463 if(get_final_value(hr,i,&value)) {
8575a877 4464 // see if some other register has similar value
4465 for(hr2=0;hr2<HOST_REGS;hr2++) {
4466 if(hr2!=EXCLUDE_REG&&((regs[i].loadedconst>>hr2)&1)) {
4467 if(is_similar_value(value,constmap[i][hr2])) {
4468 similar=1;
4469 break;
4470 }
4471 }
4472 }
4473 if(similar) {
4474 int value2;
4475 if(get_final_value(hr2,i,&value2)) // is this needed?
4476 emit_movimm_from(value2,hr2,value,hr);
4477 else
4478 emit_movimm(value,hr);
4479 }
4480 else if(value==0) {
57871462 4481 emit_zeroreg(hr);
4482 }
4483 else {
4484 emit_movimm(value,hr);
4485 }
4486 }
8575a877 4487 regs[i].loadedconst|=1<<hr;
57871462 4488 }
4489 }
4490 }
4491 }
4492 // Load 64-bit regs
4493 for(hr=0;hr<HOST_REGS;hr++) {
4494 if(hr!=EXCLUDE_REG&&regmap[hr]>=0) {
4495 //if(entry[hr]!=regmap[hr]) {
4496 if(i==0||!((regs[i-1].isconst>>hr)&1)||pre[hr]!=regmap[hr]||bt[i]) {
4497 if(((regs[i].isconst>>hr)&1)&&regmap[hr]>64) {
4498 if((is32>>(regmap[hr]&63))&1) {
4499 int lr=get_reg(regmap,regmap[hr]-64);
4500 assert(lr>=0);
4501 emit_sarimm(lr,31,hr);
4502 }
4503 else
4504 {
4505 int value;
4506 if(get_final_value(hr,i,&value)) {
4507 if(value==0) {
4508 emit_zeroreg(hr);
4509 }
4510 else {
4511 emit_movimm(value,hr);
4512 }
4513 }
4514 }
4515 }
4516 }
4517 }
4518 }
4519}
4520void load_all_consts(signed char regmap[],int is32,u_int dirty,int i)
4521{
4522 int hr;
4523 // Load 32-bit regs
4524 for(hr=0;hr<HOST_REGS;hr++) {
4525 if(hr!=EXCLUDE_REG&&regmap[hr]>=0&&((dirty>>hr)&1)) {
4526 if(((regs[i].isconst>>hr)&1)&&regmap[hr]<64&&regmap[hr]>0) {
4527 int value=constmap[i][hr];
4528 if(value==0) {
4529 emit_zeroreg(hr);
4530 }
4531 else {
4532 emit_movimm(value,hr);
4533 }
4534 }
4535 }
4536 }
4537 // Load 64-bit regs
4538 for(hr=0;hr<HOST_REGS;hr++) {
4539 if(hr!=EXCLUDE_REG&&regmap[hr]>=0&&((dirty>>hr)&1)) {
4540 if(((regs[i].isconst>>hr)&1)&&regmap[hr]>64) {
4541 if((is32>>(regmap[hr]&63))&1) {
4542 int lr=get_reg(regmap,regmap[hr]-64);
4543 assert(lr>=0);
4544 emit_sarimm(lr,31,hr);
4545 }
4546 else
4547 {
4548 int value=constmap[i][hr];
4549 if(value==0) {
4550 emit_zeroreg(hr);
4551 }
4552 else {
4553 emit_movimm(value,hr);
4554 }
4555 }
4556 }
4557 }
4558 }
4559}
4560
4561// Write out all dirty registers (except cycle count)
4562void wb_dirtys(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty)
4563{
4564 int hr;
4565 for(hr=0;hr<HOST_REGS;hr++) {
4566 if(hr!=EXCLUDE_REG) {
4567 if(i_regmap[hr]>0) {
4568 if(i_regmap[hr]!=CCREG) {
4569 if((i_dirty>>hr)&1) {
4570 if(i_regmap[hr]<64) {
4571 emit_storereg(i_regmap[hr],hr);
24385cae 4572#ifndef FORCE32
57871462 4573 if( ((i_is32>>i_regmap[hr])&1) ) {
4574 #ifdef DESTRUCTIVE_WRITEBACK
4575 emit_sarimm(hr,31,hr);
4576 emit_storereg(i_regmap[hr]|64,hr);
4577 #else
4578 emit_sarimm(hr,31,HOST_TEMPREG);
4579 emit_storereg(i_regmap[hr]|64,HOST_TEMPREG);
4580 #endif
4581 }
24385cae 4582#endif
57871462 4583 }else{
4584 if( !((i_is32>>(i_regmap[hr]&63))&1) ) {
4585 emit_storereg(i_regmap[hr],hr);
4586 }
4587 }
4588 }
4589 }
4590 }
4591 }
4592 }
4593}
4594// Write out dirty registers that we need to reload (pair with load_needed_regs)
4595// This writes the registers not written by store_regs_bt
4596void wb_needed_dirtys(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr)
4597{
4598 int hr;
4599 int t=(addr-start)>>2;
4600 for(hr=0;hr<HOST_REGS;hr++) {
4601 if(hr!=EXCLUDE_REG) {
4602 if(i_regmap[hr]>0) {
4603 if(i_regmap[hr]!=CCREG) {
4604 if(i_regmap[hr]==regs[t].regmap_entry[hr] && ((regs[t].dirty>>hr)&1) && !(((i_is32&~regs[t].was32&~unneeded_reg_upper[t])>>(i_regmap[hr]&63))&1)) {
4605 if((i_dirty>>hr)&1) {
4606 if(i_regmap[hr]<64) {
4607 emit_storereg(i_regmap[hr],hr);
24385cae 4608#ifndef FORCE32
57871462 4609 if( ((i_is32>>i_regmap[hr])&1) ) {
4610 #ifdef DESTRUCTIVE_WRITEBACK
4611 emit_sarimm(hr,31,hr);
4612 emit_storereg(i_regmap[hr]|64,hr);
4613 #else
4614 emit_sarimm(hr,31,HOST_TEMPREG);
4615 emit_storereg(i_regmap[hr]|64,HOST_TEMPREG);
4616 #endif
4617 }
24385cae 4618#endif
57871462 4619 }else{
4620 if( !((i_is32>>(i_regmap[hr]&63))&1) ) {
4621 emit_storereg(i_regmap[hr],hr);
4622 }
4623 }
4624 }
4625 }
4626 }
4627 }
4628 }
4629 }
4630}
4631
4632// Load all registers (except cycle count)
4633void load_all_regs(signed char i_regmap[])
4634{
4635 int hr;
4636 for(hr=0;hr<HOST_REGS;hr++) {
4637 if(hr!=EXCLUDE_REG) {
4638 if(i_regmap[hr]==0) {
4639 emit_zeroreg(hr);
4640 }
4641 else
ea3d2e6e 4642 if(i_regmap[hr]>0 && (i_regmap[hr]&63)<TEMPREG && i_regmap[hr]!=CCREG)
57871462 4643 {
4644 emit_loadreg(i_regmap[hr],hr);
4645 }
4646 }
4647 }
4648}
4649
4650// Load all current registers also needed by next instruction
4651void load_needed_regs(signed char i_regmap[],signed char next_regmap[])
4652{
4653 int hr;
4654 for(hr=0;hr<HOST_REGS;hr++) {
4655 if(hr!=EXCLUDE_REG) {
4656 if(get_reg(next_regmap,i_regmap[hr])>=0) {
4657 if(i_regmap[hr]==0) {
4658 emit_zeroreg(hr);
4659 }
4660 else
ea3d2e6e 4661 if(i_regmap[hr]>0 && (i_regmap[hr]&63)<TEMPREG && i_regmap[hr]!=CCREG)
57871462 4662 {
4663 emit_loadreg(i_regmap[hr],hr);
4664 }
4665 }
4666 }
4667 }
4668}
4669
4670// Load all regs, storing cycle count if necessary
4671void load_regs_entry(int t)
4672{
4673 int hr;
2573466a 4674 if(is_ds[t]) emit_addimm(HOST_CCREG,CLOCK_ADJUST(1),HOST_CCREG);
4675 else if(ccadj[t]) emit_addimm(HOST_CCREG,-CLOCK_ADJUST(ccadj[t]),HOST_CCREG);
57871462 4676 if(regs[t].regmap_entry[HOST_CCREG]!=CCREG) {
4677 emit_storereg(CCREG,HOST_CCREG);
4678 }
4679 // Load 32-bit regs
4680 for(hr=0;hr<HOST_REGS;hr++) {
ea3d2e6e 4681 if(regs[t].regmap_entry[hr]>=0&&regs[t].regmap_entry[hr]<TEMPREG) {
57871462 4682 if(regs[t].regmap_entry[hr]==0) {
4683 emit_zeroreg(hr);
4684 }
4685 else if(regs[t].regmap_entry[hr]!=CCREG)
4686 {
4687 emit_loadreg(regs[t].regmap_entry[hr],hr);
4688 }
4689 }
4690 }
4691 // Load 64-bit regs
4692 for(hr=0;hr<HOST_REGS;hr++) {
ea3d2e6e 4693 if(regs[t].regmap_entry[hr]>=64&&regs[t].regmap_entry[hr]<TEMPREG+64) {
57871462 4694 assert(regs[t].regmap_entry[hr]!=64);
4695 if((regs[t].was32>>(regs[t].regmap_entry[hr]&63))&1) {
4696 int lr=get_reg(regs[t].regmap_entry,regs[t].regmap_entry[hr]-64);
4697 if(lr<0) {
4698 emit_loadreg(regs[t].regmap_entry[hr],hr);
4699 }
4700 else
4701 {
4702 emit_sarimm(lr,31,hr);
4703 }
4704 }
4705 else
4706 {
4707 emit_loadreg(regs[t].regmap_entry[hr],hr);
4708 }
4709 }
4710 }
4711}
4712
4713// Store dirty registers prior to branch
4714void store_regs_bt(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr)
4715{
4716 if(internal_branch(i_is32,addr))
4717 {
4718 int t=(addr-start)>>2;
4719 int hr;
4720 for(hr=0;hr<HOST_REGS;hr++) {
4721 if(hr!=EXCLUDE_REG) {
4722 if(i_regmap[hr]>0 && i_regmap[hr]!=CCREG) {
4723 if(i_regmap[hr]!=regs[t].regmap_entry[hr] || !((regs[t].dirty>>hr)&1) || (((i_is32&~regs[t].was32&~unneeded_reg_upper[t])>>(i_regmap[hr]&63))&1)) {
4724 if((i_dirty>>hr)&1) {
4725 if(i_regmap[hr]<64) {
4726 if(!((unneeded_reg[t]>>i_regmap[hr])&1)) {
4727 emit_storereg(i_regmap[hr],hr);
4728 if( ((i_is32>>i_regmap[hr])&1) && !((unneeded_reg_upper[t]>>i_regmap[hr])&1) ) {
4729 #ifdef DESTRUCTIVE_WRITEBACK
4730 emit_sarimm(hr,31,hr);
4731 emit_storereg(i_regmap[hr]|64,hr);
4732 #else
4733 emit_sarimm(hr,31,HOST_TEMPREG);
4734 emit_storereg(i_regmap[hr]|64,HOST_TEMPREG);
4735 #endif
4736 }
4737 }
4738 }else{
4739 if( !((i_is32>>(i_regmap[hr]&63))&1) && !((unneeded_reg_upper[t]>>(i_regmap[hr]&63))&1) ) {
4740 emit_storereg(i_regmap[hr],hr);
4741 }
4742 }
4743 }
4744 }
4745 }
4746 }
4747 }
4748 }
4749 else
4750 {
4751 // Branch out of this block, write out all dirty regs
4752 wb_dirtys(i_regmap,i_is32,i_dirty);
4753 }
4754}
4755
4756// Load all needed registers for branch target
4757void load_regs_bt(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr)
4758{
4759 //if(addr>=start && addr<(start+slen*4))
4760 if(internal_branch(i_is32,addr))
4761 {
4762 int t=(addr-start)>>2;
4763 int hr;
4764 // Store the cycle count before loading something else
4765 if(i_regmap[HOST_CCREG]!=CCREG) {
4766 assert(i_regmap[HOST_CCREG]==-1);
4767 }
4768 if(regs[t].regmap_entry[HOST_CCREG]!=CCREG) {
4769 emit_storereg(CCREG,HOST_CCREG);
4770 }
4771 // Load 32-bit regs
4772 for(hr=0;hr<HOST_REGS;hr++) {
ea3d2e6e 4773 if(hr!=EXCLUDE_REG&&regs[t].regmap_entry[hr]>=0&&regs[t].regmap_entry[hr]<TEMPREG) {
57871462 4774 #ifdef DESTRUCTIVE_WRITEBACK
4775 if(i_regmap[hr]!=regs[t].regmap_entry[hr] || ( !((regs[t].dirty>>hr)&1) && ((i_dirty>>hr)&1) && (((i_is32&~unneeded_reg_upper[t])>>i_regmap[hr])&1) ) || (((i_is32&~regs[t].was32&~unneeded_reg_upper[t])>>(i_regmap[hr]&63))&1)) {
4776 #else
4777 if(i_regmap[hr]!=regs[t].regmap_entry[hr] ) {
4778 #endif
4779 if(regs[t].regmap_entry[hr]==0) {
4780 emit_zeroreg(hr);
4781 }
4782 else if(regs[t].regmap_entry[hr]!=CCREG)
4783 {
4784 emit_loadreg(regs[t].regmap_entry[hr],hr);
4785 }
4786 }
4787 }
4788 }
4789 //Load 64-bit regs
4790 for(hr=0;hr<HOST_REGS;hr++) {
ea3d2e6e 4791 if(hr!=EXCLUDE_REG&&regs[t].regmap_entry[hr]>=64&&regs[t].regmap_entry[hr]<TEMPREG+64) {
57871462 4792 if(i_regmap[hr]!=regs[t].regmap_entry[hr]) {
4793 assert(regs[t].regmap_entry[hr]!=64);
4794 if((i_is32>>(regs[t].regmap_entry[hr]&63))&1) {
4795 int lr=get_reg(regs[t].regmap_entry,regs[t].regmap_entry[hr]-64);
4796 if(lr<0) {
4797 emit_loadreg(regs[t].regmap_entry[hr],hr);
4798 }
4799 else
4800 {
4801 emit_sarimm(lr,31,hr);
4802 }
4803 }
4804 else
4805 {
4806 emit_loadreg(regs[t].regmap_entry[hr],hr);
4807 }
4808 }
4809 else if((i_is32>>(regs[t].regmap_entry[hr]&63))&1) {
4810 int lr=get_reg(regs[t].regmap_entry,regs[t].regmap_entry[hr]-64);
4811 assert(lr>=0);
4812 emit_sarimm(lr,31,hr);
4813 }
4814 }
4815 }
4816 }
4817}
4818
4819int match_bt(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr)
4820{
4821 if(addr>=start && addr<start+slen*4-4)
4822 {
4823 int t=(addr-start)>>2;
4824 int hr;
4825 if(regs[t].regmap_entry[HOST_CCREG]!=CCREG) return 0;
4826 for(hr=0;hr<HOST_REGS;hr++)
4827 {
4828 if(hr!=EXCLUDE_REG)
4829 {
4830 if(i_regmap[hr]!=regs[t].regmap_entry[hr])
4831 {
ea3d2e6e 4832 if(regs[t].regmap_entry[hr]>=0&&(regs[t].regmap_entry[hr]|64)<TEMPREG+64)
57871462 4833 {
4834 return 0;
4835 }
4836 else
4837 if((i_dirty>>hr)&1)
4838 {
ea3d2e6e 4839 if(i_regmap[hr]<TEMPREG)
57871462 4840 {
4841 if(!((unneeded_reg[t]>>i_regmap[hr])&1))
4842 return 0;
4843 }
ea3d2e6e 4844 else if(i_regmap[hr]>=64&&i_regmap[hr]<TEMPREG+64)
57871462 4845 {
4846 if(!((unneeded_reg_upper[t]>>(i_regmap[hr]&63))&1))
4847 return 0;
4848 }
4849 }
4850 }
4851 else // Same register but is it 32-bit or dirty?
4852 if(i_regmap[hr]>=0)
4853 {
4854 if(!((regs[t].dirty>>hr)&1))
4855 {
4856 if((i_dirty>>hr)&1)
4857 {
4858 if(!((unneeded_reg[t]>>i_regmap[hr])&1))
4859 {
4860 //printf("%x: dirty no match\n",addr);
4861 return 0;
4862 }
4863 }
4864 }
4865 if((((regs[t].was32^i_is32)&~unneeded_reg_upper[t])>>(i_regmap[hr]&63))&1)
4866 {
4867 //printf("%x: is32 no match\n",addr);
4868 return 0;
4869 }
4870 }
4871 }
4872 }
4873 //if(is32[t]&~unneeded_reg_upper[t]&~i_is32) return 0;
a28c6ce8 4874#ifndef FORCE32
57871462 4875 if(requires_32bit[t]&~i_is32) return 0;
a28c6ce8 4876#endif
57871462 4877 // Delay slots are not valid branch targets
4878 //if(t>0&&(itype[t-1]==RJUMP||itype[t-1]==UJUMP||itype[t-1]==CJUMP||itype[t-1]==SJUMP||itype[t-1]==FJUMP)) return 0;
4879 // Delay slots require additional processing, so do not match
4880 if(is_ds[t]) return 0;
4881 }
4882 else
4883 {
4884 int hr;
4885 for(hr=0;hr<HOST_REGS;hr++)
4886 {
4887 if(hr!=EXCLUDE_REG)
4888 {
4889 if(i_regmap[hr]>=0)
4890 {
4891 if(hr!=HOST_CCREG||i_regmap[hr]!=CCREG)
4892 {
4893 if((i_dirty>>hr)&1)
4894 {
4895 return 0;
4896 }
4897 }
4898 }
4899 }
4900 }
4901 }
4902 return 1;
4903}
4904
4905// Used when a branch jumps into the delay slot of another branch
4906void ds_assemble_entry(int i)
4907{
4908 int t=(ba[i]-start)>>2;
4909 if(!instr_addr[t]) instr_addr[t]=(u_int)out;
4910 assem_debug("Assemble delay slot at %x\n",ba[i]);
4911 assem_debug("<->\n");
4912 if(regs[t].regmap_entry[HOST_CCREG]==CCREG&&regs[t].regmap[HOST_CCREG]!=CCREG)
4913 wb_register(CCREG,regs[t].regmap_entry,regs[t].wasdirty,regs[t].was32);
4914 load_regs(regs[t].regmap_entry,regs[t].regmap,regs[t].was32,rs1[t],rs2[t]);
4915 address_generation(t,&regs[t],regs[t].regmap_entry);
b9b61529 4916 if(itype[t]==STORE||itype[t]==STORELR||(opcode[t]&0x3b)==0x39||(opcode[t]&0x3b)==0x3a)
57871462 4917 load_regs(regs[t].regmap_entry,regs[t].regmap,regs[t].was32,INVCP,INVCP);
4918 cop1_usable=0;
4919 is_delayslot=0;
4920 switch(itype[t]) {
4921 case ALU:
4922 alu_assemble(t,&regs[t]);break;
4923 case IMM16:
4924 imm16_assemble(t,&regs[t]);break;
4925 case SHIFT:
4926 shift_assemble(t,&regs[t]);break;
4927 case SHIFTIMM:
4928 shiftimm_assemble(t,&regs[t]);break;
4929 case LOAD:
4930 load_assemble(t,&regs[t]);break;
4931 case LOADLR:
4932 loadlr_assemble(t,&regs[t]);break;
4933 case STORE:
4934 store_assemble(t,&regs[t]);break;
4935 case STORELR:
4936 storelr_assemble(t,&regs[t]);break;
4937 case COP0:
4938 cop0_assemble(t,&regs[t]);break;
4939 case COP1:
4940 cop1_assemble(t,&regs[t]);break;
4941 case C1LS:
4942 c1ls_assemble(t,&regs[t]);break;
b9b61529 4943 case COP2:
4944 cop2_assemble(t,&regs[t]);break;
4945 case C2LS:
4946 c2ls_assemble(t,&regs[t]);break;
4947 case C2OP:
4948 c2op_assemble(t,&regs[t]);break;
57871462 4949 case FCONV:
4950 fconv_assemble(t,&regs[t]);break;
4951 case FLOAT:
4952 float_assemble(t,&regs[t]);break;
4953 case FCOMP:
4954 fcomp_assemble(t,&regs[t]);break;
4955 case MULTDIV:
4956 multdiv_assemble(t,&regs[t]);break;
4957 case MOV:
4958 mov_assemble(t,&regs[t]);break;
4959 case SYSCALL:
7139f3c8 4960 case HLECALL:
1e973cb0 4961 case INTCALL:
57871462 4962 case SPAN:
4963 case UJUMP:
4964 case RJUMP:
4965 case CJUMP:
4966 case SJUMP:
4967 case FJUMP:
4968 printf("Jump in the delay slot. This is probably a bug.\n");
4969 }
4970 store_regs_bt(regs[t].regmap,regs[t].is32,regs[t].dirty,ba[i]+4);
4971 load_regs_bt(regs[t].regmap,regs[t].is32,regs[t].dirty,ba[i]+4);
4972 if(internal_branch(regs[t].is32,ba[i]+4))
4973 assem_debug("branch: internal\n");
4974 else
4975 assem_debug("branch: external\n");
4976 assert(internal_branch(regs[t].is32,ba[i]+4));
4977 add_to_linker((int)out,ba[i]+4,internal_branch(regs[t].is32,ba[i]+4));
4978 emit_jmp(0);
4979}
4980
4981void do_cc(int i,signed char i_regmap[],int *adj,int addr,int taken,int invert)
4982{
4983 int count;
4984 int jaddr;
4985 int idle=0;
b6e87b2b 4986 int t=0;
57871462 4987 if(itype[i]==RJUMP)
4988 {
4989 *adj=0;
4990 }
4991 //if(ba[i]>=start && ba[i]<(start+slen*4))
4992 if(internal_branch(branch_regs[i].is32,ba[i]))
4993 {
b6e87b2b 4994 t=(ba[i]-start)>>2;
57871462 4995 if(is_ds[t]) *adj=-1; // Branch into delay slot adds an extra cycle
4996 else *adj=ccadj[t];
4997 }
4998 else
4999 {
5000 *adj=0;
5001 }
5002 count=ccadj[i];
5003 if(taken==TAKEN && i==(ba[i]-start)>>2 && source[i+1]==0) {
5004 // Idle loop
5005 if(count&1) emit_addimm_and_set_flags(2*(count+2),HOST_CCREG);
5006 idle=(int)out;
5007 //emit_subfrommem(&idlecount,HOST_CCREG); // Count idle cycles
5008 emit_andimm(HOST_CCREG,3,HOST_CCREG);
5009 jaddr=(int)out;
5010 emit_jmp(0);
5011 }
5012 else if(*adj==0||invert) {
b6e87b2b 5013 int cycles=CLOCK_ADJUST(count+2);
5014 // faster loop HACK
5015 if (t&&*adj) {
5016 int rel=t-i;
5017 if(-NO_CYCLE_PENALTY_THR<rel&&rel<0)
5018 cycles=CLOCK_ADJUST(*adj)+count+2-*adj;
5019 }
5020 emit_addimm_and_set_flags(cycles,HOST_CCREG);
57871462 5021 jaddr=(int)out;
5022 emit_jns(0);
5023 }
5024 else
5025 {
2573466a 5026 emit_cmpimm(HOST_CCREG,-CLOCK_ADJUST(count+2));
57871462 5027 jaddr=(int)out;
5028 emit_jns(0);
5029 }
5030 add_stub(CC_STUB,jaddr,idle?idle:(int)out,(*adj==0||invert||idle)?0:(count+2),i,addr,taken,0);
5031}
5032
5033void do_ccstub(int n)
5034{
5035 literal_pool(256);
5036 assem_debug("do_ccstub %x\n",start+stubs[n][4]*4);
5037 set_jump_target(stubs[n][1],(int)out);
5038 int i=stubs[n][4];
5039 if(stubs[n][6]==NULLDS) {
5040 // Delay slot instruction is nullified ("likely" branch)
5041 wb_dirtys(regs[i].regmap,regs[i].is32,regs[i].dirty);
5042 }
5043 else if(stubs[n][6]!=TAKEN) {
5044 wb_dirtys(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty);
5045 }
5046 else {
5047 if(internal_branch(branch_regs[i].is32,ba[i]))
5048 wb_needed_dirtys(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5049 }
5050 if(stubs[n][5]!=-1)
5051 {
5052 // Save PC as return address
5053 emit_movimm(stubs[n][5],EAX);
5054 emit_writeword(EAX,(int)&pcaddr);
5055 }
5056 else
5057 {
5058 // Return address depends on which way the branch goes
5059 if(itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
5060 {
5061 int s1l=get_reg(branch_regs[i].regmap,rs1[i]);
5062 int s1h=get_reg(branch_regs[i].regmap,rs1[i]|64);
5063 int s2l=get_reg(branch_regs[i].regmap,rs2[i]);
5064 int s2h=get_reg(branch_regs[i].regmap,rs2[i]|64);
5065 if(rs1[i]==0)
5066 {
5067 s1l=s2l;s1h=s2h;
5068 s2l=s2h=-1;
5069 }
5070 else if(rs2[i]==0)
5071 {
5072 s2l=s2h=-1;
5073 }
5074 if((branch_regs[i].is32>>rs1[i])&(branch_regs[i].is32>>rs2[i])&1) {
5075 s1h=s2h=-1;
5076 }
5077 assert(s1l>=0);
5078 #ifdef DESTRUCTIVE_WRITEBACK
5079 if(rs1[i]) {
5080 if((branch_regs[i].dirty>>s1l)&(branch_regs[i].is32>>rs1[i])&1)
5081 emit_loadreg(rs1[i],s1l);
5082 }
5083 else {
5084 if((branch_regs[i].dirty>>s1l)&(branch_regs[i].is32>>rs2[i])&1)
5085 emit_loadreg(rs2[i],s1l);
5086 }
5087 if(s2l>=0)
5088 if((branch_regs[i].dirty>>s2l)&(branch_regs[i].is32>>rs2[i])&1)
5089 emit_loadreg(rs2[i],s2l);
5090 #endif
5091 int hr=0;
5194fb95 5092 int addr=-1,alt=-1,ntaddr=-1;
57871462 5093 while(hr<HOST_REGS)
5094 {
5095 if(hr!=EXCLUDE_REG && hr!=HOST_CCREG &&
5096 (branch_regs[i].regmap[hr]&63)!=rs1[i] &&
5097 (branch_regs[i].regmap[hr]&63)!=rs2[i] )
5098 {
5099 addr=hr++;break;
5100 }
5101 hr++;
5102 }
5103 while(hr<HOST_REGS)
5104 {
5105 if(hr!=EXCLUDE_REG && hr!=HOST_CCREG &&
5106 (branch_regs[i].regmap[hr]&63)!=rs1[i] &&
5107 (branch_regs[i].regmap[hr]&63)!=rs2[i] )
5108 {
5109 alt=hr++;break;
5110 }
5111 hr++;
5112 }
5113 if((opcode[i]&0x2E)==6) // BLEZ/BGTZ needs another register
5114 {
5115 while(hr<HOST_REGS)
5116 {
5117 if(hr!=EXCLUDE_REG && hr!=HOST_CCREG &&
5118 (branch_regs[i].regmap[hr]&63)!=rs1[i] &&
5119 (branch_regs[i].regmap[hr]&63)!=rs2[i] )
5120 {
5121 ntaddr=hr;break;
5122 }
5123 hr++;
5124 }
5125 assert(hr<HOST_REGS);
5126 }
5127 if((opcode[i]&0x2f)==4) // BEQ
5128 {
5129 #ifdef HAVE_CMOV_IMM
5130 if(s1h<0) {
5131 if(s2l>=0) emit_cmp(s1l,s2l);
5132 else emit_test(s1l,s1l);
5133 emit_cmov2imm_e_ne_compact(ba[i],start+i*4+8,addr);
5134 }
5135 else
5136 #endif
5137 {
5138 emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
5139 if(s1h>=0) {
5140 if(s2h>=0) emit_cmp(s1h,s2h);
5141 else emit_test(s1h,s1h);
5142 emit_cmovne_reg(alt,addr);
5143 }
5144 if(s2l>=0) emit_cmp(s1l,s2l);
5145 else emit_test(s1l,s1l);
5146 emit_cmovne_reg(alt,addr);
5147 }
5148 }
5149 if((opcode[i]&0x2f)==5) // BNE
5150 {
5151 #ifdef HAVE_CMOV_IMM
5152 if(s1h<0) {
5153 if(s2l>=0) emit_cmp(s1l,s2l);
5154 else emit_test(s1l,s1l);
5155 emit_cmov2imm_e_ne_compact(start+i*4+8,ba[i],addr);
5156 }
5157 else
5158 #endif
5159 {
5160 emit_mov2imm_compact(start+i*4+8,addr,ba[i],alt);
5161 if(s1h>=0) {
5162 if(s2h>=0) emit_cmp(s1h,s2h);
5163 else emit_test(s1h,s1h);
5164 emit_cmovne_reg(alt,addr);
5165 }
5166 if(s2l>=0) emit_cmp(s1l,s2l);
5167 else emit_test(s1l,s1l);
5168 emit_cmovne_reg(alt,addr);
5169 }
5170 }
5171 if((opcode[i]&0x2f)==6) // BLEZ
5172 {
5173 //emit_movimm(ba[i],alt);
5174 //emit_movimm(start+i*4+8,addr);
5175 emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
5176 emit_cmpimm(s1l,1);
5177 if(s1h>=0) emit_mov(addr,ntaddr);
5178 emit_cmovl_reg(alt,addr);
5179 if(s1h>=0) {
5180 emit_test(s1h,s1h);
5181 emit_cmovne_reg(ntaddr,addr);
5182 emit_cmovs_reg(alt,addr);
5183 }
5184 }
5185 if((opcode[i]&0x2f)==7) // BGTZ
5186 {
5187 //emit_movimm(ba[i],addr);
5188 //emit_movimm(start+i*4+8,ntaddr);
5189 emit_mov2imm_compact(ba[i],addr,start+i*4+8,ntaddr);
5190 emit_cmpimm(s1l,1);
5191 if(s1h>=0) emit_mov(addr,alt);
5192 emit_cmovl_reg(ntaddr,addr);
5193 if(s1h>=0) {
5194 emit_test(s1h,s1h);
5195 emit_cmovne_reg(alt,addr);
5196 emit_cmovs_reg(ntaddr,addr);
5197 }
5198 }
5199 if((opcode[i]==1)&&(opcode2[i]&0x2D)==0) // BLTZ
5200 {
5201 //emit_movimm(ba[i],alt);
5202 //emit_movimm(start+i*4+8,addr);
5203 emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
5204 if(s1h>=0) emit_test(s1h,s1h);
5205 else emit_test(s1l,s1l);
5206 emit_cmovs_reg(alt,addr);
5207 }
5208 if((opcode[i]==1)&&(opcode2[i]&0x2D)==1) // BGEZ
5209 {
5210 //emit_movimm(ba[i],addr);
5211 //emit_movimm(start+i*4+8,alt);
5212 emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
5213 if(s1h>=0) emit_test(s1h,s1h);
5214 else emit_test(s1l,s1l);
5215 emit_cmovs_reg(alt,addr);
5216 }
5217 if(opcode[i]==0x11 && opcode2[i]==0x08 ) {
5218 if(source[i]&0x10000) // BC1T
5219 {
5220 //emit_movimm(ba[i],alt);
5221 //emit_movimm(start+i*4+8,addr);
5222 emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
5223 emit_testimm(s1l,0x800000);
5224 emit_cmovne_reg(alt,addr);
5225 }
5226 else // BC1F
5227 {
5228 //emit_movimm(ba[i],addr);
5229 //emit_movimm(start+i*4+8,alt);
5230 emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
5231 emit_testimm(s1l,0x800000);
5232 emit_cmovne_reg(alt,addr);
5233 }
5234 }
5235 emit_writeword(addr,(int)&pcaddr);
5236 }
5237 else
5238 if(itype[i]==RJUMP)
5239 {
5240 int r=get_reg(branch_regs[i].regmap,rs1[i]);
5241 if(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1]) {
5242 r=get_reg(branch_regs[i].regmap,RTEMP);
5243 }
5244 emit_writeword(r,(int)&pcaddr);
5245 }
5246 else {printf("Unknown branch type in do_ccstub\n");exit(1);}
5247 }
5248 // Update cycle count
5249 assert(branch_regs[i].regmap[HOST_CCREG]==CCREG||branch_regs[i].regmap[HOST_CCREG]==-1);
2573466a 5250 if(stubs[n][3]) emit_addimm(HOST_CCREG,CLOCK_ADJUST((int)stubs[n][3]),HOST_CCREG);
57871462 5251 emit_call((int)cc_interrupt);
2573466a 5252 if(stubs[n][3]) emit_addimm(HOST_CCREG,-CLOCK_ADJUST((int)stubs[n][3]),HOST_CCREG);
57871462 5253 if(stubs[n][6]==TAKEN) {
5254 if(internal_branch(branch_regs[i].is32,ba[i]))
5255 load_needed_regs(branch_regs[i].regmap,regs[(ba[i]-start)>>2].regmap_entry);
5256 else if(itype[i]==RJUMP) {
5257 if(get_reg(branch_regs[i].regmap,RTEMP)>=0)
5258 emit_readword((int)&pcaddr,get_reg(branch_regs[i].regmap,RTEMP));
5259 else
5260 emit_loadreg(rs1[i],get_reg(branch_regs[i].regmap,rs1[i]));
5261 }
5262 }else if(stubs[n][6]==NOTTAKEN) {
5263 if(i<slen-2) load_needed_regs(branch_regs[i].regmap,regmap_pre[i+2]);
5264 else load_all_regs(branch_regs[i].regmap);
5265 }else if(stubs[n][6]==NULLDS) {
5266 // Delay slot instruction is nullified ("likely" branch)
5267 if(i<slen-2) load_needed_regs(regs[i].regmap,regmap_pre[i+2]);
5268 else load_all_regs(regs[i].regmap);
5269 }else{
5270 load_all_regs(branch_regs[i].regmap);
5271 }
5272 emit_jmp(stubs[n][2]); // return address
5273
5274 /* This works but uses a lot of memory...
5275 emit_readword((int)&last_count,ECX);
5276 emit_add(HOST_CCREG,ECX,EAX);
5277 emit_writeword(EAX,(int)&Count);
5278 emit_call((int)gen_interupt);
5279 emit_readword((int)&Count,HOST_CCREG);
5280 emit_readword((int)&next_interupt,EAX);
5281 emit_readword((int)&pending_exception,EBX);
5282 emit_writeword(EAX,(int)&last_count);
5283 emit_sub(HOST_CCREG,EAX,HOST_CCREG);
5284 emit_test(EBX,EBX);
5285 int jne_instr=(int)out;
5286 emit_jne(0);
5287 if(stubs[n][3]) emit_addimm(HOST_CCREG,-2*stubs[n][3],HOST_CCREG);
5288 load_all_regs(branch_regs[i].regmap);
5289 emit_jmp(stubs[n][2]); // return address
5290 set_jump_target(jne_instr,(int)out);
5291 emit_readword((int)&pcaddr,EAX);
5292 // Call get_addr_ht instead of doing the hash table here.
5293 // This code is executed infrequently and takes up a lot of space
5294 // so smaller is better.
5295 emit_storereg(CCREG,HOST_CCREG);
5296 emit_pushreg(EAX);
5297 emit_call((int)get_addr_ht);
5298 emit_loadreg(CCREG,HOST_CCREG);
5299 emit_addimm(ESP,4,ESP);
5300 emit_jmpreg(EAX);*/
5301}
5302
5303add_to_linker(int addr,int target,int ext)
5304{
5305 link_addr[linkcount][0]=addr;
5306 link_addr[linkcount][1]=target;
5307 link_addr[linkcount][2]=ext;
5308 linkcount++;
5309}
5310
eba830cd 5311static void ujump_assemble_write_ra(int i)
5312{
5313 int rt;
5314 unsigned int return_address;
5315 rt=get_reg(branch_regs[i].regmap,31);
5316 assem_debug("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5317 //assert(rt>=0);
5318 return_address=start+i*4+8;
5319 if(rt>=0) {
5320 #ifdef USE_MINI_HT
5321 if(internal_branch(branch_regs[i].is32,return_address)&&rt1[i+1]!=31) {
5322 int temp=-1; // note: must be ds-safe
5323 #ifdef HOST_TEMPREG
5324 temp=HOST_TEMPREG;
5325 #endif
5326 if(temp>=0) do_miniht_insert(return_address,rt,temp);
5327 else emit_movimm(return_address,rt);
5328 }
5329 else
5330 #endif
5331 {
5332 #ifdef REG_PREFETCH
5333 if(temp>=0)
5334 {
5335 if(i_regmap[temp]!=PTEMP) emit_movimm((int)hash_table[((return_address>>16)^return_address)&0xFFFF],temp);
5336 }
5337 #endif
5338 emit_movimm(return_address,rt); // PC into link register
5339 #ifdef IMM_PREFETCH
5340 emit_prefetch(hash_table[((return_address>>16)^return_address)&0xFFFF]);
5341 #endif
5342 }
5343 }
5344}
5345
57871462 5346void ujump_assemble(int i,struct regstat *i_regs)
5347{
5348 signed char *i_regmap=i_regs->regmap;
eba830cd 5349 int ra_done=0;
57871462 5350 if(i==(ba[i]-start)>>2) assem_debug("idle loop\n");
5351 address_generation(i+1,i_regs,regs[i].regmap_entry);
5352 #ifdef REG_PREFETCH
5353 int temp=get_reg(branch_regs[i].regmap,PTEMP);
5354 if(rt1[i]==31&&temp>=0)
5355 {
5356 int return_address=start+i*4+8;
5357 if(get_reg(branch_regs[i].regmap,31)>0)
5358 if(i_regmap[temp]==PTEMP) emit_movimm((int)hash_table[((return_address>>16)^return_address)&0xFFFF],temp);
5359 }
5360 #endif
eba830cd 5361 if(rt1[i]==31&&(rt1[i]==rs1[i+1]||rt1[i]==rs2[i+1])) {
5362 ujump_assemble_write_ra(i); // writeback ra for DS
5363 ra_done=1;
57871462 5364 }
4ef8f67d 5365 ds_assemble(i+1,i_regs);
5366 uint64_t bc_unneeded=branch_regs[i].u;
5367 uint64_t bc_unneeded_upper=branch_regs[i].uu;
5368 bc_unneeded|=1|(1LL<<rt1[i]);
5369 bc_unneeded_upper|=1|(1LL<<rt1[i]);
5370 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5371 bc_unneeded,bc_unneeded_upper);
5372 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
eba830cd 5373 if(!ra_done&&rt1[i]==31)
5374 ujump_assemble_write_ra(i);
57871462 5375 int cc,adj;
5376 cc=get_reg(branch_regs[i].regmap,CCREG);
5377 assert(cc==HOST_CCREG);
5378 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5379 #ifdef REG_PREFETCH
5380 if(rt1[i]==31&&temp>=0) emit_prefetchreg(temp);
5381 #endif
5382 do_cc(i,branch_regs[i].regmap,&adj,ba[i],TAKEN,0);
2573466a 5383 if(adj) emit_addimm(cc,CLOCK_ADJUST(ccadj[i]+2-adj),cc);
57871462 5384 load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5385 if(internal_branch(branch_regs[i].is32,ba[i]))
5386 assem_debug("branch: internal\n");
5387 else
5388 assem_debug("branch: external\n");
5389 if(internal_branch(branch_regs[i].is32,ba[i])&&is_ds[(ba[i]-start)>>2]) {
5390 ds_assemble_entry(i);
5391 }
5392 else {
5393 add_to_linker((int)out,ba[i],internal_branch(branch_regs[i].is32,ba[i]));
5394 emit_jmp(0);
5395 }
5396}
5397
eba830cd 5398static void rjump_assemble_write_ra(int i)
5399{
5400 int rt,return_address;
5401 assert(rt1[i+1]!=rt1[i]);
5402 assert(rt2[i+1]!=rt1[i]);
5403 rt=get_reg(branch_regs[i].regmap,rt1[i]);
5404 assem_debug("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5405 assert(rt>=0);
5406 return_address=start+i*4+8;
5407 #ifdef REG_PREFETCH
5408 if(temp>=0)
5409 {
5410 if(i_regmap[temp]!=PTEMP) emit_movimm((int)hash_table[((return_address>>16)^return_address)&0xFFFF],temp);
5411 }
5412 #endif
5413 emit_movimm(return_address,rt); // PC into link register
5414 #ifdef IMM_PREFETCH
5415 emit_prefetch(hash_table[((return_address>>16)^return_address)&0xFFFF]);
5416 #endif
5417}
5418
57871462 5419void rjump_assemble(int i,struct regstat *i_regs)
5420{
5421 signed char *i_regmap=i_regs->regmap;
5422 int temp;
5423 int rs,cc,adj;
eba830cd 5424 int ra_done=0;
57871462 5425 rs=get_reg(branch_regs[i].regmap,rs1[i]);
5426 assert(rs>=0);
5427 if(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1]) {
5428 // Delay slot abuse, make a copy of the branch address register
5429 temp=get_reg(branch_regs[i].regmap,RTEMP);
5430 assert(temp>=0);
5431 assert(regs[i].regmap[temp]==RTEMP);
5432 emit_mov(rs,temp);
5433 rs=temp;
5434 }
5435 address_generation(i+1,i_regs,regs[i].regmap_entry);
5436 #ifdef REG_PREFETCH
5437 if(rt1[i]==31)
5438 {
5439 if((temp=get_reg(branch_regs[i].regmap,PTEMP))>=0) {
5440 int return_address=start+i*4+8;
5441 if(i_regmap[temp]==PTEMP) emit_movimm((int)hash_table[((return_address>>16)^return_address)&0xFFFF],temp);
5442 }
5443 }
5444 #endif
5445 #ifdef USE_MINI_HT
5446 if(rs1[i]==31) {
5447 int rh=get_reg(regs[i].regmap,RHASH);
5448 if(rh>=0) do_preload_rhash(rh);
5449 }
5450 #endif
eba830cd 5451 if(rt1[i]!=0&&(rt1[i]==rs1[i+1]||rt1[i]==rs2[i+1])) {
5452 rjump_assemble_write_ra(i);
5453 ra_done=1;
57871462 5454 }
d5910d5d 5455 ds_assemble(i+1,i_regs);
5456 uint64_t bc_unneeded=branch_regs[i].u;
5457 uint64_t bc_unneeded_upper=branch_regs[i].uu;
5458 bc_unneeded|=1|(1LL<<rt1[i]);
5459 bc_unneeded_upper|=1|(1LL<<rt1[i]);
5460 bc_unneeded&=~(1LL<<rs1[i]);
5461 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5462 bc_unneeded,bc_unneeded_upper);
5463 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i],CCREG);
eba830cd 5464 if(!ra_done&&rt1[i]!=0)
5465 rjump_assemble_write_ra(i);
57871462 5466 cc=get_reg(branch_regs[i].regmap,CCREG);
5467 assert(cc==HOST_CCREG);
5468 #ifdef USE_MINI_HT
5469 int rh=get_reg(branch_regs[i].regmap,RHASH);
5470 int ht=get_reg(branch_regs[i].regmap,RHTBL);
5471 if(rs1[i]==31) {
5472 if(regs[i].regmap[rh]!=RHASH) do_preload_rhash(rh);
5473 do_preload_rhtbl(ht);
5474 do_rhash(rs,rh);
5475 }
5476 #endif
5477 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,-1);
5478 #ifdef DESTRUCTIVE_WRITEBACK
5479 if((branch_regs[i].dirty>>rs)&(branch_regs[i].is32>>rs1[i])&1) {
5480 if(rs1[i]!=rt1[i+1]&&rs1[i]!=rt2[i+1]) {
5481 emit_loadreg(rs1[i],rs);
5482 }
5483 }
5484 #endif
5485 #ifdef REG_PREFETCH
5486 if(rt1[i]==31&&temp>=0) emit_prefetchreg(temp);
5487 #endif
5488 #ifdef USE_MINI_HT
5489 if(rs1[i]==31) {
5490 do_miniht_load(ht,rh);
5491 }
5492 #endif
5493 //do_cc(i,branch_regs[i].regmap,&adj,-1,TAKEN);
5494 //if(adj) emit_addimm(cc,2*(ccadj[i]+2-adj),cc); // ??? - Shouldn't happen
5495 //assert(adj==0);
2573466a 5496 emit_addimm_and_set_flags(CLOCK_ADJUST(ccadj[i]+2),HOST_CCREG);
57871462 5497 add_stub(CC_STUB,(int)out,jump_vaddr_reg[rs],0,i,-1,TAKEN,0);
911f2d55 5498#ifdef PCSX
5499 if(itype[i+1]==COP0&&(source[i+1]&0x3f)==0x10)
5500 // special case for RFE
5501 emit_jmp(0);
5502 else
5503#endif
57871462 5504 emit_jns(0);
5505 //load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,-1);
5506 #ifdef USE_MINI_HT
5507 if(rs1[i]==31) {
5508 do_miniht_jump(rs,rh,ht);
5509 }
5510 else
5511 #endif
5512 {
5513 //if(rs!=EAX) emit_mov(rs,EAX);
5514 //emit_jmp((int)jump_vaddr_eax);
5515 emit_jmp(jump_vaddr_reg[rs]);
5516 }
5517 /* Check hash table
5518 temp=!rs;
5519 emit_mov(rs,temp);
5520 emit_shrimm(rs,16,rs);
5521 emit_xor(temp,rs,rs);
5522 emit_movzwl_reg(rs,rs);
5523 emit_shlimm(rs,4,rs);
5524 emit_cmpmem_indexed((int)hash_table,rs,temp);
5525 emit_jne((int)out+14);
5526 emit_readword_indexed((int)hash_table+4,rs,rs);
5527 emit_jmpreg(rs);
5528 emit_cmpmem_indexed((int)hash_table+8,rs,temp);
5529 emit_addimm_no_flags(8,rs);
5530 emit_jeq((int)out-17);
5531 // No hit on hash table, call compiler
5532 emit_pushreg(temp);
5533//DEBUG >
5534#ifdef DEBUG_CYCLE_COUNT
5535 emit_readword((int)&last_count,ECX);
5536 emit_add(HOST_CCREG,ECX,HOST_CCREG);
5537 emit_readword((int)&next_interupt,ECX);
5538 emit_writeword(HOST_CCREG,(int)&Count);
5539 emit_sub(HOST_CCREG,ECX,HOST_CCREG);
5540 emit_writeword(ECX,(int)&last_count);
5541#endif
5542//DEBUG <
5543 emit_storereg(CCREG,HOST_CCREG);
5544 emit_call((int)get_addr);
5545 emit_loadreg(CCREG,HOST_CCREG);
5546 emit_addimm(ESP,4,ESP);
5547 emit_jmpreg(EAX);*/
5548 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5549 if(rt1[i]!=31&&i<slen-2&&(((u_int)out)&7)) emit_mov(13,13);
5550 #endif
5551}
5552
5553void cjump_assemble(int i,struct regstat *i_regs)
5554{
5555 signed char *i_regmap=i_regs->regmap;
5556 int cc;
5557 int match;
5558 match=match_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5559 assem_debug("match=%d\n",match);
5560 int s1h,s1l,s2h,s2l;
5561 int prev_cop1_usable=cop1_usable;
5562 int unconditional=0,nop=0;
5563 int only32=0;
57871462 5564 int invert=0;
5565 int internal=internal_branch(branch_regs[i].is32,ba[i]);
5566 if(i==(ba[i]-start)>>2) assem_debug("idle loop\n");
57871462 5567 if(!match) invert=1;
5568 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5569 if(i>(ba[i]-start)>>2) invert=1;
5570 #endif
e1190b87 5571
5572 if(ooo[i]) {
57871462 5573 s1l=get_reg(branch_regs[i].regmap,rs1[i]);
5574 s1h=get_reg(branch_regs[i].regmap,rs1[i]|64);
5575 s2l=get_reg(branch_regs[i].regmap,rs2[i]);
5576 s2h=get_reg(branch_regs[i].regmap,rs2[i]|64);
5577 }
5578 else {
5579 s1l=get_reg(i_regmap,rs1[i]);
5580 s1h=get_reg(i_regmap,rs1[i]|64);
5581 s2l=get_reg(i_regmap,rs2[i]);
5582 s2h=get_reg(i_regmap,rs2[i]|64);
5583 }
5584 if(rs1[i]==0&&rs2[i]==0)
5585 {
5586 if(opcode[i]&1) nop=1;
5587 else unconditional=1;
5588 //assert(opcode[i]!=5);
5589 //assert(opcode[i]!=7);
5590 //assert(opcode[i]!=0x15);
5591 //assert(opcode[i]!=0x17);
5592 }
5593 else if(rs1[i]==0)
5594 {
5595 s1l=s2l;s1h=s2h;
5596 s2l=s2h=-1;
5597 only32=(regs[i].was32>>rs2[i])&1;
5598 }
5599 else if(rs2[i]==0)
5600 {
5601 s2l=s2h=-1;
5602 only32=(regs[i].was32>>rs1[i])&1;
5603 }
5604 else {
5605 only32=(regs[i].was32>>rs1[i])&(regs[i].was32>>rs2[i])&1;
5606 }
5607
e1190b87 5608 if(ooo[i]) {
57871462 5609 // Out of order execution (delay slot first)
5610 //printf("OOOE\n");
5611 address_generation(i+1,i_regs,regs[i].regmap_entry);
5612 ds_assemble(i+1,i_regs);
5613 int adj;
5614 uint64_t bc_unneeded=branch_regs[i].u;
5615 uint64_t bc_unneeded_upper=branch_regs[i].uu;
5616 bc_unneeded&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
5617 bc_unneeded_upper&=~((1LL<<us1[i])|(1LL<<us2[i]));
5618 bc_unneeded|=1;
5619 bc_unneeded_upper|=1;
5620 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5621 bc_unneeded,bc_unneeded_upper);
5622 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i],rs2[i]);
5623 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
5624 cc=get_reg(branch_regs[i].regmap,CCREG);
5625 assert(cc==HOST_CCREG);
5626 if(unconditional)
5627 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5628 //do_cc(i,branch_regs[i].regmap,&adj,unconditional?ba[i]:-1,unconditional);
5629 //assem_debug("cycle count (adj)\n");
5630 if(unconditional) {
5631 do_cc(i,branch_regs[i].regmap,&adj,ba[i],TAKEN,0);
5632 if(i!=(ba[i]-start)>>2 || source[i+1]!=0) {
2573466a 5633 if(adj) emit_addimm(cc,CLOCK_ADJUST(ccadj[i]+2-adj),cc);
57871462 5634 load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5635 if(internal)
5636 assem_debug("branch: internal\n");
5637 else
5638 assem_debug("branch: external\n");
5639 if(internal&&is_ds[(ba[i]-start)>>2]) {
5640 ds_assemble_entry(i);
5641 }
5642 else {
5643 add_to_linker((int)out,ba[i],internal);
5644 emit_jmp(0);
5645 }
5646 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5647 if(((u_int)out)&7) emit_addnop(0);
5648 #endif
5649 }
5650 }
5651 else if(nop) {
2573466a 5652 emit_addimm_and_set_flags(CLOCK_ADJUST(ccadj[i]+2),cc);
57871462 5653 int jaddr=(int)out;
5654 emit_jns(0);
5655 add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,NOTTAKEN,0);
5656 }
5657 else {
5658 int taken=0,nottaken=0,nottaken1=0;
5659 do_cc(i,branch_regs[i].regmap,&adj,-1,0,invert);
2573466a 5660 if(adj&&!invert) emit_addimm(cc,CLOCK_ADJUST(ccadj[i]+2-adj),cc);
57871462 5661 if(!only32)
5662 {
5663 assert(s1h>=0);
5664 if(opcode[i]==4) // BEQ
5665 {
5666 if(s2h>=0) emit_cmp(s1h,s2h);
5667 else emit_test(s1h,s1h);
5668 nottaken1=(int)out;
5669 emit_jne(1);
5670 }
5671 if(opcode[i]==5) // BNE
5672 {
5673 if(s2h>=0) emit_cmp(s1h,s2h);
5674 else emit_test(s1h,s1h);
5675 if(invert) taken=(int)out;
5676 else add_to_linker((int)out,ba[i],internal);
5677 emit_jne(0);
5678 }
5679 if(opcode[i]==6) // BLEZ
5680 {
5681 emit_test(s1h,s1h);
5682 if(invert) taken=(int)out;
5683 else add_to_linker((int)out,ba[i],internal);
5684 emit_js(0);
5685 nottaken1=(int)out;
5686 emit_jne(1);
5687 }
5688 if(opcode[i]==7) // BGTZ
5689 {
5690 emit_test(s1h,s1h);
5691 nottaken1=(int)out;
5692 emit_js(1);
5693 if(invert) taken=(int)out;
5694 else add_to_linker((int)out,ba[i],internal);
5695 emit_jne(0);
5696 }
5697 } // if(!only32)
5698
5699 //printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5700 assert(s1l>=0);
5701 if(opcode[i]==4) // BEQ
5702 {
5703 if(s2l>=0) emit_cmp(s1l,s2l);
5704 else emit_test(s1l,s1l);
5705 if(invert){
5706 nottaken=(int)out;
5707 emit_jne(1);
5708 }else{
5709 add_to_linker((int)out,ba[i],internal);
5710 emit_jeq(0);
5711 }
5712 }
5713 if(opcode[i]==5) // BNE
5714 {
5715 if(s2l>=0) emit_cmp(s1l,s2l);
5716 else emit_test(s1l,s1l);
5717 if(invert){
5718 nottaken=(int)out;
5719 emit_jeq(1);
5720 }else{
5721 add_to_linker((int)out,ba[i],internal);
5722 emit_jne(0);
5723 }
5724 }
5725 if(opcode[i]==6) // BLEZ
5726 {
5727 emit_cmpimm(s1l,1);
5728 if(invert){
5729 nottaken=(int)out;
5730 emit_jge(1);
5731 }else{
5732 add_to_linker((int)out,ba[i],internal);
5733 emit_jl(0);
5734 }
5735 }
5736 if(opcode[i]==7) // BGTZ
5737 {
5738 emit_cmpimm(s1l,1);
5739 if(invert){
5740 nottaken=(int)out;
5741 emit_jl(1);
5742 }else{
5743 add_to_linker((int)out,ba[i],internal);
5744 emit_jge(0);
5745 }
5746 }
5747 if(invert) {
5748 if(taken) set_jump_target(taken,(int)out);
5749 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5750 if(match&&(!internal||!is_ds[(ba[i]-start)>>2])) {
5751 if(adj) {
2573466a 5752 emit_addimm(cc,-CLOCK_ADJUST(adj),cc);
57871462 5753 add_to_linker((int)out,ba[i],internal);
5754 }else{
5755 emit_addnop(13);
5756 add_to_linker((int)out,ba[i],internal*2);
5757 }
5758 emit_jmp(0);
5759 }else
5760 #endif
5761 {
2573466a 5762 if(adj) emit_addimm(cc,-CLOCK_ADJUST(adj),cc);
57871462 5763 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5764 load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5765 if(internal)
5766 assem_debug("branch: internal\n");
5767 else
5768 assem_debug("branch: external\n");
5769 if(internal&&is_ds[(ba[i]-start)>>2]) {
5770 ds_assemble_entry(i);
5771 }
5772 else {
5773 add_to_linker((int)out,ba[i],internal);
5774 emit_jmp(0);
5775 }
5776 }
5777 set_jump_target(nottaken,(int)out);
5778 }
5779
5780 if(nottaken1) set_jump_target(nottaken1,(int)out);
5781 if(adj) {
2573466a 5782 if(!invert) emit_addimm(cc,CLOCK_ADJUST(adj),cc);
57871462 5783 }
5784 } // (!unconditional)
5785 } // if(ooo)
5786 else
5787 {
5788 // In-order execution (branch first)
5789 //if(likely[i]) printf("IOL\n");
5790 //else
5791 //printf("IOE\n");
5792 int taken=0,nottaken=0,nottaken1=0;
5793 if(!unconditional&&!nop) {
5794 if(!only32)
5795 {
5796 assert(s1h>=0);
5797 if((opcode[i]&0x2f)==4) // BEQ
5798 {
5799 if(s2h>=0) emit_cmp(s1h,s2h);
5800 else emit_test(s1h,s1h);
5801 nottaken1=(int)out;
5802 emit_jne(2);
5803 }
5804 if((opcode[i]&0x2f)==5) // BNE
5805 {
5806 if(s2h>=0) emit_cmp(s1h,s2h);
5807 else emit_test(s1h,s1h);
5808 taken=(int)out;
5809 emit_jne(1);
5810 }
5811 if((opcode[i]&0x2f)==6) // BLEZ
5812 {
5813 emit_test(s1h,s1h);
5814 taken=(int)out;
5815 emit_js(1);
5816 nottaken1=(int)out;
5817 emit_jne(2);
5818 }
5819 if((opcode[i]&0x2f)==7) // BGTZ
5820 {
5821 emit_test(s1h,s1h);
5822 nottaken1=(int)out;
5823 emit_js(2);
5824 taken=(int)out;
5825 emit_jne(1);
5826 }
5827 } // if(!only32)
5828
5829 //printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5830 assert(s1l>=0);
5831 if((opcode[i]&0x2f)==4) // BEQ
5832 {
5833 if(s2l>=0) emit_cmp(s1l,s2l);
5834 else emit_test(s1l,s1l);
5835 nottaken=(int)out;
5836 emit_jne(2);
5837 }
5838 if((opcode[i]&0x2f)==5) // BNE
5839 {
5840 if(s2l>=0) emit_cmp(s1l,s2l);
5841 else emit_test(s1l,s1l);
5842 nottaken=(int)out;
5843 emit_jeq(2);
5844 }
5845 if((opcode[i]&0x2f)==6) // BLEZ
5846 {
5847 emit_cmpimm(s1l,1);
5848 nottaken=(int)out;
5849 emit_jge(2);
5850 }
5851 if((opcode[i]&0x2f)==7) // BGTZ
5852 {
5853 emit_cmpimm(s1l,1);
5854 nottaken=(int)out;
5855 emit_jl(2);
5856 }
5857 } // if(!unconditional)
5858 int adj;
5859 uint64_t ds_unneeded=branch_regs[i].u;
5860 uint64_t ds_unneeded_upper=branch_regs[i].uu;
5861 ds_unneeded&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
5862 ds_unneeded_upper&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
5863 if((~ds_unneeded_upper>>rt1[i+1])&1) ds_unneeded_upper&=~((1LL<<dep1[i+1])|(1LL<<dep2[i+1]));
5864 ds_unneeded|=1;
5865 ds_unneeded_upper|=1;
5866 // branch taken
5867 if(!nop) {
5868 if(taken) set_jump_target(taken,(int)out);
5869 assem_debug("1:\n");
5870 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5871 ds_unneeded,ds_unneeded_upper);
5872 // load regs
5873 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
5874 address_generation(i+1,&branch_regs[i],0);
5875 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,INVCP);
5876 ds_assemble(i+1,&branch_regs[i]);
5877 cc=get_reg(branch_regs[i].regmap,CCREG);
5878 if(cc==-1) {
5879 emit_loadreg(CCREG,cc=HOST_CCREG);
5880 // CHECK: Is the following instruction (fall thru) allocated ok?
5881 }
5882 assert(cc==HOST_CCREG);
5883 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5884 do_cc(i,i_regmap,&adj,ba[i],TAKEN,0);
5885 assem_debug("cycle count (adj)\n");
2573466a 5886 if(adj) emit_addimm(cc,CLOCK_ADJUST(ccadj[i]+2-adj),cc);
57871462 5887 load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5888 if(internal)
5889 assem_debug("branch: internal\n");
5890 else
5891 assem_debug("branch: external\n");
5892 if(internal&&is_ds[(ba[i]-start)>>2]) {
5893 ds_assemble_entry(i);
5894 }
5895 else {
5896 add_to_linker((int)out,ba[i],internal);
5897 emit_jmp(0);
5898 }
5899 }
5900 // branch not taken
5901 cop1_usable=prev_cop1_usable;
5902 if(!unconditional) {
5903 if(nottaken1) set_jump_target(nottaken1,(int)out);
5904 set_jump_target(nottaken,(int)out);
5905 assem_debug("2:\n");
5906 if(!likely[i]) {
5907 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5908 ds_unneeded,ds_unneeded_upper);
5909 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
5910 address_generation(i+1,&branch_regs[i],0);
5911 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
5912 ds_assemble(i+1,&branch_regs[i]);
5913 }
5914 cc=get_reg(branch_regs[i].regmap,CCREG);
5915 if(cc==-1&&!likely[i]) {
5916 // Cycle count isn't in a register, temporarily load it then write it out
5917 emit_loadreg(CCREG,HOST_CCREG);
2573466a 5918 emit_addimm_and_set_flags(CLOCK_ADJUST(ccadj[i]+2),HOST_CCREG);
57871462 5919 int jaddr=(int)out;
5920 emit_jns(0);
5921 add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,NOTTAKEN,0);
5922 emit_storereg(CCREG,HOST_CCREG);
5923 }
5924 else{
5925 cc=get_reg(i_regmap,CCREG);
5926 assert(cc==HOST_CCREG);
2573466a 5927 emit_addimm_and_set_flags(CLOCK_ADJUST(ccadj[i]+2),cc);
57871462 5928 int jaddr=(int)out;
5929 emit_jns(0);
5930 add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,likely[i]?NULLDS:NOTTAKEN,0);
5931 }
5932 }
5933 }
5934}
5935
5936void sjump_assemble(int i,struct regstat *i_regs)
5937{
5938 signed char *i_regmap=i_regs->regmap;
5939 int cc;
5940 int match;
5941 match=match_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5942 assem_debug("smatch=%d\n",match);
5943 int s1h,s1l;
5944 int prev_cop1_usable=cop1_usable;
5945 int unconditional=0,nevertaken=0;
5946 int only32=0;
57871462 5947 int invert=0;
5948 int internal=internal_branch(branch_regs[i].is32,ba[i]);
5949 if(i==(ba[i]-start)>>2) assem_debug("idle loop\n");
57871462 5950 if(!match) invert=1;
5951 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5952 if(i>(ba[i]-start)>>2) invert=1;
5953 #endif
5954
5955 //if(opcode2[i]>=0x10) return; // FIXME (BxxZAL)
df894a3a 5956 //assert(opcode2[i]<0x10||rs1[i]==0); // FIXME (BxxZAL)
57871462 5957
e1190b87 5958 if(ooo[i]) {
57871462 5959 s1l=get_reg(branch_regs[i].regmap,rs1[i]);
5960 s1h=get_reg(branch_regs[i].regmap,rs1[i]|64);
5961 }
5962 else {
5963 s1l=get_reg(i_regmap,rs1[i]);
5964 s1h=get_reg(i_regmap,rs1[i]|64);
5965 }
5966 if(rs1[i]==0)
5967 {
5968 if(opcode2[i]&1) unconditional=1;
5969 else nevertaken=1;
5970 // These are never taken (r0 is never less than zero)
5971 //assert(opcode2[i]!=0);
5972 //assert(opcode2[i]!=2);
5973 //assert(opcode2[i]!=0x10);
5974 //assert(opcode2[i]!=0x12);
5975 }
5976 else {
5977 only32=(regs[i].was32>>rs1[i])&1;
5978 }
5979
e1190b87 5980 if(ooo[i]) {
57871462 5981 // Out of order execution (delay slot first)
5982 //printf("OOOE\n");
5983 address_generation(i+1,i_regs,regs[i].regmap_entry);
5984 ds_assemble(i+1,i_regs);
5985 int adj;
5986 uint64_t bc_unneeded=branch_regs[i].u;
5987 uint64_t bc_unneeded_upper=branch_regs[i].uu;
5988 bc_unneeded&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
5989 bc_unneeded_upper&=~((1LL<<us1[i])|(1LL<<us2[i]));
5990 bc_unneeded|=1;
5991 bc_unneeded_upper|=1;
5992 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5993 bc_unneeded,bc_unneeded_upper);
5994 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i],rs1[i]);
5995 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
5996 if(rt1[i]==31) {
5997 int rt,return_address;
57871462 5998 rt=get_reg(branch_regs[i].regmap,31);
5999 assem_debug("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
6000 if(rt>=0) {
6001 // Save the PC even if the branch is not taken
6002 return_address=start+i*4+8;
6003 emit_movimm(return_address,rt); // PC into link register
6004 #ifdef IMM_PREFETCH
6005 if(!nevertaken) emit_prefetch(hash_table[((return_address>>16)^return_address)&0xFFFF]);
6006 #endif
6007 }
6008 }
6009 cc=get_reg(branch_regs[i].regmap,CCREG);
6010 assert(cc==HOST_CCREG);
6011 if(unconditional)
6012 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6013 //do_cc(i,branch_regs[i].regmap,&adj,unconditional?ba[i]:-1,unconditional);
6014 assem_debug("cycle count (adj)\n");
6015 if(unconditional) {
6016 do_cc(i,branch_regs[i].regmap,&adj,ba[i],TAKEN,0);
6017 if(i!=(ba[i]-start)>>2 || source[i+1]!=0) {
2573466a 6018 if(adj) emit_addimm(cc,CLOCK_ADJUST(ccadj[i]+2-adj),cc);
57871462 6019 load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6020 if(internal)
6021 assem_debug("branch: internal\n");
6022 else
6023 assem_debug("branch: external\n");
6024 if(internal&&is_ds[(ba[i]-start)>>2]) {
6025 ds_assemble_entry(i);
6026 }
6027 else {
6028 add_to_linker((int)out,ba[i],internal);
6029 emit_jmp(0);
6030 }
6031 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
6032 if(((u_int)out)&7) emit_addnop(0);
6033 #endif
6034 }
6035 }
6036 else if(nevertaken) {
2573466a 6037 emit_addimm_and_set_flags(CLOCK_ADJUST(ccadj[i]+2),cc);
57871462 6038 int jaddr=(int)out;
6039 emit_jns(0);
6040 add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,NOTTAKEN,0);
6041 }
6042 else {
6043 int nottaken=0;
6044 do_cc(i,branch_regs[i].regmap,&adj,-1,0,invert);
2573466a 6045 if(adj&&!invert) emit_addimm(cc,CLOCK_ADJUST(ccadj[i]+2-adj),cc);
57871462 6046 if(!only32)
6047 {
6048 assert(s1h>=0);
df894a3a 6049 if((opcode2[i]&0xf)==0) // BLTZ/BLTZAL
57871462 6050 {
6051 emit_test(s1h,s1h);
6052 if(invert){
6053 nottaken=(int)out;
6054 emit_jns(1);
6055 }else{
6056 add_to_linker((int)out,ba[i],internal);
6057 emit_js(0);
6058 }
6059 }
df894a3a 6060 if((opcode2[i]&0xf)==1) // BGEZ/BLTZAL
57871462 6061 {
6062 emit_test(s1h,s1h);
6063 if(invert){
6064 nottaken=(int)out;
6065 emit_js(1);
6066 }else{
6067 add_to_linker((int)out,ba[i],internal);
6068 emit_jns(0);
6069 }
6070 }
6071 } // if(!only32)
6072 else
6073 {
6074 assert(s1l>=0);
df894a3a 6075 if((opcode2[i]&0xf)==0) // BLTZ/BLTZAL
57871462 6076 {
6077 emit_test(s1l,s1l);
6078 if(invert){
6079 nottaken=(int)out;
6080 emit_jns(1);
6081 }else{
6082 add_to_linker((int)out,ba[i],internal);
6083 emit_js(0);
6084 }
6085 }
df894a3a 6086 if((opcode2[i]&0xf)==1) // BGEZ/BLTZAL
57871462 6087 {
6088 emit_test(s1l,s1l);
6089 if(invert){
6090 nottaken=(int)out;
6091 emit_js(1);
6092 }else{
6093 add_to_linker((int)out,ba[i],internal);
6094 emit_jns(0);
6095 }
6096 }
6097 } // if(!only32)
6098
6099 if(invert) {
6100 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
6101 if(match&&(!internal||!is_ds[(ba[i]-start)>>2])) {
6102 if(adj) {
2573466a 6103 emit_addimm(cc,-CLOCK_ADJUST(adj),cc);
57871462 6104 add_to_linker((int)out,ba[i],internal);
6105 }else{
6106 emit_addnop(13);
6107 add_to_linker((int)out,ba[i],internal*2);
6108 }
6109 emit_jmp(0);
6110 }else
6111 #endif
6112 {
2573466a 6113 if(adj) emit_addimm(cc,-CLOCK_ADJUST(adj),cc);
57871462 6114 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6115 load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6116 if(internal)
6117 assem_debug("branch: internal\n");
6118 else
6119 assem_debug("branch: external\n");
6120 if(internal&&is_ds[(ba[i]-start)>>2]) {
6121 ds_assemble_entry(i);
6122 }
6123 else {
6124 add_to_linker((int)out,ba[i],internal);
6125 emit_jmp(0);
6126 }
6127 }
6128 set_jump_target(nottaken,(int)out);
6129 }
6130
6131 if(adj) {
2573466a 6132 if(!invert) emit_addimm(cc,CLOCK_ADJUST(adj),cc);
57871462 6133 }
6134 } // (!unconditional)
6135 } // if(ooo)
6136 else
6137 {
6138 // In-order execution (branch first)
6139 //printf("IOE\n");
6140 int nottaken=0;
a6491170 6141 if(rt1[i]==31) {
6142 int rt,return_address;
a6491170 6143 rt=get_reg(branch_regs[i].regmap,31);
6144 if(rt>=0) {
6145 // Save the PC even if the branch is not taken
6146 return_address=start+i*4+8;
6147 emit_movimm(return_address,rt); // PC into link register
6148 #ifdef IMM_PREFETCH
6149 emit_prefetch(hash_table[((return_address>>16)^return_address)&0xFFFF]);
6150 #endif
6151 }
6152 }
57871462 6153 if(!unconditional) {
6154 //printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
6155 if(!only32)
6156 {
6157 assert(s1h>=0);
a6491170 6158 if((opcode2[i]&0x0d)==0) // BLTZ/BLTZL/BLTZAL/BLTZALL
57871462 6159 {
6160 emit_test(s1h,s1h);
6161 nottaken=(int)out;
6162 emit_jns(1);
6163 }
a6491170 6164 if((opcode2[i]&0x0d)==1) // BGEZ/BGEZL/BGEZAL/BGEZALL
57871462 6165 {
6166 emit_test(s1h,s1h);
6167 nottaken=(int)out;
6168 emit_js(1);
6169 }
6170 } // if(!only32)
6171 else
6172 {
6173 assert(s1l>=0);
a6491170 6174 if((opcode2[i]&0x0d)==0) // BLTZ/BLTZL/BLTZAL/BLTZALL
57871462 6175 {
6176 emit_test(s1l,s1l);
6177 nottaken=(int)out;
6178 emit_jns(1);
6179 }
a6491170 6180 if((opcode2[i]&0x0d)==1) // BGEZ/BGEZL/BGEZAL/BGEZALL
57871462 6181 {
6182 emit_test(s1l,s1l);
6183 nottaken=(int)out;
6184 emit_js(1);
6185 }
6186 }
6187 } // if(!unconditional)
6188 int adj;
6189 uint64_t ds_unneeded=branch_regs[i].u;
6190 uint64_t ds_unneeded_upper=branch_regs[i].uu;
6191 ds_unneeded&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
6192 ds_unneeded_upper&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
6193 if((~ds_unneeded_upper>>rt1[i+1])&1) ds_unneeded_upper&=~((1LL<<dep1[i+1])|(1LL<<dep2[i+1]));
6194 ds_unneeded|=1;
6195 ds_unneeded_upper|=1;
6196 // branch taken
6197 if(!nevertaken) {
6198 //assem_debug("1:\n");
6199 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
6200 ds_unneeded,ds_unneeded_upper);
6201 // load regs
6202 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
6203 address_generation(i+1,&branch_regs[i],0);
6204 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,INVCP);
6205 ds_assemble(i+1,&branch_regs[i]);
6206 cc=get_reg(branch_regs[i].regmap,CCREG);
6207 if(cc==-1) {
6208 emit_loadreg(CCREG,cc=HOST_CCREG);
6209 // CHECK: Is the following instruction (fall thru) allocated ok?
6210 }
6211 assert(cc==HOST_CCREG);
6212 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6213 do_cc(i,i_regmap,&adj,ba[i],TAKEN,0);
6214 assem_debug("cycle count (adj)\n");
2573466a 6215 if(adj) emit_addimm(cc,CLOCK_ADJUST(ccadj[i]+2-adj),cc);
57871462 6216 load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6217 if(internal)
6218 assem_debug("branch: internal\n");
6219 else
6220 assem_debug("branch: external\n");
6221 if(internal&&is_ds[(ba[i]-start)>>2]) {
6222 ds_assemble_entry(i);
6223 }
6224 else {
6225 add_to_linker((int)out,ba[i],internal);
6226 emit_jmp(0);
6227 }
6228 }
6229 // branch not taken
6230 cop1_usable=prev_cop1_usable;
6231 if(!unconditional) {
6232 set_jump_target(nottaken,(int)out);
6233 assem_debug("1:\n");
6234 if(!likely[i]) {
6235 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
6236 ds_unneeded,ds_unneeded_upper);
6237 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
6238 address_generation(i+1,&branch_regs[i],0);
6239 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
6240 ds_assemble(i+1,&branch_regs[i]);
6241 }
6242 cc=get_reg(branch_regs[i].regmap,CCREG);
6243 if(cc==-1&&!likely[i]) {
6244 // Cycle count isn't in a register, temporarily load it then write it out
6245 emit_loadreg(CCREG,HOST_CCREG);
2573466a 6246 emit_addimm_and_set_flags(CLOCK_ADJUST(ccadj[i]+2),HOST_CCREG);
57871462 6247 int jaddr=(int)out;
6248 emit_jns(0);
6249 add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,NOTTAKEN,0);
6250 emit_storereg(CCREG,HOST_CCREG);
6251 }
6252 else{
6253 cc=get_reg(i_regmap,CCREG);
6254 assert(cc==HOST_CCREG);
2573466a 6255 emit_addimm_and_set_flags(CLOCK_ADJUST(ccadj[i]+2),cc);
57871462 6256 int jaddr=(int)out;
6257 emit_jns(0);
6258 add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,likely[i]?NULLDS:NOTTAKEN,0);
6259 }
6260 }
6261 }
6262}
6263
6264void fjump_assemble(int i,struct regstat *i_regs)
6265{
6266 signed char *i_regmap=i_regs->regmap;
6267 int cc;
6268 int match;
6269 match=match_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6270 assem_debug("fmatch=%d\n",match);
6271 int fs,cs;
6272 int eaddr;
57871462 6273 int invert=0;
6274 int internal=internal_branch(branch_regs[i].is32,ba[i]);
6275 if(i==(ba[i]-start)>>2) assem_debug("idle loop\n");
57871462 6276 if(!match) invert=1;
6277 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
6278 if(i>(ba[i]-start)>>2) invert=1;
6279 #endif
6280
e1190b87 6281 if(ooo[i]) {
57871462 6282 fs=get_reg(branch_regs[i].regmap,FSREG);
6283 address_generation(i+1,i_regs,regs[i].regmap_entry); // Is this okay?
6284 }
6285 else {
6286 fs=get_reg(i_regmap,FSREG);
6287 }
6288
6289 // Check cop1 unusable
6290 if(!cop1_usable) {
6291 cs=get_reg(i_regmap,CSREG);
6292 assert(cs>=0);
6293 emit_testimm(cs,0x20000000);
6294 eaddr=(int)out;
6295 emit_jeq(0);
6296 add_stub(FP_STUB,eaddr,(int)out,i,cs,(int)i_regs,0,0);
6297 cop1_usable=1;
6298 }
6299
e1190b87 6300 if(ooo[i]) {
57871462 6301 // Out of order execution (delay slot first)
6302 //printf("OOOE\n");
6303 ds_assemble(i+1,i_regs);
6304 int adj;
6305 uint64_t bc_unneeded=branch_regs[i].u;
6306 uint64_t bc_unneeded_upper=branch_regs[i].uu;
6307 bc_unneeded&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
6308 bc_unneeded_upper&=~((1LL<<us1[i])|(1LL<<us2[i]));
6309 bc_unneeded|=1;
6310 bc_unneeded_upper|=1;
6311 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
6312 bc_unneeded,bc_unneeded_upper);
6313 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i],rs1[i]);
6314 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
6315 cc=get_reg(branch_regs[i].regmap,CCREG);
6316 assert(cc==HOST_CCREG);
6317 do_cc(i,branch_regs[i].regmap,&adj,-1,0,invert);
6318 assem_debug("cycle count (adj)\n");
6319 if(1) {
6320 int nottaken=0;
2573466a 6321 if(adj&&!invert) emit_addimm(cc,CLOCK_ADJUST(ccadj[i]+2-adj),cc);
57871462 6322 if(1) {
6323 assert(fs>=0);
6324 emit_testimm(fs,0x800000);
6325 if(source[i]&0x10000) // BC1T
6326 {
6327 if(invert){
6328 nottaken=(int)out;
6329 emit_jeq(1);
6330 }else{
6331 add_to_linker((int)out,ba[i],internal);
6332 emit_jne(0);
6333 }
6334 }
6335 else // BC1F
6336 if(invert){
6337 nottaken=(int)out;
6338 emit_jne(1);
6339 }else{
6340 add_to_linker((int)out,ba[i],internal);
6341 emit_jeq(0);
6342 }
6343 {
6344 }
6345 } // if(!only32)
6346
6347 if(invert) {
2573466a 6348 if(adj) emit_addimm(cc,-CLOCK_ADJUST(adj),cc);
57871462 6349 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
6350 else if(match) emit_addnop(13);
6351 #endif
6352 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6353 load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6354 if(internal)
6355 assem_debug("branch: internal\n");
6356 else
6357 assem_debug("branch: external\n");
6358 if(internal&&is_ds[(ba[i]-start)>>2]) {
6359 ds_assemble_entry(i);
6360 }
6361 else {
6362 add_to_linker((int)out,ba[i],internal);
6363 emit_jmp(0);
6364 }
6365 set_jump_target(nottaken,(int)out);
6366 }
6367
6368 if(adj) {
2573466a 6369 if(!invert) emit_addimm(cc,CLOCK_ADJUST(adj),cc);
57871462 6370 }
6371 } // (!unconditional)
6372 } // if(ooo)
6373 else
6374 {
6375 // In-order execution (branch first)
6376 //printf("IOE\n");
6377 int nottaken=0;
6378 if(1) {
6379 //printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
6380 if(1) {
6381 assert(fs>=0);
6382 emit_testimm(fs,0x800000);
6383 if(source[i]&0x10000) // BC1T
6384 {
6385 nottaken=(int)out;
6386 emit_jeq(1);
6387 }
6388 else // BC1F
6389 {
6390 nottaken=(int)out;
6391 emit_jne(1);
6392 }
6393 }
6394 } // if(!unconditional)
6395 int adj;
6396 uint64_t ds_unneeded=branch_regs[i].u;
6397 uint64_t ds_unneeded_upper=branch_regs[i].uu;
6398 ds_unneeded&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
6399 ds_unneeded_upper&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
6400 if((~ds_unneeded_upper>>rt1[i+1])&1) ds_unneeded_upper&=~((1LL<<dep1[i+1])|(1LL<<dep2[i+1]));
6401 ds_unneeded|=1;
6402 ds_unneeded_upper|=1;
6403 // branch taken
6404 //assem_debug("1:\n");
6405 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
6406 ds_unneeded,ds_unneeded_upper);
6407 // load regs
6408 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
6409 address_generation(i+1,&branch_regs[i],0);
6410 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,INVCP);
6411 ds_assemble(i+1,&branch_regs[i]);
6412 cc=get_reg(branch_regs[i].regmap,CCREG);
6413 if(cc==-1) {
6414 emit_loadreg(CCREG,cc=HOST_CCREG);
6415 // CHECK: Is the following instruction (fall thru) allocated ok?
6416 }
6417 assert(cc==HOST_CCREG);
6418 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6419 do_cc(i,i_regmap,&adj,ba[i],TAKEN,0);
6420 assem_debug("cycle count (adj)\n");
2573466a 6421 if(adj) emit_addimm(cc,CLOCK_ADJUST(ccadj[i]+2-adj),cc);
57871462 6422 load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6423 if(internal)
6424 assem_debug("branch: internal\n");
6425 else
6426 assem_debug("branch: external\n");
6427 if(internal&&is_ds[(ba[i]-start)>>2]) {
6428 ds_assemble_entry(i);
6429 }
6430 else {
6431 add_to_linker((int)out,ba[i],internal);
6432 emit_jmp(0);
6433 }
6434
6435 // branch not taken
6436 if(1) { // <- FIXME (don't need this)
6437 set_jump_target(nottaken,(int)out);
6438 assem_debug("1:\n");
6439 if(!likely[i]) {
6440 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
6441 ds_unneeded,ds_unneeded_upper);
6442 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
6443 address_generation(i+1,&branch_regs[i],0);
6444 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
6445 ds_assemble(i+1,&branch_regs[i]);
6446 }
6447 cc=get_reg(branch_regs[i].regmap,CCREG);
6448 if(cc==-1&&!likely[i]) {
6449 // Cycle count isn't in a register, temporarily load it then write it out
6450 emit_loadreg(CCREG,HOST_CCREG);
2573466a 6451 emit_addimm_and_set_flags(CLOCK_ADJUST(ccadj[i]+2),HOST_CCREG);
57871462 6452 int jaddr=(int)out;
6453 emit_jns(0);
6454 add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,NOTTAKEN,0);
6455 emit_storereg(CCREG,HOST_CCREG);
6456 }
6457 else{
6458 cc=get_reg(i_regmap,CCREG);
6459 assert(cc==HOST_CCREG);
2573466a 6460 emit_addimm_and_set_flags(CLOCK_ADJUST(ccadj[i]+2),cc);
57871462 6461 int jaddr=(int)out;
6462 emit_jns(0);
6463 add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,likely[i]?NULLDS:NOTTAKEN,0);
6464 }
6465 }
6466 }
6467}
6468
6469static void pagespan_assemble(int i,struct regstat *i_regs)
6470{
6471 int s1l=get_reg(i_regs->regmap,rs1[i]);
6472 int s1h=get_reg(i_regs->regmap,rs1[i]|64);
6473 int s2l=get_reg(i_regs->regmap,rs2[i]);
6474 int s2h=get_reg(i_regs->regmap,rs2[i]|64);
6475 void *nt_branch=NULL;
6476 int taken=0;
6477 int nottaken=0;
6478 int unconditional=0;
6479 if(rs1[i]==0)
6480 {
6481 s1l=s2l;s1h=s2h;
6482 s2l=s2h=-1;
6483 }
6484 else if(rs2[i]==0)
6485 {
6486 s2l=s2h=-1;
6487 }
6488 if((i_regs->is32>>rs1[i])&(i_regs->is32>>rs2[i])&1) {
6489 s1h=s2h=-1;
6490 }
6491 int hr=0;
6492 int addr,alt,ntaddr;
6493 if(i_regs->regmap[HOST_BTREG]<0) {addr=HOST_BTREG;}
6494 else {
6495 while(hr<HOST_REGS)
6496 {
6497 if(hr!=EXCLUDE_REG && hr!=HOST_CCREG &&
6498 (i_regs->regmap[hr]&63)!=rs1[i] &&
6499 (i_regs->regmap[hr]&63)!=rs2[i] )
6500 {
6501 addr=hr++;break;
6502 }
6503 hr++;
6504 }
6505 }
6506 while(hr<HOST_REGS)
6507 {
6508 if(hr!=EXCLUDE_REG && hr!=HOST_CCREG && hr!=HOST_BTREG &&
6509 (i_regs->regmap[hr]&63)!=rs1[i] &&
6510 (i_regs->regmap[hr]&63)!=rs2[i] )
6511 {
6512 alt=hr++;break;
6513 }
6514 hr++;
6515 }
6516 if((opcode[i]&0x2E)==6) // BLEZ/BGTZ needs another register
6517 {
6518 while(hr<HOST_REGS)
6519 {
6520 if(hr!=EXCLUDE_REG && hr!=HOST_CCREG && hr!=HOST_BTREG &&
6521 (i_regs->regmap[hr]&63)!=rs1[i] &&
6522 (i_regs->regmap[hr]&63)!=rs2[i] )
6523 {
6524 ntaddr=hr;break;
6525 }
6526 hr++;
6527 }
6528 }
6529 assert(hr<HOST_REGS);
6530 if((opcode[i]&0x2e)==4||opcode[i]==0x11) { // BEQ/BNE/BEQL/BNEL/BC1
6531 load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,CCREG,CCREG);
6532 }
2573466a 6533 emit_addimm(HOST_CCREG,CLOCK_ADJUST(ccadj[i]+2),HOST_CCREG);
57871462 6534 if(opcode[i]==2) // J
6535 {
6536 unconditional=1;
6537 }
6538 if(opcode[i]==3) // JAL
6539 {
6540 // TODO: mini_ht
6541 int rt=get_reg(i_regs->regmap,31);
6542 emit_movimm(start+i*4+8,rt);
6543 unconditional=1;
6544 }
6545 if(opcode[i]==0&&(opcode2[i]&0x3E)==8) // JR/JALR
6546 {
6547 emit_mov(s1l,addr);
6548 if(opcode2[i]==9) // JALR
6549 {
5067f341 6550 int rt=get_reg(i_regs->regmap,rt1[i]);
57871462 6551 emit_movimm(start+i*4+8,rt);
6552 }
6553 }
6554 if((opcode[i]&0x3f)==4) // BEQ
6555 {
6556 if(rs1[i]==rs2[i])
6557 {
6558 unconditional=1;
6559 }
6560 else
6561 #ifdef HAVE_CMOV_IMM
6562 if(s1h<0) {
6563 if(s2l>=0) emit_cmp(s1l,s2l);
6564 else emit_test(s1l,s1l);
6565 emit_cmov2imm_e_ne_compact(ba[i],start+i*4+8,addr);
6566 }
6567 else
6568 #endif
6569 {
6570 assert(s1l>=0);
6571 emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
6572 if(s1h>=0) {
6573 if(s2h>=0) emit_cmp(s1h,s2h);
6574 else emit_test(s1h,s1h);
6575 emit_cmovne_reg(alt,addr);
6576 }
6577 if(s2l>=0) emit_cmp(s1l,s2l);
6578 else emit_test(s1l,s1l);
6579 emit_cmovne_reg(alt,addr);
6580 }
6581 }
6582 if((opcode[i]&0x3f)==5) // BNE
6583 {
6584 #ifdef HAVE_CMOV_IMM
6585 if(s1h<0) {
6586 if(s2l>=0) emit_cmp(s1l,s2l);
6587 else emit_test(s1l,s1l);
6588 emit_cmov2imm_e_ne_compact(start+i*4+8,ba[i],addr);
6589 }
6590 else
6591 #endif
6592 {
6593 assert(s1l>=0);
6594 emit_mov2imm_compact(start+i*4+8,addr,ba[i],alt);
6595 if(s1h>=0) {
6596 if(s2h>=0) emit_cmp(s1h,s2h);
6597 else emit_test(s1h,s1h);
6598 emit_cmovne_reg(alt,addr);
6599 }
6600 if(s2l>=0) emit_cmp(s1l,s2l);
6601 else emit_test(s1l,s1l);
6602 emit_cmovne_reg(alt,addr);
6603 }
6604 }
6605 if((opcode[i]&0x3f)==0x14) // BEQL
6606 {
6607 if(s1h>=0) {
6608 if(s2h>=0) emit_cmp(s1h,s2h);
6609 else emit_test(s1h,s1h);
6610 nottaken=(int)out;
6611 emit_jne(0);
6612 }
6613 if(s2l>=0) emit_cmp(s1l,s2l);
6614 else emit_test(s1l,s1l);
6615 if(nottaken) set_jump_target(nottaken,(int)out);
6616 nottaken=(int)out;
6617 emit_jne(0);
6618 }
6619 if((opcode[i]&0x3f)==0x15) // BNEL
6620 {
6621 if(s1h>=0) {
6622 if(s2h>=0) emit_cmp(s1h,s2h);
6623 else emit_test(s1h,s1h);
6624 taken=(int)out;
6625 emit_jne(0);
6626 }
6627 if(s2l>=0) emit_cmp(s1l,s2l);
6628 else emit_test(s1l,s1l);
6629 nottaken=(int)out;
6630 emit_jeq(0);
6631 if(taken) set_jump_target(taken,(int)out);
6632 }
6633 if((opcode[i]&0x3f)==6) // BLEZ
6634 {
6635 emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
6636 emit_cmpimm(s1l,1);
6637 if(s1h>=0) emit_mov(addr,ntaddr);
6638 emit_cmovl_reg(alt,addr);
6639 if(s1h>=0) {
6640 emit_test(s1h,s1h);
6641 emit_cmovne_reg(ntaddr,addr);
6642 emit_cmovs_reg(alt,addr);
6643 }
6644 }
6645 if((opcode[i]&0x3f)==7) // BGTZ
6646 {
6647 emit_mov2imm_compact(ba[i],addr,start+i*4+8,ntaddr);
6648 emit_cmpimm(s1l,1);
6649 if(s1h>=0) emit_mov(addr,alt);
6650 emit_cmovl_reg(ntaddr,addr);
6651 if(s1h>=0) {
6652 emit_test(s1h,s1h);
6653 emit_cmovne_reg(alt,addr);
6654 emit_cmovs_reg(ntaddr,addr);
6655 }
6656 }
6657 if((opcode[i]&0x3f)==0x16) // BLEZL
6658 {
6659 assert((opcode[i]&0x3f)!=0x16);
6660 }
6661 if((opcode[i]&0x3f)==0x17) // BGTZL
6662 {
6663 assert((opcode[i]&0x3f)!=0x17);
6664 }
6665 assert(opcode[i]!=1); // BLTZ/BGEZ
6666
6667 //FIXME: Check CSREG
6668 if(opcode[i]==0x11 && opcode2[i]==0x08 ) {
6669 if((source[i]&0x30000)==0) // BC1F
6670 {
6671 emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
6672 emit_testimm(s1l,0x800000);
6673 emit_cmovne_reg(alt,addr);
6674 }
6675 if((source[i]&0x30000)==0x10000) // BC1T
6676 {
6677 emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
6678 emit_testimm(s1l,0x800000);
6679 emit_cmovne_reg(alt,addr);
6680 }
6681 if((source[i]&0x30000)==0x20000) // BC1FL
6682 {
6683 emit_testimm(s1l,0x800000);
6684 nottaken=(int)out;
6685 emit_jne(0);
6686 }
6687 if((source[i]&0x30000)==0x30000) // BC1TL
6688 {
6689 emit_testimm(s1l,0x800000);
6690 nottaken=(int)out;
6691 emit_jeq(0);
6692 }
6693 }
6694
6695 assert(i_regs->regmap[HOST_CCREG]==CCREG);
6696 wb_dirtys(regs[i].regmap,regs[i].is32,regs[i].dirty);
6697 if(likely[i]||unconditional)
6698 {
6699 emit_movimm(ba[i],HOST_BTREG);
6700 }
6701 else if(addr!=HOST_BTREG)
6702 {
6703 emit_mov(addr,HOST_BTREG);
6704 }
6705 void *branch_addr=out;
6706 emit_jmp(0);
6707 int target_addr=start+i*4+5;
6708 void *stub=out;
6709 void *compiled_target_addr=check_addr(target_addr);
6710 emit_extjump_ds((int)branch_addr,target_addr);
6711 if(compiled_target_addr) {
6712 set_jump_target((int)branch_addr,(int)compiled_target_addr);
6713 add_link(target_addr,stub);
6714 }
6715 else set_jump_target((int)branch_addr,(int)stub);
6716 if(likely[i]) {
6717 // Not-taken path
6718 set_jump_target((int)nottaken,(int)out);
6719 wb_dirtys(regs[i].regmap,regs[i].is32,regs[i].dirty);
6720 void *branch_addr=out;
6721 emit_jmp(0);
6722 int target_addr=start+i*4+8;
6723 void *stub=out;
6724 void *compiled_target_addr=check_addr(target_addr);
6725 emit_extjump_ds((int)branch_addr,target_addr);
6726 if(compiled_target_addr) {
6727 set_jump_target((int)branch_addr,(int)compiled_target_addr);
6728 add_link(target_addr,stub);
6729 }
6730 else set_jump_target((int)branch_addr,(int)stub);
6731 }
6732}
6733
6734// Assemble the delay slot for the above
6735static void pagespan_ds()
6736{
6737 assem_debug("initial delay slot:\n");
6738 u_int vaddr=start+1;
94d23bb9 6739 u_int page=get_page(vaddr);
6740 u_int vpage=get_vpage(vaddr);
57871462 6741 ll_add(jump_dirty+vpage,vaddr,(void *)out);
6742 do_dirty_stub_ds();
6743 ll_add(jump_in+page,vaddr,(void *)out);
6744 assert(regs[0].regmap_entry[HOST_CCREG]==CCREG);
6745 if(regs[0].regmap[HOST_CCREG]!=CCREG)
6746 wb_register(CCREG,regs[0].regmap_entry,regs[0].wasdirty,regs[0].was32);
6747 if(regs[0].regmap[HOST_BTREG]!=BTREG)
6748 emit_writeword(HOST_BTREG,(int)&branch_target);
6749 load_regs(regs[0].regmap_entry,regs[0].regmap,regs[0].was32,rs1[0],rs2[0]);
6750 address_generation(0,&regs[0],regs[0].regmap_entry);
b9b61529 6751 if(itype[0]==STORE||itype[0]==STORELR||(opcode[0]&0x3b)==0x39||(opcode[0]&0x3b)==0x3a)
57871462 6752 load_regs(regs[0].regmap_entry,regs[0].regmap,regs[0].was32,INVCP,INVCP);
6753 cop1_usable=0;
6754 is_delayslot=0;
6755 switch(itype[0]) {
6756 case ALU:
6757 alu_assemble(0,&regs[0]);break;
6758 case IMM16:
6759 imm16_assemble(0,&regs[0]);break;
6760 case SHIFT:
6761 shift_assemble(0,&regs[0]);break;
6762 case SHIFTIMM:
6763 shiftimm_assemble(0,&regs[0]);break;
6764 case LOAD:
6765 load_assemble(0,&regs[0]);break;
6766 case LOADLR:
6767 loadlr_assemble(0,&regs[0]);break;
6768 case STORE:
6769 store_assemble(0,&regs[0]);break;
6770 case STORELR:
6771 storelr_assemble(0,&regs[0]);break;
6772 case COP0:
6773 cop0_assemble(0,&regs[0]);break;
6774 case COP1:
6775 cop1_assemble(0,&regs[0]);break;
6776 case C1LS:
6777 c1ls_assemble(0,&regs[0]);break;
b9b61529 6778 case COP2:
6779 cop2_assemble(0,&regs[0]);break;
6780 case C2LS:
6781 c2ls_assemble(0,&regs[0]);break;
6782 case C2OP:
6783 c2op_assemble(0,&regs[0]);break;
57871462 6784 case FCONV:
6785 fconv_assemble(0,&regs[0]);break;
6786 case FLOAT:
6787 float_assemble(0,&regs[0]);break;
6788 case FCOMP:
6789 fcomp_assemble(0,&regs[0]);break;
6790 case MULTDIV:
6791 multdiv_assemble(0,&regs[0]);break;
6792 case MOV:
6793 mov_assemble(0,&regs[0]);break;
6794 case SYSCALL:
7139f3c8 6795 case HLECALL:
1e973cb0 6796 case INTCALL:
57871462 6797 case SPAN:
6798 case UJUMP:
6799 case RJUMP:
6800 case CJUMP:
6801 case SJUMP:
6802 case FJUMP:
6803 printf("Jump in the delay slot. This is probably a bug.\n");
6804 }
6805 int btaddr=get_reg(regs[0].regmap,BTREG);
6806 if(btaddr<0) {
6807 btaddr=get_reg(regs[0].regmap,-1);
6808 emit_readword((int)&branch_target,btaddr);
6809 }
6810 assert(btaddr!=HOST_CCREG);
6811 if(regs[0].regmap[HOST_CCREG]!=CCREG) emit_loadreg(CCREG,HOST_CCREG);
6812#ifdef HOST_IMM8
6813 emit_movimm(start+4,HOST_TEMPREG);
6814 emit_cmp(btaddr,HOST_TEMPREG);
6815#else
6816 emit_cmpimm(btaddr,start+4);
6817#endif
6818 int branch=(int)out;
6819 emit_jeq(0);
6820 store_regs_bt(regs[0].regmap,regs[0].is32,regs[0].dirty,-1);
6821 emit_jmp(jump_vaddr_reg[btaddr]);
6822 set_jump_target(branch,(int)out);
6823 store_regs_bt(regs[0].regmap,regs[0].is32,regs[0].dirty,start+4);
6824 load_regs_bt(regs[0].regmap,regs[0].is32,regs[0].dirty,start+4);
6825}
6826
6827// Basic liveness analysis for MIPS registers
6828void unneeded_registers(int istart,int iend,int r)
6829{
6830 int i;
bedfea38 6831 uint64_t u,uu,gte_u,b,bu,gte_bu;
0ff8c62c 6832 uint64_t temp_u,temp_uu,temp_gte_u=0;
57871462 6833 uint64_t tdep;
0ff8c62c 6834 uint64_t gte_u_unknown=0;
6835 if(new_dynarec_hacks&NDHACK_GTE_UNNEEDED)
6836 gte_u_unknown=~0ll;
57871462 6837 if(iend==slen-1) {
6838 u=1;uu=1;
0ff8c62c 6839 gte_u=gte_u_unknown;
57871462 6840 }else{
6841 u=unneeded_reg[iend+1];
6842 uu=unneeded_reg_upper[iend+1];
6843 u=1;uu=1;
0ff8c62c 6844 gte_u=gte_unneeded[iend+1];
57871462 6845 }
bedfea38 6846
57871462 6847 for (i=iend;i>=istart;i--)
6848 {
6849 //printf("unneeded registers i=%d (%d,%d) r=%d\n",i,istart,iend,r);
6850 if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
6851 {
6852 // If subroutine call, flag return address as a possible branch target
6853 if(rt1[i]==31 && i<slen-2) bt[i+2]=1;
6854
6855 if(ba[i]<start || ba[i]>=(start+slen*4))
6856 {
6857 // Branch out of this block, flush all regs
6858 u=1;
6859 uu=1;
0ff8c62c 6860 gte_u=gte_u_unknown;
57871462 6861 /* Hexagon hack
6862 if(itype[i]==UJUMP&&rt1[i]==31)
6863 {
6864 uu=u=0x300C00F; // Discard at, v0-v1, t6-t9
6865 }
6866 if(itype[i]==RJUMP&&rs1[i]==31)
6867 {
6868 uu=u=0x300C0F3; // Discard at, a0-a3, t6-t9
6869 }
4cb76aa4 6870 if(start>0x80000400&&start<0x80000000+RAM_SIZE) {
57871462 6871 if(itype[i]==UJUMP&&rt1[i]==31)
6872 {
6873 //uu=u=0x30300FF0FLL; // Discard at, v0-v1, t0-t9, lo, hi
6874 uu=u=0x300FF0F; // Discard at, v0-v1, t0-t9
6875 }
6876 if(itype[i]==RJUMP&&rs1[i]==31)
6877 {
6878 //uu=u=0x30300FFF3LL; // Discard at, a0-a3, t0-t9, lo, hi
6879 uu=u=0x300FFF3; // Discard at, a0-a3, t0-t9
6880 }
6881 }*/
6882 branch_unneeded_reg[i]=u;
6883 branch_unneeded_reg_upper[i]=uu;
6884 // Merge in delay slot
6885 tdep=(~uu>>rt1[i+1])&1;
6886 u|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6887 uu|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6888 u&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
6889 uu&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
6890 uu&=~((tdep<<dep1[i+1])|(tdep<<dep2[i+1]));
6891 u|=1;uu|=1;
bedfea38 6892 gte_u|=gte_rt[i+1];
6893 gte_u&=~gte_rs[i+1];
57871462 6894 // If branch is "likely" (and conditional)
6895 // then we skip the delay slot on the fall-thru path
6896 if(likely[i]) {
6897 if(i<slen-1) {
6898 u&=unneeded_reg[i+2];
6899 uu&=unneeded_reg_upper[i+2];
bedfea38 6900 gte_u&=gte_unneeded[i+2];
57871462 6901 }
6902 else
6903 {
6904 u=1;
6905 uu=1;
0ff8c62c 6906 gte_u=gte_u_unknown;
57871462 6907 }
6908 }
6909 }
6910 else
6911 {
6912 // Internal branch, flag target
6913 bt[(ba[i]-start)>>2]=1;
6914 if(ba[i]<=start+i*4) {
6915 // Backward branch
6916 if(itype[i]==RJUMP||itype[i]==UJUMP||(source[i]>>16)==0x1000)
6917 {
6918 // Unconditional branch
6919 temp_u=1;temp_uu=1;
bedfea38 6920 temp_gte_u=0;
57871462 6921 } else {
6922 // Conditional branch (not taken case)
6923 temp_u=unneeded_reg[i+2];
6924 temp_uu=unneeded_reg_upper[i+2];
bedfea38 6925 temp_gte_u&=gte_unneeded[i+2];
57871462 6926 }
6927 // Merge in delay slot
6928 tdep=(~temp_uu>>rt1[i+1])&1;
6929 temp_u|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6930 temp_uu|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6931 temp_u&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
6932 temp_uu&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
6933 temp_uu&=~((tdep<<dep1[i+1])|(tdep<<dep2[i+1]));
6934 temp_u|=1;temp_uu|=1;
bedfea38 6935 temp_gte_u|=gte_rt[i+1];
6936 temp_gte_u&=~gte_rs[i+1];
57871462 6937 // If branch is "likely" (and conditional)
6938 // then we skip the delay slot on the fall-thru path
6939 if(likely[i]) {
6940 if(i<slen-1) {
6941 temp_u&=unneeded_reg[i+2];
6942 temp_uu&=unneeded_reg_upper[i+2];
bedfea38 6943 temp_gte_u&=gte_unneeded[i+2];
57871462 6944 }
6945 else
6946 {
6947 temp_u=1;
6948 temp_uu=1;
0ff8c62c 6949 temp_gte_u=gte_u_unknown;
57871462 6950 }
6951 }
6952 tdep=(~temp_uu>>rt1[i])&1;
6953 temp_u|=(1LL<<rt1[i])|(1LL<<rt2[i]);
6954 temp_uu|=(1LL<<rt1[i])|(1LL<<rt2[i]);
6955 temp_u&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
6956 temp_uu&=~((1LL<<us1[i])|(1LL<<us2[i]));
6957 temp_uu&=~((tdep<<dep1[i])|(tdep<<dep2[i]));
6958 temp_u|=1;temp_uu|=1;
bedfea38 6959 temp_gte_u|=gte_rt[i];
6960 temp_gte_u&=~gte_rs[i];
57871462 6961 unneeded_reg[i]=temp_u;
6962 unneeded_reg_upper[i]=temp_uu;
bedfea38 6963 gte_unneeded[i]=temp_gte_u;
57871462 6964 // Only go three levels deep. This recursion can take an
6965 // excessive amount of time if there are a lot of nested loops.
6966 if(r<2) {
6967 unneeded_registers((ba[i]-start)>>2,i-1,r+1);
6968 }else{
6969 unneeded_reg[(ba[i]-start)>>2]=1;
6970 unneeded_reg_upper[(ba[i]-start)>>2]=1;
0ff8c62c 6971 gte_unneeded[(ba[i]-start)>>2]=gte_u_unknown;
57871462 6972 }
6973 } /*else*/ if(1) {
6974 if(itype[i]==RJUMP||itype[i]==UJUMP||(source[i]>>16)==0x1000)
6975 {
6976 // Unconditional branch
6977 u=unneeded_reg[(ba[i]-start)>>2];
6978 uu=unneeded_reg_upper[(ba[i]-start)>>2];
bedfea38 6979 gte_u=gte_unneeded[(ba[i]-start)>>2];
57871462 6980 branch_unneeded_reg[i]=u;
6981 branch_unneeded_reg_upper[i]=uu;
6982 //u=1;
6983 //uu=1;
6984 //branch_unneeded_reg[i]=u;
6985 //branch_unneeded_reg_upper[i]=uu;
6986 // Merge in delay slot
6987 tdep=(~uu>>rt1[i+1])&1;
6988 u|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6989 uu|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6990 u&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
6991 uu&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
6992 uu&=~((tdep<<dep1[i+1])|(tdep<<dep2[i+1]));
6993 u|=1;uu|=1;
bedfea38 6994 gte_u|=gte_rt[i+1];
6995 gte_u&=~gte_rs[i+1];
57871462 6996 } else {
6997 // Conditional branch
6998 b=unneeded_reg[(ba[i]-start)>>2];
6999 bu=unneeded_reg_upper[(ba[i]-start)>>2];
bedfea38 7000 gte_bu=gte_unneeded[(ba[i]-start)>>2];
57871462 7001 branch_unneeded_reg[i]=b;
7002 branch_unneeded_reg_upper[i]=bu;
7003 //b=1;
7004 //bu=1;
7005 //branch_unneeded_reg[i]=b;
7006 //branch_unneeded_reg_upper[i]=bu;
7007 // Branch delay slot
7008 tdep=(~uu>>rt1[i+1])&1;
7009 b|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
7010 bu|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
7011 b&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
7012 bu&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
7013 bu&=~((tdep<<dep1[i+1])|(tdep<<dep2[i+1]));
7014 b|=1;bu|=1;
bedfea38 7015 gte_bu|=gte_rt[i+1];
7016 gte_bu&=~gte_rs[i+1];
57871462 7017 // If branch is "likely" then we skip the
7018 // delay slot on the fall-thru path
7019 if(likely[i]) {
7020 u=b;
7021 uu=bu;
bedfea38 7022 gte_u=gte_bu;
57871462 7023 if(i<slen-1) {
7024 u&=unneeded_reg[i+2];
7025 uu&=unneeded_reg_upper[i+2];
bedfea38 7026 gte_u&=gte_unneeded[i+2];
57871462 7027 //u=1;
7028 //uu=1;
7029 }
7030 } else {
7031 u&=b;
7032 uu&=bu;
bedfea38 7033 gte_u&=gte_bu;
57871462 7034 //u=1;
7035 //uu=1;
7036 }
7037 if(i<slen-1) {
7038 branch_unneeded_reg[i]&=unneeded_reg[i+2];
7039 branch_unneeded_reg_upper[i]&=unneeded_reg_upper[i+2];
7040 //branch_unneeded_reg[i]=1;
7041 //branch_unneeded_reg_upper[i]=1;
7042 } else {
7043 branch_unneeded_reg[i]=1;
7044 branch_unneeded_reg_upper[i]=1;
7045 }
7046 }
7047 }
7048 }
7049 }
1e973cb0 7050 else if(itype[i]==SYSCALL||itype[i]==HLECALL||itype[i]==INTCALL)
57871462 7051 {
7052 // SYSCALL instruction (software interrupt)
7053 u=1;
7054 uu=1;
7055 }
7056 else if(itype[i]==COP0 && (source[i]&0x3f)==0x18)
7057 {
7058 // ERET instruction (return from interrupt)
7059 u=1;
7060 uu=1;
7061 }
7062 //u=uu=1; // DEBUG
7063 tdep=(~uu>>rt1[i])&1;
7064 // Written registers are unneeded
7065 u|=1LL<<rt1[i];
7066 u|=1LL<<rt2[i];
7067 uu|=1LL<<rt1[i];
7068 uu|=1LL<<rt2[i];
bedfea38 7069 gte_u|=gte_rt[i];
57871462 7070 // Accessed registers are needed
7071 u&=~(1LL<<rs1[i]);
7072 u&=~(1LL<<rs2[i]);
7073 uu&=~(1LL<<us1[i]);
7074 uu&=~(1LL<<us2[i]);
bedfea38 7075 gte_u&=~gte_rs[i];
eaa11918 7076 if(gte_rs[i]&&rt1[i]&&(unneeded_reg[i+1]&(1ll<<rt1[i])))
cbbd8dd7 7077 gte_u|=gte_rs[i]&gte_unneeded[i+1]; // MFC2/CFC2 to dead register, unneeded
57871462 7078 // Source-target dependencies
7079 uu&=~(tdep<<dep1[i]);
7080 uu&=~(tdep<<dep2[i]);
7081 // R0 is always unneeded
7082 u|=1;uu|=1;
7083 // Save it
7084 unneeded_reg[i]=u;
7085 unneeded_reg_upper[i]=uu;
bedfea38 7086 gte_unneeded[i]=gte_u;
57871462 7087 /*
7088 printf("ur (%d,%d) %x: ",istart,iend,start+i*4);
7089 printf("U:");
7090 int r;
7091 for(r=1;r<=CCREG;r++) {
7092 if((unneeded_reg[i]>>r)&1) {
7093 if(r==HIREG) printf(" HI");
7094 else if(r==LOREG) printf(" LO");
7095 else printf(" r%d",r);
7096 }
7097 }
7098 printf(" UU:");
7099 for(r=1;r<=CCREG;r++) {
7100 if(((unneeded_reg_upper[i]&~unneeded_reg[i])>>r)&1) {
7101 if(r==HIREG) printf(" HI");
7102 else if(r==LOREG) printf(" LO");
7103 else printf(" r%d",r);
7104 }
7105 }
7106 printf("\n");*/
7107 }
252c20fc 7108#ifdef FORCE32
7109 for (i=iend;i>=istart;i--)
7110 {
7111 unneeded_reg_upper[i]=branch_unneeded_reg_upper[i]=-1LL;
7112 }
7113#endif
57871462 7114}
7115
7116// Identify registers which are likely to contain 32-bit values
7117// This is used to predict whether any branches will jump to a
7118// location with 64-bit values in registers.
7119static void provisional_32bit()
7120{
7121 int i,j;
7122 uint64_t is32=1;
7123 uint64_t lastbranch=1;
7124
7125 for(i=0;i<slen;i++)
7126 {
7127 if(i>0) {
7128 if(itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP) {
7129 if(i>1) is32=lastbranch;
7130 else is32=1;
7131 }
7132 }
7133 if(i>1)
7134 {
7135 if(itype[i-2]==CJUMP||itype[i-2]==SJUMP||itype[i-2]==FJUMP) {
7136 if(likely[i-2]) {
7137 if(i>2) is32=lastbranch;
7138 else is32=1;
7139 }
7140 }
7141 if((opcode[i-2]&0x2f)==0x05) // BNE/BNEL
7142 {
7143 if(rs1[i-2]==0||rs2[i-2]==0)
7144 {
7145 if(rs1[i-2]) {
7146 is32|=1LL<<rs1[i-2];
7147 }
7148 if(rs2[i-2]) {
7149 is32|=1LL<<rs2[i-2];
7150 }
7151 }
7152 }
7153 }
7154 // If something jumps here with 64-bit values
7155 // then promote those registers to 64 bits
7156 if(bt[i])
7157 {
7158 uint64_t temp_is32=is32;
7159 for(j=i-1;j>=0;j--)
7160 {
7161 if(ba[j]==start+i*4)
7162 //temp_is32&=branch_regs[j].is32;
7163 temp_is32&=p32[j];
7164 }
7165 for(j=i;j<slen;j++)
7166 {
7167 if(ba[j]==start+i*4)
7168 temp_is32=1;
7169 }
7170 is32=temp_is32;
7171 }
7172 int type=itype[i];
7173 int op=opcode[i];
7174 int op2=opcode2[i];
7175 int rt=rt1[i];
7176 int s1=rs1[i];
7177 int s2=rs2[i];
7178 if(type==UJUMP||type==RJUMP||type==CJUMP||type==SJUMP||type==FJUMP) {
7179 // Branches don't write registers, consider the delay slot instead.
7180 type=itype[i+1];
7181 op=opcode[i+1];
7182 op2=opcode2[i+1];
7183 rt=rt1[i+1];
7184 s1=rs1[i+1];
7185 s2=rs2[i+1];
7186 lastbranch=is32;
7187 }
7188 switch(type) {
7189 case LOAD:
7190 if(opcode[i]==0x27||opcode[i]==0x37|| // LWU/LD
7191 opcode[i]==0x1A||opcode[i]==0x1B) // LDL/LDR
7192 is32&=~(1LL<<rt);
7193 else
7194 is32|=1LL<<rt;
7195 break;
7196 case STORE:
7197 case STORELR:
7198 break;
7199 case LOADLR:
7200 if(op==0x1a||op==0x1b) is32&=~(1LL<<rt); // LDR/LDL
7201 if(op==0x22) is32|=1LL<<rt; // LWL
7202 break;
7203 case IMM16:
7204 if (op==0x08||op==0x09|| // ADDI/ADDIU
7205 op==0x0a||op==0x0b|| // SLTI/SLTIU
7206 op==0x0c|| // ANDI
7207 op==0x0f) // LUI
7208 {
7209 is32|=1LL<<rt;
7210 }
7211 if(op==0x18||op==0x19) { // DADDI/DADDIU
7212 is32&=~(1LL<<rt);
7213 //if(imm[i]==0)
7214 // is32|=((is32>>s1)&1LL)<<rt;
7215 }
7216 if(op==0x0d||op==0x0e) { // ORI/XORI
7217 uint64_t sr=((is32>>s1)&1LL);
7218 is32&=~(1LL<<rt);
7219 is32|=sr<<rt;
7220 }
7221 break;
7222 case UJUMP:
7223 break;
7224 case RJUMP:
7225 break;
7226 case CJUMP:
7227 break;
7228 case SJUMP:
7229 break;
7230 case FJUMP:
7231 break;
7232 case ALU:
7233 if(op2>=0x20&&op2<=0x23) { // ADD/ADDU/SUB/SUBU
7234 is32|=1LL<<rt;
7235 }
7236 if(op2==0x2a||op2==0x2b) { // SLT/SLTU
7237 is32|=1LL<<rt;
7238 }
7239 else if(op2>=0x24&&op2<=0x27) { // AND/OR/XOR/NOR
7240 uint64_t sr=((is32>>s1)&(is32>>s2)&1LL);
7241 is32&=~(1LL<<rt);
7242 is32|=sr<<rt;
7243 }
7244 else if(op2>=0x2c&&op2<=0x2d) { // DADD/DADDU
7245 if(s1==0&&s2==0) {
7246 is32|=1LL<<rt;
7247 }
7248 else if(s2==0) {
7249 uint64_t sr=((is32>>s1)&1LL);
7250 is32&=~(1LL<<rt);
7251 is32|=sr<<rt;
7252 }
7253 else if(s1==0) {
7254 uint64_t sr=((is32>>s2)&1LL);
7255 is32&=~(1LL<<rt);
7256 is32|=sr<<rt;
7257 }
7258 else {
7259 is32&=~(1LL<<rt);
7260 }
7261 }
7262 else if(op2>=0x2e&&op2<=0x2f) { // DSUB/DSUBU
7263 if(s1==0&&s2==0) {
7264 is32|=1LL<<rt;
7265 }
7266 else if(s2==0) {
7267 uint64_t sr=((is32>>s1)&1LL);
7268 is32&=~(1LL<<rt);
7269 is32|=sr<<rt;
7270 }
7271 else {
7272 is32&=~(1LL<<rt);
7273 }
7274 }
7275 break;
7276 case MULTDIV:
7277 if (op2>=0x1c&&op2<=0x1f) { // DMULT/DMULTU/DDIV/DDIVU
7278 is32&=~((1LL<<HIREG)|(1LL<<LOREG));
7279 }
7280 else {
7281 is32|=(1LL<<HIREG)|(1LL<<LOREG);
7282 }
7283 break;
7284 case MOV:
7285 {
7286 uint64_t sr=((is32>>s1)&1LL);
7287 is32&=~(1LL<<rt);
7288 is32|=sr<<rt;
7289 }
7290 break;
7291 case SHIFT:
7292 if(op2>=0x14&&op2<=0x17) is32&=~(1LL<<rt); // DSLLV/DSRLV/DSRAV
7293 else is32|=1LL<<rt; // SLLV/SRLV/SRAV
7294 break;
7295 case SHIFTIMM:
7296 is32|=1LL<<rt;
7297 // DSLL/DSRL/DSRA/DSLL32/DSRL32 but not DSRA32 have 64-bit result
7298 if(op2>=0x38&&op2<0x3f) is32&=~(1LL<<rt);
7299 break;
7300 case COP0:
7301 if(op2==0) is32|=1LL<<rt; // MFC0
7302 break;
7303 case COP1:
b9b61529 7304 case COP2:
57871462 7305 if(op2==0) is32|=1LL<<rt; // MFC1
7306 if(op2==1) is32&=~(1LL<<rt); // DMFC1
7307 if(op2==2) is32|=1LL<<rt; // CFC1
7308 break;
7309 case C1LS:
b9b61529 7310 case C2LS:
57871462 7311 break;
7312 case FLOAT:
7313 case FCONV:
7314 break;
7315 case FCOMP:
7316 break;
b9b61529 7317 case C2OP:
57871462 7318 case SYSCALL:
7139f3c8 7319 case HLECALL:
57871462 7320 break;
7321 default:
7322 break;
7323 }
7324 is32|=1;
7325 p32[i]=is32;
7326
7327 if(i>0)
7328 {
7329 if(itype[i-1]==UJUMP||itype[i-1]==RJUMP||(source[i-1]>>16)==0x1000)
7330 {
7331 if(rt1[i-1]==31) // JAL/JALR
7332 {
7333 // Subroutine call will return here, don't alloc any registers
7334 is32=1;
7335 }
7336 else if(i+1<slen)
7337 {
7338 // Internal branch will jump here, match registers to caller
7339 is32=0x3FFFFFFFFLL;
7340 }
7341 }
7342 }
7343 }
7344}
7345
7346// Identify registers which may be assumed to contain 32-bit values
7347// and where optimizations will rely on this.
7348// This is used to determine whether backward branches can safely
7349// jump to a location with 64-bit values in registers.
7350static void provisional_r32()
7351{
7352 u_int r32=0;
7353 int i;
7354
7355 for (i=slen-1;i>=0;i--)
7356 {
7357 int hr;
7358 if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
7359 {
7360 if(ba[i]<start || ba[i]>=(start+slen*4))
7361 {
7362 // Branch out of this block, don't need anything
7363 r32=0;
7364 }
7365 else
7366 {
7367 // Internal branch
7368 // Need whatever matches the target
7369 // (and doesn't get overwritten by the delay slot instruction)
7370 r32=0;
7371 int t=(ba[i]-start)>>2;
7372 if(ba[i]>start+i*4) {
7373 // Forward branch
7374 //if(!(requires_32bit[t]&~regs[i].was32))
7375 // r32|=requires_32bit[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
7376 if(!(pr32[t]&~regs[i].was32))
7377 r32|=pr32[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
7378 }else{
7379 // Backward branch
7380 if(!(regs[t].was32&~unneeded_reg_upper[t]&~regs[i].was32))
7381 r32|=regs[t].was32&~unneeded_reg_upper[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
7382 }
7383 }
7384 // Conditional branch may need registers for following instructions
7385 if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000)
7386 {
7387 if(i<slen-2) {
7388 //r32|=requires_32bit[i+2];
7389 r32|=pr32[i+2];
7390 r32&=regs[i].was32;
7391 // Mark this address as a branch target since it may be called
7392 // upon return from interrupt
7393 //bt[i+2]=1;
7394 }
7395 }
7396 // Merge in delay slot
7397 if(!likely[i]) {
7398 // These are overwritten unless the branch is "likely"
7399 // and the delay slot is nullified if not taken
7400 r32&=~(1LL<<rt1[i+1]);
7401 r32&=~(1LL<<rt2[i+1]);
7402 }
7403 // Assume these are needed (delay slot)
7404 if(us1[i+1]>0)
7405 {
7406 if((regs[i].was32>>us1[i+1])&1) r32|=1LL<<us1[i+1];
7407 }
7408 if(us2[i+1]>0)
7409 {
7410 if((regs[i].was32>>us2[i+1])&1) r32|=1LL<<us2[i+1];
7411 }
7412 if(dep1[i+1]&&!((unneeded_reg_upper[i]>>dep1[i+1])&1))
7413 {
7414 if((regs[i].was32>>dep1[i+1])&1) r32|=1LL<<dep1[i+1];
7415 }
7416 if(dep2[i+1]&&!((unneeded_reg_upper[i]>>dep2[i+1])&1))
7417 {
7418 if((regs[i].was32>>dep2[i+1])&1) r32|=1LL<<dep2[i+1];
7419 }
7420 }
1e973cb0 7421 else if(itype[i]==SYSCALL||itype[i]==HLECALL||itype[i]==INTCALL)
57871462 7422 {
7423 // SYSCALL instruction (software interrupt)
7424 r32=0;
7425 }
7426 else if(itype[i]==COP0 && (source[i]&0x3f)==0x18)
7427 {
7428 // ERET instruction (return from interrupt)
7429 r32=0;
7430 }
7431 // Check 32 bits
7432 r32&=~(1LL<<rt1[i]);
7433 r32&=~(1LL<<rt2[i]);
7434 if(us1[i]>0)
7435 {
7436 if((regs[i].was32>>us1[i])&1) r32|=1LL<<us1[i];
7437 }
7438 if(us2[i]>0)
7439 {
7440 if((regs[i].was32>>us2[i])&1) r32|=1LL<<us2[i];
7441 }
7442 if(dep1[i]&&!((unneeded_reg_upper[i]>>dep1[i])&1))
7443 {
7444 if((regs[i].was32>>dep1[i])&1) r32|=1LL<<dep1[i];
7445 }
7446 if(dep2[i]&&!((unneeded_reg_upper[i]>>dep2[i])&1))
7447 {
7448 if((regs[i].was32>>dep2[i])&1) r32|=1LL<<dep2[i];
7449 }
7450 //requires_32bit[i]=r32;
7451 pr32[i]=r32;
7452
7453 // Dirty registers which are 32-bit, require 32-bit input
7454 // as they will be written as 32-bit values
7455 for(hr=0;hr<HOST_REGS;hr++)
7456 {
7457 if(regs[i].regmap_entry[hr]>0&&regs[i].regmap_entry[hr]<64) {
7458 if((regs[i].was32>>regs[i].regmap_entry[hr])&(regs[i].wasdirty>>hr)&1) {
7459 if(!((unneeded_reg_upper[i]>>regs[i].regmap_entry[hr])&1))
7460 pr32[i]|=1LL<<regs[i].regmap_entry[hr];
7461 //requires_32bit[i]|=1LL<<regs[i].regmap_entry[hr];
7462 }
7463 }
7464 }
7465 }
7466}
7467
7468// Write back dirty registers as soon as we will no longer modify them,
7469// so that we don't end up with lots of writes at the branches.
7470void clean_registers(int istart,int iend,int wr)
7471{
7472 int i;
7473 int r;
7474 u_int will_dirty_i,will_dirty_next,temp_will_dirty;
7475 u_int wont_dirty_i,wont_dirty_next,temp_wont_dirty;
7476 if(iend==slen-1) {
7477 will_dirty_i=will_dirty_next=0;
7478 wont_dirty_i=wont_dirty_next=0;
7479 }else{
7480 will_dirty_i=will_dirty_next=will_dirty[iend+1];
7481 wont_dirty_i=wont_dirty_next=wont_dirty[iend+1];
7482 }
7483 for (i=iend;i>=istart;i--)
7484 {
7485 if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
7486 {
7487 if(ba[i]<start || ba[i]>=(start+slen*4))
7488 {
7489 // Branch out of this block, flush all regs
7490 if(itype[i]==RJUMP||itype[i]==UJUMP||(source[i]>>16)==0x1000)
7491 {
7492 // Unconditional branch
7493 will_dirty_i=0;
7494 wont_dirty_i=0;
7495 // Merge in delay slot (will dirty)
7496 for(r=0;r<HOST_REGS;r++) {
7497 if(r!=EXCLUDE_REG) {
7498 if((branch_regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7499 if((branch_regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7500 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7501 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7502 if((branch_regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7503 if(branch_regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7504 if(branch_regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7505 if((regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7506 if((regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7507 if((regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7508 if((regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7509 if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7510 if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7511 if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7512 }
7513 }
7514 }
7515 else
7516 {
7517 // Conditional branch
7518 will_dirty_i=0;
7519 wont_dirty_i=wont_dirty_next;
7520 // Merge in delay slot (will dirty)
7521 for(r=0;r<HOST_REGS;r++) {
7522 if(r!=EXCLUDE_REG) {
7523 if(!likely[i]) {
7524 // Might not dirty if likely branch is not taken
7525 if((branch_regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7526 if((branch_regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7527 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7528 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7529 if((branch_regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7530 if(branch_regs[i].regmap[r]==0) will_dirty_i&=~(1<<r);
7531 if(branch_regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7532 //if((regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7533 //if((regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7534 if((regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7535 if((regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7536 if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7537 if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7538 if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7539 }
7540 }
7541 }
7542 }
7543 // Merge in delay slot (wont dirty)
7544 for(r=0;r<HOST_REGS;r++) {
7545 if(r!=EXCLUDE_REG) {
7546 if((regs[i].regmap[r]&63)==rt1[i]) wont_dirty_i|=1<<r;
7547 if((regs[i].regmap[r]&63)==rt2[i]) wont_dirty_i|=1<<r;
7548 if((regs[i].regmap[r]&63)==rt1[i+1]) wont_dirty_i|=1<<r;
7549 if((regs[i].regmap[r]&63)==rt2[i+1]) wont_dirty_i|=1<<r;
7550 if(regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
7551 if((branch_regs[i].regmap[r]&63)==rt1[i]) wont_dirty_i|=1<<r;
7552 if((branch_regs[i].regmap[r]&63)==rt2[i]) wont_dirty_i|=1<<r;
7553 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) wont_dirty_i|=1<<r;
7554 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) wont_dirty_i|=1<<r;
7555 if(branch_regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
7556 }
7557 }
7558 if(wr) {
7559 #ifndef DESTRUCTIVE_WRITEBACK
7560 branch_regs[i].dirty&=wont_dirty_i;
7561 #endif
7562 branch_regs[i].dirty|=will_dirty_i;
7563 }
7564 }
7565 else
7566 {
7567 // Internal branch
7568 if(ba[i]<=start+i*4) {
7569 // Backward branch
7570 if(itype[i]==RJUMP||itype[i]==UJUMP||(source[i]>>16)==0x1000)
7571 {
7572 // Unconditional branch
7573 temp_will_dirty=0;
7574 temp_wont_dirty=0;
7575 // Merge in delay slot (will dirty)
7576 for(r=0;r<HOST_REGS;r++) {
7577 if(r!=EXCLUDE_REG) {
7578 if((branch_regs[i].regmap[r]&63)==rt1[i]) temp_will_dirty|=1<<r;
7579 if((branch_regs[i].regmap[r]&63)==rt2[i]) temp_will_dirty|=1<<r;
7580 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) temp_will_dirty|=1<<r;
7581 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) temp_will_dirty|=1<<r;
7582 if((branch_regs[i].regmap[r]&63)>33) temp_will_dirty&=~(1<<r);
7583 if(branch_regs[i].regmap[r]<=0) temp_will_dirty&=~(1<<r);
7584 if(branch_regs[i].regmap[r]==CCREG) temp_will_dirty|=1<<r;
7585 if((regs[i].regmap[r]&63)==rt1[i]) temp_will_dirty|=1<<r;
7586 if((regs[i].regmap[r]&63)==rt2[i]) temp_will_dirty|=1<<r;
7587 if((regs[i].regmap[r]&63)==rt1[i+1]) temp_will_dirty|=1<<r;
7588 if((regs[i].regmap[r]&63)==rt2[i+1]) temp_will_dirty|=1<<r;
7589 if((regs[i].regmap[r]&63)>33) temp_will_dirty&=~(1<<r);
7590 if(regs[i].regmap[r]<=0) temp_will_dirty&=~(1<<r);
7591 if(regs[i].regmap[r]==CCREG) temp_will_dirty|=1<<r;
7592 }
7593 }
7594 } else {
7595 // Conditional branch (not taken case)
7596 temp_will_dirty=will_dirty_next;
7597 temp_wont_dirty=wont_dirty_next;
7598 // Merge in delay slot (will dirty)
7599 for(r=0;r<HOST_REGS;r++) {
7600 if(r!=EXCLUDE_REG) {
7601 if(!likely[i]) {
7602 // Will not dirty if likely branch is not taken
7603 if((branch_regs[i].regmap[r]&63)==rt1[i]) temp_will_dirty|=1<<r;
7604 if((branch_regs[i].regmap[r]&63)==rt2[i]) temp_will_dirty|=1<<r;
7605 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) temp_will_dirty|=1<<r;
7606 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) temp_will_dirty|=1<<r;
7607 if((branch_regs[i].regmap[r]&63)>33) temp_will_dirty&=~(1<<r);
7608 if(branch_regs[i].regmap[r]==0) temp_will_dirty&=~(1<<r);
7609 if(branch_regs[i].regmap[r]==CCREG) temp_will_dirty|=1<<r;
7610 //if((regs[i].regmap[r]&63)==rt1[i]) temp_will_dirty|=1<<r;
7611 //if((regs[i].regmap[r]&63)==rt2[i]) temp_will_dirty|=1<<r;
7612 if((regs[i].regmap[r]&63)==rt1[i+1]) temp_will_dirty|=1<<r;
7613 if((regs[i].regmap[r]&63)==rt2[i+1]) temp_will_dirty|=1<<r;
7614 if((regs[i].regmap[r]&63)>33) temp_will_dirty&=~(1<<r);
7615 if(regs[i].regmap[r]<=0) temp_will_dirty&=~(1<<r);
7616 if(regs[i].regmap[r]==CCREG) temp_will_dirty|=1<<r;
7617 }
7618 }
7619 }
7620 }
7621 // Merge in delay slot (wont dirty)
7622 for(r=0;r<HOST_REGS;r++) {
7623 if(r!=EXCLUDE_REG) {
7624 if((regs[i].regmap[r]&63)==rt1[i]) temp_wont_dirty|=1<<r;
7625 if((regs[i].regmap[r]&63)==rt2[i]) temp_wont_dirty|=1<<r;
7626 if((regs[i].regmap[r]&63)==rt1[i+1]) temp_wont_dirty|=1<<r;
7627 if((regs[i].regmap[r]&63)==rt2[i+1]) temp_wont_dirty|=1<<r;
7628 if(regs[i].regmap[r]==CCREG) temp_wont_dirty|=1<<r;
7629 if((branch_regs[i].regmap[r]&63)==rt1[i]) temp_wont_dirty|=1<<r;
7630 if((branch_regs[i].regmap[r]&63)==rt2[i]) temp_wont_dirty|=1<<r;
7631 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) temp_wont_dirty|=1<<r;
7632 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) temp_wont_dirty|=1<<r;
7633 if(branch_regs[i].regmap[r]==CCREG) temp_wont_dirty|=1<<r;
7634 }
7635 }
7636 // Deal with changed mappings
7637 if(i<iend) {
7638 for(r=0;r<HOST_REGS;r++) {
7639 if(r!=EXCLUDE_REG) {
7640 if(regs[i].regmap[r]!=regmap_pre[i][r]) {
7641 temp_will_dirty&=~(1<<r);
7642 temp_wont_dirty&=~(1<<r);
7643 if((regmap_pre[i][r]&63)>0 && (regmap_pre[i][r]&63)<34) {
7644 temp_will_dirty|=((unneeded_reg[i]>>(regmap_pre[i][r]&63))&1)<<r;
7645 temp_wont_dirty|=((unneeded_reg[i]>>(regmap_pre[i][r]&63))&1)<<r;
7646 } else {
7647 temp_will_dirty|=1<<r;
7648 temp_wont_dirty|=1<<r;
7649 }
7650 }
7651 }
7652 }
7653 }
7654 if(wr) {
7655 will_dirty[i]=temp_will_dirty;
7656 wont_dirty[i]=temp_wont_dirty;
7657 clean_registers((ba[i]-start)>>2,i-1,0);
7658 }else{
7659 // Limit recursion. It can take an excessive amount
7660 // of time if there are a lot of nested loops.
7661 will_dirty[(ba[i]-start)>>2]=0;
7662 wont_dirty[(ba[i]-start)>>2]=-1;
7663 }
7664 }
7665 /*else*/ if(1)
7666 {
7667 if(itype[i]==RJUMP||itype[i]==UJUMP||(source[i]>>16)==0x1000)
7668 {
7669 // Unconditional branch
7670 will_dirty_i=0;
7671 wont_dirty_i=0;
7672 //if(ba[i]>start+i*4) { // Disable recursion (for debugging)
7673 for(r=0;r<HOST_REGS;r++) {
7674 if(r!=EXCLUDE_REG) {
7675 if(branch_regs[i].regmap[r]==regs[(ba[i]-start)>>2].regmap_entry[r]) {
7676 will_dirty_i|=will_dirty[(ba[i]-start)>>2]&(1<<r);
7677 wont_dirty_i|=wont_dirty[(ba[i]-start)>>2]&(1<<r);
7678 }
e3234ecf 7679 if(branch_regs[i].regmap[r]>=0) {
7680 will_dirty_i|=((unneeded_reg[(ba[i]-start)>>2]>>(branch_regs[i].regmap[r]&63))&1)<<r;
7681 wont_dirty_i|=((unneeded_reg[(ba[i]-start)>>2]>>(branch_regs[i].regmap[r]&63))&1)<<r;
7682 }
57871462 7683 }
7684 }
7685 //}
7686 // Merge in delay slot
7687 for(r=0;r<HOST_REGS;r++) {
7688 if(r!=EXCLUDE_REG) {
7689 if((branch_regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7690 if((branch_regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7691 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7692 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7693 if((branch_regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7694 if(branch_regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7695 if(branch_regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7696 if((regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7697 if((regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7698 if((regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7699 if((regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7700 if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7701 if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7702 if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7703 }
7704 }
7705 } else {
7706 // Conditional branch
7707 will_dirty_i=will_dirty_next;
7708 wont_dirty_i=wont_dirty_next;
7709 //if(ba[i]>start+i*4) { // Disable recursion (for debugging)
7710 for(r=0;r<HOST_REGS;r++) {
7711 if(r!=EXCLUDE_REG) {
e3234ecf 7712 signed char target_reg=branch_regs[i].regmap[r];
7713 if(target_reg==regs[(ba[i]-start)>>2].regmap_entry[r]) {
57871462 7714 will_dirty_i&=will_dirty[(ba[i]-start)>>2]&(1<<r);
7715 wont_dirty_i|=wont_dirty[(ba[i]-start)>>2]&(1<<r);
7716 }
e3234ecf 7717 else if(target_reg>=0) {
7718 will_dirty_i&=((unneeded_reg[(ba[i]-start)>>2]>>(target_reg&63))&1)<<r;
7719 wont_dirty_i|=((unneeded_reg[(ba[i]-start)>>2]>>(target_reg&63))&1)<<r;
57871462 7720 }
7721 // Treat delay slot as part of branch too
7722 /*if(regs[i+1].regmap[r]==regs[(ba[i]-start)>>2].regmap_entry[r]) {
7723 will_dirty[i+1]&=will_dirty[(ba[i]-start)>>2]&(1<<r);
7724 wont_dirty[i+1]|=wont_dirty[(ba[i]-start)>>2]&(1<<r);
7725 }
7726 else
7727 {
7728 will_dirty[i+1]&=~(1<<r);
7729 }*/
7730 }
7731 }
7732 //}
7733 // Merge in delay slot
7734 for(r=0;r<HOST_REGS;r++) {
7735 if(r!=EXCLUDE_REG) {
7736 if(!likely[i]) {
7737 // Might not dirty if likely branch is not taken
7738 if((branch_regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7739 if((branch_regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7740 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7741 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7742 if((branch_regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7743 if(branch_regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7744 if(branch_regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7745 //if((regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7746 //if((regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7747 if((regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7748 if((regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7749 if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7750 if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7751 if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7752 }
7753 }
7754 }
7755 }
e3234ecf 7756 // Merge in delay slot (won't dirty)
57871462 7757 for(r=0;r<HOST_REGS;r++) {
7758 if(r!=EXCLUDE_REG) {
7759 if((regs[i].regmap[r]&63)==rt1[i]) wont_dirty_i|=1<<r;
7760 if((regs[i].regmap[r]&63)==rt2[i]) wont_dirty_i|=1<<r;
7761 if((regs[i].regmap[r]&63)==rt1[i+1]) wont_dirty_i|=1<<r;
7762 if((regs[i].regmap[r]&63)==rt2[i+1]) wont_dirty_i|=1<<r;
7763 if(regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
7764 if((branch_regs[i].regmap[r]&63)==rt1[i]) wont_dirty_i|=1<<r;
7765 if((branch_regs[i].regmap[r]&63)==rt2[i]) wont_dirty_i|=1<<r;
7766 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) wont_dirty_i|=1<<r;
7767 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) wont_dirty_i|=1<<r;
7768 if(branch_regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
7769 }
7770 }
7771 if(wr) {
7772 #ifndef DESTRUCTIVE_WRITEBACK
7773 branch_regs[i].dirty&=wont_dirty_i;
7774 #endif
7775 branch_regs[i].dirty|=will_dirty_i;
7776 }
7777 }
7778 }
7779 }
1e973cb0 7780 else if(itype[i]==SYSCALL||itype[i]==HLECALL||itype[i]==INTCALL)
57871462 7781 {
7782 // SYSCALL instruction (software interrupt)
7783 will_dirty_i=0;
7784 wont_dirty_i=0;
7785 }
7786 else if(itype[i]==COP0 && (source[i]&0x3f)==0x18)
7787 {
7788 // ERET instruction (return from interrupt)
7789 will_dirty_i=0;
7790 wont_dirty_i=0;
7791 }
7792 will_dirty_next=will_dirty_i;
7793 wont_dirty_next=wont_dirty_i;
7794 for(r=0;r<HOST_REGS;r++) {
7795 if(r!=EXCLUDE_REG) {
7796 if((regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7797 if((regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7798 if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7799 if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7800 if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7801 if((regs[i].regmap[r]&63)==rt1[i]) wont_dirty_i|=1<<r;
7802 if((regs[i].regmap[r]&63)==rt2[i]) wont_dirty_i|=1<<r;
7803 if(regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
7804 if(i>istart) {
7805 if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&itype[i]!=CJUMP&&itype[i]!=SJUMP&&itype[i]!=FJUMP)
7806 {
7807 // Don't store a register immediately after writing it,
7808 // may prevent dual-issue.
7809 if((regs[i].regmap[r]&63)==rt1[i-1]) wont_dirty_i|=1<<r;
7810 if((regs[i].regmap[r]&63)==rt2[i-1]) wont_dirty_i|=1<<r;
7811 }
7812 }
7813 }
7814 }
7815 // Save it
7816 will_dirty[i]=will_dirty_i;
7817 wont_dirty[i]=wont_dirty_i;
7818 // Mark registers that won't be dirtied as not dirty
7819 if(wr) {
7820 /*printf("wr (%d,%d) %x will:",istart,iend,start+i*4);
7821 for(r=0;r<HOST_REGS;r++) {
7822 if((will_dirty_i>>r)&1) {
7823 printf(" r%d",r);
7824 }
7825 }
7826 printf("\n");*/
7827
7828 //if(i==istart||(itype[i-1]!=RJUMP&&itype[i-1]!=UJUMP&&itype[i-1]!=CJUMP&&itype[i-1]!=SJUMP&&itype[i-1]!=FJUMP)) {
7829 regs[i].dirty|=will_dirty_i;
7830 #ifndef DESTRUCTIVE_WRITEBACK
7831 regs[i].dirty&=wont_dirty_i;
7832 if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
7833 {
7834 if(i<iend-1&&itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000) {
7835 for(r=0;r<HOST_REGS;r++) {
7836 if(r!=EXCLUDE_REG) {
7837 if(regs[i].regmap[r]==regmap_pre[i+2][r]) {
7838 regs[i+2].wasdirty&=wont_dirty_i|~(1<<r);
7839 }else {/*printf("i: %x (%d) mismatch(+2): %d\n",start+i*4,i,r);/*assert(!((wont_dirty_i>>r)&1));*/}
7840 }
7841 }
7842 }
7843 }
7844 else
7845 {
7846 if(i<iend) {
7847 for(r=0;r<HOST_REGS;r++) {
7848 if(r!=EXCLUDE_REG) {
7849 if(regs[i].regmap[r]==regmap_pre[i+1][r]) {
7850 regs[i+1].wasdirty&=wont_dirty_i|~(1<<r);
7851 }else {/*printf("i: %x (%d) mismatch(+1): %d\n",start+i*4,i,r);/*assert(!((wont_dirty_i>>r)&1));*/}
7852 }
7853 }
7854 }
7855 }
7856 #endif
7857 //}
7858 }
7859 // Deal with changed mappings
7860 temp_will_dirty=will_dirty_i;
7861 temp_wont_dirty=wont_dirty_i;
7862 for(r=0;r<HOST_REGS;r++) {
7863 if(r!=EXCLUDE_REG) {
7864 int nr;
7865 if(regs[i].regmap[r]==regmap_pre[i][r]) {
7866 if(wr) {
7867 #ifndef DESTRUCTIVE_WRITEBACK
7868 regs[i].wasdirty&=wont_dirty_i|~(1<<r);
7869 #endif
7870 regs[i].wasdirty|=will_dirty_i&(1<<r);
7871 }
7872 }
f776eb14 7873 else if(regmap_pre[i][r]>=0&&(nr=get_reg(regs[i].regmap,regmap_pre[i][r]))>=0) {
57871462 7874 // Register moved to a different register
7875 will_dirty_i&=~(1<<r);
7876 wont_dirty_i&=~(1<<r);
7877 will_dirty_i|=((temp_will_dirty>>nr)&1)<<r;
7878 wont_dirty_i|=((temp_wont_dirty>>nr)&1)<<r;
7879 if(wr) {
7880 #ifndef DESTRUCTIVE_WRITEBACK
7881 regs[i].wasdirty&=wont_dirty_i|~(1<<r);
7882 #endif
7883 regs[i].wasdirty|=will_dirty_i&(1<<r);
7884 }
7885 }
7886 else {
7887 will_dirty_i&=~(1<<r);
7888 wont_dirty_i&=~(1<<r);
7889 if((regmap_pre[i][r]&63)>0 && (regmap_pre[i][r]&63)<34) {
7890 will_dirty_i|=((unneeded_reg[i]>>(regmap_pre[i][r]&63))&1)<<r;
7891 wont_dirty_i|=((unneeded_reg[i]>>(regmap_pre[i][r]&63))&1)<<r;
7892 } else {
7893 wont_dirty_i|=1<<r;
7894 /*printf("i: %x (%d) mismatch: %d\n",start+i*4,i,r);/*assert(!((will_dirty>>r)&1));*/
7895 }
7896 }
7897 }
7898 }
7899 }
7900}
7901
4600ba03 7902#ifdef DISASM
57871462 7903 /* disassembly */
7904void disassemble_inst(int i)
7905{
7906 if (bt[i]) printf("*"); else printf(" ");
7907 switch(itype[i]) {
7908 case UJUMP:
7909 printf (" %x: %s %8x\n",start+i*4,insn[i],ba[i]);break;
7910 case CJUMP:
7911 printf (" %x: %s r%d,r%d,%8x\n",start+i*4,insn[i],rs1[i],rs2[i],i?start+i*4+4+((signed int)((unsigned int)source[i]<<16)>>14):*ba);break;
7912 case SJUMP:
7913 printf (" %x: %s r%d,%8x\n",start+i*4,insn[i],rs1[i],start+i*4+4+((signed int)((unsigned int)source[i]<<16)>>14));break;
7914 case FJUMP:
7915 printf (" %x: %s %8x\n",start+i*4,insn[i],ba[i]);break;
7916 case RJUMP:
74426039 7917 if (opcode[i]==0x9&&rt1[i]!=31)
5067f341 7918 printf (" %x: %s r%d,r%d\n",start+i*4,insn[i],rt1[i],rs1[i]);
7919 else
7920 printf (" %x: %s r%d\n",start+i*4,insn[i],rs1[i]);
7921 break;
57871462 7922 case SPAN:
7923 printf (" %x: %s (pagespan) r%d,r%d,%8x\n",start+i*4,insn[i],rs1[i],rs2[i],ba[i]);break;
7924 case IMM16:
7925 if(opcode[i]==0xf) //LUI
7926 printf (" %x: %s r%d,%4x0000\n",start+i*4,insn[i],rt1[i],imm[i]&0xffff);
7927 else
7928 printf (" %x: %s r%d,r%d,%d\n",start+i*4,insn[i],rt1[i],rs1[i],imm[i]);
7929 break;
7930 case LOAD:
7931 case LOADLR:
7932 printf (" %x: %s r%d,r%d+%x\n",start+i*4,insn[i],rt1[i],rs1[i],imm[i]);
7933 break;
7934 case STORE:
7935 case STORELR:
7936 printf (" %x: %s r%d,r%d+%x\n",start+i*4,insn[i],rs2[i],rs1[i],imm[i]);
7937 break;
7938 case ALU:
7939 case SHIFT:
7940 printf (" %x: %s r%d,r%d,r%d\n",start+i*4,insn[i],rt1[i],rs1[i],rs2[i]);
7941 break;
7942 case MULTDIV:
7943 printf (" %x: %s r%d,r%d\n",start+i*4,insn[i],rs1[i],rs2[i]);
7944 break;
7945 case SHIFTIMM:
7946 printf (" %x: %s r%d,r%d,%d\n",start+i*4,insn[i],rt1[i],rs1[i],imm[i]);
7947 break;
7948 case MOV:
7949 if((opcode2[i]&0x1d)==0x10)
7950 printf (" %x: %s r%d\n",start+i*4,insn[i],rt1[i]);
7951 else if((opcode2[i]&0x1d)==0x11)
7952 printf (" %x: %s r%d\n",start+i*4,insn[i],rs1[i]);
7953 else
7954 printf (" %x: %s\n",start+i*4,insn[i]);
7955 break;
7956 case COP0:
7957 if(opcode2[i]==0)
7958 printf (" %x: %s r%d,cpr0[%d]\n",start+i*4,insn[i],rt1[i],(source[i]>>11)&0x1f); // MFC0
7959 else if(opcode2[i]==4)
7960 printf (" %x: %s r%d,cpr0[%d]\n",start+i*4,insn[i],rs1[i],(source[i]>>11)&0x1f); // MTC0
7961 else printf (" %x: %s\n",start+i*4,insn[i]);
7962 break;
7963 case COP1:
7964 if(opcode2[i]<3)
7965 printf (" %x: %s r%d,cpr1[%d]\n",start+i*4,insn[i],rt1[i],(source[i]>>11)&0x1f); // MFC1
7966 else if(opcode2[i]>3)
7967 printf (" %x: %s r%d,cpr1[%d]\n",start+i*4,insn[i],rs1[i],(source[i]>>11)&0x1f); // MTC1
7968 else printf (" %x: %s\n",start+i*4,insn[i]);
7969 break;
b9b61529 7970 case COP2:
7971 if(opcode2[i]<3)
7972 printf (" %x: %s r%d,cpr2[%d]\n",start+i*4,insn[i],rt1[i],(source[i]>>11)&0x1f); // MFC2
7973 else if(opcode2[i]>3)
7974 printf (" %x: %s r%d,cpr2[%d]\n",start+i*4,insn[i],rs1[i],(source[i]>>11)&0x1f); // MTC2
7975 else printf (" %x: %s\n",start+i*4,insn[i]);
7976 break;
57871462 7977 case C1LS:
7978 printf (" %x: %s cpr1[%d],r%d+%x\n",start+i*4,insn[i],(source[i]>>16)&0x1f,rs1[i],imm[i]);
7979 break;
b9b61529 7980 case C2LS:
7981 printf (" %x: %s cpr2[%d],r%d+%x\n",start+i*4,insn[i],(source[i]>>16)&0x1f,rs1[i],imm[i]);
7982 break;
1e973cb0 7983 case INTCALL:
7984 printf (" %x: %s (INTCALL)\n",start+i*4,insn[i]);
7985 break;
57871462 7986 default:
7987 //printf (" %s %8x\n",insn[i],source[i]);
7988 printf (" %x: %s\n",start+i*4,insn[i]);
7989 }
7990}
4600ba03 7991#else
7992static void disassemble_inst(int i) {}
7993#endif // DISASM
57871462 7994
dc990066 7995// clear the state completely, instead of just marking
7996// things invalid like invalidate_all_pages() does
7997void new_dynarec_clear_full()
57871462 7998{
57871462 7999 int n;
35775df7 8000 out=(u_char *)BASE_ADDR;
8001 memset(invalid_code,1,sizeof(invalid_code));
8002 memset(hash_table,0xff,sizeof(hash_table));
57871462 8003 memset(mini_ht,-1,sizeof(mini_ht));
8004 memset(restore_candidate,0,sizeof(restore_candidate));
dc990066 8005 memset(shadow,0,sizeof(shadow));
57871462 8006 copy=shadow;
8007 expirep=16384; // Expiry pointer, +2 blocks
8008 pending_exception=0;
8009 literalcount=0;
57871462 8010 stop_after_jal=0;
9be4ba64 8011 inv_code_start=inv_code_end=~0;
57871462 8012 // TLB
af4ee1fe 8013#ifndef DISABLE_TLB
57871462 8014 using_tlb=0;
8015 for(n=0;n<524288;n++) // 0 .. 0x7FFFFFFF
8016 memory_map[n]=-1;
8017 for(n=524288;n<526336;n++) // 0x80000000 .. 0x807FFFFF
8018 memory_map[n]=((u_int)rdram-0x80000000)>>2;
8019 for(n=526336;n<1048576;n++) // 0x80800000 .. 0xFFFFFFFF
8020 memory_map[n]=-1;
63cb0298 8021#endif
dc990066 8022 for(n=0;n<4096;n++) ll_clear(jump_in+n);
8023 for(n=0;n<4096;n++) ll_clear(jump_out+n);
8024 for(n=0;n<4096;n++) ll_clear(jump_dirty+n);
8025}
8026
8027void new_dynarec_init()
8028{
8029 printf("Init new dynarec\n");
8030 out=(u_char *)BASE_ADDR;
a327ad27 8031#if BASE_ADDR_FIXED
dc990066 8032 if (mmap (out, 1<<TARGET_SIZE_2,
8033 PROT_READ | PROT_WRITE | PROT_EXEC,
8034 MAP_FIXED | MAP_PRIVATE | MAP_ANONYMOUS,
8035 -1, 0) <= 0) {printf("mmap() failed\n");}
bdeade46 8036#else
8037 // not all systems allow execute in data segment by default
8038 if (mprotect(out, 1<<TARGET_SIZE_2, PROT_READ | PROT_WRITE | PROT_EXEC) != 0)
8039 printf("mprotect() failed\n");
8040#endif
dc990066 8041#ifdef MUPEN64
8042 rdword=&readmem_dword;
8043 fake_pc.f.r.rs=&readmem_dword;
8044 fake_pc.f.r.rt=&readmem_dword;
8045 fake_pc.f.r.rd=&readmem_dword;
8046#endif
8047 int n;
2573466a 8048 cycle_multiplier=200;
dc990066 8049 new_dynarec_clear_full();
8050#ifdef HOST_IMM8
8051 // Copy this into local area so we don't have to put it in every literal pool
8052 invc_ptr=invalid_code;
8053#endif
24385cae 8054#ifdef MUPEN64
57871462 8055 for(n=0;n<0x8000;n++) { // 0 .. 0x7FFFFFFF
8056 writemem[n] = write_nomem_new;
8057 writememb[n] = write_nomemb_new;
8058 writememh[n] = write_nomemh_new;
24385cae 8059#ifndef FORCE32
57871462 8060 writememd[n] = write_nomemd_new;
24385cae 8061#endif
57871462 8062 readmem[n] = read_nomem_new;
8063 readmemb[n] = read_nomemb_new;
8064 readmemh[n] = read_nomemh_new;
24385cae 8065#ifndef FORCE32
57871462 8066 readmemd[n] = read_nomemd_new;
24385cae 8067#endif
57871462 8068 }
8069 for(n=0x8000;n<0x8080;n++) { // 0x80000000 .. 0x807FFFFF
8070 writemem[n] = write_rdram_new;
8071 writememb[n] = write_rdramb_new;
8072 writememh[n] = write_rdramh_new;
24385cae 8073#ifndef FORCE32
57871462 8074 writememd[n] = write_rdramd_new;
24385cae 8075#endif
57871462 8076 }
8077 for(n=0xC000;n<0x10000;n++) { // 0xC0000000 .. 0xFFFFFFFF
8078 writemem[n] = write_nomem_new;
8079 writememb[n] = write_nomemb_new;
8080 writememh[n] = write_nomemh_new;
24385cae 8081#ifndef FORCE32
57871462 8082 writememd[n] = write_nomemd_new;
24385cae 8083#endif
57871462 8084 readmem[n] = read_nomem_new;
8085 readmemb[n] = read_nomemb_new;
8086 readmemh[n] = read_nomemh_new;
24385cae 8087#ifndef FORCE32
57871462 8088 readmemd[n] = read_nomemd_new;
24385cae 8089#endif
57871462 8090 }
24385cae 8091#endif
57871462 8092 tlb_hacks();
8093 arch_init();
a327ad27 8094#ifndef RAM_FIXED
8095 ram_offset=(u_int)rdram-0x80000000;
8096#endif
b105cf4f 8097 if (ram_offset!=0)
8098 printf("warning: RAM is not directly mapped, performance will suffer\n");
57871462 8099}
8100
8101void new_dynarec_cleanup()
8102{
8103 int n;
a327ad27 8104 #if BASE_ADDR_FIXED
57871462 8105 if (munmap ((void *)BASE_ADDR, 1<<TARGET_SIZE_2) < 0) {printf("munmap() failed\n");}
bdeade46 8106 #endif
57871462 8107 for(n=0;n<4096;n++) ll_clear(jump_in+n);
8108 for(n=0;n<4096;n++) ll_clear(jump_out+n);
8109 for(n=0;n<4096;n++) ll_clear(jump_dirty+n);
8110 #ifdef ROM_COPY
8111 if (munmap (ROM_COPY, 67108864) < 0) {printf("munmap() failed\n");}
8112 #endif
8113}
8114
8115int new_recompile_block(int addr)
8116{
8117/*
8118 if(addr==0x800cd050) {
8119 int block;
8120 for(block=0x80000;block<0x80800;block++) invalidate_block(block);
8121 int n;
8122 for(n=0;n<=2048;n++) ll_clear(jump_dirty+n);
8123 }
8124*/
8125 //if(Count==365117028) tracedebug=1;
8126 assem_debug("NOTCOMPILED: addr = %x -> %x\n", (int)addr, (int)out);
8127 //printf("NOTCOMPILED: addr = %x -> %x\n", (int)addr, (int)out);
8128 //printf("TRACE: count=%d next=%d (compile %x)\n",Count,next_interupt,addr);
8129 //if(debug)
8130 //printf("TRACE: count=%d next=%d (checksum %x)\n",Count,next_interupt,mchecksum());
8131 //printf("fpu mapping=%x enabled=%x\n",(Status & 0x04000000)>>26,(Status & 0x20000000)>>29);
8132 /*if(Count>=312978186) {
8133 rlist();
8134 }*/
8135 //rlist();
8136 start = (u_int)addr&~3;
8137 //assert(((u_int)addr&1)==0);
2f546f9a 8138 new_dynarec_did_compile=1;
7139f3c8 8139#ifdef PCSX
9ad4d757 8140 if (Config.HLE && start == 0x80001000) // hlecall
560e4a12 8141 {
7139f3c8 8142 // XXX: is this enough? Maybe check hleSoftCall?
bb5285ef 8143 u_int beginning=(u_int)out;
7139f3c8 8144 u_int page=get_page(start);
7139f3c8 8145 invalid_code[start>>12]=0;
8146 emit_movimm(start,0);
8147 emit_writeword(0,(int)&pcaddr);
bb5285ef 8148 emit_jmp((int)new_dyna_leave);
15776b68 8149 literal_pool(0);
bb5285ef 8150#ifdef __arm__
8151 __clear_cache((void *)beginning,out);
8152#endif
9ad4d757 8153 ll_add(jump_in+page,start,(void *)beginning);
7139f3c8 8154 return 0;
8155 }
560e4a12 8156 else if ((u_int)addr < 0x00200000 ||
8157 (0xa0000000 <= addr && addr < 0xa0200000)) {
7139f3c8 8158 // used for BIOS calls mostly?
560e4a12 8159 source = (u_int *)((u_int)rdram+(start&0x1fffff));
8160 pagelimit = (addr&0xa0000000)|0x00200000;
8161 }
8162 else if (!Config.HLE && (
8163/* (0x9fc00000 <= addr && addr < 0x9fc80000) ||*/
8164 (0xbfc00000 <= addr && addr < 0xbfc80000))) {
8165 // BIOS
8166 source = (u_int *)((u_int)psxR+(start&0x7ffff));
8167 pagelimit = (addr&0xfff00000)|0x80000;
7139f3c8 8168 }
8169 else
8170#endif
3d624f89 8171#ifdef MUPEN64
57871462 8172 if ((int)addr >= 0xa4000000 && (int)addr < 0xa4001000) {
8173 source = (u_int *)((u_int)SP_DMEM+start-0xa4000000);
8174 pagelimit = 0xa4001000;
8175 }
3d624f89 8176 else
8177#endif
4cb76aa4 8178 if ((int)addr >= 0x80000000 && (int)addr < 0x80000000+RAM_SIZE) {
57871462 8179 source = (u_int *)((u_int)rdram+start-0x80000000);
4cb76aa4 8180 pagelimit = 0x80000000+RAM_SIZE;
57871462 8181 }
90ae6d4e 8182#ifndef DISABLE_TLB
57871462 8183 else if ((signed int)addr >= (signed int)0xC0000000) {
8184 //printf("addr=%x mm=%x\n",(u_int)addr,(memory_map[start>>12]<<2));
8185 //if(tlb_LUT_r[start>>12])
8186 //source = (u_int *)(((int)rdram)+(tlb_LUT_r[start>>12]&0xFFFFF000)+(((int)addr)&0xFFF)-0x80000000);
8187 if((signed int)memory_map[start>>12]>=0) {
8188 source = (u_int *)((u_int)(start+(memory_map[start>>12]<<2)));
8189 pagelimit=(start+4096)&0xFFFFF000;
8190 int map=memory_map[start>>12];
8191 int i;
8192 for(i=0;i<5;i++) {
8193 //printf("start: %x next: %x\n",map,memory_map[pagelimit>>12]);
8194 if((map&0xBFFFFFFF)==(memory_map[pagelimit>>12]&0xBFFFFFFF)) pagelimit+=4096;
8195 }
8196 assem_debug("pagelimit=%x\n",pagelimit);
8197 assem_debug("mapping=%x (%x)\n",memory_map[start>>12],(memory_map[start>>12]<<2)+start);
8198 }
8199 else {
8200 assem_debug("Compile at unmapped memory address: %x \n", (int)addr);
8201 //assem_debug("start: %x next: %x\n",memory_map[start>>12],memory_map[(start+4096)>>12]);
560e4a12 8202 return -1; // Caller will invoke exception handler
57871462 8203 }
8204 //printf("source= %x\n",(int)source);
8205 }
90ae6d4e 8206#endif
57871462 8207 else {
8208 printf("Compile at bogus memory address: %x \n", (int)addr);
8209 exit(1);
8210 }
8211
8212 /* Pass 1: disassemble */
8213 /* Pass 2: register dependencies, branch targets */
8214 /* Pass 3: register allocation */
8215 /* Pass 4: branch dependencies */
8216 /* Pass 5: pre-alloc */
8217 /* Pass 6: optimize clean/dirty state */
8218 /* Pass 7: flag 32-bit registers */
8219 /* Pass 8: assembly */
8220 /* Pass 9: linker */
8221 /* Pass 10: garbage collection / free memory */
8222
8223 int i,j;
8224 int done=0;
8225 unsigned int type,op,op2;
8226
8227 //printf("addr = %x source = %x %x\n", addr,source,source[0]);
8228
8229 /* Pass 1 disassembly */
8230
8231 for(i=0;!done;i++) {
e1190b87 8232 bt[i]=0;likely[i]=0;ooo[i]=0;op2=0;
8233 minimum_free_regs[i]=0;
57871462 8234 opcode[i]=op=source[i]>>26;
8235 switch(op)
8236 {
8237 case 0x00: strcpy(insn[i],"special"); type=NI;
8238 op2=source[i]&0x3f;
8239 switch(op2)
8240 {
8241 case 0x00: strcpy(insn[i],"SLL"); type=SHIFTIMM; break;
8242 case 0x02: strcpy(insn[i],"SRL"); type=SHIFTIMM; break;
8243 case 0x03: strcpy(insn[i],"SRA"); type=SHIFTIMM; break;
8244 case 0x04: strcpy(insn[i],"SLLV"); type=SHIFT; break;
8245 case 0x06: strcpy(insn[i],"SRLV"); type=SHIFT; break;
8246 case 0x07: strcpy(insn[i],"SRAV"); type=SHIFT; break;
8247 case 0x08: strcpy(insn[i],"JR"); type=RJUMP; break;
8248 case 0x09: strcpy(insn[i],"JALR"); type=RJUMP; break;
8249 case 0x0C: strcpy(insn[i],"SYSCALL"); type=SYSCALL; break;
8250 case 0x0D: strcpy(insn[i],"BREAK"); type=OTHER; break;
8251 case 0x0F: strcpy(insn[i],"SYNC"); type=OTHER; break;
8252 case 0x10: strcpy(insn[i],"MFHI"); type=MOV; break;
8253 case 0x11: strcpy(insn[i],"MTHI"); type=MOV; break;
8254 case 0x12: strcpy(insn[i],"MFLO"); type=MOV; break;
8255 case 0x13: strcpy(insn[i],"MTLO"); type=MOV; break;
57871462 8256 case 0x18: strcpy(insn[i],"MULT"); type=MULTDIV; break;
8257 case 0x19: strcpy(insn[i],"MULTU"); type=MULTDIV; break;
8258 case 0x1A: strcpy(insn[i],"DIV"); type=MULTDIV; break;
8259 case 0x1B: strcpy(insn[i],"DIVU"); type=MULTDIV; break;
57871462 8260 case 0x20: strcpy(insn[i],"ADD"); type=ALU; break;
8261 case 0x21: strcpy(insn[i],"ADDU"); type=ALU; break;
8262 case 0x22: strcpy(insn[i],"SUB"); type=ALU; break;
8263 case 0x23: strcpy(insn[i],"SUBU"); type=ALU; break;
8264 case 0x24: strcpy(insn[i],"AND"); type=ALU; break;
8265 case 0x25: strcpy(insn[i],"OR"); type=ALU; break;
8266 case 0x26: strcpy(insn[i],"XOR"); type=ALU; break;
8267 case 0x27: strcpy(insn[i],"NOR"); type=ALU; break;
8268 case 0x2A: strcpy(insn[i],"SLT"); type=ALU; break;
8269 case 0x2B: strcpy(insn[i],"SLTU"); type=ALU; break;
57871462 8270 case 0x30: strcpy(insn[i],"TGE"); type=NI; break;
8271 case 0x31: strcpy(insn[i],"TGEU"); type=NI; break;
8272 case 0x32: strcpy(insn[i],"TLT"); type=NI; break;
8273 case 0x33: strcpy(insn[i],"TLTU"); type=NI; break;
8274 case 0x34: strcpy(insn[i],"TEQ"); type=NI; break;
8275 case 0x36: strcpy(insn[i],"TNE"); type=NI; break;
7f2607ea 8276#ifndef FORCE32
8277 case 0x14: strcpy(insn[i],"DSLLV"); type=SHIFT; break;
8278 case 0x16: strcpy(insn[i],"DSRLV"); type=SHIFT; break;
8279 case 0x17: strcpy(insn[i],"DSRAV"); type=SHIFT; break;
8280 case 0x1C: strcpy(insn[i],"DMULT"); type=MULTDIV; break;
8281 case 0x1D: strcpy(insn[i],"DMULTU"); type=MULTDIV; break;
8282 case 0x1E: strcpy(insn[i],"DDIV"); type=MULTDIV; break;
8283 case 0x1F: strcpy(insn[i],"DDIVU"); type=MULTDIV; break;
8284 case 0x2C: strcpy(insn[i],"DADD"); type=ALU; break;
8285 case 0x2D: strcpy(insn[i],"DADDU"); type=ALU; break;
8286 case 0x2E: strcpy(insn[i],"DSUB"); type=ALU; break;
8287 case 0x2F: strcpy(insn[i],"DSUBU"); type=ALU; break;
57871462 8288 case 0x38: strcpy(insn[i],"DSLL"); type=SHIFTIMM; break;
8289 case 0x3A: strcpy(insn[i],"DSRL"); type=SHIFTIMM; break;
8290 case 0x3B: strcpy(insn[i],"DSRA"); type=SHIFTIMM; break;
8291 case 0x3C: strcpy(insn[i],"DSLL32"); type=SHIFTIMM; break;
8292 case 0x3E: strcpy(insn[i],"DSRL32"); type=SHIFTIMM; break;
8293 case 0x3F: strcpy(insn[i],"DSRA32"); type=SHIFTIMM; break;
7f2607ea 8294#endif
57871462 8295 }
8296 break;
8297 case 0x01: strcpy(insn[i],"regimm"); type=NI;
8298 op2=(source[i]>>16)&0x1f;
8299 switch(op2)
8300 {
8301 case 0x00: strcpy(insn[i],"BLTZ"); type=SJUMP; break;
8302 case 0x01: strcpy(insn[i],"BGEZ"); type=SJUMP; break;
8303 case 0x02: strcpy(insn[i],"BLTZL"); type=SJUMP; break;
8304 case 0x03: strcpy(insn[i],"BGEZL"); type=SJUMP; break;
8305 case 0x08: strcpy(insn[i],"TGEI"); type=NI; break;
8306 case 0x09: strcpy(insn[i],"TGEIU"); type=NI; break;
8307 case 0x0A: strcpy(insn[i],"TLTI"); type=NI; break;
8308 case 0x0B: strcpy(insn[i],"TLTIU"); type=NI; break;
8309 case 0x0C: strcpy(insn[i],"TEQI"); type=NI; break;
8310 case 0x0E: strcpy(insn[i],"TNEI"); type=NI; break;
8311 case 0x10: strcpy(insn[i],"BLTZAL"); type=SJUMP; break;
8312 case 0x11: strcpy(insn[i],"BGEZAL"); type=SJUMP; break;
8313 case 0x12: strcpy(insn[i],"BLTZALL"); type=SJUMP; break;
8314 case 0x13: strcpy(insn[i],"BGEZALL"); type=SJUMP; break;
8315 }
8316 break;
8317 case 0x02: strcpy(insn[i],"J"); type=UJUMP; break;
8318 case 0x03: strcpy(insn[i],"JAL"); type=UJUMP; break;
8319 case 0x04: strcpy(insn[i],"BEQ"); type=CJUMP; break;
8320 case 0x05: strcpy(insn[i],"BNE"); type=CJUMP; break;
8321 case 0x06: strcpy(insn[i],"BLEZ"); type=CJUMP; break;
8322 case 0x07: strcpy(insn[i],"BGTZ"); type=CJUMP; break;
8323 case 0x08: strcpy(insn[i],"ADDI"); type=IMM16; break;
8324 case 0x09: strcpy(insn[i],"ADDIU"); type=IMM16; break;
8325 case 0x0A: strcpy(insn[i],"SLTI"); type=IMM16; break;
8326 case 0x0B: strcpy(insn[i],"SLTIU"); type=IMM16; break;
8327 case 0x0C: strcpy(insn[i],"ANDI"); type=IMM16; break;
8328 case 0x0D: strcpy(insn[i],"ORI"); type=IMM16; break;
8329 case 0x0E: strcpy(insn[i],"XORI"); type=IMM16; break;
8330 case 0x0F: strcpy(insn[i],"LUI"); type=IMM16; break;
8331 case 0x10: strcpy(insn[i],"cop0"); type=NI;
8332 op2=(source[i]>>21)&0x1f;
8333 switch(op2)
8334 {
8335 case 0x00: strcpy(insn[i],"MFC0"); type=COP0; break;
8336 case 0x04: strcpy(insn[i],"MTC0"); type=COP0; break;
8337 case 0x10: strcpy(insn[i],"tlb"); type=NI;
8338 switch(source[i]&0x3f)
8339 {
8340 case 0x01: strcpy(insn[i],"TLBR"); type=COP0; break;
8341 case 0x02: strcpy(insn[i],"TLBWI"); type=COP0; break;
8342 case 0x06: strcpy(insn[i],"TLBWR"); type=COP0; break;
8343 case 0x08: strcpy(insn[i],"TLBP"); type=COP0; break;
576bbd8f 8344#ifdef PCSX
8345 case 0x10: strcpy(insn[i],"RFE"); type=COP0; break;
8346#else
57871462 8347 case 0x18: strcpy(insn[i],"ERET"); type=COP0; break;
576bbd8f 8348#endif
57871462 8349 }
8350 }
8351 break;
8352 case 0x11: strcpy(insn[i],"cop1"); type=NI;
8353 op2=(source[i]>>21)&0x1f;
8354 switch(op2)
8355 {
8356 case 0x00: strcpy(insn[i],"MFC1"); type=COP1; break;
8357 case 0x01: strcpy(insn[i],"DMFC1"); type=COP1; break;
8358 case 0x02: strcpy(insn[i],"CFC1"); type=COP1; break;
8359 case 0x04: strcpy(insn[i],"MTC1"); type=COP1; break;
8360 case 0x05: strcpy(insn[i],"DMTC1"); type=COP1; break;
8361 case 0x06: strcpy(insn[i],"CTC1"); type=COP1; break;
8362 case 0x08: strcpy(insn[i],"BC1"); type=FJUMP;
8363 switch((source[i]>>16)&0x3)
8364 {
8365 case 0x00: strcpy(insn[i],"BC1F"); break;
8366 case 0x01: strcpy(insn[i],"BC1T"); break;
8367 case 0x02: strcpy(insn[i],"BC1FL"); break;
8368 case 0x03: strcpy(insn[i],"BC1TL"); break;
8369 }
8370 break;
8371 case 0x10: strcpy(insn[i],"C1.S"); type=NI;
8372 switch(source[i]&0x3f)
8373 {
8374 case 0x00: strcpy(insn[i],"ADD.S"); type=FLOAT; break;
8375 case 0x01: strcpy(insn[i],"SUB.S"); type=FLOAT; break;
8376 case 0x02: strcpy(insn[i],"MUL.S"); type=FLOAT; break;
8377 case 0x03: strcpy(insn[i],"DIV.S"); type=FLOAT; break;
8378 case 0x04: strcpy(insn[i],"SQRT.S"); type=FLOAT; break;
8379 case 0x05: strcpy(insn[i],"ABS.S"); type=FLOAT; break;
8380 case 0x06: strcpy(insn[i],"MOV.S"); type=FLOAT; break;
8381 case 0x07: strcpy(insn[i],"NEG.S"); type=FLOAT; break;
8382 case 0x08: strcpy(insn[i],"ROUND.L.S"); type=FCONV; break;
8383 case 0x09: strcpy(insn[i],"TRUNC.L.S"); type=FCONV; break;
8384 case 0x0A: strcpy(insn[i],"CEIL.L.S"); type=FCONV; break;
8385 case 0x0B: strcpy(insn[i],"FLOOR.L.S"); type=FCONV; break;
8386 case 0x0C: strcpy(insn[i],"ROUND.W.S"); type=FCONV; break;
8387 case 0x0D: strcpy(insn[i],"TRUNC.W.S"); type=FCONV; break;
8388 case 0x0E: strcpy(insn[i],"CEIL.W.S"); type=FCONV; break;
8389 case 0x0F: strcpy(insn[i],"FLOOR.W.S"); type=FCONV; break;
8390 case 0x21: strcpy(insn[i],"CVT.D.S"); type=FCONV; break;
8391 case 0x24: strcpy(insn[i],"CVT.W.S"); type=FCONV; break;
8392 case 0x25: strcpy(insn[i],"CVT.L.S"); type=FCONV; break;
8393 case 0x30: strcpy(insn[i],"C.F.S"); type=FCOMP; break;
8394 case 0x31: strcpy(insn[i],"C.UN.S"); type=FCOMP; break;
8395 case 0x32: strcpy(insn[i],"C.EQ.S"); type=FCOMP; break;
8396 case 0x33: strcpy(insn[i],"C.UEQ.S"); type=FCOMP; break;
8397 case 0x34: strcpy(insn[i],"C.OLT.S"); type=FCOMP; break;
8398 case 0x35: strcpy(insn[i],"C.ULT.S"); type=FCOMP; break;
8399 case 0x36: strcpy(insn[i],"C.OLE.S"); type=FCOMP; break;
8400 case 0x37: strcpy(insn[i],"C.ULE.S"); type=FCOMP; break;
8401 case 0x38: strcpy(insn[i],"C.SF.S"); type=FCOMP; break;
8402 case 0x39: strcpy(insn[i],"C.NGLE.S"); type=FCOMP; break;
8403 case 0x3A: strcpy(insn[i],"C.SEQ.S"); type=FCOMP; break;
8404 case 0x3B: strcpy(insn[i],"C.NGL.S"); type=FCOMP; break;
8405 case 0x3C: strcpy(insn[i],"C.LT.S"); type=FCOMP; break;
8406 case 0x3D: strcpy(insn[i],"C.NGE.S"); type=FCOMP; break;
8407 case 0x3E: strcpy(insn[i],"C.LE.S"); type=FCOMP; break;
8408 case 0x3F: strcpy(insn[i],"C.NGT.S"); type=FCOMP; break;
8409 }
8410 break;
8411 case 0x11: strcpy(insn[i],"C1.D"); type=NI;
8412 switch(source[i]&0x3f)
8413 {
8414 case 0x00: strcpy(insn[i],"ADD.D"); type=FLOAT; break;
8415 case 0x01: strcpy(insn[i],"SUB.D"); type=FLOAT; break;
8416 case 0x02: strcpy(insn[i],"MUL.D"); type=FLOAT; break;
8417 case 0x03: strcpy(insn[i],"DIV.D"); type=FLOAT; break;
8418 case 0x04: strcpy(insn[i],"SQRT.D"); type=FLOAT; break;
8419 case 0x05: strcpy(insn[i],"ABS.D"); type=FLOAT; break;
8420 case 0x06: strcpy(insn[i],"MOV.D"); type=FLOAT; break;
8421 case 0x07: strcpy(insn[i],"NEG.D"); type=FLOAT; break;
8422 case 0x08: strcpy(insn[i],"ROUND.L.D"); type=FCONV; break;
8423 case 0x09: strcpy(insn[i],"TRUNC.L.D"); type=FCONV; break;
8424 case 0x0A: strcpy(insn[i],"CEIL.L.D"); type=FCONV; break;
8425 case 0x0B: strcpy(insn[i],"FLOOR.L.D"); type=FCONV; break;
8426 case 0x0C: strcpy(insn[i],"ROUND.W.D"); type=FCONV; break;
8427 case 0x0D: strcpy(insn[i],"TRUNC.W.D"); type=FCONV; break;
8428 case 0x0E: strcpy(insn[i],"CEIL.W.D"); type=FCONV; break;
8429 case 0x0F: strcpy(insn[i],"FLOOR.W.D"); type=FCONV; break;
8430 case 0x20: strcpy(insn[i],"CVT.S.D"); type=FCONV; break;
8431 case 0x24: strcpy(insn[i],"CVT.W.D"); type=FCONV; break;
8432 case 0x25: strcpy(insn[i],"CVT.L.D"); type=FCONV; break;
8433 case 0x30: strcpy(insn[i],"C.F.D"); type=FCOMP; break;
8434 case 0x31: strcpy(insn[i],"C.UN.D"); type=FCOMP; break;
8435 case 0x32: strcpy(insn[i],"C.EQ.D"); type=FCOMP; break;
8436 case 0x33: strcpy(insn[i],"C.UEQ.D"); type=FCOMP; break;
8437 case 0x34: strcpy(insn[i],"C.OLT.D"); type=FCOMP; break;
8438 case 0x35: strcpy(insn[i],"C.ULT.D"); type=FCOMP; break;
8439 case 0x36: strcpy(insn[i],"C.OLE.D"); type=FCOMP; break;
8440 case 0x37: strcpy(insn[i],"C.ULE.D"); type=FCOMP; break;
8441 case 0x38: strcpy(insn[i],"C.SF.D"); type=FCOMP; break;
8442 case 0x39: strcpy(insn[i],"C.NGLE.D"); type=FCOMP; break;
8443 case 0x3A: strcpy(insn[i],"C.SEQ.D"); type=FCOMP; break;
8444 case 0x3B: strcpy(insn[i],"C.NGL.D"); type=FCOMP; break;
8445 case 0x3C: strcpy(insn[i],"C.LT.D"); type=FCOMP; break;
8446 case 0x3D: strcpy(insn[i],"C.NGE.D"); type=FCOMP; break;
8447 case 0x3E: strcpy(insn[i],"C.LE.D"); type=FCOMP; break;
8448 case 0x3F: strcpy(insn[i],"C.NGT.D"); type=FCOMP; break;
8449 }
8450 break;
8451 case 0x14: strcpy(insn[i],"C1.W"); type=NI;
8452 switch(source[i]&0x3f)
8453 {
8454 case 0x20: strcpy(insn[i],"CVT.S.W"); type=FCONV; break;
8455 case 0x21: strcpy(insn[i],"CVT.D.W"); type=FCONV; break;
8456 }
8457 break;
8458 case 0x15: strcpy(insn[i],"C1.L"); type=NI;
8459 switch(source[i]&0x3f)
8460 {
8461 case 0x20: strcpy(insn[i],"CVT.S.L"); type=FCONV; break;
8462 case 0x21: strcpy(insn[i],"CVT.D.L"); type=FCONV; break;
8463 }
8464 break;
8465 }
8466 break;
909168d6 8467#ifndef FORCE32
57871462 8468 case 0x14: strcpy(insn[i],"BEQL"); type=CJUMP; break;
8469 case 0x15: strcpy(insn[i],"BNEL"); type=CJUMP; break;
8470 case 0x16: strcpy(insn[i],"BLEZL"); type=CJUMP; break;
8471 case 0x17: strcpy(insn[i],"BGTZL"); type=CJUMP; break;
8472 case 0x18: strcpy(insn[i],"DADDI"); type=IMM16; break;
8473 case 0x19: strcpy(insn[i],"DADDIU"); type=IMM16; break;
8474 case 0x1A: strcpy(insn[i],"LDL"); type=LOADLR; break;
8475 case 0x1B: strcpy(insn[i],"LDR"); type=LOADLR; break;
996cc15d 8476#endif
57871462 8477 case 0x20: strcpy(insn[i],"LB"); type=LOAD; break;
8478 case 0x21: strcpy(insn[i],"LH"); type=LOAD; break;
8479 case 0x22: strcpy(insn[i],"LWL"); type=LOADLR; break;
8480 case 0x23: strcpy(insn[i],"LW"); type=LOAD; break;
8481 case 0x24: strcpy(insn[i],"LBU"); type=LOAD; break;
8482 case 0x25: strcpy(insn[i],"LHU"); type=LOAD; break;
8483 case 0x26: strcpy(insn[i],"LWR"); type=LOADLR; break;
64bd6f82 8484#ifndef FORCE32
57871462 8485 case 0x27: strcpy(insn[i],"LWU"); type=LOAD; break;
64bd6f82 8486#endif
57871462 8487 case 0x28: strcpy(insn[i],"SB"); type=STORE; break;
8488 case 0x29: strcpy(insn[i],"SH"); type=STORE; break;
8489 case 0x2A: strcpy(insn[i],"SWL"); type=STORELR; break;
8490 case 0x2B: strcpy(insn[i],"SW"); type=STORE; break;
996cc15d 8491#ifndef FORCE32
57871462 8492 case 0x2C: strcpy(insn[i],"SDL"); type=STORELR; break;
8493 case 0x2D: strcpy(insn[i],"SDR"); type=STORELR; break;
996cc15d 8494#endif
57871462 8495 case 0x2E: strcpy(insn[i],"SWR"); type=STORELR; break;
8496 case 0x2F: strcpy(insn[i],"CACHE"); type=NOP; break;
8497 case 0x30: strcpy(insn[i],"LL"); type=NI; break;
8498 case 0x31: strcpy(insn[i],"LWC1"); type=C1LS; break;
996cc15d 8499#ifndef FORCE32
57871462 8500 case 0x34: strcpy(insn[i],"LLD"); type=NI; break;
8501 case 0x35: strcpy(insn[i],"LDC1"); type=C1LS; break;
8502 case 0x37: strcpy(insn[i],"LD"); type=LOAD; break;
996cc15d 8503#endif
57871462 8504 case 0x38: strcpy(insn[i],"SC"); type=NI; break;
8505 case 0x39: strcpy(insn[i],"SWC1"); type=C1LS; break;
996cc15d 8506#ifndef FORCE32
57871462 8507 case 0x3C: strcpy(insn[i],"SCD"); type=NI; break;
8508 case 0x3D: strcpy(insn[i],"SDC1"); type=C1LS; break;
8509 case 0x3F: strcpy(insn[i],"SD"); type=STORE; break;
996cc15d 8510#endif
b9b61529 8511#ifdef PCSX
8512 case 0x12: strcpy(insn[i],"COP2"); type=NI;
8513 op2=(source[i]>>21)&0x1f;
bedfea38 8514 //if (op2 & 0x10) {
8515 if (source[i]&0x3f) { // use this hack to support old savestates with patched gte insns
c7abc864 8516 if (gte_handlers[source[i]&0x3f]!=NULL) {
bedfea38 8517 if (gte_regnames[source[i]&0x3f]!=NULL)
8518 strcpy(insn[i],gte_regnames[source[i]&0x3f]);
8519 else
8520 snprintf(insn[i], sizeof(insn[i]), "COP2 %x", source[i]&0x3f);
c7abc864 8521 type=C2OP;
8522 }
8523 }
8524 else switch(op2)
b9b61529 8525 {
8526 case 0x00: strcpy(insn[i],"MFC2"); type=COP2; break;
8527 case 0x02: strcpy(insn[i],"CFC2"); type=COP2; break;
8528 case 0x04: strcpy(insn[i],"MTC2"); type=COP2; break;
8529 case 0x06: strcpy(insn[i],"CTC2"); type=COP2; break;
b9b61529 8530 }
8531 break;
8532 case 0x32: strcpy(insn[i],"LWC2"); type=C2LS; break;
8533 case 0x3A: strcpy(insn[i],"SWC2"); type=C2LS; break;
8534 case 0x3B: strcpy(insn[i],"HLECALL"); type=HLECALL; break;
8535#endif
90ae6d4e 8536 default: strcpy(insn[i],"???"); type=NI;
75dec299 8537 printf("NI %08x @%08x (%08x)\n", source[i], addr + i*4, addr);
90ae6d4e 8538 break;
57871462 8539 }
8540 itype[i]=type;
8541 opcode2[i]=op2;
8542 /* Get registers/immediates */
8543 lt1[i]=0;
8544 us1[i]=0;
8545 us2[i]=0;
8546 dep1[i]=0;
8547 dep2[i]=0;
bedfea38 8548 gte_rs[i]=gte_rt[i]=0;
57871462 8549 switch(type) {
8550 case LOAD:
8551 rs1[i]=(source[i]>>21)&0x1f;
8552 rs2[i]=0;
8553 rt1[i]=(source[i]>>16)&0x1f;
8554 rt2[i]=0;
8555 imm[i]=(short)source[i];
8556 break;
8557 case STORE:
8558 case STORELR:
8559 rs1[i]=(source[i]>>21)&0x1f;
8560 rs2[i]=(source[i]>>16)&0x1f;
8561 rt1[i]=0;
8562 rt2[i]=0;
8563 imm[i]=(short)source[i];
8564 if(op==0x2c||op==0x2d||op==0x3f) us1[i]=rs2[i]; // 64-bit SDL/SDR/SD
8565 break;
8566 case LOADLR:
8567 // LWL/LWR only load part of the register,
8568 // therefore the target register must be treated as a source too
8569 rs1[i]=(source[i]>>21)&0x1f;
8570 rs2[i]=(source[i]>>16)&0x1f;
8571 rt1[i]=(source[i]>>16)&0x1f;
8572 rt2[i]=0;
8573 imm[i]=(short)source[i];
8574 if(op==0x1a||op==0x1b) us1[i]=rs2[i]; // LDR/LDL
8575 if(op==0x26) dep1[i]=rt1[i]; // LWR
8576 break;
8577 case IMM16:
8578 if (op==0x0f) rs1[i]=0; // LUI instruction has no source register
8579 else rs1[i]=(source[i]>>21)&0x1f;
8580 rs2[i]=0;
8581 rt1[i]=(source[i]>>16)&0x1f;
8582 rt2[i]=0;
8583 if(op>=0x0c&&op<=0x0e) { // ANDI/ORI/XORI
8584 imm[i]=(unsigned short)source[i];
8585 }else{
8586 imm[i]=(short)source[i];
8587 }
8588 if(op==0x18||op==0x19) us1[i]=rs1[i]; // DADDI/DADDIU
8589 if(op==0x0a||op==0x0b) us1[i]=rs1[i]; // SLTI/SLTIU
8590 if(op==0x0d||op==0x0e) dep1[i]=rs1[i]; // ORI/XORI
8591 break;
8592 case UJUMP:
8593 rs1[i]=0;
8594 rs2[i]=0;
8595 rt1[i]=0;
8596 rt2[i]=0;
8597 // The JAL instruction writes to r31.
8598 if (op&1) {
8599 rt1[i]=31;
8600 }
8601 rs2[i]=CCREG;
8602 break;
8603 case RJUMP:
8604 rs1[i]=(source[i]>>21)&0x1f;
8605 rs2[i]=0;
8606 rt1[i]=0;
8607 rt2[i]=0;
5067f341 8608 // The JALR instruction writes to rd.
57871462 8609 if (op2&1) {
5067f341 8610 rt1[i]=(source[i]>>11)&0x1f;
57871462 8611 }
8612 rs2[i]=CCREG;
8613 break;
8614 case CJUMP:
8615 rs1[i]=(source[i]>>21)&0x1f;
8616 rs2[i]=(source[i]>>16)&0x1f;
8617 rt1[i]=0;
8618 rt2[i]=0;
8619 if(op&2) { // BGTZ/BLEZ
8620 rs2[i]=0;
8621 }
8622 us1[i]=rs1[i];
8623 us2[i]=rs2[i];
8624 likely[i]=op>>4;
8625 break;
8626 case SJUMP:
8627 rs1[i]=(source[i]>>21)&0x1f;
8628 rs2[i]=CCREG;
8629 rt1[i]=0;
8630 rt2[i]=0;
8631 us1[i]=rs1[i];
8632 if(op2&0x10) { // BxxAL
8633 rt1[i]=31;
8634 // NOTE: If the branch is not taken, r31 is still overwritten
8635 }
8636 likely[i]=(op2&2)>>1;
8637 break;
8638 case FJUMP:
8639 rs1[i]=FSREG;
8640 rs2[i]=CSREG;
8641 rt1[i]=0;
8642 rt2[i]=0;
8643 likely[i]=((source[i])>>17)&1;
8644 break;
8645 case ALU:
8646 rs1[i]=(source[i]>>21)&0x1f; // source
8647 rs2[i]=(source[i]>>16)&0x1f; // subtract amount
8648 rt1[i]=(source[i]>>11)&0x1f; // destination
8649 rt2[i]=0;
8650 if(op2==0x2a||op2==0x2b) { // SLT/SLTU
8651 us1[i]=rs1[i];us2[i]=rs2[i];
8652 }
8653 else if(op2>=0x24&&op2<=0x27) { // AND/OR/XOR/NOR
8654 dep1[i]=rs1[i];dep2[i]=rs2[i];
8655 }
8656 else if(op2>=0x2c&&op2<=0x2f) { // DADD/DSUB
8657 dep1[i]=rs1[i];dep2[i]=rs2[i];
8658 }
8659 break;
8660 case MULTDIV:
8661 rs1[i]=(source[i]>>21)&0x1f; // source
8662 rs2[i]=(source[i]>>16)&0x1f; // divisor
8663 rt1[i]=HIREG;
8664 rt2[i]=LOREG;
8665 if (op2>=0x1c&&op2<=0x1f) { // DMULT/DMULTU/DDIV/DDIVU
8666 us1[i]=rs1[i];us2[i]=rs2[i];
8667 }
8668 break;
8669 case MOV:
8670 rs1[i]=0;
8671 rs2[i]=0;
8672 rt1[i]=0;
8673 rt2[i]=0;
8674 if(op2==0x10) rs1[i]=HIREG; // MFHI
8675 if(op2==0x11) rt1[i]=HIREG; // MTHI
8676 if(op2==0x12) rs1[i]=LOREG; // MFLO
8677 if(op2==0x13) rt1[i]=LOREG; // MTLO
8678 if((op2&0x1d)==0x10) rt1[i]=(source[i]>>11)&0x1f; // MFxx
8679 if((op2&0x1d)==0x11) rs1[i]=(source[i]>>21)&0x1f; // MTxx
8680 dep1[i]=rs1[i];
8681 break;
8682 case SHIFT:
8683 rs1[i]=(source[i]>>16)&0x1f; // target of shift
8684 rs2[i]=(source[i]>>21)&0x1f; // shift amount
8685 rt1[i]=(source[i]>>11)&0x1f; // destination
8686 rt2[i]=0;
8687 // DSLLV/DSRLV/DSRAV are 64-bit
8688 if(op2>=0x14&&op2<=0x17) us1[i]=rs1[i];
8689 break;
8690 case SHIFTIMM:
8691 rs1[i]=(source[i]>>16)&0x1f;
8692 rs2[i]=0;
8693 rt1[i]=(source[i]>>11)&0x1f;
8694 rt2[i]=0;
8695 imm[i]=(source[i]>>6)&0x1f;
8696 // DSxx32 instructions
8697 if(op2>=0x3c) imm[i]|=0x20;
8698 // DSLL/DSRL/DSRA/DSRA32/DSRL32 but not DSLL32 require 64-bit source
8699 if(op2>=0x38&&op2!=0x3c) us1[i]=rs1[i];
8700 break;
8701 case COP0:
8702 rs1[i]=0;
8703 rs2[i]=0;
8704 rt1[i]=0;
8705 rt2[i]=0;
8706 if(op2==0) rt1[i]=(source[i]>>16)&0x1F; // MFC0
8707 if(op2==4) rs1[i]=(source[i]>>16)&0x1F; // MTC0
8708 if(op2==4&&((source[i]>>11)&0x1f)==12) rt2[i]=CSREG; // Status
8709 if(op2==16) if((source[i]&0x3f)==0x18) rs2[i]=CCREG; // ERET
8710 break;
8711 case COP1:
8712 rs1[i]=0;
8713 rs2[i]=0;
8714 rt1[i]=0;
8715 rt2[i]=0;
8716 if(op2<3) rt1[i]=(source[i]>>16)&0x1F; // MFC1/DMFC1/CFC1
8717 if(op2>3) rs1[i]=(source[i]>>16)&0x1F; // MTC1/DMTC1/CTC1
8718 if(op2==5) us1[i]=rs1[i]; // DMTC1
8719 rs2[i]=CSREG;
8720 break;
bedfea38 8721 case COP2:
8722 rs1[i]=0;
8723 rs2[i]=0;
8724 rt1[i]=0;
8725 rt2[i]=0;
8726 if(op2<3) rt1[i]=(source[i]>>16)&0x1F; // MFC2/CFC2
8727 if(op2>3) rs1[i]=(source[i]>>16)&0x1F; // MTC2/CTC2
8728 rs2[i]=CSREG;
8729 int gr=(source[i]>>11)&0x1F;
8730 switch(op2)
8731 {
8732 case 0x00: gte_rs[i]=1ll<<gr; break; // MFC2
8733 case 0x04: gte_rt[i]=1ll<<gr; break; // MTC2
0ff8c62c 8734 case 0x02: gte_rs[i]=1ll<<(gr+32); break; // CFC2
bedfea38 8735 case 0x06: gte_rt[i]=1ll<<(gr+32); break; // CTC2
8736 }
8737 break;
57871462 8738 case C1LS:
8739 rs1[i]=(source[i]>>21)&0x1F;
8740 rs2[i]=CSREG;
8741 rt1[i]=0;
8742 rt2[i]=0;
8743 imm[i]=(short)source[i];
8744 break;
b9b61529 8745 case C2LS:
8746 rs1[i]=(source[i]>>21)&0x1F;
8747 rs2[i]=0;
8748 rt1[i]=0;
8749 rt2[i]=0;
8750 imm[i]=(short)source[i];
bedfea38 8751 if(op==0x32) gte_rt[i]=1ll<<((source[i]>>16)&0x1F); // LWC2
8752 else gte_rs[i]=1ll<<((source[i]>>16)&0x1F); // SWC2
8753 break;
8754 case C2OP:
8755 rs1[i]=0;
8756 rs2[i]=0;
8757 rt1[i]=0;
8758 rt2[i]=0;
2167bef6 8759 gte_rs[i]=gte_reg_reads[source[i]&0x3f];
8760 gte_rt[i]=gte_reg_writes[source[i]&0x3f];
8761 gte_rt[i]|=1ll<<63; // every op changes flags
587a5b1c 8762 if((source[i]&0x3f)==GTE_MVMVA) {
8763 int v = (source[i] >> 15) & 3;
8764 gte_rs[i]&=~0xe3fll;
8765 if(v==3) gte_rs[i]|=0xe00ll;
8766 else gte_rs[i]|=3ll<<(v*2);
8767 }
b9b61529 8768 break;
57871462 8769 case FLOAT:
8770 case FCONV:
8771 rs1[i]=0;
8772 rs2[i]=CSREG;
8773 rt1[i]=0;
8774 rt2[i]=0;
8775 break;
8776 case FCOMP:
8777 rs1[i]=FSREG;
8778 rs2[i]=CSREG;
8779 rt1[i]=FSREG;
8780 rt2[i]=0;
8781 break;
8782 case SYSCALL:
7139f3c8 8783 case HLECALL:
1e973cb0 8784 case INTCALL:
57871462 8785 rs1[i]=CCREG;
8786 rs2[i]=0;
8787 rt1[i]=0;
8788 rt2[i]=0;
8789 break;
8790 default:
8791 rs1[i]=0;
8792 rs2[i]=0;
8793 rt1[i]=0;
8794 rt2[i]=0;
8795 }
8796 /* Calculate branch target addresses */
8797 if(type==UJUMP)
8798 ba[i]=((start+i*4+4)&0xF0000000)|(((unsigned int)source[i]<<6)>>4);
8799 else if(type==CJUMP&&rs1[i]==rs2[i]&&(op&1))
8800 ba[i]=start+i*4+8; // Ignore never taken branch
8801 else if(type==SJUMP&&rs1[i]==0&&!(op2&1))
8802 ba[i]=start+i*4+8; // Ignore never taken branch
8803 else if(type==CJUMP||type==SJUMP||type==FJUMP)
8804 ba[i]=start+i*4+4+((signed int)((unsigned int)source[i]<<16)>>14);
8805 else ba[i]=-1;
26869094 8806#ifdef PCSX
3e535354 8807 if(i>0&&(itype[i-1]==RJUMP||itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP)) {
8808 int do_in_intrp=0;
8809 // branch in delay slot?
8810 if(type==RJUMP||type==UJUMP||type==CJUMP||type==SJUMP||type==FJUMP) {
8811 // don't handle first branch and call interpreter if it's hit
8812 printf("branch in delay slot @%08x (%08x)\n", addr + i*4, addr);
8813 do_in_intrp=1;
8814 }
8815 // basic load delay detection
8816 else if((type==LOAD||type==LOADLR||type==COP0||type==COP2||type==C2LS)&&rt1[i]!=0) {
8817 int t=(ba[i-1]-start)/4;
8818 if(0 <= t && t < i &&(rt1[i]==rs1[t]||rt1[i]==rs2[t])&&itype[t]!=CJUMP&&itype[t]!=SJUMP) {
8819 // jump target wants DS result - potential load delay effect
8820 printf("load delay @%08x (%08x)\n", addr + i*4, addr);
8821 do_in_intrp=1;
8822 bt[t+1]=1; // expected return from interpreter
8823 }
8824 else if(i>=2&&rt1[i-2]==2&&rt1[i]==2&&rs1[i]!=2&&rs2[i]!=2&&rs1[i-1]!=2&&rs2[i-1]!=2&&
8825 !(i>=3&&(itype[i-3]==RJUMP||itype[i-3]==UJUMP||itype[i-3]==CJUMP||itype[i-3]==SJUMP))) {
8826 // v0 overwrite like this is a sign of trouble, bail out
8827 printf("v0 overwrite @%08x (%08x)\n", addr + i*4, addr);
8828 do_in_intrp=1;
8829 }
8830 }
3e535354 8831 if(do_in_intrp) {
8832 rs1[i-1]=CCREG;
8833 rs2[i-1]=rt1[i-1]=rt2[i-1]=0;
26869094 8834 ba[i-1]=-1;
8835 itype[i-1]=INTCALL;
8836 done=2;
3e535354 8837 i--; // don't compile the DS
26869094 8838 }
3e535354 8839 }
26869094 8840#endif
3e535354 8841 /* Is this the end of the block? */
8842 if(i>0&&(itype[i-1]==UJUMP||itype[i-1]==RJUMP||(source[i-1]>>16)==0x1000)) {
5067f341 8843 if(rt1[i-1]==0) { // Continue past subroutine call (JAL)
1e973cb0 8844 done=2;
57871462 8845 }
8846 else {
8847 if(stop_after_jal) done=1;
8848 // Stop on BREAK
8849 if((source[i+1]&0xfc00003f)==0x0d) done=1;
8850 }
8851 // Don't recompile stuff that's already compiled
8852 if(check_addr(start+i*4+4)) done=1;
8853 // Don't get too close to the limit
8854 if(i>MAXBLOCK/2) done=1;
8855 }
75dec299 8856 if(itype[i]==SYSCALL&&stop_after_jal) done=1;
1e973cb0 8857 if(itype[i]==HLECALL||itype[i]==INTCALL) done=2;
8858 if(done==2) {
8859 // Does the block continue due to a branch?
8860 for(j=i-1;j>=0;j--)
8861 {
2a706964 8862 if(ba[j]==start+i*4) done=j=0; // Branch into delay slot
1e973cb0 8863 if(ba[j]==start+i*4+4) done=j=0;
8864 if(ba[j]==start+i*4+8) done=j=0;
8865 }
8866 }
75dec299 8867 //assert(i<MAXBLOCK-1);
57871462 8868 if(start+i*4==pagelimit-4) done=1;
8869 assert(start+i*4<pagelimit);
8870 if (i==MAXBLOCK-1) done=1;
8871 // Stop if we're compiling junk
8872 if(itype[i]==NI&&opcode[i]==0x11) {
8873 done=stop_after_jal=1;
8874 printf("Disabled speculative precompilation\n");
8875 }
8876 }
8877 slen=i;
8878 if(itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==RJUMP||itype[i-1]==FJUMP) {
8879 if(start+i*4==pagelimit) {
8880 itype[i-1]=SPAN;
8881 }
8882 }
8883 assert(slen>0);
8884
8885 /* Pass 2 - Register dependencies and branch targets */
8886
8887 unneeded_registers(0,slen-1,0);
8888
8889 /* Pass 3 - Register allocation */
8890
8891 struct regstat current; // Current register allocations/status
8892 current.is32=1;
8893 current.dirty=0;
8894 current.u=unneeded_reg[0];
8895 current.uu=unneeded_reg_upper[0];
8896 clear_all_regs(current.regmap);
8897 alloc_reg(&current,0,CCREG);
8898 dirty_reg(&current,CCREG);
8899 current.isconst=0;
8900 current.wasconst=0;
27727b63 8901 current.waswritten=0;
57871462 8902 int ds=0;
8903 int cc=0;
5194fb95 8904 int hr=-1;
6ebf4adf 8905
8906#ifndef FORCE32
57871462 8907 provisional_32bit();
6ebf4adf 8908#endif
57871462 8909 if((u_int)addr&1) {
8910 // First instruction is delay slot
8911 cc=-1;
8912 bt[1]=1;
8913 ds=1;
8914 unneeded_reg[0]=1;
8915 unneeded_reg_upper[0]=1;
8916 current.regmap[HOST_BTREG]=BTREG;
8917 }
8918
8919 for(i=0;i<slen;i++)
8920 {
8921 if(bt[i])
8922 {
8923 int hr;
8924 for(hr=0;hr<HOST_REGS;hr++)
8925 {
8926 // Is this really necessary?
8927 if(current.regmap[hr]==0) current.regmap[hr]=-1;
8928 }
8929 current.isconst=0;
27727b63 8930 current.waswritten=0;
57871462 8931 }
8932 if(i>1)
8933 {
8934 if((opcode[i-2]&0x2f)==0x05) // BNE/BNEL
8935 {
8936 if(rs1[i-2]==0||rs2[i-2]==0)
8937 {
8938 if(rs1[i-2]) {
8939 current.is32|=1LL<<rs1[i-2];
8940 int hr=get_reg(current.regmap,rs1[i-2]|64);
8941 if(hr>=0) current.regmap[hr]=-1;
8942 }
8943 if(rs2[i-2]) {
8944 current.is32|=1LL<<rs2[i-2];
8945 int hr=get_reg(current.regmap,rs2[i-2]|64);
8946 if(hr>=0) current.regmap[hr]=-1;
8947 }
8948 }
8949 }
8950 }
6ebf4adf 8951#ifndef FORCE32
57871462 8952 // If something jumps here with 64-bit values
8953 // then promote those registers to 64 bits
8954 if(bt[i])
8955 {
8956 uint64_t temp_is32=current.is32;
8957 for(j=i-1;j>=0;j--)
8958 {
8959 if(ba[j]==start+i*4)
8960 temp_is32&=branch_regs[j].is32;
8961 }
8962 for(j=i;j<slen;j++)
8963 {
8964 if(ba[j]==start+i*4)
8965 //temp_is32=1;
8966 temp_is32&=p32[j];
8967 }
8968 if(temp_is32!=current.is32) {
8969 //printf("dumping 32-bit regs (%x)\n",start+i*4);
311301dc 8970 #ifndef DESTRUCTIVE_WRITEBACK
8971 if(ds)
8972 #endif
57871462 8973 for(hr=0;hr<HOST_REGS;hr++)
8974 {
8975 int r=current.regmap[hr];
8976 if(r>0&&r<64)
8977 {
8978 if((current.dirty>>hr)&((current.is32&~temp_is32)>>r)&1) {
8979 temp_is32|=1LL<<r;
8980 //printf("restore %d\n",r);
8981 }
8982 }
8983 }
57871462 8984 current.is32=temp_is32;
8985 }
8986 }
6ebf4adf 8987#else
24385cae 8988 current.is32=-1LL;
8989#endif
8990
57871462 8991 memcpy(regmap_pre[i],current.regmap,sizeof(current.regmap));
8992 regs[i].wasconst=current.isconst;
8993 regs[i].was32=current.is32;
8994 regs[i].wasdirty=current.dirty;
8575a877 8995 regs[i].loadedconst=0;
6ebf4adf 8996 #if defined(DESTRUCTIVE_WRITEBACK) && !defined(FORCE32)
57871462 8997 // To change a dirty register from 32 to 64 bits, we must write
8998 // it out during the previous cycle (for branches, 2 cycles)
8999 if(i<slen-1&&bt[i+1]&&itype[i-1]!=UJUMP&&itype[i-1]!=CJUMP&&itype[i-1]!=SJUMP&&itype[i-1]!=RJUMP&&itype[i-1]!=FJUMP)
9000 {
9001 uint64_t temp_is32=current.is32;
9002 for(j=i-1;j>=0;j--)
9003 {
9004 if(ba[j]==start+i*4+4)
9005 temp_is32&=branch_regs[j].is32;
9006 }
9007 for(j=i;j<slen;j++)
9008 {
9009 if(ba[j]==start+i*4+4)
9010 //temp_is32=1;
9011 temp_is32&=p32[j];
9012 }
9013 if(temp_is32!=current.is32) {
9014 //printf("pre-dumping 32-bit regs (%x)\n",start+i*4);
9015 for(hr=0;hr<HOST_REGS;hr++)
9016 {
9017 int r=current.regmap[hr];
9018 if(r>0)
9019 {
9020 if((current.dirty>>hr)&((current.is32&~temp_is32)>>(r&63))&1) {
9021 if(itype[i]!=UJUMP&&itype[i]!=CJUMP&&itype[i]!=SJUMP&&itype[i]!=RJUMP&&itype[i]!=FJUMP)
9022 {
9023 if(rs1[i]!=(r&63)&&rs2[i]!=(r&63))
9024 {
9025 //printf("dump %d/r%d\n",hr,r);
9026 current.regmap[hr]=-1;
9027 if(get_reg(current.regmap,r|64)>=0)
9028 current.regmap[get_reg(current.regmap,r|64)]=-1;
9029 }
9030 }
9031 }
9032 }
9033 }
9034 }
9035 }
9036 else if(i<slen-2&&bt[i+2]&&(source[i-1]>>16)!=0x1000&&(itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP))
9037 {
9038 uint64_t temp_is32=current.is32;
9039 for(j=i-1;j>=0;j--)
9040 {
9041 if(ba[j]==start+i*4+8)
9042 temp_is32&=branch_regs[j].is32;
9043 }
9044 for(j=i;j<slen;j++)
9045 {
9046 if(ba[j]==start+i*4+8)
9047 //temp_is32=1;
9048 temp_is32&=p32[j];
9049 }
9050 if(temp_is32!=current.is32) {
9051 //printf("pre-dumping 32-bit regs (%x)\n",start+i*4);
9052 for(hr=0;hr<HOST_REGS;hr++)
9053 {
9054 int r=current.regmap[hr];
9055 if(r>0)
9056 {
9057 if((current.dirty>>hr)&((current.is32&~temp_is32)>>(r&63))&1) {
9058 if(rs1[i]!=(r&63)&&rs2[i]!=(r&63)&&rs1[i+1]!=(r&63)&&rs2[i+1]!=(r&63))
9059 {
9060 //printf("dump %d/r%d\n",hr,r);
9061 current.regmap[hr]=-1;
9062 if(get_reg(current.regmap,r|64)>=0)
9063 current.regmap[get_reg(current.regmap,r|64)]=-1;
9064 }
9065 }
9066 }
9067 }
9068 }
9069 }
9070 #endif
9071 if(itype[i]!=UJUMP&&itype[i]!=CJUMP&&itype[i]!=SJUMP&&itype[i]!=RJUMP&&itype[i]!=FJUMP) {
9072 if(i+1<slen) {
9073 current.u=unneeded_reg[i+1]&~((1LL<<rs1[i])|(1LL<<rs2[i]));
9074 current.uu=unneeded_reg_upper[i+1]&~((1LL<<us1[i])|(1LL<<us2[i]));
9075 if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
9076 current.u|=1;
9077 current.uu|=1;
9078 } else {
9079 current.u=1;
9080 current.uu=1;
9081 }
9082 } else {
9083 if(i+1<slen) {
9084 current.u=branch_unneeded_reg[i]&~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
9085 current.uu=branch_unneeded_reg_upper[i]&~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
9086 if((~current.uu>>rt1[i+1])&1) current.uu&=~((1LL<<dep1[i+1])|(1LL<<dep2[i+1]));
9087 current.u&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
9088 current.uu&=~((1LL<<us1[i])|(1LL<<us2[i]));
9089 current.u|=1;
9090 current.uu|=1;
9091 } else { printf("oops, branch at end of block with no delay slot\n");exit(1); }
9092 }
9093 is_ds[i]=ds;
9094 if(ds) {
9095 ds=0; // Skip delay slot, already allocated as part of branch
9096 // ...but we need to alloc it in case something jumps here
9097 if(i+1<slen) {
9098 current.u=branch_unneeded_reg[i-1]&unneeded_reg[i+1];
9099 current.uu=branch_unneeded_reg_upper[i-1]&unneeded_reg_upper[i+1];
9100 }else{
9101 current.u=branch_unneeded_reg[i-1];
9102 current.uu=branch_unneeded_reg_upper[i-1];
9103 }
9104 current.u&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
9105 current.uu&=~((1LL<<us1[i])|(1LL<<us2[i]));
9106 if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
9107 current.u|=1;
9108 current.uu|=1;
9109 struct regstat temp;
9110 memcpy(&temp,&current,sizeof(current));
9111 temp.wasdirty=temp.dirty;
9112 temp.was32=temp.is32;
9113 // TODO: Take into account unconditional branches, as below
9114 delayslot_alloc(&temp,i);
9115 memcpy(regs[i].regmap,temp.regmap,sizeof(temp.regmap));
9116 regs[i].wasdirty=temp.wasdirty;
9117 regs[i].was32=temp.was32;
9118 regs[i].dirty=temp.dirty;
9119 regs[i].is32=temp.is32;
9120 regs[i].isconst=0;
9121 regs[i].wasconst=0;
9122 current.isconst=0;
9123 // Create entry (branch target) regmap
9124 for(hr=0;hr<HOST_REGS;hr++)
9125 {
9126 int r=temp.regmap[hr];
9127 if(r>=0) {
9128 if(r!=regmap_pre[i][hr]) {
9129 regs[i].regmap_entry[hr]=-1;
9130 }
9131 else
9132 {
9133 if(r<64){
9134 if((current.u>>r)&1) {
9135 regs[i].regmap_entry[hr]=-1;
9136 regs[i].regmap[hr]=-1;
9137 //Don't clear regs in the delay slot as the branch might need them
9138 //current.regmap[hr]=-1;
9139 }else
9140 regs[i].regmap_entry[hr]=r;
9141 }
9142 else {
9143 if((current.uu>>(r&63))&1) {
9144 regs[i].regmap_entry[hr]=-1;
9145 regs[i].regmap[hr]=-1;
9146 //Don't clear regs in the delay slot as the branch might need them
9147 //current.regmap[hr]=-1;
9148 }else
9149 regs[i].regmap_entry[hr]=r;
9150 }
9151 }
9152 } else {
9153 // First instruction expects CCREG to be allocated
9154 if(i==0&&hr==HOST_CCREG)
9155 regs[i].regmap_entry[hr]=CCREG;
9156 else
9157 regs[i].regmap_entry[hr]=-1;
9158 }
9159 }
9160 }
9161 else { // Not delay slot
9162 switch(itype[i]) {
9163 case UJUMP:
9164 //current.isconst=0; // DEBUG
9165 //current.wasconst=0; // DEBUG
9166 //regs[i].wasconst=0; // DEBUG
9167 clear_const(&current,rt1[i]);
9168 alloc_cc(&current,i);
9169 dirty_reg(&current,CCREG);
9170 if (rt1[i]==31) {
9171 alloc_reg(&current,i,31);
9172 dirty_reg(&current,31);
4ef8f67d 9173 //assert(rs1[i+1]!=31&&rs2[i+1]!=31);
9174 //assert(rt1[i+1]!=rt1[i]);
57871462 9175 #ifdef REG_PREFETCH
9176 alloc_reg(&current,i,PTEMP);
9177 #endif
9178 //current.is32|=1LL<<rt1[i];
9179 }
269bb29a 9180 ooo[i]=1;
9181 delayslot_alloc(&current,i+1);
57871462 9182 //current.isconst=0; // DEBUG
9183 ds=1;
9184 //printf("i=%d, isconst=%x\n",i,current.isconst);
9185 break;
9186 case RJUMP:
9187 //current.isconst=0;
9188 //current.wasconst=0;
9189 //regs[i].wasconst=0;
9190 clear_const(&current,rs1[i]);
9191 clear_const(&current,rt1[i]);
9192 alloc_cc(&current,i);
9193 dirty_reg(&current,CCREG);
9194 if(rs1[i]!=rt1[i+1]&&rs1[i]!=rt2[i+1]) {
9195 alloc_reg(&current,i,rs1[i]);
5067f341 9196 if (rt1[i]!=0) {
9197 alloc_reg(&current,i,rt1[i]);
9198 dirty_reg(&current,rt1[i]);
68b3faee 9199 assert(rs1[i+1]!=rt1[i]&&rs2[i+1]!=rt1[i]);
076655d1 9200 assert(rt1[i+1]!=rt1[i]);
57871462 9201 #ifdef REG_PREFETCH
9202 alloc_reg(&current,i,PTEMP);
9203 #endif
9204 }
9205 #ifdef USE_MINI_HT
9206 if(rs1[i]==31) { // JALR
9207 alloc_reg(&current,i,RHASH);
9208 #ifndef HOST_IMM_ADDR32
9209 alloc_reg(&current,i,RHTBL);
9210 #endif
9211 }
9212 #endif
9213 delayslot_alloc(&current,i+1);
9214 } else {
9215 // The delay slot overwrites our source register,
9216 // allocate a temporary register to hold the old value.
9217 current.isconst=0;
9218 current.wasconst=0;
9219 regs[i].wasconst=0;
9220 delayslot_alloc(&current,i+1);
9221 current.isconst=0;
9222 alloc_reg(&current,i,RTEMP);
9223 }
9224 //current.isconst=0; // DEBUG
e1190b87 9225 ooo[i]=1;
57871462 9226 ds=1;
9227 break;
9228 case CJUMP:
9229 //current.isconst=0;
9230 //current.wasconst=0;
9231 //regs[i].wasconst=0;
9232 clear_const(&current,rs1[i]);
9233 clear_const(&current,rs2[i]);
9234 if((opcode[i]&0x3E)==4) // BEQ/BNE
9235 {
9236 alloc_cc(&current,i);
9237 dirty_reg(&current,CCREG);
9238 if(rs1[i]) alloc_reg(&current,i,rs1[i]);
9239 if(rs2[i]) alloc_reg(&current,i,rs2[i]);
9240 if(!((current.is32>>rs1[i])&(current.is32>>rs2[i])&1))
9241 {
9242 if(rs1[i]) alloc_reg64(&current,i,rs1[i]);
9243 if(rs2[i]) alloc_reg64(&current,i,rs2[i]);
9244 }
9245 if((rs1[i]&&(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1]))||
9246 (rs2[i]&&(rs2[i]==rt1[i+1]||rs2[i]==rt2[i+1]))) {
9247 // The delay slot overwrites one of our conditions.
9248 // Allocate the branch condition registers instead.
57871462 9249 current.isconst=0;
9250 current.wasconst=0;
9251 regs[i].wasconst=0;
9252 if(rs1[i]) alloc_reg(&current,i,rs1[i]);
9253 if(rs2[i]) alloc_reg(&current,i,rs2[i]);
9254 if(!((current.is32>>rs1[i])&(current.is32>>rs2[i])&1))
9255 {
9256 if(rs1[i]) alloc_reg64(&current,i,rs1[i]);
9257 if(rs2[i]) alloc_reg64(&current,i,rs2[i]);
9258 }
9259 }
e1190b87 9260 else
9261 {
9262 ooo[i]=1;
9263 delayslot_alloc(&current,i+1);
9264 }
57871462 9265 }
9266 else
9267 if((opcode[i]&0x3E)==6) // BLEZ/BGTZ
9268 {
9269 alloc_cc(&current,i);
9270 dirty_reg(&current,CCREG);
9271 alloc_reg(&current,i,rs1[i]);
9272 if(!(current.is32>>rs1[i]&1))
9273 {
9274 alloc_reg64(&current,i,rs1[i]);
9275 }
9276 if(rs1[i]&&(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1])) {
9277 // The delay slot overwrites one of our conditions.
9278 // Allocate the branch condition registers instead.
57871462 9279 current.isconst=0;
9280 current.wasconst=0;
9281 regs[i].wasconst=0;
9282 if(rs1[i]) alloc_reg(&current,i,rs1[i]);
9283 if(!((current.is32>>rs1[i])&1))
9284 {
9285 if(rs1[i]) alloc_reg64(&current,i,rs1[i]);
9286 }
9287 }
e1190b87 9288 else
9289 {
9290 ooo[i]=1;
9291 delayslot_alloc(&current,i+1);
9292 }
57871462 9293 }
9294 else
9295 // Don't alloc the delay slot yet because we might not execute it
9296 if((opcode[i]&0x3E)==0x14) // BEQL/BNEL
9297 {
9298 current.isconst=0;
9299 current.wasconst=0;
9300 regs[i].wasconst=0;
9301 alloc_cc(&current,i);
9302 dirty_reg(&current,CCREG);
9303 alloc_reg(&current,i,rs1[i]);
9304 alloc_reg(&current,i,rs2[i]);
9305 if(!((current.is32>>rs1[i])&(current.is32>>rs2[i])&1))
9306 {
9307 alloc_reg64(&current,i,rs1[i]);
9308 alloc_reg64(&current,i,rs2[i]);
9309 }
9310 }
9311 else
9312 if((opcode[i]&0x3E)==0x16) // BLEZL/BGTZL
9313 {
9314 current.isconst=0;
9315 current.wasconst=0;
9316 regs[i].wasconst=0;
9317 alloc_cc(&current,i);
9318 dirty_reg(&current,CCREG);
9319 alloc_reg(&current,i,rs1[i]);
9320 if(!(current.is32>>rs1[i]&1))
9321 {
9322 alloc_reg64(&current,i,rs1[i]);
9323 }
9324 }
9325 ds=1;
9326 //current.isconst=0;
9327 break;
9328 case SJUMP:
9329 //current.isconst=0;
9330 //current.wasconst=0;
9331 //regs[i].wasconst=0;
9332 clear_const(&current,rs1[i]);
9333 clear_const(&current,rt1[i]);
9334 //if((opcode2[i]&0x1E)==0x0) // BLTZ/BGEZ
9335 if((opcode2[i]&0x0E)==0x0) // BLTZ/BGEZ
9336 {
9337 alloc_cc(&current,i);
9338 dirty_reg(&current,CCREG);
9339 alloc_reg(&current,i,rs1[i]);
9340 if(!(current.is32>>rs1[i]&1))
9341 {
9342 alloc_reg64(&current,i,rs1[i]);
9343 }
9344 if (rt1[i]==31) { // BLTZAL/BGEZAL
9345 alloc_reg(&current,i,31);
9346 dirty_reg(&current,31);
57871462 9347 //#ifdef REG_PREFETCH
9348 //alloc_reg(&current,i,PTEMP);
9349 //#endif
9350 //current.is32|=1LL<<rt1[i];
9351 }
e1190b87 9352 if((rs1[i]&&(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1])) // The delay slot overwrites the branch condition.
9353 ||(rt1[i]==31&&(rs1[i+1]==31||rs2[i+1]==31||rt1[i+1]==31||rt2[i+1]==31))) { // DS touches $ra
57871462 9354 // Allocate the branch condition registers instead.
57871462 9355 current.isconst=0;
9356 current.wasconst=0;
9357 regs[i].wasconst=0;
9358 if(rs1[i]) alloc_reg(&current,i,rs1[i]);
9359 if(!((current.is32>>rs1[i])&1))
9360 {
9361 if(rs1[i]) alloc_reg64(&current,i,rs1[i]);
9362 }
9363 }
e1190b87 9364 else
9365 {
9366 ooo[i]=1;
9367 delayslot_alloc(&current,i+1);
9368 }
57871462 9369 }
9370 else
9371 // Don't alloc the delay slot yet because we might not execute it
9372 if((opcode2[i]&0x1E)==0x2) // BLTZL/BGEZL
9373 {
9374 current.isconst=0;
9375 current.wasconst=0;
9376 regs[i].wasconst=0;
9377 alloc_cc(&current,i);
9378 dirty_reg(&current,CCREG);
9379 alloc_reg(&current,i,rs1[i]);
9380 if(!(current.is32>>rs1[i]&1))
9381 {
9382 alloc_reg64(&current,i,rs1[i]);
9383 }
9384 }
9385 ds=1;
9386 //current.isconst=0;
9387 break;
9388 case FJUMP:
9389 current.isconst=0;
9390 current.wasconst=0;
9391 regs[i].wasconst=0;
9392 if(likely[i]==0) // BC1F/BC1T
9393 {
9394 // TODO: Theoretically we can run out of registers here on x86.
9395 // The delay slot can allocate up to six, and we need to check
9396 // CSREG before executing the delay slot. Possibly we can drop
9397 // the cycle count and then reload it after checking that the
9398 // FPU is in a usable state, or don't do out-of-order execution.
9399 alloc_cc(&current,i);
9400 dirty_reg(&current,CCREG);
9401 alloc_reg(&current,i,FSREG);
9402 alloc_reg(&current,i,CSREG);
9403 if(itype[i+1]==FCOMP) {
9404 // The delay slot overwrites the branch condition.
9405 // Allocate the branch condition registers instead.
57871462 9406 alloc_cc(&current,i);
9407 dirty_reg(&current,CCREG);
9408 alloc_reg(&current,i,CSREG);
9409 alloc_reg(&current,i,FSREG);
9410 }
9411 else {
e1190b87 9412 ooo[i]=1;
57871462 9413 delayslot_alloc(&current,i+1);
9414 alloc_reg(&current,i+1,CSREG);
9415 }
9416 }
9417 else
9418 // Don't alloc the delay slot yet because we might not execute it
9419 if(likely[i]) // BC1FL/BC1TL
9420 {
9421 alloc_cc(&current,i);
9422 dirty_reg(&current,CCREG);
9423 alloc_reg(&current,i,CSREG);
9424 alloc_reg(&current,i,FSREG);
9425 }
9426 ds=1;
9427 current.isconst=0;
9428 break;
9429 case IMM16:
9430 imm16_alloc(&current,i);
9431 break;
9432 case LOAD:
9433 case LOADLR:
9434 load_alloc(&current,i);
9435 break;
9436 case STORE:
9437 case STORELR:
9438 store_alloc(&current,i);
9439 break;
9440 case ALU:
9441 alu_alloc(&current,i);
9442 break;
9443 case SHIFT:
9444 shift_alloc(&current,i);
9445 break;
9446 case MULTDIV:
9447 multdiv_alloc(&current,i);
9448 break;
9449 case SHIFTIMM:
9450 shiftimm_alloc(&current,i);
9451 break;
9452 case MOV:
9453 mov_alloc(&current,i);
9454 break;
9455 case COP0:
9456 cop0_alloc(&current,i);
9457 break;
9458 case COP1:
b9b61529 9459 case COP2:
57871462 9460 cop1_alloc(&current,i);
9461 break;
9462 case C1LS:
9463 c1ls_alloc(&current,i);
9464 break;
b9b61529 9465 case C2LS:
9466 c2ls_alloc(&current,i);
9467 break;
9468 case C2OP:
9469 c2op_alloc(&current,i);
9470 break;
57871462 9471 case FCONV:
9472 fconv_alloc(&current,i);
9473 break;
9474 case FLOAT:
9475 float_alloc(&current,i);
9476 break;
9477 case FCOMP:
9478 fcomp_alloc(&current,i);
9479 break;
9480 case SYSCALL:
7139f3c8 9481 case HLECALL:
1e973cb0 9482 case INTCALL:
57871462 9483 syscall_alloc(&current,i);
9484 break;
9485 case SPAN:
9486 pagespan_alloc(&current,i);
9487 break;
9488 }
9489
9490 // Drop the upper half of registers that have become 32-bit
9491 current.uu|=current.is32&((1LL<<rt1[i])|(1LL<<rt2[i]));
9492 if(itype[i]!=UJUMP&&itype[i]!=CJUMP&&itype[i]!=SJUMP&&itype[i]!=RJUMP&&itype[i]!=FJUMP) {
9493 current.uu&=~((1LL<<us1[i])|(1LL<<us2[i]));
9494 if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
9495 current.uu|=1;
9496 } else {
9497 current.uu|=current.is32&((1LL<<rt1[i+1])|(1LL<<rt2[i+1]));
9498 current.uu&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
9499 if((~current.uu>>rt1[i+1])&1) current.uu&=~((1LL<<dep1[i+1])|(1LL<<dep2[i+1]));
9500 current.uu&=~((1LL<<us1[i])|(1LL<<us2[i]));
9501 current.uu|=1;
9502 }
9503
9504 // Create entry (branch target) regmap
9505 for(hr=0;hr<HOST_REGS;hr++)
9506 {
9507 int r,or,er;
9508 r=current.regmap[hr];
9509 if(r>=0) {
9510 if(r!=regmap_pre[i][hr]) {
9511 // TODO: delay slot (?)
9512 or=get_reg(regmap_pre[i],r); // Get old mapping for this register
9513 if(or<0||(r&63)>=TEMPREG){
9514 regs[i].regmap_entry[hr]=-1;
9515 }
9516 else
9517 {
9518 // Just move it to a different register
9519 regs[i].regmap_entry[hr]=r;
9520 // If it was dirty before, it's still dirty
9521 if((regs[i].wasdirty>>or)&1) dirty_reg(&current,r&63);
9522 }
9523 }
9524 else
9525 {
9526 // Unneeded
9527 if(r==0){
9528 regs[i].regmap_entry[hr]=0;
9529 }
9530 else
9531 if(r<64){
9532 if((current.u>>r)&1) {
9533 regs[i].regmap_entry[hr]=-1;
9534 //regs[i].regmap[hr]=-1;
9535 current.regmap[hr]=-1;
9536 }else
9537 regs[i].regmap_entry[hr]=r;
9538 }
9539 else {
9540 if((current.uu>>(r&63))&1) {
9541 regs[i].regmap_entry[hr]=-1;
9542 //regs[i].regmap[hr]=-1;
9543 current.regmap[hr]=-1;
9544 }else
9545 regs[i].regmap_entry[hr]=r;
9546 }
9547 }
9548 } else {
9549 // Branches expect CCREG to be allocated at the target
9550 if(regmap_pre[i][hr]==CCREG)
9551 regs[i].regmap_entry[hr]=CCREG;
9552 else
9553 regs[i].regmap_entry[hr]=-1;
9554 }
9555 }
9556 memcpy(regs[i].regmap,current.regmap,sizeof(current.regmap));
9557 }
27727b63 9558
9559 if(i>0&&(itype[i-1]==STORE||itype[i-1]==STORELR||(itype[i-1]==C2LS&&opcode[i-1]==0x3a))&&(u_int)imm[i-1]<0x800)
9560 current.waswritten|=1<<rs1[i-1];
9561 current.waswritten&=~(1<<rt1[i]);
9562 current.waswritten&=~(1<<rt2[i]);
9563 if((itype[i]==STORE||itype[i]==STORELR||(itype[i]==C2LS&&opcode[i]==0x3a))&&(u_int)imm[i]>=0x800)
9564 current.waswritten&=~(1<<rs1[i]);
9565
57871462 9566 /* Branch post-alloc */
9567 if(i>0)
9568 {
9569 current.was32=current.is32;
9570 current.wasdirty=current.dirty;
9571 switch(itype[i-1]) {
9572 case UJUMP:
9573 memcpy(&branch_regs[i-1],&current,sizeof(current));
9574 branch_regs[i-1].isconst=0;
9575 branch_regs[i-1].wasconst=0;
9576 branch_regs[i-1].u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i-1])|(1LL<<rs2[i-1]));
9577 branch_regs[i-1].uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i-1])|(1LL<<us2[i-1]));
9578 alloc_cc(&branch_regs[i-1],i-1);
9579 dirty_reg(&branch_regs[i-1],CCREG);
9580 if(rt1[i-1]==31) { // JAL
9581 alloc_reg(&branch_regs[i-1],i-1,31);
9582 dirty_reg(&branch_regs[i-1],31);
9583 branch_regs[i-1].is32|=1LL<<31;
9584 }
9585 memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
956f3129 9586 memcpy(constmap[i],constmap[i-1],sizeof(current_constmap));
57871462 9587 break;
9588 case RJUMP:
9589 memcpy(&branch_regs[i-1],&current,sizeof(current));
9590 branch_regs[i-1].isconst=0;
9591 branch_regs[i-1].wasconst=0;
9592 branch_regs[i-1].u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i-1])|(1LL<<rs2[i-1]));
9593 branch_regs[i-1].uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i-1])|(1LL<<us2[i-1]));
9594 alloc_cc(&branch_regs[i-1],i-1);
9595 dirty_reg(&branch_regs[i-1],CCREG);
9596 alloc_reg(&branch_regs[i-1],i-1,rs1[i-1]);
5067f341 9597 if(rt1[i-1]!=0) { // JALR
9598 alloc_reg(&branch_regs[i-1],i-1,rt1[i-1]);
9599 dirty_reg(&branch_regs[i-1],rt1[i-1]);
9600 branch_regs[i-1].is32|=1LL<<rt1[i-1];
57871462 9601 }
9602 #ifdef USE_MINI_HT
9603 if(rs1[i-1]==31) { // JALR
9604 alloc_reg(&branch_regs[i-1],i-1,RHASH);
9605 #ifndef HOST_IMM_ADDR32
9606 alloc_reg(&branch_regs[i-1],i-1,RHTBL);
9607 #endif
9608 }
9609 #endif
9610 memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
956f3129 9611 memcpy(constmap[i],constmap[i-1],sizeof(current_constmap));
57871462 9612 break;
9613 case CJUMP:
9614 if((opcode[i-1]&0x3E)==4) // BEQ/BNE
9615 {
9616 alloc_cc(&current,i-1);
9617 dirty_reg(&current,CCREG);
9618 if((rs1[i-1]&&(rs1[i-1]==rt1[i]||rs1[i-1]==rt2[i]))||
9619 (rs2[i-1]&&(rs2[i-1]==rt1[i]||rs2[i-1]==rt2[i]))) {
9620 // The delay slot overwrote one of our conditions
9621 // Delay slot goes after the test (in order)
9622 current.u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i]));
9623 current.uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i]));
9624 if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
9625 current.u|=1;
9626 current.uu|=1;
9627 delayslot_alloc(&current,i);
9628 current.isconst=0;
9629 }
9630 else
9631 {
9632 current.u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i-1])|(1LL<<rs2[i-1]));
9633 current.uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i-1])|(1LL<<us2[i-1]));
9634 // Alloc the branch condition registers
9635 if(rs1[i-1]) alloc_reg(&current,i-1,rs1[i-1]);
9636 if(rs2[i-1]) alloc_reg(&current,i-1,rs2[i-1]);
9637 if(!((current.is32>>rs1[i-1])&(current.is32>>rs2[i-1])&1))
9638 {
9639 if(rs1[i-1]) alloc_reg64(&current,i-1,rs1[i-1]);
9640 if(rs2[i-1]) alloc_reg64(&current,i-1,rs2[i-1]);
9641 }
9642 }
9643 memcpy(&branch_regs[i-1],&current,sizeof(current));
9644 branch_regs[i-1].isconst=0;
9645 branch_regs[i-1].wasconst=0;
9646 memcpy(&branch_regs[i-1].regmap_entry,&current.regmap,sizeof(current.regmap));
956f3129 9647 memcpy(constmap[i],constmap[i-1],sizeof(current_constmap));
57871462 9648 }
9649 else
9650 if((opcode[i-1]&0x3E)==6) // BLEZ/BGTZ
9651 {
9652 alloc_cc(&current,i-1);
9653 dirty_reg(&current,CCREG);
9654 if(rs1[i-1]==rt1[i]||rs1[i-1]==rt2[i]) {
9655 // The delay slot overwrote the branch condition
9656 // Delay slot goes after the test (in order)
9657 current.u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i]));
9658 current.uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i]));
9659 if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
9660 current.u|=1;
9661 current.uu|=1;
9662 delayslot_alloc(&current,i);
9663 current.isconst=0;
9664 }
9665 else
9666 {
9667 current.u=branch_unneeded_reg[i-1]&~(1LL<<rs1[i-1]);
9668 current.uu=branch_unneeded_reg_upper[i-1]&~(1LL<<us1[i-1]);
9669 // Alloc the branch condition register
9670 alloc_reg(&current,i-1,rs1[i-1]);
9671 if(!(current.is32>>rs1[i-1]&1))
9672 {
9673 alloc_reg64(&current,i-1,rs1[i-1]);
9674 }
9675 }
9676 memcpy(&branch_regs[i-1],&current,sizeof(current));
9677 branch_regs[i-1].isconst=0;
9678 branch_regs[i-1].wasconst=0;
9679 memcpy(&branch_regs[i-1].regmap_entry,&current.regmap,sizeof(current.regmap));
956f3129 9680 memcpy(constmap[i],constmap[i-1],sizeof(current_constmap));
57871462 9681 }
9682 else
9683 // Alloc the delay slot in case the branch is taken
9684 if((opcode[i-1]&0x3E)==0x14) // BEQL/BNEL
9685 {
9686 memcpy(&branch_regs[i-1],&current,sizeof(current));
9687 branch_regs[i-1].u=(branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9688 branch_regs[i-1].uu=(branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9689 if((~branch_regs[i-1].uu>>rt1[i])&1) branch_regs[i-1].uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]))|1;
9690 alloc_cc(&branch_regs[i-1],i);
9691 dirty_reg(&branch_regs[i-1],CCREG);
9692 delayslot_alloc(&branch_regs[i-1],i);
9693 branch_regs[i-1].isconst=0;
9694 alloc_reg(&current,i,CCREG); // Not taken path
9695 dirty_reg(&current,CCREG);
9696 memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
9697 }
9698 else
9699 if((opcode[i-1]&0x3E)==0x16) // BLEZL/BGTZL
9700 {
9701 memcpy(&branch_regs[i-1],&current,sizeof(current));
9702 branch_regs[i-1].u=(branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9703 branch_regs[i-1].uu=(branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9704 if((~branch_regs[i-1].uu>>rt1[i])&1) branch_regs[i-1].uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]))|1;
9705 alloc_cc(&branch_regs[i-1],i);
9706 dirty_reg(&branch_regs[i-1],CCREG);
9707 delayslot_alloc(&branch_regs[i-1],i);
9708 branch_regs[i-1].isconst=0;
9709 alloc_reg(&current,i,CCREG); // Not taken path
9710 dirty_reg(&current,CCREG);
9711 memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
9712 }
9713 break;
9714 case SJUMP:
9715 //if((opcode2[i-1]&0x1E)==0) // BLTZ/BGEZ
9716 if((opcode2[i-1]&0x0E)==0) // BLTZ/BGEZ
9717 {
9718 alloc_cc(&current,i-1);
9719 dirty_reg(&current,CCREG);
9720 if(rs1[i-1]==rt1[i]||rs1[i-1]==rt2[i]) {
9721 // The delay slot overwrote the branch condition
9722 // Delay slot goes after the test (in order)
9723 current.u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i]));
9724 current.uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i]));
9725 if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
9726 current.u|=1;
9727 current.uu|=1;
9728 delayslot_alloc(&current,i);
9729 current.isconst=0;
9730 }
9731 else
9732 {
9733 current.u=branch_unneeded_reg[i-1]&~(1LL<<rs1[i-1]);
9734 current.uu=branch_unneeded_reg_upper[i-1]&~(1LL<<us1[i-1]);
9735 // Alloc the branch condition register
9736 alloc_reg(&current,i-1,rs1[i-1]);
9737 if(!(current.is32>>rs1[i-1]&1))
9738 {
9739 alloc_reg64(&current,i-1,rs1[i-1]);
9740 }
9741 }
9742 memcpy(&branch_regs[i-1],&current,sizeof(current));
9743 branch_regs[i-1].isconst=0;
9744 branch_regs[i-1].wasconst=0;
9745 memcpy(&branch_regs[i-1].regmap_entry,&current.regmap,sizeof(current.regmap));
956f3129 9746 memcpy(constmap[i],constmap[i-1],sizeof(current_constmap));
57871462 9747 }
9748 else
9749 // Alloc the delay slot in case the branch is taken
9750 if((opcode2[i-1]&0x1E)==2) // BLTZL/BGEZL
9751 {
9752 memcpy(&branch_regs[i-1],&current,sizeof(current));
9753 branch_regs[i-1].u=(branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9754 branch_regs[i-1].uu=(branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9755 if((~branch_regs[i-1].uu>>rt1[i])&1) branch_regs[i-1].uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]))|1;
9756 alloc_cc(&branch_regs[i-1],i);
9757 dirty_reg(&branch_regs[i-1],CCREG);
9758 delayslot_alloc(&branch_regs[i-1],i);
9759 branch_regs[i-1].isconst=0;
9760 alloc_reg(&current,i,CCREG); // Not taken path
9761 dirty_reg(&current,CCREG);
9762 memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
9763 }
9764 // FIXME: BLTZAL/BGEZAL
9765 if(opcode2[i-1]&0x10) { // BxxZAL
9766 alloc_reg(&branch_regs[i-1],i-1,31);
9767 dirty_reg(&branch_regs[i-1],31);
9768 branch_regs[i-1].is32|=1LL<<31;
9769 }
9770 break;
9771 case FJUMP:
9772 if(likely[i-1]==0) // BC1F/BC1T
9773 {
9774 alloc_cc(&current,i-1);
9775 dirty_reg(&current,CCREG);
9776 if(itype[i]==FCOMP) {
9777 // The delay slot overwrote the branch condition
9778 // Delay slot goes after the test (in order)
9779 delayslot_alloc(&current,i);
9780 current.isconst=0;
9781 }
9782 else
9783 {
9784 current.u=branch_unneeded_reg[i-1]&~(1LL<<rs1[i-1]);
9785 current.uu=branch_unneeded_reg_upper[i-1]&~(1LL<<us1[i-1]);
9786 // Alloc the branch condition register
9787 alloc_reg(&current,i-1,FSREG);
9788 }
9789 memcpy(&branch_regs[i-1],&current,sizeof(current));
9790 memcpy(&branch_regs[i-1].regmap_entry,&current.regmap,sizeof(current.regmap));
9791 }
9792 else // BC1FL/BC1TL
9793 {
9794 // Alloc the delay slot in case the branch is taken
9795 memcpy(&branch_regs[i-1],&current,sizeof(current));
9796 branch_regs[i-1].u=(branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9797 branch_regs[i-1].uu=(branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9798 if((~branch_regs[i-1].uu>>rt1[i])&1) branch_regs[i-1].uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]))|1;
9799 alloc_cc(&branch_regs[i-1],i);
9800 dirty_reg(&branch_regs[i-1],CCREG);
9801 delayslot_alloc(&branch_regs[i-1],i);
9802 branch_regs[i-1].isconst=0;
9803 alloc_reg(&current,i,CCREG); // Not taken path
9804 dirty_reg(&current,CCREG);
9805 memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
9806 }
9807 break;
9808 }
9809
9810 if(itype[i-1]==UJUMP||itype[i-1]==RJUMP||(source[i-1]>>16)==0x1000)
9811 {
9812 if(rt1[i-1]==31) // JAL/JALR
9813 {
9814 // Subroutine call will return here, don't alloc any registers
9815 current.is32=1;
9816 current.dirty=0;
9817 clear_all_regs(current.regmap);
9818 alloc_reg(&current,i,CCREG);
9819 dirty_reg(&current,CCREG);
9820 }
9821 else if(i+1<slen)
9822 {
9823 // Internal branch will jump here, match registers to caller
9824 current.is32=0x3FFFFFFFFLL;
9825 current.dirty=0;
9826 clear_all_regs(current.regmap);
9827 alloc_reg(&current,i,CCREG);
9828 dirty_reg(&current,CCREG);
9829 for(j=i-1;j>=0;j--)
9830 {
9831 if(ba[j]==start+i*4+4) {
9832 memcpy(current.regmap,branch_regs[j].regmap,sizeof(current.regmap));
9833 current.is32=branch_regs[j].is32;
9834 current.dirty=branch_regs[j].dirty;
9835 break;
9836 }
9837 }
9838 while(j>=0) {
9839 if(ba[j]==start+i*4+4) {
9840 for(hr=0;hr<HOST_REGS;hr++) {
9841 if(current.regmap[hr]!=branch_regs[j].regmap[hr]) {
9842 current.regmap[hr]=-1;
9843 }
9844 current.is32&=branch_regs[j].is32;
9845 current.dirty&=branch_regs[j].dirty;
9846 }
9847 }
9848 j--;
9849 }
9850 }
9851 }
9852 }
9853
9854 // Count cycles in between branches
9855 ccadj[i]=cc;
7139f3c8 9856 if(i>0&&(itype[i-1]==RJUMP||itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP||itype[i]==SYSCALL||itype[i]==HLECALL))
57871462 9857 {
9858 cc=0;
9859 }
19776aef 9860#if defined(PCSX) && !defined(DRC_DBG)
054175e9 9861 else if(itype[i]==C2OP&&gte_cycletab[source[i]&0x3f]>2)
9862 {
9863 // GTE runs in parallel until accessed, divide by 2 for a rough guess
9864 cc+=gte_cycletab[source[i]&0x3f]/2;
9865 }
b6e87b2b 9866 else if(/*itype[i]==LOAD||itype[i]==STORE||*/itype[i]==C1LS) // load,store causes weird timing issues
fb407447 9867 {
9868 cc+=2; // 2 cycle penalty (after CLOCK_DIVIDER)
9869 }
9870 else if(itype[i]==C2LS)
9871 {
9872 cc+=4;
9873 }
9874#endif
57871462 9875 else
9876 {
9877 cc++;
9878 }
9879
9880 flush_dirty_uppers(&current);
9881 if(!is_ds[i]) {
9882 regs[i].is32=current.is32;
9883 regs[i].dirty=current.dirty;
9884 regs[i].isconst=current.isconst;
956f3129 9885 memcpy(constmap[i],current_constmap,sizeof(current_constmap));
57871462 9886 }
9887 for(hr=0;hr<HOST_REGS;hr++) {
9888 if(hr!=EXCLUDE_REG&&regs[i].regmap[hr]>=0) {
9889 if(regmap_pre[i][hr]!=regs[i].regmap[hr]) {
9890 regs[i].wasconst&=~(1<<hr);
9891 }
9892 }
9893 }
9894 if(current.regmap[HOST_BTREG]==BTREG) current.regmap[HOST_BTREG]=-1;
27727b63 9895 regs[i].waswritten=current.waswritten;
57871462 9896 }
9897
9898 /* Pass 4 - Cull unused host registers */
9899
9900 uint64_t nr=0;
9901
9902 for (i=slen-1;i>=0;i--)
9903 {
9904 int hr;
9905 if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
9906 {
9907 if(ba[i]<start || ba[i]>=(start+slen*4))
9908 {
9909 // Branch out of this block, don't need anything
9910 nr=0;
9911 }
9912 else
9913 {
9914 // Internal branch
9915 // Need whatever matches the target
9916 nr=0;
9917 int t=(ba[i]-start)>>2;
9918 for(hr=0;hr<HOST_REGS;hr++)
9919 {
9920 if(regs[i].regmap_entry[hr]>=0) {
9921 if(regs[i].regmap_entry[hr]==regs[t].regmap_entry[hr]) nr|=1<<hr;
9922 }
9923 }
9924 }
9925 // Conditional branch may need registers for following instructions
9926 if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000)
9927 {
9928 if(i<slen-2) {
9929 nr|=needed_reg[i+2];
9930 for(hr=0;hr<HOST_REGS;hr++)
9931 {
9932 if(regmap_pre[i+2][hr]>=0&&get_reg(regs[i+2].regmap_entry,regmap_pre[i+2][hr])<0) nr&=~(1<<hr);
9933 //if((regmap_entry[i+2][hr])>=0) if(!((nr>>hr)&1)) printf("%x-bogus(%d=%d)\n",start+i*4,hr,regmap_entry[i+2][hr]);
9934 }
9935 }
9936 }
9937 // Don't need stuff which is overwritten
f5955059 9938 //if(regs[i].regmap[hr]!=regmap_pre[i][hr]) nr&=~(1<<hr);
9939 //if(regs[i].regmap[hr]<0) nr&=~(1<<hr);
57871462 9940 // Merge in delay slot
9941 for(hr=0;hr<HOST_REGS;hr++)
9942 {
9943 if(!likely[i]) {
9944 // These are overwritten unless the branch is "likely"
9945 // and the delay slot is nullified if not taken
9946 if(rt1[i+1]&&rt1[i+1]==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
9947 if(rt2[i+1]&&rt2[i+1]==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
9948 }
9949 if(us1[i+1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9950 if(us2[i+1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9951 if(rs1[i+1]==regmap_pre[i][hr]) nr|=1<<hr;
9952 if(rs2[i+1]==regmap_pre[i][hr]) nr|=1<<hr;
9953 if(us1[i+1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9954 if(us2[i+1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9955 if(rs1[i+1]==regs[i].regmap_entry[hr]) nr|=1<<hr;
9956 if(rs2[i+1]==regs[i].regmap_entry[hr]) nr|=1<<hr;
9957 if(dep1[i+1]&&!((unneeded_reg_upper[i]>>dep1[i+1])&1)) {
9958 if(dep1[i+1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9959 if(dep2[i+1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9960 }
9961 if(dep2[i+1]&&!((unneeded_reg_upper[i]>>dep2[i+1])&1)) {
9962 if(dep1[i+1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9963 if(dep2[i+1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9964 }
b9b61529 9965 if(itype[i+1]==STORE || itype[i+1]==STORELR || (opcode[i+1]&0x3b)==0x39 || (opcode[i+1]&0x3b)==0x3a) {
57871462 9966 if(regmap_pre[i][hr]==INVCP) nr|=1<<hr;
9967 if(regs[i].regmap_entry[hr]==INVCP) nr|=1<<hr;
9968 }
9969 }
9970 }
1e973cb0 9971 else if(itype[i]==SYSCALL||itype[i]==HLECALL||itype[i]==INTCALL)
57871462 9972 {
9973 // SYSCALL instruction (software interrupt)
9974 nr=0;
9975 }
9976 else if(itype[i]==COP0 && (source[i]&0x3f)==0x18)
9977 {
9978 // ERET instruction (return from interrupt)
9979 nr=0;
9980 }
9981 else // Non-branch
9982 {
9983 if(i<slen-1) {
9984 for(hr=0;hr<HOST_REGS;hr++) {
9985 if(regmap_pre[i+1][hr]>=0&&get_reg(regs[i+1].regmap_entry,regmap_pre[i+1][hr])<0) nr&=~(1<<hr);
9986 if(regs[i].regmap[hr]!=regmap_pre[i+1][hr]) nr&=~(1<<hr);
9987 if(regs[i].regmap[hr]!=regmap_pre[i][hr]) nr&=~(1<<hr);
9988 if(regs[i].regmap[hr]<0) nr&=~(1<<hr);
9989 }
9990 }
9991 }
9992 for(hr=0;hr<HOST_REGS;hr++)
9993 {
9994 // Overwritten registers are not needed
9995 if(rt1[i]&&rt1[i]==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
9996 if(rt2[i]&&rt2[i]==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
9997 if(FTEMP==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
9998 // Source registers are needed
9999 if(us1[i]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
10000 if(us2[i]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
10001 if(rs1[i]==regmap_pre[i][hr]) nr|=1<<hr;
10002 if(rs2[i]==regmap_pre[i][hr]) nr|=1<<hr;
10003 if(us1[i]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
10004 if(us2[i]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
10005 if(rs1[i]==regs[i].regmap_entry[hr]) nr|=1<<hr;
10006 if(rs2[i]==regs[i].regmap_entry[hr]) nr|=1<<hr;
10007 if(dep1[i]&&!((unneeded_reg_upper[i]>>dep1[i])&1)) {
10008 if(dep1[i]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
10009 if(dep1[i]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
10010 }
10011 if(dep2[i]&&!((unneeded_reg_upper[i]>>dep2[i])&1)) {
10012 if(dep2[i]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
10013 if(dep2[i]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
10014 }
b9b61529 10015 if(itype[i]==STORE || itype[i]==STORELR || (opcode[i]&0x3b)==0x39 || (opcode[i]&0x3b)==0x3a) {
57871462 10016 if(regmap_pre[i][hr]==INVCP) nr|=1<<hr;
10017 if(regs[i].regmap_entry[hr]==INVCP) nr|=1<<hr;
10018 }
10019 // Don't store a register immediately after writing it,
10020 // may prevent dual-issue.
10021 // But do so if this is a branch target, otherwise we
10022 // might have to load the register before the branch.
10023 if(i>0&&!bt[i]&&((regs[i].wasdirty>>hr)&1)) {
10024 if((regmap_pre[i][hr]>0&&regmap_pre[i][hr]<64&&!((unneeded_reg[i]>>regmap_pre[i][hr])&1)) ||
10025 (regmap_pre[i][hr]>64&&!((unneeded_reg_upper[i]>>(regmap_pre[i][hr]&63))&1)) ) {
10026 if(rt1[i-1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
10027 if(rt2[i-1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
10028 }
10029 if((regs[i].regmap_entry[hr]>0&&regs[i].regmap_entry[hr]<64&&!((unneeded_reg[i]>>regs[i].regmap_entry[hr])&1)) ||
10030 (regs[i].regmap_entry[hr]>64&&!((unneeded_reg_upper[i]>>(regs[i].regmap_entry[hr]&63))&1)) ) {
10031 if(rt1[i-1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
10032 if(rt2[i-1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
10033 }
10034 }
10035 }
10036 // Cycle count is needed at branches. Assume it is needed at the target too.
10037 if(i==0||bt[i]||itype[i]==CJUMP||itype[i]==FJUMP||itype[i]==SPAN) {
10038 if(regmap_pre[i][HOST_CCREG]==CCREG) nr|=1<<HOST_CCREG;
10039 if(regs[i].regmap_entry[HOST_CCREG]==CCREG) nr|=1<<HOST_CCREG;
10040 }
10041 // Save it
10042 needed_reg[i]=nr;
10043
10044 // Deallocate unneeded registers
10045 for(hr=0;hr<HOST_REGS;hr++)
10046 {
10047 if(!((nr>>hr)&1)) {
10048 if(regs[i].regmap_entry[hr]!=CCREG) regs[i].regmap_entry[hr]=-1;
10049 if((regs[i].regmap[hr]&63)!=rs1[i] && (regs[i].regmap[hr]&63)!=rs2[i] &&
10050 (regs[i].regmap[hr]&63)!=rt1[i] && (regs[i].regmap[hr]&63)!=rt2[i] &&
10051 (regs[i].regmap[hr]&63)!=PTEMP && (regs[i].regmap[hr]&63)!=CCREG)
10052 {
10053 if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000)
10054 {
10055 if(likely[i]) {
10056 regs[i].regmap[hr]=-1;
10057 regs[i].isconst&=~(1<<hr);
79c75f1b 10058 if(i<slen-2) {
10059 regmap_pre[i+2][hr]=-1;
10060 regs[i+2].wasconst&=~(1<<hr);
10061 }
57871462 10062 }
10063 }
10064 }
10065 if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
10066 {
10067 int d1=0,d2=0,map=0,temp=0;
10068 if(get_reg(regs[i].regmap,rt1[i+1]|64)>=0||get_reg(branch_regs[i].regmap,rt1[i+1]|64)>=0)
10069 {
10070 d1=dep1[i+1];
10071 d2=dep2[i+1];
10072 }
10073 if(using_tlb) {
10074 if(itype[i+1]==LOAD || itype[i+1]==LOADLR ||
10075 itype[i+1]==STORE || itype[i+1]==STORELR ||
b9b61529 10076 itype[i+1]==C1LS || itype[i+1]==C2LS)
57871462 10077 map=TLREG;
10078 } else
b9b61529 10079 if(itype[i+1]==STORE || itype[i+1]==STORELR ||
10080 (opcode[i+1]&0x3b)==0x39 || (opcode[i+1]&0x3b)==0x3a) { // SWC1/SDC1 || SWC2/SDC2
57871462 10081 map=INVCP;
10082 }
10083 if(itype[i+1]==LOADLR || itype[i+1]==STORELR ||
b9b61529 10084 itype[i+1]==C1LS || itype[i+1]==C2LS)
57871462 10085 temp=FTEMP;
10086 if((regs[i].regmap[hr]&63)!=rs1[i] && (regs[i].regmap[hr]&63)!=rs2[i] &&
10087 (regs[i].regmap[hr]&63)!=rt1[i] && (regs[i].regmap[hr]&63)!=rt2[i] &&
10088 (regs[i].regmap[hr]&63)!=rt1[i+1] && (regs[i].regmap[hr]&63)!=rt2[i+1] &&
10089 (regs[i].regmap[hr]^64)!=us1[i+1] && (regs[i].regmap[hr]^64)!=us2[i+1] &&
10090 (regs[i].regmap[hr]^64)!=d1 && (regs[i].regmap[hr]^64)!=d2 &&
10091 regs[i].regmap[hr]!=rs1[i+1] && regs[i].regmap[hr]!=rs2[i+1] &&
10092 (regs[i].regmap[hr]&63)!=temp && regs[i].regmap[hr]!=PTEMP &&
10093 regs[i].regmap[hr]!=RHASH && regs[i].regmap[hr]!=RHTBL &&
10094 regs[i].regmap[hr]!=RTEMP && regs[i].regmap[hr]!=CCREG &&
10095 regs[i].regmap[hr]!=map )
10096 {
10097 regs[i].regmap[hr]=-1;
10098 regs[i].isconst&=~(1<<hr);
10099 if((branch_regs[i].regmap[hr]&63)!=rs1[i] && (branch_regs[i].regmap[hr]&63)!=rs2[i] &&
10100 (branch_regs[i].regmap[hr]&63)!=rt1[i] && (branch_regs[i].regmap[hr]&63)!=rt2[i] &&
10101 (branch_regs[i].regmap[hr]&63)!=rt1[i+1] && (branch_regs[i].regmap[hr]&63)!=rt2[i+1] &&
10102 (branch_regs[i].regmap[hr]^64)!=us1[i+1] && (branch_regs[i].regmap[hr]^64)!=us2[i+1] &&
10103 (branch_regs[i].regmap[hr]^64)!=d1 && (branch_regs[i].regmap[hr]^64)!=d2 &&
10104 branch_regs[i].regmap[hr]!=rs1[i+1] && branch_regs[i].regmap[hr]!=rs2[i+1] &&
10105 (branch_regs[i].regmap[hr]&63)!=temp && branch_regs[i].regmap[hr]!=PTEMP &&
10106 branch_regs[i].regmap[hr]!=RHASH && branch_regs[i].regmap[hr]!=RHTBL &&
10107 branch_regs[i].regmap[hr]!=RTEMP && branch_regs[i].regmap[hr]!=CCREG &&
10108 branch_regs[i].regmap[hr]!=map)
10109 {
10110 branch_regs[i].regmap[hr]=-1;
10111 branch_regs[i].regmap_entry[hr]=-1;
10112 if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000)
10113 {
10114 if(!likely[i]&&i<slen-2) {
10115 regmap_pre[i+2][hr]=-1;
79c75f1b 10116 regs[i+2].wasconst&=~(1<<hr);
57871462 10117 }
10118 }
10119 }
10120 }
10121 }
10122 else
10123 {
10124 // Non-branch
10125 if(i>0)
10126 {
10127 int d1=0,d2=0,map=-1,temp=-1;
10128 if(get_reg(regs[i].regmap,rt1[i]|64)>=0)
10129 {
10130 d1=dep1[i];
10131 d2=dep2[i];
10132 }
10133 if(using_tlb) {
10134 if(itype[i]==LOAD || itype[i]==LOADLR ||
10135 itype[i]==STORE || itype[i]==STORELR ||
b9b61529 10136 itype[i]==C1LS || itype[i]==C2LS)
57871462 10137 map=TLREG;
b9b61529 10138 } else if(itype[i]==STORE || itype[i]==STORELR ||
10139 (opcode[i]&0x3b)==0x39 || (opcode[i]&0x3b)==0x3a) { // SWC1/SDC1 || SWC2/SDC2
57871462 10140 map=INVCP;
10141 }
10142 if(itype[i]==LOADLR || itype[i]==STORELR ||
b9b61529 10143 itype[i]==C1LS || itype[i]==C2LS)
57871462 10144 temp=FTEMP;
10145 if((regs[i].regmap[hr]&63)!=rt1[i] && (regs[i].regmap[hr]&63)!=rt2[i] &&
10146 (regs[i].regmap[hr]^64)!=us1[i] && (regs[i].regmap[hr]^64)!=us2[i] &&
10147 (regs[i].regmap[hr]^64)!=d1 && (regs[i].regmap[hr]^64)!=d2 &&
10148 regs[i].regmap[hr]!=rs1[i] && regs[i].regmap[hr]!=rs2[i] &&
10149 (regs[i].regmap[hr]&63)!=temp && regs[i].regmap[hr]!=map &&
10150 (itype[i]!=SPAN||regs[i].regmap[hr]!=CCREG))
10151 {
10152 if(i<slen-1&&!is_ds[i]) {
10153 if(regmap_pre[i+1][hr]!=-1 || regs[i].regmap[hr]!=-1)
10154 if(regmap_pre[i+1][hr]!=regs[i].regmap[hr])
10155 if(regs[i].regmap[hr]<64||!((regs[i].was32>>(regs[i].regmap[hr]&63))&1))
10156 {
10157 printf("fail: %x (%d %d!=%d)\n",start+i*4,hr,regmap_pre[i+1][hr],regs[i].regmap[hr]);
10158 assert(regmap_pre[i+1][hr]==regs[i].regmap[hr]);
10159 }
10160 regmap_pre[i+1][hr]=-1;
10161 if(regs[i+1].regmap_entry[hr]==CCREG) regs[i+1].regmap_entry[hr]=-1;
79c75f1b 10162 regs[i+1].wasconst&=~(1<<hr);
57871462 10163 }
10164 regs[i].regmap[hr]=-1;
10165 regs[i].isconst&=~(1<<hr);
10166 }
10167 }
10168 }
10169 }
10170 }
10171 }
10172
10173 /* Pass 5 - Pre-allocate registers */
10174
10175 // If a register is allocated during a loop, try to allocate it for the
10176 // entire loop, if possible. This avoids loading/storing registers
10177 // inside of the loop.
198df76f 10178
57871462 10179 signed char f_regmap[HOST_REGS];
10180 clear_all_regs(f_regmap);
10181 for(i=0;i<slen-1;i++)
10182 {
10183 if(itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
10184 {
10185 if(ba[i]>=start && ba[i]<(start+i*4))
10186 if(itype[i+1]==NOP||itype[i+1]==MOV||itype[i+1]==ALU
10187 ||itype[i+1]==SHIFTIMM||itype[i+1]==IMM16||itype[i+1]==LOAD
10188 ||itype[i+1]==STORE||itype[i+1]==STORELR||itype[i+1]==C1LS
10189 ||itype[i+1]==SHIFT||itype[i+1]==COP1||itype[i+1]==FLOAT
b9b61529 10190 ||itype[i+1]==FCOMP||itype[i+1]==FCONV
10191 ||itype[i+1]==COP2||itype[i+1]==C2LS||itype[i+1]==C2OP)
57871462 10192 {
10193 int t=(ba[i]-start)>>2;
10194 if(t>0&&(itype[t-1]!=UJUMP&&itype[t-1]!=RJUMP&&itype[t-1]!=CJUMP&&itype[t-1]!=SJUMP&&itype[t-1]!=FJUMP)) // loop_preload can't handle jumps into delay slots
198df76f 10195 if(t<2||(itype[t-2]!=UJUMP&&itype[t-2]!=RJUMP)||rt1[t-2]!=31) // call/ret assumes no registers allocated
57871462 10196 for(hr=0;hr<HOST_REGS;hr++)
10197 {
10198 if(regs[i].regmap[hr]>64) {
10199 if(!((regs[i].dirty>>hr)&1))
10200 f_regmap[hr]=regs[i].regmap[hr];
10201 else f_regmap[hr]=-1;
10202 }
b372a952 10203 else if(regs[i].regmap[hr]>=0) {
10204 if(f_regmap[hr]!=regs[i].regmap[hr]) {
10205 // dealloc old register
10206 int n;
10207 for(n=0;n<HOST_REGS;n++)
10208 {
10209 if(f_regmap[n]==regs[i].regmap[hr]) {f_regmap[n]=-1;}
10210 }
10211 // and alloc new one
10212 f_regmap[hr]=regs[i].regmap[hr];
10213 }
10214 }
57871462 10215 if(branch_regs[i].regmap[hr]>64) {
10216 if(!((branch_regs[i].dirty>>hr)&1))
10217 f_regmap[hr]=branch_regs[i].regmap[hr];
10218 else f_regmap[hr]=-1;
10219 }
b372a952 10220 else if(branch_regs[i].regmap[hr]>=0) {
10221 if(f_regmap[hr]!=branch_regs[i].regmap[hr]) {
10222 // dealloc old register
10223 int n;
10224 for(n=0;n<HOST_REGS;n++)
10225 {
10226 if(f_regmap[n]==branch_regs[i].regmap[hr]) {f_regmap[n]=-1;}
10227 }
10228 // and alloc new one
10229 f_regmap[hr]=branch_regs[i].regmap[hr];
10230 }
10231 }
e1190b87 10232 if(ooo[i]) {
10233 if(count_free_regs(regs[i].regmap)<=minimum_free_regs[i+1])
10234 f_regmap[hr]=branch_regs[i].regmap[hr];
10235 }else{
10236 if(count_free_regs(branch_regs[i].regmap)<=minimum_free_regs[i+1])
57871462 10237 f_regmap[hr]=branch_regs[i].regmap[hr];
10238 }
10239 // Avoid dirty->clean transition
e1190b87 10240 #ifdef DESTRUCTIVE_WRITEBACK
57871462 10241 if(t>0) if(get_reg(regmap_pre[t],f_regmap[hr])>=0) if((regs[t].wasdirty>>get_reg(regmap_pre[t],f_regmap[hr]))&1) f_regmap[hr]=-1;
e1190b87 10242 #endif
10243 // This check is only strictly required in the DESTRUCTIVE_WRITEBACK
10244 // case above, however it's always a good idea. We can't hoist the
10245 // load if the register was already allocated, so there's no point
10246 // wasting time analyzing most of these cases. It only "succeeds"
10247 // when the mapping was different and the load can be replaced with
10248 // a mov, which is of negligible benefit. So such cases are
10249 // skipped below.
57871462 10250 if(f_regmap[hr]>0) {
198df76f 10251 if(regs[t].regmap[hr]==f_regmap[hr]||(regs[t].regmap_entry[hr]<0&&get_reg(regmap_pre[t],f_regmap[hr])<0)) {
57871462 10252 int r=f_regmap[hr];
10253 for(j=t;j<=i;j++)
10254 {
10255 //printf("Test %x -> %x, %x %d/%d\n",start+i*4,ba[i],start+j*4,hr,r);
10256 if(r<34&&((unneeded_reg[j]>>r)&1)) break;
10257 if(r>63&&((unneeded_reg_upper[j]>>(r&63))&1)) break;
10258 if(r>63) {
10259 // NB This can exclude the case where the upper-half
10260 // register is lower numbered than the lower-half
10261 // register. Not sure if it's worth fixing...
10262 if(get_reg(regs[j].regmap,r&63)<0) break;
e1190b87 10263 if(get_reg(regs[j].regmap_entry,r&63)<0) break;
57871462 10264 if(regs[j].is32&(1LL<<(r&63))) break;
10265 }
10266 if(regs[j].regmap[hr]==f_regmap[hr]&&(f_regmap[hr]&63)<TEMPREG) {
10267 //printf("Hit %x -> %x, %x %d/%d\n",start+i*4,ba[i],start+j*4,hr,r);
10268 int k;
10269 if(regs[i].regmap[hr]==-1&&branch_regs[i].regmap[hr]==-1) {
10270 if(get_reg(regs[i+2].regmap,f_regmap[hr])>=0) break;
10271 if(r>63) {
10272 if(get_reg(regs[i].regmap,r&63)<0) break;
10273 if(get_reg(branch_regs[i].regmap,r&63)<0) break;
10274 }
10275 k=i;
10276 while(k>1&&regs[k-1].regmap[hr]==-1) {
e1190b87 10277 if(count_free_regs(regs[k-1].regmap)<=minimum_free_regs[k-1]) {
10278 //printf("no free regs for store %x\n",start+(k-1)*4);
10279 break;
57871462 10280 }
57871462 10281 if(get_reg(regs[k-1].regmap,f_regmap[hr])>=0) {
10282 //printf("no-match due to different register\n");
10283 break;
10284 }
10285 if(itype[k-2]==UJUMP||itype[k-2]==RJUMP||itype[k-2]==CJUMP||itype[k-2]==SJUMP||itype[k-2]==FJUMP) {
10286 //printf("no-match due to branch\n");
10287 break;
10288 }
10289 // call/ret fast path assumes no registers allocated
198df76f 10290 if(k>2&&(itype[k-3]==UJUMP||itype[k-3]==RJUMP)&&rt1[k-3]==31) {
57871462 10291 break;
10292 }
10293 if(r>63) {
10294 // NB This can exclude the case where the upper-half
10295 // register is lower numbered than the lower-half
10296 // register. Not sure if it's worth fixing...
10297 if(get_reg(regs[k-1].regmap,r&63)<0) break;
10298 if(regs[k-1].is32&(1LL<<(r&63))) break;
10299 }
10300 k--;
10301 }
10302 if(i<slen-1) {
10303 if((regs[k].is32&(1LL<<f_regmap[hr]))!=
10304 (regs[i+2].was32&(1LL<<f_regmap[hr]))) {
10305 //printf("bad match after branch\n");
10306 break;
10307 }
10308 }
10309 if(regs[k-1].regmap[hr]==f_regmap[hr]&&regmap_pre[k][hr]==f_regmap[hr]) {
10310 //printf("Extend r%d, %x ->\n",hr,start+k*4);
10311 while(k<i) {
10312 regs[k].regmap_entry[hr]=f_regmap[hr];
10313 regs[k].regmap[hr]=f_regmap[hr];
10314 regmap_pre[k+1][hr]=f_regmap[hr];
10315 regs[k].wasdirty&=~(1<<hr);
10316 regs[k].dirty&=~(1<<hr);
10317 regs[k].wasdirty|=(1<<hr)&regs[k-1].dirty;
10318 regs[k].dirty|=(1<<hr)&regs[k].wasdirty;
10319 regs[k].wasconst&=~(1<<hr);
10320 regs[k].isconst&=~(1<<hr);
10321 k++;
10322 }
10323 }
10324 else {
10325 //printf("Fail Extend r%d, %x ->\n",hr,start+k*4);
10326 break;
10327 }
10328 assert(regs[i-1].regmap[hr]==f_regmap[hr]);
10329 if(regs[i-1].regmap[hr]==f_regmap[hr]&&regmap_pre[i][hr]==f_regmap[hr]) {
10330 //printf("OK fill %x (r%d)\n",start+i*4,hr);
10331 regs[i].regmap_entry[hr]=f_regmap[hr];
10332 regs[i].regmap[hr]=f_regmap[hr];
10333 regs[i].wasdirty&=~(1<<hr);
10334 regs[i].dirty&=~(1<<hr);
10335 regs[i].wasdirty|=(1<<hr)&regs[i-1].dirty;
10336 regs[i].dirty|=(1<<hr)&regs[i-1].dirty;
10337 regs[i].wasconst&=~(1<<hr);
10338 regs[i].isconst&=~(1<<hr);
10339 branch_regs[i].regmap_entry[hr]=f_regmap[hr];
10340 branch_regs[i].wasdirty&=~(1<<hr);
10341 branch_regs[i].wasdirty|=(1<<hr)&regs[i].dirty;
10342 branch_regs[i].regmap[hr]=f_regmap[hr];
10343 branch_regs[i].dirty&=~(1<<hr);
10344 branch_regs[i].dirty|=(1<<hr)&regs[i].dirty;
10345 branch_regs[i].wasconst&=~(1<<hr);
10346 branch_regs[i].isconst&=~(1<<hr);
10347 if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000) {
10348 regmap_pre[i+2][hr]=f_regmap[hr];
10349 regs[i+2].wasdirty&=~(1<<hr);
10350 regs[i+2].wasdirty|=(1<<hr)&regs[i].dirty;
10351 assert((branch_regs[i].is32&(1LL<<f_regmap[hr]))==
10352 (regs[i+2].was32&(1LL<<f_regmap[hr])));
10353 }
10354 }
10355 }
10356 for(k=t;k<j;k++) {
e1190b87 10357 // Alloc register clean at beginning of loop,
10358 // but may dirty it in pass 6
57871462 10359 regs[k].regmap_entry[hr]=f_regmap[hr];
10360 regs[k].regmap[hr]=f_regmap[hr];
57871462 10361 regs[k].dirty&=~(1<<hr);
10362 regs[k].wasconst&=~(1<<hr);
10363 regs[k].isconst&=~(1<<hr);
e1190b87 10364 if(itype[k]==UJUMP||itype[k]==RJUMP||itype[k]==CJUMP||itype[k]==SJUMP||itype[k]==FJUMP) {
10365 branch_regs[k].regmap_entry[hr]=f_regmap[hr];
10366 branch_regs[k].regmap[hr]=f_regmap[hr];
10367 branch_regs[k].dirty&=~(1<<hr);
10368 branch_regs[k].wasconst&=~(1<<hr);
10369 branch_regs[k].isconst&=~(1<<hr);
10370 if(itype[k]!=RJUMP&&itype[k]!=UJUMP&&(source[k]>>16)!=0x1000) {
10371 regmap_pre[k+2][hr]=f_regmap[hr];
10372 regs[k+2].wasdirty&=~(1<<hr);
10373 assert((branch_regs[k].is32&(1LL<<f_regmap[hr]))==
10374 (regs[k+2].was32&(1LL<<f_regmap[hr])));
10375 }
10376 }
10377 else
10378 {
10379 regmap_pre[k+1][hr]=f_regmap[hr];
10380 regs[k+1].wasdirty&=~(1<<hr);
10381 }
57871462 10382 }
10383 if(regs[j].regmap[hr]==f_regmap[hr])
10384 regs[j].regmap_entry[hr]=f_regmap[hr];
10385 break;
10386 }
10387 if(j==i) break;
10388 if(regs[j].regmap[hr]>=0)
10389 break;
10390 if(get_reg(regs[j].regmap,f_regmap[hr])>=0) {
10391 //printf("no-match due to different register\n");
10392 break;
10393 }
10394 if((regs[j+1].is32&(1LL<<f_regmap[hr]))!=(regs[j].is32&(1LL<<f_regmap[hr]))) {
10395 //printf("32/64 mismatch %x %d\n",start+j*4,hr);
10396 break;
10397 }
e1190b87 10398 if(itype[j]==UJUMP||itype[j]==RJUMP||(source[j]>>16)==0x1000)
10399 {
10400 // Stop on unconditional branch
10401 break;
10402 }
10403 if(itype[j]==CJUMP||itype[j]==SJUMP||itype[j]==FJUMP)
10404 {
10405 if(ooo[j]) {
10406 if(count_free_regs(regs[j].regmap)<=minimum_free_regs[j+1])
10407 break;
10408 }else{
10409 if(count_free_regs(branch_regs[j].regmap)<=minimum_free_regs[j+1])
10410 break;
10411 }
10412 if(get_reg(branch_regs[j].regmap,f_regmap[hr])>=0) {
10413 //printf("no-match due to different register (branch)\n");
57871462 10414 break;
10415 }
10416 }
e1190b87 10417 if(count_free_regs(regs[j].regmap)<=minimum_free_regs[j]) {
10418 //printf("No free regs for store %x\n",start+j*4);
10419 break;
10420 }
57871462 10421 if(f_regmap[hr]>=64) {
10422 if(regs[j].is32&(1LL<<(f_regmap[hr]&63))) {
10423 break;
10424 }
10425 else
10426 {
10427 if(get_reg(regs[j].regmap,f_regmap[hr]&63)<0) {
10428 break;
10429 }
10430 }
10431 }
10432 }
10433 }
10434 }
10435 }
10436 }
10437 }else{
198df76f 10438 // Non branch or undetermined branch target
57871462 10439 for(hr=0;hr<HOST_REGS;hr++)
10440 {
10441 if(hr!=EXCLUDE_REG) {
10442 if(regs[i].regmap[hr]>64) {
10443 if(!((regs[i].dirty>>hr)&1))
10444 f_regmap[hr]=regs[i].regmap[hr];
10445 }
b372a952 10446 else if(regs[i].regmap[hr]>=0) {
10447 if(f_regmap[hr]!=regs[i].regmap[hr]) {
10448 // dealloc old register
10449 int n;
10450 for(n=0;n<HOST_REGS;n++)
10451 {
10452 if(f_regmap[n]==regs[i].regmap[hr]) {f_regmap[n]=-1;}
10453 }
10454 // and alloc new one
10455 f_regmap[hr]=regs[i].regmap[hr];
10456 }
10457 }
57871462 10458 }
10459 }
10460 // Try to restore cycle count at branch targets
10461 if(bt[i]) {
10462 for(j=i;j<slen-1;j++) {
10463 if(regs[j].regmap[HOST_CCREG]!=-1) break;
e1190b87 10464 if(count_free_regs(regs[j].regmap)<=minimum_free_regs[j]) {
10465 //printf("no free regs for store %x\n",start+j*4);
10466 break;
57871462 10467 }
57871462 10468 }
10469 if(regs[j].regmap[HOST_CCREG]==CCREG) {
10470 int k=i;
10471 //printf("Extend CC, %x -> %x\n",start+k*4,start+j*4);
10472 while(k<j) {
10473 regs[k].regmap_entry[HOST_CCREG]=CCREG;
10474 regs[k].regmap[HOST_CCREG]=CCREG;
10475 regmap_pre[k+1][HOST_CCREG]=CCREG;
10476 regs[k+1].wasdirty|=1<<HOST_CCREG;
10477 regs[k].dirty|=1<<HOST_CCREG;
10478 regs[k].wasconst&=~(1<<HOST_CCREG);
10479 regs[k].isconst&=~(1<<HOST_CCREG);
10480 k++;
10481 }
10482 regs[j].regmap_entry[HOST_CCREG]=CCREG;
10483 }
10484 // Work backwards from the branch target
10485 if(j>i&&f_regmap[HOST_CCREG]==CCREG)
10486 {
10487 //printf("Extend backwards\n");
10488 int k;
10489 k=i;
10490 while(regs[k-1].regmap[HOST_CCREG]==-1) {
e1190b87 10491 if(count_free_regs(regs[k-1].regmap)<=minimum_free_regs[k-1]) {
10492 //printf("no free regs for store %x\n",start+(k-1)*4);
10493 break;
57871462 10494 }
57871462 10495 k--;
10496 }
10497 if(regs[k-1].regmap[HOST_CCREG]==CCREG) {
10498 //printf("Extend CC, %x ->\n",start+k*4);
10499 while(k<=i) {
10500 regs[k].regmap_entry[HOST_CCREG]=CCREG;
10501 regs[k].regmap[HOST_CCREG]=CCREG;
10502 regmap_pre[k+1][HOST_CCREG]=CCREG;
10503 regs[k+1].wasdirty|=1<<HOST_CCREG;
10504 regs[k].dirty|=1<<HOST_CCREG;
10505 regs[k].wasconst&=~(1<<HOST_CCREG);
10506 regs[k].isconst&=~(1<<HOST_CCREG);
10507 k++;
10508 }
10509 }
10510 else {
10511 //printf("Fail Extend CC, %x ->\n",start+k*4);
10512 }
10513 }
10514 }
10515 if(itype[i]!=STORE&&itype[i]!=STORELR&&itype[i]!=C1LS&&itype[i]!=SHIFT&&
10516 itype[i]!=NOP&&itype[i]!=MOV&&itype[i]!=ALU&&itype[i]!=SHIFTIMM&&
10517 itype[i]!=IMM16&&itype[i]!=LOAD&&itype[i]!=COP1&&itype[i]!=FLOAT&&
e1190b87 10518 itype[i]!=FCONV&&itype[i]!=FCOMP)
57871462 10519 {
10520 memcpy(f_regmap,regs[i].regmap,sizeof(f_regmap));
10521 }
10522 }
10523 }
10524
d61de97e 10525 // Cache memory offset or tlb map pointer if a register is available
10526 #ifndef HOST_IMM_ADDR32
10527 #ifndef RAM_OFFSET
10528 if(using_tlb)
10529 #endif
10530 {
10531 int earliest_available[HOST_REGS];
10532 int loop_start[HOST_REGS];
10533 int score[HOST_REGS];
10534 int end[HOST_REGS];
10535 int reg=using_tlb?MMREG:ROREG;
10536
10537 // Init
10538 for(hr=0;hr<HOST_REGS;hr++) {
10539 score[hr]=0;earliest_available[hr]=0;
10540 loop_start[hr]=MAXBLOCK;
10541 }
10542 for(i=0;i<slen-1;i++)
10543 {
10544 // Can't do anything if no registers are available
10545 if(count_free_regs(regs[i].regmap)<=minimum_free_regs[i]) {
10546 for(hr=0;hr<HOST_REGS;hr++) {
10547 score[hr]=0;earliest_available[hr]=i+1;
10548 loop_start[hr]=MAXBLOCK;
10549 }
10550 }
10551 if(itype[i]==UJUMP||itype[i]==RJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP) {
10552 if(!ooo[i]) {
10553 if(count_free_regs(branch_regs[i].regmap)<=minimum_free_regs[i+1]) {
10554 for(hr=0;hr<HOST_REGS;hr++) {
10555 score[hr]=0;earliest_available[hr]=i+1;
10556 loop_start[hr]=MAXBLOCK;
10557 }
10558 }
198df76f 10559 }else{
10560 if(count_free_regs(regs[i].regmap)<=minimum_free_regs[i+1]) {
10561 for(hr=0;hr<HOST_REGS;hr++) {
10562 score[hr]=0;earliest_available[hr]=i+1;
10563 loop_start[hr]=MAXBLOCK;
10564 }
10565 }
d61de97e 10566 }
10567 }
10568 // Mark unavailable registers
10569 for(hr=0;hr<HOST_REGS;hr++) {
10570 if(regs[i].regmap[hr]>=0) {
10571 score[hr]=0;earliest_available[hr]=i+1;
10572 loop_start[hr]=MAXBLOCK;
10573 }
10574 if(itype[i]==UJUMP||itype[i]==RJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP) {
10575 if(branch_regs[i].regmap[hr]>=0) {
10576 score[hr]=0;earliest_available[hr]=i+2;
10577 loop_start[hr]=MAXBLOCK;
10578 }
10579 }
10580 }
10581 // No register allocations after unconditional jumps
10582 if(itype[i]==UJUMP||itype[i]==RJUMP||(source[i]>>16)==0x1000)
10583 {
10584 for(hr=0;hr<HOST_REGS;hr++) {
10585 score[hr]=0;earliest_available[hr]=i+2;
10586 loop_start[hr]=MAXBLOCK;
10587 }
10588 i++; // Skip delay slot too
10589 //printf("skip delay slot: %x\n",start+i*4);
10590 }
10591 else
10592 // Possible match
10593 if(itype[i]==LOAD||itype[i]==LOADLR||
10594 itype[i]==STORE||itype[i]==STORELR||itype[i]==C1LS) {
10595 for(hr=0;hr<HOST_REGS;hr++) {
10596 if(hr!=EXCLUDE_REG) {
10597 end[hr]=i-1;
10598 for(j=i;j<slen-1;j++) {
10599 if(regs[j].regmap[hr]>=0) break;
10600 if(itype[j]==UJUMP||itype[j]==RJUMP||itype[j]==CJUMP||itype[j]==SJUMP||itype[j]==FJUMP) {
10601 if(branch_regs[j].regmap[hr]>=0) break;
10602 if(ooo[j]) {
10603 if(count_free_regs(regs[j].regmap)<=minimum_free_regs[j+1]) break;
10604 }else{
10605 if(count_free_regs(branch_regs[j].regmap)<=minimum_free_regs[j+1]) break;
10606 }
10607 }
10608 else if(count_free_regs(regs[j].regmap)<=minimum_free_regs[j]) break;
10609 if(itype[j]==UJUMP||itype[j]==RJUMP||itype[j]==CJUMP||itype[j]==SJUMP||itype[j]==FJUMP) {
10610 int t=(ba[j]-start)>>2;
10611 if(t<j&&t>=earliest_available[hr]) {
198df76f 10612 if(t==1||(t>1&&itype[t-2]!=UJUMP&&itype[t-2]!=RJUMP)||(t>1&&rt1[t-2]!=31)) { // call/ret assumes no registers allocated
10613 // Score a point for hoisting loop invariant
10614 if(t<loop_start[hr]) loop_start[hr]=t;
10615 //printf("set loop_start: i=%x j=%x (%x)\n",start+i*4,start+j*4,start+t*4);
10616 score[hr]++;
10617 end[hr]=j;
10618 }
d61de97e 10619 }
10620 else if(t<j) {
10621 if(regs[t].regmap[hr]==reg) {
10622 // Score a point if the branch target matches this register
10623 score[hr]++;
10624 end[hr]=j;
10625 }
10626 }
10627 if(itype[j+1]==LOAD||itype[j+1]==LOADLR||
10628 itype[j+1]==STORE||itype[j+1]==STORELR||itype[j+1]==C1LS) {
10629 score[hr]++;
10630 end[hr]=j;
10631 }
10632 }
10633 if(itype[j]==UJUMP||itype[j]==RJUMP||(source[j]>>16)==0x1000)
10634 {
10635 // Stop on unconditional branch
10636 break;
10637 }
10638 else
10639 if(itype[j]==LOAD||itype[j]==LOADLR||
10640 itype[j]==STORE||itype[j]==STORELR||itype[j]==C1LS) {
10641 score[hr]++;
10642 end[hr]=j;
10643 }
10644 }
10645 }
10646 }
10647 // Find highest score and allocate that register
10648 int maxscore=0;
10649 for(hr=0;hr<HOST_REGS;hr++) {
10650 if(hr!=EXCLUDE_REG) {
10651 if(score[hr]>score[maxscore]) {
10652 maxscore=hr;
10653 //printf("highest score: %d %d (%x->%x)\n",score[hr],hr,start+i*4,start+end[hr]*4);
10654 }
10655 }
10656 }
10657 if(score[maxscore]>1)
10658 {
10659 if(i<loop_start[maxscore]) loop_start[maxscore]=i;
10660 for(j=loop_start[maxscore];j<slen&&j<=end[maxscore];j++) {
10661 //if(regs[j].regmap[maxscore]>=0) {printf("oops: %x %x was %d=%d\n",loop_start[maxscore]*4+start,j*4+start,maxscore,regs[j].regmap[maxscore]);}
10662 assert(regs[j].regmap[maxscore]<0);
10663 if(j>loop_start[maxscore]) regs[j].regmap_entry[maxscore]=reg;
10664 regs[j].regmap[maxscore]=reg;
10665 regs[j].dirty&=~(1<<maxscore);
10666 regs[j].wasconst&=~(1<<maxscore);
10667 regs[j].isconst&=~(1<<maxscore);
10668 if(itype[j]==UJUMP||itype[j]==RJUMP||itype[j]==CJUMP||itype[j]==SJUMP||itype[j]==FJUMP) {
10669 branch_regs[j].regmap[maxscore]=reg;
10670 branch_regs[j].wasdirty&=~(1<<maxscore);
10671 branch_regs[j].dirty&=~(1<<maxscore);
10672 branch_regs[j].wasconst&=~(1<<maxscore);
10673 branch_regs[j].isconst&=~(1<<maxscore);
10674 if(itype[j]!=RJUMP&&itype[j]!=UJUMP&&(source[j]>>16)!=0x1000) {
10675 regmap_pre[j+2][maxscore]=reg;
10676 regs[j+2].wasdirty&=~(1<<maxscore);
10677 }
10678 // loop optimization (loop_preload)
10679 int t=(ba[j]-start)>>2;
198df76f 10680 if(t==loop_start[maxscore]) {
10681 if(t==1||(t>1&&itype[t-2]!=UJUMP&&itype[t-2]!=RJUMP)||(t>1&&rt1[t-2]!=31)) // call/ret assumes no registers allocated
10682 regs[t].regmap_entry[maxscore]=reg;
10683 }
d61de97e 10684 }
10685 else
10686 {
10687 if(j<1||(itype[j-1]!=RJUMP&&itype[j-1]!=UJUMP&&itype[j-1]!=CJUMP&&itype[j-1]!=SJUMP&&itype[j-1]!=FJUMP)) {
10688 regmap_pre[j+1][maxscore]=reg;
10689 regs[j+1].wasdirty&=~(1<<maxscore);
10690 }
10691 }
10692 }
10693 i=j-1;
10694 if(itype[j-1]==RJUMP||itype[j-1]==UJUMP||itype[j-1]==CJUMP||itype[j-1]==SJUMP||itype[j-1]==FJUMP) i++; // skip delay slot
10695 for(hr=0;hr<HOST_REGS;hr++) {
10696 score[hr]=0;earliest_available[hr]=i+i;
10697 loop_start[hr]=MAXBLOCK;
10698 }
10699 }
10700 }
10701 }
10702 }
10703 #endif
10704
57871462 10705 // This allocates registers (if possible) one instruction prior
10706 // to use, which can avoid a load-use penalty on certain CPUs.
10707 for(i=0;i<slen-1;i++)
10708 {
10709 if(!i||(itype[i-1]!=UJUMP&&itype[i-1]!=CJUMP&&itype[i-1]!=SJUMP&&itype[i-1]!=RJUMP&&itype[i-1]!=FJUMP))
10710 {
10711 if(!bt[i+1])
10712 {
b9b61529 10713 if(itype[i]==ALU||itype[i]==MOV||itype[i]==LOAD||itype[i]==SHIFTIMM||itype[i]==IMM16
10714 ||((itype[i]==COP1||itype[i]==COP2)&&opcode2[i]<3))
57871462 10715 {
10716 if(rs1[i+1]) {
10717 if((hr=get_reg(regs[i+1].regmap,rs1[i+1]))>=0)
10718 {
10719 if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
10720 {
10721 regs[i].regmap[hr]=regs[i+1].regmap[hr];
10722 regmap_pre[i+1][hr]=regs[i+1].regmap[hr];
10723 regs[i+1].regmap_entry[hr]=regs[i+1].regmap[hr];
10724 regs[i].isconst&=~(1<<hr);
10725 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10726 constmap[i][hr]=constmap[i+1][hr];
10727 regs[i+1].wasdirty&=~(1<<hr);
10728 regs[i].dirty&=~(1<<hr);
10729 }
10730 }
10731 }
10732 if(rs2[i+1]) {
10733 if((hr=get_reg(regs[i+1].regmap,rs2[i+1]))>=0)
10734 {
10735 if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
10736 {
10737 regs[i].regmap[hr]=regs[i+1].regmap[hr];
10738 regmap_pre[i+1][hr]=regs[i+1].regmap[hr];
10739 regs[i+1].regmap_entry[hr]=regs[i+1].regmap[hr];
10740 regs[i].isconst&=~(1<<hr);
10741 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10742 constmap[i][hr]=constmap[i+1][hr];
10743 regs[i+1].wasdirty&=~(1<<hr);
10744 regs[i].dirty&=~(1<<hr);
10745 }
10746 }
10747 }
198df76f 10748 // Preload target address for load instruction (non-constant)
57871462 10749 if(itype[i+1]==LOAD&&rs1[i+1]&&get_reg(regs[i+1].regmap,rs1[i+1])<0) {
10750 if((hr=get_reg(regs[i+1].regmap,rt1[i+1]))>=0)
10751 {
10752 if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
10753 {
10754 regs[i].regmap[hr]=rs1[i+1];
10755 regmap_pre[i+1][hr]=rs1[i+1];
10756 regs[i+1].regmap_entry[hr]=rs1[i+1];
10757 regs[i].isconst&=~(1<<hr);
10758 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10759 constmap[i][hr]=constmap[i+1][hr];
10760 regs[i+1].wasdirty&=~(1<<hr);
10761 regs[i].dirty&=~(1<<hr);
10762 }
10763 }
10764 }
198df76f 10765 // Load source into target register
57871462 10766 if(lt1[i+1]&&get_reg(regs[i+1].regmap,rs1[i+1])<0) {
10767 if((hr=get_reg(regs[i+1].regmap,rt1[i+1]))>=0)
10768 {
10769 if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
10770 {
10771 regs[i].regmap[hr]=rs1[i+1];
10772 regmap_pre[i+1][hr]=rs1[i+1];
10773 regs[i+1].regmap_entry[hr]=rs1[i+1];
10774 regs[i].isconst&=~(1<<hr);
10775 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10776 constmap[i][hr]=constmap[i+1][hr];
10777 regs[i+1].wasdirty&=~(1<<hr);
10778 regs[i].dirty&=~(1<<hr);
10779 }
10780 }
10781 }
198df76f 10782 // Preload map address
57871462 10783 #ifndef HOST_IMM_ADDR32
b9b61529 10784 if(itype[i+1]==LOAD||itype[i+1]==LOADLR||itype[i+1]==STORE||itype[i+1]==STORELR||itype[i+1]==C1LS||itype[i+1]==C2LS) {
57871462 10785 hr=get_reg(regs[i+1].regmap,TLREG);
10786 if(hr>=0) {
10787 int sr=get_reg(regs[i+1].regmap,rs1[i+1]);
10788 if(sr>=0&&((regs[i+1].wasconst>>sr)&1)) {
10789 int nr;
10790 if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
10791 {
10792 regs[i].regmap[hr]=MGEN1+((i+1)&1);
10793 regmap_pre[i+1][hr]=MGEN1+((i+1)&1);
10794 regs[i+1].regmap_entry[hr]=MGEN1+((i+1)&1);
10795 regs[i].isconst&=~(1<<hr);
10796 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10797 constmap[i][hr]=constmap[i+1][hr];
10798 regs[i+1].wasdirty&=~(1<<hr);
10799 regs[i].dirty&=~(1<<hr);
10800 }
10801 else if((nr=get_reg2(regs[i].regmap,regs[i+1].regmap,-1))>=0)
10802 {
10803 // move it to another register
10804 regs[i+1].regmap[hr]=-1;
10805 regmap_pre[i+2][hr]=-1;
10806 regs[i+1].regmap[nr]=TLREG;
10807 regmap_pre[i+2][nr]=TLREG;
10808 regs[i].regmap[nr]=MGEN1+((i+1)&1);
10809 regmap_pre[i+1][nr]=MGEN1+((i+1)&1);
10810 regs[i+1].regmap_entry[nr]=MGEN1+((i+1)&1);
10811 regs[i].isconst&=~(1<<nr);
10812 regs[i+1].isconst&=~(1<<nr);
10813 regs[i].dirty&=~(1<<nr);
10814 regs[i+1].wasdirty&=~(1<<nr);
10815 regs[i+1].dirty&=~(1<<nr);
10816 regs[i+2].wasdirty&=~(1<<nr);
10817 }
10818 }
10819 }
10820 }
10821 #endif
198df76f 10822 // Address for store instruction (non-constant)
b9b61529 10823 if(itype[i+1]==STORE||itype[i+1]==STORELR
10824 ||(opcode[i+1]&0x3b)==0x39||(opcode[i+1]&0x3b)==0x3a) { // SB/SH/SW/SD/SWC1/SDC1/SWC2/SDC2
57871462 10825 if(get_reg(regs[i+1].regmap,rs1[i+1])<0) {
10826 hr=get_reg2(regs[i].regmap,regs[i+1].regmap,-1);
10827 if(hr<0) hr=get_reg(regs[i+1].regmap,-1);
10828 else {regs[i+1].regmap[hr]=AGEN1+((i+1)&1);regs[i+1].isconst&=~(1<<hr);}
10829 assert(hr>=0);
10830 if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
10831 {
10832 regs[i].regmap[hr]=rs1[i+1];
10833 regmap_pre[i+1][hr]=rs1[i+1];
10834 regs[i+1].regmap_entry[hr]=rs1[i+1];
10835 regs[i].isconst&=~(1<<hr);
10836 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10837 constmap[i][hr]=constmap[i+1][hr];
10838 regs[i+1].wasdirty&=~(1<<hr);
10839 regs[i].dirty&=~(1<<hr);
10840 }
10841 }
10842 }
b9b61529 10843 if(itype[i+1]==LOADLR||(opcode[i+1]&0x3b)==0x31||(opcode[i+1]&0x3b)==0x32) { // LWC1/LDC1, LWC2/LDC2
57871462 10844 if(get_reg(regs[i+1].regmap,rs1[i+1])<0) {
10845 int nr;
10846 hr=get_reg(regs[i+1].regmap,FTEMP);
10847 assert(hr>=0);
10848 if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
10849 {
10850 regs[i].regmap[hr]=rs1[i+1];
10851 regmap_pre[i+1][hr]=rs1[i+1];
10852 regs[i+1].regmap_entry[hr]=rs1[i+1];
10853 regs[i].isconst&=~(1<<hr);
10854 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10855 constmap[i][hr]=constmap[i+1][hr];
10856 regs[i+1].wasdirty&=~(1<<hr);
10857 regs[i].dirty&=~(1<<hr);
10858 }
10859 else if((nr=get_reg2(regs[i].regmap,regs[i+1].regmap,-1))>=0)
10860 {
10861 // move it to another register
10862 regs[i+1].regmap[hr]=-1;
10863 regmap_pre[i+2][hr]=-1;
10864 regs[i+1].regmap[nr]=FTEMP;
10865 regmap_pre[i+2][nr]=FTEMP;
10866 regs[i].regmap[nr]=rs1[i+1];
10867 regmap_pre[i+1][nr]=rs1[i+1];
10868 regs[i+1].regmap_entry[nr]=rs1[i+1];
10869 regs[i].isconst&=~(1<<nr);
10870 regs[i+1].isconst&=~(1<<nr);
10871 regs[i].dirty&=~(1<<nr);
10872 regs[i+1].wasdirty&=~(1<<nr);
10873 regs[i+1].dirty&=~(1<<nr);
10874 regs[i+2].wasdirty&=~(1<<nr);
10875 }
10876 }
10877 }
b9b61529 10878 if(itype[i+1]==LOAD||itype[i+1]==LOADLR||itype[i+1]==STORE||itype[i+1]==STORELR/*||itype[i+1]==C1LS||||itype[i+1]==C2LS*/) {
57871462 10879 if(itype[i+1]==LOAD)
10880 hr=get_reg(regs[i+1].regmap,rt1[i+1]);
b9b61529 10881 if(itype[i+1]==LOADLR||(opcode[i+1]&0x3b)==0x31||(opcode[i+1]&0x3b)==0x32) // LWC1/LDC1, LWC2/LDC2
57871462 10882 hr=get_reg(regs[i+1].regmap,FTEMP);
b9b61529 10883 if(itype[i+1]==STORE||itype[i+1]==STORELR||(opcode[i+1]&0x3b)==0x39||(opcode[i+1]&0x3b)==0x3a) { // SWC1/SDC1/SWC2/SDC2
57871462 10884 hr=get_reg(regs[i+1].regmap,AGEN1+((i+1)&1));
10885 if(hr<0) hr=get_reg(regs[i+1].regmap,-1);
10886 }
10887 if(hr>=0&&regs[i].regmap[hr]<0) {
10888 int rs=get_reg(regs[i+1].regmap,rs1[i+1]);
10889 if(rs>=0&&((regs[i+1].wasconst>>rs)&1)) {
10890 regs[i].regmap[hr]=AGEN1+((i+1)&1);
10891 regmap_pre[i+1][hr]=AGEN1+((i+1)&1);
10892 regs[i+1].regmap_entry[hr]=AGEN1+((i+1)&1);
10893 regs[i].isconst&=~(1<<hr);
10894 regs[i+1].wasdirty&=~(1<<hr);
10895 regs[i].dirty&=~(1<<hr);
10896 }
10897 }
10898 }
10899 }
10900 }
10901 }
10902 }
10903
10904 /* Pass 6 - Optimize clean/dirty state */
10905 clean_registers(0,slen-1,1);
10906
10907 /* Pass 7 - Identify 32-bit registers */
a28c6ce8 10908#ifndef FORCE32
57871462 10909 provisional_r32();
10910
10911 u_int r32=0;
10912
10913 for (i=slen-1;i>=0;i--)
10914 {
10915 int hr;
10916 if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
10917 {
10918 if(ba[i]<start || ba[i]>=(start+slen*4))
10919 {
10920 // Branch out of this block, don't need anything
10921 r32=0;
10922 }
10923 else
10924 {
10925 // Internal branch
10926 // Need whatever matches the target
10927 // (and doesn't get overwritten by the delay slot instruction)
10928 r32=0;
10929 int t=(ba[i]-start)>>2;
10930 if(ba[i]>start+i*4) {
10931 // Forward branch
10932 if(!(requires_32bit[t]&~regs[i].was32))
10933 r32|=requires_32bit[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
10934 }else{
10935 // Backward branch
10936 //if(!(regs[t].was32&~unneeded_reg_upper[t]&~regs[i].was32))
10937 // r32|=regs[t].was32&~unneeded_reg_upper[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
10938 if(!(pr32[t]&~regs[i].was32))
10939 r32|=pr32[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
10940 }
10941 }
10942 // Conditional branch may need registers for following instructions
10943 if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000)
10944 {
10945 if(i<slen-2) {
10946 r32|=requires_32bit[i+2];
10947 r32&=regs[i].was32;
10948 // Mark this address as a branch target since it may be called
10949 // upon return from interrupt
10950 bt[i+2]=1;
10951 }
10952 }
10953 // Merge in delay slot
10954 if(!likely[i]) {
10955 // These are overwritten unless the branch is "likely"
10956 // and the delay slot is nullified if not taken
10957 r32&=~(1LL<<rt1[i+1]);
10958 r32&=~(1LL<<rt2[i+1]);
10959 }
10960 // Assume these are needed (delay slot)
10961 if(us1[i+1]>0)
10962 {
10963 if((regs[i].was32>>us1[i+1])&1) r32|=1LL<<us1[i+1];
10964 }
10965 if(us2[i+1]>0)
10966 {
10967 if((regs[i].was32>>us2[i+1])&1) r32|=1LL<<us2[i+1];
10968 }
10969 if(dep1[i+1]&&!((unneeded_reg_upper[i]>>dep1[i+1])&1))
10970 {
10971 if((regs[i].was32>>dep1[i+1])&1) r32|=1LL<<dep1[i+1];
10972 }
10973 if(dep2[i+1]&&!((unneeded_reg_upper[i]>>dep2[i+1])&1))
10974 {
10975 if((regs[i].was32>>dep2[i+1])&1) r32|=1LL<<dep2[i+1];
10976 }
10977 }
1e973cb0 10978 else if(itype[i]==SYSCALL||itype[i]==HLECALL||itype[i]==INTCALL)
57871462 10979 {
10980 // SYSCALL instruction (software interrupt)
10981 r32=0;
10982 }
10983 else if(itype[i]==COP0 && (source[i]&0x3f)==0x18)
10984 {
10985 // ERET instruction (return from interrupt)
10986 r32=0;
10987 }
10988 // Check 32 bits
10989 r32&=~(1LL<<rt1[i]);
10990 r32&=~(1LL<<rt2[i]);
10991 if(us1[i]>0)
10992 {
10993 if((regs[i].was32>>us1[i])&1) r32|=1LL<<us1[i];
10994 }
10995 if(us2[i]>0)
10996 {
10997 if((regs[i].was32>>us2[i])&1) r32|=1LL<<us2[i];
10998 }
10999 if(dep1[i]&&!((unneeded_reg_upper[i]>>dep1[i])&1))
11000 {
11001 if((regs[i].was32>>dep1[i])&1) r32|=1LL<<dep1[i];
11002 }
11003 if(dep2[i]&&!((unneeded_reg_upper[i]>>dep2[i])&1))
11004 {
11005 if((regs[i].was32>>dep2[i])&1) r32|=1LL<<dep2[i];
11006 }
11007 requires_32bit[i]=r32;
11008
11009 // Dirty registers which are 32-bit, require 32-bit input
11010 // as they will be written as 32-bit values
11011 for(hr=0;hr<HOST_REGS;hr++)
11012 {
11013 if(regs[i].regmap_entry[hr]>0&&regs[i].regmap_entry[hr]<64) {
11014 if((regs[i].was32>>regs[i].regmap_entry[hr])&(regs[i].wasdirty>>hr)&1) {
11015 if(!((unneeded_reg_upper[i]>>regs[i].regmap_entry[hr])&1))
11016 requires_32bit[i]|=1LL<<regs[i].regmap_entry[hr];
11017 }
11018 }
11019 }
11020 //requires_32bit[i]=is32[i]&~unneeded_reg_upper[i]; // DEBUG
11021 }
04fd948a 11022#else
11023 for (i=slen-1;i>=0;i--)
11024 {
11025 if(itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
11026 {
11027 // Conditional branch
11028 if((source[i]>>16)!=0x1000&&i<slen-2) {
11029 // Mark this address as a branch target since it may be called
11030 // upon return from interrupt
11031 bt[i+2]=1;
11032 }
11033 }
11034 }
a28c6ce8 11035#endif
57871462 11036
11037 if(itype[slen-1]==SPAN) {
11038 bt[slen-1]=1; // Mark as a branch target so instruction can restart after exception
11039 }
4600ba03 11040
11041#ifdef DISASM
57871462 11042 /* Debug/disassembly */
57871462 11043 for(i=0;i<slen;i++)
11044 {
11045 printf("U:");
11046 int r;
11047 for(r=1;r<=CCREG;r++) {
11048 if((unneeded_reg[i]>>r)&1) {
11049 if(r==HIREG) printf(" HI");
11050 else if(r==LOREG) printf(" LO");
11051 else printf(" r%d",r);
11052 }
11053 }
90ae6d4e 11054#ifndef FORCE32
57871462 11055 printf(" UU:");
11056 for(r=1;r<=CCREG;r++) {
11057 if(((unneeded_reg_upper[i]&~unneeded_reg[i])>>r)&1) {
11058 if(r==HIREG) printf(" HI");
11059 else if(r==LOREG) printf(" LO");
11060 else printf(" r%d",r);
11061 }
11062 }
11063 printf(" 32:");
11064 for(r=0;r<=CCREG;r++) {
11065 //if(((is32[i]>>r)&(~unneeded_reg[i]>>r))&1) {
11066 if((regs[i].was32>>r)&1) {
11067 if(r==CCREG) printf(" CC");
11068 else if(r==HIREG) printf(" HI");
11069 else if(r==LOREG) printf(" LO");
11070 else printf(" r%d",r);
11071 }
11072 }
90ae6d4e 11073#endif
57871462 11074 printf("\n");
11075 #if defined(__i386__) || defined(__x86_64__)
11076 printf("pre: eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",regmap_pre[i][0],regmap_pre[i][1],regmap_pre[i][2],regmap_pre[i][3],regmap_pre[i][5],regmap_pre[i][6],regmap_pre[i][7]);
11077 #endif
11078 #ifdef __arm__
11079 printf("pre: r0=%d r1=%d r2=%d r3=%d r4=%d r5=%d r6=%d r7=%d r8=%d r9=%d r10=%d r12=%d\n",regmap_pre[i][0],regmap_pre[i][1],regmap_pre[i][2],regmap_pre[i][3],regmap_pre[i][4],regmap_pre[i][5],regmap_pre[i][6],regmap_pre[i][7],regmap_pre[i][8],regmap_pre[i][9],regmap_pre[i][10],regmap_pre[i][12]);
11080 #endif
11081 printf("needs: ");
11082 if(needed_reg[i]&1) printf("eax ");
11083 if((needed_reg[i]>>1)&1) printf("ecx ");
11084 if((needed_reg[i]>>2)&1) printf("edx ");
11085 if((needed_reg[i]>>3)&1) printf("ebx ");
11086 if((needed_reg[i]>>5)&1) printf("ebp ");
11087 if((needed_reg[i]>>6)&1) printf("esi ");
11088 if((needed_reg[i]>>7)&1) printf("edi ");
11089 printf("r:");
11090 for(r=0;r<=CCREG;r++) {
11091 //if(((requires_32bit[i]>>r)&(~unneeded_reg[i]>>r))&1) {
11092 if((requires_32bit[i]>>r)&1) {
11093 if(r==CCREG) printf(" CC");
11094 else if(r==HIREG) printf(" HI");
11095 else if(r==LOREG) printf(" LO");
11096 else printf(" r%d",r);
11097 }
11098 }
11099 printf("\n");
11100 /*printf("pr:");
11101 for(r=0;r<=CCREG;r++) {
11102 //if(((requires_32bit[i]>>r)&(~unneeded_reg[i]>>r))&1) {
11103 if((pr32[i]>>r)&1) {
11104 if(r==CCREG) printf(" CC");
11105 else if(r==HIREG) printf(" HI");
11106 else if(r==LOREG) printf(" LO");
11107 else printf(" r%d",r);
11108 }
11109 }
11110 if(pr32[i]!=requires_32bit[i]) printf(" OOPS");
11111 printf("\n");*/
11112 #if defined(__i386__) || defined(__x86_64__)
11113 printf("entry: eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",regs[i].regmap_entry[0],regs[i].regmap_entry[1],regs[i].regmap_entry[2],regs[i].regmap_entry[3],regs[i].regmap_entry[5],regs[i].regmap_entry[6],regs[i].regmap_entry[7]);
11114 printf("dirty: ");
11115 if(regs[i].wasdirty&1) printf("eax ");
11116 if((regs[i].wasdirty>>1)&1) printf("ecx ");
11117 if((regs[i].wasdirty>>2)&1) printf("edx ");
11118 if((regs[i].wasdirty>>3)&1) printf("ebx ");
11119 if((regs[i].wasdirty>>5)&1) printf("ebp ");
11120 if((regs[i].wasdirty>>6)&1) printf("esi ");
11121 if((regs[i].wasdirty>>7)&1) printf("edi ");
11122 #endif
11123 #ifdef __arm__
11124 printf("entry: r0=%d r1=%d r2=%d r3=%d r4=%d r5=%d r6=%d r7=%d r8=%d r9=%d r10=%d r12=%d\n",regs[i].regmap_entry[0],regs[i].regmap_entry[1],regs[i].regmap_entry[2],regs[i].regmap_entry[3],regs[i].regmap_entry[4],regs[i].regmap_entry[5],regs[i].regmap_entry[6],regs[i].regmap_entry[7],regs[i].regmap_entry[8],regs[i].regmap_entry[9],regs[i].regmap_entry[10],regs[i].regmap_entry[12]);
11125 printf("dirty: ");
11126 if(regs[i].wasdirty&1) printf("r0 ");
11127 if((regs[i].wasdirty>>1)&1) printf("r1 ");
11128 if((regs[i].wasdirty>>2)&1) printf("r2 ");
11129 if((regs[i].wasdirty>>3)&1) printf("r3 ");
11130 if((regs[i].wasdirty>>4)&1) printf("r4 ");
11131 if((regs[i].wasdirty>>5)&1) printf("r5 ");
11132 if((regs[i].wasdirty>>6)&1) printf("r6 ");
11133 if((regs[i].wasdirty>>7)&1) printf("r7 ");
11134 if((regs[i].wasdirty>>8)&1) printf("r8 ");
11135 if((regs[i].wasdirty>>9)&1) printf("r9 ");
11136 if((regs[i].wasdirty>>10)&1) printf("r10 ");
11137 if((regs[i].wasdirty>>12)&1) printf("r12 ");
11138 #endif
11139 printf("\n");
11140 disassemble_inst(i);
11141 //printf ("ccadj[%d] = %d\n",i,ccadj[i]);
11142 #if defined(__i386__) || defined(__x86_64__)
11143 printf("eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d dirty: ",regs[i].regmap[0],regs[i].regmap[1],regs[i].regmap[2],regs[i].regmap[3],regs[i].regmap[5],regs[i].regmap[6],regs[i].regmap[7]);
11144 if(regs[i].dirty&1) printf("eax ");
11145 if((regs[i].dirty>>1)&1) printf("ecx ");
11146 if((regs[i].dirty>>2)&1) printf("edx ");
11147 if((regs[i].dirty>>3)&1) printf("ebx ");
11148 if((regs[i].dirty>>5)&1) printf("ebp ");
11149 if((regs[i].dirty>>6)&1) printf("esi ");
11150 if((regs[i].dirty>>7)&1) printf("edi ");
11151 #endif
11152 #ifdef __arm__
11153 printf("r0=%d r1=%d r2=%d r3=%d r4=%d r5=%d r6=%d r7=%d r8=%d r9=%d r10=%d r12=%d dirty: ",regs[i].regmap[0],regs[i].regmap[1],regs[i].regmap[2],regs[i].regmap[3],regs[i].regmap[4],regs[i].regmap[5],regs[i].regmap[6],regs[i].regmap[7],regs[i].regmap[8],regs[i].regmap[9],regs[i].regmap[10],regs[i].regmap[12]);
11154 if(regs[i].dirty&1) printf("r0 ");
11155 if((regs[i].dirty>>1)&1) printf("r1 ");
11156 if((regs[i].dirty>>2)&1) printf("r2 ");
11157 if((regs[i].dirty>>3)&1) printf("r3 ");
11158 if((regs[i].dirty>>4)&1) printf("r4 ");
11159 if((regs[i].dirty>>5)&1) printf("r5 ");
11160 if((regs[i].dirty>>6)&1) printf("r6 ");
11161 if((regs[i].dirty>>7)&1) printf("r7 ");
11162 if((regs[i].dirty>>8)&1) printf("r8 ");
11163 if((regs[i].dirty>>9)&1) printf("r9 ");
11164 if((regs[i].dirty>>10)&1) printf("r10 ");
11165 if((regs[i].dirty>>12)&1) printf("r12 ");
11166 #endif
11167 printf("\n");
11168 if(regs[i].isconst) {
11169 printf("constants: ");
11170 #if defined(__i386__) || defined(__x86_64__)
11171 if(regs[i].isconst&1) printf("eax=%x ",(int)constmap[i][0]);
11172 if((regs[i].isconst>>1)&1) printf("ecx=%x ",(int)constmap[i][1]);
11173 if((regs[i].isconst>>2)&1) printf("edx=%x ",(int)constmap[i][2]);
11174 if((regs[i].isconst>>3)&1) printf("ebx=%x ",(int)constmap[i][3]);
11175 if((regs[i].isconst>>5)&1) printf("ebp=%x ",(int)constmap[i][5]);
11176 if((regs[i].isconst>>6)&1) printf("esi=%x ",(int)constmap[i][6]);
11177 if((regs[i].isconst>>7)&1) printf("edi=%x ",(int)constmap[i][7]);
11178 #endif
11179 #ifdef __arm__
11180 if(regs[i].isconst&1) printf("r0=%x ",(int)constmap[i][0]);
11181 if((regs[i].isconst>>1)&1) printf("r1=%x ",(int)constmap[i][1]);
11182 if((regs[i].isconst>>2)&1) printf("r2=%x ",(int)constmap[i][2]);
11183 if((regs[i].isconst>>3)&1) printf("r3=%x ",(int)constmap[i][3]);
11184 if((regs[i].isconst>>4)&1) printf("r4=%x ",(int)constmap[i][4]);
11185 if((regs[i].isconst>>5)&1) printf("r5=%x ",(int)constmap[i][5]);
11186 if((regs[i].isconst>>6)&1) printf("r6=%x ",(int)constmap[i][6]);
11187 if((regs[i].isconst>>7)&1) printf("r7=%x ",(int)constmap[i][7]);
11188 if((regs[i].isconst>>8)&1) printf("r8=%x ",(int)constmap[i][8]);
11189 if((regs[i].isconst>>9)&1) printf("r9=%x ",(int)constmap[i][9]);
11190 if((regs[i].isconst>>10)&1) printf("r10=%x ",(int)constmap[i][10]);
11191 if((regs[i].isconst>>12)&1) printf("r12=%x ",(int)constmap[i][12]);
11192 #endif
11193 printf("\n");
11194 }
90ae6d4e 11195#ifndef FORCE32
57871462 11196 printf(" 32:");
11197 for(r=0;r<=CCREG;r++) {
11198 if((regs[i].is32>>r)&1) {
11199 if(r==CCREG) printf(" CC");
11200 else if(r==HIREG) printf(" HI");
11201 else if(r==LOREG) printf(" LO");
11202 else printf(" r%d",r);
11203 }
11204 }
11205 printf("\n");
90ae6d4e 11206#endif
57871462 11207 /*printf(" p32:");
11208 for(r=0;r<=CCREG;r++) {
11209 if((p32[i]>>r)&1) {
11210 if(r==CCREG) printf(" CC");
11211 else if(r==HIREG) printf(" HI");
11212 else if(r==LOREG) printf(" LO");
11213 else printf(" r%d",r);
11214 }
11215 }
11216 if(p32[i]!=regs[i].is32) printf(" NO MATCH\n");
11217 else printf("\n");*/
11218 if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP) {
11219 #if defined(__i386__) || defined(__x86_64__)
11220 printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d dirty: ",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
11221 if(branch_regs[i].dirty&1) printf("eax ");
11222 if((branch_regs[i].dirty>>1)&1) printf("ecx ");
11223 if((branch_regs[i].dirty>>2)&1) printf("edx ");
11224 if((branch_regs[i].dirty>>3)&1) printf("ebx ");
11225 if((branch_regs[i].dirty>>5)&1) printf("ebp ");
11226 if((branch_regs[i].dirty>>6)&1) printf("esi ");
11227 if((branch_regs[i].dirty>>7)&1) printf("edi ");
11228 #endif
11229 #ifdef __arm__
11230 printf("branch(%d): r0=%d r1=%d r2=%d r3=%d r4=%d r5=%d r6=%d r7=%d r8=%d r9=%d r10=%d r12=%d dirty: ",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[4],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7],branch_regs[i].regmap[8],branch_regs[i].regmap[9],branch_regs[i].regmap[10],branch_regs[i].regmap[12]);
11231 if(branch_regs[i].dirty&1) printf("r0 ");
11232 if((branch_regs[i].dirty>>1)&1) printf("r1 ");
11233 if((branch_regs[i].dirty>>2)&1) printf("r2 ");
11234 if((branch_regs[i].dirty>>3)&1) printf("r3 ");
11235 if((branch_regs[i].dirty>>4)&1) printf("r4 ");
11236 if((branch_regs[i].dirty>>5)&1) printf("r5 ");
11237 if((branch_regs[i].dirty>>6)&1) printf("r6 ");
11238 if((branch_regs[i].dirty>>7)&1) printf("r7 ");
11239 if((branch_regs[i].dirty>>8)&1) printf("r8 ");
11240 if((branch_regs[i].dirty>>9)&1) printf("r9 ");
11241 if((branch_regs[i].dirty>>10)&1) printf("r10 ");
11242 if((branch_regs[i].dirty>>12)&1) printf("r12 ");
11243 #endif
90ae6d4e 11244#ifndef FORCE32
57871462 11245 printf(" 32:");
11246 for(r=0;r<=CCREG;r++) {
11247 if((branch_regs[i].is32>>r)&1) {
11248 if(r==CCREG) printf(" CC");
11249 else if(r==HIREG) printf(" HI");
11250 else if(r==LOREG) printf(" LO");
11251 else printf(" r%d",r);
11252 }
11253 }
11254 printf("\n");
90ae6d4e 11255#endif
57871462 11256 }
11257 }
4600ba03 11258#endif // DISASM
57871462 11259
11260 /* Pass 8 - Assembly */
11261 linkcount=0;stubcount=0;
11262 ds=0;is_delayslot=0;
11263 cop1_usable=0;
11264 uint64_t is32_pre=0;
11265 u_int dirty_pre=0;
11266 u_int beginning=(u_int)out;
11267 if((u_int)addr&1) {
11268 ds=1;
11269 pagespan_ds();
11270 }
9ad4d757 11271 u_int instr_addr0_override=0;
11272
11273#ifdef PCSX
11274 if (start == 0x80030000) {
11275 // nasty hack for fastbios thing
96186eba 11276 // override block entry to this code
9ad4d757 11277 instr_addr0_override=(u_int)out;
11278 emit_movimm(start,0);
96186eba 11279 // abuse io address var as a flag that we
11280 // have already returned here once
11281 emit_readword((int)&address,1);
9ad4d757 11282 emit_writeword(0,(int)&pcaddr);
96186eba 11283 emit_writeword(0,(int)&address);
9ad4d757 11284 emit_cmp(0,1);
11285 emit_jne((int)new_dyna_leave);
11286 }
11287#endif
57871462 11288 for(i=0;i<slen;i++)
11289 {
11290 //if(ds) printf("ds: ");
4600ba03 11291 disassemble_inst(i);
57871462 11292 if(ds) {
11293 ds=0; // Skip delay slot
11294 if(bt[i]) assem_debug("OOPS - branch into delay slot\n");
11295 instr_addr[i]=0;
11296 } else {
ffb0b9e0 11297 speculate_register_values(i);
57871462 11298 #ifndef DESTRUCTIVE_WRITEBACK
11299 if(i<2||(itype[i-2]!=UJUMP&&itype[i-2]!=RJUMP&&(source[i-2]>>16)!=0x1000))
11300 {
11301 wb_sx(regmap_pre[i],regs[i].regmap_entry,regs[i].wasdirty,is32_pre,regs[i].was32,
11302 unneeded_reg[i],unneeded_reg_upper[i]);
11303 wb_valid(regmap_pre[i],regs[i].regmap_entry,dirty_pre,regs[i].wasdirty,is32_pre,
11304 unneeded_reg[i],unneeded_reg_upper[i]);
11305 }
f776eb14 11306 if((itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)&&!likely[i]) {
11307 is32_pre=branch_regs[i].is32;
11308 dirty_pre=branch_regs[i].dirty;
11309 }else{
11310 is32_pre=regs[i].is32;
11311 dirty_pre=regs[i].dirty;
11312 }
57871462 11313 #endif
11314 // write back
11315 if(i<2||(itype[i-2]!=UJUMP&&itype[i-2]!=RJUMP&&(source[i-2]>>16)!=0x1000))
11316 {
11317 wb_invalidate(regmap_pre[i],regs[i].regmap_entry,regs[i].wasdirty,regs[i].was32,
11318 unneeded_reg[i],unneeded_reg_upper[i]);
11319 loop_preload(regmap_pre[i],regs[i].regmap_entry);
11320 }
11321 // branch target entry point
11322 instr_addr[i]=(u_int)out;
11323 assem_debug("<->\n");
11324 // load regs
11325 if(regs[i].regmap_entry[HOST_CCREG]==CCREG&&regs[i].regmap[HOST_CCREG]!=CCREG)
11326 wb_register(CCREG,regs[i].regmap_entry,regs[i].wasdirty,regs[i].was32);
11327 load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,rs1[i],rs2[i]);
11328 address_generation(i,&regs[i],regs[i].regmap_entry);
11329 load_consts(regmap_pre[i],regs[i].regmap,regs[i].was32,i);
11330 if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
11331 {
11332 // Load the delay slot registers if necessary
4ef8f67d 11333 if(rs1[i+1]!=rs1[i]&&rs1[i+1]!=rs2[i]&&(rs1[i+1]!=rt1[i]||rt1[i]==0))
57871462 11334 load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,rs1[i+1],rs1[i+1]);
4ef8f67d 11335 if(rs2[i+1]!=rs1[i+1]&&rs2[i+1]!=rs1[i]&&rs2[i+1]!=rs2[i]&&(rs2[i+1]!=rt1[i]||rt1[i]==0))
57871462 11336 load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,rs2[i+1],rs2[i+1]);
b9b61529 11337 if(itype[i+1]==STORE||itype[i+1]==STORELR||(opcode[i+1]&0x3b)==0x39||(opcode[i+1]&0x3b)==0x3a)
57871462 11338 load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,INVCP,INVCP);
11339 }
11340 else if(i+1<slen)
11341 {
11342 // Preload registers for following instruction
11343 if(rs1[i+1]!=rs1[i]&&rs1[i+1]!=rs2[i])
11344 if(rs1[i+1]!=rt1[i]&&rs1[i+1]!=rt2[i])
11345 load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,rs1[i+1],rs1[i+1]);
11346 if(rs2[i+1]!=rs1[i+1]&&rs2[i+1]!=rs1[i]&&rs2[i+1]!=rs2[i])
11347 if(rs2[i+1]!=rt1[i]&&rs2[i+1]!=rt2[i])
11348 load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,rs2[i+1],rs2[i+1]);
11349 }
11350 // TODO: if(is_ooo(i)) address_generation(i+1);
11351 if(itype[i]==CJUMP||itype[i]==FJUMP)
11352 load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,CCREG,CCREG);
b9b61529 11353 if(itype[i]==STORE||itype[i]==STORELR||(opcode[i]&0x3b)==0x39||(opcode[i]&0x3b)==0x3a)
57871462 11354 load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,INVCP,INVCP);
11355 if(bt[i]) cop1_usable=0;
11356 // assemble
11357 switch(itype[i]) {
11358 case ALU:
11359 alu_assemble(i,&regs[i]);break;
11360 case IMM16:
11361 imm16_assemble(i,&regs[i]);break;
11362 case SHIFT:
11363 shift_assemble(i,&regs[i]);break;
11364 case SHIFTIMM:
11365 shiftimm_assemble(i,&regs[i]);break;
11366 case LOAD:
11367 load_assemble(i,&regs[i]);break;
11368 case LOADLR:
11369 loadlr_assemble(i,&regs[i]);break;
11370 case STORE:
11371 store_assemble(i,&regs[i]);break;
11372 case STORELR:
11373 storelr_assemble(i,&regs[i]);break;
11374 case COP0:
11375 cop0_assemble(i,&regs[i]);break;
11376 case COP1:
11377 cop1_assemble(i,&regs[i]);break;
11378 case C1LS:
11379 c1ls_assemble(i,&regs[i]);break;
b9b61529 11380 case COP2:
11381 cop2_assemble(i,&regs[i]);break;
11382 case C2LS:
11383 c2ls_assemble(i,&regs[i]);break;
11384 case C2OP:
11385 c2op_assemble(i,&regs[i]);break;
57871462 11386 case FCONV:
11387 fconv_assemble(i,&regs[i]);break;
11388 case FLOAT:
11389 float_assemble(i,&regs[i]);break;
11390 case FCOMP:
11391 fcomp_assemble(i,&regs[i]);break;
11392 case MULTDIV:
11393 multdiv_assemble(i,&regs[i]);break;
11394 case MOV:
11395 mov_assemble(i,&regs[i]);break;
11396 case SYSCALL:
11397 syscall_assemble(i,&regs[i]);break;
7139f3c8 11398 case HLECALL:
11399 hlecall_assemble(i,&regs[i]);break;
1e973cb0 11400 case INTCALL:
11401 intcall_assemble(i,&regs[i]);break;
57871462 11402 case UJUMP:
11403 ujump_assemble(i,&regs[i]);ds=1;break;
11404 case RJUMP:
11405 rjump_assemble(i,&regs[i]);ds=1;break;
11406 case CJUMP:
11407 cjump_assemble(i,&regs[i]);ds=1;break;
11408 case SJUMP:
11409 sjump_assemble(i,&regs[i]);ds=1;break;
11410 case FJUMP:
11411 fjump_assemble(i,&regs[i]);ds=1;break;
11412 case SPAN:
11413 pagespan_assemble(i,&regs[i]);break;
11414 }
11415 if(itype[i]==UJUMP||itype[i]==RJUMP||(source[i]>>16)==0x1000)
11416 literal_pool(1024);
11417 else
11418 literal_pool_jumpover(256);
11419 }
11420 }
11421 //assert(itype[i-2]==UJUMP||itype[i-2]==RJUMP||(source[i-2]>>16)==0x1000);
11422 // If the block did not end with an unconditional branch,
11423 // add a jump to the next instruction.
11424 if(i>1) {
11425 if(itype[i-2]!=UJUMP&&itype[i-2]!=RJUMP&&(source[i-2]>>16)!=0x1000&&itype[i-1]!=SPAN) {
11426 assert(itype[i-1]!=UJUMP&&itype[i-1]!=CJUMP&&itype[i-1]!=SJUMP&&itype[i-1]!=RJUMP&&itype[i-1]!=FJUMP);
11427 assert(i==slen);
11428 if(itype[i-2]!=CJUMP&&itype[i-2]!=SJUMP&&itype[i-2]!=FJUMP) {
11429 store_regs_bt(regs[i-1].regmap,regs[i-1].is32,regs[i-1].dirty,start+i*4);
11430 if(regs[i-1].regmap[HOST_CCREG]!=CCREG)
11431 emit_loadreg(CCREG,HOST_CCREG);
2573466a 11432 emit_addimm(HOST_CCREG,CLOCK_ADJUST(ccadj[i-1]+1),HOST_CCREG);
57871462 11433 }
11434 else if(!likely[i-2])
11435 {
11436 store_regs_bt(branch_regs[i-2].regmap,branch_regs[i-2].is32,branch_regs[i-2].dirty,start+i*4);
11437 assert(branch_regs[i-2].regmap[HOST_CCREG]==CCREG);
11438 }
11439 else
11440 {
11441 store_regs_bt(regs[i-2].regmap,regs[i-2].is32,regs[i-2].dirty,start+i*4);
11442 assert(regs[i-2].regmap[HOST_CCREG]==CCREG);
11443 }
11444 add_to_linker((int)out,start+i*4,0);
11445 emit_jmp(0);
11446 }
11447 }
11448 else
11449 {
11450 assert(i>0);
11451 assert(itype[i-1]!=UJUMP&&itype[i-1]!=CJUMP&&itype[i-1]!=SJUMP&&itype[i-1]!=RJUMP&&itype[i-1]!=FJUMP);
11452 store_regs_bt(regs[i-1].regmap,regs[i-1].is32,regs[i-1].dirty,start+i*4);
11453 if(regs[i-1].regmap[HOST_CCREG]!=CCREG)
11454 emit_loadreg(CCREG,HOST_CCREG);
2573466a 11455 emit_addimm(HOST_CCREG,CLOCK_ADJUST(ccadj[i-1]+1),HOST_CCREG);
57871462 11456 add_to_linker((int)out,start+i*4,0);
11457 emit_jmp(0);
11458 }
11459
11460 // TODO: delay slot stubs?
11461 // Stubs
11462 for(i=0;i<stubcount;i++)
11463 {
11464 switch(stubs[i][0])
11465 {
11466 case LOADB_STUB:
11467 case LOADH_STUB:
11468 case LOADW_STUB:
11469 case LOADD_STUB:
11470 case LOADBU_STUB:
11471 case LOADHU_STUB:
11472 do_readstub(i);break;
11473 case STOREB_STUB:
11474 case STOREH_STUB:
11475 case STOREW_STUB:
11476 case STORED_STUB:
11477 do_writestub(i);break;
11478 case CC_STUB:
11479 do_ccstub(i);break;
11480 case INVCODE_STUB:
11481 do_invstub(i);break;
11482 case FP_STUB:
11483 do_cop1stub(i);break;
11484 case STORELR_STUB:
11485 do_unalignedwritestub(i);break;
11486 }
11487 }
11488
9ad4d757 11489 if (instr_addr0_override)
11490 instr_addr[0] = instr_addr0_override;
11491
57871462 11492 /* Pass 9 - Linker */
11493 for(i=0;i<linkcount;i++)
11494 {
11495 assem_debug("%8x -> %8x\n",link_addr[i][0],link_addr[i][1]);
11496 literal_pool(64);
11497 if(!link_addr[i][2])
11498 {
11499 void *stub=out;
11500 void *addr=check_addr(link_addr[i][1]);
11501 emit_extjump(link_addr[i][0],link_addr[i][1]);
11502 if(addr) {
11503 set_jump_target(link_addr[i][0],(int)addr);
11504 add_link(link_addr[i][1],stub);
11505 }
11506 else set_jump_target(link_addr[i][0],(int)stub);
11507 }
11508 else
11509 {
11510 // Internal branch
11511 int target=(link_addr[i][1]-start)>>2;
11512 assert(target>=0&&target<slen);
11513 assert(instr_addr[target]);
11514 //#ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
11515 //set_jump_target_fillslot(link_addr[i][0],instr_addr[target],link_addr[i][2]>>1);
11516 //#else
11517 set_jump_target(link_addr[i][0],instr_addr[target]);
11518 //#endif
11519 }
11520 }
11521 // External Branch Targets (jump_in)
11522 if(copy+slen*4>(void *)shadow+sizeof(shadow)) copy=shadow;
11523 for(i=0;i<slen;i++)
11524 {
11525 if(bt[i]||i==0)
11526 {
11527 if(instr_addr[i]) // TODO - delay slots (=null)
11528 {
11529 u_int vaddr=start+i*4;
94d23bb9 11530 u_int page=get_page(vaddr);
11531 u_int vpage=get_vpage(vaddr);
57871462 11532 literal_pool(256);
11533 //if(!(is32[i]&(~unneeded_reg_upper[i])&~(1LL<<CCREG)))
a28c6ce8 11534#ifndef FORCE32
57871462 11535 if(!requires_32bit[i])
a28c6ce8 11536#else
11537 if(1)
11538#endif
57871462 11539 {
11540 assem_debug("%8x (%d) <- %8x\n",instr_addr[i],i,start+i*4);
11541 assem_debug("jump_in: %x\n",start+i*4);
11542 ll_add(jump_dirty+vpage,vaddr,(void *)out);
11543 int entry_point=do_dirty_stub(i);
11544 ll_add(jump_in+page,vaddr,(void *)entry_point);
11545 // If there was an existing entry in the hash table,
11546 // replace it with the new address.
11547 // Don't add new entries. We'll insert the
11548 // ones that actually get used in check_addr().
11549 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
11550 if(ht_bin[0]==vaddr) {
11551 ht_bin[1]=entry_point;
11552 }
11553 if(ht_bin[2]==vaddr) {
11554 ht_bin[3]=entry_point;
11555 }
11556 }
11557 else
11558 {
11559 u_int r=requires_32bit[i]|!!(requires_32bit[i]>>32);
11560 assem_debug("%8x (%d) <- %8x\n",instr_addr[i],i,start+i*4);
11561 assem_debug("jump_in: %x (restricted - %x)\n",start+i*4,r);
11562 //int entry_point=(int)out;
11563 ////assem_debug("entry_point: %x\n",entry_point);
11564 //load_regs_entry(i);
11565 //if(entry_point==(int)out)
11566 // entry_point=instr_addr[i];
11567 //else
11568 // emit_jmp(instr_addr[i]);
11569 //ll_add_32(jump_in+page,vaddr,r,(void *)entry_point);
11570 ll_add_32(jump_dirty+vpage,vaddr,r,(void *)out);
11571 int entry_point=do_dirty_stub(i);
11572 ll_add_32(jump_in+page,vaddr,r,(void *)entry_point);
11573 }
11574 }
11575 }
11576 }
11577 // Write out the literal pool if necessary
11578 literal_pool(0);
11579 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
11580 // Align code
11581 if(((u_int)out)&7) emit_addnop(13);
11582 #endif
11583 assert((u_int)out-beginning<MAX_OUTPUT_BLOCK_SIZE);
11584 //printf("shadow buffer: %x-%x\n",(int)copy,(int)copy+slen*4);
11585 memcpy(copy,source,slen*4);
11586 copy+=slen*4;
11587
11588 #ifdef __arm__
11589 __clear_cache((void *)beginning,out);
11590 #endif
11591
11592 // If we're within 256K of the end of the buffer,
11593 // start over from the beginning. (Is 256K enough?)
bdeade46 11594 if((u_int)out>(u_int)BASE_ADDR+(1<<TARGET_SIZE_2)-MAX_OUTPUT_BLOCK_SIZE) out=(u_char *)BASE_ADDR;
57871462 11595
11596 // Trap writes to any of the pages we compiled
11597 for(i=start>>12;i<=(start+slen*4)>>12;i++) {
11598 invalid_code[i]=0;
90ae6d4e 11599#ifndef DISABLE_TLB
57871462 11600 memory_map[i]|=0x40000000;
11601 if((signed int)start>=(signed int)0xC0000000) {
11602 assert(using_tlb);
11603 j=(((u_int)i<<12)+(memory_map[i]<<2)-(u_int)rdram+(u_int)0x80000000)>>12;
11604 invalid_code[j]=0;
11605 memory_map[j]|=0x40000000;
11606 //printf("write protect physical page: %x (virtual %x)\n",j<<12,start);
11607 }
90ae6d4e 11608#endif
57871462 11609 }
9be4ba64 11610 inv_code_start=inv_code_end=~0;
b12c9fb8 11611#ifdef PCSX
b96d3df7 11612 // for PCSX we need to mark all mirrors too
b12c9fb8 11613 if(get_page(start)<(RAM_SIZE>>12))
11614 for(i=start>>12;i<=(start+slen*4)>>12;i++)
b96d3df7 11615 invalid_code[((u_int)0x00000000>>12)|(i&0x1ff)]=
11616 invalid_code[((u_int)0x80000000>>12)|(i&0x1ff)]=
11617 invalid_code[((u_int)0xa0000000>>12)|(i&0x1ff)]=0;
b12c9fb8 11618#endif
57871462 11619
11620 /* Pass 10 - Free memory by expiring oldest blocks */
11621
bdeade46 11622 int end=((((int)out-(int)BASE_ADDR)>>(TARGET_SIZE_2-16))+16384)&65535;
57871462 11623 while(expirep!=end)
11624 {
11625 int shift=TARGET_SIZE_2-3; // Divide into 8 blocks
bdeade46 11626 int base=(int)BASE_ADDR+((expirep>>13)<<shift); // Base address of this block
57871462 11627 inv_debug("EXP: Phase %d\n",expirep);
11628 switch((expirep>>11)&3)
11629 {
11630 case 0:
11631 // Clear jump_in and jump_dirty
11632 ll_remove_matching_addrs(jump_in+(expirep&2047),base,shift);
11633 ll_remove_matching_addrs(jump_dirty+(expirep&2047),base,shift);
11634 ll_remove_matching_addrs(jump_in+2048+(expirep&2047),base,shift);
11635 ll_remove_matching_addrs(jump_dirty+2048+(expirep&2047),base,shift);
11636 break;
11637 case 1:
11638 // Clear pointers
11639 ll_kill_pointers(jump_out[expirep&2047],base,shift);
11640 ll_kill_pointers(jump_out[(expirep&2047)+2048],base,shift);
11641 break;
11642 case 2:
11643 // Clear hash table
11644 for(i=0;i<32;i++) {
11645 int *ht_bin=hash_table[((expirep&2047)<<5)+i];
11646 if((ht_bin[3]>>shift)==(base>>shift) ||
11647 ((ht_bin[3]-MAX_OUTPUT_BLOCK_SIZE)>>shift)==(base>>shift)) {
11648 inv_debug("EXP: Remove hash %x -> %x\n",ht_bin[2],ht_bin[3]);
11649 ht_bin[2]=ht_bin[3]=-1;
11650 }
11651 if((ht_bin[1]>>shift)==(base>>shift) ||
11652 ((ht_bin[1]-MAX_OUTPUT_BLOCK_SIZE)>>shift)==(base>>shift)) {
11653 inv_debug("EXP: Remove hash %x -> %x\n",ht_bin[0],ht_bin[1]);
11654 ht_bin[0]=ht_bin[2];
11655 ht_bin[1]=ht_bin[3];
11656 ht_bin[2]=ht_bin[3]=-1;
11657 }
11658 }
11659 break;
11660 case 3:
11661 // Clear jump_out
dd3a91a1 11662 #ifdef __arm__
11663 if((expirep&2047)==0)
11664 do_clear_cache();
11665 #endif
57871462 11666 ll_remove_matching_addrs(jump_out+(expirep&2047),base,shift);
11667 ll_remove_matching_addrs(jump_out+2048+(expirep&2047),base,shift);
11668 break;
11669 }
11670 expirep=(expirep+1)&65535;
11671 }
11672 return 0;
11673}
b9b61529 11674
11675// vim:shiftwidth=2:expandtab
ARM optimized PCSX fork