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[picodrive.git] / pico / pico_int.h
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cff531af 1/*\r
2 * PicoDrive - Internal Header File\r
3 * (c) Copyright Dave, 2004\r
4 * (C) notaz, 2006-2010\r
5 *\r
6 * This work is licensed under the terms of MAME license.\r
7 * See COPYING file in the top-level directory.\r
8 */\r
cc68a136 9\r
eff55556 10#ifndef PICO_INTERNAL_INCLUDED\r
11#define PICO_INTERNAL_INCLUDED\r
cc68a136 12\r
13#include <stdio.h>\r
14#include <stdlib.h>\r
15#include <string.h>\r
efcba75f 16#include "pico.h"\r
f53f286a 17#include "carthw/carthw.h"\r
cc68a136 18\r
89fa852d 19//\r
20#define USE_POLL_DETECT\r
21\r
eff55556 22#ifndef PICO_INTERNAL\r
23#define PICO_INTERNAL\r
24#endif\r
25#ifndef PICO_INTERNAL_ASM\r
26#define PICO_INTERNAL_ASM\r
27#endif\r
cc68a136 28\r
70357ce5 29// to select core, define EMU_C68K, EMU_M68K or EMU_F68K in your makefile or project\r
cc68a136 30\r
31#ifdef __cplusplus\r
32extern "C" {\r
33#endif\r
34\r
35\r
36// ----------------------- 68000 CPU -----------------------\r
37#ifdef EMU_C68K\r
d4d62665 38#include "../cpu/cyclone/Cyclone.h"\r
3aa1e148 39extern struct Cyclone PicoCpuCM68k, PicoCpuCS68k;\r
40#define SekCyclesLeftNoMCD PicoCpuCM68k.cycles // cycles left for this run\r
7336a99a 41#define SekCyclesLeft \\r
602133e1 42 (((PicoAHW&1) && (PicoOpt & POPT_EN_MCD_PSYNC)) ? (SekCycleAim-SekCycleCnt) : SekCyclesLeftNoMCD)\r
7a1f6e45 43#define SekCyclesLeftS68k \\r
602133e1 44 ((PicoOpt & POPT_EN_MCD_PSYNC) ? (SekCycleAimS68k-SekCycleCntS68k) : PicoCpuCS68k.cycles)\r
ef090115 45#define SekEndTimeslice(after) PicoCpuCM68k.cycles=after\r
07ceafdb 46#define SekEndTimesliceS68k(after) PicoCpuCS68k.cycles=after\r
3aa1e148 47#define SekPc (PicoCpuCM68k.pc-PicoCpuCM68k.membase)\r
48#define SekPcS68k (PicoCpuCS68k.pc-PicoCpuCS68k.membase)\r
d4d62665 49#define SekDar(x) (x < 8 ? PicoCpuCM68k.d[x] : PicoCpuCM68k.a[x - 8])\r
5fadfb1c 50#define SekSr CycloneGetSr(&PicoCpuCM68k)\r
3aa1e148 51#define SekSetStop(x) { PicoCpuCM68k.state_flags&=~1; if (x) { PicoCpuCM68k.state_flags|=1; PicoCpuCM68k.cycles=0; } }\r
52#define SekSetStopS68k(x) { PicoCpuCS68k.state_flags&=~1; if (x) { PicoCpuCS68k.state_flags|=1; PicoCpuCS68k.cycles=0; } }\r
ed4402a7 53#define SekIsStoppedM68k() (PicoCpuCM68k.state_flags&1)\r
ca61ee42 54#define SekIsStoppedS68k() (PicoCpuCS68k.state_flags&1)\r
03e4f2a3 55#define SekShouldInterrupt (PicoCpuCM68k.irq > (PicoCpuCM68k.srh&7))\r
b542be46 56\r
57#define SekInterrupt(i) PicoCpuCM68k.irq=i\r
5fadfb1c 58#define SekIrqLevel PicoCpuCM68k.irq\r
b542be46 59\r
03e4f2a3 60#ifdef EMU_M68K\r
61#define EMU_CORE_DEBUG\r
62#endif\r
cc68a136 63#endif\r
64\r
70357ce5 65#ifdef EMU_F68K\r
66#include "../cpu/fame/fame.h"\r
b542be46 67extern M68K_CONTEXT PicoCpuFM68k, PicoCpuFS68k;\r
3aa1e148 68#define SekCyclesLeftNoMCD PicoCpuFM68k.io_cycle_counter\r
70357ce5 69#define SekCyclesLeft \\r
602133e1 70 (((PicoAHW&1) && (PicoOpt & POPT_EN_MCD_PSYNC)) ? (SekCycleAim-SekCycleCnt) : SekCyclesLeftNoMCD)\r
70357ce5 71#define SekCyclesLeftS68k \\r
602133e1 72 ((PicoOpt & POPT_EN_MCD_PSYNC) ? (SekCycleAimS68k-SekCycleCntS68k) : PicoCpuFS68k.io_cycle_counter)\r
ef090115 73#define SekEndTimeslice(after) PicoCpuFM68k.io_cycle_counter=after\r
07ceafdb 74#define SekEndTimesliceS68k(after) PicoCpuFS68k.io_cycle_counter=after\r
03e4f2a3 75#define SekPc fm68k_get_pc(&PicoCpuFM68k)\r
76#define SekPcS68k fm68k_get_pc(&PicoCpuFS68k)\r
d4d62665 77#define SekDar(x) (x < 8 ? PicoCpuFM68k.dreg[x].D : PicoCpuFM68k.areg[x - 8].D)\r
5fadfb1c 78#define SekSr PicoCpuFM68k.sr\r
70357ce5 79#define SekSetStop(x) { \\r
03e4f2a3 80 PicoCpuFM68k.execinfo &= ~FM68K_HALTED; \\r
81 if (x) { PicoCpuFM68k.execinfo |= FM68K_HALTED; PicoCpuFM68k.io_cycle_counter = 0; } \\r
70357ce5 82}\r
83#define SekSetStopS68k(x) { \\r
03e4f2a3 84 PicoCpuFS68k.execinfo &= ~FM68K_HALTED; \\r
85 if (x) { PicoCpuFS68k.execinfo |= FM68K_HALTED; PicoCpuFS68k.io_cycle_counter = 0; } \\r
70357ce5 86}\r
ed4402a7 87#define SekIsStoppedM68k() (PicoCpuFM68k.execinfo&FM68K_HALTED)\r
ca61ee42 88#define SekIsStoppedS68k() (PicoCpuFS68k.execinfo&FM68K_HALTED)\r
03e4f2a3 89#define SekShouldInterrupt fm68k_would_interrupt()\r
b542be46 90\r
91#define SekInterrupt(irq) PicoCpuFM68k.interrupts[0]=irq\r
5fadfb1c 92#define SekIrqLevel PicoCpuFM68k.interrupts[0]\r
b542be46 93\r
03e4f2a3 94#ifdef EMU_M68K\r
95#define EMU_CORE_DEBUG\r
96#endif\r
cc68a136 97#endif\r
98\r
99#ifdef EMU_M68K\r
100#include "../cpu/musashi/m68kcpu.h"\r
3aa1e148 101extern m68ki_cpu_core PicoCpuMM68k, PicoCpuMS68k;\r
cc68a136 102#ifndef SekCyclesLeft\r
3aa1e148 103#define SekCyclesLeftNoMCD PicoCpuMM68k.cyc_remaining_cycles\r
7336a99a 104#define SekCyclesLeft \\r
602133e1 105 (((PicoAHW&1) && (PicoOpt & POPT_EN_MCD_PSYNC)) ? (SekCycleAim-SekCycleCnt) : SekCyclesLeftNoMCD)\r
7a1f6e45 106#define SekCyclesLeftS68k \\r
602133e1 107 ((PicoOpt & POPT_EN_MCD_PSYNC) ? (SekCycleAimS68k-SekCycleCntS68k) : PicoCpuMS68k.cyc_remaining_cycles)\r
ef090115 108#define SekEndTimeslice(after) SET_CYCLES(after)\r
07ceafdb 109#define SekEndTimesliceS68k(after) PicoCpuMS68k.cyc_remaining_cycles=after\r
3aa1e148 110#define SekPc m68k_get_reg(&PicoCpuMM68k, M68K_REG_PC)\r
111#define SekPcS68k m68k_get_reg(&PicoCpuMS68k, M68K_REG_PC)\r
5fadfb1c 112#define SekDar(x) PicoCpuMM68k.dar[x]\r
113#define SekSr m68k_get_reg(&PicoCpuMM68k, M68K_REG_SR)\r
7a1f6e45 114#define SekSetStop(x) { \\r
3aa1e148 115 if(x) { SET_CYCLES(0); PicoCpuMM68k.stopped=STOP_LEVEL_STOP; } \\r
116 else PicoCpuMM68k.stopped=0; \\r
7a1f6e45 117}\r
118#define SekSetStopS68k(x) { \\r
3aa1e148 119 if(x) { SET_CYCLES(0); PicoCpuMS68k.stopped=STOP_LEVEL_STOP; } \\r
120 else PicoCpuMS68k.stopped=0; \\r
7a1f6e45 121}\r
ed4402a7 122#define SekIsStoppedM68k() (PicoCpuMM68k.stopped==STOP_LEVEL_STOP)\r
ca61ee42 123#define SekIsStoppedS68k() (PicoCpuMS68k.stopped==STOP_LEVEL_STOP)\r
03e4f2a3 124#define SekShouldInterrupt (CPU_INT_LEVEL > FLAG_INT_MASK)\r
b542be46 125\r
71de3cd9 126#define SekInterrupt(irq) { \\r
b542be46 127 void *oldcontext = m68ki_cpu_p; \\r
128 m68k_set_context(&PicoCpuMM68k); \\r
129 m68k_set_irq(irq); \\r
130 m68k_set_context(oldcontext); \\r
131}\r
5fadfb1c 132#define SekIrqLevel (PicoCpuMM68k.int_level >> 8)\r
b542be46 133\r
cc68a136 134#endif\r
ef090115 135#endif // EMU_M68K\r
cc68a136 136\r
137extern int SekCycleCnt; // cycles done in this frame\r
138extern int SekCycleAim; // cycle aim\r
139extern unsigned int SekCycleCntT; // total cycle counter, updated once per frame\r
140\r
b8cbd802 141#define SekCyclesReset() { \\r
142 SekCycleCntT+=SekCycleAim; \\r
143 SekCycleCnt-=SekCycleAim; \\r
144 SekCycleAim=0; \\r
145}\r
cc68a136 146#define SekCyclesBurn(c) SekCycleCnt+=c\r
4b9c5888 147#define SekCyclesDone() (SekCycleAim-SekCyclesLeft) // number of cycles done in this frame (can be checked anywhere)\r
cc68a136 148#define SekCyclesDoneT() (SekCycleCntT+SekCyclesDone()) // total nuber of cycles done for this rom\r
149\r
150#define SekEndRun(after) { \\r
ef090115 151 SekCycleCnt -= SekCyclesLeft - (after); \\r
152 if (SekCycleCnt < 0) SekCycleCnt = 0; \\r
153 SekEndTimeslice(after); \\r
cc68a136 154}\r
155\r
07ceafdb 156#define SekEndRunS68k(after) { \\r
157 SekCycleCntS68k -= SekCyclesLeftS68k - (after); \\r
158 if (SekCycleCntS68k < 0) SekCycleCntS68k = 0; \\r
159 SekEndTimesliceS68k(after); \\r
160}\r
161\r
cc68a136 162extern int SekCycleCntS68k;\r
163extern int SekCycleAimS68k;\r
164\r
bf5fbbb4 165#define SekCyclesResetS68k() { \\r
166 SekCycleCntS68k-=SekCycleAimS68k; \\r
167 SekCycleAimS68k=0; \\r
168}\r
7a1f6e45 169#define SekCyclesDoneS68k() (SekCycleAimS68k-SekCyclesLeftS68k)\r
cc68a136 170\r
03e4f2a3 171#ifdef EMU_CORE_DEBUG\r
99464b62 172extern int dbg_irq_level;\r
ef090115 173#undef SekEndTimeslice\r
2d0b15bb 174#undef SekCyclesBurn\r
175#undef SekEndRun\r
99464b62 176#undef SekInterrupt\r
ef090115 177#define SekEndTimeslice(c)\r
2270612a 178#define SekCyclesBurn(c) c\r
2d0b15bb 179#define SekEndRun(c)\r
99464b62 180#define SekInterrupt(irq) dbg_irq_level=irq\r
2d0b15bb 181#endif\r
cc68a136 182\r
b542be46 183// ----------------------- Z80 CPU -----------------------\r
184\r
b4db550e 185#if defined(_USE_DRZ80)\r
dca310c4 186#include "../cpu/DrZ80/drz80.h"\r
b542be46 187\r
188extern struct DrZ80 drZ80;\r
189\r
190#define z80_run(cycles) ((cycles) - DrZ80Run(&drZ80, cycles))\r
191#define z80_run_nr(cycles) DrZ80Run(&drZ80, cycles)\r
4936aac1 192#define z80_int() drZ80.Z80_IRQ = 1\r
4b9c5888 193\r
194#define z80_cyclesLeft drZ80.cycles\r
19954be1 195#define z80_pc() (drZ80.Z80PC - drZ80.Z80PC_BASE)\r
b542be46 196\r
197#elif defined(_USE_CZ80)\r
dca310c4 198#include "../cpu/cz80/cz80.h"\r
b542be46 199\r
200#define z80_run(cycles) Cz80_Exec(&CZ80, cycles)\r
201#define z80_run_nr(cycles) Cz80_Exec(&CZ80, cycles)\r
202#define z80_int() Cz80_Set_IRQ(&CZ80, 0, HOLD_LINE)\r
4b9c5888 203\r
204#define z80_cyclesLeft (CZ80.ICount - CZ80.ExtraCycles)\r
19954be1 205#define z80_pc() Cz80_Get_Reg(&CZ80, CZ80_PC)\r
b542be46 206\r
207#else\r
208\r
209#define z80_run(cycles) (cycles)\r
210#define z80_run_nr(cycles)\r
211#define z80_int()\r
b542be46 212\r
213#endif\r
214\r
b4db550e 215#define Z80_STATE_SIZE 0x60\r
216\r
4b9c5888 217extern int z80stopCycle; /* in 68k cycles */\r
218extern int z80_cycle_cnt; /* 'done' z80 cycles before z80_run() */\r
219extern int z80_cycle_aim;\r
220extern int z80_scanline;\r
221extern int z80_scanline_cycles; /* cycles done until z80_scanline */\r
222\r
223#define z80_resetCycles() \\r
224 z80_cycle_cnt = z80_cycle_aim = z80_scanline = z80_scanline_cycles = 0;\r
225\r
226#define z80_cyclesDone() \\r
227 (z80_cycle_aim - z80_cyclesLeft)\r
228\r
229#define cycles_68k_to_z80(x) ((x)*957 >> 11)\r
230\r
acd35d4c 231// ----------------------- SH2 CPU -----------------------\r
232\r
41397701 233#include "cpu/sh2/sh2.h"\r
acd35d4c 234\r
1d7a28a7 235extern SH2 sh2s[2];\r
236#define msh2 sh2s[0]\r
237#define ssh2 sh2s[1]\r
238\r
679af8a3 239#ifndef DRC_SH2\r
a8fd6e37 240# define ash2_end_run(after) do { \\r
241 if (sh2->icount > (after)) { \\r
242 sh2->cycles_timeslice -= sh2->icount; \\r
243 sh2->icount = after; \\r
244 } \\r
245} while (0)\r
ed4402a7 246# define ash2_cycles_done() (sh2->cycles_timeslice - sh2->icount)\r
679af8a3 247#else\r
a8fd6e37 248# define ash2_end_run(after) do { \\r
249 int left = sh2->sr >> 12; \\r
250 if (left > (after)) { \\r
251 sh2->cycles_timeslice -= left; \\r
252 sh2->sr &= 0xfff; \\r
253 sh2->sr |= (after) << 12; \\r
254 } \\r
255} while (0)\r
ed4402a7 256# define ash2_cycles_done() (sh2->cycles_timeslice - (sh2->sr >> 12))\r
679af8a3 257#endif\r
266c6afa 258\r
679af8a3 259//#define sh2_pc(c) (c) ? ssh2.ppc : msh2.ppc\r
260#define sh2_pc(c) (c) ? ssh2.pc : msh2.pc\r
4ea707e1 261#define sh2_reg(c, x) (c) ? ssh2.r[x] : msh2.r[x]\r
262#define sh2_gbr(c) (c) ? ssh2.gbr : msh2.gbr\r
263#define sh2_vbr(c) (c) ? ssh2.vbr : msh2.vbr\r
6add7875 264#define sh2_sr(c) (((c) ? ssh2.sr : msh2.sr) & 0xfff)\r
acd35d4c 265\r
83ff19ec 266#define sh2_set_gbr(c, v) \\r
267 { if (c) ssh2.gbr = v; else msh2.gbr = v; }\r
268#define sh2_set_vbr(c, v) \\r
269 { if (c) ssh2.vbr = v; else msh2.vbr = v; }\r
270\r
cc68a136 271// ---------------------------------------------------------\r
272\r
273// main oscillator clock which controls timing\r
274#define OSC_NTSC 53693100\r
b8cbd802 275#define OSC_PAL 53203424\r
cc68a136 276\r
277struct PicoVideo\r
278{\r
279 unsigned char reg[0x20];\r
b8cbd802 280 unsigned int command; // 32-bit Command\r
281 unsigned char pending; // 1 if waiting for second half of 32-bit command\r
282 unsigned char type; // Command type (v/c/vsram read/write)\r
283 unsigned short addr; // Read/Write address\r
284 int status; // Status bits\r
cc68a136 285 unsigned char pending_ints; // pending interrupts: ??VH????\r
b8cbd802 286 signed char lwrite_cnt; // VDP write count during active display line\r
9761a7d0 287 unsigned short v_counter; // V-counter\r
288 unsigned char pad[0x10];\r
cc68a136 289};\r
290\r
291struct PicoMisc\r
292{\r
293 unsigned char rotate;\r
294 unsigned char z80Run;\r
e5503e2f 295 unsigned char padTHPhase[2]; // 02 phase of gamepad TH switches\r
2aa27095 296 unsigned short scanline; // 04 0 to 261||311\r
e5503e2f 297 char dirtyPal; // 06 Is the palette dirty (1 - change @ this frame, 2 - some time before)\r
298 unsigned char hardware; // 07 Hardware value for country\r
299 unsigned char pal; // 08 1=PAL 0=NTSC\r
45f2f245 300 unsigned char sram_reg; // 09 SRAM reg. See SRR_* below\r
e5503e2f 301 unsigned short z80_bank68k; // 0a\r
be2c4208 302 unsigned short pad0;\r
303 unsigned char pad1;\r
0ace9b9a 304 unsigned char z80_reset; // 0f z80 reset held\r
e5503e2f 305 unsigned char padDelay[2]; // 10 gamepad phase time outs, so we count a delay\r
1dceadae 306 unsigned short eeprom_addr; // EEPROM address register\r
45f2f245 307 unsigned char eeprom_cycle; // EEPROM cycle number\r
1dceadae 308 unsigned char eeprom_slave; // EEPROM slave word for X24C02 and better SRAMs\r
45f2f245 309 unsigned char eeprom_status;\r
be2c4208 310 unsigned char pad2;\r
053fd9b4 311 unsigned short dma_xfers; // 18\r
45f2f245 312 unsigned char eeprom_wb[2]; // EEPROM latch/write buffer\r
053fd9b4 313 unsigned int frame_count; // 1c for movies and idle det\r
cc68a136 314};\r
315\r
b4db550e 316struct PicoMS\r
317{\r
318 unsigned char carthw[0x10];\r
319 unsigned char io_ctl;\r
320 unsigned char pad[0x4f];\r
321};\r
322\r
cc68a136 323// some assembly stuff depend on these, do not touch!\r
324struct Pico\r
325{\r
326 unsigned char ram[0x10000]; // 0x00000 scratch ram\r
200772b7 327 union { // vram is byteswapped for easier reads when drawing\r
2ec9bec5 328 unsigned short vram[0x8000]; // 0x10000\r
329 unsigned char vramb[0x4000]; // VRAM in SMS mode\r
330 };\r
cc68a136 331 unsigned char zram[0x2000]; // 0x20000 Z80 ram\r
b4db550e 332 unsigned char ioports[0x10]; // XXX: fix asm and mv\r
333 unsigned char pad[0xf0]; // unused\r
cc68a136 334 unsigned short cram[0x40]; // 0x22100\r
335 unsigned short vsram[0x40]; // 0x22180\r
336\r
337 unsigned char *rom; // 0x22200\r
338 unsigned int romsize; // 0x22204\r
339\r
340 struct PicoMisc m;\r
341 struct PicoVideo video;\r
b4db550e 342 struct PicoMS ms;\r
cc68a136 343};\r
344\r
345// sram\r
45f2f245 346#define SRR_MAPPED (1 << 0)\r
347#define SRR_READONLY (1 << 1)\r
348\r
349#define SRF_ENABLED (1 << 0)\r
350#define SRF_EEPROM (1 << 1)\r
af37bca8 351\r
cc68a136 352struct PicoSRAM\r
353{\r
4ff2d527 354 unsigned char *data; // actual data\r
355 unsigned int start; // start address in 68k address space\r
cc68a136 356 unsigned int end;\r
45f2f245 357 unsigned char flags; // 0c: SRF_*\r
1dceadae 358 unsigned char unused2;\r
cc68a136 359 unsigned char changed;\r
45f2f245 360 unsigned char eeprom_type; // eeprom type: 0: 7bit (24C01), 2: 2 addr words (X24C02+), 3: 3 addr words\r
361 unsigned char unused3;\r
1dceadae 362 unsigned char eeprom_bit_cl; // bit number for cl\r
363 unsigned char eeprom_bit_in; // bit number for in\r
364 unsigned char eeprom_bit_out; // bit number for out\r
45f2f245 365 unsigned int size;\r
cc68a136 366};\r
367\r
368// MCD\r
369#include "cd/cd_sys.h"\r
370#include "cd/LC89510.h"\r
d1df8786 371#include "cd/gfx_cd.h"\r
cc68a136 372\r
4f265db7 373struct mcd_pcm\r
374{\r
375 unsigned char control; // reg7\r
376 unsigned char enabled; // reg8\r
377 unsigned char cur_ch;\r
378 unsigned char bank;\r
379 int pad1;\r
380\r
4ff2d527 381 struct pcm_chan // 08, size 0x10\r
4f265db7 382 {\r
383 unsigned char regs[8];\r
4ff2d527 384 unsigned int addr; // .08: played sample address\r
4f265db7 385 int pad;\r
386 } ch[8];\r
387};\r
388\r
c459aefd 389struct mcd_misc\r
390{\r
391 unsigned short hint_vector;\r
392 unsigned char busreq;\r
51a902ae 393 unsigned char s68k_pend_ints;\r
ef090115 394 unsigned int state_flags; // 04: emu state: reset_pending\r
51a902ae 395 unsigned int counter75hz;\r
c9e1affc 396 unsigned int pad0;\r
4ff2d527 397 int timer_int3; // 10\r
4f265db7 398 unsigned int timer_stopwatch;\r
6cadc2da 399 unsigned char bcram_reg; // 18: battery-backed RAM cart register\r
400 unsigned char pad2;\r
401 unsigned short pad3;\r
402 int pad[9];\r
c459aefd 403};\r
404\r
cc68a136 405typedef struct\r
406{\r
4ff2d527 407 unsigned char bios[0x20000]; // 000000: 128K\r
408 union { // 020000: 512K\r
fa1e5e29 409 unsigned char prg_ram[0x80000];\r
cc68a136 410 unsigned char prg_ram_b[4][0x20000];\r
411 };\r
4ff2d527 412 union { // 0a0000: 256K\r
fa1e5e29 413 struct {\r
414 unsigned char word_ram2M[0x40000];\r
dca310c4 415 unsigned char unused0[0x20000];\r
fa1e5e29 416 };\r
417 struct {\r
dca310c4 418 unsigned char unused1[0x20000];\r
fa1e5e29 419 unsigned char word_ram1M[2][0x20000];\r
420 };\r
421 };\r
4ff2d527 422 union { // 100000: 64K\r
fa1e5e29 423 unsigned char pcm_ram[0x10000];\r
4f265db7 424 unsigned char pcm_ram_b[0x10][0x1000];\r
425 };\r
4ff2d527 426 unsigned char s68k_regs[0x200]; // 110000: GA, not CPU regs\r
427 unsigned char bram[0x2000]; // 110200: 8K\r
428 struct mcd_misc m; // 112200: misc\r
429 struct mcd_pcm pcm; // 112240:\r
75736070 430 _scd_toc TOC; // not to be saved\r
cc68a136 431 CDD cdd;\r
432 CDC cdc;\r
433 _scd scd;\r
d1df8786 434 Rot_Comp rot_comp;\r
cc68a136 435} mcd_state;\r
436\r
be2c4208 437// XXX: this will need to be reworked for cart+cd support.\r
cc68a136 438#define Pico_mcd ((mcd_state *)Pico.rom)\r
439\r
be2c4208 440// 32X\r
acd35d4c 441#define P32XS_FM (1<<15)\r
83ff19ec 442#define P32XS_REN (1<< 7)\r
443#define P32XS_nRES (1<< 1)\r
444#define P32XS_ADEN (1<< 0)\r
acd35d4c 445#define P32XS2_ADEN (1<< 9)\r
5e128c6d 446#define P32XS_FULL (1<< 7) // DREQ FIFO full\r
4ea707e1 447#define P32XS_68S (1<< 2)\r
97d3f47f 448#define P32XS_DMA (1<< 1)\r
4ea707e1 449#define P32XS_RV (1<< 0)\r
acd35d4c 450\r
5e128c6d 451#define P32XV_nPAL (1<<15) // VDP\r
acd35d4c 452#define P32XV_PRI (1<< 7)\r
4ea707e1 453#define P32XV_Mx (3<< 0) // display mode mask\r
974fdb5b 454\r
e51e5983 455#define P32XV_SFT (1<< 0)\r
456\r
acd35d4c 457#define P32XV_VBLK (1<<15)\r
458#define P32XV_HBLK (1<<14)\r
459#define P32XV_PEN (1<<13)\r
460#define P32XV_nFEN (1<< 1)\r
461#define P32XV_FS (1<< 0)\r
974fdb5b 462\r
db1d3564 463#define P32XP_FULL (1<<15) // PWM\r
464#define P32XP_EMPTY (1<<14)\r
465\r
4ea707e1 466#define P32XF_68KPOLL (1 << 0)\r
467#define P32XF_MSH2POLL (1 << 1)\r
468#define P32XF_SSH2POLL (1 << 2)\r
469#define P32XF_68KVPOLL (1 << 3)\r
470#define P32XF_MSH2VPOLL (1 << 4)\r
471#define P32XF_SSH2VPOLL (1 << 5)\r
a8fd6e37 472#define P32XF_PWM_PEND (1 << 6)\r
4ea707e1 473\r
474#define P32XI_VRES (1 << 14/2) // IRL/2\r
475#define P32XI_VINT (1 << 12/2)\r
476#define P32XI_HINT (1 << 10/2)\r
477#define P32XI_CMD (1 << 8/2)\r
478#define P32XI_PWM (1 << 6/2)\r
479\r
1d7a28a7 480// peripheral reg access\r
481#define PREG8(regs,offs) ((unsigned char *)regs)[offs ^ 3]\r
482\r
4ea707e1 483// real one is 4*2, but we use more because we don't lockstep\r
484#define DMAC_FIFO_LEN (4*4)\r
db1d3564 485#define PWM_BUFF_LEN 1024 // in one channel samples\r
266c6afa 486\r
f4bb5d6b 487#define SH2_DRCBLK_RAM_SHIFT 1\r
488#define SH2_DRCBLK_DA_SHIFT 1\r
489\r
e05b81fc 490#define SH2_WRITE_SHIFT 25\r
491\r
be2c4208 492struct Pico32x\r
493{\r
494 unsigned short regs[0x20];\r
5a681086 495 unsigned short vdp_regs[0x10]; // 0x40\r
496 unsigned short sh2_regs[3]; // 0x60\r
be2c4208 497 unsigned char pending_fb;\r
974fdb5b 498 unsigned char dirty_pal;\r
266c6afa 499 unsigned int emu_flags;\r
4ea707e1 500 unsigned char sh2irq_mask[2];\r
501 unsigned char sh2irqi[2]; // individual\r
502 unsigned int sh2irqs; // common irqs\r
503 unsigned short dmac_fifo[DMAC_FIFO_LEN];\r
504 unsigned int dmac_ptr;\r
db1d3564 505 unsigned int pwm_irq_sample_cnt;\r
a8fd6e37 506 unsigned char comm_dirty_68k;\r
507 unsigned char comm_dirty_sh2;\r
508 unsigned short pad;\r
509 unsigned int reserved[8];\r
974fdb5b 510};\r
511\r
512struct Pico32xMem\r
513{\r
514 unsigned char sdram[0x40000];\r
f4bb5d6b 515#ifdef DRC_SH2\r
516 unsigned short drcblk_ram[1 << (18 - SH2_DRCBLK_RAM_SHIFT)];\r
517#endif\r
b78efee2 518 unsigned short dram[2][0x20000/2]; // AKA fb\r
b4db550e 519 union {\r
520 unsigned char m68k_rom[0x100];\r
521 unsigned char m68k_rom_bank[0x10000]; // M68K_BANK_SIZE\r
522 };\r
b78efee2 523 unsigned char data_array[2][0x1000]; // cache in SH2s (can be used as RAM)\r
f4bb5d6b 524#ifdef DRC_SH2\r
525 unsigned short drcblk_da[2][1 << (12 - SH2_DRCBLK_DA_SHIFT)];\r
526#endif\r
acd35d4c 527 unsigned char sh2_rom_m[0x800];\r
528 unsigned char sh2_rom_s[0x400];\r
974fdb5b 529 unsigned short pal[0x100];\r
5e128c6d 530 unsigned short pal_native[0x100]; // converted to native (for renderer)\r
4ea707e1 531 unsigned int sh2_peri_regs[2][0x200/4]; // periphereal regs of SH2s\r
db1d3564 532 signed short pwm[2*PWM_BUFF_LEN]; // PWM buffer for current frame\r
be2c4208 533};\r
d49b10c2 534\r
c8d1e9b6 535// area.c\r
fad24893 536extern void (*PicoLoadStateHook)(void);\r
51a902ae 537\r
945c2fdc 538typedef struct {\r
539 int chunk;\r
540 int size;\r
541 void *ptr;\r
542} carthw_state_chunk;\r
543extern carthw_state_chunk *carthw_chunks;\r
544#define CHUNK_CARTHW 64\r
545\r
c8d1e9b6 546// cart.c\r
b4db550e 547extern int PicoCartResize(int newsize);\r
548extern void Byteswap(void *dst, const void *src, int len);\r
45f2f245 549extern void (*PicoCartMemSetup)(void);\r
e807ac75 550extern void (*PicoCartUnloadHook)(void);\r
1dceadae 551\r
c8d1e9b6 552// debug.c\r
b5e5172d 553int CM_compareRun(int cyc, int is_sub);\r
03e4f2a3 554\r
c8d1e9b6 555// draw.c\r
eff55556 556PICO_INTERNAL void PicoFrameStart(void);\r
b6d7ac70 557void PicoDrawSync(int to, int blank_last_line);\r
200772b7 558void BackFill(int reg7, int sh);\r
5a681086 559void FinalizeLine555(int sh, int line);\r
f4750ee0 560extern int (*PicoScanBegin)(unsigned int num);\r
561extern int (*PicoScanEnd)(unsigned int num);\r
b6d7ac70 562extern int DrawScanline;\r
f579f7b8 563#define MAX_LINE_SPRITES 29\r
564extern unsigned char HighLnSpr[240][3 + MAX_LINE_SPRITES];\r
5a681086 565extern void *DrawLineDestBase;\r
566extern int DrawLineDestIncrement;\r
cc68a136 567\r
c8d1e9b6 568// draw2.c\r
eff55556 569PICO_INTERNAL void PicoFrameFull();\r
cc68a136 570\r
200772b7 571// mode4.c\r
572void PicoFrameStartMode4(void);\r
573void PicoLineMode4(int line);\r
574void PicoDoHighPal555M4(void);\r
5a681086 575void PicoDrawSetOutputMode4(pdso_t which);\r
200772b7 576\r
c8d1e9b6 577// memory.c\r
eff55556 578PICO_INTERNAL void PicoMemSetup(void);\r
af37bca8 579unsigned int PicoRead8_io(unsigned int a);\r
580unsigned int PicoRead16_io(unsigned int a);\r
581void PicoWrite8_io(unsigned int a, unsigned int d);\r
582void PicoWrite16_io(unsigned int a, unsigned int d);\r
583\r
584// pico/memory.c\r
585PICO_INTERNAL void PicoMemSetupPico(void);\r
cc68a136 586\r
c8d1e9b6 587// cd/memory.c\r
eff55556 588PICO_INTERNAL void PicoMemSetupCD(void);\r
0ace9b9a 589void PicoMemStateLoaded(void);\r
cc68a136 590\r
c8d1e9b6 591// pico.c\r
cc68a136 592extern struct Pico Pico;\r
593extern struct PicoSRAM SRam;\r
5f9a0d16 594extern int PicoPadInt[2];\r
cc68a136 595extern int emustatus;\r
5e128c6d 596extern int scanlines_total;\r
f8ef8ff7 597extern void (*PicoResetHook)(void);\r
b0677887 598extern void (*PicoLineHook)(void);\r
1e6b5e39 599PICO_INTERNAL int CheckDMA(void);\r
600PICO_INTERNAL void PicoDetectRegion(void);\r
4b9c5888 601PICO_INTERNAL void PicoSyncZ80(int m68k_cycles_done);\r
cc68a136 602\r
c8d1e9b6 603// cd/pico.c\r
2aa27095 604PICO_INTERNAL void PicoInitMCD(void);\r
e5f426aa 605PICO_INTERNAL void PicoExitMCD(void);\r
1cb1584b 606PICO_INTERNAL void PicoPowerMCD(void);\r
2aa27095 607PICO_INTERNAL int PicoResetMCD(void);\r
608PICO_INTERNAL void PicoFrameMCD(void);\r
cc68a136 609\r
c8d1e9b6 610// pico/pico.c\r
2aa27095 611PICO_INTERNAL void PicoInitPico(void);\r
ed367a3f 612PICO_INTERNAL void PicoReratePico(void);\r
9037e45d 613\r
c8d1e9b6 614// pico/xpcm.c\r
ef4eb506 615PICO_INTERNAL void PicoPicoPCMUpdate(short *buffer, int length, int stereo);\r
616PICO_INTERNAL void PicoPicoPCMReset(void);\r
213c16ad 617PICO_INTERNAL void PicoPicoPCMRerate(int xpcm_rate);\r
ef4eb506 618\r
c8d1e9b6 619// sek.c\r
2aa27095 620PICO_INTERNAL void SekInit(void);\r
621PICO_INTERNAL int SekReset(void);\r
3aa1e148 622PICO_INTERNAL void SekState(int *data);\r
eff55556 623PICO_INTERNAL void SekSetRealTAS(int use_real);\r
b4db550e 624PICO_INTERNAL void SekPackCpu(unsigned char *cpu, int is_sub);\r
625PICO_INTERNAL void SekUnpackCpu(const unsigned char *cpu, int is_sub);\r
5f9a0d16 626void SekStepM68k(void);\r
053fd9b4 627void SekInitIdleDet(void);\r
628void SekFinishIdleDet(void);\r
cc68a136 629\r
c8d1e9b6 630// cd/sek.c\r
2aa27095 631PICO_INTERNAL void SekInitS68k(void);\r
632PICO_INTERNAL int SekResetS68k(void);\r
633PICO_INTERNAL int SekInterruptS68k(int irq);\r
cc68a136 634\r
7a93adeb 635// sound/sound.c\r
c9e1affc 636PICO_INTERNAL void cdda_start_play();\r
637extern short cdda_out_buffer[2*1152];\r
7a93adeb 638extern int PsndLen_exc_cnt;\r
639extern int PsndLen_exc_add;\r
48dc74f2 640extern int timer_a_next_oflow, timer_a_step; // in z80 cycles\r
641extern int timer_b_next_oflow, timer_b_step;\r
43e6eaad 642\r
643void ym2612_sync_timers(int z80_cycles, int mode_old, int mode_new);\r
d2721b08 644void ym2612_pack_state(void);\r
453d2a6e 645void ym2612_unpack_state(void);\r
4b9c5888 646\r
e53704e6 647#define TIMER_NO_OFLOW 0x70000000\r
45a1ef71 648// tA = 72 * (1024 - NA) / M\r
649#define TIMER_A_TICK_ZCYCLES 17203\r
650// tB = 1152 * (256 - NA) / M\r
651#define TIMER_B_TICK_ZCYCLES 262800 // 275251 broken, see Dai Makaimura\r
e53704e6 652\r
4b9c5888 653#define timers_cycle() \\r
e53704e6 654 if (timer_a_next_oflow > 0 && timer_a_next_oflow < TIMER_NO_OFLOW) \\r
43e6eaad 655 timer_a_next_oflow -= Pico.m.pal ? 70938*256 : 59659*256; \\r
e53704e6 656 if (timer_b_next_oflow > 0 && timer_b_next_oflow < TIMER_NO_OFLOW) \\r
43e6eaad 657 timer_b_next_oflow -= Pico.m.pal ? 70938*256 : 59659*256; \\r
658 ym2612_sync_timers(0, ym2612.OPN.ST.mode, ym2612.OPN.ST.mode);\r
4b9c5888 659\r
660#define timers_reset() \\r
e53704e6 661 timer_a_next_oflow = timer_b_next_oflow = TIMER_NO_OFLOW; \\r
48dc74f2 662 timer_a_step = TIMER_A_TICK_ZCYCLES * 1024; \\r
663 timer_b_step = TIMER_B_TICK_ZCYCLES * 256;\r
43e6eaad 664\r
7a93adeb 665\r
c8d1e9b6 666// videoport.c\r
eff55556 667PICO_INTERNAL_ASM void PicoVideoWrite(unsigned int a,unsigned short d);\r
668PICO_INTERNAL_ASM unsigned int PicoVideoRead(unsigned int a);\r
9761a7d0 669PICO_INTERNAL_ASM unsigned int PicoVideoRead8(unsigned int a);\r
5de27868 670extern int (*PicoDmaHook)(unsigned int source, int len, unsigned short **srcp, unsigned short **limitp);\r
cc68a136 671\r
c8d1e9b6 672// misc.c\r
eff55556 673PICO_INTERNAL_ASM void memcpy16(unsigned short *dest, unsigned short *src, int count);\r
674PICO_INTERNAL_ASM void memcpy16bswap(unsigned short *dest, void *src, int count);\r
675PICO_INTERNAL_ASM void memcpy32(int *dest, int *src, int count); // 32bit word count\r
676PICO_INTERNAL_ASM void memset32(int *dest, int c, int count);\r
cc68a136 677\r
45f2f245 678// eeprom.c\r
679void EEPROM_write8(unsigned int a, unsigned int d);\r
680void EEPROM_write16(unsigned int d);\r
681unsigned int EEPROM_read(void);\r
682\r
c8d1e9b6 683// z80 functionality wrappers\r
684PICO_INTERNAL void z80_init(void);\r
b4db550e 685PICO_INTERNAL void z80_pack(void *data);\r
686PICO_INTERNAL int z80_unpack(const void *data);\r
c8d1e9b6 687PICO_INTERNAL void z80_reset(void);\r
688PICO_INTERNAL void z80_exit(void);\r
c8d1e9b6 689\r
690// cd/misc.c\r
eff55556 691PICO_INTERNAL_ASM void wram_2M_to_1M(unsigned char *m);\r
692PICO_INTERNAL_ASM void wram_1M_to_2M(unsigned char *m);\r
693\r
694// cd/buffering.c\r
695PICO_INTERNAL void PicoCDBufferRead(void *dest, int lba);\r
696\r
697// sound/sound.c\r
9d917eea 698PICO_INTERNAL void PsndReset(void);\r
4b9c5888 699PICO_INTERNAL void PsndDoDAC(int line_to);\r
9d917eea 700PICO_INTERNAL void PsndClear(void);\r
7b3f44c6 701PICO_INTERNAL void PsndGetSamples(int y);\r
2ec9bec5 702PICO_INTERNAL void PsndGetSamplesMS(void);\r
4b9c5888 703extern int PsndDacLine;\r
cc68a136 704\r
3e49ffd0 705// sms.c\r
f3a57b2d 706#ifndef NO_SMS\r
3e49ffd0 707void PicoPowerMS(void);\r
2ec9bec5 708void PicoResetMS(void);\r
3e49ffd0 709void PicoMemSetupMS(void);\r
b4db550e 710void PicoStateLoadedMS(void);\r
3e49ffd0 711void PicoFrameMS(void);\r
87b0845f 712void PicoFrameDrawOnlyMS(void);\r
f3a57b2d 713#else\r
714#define PicoPowerMS()\r
715#define PicoResetMS()\r
716#define PicoMemSetupMS()\r
717#define PicoStateLoadedMS()\r
718#define PicoFrameMS()\r
719#define PicoFrameDrawOnlyMS()\r
720#endif\r
3e49ffd0 721\r
be2c4208 722// 32x/32x.c\r
f3a57b2d 723#ifndef NO_32X\r
be2c4208 724extern struct Pico32x Pico32x;\r
725void Pico32xInit(void);\r
974fdb5b 726void PicoPower32x(void);\r
be2c4208 727void PicoReset32x(void);\r
974fdb5b 728void Pico32xStartup(void);\r
5e49c3a8 729void PicoUnload32x(void);\r
974fdb5b 730void PicoFrame32x(void);\r
ed4402a7 731void p32x_sync_sh2s(unsigned int m68k_target);\r
1f1ff763 732void p32x_update_irls(int nested_call);\r
83ff19ec 733void p32x_reset_sh2s(void);\r
be2c4208 734\r
a8fd6e37 735enum p32x_event {\r
736 P32X_EVENT_PWM,\r
737 P32X_EVENT_FILLEND,\r
738 P32X_EVENT_COUNT,\r
739};\r
740void p32x_event_schedule(enum p32x_event event, unsigned int now, int after);\r
741\r
be2c4208 742// 32x/memory.c\r
974fdb5b 743struct Pico32xMem *Pico32xMem;\r
be2c4208 744unsigned int PicoRead8_32x(unsigned int a);\r
745unsigned int PicoRead16_32x(unsigned int a);\r
746void PicoWrite8_32x(unsigned int a, unsigned int d);\r
747void PicoWrite16_32x(unsigned int a, unsigned int d);\r
748void PicoMemSetup32x(void);\r
974fdb5b 749void Pico32xSwapDRAM(int b);\r
b4db550e 750void Pico32xStateLoaded(void);\r
87accdf7 751void p32x_poll_event(int cpu_mask, int is_vdp);\r
974fdb5b 752\r
753// 32x/draw.c\r
754void FinalizeLine32xRGB555(int sh, int line);\r
5a681086 755void PicoDraw32xLayer(int offs, int lines, int mdbg);\r
7a961c19 756void PicoDraw32xLayerMdOnly(int offs, int lines);\r
f4750ee0 757extern int (*PicoScan32xBegin)(unsigned int num);\r
758extern int (*PicoScan32xEnd)(unsigned int num);\r
7a961c19 759enum {\r
760 PDM32X_OFF,\r
761 PDM32X_32X_ONLY,\r
762 PDM32X_BOTH,\r
763};\r
5a681086 764extern int Pico32xDrawMode;\r
be2c4208 765\r
db1d3564 766// 32x/pwm.c\r
767unsigned int p32x_pwm_read16(unsigned int a);\r
768void p32x_pwm_write16(unsigned int a, unsigned int d);\r
db1d3564 769void p32x_pwm_update(int *buf32, int length, int stereo);\r
a8fd6e37 770void p32x_timers_do(unsigned int cycles);\r
1d7a28a7 771void p32x_timers_recalc(void);\r
a8fd6e37 772void p32x_pwm_schedule(unsigned int now);\r
f3a57b2d 773#else\r
774#define Pico32xInit()\r
775#define PicoPower32x()\r
776#define PicoReset32x()\r
777#define PicoFrame32x()\r
778#define PicoUnload32x()\r
779#define Pico32xStateLoaded()\r
780#define PicoDraw32xSetFrameMode(...)\r
781#define FinalizeLine32xRGB555 NULL\r
782#define p32x_pwm_update(...)\r
783#define p32x_timers_recalc()\r
784#endif\r
db1d3564 785\r
45f2f245 786/* avoid dependency on newer glibc */\r
787static __inline int isspace_(int c)\r
788{\r
789 return (0x09 <= c && c <= 0x0d) || c == ' ';\r
790}\r
791\r
f4bb5d6b 792#ifndef ARRAY_SIZE\r
793#define ARRAY_SIZE(x) (sizeof(x) / sizeof(x[0]))\r
794#endif\r
795\r
b8cbd802 796// emulation event logging\r
797#ifndef EL_LOGMASK\r
798#define EL_LOGMASK 0\r
799#endif\r
800\r
017512f2 801#define EL_HVCNT 0x00000001 /* hv counter reads */\r
802#define EL_SR 0x00000002 /* SR reads */\r
803#define EL_INTS 0x00000004 /* ints and acks */\r
43e6eaad 804#define EL_YMTIMER 0x00000008 /* ym2612 timer stuff */\r
017512f2 805#define EL_INTSW 0x00000010 /* log irq switching on/off */\r
806#define EL_ASVDP 0x00000020 /* VDP accesses during active scan */\r
807#define EL_VDPDMA 0x00000040 /* VDP DMA transfers and their timing */\r
808#define EL_BUSREQ 0x00000080 /* z80 busreq r/w or reset w */\r
809#define EL_Z80BNK 0x00000100 /* z80 i/o through bank area */\r
810#define EL_SRAMIO 0x00000200 /* sram i/o */\r
811#define EL_EEPROM 0x00000400 /* eeprom debug */\r
812#define EL_UIO 0x00000800 /* unmapped i/o */\r
813#define EL_IO 0x00001000 /* all i/o */\r
814#define EL_CDPOLL 0x00002000 /* MCD: log poll detection */\r
815#define EL_SVP 0x00004000 /* SVP stuff */\r
fa22af4c 816#define EL_PICOHW 0x00008000 /* Pico stuff */\r
053fd9b4 817#define EL_IDLE 0x00010000 /* idle loop det. */\r
af37bca8 818#define EL_CDREGS 0x00020000 /* MCD: register access */\r
819#define EL_CDREG3 0x00040000 /* MCD: register 3 only */\r
be2c4208 820#define EL_32X 0x00080000\r
1b3f5844 821#define EL_PWM 0x00100000 /* 32X PWM stuff (LOTS of output) */\r
017512f2 822\r
823#define EL_STATUS 0x40000000 /* status messages */\r
824#define EL_ANOMALY 0x80000000 /* some unexpected conditions (during emulation) */\r
b8cbd802 825\r
826#if EL_LOGMASK\r
827#define elprintf(w,f,...) \\r
a8fd6e37 828do { \\r
b8cbd802 829 if ((w) & EL_LOGMASK) \\r
7d0143a2 830 lprintf("%05i:%03i: " f "\n",Pico.m.frame_count,Pico.m.scanline,##__VA_ARGS__); \\r
a8fd6e37 831} while (0)\r
dca310c4 832#elif defined(_MSC_VER)\r
833#define elprintf\r
b8cbd802 834#else\r
835#define elprintf(w,f,...)\r
836#endif\r
837\r
f6c49d38 838// profiling\r
839#ifdef PPROF\r
840#include <platform/linux/pprof.h>\r
841#else\r
842#define pprof_init()\r
843#define pprof_finish()\r
844#define pprof_start(x)\r
845#define pprof_end(...)\r
846#define pprof_end_sub(...)\r
847#endif\r
848\r
849// misc\r
dca310c4 850#ifdef _MSC_VER\r
851#define cdprintf\r
852#else\r
853#define cdprintf(x...)\r
854#endif\r
855\r
553c3eaa 856#ifdef __i386__\r
857#define REGPARM(x) __attribute__((regparm(x)))\r
c8d1e9b6 858#else\r
553c3eaa 859#define REGPARM(x)\r
c8d1e9b6 860#endif\r
861\r
5e89f0f5 862#ifdef __GNUC__\r
863#define NOINLINE __attribute__((noinline))\r
864#else\r
865#define NOINLINE\r
866#endif\r
867\r
f8af9634 868#ifdef __cplusplus\r
869} // End of extern "C"\r
870#endif\r
871\r
eff55556 872#endif // PICO_INTERNAL_INCLUDED\r
873\r
fast MegaDrive/MegaCD/32X emulator