notaz.gp2x.de / picodrive.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
32x: start reworking sheduling
[picodrive.git] / pico / pico_int.h
CommitLineData
cff531af 1/*\r
2 * PicoDrive - Internal Header File\r
3 * (c) Copyright Dave, 2004\r
4 * (C) notaz, 2006-2010\r
5 *\r
6 * This work is licensed under the terms of MAME license.\r
7 * See COPYING file in the top-level directory.\r
8 */\r
cc68a136 9\r
eff55556 10#ifndef PICO_INTERNAL_INCLUDED\r
11#define PICO_INTERNAL_INCLUDED\r
cc68a136 12\r
13#include <stdio.h>\r
14#include <stdlib.h>\r
15#include <string.h>\r
efcba75f 16#include "pico.h"\r
f53f286a 17#include "carthw/carthw.h"\r
cc68a136 18\r
89fa852d 19//\r
20#define USE_POLL_DETECT\r
21\r
eff55556 22#ifndef PICO_INTERNAL\r
23#define PICO_INTERNAL\r
24#endif\r
25#ifndef PICO_INTERNAL_ASM\r
26#define PICO_INTERNAL_ASM\r
27#endif\r
cc68a136 28\r
70357ce5 29// to select core, define EMU_C68K, EMU_M68K or EMU_F68K in your makefile or project\r
cc68a136 30\r
31#ifdef __cplusplus\r
32extern "C" {\r
33#endif\r
34\r
35\r
36// ----------------------- 68000 CPU -----------------------\r
37#ifdef EMU_C68K\r
d4d62665 38#include "../cpu/cyclone/Cyclone.h"\r
3aa1e148 39extern struct Cyclone PicoCpuCM68k, PicoCpuCS68k;\r
40#define SekCyclesLeftNoMCD PicoCpuCM68k.cycles // cycles left for this run\r
7336a99a 41#define SekCyclesLeft \\r
602133e1 42 (((PicoAHW&1) && (PicoOpt & POPT_EN_MCD_PSYNC)) ? (SekCycleAim-SekCycleCnt) : SekCyclesLeftNoMCD)\r
7a1f6e45 43#define SekCyclesLeftS68k \\r
602133e1 44 ((PicoOpt & POPT_EN_MCD_PSYNC) ? (SekCycleAimS68k-SekCycleCntS68k) : PicoCpuCS68k.cycles)\r
ef090115 45#define SekEndTimeslice(after) PicoCpuCM68k.cycles=after\r
07ceafdb 46#define SekEndTimesliceS68k(after) PicoCpuCS68k.cycles=after\r
3aa1e148 47#define SekPc (PicoCpuCM68k.pc-PicoCpuCM68k.membase)\r
48#define SekPcS68k (PicoCpuCS68k.pc-PicoCpuCS68k.membase)\r
d4d62665 49#define SekDar(x) (x < 8 ? PicoCpuCM68k.d[x] : PicoCpuCM68k.a[x - 8])\r
5fadfb1c 50#define SekSr CycloneGetSr(&PicoCpuCM68k)\r
3aa1e148 51#define SekSetStop(x) { PicoCpuCM68k.state_flags&=~1; if (x) { PicoCpuCM68k.state_flags|=1; PicoCpuCM68k.cycles=0; } }\r
52#define SekSetStopS68k(x) { PicoCpuCS68k.state_flags&=~1; if (x) { PicoCpuCS68k.state_flags|=1; PicoCpuCS68k.cycles=0; } }\r
ed4402a7 53#define SekIsStoppedM68k() (PicoCpuCM68k.state_flags&1)\r
ca61ee42 54#define SekIsStoppedS68k() (PicoCpuCS68k.state_flags&1)\r
03e4f2a3 55#define SekShouldInterrupt (PicoCpuCM68k.irq > (PicoCpuCM68k.srh&7))\r
b542be46 56\r
57#define SekInterrupt(i) PicoCpuCM68k.irq=i\r
5fadfb1c 58#define SekIrqLevel PicoCpuCM68k.irq\r
b542be46 59\r
03e4f2a3 60#ifdef EMU_M68K\r
61#define EMU_CORE_DEBUG\r
62#endif\r
cc68a136 63#endif\r
64\r
70357ce5 65#ifdef EMU_F68K\r
66#include "../cpu/fame/fame.h"\r
b542be46 67extern M68K_CONTEXT PicoCpuFM68k, PicoCpuFS68k;\r
3aa1e148 68#define SekCyclesLeftNoMCD PicoCpuFM68k.io_cycle_counter\r
70357ce5 69#define SekCyclesLeft \\r
602133e1 70 (((PicoAHW&1) && (PicoOpt & POPT_EN_MCD_PSYNC)) ? (SekCycleAim-SekCycleCnt) : SekCyclesLeftNoMCD)\r
70357ce5 71#define SekCyclesLeftS68k \\r
602133e1 72 ((PicoOpt & POPT_EN_MCD_PSYNC) ? (SekCycleAimS68k-SekCycleCntS68k) : PicoCpuFS68k.io_cycle_counter)\r
ef090115 73#define SekEndTimeslice(after) PicoCpuFM68k.io_cycle_counter=after\r
07ceafdb 74#define SekEndTimesliceS68k(after) PicoCpuFS68k.io_cycle_counter=after\r
03e4f2a3 75#define SekPc fm68k_get_pc(&PicoCpuFM68k)\r
76#define SekPcS68k fm68k_get_pc(&PicoCpuFS68k)\r
d4d62665 77#define SekDar(x) (x < 8 ? PicoCpuFM68k.dreg[x].D : PicoCpuFM68k.areg[x - 8].D)\r
5fadfb1c 78#define SekSr PicoCpuFM68k.sr\r
70357ce5 79#define SekSetStop(x) { \\r
03e4f2a3 80 PicoCpuFM68k.execinfo &= ~FM68K_HALTED; \\r
81 if (x) { PicoCpuFM68k.execinfo |= FM68K_HALTED; PicoCpuFM68k.io_cycle_counter = 0; } \\r
70357ce5 82}\r
83#define SekSetStopS68k(x) { \\r
03e4f2a3 84 PicoCpuFS68k.execinfo &= ~FM68K_HALTED; \\r
85 if (x) { PicoCpuFS68k.execinfo |= FM68K_HALTED; PicoCpuFS68k.io_cycle_counter = 0; } \\r
70357ce5 86}\r
ed4402a7 87#define SekIsStoppedM68k() (PicoCpuFM68k.execinfo&FM68K_HALTED)\r
ca61ee42 88#define SekIsStoppedS68k() (PicoCpuFS68k.execinfo&FM68K_HALTED)\r
03e4f2a3 89#define SekShouldInterrupt fm68k_would_interrupt()\r
b542be46 90\r
91#define SekInterrupt(irq) PicoCpuFM68k.interrupts[0]=irq\r
5fadfb1c 92#define SekIrqLevel PicoCpuFM68k.interrupts[0]\r
b542be46 93\r
03e4f2a3 94#ifdef EMU_M68K\r
95#define EMU_CORE_DEBUG\r
96#endif\r
cc68a136 97#endif\r
98\r
99#ifdef EMU_M68K\r
100#include "../cpu/musashi/m68kcpu.h"\r
3aa1e148 101extern m68ki_cpu_core PicoCpuMM68k, PicoCpuMS68k;\r
cc68a136 102#ifndef SekCyclesLeft\r
3aa1e148 103#define SekCyclesLeftNoMCD PicoCpuMM68k.cyc_remaining_cycles\r
7336a99a 104#define SekCyclesLeft \\r
602133e1 105 (((PicoAHW&1) && (PicoOpt & POPT_EN_MCD_PSYNC)) ? (SekCycleAim-SekCycleCnt) : SekCyclesLeftNoMCD)\r
7a1f6e45 106#define SekCyclesLeftS68k \\r
602133e1 107 ((PicoOpt & POPT_EN_MCD_PSYNC) ? (SekCycleAimS68k-SekCycleCntS68k) : PicoCpuMS68k.cyc_remaining_cycles)\r
ef090115 108#define SekEndTimeslice(after) SET_CYCLES(after)\r
07ceafdb 109#define SekEndTimesliceS68k(after) PicoCpuMS68k.cyc_remaining_cycles=after\r
3aa1e148 110#define SekPc m68k_get_reg(&PicoCpuMM68k, M68K_REG_PC)\r
111#define SekPcS68k m68k_get_reg(&PicoCpuMS68k, M68K_REG_PC)\r
5fadfb1c 112#define SekDar(x) PicoCpuMM68k.dar[x]\r
113#define SekSr m68k_get_reg(&PicoCpuMM68k, M68K_REG_SR)\r
7a1f6e45 114#define SekSetStop(x) { \\r
3aa1e148 115 if(x) { SET_CYCLES(0); PicoCpuMM68k.stopped=STOP_LEVEL_STOP; } \\r
116 else PicoCpuMM68k.stopped=0; \\r
7a1f6e45 117}\r
118#define SekSetStopS68k(x) { \\r
3aa1e148 119 if(x) { SET_CYCLES(0); PicoCpuMS68k.stopped=STOP_LEVEL_STOP; } \\r
120 else PicoCpuMS68k.stopped=0; \\r
7a1f6e45 121}\r
ed4402a7 122#define SekIsStoppedM68k() (PicoCpuMM68k.stopped==STOP_LEVEL_STOP)\r
ca61ee42 123#define SekIsStoppedS68k() (PicoCpuMS68k.stopped==STOP_LEVEL_STOP)\r
03e4f2a3 124#define SekShouldInterrupt (CPU_INT_LEVEL > FLAG_INT_MASK)\r
b542be46 125\r
71de3cd9 126#define SekInterrupt(irq) { \\r
b542be46 127 void *oldcontext = m68ki_cpu_p; \\r
128 m68k_set_context(&PicoCpuMM68k); \\r
129 m68k_set_irq(irq); \\r
130 m68k_set_context(oldcontext); \\r
131}\r
5fadfb1c 132#define SekIrqLevel (PicoCpuMM68k.int_level >> 8)\r
b542be46 133\r
cc68a136 134#endif\r
ef090115 135#endif // EMU_M68K\r
cc68a136 136\r
137extern int SekCycleCnt; // cycles done in this frame\r
138extern int SekCycleAim; // cycle aim\r
139extern unsigned int SekCycleCntT; // total cycle counter, updated once per frame\r
140\r
b8cbd802 141#define SekCyclesReset() { \\r
142 SekCycleCntT+=SekCycleAim; \\r
143 SekCycleCnt-=SekCycleAim; \\r
144 SekCycleAim=0; \\r
145}\r
cc68a136 146#define SekCyclesBurn(c) SekCycleCnt+=c\r
4b9c5888 147#define SekCyclesDone() (SekCycleAim-SekCyclesLeft) // number of cycles done in this frame (can be checked anywhere)\r
cc68a136 148#define SekCyclesDoneT() (SekCycleCntT+SekCyclesDone()) // total nuber of cycles done for this rom\r
149\r
150#define SekEndRun(after) { \\r
ef090115 151 SekCycleCnt -= SekCyclesLeft - (after); \\r
152 if (SekCycleCnt < 0) SekCycleCnt = 0; \\r
153 SekEndTimeslice(after); \\r
cc68a136 154}\r
155\r
07ceafdb 156#define SekEndRunS68k(after) { \\r
157 SekCycleCntS68k -= SekCyclesLeftS68k - (after); \\r
158 if (SekCycleCntS68k < 0) SekCycleCntS68k = 0; \\r
159 SekEndTimesliceS68k(after); \\r
160}\r
161\r
cc68a136 162extern int SekCycleCntS68k;\r
163extern int SekCycleAimS68k;\r
164\r
bf5fbbb4 165#define SekCyclesResetS68k() { \\r
166 SekCycleCntS68k-=SekCycleAimS68k; \\r
167 SekCycleAimS68k=0; \\r
168}\r
7a1f6e45 169#define SekCyclesDoneS68k() (SekCycleAimS68k-SekCyclesLeftS68k)\r
cc68a136 170\r
03e4f2a3 171#ifdef EMU_CORE_DEBUG\r
99464b62 172extern int dbg_irq_level;\r
ef090115 173#undef SekEndTimeslice\r
2d0b15bb 174#undef SekCyclesBurn\r
175#undef SekEndRun\r
99464b62 176#undef SekInterrupt\r
ef090115 177#define SekEndTimeslice(c)\r
2270612a 178#define SekCyclesBurn(c) c\r
2d0b15bb 179#define SekEndRun(c)\r
99464b62 180#define SekInterrupt(irq) dbg_irq_level=irq\r
2d0b15bb 181#endif\r
cc68a136 182\r
b542be46 183// ----------------------- Z80 CPU -----------------------\r
184\r
b4db550e 185#if defined(_USE_DRZ80)\r
dca310c4 186#include "../cpu/DrZ80/drz80.h"\r
b542be46 187\r
188extern struct DrZ80 drZ80;\r
189\r
190#define z80_run(cycles) ((cycles) - DrZ80Run(&drZ80, cycles))\r
191#define z80_run_nr(cycles) DrZ80Run(&drZ80, cycles)\r
4936aac1 192#define z80_int() drZ80.Z80_IRQ = 1\r
4b9c5888 193\r
194#define z80_cyclesLeft drZ80.cycles\r
19954be1 195#define z80_pc() (drZ80.Z80PC - drZ80.Z80PC_BASE)\r
b542be46 196\r
197#elif defined(_USE_CZ80)\r
dca310c4 198#include "../cpu/cz80/cz80.h"\r
b542be46 199\r
200#define z80_run(cycles) Cz80_Exec(&CZ80, cycles)\r
201#define z80_run_nr(cycles) Cz80_Exec(&CZ80, cycles)\r
202#define z80_int() Cz80_Set_IRQ(&CZ80, 0, HOLD_LINE)\r
4b9c5888 203\r
204#define z80_cyclesLeft (CZ80.ICount - CZ80.ExtraCycles)\r
19954be1 205#define z80_pc() Cz80_Get_Reg(&CZ80, CZ80_PC)\r
b542be46 206\r
207#else\r
208\r
209#define z80_run(cycles) (cycles)\r
210#define z80_run_nr(cycles)\r
211#define z80_int()\r
b542be46 212\r
213#endif\r
214\r
b4db550e 215#define Z80_STATE_SIZE 0x60\r
216\r
4b9c5888 217extern int z80stopCycle; /* in 68k cycles */\r
218extern int z80_cycle_cnt; /* 'done' z80 cycles before z80_run() */\r
219extern int z80_cycle_aim;\r
220extern int z80_scanline;\r
221extern int z80_scanline_cycles; /* cycles done until z80_scanline */\r
222\r
223#define z80_resetCycles() \\r
224 z80_cycle_cnt = z80_cycle_aim = z80_scanline = z80_scanline_cycles = 0;\r
225\r
226#define z80_cyclesDone() \\r
227 (z80_cycle_aim - z80_cyclesLeft)\r
228\r
229#define cycles_68k_to_z80(x) ((x)*957 >> 11)\r
230\r
acd35d4c 231// ----------------------- SH2 CPU -----------------------\r
232\r
41397701 233#include "cpu/sh2/sh2.h"\r
acd35d4c 234\r
1d7a28a7 235extern SH2 sh2s[2];\r
236#define msh2 sh2s[0]\r
237#define ssh2 sh2s[1]\r
238\r
679af8a3 239#ifndef DRC_SH2\r
240# define ash2_end_run(after) if (sh2->icount > (after)) sh2->icount = after\r
ed4402a7 241# define ash2_cycles_done() (sh2->cycles_timeslice - sh2->icount)\r
679af8a3 242#else\r
243# define ash2_end_run(after) { \\r
244 if ((sh2->sr >> 12) > (after)) \\r
245 { sh2->sr &= 0xfff; sh2->sr |= (after) << 12; } \\r
246}\r
ed4402a7 247# define ash2_cycles_done() (sh2->cycles_timeslice - (sh2->sr >> 12))\r
679af8a3 248#endif\r
266c6afa 249\r
679af8a3 250//#define sh2_pc(c) (c) ? ssh2.ppc : msh2.ppc\r
251#define sh2_pc(c) (c) ? ssh2.pc : msh2.pc\r
4ea707e1 252#define sh2_reg(c, x) (c) ? ssh2.r[x] : msh2.r[x]\r
253#define sh2_gbr(c) (c) ? ssh2.gbr : msh2.gbr\r
254#define sh2_vbr(c) (c) ? ssh2.vbr : msh2.vbr\r
6add7875 255#define sh2_sr(c) (((c) ? ssh2.sr : msh2.sr) & 0xfff)\r
acd35d4c 256\r
83ff19ec 257#define sh2_set_gbr(c, v) \\r
258 { if (c) ssh2.gbr = v; else msh2.gbr = v; }\r
259#define sh2_set_vbr(c, v) \\r
260 { if (c) ssh2.vbr = v; else msh2.vbr = v; }\r
261\r
cc68a136 262// ---------------------------------------------------------\r
263\r
264// main oscillator clock which controls timing\r
265#define OSC_NTSC 53693100\r
b8cbd802 266#define OSC_PAL 53203424\r
cc68a136 267\r
268struct PicoVideo\r
269{\r
270 unsigned char reg[0x20];\r
b8cbd802 271 unsigned int command; // 32-bit Command\r
272 unsigned char pending; // 1 if waiting for second half of 32-bit command\r
273 unsigned char type; // Command type (v/c/vsram read/write)\r
274 unsigned short addr; // Read/Write address\r
275 int status; // Status bits\r
cc68a136 276 unsigned char pending_ints; // pending interrupts: ??VH????\r
b8cbd802 277 signed char lwrite_cnt; // VDP write count during active display line\r
9761a7d0 278 unsigned short v_counter; // V-counter\r
279 unsigned char pad[0x10];\r
cc68a136 280};\r
281\r
282struct PicoMisc\r
283{\r
284 unsigned char rotate;\r
285 unsigned char z80Run;\r
e5503e2f 286 unsigned char padTHPhase[2]; // 02 phase of gamepad TH switches\r
2aa27095 287 unsigned short scanline; // 04 0 to 261||311\r
e5503e2f 288 char dirtyPal; // 06 Is the palette dirty (1 - change @ this frame, 2 - some time before)\r
289 unsigned char hardware; // 07 Hardware value for country\r
290 unsigned char pal; // 08 1=PAL 0=NTSC\r
45f2f245 291 unsigned char sram_reg; // 09 SRAM reg. See SRR_* below\r
e5503e2f 292 unsigned short z80_bank68k; // 0a\r
be2c4208 293 unsigned short pad0;\r
294 unsigned char pad1;\r
0ace9b9a 295 unsigned char z80_reset; // 0f z80 reset held\r
e5503e2f 296 unsigned char padDelay[2]; // 10 gamepad phase time outs, so we count a delay\r
1dceadae 297 unsigned short eeprom_addr; // EEPROM address register\r
45f2f245 298 unsigned char eeprom_cycle; // EEPROM cycle number\r
1dceadae 299 unsigned char eeprom_slave; // EEPROM slave word for X24C02 and better SRAMs\r
45f2f245 300 unsigned char eeprom_status;\r
be2c4208 301 unsigned char pad2;\r
053fd9b4 302 unsigned short dma_xfers; // 18\r
45f2f245 303 unsigned char eeprom_wb[2]; // EEPROM latch/write buffer\r
053fd9b4 304 unsigned int frame_count; // 1c for movies and idle det\r
cc68a136 305};\r
306\r
b4db550e 307struct PicoMS\r
308{\r
309 unsigned char carthw[0x10];\r
310 unsigned char io_ctl;\r
311 unsigned char pad[0x4f];\r
312};\r
313\r
cc68a136 314// some assembly stuff depend on these, do not touch!\r
315struct Pico\r
316{\r
317 unsigned char ram[0x10000]; // 0x00000 scratch ram\r
200772b7 318 union { // vram is byteswapped for easier reads when drawing\r
2ec9bec5 319 unsigned short vram[0x8000]; // 0x10000\r
320 unsigned char vramb[0x4000]; // VRAM in SMS mode\r
321 };\r
cc68a136 322 unsigned char zram[0x2000]; // 0x20000 Z80 ram\r
b4db550e 323 unsigned char ioports[0x10]; // XXX: fix asm and mv\r
324 unsigned char pad[0xf0]; // unused\r
cc68a136 325 unsigned short cram[0x40]; // 0x22100\r
326 unsigned short vsram[0x40]; // 0x22180\r
327\r
328 unsigned char *rom; // 0x22200\r
329 unsigned int romsize; // 0x22204\r
330\r
331 struct PicoMisc m;\r
332 struct PicoVideo video;\r
b4db550e 333 struct PicoMS ms;\r
cc68a136 334};\r
335\r
336// sram\r
45f2f245 337#define SRR_MAPPED (1 << 0)\r
338#define SRR_READONLY (1 << 1)\r
339\r
340#define SRF_ENABLED (1 << 0)\r
341#define SRF_EEPROM (1 << 1)\r
af37bca8 342\r
cc68a136 343struct PicoSRAM\r
344{\r
4ff2d527 345 unsigned char *data; // actual data\r
346 unsigned int start; // start address in 68k address space\r
cc68a136 347 unsigned int end;\r
45f2f245 348 unsigned char flags; // 0c: SRF_*\r
1dceadae 349 unsigned char unused2;\r
cc68a136 350 unsigned char changed;\r
45f2f245 351 unsigned char eeprom_type; // eeprom type: 0: 7bit (24C01), 2: 2 addr words (X24C02+), 3: 3 addr words\r
352 unsigned char unused3;\r
1dceadae 353 unsigned char eeprom_bit_cl; // bit number for cl\r
354 unsigned char eeprom_bit_in; // bit number for in\r
355 unsigned char eeprom_bit_out; // bit number for out\r
45f2f245 356 unsigned int size;\r
cc68a136 357};\r
358\r
359// MCD\r
360#include "cd/cd_sys.h"\r
361#include "cd/LC89510.h"\r
d1df8786 362#include "cd/gfx_cd.h"\r
cc68a136 363\r
4f265db7 364struct mcd_pcm\r
365{\r
366 unsigned char control; // reg7\r
367 unsigned char enabled; // reg8\r
368 unsigned char cur_ch;\r
369 unsigned char bank;\r
370 int pad1;\r
371\r
4ff2d527 372 struct pcm_chan // 08, size 0x10\r
4f265db7 373 {\r
374 unsigned char regs[8];\r
4ff2d527 375 unsigned int addr; // .08: played sample address\r
4f265db7 376 int pad;\r
377 } ch[8];\r
378};\r
379\r
c459aefd 380struct mcd_misc\r
381{\r
382 unsigned short hint_vector;\r
383 unsigned char busreq;\r
51a902ae 384 unsigned char s68k_pend_ints;\r
ef090115 385 unsigned int state_flags; // 04: emu state: reset_pending\r
51a902ae 386 unsigned int counter75hz;\r
c9e1affc 387 unsigned int pad0;\r
4ff2d527 388 int timer_int3; // 10\r
4f265db7 389 unsigned int timer_stopwatch;\r
6cadc2da 390 unsigned char bcram_reg; // 18: battery-backed RAM cart register\r
391 unsigned char pad2;\r
392 unsigned short pad3;\r
393 int pad[9];\r
c459aefd 394};\r
395\r
cc68a136 396typedef struct\r
397{\r
4ff2d527 398 unsigned char bios[0x20000]; // 000000: 128K\r
399 union { // 020000: 512K\r
fa1e5e29 400 unsigned char prg_ram[0x80000];\r
cc68a136 401 unsigned char prg_ram_b[4][0x20000];\r
402 };\r
4ff2d527 403 union { // 0a0000: 256K\r
fa1e5e29 404 struct {\r
405 unsigned char word_ram2M[0x40000];\r
dca310c4 406 unsigned char unused0[0x20000];\r
fa1e5e29 407 };\r
408 struct {\r
dca310c4 409 unsigned char unused1[0x20000];\r
fa1e5e29 410 unsigned char word_ram1M[2][0x20000];\r
411 };\r
412 };\r
4ff2d527 413 union { // 100000: 64K\r
fa1e5e29 414 unsigned char pcm_ram[0x10000];\r
4f265db7 415 unsigned char pcm_ram_b[0x10][0x1000];\r
416 };\r
4ff2d527 417 unsigned char s68k_regs[0x200]; // 110000: GA, not CPU regs\r
418 unsigned char bram[0x2000]; // 110200: 8K\r
419 struct mcd_misc m; // 112200: misc\r
420 struct mcd_pcm pcm; // 112240:\r
75736070 421 _scd_toc TOC; // not to be saved\r
cc68a136 422 CDD cdd;\r
423 CDC cdc;\r
424 _scd scd;\r
d1df8786 425 Rot_Comp rot_comp;\r
cc68a136 426} mcd_state;\r
427\r
be2c4208 428// XXX: this will need to be reworked for cart+cd support.\r
cc68a136 429#define Pico_mcd ((mcd_state *)Pico.rom)\r
430\r
be2c4208 431// 32X\r
acd35d4c 432#define P32XS_FM (1<<15)\r
83ff19ec 433#define P32XS_REN (1<< 7)\r
434#define P32XS_nRES (1<< 1)\r
435#define P32XS_ADEN (1<< 0)\r
acd35d4c 436#define P32XS2_ADEN (1<< 9)\r
5e128c6d 437#define P32XS_FULL (1<< 7) // DREQ FIFO full\r
4ea707e1 438#define P32XS_68S (1<< 2)\r
97d3f47f 439#define P32XS_DMA (1<< 1)\r
4ea707e1 440#define P32XS_RV (1<< 0)\r
acd35d4c 441\r
5e128c6d 442#define P32XV_nPAL (1<<15) // VDP\r
acd35d4c 443#define P32XV_PRI (1<< 7)\r
4ea707e1 444#define P32XV_Mx (3<< 0) // display mode mask\r
974fdb5b 445\r
e51e5983 446#define P32XV_SFT (1<< 0)\r
447\r
acd35d4c 448#define P32XV_VBLK (1<<15)\r
449#define P32XV_HBLK (1<<14)\r
450#define P32XV_PEN (1<<13)\r
451#define P32XV_nFEN (1<< 1)\r
452#define P32XV_FS (1<< 0)\r
974fdb5b 453\r
db1d3564 454#define P32XP_FULL (1<<15) // PWM\r
455#define P32XP_EMPTY (1<<14)\r
456\r
4ea707e1 457#define P32XF_68KPOLL (1 << 0)\r
458#define P32XF_MSH2POLL (1 << 1)\r
459#define P32XF_SSH2POLL (1 << 2)\r
460#define P32XF_68KVPOLL (1 << 3)\r
461#define P32XF_MSH2VPOLL (1 << 4)\r
462#define P32XF_SSH2VPOLL (1 << 5)\r
463\r
464#define P32XI_VRES (1 << 14/2) // IRL/2\r
465#define P32XI_VINT (1 << 12/2)\r
466#define P32XI_HINT (1 << 10/2)\r
467#define P32XI_CMD (1 << 8/2)\r
468#define P32XI_PWM (1 << 6/2)\r
469\r
1d7a28a7 470// peripheral reg access\r
471#define PREG8(regs,offs) ((unsigned char *)regs)[offs ^ 3]\r
472\r
4ea707e1 473// real one is 4*2, but we use more because we don't lockstep\r
474#define DMAC_FIFO_LEN (4*4)\r
db1d3564 475#define PWM_BUFF_LEN 1024 // in one channel samples\r
266c6afa 476\r
f4bb5d6b 477#define SH2_DRCBLK_RAM_SHIFT 1\r
478#define SH2_DRCBLK_DA_SHIFT 1\r
479\r
e05b81fc 480#define SH2_WRITE_SHIFT 25\r
481\r
be2c4208 482struct Pico32x\r
483{\r
484 unsigned short regs[0x20];\r
5a681086 485 unsigned short vdp_regs[0x10]; // 0x40\r
486 unsigned short sh2_regs[3]; // 0x60\r
be2c4208 487 unsigned char pending_fb;\r
974fdb5b 488 unsigned char dirty_pal;\r
266c6afa 489 unsigned int emu_flags;\r
4ea707e1 490 unsigned char sh2irq_mask[2];\r
491 unsigned char sh2irqi[2]; // individual\r
492 unsigned int sh2irqs; // common irqs\r
493 unsigned short dmac_fifo[DMAC_FIFO_LEN];\r
494 unsigned int dmac_ptr;\r
db1d3564 495 unsigned int pwm_irq_sample_cnt;\r
b4db550e 496 unsigned int reserved[9];\r
974fdb5b 497};\r
498\r
499struct Pico32xMem\r
500{\r
501 unsigned char sdram[0x40000];\r
f4bb5d6b 502#ifdef DRC_SH2\r
503 unsigned short drcblk_ram[1 << (18 - SH2_DRCBLK_RAM_SHIFT)];\r
504#endif\r
b78efee2 505 unsigned short dram[2][0x20000/2]; // AKA fb\r
b4db550e 506 union {\r
507 unsigned char m68k_rom[0x100];\r
508 unsigned char m68k_rom_bank[0x10000]; // M68K_BANK_SIZE\r
509 };\r
b78efee2 510 unsigned char data_array[2][0x1000]; // cache in SH2s (can be used as RAM)\r
f4bb5d6b 511#ifdef DRC_SH2\r
512 unsigned short drcblk_da[2][1 << (12 - SH2_DRCBLK_DA_SHIFT)];\r
513#endif\r
acd35d4c 514 unsigned char sh2_rom_m[0x800];\r
515 unsigned char sh2_rom_s[0x400];\r
974fdb5b 516 unsigned short pal[0x100];\r
5e128c6d 517 unsigned short pal_native[0x100]; // converted to native (for renderer)\r
4ea707e1 518 unsigned int sh2_peri_regs[2][0x200/4]; // periphereal regs of SH2s\r
db1d3564 519 signed short pwm[2*PWM_BUFF_LEN]; // PWM buffer for current frame\r
be2c4208 520};\r
d49b10c2 521\r
c8d1e9b6 522// area.c\r
fad24893 523extern void (*PicoLoadStateHook)(void);\r
51a902ae 524\r
945c2fdc 525typedef struct {\r
526 int chunk;\r
527 int size;\r
528 void *ptr;\r
529} carthw_state_chunk;\r
530extern carthw_state_chunk *carthw_chunks;\r
531#define CHUNK_CARTHW 64\r
532\r
c8d1e9b6 533// cart.c\r
b4db550e 534extern int PicoCartResize(int newsize);\r
535extern void Byteswap(void *dst, const void *src, int len);\r
45f2f245 536extern void (*PicoCartMemSetup)(void);\r
e807ac75 537extern void (*PicoCartUnloadHook)(void);\r
1dceadae 538\r
c8d1e9b6 539// debug.c\r
b5e5172d 540int CM_compareRun(int cyc, int is_sub);\r
03e4f2a3 541\r
c8d1e9b6 542// draw.c\r
eff55556 543PICO_INTERNAL void PicoFrameStart(void);\r
b6d7ac70 544void PicoDrawSync(int to, int blank_last_line);\r
200772b7 545void BackFill(int reg7, int sh);\r
5a681086 546void FinalizeLine555(int sh, int line);\r
f4750ee0 547extern int (*PicoScanBegin)(unsigned int num);\r
548extern int (*PicoScanEnd)(unsigned int num);\r
b6d7ac70 549extern int DrawScanline;\r
f579f7b8 550#define MAX_LINE_SPRITES 29\r
551extern unsigned char HighLnSpr[240][3 + MAX_LINE_SPRITES];\r
5a681086 552extern void *DrawLineDestBase;\r
553extern int DrawLineDestIncrement;\r
cc68a136 554\r
c8d1e9b6 555// draw2.c\r
eff55556 556PICO_INTERNAL void PicoFrameFull();\r
cc68a136 557\r
200772b7 558// mode4.c\r
559void PicoFrameStartMode4(void);\r
560void PicoLineMode4(int line);\r
561void PicoDoHighPal555M4(void);\r
5a681086 562void PicoDrawSetOutputMode4(pdso_t which);\r
200772b7 563\r
c8d1e9b6 564// memory.c\r
eff55556 565PICO_INTERNAL void PicoMemSetup(void);\r
af37bca8 566unsigned int PicoRead8_io(unsigned int a);\r
567unsigned int PicoRead16_io(unsigned int a);\r
568void PicoWrite8_io(unsigned int a, unsigned int d);\r
569void PicoWrite16_io(unsigned int a, unsigned int d);\r
570\r
571// pico/memory.c\r
572PICO_INTERNAL void PicoMemSetupPico(void);\r
cc68a136 573\r
c8d1e9b6 574// cd/memory.c\r
eff55556 575PICO_INTERNAL void PicoMemSetupCD(void);\r
0ace9b9a 576void PicoMemStateLoaded(void);\r
cc68a136 577\r
c8d1e9b6 578// pico.c\r
cc68a136 579extern struct Pico Pico;\r
580extern struct PicoSRAM SRam;\r
5f9a0d16 581extern int PicoPadInt[2];\r
cc68a136 582extern int emustatus;\r
5e128c6d 583extern int scanlines_total;\r
f8ef8ff7 584extern void (*PicoResetHook)(void);\r
b0677887 585extern void (*PicoLineHook)(void);\r
1e6b5e39 586PICO_INTERNAL int CheckDMA(void);\r
587PICO_INTERNAL void PicoDetectRegion(void);\r
4b9c5888 588PICO_INTERNAL void PicoSyncZ80(int m68k_cycles_done);\r
cc68a136 589\r
c8d1e9b6 590// cd/pico.c\r
2aa27095 591PICO_INTERNAL void PicoInitMCD(void);\r
e5f426aa 592PICO_INTERNAL void PicoExitMCD(void);\r
1cb1584b 593PICO_INTERNAL void PicoPowerMCD(void);\r
2aa27095 594PICO_INTERNAL int PicoResetMCD(void);\r
595PICO_INTERNAL void PicoFrameMCD(void);\r
cc68a136 596\r
c8d1e9b6 597// pico/pico.c\r
2aa27095 598PICO_INTERNAL void PicoInitPico(void);\r
ed367a3f 599PICO_INTERNAL void PicoReratePico(void);\r
9037e45d 600\r
c8d1e9b6 601// pico/xpcm.c\r
ef4eb506 602PICO_INTERNAL void PicoPicoPCMUpdate(short *buffer, int length, int stereo);\r
603PICO_INTERNAL void PicoPicoPCMReset(void);\r
213c16ad 604PICO_INTERNAL void PicoPicoPCMRerate(int xpcm_rate);\r
ef4eb506 605\r
c8d1e9b6 606// sek.c\r
2aa27095 607PICO_INTERNAL void SekInit(void);\r
608PICO_INTERNAL int SekReset(void);\r
3aa1e148 609PICO_INTERNAL void SekState(int *data);\r
eff55556 610PICO_INTERNAL void SekSetRealTAS(int use_real);\r
b4db550e 611PICO_INTERNAL void SekPackCpu(unsigned char *cpu, int is_sub);\r
612PICO_INTERNAL void SekUnpackCpu(const unsigned char *cpu, int is_sub);\r
5f9a0d16 613void SekStepM68k(void);\r
053fd9b4 614void SekInitIdleDet(void);\r
615void SekFinishIdleDet(void);\r
cc68a136 616\r
c8d1e9b6 617// cd/sek.c\r
2aa27095 618PICO_INTERNAL void SekInitS68k(void);\r
619PICO_INTERNAL int SekResetS68k(void);\r
620PICO_INTERNAL int SekInterruptS68k(int irq);\r
cc68a136 621\r
7a93adeb 622// sound/sound.c\r
c9e1affc 623PICO_INTERNAL void cdda_start_play();\r
624extern short cdda_out_buffer[2*1152];\r
7a93adeb 625extern int PsndLen_exc_cnt;\r
626extern int PsndLen_exc_add;\r
48dc74f2 627extern int timer_a_next_oflow, timer_a_step; // in z80 cycles\r
628extern int timer_b_next_oflow, timer_b_step;\r
43e6eaad 629\r
630void ym2612_sync_timers(int z80_cycles, int mode_old, int mode_new);\r
d2721b08 631void ym2612_pack_state(void);\r
453d2a6e 632void ym2612_unpack_state(void);\r
4b9c5888 633\r
e53704e6 634#define TIMER_NO_OFLOW 0x70000000\r
45a1ef71 635// tA = 72 * (1024 - NA) / M\r
636#define TIMER_A_TICK_ZCYCLES 17203\r
637// tB = 1152 * (256 - NA) / M\r
638#define TIMER_B_TICK_ZCYCLES 262800 // 275251 broken, see Dai Makaimura\r
e53704e6 639\r
4b9c5888 640#define timers_cycle() \\r
e53704e6 641 if (timer_a_next_oflow > 0 && timer_a_next_oflow < TIMER_NO_OFLOW) \\r
43e6eaad 642 timer_a_next_oflow -= Pico.m.pal ? 70938*256 : 59659*256; \\r
e53704e6 643 if (timer_b_next_oflow > 0 && timer_b_next_oflow < TIMER_NO_OFLOW) \\r
43e6eaad 644 timer_b_next_oflow -= Pico.m.pal ? 70938*256 : 59659*256; \\r
645 ym2612_sync_timers(0, ym2612.OPN.ST.mode, ym2612.OPN.ST.mode);\r
4b9c5888 646\r
647#define timers_reset() \\r
e53704e6 648 timer_a_next_oflow = timer_b_next_oflow = TIMER_NO_OFLOW; \\r
48dc74f2 649 timer_a_step = TIMER_A_TICK_ZCYCLES * 1024; \\r
650 timer_b_step = TIMER_B_TICK_ZCYCLES * 256;\r
43e6eaad 651\r
7a93adeb 652\r
c8d1e9b6 653// videoport.c\r
eff55556 654PICO_INTERNAL_ASM void PicoVideoWrite(unsigned int a,unsigned short d);\r
655PICO_INTERNAL_ASM unsigned int PicoVideoRead(unsigned int a);\r
9761a7d0 656PICO_INTERNAL_ASM unsigned int PicoVideoRead8(unsigned int a);\r
5de27868 657extern int (*PicoDmaHook)(unsigned int source, int len, unsigned short **srcp, unsigned short **limitp);\r
cc68a136 658\r
c8d1e9b6 659// misc.c\r
eff55556 660PICO_INTERNAL_ASM void memcpy16(unsigned short *dest, unsigned short *src, int count);\r
661PICO_INTERNAL_ASM void memcpy16bswap(unsigned short *dest, void *src, int count);\r
662PICO_INTERNAL_ASM void memcpy32(int *dest, int *src, int count); // 32bit word count\r
663PICO_INTERNAL_ASM void memset32(int *dest, int c, int count);\r
cc68a136 664\r
45f2f245 665// eeprom.c\r
666void EEPROM_write8(unsigned int a, unsigned int d);\r
667void EEPROM_write16(unsigned int d);\r
668unsigned int EEPROM_read(void);\r
669\r
c8d1e9b6 670// z80 functionality wrappers\r
671PICO_INTERNAL void z80_init(void);\r
b4db550e 672PICO_INTERNAL void z80_pack(void *data);\r
673PICO_INTERNAL int z80_unpack(const void *data);\r
c8d1e9b6 674PICO_INTERNAL void z80_reset(void);\r
675PICO_INTERNAL void z80_exit(void);\r
c8d1e9b6 676\r
677// cd/misc.c\r
eff55556 678PICO_INTERNAL_ASM void wram_2M_to_1M(unsigned char *m);\r
679PICO_INTERNAL_ASM void wram_1M_to_2M(unsigned char *m);\r
680\r
681// cd/buffering.c\r
682PICO_INTERNAL void PicoCDBufferRead(void *dest, int lba);\r
683\r
684// sound/sound.c\r
9d917eea 685PICO_INTERNAL void PsndReset(void);\r
4b9c5888 686PICO_INTERNAL void PsndDoDAC(int line_to);\r
9d917eea 687PICO_INTERNAL void PsndClear(void);\r
7b3f44c6 688PICO_INTERNAL void PsndGetSamples(int y);\r
2ec9bec5 689PICO_INTERNAL void PsndGetSamplesMS(void);\r
4b9c5888 690extern int PsndDacLine;\r
cc68a136 691\r
3e49ffd0 692// sms.c\r
f3a57b2d 693#ifndef NO_SMS\r
3e49ffd0 694void PicoPowerMS(void);\r
2ec9bec5 695void PicoResetMS(void);\r
3e49ffd0 696void PicoMemSetupMS(void);\r
b4db550e 697void PicoStateLoadedMS(void);\r
3e49ffd0 698void PicoFrameMS(void);\r
87b0845f 699void PicoFrameDrawOnlyMS(void);\r
f3a57b2d 700#else\r
701#define PicoPowerMS()\r
702#define PicoResetMS()\r
703#define PicoMemSetupMS()\r
704#define PicoStateLoadedMS()\r
705#define PicoFrameMS()\r
706#define PicoFrameDrawOnlyMS()\r
707#endif\r
3e49ffd0 708\r
be2c4208 709// 32x/32x.c\r
f3a57b2d 710#ifndef NO_32X\r
be2c4208 711extern struct Pico32x Pico32x;\r
712void Pico32xInit(void);\r
974fdb5b 713void PicoPower32x(void);\r
be2c4208 714void PicoReset32x(void);\r
974fdb5b 715void Pico32xStartup(void);\r
5e49c3a8 716void PicoUnload32x(void);\r
974fdb5b 717void PicoFrame32x(void);\r
ed4402a7 718void p32x_sync_sh2s(unsigned int m68k_target);\r
1f1ff763 719void p32x_update_irls(int nested_call);\r
83ff19ec 720void p32x_reset_sh2s(void);\r
be2c4208 721\r
722// 32x/memory.c\r
974fdb5b 723struct Pico32xMem *Pico32xMem;\r
be2c4208 724unsigned int PicoRead8_32x(unsigned int a);\r
725unsigned int PicoRead16_32x(unsigned int a);\r
726void PicoWrite8_32x(unsigned int a, unsigned int d);\r
727void PicoWrite16_32x(unsigned int a, unsigned int d);\r
728void PicoMemSetup32x(void);\r
974fdb5b 729void Pico32xSwapDRAM(int b);\r
b4db550e 730void Pico32xStateLoaded(void);\r
87accdf7 731void p32x_poll_event(int cpu_mask, int is_vdp);\r
974fdb5b 732\r
733// 32x/draw.c\r
734void FinalizeLine32xRGB555(int sh, int line);\r
5a681086 735void PicoDraw32xLayer(int offs, int lines, int mdbg);\r
7a961c19 736void PicoDraw32xLayerMdOnly(int offs, int lines);\r
f4750ee0 737extern int (*PicoScan32xBegin)(unsigned int num);\r
738extern int (*PicoScan32xEnd)(unsigned int num);\r
7a961c19 739enum {\r
740 PDM32X_OFF,\r
741 PDM32X_32X_ONLY,\r
742 PDM32X_BOTH,\r
743};\r
5a681086 744extern int Pico32xDrawMode;\r
be2c4208 745\r
db1d3564 746// 32x/pwm.c\r
747unsigned int p32x_pwm_read16(unsigned int a);\r
748void p32x_pwm_write16(unsigned int a, unsigned int d);\r
db1d3564 749void p32x_pwm_update(int *buf32, int length, int stereo);\r
1f1ff763 750void p32x_timers_do(int line_call);\r
1d7a28a7 751void p32x_timers_recalc(void);\r
db1d3564 752extern int pwm_frame_smp_cnt;\r
f3a57b2d 753#else\r
754#define Pico32xInit()\r
755#define PicoPower32x()\r
756#define PicoReset32x()\r
757#define PicoFrame32x()\r
758#define PicoUnload32x()\r
759#define Pico32xStateLoaded()\r
760#define PicoDraw32xSetFrameMode(...)\r
761#define FinalizeLine32xRGB555 NULL\r
762#define p32x_pwm_update(...)\r
763#define p32x_timers_recalc()\r
764#endif\r
db1d3564 765\r
45f2f245 766/* avoid dependency on newer glibc */\r
767static __inline int isspace_(int c)\r
768{\r
769 return (0x09 <= c && c <= 0x0d) || c == ' ';\r
770}\r
771\r
f4bb5d6b 772#ifndef ARRAY_SIZE\r
773#define ARRAY_SIZE(x) (sizeof(x) / sizeof(x[0]))\r
774#endif\r
775\r
b8cbd802 776// emulation event logging\r
777#ifndef EL_LOGMASK\r
778#define EL_LOGMASK 0\r
779#endif\r
780\r
017512f2 781#define EL_HVCNT 0x00000001 /* hv counter reads */\r
782#define EL_SR 0x00000002 /* SR reads */\r
783#define EL_INTS 0x00000004 /* ints and acks */\r
43e6eaad 784#define EL_YMTIMER 0x00000008 /* ym2612 timer stuff */\r
017512f2 785#define EL_INTSW 0x00000010 /* log irq switching on/off */\r
786#define EL_ASVDP 0x00000020 /* VDP accesses during active scan */\r
787#define EL_VDPDMA 0x00000040 /* VDP DMA transfers and their timing */\r
788#define EL_BUSREQ 0x00000080 /* z80 busreq r/w or reset w */\r
789#define EL_Z80BNK 0x00000100 /* z80 i/o through bank area */\r
790#define EL_SRAMIO 0x00000200 /* sram i/o */\r
791#define EL_EEPROM 0x00000400 /* eeprom debug */\r
792#define EL_UIO 0x00000800 /* unmapped i/o */\r
793#define EL_IO 0x00001000 /* all i/o */\r
794#define EL_CDPOLL 0x00002000 /* MCD: log poll detection */\r
795#define EL_SVP 0x00004000 /* SVP stuff */\r
fa22af4c 796#define EL_PICOHW 0x00008000 /* Pico stuff */\r
053fd9b4 797#define EL_IDLE 0x00010000 /* idle loop det. */\r
af37bca8 798#define EL_CDREGS 0x00020000 /* MCD: register access */\r
799#define EL_CDREG3 0x00040000 /* MCD: register 3 only */\r
be2c4208 800#define EL_32X 0x00080000\r
1b3f5844 801#define EL_PWM 0x00100000 /* 32X PWM stuff (LOTS of output) */\r
017512f2 802\r
803#define EL_STATUS 0x40000000 /* status messages */\r
804#define EL_ANOMALY 0x80000000 /* some unexpected conditions (during emulation) */\r
b8cbd802 805\r
806#if EL_LOGMASK\r
807#define elprintf(w,f,...) \\r
808{ \\r
809 if ((w) & EL_LOGMASK) \\r
7d0143a2 810 lprintf("%05i:%03i: " f "\n",Pico.m.frame_count,Pico.m.scanline,##__VA_ARGS__); \\r
b8cbd802 811}\r
dca310c4 812#elif defined(_MSC_VER)\r
813#define elprintf\r
b8cbd802 814#else\r
815#define elprintf(w,f,...)\r
816#endif\r
817\r
f6c49d38 818// profiling\r
819#ifdef PPROF\r
820#include <platform/linux/pprof.h>\r
821#else\r
822#define pprof_init()\r
823#define pprof_finish()\r
824#define pprof_start(x)\r
825#define pprof_end(...)\r
826#define pprof_end_sub(...)\r
827#endif\r
828\r
829// misc\r
dca310c4 830#ifdef _MSC_VER\r
831#define cdprintf\r
832#else\r
833#define cdprintf(x...)\r
834#endif\r
835\r
553c3eaa 836#ifdef __i386__\r
837#define REGPARM(x) __attribute__((regparm(x)))\r
c8d1e9b6 838#else\r
553c3eaa 839#define REGPARM(x)\r
c8d1e9b6 840#endif\r
841\r
5e89f0f5 842#ifdef __GNUC__\r
843#define NOINLINE __attribute__((noinline))\r
844#else\r
845#define NOINLINE\r
846#endif\r
847\r
f8af9634 848#ifdef __cplusplus\r
849} // End of extern "C"\r
850#endif\r
851\r
eff55556 852#endif // PICO_INTERNAL_INCLUDED\r
853\r
fast MegaDrive/MegaCD/32X emulator