| cff531af |
1 | /*\r |
| 2 | * PicoDrive - Internal Header File\r |
| 3 | * (c) Copyright Dave, 2004\r |
| 4 | * (C) notaz, 2006-2010\r |
| 5 | *\r |
| 6 | * This work is licensed under the terms of MAME license.\r |
| 7 | * See COPYING file in the top-level directory.\r |
| 8 | */\r |
| cc68a136 |
9 | \r |
| eff55556 |
10 | #ifndef PICO_INTERNAL_INCLUDED\r |
| 11 | #define PICO_INTERNAL_INCLUDED\r |
| cc68a136 |
12 | \r |
| 13 | #include <stdio.h>\r |
| 14 | #include <stdlib.h>\r |
| 15 | #include <string.h>\r |
| efcba75f |
16 | #include "pico.h"\r |
| f53f286a |
17 | #include "carthw/carthw.h"\r |
| cc68a136 |
18 | \r |
| 89fa852d |
19 | //\r |
| 20 | #define USE_POLL_DETECT\r |
| 21 | \r |
| eff55556 |
22 | #ifndef PICO_INTERNAL\r |
| 23 | #define PICO_INTERNAL\r |
| 24 | #endif\r |
| 25 | #ifndef PICO_INTERNAL_ASM\r |
| 26 | #define PICO_INTERNAL_ASM\r |
| 27 | #endif\r |
| cc68a136 |
28 | \r |
| 70357ce5 |
29 | // to select core, define EMU_C68K, EMU_M68K or EMU_F68K in your makefile or project\r |
| cc68a136 |
30 | \r |
| 31 | #ifdef __cplusplus\r |
| 32 | extern "C" {\r |
| 33 | #endif\r |
| 34 | \r |
| 35 | \r |
| 36 | // ----------------------- 68000 CPU -----------------------\r |
| 37 | #ifdef EMU_C68K\r |
| d4d62665 |
38 | #include "../cpu/cyclone/Cyclone.h"\r |
| 3aa1e148 |
39 | extern struct Cyclone PicoCpuCM68k, PicoCpuCS68k;\r |
| 40 | #define SekCyclesLeftNoMCD PicoCpuCM68k.cycles // cycles left for this run\r |
| 7336a99a |
41 | #define SekCyclesLeft \\r |
| 602133e1 |
42 | (((PicoAHW&1) && (PicoOpt & POPT_EN_MCD_PSYNC)) ? (SekCycleAim-SekCycleCnt) : SekCyclesLeftNoMCD)\r |
| 7a1f6e45 |
43 | #define SekCyclesLeftS68k \\r |
| 602133e1 |
44 | ((PicoOpt & POPT_EN_MCD_PSYNC) ? (SekCycleAimS68k-SekCycleCntS68k) : PicoCpuCS68k.cycles)\r |
| ef090115 |
45 | #define SekEndTimeslice(after) PicoCpuCM68k.cycles=after\r |
| 07ceafdb |
46 | #define SekEndTimesliceS68k(after) PicoCpuCS68k.cycles=after\r |
| 3aa1e148 |
47 | #define SekPc (PicoCpuCM68k.pc-PicoCpuCM68k.membase)\r |
| 48 | #define SekPcS68k (PicoCpuCS68k.pc-PicoCpuCS68k.membase)\r |
| d4d62665 |
49 | #define SekDar(x) (x < 8 ? PicoCpuCM68k.d[x] : PicoCpuCM68k.a[x - 8])\r |
| 5fadfb1c |
50 | #define SekSr CycloneGetSr(&PicoCpuCM68k)\r |
| 3aa1e148 |
51 | #define SekSetStop(x) { PicoCpuCM68k.state_flags&=~1; if (x) { PicoCpuCM68k.state_flags|=1; PicoCpuCM68k.cycles=0; } }\r |
| 52 | #define SekSetStopS68k(x) { PicoCpuCS68k.state_flags&=~1; if (x) { PicoCpuCS68k.state_flags|=1; PicoCpuCS68k.cycles=0; } }\r |
| ed4402a7 |
53 | #define SekIsStoppedM68k() (PicoCpuCM68k.state_flags&1)\r |
| ca61ee42 |
54 | #define SekIsStoppedS68k() (PicoCpuCS68k.state_flags&1)\r |
| 03e4f2a3 |
55 | #define SekShouldInterrupt (PicoCpuCM68k.irq > (PicoCpuCM68k.srh&7))\r |
| b542be46 |
56 | \r |
| 57 | #define SekInterrupt(i) PicoCpuCM68k.irq=i\r |
| 5fadfb1c |
58 | #define SekIrqLevel PicoCpuCM68k.irq\r |
| b542be46 |
59 | \r |
| 03e4f2a3 |
60 | #ifdef EMU_M68K\r |
| 61 | #define EMU_CORE_DEBUG\r |
| 62 | #endif\r |
| cc68a136 |
63 | #endif\r |
| 64 | \r |
| 70357ce5 |
65 | #ifdef EMU_F68K\r |
| 66 | #include "../cpu/fame/fame.h"\r |
| b542be46 |
67 | extern M68K_CONTEXT PicoCpuFM68k, PicoCpuFS68k;\r |
| 3aa1e148 |
68 | #define SekCyclesLeftNoMCD PicoCpuFM68k.io_cycle_counter\r |
| 70357ce5 |
69 | #define SekCyclesLeft \\r |
| 602133e1 |
70 | (((PicoAHW&1) && (PicoOpt & POPT_EN_MCD_PSYNC)) ? (SekCycleAim-SekCycleCnt) : SekCyclesLeftNoMCD)\r |
| 70357ce5 |
71 | #define SekCyclesLeftS68k \\r |
| 602133e1 |
72 | ((PicoOpt & POPT_EN_MCD_PSYNC) ? (SekCycleAimS68k-SekCycleCntS68k) : PicoCpuFS68k.io_cycle_counter)\r |
| ef090115 |
73 | #define SekEndTimeslice(after) PicoCpuFM68k.io_cycle_counter=after\r |
| 07ceafdb |
74 | #define SekEndTimesliceS68k(after) PicoCpuFS68k.io_cycle_counter=after\r |
| 03e4f2a3 |
75 | #define SekPc fm68k_get_pc(&PicoCpuFM68k)\r |
| 76 | #define SekPcS68k fm68k_get_pc(&PicoCpuFS68k)\r |
| d4d62665 |
77 | #define SekDar(x) (x < 8 ? PicoCpuFM68k.dreg[x].D : PicoCpuFM68k.areg[x - 8].D)\r |
| 5fadfb1c |
78 | #define SekSr PicoCpuFM68k.sr\r |
| 70357ce5 |
79 | #define SekSetStop(x) { \\r |
| 03e4f2a3 |
80 | PicoCpuFM68k.execinfo &= ~FM68K_HALTED; \\r |
| 81 | if (x) { PicoCpuFM68k.execinfo |= FM68K_HALTED; PicoCpuFM68k.io_cycle_counter = 0; } \\r |
| 70357ce5 |
82 | }\r |
| 83 | #define SekSetStopS68k(x) { \\r |
| 03e4f2a3 |
84 | PicoCpuFS68k.execinfo &= ~FM68K_HALTED; \\r |
| 85 | if (x) { PicoCpuFS68k.execinfo |= FM68K_HALTED; PicoCpuFS68k.io_cycle_counter = 0; } \\r |
| 70357ce5 |
86 | }\r |
| ed4402a7 |
87 | #define SekIsStoppedM68k() (PicoCpuFM68k.execinfo&FM68K_HALTED)\r |
| ca61ee42 |
88 | #define SekIsStoppedS68k() (PicoCpuFS68k.execinfo&FM68K_HALTED)\r |
| 03e4f2a3 |
89 | #define SekShouldInterrupt fm68k_would_interrupt()\r |
| b542be46 |
90 | \r |
| 91 | #define SekInterrupt(irq) PicoCpuFM68k.interrupts[0]=irq\r |
| 5fadfb1c |
92 | #define SekIrqLevel PicoCpuFM68k.interrupts[0]\r |
| b542be46 |
93 | \r |
| 03e4f2a3 |
94 | #ifdef EMU_M68K\r |
| 95 | #define EMU_CORE_DEBUG\r |
| 96 | #endif\r |
| cc68a136 |
97 | #endif\r |
| 98 | \r |
| 99 | #ifdef EMU_M68K\r |
| 100 | #include "../cpu/musashi/m68kcpu.h"\r |
| 3aa1e148 |
101 | extern m68ki_cpu_core PicoCpuMM68k, PicoCpuMS68k;\r |
| cc68a136 |
102 | #ifndef SekCyclesLeft\r |
| 3aa1e148 |
103 | #define SekCyclesLeftNoMCD PicoCpuMM68k.cyc_remaining_cycles\r |
| 7336a99a |
104 | #define SekCyclesLeft \\r |
| 602133e1 |
105 | (((PicoAHW&1) && (PicoOpt & POPT_EN_MCD_PSYNC)) ? (SekCycleAim-SekCycleCnt) : SekCyclesLeftNoMCD)\r |
| 7a1f6e45 |
106 | #define SekCyclesLeftS68k \\r |
| 602133e1 |
107 | ((PicoOpt & POPT_EN_MCD_PSYNC) ? (SekCycleAimS68k-SekCycleCntS68k) : PicoCpuMS68k.cyc_remaining_cycles)\r |
| ef090115 |
108 | #define SekEndTimeslice(after) SET_CYCLES(after)\r |
| 07ceafdb |
109 | #define SekEndTimesliceS68k(after) PicoCpuMS68k.cyc_remaining_cycles=after\r |
| 3aa1e148 |
110 | #define SekPc m68k_get_reg(&PicoCpuMM68k, M68K_REG_PC)\r |
| 111 | #define SekPcS68k m68k_get_reg(&PicoCpuMS68k, M68K_REG_PC)\r |
| 5fadfb1c |
112 | #define SekDar(x) PicoCpuMM68k.dar[x]\r |
| 113 | #define SekSr m68k_get_reg(&PicoCpuMM68k, M68K_REG_SR)\r |
| 7a1f6e45 |
114 | #define SekSetStop(x) { \\r |
| 3aa1e148 |
115 | if(x) { SET_CYCLES(0); PicoCpuMM68k.stopped=STOP_LEVEL_STOP; } \\r |
| 116 | else PicoCpuMM68k.stopped=0; \\r |
| 7a1f6e45 |
117 | }\r |
| 118 | #define SekSetStopS68k(x) { \\r |
| 3aa1e148 |
119 | if(x) { SET_CYCLES(0); PicoCpuMS68k.stopped=STOP_LEVEL_STOP; } \\r |
| 120 | else PicoCpuMS68k.stopped=0; \\r |
| 7a1f6e45 |
121 | }\r |
| ed4402a7 |
122 | #define SekIsStoppedM68k() (PicoCpuMM68k.stopped==STOP_LEVEL_STOP)\r |
| ca61ee42 |
123 | #define SekIsStoppedS68k() (PicoCpuMS68k.stopped==STOP_LEVEL_STOP)\r |
| 03e4f2a3 |
124 | #define SekShouldInterrupt (CPU_INT_LEVEL > FLAG_INT_MASK)\r |
| b542be46 |
125 | \r |
| 71de3cd9 |
126 | #define SekInterrupt(irq) { \\r |
| b542be46 |
127 | void *oldcontext = m68ki_cpu_p; \\r |
| 128 | m68k_set_context(&PicoCpuMM68k); \\r |
| 129 | m68k_set_irq(irq); \\r |
| 130 | m68k_set_context(oldcontext); \\r |
| 131 | }\r |
| 5fadfb1c |
132 | #define SekIrqLevel (PicoCpuMM68k.int_level >> 8)\r |
| b542be46 |
133 | \r |
| cc68a136 |
134 | #endif\r |
| ef090115 |
135 | #endif // EMU_M68K\r |
| cc68a136 |
136 | \r |
| 137 | extern int SekCycleCnt; // cycles done in this frame\r |
| 138 | extern int SekCycleAim; // cycle aim\r |
| 139 | extern unsigned int SekCycleCntT; // total cycle counter, updated once per frame\r |
| 140 | \r |
| b8cbd802 |
141 | #define SekCyclesReset() { \\r |
| 142 | SekCycleCntT+=SekCycleAim; \\r |
| 143 | SekCycleCnt-=SekCycleAim; \\r |
| 144 | SekCycleAim=0; \\r |
| 145 | }\r |
| cc68a136 |
146 | #define SekCyclesBurn(c) SekCycleCnt+=c\r |
| 4b9c5888 |
147 | #define SekCyclesDone() (SekCycleAim-SekCyclesLeft) // number of cycles done in this frame (can be checked anywhere)\r |
| cc68a136 |
148 | #define SekCyclesDoneT() (SekCycleCntT+SekCyclesDone()) // total nuber of cycles done for this rom\r |
| 19886062 |
149 | #define SekCyclesDoneT2() (SekCycleCntT + SekCycleCnt) // same as above but not from memhandlers\r |
| cc68a136 |
150 | \r |
| 151 | #define SekEndRun(after) { \\r |
| ef090115 |
152 | SekCycleCnt -= SekCyclesLeft - (after); \\r |
| 153 | if (SekCycleCnt < 0) SekCycleCnt = 0; \\r |
| 154 | SekEndTimeslice(after); \\r |
| cc68a136 |
155 | }\r |
| 156 | \r |
| 07ceafdb |
157 | #define SekEndRunS68k(after) { \\r |
| 158 | SekCycleCntS68k -= SekCyclesLeftS68k - (after); \\r |
| 159 | if (SekCycleCntS68k < 0) SekCycleCntS68k = 0; \\r |
| 160 | SekEndTimesliceS68k(after); \\r |
| 161 | }\r |
| 162 | \r |
| cc68a136 |
163 | extern int SekCycleCntS68k;\r |
| 164 | extern int SekCycleAimS68k;\r |
| 165 | \r |
| bf5fbbb4 |
166 | #define SekCyclesResetS68k() { \\r |
| 167 | SekCycleCntS68k-=SekCycleAimS68k; \\r |
| 168 | SekCycleAimS68k=0; \\r |
| 169 | }\r |
| 7a1f6e45 |
170 | #define SekCyclesDoneS68k() (SekCycleAimS68k-SekCyclesLeftS68k)\r |
| cc68a136 |
171 | \r |
| 03e4f2a3 |
172 | #ifdef EMU_CORE_DEBUG\r |
| 99464b62 |
173 | extern int dbg_irq_level;\r |
| ef090115 |
174 | #undef SekEndTimeslice\r |
| 2d0b15bb |
175 | #undef SekCyclesBurn\r |
| 176 | #undef SekEndRun\r |
| 99464b62 |
177 | #undef SekInterrupt\r |
| ef090115 |
178 | #define SekEndTimeslice(c)\r |
| 2270612a |
179 | #define SekCyclesBurn(c) c\r |
| 2d0b15bb |
180 | #define SekEndRun(c)\r |
| 99464b62 |
181 | #define SekInterrupt(irq) dbg_irq_level=irq\r |
| 2d0b15bb |
182 | #endif\r |
| cc68a136 |
183 | \r |
| b542be46 |
184 | // ----------------------- Z80 CPU -----------------------\r |
| 185 | \r |
| b4db550e |
186 | #if defined(_USE_DRZ80)\r |
| dca310c4 |
187 | #include "../cpu/DrZ80/drz80.h"\r |
| b542be46 |
188 | \r |
| 189 | extern struct DrZ80 drZ80;\r |
| 190 | \r |
| 191 | #define z80_run(cycles) ((cycles) - DrZ80Run(&drZ80, cycles))\r |
| 192 | #define z80_run_nr(cycles) DrZ80Run(&drZ80, cycles)\r |
| 4936aac1 |
193 | #define z80_int() drZ80.Z80_IRQ = 1\r |
| 4b9c5888 |
194 | \r |
| 195 | #define z80_cyclesLeft drZ80.cycles\r |
| 19954be1 |
196 | #define z80_pc() (drZ80.Z80PC - drZ80.Z80PC_BASE)\r |
| b542be46 |
197 | \r |
| 198 | #elif defined(_USE_CZ80)\r |
| dca310c4 |
199 | #include "../cpu/cz80/cz80.h"\r |
| b542be46 |
200 | \r |
| 201 | #define z80_run(cycles) Cz80_Exec(&CZ80, cycles)\r |
| 202 | #define z80_run_nr(cycles) Cz80_Exec(&CZ80, cycles)\r |
| 203 | #define z80_int() Cz80_Set_IRQ(&CZ80, 0, HOLD_LINE)\r |
| 4b9c5888 |
204 | \r |
| 205 | #define z80_cyclesLeft (CZ80.ICount - CZ80.ExtraCycles)\r |
| 19954be1 |
206 | #define z80_pc() Cz80_Get_Reg(&CZ80, CZ80_PC)\r |
| b542be46 |
207 | \r |
| 208 | #else\r |
| 209 | \r |
| 210 | #define z80_run(cycles) (cycles)\r |
| 211 | #define z80_run_nr(cycles)\r |
| 212 | #define z80_int()\r |
| b542be46 |
213 | \r |
| 214 | #endif\r |
| 215 | \r |
| b4db550e |
216 | #define Z80_STATE_SIZE 0x60\r |
| 217 | \r |
| 4b9c5888 |
218 | extern int z80stopCycle; /* in 68k cycles */\r |
| 219 | extern int z80_cycle_cnt; /* 'done' z80 cycles before z80_run() */\r |
| 220 | extern int z80_cycle_aim;\r |
| 221 | extern int z80_scanline;\r |
| 222 | extern int z80_scanline_cycles; /* cycles done until z80_scanline */\r |
| 223 | \r |
| 224 | #define z80_resetCycles() \\r |
| 225 | z80_cycle_cnt = z80_cycle_aim = z80_scanline = z80_scanline_cycles = 0;\r |
| 226 | \r |
| 227 | #define z80_cyclesDone() \\r |
| 228 | (z80_cycle_aim - z80_cyclesLeft)\r |
| 229 | \r |
| 230 | #define cycles_68k_to_z80(x) ((x)*957 >> 11)\r |
| 231 | \r |
| acd35d4c |
232 | // ----------------------- SH2 CPU -----------------------\r |
| 233 | \r |
| 41397701 |
234 | #include "cpu/sh2/sh2.h"\r |
| acd35d4c |
235 | \r |
| 1d7a28a7 |
236 | extern SH2 sh2s[2];\r |
| 237 | #define msh2 sh2s[0]\r |
| 238 | #define ssh2 sh2s[1]\r |
| 239 | \r |
| 679af8a3 |
240 | #ifndef DRC_SH2\r |
| 19886062 |
241 | # define sh2_end_run(sh2, after_) do { \\r |
| 242 | if ((sh2)->icount > (after_)) { \\r |
| f4c0720c |
243 | (sh2)->cycles_timeslice -= (sh2)->icount; \\r |
| 19886062 |
244 | (sh2)->icount = after_; \\r |
| a8fd6e37 |
245 | } \\r |
| 246 | } while (0)\r |
| 19886062 |
247 | # define sh2_cycles_left(sh2) (sh2)->icount\r |
| 6d797957 |
248 | # define sh2_pc(c) (c) ? ssh2.ppc : msh2.ppc\r |
| 679af8a3 |
249 | #else\r |
| 19886062 |
250 | # define sh2_end_run(sh2, after_) do { \\r |
| 251 | int left_ = (signed int)(sh2)->sr >> 12; \\r |
| 252 | if (left_ > (after_)) { \\r |
| 253 | (sh2)->cycles_timeslice -= left_; \\r |
| f4c0720c |
254 | (sh2)->sr &= 0xfff; \\r |
| 19886062 |
255 | (sh2)->sr |= (after_) << 12; \\r |
| a8fd6e37 |
256 | } \\r |
| 257 | } while (0)\r |
| 19886062 |
258 | # define sh2_cycles_left(sh2) ((signed int)(sh2)->sr >> 12)\r |
| 6d797957 |
259 | # define sh2_pc(c) (c) ? ssh2.pc : msh2.pc\r |
| 679af8a3 |
260 | #endif\r |
| 266c6afa |
261 | \r |
| 19886062 |
262 | #define sh2_cycles_done(sh2) ((int)(sh2)->cycles_timeslice - sh2_cycles_left(sh2))\r |
| 263 | #define sh2_cycles_done_m68k(sh2) \\r |
| 264 | ((sh2)->m68krcycles_done + (sh2_cycles_done(sh2) / 3))\r |
| 265 | \r |
| 4ea707e1 |
266 | #define sh2_reg(c, x) (c) ? ssh2.r[x] : msh2.r[x]\r |
| 267 | #define sh2_gbr(c) (c) ? ssh2.gbr : msh2.gbr\r |
| 268 | #define sh2_vbr(c) (c) ? ssh2.vbr : msh2.vbr\r |
| 6add7875 |
269 | #define sh2_sr(c) (((c) ? ssh2.sr : msh2.sr) & 0xfff)\r |
| acd35d4c |
270 | \r |
| 83ff19ec |
271 | #define sh2_set_gbr(c, v) \\r |
| 272 | { if (c) ssh2.gbr = v; else msh2.gbr = v; }\r |
| 273 | #define sh2_set_vbr(c, v) \\r |
| 274 | { if (c) ssh2.vbr = v; else msh2.vbr = v; }\r |
| 275 | \r |
| cc68a136 |
276 | // ---------------------------------------------------------\r |
| 277 | \r |
| 278 | // main oscillator clock which controls timing\r |
| 279 | #define OSC_NTSC 53693100\r |
| b8cbd802 |
280 | #define OSC_PAL 53203424\r |
| cc68a136 |
281 | \r |
| 282 | struct PicoVideo\r |
| 283 | {\r |
| 284 | unsigned char reg[0x20];\r |
| b8cbd802 |
285 | unsigned int command; // 32-bit Command\r |
| 286 | unsigned char pending; // 1 if waiting for second half of 32-bit command\r |
| 287 | unsigned char type; // Command type (v/c/vsram read/write)\r |
| 288 | unsigned short addr; // Read/Write address\r |
| 289 | int status; // Status bits\r |
| cc68a136 |
290 | unsigned char pending_ints; // pending interrupts: ??VH????\r |
| b8cbd802 |
291 | signed char lwrite_cnt; // VDP write count during active display line\r |
| 9761a7d0 |
292 | unsigned short v_counter; // V-counter\r |
| 293 | unsigned char pad[0x10];\r |
| cc68a136 |
294 | };\r |
| 295 | \r |
| 296 | struct PicoMisc\r |
| 297 | {\r |
| 298 | unsigned char rotate;\r |
| 299 | unsigned char z80Run;\r |
| e5503e2f |
300 | unsigned char padTHPhase[2]; // 02 phase of gamepad TH switches\r |
| 2aa27095 |
301 | unsigned short scanline; // 04 0 to 261||311\r |
| e5503e2f |
302 | char dirtyPal; // 06 Is the palette dirty (1 - change @ this frame, 2 - some time before)\r |
| 303 | unsigned char hardware; // 07 Hardware value for country\r |
| 304 | unsigned char pal; // 08 1=PAL 0=NTSC\r |
| 45f2f245 |
305 | unsigned char sram_reg; // 09 SRAM reg. See SRR_* below\r |
| e5503e2f |
306 | unsigned short z80_bank68k; // 0a\r |
| be2c4208 |
307 | unsigned short pad0;\r |
| 308 | unsigned char pad1;\r |
| 0ace9b9a |
309 | unsigned char z80_reset; // 0f z80 reset held\r |
| e5503e2f |
310 | unsigned char padDelay[2]; // 10 gamepad phase time outs, so we count a delay\r |
| 1dceadae |
311 | unsigned short eeprom_addr; // EEPROM address register\r |
| 45f2f245 |
312 | unsigned char eeprom_cycle; // EEPROM cycle number\r |
| 1dceadae |
313 | unsigned char eeprom_slave; // EEPROM slave word for X24C02 and better SRAMs\r |
| 45f2f245 |
314 | unsigned char eeprom_status;\r |
| be2c4208 |
315 | unsigned char pad2;\r |
| 053fd9b4 |
316 | unsigned short dma_xfers; // 18\r |
| 45f2f245 |
317 | unsigned char eeprom_wb[2]; // EEPROM latch/write buffer\r |
| 053fd9b4 |
318 | unsigned int frame_count; // 1c for movies and idle det\r |
| cc68a136 |
319 | };\r |
| 320 | \r |
| b4db550e |
321 | struct PicoMS\r |
| 322 | {\r |
| 323 | unsigned char carthw[0x10];\r |
| 324 | unsigned char io_ctl;\r |
| 325 | unsigned char pad[0x4f];\r |
| 326 | };\r |
| 327 | \r |
| cc68a136 |
328 | // some assembly stuff depend on these, do not touch!\r |
| 329 | struct Pico\r |
| 330 | {\r |
| 331 | unsigned char ram[0x10000]; // 0x00000 scratch ram\r |
| 200772b7 |
332 | union { // vram is byteswapped for easier reads when drawing\r |
| 2ec9bec5 |
333 | unsigned short vram[0x8000]; // 0x10000\r |
| 334 | unsigned char vramb[0x4000]; // VRAM in SMS mode\r |
| 335 | };\r |
| cc68a136 |
336 | unsigned char zram[0x2000]; // 0x20000 Z80 ram\r |
| b4db550e |
337 | unsigned char ioports[0x10]; // XXX: fix asm and mv\r |
| 338 | unsigned char pad[0xf0]; // unused\r |
| cc68a136 |
339 | unsigned short cram[0x40]; // 0x22100\r |
| 340 | unsigned short vsram[0x40]; // 0x22180\r |
| 341 | \r |
| 342 | unsigned char *rom; // 0x22200\r |
| 343 | unsigned int romsize; // 0x22204\r |
| 344 | \r |
| 345 | struct PicoMisc m;\r |
| 346 | struct PicoVideo video;\r |
| b4db550e |
347 | struct PicoMS ms;\r |
| cc68a136 |
348 | };\r |
| 349 | \r |
| 350 | // sram\r |
| 45f2f245 |
351 | #define SRR_MAPPED (1 << 0)\r |
| 352 | #define SRR_READONLY (1 << 1)\r |
| 353 | \r |
| 354 | #define SRF_ENABLED (1 << 0)\r |
| 355 | #define SRF_EEPROM (1 << 1)\r |
| af37bca8 |
356 | \r |
| cc68a136 |
357 | struct PicoSRAM\r |
| 358 | {\r |
| 4ff2d527 |
359 | unsigned char *data; // actual data\r |
| 360 | unsigned int start; // start address in 68k address space\r |
| cc68a136 |
361 | unsigned int end;\r |
| 45f2f245 |
362 | unsigned char flags; // 0c: SRF_*\r |
| 1dceadae |
363 | unsigned char unused2;\r |
| cc68a136 |
364 | unsigned char changed;\r |
| 45f2f245 |
365 | unsigned char eeprom_type; // eeprom type: 0: 7bit (24C01), 2: 2 addr words (X24C02+), 3: 3 addr words\r |
| 366 | unsigned char unused3;\r |
| 1dceadae |
367 | unsigned char eeprom_bit_cl; // bit number for cl\r |
| 368 | unsigned char eeprom_bit_in; // bit number for in\r |
| 369 | unsigned char eeprom_bit_out; // bit number for out\r |
| 45f2f245 |
370 | unsigned int size;\r |
| cc68a136 |
371 | };\r |
| 372 | \r |
| 373 | // MCD\r |
| 374 | #include "cd/cd_sys.h"\r |
| 375 | #include "cd/LC89510.h"\r |
| d1df8786 |
376 | #include "cd/gfx_cd.h"\r |
| cc68a136 |
377 | \r |
| 4f265db7 |
378 | struct mcd_pcm\r |
| 379 | {\r |
| 380 | unsigned char control; // reg7\r |
| 381 | unsigned char enabled; // reg8\r |
| 382 | unsigned char cur_ch;\r |
| 383 | unsigned char bank;\r |
| 384 | int pad1;\r |
| 385 | \r |
| 4ff2d527 |
386 | struct pcm_chan // 08, size 0x10\r |
| 4f265db7 |
387 | {\r |
| 388 | unsigned char regs[8];\r |
| 4ff2d527 |
389 | unsigned int addr; // .08: played sample address\r |
| 4f265db7 |
390 | int pad;\r |
| 391 | } ch[8];\r |
| 392 | };\r |
| 393 | \r |
| c459aefd |
394 | struct mcd_misc\r |
| 395 | {\r |
| 396 | unsigned short hint_vector;\r |
| 397 | unsigned char busreq;\r |
| 51a902ae |
398 | unsigned char s68k_pend_ints;\r |
| ef090115 |
399 | unsigned int state_flags; // 04: emu state: reset_pending\r |
| 51a902ae |
400 | unsigned int counter75hz;\r |
| c9e1affc |
401 | unsigned int pad0;\r |
| 4ff2d527 |
402 | int timer_int3; // 10\r |
| 4f265db7 |
403 | unsigned int timer_stopwatch;\r |
| 6cadc2da |
404 | unsigned char bcram_reg; // 18: battery-backed RAM cart register\r |
| 405 | unsigned char pad2;\r |
| 406 | unsigned short pad3;\r |
| 407 | int pad[9];\r |
| c459aefd |
408 | };\r |
| 409 | \r |
| cc68a136 |
410 | typedef struct\r |
| 411 | {\r |
| 4ff2d527 |
412 | unsigned char bios[0x20000]; // 000000: 128K\r |
| 413 | union { // 020000: 512K\r |
| fa1e5e29 |
414 | unsigned char prg_ram[0x80000];\r |
| cc68a136 |
415 | unsigned char prg_ram_b[4][0x20000];\r |
| 416 | };\r |
| 4ff2d527 |
417 | union { // 0a0000: 256K\r |
| fa1e5e29 |
418 | struct {\r |
| 419 | unsigned char word_ram2M[0x40000];\r |
| dca310c4 |
420 | unsigned char unused0[0x20000];\r |
| fa1e5e29 |
421 | };\r |
| 422 | struct {\r |
| dca310c4 |
423 | unsigned char unused1[0x20000];\r |
| fa1e5e29 |
424 | unsigned char word_ram1M[2][0x20000];\r |
| 425 | };\r |
| 426 | };\r |
| 4ff2d527 |
427 | union { // 100000: 64K\r |
| fa1e5e29 |
428 | unsigned char pcm_ram[0x10000];\r |
| 4f265db7 |
429 | unsigned char pcm_ram_b[0x10][0x1000];\r |
| 430 | };\r |
| 4ff2d527 |
431 | unsigned char s68k_regs[0x200]; // 110000: GA, not CPU regs\r |
| 432 | unsigned char bram[0x2000]; // 110200: 8K\r |
| 433 | struct mcd_misc m; // 112200: misc\r |
| 434 | struct mcd_pcm pcm; // 112240:\r |
| 75736070 |
435 | _scd_toc TOC; // not to be saved\r |
| cc68a136 |
436 | CDD cdd;\r |
| 437 | CDC cdc;\r |
| 438 | _scd scd;\r |
| d1df8786 |
439 | Rot_Comp rot_comp;\r |
| cc68a136 |
440 | } mcd_state;\r |
| 441 | \r |
| be2c4208 |
442 | // XXX: this will need to be reworked for cart+cd support.\r |
| cc68a136 |
443 | #define Pico_mcd ((mcd_state *)Pico.rom)\r |
| 444 | \r |
| be2c4208 |
445 | // 32X\r |
| acd35d4c |
446 | #define P32XS_FM (1<<15)\r |
| 83ff19ec |
447 | #define P32XS_REN (1<< 7)\r |
| 448 | #define P32XS_nRES (1<< 1)\r |
| 449 | #define P32XS_ADEN (1<< 0)\r |
| acd35d4c |
450 | #define P32XS2_ADEN (1<< 9)\r |
| 5e128c6d |
451 | #define P32XS_FULL (1<< 7) // DREQ FIFO full\r |
| 4ea707e1 |
452 | #define P32XS_68S (1<< 2)\r |
| 97d3f47f |
453 | #define P32XS_DMA (1<< 1)\r |
| 4ea707e1 |
454 | #define P32XS_RV (1<< 0)\r |
| acd35d4c |
455 | \r |
| 5e128c6d |
456 | #define P32XV_nPAL (1<<15) // VDP\r |
| acd35d4c |
457 | #define P32XV_PRI (1<< 7)\r |
| 4ea707e1 |
458 | #define P32XV_Mx (3<< 0) // display mode mask\r |
| 974fdb5b |
459 | \r |
| e51e5983 |
460 | #define P32XV_SFT (1<< 0)\r |
| 461 | \r |
| acd35d4c |
462 | #define P32XV_VBLK (1<<15)\r |
| 463 | #define P32XV_HBLK (1<<14)\r |
| 464 | #define P32XV_PEN (1<<13)\r |
| 465 | #define P32XV_nFEN (1<< 1)\r |
| 466 | #define P32XV_FS (1<< 0)\r |
| 974fdb5b |
467 | \r |
| db1d3564 |
468 | #define P32XP_FULL (1<<15) // PWM\r |
| 469 | #define P32XP_EMPTY (1<<14)\r |
| 470 | \r |
| 19886062 |
471 | #define P32XF_68KCPOLL (1 << 0)\r |
| 472 | #define P32XF_68KVPOLL (1 << 1)\r |
| a8fd6e37 |
473 | #define P32XF_PWM_PEND (1 << 6)\r |
| 4ea707e1 |
474 | \r |
| 475 | #define P32XI_VRES (1 << 14/2) // IRL/2\r |
| 476 | #define P32XI_VINT (1 << 12/2)\r |
| 477 | #define P32XI_HINT (1 << 10/2)\r |
| 478 | #define P32XI_CMD (1 << 8/2)\r |
| 479 | #define P32XI_PWM (1 << 6/2)\r |
| 480 | \r |
| 1d7a28a7 |
481 | // peripheral reg access\r |
| 482 | #define PREG8(regs,offs) ((unsigned char *)regs)[offs ^ 3]\r |
| 483 | \r |
| 4ea707e1 |
484 | // real one is 4*2, but we use more because we don't lockstep\r |
| 485 | #define DMAC_FIFO_LEN (4*4)\r |
| db1d3564 |
486 | #define PWM_BUFF_LEN 1024 // in one channel samples\r |
| 266c6afa |
487 | \r |
| f4bb5d6b |
488 | #define SH2_DRCBLK_RAM_SHIFT 1\r |
| 489 | #define SH2_DRCBLK_DA_SHIFT 1\r |
| 490 | \r |
| e05b81fc |
491 | #define SH2_WRITE_SHIFT 25\r |
| 492 | \r |
| be2c4208 |
493 | struct Pico32x\r |
| 494 | {\r |
| 495 | unsigned short regs[0x20];\r |
| 5a681086 |
496 | unsigned short vdp_regs[0x10]; // 0x40\r |
| 497 | unsigned short sh2_regs[3]; // 0x60\r |
| be2c4208 |
498 | unsigned char pending_fb;\r |
| 974fdb5b |
499 | unsigned char dirty_pal;\r |
| 266c6afa |
500 | unsigned int emu_flags;\r |
| 4ea707e1 |
501 | unsigned char sh2irq_mask[2];\r |
| 502 | unsigned char sh2irqi[2]; // individual\r |
| 503 | unsigned int sh2irqs; // common irqs\r |
| 504 | unsigned short dmac_fifo[DMAC_FIFO_LEN];\r |
| 505 | unsigned int dmac_ptr;\r |
| db1d3564 |
506 | unsigned int pwm_irq_sample_cnt;\r |
| a8fd6e37 |
507 | unsigned char comm_dirty_68k;\r |
| 508 | unsigned char comm_dirty_sh2;\r |
| 509 | unsigned short pad;\r |
| 510 | unsigned int reserved[8];\r |
| 974fdb5b |
511 | };\r |
| 512 | \r |
| 513 | struct Pico32xMem\r |
| 514 | {\r |
| 515 | unsigned char sdram[0x40000];\r |
| f4bb5d6b |
516 | #ifdef DRC_SH2\r |
| 517 | unsigned short drcblk_ram[1 << (18 - SH2_DRCBLK_RAM_SHIFT)];\r |
| 518 | #endif\r |
| b78efee2 |
519 | unsigned short dram[2][0x20000/2]; // AKA fb\r |
| b4db550e |
520 | union {\r |
| 521 | unsigned char m68k_rom[0x100];\r |
| 522 | unsigned char m68k_rom_bank[0x10000]; // M68K_BANK_SIZE\r |
| 523 | };\r |
| b78efee2 |
524 | unsigned char data_array[2][0x1000]; // cache in SH2s (can be used as RAM)\r |
| f4bb5d6b |
525 | #ifdef DRC_SH2\r |
| 526 | unsigned short drcblk_da[2][1 << (12 - SH2_DRCBLK_DA_SHIFT)];\r |
| 527 | #endif\r |
| acd35d4c |
528 | unsigned char sh2_rom_m[0x800];\r |
| 529 | unsigned char sh2_rom_s[0x400];\r |
| 974fdb5b |
530 | unsigned short pal[0x100];\r |
| 5e128c6d |
531 | unsigned short pal_native[0x100]; // converted to native (for renderer)\r |
| 4ea707e1 |
532 | unsigned int sh2_peri_regs[2][0x200/4]; // periphereal regs of SH2s\r |
| db1d3564 |
533 | signed short pwm[2*PWM_BUFF_LEN]; // PWM buffer for current frame\r |
| be2c4208 |
534 | };\r |
| d49b10c2 |
535 | \r |
| c8d1e9b6 |
536 | // area.c\r |
| fad24893 |
537 | extern void (*PicoLoadStateHook)(void);\r |
| 51a902ae |
538 | \r |
| 945c2fdc |
539 | typedef struct {\r |
| 540 | int chunk;\r |
| 541 | int size;\r |
| 542 | void *ptr;\r |
| 543 | } carthw_state_chunk;\r |
| 544 | extern carthw_state_chunk *carthw_chunks;\r |
| 545 | #define CHUNK_CARTHW 64\r |
| 546 | \r |
| c8d1e9b6 |
547 | // cart.c\r |
| b4db550e |
548 | extern int PicoCartResize(int newsize);\r |
| 549 | extern void Byteswap(void *dst, const void *src, int len);\r |
| 45f2f245 |
550 | extern void (*PicoCartMemSetup)(void);\r |
| e807ac75 |
551 | extern void (*PicoCartUnloadHook)(void);\r |
| 1dceadae |
552 | \r |
| c8d1e9b6 |
553 | // debug.c\r |
| b5e5172d |
554 | int CM_compareRun(int cyc, int is_sub);\r |
| 03e4f2a3 |
555 | \r |
| c8d1e9b6 |
556 | // draw.c\r |
| eff55556 |
557 | PICO_INTERNAL void PicoFrameStart(void);\r |
| b6d7ac70 |
558 | void PicoDrawSync(int to, int blank_last_line);\r |
| 200772b7 |
559 | void BackFill(int reg7, int sh);\r |
| 5a681086 |
560 | void FinalizeLine555(int sh, int line);\r |
| f4750ee0 |
561 | extern int (*PicoScanBegin)(unsigned int num);\r |
| 562 | extern int (*PicoScanEnd)(unsigned int num);\r |
| b6d7ac70 |
563 | extern int DrawScanline;\r |
| f579f7b8 |
564 | #define MAX_LINE_SPRITES 29\r |
| 565 | extern unsigned char HighLnSpr[240][3 + MAX_LINE_SPRITES];\r |
| 5a681086 |
566 | extern void *DrawLineDestBase;\r |
| 567 | extern int DrawLineDestIncrement;\r |
| cc68a136 |
568 | \r |
| c8d1e9b6 |
569 | // draw2.c\r |
| eff55556 |
570 | PICO_INTERNAL void PicoFrameFull();\r |
| cc68a136 |
571 | \r |
| 200772b7 |
572 | // mode4.c\r |
| 573 | void PicoFrameStartMode4(void);\r |
| 574 | void PicoLineMode4(int line);\r |
| 575 | void PicoDoHighPal555M4(void);\r |
| 5a681086 |
576 | void PicoDrawSetOutputMode4(pdso_t which);\r |
| 200772b7 |
577 | \r |
| c8d1e9b6 |
578 | // memory.c\r |
| eff55556 |
579 | PICO_INTERNAL void PicoMemSetup(void);\r |
| af37bca8 |
580 | unsigned int PicoRead8_io(unsigned int a);\r |
| 581 | unsigned int PicoRead16_io(unsigned int a);\r |
| 582 | void PicoWrite8_io(unsigned int a, unsigned int d);\r |
| 583 | void PicoWrite16_io(unsigned int a, unsigned int d);\r |
| 584 | \r |
| 585 | // pico/memory.c\r |
| 586 | PICO_INTERNAL void PicoMemSetupPico(void);\r |
| cc68a136 |
587 | \r |
| c8d1e9b6 |
588 | // cd/memory.c\r |
| eff55556 |
589 | PICO_INTERNAL void PicoMemSetupCD(void);\r |
| 0ace9b9a |
590 | void PicoMemStateLoaded(void);\r |
| cc68a136 |
591 | \r |
| c8d1e9b6 |
592 | // pico.c\r |
| cc68a136 |
593 | extern struct Pico Pico;\r |
| 594 | extern struct PicoSRAM SRam;\r |
| 5f9a0d16 |
595 | extern int PicoPadInt[2];\r |
| cc68a136 |
596 | extern int emustatus;\r |
| 5e128c6d |
597 | extern int scanlines_total;\r |
| f8ef8ff7 |
598 | extern void (*PicoResetHook)(void);\r |
| b0677887 |
599 | extern void (*PicoLineHook)(void);\r |
| 1e6b5e39 |
600 | PICO_INTERNAL int CheckDMA(void);\r |
| 601 | PICO_INTERNAL void PicoDetectRegion(void);\r |
| 4b9c5888 |
602 | PICO_INTERNAL void PicoSyncZ80(int m68k_cycles_done);\r |
| cc68a136 |
603 | \r |
| c8d1e9b6 |
604 | // cd/pico.c\r |
| 2aa27095 |
605 | PICO_INTERNAL void PicoInitMCD(void);\r |
| e5f426aa |
606 | PICO_INTERNAL void PicoExitMCD(void);\r |
| 1cb1584b |
607 | PICO_INTERNAL void PicoPowerMCD(void);\r |
| 2aa27095 |
608 | PICO_INTERNAL int PicoResetMCD(void);\r |
| 609 | PICO_INTERNAL void PicoFrameMCD(void);\r |
| cc68a136 |
610 | \r |
| c8d1e9b6 |
611 | // pico/pico.c\r |
| 2aa27095 |
612 | PICO_INTERNAL void PicoInitPico(void);\r |
| ed367a3f |
613 | PICO_INTERNAL void PicoReratePico(void);\r |
| 9037e45d |
614 | \r |
| c8d1e9b6 |
615 | // pico/xpcm.c\r |
| ef4eb506 |
616 | PICO_INTERNAL void PicoPicoPCMUpdate(short *buffer, int length, int stereo);\r |
| 617 | PICO_INTERNAL void PicoPicoPCMReset(void);\r |
| 213c16ad |
618 | PICO_INTERNAL void PicoPicoPCMRerate(int xpcm_rate);\r |
| ef4eb506 |
619 | \r |
| c8d1e9b6 |
620 | // sek.c\r |
| 2aa27095 |
621 | PICO_INTERNAL void SekInit(void);\r |
| 622 | PICO_INTERNAL int SekReset(void);\r |
| 3aa1e148 |
623 | PICO_INTERNAL void SekState(int *data);\r |
| eff55556 |
624 | PICO_INTERNAL void SekSetRealTAS(int use_real);\r |
| b4db550e |
625 | PICO_INTERNAL void SekPackCpu(unsigned char *cpu, int is_sub);\r |
| 626 | PICO_INTERNAL void SekUnpackCpu(const unsigned char *cpu, int is_sub);\r |
| 5f9a0d16 |
627 | void SekStepM68k(void);\r |
| 053fd9b4 |
628 | void SekInitIdleDet(void);\r |
| 629 | void SekFinishIdleDet(void);\r |
| cc68a136 |
630 | \r |
| c8d1e9b6 |
631 | // cd/sek.c\r |
| 2aa27095 |
632 | PICO_INTERNAL void SekInitS68k(void);\r |
| 633 | PICO_INTERNAL int SekResetS68k(void);\r |
| 634 | PICO_INTERNAL int SekInterruptS68k(int irq);\r |
| cc68a136 |
635 | \r |
| 7a93adeb |
636 | // sound/sound.c\r |
| c9e1affc |
637 | PICO_INTERNAL void cdda_start_play();\r |
| 638 | extern short cdda_out_buffer[2*1152];\r |
| 7a93adeb |
639 | extern int PsndLen_exc_cnt;\r |
| 640 | extern int PsndLen_exc_add;\r |
| 48dc74f2 |
641 | extern int timer_a_next_oflow, timer_a_step; // in z80 cycles\r |
| 642 | extern int timer_b_next_oflow, timer_b_step;\r |
| 43e6eaad |
643 | \r |
| 644 | void ym2612_sync_timers(int z80_cycles, int mode_old, int mode_new);\r |
| d2721b08 |
645 | void ym2612_pack_state(void);\r |
| 453d2a6e |
646 | void ym2612_unpack_state(void);\r |
| 4b9c5888 |
647 | \r |
| e53704e6 |
648 | #define TIMER_NO_OFLOW 0x70000000\r |
| 45a1ef71 |
649 | // tA = 72 * (1024 - NA) / M\r |
| 650 | #define TIMER_A_TICK_ZCYCLES 17203\r |
| 651 | // tB = 1152 * (256 - NA) / M\r |
| 652 | #define TIMER_B_TICK_ZCYCLES 262800 // 275251 broken, see Dai Makaimura\r |
| e53704e6 |
653 | \r |
| 4b9c5888 |
654 | #define timers_cycle() \\r |
| e53704e6 |
655 | if (timer_a_next_oflow > 0 && timer_a_next_oflow < TIMER_NO_OFLOW) \\r |
| 43e6eaad |
656 | timer_a_next_oflow -= Pico.m.pal ? 70938*256 : 59659*256; \\r |
| e53704e6 |
657 | if (timer_b_next_oflow > 0 && timer_b_next_oflow < TIMER_NO_OFLOW) \\r |
| 43e6eaad |
658 | timer_b_next_oflow -= Pico.m.pal ? 70938*256 : 59659*256; \\r |
| 659 | ym2612_sync_timers(0, ym2612.OPN.ST.mode, ym2612.OPN.ST.mode);\r |
| 4b9c5888 |
660 | \r |
| 661 | #define timers_reset() \\r |
| e53704e6 |
662 | timer_a_next_oflow = timer_b_next_oflow = TIMER_NO_OFLOW; \\r |
| 48dc74f2 |
663 | timer_a_step = TIMER_A_TICK_ZCYCLES * 1024; \\r |
| 664 | timer_b_step = TIMER_B_TICK_ZCYCLES * 256;\r |
| 43e6eaad |
665 | \r |
| 7a93adeb |
666 | \r |
| c8d1e9b6 |
667 | // videoport.c\r |
| eff55556 |
668 | PICO_INTERNAL_ASM void PicoVideoWrite(unsigned int a,unsigned short d);\r |
| 669 | PICO_INTERNAL_ASM unsigned int PicoVideoRead(unsigned int a);\r |
| 9761a7d0 |
670 | PICO_INTERNAL_ASM unsigned int PicoVideoRead8(unsigned int a);\r |
| 5de27868 |
671 | extern int (*PicoDmaHook)(unsigned int source, int len, unsigned short **srcp, unsigned short **limitp);\r |
| cc68a136 |
672 | \r |
| c8d1e9b6 |
673 | // misc.c\r |
| eff55556 |
674 | PICO_INTERNAL_ASM void memcpy16(unsigned short *dest, unsigned short *src, int count);\r |
| 675 | PICO_INTERNAL_ASM void memcpy16bswap(unsigned short *dest, void *src, int count);\r |
| 676 | PICO_INTERNAL_ASM void memcpy32(int *dest, int *src, int count); // 32bit word count\r |
| 677 | PICO_INTERNAL_ASM void memset32(int *dest, int c, int count);\r |
| cc68a136 |
678 | \r |
| 45f2f245 |
679 | // eeprom.c\r |
| 680 | void EEPROM_write8(unsigned int a, unsigned int d);\r |
| 681 | void EEPROM_write16(unsigned int d);\r |
| 682 | unsigned int EEPROM_read(void);\r |
| 683 | \r |
| c8d1e9b6 |
684 | // z80 functionality wrappers\r |
| 685 | PICO_INTERNAL void z80_init(void);\r |
| b4db550e |
686 | PICO_INTERNAL void z80_pack(void *data);\r |
| 687 | PICO_INTERNAL int z80_unpack(const void *data);\r |
| c8d1e9b6 |
688 | PICO_INTERNAL void z80_reset(void);\r |
| 689 | PICO_INTERNAL void z80_exit(void);\r |
| c8d1e9b6 |
690 | \r |
| 691 | // cd/misc.c\r |
| eff55556 |
692 | PICO_INTERNAL_ASM void wram_2M_to_1M(unsigned char *m);\r |
| 693 | PICO_INTERNAL_ASM void wram_1M_to_2M(unsigned char *m);\r |
| 694 | \r |
| 695 | // cd/buffering.c\r |
| 696 | PICO_INTERNAL void PicoCDBufferRead(void *dest, int lba);\r |
| 697 | \r |
| 698 | // sound/sound.c\r |
| 9d917eea |
699 | PICO_INTERNAL void PsndReset(void);\r |
| 4b9c5888 |
700 | PICO_INTERNAL void PsndDoDAC(int line_to);\r |
| 9d917eea |
701 | PICO_INTERNAL void PsndClear(void);\r |
| 7b3f44c6 |
702 | PICO_INTERNAL void PsndGetSamples(int y);\r |
| 2ec9bec5 |
703 | PICO_INTERNAL void PsndGetSamplesMS(void);\r |
| 4b9c5888 |
704 | extern int PsndDacLine;\r |
| cc68a136 |
705 | \r |
| 3e49ffd0 |
706 | // sms.c\r |
| f3a57b2d |
707 | #ifndef NO_SMS\r |
| 3e49ffd0 |
708 | void PicoPowerMS(void);\r |
| 2ec9bec5 |
709 | void PicoResetMS(void);\r |
| 3e49ffd0 |
710 | void PicoMemSetupMS(void);\r |
| b4db550e |
711 | void PicoStateLoadedMS(void);\r |
| 3e49ffd0 |
712 | void PicoFrameMS(void);\r |
| 87b0845f |
713 | void PicoFrameDrawOnlyMS(void);\r |
| f3a57b2d |
714 | #else\r |
| 715 | #define PicoPowerMS()\r |
| 716 | #define PicoResetMS()\r |
| 717 | #define PicoMemSetupMS()\r |
| 718 | #define PicoStateLoadedMS()\r |
| 719 | #define PicoFrameMS()\r |
| 720 | #define PicoFrameDrawOnlyMS()\r |
| 721 | #endif\r |
| 3e49ffd0 |
722 | \r |
| be2c4208 |
723 | // 32x/32x.c\r |
| f3a57b2d |
724 | #ifndef NO_32X\r |
| be2c4208 |
725 | extern struct Pico32x Pico32x;\r |
| 6a98f03e |
726 | enum p32x_event {\r |
| 727 | P32X_EVENT_PWM,\r |
| 728 | P32X_EVENT_FILLEND,\r |
| 729 | P32X_EVENT_COUNT,\r |
| 730 | };\r |
| 731 | extern unsigned int event_times[P32X_EVENT_COUNT];\r |
| 732 | \r |
| be2c4208 |
733 | void Pico32xInit(void);\r |
| 974fdb5b |
734 | void PicoPower32x(void);\r |
| be2c4208 |
735 | void PicoReset32x(void);\r |
| 974fdb5b |
736 | void Pico32xStartup(void);\r |
| 5e49c3a8 |
737 | void PicoUnload32x(void);\r |
| 974fdb5b |
738 | void PicoFrame32x(void);\r |
| 27e26273 |
739 | void Pico32xStateLoaded(int is_early);\r |
| ed4402a7 |
740 | void p32x_sync_sh2s(unsigned int m68k_target);\r |
| 19886062 |
741 | void p32x_sync_other_sh2(SH2 *sh2, unsigned int m68k_target);\r |
| 742 | void p32x_update_irls(SH2 *active_sh2);\r |
| 83ff19ec |
743 | void p32x_reset_sh2s(void);\r |
| 19886062 |
744 | void p32x_event_schedule(unsigned int now, enum p32x_event event, int after);\r |
| 745 | void p32x_event_schedule_sh2(SH2 *sh2, enum p32x_event event, int after);\r |
| a8fd6e37 |
746 | \r |
| be2c4208 |
747 | // 32x/memory.c\r |
| 974fdb5b |
748 | struct Pico32xMem *Pico32xMem;\r |
| be2c4208 |
749 | unsigned int PicoRead8_32x(unsigned int a);\r |
| 750 | unsigned int PicoRead16_32x(unsigned int a);\r |
| 751 | void PicoWrite8_32x(unsigned int a, unsigned int d);\r |
| 752 | void PicoWrite16_32x(unsigned int a, unsigned int d);\r |
| 753 | void PicoMemSetup32x(void);\r |
| 974fdb5b |
754 | void Pico32xSwapDRAM(int b);\r |
| 27e26273 |
755 | void Pico32xMemStateLoaded(void);\r |
| 19886062 |
756 | void p32x_m68k_poll_event(unsigned int flags);\r |
| 757 | void p32x_sh2_poll_event(SH2 *sh2, unsigned int flags, unsigned int m68k_cycles);\r |
| 974fdb5b |
758 | \r |
| 759 | // 32x/draw.c\r |
| 41946d70 |
760 | void PicoDrawSetOutFormat32x(pdso_t which, int use_32x_line_mode);\r |
| 974fdb5b |
761 | void FinalizeLine32xRGB555(int sh, int line);\r |
| 5a681086 |
762 | void PicoDraw32xLayer(int offs, int lines, int mdbg);\r |
| 7a961c19 |
763 | void PicoDraw32xLayerMdOnly(int offs, int lines);\r |
| f4750ee0 |
764 | extern int (*PicoScan32xBegin)(unsigned int num);\r |
| 765 | extern int (*PicoScan32xEnd)(unsigned int num);\r |
| 7a961c19 |
766 | enum {\r |
| 767 | PDM32X_OFF,\r |
| 768 | PDM32X_32X_ONLY,\r |
| 769 | PDM32X_BOTH,\r |
| 770 | };\r |
| 5a681086 |
771 | extern int Pico32xDrawMode;\r |
| be2c4208 |
772 | \r |
| db1d3564 |
773 | // 32x/pwm.c\r |
| 774 | unsigned int p32x_pwm_read16(unsigned int a);\r |
| 775 | void p32x_pwm_write16(unsigned int a, unsigned int d);\r |
| db1d3564 |
776 | void p32x_pwm_update(int *buf32, int length, int stereo);\r |
| a8fd6e37 |
777 | void p32x_timers_do(unsigned int cycles);\r |
| 1d7a28a7 |
778 | void p32x_timers_recalc(void);\r |
| a8fd6e37 |
779 | void p32x_pwm_schedule(unsigned int now);\r |
| 19886062 |
780 | void p32x_pwm_schedule_sh2(SH2 *sh2);\r |
| f3a57b2d |
781 | #else\r |
| 782 | #define Pico32xInit()\r |
| 783 | #define PicoPower32x()\r |
| 784 | #define PicoReset32x()\r |
| 785 | #define PicoFrame32x()\r |
| 786 | #define PicoUnload32x()\r |
| 787 | #define Pico32xStateLoaded()\r |
| f3a57b2d |
788 | #define FinalizeLine32xRGB555 NULL\r |
| 789 | #define p32x_pwm_update(...)\r |
| 790 | #define p32x_timers_recalc()\r |
| 791 | #endif\r |
| db1d3564 |
792 | \r |
| 45f2f245 |
793 | /* avoid dependency on newer glibc */\r |
| 794 | static __inline int isspace_(int c)\r |
| 795 | {\r |
| 796 | return (0x09 <= c && c <= 0x0d) || c == ' ';\r |
| 797 | }\r |
| 798 | \r |
| f4bb5d6b |
799 | #ifndef ARRAY_SIZE\r |
| 800 | #define ARRAY_SIZE(x) (sizeof(x) / sizeof(x[0]))\r |
| 801 | #endif\r |
| 802 | \r |
| b8cbd802 |
803 | // emulation event logging\r |
| 804 | #ifndef EL_LOGMASK\r |
| 9c9cda8c |
805 | # ifdef __x86_64__ // HACK\r |
| 806 | # define EL_LOGMASK (EL_STATUS|EL_IDLE|EL_ANOMALY)\r |
| 807 | # else\r |
| 1555935b |
808 | # define EL_LOGMASK (EL_STATUS)\r |
| 9c9cda8c |
809 | # endif\r |
| b8cbd802 |
810 | #endif\r |
| 811 | \r |
| 017512f2 |
812 | #define EL_HVCNT 0x00000001 /* hv counter reads */\r |
| 813 | #define EL_SR 0x00000002 /* SR reads */\r |
| 814 | #define EL_INTS 0x00000004 /* ints and acks */\r |
| 43e6eaad |
815 | #define EL_YMTIMER 0x00000008 /* ym2612 timer stuff */\r |
| 017512f2 |
816 | #define EL_INTSW 0x00000010 /* log irq switching on/off */\r |
| 817 | #define EL_ASVDP 0x00000020 /* VDP accesses during active scan */\r |
| 818 | #define EL_VDPDMA 0x00000040 /* VDP DMA transfers and their timing */\r |
| 819 | #define EL_BUSREQ 0x00000080 /* z80 busreq r/w or reset w */\r |
| 820 | #define EL_Z80BNK 0x00000100 /* z80 i/o through bank area */\r |
| 821 | #define EL_SRAMIO 0x00000200 /* sram i/o */\r |
| 822 | #define EL_EEPROM 0x00000400 /* eeprom debug */\r |
| 823 | #define EL_UIO 0x00000800 /* unmapped i/o */\r |
| 824 | #define EL_IO 0x00001000 /* all i/o */\r |
| 825 | #define EL_CDPOLL 0x00002000 /* MCD: log poll detection */\r |
| 826 | #define EL_SVP 0x00004000 /* SVP stuff */\r |
| fa22af4c |
827 | #define EL_PICOHW 0x00008000 /* Pico stuff */\r |
| 053fd9b4 |
828 | #define EL_IDLE 0x00010000 /* idle loop det. */\r |
| af37bca8 |
829 | #define EL_CDREGS 0x00020000 /* MCD: register access */\r |
| 830 | #define EL_CDREG3 0x00040000 /* MCD: register 3 only */\r |
| be2c4208 |
831 | #define EL_32X 0x00080000\r |
| 1b3f5844 |
832 | #define EL_PWM 0x00100000 /* 32X PWM stuff (LOTS of output) */\r |
| 017512f2 |
833 | \r |
| 834 | #define EL_STATUS 0x40000000 /* status messages */\r |
| 835 | #define EL_ANOMALY 0x80000000 /* some unexpected conditions (during emulation) */\r |
| b8cbd802 |
836 | \r |
| 837 | #if EL_LOGMASK\r |
| 838 | #define elprintf(w,f,...) \\r |
| a8fd6e37 |
839 | do { \\r |
| b8cbd802 |
840 | if ((w) & EL_LOGMASK) \\r |
| 7d0143a2 |
841 | lprintf("%05i:%03i: " f "\n",Pico.m.frame_count,Pico.m.scanline,##__VA_ARGS__); \\r |
| a8fd6e37 |
842 | } while (0)\r |
| dca310c4 |
843 | #elif defined(_MSC_VER)\r |
| 844 | #define elprintf\r |
| b8cbd802 |
845 | #else\r |
| 846 | #define elprintf(w,f,...)\r |
| 847 | #endif\r |
| 848 | \r |
| f6c49d38 |
849 | // profiling\r |
| 850 | #ifdef PPROF\r |
| 851 | #include <platform/linux/pprof.h>\r |
| 852 | #else\r |
| 853 | #define pprof_init()\r |
| 854 | #define pprof_finish()\r |
| 855 | #define pprof_start(x)\r |
| 856 | #define pprof_end(...)\r |
| 857 | #define pprof_end_sub(...)\r |
| 858 | #endif\r |
| 859 | \r |
| 19886062 |
860 | #ifdef EVT_LOG\r |
| 861 | enum evt {\r |
| 862 | EVT_FRAME_START,\r |
| 863 | EVT_NEXT_LINE,\r |
| 864 | EVT_RUN_START,\r |
| 865 | EVT_RUN_END,\r |
| 866 | EVT_POLL_START,\r |
| 867 | EVT_POLL_END,\r |
| 868 | EVT_CNT\r |
| 869 | };\r |
| 870 | \r |
| 871 | enum evt_cpu {\r |
| 872 | EVT_M68K,\r |
| 873 | EVT_S68K,\r |
| 874 | EVT_MSH2,\r |
| 875 | EVT_SSH2,\r |
| 876 | EVT_CPU_CNT\r |
| 877 | };\r |
| 878 | \r |
| 879 | void pevt_log(unsigned int cycles, enum evt_cpu c, enum evt e);\r |
| 880 | void pevt_dump(void);\r |
| 881 | \r |
| 882 | #define pevt_log_m68k(e) \\r |
| 883 | pevt_log(SekCyclesDoneT(), EVT_M68K, e)\r |
| 884 | #define pevt_log_m68k_o(e) \\r |
| 885 | pevt_log(SekCyclesDoneT2(), EVT_M68K, e)\r |
| 886 | #define pevt_log_sh2(sh2, e) \\r |
| 887 | pevt_log(sh2_cycles_done_m68k(sh2), EVT_MSH2 + (sh2)->is_slave, e)\r |
| 888 | #define pevt_log_sh2_o(sh2, e) \\r |
| 889 | pevt_log((sh2)->m68krcycles_done, EVT_MSH2 + (sh2)->is_slave, e)\r |
| 890 | #else\r |
| 891 | #define pevt_log(c, e)\r |
| 892 | #define pevt_log_m68k(e)\r |
| 893 | #define pevt_log_m68k_o(e)\r |
| 894 | #define pevt_log_sh2(sh2, e)\r |
| 895 | #define pevt_log_sh2_o(sh2, e)\r |
| 896 | #define pevt_dump()\r |
| 897 | #endif\r |
| 898 | \r |
| f6c49d38 |
899 | // misc\r |
| dca310c4 |
900 | #ifdef _MSC_VER\r |
| 901 | #define cdprintf\r |
| 902 | #else\r |
| 903 | #define cdprintf(x...)\r |
| 904 | #endif\r |
| 905 | \r |
| 553c3eaa |
906 | #ifdef __i386__\r |
| 907 | #define REGPARM(x) __attribute__((regparm(x)))\r |
| c8d1e9b6 |
908 | #else\r |
| 553c3eaa |
909 | #define REGPARM(x)\r |
| c8d1e9b6 |
910 | #endif\r |
| 911 | \r |
| 5e89f0f5 |
912 | #ifdef __GNUC__\r |
| 913 | #define NOINLINE __attribute__((noinline))\r |
| 914 | #else\r |
| 915 | #define NOINLINE\r |
| 916 | #endif\r |
| 917 | \r |
| f8af9634 |
918 | #ifdef __cplusplus\r |
| 919 | } // End of extern "C"\r |
| 920 | #endif\r |
| 921 | \r |
| eff55556 |
922 | #endif // PICO_INTERNAL_INCLUDED\r |
| 923 | \r |
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