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drc: align size passed to mprotect
[pcsx_rearmed.git] / libpcsxcore / new_dynarec / new_dynarec.c
CommitLineData
57871462 1/* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
2 * Mupen64plus - new_dynarec.c *
20d507ba 3 * Copyright (C) 2009-2011 Ari64 *
57871462 4 * *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
9 * *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
14 * *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. *
19 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */
20
21#include <stdlib.h>
22#include <stdint.h> //include for uint64_t
23#include <assert.h>
d848b60a 24#include <errno.h>
4600ba03 25#include <sys/mman.h>
d148d265 26#ifdef __MACH__
27#include <libkern/OSCacheControl.h>
28#endif
1e212a25 29#ifdef _3DS
30#include <3ds_utils.h>
31#endif
32#ifdef VITA
33#include <psp2/kernel/sysmem.h>
34static int sceBlock;
35#endif
57871462 36
d148d265 37#include "new_dynarec_config.h"
3968e69e 38#include "../psxhle.h"
39#include "../psxinterpreter.h"
81dbbf4c 40#include "../gte.h"
41#include "emu_if.h" // emulator interface
57871462 42
d1e4ebd9 43#define noinline __attribute__((noinline,noclone))
b14b6a8f 44#ifndef ARRAY_SIZE
45#define ARRAY_SIZE(x) (sizeof(x) / sizeof(x[0]))
46#endif
e3c6bdb5 47#ifndef min
48#define min(a, b) ((b) < (a) ? (b) : (a))
49#endif
32631e6a 50#ifndef max
51#define max(a, b) ((b) > (a) ? (b) : (a))
52#endif
b14b6a8f 53
4600ba03 54//#define DISASM
32631e6a 55//#define ASSEM_PRINT
56
57#ifdef ASSEM_PRINT
58#define assem_debug printf
59#else
4600ba03 60#define assem_debug(...)
32631e6a 61#endif
62//#define inv_debug printf
4600ba03 63#define inv_debug(...)
57871462 64
65#ifdef __i386__
66#include "assem_x86.h"
67#endif
68#ifdef __x86_64__
69#include "assem_x64.h"
70#endif
71#ifdef __arm__
72#include "assem_arm.h"
73#endif
be516ebe 74#ifdef __aarch64__
75#include "assem_arm64.h"
76#endif
57871462 77
81dbbf4c 78#define RAM_SIZE 0x200000
57871462 79#define MAXBLOCK 4096
80#define MAX_OUTPUT_BLOCK_SIZE 262144
2573466a 81
2a014d73 82struct ndrc_mem
83{
84 u_char translation_cache[1 << TARGET_SIZE_2];
85 struct
86 {
87 struct tramp_insns ops[2048 / sizeof(struct tramp_insns)];
88 const void *f[2048 / sizeof(void *)];
89 } tramp;
90};
91
92#ifdef BASE_ADDR_DYNAMIC
93static struct ndrc_mem *ndrc;
94#else
95static struct ndrc_mem ndrc_ __attribute__((aligned(4096)));
96static struct ndrc_mem *ndrc = &ndrc_;
97#endif
98
b14b6a8f 99// stubs
100enum stub_type {
101 CC_STUB = 1,
102 FP_STUB = 2,
103 LOADB_STUB = 3,
104 LOADH_STUB = 4,
105 LOADW_STUB = 5,
106 LOADD_STUB = 6,
107 LOADBU_STUB = 7,
108 LOADHU_STUB = 8,
109 STOREB_STUB = 9,
110 STOREH_STUB = 10,
111 STOREW_STUB = 11,
112 STORED_STUB = 12,
113 STORELR_STUB = 13,
114 INVCODE_STUB = 14,
115};
116
57871462 117struct regstat
118{
2330734f 119 signed char regmap_entry[HOST_REGS]; // pre-insn + loop preloaded regs?
57871462 120 signed char regmap[HOST_REGS];
57871462 121 uint64_t wasdirty;
122 uint64_t dirty;
123 uint64_t u;
24058131 124 u_int wasconst; // before; for example 'lw r2, (r2)' wasconst is true
125 u_int isconst; // ... but isconst is false when r2 is known
8575a877 126 u_int loadedconst; // host regs that have constants loaded
127 u_int waswritten; // MIPS regs that were used as store base before
57871462 128};
129
de5a60c3 130// note: asm depends on this layout
57871462 131struct ll_entry
132{
133 u_int vaddr;
de5a60c3 134 u_int reg_sv_flags;
57871462 135 void *addr;
136 struct ll_entry *next;
137};
138
df4dc2b1 139struct ht_entry
140{
141 u_int vaddr[2];
142 void *tcaddr[2];
143};
144
b14b6a8f 145struct code_stub
146{
147 enum stub_type type;
148 void *addr;
149 void *retaddr;
150 u_int a;
151 uintptr_t b;
152 uintptr_t c;
153 u_int d;
154 u_int e;
155};
156
643aeae3 157struct link_entry
158{
159 void *addr;
160 u_int target;
161 u_int ext;
162};
163
cf95b4f0 164static struct decoded_insn
165{
166 u_char itype;
167 u_char opcode;
168 u_char opcode2;
169 u_char rs1;
170 u_char rs2;
171 u_char rt1;
172 u_char rt2;
173 u_char lt1;
174 u_char bt:1;
cf95b4f0 175 u_char ooo:1;
176 u_char is_ds:1;
fe807a8a 177 u_char is_jump:1;
178 u_char is_ujump:1;
37387d8b 179 u_char is_load:1;
180 u_char is_store:1;
cf95b4f0 181} dops[MAXBLOCK];
182
e2b5e7aa 183 // used by asm:
184 u_char *out;
df4dc2b1 185 struct ht_entry hash_table[65536] __attribute__((aligned(16)));
e2b5e7aa 186 struct ll_entry *jump_in[4096] __attribute__((aligned(16)));
187 struct ll_entry *jump_dirty[4096];
188
189 static struct ll_entry *jump_out[4096];
190 static u_int start;
191 static u_int *source;
192 static char insn[MAXBLOCK][10];
bedfea38 193 static uint64_t gte_rs[MAXBLOCK]; // gte: 32 data and 32 ctl regs
194 static uint64_t gte_rt[MAXBLOCK];
195 static uint64_t gte_unneeded[MAXBLOCK];
ffb0b9e0 196 static u_int smrv[32]; // speculated MIPS register values
197 static u_int smrv_strong; // mask or regs that are likely to have correct values
198 static u_int smrv_weak; // same, but somewhat less likely
199 static u_int smrv_strong_next; // same, but after current insn executes
200 static u_int smrv_weak_next;
e2b5e7aa 201 static int imm[MAXBLOCK];
202 static u_int ba[MAXBLOCK];
e2b5e7aa 203 static uint64_t unneeded_reg[MAXBLOCK];
e2b5e7aa 204 static uint64_t branch_unneeded_reg[MAXBLOCK];
2330734f 205 // pre-instruction [i], excluding loop-preload regs?
206 static signed char regmap_pre[MAXBLOCK][HOST_REGS];
40fca85b 207 // contains 'real' consts at [i] insn, but may differ from what's actually
208 // loaded in host reg as 'final' value is always loaded, see get_final_value()
209 static uint32_t current_constmap[HOST_REGS];
210 static uint32_t constmap[MAXBLOCK][HOST_REGS];
956f3129 211 static struct regstat regs[MAXBLOCK];
212 static struct regstat branch_regs[MAXBLOCK];
e2b5e7aa 213 static signed char minimum_free_regs[MAXBLOCK];
214 static u_int needed_reg[MAXBLOCK];
215 static u_int wont_dirty[MAXBLOCK];
216 static u_int will_dirty[MAXBLOCK];
217 static int ccadj[MAXBLOCK];
218 static int slen;
df4dc2b1 219 static void *instr_addr[MAXBLOCK];
643aeae3 220 static struct link_entry link_addr[MAXBLOCK];
e2b5e7aa 221 static int linkcount;
b14b6a8f 222 static struct code_stub stubs[MAXBLOCK*3];
e2b5e7aa 223 static int stubcount;
224 static u_int literals[1024][2];
225 static int literalcount;
226 static int is_delayslot;
e2b5e7aa 227 static char shadow[1048576] __attribute__((aligned(16)));
228 static void *copy;
229 static int expirep;
230 static u_int stop_after_jal;
39b71d9a 231 static u_int f1_hack; // 0 - off, ~0 - capture address, else addr
e2b5e7aa 232
233 int new_dynarec_hacks;
d62c125a 234 int new_dynarec_hacks_pergame;
32631e6a 235 int new_dynarec_hacks_old;
e2b5e7aa 236 int new_dynarec_did_compile;
687b4580 237
d62c125a 238 #define HACK_ENABLED(x) ((new_dynarec_hacks | new_dynarec_hacks_pergame) & (x))
239
687b4580 240 extern int cycle_count; // ... until end of the timeslice, counts -N -> 0
241 extern int last_count; // last absolute target, often = next_interupt
242 extern int pcaddr;
243 extern int pending_exception;
244 extern int branch_target;
37387d8b 245 extern uintptr_t ram_offset;
d1e4ebd9 246 extern uintptr_t mini_ht[32][2];
57871462 247 extern u_char restore_candidate[512];
57871462 248
249 /* registers that may be allocated */
250 /* 1-31 gpr */
7c3a5182 251#define LOREG 32 // lo
252#define HIREG 33 // hi
00fa9369 253//#define FSREG 34 // FPU status (FCSR)
57871462 254#define CSREG 35 // Coprocessor status
255#define CCREG 36 // Cycle count
256#define INVCP 37 // Pointer to invalid_code
1edfcc68 257//#define MMREG 38 // Pointer to memory_map
37387d8b 258#define ROREG 39 // ram offset (if rdram!=0x80000000)
619e5ded 259#define TEMPREG 40
260#define FTEMP 40 // FPU temporary register
261#define PTEMP 41 // Prefetch temporary register
1edfcc68 262//#define TLREG 42 // TLB mapping offset
619e5ded 263#define RHASH 43 // Return address hash
264#define RHTBL 44 // Return address hash table address
265#define RTEMP 45 // JR/JALR address register
266#define MAXREG 45
267#define AGEN1 46 // Address generation temporary register
1edfcc68 268//#define AGEN2 47 // Address generation temporary register
269//#define MGEN1 48 // Maptable address generation temporary register
270//#define MGEN2 49 // Maptable address generation temporary register
619e5ded 271#define BTREG 50 // Branch target temporary register
57871462 272
273 /* instruction types */
274#define NOP 0 // No operation
275#define LOAD 1 // Load
276#define STORE 2 // Store
277#define LOADLR 3 // Unaligned load
278#define STORELR 4 // Unaligned store
9f51b4b9 279#define MOV 5 // Move
57871462 280#define ALU 6 // Arithmetic/logic
281#define MULTDIV 7 // Multiply/divide
282#define SHIFT 8 // Shift by register
283#define SHIFTIMM 9// Shift by immediate
284#define IMM16 10 // 16-bit immediate
285#define RJUMP 11 // Unconditional jump to register
286#define UJUMP 12 // Unconditional jump
287#define CJUMP 13 // Conditional branch (BEQ/BNE/BGTZ/BLEZ)
288#define SJUMP 14 // Conditional branch (regimm format)
289#define COP0 15 // Coprocessor 0
290#define COP1 16 // Coprocessor 1
291#define C1LS 17 // Coprocessor 1 load/store
ad49de89 292//#define FJUMP 18 // Conditional branch (floating point)
00fa9369 293//#define FLOAT 19 // Floating point unit
294//#define FCONV 20 // Convert integer to float
295//#define FCOMP 21 // Floating point compare (sets FSREG)
57871462 296#define SYSCALL 22// SYSCALL
297#define OTHER 23 // Other
298#define SPAN 24 // Branch/delay slot spans 2 pages
299#define NI 25 // Not implemented
7139f3c8 300#define HLECALL 26// PCSX fake opcodes for HLE
b9b61529 301#define COP2 27 // Coprocessor 2 move
302#define C2LS 28 // Coprocessor 2 load/store
303#define C2OP 29 // Coprocessor 2 operation
1e973cb0 304#define INTCALL 30// Call interpreter to handle rare corner cases
57871462 305
57871462 306 /* branch codes */
307#define TAKEN 1
308#define NOTTAKEN 2
309#define NULLDS 3
310
7c3a5182 311#define DJT_1 (void *)1l // no function, just a label in assem_debug log
312#define DJT_2 (void *)2l
313
57871462 314// asm linkage
3968e69e 315int new_recompile_block(u_int addr);
57871462 316void *get_addr_ht(u_int vaddr);
317void invalidate_block(u_int block);
318void invalidate_addr(u_int addr);
319void remove_hash(int vaddr);
57871462 320void dyna_linker();
321void dyna_linker_ds();
322void verify_code();
57871462 323void verify_code_ds();
324void cc_interrupt();
325void fp_exception();
326void fp_exception_ds();
3968e69e 327void jump_to_new_pc();
81dbbf4c 328void call_gteStall();
7139f3c8 329void new_dyna_leave();
57871462 330
57871462 331// Needed by assembler
2330734f 332static void wb_register(signed char r, const signed char regmap[], uint64_t dirty);
333static void wb_dirtys(const signed char i_regmap[], uint64_t i_dirty);
334static void wb_needed_dirtys(const signed char i_regmap[], uint64_t i_dirty, int addr);
335static void load_all_regs(const signed char i_regmap[]);
336static void load_needed_regs(const signed char i_regmap[], const signed char next_regmap[]);
e2b5e7aa 337static void load_regs_entry(int t);
2330734f 338static void load_all_consts(const signed char regmap[], u_int dirty, int i);
81dbbf4c 339static u_int get_host_reglist(const signed char *regmap);
e2b5e7aa 340
3968e69e 341static int verify_dirty(const u_int *ptr);
e2b5e7aa 342static int get_final_value(int hr, int i, int *value);
b14b6a8f 343static void add_stub(enum stub_type type, void *addr, void *retaddr,
344 u_int a, uintptr_t b, uintptr_t c, u_int d, u_int e);
345static void add_stub_r(enum stub_type type, void *addr, void *retaddr,
81dbbf4c 346 int i, int addr_reg, const struct regstat *i_regs, int ccadj, u_int reglist);
643aeae3 347static void add_to_linker(void *addr, u_int target, int ext);
37387d8b 348static void *emit_fastpath_cmp_jump(int i, const struct regstat *i_regs,
349 int addr, int *offset_reg, int *addr_reg_override);
687b4580 350static void *get_direct_memhandler(void *table, u_int addr,
351 enum stub_type type, uintptr_t *addr_host);
32631e6a 352static void cop2_do_stall_check(u_int op, int i, const struct regstat *i_regs, u_int reglist);
687b4580 353static void pass_args(int a0, int a1);
2a014d73 354static void emit_far_jump(const void *f);
355static void emit_far_call(const void *f);
57871462 356
d148d265 357static void mprotect_w_x(void *start, void *end, int is_x)
358{
359#ifdef NO_WRITE_EXEC
1e212a25 360 #if defined(VITA)
361 // *Open* enables write on all memory that was
362 // allocated by sceKernelAllocMemBlockForVM()?
363 if (is_x)
364 sceKernelCloseVMDomain();
365 else
366 sceKernelOpenVMDomain();
367 #else
d148d265 368 u_long mstart = (u_long)start & ~4095ul;
369 u_long mend = (u_long)end;
370 if (mprotect((void *)mstart, mend - mstart,
371 PROT_READ | (is_x ? PROT_EXEC : PROT_WRITE)) != 0)
372 SysPrintf("mprotect(%c) failed: %s\n", is_x ? 'x' : 'w', strerror(errno));
1e212a25 373 #endif
d148d265 374#endif
375}
376
377static void start_tcache_write(void *start, void *end)
378{
379 mprotect_w_x(start, end, 0);
380}
381
382static void end_tcache_write(void *start, void *end)
383{
919981d0 384#if defined(__arm__) || defined(__aarch64__)
d148d265 385 size_t len = (char *)end - (char *)start;
386 #if defined(__BLACKBERRY_QNX__)
387 msync(start, len, MS_SYNC | MS_CACHE_ONLY | MS_INVALIDATE_ICACHE);
388 #elif defined(__MACH__)
389 sys_cache_control(kCacheFunctionPrepareForExecution, start, len);
390 #elif defined(VITA)
1e212a25 391 sceKernelSyncVMDomain(sceBlock, start, len);
392 #elif defined(_3DS)
393 ctr_flush_invalidate_cache();
919981d0 394 #elif defined(__aarch64__)
395 // as of 2021, __clear_cache() is still broken on arm64
396 // so here is a custom one :(
397 clear_cache_arm64(start, end);
d148d265 398 #else
399 __clear_cache(start, end);
400 #endif
401 (void)len;
402#endif
403
404 mprotect_w_x(start, end, 1);
405}
406
407static void *start_block(void)
408{
409 u_char *end = out + MAX_OUTPUT_BLOCK_SIZE;
2a014d73 410 if (end > ndrc->translation_cache + sizeof(ndrc->translation_cache))
411 end = ndrc->translation_cache + sizeof(ndrc->translation_cache);
d148d265 412 start_tcache_write(out, end);
413 return out;
414}
415
416static void end_block(void *start)
417{
418 end_tcache_write(start, out);
419}
420
919981d0 421// also takes care of w^x mappings when patching code
422static u_int needs_clear_cache[1<<(TARGET_SIZE_2-17)];
423
424static void mark_clear_cache(void *target)
425{
426 uintptr_t offset = (u_char *)target - ndrc->translation_cache;
427 u_int mask = 1u << ((offset >> 12) & 31);
428 if (!(needs_clear_cache[offset >> 17] & mask)) {
429 char *start = (char *)((uintptr_t)target & ~4095l);
430 start_tcache_write(start, start + 4095);
431 needs_clear_cache[offset >> 17] |= mask;
432 }
433}
434
435// Clearing the cache is rather slow on ARM Linux, so mark the areas
436// that need to be cleared, and then only clear these areas once.
437static void do_clear_cache(void)
438{
439 int i, j;
440 for (i = 0; i < (1<<(TARGET_SIZE_2-17)); i++)
441 {
442 u_int bitmap = needs_clear_cache[i];
443 if (!bitmap)
444 continue;
445 for (j = 0; j < 32; j++)
446 {
447 u_char *start, *end;
448 if (!(bitmap & (1<<j)))
449 continue;
450
451 start = ndrc->translation_cache + i*131072 + j*4096;
452 end = start + 4095;
453 for (j++; j < 32; j++) {
454 if (!(bitmap & (1<<j)))
455 break;
456 end += 4096;
457 }
458 end_tcache_write(start, end);
459 }
460 needs_clear_cache[i] = 0;
461 }
462}
463
57871462 464//#define DEBUG_CYCLE_COUNT 1
465
b6e87b2b 466#define NO_CYCLE_PENALTY_THR 12
467
26bd3dad 468int cycle_multiplier = CYCLE_MULT_DEFAULT; // 100 for 1.0
a3203cf4 469int cycle_multiplier_override;
32631e6a 470int cycle_multiplier_old;
24058131 471static int cycle_multiplier_active;
4e9dcd7f 472
473static int CLOCK_ADJUST(int x)
474{
24058131 475 int m = cycle_multiplier_active;
476 int s = (x >> 31) | 1;
a3203cf4 477 return (x * m + s * 50) / 100;
4e9dcd7f 478}
479
4919de1e 480static int ds_writes_rjump_rs(int i)
481{
cf95b4f0 482 return dops[i].rs1 != 0 && (dops[i].rs1 == dops[i+1].rt1 || dops[i].rs1 == dops[i+1].rt2);
4919de1e 483}
484
94d23bb9 485static u_int get_page(u_int vaddr)
57871462 486{
0ce47d46 487 u_int page=vaddr&~0xe0000000;
488 if (page < 0x1000000)
489 page &= ~0x0e00000; // RAM mirrors
490 page>>=12;
57871462 491 if(page>2048) page=2048+(page&2047);
94d23bb9 492 return page;
493}
494
d25604ca 495// no virtual mem in PCSX
496static u_int get_vpage(u_int vaddr)
497{
498 return get_page(vaddr);
499}
94d23bb9 500
df4dc2b1 501static struct ht_entry *hash_table_get(u_int vaddr)
502{
503 return &hash_table[((vaddr>>16)^vaddr)&0xFFFF];
504}
505
506static void hash_table_add(struct ht_entry *ht_bin, u_int vaddr, void *tcaddr)
507{
508 ht_bin->vaddr[1] = ht_bin->vaddr[0];
509 ht_bin->tcaddr[1] = ht_bin->tcaddr[0];
510 ht_bin->vaddr[0] = vaddr;
511 ht_bin->tcaddr[0] = tcaddr;
512}
513
514// some messy ari64's code, seems to rely on unsigned 32bit overflow
515static int doesnt_expire_soon(void *tcaddr)
516{
517 u_int diff = (u_int)((u_char *)tcaddr - out) << (32-TARGET_SIZE_2);
518 return diff > (u_int)(0x60000000 + (MAX_OUTPUT_BLOCK_SIZE << (32-TARGET_SIZE_2)));
519}
520
94d23bb9 521// Get address from virtual address
522// This is called from the recompiled JR/JALR instructions
d1e4ebd9 523void noinline *get_addr(u_int vaddr)
94d23bb9 524{
525 u_int page=get_page(vaddr);
526 u_int vpage=get_vpage(vaddr);
57871462 527 struct ll_entry *head;
528 //printf("TRACE: count=%d next=%d (get_addr %x,page %d)\n",Count,next_interupt,vaddr,page);
529 head=jump_in[page];
530 while(head!=NULL) {
de5a60c3 531 if(head->vaddr==vaddr) {
643aeae3 532 //printf("TRACE: count=%d next=%d (get_addr match %x: %p)\n",Count,next_interupt,vaddr,head->addr);
df4dc2b1 533 hash_table_add(hash_table_get(vaddr), vaddr, head->addr);
57871462 534 return head->addr;
535 }
536 head=head->next;
537 }
538 head=jump_dirty[vpage];
539 while(head!=NULL) {
de5a60c3 540 if(head->vaddr==vaddr) {
643aeae3 541 //printf("TRACE: count=%d next=%d (get_addr match dirty %x: %p)\n",Count,next_interupt,vaddr,head->addr);
57871462 542 // Don't restore blocks which are about to expire from the cache
df4dc2b1 543 if (doesnt_expire_soon(head->addr))
544 if (verify_dirty(head->addr)) {
57871462 545 //printf("restore candidate: %x (%d) d=%d\n",vaddr,page,invalid_code[vaddr>>12]);
546 invalid_code[vaddr>>12]=0;
9be4ba64 547 inv_code_start=inv_code_end=~0;
57871462 548 if(vpage<2048) {
57871462 549 restore_candidate[vpage>>3]|=1<<(vpage&7);
550 }
551 else restore_candidate[page>>3]|=1<<(page&7);
df4dc2b1 552 struct ht_entry *ht_bin = hash_table_get(vaddr);
553 if (ht_bin->vaddr[0] == vaddr)
554 ht_bin->tcaddr[0] = head->addr; // Replace existing entry
57871462 555 else
df4dc2b1 556 hash_table_add(ht_bin, vaddr, head->addr);
557
57871462 558 return head->addr;
559 }
560 }
561 head=head->next;
562 }
563 //printf("TRACE: count=%d next=%d (get_addr no-match %x)\n",Count,next_interupt,vaddr);
564 int r=new_recompile_block(vaddr);
565 if(r==0) return get_addr(vaddr);
566 // Execute in unmapped page, generate pagefault execption
567 Status|=2;
568 Cause=(vaddr<<31)|0x8;
569 EPC=(vaddr&1)?vaddr-5:vaddr;
570 BadVAddr=(vaddr&~1);
571 Context=(Context&0xFF80000F)|((BadVAddr>>9)&0x007FFFF0);
572 EntryHi=BadVAddr&0xFFFFE000;
573 return get_addr_ht(0x80000000);
574}
575// Look up address in hash table first
576void *get_addr_ht(u_int vaddr)
577{
578 //printf("TRACE: count=%d next=%d (get_addr_ht %x)\n",Count,next_interupt,vaddr);
df4dc2b1 579 const struct ht_entry *ht_bin = hash_table_get(vaddr);
580 if (ht_bin->vaddr[0] == vaddr) return ht_bin->tcaddr[0];
581 if (ht_bin->vaddr[1] == vaddr) return ht_bin->tcaddr[1];
57871462 582 return get_addr(vaddr);
583}
584
57871462 585void clear_all_regs(signed char regmap[])
586{
587 int hr;
588 for (hr=0;hr<HOST_REGS;hr++) regmap[hr]=-1;
589}
590
d1e4ebd9 591static signed char get_reg(const signed char regmap[],int r)
57871462 592{
593 int hr;
594 for (hr=0;hr<HOST_REGS;hr++) if(hr!=EXCLUDE_REG&&regmap[hr]==r) return hr;
595 return -1;
596}
597
598// Find a register that is available for two consecutive cycles
d1e4ebd9 599static signed char get_reg2(signed char regmap1[], const signed char regmap2[], int r)
57871462 600{
601 int hr;
602 for (hr=0;hr<HOST_REGS;hr++) if(hr!=EXCLUDE_REG&&regmap1[hr]==r&&regmap2[hr]==r) return hr;
603 return -1;
604}
605
606int count_free_regs(signed char regmap[])
607{
608 int count=0;
609 int hr;
610 for(hr=0;hr<HOST_REGS;hr++)
611 {
612 if(hr!=EXCLUDE_REG) {
613 if(regmap[hr]<0) count++;
614 }
615 }
616 return count;
617}
618
619void dirty_reg(struct regstat *cur,signed char reg)
620{
621 int hr;
622 if(!reg) return;
623 for (hr=0;hr<HOST_REGS;hr++) {
624 if((cur->regmap[hr]&63)==reg) {
625 cur->dirty|=1<<hr;
626 }
627 }
628}
629
40fca85b 630static void set_const(struct regstat *cur, signed char reg, uint32_t value)
57871462 631{
632 int hr;
633 if(!reg) return;
634 for (hr=0;hr<HOST_REGS;hr++) {
635 if(cur->regmap[hr]==reg) {
636 cur->isconst|=1<<hr;
956f3129 637 current_constmap[hr]=value;
57871462 638 }
57871462 639 }
640}
641
40fca85b 642static void clear_const(struct regstat *cur, signed char reg)
57871462 643{
644 int hr;
645 if(!reg) return;
646 for (hr=0;hr<HOST_REGS;hr++) {
647 if((cur->regmap[hr]&63)==reg) {
648 cur->isconst&=~(1<<hr);
649 }
650 }
651}
652
40fca85b 653static int is_const(struct regstat *cur, signed char reg)
57871462 654{
655 int hr;
79c75f1b 656 if(reg<0) return 0;
57871462 657 if(!reg) return 1;
658 for (hr=0;hr<HOST_REGS;hr++) {
659 if((cur->regmap[hr]&63)==reg) {
660 return (cur->isconst>>hr)&1;
661 }
662 }
663 return 0;
664}
40fca85b 665
666static uint32_t get_const(struct regstat *cur, signed char reg)
57871462 667{
668 int hr;
669 if(!reg) return 0;
670 for (hr=0;hr<HOST_REGS;hr++) {
671 if(cur->regmap[hr]==reg) {
956f3129 672 return current_constmap[hr];
57871462 673 }
674 }
c43b5311 675 SysPrintf("Unknown constant in r%d\n",reg);
7c3a5182 676 abort();
57871462 677}
678
679// Least soon needed registers
680// Look at the next ten instructions and see which registers
681// will be used. Try not to reallocate these.
682void lsn(u_char hsn[], int i, int *preferred_reg)
683{
684 int j;
685 int b=-1;
686 for(j=0;j<9;j++)
687 {
688 if(i+j>=slen) {
689 j=slen-i-1;
690 break;
691 }
fe807a8a 692 if (dops[i+j].is_ujump)
57871462 693 {
694 // Don't go past an unconditonal jump
695 j++;
696 break;
697 }
698 }
699 for(;j>=0;j--)
700 {
cf95b4f0 701 if(dops[i+j].rs1) hsn[dops[i+j].rs1]=j;
702 if(dops[i+j].rs2) hsn[dops[i+j].rs2]=j;
703 if(dops[i+j].rt1) hsn[dops[i+j].rt1]=j;
704 if(dops[i+j].rt2) hsn[dops[i+j].rt2]=j;
705 if(dops[i+j].itype==STORE || dops[i+j].itype==STORELR) {
57871462 706 // Stores can allocate zero
cf95b4f0 707 hsn[dops[i+j].rs1]=j;
708 hsn[dops[i+j].rs2]=j;
57871462 709 }
37387d8b 710 if (ram_offset && (dops[i+j].is_load || dops[i+j].is_store))
711 hsn[ROREG] = j;
57871462 712 // On some architectures stores need invc_ptr
713 #if defined(HOST_IMM8)
37387d8b 714 if (dops[i+j].is_store)
715 hsn[INVCP] = j;
57871462 716 #endif
cf95b4f0 717 if(i+j>=0&&(dops[i+j].itype==UJUMP||dops[i+j].itype==CJUMP||dops[i+j].itype==SJUMP))
57871462 718 {
719 hsn[CCREG]=j;
720 b=j;
721 }
722 }
723 if(b>=0)
724 {
725 if(ba[i+b]>=start && ba[i+b]<(start+slen*4))
726 {
727 // Follow first branch
728 int t=(ba[i+b]-start)>>2;
729 j=7-b;if(t+j>=slen) j=slen-t-1;
730 for(;j>=0;j--)
731 {
cf95b4f0 732 if(dops[t+j].rs1) if(hsn[dops[t+j].rs1]>j+b+2) hsn[dops[t+j].rs1]=j+b+2;
733 if(dops[t+j].rs2) if(hsn[dops[t+j].rs2]>j+b+2) hsn[dops[t+j].rs2]=j+b+2;
734 //if(dops[t+j].rt1) if(hsn[dops[t+j].rt1]>j+b+2) hsn[dops[t+j].rt1]=j+b+2;
735 //if(dops[t+j].rt2) if(hsn[dops[t+j].rt2]>j+b+2) hsn[dops[t+j].rt2]=j+b+2;
57871462 736 }
737 }
738 // TODO: preferred register based on backward branch
739 }
740 // Delay slot should preferably not overwrite branch conditions or cycle count
fe807a8a 741 if (i > 0 && dops[i-1].is_jump) {
cf95b4f0 742 if(dops[i-1].rs1) if(hsn[dops[i-1].rs1]>1) hsn[dops[i-1].rs1]=1;
743 if(dops[i-1].rs2) if(hsn[dops[i-1].rs2]>1) hsn[dops[i-1].rs2]=1;
57871462 744 hsn[CCREG]=1;
745 // ...or hash tables
746 hsn[RHASH]=1;
747 hsn[RHTBL]=1;
748 }
749 // Coprocessor load/store needs FTEMP, even if not declared
37387d8b 750 if(dops[i].itype==C2LS) {
57871462 751 hsn[FTEMP]=0;
752 }
753 // Load L/R also uses FTEMP as a temporary register
cf95b4f0 754 if(dops[i].itype==LOADLR) {
57871462 755 hsn[FTEMP]=0;
756 }
b7918751 757 // Also SWL/SWR/SDL/SDR
cf95b4f0 758 if(dops[i].opcode==0x2a||dops[i].opcode==0x2e||dops[i].opcode==0x2c||dops[i].opcode==0x2d) {
57871462 759 hsn[FTEMP]=0;
760 }
57871462 761 // Don't remove the miniht registers
cf95b4f0 762 if(dops[i].itype==UJUMP||dops[i].itype==RJUMP)
57871462 763 {
764 hsn[RHASH]=0;
765 hsn[RHTBL]=0;
766 }
767}
768
769// We only want to allocate registers if we're going to use them again soon
770int needed_again(int r, int i)
771{
772 int j;
773 int b=-1;
774 int rn=10;
9f51b4b9 775
fe807a8a 776 if (i > 0 && dops[i-1].is_ujump)
57871462 777 {
778 if(ba[i-1]<start || ba[i-1]>start+slen*4-4)
779 return 0; // Don't need any registers if exiting the block
780 }
781 for(j=0;j<9;j++)
782 {
783 if(i+j>=slen) {
784 j=slen-i-1;
785 break;
786 }
fe807a8a 787 if (dops[i+j].is_ujump)
57871462 788 {
789 // Don't go past an unconditonal jump
790 j++;
791 break;
792 }
cf95b4f0 793 if(dops[i+j].itype==SYSCALL||dops[i+j].itype==HLECALL||dops[i+j].itype==INTCALL||((source[i+j]&0xfc00003f)==0x0d))
57871462 794 {
795 break;
796 }
797 }
798 for(;j>=1;j--)
799 {
cf95b4f0 800 if(dops[i+j].rs1==r) rn=j;
801 if(dops[i+j].rs2==r) rn=j;
57871462 802 if((unneeded_reg[i+j]>>r)&1) rn=10;
cf95b4f0 803 if(i+j>=0&&(dops[i+j].itype==UJUMP||dops[i+j].itype==CJUMP||dops[i+j].itype==SJUMP))
57871462 804 {
805 b=j;
806 }
807 }
b7217e13 808 if(rn<10) return 1;
581335b0 809 (void)b;
57871462 810 return 0;
811}
812
813// Try to match register allocations at the end of a loop with those
814// at the beginning
815int loop_reg(int i, int r, int hr)
816{
817 int j,k;
818 for(j=0;j<9;j++)
819 {
820 if(i+j>=slen) {
821 j=slen-i-1;
822 break;
823 }
fe807a8a 824 if (dops[i+j].is_ujump)
57871462 825 {
826 // Don't go past an unconditonal jump
827 j++;
828 break;
829 }
830 }
831 k=0;
832 if(i>0){
cf95b4f0 833 if(dops[i-1].itype==UJUMP||dops[i-1].itype==CJUMP||dops[i-1].itype==SJUMP)
57871462 834 k--;
835 }
836 for(;k<j;k++)
837 {
00fa9369 838 assert(r < 64);
839 if((unneeded_reg[i+k]>>r)&1) return hr;
cf95b4f0 840 if(i+k>=0&&(dops[i+k].itype==UJUMP||dops[i+k].itype==CJUMP||dops[i+k].itype==SJUMP))
57871462 841 {
842 if(ba[i+k]>=start && ba[i+k]<(start+i*4))
843 {
844 int t=(ba[i+k]-start)>>2;
845 int reg=get_reg(regs[t].regmap_entry,r);
846 if(reg>=0) return reg;
847 //reg=get_reg(regs[t+1].regmap_entry,r);
848 //if(reg>=0) return reg;
849 }
850 }
851 }
852 return hr;
853}
854
855
856// Allocate every register, preserving source/target regs
857void alloc_all(struct regstat *cur,int i)
858{
859 int hr;
9f51b4b9 860
57871462 861 for(hr=0;hr<HOST_REGS;hr++) {
862 if(hr!=EXCLUDE_REG) {
cf95b4f0 863 if(((cur->regmap[hr]&63)!=dops[i].rs1)&&((cur->regmap[hr]&63)!=dops[i].rs2)&&
864 ((cur->regmap[hr]&63)!=dops[i].rt1)&&((cur->regmap[hr]&63)!=dops[i].rt2))
57871462 865 {
866 cur->regmap[hr]=-1;
867 cur->dirty&=~(1<<hr);
868 }
869 // Don't need zeros
870 if((cur->regmap[hr]&63)==0)
871 {
872 cur->regmap[hr]=-1;
873 cur->dirty&=~(1<<hr);
874 }
875 }
876 }
877}
878
d1e4ebd9 879#ifndef NDEBUG
880static int host_tempreg_in_use;
881
882static void host_tempreg_acquire(void)
883{
884 assert(!host_tempreg_in_use);
885 host_tempreg_in_use = 1;
886}
887
888static void host_tempreg_release(void)
889{
890 host_tempreg_in_use = 0;
891}
892#else
893static void host_tempreg_acquire(void) {}
894static void host_tempreg_release(void) {}
895#endif
896
32631e6a 897#ifdef ASSEM_PRINT
8062d65a 898extern void gen_interupt();
899extern void do_insn_cmp();
d1e4ebd9 900#define FUNCNAME(f) { f, " " #f }
8062d65a 901static const struct {
d1e4ebd9 902 void *addr;
8062d65a 903 const char *name;
904} function_names[] = {
905 FUNCNAME(cc_interrupt),
906 FUNCNAME(gen_interupt),
907 FUNCNAME(get_addr_ht),
908 FUNCNAME(get_addr),
909 FUNCNAME(jump_handler_read8),
910 FUNCNAME(jump_handler_read16),
911 FUNCNAME(jump_handler_read32),
912 FUNCNAME(jump_handler_write8),
913 FUNCNAME(jump_handler_write16),
914 FUNCNAME(jump_handler_write32),
915 FUNCNAME(invalidate_addr),
3968e69e 916 FUNCNAME(jump_to_new_pc),
81dbbf4c 917 FUNCNAME(call_gteStall),
8062d65a 918 FUNCNAME(new_dyna_leave),
919 FUNCNAME(pcsx_mtc0),
920 FUNCNAME(pcsx_mtc0_ds),
32631e6a 921#ifdef DRC_DBG
8062d65a 922 FUNCNAME(do_insn_cmp),
32631e6a 923#endif
3968e69e 924#ifdef __arm__
925 FUNCNAME(verify_code),
926#endif
8062d65a 927};
928
d1e4ebd9 929static const char *func_name(const void *a)
8062d65a 930{
931 int i;
932 for (i = 0; i < sizeof(function_names)/sizeof(function_names[0]); i++)
933 if (function_names[i].addr == a)
934 return function_names[i].name;
935 return "";
936}
937#else
938#define func_name(x) ""
939#endif
940
57871462 941#ifdef __i386__
942#include "assem_x86.c"
943#endif
944#ifdef __x86_64__
945#include "assem_x64.c"
946#endif
947#ifdef __arm__
948#include "assem_arm.c"
949#endif
be516ebe 950#ifdef __aarch64__
951#include "assem_arm64.c"
952#endif
57871462 953
2a014d73 954static void *get_trampoline(const void *f)
955{
956 size_t i;
957
958 for (i = 0; i < ARRAY_SIZE(ndrc->tramp.f); i++) {
959 if (ndrc->tramp.f[i] == f || ndrc->tramp.f[i] == NULL)
960 break;
961 }
962 if (i == ARRAY_SIZE(ndrc->tramp.f)) {
963 SysPrintf("trampoline table is full, last func %p\n", f);
964 abort();
965 }
966 if (ndrc->tramp.f[i] == NULL) {
967 start_tcache_write(&ndrc->tramp.f[i], &ndrc->tramp.f[i + 1]);
968 ndrc->tramp.f[i] = f;
969 end_tcache_write(&ndrc->tramp.f[i], &ndrc->tramp.f[i + 1]);
970 }
971 return &ndrc->tramp.ops[i];
972}
973
974static void emit_far_jump(const void *f)
975{
976 if (can_jump_or_call(f)) {
977 emit_jmp(f);
978 return;
979 }
980
981 f = get_trampoline(f);
982 emit_jmp(f);
983}
984
985static void emit_far_call(const void *f)
986{
987 if (can_jump_or_call(f)) {
988 emit_call(f);
989 return;
990 }
991
992 f = get_trampoline(f);
993 emit_call(f);
994}
995
57871462 996// Add virtual address mapping to linked list
997void ll_add(struct ll_entry **head,int vaddr,void *addr)
998{
999 struct ll_entry *new_entry;
1000 new_entry=malloc(sizeof(struct ll_entry));
1001 assert(new_entry!=NULL);
1002 new_entry->vaddr=vaddr;
de5a60c3 1003 new_entry->reg_sv_flags=0;
57871462 1004 new_entry->addr=addr;
1005 new_entry->next=*head;
1006 *head=new_entry;
1007}
1008
de5a60c3 1009void ll_add_flags(struct ll_entry **head,int vaddr,u_int reg_sv_flags,void *addr)
57871462 1010{
7139f3c8 1011 ll_add(head,vaddr,addr);
de5a60c3 1012 (*head)->reg_sv_flags=reg_sv_flags;
57871462 1013}
1014
1015// Check if an address is already compiled
1016// but don't return addresses which are about to expire from the cache
1017void *check_addr(u_int vaddr)
1018{
df4dc2b1 1019 struct ht_entry *ht_bin = hash_table_get(vaddr);
1020 size_t i;
b14b6a8f 1021 for (i = 0; i < ARRAY_SIZE(ht_bin->vaddr); i++) {
df4dc2b1 1022 if (ht_bin->vaddr[i] == vaddr)
1023 if (doesnt_expire_soon((u_char *)ht_bin->tcaddr[i] - MAX_OUTPUT_BLOCK_SIZE))
1024 if (isclean(ht_bin->tcaddr[i]))
1025 return ht_bin->tcaddr[i];
57871462 1026 }
94d23bb9 1027 u_int page=get_page(vaddr);
57871462 1028 struct ll_entry *head;
1029 head=jump_in[page];
df4dc2b1 1030 while (head != NULL) {
1031 if (head->vaddr == vaddr) {
1032 if (doesnt_expire_soon(head->addr)) {
57871462 1033 // Update existing entry with current address
df4dc2b1 1034 if (ht_bin->vaddr[0] == vaddr) {
1035 ht_bin->tcaddr[0] = head->addr;
57871462 1036 return head->addr;
1037 }
df4dc2b1 1038 if (ht_bin->vaddr[1] == vaddr) {
1039 ht_bin->tcaddr[1] = head->addr;
57871462 1040 return head->addr;
1041 }
1042 // Insert into hash table with low priority.
1043 // Don't evict existing entries, as they are probably
1044 // addresses that are being accessed frequently.
df4dc2b1 1045 if (ht_bin->vaddr[0] == -1) {
1046 ht_bin->vaddr[0] = vaddr;
1047 ht_bin->tcaddr[0] = head->addr;
1048 }
1049 else if (ht_bin->vaddr[1] == -1) {
1050 ht_bin->vaddr[1] = vaddr;
1051 ht_bin->tcaddr[1] = head->addr;
57871462 1052 }
1053 return head->addr;
1054 }
1055 }
1056 head=head->next;
1057 }
1058 return 0;
1059}
1060
1061void remove_hash(int vaddr)
1062{
1063 //printf("remove hash: %x\n",vaddr);
df4dc2b1 1064 struct ht_entry *ht_bin = hash_table_get(vaddr);
1065 if (ht_bin->vaddr[1] == vaddr) {
1066 ht_bin->vaddr[1] = -1;
1067 ht_bin->tcaddr[1] = NULL;
57871462 1068 }
df4dc2b1 1069 if (ht_bin->vaddr[0] == vaddr) {
1070 ht_bin->vaddr[0] = ht_bin->vaddr[1];
1071 ht_bin->tcaddr[0] = ht_bin->tcaddr[1];
1072 ht_bin->vaddr[1] = -1;
1073 ht_bin->tcaddr[1] = NULL;
57871462 1074 }
1075}
1076
943f42f3 1077static void ll_remove_matching_addrs(struct ll_entry **head,
1078 uintptr_t base_offs_s, int shift)
57871462 1079{
1080 struct ll_entry *next;
1081 while(*head) {
943f42f3 1082 uintptr_t o1 = (u_char *)(*head)->addr - ndrc->translation_cache;
1083 uintptr_t o2 = o1 - MAX_OUTPUT_BLOCK_SIZE;
1084 if ((o1 >> shift) == base_offs_s || (o2 >> shift) == base_offs_s)
57871462 1085 {
643aeae3 1086 inv_debug("EXP: Remove pointer to %p (%x)\n",(*head)->addr,(*head)->vaddr);
57871462 1087 remove_hash((*head)->vaddr);
1088 next=(*head)->next;
1089 free(*head);
1090 *head=next;
1091 }
1092 else
1093 {
1094 head=&((*head)->next);
1095 }
1096 }
1097}
1098
1099// Remove all entries from linked list
1100void ll_clear(struct ll_entry **head)
1101{
1102 struct ll_entry *cur;
1103 struct ll_entry *next;
581335b0 1104 if((cur=*head)) {
57871462 1105 *head=0;
1106 while(cur) {
1107 next=cur->next;
1108 free(cur);
1109 cur=next;
1110 }
1111 }
1112}
1113
1114// Dereference the pointers and remove if it matches
943f42f3 1115static void ll_kill_pointers(struct ll_entry *head,
1116 uintptr_t base_offs_s, int shift)
57871462 1117{
1118 while(head) {
943f42f3 1119 u_char *ptr = get_pointer(head->addr);
1120 uintptr_t o1 = ptr - ndrc->translation_cache;
1121 uintptr_t o2 = o1 - MAX_OUTPUT_BLOCK_SIZE;
1122 inv_debug("EXP: Lookup pointer to %p at %p (%x)\n",ptr,head->addr,head->vaddr);
1123 if ((o1 >> shift) == base_offs_s || (o2 >> shift) == base_offs_s)
57871462 1124 {
643aeae3 1125 inv_debug("EXP: Kill pointer at %p (%x)\n",head->addr,head->vaddr);
d148d265 1126 void *host_addr=find_extjump_insn(head->addr);
919981d0 1127 mark_clear_cache(host_addr);
df4dc2b1 1128 set_jump_target(host_addr, head->addr);
57871462 1129 }
1130 head=head->next;
1131 }
1132}
1133
1134// This is called when we write to a compiled block (see do_invstub)
d1e4ebd9 1135static void invalidate_page(u_int page)
57871462 1136{
57871462 1137 struct ll_entry *head;
1138 struct ll_entry *next;
1139 head=jump_in[page];
1140 jump_in[page]=0;
1141 while(head!=NULL) {
1142 inv_debug("INVALIDATE: %x\n",head->vaddr);
1143 remove_hash(head->vaddr);
1144 next=head->next;
1145 free(head);
1146 head=next;
1147 }
1148 head=jump_out[page];
1149 jump_out[page]=0;
1150 while(head!=NULL) {
643aeae3 1151 inv_debug("INVALIDATE: kill pointer to %x (%p)\n",head->vaddr,head->addr);
d148d265 1152 void *host_addr=find_extjump_insn(head->addr);
919981d0 1153 mark_clear_cache(host_addr);
3d680478 1154 set_jump_target(host_addr, head->addr); // point back to dyna_linker
57871462 1155 next=head->next;
1156 free(head);
1157 head=next;
1158 }
57871462 1159}
9be4ba64 1160
1161static void invalidate_block_range(u_int block, u_int first, u_int last)
57871462 1162{
94d23bb9 1163 u_int page=get_page(block<<12);
57871462 1164 //printf("first=%d last=%d\n",first,last);
f76eeef9 1165 invalidate_page(page);
57871462 1166 assert(first+5>page); // NB: this assumes MAXBLOCK<=4096 (4 pages)
1167 assert(last<page+5);
1168 // Invalidate the adjacent pages if a block crosses a 4K boundary
1169 while(first<page) {
1170 invalidate_page(first);
1171 first++;
1172 }
1173 for(first=page+1;first<last;first++) {
1174 invalidate_page(first);
1175 }
919981d0 1176 do_clear_cache();
9f51b4b9 1177
57871462 1178 // Don't trap writes
1179 invalid_code[block]=1;
f76eeef9 1180
57871462 1181 #ifdef USE_MINI_HT
1182 memset(mini_ht,-1,sizeof(mini_ht));
1183 #endif
1184}
9be4ba64 1185
1186void invalidate_block(u_int block)
1187{
1188 u_int page=get_page(block<<12);
1189 u_int vpage=get_vpage(block<<12);
1190 inv_debug("INVALIDATE: %x (%d)\n",block<<12,page);
1191 //inv_debug("invalid_code[block]=%d\n",invalid_code[block]);
1192 u_int first,last;
1193 first=last=page;
1194 struct ll_entry *head;
1195 head=jump_dirty[vpage];
1196 //printf("page=%d vpage=%d\n",page,vpage);
1197 while(head!=NULL) {
9be4ba64 1198 if(vpage>2047||(head->vaddr>>12)==block) { // Ignore vaddr hash collision
01d26796 1199 u_char *start, *end;
1200 get_bounds(head->addr, &start, &end);
1201 //printf("start: %p end: %p\n", start, end);
1202 if (page < 2048 && start >= rdram && end < rdram+RAM_SIZE) {
1203 if (((start-rdram)>>12) <= page && ((end-1-rdram)>>12) >= page) {
1204 if ((((start-rdram)>>12)&2047) < first) first = ((start-rdram)>>12)&2047;
1205 if ((((end-1-rdram)>>12)&2047) > last) last = ((end-1-rdram)>>12)&2047;
9be4ba64 1206 }
1207 }
9be4ba64 1208 }
1209 head=head->next;
1210 }
1211 invalidate_block_range(block,first,last);
1212}
1213
57871462 1214void invalidate_addr(u_int addr)
1215{
9be4ba64 1216 //static int rhits;
1217 // this check is done by the caller
1218 //if (inv_code_start<=addr&&addr<=inv_code_end) { rhits++; return; }
d25604ca 1219 u_int page=get_vpage(addr);
9be4ba64 1220 if(page<2048) { // RAM
1221 struct ll_entry *head;
1222 u_int addr_min=~0, addr_max=0;
4a35de07 1223 u_int mask=RAM_SIZE-1;
1224 u_int addr_main=0x80000000|(addr&mask);
9be4ba64 1225 int pg1;
4a35de07 1226 inv_code_start=addr_main&~0xfff;
1227 inv_code_end=addr_main|0xfff;
9be4ba64 1228 pg1=page;
1229 if (pg1>0) {
1230 // must check previous page too because of spans..
1231 pg1--;
1232 inv_code_start-=0x1000;
1233 }
1234 for(;pg1<=page;pg1++) {
1235 for(head=jump_dirty[pg1];head!=NULL;head=head->next) {
01d26796 1236 u_char *start_h, *end_h;
1237 u_int start, end;
1238 get_bounds(head->addr, &start_h, &end_h);
1239 start = (uintptr_t)start_h - ram_offset;
1240 end = (uintptr_t)end_h - ram_offset;
4a35de07 1241 if(start<=addr_main&&addr_main<end) {
9be4ba64 1242 if(start<addr_min) addr_min=start;
1243 if(end>addr_max) addr_max=end;
1244 }
4a35de07 1245 else if(addr_main<start) {
9be4ba64 1246 if(start<inv_code_end)
1247 inv_code_end=start-1;
1248 }
1249 else {
1250 if(end>inv_code_start)
1251 inv_code_start=end;
1252 }
1253 }
1254 }
1255 if (addr_min!=~0) {
1256 inv_debug("INV ADDR: %08x hit %08x-%08x\n", addr, addr_min, addr_max);
1257 inv_code_start=inv_code_end=~0;
1258 invalidate_block_range(addr>>12,(addr_min&mask)>>12,(addr_max&mask)>>12);
1259 return;
1260 }
1261 else {
4a35de07 1262 inv_code_start=(addr&~mask)|(inv_code_start&mask);
1263 inv_code_end=(addr&~mask)|(inv_code_end&mask);
d25604ca 1264 inv_debug("INV ADDR: %08x miss, inv %08x-%08x, sk %d\n", addr, inv_code_start, inv_code_end, 0);
9be4ba64 1265 return;
d25604ca 1266 }
9be4ba64 1267 }
57871462 1268 invalidate_block(addr>>12);
1269}
9be4ba64 1270
dd3a91a1 1271// This is called when loading a save state.
1272// Anything could have changed, so invalidate everything.
919981d0 1273void invalidate_all_pages(void)
57871462 1274{
581335b0 1275 u_int page;
57871462 1276 for(page=0;page<4096;page++)
1277 invalidate_page(page);
1278 for(page=0;page<1048576;page++)
1279 if(!invalid_code[page]) {
1280 restore_candidate[(page&2047)>>3]|=1<<(page&7);
1281 restore_candidate[((page&2047)>>3)+256]|=1<<(page&7);
1282 }
57871462 1283 #ifdef USE_MINI_HT
1284 memset(mini_ht,-1,sizeof(mini_ht));
1285 #endif
919981d0 1286 do_clear_cache();
57871462 1287}
1288
d1e4ebd9 1289static void do_invstub(int n)
1290{
1291 literal_pool(20);
1292 u_int reglist=stubs[n].a;
1293 set_jump_target(stubs[n].addr, out);
1294 save_regs(reglist);
1295 if(stubs[n].b!=0) emit_mov(stubs[n].b,0);
2a014d73 1296 emit_far_call(invalidate_addr);
d1e4ebd9 1297 restore_regs(reglist);
1298 emit_jmp(stubs[n].retaddr); // return address
1299}
1300
57871462 1301// Add an entry to jump_out after making a link
d1e4ebd9 1302// src should point to code by emit_extjump2()
3d680478 1303void add_jump_out(u_int vaddr,void *src)
57871462 1304{
94d23bb9 1305 u_int page=get_page(vaddr);
3d680478 1306 inv_debug("add_jump_out: %p -> %x (%d)\n",src,vaddr,page);
d1e4ebd9 1307 check_extjump2(src);
57871462 1308 ll_add(jump_out+page,vaddr,src);
3d680478 1309 //inv_debug("add_jump_out: to %p\n",get_pointer(src));
57871462 1310}
1311
1312// If a code block was found to be unmodified (bit was set in
1313// restore_candidate) and it remains unmodified (bit is clear
1314// in invalid_code) then move the entries for that 4K page from
1315// the dirty list to the clean list.
1316void clean_blocks(u_int page)
1317{
1318 struct ll_entry *head;
1319 inv_debug("INV: clean_blocks page=%d\n",page);
1320 head=jump_dirty[page];
1321 while(head!=NULL) {
1322 if(!invalid_code[head->vaddr>>12]) {
1323 // Don't restore blocks which are about to expire from the cache
df4dc2b1 1324 if (doesnt_expire_soon(head->addr)) {
581335b0 1325 if(verify_dirty(head->addr)) {
01d26796 1326 u_char *start, *end;
643aeae3 1327 //printf("Possibly Restore %x (%p)\n",head->vaddr, head->addr);
57871462 1328 u_int i;
1329 u_int inv=0;
01d26796 1330 get_bounds(head->addr, &start, &end);
1331 if (start - rdram < RAM_SIZE) {
1332 for (i = (start-rdram+0x80000000)>>12; i <= (end-1-rdram+0x80000000)>>12; i++) {
57871462 1333 inv|=invalid_code[i];
1334 }
1335 }
4cb76aa4 1336 else if((signed int)head->vaddr>=(signed int)0x80000000+RAM_SIZE) {
57871462 1337 inv=1;
1338 }
1339 if(!inv) {
df4dc2b1 1340 void *clean_addr = get_clean_addr(head->addr);
1341 if (doesnt_expire_soon(clean_addr)) {
57871462 1342 u_int ppage=page;
643aeae3 1343 inv_debug("INV: Restored %x (%p/%p)\n",head->vaddr, head->addr, clean_addr);
57871462 1344 //printf("page=%x, addr=%x\n",page,head->vaddr);
1345 //assert(head->vaddr>>12==(page|0x80000));
de5a60c3 1346 ll_add_flags(jump_in+ppage,head->vaddr,head->reg_sv_flags,clean_addr);
df4dc2b1 1347 struct ht_entry *ht_bin = hash_table_get(head->vaddr);
1348 if (ht_bin->vaddr[0] == head->vaddr)
1349 ht_bin->tcaddr[0] = clean_addr; // Replace existing entry
1350 if (ht_bin->vaddr[1] == head->vaddr)
1351 ht_bin->tcaddr[1] = clean_addr; // Replace existing entry
57871462 1352 }
1353 }
1354 }
1355 }
1356 }
1357 head=head->next;
1358 }
1359}
1360
8062d65a 1361/* Register allocation */
1362
1363// Note: registers are allocated clean (unmodified state)
1364// if you intend to modify the register, you must call dirty_reg().
1365static void alloc_reg(struct regstat *cur,int i,signed char reg)
1366{
1367 int r,hr;
b7ec323c 1368 int preferred_reg = PREFERRED_REG_FIRST
1369 + reg % (PREFERRED_REG_LAST - PREFERRED_REG_FIRST + 1);
1370 if (reg == CCREG) preferred_reg = HOST_CCREG;
1371 if (reg == PTEMP || reg == FTEMP) preferred_reg = 12;
1372 assert(PREFERRED_REG_FIRST != EXCLUDE_REG && EXCLUDE_REG != HOST_REGS);
8062d65a 1373
1374 // Don't allocate unused registers
1375 if((cur->u>>reg)&1) return;
1376
1377 // see if it's already allocated
1378 for(hr=0;hr<HOST_REGS;hr++)
1379 {
1380 if(cur->regmap[hr]==reg) return;
1381 }
1382
1383 // Keep the same mapping if the register was already allocated in a loop
1384 preferred_reg = loop_reg(i,reg,preferred_reg);
1385
1386 // Try to allocate the preferred register
1387 if(cur->regmap[preferred_reg]==-1) {
1388 cur->regmap[preferred_reg]=reg;
1389 cur->dirty&=~(1<<preferred_reg);
1390 cur->isconst&=~(1<<preferred_reg);
1391 return;
1392 }
1393 r=cur->regmap[preferred_reg];
1394 assert(r < 64);
1395 if((cur->u>>r)&1) {
1396 cur->regmap[preferred_reg]=reg;
1397 cur->dirty&=~(1<<preferred_reg);
1398 cur->isconst&=~(1<<preferred_reg);
1399 return;
1400 }
1401
1402 // Clear any unneeded registers
1403 // We try to keep the mapping consistent, if possible, because it
1404 // makes branches easier (especially loops). So we try to allocate
1405 // first (see above) before removing old mappings. If this is not
1406 // possible then go ahead and clear out the registers that are no
1407 // longer needed.
1408 for(hr=0;hr<HOST_REGS;hr++)
1409 {
1410 r=cur->regmap[hr];
1411 if(r>=0) {
1412 assert(r < 64);
1413 if((cur->u>>r)&1) {cur->regmap[hr]=-1;break;}
1414 }
1415 }
b7ec323c 1416
8062d65a 1417 // Try to allocate any available register, but prefer
1418 // registers that have not been used recently.
b7ec323c 1419 if (i > 0) {
1420 for (hr = PREFERRED_REG_FIRST; ; ) {
1421 if (cur->regmap[hr] < 0) {
1422 int oldreg = regs[i-1].regmap[hr];
1423 if (oldreg < 0 || (oldreg != dops[i-1].rs1 && oldreg != dops[i-1].rs2
1424 && oldreg != dops[i-1].rt1 && oldreg != dops[i-1].rt2))
1425 {
8062d65a 1426 cur->regmap[hr]=reg;
1427 cur->dirty&=~(1<<hr);
1428 cur->isconst&=~(1<<hr);
1429 return;
1430 }
1431 }
b7ec323c 1432 hr++;
1433 if (hr == EXCLUDE_REG)
1434 hr++;
1435 if (hr == HOST_REGS)
1436 hr = 0;
1437 if (hr == PREFERRED_REG_FIRST)
1438 break;
8062d65a 1439 }
1440 }
b7ec323c 1441
8062d65a 1442 // Try to allocate any available register
b7ec323c 1443 for (hr = PREFERRED_REG_FIRST; ; ) {
1444 if (cur->regmap[hr] < 0) {
8062d65a 1445 cur->regmap[hr]=reg;
1446 cur->dirty&=~(1<<hr);
1447 cur->isconst&=~(1<<hr);
1448 return;
1449 }
b7ec323c 1450 hr++;
1451 if (hr == EXCLUDE_REG)
1452 hr++;
1453 if (hr == HOST_REGS)
1454 hr = 0;
1455 if (hr == PREFERRED_REG_FIRST)
1456 break;
8062d65a 1457 }
1458
1459 // Ok, now we have to evict someone
1460 // Pick a register we hopefully won't need soon
1461 u_char hsn[MAXREG+1];
1462 memset(hsn,10,sizeof(hsn));
1463 int j;
1464 lsn(hsn,i,&preferred_reg);
1465 //printf("eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",cur->regmap[0],cur->regmap[1],cur->regmap[2],cur->regmap[3],cur->regmap[5],cur->regmap[6],cur->regmap[7]);
1466 //printf("hsn(%x): %d %d %d %d %d %d %d\n",start+i*4,hsn[cur->regmap[0]&63],hsn[cur->regmap[1]&63],hsn[cur->regmap[2]&63],hsn[cur->regmap[3]&63],hsn[cur->regmap[5]&63],hsn[cur->regmap[6]&63],hsn[cur->regmap[7]&63]);
1467 if(i>0) {
1468 // Don't evict the cycle count at entry points, otherwise the entry
1469 // stub will have to write it.
cf95b4f0 1470 if(dops[i].bt&&hsn[CCREG]>2) hsn[CCREG]=2;
fe807a8a 1471 if (i>1 && hsn[CCREG] > 2 && dops[i-2].is_jump) hsn[CCREG]=2;
8062d65a 1472 for(j=10;j>=3;j--)
1473 {
1474 // Alloc preferred register if available
1475 if(hsn[r=cur->regmap[preferred_reg]&63]==j) {
1476 for(hr=0;hr<HOST_REGS;hr++) {
1477 // Evict both parts of a 64-bit register
1478 if((cur->regmap[hr]&63)==r) {
1479 cur->regmap[hr]=-1;
1480 cur->dirty&=~(1<<hr);
1481 cur->isconst&=~(1<<hr);
1482 }
1483 }
1484 cur->regmap[preferred_reg]=reg;
1485 return;
1486 }
1487 for(r=1;r<=MAXREG;r++)
1488 {
cf95b4f0 1489 if(hsn[r]==j&&r!=dops[i-1].rs1&&r!=dops[i-1].rs2&&r!=dops[i-1].rt1&&r!=dops[i-1].rt2) {
8062d65a 1490 for(hr=0;hr<HOST_REGS;hr++) {
1491 if(hr!=HOST_CCREG||j<hsn[CCREG]) {
1492 if(cur->regmap[hr]==r) {
1493 cur->regmap[hr]=reg;
1494 cur->dirty&=~(1<<hr);
1495 cur->isconst&=~(1<<hr);
1496 return;
1497 }
1498 }
1499 }
1500 }
1501 }
1502 }
1503 }
1504 for(j=10;j>=0;j--)
1505 {
1506 for(r=1;r<=MAXREG;r++)
1507 {
1508 if(hsn[r]==j) {
8062d65a 1509 for(hr=0;hr<HOST_REGS;hr++) {
1510 if(cur->regmap[hr]==r) {
1511 cur->regmap[hr]=reg;
1512 cur->dirty&=~(1<<hr);
1513 cur->isconst&=~(1<<hr);
1514 return;
1515 }
1516 }
1517 }
1518 }
1519 }
7c3a5182 1520 SysPrintf("This shouldn't happen (alloc_reg)");abort();
8062d65a 1521}
1522
1523// Allocate a temporary register. This is done without regard to
1524// dirty status or whether the register we request is on the unneeded list
1525// Note: This will only allocate one register, even if called multiple times
1526static void alloc_reg_temp(struct regstat *cur,int i,signed char reg)
1527{
1528 int r,hr;
1529 int preferred_reg = -1;
1530
1531 // see if it's already allocated
1532 for(hr=0;hr<HOST_REGS;hr++)
1533 {
1534 if(hr!=EXCLUDE_REG&&cur->regmap[hr]==reg) return;
1535 }
1536
1537 // Try to allocate any available register
1538 for(hr=HOST_REGS-1;hr>=0;hr--) {
1539 if(hr!=EXCLUDE_REG&&cur->regmap[hr]==-1) {
1540 cur->regmap[hr]=reg;
1541 cur->dirty&=~(1<<hr);
1542 cur->isconst&=~(1<<hr);
1543 return;
1544 }
1545 }
1546
1547 // Find an unneeded register
1548 for(hr=HOST_REGS-1;hr>=0;hr--)
1549 {
1550 r=cur->regmap[hr];
1551 if(r>=0) {
1552 assert(r < 64);
1553 if((cur->u>>r)&1) {
1554 if(i==0||((unneeded_reg[i-1]>>r)&1)) {
1555 cur->regmap[hr]=reg;
1556 cur->dirty&=~(1<<hr);
1557 cur->isconst&=~(1<<hr);
1558 return;
1559 }
1560 }
1561 }
1562 }
1563
1564 // Ok, now we have to evict someone
1565 // Pick a register we hopefully won't need soon
1566 // TODO: we might want to follow unconditional jumps here
1567 // TODO: get rid of dupe code and make this into a function
1568 u_char hsn[MAXREG+1];
1569 memset(hsn,10,sizeof(hsn));
1570 int j;
1571 lsn(hsn,i,&preferred_reg);
1572 //printf("hsn: %d %d %d %d %d %d %d\n",hsn[cur->regmap[0]&63],hsn[cur->regmap[1]&63],hsn[cur->regmap[2]&63],hsn[cur->regmap[3]&63],hsn[cur->regmap[5]&63],hsn[cur->regmap[6]&63],hsn[cur->regmap[7]&63]);
1573 if(i>0) {
1574 // Don't evict the cycle count at entry points, otherwise the entry
1575 // stub will have to write it.
cf95b4f0 1576 if(dops[i].bt&&hsn[CCREG]>2) hsn[CCREG]=2;
fe807a8a 1577 if (i>1 && hsn[CCREG] > 2 && dops[i-2].is_jump) hsn[CCREG]=2;
8062d65a 1578 for(j=10;j>=3;j--)
1579 {
1580 for(r=1;r<=MAXREG;r++)
1581 {
cf95b4f0 1582 if(hsn[r]==j&&r!=dops[i-1].rs1&&r!=dops[i-1].rs2&&r!=dops[i-1].rt1&&r!=dops[i-1].rt2) {
8062d65a 1583 for(hr=0;hr<HOST_REGS;hr++) {
1584 if(hr!=HOST_CCREG||hsn[CCREG]>2) {
1585 if(cur->regmap[hr]==r) {
1586 cur->regmap[hr]=reg;
1587 cur->dirty&=~(1<<hr);
1588 cur->isconst&=~(1<<hr);
1589 return;
1590 }
1591 }
1592 }
1593 }
1594 }
1595 }
1596 }
1597 for(j=10;j>=0;j--)
1598 {
1599 for(r=1;r<=MAXREG;r++)
1600 {
1601 if(hsn[r]==j) {
8062d65a 1602 for(hr=0;hr<HOST_REGS;hr++) {
1603 if(cur->regmap[hr]==r) {
1604 cur->regmap[hr]=reg;
1605 cur->dirty&=~(1<<hr);
1606 cur->isconst&=~(1<<hr);
1607 return;
1608 }
1609 }
1610 }
1611 }
1612 }
7c3a5182 1613 SysPrintf("This shouldn't happen");abort();
8062d65a 1614}
1615
ad49de89 1616static void mov_alloc(struct regstat *current,int i)
57871462 1617{
cf95b4f0 1618 if (dops[i].rs1 == HIREG || dops[i].rs1 == LOREG) {
9a3ccfeb 1619 alloc_cc(current,i); // for stalls
1620 dirty_reg(current,CCREG);
32631e6a 1621 }
1622
57871462 1623 // Note: Don't need to actually alloc the source registers
cf95b4f0 1624 //alloc_reg(current,i,dops[i].rs1);
1625 alloc_reg(current,i,dops[i].rt1);
ad49de89 1626
cf95b4f0 1627 clear_const(current,dops[i].rs1);
1628 clear_const(current,dops[i].rt1);
1629 dirty_reg(current,dops[i].rt1);
57871462 1630}
1631
ad49de89 1632static void shiftimm_alloc(struct regstat *current,int i)
57871462 1633{
cf95b4f0 1634 if(dops[i].opcode2<=0x3) // SLL/SRL/SRA
57871462 1635 {
cf95b4f0 1636 if(dops[i].rt1) {
1637 if(dops[i].rs1&&needed_again(dops[i].rs1,i)) alloc_reg(current,i,dops[i].rs1);
1638 else dops[i].lt1=dops[i].rs1;
1639 alloc_reg(current,i,dops[i].rt1);
1640 dirty_reg(current,dops[i].rt1);
1641 if(is_const(current,dops[i].rs1)) {
1642 int v=get_const(current,dops[i].rs1);
1643 if(dops[i].opcode2==0x00) set_const(current,dops[i].rt1,v<<imm[i]);
1644 if(dops[i].opcode2==0x02) set_const(current,dops[i].rt1,(u_int)v>>imm[i]);
1645 if(dops[i].opcode2==0x03) set_const(current,dops[i].rt1,v>>imm[i]);
dc49e339 1646 }
cf95b4f0 1647 else clear_const(current,dops[i].rt1);
57871462 1648 }
1649 }
dc49e339 1650 else
1651 {
cf95b4f0 1652 clear_const(current,dops[i].rs1);
1653 clear_const(current,dops[i].rt1);
dc49e339 1654 }
1655
cf95b4f0 1656 if(dops[i].opcode2>=0x38&&dops[i].opcode2<=0x3b) // DSLL/DSRL/DSRA
57871462 1657 {
9c45ca93 1658 assert(0);
57871462 1659 }
cf95b4f0 1660 if(dops[i].opcode2==0x3c) // DSLL32
57871462 1661 {
9c45ca93 1662 assert(0);
57871462 1663 }
cf95b4f0 1664 if(dops[i].opcode2==0x3e) // DSRL32
57871462 1665 {
9c45ca93 1666 assert(0);
57871462 1667 }
cf95b4f0 1668 if(dops[i].opcode2==0x3f) // DSRA32
57871462 1669 {
9c45ca93 1670 assert(0);
57871462 1671 }
1672}
1673
ad49de89 1674static void shift_alloc(struct regstat *current,int i)
57871462 1675{
cf95b4f0 1676 if(dops[i].rt1) {
1677 if(dops[i].opcode2<=0x07) // SLLV/SRLV/SRAV
57871462 1678 {
cf95b4f0 1679 if(dops[i].rs1) alloc_reg(current,i,dops[i].rs1);
1680 if(dops[i].rs2) alloc_reg(current,i,dops[i].rs2);
1681 alloc_reg(current,i,dops[i].rt1);
1682 if(dops[i].rt1==dops[i].rs2) {
e1190b87 1683 alloc_reg_temp(current,i,-1);
1684 minimum_free_regs[i]=1;
1685 }
57871462 1686 } else { // DSLLV/DSRLV/DSRAV
00fa9369 1687 assert(0);
57871462 1688 }
cf95b4f0 1689 clear_const(current,dops[i].rs1);
1690 clear_const(current,dops[i].rs2);
1691 clear_const(current,dops[i].rt1);
1692 dirty_reg(current,dops[i].rt1);
57871462 1693 }
1694}
1695
ad49de89 1696static void alu_alloc(struct regstat *current,int i)
57871462 1697{
cf95b4f0 1698 if(dops[i].opcode2>=0x20&&dops[i].opcode2<=0x23) { // ADD/ADDU/SUB/SUBU
1699 if(dops[i].rt1) {
1700 if(dops[i].rs1&&dops[i].rs2) {
1701 alloc_reg(current,i,dops[i].rs1);
1702 alloc_reg(current,i,dops[i].rs2);
57871462 1703 }
1704 else {
cf95b4f0 1705 if(dops[i].rs1&&needed_again(dops[i].rs1,i)) alloc_reg(current,i,dops[i].rs1);
1706 if(dops[i].rs2&&needed_again(dops[i].rs2,i)) alloc_reg(current,i,dops[i].rs2);
57871462 1707 }
cf95b4f0 1708 alloc_reg(current,i,dops[i].rt1);
57871462 1709 }
57871462 1710 }
cf95b4f0 1711 if(dops[i].opcode2==0x2a||dops[i].opcode2==0x2b) { // SLT/SLTU
1712 if(dops[i].rt1) {
1713 alloc_reg(current,i,dops[i].rs1);
1714 alloc_reg(current,i,dops[i].rs2);
1715 alloc_reg(current,i,dops[i].rt1);
57871462 1716 }
57871462 1717 }
cf95b4f0 1718 if(dops[i].opcode2>=0x24&&dops[i].opcode2<=0x27) { // AND/OR/XOR/NOR
1719 if(dops[i].rt1) {
1720 if(dops[i].rs1&&dops[i].rs2) {
1721 alloc_reg(current,i,dops[i].rs1);
1722 alloc_reg(current,i,dops[i].rs2);
57871462 1723 }
1724 else
1725 {
cf95b4f0 1726 if(dops[i].rs1&&needed_again(dops[i].rs1,i)) alloc_reg(current,i,dops[i].rs1);
1727 if(dops[i].rs2&&needed_again(dops[i].rs2,i)) alloc_reg(current,i,dops[i].rs2);
57871462 1728 }
cf95b4f0 1729 alloc_reg(current,i,dops[i].rt1);
57871462 1730 }
1731 }
cf95b4f0 1732 if(dops[i].opcode2>=0x2c&&dops[i].opcode2<=0x2f) { // DADD/DADDU/DSUB/DSUBU
00fa9369 1733 assert(0);
57871462 1734 }
cf95b4f0 1735 clear_const(current,dops[i].rs1);
1736 clear_const(current,dops[i].rs2);
1737 clear_const(current,dops[i].rt1);
1738 dirty_reg(current,dops[i].rt1);
57871462 1739}
1740
ad49de89 1741static void imm16_alloc(struct regstat *current,int i)
57871462 1742{
cf95b4f0 1743 if(dops[i].rs1&&needed_again(dops[i].rs1,i)) alloc_reg(current,i,dops[i].rs1);
1744 else dops[i].lt1=dops[i].rs1;
1745 if(dops[i].rt1) alloc_reg(current,i,dops[i].rt1);
1746 if(dops[i].opcode==0x18||dops[i].opcode==0x19) { // DADDI/DADDIU
00fa9369 1747 assert(0);
57871462 1748 }
cf95b4f0 1749 else if(dops[i].opcode==0x0a||dops[i].opcode==0x0b) { // SLTI/SLTIU
1750 clear_const(current,dops[i].rs1);
1751 clear_const(current,dops[i].rt1);
57871462 1752 }
cf95b4f0 1753 else if(dops[i].opcode>=0x0c&&dops[i].opcode<=0x0e) { // ANDI/ORI/XORI
1754 if(is_const(current,dops[i].rs1)) {
1755 int v=get_const(current,dops[i].rs1);
1756 if(dops[i].opcode==0x0c) set_const(current,dops[i].rt1,v&imm[i]);
1757 if(dops[i].opcode==0x0d) set_const(current,dops[i].rt1,v|imm[i]);
1758 if(dops[i].opcode==0x0e) set_const(current,dops[i].rt1,v^imm[i]);
57871462 1759 }
cf95b4f0 1760 else clear_const(current,dops[i].rt1);
57871462 1761 }
cf95b4f0 1762 else if(dops[i].opcode==0x08||dops[i].opcode==0x09) { // ADDI/ADDIU
1763 if(is_const(current,dops[i].rs1)) {
1764 int v=get_const(current,dops[i].rs1);
1765 set_const(current,dops[i].rt1,v+imm[i]);
57871462 1766 }
cf95b4f0 1767 else clear_const(current,dops[i].rt1);
57871462 1768 }
1769 else {
cf95b4f0 1770 set_const(current,dops[i].rt1,imm[i]<<16); // LUI
57871462 1771 }
cf95b4f0 1772 dirty_reg(current,dops[i].rt1);
57871462 1773}
1774
ad49de89 1775static void load_alloc(struct regstat *current,int i)
57871462 1776{
cf95b4f0 1777 clear_const(current,dops[i].rt1);
1778 //if(dops[i].rs1!=dops[i].rt1&&needed_again(dops[i].rs1,i)) clear_const(current,dops[i].rs1); // Does this help or hurt?
1779 if(!dops[i].rs1) current->u&=~1LL; // Allow allocating r0 if it's the source register
37387d8b 1780 if (needed_again(dops[i].rs1, i))
1781 alloc_reg(current, i, dops[i].rs1);
1782 if (ram_offset)
1783 alloc_reg(current, i, ROREG);
cf95b4f0 1784 if(dops[i].rt1&&!((current->u>>dops[i].rt1)&1)) {
1785 alloc_reg(current,i,dops[i].rt1);
1786 assert(get_reg(current->regmap,dops[i].rt1)>=0);
1787 if(dops[i].opcode==0x27||dops[i].opcode==0x37) // LWU/LD
57871462 1788 {
ad49de89 1789 assert(0);
57871462 1790 }
cf95b4f0 1791 else if(dops[i].opcode==0x1A||dops[i].opcode==0x1B) // LDL/LDR
57871462 1792 {
ad49de89 1793 assert(0);
57871462 1794 }
cf95b4f0 1795 dirty_reg(current,dops[i].rt1);
57871462 1796 // LWL/LWR need a temporary register for the old value
cf95b4f0 1797 if(dops[i].opcode==0x22||dops[i].opcode==0x26)
57871462 1798 {
1799 alloc_reg(current,i,FTEMP);
1800 alloc_reg_temp(current,i,-1);
e1190b87 1801 minimum_free_regs[i]=1;
57871462 1802 }
1803 }
1804 else
1805 {
373d1d07 1806 // Load to r0 or unneeded register (dummy load)
57871462 1807 // but we still need a register to calculate the address
cf95b4f0 1808 if(dops[i].opcode==0x22||dops[i].opcode==0x26)
535d208a 1809 {
1810 alloc_reg(current,i,FTEMP); // LWL/LWR need another temporary
1811 }
57871462 1812 alloc_reg_temp(current,i,-1);
e1190b87 1813 minimum_free_regs[i]=1;
cf95b4f0 1814 if(dops[i].opcode==0x1A||dops[i].opcode==0x1B) // LDL/LDR
535d208a 1815 {
ad49de89 1816 assert(0);
535d208a 1817 }
57871462 1818 }
1819}
1820
1821void store_alloc(struct regstat *current,int i)
1822{
cf95b4f0 1823 clear_const(current,dops[i].rs2);
1824 if(!(dops[i].rs2)) current->u&=~1LL; // Allow allocating r0 if necessary
1825 if(needed_again(dops[i].rs1,i)) alloc_reg(current,i,dops[i].rs1);
1826 alloc_reg(current,i,dops[i].rs2);
1827 if(dops[i].opcode==0x2c||dops[i].opcode==0x2d||dops[i].opcode==0x3f) { // 64-bit SDL/SDR/SD
ad49de89 1828 assert(0);
57871462 1829 }
37387d8b 1830 if (ram_offset)
1831 alloc_reg(current, i, ROREG);
57871462 1832 #if defined(HOST_IMM8)
1833 // On CPUs without 32-bit immediates we need a pointer to invalid_code
37387d8b 1834 alloc_reg(current, i, INVCP);
57871462 1835 #endif
cf95b4f0 1836 if(dops[i].opcode==0x2a||dops[i].opcode==0x2e||dops[i].opcode==0x2c||dops[i].opcode==0x2d) { // SWL/SWL/SDL/SDR
57871462 1837 alloc_reg(current,i,FTEMP);
1838 }
1839 // We need a temporary register for address generation
1840 alloc_reg_temp(current,i,-1);
e1190b87 1841 minimum_free_regs[i]=1;
57871462 1842}
1843
1844void c1ls_alloc(struct regstat *current,int i)
1845{
cf95b4f0 1846 clear_const(current,dops[i].rt1);
57871462 1847 alloc_reg(current,i,CSREG); // Status
57871462 1848}
1849
b9b61529 1850void c2ls_alloc(struct regstat *current,int i)
1851{
cf95b4f0 1852 clear_const(current,dops[i].rt1);
1853 if(needed_again(dops[i].rs1,i)) alloc_reg(current,i,dops[i].rs1);
b9b61529 1854 alloc_reg(current,i,FTEMP);
37387d8b 1855 if (ram_offset)
1856 alloc_reg(current, i, ROREG);
b9b61529 1857 #if defined(HOST_IMM8)
1858 // On CPUs without 32-bit immediates we need a pointer to invalid_code
37387d8b 1859 if (dops[i].opcode == 0x3a) // SWC2
b9b61529 1860 alloc_reg(current,i,INVCP);
1861 #endif
1862 // We need a temporary register for address generation
1863 alloc_reg_temp(current,i,-1);
e1190b87 1864 minimum_free_regs[i]=1;
b9b61529 1865}
1866
57871462 1867#ifndef multdiv_alloc
1868void multdiv_alloc(struct regstat *current,int i)
1869{
1870 // case 0x18: MULT
1871 // case 0x19: MULTU
1872 // case 0x1A: DIV
1873 // case 0x1B: DIVU
1874 // case 0x1C: DMULT
1875 // case 0x1D: DMULTU
1876 // case 0x1E: DDIV
1877 // case 0x1F: DDIVU
cf95b4f0 1878 clear_const(current,dops[i].rs1);
1879 clear_const(current,dops[i].rs2);
32631e6a 1880 alloc_cc(current,i); // for stalls
cf95b4f0 1881 if(dops[i].rs1&&dops[i].rs2)
57871462 1882 {
cf95b4f0 1883 if((dops[i].opcode2&4)==0) // 32-bit
57871462 1884 {
1885 current->u&=~(1LL<<HIREG);
1886 current->u&=~(1LL<<LOREG);
1887 alloc_reg(current,i,HIREG);
1888 alloc_reg(current,i,LOREG);
cf95b4f0 1889 alloc_reg(current,i,dops[i].rs1);
1890 alloc_reg(current,i,dops[i].rs2);
57871462 1891 dirty_reg(current,HIREG);
1892 dirty_reg(current,LOREG);
1893 }
1894 else // 64-bit
1895 {
00fa9369 1896 assert(0);
57871462 1897 }
1898 }
1899 else
1900 {
1901 // Multiply by zero is zero.
1902 // MIPS does not have a divide by zero exception.
1903 // The result is undefined, we return zero.
1904 alloc_reg(current,i,HIREG);
1905 alloc_reg(current,i,LOREG);
57871462 1906 dirty_reg(current,HIREG);
1907 dirty_reg(current,LOREG);
1908 }
1909}
1910#endif
1911
1912void cop0_alloc(struct regstat *current,int i)
1913{
cf95b4f0 1914 if(dops[i].opcode2==0) // MFC0
57871462 1915 {
cf95b4f0 1916 if(dops[i].rt1) {
1917 clear_const(current,dops[i].rt1);
57871462 1918 alloc_all(current,i);
cf95b4f0 1919 alloc_reg(current,i,dops[i].rt1);
1920 dirty_reg(current,dops[i].rt1);
57871462 1921 }
1922 }
cf95b4f0 1923 else if(dops[i].opcode2==4) // MTC0
57871462 1924 {
cf95b4f0 1925 if(dops[i].rs1){
1926 clear_const(current,dops[i].rs1);
1927 alloc_reg(current,i,dops[i].rs1);
57871462 1928 alloc_all(current,i);
1929 }
1930 else {
1931 alloc_all(current,i); // FIXME: Keep r0
1932 current->u&=~1LL;
1933 alloc_reg(current,i,0);
1934 }
1935 }
1936 else
1937 {
1938 // TLBR/TLBWI/TLBWR/TLBP/ERET
cf95b4f0 1939 assert(dops[i].opcode2==0x10);
57871462 1940 alloc_all(current,i);
1941 }
e1190b87 1942 minimum_free_regs[i]=HOST_REGS;
57871462 1943}
1944
81dbbf4c 1945static void cop2_alloc(struct regstat *current,int i)
57871462 1946{
cf95b4f0 1947 if (dops[i].opcode2 < 3) // MFC2/CFC2
57871462 1948 {
81dbbf4c 1949 alloc_cc(current,i); // for stalls
1950 dirty_reg(current,CCREG);
cf95b4f0 1951 if(dops[i].rt1){
1952 clear_const(current,dops[i].rt1);
1953 alloc_reg(current,i,dops[i].rt1);
1954 dirty_reg(current,dops[i].rt1);
57871462 1955 }
57871462 1956 }
cf95b4f0 1957 else if (dops[i].opcode2 > 3) // MTC2/CTC2
57871462 1958 {
cf95b4f0 1959 if(dops[i].rs1){
1960 clear_const(current,dops[i].rs1);
1961 alloc_reg(current,i,dops[i].rs1);
57871462 1962 }
1963 else {
1964 current->u&=~1LL;
1965 alloc_reg(current,i,0);
57871462 1966 }
1967 }
81dbbf4c 1968 alloc_reg_temp(current,i,-1);
e1190b87 1969 minimum_free_regs[i]=1;
57871462 1970}
00fa9369 1971
b9b61529 1972void c2op_alloc(struct regstat *current,int i)
1973{
81dbbf4c 1974 alloc_cc(current,i); // for stalls
1975 dirty_reg(current,CCREG);
b9b61529 1976 alloc_reg_temp(current,i,-1);
1977}
57871462 1978
1979void syscall_alloc(struct regstat *current,int i)
1980{
1981 alloc_cc(current,i);
1982 dirty_reg(current,CCREG);
1983 alloc_all(current,i);
e1190b87 1984 minimum_free_regs[i]=HOST_REGS;
57871462 1985 current->isconst=0;
1986}
1987
1988void delayslot_alloc(struct regstat *current,int i)
1989{
cf95b4f0 1990 switch(dops[i].itype) {
57871462 1991 case UJUMP:
1992 case CJUMP:
1993 case SJUMP:
1994 case RJUMP:
57871462 1995 case SYSCALL:
7139f3c8 1996 case HLECALL:
57871462 1997 case SPAN:
7c3a5182 1998 assem_debug("jump in the delay slot. this shouldn't happen.\n");//abort();
c43b5311 1999 SysPrintf("Disabled speculative precompilation\n");
57871462 2000 stop_after_jal=1;
2001 break;
2002 case IMM16:
2003 imm16_alloc(current,i);
2004 break;
2005 case LOAD:
2006 case LOADLR:
2007 load_alloc(current,i);
2008 break;
2009 case STORE:
2010 case STORELR:
2011 store_alloc(current,i);
2012 break;
2013 case ALU:
2014 alu_alloc(current,i);
2015 break;
2016 case SHIFT:
2017 shift_alloc(current,i);
2018 break;
2019 case MULTDIV:
2020 multdiv_alloc(current,i);
2021 break;
2022 case SHIFTIMM:
2023 shiftimm_alloc(current,i);
2024 break;
2025 case MOV:
2026 mov_alloc(current,i);
2027 break;
2028 case COP0:
2029 cop0_alloc(current,i);
2030 break;
2031 case COP1:
81dbbf4c 2032 break;
b9b61529 2033 case COP2:
81dbbf4c 2034 cop2_alloc(current,i);
57871462 2035 break;
2036 case C1LS:
2037 c1ls_alloc(current,i);
2038 break;
b9b61529 2039 case C2LS:
2040 c2ls_alloc(current,i);
2041 break;
b9b61529 2042 case C2OP:
2043 c2op_alloc(current,i);
2044 break;
57871462 2045 }
2046}
2047
2048// Special case where a branch and delay slot span two pages in virtual memory
2049static void pagespan_alloc(struct regstat *current,int i)
2050{
2051 current->isconst=0;
2052 current->wasconst=0;
2053 regs[i].wasconst=0;
e1190b87 2054 minimum_free_regs[i]=HOST_REGS;
57871462 2055 alloc_all(current,i);
2056 alloc_cc(current,i);
2057 dirty_reg(current,CCREG);
cf95b4f0 2058 if(dops[i].opcode==3) // JAL
57871462 2059 {
2060 alloc_reg(current,i,31);
2061 dirty_reg(current,31);
2062 }
cf95b4f0 2063 if(dops[i].opcode==0&&(dops[i].opcode2&0x3E)==8) // JR/JALR
57871462 2064 {
cf95b4f0 2065 alloc_reg(current,i,dops[i].rs1);
2066 if (dops[i].rt1!=0) {
2067 alloc_reg(current,i,dops[i].rt1);
2068 dirty_reg(current,dops[i].rt1);
57871462 2069 }
2070 }
cf95b4f0 2071 if((dops[i].opcode&0x2E)==4) // BEQ/BNE/BEQL/BNEL
57871462 2072 {
cf95b4f0 2073 if(dops[i].rs1) alloc_reg(current,i,dops[i].rs1);
2074 if(dops[i].rs2) alloc_reg(current,i,dops[i].rs2);
57871462 2075 }
2076 else
cf95b4f0 2077 if((dops[i].opcode&0x2E)==6) // BLEZ/BGTZ/BLEZL/BGTZL
57871462 2078 {
cf95b4f0 2079 if(dops[i].rs1) alloc_reg(current,i,dops[i].rs1);
57871462 2080 }
57871462 2081 //else ...
2082}
2083
b14b6a8f 2084static void add_stub(enum stub_type type, void *addr, void *retaddr,
2085 u_int a, uintptr_t b, uintptr_t c, u_int d, u_int e)
2086{
d1e4ebd9 2087 assert(stubcount < ARRAY_SIZE(stubs));
b14b6a8f 2088 stubs[stubcount].type = type;
2089 stubs[stubcount].addr = addr;
2090 stubs[stubcount].retaddr = retaddr;
2091 stubs[stubcount].a = a;
2092 stubs[stubcount].b = b;
2093 stubs[stubcount].c = c;
2094 stubs[stubcount].d = d;
2095 stubs[stubcount].e = e;
57871462 2096 stubcount++;
2097}
2098
b14b6a8f 2099static void add_stub_r(enum stub_type type, void *addr, void *retaddr,
81dbbf4c 2100 int i, int addr_reg, const struct regstat *i_regs, int ccadj, u_int reglist)
b14b6a8f 2101{
2102 add_stub(type, addr, retaddr, i, addr_reg, (uintptr_t)i_regs, ccadj, reglist);
2103}
2104
57871462 2105// Write out a single register
2330734f 2106static void wb_register(signed char r, const signed char regmap[], uint64_t dirty)
57871462 2107{
2108 int hr;
2109 for(hr=0;hr<HOST_REGS;hr++) {
2110 if(hr!=EXCLUDE_REG) {
2111 if((regmap[hr]&63)==r) {
2112 if((dirty>>hr)&1) {
ad49de89 2113 assert(regmap[hr]<64);
2114 emit_storereg(r,hr);
57871462 2115 }
2116 }
2117 }
2118 }
2119}
2120
8062d65a 2121static void wb_valid(signed char pre[],signed char entry[],u_int dirty_pre,u_int dirty,uint64_t u)
2122{
2123 //if(dirty_pre==dirty) return;
2124 int hr,reg;
2125 for(hr=0;hr<HOST_REGS;hr++) {
2126 if(hr!=EXCLUDE_REG) {
2127 reg=pre[hr];
2128 if(((~u)>>(reg&63))&1) {
2129 if(reg>0) {
2130 if(((dirty_pre&~dirty)>>hr)&1) {
2131 if(reg>0&&reg<34) {
2132 emit_storereg(reg,hr);
2133 }
2134 else if(reg>=64) {
2135 assert(0);
2136 }
2137 }
2138 }
2139 }
2140 }
2141 }
2142}
2143
687b4580 2144// trashes r2
2145static void pass_args(int a0, int a1)
2146{
2147 if(a0==1&&a1==0) {
2148 // must swap
2149 emit_mov(a0,2); emit_mov(a1,1); emit_mov(2,0);
2150 }
2151 else if(a0!=0&&a1==0) {
2152 emit_mov(a1,1);
2153 if (a0>=0) emit_mov(a0,0);
2154 }
2155 else {
2156 if(a0>=0&&a0!=0) emit_mov(a0,0);
2157 if(a1>=0&&a1!=1) emit_mov(a1,1);
2158 }
2159}
2160
2330734f 2161static void alu_assemble(int i, const struct regstat *i_regs)
57871462 2162{
cf95b4f0 2163 if(dops[i].opcode2>=0x20&&dops[i].opcode2<=0x23) { // ADD/ADDU/SUB/SUBU
2164 if(dops[i].rt1) {
57871462 2165 signed char s1,s2,t;
cf95b4f0 2166 t=get_reg(i_regs->regmap,dops[i].rt1);
57871462 2167 if(t>=0) {
cf95b4f0 2168 s1=get_reg(i_regs->regmap,dops[i].rs1);
2169 s2=get_reg(i_regs->regmap,dops[i].rs2);
2170 if(dops[i].rs1&&dops[i].rs2) {
57871462 2171 assert(s1>=0);
2172 assert(s2>=0);
cf95b4f0 2173 if(dops[i].opcode2&2) emit_sub(s1,s2,t);
57871462 2174 else emit_add(s1,s2,t);
2175 }
cf95b4f0 2176 else if(dops[i].rs1) {
57871462 2177 if(s1>=0) emit_mov(s1,t);
cf95b4f0 2178 else emit_loadreg(dops[i].rs1,t);
57871462 2179 }
cf95b4f0 2180 else if(dops[i].rs2) {
57871462 2181 if(s2>=0) {
cf95b4f0 2182 if(dops[i].opcode2&2) emit_neg(s2,t);
57871462 2183 else emit_mov(s2,t);
2184 }
2185 else {
cf95b4f0 2186 emit_loadreg(dops[i].rs2,t);
2187 if(dops[i].opcode2&2) emit_neg(t,t);
57871462 2188 }
2189 }
2190 else emit_zeroreg(t);
2191 }
2192 }
2193 }
cf95b4f0 2194 if(dops[i].opcode2>=0x2c&&dops[i].opcode2<=0x2f) { // DADD/DADDU/DSUB/DSUBU
00fa9369 2195 assert(0);
57871462 2196 }
cf95b4f0 2197 if(dops[i].opcode2==0x2a||dops[i].opcode2==0x2b) { // SLT/SLTU
2198 if(dops[i].rt1) {
ad49de89 2199 signed char s1l,s2l,t;
57871462 2200 {
cf95b4f0 2201 t=get_reg(i_regs->regmap,dops[i].rt1);
57871462 2202 //assert(t>=0);
2203 if(t>=0) {
cf95b4f0 2204 s1l=get_reg(i_regs->regmap,dops[i].rs1);
2205 s2l=get_reg(i_regs->regmap,dops[i].rs2);
2206 if(dops[i].rs2==0) // rx<r0
57871462 2207 {
cf95b4f0 2208 if(dops[i].opcode2==0x2a&&dops[i].rs1!=0) { // SLT
06e425d7 2209 assert(s1l>=0);
57871462 2210 emit_shrimm(s1l,31,t);
06e425d7 2211 }
2212 else // SLTU (unsigned can not be less than zero, 0<0)
57871462 2213 emit_zeroreg(t);
2214 }
cf95b4f0 2215 else if(dops[i].rs1==0) // r0<rx
57871462 2216 {
2217 assert(s2l>=0);
cf95b4f0 2218 if(dops[i].opcode2==0x2a) // SLT
57871462 2219 emit_set_gz32(s2l,t);
2220 else // SLTU (set if not zero)
2221 emit_set_nz32(s2l,t);
2222 }
2223 else{
2224 assert(s1l>=0);assert(s2l>=0);
cf95b4f0 2225 if(dops[i].opcode2==0x2a) // SLT
57871462 2226 emit_set_if_less32(s1l,s2l,t);
2227 else // SLTU
2228 emit_set_if_carry32(s1l,s2l,t);
2229 }
2230 }
2231 }
2232 }
2233 }
cf95b4f0 2234 if(dops[i].opcode2>=0x24&&dops[i].opcode2<=0x27) { // AND/OR/XOR/NOR
2235 if(dops[i].rt1) {
ad49de89 2236 signed char s1l,s2l,tl;
cf95b4f0 2237 tl=get_reg(i_regs->regmap,dops[i].rt1);
57871462 2238 {
57871462 2239 if(tl>=0) {
cf95b4f0 2240 s1l=get_reg(i_regs->regmap,dops[i].rs1);
2241 s2l=get_reg(i_regs->regmap,dops[i].rs2);
2242 if(dops[i].rs1&&dops[i].rs2) {
57871462 2243 assert(s1l>=0);
2244 assert(s2l>=0);
cf95b4f0 2245 if(dops[i].opcode2==0x24) { // AND
57871462 2246 emit_and(s1l,s2l,tl);
2247 } else
cf95b4f0 2248 if(dops[i].opcode2==0x25) { // OR
57871462 2249 emit_or(s1l,s2l,tl);
2250 } else
cf95b4f0 2251 if(dops[i].opcode2==0x26) { // XOR
57871462 2252 emit_xor(s1l,s2l,tl);
2253 } else
cf95b4f0 2254 if(dops[i].opcode2==0x27) { // NOR
57871462 2255 emit_or(s1l,s2l,tl);
2256 emit_not(tl,tl);
2257 }
2258 }
2259 else
2260 {
cf95b4f0 2261 if(dops[i].opcode2==0x24) { // AND
57871462 2262 emit_zeroreg(tl);
2263 } else
cf95b4f0 2264 if(dops[i].opcode2==0x25||dops[i].opcode2==0x26) { // OR/XOR
2265 if(dops[i].rs1){
57871462 2266 if(s1l>=0) emit_mov(s1l,tl);
cf95b4f0 2267 else emit_loadreg(dops[i].rs1,tl); // CHECK: regmap_entry?
57871462 2268 }
2269 else
cf95b4f0 2270 if(dops[i].rs2){
57871462 2271 if(s2l>=0) emit_mov(s2l,tl);
cf95b4f0 2272 else emit_loadreg(dops[i].rs2,tl); // CHECK: regmap_entry?
57871462 2273 }
2274 else emit_zeroreg(tl);
2275 } else
cf95b4f0 2276 if(dops[i].opcode2==0x27) { // NOR
2277 if(dops[i].rs1){
57871462 2278 if(s1l>=0) emit_not(s1l,tl);
2279 else {
cf95b4f0 2280 emit_loadreg(dops[i].rs1,tl);
57871462 2281 emit_not(tl,tl);
2282 }
2283 }
2284 else
cf95b4f0 2285 if(dops[i].rs2){
57871462 2286 if(s2l>=0) emit_not(s2l,tl);
2287 else {
cf95b4f0 2288 emit_loadreg(dops[i].rs2,tl);
57871462 2289 emit_not(tl,tl);
2290 }
2291 }
2292 else emit_movimm(-1,tl);
2293 }
2294 }
2295 }
2296 }
2297 }
2298 }
2299}
2300
2330734f 2301static void imm16_assemble(int i, const struct regstat *i_regs)
57871462 2302{
cf95b4f0 2303 if (dops[i].opcode==0x0f) { // LUI
2304 if(dops[i].rt1) {
57871462 2305 signed char t;
cf95b4f0 2306 t=get_reg(i_regs->regmap,dops[i].rt1);
57871462 2307 //assert(t>=0);
2308 if(t>=0) {
2309 if(!((i_regs->isconst>>t)&1))
2310 emit_movimm(imm[i]<<16,t);
2311 }
2312 }
2313 }
cf95b4f0 2314 if(dops[i].opcode==0x08||dops[i].opcode==0x09) { // ADDI/ADDIU
2315 if(dops[i].rt1) {
57871462 2316 signed char s,t;
cf95b4f0 2317 t=get_reg(i_regs->regmap,dops[i].rt1);
2318 s=get_reg(i_regs->regmap,dops[i].rs1);
2319 if(dops[i].rs1) {
57871462 2320 //assert(t>=0);
2321 //assert(s>=0);
2322 if(t>=0) {
2323 if(!((i_regs->isconst>>t)&1)) {
2324 if(s<0) {
cf95b4f0 2325 if(i_regs->regmap_entry[t]!=dops[i].rs1) emit_loadreg(dops[i].rs1,t);
57871462 2326 emit_addimm(t,imm[i],t);
2327 }else{
2328 if(!((i_regs->wasconst>>s)&1))
2329 emit_addimm(s,imm[i],t);
2330 else
2331 emit_movimm(constmap[i][s]+imm[i],t);
2332 }
2333 }
2334 }
2335 } else {
2336 if(t>=0) {
2337 if(!((i_regs->isconst>>t)&1))
2338 emit_movimm(imm[i],t);
2339 }
2340 }
2341 }
2342 }
cf95b4f0 2343 if(dops[i].opcode==0x18||dops[i].opcode==0x19) { // DADDI/DADDIU
2344 if(dops[i].rt1) {
7c3a5182 2345 signed char sl,tl;
cf95b4f0 2346 tl=get_reg(i_regs->regmap,dops[i].rt1);
2347 sl=get_reg(i_regs->regmap,dops[i].rs1);
57871462 2348 if(tl>=0) {
cf95b4f0 2349 if(dops[i].rs1) {
57871462 2350 assert(sl>=0);
7c3a5182 2351 emit_addimm(sl,imm[i],tl);
57871462 2352 } else {
2353 emit_movimm(imm[i],tl);
57871462 2354 }
2355 }
2356 }
2357 }
cf95b4f0 2358 else if(dops[i].opcode==0x0a||dops[i].opcode==0x0b) { // SLTI/SLTIU
2359 if(dops[i].rt1) {
2360 //assert(dops[i].rs1!=0); // r0 might be valid, but it's probably a bug
ad49de89 2361 signed char sl,t;
cf95b4f0 2362 t=get_reg(i_regs->regmap,dops[i].rt1);
2363 sl=get_reg(i_regs->regmap,dops[i].rs1);
57871462 2364 //assert(t>=0);
2365 if(t>=0) {
cf95b4f0 2366 if(dops[i].rs1>0) {
2367 if(dops[i].opcode==0x0a) { // SLTI
57871462 2368 if(sl<0) {
cf95b4f0 2369 if(i_regs->regmap_entry[t]!=dops[i].rs1) emit_loadreg(dops[i].rs1,t);
57871462 2370 emit_slti32(t,imm[i],t);
2371 }else{
2372 emit_slti32(sl,imm[i],t);
2373 }
2374 }
2375 else { // SLTIU
2376 if(sl<0) {
cf95b4f0 2377 if(i_regs->regmap_entry[t]!=dops[i].rs1) emit_loadreg(dops[i].rs1,t);
57871462 2378 emit_sltiu32(t,imm[i],t);
2379 }else{
2380 emit_sltiu32(sl,imm[i],t);
2381 }
2382 }
57871462 2383 }else{
2384 // SLTI(U) with r0 is just stupid,
2385 // nonetheless examples can be found
cf95b4f0 2386 if(dops[i].opcode==0x0a) // SLTI
57871462 2387 if(0<imm[i]) emit_movimm(1,t);
2388 else emit_zeroreg(t);
2389 else // SLTIU
2390 {
2391 if(imm[i]) emit_movimm(1,t);
2392 else emit_zeroreg(t);
2393 }
2394 }
2395 }
2396 }
2397 }
cf95b4f0 2398 else if(dops[i].opcode>=0x0c&&dops[i].opcode<=0x0e) { // ANDI/ORI/XORI
2399 if(dops[i].rt1) {
7c3a5182 2400 signed char sl,tl;
cf95b4f0 2401 tl=get_reg(i_regs->regmap,dops[i].rt1);
2402 sl=get_reg(i_regs->regmap,dops[i].rs1);
57871462 2403 if(tl>=0 && !((i_regs->isconst>>tl)&1)) {
cf95b4f0 2404 if(dops[i].opcode==0x0c) //ANDI
57871462 2405 {
cf95b4f0 2406 if(dops[i].rs1) {
57871462 2407 if(sl<0) {
cf95b4f0 2408 if(i_regs->regmap_entry[tl]!=dops[i].rs1) emit_loadreg(dops[i].rs1,tl);
57871462 2409 emit_andimm(tl,imm[i],tl);
2410 }else{
2411 if(!((i_regs->wasconst>>sl)&1))
2412 emit_andimm(sl,imm[i],tl);
2413 else
2414 emit_movimm(constmap[i][sl]&imm[i],tl);
2415 }
2416 }
2417 else
2418 emit_zeroreg(tl);
57871462 2419 }
2420 else
2421 {
cf95b4f0 2422 if(dops[i].rs1) {
57871462 2423 if(sl<0) {
cf95b4f0 2424 if(i_regs->regmap_entry[tl]!=dops[i].rs1) emit_loadreg(dops[i].rs1,tl);
57871462 2425 }
cf95b4f0 2426 if(dops[i].opcode==0x0d) { // ORI
581335b0 2427 if(sl<0) {
2428 emit_orimm(tl,imm[i],tl);
2429 }else{
2430 if(!((i_regs->wasconst>>sl)&1))
2431 emit_orimm(sl,imm[i],tl);
2432 else
2433 emit_movimm(constmap[i][sl]|imm[i],tl);
2434 }
57871462 2435 }
cf95b4f0 2436 if(dops[i].opcode==0x0e) { // XORI
581335b0 2437 if(sl<0) {
2438 emit_xorimm(tl,imm[i],tl);
2439 }else{
2440 if(!((i_regs->wasconst>>sl)&1))
2441 emit_xorimm(sl,imm[i],tl);
2442 else
2443 emit_movimm(constmap[i][sl]^imm[i],tl);
2444 }
57871462 2445 }
2446 }
2447 else {
2448 emit_movimm(imm[i],tl);
57871462 2449 }
2450 }
2451 }
2452 }
2453 }
2454}
2455
2330734f 2456static void shiftimm_assemble(int i, const struct regstat *i_regs)
57871462 2457{
cf95b4f0 2458 if(dops[i].opcode2<=0x3) // SLL/SRL/SRA
57871462 2459 {
cf95b4f0 2460 if(dops[i].rt1) {
57871462 2461 signed char s,t;
cf95b4f0 2462 t=get_reg(i_regs->regmap,dops[i].rt1);
2463 s=get_reg(i_regs->regmap,dops[i].rs1);
57871462 2464 //assert(t>=0);
dc49e339 2465 if(t>=0&&!((i_regs->isconst>>t)&1)){
cf95b4f0 2466 if(dops[i].rs1==0)
57871462 2467 {
2468 emit_zeroreg(t);
2469 }
2470 else
2471 {
cf95b4f0 2472 if(s<0&&i_regs->regmap_entry[t]!=dops[i].rs1) emit_loadreg(dops[i].rs1,t);
57871462 2473 if(imm[i]) {
cf95b4f0 2474 if(dops[i].opcode2==0) // SLL
57871462 2475 {
2476 emit_shlimm(s<0?t:s,imm[i],t);
2477 }
cf95b4f0 2478 if(dops[i].opcode2==2) // SRL
57871462 2479 {
2480 emit_shrimm(s<0?t:s,imm[i],t);
2481 }
cf95b4f0 2482 if(dops[i].opcode2==3) // SRA
57871462 2483 {
2484 emit_sarimm(s<0?t:s,imm[i],t);
2485 }
2486 }else{
2487 // Shift by zero
2488 if(s>=0 && s!=t) emit_mov(s,t);
2489 }
2490 }
2491 }
cf95b4f0 2492 //emit_storereg(dops[i].rt1,t); //DEBUG
57871462 2493 }
2494 }
cf95b4f0 2495 if(dops[i].opcode2>=0x38&&dops[i].opcode2<=0x3b) // DSLL/DSRL/DSRA
57871462 2496 {
9c45ca93 2497 assert(0);
57871462 2498 }
cf95b4f0 2499 if(dops[i].opcode2==0x3c) // DSLL32
57871462 2500 {
9c45ca93 2501 assert(0);
57871462 2502 }
cf95b4f0 2503 if(dops[i].opcode2==0x3e) // DSRL32
57871462 2504 {
9c45ca93 2505 assert(0);
57871462 2506 }
cf95b4f0 2507 if(dops[i].opcode2==0x3f) // DSRA32
57871462 2508 {
9c45ca93 2509 assert(0);
57871462 2510 }
2511}
2512
2513#ifndef shift_assemble
2330734f 2514static void shift_assemble(int i, const struct regstat *i_regs)
57871462 2515{
3968e69e 2516 signed char s,t,shift;
cf95b4f0 2517 if (dops[i].rt1 == 0)
3968e69e 2518 return;
cf95b4f0 2519 assert(dops[i].opcode2<=0x07); // SLLV/SRLV/SRAV
2520 t = get_reg(i_regs->regmap, dops[i].rt1);
2521 s = get_reg(i_regs->regmap, dops[i].rs1);
2522 shift = get_reg(i_regs->regmap, dops[i].rs2);
3968e69e 2523 if (t < 0)
2524 return;
2525
cf95b4f0 2526 if(dops[i].rs1==0)
3968e69e 2527 emit_zeroreg(t);
cf95b4f0 2528 else if(dops[i].rs2==0) {
3968e69e 2529 assert(s>=0);
2530 if(s!=t) emit_mov(s,t);
2531 }
2532 else {
2533 host_tempreg_acquire();
2534 emit_andimm(shift,31,HOST_TEMPREG);
cf95b4f0 2535 switch(dops[i].opcode2) {
3968e69e 2536 case 4: // SLLV
2537 emit_shl(s,HOST_TEMPREG,t);
2538 break;
2539 case 6: // SRLV
2540 emit_shr(s,HOST_TEMPREG,t);
2541 break;
2542 case 7: // SRAV
2543 emit_sar(s,HOST_TEMPREG,t);
2544 break;
2545 default:
2546 assert(0);
2547 }
2548 host_tempreg_release();
2549 }
57871462 2550}
3968e69e 2551
57871462 2552#endif
2553
8062d65a 2554enum {
2555 MTYPE_8000 = 0,
2556 MTYPE_8020,
2557 MTYPE_0000,
2558 MTYPE_A000,
2559 MTYPE_1F80,
2560};
2561
2562static int get_ptr_mem_type(u_int a)
2563{
2564 if(a < 0x00200000) {
2565 if(a<0x1000&&((start>>20)==0xbfc||(start>>24)==0xa0))
2566 // return wrong, must use memhandler for BIOS self-test to pass
2567 // 007 does similar stuff from a00 mirror, weird stuff
2568 return MTYPE_8000;
2569 return MTYPE_0000;
2570 }
2571 if(0x1f800000 <= a && a < 0x1f801000)
2572 return MTYPE_1F80;
2573 if(0x80200000 <= a && a < 0x80800000)
2574 return MTYPE_8020;
2575 if(0xa0000000 <= a && a < 0xa0200000)
2576 return MTYPE_A000;
2577 return MTYPE_8000;
2578}
2579
37387d8b 2580static int get_ro_reg(const struct regstat *i_regs, int host_tempreg_free)
2581{
2582 int r = get_reg(i_regs->regmap, ROREG);
2583 if (r < 0 && host_tempreg_free) {
2584 host_tempreg_acquire();
2585 emit_loadreg(ROREG, r = HOST_TEMPREG);
2586 }
2587 if (r < 0)
2588 abort();
2589 return r;
2590}
2591
2592static void *emit_fastpath_cmp_jump(int i, const struct regstat *i_regs,
2593 int addr, int *offset_reg, int *addr_reg_override)
8062d65a 2594{
2595 void *jaddr = NULL;
37387d8b 2596 int type = 0;
2597 int mr = dops[i].rs1;
2598 *offset_reg = -1;
8062d65a 2599 if(((smrv_strong|smrv_weak)>>mr)&1) {
2600 type=get_ptr_mem_type(smrv[mr]);
2601 //printf("set %08x @%08x r%d %d\n", smrv[mr], start+i*4, mr, type);
2602 }
2603 else {
2604 // use the mirror we are running on
2605 type=get_ptr_mem_type(start);
2606 //printf("set nospec @%08x r%d %d\n", start+i*4, mr, type);
2607 }
2608
2609 if(type==MTYPE_8020) { // RAM 80200000+ mirror
d1e4ebd9 2610 host_tempreg_acquire();
8062d65a 2611 emit_andimm(addr,~0x00e00000,HOST_TEMPREG);
2612 addr=*addr_reg_override=HOST_TEMPREG;
2613 type=0;
2614 }
2615 else if(type==MTYPE_0000) { // RAM 0 mirror
d1e4ebd9 2616 host_tempreg_acquire();
8062d65a 2617 emit_orimm(addr,0x80000000,HOST_TEMPREG);
2618 addr=*addr_reg_override=HOST_TEMPREG;
2619 type=0;
2620 }
2621 else if(type==MTYPE_A000) { // RAM A mirror
d1e4ebd9 2622 host_tempreg_acquire();
8062d65a 2623 emit_andimm(addr,~0x20000000,HOST_TEMPREG);
2624 addr=*addr_reg_override=HOST_TEMPREG;
2625 type=0;
2626 }
2627 else if(type==MTYPE_1F80) { // scratchpad
2628 if (psxH == (void *)0x1f800000) {
d1e4ebd9 2629 host_tempreg_acquire();
3968e69e 2630 emit_xorimm(addr,0x1f800000,HOST_TEMPREG);
8062d65a 2631 emit_cmpimm(HOST_TEMPREG,0x1000);
d1e4ebd9 2632 host_tempreg_release();
8062d65a 2633 jaddr=out;
2634 emit_jc(0);
2635 }
2636 else {
2637 // do the usual RAM check, jump will go to the right handler
2638 type=0;
2639 }
2640 }
2641
37387d8b 2642 if (type == 0) // need ram check
8062d65a 2643 {
2644 emit_cmpimm(addr,RAM_SIZE);
37387d8b 2645 jaddr = out;
8062d65a 2646 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
2647 // Hint to branch predictor that the branch is unlikely to be taken
37387d8b 2648 if (dops[i].rs1 >= 28)
8062d65a 2649 emit_jno_unlikely(0);
2650 else
2651 #endif
2652 emit_jno(0);
37387d8b 2653 if (ram_offset != 0)
2654 *offset_reg = get_ro_reg(i_regs, 0);
8062d65a 2655 }
2656
2657 return jaddr;
2658}
2659
687b4580 2660// return memhandler, or get directly accessable address and return 0
2661static void *get_direct_memhandler(void *table, u_int addr,
2662 enum stub_type type, uintptr_t *addr_host)
2663{
c979e8c2 2664 uintptr_t msb = 1ull << (sizeof(uintptr_t)*8 - 1);
687b4580 2665 uintptr_t l1, l2 = 0;
2666 l1 = ((uintptr_t *)table)[addr>>12];
c979e8c2 2667 if (!(l1 & msb)) {
687b4580 2668 uintptr_t v = l1 << 1;
2669 *addr_host = v + addr;
2670 return NULL;
2671 }
2672 else {
2673 l1 <<= 1;
2674 if (type == LOADB_STUB || type == LOADBU_STUB || type == STOREB_STUB)
2675 l2 = ((uintptr_t *)l1)[0x1000/4 + 0x1000/2 + (addr&0xfff)];
2676 else if (type == LOADH_STUB || type == LOADHU_STUB || type == STOREH_STUB)
c979e8c2 2677 l2 = ((uintptr_t *)l1)[0x1000/4 + (addr&0xfff)/2];
687b4580 2678 else
c979e8c2 2679 l2 = ((uintptr_t *)l1)[(addr&0xfff)/4];
2680 if (!(l2 & msb)) {
687b4580 2681 uintptr_t v = l2 << 1;
2682 *addr_host = v + (addr&0xfff);
2683 return NULL;
2684 }
2685 return (void *)(l2 << 1);
2686 }
2687}
2688
81dbbf4c 2689static u_int get_host_reglist(const signed char *regmap)
2690{
2691 u_int reglist = 0, hr;
2692 for (hr = 0; hr < HOST_REGS; hr++) {
2693 if (hr != EXCLUDE_REG && regmap[hr] >= 0)
2694 reglist |= 1 << hr;
2695 }
2696 return reglist;
2697}
2698
2699static u_int reglist_exclude(u_int reglist, int r1, int r2)
2700{
2701 if (r1 >= 0)
2702 reglist &= ~(1u << r1);
2703 if (r2 >= 0)
2704 reglist &= ~(1u << r2);
2705 return reglist;
2706}
2707
e3c6bdb5 2708// find a temp caller-saved register not in reglist (so assumed to be free)
2709static int reglist_find_free(u_int reglist)
2710{
2711 u_int free_regs = ~reglist & CALLER_SAVE_REGS;
2712 if (free_regs == 0)
2713 return -1;
2714 return __builtin_ctz(free_regs);
2715}
2716
37387d8b 2717static void do_load_word(int a, int rt, int offset_reg)
2718{
2719 if (offset_reg >= 0)
2720 emit_ldr_dualindexed(offset_reg, a, rt);
2721 else
2722 emit_readword_indexed(0, a, rt);
2723}
2724
2725static void do_store_word(int a, int ofs, int rt, int offset_reg, int preseve_a)
2726{
2727 if (offset_reg < 0) {
2728 emit_writeword_indexed(rt, ofs, a);
2729 return;
2730 }
2731 if (ofs != 0)
2732 emit_addimm(a, ofs, a);
2733 emit_str_dualindexed(offset_reg, a, rt);
2734 if (ofs != 0 && preseve_a)
2735 emit_addimm(a, -ofs, a);
2736}
2737
2738static void do_store_hword(int a, int ofs, int rt, int offset_reg, int preseve_a)
2739{
2740 if (offset_reg < 0) {
2741 emit_writehword_indexed(rt, ofs, a);
2742 return;
2743 }
2744 if (ofs != 0)
2745 emit_addimm(a, ofs, a);
2746 emit_strh_dualindexed(offset_reg, a, rt);
2747 if (ofs != 0 && preseve_a)
2748 emit_addimm(a, -ofs, a);
2749}
2750
2751static void do_store_byte(int a, int rt, int offset_reg)
2752{
2753 if (offset_reg >= 0)
2754 emit_strb_dualindexed(offset_reg, a, rt);
2755 else
2756 emit_writebyte_indexed(rt, 0, a);
2757}
2758
2330734f 2759static void load_assemble(int i, const struct regstat *i_regs, int ccadj_)
57871462 2760{
7c3a5182 2761 int s,tl,addr;
57871462 2762 int offset;
b14b6a8f 2763 void *jaddr=0;
5bf843dc 2764 int memtarget=0,c=0;
37387d8b 2765 int offset_reg = -1;
2766 int fastio_reg_override = -1;
81dbbf4c 2767 u_int reglist=get_host_reglist(i_regs->regmap);
cf95b4f0 2768 tl=get_reg(i_regs->regmap,dops[i].rt1);
2769 s=get_reg(i_regs->regmap,dops[i].rs1);
57871462 2770 offset=imm[i];
57871462 2771 if(i_regs->regmap[HOST_CCREG]==CCREG) reglist&=~(1<<HOST_CCREG);
2772 if(s>=0) {
2773 c=(i_regs->wasconst>>s)&1;
af4ee1fe 2774 if (c) {
2775 memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
af4ee1fe 2776 }
57871462 2777 }
57871462 2778 //printf("load_assemble: c=%d\n",c);
643aeae3 2779 //if(c) printf("load_assemble: const=%lx\n",(long)constmap[i][s]+offset);
57871462 2780 // FIXME: Even if the load is a NOP, we should check for pagefaults...
581335b0 2781 if((tl<0&&(!c||(((u_int)constmap[i][s]+offset)>>16)==0x1f80))
cf95b4f0 2782 ||dops[i].rt1==0) {
5bf843dc 2783 // could be FIFO, must perform the read
f18c0f46 2784 // ||dummy read
5bf843dc 2785 assem_debug("(forced read)\n");
2786 tl=get_reg(i_regs->regmap,-1);
2787 assert(tl>=0);
5bf843dc 2788 }
2789 if(offset||s<0||c) addr=tl;
2790 else addr=s;
535d208a 2791 //if(tl<0) tl=get_reg(i_regs->regmap,-1);
2792 if(tl>=0) {
2793 //printf("load_assemble: c=%d\n",c);
643aeae3 2794 //if(c) printf("load_assemble: const=%lx\n",(long)constmap[i][s]+offset);
535d208a 2795 assert(tl>=0); // Even if the load is a NOP, we must check for pagefaults and I/O
2796 reglist&=~(1<<tl);
1edfcc68 2797 if(!c) {
1edfcc68 2798 #ifdef R29_HACK
2799 // Strmnnrmn's speed hack
cf95b4f0 2800 if(dops[i].rs1!=29||start<0x80001000||start>=0x80000000+RAM_SIZE)
1edfcc68 2801 #endif
2802 {
37387d8b 2803 jaddr = emit_fastpath_cmp_jump(i, i_regs, addr,
2804 &offset_reg, &fastio_reg_override);
535d208a 2805 }
1edfcc68 2806 }
37387d8b 2807 else if (ram_offset && memtarget) {
2808 offset_reg = get_ro_reg(i_regs, 0);
535d208a 2809 }
cf95b4f0 2810 int dummy=(dops[i].rt1==0)||(tl!=get_reg(i_regs->regmap,dops[i].rt1)); // ignore loads to r0 and unneeded reg
37387d8b 2811 switch (dops[i].opcode) {
2812 case 0x20: // LB
535d208a 2813 if(!c||memtarget) {
2814 if(!dummy) {
37387d8b 2815 int a = tl;
2816 if (!c) a = addr;
2817 if (fastio_reg_override >= 0)
2818 a = fastio_reg_override;
b1570849 2819
37387d8b 2820 if (offset_reg >= 0)
2821 emit_ldrsb_dualindexed(offset_reg, a, tl);
2822 else
2823 emit_movsbl_indexed(0, a, tl);
57871462 2824 }
535d208a 2825 if(jaddr)
2330734f 2826 add_stub_r(LOADB_STUB,jaddr,out,i,addr,i_regs,ccadj_,reglist);
57871462 2827 }
535d208a 2828 else
2330734f 2829 inline_readstub(LOADB_STUB,i,constmap[i][s]+offset,i_regs->regmap,dops[i].rt1,ccadj_,reglist);
37387d8b 2830 break;
2831 case 0x21: // LH
535d208a 2832 if(!c||memtarget) {
2833 if(!dummy) {
37387d8b 2834 int a = tl;
2835 if (!c) a = addr;
2836 if (fastio_reg_override >= 0)
2837 a = fastio_reg_override;
2838 if (offset_reg >= 0)
2839 emit_ldrsh_dualindexed(offset_reg, a, tl);
2840 else
2841 emit_movswl_indexed(0, a, tl);
57871462 2842 }
535d208a 2843 if(jaddr)
2330734f 2844 add_stub_r(LOADH_STUB,jaddr,out,i,addr,i_regs,ccadj_,reglist);
57871462 2845 }
535d208a 2846 else
2330734f 2847 inline_readstub(LOADH_STUB,i,constmap[i][s]+offset,i_regs->regmap,dops[i].rt1,ccadj_,reglist);
37387d8b 2848 break;
2849 case 0x23: // LW
535d208a 2850 if(!c||memtarget) {
2851 if(!dummy) {
37387d8b 2852 int a = addr;
2853 if (fastio_reg_override >= 0)
2854 a = fastio_reg_override;
2855 do_load_word(a, tl, offset_reg);
57871462 2856 }
535d208a 2857 if(jaddr)
2330734f 2858 add_stub_r(LOADW_STUB,jaddr,out,i,addr,i_regs,ccadj_,reglist);
57871462 2859 }
535d208a 2860 else
2330734f 2861 inline_readstub(LOADW_STUB,i,constmap[i][s]+offset,i_regs->regmap,dops[i].rt1,ccadj_,reglist);
37387d8b 2862 break;
2863 case 0x24: // LBU
535d208a 2864 if(!c||memtarget) {
2865 if(!dummy) {
37387d8b 2866 int a = tl;
2867 if (!c) a = addr;
2868 if (fastio_reg_override >= 0)
2869 a = fastio_reg_override;
b1570849 2870
37387d8b 2871 if (offset_reg >= 0)
2872 emit_ldrb_dualindexed(offset_reg, a, tl);
2873 else
2874 emit_movzbl_indexed(0, a, tl);
57871462 2875 }
535d208a 2876 if(jaddr)
2330734f 2877 add_stub_r(LOADBU_STUB,jaddr,out,i,addr,i_regs,ccadj_,reglist);
57871462 2878 }
535d208a 2879 else
2330734f 2880 inline_readstub(LOADBU_STUB,i,constmap[i][s]+offset,i_regs->regmap,dops[i].rt1,ccadj_,reglist);
37387d8b 2881 break;
2882 case 0x25: // LHU
535d208a 2883 if(!c||memtarget) {
2884 if(!dummy) {
37387d8b 2885 int a = tl;
2886 if(!c) a = addr;
2887 if (fastio_reg_override >= 0)
2888 a = fastio_reg_override;
2889 if (offset_reg >= 0)
2890 emit_ldrh_dualindexed(offset_reg, a, tl);
2891 else
2892 emit_movzwl_indexed(0, a, tl);
57871462 2893 }
535d208a 2894 if(jaddr)
2330734f 2895 add_stub_r(LOADHU_STUB,jaddr,out,i,addr,i_regs,ccadj_,reglist);
57871462 2896 }
535d208a 2897 else
2330734f 2898 inline_readstub(LOADHU_STUB,i,constmap[i][s]+offset,i_regs->regmap,dops[i].rt1,ccadj_,reglist);
37387d8b 2899 break;
2900 case 0x27: // LWU
2901 case 0x37: // LD
2902 default:
9c45ca93 2903 assert(0);
57871462 2904 }
535d208a 2905 }
37387d8b 2906 if (fastio_reg_override == HOST_TEMPREG || offset_reg == HOST_TEMPREG)
d1e4ebd9 2907 host_tempreg_release();
57871462 2908}
2909
2910#ifndef loadlr_assemble
2330734f 2911static void loadlr_assemble(int i, const struct regstat *i_regs, int ccadj_)
57871462 2912{
3968e69e 2913 int s,tl,temp,temp2,addr;
2914 int offset;
2915 void *jaddr=0;
2916 int memtarget=0,c=0;
37387d8b 2917 int offset_reg = -1;
2918 int fastio_reg_override = -1;
81dbbf4c 2919 u_int reglist=get_host_reglist(i_regs->regmap);
cf95b4f0 2920 tl=get_reg(i_regs->regmap,dops[i].rt1);
2921 s=get_reg(i_regs->regmap,dops[i].rs1);
3968e69e 2922 temp=get_reg(i_regs->regmap,-1);
2923 temp2=get_reg(i_regs->regmap,FTEMP);
2924 addr=get_reg(i_regs->regmap,AGEN1+(i&1));
2925 assert(addr<0);
2926 offset=imm[i];
3968e69e 2927 reglist|=1<<temp;
2928 if(offset||s<0||c) addr=temp2;
2929 else addr=s;
2930 if(s>=0) {
2931 c=(i_regs->wasconst>>s)&1;
2932 if(c) {
2933 memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
2934 }
2935 }
2936 if(!c) {
2937 emit_shlimm(addr,3,temp);
cf95b4f0 2938 if (dops[i].opcode==0x22||dops[i].opcode==0x26) {
3968e69e 2939 emit_andimm(addr,0xFFFFFFFC,temp2); // LWL/LWR
2940 }else{
2941 emit_andimm(addr,0xFFFFFFF8,temp2); // LDL/LDR
2942 }
37387d8b 2943 jaddr = emit_fastpath_cmp_jump(i, i_regs, temp2,
2944 &offset_reg, &fastio_reg_override);
3968e69e 2945 }
2946 else {
37387d8b 2947 if (ram_offset && memtarget) {
2948 offset_reg = get_ro_reg(i_regs, 0);
3968e69e 2949 }
cf95b4f0 2950 if (dops[i].opcode==0x22||dops[i].opcode==0x26) {
3968e69e 2951 emit_movimm(((constmap[i][s]+offset)<<3)&24,temp); // LWL/LWR
2952 }else{
2953 emit_movimm(((constmap[i][s]+offset)<<3)&56,temp); // LDL/LDR
2954 }
2955 }
cf95b4f0 2956 if (dops[i].opcode==0x22||dops[i].opcode==0x26) { // LWL/LWR
3968e69e 2957 if(!c||memtarget) {
37387d8b 2958 int a = temp2;
2959 if (fastio_reg_override >= 0)
2960 a = fastio_reg_override;
2961 do_load_word(a, temp2, offset_reg);
2962 if (fastio_reg_override == HOST_TEMPREG || offset_reg == HOST_TEMPREG)
2963 host_tempreg_release();
2330734f 2964 if(jaddr) add_stub_r(LOADW_STUB,jaddr,out,i,temp2,i_regs,ccadj_,reglist);
3968e69e 2965 }
2966 else
2330734f 2967 inline_readstub(LOADW_STUB,i,(constmap[i][s]+offset)&0xFFFFFFFC,i_regs->regmap,FTEMP,ccadj_,reglist);
cf95b4f0 2968 if(dops[i].rt1) {
3968e69e 2969 assert(tl>=0);
2970 emit_andimm(temp,24,temp);
cf95b4f0 2971 if (dops[i].opcode==0x22) // LWL
3968e69e 2972 emit_xorimm(temp,24,temp);
2973 host_tempreg_acquire();
2974 emit_movimm(-1,HOST_TEMPREG);
cf95b4f0 2975 if (dops[i].opcode==0x26) {
3968e69e 2976 emit_shr(temp2,temp,temp2);
2977 emit_bic_lsr(tl,HOST_TEMPREG,temp,tl);
2978 }else{
2979 emit_shl(temp2,temp,temp2);
2980 emit_bic_lsl(tl,HOST_TEMPREG,temp,tl);
2981 }
2982 host_tempreg_release();
2983 emit_or(temp2,tl,tl);
2984 }
cf95b4f0 2985 //emit_storereg(dops[i].rt1,tl); // DEBUG
3968e69e 2986 }
cf95b4f0 2987 if (dops[i].opcode==0x1A||dops[i].opcode==0x1B) { // LDL/LDR
3968e69e 2988 assert(0);
2989 }
57871462 2990}
2991#endif
2992
2330734f 2993static void store_assemble(int i, const struct regstat *i_regs, int ccadj_)
57871462 2994{
9c45ca93 2995 int s,tl;
57871462 2996 int addr,temp;
2997 int offset;
b14b6a8f 2998 void *jaddr=0;
37387d8b 2999 enum stub_type type=0;
666a299d 3000 int memtarget=0,c=0;
57871462 3001 int agr=AGEN1+(i&1);
37387d8b 3002 int offset_reg = -1;
3003 int fastio_reg_override = -1;
81dbbf4c 3004 u_int reglist=get_host_reglist(i_regs->regmap);
cf95b4f0 3005 tl=get_reg(i_regs->regmap,dops[i].rs2);
3006 s=get_reg(i_regs->regmap,dops[i].rs1);
57871462 3007 temp=get_reg(i_regs->regmap,agr);
3008 if(temp<0) temp=get_reg(i_regs->regmap,-1);
3009 offset=imm[i];
3010 if(s>=0) {
3011 c=(i_regs->wasconst>>s)&1;
af4ee1fe 3012 if(c) {
3013 memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
af4ee1fe 3014 }
57871462 3015 }
3016 assert(tl>=0);
3017 assert(temp>=0);
57871462 3018 if(i_regs->regmap[HOST_CCREG]==CCREG) reglist&=~(1<<HOST_CCREG);
3019 if(offset||s<0||c) addr=temp;
3020 else addr=s;
37387d8b 3021 if (!c) {
3022 jaddr = emit_fastpath_cmp_jump(i, i_regs, addr,
3023 &offset_reg, &fastio_reg_override);
1edfcc68 3024 }
37387d8b 3025 else if (ram_offset && memtarget) {
3026 offset_reg = get_ro_reg(i_regs, 0);
57871462 3027 }
3028
37387d8b 3029 switch (dops[i].opcode) {
3030 case 0x28: // SB
57871462 3031 if(!c||memtarget) {
37387d8b 3032 int a = temp;
3033 if (!c) a = addr;
3034 if (fastio_reg_override >= 0)
3035 a = fastio_reg_override;
3036 do_store_byte(a, tl, offset_reg);
3037 }
3038 type = STOREB_STUB;
3039 break;
3040 case 0x29: // SH
57871462 3041 if(!c||memtarget) {
37387d8b 3042 int a = temp;
3043 if (!c) a = addr;
3044 if (fastio_reg_override >= 0)
3045 a = fastio_reg_override;
3046 do_store_hword(a, 0, tl, offset_reg, 1);
3047 }
3048 type = STOREH_STUB;
3049 break;
3050 case 0x2B: // SW
dadf55f2 3051 if(!c||memtarget) {
37387d8b 3052 int a = addr;
3053 if (fastio_reg_override >= 0)
3054 a = fastio_reg_override;
3055 do_store_word(a, 0, tl, offset_reg, 1);
3056 }
3057 type = STOREW_STUB;
3058 break;
3059 case 0x3F: // SD
3060 default:
9c45ca93 3061 assert(0);
57871462 3062 }
37387d8b 3063 if (fastio_reg_override == HOST_TEMPREG || offset_reg == HOST_TEMPREG)
d1e4ebd9 3064 host_tempreg_release();
b96d3df7 3065 if(jaddr) {
3066 // PCSX store handlers don't check invcode again
3067 reglist|=1<<addr;
2330734f 3068 add_stub_r(type,jaddr,out,i,addr,i_regs,ccadj_,reglist);
b96d3df7 3069 jaddr=0;
3070 }
cf95b4f0 3071 if(!(i_regs->waswritten&(1<<dops[i].rs1)) && !HACK_ENABLED(NDHACK_NO_SMC_CHECK)) {
57871462 3072 if(!c||memtarget) {
3073 #ifdef DESTRUCTIVE_SHIFT
3074 // The x86 shift operation is 'destructive'; it overwrites the
3075 // source register, so we need to make a copy first and use that.
3076 addr=temp;
3077 #endif
3078 #if defined(HOST_IMM8)
3079 int ir=get_reg(i_regs->regmap,INVCP);
3080 assert(ir>=0);
3081 emit_cmpmem_indexedsr12_reg(ir,addr,1);
3082 #else
643aeae3 3083 emit_cmpmem_indexedsr12_imm(invalid_code,addr,1);
57871462 3084 #endif
0bbd1454 3085 #if defined(HAVE_CONDITIONAL_CALL) && !defined(DESTRUCTIVE_SHIFT)
3086 emit_callne(invalidate_addr_reg[addr]);
3087 #else
b14b6a8f 3088 void *jaddr2 = out;
57871462 3089 emit_jne(0);
b14b6a8f 3090 add_stub(INVCODE_STUB,jaddr2,out,reglist|(1<<HOST_CCREG),addr,0,0,0);
0bbd1454 3091 #endif
57871462 3092 }
3093 }
7a518516 3094 u_int addr_val=constmap[i][s]+offset;
3eaa7048 3095 if(jaddr) {
2330734f 3096 add_stub_r(type,jaddr,out,i,addr,i_regs,ccadj_,reglist);
3eaa7048 3097 } else if(c&&!memtarget) {
2330734f 3098 inline_writestub(type,i,addr_val,i_regs->regmap,dops[i].rs2,ccadj_,reglist);
7a518516 3099 }
3100 // basic current block modification detection..
3101 // not looking back as that should be in mips cache already
3968e69e 3102 // (see Spyro2 title->attract mode)
7a518516 3103 if(c&&start+i*4<addr_val&&addr_val<start+slen*4) {
c43b5311 3104 SysPrintf("write to %08x hits block %08x, pc=%08x\n",addr_val,start,start+i*4);
7a518516 3105 assert(i_regs->regmap==regs[i].regmap); // not delay slot
3106 if(i_regs->regmap==regs[i].regmap) {
ad49de89 3107 load_all_consts(regs[i].regmap_entry,regs[i].wasdirty,i);
3108 wb_dirtys(regs[i].regmap_entry,regs[i].wasdirty);
7a518516 3109 emit_movimm(start+i*4+4,0);
643aeae3 3110 emit_writeword(0,&pcaddr);
d1e4ebd9 3111 emit_addimm(HOST_CCREG,2,HOST_CCREG);
2a014d73 3112 emit_far_call(get_addr_ht);
d1e4ebd9 3113 emit_jmpreg(0);
7a518516 3114 }
3eaa7048 3115 }
57871462 3116}
3117
2330734f 3118static void storelr_assemble(int i, const struct regstat *i_regs, int ccadj_)
57871462 3119{
9c45ca93 3120 int s,tl;
57871462 3121 int temp;
57871462 3122 int offset;
b14b6a8f 3123 void *jaddr=0;
37387d8b 3124 void *case1, *case23, *case3;
df4dc2b1 3125 void *done0, *done1, *done2;
af4ee1fe 3126 int memtarget=0,c=0;
fab5d06d 3127 int agr=AGEN1+(i&1);
37387d8b 3128 int offset_reg = -1;
81dbbf4c 3129 u_int reglist=get_host_reglist(i_regs->regmap);
cf95b4f0 3130 tl=get_reg(i_regs->regmap,dops[i].rs2);
3131 s=get_reg(i_regs->regmap,dops[i].rs1);
fab5d06d 3132 temp=get_reg(i_regs->regmap,agr);
3133 if(temp<0) temp=get_reg(i_regs->regmap,-1);
57871462 3134 offset=imm[i];
3135 if(s>=0) {
3136 c=(i_regs->isconst>>s)&1;
af4ee1fe 3137 if(c) {
3138 memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
af4ee1fe 3139 }
57871462 3140 }
3141 assert(tl>=0);
535d208a 3142 assert(temp>=0);
1edfcc68 3143 if(!c) {
3144 emit_cmpimm(s<0||offset?temp:s,RAM_SIZE);
3145 if(!offset&&s!=temp) emit_mov(s,temp);
b14b6a8f 3146 jaddr=out;
1edfcc68 3147 emit_jno(0);
3148 }
3149 else
3150 {
cf95b4f0 3151 if(!memtarget||!dops[i].rs1) {
b14b6a8f 3152 jaddr=out;
535d208a 3153 emit_jmp(0);
57871462 3154 }
535d208a 3155 }
37387d8b 3156 if (ram_offset)
3157 offset_reg = get_ro_reg(i_regs, 0);
535d208a 3158
cf95b4f0 3159 if (dops[i].opcode==0x2C||dops[i].opcode==0x2D) { // SDL/SDR
9c45ca93 3160 assert(0);
535d208a 3161 }
57871462 3162
535d208a 3163 emit_testimm(temp,2);
37387d8b 3164 case23=out;
535d208a 3165 emit_jne(0);
3166 emit_testimm(temp,1);
df4dc2b1 3167 case1=out;
535d208a 3168 emit_jne(0);
3169 // 0
37387d8b 3170 if (dops[i].opcode == 0x2A) { // SWL
3171 // Write msb into least significant byte
3172 if (dops[i].rs2) emit_rorimm(tl, 24, tl);
3173 do_store_byte(temp, tl, offset_reg);
3174 if (dops[i].rs2) emit_rorimm(tl, 8, tl);
535d208a 3175 }
37387d8b 3176 else if (dops[i].opcode == 0x2E) { // SWR
3177 // Write entire word
3178 do_store_word(temp, 0, tl, offset_reg, 1);
535d208a 3179 }
37387d8b 3180 done0 = out;
535d208a 3181 emit_jmp(0);
3182 // 1
df4dc2b1 3183 set_jump_target(case1, out);
37387d8b 3184 if (dops[i].opcode == 0x2A) { // SWL
3185 // Write two msb into two least significant bytes
3186 if (dops[i].rs2) emit_rorimm(tl, 16, tl);
3187 do_store_hword(temp, -1, tl, offset_reg, 0);
3188 if (dops[i].rs2) emit_rorimm(tl, 16, tl);
535d208a 3189 }
37387d8b 3190 else if (dops[i].opcode == 0x2E) { // SWR
3191 // Write 3 lsb into three most significant bytes
3192 do_store_byte(temp, tl, offset_reg);
3193 if (dops[i].rs2) emit_rorimm(tl, 8, tl);
3194 do_store_hword(temp, 1, tl, offset_reg, 0);
3195 if (dops[i].rs2) emit_rorimm(tl, 24, tl);
535d208a 3196 }
df4dc2b1 3197 done1=out;
535d208a 3198 emit_jmp(0);
37387d8b 3199 // 2,3
3200 set_jump_target(case23, out);
535d208a 3201 emit_testimm(temp,1);
37387d8b 3202 case3 = out;
535d208a 3203 emit_jne(0);
37387d8b 3204 // 2
cf95b4f0 3205 if (dops[i].opcode==0x2A) { // SWL
37387d8b 3206 // Write 3 msb into three least significant bytes
3207 if (dops[i].rs2) emit_rorimm(tl, 8, tl);
3208 do_store_hword(temp, -2, tl, offset_reg, 1);
3209 if (dops[i].rs2) emit_rorimm(tl, 16, tl);
3210 do_store_byte(temp, tl, offset_reg);
3211 if (dops[i].rs2) emit_rorimm(tl, 8, tl);
535d208a 3212 }
37387d8b 3213 else if (dops[i].opcode == 0x2E) { // SWR
3214 // Write two lsb into two most significant bytes
3215 do_store_hword(temp, 0, tl, offset_reg, 1);
535d208a 3216 }
37387d8b 3217 done2 = out;
535d208a 3218 emit_jmp(0);
3219 // 3
df4dc2b1 3220 set_jump_target(case3, out);
37387d8b 3221 if (dops[i].opcode == 0x2A) { // SWL
3222 do_store_word(temp, -3, tl, offset_reg, 0);
535d208a 3223 }
37387d8b 3224 else if (dops[i].opcode == 0x2E) { // SWR
3225 do_store_byte(temp, tl, offset_reg);
535d208a 3226 }
df4dc2b1 3227 set_jump_target(done0, out);
3228 set_jump_target(done1, out);
3229 set_jump_target(done2, out);
37387d8b 3230 if (offset_reg == HOST_TEMPREG)
3231 host_tempreg_release();
535d208a 3232 if(!c||!memtarget)
2330734f 3233 add_stub_r(STORELR_STUB,jaddr,out,i,temp,i_regs,ccadj_,reglist);
cf95b4f0 3234 if(!(i_regs->waswritten&(1<<dops[i].rs1)) && !HACK_ENABLED(NDHACK_NO_SMC_CHECK)) {
57871462 3235 #if defined(HOST_IMM8)
3236 int ir=get_reg(i_regs->regmap,INVCP);
3237 assert(ir>=0);
3238 emit_cmpmem_indexedsr12_reg(ir,temp,1);
3239 #else
643aeae3 3240 emit_cmpmem_indexedsr12_imm(invalid_code,temp,1);
57871462 3241 #endif
535d208a 3242 #if defined(HAVE_CONDITIONAL_CALL) && !defined(DESTRUCTIVE_SHIFT)
3243 emit_callne(invalidate_addr_reg[temp]);
3244 #else
b14b6a8f 3245 void *jaddr2 = out;
57871462 3246 emit_jne(0);
b14b6a8f 3247 add_stub(INVCODE_STUB,jaddr2,out,reglist|(1<<HOST_CCREG),temp,0,0,0);
535d208a 3248 #endif
57871462 3249 }
57871462 3250}
3251
2330734f 3252static void cop0_assemble(int i, const struct regstat *i_regs, int ccadj_)
8062d65a 3253{
cf95b4f0 3254 if(dops[i].opcode2==0) // MFC0
8062d65a 3255 {
cf95b4f0 3256 signed char t=get_reg(i_regs->regmap,dops[i].rt1);
8062d65a 3257 u_int copr=(source[i]>>11)&0x1f;
3258 //assert(t>=0); // Why does this happen? OOT is weird
cf95b4f0 3259 if(t>=0&&dops[i].rt1!=0) {
8062d65a 3260 emit_readword(&reg_cop0[copr],t);
3261 }
3262 }
cf95b4f0 3263 else if(dops[i].opcode2==4) // MTC0
8062d65a 3264 {
cf95b4f0 3265 signed char s=get_reg(i_regs->regmap,dops[i].rs1);
8062d65a 3266 char copr=(source[i]>>11)&0x1f;
3267 assert(s>=0);
cf95b4f0 3268 wb_register(dops[i].rs1,i_regs->regmap,i_regs->dirty);
8062d65a 3269 if(copr==9||copr==11||copr==12||copr==13) {
3270 emit_readword(&last_count,HOST_TEMPREG);
3271 emit_loadreg(CCREG,HOST_CCREG); // TODO: do proper reg alloc
3272 emit_add(HOST_CCREG,HOST_TEMPREG,HOST_CCREG);
2330734f 3273 emit_addimm(HOST_CCREG,ccadj_,HOST_CCREG);
8062d65a 3274 emit_writeword(HOST_CCREG,&Count);
3275 }
3276 // What a mess. The status register (12) can enable interrupts,
3277 // so needs a special case to handle a pending interrupt.
3278 // The interrupt must be taken immediately, because a subsequent
3279 // instruction might disable interrupts again.
3280 if(copr==12||copr==13) {
3281 if (is_delayslot) {
3282 // burn cycles to cause cc_interrupt, which will
3283 // reschedule next_interupt. Relies on CCREG from above.
3284 assem_debug("MTC0 DS %d\n", copr);
3285 emit_writeword(HOST_CCREG,&last_count);
3286 emit_movimm(0,HOST_CCREG);
3287 emit_storereg(CCREG,HOST_CCREG);
cf95b4f0 3288 emit_loadreg(dops[i].rs1,1);
8062d65a 3289 emit_movimm(copr,0);
2a014d73 3290 emit_far_call(pcsx_mtc0_ds);
cf95b4f0 3291 emit_loadreg(dops[i].rs1,s);
8062d65a 3292 return;
3293 }
3294 emit_movimm(start+i*4+4,HOST_TEMPREG);
3295 emit_writeword(HOST_TEMPREG,&pcaddr);
3296 emit_movimm(0,HOST_TEMPREG);
3297 emit_writeword(HOST_TEMPREG,&pending_exception);
3298 }
8062d65a 3299 if(s==HOST_CCREG)
cf95b4f0 3300 emit_loadreg(dops[i].rs1,1);
8062d65a 3301 else if(s!=1)
3302 emit_mov(s,1);
3303 emit_movimm(copr,0);
2a014d73 3304 emit_far_call(pcsx_mtc0);
8062d65a 3305 if(copr==9||copr==11||copr==12||copr==13) {
3306 emit_readword(&Count,HOST_CCREG);
3307 emit_readword(&next_interupt,HOST_TEMPREG);
2330734f 3308 emit_addimm(HOST_CCREG,-ccadj_,HOST_CCREG);
8062d65a 3309 emit_sub(HOST_CCREG,HOST_TEMPREG,HOST_CCREG);
3310 emit_writeword(HOST_TEMPREG,&last_count);
3311 emit_storereg(CCREG,HOST_CCREG);
3312 }
3313 if(copr==12||copr==13) {
3314 assert(!is_delayslot);
3315 emit_readword(&pending_exception,14);
3316 emit_test(14,14);
d1e4ebd9 3317 void *jaddr = out;
3318 emit_jeq(0);
3319 emit_readword(&pcaddr, 0);
3320 emit_addimm(HOST_CCREG,2,HOST_CCREG);
2a014d73 3321 emit_far_call(get_addr_ht);
d1e4ebd9 3322 emit_jmpreg(0);
3323 set_jump_target(jaddr, out);
8062d65a 3324 }
cf95b4f0 3325 emit_loadreg(dops[i].rs1,s);
8062d65a 3326 }
3327 else
3328 {
cf95b4f0 3329 assert(dops[i].opcode2==0x10);
8062d65a 3330 //if((source[i]&0x3f)==0x10) // RFE
3331 {
3332 emit_readword(&Status,0);
3333 emit_andimm(0,0x3c,1);
3334 emit_andimm(0,~0xf,0);
3335 emit_orrshr_imm(1,2,0);
3336 emit_writeword(0,&Status);
3337 }
3338 }
3339}
3340
2330734f 3341static void cop1_unusable(int i, const struct regstat *i_regs)
8062d65a 3342{
3343 // XXX: should just just do the exception instead
3344 //if(!cop1_usable)
3345 {
3346 void *jaddr=out;
3347 emit_jmp(0);
3348 add_stub_r(FP_STUB,jaddr,out,i,0,i_regs,is_delayslot,0);
3349 }
3350}
3351
2330734f 3352static void cop1_assemble(int i, const struct regstat *i_regs)
8062d65a 3353{
3354 cop1_unusable(i, i_regs);
3355}
3356
2330734f 3357static void c1ls_assemble(int i, const struct regstat *i_regs)
57871462 3358{
3d624f89 3359 cop1_unusable(i, i_regs);
57871462 3360}
3361
8062d65a 3362// FP_STUB
3363static void do_cop1stub(int n)
3364{
3365 literal_pool(256);
3366 assem_debug("do_cop1stub %x\n",start+stubs[n].a*4);
3367 set_jump_target(stubs[n].addr, out);
3368 int i=stubs[n].a;
3369// int rs=stubs[n].b;
3370 struct regstat *i_regs=(struct regstat *)stubs[n].c;
3371 int ds=stubs[n].d;
3372 if(!ds) {
3373 load_all_consts(regs[i].regmap_entry,regs[i].wasdirty,i);
3374 //if(i_regs!=&regs[i]) printf("oops: regs[i]=%x i_regs=%x",(int)&regs[i],(int)i_regs);
3375 }
3376 //else {printf("fp exception in delay slot\n");}
3377 wb_dirtys(i_regs->regmap_entry,i_regs->wasdirty);
3378 if(regs[i].regmap_entry[HOST_CCREG]!=CCREG) emit_loadreg(CCREG,HOST_CCREG);
3379 emit_movimm(start+(i-ds)*4,EAX); // Get PC
2330734f 3380 emit_addimm(HOST_CCREG,ccadj[i],HOST_CCREG); // CHECK: is this right? There should probably be an extra cycle...
2a014d73 3381 emit_far_jump(ds?fp_exception_ds:fp_exception);
8062d65a 3382}
3383
e3c6bdb5 3384static int cop2_is_stalling_op(int i, int *cycles)
3385{
cf95b4f0 3386 if (dops[i].opcode == 0x3a) { // SWC2
e3c6bdb5 3387 *cycles = 0;
3388 return 1;
3389 }
cf95b4f0 3390 if (dops[i].itype == COP2 && (dops[i].opcode2 == 0 || dops[i].opcode2 == 2)) { // MFC2/CFC2
e3c6bdb5 3391 *cycles = 0;
3392 return 1;
3393 }
cf95b4f0 3394 if (dops[i].itype == C2OP) {
e3c6bdb5 3395 *cycles = gte_cycletab[source[i] & 0x3f];
3396 return 1;
3397 }
3398 // ... what about MTC2/CTC2/LWC2?
3399 return 0;
3400}
3401
3402#if 0
3403static void log_gte_stall(int stall, u_int cycle)
3404{
3405 if ((u_int)stall <= 44)
3406 printf("x stall %2d %u\n", stall, cycle + last_count);
e3c6bdb5 3407}
3408
3409static void emit_log_gte_stall(int i, int stall, u_int reglist)
3410{
3411 save_regs(reglist);
3412 if (stall > 0)
3413 emit_movimm(stall, 0);
3414 else
3415 emit_mov(HOST_TEMPREG, 0);
2330734f 3416 emit_addimm(HOST_CCREG, ccadj[i], 1);
e3c6bdb5 3417 emit_far_call(log_gte_stall);
3418 restore_regs(reglist);
3419}
3420#endif
3421
32631e6a 3422static void cop2_do_stall_check(u_int op, int i, const struct regstat *i_regs, u_int reglist)
81dbbf4c 3423{
e3c6bdb5 3424 int j = i, other_gte_op_cycles = -1, stall = -MAXBLOCK, cycles_passed;
3425 int rtmp = reglist_find_free(reglist);
3426
32631e6a 3427 if (HACK_ENABLED(NDHACK_NO_STALLS))
81dbbf4c 3428 return;
81dbbf4c 3429 if (get_reg(i_regs->regmap, CCREG) != HOST_CCREG) {
3430 // happens occasionally... cc evicted? Don't bother then
3431 //printf("no cc %08x\n", start + i*4);
3432 return;
3433 }
cf95b4f0 3434 if (!dops[i].bt) {
e3c6bdb5 3435 for (j = i - 1; j >= 0; j--) {
cf95b4f0 3436 //if (dops[j].is_ds) break;
3437 if (cop2_is_stalling_op(j, &other_gte_op_cycles) || dops[j].bt)
e3c6bdb5 3438 break;
2330734f 3439 if (j > 0 && ccadj[j - 1] > ccadj[j])
3440 break;
e3c6bdb5 3441 }
32631e6a 3442 j = max(j, 0);
e3c6bdb5 3443 }
2330734f 3444 cycles_passed = ccadj[i] - ccadj[j];
e3c6bdb5 3445 if (other_gte_op_cycles >= 0)
3446 stall = other_gte_op_cycles - cycles_passed;
3447 else if (cycles_passed >= 44)
3448 stall = 0; // can't stall
3449 if (stall == -MAXBLOCK && rtmp >= 0) {
3450 // unknown stall, do the expensive runtime check
32631e6a 3451 assem_debug("; cop2_do_stall_check\n");
e3c6bdb5 3452#if 0 // too slow
3453 save_regs(reglist);
3454 emit_movimm(gte_cycletab[op], 0);
2330734f 3455 emit_addimm(HOST_CCREG, ccadj[i], 1);
e3c6bdb5 3456 emit_far_call(call_gteStall);
3457 restore_regs(reglist);
3458#else
3459 host_tempreg_acquire();
3460 emit_readword(&psxRegs.gteBusyCycle, rtmp);
2330734f 3461 emit_addimm(rtmp, -ccadj[i], rtmp);
e3c6bdb5 3462 emit_sub(rtmp, HOST_CCREG, HOST_TEMPREG);
3463 emit_cmpimm(HOST_TEMPREG, 44);
3464 emit_cmovb_reg(rtmp, HOST_CCREG);
3465 //emit_log_gte_stall(i, 0, reglist);
3466 host_tempreg_release();
3467#endif
3468 }
3469 else if (stall > 0) {
3470 //emit_log_gte_stall(i, stall, reglist);
3471 emit_addimm(HOST_CCREG, stall, HOST_CCREG);
3472 }
3473
3474 // save gteBusyCycle, if needed
3475 if (gte_cycletab[op] == 0)
3476 return;
3477 other_gte_op_cycles = -1;
3478 for (j = i + 1; j < slen; j++) {
3479 if (cop2_is_stalling_op(j, &other_gte_op_cycles))
3480 break;
fe807a8a 3481 if (dops[j].is_jump) {
e3c6bdb5 3482 // check ds
3483 if (j + 1 < slen && cop2_is_stalling_op(j + 1, &other_gte_op_cycles))
3484 j++;
3485 break;
3486 }
3487 }
3488 if (other_gte_op_cycles >= 0)
3489 // will handle stall when assembling that op
3490 return;
2330734f 3491 cycles_passed = ccadj[min(j, slen -1)] - ccadj[i];
e3c6bdb5 3492 if (cycles_passed >= 44)
3493 return;
3494 assem_debug("; save gteBusyCycle\n");
3495 host_tempreg_acquire();
3496#if 0
3497 emit_readword(&last_count, HOST_TEMPREG);
3498 emit_add(HOST_TEMPREG, HOST_CCREG, HOST_TEMPREG);
2330734f 3499 emit_addimm(HOST_TEMPREG, ccadj[i], HOST_TEMPREG);
e3c6bdb5 3500 emit_addimm(HOST_TEMPREG, gte_cycletab[op]), HOST_TEMPREG);
3501 emit_writeword(HOST_TEMPREG, &psxRegs.gteBusyCycle);
3502#else
2330734f 3503 emit_addimm(HOST_CCREG, ccadj[i] + gte_cycletab[op], HOST_TEMPREG);
e3c6bdb5 3504 emit_writeword(HOST_TEMPREG, &psxRegs.gteBusyCycle);
3505#endif
3506 host_tempreg_release();
81dbbf4c 3507}
3508
32631e6a 3509static int is_mflohi(int i)
3510{
cf95b4f0 3511 return (dops[i].itype == MOV && (dops[i].rs1 == HIREG || dops[i].rs1 == LOREG));
32631e6a 3512}
3513
3514static int check_multdiv(int i, int *cycles)
3515{
cf95b4f0 3516 if (dops[i].itype != MULTDIV)
32631e6a 3517 return 0;
cf95b4f0 3518 if (dops[i].opcode2 == 0x18 || dops[i].opcode2 == 0x19) // MULT(U)
32631e6a 3519 *cycles = 11; // approx from 7 11 14
3520 else
3521 *cycles = 37;
3522 return 1;
3523}
3524
2330734f 3525static void multdiv_prepare_stall(int i, const struct regstat *i_regs, int ccadj_)
32631e6a 3526{
3527 int j, found = 0, c = 0;
3528 if (HACK_ENABLED(NDHACK_NO_STALLS))
3529 return;
3530 if (get_reg(i_regs->regmap, CCREG) != HOST_CCREG) {
3531 // happens occasionally... cc evicted? Don't bother then
3532 return;
3533 }
3534 for (j = i + 1; j < slen; j++) {
cf95b4f0 3535 if (dops[j].bt)
32631e6a 3536 break;
3537 if ((found = is_mflohi(j)))
3538 break;
fe807a8a 3539 if (dops[j].is_jump) {
32631e6a 3540 // check ds
3541 if (j + 1 < slen && (found = is_mflohi(j + 1)))
3542 j++;
3543 break;
3544 }
3545 }
3546 if (found)
3547 // handle all in multdiv_do_stall()
3548 return;
3549 check_multdiv(i, &c);
3550 assert(c > 0);
3551 assem_debug("; muldiv prepare stall %d\n", c);
3552 host_tempreg_acquire();
2330734f 3553 emit_addimm(HOST_CCREG, ccadj_ + c, HOST_TEMPREG);
32631e6a 3554 emit_writeword(HOST_TEMPREG, &psxRegs.muldivBusyCycle);
3555 host_tempreg_release();
3556}
3557
3558static void multdiv_do_stall(int i, const struct regstat *i_regs)
3559{
3560 int j, known_cycles = 0;
3561 u_int reglist = get_host_reglist(i_regs->regmap);
3562 int rtmp = get_reg(i_regs->regmap, -1);
3563 if (rtmp < 0)
3564 rtmp = reglist_find_free(reglist);
3565 if (HACK_ENABLED(NDHACK_NO_STALLS))
3566 return;
3567 if (get_reg(i_regs->regmap, CCREG) != HOST_CCREG || rtmp < 0) {
3568 // happens occasionally... cc evicted? Don't bother then
3569 //printf("no cc/rtmp %08x\n", start + i*4);
3570 return;
3571 }
cf95b4f0 3572 if (!dops[i].bt) {
32631e6a 3573 for (j = i - 1; j >= 0; j--) {
cf95b4f0 3574 if (dops[j].is_ds) break;
2330734f 3575 if (check_multdiv(j, &known_cycles))
32631e6a 3576 break;
3577 if (is_mflohi(j))
3578 // already handled by this op
3579 return;
2330734f 3580 if (dops[j].bt || (j > 0 && ccadj[j - 1] > ccadj[j]))
3581 break;
32631e6a 3582 }
3583 j = max(j, 0);
3584 }
3585 if (known_cycles > 0) {
2330734f 3586 known_cycles -= ccadj[i] - ccadj[j];
32631e6a 3587 assem_debug("; muldiv stall resolved %d\n", known_cycles);
3588 if (known_cycles > 0)
3589 emit_addimm(HOST_CCREG, known_cycles, HOST_CCREG);
3590 return;
3591 }
3592 assem_debug("; muldiv stall unresolved\n");
3593 host_tempreg_acquire();
3594 emit_readword(&psxRegs.muldivBusyCycle, rtmp);
2330734f 3595 emit_addimm(rtmp, -ccadj[i], rtmp);
32631e6a 3596 emit_sub(rtmp, HOST_CCREG, HOST_TEMPREG);
3597 emit_cmpimm(HOST_TEMPREG, 37);
3598 emit_cmovb_reg(rtmp, HOST_CCREG);
3599 //emit_log_gte_stall(i, 0, reglist);
3600 host_tempreg_release();
3601}
3602
8062d65a 3603static void cop2_get_dreg(u_int copr,signed char tl,signed char temp)
3604{
3605 switch (copr) {
3606 case 1:
3607 case 3:
3608 case 5:
3609 case 8:
3610 case 9:
3611 case 10:
3612 case 11:
3613 emit_readword(&reg_cop2d[copr],tl);
3614 emit_signextend16(tl,tl);
3615 emit_writeword(tl,&reg_cop2d[copr]); // hmh
3616 break;
3617 case 7:
3618 case 16:
3619 case 17:
3620 case 18:
3621 case 19:
3622 emit_readword(&reg_cop2d[copr],tl);
3623 emit_andimm(tl,0xffff,tl);
3624 emit_writeword(tl,&reg_cop2d[copr]);
3625 break;
3626 case 15:
3627 emit_readword(&reg_cop2d[14],tl); // SXY2
3628 emit_writeword(tl,&reg_cop2d[copr]);
3629 break;
3630 case 28:
3631 case 29:
3968e69e 3632 c2op_mfc2_29_assemble(tl,temp);
8062d65a 3633 break;
3634 default:
3635 emit_readword(&reg_cop2d[copr],tl);
3636 break;
3637 }
3638}
3639
3640static void cop2_put_dreg(u_int copr,signed char sl,signed char temp)
3641{
3642 switch (copr) {
3643 case 15:
3644 emit_readword(&reg_cop2d[13],temp); // SXY1
3645 emit_writeword(sl,&reg_cop2d[copr]);
3646 emit_writeword(temp,&reg_cop2d[12]); // SXY0
3647 emit_readword(&reg_cop2d[14],temp); // SXY2
3648 emit_writeword(sl,&reg_cop2d[14]);
3649 emit_writeword(temp,&reg_cop2d[13]); // SXY1
3650 break;
3651 case 28:
3652 emit_andimm(sl,0x001f,temp);
3653 emit_shlimm(temp,7,temp);
3654 emit_writeword(temp,&reg_cop2d[9]);
3655 emit_andimm(sl,0x03e0,temp);
3656 emit_shlimm(temp,2,temp);
3657 emit_writeword(temp,&reg_cop2d[10]);
3658 emit_andimm(sl,0x7c00,temp);
3659 emit_shrimm(temp,3,temp);
3660 emit_writeword(temp,&reg_cop2d[11]);
3661 emit_writeword(sl,&reg_cop2d[28]);
3662 break;
3663 case 30:
3968e69e 3664 emit_xorsar_imm(sl,sl,31,temp);
be516ebe 3665#if defined(HAVE_ARMV5) || defined(__aarch64__)
8062d65a 3666 emit_clz(temp,temp);
3667#else
3668 emit_movs(temp,HOST_TEMPREG);
3669 emit_movimm(0,temp);
3670 emit_jeq((int)out+4*4);
3671 emit_addpl_imm(temp,1,temp);
3672 emit_lslpls_imm(HOST_TEMPREG,1,HOST_TEMPREG);
3673 emit_jns((int)out-2*4);
3674#endif
3675 emit_writeword(sl,&reg_cop2d[30]);
3676 emit_writeword(temp,&reg_cop2d[31]);
3677 break;
3678 case 31:
3679 break;
3680 default:
3681 emit_writeword(sl,&reg_cop2d[copr]);
3682 break;
3683 }
3684}
3685
2330734f 3686static void c2ls_assemble(int i, const struct regstat *i_regs, int ccadj_)
b9b61529 3687{
3688 int s,tl;
3689 int ar;
3690 int offset;
1fd1aceb 3691 int memtarget=0,c=0;
b14b6a8f 3692 void *jaddr2=NULL;
3693 enum stub_type type;
b9b61529 3694 int agr=AGEN1+(i&1);
37387d8b 3695 int offset_reg = -1;
3696 int fastio_reg_override = -1;
81dbbf4c 3697 u_int reglist=get_host_reglist(i_regs->regmap);
b9b61529 3698 u_int copr=(source[i]>>16)&0x1f;
cf95b4f0 3699 s=get_reg(i_regs->regmap,dops[i].rs1);
b9b61529 3700 tl=get_reg(i_regs->regmap,FTEMP);
3701 offset=imm[i];
cf95b4f0 3702 assert(dops[i].rs1>0);
b9b61529 3703 assert(tl>=0);
b9b61529 3704
b9b61529 3705 if(i_regs->regmap[HOST_CCREG]==CCREG)
3706 reglist&=~(1<<HOST_CCREG);
3707
3708 // get the address
cf95b4f0 3709 if (dops[i].opcode==0x3a) { // SWC2
b9b61529 3710 ar=get_reg(i_regs->regmap,agr);
3711 if(ar<0) ar=get_reg(i_regs->regmap,-1);
3712 reglist|=1<<ar;
3713 } else { // LWC2
3714 ar=tl;
3715 }
1fd1aceb 3716 if(s>=0) c=(i_regs->wasconst>>s)&1;
3717 memtarget=c&&(((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE);
b9b61529 3718 if (!offset&&!c&&s>=0) ar=s;
3719 assert(ar>=0);
3720
32631e6a 3721 cop2_do_stall_check(0, i, i_regs, reglist);
3722
cf95b4f0 3723 if (dops[i].opcode==0x3a) { // SWC2
3968e69e 3724 cop2_get_dreg(copr,tl,-1);
1fd1aceb 3725 type=STOREW_STUB;
b9b61529 3726 }
1fd1aceb 3727 else
b9b61529 3728 type=LOADW_STUB;
1fd1aceb 3729
3730 if(c&&!memtarget) {
b14b6a8f 3731 jaddr2=out;
1fd1aceb 3732 emit_jmp(0); // inline_readstub/inline_writestub?
b9b61529 3733 }
1fd1aceb 3734 else {
3735 if(!c) {
37387d8b 3736 jaddr2 = emit_fastpath_cmp_jump(i, i_regs, ar,
3737 &offset_reg, &fastio_reg_override);
3738 }
3739 else if (ram_offset && memtarget) {
3740 offset_reg = get_ro_reg(i_regs, 0);
3741 }
3742 switch (dops[i].opcode) {
3743 case 0x32: { // LWC2
3744 int a = ar;
3745 if (fastio_reg_override >= 0)
3746 a = fastio_reg_override;
3747 do_load_word(a, tl, offset_reg);
3748 break;
1fd1aceb 3749 }
37387d8b 3750 case 0x3a: { // SWC2
1fd1aceb 3751 #ifdef DESTRUCTIVE_SHIFT
3752 if(!offset&&!c&&s>=0) emit_mov(s,ar);
3753 #endif
37387d8b 3754 int a = ar;
3755 if (fastio_reg_override >= 0)
3756 a = fastio_reg_override;
3757 do_store_word(a, 0, tl, offset_reg, 1);
3758 break;
3759 }
3760 default:
3761 assert(0);
1fd1aceb 3762 }
b9b61529 3763 }
37387d8b 3764 if (fastio_reg_override == HOST_TEMPREG || offset_reg == HOST_TEMPREG)
d1e4ebd9 3765 host_tempreg_release();
b9b61529 3766 if(jaddr2)
2330734f 3767 add_stub_r(type,jaddr2,out,i,ar,i_regs,ccadj_,reglist);
cf95b4f0 3768 if(dops[i].opcode==0x3a) // SWC2
3769 if(!(i_regs->waswritten&(1<<dops[i].rs1)) && !HACK_ENABLED(NDHACK_NO_SMC_CHECK)) {
b9b61529 3770#if defined(HOST_IMM8)
3771 int ir=get_reg(i_regs->regmap,INVCP);
3772 assert(ir>=0);
3773 emit_cmpmem_indexedsr12_reg(ir,ar,1);
3774#else
643aeae3 3775 emit_cmpmem_indexedsr12_imm(invalid_code,ar,1);
b9b61529 3776#endif
0bbd1454 3777 #if defined(HAVE_CONDITIONAL_CALL) && !defined(DESTRUCTIVE_SHIFT)
3778 emit_callne(invalidate_addr_reg[ar]);
3779 #else
b14b6a8f 3780 void *jaddr3 = out;
b9b61529 3781 emit_jne(0);
b14b6a8f 3782 add_stub(INVCODE_STUB,jaddr3,out,reglist|(1<<HOST_CCREG),ar,0,0,0);
0bbd1454 3783 #endif
b9b61529 3784 }
cf95b4f0 3785 if (dops[i].opcode==0x32) { // LWC2
d1e4ebd9 3786 host_tempreg_acquire();
b9b61529 3787 cop2_put_dreg(copr,tl,HOST_TEMPREG);
d1e4ebd9 3788 host_tempreg_release();
b9b61529 3789 }
3790}
3791
81dbbf4c 3792static void cop2_assemble(int i, const struct regstat *i_regs)
8062d65a 3793{
81dbbf4c 3794 u_int copr = (source[i]>>11) & 0x1f;
3795 signed char temp = get_reg(i_regs->regmap, -1);
3796
32631e6a 3797 if (!HACK_ENABLED(NDHACK_NO_STALLS)) {
3798 u_int reglist = reglist_exclude(get_host_reglist(i_regs->regmap), temp, -1);
cf95b4f0 3799 if (dops[i].opcode2 == 0 || dops[i].opcode2 == 2) { // MFC2/CFC2
3800 signed char tl = get_reg(i_regs->regmap, dops[i].rt1);
32631e6a 3801 reglist = reglist_exclude(reglist, tl, -1);
81dbbf4c 3802 }
32631e6a 3803 cop2_do_stall_check(0, i, i_regs, reglist);
81dbbf4c 3804 }
cf95b4f0 3805 if (dops[i].opcode2==0) { // MFC2
3806 signed char tl=get_reg(i_regs->regmap,dops[i].rt1);
3807 if(tl>=0&&dops[i].rt1!=0)
8062d65a 3808 cop2_get_dreg(copr,tl,temp);
3809 }
cf95b4f0 3810 else if (dops[i].opcode2==4) { // MTC2
3811 signed char sl=get_reg(i_regs->regmap,dops[i].rs1);
8062d65a 3812 cop2_put_dreg(copr,sl,temp);
3813 }
cf95b4f0 3814 else if (dops[i].opcode2==2) // CFC2
8062d65a 3815 {
cf95b4f0 3816 signed char tl=get_reg(i_regs->regmap,dops[i].rt1);
3817 if(tl>=0&&dops[i].rt1!=0)
8062d65a 3818 emit_readword(&reg_cop2c[copr],tl);
3819 }
cf95b4f0 3820 else if (dops[i].opcode2==6) // CTC2
8062d65a 3821 {
cf95b4f0 3822 signed char sl=get_reg(i_regs->regmap,dops[i].rs1);
8062d65a 3823 switch(copr) {
3824 case 4:
3825 case 12:
3826 case 20:
3827 case 26:
3828 case 27:
3829 case 29:
3830 case 30:
3831 emit_signextend16(sl,temp);
3832 break;
3833 case 31:
3968e69e 3834 c2op_ctc2_31_assemble(sl,temp);
8062d65a 3835 break;
3836 default:
3837 temp=sl;
3838 break;
3839 }
3840 emit_writeword(temp,&reg_cop2c[copr]);
3841 assert(sl>=0);
3842 }
3843}
3844
3968e69e 3845static void do_unalignedwritestub(int n)
3846{
3847 assem_debug("do_unalignedwritestub %x\n",start+stubs[n].a*4);
3848 literal_pool(256);
3849 set_jump_target(stubs[n].addr, out);
3850
3851 int i=stubs[n].a;
3852 struct regstat *i_regs=(struct regstat *)stubs[n].c;
3853 int addr=stubs[n].b;
3854 u_int reglist=stubs[n].e;
3855 signed char *i_regmap=i_regs->regmap;
3856 int temp2=get_reg(i_regmap,FTEMP);
3857 int rt;
cf95b4f0 3858 rt=get_reg(i_regmap,dops[i].rs2);
3968e69e 3859 assert(rt>=0);
3860 assert(addr>=0);
cf95b4f0 3861 assert(dops[i].opcode==0x2a||dops[i].opcode==0x2e); // SWL/SWR only implemented
3968e69e 3862 reglist|=(1<<addr);
3863 reglist&=~(1<<temp2);
3864
3968e69e 3865 // don't bother with it and call write handler
3866 save_regs(reglist);
3867 pass_args(addr,rt);
3868 int cc=get_reg(i_regmap,CCREG);
3869 if(cc<0)
3870 emit_loadreg(CCREG,2);
2330734f 3871 emit_addimm(cc<0?2:cc,(int)stubs[n].d+1,2);
cf95b4f0 3872 emit_far_call((dops[i].opcode==0x2a?jump_handle_swl:jump_handle_swr));
2330734f 3873 emit_addimm(0,-((int)stubs[n].d+1),cc<0?2:cc);
3968e69e 3874 if(cc<0)
3875 emit_storereg(CCREG,2);
3876 restore_regs(reglist);
3877 emit_jmp(stubs[n].retaddr); // return address
3968e69e 3878}
3879
57871462 3880#ifndef multdiv_assemble
3881void multdiv_assemble(int i,struct regstat *i_regs)
3882{
3883 printf("Need multdiv_assemble for this architecture.\n");
7c3a5182 3884 abort();
57871462 3885}
3886#endif
3887
2330734f 3888static void mov_assemble(int i, const struct regstat *i_regs)
57871462 3889{
cf95b4f0 3890 //if(dops[i].opcode2==0x10||dops[i].opcode2==0x12) { // MFHI/MFLO
3891 //if(dops[i].opcode2==0x11||dops[i].opcode2==0x13) { // MTHI/MTLO
3892 if(dops[i].rt1) {
7c3a5182 3893 signed char sl,tl;
cf95b4f0 3894 tl=get_reg(i_regs->regmap,dops[i].rt1);
57871462 3895 //assert(tl>=0);
3896 if(tl>=0) {
cf95b4f0 3897 sl=get_reg(i_regs->regmap,dops[i].rs1);
57871462 3898 if(sl>=0) emit_mov(sl,tl);
cf95b4f0 3899 else emit_loadreg(dops[i].rs1,tl);
57871462 3900 }
3901 }
cf95b4f0 3902 if (dops[i].rs1 == HIREG || dops[i].rs1 == LOREG) // MFHI/MFLO
32631e6a 3903 multdiv_do_stall(i, i_regs);
57871462 3904}
3905
3968e69e 3906// call interpreter, exception handler, things that change pc/regs/cycles ...
2330734f 3907static void call_c_cpu_handler(int i, const struct regstat *i_regs, int ccadj_, u_int pc, void *func)
57871462 3908{
3909 signed char ccreg=get_reg(i_regs->regmap,CCREG);
3910 assert(ccreg==HOST_CCREG);
3911 assert(!is_delayslot);
581335b0 3912 (void)ccreg;
3968e69e 3913
3914 emit_movimm(pc,3); // Get PC
3915 emit_readword(&last_count,2);
3916 emit_writeword(3,&psxRegs.pc);
2330734f 3917 emit_addimm(HOST_CCREG,ccadj_,HOST_CCREG);
3968e69e 3918 emit_add(2,HOST_CCREG,2);
3919 emit_writeword(2,&psxRegs.cycle);
2a014d73 3920 emit_far_call(func);
3921 emit_far_jump(jump_to_new_pc);
3968e69e 3922}
3923
2330734f 3924static void syscall_assemble(int i, const struct regstat *i_regs, int ccadj_)
3968e69e 3925{
3926 emit_movimm(0x20,0); // cause code
3927 emit_movimm(0,1); // not in delay slot
2330734f 3928 call_c_cpu_handler(i, i_regs, ccadj_, start+i*4, psxException);
7139f3c8 3929}
3930
2330734f 3931static void hlecall_assemble(int i, const struct regstat *i_regs, int ccadj_)
7139f3c8 3932{
3968e69e 3933 void *hlefunc = psxNULL;
dd79da89 3934 uint32_t hleCode = source[i] & 0x03ffffff;
3968e69e 3935 if (hleCode < ARRAY_SIZE(psxHLEt))
3936 hlefunc = psxHLEt[hleCode];
3937
2330734f 3938 call_c_cpu_handler(i, i_regs, ccadj_, start + i*4+4, hlefunc);
57871462 3939}
3940
2330734f 3941static void intcall_assemble(int i, const struct regstat *i_regs, int ccadj_)
1e973cb0 3942{
2330734f 3943 call_c_cpu_handler(i, i_regs, ccadj_, start + i*4, execI);
1e973cb0 3944}
3945
8062d65a 3946static void speculate_mov(int rs,int rt)
3947{
3948 if(rt!=0) {
3949 smrv_strong_next|=1<<rt;
3950 smrv[rt]=smrv[rs];
3951 }
3952}
3953
3954static void speculate_mov_weak(int rs,int rt)
3955{
3956 if(rt!=0) {
3957 smrv_weak_next|=1<<rt;
3958 smrv[rt]=smrv[rs];
3959 }
3960}
3961
3962static void speculate_register_values(int i)
3963{
3964 if(i==0) {
3965 memcpy(smrv,psxRegs.GPR.r,sizeof(smrv));
3966 // gp,sp are likely to stay the same throughout the block
3967 smrv_strong_next=(1<<28)|(1<<29)|(1<<30);
3968 smrv_weak_next=~smrv_strong_next;
3969 //printf(" llr %08x\n", smrv[4]);
3970 }
3971 smrv_strong=smrv_strong_next;
3972 smrv_weak=smrv_weak_next;
cf95b4f0 3973 switch(dops[i].itype) {
8062d65a 3974 case ALU:
cf95b4f0 3975 if ((smrv_strong>>dops[i].rs1)&1) speculate_mov(dops[i].rs1,dops[i].rt1);
3976 else if((smrv_strong>>dops[i].rs2)&1) speculate_mov(dops[i].rs2,dops[i].rt1);
3977 else if((smrv_weak>>dops[i].rs1)&1) speculate_mov_weak(dops[i].rs1,dops[i].rt1);
3978 else if((smrv_weak>>dops[i].rs2)&1) speculate_mov_weak(dops[i].rs2,dops[i].rt1);
8062d65a 3979 else {
cf95b4f0 3980 smrv_strong_next&=~(1<<dops[i].rt1);
3981 smrv_weak_next&=~(1<<dops[i].rt1);
8062d65a 3982 }
3983 break;
3984 case SHIFTIMM:
cf95b4f0 3985 smrv_strong_next&=~(1<<dops[i].rt1);
3986 smrv_weak_next&=~(1<<dops[i].rt1);
8062d65a 3987 // fallthrough
3988 case IMM16:
cf95b4f0 3989 if(dops[i].rt1&&is_const(&regs[i],dops[i].rt1)) {
3990 int value,hr=get_reg(regs[i].regmap,dops[i].rt1);
8062d65a 3991 if(hr>=0) {
3992 if(get_final_value(hr,i,&value))
cf95b4f0 3993 smrv[dops[i].rt1]=value;
3994 else smrv[dops[i].rt1]=constmap[i][hr];
3995 smrv_strong_next|=1<<dops[i].rt1;
8062d65a 3996 }
3997 }
3998 else {
cf95b4f0 3999 if ((smrv_strong>>dops[i].rs1)&1) speculate_mov(dops[i].rs1,dops[i].rt1);
4000 else if((smrv_weak>>dops[i].rs1)&1) speculate_mov_weak(dops[i].rs1,dops[i].rt1);
8062d65a 4001 }
4002 break;
4003 case LOAD:
cf95b4f0 4004 if(start<0x2000&&(dops[i].rt1==26||(smrv[dops[i].rt1]>>24)==0xa0)) {
8062d65a 4005 // special case for BIOS
cf95b4f0 4006 smrv[dops[i].rt1]=0xa0000000;
4007 smrv_strong_next|=1<<dops[i].rt1;
8062d65a 4008 break;
4009 }
4010 // fallthrough
4011 case SHIFT:
4012 case LOADLR:
4013 case MOV:
cf95b4f0 4014 smrv_strong_next&=~(1<<dops[i].rt1);
4015 smrv_weak_next&=~(1<<dops[i].rt1);
8062d65a 4016 break;
4017 case COP0:
4018 case COP2:
cf95b4f0 4019 if(dops[i].opcode2==0||dops[i].opcode2==2) { // MFC/CFC
4020 smrv_strong_next&=~(1<<dops[i].rt1);
4021 smrv_weak_next&=~(1<<dops[i].rt1);
8062d65a 4022 }
4023 break;
4024 case C2LS:
cf95b4f0 4025 if (dops[i].opcode==0x32) { // LWC2
4026 smrv_strong_next&=~(1<<dops[i].rt1);
4027 smrv_weak_next&=~(1<<dops[i].rt1);
8062d65a 4028 }
4029 break;
4030 }
4031#if 0
4032 int r=4;
4033 printf("x %08x %08x %d %d c %08x %08x\n",smrv[r],start+i*4,
4034 ((smrv_strong>>r)&1),(smrv_weak>>r)&1,regs[i].isconst,regs[i].wasconst);
4035#endif
4036}
4037
2330734f 4038static void ujump_assemble(int i, const struct regstat *i_regs);
4039static void rjump_assemble(int i, const struct regstat *i_regs);
4040static void cjump_assemble(int i, const struct regstat *i_regs);
4041static void sjump_assemble(int i, const struct regstat *i_regs);
4042static void pagespan_assemble(int i, const struct regstat *i_regs);
4043
4044static int assemble(int i, const struct regstat *i_regs, int ccadj_)
57871462 4045{
2330734f 4046 int ds = 0;
4047 switch (dops[i].itype) {
57871462 4048 case ALU:
2330734f 4049 alu_assemble(i, i_regs);
4050 break;
57871462 4051 case IMM16:
2330734f 4052 imm16_assemble(i, i_regs);
4053 break;
57871462 4054 case SHIFT:
2330734f 4055 shift_assemble(i, i_regs);
4056 break;
57871462 4057 case SHIFTIMM:
2330734f 4058 shiftimm_assemble(i, i_regs);
4059 break;
57871462 4060 case LOAD:
2330734f 4061 load_assemble(i, i_regs, ccadj_);
4062 break;
57871462 4063 case LOADLR:
2330734f 4064 loadlr_assemble(i, i_regs, ccadj_);
4065 break;
57871462 4066 case STORE:
2330734f 4067 store_assemble(i, i_regs, ccadj_);
4068 break;
57871462 4069 case STORELR:
2330734f 4070 storelr_assemble(i, i_regs, ccadj_);
4071 break;
57871462 4072 case COP0:
2330734f 4073 cop0_assemble(i, i_regs, ccadj_);
4074 break;
57871462 4075 case COP1:
2330734f 4076 cop1_assemble(i, i_regs);
4077 break;
57871462 4078 case C1LS:
2330734f 4079 c1ls_assemble(i, i_regs);
4080 break;
b9b61529 4081 case COP2:
2330734f 4082 cop2_assemble(i, i_regs);
4083 break;
b9b61529 4084 case C2LS:
2330734f 4085 c2ls_assemble(i, i_regs, ccadj_);
4086 break;
b9b61529 4087 case C2OP:
2330734f 4088 c2op_assemble(i, i_regs);
4089 break;
57871462 4090 case MULTDIV:
2330734f 4091 multdiv_assemble(i, i_regs);
4092 multdiv_prepare_stall(i, i_regs, ccadj_);
32631e6a 4093 break;
57871462 4094 case MOV:
2330734f 4095 mov_assemble(i, i_regs);
4096 break;
4097 case SYSCALL:
4098 syscall_assemble(i, i_regs, ccadj_);
4099 break;
4100 case HLECALL:
4101 hlecall_assemble(i, i_regs, ccadj_);
4102 break;
4103 case INTCALL:
4104 intcall_assemble(i, i_regs, ccadj_);
4105 break;
4106 case UJUMP:
4107 ujump_assemble(i, i_regs);
4108 ds = 1;
4109 break;
4110 case RJUMP:
4111 rjump_assemble(i, i_regs);
4112 ds = 1;
4113 break;
4114 case CJUMP:
4115 cjump_assemble(i, i_regs);
4116 ds = 1;
4117 break;
4118 case SJUMP:
4119 sjump_assemble(i, i_regs);
4120 ds = 1;
4121 break;
4122 case SPAN:
4123 pagespan_assemble(i, i_regs);
4124 break;
24058131 4125 case NOP:
2330734f 4126 case OTHER:
4127 case NI:
4128 // not handled, just skip
4129 break;
4130 default:
4131 assert(0);
4132 }
4133 return ds;
4134}
4135
4136static void ds_assemble(int i, const struct regstat *i_regs)
4137{
4138 speculate_register_values(i);
4139 is_delayslot = 1;
4140 switch (dops[i].itype) {
57871462 4141 case SYSCALL:
7139f3c8 4142 case HLECALL:
1e973cb0 4143 case INTCALL:
57871462 4144 case SPAN:
4145 case UJUMP:
4146 case RJUMP:
4147 case CJUMP:
4148 case SJUMP:
c43b5311 4149 SysPrintf("Jump in the delay slot. This is probably a bug.\n");
2330734f 4150 break;
4151 default:
4152 assemble(i, i_regs, ccadj[i]);
57871462 4153 }
2330734f 4154 is_delayslot = 0;
57871462 4155}
4156
4157// Is the branch target a valid internal jump?
ad49de89 4158static int internal_branch(int addr)
57871462 4159{
4160 if(addr&1) return 0; // Indirect (register) jump
4161 if(addr>=start && addr<start+slen*4-4)
4162 {
71e490c5 4163 return 1;
57871462 4164 }
4165 return 0;
4166}
4167
ad49de89 4168static void wb_invalidate(signed char pre[],signed char entry[],uint64_t dirty,uint64_t u)
57871462 4169{
4170 int hr;
4171 for(hr=0;hr<HOST_REGS;hr++) {
4172 if(hr!=EXCLUDE_REG) {
4173 if(pre[hr]!=entry[hr]) {
4174 if(pre[hr]>=0) {
4175 if((dirty>>hr)&1) {
4176 if(get_reg(entry,pre[hr])<0) {
00fa9369 4177 assert(pre[hr]<64);
4178 if(!((u>>pre[hr])&1))
4179 emit_storereg(pre[hr],hr);
57871462 4180 }
4181 }
4182 }
4183 }
4184 }
4185 }
4186 // Move from one register to another (no writeback)
4187 for(hr=0;hr<HOST_REGS;hr++) {
4188 if(hr!=EXCLUDE_REG) {
4189 if(pre[hr]!=entry[hr]) {
4190 if(pre[hr]>=0&&(pre[hr]&63)<TEMPREG) {
4191 int nr;
4192 if((nr=get_reg(entry,pre[hr]))>=0) {
4193 emit_mov(hr,nr);
4194 }
4195 }
4196 }
4197 }
4198 }
4199}
57871462 4200
4201// Load the specified registers
4202// This only loads the registers given as arguments because
4203// we don't want to load things that will be overwritten
ad49de89 4204static void load_regs(signed char entry[],signed char regmap[],int rs1,int rs2)
57871462 4205{
4206 int hr;
4207 // Load 32-bit regs
4208 for(hr=0;hr<HOST_REGS;hr++) {
4209 if(hr!=EXCLUDE_REG&&regmap[hr]>=0) {
4210 if(entry[hr]!=regmap[hr]) {
4211 if(regmap[hr]==rs1||regmap[hr]==rs2)
4212 {
4213 if(regmap[hr]==0) {
4214 emit_zeroreg(hr);
4215 }
4216 else
4217 {
4218 emit_loadreg(regmap[hr],hr);
4219 }
4220 }
4221 }
4222 }
4223 }
57871462 4224}
4225
4226// Load registers prior to the start of a loop
4227// so that they are not loaded within the loop
4228static void loop_preload(signed char pre[],signed char entry[])
4229{
4230 int hr;
4231 for(hr=0;hr<HOST_REGS;hr++) {
4232 if(hr!=EXCLUDE_REG) {
4233 if(pre[hr]!=entry[hr]) {
4234 if(entry[hr]>=0) {
4235 if(get_reg(pre,entry[hr])<0) {
4236 assem_debug("loop preload:\n");
4237 //printf("loop preload: %d\n",hr);
4238 if(entry[hr]==0) {
4239 emit_zeroreg(hr);
4240 }
4241 else if(entry[hr]<TEMPREG)
4242 {
4243 emit_loadreg(entry[hr],hr);
4244 }
4245 else if(entry[hr]-64<TEMPREG)
4246 {
4247 emit_loadreg(entry[hr],hr);
4248 }
4249 }
4250 }
4251 }
4252 }
4253 }
4254}
4255
4256// Generate address for load/store instruction
b9b61529 4257// goes to AGEN for writes, FTEMP for LOADLR and cop1/2 loads
2330734f 4258void address_generation(int i, const struct regstat *i_regs, signed char entry[])
57871462 4259{
37387d8b 4260 if (dops[i].is_load || dops[i].is_store) {
5194fb95 4261 int ra=-1;
57871462 4262 int agr=AGEN1+(i&1);
cf95b4f0 4263 if(dops[i].itype==LOAD) {
4264 ra=get_reg(i_regs->regmap,dops[i].rt1);
9f51b4b9 4265 if(ra<0) ra=get_reg(i_regs->regmap,-1);
535d208a 4266 assert(ra>=0);
57871462 4267 }
cf95b4f0 4268 if(dops[i].itype==LOADLR) {
57871462 4269 ra=get_reg(i_regs->regmap,FTEMP);
4270 }
cf95b4f0 4271 if(dops[i].itype==STORE||dops[i].itype==STORELR) {
57871462 4272 ra=get_reg(i_regs->regmap,agr);
4273 if(ra<0) ra=get_reg(i_regs->regmap,-1);
4274 }
37387d8b 4275 if(dops[i].itype==C2LS) {
cf95b4f0 4276 if ((dops[i].opcode&0x3b)==0x31||(dops[i].opcode&0x3b)==0x32) // LWC1/LDC1/LWC2/LDC2
57871462 4277 ra=get_reg(i_regs->regmap,FTEMP);
1fd1aceb 4278 else { // SWC1/SDC1/SWC2/SDC2
57871462 4279 ra=get_reg(i_regs->regmap,agr);
4280 if(ra<0) ra=get_reg(i_regs->regmap,-1);
4281 }
4282 }
cf95b4f0 4283 int rs=get_reg(i_regs->regmap,dops[i].rs1);
57871462 4284 if(ra>=0) {
4285 int offset=imm[i];
4286 int c=(i_regs->wasconst>>rs)&1;
cf95b4f0 4287 if(dops[i].rs1==0) {
57871462 4288 // Using r0 as a base address
57871462 4289 if(!entry||entry[ra]!=agr) {
cf95b4f0 4290 if (dops[i].opcode==0x22||dops[i].opcode==0x26) {
57871462 4291 emit_movimm(offset&0xFFFFFFFC,ra); // LWL/LWR
cf95b4f0 4292 }else if (dops[i].opcode==0x1a||dops[i].opcode==0x1b) {
57871462 4293 emit_movimm(offset&0xFFFFFFF8,ra); // LDL/LDR
4294 }else{
4295 emit_movimm(offset,ra);
4296 }
4297 } // else did it in the previous cycle
4298 }
4299 else if(rs<0) {
cf95b4f0 4300 if(!entry||entry[ra]!=dops[i].rs1)
4301 emit_loadreg(dops[i].rs1,ra);
4302 //if(!entry||entry[ra]!=dops[i].rs1)
57871462 4303 // printf("poor load scheduling!\n");
4304 }
4305 else if(c) {
cf95b4f0 4306 if(dops[i].rs1!=dops[i].rt1||dops[i].itype!=LOAD) {
57871462 4307 if(!entry||entry[ra]!=agr) {
cf95b4f0 4308 if (dops[i].opcode==0x22||dops[i].opcode==0x26) {
57871462 4309 emit_movimm((constmap[i][rs]+offset)&0xFFFFFFFC,ra); // LWL/LWR
cf95b4f0 4310 }else if (dops[i].opcode==0x1a||dops[i].opcode==0x1b) {
57871462 4311 emit_movimm((constmap[i][rs]+offset)&0xFFFFFFF8,ra); // LDL/LDR
4312 }else{
57871462 4313 emit_movimm(constmap[i][rs]+offset,ra);
8575a877 4314 regs[i].loadedconst|=1<<ra;
57871462 4315 }
4316 } // else did it in the previous cycle
4317 } // else load_consts already did it
4318 }
cf95b4f0 4319 if(offset&&!c&&dops[i].rs1) {
57871462 4320 if(rs>=0) {
4321 emit_addimm(rs,offset,ra);
4322 }else{
4323 emit_addimm(ra,offset,ra);
4324 }
4325 }
4326 }
4327 }
4328 // Preload constants for next instruction
37387d8b 4329 if (dops[i+1].is_load || dops[i+1].is_store) {
57871462 4330 int agr,ra;
57871462 4331 // Actual address
4332 agr=AGEN1+((i+1)&1);
4333 ra=get_reg(i_regs->regmap,agr);
4334 if(ra>=0) {
cf95b4f0 4335 int rs=get_reg(regs[i+1].regmap,dops[i+1].rs1);
57871462 4336 int offset=imm[i+1];
4337 int c=(regs[i+1].wasconst>>rs)&1;
cf95b4f0 4338 if(c&&(dops[i+1].rs1!=dops[i+1].rt1||dops[i+1].itype!=LOAD)) {
4339 if (dops[i+1].opcode==0x22||dops[i+1].opcode==0x26) {
57871462 4340 emit_movimm((constmap[i+1][rs]+offset)&0xFFFFFFFC,ra); // LWL/LWR
cf95b4f0 4341 }else if (dops[i+1].opcode==0x1a||dops[i+1].opcode==0x1b) {
57871462 4342 emit_movimm((constmap[i+1][rs]+offset)&0xFFFFFFF8,ra); // LDL/LDR
4343 }else{
57871462 4344 emit_movimm(constmap[i+1][rs]+offset,ra);
8575a877 4345 regs[i+1].loadedconst|=1<<ra;
57871462 4346 }
4347 }
cf95b4f0 4348 else if(dops[i+1].rs1==0) {
57871462 4349 // Using r0 as a base address
cf95b4f0 4350 if (dops[i+1].opcode==0x22||dops[i+1].opcode==0x26) {
57871462 4351 emit_movimm(offset&0xFFFFFFFC,ra); // LWL/LWR
cf95b4f0 4352 }else if (dops[i+1].opcode==0x1a||dops[i+1].opcode==0x1b) {
57871462 4353 emit_movimm(offset&0xFFFFFFF8,ra); // LDL/LDR
4354 }else{
4355 emit_movimm(offset,ra);
4356 }
4357 }
4358 }
4359 }
4360}
4361
e2b5e7aa 4362static int get_final_value(int hr, int i, int *value)
57871462 4363{
4364 int reg=regs[i].regmap[hr];
4365 while(i<slen-1) {
4366 if(regs[i+1].regmap[hr]!=reg) break;
4367 if(!((regs[i+1].isconst>>hr)&1)) break;
cf95b4f0 4368 if(dops[i+1].bt) break;
57871462 4369 i++;
4370 }
4371 if(i<slen-1) {
fe807a8a 4372 if (dops[i].is_jump) {
57871462 4373 *value=constmap[i][hr];
4374 return 1;
4375 }
cf95b4f0 4376 if(!dops[i+1].bt) {
fe807a8a 4377 if (dops[i+1].is_jump) {
57871462 4378 // Load in delay slot, out-of-order execution
cf95b4f0 4379 if(dops[i+2].itype==LOAD&&dops[i+2].rs1==reg&&dops[i+2].rt1==reg&&((regs[i+1].wasconst>>hr)&1))
57871462 4380 {
57871462 4381 // Precompute load address
4382 *value=constmap[i][hr]+imm[i+2];
4383 return 1;
4384 }
4385 }
cf95b4f0 4386 if(dops[i+1].itype==LOAD&&dops[i+1].rs1==reg&&dops[i+1].rt1==reg)
57871462 4387 {
57871462 4388 // Precompute load address
4389 *value=constmap[i][hr]+imm[i+1];
643aeae3 4390 //printf("c=%x imm=%lx\n",(long)constmap[i][hr],imm[i+1]);
57871462 4391 return 1;
4392 }
4393 }
4394 }
4395 *value=constmap[i][hr];
643aeae3 4396 //printf("c=%lx\n",(long)constmap[i][hr]);
57871462 4397 if(i==slen-1) return 1;
00fa9369 4398 assert(reg < 64);
4399 return !((unneeded_reg[i+1]>>reg)&1);
57871462 4400}
4401
4402// Load registers with known constants
ad49de89 4403static void load_consts(signed char pre[],signed char regmap[],int i)
57871462 4404{
8575a877 4405 int hr,hr2;
4406 // propagate loaded constant flags
cf95b4f0 4407 if(i==0||dops[i].bt)
8575a877 4408 regs[i].loadedconst=0;
4409 else {
4410 for(hr=0;hr<HOST_REGS;hr++) {
4411 if(hr!=EXCLUDE_REG&&regmap[hr]>=0&&((regs[i-1].isconst>>hr)&1)&&pre[hr]==regmap[hr]
4412 &&regmap[hr]==regs[i-1].regmap[hr]&&((regs[i-1].loadedconst>>hr)&1))
4413 {
4414 regs[i].loadedconst|=1<<hr;
4415 }
4416 }
4417 }
57871462 4418 // Load 32-bit regs
4419 for(hr=0;hr<HOST_REGS;hr++) {
4420 if(hr!=EXCLUDE_REG&&regmap[hr]>=0) {
4421 //if(entry[hr]!=regmap[hr]) {
8575a877 4422 if(!((regs[i].loadedconst>>hr)&1)) {
ad49de89 4423 assert(regmap[hr]<64);
4424 if(((regs[i].isconst>>hr)&1)&&regmap[hr]>0) {
8575a877 4425 int value,similar=0;
57871462 4426 if(get_final_value(hr,i,&value)) {
8575a877 4427 // see if some other register has similar value
4428 for(hr2=0;hr2<HOST_REGS;hr2++) {
4429 if(hr2!=EXCLUDE_REG&&((regs[i].loadedconst>>hr2)&1)) {
4430 if(is_similar_value(value,constmap[i][hr2])) {
4431 similar=1;
4432 break;
4433 }
4434 }
4435 }
4436 if(similar) {
4437 int value2;
4438 if(get_final_value(hr2,i,&value2)) // is this needed?
4439 emit_movimm_from(value2,hr2,value,hr);
4440 else
4441 emit_movimm(value,hr);
4442 }
4443 else if(value==0) {
57871462 4444 emit_zeroreg(hr);
4445 }
4446 else {
4447 emit_movimm(value,hr);
4448 }
4449 }
8575a877 4450 regs[i].loadedconst|=1<<hr;
57871462 4451 }
4452 }
4453 }
4454 }
57871462 4455}
ad49de89 4456
2330734f 4457static void load_all_consts(const signed char regmap[], u_int dirty, int i)
57871462 4458{
4459 int hr;
4460 // Load 32-bit regs
4461 for(hr=0;hr<HOST_REGS;hr++) {
4462 if(hr!=EXCLUDE_REG&&regmap[hr]>=0&&((dirty>>hr)&1)) {
ad49de89 4463 assert(regmap[hr] < 64);
4464 if(((regs[i].isconst>>hr)&1)&&regmap[hr]>0) {
57871462 4465 int value=constmap[i][hr];
4466 if(value==0) {
4467 emit_zeroreg(hr);
4468 }
4469 else {
4470 emit_movimm(value,hr);
4471 }
4472 }
4473 }
4474 }
57871462 4475}
4476
4477// Write out all dirty registers (except cycle count)
2330734f 4478static void wb_dirtys(const signed char i_regmap[], uint64_t i_dirty)
57871462 4479{
4480 int hr;
4481 for(hr=0;hr<HOST_REGS;hr++) {
4482 if(hr!=EXCLUDE_REG) {
4483 if(i_regmap[hr]>0) {
4484 if(i_regmap[hr]!=CCREG) {
4485 if((i_dirty>>hr)&1) {
00fa9369 4486 assert(i_regmap[hr]<64);
4487 emit_storereg(i_regmap[hr],hr);
57871462 4488 }
4489 }
4490 }
4491 }
4492 }
4493}
ad49de89 4494
57871462 4495// Write out dirty registers that we need to reload (pair with load_needed_regs)
4496// This writes the registers not written by store_regs_bt
2330734f 4497static void wb_needed_dirtys(const signed char i_regmap[], uint64_t i_dirty, int addr)
57871462 4498{
4499 int hr;
4500 int t=(addr-start)>>2;
4501 for(hr=0;hr<HOST_REGS;hr++) {
4502 if(hr!=EXCLUDE_REG) {
4503 if(i_regmap[hr]>0) {
4504 if(i_regmap[hr]!=CCREG) {
ad49de89 4505 if(i_regmap[hr]==regs[t].regmap_entry[hr] && ((regs[t].dirty>>hr)&1)) {
57871462 4506 if((i_dirty>>hr)&1) {
00fa9369 4507 assert(i_regmap[hr]<64);
4508 emit_storereg(i_regmap[hr],hr);
57871462 4509 }
4510 }
4511 }
4512 }
4513 }
4514 }
4515}
4516
4517// Load all registers (except cycle count)
2330734f 4518static void load_all_regs(const signed char i_regmap[])
57871462 4519{
4520 int hr;
4521 for(hr=0;hr<HOST_REGS;hr++) {
4522 if(hr!=EXCLUDE_REG) {
4523 if(i_regmap[hr]==0) {
4524 emit_zeroreg(hr);
4525 }
4526 else
ea3d2e6e 4527 if(i_regmap[hr]>0 && (i_regmap[hr]&63)<TEMPREG && i_regmap[hr]!=CCREG)
57871462 4528 {
4529 emit_loadreg(i_regmap[hr],hr);
4530 }
4531 }
4532 }
4533}
4534
4535// Load all current registers also needed by next instruction
2330734f 4536static void load_needed_regs(const signed char i_regmap[], const signed char next_regmap[])
57871462 4537{
4538 int hr;
4539 for(hr=0;hr<HOST_REGS;hr++) {
4540 if(hr!=EXCLUDE_REG) {
4541 if(get_reg(next_regmap,i_regmap[hr])>=0) {
4542 if(i_regmap[hr]==0) {
4543 emit_zeroreg(hr);
4544 }
4545 else
ea3d2e6e 4546 if(i_regmap[hr]>0 && (i_regmap[hr]&63)<TEMPREG && i_regmap[hr]!=CCREG)
57871462 4547 {
4548 emit_loadreg(i_regmap[hr],hr);
4549 }
4550 }
4551 }
4552 }
4553}
4554
4555// Load all regs, storing cycle count if necessary
2330734f 4556static void load_regs_entry(int t)
57871462 4557{
4558 int hr;
cf95b4f0 4559 if(dops[t].is_ds) emit_addimm(HOST_CCREG,CLOCK_ADJUST(1),HOST_CCREG);
2330734f 4560 else if(ccadj[t]) emit_addimm(HOST_CCREG,-ccadj[t],HOST_CCREG);
57871462 4561 if(regs[t].regmap_entry[HOST_CCREG]!=CCREG) {
4562 emit_storereg(CCREG,HOST_CCREG);
4563 }
4564 // Load 32-bit regs
4565 for(hr=0;hr<HOST_REGS;hr++) {
ea3d2e6e 4566 if(regs[t].regmap_entry[hr]>=0&&regs[t].regmap_entry[hr]<TEMPREG) {
57871462 4567 if(regs[t].regmap_entry[hr]==0) {
4568 emit_zeroreg(hr);
4569 }
4570 else if(regs[t].regmap_entry[hr]!=CCREG)
4571 {
4572 emit_loadreg(regs[t].regmap_entry[hr],hr);
4573 }
4574 }
4575 }
57871462 4576}
4577
4578// Store dirty registers prior to branch
ad49de89 4579void store_regs_bt(signed char i_regmap[],uint64_t i_dirty,int addr)
57871462 4580{
ad49de89 4581 if(internal_branch(addr))
57871462 4582 {
4583 int t=(addr-start)>>2;
4584 int hr;
4585 for(hr=0;hr<HOST_REGS;hr++) {
4586 if(hr!=EXCLUDE_REG) {
4587 if(i_regmap[hr]>0 && i_regmap[hr]!=CCREG) {
ad49de89 4588 if(i_regmap[hr]!=regs[t].regmap_entry[hr] || !((regs[t].dirty>>hr)&1)) {
57871462 4589 if((i_dirty>>hr)&1) {
00fa9369 4590 assert(i_regmap[hr]<64);
4591 if(!((unneeded_reg[t]>>i_regmap[hr])&1))
4592 emit_storereg(i_regmap[hr],hr);
57871462 4593 }
4594 }
4595 }
4596 }
4597 }
4598 }
4599 else
4600 {
4601 // Branch out of this block, write out all dirty regs
ad49de89 4602 wb_dirtys(i_regmap,i_dirty);
57871462 4603 }
4604}
4605
4606// Load all needed registers for branch target
ad49de89 4607static void load_regs_bt(signed char i_regmap[],uint64_t i_dirty,int addr)
57871462 4608{
4609 //if(addr>=start && addr<(start+slen*4))
ad49de89 4610 if(internal_branch(addr))
57871462 4611 {
4612 int t=(addr-start)>>2;
4613 int hr;
4614 // Store the cycle count before loading something else
4615 if(i_regmap[HOST_CCREG]!=CCREG) {
4616 assert(i_regmap[HOST_CCREG]==-1);
4617 }
4618 if(regs[t].regmap_entry[HOST_CCREG]!=CCREG) {
4619 emit_storereg(CCREG,HOST_CCREG);
4620 }
4621 // Load 32-bit regs
4622 for(hr=0;hr<HOST_REGS;hr++) {
ea3d2e6e 4623 if(hr!=EXCLUDE_REG&&regs[t].regmap_entry[hr]>=0&&regs[t].regmap_entry[hr]<TEMPREG) {
00fa9369 4624 if(i_regmap[hr]!=regs[t].regmap_entry[hr]) {
57871462 4625 if(regs[t].regmap_entry[hr]==0) {
4626 emit_zeroreg(hr);
4627 }
4628 else if(regs[t].regmap_entry[hr]!=CCREG)
4629 {
4630 emit_loadreg(regs[t].regmap_entry[hr],hr);
4631 }
4632 }
4633 }
4634 }
57871462 4635 }
4636}
4637
ad49de89 4638static int match_bt(signed char i_regmap[],uint64_t i_dirty,int addr)
57871462 4639{
4640 if(addr>=start && addr<start+slen*4-4)
4641 {
4642 int t=(addr-start)>>2;
4643 int hr;
4644 if(regs[t].regmap_entry[HOST_CCREG]!=CCREG) return 0;
4645 for(hr=0;hr<HOST_REGS;hr++)
4646 {
4647 if(hr!=EXCLUDE_REG)
4648 {
4649 if(i_regmap[hr]!=regs[t].regmap_entry[hr])
4650 {
ea3d2e6e 4651 if(regs[t].regmap_entry[hr]>=0&&(regs[t].regmap_entry[hr]|64)<TEMPREG+64)
57871462 4652 {
4653 return 0;
4654 }
9f51b4b9 4655 else
57871462 4656 if((i_dirty>>hr)&1)
4657 {
ea3d2e6e 4658 if(i_regmap[hr]<TEMPREG)
57871462 4659 {
4660 if(!((unneeded_reg[t]>>i_regmap[hr])&1))
4661 return 0;
4662 }
ea3d2e6e 4663 else if(i_regmap[hr]>=64&&i_regmap[hr]<TEMPREG+64)
57871462 4664 {
00fa9369 4665 assert(0);
57871462 4666 }
4667 }
4668 }
4669 else // Same register but is it 32-bit or dirty?
4670 if(i_regmap[hr]>=0)
4671 {
4672 if(!((regs[t].dirty>>hr)&1))
4673 {
4674 if((i_dirty>>hr)&1)
4675 {
4676 if(!((unneeded_reg[t]>>i_regmap[hr])&1))
4677 {
4678 //printf("%x: dirty no match\n",addr);
4679 return 0;
4680 }
4681 }
4682 }
57871462 4683 }
4684 }
4685 }
57871462 4686 // Delay slots are not valid branch targets
fe807a8a 4687 //if(t>0&&(dops[t-1].is_jump) return 0;
57871462 4688 // Delay slots require additional processing, so do not match
cf95b4f0 4689 if(dops[t].is_ds) return 0;
57871462 4690 }
4691 else
4692 {
4693 int hr;
4694 for(hr=0;hr<HOST_REGS;hr++)
4695 {
4696 if(hr!=EXCLUDE_REG)
4697 {
4698 if(i_regmap[hr]>=0)
4699 {
4700 if(hr!=HOST_CCREG||i_regmap[hr]!=CCREG)
4701 {
4702 if((i_dirty>>hr)&1)
4703 {
4704 return 0;
4705 }
4706 }
4707 }
4708 }
4709 }
4710 }
4711 return 1;
4712}
4713
dd114d7d 4714#ifdef DRC_DBG
2330734f 4715static void drc_dbg_emit_do_cmp(int i, int ccadj_)
dd114d7d 4716{
4717 extern void do_insn_cmp();
3968e69e 4718 //extern int cycle;
81dbbf4c 4719 u_int hr, reglist = get_host_reglist(regs[i].regmap);
dd114d7d 4720
40fca85b 4721 assem_debug("//do_insn_cmp %08x\n", start+i*4);
dd114d7d 4722 save_regs(reglist);
40fca85b 4723 // write out changed consts to match the interpreter
cf95b4f0 4724 if (i > 0 && !dops[i].bt) {
40fca85b 4725 for (hr = 0; hr < HOST_REGS; hr++) {
2330734f 4726 int reg = regs[i].regmap_entry[hr]; // regs[i-1].regmap[hr];
40fca85b 4727 if (hr == EXCLUDE_REG || reg < 0)
4728 continue;
4729 if (!((regs[i-1].isconst >> hr) & 1))
4730 continue;
4731 if (i > 1 && reg == regs[i-2].regmap[hr] && constmap[i-1][hr] == constmap[i-2][hr])
4732 continue;
4733 emit_movimm(constmap[i-1][hr],0);
4734 emit_storereg(reg, 0);
4735 }
4736 }
dd114d7d 4737 emit_movimm(start+i*4,0);
643aeae3 4738 emit_writeword(0,&pcaddr);
2330734f 4739 int cc = get_reg(regs[i].regmap_entry, CCREG);
4740 if (cc < 0)
4741 emit_loadreg(CCREG, cc = 0);
4742 emit_addimm(cc, ccadj_, 0);
4743 emit_writeword(0, &psxRegs.cycle);
2a014d73 4744 emit_far_call(do_insn_cmp);
643aeae3 4745 //emit_readword(&cycle,0);
dd114d7d 4746 //emit_addimm(0,2,0);
643aeae3 4747 //emit_writeword(0,&cycle);
3968e69e 4748 (void)get_reg2;
dd114d7d 4749 restore_regs(reglist);
40fca85b 4750 assem_debug("\\\\do_insn_cmp\n");
dd114d7d 4751}
4752#else
2330734f 4753#define drc_dbg_emit_do_cmp(x,y)
dd114d7d 4754#endif
4755
57871462 4756// Used when a branch jumps into the delay slot of another branch
7c3a5182 4757static void ds_assemble_entry(int i)
57871462 4758{
2330734f 4759 int t = (ba[i] - start) >> 2;
4760 int ccadj_ = -CLOCK_ADJUST(1);
df4dc2b1 4761 if (!instr_addr[t])
4762 instr_addr[t] = out;
57871462 4763 assem_debug("Assemble delay slot at %x\n",ba[i]);
4764 assem_debug("<->\n");
2330734f 4765 drc_dbg_emit_do_cmp(t, ccadj_);
57871462 4766 if(regs[t].regmap_entry[HOST_CCREG]==CCREG&&regs[t].regmap[HOST_CCREG]!=CCREG)
ad49de89 4767 wb_register(CCREG,regs[t].regmap_entry,regs[t].wasdirty);
cf95b4f0 4768 load_regs(regs[t].regmap_entry,regs[t].regmap,dops[t].rs1,dops[t].rs2);
57871462 4769 address_generation(t,&regs[t],regs[t].regmap_entry);
37387d8b 4770 if (ram_offset && (dops[t].is_load || dops[t].is_store))
4771 load_regs(regs[t].regmap_entry,regs[t].regmap,ROREG,ROREG);
4772 if (dops[t].is_store)
ad49de89 4773 load_regs(regs[t].regmap_entry,regs[t].regmap,INVCP,INVCP);
57871462 4774 is_delayslot=0;
2330734f 4775 switch (dops[t].itype) {
57871462 4776 case SYSCALL:
7139f3c8 4777 case HLECALL:
1e973cb0 4778 case INTCALL:
57871462 4779 case SPAN:
4780 case UJUMP:
4781 case RJUMP:
4782 case CJUMP:
4783 case SJUMP:
c43b5311 4784 SysPrintf("Jump in the delay slot. This is probably a bug.\n");
2330734f 4785 break;
4786 default:
4787 assemble(t, &regs[t], ccadj_);
57871462 4788 }
ad49de89 4789 store_regs_bt(regs[t].regmap,regs[t].dirty,ba[i]+4);
4790 load_regs_bt(regs[t].regmap,regs[t].dirty,ba[i]+4);
4791 if(internal_branch(ba[i]+4))
57871462 4792 assem_debug("branch: internal\n");
4793 else
4794 assem_debug("branch: external\n");
ad49de89 4795 assert(internal_branch(ba[i]+4));
4796 add_to_linker(out,ba[i]+4,internal_branch(ba[i]+4));
57871462 4797 emit_jmp(0);
4798}
4799
7c3a5182 4800static void emit_extjump(void *addr, u_int target)
4801{
4802 emit_extjump2(addr, target, dyna_linker);
4803}
4804
4805static void emit_extjump_ds(void *addr, u_int target)
4806{
4807 emit_extjump2(addr, target, dyna_linker_ds);
4808}
4809
d1e4ebd9 4810// Load 2 immediates optimizing for small code size
4811static void emit_mov2imm_compact(int imm1,u_int rt1,int imm2,u_int rt2)
4812{
4813 emit_movimm(imm1,rt1);
4814 emit_movimm_from(imm1,rt1,imm2,rt2);
4815}
4816
2330734f 4817static void do_cc(int i, const signed char i_regmap[], int *adj,
4818 int addr, int taken, int invert)
57871462 4819{
2330734f 4820 int count, count_plus2;
b14b6a8f 4821 void *jaddr;
4822 void *idle=NULL;
b6e87b2b 4823 int t=0;
cf95b4f0 4824 if(dops[i].itype==RJUMP)
57871462 4825 {
4826 *adj=0;
4827 }
4828 //if(ba[i]>=start && ba[i]<(start+slen*4))
ad49de89 4829 if(internal_branch(ba[i]))
57871462 4830 {
b6e87b2b 4831 t=(ba[i]-start)>>2;
2330734f 4832 if(dops[t].is_ds) *adj=-CLOCK_ADJUST(1); // Branch into delay slot adds an extra cycle
57871462 4833 else *adj=ccadj[t];
4834 }
4835 else
4836 {
4837 *adj=0;
4838 }
2330734f 4839 count = ccadj[i];
4840 count_plus2 = count + CLOCK_ADJUST(2);
57871462 4841 if(taken==TAKEN && i==(ba[i]-start)>>2 && source[i+1]==0) {
4842 // Idle loop
4843 if(count&1) emit_addimm_and_set_flags(2*(count+2),HOST_CCREG);
b14b6a8f 4844 idle=out;
57871462 4845 //emit_subfrommem(&idlecount,HOST_CCREG); // Count idle cycles
4846 emit_andimm(HOST_CCREG,3,HOST_CCREG);
b14b6a8f 4847 jaddr=out;
57871462 4848 emit_jmp(0);
4849 }
4850 else if(*adj==0||invert) {
2330734f 4851 int cycles = count_plus2;
b6e87b2b 4852 // faster loop HACK
bb4f300c 4853#if 0
b6e87b2b 4854 if (t&&*adj) {
4855 int rel=t-i;
4856 if(-NO_CYCLE_PENALTY_THR<rel&&rel<0)
2330734f 4857 cycles=*adj+count+2-*adj;
b6e87b2b 4858 }
bb4f300c 4859#endif
2330734f 4860 emit_addimm_and_set_flags(cycles, HOST_CCREG);
4861 jaddr = out;
57871462 4862 emit_jns(0);
4863 }
4864 else
4865 {
2330734f 4866 emit_cmpimm(HOST_CCREG, -count_plus2);
4867 jaddr = out;
57871462 4868 emit_jns(0);
4869 }
2330734f 4870 add_stub(CC_STUB,jaddr,idle?idle:out,(*adj==0||invert||idle)?0:count_plus2,i,addr,taken,0);
57871462 4871}
4872
b14b6a8f 4873static void do_ccstub(int n)
57871462 4874{
4875 literal_pool(256);
d1e4ebd9 4876 assem_debug("do_ccstub %x\n",start+(u_int)stubs[n].b*4);
b14b6a8f 4877 set_jump_target(stubs[n].addr, out);
4878 int i=stubs[n].b;
4879 if(stubs[n].d==NULLDS) {
57871462 4880 // Delay slot instruction is nullified ("likely" branch)
ad49de89 4881 wb_dirtys(regs[i].regmap,regs[i].dirty);
57871462 4882 }
b14b6a8f 4883 else if(stubs[n].d!=TAKEN) {
ad49de89 4884 wb_dirtys(branch_regs[i].regmap,branch_regs[i].dirty);
57871462 4885 }
4886 else {
ad49de89 4887 if(internal_branch(ba[i]))
4888 wb_needed_dirtys(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]);
57871462 4889 }
b14b6a8f 4890 if(stubs[n].c!=-1)
57871462 4891 {
4892 // Save PC as return address
b14b6a8f 4893 emit_movimm(stubs[n].c,EAX);
643aeae3 4894 emit_writeword(EAX,&pcaddr);
57871462 4895 }
4896 else
4897 {
4898 // Return address depends on which way the branch goes
cf95b4f0 4899 if(dops[i].itype==CJUMP||dops[i].itype==SJUMP)
57871462 4900 {
cf95b4f0 4901 int s1l=get_reg(branch_regs[i].regmap,dops[i].rs1);
4902 int s2l=get_reg(branch_regs[i].regmap,dops[i].rs2);
4903 if(dops[i].rs1==0)
57871462 4904 {
ad49de89 4905 s1l=s2l;
4906 s2l=-1;
57871462 4907 }
cf95b4f0 4908 else if(dops[i].rs2==0)
57871462 4909 {
ad49de89 4910 s2l=-1;
57871462 4911 }
4912 assert(s1l>=0);
4913 #ifdef DESTRUCTIVE_WRITEBACK
cf95b4f0 4914 if(dops[i].rs1) {
ad49de89 4915 if((branch_regs[i].dirty>>s1l)&&1)
cf95b4f0 4916 emit_loadreg(dops[i].rs1,s1l);
9f51b4b9 4917 }
57871462 4918 else {
ad49de89 4919 if((branch_regs[i].dirty>>s1l)&1)
cf95b4f0 4920 emit_loadreg(dops[i].rs2,s1l);
57871462 4921 }
4922 if(s2l>=0)
ad49de89 4923 if((branch_regs[i].dirty>>s2l)&1)
cf95b4f0 4924 emit_loadreg(dops[i].rs2,s2l);
57871462 4925 #endif
4926 int hr=0;
5194fb95 4927 int addr=-1,alt=-1,ntaddr=-1;
57871462 4928 while(hr<HOST_REGS)
4929 {
4930 if(hr!=EXCLUDE_REG && hr!=HOST_CCREG &&
cf95b4f0 4931 (branch_regs[i].regmap[hr]&63)!=dops[i].rs1 &&
4932 (branch_regs[i].regmap[hr]&63)!=dops[i].rs2 )
57871462 4933 {
4934 addr=hr++;break;
4935 }
4936 hr++;
4937 }
4938 while(hr<HOST_REGS)
4939 {
4940 if(hr!=EXCLUDE_REG && hr!=HOST_CCREG &&
cf95b4f0 4941 (branch_regs[i].regmap[hr]&63)!=dops[i].rs1 &&
4942 (branch_regs[i].regmap[hr]&63)!=dops[i].rs2 )
57871462 4943 {
4944 alt=hr++;break;
4945 }
4946 hr++;
4947 }
cf95b4f0 4948 if((dops[i].opcode&0x2E)==6) // BLEZ/BGTZ needs another register
57871462 4949 {
4950 while(hr<HOST_REGS)
4951 {
4952 if(hr!=EXCLUDE_REG && hr!=HOST_CCREG &&
cf95b4f0 4953 (branch_regs[i].regmap[hr]&63)!=dops[i].rs1 &&
4954 (branch_regs[i].regmap[hr]&63)!=dops[i].rs2 )
57871462 4955 {
4956 ntaddr=hr;break;
4957 }
4958 hr++;
4959 }
4960 assert(hr<HOST_REGS);
4961 }
cf95b4f0 4962 if((dops[i].opcode&0x2f)==4) // BEQ
57871462 4963 {
4964 #ifdef HAVE_CMOV_IMM
ad49de89 4965 if(s2l>=0) emit_cmp(s1l,s2l);
4966 else emit_test(s1l,s1l);
4967 emit_cmov2imm_e_ne_compact(ba[i],start+i*4+8,addr);
4968 #else
4969 emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
4970 if(s2l>=0) emit_cmp(s1l,s2l);
4971 else emit_test(s1l,s1l);
4972 emit_cmovne_reg(alt,addr);
57871462 4973 #endif
57871462 4974 }
cf95b4f0 4975 if((dops[i].opcode&0x2f)==5) // BNE
57871462 4976 {
4977 #ifdef HAVE_CMOV_IMM
ad49de89 4978 if(s2l>=0) emit_cmp(s1l,s2l);
4979 else emit_test(s1l,s1l);
4980 emit_cmov2imm_e_ne_compact(start+i*4+8,ba[i],addr);
4981 #else
4982 emit_mov2imm_compact(start+i*4+8,addr,ba[i],alt);
4983 if(s2l>=0) emit_cmp(s1l,s2l);
4984 else emit_test(s1l,s1l);
4985 emit_cmovne_reg(alt,addr);
57871462 4986 #endif
57871462 4987 }
cf95b4f0 4988 if((dops[i].opcode&0x2f)==6) // BLEZ
57871462 4989 {
4990 //emit_movimm(ba[i],alt);
4991 //emit_movimm(start+i*4+8,addr);
4992 emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
4993 emit_cmpimm(s1l,1);
57871462 4994 emit_cmovl_reg(alt,addr);
57871462 4995 }
cf95b4f0 4996 if((dops[i].opcode&0x2f)==7) // BGTZ
57871462 4997 {
4998 //emit_movimm(ba[i],addr);
4999 //emit_movimm(start+i*4+8,ntaddr);
5000 emit_mov2imm_compact(ba[i],addr,start+i*4+8,ntaddr);
5001 emit_cmpimm(s1l,1);
57871462 5002 emit_cmovl_reg(ntaddr,addr);
57871462 5003 }
cf95b4f0 5004 if((dops[i].opcode==1)&&(dops[i].opcode2&0x2D)==0) // BLTZ
57871462 5005 {
5006 //emit_movimm(ba[i],alt);
5007 //emit_movimm(start+i*4+8,addr);
5008 emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
ad49de89 5009 emit_test(s1l,s1l);
57871462 5010 emit_cmovs_reg(alt,addr);
5011 }
cf95b4f0 5012 if((dops[i].opcode==1)&&(dops[i].opcode2&0x2D)==1) // BGEZ
57871462 5013 {
5014 //emit_movimm(ba[i],addr);
5015 //emit_movimm(start+i*4+8,alt);
5016 emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
ad49de89 5017 emit_test(s1l,s1l);
57871462 5018 emit_cmovs_reg(alt,addr);
5019 }
cf95b4f0 5020 if(dops[i].opcode==0x11 && dops[i].opcode2==0x08 ) {
57871462 5021 if(source[i]&0x10000) // BC1T
5022 {
5023 //emit_movimm(ba[i],alt);
5024 //emit_movimm(start+i*4+8,addr);
5025 emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
5026 emit_testimm(s1l,0x800000);
5027 emit_cmovne_reg(alt,addr);
5028 }
5029 else // BC1F
5030 {
5031 //emit_movimm(ba[i],addr);
5032 //emit_movimm(start+i*4+8,alt);
5033 emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
5034 emit_testimm(s1l,0x800000);
5035 emit_cmovne_reg(alt,addr);
5036 }
5037 }
643aeae3 5038 emit_writeword(addr,&pcaddr);
57871462 5039 }
5040 else
cf95b4f0 5041 if(dops[i].itype==RJUMP)
57871462 5042 {
cf95b4f0 5043 int r=get_reg(branch_regs[i].regmap,dops[i].rs1);
4919de1e 5044 if (ds_writes_rjump_rs(i)) {
57871462 5045 r=get_reg(branch_regs[i].regmap,RTEMP);
5046 }
643aeae3 5047 emit_writeword(r,&pcaddr);
57871462 5048 }
7c3a5182 5049 else {SysPrintf("Unknown branch type in do_ccstub\n");abort();}
57871462 5050 }
5051 // Update cycle count
5052 assert(branch_regs[i].regmap[HOST_CCREG]==CCREG||branch_regs[i].regmap[HOST_CCREG]==-1);
2330734f 5053 if(stubs[n].a) emit_addimm(HOST_CCREG,(int)stubs[n].a,HOST_CCREG);
2a014d73 5054 emit_far_call(cc_interrupt);
2330734f 5055 if(stubs[n].a) emit_addimm(HOST_CCREG,-(int)stubs[n].a,HOST_CCREG);
b14b6a8f 5056 if(stubs[n].d==TAKEN) {
ad49de89 5057 if(internal_branch(ba[i]))
57871462 5058 load_needed_regs(branch_regs[i].regmap,regs[(ba[i]-start)>>2].regmap_entry);
cf95b4f0 5059 else if(dops[i].itype==RJUMP) {
57871462 5060 if(get_reg(branch_regs[i].regmap,RTEMP)>=0)
643aeae3 5061 emit_readword(&pcaddr,get_reg(branch_regs[i].regmap,RTEMP));
57871462 5062 else
cf95b4f0 5063 emit_loadreg(dops[i].rs1,get_reg(branch_regs[i].regmap,dops[i].rs1));
57871462 5064 }
b14b6a8f 5065 }else if(stubs[n].d==NOTTAKEN) {
57871462 5066 if(i<slen-2) load_needed_regs(branch_regs[i].regmap,regmap_pre[i+2]);
5067 else load_all_regs(branch_regs[i].regmap);
b14b6a8f 5068 }else if(stubs[n].d==NULLDS) {
57871462 5069 // Delay slot instruction is nullified ("likely" branch)
5070 if(i<slen-2) load_needed_regs(regs[i].regmap,regmap_pre[i+2]);
5071 else load_all_regs(regs[i].regmap);
5072 }else{
5073 load_all_regs(branch_regs[i].regmap);
5074 }
d1e4ebd9 5075 if (stubs[n].retaddr)
5076 emit_jmp(stubs[n].retaddr);
5077 else
5078 do_jump_vaddr(stubs[n].e);
57871462 5079}
5080
643aeae3 5081static void add_to_linker(void *addr, u_int target, int ext)
57871462 5082{
643aeae3 5083 assert(linkcount < ARRAY_SIZE(link_addr));
5084 link_addr[linkcount].addr = addr;
5085 link_addr[linkcount].target = target;
5086 link_addr[linkcount].ext = ext;
57871462 5087 linkcount++;
5088}
5089
eba830cd 5090static void ujump_assemble_write_ra(int i)
5091{
5092 int rt;
5093 unsigned int return_address;
5094 rt=get_reg(branch_regs[i].regmap,31);
5095 assem_debug("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5096 //assert(rt>=0);
5097 return_address=start+i*4+8;
5098 if(rt>=0) {
5099 #ifdef USE_MINI_HT
cf95b4f0 5100 if(internal_branch(return_address)&&dops[i+1].rt1!=31) {
eba830cd 5101 int temp=-1; // note: must be ds-safe
5102 #ifdef HOST_TEMPREG
5103 temp=HOST_TEMPREG;
5104 #endif
5105 if(temp>=0) do_miniht_insert(return_address,rt,temp);
5106 else emit_movimm(return_address,rt);
5107 }
5108 else
5109 #endif
5110 {
5111 #ifdef REG_PREFETCH
9f51b4b9 5112 if(temp>=0)
eba830cd 5113 {
643aeae3 5114 if(i_regmap[temp]!=PTEMP) emit_movimm((uintptr_t)hash_table_get(return_address),temp);
eba830cd 5115 }
5116 #endif
5117 emit_movimm(return_address,rt); // PC into link register
5118 #ifdef IMM_PREFETCH
df4dc2b1 5119 emit_prefetch(hash_table_get(return_address));
eba830cd 5120 #endif
5121 }
5122 }
5123}
5124
2330734f 5125static void ujump_assemble(int i, const struct regstat *i_regs)
57871462 5126{
eba830cd 5127 int ra_done=0;
57871462 5128 if(i==(ba[i]-start)>>2) assem_debug("idle loop\n");
5129 address_generation(i+1,i_regs,regs[i].regmap_entry);
5130 #ifdef REG_PREFETCH
5131 int temp=get_reg(branch_regs[i].regmap,PTEMP);
cf95b4f0 5132 if(dops[i].rt1==31&&temp>=0)
57871462 5133 {
581335b0 5134 signed char *i_regmap=i_regs->regmap;
57871462 5135 int return_address=start+i*4+8;
9f51b4b9 5136 if(get_reg(branch_regs[i].regmap,31)>0)
643aeae3 5137 if(i_regmap[temp]==PTEMP) emit_movimm((uintptr_t)hash_table_get(return_address),temp);
57871462 5138 }
5139 #endif
cf95b4f0 5140 if(dops[i].rt1==31&&(dops[i].rt1==dops[i+1].rs1||dops[i].rt1==dops[i+1].rs2)) {
eba830cd 5141 ujump_assemble_write_ra(i); // writeback ra for DS
5142 ra_done=1;
57871462 5143 }
4ef8f67d 5144 ds_assemble(i+1,i_regs);
5145 uint64_t bc_unneeded=branch_regs[i].u;
cf95b4f0 5146 bc_unneeded|=1|(1LL<<dops[i].rt1);
ad49de89 5147 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,bc_unneeded);
5148 load_regs(regs[i].regmap,branch_regs[i].regmap,CCREG,CCREG);
cf95b4f0 5149 if(!ra_done&&dops[i].rt1==31)
eba830cd 5150 ujump_assemble_write_ra(i);
57871462 5151 int cc,adj;
5152 cc=get_reg(branch_regs[i].regmap,CCREG);
5153 assert(cc==HOST_CCREG);
ad49de89 5154 store_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]);
57871462 5155 #ifdef REG_PREFETCH
cf95b4f0 5156 if(dops[i].rt1==31&&temp>=0) emit_prefetchreg(temp);
57871462 5157 #endif
5158 do_cc(i,branch_regs[i].regmap,&adj,ba[i],TAKEN,0);
2330734f 5159 if(adj) emit_addimm(cc, ccadj[i] + CLOCK_ADJUST(2) - adj, cc);
ad49de89 5160 load_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]);
5161 if(internal_branch(ba[i]))
57871462 5162 assem_debug("branch: internal\n");
5163 else
5164 assem_debug("branch: external\n");
cf95b4f0 5165 if (internal_branch(ba[i]) && dops[(ba[i]-start)>>2].is_ds) {
57871462 5166 ds_assemble_entry(i);
5167 }
5168 else {
ad49de89 5169 add_to_linker(out,ba[i],internal_branch(ba[i]));
57871462 5170 emit_jmp(0);
5171 }
5172}
5173
eba830cd 5174static void rjump_assemble_write_ra(int i)
5175{
5176 int rt,return_address;
cf95b4f0 5177 assert(dops[i+1].rt1!=dops[i].rt1);
5178 assert(dops[i+1].rt2!=dops[i].rt1);
5179 rt=get_reg(branch_regs[i].regmap,dops[i].rt1);
eba830cd 5180 assem_debug("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5181 assert(rt>=0);
5182 return_address=start+i*4+8;
5183 #ifdef REG_PREFETCH
9f51b4b9 5184 if(temp>=0)
eba830cd 5185 {
643aeae3 5186 if(i_regmap[temp]!=PTEMP) emit_movimm((uintptr_t)hash_table_get(return_address),temp);
eba830cd 5187 }
5188 #endif
5189 emit_movimm(return_address,rt); // PC into link register
5190 #ifdef IMM_PREFETCH
df4dc2b1 5191 emit_prefetch(hash_table_get(return_address));
eba830cd 5192 #endif
5193}
5194
2330734f 5195static void rjump_assemble(int i, const struct regstat *i_regs)
57871462 5196{
57871462 5197 int temp;
581335b0 5198 int rs,cc;
eba830cd 5199 int ra_done=0;
cf95b4f0 5200 rs=get_reg(branch_regs[i].regmap,dops[i].rs1);
57871462 5201 assert(rs>=0);
4919de1e 5202 if (ds_writes_rjump_rs(i)) {
57871462 5203 // Delay slot abuse, make a copy of the branch address register
5204 temp=get_reg(branch_regs[i].regmap,RTEMP);
5205 assert(temp>=0);
5206 assert(regs[i].regmap[temp]==RTEMP);
5207 emit_mov(rs,temp);
5208 rs=temp;
5209 }
5210 address_generation(i+1,i_regs,regs[i].regmap_entry);
5211 #ifdef REG_PREFETCH
cf95b4f0 5212 if(dops[i].rt1==31)
57871462 5213 {
5214 if((temp=get_reg(branch_regs[i].regmap,PTEMP))>=0) {
581335b0 5215 signed char *i_regmap=i_regs->regmap;
57871462 5216 int return_address=start+i*4+8;
643aeae3 5217 if(i_regmap[temp]==PTEMP) emit_movimm((uintptr_t)hash_table_get(return_address),temp);
57871462 5218 }
5219 }
5220 #endif
5221 #ifdef USE_MINI_HT
cf95b4f0 5222 if(dops[i].rs1==31) {
57871462 5223 int rh=get_reg(regs[i].regmap,RHASH);
5224 if(rh>=0) do_preload_rhash(rh);
5225 }
5226 #endif
cf95b4f0 5227 if(dops[i].rt1!=0&&(dops[i].rt1==dops[i+1].rs1||dops[i].rt1==dops[i+1].rs2)) {
eba830cd 5228 rjump_assemble_write_ra(i);
5229 ra_done=1;
57871462 5230 }
d5910d5d 5231 ds_assemble(i+1,i_regs);
5232 uint64_t bc_unneeded=branch_regs[i].u;
cf95b4f0 5233 bc_unneeded|=1|(1LL<<dops[i].rt1);
5234 bc_unneeded&=~(1LL<<dops[i].rs1);
ad49de89 5235 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,bc_unneeded);
cf95b4f0 5236 load_regs(regs[i].regmap,branch_regs[i].regmap,dops[i].rs1,CCREG);
5237 if(!ra_done&&dops[i].rt1!=0)
eba830cd 5238 rjump_assemble_write_ra(i);
57871462 5239 cc=get_reg(branch_regs[i].regmap,CCREG);
5240 assert(cc==HOST_CCREG);
581335b0 5241 (void)cc;
57871462 5242 #ifdef USE_MINI_HT
5243 int rh=get_reg(branch_regs[i].regmap,RHASH);
5244 int ht=get_reg(branch_regs[i].regmap,RHTBL);
cf95b4f0 5245 if(dops[i].rs1==31) {
57871462 5246 if(regs[i].regmap[rh]!=RHASH) do_preload_rhash(rh);
5247 do_preload_rhtbl(ht);
5248 do_rhash(rs,rh);
5249 }
5250 #endif
ad49de89 5251 store_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,-1);
57871462 5252 #ifdef DESTRUCTIVE_WRITEBACK
ad49de89 5253 if((branch_regs[i].dirty>>rs)&1) {
cf95b4f0 5254 if(dops[i].rs1!=dops[i+1].rt1&&dops[i].rs1!=dops[i+1].rt2) {
5255 emit_loadreg(dops[i].rs1,rs);
57871462 5256 }
5257 }
5258 #endif
5259 #ifdef REG_PREFETCH
cf95b4f0 5260 if(dops[i].rt1==31&&temp>=0) emit_prefetchreg(temp);
57871462 5261 #endif
5262 #ifdef USE_MINI_HT
cf95b4f0 5263 if(dops[i].rs1==31) {
57871462 5264 do_miniht_load(ht,rh);
5265 }
5266 #endif
5267 //do_cc(i,branch_regs[i].regmap,&adj,-1,TAKEN);
5268 //if(adj) emit_addimm(cc,2*(ccadj[i]+2-adj),cc); // ??? - Shouldn't happen
5269 //assert(adj==0);
2330734f 5270 emit_addimm_and_set_flags(ccadj[i] + CLOCK_ADJUST(2), HOST_CCREG);
d1e4ebd9 5271 add_stub(CC_STUB,out,NULL,0,i,-1,TAKEN,rs);
cf95b4f0 5272 if(dops[i+1].itype==COP0&&(source[i+1]&0x3f)==0x10)
911f2d55 5273 // special case for RFE
5274 emit_jmp(0);
5275 else
71e490c5 5276 emit_jns(0);
ad49de89 5277 //load_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,-1);
57871462 5278 #ifdef USE_MINI_HT
cf95b4f0 5279 if(dops[i].rs1==31) {
57871462 5280 do_miniht_jump(rs,rh,ht);
5281 }
5282 else
5283 #endif
5284 {
d1e4ebd9 5285 do_jump_vaddr(rs);
57871462 5286 }
57871462 5287 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
cf95b4f0 5288 if(dops[i].rt1!=31&&i<slen-2&&(((u_int)out)&7)) emit_mov(13,13);
57871462 5289 #endif
5290}
5291
2330734f 5292static void cjump_assemble(int i, const struct regstat *i_regs)
57871462 5293{
2330734f 5294 const signed char *i_regmap = i_regs->regmap;
57871462 5295 int cc;
5296 int match;
ad49de89 5297 match=match_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]);
57871462 5298 assem_debug("match=%d\n",match);
ad49de89 5299 int s1l,s2l;
57871462 5300 int unconditional=0,nop=0;
57871462 5301 int invert=0;
ad49de89 5302 int internal=internal_branch(ba[i]);
57871462 5303 if(i==(ba[i]-start)>>2) assem_debug("idle loop\n");
57871462 5304 if(!match) invert=1;
5305 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5306 if(i>(ba[i]-start)>>2) invert=1;
5307 #endif
3968e69e 5308 #ifdef __aarch64__
5309 invert=1; // because of near cond. branches
5310 #endif
9f51b4b9 5311
cf95b4f0 5312 if(dops[i].ooo) {
5313 s1l=get_reg(branch_regs[i].regmap,dops[i].rs1);
5314 s2l=get_reg(branch_regs[i].regmap,dops[i].rs2);
57871462 5315 }
5316 else {
cf95b4f0 5317 s1l=get_reg(i_regmap,dops[i].rs1);
5318 s2l=get_reg(i_regmap,dops[i].rs2);
57871462 5319 }
cf95b4f0 5320 if(dops[i].rs1==0&&dops[i].rs2==0)
57871462 5321 {
cf95b4f0 5322 if(dops[i].opcode&1) nop=1;
57871462 5323 else unconditional=1;
cf95b4f0 5324 //assert(dops[i].opcode!=5);
5325 //assert(dops[i].opcode!=7);
5326 //assert(dops[i].opcode!=0x15);
5327 //assert(dops[i].opcode!=0x17);
57871462 5328 }
cf95b4f0 5329 else if(dops[i].rs1==0)
57871462 5330 {
ad49de89 5331 s1l=s2l;
5332 s2l=-1;
57871462 5333 }
cf95b4f0 5334 else if(dops[i].rs2==0)
57871462 5335 {
ad49de89 5336 s2l=-1;
57871462 5337 }
5338
cf95b4f0 5339 if(dops[i].ooo) {
57871462 5340 // Out of order execution (delay slot first)
5341 //printf("OOOE\n");
5342 address_generation(i+1,i_regs,regs[i].regmap_entry);
5343 ds_assemble(i+1,i_regs);
5344 int adj;
5345 uint64_t bc_unneeded=branch_regs[i].u;
cf95b4f0 5346 bc_unneeded&=~((1LL<<dops[i].rs1)|(1LL<<dops[i].rs2));
57871462 5347 bc_unneeded|=1;
ad49de89 5348 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,bc_unneeded);
cf95b4f0 5349 load_regs(regs[i].regmap,branch_regs[i].regmap,dops[i].rs1,dops[i].rs2);
ad49de89 5350 load_regs(regs[i].regmap,branch_regs[i].regmap,CCREG,CCREG);
57871462 5351 cc=get_reg(branch_regs[i].regmap,CCREG);
5352 assert(cc==HOST_CCREG);
9f51b4b9 5353 if(unconditional)
ad49de89 5354 store_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]);
57871462 5355 //do_cc(i,branch_regs[i].regmap,&adj,unconditional?ba[i]:-1,unconditional);
5356 //assem_debug("cycle count (adj)\n");
5357 if(unconditional) {
5358 do_cc(i,branch_regs[i].regmap,&adj,ba[i],TAKEN,0);
5359 if(i!=(ba[i]-start)>>2 || source[i+1]!=0) {
2330734f 5360 if(adj) emit_addimm(cc, ccadj[i] + CLOCK_ADJUST(2) - adj, cc);
ad49de89 5361 load_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]);
57871462 5362 if(internal)
5363 assem_debug("branch: internal\n");
5364 else
5365 assem_debug("branch: external\n");
cf95b4f0 5366 if (internal && dops[(ba[i]-start)>>2].is_ds) {
57871462 5367 ds_assemble_entry(i);
5368 }
5369 else {
643aeae3 5370 add_to_linker(out,ba[i],internal);
57871462 5371 emit_jmp(0);
5372 }
5373 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5374 if(((u_int)out)&7) emit_addnop(0);
5375 #endif
5376 }
5377 }
5378 else if(nop) {
2330734f 5379 emit_addimm_and_set_flags(ccadj[i] + CLOCK_ADJUST(2), cc);
b14b6a8f 5380 void *jaddr=out;
57871462 5381 emit_jns(0);
b14b6a8f 5382 add_stub(CC_STUB,jaddr,out,0,i,start+i*4+8,NOTTAKEN,0);
57871462 5383 }
5384 else {
df4dc2b1 5385 void *taken = NULL, *nottaken = NULL, *nottaken1 = NULL;
57871462 5386 do_cc(i,branch_regs[i].regmap,&adj,-1,0,invert);
2330734f 5387 if(adj&&!invert) emit_addimm(cc, ccadj[i] + CLOCK_ADJUST(2) - adj, cc);
9f51b4b9 5388
57871462 5389 //printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5390 assert(s1l>=0);
cf95b4f0 5391 if(dops[i].opcode==4) // BEQ
57871462 5392 {
5393 if(s2l>=0) emit_cmp(s1l,s2l);
5394 else emit_test(s1l,s1l);
5395 if(invert){
df4dc2b1 5396 nottaken=out;
7c3a5182 5397 emit_jne(DJT_1);
57871462 5398 }else{
643aeae3 5399 add_to_linker(out,ba[i],internal);
57871462 5400 emit_jeq(0);
5401 }
5402 }
cf95b4f0 5403 if(dops[i].opcode==5) // BNE
57871462 5404 {
5405 if(s2l>=0) emit_cmp(s1l,s2l);
5406 else emit_test(s1l,s1l);
5407 if(invert){
df4dc2b1 5408 nottaken=out;
7c3a5182 5409 emit_jeq(DJT_1);
57871462 5410 }else{
643aeae3 5411 add_to_linker(out,ba[i],internal);
57871462 5412 emit_jne(0);
5413 }
5414 }
cf95b4f0 5415 if(dops[i].opcode==6) // BLEZ
57871462 5416 {
5417 emit_cmpimm(s1l,1);
5418 if(invert){
df4dc2b1 5419 nottaken=out;
7c3a5182 5420 emit_jge(DJT_1);
57871462 5421 }else{
643aeae3 5422 add_to_linker(out,ba[i],internal);
57871462 5423 emit_jl(0);
5424 }
5425 }
cf95b4f0 5426 if(dops[i].opcode==7) // BGTZ
57871462 5427 {
5428 emit_cmpimm(s1l,1);
5429 if(invert){
df4dc2b1 5430 nottaken=out;
7c3a5182 5431 emit_jl(DJT_1);
57871462 5432 }else{
643aeae3 5433 add_to_linker(out,ba[i],internal);
57871462 5434 emit_jge(0);
5435 }
5436 }
5437 if(invert) {
df4dc2b1 5438 if(taken) set_jump_target(taken, out);
57871462 5439 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
cf95b4f0 5440 if (match && (!internal || !dops[(ba[i]-start)>>2].is_ds)) {
57871462 5441 if(adj) {
2330734f 5442 emit_addimm(cc,-adj,cc);
643aeae3 5443 add_to_linker(out,ba[i],internal);
57871462 5444 }else{
5445 emit_addnop(13);
643aeae3 5446 add_to_linker(out,ba[i],internal*2);
57871462 5447 }
5448 emit_jmp(0);
5449 }else
5450 #endif
5451 {
2330734f 5452 if(adj) emit_addimm(cc,-adj,cc);
ad49de89 5453 store_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]);
5454 load_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]);
57871462 5455 if(internal)
5456 assem_debug("branch: internal\n");
5457 else
5458 assem_debug("branch: external\n");
cf95b4f0 5459 if (internal && dops[(ba[i] - start) >> 2].is_ds) {
57871462 5460 ds_assemble_entry(i);
5461 }
5462 else {
643aeae3 5463 add_to_linker(out,ba[i],internal);
57871462 5464 emit_jmp(0);
5465 }
5466 }
df4dc2b1 5467 set_jump_target(nottaken, out);
57871462 5468 }
5469
df4dc2b1 5470 if(nottaken1) set_jump_target(nottaken1, out);
57871462 5471 if(adj) {
2330734f 5472 if(!invert) emit_addimm(cc,adj,cc);
57871462 5473 }
5474 } // (!unconditional)
5475 } // if(ooo)
5476 else
5477 {
5478 // In-order execution (branch first)
df4dc2b1 5479 void *taken = NULL, *nottaken = NULL, *nottaken1 = NULL;
57871462 5480 if(!unconditional&&!nop) {
57871462 5481 //printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5482 assert(s1l>=0);
cf95b4f0 5483 if((dops[i].opcode&0x2f)==4) // BEQ
57871462 5484 {
5485 if(s2l>=0) emit_cmp(s1l,s2l);
5486 else emit_test(s1l,s1l);
df4dc2b1 5487 nottaken=out;
7c3a5182 5488 emit_jne(DJT_2);
57871462 5489 }
cf95b4f0 5490 if((dops[i].opcode&0x2f)==5) // BNE
57871462 5491 {
5492 if(s2l>=0) emit_cmp(s1l,s2l);
5493 else emit_test(s1l,s1l);
df4dc2b1 5494 nottaken=out;
7c3a5182 5495 emit_jeq(DJT_2);
57871462 5496 }
cf95b4f0 5497 if((dops[i].opcode&0x2f)==6) // BLEZ
57871462 5498 {
5499 emit_cmpimm(s1l,1);
df4dc2b1 5500 nottaken=out;
7c3a5182 5501 emit_jge(DJT_2);
57871462 5502 }
cf95b4f0 5503 if((dops[i].opcode&0x2f)==7) // BGTZ
57871462 5504 {
5505 emit_cmpimm(s1l,1);
df4dc2b1 5506 nottaken=out;
7c3a5182 5507 emit_jl(DJT_2);
57871462 5508 }
5509 } // if(!unconditional)
5510 int adj;
5511 uint64_t ds_unneeded=branch_regs[i].u;
cf95b4f0 5512 ds_unneeded&=~((1LL<<dops[i+1].rs1)|(1LL<<dops[i+1].rs2));
57871462 5513 ds_unneeded|=1;
57871462 5514 // branch taken
5515 if(!nop) {
df4dc2b1 5516 if(taken) set_jump_target(taken, out);
57871462 5517 assem_debug("1:\n");
ad49de89 5518 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,ds_unneeded);
57871462 5519 // load regs
cf95b4f0 5520 load_regs(regs[i].regmap,branch_regs[i].regmap,dops[i+1].rs1,dops[i+1].rs2);
57871462 5521 address_generation(i+1,&branch_regs[i],0);
37387d8b 5522 if (ram_offset)
5523 load_regs(regs[i].regmap,branch_regs[i].regmap,ROREG,ROREG);
ad49de89 5524 load_regs(regs[i].regmap,branch_regs[i].regmap,CCREG,INVCP);
57871462 5525 ds_assemble(i+1,&branch_regs[i]);
5526 cc=get_reg(branch_regs[i].regmap,CCREG);
5527 if(cc==-1) {
5528 emit_loadreg(CCREG,cc=HOST_CCREG);
5529 // CHECK: Is the following instruction (fall thru) allocated ok?
5530 }
5531 assert(cc==HOST_CCREG);
ad49de89 5532 store_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]);
57871462 5533 do_cc(i,i_regmap,&adj,ba[i],TAKEN,0);
5534 assem_debug("cycle count (adj)\n");
2330734f 5535 if(adj) emit_addimm(cc, ccadj[i] + CLOCK_ADJUST(2) - adj, cc);
ad49de89 5536 load_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]);
57871462 5537 if(internal)
5538 assem_debug("branch: internal\n");
5539 else
5540 assem_debug("branch: external\n");
cf95b4f0 5541 if (internal && dops[(ba[i] - start) >> 2].is_ds) {
57871462 5542 ds_assemble_entry(i);
5543 }
5544 else {
643aeae3 5545 add_to_linker(out,ba[i],internal);
57871462 5546 emit_jmp(0);
5547 }
5548 }
5549 // branch not taken
57871462 5550 if(!unconditional) {
df4dc2b1 5551 if(nottaken1) set_jump_target(nottaken1, out);
5552 set_jump_target(nottaken, out);
57871462 5553 assem_debug("2:\n");
fe807a8a 5554 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,ds_unneeded);
37387d8b 5555 // load regs
fe807a8a 5556 load_regs(regs[i].regmap,branch_regs[i].regmap,dops[i+1].rs1,dops[i+1].rs2);
5557 address_generation(i+1,&branch_regs[i],0);
37387d8b 5558 if (ram_offset)
5559 load_regs(regs[i].regmap,branch_regs[i].regmap,ROREG,ROREG);
5560 load_regs(regs[i].regmap,branch_regs[i].regmap,CCREG,INVCP);
fe807a8a 5561 ds_assemble(i+1,&branch_regs[i]);
57871462 5562 cc=get_reg(branch_regs[i].regmap,CCREG);
fe807a8a 5563 if (cc == -1) {
57871462 5564 // Cycle count isn't in a register, temporarily load it then write it out
5565 emit_loadreg(CCREG,HOST_CCREG);
2330734f 5566 emit_addimm_and_set_flags(ccadj[i] + CLOCK_ADJUST(2), HOST_CCREG);
b14b6a8f 5567 void *jaddr=out;
57871462 5568 emit_jns(0);
b14b6a8f 5569 add_stub(CC_STUB,jaddr,out,0,i,start+i*4+8,NOTTAKEN,0);
57871462 5570 emit_storereg(CCREG,HOST_CCREG);
5571 }
5572 else{
5573 cc=get_reg(i_regmap,CCREG);
5574 assert(cc==HOST_CCREG);
2330734f 5575 emit_addimm_and_set_flags(ccadj[i] + CLOCK_ADJUST(2), cc);
b14b6a8f 5576 void *jaddr=out;
57871462 5577 emit_jns(0);
fe807a8a 5578 add_stub(CC_STUB,jaddr,out,0,i,start+i*4+8,NOTTAKEN,0);
57871462 5579 }
5580 }
5581 }
5582}
5583
2330734f 5584static void sjump_assemble(int i, const struct regstat *i_regs)
57871462 5585{
2330734f 5586 const signed char *i_regmap = i_regs->regmap;
57871462 5587 int cc;
5588 int match;
ad49de89 5589 match=match_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]);
57871462 5590 assem_debug("smatch=%d\n",match);
ad49de89 5591 int s1l;
57871462 5592 int unconditional=0,nevertaken=0;
57871462 5593 int invert=0;
ad49de89 5594 int internal=internal_branch(ba[i]);
57871462 5595 if(i==(ba[i]-start)>>2) assem_debug("idle loop\n");
57871462 5596 if(!match) invert=1;
5597 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5598 if(i>(ba[i]-start)>>2) invert=1;
5599 #endif
3968e69e 5600 #ifdef __aarch64__
5601 invert=1; // because of near cond. branches
5602 #endif
57871462 5603
cf95b4f0 5604 //if(dops[i].opcode2>=0x10) return; // FIXME (BxxZAL)
5605 //assert(dops[i].opcode2<0x10||dops[i].rs1==0); // FIXME (BxxZAL)
57871462 5606
cf95b4f0 5607 if(dops[i].ooo) {
5608 s1l=get_reg(branch_regs[i].regmap,dops[i].rs1);
57871462 5609 }
5610 else {
cf95b4f0 5611 s1l=get_reg(i_regmap,dops[i].rs1);
57871462 5612 }
cf95b4f0 5613 if(dops[i].rs1==0)
57871462 5614 {
cf95b4f0 5615 if(dops[i].opcode2&1) unconditional=1;
57871462 5616 else nevertaken=1;
5617 // These are never taken (r0 is never less than zero)
cf95b4f0 5618 //assert(dops[i].opcode2!=0);
5619 //assert(dops[i].opcode2!=2);
5620 //assert(dops[i].opcode2!=0x10);
5621 //assert(dops[i].opcode2!=0x12);
57871462 5622 }
57871462 5623
cf95b4f0 5624 if(dops[i].ooo) {
57871462 5625 // Out of order execution (delay slot first)
5626 //printf("OOOE\n");
5627 address_generation(i+1,i_regs,regs[i].regmap_entry);
5628 ds_assemble(i+1,i_regs);
5629 int adj;
5630 uint64_t bc_unneeded=branch_regs[i].u;
cf95b4f0 5631 bc_unneeded&=~((1LL<<dops[i].rs1)|(1LL<<dops[i].rs2));
57871462 5632 bc_unneeded|=1;
ad49de89 5633 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,bc_unneeded);
cf95b4f0 5634 load_regs(regs[i].regmap,branch_regs[i].regmap,dops[i].rs1,dops[i].rs1);
ad49de89 5635 load_regs(regs[i].regmap,branch_regs[i].regmap,CCREG,CCREG);
cf95b4f0 5636 if(dops[i].rt1==31) {
57871462 5637 int rt,return_address;
57871462 5638 rt=get_reg(branch_regs[i].regmap,31);
5639 assem_debug("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5640 if(rt>=0) {
5641 // Save the PC even if the branch is not taken
5642 return_address=start+i*4+8;
5643 emit_movimm(return_address,rt); // PC into link register
5644 #ifdef IMM_PREFETCH
df4dc2b1 5645 if(!nevertaken) emit_prefetch(hash_table_get(return_address));
57871462 5646 #endif
5647 }
5648 }
5649 cc=get_reg(branch_regs[i].regmap,CCREG);
5650 assert(cc==HOST_CCREG);
9f51b4b9 5651 if(unconditional)
ad49de89 5652 store_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]);
57871462 5653 //do_cc(i,branch_regs[i].regmap,&adj,unconditional?ba[i]:-1,unconditional);
5654 assem_debug("cycle count (adj)\n");
5655 if(unconditional) {
5656 do_cc(i,branch_regs[i].regmap,&adj,ba[i],TAKEN,0);
5657 if(i!=(ba[i]-start)>>2 || source[i+1]!=0) {
2330734f 5658 if(adj) emit_addimm(cc, ccadj[i] + CLOCK_ADJUST(2) - adj, cc);
ad49de89 5659 load_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]);
57871462 5660 if(internal)
5661 assem_debug("branch: internal\n");
5662 else
5663 assem_debug("branch: external\n");
cf95b4f0 5664 if (internal && dops[(ba[i] - start) >> 2].is_ds) {
57871462 5665 ds_assemble_entry(i);
5666 }
5667 else {
643aeae3 5668 add_to_linker(out,ba[i],internal);
57871462 5669 emit_jmp(0);
5670 }
5671 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5672 if(((u_int)out)&7) emit_addnop(0);
5673 #endif
5674 }
5675 }
5676 else if(nevertaken) {
2330734f 5677 emit_addimm_and_set_flags(ccadj[i] + CLOCK_ADJUST(2), cc);
b14b6a8f 5678 void *jaddr=out;
57871462 5679 emit_jns(0);
b14b6a8f 5680 add_stub(CC_STUB,jaddr,out,0,i,start+i*4+8,NOTTAKEN,0);
57871462 5681 }
5682 else {
df4dc2b1 5683 void *nottaken = NULL;
57871462 5684 do_cc(i,branch_regs[i].regmap,&adj,-1,0,invert);
2330734f 5685 if(adj&&!invert) emit_addimm(cc, ccadj[i] + CLOCK_ADJUST(2) - adj, cc);
57871462 5686 {
5687 assert(s1l>=0);
cf95b4f0 5688 if((dops[i].opcode2&0xf)==0) // BLTZ/BLTZAL
57871462 5689 {
5690 emit_test(s1l,s1l);
5691 if(invert){
df4dc2b1 5692 nottaken=out;
7c3a5182 5693 emit_jns(DJT_1);
57871462 5694 }else{
643aeae3 5695 add_to_linker(out,ba[i],internal);
57871462 5696 emit_js(0);
5697 }
5698 }
cf95b4f0 5699 if((dops[i].opcode2&0xf)==1) // BGEZ/BLTZAL
57871462 5700 {
5701 emit_test(s1l,s1l);
5702 if(invert){
df4dc2b1 5703 nottaken=out;
7c3a5182 5704 emit_js(DJT_1);
57871462 5705 }else{
643aeae3 5706 add_to_linker(out,ba[i],internal);
57871462 5707 emit_jns(0);
5708 }
5709 }
ad49de89 5710 }
9f51b4b9 5711
57871462 5712 if(invert) {
5713 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
cf95b4f0 5714 if (match && (!internal || !dops[(ba[i] - start) >> 2].is_ds)) {
57871462 5715 if(adj) {
2330734f 5716 emit_addimm(cc,-adj,cc);
643aeae3 5717 add_to_linker(out,ba[i],internal);
57871462 5718 }else{
5719 emit_addnop(13);
643aeae3 5720 add_to_linker(out,ba[i],internal*2);
57871462 5721 }
5722 emit_jmp(0);
5723 }else
5724 #endif
5725 {
2330734f 5726 if(adj) emit_addimm(cc,-adj,cc);
ad49de89 5727 store_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]);
5728 load_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]);
57871462 5729 if(internal)
5730 assem_debug("branch: internal\n");
5731 else
5732 assem_debug("branch: external\n");
cf95b4f0 5733 if (internal && dops[(ba[i] - start) >> 2].is_ds) {
57871462 5734 ds_assemble_entry(i);
5735 }
5736 else {
643aeae3 5737 add_to_linker(out,ba[i],internal);
57871462 5738 emit_jmp(0);
5739 }
5740 }
df4dc2b1 5741 set_jump_target(nottaken, out);
57871462 5742 }
5743
5744 if(adj) {
2330734f 5745 if(!invert) emit_addimm(cc,adj,cc);
57871462 5746 }
5747 } // (!unconditional)
5748 } // if(ooo)
5749 else
5750 {
5751 // In-order execution (branch first)
5752 //printf("IOE\n");
df4dc2b1 5753 void *nottaken = NULL;
cf95b4f0 5754 if(dops[i].rt1==31) {
a6491170 5755 int rt,return_address;
a6491170 5756 rt=get_reg(branch_regs[i].regmap,31);
5757 if(rt>=0) {
5758 // Save the PC even if the branch is not taken
5759 return_address=start+i*4+8;
5760 emit_movimm(return_address,rt); // PC into link register
5761 #ifdef IMM_PREFETCH
df4dc2b1 5762 emit_prefetch(hash_table_get(return_address));
a6491170 5763 #endif
5764 }
5765 }
57871462 5766 if(!unconditional) {
5767 //printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
57871462 5768 assert(s1l>=0);
cf95b4f0 5769 if((dops[i].opcode2&0x0d)==0) // BLTZ/BLTZL/BLTZAL/BLTZALL
57871462 5770 {
5771 emit_test(s1l,s1l);
df4dc2b1 5772 nottaken=out;
7c3a5182 5773 emit_jns(DJT_1);
57871462 5774 }
cf95b4f0 5775 if((dops[i].opcode2&0x0d)==1) // BGEZ/BGEZL/BGEZAL/BGEZALL
57871462 5776 {
5777 emit_test(s1l,s1l);
df4dc2b1 5778 nottaken=out;
7c3a5182 5779 emit_js(DJT_1);
57871462 5780 }
57871462 5781 } // if(!unconditional)
5782 int adj;
5783 uint64_t ds_unneeded=branch_regs[i].u;
cf95b4f0 5784 ds_unneeded&=~((1LL<<dops[i+1].rs1)|(1LL<<dops[i+1].rs2));
57871462 5785 ds_unneeded|=1;
57871462 5786 // branch taken
5787 if(!nevertaken) {
5788 //assem_debug("1:\n");
ad49de89 5789 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,ds_unneeded);
57871462 5790 // load regs
cf95b4f0 5791 load_regs(regs[i].regmap,branch_regs[i].regmap,dops[i+1].rs1,dops[i+1].rs2);
57871462 5792 address_generation(i+1,&branch_regs[i],0);
37387d8b 5793 if (ram_offset)
5794 load_regs(regs[i].regmap,branch_regs[i].regmap,ROREG,ROREG);
ad49de89 5795 load_regs(regs[i].regmap,branch_regs[i].regmap,CCREG,INVCP);
57871462 5796 ds_assemble(i+1,&branch_regs[i]);
5797 cc=get_reg(branch_regs[i].regmap,CCREG);
5798 if(cc==-1) {
5799 emit_loadreg(CCREG,cc=HOST_CCREG);
5800 // CHECK: Is the following instruction (fall thru) allocated ok?
5801 }
5802 assert(cc==HOST_CCREG);
ad49de89 5803 store_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]);
57871462 5804 do_cc(i,i_regmap,&adj,ba[i],TAKEN,0);
5805 assem_debug("cycle count (adj)\n");
2330734f 5806 if(adj) emit_addimm(cc, ccadj[i] + CLOCK_ADJUST(2) - adj, cc);
ad49de89 5807 load_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]);
57871462 5808 if(internal)
5809 assem_debug("branch: internal\n");
5810 else
5811 assem_debug("branch: external\n");
cf95b4f0 5812 if (internal && dops[(ba[i] - start) >> 2].is_ds) {
57871462 5813 ds_assemble_entry(i);
5814 }
5815 else {
643aeae3 5816 add_to_linker(out,ba[i],internal);
57871462 5817 emit_jmp(0);
5818 }
5819 }
5820 // branch not taken
57871462 5821 if(!unconditional) {
df4dc2b1 5822 set_jump_target(nottaken, out);
57871462 5823 assem_debug("1:\n");
fe807a8a 5824 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,ds_unneeded);
5825 load_regs(regs[i].regmap,branch_regs[i].regmap,dops[i+1].rs1,dops[i+1].rs2);
5826 address_generation(i+1,&branch_regs[i],0);
5827 load_regs(regs[i].regmap,branch_regs[i].regmap,CCREG,CCREG);
5828 ds_assemble(i+1,&branch_regs[i]);
57871462 5829 cc=get_reg(branch_regs[i].regmap,CCREG);
fe807a8a 5830 if (cc == -1) {
57871462 5831 // Cycle count isn't in a register, temporarily load it then write it out
5832 emit_loadreg(CCREG,HOST_CCREG);
2330734f 5833 emit_addimm_and_set_flags(ccadj[i] + CLOCK_ADJUST(2), HOST_CCREG);
b14b6a8f 5834 void *jaddr=out;
57871462 5835 emit_jns(0);
b14b6a8f 5836 add_stub(CC_STUB,jaddr,out,0,i,start+i*4+8,NOTTAKEN,0);
57871462 5837 emit_storereg(CCREG,HOST_CCREG);
5838 }
5839 else{
5840 cc=get_reg(i_regmap,CCREG);
5841 assert(cc==HOST_CCREG);
2330734f 5842 emit_addimm_and_set_flags(ccadj[i] + CLOCK_ADJUST(2), cc);
b14b6a8f 5843 void *jaddr=out;
57871462 5844 emit_jns(0);
fe807a8a 5845 add_stub(CC_STUB,jaddr,out,0,i,start+i*4+8,NOTTAKEN,0);
57871462 5846 }
5847 }
5848 }
5849}
5850
2330734f 5851static void pagespan_assemble(int i, const struct regstat *i_regs)
57871462 5852{
cf95b4f0 5853 int s1l=get_reg(i_regs->regmap,dops[i].rs1);
5854 int s2l=get_reg(i_regs->regmap,dops[i].rs2);
df4dc2b1 5855 void *taken = NULL;
5856 void *nottaken = NULL;
57871462 5857 int unconditional=0;
cf95b4f0 5858 if(dops[i].rs1==0)
57871462 5859 {
ad49de89 5860 s1l=s2l;
5861 s2l=-1;
57871462 5862 }
cf95b4f0 5863 else if(dops[i].rs2==0)
57871462 5864 {
ad49de89 5865 s2l=-1;
57871462 5866 }
5867 int hr=0;
581335b0 5868 int addr=-1,alt=-1,ntaddr=-1;
57871462 5869 if(i_regs->regmap[HOST_BTREG]<0) {addr=HOST_BTREG;}
5870 else {
5871 while(hr<HOST_REGS)
5872 {
5873 if(hr!=EXCLUDE_REG && hr!=HOST_CCREG &&
cf95b4f0 5874 (i_regs->regmap[hr]&63)!=dops[i].rs1 &&
5875 (i_regs->regmap[hr]&63)!=dops[i].rs2 )
57871462 5876 {
5877 addr=hr++;break;
5878 }
5879 hr++;
5880 }
5881 }
5882 while(hr<HOST_REGS)
5883 {
5884 if(hr!=EXCLUDE_REG && hr!=HOST_CCREG && hr!=HOST_BTREG &&
cf95b4f0 5885 (i_regs->regmap[hr]&63)!=dops[i].rs1 &&
5886 (i_regs->regmap[hr]&63)!=dops[i].rs2 )
57871462 5887 {
5888 alt=hr++;break;
5889 }
5890 hr++;
5891 }
cf95b4f0 5892 if((dops[i].opcode&0x2E)==6) // BLEZ/BGTZ needs another register
57871462 5893 {
5894 while(hr<HOST_REGS)
5895 {
5896 if(hr!=EXCLUDE_REG && hr!=HOST_CCREG && hr!=HOST_BTREG &&
cf95b4f0 5897 (i_regs->regmap[hr]&63)!=dops[i].rs1 &&
5898 (i_regs->regmap[hr]&63)!=dops[i].rs2 )
57871462 5899 {
5900 ntaddr=hr;break;
5901 }
5902 hr++;
5903 }
5904 }
5905 assert(hr<HOST_REGS);
cf95b4f0 5906 if((dops[i].opcode&0x2e)==4||dops[i].opcode==0x11) { // BEQ/BNE/BEQL/BNEL/BC1
ad49de89 5907 load_regs(regs[i].regmap_entry,regs[i].regmap,CCREG,CCREG);
57871462 5908 }
2330734f 5909 emit_addimm(HOST_CCREG, ccadj[i] + CLOCK_ADJUST(2), HOST_CCREG);
cf95b4f0 5910 if(dops[i].opcode==2) // J
57871462 5911 {
5912 unconditional=1;
5913 }
cf95b4f0 5914 if(dops[i].opcode==3) // JAL
57871462 5915 {
5916 // TODO: mini_ht
5917 int rt=get_reg(i_regs->regmap,31);
5918 emit_movimm(start+i*4+8,rt);
5919 unconditional=1;
5920 }
cf95b4f0 5921 if(dops[i].opcode==0&&(dops[i].opcode2&0x3E)==8) // JR/JALR
57871462 5922 {
5923 emit_mov(s1l,addr);
cf95b4f0 5924 if(dops[i].opcode2==9) // JALR
57871462 5925 {
cf95b4f0 5926 int rt=get_reg(i_regs->regmap,dops[i].rt1);
57871462 5927 emit_movimm(start+i*4+8,rt);
5928 }
5929 }
cf95b4f0 5930 if((dops[i].opcode&0x3f)==4) // BEQ
57871462 5931 {
cf95b4f0 5932 if(dops[i].rs1==dops[i].rs2)
57871462 5933 {
5934 unconditional=1;
5935 }
5936 else
5937 #ifdef HAVE_CMOV_IMM
ad49de89 5938 if(1) {
57871462 5939 if(s2l>=0) emit_cmp(s1l,s2l);
5940 else emit_test(s1l,s1l);
5941 emit_cmov2imm_e_ne_compact(ba[i],start+i*4+8,addr);
5942 }
5943 else
5944 #endif
5945 {
5946 assert(s1l>=0);
5947 emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
57871462 5948 if(s2l>=0) emit_cmp(s1l,s2l);
5949 else emit_test(s1l,s1l);
5950 emit_cmovne_reg(alt,addr);
5951 }
5952 }
cf95b4f0 5953 if((dops[i].opcode&0x3f)==5) // BNE
57871462 5954 {
5955 #ifdef HAVE_CMOV_IMM
ad49de89 5956 if(s2l>=0) emit_cmp(s1l,s2l);
5957 else emit_test(s1l,s1l);
5958 emit_cmov2imm_e_ne_compact(start+i*4+8,ba[i],addr);
5959 #else
5960 assert(s1l>=0);
5961 emit_mov2imm_compact(start+i*4+8,addr,ba[i],alt);
5962 if(s2l>=0) emit_cmp(s1l,s2l);
5963 else emit_test(s1l,s1l);
5964 emit_cmovne_reg(alt,addr);
57871462 5965 #endif
57871462 5966 }
cf95b4f0 5967 if((dops[i].opcode&0x3f)==0x14) // BEQL
57871462 5968 {
57871462 5969 if(s2l>=0) emit_cmp(s1l,s2l);
5970 else emit_test(s1l,s1l);
df4dc2b1 5971 if(nottaken) set_jump_target(nottaken, out);
5972 nottaken=out;
57871462 5973 emit_jne(0);
5974 }
cf95b4f0 5975 if((dops[i].opcode&0x3f)==0x15) // BNEL
57871462 5976 {
57871462 5977 if(s2l>=0) emit_cmp(s1l,s2l);
5978 else emit_test(s1l,s1l);
df4dc2b1 5979 nottaken=out;
57871462 5980 emit_jeq(0);
df4dc2b1 5981 if(taken) set_jump_target(taken, out);
57871462 5982 }
cf95b4f0 5983 if((dops[i].opcode&0x3f)==6) // BLEZ
57871462 5984 {
5985 emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
5986 emit_cmpimm(s1l,1);
57871462 5987 emit_cmovl_reg(alt,addr);
57871462 5988 }
cf95b4f0 5989 if((dops[i].opcode&0x3f)==7) // BGTZ
57871462 5990 {
5991 emit_mov2imm_compact(ba[i],addr,start+i*4+8,ntaddr);
5992 emit_cmpimm(s1l,1);
57871462 5993 emit_cmovl_reg(ntaddr,addr);
57871462 5994 }
cf95b4f0 5995 if((dops[i].opcode&0x3f)==0x16) // BLEZL
57871462 5996 {
cf95b4f0 5997 assert((dops[i].opcode&0x3f)!=0x16);
57871462 5998 }
cf95b4f0 5999 if((dops[i].opcode&0x3f)==0x17) // BGTZL
57871462 6000 {
cf95b4f0 6001 assert((dops[i].opcode&0x3f)!=0x17);
57871462 6002 }
cf95b4f0 6003 assert(dops[i].opcode!=1); // BLTZ/BGEZ
57871462 6004
6005 //FIXME: Check CSREG
cf95b4f0 6006 if(dops[i].opcode==0x11 && dops[i].opcode2==0x08 ) {
57871462 6007 if((source[i]&0x30000)==0) // BC1F
6008 {
6009 emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
6010 emit_testimm(s1l,0x800000);
6011 emit_cmovne_reg(alt,addr);
6012 }
6013 if((source[i]&0x30000)==0x10000) // BC1T
6014 {
6015 emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
6016 emit_testimm(s1l,0x800000);
6017 emit_cmovne_reg(alt,addr);
6018 }
6019 if((source[i]&0x30000)==0x20000) // BC1FL
6020 {
6021 emit_testimm(s1l,0x800000);
df4dc2b1 6022 nottaken=out;
57871462 6023 emit_jne(0);
6024 }
6025 if((source[i]&0x30000)==0x30000) // BC1TL
6026 {
6027 emit_testimm(s1l,0x800000);
df4dc2b1 6028 nottaken=out;
57871462 6029 emit_jeq(0);
6030 }
6031 }
6032
6033 assert(i_regs->regmap[HOST_CCREG]==CCREG);
ad49de89 6034 wb_dirtys(regs[i].regmap,regs[i].dirty);
fe807a8a 6035 if(unconditional)
57871462 6036 {
6037 emit_movimm(ba[i],HOST_BTREG);
6038 }
6039 else if(addr!=HOST_BTREG)
6040 {
6041 emit_mov(addr,HOST_BTREG);
6042 }
6043 void *branch_addr=out;
6044 emit_jmp(0);
6045 int target_addr=start+i*4+5;
6046 void *stub=out;
6047 void *compiled_target_addr=check_addr(target_addr);
643aeae3 6048 emit_extjump_ds(branch_addr, target_addr);
57871462 6049 if(compiled_target_addr) {
df4dc2b1 6050 set_jump_target(branch_addr, compiled_target_addr);
3d680478 6051 add_jump_out(target_addr,stub);
57871462 6052 }
df4dc2b1 6053 else set_jump_target(branch_addr, stub);
57871462 6054}
6055
6056// Assemble the delay slot for the above
6057static void pagespan_ds()
6058{
6059 assem_debug("initial delay slot:\n");
6060 u_int vaddr=start+1;
94d23bb9 6061 u_int page=get_page(vaddr);
6062 u_int vpage=get_vpage(vaddr);
57871462 6063 ll_add(jump_dirty+vpage,vaddr,(void *)out);
3d680478 6064 do_dirty_stub_ds(slen*4);
57871462 6065 ll_add(jump_in+page,vaddr,(void *)out);
6066 assert(regs[0].regmap_entry[HOST_CCREG]==CCREG);
6067 if(regs[0].regmap[HOST_CCREG]!=CCREG)
ad49de89 6068 wb_register(CCREG,regs[0].regmap_entry,regs[0].wasdirty);
57871462 6069 if(regs[0].regmap[HOST_BTREG]!=BTREG)
643aeae3 6070 emit_writeword(HOST_BTREG,&branch_target);
cf95b4f0 6071 load_regs(regs[0].regmap_entry,regs[0].regmap,dops[0].rs1,dops[0].rs2);
57871462 6072 address_generation(0,&regs[0],regs[0].regmap_entry);
37387d8b 6073 if (ram_offset && (dops[0].is_load || dops[0].is_store))
6074 load_regs(regs[0].regmap_entry,regs[0].regmap,ROREG,ROREG);
6075 if (dops[0].is_store)
ad49de89 6076 load_regs(regs[0].regmap_entry,regs[0].regmap,INVCP,INVCP);
57871462 6077 is_delayslot=0;
2330734f 6078 switch (dops[0].itype) {
57871462 6079 case SYSCALL:
7139f3c8 6080 case HLECALL:
1e973cb0 6081 case INTCALL:
57871462 6082 case SPAN:
6083 case UJUMP:
6084 case RJUMP:
6085 case CJUMP:
6086 case SJUMP:
c43b5311 6087 SysPrintf("Jump in the delay slot. This is probably a bug.\n");
2330734f 6088 break;
6089 default:
6090 assemble(0, &regs[0], 0);
57871462 6091 }
6092 int btaddr=get_reg(regs[0].regmap,BTREG);
6093 if(btaddr<0) {
6094 btaddr=get_reg(regs[0].regmap,-1);
643aeae3 6095 emit_readword(&branch_target,btaddr);
57871462 6096 }
6097 assert(btaddr!=HOST_CCREG);
6098 if(regs[0].regmap[HOST_CCREG]!=CCREG) emit_loadreg(CCREG,HOST_CCREG);
6099#ifdef HOST_IMM8
d1e4ebd9 6100 host_tempreg_acquire();
57871462 6101 emit_movimm(start+4,HOST_TEMPREG);
6102 emit_cmp(btaddr,HOST_TEMPREG);
d1e4ebd9 6103 host_tempreg_release();
57871462 6104#else
6105 emit_cmpimm(btaddr,start+4);
6106#endif
df4dc2b1 6107 void *branch = out;
57871462 6108 emit_jeq(0);
ad49de89 6109 store_regs_bt(regs[0].regmap,regs[0].dirty,-1);
d1e4ebd9 6110 do_jump_vaddr(btaddr);
df4dc2b1 6111 set_jump_target(branch, out);
ad49de89 6112 store_regs_bt(regs[0].regmap,regs[0].dirty,start+4);
6113 load_regs_bt(regs[0].regmap,regs[0].dirty,start+4);
57871462 6114}
6115
6116// Basic liveness analysis for MIPS registers
6117void unneeded_registers(int istart,int iend,int r)
6118{
6119 int i;
00fa9369 6120 uint64_t u,gte_u,b,gte_b;
6121 uint64_t temp_u,temp_gte_u=0;
0ff8c62c 6122 uint64_t gte_u_unknown=0;
d62c125a 6123 if (HACK_ENABLED(NDHACK_GTE_UNNEEDED))
0ff8c62c 6124 gte_u_unknown=~0ll;
57871462 6125 if(iend==slen-1) {
00fa9369 6126 u=1;
0ff8c62c 6127 gte_u=gte_u_unknown;
57871462 6128 }else{
00fa9369 6129 //u=unneeded_reg[iend+1];
6130 u=1;
0ff8c62c 6131 gte_u=gte_unneeded[iend+1];
57871462 6132 }
bedfea38 6133
57871462 6134 for (i=iend;i>=istart;i--)
6135 {
6136 //printf("unneeded registers i=%d (%d,%d) r=%d\n",i,istart,iend,r);
fe807a8a 6137 if(dops[i].is_jump)
57871462 6138 {
6139 // If subroutine call, flag return address as a possible branch target
cf95b4f0 6140 if(dops[i].rt1==31 && i<slen-2) dops[i+2].bt=1;
9f51b4b9 6141
57871462 6142 if(ba[i]<start || ba[i]>=(start+slen*4))
6143 {
6144 // Branch out of this block, flush all regs
6145 u=1;
0ff8c62c 6146 gte_u=gte_u_unknown;
57871462 6147 branch_unneeded_reg[i]=u;
57871462 6148 // Merge in delay slot
cf95b4f0 6149 u|=(1LL<<dops[i+1].rt1)|(1LL<<dops[i+1].rt2);
6150 u&=~((1LL<<dops[i+1].rs1)|(1LL<<dops[i+1].rs2));
00fa9369 6151 u|=1;
bedfea38 6152 gte_u|=gte_rt[i+1];
6153 gte_u&=~gte_rs[i+1];
57871462 6154 }
6155 else
6156 {
6157 // Internal branch, flag target
cf95b4f0 6158 dops[(ba[i]-start)>>2].bt=1;
57871462 6159 if(ba[i]<=start+i*4) {
6160 // Backward branch
fe807a8a 6161 if(dops[i].is_ujump)
57871462 6162 {
6163 // Unconditional branch
00fa9369 6164 temp_u=1;
bedfea38 6165 temp_gte_u=0;
57871462 6166 } else {
6167 // Conditional branch (not taken case)
6168 temp_u=unneeded_reg[i+2];
bedfea38 6169 temp_gte_u&=gte_unneeded[i+2];
57871462 6170 }
6171 // Merge in delay slot
cf95b4f0 6172 temp_u|=(1LL<<dops[i+1].rt1)|(1LL<<dops[i+1].rt2);
6173 temp_u&=~((1LL<<dops[i+1].rs1)|(1LL<<dops[i+1].rs2));
00fa9369 6174 temp_u|=1;
bedfea38 6175 temp_gte_u|=gte_rt[i+1];
6176 temp_gte_u&=~gte_rs[i+1];
cf95b4f0 6177 temp_u|=(1LL<<dops[i].rt1)|(1LL<<dops[i].rt2);
6178 temp_u&=~((1LL<<dops[i].rs1)|(1LL<<dops[i].rs2));
00fa9369 6179 temp_u|=1;
bedfea38 6180 temp_gte_u|=gte_rt[i];
6181 temp_gte_u&=~gte_rs[i];
57871462 6182 unneeded_reg[i]=temp_u;
bedfea38 6183 gte_unneeded[i]=temp_gte_u;
57871462 6184 // Only go three levels deep. This recursion can take an
6185 // excessive amount of time if there are a lot of nested loops.
6186 if(r<2) {
6187 unneeded_registers((ba[i]-start)>>2,i-1,r+1);
6188 }else{
6189 unneeded_reg[(ba[i]-start)>>2]=1;
0ff8c62c 6190 gte_unneeded[(ba[i]-start)>>2]=gte_u_unknown;
57871462 6191 }
6192 } /*else*/ if(1) {
fe807a8a 6193 if (dops[i].is_ujump)
57871462 6194 {
6195 // Unconditional branch
6196 u=unneeded_reg[(ba[i]-start)>>2];
bedfea38 6197 gte_u=gte_unneeded[(ba[i]-start)>>2];
57871462 6198 branch_unneeded_reg[i]=u;
57871462 6199 // Merge in delay slot
cf95b4f0 6200 u|=(1LL<<dops[i+1].rt1)|(1LL<<dops[i+1].rt2);
6201 u&=~((1LL<<dops[i+1].rs1)|(1LL<<dops[i+1].rs2));
00fa9369 6202 u|=1;
bedfea38 6203 gte_u|=gte_rt[i+1];
6204 gte_u&=~gte_rs[i+1];
57871462 6205 } else {
6206 // Conditional branch
6207 b=unneeded_reg[(ba[i]-start)>>2];
00fa9369 6208 gte_b=gte_unneeded[(ba[i]-start)>>2];
57871462 6209 branch_unneeded_reg[i]=b;
57871462 6210 // Branch delay slot
cf95b4f0 6211 b|=(1LL<<dops[i+1].rt1)|(1LL<<dops[i+1].rt2);
6212 b&=~((1LL<<dops[i+1].rs1)|(1LL<<dops[i+1].rs2));
00fa9369 6213 b|=1;
6214 gte_b|=gte_rt[i+1];
6215 gte_b&=~gte_rs[i+1];
fe807a8a 6216 u&=b;
6217 gte_u&=gte_b;
57871462 6218 if(i<slen-1) {
6219 branch_unneeded_reg[i]&=unneeded_reg[i+2];
57871462 6220 } else {
6221 branch_unneeded_reg[i]=1;
57871462 6222 }
6223 }
6224 }
6225 }
6226 }
cf95b4f0 6227 else if(dops[i].itype==SYSCALL||dops[i].itype==HLECALL||dops[i].itype==INTCALL)
57871462 6228 {
6229 // SYSCALL instruction (software interrupt)
6230 u=1;
57871462 6231 }
cf95b4f0 6232 else if(dops[i].itype==COP0 && (source[i]&0x3f)==0x18)
57871462 6233 {
6234 // ERET instruction (return from interrupt)
6235 u=1;
57871462 6236 }
00fa9369 6237 //u=1; // DEBUG
57871462 6238 // Written registers are unneeded
cf95b4f0 6239 u|=1LL<<dops[i].rt1;
6240 u|=1LL<<dops[i].rt2;
bedfea38 6241 gte_u|=gte_rt[i];
57871462 6242 // Accessed registers are needed
cf95b4f0 6243 u&=~(1LL<<dops[i].rs1);
6244 u&=~(1LL<<dops[i].rs2);
bedfea38 6245 gte_u&=~gte_rs[i];
cf95b4f0 6246 if(gte_rs[i]&&dops[i].rt1&&(unneeded_reg[i+1]&(1ll<<dops[i].rt1)))
cbbd8dd7 6247 gte_u|=gte_rs[i]&gte_unneeded[i+1]; // MFC2/CFC2 to dead register, unneeded
57871462 6248 // Source-target dependencies
57871462 6249 // R0 is always unneeded
00fa9369 6250 u|=1;
57871462 6251 // Save it
6252 unneeded_reg[i]=u;
bedfea38 6253 gte_unneeded[i]=gte_u;
57871462 6254 /*
6255 printf("ur (%d,%d) %x: ",istart,iend,start+i*4);
6256 printf("U:");
6257 int r;
6258 for(r=1;r<=CCREG;r++) {
6259 if((unneeded_reg[i]>>r)&1) {
6260 if(r==HIREG) printf(" HI");
6261 else if(r==LOREG) printf(" LO");
6262 else printf(" r%d",r);
6263 }
6264 }
00fa9369 6265 printf("\n");
6266 */
252c20fc 6267 }
57871462 6268}
6269
71e490c5 6270// Write back dirty registers as soon as we will no longer modify them,
6271// so that we don't end up with lots of writes at the branches.
6272void clean_registers(int istart,int iend,int wr)
57871462 6273{
71e490c5 6274 int i;
6275 int r;
6276 u_int will_dirty_i,will_dirty_next,temp_will_dirty;
6277 u_int wont_dirty_i,wont_dirty_next,temp_wont_dirty;
6278 if(iend==slen-1) {
6279 will_dirty_i=will_dirty_next=0;
6280 wont_dirty_i=wont_dirty_next=0;
6281 }else{
6282 will_dirty_i=will_dirty_next=will_dirty[iend+1];
6283 wont_dirty_i=wont_dirty_next=wont_dirty[iend+1];
6284 }
6285 for (i=iend;i>=istart;i--)
57871462 6286 {
fe807a8a 6287 if(dops[i].is_jump)
57871462 6288 {
71e490c5 6289 if(ba[i]<start || ba[i]>=(start+slen*4))
57871462 6290 {
71e490c5 6291 // Branch out of this block, flush all regs
fe807a8a 6292 if (dops[i].is_ujump)
57871462 6293 {
6294 // Unconditional branch
6295 will_dirty_i=0;
6296 wont_dirty_i=0;
6297 // Merge in delay slot (will dirty)
6298 for(r=0;r<HOST_REGS;r++) {
6299 if(r!=EXCLUDE_REG) {
cf95b4f0 6300 if((branch_regs[i].regmap[r]&63)==dops[i].rt1) will_dirty_i|=1<<r;
6301 if((branch_regs[i].regmap[r]&63)==dops[i].rt2) will_dirty_i|=1<<r;
6302 if((branch_regs[i].regmap[r]&63)==dops[i+1].rt1) will_dirty_i|=1<<r;
6303 if((branch_regs[i].regmap[r]&63)==dops[i+1].rt2) will_dirty_i|=1<<r;
57871462 6304 if((branch_regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
6305 if(branch_regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
6306 if(branch_regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
cf95b4f0 6307 if((regs[i].regmap[r]&63)==dops[i].rt1) will_dirty_i|=1<<r;
6308 if((regs[i].regmap[r]&63)==dops[i].rt2) will_dirty_i|=1<<r;
6309 if((regs[i].regmap[r]&63)==dops[i+1].rt1) will_dirty_i|=1<<r;
6310 if((regs[i].regmap[r]&63)==dops[i+1].rt2) will_dirty_i|=1<<r;
57871462 6311 if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
6312 if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
6313 if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
6314 }
6315 }
6316 }
6317 else
6318 {
6319 // Conditional branch
6320 will_dirty_i=0;
6321 wont_dirty_i=wont_dirty_next;
6322 // Merge in delay slot (will dirty)
6323 for(r=0;r<HOST_REGS;r++) {
6324 if(r!=EXCLUDE_REG) {
fe807a8a 6325 if (1) { // !dops[i].likely) {
57871462 6326 // Might not dirty if likely branch is not taken
cf95b4f0 6327 if((branch_regs[i].regmap[r]&63)==dops[i].rt1) will_dirty_i|=1<<r;
6328 if((branch_regs[i].regmap[r]&63)==dops[i].rt2) will_dirty_i|=1<<r;
6329 if((branch_regs[i].regmap[r]&63)==dops[i+1].rt1) will_dirty_i|=1<<r;
6330 if((branch_regs[i].regmap[r]&63)==dops[i+1].rt2) will_dirty_i|=1<<r;
57871462 6331 if((branch_regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
6332 if(branch_regs[i].regmap[r]==0) will_dirty_i&=~(1<<r);
6333 if(branch_regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
cf95b4f0 6334 //if((regs[i].regmap[r]&63)==dops[i].rt1) will_dirty_i|=1<<r;
6335 //if((regs[i].regmap[r]&63)==dops[i].rt2) will_dirty_i|=1<<r;
6336 if((regs[i].regmap[r]&63)==dops[i+1].rt1) will_dirty_i|=1<<r;
6337 if((regs[i].regmap[r]&63)==dops[i+1].rt2) will_dirty_i|=1<<r;
57871462 6338 if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
6339 if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
6340 if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
6341 }
6342 }
6343 }
6344 }
6345 // Merge in delay slot (wont dirty)
6346 for(r=0;r<HOST_REGS;r++) {
6347 if(r!=EXCLUDE_REG) {
cf95b4f0 6348 if((regs[i].regmap[r]&63)==dops[i].rt1) wont_dirty_i|=1<<r;
6349 if((regs[i].regmap[r]&63)==dops[i].rt2) wont_dirty_i|=1<<r;
6350 if((regs[i].regmap[r]&63)==dops[i+1].rt1) wont_dirty_i|=1<<r;
6351 if((regs[i].regmap[r]&63)==dops[i+1].rt2) wont_dirty_i|=1<<r;
57871462 6352 if(regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
cf95b4f0 6353 if((branch_regs[i].regmap[r]&63)==dops[i].rt1) wont_dirty_i|=1<<r;
6354 if((branch_regs[i].regmap[r]&63)==dops[i].rt2) wont_dirty_i|=1<<r;
6355 if((branch_regs[i].regmap[r]&63)==dops[i+1].rt1) wont_dirty_i|=1<<r;
6356 if((branch_regs[i].regmap[r]&63)==dops[i+1].rt2) wont_dirty_i|=1<<r;
57871462 6357 if(branch_regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
6358 }
6359 }
6360 if(wr) {
6361 #ifndef DESTRUCTIVE_WRITEBACK
6362 branch_regs[i].dirty&=wont_dirty_i;
6363 #endif
6364 branch_regs[i].dirty|=will_dirty_i;
6365 }
6366 }
6367 else
6368 {
6369 // Internal branch
6370 if(ba[i]<=start+i*4) {
6371 // Backward branch
fe807a8a 6372 if (dops[i].is_ujump)
57871462 6373 {
6374 // Unconditional branch
6375 temp_will_dirty=0;
6376 temp_wont_dirty=0;
6377 // Merge in delay slot (will dirty)
6378 for(r=0;r<HOST_REGS;r++) {
6379 if(r!=EXCLUDE_REG) {
cf95b4f0 6380 if((branch_regs[i].regmap[r]&63)==dops[i].rt1) temp_will_dirty|=1<<r;
6381 if((branch_regs[i].regmap[r]&63)==dops[i].rt2) temp_will_dirty|=1<<r;
6382 if((branch_regs[i].regmap[r]&63)==dops[i+1].rt1) temp_will_dirty|=1<<r;
6383 if((branch_regs[i].regmap[r]&63)==dops[i+1].rt2) temp_will_dirty|=1<<r;
57871462 6384 if((branch_regs[i].regmap[r]&63)>33) temp_will_dirty&=~(1<<r);
6385 if(branch_regs[i].regmap[r]<=0) temp_will_dirty&=~(1<<r);
6386 if(branch_regs[i].regmap[r]==CCREG) temp_will_dirty|=1<<r;
cf95b4f0 6387 if((regs[i].regmap[r]&63)==dops[i].rt1) temp_will_dirty|=1<<r;
6388 if((regs[i].regmap[r]&63)==dops[i].rt2) temp_will_dirty|=1<<r;
6389 if((regs[i].regmap[r]&63)==dops[i+1].rt1) temp_will_dirty|=1<<r;
6390 if((regs[i].regmap[r]&63)==dops[i+1].rt2) temp_will_dirty|=1<<r;
57871462 6391 if((regs[i].regmap[r]&63)>33) temp_will_dirty&=~(1<<r);
6392 if(regs[i].regmap[r]<=0) temp_will_dirty&=~(1<<r);
6393 if(regs[i].regmap[r]==CCREG) temp_will_dirty|=1<<r;
6394 }
6395 }
6396 } else {
6397 // Conditional branch (not taken case)
6398 temp_will_dirty=will_dirty_next;
6399 temp_wont_dirty=wont_dirty_next;
6400 // Merge in delay slot (will dirty)
6401 for(r=0;r<HOST_REGS;r++) {
6402 if(r!=EXCLUDE_REG) {
fe807a8a 6403 if (1) { // !dops[i].likely) {
57871462 6404 // Will not dirty if likely branch is not taken
cf95b4f0 6405 if((branch_regs[i].regmap[r]&63)==dops[i].rt1) temp_will_dirty|=1<<r;
6406 if((branch_regs[i].regmap[r]&63)==dops[i].rt2) temp_will_dirty|=1<<r;
6407 if((branch_regs[i].regmap[r]&63)==dops[i+1].rt1) temp_will_dirty|=1<<r;
6408 if((branch_regs[i].regmap[r]&63)==dops[i+1].rt2) temp_will_dirty|=1<<r;
57871462 6409 if((branch_regs[i].regmap[r]&63)>33) temp_will_dirty&=~(1<<r);
6410 if(branch_regs[i].regmap[r]==0) temp_will_dirty&=~(1<<r);
6411 if(branch_regs[i].regmap[r]==CCREG) temp_will_dirty|=1<<r;
cf95b4f0 6412 //if((regs[i].regmap[r]&63)==dops[i].rt1) temp_will_dirty|=1<<r;
6413 //if((regs[i].regmap[r]&63)==dops[i].rt2) temp_will_dirty|=1<<r;
6414 if((regs[i].regmap[r]&63)==dops[i+1].rt1) temp_will_dirty|=1<<r;
6415 if((regs[i].regmap[r]&63)==dops[i+1].rt2) temp_will_dirty|=1<<r;
57871462 6416 if((regs[i].regmap[r]&63)>33) temp_will_dirty&=~(1<<r);
6417 if(regs[i].regmap[r]<=0) temp_will_dirty&=~(1<<r);
6418 if(regs[i].regmap[r]==CCREG) temp_will_dirty|=1<<r;
6419 }
6420 }
6421 }
6422 }
6423 // Merge in delay slot (wont dirty)
6424 for(r=0;r<HOST_REGS;r++) {
6425 if(r!=EXCLUDE_REG) {
cf95b4f0 6426 if((regs[i].regmap[r]&63)==dops[i].rt1) temp_wont_dirty|=1<<r;
6427 if((regs[i].regmap[r]&63)==dops[i].rt2) temp_wont_dirty|=1<<r;
6428 if((regs[i].regmap[r]&63)==dops[i+1].rt1) temp_wont_dirty|=1<<r;
6429 if((regs[i].regmap[r]&63)==dops[i+1].rt2) temp_wont_dirty|=1<<r;
57871462 6430 if(regs[i].regmap[r]==CCREG) temp_wont_dirty|=1<<r;
cf95b4f0 6431 if((branch_regs[i].regmap[r]&63)==dops[i].rt1) temp_wont_dirty|=1<<r;
6432 if((branch_regs[i].regmap[r]&63)==dops[i].rt2) temp_wont_dirty|=1<<r;
6433 if((branch_regs[i].regmap[r]&63)==dops[i+1].rt1) temp_wont_dirty|=1<<r;
6434 if((branch_regs[i].regmap[r]&63)==dops[i+1].rt2) temp_wont_dirty|=1<<r;
57871462 6435 if(branch_regs[i].regmap[r]==CCREG) temp_wont_dirty|=1<<r;
6436 }
6437 }
6438 // Deal with changed mappings
6439 if(i<iend) {
6440 for(r=0;r<HOST_REGS;r++) {
6441 if(r!=EXCLUDE_REG) {
6442 if(regs[i].regmap[r]!=regmap_pre[i][r]) {
6443 temp_will_dirty&=~(1<<r);
6444 temp_wont_dirty&=~(1<<r);
6445 if((regmap_pre[i][r]&63)>0 && (regmap_pre[i][r]&63)<34) {
6446 temp_will_dirty|=((unneeded_reg[i]>>(regmap_pre[i][r]&63))&1)<<r;
6447 temp_wont_dirty|=((unneeded_reg[i]>>(regmap_pre[i][r]&63))&1)<<r;
6448 } else {
6449 temp_will_dirty|=1<<r;
6450 temp_wont_dirty|=1<<r;
6451 }
6452 }
6453 }
6454 }
6455 }
6456 if(wr) {
6457 will_dirty[i]=temp_will_dirty;
6458 wont_dirty[i]=temp_wont_dirty;
6459 clean_registers((ba[i]-start)>>2,i-1,0);
6460 }else{
6461 // Limit recursion. It can take an excessive amount
6462 // of time if there are a lot of nested loops.
6463 will_dirty[(ba[i]-start)>>2]=0;
6464 wont_dirty[(ba[i]-start)>>2]=-1;
6465 }
6466 }
6467 /*else*/ if(1)
6468 {
fe807a8a 6469 if (dops[i].is_ujump)
57871462 6470 {
6471 // Unconditional branch
6472 will_dirty_i=0;
6473 wont_dirty_i=0;
6474 //if(ba[i]>start+i*4) { // Disable recursion (for debugging)
6475 for(r=0;r<HOST_REGS;r++) {
6476 if(r!=EXCLUDE_REG) {
6477 if(branch_regs[i].regmap[r]==regs[(ba[i]-start)>>2].regmap_entry[r]) {
6478 will_dirty_i|=will_dirty[(ba[i]-start)>>2]&(1<<r);
6479 wont_dirty_i|=wont_dirty[(ba[i]-start)>>2]&(1<<r);
6480 }
e3234ecf 6481 if(branch_regs[i].regmap[r]>=0) {
6482 will_dirty_i|=((unneeded_reg[(ba[i]-start)>>2]>>(branch_regs[i].regmap[r]&63))&1)<<r;
6483 wont_dirty_i|=((unneeded_reg[(ba[i]-start)>>2]>>(branch_regs[i].regmap[r]&63))&1)<<r;
6484 }
57871462 6485 }
6486 }
6487 //}
6488 // Merge in delay slot
6489 for(r=0;r<HOST_REGS;r++) {
6490 if(r!=EXCLUDE_REG) {
cf95b4f0 6491 if((branch_regs[i].regmap[r]&63)==dops[i].rt1) will_dirty_i|=1<<r;
6492 if((branch_regs[i].regmap[r]&63)==dops[i].rt2) will_dirty_i|=1<<r;
6493 if((branch_regs[i].regmap[r]&63)==dops[i+1].rt1) will_dirty_i|=1<<r;
6494 if((branch_regs[i].regmap[r]&63)==dops[i+1].rt2) will_dirty_i|=1<<r;
57871462 6495 if((branch_regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
6496 if(branch_regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
6497 if(branch_regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
cf95b4f0 6498 if((regs[i].regmap[r]&63)==dops[i].rt1) will_dirty_i|=1<<r;
6499 if((regs[i].regmap[r]&63)==dops[i].rt2) will_dirty_i|=1<<r;
6500 if((regs[i].regmap[r]&63)==dops[i+1].rt1) will_dirty_i|=1<<r;
6501 if((regs[i].regmap[r]&63)==dops[i+1].rt2) will_dirty_i|=1<<r;
57871462 6502 if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
6503 if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
6504 if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
6505 }
6506 }
6507 } else {
6508 // Conditional branch
6509 will_dirty_i=will_dirty_next;
6510 wont_dirty_i=wont_dirty_next;
6511 //if(ba[i]>start+i*4) { // Disable recursion (for debugging)
6512 for(r=0;r<HOST_REGS;r++) {
6513 if(r!=EXCLUDE_REG) {
e3234ecf 6514 signed char target_reg=branch_regs[i].regmap[r];
6515 if(target_reg==regs[(ba[i]-start)>>2].regmap_entry[r]) {
57871462 6516 will_dirty_i&=will_dirty[(ba[i]-start)>>2]&(1<<r);
6517 wont_dirty_i|=wont_dirty[(ba[i]-start)>>2]&(1<<r);
6518 }
e3234ecf 6519 else if(target_reg>=0) {
6520 will_dirty_i&=((unneeded_reg[(ba[i]-start)>>2]>>(target_reg&63))&1)<<r;
6521 wont_dirty_i|=((unneeded_reg[(ba[i]-start)>>2]>>(target_reg&63))&1)<<r;
57871462 6522 }
57871462 6523 }
6524 }
6525 //}
6526 // Merge in delay slot
6527 for(r=0;r<HOST_REGS;r++) {
6528 if(r!=EXCLUDE_REG) {
fe807a8a 6529 if (1) { // !dops[i].likely) {
57871462 6530 // Might not dirty if likely branch is not taken
cf95b4f0 6531 if((branch_regs[i].regmap[r]&63)==dops[i].rt1) will_dirty_i|=1<<r;
6532 if((branch_regs[i].regmap[r]&63)==dops[i].rt2) will_dirty_i|=1<<r;
6533 if((branch_regs[i].regmap[r]&63)==dops[i+1].rt1) will_dirty_i|=1<<r;
6534 if((branch_regs[i].regmap[r]&63)==dops[i+1].rt2) will_dirty_i|=1<<r;
57871462 6535 if((branch_regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
6536 if(branch_regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
6537 if(branch_regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
cf95b4f0 6538 //if((regs[i].regmap[r]&63)==dops[i].rt1) will_dirty_i|=1<<r;
6539 //if((regs[i].regmap[r]&63)==dops[i].rt2) will_dirty_i|=1<<r;
6540 if((regs[i].regmap[r]&63)==dops[i+1].rt1) will_dirty_i|=1<<r;
6541 if((regs[i].regmap[r]&63)==dops[i+1].rt2) will_dirty_i|=1<<r;
57871462 6542 if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
6543 if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
6544 if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
6545 }
6546 }
6547 }
6548 }
e3234ecf 6549 // Merge in delay slot (won't dirty)
57871462 6550 for(r=0;r<HOST_REGS;r++) {
6551 if(r!=EXCLUDE_REG) {
cf95b4f0 6552 if((regs[i].regmap[r]&63)==dops[i].rt1) wont_dirty_i|=1<<r;
6553 if((regs[i].regmap[r]&63)==dops[i].rt2) wont_dirty_i|=1<<r;
6554 if((regs[i].regmap[r]&63)==dops[i+1].rt1) wont_dirty_i|=1<<r;
6555 if((regs[i].regmap[r]&63)==dops[i+1].rt2) wont_dirty_i|=1<<r;
57871462 6556 if(regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
cf95b4f0 6557 if((branch_regs[i].regmap[r]&63)==dops[i].rt1) wont_dirty_i|=1<<r;
6558 if((branch_regs[i].regmap[r]&63)==dops[i].rt2) wont_dirty_i|=1<<r;
6559 if((branch_regs[i].regmap[r]&63)==dops[i+1].rt1) wont_dirty_i|=1<<r;
6560 if((branch_regs[i].regmap[r]&63)==dops[i+1].rt2) wont_dirty_i|=1<<r;
57871462 6561 if(branch_regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
6562 }
6563 }
6564 if(wr) {
6565 #ifndef DESTRUCTIVE_WRITEBACK
6566 branch_regs[i].dirty&=wont_dirty_i;
6567 #endif
6568 branch_regs[i].dirty|=will_dirty_i;
6569 }
6570 }
6571 }
6572 }
cf95b4f0 6573 else if(dops[i].itype==SYSCALL||dops[i].itype==HLECALL||dops[i].itype==INTCALL)
57871462 6574 {
6575 // SYSCALL instruction (software interrupt)
6576 will_dirty_i=0;
6577 wont_dirty_i=0;
6578 }
cf95b4f0 6579 else if(dops[i].itype==COP0 && (source[i]&0x3f)==0x18)
57871462 6580 {
6581 // ERET instruction (return from interrupt)
6582 will_dirty_i=0;
6583 wont_dirty_i=0;
6584 }
6585 will_dirty_next=will_dirty_i;
6586 wont_dirty_next=wont_dirty_i;
6587 for(r=0;r<HOST_REGS;r++) {
6588 if(r!=EXCLUDE_REG) {
cf95b4f0 6589 if((regs[i].regmap[r]&63)==dops[i].rt1) will_dirty_i|=1<<r;
6590 if((regs[i].regmap[r]&63)==dops[i].rt2) will_dirty_i|=1<<r;
57871462 6591 if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
6592 if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
6593 if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
cf95b4f0 6594 if((regs[i].regmap[r]&63)==dops[i].rt1) wont_dirty_i|=1<<r;
6595 if((regs[i].regmap[r]&63)==dops[i].rt2) wont_dirty_i|=1<<r;
57871462 6596 if(regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
6597 if(i>istart) {
fe807a8a 6598 if (!dops[i].is_jump)
57871462 6599 {
6600 // Don't store a register immediately after writing it,
6601 // may prevent dual-issue.
cf95b4f0 6602 if((regs[i].regmap[r]&63)==dops[i-1].rt1) wont_dirty_i|=1<<r;
6603 if((regs[i].regmap[r]&63)==dops[i-1].rt2) wont_dirty_i|=1<<r;
57871462 6604 }
6605 }
6606 }
6607 }
6608 // Save it
6609 will_dirty[i]=will_dirty_i;
6610 wont_dirty[i]=wont_dirty_i;
6611 // Mark registers that won't be dirtied as not dirty
6612 if(wr) {
57871462 6613 regs[i].dirty|=will_dirty_i;
6614 #ifndef DESTRUCTIVE_WRITEBACK
6615 regs[i].dirty&=wont_dirty_i;
fe807a8a 6616 if(dops[i].is_jump)
57871462 6617 {
fe807a8a 6618 if (i < iend-1 && !dops[i].is_ujump) {
57871462 6619 for(r=0;r<HOST_REGS;r++) {
6620 if(r!=EXCLUDE_REG) {
6621 if(regs[i].regmap[r]==regmap_pre[i+2][r]) {
6622 regs[i+2].wasdirty&=wont_dirty_i|~(1<<r);
581335b0 6623 }else {/*printf("i: %x (%d) mismatch(+2): %d\n",start+i*4,i,r);assert(!((wont_dirty_i>>r)&1));*/}
57871462 6624 }
6625 }
6626 }
6627 }
6628 else
6629 {
6630 if(i<iend) {
6631 for(r=0;r<HOST_REGS;r++) {
6632 if(r!=EXCLUDE_REG) {
6633 if(regs[i].regmap[r]==regmap_pre[i+1][r]) {
6634 regs[i+1].wasdirty&=wont_dirty_i|~(1<<r);
581335b0 6635 }else {/*printf("i: %x (%d) mismatch(+1): %d\n",start+i*4,i,r);assert(!((wont_dirty_i>>r)&1));*/}
57871462 6636 }
6637 }
6638 }
6639 }
6640 #endif
6641 //}
6642 }
6643 // Deal with changed mappings
6644 temp_will_dirty=will_dirty_i;
6645 temp_wont_dirty=wont_dirty_i;
6646 for(r=0;r<HOST_REGS;r++) {
6647 if(r!=EXCLUDE_REG) {
6648 int nr;
6649 if(regs[i].regmap[r]==regmap_pre[i][r]) {
6650 if(wr) {
6651 #ifndef DESTRUCTIVE_WRITEBACK
6652 regs[i].wasdirty&=wont_dirty_i|~(1<<r);
6653 #endif
6654 regs[i].wasdirty|=will_dirty_i&(1<<r);
6655 }
6656 }
f776eb14 6657 else if(regmap_pre[i][r]>=0&&(nr=get_reg(regs[i].regmap,regmap_pre[i][r]))>=0) {
57871462 6658 // Register moved to a different register
6659 will_dirty_i&=~(1<<r);
6660 wont_dirty_i&=~(1<<r);
6661 will_dirty_i|=((temp_will_dirty>>nr)&1)<<r;
6662 wont_dirty_i|=((temp_wont_dirty>>nr)&1)<<r;
6663 if(wr) {
6664 #ifndef DESTRUCTIVE_WRITEBACK
6665 regs[i].wasdirty&=wont_dirty_i|~(1<<r);
6666 #endif
6667 regs[i].wasdirty|=will_dirty_i&(1<<r);
6668 }
6669 }
6670 else {
6671 will_dirty_i&=~(1<<r);
6672 wont_dirty_i&=~(1<<r);
6673 if((regmap_pre[i][r]&63)>0 && (regmap_pre[i][r]&63)<34) {
6674 will_dirty_i|=((unneeded_reg[i]>>(regmap_pre[i][r]&63))&1)<<r;
6675 wont_dirty_i|=((unneeded_reg[i]>>(regmap_pre[i][r]&63))&1)<<r;
6676 } else {
6677 wont_dirty_i|=1<<r;
581335b0 6678 /*printf("i: %x (%d) mismatch: %d\n",start+i*4,i,r);assert(!((will_dirty>>r)&1));*/
57871462 6679 }
6680 }
6681 }
6682 }
6683 }
6684}
6685
4600ba03 6686#ifdef DISASM
57871462 6687 /* disassembly */
6688void disassemble_inst(int i)
6689{
cf95b4f0 6690 if (dops[i].bt) printf("*"); else printf(" ");
6691 switch(dops[i].itype) {
57871462 6692 case UJUMP:
6693 printf (" %x: %s %8x\n",start+i*4,insn[i],ba[i]);break;
6694 case CJUMP:
cf95b4f0 6695 printf (" %x: %s r%d,r%d,%8x\n",start+i*4,insn[i],dops[i].rs1,dops[i].rs2,i?start+i*4+4+((signed int)((unsigned int)source[i]<<16)>>14):*ba);break;
57871462 6696 case SJUMP:
cf95b4f0 6697 printf (" %x: %s r%d,%8x\n",start+i*4,insn[i],dops[i].rs1,start+i*4+4+((signed int)((unsigned int)source[i]<<16)>>14));break;
57871462 6698 case RJUMP:
cf95b4f0 6699 if (dops[i].opcode==0x9&&dops[i].rt1!=31)
6700 printf (" %x: %s r%d,r%d\n",start+i*4,insn[i],dops[i].rt1,dops[i].rs1);
5067f341 6701 else
cf95b4f0 6702 printf (" %x: %s r%d\n",start+i*4,insn[i],dops[i].rs1);
5067f341 6703 break;
57871462 6704 case SPAN:
cf95b4f0 6705 printf (" %x: %s (pagespan) r%d,r%d,%8x\n",start+i*4,insn[i],dops[i].rs1,dops[i].rs2,ba[i]);break;
57871462 6706 case IMM16:
cf95b4f0 6707 if(dops[i].opcode==0xf) //LUI
6708 printf (" %x: %s r%d,%4x0000\n",start+i*4,insn[i],dops[i].rt1,imm[i]&0xffff);
57871462 6709 else
cf95b4f0 6710 printf (" %x: %s r%d,r%d,%d\n",start+i*4,insn[i],dops[i].rt1,dops[i].rs1,imm[i]);
57871462 6711 break;
6712 case LOAD:
6713 case LOADLR:
cf95b4f0 6714 printf (" %x: %s r%d,r%d+%x\n",start+i*4,insn[i],dops[i].rt1,dops[i].rs1,imm[i]);
57871462 6715 break;
6716 case STORE:
6717 case STORELR:
cf95b4f0 6718 printf (" %x: %s r%d,r%d+%x\n",start+i*4,insn[i],dops[i].rs2,dops[i].rs1,imm[i]);
57871462 6719 break;
6720 case ALU:
6721 case SHIFT:
cf95b4f0 6722 printf (" %x: %s r%d,r%d,r%d\n",start+i*4,insn[i],dops[i].rt1,dops[i].rs1,dops[i].rs2);
57871462 6723 break;
6724 case MULTDIV:
cf95b4f0 6725 printf (" %x: %s r%d,r%d\n",start+i*4,insn[i],dops[i].rs1,dops[i].rs2);
57871462 6726 break;
6727 case SHIFTIMM:
cf95b4f0 6728 printf (" %x: %s r%d,r%d,%d\n",start+i*4,insn[i],dops[i].rt1,dops[i].rs1,imm[i]);
57871462 6729 break;
6730 case MOV:
cf95b4f0 6731 if((dops[i].opcode2&0x1d)==0x10)
6732 printf (" %x: %s r%d\n",start+i*4,insn[i],dops[i].rt1);
6733 else if((dops[i].opcode2&0x1d)==0x11)
6734 printf (" %x: %s r%d\n",start+i*4,insn[i],dops[i].rs1);
57871462 6735 else
6736 printf (" %x: %s\n",start+i*4,insn[i]);
6737 break;
6738 case COP0:
cf95b4f0 6739 if(dops[i].opcode2==0)
6740 printf (" %x: %s r%d,cpr0[%d]\n",start+i*4,insn[i],dops[i].rt1,(source[i]>>11)&0x1f); // MFC0
6741 else if(dops[i].opcode2==4)
6742 printf (" %x: %s r%d,cpr0[%d]\n",start+i*4,insn[i],dops[i].rs1,(source[i]>>11)&0x1f); // MTC0
57871462 6743 else printf (" %x: %s\n",start+i*4,insn[i]);
6744 break;
6745 case COP1:
cf95b4f0 6746 if(dops[i].opcode2<3)
6747 printf (" %x: %s r%d,cpr1[%d]\n",start+i*4,insn[i],dops[i].rt1,(source[i]>>11)&0x1f); // MFC1
6748 else if(dops[i].opcode2>3)
6749 printf (" %x: %s r%d,cpr1[%d]\n",start+i*4,insn[i],dops[i].rs1,(source[i]>>11)&0x1f); // MTC1
57871462 6750 else printf (" %x: %s\n",start+i*4,insn[i]);
6751 break;
b9b61529 6752 case COP2:
cf95b4f0 6753 if(dops[i].opcode2<3)
6754 printf (" %x: %s r%d,cpr2[%d]\n",start+i*4,insn[i],dops[i].rt1,(source[i]>>11)&0x1f); // MFC2
6755 else if(dops[i].opcode2>3)
6756 printf (" %x: %s r%d,cpr2[%d]\n",start+i*4,insn[i],dops[i].rs1,(source[i]>>11)&0x1f); // MTC2
b9b61529 6757 else printf (" %x: %s\n",start+i*4,insn[i]);
6758 break;
57871462 6759 case C1LS:
cf95b4f0 6760 printf (" %x: %s cpr1[%d],r%d+%x\n",start+i*4,insn[i],(source[i]>>16)&0x1f,dops[i].rs1,imm[i]);
57871462 6761 break;
b9b61529 6762 case C2LS:
cf95b4f0 6763 printf (" %x: %s cpr2[%d],r%d+%x\n",start+i*4,insn[i],(source[i]>>16)&0x1f,dops[i].rs1,imm[i]);
b9b61529 6764 break;
1e973cb0 6765 case INTCALL:
6766 printf (" %x: %s (INTCALL)\n",start+i*4,insn[i]);
6767 break;
57871462 6768 default:
6769 //printf (" %s %8x\n",insn[i],source[i]);
6770 printf (" %x: %s\n",start+i*4,insn[i]);
6771 }
6772}
4600ba03 6773#else
6774static void disassemble_inst(int i) {}
6775#endif // DISASM
57871462 6776
d848b60a 6777#define DRC_TEST_VAL 0x74657374
6778
be516ebe 6779static void new_dynarec_test(void)
d848b60a 6780{
be516ebe 6781 int (*testfunc)(void);
d148d265 6782 void *beginning;
be516ebe 6783 int ret[2];
6784 size_t i;
d148d265 6785
687b4580 6786 // check structure linkage
7c3a5182 6787 if ((u_char *)rcnts - (u_char *)&psxRegs != sizeof(psxRegs))
687b4580 6788 {
7c3a5182 6789 SysPrintf("linkage_arm* miscompilation/breakage detected.\n");
687b4580 6790 }
6791
761fdd0a 6792 SysPrintf("testing if we can run recompiled code @%p...\n", out);
be516ebe 6793 ((volatile u_int *)out)[0]++; // make cache dirty
6794
6795 for (i = 0; i < ARRAY_SIZE(ret); i++) {
2a014d73 6796 out = ndrc->translation_cache;
be516ebe 6797 beginning = start_block();
6798 emit_movimm(DRC_TEST_VAL + i, 0); // test
6799 emit_ret();
6800 literal_pool(0);
6801 end_block(beginning);
6802 testfunc = beginning;
6803 ret[i] = testfunc();
6804 }
6805
6806 if (ret[0] == DRC_TEST_VAL && ret[1] == DRC_TEST_VAL + 1)
d848b60a 6807 SysPrintf("test passed.\n");
6808 else
be516ebe 6809 SysPrintf("test failed, will likely crash soon (r=%08x %08x)\n", ret[0], ret[1]);
2a014d73 6810 out = ndrc->translation_cache;
d848b60a 6811}
6812
dc990066 6813// clear the state completely, instead of just marking
6814// things invalid like invalidate_all_pages() does
919981d0 6815void new_dynarec_clear_full(void)
57871462 6816{
57871462 6817 int n;
2a014d73 6818 out = ndrc->translation_cache;
35775df7 6819 memset(invalid_code,1,sizeof(invalid_code));
6820 memset(hash_table,0xff,sizeof(hash_table));
57871462 6821 memset(mini_ht,-1,sizeof(mini_ht));
6822 memset(restore_candidate,0,sizeof(restore_candidate));
dc990066 6823 memset(shadow,0,sizeof(shadow));
57871462 6824 copy=shadow;
6825 expirep=16384; // Expiry pointer, +2 blocks
6826 pending_exception=0;
6827 literalcount=0;
57871462 6828 stop_after_jal=0;
9be4ba64 6829 inv_code_start=inv_code_end=~0;
39b71d9a 6830 f1_hack=0;
57871462 6831 // TLB
dc990066 6832 for(n=0;n<4096;n++) ll_clear(jump_in+n);
6833 for(n=0;n<4096;n++) ll_clear(jump_out+n);
6834 for(n=0;n<4096;n++) ll_clear(jump_dirty+n);
32631e6a 6835
6836 cycle_multiplier_old = cycle_multiplier;
6837 new_dynarec_hacks_old = new_dynarec_hacks;
dc990066 6838}
6839
919981d0 6840void new_dynarec_init(void)
dc990066 6841{
d848b60a 6842 SysPrintf("Init new dynarec\n");
1e212a25 6843
0aeb0cb9 6844#ifdef _3DS
6845 check_rosalina();
6846#endif
2a014d73 6847#ifdef BASE_ADDR_DYNAMIC
1e212a25 6848 #ifdef VITA
0aeb0cb9 6849 sceBlock = getVMBlock(); //sceKernelAllocMemBlockForVM("code", sizeof(*ndrc));
1e212a25 6850 if (sceBlock < 0)
6851 SysPrintf("sceKernelAllocMemBlockForVM failed\n");
2a014d73 6852 int ret = sceKernelGetMemBlockBase(sceBlock, (void **)&ndrc);
1e212a25 6853 if (ret < 0)
6854 SysPrintf("sceKernelGetMemBlockBase failed\n");
0aeb0cb9 6855 sceKernelOpenVMDomain();
6856 sceClibPrintf("translation_cache = 0x%08lx\n ", (long)ndrc->translation_cache);
6857 #elif defined(_MSC_VER)
6858 ndrc = VirtualAlloc(NULL, sizeof(*ndrc), MEM_COMMIT | MEM_RESERVE,
6859 PAGE_EXECUTE_READWRITE);
1e212a25 6860 #else
2a014d73 6861 uintptr_t desired_addr = 0;
6862 #ifdef __ELF__
6863 extern char _end;
6864 desired_addr = ((uintptr_t)&_end + 0xffffff) & ~0xffffffl;
6865 #endif
6866 ndrc = mmap((void *)desired_addr, sizeof(*ndrc),
1e212a25 6867 PROT_READ | PROT_WRITE | PROT_EXEC,
6868 MAP_PRIVATE | MAP_ANONYMOUS, -1, 0);
2a014d73 6869 if (ndrc == MAP_FAILED) {
d848b60a 6870 SysPrintf("mmap() failed: %s\n", strerror(errno));
1e212a25 6871 abort();
d848b60a 6872 }
1e212a25 6873 #endif
6874#else
6875 #ifndef NO_WRITE_EXEC
bdeade46 6876 // not all systems allow execute in data segment by default
761fdd0a 6877 // size must be 4K aligned for 3DS?
6878 if (mprotect(ndrc, sizeof(*ndrc),
2a014d73 6879 PROT_READ | PROT_WRITE | PROT_EXEC) != 0)
d848b60a 6880 SysPrintf("mprotect() failed: %s\n", strerror(errno));
1e212a25 6881 #endif
dc990066 6882#endif
2a014d73 6883 out = ndrc->translation_cache;
2573466a 6884 cycle_multiplier=200;
dc990066 6885 new_dynarec_clear_full();
6886#ifdef HOST_IMM8
6887 // Copy this into local area so we don't have to put it in every literal pool
6888 invc_ptr=invalid_code;
6889#endif
57871462 6890 arch_init();
d848b60a 6891 new_dynarec_test();
01d26796 6892 ram_offset=(uintptr_t)rdram-0x80000000;
b105cf4f 6893 if (ram_offset!=0)
c43b5311 6894 SysPrintf("warning: RAM is not directly mapped, performance will suffer\n");
57871462 6895}
6896
919981d0 6897void new_dynarec_cleanup(void)
57871462 6898{
6899 int n;
2a014d73 6900#ifdef BASE_ADDR_DYNAMIC
1e212a25 6901 #ifdef VITA
6902 sceKernelFreeMemBlock(sceBlock);
6903 sceBlock = -1;
6904 #else
2a014d73 6905 if (munmap(ndrc, sizeof(*ndrc)) < 0)
1e212a25 6906 SysPrintf("munmap() failed\n");
bdeade46 6907 #endif
1e212a25 6908#endif
57871462 6909 for(n=0;n<4096;n++) ll_clear(jump_in+n);
6910 for(n=0;n<4096;n++) ll_clear(jump_out+n);
6911 for(n=0;n<4096;n++) ll_clear(jump_dirty+n);
6912 #ifdef ROM_COPY
c43b5311 6913 if (munmap (ROM_COPY, 67108864) < 0) {SysPrintf("munmap() failed\n");}
57871462 6914 #endif
6915}
6916
03f55e6b 6917static u_int *get_source_start(u_int addr, u_int *limit)
57871462 6918{
03f55e6b 6919 if (addr < 0x00200000 ||
a3203cf4 6920 (0xa0000000 <= addr && addr < 0xa0200000))
6921 {
03f55e6b 6922 // used for BIOS calls mostly?
6923 *limit = (addr&0xa0000000)|0x00200000;
01d26796 6924 return (u_int *)(rdram + (addr&0x1fffff));
03f55e6b 6925 }
6926 else if (!Config.HLE && (
6927 /* (0x9fc00000 <= addr && addr < 0x9fc80000) ||*/
a3203cf4 6928 (0xbfc00000 <= addr && addr < 0xbfc80000)))
6929 {
6930 // BIOS. The multiplier should be much higher as it's uncached 8bit mem,
6931 // but timings in PCSX are too tied to the interpreter's BIAS
d62c125a 6932 if (!HACK_ENABLED(NDHACK_OVERRIDE_CYCLE_M))
24058131 6933 cycle_multiplier_active = 200;
a3203cf4 6934
03f55e6b 6935 *limit = (addr & 0xfff00000) | 0x80000;
01d26796 6936 return (u_int *)((u_char *)psxR + (addr&0x7ffff));
03f55e6b 6937 }
6938 else if (addr >= 0x80000000 && addr < 0x80000000+RAM_SIZE) {
6939 *limit = (addr & 0x80600000) + 0x00200000;
01d26796 6940 return (u_int *)(rdram + (addr&0x1fffff));
03f55e6b 6941 }
581335b0 6942 return NULL;
03f55e6b 6943}
6944
6945static u_int scan_for_ret(u_int addr)
6946{
6947 u_int limit = 0;
6948 u_int *mem;
6949
6950 mem = get_source_start(addr, &limit);
6951 if (mem == NULL)
6952 return addr;
6953
6954 if (limit > addr + 0x1000)
6955 limit = addr + 0x1000;
6956 for (; addr < limit; addr += 4, mem++) {
6957 if (*mem == 0x03e00008) // jr $ra
6958 return addr + 8;
57871462 6959 }
581335b0 6960 return addr;
03f55e6b 6961}
6962
6963struct savestate_block {
6964 uint32_t addr;
6965 uint32_t regflags;
6966};
6967
6968static int addr_cmp(const void *p1_, const void *p2_)
6969{
6970 const struct savestate_block *p1 = p1_, *p2 = p2_;
6971 return p1->addr - p2->addr;
6972}
6973
6974int new_dynarec_save_blocks(void *save, int size)
6975{
6976 struct savestate_block *blocks = save;
6977 int maxcount = size / sizeof(blocks[0]);
6978 struct savestate_block tmp_blocks[1024];
6979 struct ll_entry *head;
6980 int p, s, d, o, bcnt;
6981 u_int addr;
6982
6983 o = 0;
b14b6a8f 6984 for (p = 0; p < ARRAY_SIZE(jump_in); p++) {
03f55e6b 6985 bcnt = 0;
6986 for (head = jump_in[p]; head != NULL; head = head->next) {
6987 tmp_blocks[bcnt].addr = head->vaddr;
6988 tmp_blocks[bcnt].regflags = head->reg_sv_flags;
6989 bcnt++;
6990 }
6991 if (bcnt < 1)
6992 continue;
6993 qsort(tmp_blocks, bcnt, sizeof(tmp_blocks[0]), addr_cmp);
6994
6995 addr = tmp_blocks[0].addr;
6996 for (s = d = 0; s < bcnt; s++) {
6997 if (tmp_blocks[s].addr < addr)
6998 continue;
6999 if (d == 0 || tmp_blocks[d-1].addr != tmp_blocks[s].addr)
7000 tmp_blocks[d++] = tmp_blocks[s];
7001 addr = scan_for_ret(tmp_blocks[s].addr);
7002 }
7003
7004 if (o + d > maxcount)
7005 d = maxcount - o;
7006 memcpy(&blocks[o], tmp_blocks, d * sizeof(blocks[0]));
7007 o += d;
7008 }
7009
7010 return o * sizeof(blocks[0]);
7011}
7012
7013void new_dynarec_load_blocks(const void *save, int size)
7014{
7015 const struct savestate_block *blocks = save;
7016 int count = size / sizeof(blocks[0]);
7017 u_int regs_save[32];
7018 uint32_t f;
7019 int i, b;
7020
7021 get_addr(psxRegs.pc);
7022
7023 // change GPRs for speculation to at least partially work..
7024 memcpy(regs_save, &psxRegs.GPR, sizeof(regs_save));
7025 for (i = 1; i < 32; i++)
7026 psxRegs.GPR.r[i] = 0x80000000;
7027
7028 for (b = 0; b < count; b++) {
7029 for (f = blocks[b].regflags, i = 0; f; f >>= 1, i++) {
7030 if (f & 1)
7031 psxRegs.GPR.r[i] = 0x1f800000;
7032 }
7033
7034 get_addr(blocks[b].addr);
7035
7036 for (f = blocks[b].regflags, i = 0; f; f >>= 1, i++) {
7037 if (f & 1)
7038 psxRegs.GPR.r[i] = 0x80000000;
7039 }
7040 }
7041
7042 memcpy(&psxRegs.GPR, regs_save, sizeof(regs_save));
7043}
7044
24058131 7045static void apply_hacks(void)
7046{
7047 int i;
7048 if (HACK_ENABLED(NDHACK_NO_COMPAT_HACKS))
7049 return;
7050 /* special hack(s) */
7051 for (i = 0; i < slen - 4; i++)
7052 {
7053 // lui a4, 0xf200; jal <rcnt_read>; addu a0, 2; slti v0, 28224
7054 if (source[i] == 0x3c04f200 && dops[i+1].itype == UJUMP
7055 && source[i+2] == 0x34840002 && dops[i+3].opcode == 0x0a
7056 && imm[i+3] == 0x6e40 && dops[i+3].rs1 == 2)
7057 {
7058 SysPrintf("PE2 hack @%08x\n", start + (i+3)*4);
7059 dops[i + 3].itype = NOP;
7060 }
7061 }
7062 i = slen;
7063 if (i > 10 && source[i-1] == 0 && source[i-2] == 0x03e00008
7064 && source[i-4] == 0x8fbf0018 && source[i-6] == 0x00c0f809
7065 && dops[i-7].itype == STORE)
7066 {
7067 i = i-8;
7068 if (dops[i].itype == IMM16)
7069 i--;
7070 // swl r2, 15(r6); swr r2, 12(r6); sw r6, *; jalr r6
7071 if (dops[i].itype == STORELR && dops[i].rs1 == 6
7072 && dops[i-1].itype == STORELR && dops[i-1].rs1 == 6)
7073 {
7074 SysPrintf("F1 hack from %08x\n", start);
7075 if (f1_hack == 0)
7076 f1_hack = ~0u;
7077 }
7078 }
7079}
7080
3968e69e 7081int new_recompile_block(u_int addr)
03f55e6b 7082{
7083 u_int pagelimit = 0;
7084 u_int state_rflags = 0;
7085 int i;
7086
1a4301c4 7087 assem_debug("NOTCOMPILED: addr = %x -> %p\n", addr, out);
57871462 7088 //printf("TRACE: count=%d next=%d (compile %x)\n",Count,next_interupt,addr);
9f51b4b9 7089 //if(debug)
57871462 7090 //printf("fpu mapping=%x enabled=%x\n",(Status & 0x04000000)>>26,(Status & 0x20000000)>>29);
03f55e6b 7091
7092 // this is just for speculation
7093 for (i = 1; i < 32; i++) {
7094 if ((psxRegs.GPR.r[i] & 0xffff0000) == 0x1f800000)
7095 state_rflags |= 1 << i;
7096 }
7097
57871462 7098 start = (u_int)addr&~3;
7c3a5182 7099 //assert(((u_int)addr&1)==0); // start-in-delay-slot flag
2f546f9a 7100 new_dynarec_did_compile=1;
9ad4d757 7101 if (Config.HLE && start == 0x80001000) // hlecall
560e4a12 7102 {
7139f3c8 7103 // XXX: is this enough? Maybe check hleSoftCall?
d148d265 7104 void *beginning=start_block();
7139f3c8 7105 u_int page=get_page(start);
d148d265 7106
7139f3c8 7107 invalid_code[start>>12]=0;
7108 emit_movimm(start,0);
643aeae3 7109 emit_writeword(0,&pcaddr);
2a014d73 7110 emit_far_jump(new_dyna_leave);
15776b68 7111 literal_pool(0);
d148d265 7112 end_block(beginning);
03f55e6b 7113 ll_add_flags(jump_in+page,start,state_rflags,(void *)beginning);
7139f3c8 7114 return 0;
7115 }
39b71d9a 7116 else if (f1_hack == ~0u || (f1_hack != 0 && start == f1_hack)) {
7117 void *beginning = start_block();
7118 u_int page = get_page(start);
7119 emit_readword(&psxRegs.GPR.n.sp, 0);
7120 emit_readptr(&mem_rtab, 1);
7121 emit_shrimm(0, 12, 2);
7122 emit_readptr_dualindexedx_ptrlen(1, 2, 1);
7123 emit_addimm(0, 0x18, 0);
7124 emit_adds_ptr(1, 1, 1);
7125 emit_ldr_dualindexed(1, 0, 0);
7126 emit_writeword(0, &psxRegs.GPR.r[26]); // lw k0, 0x18(sp)
7127 emit_far_call(get_addr_ht);
7128 emit_jmpreg(0); // jr k0
7129 literal_pool(0);
7130 end_block(beginning);
7131
7132 ll_add_flags(jump_in + page, start, state_rflags, beginning);
7133 SysPrintf("F1 hack to %08x\n", start);
7134 f1_hack = start;
7135 return 0;
7136 }
03f55e6b 7137
24058131 7138 cycle_multiplier_active = cycle_multiplier_override && cycle_multiplier == CYCLE_MULT_DEFAULT
7139 ? cycle_multiplier_override : cycle_multiplier;
7140
03f55e6b 7141 source = get_source_start(start, &pagelimit);
7142 if (source == NULL) {
7143 SysPrintf("Compile at bogus memory address: %08x\n", addr);
7c3a5182 7144 abort();
57871462 7145 }
7146
7147 /* Pass 1: disassemble */
7148 /* Pass 2: register dependencies, branch targets */
7149 /* Pass 3: register allocation */
7150 /* Pass 4: branch dependencies */
7151 /* Pass 5: pre-alloc */
7152 /* Pass 6: optimize clean/dirty state */
7153 /* Pass 7: flag 32-bit registers */
7154 /* Pass 8: assembly */
7155 /* Pass 9: linker */
7156 /* Pass 10: garbage collection / free memory */
7157
03f55e6b 7158 int j;
57871462 7159 int done=0;
7160 unsigned int type,op,op2;
7161
7162 //printf("addr = %x source = %x %x\n", addr,source,source[0]);
9f51b4b9 7163
57871462 7164 /* Pass 1 disassembly */
7165
7ebfcedf 7166 for (i = 0; !done; i++)
7167 {
7168 memset(&dops[i], 0, sizeof(dops[i]));
cf95b4f0 7169 op2=0;
e1190b87 7170 minimum_free_regs[i]=0;
cf95b4f0 7171 dops[i].opcode=op=source[i]>>26;
57871462 7172 switch(op)
7173 {
7174 case 0x00: strcpy(insn[i],"special"); type=NI;
7175 op2=source[i]&0x3f;
7176 switch(op2)
7177 {
7178 case 0x00: strcpy(insn[i],"SLL"); type=SHIFTIMM; break;
7179 case 0x02: strcpy(insn[i],"SRL"); type=SHIFTIMM; break;
7180 case 0x03: strcpy(insn[i],"SRA"); type=SHIFTIMM; break;
7181 case 0x04: strcpy(insn[i],"SLLV"); type=SHIFT; break;
7182 case 0x06: strcpy(insn[i],"SRLV"); type=SHIFT; break;
7183 case 0x07: strcpy(insn[i],"SRAV"); type=SHIFT; break;
7184 case 0x08: strcpy(insn[i],"JR"); type=RJUMP; break;
7185 case 0x09: strcpy(insn[i],"JALR"); type=RJUMP; break;
7186 case 0x0C: strcpy(insn[i],"SYSCALL"); type=SYSCALL; break;
7187 case 0x0D: strcpy(insn[i],"BREAK"); type=OTHER; break;
7188 case 0x0F: strcpy(insn[i],"SYNC"); type=OTHER; break;
7189 case 0x10: strcpy(insn[i],"MFHI"); type=MOV; break;
7190 case 0x11: strcpy(insn[i],"MTHI"); type=MOV; break;
7191 case 0x12: strcpy(insn[i],"MFLO"); type=MOV; break;
7192 case 0x13: strcpy(insn[i],"MTLO"); type=MOV; break;
57871462 7193 case 0x18: strcpy(insn[i],"MULT"); type=MULTDIV; break;
7194 case 0x19: strcpy(insn[i],"MULTU"); type=MULTDIV; break;
7195 case 0x1A: strcpy(insn[i],"DIV"); type=MULTDIV; break;
7196 case 0x1B: strcpy(insn[i],"DIVU"); type=MULTDIV; break;
57871462 7197 case 0x20: strcpy(insn[i],"ADD"); type=ALU; break;
7198 case 0x21: strcpy(insn[i],"ADDU"); type=ALU; break;
7199 case 0x22: strcpy(insn[i],"SUB"); type=ALU; break;
7200 case 0x23: strcpy(insn[i],"SUBU"); type=ALU; break;
7201 case 0x24: strcpy(insn[i],"AND"); type=ALU; break;
7202 case 0x25: strcpy(insn[i],"OR"); type=ALU; break;
7203 case 0x26: strcpy(insn[i],"XOR"); type=ALU; break;
7204 case 0x27: strcpy(insn[i],"NOR"); type=ALU; break;
7205 case 0x2A: strcpy(insn[i],"SLT"); type=ALU; break;
7206 case 0x2B: strcpy(insn[i],"SLTU"); type=ALU; break;
57871462 7207 case 0x30: strcpy(insn[i],"TGE"); type=NI; break;
7208 case 0x31: strcpy(insn[i],"TGEU"); type=NI; break;
7209 case 0x32: strcpy(insn[i],"TLT"); type=NI; break;
7210 case 0x33: strcpy(insn[i],"TLTU"); type=NI; break;
7211 case 0x34: strcpy(insn[i],"TEQ"); type=NI; break;
7212 case 0x36: strcpy(insn[i],"TNE"); type=NI; break;
71e490c5 7213#if 0
7f2607ea 7214 case 0x14: strcpy(insn[i],"DSLLV"); type=SHIFT; break;
7215 case 0x16: strcpy(insn[i],"DSRLV"); type=SHIFT; break;
7216 case 0x17: strcpy(insn[i],"DSRAV"); type=SHIFT; break;
7217 case 0x1C: strcpy(insn[i],"DMULT"); type=MULTDIV; break;
7218 case 0x1D: strcpy(insn[i],"DMULTU"); type=MULTDIV; break;
7219 case 0x1E: strcpy(insn[i],"DDIV"); type=MULTDIV; break;
7220 case 0x1F: strcpy(insn[i],"DDIVU"); type=MULTDIV; break;
7221 case 0x2C: strcpy(insn[i],"DADD"); type=ALU; break;
7222 case 0x2D: strcpy(insn[i],"DADDU"); type=ALU; break;
7223 case 0x2E: strcpy(insn[i],"DSUB"); type=ALU; break;
7224 case 0x2F: strcpy(insn[i],"DSUBU"); type=ALU; break;
57871462 7225 case 0x38: strcpy(insn[i],"DSLL"); type=SHIFTIMM; break;
7226 case 0x3A: strcpy(insn[i],"DSRL"); type=SHIFTIMM; break;
7227 case 0x3B: strcpy(insn[i],"DSRA"); type=SHIFTIMM; break;
7228 case 0x3C: strcpy(insn[i],"DSLL32"); type=SHIFTIMM; break;
7229 case 0x3E: strcpy(insn[i],"DSRL32"); type=SHIFTIMM; break;
7230 case 0x3F: strcpy(insn[i],"DSRA32"); type=SHIFTIMM; break;
7f2607ea 7231#endif
57871462 7232 }
7233 break;
7234 case 0x01: strcpy(insn[i],"regimm"); type=NI;
7235 op2=(source[i]>>16)&0x1f;
7236 switch(op2)
7237 {
7238 case 0x00: strcpy(insn[i],"BLTZ"); type=SJUMP; break;
7239 case 0x01: strcpy(insn[i],"BGEZ"); type=SJUMP; break;
4919de1e 7240 //case 0x02: strcpy(insn[i],"BLTZL"); type=SJUMP; break;
7241 //case 0x03: strcpy(insn[i],"BGEZL"); type=SJUMP; break;
7242 //case 0x08: strcpy(insn[i],"TGEI"); type=NI; break;
7243 //case 0x09: strcpy(insn[i],"TGEIU"); type=NI; break;
7244 //case 0x0A: strcpy(insn[i],"TLTI"); type=NI; break;
7245 //case 0x0B: strcpy(insn[i],"TLTIU"); type=NI; break;
7246 //case 0x0C: strcpy(insn[i],"TEQI"); type=NI; break;
7247 //case 0x0E: strcpy(insn[i],"TNEI"); type=NI; break;
57871462 7248 case 0x10: strcpy(insn[i],"BLTZAL"); type=SJUMP; break;
7249 case 0x11: strcpy(insn[i],"BGEZAL"); type=SJUMP; break;
4919de1e 7250 //case 0x12: strcpy(insn[i],"BLTZALL"); type=SJUMP; break;
7251 //case 0x13: strcpy(insn[i],"BGEZALL"); type=SJUMP; break;
57871462 7252 }
7253 break;
7254 case 0x02: strcpy(insn[i],"J"); type=UJUMP; break;
7255 case 0x03: strcpy(insn[i],"JAL"); type=UJUMP; break;
7256 case 0x04: strcpy(insn[i],"BEQ"); type=CJUMP; break;
7257 case 0x05: strcpy(insn[i],"BNE"); type=CJUMP; break;
7258 case 0x06: strcpy(insn[i],"BLEZ"); type=CJUMP; break;
7259 case 0x07: strcpy(insn[i],"BGTZ"); type=CJUMP; break;
7260 case 0x08: strcpy(insn[i],"ADDI"); type=IMM16; break;
7261 case 0x09: strcpy(insn[i],"ADDIU"); type=IMM16; break;
7262 case 0x0A: strcpy(insn[i],"SLTI"); type=IMM16; break;
7263 case 0x0B: strcpy(insn[i],"SLTIU"); type=IMM16; break;
7264 case 0x0C: strcpy(insn[i],"ANDI"); type=IMM16; break;
7265 case 0x0D: strcpy(insn[i],"ORI"); type=IMM16; break;
7266 case 0x0E: strcpy(insn[i],"XORI"); type=IMM16; break;
7267 case 0x0F: strcpy(insn[i],"LUI"); type=IMM16; break;
7268 case 0x10: strcpy(insn[i],"cop0"); type=NI;
7269 op2=(source[i]>>21)&0x1f;
7270 switch(op2)
7271 {
7272 case 0x00: strcpy(insn[i],"MFC0"); type=COP0; break;
00fa9369 7273 case 0x02: strcpy(insn[i],"CFC0"); type=COP0; break;
57871462 7274 case 0x04: strcpy(insn[i],"MTC0"); type=COP0; break;
00fa9369 7275 case 0x06: strcpy(insn[i],"CTC0"); type=COP0; break;
7276 case 0x10: strcpy(insn[i],"RFE"); type=COP0; break;
57871462 7277 }
7278 break;
00fa9369 7279 case 0x11: strcpy(insn[i],"cop1"); type=COP1;
57871462 7280 op2=(source[i]>>21)&0x1f;
57871462 7281 break;
71e490c5 7282#if 0
57871462 7283 case 0x14: strcpy(insn[i],"BEQL"); type=CJUMP; break;
7284 case 0x15: strcpy(insn[i],"BNEL"); type=CJUMP; break;
7285 case 0x16: strcpy(insn[i],"BLEZL"); type=CJUMP; break;
7286 case 0x17: strcpy(insn[i],"BGTZL"); type=CJUMP; break;
7287 case 0x18: strcpy(insn[i],"DADDI"); type=IMM16; break;
7288 case 0x19: strcpy(insn[i],"DADDIU"); type=IMM16; break;
7289 case 0x1A: strcpy(insn[i],"LDL"); type=LOADLR; break;
7290 case 0x1B: strcpy(insn[i],"LDR"); type=LOADLR; break;
996cc15d 7291#endif
57871462 7292 case 0x20: strcpy(insn[i],"LB"); type=LOAD; break;
7293 case 0x21: strcpy(insn[i],"LH"); type=LOAD; break;
7294 case 0x22: strcpy(insn[i],"LWL"); type=LOADLR; break;
7295 case 0x23: strcpy(insn[i],"LW"); type=LOAD; break;
7296 case 0x24: strcpy(insn[i],"LBU"); type=LOAD; break;
7297 case 0x25: strcpy(insn[i],"LHU"); type=LOAD; break;
7298 case 0x26: strcpy(insn[i],"LWR"); type=LOADLR; break;
71e490c5 7299#if 0
57871462 7300 case 0x27: strcpy(insn[i],"LWU"); type=LOAD; break;
64bd6f82 7301#endif
57871462 7302 case 0x28: strcpy(insn[i],"SB"); type=STORE; break;
7303 case 0x29: strcpy(insn[i],"SH"); type=STORE; break;
7304 case 0x2A: strcpy(insn[i],"SWL"); type=STORELR; break;
7305 case 0x2B: strcpy(insn[i],"SW"); type=STORE; break;
71e490c5 7306#if 0
57871462 7307 case 0x2C: strcpy(insn[i],"SDL"); type=STORELR; break;
7308 case 0x2D: strcpy(insn[i],"SDR"); type=STORELR; break;
996cc15d 7309#endif
57871462 7310 case 0x2E: strcpy(insn[i],"SWR"); type=STORELR; break;
7311 case 0x2F: strcpy(insn[i],"CACHE"); type=NOP; break;
7312 case 0x30: strcpy(insn[i],"LL"); type=NI; break;
7313 case 0x31: strcpy(insn[i],"LWC1"); type=C1LS; break;
71e490c5 7314#if 0
57871462 7315 case 0x34: strcpy(insn[i],"LLD"); type=NI; break;
7316 case 0x35: strcpy(insn[i],"LDC1"); type=C1LS; break;
7317 case 0x37: strcpy(insn[i],"LD"); type=LOAD; break;
996cc15d 7318#endif
57871462 7319 case 0x38: strcpy(insn[i],"SC"); type=NI; break;
7320 case 0x39: strcpy(insn[i],"SWC1"); type=C1LS; break;
71e490c5 7321#if 0
57871462 7322 case 0x3C: strcpy(insn[i],"SCD"); type=NI; break;
7323 case 0x3D: strcpy(insn[i],"SDC1"); type=C1LS; break;
7324 case 0x3F: strcpy(insn[i],"SD"); type=STORE; break;
996cc15d 7325#endif
b9b61529 7326 case 0x12: strcpy(insn[i],"COP2"); type=NI;
7327 op2=(source[i]>>21)&0x1f;
be516ebe 7328 //if (op2 & 0x10)
bedfea38 7329 if (source[i]&0x3f) { // use this hack to support old savestates with patched gte insns
c7abc864 7330 if (gte_handlers[source[i]&0x3f]!=NULL) {
bedfea38 7331 if (gte_regnames[source[i]&0x3f]!=NULL)
7332 strcpy(insn[i],gte_regnames[source[i]&0x3f]);
7333 else
7334 snprintf(insn[i], sizeof(insn[i]), "COP2 %x", source[i]&0x3f);
c7abc864 7335 type=C2OP;
7336 }
7337 }
7338 else switch(op2)
b9b61529 7339 {
7340 case 0x00: strcpy(insn[i],"MFC2"); type=COP2; break;
7341 case 0x02: strcpy(insn[i],"CFC2"); type=COP2; break;
7342 case 0x04: strcpy(insn[i],"MTC2"); type=COP2; break;
7343 case 0x06: strcpy(insn[i],"CTC2"); type=COP2; break;
b9b61529 7344 }
7345 break;
7346 case 0x32: strcpy(insn[i],"LWC2"); type=C2LS; break;
7347 case 0x3A: strcpy(insn[i],"SWC2"); type=C2LS; break;
7348 case 0x3B: strcpy(insn[i],"HLECALL"); type=HLECALL; break;
90ae6d4e 7349 default: strcpy(insn[i],"???"); type=NI;
c43b5311 7350 SysPrintf("NI %08x @%08x (%08x)\n", source[i], addr + i*4, addr);
90ae6d4e 7351 break;
57871462 7352 }
cf95b4f0 7353 dops[i].itype=type;
7354 dops[i].opcode2=op2;
57871462 7355 /* Get registers/immediates */
cf95b4f0 7356 dops[i].lt1=0;
bedfea38 7357 gte_rs[i]=gte_rt[i]=0;
57871462 7358 switch(type) {
7359 case LOAD:
cf95b4f0 7360 dops[i].rs1=(source[i]>>21)&0x1f;
7361 dops[i].rs2=0;
7362 dops[i].rt1=(source[i]>>16)&0x1f;
7363 dops[i].rt2=0;
57871462 7364 imm[i]=(short)source[i];
7365 break;
7366 case STORE:
7367 case STORELR:
cf95b4f0 7368 dops[i].rs1=(source[i]>>21)&0x1f;
7369 dops[i].rs2=(source[i]>>16)&0x1f;
7370 dops[i].rt1=0;
7371 dops[i].rt2=0;
57871462 7372 imm[i]=(short)source[i];
57871462 7373 break;
7374 case LOADLR:
7375 // LWL/LWR only load part of the register,
7376 // therefore the target register must be treated as a source too
cf95b4f0 7377 dops[i].rs1=(source[i]>>21)&0x1f;
7378 dops[i].rs2=(source[i]>>16)&0x1f;
7379 dops[i].rt1=(source[i]>>16)&0x1f;
7380 dops[i].rt2=0;
57871462 7381 imm[i]=(short)source[i];
57871462 7382 break;
7383 case IMM16:
cf95b4f0 7384 if (op==0x0f) dops[i].rs1=0; // LUI instruction has no source register
7385 else dops[i].rs1=(source[i]>>21)&0x1f;
7386 dops[i].rs2=0;
7387 dops[i].rt1=(source[i]>>16)&0x1f;
7388 dops[i].rt2=0;
57871462 7389 if(op>=0x0c&&op<=0x0e) { // ANDI/ORI/XORI
7390 imm[i]=(unsigned short)source[i];
7391 }else{
7392 imm[i]=(short)source[i];
7393 }
57871462 7394 break;
7395 case UJUMP:
cf95b4f0 7396 dops[i].rs1=0;
7397 dops[i].rs2=0;
7398 dops[i].rt1=0;
7399 dops[i].rt2=0;
57871462 7400 // The JAL instruction writes to r31.
7401 if (op&1) {
cf95b4f0 7402 dops[i].rt1=31;
57871462 7403 }
cf95b4f0 7404 dops[i].rs2=CCREG;
57871462 7405 break;
7406 case RJUMP:
cf95b4f0 7407 dops[i].rs1=(source[i]>>21)&0x1f;
7408 dops[i].rs2=0;
7409 dops[i].rt1=0;
7410 dops[i].rt2=0;
5067f341 7411 // The JALR instruction writes to rd.
57871462 7412 if (op2&1) {
cf95b4f0 7413 dops[i].rt1=(source[i]>>11)&0x1f;
57871462 7414 }
cf95b4f0 7415 dops[i].rs2=CCREG;
57871462 7416 break;
7417 case CJUMP:
cf95b4f0 7418 dops[i].rs1=(source[i]>>21)&0x1f;
7419 dops[i].rs2=(source[i]>>16)&0x1f;
7420 dops[i].rt1=0;
7421 dops[i].rt2=0;
57871462 7422 if(op&2) { // BGTZ/BLEZ
cf95b4f0 7423 dops[i].rs2=0;
57871462 7424 }
57871462 7425 break;
7426 case SJUMP:
cf95b4f0 7427 dops[i].rs1=(source[i]>>21)&0x1f;
7428 dops[i].rs2=CCREG;
7429 dops[i].rt1=0;
7430 dops[i].rt2=0;
57871462 7431 if(op2&0x10) { // BxxAL
cf95b4f0 7432 dops[i].rt1=31;
57871462 7433 // NOTE: If the branch is not taken, r31 is still overwritten
7434 }
57871462 7435 break;
57871462 7436 case ALU:
cf95b4f0 7437 dops[i].rs1=(source[i]>>21)&0x1f; // source
7438 dops[i].rs2=(source[i]>>16)&0x1f; // subtract amount
7439 dops[i].rt1=(source[i]>>11)&0x1f; // destination
7440 dops[i].rt2=0;
57871462 7441 break;
7442 case MULTDIV:
cf95b4f0 7443 dops[i].rs1=(source[i]>>21)&0x1f; // source
7444 dops[i].rs2=(source[i]>>16)&0x1f; // divisor
7445 dops[i].rt1=HIREG;
7446 dops[i].rt2=LOREG;
57871462 7447 break;
7448 case MOV:
cf95b4f0 7449 dops[i].rs1=0;
7450 dops[i].rs2=0;
7451 dops[i].rt1=0;
7452 dops[i].rt2=0;
7453 if(op2==0x10) dops[i].rs1=HIREG; // MFHI
7454 if(op2==0x11) dops[i].rt1=HIREG; // MTHI
7455 if(op2==0x12) dops[i].rs1=LOREG; // MFLO
7456 if(op2==0x13) dops[i].rt1=LOREG; // MTLO
7457 if((op2&0x1d)==0x10) dops[i].rt1=(source[i]>>11)&0x1f; // MFxx
7458 if((op2&0x1d)==0x11) dops[i].rs1=(source[i]>>21)&0x1f; // MTxx
57871462 7459 break;
7460 case SHIFT:
cf95b4f0 7461 dops[i].rs1=(source[i]>>16)&0x1f; // target of shift
7462 dops[i].rs2=(source[i]>>21)&0x1f; // shift amount
7463 dops[i].rt1=(source[i]>>11)&0x1f; // destination
7464 dops[i].rt2=0;
57871462 7465 break;
7466 case SHIFTIMM:
cf95b4f0 7467 dops[i].rs1=(source[i]>>16)&0x1f;
7468 dops[i].rs2=0;
7469 dops[i].rt1=(source[i]>>11)&0x1f;
7470 dops[i].rt2=0;
57871462 7471 imm[i]=(source[i]>>6)&0x1f;
7472 // DSxx32 instructions
7473 if(op2>=0x3c) imm[i]|=0x20;
57871462 7474 break;
7475 case COP0:
cf95b4f0 7476 dops[i].rs1=0;
7477 dops[i].rs2=0;
7478 dops[i].rt1=0;
7479 dops[i].rt2=0;
7480 if(op2==0||op2==2) dops[i].rt1=(source[i]>>16)&0x1F; // MFC0/CFC0
7481 if(op2==4||op2==6) dops[i].rs1=(source[i]>>16)&0x1F; // MTC0/CTC0
7482 if(op2==4&&((source[i]>>11)&0x1f)==12) dops[i].rt2=CSREG; // Status
7483 if(op2==16) if((source[i]&0x3f)==0x18) dops[i].rs2=CCREG; // ERET
57871462 7484 break;
7485 case COP1:
cf95b4f0 7486 dops[i].rs1=0;
7487 dops[i].rs2=0;
7488 dops[i].rt1=0;
7489 dops[i].rt2=0;
7490 if(op2<3) dops[i].rt1=(source[i]>>16)&0x1F; // MFC1/DMFC1/CFC1
7491 if(op2>3) dops[i].rs1=(source[i]>>16)&0x1F; // MTC1/DMTC1/CTC1
7492 dops[i].rs2=CSREG;
57871462 7493 break;
bedfea38 7494 case COP2:
cf95b4f0 7495 dops[i].rs1=0;
7496 dops[i].rs2=0;
7497 dops[i].rt1=0;
7498 dops[i].rt2=0;
7499 if(op2<3) dops[i].rt1=(source[i]>>16)&0x1F; // MFC2/CFC2
7500 if(op2>3) dops[i].rs1=(source[i]>>16)&0x1F; // MTC2/CTC2
7501 dops[i].rs2=CSREG;
bedfea38 7502 int gr=(source[i]>>11)&0x1F;
7503 switch(op2)
7504 {
7505 case 0x00: gte_rs[i]=1ll<<gr; break; // MFC2
7506 case 0x04: gte_rt[i]=1ll<<gr; break; // MTC2
0ff8c62c 7507 case 0x02: gte_rs[i]=1ll<<(gr+32); break; // CFC2
bedfea38 7508 case 0x06: gte_rt[i]=1ll<<(gr+32); break; // CTC2
7509 }
7510 break;
57871462 7511 case C1LS:
cf95b4f0 7512 dops[i].rs1=(source[i]>>21)&0x1F;
7513 dops[i].rs2=CSREG;
7514 dops[i].rt1=0;
7515 dops[i].rt2=0;
57871462 7516 imm[i]=(short)source[i];
7517 break;
b9b61529 7518 case C2LS:
cf95b4f0 7519 dops[i].rs1=(source[i]>>21)&0x1F;
7520 dops[i].rs2=0;
7521 dops[i].rt1=0;
7522 dops[i].rt2=0;
b9b61529 7523 imm[i]=(short)source[i];
bedfea38 7524 if(op==0x32) gte_rt[i]=1ll<<((source[i]>>16)&0x1F); // LWC2
7525 else gte_rs[i]=1ll<<((source[i]>>16)&0x1F); // SWC2
7526 break;
7527 case C2OP:
cf95b4f0 7528 dops[i].rs1=0;
7529 dops[i].rs2=0;
7530 dops[i].rt1=0;
7531 dops[i].rt2=0;
2167bef6 7532 gte_rs[i]=gte_reg_reads[source[i]&0x3f];
7533 gte_rt[i]=gte_reg_writes[source[i]&0x3f];
7534 gte_rt[i]|=1ll<<63; // every op changes flags
587a5b1c 7535 if((source[i]&0x3f)==GTE_MVMVA) {
7536 int v = (source[i] >> 15) & 3;
7537 gte_rs[i]&=~0xe3fll;
7538 if(v==3) gte_rs[i]|=0xe00ll;
7539 else gte_rs[i]|=3ll<<(v*2);
7540 }
b9b61529 7541 break;
57871462 7542 case SYSCALL:
7139f3c8 7543 case HLECALL:
1e973cb0 7544 case INTCALL:
cf95b4f0 7545 dops[i].rs1=CCREG;
7546 dops[i].rs2=0;
7547 dops[i].rt1=0;
7548 dops[i].rt2=0;
57871462 7549 break;
7550 default:
cf95b4f0 7551 dops[i].rs1=0;
7552 dops[i].rs2=0;
7553 dops[i].rt1=0;
7554 dops[i].rt2=0;
57871462 7555 }
7556 /* Calculate branch target addresses */
7557 if(type==UJUMP)
7558 ba[i]=((start+i*4+4)&0xF0000000)|(((unsigned int)source[i]<<6)>>4);
cf95b4f0 7559 else if(type==CJUMP&&dops[i].rs1==dops[i].rs2&&(op&1))
57871462 7560 ba[i]=start+i*4+8; // Ignore never taken branch
cf95b4f0 7561 else if(type==SJUMP&&dops[i].rs1==0&&!(op2&1))
57871462 7562 ba[i]=start+i*4+8; // Ignore never taken branch
ad49de89 7563 else if(type==CJUMP||type==SJUMP)
57871462 7564 ba[i]=start+i*4+4+((signed int)((unsigned int)source[i]<<16)>>14);
7565 else ba[i]=-1;
4919de1e 7566
7567 /* simplify always (not)taken branches */
cf95b4f0 7568 if (type == CJUMP && dops[i].rs1 == dops[i].rs2) {
7569 dops[i].rs1 = dops[i].rs2 = 0;
4919de1e 7570 if (!(op & 1)) {
cf95b4f0 7571 dops[i].itype = type = UJUMP;
7572 dops[i].rs2 = CCREG;
4919de1e 7573 }
7574 }
cf95b4f0 7575 else if (type == SJUMP && dops[i].rs1 == 0 && (op2 & 1))
7576 dops[i].itype = type = UJUMP;
4919de1e 7577
fe807a8a 7578 dops[i].is_jump = (dops[i].itype == RJUMP || dops[i].itype == UJUMP || dops[i].itype == CJUMP || dops[i].itype == SJUMP);
7579 dops[i].is_ujump = (dops[i].itype == RJUMP || dops[i].itype == UJUMP); // || (source[i] >> 16) == 0x1000 // beq r0,r0
37387d8b 7580 dops[i].is_load = (dops[i].itype == LOAD || dops[i].itype == LOADLR || op == 0x32); // LWC2
7581 dops[i].is_store = (dops[i].itype == STORE || dops[i].itype == STORELR || op == 0x3a); // SWC2
fe807a8a 7582
4919de1e 7583 /* messy cases to just pass over to the interpreter */
fe807a8a 7584 if (i > 0 && dops[i-1].is_jump) {
3e535354 7585 int do_in_intrp=0;
7586 // branch in delay slot?
fe807a8a 7587 if (dops[i].is_jump) {
3e535354 7588 // don't handle first branch and call interpreter if it's hit
c43b5311 7589 SysPrintf("branch in delay slot @%08x (%08x)\n", addr + i*4, addr);
3e535354 7590 do_in_intrp=1;
7591 }
7592 // basic load delay detection
cf95b4f0 7593 else if((type==LOAD||type==LOADLR||type==COP0||type==COP2||type==C2LS)&&dops[i].rt1!=0) {
3e535354 7594 int t=(ba[i-1]-start)/4;
cf95b4f0 7595 if(0 <= t && t < i &&(dops[i].rt1==dops[t].rs1||dops[i].rt1==dops[t].rs2)&&dops[t].itype!=CJUMP&&dops[t].itype!=SJUMP) {
3e535354 7596 // jump target wants DS result - potential load delay effect
c43b5311 7597 SysPrintf("load delay @%08x (%08x)\n", addr + i*4, addr);
3e535354 7598 do_in_intrp=1;
cf95b4f0 7599 dops[t+1].bt=1; // expected return from interpreter
3e535354 7600 }
cf95b4f0 7601 else if(i>=2&&dops[i-2].rt1==2&&dops[i].rt1==2&&dops[i].rs1!=2&&dops[i].rs2!=2&&dops[i-1].rs1!=2&&dops[i-1].rs2!=2&&
fe807a8a 7602 !(i>=3&&dops[i-3].is_jump)) {
3e535354 7603 // v0 overwrite like this is a sign of trouble, bail out
c43b5311 7604 SysPrintf("v0 overwrite @%08x (%08x)\n", addr + i*4, addr);
3e535354 7605 do_in_intrp=1;
7606 }
7607 }
7ebfcedf 7608 if (do_in_intrp) {
7609 memset(&dops[i-1], 0, sizeof(dops[i-1]));
7610 dops[i-1].itype = INTCALL;
7611 dops[i-1].rs1 = CCREG;
7612 ba[i-1] = -1;
7613 done = 2;
3e535354 7614 i--; // don't compile the DS
26869094 7615 }
3e535354 7616 }
4919de1e 7617
3e535354 7618 /* Is this the end of the block? */
fe807a8a 7619 if (i > 0 && dops[i-1].is_ujump) {
cf95b4f0 7620 if(dops[i-1].rt1==0) { // Continue past subroutine call (JAL)
1e973cb0 7621 done=2;
57871462 7622 }
7623 else {
7624 if(stop_after_jal) done=1;
7625 // Stop on BREAK
7626 if((source[i+1]&0xfc00003f)==0x0d) done=1;
7627 }
7628 // Don't recompile stuff that's already compiled
7629 if(check_addr(start+i*4+4)) done=1;
7630 // Don't get too close to the limit
7631 if(i>MAXBLOCK/2) done=1;
7632 }
cf95b4f0 7633 if(dops[i].itype==SYSCALL&&stop_after_jal) done=1;
7634 if(dops[i].itype==HLECALL||dops[i].itype==INTCALL) done=2;
1e973cb0 7635 if(done==2) {
7636 // Does the block continue due to a branch?
7637 for(j=i-1;j>=0;j--)
7638 {
2a706964 7639 if(ba[j]==start+i*4) done=j=0; // Branch into delay slot
1e973cb0 7640 if(ba[j]==start+i*4+4) done=j=0;
7641 if(ba[j]==start+i*4+8) done=j=0;
7642 }
7643 }
75dec299 7644 //assert(i<MAXBLOCK-1);
57871462 7645 if(start+i*4==pagelimit-4) done=1;
7646 assert(start+i*4<pagelimit);
7647 if (i==MAXBLOCK-1) done=1;
7648 // Stop if we're compiling junk
cf95b4f0 7649 if(dops[i].itype==NI&&dops[i].opcode==0x11) {
57871462 7650 done=stop_after_jal=1;
c43b5311 7651 SysPrintf("Disabled speculative precompilation\n");
57871462 7652 }
7653 }
7654 slen=i;
fe807a8a 7655 if (dops[i-1].is_jump) {
57871462 7656 if(start+i*4==pagelimit) {
cf95b4f0 7657 dops[i-1].itype=SPAN;
57871462 7658 }
7659 }
7660 assert(slen>0);
7661
24058131 7662 apply_hacks();
39b71d9a 7663
57871462 7664 /* Pass 2 - Register dependencies and branch targets */
7665
7666 unneeded_registers(0,slen-1,0);
9f51b4b9 7667
57871462 7668 /* Pass 3 - Register allocation */
7669
7670 struct regstat current; // Current register allocations/status
57871462 7671 current.dirty=0;
7672 current.u=unneeded_reg[0];
57871462 7673 clear_all_regs(current.regmap);
7674 alloc_reg(&current,0,CCREG);
7675 dirty_reg(&current,CCREG);
7676 current.isconst=0;
7677 current.wasconst=0;
27727b63 7678 current.waswritten=0;
57871462 7679 int ds=0;
7680 int cc=0;
5194fb95 7681 int hr=-1;
6ebf4adf 7682
57871462 7683 if((u_int)addr&1) {
7684 // First instruction is delay slot
7685 cc=-1;
cf95b4f0 7686 dops[1].bt=1;
57871462 7687 ds=1;
7688 unneeded_reg[0]=1;
57871462 7689 current.regmap[HOST_BTREG]=BTREG;
7690 }
9f51b4b9 7691
57871462 7692 for(i=0;i<slen;i++)
7693 {
cf95b4f0 7694 if(dops[i].bt)
57871462 7695 {
7696 int hr;
7697 for(hr=0;hr<HOST_REGS;hr++)
7698 {
7699 // Is this really necessary?
7700 if(current.regmap[hr]==0) current.regmap[hr]=-1;
7701 }
7702 current.isconst=0;
27727b63 7703 current.waswritten=0;
57871462 7704 }
24385cae 7705
57871462 7706 memcpy(regmap_pre[i],current.regmap,sizeof(current.regmap));
7707 regs[i].wasconst=current.isconst;
57871462 7708 regs[i].wasdirty=current.dirty;
8575a877 7709 regs[i].loadedconst=0;
fe807a8a 7710 if (!dops[i].is_jump) {
57871462 7711 if(i+1<slen) {
cf95b4f0 7712 current.u=unneeded_reg[i+1]&~((1LL<<dops[i].rs1)|(1LL<<dops[i].rs2));
57871462 7713 current.u|=1;
57871462 7714 } else {
7715 current.u=1;
57871462 7716 }
7717 } else {
7718 if(i+1<slen) {
cf95b4f0 7719 current.u=branch_unneeded_reg[i]&~((1LL<<dops[i+1].rs1)|(1LL<<dops[i+1].rs2));
7720 current.u&=~((1LL<<dops[i].rs1)|(1LL<<dops[i].rs2));
57871462 7721 current.u|=1;
7ebfcedf 7722 } else {
7723 SysPrintf("oops, branch at end of block with no delay slot @%08x\n", start + i*4);
7724 abort();
7725 }
57871462 7726 }
cf95b4f0 7727 dops[i].is_ds=ds;
57871462 7728 if(ds) {
7729 ds=0; // Skip delay slot, already allocated as part of branch
7730 // ...but we need to alloc it in case something jumps here
7731 if(i+1<slen) {
7732 current.u=branch_unneeded_reg[i-1]&unneeded_reg[i+1];
57871462 7733 }else{
7734 current.u=branch_unneeded_reg[i-1];
57871462 7735 }
cf95b4f0 7736 current.u&=~((1LL<<dops[i].rs1)|(1LL<<dops[i].rs2));
57871462 7737 current.u|=1;
57871462 7738 struct regstat temp;
7739 memcpy(&temp,&current,sizeof(current));
7740 temp.wasdirty=temp.dirty;
57871462 7741 // TODO: Take into account unconditional branches, as below
7742 delayslot_alloc(&temp,i);
7743 memcpy(regs[i].regmap,temp.regmap,sizeof(temp.regmap));
7744 regs[i].wasdirty=temp.wasdirty;
57871462 7745 regs[i].dirty=temp.dirty;
57871462 7746 regs[i].isconst=0;
7747 regs[i].wasconst=0;
7748 current.isconst=0;
7749 // Create entry (branch target) regmap
7750 for(hr=0;hr<HOST_REGS;hr++)
7751 {
7752 int r=temp.regmap[hr];
7753 if(r>=0) {
7754 if(r!=regmap_pre[i][hr]) {
7755 regs[i].regmap_entry[hr]=-1;
7756 }
7757 else
7758 {
7c3a5182 7759 assert(r < 64);
57871462 7760 if((current.u>>r)&1) {
7761 regs[i].regmap_entry[hr]=-1;
7762 regs[i].regmap[hr]=-1;
7763 //Don't clear regs in the delay slot as the branch might need them
7764 //current.regmap[hr]=-1;
7765 }else
7766 regs[i].regmap_entry[hr]=r;
57871462 7767 }
7768 } else {
7769 // First instruction expects CCREG to be allocated
9f51b4b9 7770 if(i==0&&hr==HOST_CCREG)
57871462 7771 regs[i].regmap_entry[hr]=CCREG;
7772 else
7773 regs[i].regmap_entry[hr]=-1;
7774 }
7775 }
7776 }
7777 else { // Not delay slot
cf95b4f0 7778 switch(dops[i].itype) {
57871462 7779 case UJUMP:
7780 //current.isconst=0; // DEBUG
7781 //current.wasconst=0; // DEBUG
7782 //regs[i].wasconst=0; // DEBUG
cf95b4f0 7783 clear_const(&current,dops[i].rt1);
57871462 7784 alloc_cc(&current,i);
7785 dirty_reg(&current,CCREG);
cf95b4f0 7786 if (dops[i].rt1==31) {
57871462 7787 alloc_reg(&current,i,31);
7788 dirty_reg(&current,31);
cf95b4f0 7789 //assert(dops[i+1].rs1!=31&&dops[i+1].rs2!=31);
7790 //assert(dops[i+1].rt1!=dops[i].rt1);
57871462 7791 #ifdef REG_PREFETCH
7792 alloc_reg(&current,i,PTEMP);
7793 #endif
57871462 7794 }
cf95b4f0 7795 dops[i].ooo=1;
269bb29a 7796 delayslot_alloc(&current,i+1);
57871462 7797 //current.isconst=0; // DEBUG
7798 ds=1;
7799 //printf("i=%d, isconst=%x\n",i,current.isconst);
7800 break;
7801 case RJUMP:
7802 //current.isconst=0;
7803 //current.wasconst=0;
7804 //regs[i].wasconst=0;
cf95b4f0 7805 clear_const(&current,dops[i].rs1);
7806 clear_const(&current,dops[i].rt1);
57871462 7807 alloc_cc(&current,i);
7808 dirty_reg(&current,CCREG);
4919de1e 7809 if (!ds_writes_rjump_rs(i)) {
cf95b4f0 7810 alloc_reg(&current,i,dops[i].rs1);
7811 if (dops[i].rt1!=0) {
7812 alloc_reg(&current,i,dops[i].rt1);
7813 dirty_reg(&current,dops[i].rt1);
7814 assert(dops[i+1].rs1!=dops[i].rt1&&dops[i+1].rs2!=dops[i].rt1);
7815 assert(dops[i+1].rt1!=dops[i].rt1);
57871462 7816 #ifdef REG_PREFETCH
7817 alloc_reg(&current,i,PTEMP);
7818 #endif
7819 }
7820 #ifdef USE_MINI_HT
cf95b4f0 7821 if(dops[i].rs1==31) { // JALR
57871462 7822 alloc_reg(&current,i,RHASH);
57871462 7823 alloc_reg(&current,i,RHTBL);
57871462 7824 }
7825 #endif
7826 delayslot_alloc(&current,i+1);
7827 } else {
7828 // The delay slot overwrites our source register,
7829 // allocate a temporary register to hold the old value.
7830 current.isconst=0;
7831 current.wasconst=0;
7832 regs[i].wasconst=0;
7833 delayslot_alloc(&current,i+1);
7834 current.isconst=0;
7835 alloc_reg(&current,i,RTEMP);
7836 }
7837 //current.isconst=0; // DEBUG
cf95b4f0 7838 dops[i].ooo=1;
57871462 7839 ds=1;
7840 break;
7841 case CJUMP:
7842 //current.isconst=0;
7843 //current.wasconst=0;
7844 //regs[i].wasconst=0;
cf95b4f0 7845 clear_const(&current,dops[i].rs1);
7846 clear_const(&current,dops[i].rs2);
7847 if((dops[i].opcode&0x3E)==4) // BEQ/BNE
57871462 7848 {
7849 alloc_cc(&current,i);
7850 dirty_reg(&current,CCREG);
cf95b4f0 7851 if(dops[i].rs1) alloc_reg(&current,i,dops[i].rs1);
7852 if(dops[i].rs2) alloc_reg(&current,i,dops[i].rs2);
7853 if((dops[i].rs1&&(dops[i].rs1==dops[i+1].rt1||dops[i].rs1==dops[i+1].rt2))||
7854 (dops[i].rs2&&(dops[i].rs2==dops[i+1].rt1||dops[i].rs2==dops[i+1].rt2))) {
57871462 7855 // The delay slot overwrites one of our conditions.
7856 // Allocate the branch condition registers instead.
57871462 7857 current.isconst=0;
7858 current.wasconst=0;
7859 regs[i].wasconst=0;
cf95b4f0 7860 if(dops[i].rs1) alloc_reg(&current,i,dops[i].rs1);
7861 if(dops[i].rs2) alloc_reg(&current,i,dops[i].rs2);
57871462 7862 }
e1190b87 7863 else
7864 {
cf95b4f0 7865 dops[i].ooo=1;
e1190b87 7866 delayslot_alloc(&current,i+1);
7867 }
57871462 7868 }
7869 else
cf95b4f0 7870 if((dops[i].opcode&0x3E)==6) // BLEZ/BGTZ
57871462 7871 {
7872 alloc_cc(&current,i);
7873 dirty_reg(&current,CCREG);
cf95b4f0 7874 alloc_reg(&current,i,dops[i].rs1);
7875 if(dops[i].rs1&&(dops[i].rs1==dops[i+1].rt1||dops[i].rs1==dops[i+1].rt2)) {
57871462 7876 // The delay slot overwrites one of our conditions.
7877 // Allocate the branch condition registers instead.
57871462 7878 current.isconst=0;
7879 current.wasconst=0;
7880 regs[i].wasconst=0;
cf95b4f0 7881 if(dops[i].rs1) alloc_reg(&current,i,dops[i].rs1);
57871462 7882 }
e1190b87 7883 else
7884 {
cf95b4f0 7885 dops[i].ooo=1;
e1190b87 7886 delayslot_alloc(&current,i+1);
7887 }
57871462 7888 }
7889 else
7890 // Don't alloc the delay slot yet because we might not execute it
cf95b4f0 7891 if((dops[i].opcode&0x3E)==0x14) // BEQL/BNEL
57871462 7892 {
7893 current.isconst=0;
7894 current.wasconst=0;
7895 regs[i].wasconst=0;
7896 alloc_cc(&current,i);
7897 dirty_reg(&current,CCREG);
cf95b4f0 7898 alloc_reg(&current,i,dops[i].rs1);
7899 alloc_reg(&current,i,dops[i].rs2);
57871462 7900 }
7901 else
cf95b4f0 7902 if((dops[i].opcode&0x3E)==0x16) // BLEZL/BGTZL
57871462 7903 {
7904 current.isconst=0;
7905 current.wasconst=0;
7906 regs[i].wasconst=0;
7907 alloc_cc(&current,i);
7908 dirty_reg(&current,CCREG);
cf95b4f0 7909 alloc_reg(&current,i,dops[i].rs1);
57871462 7910 }
7911 ds=1;
7912 //current.isconst=0;
7913 break;
7914 case SJUMP:
7915 //current.isconst=0;
7916 //current.wasconst=0;
7917 //regs[i].wasconst=0;
cf95b4f0 7918 clear_const(&current,dops[i].rs1);
7919 clear_const(&current,dops[i].rt1);
7920 //if((dops[i].opcode2&0x1E)==0x0) // BLTZ/BGEZ
7921 if((dops[i].opcode2&0x0E)==0x0) // BLTZ/BGEZ
57871462 7922 {
7923 alloc_cc(&current,i);
7924 dirty_reg(&current,CCREG);
cf95b4f0 7925 alloc_reg(&current,i,dops[i].rs1);
7926 if (dops[i].rt1==31) { // BLTZAL/BGEZAL
57871462 7927 alloc_reg(&current,i,31);
7928 dirty_reg(&current,31);
57871462 7929 //#ifdef REG_PREFETCH
7930 //alloc_reg(&current,i,PTEMP);
7931 //#endif
57871462 7932 }
cf95b4f0 7933 if((dops[i].rs1&&(dops[i].rs1==dops[i+1].rt1||dops[i].rs1==dops[i+1].rt2)) // The delay slot overwrites the branch condition.
7934 ||(dops[i].rt1==31&&(dops[i+1].rs1==31||dops[i+1].rs2==31||dops[i+1].rt1==31||dops[i+1].rt2==31))) { // DS touches $ra
57871462 7935 // Allocate the branch condition registers instead.
57871462 7936 current.isconst=0;
7937 current.wasconst=0;
7938 regs[i].wasconst=0;
cf95b4f0 7939 if(dops[i].rs1) alloc_reg(&current,i,dops[i].rs1);
57871462 7940 }
e1190b87 7941 else
7942 {
cf95b4f0 7943 dops[i].ooo=1;
e1190b87 7944 delayslot_alloc(&current,i+1);
7945 }
57871462 7946 }
7947 else
7948 // Don't alloc the delay slot yet because we might not execute it
cf95b4f0 7949 if((dops[i].opcode2&0x1E)==0x2) // BLTZL/BGEZL
57871462 7950 {
7951 current.isconst=0;
7952 current.wasconst=0;
7953 regs[i].wasconst=0;
7954 alloc_cc(&current,i);
7955 dirty_reg(&current,CCREG);
cf95b4f0 7956 alloc_reg(&current,i,dops[i].rs1);
57871462 7957 }
7958 ds=1;
7959 //current.isconst=0;
7960 break;
57871462 7961 case IMM16:
7962 imm16_alloc(&current,i);
7963 break;
7964 case LOAD:
7965 case LOADLR:
7966 load_alloc(&current,i);
7967 break;
7968 case STORE:
7969 case STORELR:
7970 store_alloc(&current,i);
7971 break;
7972 case ALU:
7973 alu_alloc(&current,i);
7974 break;
7975 case SHIFT:
7976 shift_alloc(&current,i);
7977 break;
7978 case MULTDIV:
7979 multdiv_alloc(&current,i);
7980 break;
7981 case SHIFTIMM:
7982 shiftimm_alloc(&current,i);
7983 break;
7984 case MOV:
7985 mov_alloc(&current,i);
7986 break;
7987 case COP0:
7988 cop0_alloc(&current,i);
7989 break;
7990 case COP1:
81dbbf4c 7991 break;
b9b61529 7992 case COP2:
81dbbf4c 7993 cop2_alloc(&current,i);
57871462 7994 break;
7995 case C1LS:
7996 c1ls_alloc(&current,i);
7997 break;
b9b61529 7998 case C2LS:
7999 c2ls_alloc(&current,i);
8000 break;
8001 case C2OP:
8002 c2op_alloc(&current,i);
8003 break;
57871462 8004 case SYSCALL:
7139f3c8 8005 case HLECALL:
1e973cb0 8006 case INTCALL:
57871462 8007 syscall_alloc(&current,i);
8008 break;
8009 case SPAN:
8010 pagespan_alloc(&current,i);
8011 break;
8012 }
9f51b4b9 8013
57871462 8014 // Create entry (branch target) regmap
8015 for(hr=0;hr<HOST_REGS;hr++)
8016 {
581335b0 8017 int r,or;
57871462 8018 r=current.regmap[hr];
8019 if(r>=0) {
8020 if(r!=regmap_pre[i][hr]) {
8021 // TODO: delay slot (?)
8022 or=get_reg(regmap_pre[i],r); // Get old mapping for this register
8023 if(or<0||(r&63)>=TEMPREG){
8024 regs[i].regmap_entry[hr]=-1;
8025 }
8026 else
8027 {
8028 // Just move it to a different register
8029 regs[i].regmap_entry[hr]=r;
8030 // If it was dirty before, it's still dirty
8031 if((regs[i].wasdirty>>or)&1) dirty_reg(&current,r&63);
8032 }
8033 }
8034 else
8035 {
8036 // Unneeded
8037 if(r==0){
8038 regs[i].regmap_entry[hr]=0;
8039 }
8040 else
7c3a5182 8041 {
8042 assert(r<64);
57871462 8043 if((current.u>>r)&1) {
8044 regs[i].regmap_entry[hr]=-1;
8045 //regs[i].regmap[hr]=-1;
8046 current.regmap[hr]=-1;
8047 }else
8048 regs[i].regmap_entry[hr]=r;
8049 }
57871462 8050 }
8051 } else {
8052 // Branches expect CCREG to be allocated at the target
9f51b4b9 8053 if(regmap_pre[i][hr]==CCREG)
57871462 8054 regs[i].regmap_entry[hr]=CCREG;
8055 else
8056 regs[i].regmap_entry[hr]=-1;
8057 }
8058 }
8059 memcpy(regs[i].regmap,current.regmap,sizeof(current.regmap));
8060 }
27727b63 8061
cf95b4f0 8062 if(i>0&&(dops[i-1].itype==STORE||dops[i-1].itype==STORELR||(dops[i-1].itype==C2LS&&dops[i-1].opcode==0x3a))&&(u_int)imm[i-1]<0x800)
8063 current.waswritten|=1<<dops[i-1].rs1;
8064 current.waswritten&=~(1<<dops[i].rt1);
8065 current.waswritten&=~(1<<dops[i].rt2);
8066 if((dops[i].itype==STORE||dops[i].itype==STORELR||(dops[i].itype==C2LS&&dops[i].opcode==0x3a))&&(u_int)imm[i]>=0x800)
8067 current.waswritten&=~(1<<dops[i].rs1);
27727b63 8068
57871462 8069 /* Branch post-alloc */
8070 if(i>0)
8071 {
57871462 8072 current.wasdirty=current.dirty;
cf95b4f0 8073 switch(dops[i-1].itype) {
57871462 8074 case UJUMP:
8075 memcpy(&branch_regs[i-1],&current,sizeof(current));
8076 branch_regs[i-1].isconst=0;
8077 branch_regs[i-1].wasconst=0;
cf95b4f0 8078 branch_regs[i-1].u=branch_unneeded_reg[i-1]&~((1LL<<dops[i-1].rs1)|(1LL<<dops[i-1].rs2));
57871462 8079 alloc_cc(&branch_regs[i-1],i-1);
8080 dirty_reg(&branch_regs[i-1],CCREG);
cf95b4f0 8081 if(dops[i-1].rt1==31) { // JAL
57871462 8082 alloc_reg(&branch_regs[i-1],i-1,31);
8083 dirty_reg(&branch_regs[i-1],31);
57871462 8084 }
8085 memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
40fca85b 8086 memcpy(constmap[i],constmap[i-1],sizeof(constmap[i]));
57871462 8087 break;
8088 case RJUMP:
8089 memcpy(&branch_regs[i-1],&current,sizeof(current));
8090 branch_regs[i-1].isconst=0;
8091 branch_regs[i-1].wasconst=0;
cf95b4f0 8092 branch_regs[i-1].u=branch_unneeded_reg[i-1]&~((1LL<<dops[i-1].rs1)|(1LL<<dops[i-1].rs2));
57871462 8093 alloc_cc(&branch_regs[i-1],i-1);
8094 dirty_reg(&branch_regs[i-1],CCREG);
cf95b4f0 8095 alloc_reg(&branch_regs[i-1],i-1,dops[i-1].rs1);
8096 if(dops[i-1].rt1!=0) { // JALR
8097 alloc_reg(&branch_regs[i-1],i-1,dops[i-1].rt1);
8098 dirty_reg(&branch_regs[i-1],dops[i-1].rt1);
57871462 8099 }
8100 #ifdef USE_MINI_HT
cf95b4f0 8101 if(dops[i-1].rs1==31) { // JALR
57871462 8102 alloc_reg(&branch_regs[i-1],i-1,RHASH);
57871462 8103 alloc_reg(&branch_regs[i-1],i-1,RHTBL);
57871462 8104 }
8105 #endif
8106 memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
40fca85b 8107 memcpy(constmap[i],constmap[i-1],sizeof(constmap[i]));
57871462 8108 break;
8109 case CJUMP:
cf95b4f0 8110 if((dops[i-1].opcode&0x3E)==4) // BEQ/BNE
57871462 8111 {
8112 alloc_cc(&current,i-1);
8113 dirty_reg(&current,CCREG);
cf95b4f0 8114 if((dops[i-1].rs1&&(dops[i-1].rs1==dops[i].rt1||dops[i-1].rs1==dops[i].rt2))||
8115 (dops[i-1].rs2&&(dops[i-1].rs2==dops[i].rt1||dops[i-1].rs2==dops[i].rt2))) {
57871462 8116 // The delay slot overwrote one of our conditions
8117 // Delay slot goes after the test (in order)
cf95b4f0 8118 current.u=branch_unneeded_reg[i-1]&~((1LL<<dops[i].rs1)|(1LL<<dops[i].rs2));
57871462 8119 current.u|=1;
57871462 8120 delayslot_alloc(&current,i);
8121 current.isconst=0;
8122 }
8123 else
8124 {
cf95b4f0 8125 current.u=branch_unneeded_reg[i-1]&~((1LL<<dops[i-1].rs1)|(1LL<<dops[i-1].rs2));
57871462 8126 // Alloc the branch condition registers
cf95b4f0 8127 if(dops[i-1].rs1) alloc_reg(&current,i-1,dops[i-1].rs1);
8128 if(dops[i-1].rs2) alloc_reg(&current,i-1,dops[i-1].rs2);
57871462 8129 }
8130 memcpy(&branch_regs[i-1],&current,sizeof(current));
8131 branch_regs[i-1].isconst=0;
8132 branch_regs[i-1].wasconst=0;
8133 memcpy(&branch_regs[i-1].regmap_entry,&current.regmap,sizeof(current.regmap));
40fca85b 8134 memcpy(constmap[i],constmap[i-1],sizeof(constmap[i]));
57871462 8135 }
8136 else
cf95b4f0 8137 if((dops[i-1].opcode&0x3E)==6) // BLEZ/BGTZ
57871462 8138 {
8139 alloc_cc(&current,i-1);
8140 dirty_reg(&current,CCREG);
cf95b4f0 8141 if(dops[i-1].rs1==dops[i].rt1||dops[i-1].rs1==dops[i].rt2) {
57871462 8142 // The delay slot overwrote the branch condition
8143 // Delay slot goes after the test (in order)
cf95b4f0 8144 current.u=branch_unneeded_reg[i-1]&~((1LL<<dops[i].rs1)|(1LL<<dops[i].rs2));
57871462 8145 current.u|=1;
57871462 8146 delayslot_alloc(&current,i);
8147 current.isconst=0;
8148 }
8149 else
8150 {
cf95b4f0 8151 current.u=branch_unneeded_reg[i-1]&~(1LL<<dops[i-1].rs1);
57871462 8152 // Alloc the branch condition register
cf95b4f0 8153 alloc_reg(&current,i-1,dops[i-1].rs1);
57871462 8154 }
8155 memcpy(&branch_regs[i-1],&current,sizeof(current));
8156 branch_regs[i-1].isconst=0;
8157 branch_regs[i-1].wasconst=0;
8158 memcpy(&branch_regs[i-1].regmap_entry,&current.regmap,sizeof(current.regmap));
40fca85b 8159 memcpy(constmap[i],constmap[i-1],sizeof(constmap[i]));
57871462 8160 }
8161 else
8162 // Alloc the delay slot in case the branch is taken
cf95b4f0 8163 if((dops[i-1].opcode&0x3E)==0x14) // BEQL/BNEL
57871462 8164 {
8165 memcpy(&branch_regs[i-1],&current,sizeof(current));
cf95b4f0 8166 branch_regs[i-1].u=(branch_unneeded_reg[i-1]&~((1LL<<dops[i].rs1)|(1LL<<dops[i].rs2)|(1LL<<dops[i].rt1)|(1LL<<dops[i].rt2)))|1;
57871462 8167 alloc_cc(&branch_regs[i-1],i);
8168 dirty_reg(&branch_regs[i-1],CCREG);
8169 delayslot_alloc(&branch_regs[i-1],i);
8170 branch_regs[i-1].isconst=0;
8171 alloc_reg(&current,i,CCREG); // Not taken path
8172 dirty_reg(&current,CCREG);
8173 memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
8174 }
8175 else
cf95b4f0 8176 if((dops[i-1].opcode&0x3E)==0x16) // BLEZL/BGTZL
57871462 8177 {
8178 memcpy(&branch_regs[i-1],&current,sizeof(current));
cf95b4f0 8179 branch_regs[i-1].u=(branch_unneeded_reg[i-1]&~((1LL<<dops[i].rs1)|(1LL<<dops[i].rs2)|(1LL<<dops[i].rt1)|(1LL<<dops[i].rt2)))|1;
57871462 8180 alloc_cc(&branch_regs[i-1],i);
8181 dirty_reg(&branch_regs[i-1],CCREG);
8182 delayslot_alloc(&branch_regs[i-1],i);
8183 branch_regs[i-1].isconst=0;
8184 alloc_reg(&current,i,CCREG); // Not taken path
8185 dirty_reg(&current,CCREG);
8186 memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
8187 }
8188 break;
8189 case SJUMP:
cf95b4f0 8190 //if((dops[i-1].opcode2&0x1E)==0) // BLTZ/BGEZ
8191 if((dops[i-1].opcode2&0x0E)==0) // BLTZ/BGEZ
57871462 8192 {
8193 alloc_cc(&current,i-1);
8194 dirty_reg(&current,CCREG);
cf95b4f0 8195 if(dops[i-1].rs1==dops[i].rt1||dops[i-1].rs1==dops[i].rt2) {
57871462 8196 // The delay slot overwrote the branch condition
8197 // Delay slot goes after the test (in order)
cf95b4f0 8198 current.u=branch_unneeded_reg[i-1]&~((1LL<<dops[i].rs1)|(1LL<<dops[i].rs2));
57871462 8199 current.u|=1;
57871462 8200 delayslot_alloc(&current,i);
8201 current.isconst=0;
8202 }
8203 else
8204 {
cf95b4f0 8205 current.u=branch_unneeded_reg[i-1]&~(1LL<<dops[i-1].rs1);
57871462 8206 // Alloc the branch condition register
cf95b4f0 8207 alloc_reg(&current,i-1,dops[i-1].rs1);
57871462 8208 }
8209 memcpy(&branch_regs[i-1],&current,sizeof(current));
8210 branch_regs[i-1].isconst=0;
8211 branch_regs[i-1].wasconst=0;
8212 memcpy(&branch_regs[i-1].regmap_entry,&current.regmap,sizeof(current.regmap));
40fca85b 8213 memcpy(constmap[i],constmap[i-1],sizeof(constmap[i]));
57871462 8214 }
8215 else
8216 // Alloc the delay slot in case the branch is taken
cf95b4f0 8217 if((dops[i-1].opcode2&0x1E)==2) // BLTZL/BGEZL
57871462 8218 {
8219 memcpy(&branch_regs[i-1],&current,sizeof(current));
cf95b4f0 8220 branch_regs[i-1].u=(branch_unneeded_reg[i-1]&~((1LL<<dops[i].rs1)|(1LL<<dops[i].rs2)|(1LL<<dops[i].rt1)|(1LL<<dops[i].rt2)))|1;
57871462 8221 alloc_cc(&branch_regs[i-1],i);
8222 dirty_reg(&branch_regs[i-1],CCREG);
8223 delayslot_alloc(&branch_regs[i-1],i);
8224 branch_regs[i-1].isconst=0;
8225 alloc_reg(&current,i,CCREG); // Not taken path
8226 dirty_reg(&current,CCREG);
8227 memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
8228 }
8229 // FIXME: BLTZAL/BGEZAL
cf95b4f0 8230 if(dops[i-1].opcode2&0x10) { // BxxZAL
57871462 8231 alloc_reg(&branch_regs[i-1],i-1,31);
8232 dirty_reg(&branch_regs[i-1],31);
57871462 8233 }
8234 break;
57871462 8235 }
8236
fe807a8a 8237 if (dops[i-1].is_ujump)
57871462 8238 {
cf95b4f0 8239 if(dops[i-1].rt1==31) // JAL/JALR
57871462 8240 {
8241 // Subroutine call will return here, don't alloc any registers
57871462 8242 current.dirty=0;
8243 clear_all_regs(current.regmap);
8244 alloc_reg(&current,i,CCREG);
8245 dirty_reg(&current,CCREG);
8246 }
8247 else if(i+1<slen)
8248 {
8249 // Internal branch will jump here, match registers to caller
57871462 8250 current.dirty=0;
8251 clear_all_regs(current.regmap);
8252 alloc_reg(&current,i,CCREG);
8253 dirty_reg(&current,CCREG);
8254 for(j=i-1;j>=0;j--)
8255 {
8256 if(ba[j]==start+i*4+4) {
8257 memcpy(current.regmap,branch_regs[j].regmap,sizeof(current.regmap));
57871462 8258 current.dirty=branch_regs[j].dirty;
8259 break;
8260 }
8261 }
8262 while(j>=0) {
8263 if(ba[j]==start+i*4+4) {
8264 for(hr=0;hr<HOST_REGS;hr++) {
8265 if(current.regmap[hr]!=branch_regs[j].regmap[hr]) {
8266 current.regmap[hr]=-1;
8267 }
57871462 8268 current.dirty&=branch_regs[j].dirty;
8269 }
8270 }
8271 j--;
8272 }
8273 }
8274 }
8275 }
8276
8277 // Count cycles in between branches
2330734f 8278 ccadj[i] = CLOCK_ADJUST(cc);
fe807a8a 8279 if (i > 0 && (dops[i-1].is_jump || dops[i].itype == SYSCALL || dops[i].itype == HLECALL))
57871462 8280 {
8281 cc=0;
8282 }
71e490c5 8283#if !defined(DRC_DBG)
cf95b4f0 8284 else if(dops[i].itype==C2OP&&gte_cycletab[source[i]&0x3f]>2)
054175e9 8285 {
81dbbf4c 8286 // this should really be removed since the real stalls have been implemented,
8287 // but doing so causes sizeable perf regression against the older version
8288 u_int gtec = gte_cycletab[source[i] & 0x3f];
32631e6a 8289 cc += HACK_ENABLED(NDHACK_NO_STALLS) ? gtec/2 : 2;
fb407447 8290 }
cf95b4f0 8291 else if(i>1&&dops[i].itype==STORE&&dops[i-1].itype==STORE&&dops[i-2].itype==STORE&&!dops[i].bt)
5fdcbb5a 8292 {
8293 cc+=4;
8294 }
cf95b4f0 8295 else if(dops[i].itype==C2LS)
fb407447 8296 {
81dbbf4c 8297 // same as with C2OP
32631e6a 8298 cc += HACK_ENABLED(NDHACK_NO_STALLS) ? 4 : 2;
fb407447 8299 }
8300#endif
57871462 8301 else
8302 {
8303 cc++;
8304 }
8305
cf95b4f0 8306 if(!dops[i].is_ds) {
57871462 8307 regs[i].dirty=current.dirty;
8308 regs[i].isconst=current.isconst;
40fca85b 8309 memcpy(constmap[i],current_constmap,sizeof(constmap[i]));
57871462 8310 }
8311 for(hr=0;hr<HOST_REGS;hr++) {
8312 if(hr!=EXCLUDE_REG&&regs[i].regmap[hr]>=0) {
8313 if(regmap_pre[i][hr]!=regs[i].regmap[hr]) {
8314 regs[i].wasconst&=~(1<<hr);
8315 }
8316 }
8317 }
8318 if(current.regmap[HOST_BTREG]==BTREG) current.regmap[HOST_BTREG]=-1;
27727b63 8319 regs[i].waswritten=current.waswritten;
57871462 8320 }
9f51b4b9 8321
57871462 8322 /* Pass 4 - Cull unused host registers */
9f51b4b9 8323
57871462 8324 uint64_t nr=0;
9f51b4b9 8325
57871462 8326 for (i=slen-1;i>=0;i--)
8327 {
8328 int hr;
fe807a8a 8329 if(dops[i].is_jump)
57871462 8330 {
8331 if(ba[i]<start || ba[i]>=(start+slen*4))
8332 {
8333 // Branch out of this block, don't need anything
8334 nr=0;
8335 }
8336 else
8337 {
8338 // Internal branch
8339 // Need whatever matches the target
8340 nr=0;
8341 int t=(ba[i]-start)>>2;
8342 for(hr=0;hr<HOST_REGS;hr++)
8343 {
8344 if(regs[i].regmap_entry[hr]>=0) {
8345 if(regs[i].regmap_entry[hr]==regs[t].regmap_entry[hr]) nr|=1<<hr;
8346 }
8347 }
8348 }
8349 // Conditional branch may need registers for following instructions
fe807a8a 8350 if (!dops[i].is_ujump)
57871462 8351 {
8352 if(i<slen-2) {
8353 nr|=needed_reg[i+2];
8354 for(hr=0;hr<HOST_REGS;hr++)
8355 {
8356 if(regmap_pre[i+2][hr]>=0&&get_reg(regs[i+2].regmap_entry,regmap_pre[i+2][hr])<0) nr&=~(1<<hr);
8357 //if((regmap_entry[i+2][hr])>=0) if(!((nr>>hr)&1)) printf("%x-bogus(%d=%d)\n",start+i*4,hr,regmap_entry[i+2][hr]);
8358 }
8359 }
8360 }
8361 // Don't need stuff which is overwritten
f5955059 8362 //if(regs[i].regmap[hr]!=regmap_pre[i][hr]) nr&=~(1<<hr);
8363 //if(regs[i].regmap[hr]<0) nr&=~(1<<hr);
57871462 8364 // Merge in delay slot
8365 for(hr=0;hr<HOST_REGS;hr++)
8366 {
fe807a8a 8367 if(dops[i+1].rt1&&dops[i+1].rt1==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
8368 if(dops[i+1].rt2&&dops[i+1].rt2==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
cf95b4f0 8369 if(dops[i+1].rs1==regmap_pre[i][hr]) nr|=1<<hr;
8370 if(dops[i+1].rs2==regmap_pre[i][hr]) nr|=1<<hr;
8371 if(dops[i+1].rs1==regs[i].regmap_entry[hr]) nr|=1<<hr;
8372 if(dops[i+1].rs2==regs[i].regmap_entry[hr]) nr|=1<<hr;
37387d8b 8373 if(ram_offset && (dops[i+1].is_load || dops[i+1].is_store)) {
8374 if(regmap_pre[i][hr]==ROREG) nr|=1<<hr;
8375 if(regs[i].regmap_entry[hr]==ROREG) nr|=1<<hr;
8376 }
8377 if(dops[i+1].is_store) {
57871462 8378 if(regmap_pre[i][hr]==INVCP) nr|=1<<hr;
8379 if(regs[i].regmap_entry[hr]==INVCP) nr|=1<<hr;
8380 }
8381 }
8382 }
cf95b4f0 8383 else if(dops[i].itype==SYSCALL||dops[i].itype==HLECALL||dops[i].itype==INTCALL)
57871462 8384 {
8385 // SYSCALL instruction (software interrupt)
8386 nr=0;
8387 }
cf95b4f0 8388 else if(dops[i].itype==COP0 && (source[i]&0x3f)==0x18)
57871462 8389 {
8390 // ERET instruction (return from interrupt)
8391 nr=0;
8392 }
8393 else // Non-branch
8394 {
8395 if(i<slen-1) {
8396 for(hr=0;hr<HOST_REGS;hr++) {
8397 if(regmap_pre[i+1][hr]>=0&&get_reg(regs[i+1].regmap_entry,regmap_pre[i+1][hr])<0) nr&=~(1<<hr);
8398 if(regs[i].regmap[hr]!=regmap_pre[i+1][hr]) nr&=~(1<<hr);
8399 if(regs[i].regmap[hr]!=regmap_pre[i][hr]) nr&=~(1<<hr);
8400 if(regs[i].regmap[hr]<0) nr&=~(1<<hr);
8401 }
8402 }
8403 }
8404 for(hr=0;hr<HOST_REGS;hr++)
8405 {
8406 // Overwritten registers are not needed
cf95b4f0 8407 if(dops[i].rt1&&dops[i].rt1==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
8408 if(dops[i].rt2&&dops[i].rt2==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
57871462 8409 if(FTEMP==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
8410 // Source registers are needed
cf95b4f0 8411 if(dops[i].rs1==regmap_pre[i][hr]) nr|=1<<hr;
8412 if(dops[i].rs2==regmap_pre[i][hr]) nr|=1<<hr;
8413 if(dops[i].rs1==regs[i].regmap_entry[hr]) nr|=1<<hr;
8414 if(dops[i].rs2==regs[i].regmap_entry[hr]) nr|=1<<hr;
37387d8b 8415 if(ram_offset && (dops[i].is_load || dops[i].is_store)) {
8416 if(regmap_pre[i][hr]==ROREG) nr|=1<<hr;
8417 if(regs[i].regmap_entry[hr]==ROREG) nr|=1<<hr;
8418 }
8419 if(dops[i].is_store) {
57871462 8420 if(regmap_pre[i][hr]==INVCP) nr|=1<<hr;
8421 if(regs[i].regmap_entry[hr]==INVCP) nr|=1<<hr;
8422 }
8423 // Don't store a register immediately after writing it,
8424 // may prevent dual-issue.
8425 // But do so if this is a branch target, otherwise we
8426 // might have to load the register before the branch.
cf95b4f0 8427 if(i>0&&!dops[i].bt&&((regs[i].wasdirty>>hr)&1)) {
7c3a5182 8428 if((regmap_pre[i][hr]>0&&!((unneeded_reg[i]>>regmap_pre[i][hr])&1))) {
cf95b4f0 8429 if(dops[i-1].rt1==(regmap_pre[i][hr]&63)) nr|=1<<hr;
8430 if(dops[i-1].rt2==(regmap_pre[i][hr]&63)) nr|=1<<hr;
57871462 8431 }
7c3a5182 8432 if((regs[i].regmap_entry[hr]>0&&!((unneeded_reg[i]>>regs[i].regmap_entry[hr])&1))) {
cf95b4f0 8433 if(dops[i-1].rt1==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
8434 if(dops[i-1].rt2==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
57871462 8435 }
8436 }
8437 }
8438 // Cycle count is needed at branches. Assume it is needed at the target too.
cf95b4f0 8439 if(i==0||dops[i].bt||dops[i].itype==CJUMP||dops[i].itype==SPAN) {
57871462 8440 if(regmap_pre[i][HOST_CCREG]==CCREG) nr|=1<<HOST_CCREG;
8441 if(regs[i].regmap_entry[HOST_CCREG]==CCREG) nr|=1<<HOST_CCREG;
8442 }
8443 // Save it
8444 needed_reg[i]=nr;
9f51b4b9 8445
57871462 8446 // Deallocate unneeded registers
8447 for(hr=0;hr<HOST_REGS;hr++)
8448 {
8449 if(!((nr>>hr)&1)) {
8450 if(regs[i].regmap_entry[hr]!=CCREG) regs[i].regmap_entry[hr]=-1;
fe807a8a 8451 if(dops[i].is_jump)
57871462 8452 {
37387d8b 8453 int map1 = 0, map2 = 0, temp = 0; // or -1 ??
8454 if (dops[i+1].is_load || dops[i+1].is_store)
8455 map1 = ROREG;
8456 if (dops[i+1].is_store)
8457 map2 = INVCP;
8458 if(dops[i+1].itype==LOADLR || dops[i+1].itype==STORELR || dops[i+1].itype==C2LS)
8459 temp = FTEMP;
cf95b4f0 8460 if((regs[i].regmap[hr]&63)!=dops[i].rs1 && (regs[i].regmap[hr]&63)!=dops[i].rs2 &&
8461 (regs[i].regmap[hr]&63)!=dops[i].rt1 && (regs[i].regmap[hr]&63)!=dops[i].rt2 &&
8462 (regs[i].regmap[hr]&63)!=dops[i+1].rt1 && (regs[i].regmap[hr]&63)!=dops[i+1].rt2 &&
8463 regs[i].regmap[hr]!=dops[i+1].rs1 && regs[i].regmap[hr]!=dops[i+1].rs2 &&
57871462 8464 (regs[i].regmap[hr]&63)!=temp && regs[i].regmap[hr]!=PTEMP &&
8465 regs[i].regmap[hr]!=RHASH && regs[i].regmap[hr]!=RHTBL &&
8466 regs[i].regmap[hr]!=RTEMP && regs[i].regmap[hr]!=CCREG &&
37387d8b 8467 regs[i].regmap[hr]!=map1 && regs[i].regmap[hr]!=map2)
57871462 8468 {
8469 regs[i].regmap[hr]=-1;
8470 regs[i].isconst&=~(1<<hr);
cf95b4f0 8471 if((branch_regs[i].regmap[hr]&63)!=dops[i].rs1 && (branch_regs[i].regmap[hr]&63)!=dops[i].rs2 &&
8472 (branch_regs[i].regmap[hr]&63)!=dops[i].rt1 && (branch_regs[i].regmap[hr]&63)!=dops[i].rt2 &&
8473 (branch_regs[i].regmap[hr]&63)!=dops[i+1].rt1 && (branch_regs[i].regmap[hr]&63)!=dops[i+1].rt2 &&
8474 branch_regs[i].regmap[hr]!=dops[i+1].rs1 && branch_regs[i].regmap[hr]!=dops[i+1].rs2 &&
57871462 8475 (branch_regs[i].regmap[hr]&63)!=temp && branch_regs[i].regmap[hr]!=PTEMP &&
8476 branch_regs[i].regmap[hr]!=RHASH && branch_regs[i].regmap[hr]!=RHTBL &&
8477 branch_regs[i].regmap[hr]!=RTEMP && branch_regs[i].regmap[hr]!=CCREG &&
37387d8b 8478 branch_regs[i].regmap[hr]!=map1 && branch_regs[i].regmap[hr]!=map2)
57871462 8479 {
8480 branch_regs[i].regmap[hr]=-1;
8481 branch_regs[i].regmap_entry[hr]=-1;
fe807a8a 8482 if (!dops[i].is_ujump)
57871462 8483 {
fe807a8a 8484 if (i < slen-2) {
57871462 8485 regmap_pre[i+2][hr]=-1;
79c75f1b 8486 regs[i+2].wasconst&=~(1<<hr);
57871462 8487 }
8488 }
8489 }
8490 }
8491 }
8492 else
8493 {
8494 // Non-branch
8495 if(i>0)
8496 {
37387d8b 8497 int map1 = -1, map2 = -1, temp=-1;
8498 if (dops[i].is_load || dops[i].is_store)
8499 map1 = ROREG;
8500 if (dops[i].is_store)
8501 map2 = INVCP;
8502 if (dops[i].itype==LOADLR || dops[i].itype==STORELR || dops[i].itype==C2LS)
8503 temp = FTEMP;
cf95b4f0 8504 if((regs[i].regmap[hr]&63)!=dops[i].rt1 && (regs[i].regmap[hr]&63)!=dops[i].rt2 &&
8505 regs[i].regmap[hr]!=dops[i].rs1 && regs[i].regmap[hr]!=dops[i].rs2 &&
37387d8b 8506 (regs[i].regmap[hr]&63)!=temp && regs[i].regmap[hr]!=map1 && regs[i].regmap[hr]!=map2 &&
4b1c7cd1 8507 //(dops[i].itype!=SPAN||regs[i].regmap[hr]!=CCREG)
8508 regs[i].regmap[hr] != CCREG)
57871462 8509 {
cf95b4f0 8510 if(i<slen-1&&!dops[i].is_ds) {
ad49de89 8511 assert(regs[i].regmap[hr]<64);
afec9d44 8512 if(regmap_pre[i+1][hr]!=-1 || regs[i].regmap[hr]>0)
57871462 8513 if(regmap_pre[i+1][hr]!=regs[i].regmap[hr])
57871462 8514 {
c43b5311 8515 SysPrintf("fail: %x (%d %d!=%d)\n",start+i*4,hr,regmap_pre[i+1][hr],regs[i].regmap[hr]);
57871462 8516 assert(regmap_pre[i+1][hr]==regs[i].regmap[hr]);
8517 }
8518 regmap_pre[i+1][hr]=-1;
8519 if(regs[i+1].regmap_entry[hr]==CCREG) regs[i+1].regmap_entry[hr]=-1;
79c75f1b 8520 regs[i+1].wasconst&=~(1<<hr);
57871462 8521 }
8522 regs[i].regmap[hr]=-1;
8523 regs[i].isconst&=~(1<<hr);
8524 }
8525 }
8526 }
3968e69e 8527 } // if needed
8528 } // for hr
57871462 8529 }
9f51b4b9 8530
57871462 8531 /* Pass 5 - Pre-allocate registers */
9f51b4b9 8532
57871462 8533 // If a register is allocated during a loop, try to allocate it for the
8534 // entire loop, if possible. This avoids loading/storing registers
8535 // inside of the loop.
9f51b4b9 8536
57871462 8537 signed char f_regmap[HOST_REGS];
8538 clear_all_regs(f_regmap);
8539 for(i=0;i<slen-1;i++)
8540 {
cf95b4f0 8541 if(dops[i].itype==UJUMP||dops[i].itype==CJUMP||dops[i].itype==SJUMP)
57871462 8542 {
9f51b4b9 8543 if(ba[i]>=start && ba[i]<(start+i*4))
cf95b4f0 8544 if(dops[i+1].itype==NOP||dops[i+1].itype==MOV||dops[i+1].itype==ALU
8545 ||dops[i+1].itype==SHIFTIMM||dops[i+1].itype==IMM16||dops[i+1].itype==LOAD
8546 ||dops[i+1].itype==STORE||dops[i+1].itype==STORELR||dops[i+1].itype==C1LS
8547 ||dops[i+1].itype==SHIFT||dops[i+1].itype==COP1
8548 ||dops[i+1].itype==COP2||dops[i+1].itype==C2LS||dops[i+1].itype==C2OP)
57871462 8549 {
8550 int t=(ba[i]-start)>>2;
fe807a8a 8551 if(t > 0 && !dops[t-1].is_jump) // loop_preload can't handle jumps into delay slots
cf95b4f0 8552 if(t<2||(dops[t-2].itype!=UJUMP&&dops[t-2].itype!=RJUMP)||dops[t-2].rt1!=31) // call/ret assumes no registers allocated
57871462 8553 for(hr=0;hr<HOST_REGS;hr++)
8554 {
7c3a5182 8555 if(regs[i].regmap[hr]>=0) {
b372a952 8556 if(f_regmap[hr]!=regs[i].regmap[hr]) {
8557 // dealloc old register
8558 int n;
8559 for(n=0;n<HOST_REGS;n++)
8560 {
8561 if(f_regmap[n]==regs[i].regmap[hr]) {f_regmap[n]=-1;}
8562 }
8563 // and alloc new one
8564 f_regmap[hr]=regs[i].regmap[hr];
8565 }
8566 }
7c3a5182 8567 if(branch_regs[i].regmap[hr]>=0) {
b372a952 8568 if(f_regmap[hr]!=branch_regs[i].regmap[hr]) {
8569 // dealloc old register
8570 int n;
8571 for(n=0;n<HOST_REGS;n++)
8572 {
8573 if(f_regmap[n]==branch_regs[i].regmap[hr]) {f_regmap[n]=-1;}
8574 }
8575 // and alloc new one
8576 f_regmap[hr]=branch_regs[i].regmap[hr];
8577 }
8578 }
cf95b4f0 8579 if(dops[i].ooo) {
9f51b4b9 8580 if(count_free_regs(regs[i].regmap)<=minimum_free_regs[i+1])
e1190b87 8581 f_regmap[hr]=branch_regs[i].regmap[hr];
8582 }else{
9f51b4b9 8583 if(count_free_regs(branch_regs[i].regmap)<=minimum_free_regs[i+1])
57871462 8584 f_regmap[hr]=branch_regs[i].regmap[hr];
8585 }
8586 // Avoid dirty->clean transition
e1190b87 8587 #ifdef DESTRUCTIVE_WRITEBACK
57871462 8588 if(t>0) if(get_reg(regmap_pre[t],f_regmap[hr])>=0) if((regs[t].wasdirty>>get_reg(regmap_pre[t],f_regmap[hr]))&1) f_regmap[hr]=-1;
e1190b87 8589 #endif
8590 // This check is only strictly required in the DESTRUCTIVE_WRITEBACK
8591 // case above, however it's always a good idea. We can't hoist the
8592 // load if the register was already allocated, so there's no point
8593 // wasting time analyzing most of these cases. It only "succeeds"
8594 // when the mapping was different and the load can be replaced with
8595 // a mov, which is of negligible benefit. So such cases are
8596 // skipped below.
57871462 8597 if(f_regmap[hr]>0) {
198df76f 8598 if(regs[t].regmap[hr]==f_regmap[hr]||(regs[t].regmap_entry[hr]<0&&get_reg(regmap_pre[t],f_regmap[hr])<0)) {
57871462 8599 int r=f_regmap[hr];
8600 for(j=t;j<=i;j++)
8601 {
8602 //printf("Test %x -> %x, %x %d/%d\n",start+i*4,ba[i],start+j*4,hr,r);
8603 if(r<34&&((unneeded_reg[j]>>r)&1)) break;
00fa9369 8604 assert(r < 64);
57871462 8605 if(regs[j].regmap[hr]==f_regmap[hr]&&(f_regmap[hr]&63)<TEMPREG) {
8606 //printf("Hit %x -> %x, %x %d/%d\n",start+i*4,ba[i],start+j*4,hr,r);
8607 int k;
8608 if(regs[i].regmap[hr]==-1&&branch_regs[i].regmap[hr]==-1) {
8609 if(get_reg(regs[i+2].regmap,f_regmap[hr])>=0) break;
8610 if(r>63) {
8611 if(get_reg(regs[i].regmap,r&63)<0) break;
8612 if(get_reg(branch_regs[i].regmap,r&63)<0) break;
8613 }
8614 k=i;
8615 while(k>1&&regs[k-1].regmap[hr]==-1) {
e1190b87 8616 if(count_free_regs(regs[k-1].regmap)<=minimum_free_regs[k-1]) {
8617 //printf("no free regs for store %x\n",start+(k-1)*4);
8618 break;
57871462 8619 }
57871462 8620 if(get_reg(regs[k-1].regmap,f_regmap[hr])>=0) {
8621 //printf("no-match due to different register\n");
8622 break;
8623 }
fe807a8a 8624 if (dops[k-2].is_jump) {
57871462 8625 //printf("no-match due to branch\n");
8626 break;
8627 }
8628 // call/ret fast path assumes no registers allocated
cf95b4f0 8629 if(k>2&&(dops[k-3].itype==UJUMP||dops[k-3].itype==RJUMP)&&dops[k-3].rt1==31) {
57871462 8630 break;
8631 }
ad49de89 8632 assert(r < 64);
57871462 8633 k--;
8634 }
57871462 8635 if(regs[k-1].regmap[hr]==f_regmap[hr]&&regmap_pre[k][hr]==f_regmap[hr]) {
8636 //printf("Extend r%d, %x ->\n",hr,start+k*4);
8637 while(k<i) {
8638 regs[k].regmap_entry[hr]=f_regmap[hr];
8639 regs[k].regmap[hr]=f_regmap[hr];
8640 regmap_pre[k+1][hr]=f_regmap[hr];
8641 regs[k].wasdirty&=~(1<<hr);
8642 regs[k].dirty&=~(1<<hr);
8643 regs[k].wasdirty|=(1<<hr)&regs[k-1].dirty;
8644 regs[k].dirty|=(1<<hr)&regs[k].wasdirty;
8645 regs[k].wasconst&=~(1<<hr);
8646 regs[k].isconst&=~(1<<hr);
8647 k++;
8648 }
8649 }
8650 else {
8651 //printf("Fail Extend r%d, %x ->\n",hr,start+k*4);
8652 break;
8653 }
8654 assert(regs[i-1].regmap[hr]==f_regmap[hr]);
8655 if(regs[i-1].regmap[hr]==f_regmap[hr]&&regmap_pre[i][hr]==f_regmap[hr]) {
8656 //printf("OK fill %x (r%d)\n",start+i*4,hr);
8657 regs[i].regmap_entry[hr]=f_regmap[hr];
8658 regs[i].regmap[hr]=f_regmap[hr];
8659 regs[i].wasdirty&=~(1<<hr);
8660 regs[i].dirty&=~(1<<hr);
8661 regs[i].wasdirty|=(1<<hr)&regs[i-1].dirty;
8662 regs[i].dirty|=(1<<hr)&regs[i-1].dirty;
8663 regs[i].wasconst&=~(1<<hr);
8664 regs[i].isconst&=~(1<<hr);
8665 branch_regs[i].regmap_entry[hr]=f_regmap[hr];
8666 branch_regs[i].wasdirty&=~(1<<hr);
8667 branch_regs[i].wasdirty|=(1<<hr)&regs[i].dirty;
8668 branch_regs[i].regmap[hr]=f_regmap[hr];
8669 branch_regs[i].dirty&=~(1<<hr);
8670 branch_regs[i].dirty|=(1<<hr)&regs[i].dirty;
8671 branch_regs[i].wasconst&=~(1<<hr);
8672 branch_regs[i].isconst&=~(1<<hr);
fe807a8a 8673 if (!dops[i].is_ujump) {
57871462 8674 regmap_pre[i+2][hr]=f_regmap[hr];
8675 regs[i+2].wasdirty&=~(1<<hr);
8676 regs[i+2].wasdirty|=(1<<hr)&regs[i].dirty;
57871462 8677 }
8678 }
8679 }
8680 for(k=t;k<j;k++) {
e1190b87 8681 // Alloc register clean at beginning of loop,
8682 // but may dirty it in pass 6
57871462 8683 regs[k].regmap_entry[hr]=f_regmap[hr];
8684 regs[k].regmap[hr]=f_regmap[hr];
57871462 8685 regs[k].dirty&=~(1<<hr);
8686 regs[k].wasconst&=~(1<<hr);
8687 regs[k].isconst&=~(1<<hr);
fe807a8a 8688 if (dops[k].is_jump) {
e1190b87 8689 branch_regs[k].regmap_entry[hr]=f_regmap[hr];
8690 branch_regs[k].regmap[hr]=f_regmap[hr];
8691 branch_regs[k].dirty&=~(1<<hr);
8692 branch_regs[k].wasconst&=~(1<<hr);
8693 branch_regs[k].isconst&=~(1<<hr);
fe807a8a 8694 if (!dops[k].is_ujump) {
e1190b87 8695 regmap_pre[k+2][hr]=f_regmap[hr];
8696 regs[k+2].wasdirty&=~(1<<hr);
e1190b87 8697 }
8698 }
8699 else
8700 {
8701 regmap_pre[k+1][hr]=f_regmap[hr];
8702 regs[k+1].wasdirty&=~(1<<hr);
8703 }
57871462 8704 }
8705 if(regs[j].regmap[hr]==f_regmap[hr])
8706 regs[j].regmap_entry[hr]=f_regmap[hr];
8707 break;
8708 }
8709 if(j==i) break;
8710 if(regs[j].regmap[hr]>=0)
8711 break;
8712 if(get_reg(regs[j].regmap,f_regmap[hr])>=0) {
8713 //printf("no-match due to different register\n");
8714 break;
8715 }
fe807a8a 8716 if (dops[j].is_ujump)
e1190b87 8717 {
8718 // Stop on unconditional branch
8719 break;
8720 }
cf95b4f0 8721 if(dops[j].itype==CJUMP||dops[j].itype==SJUMP)
e1190b87 8722 {
cf95b4f0 8723 if(dops[j].ooo) {
9f51b4b9 8724 if(count_free_regs(regs[j].regmap)<=minimum_free_regs[j+1])
e1190b87 8725 break;
8726 }else{
9f51b4b9 8727 if(count_free_regs(branch_regs[j].regmap)<=minimum_free_regs[j+1])
e1190b87 8728 break;
8729 }
8730 if(get_reg(branch_regs[j].regmap,f_regmap[hr])>=0) {
8731 //printf("no-match due to different register (branch)\n");
57871462 8732 break;
8733 }
8734 }
e1190b87 8735 if(count_free_regs(regs[j].regmap)<=minimum_free_regs[j]) {
8736 //printf("No free regs for store %x\n",start+j*4);
8737 break;
8738 }
ad49de89 8739 assert(f_regmap[hr]<64);
57871462 8740 }
8741 }
8742 }
8743 }
8744 }
8745 }else{
198df76f 8746 // Non branch or undetermined branch target
57871462 8747 for(hr=0;hr<HOST_REGS;hr++)
8748 {
8749 if(hr!=EXCLUDE_REG) {
7c3a5182 8750 if(regs[i].regmap[hr]>=0) {
b372a952 8751 if(f_regmap[hr]!=regs[i].regmap[hr]) {
8752 // dealloc old register
8753 int n;
8754 for(n=0;n<HOST_REGS;n++)
8755 {
8756 if(f_regmap[n]==regs[i].regmap[hr]) {f_regmap[n]=-1;}
8757 }
8758 // and alloc new one
8759 f_regmap[hr]=regs[i].regmap[hr];
8760 }
8761 }
57871462 8762 }
8763 }
8764 // Try to restore cycle count at branch targets
cf95b4f0 8765 if(dops[i].bt) {
57871462 8766 for(j=i;j<slen-1;j++) {
8767 if(regs[j].regmap[HOST_CCREG]!=-1) break;
e1190b87 8768 if(count_free_regs(regs[j].regmap)<=minimum_free_regs[j]) {
8769 //printf("no free regs for store %x\n",start+j*4);
8770 break;
57871462 8771 }
57871462 8772 }
8773 if(regs[j].regmap[HOST_CCREG]==CCREG) {
8774 int k=i;
8775 //printf("Extend CC, %x -> %x\n",start+k*4,start+j*4);
8776 while(k<j) {
8777 regs[k].regmap_entry[HOST_CCREG]=CCREG;
8778 regs[k].regmap[HOST_CCREG]=CCREG;
8779 regmap_pre[k+1][HOST_CCREG]=CCREG;
8780 regs[k+1].wasdirty|=1<<HOST_CCREG;
8781 regs[k].dirty|=1<<HOST_CCREG;
8782 regs[k].wasconst&=~(1<<HOST_CCREG);
8783 regs[k].isconst&=~(1<<HOST_CCREG);
8784 k++;
8785 }
9f51b4b9 8786 regs[j].regmap_entry[HOST_CCREG]=CCREG;
57871462 8787 }
8788 // Work backwards from the branch target
8789 if(j>i&&f_regmap[HOST_CCREG]==CCREG)
8790 {
8791 //printf("Extend backwards\n");
8792 int k;
8793 k=i;
8794 while(regs[k-1].regmap[HOST_CCREG]==-1) {
e1190b87 8795 if(count_free_regs(regs[k-1].regmap)<=minimum_free_regs[k-1]) {
8796 //printf("no free regs for store %x\n",start+(k-1)*4);
8797 break;
57871462 8798 }
57871462 8799 k--;
8800 }
8801 if(regs[k-1].regmap[HOST_CCREG]==CCREG) {
8802 //printf("Extend CC, %x ->\n",start+k*4);
8803 while(k<=i) {
8804 regs[k].regmap_entry[HOST_CCREG]=CCREG;
8805 regs[k].regmap[HOST_CCREG]=CCREG;
8806 regmap_pre[k+1][HOST_CCREG]=CCREG;
8807 regs[k+1].wasdirty|=1<<HOST_CCREG;
8808 regs[k].dirty|=1<<HOST_CCREG;
8809 regs[k].wasconst&=~(1<<HOST_CCREG);
8810 regs[k].isconst&=~(1<<HOST_CCREG);
8811 k++;
8812 }
8813 }
8814 else {
8815 //printf("Fail Extend CC, %x ->\n",start+k*4);
8816 }
8817 }
8818 }
cf95b4f0 8819 if(dops[i].itype!=STORE&&dops[i].itype!=STORELR&&dops[i].itype!=C1LS&&dops[i].itype!=SHIFT&&
8820 dops[i].itype!=NOP&&dops[i].itype!=MOV&&dops[i].itype!=ALU&&dops[i].itype!=SHIFTIMM&&
8821 dops[i].itype!=IMM16&&dops[i].itype!=LOAD&&dops[i].itype!=COP1)
57871462 8822 {
8823 memcpy(f_regmap,regs[i].regmap,sizeof(f_regmap));
8824 }
8825 }
8826 }
9f51b4b9 8827
57871462 8828 // This allocates registers (if possible) one instruction prior
8829 // to use, which can avoid a load-use penalty on certain CPUs.
8830 for(i=0;i<slen-1;i++)
8831 {
fe807a8a 8832 if (!i || !dops[i-1].is_jump)
57871462 8833 {
cf95b4f0 8834 if(!dops[i+1].bt)
57871462 8835 {
cf95b4f0 8836 if(dops[i].itype==ALU||dops[i].itype==MOV||dops[i].itype==LOAD||dops[i].itype==SHIFTIMM||dops[i].itype==IMM16
8837 ||((dops[i].itype==COP1||dops[i].itype==COP2)&&dops[i].opcode2<3))
57871462 8838 {
cf95b4f0 8839 if(dops[i+1].rs1) {
8840 if((hr=get_reg(regs[i+1].regmap,dops[i+1].rs1))>=0)
57871462 8841 {
8842 if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
8843 {
8844 regs[i].regmap[hr]=regs[i+1].regmap[hr];
8845 regmap_pre[i+1][hr]=regs[i+1].regmap[hr];
8846 regs[i+1].regmap_entry[hr]=regs[i+1].regmap[hr];
8847 regs[i].isconst&=~(1<<hr);
8848 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
8849 constmap[i][hr]=constmap[i+1][hr];
8850 regs[i+1].wasdirty&=~(1<<hr);
8851 regs[i].dirty&=~(1<<hr);
8852 }
8853 }
8854 }
cf95b4f0 8855 if(dops[i+1].rs2) {
8856 if((hr=get_reg(regs[i+1].regmap,dops[i+1].rs2))>=0)
57871462 8857 {
8858 if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
8859 {
8860 regs[i].regmap[hr]=regs[i+1].regmap[hr];
8861 regmap_pre[i+1][hr]=regs[i+1].regmap[hr];
8862 regs[i+1].regmap_entry[hr]=regs[i+1].regmap[hr];
8863 regs[i].isconst&=~(1<<hr);
8864 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
8865 constmap[i][hr]=constmap[i+1][hr];
8866 regs[i+1].wasdirty&=~(1<<hr);
8867 regs[i].dirty&=~(1<<hr);
8868 }
8869 }
8870 }
198df76f 8871 // Preload target address for load instruction (non-constant)
cf95b4f0 8872 if(dops[i+1].itype==LOAD&&dops[i+1].rs1&&get_reg(regs[i+1].regmap,dops[i+1].rs1)<0) {
8873 if((hr=get_reg(regs[i+1].regmap,dops[i+1].rt1))>=0)
57871462 8874 {
8875 if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
8876 {
cf95b4f0 8877 regs[i].regmap[hr]=dops[i+1].rs1;
8878 regmap_pre[i+1][hr]=dops[i+1].rs1;
8879 regs[i+1].regmap_entry[hr]=dops[i+1].rs1;
57871462 8880 regs[i].isconst&=~(1<<hr);
8881 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
8882 constmap[i][hr]=constmap[i+1][hr];
8883 regs[i+1].wasdirty&=~(1<<hr);
8884 regs[i].dirty&=~(1<<hr);
8885 }
8886 }
8887 }
9f51b4b9 8888 // Load source into target register
cf95b4f0 8889 if(dops[i+1].lt1&&get_reg(regs[i+1].regmap,dops[i+1].rs1)<0) {
8890 if((hr=get_reg(regs[i+1].regmap,dops[i+1].rt1))>=0)
57871462 8891 {
8892 if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
8893 {
cf95b4f0 8894 regs[i].regmap[hr]=dops[i+1].rs1;
8895 regmap_pre[i+1][hr]=dops[i+1].rs1;
8896 regs[i+1].regmap_entry[hr]=dops[i+1].rs1;
57871462 8897 regs[i].isconst&=~(1<<hr);
8898 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
8899 constmap[i][hr]=constmap[i+1][hr];
8900 regs[i+1].wasdirty&=~(1<<hr);
8901 regs[i].dirty&=~(1<<hr);
8902 }
8903 }
8904 }
198df76f 8905 // Address for store instruction (non-constant)
cf95b4f0 8906 if(dops[i+1].itype==STORE||dops[i+1].itype==STORELR
8907 ||(dops[i+1].opcode&0x3b)==0x39||(dops[i+1].opcode&0x3b)==0x3a) { // SB/SH/SW/SD/SWC1/SDC1/SWC2/SDC2
8908 if(get_reg(regs[i+1].regmap,dops[i+1].rs1)<0) {
57871462 8909 hr=get_reg2(regs[i].regmap,regs[i+1].regmap,-1);
8910 if(hr<0) hr=get_reg(regs[i+1].regmap,-1);
8911 else {regs[i+1].regmap[hr]=AGEN1+((i+1)&1);regs[i+1].isconst&=~(1<<hr);}
8912 assert(hr>=0);
8913 if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
8914 {
cf95b4f0 8915 regs[i].regmap[hr]=dops[i+1].rs1;
8916 regmap_pre[i+1][hr]=dops[i+1].rs1;
8917 regs[i+1].regmap_entry[hr]=dops[i+1].rs1;
57871462 8918 regs[i].isconst&=~(1<<hr);
8919 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
8920 constmap[i][hr]=constmap[i+1][hr];
8921 regs[i+1].wasdirty&=~(1<<hr);
8922 regs[i].dirty&=~(1<<hr);
8923 }
8924 }
8925 }
cf95b4f0 8926 if(dops[i+1].itype==LOADLR||(dops[i+1].opcode&0x3b)==0x31||(dops[i+1].opcode&0x3b)==0x32) { // LWC1/LDC1, LWC2/LDC2
8927 if(get_reg(regs[i+1].regmap,dops[i+1].rs1)<0) {
57871462 8928 int nr;
8929 hr=get_reg(regs[i+1].regmap,FTEMP);
8930 assert(hr>=0);
8931 if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
8932 {
cf95b4f0 8933 regs[i].regmap[hr]=dops[i+1].rs1;
8934 regmap_pre[i+1][hr]=dops[i+1].rs1;
8935 regs[i+1].regmap_entry[hr]=dops[i+1].rs1;
57871462 8936 regs[i].isconst&=~(1<<hr);
8937 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
8938 constmap[i][hr]=constmap[i+1][hr];
8939 regs[i+1].wasdirty&=~(1<<hr);
8940 regs[i].dirty&=~(1<<hr);
8941 }
8942 else if((nr=get_reg2(regs[i].regmap,regs[i+1].regmap,-1))>=0)
8943 {
8944 // move it to another register
8945 regs[i+1].regmap[hr]=-1;
8946 regmap_pre[i+2][hr]=-1;
8947 regs[i+1].regmap[nr]=FTEMP;
8948 regmap_pre[i+2][nr]=FTEMP;
cf95b4f0 8949 regs[i].regmap[nr]=dops[i+1].rs1;
8950 regmap_pre[i+1][nr]=dops[i+1].rs1;
8951 regs[i+1].regmap_entry[nr]=dops[i+1].rs1;
57871462 8952 regs[i].isconst&=~(1<<nr);
8953 regs[i+1].isconst&=~(1<<nr);
8954 regs[i].dirty&=~(1<<nr);
8955 regs[i+1].wasdirty&=~(1<<nr);
8956 regs[i+1].dirty&=~(1<<nr);
8957 regs[i+2].wasdirty&=~(1<<nr);
8958 }
8959 }
8960 }
cf95b4f0 8961 if(dops[i+1].itype==LOAD||dops[i+1].itype==LOADLR||dops[i+1].itype==STORE||dops[i+1].itype==STORELR/*||dops[i+1].itype==C1LS||||dops[i+1].itype==C2LS*/) {
8962 if(dops[i+1].itype==LOAD)
8963 hr=get_reg(regs[i+1].regmap,dops[i+1].rt1);
8964 if(dops[i+1].itype==LOADLR||(dops[i+1].opcode&0x3b)==0x31||(dops[i+1].opcode&0x3b)==0x32) // LWC1/LDC1, LWC2/LDC2
57871462 8965 hr=get_reg(regs[i+1].regmap,FTEMP);
cf95b4f0 8966 if(dops[i+1].itype==STORE||dops[i+1].itype==STORELR||(dops[i+1].opcode&0x3b)==0x39||(dops[i+1].opcode&0x3b)==0x3a) { // SWC1/SDC1/SWC2/SDC2
57871462 8967 hr=get_reg(regs[i+1].regmap,AGEN1+((i+1)&1));
8968 if(hr<0) hr=get_reg(regs[i+1].regmap,-1);
8969 }
8970 if(hr>=0&&regs[i].regmap[hr]<0) {
cf95b4f0 8971 int rs=get_reg(regs[i+1].regmap,dops[i+1].rs1);
57871462 8972 if(rs>=0&&((regs[i+1].wasconst>>rs)&1)) {
8973 regs[i].regmap[hr]=AGEN1+((i+1)&1);
8974 regmap_pre[i+1][hr]=AGEN1+((i+1)&1);
8975 regs[i+1].regmap_entry[hr]=AGEN1+((i+1)&1);
8976 regs[i].isconst&=~(1<<hr);
8977 regs[i+1].wasdirty&=~(1<<hr);
8978 regs[i].dirty&=~(1<<hr);
8979 }
8980 }
8981 }
8982 }
8983 }
8984 }
8985 }
9f51b4b9 8986
57871462 8987 /* Pass 6 - Optimize clean/dirty state */
8988 clean_registers(0,slen-1,1);
9f51b4b9 8989
57871462 8990 /* Pass 7 - Identify 32-bit registers */
04fd948a 8991 for (i=slen-1;i>=0;i--)
8992 {
cf95b4f0 8993 if(dops[i].itype==CJUMP||dops[i].itype==SJUMP)
04fd948a 8994 {
8995 // Conditional branch
8996 if((source[i]>>16)!=0x1000&&i<slen-2) {
8997 // Mark this address as a branch target since it may be called
8998 // upon return from interrupt
cf95b4f0 8999 dops[i+2].bt=1;
04fd948a 9000 }
9001 }
9002 }
57871462 9003
cf95b4f0 9004 if(dops[slen-1].itype==SPAN) {
9005 dops[slen-1].bt=1; // Mark as a branch target so instruction can restart after exception
57871462 9006 }
4600ba03 9007
9008#ifdef DISASM
57871462 9009 /* Debug/disassembly */
57871462 9010 for(i=0;i<slen;i++)
9011 {
9012 printf("U:");
9013 int r;
9014 for(r=1;r<=CCREG;r++) {
9015 if((unneeded_reg[i]>>r)&1) {
9016 if(r==HIREG) printf(" HI");
9017 else if(r==LOREG) printf(" LO");
9018 else printf(" r%d",r);
9019 }
9020 }
57871462 9021 printf("\n");
9022 #if defined(__i386__) || defined(__x86_64__)
9023 printf("pre: eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",regmap_pre[i][0],regmap_pre[i][1],regmap_pre[i][2],regmap_pre[i][3],regmap_pre[i][5],regmap_pre[i][6],regmap_pre[i][7]);
9024 #endif
9025 #ifdef __arm__
9026 printf("pre: r0=%d r1=%d r2=%d r3=%d r4=%d r5=%d r6=%d r7=%d r8=%d r9=%d r10=%d r12=%d\n",regmap_pre[i][0],regmap_pre[i][1],regmap_pre[i][2],regmap_pre[i][3],regmap_pre[i][4],regmap_pre[i][5],regmap_pre[i][6],regmap_pre[i][7],regmap_pre[i][8],regmap_pre[i][9],regmap_pre[i][10],regmap_pre[i][12]);
9027 #endif
7c3a5182 9028 #if defined(__i386__) || defined(__x86_64__)
57871462 9029 printf("needs: ");
9030 if(needed_reg[i]&1) printf("eax ");
9031 if((needed_reg[i]>>1)&1) printf("ecx ");
9032 if((needed_reg[i]>>2)&1) printf("edx ");
9033 if((needed_reg[i]>>3)&1) printf("ebx ");
9034 if((needed_reg[i]>>5)&1) printf("ebp ");
9035 if((needed_reg[i]>>6)&1) printf("esi ");
9036 if((needed_reg[i]>>7)&1) printf("edi ");
57871462 9037 printf("\n");
57871462 9038 printf("entry: eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",regs[i].regmap_entry[0],regs[i].regmap_entry[1],regs[i].regmap_entry[2],regs[i].regmap_entry[3],regs[i].regmap_entry[5],regs[i].regmap_entry[6],regs[i].regmap_entry[7]);
9039 printf("dirty: ");
9040 if(regs[i].wasdirty&1) printf("eax ");
9041 if((regs[i].wasdirty>>1)&1) printf("ecx ");
9042 if((regs[i].wasdirty>>2)&1) printf("edx ");
9043 if((regs[i].wasdirty>>3)&1) printf("ebx ");
9044 if((regs[i].wasdirty>>5)&1) printf("ebp ");
9045 if((regs[i].wasdirty>>6)&1) printf("esi ");
9046 if((regs[i].wasdirty>>7)&1) printf("edi ");
9047 #endif
9048 #ifdef __arm__
9049 printf("entry: r0=%d r1=%d r2=%d r3=%d r4=%d r5=%d r6=%d r7=%d r8=%d r9=%d r10=%d r12=%d\n",regs[i].regmap_entry[0],regs[i].regmap_entry[1],regs[i].regmap_entry[2],regs[i].regmap_entry[3],regs[i].regmap_entry[4],regs[i].regmap_entry[5],regs[i].regmap_entry[6],regs[i].regmap_entry[7],regs[i].regmap_entry[8],regs[i].regmap_entry[9],regs[i].regmap_entry[10],regs[i].regmap_entry[12]);
9050 printf("dirty: ");
9051 if(regs[i].wasdirty&1) printf("r0 ");
9052 if((regs[i].wasdirty>>1)&1) printf("r1 ");
9053 if((regs[i].wasdirty>>2)&1) printf("r2 ");
9054 if((regs[i].wasdirty>>3)&1) printf("r3 ");
9055 if((regs[i].wasdirty>>4)&1) printf("r4 ");
9056 if((regs[i].wasdirty>>5)&1) printf("r5 ");
9057 if((regs[i].wasdirty>>6)&1) printf("r6 ");
9058 if((regs[i].wasdirty>>7)&1) printf("r7 ");
9059 if((regs[i].wasdirty>>8)&1) printf("r8 ");
9060 if((regs[i].wasdirty>>9)&1) printf("r9 ");
9061 if((regs[i].wasdirty>>10)&1) printf("r10 ");
9062 if((regs[i].wasdirty>>12)&1) printf("r12 ");
9063 #endif
9064 printf("\n");
9065 disassemble_inst(i);
9066 //printf ("ccadj[%d] = %d\n",i,ccadj[i]);
9067 #if defined(__i386__) || defined(__x86_64__)
9068 printf("eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d dirty: ",regs[i].regmap[0],regs[i].regmap[1],regs[i].regmap[2],regs[i].regmap[3],regs[i].regmap[5],regs[i].regmap[6],regs[i].regmap[7]);
9069 if(regs[i].dirty&1) printf("eax ");
9070 if((regs[i].dirty>>1)&1) printf("ecx ");
9071 if((regs[i].dirty>>2)&1) printf("edx ");
9072 if((regs[i].dirty>>3)&1) printf("ebx ");
9073 if((regs[i].dirty>>5)&1) printf("ebp ");
9074 if((regs[i].dirty>>6)&1) printf("esi ");
9075 if((regs[i].dirty>>7)&1) printf("edi ");
9076 #endif
9077 #ifdef __arm__
9078 printf("r0=%d r1=%d r2=%d r3=%d r4=%d r5=%d r6=%d r7=%d r8=%d r9=%d r10=%d r12=%d dirty: ",regs[i].regmap[0],regs[i].regmap[1],regs[i].regmap[2],regs[i].regmap[3],regs[i].regmap[4],regs[i].regmap[5],regs[i].regmap[6],regs[i].regmap[7],regs[i].regmap[8],regs[i].regmap[9],regs[i].regmap[10],regs[i].regmap[12]);
9079 if(regs[i].dirty&1) printf("r0 ");
9080 if((regs[i].dirty>>1)&1) printf("r1 ");
9081 if((regs[i].dirty>>2)&1) printf("r2 ");
9082 if((regs[i].dirty>>3)&1) printf("r3 ");
9083 if((regs[i].dirty>>4)&1) printf("r4 ");
9084 if((regs[i].dirty>>5)&1) printf("r5 ");
9085 if((regs[i].dirty>>6)&1) printf("r6 ");
9086 if((regs[i].dirty>>7)&1) printf("r7 ");
9087 if((regs[i].dirty>>8)&1) printf("r8 ");
9088 if((regs[i].dirty>>9)&1) printf("r9 ");
9089 if((regs[i].dirty>>10)&1) printf("r10 ");
9090 if((regs[i].dirty>>12)&1) printf("r12 ");
9091 #endif
9092 printf("\n");
9093 if(regs[i].isconst) {
9094 printf("constants: ");
9095 #if defined(__i386__) || defined(__x86_64__)
643aeae3 9096 if(regs[i].isconst&1) printf("eax=%x ",(u_int)constmap[i][0]);
9097 if((regs[i].isconst>>1)&1) printf("ecx=%x ",(u_int)constmap[i][1]);
9098 if((regs[i].isconst>>2)&1) printf("edx=%x ",(u_int)constmap[i][2]);
9099 if((regs[i].isconst>>3)&1) printf("ebx=%x ",(u_int)constmap[i][3]);
9100 if((regs[i].isconst>>5)&1) printf("ebp=%x ",(u_int)constmap[i][5]);
9101 if((regs[i].isconst>>6)&1) printf("esi=%x ",(u_int)constmap[i][6]);
9102 if((regs[i].isconst>>7)&1) printf("edi=%x ",(u_int)constmap[i][7]);
57871462 9103 #endif
7c3a5182 9104 #if defined(__arm__) || defined(__aarch64__)
643aeae3 9105 int r;
9106 for (r = 0; r < ARRAY_SIZE(constmap[i]); r++)
9107 if ((regs[i].isconst >> r) & 1)
9108 printf(" r%d=%x", r, (u_int)constmap[i][r]);
57871462 9109 #endif
9110 printf("\n");
9111 }
fe807a8a 9112 if(dops[i].is_jump) {
57871462 9113 #if defined(__i386__) || defined(__x86_64__)
9114 printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d dirty: ",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
9115 if(branch_regs[i].dirty&1) printf("eax ");
9116 if((branch_regs[i].dirty>>1)&1) printf("ecx ");
9117 if((branch_regs[i].dirty>>2)&1) printf("edx ");
9118 if((branch_regs[i].dirty>>3)&1) printf("ebx ");
9119 if((branch_regs[i].dirty>>5)&1) printf("ebp ");
9120 if((branch_regs[i].dirty>>6)&1) printf("esi ");
9121 if((branch_regs[i].dirty>>7)&1) printf("edi ");
9122 #endif
9123 #ifdef __arm__
9124 printf("branch(%d): r0=%d r1=%d r2=%d r3=%d r4=%d r5=%d r6=%d r7=%d r8=%d r9=%d r10=%d r12=%d dirty: ",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[4],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7],branch_regs[i].regmap[8],branch_regs[i].regmap[9],branch_regs[i].regmap[10],branch_regs[i].regmap[12]);
9125 if(branch_regs[i].dirty&1) printf("r0 ");
9126 if((branch_regs[i].dirty>>1)&1) printf("r1 ");
9127 if((branch_regs[i].dirty>>2)&1) printf("r2 ");
9128 if((branch_regs[i].dirty>>3)&1) printf("r3 ");
9129 if((branch_regs[i].dirty>>4)&1) printf("r4 ");
9130 if((branch_regs[i].dirty>>5)&1) printf("r5 ");
9131 if((branch_regs[i].dirty>>6)&1) printf("r6 ");
9132 if((branch_regs[i].dirty>>7)&1) printf("r7 ");
9133 if((branch_regs[i].dirty>>8)&1) printf("r8 ");
9134 if((branch_regs[i].dirty>>9)&1) printf("r9 ");
9135 if((branch_regs[i].dirty>>10)&1) printf("r10 ");
9136 if((branch_regs[i].dirty>>12)&1) printf("r12 ");
9137 #endif
57871462 9138 }
9139 }
4600ba03 9140#endif // DISASM
57871462 9141
9142 /* Pass 8 - Assembly */
9143 linkcount=0;stubcount=0;
9144 ds=0;is_delayslot=0;
57871462 9145 u_int dirty_pre=0;
d148d265 9146 void *beginning=start_block();
57871462 9147 if((u_int)addr&1) {
9148 ds=1;
9149 pagespan_ds();
9150 }
df4dc2b1 9151 void *instr_addr0_override = NULL;
9ad4d757 9152
9ad4d757 9153 if (start == 0x80030000) {
3968e69e 9154 // nasty hack for the fastbios thing
96186eba 9155 // override block entry to this code
df4dc2b1 9156 instr_addr0_override = out;
9ad4d757 9157 emit_movimm(start,0);
96186eba 9158 // abuse io address var as a flag that we
9159 // have already returned here once
643aeae3 9160 emit_readword(&address,1);
9161 emit_writeword(0,&pcaddr);
9162 emit_writeword(0,&address);
9ad4d757 9163 emit_cmp(0,1);
3968e69e 9164 #ifdef __aarch64__
9165 emit_jeq(out + 4*2);
2a014d73 9166 emit_far_jump(new_dyna_leave);
3968e69e 9167 #else
643aeae3 9168 emit_jne(new_dyna_leave);
3968e69e 9169 #endif
9ad4d757 9170 }
57871462 9171 for(i=0;i<slen;i++)
9172 {
9173 //if(ds) printf("ds: ");
4600ba03 9174 disassemble_inst(i);
57871462 9175 if(ds) {
9176 ds=0; // Skip delay slot
cf95b4f0 9177 if(dops[i].bt) assem_debug("OOPS - branch into delay slot\n");
df4dc2b1 9178 instr_addr[i] = NULL;
57871462 9179 } else {
ffb0b9e0 9180 speculate_register_values(i);
57871462 9181 #ifndef DESTRUCTIVE_WRITEBACK
fe807a8a 9182 if (i < 2 || !dops[i-2].is_ujump)
57871462 9183 {
ad49de89 9184 wb_valid(regmap_pre[i],regs[i].regmap_entry,dirty_pre,regs[i].wasdirty,unneeded_reg[i]);
57871462 9185 }
fe807a8a 9186 if((dops[i].itype==CJUMP||dops[i].itype==SJUMP)) {
f776eb14 9187 dirty_pre=branch_regs[i].dirty;
9188 }else{
f776eb14 9189 dirty_pre=regs[i].dirty;
9190 }
57871462 9191 #endif
9192 // write back
fe807a8a 9193 if (i < 2 || !dops[i-2].is_ujump)
57871462 9194 {
ad49de89 9195 wb_invalidate(regmap_pre[i],regs[i].regmap_entry,regs[i].wasdirty,unneeded_reg[i]);
57871462 9196 loop_preload(regmap_pre[i],regs[i].regmap_entry);
9197 }
9198 // branch target entry point
df4dc2b1 9199 instr_addr[i] = out;
57871462 9200 assem_debug("<->\n");
2330734f 9201 drc_dbg_emit_do_cmp(i, ccadj[i]);
dd114d7d 9202
57871462 9203 // load regs
9204 if(regs[i].regmap_entry[HOST_CCREG]==CCREG&&regs[i].regmap[HOST_CCREG]!=CCREG)
ad49de89 9205 wb_register(CCREG,regs[i].regmap_entry,regs[i].wasdirty);
cf95b4f0 9206 load_regs(regs[i].regmap_entry,regs[i].regmap,dops[i].rs1,dops[i].rs2);
57871462 9207 address_generation(i,&regs[i],regs[i].regmap_entry);
ad49de89 9208 load_consts(regmap_pre[i],regs[i].regmap,i);
fe807a8a 9209 if(dops[i].is_jump)
57871462 9210 {
9211 // Load the delay slot registers if necessary
cf95b4f0 9212 if(dops[i+1].rs1!=dops[i].rs1&&dops[i+1].rs1!=dops[i].rs2&&(dops[i+1].rs1!=dops[i].rt1||dops[i].rt1==0))
9213 load_regs(regs[i].regmap_entry,regs[i].regmap,dops[i+1].rs1,dops[i+1].rs1);
9214 if(dops[i+1].rs2!=dops[i+1].rs1&&dops[i+1].rs2!=dops[i].rs1&&dops[i+1].rs2!=dops[i].rs2&&(dops[i+1].rs2!=dops[i].rt1||dops[i].rt1==0))
9215 load_regs(regs[i].regmap_entry,regs[i].regmap,dops[i+1].rs2,dops[i+1].rs2);
37387d8b 9216 if (ram_offset && (dops[i+1].is_load || dops[i+1].is_store))
9217 load_regs(regs[i].regmap_entry,regs[i].regmap,ROREG,ROREG);
9218 if (dops[i+1].is_store)
ad49de89 9219 load_regs(regs[i].regmap_entry,regs[i].regmap,INVCP,INVCP);
57871462 9220 }
9221 else if(i+1<slen)
9222 {
9223 // Preload registers for following instruction
cf95b4f0 9224 if(dops[i+1].rs1!=dops[i].rs1&&dops[i+1].rs1!=dops[i].rs2)
9225 if(dops[i+1].rs1!=dops[i].rt1&&dops[i+1].rs1!=dops[i].rt2)
9226 load_regs(regs[i].regmap_entry,regs[i].regmap,dops[i+1].rs1,dops[i+1].rs1);
9227 if(dops[i+1].rs2!=dops[i+1].rs1&&dops[i+1].rs2!=dops[i].rs1&&dops[i+1].rs2!=dops[i].rs2)
9228 if(dops[i+1].rs2!=dops[i].rt1&&dops[i+1].rs2!=dops[i].rt2)
9229 load_regs(regs[i].regmap_entry,regs[i].regmap,dops[i+1].rs2,dops[i+1].rs2);
57871462 9230 }
9231 // TODO: if(is_ooo(i)) address_generation(i+1);
9a3ccfeb 9232 if (!dops[i].is_jump || dops[i].itype == CJUMP)
ad49de89 9233 load_regs(regs[i].regmap_entry,regs[i].regmap,CCREG,CCREG);
37387d8b 9234 if (ram_offset && (dops[i].is_load || dops[i].is_store))
9235 load_regs(regs[i].regmap_entry,regs[i].regmap,ROREG,ROREG);
9236 if (dops[i].is_store)
ad49de89 9237 load_regs(regs[i].regmap_entry,regs[i].regmap,INVCP,INVCP);
2330734f 9238
9239 ds = assemble(i, &regs[i], ccadj[i]);
9240
fe807a8a 9241 if (dops[i].is_ujump)
57871462 9242 literal_pool(1024);
9243 else
9244 literal_pool_jumpover(256);
9245 }
9246 }
3d680478 9247
9248 assert(slen > 0);
cf95b4f0 9249 if (slen > 0 && dops[slen-1].itype == INTCALL) {
3d680478 9250 // no ending needed for this block since INTCALL never returns
9251 }
57871462 9252 // If the block did not end with an unconditional branch,
9253 // add a jump to the next instruction.
3d680478 9254 else if (i > 1) {
fe807a8a 9255 if (!dops[i-2].is_ujump && dops[i-1].itype != SPAN) {
9256 assert(!dops[i-1].is_jump);
57871462 9257 assert(i==slen);
cf95b4f0 9258 if(dops[i-2].itype!=CJUMP&&dops[i-2].itype!=SJUMP) {
ad49de89 9259 store_regs_bt(regs[i-1].regmap,regs[i-1].dirty,start+i*4);
57871462 9260 if(regs[i-1].regmap[HOST_CCREG]!=CCREG)
9261 emit_loadreg(CCREG,HOST_CCREG);
2330734f 9262 emit_addimm(HOST_CCREG, ccadj[i-1] + CLOCK_ADJUST(1), HOST_CCREG);
57871462 9263 }
fe807a8a 9264 else
57871462 9265 {
ad49de89 9266 store_regs_bt(branch_regs[i-2].regmap,branch_regs[i-2].dirty,start+i*4);
57871462 9267 assert(branch_regs[i-2].regmap[HOST_CCREG]==CCREG);
9268 }
643aeae3 9269 add_to_linker(out,start+i*4,0);
57871462 9270 emit_jmp(0);
9271 }
9272 }
9273 else
9274 {
9275 assert(i>0);
fe807a8a 9276 assert(!dops[i-1].is_jump);
ad49de89 9277 store_regs_bt(regs[i-1].regmap,regs[i-1].dirty,start+i*4);
57871462 9278 if(regs[i-1].regmap[HOST_CCREG]!=CCREG)
9279 emit_loadreg(CCREG,HOST_CCREG);
2330734f 9280 emit_addimm(HOST_CCREG, ccadj[i-1] + CLOCK_ADJUST(1), HOST_CCREG);
643aeae3 9281 add_to_linker(out,start+i*4,0);
57871462 9282 emit_jmp(0);
9283 }
9284
9285 // TODO: delay slot stubs?
9286 // Stubs
9287 for(i=0;i<stubcount;i++)
9288 {
b14b6a8f 9289 switch(stubs[i].type)
57871462 9290 {
9291 case LOADB_STUB:
9292 case LOADH_STUB:
9293 case LOADW_STUB:
9294 case LOADD_STUB:
9295 case LOADBU_STUB:
9296 case LOADHU_STUB:
9297 do_readstub(i);break;
9298 case STOREB_STUB:
9299 case STOREH_STUB:
9300 case STOREW_STUB:
9301 case STORED_STUB:
9302 do_writestub(i);break;
9303 case CC_STUB:
9304 do_ccstub(i);break;
9305 case INVCODE_STUB:
9306 do_invstub(i);break;
9307 case FP_STUB:
9308 do_cop1stub(i);break;
9309 case STORELR_STUB:
9310 do_unalignedwritestub(i);break;
9311 }
9312 }
9313
9ad4d757 9314 if (instr_addr0_override)
9315 instr_addr[0] = instr_addr0_override;
9316
57871462 9317 /* Pass 9 - Linker */
9318 for(i=0;i<linkcount;i++)
9319 {
643aeae3 9320 assem_debug("%p -> %8x\n",link_addr[i].addr,link_addr[i].target);
57871462 9321 literal_pool(64);
643aeae3 9322 if (!link_addr[i].ext)
57871462 9323 {
643aeae3 9324 void *stub = out;
9325 void *addr = check_addr(link_addr[i].target);
9326 emit_extjump(link_addr[i].addr, link_addr[i].target);
9327 if (addr) {
9328 set_jump_target(link_addr[i].addr, addr);
3d680478 9329 add_jump_out(link_addr[i].target,stub);
57871462 9330 }
643aeae3 9331 else
9332 set_jump_target(link_addr[i].addr, stub);
57871462 9333 }
9334 else
9335 {
9336 // Internal branch
643aeae3 9337 int target=(link_addr[i].target-start)>>2;
57871462 9338 assert(target>=0&&target<slen);
9339 assert(instr_addr[target]);
9340 //#ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
643aeae3 9341 //set_jump_target_fillslot(link_addr[i].addr,instr_addr[target],link_addr[i].ext>>1);
57871462 9342 //#else
643aeae3 9343 set_jump_target(link_addr[i].addr, instr_addr[target]);
57871462 9344 //#endif
9345 }
9346 }
3d680478 9347
9348 u_int source_len = slen*4;
cf95b4f0 9349 if (dops[slen-1].itype == INTCALL && source_len > 4)
3d680478 9350 // no need to treat the last instruction as compiled
9351 // as interpreter fully handles it
9352 source_len -= 4;
9353
9354 if ((u_char *)copy + source_len > (u_char *)shadow + sizeof(shadow))
9355 copy = shadow;
9356
57871462 9357 // External Branch Targets (jump_in)
57871462 9358 for(i=0;i<slen;i++)
9359 {
cf95b4f0 9360 if(dops[i].bt||i==0)
57871462 9361 {
9362 if(instr_addr[i]) // TODO - delay slots (=null)
9363 {
9364 u_int vaddr=start+i*4;
94d23bb9 9365 u_int page=get_page(vaddr);
9366 u_int vpage=get_vpage(vaddr);
57871462 9367 literal_pool(256);
57871462 9368 {
df4dc2b1 9369 assem_debug("%p (%d) <- %8x\n",instr_addr[i],i,start+i*4);
57871462 9370 assem_debug("jump_in: %x\n",start+i*4);
df4dc2b1 9371 ll_add(jump_dirty+vpage,vaddr,out);
3d680478 9372 void *entry_point = do_dirty_stub(i, source_len);
df4dc2b1 9373 ll_add_flags(jump_in+page,vaddr,state_rflags,entry_point);
57871462 9374 // If there was an existing entry in the hash table,
9375 // replace it with the new address.
9376 // Don't add new entries. We'll insert the
9377 // ones that actually get used in check_addr().
df4dc2b1 9378 struct ht_entry *ht_bin = hash_table_get(vaddr);
9379 if (ht_bin->vaddr[0] == vaddr)
9380 ht_bin->tcaddr[0] = entry_point;
9381 if (ht_bin->vaddr[1] == vaddr)
9382 ht_bin->tcaddr[1] = entry_point;
57871462 9383 }
57871462 9384 }
9385 }
9386 }
9387 // Write out the literal pool if necessary
9388 literal_pool(0);
9389 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
9390 // Align code
9391 if(((u_int)out)&7) emit_addnop(13);
9392 #endif
01d26796 9393 assert(out - (u_char *)beginning < MAX_OUTPUT_BLOCK_SIZE);
643aeae3 9394 //printf("shadow buffer: %p-%p\n",copy,(u_char *)copy+slen*4);
3d680478 9395 memcpy(copy, source, source_len);
9396 copy += source_len;
9f51b4b9 9397
d148d265 9398 end_block(beginning);
9f51b4b9 9399
57871462 9400 // If we're within 256K of the end of the buffer,
9401 // start over from the beginning. (Is 256K enough?)
2a014d73 9402 if (out > ndrc->translation_cache + sizeof(ndrc->translation_cache) - MAX_OUTPUT_BLOCK_SIZE)
9403 out = ndrc->translation_cache;
9f51b4b9 9404
57871462 9405 // Trap writes to any of the pages we compiled
9406 for(i=start>>12;i<=(start+slen*4)>>12;i++) {
9407 invalid_code[i]=0;
57871462 9408 }
9be4ba64 9409 inv_code_start=inv_code_end=~0;
71e490c5 9410
b96d3df7 9411 // for PCSX we need to mark all mirrors too
b12c9fb8 9412 if(get_page(start)<(RAM_SIZE>>12))
9413 for(i=start>>12;i<=(start+slen*4)>>12;i++)
b96d3df7 9414 invalid_code[((u_int)0x00000000>>12)|(i&0x1ff)]=
9415 invalid_code[((u_int)0x80000000>>12)|(i&0x1ff)]=
9416 invalid_code[((u_int)0xa0000000>>12)|(i&0x1ff)]=0;
9f51b4b9 9417
57871462 9418 /* Pass 10 - Free memory by expiring oldest blocks */
9f51b4b9 9419
2a014d73 9420 int end=(((out-ndrc->translation_cache)>>(TARGET_SIZE_2-16))+16384)&65535;
57871462 9421 while(expirep!=end)
9422 {
9423 int shift=TARGET_SIZE_2-3; // Divide into 8 blocks
943f42f3 9424 uintptr_t base_offs = ((uintptr_t)(expirep >> 13) << shift); // Base offset of this block
9425 uintptr_t base_offs_s = base_offs >> shift;
57871462 9426 inv_debug("EXP: Phase %d\n",expirep);
9427 switch((expirep>>11)&3)
9428 {
9429 case 0:
9430 // Clear jump_in and jump_dirty
943f42f3 9431 ll_remove_matching_addrs(jump_in+(expirep&2047),base_offs_s,shift);
9432 ll_remove_matching_addrs(jump_dirty+(expirep&2047),base_offs_s,shift);
9433 ll_remove_matching_addrs(jump_in+2048+(expirep&2047),base_offs_s,shift);
9434 ll_remove_matching_addrs(jump_dirty+2048+(expirep&2047),base_offs_s,shift);
57871462 9435 break;
9436 case 1:
9437 // Clear pointers
943f42f3 9438 ll_kill_pointers(jump_out[expirep&2047],base_offs_s,shift);
9439 ll_kill_pointers(jump_out[(expirep&2047)+2048],base_offs_s,shift);
57871462 9440 break;
9441 case 2:
9442 // Clear hash table
9443 for(i=0;i<32;i++) {
df4dc2b1 9444 struct ht_entry *ht_bin = &hash_table[((expirep&2047)<<5)+i];
943f42f3 9445 uintptr_t o1 = (u_char *)ht_bin->tcaddr[1] - ndrc->translation_cache;
9446 uintptr_t o2 = o1 - MAX_OUTPUT_BLOCK_SIZE;
9447 if ((o1 >> shift) == base_offs_s || (o2 >> shift) == base_offs_s) {
df4dc2b1 9448 inv_debug("EXP: Remove hash %x -> %p\n",ht_bin->vaddr[1],ht_bin->tcaddr[1]);
9449 ht_bin->vaddr[1] = -1;
9450 ht_bin->tcaddr[1] = NULL;
9451 }
943f42f3 9452 o1 = (u_char *)ht_bin->tcaddr[0] - ndrc->translation_cache;
9453 o2 = o1 - MAX_OUTPUT_BLOCK_SIZE;
9454 if ((o1 >> shift) == base_offs_s || (o2 >> shift) == base_offs_s) {
df4dc2b1 9455 inv_debug("EXP: Remove hash %x -> %p\n",ht_bin->vaddr[0],ht_bin->tcaddr[0]);
9456 ht_bin->vaddr[0] = ht_bin->vaddr[1];
9457 ht_bin->tcaddr[0] = ht_bin->tcaddr[1];
9458 ht_bin->vaddr[1] = -1;
9459 ht_bin->tcaddr[1] = NULL;
57871462 9460 }
9461 }
9462 break;
9463 case 3:
9464 // Clear jump_out
9f51b4b9 9465 if((expirep&2047)==0)
dd3a91a1 9466 do_clear_cache();
943f42f3 9467 ll_remove_matching_addrs(jump_out+(expirep&2047),base_offs_s,shift);
9468 ll_remove_matching_addrs(jump_out+2048+(expirep&2047),base_offs_s,shift);
57871462 9469 break;
9470 }
9471 expirep=(expirep+1)&65535;
9472 }
37387d8b 9473#ifdef ASSEM_PRINT
9474 fflush(stdout);
9475#endif
57871462 9476 return 0;
9477}
b9b61529 9478
9479// vim:shiftwidth=2:expandtab
ARM optimized PCSX fork