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32x: improve pwm accuracy
[picodrive.git] / pico / pico_int.h
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cff531af 1/*\r
2 * PicoDrive - Internal Header File\r
3 * (c) Copyright Dave, 2004\r
4 * (C) notaz, 2006-2010\r
5 *\r
6 * This work is licensed under the terms of MAME license.\r
7 * See COPYING file in the top-level directory.\r
8 */\r
cc68a136 9\r
eff55556 10#ifndef PICO_INTERNAL_INCLUDED\r
11#define PICO_INTERNAL_INCLUDED\r
cc68a136 12\r
13#include <stdio.h>\r
14#include <stdlib.h>\r
15#include <string.h>\r
efcba75f 16#include "pico.h"\r
f53f286a 17#include "carthw/carthw.h"\r
cc68a136 18\r
89fa852d 19//\r
20#define USE_POLL_DETECT\r
21\r
eff55556 22#ifndef PICO_INTERNAL\r
23#define PICO_INTERNAL\r
24#endif\r
25#ifndef PICO_INTERNAL_ASM\r
26#define PICO_INTERNAL_ASM\r
27#endif\r
cc68a136 28\r
70357ce5 29// to select core, define EMU_C68K, EMU_M68K or EMU_F68K in your makefile or project\r
cc68a136 30\r
31#ifdef __cplusplus\r
32extern "C" {\r
33#endif\r
34\r
35\r
36// ----------------------- 68000 CPU -----------------------\r
37#ifdef EMU_C68K\r
d4d62665 38#include "../cpu/cyclone/Cyclone.h"\r
3aa1e148 39extern struct Cyclone PicoCpuCM68k, PicoCpuCS68k;\r
40#define SekCyclesLeftNoMCD PicoCpuCM68k.cycles // cycles left for this run\r
7336a99a 41#define SekCyclesLeft \\r
602133e1 42 (((PicoAHW&1) && (PicoOpt & POPT_EN_MCD_PSYNC)) ? (SekCycleAim-SekCycleCnt) : SekCyclesLeftNoMCD)\r
7a1f6e45 43#define SekCyclesLeftS68k \\r
602133e1 44 ((PicoOpt & POPT_EN_MCD_PSYNC) ? (SekCycleAimS68k-SekCycleCntS68k) : PicoCpuCS68k.cycles)\r
ef090115 45#define SekEndTimeslice(after) PicoCpuCM68k.cycles=after\r
07ceafdb 46#define SekEndTimesliceS68k(after) PicoCpuCS68k.cycles=after\r
3aa1e148 47#define SekPc (PicoCpuCM68k.pc-PicoCpuCM68k.membase)\r
48#define SekPcS68k (PicoCpuCS68k.pc-PicoCpuCS68k.membase)\r
d4d62665 49#define SekDar(x) (x < 8 ? PicoCpuCM68k.d[x] : PicoCpuCM68k.a[x - 8])\r
5fadfb1c 50#define SekSr CycloneGetSr(&PicoCpuCM68k)\r
3aa1e148 51#define SekSetStop(x) { PicoCpuCM68k.state_flags&=~1; if (x) { PicoCpuCM68k.state_flags|=1; PicoCpuCM68k.cycles=0; } }\r
52#define SekSetStopS68k(x) { PicoCpuCS68k.state_flags&=~1; if (x) { PicoCpuCS68k.state_flags|=1; PicoCpuCS68k.cycles=0; } }\r
ed4402a7 53#define SekIsStoppedM68k() (PicoCpuCM68k.state_flags&1)\r
ca61ee42 54#define SekIsStoppedS68k() (PicoCpuCS68k.state_flags&1)\r
03e4f2a3 55#define SekShouldInterrupt (PicoCpuCM68k.irq > (PicoCpuCM68k.srh&7))\r
b542be46 56\r
57#define SekInterrupt(i) PicoCpuCM68k.irq=i\r
5fadfb1c 58#define SekIrqLevel PicoCpuCM68k.irq\r
b542be46 59\r
03e4f2a3 60#ifdef EMU_M68K\r
61#define EMU_CORE_DEBUG\r
62#endif\r
cc68a136 63#endif\r
64\r
70357ce5 65#ifdef EMU_F68K\r
66#include "../cpu/fame/fame.h"\r
b542be46 67extern M68K_CONTEXT PicoCpuFM68k, PicoCpuFS68k;\r
3aa1e148 68#define SekCyclesLeftNoMCD PicoCpuFM68k.io_cycle_counter\r
70357ce5 69#define SekCyclesLeft \\r
602133e1 70 (((PicoAHW&1) && (PicoOpt & POPT_EN_MCD_PSYNC)) ? (SekCycleAim-SekCycleCnt) : SekCyclesLeftNoMCD)\r
70357ce5 71#define SekCyclesLeftS68k \\r
602133e1 72 ((PicoOpt & POPT_EN_MCD_PSYNC) ? (SekCycleAimS68k-SekCycleCntS68k) : PicoCpuFS68k.io_cycle_counter)\r
ef090115 73#define SekEndTimeslice(after) PicoCpuFM68k.io_cycle_counter=after\r
07ceafdb 74#define SekEndTimesliceS68k(after) PicoCpuFS68k.io_cycle_counter=after\r
03e4f2a3 75#define SekPc fm68k_get_pc(&PicoCpuFM68k)\r
76#define SekPcS68k fm68k_get_pc(&PicoCpuFS68k)\r
d4d62665 77#define SekDar(x) (x < 8 ? PicoCpuFM68k.dreg[x].D : PicoCpuFM68k.areg[x - 8].D)\r
5fadfb1c 78#define SekSr PicoCpuFM68k.sr\r
70357ce5 79#define SekSetStop(x) { \\r
03e4f2a3 80 PicoCpuFM68k.execinfo &= ~FM68K_HALTED; \\r
81 if (x) { PicoCpuFM68k.execinfo |= FM68K_HALTED; PicoCpuFM68k.io_cycle_counter = 0; } \\r
70357ce5 82}\r
83#define SekSetStopS68k(x) { \\r
03e4f2a3 84 PicoCpuFS68k.execinfo &= ~FM68K_HALTED; \\r
85 if (x) { PicoCpuFS68k.execinfo |= FM68K_HALTED; PicoCpuFS68k.io_cycle_counter = 0; } \\r
70357ce5 86}\r
ed4402a7 87#define SekIsStoppedM68k() (PicoCpuFM68k.execinfo&FM68K_HALTED)\r
ca61ee42 88#define SekIsStoppedS68k() (PicoCpuFS68k.execinfo&FM68K_HALTED)\r
03e4f2a3 89#define SekShouldInterrupt fm68k_would_interrupt()\r
b542be46 90\r
91#define SekInterrupt(irq) PicoCpuFM68k.interrupts[0]=irq\r
5fadfb1c 92#define SekIrqLevel PicoCpuFM68k.interrupts[0]\r
b542be46 93\r
03e4f2a3 94#ifdef EMU_M68K\r
95#define EMU_CORE_DEBUG\r
96#endif\r
cc68a136 97#endif\r
98\r
99#ifdef EMU_M68K\r
100#include "../cpu/musashi/m68kcpu.h"\r
3aa1e148 101extern m68ki_cpu_core PicoCpuMM68k, PicoCpuMS68k;\r
cc68a136 102#ifndef SekCyclesLeft\r
3aa1e148 103#define SekCyclesLeftNoMCD PicoCpuMM68k.cyc_remaining_cycles\r
7336a99a 104#define SekCyclesLeft \\r
602133e1 105 (((PicoAHW&1) && (PicoOpt & POPT_EN_MCD_PSYNC)) ? (SekCycleAim-SekCycleCnt) : SekCyclesLeftNoMCD)\r
7a1f6e45 106#define SekCyclesLeftS68k \\r
602133e1 107 ((PicoOpt & POPT_EN_MCD_PSYNC) ? (SekCycleAimS68k-SekCycleCntS68k) : PicoCpuMS68k.cyc_remaining_cycles)\r
ef090115 108#define SekEndTimeslice(after) SET_CYCLES(after)\r
07ceafdb 109#define SekEndTimesliceS68k(after) PicoCpuMS68k.cyc_remaining_cycles=after\r
3aa1e148 110#define SekPc m68k_get_reg(&PicoCpuMM68k, M68K_REG_PC)\r
111#define SekPcS68k m68k_get_reg(&PicoCpuMS68k, M68K_REG_PC)\r
5fadfb1c 112#define SekDar(x) PicoCpuMM68k.dar[x]\r
113#define SekSr m68k_get_reg(&PicoCpuMM68k, M68K_REG_SR)\r
7a1f6e45 114#define SekSetStop(x) { \\r
3aa1e148 115 if(x) { SET_CYCLES(0); PicoCpuMM68k.stopped=STOP_LEVEL_STOP; } \\r
116 else PicoCpuMM68k.stopped=0; \\r
7a1f6e45 117}\r
118#define SekSetStopS68k(x) { \\r
3aa1e148 119 if(x) { SET_CYCLES(0); PicoCpuMS68k.stopped=STOP_LEVEL_STOP; } \\r
120 else PicoCpuMS68k.stopped=0; \\r
7a1f6e45 121}\r
ed4402a7 122#define SekIsStoppedM68k() (PicoCpuMM68k.stopped==STOP_LEVEL_STOP)\r
ca61ee42 123#define SekIsStoppedS68k() (PicoCpuMS68k.stopped==STOP_LEVEL_STOP)\r
03e4f2a3 124#define SekShouldInterrupt (CPU_INT_LEVEL > FLAG_INT_MASK)\r
b542be46 125\r
71de3cd9 126#define SekInterrupt(irq) { \\r
b542be46 127 void *oldcontext = m68ki_cpu_p; \\r
128 m68k_set_context(&PicoCpuMM68k); \\r
129 m68k_set_irq(irq); \\r
130 m68k_set_context(oldcontext); \\r
131}\r
5fadfb1c 132#define SekIrqLevel (PicoCpuMM68k.int_level >> 8)\r
b542be46 133\r
cc68a136 134#endif\r
ef090115 135#endif // EMU_M68K\r
cc68a136 136\r
137extern int SekCycleCnt; // cycles done in this frame\r
138extern int SekCycleAim; // cycle aim\r
139extern unsigned int SekCycleCntT; // total cycle counter, updated once per frame\r
140\r
b8cbd802 141#define SekCyclesReset() { \\r
142 SekCycleCntT+=SekCycleAim; \\r
143 SekCycleCnt-=SekCycleAim; \\r
144 SekCycleAim=0; \\r
145}\r
cc68a136 146#define SekCyclesBurn(c) SekCycleCnt+=c\r
4b9c5888 147#define SekCyclesDone() (SekCycleAim-SekCyclesLeft) // number of cycles done in this frame (can be checked anywhere)\r
cc68a136 148#define SekCyclesDoneT() (SekCycleCntT+SekCyclesDone()) // total nuber of cycles done for this rom\r
19886062 149#define SekCyclesDoneT2() (SekCycleCntT + SekCycleCnt) // same as above but not from memhandlers\r
cc68a136 150\r
151#define SekEndRun(after) { \\r
ef090115 152 SekCycleCnt -= SekCyclesLeft - (after); \\r
153 if (SekCycleCnt < 0) SekCycleCnt = 0; \\r
154 SekEndTimeslice(after); \\r
cc68a136 155}\r
156\r
07ceafdb 157#define SekEndRunS68k(after) { \\r
158 SekCycleCntS68k -= SekCyclesLeftS68k - (after); \\r
159 if (SekCycleCntS68k < 0) SekCycleCntS68k = 0; \\r
160 SekEndTimesliceS68k(after); \\r
161}\r
162\r
cc68a136 163extern int SekCycleCntS68k;\r
164extern int SekCycleAimS68k;\r
165\r
bf5fbbb4 166#define SekCyclesResetS68k() { \\r
167 SekCycleCntS68k-=SekCycleAimS68k; \\r
168 SekCycleAimS68k=0; \\r
169}\r
7a1f6e45 170#define SekCyclesDoneS68k() (SekCycleAimS68k-SekCyclesLeftS68k)\r
cc68a136 171\r
03e4f2a3 172#ifdef EMU_CORE_DEBUG\r
99464b62 173extern int dbg_irq_level;\r
ef090115 174#undef SekEndTimeslice\r
2d0b15bb 175#undef SekCyclesBurn\r
176#undef SekEndRun\r
99464b62 177#undef SekInterrupt\r
ef090115 178#define SekEndTimeslice(c)\r
2270612a 179#define SekCyclesBurn(c) c\r
2d0b15bb 180#define SekEndRun(c)\r
99464b62 181#define SekInterrupt(irq) dbg_irq_level=irq\r
2d0b15bb 182#endif\r
cc68a136 183\r
b542be46 184// ----------------------- Z80 CPU -----------------------\r
185\r
b4db550e 186#if defined(_USE_DRZ80)\r
dca310c4 187#include "../cpu/DrZ80/drz80.h"\r
b542be46 188\r
189extern struct DrZ80 drZ80;\r
190\r
191#define z80_run(cycles) ((cycles) - DrZ80Run(&drZ80, cycles))\r
192#define z80_run_nr(cycles) DrZ80Run(&drZ80, cycles)\r
4936aac1 193#define z80_int() drZ80.Z80_IRQ = 1\r
4b9c5888 194\r
195#define z80_cyclesLeft drZ80.cycles\r
19954be1 196#define z80_pc() (drZ80.Z80PC - drZ80.Z80PC_BASE)\r
b542be46 197\r
198#elif defined(_USE_CZ80)\r
dca310c4 199#include "../cpu/cz80/cz80.h"\r
b542be46 200\r
201#define z80_run(cycles) Cz80_Exec(&CZ80, cycles)\r
202#define z80_run_nr(cycles) Cz80_Exec(&CZ80, cycles)\r
203#define z80_int() Cz80_Set_IRQ(&CZ80, 0, HOLD_LINE)\r
4b9c5888 204\r
205#define z80_cyclesLeft (CZ80.ICount - CZ80.ExtraCycles)\r
19954be1 206#define z80_pc() Cz80_Get_Reg(&CZ80, CZ80_PC)\r
b542be46 207\r
208#else\r
209\r
210#define z80_run(cycles) (cycles)\r
211#define z80_run_nr(cycles)\r
212#define z80_int()\r
b542be46 213\r
214#endif\r
215\r
b4db550e 216#define Z80_STATE_SIZE 0x60\r
217\r
4b9c5888 218extern int z80stopCycle; /* in 68k cycles */\r
219extern int z80_cycle_cnt; /* 'done' z80 cycles before z80_run() */\r
220extern int z80_cycle_aim;\r
221extern int z80_scanline;\r
222extern int z80_scanline_cycles; /* cycles done until z80_scanline */\r
223\r
224#define z80_resetCycles() \\r
225 z80_cycle_cnt = z80_cycle_aim = z80_scanline = z80_scanline_cycles = 0;\r
226\r
227#define z80_cyclesDone() \\r
228 (z80_cycle_aim - z80_cyclesLeft)\r
229\r
230#define cycles_68k_to_z80(x) ((x)*957 >> 11)\r
231\r
acd35d4c 232// ----------------------- SH2 CPU -----------------------\r
233\r
41397701 234#include "cpu/sh2/sh2.h"\r
acd35d4c 235\r
1d7a28a7 236extern SH2 sh2s[2];\r
237#define msh2 sh2s[0]\r
238#define ssh2 sh2s[1]\r
239\r
679af8a3 240#ifndef DRC_SH2\r
19886062 241# define sh2_end_run(sh2, after_) do { \\r
242 if ((sh2)->icount > (after_)) { \\r
f4c0720c 243 (sh2)->cycles_timeslice -= (sh2)->icount; \\r
19886062 244 (sh2)->icount = after_; \\r
a8fd6e37 245 } \\r
246} while (0)\r
19886062 247# define sh2_cycles_left(sh2) (sh2)->icount\r
6d797957 248# define sh2_pc(c) (c) ? ssh2.ppc : msh2.ppc\r
679af8a3 249#else\r
19886062 250# define sh2_end_run(sh2, after_) do { \\r
251 int left_ = (signed int)(sh2)->sr >> 12; \\r
252 if (left_ > (after_)) { \\r
253 (sh2)->cycles_timeslice -= left_; \\r
f4c0720c 254 (sh2)->sr &= 0xfff; \\r
19886062 255 (sh2)->sr |= (after_) << 12; \\r
a8fd6e37 256 } \\r
257} while (0)\r
19886062 258# define sh2_cycles_left(sh2) ((signed int)(sh2)->sr >> 12)\r
6d797957 259# define sh2_pc(c) (c) ? ssh2.pc : msh2.pc\r
679af8a3 260#endif\r
266c6afa 261\r
19886062 262#define sh2_cycles_done(sh2) ((int)(sh2)->cycles_timeslice - sh2_cycles_left(sh2))\r
a7f82a77 263#define sh2_cycles_done_t(sh2) \\r
264 ((sh2)->m68krcycles_done * 3 + sh2_cycles_done(sh2))\r
19886062 265#define sh2_cycles_done_m68k(sh2) \\r
266 ((sh2)->m68krcycles_done + (sh2_cycles_done(sh2) / 3))\r
267\r
4ea707e1 268#define sh2_reg(c, x) (c) ? ssh2.r[x] : msh2.r[x]\r
269#define sh2_gbr(c) (c) ? ssh2.gbr : msh2.gbr\r
270#define sh2_vbr(c) (c) ? ssh2.vbr : msh2.vbr\r
6add7875 271#define sh2_sr(c) (((c) ? ssh2.sr : msh2.sr) & 0xfff)\r
acd35d4c 272\r
83ff19ec 273#define sh2_set_gbr(c, v) \\r
274 { if (c) ssh2.gbr = v; else msh2.gbr = v; }\r
275#define sh2_set_vbr(c, v) \\r
276 { if (c) ssh2.vbr = v; else msh2.vbr = v; }\r
277\r
cc68a136 278// ---------------------------------------------------------\r
279\r
280// main oscillator clock which controls timing\r
281#define OSC_NTSC 53693100\r
b8cbd802 282#define OSC_PAL 53203424\r
cc68a136 283\r
284struct PicoVideo\r
285{\r
286 unsigned char reg[0x20];\r
b8cbd802 287 unsigned int command; // 32-bit Command\r
288 unsigned char pending; // 1 if waiting for second half of 32-bit command\r
289 unsigned char type; // Command type (v/c/vsram read/write)\r
290 unsigned short addr; // Read/Write address\r
291 int status; // Status bits\r
cc68a136 292 unsigned char pending_ints; // pending interrupts: ??VH????\r
b8cbd802 293 signed char lwrite_cnt; // VDP write count during active display line\r
9761a7d0 294 unsigned short v_counter; // V-counter\r
295 unsigned char pad[0x10];\r
cc68a136 296};\r
297\r
298struct PicoMisc\r
299{\r
300 unsigned char rotate;\r
301 unsigned char z80Run;\r
e5503e2f 302 unsigned char padTHPhase[2]; // 02 phase of gamepad TH switches\r
2aa27095 303 unsigned short scanline; // 04 0 to 261||311\r
e5503e2f 304 char dirtyPal; // 06 Is the palette dirty (1 - change @ this frame, 2 - some time before)\r
305 unsigned char hardware; // 07 Hardware value for country\r
306 unsigned char pal; // 08 1=PAL 0=NTSC\r
45f2f245 307 unsigned char sram_reg; // 09 SRAM reg. See SRR_* below\r
e5503e2f 308 unsigned short z80_bank68k; // 0a\r
be2c4208 309 unsigned short pad0;\r
310 unsigned char pad1;\r
0ace9b9a 311 unsigned char z80_reset; // 0f z80 reset held\r
e5503e2f 312 unsigned char padDelay[2]; // 10 gamepad phase time outs, so we count a delay\r
1dceadae 313 unsigned short eeprom_addr; // EEPROM address register\r
45f2f245 314 unsigned char eeprom_cycle; // EEPROM cycle number\r
1dceadae 315 unsigned char eeprom_slave; // EEPROM slave word for X24C02 and better SRAMs\r
45f2f245 316 unsigned char eeprom_status;\r
be2c4208 317 unsigned char pad2;\r
053fd9b4 318 unsigned short dma_xfers; // 18\r
45f2f245 319 unsigned char eeprom_wb[2]; // EEPROM latch/write buffer\r
053fd9b4 320 unsigned int frame_count; // 1c for movies and idle det\r
cc68a136 321};\r
322\r
b4db550e 323struct PicoMS\r
324{\r
325 unsigned char carthw[0x10];\r
326 unsigned char io_ctl;\r
327 unsigned char pad[0x4f];\r
328};\r
329\r
cc68a136 330// some assembly stuff depend on these, do not touch!\r
331struct Pico\r
332{\r
333 unsigned char ram[0x10000]; // 0x00000 scratch ram\r
200772b7 334 union { // vram is byteswapped for easier reads when drawing\r
2ec9bec5 335 unsigned short vram[0x8000]; // 0x10000\r
336 unsigned char vramb[0x4000]; // VRAM in SMS mode\r
337 };\r
cc68a136 338 unsigned char zram[0x2000]; // 0x20000 Z80 ram\r
b4db550e 339 unsigned char ioports[0x10]; // XXX: fix asm and mv\r
340 unsigned char pad[0xf0]; // unused\r
cc68a136 341 unsigned short cram[0x40]; // 0x22100\r
342 unsigned short vsram[0x40]; // 0x22180\r
343\r
344 unsigned char *rom; // 0x22200\r
345 unsigned int romsize; // 0x22204\r
346\r
347 struct PicoMisc m;\r
348 struct PicoVideo video;\r
b4db550e 349 struct PicoMS ms;\r
cc68a136 350};\r
351\r
352// sram\r
45f2f245 353#define SRR_MAPPED (1 << 0)\r
354#define SRR_READONLY (1 << 1)\r
355\r
356#define SRF_ENABLED (1 << 0)\r
357#define SRF_EEPROM (1 << 1)\r
af37bca8 358\r
cc68a136 359struct PicoSRAM\r
360{\r
4ff2d527 361 unsigned char *data; // actual data\r
362 unsigned int start; // start address in 68k address space\r
cc68a136 363 unsigned int end;\r
45f2f245 364 unsigned char flags; // 0c: SRF_*\r
1dceadae 365 unsigned char unused2;\r
cc68a136 366 unsigned char changed;\r
45f2f245 367 unsigned char eeprom_type; // eeprom type: 0: 7bit (24C01), 2: 2 addr words (X24C02+), 3: 3 addr words\r
368 unsigned char unused3;\r
1dceadae 369 unsigned char eeprom_bit_cl; // bit number for cl\r
370 unsigned char eeprom_bit_in; // bit number for in\r
371 unsigned char eeprom_bit_out; // bit number for out\r
45f2f245 372 unsigned int size;\r
cc68a136 373};\r
374\r
375// MCD\r
376#include "cd/cd_sys.h"\r
377#include "cd/LC89510.h"\r
d1df8786 378#include "cd/gfx_cd.h"\r
cc68a136 379\r
4f265db7 380struct mcd_pcm\r
381{\r
382 unsigned char control; // reg7\r
383 unsigned char enabled; // reg8\r
384 unsigned char cur_ch;\r
385 unsigned char bank;\r
386 int pad1;\r
387\r
4ff2d527 388 struct pcm_chan // 08, size 0x10\r
4f265db7 389 {\r
390 unsigned char regs[8];\r
4ff2d527 391 unsigned int addr; // .08: played sample address\r
4f265db7 392 int pad;\r
393 } ch[8];\r
394};\r
395\r
c459aefd 396struct mcd_misc\r
397{\r
398 unsigned short hint_vector;\r
399 unsigned char busreq;\r
51a902ae 400 unsigned char s68k_pend_ints;\r
ef090115 401 unsigned int state_flags; // 04: emu state: reset_pending\r
51a902ae 402 unsigned int counter75hz;\r
c9e1affc 403 unsigned int pad0;\r
4ff2d527 404 int timer_int3; // 10\r
4f265db7 405 unsigned int timer_stopwatch;\r
6cadc2da 406 unsigned char bcram_reg; // 18: battery-backed RAM cart register\r
407 unsigned char pad2;\r
408 unsigned short pad3;\r
409 int pad[9];\r
c459aefd 410};\r
411\r
cc68a136 412typedef struct\r
413{\r
4ff2d527 414 unsigned char bios[0x20000]; // 000000: 128K\r
415 union { // 020000: 512K\r
fa1e5e29 416 unsigned char prg_ram[0x80000];\r
cc68a136 417 unsigned char prg_ram_b[4][0x20000];\r
418 };\r
4ff2d527 419 union { // 0a0000: 256K\r
fa1e5e29 420 struct {\r
421 unsigned char word_ram2M[0x40000];\r
dca310c4 422 unsigned char unused0[0x20000];\r
fa1e5e29 423 };\r
424 struct {\r
dca310c4 425 unsigned char unused1[0x20000];\r
fa1e5e29 426 unsigned char word_ram1M[2][0x20000];\r
427 };\r
428 };\r
4ff2d527 429 union { // 100000: 64K\r
fa1e5e29 430 unsigned char pcm_ram[0x10000];\r
4f265db7 431 unsigned char pcm_ram_b[0x10][0x1000];\r
432 };\r
4ff2d527 433 unsigned char s68k_regs[0x200]; // 110000: GA, not CPU regs\r
434 unsigned char bram[0x2000]; // 110200: 8K\r
435 struct mcd_misc m; // 112200: misc\r
436 struct mcd_pcm pcm; // 112240:\r
75736070 437 _scd_toc TOC; // not to be saved\r
cc68a136 438 CDD cdd;\r
439 CDC cdc;\r
440 _scd scd;\r
d1df8786 441 Rot_Comp rot_comp;\r
cc68a136 442} mcd_state;\r
443\r
be2c4208 444// XXX: this will need to be reworked for cart+cd support.\r
cc68a136 445#define Pico_mcd ((mcd_state *)Pico.rom)\r
446\r
be2c4208 447// 32X\r
acd35d4c 448#define P32XS_FM (1<<15)\r
83ff19ec 449#define P32XS_REN (1<< 7)\r
450#define P32XS_nRES (1<< 1)\r
451#define P32XS_ADEN (1<< 0)\r
acd35d4c 452#define P32XS2_ADEN (1<< 9)\r
5e128c6d 453#define P32XS_FULL (1<< 7) // DREQ FIFO full\r
4ea707e1 454#define P32XS_68S (1<< 2)\r
97d3f47f 455#define P32XS_DMA (1<< 1)\r
4ea707e1 456#define P32XS_RV (1<< 0)\r
acd35d4c 457\r
5e128c6d 458#define P32XV_nPAL (1<<15) // VDP\r
acd35d4c 459#define P32XV_PRI (1<< 7)\r
4ea707e1 460#define P32XV_Mx (3<< 0) // display mode mask\r
974fdb5b 461\r
e51e5983 462#define P32XV_SFT (1<< 0)\r
463\r
acd35d4c 464#define P32XV_VBLK (1<<15)\r
465#define P32XV_HBLK (1<<14)\r
466#define P32XV_PEN (1<<13)\r
467#define P32XV_nFEN (1<< 1)\r
468#define P32XV_FS (1<< 0)\r
974fdb5b 469\r
db1d3564 470#define P32XP_FULL (1<<15) // PWM\r
471#define P32XP_EMPTY (1<<14)\r
472\r
19886062 473#define P32XF_68KCPOLL (1 << 0)\r
474#define P32XF_68KVPOLL (1 << 1)\r
a8fd6e37 475#define P32XF_PWM_PEND (1 << 6)\r
4ea707e1 476\r
477#define P32XI_VRES (1 << 14/2) // IRL/2\r
478#define P32XI_VINT (1 << 12/2)\r
479#define P32XI_HINT (1 << 10/2)\r
480#define P32XI_CMD (1 << 8/2)\r
481#define P32XI_PWM (1 << 6/2)\r
482\r
1d7a28a7 483// peripheral reg access\r
484#define PREG8(regs,offs) ((unsigned char *)regs)[offs ^ 3]\r
485\r
4ea707e1 486// real one is 4*2, but we use more because we don't lockstep\r
487#define DMAC_FIFO_LEN (4*4)\r
db1d3564 488#define PWM_BUFF_LEN 1024 // in one channel samples\r
266c6afa 489\r
f4bb5d6b 490#define SH2_DRCBLK_RAM_SHIFT 1\r
491#define SH2_DRCBLK_DA_SHIFT 1\r
492\r
e05b81fc 493#define SH2_WRITE_SHIFT 25\r
494\r
be2c4208 495struct Pico32x\r
496{\r
497 unsigned short regs[0x20];\r
5a681086 498 unsigned short vdp_regs[0x10]; // 0x40\r
499 unsigned short sh2_regs[3]; // 0x60\r
be2c4208 500 unsigned char pending_fb;\r
974fdb5b 501 unsigned char dirty_pal;\r
266c6afa 502 unsigned int emu_flags;\r
4ea707e1 503 unsigned char sh2irq_mask[2];\r
504 unsigned char sh2irqi[2]; // individual\r
505 unsigned int sh2irqs; // common irqs\r
506 unsigned short dmac_fifo[DMAC_FIFO_LEN];\r
507 unsigned int dmac_ptr;\r
db1d3564 508 unsigned int pwm_irq_sample_cnt;\r
a8fd6e37 509 unsigned char comm_dirty_68k;\r
510 unsigned char comm_dirty_sh2;\r
511 unsigned short pad;\r
a7f82a77 512 unsigned short pwm_p[2]; // pwm pos in fifo\r
513 unsigned int pwm_cycle_p; // pwm play cursor (32x cycles)\r
514 unsigned int reserved[6];\r
974fdb5b 515};\r
516\r
517struct Pico32xMem\r
518{\r
519 unsigned char sdram[0x40000];\r
f4bb5d6b 520#ifdef DRC_SH2\r
521 unsigned short drcblk_ram[1 << (18 - SH2_DRCBLK_RAM_SHIFT)];\r
522#endif\r
b78efee2 523 unsigned short dram[2][0x20000/2]; // AKA fb\r
b4db550e 524 union {\r
525 unsigned char m68k_rom[0x100];\r
526 unsigned char m68k_rom_bank[0x10000]; // M68K_BANK_SIZE\r
527 };\r
b78efee2 528 unsigned char data_array[2][0x1000]; // cache in SH2s (can be used as RAM)\r
f4bb5d6b 529#ifdef DRC_SH2\r
530 unsigned short drcblk_da[2][1 << (12 - SH2_DRCBLK_DA_SHIFT)];\r
531#endif\r
acd35d4c 532 unsigned char sh2_rom_m[0x800];\r
533 unsigned char sh2_rom_s[0x400];\r
974fdb5b 534 unsigned short pal[0x100];\r
5e128c6d 535 unsigned short pal_native[0x100]; // converted to native (for renderer)\r
4ea707e1 536 unsigned int sh2_peri_regs[2][0x200/4]; // periphereal regs of SH2s\r
db1d3564 537 signed short pwm[2*PWM_BUFF_LEN]; // PWM buffer for current frame\r
a7f82a77 538 signed short pwm_fifo[2][4]; // [0] - current, others - fifo entries\r
be2c4208 539};\r
d49b10c2 540\r
c8d1e9b6 541// area.c\r
fad24893 542extern void (*PicoLoadStateHook)(void);\r
51a902ae 543\r
945c2fdc 544typedef struct {\r
545 int chunk;\r
546 int size;\r
547 void *ptr;\r
548} carthw_state_chunk;\r
549extern carthw_state_chunk *carthw_chunks;\r
550#define CHUNK_CARTHW 64\r
551\r
c8d1e9b6 552// cart.c\r
b4db550e 553extern int PicoCartResize(int newsize);\r
554extern void Byteswap(void *dst, const void *src, int len);\r
45f2f245 555extern void (*PicoCartMemSetup)(void);\r
e807ac75 556extern void (*PicoCartUnloadHook)(void);\r
1dceadae 557\r
c8d1e9b6 558// debug.c\r
b5e5172d 559int CM_compareRun(int cyc, int is_sub);\r
03e4f2a3 560\r
c8d1e9b6 561// draw.c\r
eff55556 562PICO_INTERNAL void PicoFrameStart(void);\r
b6d7ac70 563void PicoDrawSync(int to, int blank_last_line);\r
200772b7 564void BackFill(int reg7, int sh);\r
5a681086 565void FinalizeLine555(int sh, int line);\r
f4750ee0 566extern int (*PicoScanBegin)(unsigned int num);\r
567extern int (*PicoScanEnd)(unsigned int num);\r
b6d7ac70 568extern int DrawScanline;\r
f579f7b8 569#define MAX_LINE_SPRITES 29\r
570extern unsigned char HighLnSpr[240][3 + MAX_LINE_SPRITES];\r
5a681086 571extern void *DrawLineDestBase;\r
572extern int DrawLineDestIncrement;\r
cc68a136 573\r
c8d1e9b6 574// draw2.c\r
eff55556 575PICO_INTERNAL void PicoFrameFull();\r
cc68a136 576\r
200772b7 577// mode4.c\r
578void PicoFrameStartMode4(void);\r
579void PicoLineMode4(int line);\r
580void PicoDoHighPal555M4(void);\r
5a681086 581void PicoDrawSetOutputMode4(pdso_t which);\r
200772b7 582\r
c8d1e9b6 583// memory.c\r
eff55556 584PICO_INTERNAL void PicoMemSetup(void);\r
af37bca8 585unsigned int PicoRead8_io(unsigned int a);\r
586unsigned int PicoRead16_io(unsigned int a);\r
587void PicoWrite8_io(unsigned int a, unsigned int d);\r
588void PicoWrite16_io(unsigned int a, unsigned int d);\r
589\r
590// pico/memory.c\r
591PICO_INTERNAL void PicoMemSetupPico(void);\r
cc68a136 592\r
c8d1e9b6 593// cd/memory.c\r
eff55556 594PICO_INTERNAL void PicoMemSetupCD(void);\r
0ace9b9a 595void PicoMemStateLoaded(void);\r
cc68a136 596\r
c8d1e9b6 597// pico.c\r
cc68a136 598extern struct Pico Pico;\r
599extern struct PicoSRAM SRam;\r
5f9a0d16 600extern int PicoPadInt[2];\r
cc68a136 601extern int emustatus;\r
5e128c6d 602extern int scanlines_total;\r
f8ef8ff7 603extern void (*PicoResetHook)(void);\r
b0677887 604extern void (*PicoLineHook)(void);\r
1e6b5e39 605PICO_INTERNAL int CheckDMA(void);\r
606PICO_INTERNAL void PicoDetectRegion(void);\r
4b9c5888 607PICO_INTERNAL void PicoSyncZ80(int m68k_cycles_done);\r
cc68a136 608\r
c8d1e9b6 609// cd/pico.c\r
2aa27095 610PICO_INTERNAL void PicoInitMCD(void);\r
e5f426aa 611PICO_INTERNAL void PicoExitMCD(void);\r
1cb1584b 612PICO_INTERNAL void PicoPowerMCD(void);\r
2aa27095 613PICO_INTERNAL int PicoResetMCD(void);\r
614PICO_INTERNAL void PicoFrameMCD(void);\r
cc68a136 615\r
c8d1e9b6 616// pico/pico.c\r
2aa27095 617PICO_INTERNAL void PicoInitPico(void);\r
ed367a3f 618PICO_INTERNAL void PicoReratePico(void);\r
9037e45d 619\r
c8d1e9b6 620// pico/xpcm.c\r
ef4eb506 621PICO_INTERNAL void PicoPicoPCMUpdate(short *buffer, int length, int stereo);\r
622PICO_INTERNAL void PicoPicoPCMReset(void);\r
213c16ad 623PICO_INTERNAL void PicoPicoPCMRerate(int xpcm_rate);\r
ef4eb506 624\r
c8d1e9b6 625// sek.c\r
2aa27095 626PICO_INTERNAL void SekInit(void);\r
627PICO_INTERNAL int SekReset(void);\r
3aa1e148 628PICO_INTERNAL void SekState(int *data);\r
eff55556 629PICO_INTERNAL void SekSetRealTAS(int use_real);\r
b4db550e 630PICO_INTERNAL void SekPackCpu(unsigned char *cpu, int is_sub);\r
631PICO_INTERNAL void SekUnpackCpu(const unsigned char *cpu, int is_sub);\r
5f9a0d16 632void SekStepM68k(void);\r
053fd9b4 633void SekInitIdleDet(void);\r
634void SekFinishIdleDet(void);\r
cc68a136 635\r
c8d1e9b6 636// cd/sek.c\r
2aa27095 637PICO_INTERNAL void SekInitS68k(void);\r
638PICO_INTERNAL int SekResetS68k(void);\r
639PICO_INTERNAL int SekInterruptS68k(int irq);\r
cc68a136 640\r
7a93adeb 641// sound/sound.c\r
c9e1affc 642PICO_INTERNAL void cdda_start_play();\r
643extern short cdda_out_buffer[2*1152];\r
7a93adeb 644extern int PsndLen_exc_cnt;\r
645extern int PsndLen_exc_add;\r
48dc74f2 646extern int timer_a_next_oflow, timer_a_step; // in z80 cycles\r
647extern int timer_b_next_oflow, timer_b_step;\r
43e6eaad 648\r
649void ym2612_sync_timers(int z80_cycles, int mode_old, int mode_new);\r
d2721b08 650void ym2612_pack_state(void);\r
453d2a6e 651void ym2612_unpack_state(void);\r
4b9c5888 652\r
e53704e6 653#define TIMER_NO_OFLOW 0x70000000\r
45a1ef71 654// tA = 72 * (1024 - NA) / M\r
655#define TIMER_A_TICK_ZCYCLES 17203\r
656// tB = 1152 * (256 - NA) / M\r
657#define TIMER_B_TICK_ZCYCLES 262800 // 275251 broken, see Dai Makaimura\r
e53704e6 658\r
4b9c5888 659#define timers_cycle() \\r
e53704e6 660 if (timer_a_next_oflow > 0 && timer_a_next_oflow < TIMER_NO_OFLOW) \\r
43e6eaad 661 timer_a_next_oflow -= Pico.m.pal ? 70938*256 : 59659*256; \\r
e53704e6 662 if (timer_b_next_oflow > 0 && timer_b_next_oflow < TIMER_NO_OFLOW) \\r
43e6eaad 663 timer_b_next_oflow -= Pico.m.pal ? 70938*256 : 59659*256; \\r
664 ym2612_sync_timers(0, ym2612.OPN.ST.mode, ym2612.OPN.ST.mode);\r
4b9c5888 665\r
666#define timers_reset() \\r
e53704e6 667 timer_a_next_oflow = timer_b_next_oflow = TIMER_NO_OFLOW; \\r
48dc74f2 668 timer_a_step = TIMER_A_TICK_ZCYCLES * 1024; \\r
669 timer_b_step = TIMER_B_TICK_ZCYCLES * 256;\r
43e6eaad 670\r
7a93adeb 671\r
c8d1e9b6 672// videoport.c\r
eff55556 673PICO_INTERNAL_ASM void PicoVideoWrite(unsigned int a,unsigned short d);\r
674PICO_INTERNAL_ASM unsigned int PicoVideoRead(unsigned int a);\r
9761a7d0 675PICO_INTERNAL_ASM unsigned int PicoVideoRead8(unsigned int a);\r
5de27868 676extern int (*PicoDmaHook)(unsigned int source, int len, unsigned short **srcp, unsigned short **limitp);\r
cc68a136 677\r
c8d1e9b6 678// misc.c\r
eff55556 679PICO_INTERNAL_ASM void memcpy16(unsigned short *dest, unsigned short *src, int count);\r
680PICO_INTERNAL_ASM void memcpy16bswap(unsigned short *dest, void *src, int count);\r
681PICO_INTERNAL_ASM void memcpy32(int *dest, int *src, int count); // 32bit word count\r
682PICO_INTERNAL_ASM void memset32(int *dest, int c, int count);\r
cc68a136 683\r
45f2f245 684// eeprom.c\r
685void EEPROM_write8(unsigned int a, unsigned int d);\r
686void EEPROM_write16(unsigned int d);\r
687unsigned int EEPROM_read(void);\r
688\r
c8d1e9b6 689// z80 functionality wrappers\r
690PICO_INTERNAL void z80_init(void);\r
b4db550e 691PICO_INTERNAL void z80_pack(void *data);\r
692PICO_INTERNAL int z80_unpack(const void *data);\r
c8d1e9b6 693PICO_INTERNAL void z80_reset(void);\r
694PICO_INTERNAL void z80_exit(void);\r
c8d1e9b6 695\r
696// cd/misc.c\r
eff55556 697PICO_INTERNAL_ASM void wram_2M_to_1M(unsigned char *m);\r
698PICO_INTERNAL_ASM void wram_1M_to_2M(unsigned char *m);\r
699\r
700// cd/buffering.c\r
701PICO_INTERNAL void PicoCDBufferRead(void *dest, int lba);\r
702\r
703// sound/sound.c\r
9d917eea 704PICO_INTERNAL void PsndReset(void);\r
4b9c5888 705PICO_INTERNAL void PsndDoDAC(int line_to);\r
9d917eea 706PICO_INTERNAL void PsndClear(void);\r
7b3f44c6 707PICO_INTERNAL void PsndGetSamples(int y);\r
2ec9bec5 708PICO_INTERNAL void PsndGetSamplesMS(void);\r
4b9c5888 709extern int PsndDacLine;\r
cc68a136 710\r
3e49ffd0 711// sms.c\r
f3a57b2d 712#ifndef NO_SMS\r
3e49ffd0 713void PicoPowerMS(void);\r
2ec9bec5 714void PicoResetMS(void);\r
3e49ffd0 715void PicoMemSetupMS(void);\r
b4db550e 716void PicoStateLoadedMS(void);\r
3e49ffd0 717void PicoFrameMS(void);\r
87b0845f 718void PicoFrameDrawOnlyMS(void);\r
f3a57b2d 719#else\r
720#define PicoPowerMS()\r
721#define PicoResetMS()\r
722#define PicoMemSetupMS()\r
723#define PicoStateLoadedMS()\r
724#define PicoFrameMS()\r
725#define PicoFrameDrawOnlyMS()\r
726#endif\r
3e49ffd0 727\r
be2c4208 728// 32x/32x.c\r
f3a57b2d 729#ifndef NO_32X\r
be2c4208 730extern struct Pico32x Pico32x;\r
6a98f03e 731enum p32x_event {\r
732 P32X_EVENT_PWM,\r
733 P32X_EVENT_FILLEND,\r
734 P32X_EVENT_COUNT,\r
735};\r
736extern unsigned int event_times[P32X_EVENT_COUNT];\r
737\r
be2c4208 738void Pico32xInit(void);\r
974fdb5b 739void PicoPower32x(void);\r
be2c4208 740void PicoReset32x(void);\r
974fdb5b 741void Pico32xStartup(void);\r
5e49c3a8 742void PicoUnload32x(void);\r
974fdb5b 743void PicoFrame32x(void);\r
27e26273 744void Pico32xStateLoaded(int is_early);\r
ed4402a7 745void p32x_sync_sh2s(unsigned int m68k_target);\r
19886062 746void p32x_sync_other_sh2(SH2 *sh2, unsigned int m68k_target);\r
747void p32x_update_irls(SH2 *active_sh2);\r
83ff19ec 748void p32x_reset_sh2s(void);\r
19886062 749void p32x_event_schedule(unsigned int now, enum p32x_event event, int after);\r
750void p32x_event_schedule_sh2(SH2 *sh2, enum p32x_event event, int after);\r
a8fd6e37 751\r
be2c4208 752// 32x/memory.c\r
974fdb5b 753struct Pico32xMem *Pico32xMem;\r
be2c4208 754unsigned int PicoRead8_32x(unsigned int a);\r
755unsigned int PicoRead16_32x(unsigned int a);\r
756void PicoWrite8_32x(unsigned int a, unsigned int d);\r
757void PicoWrite16_32x(unsigned int a, unsigned int d);\r
758void PicoMemSetup32x(void);\r
974fdb5b 759void Pico32xSwapDRAM(int b);\r
27e26273 760void Pico32xMemStateLoaded(void);\r
19886062 761void p32x_m68k_poll_event(unsigned int flags);\r
762void p32x_sh2_poll_event(SH2 *sh2, unsigned int flags, unsigned int m68k_cycles);\r
974fdb5b 763\r
764// 32x/draw.c\r
41946d70 765void PicoDrawSetOutFormat32x(pdso_t which, int use_32x_line_mode);\r
974fdb5b 766void FinalizeLine32xRGB555(int sh, int line);\r
5a681086 767void PicoDraw32xLayer(int offs, int lines, int mdbg);\r
7a961c19 768void PicoDraw32xLayerMdOnly(int offs, int lines);\r
f4750ee0 769extern int (*PicoScan32xBegin)(unsigned int num);\r
770extern int (*PicoScan32xEnd)(unsigned int num);\r
7a961c19 771enum {\r
772 PDM32X_OFF,\r
773 PDM32X_32X_ONLY,\r
774 PDM32X_BOTH,\r
775};\r
5a681086 776extern int Pico32xDrawMode;\r
be2c4208 777\r
db1d3564 778// 32x/pwm.c\r
a7f82a77 779unsigned int p32x_pwm_read16(unsigned int a, unsigned int cycles);\r
780void p32x_pwm_write16(unsigned int a, unsigned int d, unsigned int cycles);\r
db1d3564 781void p32x_pwm_update(int *buf32, int length, int stereo);\r
a7f82a77 782void p32x_timers_do(unsigned int m68k_now, unsigned int m68k_slice);\r
1d7a28a7 783void p32x_timers_recalc(void);\r
a8fd6e37 784void p32x_pwm_schedule(unsigned int now);\r
19886062 785void p32x_pwm_schedule_sh2(SH2 *sh2);\r
f3a57b2d 786#else\r
787#define Pico32xInit()\r
788#define PicoPower32x()\r
789#define PicoReset32x()\r
790#define PicoFrame32x()\r
791#define PicoUnload32x()\r
792#define Pico32xStateLoaded()\r
f3a57b2d 793#define FinalizeLine32xRGB555 NULL\r
794#define p32x_pwm_update(...)\r
795#define p32x_timers_recalc()\r
796#endif\r
db1d3564 797\r
45f2f245 798/* avoid dependency on newer glibc */\r
799static __inline int isspace_(int c)\r
800{\r
801 return (0x09 <= c && c <= 0x0d) || c == ' ';\r
802}\r
803\r
f4bb5d6b 804#ifndef ARRAY_SIZE\r
805#define ARRAY_SIZE(x) (sizeof(x) / sizeof(x[0]))\r
806#endif\r
807\r
b8cbd802 808// emulation event logging\r
809#ifndef EL_LOGMASK\r
9c9cda8c 810# ifdef __x86_64__ // HACK\r
811# define EL_LOGMASK (EL_STATUS|EL_IDLE|EL_ANOMALY)\r
812# else\r
1555935b 813# define EL_LOGMASK (EL_STATUS)\r
9c9cda8c 814# endif\r
b8cbd802 815#endif\r
816\r
017512f2 817#define EL_HVCNT 0x00000001 /* hv counter reads */\r
818#define EL_SR 0x00000002 /* SR reads */\r
819#define EL_INTS 0x00000004 /* ints and acks */\r
43e6eaad 820#define EL_YMTIMER 0x00000008 /* ym2612 timer stuff */\r
017512f2 821#define EL_INTSW 0x00000010 /* log irq switching on/off */\r
822#define EL_ASVDP 0x00000020 /* VDP accesses during active scan */\r
823#define EL_VDPDMA 0x00000040 /* VDP DMA transfers and their timing */\r
824#define EL_BUSREQ 0x00000080 /* z80 busreq r/w or reset w */\r
825#define EL_Z80BNK 0x00000100 /* z80 i/o through bank area */\r
826#define EL_SRAMIO 0x00000200 /* sram i/o */\r
827#define EL_EEPROM 0x00000400 /* eeprom debug */\r
828#define EL_UIO 0x00000800 /* unmapped i/o */\r
829#define EL_IO 0x00001000 /* all i/o */\r
830#define EL_CDPOLL 0x00002000 /* MCD: log poll detection */\r
831#define EL_SVP 0x00004000 /* SVP stuff */\r
fa22af4c 832#define EL_PICOHW 0x00008000 /* Pico stuff */\r
053fd9b4 833#define EL_IDLE 0x00010000 /* idle loop det. */\r
af37bca8 834#define EL_CDREGS 0x00020000 /* MCD: register access */\r
835#define EL_CDREG3 0x00040000 /* MCD: register 3 only */\r
be2c4208 836#define EL_32X 0x00080000\r
1b3f5844 837#define EL_PWM 0x00100000 /* 32X PWM stuff (LOTS of output) */\r
017512f2 838\r
839#define EL_STATUS 0x40000000 /* status messages */\r
840#define EL_ANOMALY 0x80000000 /* some unexpected conditions (during emulation) */\r
b8cbd802 841\r
842#if EL_LOGMASK\r
843#define elprintf(w,f,...) \\r
a8fd6e37 844do { \\r
b8cbd802 845 if ((w) & EL_LOGMASK) \\r
7d0143a2 846 lprintf("%05i:%03i: " f "\n",Pico.m.frame_count,Pico.m.scanline,##__VA_ARGS__); \\r
a8fd6e37 847} while (0)\r
dca310c4 848#elif defined(_MSC_VER)\r
849#define elprintf\r
b8cbd802 850#else\r
851#define elprintf(w,f,...)\r
852#endif\r
853\r
f6c49d38 854// profiling\r
855#ifdef PPROF\r
856#include <platform/linux/pprof.h>\r
857#else\r
858#define pprof_init()\r
859#define pprof_finish()\r
860#define pprof_start(x)\r
861#define pprof_end(...)\r
862#define pprof_end_sub(...)\r
863#endif\r
864\r
19886062 865#ifdef EVT_LOG\r
866enum evt {\r
867 EVT_FRAME_START,\r
868 EVT_NEXT_LINE,\r
869 EVT_RUN_START,\r
870 EVT_RUN_END,\r
871 EVT_POLL_START,\r
872 EVT_POLL_END,\r
873 EVT_CNT\r
874};\r
875\r
876enum evt_cpu {\r
877 EVT_M68K,\r
878 EVT_S68K,\r
879 EVT_MSH2,\r
880 EVT_SSH2,\r
881 EVT_CPU_CNT\r
882};\r
883\r
884void pevt_log(unsigned int cycles, enum evt_cpu c, enum evt e);\r
885void pevt_dump(void);\r
886\r
887#define pevt_log_m68k(e) \\r
888 pevt_log(SekCyclesDoneT(), EVT_M68K, e)\r
889#define pevt_log_m68k_o(e) \\r
890 pevt_log(SekCyclesDoneT2(), EVT_M68K, e)\r
891#define pevt_log_sh2(sh2, e) \\r
892 pevt_log(sh2_cycles_done_m68k(sh2), EVT_MSH2 + (sh2)->is_slave, e)\r
893#define pevt_log_sh2_o(sh2, e) \\r
894 pevt_log((sh2)->m68krcycles_done, EVT_MSH2 + (sh2)->is_slave, e)\r
895#else\r
896#define pevt_log(c, e)\r
897#define pevt_log_m68k(e)\r
898#define pevt_log_m68k_o(e)\r
899#define pevt_log_sh2(sh2, e)\r
900#define pevt_log_sh2_o(sh2, e)\r
901#define pevt_dump()\r
902#endif\r
903\r
f6c49d38 904// misc\r
dca310c4 905#ifdef _MSC_VER\r
906#define cdprintf\r
907#else\r
908#define cdprintf(x...)\r
909#endif\r
910\r
553c3eaa 911#ifdef __i386__\r
912#define REGPARM(x) __attribute__((regparm(x)))\r
c8d1e9b6 913#else\r
553c3eaa 914#define REGPARM(x)\r
c8d1e9b6 915#endif\r
916\r
5e89f0f5 917#ifdef __GNUC__\r
918#define NOINLINE __attribute__((noinline))\r
919#else\r
920#define NOINLINE\r
921#endif\r
922\r
f8af9634 923#ifdef __cplusplus\r
924} // End of extern "C"\r
925#endif\r
926\r
eff55556 927#endif // PICO_INTERNAL_INCLUDED\r
928\r
fast MegaDrive/MegaCD/32X emulator