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57871462 | 1 | /* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * |
2 | * Mupen64plus - new_dynarec.c * | |
20d507ba | 3 | * Copyright (C) 2009-2011 Ari64 * |
57871462 | 4 | * * |
5 | * This program is free software; you can redistribute it and/or modify * | |
6 | * it under the terms of the GNU General Public License as published by * | |
7 | * the Free Software Foundation; either version 2 of the License, or * | |
8 | * (at your option) any later version. * | |
9 | * * | |
10 | * This program is distributed in the hope that it will be useful, * | |
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of * | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * | |
13 | * GNU General Public License for more details. * | |
14 | * * | |
15 | * You should have received a copy of the GNU General Public License * | |
16 | * along with this program; if not, write to the * | |
17 | * Free Software Foundation, Inc., * | |
18 | * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * | |
19 | * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */ | |
20 | ||
21 | #include <stdlib.h> | |
22 | #include <stdint.h> //include for uint64_t | |
23 | #include <assert.h> | |
d848b60a | 24 | #include <errno.h> |
4600ba03 | 25 | #include <sys/mman.h> |
57871462 | 26 | |
3d624f89 | 27 | #include "emu_if.h" //emulator interface |
57871462 | 28 | |
4600ba03 | 29 | //#define DISASM |
30 | //#define assem_debug printf | |
31 | //#define inv_debug printf | |
32 | #define assem_debug(...) | |
33 | #define inv_debug(...) | |
57871462 | 34 | |
35 | #ifdef __i386__ | |
36 | #include "assem_x86.h" | |
37 | #endif | |
38 | #ifdef __x86_64__ | |
39 | #include "assem_x64.h" | |
40 | #endif | |
41 | #ifdef __arm__ | |
42 | #include "assem_arm.h" | |
43 | #endif | |
44 | ||
f23d3386 | 45 | #ifdef __BLACKBERRY_QNX__ |
a4874585 C |
46 | #undef __clear_cache |
47 | #define __clear_cache(start,end) msync(start, (size_t)((void*)end - (void*)start), MS_SYNC | MS_CACHE_ONLY | MS_INVALIDATE_ICACHE); | |
c7b746f0 | 48 | #elif defined(__MACH__) |
49 | #include <libkern/OSCacheControl.h> | |
50 | #define __clear_cache mach_clear_cache | |
51 | static void __clear_cache(void *start, void *end) { | |
52 | size_t len = (char *)end - (char *)start; | |
53 | sys_dcache_flush(start, len); | |
54 | sys_icache_invalidate(start, len); | |
55 | } | |
f23d3386 | 56 | #endif |
a4874585 | 57 | |
57871462 | 58 | #define MAXBLOCK 4096 |
59 | #define MAX_OUTPUT_BLOCK_SIZE 262144 | |
2573466a | 60 | |
57871462 | 61 | struct regstat |
62 | { | |
63 | signed char regmap_entry[HOST_REGS]; | |
64 | signed char regmap[HOST_REGS]; | |
65 | uint64_t was32; | |
66 | uint64_t is32; | |
67 | uint64_t wasdirty; | |
68 | uint64_t dirty; | |
69 | uint64_t u; | |
70 | uint64_t uu; | |
71 | u_int wasconst; | |
72 | u_int isconst; | |
8575a877 | 73 | u_int loadedconst; // host regs that have constants loaded |
74 | u_int waswritten; // MIPS regs that were used as store base before | |
57871462 | 75 | }; |
76 | ||
de5a60c3 | 77 | // note: asm depends on this layout |
57871462 | 78 | struct ll_entry |
79 | { | |
80 | u_int vaddr; | |
de5a60c3 | 81 | u_int reg_sv_flags; |
57871462 | 82 | void *addr; |
83 | struct ll_entry *next; | |
84 | }; | |
85 | ||
e2b5e7aa | 86 | // used by asm: |
87 | u_char *out; | |
88 | u_int hash_table[65536][4] __attribute__((aligned(16))); | |
89 | struct ll_entry *jump_in[4096] __attribute__((aligned(16))); | |
90 | struct ll_entry *jump_dirty[4096]; | |
91 | ||
92 | static struct ll_entry *jump_out[4096]; | |
93 | static u_int start; | |
94 | static u_int *source; | |
95 | static char insn[MAXBLOCK][10]; | |
96 | static u_char itype[MAXBLOCK]; | |
97 | static u_char opcode[MAXBLOCK]; | |
98 | static u_char opcode2[MAXBLOCK]; | |
99 | static u_char bt[MAXBLOCK]; | |
100 | static u_char rs1[MAXBLOCK]; | |
101 | static u_char rs2[MAXBLOCK]; | |
102 | static u_char rt1[MAXBLOCK]; | |
103 | static u_char rt2[MAXBLOCK]; | |
104 | static u_char us1[MAXBLOCK]; | |
105 | static u_char us2[MAXBLOCK]; | |
106 | static u_char dep1[MAXBLOCK]; | |
107 | static u_char dep2[MAXBLOCK]; | |
108 | static u_char lt1[MAXBLOCK]; | |
bedfea38 | 109 | static uint64_t gte_rs[MAXBLOCK]; // gte: 32 data and 32 ctl regs |
110 | static uint64_t gte_rt[MAXBLOCK]; | |
111 | static uint64_t gte_unneeded[MAXBLOCK]; | |
ffb0b9e0 | 112 | static u_int smrv[32]; // speculated MIPS register values |
113 | static u_int smrv_strong; // mask or regs that are likely to have correct values | |
114 | static u_int smrv_weak; // same, but somewhat less likely | |
115 | static u_int smrv_strong_next; // same, but after current insn executes | |
116 | static u_int smrv_weak_next; | |
e2b5e7aa | 117 | static int imm[MAXBLOCK]; |
118 | static u_int ba[MAXBLOCK]; | |
119 | static char likely[MAXBLOCK]; | |
120 | static char is_ds[MAXBLOCK]; | |
121 | static char ooo[MAXBLOCK]; | |
122 | static uint64_t unneeded_reg[MAXBLOCK]; | |
123 | static uint64_t unneeded_reg_upper[MAXBLOCK]; | |
124 | static uint64_t branch_unneeded_reg[MAXBLOCK]; | |
125 | static uint64_t branch_unneeded_reg_upper[MAXBLOCK]; | |
126 | static signed char regmap_pre[MAXBLOCK][HOST_REGS]; | |
956f3129 | 127 | static uint64_t current_constmap[HOST_REGS]; |
128 | static uint64_t constmap[MAXBLOCK][HOST_REGS]; | |
129 | static struct regstat regs[MAXBLOCK]; | |
130 | static struct regstat branch_regs[MAXBLOCK]; | |
e2b5e7aa | 131 | static signed char minimum_free_regs[MAXBLOCK]; |
132 | static u_int needed_reg[MAXBLOCK]; | |
133 | static u_int wont_dirty[MAXBLOCK]; | |
134 | static u_int will_dirty[MAXBLOCK]; | |
135 | static int ccadj[MAXBLOCK]; | |
136 | static int slen; | |
137 | static u_int instr_addr[MAXBLOCK]; | |
138 | static u_int link_addr[MAXBLOCK][3]; | |
139 | static int linkcount; | |
140 | static u_int stubs[MAXBLOCK*3][8]; | |
141 | static int stubcount; | |
142 | static u_int literals[1024][2]; | |
143 | static int literalcount; | |
144 | static int is_delayslot; | |
145 | static int cop1_usable; | |
146 | static char shadow[1048576] __attribute__((aligned(16))); | |
147 | static void *copy; | |
148 | static int expirep; | |
149 | static u_int stop_after_jal; | |
a327ad27 | 150 | #ifndef RAM_FIXED |
151 | static u_int ram_offset; | |
152 | #else | |
153 | static const u_int ram_offset=0; | |
154 | #endif | |
e2b5e7aa | 155 | |
156 | int new_dynarec_hacks; | |
157 | int new_dynarec_did_compile; | |
57871462 | 158 | extern u_char restore_candidate[512]; |
159 | extern int cycle_count; | |
160 | ||
161 | /* registers that may be allocated */ | |
162 | /* 1-31 gpr */ | |
163 | #define HIREG 32 // hi | |
164 | #define LOREG 33 // lo | |
165 | #define FSREG 34 // FPU status (FCSR) | |
166 | #define CSREG 35 // Coprocessor status | |
167 | #define CCREG 36 // Cycle count | |
168 | #define INVCP 37 // Pointer to invalid_code | |
1edfcc68 | 169 | //#define MMREG 38 // Pointer to memory_map |
619e5ded | 170 | #define ROREG 39 // ram offset (if rdram!=0x80000000) |
171 | #define TEMPREG 40 | |
172 | #define FTEMP 40 // FPU temporary register | |
173 | #define PTEMP 41 // Prefetch temporary register | |
1edfcc68 | 174 | //#define TLREG 42 // TLB mapping offset |
619e5ded | 175 | #define RHASH 43 // Return address hash |
176 | #define RHTBL 44 // Return address hash table address | |
177 | #define RTEMP 45 // JR/JALR address register | |
178 | #define MAXREG 45 | |
179 | #define AGEN1 46 // Address generation temporary register | |
1edfcc68 | 180 | //#define AGEN2 47 // Address generation temporary register |
181 | //#define MGEN1 48 // Maptable address generation temporary register | |
182 | //#define MGEN2 49 // Maptable address generation temporary register | |
619e5ded | 183 | #define BTREG 50 // Branch target temporary register |
57871462 | 184 | |
185 | /* instruction types */ | |
186 | #define NOP 0 // No operation | |
187 | #define LOAD 1 // Load | |
188 | #define STORE 2 // Store | |
189 | #define LOADLR 3 // Unaligned load | |
190 | #define STORELR 4 // Unaligned store | |
9f51b4b9 | 191 | #define MOV 5 // Move |
57871462 | 192 | #define ALU 6 // Arithmetic/logic |
193 | #define MULTDIV 7 // Multiply/divide | |
194 | #define SHIFT 8 // Shift by register | |
195 | #define SHIFTIMM 9// Shift by immediate | |
196 | #define IMM16 10 // 16-bit immediate | |
197 | #define RJUMP 11 // Unconditional jump to register | |
198 | #define UJUMP 12 // Unconditional jump | |
199 | #define CJUMP 13 // Conditional branch (BEQ/BNE/BGTZ/BLEZ) | |
200 | #define SJUMP 14 // Conditional branch (regimm format) | |
201 | #define COP0 15 // Coprocessor 0 | |
202 | #define COP1 16 // Coprocessor 1 | |
203 | #define C1LS 17 // Coprocessor 1 load/store | |
204 | #define FJUMP 18 // Conditional branch (floating point) | |
205 | #define FLOAT 19 // Floating point unit | |
206 | #define FCONV 20 // Convert integer to float | |
207 | #define FCOMP 21 // Floating point compare (sets FSREG) | |
208 | #define SYSCALL 22// SYSCALL | |
209 | #define OTHER 23 // Other | |
210 | #define SPAN 24 // Branch/delay slot spans 2 pages | |
211 | #define NI 25 // Not implemented | |
7139f3c8 | 212 | #define HLECALL 26// PCSX fake opcodes for HLE |
b9b61529 | 213 | #define COP2 27 // Coprocessor 2 move |
214 | #define C2LS 28 // Coprocessor 2 load/store | |
215 | #define C2OP 29 // Coprocessor 2 operation | |
1e973cb0 | 216 | #define INTCALL 30// Call interpreter to handle rare corner cases |
57871462 | 217 | |
218 | /* stubs */ | |
219 | #define CC_STUB 1 | |
220 | #define FP_STUB 2 | |
221 | #define LOADB_STUB 3 | |
222 | #define LOADH_STUB 4 | |
223 | #define LOADW_STUB 5 | |
224 | #define LOADD_STUB 6 | |
225 | #define LOADBU_STUB 7 | |
226 | #define LOADHU_STUB 8 | |
227 | #define STOREB_STUB 9 | |
228 | #define STOREH_STUB 10 | |
229 | #define STOREW_STUB 11 | |
230 | #define STORED_STUB 12 | |
231 | #define STORELR_STUB 13 | |
232 | #define INVCODE_STUB 14 | |
233 | ||
234 | /* branch codes */ | |
235 | #define TAKEN 1 | |
236 | #define NOTTAKEN 2 | |
237 | #define NULLDS 3 | |
238 | ||
239 | // asm linkage | |
240 | int new_recompile_block(int addr); | |
241 | void *get_addr_ht(u_int vaddr); | |
242 | void invalidate_block(u_int block); | |
243 | void invalidate_addr(u_int addr); | |
244 | void remove_hash(int vaddr); | |
57871462 | 245 | void dyna_linker(); |
246 | void dyna_linker_ds(); | |
247 | void verify_code(); | |
248 | void verify_code_vm(); | |
249 | void verify_code_ds(); | |
250 | void cc_interrupt(); | |
251 | void fp_exception(); | |
252 | void fp_exception_ds(); | |
7139f3c8 | 253 | void jump_syscall_hle(); |
7139f3c8 | 254 | void jump_hlecall(); |
1e973cb0 | 255 | void jump_intcall(); |
7139f3c8 | 256 | void new_dyna_leave(); |
57871462 | 257 | |
57871462 | 258 | // Needed by assembler |
e2b5e7aa | 259 | static void wb_register(signed char r,signed char regmap[],uint64_t dirty,uint64_t is32); |
260 | static void wb_dirtys(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty); | |
261 | static void wb_needed_dirtys(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr); | |
262 | static void load_all_regs(signed char i_regmap[]); | |
263 | static void load_needed_regs(signed char i_regmap[],signed char next_regmap[]); | |
264 | static void load_regs_entry(int t); | |
265 | static void load_all_consts(signed char regmap[],int is32,u_int dirty,int i); | |
266 | ||
267 | static int verify_dirty(u_int *ptr); | |
268 | static int get_final_value(int hr, int i, int *value); | |
269 | static void add_stub(int type,int addr,int retaddr,int a,int b,int c,int d,int e); | |
270 | static void add_to_linker(int addr,int target,int ext); | |
57871462 | 271 | |
e2b5e7aa | 272 | static int tracedebug=0; |
57871462 | 273 | |
274 | //#define DEBUG_CYCLE_COUNT 1 | |
275 | ||
b6e87b2b | 276 | #define NO_CYCLE_PENALTY_THR 12 |
277 | ||
4e9dcd7f | 278 | int cycle_multiplier; // 100 for 1.0 |
279 | ||
280 | static int CLOCK_ADJUST(int x) | |
281 | { | |
282 | int s=(x>>31)|1; | |
283 | return (x * cycle_multiplier + s * 50) / 100; | |
284 | } | |
285 | ||
94d23bb9 | 286 | static u_int get_page(u_int vaddr) |
57871462 | 287 | { |
0ce47d46 | 288 | u_int page=vaddr&~0xe0000000; |
289 | if (page < 0x1000000) | |
290 | page &= ~0x0e00000; // RAM mirrors | |
291 | page>>=12; | |
57871462 | 292 | if(page>2048) page=2048+(page&2047); |
94d23bb9 | 293 | return page; |
294 | } | |
295 | ||
d25604ca | 296 | // no virtual mem in PCSX |
297 | static u_int get_vpage(u_int vaddr) | |
298 | { | |
299 | return get_page(vaddr); | |
300 | } | |
94d23bb9 | 301 | |
302 | // Get address from virtual address | |
303 | // This is called from the recompiled JR/JALR instructions | |
304 | void *get_addr(u_int vaddr) | |
305 | { | |
306 | u_int page=get_page(vaddr); | |
307 | u_int vpage=get_vpage(vaddr); | |
57871462 | 308 | struct ll_entry *head; |
309 | //printf("TRACE: count=%d next=%d (get_addr %x,page %d)\n",Count,next_interupt,vaddr,page); | |
310 | head=jump_in[page]; | |
311 | while(head!=NULL) { | |
de5a60c3 | 312 | if(head->vaddr==vaddr) { |
57871462 | 313 | //printf("TRACE: count=%d next=%d (get_addr match %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr); |
581335b0 | 314 | u_int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF]; |
57871462 | 315 | ht_bin[3]=ht_bin[1]; |
316 | ht_bin[2]=ht_bin[0]; | |
581335b0 | 317 | ht_bin[1]=(u_int)head->addr; |
57871462 | 318 | ht_bin[0]=vaddr; |
319 | return head->addr; | |
320 | } | |
321 | head=head->next; | |
322 | } | |
323 | head=jump_dirty[vpage]; | |
324 | while(head!=NULL) { | |
de5a60c3 | 325 | if(head->vaddr==vaddr) { |
57871462 | 326 | //printf("TRACE: count=%d next=%d (get_addr match dirty %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr); |
327 | // Don't restore blocks which are about to expire from the cache | |
328 | if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2))) | |
329 | if(verify_dirty(head->addr)) { | |
330 | //printf("restore candidate: %x (%d) d=%d\n",vaddr,page,invalid_code[vaddr>>12]); | |
331 | invalid_code[vaddr>>12]=0; | |
9be4ba64 | 332 | inv_code_start=inv_code_end=~0; |
57871462 | 333 | if(vpage<2048) { |
57871462 | 334 | restore_candidate[vpage>>3]|=1<<(vpage&7); |
335 | } | |
336 | else restore_candidate[page>>3]|=1<<(page&7); | |
581335b0 | 337 | u_int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF]; |
57871462 | 338 | if(ht_bin[0]==vaddr) { |
581335b0 | 339 | ht_bin[1]=(u_int)head->addr; // Replace existing entry |
57871462 | 340 | } |
341 | else | |
342 | { | |
343 | ht_bin[3]=ht_bin[1]; | |
344 | ht_bin[2]=ht_bin[0]; | |
345 | ht_bin[1]=(int)head->addr; | |
346 | ht_bin[0]=vaddr; | |
347 | } | |
348 | return head->addr; | |
349 | } | |
350 | } | |
351 | head=head->next; | |
352 | } | |
353 | //printf("TRACE: count=%d next=%d (get_addr no-match %x)\n",Count,next_interupt,vaddr); | |
354 | int r=new_recompile_block(vaddr); | |
355 | if(r==0) return get_addr(vaddr); | |
356 | // Execute in unmapped page, generate pagefault execption | |
357 | Status|=2; | |
358 | Cause=(vaddr<<31)|0x8; | |
359 | EPC=(vaddr&1)?vaddr-5:vaddr; | |
360 | BadVAddr=(vaddr&~1); | |
361 | Context=(Context&0xFF80000F)|((BadVAddr>>9)&0x007FFFF0); | |
362 | EntryHi=BadVAddr&0xFFFFE000; | |
363 | return get_addr_ht(0x80000000); | |
364 | } | |
365 | // Look up address in hash table first | |
366 | void *get_addr_ht(u_int vaddr) | |
367 | { | |
368 | //printf("TRACE: count=%d next=%d (get_addr_ht %x)\n",Count,next_interupt,vaddr); | |
581335b0 | 369 | u_int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF]; |
57871462 | 370 | if(ht_bin[0]==vaddr) return (void *)ht_bin[1]; |
371 | if(ht_bin[2]==vaddr) return (void *)ht_bin[3]; | |
372 | return get_addr(vaddr); | |
373 | } | |
374 | ||
57871462 | 375 | void clear_all_regs(signed char regmap[]) |
376 | { | |
377 | int hr; | |
378 | for (hr=0;hr<HOST_REGS;hr++) regmap[hr]=-1; | |
379 | } | |
380 | ||
381 | signed char get_reg(signed char regmap[],int r) | |
382 | { | |
383 | int hr; | |
384 | for (hr=0;hr<HOST_REGS;hr++) if(hr!=EXCLUDE_REG&®map[hr]==r) return hr; | |
385 | return -1; | |
386 | } | |
387 | ||
388 | // Find a register that is available for two consecutive cycles | |
389 | signed char get_reg2(signed char regmap1[],signed char regmap2[],int r) | |
390 | { | |
391 | int hr; | |
392 | for (hr=0;hr<HOST_REGS;hr++) if(hr!=EXCLUDE_REG&®map1[hr]==r&®map2[hr]==r) return hr; | |
393 | return -1; | |
394 | } | |
395 | ||
396 | int count_free_regs(signed char regmap[]) | |
397 | { | |
398 | int count=0; | |
399 | int hr; | |
400 | for(hr=0;hr<HOST_REGS;hr++) | |
401 | { | |
402 | if(hr!=EXCLUDE_REG) { | |
403 | if(regmap[hr]<0) count++; | |
404 | } | |
405 | } | |
406 | return count; | |
407 | } | |
408 | ||
409 | void dirty_reg(struct regstat *cur,signed char reg) | |
410 | { | |
411 | int hr; | |
412 | if(!reg) return; | |
413 | for (hr=0;hr<HOST_REGS;hr++) { | |
414 | if((cur->regmap[hr]&63)==reg) { | |
415 | cur->dirty|=1<<hr; | |
416 | } | |
417 | } | |
418 | } | |
419 | ||
420 | // If we dirty the lower half of a 64 bit register which is now being | |
421 | // sign-extended, we need to dump the upper half. | |
422 | // Note: Do this only after completion of the instruction, because | |
423 | // some instructions may need to read the full 64-bit value even if | |
424 | // overwriting it (eg SLTI, DSRA32). | |
425 | static void flush_dirty_uppers(struct regstat *cur) | |
426 | { | |
427 | int hr,reg; | |
428 | for (hr=0;hr<HOST_REGS;hr++) { | |
429 | if((cur->dirty>>hr)&1) { | |
430 | reg=cur->regmap[hr]; | |
9f51b4b9 | 431 | if(reg>=64) |
57871462 | 432 | if((cur->is32>>(reg&63))&1) cur->regmap[hr]=-1; |
433 | } | |
434 | } | |
435 | } | |
436 | ||
437 | void set_const(struct regstat *cur,signed char reg,uint64_t value) | |
438 | { | |
439 | int hr; | |
440 | if(!reg) return; | |
441 | for (hr=0;hr<HOST_REGS;hr++) { | |
442 | if(cur->regmap[hr]==reg) { | |
443 | cur->isconst|=1<<hr; | |
956f3129 | 444 | current_constmap[hr]=value; |
57871462 | 445 | } |
446 | else if((cur->regmap[hr]^64)==reg) { | |
447 | cur->isconst|=1<<hr; | |
956f3129 | 448 | current_constmap[hr]=value>>32; |
57871462 | 449 | } |
450 | } | |
451 | } | |
452 | ||
453 | void clear_const(struct regstat *cur,signed char reg) | |
454 | { | |
455 | int hr; | |
456 | if(!reg) return; | |
457 | for (hr=0;hr<HOST_REGS;hr++) { | |
458 | if((cur->regmap[hr]&63)==reg) { | |
459 | cur->isconst&=~(1<<hr); | |
460 | } | |
461 | } | |
462 | } | |
463 | ||
464 | int is_const(struct regstat *cur,signed char reg) | |
465 | { | |
466 | int hr; | |
79c75f1b | 467 | if(reg<0) return 0; |
57871462 | 468 | if(!reg) return 1; |
469 | for (hr=0;hr<HOST_REGS;hr++) { | |
470 | if((cur->regmap[hr]&63)==reg) { | |
471 | return (cur->isconst>>hr)&1; | |
472 | } | |
473 | } | |
474 | return 0; | |
475 | } | |
476 | uint64_t get_const(struct regstat *cur,signed char reg) | |
477 | { | |
478 | int hr; | |
479 | if(!reg) return 0; | |
480 | for (hr=0;hr<HOST_REGS;hr++) { | |
481 | if(cur->regmap[hr]==reg) { | |
956f3129 | 482 | return current_constmap[hr]; |
57871462 | 483 | } |
484 | } | |
c43b5311 | 485 | SysPrintf("Unknown constant in r%d\n",reg); |
57871462 | 486 | exit(1); |
487 | } | |
488 | ||
489 | // Least soon needed registers | |
490 | // Look at the next ten instructions and see which registers | |
491 | // will be used. Try not to reallocate these. | |
492 | void lsn(u_char hsn[], int i, int *preferred_reg) | |
493 | { | |
494 | int j; | |
495 | int b=-1; | |
496 | for(j=0;j<9;j++) | |
497 | { | |
498 | if(i+j>=slen) { | |
499 | j=slen-i-1; | |
500 | break; | |
501 | } | |
502 | if(itype[i+j]==UJUMP||itype[i+j]==RJUMP||(source[i+j]>>16)==0x1000) | |
503 | { | |
504 | // Don't go past an unconditonal jump | |
505 | j++; | |
506 | break; | |
507 | } | |
508 | } | |
509 | for(;j>=0;j--) | |
510 | { | |
511 | if(rs1[i+j]) hsn[rs1[i+j]]=j; | |
512 | if(rs2[i+j]) hsn[rs2[i+j]]=j; | |
513 | if(rt1[i+j]) hsn[rt1[i+j]]=j; | |
514 | if(rt2[i+j]) hsn[rt2[i+j]]=j; | |
515 | if(itype[i+j]==STORE || itype[i+j]==STORELR) { | |
516 | // Stores can allocate zero | |
517 | hsn[rs1[i+j]]=j; | |
518 | hsn[rs2[i+j]]=j; | |
519 | } | |
520 | // On some architectures stores need invc_ptr | |
521 | #if defined(HOST_IMM8) | |
b9b61529 | 522 | if(itype[i+j]==STORE || itype[i+j]==STORELR || (opcode[i+j]&0x3b)==0x39 || (opcode[i+j]&0x3b)==0x3a) { |
57871462 | 523 | hsn[INVCP]=j; |
524 | } | |
525 | #endif | |
526 | if(i+j>=0&&(itype[i+j]==UJUMP||itype[i+j]==CJUMP||itype[i+j]==SJUMP||itype[i+j]==FJUMP)) | |
527 | { | |
528 | hsn[CCREG]=j; | |
529 | b=j; | |
530 | } | |
531 | } | |
532 | if(b>=0) | |
533 | { | |
534 | if(ba[i+b]>=start && ba[i+b]<(start+slen*4)) | |
535 | { | |
536 | // Follow first branch | |
537 | int t=(ba[i+b]-start)>>2; | |
538 | j=7-b;if(t+j>=slen) j=slen-t-1; | |
539 | for(;j>=0;j--) | |
540 | { | |
541 | if(rs1[t+j]) if(hsn[rs1[t+j]]>j+b+2) hsn[rs1[t+j]]=j+b+2; | |
542 | if(rs2[t+j]) if(hsn[rs2[t+j]]>j+b+2) hsn[rs2[t+j]]=j+b+2; | |
543 | //if(rt1[t+j]) if(hsn[rt1[t+j]]>j+b+2) hsn[rt1[t+j]]=j+b+2; | |
544 | //if(rt2[t+j]) if(hsn[rt2[t+j]]>j+b+2) hsn[rt2[t+j]]=j+b+2; | |
545 | } | |
546 | } | |
547 | // TODO: preferred register based on backward branch | |
548 | } | |
549 | // Delay slot should preferably not overwrite branch conditions or cycle count | |
550 | if(i>0&&(itype[i-1]==RJUMP||itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP)) { | |
551 | if(rs1[i-1]) if(hsn[rs1[i-1]]>1) hsn[rs1[i-1]]=1; | |
552 | if(rs2[i-1]) if(hsn[rs2[i-1]]>1) hsn[rs2[i-1]]=1; | |
553 | hsn[CCREG]=1; | |
554 | // ...or hash tables | |
555 | hsn[RHASH]=1; | |
556 | hsn[RHTBL]=1; | |
557 | } | |
558 | // Coprocessor load/store needs FTEMP, even if not declared | |
b9b61529 | 559 | if(itype[i]==C1LS||itype[i]==C2LS) { |
57871462 | 560 | hsn[FTEMP]=0; |
561 | } | |
562 | // Load L/R also uses FTEMP as a temporary register | |
563 | if(itype[i]==LOADLR) { | |
564 | hsn[FTEMP]=0; | |
565 | } | |
b7918751 | 566 | // Also SWL/SWR/SDL/SDR |
567 | if(opcode[i]==0x2a||opcode[i]==0x2e||opcode[i]==0x2c||opcode[i]==0x2d) { | |
57871462 | 568 | hsn[FTEMP]=0; |
569 | } | |
57871462 | 570 | // Don't remove the miniht registers |
571 | if(itype[i]==UJUMP||itype[i]==RJUMP) | |
572 | { | |
573 | hsn[RHASH]=0; | |
574 | hsn[RHTBL]=0; | |
575 | } | |
576 | } | |
577 | ||
578 | // We only want to allocate registers if we're going to use them again soon | |
579 | int needed_again(int r, int i) | |
580 | { | |
581 | int j; | |
582 | int b=-1; | |
583 | int rn=10; | |
9f51b4b9 | 584 | |
57871462 | 585 | if(i>0&&(itype[i-1]==UJUMP||itype[i-1]==RJUMP||(source[i-1]>>16)==0x1000)) |
586 | { | |
587 | if(ba[i-1]<start || ba[i-1]>start+slen*4-4) | |
588 | return 0; // Don't need any registers if exiting the block | |
589 | } | |
590 | for(j=0;j<9;j++) | |
591 | { | |
592 | if(i+j>=slen) { | |
593 | j=slen-i-1; | |
594 | break; | |
595 | } | |
596 | if(itype[i+j]==UJUMP||itype[i+j]==RJUMP||(source[i+j]>>16)==0x1000) | |
597 | { | |
598 | // Don't go past an unconditonal jump | |
599 | j++; | |
600 | break; | |
601 | } | |
1e973cb0 | 602 | if(itype[i+j]==SYSCALL||itype[i+j]==HLECALL||itype[i+j]==INTCALL||((source[i+j]&0xfc00003f)==0x0d)) |
57871462 | 603 | { |
604 | break; | |
605 | } | |
606 | } | |
607 | for(;j>=1;j--) | |
608 | { | |
609 | if(rs1[i+j]==r) rn=j; | |
610 | if(rs2[i+j]==r) rn=j; | |
611 | if((unneeded_reg[i+j]>>r)&1) rn=10; | |
612 | if(i+j>=0&&(itype[i+j]==UJUMP||itype[i+j]==CJUMP||itype[i+j]==SJUMP||itype[i+j]==FJUMP)) | |
613 | { | |
614 | b=j; | |
615 | } | |
616 | } | |
617 | /* | |
618 | if(b>=0) | |
619 | { | |
620 | if(ba[i+b]>=start && ba[i+b]<(start+slen*4)) | |
621 | { | |
622 | // Follow first branch | |
623 | int o=rn; | |
624 | int t=(ba[i+b]-start)>>2; | |
625 | j=7-b;if(t+j>=slen) j=slen-t-1; | |
626 | for(;j>=0;j--) | |
627 | { | |
628 | if(!((unneeded_reg[t+j]>>r)&1)) { | |
629 | if(rs1[t+j]==r) if(rn>j+b+2) rn=j+b+2; | |
630 | if(rs2[t+j]==r) if(rn>j+b+2) rn=j+b+2; | |
631 | } | |
632 | else rn=o; | |
633 | } | |
634 | } | |
635 | }*/ | |
b7217e13 | 636 | if(rn<10) return 1; |
581335b0 | 637 | (void)b; |
57871462 | 638 | return 0; |
639 | } | |
640 | ||
641 | // Try to match register allocations at the end of a loop with those | |
642 | // at the beginning | |
643 | int loop_reg(int i, int r, int hr) | |
644 | { | |
645 | int j,k; | |
646 | for(j=0;j<9;j++) | |
647 | { | |
648 | if(i+j>=slen) { | |
649 | j=slen-i-1; | |
650 | break; | |
651 | } | |
652 | if(itype[i+j]==UJUMP||itype[i+j]==RJUMP||(source[i+j]>>16)==0x1000) | |
653 | { | |
654 | // Don't go past an unconditonal jump | |
655 | j++; | |
656 | break; | |
657 | } | |
658 | } | |
659 | k=0; | |
660 | if(i>0){ | |
661 | if(itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP) | |
662 | k--; | |
663 | } | |
664 | for(;k<j;k++) | |
665 | { | |
666 | if(r<64&&((unneeded_reg[i+k]>>r)&1)) return hr; | |
667 | if(r>64&&((unneeded_reg_upper[i+k]>>r)&1)) return hr; | |
668 | if(i+k>=0&&(itype[i+k]==UJUMP||itype[i+k]==CJUMP||itype[i+k]==SJUMP||itype[i+k]==FJUMP)) | |
669 | { | |
670 | if(ba[i+k]>=start && ba[i+k]<(start+i*4)) | |
671 | { | |
672 | int t=(ba[i+k]-start)>>2; | |
673 | int reg=get_reg(regs[t].regmap_entry,r); | |
674 | if(reg>=0) return reg; | |
675 | //reg=get_reg(regs[t+1].regmap_entry,r); | |
676 | //if(reg>=0) return reg; | |
677 | } | |
678 | } | |
679 | } | |
680 | return hr; | |
681 | } | |
682 | ||
683 | ||
684 | // Allocate every register, preserving source/target regs | |
685 | void alloc_all(struct regstat *cur,int i) | |
686 | { | |
687 | int hr; | |
9f51b4b9 | 688 | |
57871462 | 689 | for(hr=0;hr<HOST_REGS;hr++) { |
690 | if(hr!=EXCLUDE_REG) { | |
691 | if(((cur->regmap[hr]&63)!=rs1[i])&&((cur->regmap[hr]&63)!=rs2[i])&& | |
692 | ((cur->regmap[hr]&63)!=rt1[i])&&((cur->regmap[hr]&63)!=rt2[i])) | |
693 | { | |
694 | cur->regmap[hr]=-1; | |
695 | cur->dirty&=~(1<<hr); | |
696 | } | |
697 | // Don't need zeros | |
698 | if((cur->regmap[hr]&63)==0) | |
699 | { | |
700 | cur->regmap[hr]=-1; | |
701 | cur->dirty&=~(1<<hr); | |
702 | } | |
703 | } | |
704 | } | |
705 | } | |
706 | ||
57871462 | 707 | #ifdef __i386__ |
708 | #include "assem_x86.c" | |
709 | #endif | |
710 | #ifdef __x86_64__ | |
711 | #include "assem_x64.c" | |
712 | #endif | |
713 | #ifdef __arm__ | |
714 | #include "assem_arm.c" | |
715 | #endif | |
716 | ||
717 | // Add virtual address mapping to linked list | |
718 | void ll_add(struct ll_entry **head,int vaddr,void *addr) | |
719 | { | |
720 | struct ll_entry *new_entry; | |
721 | new_entry=malloc(sizeof(struct ll_entry)); | |
722 | assert(new_entry!=NULL); | |
723 | new_entry->vaddr=vaddr; | |
de5a60c3 | 724 | new_entry->reg_sv_flags=0; |
57871462 | 725 | new_entry->addr=addr; |
726 | new_entry->next=*head; | |
727 | *head=new_entry; | |
728 | } | |
729 | ||
de5a60c3 | 730 | void ll_add_flags(struct ll_entry **head,int vaddr,u_int reg_sv_flags,void *addr) |
57871462 | 731 | { |
7139f3c8 | 732 | ll_add(head,vaddr,addr); |
de5a60c3 | 733 | (*head)->reg_sv_flags=reg_sv_flags; |
57871462 | 734 | } |
735 | ||
736 | // Check if an address is already compiled | |
737 | // but don't return addresses which are about to expire from the cache | |
738 | void *check_addr(u_int vaddr) | |
739 | { | |
740 | u_int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF]; | |
741 | if(ht_bin[0]==vaddr) { | |
742 | if(((ht_bin[1]-MAX_OUTPUT_BLOCK_SIZE-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2))) | |
743 | if(isclean(ht_bin[1])) return (void *)ht_bin[1]; | |
744 | } | |
745 | if(ht_bin[2]==vaddr) { | |
746 | if(((ht_bin[3]-MAX_OUTPUT_BLOCK_SIZE-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2))) | |
747 | if(isclean(ht_bin[3])) return (void *)ht_bin[3]; | |
748 | } | |
94d23bb9 | 749 | u_int page=get_page(vaddr); |
57871462 | 750 | struct ll_entry *head; |
751 | head=jump_in[page]; | |
752 | while(head!=NULL) { | |
de5a60c3 | 753 | if(head->vaddr==vaddr) { |
57871462 | 754 | if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2))) { |
755 | // Update existing entry with current address | |
756 | if(ht_bin[0]==vaddr) { | |
757 | ht_bin[1]=(int)head->addr; | |
758 | return head->addr; | |
759 | } | |
760 | if(ht_bin[2]==vaddr) { | |
761 | ht_bin[3]=(int)head->addr; | |
762 | return head->addr; | |
763 | } | |
764 | // Insert into hash table with low priority. | |
765 | // Don't evict existing entries, as they are probably | |
766 | // addresses that are being accessed frequently. | |
767 | if(ht_bin[0]==-1) { | |
768 | ht_bin[1]=(int)head->addr; | |
769 | ht_bin[0]=vaddr; | |
770 | }else if(ht_bin[2]==-1) { | |
771 | ht_bin[3]=(int)head->addr; | |
772 | ht_bin[2]=vaddr; | |
773 | } | |
774 | return head->addr; | |
775 | } | |
776 | } | |
777 | head=head->next; | |
778 | } | |
779 | return 0; | |
780 | } | |
781 | ||
782 | void remove_hash(int vaddr) | |
783 | { | |
784 | //printf("remove hash: %x\n",vaddr); | |
581335b0 | 785 | u_int *ht_bin=hash_table[(((vaddr)>>16)^vaddr)&0xFFFF]; |
57871462 | 786 | if(ht_bin[2]==vaddr) { |
787 | ht_bin[2]=ht_bin[3]=-1; | |
788 | } | |
789 | if(ht_bin[0]==vaddr) { | |
790 | ht_bin[0]=ht_bin[2]; | |
791 | ht_bin[1]=ht_bin[3]; | |
792 | ht_bin[2]=ht_bin[3]=-1; | |
793 | } | |
794 | } | |
795 | ||
796 | void ll_remove_matching_addrs(struct ll_entry **head,int addr,int shift) | |
797 | { | |
798 | struct ll_entry *next; | |
799 | while(*head) { | |
9f51b4b9 | 800 | if(((u_int)((*head)->addr)>>shift)==(addr>>shift) || |
57871462 | 801 | ((u_int)((*head)->addr-MAX_OUTPUT_BLOCK_SIZE)>>shift)==(addr>>shift)) |
802 | { | |
803 | inv_debug("EXP: Remove pointer to %x (%x)\n",(int)(*head)->addr,(*head)->vaddr); | |
804 | remove_hash((*head)->vaddr); | |
805 | next=(*head)->next; | |
806 | free(*head); | |
807 | *head=next; | |
808 | } | |
809 | else | |
810 | { | |
811 | head=&((*head)->next); | |
812 | } | |
813 | } | |
814 | } | |
815 | ||
816 | // Remove all entries from linked list | |
817 | void ll_clear(struct ll_entry **head) | |
818 | { | |
819 | struct ll_entry *cur; | |
820 | struct ll_entry *next; | |
581335b0 | 821 | if((cur=*head)) { |
57871462 | 822 | *head=0; |
823 | while(cur) { | |
824 | next=cur->next; | |
825 | free(cur); | |
826 | cur=next; | |
827 | } | |
828 | } | |
829 | } | |
830 | ||
831 | // Dereference the pointers and remove if it matches | |
832 | void ll_kill_pointers(struct ll_entry *head,int addr,int shift) | |
833 | { | |
834 | while(head) { | |
835 | int ptr=get_pointer(head->addr); | |
836 | inv_debug("EXP: Lookup pointer to %x at %x (%x)\n",(int)ptr,(int)head->addr,head->vaddr); | |
837 | if(((ptr>>shift)==(addr>>shift)) || | |
838 | (((ptr-MAX_OUTPUT_BLOCK_SIZE)>>shift)==(addr>>shift))) | |
839 | { | |
5088bb70 | 840 | inv_debug("EXP: Kill pointer at %x (%x)\n",(int)head->addr,head->vaddr); |
f76eeef9 | 841 | u_int host_addr=(u_int)kill_pointer(head->addr); |
dd3a91a1 | 842 | #ifdef __arm__ |
843 | needs_clear_cache[(host_addr-(u_int)BASE_ADDR)>>17]|=1<<(((host_addr-(u_int)BASE_ADDR)>>12)&31); | |
844 | #endif | |
57871462 | 845 | } |
846 | head=head->next; | |
847 | } | |
848 | } | |
849 | ||
850 | // This is called when we write to a compiled block (see do_invstub) | |
f76eeef9 | 851 | void invalidate_page(u_int page) |
57871462 | 852 | { |
57871462 | 853 | struct ll_entry *head; |
854 | struct ll_entry *next; | |
855 | head=jump_in[page]; | |
856 | jump_in[page]=0; | |
857 | while(head!=NULL) { | |
858 | inv_debug("INVALIDATE: %x\n",head->vaddr); | |
859 | remove_hash(head->vaddr); | |
860 | next=head->next; | |
861 | free(head); | |
862 | head=next; | |
863 | } | |
864 | head=jump_out[page]; | |
865 | jump_out[page]=0; | |
866 | while(head!=NULL) { | |
867 | inv_debug("INVALIDATE: kill pointer to %x (%x)\n",head->vaddr,(int)head->addr); | |
f76eeef9 | 868 | u_int host_addr=(u_int)kill_pointer(head->addr); |
dd3a91a1 | 869 | #ifdef __arm__ |
870 | needs_clear_cache[(host_addr-(u_int)BASE_ADDR)>>17]|=1<<(((host_addr-(u_int)BASE_ADDR)>>12)&31); | |
871 | #endif | |
57871462 | 872 | next=head->next; |
873 | free(head); | |
874 | head=next; | |
875 | } | |
57871462 | 876 | } |
9be4ba64 | 877 | |
878 | static void invalidate_block_range(u_int block, u_int first, u_int last) | |
57871462 | 879 | { |
94d23bb9 | 880 | u_int page=get_page(block<<12); |
57871462 | 881 | //printf("first=%d last=%d\n",first,last); |
f76eeef9 | 882 | invalidate_page(page); |
57871462 | 883 | assert(first+5>page); // NB: this assumes MAXBLOCK<=4096 (4 pages) |
884 | assert(last<page+5); | |
885 | // Invalidate the adjacent pages if a block crosses a 4K boundary | |
886 | while(first<page) { | |
887 | invalidate_page(first); | |
888 | first++; | |
889 | } | |
890 | for(first=page+1;first<last;first++) { | |
891 | invalidate_page(first); | |
892 | } | |
dd3a91a1 | 893 | #ifdef __arm__ |
894 | do_clear_cache(); | |
895 | #endif | |
9f51b4b9 | 896 | |
57871462 | 897 | // Don't trap writes |
898 | invalid_code[block]=1; | |
f76eeef9 | 899 | |
57871462 | 900 | #ifdef USE_MINI_HT |
901 | memset(mini_ht,-1,sizeof(mini_ht)); | |
902 | #endif | |
903 | } | |
9be4ba64 | 904 | |
905 | void invalidate_block(u_int block) | |
906 | { | |
907 | u_int page=get_page(block<<12); | |
908 | u_int vpage=get_vpage(block<<12); | |
909 | inv_debug("INVALIDATE: %x (%d)\n",block<<12,page); | |
910 | //inv_debug("invalid_code[block]=%d\n",invalid_code[block]); | |
911 | u_int first,last; | |
912 | first=last=page; | |
913 | struct ll_entry *head; | |
914 | head=jump_dirty[vpage]; | |
915 | //printf("page=%d vpage=%d\n",page,vpage); | |
916 | while(head!=NULL) { | |
917 | u_int start,end; | |
918 | if(vpage>2047||(head->vaddr>>12)==block) { // Ignore vaddr hash collision | |
919 | get_bounds((int)head->addr,&start,&end); | |
920 | //printf("start: %x end: %x\n",start,end); | |
4a35de07 | 921 | if(page<2048&&start>=(u_int)rdram&&end<(u_int)rdram+RAM_SIZE) { |
9be4ba64 | 922 | if(((start-(u_int)rdram)>>12)<=page&&((end-1-(u_int)rdram)>>12)>=page) { |
923 | if((((start-(u_int)rdram)>>12)&2047)<first) first=((start-(u_int)rdram)>>12)&2047; | |
924 | if((((end-1-(u_int)rdram)>>12)&2047)>last) last=((end-1-(u_int)rdram)>>12)&2047; | |
925 | } | |
926 | } | |
9be4ba64 | 927 | } |
928 | head=head->next; | |
929 | } | |
930 | invalidate_block_range(block,first,last); | |
931 | } | |
932 | ||
57871462 | 933 | void invalidate_addr(u_int addr) |
934 | { | |
9be4ba64 | 935 | //static int rhits; |
936 | // this check is done by the caller | |
937 | //if (inv_code_start<=addr&&addr<=inv_code_end) { rhits++; return; } | |
d25604ca | 938 | u_int page=get_vpage(addr); |
9be4ba64 | 939 | if(page<2048) { // RAM |
940 | struct ll_entry *head; | |
941 | u_int addr_min=~0, addr_max=0; | |
4a35de07 | 942 | u_int mask=RAM_SIZE-1; |
943 | u_int addr_main=0x80000000|(addr&mask); | |
9be4ba64 | 944 | int pg1; |
4a35de07 | 945 | inv_code_start=addr_main&~0xfff; |
946 | inv_code_end=addr_main|0xfff; | |
9be4ba64 | 947 | pg1=page; |
948 | if (pg1>0) { | |
949 | // must check previous page too because of spans.. | |
950 | pg1--; | |
951 | inv_code_start-=0x1000; | |
952 | } | |
953 | for(;pg1<=page;pg1++) { | |
954 | for(head=jump_dirty[pg1];head!=NULL;head=head->next) { | |
955 | u_int start,end; | |
956 | get_bounds((int)head->addr,&start,&end); | |
4a35de07 | 957 | if(ram_offset) { |
958 | start-=ram_offset; | |
959 | end-=ram_offset; | |
960 | } | |
961 | if(start<=addr_main&&addr_main<end) { | |
9be4ba64 | 962 | if(start<addr_min) addr_min=start; |
963 | if(end>addr_max) addr_max=end; | |
964 | } | |
4a35de07 | 965 | else if(addr_main<start) { |
9be4ba64 | 966 | if(start<inv_code_end) |
967 | inv_code_end=start-1; | |
968 | } | |
969 | else { | |
970 | if(end>inv_code_start) | |
971 | inv_code_start=end; | |
972 | } | |
973 | } | |
974 | } | |
975 | if (addr_min!=~0) { | |
976 | inv_debug("INV ADDR: %08x hit %08x-%08x\n", addr, addr_min, addr_max); | |
977 | inv_code_start=inv_code_end=~0; | |
978 | invalidate_block_range(addr>>12,(addr_min&mask)>>12,(addr_max&mask)>>12); | |
979 | return; | |
980 | } | |
981 | else { | |
4a35de07 | 982 | inv_code_start=(addr&~mask)|(inv_code_start&mask); |
983 | inv_code_end=(addr&~mask)|(inv_code_end&mask); | |
d25604ca | 984 | inv_debug("INV ADDR: %08x miss, inv %08x-%08x, sk %d\n", addr, inv_code_start, inv_code_end, 0); |
9be4ba64 | 985 | return; |
d25604ca | 986 | } |
9be4ba64 | 987 | } |
57871462 | 988 | invalidate_block(addr>>12); |
989 | } | |
9be4ba64 | 990 | |
dd3a91a1 | 991 | // This is called when loading a save state. |
992 | // Anything could have changed, so invalidate everything. | |
57871462 | 993 | void invalidate_all_pages() |
994 | { | |
581335b0 | 995 | u_int page; |
57871462 | 996 | for(page=0;page<4096;page++) |
997 | invalidate_page(page); | |
998 | for(page=0;page<1048576;page++) | |
999 | if(!invalid_code[page]) { | |
1000 | restore_candidate[(page&2047)>>3]|=1<<(page&7); | |
1001 | restore_candidate[((page&2047)>>3)+256]|=1<<(page&7); | |
1002 | } | |
57871462 | 1003 | #ifdef USE_MINI_HT |
1004 | memset(mini_ht,-1,sizeof(mini_ht)); | |
1005 | #endif | |
57871462 | 1006 | } |
1007 | ||
1008 | // Add an entry to jump_out after making a link | |
1009 | void add_link(u_int vaddr,void *src) | |
1010 | { | |
94d23bb9 | 1011 | u_int page=get_page(vaddr); |
57871462 | 1012 | inv_debug("add_link: %x -> %x (%d)\n",(int)src,vaddr,page); |
76f71c27 | 1013 | int *ptr=(int *)(src+4); |
1014 | assert((*ptr&0x0fff0000)==0x059f0000); | |
581335b0 | 1015 | (void)ptr; |
57871462 | 1016 | ll_add(jump_out+page,vaddr,src); |
1017 | //int ptr=get_pointer(src); | |
1018 | //inv_debug("add_link: Pointer is to %x\n",(int)ptr); | |
1019 | } | |
1020 | ||
1021 | // If a code block was found to be unmodified (bit was set in | |
1022 | // restore_candidate) and it remains unmodified (bit is clear | |
1023 | // in invalid_code) then move the entries for that 4K page from | |
1024 | // the dirty list to the clean list. | |
1025 | void clean_blocks(u_int page) | |
1026 | { | |
1027 | struct ll_entry *head; | |
1028 | inv_debug("INV: clean_blocks page=%d\n",page); | |
1029 | head=jump_dirty[page]; | |
1030 | while(head!=NULL) { | |
1031 | if(!invalid_code[head->vaddr>>12]) { | |
1032 | // Don't restore blocks which are about to expire from the cache | |
1033 | if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2))) { | |
1034 | u_int start,end; | |
581335b0 | 1035 | if(verify_dirty(head->addr)) { |
57871462 | 1036 | //printf("Possibly Restore %x (%x)\n",head->vaddr, (int)head->addr); |
1037 | u_int i; | |
1038 | u_int inv=0; | |
1039 | get_bounds((int)head->addr,&start,&end); | |
4cb76aa4 | 1040 | if(start-(u_int)rdram<RAM_SIZE) { |
57871462 | 1041 | for(i=(start-(u_int)rdram+0x80000000)>>12;i<=(end-1-(u_int)rdram+0x80000000)>>12;i++) { |
1042 | inv|=invalid_code[i]; | |
1043 | } | |
1044 | } | |
4cb76aa4 | 1045 | else if((signed int)head->vaddr>=(signed int)0x80000000+RAM_SIZE) { |
57871462 | 1046 | inv=1; |
1047 | } | |
1048 | if(!inv) { | |
1049 | void * clean_addr=(void *)get_clean_addr((int)head->addr); | |
1050 | if((((u_int)clean_addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2))) { | |
1051 | u_int ppage=page; | |
57871462 | 1052 | inv_debug("INV: Restored %x (%x/%x)\n",head->vaddr, (int)head->addr, (int)clean_addr); |
1053 | //printf("page=%x, addr=%x\n",page,head->vaddr); | |
1054 | //assert(head->vaddr>>12==(page|0x80000)); | |
de5a60c3 | 1055 | ll_add_flags(jump_in+ppage,head->vaddr,head->reg_sv_flags,clean_addr); |
581335b0 | 1056 | u_int *ht_bin=hash_table[((head->vaddr>>16)^head->vaddr)&0xFFFF]; |
de5a60c3 | 1057 | if(ht_bin[0]==head->vaddr) { |
581335b0 | 1058 | ht_bin[1]=(u_int)clean_addr; // Replace existing entry |
de5a60c3 | 1059 | } |
1060 | if(ht_bin[2]==head->vaddr) { | |
581335b0 | 1061 | ht_bin[3]=(u_int)clean_addr; // Replace existing entry |
57871462 | 1062 | } |
1063 | } | |
1064 | } | |
1065 | } | |
1066 | } | |
1067 | } | |
1068 | head=head->next; | |
1069 | } | |
1070 | } | |
1071 | ||
1072 | ||
1073 | void mov_alloc(struct regstat *current,int i) | |
1074 | { | |
1075 | // Note: Don't need to actually alloc the source registers | |
1076 | if((~current->is32>>rs1[i])&1) { | |
1077 | //alloc_reg64(current,i,rs1[i]); | |
1078 | alloc_reg64(current,i,rt1[i]); | |
1079 | current->is32&=~(1LL<<rt1[i]); | |
1080 | } else { | |
1081 | //alloc_reg(current,i,rs1[i]); | |
1082 | alloc_reg(current,i,rt1[i]); | |
1083 | current->is32|=(1LL<<rt1[i]); | |
1084 | } | |
1085 | clear_const(current,rs1[i]); | |
1086 | clear_const(current,rt1[i]); | |
1087 | dirty_reg(current,rt1[i]); | |
1088 | } | |
1089 | ||
1090 | void shiftimm_alloc(struct regstat *current,int i) | |
1091 | { | |
57871462 | 1092 | if(opcode2[i]<=0x3) // SLL/SRL/SRA |
1093 | { | |
1094 | if(rt1[i]) { | |
1095 | if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]); | |
1096 | else lt1[i]=rs1[i]; | |
1097 | alloc_reg(current,i,rt1[i]); | |
1098 | current->is32|=1LL<<rt1[i]; | |
1099 | dirty_reg(current,rt1[i]); | |
dc49e339 | 1100 | if(is_const(current,rs1[i])) { |
1101 | int v=get_const(current,rs1[i]); | |
1102 | if(opcode2[i]==0x00) set_const(current,rt1[i],v<<imm[i]); | |
1103 | if(opcode2[i]==0x02) set_const(current,rt1[i],(u_int)v>>imm[i]); | |
1104 | if(opcode2[i]==0x03) set_const(current,rt1[i],v>>imm[i]); | |
1105 | } | |
1106 | else clear_const(current,rt1[i]); | |
57871462 | 1107 | } |
1108 | } | |
dc49e339 | 1109 | else |
1110 | { | |
1111 | clear_const(current,rs1[i]); | |
1112 | clear_const(current,rt1[i]); | |
1113 | } | |
1114 | ||
57871462 | 1115 | if(opcode2[i]>=0x38&&opcode2[i]<=0x3b) // DSLL/DSRL/DSRA |
1116 | { | |
1117 | if(rt1[i]) { | |
1118 | if(rs1[i]) alloc_reg64(current,i,rs1[i]); | |
1119 | alloc_reg64(current,i,rt1[i]); | |
1120 | current->is32&=~(1LL<<rt1[i]); | |
1121 | dirty_reg(current,rt1[i]); | |
1122 | } | |
1123 | } | |
1124 | if(opcode2[i]==0x3c) // DSLL32 | |
1125 | { | |
1126 | if(rt1[i]) { | |
1127 | if(rs1[i]) alloc_reg(current,i,rs1[i]); | |
1128 | alloc_reg64(current,i,rt1[i]); | |
1129 | current->is32&=~(1LL<<rt1[i]); | |
1130 | dirty_reg(current,rt1[i]); | |
1131 | } | |
1132 | } | |
1133 | if(opcode2[i]==0x3e) // DSRL32 | |
1134 | { | |
1135 | if(rt1[i]) { | |
1136 | alloc_reg64(current,i,rs1[i]); | |
1137 | if(imm[i]==32) { | |
1138 | alloc_reg64(current,i,rt1[i]); | |
1139 | current->is32&=~(1LL<<rt1[i]); | |
1140 | } else { | |
1141 | alloc_reg(current,i,rt1[i]); | |
1142 | current->is32|=1LL<<rt1[i]; | |
1143 | } | |
1144 | dirty_reg(current,rt1[i]); | |
1145 | } | |
1146 | } | |
1147 | if(opcode2[i]==0x3f) // DSRA32 | |
1148 | { | |
1149 | if(rt1[i]) { | |
1150 | alloc_reg64(current,i,rs1[i]); | |
1151 | alloc_reg(current,i,rt1[i]); | |
1152 | current->is32|=1LL<<rt1[i]; | |
1153 | dirty_reg(current,rt1[i]); | |
1154 | } | |
1155 | } | |
1156 | } | |
1157 | ||
1158 | void shift_alloc(struct regstat *current,int i) | |
1159 | { | |
1160 | if(rt1[i]) { | |
1161 | if(opcode2[i]<=0x07) // SLLV/SRLV/SRAV | |
1162 | { | |
1163 | if(rs1[i]) alloc_reg(current,i,rs1[i]); | |
1164 | if(rs2[i]) alloc_reg(current,i,rs2[i]); | |
1165 | alloc_reg(current,i,rt1[i]); | |
e1190b87 | 1166 | if(rt1[i]==rs2[i]) { |
1167 | alloc_reg_temp(current,i,-1); | |
1168 | minimum_free_regs[i]=1; | |
1169 | } | |
57871462 | 1170 | current->is32|=1LL<<rt1[i]; |
1171 | } else { // DSLLV/DSRLV/DSRAV | |
1172 | if(rs1[i]) alloc_reg64(current,i,rs1[i]); | |
1173 | if(rs2[i]) alloc_reg(current,i,rs2[i]); | |
1174 | alloc_reg64(current,i,rt1[i]); | |
1175 | current->is32&=~(1LL<<rt1[i]); | |
1176 | if(opcode2[i]==0x16||opcode2[i]==0x17) // DSRLV and DSRAV need a temporary register | |
e1190b87 | 1177 | { |
57871462 | 1178 | alloc_reg_temp(current,i,-1); |
e1190b87 | 1179 | minimum_free_regs[i]=1; |
1180 | } | |
57871462 | 1181 | } |
1182 | clear_const(current,rs1[i]); | |
1183 | clear_const(current,rs2[i]); | |
1184 | clear_const(current,rt1[i]); | |
1185 | dirty_reg(current,rt1[i]); | |
1186 | } | |
1187 | } | |
1188 | ||
1189 | void alu_alloc(struct regstat *current,int i) | |
1190 | { | |
1191 | if(opcode2[i]>=0x20&&opcode2[i]<=0x23) { // ADD/ADDU/SUB/SUBU | |
1192 | if(rt1[i]) { | |
1193 | if(rs1[i]&&rs2[i]) { | |
1194 | alloc_reg(current,i,rs1[i]); | |
1195 | alloc_reg(current,i,rs2[i]); | |
1196 | } | |
1197 | else { | |
1198 | if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]); | |
1199 | if(rs2[i]&&needed_again(rs2[i],i)) alloc_reg(current,i,rs2[i]); | |
1200 | } | |
1201 | alloc_reg(current,i,rt1[i]); | |
1202 | } | |
1203 | current->is32|=1LL<<rt1[i]; | |
1204 | } | |
1205 | if(opcode2[i]==0x2a||opcode2[i]==0x2b) { // SLT/SLTU | |
1206 | if(rt1[i]) { | |
1207 | if(!((current->is32>>rs1[i])&(current->is32>>rs2[i])&1)) | |
1208 | { | |
1209 | alloc_reg64(current,i,rs1[i]); | |
1210 | alloc_reg64(current,i,rs2[i]); | |
1211 | alloc_reg(current,i,rt1[i]); | |
1212 | } else { | |
1213 | alloc_reg(current,i,rs1[i]); | |
1214 | alloc_reg(current,i,rs2[i]); | |
1215 | alloc_reg(current,i,rt1[i]); | |
1216 | } | |
1217 | } | |
1218 | current->is32|=1LL<<rt1[i]; | |
1219 | } | |
1220 | if(opcode2[i]>=0x24&&opcode2[i]<=0x27) { // AND/OR/XOR/NOR | |
1221 | if(rt1[i]) { | |
1222 | if(rs1[i]&&rs2[i]) { | |
1223 | alloc_reg(current,i,rs1[i]); | |
1224 | alloc_reg(current,i,rs2[i]); | |
1225 | } | |
1226 | else | |
1227 | { | |
1228 | if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]); | |
1229 | if(rs2[i]&&needed_again(rs2[i],i)) alloc_reg(current,i,rs2[i]); | |
1230 | } | |
1231 | alloc_reg(current,i,rt1[i]); | |
1232 | if(!((current->is32>>rs1[i])&(current->is32>>rs2[i])&1)) | |
1233 | { | |
1234 | if(!((current->uu>>rt1[i])&1)) { | |
1235 | alloc_reg64(current,i,rt1[i]); | |
1236 | } | |
1237 | if(get_reg(current->regmap,rt1[i]|64)>=0) { | |
1238 | if(rs1[i]&&rs2[i]) { | |
1239 | alloc_reg64(current,i,rs1[i]); | |
1240 | alloc_reg64(current,i,rs2[i]); | |
1241 | } | |
1242 | else | |
1243 | { | |
1244 | // Is is really worth it to keep 64-bit values in registers? | |
1245 | #ifdef NATIVE_64BIT | |
1246 | if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg64(current,i,rs1[i]); | |
1247 | if(rs2[i]&&needed_again(rs2[i],i)) alloc_reg64(current,i,rs2[i]); | |
1248 | #endif | |
1249 | } | |
1250 | } | |
1251 | current->is32&=~(1LL<<rt1[i]); | |
1252 | } else { | |
1253 | current->is32|=1LL<<rt1[i]; | |
1254 | } | |
1255 | } | |
1256 | } | |
1257 | if(opcode2[i]>=0x2c&&opcode2[i]<=0x2f) { // DADD/DADDU/DSUB/DSUBU | |
1258 | if(rt1[i]) { | |
1259 | if(rs1[i]&&rs2[i]) { | |
1260 | if(!((current->uu>>rt1[i])&1)||get_reg(current->regmap,rt1[i]|64)>=0) { | |
1261 | alloc_reg64(current,i,rs1[i]); | |
1262 | alloc_reg64(current,i,rs2[i]); | |
1263 | alloc_reg64(current,i,rt1[i]); | |
1264 | } else { | |
1265 | alloc_reg(current,i,rs1[i]); | |
1266 | alloc_reg(current,i,rs2[i]); | |
1267 | alloc_reg(current,i,rt1[i]); | |
1268 | } | |
1269 | } | |
1270 | else { | |
1271 | alloc_reg(current,i,rt1[i]); | |
1272 | if(!((current->uu>>rt1[i])&1)||get_reg(current->regmap,rt1[i]|64)>=0) { | |
1273 | // DADD used as move, or zeroing | |
1274 | // If we have a 64-bit source, then make the target 64 bits too | |
1275 | if(rs1[i]&&!((current->is32>>rs1[i])&1)) { | |
1276 | if(get_reg(current->regmap,rs1[i])>=0) alloc_reg64(current,i,rs1[i]); | |
1277 | alloc_reg64(current,i,rt1[i]); | |
1278 | } else if(rs2[i]&&!((current->is32>>rs2[i])&1)) { | |
1279 | if(get_reg(current->regmap,rs2[i])>=0) alloc_reg64(current,i,rs2[i]); | |
1280 | alloc_reg64(current,i,rt1[i]); | |
1281 | } | |
1282 | if(opcode2[i]>=0x2e&&rs2[i]) { | |
1283 | // DSUB used as negation - 64-bit result | |
1284 | // If we have a 32-bit register, extend it to 64 bits | |
1285 | if(get_reg(current->regmap,rs2[i])>=0) alloc_reg64(current,i,rs2[i]); | |
1286 | alloc_reg64(current,i,rt1[i]); | |
1287 | } | |
1288 | } | |
1289 | } | |
1290 | if(rs1[i]&&rs2[i]) { | |
1291 | current->is32&=~(1LL<<rt1[i]); | |
1292 | } else if(rs1[i]) { | |
1293 | current->is32&=~(1LL<<rt1[i]); | |
1294 | if((current->is32>>rs1[i])&1) | |
1295 | current->is32|=1LL<<rt1[i]; | |
1296 | } else if(rs2[i]) { | |
1297 | current->is32&=~(1LL<<rt1[i]); | |
1298 | if((current->is32>>rs2[i])&1) | |
1299 | current->is32|=1LL<<rt1[i]; | |
1300 | } else { | |
1301 | current->is32|=1LL<<rt1[i]; | |
1302 | } | |
1303 | } | |
1304 | } | |
1305 | clear_const(current,rs1[i]); | |
1306 | clear_const(current,rs2[i]); | |
1307 | clear_const(current,rt1[i]); | |
1308 | dirty_reg(current,rt1[i]); | |
1309 | } | |
1310 | ||
1311 | void imm16_alloc(struct regstat *current,int i) | |
1312 | { | |
1313 | if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]); | |
1314 | else lt1[i]=rs1[i]; | |
1315 | if(rt1[i]) alloc_reg(current,i,rt1[i]); | |
1316 | if(opcode[i]==0x18||opcode[i]==0x19) { // DADDI/DADDIU | |
1317 | current->is32&=~(1LL<<rt1[i]); | |
1318 | if(!((current->uu>>rt1[i])&1)||get_reg(current->regmap,rt1[i]|64)>=0) { | |
1319 | // TODO: Could preserve the 32-bit flag if the immediate is zero | |
1320 | alloc_reg64(current,i,rt1[i]); | |
1321 | alloc_reg64(current,i,rs1[i]); | |
1322 | } | |
1323 | clear_const(current,rs1[i]); | |
1324 | clear_const(current,rt1[i]); | |
1325 | } | |
1326 | else if(opcode[i]==0x0a||opcode[i]==0x0b) { // SLTI/SLTIU | |
1327 | if((~current->is32>>rs1[i])&1) alloc_reg64(current,i,rs1[i]); | |
1328 | current->is32|=1LL<<rt1[i]; | |
1329 | clear_const(current,rs1[i]); | |
1330 | clear_const(current,rt1[i]); | |
1331 | } | |
1332 | else if(opcode[i]>=0x0c&&opcode[i]<=0x0e) { // ANDI/ORI/XORI | |
1333 | if(((~current->is32>>rs1[i])&1)&&opcode[i]>0x0c) { | |
1334 | if(rs1[i]!=rt1[i]) { | |
1335 | if(needed_again(rs1[i],i)) alloc_reg64(current,i,rs1[i]); | |
1336 | alloc_reg64(current,i,rt1[i]); | |
1337 | current->is32&=~(1LL<<rt1[i]); | |
1338 | } | |
1339 | } | |
1340 | else current->is32|=1LL<<rt1[i]; // ANDI clears upper bits | |
1341 | if(is_const(current,rs1[i])) { | |
1342 | int v=get_const(current,rs1[i]); | |
1343 | if(opcode[i]==0x0c) set_const(current,rt1[i],v&imm[i]); | |
1344 | if(opcode[i]==0x0d) set_const(current,rt1[i],v|imm[i]); | |
1345 | if(opcode[i]==0x0e) set_const(current,rt1[i],v^imm[i]); | |
1346 | } | |
1347 | else clear_const(current,rt1[i]); | |
1348 | } | |
1349 | else if(opcode[i]==0x08||opcode[i]==0x09) { // ADDI/ADDIU | |
1350 | if(is_const(current,rs1[i])) { | |
1351 | int v=get_const(current,rs1[i]); | |
1352 | set_const(current,rt1[i],v+imm[i]); | |
1353 | } | |
1354 | else clear_const(current,rt1[i]); | |
1355 | current->is32|=1LL<<rt1[i]; | |
1356 | } | |
1357 | else { | |
1358 | set_const(current,rt1[i],((long long)((short)imm[i]))<<16); // LUI | |
1359 | current->is32|=1LL<<rt1[i]; | |
1360 | } | |
1361 | dirty_reg(current,rt1[i]); | |
1362 | } | |
1363 | ||
1364 | void load_alloc(struct regstat *current,int i) | |
1365 | { | |
1366 | clear_const(current,rt1[i]); | |
1367 | //if(rs1[i]!=rt1[i]&&needed_again(rs1[i],i)) clear_const(current,rs1[i]); // Does this help or hurt? | |
1368 | if(!rs1[i]) current->u&=~1LL; // Allow allocating r0 if it's the source register | |
1369 | if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]); | |
373d1d07 | 1370 | if(rt1[i]&&!((current->u>>rt1[i])&1)) { |
57871462 | 1371 | alloc_reg(current,i,rt1[i]); |
373d1d07 | 1372 | assert(get_reg(current->regmap,rt1[i])>=0); |
57871462 | 1373 | if(opcode[i]==0x27||opcode[i]==0x37) // LWU/LD |
1374 | { | |
1375 | current->is32&=~(1LL<<rt1[i]); | |
1376 | alloc_reg64(current,i,rt1[i]); | |
1377 | } | |
1378 | else if(opcode[i]==0x1A||opcode[i]==0x1B) // LDL/LDR | |
1379 | { | |
1380 | current->is32&=~(1LL<<rt1[i]); | |
1381 | alloc_reg64(current,i,rt1[i]); | |
1382 | alloc_all(current,i); | |
1383 | alloc_reg64(current,i,FTEMP); | |
e1190b87 | 1384 | minimum_free_regs[i]=HOST_REGS; |
57871462 | 1385 | } |
1386 | else current->is32|=1LL<<rt1[i]; | |
1387 | dirty_reg(current,rt1[i]); | |
57871462 | 1388 | // LWL/LWR need a temporary register for the old value |
1389 | if(opcode[i]==0x22||opcode[i]==0x26) | |
1390 | { | |
1391 | alloc_reg(current,i,FTEMP); | |
1392 | alloc_reg_temp(current,i,-1); | |
e1190b87 | 1393 | minimum_free_regs[i]=1; |
57871462 | 1394 | } |
1395 | } | |
1396 | else | |
1397 | { | |
373d1d07 | 1398 | // Load to r0 or unneeded register (dummy load) |
57871462 | 1399 | // but we still need a register to calculate the address |
535d208a | 1400 | if(opcode[i]==0x22||opcode[i]==0x26) |
1401 | { | |
1402 | alloc_reg(current,i,FTEMP); // LWL/LWR need another temporary | |
1403 | } | |
57871462 | 1404 | alloc_reg_temp(current,i,-1); |
e1190b87 | 1405 | minimum_free_regs[i]=1; |
535d208a | 1406 | if(opcode[i]==0x1A||opcode[i]==0x1B) // LDL/LDR |
1407 | { | |
1408 | alloc_all(current,i); | |
1409 | alloc_reg64(current,i,FTEMP); | |
e1190b87 | 1410 | minimum_free_regs[i]=HOST_REGS; |
535d208a | 1411 | } |
57871462 | 1412 | } |
1413 | } | |
1414 | ||
1415 | void store_alloc(struct regstat *current,int i) | |
1416 | { | |
1417 | clear_const(current,rs2[i]); | |
1418 | if(!(rs2[i])) current->u&=~1LL; // Allow allocating r0 if necessary | |
1419 | if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]); | |
1420 | alloc_reg(current,i,rs2[i]); | |
1421 | if(opcode[i]==0x2c||opcode[i]==0x2d||opcode[i]==0x3f) { // 64-bit SDL/SDR/SD | |
1422 | alloc_reg64(current,i,rs2[i]); | |
1423 | if(rs2[i]) alloc_reg(current,i,FTEMP); | |
1424 | } | |
57871462 | 1425 | #if defined(HOST_IMM8) |
1426 | // On CPUs without 32-bit immediates we need a pointer to invalid_code | |
1427 | else alloc_reg(current,i,INVCP); | |
1428 | #endif | |
b7918751 | 1429 | if(opcode[i]==0x2a||opcode[i]==0x2e||opcode[i]==0x2c||opcode[i]==0x2d) { // SWL/SWL/SDL/SDR |
57871462 | 1430 | alloc_reg(current,i,FTEMP); |
1431 | } | |
1432 | // We need a temporary register for address generation | |
1433 | alloc_reg_temp(current,i,-1); | |
e1190b87 | 1434 | minimum_free_regs[i]=1; |
57871462 | 1435 | } |
1436 | ||
1437 | void c1ls_alloc(struct regstat *current,int i) | |
1438 | { | |
1439 | //clear_const(current,rs1[i]); // FIXME | |
1440 | clear_const(current,rt1[i]); | |
1441 | if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]); | |
1442 | alloc_reg(current,i,CSREG); // Status | |
1443 | alloc_reg(current,i,FTEMP); | |
1444 | if(opcode[i]==0x35||opcode[i]==0x3d) { // 64-bit LDC1/SDC1 | |
1445 | alloc_reg64(current,i,FTEMP); | |
1446 | } | |
57871462 | 1447 | #if defined(HOST_IMM8) |
1448 | // On CPUs without 32-bit immediates we need a pointer to invalid_code | |
1449 | else if((opcode[i]&0x3b)==0x39) // SWC1/SDC1 | |
1450 | alloc_reg(current,i,INVCP); | |
1451 | #endif | |
1452 | // We need a temporary register for address generation | |
1453 | alloc_reg_temp(current,i,-1); | |
1454 | } | |
1455 | ||
b9b61529 | 1456 | void c2ls_alloc(struct regstat *current,int i) |
1457 | { | |
1458 | clear_const(current,rt1[i]); | |
1459 | if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]); | |
1460 | alloc_reg(current,i,FTEMP); | |
b9b61529 | 1461 | #if defined(HOST_IMM8) |
1462 | // On CPUs without 32-bit immediates we need a pointer to invalid_code | |
1edfcc68 | 1463 | if((opcode[i]&0x3b)==0x3a) // SWC2/SDC2 |
b9b61529 | 1464 | alloc_reg(current,i,INVCP); |
1465 | #endif | |
1466 | // We need a temporary register for address generation | |
1467 | alloc_reg_temp(current,i,-1); | |
e1190b87 | 1468 | minimum_free_regs[i]=1; |
b9b61529 | 1469 | } |
1470 | ||
57871462 | 1471 | #ifndef multdiv_alloc |
1472 | void multdiv_alloc(struct regstat *current,int i) | |
1473 | { | |
1474 | // case 0x18: MULT | |
1475 | // case 0x19: MULTU | |
1476 | // case 0x1A: DIV | |
1477 | // case 0x1B: DIVU | |
1478 | // case 0x1C: DMULT | |
1479 | // case 0x1D: DMULTU | |
1480 | // case 0x1E: DDIV | |
1481 | // case 0x1F: DDIVU | |
1482 | clear_const(current,rs1[i]); | |
1483 | clear_const(current,rs2[i]); | |
1484 | if(rs1[i]&&rs2[i]) | |
1485 | { | |
1486 | if((opcode2[i]&4)==0) // 32-bit | |
1487 | { | |
1488 | current->u&=~(1LL<<HIREG); | |
1489 | current->u&=~(1LL<<LOREG); | |
1490 | alloc_reg(current,i,HIREG); | |
1491 | alloc_reg(current,i,LOREG); | |
1492 | alloc_reg(current,i,rs1[i]); | |
1493 | alloc_reg(current,i,rs2[i]); | |
1494 | current->is32|=1LL<<HIREG; | |
1495 | current->is32|=1LL<<LOREG; | |
1496 | dirty_reg(current,HIREG); | |
1497 | dirty_reg(current,LOREG); | |
1498 | } | |
1499 | else // 64-bit | |
1500 | { | |
1501 | current->u&=~(1LL<<HIREG); | |
1502 | current->u&=~(1LL<<LOREG); | |
1503 | current->uu&=~(1LL<<HIREG); | |
1504 | current->uu&=~(1LL<<LOREG); | |
1505 | alloc_reg64(current,i,HIREG); | |
1506 | //if(HOST_REGS>10) alloc_reg64(current,i,LOREG); | |
1507 | alloc_reg64(current,i,rs1[i]); | |
1508 | alloc_reg64(current,i,rs2[i]); | |
1509 | alloc_all(current,i); | |
1510 | current->is32&=~(1LL<<HIREG); | |
1511 | current->is32&=~(1LL<<LOREG); | |
1512 | dirty_reg(current,HIREG); | |
1513 | dirty_reg(current,LOREG); | |
e1190b87 | 1514 | minimum_free_regs[i]=HOST_REGS; |
57871462 | 1515 | } |
1516 | } | |
1517 | else | |
1518 | { | |
1519 | // Multiply by zero is zero. | |
1520 | // MIPS does not have a divide by zero exception. | |
1521 | // The result is undefined, we return zero. | |
1522 | alloc_reg(current,i,HIREG); | |
1523 | alloc_reg(current,i,LOREG); | |
1524 | current->is32|=1LL<<HIREG; | |
1525 | current->is32|=1LL<<LOREG; | |
1526 | dirty_reg(current,HIREG); | |
1527 | dirty_reg(current,LOREG); | |
1528 | } | |
1529 | } | |
1530 | #endif | |
1531 | ||
1532 | void cop0_alloc(struct regstat *current,int i) | |
1533 | { | |
1534 | if(opcode2[i]==0) // MFC0 | |
1535 | { | |
1536 | if(rt1[i]) { | |
1537 | clear_const(current,rt1[i]); | |
1538 | alloc_all(current,i); | |
1539 | alloc_reg(current,i,rt1[i]); | |
1540 | current->is32|=1LL<<rt1[i]; | |
1541 | dirty_reg(current,rt1[i]); | |
1542 | } | |
1543 | } | |
1544 | else if(opcode2[i]==4) // MTC0 | |
1545 | { | |
1546 | if(rs1[i]){ | |
1547 | clear_const(current,rs1[i]); | |
1548 | alloc_reg(current,i,rs1[i]); | |
1549 | alloc_all(current,i); | |
1550 | } | |
1551 | else { | |
1552 | alloc_all(current,i); // FIXME: Keep r0 | |
1553 | current->u&=~1LL; | |
1554 | alloc_reg(current,i,0); | |
1555 | } | |
1556 | } | |
1557 | else | |
1558 | { | |
1559 | // TLBR/TLBWI/TLBWR/TLBP/ERET | |
1560 | assert(opcode2[i]==0x10); | |
1561 | alloc_all(current,i); | |
1562 | } | |
e1190b87 | 1563 | minimum_free_regs[i]=HOST_REGS; |
57871462 | 1564 | } |
1565 | ||
1566 | void cop1_alloc(struct regstat *current,int i) | |
1567 | { | |
1568 | alloc_reg(current,i,CSREG); // Load status | |
1569 | if(opcode2[i]<3) // MFC1/DMFC1/CFC1 | |
1570 | { | |
7de557a6 | 1571 | if(rt1[i]){ |
1572 | clear_const(current,rt1[i]); | |
1573 | if(opcode2[i]==1) { | |
1574 | alloc_reg64(current,i,rt1[i]); // DMFC1 | |
1575 | current->is32&=~(1LL<<rt1[i]); | |
1576 | }else{ | |
1577 | alloc_reg(current,i,rt1[i]); // MFC1/CFC1 | |
1578 | current->is32|=1LL<<rt1[i]; | |
1579 | } | |
1580 | dirty_reg(current,rt1[i]); | |
57871462 | 1581 | } |
57871462 | 1582 | alloc_reg_temp(current,i,-1); |
1583 | } | |
1584 | else if(opcode2[i]>3) // MTC1/DMTC1/CTC1 | |
1585 | { | |
1586 | if(rs1[i]){ | |
1587 | clear_const(current,rs1[i]); | |
1588 | if(opcode2[i]==5) | |
1589 | alloc_reg64(current,i,rs1[i]); // DMTC1 | |
1590 | else | |
1591 | alloc_reg(current,i,rs1[i]); // MTC1/CTC1 | |
1592 | alloc_reg_temp(current,i,-1); | |
1593 | } | |
1594 | else { | |
1595 | current->u&=~1LL; | |
1596 | alloc_reg(current,i,0); | |
1597 | alloc_reg_temp(current,i,-1); | |
1598 | } | |
1599 | } | |
e1190b87 | 1600 | minimum_free_regs[i]=1; |
57871462 | 1601 | } |
1602 | void fconv_alloc(struct regstat *current,int i) | |
1603 | { | |
1604 | alloc_reg(current,i,CSREG); // Load status | |
1605 | alloc_reg_temp(current,i,-1); | |
e1190b87 | 1606 | minimum_free_regs[i]=1; |
57871462 | 1607 | } |
1608 | void float_alloc(struct regstat *current,int i) | |
1609 | { | |
1610 | alloc_reg(current,i,CSREG); // Load status | |
1611 | alloc_reg_temp(current,i,-1); | |
e1190b87 | 1612 | minimum_free_regs[i]=1; |
57871462 | 1613 | } |
b9b61529 | 1614 | void c2op_alloc(struct regstat *current,int i) |
1615 | { | |
1616 | alloc_reg_temp(current,i,-1); | |
1617 | } | |
57871462 | 1618 | void fcomp_alloc(struct regstat *current,int i) |
1619 | { | |
1620 | alloc_reg(current,i,CSREG); // Load status | |
1621 | alloc_reg(current,i,FSREG); // Load flags | |
1622 | dirty_reg(current,FSREG); // Flag will be modified | |
1623 | alloc_reg_temp(current,i,-1); | |
e1190b87 | 1624 | minimum_free_regs[i]=1; |
57871462 | 1625 | } |
1626 | ||
1627 | void syscall_alloc(struct regstat *current,int i) | |
1628 | { | |
1629 | alloc_cc(current,i); | |
1630 | dirty_reg(current,CCREG); | |
1631 | alloc_all(current,i); | |
e1190b87 | 1632 | minimum_free_regs[i]=HOST_REGS; |
57871462 | 1633 | current->isconst=0; |
1634 | } | |
1635 | ||
1636 | void delayslot_alloc(struct regstat *current,int i) | |
1637 | { | |
1638 | switch(itype[i]) { | |
1639 | case UJUMP: | |
1640 | case CJUMP: | |
1641 | case SJUMP: | |
1642 | case RJUMP: | |
1643 | case FJUMP: | |
1644 | case SYSCALL: | |
7139f3c8 | 1645 | case HLECALL: |
57871462 | 1646 | case SPAN: |
1647 | assem_debug("jump in the delay slot. this shouldn't happen.\n");//exit(1); | |
c43b5311 | 1648 | SysPrintf("Disabled speculative precompilation\n"); |
57871462 | 1649 | stop_after_jal=1; |
1650 | break; | |
1651 | case IMM16: | |
1652 | imm16_alloc(current,i); | |
1653 | break; | |
1654 | case LOAD: | |
1655 | case LOADLR: | |
1656 | load_alloc(current,i); | |
1657 | break; | |
1658 | case STORE: | |
1659 | case STORELR: | |
1660 | store_alloc(current,i); | |
1661 | break; | |
1662 | case ALU: | |
1663 | alu_alloc(current,i); | |
1664 | break; | |
1665 | case SHIFT: | |
1666 | shift_alloc(current,i); | |
1667 | break; | |
1668 | case MULTDIV: | |
1669 | multdiv_alloc(current,i); | |
1670 | break; | |
1671 | case SHIFTIMM: | |
1672 | shiftimm_alloc(current,i); | |
1673 | break; | |
1674 | case MOV: | |
1675 | mov_alloc(current,i); | |
1676 | break; | |
1677 | case COP0: | |
1678 | cop0_alloc(current,i); | |
1679 | break; | |
1680 | case COP1: | |
b9b61529 | 1681 | case COP2: |
57871462 | 1682 | cop1_alloc(current,i); |
1683 | break; | |
1684 | case C1LS: | |
1685 | c1ls_alloc(current,i); | |
1686 | break; | |
b9b61529 | 1687 | case C2LS: |
1688 | c2ls_alloc(current,i); | |
1689 | break; | |
57871462 | 1690 | case FCONV: |
1691 | fconv_alloc(current,i); | |
1692 | break; | |
1693 | case FLOAT: | |
1694 | float_alloc(current,i); | |
1695 | break; | |
1696 | case FCOMP: | |
1697 | fcomp_alloc(current,i); | |
1698 | break; | |
b9b61529 | 1699 | case C2OP: |
1700 | c2op_alloc(current,i); | |
1701 | break; | |
57871462 | 1702 | } |
1703 | } | |
1704 | ||
1705 | // Special case where a branch and delay slot span two pages in virtual memory | |
1706 | static void pagespan_alloc(struct regstat *current,int i) | |
1707 | { | |
1708 | current->isconst=0; | |
1709 | current->wasconst=0; | |
1710 | regs[i].wasconst=0; | |
e1190b87 | 1711 | minimum_free_regs[i]=HOST_REGS; |
57871462 | 1712 | alloc_all(current,i); |
1713 | alloc_cc(current,i); | |
1714 | dirty_reg(current,CCREG); | |
1715 | if(opcode[i]==3) // JAL | |
1716 | { | |
1717 | alloc_reg(current,i,31); | |
1718 | dirty_reg(current,31); | |
1719 | } | |
1720 | if(opcode[i]==0&&(opcode2[i]&0x3E)==8) // JR/JALR | |
1721 | { | |
1722 | alloc_reg(current,i,rs1[i]); | |
5067f341 | 1723 | if (rt1[i]!=0) { |
1724 | alloc_reg(current,i,rt1[i]); | |
1725 | dirty_reg(current,rt1[i]); | |
57871462 | 1726 | } |
1727 | } | |
1728 | if((opcode[i]&0x2E)==4) // BEQ/BNE/BEQL/BNEL | |
1729 | { | |
1730 | if(rs1[i]) alloc_reg(current,i,rs1[i]); | |
1731 | if(rs2[i]) alloc_reg(current,i,rs2[i]); | |
1732 | if(!((current->is32>>rs1[i])&(current->is32>>rs2[i])&1)) | |
1733 | { | |
1734 | if(rs1[i]) alloc_reg64(current,i,rs1[i]); | |
1735 | if(rs2[i]) alloc_reg64(current,i,rs2[i]); | |
1736 | } | |
1737 | } | |
1738 | else | |
1739 | if((opcode[i]&0x2E)==6) // BLEZ/BGTZ/BLEZL/BGTZL | |
1740 | { | |
1741 | if(rs1[i]) alloc_reg(current,i,rs1[i]); | |
1742 | if(!((current->is32>>rs1[i])&1)) | |
1743 | { | |
1744 | if(rs1[i]) alloc_reg64(current,i,rs1[i]); | |
1745 | } | |
1746 | } | |
1747 | else | |
1748 | if(opcode[i]==0x11) // BC1 | |
1749 | { | |
1750 | alloc_reg(current,i,FSREG); | |
1751 | alloc_reg(current,i,CSREG); | |
1752 | } | |
1753 | //else ... | |
1754 | } | |
1755 | ||
e2b5e7aa | 1756 | static void add_stub(int type,int addr,int retaddr,int a,int b,int c,int d,int e) |
57871462 | 1757 | { |
1758 | stubs[stubcount][0]=type; | |
1759 | stubs[stubcount][1]=addr; | |
1760 | stubs[stubcount][2]=retaddr; | |
1761 | stubs[stubcount][3]=a; | |
1762 | stubs[stubcount][4]=b; | |
1763 | stubs[stubcount][5]=c; | |
1764 | stubs[stubcount][6]=d; | |
1765 | stubs[stubcount][7]=e; | |
1766 | stubcount++; | |
1767 | } | |
1768 | ||
1769 | // Write out a single register | |
1770 | void wb_register(signed char r,signed char regmap[],uint64_t dirty,uint64_t is32) | |
1771 | { | |
1772 | int hr; | |
1773 | for(hr=0;hr<HOST_REGS;hr++) { | |
1774 | if(hr!=EXCLUDE_REG) { | |
1775 | if((regmap[hr]&63)==r) { | |
1776 | if((dirty>>hr)&1) { | |
1777 | if(regmap[hr]<64) { | |
1778 | emit_storereg(r,hr); | |
57871462 | 1779 | }else{ |
1780 | emit_storereg(r|64,hr); | |
1781 | } | |
1782 | } | |
1783 | } | |
1784 | } | |
1785 | } | |
1786 | } | |
1787 | ||
1788 | int mchecksum() | |
1789 | { | |
1790 | //if(!tracedebug) return 0; | |
1791 | int i; | |
1792 | int sum=0; | |
1793 | for(i=0;i<2097152;i++) { | |
1794 | unsigned int temp=sum; | |
1795 | sum<<=1; | |
1796 | sum|=(~temp)>>31; | |
1797 | sum^=((u_int *)rdram)[i]; | |
1798 | } | |
1799 | return sum; | |
1800 | } | |
1801 | int rchecksum() | |
1802 | { | |
1803 | int i; | |
1804 | int sum=0; | |
1805 | for(i=0;i<64;i++) | |
1806 | sum^=((u_int *)reg)[i]; | |
1807 | return sum; | |
1808 | } | |
57871462 | 1809 | void rlist() |
1810 | { | |
1811 | int i; | |
1812 | printf("TRACE: "); | |
1813 | for(i=0;i<32;i++) | |
1814 | printf("r%d:%8x%8x ",i,((int *)(reg+i))[1],((int *)(reg+i))[0]); | |
1815 | printf("\n"); | |
57871462 | 1816 | } |
1817 | ||
1818 | void enabletrace() | |
1819 | { | |
1820 | tracedebug=1; | |
1821 | } | |
1822 | ||
1823 | void memdebug(int i) | |
1824 | { | |
1825 | //printf("TRACE: count=%d next=%d (checksum %x) lo=%8x%8x\n",Count,next_interupt,mchecksum(),(int)(reg[LOREG]>>32),(int)reg[LOREG]); | |
1826 | //printf("TRACE: count=%d next=%d (rchecksum %x)\n",Count,next_interupt,rchecksum()); | |
1827 | //rlist(); | |
1828 | //if(tracedebug) { | |
1829 | //if(Count>=-2084597794) { | |
1830 | if((signed int)Count>=-2084597794&&(signed int)Count<0) { | |
1831 | //if(0) { | |
1832 | printf("TRACE: count=%d next=%d (checksum %x)\n",Count,next_interupt,mchecksum()); | |
1833 | //printf("TRACE: count=%d next=%d (checksum %x) Status=%x\n",Count,next_interupt,mchecksum(),Status); | |
1834 | //printf("TRACE: count=%d next=%d (checksum %x) hi=%8x%8x\n",Count,next_interupt,mchecksum(),(int)(reg[HIREG]>>32),(int)reg[HIREG]); | |
1835 | rlist(); | |
1836 | #ifdef __i386__ | |
1837 | printf("TRACE: %x\n",(&i)[-1]); | |
1838 | #endif | |
1839 | #ifdef __arm__ | |
1840 | int j; | |
1841 | printf("TRACE: %x \n",(&j)[10]); | |
1842 | printf("TRACE: %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x\n",(&j)[1],(&j)[2],(&j)[3],(&j)[4],(&j)[5],(&j)[6],(&j)[7],(&j)[8],(&j)[9],(&j)[10],(&j)[11],(&j)[12],(&j)[13],(&j)[14],(&j)[15],(&j)[16],(&j)[17],(&j)[18],(&j)[19],(&j)[20]); | |
1843 | #endif | |
1844 | //fflush(stdout); | |
1845 | } | |
1846 | //printf("TRACE: %x\n",(&i)[-1]); | |
1847 | } | |
1848 | ||
57871462 | 1849 | void alu_assemble(int i,struct regstat *i_regs) |
1850 | { | |
1851 | if(opcode2[i]>=0x20&&opcode2[i]<=0x23) { // ADD/ADDU/SUB/SUBU | |
1852 | if(rt1[i]) { | |
1853 | signed char s1,s2,t; | |
1854 | t=get_reg(i_regs->regmap,rt1[i]); | |
1855 | if(t>=0) { | |
1856 | s1=get_reg(i_regs->regmap,rs1[i]); | |
1857 | s2=get_reg(i_regs->regmap,rs2[i]); | |
1858 | if(rs1[i]&&rs2[i]) { | |
1859 | assert(s1>=0); | |
1860 | assert(s2>=0); | |
1861 | if(opcode2[i]&2) emit_sub(s1,s2,t); | |
1862 | else emit_add(s1,s2,t); | |
1863 | } | |
1864 | else if(rs1[i]) { | |
1865 | if(s1>=0) emit_mov(s1,t); | |
1866 | else emit_loadreg(rs1[i],t); | |
1867 | } | |
1868 | else if(rs2[i]) { | |
1869 | if(s2>=0) { | |
1870 | if(opcode2[i]&2) emit_neg(s2,t); | |
1871 | else emit_mov(s2,t); | |
1872 | } | |
1873 | else { | |
1874 | emit_loadreg(rs2[i],t); | |
1875 | if(opcode2[i]&2) emit_neg(t,t); | |
1876 | } | |
1877 | } | |
1878 | else emit_zeroreg(t); | |
1879 | } | |
1880 | } | |
1881 | } | |
1882 | if(opcode2[i]>=0x2c&&opcode2[i]<=0x2f) { // DADD/DADDU/DSUB/DSUBU | |
1883 | if(rt1[i]) { | |
1884 | signed char s1l,s2l,s1h,s2h,tl,th; | |
1885 | tl=get_reg(i_regs->regmap,rt1[i]); | |
1886 | th=get_reg(i_regs->regmap,rt1[i]|64); | |
1887 | if(tl>=0) { | |
1888 | s1l=get_reg(i_regs->regmap,rs1[i]); | |
1889 | s2l=get_reg(i_regs->regmap,rs2[i]); | |
1890 | s1h=get_reg(i_regs->regmap,rs1[i]|64); | |
1891 | s2h=get_reg(i_regs->regmap,rs2[i]|64); | |
1892 | if(rs1[i]&&rs2[i]) { | |
1893 | assert(s1l>=0); | |
1894 | assert(s2l>=0); | |
1895 | if(opcode2[i]&2) emit_subs(s1l,s2l,tl); | |
1896 | else emit_adds(s1l,s2l,tl); | |
1897 | if(th>=0) { | |
1898 | #ifdef INVERTED_CARRY | |
1899 | if(opcode2[i]&2) {if(s1h!=th) emit_mov(s1h,th);emit_sbb(th,s2h);} | |
1900 | #else | |
1901 | if(opcode2[i]&2) emit_sbc(s1h,s2h,th); | |
1902 | #endif | |
1903 | else emit_add(s1h,s2h,th); | |
1904 | } | |
1905 | } | |
1906 | else if(rs1[i]) { | |
1907 | if(s1l>=0) emit_mov(s1l,tl); | |
1908 | else emit_loadreg(rs1[i],tl); | |
1909 | if(th>=0) { | |
1910 | if(s1h>=0) emit_mov(s1h,th); | |
1911 | else emit_loadreg(rs1[i]|64,th); | |
1912 | } | |
1913 | } | |
1914 | else if(rs2[i]) { | |
1915 | if(s2l>=0) { | |
1916 | if(opcode2[i]&2) emit_negs(s2l,tl); | |
1917 | else emit_mov(s2l,tl); | |
1918 | } | |
1919 | else { | |
1920 | emit_loadreg(rs2[i],tl); | |
1921 | if(opcode2[i]&2) emit_negs(tl,tl); | |
1922 | } | |
1923 | if(th>=0) { | |
1924 | #ifdef INVERTED_CARRY | |
1925 | if(s2h>=0) emit_mov(s2h,th); | |
1926 | else emit_loadreg(rs2[i]|64,th); | |
1927 | if(opcode2[i]&2) { | |
1928 | emit_adcimm(-1,th); // x86 has inverted carry flag | |
1929 | emit_not(th,th); | |
1930 | } | |
1931 | #else | |
1932 | if(opcode2[i]&2) { | |
1933 | if(s2h>=0) emit_rscimm(s2h,0,th); | |
1934 | else { | |
1935 | emit_loadreg(rs2[i]|64,th); | |
1936 | emit_rscimm(th,0,th); | |
1937 | } | |
1938 | }else{ | |
1939 | if(s2h>=0) emit_mov(s2h,th); | |
1940 | else emit_loadreg(rs2[i]|64,th); | |
1941 | } | |
1942 | #endif | |
1943 | } | |
1944 | } | |
1945 | else { | |
1946 | emit_zeroreg(tl); | |
1947 | if(th>=0) emit_zeroreg(th); | |
1948 | } | |
1949 | } | |
1950 | } | |
1951 | } | |
1952 | if(opcode2[i]==0x2a||opcode2[i]==0x2b) { // SLT/SLTU | |
1953 | if(rt1[i]) { | |
1954 | signed char s1l,s1h,s2l,s2h,t; | |
1955 | if(!((i_regs->was32>>rs1[i])&(i_regs->was32>>rs2[i])&1)) | |
1956 | { | |
1957 | t=get_reg(i_regs->regmap,rt1[i]); | |
1958 | //assert(t>=0); | |
1959 | if(t>=0) { | |
1960 | s1l=get_reg(i_regs->regmap,rs1[i]); | |
1961 | s1h=get_reg(i_regs->regmap,rs1[i]|64); | |
1962 | s2l=get_reg(i_regs->regmap,rs2[i]); | |
1963 | s2h=get_reg(i_regs->regmap,rs2[i]|64); | |
1964 | if(rs2[i]==0) // rx<r0 | |
1965 | { | |
1966 | assert(s1h>=0); | |
1967 | if(opcode2[i]==0x2a) // SLT | |
1968 | emit_shrimm(s1h,31,t); | |
1969 | else // SLTU (unsigned can not be less than zero) | |
1970 | emit_zeroreg(t); | |
1971 | } | |
1972 | else if(rs1[i]==0) // r0<rx | |
1973 | { | |
1974 | assert(s2h>=0); | |
1975 | if(opcode2[i]==0x2a) // SLT | |
1976 | emit_set_gz64_32(s2h,s2l,t); | |
1977 | else // SLTU (set if not zero) | |
1978 | emit_set_nz64_32(s2h,s2l,t); | |
1979 | } | |
1980 | else { | |
1981 | assert(s1l>=0);assert(s1h>=0); | |
1982 | assert(s2l>=0);assert(s2h>=0); | |
1983 | if(opcode2[i]==0x2a) // SLT | |
1984 | emit_set_if_less64_32(s1h,s1l,s2h,s2l,t); | |
1985 | else // SLTU | |
1986 | emit_set_if_carry64_32(s1h,s1l,s2h,s2l,t); | |
1987 | } | |
1988 | } | |
1989 | } else { | |
1990 | t=get_reg(i_regs->regmap,rt1[i]); | |
1991 | //assert(t>=0); | |
1992 | if(t>=0) { | |
1993 | s1l=get_reg(i_regs->regmap,rs1[i]); | |
1994 | s2l=get_reg(i_regs->regmap,rs2[i]); | |
1995 | if(rs2[i]==0) // rx<r0 | |
1996 | { | |
1997 | assert(s1l>=0); | |
1998 | if(opcode2[i]==0x2a) // SLT | |
1999 | emit_shrimm(s1l,31,t); | |
2000 | else // SLTU (unsigned can not be less than zero) | |
2001 | emit_zeroreg(t); | |
2002 | } | |
2003 | else if(rs1[i]==0) // r0<rx | |
2004 | { | |
2005 | assert(s2l>=0); | |
2006 | if(opcode2[i]==0x2a) // SLT | |
2007 | emit_set_gz32(s2l,t); | |
2008 | else // SLTU (set if not zero) | |
2009 | emit_set_nz32(s2l,t); | |
2010 | } | |
2011 | else{ | |
2012 | assert(s1l>=0);assert(s2l>=0); | |
2013 | if(opcode2[i]==0x2a) // SLT | |
2014 | emit_set_if_less32(s1l,s2l,t); | |
2015 | else // SLTU | |
2016 | emit_set_if_carry32(s1l,s2l,t); | |
2017 | } | |
2018 | } | |
2019 | } | |
2020 | } | |
2021 | } | |
2022 | if(opcode2[i]>=0x24&&opcode2[i]<=0x27) { // AND/OR/XOR/NOR | |
2023 | if(rt1[i]) { | |
2024 | signed char s1l,s1h,s2l,s2h,th,tl; | |
2025 | tl=get_reg(i_regs->regmap,rt1[i]); | |
2026 | th=get_reg(i_regs->regmap,rt1[i]|64); | |
2027 | if(!((i_regs->was32>>rs1[i])&(i_regs->was32>>rs2[i])&1)&&th>=0) | |
2028 | { | |
2029 | assert(tl>=0); | |
2030 | if(tl>=0) { | |
2031 | s1l=get_reg(i_regs->regmap,rs1[i]); | |
2032 | s1h=get_reg(i_regs->regmap,rs1[i]|64); | |
2033 | s2l=get_reg(i_regs->regmap,rs2[i]); | |
2034 | s2h=get_reg(i_regs->regmap,rs2[i]|64); | |
2035 | if(rs1[i]&&rs2[i]) { | |
2036 | assert(s1l>=0);assert(s1h>=0); | |
2037 | assert(s2l>=0);assert(s2h>=0); | |
2038 | if(opcode2[i]==0x24) { // AND | |
2039 | emit_and(s1l,s2l,tl); | |
2040 | emit_and(s1h,s2h,th); | |
2041 | } else | |
2042 | if(opcode2[i]==0x25) { // OR | |
2043 | emit_or(s1l,s2l,tl); | |
2044 | emit_or(s1h,s2h,th); | |
2045 | } else | |
2046 | if(opcode2[i]==0x26) { // XOR | |
2047 | emit_xor(s1l,s2l,tl); | |
2048 | emit_xor(s1h,s2h,th); | |
2049 | } else | |
2050 | if(opcode2[i]==0x27) { // NOR | |
2051 | emit_or(s1l,s2l,tl); | |
2052 | emit_or(s1h,s2h,th); | |
2053 | emit_not(tl,tl); | |
2054 | emit_not(th,th); | |
2055 | } | |
2056 | } | |
2057 | else | |
2058 | { | |
2059 | if(opcode2[i]==0x24) { // AND | |
2060 | emit_zeroreg(tl); | |
2061 | emit_zeroreg(th); | |
2062 | } else | |
2063 | if(opcode2[i]==0x25||opcode2[i]==0x26) { // OR/XOR | |
2064 | if(rs1[i]){ | |
2065 | if(s1l>=0) emit_mov(s1l,tl); | |
2066 | else emit_loadreg(rs1[i],tl); | |
2067 | if(s1h>=0) emit_mov(s1h,th); | |
2068 | else emit_loadreg(rs1[i]|64,th); | |
2069 | } | |
2070 | else | |
2071 | if(rs2[i]){ | |
2072 | if(s2l>=0) emit_mov(s2l,tl); | |
2073 | else emit_loadreg(rs2[i],tl); | |
2074 | if(s2h>=0) emit_mov(s2h,th); | |
2075 | else emit_loadreg(rs2[i]|64,th); | |
2076 | } | |
2077 | else{ | |
2078 | emit_zeroreg(tl); | |
2079 | emit_zeroreg(th); | |
2080 | } | |
2081 | } else | |
2082 | if(opcode2[i]==0x27) { // NOR | |
2083 | if(rs1[i]){ | |
2084 | if(s1l>=0) emit_not(s1l,tl); | |
2085 | else{ | |
2086 | emit_loadreg(rs1[i],tl); | |
2087 | emit_not(tl,tl); | |
2088 | } | |
2089 | if(s1h>=0) emit_not(s1h,th); | |
2090 | else{ | |
2091 | emit_loadreg(rs1[i]|64,th); | |
2092 | emit_not(th,th); | |
2093 | } | |
2094 | } | |
2095 | else | |
2096 | if(rs2[i]){ | |
2097 | if(s2l>=0) emit_not(s2l,tl); | |
2098 | else{ | |
2099 | emit_loadreg(rs2[i],tl); | |
2100 | emit_not(tl,tl); | |
2101 | } | |
2102 | if(s2h>=0) emit_not(s2h,th); | |
2103 | else{ | |
2104 | emit_loadreg(rs2[i]|64,th); | |
2105 | emit_not(th,th); | |
2106 | } | |
2107 | } | |
2108 | else { | |
2109 | emit_movimm(-1,tl); | |
2110 | emit_movimm(-1,th); | |
2111 | } | |
2112 | } | |
2113 | } | |
2114 | } | |
2115 | } | |
2116 | else | |
2117 | { | |
2118 | // 32 bit | |
2119 | if(tl>=0) { | |
2120 | s1l=get_reg(i_regs->regmap,rs1[i]); | |
2121 | s2l=get_reg(i_regs->regmap,rs2[i]); | |
2122 | if(rs1[i]&&rs2[i]) { | |
2123 | assert(s1l>=0); | |
2124 | assert(s2l>=0); | |
2125 | if(opcode2[i]==0x24) { // AND | |
2126 | emit_and(s1l,s2l,tl); | |
2127 | } else | |
2128 | if(opcode2[i]==0x25) { // OR | |
2129 | emit_or(s1l,s2l,tl); | |
2130 | } else | |
2131 | if(opcode2[i]==0x26) { // XOR | |
2132 | emit_xor(s1l,s2l,tl); | |
2133 | } else | |
2134 | if(opcode2[i]==0x27) { // NOR | |
2135 | emit_or(s1l,s2l,tl); | |
2136 | emit_not(tl,tl); | |
2137 | } | |
2138 | } | |
2139 | else | |
2140 | { | |
2141 | if(opcode2[i]==0x24) { // AND | |
2142 | emit_zeroreg(tl); | |
2143 | } else | |
2144 | if(opcode2[i]==0x25||opcode2[i]==0x26) { // OR/XOR | |
2145 | if(rs1[i]){ | |
2146 | if(s1l>=0) emit_mov(s1l,tl); | |
2147 | else emit_loadreg(rs1[i],tl); // CHECK: regmap_entry? | |
2148 | } | |
2149 | else | |
2150 | if(rs2[i]){ | |
2151 | if(s2l>=0) emit_mov(s2l,tl); | |
2152 | else emit_loadreg(rs2[i],tl); // CHECK: regmap_entry? | |
2153 | } | |
2154 | else emit_zeroreg(tl); | |
2155 | } else | |
2156 | if(opcode2[i]==0x27) { // NOR | |
2157 | if(rs1[i]){ | |
2158 | if(s1l>=0) emit_not(s1l,tl); | |
2159 | else { | |
2160 | emit_loadreg(rs1[i],tl); | |
2161 | emit_not(tl,tl); | |
2162 | } | |
2163 | } | |
2164 | else | |
2165 | if(rs2[i]){ | |
2166 | if(s2l>=0) emit_not(s2l,tl); | |
2167 | else { | |
2168 | emit_loadreg(rs2[i],tl); | |
2169 | emit_not(tl,tl); | |
2170 | } | |
2171 | } | |
2172 | else emit_movimm(-1,tl); | |
2173 | } | |
2174 | } | |
2175 | } | |
2176 | } | |
2177 | } | |
2178 | } | |
2179 | } | |
2180 | ||
2181 | void imm16_assemble(int i,struct regstat *i_regs) | |
2182 | { | |
2183 | if (opcode[i]==0x0f) { // LUI | |
2184 | if(rt1[i]) { | |
2185 | signed char t; | |
2186 | t=get_reg(i_regs->regmap,rt1[i]); | |
2187 | //assert(t>=0); | |
2188 | if(t>=0) { | |
2189 | if(!((i_regs->isconst>>t)&1)) | |
2190 | emit_movimm(imm[i]<<16,t); | |
2191 | } | |
2192 | } | |
2193 | } | |
2194 | if(opcode[i]==0x08||opcode[i]==0x09) { // ADDI/ADDIU | |
2195 | if(rt1[i]) { | |
2196 | signed char s,t; | |
2197 | t=get_reg(i_regs->regmap,rt1[i]); | |
2198 | s=get_reg(i_regs->regmap,rs1[i]); | |
2199 | if(rs1[i]) { | |
2200 | //assert(t>=0); | |
2201 | //assert(s>=0); | |
2202 | if(t>=0) { | |
2203 | if(!((i_regs->isconst>>t)&1)) { | |
2204 | if(s<0) { | |
2205 | if(i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t); | |
2206 | emit_addimm(t,imm[i],t); | |
2207 | }else{ | |
2208 | if(!((i_regs->wasconst>>s)&1)) | |
2209 | emit_addimm(s,imm[i],t); | |
2210 | else | |
2211 | emit_movimm(constmap[i][s]+imm[i],t); | |
2212 | } | |
2213 | } | |
2214 | } | |
2215 | } else { | |
2216 | if(t>=0) { | |
2217 | if(!((i_regs->isconst>>t)&1)) | |
2218 | emit_movimm(imm[i],t); | |
2219 | } | |
2220 | } | |
2221 | } | |
2222 | } | |
2223 | if(opcode[i]==0x18||opcode[i]==0x19) { // DADDI/DADDIU | |
2224 | if(rt1[i]) { | |
2225 | signed char sh,sl,th,tl; | |
2226 | th=get_reg(i_regs->regmap,rt1[i]|64); | |
2227 | tl=get_reg(i_regs->regmap,rt1[i]); | |
2228 | sh=get_reg(i_regs->regmap,rs1[i]|64); | |
2229 | sl=get_reg(i_regs->regmap,rs1[i]); | |
2230 | if(tl>=0) { | |
2231 | if(rs1[i]) { | |
2232 | assert(sh>=0); | |
2233 | assert(sl>=0); | |
2234 | if(th>=0) { | |
2235 | emit_addimm64_32(sh,sl,imm[i],th,tl); | |
2236 | } | |
2237 | else { | |
2238 | emit_addimm(sl,imm[i],tl); | |
2239 | } | |
2240 | } else { | |
2241 | emit_movimm(imm[i],tl); | |
2242 | if(th>=0) emit_movimm(((signed int)imm[i])>>31,th); | |
2243 | } | |
2244 | } | |
2245 | } | |
2246 | } | |
2247 | else if(opcode[i]==0x0a||opcode[i]==0x0b) { // SLTI/SLTIU | |
2248 | if(rt1[i]) { | |
2249 | //assert(rs1[i]!=0); // r0 might be valid, but it's probably a bug | |
2250 | signed char sh,sl,t; | |
2251 | t=get_reg(i_regs->regmap,rt1[i]); | |
2252 | sh=get_reg(i_regs->regmap,rs1[i]|64); | |
2253 | sl=get_reg(i_regs->regmap,rs1[i]); | |
2254 | //assert(t>=0); | |
2255 | if(t>=0) { | |
2256 | if(rs1[i]>0) { | |
2257 | if(sh<0) assert((i_regs->was32>>rs1[i])&1); | |
2258 | if(sh<0||((i_regs->was32>>rs1[i])&1)) { | |
2259 | if(opcode[i]==0x0a) { // SLTI | |
2260 | if(sl<0) { | |
2261 | if(i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t); | |
2262 | emit_slti32(t,imm[i],t); | |
2263 | }else{ | |
2264 | emit_slti32(sl,imm[i],t); | |
2265 | } | |
2266 | } | |
2267 | else { // SLTIU | |
2268 | if(sl<0) { | |
2269 | if(i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t); | |
2270 | emit_sltiu32(t,imm[i],t); | |
2271 | }else{ | |
2272 | emit_sltiu32(sl,imm[i],t); | |
2273 | } | |
2274 | } | |
2275 | }else{ // 64-bit | |
2276 | assert(sl>=0); | |
2277 | if(opcode[i]==0x0a) // SLTI | |
2278 | emit_slti64_32(sh,sl,imm[i],t); | |
2279 | else // SLTIU | |
2280 | emit_sltiu64_32(sh,sl,imm[i],t); | |
2281 | } | |
2282 | }else{ | |
2283 | // SLTI(U) with r0 is just stupid, | |
2284 | // nonetheless examples can be found | |
2285 | if(opcode[i]==0x0a) // SLTI | |
2286 | if(0<imm[i]) emit_movimm(1,t); | |
2287 | else emit_zeroreg(t); | |
2288 | else // SLTIU | |
2289 | { | |
2290 | if(imm[i]) emit_movimm(1,t); | |
2291 | else emit_zeroreg(t); | |
2292 | } | |
2293 | } | |
2294 | } | |
2295 | } | |
2296 | } | |
2297 | else if(opcode[i]>=0x0c&&opcode[i]<=0x0e) { // ANDI/ORI/XORI | |
2298 | if(rt1[i]) { | |
2299 | signed char sh,sl,th,tl; | |
2300 | th=get_reg(i_regs->regmap,rt1[i]|64); | |
2301 | tl=get_reg(i_regs->regmap,rt1[i]); | |
2302 | sh=get_reg(i_regs->regmap,rs1[i]|64); | |
2303 | sl=get_reg(i_regs->regmap,rs1[i]); | |
2304 | if(tl>=0 && !((i_regs->isconst>>tl)&1)) { | |
2305 | if(opcode[i]==0x0c) //ANDI | |
2306 | { | |
2307 | if(rs1[i]) { | |
2308 | if(sl<0) { | |
2309 | if(i_regs->regmap_entry[tl]!=rs1[i]) emit_loadreg(rs1[i],tl); | |
2310 | emit_andimm(tl,imm[i],tl); | |
2311 | }else{ | |
2312 | if(!((i_regs->wasconst>>sl)&1)) | |
2313 | emit_andimm(sl,imm[i],tl); | |
2314 | else | |
2315 | emit_movimm(constmap[i][sl]&imm[i],tl); | |
2316 | } | |
2317 | } | |
2318 | else | |
2319 | emit_zeroreg(tl); | |
2320 | if(th>=0) emit_zeroreg(th); | |
2321 | } | |
2322 | else | |
2323 | { | |
2324 | if(rs1[i]) { | |
2325 | if(sl<0) { | |
2326 | if(i_regs->regmap_entry[tl]!=rs1[i]) emit_loadreg(rs1[i],tl); | |
2327 | } | |
2328 | if(th>=0) { | |
2329 | if(sh<0) { | |
2330 | emit_loadreg(rs1[i]|64,th); | |
2331 | }else{ | |
2332 | emit_mov(sh,th); | |
2333 | } | |
2334 | } | |
581335b0 | 2335 | if(opcode[i]==0x0d) { // ORI |
2336 | if(sl<0) { | |
2337 | emit_orimm(tl,imm[i],tl); | |
2338 | }else{ | |
2339 | if(!((i_regs->wasconst>>sl)&1)) | |
2340 | emit_orimm(sl,imm[i],tl); | |
2341 | else | |
2342 | emit_movimm(constmap[i][sl]|imm[i],tl); | |
2343 | } | |
57871462 | 2344 | } |
581335b0 | 2345 | if(opcode[i]==0x0e) { // XORI |
2346 | if(sl<0) { | |
2347 | emit_xorimm(tl,imm[i],tl); | |
2348 | }else{ | |
2349 | if(!((i_regs->wasconst>>sl)&1)) | |
2350 | emit_xorimm(sl,imm[i],tl); | |
2351 | else | |
2352 | emit_movimm(constmap[i][sl]^imm[i],tl); | |
2353 | } | |
57871462 | 2354 | } |
2355 | } | |
2356 | else { | |
2357 | emit_movimm(imm[i],tl); | |
2358 | if(th>=0) emit_zeroreg(th); | |
2359 | } | |
2360 | } | |
2361 | } | |
2362 | } | |
2363 | } | |
2364 | } | |
2365 | ||
2366 | void shiftimm_assemble(int i,struct regstat *i_regs) | |
2367 | { | |
2368 | if(opcode2[i]<=0x3) // SLL/SRL/SRA | |
2369 | { | |
2370 | if(rt1[i]) { | |
2371 | signed char s,t; | |
2372 | t=get_reg(i_regs->regmap,rt1[i]); | |
2373 | s=get_reg(i_regs->regmap,rs1[i]); | |
2374 | //assert(t>=0); | |
dc49e339 | 2375 | if(t>=0&&!((i_regs->isconst>>t)&1)){ |
57871462 | 2376 | if(rs1[i]==0) |
2377 | { | |
2378 | emit_zeroreg(t); | |
2379 | } | |
2380 | else | |
2381 | { | |
2382 | if(s<0&&i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t); | |
2383 | if(imm[i]) { | |
2384 | if(opcode2[i]==0) // SLL | |
2385 | { | |
2386 | emit_shlimm(s<0?t:s,imm[i],t); | |
2387 | } | |
2388 | if(opcode2[i]==2) // SRL | |
2389 | { | |
2390 | emit_shrimm(s<0?t:s,imm[i],t); | |
2391 | } | |
2392 | if(opcode2[i]==3) // SRA | |
2393 | { | |
2394 | emit_sarimm(s<0?t:s,imm[i],t); | |
2395 | } | |
2396 | }else{ | |
2397 | // Shift by zero | |
2398 | if(s>=0 && s!=t) emit_mov(s,t); | |
2399 | } | |
2400 | } | |
2401 | } | |
2402 | //emit_storereg(rt1[i],t); //DEBUG | |
2403 | } | |
2404 | } | |
2405 | if(opcode2[i]>=0x38&&opcode2[i]<=0x3b) // DSLL/DSRL/DSRA | |
2406 | { | |
2407 | if(rt1[i]) { | |
2408 | signed char sh,sl,th,tl; | |
2409 | th=get_reg(i_regs->regmap,rt1[i]|64); | |
2410 | tl=get_reg(i_regs->regmap,rt1[i]); | |
2411 | sh=get_reg(i_regs->regmap,rs1[i]|64); | |
2412 | sl=get_reg(i_regs->regmap,rs1[i]); | |
2413 | if(tl>=0) { | |
2414 | if(rs1[i]==0) | |
2415 | { | |
2416 | emit_zeroreg(tl); | |
2417 | if(th>=0) emit_zeroreg(th); | |
2418 | } | |
2419 | else | |
2420 | { | |
2421 | assert(sl>=0); | |
2422 | assert(sh>=0); | |
2423 | if(imm[i]) { | |
2424 | if(opcode2[i]==0x38) // DSLL | |
2425 | { | |
2426 | if(th>=0) emit_shldimm(sh,sl,imm[i],th); | |
2427 | emit_shlimm(sl,imm[i],tl); | |
2428 | } | |
2429 | if(opcode2[i]==0x3a) // DSRL | |
2430 | { | |
2431 | emit_shrdimm(sl,sh,imm[i],tl); | |
2432 | if(th>=0) emit_shrimm(sh,imm[i],th); | |
2433 | } | |
2434 | if(opcode2[i]==0x3b) // DSRA | |
2435 | { | |
2436 | emit_shrdimm(sl,sh,imm[i],tl); | |
2437 | if(th>=0) emit_sarimm(sh,imm[i],th); | |
2438 | } | |
2439 | }else{ | |
2440 | // Shift by zero | |
2441 | if(sl!=tl) emit_mov(sl,tl); | |
2442 | if(th>=0&&sh!=th) emit_mov(sh,th); | |
2443 | } | |
2444 | } | |
2445 | } | |
2446 | } | |
2447 | } | |
2448 | if(opcode2[i]==0x3c) // DSLL32 | |
2449 | { | |
2450 | if(rt1[i]) { | |
2451 | signed char sl,tl,th; | |
2452 | tl=get_reg(i_regs->regmap,rt1[i]); | |
2453 | th=get_reg(i_regs->regmap,rt1[i]|64); | |
2454 | sl=get_reg(i_regs->regmap,rs1[i]); | |
2455 | if(th>=0||tl>=0){ | |
2456 | assert(tl>=0); | |
2457 | assert(th>=0); | |
2458 | assert(sl>=0); | |
2459 | emit_mov(sl,th); | |
2460 | emit_zeroreg(tl); | |
2461 | if(imm[i]>32) | |
2462 | { | |
2463 | emit_shlimm(th,imm[i]&31,th); | |
2464 | } | |
2465 | } | |
2466 | } | |
2467 | } | |
2468 | if(opcode2[i]==0x3e) // DSRL32 | |
2469 | { | |
2470 | if(rt1[i]) { | |
2471 | signed char sh,tl,th; | |
2472 | tl=get_reg(i_regs->regmap,rt1[i]); | |
2473 | th=get_reg(i_regs->regmap,rt1[i]|64); | |
2474 | sh=get_reg(i_regs->regmap,rs1[i]|64); | |
2475 | if(tl>=0){ | |
2476 | assert(sh>=0); | |
2477 | emit_mov(sh,tl); | |
2478 | if(th>=0) emit_zeroreg(th); | |
2479 | if(imm[i]>32) | |
2480 | { | |
2481 | emit_shrimm(tl,imm[i]&31,tl); | |
2482 | } | |
2483 | } | |
2484 | } | |
2485 | } | |
2486 | if(opcode2[i]==0x3f) // DSRA32 | |
2487 | { | |
2488 | if(rt1[i]) { | |
2489 | signed char sh,tl; | |
2490 | tl=get_reg(i_regs->regmap,rt1[i]); | |
2491 | sh=get_reg(i_regs->regmap,rs1[i]|64); | |
2492 | if(tl>=0){ | |
2493 | assert(sh>=0); | |
2494 | emit_mov(sh,tl); | |
2495 | if(imm[i]>32) | |
2496 | { | |
2497 | emit_sarimm(tl,imm[i]&31,tl); | |
2498 | } | |
2499 | } | |
2500 | } | |
2501 | } | |
2502 | } | |
2503 | ||
2504 | #ifndef shift_assemble | |
2505 | void shift_assemble(int i,struct regstat *i_regs) | |
2506 | { | |
2507 | printf("Need shift_assemble for this architecture.\n"); | |
2508 | exit(1); | |
2509 | } | |
2510 | #endif | |
2511 | ||
2512 | void load_assemble(int i,struct regstat *i_regs) | |
2513 | { | |
2514 | int s,th,tl,addr,map=-1; | |
2515 | int offset; | |
2516 | int jaddr=0; | |
5bf843dc | 2517 | int memtarget=0,c=0; |
b1570849 | 2518 | int fastload_reg_override=0; |
57871462 | 2519 | u_int hr,reglist=0; |
2520 | th=get_reg(i_regs->regmap,rt1[i]|64); | |
2521 | tl=get_reg(i_regs->regmap,rt1[i]); | |
2522 | s=get_reg(i_regs->regmap,rs1[i]); | |
2523 | offset=imm[i]; | |
2524 | for(hr=0;hr<HOST_REGS;hr++) { | |
2525 | if(i_regs->regmap[hr]>=0) reglist|=1<<hr; | |
2526 | } | |
2527 | if(i_regs->regmap[HOST_CCREG]==CCREG) reglist&=~(1<<HOST_CCREG); | |
2528 | if(s>=0) { | |
2529 | c=(i_regs->wasconst>>s)&1; | |
af4ee1fe | 2530 | if (c) { |
2531 | memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE; | |
af4ee1fe | 2532 | } |
57871462 | 2533 | } |
57871462 | 2534 | //printf("load_assemble: c=%d\n",c); |
2535 | //if(c) printf("load_assemble: const=%x\n",(int)constmap[i][s]+offset); | |
2536 | // FIXME: Even if the load is a NOP, we should check for pagefaults... | |
581335b0 | 2537 | if((tl<0&&(!c||(((u_int)constmap[i][s]+offset)>>16)==0x1f80)) |
f18c0f46 | 2538 | ||rt1[i]==0) { |
5bf843dc | 2539 | // could be FIFO, must perform the read |
f18c0f46 | 2540 | // ||dummy read |
5bf843dc | 2541 | assem_debug("(forced read)\n"); |
2542 | tl=get_reg(i_regs->regmap,-1); | |
2543 | assert(tl>=0); | |
5bf843dc | 2544 | } |
2545 | if(offset||s<0||c) addr=tl; | |
2546 | else addr=s; | |
535d208a | 2547 | //if(tl<0) tl=get_reg(i_regs->regmap,-1); |
2548 | if(tl>=0) { | |
2549 | //printf("load_assemble: c=%d\n",c); | |
2550 | //if(c) printf("load_assemble: const=%x\n",(int)constmap[i][s]+offset); | |
2551 | assert(tl>=0); // Even if the load is a NOP, we must check for pagefaults and I/O | |
2552 | reglist&=~(1<<tl); | |
2553 | if(th>=0) reglist&=~(1<<th); | |
1edfcc68 | 2554 | if(!c) { |
2555 | #ifdef RAM_OFFSET | |
2556 | map=get_reg(i_regs->regmap,ROREG); | |
2557 | if(map<0) emit_loadreg(ROREG,map=HOST_TEMPREG); | |
2558 | #endif | |
2559 | #ifdef R29_HACK | |
2560 | // Strmnnrmn's speed hack | |
2561 | if(rs1[i]!=29||start<0x80001000||start>=0x80000000+RAM_SIZE) | |
2562 | #endif | |
2563 | { | |
2564 | jaddr=emit_fastpath_cmp_jump(i,addr,&fastload_reg_override); | |
535d208a | 2565 | } |
1edfcc68 | 2566 | } |
2567 | else if(ram_offset&&memtarget) { | |
2568 | emit_addimm(addr,ram_offset,HOST_TEMPREG); | |
2569 | fastload_reg_override=HOST_TEMPREG; | |
535d208a | 2570 | } |
2571 | int dummy=(rt1[i]==0)||(tl!=get_reg(i_regs->regmap,rt1[i])); // ignore loads to r0 and unneeded reg | |
2572 | if (opcode[i]==0x20) { // LB | |
2573 | if(!c||memtarget) { | |
2574 | if(!dummy) { | |
57871462 | 2575 | #ifdef HOST_IMM_ADDR32 |
2576 | if(c) | |
2577 | emit_movsbl_tlb((constmap[i][s]+offset)^3,map,tl); | |
2578 | else | |
2579 | #endif | |
2580 | { | |
2581 | //emit_xorimm(addr,3,tl); | |
57871462 | 2582 | //emit_movsbl_indexed((int)rdram-0x80000000,tl,tl); |
535d208a | 2583 | int x=0,a=tl; |
2002a1db | 2584 | #ifdef BIG_ENDIAN_MIPS |
57871462 | 2585 | if(!c) emit_xorimm(addr,3,tl); |
2586 | else x=((constmap[i][s]+offset)^3)-(constmap[i][s]+offset); | |
2002a1db | 2587 | #else |
535d208a | 2588 | if(!c) a=addr; |
dadf55f2 | 2589 | #endif |
b1570849 | 2590 | if(fastload_reg_override) a=fastload_reg_override; |
2591 | ||
535d208a | 2592 | emit_movsbl_indexed_tlb(x,a,map,tl); |
57871462 | 2593 | } |
57871462 | 2594 | } |
535d208a | 2595 | if(jaddr) |
2596 | add_stub(LOADB_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist); | |
57871462 | 2597 | } |
535d208a | 2598 | else |
2599 | inline_readstub(LOADB_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist); | |
2600 | } | |
2601 | if (opcode[i]==0x21) { // LH | |
2602 | if(!c||memtarget) { | |
2603 | if(!dummy) { | |
57871462 | 2604 | #ifdef HOST_IMM_ADDR32 |
2605 | if(c) | |
2606 | emit_movswl_tlb((constmap[i][s]+offset)^2,map,tl); | |
2607 | else | |
2608 | #endif | |
2609 | { | |
535d208a | 2610 | int x=0,a=tl; |
2002a1db | 2611 | #ifdef BIG_ENDIAN_MIPS |
57871462 | 2612 | if(!c) emit_xorimm(addr,2,tl); |
2613 | else x=((constmap[i][s]+offset)^2)-(constmap[i][s]+offset); | |
2002a1db | 2614 | #else |
535d208a | 2615 | if(!c) a=addr; |
dadf55f2 | 2616 | #endif |
b1570849 | 2617 | if(fastload_reg_override) a=fastload_reg_override; |
57871462 | 2618 | //#ifdef |
2619 | //emit_movswl_indexed_tlb(x,tl,map,tl); | |
2620 | //else | |
2621 | if(map>=0) { | |
535d208a | 2622 | emit_movswl_indexed(x,a,tl); |
2623 | }else{ | |
a327ad27 | 2624 | #if 1 //def RAM_OFFSET |
535d208a | 2625 | emit_movswl_indexed(x,a,tl); |
2626 | #else | |
2627 | emit_movswl_indexed((int)rdram-0x80000000+x,a,tl); | |
2628 | #endif | |
2629 | } | |
57871462 | 2630 | } |
57871462 | 2631 | } |
535d208a | 2632 | if(jaddr) |
2633 | add_stub(LOADH_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist); | |
57871462 | 2634 | } |
535d208a | 2635 | else |
2636 | inline_readstub(LOADH_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist); | |
2637 | } | |
2638 | if (opcode[i]==0x23) { // LW | |
2639 | if(!c||memtarget) { | |
2640 | if(!dummy) { | |
dadf55f2 | 2641 | int a=addr; |
b1570849 | 2642 | if(fastload_reg_override) a=fastload_reg_override; |
57871462 | 2643 | //emit_readword_indexed((int)rdram-0x80000000,addr,tl); |
2644 | #ifdef HOST_IMM_ADDR32 | |
2645 | if(c) | |
2646 | emit_readword_tlb(constmap[i][s]+offset,map,tl); | |
2647 | else | |
2648 | #endif | |
dadf55f2 | 2649 | emit_readword_indexed_tlb(0,a,map,tl); |
57871462 | 2650 | } |
535d208a | 2651 | if(jaddr) |
2652 | add_stub(LOADW_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist); | |
57871462 | 2653 | } |
535d208a | 2654 | else |
2655 | inline_readstub(LOADW_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist); | |
2656 | } | |
2657 | if (opcode[i]==0x24) { // LBU | |
2658 | if(!c||memtarget) { | |
2659 | if(!dummy) { | |
57871462 | 2660 | #ifdef HOST_IMM_ADDR32 |
2661 | if(c) | |
2662 | emit_movzbl_tlb((constmap[i][s]+offset)^3,map,tl); | |
2663 | else | |
2664 | #endif | |
2665 | { | |
2666 | //emit_xorimm(addr,3,tl); | |
57871462 | 2667 | //emit_movzbl_indexed((int)rdram-0x80000000,tl,tl); |
535d208a | 2668 | int x=0,a=tl; |
2002a1db | 2669 | #ifdef BIG_ENDIAN_MIPS |
57871462 | 2670 | if(!c) emit_xorimm(addr,3,tl); |
2671 | else x=((constmap[i][s]+offset)^3)-(constmap[i][s]+offset); | |
2002a1db | 2672 | #else |
535d208a | 2673 | if(!c) a=addr; |
dadf55f2 | 2674 | #endif |
b1570849 | 2675 | if(fastload_reg_override) a=fastload_reg_override; |
2676 | ||
535d208a | 2677 | emit_movzbl_indexed_tlb(x,a,map,tl); |
57871462 | 2678 | } |
57871462 | 2679 | } |
535d208a | 2680 | if(jaddr) |
2681 | add_stub(LOADBU_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist); | |
57871462 | 2682 | } |
535d208a | 2683 | else |
2684 | inline_readstub(LOADBU_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist); | |
2685 | } | |
2686 | if (opcode[i]==0x25) { // LHU | |
2687 | if(!c||memtarget) { | |
2688 | if(!dummy) { | |
57871462 | 2689 | #ifdef HOST_IMM_ADDR32 |
2690 | if(c) | |
2691 | emit_movzwl_tlb((constmap[i][s]+offset)^2,map,tl); | |
2692 | else | |
2693 | #endif | |
2694 | { | |
535d208a | 2695 | int x=0,a=tl; |
2002a1db | 2696 | #ifdef BIG_ENDIAN_MIPS |
57871462 | 2697 | if(!c) emit_xorimm(addr,2,tl); |
2698 | else x=((constmap[i][s]+offset)^2)-(constmap[i][s]+offset); | |
2002a1db | 2699 | #else |
535d208a | 2700 | if(!c) a=addr; |
dadf55f2 | 2701 | #endif |
b1570849 | 2702 | if(fastload_reg_override) a=fastload_reg_override; |
57871462 | 2703 | //#ifdef |
2704 | //emit_movzwl_indexed_tlb(x,tl,map,tl); | |
2705 | //#else | |
2706 | if(map>=0) { | |
535d208a | 2707 | emit_movzwl_indexed(x,a,tl); |
2708 | }else{ | |
a327ad27 | 2709 | #if 1 //def RAM_OFFSET |
535d208a | 2710 | emit_movzwl_indexed(x,a,tl); |
2711 | #else | |
2712 | emit_movzwl_indexed((int)rdram-0x80000000+x,a,tl); | |
2713 | #endif | |
2714 | } | |
57871462 | 2715 | } |
2716 | } | |
535d208a | 2717 | if(jaddr) |
2718 | add_stub(LOADHU_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist); | |
57871462 | 2719 | } |
535d208a | 2720 | else |
2721 | inline_readstub(LOADHU_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist); | |
2722 | } | |
2723 | if (opcode[i]==0x27) { // LWU | |
2724 | assert(th>=0); | |
2725 | if(!c||memtarget) { | |
2726 | if(!dummy) { | |
dadf55f2 | 2727 | int a=addr; |
b1570849 | 2728 | if(fastload_reg_override) a=fastload_reg_override; |
57871462 | 2729 | //emit_readword_indexed((int)rdram-0x80000000,addr,tl); |
2730 | #ifdef HOST_IMM_ADDR32 | |
2731 | if(c) | |
2732 | emit_readword_tlb(constmap[i][s]+offset,map,tl); | |
2733 | else | |
2734 | #endif | |
dadf55f2 | 2735 | emit_readword_indexed_tlb(0,a,map,tl); |
57871462 | 2736 | } |
535d208a | 2737 | if(jaddr) |
2738 | add_stub(LOADW_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist); | |
2739 | } | |
2740 | else { | |
2741 | inline_readstub(LOADW_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist); | |
57871462 | 2742 | } |
535d208a | 2743 | emit_zeroreg(th); |
2744 | } | |
2745 | if (opcode[i]==0x37) { // LD | |
2746 | if(!c||memtarget) { | |
2747 | if(!dummy) { | |
dadf55f2 | 2748 | int a=addr; |
b1570849 | 2749 | if(fastload_reg_override) a=fastload_reg_override; |
57871462 | 2750 | //if(th>=0) emit_readword_indexed((int)rdram-0x80000000,addr,th); |
2751 | //emit_readword_indexed((int)rdram-0x7FFFFFFC,addr,tl); | |
2752 | #ifdef HOST_IMM_ADDR32 | |
2753 | if(c) | |
2754 | emit_readdword_tlb(constmap[i][s]+offset,map,th,tl); | |
2755 | else | |
2756 | #endif | |
dadf55f2 | 2757 | emit_readdword_indexed_tlb(0,a,map,th,tl); |
57871462 | 2758 | } |
535d208a | 2759 | if(jaddr) |
2760 | add_stub(LOADD_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist); | |
57871462 | 2761 | } |
535d208a | 2762 | else |
2763 | inline_readstub(LOADD_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist); | |
57871462 | 2764 | } |
535d208a | 2765 | } |
2766 | //emit_storereg(rt1[i],tl); // DEBUG | |
57871462 | 2767 | //if(opcode[i]==0x23) |
2768 | //if(opcode[i]==0x24) | |
2769 | //if(opcode[i]==0x23||opcode[i]==0x24) | |
2770 | /*if(opcode[i]==0x21||opcode[i]==0x23||opcode[i]==0x24) | |
2771 | { | |
2772 | //emit_pusha(); | |
2773 | save_regs(0x100f); | |
2774 | emit_readword((int)&last_count,ECX); | |
2775 | #ifdef __i386__ | |
2776 | if(get_reg(i_regs->regmap,CCREG)<0) | |
2777 | emit_loadreg(CCREG,HOST_CCREG); | |
2778 | emit_add(HOST_CCREG,ECX,HOST_CCREG); | |
2779 | emit_addimm(HOST_CCREG,2*ccadj[i],HOST_CCREG); | |
2780 | emit_writeword(HOST_CCREG,(int)&Count); | |
2781 | #endif | |
2782 | #ifdef __arm__ | |
2783 | if(get_reg(i_regs->regmap,CCREG)<0) | |
2784 | emit_loadreg(CCREG,0); | |
2785 | else | |
2786 | emit_mov(HOST_CCREG,0); | |
2787 | emit_add(0,ECX,0); | |
2788 | emit_addimm(0,2*ccadj[i],0); | |
2789 | emit_writeword(0,(int)&Count); | |
2790 | #endif | |
2791 | emit_call((int)memdebug); | |
2792 | //emit_popa(); | |
2793 | restore_regs(0x100f); | |
581335b0 | 2794 | }*/ |
57871462 | 2795 | } |
2796 | ||
2797 | #ifndef loadlr_assemble | |
2798 | void loadlr_assemble(int i,struct regstat *i_regs) | |
2799 | { | |
2800 | printf("Need loadlr_assemble for this architecture.\n"); | |
2801 | exit(1); | |
2802 | } | |
2803 | #endif | |
2804 | ||
2805 | void store_assemble(int i,struct regstat *i_regs) | |
2806 | { | |
2807 | int s,th,tl,map=-1; | |
2808 | int addr,temp; | |
2809 | int offset; | |
581335b0 | 2810 | int jaddr=0,type; |
666a299d | 2811 | int memtarget=0,c=0; |
57871462 | 2812 | int agr=AGEN1+(i&1); |
b1570849 | 2813 | int faststore_reg_override=0; |
57871462 | 2814 | u_int hr,reglist=0; |
2815 | th=get_reg(i_regs->regmap,rs2[i]|64); | |
2816 | tl=get_reg(i_regs->regmap,rs2[i]); | |
2817 | s=get_reg(i_regs->regmap,rs1[i]); | |
2818 | temp=get_reg(i_regs->regmap,agr); | |
2819 | if(temp<0) temp=get_reg(i_regs->regmap,-1); | |
2820 | offset=imm[i]; | |
2821 | if(s>=0) { | |
2822 | c=(i_regs->wasconst>>s)&1; | |
af4ee1fe | 2823 | if(c) { |
2824 | memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE; | |
af4ee1fe | 2825 | } |
57871462 | 2826 | } |
2827 | assert(tl>=0); | |
2828 | assert(temp>=0); | |
2829 | for(hr=0;hr<HOST_REGS;hr++) { | |
2830 | if(i_regs->regmap[hr]>=0) reglist|=1<<hr; | |
2831 | } | |
2832 | if(i_regs->regmap[HOST_CCREG]==CCREG) reglist&=~(1<<HOST_CCREG); | |
2833 | if(offset||s<0||c) addr=temp; | |
2834 | else addr=s; | |
1edfcc68 | 2835 | if(!c) { |
2836 | jaddr=emit_fastpath_cmp_jump(i,addr,&faststore_reg_override); | |
2837 | } | |
2838 | else if(ram_offset&&memtarget) { | |
2839 | emit_addimm(addr,ram_offset,HOST_TEMPREG); | |
2840 | faststore_reg_override=HOST_TEMPREG; | |
57871462 | 2841 | } |
2842 | ||
2843 | if (opcode[i]==0x28) { // SB | |
2844 | if(!c||memtarget) { | |
97a238a6 | 2845 | int x=0,a=temp; |
2002a1db | 2846 | #ifdef BIG_ENDIAN_MIPS |
57871462 | 2847 | if(!c) emit_xorimm(addr,3,temp); |
2848 | else x=((constmap[i][s]+offset)^3)-(constmap[i][s]+offset); | |
2002a1db | 2849 | #else |
97a238a6 | 2850 | if(!c) a=addr; |
dadf55f2 | 2851 | #endif |
b1570849 | 2852 | if(faststore_reg_override) a=faststore_reg_override; |
57871462 | 2853 | //emit_writebyte_indexed(tl,(int)rdram-0x80000000,temp); |
97a238a6 | 2854 | emit_writebyte_indexed_tlb(tl,x,a,map,a); |
57871462 | 2855 | } |
2856 | type=STOREB_STUB; | |
2857 | } | |
2858 | if (opcode[i]==0x29) { // SH | |
2859 | if(!c||memtarget) { | |
97a238a6 | 2860 | int x=0,a=temp; |
2002a1db | 2861 | #ifdef BIG_ENDIAN_MIPS |
57871462 | 2862 | if(!c) emit_xorimm(addr,2,temp); |
2863 | else x=((constmap[i][s]+offset)^2)-(constmap[i][s]+offset); | |
2002a1db | 2864 | #else |
97a238a6 | 2865 | if(!c) a=addr; |
dadf55f2 | 2866 | #endif |
b1570849 | 2867 | if(faststore_reg_override) a=faststore_reg_override; |
57871462 | 2868 | //#ifdef |
2869 | //emit_writehword_indexed_tlb(tl,x,temp,map,temp); | |
2870 | //#else | |
2871 | if(map>=0) { | |
97a238a6 | 2872 | emit_writehword_indexed(tl,x,a); |
57871462 | 2873 | }else |
a327ad27 | 2874 | //emit_writehword_indexed(tl,(int)rdram-0x80000000+x,a); |
2875 | emit_writehword_indexed(tl,x,a); | |
57871462 | 2876 | } |
2877 | type=STOREH_STUB; | |
2878 | } | |
2879 | if (opcode[i]==0x2B) { // SW | |
dadf55f2 | 2880 | if(!c||memtarget) { |
2881 | int a=addr; | |
b1570849 | 2882 | if(faststore_reg_override) a=faststore_reg_override; |
57871462 | 2883 | //emit_writeword_indexed(tl,(int)rdram-0x80000000,addr); |
dadf55f2 | 2884 | emit_writeword_indexed_tlb(tl,0,a,map,temp); |
2885 | } | |
57871462 | 2886 | type=STOREW_STUB; |
2887 | } | |
2888 | if (opcode[i]==0x3F) { // SD | |
2889 | if(!c||memtarget) { | |
dadf55f2 | 2890 | int a=addr; |
b1570849 | 2891 | if(faststore_reg_override) a=faststore_reg_override; |
57871462 | 2892 | if(rs2[i]) { |
2893 | assert(th>=0); | |
2894 | //emit_writeword_indexed(th,(int)rdram-0x80000000,addr); | |
2895 | //emit_writeword_indexed(tl,(int)rdram-0x7FFFFFFC,addr); | |
dadf55f2 | 2896 | emit_writedword_indexed_tlb(th,tl,0,a,map,temp); |
57871462 | 2897 | }else{ |
2898 | // Store zero | |
2899 | //emit_writeword_indexed(tl,(int)rdram-0x80000000,temp); | |
2900 | //emit_writeword_indexed(tl,(int)rdram-0x7FFFFFFC,temp); | |
dadf55f2 | 2901 | emit_writedword_indexed_tlb(tl,tl,0,a,map,temp); |
57871462 | 2902 | } |
2903 | } | |
2904 | type=STORED_STUB; | |
2905 | } | |
b96d3df7 | 2906 | if(jaddr) { |
2907 | // PCSX store handlers don't check invcode again | |
2908 | reglist|=1<<addr; | |
2909 | add_stub(type,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist); | |
2910 | jaddr=0; | |
2911 | } | |
1edfcc68 | 2912 | if(!(i_regs->waswritten&(1<<rs1[i]))&&!(new_dynarec_hacks&NDHACK_NO_SMC_CHECK)) { |
57871462 | 2913 | if(!c||memtarget) { |
2914 | #ifdef DESTRUCTIVE_SHIFT | |
2915 | // The x86 shift operation is 'destructive'; it overwrites the | |
2916 | // source register, so we need to make a copy first and use that. | |
2917 | addr=temp; | |
2918 | #endif | |
2919 | #if defined(HOST_IMM8) | |
2920 | int ir=get_reg(i_regs->regmap,INVCP); | |
2921 | assert(ir>=0); | |
2922 | emit_cmpmem_indexedsr12_reg(ir,addr,1); | |
2923 | #else | |
2924 | emit_cmpmem_indexedsr12_imm((int)invalid_code,addr,1); | |
2925 | #endif | |
0bbd1454 | 2926 | #if defined(HAVE_CONDITIONAL_CALL) && !defined(DESTRUCTIVE_SHIFT) |
2927 | emit_callne(invalidate_addr_reg[addr]); | |
2928 | #else | |
581335b0 | 2929 | int jaddr2=(int)out; |
57871462 | 2930 | emit_jne(0); |
2931 | add_stub(INVCODE_STUB,jaddr2,(int)out,reglist|(1<<HOST_CCREG),addr,0,0,0); | |
0bbd1454 | 2932 | #endif |
57871462 | 2933 | } |
2934 | } | |
7a518516 | 2935 | u_int addr_val=constmap[i][s]+offset; |
3eaa7048 | 2936 | if(jaddr) { |
2937 | add_stub(type,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist); | |
2938 | } else if(c&&!memtarget) { | |
7a518516 | 2939 | inline_writestub(type,i,addr_val,i_regs->regmap,rs2[i],ccadj[i],reglist); |
2940 | } | |
2941 | // basic current block modification detection.. | |
2942 | // not looking back as that should be in mips cache already | |
2943 | if(c&&start+i*4<addr_val&&addr_val<start+slen*4) { | |
c43b5311 | 2944 | SysPrintf("write to %08x hits block %08x, pc=%08x\n",addr_val,start,start+i*4); |
7a518516 | 2945 | assert(i_regs->regmap==regs[i].regmap); // not delay slot |
2946 | if(i_regs->regmap==regs[i].regmap) { | |
2947 | load_all_consts(regs[i].regmap_entry,regs[i].was32,regs[i].wasdirty,i); | |
2948 | wb_dirtys(regs[i].regmap_entry,regs[i].was32,regs[i].wasdirty); | |
2949 | emit_movimm(start+i*4+4,0); | |
2950 | emit_writeword(0,(int)&pcaddr); | |
2951 | emit_jmp((int)do_interrupt); | |
2952 | } | |
3eaa7048 | 2953 | } |
57871462 | 2954 | //if(opcode[i]==0x2B || opcode[i]==0x3F) |
2955 | //if(opcode[i]==0x2B || opcode[i]==0x28) | |
2956 | //if(opcode[i]==0x2B || opcode[i]==0x29) | |
2957 | //if(opcode[i]==0x2B) | |
2958 | /*if(opcode[i]==0x2B || opcode[i]==0x28 || opcode[i]==0x29 || opcode[i]==0x3F) | |
2959 | { | |
28d74ee8 | 2960 | #ifdef __i386__ |
2961 | emit_pusha(); | |
2962 | #endif | |
2963 | #ifdef __arm__ | |
57871462 | 2964 | save_regs(0x100f); |
28d74ee8 | 2965 | #endif |
57871462 | 2966 | emit_readword((int)&last_count,ECX); |
2967 | #ifdef __i386__ | |
2968 | if(get_reg(i_regs->regmap,CCREG)<0) | |
2969 | emit_loadreg(CCREG,HOST_CCREG); | |
2970 | emit_add(HOST_CCREG,ECX,HOST_CCREG); | |
2971 | emit_addimm(HOST_CCREG,2*ccadj[i],HOST_CCREG); | |
2972 | emit_writeword(HOST_CCREG,(int)&Count); | |
2973 | #endif | |
2974 | #ifdef __arm__ | |
2975 | if(get_reg(i_regs->regmap,CCREG)<0) | |
2976 | emit_loadreg(CCREG,0); | |
2977 | else | |
2978 | emit_mov(HOST_CCREG,0); | |
2979 | emit_add(0,ECX,0); | |
2980 | emit_addimm(0,2*ccadj[i],0); | |
2981 | emit_writeword(0,(int)&Count); | |
2982 | #endif | |
2983 | emit_call((int)memdebug); | |
28d74ee8 | 2984 | #ifdef __i386__ |
2985 | emit_popa(); | |
2986 | #endif | |
2987 | #ifdef __arm__ | |
57871462 | 2988 | restore_regs(0x100f); |
28d74ee8 | 2989 | #endif |
581335b0 | 2990 | }*/ |
57871462 | 2991 | } |
2992 | ||
2993 | void storelr_assemble(int i,struct regstat *i_regs) | |
2994 | { | |
2995 | int s,th,tl; | |
2996 | int temp; | |
581335b0 | 2997 | int temp2=-1; |
57871462 | 2998 | int offset; |
581335b0 | 2999 | int jaddr=0; |
57871462 | 3000 | int case1,case2,case3; |
3001 | int done0,done1,done2; | |
af4ee1fe | 3002 | int memtarget=0,c=0; |
fab5d06d | 3003 | int agr=AGEN1+(i&1); |
57871462 | 3004 | u_int hr,reglist=0; |
3005 | th=get_reg(i_regs->regmap,rs2[i]|64); | |
3006 | tl=get_reg(i_regs->regmap,rs2[i]); | |
3007 | s=get_reg(i_regs->regmap,rs1[i]); | |
fab5d06d | 3008 | temp=get_reg(i_regs->regmap,agr); |
3009 | if(temp<0) temp=get_reg(i_regs->regmap,-1); | |
57871462 | 3010 | offset=imm[i]; |
3011 | if(s>=0) { | |
3012 | c=(i_regs->isconst>>s)&1; | |
af4ee1fe | 3013 | if(c) { |
3014 | memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE; | |
af4ee1fe | 3015 | } |
57871462 | 3016 | } |
3017 | assert(tl>=0); | |
3018 | for(hr=0;hr<HOST_REGS;hr++) { | |
3019 | if(i_regs->regmap[hr]>=0) reglist|=1<<hr; | |
3020 | } | |
535d208a | 3021 | assert(temp>=0); |
1edfcc68 | 3022 | if(!c) { |
3023 | emit_cmpimm(s<0||offset?temp:s,RAM_SIZE); | |
3024 | if(!offset&&s!=temp) emit_mov(s,temp); | |
3025 | jaddr=(int)out; | |
3026 | emit_jno(0); | |
3027 | } | |
3028 | else | |
3029 | { | |
3030 | if(!memtarget||!rs1[i]) { | |
535d208a | 3031 | jaddr=(int)out; |
3032 | emit_jmp(0); | |
57871462 | 3033 | } |
535d208a | 3034 | } |
1edfcc68 | 3035 | #ifdef RAM_OFFSET |
3036 | int map=get_reg(i_regs->regmap,ROREG); | |
3037 | if(map<0) emit_loadreg(ROREG,map=HOST_TEMPREG); | |
3038 | #else | |
9f51b4b9 | 3039 | if((u_int)rdram!=0x80000000) |
1edfcc68 | 3040 | emit_addimm_no_flags((u_int)rdram-(u_int)0x80000000,temp); |
3041 | #endif | |
535d208a | 3042 | |
3043 | if (opcode[i]==0x2C||opcode[i]==0x2D) { // SDL/SDR | |
3044 | temp2=get_reg(i_regs->regmap,FTEMP); | |
3045 | if(!rs2[i]) temp2=th=tl; | |
3046 | } | |
57871462 | 3047 | |
2002a1db | 3048 | #ifndef BIG_ENDIAN_MIPS |
3049 | emit_xorimm(temp,3,temp); | |
3050 | #endif | |
535d208a | 3051 | emit_testimm(temp,2); |
3052 | case2=(int)out; | |
3053 | emit_jne(0); | |
3054 | emit_testimm(temp,1); | |
3055 | case1=(int)out; | |
3056 | emit_jne(0); | |
3057 | // 0 | |
3058 | if (opcode[i]==0x2A) { // SWL | |
3059 | emit_writeword_indexed(tl,0,temp); | |
3060 | } | |
3061 | if (opcode[i]==0x2E) { // SWR | |
3062 | emit_writebyte_indexed(tl,3,temp); | |
3063 | } | |
3064 | if (opcode[i]==0x2C) { // SDL | |
3065 | emit_writeword_indexed(th,0,temp); | |
3066 | if(rs2[i]) emit_mov(tl,temp2); | |
3067 | } | |
3068 | if (opcode[i]==0x2D) { // SDR | |
3069 | emit_writebyte_indexed(tl,3,temp); | |
3070 | if(rs2[i]) emit_shldimm(th,tl,24,temp2); | |
3071 | } | |
3072 | done0=(int)out; | |
3073 | emit_jmp(0); | |
3074 | // 1 | |
3075 | set_jump_target(case1,(int)out); | |
3076 | if (opcode[i]==0x2A) { // SWL | |
3077 | // Write 3 msb into three least significant bytes | |
3078 | if(rs2[i]) emit_rorimm(tl,8,tl); | |
3079 | emit_writehword_indexed(tl,-1,temp); | |
3080 | if(rs2[i]) emit_rorimm(tl,16,tl); | |
3081 | emit_writebyte_indexed(tl,1,temp); | |
3082 | if(rs2[i]) emit_rorimm(tl,8,tl); | |
3083 | } | |
3084 | if (opcode[i]==0x2E) { // SWR | |
3085 | // Write two lsb into two most significant bytes | |
3086 | emit_writehword_indexed(tl,1,temp); | |
3087 | } | |
3088 | if (opcode[i]==0x2C) { // SDL | |
3089 | if(rs2[i]) emit_shrdimm(tl,th,8,temp2); | |
3090 | // Write 3 msb into three least significant bytes | |
3091 | if(rs2[i]) emit_rorimm(th,8,th); | |
3092 | emit_writehword_indexed(th,-1,temp); | |
3093 | if(rs2[i]) emit_rorimm(th,16,th); | |
3094 | emit_writebyte_indexed(th,1,temp); | |
3095 | if(rs2[i]) emit_rorimm(th,8,th); | |
3096 | } | |
3097 | if (opcode[i]==0x2D) { // SDR | |
3098 | if(rs2[i]) emit_shldimm(th,tl,16,temp2); | |
3099 | // Write two lsb into two most significant bytes | |
3100 | emit_writehword_indexed(tl,1,temp); | |
3101 | } | |
3102 | done1=(int)out; | |
3103 | emit_jmp(0); | |
3104 | // 2 | |
3105 | set_jump_target(case2,(int)out); | |
3106 | emit_testimm(temp,1); | |
3107 | case3=(int)out; | |
3108 | emit_jne(0); | |
3109 | if (opcode[i]==0x2A) { // SWL | |
3110 | // Write two msb into two least significant bytes | |
3111 | if(rs2[i]) emit_rorimm(tl,16,tl); | |
3112 | emit_writehword_indexed(tl,-2,temp); | |
3113 | if(rs2[i]) emit_rorimm(tl,16,tl); | |
3114 | } | |
3115 | if (opcode[i]==0x2E) { // SWR | |
3116 | // Write 3 lsb into three most significant bytes | |
3117 | emit_writebyte_indexed(tl,-1,temp); | |
3118 | if(rs2[i]) emit_rorimm(tl,8,tl); | |
3119 | emit_writehword_indexed(tl,0,temp); | |
3120 | if(rs2[i]) emit_rorimm(tl,24,tl); | |
3121 | } | |
3122 | if (opcode[i]==0x2C) { // SDL | |
3123 | if(rs2[i]) emit_shrdimm(tl,th,16,temp2); | |
3124 | // Write two msb into two least significant bytes | |
3125 | if(rs2[i]) emit_rorimm(th,16,th); | |
3126 | emit_writehword_indexed(th,-2,temp); | |
3127 | if(rs2[i]) emit_rorimm(th,16,th); | |
3128 | } | |
3129 | if (opcode[i]==0x2D) { // SDR | |
3130 | if(rs2[i]) emit_shldimm(th,tl,8,temp2); | |
3131 | // Write 3 lsb into three most significant bytes | |
3132 | emit_writebyte_indexed(tl,-1,temp); | |
3133 | if(rs2[i]) emit_rorimm(tl,8,tl); | |
3134 | emit_writehword_indexed(tl,0,temp); | |
3135 | if(rs2[i]) emit_rorimm(tl,24,tl); | |
3136 | } | |
3137 | done2=(int)out; | |
3138 | emit_jmp(0); | |
3139 | // 3 | |
3140 | set_jump_target(case3,(int)out); | |
3141 | if (opcode[i]==0x2A) { // SWL | |
3142 | // Write msb into least significant byte | |
3143 | if(rs2[i]) emit_rorimm(tl,24,tl); | |
3144 | emit_writebyte_indexed(tl,-3,temp); | |
3145 | if(rs2[i]) emit_rorimm(tl,8,tl); | |
3146 | } | |
3147 | if (opcode[i]==0x2E) { // SWR | |
3148 | // Write entire word | |
3149 | emit_writeword_indexed(tl,-3,temp); | |
3150 | } | |
3151 | if (opcode[i]==0x2C) { // SDL | |
3152 | if(rs2[i]) emit_shrdimm(tl,th,24,temp2); | |
3153 | // Write msb into least significant byte | |
3154 | if(rs2[i]) emit_rorimm(th,24,th); | |
3155 | emit_writebyte_indexed(th,-3,temp); | |
3156 | if(rs2[i]) emit_rorimm(th,8,th); | |
3157 | } | |
3158 | if (opcode[i]==0x2D) { // SDR | |
3159 | if(rs2[i]) emit_mov(th,temp2); | |
3160 | // Write entire word | |
3161 | emit_writeword_indexed(tl,-3,temp); | |
3162 | } | |
3163 | set_jump_target(done0,(int)out); | |
3164 | set_jump_target(done1,(int)out); | |
3165 | set_jump_target(done2,(int)out); | |
3166 | if (opcode[i]==0x2C) { // SDL | |
3167 | emit_testimm(temp,4); | |
57871462 | 3168 | done0=(int)out; |
57871462 | 3169 | emit_jne(0); |
535d208a | 3170 | emit_andimm(temp,~3,temp); |
3171 | emit_writeword_indexed(temp2,4,temp); | |
3172 | set_jump_target(done0,(int)out); | |
3173 | } | |
3174 | if (opcode[i]==0x2D) { // SDR | |
3175 | emit_testimm(temp,4); | |
3176 | done0=(int)out; | |
3177 | emit_jeq(0); | |
3178 | emit_andimm(temp,~3,temp); | |
3179 | emit_writeword_indexed(temp2,-4,temp); | |
57871462 | 3180 | set_jump_target(done0,(int)out); |
57871462 | 3181 | } |
535d208a | 3182 | if(!c||!memtarget) |
3183 | add_stub(STORELR_STUB,jaddr,(int)out,i,(int)i_regs,temp,ccadj[i],reglist); | |
1edfcc68 | 3184 | if(!(i_regs->waswritten&(1<<rs1[i]))&&!(new_dynarec_hacks&NDHACK_NO_SMC_CHECK)) { |
535d208a | 3185 | #ifdef RAM_OFFSET |
3186 | int map=get_reg(i_regs->regmap,ROREG); | |
3187 | if(map<0) map=HOST_TEMPREG; | |
3188 | gen_orig_addr_w(temp,map); | |
3189 | #else | |
57871462 | 3190 | emit_addimm_no_flags((u_int)0x80000000-(u_int)rdram,temp); |
535d208a | 3191 | #endif |
57871462 | 3192 | #if defined(HOST_IMM8) |
3193 | int ir=get_reg(i_regs->regmap,INVCP); | |
3194 | assert(ir>=0); | |
3195 | emit_cmpmem_indexedsr12_reg(ir,temp,1); | |
3196 | #else | |
3197 | emit_cmpmem_indexedsr12_imm((int)invalid_code,temp,1); | |
3198 | #endif | |
535d208a | 3199 | #if defined(HAVE_CONDITIONAL_CALL) && !defined(DESTRUCTIVE_SHIFT) |
3200 | emit_callne(invalidate_addr_reg[temp]); | |
3201 | #else | |
581335b0 | 3202 | int jaddr2=(int)out; |
57871462 | 3203 | emit_jne(0); |
3204 | add_stub(INVCODE_STUB,jaddr2,(int)out,reglist|(1<<HOST_CCREG),temp,0,0,0); | |
535d208a | 3205 | #endif |
57871462 | 3206 | } |
3207 | /* | |
3208 | emit_pusha(); | |
3209 | //save_regs(0x100f); | |
3210 | emit_readword((int)&last_count,ECX); | |
3211 | if(get_reg(i_regs->regmap,CCREG)<0) | |
3212 | emit_loadreg(CCREG,HOST_CCREG); | |
3213 | emit_add(HOST_CCREG,ECX,HOST_CCREG); | |
3214 | emit_addimm(HOST_CCREG,2*ccadj[i],HOST_CCREG); | |
3215 | emit_writeword(HOST_CCREG,(int)&Count); | |
3216 | emit_call((int)memdebug); | |
3217 | emit_popa(); | |
3218 | //restore_regs(0x100f); | |
581335b0 | 3219 | */ |
57871462 | 3220 | } |
3221 | ||
3222 | void c1ls_assemble(int i,struct regstat *i_regs) | |
3223 | { | |
3d624f89 | 3224 | cop1_unusable(i, i_regs); |
57871462 | 3225 | } |
3226 | ||
b9b61529 | 3227 | void c2ls_assemble(int i,struct regstat *i_regs) |
3228 | { | |
3229 | int s,tl; | |
3230 | int ar; | |
3231 | int offset; | |
1fd1aceb | 3232 | int memtarget=0,c=0; |
581335b0 | 3233 | int jaddr2=0,type; |
b9b61529 | 3234 | int agr=AGEN1+(i&1); |
ffb0b9e0 | 3235 | int fastio_reg_override=0; |
b9b61529 | 3236 | u_int hr,reglist=0; |
3237 | u_int copr=(source[i]>>16)&0x1f; | |
3238 | s=get_reg(i_regs->regmap,rs1[i]); | |
3239 | tl=get_reg(i_regs->regmap,FTEMP); | |
3240 | offset=imm[i]; | |
3241 | assert(rs1[i]>0); | |
3242 | assert(tl>=0); | |
b9b61529 | 3243 | |
3244 | for(hr=0;hr<HOST_REGS;hr++) { | |
3245 | if(i_regs->regmap[hr]>=0) reglist|=1<<hr; | |
3246 | } | |
3247 | if(i_regs->regmap[HOST_CCREG]==CCREG) | |
3248 | reglist&=~(1<<HOST_CCREG); | |
3249 | ||
3250 | // get the address | |
3251 | if (opcode[i]==0x3a) { // SWC2 | |
3252 | ar=get_reg(i_regs->regmap,agr); | |
3253 | if(ar<0) ar=get_reg(i_regs->regmap,-1); | |
3254 | reglist|=1<<ar; | |
3255 | } else { // LWC2 | |
3256 | ar=tl; | |
3257 | } | |
1fd1aceb | 3258 | if(s>=0) c=(i_regs->wasconst>>s)&1; |
3259 | memtarget=c&&(((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE); | |
b9b61529 | 3260 | if (!offset&&!c&&s>=0) ar=s; |
3261 | assert(ar>=0); | |
3262 | ||
3263 | if (opcode[i]==0x3a) { // SWC2 | |
3264 | cop2_get_dreg(copr,tl,HOST_TEMPREG); | |
1fd1aceb | 3265 | type=STOREW_STUB; |
b9b61529 | 3266 | } |
1fd1aceb | 3267 | else |
b9b61529 | 3268 | type=LOADW_STUB; |
1fd1aceb | 3269 | |
3270 | if(c&&!memtarget) { | |
3271 | jaddr2=(int)out; | |
3272 | emit_jmp(0); // inline_readstub/inline_writestub? | |
b9b61529 | 3273 | } |
1fd1aceb | 3274 | else { |
3275 | if(!c) { | |
ffb0b9e0 | 3276 | jaddr2=emit_fastpath_cmp_jump(i,ar,&fastio_reg_override); |
1fd1aceb | 3277 | } |
a327ad27 | 3278 | else if(ram_offset&&memtarget) { |
3279 | emit_addimm(ar,ram_offset,HOST_TEMPREG); | |
3280 | fastio_reg_override=HOST_TEMPREG; | |
3281 | } | |
1fd1aceb | 3282 | if (opcode[i]==0x32) { // LWC2 |
3283 | #ifdef HOST_IMM_ADDR32 | |
3284 | if(c) emit_readword_tlb(constmap[i][s]+offset,-1,tl); | |
3285 | else | |
3286 | #endif | |
ffb0b9e0 | 3287 | int a=ar; |
3288 | if(fastio_reg_override) a=fastio_reg_override; | |
3289 | emit_readword_indexed(0,a,tl); | |
1fd1aceb | 3290 | } |
3291 | if (opcode[i]==0x3a) { // SWC2 | |
3292 | #ifdef DESTRUCTIVE_SHIFT | |
3293 | if(!offset&&!c&&s>=0) emit_mov(s,ar); | |
3294 | #endif | |
ffb0b9e0 | 3295 | int a=ar; |
3296 | if(fastio_reg_override) a=fastio_reg_override; | |
3297 | emit_writeword_indexed(tl,0,a); | |
1fd1aceb | 3298 | } |
b9b61529 | 3299 | } |
3300 | if(jaddr2) | |
3301 | add_stub(type,jaddr2,(int)out,i,ar,(int)i_regs,ccadj[i],reglist); | |
0ff8c62c | 3302 | if(opcode[i]==0x3a) // SWC2 |
3303 | if(!(i_regs->waswritten&(1<<rs1[i]))&&!(new_dynarec_hacks&NDHACK_NO_SMC_CHECK)) { | |
b9b61529 | 3304 | #if defined(HOST_IMM8) |
3305 | int ir=get_reg(i_regs->regmap,INVCP); | |
3306 | assert(ir>=0); | |
3307 | emit_cmpmem_indexedsr12_reg(ir,ar,1); | |
3308 | #else | |
3309 | emit_cmpmem_indexedsr12_imm((int)invalid_code,ar,1); | |
3310 | #endif | |
0bbd1454 | 3311 | #if defined(HAVE_CONDITIONAL_CALL) && !defined(DESTRUCTIVE_SHIFT) |
3312 | emit_callne(invalidate_addr_reg[ar]); | |
3313 | #else | |
581335b0 | 3314 | int jaddr3=(int)out; |
b9b61529 | 3315 | emit_jne(0); |
3316 | add_stub(INVCODE_STUB,jaddr3,(int)out,reglist|(1<<HOST_CCREG),ar,0,0,0); | |
0bbd1454 | 3317 | #endif |
b9b61529 | 3318 | } |
3319 | if (opcode[i]==0x32) { // LWC2 | |
3320 | cop2_put_dreg(copr,tl,HOST_TEMPREG); | |
3321 | } | |
3322 | } | |
3323 | ||
57871462 | 3324 | #ifndef multdiv_assemble |
3325 | void multdiv_assemble(int i,struct regstat *i_regs) | |
3326 | { | |
3327 | printf("Need multdiv_assemble for this architecture.\n"); | |
3328 | exit(1); | |
3329 | } | |
3330 | #endif | |
3331 | ||
3332 | void mov_assemble(int i,struct regstat *i_regs) | |
3333 | { | |
3334 | //if(opcode2[i]==0x10||opcode2[i]==0x12) { // MFHI/MFLO | |
3335 | //if(opcode2[i]==0x11||opcode2[i]==0x13) { // MTHI/MTLO | |
57871462 | 3336 | if(rt1[i]) { |
3337 | signed char sh,sl,th,tl; | |
3338 | th=get_reg(i_regs->regmap,rt1[i]|64); | |
3339 | tl=get_reg(i_regs->regmap,rt1[i]); | |
3340 | //assert(tl>=0); | |
3341 | if(tl>=0) { | |
3342 | sh=get_reg(i_regs->regmap,rs1[i]|64); | |
3343 | sl=get_reg(i_regs->regmap,rs1[i]); | |
3344 | if(sl>=0) emit_mov(sl,tl); | |
3345 | else emit_loadreg(rs1[i],tl); | |
3346 | if(th>=0) { | |
3347 | if(sh>=0) emit_mov(sh,th); | |
3348 | else emit_loadreg(rs1[i]|64,th); | |
3349 | } | |
3350 | } | |
3351 | } | |
3352 | } | |
3353 | ||
3354 | #ifndef fconv_assemble | |
3355 | void fconv_assemble(int i,struct regstat *i_regs) | |
3356 | { | |
3357 | printf("Need fconv_assemble for this architecture.\n"); | |
3358 | exit(1); | |
3359 | } | |
3360 | #endif | |
3361 | ||
3362 | #if 0 | |
3363 | void float_assemble(int i,struct regstat *i_regs) | |
3364 | { | |
3365 | printf("Need float_assemble for this architecture.\n"); | |
3366 | exit(1); | |
3367 | } | |
3368 | #endif | |
3369 | ||
3370 | void syscall_assemble(int i,struct regstat *i_regs) | |
3371 | { | |
3372 | signed char ccreg=get_reg(i_regs->regmap,CCREG); | |
3373 | assert(ccreg==HOST_CCREG); | |
3374 | assert(!is_delayslot); | |
581335b0 | 3375 | (void)ccreg; |
57871462 | 3376 | emit_movimm(start+i*4,EAX); // Get PC |
2573466a | 3377 | emit_addimm(HOST_CCREG,CLOCK_ADJUST(ccadj[i]),HOST_CCREG); // CHECK: is this right? There should probably be an extra cycle... |
7139f3c8 | 3378 | emit_jmp((int)jump_syscall_hle); // XXX |
3379 | } | |
3380 | ||
3381 | void hlecall_assemble(int i,struct regstat *i_regs) | |
3382 | { | |
3383 | signed char ccreg=get_reg(i_regs->regmap,CCREG); | |
3384 | assert(ccreg==HOST_CCREG); | |
3385 | assert(!is_delayslot); | |
581335b0 | 3386 | (void)ccreg; |
7139f3c8 | 3387 | emit_movimm(start+i*4+4,0); // Get PC |
67ba0fb4 | 3388 | emit_movimm((int)psxHLEt[source[i]&7],1); |
2573466a | 3389 | emit_addimm(HOST_CCREG,CLOCK_ADJUST(ccadj[i]),HOST_CCREG); // XXX |
67ba0fb4 | 3390 | emit_jmp((int)jump_hlecall); |
57871462 | 3391 | } |
3392 | ||
1e973cb0 | 3393 | void intcall_assemble(int i,struct regstat *i_regs) |
3394 | { | |
3395 | signed char ccreg=get_reg(i_regs->regmap,CCREG); | |
3396 | assert(ccreg==HOST_CCREG); | |
3397 | assert(!is_delayslot); | |
581335b0 | 3398 | (void)ccreg; |
1e973cb0 | 3399 | emit_movimm(start+i*4,0); // Get PC |
2573466a | 3400 | emit_addimm(HOST_CCREG,CLOCK_ADJUST(ccadj[i]),HOST_CCREG); |
1e973cb0 | 3401 | emit_jmp((int)jump_intcall); |
3402 | } | |
3403 | ||
57871462 | 3404 | void ds_assemble(int i,struct regstat *i_regs) |
3405 | { | |
ffb0b9e0 | 3406 | speculate_register_values(i); |
57871462 | 3407 | is_delayslot=1; |
3408 | switch(itype[i]) { | |
3409 | case ALU: | |
3410 | alu_assemble(i,i_regs);break; | |
3411 | case IMM16: | |
3412 | imm16_assemble(i,i_regs);break; | |
3413 | case SHIFT: | |
3414 | shift_assemble(i,i_regs);break; | |
3415 | case SHIFTIMM: | |
3416 | shiftimm_assemble(i,i_regs);break; | |
3417 | case LOAD: | |
3418 | load_assemble(i,i_regs);break; | |
3419 | case LOADLR: | |
3420 | loadlr_assemble(i,i_regs);break; | |
3421 | case STORE: | |
3422 | store_assemble(i,i_regs);break; | |
3423 | case STORELR: | |
3424 | storelr_assemble(i,i_regs);break; | |
3425 | case COP0: | |
3426 | cop0_assemble(i,i_regs);break; | |
3427 | case COP1: | |
3428 | cop1_assemble(i,i_regs);break; | |
3429 | case C1LS: | |
3430 | c1ls_assemble(i,i_regs);break; | |
b9b61529 | 3431 | case COP2: |
3432 | cop2_assemble(i,i_regs);break; | |
3433 | case C2LS: | |
3434 | c2ls_assemble(i,i_regs);break; | |
3435 | case C2OP: | |
3436 | c2op_assemble(i,i_regs);break; | |
57871462 | 3437 | case FCONV: |
3438 | fconv_assemble(i,i_regs);break; | |
3439 | case FLOAT: | |
3440 | float_assemble(i,i_regs);break; | |
3441 | case FCOMP: | |
3442 | fcomp_assemble(i,i_regs);break; | |
3443 | case MULTDIV: | |
3444 | multdiv_assemble(i,i_regs);break; | |
3445 | case MOV: | |
3446 | mov_assemble(i,i_regs);break; | |
3447 | case SYSCALL: | |
7139f3c8 | 3448 | case HLECALL: |
1e973cb0 | 3449 | case INTCALL: |
57871462 | 3450 | case SPAN: |
3451 | case UJUMP: | |
3452 | case RJUMP: | |
3453 | case CJUMP: | |
3454 | case SJUMP: | |
3455 | case FJUMP: | |
c43b5311 | 3456 | SysPrintf("Jump in the delay slot. This is probably a bug.\n"); |
57871462 | 3457 | } |
3458 | is_delayslot=0; | |
3459 | } | |
3460 | ||
3461 | // Is the branch target a valid internal jump? | |
3462 | int internal_branch(uint64_t i_is32,int addr) | |
3463 | { | |
3464 | if(addr&1) return 0; // Indirect (register) jump | |
3465 | if(addr>=start && addr<start+slen*4-4) | |
3466 | { | |
71e490c5 | 3467 | //int t=(addr-start)>>2; |
57871462 | 3468 | // Delay slots are not valid branch targets |
3469 | //if(t>0&&(itype[t-1]==RJUMP||itype[t-1]==UJUMP||itype[t-1]==CJUMP||itype[t-1]==SJUMP||itype[t-1]==FJUMP)) return 0; | |
3470 | // 64 -> 32 bit transition requires a recompile | |
3471 | /*if(is32[t]&~unneeded_reg_upper[t]&~i_is32) | |
3472 | { | |
3473 | if(requires_32bit[t]&~i_is32) printf("optimizable: no\n"); | |
3474 | else printf("optimizable: yes\n"); | |
3475 | }*/ | |
3476 | //if(is32[t]&~unneeded_reg_upper[t]&~i_is32) return 0; | |
71e490c5 | 3477 | return 1; |
57871462 | 3478 | } |
3479 | return 0; | |
3480 | } | |
3481 | ||
3482 | #ifndef wb_invalidate | |
3483 | void wb_invalidate(signed char pre[],signed char entry[],uint64_t dirty,uint64_t is32, | |
3484 | uint64_t u,uint64_t uu) | |
3485 | { | |
3486 | int hr; | |
3487 | for(hr=0;hr<HOST_REGS;hr++) { | |
3488 | if(hr!=EXCLUDE_REG) { | |
3489 | if(pre[hr]!=entry[hr]) { | |
3490 | if(pre[hr]>=0) { | |
3491 | if((dirty>>hr)&1) { | |
3492 | if(get_reg(entry,pre[hr])<0) { | |
3493 | if(pre[hr]<64) { | |
3494 | if(!((u>>pre[hr])&1)) { | |
3495 | emit_storereg(pre[hr],hr); | |
3496 | if( ((is32>>pre[hr])&1) && !((uu>>pre[hr])&1) ) { | |
3497 | emit_sarimm(hr,31,hr); | |
3498 | emit_storereg(pre[hr]|64,hr); | |
3499 | } | |
3500 | } | |
3501 | }else{ | |
3502 | if(!((uu>>(pre[hr]&63))&1) && !((is32>>(pre[hr]&63))&1)) { | |
3503 | emit_storereg(pre[hr],hr); | |
3504 | } | |
3505 | } | |
3506 | } | |
3507 | } | |
3508 | } | |
3509 | } | |
3510 | } | |
3511 | } | |
3512 | // Move from one register to another (no writeback) | |
3513 | for(hr=0;hr<HOST_REGS;hr++) { | |
3514 | if(hr!=EXCLUDE_REG) { | |
3515 | if(pre[hr]!=entry[hr]) { | |
3516 | if(pre[hr]>=0&&(pre[hr]&63)<TEMPREG) { | |
3517 | int nr; | |
3518 | if((nr=get_reg(entry,pre[hr]))>=0) { | |
3519 | emit_mov(hr,nr); | |
3520 | } | |
3521 | } | |
3522 | } | |
3523 | } | |
3524 | } | |
3525 | } | |
3526 | #endif | |
3527 | ||
3528 | // Load the specified registers | |
3529 | // This only loads the registers given as arguments because | |
3530 | // we don't want to load things that will be overwritten | |
3531 | void load_regs(signed char entry[],signed char regmap[],int is32,int rs1,int rs2) | |
3532 | { | |
3533 | int hr; | |
3534 | // Load 32-bit regs | |
3535 | for(hr=0;hr<HOST_REGS;hr++) { | |
3536 | if(hr!=EXCLUDE_REG&®map[hr]>=0) { | |
3537 | if(entry[hr]!=regmap[hr]) { | |
3538 | if(regmap[hr]==rs1||regmap[hr]==rs2) | |
3539 | { | |
3540 | if(regmap[hr]==0) { | |
3541 | emit_zeroreg(hr); | |
3542 | } | |
3543 | else | |
3544 | { | |
3545 | emit_loadreg(regmap[hr],hr); | |
3546 | } | |
3547 | } | |
3548 | } | |
3549 | } | |
3550 | } | |
3551 | //Load 64-bit regs | |
3552 | for(hr=0;hr<HOST_REGS;hr++) { | |
3553 | if(hr!=EXCLUDE_REG&®map[hr]>=0) { | |
3554 | if(entry[hr]!=regmap[hr]) { | |
3555 | if(regmap[hr]-64==rs1||regmap[hr]-64==rs2) | |
3556 | { | |
3557 | assert(regmap[hr]!=64); | |
3558 | if((is32>>(regmap[hr]&63))&1) { | |
3559 | int lr=get_reg(regmap,regmap[hr]-64); | |
3560 | if(lr>=0) | |
3561 | emit_sarimm(lr,31,hr); | |
3562 | else | |
3563 | emit_loadreg(regmap[hr],hr); | |
3564 | } | |
3565 | else | |
3566 | { | |
3567 | emit_loadreg(regmap[hr],hr); | |
3568 | } | |
3569 | } | |
3570 | } | |
3571 | } | |
3572 | } | |
3573 | } | |
3574 | ||
3575 | // Load registers prior to the start of a loop | |
3576 | // so that they are not loaded within the loop | |
3577 | static void loop_preload(signed char pre[],signed char entry[]) | |
3578 | { | |
3579 | int hr; | |
3580 | for(hr=0;hr<HOST_REGS;hr++) { | |
3581 | if(hr!=EXCLUDE_REG) { | |
3582 | if(pre[hr]!=entry[hr]) { | |
3583 | if(entry[hr]>=0) { | |
3584 | if(get_reg(pre,entry[hr])<0) { | |
3585 | assem_debug("loop preload:\n"); | |
3586 | //printf("loop preload: %d\n",hr); | |
3587 | if(entry[hr]==0) { | |
3588 | emit_zeroreg(hr); | |
3589 | } | |
3590 | else if(entry[hr]<TEMPREG) | |
3591 | { | |
3592 | emit_loadreg(entry[hr],hr); | |
3593 | } | |
3594 | else if(entry[hr]-64<TEMPREG) | |
3595 | { | |
3596 | emit_loadreg(entry[hr],hr); | |
3597 | } | |
3598 | } | |
3599 | } | |
3600 | } | |
3601 | } | |
3602 | } | |
3603 | } | |
3604 | ||
3605 | // Generate address for load/store instruction | |
b9b61529 | 3606 | // goes to AGEN for writes, FTEMP for LOADLR and cop1/2 loads |
57871462 | 3607 | void address_generation(int i,struct regstat *i_regs,signed char entry[]) |
3608 | { | |
b9b61529 | 3609 | if(itype[i]==LOAD||itype[i]==LOADLR||itype[i]==STORE||itype[i]==STORELR||itype[i]==C1LS||itype[i]==C2LS) { |
5194fb95 | 3610 | int ra=-1; |
57871462 | 3611 | int agr=AGEN1+(i&1); |
57871462 | 3612 | if(itype[i]==LOAD) { |
3613 | ra=get_reg(i_regs->regmap,rt1[i]); | |
9f51b4b9 | 3614 | if(ra<0) ra=get_reg(i_regs->regmap,-1); |
535d208a | 3615 | assert(ra>=0); |
57871462 | 3616 | } |
3617 | if(itype[i]==LOADLR) { | |
3618 | ra=get_reg(i_regs->regmap,FTEMP); | |
3619 | } | |
3620 | if(itype[i]==STORE||itype[i]==STORELR) { | |
3621 | ra=get_reg(i_regs->regmap,agr); | |
3622 | if(ra<0) ra=get_reg(i_regs->regmap,-1); | |
3623 | } | |
b9b61529 | 3624 | if(itype[i]==C1LS||itype[i]==C2LS) { |
3625 | if ((opcode[i]&0x3b)==0x31||(opcode[i]&0x3b)==0x32) // LWC1/LDC1/LWC2/LDC2 | |
57871462 | 3626 | ra=get_reg(i_regs->regmap,FTEMP); |
1fd1aceb | 3627 | else { // SWC1/SDC1/SWC2/SDC2 |
57871462 | 3628 | ra=get_reg(i_regs->regmap,agr); |
3629 | if(ra<0) ra=get_reg(i_regs->regmap,-1); | |
3630 | } | |
3631 | } | |
3632 | int rs=get_reg(i_regs->regmap,rs1[i]); | |
57871462 | 3633 | if(ra>=0) { |
3634 | int offset=imm[i]; | |
3635 | int c=(i_regs->wasconst>>rs)&1; | |
3636 | if(rs1[i]==0) { | |
3637 | // Using r0 as a base address | |
57871462 | 3638 | if(!entry||entry[ra]!=agr) { |
3639 | if (opcode[i]==0x22||opcode[i]==0x26) { | |
3640 | emit_movimm(offset&0xFFFFFFFC,ra); // LWL/LWR | |
3641 | }else if (opcode[i]==0x1a||opcode[i]==0x1b) { | |
3642 | emit_movimm(offset&0xFFFFFFF8,ra); // LDL/LDR | |
3643 | }else{ | |
3644 | emit_movimm(offset,ra); | |
3645 | } | |
3646 | } // else did it in the previous cycle | |
3647 | } | |
3648 | else if(rs<0) { | |
3649 | if(!entry||entry[ra]!=rs1[i]) | |
3650 | emit_loadreg(rs1[i],ra); | |
3651 | //if(!entry||entry[ra]!=rs1[i]) | |
3652 | // printf("poor load scheduling!\n"); | |
3653 | } | |
3654 | else if(c) { | |
57871462 | 3655 | if(rs1[i]!=rt1[i]||itype[i]!=LOAD) { |
3656 | if(!entry||entry[ra]!=agr) { | |
3657 | if (opcode[i]==0x22||opcode[i]==0x26) { | |
3658 | emit_movimm((constmap[i][rs]+offset)&0xFFFFFFFC,ra); // LWL/LWR | |
3659 | }else if (opcode[i]==0x1a||opcode[i]==0x1b) { | |
3660 | emit_movimm((constmap[i][rs]+offset)&0xFFFFFFF8,ra); // LDL/LDR | |
3661 | }else{ | |
3662 | #ifdef HOST_IMM_ADDR32 | |
1edfcc68 | 3663 | if((itype[i]!=LOAD&&(opcode[i]&0x3b)!=0x31&&(opcode[i]&0x3b)!=0x32)) // LWC1/LDC1/LWC2/LDC2 |
57871462 | 3664 | #endif |
3665 | emit_movimm(constmap[i][rs]+offset,ra); | |
8575a877 | 3666 | regs[i].loadedconst|=1<<ra; |
57871462 | 3667 | } |
3668 | } // else did it in the previous cycle | |
3669 | } // else load_consts already did it | |
3670 | } | |
3671 | if(offset&&!c&&rs1[i]) { | |
3672 | if(rs>=0) { | |
3673 | emit_addimm(rs,offset,ra); | |
3674 | }else{ | |
3675 | emit_addimm(ra,offset,ra); | |
3676 | } | |
3677 | } | |
3678 | } | |
3679 | } | |
3680 | // Preload constants for next instruction | |
b9b61529 | 3681 | if(itype[i+1]==LOAD||itype[i+1]==LOADLR||itype[i+1]==STORE||itype[i+1]==STORELR||itype[i+1]==C1LS||itype[i+1]==C2LS) { |
57871462 | 3682 | int agr,ra; |
57871462 | 3683 | // Actual address |
3684 | agr=AGEN1+((i+1)&1); | |
3685 | ra=get_reg(i_regs->regmap,agr); | |
3686 | if(ra>=0) { | |
3687 | int rs=get_reg(regs[i+1].regmap,rs1[i+1]); | |
3688 | int offset=imm[i+1]; | |
3689 | int c=(regs[i+1].wasconst>>rs)&1; | |
3690 | if(c&&(rs1[i+1]!=rt1[i+1]||itype[i+1]!=LOAD)) { | |
3691 | if (opcode[i+1]==0x22||opcode[i+1]==0x26) { | |
3692 | emit_movimm((constmap[i+1][rs]+offset)&0xFFFFFFFC,ra); // LWL/LWR | |
3693 | }else if (opcode[i+1]==0x1a||opcode[i+1]==0x1b) { | |
3694 | emit_movimm((constmap[i+1][rs]+offset)&0xFFFFFFF8,ra); // LDL/LDR | |
3695 | }else{ | |
3696 | #ifdef HOST_IMM_ADDR32 | |
1edfcc68 | 3697 | if((itype[i+1]!=LOAD&&(opcode[i+1]&0x3b)!=0x31&&(opcode[i+1]&0x3b)!=0x32)) // LWC1/LDC1/LWC2/LDC2 |
57871462 | 3698 | #endif |
3699 | emit_movimm(constmap[i+1][rs]+offset,ra); | |
8575a877 | 3700 | regs[i+1].loadedconst|=1<<ra; |
57871462 | 3701 | } |
3702 | } | |
3703 | else if(rs1[i+1]==0) { | |
3704 | // Using r0 as a base address | |
3705 | if (opcode[i+1]==0x22||opcode[i+1]==0x26) { | |
3706 | emit_movimm(offset&0xFFFFFFFC,ra); // LWL/LWR | |
3707 | }else if (opcode[i+1]==0x1a||opcode[i+1]==0x1b) { | |
3708 | emit_movimm(offset&0xFFFFFFF8,ra); // LDL/LDR | |
3709 | }else{ | |
3710 | emit_movimm(offset,ra); | |
3711 | } | |
3712 | } | |
3713 | } | |
3714 | } | |
3715 | } | |
3716 | ||
e2b5e7aa | 3717 | static int get_final_value(int hr, int i, int *value) |
57871462 | 3718 | { |
3719 | int reg=regs[i].regmap[hr]; | |
3720 | while(i<slen-1) { | |
3721 | if(regs[i+1].regmap[hr]!=reg) break; | |
3722 | if(!((regs[i+1].isconst>>hr)&1)) break; | |
3723 | if(bt[i+1]) break; | |
3724 | i++; | |
3725 | } | |
3726 | if(i<slen-1) { | |
3727 | if(itype[i]==UJUMP||itype[i]==RJUMP||itype[i]==CJUMP||itype[i]==SJUMP) { | |
3728 | *value=constmap[i][hr]; | |
3729 | return 1; | |
3730 | } | |
3731 | if(!bt[i+1]) { | |
3732 | if(itype[i+1]==UJUMP||itype[i+1]==RJUMP||itype[i+1]==CJUMP||itype[i+1]==SJUMP) { | |
3733 | // Load in delay slot, out-of-order execution | |
3734 | if(itype[i+2]==LOAD&&rs1[i+2]==reg&&rt1[i+2]==reg&&((regs[i+1].wasconst>>hr)&1)) | |
3735 | { | |
57871462 | 3736 | // Precompute load address |
3737 | *value=constmap[i][hr]+imm[i+2]; | |
3738 | return 1; | |
3739 | } | |
3740 | } | |
3741 | if(itype[i+1]==LOAD&&rs1[i+1]==reg&&rt1[i+1]==reg) | |
3742 | { | |
57871462 | 3743 | // Precompute load address |
3744 | *value=constmap[i][hr]+imm[i+1]; | |
3745 | //printf("c=%x imm=%x\n",(int)constmap[i][hr],imm[i+1]); | |
3746 | return 1; | |
3747 | } | |
3748 | } | |
3749 | } | |
3750 | *value=constmap[i][hr]; | |
3751 | //printf("c=%x\n",(int)constmap[i][hr]); | |
3752 | if(i==slen-1) return 1; | |
3753 | if(reg<64) { | |
3754 | return !((unneeded_reg[i+1]>>reg)&1); | |
3755 | }else{ | |
3756 | return !((unneeded_reg_upper[i+1]>>reg)&1); | |
3757 | } | |
3758 | } | |
3759 | ||
3760 | // Load registers with known constants | |
3761 | void load_consts(signed char pre[],signed char regmap[],int is32,int i) | |
3762 | { | |
8575a877 | 3763 | int hr,hr2; |
3764 | // propagate loaded constant flags | |
3765 | if(i==0||bt[i]) | |
3766 | regs[i].loadedconst=0; | |
3767 | else { | |
3768 | for(hr=0;hr<HOST_REGS;hr++) { | |
3769 | if(hr!=EXCLUDE_REG&®map[hr]>=0&&((regs[i-1].isconst>>hr)&1)&&pre[hr]==regmap[hr] | |
3770 | &®map[hr]==regs[i-1].regmap[hr]&&((regs[i-1].loadedconst>>hr)&1)) | |
3771 | { | |
3772 | regs[i].loadedconst|=1<<hr; | |
3773 | } | |
3774 | } | |
3775 | } | |
57871462 | 3776 | // Load 32-bit regs |
3777 | for(hr=0;hr<HOST_REGS;hr++) { | |
3778 | if(hr!=EXCLUDE_REG&®map[hr]>=0) { | |
3779 | //if(entry[hr]!=regmap[hr]) { | |
8575a877 | 3780 | if(!((regs[i].loadedconst>>hr)&1)) { |
57871462 | 3781 | if(((regs[i].isconst>>hr)&1)&®map[hr]<64&®map[hr]>0) { |
8575a877 | 3782 | int value,similar=0; |
57871462 | 3783 | if(get_final_value(hr,i,&value)) { |
8575a877 | 3784 | // see if some other register has similar value |
3785 | for(hr2=0;hr2<HOST_REGS;hr2++) { | |
3786 | if(hr2!=EXCLUDE_REG&&((regs[i].loadedconst>>hr2)&1)) { | |
3787 | if(is_similar_value(value,constmap[i][hr2])) { | |
3788 | similar=1; | |
3789 | break; | |
3790 | } | |
3791 | } | |
3792 | } | |
3793 | if(similar) { | |
3794 | int value2; | |
3795 | if(get_final_value(hr2,i,&value2)) // is this needed? | |
3796 | emit_movimm_from(value2,hr2,value,hr); | |
3797 | else | |
3798 | emit_movimm(value,hr); | |
3799 | } | |
3800 | else if(value==0) { | |
57871462 | 3801 | emit_zeroreg(hr); |
3802 | } | |
3803 | else { | |
3804 | emit_movimm(value,hr); | |
3805 | } | |
3806 | } | |
8575a877 | 3807 | regs[i].loadedconst|=1<<hr; |
57871462 | 3808 | } |
3809 | } | |
3810 | } | |
3811 | } | |
3812 | // Load 64-bit regs | |
3813 | for(hr=0;hr<HOST_REGS;hr++) { | |
3814 | if(hr!=EXCLUDE_REG&®map[hr]>=0) { | |
3815 | //if(entry[hr]!=regmap[hr]) { | |
3816 | if(i==0||!((regs[i-1].isconst>>hr)&1)||pre[hr]!=regmap[hr]||bt[i]) { | |
3817 | if(((regs[i].isconst>>hr)&1)&®map[hr]>64) { | |
3818 | if((is32>>(regmap[hr]&63))&1) { | |
3819 | int lr=get_reg(regmap,regmap[hr]-64); | |
3820 | assert(lr>=0); | |
3821 | emit_sarimm(lr,31,hr); | |
3822 | } | |
3823 | else | |
3824 | { | |
3825 | int value; | |
3826 | if(get_final_value(hr,i,&value)) { | |
3827 | if(value==0) { | |
3828 | emit_zeroreg(hr); | |
3829 | } | |
3830 | else { | |
3831 | emit_movimm(value,hr); | |
3832 | } | |
3833 | } | |
3834 | } | |
3835 | } | |
3836 | } | |
3837 | } | |
3838 | } | |
3839 | } | |
3840 | void load_all_consts(signed char regmap[],int is32,u_int dirty,int i) | |
3841 | { | |
3842 | int hr; | |
3843 | // Load 32-bit regs | |
3844 | for(hr=0;hr<HOST_REGS;hr++) { | |
3845 | if(hr!=EXCLUDE_REG&®map[hr]>=0&&((dirty>>hr)&1)) { | |
3846 | if(((regs[i].isconst>>hr)&1)&®map[hr]<64&®map[hr]>0) { | |
3847 | int value=constmap[i][hr]; | |
3848 | if(value==0) { | |
3849 | emit_zeroreg(hr); | |
3850 | } | |
3851 | else { | |
3852 | emit_movimm(value,hr); | |
3853 | } | |
3854 | } | |
3855 | } | |
3856 | } | |
3857 | // Load 64-bit regs | |
3858 | for(hr=0;hr<HOST_REGS;hr++) { | |
3859 | if(hr!=EXCLUDE_REG&®map[hr]>=0&&((dirty>>hr)&1)) { | |
3860 | if(((regs[i].isconst>>hr)&1)&®map[hr]>64) { | |
3861 | if((is32>>(regmap[hr]&63))&1) { | |
3862 | int lr=get_reg(regmap,regmap[hr]-64); | |
3863 | assert(lr>=0); | |
3864 | emit_sarimm(lr,31,hr); | |
3865 | } | |
3866 | else | |
3867 | { | |
3868 | int value=constmap[i][hr]; | |
3869 | if(value==0) { | |
3870 | emit_zeroreg(hr); | |
3871 | } | |
3872 | else { | |
3873 | emit_movimm(value,hr); | |
3874 | } | |
3875 | } | |
3876 | } | |
3877 | } | |
3878 | } | |
3879 | } | |
3880 | ||
3881 | // Write out all dirty registers (except cycle count) | |
3882 | void wb_dirtys(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty) | |
3883 | { | |
3884 | int hr; | |
3885 | for(hr=0;hr<HOST_REGS;hr++) { | |
3886 | if(hr!=EXCLUDE_REG) { | |
3887 | if(i_regmap[hr]>0) { | |
3888 | if(i_regmap[hr]!=CCREG) { | |
3889 | if((i_dirty>>hr)&1) { | |
3890 | if(i_regmap[hr]<64) { | |
3891 | emit_storereg(i_regmap[hr],hr); | |
57871462 | 3892 | }else{ |
3893 | if( !((i_is32>>(i_regmap[hr]&63))&1) ) { | |
3894 | emit_storereg(i_regmap[hr],hr); | |
3895 | } | |
3896 | } | |
3897 | } | |
3898 | } | |
3899 | } | |
3900 | } | |
3901 | } | |
3902 | } | |
3903 | // Write out dirty registers that we need to reload (pair with load_needed_regs) | |
3904 | // This writes the registers not written by store_regs_bt | |
3905 | void wb_needed_dirtys(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr) | |
3906 | { | |
3907 | int hr; | |
3908 | int t=(addr-start)>>2; | |
3909 | for(hr=0;hr<HOST_REGS;hr++) { | |
3910 | if(hr!=EXCLUDE_REG) { | |
3911 | if(i_regmap[hr]>0) { | |
3912 | if(i_regmap[hr]!=CCREG) { | |
3913 | if(i_regmap[hr]==regs[t].regmap_entry[hr] && ((regs[t].dirty>>hr)&1) && !(((i_is32&~regs[t].was32&~unneeded_reg_upper[t])>>(i_regmap[hr]&63))&1)) { | |
3914 | if((i_dirty>>hr)&1) { | |
3915 | if(i_regmap[hr]<64) { | |
3916 | emit_storereg(i_regmap[hr],hr); | |
57871462 | 3917 | }else{ |
3918 | if( !((i_is32>>(i_regmap[hr]&63))&1) ) { | |
3919 | emit_storereg(i_regmap[hr],hr); | |
3920 | } | |
3921 | } | |
3922 | } | |
3923 | } | |
3924 | } | |
3925 | } | |
3926 | } | |
3927 | } | |
3928 | } | |
3929 | ||
3930 | // Load all registers (except cycle count) | |
3931 | void load_all_regs(signed char i_regmap[]) | |
3932 | { | |
3933 | int hr; | |
3934 | for(hr=0;hr<HOST_REGS;hr++) { | |
3935 | if(hr!=EXCLUDE_REG) { | |
3936 | if(i_regmap[hr]==0) { | |
3937 | emit_zeroreg(hr); | |
3938 | } | |
3939 | else | |
ea3d2e6e | 3940 | if(i_regmap[hr]>0 && (i_regmap[hr]&63)<TEMPREG && i_regmap[hr]!=CCREG) |
57871462 | 3941 | { |
3942 | emit_loadreg(i_regmap[hr],hr); | |
3943 | } | |
3944 | } | |
3945 | } | |
3946 | } | |
3947 | ||
3948 | // Load all current registers also needed by next instruction | |
3949 | void load_needed_regs(signed char i_regmap[],signed char next_regmap[]) | |
3950 | { | |
3951 | int hr; | |
3952 | for(hr=0;hr<HOST_REGS;hr++) { | |
3953 | if(hr!=EXCLUDE_REG) { | |
3954 | if(get_reg(next_regmap,i_regmap[hr])>=0) { | |
3955 | if(i_regmap[hr]==0) { | |
3956 | emit_zeroreg(hr); | |
3957 | } | |
3958 | else | |
ea3d2e6e | 3959 | if(i_regmap[hr]>0 && (i_regmap[hr]&63)<TEMPREG && i_regmap[hr]!=CCREG) |
57871462 | 3960 | { |
3961 | emit_loadreg(i_regmap[hr],hr); | |
3962 | } | |
3963 | } | |
3964 | } | |
3965 | } | |
3966 | } | |
3967 | ||
3968 | // Load all regs, storing cycle count if necessary | |
3969 | void load_regs_entry(int t) | |
3970 | { | |
3971 | int hr; | |
2573466a | 3972 | if(is_ds[t]) emit_addimm(HOST_CCREG,CLOCK_ADJUST(1),HOST_CCREG); |
3973 | else if(ccadj[t]) emit_addimm(HOST_CCREG,-CLOCK_ADJUST(ccadj[t]),HOST_CCREG); | |
57871462 | 3974 | if(regs[t].regmap_entry[HOST_CCREG]!=CCREG) { |
3975 | emit_storereg(CCREG,HOST_CCREG); | |
3976 | } | |
3977 | // Load 32-bit regs | |
3978 | for(hr=0;hr<HOST_REGS;hr++) { | |
ea3d2e6e | 3979 | if(regs[t].regmap_entry[hr]>=0&®s[t].regmap_entry[hr]<TEMPREG) { |
57871462 | 3980 | if(regs[t].regmap_entry[hr]==0) { |
3981 | emit_zeroreg(hr); | |
3982 | } | |
3983 | else if(regs[t].regmap_entry[hr]!=CCREG) | |
3984 | { | |
3985 | emit_loadreg(regs[t].regmap_entry[hr],hr); | |
3986 | } | |
3987 | } | |
3988 | } | |
3989 | // Load 64-bit regs | |
3990 | for(hr=0;hr<HOST_REGS;hr++) { | |
ea3d2e6e | 3991 | if(regs[t].regmap_entry[hr]>=64&®s[t].regmap_entry[hr]<TEMPREG+64) { |
57871462 | 3992 | assert(regs[t].regmap_entry[hr]!=64); |
3993 | if((regs[t].was32>>(regs[t].regmap_entry[hr]&63))&1) { | |
3994 | int lr=get_reg(regs[t].regmap_entry,regs[t].regmap_entry[hr]-64); | |
3995 | if(lr<0) { | |
3996 | emit_loadreg(regs[t].regmap_entry[hr],hr); | |
3997 | } | |
3998 | else | |
3999 | { | |
4000 | emit_sarimm(lr,31,hr); | |
4001 | } | |
4002 | } | |
4003 | else | |
4004 | { | |
4005 | emit_loadreg(regs[t].regmap_entry[hr],hr); | |
4006 | } | |
4007 | } | |
4008 | } | |
4009 | } | |
4010 | ||
4011 | // Store dirty registers prior to branch | |
4012 | void store_regs_bt(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr) | |
4013 | { | |
4014 | if(internal_branch(i_is32,addr)) | |
4015 | { | |
4016 | int t=(addr-start)>>2; | |
4017 | int hr; | |
4018 | for(hr=0;hr<HOST_REGS;hr++) { | |
4019 | if(hr!=EXCLUDE_REG) { | |
4020 | if(i_regmap[hr]>0 && i_regmap[hr]!=CCREG) { | |
4021 | if(i_regmap[hr]!=regs[t].regmap_entry[hr] || !((regs[t].dirty>>hr)&1) || (((i_is32&~regs[t].was32&~unneeded_reg_upper[t])>>(i_regmap[hr]&63))&1)) { | |
4022 | if((i_dirty>>hr)&1) { | |
4023 | if(i_regmap[hr]<64) { | |
4024 | if(!((unneeded_reg[t]>>i_regmap[hr])&1)) { | |
4025 | emit_storereg(i_regmap[hr],hr); | |
4026 | if( ((i_is32>>i_regmap[hr])&1) && !((unneeded_reg_upper[t]>>i_regmap[hr])&1) ) { | |
4027 | #ifdef DESTRUCTIVE_WRITEBACK | |
4028 | emit_sarimm(hr,31,hr); | |
4029 | emit_storereg(i_regmap[hr]|64,hr); | |
4030 | #else | |
4031 | emit_sarimm(hr,31,HOST_TEMPREG); | |
4032 | emit_storereg(i_regmap[hr]|64,HOST_TEMPREG); | |
4033 | #endif | |
4034 | } | |
4035 | } | |
4036 | }else{ | |
4037 | if( !((i_is32>>(i_regmap[hr]&63))&1) && !((unneeded_reg_upper[t]>>(i_regmap[hr]&63))&1) ) { | |
4038 | emit_storereg(i_regmap[hr],hr); | |
4039 | } | |
4040 | } | |
4041 | } | |
4042 | } | |
4043 | } | |
4044 | } | |
4045 | } | |
4046 | } | |
4047 | else | |
4048 | { | |
4049 | // Branch out of this block, write out all dirty regs | |
4050 | wb_dirtys(i_regmap,i_is32,i_dirty); | |
4051 | } | |
4052 | } | |
4053 | ||
4054 | // Load all needed registers for branch target | |
4055 | void load_regs_bt(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr) | |
4056 | { | |
4057 | //if(addr>=start && addr<(start+slen*4)) | |
4058 | if(internal_branch(i_is32,addr)) | |
4059 | { | |
4060 | int t=(addr-start)>>2; | |
4061 | int hr; | |
4062 | // Store the cycle count before loading something else | |
4063 | if(i_regmap[HOST_CCREG]!=CCREG) { | |
4064 | assert(i_regmap[HOST_CCREG]==-1); | |
4065 | } | |
4066 | if(regs[t].regmap_entry[HOST_CCREG]!=CCREG) { | |
4067 | emit_storereg(CCREG,HOST_CCREG); | |
4068 | } | |
4069 | // Load 32-bit regs | |
4070 | for(hr=0;hr<HOST_REGS;hr++) { | |
ea3d2e6e | 4071 | if(hr!=EXCLUDE_REG&®s[t].regmap_entry[hr]>=0&®s[t].regmap_entry[hr]<TEMPREG) { |
57871462 | 4072 | #ifdef DESTRUCTIVE_WRITEBACK |
4073 | if(i_regmap[hr]!=regs[t].regmap_entry[hr] || ( !((regs[t].dirty>>hr)&1) && ((i_dirty>>hr)&1) && (((i_is32&~unneeded_reg_upper[t])>>i_regmap[hr])&1) ) || (((i_is32&~regs[t].was32&~unneeded_reg_upper[t])>>(i_regmap[hr]&63))&1)) { | |
4074 | #else | |
4075 | if(i_regmap[hr]!=regs[t].regmap_entry[hr] ) { | |
4076 | #endif | |
4077 | if(regs[t].regmap_entry[hr]==0) { | |
4078 | emit_zeroreg(hr); | |
4079 | } | |
4080 | else if(regs[t].regmap_entry[hr]!=CCREG) | |
4081 | { | |
4082 | emit_loadreg(regs[t].regmap_entry[hr],hr); | |
4083 | } | |
4084 | } | |
4085 | } | |
4086 | } | |
4087 | //Load 64-bit regs | |
4088 | for(hr=0;hr<HOST_REGS;hr++) { | |
ea3d2e6e | 4089 | if(hr!=EXCLUDE_REG&®s[t].regmap_entry[hr]>=64&®s[t].regmap_entry[hr]<TEMPREG+64) { |
57871462 | 4090 | if(i_regmap[hr]!=regs[t].regmap_entry[hr]) { |
4091 | assert(regs[t].regmap_entry[hr]!=64); | |
4092 | if((i_is32>>(regs[t].regmap_entry[hr]&63))&1) { | |
4093 | int lr=get_reg(regs[t].regmap_entry,regs[t].regmap_entry[hr]-64); | |
4094 | if(lr<0) { | |
4095 | emit_loadreg(regs[t].regmap_entry[hr],hr); | |
4096 | } | |
4097 | else | |
4098 | { | |
4099 | emit_sarimm(lr,31,hr); | |
4100 | } | |
4101 | } | |
4102 | else | |
4103 | { | |
4104 | emit_loadreg(regs[t].regmap_entry[hr],hr); | |
4105 | } | |
4106 | } | |
4107 | else if((i_is32>>(regs[t].regmap_entry[hr]&63))&1) { | |
4108 | int lr=get_reg(regs[t].regmap_entry,regs[t].regmap_entry[hr]-64); | |
4109 | assert(lr>=0); | |
4110 | emit_sarimm(lr,31,hr); | |
4111 | } | |
4112 | } | |
4113 | } | |
4114 | } | |
4115 | } | |
4116 | ||
4117 | int match_bt(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr) | |
4118 | { | |
4119 | if(addr>=start && addr<start+slen*4-4) | |
4120 | { | |
4121 | int t=(addr-start)>>2; | |
4122 | int hr; | |
4123 | if(regs[t].regmap_entry[HOST_CCREG]!=CCREG) return 0; | |
4124 | for(hr=0;hr<HOST_REGS;hr++) | |
4125 | { | |
4126 | if(hr!=EXCLUDE_REG) | |
4127 | { | |
4128 | if(i_regmap[hr]!=regs[t].regmap_entry[hr]) | |
4129 | { | |
ea3d2e6e | 4130 | if(regs[t].regmap_entry[hr]>=0&&(regs[t].regmap_entry[hr]|64)<TEMPREG+64) |
57871462 | 4131 | { |
4132 | return 0; | |
4133 | } | |
9f51b4b9 | 4134 | else |
57871462 | 4135 | if((i_dirty>>hr)&1) |
4136 | { | |
ea3d2e6e | 4137 | if(i_regmap[hr]<TEMPREG) |
57871462 | 4138 | { |
4139 | if(!((unneeded_reg[t]>>i_regmap[hr])&1)) | |
4140 | return 0; | |
4141 | } | |
ea3d2e6e | 4142 | else if(i_regmap[hr]>=64&&i_regmap[hr]<TEMPREG+64) |
57871462 | 4143 | { |
4144 | if(!((unneeded_reg_upper[t]>>(i_regmap[hr]&63))&1)) | |
4145 | return 0; | |
4146 | } | |
4147 | } | |
4148 | } | |
4149 | else // Same register but is it 32-bit or dirty? | |
4150 | if(i_regmap[hr]>=0) | |
4151 | { | |
4152 | if(!((regs[t].dirty>>hr)&1)) | |
4153 | { | |
4154 | if((i_dirty>>hr)&1) | |
4155 | { | |
4156 | if(!((unneeded_reg[t]>>i_regmap[hr])&1)) | |
4157 | { | |
4158 | //printf("%x: dirty no match\n",addr); | |
4159 | return 0; | |
4160 | } | |
4161 | } | |
4162 | } | |
4163 | if((((regs[t].was32^i_is32)&~unneeded_reg_upper[t])>>(i_regmap[hr]&63))&1) | |
4164 | { | |
4165 | //printf("%x: is32 no match\n",addr); | |
4166 | return 0; | |
4167 | } | |
4168 | } | |
4169 | } | |
4170 | } | |
4171 | //if(is32[t]&~unneeded_reg_upper[t]&~i_is32) return 0; | |
57871462 | 4172 | // Delay slots are not valid branch targets |
4173 | //if(t>0&&(itype[t-1]==RJUMP||itype[t-1]==UJUMP||itype[t-1]==CJUMP||itype[t-1]==SJUMP||itype[t-1]==FJUMP)) return 0; | |
4174 | // Delay slots require additional processing, so do not match | |
4175 | if(is_ds[t]) return 0; | |
4176 | } | |
4177 | else | |
4178 | { | |
4179 | int hr; | |
4180 | for(hr=0;hr<HOST_REGS;hr++) | |
4181 | { | |
4182 | if(hr!=EXCLUDE_REG) | |
4183 | { | |
4184 | if(i_regmap[hr]>=0) | |
4185 | { | |
4186 | if(hr!=HOST_CCREG||i_regmap[hr]!=CCREG) | |
4187 | { | |
4188 | if((i_dirty>>hr)&1) | |
4189 | { | |
4190 | return 0; | |
4191 | } | |
4192 | } | |
4193 | } | |
4194 | } | |
4195 | } | |
4196 | } | |
4197 | return 1; | |
4198 | } | |
4199 | ||
4200 | // Used when a branch jumps into the delay slot of another branch | |
4201 | void ds_assemble_entry(int i) | |
4202 | { | |
4203 | int t=(ba[i]-start)>>2; | |
4204 | if(!instr_addr[t]) instr_addr[t]=(u_int)out; | |
4205 | assem_debug("Assemble delay slot at %x\n",ba[i]); | |
4206 | assem_debug("<->\n"); | |
4207 | if(regs[t].regmap_entry[HOST_CCREG]==CCREG&®s[t].regmap[HOST_CCREG]!=CCREG) | |
4208 | wb_register(CCREG,regs[t].regmap_entry,regs[t].wasdirty,regs[t].was32); | |
4209 | load_regs(regs[t].regmap_entry,regs[t].regmap,regs[t].was32,rs1[t],rs2[t]); | |
4210 | address_generation(t,®s[t],regs[t].regmap_entry); | |
b9b61529 | 4211 | if(itype[t]==STORE||itype[t]==STORELR||(opcode[t]&0x3b)==0x39||(opcode[t]&0x3b)==0x3a) |
57871462 | 4212 | load_regs(regs[t].regmap_entry,regs[t].regmap,regs[t].was32,INVCP,INVCP); |
4213 | cop1_usable=0; | |
4214 | is_delayslot=0; | |
4215 | switch(itype[t]) { | |
4216 | case ALU: | |
4217 | alu_assemble(t,®s[t]);break; | |
4218 | case IMM16: | |
4219 | imm16_assemble(t,®s[t]);break; | |
4220 | case SHIFT: | |
4221 | shift_assemble(t,®s[t]);break; | |
4222 | case SHIFTIMM: | |
4223 | shiftimm_assemble(t,®s[t]);break; | |
4224 | case LOAD: | |
4225 | load_assemble(t,®s[t]);break; | |
4226 | case LOADLR: | |
4227 | loadlr_assemble(t,®s[t]);break; | |
4228 | case STORE: | |
4229 | store_assemble(t,®s[t]);break; | |
4230 | case STORELR: | |
4231 | storelr_assemble(t,®s[t]);break; | |
4232 | case COP0: | |
4233 | cop0_assemble(t,®s[t]);break; | |
4234 | case COP1: | |
4235 | cop1_assemble(t,®s[t]);break; | |
4236 | case C1LS: | |
4237 | c1ls_assemble(t,®s[t]);break; | |
b9b61529 | 4238 | case COP2: |
4239 | cop2_assemble(t,®s[t]);break; | |
4240 | case C2LS: | |
4241 | c2ls_assemble(t,®s[t]);break; | |
4242 | case C2OP: | |
4243 | c2op_assemble(t,®s[t]);break; | |
57871462 | 4244 | case FCONV: |
4245 | fconv_assemble(t,®s[t]);break; | |
4246 | case FLOAT: | |
4247 | float_assemble(t,®s[t]);break; | |
4248 | case FCOMP: | |
4249 | fcomp_assemble(t,®s[t]);break; | |
4250 | case MULTDIV: | |
4251 | multdiv_assemble(t,®s[t]);break; | |
4252 | case MOV: | |
4253 | mov_assemble(t,®s[t]);break; | |
4254 | case SYSCALL: | |
7139f3c8 | 4255 | case HLECALL: |
1e973cb0 | 4256 | case INTCALL: |
57871462 | 4257 | case SPAN: |
4258 | case UJUMP: | |
4259 | case RJUMP: | |
4260 | case CJUMP: | |
4261 | case SJUMP: | |
4262 | case FJUMP: | |
c43b5311 | 4263 | SysPrintf("Jump in the delay slot. This is probably a bug.\n"); |
57871462 | 4264 | } |
4265 | store_regs_bt(regs[t].regmap,regs[t].is32,regs[t].dirty,ba[i]+4); | |
4266 | load_regs_bt(regs[t].regmap,regs[t].is32,regs[t].dirty,ba[i]+4); | |
4267 | if(internal_branch(regs[t].is32,ba[i]+4)) | |
4268 | assem_debug("branch: internal\n"); | |
4269 | else | |
4270 | assem_debug("branch: external\n"); | |
4271 | assert(internal_branch(regs[t].is32,ba[i]+4)); | |
4272 | add_to_linker((int)out,ba[i]+4,internal_branch(regs[t].is32,ba[i]+4)); | |
4273 | emit_jmp(0); | |
4274 | } | |
4275 | ||
4276 | void do_cc(int i,signed char i_regmap[],int *adj,int addr,int taken,int invert) | |
4277 | { | |
4278 | int count; | |
4279 | int jaddr; | |
4280 | int idle=0; | |
b6e87b2b | 4281 | int t=0; |
57871462 | 4282 | if(itype[i]==RJUMP) |
4283 | { | |
4284 | *adj=0; | |
4285 | } | |
4286 | //if(ba[i]>=start && ba[i]<(start+slen*4)) | |
4287 | if(internal_branch(branch_regs[i].is32,ba[i])) | |
4288 | { | |
b6e87b2b | 4289 | t=(ba[i]-start)>>2; |
57871462 | 4290 | if(is_ds[t]) *adj=-1; // Branch into delay slot adds an extra cycle |
4291 | else *adj=ccadj[t]; | |
4292 | } | |
4293 | else | |
4294 | { | |
4295 | *adj=0; | |
4296 | } | |
4297 | count=ccadj[i]; | |
4298 | if(taken==TAKEN && i==(ba[i]-start)>>2 && source[i+1]==0) { | |
4299 | // Idle loop | |
4300 | if(count&1) emit_addimm_and_set_flags(2*(count+2),HOST_CCREG); | |
4301 | idle=(int)out; | |
4302 | //emit_subfrommem(&idlecount,HOST_CCREG); // Count idle cycles | |
4303 | emit_andimm(HOST_CCREG,3,HOST_CCREG); | |
4304 | jaddr=(int)out; | |
4305 | emit_jmp(0); | |
4306 | } | |
4307 | else if(*adj==0||invert) { | |
b6e87b2b | 4308 | int cycles=CLOCK_ADJUST(count+2); |
4309 | // faster loop HACK | |
4310 | if (t&&*adj) { | |
4311 | int rel=t-i; | |
4312 | if(-NO_CYCLE_PENALTY_THR<rel&&rel<0) | |
4313 | cycles=CLOCK_ADJUST(*adj)+count+2-*adj; | |
4314 | } | |
4315 | emit_addimm_and_set_flags(cycles,HOST_CCREG); | |
57871462 | 4316 | jaddr=(int)out; |
4317 | emit_jns(0); | |
4318 | } | |
4319 | else | |
4320 | { | |
2573466a | 4321 | emit_cmpimm(HOST_CCREG,-CLOCK_ADJUST(count+2)); |
57871462 | 4322 | jaddr=(int)out; |
4323 | emit_jns(0); | |
4324 | } | |
4325 | add_stub(CC_STUB,jaddr,idle?idle:(int)out,(*adj==0||invert||idle)?0:(count+2),i,addr,taken,0); | |
4326 | } | |
4327 | ||
4328 | void do_ccstub(int n) | |
4329 | { | |
4330 | literal_pool(256); | |
4331 | assem_debug("do_ccstub %x\n",start+stubs[n][4]*4); | |
4332 | set_jump_target(stubs[n][1],(int)out); | |
4333 | int i=stubs[n][4]; | |
4334 | if(stubs[n][6]==NULLDS) { | |
4335 | // Delay slot instruction is nullified ("likely" branch) | |
4336 | wb_dirtys(regs[i].regmap,regs[i].is32,regs[i].dirty); | |
4337 | } | |
4338 | else if(stubs[n][6]!=TAKEN) { | |
4339 | wb_dirtys(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty); | |
4340 | } | |
4341 | else { | |
4342 | if(internal_branch(branch_regs[i].is32,ba[i])) | |
4343 | wb_needed_dirtys(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]); | |
4344 | } | |
4345 | if(stubs[n][5]!=-1) | |
4346 | { | |
4347 | // Save PC as return address | |
4348 | emit_movimm(stubs[n][5],EAX); | |
4349 | emit_writeword(EAX,(int)&pcaddr); | |
4350 | } | |
4351 | else | |
4352 | { | |
4353 | // Return address depends on which way the branch goes | |
4354 | if(itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP) | |
4355 | { | |
4356 | int s1l=get_reg(branch_regs[i].regmap,rs1[i]); | |
4357 | int s1h=get_reg(branch_regs[i].regmap,rs1[i]|64); | |
4358 | int s2l=get_reg(branch_regs[i].regmap,rs2[i]); | |
4359 | int s2h=get_reg(branch_regs[i].regmap,rs2[i]|64); | |
4360 | if(rs1[i]==0) | |
4361 | { | |
4362 | s1l=s2l;s1h=s2h; | |
4363 | s2l=s2h=-1; | |
4364 | } | |
4365 | else if(rs2[i]==0) | |
4366 | { | |
4367 | s2l=s2h=-1; | |
4368 | } | |
4369 | if((branch_regs[i].is32>>rs1[i])&(branch_regs[i].is32>>rs2[i])&1) { | |
4370 | s1h=s2h=-1; | |
4371 | } | |
4372 | assert(s1l>=0); | |
4373 | #ifdef DESTRUCTIVE_WRITEBACK | |
4374 | if(rs1[i]) { | |
4375 | if((branch_regs[i].dirty>>s1l)&(branch_regs[i].is32>>rs1[i])&1) | |
4376 | emit_loadreg(rs1[i],s1l); | |
9f51b4b9 | 4377 | } |
57871462 | 4378 | else { |
4379 | if((branch_regs[i].dirty>>s1l)&(branch_regs[i].is32>>rs2[i])&1) | |
4380 | emit_loadreg(rs2[i],s1l); | |
4381 | } | |
4382 | if(s2l>=0) | |
4383 | if((branch_regs[i].dirty>>s2l)&(branch_regs[i].is32>>rs2[i])&1) | |
4384 | emit_loadreg(rs2[i],s2l); | |
4385 | #endif | |
4386 | int hr=0; | |
5194fb95 | 4387 | int addr=-1,alt=-1,ntaddr=-1; |
57871462 | 4388 | while(hr<HOST_REGS) |
4389 | { | |
4390 | if(hr!=EXCLUDE_REG && hr!=HOST_CCREG && | |
4391 | (branch_regs[i].regmap[hr]&63)!=rs1[i] && | |
4392 | (branch_regs[i].regmap[hr]&63)!=rs2[i] ) | |
4393 | { | |
4394 | addr=hr++;break; | |
4395 | } | |
4396 | hr++; | |
4397 | } | |
4398 | while(hr<HOST_REGS) | |
4399 | { | |
4400 | if(hr!=EXCLUDE_REG && hr!=HOST_CCREG && | |
4401 | (branch_regs[i].regmap[hr]&63)!=rs1[i] && | |
4402 | (branch_regs[i].regmap[hr]&63)!=rs2[i] ) | |
4403 | { | |
4404 | alt=hr++;break; | |
4405 | } | |
4406 | hr++; | |
4407 | } | |
4408 | if((opcode[i]&0x2E)==6) // BLEZ/BGTZ needs another register | |
4409 | { | |
4410 | while(hr<HOST_REGS) | |
4411 | { | |
4412 | if(hr!=EXCLUDE_REG && hr!=HOST_CCREG && | |
4413 | (branch_regs[i].regmap[hr]&63)!=rs1[i] && | |
4414 | (branch_regs[i].regmap[hr]&63)!=rs2[i] ) | |
4415 | { | |
4416 | ntaddr=hr;break; | |
4417 | } | |
4418 | hr++; | |
4419 | } | |
4420 | assert(hr<HOST_REGS); | |
4421 | } | |
4422 | if((opcode[i]&0x2f)==4) // BEQ | |
4423 | { | |
4424 | #ifdef HAVE_CMOV_IMM | |
4425 | if(s1h<0) { | |
4426 | if(s2l>=0) emit_cmp(s1l,s2l); | |
4427 | else emit_test(s1l,s1l); | |
4428 | emit_cmov2imm_e_ne_compact(ba[i],start+i*4+8,addr); | |
4429 | } | |
4430 | else | |
4431 | #endif | |
4432 | { | |
4433 | emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt); | |
4434 | if(s1h>=0) { | |
4435 | if(s2h>=0) emit_cmp(s1h,s2h); | |
4436 | else emit_test(s1h,s1h); | |
4437 | emit_cmovne_reg(alt,addr); | |
4438 | } | |
4439 | if(s2l>=0) emit_cmp(s1l,s2l); | |
4440 | else emit_test(s1l,s1l); | |
4441 | emit_cmovne_reg(alt,addr); | |
4442 | } | |
4443 | } | |
4444 | if((opcode[i]&0x2f)==5) // BNE | |
4445 | { | |
4446 | #ifdef HAVE_CMOV_IMM | |
4447 | if(s1h<0) { | |
4448 | if(s2l>=0) emit_cmp(s1l,s2l); | |
4449 | else emit_test(s1l,s1l); | |
4450 | emit_cmov2imm_e_ne_compact(start+i*4+8,ba[i],addr); | |
4451 | } | |
4452 | else | |
4453 | #endif | |
4454 | { | |
4455 | emit_mov2imm_compact(start+i*4+8,addr,ba[i],alt); | |
4456 | if(s1h>=0) { | |
4457 | if(s2h>=0) emit_cmp(s1h,s2h); | |
4458 | else emit_test(s1h,s1h); | |
4459 | emit_cmovne_reg(alt,addr); | |
4460 | } | |
4461 | if(s2l>=0) emit_cmp(s1l,s2l); | |
4462 | else emit_test(s1l,s1l); | |
4463 | emit_cmovne_reg(alt,addr); | |
4464 | } | |
4465 | } | |
4466 | if((opcode[i]&0x2f)==6) // BLEZ | |
4467 | { | |
4468 | //emit_movimm(ba[i],alt); | |
4469 | //emit_movimm(start+i*4+8,addr); | |
4470 | emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr); | |
4471 | emit_cmpimm(s1l,1); | |
4472 | if(s1h>=0) emit_mov(addr,ntaddr); | |
4473 | emit_cmovl_reg(alt,addr); | |
4474 | if(s1h>=0) { | |
4475 | emit_test(s1h,s1h); | |
4476 | emit_cmovne_reg(ntaddr,addr); | |
4477 | emit_cmovs_reg(alt,addr); | |
4478 | } | |
4479 | } | |
4480 | if((opcode[i]&0x2f)==7) // BGTZ | |
4481 | { | |
4482 | //emit_movimm(ba[i],addr); | |
4483 | //emit_movimm(start+i*4+8,ntaddr); | |
4484 | emit_mov2imm_compact(ba[i],addr,start+i*4+8,ntaddr); | |
4485 | emit_cmpimm(s1l,1); | |
4486 | if(s1h>=0) emit_mov(addr,alt); | |
4487 | emit_cmovl_reg(ntaddr,addr); | |
4488 | if(s1h>=0) { | |
4489 | emit_test(s1h,s1h); | |
4490 | emit_cmovne_reg(alt,addr); | |
4491 | emit_cmovs_reg(ntaddr,addr); | |
4492 | } | |
4493 | } | |
4494 | if((opcode[i]==1)&&(opcode2[i]&0x2D)==0) // BLTZ | |
4495 | { | |
4496 | //emit_movimm(ba[i],alt); | |
4497 | //emit_movimm(start+i*4+8,addr); | |
4498 | emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr); | |
4499 | if(s1h>=0) emit_test(s1h,s1h); | |
4500 | else emit_test(s1l,s1l); | |
4501 | emit_cmovs_reg(alt,addr); | |
4502 | } | |
4503 | if((opcode[i]==1)&&(opcode2[i]&0x2D)==1) // BGEZ | |
4504 | { | |
4505 | //emit_movimm(ba[i],addr); | |
4506 | //emit_movimm(start+i*4+8,alt); | |
4507 | emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt); | |
4508 | if(s1h>=0) emit_test(s1h,s1h); | |
4509 | else emit_test(s1l,s1l); | |
4510 | emit_cmovs_reg(alt,addr); | |
4511 | } | |
4512 | if(opcode[i]==0x11 && opcode2[i]==0x08 ) { | |
4513 | if(source[i]&0x10000) // BC1T | |
4514 | { | |
4515 | //emit_movimm(ba[i],alt); | |
4516 | //emit_movimm(start+i*4+8,addr); | |
4517 | emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr); | |
4518 | emit_testimm(s1l,0x800000); | |
4519 | emit_cmovne_reg(alt,addr); | |
4520 | } | |
4521 | else // BC1F | |
4522 | { | |
4523 | //emit_movimm(ba[i],addr); | |
4524 | //emit_movimm(start+i*4+8,alt); | |
4525 | emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt); | |
4526 | emit_testimm(s1l,0x800000); | |
4527 | emit_cmovne_reg(alt,addr); | |
4528 | } | |
4529 | } | |
4530 | emit_writeword(addr,(int)&pcaddr); | |
4531 | } | |
4532 | else | |
4533 | if(itype[i]==RJUMP) | |
4534 | { | |
4535 | int r=get_reg(branch_regs[i].regmap,rs1[i]); | |
4536 | if(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1]) { | |
4537 | r=get_reg(branch_regs[i].regmap,RTEMP); | |
4538 | } | |
4539 | emit_writeword(r,(int)&pcaddr); | |
4540 | } | |
c43b5311 | 4541 | else {SysPrintf("Unknown branch type in do_ccstub\n");exit(1);} |
57871462 | 4542 | } |
4543 | // Update cycle count | |
4544 | assert(branch_regs[i].regmap[HOST_CCREG]==CCREG||branch_regs[i].regmap[HOST_CCREG]==-1); | |
2573466a | 4545 | if(stubs[n][3]) emit_addimm(HOST_CCREG,CLOCK_ADJUST((int)stubs[n][3]),HOST_CCREG); |
57871462 | 4546 | emit_call((int)cc_interrupt); |
2573466a | 4547 | if(stubs[n][3]) emit_addimm(HOST_CCREG,-CLOCK_ADJUST((int)stubs[n][3]),HOST_CCREG); |
57871462 | 4548 | if(stubs[n][6]==TAKEN) { |
4549 | if(internal_branch(branch_regs[i].is32,ba[i])) | |
4550 | load_needed_regs(branch_regs[i].regmap,regs[(ba[i]-start)>>2].regmap_entry); | |
4551 | else if(itype[i]==RJUMP) { | |
4552 | if(get_reg(branch_regs[i].regmap,RTEMP)>=0) | |
4553 | emit_readword((int)&pcaddr,get_reg(branch_regs[i].regmap,RTEMP)); | |
4554 | else | |
4555 | emit_loadreg(rs1[i],get_reg(branch_regs[i].regmap,rs1[i])); | |
4556 | } | |
4557 | }else if(stubs[n][6]==NOTTAKEN) { | |
4558 | if(i<slen-2) load_needed_regs(branch_regs[i].regmap,regmap_pre[i+2]); | |
4559 | else load_all_regs(branch_regs[i].regmap); | |
4560 | }else if(stubs[n][6]==NULLDS) { | |
4561 | // Delay slot instruction is nullified ("likely" branch) | |
4562 | if(i<slen-2) load_needed_regs(regs[i].regmap,regmap_pre[i+2]); | |
4563 | else load_all_regs(regs[i].regmap); | |
4564 | }else{ | |
4565 | load_all_regs(branch_regs[i].regmap); | |
4566 | } | |
4567 | emit_jmp(stubs[n][2]); // return address | |
9f51b4b9 | 4568 | |
57871462 | 4569 | /* This works but uses a lot of memory... |
4570 | emit_readword((int)&last_count,ECX); | |
4571 | emit_add(HOST_CCREG,ECX,EAX); | |
4572 | emit_writeword(EAX,(int)&Count); | |
4573 | emit_call((int)gen_interupt); | |
4574 | emit_readword((int)&Count,HOST_CCREG); | |
4575 | emit_readword((int)&next_interupt,EAX); | |
4576 | emit_readword((int)&pending_exception,EBX); | |
4577 | emit_writeword(EAX,(int)&last_count); | |
4578 | emit_sub(HOST_CCREG,EAX,HOST_CCREG); | |
4579 | emit_test(EBX,EBX); | |
4580 | int jne_instr=(int)out; | |
4581 | emit_jne(0); | |
4582 | if(stubs[n][3]) emit_addimm(HOST_CCREG,-2*stubs[n][3],HOST_CCREG); | |
4583 | load_all_regs(branch_regs[i].regmap); | |
4584 | emit_jmp(stubs[n][2]); // return address | |
4585 | set_jump_target(jne_instr,(int)out); | |
4586 | emit_readword((int)&pcaddr,EAX); | |
4587 | // Call get_addr_ht instead of doing the hash table here. | |
4588 | // This code is executed infrequently and takes up a lot of space | |
4589 | // so smaller is better. | |
4590 | emit_storereg(CCREG,HOST_CCREG); | |
4591 | emit_pushreg(EAX); | |
4592 | emit_call((int)get_addr_ht); | |
4593 | emit_loadreg(CCREG,HOST_CCREG); | |
4594 | emit_addimm(ESP,4,ESP); | |
4595 | emit_jmpreg(EAX);*/ | |
4596 | } | |
4597 | ||
e2b5e7aa | 4598 | static void add_to_linker(int addr,int target,int ext) |
57871462 | 4599 | { |
4600 | link_addr[linkcount][0]=addr; | |
4601 | link_addr[linkcount][1]=target; | |
9f51b4b9 | 4602 | link_addr[linkcount][2]=ext; |
57871462 | 4603 | linkcount++; |
4604 | } | |
4605 | ||
eba830cd | 4606 | static void ujump_assemble_write_ra(int i) |
4607 | { | |
4608 | int rt; | |
4609 | unsigned int return_address; | |
4610 | rt=get_reg(branch_regs[i].regmap,31); | |
4611 | assem_debug("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]); | |
4612 | //assert(rt>=0); | |
4613 | return_address=start+i*4+8; | |
4614 | if(rt>=0) { | |
4615 | #ifdef USE_MINI_HT | |
4616 | if(internal_branch(branch_regs[i].is32,return_address)&&rt1[i+1]!=31) { | |
4617 | int temp=-1; // note: must be ds-safe | |
4618 | #ifdef HOST_TEMPREG | |
4619 | temp=HOST_TEMPREG; | |
4620 | #endif | |
4621 | if(temp>=0) do_miniht_insert(return_address,rt,temp); | |
4622 | else emit_movimm(return_address,rt); | |
4623 | } | |
4624 | else | |
4625 | #endif | |
4626 | { | |
4627 | #ifdef REG_PREFETCH | |
9f51b4b9 | 4628 | if(temp>=0) |
eba830cd | 4629 | { |
4630 | if(i_regmap[temp]!=PTEMP) emit_movimm((int)hash_table[((return_address>>16)^return_address)&0xFFFF],temp); | |
4631 | } | |
4632 | #endif | |
4633 | emit_movimm(return_address,rt); // PC into link register | |
4634 | #ifdef IMM_PREFETCH | |
4635 | emit_prefetch(hash_table[((return_address>>16)^return_address)&0xFFFF]); | |
4636 | #endif | |
4637 | } | |
4638 | } | |
4639 | } | |
4640 | ||
57871462 | 4641 | void ujump_assemble(int i,struct regstat *i_regs) |
4642 | { | |
eba830cd | 4643 | int ra_done=0; |
57871462 | 4644 | if(i==(ba[i]-start)>>2) assem_debug("idle loop\n"); |
4645 | address_generation(i+1,i_regs,regs[i].regmap_entry); | |
4646 | #ifdef REG_PREFETCH | |
4647 | int temp=get_reg(branch_regs[i].regmap,PTEMP); | |
9f51b4b9 | 4648 | if(rt1[i]==31&&temp>=0) |
57871462 | 4649 | { |
581335b0 | 4650 | signed char *i_regmap=i_regs->regmap; |
57871462 | 4651 | int return_address=start+i*4+8; |
9f51b4b9 | 4652 | if(get_reg(branch_regs[i].regmap,31)>0) |
57871462 | 4653 | if(i_regmap[temp]==PTEMP) emit_movimm((int)hash_table[((return_address>>16)^return_address)&0xFFFF],temp); |
4654 | } | |
4655 | #endif | |
eba830cd | 4656 | if(rt1[i]==31&&(rt1[i]==rs1[i+1]||rt1[i]==rs2[i+1])) { |
4657 | ujump_assemble_write_ra(i); // writeback ra for DS | |
4658 | ra_done=1; | |
57871462 | 4659 | } |
4ef8f67d | 4660 | ds_assemble(i+1,i_regs); |
4661 | uint64_t bc_unneeded=branch_regs[i].u; | |
4662 | uint64_t bc_unneeded_upper=branch_regs[i].uu; | |
4663 | bc_unneeded|=1|(1LL<<rt1[i]); | |
4664 | bc_unneeded_upper|=1|(1LL<<rt1[i]); | |
4665 | wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32, | |
4666 | bc_unneeded,bc_unneeded_upper); | |
4667 | load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG); | |
eba830cd | 4668 | if(!ra_done&&rt1[i]==31) |
4669 | ujump_assemble_write_ra(i); | |
57871462 | 4670 | int cc,adj; |
4671 | cc=get_reg(branch_regs[i].regmap,CCREG); | |
4672 | assert(cc==HOST_CCREG); | |
4673 | store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]); | |
4674 | #ifdef REG_PREFETCH | |
4675 | if(rt1[i]==31&&temp>=0) emit_prefetchreg(temp); | |
4676 | #endif | |
4677 | do_cc(i,branch_regs[i].regmap,&adj,ba[i],TAKEN,0); | |
2573466a | 4678 | if(adj) emit_addimm(cc,CLOCK_ADJUST(ccadj[i]+2-adj),cc); |
57871462 | 4679 | load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]); |
4680 | if(internal_branch(branch_regs[i].is32,ba[i])) | |
4681 | assem_debug("branch: internal\n"); | |
4682 | else | |
4683 | assem_debug("branch: external\n"); | |
4684 | if(internal_branch(branch_regs[i].is32,ba[i])&&is_ds[(ba[i]-start)>>2]) { | |
4685 | ds_assemble_entry(i); | |
4686 | } | |
4687 | else { | |
4688 | add_to_linker((int)out,ba[i],internal_branch(branch_regs[i].is32,ba[i])); | |
4689 | emit_jmp(0); | |
4690 | } | |
4691 | } | |
4692 | ||
eba830cd | 4693 | static void rjump_assemble_write_ra(int i) |
4694 | { | |
4695 | int rt,return_address; | |
4696 | assert(rt1[i+1]!=rt1[i]); | |
4697 | assert(rt2[i+1]!=rt1[i]); | |
4698 | rt=get_reg(branch_regs[i].regmap,rt1[i]); | |
4699 | assem_debug("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]); | |
4700 | assert(rt>=0); | |
4701 | return_address=start+i*4+8; | |
4702 | #ifdef REG_PREFETCH | |
9f51b4b9 | 4703 | if(temp>=0) |
eba830cd | 4704 | { |
4705 | if(i_regmap[temp]!=PTEMP) emit_movimm((int)hash_table[((return_address>>16)^return_address)&0xFFFF],temp); | |
4706 | } | |
4707 | #endif | |
4708 | emit_movimm(return_address,rt); // PC into link register | |
4709 | #ifdef IMM_PREFETCH | |
4710 | emit_prefetch(hash_table[((return_address>>16)^return_address)&0xFFFF]); | |
4711 | #endif | |
4712 | } | |
4713 | ||
57871462 | 4714 | void rjump_assemble(int i,struct regstat *i_regs) |
4715 | { | |
57871462 | 4716 | int temp; |
581335b0 | 4717 | int rs,cc; |
eba830cd | 4718 | int ra_done=0; |
57871462 | 4719 | rs=get_reg(branch_regs[i].regmap,rs1[i]); |
4720 | assert(rs>=0); | |
4721 | if(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1]) { | |
4722 | // Delay slot abuse, make a copy of the branch address register | |
4723 | temp=get_reg(branch_regs[i].regmap,RTEMP); | |
4724 | assert(temp>=0); | |
4725 | assert(regs[i].regmap[temp]==RTEMP); | |
4726 | emit_mov(rs,temp); | |
4727 | rs=temp; | |
4728 | } | |
4729 | address_generation(i+1,i_regs,regs[i].regmap_entry); | |
4730 | #ifdef REG_PREFETCH | |
9f51b4b9 | 4731 | if(rt1[i]==31) |
57871462 | 4732 | { |
4733 | if((temp=get_reg(branch_regs[i].regmap,PTEMP))>=0) { | |
581335b0 | 4734 | signed char *i_regmap=i_regs->regmap; |
57871462 | 4735 | int return_address=start+i*4+8; |
4736 | if(i_regmap[temp]==PTEMP) emit_movimm((int)hash_table[((return_address>>16)^return_address)&0xFFFF],temp); | |
4737 | } | |
4738 | } | |
4739 | #endif | |
4740 | #ifdef USE_MINI_HT | |
4741 | if(rs1[i]==31) { | |
4742 | int rh=get_reg(regs[i].regmap,RHASH); | |
4743 | if(rh>=0) do_preload_rhash(rh); | |
4744 | } | |
4745 | #endif | |
eba830cd | 4746 | if(rt1[i]!=0&&(rt1[i]==rs1[i+1]||rt1[i]==rs2[i+1])) { |
4747 | rjump_assemble_write_ra(i); | |
4748 | ra_done=1; | |
57871462 | 4749 | } |
d5910d5d | 4750 | ds_assemble(i+1,i_regs); |
4751 | uint64_t bc_unneeded=branch_regs[i].u; | |
4752 | uint64_t bc_unneeded_upper=branch_regs[i].uu; | |
4753 | bc_unneeded|=1|(1LL<<rt1[i]); | |
4754 | bc_unneeded_upper|=1|(1LL<<rt1[i]); | |
4755 | bc_unneeded&=~(1LL<<rs1[i]); | |
4756 | wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32, | |
4757 | bc_unneeded,bc_unneeded_upper); | |
4758 | load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i],CCREG); | |
eba830cd | 4759 | if(!ra_done&&rt1[i]!=0) |
4760 | rjump_assemble_write_ra(i); | |
57871462 | 4761 | cc=get_reg(branch_regs[i].regmap,CCREG); |
4762 | assert(cc==HOST_CCREG); | |
581335b0 | 4763 | (void)cc; |
57871462 | 4764 | #ifdef USE_MINI_HT |
4765 | int rh=get_reg(branch_regs[i].regmap,RHASH); | |
4766 | int ht=get_reg(branch_regs[i].regmap,RHTBL); | |
4767 | if(rs1[i]==31) { | |
4768 | if(regs[i].regmap[rh]!=RHASH) do_preload_rhash(rh); | |
4769 | do_preload_rhtbl(ht); | |
4770 | do_rhash(rs,rh); | |
4771 | } | |
4772 | #endif | |
4773 | store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,-1); | |
4774 | #ifdef DESTRUCTIVE_WRITEBACK | |
4775 | if((branch_regs[i].dirty>>rs)&(branch_regs[i].is32>>rs1[i])&1) { | |
4776 | if(rs1[i]!=rt1[i+1]&&rs1[i]!=rt2[i+1]) { | |
4777 | emit_loadreg(rs1[i],rs); | |
4778 | } | |
4779 | } | |
4780 | #endif | |
4781 | #ifdef REG_PREFETCH | |
4782 | if(rt1[i]==31&&temp>=0) emit_prefetchreg(temp); | |
4783 | #endif | |
4784 | #ifdef USE_MINI_HT | |
4785 | if(rs1[i]==31) { | |
4786 | do_miniht_load(ht,rh); | |
4787 | } | |
4788 | #endif | |
4789 | //do_cc(i,branch_regs[i].regmap,&adj,-1,TAKEN); | |
4790 | //if(adj) emit_addimm(cc,2*(ccadj[i]+2-adj),cc); // ??? - Shouldn't happen | |
4791 | //assert(adj==0); | |
2573466a | 4792 | emit_addimm_and_set_flags(CLOCK_ADJUST(ccadj[i]+2),HOST_CCREG); |
57871462 | 4793 | add_stub(CC_STUB,(int)out,jump_vaddr_reg[rs],0,i,-1,TAKEN,0); |
911f2d55 | 4794 | if(itype[i+1]==COP0&&(source[i+1]&0x3f)==0x10) |
4795 | // special case for RFE | |
4796 | emit_jmp(0); | |
4797 | else | |
71e490c5 | 4798 | emit_jns(0); |
57871462 | 4799 | //load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,-1); |
4800 | #ifdef USE_MINI_HT | |
4801 | if(rs1[i]==31) { | |
4802 | do_miniht_jump(rs,rh,ht); | |
4803 | } | |
4804 | else | |
4805 | #endif | |
4806 | { | |
4807 | //if(rs!=EAX) emit_mov(rs,EAX); | |
4808 | //emit_jmp((int)jump_vaddr_eax); | |
4809 | emit_jmp(jump_vaddr_reg[rs]); | |
4810 | } | |
4811 | /* Check hash table | |
4812 | temp=!rs; | |
4813 | emit_mov(rs,temp); | |
4814 | emit_shrimm(rs,16,rs); | |
4815 | emit_xor(temp,rs,rs); | |
4816 | emit_movzwl_reg(rs,rs); | |
4817 | emit_shlimm(rs,4,rs); | |
4818 | emit_cmpmem_indexed((int)hash_table,rs,temp); | |
4819 | emit_jne((int)out+14); | |
4820 | emit_readword_indexed((int)hash_table+4,rs,rs); | |
4821 | emit_jmpreg(rs); | |
4822 | emit_cmpmem_indexed((int)hash_table+8,rs,temp); | |
4823 | emit_addimm_no_flags(8,rs); | |
4824 | emit_jeq((int)out-17); | |
4825 | // No hit on hash table, call compiler | |
4826 | emit_pushreg(temp); | |
4827 | //DEBUG > | |
4828 | #ifdef DEBUG_CYCLE_COUNT | |
4829 | emit_readword((int)&last_count,ECX); | |
4830 | emit_add(HOST_CCREG,ECX,HOST_CCREG); | |
4831 | emit_readword((int)&next_interupt,ECX); | |
4832 | emit_writeword(HOST_CCREG,(int)&Count); | |
4833 | emit_sub(HOST_CCREG,ECX,HOST_CCREG); | |
4834 | emit_writeword(ECX,(int)&last_count); | |
4835 | #endif | |
4836 | //DEBUG < | |
4837 | emit_storereg(CCREG,HOST_CCREG); | |
4838 | emit_call((int)get_addr); | |
4839 | emit_loadreg(CCREG,HOST_CCREG); | |
4840 | emit_addimm(ESP,4,ESP); | |
4841 | emit_jmpreg(EAX);*/ | |
4842 | #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK | |
4843 | if(rt1[i]!=31&&i<slen-2&&(((u_int)out)&7)) emit_mov(13,13); | |
4844 | #endif | |
4845 | } | |
4846 | ||
4847 | void cjump_assemble(int i,struct regstat *i_regs) | |
4848 | { | |
4849 | signed char *i_regmap=i_regs->regmap; | |
4850 | int cc; | |
4851 | int match; | |
4852 | match=match_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]); | |
4853 | assem_debug("match=%d\n",match); | |
4854 | int s1h,s1l,s2h,s2l; | |
4855 | int prev_cop1_usable=cop1_usable; | |
4856 | int unconditional=0,nop=0; | |
4857 | int only32=0; | |
57871462 | 4858 | int invert=0; |
4859 | int internal=internal_branch(branch_regs[i].is32,ba[i]); | |
4860 | if(i==(ba[i]-start)>>2) assem_debug("idle loop\n"); | |
57871462 | 4861 | if(!match) invert=1; |
4862 | #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK | |
4863 | if(i>(ba[i]-start)>>2) invert=1; | |
4864 | #endif | |
9f51b4b9 | 4865 | |
e1190b87 | 4866 | if(ooo[i]) { |
57871462 | 4867 | s1l=get_reg(branch_regs[i].regmap,rs1[i]); |
4868 | s1h=get_reg(branch_regs[i].regmap,rs1[i]|64); | |
4869 | s2l=get_reg(branch_regs[i].regmap,rs2[i]); | |
4870 | s2h=get_reg(branch_regs[i].regmap,rs2[i]|64); | |
4871 | } | |
4872 | else { | |
4873 | s1l=get_reg(i_regmap,rs1[i]); | |
4874 | s1h=get_reg(i_regmap,rs1[i]|64); | |
4875 | s2l=get_reg(i_regmap,rs2[i]); | |
4876 | s2h=get_reg(i_regmap,rs2[i]|64); | |
4877 | } | |
4878 | if(rs1[i]==0&&rs2[i]==0) | |
4879 | { | |
4880 | if(opcode[i]&1) nop=1; | |
4881 | else unconditional=1; | |
4882 | //assert(opcode[i]!=5); | |
4883 | //assert(opcode[i]!=7); | |
4884 | //assert(opcode[i]!=0x15); | |
4885 | //assert(opcode[i]!=0x17); | |
4886 | } | |
4887 | else if(rs1[i]==0) | |
4888 | { | |
4889 | s1l=s2l;s1h=s2h; | |
4890 | s2l=s2h=-1; | |
4891 | only32=(regs[i].was32>>rs2[i])&1; | |
4892 | } | |
4893 | else if(rs2[i]==0) | |
4894 | { | |
4895 | s2l=s2h=-1; | |
4896 | only32=(regs[i].was32>>rs1[i])&1; | |
4897 | } | |
4898 | else { | |
4899 | only32=(regs[i].was32>>rs1[i])&(regs[i].was32>>rs2[i])&1; | |
4900 | } | |
4901 | ||
e1190b87 | 4902 | if(ooo[i]) { |
57871462 | 4903 | // Out of order execution (delay slot first) |
4904 | //printf("OOOE\n"); | |
4905 | address_generation(i+1,i_regs,regs[i].regmap_entry); | |
4906 | ds_assemble(i+1,i_regs); | |
4907 | int adj; | |
4908 | uint64_t bc_unneeded=branch_regs[i].u; | |
4909 | uint64_t bc_unneeded_upper=branch_regs[i].uu; | |
4910 | bc_unneeded&=~((1LL<<rs1[i])|(1LL<<rs2[i])); | |
4911 | bc_unneeded_upper&=~((1LL<<us1[i])|(1LL<<us2[i])); | |
4912 | bc_unneeded|=1; | |
4913 | bc_unneeded_upper|=1; | |
4914 | wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32, | |
4915 | bc_unneeded,bc_unneeded_upper); | |
4916 | load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i],rs2[i]); | |
4917 | load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG); | |
4918 | cc=get_reg(branch_regs[i].regmap,CCREG); | |
4919 | assert(cc==HOST_CCREG); | |
9f51b4b9 | 4920 | if(unconditional) |
57871462 | 4921 | store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]); |
4922 | //do_cc(i,branch_regs[i].regmap,&adj,unconditional?ba[i]:-1,unconditional); | |
4923 | //assem_debug("cycle count (adj)\n"); | |
4924 | if(unconditional) { | |
4925 | do_cc(i,branch_regs[i].regmap,&adj,ba[i],TAKEN,0); | |
4926 | if(i!=(ba[i]-start)>>2 || source[i+1]!=0) { | |
2573466a | 4927 | if(adj) emit_addimm(cc,CLOCK_ADJUST(ccadj[i]+2-adj),cc); |
57871462 | 4928 | load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]); |
4929 | if(internal) | |
4930 | assem_debug("branch: internal\n"); | |
4931 | else | |
4932 | assem_debug("branch: external\n"); | |
4933 | if(internal&&is_ds[(ba[i]-start)>>2]) { | |
4934 | ds_assemble_entry(i); | |
4935 | } | |
4936 | else { | |
4937 | add_to_linker((int)out,ba[i],internal); | |
4938 | emit_jmp(0); | |
4939 | } | |
4940 | #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK | |
4941 | if(((u_int)out)&7) emit_addnop(0); | |
4942 | #endif | |
4943 | } | |
4944 | } | |
4945 | else if(nop) { | |
2573466a | 4946 | emit_addimm_and_set_flags(CLOCK_ADJUST(ccadj[i]+2),cc); |
57871462 | 4947 | int jaddr=(int)out; |
4948 | emit_jns(0); | |
4949 | add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,NOTTAKEN,0); | |
4950 | } | |
4951 | else { | |
4952 | int taken=0,nottaken=0,nottaken1=0; | |
4953 | do_cc(i,branch_regs[i].regmap,&adj,-1,0,invert); | |
2573466a | 4954 | if(adj&&!invert) emit_addimm(cc,CLOCK_ADJUST(ccadj[i]+2-adj),cc); |
57871462 | 4955 | if(!only32) |
4956 | { | |
4957 | assert(s1h>=0); | |
4958 | if(opcode[i]==4) // BEQ | |
4959 | { | |
4960 | if(s2h>=0) emit_cmp(s1h,s2h); | |
4961 | else emit_test(s1h,s1h); | |
4962 | nottaken1=(int)out; | |
4963 | emit_jne(1); | |
4964 | } | |
4965 | if(opcode[i]==5) // BNE | |
4966 | { | |
4967 | if(s2h>=0) emit_cmp(s1h,s2h); | |
4968 | else emit_test(s1h,s1h); | |
4969 | if(invert) taken=(int)out; | |
4970 | else add_to_linker((int)out,ba[i],internal); | |
4971 | emit_jne(0); | |
4972 | } | |
4973 | if(opcode[i]==6) // BLEZ | |
4974 | { | |
4975 | emit_test(s1h,s1h); | |
4976 | if(invert) taken=(int)out; | |
4977 | else add_to_linker((int)out,ba[i],internal); | |
4978 | emit_js(0); | |
4979 | nottaken1=(int)out; | |
4980 | emit_jne(1); | |
4981 | } | |
4982 | if(opcode[i]==7) // BGTZ | |
4983 | { | |
4984 | emit_test(s1h,s1h); | |
4985 | nottaken1=(int)out; | |
4986 | emit_js(1); | |
4987 | if(invert) taken=(int)out; | |
4988 | else add_to_linker((int)out,ba[i],internal); | |
4989 | emit_jne(0); | |
4990 | } | |
4991 | } // if(!only32) | |
9f51b4b9 | 4992 | |
57871462 | 4993 | //printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]); |
4994 | assert(s1l>=0); | |
4995 | if(opcode[i]==4) // BEQ | |
4996 | { | |
4997 | if(s2l>=0) emit_cmp(s1l,s2l); | |
4998 | else emit_test(s1l,s1l); | |
4999 | if(invert){ | |
5000 | nottaken=(int)out; | |
5001 | emit_jne(1); | |
5002 | }else{ | |
5003 | add_to_linker((int)out,ba[i],internal); | |
5004 | emit_jeq(0); | |
5005 | } | |
5006 | } | |
5007 | if(opcode[i]==5) // BNE | |
5008 | { | |
5009 | if(s2l>=0) emit_cmp(s1l,s2l); | |
5010 | else emit_test(s1l,s1l); | |
5011 | if(invert){ | |
5012 | nottaken=(int)out; | |
5013 | emit_jeq(1); | |
5014 | }else{ | |
5015 | add_to_linker((int)out,ba[i],internal); | |
5016 | emit_jne(0); | |
5017 | } | |
5018 | } | |
5019 | if(opcode[i]==6) // BLEZ | |
5020 | { | |
5021 | emit_cmpimm(s1l,1); | |
5022 | if(invert){ | |
5023 | nottaken=(int)out; | |
5024 | emit_jge(1); | |
5025 | }else{ | |
5026 | add_to_linker((int)out,ba[i],internal); | |
5027 | emit_jl(0); | |
5028 | } | |
5029 | } | |
5030 | if(opcode[i]==7) // BGTZ | |
5031 | { | |
5032 | emit_cmpimm(s1l,1); | |
5033 | if(invert){ | |
5034 | nottaken=(int)out; | |
5035 | emit_jl(1); | |
5036 | }else{ | |
5037 | add_to_linker((int)out,ba[i],internal); | |
5038 | emit_jge(0); | |
5039 | } | |
5040 | } | |
5041 | if(invert) { | |
5042 | if(taken) set_jump_target(taken,(int)out); | |
5043 | #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK | |
5044 | if(match&&(!internal||!is_ds[(ba[i]-start)>>2])) { | |
5045 | if(adj) { | |
2573466a | 5046 | emit_addimm(cc,-CLOCK_ADJUST(adj),cc); |
57871462 | 5047 | add_to_linker((int)out,ba[i],internal); |
5048 | }else{ | |
5049 | emit_addnop(13); | |
5050 | add_to_linker((int)out,ba[i],internal*2); | |
5051 | } | |
5052 | emit_jmp(0); | |
5053 | }else | |
5054 | #endif | |
5055 | { | |
2573466a | 5056 | if(adj) emit_addimm(cc,-CLOCK_ADJUST(adj),cc); |
57871462 | 5057 | store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]); |
5058 | load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]); | |
5059 | if(internal) | |
5060 | assem_debug("branch: internal\n"); | |
5061 | else | |
5062 | assem_debug("branch: external\n"); | |
5063 | if(internal&&is_ds[(ba[i]-start)>>2]) { | |
5064 | ds_assemble_entry(i); | |
5065 | } | |
5066 | else { | |
5067 | add_to_linker((int)out,ba[i],internal); | |
5068 | emit_jmp(0); | |
5069 | } | |
5070 | } | |
5071 | set_jump_target(nottaken,(int)out); | |
5072 | } | |
5073 | ||
5074 | if(nottaken1) set_jump_target(nottaken1,(int)out); | |
5075 | if(adj) { | |
2573466a | 5076 | if(!invert) emit_addimm(cc,CLOCK_ADJUST(adj),cc); |
57871462 | 5077 | } |
5078 | } // (!unconditional) | |
5079 | } // if(ooo) | |
5080 | else | |
5081 | { | |
5082 | // In-order execution (branch first) | |
5083 | //if(likely[i]) printf("IOL\n"); | |
5084 | //else | |
5085 | //printf("IOE\n"); | |
5086 | int taken=0,nottaken=0,nottaken1=0; | |
5087 | if(!unconditional&&!nop) { | |
5088 | if(!only32) | |
5089 | { | |
5090 | assert(s1h>=0); | |
5091 | if((opcode[i]&0x2f)==4) // BEQ | |
5092 | { | |
5093 | if(s2h>=0) emit_cmp(s1h,s2h); | |
5094 | else emit_test(s1h,s1h); | |
5095 | nottaken1=(int)out; | |
5096 | emit_jne(2); | |
5097 | } | |
5098 | if((opcode[i]&0x2f)==5) // BNE | |
5099 | { | |
5100 | if(s2h>=0) emit_cmp(s1h,s2h); | |
5101 | else emit_test(s1h,s1h); | |
5102 | taken=(int)out; | |
5103 | emit_jne(1); | |
5104 | } | |
5105 | if((opcode[i]&0x2f)==6) // BLEZ | |
5106 | { | |
5107 | emit_test(s1h,s1h); | |
5108 | taken=(int)out; | |
5109 | emit_js(1); | |
5110 | nottaken1=(int)out; | |
5111 | emit_jne(2); | |
5112 | } | |
5113 | if((opcode[i]&0x2f)==7) // BGTZ | |
5114 | { | |
5115 | emit_test(s1h,s1h); | |
5116 | nottaken1=(int)out; | |
5117 | emit_js(2); | |
5118 | taken=(int)out; | |
5119 | emit_jne(1); | |
5120 | } | |
5121 | } // if(!only32) | |
9f51b4b9 | 5122 | |
57871462 | 5123 | //printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]); |
5124 | assert(s1l>=0); | |
5125 | if((opcode[i]&0x2f)==4) // BEQ | |
5126 | { | |
5127 | if(s2l>=0) emit_cmp(s1l,s2l); | |
5128 | else emit_test(s1l,s1l); | |
5129 | nottaken=(int)out; | |
5130 | emit_jne(2); | |
5131 | } | |
5132 | if((opcode[i]&0x2f)==5) // BNE | |
5133 | { | |
5134 | if(s2l>=0) emit_cmp(s1l,s2l); | |
5135 | else emit_test(s1l,s1l); | |
5136 | nottaken=(int)out; | |
5137 | emit_jeq(2); | |
5138 | } | |
5139 | if((opcode[i]&0x2f)==6) // BLEZ | |
5140 | { | |
5141 | emit_cmpimm(s1l,1); | |
5142 | nottaken=(int)out; | |
5143 | emit_jge(2); | |
5144 | } | |
5145 | if((opcode[i]&0x2f)==7) // BGTZ | |
5146 | { | |
5147 | emit_cmpimm(s1l,1); | |
5148 | nottaken=(int)out; | |
5149 | emit_jl(2); | |
5150 | } | |
5151 | } // if(!unconditional) | |
5152 | int adj; | |
5153 | uint64_t ds_unneeded=branch_regs[i].u; | |
5154 | uint64_t ds_unneeded_upper=branch_regs[i].uu; | |
5155 | ds_unneeded&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1])); | |
5156 | ds_unneeded_upper&=~((1LL<<us1[i+1])|(1LL<<us2[i+1])); | |
5157 | if((~ds_unneeded_upper>>rt1[i+1])&1) ds_unneeded_upper&=~((1LL<<dep1[i+1])|(1LL<<dep2[i+1])); | |
5158 | ds_unneeded|=1; | |
5159 | ds_unneeded_upper|=1; | |
5160 | // branch taken | |
5161 | if(!nop) { | |
5162 | if(taken) set_jump_target(taken,(int)out); | |
5163 | assem_debug("1:\n"); | |
5164 | wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32, | |
5165 | ds_unneeded,ds_unneeded_upper); | |
5166 | // load regs | |
5167 | load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]); | |
5168 | address_generation(i+1,&branch_regs[i],0); | |
5169 | load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,INVCP); | |
5170 | ds_assemble(i+1,&branch_regs[i]); | |
5171 | cc=get_reg(branch_regs[i].regmap,CCREG); | |
5172 | if(cc==-1) { | |
5173 | emit_loadreg(CCREG,cc=HOST_CCREG); | |
5174 | // CHECK: Is the following instruction (fall thru) allocated ok? | |
5175 | } | |
5176 | assert(cc==HOST_CCREG); | |
5177 | store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]); | |
5178 | do_cc(i,i_regmap,&adj,ba[i],TAKEN,0); | |
5179 | assem_debug("cycle count (adj)\n"); | |
2573466a | 5180 | if(adj) emit_addimm(cc,CLOCK_ADJUST(ccadj[i]+2-adj),cc); |
57871462 | 5181 | load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]); |
5182 | if(internal) | |
5183 | assem_debug("branch: internal\n"); | |
5184 | else | |
5185 | assem_debug("branch: external\n"); | |
5186 | if(internal&&is_ds[(ba[i]-start)>>2]) { | |
5187 | ds_assemble_entry(i); | |
5188 | } | |
5189 | else { | |
5190 | add_to_linker((int)out,ba[i],internal); | |
5191 | emit_jmp(0); | |
5192 | } | |
5193 | } | |
5194 | // branch not taken | |
5195 | cop1_usable=prev_cop1_usable; | |
5196 | if(!unconditional) { | |
5197 | if(nottaken1) set_jump_target(nottaken1,(int)out); | |
5198 | set_jump_target(nottaken,(int)out); | |
5199 | assem_debug("2:\n"); | |
5200 | if(!likely[i]) { | |
5201 | wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32, | |
5202 | ds_unneeded,ds_unneeded_upper); | |
5203 | load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]); | |
5204 | address_generation(i+1,&branch_regs[i],0); | |
5205 | load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG); | |
5206 | ds_assemble(i+1,&branch_regs[i]); | |
5207 | } | |
5208 | cc=get_reg(branch_regs[i].regmap,CCREG); | |
5209 | if(cc==-1&&!likely[i]) { | |
5210 | // Cycle count isn't in a register, temporarily load it then write it out | |
5211 | emit_loadreg(CCREG,HOST_CCREG); | |
2573466a | 5212 | emit_addimm_and_set_flags(CLOCK_ADJUST(ccadj[i]+2),HOST_CCREG); |
57871462 | 5213 | int jaddr=(int)out; |
5214 | emit_jns(0); | |
5215 | add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,NOTTAKEN,0); | |
5216 | emit_storereg(CCREG,HOST_CCREG); | |
5217 | } | |
5218 | else{ | |
5219 | cc=get_reg(i_regmap,CCREG); | |
5220 | assert(cc==HOST_CCREG); | |
2573466a | 5221 | emit_addimm_and_set_flags(CLOCK_ADJUST(ccadj[i]+2),cc); |
57871462 | 5222 | int jaddr=(int)out; |
5223 | emit_jns(0); | |
5224 | add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,likely[i]?NULLDS:NOTTAKEN,0); | |
5225 | } | |
5226 | } | |
5227 | } | |
5228 | } | |
5229 | ||
5230 | void sjump_assemble(int i,struct regstat *i_regs) | |
5231 | { | |
5232 | signed char *i_regmap=i_regs->regmap; | |
5233 | int cc; | |
5234 | int match; | |
5235 | match=match_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]); | |
5236 | assem_debug("smatch=%d\n",match); | |
5237 | int s1h,s1l; | |
5238 | int prev_cop1_usable=cop1_usable; | |
5239 | int unconditional=0,nevertaken=0; | |
5240 | int only32=0; | |
57871462 | 5241 | int invert=0; |
5242 | int internal=internal_branch(branch_regs[i].is32,ba[i]); | |
5243 | if(i==(ba[i]-start)>>2) assem_debug("idle loop\n"); | |
57871462 | 5244 | if(!match) invert=1; |
5245 | #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK | |
5246 | if(i>(ba[i]-start)>>2) invert=1; | |
5247 | #endif | |
5248 | ||
5249 | //if(opcode2[i]>=0x10) return; // FIXME (BxxZAL) | |
df894a3a | 5250 | //assert(opcode2[i]<0x10||rs1[i]==0); // FIXME (BxxZAL) |
57871462 | 5251 | |
e1190b87 | 5252 | if(ooo[i]) { |
57871462 | 5253 | s1l=get_reg(branch_regs[i].regmap,rs1[i]); |
5254 | s1h=get_reg(branch_regs[i].regmap,rs1[i]|64); | |
5255 | } | |
5256 | else { | |
5257 | s1l=get_reg(i_regmap,rs1[i]); | |
5258 | s1h=get_reg(i_regmap,rs1[i]|64); | |
5259 | } | |
5260 | if(rs1[i]==0) | |
5261 | { | |
5262 | if(opcode2[i]&1) unconditional=1; | |
5263 | else nevertaken=1; | |
5264 | // These are never taken (r0 is never less than zero) | |
5265 | //assert(opcode2[i]!=0); | |
5266 | //assert(opcode2[i]!=2); | |
5267 | //assert(opcode2[i]!=0x10); | |
5268 | //assert(opcode2[i]!=0x12); | |
5269 | } | |
5270 | else { | |
5271 | only32=(regs[i].was32>>rs1[i])&1; | |
5272 | } | |
5273 | ||
e1190b87 | 5274 | if(ooo[i]) { |
57871462 | 5275 | // Out of order execution (delay slot first) |
5276 | //printf("OOOE\n"); | |
5277 | address_generation(i+1,i_regs,regs[i].regmap_entry); | |
5278 | ds_assemble(i+1,i_regs); | |
5279 | int adj; | |
5280 | uint64_t bc_unneeded=branch_regs[i].u; | |
5281 | uint64_t bc_unneeded_upper=branch_regs[i].uu; | |
5282 | bc_unneeded&=~((1LL<<rs1[i])|(1LL<<rs2[i])); | |
5283 | bc_unneeded_upper&=~((1LL<<us1[i])|(1LL<<us2[i])); | |
5284 | bc_unneeded|=1; | |
5285 | bc_unneeded_upper|=1; | |
5286 | wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32, | |
5287 | bc_unneeded,bc_unneeded_upper); | |
5288 | load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i],rs1[i]); | |
5289 | load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG); | |
5290 | if(rt1[i]==31) { | |
5291 | int rt,return_address; | |
57871462 | 5292 | rt=get_reg(branch_regs[i].regmap,31); |
5293 | assem_debug("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]); | |
5294 | if(rt>=0) { | |
5295 | // Save the PC even if the branch is not taken | |
5296 | return_address=start+i*4+8; | |
5297 | emit_movimm(return_address,rt); // PC into link register | |
5298 | #ifdef IMM_PREFETCH | |
5299 | if(!nevertaken) emit_prefetch(hash_table[((return_address>>16)^return_address)&0xFFFF]); | |
5300 | #endif | |
5301 | } | |
5302 | } | |
5303 | cc=get_reg(branch_regs[i].regmap,CCREG); | |
5304 | assert(cc==HOST_CCREG); | |
9f51b4b9 | 5305 | if(unconditional) |
57871462 | 5306 | store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]); |
5307 | //do_cc(i,branch_regs[i].regmap,&adj,unconditional?ba[i]:-1,unconditional); | |
5308 | assem_debug("cycle count (adj)\n"); | |
5309 | if(unconditional) { | |
5310 | do_cc(i,branch_regs[i].regmap,&adj,ba[i],TAKEN,0); | |
5311 | if(i!=(ba[i]-start)>>2 || source[i+1]!=0) { | |
2573466a | 5312 | if(adj) emit_addimm(cc,CLOCK_ADJUST(ccadj[i]+2-adj),cc); |
57871462 | 5313 | load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]); |
5314 | if(internal) | |
5315 | assem_debug("branch: internal\n"); | |
5316 | else | |
5317 | assem_debug("branch: external\n"); | |
5318 | if(internal&&is_ds[(ba[i]-start)>>2]) { | |
5319 | ds_assemble_entry(i); | |
5320 | } | |
5321 | else { | |
5322 | add_to_linker((int)out,ba[i],internal); | |
5323 | emit_jmp(0); | |
5324 | } | |
5325 | #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK | |
5326 | if(((u_int)out)&7) emit_addnop(0); | |
5327 | #endif | |
5328 | } | |
5329 | } | |
5330 | else if(nevertaken) { | |
2573466a | 5331 | emit_addimm_and_set_flags(CLOCK_ADJUST(ccadj[i]+2),cc); |
57871462 | 5332 | int jaddr=(int)out; |
5333 | emit_jns(0); | |
5334 | add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,NOTTAKEN,0); | |
5335 | } | |
5336 | else { | |
5337 | int nottaken=0; | |
5338 | do_cc(i,branch_regs[i].regmap,&adj,-1,0,invert); | |
2573466a | 5339 | if(adj&&!invert) emit_addimm(cc,CLOCK_ADJUST(ccadj[i]+2-adj),cc); |
57871462 | 5340 | if(!only32) |
5341 | { | |
5342 | assert(s1h>=0); | |
df894a3a | 5343 | if((opcode2[i]&0xf)==0) // BLTZ/BLTZAL |
57871462 | 5344 | { |
5345 | emit_test(s1h,s1h); | |
5346 | if(invert){ | |
5347 | nottaken=(int)out; | |
5348 | emit_jns(1); | |
5349 | }else{ | |
5350 | add_to_linker((int)out,ba[i],internal); | |
5351 | emit_js(0); | |
5352 | } | |
5353 | } | |
df894a3a | 5354 | if((opcode2[i]&0xf)==1) // BGEZ/BLTZAL |
57871462 | 5355 | { |
5356 | emit_test(s1h,s1h); | |
5357 | if(invert){ | |
5358 | nottaken=(int)out; | |
5359 | emit_js(1); | |
5360 | }else{ | |
5361 | add_to_linker((int)out,ba[i],internal); | |
5362 | emit_jns(0); | |
5363 | } | |
5364 | } | |
5365 | } // if(!only32) | |
5366 | else | |
5367 | { | |
5368 | assert(s1l>=0); | |
df894a3a | 5369 | if((opcode2[i]&0xf)==0) // BLTZ/BLTZAL |
57871462 | 5370 | { |
5371 | emit_test(s1l,s1l); | |
5372 | if(invert){ | |
5373 | nottaken=(int)out; | |
5374 | emit_jns(1); | |
5375 | }else{ | |
5376 | add_to_linker((int)out,ba[i],internal); | |
5377 | emit_js(0); | |
5378 | } | |
5379 | } | |
df894a3a | 5380 | if((opcode2[i]&0xf)==1) // BGEZ/BLTZAL |
57871462 | 5381 | { |
5382 | emit_test(s1l,s1l); | |
5383 | if(invert){ | |
5384 | nottaken=(int)out; | |
5385 | emit_js(1); | |
5386 | }else{ | |
5387 | add_to_linker((int)out,ba[i],internal); | |
5388 | emit_jns(0); | |
5389 | } | |
5390 | } | |
5391 | } // if(!only32) | |
9f51b4b9 | 5392 | |
57871462 | 5393 | if(invert) { |
5394 | #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK | |
5395 | if(match&&(!internal||!is_ds[(ba[i]-start)>>2])) { | |
5396 | if(adj) { | |
2573466a | 5397 | emit_addimm(cc,-CLOCK_ADJUST(adj),cc); |
57871462 | 5398 | add_to_linker((int)out,ba[i],internal); |
5399 | }else{ | |
5400 | emit_addnop(13); | |
5401 | add_to_linker((int)out,ba[i],internal*2); | |
5402 | } | |
5403 | emit_jmp(0); | |
5404 | }else | |
5405 | #endif | |
5406 | { | |
2573466a | 5407 | if(adj) emit_addimm(cc,-CLOCK_ADJUST(adj),cc); |
57871462 | 5408 | store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]); |
5409 | load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]); | |
5410 | if(internal) | |
5411 | assem_debug("branch: internal\n"); | |
5412 | else | |
5413 | assem_debug("branch: external\n"); | |
5414 | if(internal&&is_ds[(ba[i]-start)>>2]) { | |
5415 | ds_assemble_entry(i); | |
5416 | } | |
5417 | else { | |
5418 | add_to_linker((int)out,ba[i],internal); | |
5419 | emit_jmp(0); | |
5420 | } | |
5421 | } | |
5422 | set_jump_target(nottaken,(int)out); | |
5423 | } | |
5424 | ||
5425 | if(adj) { | |
2573466a | 5426 | if(!invert) emit_addimm(cc,CLOCK_ADJUST(adj),cc); |
57871462 | 5427 | } |
5428 | } // (!unconditional) | |
5429 | } // if(ooo) | |
5430 | else | |
5431 | { | |
5432 | // In-order execution (branch first) | |
5433 | //printf("IOE\n"); | |
5434 | int nottaken=0; | |
a6491170 | 5435 | if(rt1[i]==31) { |
5436 | int rt,return_address; | |
a6491170 | 5437 | rt=get_reg(branch_regs[i].regmap,31); |
5438 | if(rt>=0) { | |
5439 | // Save the PC even if the branch is not taken | |
5440 | return_address=start+i*4+8; | |
5441 | emit_movimm(return_address,rt); // PC into link register | |
5442 | #ifdef IMM_PREFETCH | |
5443 | emit_prefetch(hash_table[((return_address>>16)^return_address)&0xFFFF]); | |
5444 | #endif | |
5445 | } | |
5446 | } | |
57871462 | 5447 | if(!unconditional) { |
5448 | //printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]); | |
5449 | if(!only32) | |
5450 | { | |
5451 | assert(s1h>=0); | |
a6491170 | 5452 | if((opcode2[i]&0x0d)==0) // BLTZ/BLTZL/BLTZAL/BLTZALL |
57871462 | 5453 | { |
5454 | emit_test(s1h,s1h); | |
5455 | nottaken=(int)out; | |
5456 | emit_jns(1); | |
5457 | } | |
a6491170 | 5458 | if((opcode2[i]&0x0d)==1) // BGEZ/BGEZL/BGEZAL/BGEZALL |
57871462 | 5459 | { |
5460 | emit_test(s1h,s1h); | |
5461 | nottaken=(int)out; | |
5462 | emit_js(1); | |
5463 | } | |
5464 | } // if(!only32) | |
5465 | else | |
5466 | { | |
5467 | assert(s1l>=0); | |
a6491170 | 5468 | if((opcode2[i]&0x0d)==0) // BLTZ/BLTZL/BLTZAL/BLTZALL |
57871462 | 5469 | { |
5470 | emit_test(s1l,s1l); | |
5471 | nottaken=(int)out; | |
5472 | emit_jns(1); | |
5473 | } | |
a6491170 | 5474 | if((opcode2[i]&0x0d)==1) // BGEZ/BGEZL/BGEZAL/BGEZALL |
57871462 | 5475 | { |
5476 | emit_test(s1l,s1l); | |
5477 | nottaken=(int)out; | |
5478 | emit_js(1); | |
5479 | } | |
5480 | } | |
5481 | } // if(!unconditional) | |
5482 | int adj; | |
5483 | uint64_t ds_unneeded=branch_regs[i].u; | |
5484 | uint64_t ds_unneeded_upper=branch_regs[i].uu; | |
5485 | ds_unneeded&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1])); | |
5486 | ds_unneeded_upper&=~((1LL<<us1[i+1])|(1LL<<us2[i+1])); | |
5487 | if((~ds_unneeded_upper>>rt1[i+1])&1) ds_unneeded_upper&=~((1LL<<dep1[i+1])|(1LL<<dep2[i+1])); | |
5488 | ds_unneeded|=1; | |
5489 | ds_unneeded_upper|=1; | |
5490 | // branch taken | |
5491 | if(!nevertaken) { | |
5492 | //assem_debug("1:\n"); | |
5493 | wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32, | |
5494 | ds_unneeded,ds_unneeded_upper); | |
5495 | // load regs | |
5496 | load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]); | |
5497 | address_generation(i+1,&branch_regs[i],0); | |
5498 | load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,INVCP); | |
5499 | ds_assemble(i+1,&branch_regs[i]); | |
5500 | cc=get_reg(branch_regs[i].regmap,CCREG); | |
5501 | if(cc==-1) { | |
5502 | emit_loadreg(CCREG,cc=HOST_CCREG); | |
5503 | // CHECK: Is the following instruction (fall thru) allocated ok? | |
5504 | } | |
5505 | assert(cc==HOST_CCREG); | |
5506 | store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]); | |
5507 | do_cc(i,i_regmap,&adj,ba[i],TAKEN,0); | |
5508 | assem_debug("cycle count (adj)\n"); | |
2573466a | 5509 | if(adj) emit_addimm(cc,CLOCK_ADJUST(ccadj[i]+2-adj),cc); |
57871462 | 5510 | load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]); |
5511 | if(internal) | |
5512 | assem_debug("branch: internal\n"); | |
5513 | else | |
5514 | assem_debug("branch: external\n"); | |
5515 | if(internal&&is_ds[(ba[i]-start)>>2]) { | |
5516 | ds_assemble_entry(i); | |
5517 | } | |
5518 | else { | |
5519 | add_to_linker((int)out,ba[i],internal); | |
5520 | emit_jmp(0); | |
5521 | } | |
5522 | } | |
5523 | // branch not taken | |
5524 | cop1_usable=prev_cop1_usable; | |
5525 | if(!unconditional) { | |
5526 | set_jump_target(nottaken,(int)out); | |
5527 | assem_debug("1:\n"); | |
5528 | if(!likely[i]) { | |
5529 | wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32, | |
5530 | ds_unneeded,ds_unneeded_upper); | |
5531 | load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]); | |
5532 | address_generation(i+1,&branch_regs[i],0); | |
5533 | load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG); | |
5534 | ds_assemble(i+1,&branch_regs[i]); | |
5535 | } | |
5536 | cc=get_reg(branch_regs[i].regmap,CCREG); | |
5537 | if(cc==-1&&!likely[i]) { | |
5538 | // Cycle count isn't in a register, temporarily load it then write it out | |
5539 | emit_loadreg(CCREG,HOST_CCREG); | |
2573466a | 5540 | emit_addimm_and_set_flags(CLOCK_ADJUST(ccadj[i]+2),HOST_CCREG); |
57871462 | 5541 | int jaddr=(int)out; |
5542 | emit_jns(0); | |
5543 | add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,NOTTAKEN,0); | |
5544 | emit_storereg(CCREG,HOST_CCREG); | |
5545 | } | |
5546 | else{ | |
5547 | cc=get_reg(i_regmap,CCREG); | |
5548 | assert(cc==HOST_CCREG); | |
2573466a | 5549 | emit_addimm_and_set_flags(CLOCK_ADJUST(ccadj[i]+2),cc); |
57871462 | 5550 | int jaddr=(int)out; |
5551 | emit_jns(0); | |
5552 | add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,likely[i]?NULLDS:NOTTAKEN,0); | |
5553 | } | |
5554 | } | |
5555 | } | |
5556 | } | |
5557 | ||
5558 | void fjump_assemble(int i,struct regstat *i_regs) | |
5559 | { | |
5560 | signed char *i_regmap=i_regs->regmap; | |
5561 | int cc; | |
5562 | int match; | |
5563 | match=match_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]); | |
5564 | assem_debug("fmatch=%d\n",match); | |
5565 | int fs,cs; | |
5566 | int eaddr; | |
57871462 | 5567 | int invert=0; |
5568 | int internal=internal_branch(branch_regs[i].is32,ba[i]); | |
5569 | if(i==(ba[i]-start)>>2) assem_debug("idle loop\n"); | |
57871462 | 5570 | if(!match) invert=1; |
5571 | #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK | |
5572 | if(i>(ba[i]-start)>>2) invert=1; | |
5573 | #endif | |
5574 | ||
e1190b87 | 5575 | if(ooo[i]) { |
57871462 | 5576 | fs=get_reg(branch_regs[i].regmap,FSREG); |
5577 | address_generation(i+1,i_regs,regs[i].regmap_entry); // Is this okay? | |
5578 | } | |
5579 | else { | |
5580 | fs=get_reg(i_regmap,FSREG); | |
5581 | } | |
5582 | ||
5583 | // Check cop1 unusable | |
5584 | if(!cop1_usable) { | |
5585 | cs=get_reg(i_regmap,CSREG); | |
5586 | assert(cs>=0); | |
5587 | emit_testimm(cs,0x20000000); | |
5588 | eaddr=(int)out; | |
5589 | emit_jeq(0); | |
5590 | add_stub(FP_STUB,eaddr,(int)out,i,cs,(int)i_regs,0,0); | |
5591 | cop1_usable=1; | |
5592 | } | |
5593 | ||
e1190b87 | 5594 | if(ooo[i]) { |
57871462 | 5595 | // Out of order execution (delay slot first) |
5596 | //printf("OOOE\n"); | |
5597 | ds_assemble(i+1,i_regs); | |
5598 | int adj; | |
5599 | uint64_t bc_unneeded=branch_regs[i].u; | |
5600 | uint64_t bc_unneeded_upper=branch_regs[i].uu; | |
5601 | bc_unneeded&=~((1LL<<rs1[i])|(1LL<<rs2[i])); | |
5602 | bc_unneeded_upper&=~((1LL<<us1[i])|(1LL<<us2[i])); | |
5603 | bc_unneeded|=1; | |
5604 | bc_unneeded_upper|=1; | |
5605 | wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32, | |
5606 | bc_unneeded,bc_unneeded_upper); | |
5607 | load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i],rs1[i]); | |
5608 | load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG); | |
5609 | cc=get_reg(branch_regs[i].regmap,CCREG); | |
5610 | assert(cc==HOST_CCREG); | |
5611 | do_cc(i,branch_regs[i].regmap,&adj,-1,0,invert); | |
5612 | assem_debug("cycle count (adj)\n"); | |
5613 | if(1) { | |
5614 | int nottaken=0; | |
2573466a | 5615 | if(adj&&!invert) emit_addimm(cc,CLOCK_ADJUST(ccadj[i]+2-adj),cc); |
57871462 | 5616 | if(1) { |
5617 | assert(fs>=0); | |
5618 | emit_testimm(fs,0x800000); | |
5619 | if(source[i]&0x10000) // BC1T | |
5620 | { | |
5621 | if(invert){ | |
5622 | nottaken=(int)out; | |
5623 | emit_jeq(1); | |
5624 | }else{ | |
5625 | add_to_linker((int)out,ba[i],internal); | |
5626 | emit_jne(0); | |
5627 | } | |
5628 | } | |
5629 | else // BC1F | |
5630 | if(invert){ | |
5631 | nottaken=(int)out; | |
5632 | emit_jne(1); | |
5633 | }else{ | |
5634 | add_to_linker((int)out,ba[i],internal); | |
5635 | emit_jeq(0); | |
5636 | } | |
5637 | { | |
5638 | } | |
5639 | } // if(!only32) | |
9f51b4b9 | 5640 | |
57871462 | 5641 | if(invert) { |
2573466a | 5642 | if(adj) emit_addimm(cc,-CLOCK_ADJUST(adj),cc); |
57871462 | 5643 | #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK |
5644 | else if(match) emit_addnop(13); | |
5645 | #endif | |
5646 | store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]); | |
5647 | load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]); | |
5648 | if(internal) | |
5649 | assem_debug("branch: internal\n"); | |
5650 | else | |
5651 | assem_debug("branch: external\n"); | |
5652 | if(internal&&is_ds[(ba[i]-start)>>2]) { | |
5653 | ds_assemble_entry(i); | |
5654 | } | |
5655 | else { | |
5656 | add_to_linker((int)out,ba[i],internal); | |
5657 | emit_jmp(0); | |
5658 | } | |
5659 | set_jump_target(nottaken,(int)out); | |
5660 | } | |
5661 | ||
5662 | if(adj) { | |
2573466a | 5663 | if(!invert) emit_addimm(cc,CLOCK_ADJUST(adj),cc); |
57871462 | 5664 | } |
5665 | } // (!unconditional) | |
5666 | } // if(ooo) | |
5667 | else | |
5668 | { | |
5669 | // In-order execution (branch first) | |
5670 | //printf("IOE\n"); | |
5671 | int nottaken=0; | |
5672 | if(1) { | |
5673 | //printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]); | |
5674 | if(1) { | |
5675 | assert(fs>=0); | |
5676 | emit_testimm(fs,0x800000); | |
5677 | if(source[i]&0x10000) // BC1T | |
5678 | { | |
5679 | nottaken=(int)out; | |
5680 | emit_jeq(1); | |
5681 | } | |
5682 | else // BC1F | |
5683 | { | |
5684 | nottaken=(int)out; | |
5685 | emit_jne(1); | |
5686 | } | |
5687 | } | |
5688 | } // if(!unconditional) | |
5689 | int adj; | |
5690 | uint64_t ds_unneeded=branch_regs[i].u; | |
5691 | uint64_t ds_unneeded_upper=branch_regs[i].uu; | |
5692 | ds_unneeded&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1])); | |
5693 | ds_unneeded_upper&=~((1LL<<us1[i+1])|(1LL<<us2[i+1])); | |
5694 | if((~ds_unneeded_upper>>rt1[i+1])&1) ds_unneeded_upper&=~((1LL<<dep1[i+1])|(1LL<<dep2[i+1])); | |
5695 | ds_unneeded|=1; | |
5696 | ds_unneeded_upper|=1; | |
5697 | // branch taken | |
5698 | //assem_debug("1:\n"); | |
5699 | wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32, | |
5700 | ds_unneeded,ds_unneeded_upper); | |
5701 | // load regs | |
5702 | load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]); | |
5703 | address_generation(i+1,&branch_regs[i],0); | |
5704 | load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,INVCP); | |
5705 | ds_assemble(i+1,&branch_regs[i]); | |
5706 | cc=get_reg(branch_regs[i].regmap,CCREG); | |
5707 | if(cc==-1) { | |
5708 | emit_loadreg(CCREG,cc=HOST_CCREG); | |
5709 | // CHECK: Is the following instruction (fall thru) allocated ok? | |
5710 | } | |
5711 | assert(cc==HOST_CCREG); | |
5712 | store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]); | |
5713 | do_cc(i,i_regmap,&adj,ba[i],TAKEN,0); | |
5714 | assem_debug("cycle count (adj)\n"); | |
2573466a | 5715 | if(adj) emit_addimm(cc,CLOCK_ADJUST(ccadj[i]+2-adj),cc); |
57871462 | 5716 | load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]); |
5717 | if(internal) | |
5718 | assem_debug("branch: internal\n"); | |
5719 | else | |
5720 | assem_debug("branch: external\n"); | |
5721 | if(internal&&is_ds[(ba[i]-start)>>2]) { | |
5722 | ds_assemble_entry(i); | |
5723 | } | |
5724 | else { | |
5725 | add_to_linker((int)out,ba[i],internal); | |
5726 | emit_jmp(0); | |
5727 | } | |
5728 | ||
5729 | // branch not taken | |
5730 | if(1) { // <- FIXME (don't need this) | |
5731 | set_jump_target(nottaken,(int)out); | |
5732 | assem_debug("1:\n"); | |
5733 | if(!likely[i]) { | |
5734 | wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32, | |
5735 | ds_unneeded,ds_unneeded_upper); | |
5736 | load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]); | |
5737 | address_generation(i+1,&branch_regs[i],0); | |
5738 | load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG); | |
5739 | ds_assemble(i+1,&branch_regs[i]); | |
5740 | } | |
5741 | cc=get_reg(branch_regs[i].regmap,CCREG); | |
5742 | if(cc==-1&&!likely[i]) { | |
5743 | // Cycle count isn't in a register, temporarily load it then write it out | |
5744 | emit_loadreg(CCREG,HOST_CCREG); | |
2573466a | 5745 | emit_addimm_and_set_flags(CLOCK_ADJUST(ccadj[i]+2),HOST_CCREG); |
57871462 | 5746 | int jaddr=(int)out; |
5747 | emit_jns(0); | |
5748 | add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,NOTTAKEN,0); | |
5749 | emit_storereg(CCREG,HOST_CCREG); | |
5750 | } | |
5751 | else{ | |
5752 | cc=get_reg(i_regmap,CCREG); | |
5753 | assert(cc==HOST_CCREG); | |
2573466a | 5754 | emit_addimm_and_set_flags(CLOCK_ADJUST(ccadj[i]+2),cc); |
57871462 | 5755 | int jaddr=(int)out; |
5756 | emit_jns(0); | |
5757 | add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,likely[i]?NULLDS:NOTTAKEN,0); | |
5758 | } | |
5759 | } | |
5760 | } | |
5761 | } | |
5762 | ||
5763 | static void pagespan_assemble(int i,struct regstat *i_regs) | |
5764 | { | |
5765 | int s1l=get_reg(i_regs->regmap,rs1[i]); | |
5766 | int s1h=get_reg(i_regs->regmap,rs1[i]|64); | |
5767 | int s2l=get_reg(i_regs->regmap,rs2[i]); | |
5768 | int s2h=get_reg(i_regs->regmap,rs2[i]|64); | |
57871462 | 5769 | int taken=0; |
5770 | int nottaken=0; | |
5771 | int unconditional=0; | |
5772 | if(rs1[i]==0) | |
5773 | { | |
5774 | s1l=s2l;s1h=s2h; | |
5775 | s2l=s2h=-1; | |
5776 | } | |
5777 | else if(rs2[i]==0) | |
5778 | { | |
5779 | s2l=s2h=-1; | |
5780 | } | |
5781 | if((i_regs->is32>>rs1[i])&(i_regs->is32>>rs2[i])&1) { | |
5782 | s1h=s2h=-1; | |
5783 | } | |
5784 | int hr=0; | |
581335b0 | 5785 | int addr=-1,alt=-1,ntaddr=-1; |
57871462 | 5786 | if(i_regs->regmap[HOST_BTREG]<0) {addr=HOST_BTREG;} |
5787 | else { | |
5788 | while(hr<HOST_REGS) | |
5789 | { | |
5790 | if(hr!=EXCLUDE_REG && hr!=HOST_CCREG && | |
5791 | (i_regs->regmap[hr]&63)!=rs1[i] && | |
5792 | (i_regs->regmap[hr]&63)!=rs2[i] ) | |
5793 | { | |
5794 | addr=hr++;break; | |
5795 | } | |
5796 | hr++; | |
5797 | } | |
5798 | } | |
5799 | while(hr<HOST_REGS) | |
5800 | { | |
5801 | if(hr!=EXCLUDE_REG && hr!=HOST_CCREG && hr!=HOST_BTREG && | |
5802 | (i_regs->regmap[hr]&63)!=rs1[i] && | |
5803 | (i_regs->regmap[hr]&63)!=rs2[i] ) | |
5804 | { | |
5805 | alt=hr++;break; | |
5806 | } | |
5807 | hr++; | |
5808 | } | |
5809 | if((opcode[i]&0x2E)==6) // BLEZ/BGTZ needs another register | |
5810 | { | |
5811 | while(hr<HOST_REGS) | |
5812 | { | |
5813 | if(hr!=EXCLUDE_REG && hr!=HOST_CCREG && hr!=HOST_BTREG && | |
5814 | (i_regs->regmap[hr]&63)!=rs1[i] && | |
5815 | (i_regs->regmap[hr]&63)!=rs2[i] ) | |
5816 | { | |
5817 | ntaddr=hr;break; | |
5818 | } | |
5819 | hr++; | |
5820 | } | |
5821 | } | |
5822 | assert(hr<HOST_REGS); | |
5823 | if((opcode[i]&0x2e)==4||opcode[i]==0x11) { // BEQ/BNE/BEQL/BNEL/BC1 | |
5824 | load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,CCREG,CCREG); | |
5825 | } | |
2573466a | 5826 | emit_addimm(HOST_CCREG,CLOCK_ADJUST(ccadj[i]+2),HOST_CCREG); |
57871462 | 5827 | if(opcode[i]==2) // J |
5828 | { | |
5829 | unconditional=1; | |
5830 | } | |
5831 | if(opcode[i]==3) // JAL | |
5832 | { | |
5833 | // TODO: mini_ht | |
5834 | int rt=get_reg(i_regs->regmap,31); | |
5835 | emit_movimm(start+i*4+8,rt); | |
5836 | unconditional=1; | |
5837 | } | |
5838 | if(opcode[i]==0&&(opcode2[i]&0x3E)==8) // JR/JALR | |
5839 | { | |
5840 | emit_mov(s1l,addr); | |
5841 | if(opcode2[i]==9) // JALR | |
5842 | { | |
5067f341 | 5843 | int rt=get_reg(i_regs->regmap,rt1[i]); |
57871462 | 5844 | emit_movimm(start+i*4+8,rt); |
5845 | } | |
5846 | } | |
5847 | if((opcode[i]&0x3f)==4) // BEQ | |
5848 | { | |
5849 | if(rs1[i]==rs2[i]) | |
5850 | { | |
5851 | unconditional=1; | |
5852 | } | |
5853 | else | |
5854 | #ifdef HAVE_CMOV_IMM | |
5855 | if(s1h<0) { | |
5856 | if(s2l>=0) emit_cmp(s1l,s2l); | |
5857 | else emit_test(s1l,s1l); | |
5858 | emit_cmov2imm_e_ne_compact(ba[i],start+i*4+8,addr); | |
5859 | } | |
5860 | else | |
5861 | #endif | |
5862 | { | |
5863 | assert(s1l>=0); | |
5864 | emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt); | |
5865 | if(s1h>=0) { | |
5866 | if(s2h>=0) emit_cmp(s1h,s2h); | |
5867 | else emit_test(s1h,s1h); | |
5868 | emit_cmovne_reg(alt,addr); | |
5869 | } | |
5870 | if(s2l>=0) emit_cmp(s1l,s2l); | |
5871 | else emit_test(s1l,s1l); | |
5872 | emit_cmovne_reg(alt,addr); | |
5873 | } | |
5874 | } | |
5875 | if((opcode[i]&0x3f)==5) // BNE | |
5876 | { | |
5877 | #ifdef HAVE_CMOV_IMM | |
5878 | if(s1h<0) { | |
5879 | if(s2l>=0) emit_cmp(s1l,s2l); | |
5880 | else emit_test(s1l,s1l); | |
5881 | emit_cmov2imm_e_ne_compact(start+i*4+8,ba[i],addr); | |
5882 | } | |
5883 | else | |
5884 | #endif | |
5885 | { | |
5886 | assert(s1l>=0); | |
5887 | emit_mov2imm_compact(start+i*4+8,addr,ba[i],alt); | |
5888 | if(s1h>=0) { | |
5889 | if(s2h>=0) emit_cmp(s1h,s2h); | |
5890 | else emit_test(s1h,s1h); | |
5891 | emit_cmovne_reg(alt,addr); | |
5892 | } | |
5893 | if(s2l>=0) emit_cmp(s1l,s2l); | |
5894 | else emit_test(s1l,s1l); | |
5895 | emit_cmovne_reg(alt,addr); | |
5896 | } | |
5897 | } | |
5898 | if((opcode[i]&0x3f)==0x14) // BEQL | |
5899 | { | |
5900 | if(s1h>=0) { | |
5901 | if(s2h>=0) emit_cmp(s1h,s2h); | |
5902 | else emit_test(s1h,s1h); | |
5903 | nottaken=(int)out; | |
5904 | emit_jne(0); | |
5905 | } | |
5906 | if(s2l>=0) emit_cmp(s1l,s2l); | |
5907 | else emit_test(s1l,s1l); | |
5908 | if(nottaken) set_jump_target(nottaken,(int)out); | |
5909 | nottaken=(int)out; | |
5910 | emit_jne(0); | |
5911 | } | |
5912 | if((opcode[i]&0x3f)==0x15) // BNEL | |
5913 | { | |
5914 | if(s1h>=0) { | |
5915 | if(s2h>=0) emit_cmp(s1h,s2h); | |
5916 | else emit_test(s1h,s1h); | |
5917 | taken=(int)out; | |
5918 | emit_jne(0); | |
5919 | } | |
5920 | if(s2l>=0) emit_cmp(s1l,s2l); | |
5921 | else emit_test(s1l,s1l); | |
5922 | nottaken=(int)out; | |
5923 | emit_jeq(0); | |
5924 | if(taken) set_jump_target(taken,(int)out); | |
5925 | } | |
5926 | if((opcode[i]&0x3f)==6) // BLEZ | |
5927 | { | |
5928 | emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr); | |
5929 | emit_cmpimm(s1l,1); | |
5930 | if(s1h>=0) emit_mov(addr,ntaddr); | |
5931 | emit_cmovl_reg(alt,addr); | |
5932 | if(s1h>=0) { | |
5933 | emit_test(s1h,s1h); | |
5934 | emit_cmovne_reg(ntaddr,addr); | |
5935 | emit_cmovs_reg(alt,addr); | |
5936 | } | |
5937 | } | |
5938 | if((opcode[i]&0x3f)==7) // BGTZ | |
5939 | { | |
5940 | emit_mov2imm_compact(ba[i],addr,start+i*4+8,ntaddr); | |
5941 | emit_cmpimm(s1l,1); | |
5942 | if(s1h>=0) emit_mov(addr,alt); | |
5943 | emit_cmovl_reg(ntaddr,addr); | |
5944 | if(s1h>=0) { | |
5945 | emit_test(s1h,s1h); | |
5946 | emit_cmovne_reg(alt,addr); | |
5947 | emit_cmovs_reg(ntaddr,addr); | |
5948 | } | |
5949 | } | |
5950 | if((opcode[i]&0x3f)==0x16) // BLEZL | |
5951 | { | |
5952 | assert((opcode[i]&0x3f)!=0x16); | |
5953 | } | |
5954 | if((opcode[i]&0x3f)==0x17) // BGTZL | |
5955 | { | |
5956 | assert((opcode[i]&0x3f)!=0x17); | |
5957 | } | |
5958 | assert(opcode[i]!=1); // BLTZ/BGEZ | |
5959 | ||
5960 | //FIXME: Check CSREG | |
5961 | if(opcode[i]==0x11 && opcode2[i]==0x08 ) { | |
5962 | if((source[i]&0x30000)==0) // BC1F | |
5963 | { | |
5964 | emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt); | |
5965 | emit_testimm(s1l,0x800000); | |
5966 | emit_cmovne_reg(alt,addr); | |
5967 | } | |
5968 | if((source[i]&0x30000)==0x10000) // BC1T | |
5969 | { | |
5970 | emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr); | |
5971 | emit_testimm(s1l,0x800000); | |
5972 | emit_cmovne_reg(alt,addr); | |
5973 | } | |
5974 | if((source[i]&0x30000)==0x20000) // BC1FL | |
5975 | { | |
5976 | emit_testimm(s1l,0x800000); | |
5977 | nottaken=(int)out; | |
5978 | emit_jne(0); | |
5979 | } | |
5980 | if((source[i]&0x30000)==0x30000) // BC1TL | |
5981 | { | |
5982 | emit_testimm(s1l,0x800000); | |
5983 | nottaken=(int)out; | |
5984 | emit_jeq(0); | |
5985 | } | |
5986 | } | |
5987 | ||
5988 | assert(i_regs->regmap[HOST_CCREG]==CCREG); | |
5989 | wb_dirtys(regs[i].regmap,regs[i].is32,regs[i].dirty); | |
5990 | if(likely[i]||unconditional) | |
5991 | { | |
5992 | emit_movimm(ba[i],HOST_BTREG); | |
5993 | } | |
5994 | else if(addr!=HOST_BTREG) | |
5995 | { | |
5996 | emit_mov(addr,HOST_BTREG); | |
5997 | } | |
5998 | void *branch_addr=out; | |
5999 | emit_jmp(0); | |
6000 | int target_addr=start+i*4+5; | |
6001 | void *stub=out; | |
6002 | void *compiled_target_addr=check_addr(target_addr); | |
6003 | emit_extjump_ds((int)branch_addr,target_addr); | |
6004 | if(compiled_target_addr) { | |
6005 | set_jump_target((int)branch_addr,(int)compiled_target_addr); | |
6006 | add_link(target_addr,stub); | |
6007 | } | |
6008 | else set_jump_target((int)branch_addr,(int)stub); | |
6009 | if(likely[i]) { | |
6010 | // Not-taken path | |
6011 | set_jump_target((int)nottaken,(int)out); | |
6012 | wb_dirtys(regs[i].regmap,regs[i].is32,regs[i].dirty); | |
6013 | void *branch_addr=out; | |
6014 | emit_jmp(0); | |
6015 | int target_addr=start+i*4+8; | |
6016 | void *stub=out; | |
6017 | void *compiled_target_addr=check_addr(target_addr); | |
6018 | emit_extjump_ds((int)branch_addr,target_addr); | |
6019 | if(compiled_target_addr) { | |
6020 | set_jump_target((int)branch_addr,(int)compiled_target_addr); | |
6021 | add_link(target_addr,stub); | |
6022 | } | |
6023 | else set_jump_target((int)branch_addr,(int)stub); | |
6024 | } | |
6025 | } | |
6026 | ||
6027 | // Assemble the delay slot for the above | |
6028 | static void pagespan_ds() | |
6029 | { | |
6030 | assem_debug("initial delay slot:\n"); | |
6031 | u_int vaddr=start+1; | |
94d23bb9 | 6032 | u_int page=get_page(vaddr); |
6033 | u_int vpage=get_vpage(vaddr); | |
57871462 | 6034 | ll_add(jump_dirty+vpage,vaddr,(void *)out); |
6035 | do_dirty_stub_ds(); | |
6036 | ll_add(jump_in+page,vaddr,(void *)out); | |
6037 | assert(regs[0].regmap_entry[HOST_CCREG]==CCREG); | |
6038 | if(regs[0].regmap[HOST_CCREG]!=CCREG) | |
6039 | wb_register(CCREG,regs[0].regmap_entry,regs[0].wasdirty,regs[0].was32); | |
6040 | if(regs[0].regmap[HOST_BTREG]!=BTREG) | |
6041 | emit_writeword(HOST_BTREG,(int)&branch_target); | |
6042 | load_regs(regs[0].regmap_entry,regs[0].regmap,regs[0].was32,rs1[0],rs2[0]); | |
6043 | address_generation(0,®s[0],regs[0].regmap_entry); | |
b9b61529 | 6044 | if(itype[0]==STORE||itype[0]==STORELR||(opcode[0]&0x3b)==0x39||(opcode[0]&0x3b)==0x3a) |
57871462 | 6045 | load_regs(regs[0].regmap_entry,regs[0].regmap,regs[0].was32,INVCP,INVCP); |
6046 | cop1_usable=0; | |
6047 | is_delayslot=0; | |
6048 | switch(itype[0]) { | |
6049 | case ALU: | |
6050 | alu_assemble(0,®s[0]);break; | |
6051 | case IMM16: | |
6052 | imm16_assemble(0,®s[0]);break; | |
6053 | case SHIFT: | |
6054 | shift_assemble(0,®s[0]);break; | |
6055 | case SHIFTIMM: | |
6056 | shiftimm_assemble(0,®s[0]);break; | |
6057 | case LOAD: | |
6058 | load_assemble(0,®s[0]);break; | |
6059 | case LOADLR: | |
6060 | loadlr_assemble(0,®s[0]);break; | |
6061 | case STORE: | |
6062 | store_assemble(0,®s[0]);break; | |
6063 | case STORELR: | |
6064 | storelr_assemble(0,®s[0]);break; | |
6065 | case COP0: | |
6066 | cop0_assemble(0,®s[0]);break; | |
6067 | case COP1: | |
6068 | cop1_assemble(0,®s[0]);break; | |
6069 | case C1LS: | |
6070 | c1ls_assemble(0,®s[0]);break; | |
b9b61529 | 6071 | case COP2: |
6072 | cop2_assemble(0,®s[0]);break; | |
6073 | case C2LS: | |
6074 | c2ls_assemble(0,®s[0]);break; | |
6075 | case C2OP: | |
6076 | c2op_assemble(0,®s[0]);break; | |
57871462 | 6077 | case FCONV: |
6078 | fconv_assemble(0,®s[0]);break; | |
6079 | case FLOAT: | |
6080 | float_assemble(0,®s[0]);break; | |
6081 | case FCOMP: | |
6082 | fcomp_assemble(0,®s[0]);break; | |
6083 | case MULTDIV: | |
6084 | multdiv_assemble(0,®s[0]);break; | |
6085 | case MOV: | |
6086 | mov_assemble(0,®s[0]);break; | |
6087 | case SYSCALL: | |
7139f3c8 | 6088 | case HLECALL: |
1e973cb0 | 6089 | case INTCALL: |
57871462 | 6090 | case SPAN: |
6091 | case UJUMP: | |
6092 | case RJUMP: | |
6093 | case CJUMP: | |
6094 | case SJUMP: | |
6095 | case FJUMP: | |
c43b5311 | 6096 | SysPrintf("Jump in the delay slot. This is probably a bug.\n"); |
57871462 | 6097 | } |
6098 | int btaddr=get_reg(regs[0].regmap,BTREG); | |
6099 | if(btaddr<0) { | |
6100 | btaddr=get_reg(regs[0].regmap,-1); | |
6101 | emit_readword((int)&branch_target,btaddr); | |
6102 | } | |
6103 | assert(btaddr!=HOST_CCREG); | |
6104 | if(regs[0].regmap[HOST_CCREG]!=CCREG) emit_loadreg(CCREG,HOST_CCREG); | |
6105 | #ifdef HOST_IMM8 | |
6106 | emit_movimm(start+4,HOST_TEMPREG); | |
6107 | emit_cmp(btaddr,HOST_TEMPREG); | |
6108 | #else | |
6109 | emit_cmpimm(btaddr,start+4); | |
6110 | #endif | |
6111 | int branch=(int)out; | |
6112 | emit_jeq(0); | |
6113 | store_regs_bt(regs[0].regmap,regs[0].is32,regs[0].dirty,-1); | |
6114 | emit_jmp(jump_vaddr_reg[btaddr]); | |
6115 | set_jump_target(branch,(int)out); | |
6116 | store_regs_bt(regs[0].regmap,regs[0].is32,regs[0].dirty,start+4); | |
6117 | load_regs_bt(regs[0].regmap,regs[0].is32,regs[0].dirty,start+4); | |
6118 | } | |
6119 | ||
6120 | // Basic liveness analysis for MIPS registers | |
6121 | void unneeded_registers(int istart,int iend,int r) | |
6122 | { | |
6123 | int i; | |
bedfea38 | 6124 | uint64_t u,uu,gte_u,b,bu,gte_bu; |
0ff8c62c | 6125 | uint64_t temp_u,temp_uu,temp_gte_u=0; |
57871462 | 6126 | uint64_t tdep; |
0ff8c62c | 6127 | uint64_t gte_u_unknown=0; |
6128 | if(new_dynarec_hacks&NDHACK_GTE_UNNEEDED) | |
6129 | gte_u_unknown=~0ll; | |
57871462 | 6130 | if(iend==slen-1) { |
6131 | u=1;uu=1; | |
0ff8c62c | 6132 | gte_u=gte_u_unknown; |
57871462 | 6133 | }else{ |
6134 | u=unneeded_reg[iend+1]; | |
6135 | uu=unneeded_reg_upper[iend+1]; | |
6136 | u=1;uu=1; | |
0ff8c62c | 6137 | gte_u=gte_unneeded[iend+1]; |
57871462 | 6138 | } |
bedfea38 | 6139 | |
57871462 | 6140 | for (i=iend;i>=istart;i--) |
6141 | { | |
6142 | //printf("unneeded registers i=%d (%d,%d) r=%d\n",i,istart,iend,r); | |
6143 | if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP) | |
6144 | { | |
6145 | // If subroutine call, flag return address as a possible branch target | |
6146 | if(rt1[i]==31 && i<slen-2) bt[i+2]=1; | |
9f51b4b9 | 6147 | |
57871462 | 6148 | if(ba[i]<start || ba[i]>=(start+slen*4)) |
6149 | { | |
6150 | // Branch out of this block, flush all regs | |
6151 | u=1; | |
6152 | uu=1; | |
0ff8c62c | 6153 | gte_u=gte_u_unknown; |
9f51b4b9 | 6154 | /* Hexagon hack |
57871462 | 6155 | if(itype[i]==UJUMP&&rt1[i]==31) |
6156 | { | |
6157 | uu=u=0x300C00F; // Discard at, v0-v1, t6-t9 | |
6158 | } | |
6159 | if(itype[i]==RJUMP&&rs1[i]==31) | |
6160 | { | |
6161 | uu=u=0x300C0F3; // Discard at, a0-a3, t6-t9 | |
6162 | } | |
4cb76aa4 | 6163 | if(start>0x80000400&&start<0x80000000+RAM_SIZE) { |
57871462 | 6164 | if(itype[i]==UJUMP&&rt1[i]==31) |
6165 | { | |
6166 | //uu=u=0x30300FF0FLL; // Discard at, v0-v1, t0-t9, lo, hi | |
6167 | uu=u=0x300FF0F; // Discard at, v0-v1, t0-t9 | |
6168 | } | |
6169 | if(itype[i]==RJUMP&&rs1[i]==31) | |
6170 | { | |
6171 | //uu=u=0x30300FFF3LL; // Discard at, a0-a3, t0-t9, lo, hi | |
6172 | uu=u=0x300FFF3; // Discard at, a0-a3, t0-t9 | |
6173 | } | |
6174 | }*/ | |
6175 | branch_unneeded_reg[i]=u; | |
6176 | branch_unneeded_reg_upper[i]=uu; | |
6177 | // Merge in delay slot | |
6178 | tdep=(~uu>>rt1[i+1])&1; | |
6179 | u|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]); | |
6180 | uu|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]); | |
6181 | u&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1])); | |
6182 | uu&=~((1LL<<us1[i+1])|(1LL<<us2[i+1])); | |
6183 | uu&=~((tdep<<dep1[i+1])|(tdep<<dep2[i+1])); | |
6184 | u|=1;uu|=1; | |
bedfea38 | 6185 | gte_u|=gte_rt[i+1]; |
6186 | gte_u&=~gte_rs[i+1]; | |
57871462 | 6187 | // If branch is "likely" (and conditional) |
6188 | // then we skip the delay slot on the fall-thru path | |
6189 | if(likely[i]) { | |
6190 | if(i<slen-1) { | |
6191 | u&=unneeded_reg[i+2]; | |
6192 | uu&=unneeded_reg_upper[i+2]; | |
bedfea38 | 6193 | gte_u&=gte_unneeded[i+2]; |
57871462 | 6194 | } |
6195 | else | |
6196 | { | |
6197 | u=1; | |
6198 | uu=1; | |
0ff8c62c | 6199 | gte_u=gte_u_unknown; |
57871462 | 6200 | } |
6201 | } | |
6202 | } | |
6203 | else | |
6204 | { | |
6205 | // Internal branch, flag target | |
6206 | bt[(ba[i]-start)>>2]=1; | |
6207 | if(ba[i]<=start+i*4) { | |
6208 | // Backward branch | |
6209 | if(itype[i]==RJUMP||itype[i]==UJUMP||(source[i]>>16)==0x1000) | |
6210 | { | |
6211 | // Unconditional branch | |
6212 | temp_u=1;temp_uu=1; | |
bedfea38 | 6213 | temp_gte_u=0; |
57871462 | 6214 | } else { |
6215 | // Conditional branch (not taken case) | |
6216 | temp_u=unneeded_reg[i+2]; | |
6217 | temp_uu=unneeded_reg_upper[i+2]; | |
bedfea38 | 6218 | temp_gte_u&=gte_unneeded[i+2]; |
57871462 | 6219 | } |
6220 | // Merge in delay slot | |
6221 | tdep=(~temp_uu>>rt1[i+1])&1; | |
6222 | temp_u|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]); | |
6223 | temp_uu|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]); | |
6224 | temp_u&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1])); | |
6225 | temp_uu&=~((1LL<<us1[i+1])|(1LL<<us2[i+1])); | |
6226 | temp_uu&=~((tdep<<dep1[i+1])|(tdep<<dep2[i+1])); | |
6227 | temp_u|=1;temp_uu|=1; | |
bedfea38 | 6228 | temp_gte_u|=gte_rt[i+1]; |
6229 | temp_gte_u&=~gte_rs[i+1]; | |
57871462 | 6230 | // If branch is "likely" (and conditional) |
6231 | // then we skip the delay slot on the fall-thru path | |
6232 | if(likely[i]) { | |
6233 | if(i<slen-1) { | |
6234 | temp_u&=unneeded_reg[i+2]; | |
6235 | temp_uu&=unneeded_reg_upper[i+2]; | |
bedfea38 | 6236 | temp_gte_u&=gte_unneeded[i+2]; |
57871462 | 6237 | } |
6238 | else | |
6239 | { | |
6240 | temp_u=1; | |
6241 | temp_uu=1; | |
0ff8c62c | 6242 | temp_gte_u=gte_u_unknown; |
57871462 | 6243 | } |
6244 | } | |
6245 | tdep=(~temp_uu>>rt1[i])&1; | |
6246 | temp_u|=(1LL<<rt1[i])|(1LL<<rt2[i]); | |
6247 | temp_uu|=(1LL<<rt1[i])|(1LL<<rt2[i]); | |
6248 | temp_u&=~((1LL<<rs1[i])|(1LL<<rs2[i])); | |
6249 | temp_uu&=~((1LL<<us1[i])|(1LL<<us2[i])); | |
6250 | temp_uu&=~((tdep<<dep1[i])|(tdep<<dep2[i])); | |
6251 | temp_u|=1;temp_uu|=1; | |
bedfea38 | 6252 | temp_gte_u|=gte_rt[i]; |
6253 | temp_gte_u&=~gte_rs[i]; | |
57871462 | 6254 | unneeded_reg[i]=temp_u; |
6255 | unneeded_reg_upper[i]=temp_uu; | |
bedfea38 | 6256 | gte_unneeded[i]=temp_gte_u; |
57871462 | 6257 | // Only go three levels deep. This recursion can take an |
6258 | // excessive amount of time if there are a lot of nested loops. | |
6259 | if(r<2) { | |
6260 | unneeded_registers((ba[i]-start)>>2,i-1,r+1); | |
6261 | }else{ | |
6262 | unneeded_reg[(ba[i]-start)>>2]=1; | |
6263 | unneeded_reg_upper[(ba[i]-start)>>2]=1; | |
0ff8c62c | 6264 | gte_unneeded[(ba[i]-start)>>2]=gte_u_unknown; |
57871462 | 6265 | } |
6266 | } /*else*/ if(1) { | |
6267 | if(itype[i]==RJUMP||itype[i]==UJUMP||(source[i]>>16)==0x1000) | |
6268 | { | |
6269 | // Unconditional branch | |
6270 | u=unneeded_reg[(ba[i]-start)>>2]; | |
6271 | uu=unneeded_reg_upper[(ba[i]-start)>>2]; | |
bedfea38 | 6272 | gte_u=gte_unneeded[(ba[i]-start)>>2]; |
57871462 | 6273 | branch_unneeded_reg[i]=u; |
6274 | branch_unneeded_reg_upper[i]=uu; | |
6275 | //u=1; | |
6276 | //uu=1; | |
6277 | //branch_unneeded_reg[i]=u; | |
6278 | //branch_unneeded_reg_upper[i]=uu; | |
6279 | // Merge in delay slot | |
6280 | tdep=(~uu>>rt1[i+1])&1; | |
6281 | u|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]); | |
6282 | uu|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]); | |
6283 | u&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1])); | |
6284 | uu&=~((1LL<<us1[i+1])|(1LL<<us2[i+1])); | |
6285 | uu&=~((tdep<<dep1[i+1])|(tdep<<dep2[i+1])); | |
6286 | u|=1;uu|=1; | |
bedfea38 | 6287 | gte_u|=gte_rt[i+1]; |
6288 | gte_u&=~gte_rs[i+1]; | |
57871462 | 6289 | } else { |
6290 | // Conditional branch | |
6291 | b=unneeded_reg[(ba[i]-start)>>2]; | |
6292 | bu=unneeded_reg_upper[(ba[i]-start)>>2]; | |
bedfea38 | 6293 | gte_bu=gte_unneeded[(ba[i]-start)>>2]; |
57871462 | 6294 | branch_unneeded_reg[i]=b; |
6295 | branch_unneeded_reg_upper[i]=bu; | |
6296 | //b=1; | |
6297 | //bu=1; | |
6298 | //branch_unneeded_reg[i]=b; | |
6299 | //branch_unneeded_reg_upper[i]=bu; | |
6300 | // Branch delay slot | |
6301 | tdep=(~uu>>rt1[i+1])&1; | |
6302 | b|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]); | |
6303 | bu|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]); | |
6304 | b&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1])); | |
6305 | bu&=~((1LL<<us1[i+1])|(1LL<<us2[i+1])); | |
6306 | bu&=~((tdep<<dep1[i+1])|(tdep<<dep2[i+1])); | |
6307 | b|=1;bu|=1; | |
bedfea38 | 6308 | gte_bu|=gte_rt[i+1]; |
6309 | gte_bu&=~gte_rs[i+1]; | |
57871462 | 6310 | // If branch is "likely" then we skip the |
6311 | // delay slot on the fall-thru path | |
6312 | if(likely[i]) { | |
6313 | u=b; | |
6314 | uu=bu; | |
bedfea38 | 6315 | gte_u=gte_bu; |
57871462 | 6316 | if(i<slen-1) { |
6317 | u&=unneeded_reg[i+2]; | |
6318 | uu&=unneeded_reg_upper[i+2]; | |
bedfea38 | 6319 | gte_u&=gte_unneeded[i+2]; |
57871462 | 6320 | //u=1; |
6321 | //uu=1; | |
6322 | } | |
6323 | } else { | |
6324 | u&=b; | |
6325 | uu&=bu; | |
bedfea38 | 6326 | gte_u&=gte_bu; |
57871462 | 6327 | //u=1; |
6328 | //uu=1; | |
6329 | } | |
6330 | if(i<slen-1) { | |
6331 | branch_unneeded_reg[i]&=unneeded_reg[i+2]; | |
6332 | branch_unneeded_reg_upper[i]&=unneeded_reg_upper[i+2]; | |
6333 | //branch_unneeded_reg[i]=1; | |
6334 | //branch_unneeded_reg_upper[i]=1; | |
6335 | } else { | |
6336 | branch_unneeded_reg[i]=1; | |
6337 | branch_unneeded_reg_upper[i]=1; | |
6338 | } | |
6339 | } | |
6340 | } | |
6341 | } | |
6342 | } | |
1e973cb0 | 6343 | else if(itype[i]==SYSCALL||itype[i]==HLECALL||itype[i]==INTCALL) |
57871462 | 6344 | { |
6345 | // SYSCALL instruction (software interrupt) | |
6346 | u=1; | |
6347 | uu=1; | |
6348 | } | |
6349 | else if(itype[i]==COP0 && (source[i]&0x3f)==0x18) | |
6350 | { | |
6351 | // ERET instruction (return from interrupt) | |
6352 | u=1; | |
6353 | uu=1; | |
6354 | } | |
6355 | //u=uu=1; // DEBUG | |
6356 | tdep=(~uu>>rt1[i])&1; | |
6357 | // Written registers are unneeded | |
6358 | u|=1LL<<rt1[i]; | |
6359 | u|=1LL<<rt2[i]; | |
6360 | uu|=1LL<<rt1[i]; | |
6361 | uu|=1LL<<rt2[i]; | |
bedfea38 | 6362 | gte_u|=gte_rt[i]; |
57871462 | 6363 | // Accessed registers are needed |
6364 | u&=~(1LL<<rs1[i]); | |
6365 | u&=~(1LL<<rs2[i]); | |
6366 | uu&=~(1LL<<us1[i]); | |
6367 | uu&=~(1LL<<us2[i]); | |
bedfea38 | 6368 | gte_u&=~gte_rs[i]; |
eaa11918 | 6369 | if(gte_rs[i]&&rt1[i]&&(unneeded_reg[i+1]&(1ll<<rt1[i]))) |
cbbd8dd7 | 6370 | gte_u|=gte_rs[i]>e_unneeded[i+1]; // MFC2/CFC2 to dead register, unneeded |
57871462 | 6371 | // Source-target dependencies |
6372 | uu&=~(tdep<<dep1[i]); | |
6373 | uu&=~(tdep<<dep2[i]); | |
6374 | // R0 is always unneeded | |
6375 | u|=1;uu|=1; | |
6376 | // Save it | |
6377 | unneeded_reg[i]=u; | |
6378 | unneeded_reg_upper[i]=uu; | |
bedfea38 | 6379 | gte_unneeded[i]=gte_u; |
57871462 | 6380 | /* |
6381 | printf("ur (%d,%d) %x: ",istart,iend,start+i*4); | |
6382 | printf("U:"); | |
6383 | int r; | |
6384 | for(r=1;r<=CCREG;r++) { | |
6385 | if((unneeded_reg[i]>>r)&1) { | |
6386 | if(r==HIREG) printf(" HI"); | |
6387 | else if(r==LOREG) printf(" LO"); | |
6388 | else printf(" r%d",r); | |
6389 | } | |
6390 | } | |
6391 | printf(" UU:"); | |
6392 | for(r=1;r<=CCREG;r++) { | |
6393 | if(((unneeded_reg_upper[i]&~unneeded_reg[i])>>r)&1) { | |
6394 | if(r==HIREG) printf(" HI"); | |
6395 | else if(r==LOREG) printf(" LO"); | |
6396 | else printf(" r%d",r); | |
6397 | } | |
6398 | } | |
6399 | printf("\n");*/ | |
6400 | } | |
252c20fc | 6401 | for (i=iend;i>=istart;i--) |
6402 | { | |
6403 | unneeded_reg_upper[i]=branch_unneeded_reg_upper[i]=-1LL; | |
6404 | } | |
57871462 | 6405 | } |
6406 | ||
71e490c5 | 6407 | // Write back dirty registers as soon as we will no longer modify them, |
6408 | // so that we don't end up with lots of writes at the branches. | |
6409 | void clean_registers(int istart,int iend,int wr) | |
57871462 | 6410 | { |
71e490c5 | 6411 | int i; |
6412 | int r; | |
6413 | u_int will_dirty_i,will_dirty_next,temp_will_dirty; | |
6414 | u_int wont_dirty_i,wont_dirty_next,temp_wont_dirty; | |
6415 | if(iend==slen-1) { | |
6416 | will_dirty_i=will_dirty_next=0; | |
6417 | wont_dirty_i=wont_dirty_next=0; | |
6418 | }else{ | |
6419 | will_dirty_i=will_dirty_next=will_dirty[iend+1]; | |
6420 | wont_dirty_i=wont_dirty_next=wont_dirty[iend+1]; | |
6421 | } | |
6422 | for (i=iend;i>=istart;i--) | |
57871462 | 6423 | { |
71e490c5 | 6424 | if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP) |
57871462 | 6425 | { |
71e490c5 | 6426 | if(ba[i]<start || ba[i]>=(start+slen*4)) |
57871462 | 6427 | { |
71e490c5 | 6428 | // Branch out of this block, flush all regs |
6429 | if(itype[i]==RJUMP||itype[i]==UJUMP||(source[i]>>16)==0x1000) | |
57871462 | 6430 | { |
6431 | // Unconditional branch | |
6432 | will_dirty_i=0; | |
6433 | wont_dirty_i=0; | |
6434 | // Merge in delay slot (will dirty) | |
6435 | for(r=0;r<HOST_REGS;r++) { | |
6436 | if(r!=EXCLUDE_REG) { | |
6437 | if((branch_regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r; | |
6438 | if((branch_regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r; | |
6439 | if((branch_regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r; | |
6440 | if((branch_regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r; | |
6441 | if((branch_regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r); | |
6442 | if(branch_regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r); | |
6443 | if(branch_regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r; | |
6444 | if((regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r; | |
6445 | if((regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r; | |
6446 | if((regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r; | |
6447 | if((regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r; | |
6448 | if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r); | |
6449 | if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r); | |
6450 | if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r; | |
6451 | } | |
6452 | } | |
6453 | } | |
6454 | else | |
6455 | { | |
6456 | // Conditional branch | |
6457 | will_dirty_i=0; | |
6458 | wont_dirty_i=wont_dirty_next; | |
6459 | // Merge in delay slot (will dirty) | |
6460 | for(r=0;r<HOST_REGS;r++) { | |
6461 | if(r!=EXCLUDE_REG) { | |
6462 | if(!likely[i]) { | |
6463 | // Might not dirty if likely branch is not taken | |
6464 | if((branch_regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r; | |
6465 | if((branch_regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r; | |
6466 | if((branch_regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r; | |
6467 | if((branch_regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r; | |
6468 | if((branch_regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r); | |
6469 | if(branch_regs[i].regmap[r]==0) will_dirty_i&=~(1<<r); | |
6470 | if(branch_regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r; | |
6471 | //if((regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r; | |
6472 | //if((regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r; | |
6473 | if((regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r; | |
6474 | if((regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r; | |
6475 | if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r); | |
6476 | if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r); | |
6477 | if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r; | |
6478 | } | |
6479 | } | |
6480 | } | |
6481 | } | |
6482 | // Merge in delay slot (wont dirty) | |
6483 | for(r=0;r<HOST_REGS;r++) { | |
6484 | if(r!=EXCLUDE_REG) { | |
6485 | if((regs[i].regmap[r]&63)==rt1[i]) wont_dirty_i|=1<<r; | |
6486 | if((regs[i].regmap[r]&63)==rt2[i]) wont_dirty_i|=1<<r; | |
6487 | if((regs[i].regmap[r]&63)==rt1[i+1]) wont_dirty_i|=1<<r; | |
6488 | if((regs[i].regmap[r]&63)==rt2[i+1]) wont_dirty_i|=1<<r; | |
6489 | if(regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r; | |
6490 | if((branch_regs[i].regmap[r]&63)==rt1[i]) wont_dirty_i|=1<<r; | |
6491 | if((branch_regs[i].regmap[r]&63)==rt2[i]) wont_dirty_i|=1<<r; | |
6492 | if((branch_regs[i].regmap[r]&63)==rt1[i+1]) wont_dirty_i|=1<<r; | |
6493 | if((branch_regs[i].regmap[r]&63)==rt2[i+1]) wont_dirty_i|=1<<r; | |
6494 | if(branch_regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r; | |
6495 | } | |
6496 | } | |
6497 | if(wr) { | |
6498 | #ifndef DESTRUCTIVE_WRITEBACK | |
6499 | branch_regs[i].dirty&=wont_dirty_i; | |
6500 | #endif | |
6501 | branch_regs[i].dirty|=will_dirty_i; | |
6502 | } | |
6503 | } | |
6504 | else | |
6505 | { | |
6506 | // Internal branch | |
6507 | if(ba[i]<=start+i*4) { | |
6508 | // Backward branch | |
6509 | if(itype[i]==RJUMP||itype[i]==UJUMP||(source[i]>>16)==0x1000) | |
6510 | { | |
6511 | // Unconditional branch | |
6512 | temp_will_dirty=0; | |
6513 | temp_wont_dirty=0; | |
6514 | // Merge in delay slot (will dirty) | |
6515 | for(r=0;r<HOST_REGS;r++) { | |
6516 | if(r!=EXCLUDE_REG) { | |
6517 | if((branch_regs[i].regmap[r]&63)==rt1[i]) temp_will_dirty|=1<<r; | |
6518 | if((branch_regs[i].regmap[r]&63)==rt2[i]) temp_will_dirty|=1<<r; | |
6519 | if((branch_regs[i].regmap[r]&63)==rt1[i+1]) temp_will_dirty|=1<<r; | |
6520 | if((branch_regs[i].regmap[r]&63)==rt2[i+1]) temp_will_dirty|=1<<r; | |
6521 | if((branch_regs[i].regmap[r]&63)>33) temp_will_dirty&=~(1<<r); | |
6522 | if(branch_regs[i].regmap[r]<=0) temp_will_dirty&=~(1<<r); | |
6523 | if(branch_regs[i].regmap[r]==CCREG) temp_will_dirty|=1<<r; | |
6524 | if((regs[i].regmap[r]&63)==rt1[i]) temp_will_dirty|=1<<r; | |
6525 | if((regs[i].regmap[r]&63)==rt2[i]) temp_will_dirty|=1<<r; | |
6526 | if((regs[i].regmap[r]&63)==rt1[i+1]) temp_will_dirty|=1<<r; | |
6527 | if((regs[i].regmap[r]&63)==rt2[i+1]) temp_will_dirty|=1<<r; | |
6528 | if((regs[i].regmap[r]&63)>33) temp_will_dirty&=~(1<<r); | |
6529 | if(regs[i].regmap[r]<=0) temp_will_dirty&=~(1<<r); | |
6530 | if(regs[i].regmap[r]==CCREG) temp_will_dirty|=1<<r; | |
6531 | } | |
6532 | } | |
6533 | } else { | |
6534 | // Conditional branch (not taken case) | |
6535 | temp_will_dirty=will_dirty_next; | |
6536 | temp_wont_dirty=wont_dirty_next; | |
6537 | // Merge in delay slot (will dirty) | |
6538 | for(r=0;r<HOST_REGS;r++) { | |
6539 | if(r!=EXCLUDE_REG) { | |
6540 | if(!likely[i]) { | |
6541 | // Will not dirty if likely branch is not taken | |
6542 | if((branch_regs[i].regmap[r]&63)==rt1[i]) temp_will_dirty|=1<<r; | |
6543 | if((branch_regs[i].regmap[r]&63)==rt2[i]) temp_will_dirty|=1<<r; | |
6544 | if((branch_regs[i].regmap[r]&63)==rt1[i+1]) temp_will_dirty|=1<<r; | |
6545 | if((branch_regs[i].regmap[r]&63)==rt2[i+1]) temp_will_dirty|=1<<r; | |
6546 | if((branch_regs[i].regmap[r]&63)>33) temp_will_dirty&=~(1<<r); | |
6547 | if(branch_regs[i].regmap[r]==0) temp_will_dirty&=~(1<<r); | |
6548 | if(branch_regs[i].regmap[r]==CCREG) temp_will_dirty|=1<<r; | |
6549 | //if((regs[i].regmap[r]&63)==rt1[i]) temp_will_dirty|=1<<r; | |
6550 | //if((regs[i].regmap[r]&63)==rt2[i]) temp_will_dirty|=1<<r; | |
6551 | if((regs[i].regmap[r]&63)==rt1[i+1]) temp_will_dirty|=1<<r; | |
6552 | if((regs[i].regmap[r]&63)==rt2[i+1]) temp_will_dirty|=1<<r; | |
6553 | if((regs[i].regmap[r]&63)>33) temp_will_dirty&=~(1<<r); | |
6554 | if(regs[i].regmap[r]<=0) temp_will_dirty&=~(1<<r); | |
6555 | if(regs[i].regmap[r]==CCREG) temp_will_dirty|=1<<r; | |
6556 | } | |
6557 | } | |
6558 | } | |
6559 | } | |
6560 | // Merge in delay slot (wont dirty) | |
6561 | for(r=0;r<HOST_REGS;r++) { | |
6562 | if(r!=EXCLUDE_REG) { | |
6563 | if((regs[i].regmap[r]&63)==rt1[i]) temp_wont_dirty|=1<<r; | |
6564 | if((regs[i].regmap[r]&63)==rt2[i]) temp_wont_dirty|=1<<r; | |
6565 | if((regs[i].regmap[r]&63)==rt1[i+1]) temp_wont_dirty|=1<<r; | |
6566 | if((regs[i].regmap[r]&63)==rt2[i+1]) temp_wont_dirty|=1<<r; | |
6567 | if(regs[i].regmap[r]==CCREG) temp_wont_dirty|=1<<r; | |
6568 | if((branch_regs[i].regmap[r]&63)==rt1[i]) temp_wont_dirty|=1<<r; | |
6569 | if((branch_regs[i].regmap[r]&63)==rt2[i]) temp_wont_dirty|=1<<r; | |
6570 | if((branch_regs[i].regmap[r]&63)==rt1[i+1]) temp_wont_dirty|=1<<r; | |
6571 | if((branch_regs[i].regmap[r]&63)==rt2[i+1]) temp_wont_dirty|=1<<r; | |
6572 | if(branch_regs[i].regmap[r]==CCREG) temp_wont_dirty|=1<<r; | |
6573 | } | |
6574 | } | |
6575 | // Deal with changed mappings | |
6576 | if(i<iend) { | |
6577 | for(r=0;r<HOST_REGS;r++) { | |
6578 | if(r!=EXCLUDE_REG) { | |
6579 | if(regs[i].regmap[r]!=regmap_pre[i][r]) { | |
6580 | temp_will_dirty&=~(1<<r); | |
6581 | temp_wont_dirty&=~(1<<r); | |
6582 | if((regmap_pre[i][r]&63)>0 && (regmap_pre[i][r]&63)<34) { | |
6583 | temp_will_dirty|=((unneeded_reg[i]>>(regmap_pre[i][r]&63))&1)<<r; | |
6584 | temp_wont_dirty|=((unneeded_reg[i]>>(regmap_pre[i][r]&63))&1)<<r; | |
6585 | } else { | |
6586 | temp_will_dirty|=1<<r; | |
6587 | temp_wont_dirty|=1<<r; | |
6588 | } | |
6589 | } | |
6590 | } | |
6591 | } | |
6592 | } | |
6593 | if(wr) { | |
6594 | will_dirty[i]=temp_will_dirty; | |
6595 | wont_dirty[i]=temp_wont_dirty; | |
6596 | clean_registers((ba[i]-start)>>2,i-1,0); | |
6597 | }else{ | |
6598 | // Limit recursion. It can take an excessive amount | |
6599 | // of time if there are a lot of nested loops. | |
6600 | will_dirty[(ba[i]-start)>>2]=0; | |
6601 | wont_dirty[(ba[i]-start)>>2]=-1; | |
6602 | } | |
6603 | } | |
6604 | /*else*/ if(1) | |
6605 | { | |
6606 | if(itype[i]==RJUMP||itype[i]==UJUMP||(source[i]>>16)==0x1000) | |
6607 | { | |
6608 | // Unconditional branch | |
6609 | will_dirty_i=0; | |
6610 | wont_dirty_i=0; | |
6611 | //if(ba[i]>start+i*4) { // Disable recursion (for debugging) | |
6612 | for(r=0;r<HOST_REGS;r++) { | |
6613 | if(r!=EXCLUDE_REG) { | |
6614 | if(branch_regs[i].regmap[r]==regs[(ba[i]-start)>>2].regmap_entry[r]) { | |
6615 | will_dirty_i|=will_dirty[(ba[i]-start)>>2]&(1<<r); | |
6616 | wont_dirty_i|=wont_dirty[(ba[i]-start)>>2]&(1<<r); | |
6617 | } | |
e3234ecf | 6618 | if(branch_regs[i].regmap[r]>=0) { |
6619 | will_dirty_i|=((unneeded_reg[(ba[i]-start)>>2]>>(branch_regs[i].regmap[r]&63))&1)<<r; | |
6620 | wont_dirty_i|=((unneeded_reg[(ba[i]-start)>>2]>>(branch_regs[i].regmap[r]&63))&1)<<r; | |
6621 | } | |
57871462 | 6622 | } |
6623 | } | |
6624 | //} | |
6625 | // Merge in delay slot | |
6626 | for(r=0;r<HOST_REGS;r++) { | |
6627 | if(r!=EXCLUDE_REG) { | |
6628 | if((branch_regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r; | |
6629 | if((branch_regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r; | |
6630 | if((branch_regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r; | |
6631 | if((branch_regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r; | |
6632 | if((branch_regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r); | |
6633 | if(branch_regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r); | |
6634 | if(branch_regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r; | |
6635 | if((regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r; | |
6636 | if((regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r; | |
6637 | if((regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r; | |
6638 | if((regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r; | |
6639 | if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r); | |
6640 | if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r); | |
6641 | if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r; | |
6642 | } | |
6643 | } | |
6644 | } else { | |
6645 | // Conditional branch | |
6646 | will_dirty_i=will_dirty_next; | |
6647 | wont_dirty_i=wont_dirty_next; | |
6648 | //if(ba[i]>start+i*4) { // Disable recursion (for debugging) | |
6649 | for(r=0;r<HOST_REGS;r++) { | |
6650 | if(r!=EXCLUDE_REG) { | |
e3234ecf | 6651 | signed char target_reg=branch_regs[i].regmap[r]; |
6652 | if(target_reg==regs[(ba[i]-start)>>2].regmap_entry[r]) { | |
57871462 | 6653 | will_dirty_i&=will_dirty[(ba[i]-start)>>2]&(1<<r); |
6654 | wont_dirty_i|=wont_dirty[(ba[i]-start)>>2]&(1<<r); | |
6655 | } | |
e3234ecf | 6656 | else if(target_reg>=0) { |
6657 | will_dirty_i&=((unneeded_reg[(ba[i]-start)>>2]>>(target_reg&63))&1)<<r; | |
6658 | wont_dirty_i|=((unneeded_reg[(ba[i]-start)>>2]>>(target_reg&63))&1)<<r; | |
57871462 | 6659 | } |
6660 | // Treat delay slot as part of branch too | |
6661 | /*if(regs[i+1].regmap[r]==regs[(ba[i]-start)>>2].regmap_entry[r]) { | |
6662 | will_dirty[i+1]&=will_dirty[(ba[i]-start)>>2]&(1<<r); | |
6663 | wont_dirty[i+1]|=wont_dirty[(ba[i]-start)>>2]&(1<<r); | |
6664 | } | |
6665 | else | |
6666 | { | |
6667 | will_dirty[i+1]&=~(1<<r); | |
6668 | }*/ | |
6669 | } | |
6670 | } | |
6671 | //} | |
6672 | // Merge in delay slot | |
6673 | for(r=0;r<HOST_REGS;r++) { | |
6674 | if(r!=EXCLUDE_REG) { | |
6675 | if(!likely[i]) { | |
6676 | // Might not dirty if likely branch is not taken | |
6677 | if((branch_regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r; | |
6678 | if((branch_regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r; | |
6679 | if((branch_regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r; | |
6680 | if((branch_regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r; | |
6681 | if((branch_regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r); | |
6682 | if(branch_regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r); | |
6683 | if(branch_regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r; | |
6684 | //if((regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r; | |
6685 | //if((regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r; | |
6686 | if((regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r; | |
6687 | if((regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r; | |
6688 | if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r); | |
6689 | if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r); | |
6690 | if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r; | |
6691 | } | |
6692 | } | |
6693 | } | |
6694 | } | |
e3234ecf | 6695 | // Merge in delay slot (won't dirty) |
57871462 | 6696 | for(r=0;r<HOST_REGS;r++) { |
6697 | if(r!=EXCLUDE_REG) { | |
6698 | if((regs[i].regmap[r]&63)==rt1[i]) wont_dirty_i|=1<<r; | |
6699 | if((regs[i].regmap[r]&63)==rt2[i]) wont_dirty_i|=1<<r; | |
6700 | if((regs[i].regmap[r]&63)==rt1[i+1]) wont_dirty_i|=1<<r; | |
6701 | if((regs[i].regmap[r]&63)==rt2[i+1]) wont_dirty_i|=1<<r; | |
6702 | if(regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r; | |
6703 | if((branch_regs[i].regmap[r]&63)==rt1[i]) wont_dirty_i|=1<<r; | |
6704 | if((branch_regs[i].regmap[r]&63)==rt2[i]) wont_dirty_i|=1<<r; | |
6705 | if((branch_regs[i].regmap[r]&63)==rt1[i+1]) wont_dirty_i|=1<<r; | |
6706 | if((branch_regs[i].regmap[r]&63)==rt2[i+1]) wont_dirty_i|=1<<r; | |
6707 | if(branch_regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r; | |
6708 | } | |
6709 | } | |
6710 | if(wr) { | |
6711 | #ifndef DESTRUCTIVE_WRITEBACK | |
6712 | branch_regs[i].dirty&=wont_dirty_i; | |
6713 | #endif | |
6714 | branch_regs[i].dirty|=will_dirty_i; | |
6715 | } | |
6716 | } | |
6717 | } | |
6718 | } | |
1e973cb0 | 6719 | else if(itype[i]==SYSCALL||itype[i]==HLECALL||itype[i]==INTCALL) |
57871462 | 6720 | { |
6721 | // SYSCALL instruction (software interrupt) | |
6722 | will_dirty_i=0; | |
6723 | wont_dirty_i=0; | |
6724 | } | |
6725 | else if(itype[i]==COP0 && (source[i]&0x3f)==0x18) | |
6726 | { | |
6727 | // ERET instruction (return from interrupt) | |
6728 | will_dirty_i=0; | |
6729 | wont_dirty_i=0; | |
6730 | } | |
6731 | will_dirty_next=will_dirty_i; | |
6732 | wont_dirty_next=wont_dirty_i; | |
6733 | for(r=0;r<HOST_REGS;r++) { | |
6734 | if(r!=EXCLUDE_REG) { | |
6735 | if((regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r; | |
6736 | if((regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r; | |
6737 | if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r); | |
6738 | if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r); | |
6739 | if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r; | |
6740 | if((regs[i].regmap[r]&63)==rt1[i]) wont_dirty_i|=1<<r; | |
6741 | if((regs[i].regmap[r]&63)==rt2[i]) wont_dirty_i|=1<<r; | |
6742 | if(regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r; | |
6743 | if(i>istart) { | |
9f51b4b9 | 6744 | if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&itype[i]!=CJUMP&&itype[i]!=SJUMP&&itype[i]!=FJUMP) |
57871462 | 6745 | { |
6746 | // Don't store a register immediately after writing it, | |
6747 | // may prevent dual-issue. | |
6748 | if((regs[i].regmap[r]&63)==rt1[i-1]) wont_dirty_i|=1<<r; | |
6749 | if((regs[i].regmap[r]&63)==rt2[i-1]) wont_dirty_i|=1<<r; | |
6750 | } | |
6751 | } | |
6752 | } | |
6753 | } | |
6754 | // Save it | |
6755 | will_dirty[i]=will_dirty_i; | |
6756 | wont_dirty[i]=wont_dirty_i; | |
6757 | // Mark registers that won't be dirtied as not dirty | |
6758 | if(wr) { | |
6759 | /*printf("wr (%d,%d) %x will:",istart,iend,start+i*4); | |
6760 | for(r=0;r<HOST_REGS;r++) { | |
6761 | if((will_dirty_i>>r)&1) { | |
6762 | printf(" r%d",r); | |
6763 | } | |
6764 | } | |
6765 | printf("\n");*/ | |
6766 | ||
6767 | //if(i==istart||(itype[i-1]!=RJUMP&&itype[i-1]!=UJUMP&&itype[i-1]!=CJUMP&&itype[i-1]!=SJUMP&&itype[i-1]!=FJUMP)) { | |
6768 | regs[i].dirty|=will_dirty_i; | |
6769 | #ifndef DESTRUCTIVE_WRITEBACK | |
6770 | regs[i].dirty&=wont_dirty_i; | |
6771 | if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP) | |
6772 | { | |
6773 | if(i<iend-1&&itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000) { | |
6774 | for(r=0;r<HOST_REGS;r++) { | |
6775 | if(r!=EXCLUDE_REG) { | |
6776 | if(regs[i].regmap[r]==regmap_pre[i+2][r]) { | |
6777 | regs[i+2].wasdirty&=wont_dirty_i|~(1<<r); | |
581335b0 | 6778 | }else {/*printf("i: %x (%d) mismatch(+2): %d\n",start+i*4,i,r);assert(!((wont_dirty_i>>r)&1));*/} |
57871462 | 6779 | } |
6780 | } | |
6781 | } | |
6782 | } | |
6783 | else | |
6784 | { | |
6785 | if(i<iend) { | |
6786 | for(r=0;r<HOST_REGS;r++) { | |
6787 | if(r!=EXCLUDE_REG) { | |
6788 | if(regs[i].regmap[r]==regmap_pre[i+1][r]) { | |
6789 | regs[i+1].wasdirty&=wont_dirty_i|~(1<<r); | |
581335b0 | 6790 | }else {/*printf("i: %x (%d) mismatch(+1): %d\n",start+i*4,i,r);assert(!((wont_dirty_i>>r)&1));*/} |
57871462 | 6791 | } |
6792 | } | |
6793 | } | |
6794 | } | |
6795 | #endif | |
6796 | //} | |
6797 | } | |
6798 | // Deal with changed mappings | |
6799 | temp_will_dirty=will_dirty_i; | |
6800 | temp_wont_dirty=wont_dirty_i; | |
6801 | for(r=0;r<HOST_REGS;r++) { | |
6802 | if(r!=EXCLUDE_REG) { | |
6803 | int nr; | |
6804 | if(regs[i].regmap[r]==regmap_pre[i][r]) { | |
6805 | if(wr) { | |
6806 | #ifndef DESTRUCTIVE_WRITEBACK | |
6807 | regs[i].wasdirty&=wont_dirty_i|~(1<<r); | |
6808 | #endif | |
6809 | regs[i].wasdirty|=will_dirty_i&(1<<r); | |
6810 | } | |
6811 | } | |
f776eb14 | 6812 | else if(regmap_pre[i][r]>=0&&(nr=get_reg(regs[i].regmap,regmap_pre[i][r]))>=0) { |
57871462 | 6813 | // Register moved to a different register |
6814 | will_dirty_i&=~(1<<r); | |
6815 | wont_dirty_i&=~(1<<r); | |
6816 | will_dirty_i|=((temp_will_dirty>>nr)&1)<<r; | |
6817 | wont_dirty_i|=((temp_wont_dirty>>nr)&1)<<r; | |
6818 | if(wr) { | |
6819 | #ifndef DESTRUCTIVE_WRITEBACK | |
6820 | regs[i].wasdirty&=wont_dirty_i|~(1<<r); | |
6821 | #endif | |
6822 | regs[i].wasdirty|=will_dirty_i&(1<<r); | |
6823 | } | |
6824 | } | |
6825 | else { | |
6826 | will_dirty_i&=~(1<<r); | |
6827 | wont_dirty_i&=~(1<<r); | |
6828 | if((regmap_pre[i][r]&63)>0 && (regmap_pre[i][r]&63)<34) { | |
6829 | will_dirty_i|=((unneeded_reg[i]>>(regmap_pre[i][r]&63))&1)<<r; | |
6830 | wont_dirty_i|=((unneeded_reg[i]>>(regmap_pre[i][r]&63))&1)<<r; | |
6831 | } else { | |
6832 | wont_dirty_i|=1<<r; | |
581335b0 | 6833 | /*printf("i: %x (%d) mismatch: %d\n",start+i*4,i,r);assert(!((will_dirty>>r)&1));*/ |
57871462 | 6834 | } |
6835 | } | |
6836 | } | |
6837 | } | |
6838 | } | |
6839 | } | |
6840 | ||
4600ba03 | 6841 | #ifdef DISASM |
57871462 | 6842 | /* disassembly */ |
6843 | void disassemble_inst(int i) | |
6844 | { | |
6845 | if (bt[i]) printf("*"); else printf(" "); | |
6846 | switch(itype[i]) { | |
6847 | case UJUMP: | |
6848 | printf (" %x: %s %8x\n",start+i*4,insn[i],ba[i]);break; | |
6849 | case CJUMP: | |
6850 | printf (" %x: %s r%d,r%d,%8x\n",start+i*4,insn[i],rs1[i],rs2[i],i?start+i*4+4+((signed int)((unsigned int)source[i]<<16)>>14):*ba);break; | |
6851 | case SJUMP: | |
6852 | printf (" %x: %s r%d,%8x\n",start+i*4,insn[i],rs1[i],start+i*4+4+((signed int)((unsigned int)source[i]<<16)>>14));break; | |
6853 | case FJUMP: | |
6854 | printf (" %x: %s %8x\n",start+i*4,insn[i],ba[i]);break; | |
6855 | case RJUMP: | |
74426039 | 6856 | if (opcode[i]==0x9&&rt1[i]!=31) |
5067f341 | 6857 | printf (" %x: %s r%d,r%d\n",start+i*4,insn[i],rt1[i],rs1[i]); |
6858 | else | |
6859 | printf (" %x: %s r%d\n",start+i*4,insn[i],rs1[i]); | |
6860 | break; | |
57871462 | 6861 | case SPAN: |
6862 | printf (" %x: %s (pagespan) r%d,r%d,%8x\n",start+i*4,insn[i],rs1[i],rs2[i],ba[i]);break; | |
6863 | case IMM16: | |
6864 | if(opcode[i]==0xf) //LUI | |
6865 | printf (" %x: %s r%d,%4x0000\n",start+i*4,insn[i],rt1[i],imm[i]&0xffff); | |
6866 | else | |
6867 | printf (" %x: %s r%d,r%d,%d\n",start+i*4,insn[i],rt1[i],rs1[i],imm[i]); | |
6868 | break; | |
6869 | case LOAD: | |
6870 | case LOADLR: | |
6871 | printf (" %x: %s r%d,r%d+%x\n",start+i*4,insn[i],rt1[i],rs1[i],imm[i]); | |
6872 | break; | |
6873 | case STORE: | |
6874 | case STORELR: | |
6875 | printf (" %x: %s r%d,r%d+%x\n",start+i*4,insn[i],rs2[i],rs1[i],imm[i]); | |
6876 | break; | |
6877 | case ALU: | |
6878 | case SHIFT: | |
6879 | printf (" %x: %s r%d,r%d,r%d\n",start+i*4,insn[i],rt1[i],rs1[i],rs2[i]); | |
6880 | break; | |
6881 | case MULTDIV: | |
6882 | printf (" %x: %s r%d,r%d\n",start+i*4,insn[i],rs1[i],rs2[i]); | |
6883 | break; | |
6884 | case SHIFTIMM: | |
6885 | printf (" %x: %s r%d,r%d,%d\n",start+i*4,insn[i],rt1[i],rs1[i],imm[i]); | |
6886 | break; | |
6887 | case MOV: | |
6888 | if((opcode2[i]&0x1d)==0x10) | |
6889 | printf (" %x: %s r%d\n",start+i*4,insn[i],rt1[i]); | |
6890 | else if((opcode2[i]&0x1d)==0x11) | |
6891 | printf (" %x: %s r%d\n",start+i*4,insn[i],rs1[i]); | |
6892 | else | |
6893 | printf (" %x: %s\n",start+i*4,insn[i]); | |
6894 | break; | |
6895 | case COP0: | |
6896 | if(opcode2[i]==0) | |
6897 | printf (" %x: %s r%d,cpr0[%d]\n",start+i*4,insn[i],rt1[i],(source[i]>>11)&0x1f); // MFC0 | |
6898 | else if(opcode2[i]==4) | |
6899 | printf (" %x: %s r%d,cpr0[%d]\n",start+i*4,insn[i],rs1[i],(source[i]>>11)&0x1f); // MTC0 | |
6900 | else printf (" %x: %s\n",start+i*4,insn[i]); | |
6901 | break; | |
6902 | case COP1: | |
6903 | if(opcode2[i]<3) | |
6904 | printf (" %x: %s r%d,cpr1[%d]\n",start+i*4,insn[i],rt1[i],(source[i]>>11)&0x1f); // MFC1 | |
6905 | else if(opcode2[i]>3) | |
6906 | printf (" %x: %s r%d,cpr1[%d]\n",start+i*4,insn[i],rs1[i],(source[i]>>11)&0x1f); // MTC1 | |
6907 | else printf (" %x: %s\n",start+i*4,insn[i]); | |
6908 | break; | |
b9b61529 | 6909 | case COP2: |
6910 | if(opcode2[i]<3) | |
6911 | printf (" %x: %s r%d,cpr2[%d]\n",start+i*4,insn[i],rt1[i],(source[i]>>11)&0x1f); // MFC2 | |
6912 | else if(opcode2[i]>3) | |
6913 | printf (" %x: %s r%d,cpr2[%d]\n",start+i*4,insn[i],rs1[i],(source[i]>>11)&0x1f); // MTC2 | |
6914 | else printf (" %x: %s\n",start+i*4,insn[i]); | |
6915 | break; | |
57871462 | 6916 | case C1LS: |
6917 | printf (" %x: %s cpr1[%d],r%d+%x\n",start+i*4,insn[i],(source[i]>>16)&0x1f,rs1[i],imm[i]); | |
6918 | break; | |
b9b61529 | 6919 | case C2LS: |
6920 | printf (" %x: %s cpr2[%d],r%d+%x\n",start+i*4,insn[i],(source[i]>>16)&0x1f,rs1[i],imm[i]); | |
6921 | break; | |
1e973cb0 | 6922 | case INTCALL: |
6923 | printf (" %x: %s (INTCALL)\n",start+i*4,insn[i]); | |
6924 | break; | |
57871462 | 6925 | default: |
6926 | //printf (" %s %8x\n",insn[i],source[i]); | |
6927 | printf (" %x: %s\n",start+i*4,insn[i]); | |
6928 | } | |
6929 | } | |
4600ba03 | 6930 | #else |
6931 | static void disassemble_inst(int i) {} | |
6932 | #endif // DISASM | |
57871462 | 6933 | |
d848b60a | 6934 | #define DRC_TEST_VAL 0x74657374 |
6935 | ||
6936 | static int new_dynarec_test(void) | |
6937 | { | |
6938 | int (*testfunc)(void) = (void *)out; | |
6939 | int ret; | |
6940 | emit_movimm(DRC_TEST_VAL,0); // test | |
6941 | emit_jmpreg(14); | |
6942 | literal_pool(0); | |
6943 | #ifdef __arm__ | |
6944 | __clear_cache((void *)testfunc, out); | |
6945 | #endif | |
6946 | SysPrintf("testing if we can run recompiled code..\n"); | |
6947 | ret = testfunc(); | |
6948 | if (ret == DRC_TEST_VAL) | |
6949 | SysPrintf("test passed.\n"); | |
6950 | else | |
6951 | SysPrintf("test failed: %08x\n", ret); | |
6952 | out=(u_char *)BASE_ADDR; | |
6953 | return ret == DRC_TEST_VAL; | |
6954 | } | |
6955 | ||
dc990066 | 6956 | // clear the state completely, instead of just marking |
6957 | // things invalid like invalidate_all_pages() does | |
6958 | void new_dynarec_clear_full() | |
57871462 | 6959 | { |
57871462 | 6960 | int n; |
35775df7 | 6961 | out=(u_char *)BASE_ADDR; |
6962 | memset(invalid_code,1,sizeof(invalid_code)); | |
6963 | memset(hash_table,0xff,sizeof(hash_table)); | |
57871462 | 6964 | memset(mini_ht,-1,sizeof(mini_ht)); |
6965 | memset(restore_candidate,0,sizeof(restore_candidate)); | |
dc990066 | 6966 | memset(shadow,0,sizeof(shadow)); |
57871462 | 6967 | copy=shadow; |
6968 | expirep=16384; // Expiry pointer, +2 blocks | |
6969 | pending_exception=0; | |
6970 | literalcount=0; | |
57871462 | 6971 | stop_after_jal=0; |
9be4ba64 | 6972 | inv_code_start=inv_code_end=~0; |
57871462 | 6973 | // TLB |
dc990066 | 6974 | for(n=0;n<4096;n++) ll_clear(jump_in+n); |
6975 | for(n=0;n<4096;n++) ll_clear(jump_out+n); | |
6976 | for(n=0;n<4096;n++) ll_clear(jump_dirty+n); | |
6977 | } | |
6978 | ||
6979 | void new_dynarec_init() | |
6980 | { | |
d848b60a | 6981 | SysPrintf("Init new dynarec\n"); |
dc990066 | 6982 | out=(u_char *)BASE_ADDR; |
a327ad27 | 6983 | #if BASE_ADDR_FIXED |
dc990066 | 6984 | if (mmap (out, 1<<TARGET_SIZE_2, |
6985 | PROT_READ | PROT_WRITE | PROT_EXEC, | |
6986 | MAP_FIXED | MAP_PRIVATE | MAP_ANONYMOUS, | |
d848b60a | 6987 | -1, 0) <= 0) { |
6988 | SysPrintf("mmap() failed: %s\n", strerror(errno)); | |
6989 | } | |
bdeade46 | 6990 | #else |
6991 | // not all systems allow execute in data segment by default | |
6992 | if (mprotect(out, 1<<TARGET_SIZE_2, PROT_READ | PROT_WRITE | PROT_EXEC) != 0) | |
d848b60a | 6993 | SysPrintf("mprotect() failed: %s\n", strerror(errno)); |
dc990066 | 6994 | #endif |
2573466a | 6995 | cycle_multiplier=200; |
dc990066 | 6996 | new_dynarec_clear_full(); |
6997 | #ifdef HOST_IMM8 | |
6998 | // Copy this into local area so we don't have to put it in every literal pool | |
6999 | invc_ptr=invalid_code; | |
7000 | #endif | |
57871462 | 7001 | arch_init(); |
d848b60a | 7002 | new_dynarec_test(); |
a327ad27 | 7003 | #ifndef RAM_FIXED |
7004 | ram_offset=(u_int)rdram-0x80000000; | |
7005 | #endif | |
b105cf4f | 7006 | if (ram_offset!=0) |
c43b5311 | 7007 | SysPrintf("warning: RAM is not directly mapped, performance will suffer\n"); |
57871462 | 7008 | } |
7009 | ||
7010 | void new_dynarec_cleanup() | |
7011 | { | |
7012 | int n; | |
a327ad27 | 7013 | #if BASE_ADDR_FIXED |
c43b5311 | 7014 | if (munmap ((void *)BASE_ADDR, 1<<TARGET_SIZE_2) < 0) {SysPrintf("munmap() failed\n");} |
bdeade46 | 7015 | #endif |
57871462 | 7016 | for(n=0;n<4096;n++) ll_clear(jump_in+n); |
7017 | for(n=0;n<4096;n++) ll_clear(jump_out+n); | |
7018 | for(n=0;n<4096;n++) ll_clear(jump_dirty+n); | |
7019 | #ifdef ROM_COPY | |
c43b5311 | 7020 | if (munmap (ROM_COPY, 67108864) < 0) {SysPrintf("munmap() failed\n");} |
57871462 | 7021 | #endif |
7022 | } | |
7023 | ||
03f55e6b | 7024 | static u_int *get_source_start(u_int addr, u_int *limit) |
57871462 | 7025 | { |
03f55e6b | 7026 | if (addr < 0x00200000 || |
7027 | (0xa0000000 <= addr && addr < 0xa0200000)) { | |
7028 | // used for BIOS calls mostly? | |
7029 | *limit = (addr&0xa0000000)|0x00200000; | |
7030 | return (u_int *)((u_int)rdram + (addr&0x1fffff)); | |
7031 | } | |
7032 | else if (!Config.HLE && ( | |
7033 | /* (0x9fc00000 <= addr && addr < 0x9fc80000) ||*/ | |
7034 | (0xbfc00000 <= addr && addr < 0xbfc80000))) { | |
7035 | // BIOS | |
7036 | *limit = (addr & 0xfff00000) | 0x80000; | |
7037 | return (u_int *)((u_int)psxR + (addr&0x7ffff)); | |
7038 | } | |
7039 | else if (addr >= 0x80000000 && addr < 0x80000000+RAM_SIZE) { | |
7040 | *limit = (addr & 0x80600000) + 0x00200000; | |
7041 | return (u_int *)((u_int)rdram + (addr&0x1fffff)); | |
7042 | } | |
581335b0 | 7043 | return NULL; |
03f55e6b | 7044 | } |
7045 | ||
7046 | static u_int scan_for_ret(u_int addr) | |
7047 | { | |
7048 | u_int limit = 0; | |
7049 | u_int *mem; | |
7050 | ||
7051 | mem = get_source_start(addr, &limit); | |
7052 | if (mem == NULL) | |
7053 | return addr; | |
7054 | ||
7055 | if (limit > addr + 0x1000) | |
7056 | limit = addr + 0x1000; | |
7057 | for (; addr < limit; addr += 4, mem++) { | |
7058 | if (*mem == 0x03e00008) // jr $ra | |
7059 | return addr + 8; | |
57871462 | 7060 | } |
581335b0 | 7061 | return addr; |
03f55e6b | 7062 | } |
7063 | ||
7064 | struct savestate_block { | |
7065 | uint32_t addr; | |
7066 | uint32_t regflags; | |
7067 | }; | |
7068 | ||
7069 | static int addr_cmp(const void *p1_, const void *p2_) | |
7070 | { | |
7071 | const struct savestate_block *p1 = p1_, *p2 = p2_; | |
7072 | return p1->addr - p2->addr; | |
7073 | } | |
7074 | ||
7075 | int new_dynarec_save_blocks(void *save, int size) | |
7076 | { | |
7077 | struct savestate_block *blocks = save; | |
7078 | int maxcount = size / sizeof(blocks[0]); | |
7079 | struct savestate_block tmp_blocks[1024]; | |
7080 | struct ll_entry *head; | |
7081 | int p, s, d, o, bcnt; | |
7082 | u_int addr; | |
7083 | ||
7084 | o = 0; | |
7085 | for (p = 0; p < sizeof(jump_in) / sizeof(jump_in[0]); p++) { | |
7086 | bcnt = 0; | |
7087 | for (head = jump_in[p]; head != NULL; head = head->next) { | |
7088 | tmp_blocks[bcnt].addr = head->vaddr; | |
7089 | tmp_blocks[bcnt].regflags = head->reg_sv_flags; | |
7090 | bcnt++; | |
7091 | } | |
7092 | if (bcnt < 1) | |
7093 | continue; | |
7094 | qsort(tmp_blocks, bcnt, sizeof(tmp_blocks[0]), addr_cmp); | |
7095 | ||
7096 | addr = tmp_blocks[0].addr; | |
7097 | for (s = d = 0; s < bcnt; s++) { | |
7098 | if (tmp_blocks[s].addr < addr) | |
7099 | continue; | |
7100 | if (d == 0 || tmp_blocks[d-1].addr != tmp_blocks[s].addr) | |
7101 | tmp_blocks[d++] = tmp_blocks[s]; | |
7102 | addr = scan_for_ret(tmp_blocks[s].addr); | |
7103 | } | |
7104 | ||
7105 | if (o + d > maxcount) | |
7106 | d = maxcount - o; | |
7107 | memcpy(&blocks[o], tmp_blocks, d * sizeof(blocks[0])); | |
7108 | o += d; | |
7109 | } | |
7110 | ||
7111 | return o * sizeof(blocks[0]); | |
7112 | } | |
7113 | ||
7114 | void new_dynarec_load_blocks(const void *save, int size) | |
7115 | { | |
7116 | const struct savestate_block *blocks = save; | |
7117 | int count = size / sizeof(blocks[0]); | |
7118 | u_int regs_save[32]; | |
7119 | uint32_t f; | |
7120 | int i, b; | |
7121 | ||
7122 | get_addr(psxRegs.pc); | |
7123 | ||
7124 | // change GPRs for speculation to at least partially work.. | |
7125 | memcpy(regs_save, &psxRegs.GPR, sizeof(regs_save)); | |
7126 | for (i = 1; i < 32; i++) | |
7127 | psxRegs.GPR.r[i] = 0x80000000; | |
7128 | ||
7129 | for (b = 0; b < count; b++) { | |
7130 | for (f = blocks[b].regflags, i = 0; f; f >>= 1, i++) { | |
7131 | if (f & 1) | |
7132 | psxRegs.GPR.r[i] = 0x1f800000; | |
7133 | } | |
7134 | ||
7135 | get_addr(blocks[b].addr); | |
7136 | ||
7137 | for (f = blocks[b].regflags, i = 0; f; f >>= 1, i++) { | |
7138 | if (f & 1) | |
7139 | psxRegs.GPR.r[i] = 0x80000000; | |
7140 | } | |
7141 | } | |
7142 | ||
7143 | memcpy(&psxRegs.GPR, regs_save, sizeof(regs_save)); | |
7144 | } | |
7145 | ||
7146 | int new_recompile_block(int addr) | |
7147 | { | |
7148 | u_int pagelimit = 0; | |
7149 | u_int state_rflags = 0; | |
7150 | int i; | |
7151 | ||
57871462 | 7152 | assem_debug("NOTCOMPILED: addr = %x -> %x\n", (int)addr, (int)out); |
7153 | //printf("NOTCOMPILED: addr = %x -> %x\n", (int)addr, (int)out); | |
7154 | //printf("TRACE: count=%d next=%d (compile %x)\n",Count,next_interupt,addr); | |
9f51b4b9 | 7155 | //if(debug) |
57871462 | 7156 | //printf("TRACE: count=%d next=%d (checksum %x)\n",Count,next_interupt,mchecksum()); |
7157 | //printf("fpu mapping=%x enabled=%x\n",(Status & 0x04000000)>>26,(Status & 0x20000000)>>29); | |
7158 | /*if(Count>=312978186) { | |
7159 | rlist(); | |
7160 | }*/ | |
7161 | //rlist(); | |
03f55e6b | 7162 | |
7163 | // this is just for speculation | |
7164 | for (i = 1; i < 32; i++) { | |
7165 | if ((psxRegs.GPR.r[i] & 0xffff0000) == 0x1f800000) | |
7166 | state_rflags |= 1 << i; | |
7167 | } | |
7168 | ||
57871462 | 7169 | start = (u_int)addr&~3; |
7170 | //assert(((u_int)addr&1)==0); | |
2f546f9a | 7171 | new_dynarec_did_compile=1; |
9ad4d757 | 7172 | if (Config.HLE && start == 0x80001000) // hlecall |
560e4a12 | 7173 | { |
7139f3c8 | 7174 | // XXX: is this enough? Maybe check hleSoftCall? |
bb5285ef | 7175 | u_int beginning=(u_int)out; |
7139f3c8 | 7176 | u_int page=get_page(start); |
7139f3c8 | 7177 | invalid_code[start>>12]=0; |
7178 | emit_movimm(start,0); | |
7179 | emit_writeword(0,(int)&pcaddr); | |
bb5285ef | 7180 | emit_jmp((int)new_dyna_leave); |
15776b68 | 7181 | literal_pool(0); |
bb5285ef | 7182 | #ifdef __arm__ |
7183 | __clear_cache((void *)beginning,out); | |
7184 | #endif | |
03f55e6b | 7185 | ll_add_flags(jump_in+page,start,state_rflags,(void *)beginning); |
7139f3c8 | 7186 | return 0; |
7187 | } | |
03f55e6b | 7188 | |
7189 | source = get_source_start(start, &pagelimit); | |
7190 | if (source == NULL) { | |
7191 | SysPrintf("Compile at bogus memory address: %08x\n", addr); | |
57871462 | 7192 | exit(1); |
7193 | } | |
7194 | ||
7195 | /* Pass 1: disassemble */ | |
7196 | /* Pass 2: register dependencies, branch targets */ | |
7197 | /* Pass 3: register allocation */ | |
7198 | /* Pass 4: branch dependencies */ | |
7199 | /* Pass 5: pre-alloc */ | |
7200 | /* Pass 6: optimize clean/dirty state */ | |
7201 | /* Pass 7: flag 32-bit registers */ | |
7202 | /* Pass 8: assembly */ | |
7203 | /* Pass 9: linker */ | |
7204 | /* Pass 10: garbage collection / free memory */ | |
7205 | ||
03f55e6b | 7206 | int j; |
57871462 | 7207 | int done=0; |
7208 | unsigned int type,op,op2; | |
7209 | ||
7210 | //printf("addr = %x source = %x %x\n", addr,source,source[0]); | |
9f51b4b9 | 7211 | |
57871462 | 7212 | /* Pass 1 disassembly */ |
7213 | ||
7214 | for(i=0;!done;i++) { | |
e1190b87 | 7215 | bt[i]=0;likely[i]=0;ooo[i]=0;op2=0; |
7216 | minimum_free_regs[i]=0; | |
57871462 | 7217 | opcode[i]=op=source[i]>>26; |
7218 | switch(op) | |
7219 | { | |
7220 | case 0x00: strcpy(insn[i],"special"); type=NI; | |
7221 | op2=source[i]&0x3f; | |
7222 | switch(op2) | |
7223 | { | |
7224 | case 0x00: strcpy(insn[i],"SLL"); type=SHIFTIMM; break; | |
7225 | case 0x02: strcpy(insn[i],"SRL"); type=SHIFTIMM; break; | |
7226 | case 0x03: strcpy(insn[i],"SRA"); type=SHIFTIMM; break; | |
7227 | case 0x04: strcpy(insn[i],"SLLV"); type=SHIFT; break; | |
7228 | case 0x06: strcpy(insn[i],"SRLV"); type=SHIFT; break; | |
7229 | case 0x07: strcpy(insn[i],"SRAV"); type=SHIFT; break; | |
7230 | case 0x08: strcpy(insn[i],"JR"); type=RJUMP; break; | |
7231 | case 0x09: strcpy(insn[i],"JALR"); type=RJUMP; break; | |
7232 | case 0x0C: strcpy(insn[i],"SYSCALL"); type=SYSCALL; break; | |
7233 | case 0x0D: strcpy(insn[i],"BREAK"); type=OTHER; break; | |
7234 | case 0x0F: strcpy(insn[i],"SYNC"); type=OTHER; break; | |
7235 | case 0x10: strcpy(insn[i],"MFHI"); type=MOV; break; | |
7236 | case 0x11: strcpy(insn[i],"MTHI"); type=MOV; break; | |
7237 | case 0x12: strcpy(insn[i],"MFLO"); type=MOV; break; | |
7238 | case 0x13: strcpy(insn[i],"MTLO"); type=MOV; break; | |
57871462 | 7239 | case 0x18: strcpy(insn[i],"MULT"); type=MULTDIV; break; |
7240 | case 0x19: strcpy(insn[i],"MULTU"); type=MULTDIV; break; | |
7241 | case 0x1A: strcpy(insn[i],"DIV"); type=MULTDIV; break; | |
7242 | case 0x1B: strcpy(insn[i],"DIVU"); type=MULTDIV; break; | |
57871462 | 7243 | case 0x20: strcpy(insn[i],"ADD"); type=ALU; break; |
7244 | case 0x21: strcpy(insn[i],"ADDU"); type=ALU; break; | |
7245 | case 0x22: strcpy(insn[i],"SUB"); type=ALU; break; | |
7246 | case 0x23: strcpy(insn[i],"SUBU"); type=ALU; break; | |
7247 | case 0x24: strcpy(insn[i],"AND"); type=ALU; break; | |
7248 | case 0x25: strcpy(insn[i],"OR"); type=ALU; break; | |
7249 | case 0x26: strcpy(insn[i],"XOR"); type=ALU; break; | |
7250 | case 0x27: strcpy(insn[i],"NOR"); type=ALU; break; | |
7251 | case 0x2A: strcpy(insn[i],"SLT"); type=ALU; break; | |
7252 | case 0x2B: strcpy(insn[i],"SLTU"); type=ALU; break; | |
57871462 | 7253 | case 0x30: strcpy(insn[i],"TGE"); type=NI; break; |
7254 | case 0x31: strcpy(insn[i],"TGEU"); type=NI; break; | |
7255 | case 0x32: strcpy(insn[i],"TLT"); type=NI; break; | |
7256 | case 0x33: strcpy(insn[i],"TLTU"); type=NI; break; | |
7257 | case 0x34: strcpy(insn[i],"TEQ"); type=NI; break; | |
7258 | case 0x36: strcpy(insn[i],"TNE"); type=NI; break; | |
71e490c5 | 7259 | #if 0 |
7f2607ea | 7260 | case 0x14: strcpy(insn[i],"DSLLV"); type=SHIFT; break; |
7261 | case 0x16: strcpy(insn[i],"DSRLV"); type=SHIFT; break; | |
7262 | case 0x17: strcpy(insn[i],"DSRAV"); type=SHIFT; break; | |
7263 | case 0x1C: strcpy(insn[i],"DMULT"); type=MULTDIV; break; | |
7264 | case 0x1D: strcpy(insn[i],"DMULTU"); type=MULTDIV; break; | |
7265 | case 0x1E: strcpy(insn[i],"DDIV"); type=MULTDIV; break; | |
7266 | case 0x1F: strcpy(insn[i],"DDIVU"); type=MULTDIV; break; | |
7267 | case 0x2C: strcpy(insn[i],"DADD"); type=ALU; break; | |
7268 | case 0x2D: strcpy(insn[i],"DADDU"); type=ALU; break; | |
7269 | case 0x2E: strcpy(insn[i],"DSUB"); type=ALU; break; | |
7270 | case 0x2F: strcpy(insn[i],"DSUBU"); type=ALU; break; | |
57871462 | 7271 | case 0x38: strcpy(insn[i],"DSLL"); type=SHIFTIMM; break; |
7272 | case 0x3A: strcpy(insn[i],"DSRL"); type=SHIFTIMM; break; | |
7273 | case 0x3B: strcpy(insn[i],"DSRA"); type=SHIFTIMM; break; | |
7274 | case 0x3C: strcpy(insn[i],"DSLL32"); type=SHIFTIMM; break; | |
7275 | case 0x3E: strcpy(insn[i],"DSRL32"); type=SHIFTIMM; break; | |
7276 | case 0x3F: strcpy(insn[i],"DSRA32"); type=SHIFTIMM; break; | |
7f2607ea | 7277 | #endif |
57871462 | 7278 | } |
7279 | break; | |
7280 | case 0x01: strcpy(insn[i],"regimm"); type=NI; | |
7281 | op2=(source[i]>>16)&0x1f; | |
7282 | switch(op2) | |
7283 | { | |
7284 | case 0x00: strcpy(insn[i],"BLTZ"); type=SJUMP; break; | |
7285 | case 0x01: strcpy(insn[i],"BGEZ"); type=SJUMP; break; | |
7286 | case 0x02: strcpy(insn[i],"BLTZL"); type=SJUMP; break; | |
7287 | case 0x03: strcpy(insn[i],"BGEZL"); type=SJUMP; break; | |
7288 | case 0x08: strcpy(insn[i],"TGEI"); type=NI; break; | |
7289 | case 0x09: strcpy(insn[i],"TGEIU"); type=NI; break; | |
7290 | case 0x0A: strcpy(insn[i],"TLTI"); type=NI; break; | |
7291 | case 0x0B: strcpy(insn[i],"TLTIU"); type=NI; break; | |
7292 | case 0x0C: strcpy(insn[i],"TEQI"); type=NI; break; | |
7293 | case 0x0E: strcpy(insn[i],"TNEI"); type=NI; break; | |
7294 | case 0x10: strcpy(insn[i],"BLTZAL"); type=SJUMP; break; | |
7295 | case 0x11: strcpy(insn[i],"BGEZAL"); type=SJUMP; break; | |
7296 | case 0x12: strcpy(insn[i],"BLTZALL"); type=SJUMP; break; | |
7297 | case 0x13: strcpy(insn[i],"BGEZALL"); type=SJUMP; break; | |
7298 | } | |
7299 | break; | |
7300 | case 0x02: strcpy(insn[i],"J"); type=UJUMP; break; | |
7301 | case 0x03: strcpy(insn[i],"JAL"); type=UJUMP; break; | |
7302 | case 0x04: strcpy(insn[i],"BEQ"); type=CJUMP; break; | |
7303 | case 0x05: strcpy(insn[i],"BNE"); type=CJUMP; break; | |
7304 | case 0x06: strcpy(insn[i],"BLEZ"); type=CJUMP; break; | |
7305 | case 0x07: strcpy(insn[i],"BGTZ"); type=CJUMP; break; | |
7306 | case 0x08: strcpy(insn[i],"ADDI"); type=IMM16; break; | |
7307 | case 0x09: strcpy(insn[i],"ADDIU"); type=IMM16; break; | |
7308 | case 0x0A: strcpy(insn[i],"SLTI"); type=IMM16; break; | |
7309 | case 0x0B: strcpy(insn[i],"SLTIU"); type=IMM16; break; | |
7310 | case 0x0C: strcpy(insn[i],"ANDI"); type=IMM16; break; | |
7311 | case 0x0D: strcpy(insn[i],"ORI"); type=IMM16; break; | |
7312 | case 0x0E: strcpy(insn[i],"XORI"); type=IMM16; break; | |
7313 | case 0x0F: strcpy(insn[i],"LUI"); type=IMM16; break; | |
7314 | case 0x10: strcpy(insn[i],"cop0"); type=NI; | |
7315 | op2=(source[i]>>21)&0x1f; | |
7316 | switch(op2) | |
7317 | { | |
7318 | case 0x00: strcpy(insn[i],"MFC0"); type=COP0; break; | |
7319 | case 0x04: strcpy(insn[i],"MTC0"); type=COP0; break; | |
7320 | case 0x10: strcpy(insn[i],"tlb"); type=NI; | |
7321 | switch(source[i]&0x3f) | |
7322 | { | |
7323 | case 0x01: strcpy(insn[i],"TLBR"); type=COP0; break; | |
7324 | case 0x02: strcpy(insn[i],"TLBWI"); type=COP0; break; | |
7325 | case 0x06: strcpy(insn[i],"TLBWR"); type=COP0; break; | |
7326 | case 0x08: strcpy(insn[i],"TLBP"); type=COP0; break; | |
576bbd8f | 7327 | case 0x10: strcpy(insn[i],"RFE"); type=COP0; break; |
71e490c5 | 7328 | //case 0x18: strcpy(insn[i],"ERET"); type=COP0; break; |
57871462 | 7329 | } |
7330 | } | |
7331 | break; | |
7332 | case 0x11: strcpy(insn[i],"cop1"); type=NI; | |
7333 | op2=(source[i]>>21)&0x1f; | |
7334 | switch(op2) | |
7335 | { | |
7336 | case 0x00: strcpy(insn[i],"MFC1"); type=COP1; break; | |
7337 | case 0x01: strcpy(insn[i],"DMFC1"); type=COP1; break; | |
7338 | case 0x02: strcpy(insn[i],"CFC1"); type=COP1; break; | |
7339 | case 0x04: strcpy(insn[i],"MTC1"); type=COP1; break; | |
7340 | case 0x05: strcpy(insn[i],"DMTC1"); type=COP1; break; | |
7341 | case 0x06: strcpy(insn[i],"CTC1"); type=COP1; break; | |
7342 | case 0x08: strcpy(insn[i],"BC1"); type=FJUMP; | |
7343 | switch((source[i]>>16)&0x3) | |
7344 | { | |
7345 | case 0x00: strcpy(insn[i],"BC1F"); break; | |
7346 | case 0x01: strcpy(insn[i],"BC1T"); break; | |
7347 | case 0x02: strcpy(insn[i],"BC1FL"); break; | |
7348 | case 0x03: strcpy(insn[i],"BC1TL"); break; | |
7349 | } | |
7350 | break; | |
7351 | case 0x10: strcpy(insn[i],"C1.S"); type=NI; | |
7352 | switch(source[i]&0x3f) | |
7353 | { | |
7354 | case 0x00: strcpy(insn[i],"ADD.S"); type=FLOAT; break; | |
7355 | case 0x01: strcpy(insn[i],"SUB.S"); type=FLOAT; break; | |
7356 | case 0x02: strcpy(insn[i],"MUL.S"); type=FLOAT; break; | |
7357 | case 0x03: strcpy(insn[i],"DIV.S"); type=FLOAT; break; | |
7358 | case 0x04: strcpy(insn[i],"SQRT.S"); type=FLOAT; break; | |
7359 | case 0x05: strcpy(insn[i],"ABS.S"); type=FLOAT; break; | |
7360 | case 0x06: strcpy(insn[i],"MOV.S"); type=FLOAT; break; | |
7361 | case 0x07: strcpy(insn[i],"NEG.S"); type=FLOAT; break; | |
7362 | case 0x08: strcpy(insn[i],"ROUND.L.S"); type=FCONV; break; | |
7363 | case 0x09: strcpy(insn[i],"TRUNC.L.S"); type=FCONV; break; | |
7364 | case 0x0A: strcpy(insn[i],"CEIL.L.S"); type=FCONV; break; | |
7365 | case 0x0B: strcpy(insn[i],"FLOOR.L.S"); type=FCONV; break; | |
7366 | case 0x0C: strcpy(insn[i],"ROUND.W.S"); type=FCONV; break; | |
7367 | case 0x0D: strcpy(insn[i],"TRUNC.W.S"); type=FCONV; break; | |
7368 | case 0x0E: strcpy(insn[i],"CEIL.W.S"); type=FCONV; break; | |
7369 | case 0x0F: strcpy(insn[i],"FLOOR.W.S"); type=FCONV; break; | |
7370 | case 0x21: strcpy(insn[i],"CVT.D.S"); type=FCONV; break; | |
7371 | case 0x24: strcpy(insn[i],"CVT.W.S"); type=FCONV; break; | |
7372 | case 0x25: strcpy(insn[i],"CVT.L.S"); type=FCONV; break; | |
7373 | case 0x30: strcpy(insn[i],"C.F.S"); type=FCOMP; break; | |
7374 | case 0x31: strcpy(insn[i],"C.UN.S"); type=FCOMP; break; | |
7375 | case 0x32: strcpy(insn[i],"C.EQ.S"); type=FCOMP; break; | |
7376 | case 0x33: strcpy(insn[i],"C.UEQ.S"); type=FCOMP; break; | |
7377 | case 0x34: strcpy(insn[i],"C.OLT.S"); type=FCOMP; break; | |
7378 | case 0x35: strcpy(insn[i],"C.ULT.S"); type=FCOMP; break; | |
7379 | case 0x36: strcpy(insn[i],"C.OLE.S"); type=FCOMP; break; | |
7380 | case 0x37: strcpy(insn[i],"C.ULE.S"); type=FCOMP; break; | |
7381 | case 0x38: strcpy(insn[i],"C.SF.S"); type=FCOMP; break; | |
7382 | case 0x39: strcpy(insn[i],"C.NGLE.S"); type=FCOMP; break; | |
7383 | case 0x3A: strcpy(insn[i],"C.SEQ.S"); type=FCOMP; break; | |
7384 | case 0x3B: strcpy(insn[i],"C.NGL.S"); type=FCOMP; break; | |
7385 | case 0x3C: strcpy(insn[i],"C.LT.S"); type=FCOMP; break; | |
7386 | case 0x3D: strcpy(insn[i],"C.NGE.S"); type=FCOMP; break; | |
7387 | case 0x3E: strcpy(insn[i],"C.LE.S"); type=FCOMP; break; | |
7388 | case 0x3F: strcpy(insn[i],"C.NGT.S"); type=FCOMP; break; | |
7389 | } | |
7390 | break; | |
7391 | case 0x11: strcpy(insn[i],"C1.D"); type=NI; | |
7392 | switch(source[i]&0x3f) | |
7393 | { | |
7394 | case 0x00: strcpy(insn[i],"ADD.D"); type=FLOAT; break; | |
7395 | case 0x01: strcpy(insn[i],"SUB.D"); type=FLOAT; break; | |
7396 | case 0x02: strcpy(insn[i],"MUL.D"); type=FLOAT; break; | |
7397 | case 0x03: strcpy(insn[i],"DIV.D"); type=FLOAT; break; | |
7398 | case 0x04: strcpy(insn[i],"SQRT.D"); type=FLOAT; break; | |
7399 | case 0x05: strcpy(insn[i],"ABS.D"); type=FLOAT; break; | |
7400 | case 0x06: strcpy(insn[i],"MOV.D"); type=FLOAT; break; | |
7401 | case 0x07: strcpy(insn[i],"NEG.D"); type=FLOAT; break; | |
7402 | case 0x08: strcpy(insn[i],"ROUND.L.D"); type=FCONV; break; | |
7403 | case 0x09: strcpy(insn[i],"TRUNC.L.D"); type=FCONV; break; | |
7404 | case 0x0A: strcpy(insn[i],"CEIL.L.D"); type=FCONV; break; | |
7405 | case 0x0B: strcpy(insn[i],"FLOOR.L.D"); type=FCONV; break; | |
7406 | case 0x0C: strcpy(insn[i],"ROUND.W.D"); type=FCONV; break; | |
7407 | case 0x0D: strcpy(insn[i],"TRUNC.W.D"); type=FCONV; break; | |
7408 | case 0x0E: strcpy(insn[i],"CEIL.W.D"); type=FCONV; break; | |
7409 | case 0x0F: strcpy(insn[i],"FLOOR.W.D"); type=FCONV; break; | |
7410 | case 0x20: strcpy(insn[i],"CVT.S.D"); type=FCONV; break; | |
7411 | case 0x24: strcpy(insn[i],"CVT.W.D"); type=FCONV; break; | |
7412 | case 0x25: strcpy(insn[i],"CVT.L.D"); type=FCONV; break; | |
7413 | case 0x30: strcpy(insn[i],"C.F.D"); type=FCOMP; break; | |
7414 | case 0x31: strcpy(insn[i],"C.UN.D"); type=FCOMP; break; | |
7415 | case 0x32: strcpy(insn[i],"C.EQ.D"); type=FCOMP; break; | |
7416 | case 0x33: strcpy(insn[i],"C.UEQ.D"); type=FCOMP; break; | |
7417 | case 0x34: strcpy(insn[i],"C.OLT.D"); type=FCOMP; break; | |
7418 | case 0x35: strcpy(insn[i],"C.ULT.D"); type=FCOMP; break; | |
7419 | case 0x36: strcpy(insn[i],"C.OLE.D"); type=FCOMP; break; | |
7420 | case 0x37: strcpy(insn[i],"C.ULE.D"); type=FCOMP; break; | |
7421 | case 0x38: strcpy(insn[i],"C.SF.D"); type=FCOMP; break; | |
7422 | case 0x39: strcpy(insn[i],"C.NGLE.D"); type=FCOMP; break; | |
7423 | case 0x3A: strcpy(insn[i],"C.SEQ.D"); type=FCOMP; break; | |
7424 | case 0x3B: strcpy(insn[i],"C.NGL.D"); type=FCOMP; break; | |
7425 | case 0x3C: strcpy(insn[i],"C.LT.D"); type=FCOMP; break; | |
7426 | case 0x3D: strcpy(insn[i],"C.NGE.D"); type=FCOMP; break; | |
7427 | case 0x3E: strcpy(insn[i],"C.LE.D"); type=FCOMP; break; | |
7428 | case 0x3F: strcpy(insn[i],"C.NGT.D"); type=FCOMP; break; | |
7429 | } | |
7430 | break; | |
7431 | case 0x14: strcpy(insn[i],"C1.W"); type=NI; | |
7432 | switch(source[i]&0x3f) | |
7433 | { | |
7434 | case 0x20: strcpy(insn[i],"CVT.S.W"); type=FCONV; break; | |
7435 | case 0x21: strcpy(insn[i],"CVT.D.W"); type=FCONV; break; | |
7436 | } | |
7437 | break; | |
7438 | case 0x15: strcpy(insn[i],"C1.L"); type=NI; | |
7439 | switch(source[i]&0x3f) | |
7440 | { | |
7441 | case 0x20: strcpy(insn[i],"CVT.S.L"); type=FCONV; break; | |
7442 | case 0x21: strcpy(insn[i],"CVT.D.L"); type=FCONV; break; | |
7443 | } | |
7444 | break; | |
7445 | } | |
7446 | break; | |
71e490c5 | 7447 | #if 0 |
57871462 | 7448 | case 0x14: strcpy(insn[i],"BEQL"); type=CJUMP; break; |
7449 | case 0x15: strcpy(insn[i],"BNEL"); type=CJUMP; break; | |
7450 | case 0x16: strcpy(insn[i],"BLEZL"); type=CJUMP; break; | |
7451 | case 0x17: strcpy(insn[i],"BGTZL"); type=CJUMP; break; | |
7452 | case 0x18: strcpy(insn[i],"DADDI"); type=IMM16; break; | |
7453 | case 0x19: strcpy(insn[i],"DADDIU"); type=IMM16; break; | |
7454 | case 0x1A: strcpy(insn[i],"LDL"); type=LOADLR; break; | |
7455 | case 0x1B: strcpy(insn[i],"LDR"); type=LOADLR; break; | |
996cc15d | 7456 | #endif |
57871462 | 7457 | case 0x20: strcpy(insn[i],"LB"); type=LOAD; break; |
7458 | case 0x21: strcpy(insn[i],"LH"); type=LOAD; break; | |
7459 | case 0x22: strcpy(insn[i],"LWL"); type=LOADLR; break; | |
7460 | case 0x23: strcpy(insn[i],"LW"); type=LOAD; break; | |
7461 | case 0x24: strcpy(insn[i],"LBU"); type=LOAD; break; | |
7462 | case 0x25: strcpy(insn[i],"LHU"); type=LOAD; break; | |
7463 | case 0x26: strcpy(insn[i],"LWR"); type=LOADLR; break; | |
71e490c5 | 7464 | #if 0 |
57871462 | 7465 | case 0x27: strcpy(insn[i],"LWU"); type=LOAD; break; |
64bd6f82 | 7466 | #endif |
57871462 | 7467 | case 0x28: strcpy(insn[i],"SB"); type=STORE; break; |
7468 | case 0x29: strcpy(insn[i],"SH"); type=STORE; break; | |
7469 | case 0x2A: strcpy(insn[i],"SWL"); type=STORELR; break; | |
7470 | case 0x2B: strcpy(insn[i],"SW"); type=STORE; break; | |
71e490c5 | 7471 | #if 0 |
57871462 | 7472 | case 0x2C: strcpy(insn[i],"SDL"); type=STORELR; break; |
7473 | case 0x2D: strcpy(insn[i],"SDR"); type=STORELR; break; | |
996cc15d | 7474 | #endif |
57871462 | 7475 | case 0x2E: strcpy(insn[i],"SWR"); type=STORELR; break; |
7476 | case 0x2F: strcpy(insn[i],"CACHE"); type=NOP; break; | |
7477 | case 0x30: strcpy(insn[i],"LL"); type=NI; break; | |
7478 | case 0x31: strcpy(insn[i],"LWC1"); type=C1LS; break; | |
71e490c5 | 7479 | #if 0 |
57871462 | 7480 | case 0x34: strcpy(insn[i],"LLD"); type=NI; break; |
7481 | case 0x35: strcpy(insn[i],"LDC1"); type=C1LS; break; | |
7482 | case 0x37: strcpy(insn[i],"LD"); type=LOAD; break; | |
996cc15d | 7483 | #endif |
57871462 | 7484 | case 0x38: strcpy(insn[i],"SC"); type=NI; break; |
7485 | case 0x39: strcpy(insn[i],"SWC1"); type=C1LS; break; | |
71e490c5 | 7486 | #if 0 |
57871462 | 7487 | case 0x3C: strcpy(insn[i],"SCD"); type=NI; break; |
7488 | case 0x3D: strcpy(insn[i],"SDC1"); type=C1LS; break; | |
7489 | case 0x3F: strcpy(insn[i],"SD"); type=STORE; break; | |
996cc15d | 7490 | #endif |
b9b61529 | 7491 | case 0x12: strcpy(insn[i],"COP2"); type=NI; |
7492 | op2=(source[i]>>21)&0x1f; | |
bedfea38 | 7493 | //if (op2 & 0x10) { |
7494 | if (source[i]&0x3f) { // use this hack to support old savestates with patched gte insns | |
c7abc864 | 7495 | if (gte_handlers[source[i]&0x3f]!=NULL) { |
bedfea38 | 7496 | if (gte_regnames[source[i]&0x3f]!=NULL) |
7497 | strcpy(insn[i],gte_regnames[source[i]&0x3f]); | |
7498 | else | |
7499 | snprintf(insn[i], sizeof(insn[i]), "COP2 %x", source[i]&0x3f); | |
c7abc864 | 7500 | type=C2OP; |
7501 | } | |
7502 | } | |
7503 | else switch(op2) | |
b9b61529 | 7504 | { |
7505 | case 0x00: strcpy(insn[i],"MFC2"); type=COP2; break; | |
7506 | case 0x02: strcpy(insn[i],"CFC2"); type=COP2; break; | |
7507 | case 0x04: strcpy(insn[i],"MTC2"); type=COP2; break; | |
7508 | case 0x06: strcpy(insn[i],"CTC2"); type=COP2; break; | |
b9b61529 | 7509 | } |
7510 | break; | |
7511 | case 0x32: strcpy(insn[i],"LWC2"); type=C2LS; break; | |
7512 | case 0x3A: strcpy(insn[i],"SWC2"); type=C2LS; break; | |
7513 | case 0x3B: strcpy(insn[i],"HLECALL"); type=HLECALL; break; | |
90ae6d4e | 7514 | default: strcpy(insn[i],"???"); type=NI; |
c43b5311 | 7515 | SysPrintf("NI %08x @%08x (%08x)\n", source[i], addr + i*4, addr); |
90ae6d4e | 7516 | break; |
57871462 | 7517 | } |
7518 | itype[i]=type; | |
7519 | opcode2[i]=op2; | |
7520 | /* Get registers/immediates */ | |
7521 | lt1[i]=0; | |
7522 | us1[i]=0; | |
7523 | us2[i]=0; | |
7524 | dep1[i]=0; | |
7525 | dep2[i]=0; | |
bedfea38 | 7526 | gte_rs[i]=gte_rt[i]=0; |
57871462 | 7527 | switch(type) { |
7528 | case LOAD: | |
7529 | rs1[i]=(source[i]>>21)&0x1f; | |
7530 | rs2[i]=0; | |
7531 | rt1[i]=(source[i]>>16)&0x1f; | |
7532 | rt2[i]=0; | |
7533 | imm[i]=(short)source[i]; | |
7534 | break; | |
7535 | case STORE: | |
7536 | case STORELR: | |
7537 | rs1[i]=(source[i]>>21)&0x1f; | |
7538 | rs2[i]=(source[i]>>16)&0x1f; | |
7539 | rt1[i]=0; | |
7540 | rt2[i]=0; | |
7541 | imm[i]=(short)source[i]; | |
7542 | if(op==0x2c||op==0x2d||op==0x3f) us1[i]=rs2[i]; // 64-bit SDL/SDR/SD | |
7543 | break; | |
7544 | case LOADLR: | |
7545 | // LWL/LWR only load part of the register, | |
7546 | // therefore the target register must be treated as a source too | |
7547 | rs1[i]=(source[i]>>21)&0x1f; | |
7548 | rs2[i]=(source[i]>>16)&0x1f; | |
7549 | rt1[i]=(source[i]>>16)&0x1f; | |
7550 | rt2[i]=0; | |
7551 | imm[i]=(short)source[i]; | |
7552 | if(op==0x1a||op==0x1b) us1[i]=rs2[i]; // LDR/LDL | |
7553 | if(op==0x26) dep1[i]=rt1[i]; // LWR | |
7554 | break; | |
7555 | case IMM16: | |
7556 | if (op==0x0f) rs1[i]=0; // LUI instruction has no source register | |
7557 | else rs1[i]=(source[i]>>21)&0x1f; | |
7558 | rs2[i]=0; | |
7559 | rt1[i]=(source[i]>>16)&0x1f; | |
7560 | rt2[i]=0; | |
7561 | if(op>=0x0c&&op<=0x0e) { // ANDI/ORI/XORI | |
7562 | imm[i]=(unsigned short)source[i]; | |
7563 | }else{ | |
7564 | imm[i]=(short)source[i]; | |
7565 | } | |
7566 | if(op==0x18||op==0x19) us1[i]=rs1[i]; // DADDI/DADDIU | |
7567 | if(op==0x0a||op==0x0b) us1[i]=rs1[i]; // SLTI/SLTIU | |
7568 | if(op==0x0d||op==0x0e) dep1[i]=rs1[i]; // ORI/XORI | |
7569 | break; | |
7570 | case UJUMP: | |
7571 | rs1[i]=0; | |
7572 | rs2[i]=0; | |
7573 | rt1[i]=0; | |
7574 | rt2[i]=0; | |
7575 | // The JAL instruction writes to r31. | |
7576 | if (op&1) { | |
7577 | rt1[i]=31; | |
7578 | } | |
7579 | rs2[i]=CCREG; | |
7580 | break; | |
7581 | case RJUMP: | |
7582 | rs1[i]=(source[i]>>21)&0x1f; | |
7583 | rs2[i]=0; | |
7584 | rt1[i]=0; | |
7585 | rt2[i]=0; | |
5067f341 | 7586 | // The JALR instruction writes to rd. |
57871462 | 7587 | if (op2&1) { |
5067f341 | 7588 | rt1[i]=(source[i]>>11)&0x1f; |
57871462 | 7589 | } |
7590 | rs2[i]=CCREG; | |
7591 | break; | |
7592 | case CJUMP: | |
7593 | rs1[i]=(source[i]>>21)&0x1f; | |
7594 | rs2[i]=(source[i]>>16)&0x1f; | |
7595 | rt1[i]=0; | |
7596 | rt2[i]=0; | |
7597 | if(op&2) { // BGTZ/BLEZ | |
7598 | rs2[i]=0; | |
7599 | } | |
7600 | us1[i]=rs1[i]; | |
7601 | us2[i]=rs2[i]; | |
7602 | likely[i]=op>>4; | |
7603 | break; | |
7604 | case SJUMP: | |
7605 | rs1[i]=(source[i]>>21)&0x1f; | |
7606 | rs2[i]=CCREG; | |
7607 | rt1[i]=0; | |
7608 | rt2[i]=0; | |
7609 | us1[i]=rs1[i]; | |
7610 | if(op2&0x10) { // BxxAL | |
7611 | rt1[i]=31; | |
7612 | // NOTE: If the branch is not taken, r31 is still overwritten | |
7613 | } | |
7614 | likely[i]=(op2&2)>>1; | |
7615 | break; | |
7616 | case FJUMP: | |
7617 | rs1[i]=FSREG; | |
7618 | rs2[i]=CSREG; | |
7619 | rt1[i]=0; | |
7620 | rt2[i]=0; | |
7621 | likely[i]=((source[i])>>17)&1; | |
7622 | break; | |
7623 | case ALU: | |
7624 | rs1[i]=(source[i]>>21)&0x1f; // source | |
7625 | rs2[i]=(source[i]>>16)&0x1f; // subtract amount | |
7626 | rt1[i]=(source[i]>>11)&0x1f; // destination | |
7627 | rt2[i]=0; | |
7628 | if(op2==0x2a||op2==0x2b) { // SLT/SLTU | |
7629 | us1[i]=rs1[i];us2[i]=rs2[i]; | |
7630 | } | |
7631 | else if(op2>=0x24&&op2<=0x27) { // AND/OR/XOR/NOR | |
7632 | dep1[i]=rs1[i];dep2[i]=rs2[i]; | |
7633 | } | |
7634 | else if(op2>=0x2c&&op2<=0x2f) { // DADD/DSUB | |
7635 | dep1[i]=rs1[i];dep2[i]=rs2[i]; | |
7636 | } | |
7637 | break; | |
7638 | case MULTDIV: | |
7639 | rs1[i]=(source[i]>>21)&0x1f; // source | |
7640 | rs2[i]=(source[i]>>16)&0x1f; // divisor | |
7641 | rt1[i]=HIREG; | |
7642 | rt2[i]=LOREG; | |
7643 | if (op2>=0x1c&&op2<=0x1f) { // DMULT/DMULTU/DDIV/DDIVU | |
7644 | us1[i]=rs1[i];us2[i]=rs2[i]; | |
7645 | } | |
7646 | break; | |
7647 | case MOV: | |
7648 | rs1[i]=0; | |
7649 | rs2[i]=0; | |
7650 | rt1[i]=0; | |
7651 | rt2[i]=0; | |
7652 | if(op2==0x10) rs1[i]=HIREG; // MFHI | |
7653 | if(op2==0x11) rt1[i]=HIREG; // MTHI | |
7654 | if(op2==0x12) rs1[i]=LOREG; // MFLO | |
7655 | if(op2==0x13) rt1[i]=LOREG; // MTLO | |
7656 | if((op2&0x1d)==0x10) rt1[i]=(source[i]>>11)&0x1f; // MFxx | |
7657 | if((op2&0x1d)==0x11) rs1[i]=(source[i]>>21)&0x1f; // MTxx | |
7658 | dep1[i]=rs1[i]; | |
7659 | break; | |
7660 | case SHIFT: | |
7661 | rs1[i]=(source[i]>>16)&0x1f; // target of shift | |
7662 | rs2[i]=(source[i]>>21)&0x1f; // shift amount | |
7663 | rt1[i]=(source[i]>>11)&0x1f; // destination | |
7664 | rt2[i]=0; | |
7665 | // DSLLV/DSRLV/DSRAV are 64-bit | |
7666 | if(op2>=0x14&&op2<=0x17) us1[i]=rs1[i]; | |
7667 | break; | |
7668 | case SHIFTIMM: | |
7669 | rs1[i]=(source[i]>>16)&0x1f; | |
7670 | rs2[i]=0; | |
7671 | rt1[i]=(source[i]>>11)&0x1f; | |
7672 | rt2[i]=0; | |
7673 | imm[i]=(source[i]>>6)&0x1f; | |
7674 | // DSxx32 instructions | |
7675 | if(op2>=0x3c) imm[i]|=0x20; | |
7676 | // DSLL/DSRL/DSRA/DSRA32/DSRL32 but not DSLL32 require 64-bit source | |
7677 | if(op2>=0x38&&op2!=0x3c) us1[i]=rs1[i]; | |
7678 | break; | |
7679 | case COP0: | |
7680 | rs1[i]=0; | |
7681 | rs2[i]=0; | |
7682 | rt1[i]=0; | |
7683 | rt2[i]=0; | |
7684 | if(op2==0) rt1[i]=(source[i]>>16)&0x1F; // MFC0 | |
7685 | if(op2==4) rs1[i]=(source[i]>>16)&0x1F; // MTC0 | |
7686 | if(op2==4&&((source[i]>>11)&0x1f)==12) rt2[i]=CSREG; // Status | |
7687 | if(op2==16) if((source[i]&0x3f)==0x18) rs2[i]=CCREG; // ERET | |
7688 | break; | |
7689 | case COP1: | |
7690 | rs1[i]=0; | |
7691 | rs2[i]=0; | |
7692 | rt1[i]=0; | |
7693 | rt2[i]=0; | |
7694 | if(op2<3) rt1[i]=(source[i]>>16)&0x1F; // MFC1/DMFC1/CFC1 | |
7695 | if(op2>3) rs1[i]=(source[i]>>16)&0x1F; // MTC1/DMTC1/CTC1 | |
7696 | if(op2==5) us1[i]=rs1[i]; // DMTC1 | |
7697 | rs2[i]=CSREG; | |
7698 | break; | |
bedfea38 | 7699 | case COP2: |
7700 | rs1[i]=0; | |
7701 | rs2[i]=0; | |
7702 | rt1[i]=0; | |
7703 | rt2[i]=0; | |
7704 | if(op2<3) rt1[i]=(source[i]>>16)&0x1F; // MFC2/CFC2 | |
7705 | if(op2>3) rs1[i]=(source[i]>>16)&0x1F; // MTC2/CTC2 | |
7706 | rs2[i]=CSREG; | |
7707 | int gr=(source[i]>>11)&0x1F; | |
7708 | switch(op2) | |
7709 | { | |
7710 | case 0x00: gte_rs[i]=1ll<<gr; break; // MFC2 | |
7711 | case 0x04: gte_rt[i]=1ll<<gr; break; // MTC2 | |
0ff8c62c | 7712 | case 0x02: gte_rs[i]=1ll<<(gr+32); break; // CFC2 |
bedfea38 | 7713 | case 0x06: gte_rt[i]=1ll<<(gr+32); break; // CTC2 |
7714 | } | |
7715 | break; | |
57871462 | 7716 | case C1LS: |
7717 | rs1[i]=(source[i]>>21)&0x1F; | |
7718 | rs2[i]=CSREG; | |
7719 | rt1[i]=0; | |
7720 | rt2[i]=0; | |
7721 | imm[i]=(short)source[i]; | |
7722 | break; | |
b9b61529 | 7723 | case C2LS: |
7724 | rs1[i]=(source[i]>>21)&0x1F; | |
7725 | rs2[i]=0; | |
7726 | rt1[i]=0; | |
7727 | rt2[i]=0; | |
7728 | imm[i]=(short)source[i]; | |
bedfea38 | 7729 | if(op==0x32) gte_rt[i]=1ll<<((source[i]>>16)&0x1F); // LWC2 |
7730 | else gte_rs[i]=1ll<<((source[i]>>16)&0x1F); // SWC2 | |
7731 | break; | |
7732 | case C2OP: | |
7733 | rs1[i]=0; | |
7734 | rs2[i]=0; | |
7735 | rt1[i]=0; | |
7736 | rt2[i]=0; | |
2167bef6 | 7737 | gte_rs[i]=gte_reg_reads[source[i]&0x3f]; |
7738 | gte_rt[i]=gte_reg_writes[source[i]&0x3f]; | |
7739 | gte_rt[i]|=1ll<<63; // every op changes flags | |
587a5b1c | 7740 | if((source[i]&0x3f)==GTE_MVMVA) { |
7741 | int v = (source[i] >> 15) & 3; | |
7742 | gte_rs[i]&=~0xe3fll; | |
7743 | if(v==3) gte_rs[i]|=0xe00ll; | |
7744 | else gte_rs[i]|=3ll<<(v*2); | |
7745 | } | |
b9b61529 | 7746 | break; |
57871462 | 7747 | case FLOAT: |
7748 | case FCONV: | |
7749 | rs1[i]=0; | |
7750 | rs2[i]=CSREG; | |
7751 | rt1[i]=0; | |
7752 | rt2[i]=0; | |
7753 | break; | |
7754 | case FCOMP: | |
7755 | rs1[i]=FSREG; | |
7756 | rs2[i]=CSREG; | |
7757 | rt1[i]=FSREG; | |
7758 | rt2[i]=0; | |
7759 | break; | |
7760 | case SYSCALL: | |
7139f3c8 | 7761 | case HLECALL: |
1e973cb0 | 7762 | case INTCALL: |
57871462 | 7763 | rs1[i]=CCREG; |
7764 | rs2[i]=0; | |
7765 | rt1[i]=0; | |
7766 | rt2[i]=0; | |
7767 | break; | |
7768 | default: | |
7769 | rs1[i]=0; | |
7770 | rs2[i]=0; | |
7771 | rt1[i]=0; | |
7772 | rt2[i]=0; | |
7773 | } | |
7774 | /* Calculate branch target addresses */ | |
7775 | if(type==UJUMP) | |
7776 | ba[i]=((start+i*4+4)&0xF0000000)|(((unsigned int)source[i]<<6)>>4); | |
7777 | else if(type==CJUMP&&rs1[i]==rs2[i]&&(op&1)) | |
7778 | ba[i]=start+i*4+8; // Ignore never taken branch | |
7779 | else if(type==SJUMP&&rs1[i]==0&&!(op2&1)) | |
7780 | ba[i]=start+i*4+8; // Ignore never taken branch | |
7781 | else if(type==CJUMP||type==SJUMP||type==FJUMP) | |
7782 | ba[i]=start+i*4+4+((signed int)((unsigned int)source[i]<<16)>>14); | |
7783 | else ba[i]=-1; | |
3e535354 | 7784 | if(i>0&&(itype[i-1]==RJUMP||itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP)) { |
7785 | int do_in_intrp=0; | |
7786 | // branch in delay slot? | |
7787 | if(type==RJUMP||type==UJUMP||type==CJUMP||type==SJUMP||type==FJUMP) { | |
7788 | // don't handle first branch and call interpreter if it's hit | |
c43b5311 | 7789 | SysPrintf("branch in delay slot @%08x (%08x)\n", addr + i*4, addr); |
3e535354 | 7790 | do_in_intrp=1; |
7791 | } | |
7792 | // basic load delay detection | |
7793 | else if((type==LOAD||type==LOADLR||type==COP0||type==COP2||type==C2LS)&&rt1[i]!=0) { | |
7794 | int t=(ba[i-1]-start)/4; | |
7795 | if(0 <= t && t < i &&(rt1[i]==rs1[t]||rt1[i]==rs2[t])&&itype[t]!=CJUMP&&itype[t]!=SJUMP) { | |
7796 | // jump target wants DS result - potential load delay effect | |
c43b5311 | 7797 | SysPrintf("load delay @%08x (%08x)\n", addr + i*4, addr); |
3e535354 | 7798 | do_in_intrp=1; |
7799 | bt[t+1]=1; // expected return from interpreter | |
7800 | } | |
7801 | else if(i>=2&&rt1[i-2]==2&&rt1[i]==2&&rs1[i]!=2&&rs2[i]!=2&&rs1[i-1]!=2&&rs2[i-1]!=2&& | |
7802 | !(i>=3&&(itype[i-3]==RJUMP||itype[i-3]==UJUMP||itype[i-3]==CJUMP||itype[i-3]==SJUMP))) { | |
7803 | // v0 overwrite like this is a sign of trouble, bail out | |
c43b5311 | 7804 | SysPrintf("v0 overwrite @%08x (%08x)\n", addr + i*4, addr); |
3e535354 | 7805 | do_in_intrp=1; |
7806 | } | |
7807 | } | |
3e535354 | 7808 | if(do_in_intrp) { |
7809 | rs1[i-1]=CCREG; | |
7810 | rs2[i-1]=rt1[i-1]=rt2[i-1]=0; | |
26869094 | 7811 | ba[i-1]=-1; |
7812 | itype[i-1]=INTCALL; | |
7813 | done=2; | |
3e535354 | 7814 | i--; // don't compile the DS |
26869094 | 7815 | } |
3e535354 | 7816 | } |
3e535354 | 7817 | /* Is this the end of the block? */ |
7818 | if(i>0&&(itype[i-1]==UJUMP||itype[i-1]==RJUMP||(source[i-1]>>16)==0x1000)) { | |
5067f341 | 7819 | if(rt1[i-1]==0) { // Continue past subroutine call (JAL) |
1e973cb0 | 7820 | done=2; |
57871462 | 7821 | } |
7822 | else { | |
7823 | if(stop_after_jal) done=1; | |
7824 | // Stop on BREAK | |
7825 | if((source[i+1]&0xfc00003f)==0x0d) done=1; | |
7826 | } | |
7827 | // Don't recompile stuff that's already compiled | |
7828 | if(check_addr(start+i*4+4)) done=1; | |
7829 | // Don't get too close to the limit | |
7830 | if(i>MAXBLOCK/2) done=1; | |
7831 | } | |
75dec299 | 7832 | if(itype[i]==SYSCALL&&stop_after_jal) done=1; |
1e973cb0 | 7833 | if(itype[i]==HLECALL||itype[i]==INTCALL) done=2; |
7834 | if(done==2) { | |
7835 | // Does the block continue due to a branch? | |
7836 | for(j=i-1;j>=0;j--) | |
7837 | { | |
2a706964 | 7838 | if(ba[j]==start+i*4) done=j=0; // Branch into delay slot |
1e973cb0 | 7839 | if(ba[j]==start+i*4+4) done=j=0; |
7840 | if(ba[j]==start+i*4+8) done=j=0; | |
7841 | } | |
7842 | } | |
75dec299 | 7843 | //assert(i<MAXBLOCK-1); |
57871462 | 7844 | if(start+i*4==pagelimit-4) done=1; |
7845 | assert(start+i*4<pagelimit); | |
7846 | if (i==MAXBLOCK-1) done=1; | |
7847 | // Stop if we're compiling junk | |
7848 | if(itype[i]==NI&&opcode[i]==0x11) { | |
7849 | done=stop_after_jal=1; | |
c43b5311 | 7850 | SysPrintf("Disabled speculative precompilation\n"); |
57871462 | 7851 | } |
7852 | } | |
7853 | slen=i; | |
7854 | if(itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==RJUMP||itype[i-1]==FJUMP) { | |
7855 | if(start+i*4==pagelimit) { | |
7856 | itype[i-1]=SPAN; | |
7857 | } | |
7858 | } | |
7859 | assert(slen>0); | |
7860 | ||
7861 | /* Pass 2 - Register dependencies and branch targets */ | |
7862 | ||
7863 | unneeded_registers(0,slen-1,0); | |
9f51b4b9 | 7864 | |
57871462 | 7865 | /* Pass 3 - Register allocation */ |
7866 | ||
7867 | struct regstat current; // Current register allocations/status | |
7868 | current.is32=1; | |
7869 | current.dirty=0; | |
7870 | current.u=unneeded_reg[0]; | |
7871 | current.uu=unneeded_reg_upper[0]; | |
7872 | clear_all_regs(current.regmap); | |
7873 | alloc_reg(¤t,0,CCREG); | |
7874 | dirty_reg(¤t,CCREG); | |
7875 | current.isconst=0; | |
7876 | current.wasconst=0; | |
27727b63 | 7877 | current.waswritten=0; |
57871462 | 7878 | int ds=0; |
7879 | int cc=0; | |
5194fb95 | 7880 | int hr=-1; |
6ebf4adf | 7881 | |
57871462 | 7882 | if((u_int)addr&1) { |
7883 | // First instruction is delay slot | |
7884 | cc=-1; | |
7885 | bt[1]=1; | |
7886 | ds=1; | |
7887 | unneeded_reg[0]=1; | |
7888 | unneeded_reg_upper[0]=1; | |
7889 | current.regmap[HOST_BTREG]=BTREG; | |
7890 | } | |
9f51b4b9 | 7891 | |
57871462 | 7892 | for(i=0;i<slen;i++) |
7893 | { | |
7894 | if(bt[i]) | |
7895 | { | |
7896 | int hr; | |
7897 | for(hr=0;hr<HOST_REGS;hr++) | |
7898 | { | |
7899 | // Is this really necessary? | |
7900 | if(current.regmap[hr]==0) current.regmap[hr]=-1; | |
7901 | } | |
7902 | current.isconst=0; | |
27727b63 | 7903 | current.waswritten=0; |
57871462 | 7904 | } |
7905 | if(i>1) | |
7906 | { | |
7907 | if((opcode[i-2]&0x2f)==0x05) // BNE/BNEL | |
7908 | { | |
7909 | if(rs1[i-2]==0||rs2[i-2]==0) | |
7910 | { | |
7911 | if(rs1[i-2]) { | |
7912 | current.is32|=1LL<<rs1[i-2]; | |
7913 | int hr=get_reg(current.regmap,rs1[i-2]|64); | |
7914 | if(hr>=0) current.regmap[hr]=-1; | |
7915 | } | |
7916 | if(rs2[i-2]) { | |
7917 | current.is32|=1LL<<rs2[i-2]; | |
7918 | int hr=get_reg(current.regmap,rs2[i-2]|64); | |
7919 | if(hr>=0) current.regmap[hr]=-1; | |
7920 | } | |
7921 | } | |
7922 | } | |
7923 | } | |
24385cae | 7924 | current.is32=-1LL; |
24385cae | 7925 | |
57871462 | 7926 | memcpy(regmap_pre[i],current.regmap,sizeof(current.regmap)); |
7927 | regs[i].wasconst=current.isconst; | |
7928 | regs[i].was32=current.is32; | |
7929 | regs[i].wasdirty=current.dirty; | |
8575a877 | 7930 | regs[i].loadedconst=0; |
57871462 | 7931 | if(itype[i]!=UJUMP&&itype[i]!=CJUMP&&itype[i]!=SJUMP&&itype[i]!=RJUMP&&itype[i]!=FJUMP) { |
7932 | if(i+1<slen) { | |
7933 | current.u=unneeded_reg[i+1]&~((1LL<<rs1[i])|(1LL<<rs2[i])); | |
7934 | current.uu=unneeded_reg_upper[i+1]&~((1LL<<us1[i])|(1LL<<us2[i])); | |
7935 | if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i])); | |
7936 | current.u|=1; | |
7937 | current.uu|=1; | |
7938 | } else { | |
7939 | current.u=1; | |
7940 | current.uu=1; | |
7941 | } | |
7942 | } else { | |
7943 | if(i+1<slen) { | |
7944 | current.u=branch_unneeded_reg[i]&~((1LL<<rs1[i+1])|(1LL<<rs2[i+1])); | |
7945 | current.uu=branch_unneeded_reg_upper[i]&~((1LL<<us1[i+1])|(1LL<<us2[i+1])); | |
7946 | if((~current.uu>>rt1[i+1])&1) current.uu&=~((1LL<<dep1[i+1])|(1LL<<dep2[i+1])); | |
7947 | current.u&=~((1LL<<rs1[i])|(1LL<<rs2[i])); | |
7948 | current.uu&=~((1LL<<us1[i])|(1LL<<us2[i])); | |
7949 | current.u|=1; | |
7950 | current.uu|=1; | |
c43b5311 | 7951 | } else { SysPrintf("oops, branch at end of block with no delay slot\n");exit(1); } |
57871462 | 7952 | } |
7953 | is_ds[i]=ds; | |
7954 | if(ds) { | |
7955 | ds=0; // Skip delay slot, already allocated as part of branch | |
7956 | // ...but we need to alloc it in case something jumps here | |
7957 | if(i+1<slen) { | |
7958 | current.u=branch_unneeded_reg[i-1]&unneeded_reg[i+1]; | |
7959 | current.uu=branch_unneeded_reg_upper[i-1]&unneeded_reg_upper[i+1]; | |
7960 | }else{ | |
7961 | current.u=branch_unneeded_reg[i-1]; | |
7962 | current.uu=branch_unneeded_reg_upper[i-1]; | |
7963 | } | |
7964 | current.u&=~((1LL<<rs1[i])|(1LL<<rs2[i])); | |
7965 | current.uu&=~((1LL<<us1[i])|(1LL<<us2[i])); | |
7966 | if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i])); | |
7967 | current.u|=1; | |
7968 | current.uu|=1; | |
7969 | struct regstat temp; | |
7970 | memcpy(&temp,¤t,sizeof(current)); | |
7971 | temp.wasdirty=temp.dirty; | |
7972 | temp.was32=temp.is32; | |
7973 | // TODO: Take into account unconditional branches, as below | |
7974 | delayslot_alloc(&temp,i); | |
7975 | memcpy(regs[i].regmap,temp.regmap,sizeof(temp.regmap)); | |
7976 | regs[i].wasdirty=temp.wasdirty; | |
7977 | regs[i].was32=temp.was32; | |
7978 | regs[i].dirty=temp.dirty; | |
7979 | regs[i].is32=temp.is32; | |
7980 | regs[i].isconst=0; | |
7981 | regs[i].wasconst=0; | |
7982 | current.isconst=0; | |
7983 | // Create entry (branch target) regmap | |
7984 | for(hr=0;hr<HOST_REGS;hr++) | |
7985 | { | |
7986 | int r=temp.regmap[hr]; | |
7987 | if(r>=0) { | |
7988 | if(r!=regmap_pre[i][hr]) { | |
7989 | regs[i].regmap_entry[hr]=-1; | |
7990 | } | |
7991 | else | |
7992 | { | |
7993 | if(r<64){ | |
7994 | if((current.u>>r)&1) { | |
7995 | regs[i].regmap_entry[hr]=-1; | |
7996 | regs[i].regmap[hr]=-1; | |
7997 | //Don't clear regs in the delay slot as the branch might need them | |
7998 | //current.regmap[hr]=-1; | |
7999 | }else | |
8000 | regs[i].regmap_entry[hr]=r; | |
8001 | } | |
8002 | else { | |
8003 | if((current.uu>>(r&63))&1) { | |
8004 | regs[i].regmap_entry[hr]=-1; | |
8005 | regs[i].regmap[hr]=-1; | |
8006 | //Don't clear regs in the delay slot as the branch might need them | |
8007 | //current.regmap[hr]=-1; | |
8008 | }else | |
8009 | regs[i].regmap_entry[hr]=r; | |
8010 | } | |
8011 | } | |
8012 | } else { | |
8013 | // First instruction expects CCREG to be allocated | |
9f51b4b9 | 8014 | if(i==0&&hr==HOST_CCREG) |
57871462 | 8015 | regs[i].regmap_entry[hr]=CCREG; |
8016 | else | |
8017 | regs[i].regmap_entry[hr]=-1; | |
8018 | } | |
8019 | } | |
8020 | } | |
8021 | else { // Not delay slot | |
8022 | switch(itype[i]) { | |
8023 | case UJUMP: | |
8024 | //current.isconst=0; // DEBUG | |
8025 | //current.wasconst=0; // DEBUG | |
8026 | //regs[i].wasconst=0; // DEBUG | |
8027 | clear_const(¤t,rt1[i]); | |
8028 | alloc_cc(¤t,i); | |
8029 | dirty_reg(¤t,CCREG); | |
8030 | if (rt1[i]==31) { | |
8031 | alloc_reg(¤t,i,31); | |
8032 | dirty_reg(¤t,31); | |
4ef8f67d | 8033 | //assert(rs1[i+1]!=31&&rs2[i+1]!=31); |
8034 | //assert(rt1[i+1]!=rt1[i]); | |
57871462 | 8035 | #ifdef REG_PREFETCH |
8036 | alloc_reg(¤t,i,PTEMP); | |
8037 | #endif | |
8038 | //current.is32|=1LL<<rt1[i]; | |
8039 | } | |
269bb29a | 8040 | ooo[i]=1; |
8041 | delayslot_alloc(¤t,i+1); | |
57871462 | 8042 | //current.isconst=0; // DEBUG |
8043 | ds=1; | |
8044 | //printf("i=%d, isconst=%x\n",i,current.isconst); | |
8045 | break; | |
8046 | case RJUMP: | |
8047 | //current.isconst=0; | |
8048 | //current.wasconst=0; | |
8049 | //regs[i].wasconst=0; | |
8050 | clear_const(¤t,rs1[i]); | |
8051 | clear_const(¤t,rt1[i]); | |
8052 | alloc_cc(¤t,i); | |
8053 | dirty_reg(¤t,CCREG); | |
8054 | if(rs1[i]!=rt1[i+1]&&rs1[i]!=rt2[i+1]) { | |
8055 | alloc_reg(¤t,i,rs1[i]); | |
5067f341 | 8056 | if (rt1[i]!=0) { |
8057 | alloc_reg(¤t,i,rt1[i]); | |
8058 | dirty_reg(¤t,rt1[i]); | |
68b3faee | 8059 | assert(rs1[i+1]!=rt1[i]&&rs2[i+1]!=rt1[i]); |
076655d1 | 8060 | assert(rt1[i+1]!=rt1[i]); |
57871462 | 8061 | #ifdef REG_PREFETCH |
8062 | alloc_reg(¤t,i,PTEMP); | |
8063 | #endif | |
8064 | } | |
8065 | #ifdef USE_MINI_HT | |
8066 | if(rs1[i]==31) { // JALR | |
8067 | alloc_reg(¤t,i,RHASH); | |
8068 | #ifndef HOST_IMM_ADDR32 | |
8069 | alloc_reg(¤t,i,RHTBL); | |
8070 | #endif | |
8071 | } | |
8072 | #endif | |
8073 | delayslot_alloc(¤t,i+1); | |
8074 | } else { | |
8075 | // The delay slot overwrites our source register, | |
8076 | // allocate a temporary register to hold the old value. | |
8077 | current.isconst=0; | |
8078 | current.wasconst=0; | |
8079 | regs[i].wasconst=0; | |
8080 | delayslot_alloc(¤t,i+1); | |
8081 | current.isconst=0; | |
8082 | alloc_reg(¤t,i,RTEMP); | |
8083 | } | |
8084 | //current.isconst=0; // DEBUG | |
e1190b87 | 8085 | ooo[i]=1; |
57871462 | 8086 | ds=1; |
8087 | break; | |
8088 | case CJUMP: | |
8089 | //current.isconst=0; | |
8090 | //current.wasconst=0; | |
8091 | //regs[i].wasconst=0; | |
8092 | clear_const(¤t,rs1[i]); | |
8093 | clear_const(¤t,rs2[i]); | |
8094 | if((opcode[i]&0x3E)==4) // BEQ/BNE | |
8095 | { | |
8096 | alloc_cc(¤t,i); | |
8097 | dirty_reg(¤t,CCREG); | |
8098 | if(rs1[i]) alloc_reg(¤t,i,rs1[i]); | |
8099 | if(rs2[i]) alloc_reg(¤t,i,rs2[i]); | |
8100 | if(!((current.is32>>rs1[i])&(current.is32>>rs2[i])&1)) | |
8101 | { | |
8102 | if(rs1[i]) alloc_reg64(¤t,i,rs1[i]); | |
8103 | if(rs2[i]) alloc_reg64(¤t,i,rs2[i]); | |
8104 | } | |
8105 | if((rs1[i]&&(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1]))|| | |
8106 | (rs2[i]&&(rs2[i]==rt1[i+1]||rs2[i]==rt2[i+1]))) { | |
8107 | // The delay slot overwrites one of our conditions. | |
8108 | // Allocate the branch condition registers instead. | |
57871462 | 8109 | current.isconst=0; |
8110 | current.wasconst=0; | |
8111 | regs[i].wasconst=0; | |
8112 | if(rs1[i]) alloc_reg(¤t,i,rs1[i]); | |
8113 | if(rs2[i]) alloc_reg(¤t,i,rs2[i]); | |
8114 | if(!((current.is32>>rs1[i])&(current.is32>>rs2[i])&1)) | |
8115 | { | |
8116 | if(rs1[i]) alloc_reg64(¤t,i,rs1[i]); | |
8117 | if(rs2[i]) alloc_reg64(¤t,i,rs2[i]); | |
8118 | } | |
8119 | } | |
e1190b87 | 8120 | else |
8121 | { | |
8122 | ooo[i]=1; | |
8123 | delayslot_alloc(¤t,i+1); | |
8124 | } | |
57871462 | 8125 | } |
8126 | else | |
8127 | if((opcode[i]&0x3E)==6) // BLEZ/BGTZ | |
8128 | { | |
8129 | alloc_cc(¤t,i); | |
8130 | dirty_reg(¤t,CCREG); | |
8131 | alloc_reg(¤t,i,rs1[i]); | |
8132 | if(!(current.is32>>rs1[i]&1)) | |
8133 | { | |
8134 | alloc_reg64(¤t,i,rs1[i]); | |
8135 | } | |
8136 | if(rs1[i]&&(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1])) { | |
8137 | // The delay slot overwrites one of our conditions. | |
8138 | // Allocate the branch condition registers instead. | |
57871462 | 8139 | current.isconst=0; |
8140 | current.wasconst=0; | |
8141 | regs[i].wasconst=0; | |
8142 | if(rs1[i]) alloc_reg(¤t,i,rs1[i]); | |
8143 | if(!((current.is32>>rs1[i])&1)) | |
8144 | { | |
8145 | if(rs1[i]) alloc_reg64(¤t,i,rs1[i]); | |
8146 | } | |
8147 | } | |
e1190b87 | 8148 | else |
8149 | { | |
8150 | ooo[i]=1; | |
8151 | delayslot_alloc(¤t,i+1); | |
8152 | } | |
57871462 | 8153 | } |
8154 | else | |
8155 | // Don't alloc the delay slot yet because we might not execute it | |
8156 | if((opcode[i]&0x3E)==0x14) // BEQL/BNEL | |
8157 | { | |
8158 | current.isconst=0; | |
8159 | current.wasconst=0; | |
8160 | regs[i].wasconst=0; | |
8161 | alloc_cc(¤t,i); | |
8162 | dirty_reg(¤t,CCREG); | |
8163 | alloc_reg(¤t,i,rs1[i]); | |
8164 | alloc_reg(¤t,i,rs2[i]); | |
8165 | if(!((current.is32>>rs1[i])&(current.is32>>rs2[i])&1)) | |
8166 | { | |
8167 | alloc_reg64(¤t,i,rs1[i]); | |
8168 | alloc_reg64(¤t,i,rs2[i]); | |
8169 | } | |
8170 | } | |
8171 | else | |
8172 | if((opcode[i]&0x3E)==0x16) // BLEZL/BGTZL | |
8173 | { | |
8174 | current.isconst=0; | |
8175 | current.wasconst=0; | |
8176 | regs[i].wasconst=0; | |
8177 | alloc_cc(¤t,i); | |
8178 | dirty_reg(¤t,CCREG); | |
8179 | alloc_reg(¤t,i,rs1[i]); | |
8180 | if(!(current.is32>>rs1[i]&1)) | |
8181 | { | |
8182 | alloc_reg64(¤t,i,rs1[i]); | |
8183 | } | |
8184 | } | |
8185 | ds=1; | |
8186 | //current.isconst=0; | |
8187 | break; | |
8188 | case SJUMP: | |
8189 | //current.isconst=0; | |
8190 | //current.wasconst=0; | |
8191 | //regs[i].wasconst=0; | |
8192 | clear_const(¤t,rs1[i]); | |
8193 | clear_const(¤t,rt1[i]); | |
8194 | //if((opcode2[i]&0x1E)==0x0) // BLTZ/BGEZ | |
8195 | if((opcode2[i]&0x0E)==0x0) // BLTZ/BGEZ | |
8196 | { | |
8197 | alloc_cc(¤t,i); | |
8198 | dirty_reg(¤t,CCREG); | |
8199 | alloc_reg(¤t,i,rs1[i]); | |
8200 | if(!(current.is32>>rs1[i]&1)) | |
8201 | { | |
8202 | alloc_reg64(¤t,i,rs1[i]); | |
8203 | } | |
8204 | if (rt1[i]==31) { // BLTZAL/BGEZAL | |
8205 | alloc_reg(¤t,i,31); | |
8206 | dirty_reg(¤t,31); | |
57871462 | 8207 | //#ifdef REG_PREFETCH |
8208 | //alloc_reg(¤t,i,PTEMP); | |
8209 | //#endif | |
8210 | //current.is32|=1LL<<rt1[i]; | |
8211 | } | |
e1190b87 | 8212 | if((rs1[i]&&(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1])) // The delay slot overwrites the branch condition. |
8213 | ||(rt1[i]==31&&(rs1[i+1]==31||rs2[i+1]==31||rt1[i+1]==31||rt2[i+1]==31))) { // DS touches $ra | |
57871462 | 8214 | // Allocate the branch condition registers instead. |
57871462 | 8215 | current.isconst=0; |
8216 | current.wasconst=0; | |
8217 | regs[i].wasconst=0; | |
8218 | if(rs1[i]) alloc_reg(¤t,i,rs1[i]); | |
8219 | if(!((current.is32>>rs1[i])&1)) | |
8220 | { | |
8221 | if(rs1[i]) alloc_reg64(¤t,i,rs1[i]); | |
8222 | } | |
8223 | } | |
e1190b87 | 8224 | else |
8225 | { | |
8226 | ooo[i]=1; | |
8227 | delayslot_alloc(¤t,i+1); | |
8228 | } | |
57871462 | 8229 | } |
8230 | else | |
8231 | // Don't alloc the delay slot yet because we might not execute it | |
8232 | if((opcode2[i]&0x1E)==0x2) // BLTZL/BGEZL | |
8233 | { | |
8234 | current.isconst=0; | |
8235 | current.wasconst=0; | |
8236 | regs[i].wasconst=0; | |
8237 | alloc_cc(¤t,i); | |
8238 | dirty_reg(¤t,CCREG); | |
8239 | alloc_reg(¤t,i,rs1[i]); | |
8240 | if(!(current.is32>>rs1[i]&1)) | |
8241 | { | |
8242 | alloc_reg64(¤t,i,rs1[i]); | |
8243 | } | |
8244 | } | |
8245 | ds=1; | |
8246 | //current.isconst=0; | |
8247 | break; | |
8248 | case FJUMP: | |
8249 | current.isconst=0; | |
8250 | current.wasconst=0; | |
8251 | regs[i].wasconst=0; | |
8252 | if(likely[i]==0) // BC1F/BC1T | |
8253 | { | |
8254 | // TODO: Theoretically we can run out of registers here on x86. | |
8255 | // The delay slot can allocate up to six, and we need to check | |
8256 | // CSREG before executing the delay slot. Possibly we can drop | |
8257 | // the cycle count and then reload it after checking that the | |
8258 | // FPU is in a usable state, or don't do out-of-order execution. | |
8259 | alloc_cc(¤t,i); | |
8260 | dirty_reg(¤t,CCREG); | |
8261 | alloc_reg(¤t,i,FSREG); | |
8262 | alloc_reg(¤t,i,CSREG); | |
8263 | if(itype[i+1]==FCOMP) { | |
8264 | // The delay slot overwrites the branch condition. | |
8265 | // Allocate the branch condition registers instead. | |
57871462 | 8266 | alloc_cc(¤t,i); |
8267 | dirty_reg(¤t,CCREG); | |
8268 | alloc_reg(¤t,i,CSREG); | |
8269 | alloc_reg(¤t,i,FSREG); | |
8270 | } | |
8271 | else { | |
e1190b87 | 8272 | ooo[i]=1; |
57871462 | 8273 | delayslot_alloc(¤t,i+1); |
8274 | alloc_reg(¤t,i+1,CSREG); | |
8275 | } | |
8276 | } | |
8277 | else | |
8278 | // Don't alloc the delay slot yet because we might not execute it | |
8279 | if(likely[i]) // BC1FL/BC1TL | |
8280 | { | |
8281 | alloc_cc(¤t,i); | |
8282 | dirty_reg(¤t,CCREG); | |
8283 | alloc_reg(¤t,i,CSREG); | |
8284 | alloc_reg(¤t,i,FSREG); | |
8285 | } | |
8286 | ds=1; | |
8287 | current.isconst=0; | |
8288 | break; | |
8289 | case IMM16: | |
8290 | imm16_alloc(¤t,i); | |
8291 | break; | |
8292 | case LOAD: | |
8293 | case LOADLR: | |
8294 | load_alloc(¤t,i); | |
8295 | break; | |
8296 | case STORE: | |
8297 | case STORELR: | |
8298 | store_alloc(¤t,i); | |
8299 | break; | |
8300 | case ALU: | |
8301 | alu_alloc(¤t,i); | |
8302 | break; | |
8303 | case SHIFT: | |
8304 | shift_alloc(¤t,i); | |
8305 | break; | |
8306 | case MULTDIV: | |
8307 | multdiv_alloc(¤t,i); | |
8308 | break; | |
8309 | case SHIFTIMM: | |
8310 | shiftimm_alloc(¤t,i); | |
8311 | break; | |
8312 | case MOV: | |
8313 | mov_alloc(¤t,i); | |
8314 | break; | |
8315 | case COP0: | |
8316 | cop0_alloc(¤t,i); | |
8317 | break; | |
8318 | case COP1: | |
b9b61529 | 8319 | case COP2: |
57871462 | 8320 | cop1_alloc(¤t,i); |
8321 | break; | |
8322 | case C1LS: | |
8323 | c1ls_alloc(¤t,i); | |
8324 | break; | |
b9b61529 | 8325 | case C2LS: |
8326 | c2ls_alloc(¤t,i); | |
8327 | break; | |
8328 | case C2OP: | |
8329 | c2op_alloc(¤t,i); | |
8330 | break; | |
57871462 | 8331 | case FCONV: |
8332 | fconv_alloc(¤t,i); | |
8333 | break; | |
8334 | case FLOAT: | |
8335 | float_alloc(¤t,i); | |
8336 | break; | |
8337 | case FCOMP: | |
8338 | fcomp_alloc(¤t,i); | |
8339 | break; | |
8340 | case SYSCALL: | |
7139f3c8 | 8341 | case HLECALL: |
1e973cb0 | 8342 | case INTCALL: |
57871462 | 8343 | syscall_alloc(¤t,i); |
8344 | break; | |
8345 | case SPAN: | |
8346 | pagespan_alloc(¤t,i); | |
8347 | break; | |
8348 | } | |
9f51b4b9 | 8349 | |
57871462 | 8350 | // Drop the upper half of registers that have become 32-bit |
8351 | current.uu|=current.is32&((1LL<<rt1[i])|(1LL<<rt2[i])); | |
8352 | if(itype[i]!=UJUMP&&itype[i]!=CJUMP&&itype[i]!=SJUMP&&itype[i]!=RJUMP&&itype[i]!=FJUMP) { | |
8353 | current.uu&=~((1LL<<us1[i])|(1LL<<us2[i])); | |
8354 | if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i])); | |
8355 | current.uu|=1; | |
8356 | } else { | |
8357 | current.uu|=current.is32&((1LL<<rt1[i+1])|(1LL<<rt2[i+1])); | |
8358 | current.uu&=~((1LL<<us1[i+1])|(1LL<<us2[i+1])); | |
8359 | if((~current.uu>>rt1[i+1])&1) current.uu&=~((1LL<<dep1[i+1])|(1LL<<dep2[i+1])); | |
8360 | current.uu&=~((1LL<<us1[i])|(1LL<<us2[i])); | |
8361 | current.uu|=1; | |
8362 | } | |
8363 | ||
8364 | // Create entry (branch target) regmap | |
8365 | for(hr=0;hr<HOST_REGS;hr++) | |
8366 | { | |
581335b0 | 8367 | int r,or; |
57871462 | 8368 | r=current.regmap[hr]; |
8369 | if(r>=0) { | |
8370 | if(r!=regmap_pre[i][hr]) { | |
8371 | // TODO: delay slot (?) | |
8372 | or=get_reg(regmap_pre[i],r); // Get old mapping for this register | |
8373 | if(or<0||(r&63)>=TEMPREG){ | |
8374 | regs[i].regmap_entry[hr]=-1; | |
8375 | } | |
8376 | else | |
8377 | { | |
8378 | // Just move it to a different register | |
8379 | regs[i].regmap_entry[hr]=r; | |
8380 | // If it was dirty before, it's still dirty | |
8381 | if((regs[i].wasdirty>>or)&1) dirty_reg(¤t,r&63); | |
8382 | } | |
8383 | } | |
8384 | else | |
8385 | { | |
8386 | // Unneeded | |
8387 | if(r==0){ | |
8388 | regs[i].regmap_entry[hr]=0; | |
8389 | } | |
8390 | else | |
8391 | if(r<64){ | |
8392 | if((current.u>>r)&1) { | |
8393 | regs[i].regmap_entry[hr]=-1; | |
8394 | //regs[i].regmap[hr]=-1; | |
8395 | current.regmap[hr]=-1; | |
8396 | }else | |
8397 | regs[i].regmap_entry[hr]=r; | |
8398 | } | |
8399 | else { | |
8400 | if((current.uu>>(r&63))&1) { | |
8401 | regs[i].regmap_entry[hr]=-1; | |
8402 | //regs[i].regmap[hr]=-1; | |
8403 | current.regmap[hr]=-1; | |
8404 | }else | |
8405 | regs[i].regmap_entry[hr]=r; | |
8406 | } | |
8407 | } | |
8408 | } else { | |
8409 | // Branches expect CCREG to be allocated at the target | |
9f51b4b9 | 8410 | if(regmap_pre[i][hr]==CCREG) |
57871462 | 8411 | regs[i].regmap_entry[hr]=CCREG; |
8412 | else | |
8413 | regs[i].regmap_entry[hr]=-1; | |
8414 | } | |
8415 | } | |
8416 | memcpy(regs[i].regmap,current.regmap,sizeof(current.regmap)); | |
8417 | } | |
27727b63 | 8418 | |
8419 | if(i>0&&(itype[i-1]==STORE||itype[i-1]==STORELR||(itype[i-1]==C2LS&&opcode[i-1]==0x3a))&&(u_int)imm[i-1]<0x800) | |
8420 | current.waswritten|=1<<rs1[i-1]; | |
8421 | current.waswritten&=~(1<<rt1[i]); | |
8422 | current.waswritten&=~(1<<rt2[i]); | |
8423 | if((itype[i]==STORE||itype[i]==STORELR||(itype[i]==C2LS&&opcode[i]==0x3a))&&(u_int)imm[i]>=0x800) | |
8424 | current.waswritten&=~(1<<rs1[i]); | |
8425 | ||
57871462 | 8426 | /* Branch post-alloc */ |
8427 | if(i>0) | |
8428 | { | |
8429 | current.was32=current.is32; | |
8430 | current.wasdirty=current.dirty; | |
8431 | switch(itype[i-1]) { | |
8432 | case UJUMP: | |
8433 | memcpy(&branch_regs[i-1],¤t,sizeof(current)); | |
8434 | branch_regs[i-1].isconst=0; | |
8435 | branch_regs[i-1].wasconst=0; | |
8436 | branch_regs[i-1].u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i-1])|(1LL<<rs2[i-1])); | |
8437 | branch_regs[i-1].uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i-1])|(1LL<<us2[i-1])); | |
8438 | alloc_cc(&branch_regs[i-1],i-1); | |
8439 | dirty_reg(&branch_regs[i-1],CCREG); | |
8440 | if(rt1[i-1]==31) { // JAL | |
8441 | alloc_reg(&branch_regs[i-1],i-1,31); | |
8442 | dirty_reg(&branch_regs[i-1],31); | |
8443 | branch_regs[i-1].is32|=1LL<<31; | |
8444 | } | |
8445 | memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap)); | |
956f3129 | 8446 | memcpy(constmap[i],constmap[i-1],sizeof(current_constmap)); |
57871462 | 8447 | break; |
8448 | case RJUMP: | |
8449 | memcpy(&branch_regs[i-1],¤t,sizeof(current)); | |
8450 | branch_regs[i-1].isconst=0; | |
8451 | branch_regs[i-1].wasconst=0; | |
8452 | branch_regs[i-1].u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i-1])|(1LL<<rs2[i-1])); | |
8453 | branch_regs[i-1].uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i-1])|(1LL<<us2[i-1])); | |
8454 | alloc_cc(&branch_regs[i-1],i-1); | |
8455 | dirty_reg(&branch_regs[i-1],CCREG); | |
8456 | alloc_reg(&branch_regs[i-1],i-1,rs1[i-1]); | |
5067f341 | 8457 | if(rt1[i-1]!=0) { // JALR |
8458 | alloc_reg(&branch_regs[i-1],i-1,rt1[i-1]); | |
8459 | dirty_reg(&branch_regs[i-1],rt1[i-1]); | |
8460 | branch_regs[i-1].is32|=1LL<<rt1[i-1]; | |
57871462 | 8461 | } |
8462 | #ifdef USE_MINI_HT | |
8463 | if(rs1[i-1]==31) { // JALR | |
8464 | alloc_reg(&branch_regs[i-1],i-1,RHASH); | |
8465 | #ifndef HOST_IMM_ADDR32 | |
8466 | alloc_reg(&branch_regs[i-1],i-1,RHTBL); | |
8467 | #endif | |
8468 | } | |
8469 | #endif | |
8470 | memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap)); | |
956f3129 | 8471 | memcpy(constmap[i],constmap[i-1],sizeof(current_constmap)); |
57871462 | 8472 | break; |
8473 | case CJUMP: | |
8474 | if((opcode[i-1]&0x3E)==4) // BEQ/BNE | |
8475 | { | |
8476 | alloc_cc(¤t,i-1); | |
8477 | dirty_reg(¤t,CCREG); | |
8478 | if((rs1[i-1]&&(rs1[i-1]==rt1[i]||rs1[i-1]==rt2[i]))|| | |
8479 | (rs2[i-1]&&(rs2[i-1]==rt1[i]||rs2[i-1]==rt2[i]))) { | |
8480 | // The delay slot overwrote one of our conditions | |
8481 | // Delay slot goes after the test (in order) | |
8482 | current.u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i])); | |
8483 | current.uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i])); | |
8484 | if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i])); | |
8485 | current.u|=1; | |
8486 | current.uu|=1; | |
8487 | delayslot_alloc(¤t,i); | |
8488 | current.isconst=0; | |
8489 | } | |
8490 | else | |
8491 | { | |
8492 | current.u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i-1])|(1LL<<rs2[i-1])); | |
8493 | current.uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i-1])|(1LL<<us2[i-1])); | |
8494 | // Alloc the branch condition registers | |
8495 | if(rs1[i-1]) alloc_reg(¤t,i-1,rs1[i-1]); | |
8496 | if(rs2[i-1]) alloc_reg(¤t,i-1,rs2[i-1]); | |
8497 | if(!((current.is32>>rs1[i-1])&(current.is32>>rs2[i-1])&1)) | |
8498 | { | |
8499 | if(rs1[i-1]) alloc_reg64(¤t,i-1,rs1[i-1]); | |
8500 | if(rs2[i-1]) alloc_reg64(¤t,i-1,rs2[i-1]); | |
8501 | } | |
8502 | } | |
8503 | memcpy(&branch_regs[i-1],¤t,sizeof(current)); | |
8504 | branch_regs[i-1].isconst=0; | |
8505 | branch_regs[i-1].wasconst=0; | |
8506 | memcpy(&branch_regs[i-1].regmap_entry,¤t.regmap,sizeof(current.regmap)); | |
956f3129 | 8507 | memcpy(constmap[i],constmap[i-1],sizeof(current_constmap)); |
57871462 | 8508 | } |
8509 | else | |
8510 | if((opcode[i-1]&0x3E)==6) // BLEZ/BGTZ | |
8511 | { | |
8512 | alloc_cc(¤t,i-1); | |
8513 | dirty_reg(¤t,CCREG); | |
8514 | if(rs1[i-1]==rt1[i]||rs1[i-1]==rt2[i]) { | |
8515 | // The delay slot overwrote the branch condition | |
8516 | // Delay slot goes after the test (in order) | |
8517 | current.u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i])); | |
8518 | current.uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i])); | |
8519 | if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i])); | |
8520 | current.u|=1; | |
8521 | current.uu|=1; | |
8522 | delayslot_alloc(¤t,i); | |
8523 | current.isconst=0; | |
8524 | } | |
8525 | else | |
8526 | { | |
8527 | current.u=branch_unneeded_reg[i-1]&~(1LL<<rs1[i-1]); | |
8528 | current.uu=branch_unneeded_reg_upper[i-1]&~(1LL<<us1[i-1]); | |
8529 | // Alloc the branch condition register | |
8530 | alloc_reg(¤t,i-1,rs1[i-1]); | |
8531 | if(!(current.is32>>rs1[i-1]&1)) | |
8532 | { | |
8533 | alloc_reg64(¤t,i-1,rs1[i-1]); | |
8534 | } | |
8535 | } | |
8536 | memcpy(&branch_regs[i-1],¤t,sizeof(current)); | |
8537 | branch_regs[i-1].isconst=0; | |
8538 | branch_regs[i-1].wasconst=0; | |
8539 | memcpy(&branch_regs[i-1].regmap_entry,¤t.regmap,sizeof(current.regmap)); | |
956f3129 | 8540 | memcpy(constmap[i],constmap[i-1],sizeof(current_constmap)); |
57871462 | 8541 | } |
8542 | else | |
8543 | // Alloc the delay slot in case the branch is taken | |
8544 | if((opcode[i-1]&0x3E)==0x14) // BEQL/BNEL | |
8545 | { | |
8546 | memcpy(&branch_regs[i-1],¤t,sizeof(current)); | |
8547 | branch_regs[i-1].u=(branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1; | |
8548 | branch_regs[i-1].uu=(branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1; | |
8549 | if((~branch_regs[i-1].uu>>rt1[i])&1) branch_regs[i-1].uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]))|1; | |
8550 | alloc_cc(&branch_regs[i-1],i); | |
8551 | dirty_reg(&branch_regs[i-1],CCREG); | |
8552 | delayslot_alloc(&branch_regs[i-1],i); | |
8553 | branch_regs[i-1].isconst=0; | |
8554 | alloc_reg(¤t,i,CCREG); // Not taken path | |
8555 | dirty_reg(¤t,CCREG); | |
8556 | memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap)); | |
8557 | } | |
8558 | else | |
8559 | if((opcode[i-1]&0x3E)==0x16) // BLEZL/BGTZL | |
8560 | { | |
8561 | memcpy(&branch_regs[i-1],¤t,sizeof(current)); | |
8562 | branch_regs[i-1].u=(branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1; | |
8563 | branch_regs[i-1].uu=(branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1; | |
8564 | if((~branch_regs[i-1].uu>>rt1[i])&1) branch_regs[i-1].uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]))|1; | |
8565 | alloc_cc(&branch_regs[i-1],i); | |
8566 | dirty_reg(&branch_regs[i-1],CCREG); | |
8567 | delayslot_alloc(&branch_regs[i-1],i); | |
8568 | branch_regs[i-1].isconst=0; | |
8569 | alloc_reg(¤t,i,CCREG); // Not taken path | |
8570 | dirty_reg(¤t,CCREG); | |
8571 | memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap)); | |
8572 | } | |
8573 | break; | |
8574 | case SJUMP: | |
8575 | //if((opcode2[i-1]&0x1E)==0) // BLTZ/BGEZ | |
8576 | if((opcode2[i-1]&0x0E)==0) // BLTZ/BGEZ | |
8577 | { | |
8578 | alloc_cc(¤t,i-1); | |
8579 | dirty_reg(¤t,CCREG); | |
8580 | if(rs1[i-1]==rt1[i]||rs1[i-1]==rt2[i]) { | |
8581 | // The delay slot overwrote the branch condition | |
8582 | // Delay slot goes after the test (in order) | |
8583 | current.u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i])); | |
8584 | current.uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i])); | |
8585 | if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i])); | |
8586 | current.u|=1; | |
8587 | current.uu|=1; | |
8588 | delayslot_alloc(¤t,i); | |
8589 | current.isconst=0; | |
8590 | } | |
8591 | else | |
8592 | { | |
8593 | current.u=branch_unneeded_reg[i-1]&~(1LL<<rs1[i-1]); | |
8594 | current.uu=branch_unneeded_reg_upper[i-1]&~(1LL<<us1[i-1]); | |
8595 | // Alloc the branch condition register | |
8596 | alloc_reg(¤t,i-1,rs1[i-1]); | |
8597 | if(!(current.is32>>rs1[i-1]&1)) | |
8598 | { | |
8599 | alloc_reg64(¤t,i-1,rs1[i-1]); | |
8600 | } | |
8601 | } | |
8602 | memcpy(&branch_regs[i-1],¤t,sizeof(current)); | |
8603 | branch_regs[i-1].isconst=0; | |
8604 | branch_regs[i-1].wasconst=0; | |
8605 | memcpy(&branch_regs[i-1].regmap_entry,¤t.regmap,sizeof(current.regmap)); | |
956f3129 | 8606 | memcpy(constmap[i],constmap[i-1],sizeof(current_constmap)); |
57871462 | 8607 | } |
8608 | else | |
8609 | // Alloc the delay slot in case the branch is taken | |
8610 | if((opcode2[i-1]&0x1E)==2) // BLTZL/BGEZL | |
8611 | { | |
8612 | memcpy(&branch_regs[i-1],¤t,sizeof(current)); | |
8613 | branch_regs[i-1].u=(branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1; | |
8614 | branch_regs[i-1].uu=(branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1; | |
8615 | if((~branch_regs[i-1].uu>>rt1[i])&1) branch_regs[i-1].uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]))|1; | |
8616 | alloc_cc(&branch_regs[i-1],i); | |
8617 | dirty_reg(&branch_regs[i-1],CCREG); | |
8618 | delayslot_alloc(&branch_regs[i-1],i); | |
8619 | branch_regs[i-1].isconst=0; | |
8620 | alloc_reg(¤t,i,CCREG); // Not taken path | |
8621 | dirty_reg(¤t,CCREG); | |
8622 | memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap)); | |
8623 | } | |
8624 | // FIXME: BLTZAL/BGEZAL | |
8625 | if(opcode2[i-1]&0x10) { // BxxZAL | |
8626 | alloc_reg(&branch_regs[i-1],i-1,31); | |
8627 | dirty_reg(&branch_regs[i-1],31); | |
8628 | branch_regs[i-1].is32|=1LL<<31; | |
8629 | } | |
8630 | break; | |
8631 | case FJUMP: | |
8632 | if(likely[i-1]==0) // BC1F/BC1T | |
8633 | { | |
8634 | alloc_cc(¤t,i-1); | |
8635 | dirty_reg(¤t,CCREG); | |
8636 | if(itype[i]==FCOMP) { | |
8637 | // The delay slot overwrote the branch condition | |
8638 | // Delay slot goes after the test (in order) | |
8639 | delayslot_alloc(¤t,i); | |
8640 | current.isconst=0; | |
8641 | } | |
8642 | else | |
8643 | { | |
8644 | current.u=branch_unneeded_reg[i-1]&~(1LL<<rs1[i-1]); | |
8645 | current.uu=branch_unneeded_reg_upper[i-1]&~(1LL<<us1[i-1]); | |
8646 | // Alloc the branch condition register | |
8647 | alloc_reg(¤t,i-1,FSREG); | |
8648 | } | |
8649 | memcpy(&branch_regs[i-1],¤t,sizeof(current)); | |
8650 | memcpy(&branch_regs[i-1].regmap_entry,¤t.regmap,sizeof(current.regmap)); | |
8651 | } | |
8652 | else // BC1FL/BC1TL | |
8653 | { | |
8654 | // Alloc the delay slot in case the branch is taken | |
8655 | memcpy(&branch_regs[i-1],¤t,sizeof(current)); | |
8656 | branch_regs[i-1].u=(branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1; | |
8657 | branch_regs[i-1].uu=(branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1; | |
8658 | if((~branch_regs[i-1].uu>>rt1[i])&1) branch_regs[i-1].uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]))|1; | |
8659 | alloc_cc(&branch_regs[i-1],i); | |
8660 | dirty_reg(&branch_regs[i-1],CCREG); | |
8661 | delayslot_alloc(&branch_regs[i-1],i); | |
8662 | branch_regs[i-1].isconst=0; | |
8663 | alloc_reg(¤t,i,CCREG); // Not taken path | |
8664 | dirty_reg(¤t,CCREG); | |
8665 | memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap)); | |
8666 | } | |
8667 | break; | |
8668 | } | |
8669 | ||
8670 | if(itype[i-1]==UJUMP||itype[i-1]==RJUMP||(source[i-1]>>16)==0x1000) | |
8671 | { | |
8672 | if(rt1[i-1]==31) // JAL/JALR | |
8673 | { | |
8674 | // Subroutine call will return here, don't alloc any registers | |
8675 | current.is32=1; | |
8676 | current.dirty=0; | |
8677 | clear_all_regs(current.regmap); | |
8678 | alloc_reg(¤t,i,CCREG); | |
8679 | dirty_reg(¤t,CCREG); | |
8680 | } | |
8681 | else if(i+1<slen) | |
8682 | { | |
8683 | // Internal branch will jump here, match registers to caller | |
8684 | current.is32=0x3FFFFFFFFLL; | |
8685 | current.dirty=0; | |
8686 | clear_all_regs(current.regmap); | |
8687 | alloc_reg(¤t,i,CCREG); | |
8688 | dirty_reg(¤t,CCREG); | |
8689 | for(j=i-1;j>=0;j--) | |
8690 | { | |
8691 | if(ba[j]==start+i*4+4) { | |
8692 | memcpy(current.regmap,branch_regs[j].regmap,sizeof(current.regmap)); | |
8693 | current.is32=branch_regs[j].is32; | |
8694 | current.dirty=branch_regs[j].dirty; | |
8695 | break; | |
8696 | } | |
8697 | } | |
8698 | while(j>=0) { | |
8699 | if(ba[j]==start+i*4+4) { | |
8700 | for(hr=0;hr<HOST_REGS;hr++) { | |
8701 | if(current.regmap[hr]!=branch_regs[j].regmap[hr]) { | |
8702 | current.regmap[hr]=-1; | |
8703 | } | |
8704 | current.is32&=branch_regs[j].is32; | |
8705 | current.dirty&=branch_regs[j].dirty; | |
8706 | } | |
8707 | } | |
8708 | j--; | |
8709 | } | |
8710 | } | |
8711 | } | |
8712 | } | |
8713 | ||
8714 | // Count cycles in between branches | |
8715 | ccadj[i]=cc; | |
7139f3c8 | 8716 | if(i>0&&(itype[i-1]==RJUMP||itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP||itype[i]==SYSCALL||itype[i]==HLECALL)) |
57871462 | 8717 | { |
8718 | cc=0; | |
8719 | } | |
71e490c5 | 8720 | #if !defined(DRC_DBG) |
054175e9 | 8721 | else if(itype[i]==C2OP&>e_cycletab[source[i]&0x3f]>2) |
8722 | { | |
8723 | // GTE runs in parallel until accessed, divide by 2 for a rough guess | |
8724 | cc+=gte_cycletab[source[i]&0x3f]/2; | |
8725 | } | |
b6e87b2b | 8726 | else if(/*itype[i]==LOAD||itype[i]==STORE||*/itype[i]==C1LS) // load,store causes weird timing issues |
fb407447 | 8727 | { |
8728 | cc+=2; // 2 cycle penalty (after CLOCK_DIVIDER) | |
8729 | } | |
5fdcbb5a | 8730 | else if(i>1&&itype[i]==STORE&&itype[i-1]==STORE&&itype[i-2]==STORE&&!bt[i]) |
8731 | { | |
8732 | cc+=4; | |
8733 | } | |
fb407447 | 8734 | else if(itype[i]==C2LS) |
8735 | { | |
8736 | cc+=4; | |
8737 | } | |
8738 | #endif | |
57871462 | 8739 | else |
8740 | { | |
8741 | cc++; | |
8742 | } | |
8743 | ||
8744 | flush_dirty_uppers(¤t); | |
8745 | if(!is_ds[i]) { | |
8746 | regs[i].is32=current.is32; | |
8747 | regs[i].dirty=current.dirty; | |
8748 | regs[i].isconst=current.isconst; | |
956f3129 | 8749 | memcpy(constmap[i],current_constmap,sizeof(current_constmap)); |
57871462 | 8750 | } |
8751 | for(hr=0;hr<HOST_REGS;hr++) { | |
8752 | if(hr!=EXCLUDE_REG&®s[i].regmap[hr]>=0) { | |
8753 | if(regmap_pre[i][hr]!=regs[i].regmap[hr]) { | |
8754 | regs[i].wasconst&=~(1<<hr); | |
8755 | } | |
8756 | } | |
8757 | } | |
8758 | if(current.regmap[HOST_BTREG]==BTREG) current.regmap[HOST_BTREG]=-1; | |
27727b63 | 8759 | regs[i].waswritten=current.waswritten; |
57871462 | 8760 | } |
9f51b4b9 | 8761 | |
57871462 | 8762 | /* Pass 4 - Cull unused host registers */ |
9f51b4b9 | 8763 | |
57871462 | 8764 | uint64_t nr=0; |
9f51b4b9 | 8765 | |
57871462 | 8766 | for (i=slen-1;i>=0;i--) |
8767 | { | |
8768 | int hr; | |
8769 | if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP) | |
8770 | { | |
8771 | if(ba[i]<start || ba[i]>=(start+slen*4)) | |
8772 | { | |
8773 | // Branch out of this block, don't need anything | |
8774 | nr=0; | |
8775 | } | |
8776 | else | |
8777 | { | |
8778 | // Internal branch | |
8779 | // Need whatever matches the target | |
8780 | nr=0; | |
8781 | int t=(ba[i]-start)>>2; | |
8782 | for(hr=0;hr<HOST_REGS;hr++) | |
8783 | { | |
8784 | if(regs[i].regmap_entry[hr]>=0) { | |
8785 | if(regs[i].regmap_entry[hr]==regs[t].regmap_entry[hr]) nr|=1<<hr; | |
8786 | } | |
8787 | } | |
8788 | } | |
8789 | // Conditional branch may need registers for following instructions | |
8790 | if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000) | |
8791 | { | |
8792 | if(i<slen-2) { | |
8793 | nr|=needed_reg[i+2]; | |
8794 | for(hr=0;hr<HOST_REGS;hr++) | |
8795 | { | |
8796 | if(regmap_pre[i+2][hr]>=0&&get_reg(regs[i+2].regmap_entry,regmap_pre[i+2][hr])<0) nr&=~(1<<hr); | |
8797 | //if((regmap_entry[i+2][hr])>=0) if(!((nr>>hr)&1)) printf("%x-bogus(%d=%d)\n",start+i*4,hr,regmap_entry[i+2][hr]); | |
8798 | } | |
8799 | } | |
8800 | } | |
8801 | // Don't need stuff which is overwritten | |
f5955059 | 8802 | //if(regs[i].regmap[hr]!=regmap_pre[i][hr]) nr&=~(1<<hr); |
8803 | //if(regs[i].regmap[hr]<0) nr&=~(1<<hr); | |
57871462 | 8804 | // Merge in delay slot |
8805 | for(hr=0;hr<HOST_REGS;hr++) | |
8806 | { | |
8807 | if(!likely[i]) { | |
8808 | // These are overwritten unless the branch is "likely" | |
8809 | // and the delay slot is nullified if not taken | |
8810 | if(rt1[i+1]&&rt1[i+1]==(regs[i].regmap[hr]&63)) nr&=~(1<<hr); | |
8811 | if(rt2[i+1]&&rt2[i+1]==(regs[i].regmap[hr]&63)) nr&=~(1<<hr); | |
8812 | } | |
8813 | if(us1[i+1]==(regmap_pre[i][hr]&63)) nr|=1<<hr; | |
8814 | if(us2[i+1]==(regmap_pre[i][hr]&63)) nr|=1<<hr; | |
8815 | if(rs1[i+1]==regmap_pre[i][hr]) nr|=1<<hr; | |
8816 | if(rs2[i+1]==regmap_pre[i][hr]) nr|=1<<hr; | |
8817 | if(us1[i+1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr; | |
8818 | if(us2[i+1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr; | |
8819 | if(rs1[i+1]==regs[i].regmap_entry[hr]) nr|=1<<hr; | |
8820 | if(rs2[i+1]==regs[i].regmap_entry[hr]) nr|=1<<hr; | |
8821 | if(dep1[i+1]&&!((unneeded_reg_upper[i]>>dep1[i+1])&1)) { | |
8822 | if(dep1[i+1]==(regmap_pre[i][hr]&63)) nr|=1<<hr; | |
8823 | if(dep2[i+1]==(regmap_pre[i][hr]&63)) nr|=1<<hr; | |
8824 | } | |
8825 | if(dep2[i+1]&&!((unneeded_reg_upper[i]>>dep2[i+1])&1)) { | |
8826 | if(dep1[i+1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr; | |
8827 | if(dep2[i+1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr; | |
8828 | } | |
b9b61529 | 8829 | if(itype[i+1]==STORE || itype[i+1]==STORELR || (opcode[i+1]&0x3b)==0x39 || (opcode[i+1]&0x3b)==0x3a) { |
57871462 | 8830 | if(regmap_pre[i][hr]==INVCP) nr|=1<<hr; |
8831 | if(regs[i].regmap_entry[hr]==INVCP) nr|=1<<hr; | |
8832 | } | |
8833 | } | |
8834 | } | |
1e973cb0 | 8835 | else if(itype[i]==SYSCALL||itype[i]==HLECALL||itype[i]==INTCALL) |
57871462 | 8836 | { |
8837 | // SYSCALL instruction (software interrupt) | |
8838 | nr=0; | |
8839 | } | |
8840 | else if(itype[i]==COP0 && (source[i]&0x3f)==0x18) | |
8841 | { | |
8842 | // ERET instruction (return from interrupt) | |
8843 | nr=0; | |
8844 | } | |
8845 | else // Non-branch | |
8846 | { | |
8847 | if(i<slen-1) { | |
8848 | for(hr=0;hr<HOST_REGS;hr++) { | |
8849 | if(regmap_pre[i+1][hr]>=0&&get_reg(regs[i+1].regmap_entry,regmap_pre[i+1][hr])<0) nr&=~(1<<hr); | |
8850 | if(regs[i].regmap[hr]!=regmap_pre[i+1][hr]) nr&=~(1<<hr); | |
8851 | if(regs[i].regmap[hr]!=regmap_pre[i][hr]) nr&=~(1<<hr); | |
8852 | if(regs[i].regmap[hr]<0) nr&=~(1<<hr); | |
8853 | } | |
8854 | } | |
8855 | } | |
8856 | for(hr=0;hr<HOST_REGS;hr++) | |
8857 | { | |
8858 | // Overwritten registers are not needed | |
8859 | if(rt1[i]&&rt1[i]==(regs[i].regmap[hr]&63)) nr&=~(1<<hr); | |
8860 | if(rt2[i]&&rt2[i]==(regs[i].regmap[hr]&63)) nr&=~(1<<hr); | |
8861 | if(FTEMP==(regs[i].regmap[hr]&63)) nr&=~(1<<hr); | |
8862 | // Source registers are needed | |
8863 | if(us1[i]==(regmap_pre[i][hr]&63)) nr|=1<<hr; | |
8864 | if(us2[i]==(regmap_pre[i][hr]&63)) nr|=1<<hr; | |
8865 | if(rs1[i]==regmap_pre[i][hr]) nr|=1<<hr; | |
8866 | if(rs2[i]==regmap_pre[i][hr]) nr|=1<<hr; | |
8867 | if(us1[i]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr; | |
8868 | if(us2[i]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr; | |
8869 | if(rs1[i]==regs[i].regmap_entry[hr]) nr|=1<<hr; | |
8870 | if(rs2[i]==regs[i].regmap_entry[hr]) nr|=1<<hr; | |
8871 | if(dep1[i]&&!((unneeded_reg_upper[i]>>dep1[i])&1)) { | |
8872 | if(dep1[i]==(regmap_pre[i][hr]&63)) nr|=1<<hr; | |
8873 | if(dep1[i]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr; | |
8874 | } | |
8875 | if(dep2[i]&&!((unneeded_reg_upper[i]>>dep2[i])&1)) { | |
8876 | if(dep2[i]==(regmap_pre[i][hr]&63)) nr|=1<<hr; | |
8877 | if(dep2[i]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr; | |
8878 | } | |
b9b61529 | 8879 | if(itype[i]==STORE || itype[i]==STORELR || (opcode[i]&0x3b)==0x39 || (opcode[i]&0x3b)==0x3a) { |
57871462 | 8880 | if(regmap_pre[i][hr]==INVCP) nr|=1<<hr; |
8881 | if(regs[i].regmap_entry[hr]==INVCP) nr|=1<<hr; | |
8882 | } | |
8883 | // Don't store a register immediately after writing it, | |
8884 | // may prevent dual-issue. | |
8885 | // But do so if this is a branch target, otherwise we | |
8886 | // might have to load the register before the branch. | |
8887 | if(i>0&&!bt[i]&&((regs[i].wasdirty>>hr)&1)) { | |
8888 | if((regmap_pre[i][hr]>0&®map_pre[i][hr]<64&&!((unneeded_reg[i]>>regmap_pre[i][hr])&1)) || | |
8889 | (regmap_pre[i][hr]>64&&!((unneeded_reg_upper[i]>>(regmap_pre[i][hr]&63))&1)) ) { | |
8890 | if(rt1[i-1]==(regmap_pre[i][hr]&63)) nr|=1<<hr; | |
8891 | if(rt2[i-1]==(regmap_pre[i][hr]&63)) nr|=1<<hr; | |
8892 | } | |
8893 | if((regs[i].regmap_entry[hr]>0&®s[i].regmap_entry[hr]<64&&!((unneeded_reg[i]>>regs[i].regmap_entry[hr])&1)) || | |
8894 | (regs[i].regmap_entry[hr]>64&&!((unneeded_reg_upper[i]>>(regs[i].regmap_entry[hr]&63))&1)) ) { | |
8895 | if(rt1[i-1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr; | |
8896 | if(rt2[i-1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr; | |
8897 | } | |
8898 | } | |
8899 | } | |
8900 | // Cycle count is needed at branches. Assume it is needed at the target too. | |
8901 | if(i==0||bt[i]||itype[i]==CJUMP||itype[i]==FJUMP||itype[i]==SPAN) { | |
8902 | if(regmap_pre[i][HOST_CCREG]==CCREG) nr|=1<<HOST_CCREG; | |
8903 | if(regs[i].regmap_entry[HOST_CCREG]==CCREG) nr|=1<<HOST_CCREG; | |
8904 | } | |
8905 | // Save it | |
8906 | needed_reg[i]=nr; | |
9f51b4b9 | 8907 | |
57871462 | 8908 | // Deallocate unneeded registers |
8909 | for(hr=0;hr<HOST_REGS;hr++) | |
8910 | { | |
8911 | if(!((nr>>hr)&1)) { | |
8912 | if(regs[i].regmap_entry[hr]!=CCREG) regs[i].regmap_entry[hr]=-1; | |
8913 | if((regs[i].regmap[hr]&63)!=rs1[i] && (regs[i].regmap[hr]&63)!=rs2[i] && | |
8914 | (regs[i].regmap[hr]&63)!=rt1[i] && (regs[i].regmap[hr]&63)!=rt2[i] && | |
8915 | (regs[i].regmap[hr]&63)!=PTEMP && (regs[i].regmap[hr]&63)!=CCREG) | |
8916 | { | |
8917 | if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000) | |
8918 | { | |
8919 | if(likely[i]) { | |
8920 | regs[i].regmap[hr]=-1; | |
8921 | regs[i].isconst&=~(1<<hr); | |
79c75f1b | 8922 | if(i<slen-2) { |
8923 | regmap_pre[i+2][hr]=-1; | |
8924 | regs[i+2].wasconst&=~(1<<hr); | |
8925 | } | |
57871462 | 8926 | } |
8927 | } | |
8928 | } | |
8929 | if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP) | |
8930 | { | |
8931 | int d1=0,d2=0,map=0,temp=0; | |
8932 | if(get_reg(regs[i].regmap,rt1[i+1]|64)>=0||get_reg(branch_regs[i].regmap,rt1[i+1]|64)>=0) | |
8933 | { | |
8934 | d1=dep1[i+1]; | |
8935 | d2=dep2[i+1]; | |
8936 | } | |
b9b61529 | 8937 | if(itype[i+1]==STORE || itype[i+1]==STORELR || |
8938 | (opcode[i+1]&0x3b)==0x39 || (opcode[i+1]&0x3b)==0x3a) { // SWC1/SDC1 || SWC2/SDC2 | |
57871462 | 8939 | map=INVCP; |
8940 | } | |
8941 | if(itype[i+1]==LOADLR || itype[i+1]==STORELR || | |
b9b61529 | 8942 | itype[i+1]==C1LS || itype[i+1]==C2LS) |
57871462 | 8943 | temp=FTEMP; |
8944 | if((regs[i].regmap[hr]&63)!=rs1[i] && (regs[i].regmap[hr]&63)!=rs2[i] && | |
8945 | (regs[i].regmap[hr]&63)!=rt1[i] && (regs[i].regmap[hr]&63)!=rt2[i] && | |
8946 | (regs[i].regmap[hr]&63)!=rt1[i+1] && (regs[i].regmap[hr]&63)!=rt2[i+1] && | |
8947 | (regs[i].regmap[hr]^64)!=us1[i+1] && (regs[i].regmap[hr]^64)!=us2[i+1] && | |
8948 | (regs[i].regmap[hr]^64)!=d1 && (regs[i].regmap[hr]^64)!=d2 && | |
8949 | regs[i].regmap[hr]!=rs1[i+1] && regs[i].regmap[hr]!=rs2[i+1] && | |
8950 | (regs[i].regmap[hr]&63)!=temp && regs[i].regmap[hr]!=PTEMP && | |
8951 | regs[i].regmap[hr]!=RHASH && regs[i].regmap[hr]!=RHTBL && | |
8952 | regs[i].regmap[hr]!=RTEMP && regs[i].regmap[hr]!=CCREG && | |
8953 | regs[i].regmap[hr]!=map ) | |
8954 | { | |
8955 | regs[i].regmap[hr]=-1; | |
8956 | regs[i].isconst&=~(1<<hr); | |
8957 | if((branch_regs[i].regmap[hr]&63)!=rs1[i] && (branch_regs[i].regmap[hr]&63)!=rs2[i] && | |
8958 | (branch_regs[i].regmap[hr]&63)!=rt1[i] && (branch_regs[i].regmap[hr]&63)!=rt2[i] && | |
8959 | (branch_regs[i].regmap[hr]&63)!=rt1[i+1] && (branch_regs[i].regmap[hr]&63)!=rt2[i+1] && | |
8960 | (branch_regs[i].regmap[hr]^64)!=us1[i+1] && (branch_regs[i].regmap[hr]^64)!=us2[i+1] && | |
8961 | (branch_regs[i].regmap[hr]^64)!=d1 && (branch_regs[i].regmap[hr]^64)!=d2 && | |
8962 | branch_regs[i].regmap[hr]!=rs1[i+1] && branch_regs[i].regmap[hr]!=rs2[i+1] && | |
8963 | (branch_regs[i].regmap[hr]&63)!=temp && branch_regs[i].regmap[hr]!=PTEMP && | |
8964 | branch_regs[i].regmap[hr]!=RHASH && branch_regs[i].regmap[hr]!=RHTBL && | |
8965 | branch_regs[i].regmap[hr]!=RTEMP && branch_regs[i].regmap[hr]!=CCREG && | |
8966 | branch_regs[i].regmap[hr]!=map) | |
8967 | { | |
8968 | branch_regs[i].regmap[hr]=-1; | |
8969 | branch_regs[i].regmap_entry[hr]=-1; | |
8970 | if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000) | |
8971 | { | |
8972 | if(!likely[i]&&i<slen-2) { | |
8973 | regmap_pre[i+2][hr]=-1; | |
79c75f1b | 8974 | regs[i+2].wasconst&=~(1<<hr); |
57871462 | 8975 | } |
8976 | } | |
8977 | } | |
8978 | } | |
8979 | } | |
8980 | else | |
8981 | { | |
8982 | // Non-branch | |
8983 | if(i>0) | |
8984 | { | |
8985 | int d1=0,d2=0,map=-1,temp=-1; | |
8986 | if(get_reg(regs[i].regmap,rt1[i]|64)>=0) | |
8987 | { | |
8988 | d1=dep1[i]; | |
8989 | d2=dep2[i]; | |
8990 | } | |
1edfcc68 | 8991 | if(itype[i]==STORE || itype[i]==STORELR || |
b9b61529 | 8992 | (opcode[i]&0x3b)==0x39 || (opcode[i]&0x3b)==0x3a) { // SWC1/SDC1 || SWC2/SDC2 |
57871462 | 8993 | map=INVCP; |
8994 | } | |
8995 | if(itype[i]==LOADLR || itype[i]==STORELR || | |
b9b61529 | 8996 | itype[i]==C1LS || itype[i]==C2LS) |
57871462 | 8997 | temp=FTEMP; |
8998 | if((regs[i].regmap[hr]&63)!=rt1[i] && (regs[i].regmap[hr]&63)!=rt2[i] && | |
8999 | (regs[i].regmap[hr]^64)!=us1[i] && (regs[i].regmap[hr]^64)!=us2[i] && | |
9000 | (regs[i].regmap[hr]^64)!=d1 && (regs[i].regmap[hr]^64)!=d2 && | |
9001 | regs[i].regmap[hr]!=rs1[i] && regs[i].regmap[hr]!=rs2[i] && | |
9002 | (regs[i].regmap[hr]&63)!=temp && regs[i].regmap[hr]!=map && | |
9003 | (itype[i]!=SPAN||regs[i].regmap[hr]!=CCREG)) | |
9004 | { | |
9005 | if(i<slen-1&&!is_ds[i]) { | |
9006 | if(regmap_pre[i+1][hr]!=-1 || regs[i].regmap[hr]!=-1) | |
9007 | if(regmap_pre[i+1][hr]!=regs[i].regmap[hr]) | |
9008 | if(regs[i].regmap[hr]<64||!((regs[i].was32>>(regs[i].regmap[hr]&63))&1)) | |
9009 | { | |
c43b5311 | 9010 | SysPrintf("fail: %x (%d %d!=%d)\n",start+i*4,hr,regmap_pre[i+1][hr],regs[i].regmap[hr]); |
57871462 | 9011 | assert(regmap_pre[i+1][hr]==regs[i].regmap[hr]); |
9012 | } | |
9013 | regmap_pre[i+1][hr]=-1; | |
9014 | if(regs[i+1].regmap_entry[hr]==CCREG) regs[i+1].regmap_entry[hr]=-1; | |
79c75f1b | 9015 | regs[i+1].wasconst&=~(1<<hr); |
57871462 | 9016 | } |
9017 | regs[i].regmap[hr]=-1; | |
9018 | regs[i].isconst&=~(1<<hr); | |
9019 | } | |
9020 | } | |
9021 | } | |
9022 | } | |
9023 | } | |
9024 | } | |
9f51b4b9 | 9025 | |
57871462 | 9026 | /* Pass 5 - Pre-allocate registers */ |
9f51b4b9 | 9027 | |
57871462 | 9028 | // If a register is allocated during a loop, try to allocate it for the |
9029 | // entire loop, if possible. This avoids loading/storing registers | |
9030 | // inside of the loop. | |
9f51b4b9 | 9031 | |
57871462 | 9032 | signed char f_regmap[HOST_REGS]; |
9033 | clear_all_regs(f_regmap); | |
9034 | for(i=0;i<slen-1;i++) | |
9035 | { | |
9036 | if(itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP) | |
9037 | { | |
9f51b4b9 | 9038 | if(ba[i]>=start && ba[i]<(start+i*4)) |
57871462 | 9039 | if(itype[i+1]==NOP||itype[i+1]==MOV||itype[i+1]==ALU |
9040 | ||itype[i+1]==SHIFTIMM||itype[i+1]==IMM16||itype[i+1]==LOAD | |
9041 | ||itype[i+1]==STORE||itype[i+1]==STORELR||itype[i+1]==C1LS | |
9042 | ||itype[i+1]==SHIFT||itype[i+1]==COP1||itype[i+1]==FLOAT | |
b9b61529 | 9043 | ||itype[i+1]==FCOMP||itype[i+1]==FCONV |
9044 | ||itype[i+1]==COP2||itype[i+1]==C2LS||itype[i+1]==C2OP) | |
57871462 | 9045 | { |
9046 | int t=(ba[i]-start)>>2; | |
9047 | if(t>0&&(itype[t-1]!=UJUMP&&itype[t-1]!=RJUMP&&itype[t-1]!=CJUMP&&itype[t-1]!=SJUMP&&itype[t-1]!=FJUMP)) // loop_preload can't handle jumps into delay slots | |
198df76f | 9048 | if(t<2||(itype[t-2]!=UJUMP&&itype[t-2]!=RJUMP)||rt1[t-2]!=31) // call/ret assumes no registers allocated |
57871462 | 9049 | for(hr=0;hr<HOST_REGS;hr++) |
9050 | { | |
9051 | if(regs[i].regmap[hr]>64) { | |
9052 | if(!((regs[i].dirty>>hr)&1)) | |
9053 | f_regmap[hr]=regs[i].regmap[hr]; | |
9054 | else f_regmap[hr]=-1; | |
9055 | } | |
b372a952 | 9056 | else if(regs[i].regmap[hr]>=0) { |
9057 | if(f_regmap[hr]!=regs[i].regmap[hr]) { | |
9058 | // dealloc old register | |
9059 | int n; | |
9060 | for(n=0;n<HOST_REGS;n++) | |
9061 | { | |
9062 | if(f_regmap[n]==regs[i].regmap[hr]) {f_regmap[n]=-1;} | |
9063 | } | |
9064 | // and alloc new one | |
9065 | f_regmap[hr]=regs[i].regmap[hr]; | |
9066 | } | |
9067 | } | |
57871462 | 9068 | if(branch_regs[i].regmap[hr]>64) { |
9069 | if(!((branch_regs[i].dirty>>hr)&1)) | |
9070 | f_regmap[hr]=branch_regs[i].regmap[hr]; | |
9071 | else f_regmap[hr]=-1; | |
9072 | } | |
b372a952 | 9073 | else if(branch_regs[i].regmap[hr]>=0) { |
9074 | if(f_regmap[hr]!=branch_regs[i].regmap[hr]) { | |
9075 | // dealloc old register | |
9076 | int n; | |
9077 | for(n=0;n<HOST_REGS;n++) | |
9078 | { | |
9079 | if(f_regmap[n]==branch_regs[i].regmap[hr]) {f_regmap[n]=-1;} | |
9080 | } | |
9081 | // and alloc new one | |
9082 | f_regmap[hr]=branch_regs[i].regmap[hr]; | |
9083 | } | |
9084 | } | |
e1190b87 | 9085 | if(ooo[i]) { |
9f51b4b9 | 9086 | if(count_free_regs(regs[i].regmap)<=minimum_free_regs[i+1]) |
e1190b87 | 9087 | f_regmap[hr]=branch_regs[i].regmap[hr]; |
9088 | }else{ | |
9f51b4b9 | 9089 | if(count_free_regs(branch_regs[i].regmap)<=minimum_free_regs[i+1]) |
57871462 | 9090 | f_regmap[hr]=branch_regs[i].regmap[hr]; |
9091 | } | |
9092 | // Avoid dirty->clean transition | |
e1190b87 | 9093 | #ifdef DESTRUCTIVE_WRITEBACK |
57871462 | 9094 | if(t>0) if(get_reg(regmap_pre[t],f_regmap[hr])>=0) if((regs[t].wasdirty>>get_reg(regmap_pre[t],f_regmap[hr]))&1) f_regmap[hr]=-1; |
e1190b87 | 9095 | #endif |
9096 | // This check is only strictly required in the DESTRUCTIVE_WRITEBACK | |
9097 | // case above, however it's always a good idea. We can't hoist the | |
9098 | // load if the register was already allocated, so there's no point | |
9099 | // wasting time analyzing most of these cases. It only "succeeds" | |
9100 | // when the mapping was different and the load can be replaced with | |
9101 | // a mov, which is of negligible benefit. So such cases are | |
9102 | // skipped below. | |
57871462 | 9103 | if(f_regmap[hr]>0) { |
198df76f | 9104 | if(regs[t].regmap[hr]==f_regmap[hr]||(regs[t].regmap_entry[hr]<0&&get_reg(regmap_pre[t],f_regmap[hr])<0)) { |
57871462 | 9105 | int r=f_regmap[hr]; |
9106 | for(j=t;j<=i;j++) | |
9107 | { | |
9108 | //printf("Test %x -> %x, %x %d/%d\n",start+i*4,ba[i],start+j*4,hr,r); | |
9109 | if(r<34&&((unneeded_reg[j]>>r)&1)) break; | |
9110 | if(r>63&&((unneeded_reg_upper[j]>>(r&63))&1)) break; | |
9111 | if(r>63) { | |
9112 | // NB This can exclude the case where the upper-half | |
9113 | // register is lower numbered than the lower-half | |
9114 | // register. Not sure if it's worth fixing... | |
9115 | if(get_reg(regs[j].regmap,r&63)<0) break; | |
e1190b87 | 9116 | if(get_reg(regs[j].regmap_entry,r&63)<0) break; |
57871462 | 9117 | if(regs[j].is32&(1LL<<(r&63))) break; |
9118 | } | |
9119 | if(regs[j].regmap[hr]==f_regmap[hr]&&(f_regmap[hr]&63)<TEMPREG) { | |
9120 | //printf("Hit %x -> %x, %x %d/%d\n",start+i*4,ba[i],start+j*4,hr,r); | |
9121 | int k; | |
9122 | if(regs[i].regmap[hr]==-1&&branch_regs[i].regmap[hr]==-1) { | |
9123 | if(get_reg(regs[i+2].regmap,f_regmap[hr])>=0) break; | |
9124 | if(r>63) { | |
9125 | if(get_reg(regs[i].regmap,r&63)<0) break; | |
9126 | if(get_reg(branch_regs[i].regmap,r&63)<0) break; | |
9127 | } | |
9128 | k=i; | |
9129 | while(k>1&®s[k-1].regmap[hr]==-1) { | |
e1190b87 | 9130 | if(count_free_regs(regs[k-1].regmap)<=minimum_free_regs[k-1]) { |
9131 | //printf("no free regs for store %x\n",start+(k-1)*4); | |
9132 | break; | |
57871462 | 9133 | } |
57871462 | 9134 | if(get_reg(regs[k-1].regmap,f_regmap[hr])>=0) { |
9135 | //printf("no-match due to different register\n"); | |
9136 | break; | |
9137 | } | |
9138 | if(itype[k-2]==UJUMP||itype[k-2]==RJUMP||itype[k-2]==CJUMP||itype[k-2]==SJUMP||itype[k-2]==FJUMP) { | |
9139 | //printf("no-match due to branch\n"); | |
9140 | break; | |
9141 | } | |
9142 | // call/ret fast path assumes no registers allocated | |
198df76f | 9143 | if(k>2&&(itype[k-3]==UJUMP||itype[k-3]==RJUMP)&&rt1[k-3]==31) { |
57871462 | 9144 | break; |
9145 | } | |
9146 | if(r>63) { | |
9147 | // NB This can exclude the case where the upper-half | |
9148 | // register is lower numbered than the lower-half | |
9149 | // register. Not sure if it's worth fixing... | |
9150 | if(get_reg(regs[k-1].regmap,r&63)<0) break; | |
9151 | if(regs[k-1].is32&(1LL<<(r&63))) break; | |
9152 | } | |
9153 | k--; | |
9154 | } | |
9155 | if(i<slen-1) { | |
9156 | if((regs[k].is32&(1LL<<f_regmap[hr]))!= | |
9157 | (regs[i+2].was32&(1LL<<f_regmap[hr]))) { | |
9158 | //printf("bad match after branch\n"); | |
9159 | break; | |
9160 | } | |
9161 | } | |
9162 | if(regs[k-1].regmap[hr]==f_regmap[hr]&®map_pre[k][hr]==f_regmap[hr]) { | |
9163 | //printf("Extend r%d, %x ->\n",hr,start+k*4); | |
9164 | while(k<i) { | |
9165 | regs[k].regmap_entry[hr]=f_regmap[hr]; | |
9166 | regs[k].regmap[hr]=f_regmap[hr]; | |
9167 | regmap_pre[k+1][hr]=f_regmap[hr]; | |
9168 | regs[k].wasdirty&=~(1<<hr); | |
9169 | regs[k].dirty&=~(1<<hr); | |
9170 | regs[k].wasdirty|=(1<<hr)®s[k-1].dirty; | |
9171 | regs[k].dirty|=(1<<hr)®s[k].wasdirty; | |
9172 | regs[k].wasconst&=~(1<<hr); | |
9173 | regs[k].isconst&=~(1<<hr); | |
9174 | k++; | |
9175 | } | |
9176 | } | |
9177 | else { | |
9178 | //printf("Fail Extend r%d, %x ->\n",hr,start+k*4); | |
9179 | break; | |
9180 | } | |
9181 | assert(regs[i-1].regmap[hr]==f_regmap[hr]); | |
9182 | if(regs[i-1].regmap[hr]==f_regmap[hr]&®map_pre[i][hr]==f_regmap[hr]) { | |
9183 | //printf("OK fill %x (r%d)\n",start+i*4,hr); | |
9184 | regs[i].regmap_entry[hr]=f_regmap[hr]; | |
9185 | regs[i].regmap[hr]=f_regmap[hr]; | |
9186 | regs[i].wasdirty&=~(1<<hr); | |
9187 | regs[i].dirty&=~(1<<hr); | |
9188 | regs[i].wasdirty|=(1<<hr)®s[i-1].dirty; | |
9189 | regs[i].dirty|=(1<<hr)®s[i-1].dirty; | |
9190 | regs[i].wasconst&=~(1<<hr); | |
9191 | regs[i].isconst&=~(1<<hr); | |
9192 | branch_regs[i].regmap_entry[hr]=f_regmap[hr]; | |
9193 | branch_regs[i].wasdirty&=~(1<<hr); | |
9194 | branch_regs[i].wasdirty|=(1<<hr)®s[i].dirty; | |
9195 | branch_regs[i].regmap[hr]=f_regmap[hr]; | |
9196 | branch_regs[i].dirty&=~(1<<hr); | |
9197 | branch_regs[i].dirty|=(1<<hr)®s[i].dirty; | |
9198 | branch_regs[i].wasconst&=~(1<<hr); | |
9199 | branch_regs[i].isconst&=~(1<<hr); | |
9200 | if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000) { | |
9201 | regmap_pre[i+2][hr]=f_regmap[hr]; | |
9202 | regs[i+2].wasdirty&=~(1<<hr); | |
9203 | regs[i+2].wasdirty|=(1<<hr)®s[i].dirty; | |
9204 | assert((branch_regs[i].is32&(1LL<<f_regmap[hr]))== | |
9205 | (regs[i+2].was32&(1LL<<f_regmap[hr]))); | |
9206 | } | |
9207 | } | |
9208 | } | |
9209 | for(k=t;k<j;k++) { | |
e1190b87 | 9210 | // Alloc register clean at beginning of loop, |
9211 | // but may dirty it in pass 6 | |
57871462 | 9212 | regs[k].regmap_entry[hr]=f_regmap[hr]; |
9213 | regs[k].regmap[hr]=f_regmap[hr]; | |
57871462 | 9214 | regs[k].dirty&=~(1<<hr); |
9215 | regs[k].wasconst&=~(1<<hr); | |
9216 | regs[k].isconst&=~(1<<hr); | |
e1190b87 | 9217 | if(itype[k]==UJUMP||itype[k]==RJUMP||itype[k]==CJUMP||itype[k]==SJUMP||itype[k]==FJUMP) { |
9218 | branch_regs[k].regmap_entry[hr]=f_regmap[hr]; | |
9219 | branch_regs[k].regmap[hr]=f_regmap[hr]; | |
9220 | branch_regs[k].dirty&=~(1<<hr); | |
9221 | branch_regs[k].wasconst&=~(1<<hr); | |
9222 | branch_regs[k].isconst&=~(1<<hr); | |
9223 | if(itype[k]!=RJUMP&&itype[k]!=UJUMP&&(source[k]>>16)!=0x1000) { | |
9224 | regmap_pre[k+2][hr]=f_regmap[hr]; | |
9225 | regs[k+2].wasdirty&=~(1<<hr); | |
9226 | assert((branch_regs[k].is32&(1LL<<f_regmap[hr]))== | |
9227 | (regs[k+2].was32&(1LL<<f_regmap[hr]))); | |
9228 | } | |
9229 | } | |
9230 | else | |
9231 | { | |
9232 | regmap_pre[k+1][hr]=f_regmap[hr]; | |
9233 | regs[k+1].wasdirty&=~(1<<hr); | |
9234 | } | |
57871462 | 9235 | } |
9236 | if(regs[j].regmap[hr]==f_regmap[hr]) | |
9237 | regs[j].regmap_entry[hr]=f_regmap[hr]; | |
9238 | break; | |
9239 | } | |
9240 | if(j==i) break; | |
9241 | if(regs[j].regmap[hr]>=0) | |
9242 | break; | |
9243 | if(get_reg(regs[j].regmap,f_regmap[hr])>=0) { | |
9244 | //printf("no-match due to different register\n"); | |
9245 | break; | |
9246 | } | |
9247 | if((regs[j+1].is32&(1LL<<f_regmap[hr]))!=(regs[j].is32&(1LL<<f_regmap[hr]))) { | |
9248 | //printf("32/64 mismatch %x %d\n",start+j*4,hr); | |
9249 | break; | |
9250 | } | |
e1190b87 | 9251 | if(itype[j]==UJUMP||itype[j]==RJUMP||(source[j]>>16)==0x1000) |
9252 | { | |
9253 | // Stop on unconditional branch | |
9254 | break; | |
9255 | } | |
9256 | if(itype[j]==CJUMP||itype[j]==SJUMP||itype[j]==FJUMP) | |
9257 | { | |
9258 | if(ooo[j]) { | |
9f51b4b9 | 9259 | if(count_free_regs(regs[j].regmap)<=minimum_free_regs[j+1]) |
e1190b87 | 9260 | break; |
9261 | }else{ | |
9f51b4b9 | 9262 | if(count_free_regs(branch_regs[j].regmap)<=minimum_free_regs[j+1]) |
e1190b87 | 9263 | break; |
9264 | } | |
9265 | if(get_reg(branch_regs[j].regmap,f_regmap[hr])>=0) { | |
9266 | //printf("no-match due to different register (branch)\n"); | |
57871462 | 9267 | break; |
9268 | } | |
9269 | } | |
e1190b87 | 9270 | if(count_free_regs(regs[j].regmap)<=minimum_free_regs[j]) { |
9271 | //printf("No free regs for store %x\n",start+j*4); | |
9272 | break; | |
9273 | } | |
57871462 | 9274 | if(f_regmap[hr]>=64) { |
9275 | if(regs[j].is32&(1LL<<(f_regmap[hr]&63))) { | |
9276 | break; | |
9277 | } | |
9278 | else | |
9279 | { | |
9280 | if(get_reg(regs[j].regmap,f_regmap[hr]&63)<0) { | |
9281 | break; | |
9282 | } | |
9283 | } | |
9284 | } | |
9285 | } | |
9286 | } | |
9287 | } | |
9288 | } | |
9289 | } | |
9290 | }else{ | |
198df76f | 9291 | // Non branch or undetermined branch target |
57871462 | 9292 | for(hr=0;hr<HOST_REGS;hr++) |
9293 | { | |
9294 | if(hr!=EXCLUDE_REG) { | |
9295 | if(regs[i].regmap[hr]>64) { | |
9296 | if(!((regs[i].dirty>>hr)&1)) | |
9297 | f_regmap[hr]=regs[i].regmap[hr]; | |
9298 | } | |
b372a952 | 9299 | else if(regs[i].regmap[hr]>=0) { |
9300 | if(f_regmap[hr]!=regs[i].regmap[hr]) { | |
9301 | // dealloc old register | |
9302 | int n; | |
9303 | for(n=0;n<HOST_REGS;n++) | |
9304 | { | |
9305 | if(f_regmap[n]==regs[i].regmap[hr]) {f_regmap[n]=-1;} | |
9306 | } | |
9307 | // and alloc new one | |
9308 | f_regmap[hr]=regs[i].regmap[hr]; | |
9309 | } | |
9310 | } | |
57871462 | 9311 | } |
9312 | } | |
9313 | // Try to restore cycle count at branch targets | |
9314 | if(bt[i]) { | |
9315 | for(j=i;j<slen-1;j++) { | |
9316 | if(regs[j].regmap[HOST_CCREG]!=-1) break; | |
e1190b87 | 9317 | if(count_free_regs(regs[j].regmap)<=minimum_free_regs[j]) { |
9318 | //printf("no free regs for store %x\n",start+j*4); | |
9319 | break; | |
57871462 | 9320 | } |
57871462 | 9321 | } |
9322 | if(regs[j].regmap[HOST_CCREG]==CCREG) { | |
9323 | int k=i; | |
9324 | //printf("Extend CC, %x -> %x\n",start+k*4,start+j*4); | |
9325 | while(k<j) { | |
9326 | regs[k].regmap_entry[HOST_CCREG]=CCREG; | |
9327 | regs[k].regmap[HOST_CCREG]=CCREG; | |
9328 | regmap_pre[k+1][HOST_CCREG]=CCREG; | |
9329 | regs[k+1].wasdirty|=1<<HOST_CCREG; | |
9330 | regs[k].dirty|=1<<HOST_CCREG; | |
9331 | regs[k].wasconst&=~(1<<HOST_CCREG); | |
9332 | regs[k].isconst&=~(1<<HOST_CCREG); | |
9333 | k++; | |
9334 | } | |
9f51b4b9 | 9335 | regs[j].regmap_entry[HOST_CCREG]=CCREG; |
57871462 | 9336 | } |
9337 | // Work backwards from the branch target | |
9338 | if(j>i&&f_regmap[HOST_CCREG]==CCREG) | |
9339 | { | |
9340 | //printf("Extend backwards\n"); | |
9341 | int k; | |
9342 | k=i; | |
9343 | while(regs[k-1].regmap[HOST_CCREG]==-1) { | |
e1190b87 | 9344 | if(count_free_regs(regs[k-1].regmap)<=minimum_free_regs[k-1]) { |
9345 | //printf("no free regs for store %x\n",start+(k-1)*4); | |
9346 | break; | |
57871462 | 9347 | } |
57871462 | 9348 | k--; |
9349 | } | |
9350 | if(regs[k-1].regmap[HOST_CCREG]==CCREG) { | |
9351 | //printf("Extend CC, %x ->\n",start+k*4); | |
9352 | while(k<=i) { | |
9353 | regs[k].regmap_entry[HOST_CCREG]=CCREG; | |
9354 | regs[k].regmap[HOST_CCREG]=CCREG; | |
9355 | regmap_pre[k+1][HOST_CCREG]=CCREG; | |
9356 | regs[k+1].wasdirty|=1<<HOST_CCREG; | |
9357 | regs[k].dirty|=1<<HOST_CCREG; | |
9358 | regs[k].wasconst&=~(1<<HOST_CCREG); | |
9359 | regs[k].isconst&=~(1<<HOST_CCREG); | |
9360 | k++; | |
9361 | } | |
9362 | } | |
9363 | else { | |
9364 | //printf("Fail Extend CC, %x ->\n",start+k*4); | |
9365 | } | |
9366 | } | |
9367 | } | |
9368 | if(itype[i]!=STORE&&itype[i]!=STORELR&&itype[i]!=C1LS&&itype[i]!=SHIFT&& | |
9369 | itype[i]!=NOP&&itype[i]!=MOV&&itype[i]!=ALU&&itype[i]!=SHIFTIMM&& | |
9370 | itype[i]!=IMM16&&itype[i]!=LOAD&&itype[i]!=COP1&&itype[i]!=FLOAT&& | |
e1190b87 | 9371 | itype[i]!=FCONV&&itype[i]!=FCOMP) |
57871462 | 9372 | { |
9373 | memcpy(f_regmap,regs[i].regmap,sizeof(f_regmap)); | |
9374 | } | |
9375 | } | |
9376 | } | |
9f51b4b9 | 9377 | |
d61de97e | 9378 | // Cache memory offset or tlb map pointer if a register is available |
9379 | #ifndef HOST_IMM_ADDR32 | |
9380 | #ifndef RAM_OFFSET | |
1edfcc68 | 9381 | if(0) |
d61de97e | 9382 | #endif |
9383 | { | |
9384 | int earliest_available[HOST_REGS]; | |
9385 | int loop_start[HOST_REGS]; | |
9386 | int score[HOST_REGS]; | |
9387 | int end[HOST_REGS]; | |
1edfcc68 | 9388 | int reg=ROREG; |
d61de97e | 9389 | |
9390 | // Init | |
9391 | for(hr=0;hr<HOST_REGS;hr++) { | |
9392 | score[hr]=0;earliest_available[hr]=0; | |
9393 | loop_start[hr]=MAXBLOCK; | |
9394 | } | |
9395 | for(i=0;i<slen-1;i++) | |
9396 | { | |
9397 | // Can't do anything if no registers are available | |
9398 | if(count_free_regs(regs[i].regmap)<=minimum_free_regs[i]) { | |
9399 | for(hr=0;hr<HOST_REGS;hr++) { | |
9400 | score[hr]=0;earliest_available[hr]=i+1; | |
9401 | loop_start[hr]=MAXBLOCK; | |
9402 | } | |
9403 | } | |
9404 | if(itype[i]==UJUMP||itype[i]==RJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP) { | |
9405 | if(!ooo[i]) { | |
9406 | if(count_free_regs(branch_regs[i].regmap)<=minimum_free_regs[i+1]) { | |
9407 | for(hr=0;hr<HOST_REGS;hr++) { | |
9408 | score[hr]=0;earliest_available[hr]=i+1; | |
9409 | loop_start[hr]=MAXBLOCK; | |
9410 | } | |
9411 | } | |
198df76f | 9412 | }else{ |
9413 | if(count_free_regs(regs[i].regmap)<=minimum_free_regs[i+1]) { | |
9414 | for(hr=0;hr<HOST_REGS;hr++) { | |
9415 | score[hr]=0;earliest_available[hr]=i+1; | |
9416 | loop_start[hr]=MAXBLOCK; | |
9417 | } | |
9418 | } | |
d61de97e | 9419 | } |
9420 | } | |
9421 | // Mark unavailable registers | |
9422 | for(hr=0;hr<HOST_REGS;hr++) { | |
9423 | if(regs[i].regmap[hr]>=0) { | |
9424 | score[hr]=0;earliest_available[hr]=i+1; | |
9425 | loop_start[hr]=MAXBLOCK; | |
9426 | } | |
9427 | if(itype[i]==UJUMP||itype[i]==RJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP) { | |
9428 | if(branch_regs[i].regmap[hr]>=0) { | |
9429 | score[hr]=0;earliest_available[hr]=i+2; | |
9430 | loop_start[hr]=MAXBLOCK; | |
9431 | } | |
9432 | } | |
9433 | } | |
9434 | // No register allocations after unconditional jumps | |
9435 | if(itype[i]==UJUMP||itype[i]==RJUMP||(source[i]>>16)==0x1000) | |
9436 | { | |
9437 | for(hr=0;hr<HOST_REGS;hr++) { | |
9438 | score[hr]=0;earliest_available[hr]=i+2; | |
9439 | loop_start[hr]=MAXBLOCK; | |
9440 | } | |
9441 | i++; // Skip delay slot too | |
9442 | //printf("skip delay slot: %x\n",start+i*4); | |
9443 | } | |
9444 | else | |
9445 | // Possible match | |
9446 | if(itype[i]==LOAD||itype[i]==LOADLR|| | |
9447 | itype[i]==STORE||itype[i]==STORELR||itype[i]==C1LS) { | |
9448 | for(hr=0;hr<HOST_REGS;hr++) { | |
9449 | if(hr!=EXCLUDE_REG) { | |
9450 | end[hr]=i-1; | |
9451 | for(j=i;j<slen-1;j++) { | |
9452 | if(regs[j].regmap[hr]>=0) break; | |
9453 | if(itype[j]==UJUMP||itype[j]==RJUMP||itype[j]==CJUMP||itype[j]==SJUMP||itype[j]==FJUMP) { | |
9454 | if(branch_regs[j].regmap[hr]>=0) break; | |
9455 | if(ooo[j]) { | |
9456 | if(count_free_regs(regs[j].regmap)<=minimum_free_regs[j+1]) break; | |
9457 | }else{ | |
9458 | if(count_free_regs(branch_regs[j].regmap)<=minimum_free_regs[j+1]) break; | |
9459 | } | |
9460 | } | |
9461 | else if(count_free_regs(regs[j].regmap)<=minimum_free_regs[j]) break; | |
9462 | if(itype[j]==UJUMP||itype[j]==RJUMP||itype[j]==CJUMP||itype[j]==SJUMP||itype[j]==FJUMP) { | |
9463 | int t=(ba[j]-start)>>2; | |
9464 | if(t<j&&t>=earliest_available[hr]) { | |
198df76f | 9465 | if(t==1||(t>1&&itype[t-2]!=UJUMP&&itype[t-2]!=RJUMP)||(t>1&&rt1[t-2]!=31)) { // call/ret assumes no registers allocated |
9466 | // Score a point for hoisting loop invariant | |
9467 | if(t<loop_start[hr]) loop_start[hr]=t; | |
9468 | //printf("set loop_start: i=%x j=%x (%x)\n",start+i*4,start+j*4,start+t*4); | |
9469 | score[hr]++; | |
9470 | end[hr]=j; | |
9471 | } | |
d61de97e | 9472 | } |
9473 | else if(t<j) { | |
9474 | if(regs[t].regmap[hr]==reg) { | |
9475 | // Score a point if the branch target matches this register | |
9476 | score[hr]++; | |
9477 | end[hr]=j; | |
9478 | } | |
9479 | } | |
9480 | if(itype[j+1]==LOAD||itype[j+1]==LOADLR|| | |
9481 | itype[j+1]==STORE||itype[j+1]==STORELR||itype[j+1]==C1LS) { | |
9482 | score[hr]++; | |
9483 | end[hr]=j; | |
9484 | } | |
9485 | } | |
9486 | if(itype[j]==UJUMP||itype[j]==RJUMP||(source[j]>>16)==0x1000) | |
9487 | { | |
9488 | // Stop on unconditional branch | |
9489 | break; | |
9490 | } | |
9491 | else | |
9492 | if(itype[j]==LOAD||itype[j]==LOADLR|| | |
9493 | itype[j]==STORE||itype[j]==STORELR||itype[j]==C1LS) { | |
9494 | score[hr]++; | |
9495 | end[hr]=j; | |
9496 | } | |
9497 | } | |
9498 | } | |
9499 | } | |
9500 | // Find highest score and allocate that register | |
9501 | int maxscore=0; | |
9502 | for(hr=0;hr<HOST_REGS;hr++) { | |
9503 | if(hr!=EXCLUDE_REG) { | |
9504 | if(score[hr]>score[maxscore]) { | |
9505 | maxscore=hr; | |
9506 | //printf("highest score: %d %d (%x->%x)\n",score[hr],hr,start+i*4,start+end[hr]*4); | |
9507 | } | |
9508 | } | |
9509 | } | |
9510 | if(score[maxscore]>1) | |
9511 | { | |
9512 | if(i<loop_start[maxscore]) loop_start[maxscore]=i; | |
9513 | for(j=loop_start[maxscore];j<slen&&j<=end[maxscore];j++) { | |
9514 | //if(regs[j].regmap[maxscore]>=0) {printf("oops: %x %x was %d=%d\n",loop_start[maxscore]*4+start,j*4+start,maxscore,regs[j].regmap[maxscore]);} | |
9515 | assert(regs[j].regmap[maxscore]<0); | |
9516 | if(j>loop_start[maxscore]) regs[j].regmap_entry[maxscore]=reg; | |
9517 | regs[j].regmap[maxscore]=reg; | |
9518 | regs[j].dirty&=~(1<<maxscore); | |
9519 | regs[j].wasconst&=~(1<<maxscore); | |
9520 | regs[j].isconst&=~(1<<maxscore); | |
9521 | if(itype[j]==UJUMP||itype[j]==RJUMP||itype[j]==CJUMP||itype[j]==SJUMP||itype[j]==FJUMP) { | |
9522 | branch_regs[j].regmap[maxscore]=reg; | |
9523 | branch_regs[j].wasdirty&=~(1<<maxscore); | |
9524 | branch_regs[j].dirty&=~(1<<maxscore); | |
9525 | branch_regs[j].wasconst&=~(1<<maxscore); | |
9526 | branch_regs[j].isconst&=~(1<<maxscore); | |
9527 | if(itype[j]!=RJUMP&&itype[j]!=UJUMP&&(source[j]>>16)!=0x1000) { | |
9528 | regmap_pre[j+2][maxscore]=reg; | |
9529 | regs[j+2].wasdirty&=~(1<<maxscore); | |
9530 | } | |
9531 | // loop optimization (loop_preload) | |
9532 | int t=(ba[j]-start)>>2; | |
198df76f | 9533 | if(t==loop_start[maxscore]) { |
9534 | if(t==1||(t>1&&itype[t-2]!=UJUMP&&itype[t-2]!=RJUMP)||(t>1&&rt1[t-2]!=31)) // call/ret assumes no registers allocated | |
9535 | regs[t].regmap_entry[maxscore]=reg; | |
9536 | } | |
d61de97e | 9537 | } |
9538 | else | |
9539 | { | |
9540 | if(j<1||(itype[j-1]!=RJUMP&&itype[j-1]!=UJUMP&&itype[j-1]!=CJUMP&&itype[j-1]!=SJUMP&&itype[j-1]!=FJUMP)) { | |
9541 | regmap_pre[j+1][maxscore]=reg; | |
9542 | regs[j+1].wasdirty&=~(1<<maxscore); | |
9543 | } | |
9544 | } | |
9545 | } | |
9546 | i=j-1; | |
9547 | if(itype[j-1]==RJUMP||itype[j-1]==UJUMP||itype[j-1]==CJUMP||itype[j-1]==SJUMP||itype[j-1]==FJUMP) i++; // skip delay slot | |
9548 | for(hr=0;hr<HOST_REGS;hr++) { | |
9549 | score[hr]=0;earliest_available[hr]=i+i; | |
9550 | loop_start[hr]=MAXBLOCK; | |
9551 | } | |
9552 | } | |
9553 | } | |
9554 | } | |
9555 | } | |
9556 | #endif | |
9f51b4b9 | 9557 | |
57871462 | 9558 | // This allocates registers (if possible) one instruction prior |
9559 | // to use, which can avoid a load-use penalty on certain CPUs. | |
9560 | for(i=0;i<slen-1;i++) | |
9561 | { | |
9562 | if(!i||(itype[i-1]!=UJUMP&&itype[i-1]!=CJUMP&&itype[i-1]!=SJUMP&&itype[i-1]!=RJUMP&&itype[i-1]!=FJUMP)) | |
9563 | { | |
9564 | if(!bt[i+1]) | |
9565 | { | |
b9b61529 | 9566 | if(itype[i]==ALU||itype[i]==MOV||itype[i]==LOAD||itype[i]==SHIFTIMM||itype[i]==IMM16 |
9567 | ||((itype[i]==COP1||itype[i]==COP2)&&opcode2[i]<3)) | |
57871462 | 9568 | { |
9569 | if(rs1[i+1]) { | |
9570 | if((hr=get_reg(regs[i+1].regmap,rs1[i+1]))>=0) | |
9571 | { | |
9572 | if(regs[i].regmap[hr]<0&®s[i+1].regmap_entry[hr]<0) | |
9573 | { | |
9574 | regs[i].regmap[hr]=regs[i+1].regmap[hr]; | |
9575 | regmap_pre[i+1][hr]=regs[i+1].regmap[hr]; | |
9576 | regs[i+1].regmap_entry[hr]=regs[i+1].regmap[hr]; | |
9577 | regs[i].isconst&=~(1<<hr); | |
9578 | regs[i].isconst|=regs[i+1].isconst&(1<<hr); | |
9579 | constmap[i][hr]=constmap[i+1][hr]; | |
9580 | regs[i+1].wasdirty&=~(1<<hr); | |
9581 | regs[i].dirty&=~(1<<hr); | |
9582 | } | |
9583 | } | |
9584 | } | |
9585 | if(rs2[i+1]) { | |
9586 | if((hr=get_reg(regs[i+1].regmap,rs2[i+1]))>=0) | |
9587 | { | |
9588 | if(regs[i].regmap[hr]<0&®s[i+1].regmap_entry[hr]<0) | |
9589 | { | |
9590 | regs[i].regmap[hr]=regs[i+1].regmap[hr]; | |
9591 | regmap_pre[i+1][hr]=regs[i+1].regmap[hr]; | |
9592 | regs[i+1].regmap_entry[hr]=regs[i+1].regmap[hr]; | |
9593 | regs[i].isconst&=~(1<<hr); | |
9594 | regs[i].isconst|=regs[i+1].isconst&(1<<hr); | |
9595 | constmap[i][hr]=constmap[i+1][hr]; | |
9596 | regs[i+1].wasdirty&=~(1<<hr); | |
9597 | regs[i].dirty&=~(1<<hr); | |
9598 | } | |
9599 | } | |
9600 | } | |
198df76f | 9601 | // Preload target address for load instruction (non-constant) |
57871462 | 9602 | if(itype[i+1]==LOAD&&rs1[i+1]&&get_reg(regs[i+1].regmap,rs1[i+1])<0) { |
9603 | if((hr=get_reg(regs[i+1].regmap,rt1[i+1]))>=0) | |
9604 | { | |
9605 | if(regs[i].regmap[hr]<0&®s[i+1].regmap_entry[hr]<0) | |
9606 | { | |
9607 | regs[i].regmap[hr]=rs1[i+1]; | |
9608 | regmap_pre[i+1][hr]=rs1[i+1]; | |
9609 | regs[i+1].regmap_entry[hr]=rs1[i+1]; | |
9610 | regs[i].isconst&=~(1<<hr); | |
9611 | regs[i].isconst|=regs[i+1].isconst&(1<<hr); | |
9612 | constmap[i][hr]=constmap[i+1][hr]; | |
9613 | regs[i+1].wasdirty&=~(1<<hr); | |
9614 | regs[i].dirty&=~(1<<hr); | |
9615 | } | |
9616 | } | |
9617 | } | |
9f51b4b9 | 9618 | // Load source into target register |
57871462 | 9619 | if(lt1[i+1]&&get_reg(regs[i+1].regmap,rs1[i+1])<0) { |
9620 | if((hr=get_reg(regs[i+1].regmap,rt1[i+1]))>=0) | |
9621 | { | |
9622 | if(regs[i].regmap[hr]<0&®s[i+1].regmap_entry[hr]<0) | |
9623 | { | |
9624 | regs[i].regmap[hr]=rs1[i+1]; | |
9625 | regmap_pre[i+1][hr]=rs1[i+1]; | |
9626 | regs[i+1].regmap_entry[hr]=rs1[i+1]; | |
9627 | regs[i].isconst&=~(1<<hr); | |
9628 | regs[i].isconst|=regs[i+1].isconst&(1<<hr); | |
9629 | constmap[i][hr]=constmap[i+1][hr]; | |
9630 | regs[i+1].wasdirty&=~(1<<hr); | |
9631 | regs[i].dirty&=~(1<<hr); | |
9632 | } | |
9633 | } | |
9634 | } | |
198df76f | 9635 | // Address for store instruction (non-constant) |
b9b61529 | 9636 | if(itype[i+1]==STORE||itype[i+1]==STORELR |
9637 | ||(opcode[i+1]&0x3b)==0x39||(opcode[i+1]&0x3b)==0x3a) { // SB/SH/SW/SD/SWC1/SDC1/SWC2/SDC2 | |
57871462 | 9638 | if(get_reg(regs[i+1].regmap,rs1[i+1])<0) { |
9639 | hr=get_reg2(regs[i].regmap,regs[i+1].regmap,-1); | |
9640 | if(hr<0) hr=get_reg(regs[i+1].regmap,-1); | |
9641 | else {regs[i+1].regmap[hr]=AGEN1+((i+1)&1);regs[i+1].isconst&=~(1<<hr);} | |
9642 | assert(hr>=0); | |
9643 | if(regs[i].regmap[hr]<0&®s[i+1].regmap_entry[hr]<0) | |
9644 | { | |
9645 | regs[i].regmap[hr]=rs1[i+1]; | |
9646 | regmap_pre[i+1][hr]=rs1[i+1]; | |
9647 | regs[i+1].regmap_entry[hr]=rs1[i+1]; | |
9648 | regs[i].isconst&=~(1<<hr); | |
9649 | regs[i].isconst|=regs[i+1].isconst&(1<<hr); | |
9650 | constmap[i][hr]=constmap[i+1][hr]; | |
9651 | regs[i+1].wasdirty&=~(1<<hr); | |
9652 | regs[i].dirty&=~(1<<hr); | |
9653 | } | |
9654 | } | |
9655 | } | |
b9b61529 | 9656 | if(itype[i+1]==LOADLR||(opcode[i+1]&0x3b)==0x31||(opcode[i+1]&0x3b)==0x32) { // LWC1/LDC1, LWC2/LDC2 |
57871462 | 9657 | if(get_reg(regs[i+1].regmap,rs1[i+1])<0) { |
9658 | int nr; | |
9659 | hr=get_reg(regs[i+1].regmap,FTEMP); | |
9660 | assert(hr>=0); | |
9661 | if(regs[i].regmap[hr]<0&®s[i+1].regmap_entry[hr]<0) | |
9662 | { | |
9663 | regs[i].regmap[hr]=rs1[i+1]; | |
9664 | regmap_pre[i+1][hr]=rs1[i+1]; | |
9665 | regs[i+1].regmap_entry[hr]=rs1[i+1]; | |
9666 | regs[i].isconst&=~(1<<hr); | |
9667 | regs[i].isconst|=regs[i+1].isconst&(1<<hr); | |
9668 | constmap[i][hr]=constmap[i+1][hr]; | |
9669 | regs[i+1].wasdirty&=~(1<<hr); | |
9670 | regs[i].dirty&=~(1<<hr); | |
9671 | } | |
9672 | else if((nr=get_reg2(regs[i].regmap,regs[i+1].regmap,-1))>=0) | |
9673 | { | |
9674 | // move it to another register | |
9675 | regs[i+1].regmap[hr]=-1; | |
9676 | regmap_pre[i+2][hr]=-1; | |
9677 | regs[i+1].regmap[nr]=FTEMP; | |
9678 | regmap_pre[i+2][nr]=FTEMP; | |
9679 | regs[i].regmap[nr]=rs1[i+1]; | |
9680 | regmap_pre[i+1][nr]=rs1[i+1]; | |
9681 | regs[i+1].regmap_entry[nr]=rs1[i+1]; | |
9682 | regs[i].isconst&=~(1<<nr); | |
9683 | regs[i+1].isconst&=~(1<<nr); | |
9684 | regs[i].dirty&=~(1<<nr); | |
9685 | regs[i+1].wasdirty&=~(1<<nr); | |
9686 | regs[i+1].dirty&=~(1<<nr); | |
9687 | regs[i+2].wasdirty&=~(1<<nr); | |
9688 | } | |
9689 | } | |
9690 | } | |
b9b61529 | 9691 | if(itype[i+1]==LOAD||itype[i+1]==LOADLR||itype[i+1]==STORE||itype[i+1]==STORELR/*||itype[i+1]==C1LS||||itype[i+1]==C2LS*/) { |
9f51b4b9 | 9692 | if(itype[i+1]==LOAD) |
57871462 | 9693 | hr=get_reg(regs[i+1].regmap,rt1[i+1]); |
b9b61529 | 9694 | if(itype[i+1]==LOADLR||(opcode[i+1]&0x3b)==0x31||(opcode[i+1]&0x3b)==0x32) // LWC1/LDC1, LWC2/LDC2 |
57871462 | 9695 | hr=get_reg(regs[i+1].regmap,FTEMP); |
b9b61529 | 9696 | if(itype[i+1]==STORE||itype[i+1]==STORELR||(opcode[i+1]&0x3b)==0x39||(opcode[i+1]&0x3b)==0x3a) { // SWC1/SDC1/SWC2/SDC2 |
57871462 | 9697 | hr=get_reg(regs[i+1].regmap,AGEN1+((i+1)&1)); |
9698 | if(hr<0) hr=get_reg(regs[i+1].regmap,-1); | |
9699 | } | |
9700 | if(hr>=0&®s[i].regmap[hr]<0) { | |
9701 | int rs=get_reg(regs[i+1].regmap,rs1[i+1]); | |
9702 | if(rs>=0&&((regs[i+1].wasconst>>rs)&1)) { | |
9703 | regs[i].regmap[hr]=AGEN1+((i+1)&1); | |
9704 | regmap_pre[i+1][hr]=AGEN1+((i+1)&1); | |
9705 | regs[i+1].regmap_entry[hr]=AGEN1+((i+1)&1); | |
9706 | regs[i].isconst&=~(1<<hr); | |
9707 | regs[i+1].wasdirty&=~(1<<hr); | |
9708 | regs[i].dirty&=~(1<<hr); | |
9709 | } | |
9710 | } | |
9711 | } | |
9712 | } | |
9713 | } | |
9714 | } | |
9715 | } | |
9f51b4b9 | 9716 | |
57871462 | 9717 | /* Pass 6 - Optimize clean/dirty state */ |
9718 | clean_registers(0,slen-1,1); | |
9f51b4b9 | 9719 | |
57871462 | 9720 | /* Pass 7 - Identify 32-bit registers */ |
04fd948a | 9721 | for (i=slen-1;i>=0;i--) |
9722 | { | |
9723 | if(itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP) | |
9724 | { | |
9725 | // Conditional branch | |
9726 | if((source[i]>>16)!=0x1000&&i<slen-2) { | |
9727 | // Mark this address as a branch target since it may be called | |
9728 | // upon return from interrupt | |
9729 | bt[i+2]=1; | |
9730 | } | |
9731 | } | |
9732 | } | |
57871462 | 9733 | |
9734 | if(itype[slen-1]==SPAN) { | |
9735 | bt[slen-1]=1; // Mark as a branch target so instruction can restart after exception | |
9736 | } | |
4600ba03 | 9737 | |
9738 | #ifdef DISASM | |
57871462 | 9739 | /* Debug/disassembly */ |
57871462 | 9740 | for(i=0;i<slen;i++) |
9741 | { | |
9742 | printf("U:"); | |
9743 | int r; | |
9744 | for(r=1;r<=CCREG;r++) { | |
9745 | if((unneeded_reg[i]>>r)&1) { | |
9746 | if(r==HIREG) printf(" HI"); | |
9747 | else if(r==LOREG) printf(" LO"); | |
9748 | else printf(" r%d",r); | |
9749 | } | |
9750 | } | |
57871462 | 9751 | printf("\n"); |
9752 | #if defined(__i386__) || defined(__x86_64__) | |
9753 | printf("pre: eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",regmap_pre[i][0],regmap_pre[i][1],regmap_pre[i][2],regmap_pre[i][3],regmap_pre[i][5],regmap_pre[i][6],regmap_pre[i][7]); | |
9754 | #endif | |
9755 | #ifdef __arm__ | |
9756 | printf("pre: r0=%d r1=%d r2=%d r3=%d r4=%d r5=%d r6=%d r7=%d r8=%d r9=%d r10=%d r12=%d\n",regmap_pre[i][0],regmap_pre[i][1],regmap_pre[i][2],regmap_pre[i][3],regmap_pre[i][4],regmap_pre[i][5],regmap_pre[i][6],regmap_pre[i][7],regmap_pre[i][8],regmap_pre[i][9],regmap_pre[i][10],regmap_pre[i][12]); | |
9757 | #endif | |
9758 | printf("needs: "); | |
9759 | if(needed_reg[i]&1) printf("eax "); | |
9760 | if((needed_reg[i]>>1)&1) printf("ecx "); | |
9761 | if((needed_reg[i]>>2)&1) printf("edx "); | |
9762 | if((needed_reg[i]>>3)&1) printf("ebx "); | |
9763 | if((needed_reg[i]>>5)&1) printf("ebp "); | |
9764 | if((needed_reg[i]>>6)&1) printf("esi "); | |
9765 | if((needed_reg[i]>>7)&1) printf("edi "); | |
57871462 | 9766 | printf("\n"); |
57871462 | 9767 | #if defined(__i386__) || defined(__x86_64__) |
9768 | printf("entry: eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",regs[i].regmap_entry[0],regs[i].regmap_entry[1],regs[i].regmap_entry[2],regs[i].regmap_entry[3],regs[i].regmap_entry[5],regs[i].regmap_entry[6],regs[i].regmap_entry[7]); | |
9769 | printf("dirty: "); | |
9770 | if(regs[i].wasdirty&1) printf("eax "); | |
9771 | if((regs[i].wasdirty>>1)&1) printf("ecx "); | |
9772 | if((regs[i].wasdirty>>2)&1) printf("edx "); | |
9773 | if((regs[i].wasdirty>>3)&1) printf("ebx "); | |
9774 | if((regs[i].wasdirty>>5)&1) printf("ebp "); | |
9775 | if((regs[i].wasdirty>>6)&1) printf("esi "); | |
9776 | if((regs[i].wasdirty>>7)&1) printf("edi "); | |
9777 | #endif | |
9778 | #ifdef __arm__ | |
9779 | printf("entry: r0=%d r1=%d r2=%d r3=%d r4=%d r5=%d r6=%d r7=%d r8=%d r9=%d r10=%d r12=%d\n",regs[i].regmap_entry[0],regs[i].regmap_entry[1],regs[i].regmap_entry[2],regs[i].regmap_entry[3],regs[i].regmap_entry[4],regs[i].regmap_entry[5],regs[i].regmap_entry[6],regs[i].regmap_entry[7],regs[i].regmap_entry[8],regs[i].regmap_entry[9],regs[i].regmap_entry[10],regs[i].regmap_entry[12]); | |
9780 | printf("dirty: "); | |
9781 | if(regs[i].wasdirty&1) printf("r0 "); | |
9782 | if((regs[i].wasdirty>>1)&1) printf("r1 "); | |
9783 | if((regs[i].wasdirty>>2)&1) printf("r2 "); | |
9784 | if((regs[i].wasdirty>>3)&1) printf("r3 "); | |
9785 | if((regs[i].wasdirty>>4)&1) printf("r4 "); | |
9786 | if((regs[i].wasdirty>>5)&1) printf("r5 "); | |
9787 | if((regs[i].wasdirty>>6)&1) printf("r6 "); | |
9788 | if((regs[i].wasdirty>>7)&1) printf("r7 "); | |
9789 | if((regs[i].wasdirty>>8)&1) printf("r8 "); | |
9790 | if((regs[i].wasdirty>>9)&1) printf("r9 "); | |
9791 | if((regs[i].wasdirty>>10)&1) printf("r10 "); | |
9792 | if((regs[i].wasdirty>>12)&1) printf("r12 "); | |
9793 | #endif | |
9794 | printf("\n"); | |
9795 | disassemble_inst(i); | |
9796 | //printf ("ccadj[%d] = %d\n",i,ccadj[i]); | |
9797 | #if defined(__i386__) || defined(__x86_64__) | |
9798 | printf("eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d dirty: ",regs[i].regmap[0],regs[i].regmap[1],regs[i].regmap[2],regs[i].regmap[3],regs[i].regmap[5],regs[i].regmap[6],regs[i].regmap[7]); | |
9799 | if(regs[i].dirty&1) printf("eax "); | |
9800 | if((regs[i].dirty>>1)&1) printf("ecx "); | |
9801 | if((regs[i].dirty>>2)&1) printf("edx "); | |
9802 | if((regs[i].dirty>>3)&1) printf("ebx "); | |
9803 | if((regs[i].dirty>>5)&1) printf("ebp "); | |
9804 | if((regs[i].dirty>>6)&1) printf("esi "); | |
9805 | if((regs[i].dirty>>7)&1) printf("edi "); | |
9806 | #endif | |
9807 | #ifdef __arm__ | |
9808 | printf("r0=%d r1=%d r2=%d r3=%d r4=%d r5=%d r6=%d r7=%d r8=%d r9=%d r10=%d r12=%d dirty: ",regs[i].regmap[0],regs[i].regmap[1],regs[i].regmap[2],regs[i].regmap[3],regs[i].regmap[4],regs[i].regmap[5],regs[i].regmap[6],regs[i].regmap[7],regs[i].regmap[8],regs[i].regmap[9],regs[i].regmap[10],regs[i].regmap[12]); | |
9809 | if(regs[i].dirty&1) printf("r0 "); | |
9810 | if((regs[i].dirty>>1)&1) printf("r1 "); | |
9811 | if((regs[i].dirty>>2)&1) printf("r2 "); | |
9812 | if((regs[i].dirty>>3)&1) printf("r3 "); | |
9813 | if((regs[i].dirty>>4)&1) printf("r4 "); | |
9814 | if((regs[i].dirty>>5)&1) printf("r5 "); | |
9815 | if((regs[i].dirty>>6)&1) printf("r6 "); | |
9816 | if((regs[i].dirty>>7)&1) printf("r7 "); | |
9817 | if((regs[i].dirty>>8)&1) printf("r8 "); | |
9818 | if((regs[i].dirty>>9)&1) printf("r9 "); | |
9819 | if((regs[i].dirty>>10)&1) printf("r10 "); | |
9820 | if((regs[i].dirty>>12)&1) printf("r12 "); | |
9821 | #endif | |
9822 | printf("\n"); | |
9823 | if(regs[i].isconst) { | |
9824 | printf("constants: "); | |
9825 | #if defined(__i386__) || defined(__x86_64__) | |
9826 | if(regs[i].isconst&1) printf("eax=%x ",(int)constmap[i][0]); | |
9827 | if((regs[i].isconst>>1)&1) printf("ecx=%x ",(int)constmap[i][1]); | |
9828 | if((regs[i].isconst>>2)&1) printf("edx=%x ",(int)constmap[i][2]); | |
9829 | if((regs[i].isconst>>3)&1) printf("ebx=%x ",(int)constmap[i][3]); | |
9830 | if((regs[i].isconst>>5)&1) printf("ebp=%x ",(int)constmap[i][5]); | |
9831 | if((regs[i].isconst>>6)&1) printf("esi=%x ",(int)constmap[i][6]); | |
9832 | if((regs[i].isconst>>7)&1) printf("edi=%x ",(int)constmap[i][7]); | |
9833 | #endif | |
9834 | #ifdef __arm__ | |
9835 | if(regs[i].isconst&1) printf("r0=%x ",(int)constmap[i][0]); | |
9836 | if((regs[i].isconst>>1)&1) printf("r1=%x ",(int)constmap[i][1]); | |
9837 | if((regs[i].isconst>>2)&1) printf("r2=%x ",(int)constmap[i][2]); | |
9838 | if((regs[i].isconst>>3)&1) printf("r3=%x ",(int)constmap[i][3]); | |
9839 | if((regs[i].isconst>>4)&1) printf("r4=%x ",(int)constmap[i][4]); | |
9840 | if((regs[i].isconst>>5)&1) printf("r5=%x ",(int)constmap[i][5]); | |
9841 | if((regs[i].isconst>>6)&1) printf("r6=%x ",(int)constmap[i][6]); | |
9842 | if((regs[i].isconst>>7)&1) printf("r7=%x ",(int)constmap[i][7]); | |
9843 | if((regs[i].isconst>>8)&1) printf("r8=%x ",(int)constmap[i][8]); | |
9844 | if((regs[i].isconst>>9)&1) printf("r9=%x ",(int)constmap[i][9]); | |
9845 | if((regs[i].isconst>>10)&1) printf("r10=%x ",(int)constmap[i][10]); | |
9846 | if((regs[i].isconst>>12)&1) printf("r12=%x ",(int)constmap[i][12]); | |
9847 | #endif | |
9848 | printf("\n"); | |
9849 | } | |
57871462 | 9850 | if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP) { |
9851 | #if defined(__i386__) || defined(__x86_64__) | |
9852 | printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d dirty: ",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]); | |
9853 | if(branch_regs[i].dirty&1) printf("eax "); | |
9854 | if((branch_regs[i].dirty>>1)&1) printf("ecx "); | |
9855 | if((branch_regs[i].dirty>>2)&1) printf("edx "); | |
9856 | if((branch_regs[i].dirty>>3)&1) printf("ebx "); | |
9857 | if((branch_regs[i].dirty>>5)&1) printf("ebp "); | |
9858 | if((branch_regs[i].dirty>>6)&1) printf("esi "); | |
9859 | if((branch_regs[i].dirty>>7)&1) printf("edi "); | |
9860 | #endif | |
9861 | #ifdef __arm__ | |
9862 | printf("branch(%d): r0=%d r1=%d r2=%d r3=%d r4=%d r5=%d r6=%d r7=%d r8=%d r9=%d r10=%d r12=%d dirty: ",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[4],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7],branch_regs[i].regmap[8],branch_regs[i].regmap[9],branch_regs[i].regmap[10],branch_regs[i].regmap[12]); | |
9863 | if(branch_regs[i].dirty&1) printf("r0 "); | |
9864 | if((branch_regs[i].dirty>>1)&1) printf("r1 "); | |
9865 | if((branch_regs[i].dirty>>2)&1) printf("r2 "); | |
9866 | if((branch_regs[i].dirty>>3)&1) printf("r3 "); | |
9867 | if((branch_regs[i].dirty>>4)&1) printf("r4 "); | |
9868 | if((branch_regs[i].dirty>>5)&1) printf("r5 "); | |
9869 | if((branch_regs[i].dirty>>6)&1) printf("r6 "); | |
9870 | if((branch_regs[i].dirty>>7)&1) printf("r7 "); | |
9871 | if((branch_regs[i].dirty>>8)&1) printf("r8 "); | |
9872 | if((branch_regs[i].dirty>>9)&1) printf("r9 "); | |
9873 | if((branch_regs[i].dirty>>10)&1) printf("r10 "); | |
9874 | if((branch_regs[i].dirty>>12)&1) printf("r12 "); | |
9875 | #endif | |
57871462 | 9876 | } |
9877 | } | |
4600ba03 | 9878 | #endif // DISASM |
57871462 | 9879 | |
9880 | /* Pass 8 - Assembly */ | |
9881 | linkcount=0;stubcount=0; | |
9882 | ds=0;is_delayslot=0; | |
9883 | cop1_usable=0; | |
9884 | uint64_t is32_pre=0; | |
9885 | u_int dirty_pre=0; | |
9886 | u_int beginning=(u_int)out; | |
9887 | if((u_int)addr&1) { | |
9888 | ds=1; | |
9889 | pagespan_ds(); | |
9890 | } | |
9ad4d757 | 9891 | u_int instr_addr0_override=0; |
9892 | ||
9ad4d757 | 9893 | if (start == 0x80030000) { |
9894 | // nasty hack for fastbios thing | |
96186eba | 9895 | // override block entry to this code |
9ad4d757 | 9896 | instr_addr0_override=(u_int)out; |
9897 | emit_movimm(start,0); | |
96186eba | 9898 | // abuse io address var as a flag that we |
9899 | // have already returned here once | |
9900 | emit_readword((int)&address,1); | |
9ad4d757 | 9901 | emit_writeword(0,(int)&pcaddr); |
96186eba | 9902 | emit_writeword(0,(int)&address); |
9ad4d757 | 9903 | emit_cmp(0,1); |
9904 | emit_jne((int)new_dyna_leave); | |
9905 | } | |
57871462 | 9906 | for(i=0;i<slen;i++) |
9907 | { | |
9908 | //if(ds) printf("ds: "); | |
4600ba03 | 9909 | disassemble_inst(i); |
57871462 | 9910 | if(ds) { |
9911 | ds=0; // Skip delay slot | |
9912 | if(bt[i]) assem_debug("OOPS - branch into delay slot\n"); | |
9913 | instr_addr[i]=0; | |
9914 | } else { | |
ffb0b9e0 | 9915 | speculate_register_values(i); |
57871462 | 9916 | #ifndef DESTRUCTIVE_WRITEBACK |
9917 | if(i<2||(itype[i-2]!=UJUMP&&itype[i-2]!=RJUMP&&(source[i-2]>>16)!=0x1000)) | |
9918 | { | |
57871462 | 9919 | wb_valid(regmap_pre[i],regs[i].regmap_entry,dirty_pre,regs[i].wasdirty,is32_pre, |
9920 | unneeded_reg[i],unneeded_reg_upper[i]); | |
9921 | } | |
f776eb14 | 9922 | if((itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)&&!likely[i]) { |
9923 | is32_pre=branch_regs[i].is32; | |
9924 | dirty_pre=branch_regs[i].dirty; | |
9925 | }else{ | |
9926 | is32_pre=regs[i].is32; | |
9927 | dirty_pre=regs[i].dirty; | |
9928 | } | |
57871462 | 9929 | #endif |
9930 | // write back | |
9931 | if(i<2||(itype[i-2]!=UJUMP&&itype[i-2]!=RJUMP&&(source[i-2]>>16)!=0x1000)) | |
9932 | { | |
9933 | wb_invalidate(regmap_pre[i],regs[i].regmap_entry,regs[i].wasdirty,regs[i].was32, | |
9934 | unneeded_reg[i],unneeded_reg_upper[i]); | |
9935 | loop_preload(regmap_pre[i],regs[i].regmap_entry); | |
9936 | } | |
9937 | // branch target entry point | |
9938 | instr_addr[i]=(u_int)out; | |
9939 | assem_debug("<->\n"); | |
9940 | // load regs | |
9941 | if(regs[i].regmap_entry[HOST_CCREG]==CCREG&®s[i].regmap[HOST_CCREG]!=CCREG) | |
9942 | wb_register(CCREG,regs[i].regmap_entry,regs[i].wasdirty,regs[i].was32); | |
9943 | load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,rs1[i],rs2[i]); | |
9944 | address_generation(i,®s[i],regs[i].regmap_entry); | |
9945 | load_consts(regmap_pre[i],regs[i].regmap,regs[i].was32,i); | |
9946 | if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP) | |
9947 | { | |
9948 | // Load the delay slot registers if necessary | |
4ef8f67d | 9949 | if(rs1[i+1]!=rs1[i]&&rs1[i+1]!=rs2[i]&&(rs1[i+1]!=rt1[i]||rt1[i]==0)) |
57871462 | 9950 | load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,rs1[i+1],rs1[i+1]); |
4ef8f67d | 9951 | if(rs2[i+1]!=rs1[i+1]&&rs2[i+1]!=rs1[i]&&rs2[i+1]!=rs2[i]&&(rs2[i+1]!=rt1[i]||rt1[i]==0)) |
57871462 | 9952 | load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,rs2[i+1],rs2[i+1]); |
b9b61529 | 9953 | if(itype[i+1]==STORE||itype[i+1]==STORELR||(opcode[i+1]&0x3b)==0x39||(opcode[i+1]&0x3b)==0x3a) |
57871462 | 9954 | load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,INVCP,INVCP); |
9955 | } | |
9956 | else if(i+1<slen) | |
9957 | { | |
9958 | // Preload registers for following instruction | |
9959 | if(rs1[i+1]!=rs1[i]&&rs1[i+1]!=rs2[i]) | |
9960 | if(rs1[i+1]!=rt1[i]&&rs1[i+1]!=rt2[i]) | |
9961 | load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,rs1[i+1],rs1[i+1]); | |
9962 | if(rs2[i+1]!=rs1[i+1]&&rs2[i+1]!=rs1[i]&&rs2[i+1]!=rs2[i]) | |
9963 | if(rs2[i+1]!=rt1[i]&&rs2[i+1]!=rt2[i]) | |
9964 | load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,rs2[i+1],rs2[i+1]); | |
9965 | } | |
9966 | // TODO: if(is_ooo(i)) address_generation(i+1); | |
9967 | if(itype[i]==CJUMP||itype[i]==FJUMP) | |
9968 | load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,CCREG,CCREG); | |
b9b61529 | 9969 | if(itype[i]==STORE||itype[i]==STORELR||(opcode[i]&0x3b)==0x39||(opcode[i]&0x3b)==0x3a) |
57871462 | 9970 | load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,INVCP,INVCP); |
9971 | if(bt[i]) cop1_usable=0; | |
9972 | // assemble | |
9973 | switch(itype[i]) { | |
9974 | case ALU: | |
9975 | alu_assemble(i,®s[i]);break; | |
9976 | case IMM16: | |
9977 | imm16_assemble(i,®s[i]);break; | |
9978 | case SHIFT: | |
9979 | shift_assemble(i,®s[i]);break; | |
9980 | case SHIFTIMM: | |
9981 | shiftimm_assemble(i,®s[i]);break; | |
9982 | case LOAD: | |
9983 | load_assemble(i,®s[i]);break; | |
9984 | case LOADLR: | |
9985 | loadlr_assemble(i,®s[i]);break; | |
9986 | case STORE: | |
9987 | store_assemble(i,®s[i]);break; | |
9988 | case STORELR: | |
9989 | storelr_assemble(i,®s[i]);break; | |
9990 | case COP0: | |
9991 | cop0_assemble(i,®s[i]);break; | |
9992 | case COP1: | |
9993 | cop1_assemble(i,®s[i]);break; | |
9994 | case C1LS: | |
9995 | c1ls_assemble(i,®s[i]);break; | |
b9b61529 | 9996 | case COP2: |
9997 | cop2_assemble(i,®s[i]);break; | |
9998 | case C2LS: | |
9999 | c2ls_assemble(i,®s[i]);break; | |
10000 | case C2OP: | |
10001 | c2op_assemble(i,®s[i]);break; | |
57871462 | 10002 | case FCONV: |
10003 | fconv_assemble(i,®s[i]);break; | |
10004 | case FLOAT: | |
10005 | float_assemble(i,®s[i]);break; | |
10006 | case FCOMP: | |
10007 | fcomp_assemble(i,®s[i]);break; | |
10008 | case MULTDIV: | |
10009 | multdiv_assemble(i,®s[i]);break; | |
10010 | case MOV: | |
10011 | mov_assemble(i,®s[i]);break; | |
10012 | case SYSCALL: | |
10013 | syscall_assemble(i,®s[i]);break; | |
7139f3c8 | 10014 | case HLECALL: |
10015 | hlecall_assemble(i,®s[i]);break; | |
1e973cb0 | 10016 | case INTCALL: |
10017 | intcall_assemble(i,®s[i]);break; | |
57871462 | 10018 | case UJUMP: |
10019 | ujump_assemble(i,®s[i]);ds=1;break; | |
10020 | case RJUMP: | |
10021 | rjump_assemble(i,®s[i]);ds=1;break; | |
10022 | case CJUMP: | |
10023 | cjump_assemble(i,®s[i]);ds=1;break; | |
10024 | case SJUMP: | |
10025 | sjump_assemble(i,®s[i]);ds=1;break; | |
10026 | case FJUMP: | |
10027 | fjump_assemble(i,®s[i]);ds=1;break; | |
10028 | case SPAN: | |
10029 | pagespan_assemble(i,®s[i]);break; | |
10030 | } | |
10031 | if(itype[i]==UJUMP||itype[i]==RJUMP||(source[i]>>16)==0x1000) | |
10032 | literal_pool(1024); | |
10033 | else | |
10034 | literal_pool_jumpover(256); | |
10035 | } | |
10036 | } | |
10037 | //assert(itype[i-2]==UJUMP||itype[i-2]==RJUMP||(source[i-2]>>16)==0x1000); | |
10038 | // If the block did not end with an unconditional branch, | |
10039 | // add a jump to the next instruction. | |
10040 | if(i>1) { | |
10041 | if(itype[i-2]!=UJUMP&&itype[i-2]!=RJUMP&&(source[i-2]>>16)!=0x1000&&itype[i-1]!=SPAN) { | |
10042 | assert(itype[i-1]!=UJUMP&&itype[i-1]!=CJUMP&&itype[i-1]!=SJUMP&&itype[i-1]!=RJUMP&&itype[i-1]!=FJUMP); | |
10043 | assert(i==slen); | |
10044 | if(itype[i-2]!=CJUMP&&itype[i-2]!=SJUMP&&itype[i-2]!=FJUMP) { | |
10045 | store_regs_bt(regs[i-1].regmap,regs[i-1].is32,regs[i-1].dirty,start+i*4); | |
10046 | if(regs[i-1].regmap[HOST_CCREG]!=CCREG) | |
10047 | emit_loadreg(CCREG,HOST_CCREG); | |
2573466a | 10048 | emit_addimm(HOST_CCREG,CLOCK_ADJUST(ccadj[i-1]+1),HOST_CCREG); |
57871462 | 10049 | } |
10050 | else if(!likely[i-2]) | |
10051 | { | |
10052 | store_regs_bt(branch_regs[i-2].regmap,branch_regs[i-2].is32,branch_regs[i-2].dirty,start+i*4); | |
10053 | assert(branch_regs[i-2].regmap[HOST_CCREG]==CCREG); | |
10054 | } | |
10055 | else | |
10056 | { | |
10057 | store_regs_bt(regs[i-2].regmap,regs[i-2].is32,regs[i-2].dirty,start+i*4); | |
10058 | assert(regs[i-2].regmap[HOST_CCREG]==CCREG); | |
10059 | } | |
10060 | add_to_linker((int)out,start+i*4,0); | |
10061 | emit_jmp(0); | |
10062 | } | |
10063 | } | |
10064 | else | |
10065 | { | |
10066 | assert(i>0); | |
10067 | assert(itype[i-1]!=UJUMP&&itype[i-1]!=CJUMP&&itype[i-1]!=SJUMP&&itype[i-1]!=RJUMP&&itype[i-1]!=FJUMP); | |
10068 | store_regs_bt(regs[i-1].regmap,regs[i-1].is32,regs[i-1].dirty,start+i*4); | |
10069 | if(regs[i-1].regmap[HOST_CCREG]!=CCREG) | |
10070 | emit_loadreg(CCREG,HOST_CCREG); | |
2573466a | 10071 | emit_addimm(HOST_CCREG,CLOCK_ADJUST(ccadj[i-1]+1),HOST_CCREG); |
57871462 | 10072 | add_to_linker((int)out,start+i*4,0); |
10073 | emit_jmp(0); | |
10074 | } | |
10075 | ||
10076 | // TODO: delay slot stubs? | |
10077 | // Stubs | |
10078 | for(i=0;i<stubcount;i++) | |
10079 | { | |
10080 | switch(stubs[i][0]) | |
10081 | { | |
10082 | case LOADB_STUB: | |
10083 | case LOADH_STUB: | |
10084 | case LOADW_STUB: | |
10085 | case LOADD_STUB: | |
10086 | case LOADBU_STUB: | |
10087 | case LOADHU_STUB: | |
10088 | do_readstub(i);break; | |
10089 | case STOREB_STUB: | |
10090 | case STOREH_STUB: | |
10091 | case STOREW_STUB: | |
10092 | case STORED_STUB: | |
10093 | do_writestub(i);break; | |
10094 | case CC_STUB: | |
10095 | do_ccstub(i);break; | |
10096 | case INVCODE_STUB: | |
10097 | do_invstub(i);break; | |
10098 | case FP_STUB: | |
10099 | do_cop1stub(i);break; | |
10100 | case STORELR_STUB: | |
10101 | do_unalignedwritestub(i);break; | |
10102 | } | |
10103 | } | |
10104 | ||
9ad4d757 | 10105 | if (instr_addr0_override) |
10106 | instr_addr[0] = instr_addr0_override; | |
10107 | ||
57871462 | 10108 | /* Pass 9 - Linker */ |
10109 | for(i=0;i<linkcount;i++) | |
10110 | { | |
10111 | assem_debug("%8x -> %8x\n",link_addr[i][0],link_addr[i][1]); | |
10112 | literal_pool(64); | |
10113 | if(!link_addr[i][2]) | |
10114 | { | |
10115 | void *stub=out; | |
10116 | void *addr=check_addr(link_addr[i][1]); | |
10117 | emit_extjump(link_addr[i][0],link_addr[i][1]); | |
10118 | if(addr) { | |
10119 | set_jump_target(link_addr[i][0],(int)addr); | |
10120 | add_link(link_addr[i][1],stub); | |
10121 | } | |
10122 | else set_jump_target(link_addr[i][0],(int)stub); | |
10123 | } | |
10124 | else | |
10125 | { | |
10126 | // Internal branch | |
10127 | int target=(link_addr[i][1]-start)>>2; | |
10128 | assert(target>=0&&target<slen); | |
10129 | assert(instr_addr[target]); | |
10130 | //#ifdef CORTEX_A8_BRANCH_PREDICTION_HACK | |
10131 | //set_jump_target_fillslot(link_addr[i][0],instr_addr[target],link_addr[i][2]>>1); | |
10132 | //#else | |
10133 | set_jump_target(link_addr[i][0],instr_addr[target]); | |
10134 | //#endif | |
10135 | } | |
10136 | } | |
10137 | // External Branch Targets (jump_in) | |
10138 | if(copy+slen*4>(void *)shadow+sizeof(shadow)) copy=shadow; | |
10139 | for(i=0;i<slen;i++) | |
10140 | { | |
10141 | if(bt[i]||i==0) | |
10142 | { | |
10143 | if(instr_addr[i]) // TODO - delay slots (=null) | |
10144 | { | |
10145 | u_int vaddr=start+i*4; | |
94d23bb9 | 10146 | u_int page=get_page(vaddr); |
10147 | u_int vpage=get_vpage(vaddr); | |
57871462 | 10148 | literal_pool(256); |
57871462 | 10149 | { |
10150 | assem_debug("%8x (%d) <- %8x\n",instr_addr[i],i,start+i*4); | |
10151 | assem_debug("jump_in: %x\n",start+i*4); | |
10152 | ll_add(jump_dirty+vpage,vaddr,(void *)out); | |
10153 | int entry_point=do_dirty_stub(i); | |
03f55e6b | 10154 | ll_add_flags(jump_in+page,vaddr,state_rflags,(void *)entry_point); |
57871462 | 10155 | // If there was an existing entry in the hash table, |
10156 | // replace it with the new address. | |
10157 | // Don't add new entries. We'll insert the | |
10158 | // ones that actually get used in check_addr(). | |
581335b0 | 10159 | u_int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF]; |
57871462 | 10160 | if(ht_bin[0]==vaddr) { |
10161 | ht_bin[1]=entry_point; | |
10162 | } | |
10163 | if(ht_bin[2]==vaddr) { | |
10164 | ht_bin[3]=entry_point; | |
10165 | } | |
10166 | } | |
57871462 | 10167 | } |
10168 | } | |
10169 | } | |
10170 | // Write out the literal pool if necessary | |
10171 | literal_pool(0); | |
10172 | #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK | |
10173 | // Align code | |
10174 | if(((u_int)out)&7) emit_addnop(13); | |
10175 | #endif | |
10176 | assert((u_int)out-beginning<MAX_OUTPUT_BLOCK_SIZE); | |
10177 | //printf("shadow buffer: %x-%x\n",(int)copy,(int)copy+slen*4); | |
10178 | memcpy(copy,source,slen*4); | |
10179 | copy+=slen*4; | |
9f51b4b9 | 10180 | |
57871462 | 10181 | #ifdef __arm__ |
10182 | __clear_cache((void *)beginning,out); | |
10183 | #endif | |
9f51b4b9 | 10184 | |
57871462 | 10185 | // If we're within 256K of the end of the buffer, |
10186 | // start over from the beginning. (Is 256K enough?) | |
bdeade46 | 10187 | if((u_int)out>(u_int)BASE_ADDR+(1<<TARGET_SIZE_2)-MAX_OUTPUT_BLOCK_SIZE) out=(u_char *)BASE_ADDR; |
9f51b4b9 | 10188 | |
57871462 | 10189 | // Trap writes to any of the pages we compiled |
10190 | for(i=start>>12;i<=(start+slen*4)>>12;i++) { | |
10191 | invalid_code[i]=0; | |
57871462 | 10192 | } |
9be4ba64 | 10193 | inv_code_start=inv_code_end=~0; |
71e490c5 | 10194 | |
b96d3df7 | 10195 | // for PCSX we need to mark all mirrors too |
b12c9fb8 | 10196 | if(get_page(start)<(RAM_SIZE>>12)) |
10197 | for(i=start>>12;i<=(start+slen*4)>>12;i++) | |
b96d3df7 | 10198 | invalid_code[((u_int)0x00000000>>12)|(i&0x1ff)]= |
10199 | invalid_code[((u_int)0x80000000>>12)|(i&0x1ff)]= | |
10200 | invalid_code[((u_int)0xa0000000>>12)|(i&0x1ff)]=0; | |
9f51b4b9 | 10201 | |
57871462 | 10202 | /* Pass 10 - Free memory by expiring oldest blocks */ |
9f51b4b9 | 10203 | |
bdeade46 | 10204 | int end=((((int)out-(int)BASE_ADDR)>>(TARGET_SIZE_2-16))+16384)&65535; |
57871462 | 10205 | while(expirep!=end) |
10206 | { | |
10207 | int shift=TARGET_SIZE_2-3; // Divide into 8 blocks | |
bdeade46 | 10208 | int base=(int)BASE_ADDR+((expirep>>13)<<shift); // Base address of this block |
57871462 | 10209 | inv_debug("EXP: Phase %d\n",expirep); |
10210 | switch((expirep>>11)&3) | |
10211 | { | |
10212 | case 0: | |
10213 | // Clear jump_in and jump_dirty | |
10214 | ll_remove_matching_addrs(jump_in+(expirep&2047),base,shift); | |
10215 | ll_remove_matching_addrs(jump_dirty+(expirep&2047),base,shift); | |
10216 | ll_remove_matching_addrs(jump_in+2048+(expirep&2047),base,shift); | |
10217 | ll_remove_matching_addrs(jump_dirty+2048+(expirep&2047),base,shift); | |
10218 | break; | |
10219 | case 1: | |
10220 | // Clear pointers | |
10221 | ll_kill_pointers(jump_out[expirep&2047],base,shift); | |
10222 | ll_kill_pointers(jump_out[(expirep&2047)+2048],base,shift); | |
10223 | break; | |
10224 | case 2: | |
10225 | // Clear hash table | |
10226 | for(i=0;i<32;i++) { | |
581335b0 | 10227 | u_int *ht_bin=hash_table[((expirep&2047)<<5)+i]; |
57871462 | 10228 | if((ht_bin[3]>>shift)==(base>>shift) || |
10229 | ((ht_bin[3]-MAX_OUTPUT_BLOCK_SIZE)>>shift)==(base>>shift)) { | |
10230 | inv_debug("EXP: Remove hash %x -> %x\n",ht_bin[2],ht_bin[3]); | |
10231 | ht_bin[2]=ht_bin[3]=-1; | |
10232 | } | |
10233 | if((ht_bin[1]>>shift)==(base>>shift) || | |
10234 | ((ht_bin[1]-MAX_OUTPUT_BLOCK_SIZE)>>shift)==(base>>shift)) { | |
10235 | inv_debug("EXP: Remove hash %x -> %x\n",ht_bin[0],ht_bin[1]); | |
10236 | ht_bin[0]=ht_bin[2]; | |
10237 | ht_bin[1]=ht_bin[3]; | |
10238 | ht_bin[2]=ht_bin[3]=-1; | |
10239 | } | |
10240 | } | |
10241 | break; | |
10242 | case 3: | |
10243 | // Clear jump_out | |
dd3a91a1 | 10244 | #ifdef __arm__ |
9f51b4b9 | 10245 | if((expirep&2047)==0) |
dd3a91a1 | 10246 | do_clear_cache(); |
10247 | #endif | |
57871462 | 10248 | ll_remove_matching_addrs(jump_out+(expirep&2047),base,shift); |
10249 | ll_remove_matching_addrs(jump_out+2048+(expirep&2047),base,shift); | |
10250 | break; | |
10251 | } | |
10252 | expirep=(expirep+1)&65535; | |
10253 | } | |
10254 | return 0; | |
10255 | } | |
b9b61529 | 10256 | |
10257 | // vim:shiftwidth=2:expandtab |