drc: enable and fix warnings
[pcsx_rearmed.git] / libpcsxcore / new_dynarec / new_dynarec.c
CommitLineData
57871462 1/* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
2 * Mupen64plus - new_dynarec.c *
20d507ba 3 * Copyright (C) 2009-2011 Ari64 *
57871462 4 * *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
9 * *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
14 * *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. *
19 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */
20
21#include <stdlib.h>
22#include <stdint.h> //include for uint64_t
23#include <assert.h>
d848b60a 24#include <errno.h>
4600ba03 25#include <sys/mman.h>
57871462 26
3d624f89 27#include "emu_if.h" //emulator interface
57871462 28
4600ba03 29//#define DISASM
30//#define assem_debug printf
31//#define inv_debug printf
32#define assem_debug(...)
33#define inv_debug(...)
57871462 34
35#ifdef __i386__
36#include "assem_x86.h"
37#endif
38#ifdef __x86_64__
39#include "assem_x64.h"
40#endif
41#ifdef __arm__
42#include "assem_arm.h"
43#endif
44
f23d3386 45#ifdef __BLACKBERRY_QNX__
a4874585
C
46#undef __clear_cache
47#define __clear_cache(start,end) msync(start, (size_t)((void*)end - (void*)start), MS_SYNC | MS_CACHE_ONLY | MS_INVALIDATE_ICACHE);
c7b746f0 48#elif defined(__MACH__)
49#include <libkern/OSCacheControl.h>
50#define __clear_cache mach_clear_cache
51static void __clear_cache(void *start, void *end) {
52 size_t len = (char *)end - (char *)start;
53 sys_dcache_flush(start, len);
54 sys_icache_invalidate(start, len);
55}
f23d3386 56#endif
a4874585 57
57871462 58#define MAXBLOCK 4096
59#define MAX_OUTPUT_BLOCK_SIZE 262144
2573466a 60
57871462 61struct regstat
62{
63 signed char regmap_entry[HOST_REGS];
64 signed char regmap[HOST_REGS];
65 uint64_t was32;
66 uint64_t is32;
67 uint64_t wasdirty;
68 uint64_t dirty;
69 uint64_t u;
70 uint64_t uu;
71 u_int wasconst;
72 u_int isconst;
8575a877 73 u_int loadedconst; // host regs that have constants loaded
74 u_int waswritten; // MIPS regs that were used as store base before
57871462 75};
76
de5a60c3 77// note: asm depends on this layout
57871462 78struct ll_entry
79{
80 u_int vaddr;
de5a60c3 81 u_int reg_sv_flags;
57871462 82 void *addr;
83 struct ll_entry *next;
84};
85
e2b5e7aa 86 // used by asm:
87 u_char *out;
88 u_int hash_table[65536][4] __attribute__((aligned(16)));
89 struct ll_entry *jump_in[4096] __attribute__((aligned(16)));
90 struct ll_entry *jump_dirty[4096];
91
92 static struct ll_entry *jump_out[4096];
93 static u_int start;
94 static u_int *source;
95 static char insn[MAXBLOCK][10];
96 static u_char itype[MAXBLOCK];
97 static u_char opcode[MAXBLOCK];
98 static u_char opcode2[MAXBLOCK];
99 static u_char bt[MAXBLOCK];
100 static u_char rs1[MAXBLOCK];
101 static u_char rs2[MAXBLOCK];
102 static u_char rt1[MAXBLOCK];
103 static u_char rt2[MAXBLOCK];
104 static u_char us1[MAXBLOCK];
105 static u_char us2[MAXBLOCK];
106 static u_char dep1[MAXBLOCK];
107 static u_char dep2[MAXBLOCK];
108 static u_char lt1[MAXBLOCK];
bedfea38 109 static uint64_t gte_rs[MAXBLOCK]; // gte: 32 data and 32 ctl regs
110 static uint64_t gte_rt[MAXBLOCK];
111 static uint64_t gte_unneeded[MAXBLOCK];
ffb0b9e0 112 static u_int smrv[32]; // speculated MIPS register values
113 static u_int smrv_strong; // mask or regs that are likely to have correct values
114 static u_int smrv_weak; // same, but somewhat less likely
115 static u_int smrv_strong_next; // same, but after current insn executes
116 static u_int smrv_weak_next;
e2b5e7aa 117 static int imm[MAXBLOCK];
118 static u_int ba[MAXBLOCK];
119 static char likely[MAXBLOCK];
120 static char is_ds[MAXBLOCK];
121 static char ooo[MAXBLOCK];
122 static uint64_t unneeded_reg[MAXBLOCK];
123 static uint64_t unneeded_reg_upper[MAXBLOCK];
124 static uint64_t branch_unneeded_reg[MAXBLOCK];
125 static uint64_t branch_unneeded_reg_upper[MAXBLOCK];
126 static signed char regmap_pre[MAXBLOCK][HOST_REGS];
956f3129 127 static uint64_t current_constmap[HOST_REGS];
128 static uint64_t constmap[MAXBLOCK][HOST_REGS];
129 static struct regstat regs[MAXBLOCK];
130 static struct regstat branch_regs[MAXBLOCK];
e2b5e7aa 131 static signed char minimum_free_regs[MAXBLOCK];
132 static u_int needed_reg[MAXBLOCK];
133 static u_int wont_dirty[MAXBLOCK];
134 static u_int will_dirty[MAXBLOCK];
135 static int ccadj[MAXBLOCK];
136 static int slen;
137 static u_int instr_addr[MAXBLOCK];
138 static u_int link_addr[MAXBLOCK][3];
139 static int linkcount;
140 static u_int stubs[MAXBLOCK*3][8];
141 static int stubcount;
142 static u_int literals[1024][2];
143 static int literalcount;
144 static int is_delayslot;
145 static int cop1_usable;
146 static char shadow[1048576] __attribute__((aligned(16)));
147 static void *copy;
148 static int expirep;
149 static u_int stop_after_jal;
a327ad27 150#ifndef RAM_FIXED
151 static u_int ram_offset;
152#else
153 static const u_int ram_offset=0;
154#endif
e2b5e7aa 155
156 int new_dynarec_hacks;
157 int new_dynarec_did_compile;
57871462 158 extern u_char restore_candidate[512];
159 extern int cycle_count;
160
161 /* registers that may be allocated */
162 /* 1-31 gpr */
163#define HIREG 32 // hi
164#define LOREG 33 // lo
165#define FSREG 34 // FPU status (FCSR)
166#define CSREG 35 // Coprocessor status
167#define CCREG 36 // Cycle count
168#define INVCP 37 // Pointer to invalid_code
1edfcc68 169//#define MMREG 38 // Pointer to memory_map
619e5ded 170#define ROREG 39 // ram offset (if rdram!=0x80000000)
171#define TEMPREG 40
172#define FTEMP 40 // FPU temporary register
173#define PTEMP 41 // Prefetch temporary register
1edfcc68 174//#define TLREG 42 // TLB mapping offset
619e5ded 175#define RHASH 43 // Return address hash
176#define RHTBL 44 // Return address hash table address
177#define RTEMP 45 // JR/JALR address register
178#define MAXREG 45
179#define AGEN1 46 // Address generation temporary register
1edfcc68 180//#define AGEN2 47 // Address generation temporary register
181//#define MGEN1 48 // Maptable address generation temporary register
182//#define MGEN2 49 // Maptable address generation temporary register
619e5ded 183#define BTREG 50 // Branch target temporary register
57871462 184
185 /* instruction types */
186#define NOP 0 // No operation
187#define LOAD 1 // Load
188#define STORE 2 // Store
189#define LOADLR 3 // Unaligned load
190#define STORELR 4 // Unaligned store
9f51b4b9 191#define MOV 5 // Move
57871462 192#define ALU 6 // Arithmetic/logic
193#define MULTDIV 7 // Multiply/divide
194#define SHIFT 8 // Shift by register
195#define SHIFTIMM 9// Shift by immediate
196#define IMM16 10 // 16-bit immediate
197#define RJUMP 11 // Unconditional jump to register
198#define UJUMP 12 // Unconditional jump
199#define CJUMP 13 // Conditional branch (BEQ/BNE/BGTZ/BLEZ)
200#define SJUMP 14 // Conditional branch (regimm format)
201#define COP0 15 // Coprocessor 0
202#define COP1 16 // Coprocessor 1
203#define C1LS 17 // Coprocessor 1 load/store
204#define FJUMP 18 // Conditional branch (floating point)
205#define FLOAT 19 // Floating point unit
206#define FCONV 20 // Convert integer to float
207#define FCOMP 21 // Floating point compare (sets FSREG)
208#define SYSCALL 22// SYSCALL
209#define OTHER 23 // Other
210#define SPAN 24 // Branch/delay slot spans 2 pages
211#define NI 25 // Not implemented
7139f3c8 212#define HLECALL 26// PCSX fake opcodes for HLE
b9b61529 213#define COP2 27 // Coprocessor 2 move
214#define C2LS 28 // Coprocessor 2 load/store
215#define C2OP 29 // Coprocessor 2 operation
1e973cb0 216#define INTCALL 30// Call interpreter to handle rare corner cases
57871462 217
218 /* stubs */
219#define CC_STUB 1
220#define FP_STUB 2
221#define LOADB_STUB 3
222#define LOADH_STUB 4
223#define LOADW_STUB 5
224#define LOADD_STUB 6
225#define LOADBU_STUB 7
226#define LOADHU_STUB 8
227#define STOREB_STUB 9
228#define STOREH_STUB 10
229#define STOREW_STUB 11
230#define STORED_STUB 12
231#define STORELR_STUB 13
232#define INVCODE_STUB 14
233
234 /* branch codes */
235#define TAKEN 1
236#define NOTTAKEN 2
237#define NULLDS 3
238
239// asm linkage
240int new_recompile_block(int addr);
241void *get_addr_ht(u_int vaddr);
242void invalidate_block(u_int block);
243void invalidate_addr(u_int addr);
244void remove_hash(int vaddr);
57871462 245void dyna_linker();
246void dyna_linker_ds();
247void verify_code();
248void verify_code_vm();
249void verify_code_ds();
250void cc_interrupt();
251void fp_exception();
252void fp_exception_ds();
7139f3c8 253void jump_syscall_hle();
7139f3c8 254void jump_hlecall();
1e973cb0 255void jump_intcall();
7139f3c8 256void new_dyna_leave();
57871462 257
57871462 258// Needed by assembler
e2b5e7aa 259static void wb_register(signed char r,signed char regmap[],uint64_t dirty,uint64_t is32);
260static void wb_dirtys(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty);
261static void wb_needed_dirtys(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr);
262static void load_all_regs(signed char i_regmap[]);
263static void load_needed_regs(signed char i_regmap[],signed char next_regmap[]);
264static void load_regs_entry(int t);
265static void load_all_consts(signed char regmap[],int is32,u_int dirty,int i);
266
267static int verify_dirty(u_int *ptr);
268static int get_final_value(int hr, int i, int *value);
269static void add_stub(int type,int addr,int retaddr,int a,int b,int c,int d,int e);
270static void add_to_linker(int addr,int target,int ext);
57871462 271
e2b5e7aa 272static int tracedebug=0;
57871462 273
274//#define DEBUG_CYCLE_COUNT 1
275
b6e87b2b 276#define NO_CYCLE_PENALTY_THR 12
277
4e9dcd7f 278int cycle_multiplier; // 100 for 1.0
279
280static int CLOCK_ADJUST(int x)
281{
282 int s=(x>>31)|1;
283 return (x * cycle_multiplier + s * 50) / 100;
284}
285
94d23bb9 286static u_int get_page(u_int vaddr)
57871462 287{
0ce47d46 288 u_int page=vaddr&~0xe0000000;
289 if (page < 0x1000000)
290 page &= ~0x0e00000; // RAM mirrors
291 page>>=12;
57871462 292 if(page>2048) page=2048+(page&2047);
94d23bb9 293 return page;
294}
295
d25604ca 296// no virtual mem in PCSX
297static u_int get_vpage(u_int vaddr)
298{
299 return get_page(vaddr);
300}
94d23bb9 301
302// Get address from virtual address
303// This is called from the recompiled JR/JALR instructions
304void *get_addr(u_int vaddr)
305{
306 u_int page=get_page(vaddr);
307 u_int vpage=get_vpage(vaddr);
57871462 308 struct ll_entry *head;
309 //printf("TRACE: count=%d next=%d (get_addr %x,page %d)\n",Count,next_interupt,vaddr,page);
310 head=jump_in[page];
311 while(head!=NULL) {
de5a60c3 312 if(head->vaddr==vaddr) {
57871462 313 //printf("TRACE: count=%d next=%d (get_addr match %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr);
581335b0 314 u_int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
57871462 315 ht_bin[3]=ht_bin[1];
316 ht_bin[2]=ht_bin[0];
581335b0 317 ht_bin[1]=(u_int)head->addr;
57871462 318 ht_bin[0]=vaddr;
319 return head->addr;
320 }
321 head=head->next;
322 }
323 head=jump_dirty[vpage];
324 while(head!=NULL) {
de5a60c3 325 if(head->vaddr==vaddr) {
57871462 326 //printf("TRACE: count=%d next=%d (get_addr match dirty %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr);
327 // Don't restore blocks which are about to expire from the cache
328 if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
329 if(verify_dirty(head->addr)) {
330 //printf("restore candidate: %x (%d) d=%d\n",vaddr,page,invalid_code[vaddr>>12]);
331 invalid_code[vaddr>>12]=0;
9be4ba64 332 inv_code_start=inv_code_end=~0;
57871462 333 if(vpage<2048) {
57871462 334 restore_candidate[vpage>>3]|=1<<(vpage&7);
335 }
336 else restore_candidate[page>>3]|=1<<(page&7);
581335b0 337 u_int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
57871462 338 if(ht_bin[0]==vaddr) {
581335b0 339 ht_bin[1]=(u_int)head->addr; // Replace existing entry
57871462 340 }
341 else
342 {
343 ht_bin[3]=ht_bin[1];
344 ht_bin[2]=ht_bin[0];
345 ht_bin[1]=(int)head->addr;
346 ht_bin[0]=vaddr;
347 }
348 return head->addr;
349 }
350 }
351 head=head->next;
352 }
353 //printf("TRACE: count=%d next=%d (get_addr no-match %x)\n",Count,next_interupt,vaddr);
354 int r=new_recompile_block(vaddr);
355 if(r==0) return get_addr(vaddr);
356 // Execute in unmapped page, generate pagefault execption
357 Status|=2;
358 Cause=(vaddr<<31)|0x8;
359 EPC=(vaddr&1)?vaddr-5:vaddr;
360 BadVAddr=(vaddr&~1);
361 Context=(Context&0xFF80000F)|((BadVAddr>>9)&0x007FFFF0);
362 EntryHi=BadVAddr&0xFFFFE000;
363 return get_addr_ht(0x80000000);
364}
365// Look up address in hash table first
366void *get_addr_ht(u_int vaddr)
367{
368 //printf("TRACE: count=%d next=%d (get_addr_ht %x)\n",Count,next_interupt,vaddr);
581335b0 369 u_int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
57871462 370 if(ht_bin[0]==vaddr) return (void *)ht_bin[1];
371 if(ht_bin[2]==vaddr) return (void *)ht_bin[3];
372 return get_addr(vaddr);
373}
374
57871462 375void clear_all_regs(signed char regmap[])
376{
377 int hr;
378 for (hr=0;hr<HOST_REGS;hr++) regmap[hr]=-1;
379}
380
381signed char get_reg(signed char regmap[],int r)
382{
383 int hr;
384 for (hr=0;hr<HOST_REGS;hr++) if(hr!=EXCLUDE_REG&&regmap[hr]==r) return hr;
385 return -1;
386}
387
388// Find a register that is available for two consecutive cycles
389signed char get_reg2(signed char regmap1[],signed char regmap2[],int r)
390{
391 int hr;
392 for (hr=0;hr<HOST_REGS;hr++) if(hr!=EXCLUDE_REG&&regmap1[hr]==r&&regmap2[hr]==r) return hr;
393 return -1;
394}
395
396int count_free_regs(signed char regmap[])
397{
398 int count=0;
399 int hr;
400 for(hr=0;hr<HOST_REGS;hr++)
401 {
402 if(hr!=EXCLUDE_REG) {
403 if(regmap[hr]<0) count++;
404 }
405 }
406 return count;
407}
408
409void dirty_reg(struct regstat *cur,signed char reg)
410{
411 int hr;
412 if(!reg) return;
413 for (hr=0;hr<HOST_REGS;hr++) {
414 if((cur->regmap[hr]&63)==reg) {
415 cur->dirty|=1<<hr;
416 }
417 }
418}
419
420// If we dirty the lower half of a 64 bit register which is now being
421// sign-extended, we need to dump the upper half.
422// Note: Do this only after completion of the instruction, because
423// some instructions may need to read the full 64-bit value even if
424// overwriting it (eg SLTI, DSRA32).
425static void flush_dirty_uppers(struct regstat *cur)
426{
427 int hr,reg;
428 for (hr=0;hr<HOST_REGS;hr++) {
429 if((cur->dirty>>hr)&1) {
430 reg=cur->regmap[hr];
9f51b4b9 431 if(reg>=64)
57871462 432 if((cur->is32>>(reg&63))&1) cur->regmap[hr]=-1;
433 }
434 }
435}
436
437void set_const(struct regstat *cur,signed char reg,uint64_t value)
438{
439 int hr;
440 if(!reg) return;
441 for (hr=0;hr<HOST_REGS;hr++) {
442 if(cur->regmap[hr]==reg) {
443 cur->isconst|=1<<hr;
956f3129 444 current_constmap[hr]=value;
57871462 445 }
446 else if((cur->regmap[hr]^64)==reg) {
447 cur->isconst|=1<<hr;
956f3129 448 current_constmap[hr]=value>>32;
57871462 449 }
450 }
451}
452
453void clear_const(struct regstat *cur,signed char reg)
454{
455 int hr;
456 if(!reg) return;
457 for (hr=0;hr<HOST_REGS;hr++) {
458 if((cur->regmap[hr]&63)==reg) {
459 cur->isconst&=~(1<<hr);
460 }
461 }
462}
463
464int is_const(struct regstat *cur,signed char reg)
465{
466 int hr;
79c75f1b 467 if(reg<0) return 0;
57871462 468 if(!reg) return 1;
469 for (hr=0;hr<HOST_REGS;hr++) {
470 if((cur->regmap[hr]&63)==reg) {
471 return (cur->isconst>>hr)&1;
472 }
473 }
474 return 0;
475}
476uint64_t get_const(struct regstat *cur,signed char reg)
477{
478 int hr;
479 if(!reg) return 0;
480 for (hr=0;hr<HOST_REGS;hr++) {
481 if(cur->regmap[hr]==reg) {
956f3129 482 return current_constmap[hr];
57871462 483 }
484 }
c43b5311 485 SysPrintf("Unknown constant in r%d\n",reg);
57871462 486 exit(1);
487}
488
489// Least soon needed registers
490// Look at the next ten instructions and see which registers
491// will be used. Try not to reallocate these.
492void lsn(u_char hsn[], int i, int *preferred_reg)
493{
494 int j;
495 int b=-1;
496 for(j=0;j<9;j++)
497 {
498 if(i+j>=slen) {
499 j=slen-i-1;
500 break;
501 }
502 if(itype[i+j]==UJUMP||itype[i+j]==RJUMP||(source[i+j]>>16)==0x1000)
503 {
504 // Don't go past an unconditonal jump
505 j++;
506 break;
507 }
508 }
509 for(;j>=0;j--)
510 {
511 if(rs1[i+j]) hsn[rs1[i+j]]=j;
512 if(rs2[i+j]) hsn[rs2[i+j]]=j;
513 if(rt1[i+j]) hsn[rt1[i+j]]=j;
514 if(rt2[i+j]) hsn[rt2[i+j]]=j;
515 if(itype[i+j]==STORE || itype[i+j]==STORELR) {
516 // Stores can allocate zero
517 hsn[rs1[i+j]]=j;
518 hsn[rs2[i+j]]=j;
519 }
520 // On some architectures stores need invc_ptr
521 #if defined(HOST_IMM8)
b9b61529 522 if(itype[i+j]==STORE || itype[i+j]==STORELR || (opcode[i+j]&0x3b)==0x39 || (opcode[i+j]&0x3b)==0x3a) {
57871462 523 hsn[INVCP]=j;
524 }
525 #endif
526 if(i+j>=0&&(itype[i+j]==UJUMP||itype[i+j]==CJUMP||itype[i+j]==SJUMP||itype[i+j]==FJUMP))
527 {
528 hsn[CCREG]=j;
529 b=j;
530 }
531 }
532 if(b>=0)
533 {
534 if(ba[i+b]>=start && ba[i+b]<(start+slen*4))
535 {
536 // Follow first branch
537 int t=(ba[i+b]-start)>>2;
538 j=7-b;if(t+j>=slen) j=slen-t-1;
539 for(;j>=0;j--)
540 {
541 if(rs1[t+j]) if(hsn[rs1[t+j]]>j+b+2) hsn[rs1[t+j]]=j+b+2;
542 if(rs2[t+j]) if(hsn[rs2[t+j]]>j+b+2) hsn[rs2[t+j]]=j+b+2;
543 //if(rt1[t+j]) if(hsn[rt1[t+j]]>j+b+2) hsn[rt1[t+j]]=j+b+2;
544 //if(rt2[t+j]) if(hsn[rt2[t+j]]>j+b+2) hsn[rt2[t+j]]=j+b+2;
545 }
546 }
547 // TODO: preferred register based on backward branch
548 }
549 // Delay slot should preferably not overwrite branch conditions or cycle count
550 if(i>0&&(itype[i-1]==RJUMP||itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP)) {
551 if(rs1[i-1]) if(hsn[rs1[i-1]]>1) hsn[rs1[i-1]]=1;
552 if(rs2[i-1]) if(hsn[rs2[i-1]]>1) hsn[rs2[i-1]]=1;
553 hsn[CCREG]=1;
554 // ...or hash tables
555 hsn[RHASH]=1;
556 hsn[RHTBL]=1;
557 }
558 // Coprocessor load/store needs FTEMP, even if not declared
b9b61529 559 if(itype[i]==C1LS||itype[i]==C2LS) {
57871462 560 hsn[FTEMP]=0;
561 }
562 // Load L/R also uses FTEMP as a temporary register
563 if(itype[i]==LOADLR) {
564 hsn[FTEMP]=0;
565 }
b7918751 566 // Also SWL/SWR/SDL/SDR
567 if(opcode[i]==0x2a||opcode[i]==0x2e||opcode[i]==0x2c||opcode[i]==0x2d) {
57871462 568 hsn[FTEMP]=0;
569 }
57871462 570 // Don't remove the miniht registers
571 if(itype[i]==UJUMP||itype[i]==RJUMP)
572 {
573 hsn[RHASH]=0;
574 hsn[RHTBL]=0;
575 }
576}
577
578// We only want to allocate registers if we're going to use them again soon
579int needed_again(int r, int i)
580{
581 int j;
582 int b=-1;
583 int rn=10;
9f51b4b9 584
57871462 585 if(i>0&&(itype[i-1]==UJUMP||itype[i-1]==RJUMP||(source[i-1]>>16)==0x1000))
586 {
587 if(ba[i-1]<start || ba[i-1]>start+slen*4-4)
588 return 0; // Don't need any registers if exiting the block
589 }
590 for(j=0;j<9;j++)
591 {
592 if(i+j>=slen) {
593 j=slen-i-1;
594 break;
595 }
596 if(itype[i+j]==UJUMP||itype[i+j]==RJUMP||(source[i+j]>>16)==0x1000)
597 {
598 // Don't go past an unconditonal jump
599 j++;
600 break;
601 }
1e973cb0 602 if(itype[i+j]==SYSCALL||itype[i+j]==HLECALL||itype[i+j]==INTCALL||((source[i+j]&0xfc00003f)==0x0d))
57871462 603 {
604 break;
605 }
606 }
607 for(;j>=1;j--)
608 {
609 if(rs1[i+j]==r) rn=j;
610 if(rs2[i+j]==r) rn=j;
611 if((unneeded_reg[i+j]>>r)&1) rn=10;
612 if(i+j>=0&&(itype[i+j]==UJUMP||itype[i+j]==CJUMP||itype[i+j]==SJUMP||itype[i+j]==FJUMP))
613 {
614 b=j;
615 }
616 }
617 /*
618 if(b>=0)
619 {
620 if(ba[i+b]>=start && ba[i+b]<(start+slen*4))
621 {
622 // Follow first branch
623 int o=rn;
624 int t=(ba[i+b]-start)>>2;
625 j=7-b;if(t+j>=slen) j=slen-t-1;
626 for(;j>=0;j--)
627 {
628 if(!((unneeded_reg[t+j]>>r)&1)) {
629 if(rs1[t+j]==r) if(rn>j+b+2) rn=j+b+2;
630 if(rs2[t+j]==r) if(rn>j+b+2) rn=j+b+2;
631 }
632 else rn=o;
633 }
634 }
635 }*/
b7217e13 636 if(rn<10) return 1;
581335b0 637 (void)b;
57871462 638 return 0;
639}
640
641// Try to match register allocations at the end of a loop with those
642// at the beginning
643int loop_reg(int i, int r, int hr)
644{
645 int j,k;
646 for(j=0;j<9;j++)
647 {
648 if(i+j>=slen) {
649 j=slen-i-1;
650 break;
651 }
652 if(itype[i+j]==UJUMP||itype[i+j]==RJUMP||(source[i+j]>>16)==0x1000)
653 {
654 // Don't go past an unconditonal jump
655 j++;
656 break;
657 }
658 }
659 k=0;
660 if(i>0){
661 if(itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP)
662 k--;
663 }
664 for(;k<j;k++)
665 {
666 if(r<64&&((unneeded_reg[i+k]>>r)&1)) return hr;
667 if(r>64&&((unneeded_reg_upper[i+k]>>r)&1)) return hr;
668 if(i+k>=0&&(itype[i+k]==UJUMP||itype[i+k]==CJUMP||itype[i+k]==SJUMP||itype[i+k]==FJUMP))
669 {
670 if(ba[i+k]>=start && ba[i+k]<(start+i*4))
671 {
672 int t=(ba[i+k]-start)>>2;
673 int reg=get_reg(regs[t].regmap_entry,r);
674 if(reg>=0) return reg;
675 //reg=get_reg(regs[t+1].regmap_entry,r);
676 //if(reg>=0) return reg;
677 }
678 }
679 }
680 return hr;
681}
682
683
684// Allocate every register, preserving source/target regs
685void alloc_all(struct regstat *cur,int i)
686{
687 int hr;
9f51b4b9 688
57871462 689 for(hr=0;hr<HOST_REGS;hr++) {
690 if(hr!=EXCLUDE_REG) {
691 if(((cur->regmap[hr]&63)!=rs1[i])&&((cur->regmap[hr]&63)!=rs2[i])&&
692 ((cur->regmap[hr]&63)!=rt1[i])&&((cur->regmap[hr]&63)!=rt2[i]))
693 {
694 cur->regmap[hr]=-1;
695 cur->dirty&=~(1<<hr);
696 }
697 // Don't need zeros
698 if((cur->regmap[hr]&63)==0)
699 {
700 cur->regmap[hr]=-1;
701 cur->dirty&=~(1<<hr);
702 }
703 }
704 }
705}
706
57871462 707#ifdef __i386__
708#include "assem_x86.c"
709#endif
710#ifdef __x86_64__
711#include "assem_x64.c"
712#endif
713#ifdef __arm__
714#include "assem_arm.c"
715#endif
716
717// Add virtual address mapping to linked list
718void ll_add(struct ll_entry **head,int vaddr,void *addr)
719{
720 struct ll_entry *new_entry;
721 new_entry=malloc(sizeof(struct ll_entry));
722 assert(new_entry!=NULL);
723 new_entry->vaddr=vaddr;
de5a60c3 724 new_entry->reg_sv_flags=0;
57871462 725 new_entry->addr=addr;
726 new_entry->next=*head;
727 *head=new_entry;
728}
729
de5a60c3 730void ll_add_flags(struct ll_entry **head,int vaddr,u_int reg_sv_flags,void *addr)
57871462 731{
7139f3c8 732 ll_add(head,vaddr,addr);
de5a60c3 733 (*head)->reg_sv_flags=reg_sv_flags;
57871462 734}
735
736// Check if an address is already compiled
737// but don't return addresses which are about to expire from the cache
738void *check_addr(u_int vaddr)
739{
740 u_int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
741 if(ht_bin[0]==vaddr) {
742 if(((ht_bin[1]-MAX_OUTPUT_BLOCK_SIZE-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
743 if(isclean(ht_bin[1])) return (void *)ht_bin[1];
744 }
745 if(ht_bin[2]==vaddr) {
746 if(((ht_bin[3]-MAX_OUTPUT_BLOCK_SIZE-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
747 if(isclean(ht_bin[3])) return (void *)ht_bin[3];
748 }
94d23bb9 749 u_int page=get_page(vaddr);
57871462 750 struct ll_entry *head;
751 head=jump_in[page];
752 while(head!=NULL) {
de5a60c3 753 if(head->vaddr==vaddr) {
57871462 754 if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2))) {
755 // Update existing entry with current address
756 if(ht_bin[0]==vaddr) {
757 ht_bin[1]=(int)head->addr;
758 return head->addr;
759 }
760 if(ht_bin[2]==vaddr) {
761 ht_bin[3]=(int)head->addr;
762 return head->addr;
763 }
764 // Insert into hash table with low priority.
765 // Don't evict existing entries, as they are probably
766 // addresses that are being accessed frequently.
767 if(ht_bin[0]==-1) {
768 ht_bin[1]=(int)head->addr;
769 ht_bin[0]=vaddr;
770 }else if(ht_bin[2]==-1) {
771 ht_bin[3]=(int)head->addr;
772 ht_bin[2]=vaddr;
773 }
774 return head->addr;
775 }
776 }
777 head=head->next;
778 }
779 return 0;
780}
781
782void remove_hash(int vaddr)
783{
784 //printf("remove hash: %x\n",vaddr);
581335b0 785 u_int *ht_bin=hash_table[(((vaddr)>>16)^vaddr)&0xFFFF];
57871462 786 if(ht_bin[2]==vaddr) {
787 ht_bin[2]=ht_bin[3]=-1;
788 }
789 if(ht_bin[0]==vaddr) {
790 ht_bin[0]=ht_bin[2];
791 ht_bin[1]=ht_bin[3];
792 ht_bin[2]=ht_bin[3]=-1;
793 }
794}
795
796void ll_remove_matching_addrs(struct ll_entry **head,int addr,int shift)
797{
798 struct ll_entry *next;
799 while(*head) {
9f51b4b9 800 if(((u_int)((*head)->addr)>>shift)==(addr>>shift) ||
57871462 801 ((u_int)((*head)->addr-MAX_OUTPUT_BLOCK_SIZE)>>shift)==(addr>>shift))
802 {
803 inv_debug("EXP: Remove pointer to %x (%x)\n",(int)(*head)->addr,(*head)->vaddr);
804 remove_hash((*head)->vaddr);
805 next=(*head)->next;
806 free(*head);
807 *head=next;
808 }
809 else
810 {
811 head=&((*head)->next);
812 }
813 }
814}
815
816// Remove all entries from linked list
817void ll_clear(struct ll_entry **head)
818{
819 struct ll_entry *cur;
820 struct ll_entry *next;
581335b0 821 if((cur=*head)) {
57871462 822 *head=0;
823 while(cur) {
824 next=cur->next;
825 free(cur);
826 cur=next;
827 }
828 }
829}
830
831// Dereference the pointers and remove if it matches
832void ll_kill_pointers(struct ll_entry *head,int addr,int shift)
833{
834 while(head) {
835 int ptr=get_pointer(head->addr);
836 inv_debug("EXP: Lookup pointer to %x at %x (%x)\n",(int)ptr,(int)head->addr,head->vaddr);
837 if(((ptr>>shift)==(addr>>shift)) ||
838 (((ptr-MAX_OUTPUT_BLOCK_SIZE)>>shift)==(addr>>shift)))
839 {
5088bb70 840 inv_debug("EXP: Kill pointer at %x (%x)\n",(int)head->addr,head->vaddr);
f76eeef9 841 u_int host_addr=(u_int)kill_pointer(head->addr);
dd3a91a1 842 #ifdef __arm__
843 needs_clear_cache[(host_addr-(u_int)BASE_ADDR)>>17]|=1<<(((host_addr-(u_int)BASE_ADDR)>>12)&31);
844 #endif
57871462 845 }
846 head=head->next;
847 }
848}
849
850// This is called when we write to a compiled block (see do_invstub)
f76eeef9 851void invalidate_page(u_int page)
57871462 852{
57871462 853 struct ll_entry *head;
854 struct ll_entry *next;
855 head=jump_in[page];
856 jump_in[page]=0;
857 while(head!=NULL) {
858 inv_debug("INVALIDATE: %x\n",head->vaddr);
859 remove_hash(head->vaddr);
860 next=head->next;
861 free(head);
862 head=next;
863 }
864 head=jump_out[page];
865 jump_out[page]=0;
866 while(head!=NULL) {
867 inv_debug("INVALIDATE: kill pointer to %x (%x)\n",head->vaddr,(int)head->addr);
f76eeef9 868 u_int host_addr=(u_int)kill_pointer(head->addr);
dd3a91a1 869 #ifdef __arm__
870 needs_clear_cache[(host_addr-(u_int)BASE_ADDR)>>17]|=1<<(((host_addr-(u_int)BASE_ADDR)>>12)&31);
871 #endif
57871462 872 next=head->next;
873 free(head);
874 head=next;
875 }
57871462 876}
9be4ba64 877
878static void invalidate_block_range(u_int block, u_int first, u_int last)
57871462 879{
94d23bb9 880 u_int page=get_page(block<<12);
57871462 881 //printf("first=%d last=%d\n",first,last);
f76eeef9 882 invalidate_page(page);
57871462 883 assert(first+5>page); // NB: this assumes MAXBLOCK<=4096 (4 pages)
884 assert(last<page+5);
885 // Invalidate the adjacent pages if a block crosses a 4K boundary
886 while(first<page) {
887 invalidate_page(first);
888 first++;
889 }
890 for(first=page+1;first<last;first++) {
891 invalidate_page(first);
892 }
dd3a91a1 893 #ifdef __arm__
894 do_clear_cache();
895 #endif
9f51b4b9 896
57871462 897 // Don't trap writes
898 invalid_code[block]=1;
f76eeef9 899
57871462 900 #ifdef USE_MINI_HT
901 memset(mini_ht,-1,sizeof(mini_ht));
902 #endif
903}
9be4ba64 904
905void invalidate_block(u_int block)
906{
907 u_int page=get_page(block<<12);
908 u_int vpage=get_vpage(block<<12);
909 inv_debug("INVALIDATE: %x (%d)\n",block<<12,page);
910 //inv_debug("invalid_code[block]=%d\n",invalid_code[block]);
911 u_int first,last;
912 first=last=page;
913 struct ll_entry *head;
914 head=jump_dirty[vpage];
915 //printf("page=%d vpage=%d\n",page,vpage);
916 while(head!=NULL) {
917 u_int start,end;
918 if(vpage>2047||(head->vaddr>>12)==block) { // Ignore vaddr hash collision
919 get_bounds((int)head->addr,&start,&end);
920 //printf("start: %x end: %x\n",start,end);
4a35de07 921 if(page<2048&&start>=(u_int)rdram&&end<(u_int)rdram+RAM_SIZE) {
9be4ba64 922 if(((start-(u_int)rdram)>>12)<=page&&((end-1-(u_int)rdram)>>12)>=page) {
923 if((((start-(u_int)rdram)>>12)&2047)<first) first=((start-(u_int)rdram)>>12)&2047;
924 if((((end-1-(u_int)rdram)>>12)&2047)>last) last=((end-1-(u_int)rdram)>>12)&2047;
925 }
926 }
9be4ba64 927 }
928 head=head->next;
929 }
930 invalidate_block_range(block,first,last);
931}
932
57871462 933void invalidate_addr(u_int addr)
934{
9be4ba64 935 //static int rhits;
936 // this check is done by the caller
937 //if (inv_code_start<=addr&&addr<=inv_code_end) { rhits++; return; }
d25604ca 938 u_int page=get_vpage(addr);
9be4ba64 939 if(page<2048) { // RAM
940 struct ll_entry *head;
941 u_int addr_min=~0, addr_max=0;
4a35de07 942 u_int mask=RAM_SIZE-1;
943 u_int addr_main=0x80000000|(addr&mask);
9be4ba64 944 int pg1;
4a35de07 945 inv_code_start=addr_main&~0xfff;
946 inv_code_end=addr_main|0xfff;
9be4ba64 947 pg1=page;
948 if (pg1>0) {
949 // must check previous page too because of spans..
950 pg1--;
951 inv_code_start-=0x1000;
952 }
953 for(;pg1<=page;pg1++) {
954 for(head=jump_dirty[pg1];head!=NULL;head=head->next) {
955 u_int start,end;
956 get_bounds((int)head->addr,&start,&end);
4a35de07 957 if(ram_offset) {
958 start-=ram_offset;
959 end-=ram_offset;
960 }
961 if(start<=addr_main&&addr_main<end) {
9be4ba64 962 if(start<addr_min) addr_min=start;
963 if(end>addr_max) addr_max=end;
964 }
4a35de07 965 else if(addr_main<start) {
9be4ba64 966 if(start<inv_code_end)
967 inv_code_end=start-1;
968 }
969 else {
970 if(end>inv_code_start)
971 inv_code_start=end;
972 }
973 }
974 }
975 if (addr_min!=~0) {
976 inv_debug("INV ADDR: %08x hit %08x-%08x\n", addr, addr_min, addr_max);
977 inv_code_start=inv_code_end=~0;
978 invalidate_block_range(addr>>12,(addr_min&mask)>>12,(addr_max&mask)>>12);
979 return;
980 }
981 else {
4a35de07 982 inv_code_start=(addr&~mask)|(inv_code_start&mask);
983 inv_code_end=(addr&~mask)|(inv_code_end&mask);
d25604ca 984 inv_debug("INV ADDR: %08x miss, inv %08x-%08x, sk %d\n", addr, inv_code_start, inv_code_end, 0);
9be4ba64 985 return;
d25604ca 986 }
9be4ba64 987 }
57871462 988 invalidate_block(addr>>12);
989}
9be4ba64 990
dd3a91a1 991// This is called when loading a save state.
992// Anything could have changed, so invalidate everything.
57871462 993void invalidate_all_pages()
994{
581335b0 995 u_int page;
57871462 996 for(page=0;page<4096;page++)
997 invalidate_page(page);
998 for(page=0;page<1048576;page++)
999 if(!invalid_code[page]) {
1000 restore_candidate[(page&2047)>>3]|=1<<(page&7);
1001 restore_candidate[((page&2047)>>3)+256]|=1<<(page&7);
1002 }
1003 #ifdef __arm__
1004 __clear_cache((void *)BASE_ADDR,(void *)BASE_ADDR+(1<<TARGET_SIZE_2));
1005 #endif
1006 #ifdef USE_MINI_HT
1007 memset(mini_ht,-1,sizeof(mini_ht));
1008 #endif
57871462 1009}
1010
1011// Add an entry to jump_out after making a link
1012void add_link(u_int vaddr,void *src)
1013{
94d23bb9 1014 u_int page=get_page(vaddr);
57871462 1015 inv_debug("add_link: %x -> %x (%d)\n",(int)src,vaddr,page);
76f71c27 1016 int *ptr=(int *)(src+4);
1017 assert((*ptr&0x0fff0000)==0x059f0000);
581335b0 1018 (void)ptr;
57871462 1019 ll_add(jump_out+page,vaddr,src);
1020 //int ptr=get_pointer(src);
1021 //inv_debug("add_link: Pointer is to %x\n",(int)ptr);
1022}
1023
1024// If a code block was found to be unmodified (bit was set in
1025// restore_candidate) and it remains unmodified (bit is clear
1026// in invalid_code) then move the entries for that 4K page from
1027// the dirty list to the clean list.
1028void clean_blocks(u_int page)
1029{
1030 struct ll_entry *head;
1031 inv_debug("INV: clean_blocks page=%d\n",page);
1032 head=jump_dirty[page];
1033 while(head!=NULL) {
1034 if(!invalid_code[head->vaddr>>12]) {
1035 // Don't restore blocks which are about to expire from the cache
1036 if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2))) {
1037 u_int start,end;
581335b0 1038 if(verify_dirty(head->addr)) {
57871462 1039 //printf("Possibly Restore %x (%x)\n",head->vaddr, (int)head->addr);
1040 u_int i;
1041 u_int inv=0;
1042 get_bounds((int)head->addr,&start,&end);
4cb76aa4 1043 if(start-(u_int)rdram<RAM_SIZE) {
57871462 1044 for(i=(start-(u_int)rdram+0x80000000)>>12;i<=(end-1-(u_int)rdram+0x80000000)>>12;i++) {
1045 inv|=invalid_code[i];
1046 }
1047 }
4cb76aa4 1048 else if((signed int)head->vaddr>=(signed int)0x80000000+RAM_SIZE) {
57871462 1049 inv=1;
1050 }
1051 if(!inv) {
1052 void * clean_addr=(void *)get_clean_addr((int)head->addr);
1053 if((((u_int)clean_addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2))) {
1054 u_int ppage=page;
57871462 1055 inv_debug("INV: Restored %x (%x/%x)\n",head->vaddr, (int)head->addr, (int)clean_addr);
1056 //printf("page=%x, addr=%x\n",page,head->vaddr);
1057 //assert(head->vaddr>>12==(page|0x80000));
de5a60c3 1058 ll_add_flags(jump_in+ppage,head->vaddr,head->reg_sv_flags,clean_addr);
581335b0 1059 u_int *ht_bin=hash_table[((head->vaddr>>16)^head->vaddr)&0xFFFF];
de5a60c3 1060 if(ht_bin[0]==head->vaddr) {
581335b0 1061 ht_bin[1]=(u_int)clean_addr; // Replace existing entry
de5a60c3 1062 }
1063 if(ht_bin[2]==head->vaddr) {
581335b0 1064 ht_bin[3]=(u_int)clean_addr; // Replace existing entry
57871462 1065 }
1066 }
1067 }
1068 }
1069 }
1070 }
1071 head=head->next;
1072 }
1073}
1074
1075
1076void mov_alloc(struct regstat *current,int i)
1077{
1078 // Note: Don't need to actually alloc the source registers
1079 if((~current->is32>>rs1[i])&1) {
1080 //alloc_reg64(current,i,rs1[i]);
1081 alloc_reg64(current,i,rt1[i]);
1082 current->is32&=~(1LL<<rt1[i]);
1083 } else {
1084 //alloc_reg(current,i,rs1[i]);
1085 alloc_reg(current,i,rt1[i]);
1086 current->is32|=(1LL<<rt1[i]);
1087 }
1088 clear_const(current,rs1[i]);
1089 clear_const(current,rt1[i]);
1090 dirty_reg(current,rt1[i]);
1091}
1092
1093void shiftimm_alloc(struct regstat *current,int i)
1094{
57871462 1095 if(opcode2[i]<=0x3) // SLL/SRL/SRA
1096 {
1097 if(rt1[i]) {
1098 if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1099 else lt1[i]=rs1[i];
1100 alloc_reg(current,i,rt1[i]);
1101 current->is32|=1LL<<rt1[i];
1102 dirty_reg(current,rt1[i]);
dc49e339 1103 if(is_const(current,rs1[i])) {
1104 int v=get_const(current,rs1[i]);
1105 if(opcode2[i]==0x00) set_const(current,rt1[i],v<<imm[i]);
1106 if(opcode2[i]==0x02) set_const(current,rt1[i],(u_int)v>>imm[i]);
1107 if(opcode2[i]==0x03) set_const(current,rt1[i],v>>imm[i]);
1108 }
1109 else clear_const(current,rt1[i]);
57871462 1110 }
1111 }
dc49e339 1112 else
1113 {
1114 clear_const(current,rs1[i]);
1115 clear_const(current,rt1[i]);
1116 }
1117
57871462 1118 if(opcode2[i]>=0x38&&opcode2[i]<=0x3b) // DSLL/DSRL/DSRA
1119 {
1120 if(rt1[i]) {
1121 if(rs1[i]) alloc_reg64(current,i,rs1[i]);
1122 alloc_reg64(current,i,rt1[i]);
1123 current->is32&=~(1LL<<rt1[i]);
1124 dirty_reg(current,rt1[i]);
1125 }
1126 }
1127 if(opcode2[i]==0x3c) // DSLL32
1128 {
1129 if(rt1[i]) {
1130 if(rs1[i]) alloc_reg(current,i,rs1[i]);
1131 alloc_reg64(current,i,rt1[i]);
1132 current->is32&=~(1LL<<rt1[i]);
1133 dirty_reg(current,rt1[i]);
1134 }
1135 }
1136 if(opcode2[i]==0x3e) // DSRL32
1137 {
1138 if(rt1[i]) {
1139 alloc_reg64(current,i,rs1[i]);
1140 if(imm[i]==32) {
1141 alloc_reg64(current,i,rt1[i]);
1142 current->is32&=~(1LL<<rt1[i]);
1143 } else {
1144 alloc_reg(current,i,rt1[i]);
1145 current->is32|=1LL<<rt1[i];
1146 }
1147 dirty_reg(current,rt1[i]);
1148 }
1149 }
1150 if(opcode2[i]==0x3f) // DSRA32
1151 {
1152 if(rt1[i]) {
1153 alloc_reg64(current,i,rs1[i]);
1154 alloc_reg(current,i,rt1[i]);
1155 current->is32|=1LL<<rt1[i];
1156 dirty_reg(current,rt1[i]);
1157 }
1158 }
1159}
1160
1161void shift_alloc(struct regstat *current,int i)
1162{
1163 if(rt1[i]) {
1164 if(opcode2[i]<=0x07) // SLLV/SRLV/SRAV
1165 {
1166 if(rs1[i]) alloc_reg(current,i,rs1[i]);
1167 if(rs2[i]) alloc_reg(current,i,rs2[i]);
1168 alloc_reg(current,i,rt1[i]);
e1190b87 1169 if(rt1[i]==rs2[i]) {
1170 alloc_reg_temp(current,i,-1);
1171 minimum_free_regs[i]=1;
1172 }
57871462 1173 current->is32|=1LL<<rt1[i];
1174 } else { // DSLLV/DSRLV/DSRAV
1175 if(rs1[i]) alloc_reg64(current,i,rs1[i]);
1176 if(rs2[i]) alloc_reg(current,i,rs2[i]);
1177 alloc_reg64(current,i,rt1[i]);
1178 current->is32&=~(1LL<<rt1[i]);
1179 if(opcode2[i]==0x16||opcode2[i]==0x17) // DSRLV and DSRAV need a temporary register
e1190b87 1180 {
57871462 1181 alloc_reg_temp(current,i,-1);
e1190b87 1182 minimum_free_regs[i]=1;
1183 }
57871462 1184 }
1185 clear_const(current,rs1[i]);
1186 clear_const(current,rs2[i]);
1187 clear_const(current,rt1[i]);
1188 dirty_reg(current,rt1[i]);
1189 }
1190}
1191
1192void alu_alloc(struct regstat *current,int i)
1193{
1194 if(opcode2[i]>=0x20&&opcode2[i]<=0x23) { // ADD/ADDU/SUB/SUBU
1195 if(rt1[i]) {
1196 if(rs1[i]&&rs2[i]) {
1197 alloc_reg(current,i,rs1[i]);
1198 alloc_reg(current,i,rs2[i]);
1199 }
1200 else {
1201 if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1202 if(rs2[i]&&needed_again(rs2[i],i)) alloc_reg(current,i,rs2[i]);
1203 }
1204 alloc_reg(current,i,rt1[i]);
1205 }
1206 current->is32|=1LL<<rt1[i];
1207 }
1208 if(opcode2[i]==0x2a||opcode2[i]==0x2b) { // SLT/SLTU
1209 if(rt1[i]) {
1210 if(!((current->is32>>rs1[i])&(current->is32>>rs2[i])&1))
1211 {
1212 alloc_reg64(current,i,rs1[i]);
1213 alloc_reg64(current,i,rs2[i]);
1214 alloc_reg(current,i,rt1[i]);
1215 } else {
1216 alloc_reg(current,i,rs1[i]);
1217 alloc_reg(current,i,rs2[i]);
1218 alloc_reg(current,i,rt1[i]);
1219 }
1220 }
1221 current->is32|=1LL<<rt1[i];
1222 }
1223 if(opcode2[i]>=0x24&&opcode2[i]<=0x27) { // AND/OR/XOR/NOR
1224 if(rt1[i]) {
1225 if(rs1[i]&&rs2[i]) {
1226 alloc_reg(current,i,rs1[i]);
1227 alloc_reg(current,i,rs2[i]);
1228 }
1229 else
1230 {
1231 if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1232 if(rs2[i]&&needed_again(rs2[i],i)) alloc_reg(current,i,rs2[i]);
1233 }
1234 alloc_reg(current,i,rt1[i]);
1235 if(!((current->is32>>rs1[i])&(current->is32>>rs2[i])&1))
1236 {
1237 if(!((current->uu>>rt1[i])&1)) {
1238 alloc_reg64(current,i,rt1[i]);
1239 }
1240 if(get_reg(current->regmap,rt1[i]|64)>=0) {
1241 if(rs1[i]&&rs2[i]) {
1242 alloc_reg64(current,i,rs1[i]);
1243 alloc_reg64(current,i,rs2[i]);
1244 }
1245 else
1246 {
1247 // Is is really worth it to keep 64-bit values in registers?
1248 #ifdef NATIVE_64BIT
1249 if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg64(current,i,rs1[i]);
1250 if(rs2[i]&&needed_again(rs2[i],i)) alloc_reg64(current,i,rs2[i]);
1251 #endif
1252 }
1253 }
1254 current->is32&=~(1LL<<rt1[i]);
1255 } else {
1256 current->is32|=1LL<<rt1[i];
1257 }
1258 }
1259 }
1260 if(opcode2[i]>=0x2c&&opcode2[i]<=0x2f) { // DADD/DADDU/DSUB/DSUBU
1261 if(rt1[i]) {
1262 if(rs1[i]&&rs2[i]) {
1263 if(!((current->uu>>rt1[i])&1)||get_reg(current->regmap,rt1[i]|64)>=0) {
1264 alloc_reg64(current,i,rs1[i]);
1265 alloc_reg64(current,i,rs2[i]);
1266 alloc_reg64(current,i,rt1[i]);
1267 } else {
1268 alloc_reg(current,i,rs1[i]);
1269 alloc_reg(current,i,rs2[i]);
1270 alloc_reg(current,i,rt1[i]);
1271 }
1272 }
1273 else {
1274 alloc_reg(current,i,rt1[i]);
1275 if(!((current->uu>>rt1[i])&1)||get_reg(current->regmap,rt1[i]|64)>=0) {
1276 // DADD used as move, or zeroing
1277 // If we have a 64-bit source, then make the target 64 bits too
1278 if(rs1[i]&&!((current->is32>>rs1[i])&1)) {
1279 if(get_reg(current->regmap,rs1[i])>=0) alloc_reg64(current,i,rs1[i]);
1280 alloc_reg64(current,i,rt1[i]);
1281 } else if(rs2[i]&&!((current->is32>>rs2[i])&1)) {
1282 if(get_reg(current->regmap,rs2[i])>=0) alloc_reg64(current,i,rs2[i]);
1283 alloc_reg64(current,i,rt1[i]);
1284 }
1285 if(opcode2[i]>=0x2e&&rs2[i]) {
1286 // DSUB used as negation - 64-bit result
1287 // If we have a 32-bit register, extend it to 64 bits
1288 if(get_reg(current->regmap,rs2[i])>=0) alloc_reg64(current,i,rs2[i]);
1289 alloc_reg64(current,i,rt1[i]);
1290 }
1291 }
1292 }
1293 if(rs1[i]&&rs2[i]) {
1294 current->is32&=~(1LL<<rt1[i]);
1295 } else if(rs1[i]) {
1296 current->is32&=~(1LL<<rt1[i]);
1297 if((current->is32>>rs1[i])&1)
1298 current->is32|=1LL<<rt1[i];
1299 } else if(rs2[i]) {
1300 current->is32&=~(1LL<<rt1[i]);
1301 if((current->is32>>rs2[i])&1)
1302 current->is32|=1LL<<rt1[i];
1303 } else {
1304 current->is32|=1LL<<rt1[i];
1305 }
1306 }
1307 }
1308 clear_const(current,rs1[i]);
1309 clear_const(current,rs2[i]);
1310 clear_const(current,rt1[i]);
1311 dirty_reg(current,rt1[i]);
1312}
1313
1314void imm16_alloc(struct regstat *current,int i)
1315{
1316 if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1317 else lt1[i]=rs1[i];
1318 if(rt1[i]) alloc_reg(current,i,rt1[i]);
1319 if(opcode[i]==0x18||opcode[i]==0x19) { // DADDI/DADDIU
1320 current->is32&=~(1LL<<rt1[i]);
1321 if(!((current->uu>>rt1[i])&1)||get_reg(current->regmap,rt1[i]|64)>=0) {
1322 // TODO: Could preserve the 32-bit flag if the immediate is zero
1323 alloc_reg64(current,i,rt1[i]);
1324 alloc_reg64(current,i,rs1[i]);
1325 }
1326 clear_const(current,rs1[i]);
1327 clear_const(current,rt1[i]);
1328 }
1329 else if(opcode[i]==0x0a||opcode[i]==0x0b) { // SLTI/SLTIU
1330 if((~current->is32>>rs1[i])&1) alloc_reg64(current,i,rs1[i]);
1331 current->is32|=1LL<<rt1[i];
1332 clear_const(current,rs1[i]);
1333 clear_const(current,rt1[i]);
1334 }
1335 else if(opcode[i]>=0x0c&&opcode[i]<=0x0e) { // ANDI/ORI/XORI
1336 if(((~current->is32>>rs1[i])&1)&&opcode[i]>0x0c) {
1337 if(rs1[i]!=rt1[i]) {
1338 if(needed_again(rs1[i],i)) alloc_reg64(current,i,rs1[i]);
1339 alloc_reg64(current,i,rt1[i]);
1340 current->is32&=~(1LL<<rt1[i]);
1341 }
1342 }
1343 else current->is32|=1LL<<rt1[i]; // ANDI clears upper bits
1344 if(is_const(current,rs1[i])) {
1345 int v=get_const(current,rs1[i]);
1346 if(opcode[i]==0x0c) set_const(current,rt1[i],v&imm[i]);
1347 if(opcode[i]==0x0d) set_const(current,rt1[i],v|imm[i]);
1348 if(opcode[i]==0x0e) set_const(current,rt1[i],v^imm[i]);
1349 }
1350 else clear_const(current,rt1[i]);
1351 }
1352 else if(opcode[i]==0x08||opcode[i]==0x09) { // ADDI/ADDIU
1353 if(is_const(current,rs1[i])) {
1354 int v=get_const(current,rs1[i]);
1355 set_const(current,rt1[i],v+imm[i]);
1356 }
1357 else clear_const(current,rt1[i]);
1358 current->is32|=1LL<<rt1[i];
1359 }
1360 else {
1361 set_const(current,rt1[i],((long long)((short)imm[i]))<<16); // LUI
1362 current->is32|=1LL<<rt1[i];
1363 }
1364 dirty_reg(current,rt1[i]);
1365}
1366
1367void load_alloc(struct regstat *current,int i)
1368{
1369 clear_const(current,rt1[i]);
1370 //if(rs1[i]!=rt1[i]&&needed_again(rs1[i],i)) clear_const(current,rs1[i]); // Does this help or hurt?
1371 if(!rs1[i]) current->u&=~1LL; // Allow allocating r0 if it's the source register
1372 if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
373d1d07 1373 if(rt1[i]&&!((current->u>>rt1[i])&1)) {
57871462 1374 alloc_reg(current,i,rt1[i]);
373d1d07 1375 assert(get_reg(current->regmap,rt1[i])>=0);
57871462 1376 if(opcode[i]==0x27||opcode[i]==0x37) // LWU/LD
1377 {
1378 current->is32&=~(1LL<<rt1[i]);
1379 alloc_reg64(current,i,rt1[i]);
1380 }
1381 else if(opcode[i]==0x1A||opcode[i]==0x1B) // LDL/LDR
1382 {
1383 current->is32&=~(1LL<<rt1[i]);
1384 alloc_reg64(current,i,rt1[i]);
1385 alloc_all(current,i);
1386 alloc_reg64(current,i,FTEMP);
e1190b87 1387 minimum_free_regs[i]=HOST_REGS;
57871462 1388 }
1389 else current->is32|=1LL<<rt1[i];
1390 dirty_reg(current,rt1[i]);
57871462 1391 // LWL/LWR need a temporary register for the old value
1392 if(opcode[i]==0x22||opcode[i]==0x26)
1393 {
1394 alloc_reg(current,i,FTEMP);
1395 alloc_reg_temp(current,i,-1);
e1190b87 1396 minimum_free_regs[i]=1;
57871462 1397 }
1398 }
1399 else
1400 {
373d1d07 1401 // Load to r0 or unneeded register (dummy load)
57871462 1402 // but we still need a register to calculate the address
535d208a 1403 if(opcode[i]==0x22||opcode[i]==0x26)
1404 {
1405 alloc_reg(current,i,FTEMP); // LWL/LWR need another temporary
1406 }
57871462 1407 alloc_reg_temp(current,i,-1);
e1190b87 1408 minimum_free_regs[i]=1;
535d208a 1409 if(opcode[i]==0x1A||opcode[i]==0x1B) // LDL/LDR
1410 {
1411 alloc_all(current,i);
1412 alloc_reg64(current,i,FTEMP);
e1190b87 1413 minimum_free_regs[i]=HOST_REGS;
535d208a 1414 }
57871462 1415 }
1416}
1417
1418void store_alloc(struct regstat *current,int i)
1419{
1420 clear_const(current,rs2[i]);
1421 if(!(rs2[i])) current->u&=~1LL; // Allow allocating r0 if necessary
1422 if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1423 alloc_reg(current,i,rs2[i]);
1424 if(opcode[i]==0x2c||opcode[i]==0x2d||opcode[i]==0x3f) { // 64-bit SDL/SDR/SD
1425 alloc_reg64(current,i,rs2[i]);
1426 if(rs2[i]) alloc_reg(current,i,FTEMP);
1427 }
57871462 1428 #if defined(HOST_IMM8)
1429 // On CPUs without 32-bit immediates we need a pointer to invalid_code
1430 else alloc_reg(current,i,INVCP);
1431 #endif
b7918751 1432 if(opcode[i]==0x2a||opcode[i]==0x2e||opcode[i]==0x2c||opcode[i]==0x2d) { // SWL/SWL/SDL/SDR
57871462 1433 alloc_reg(current,i,FTEMP);
1434 }
1435 // We need a temporary register for address generation
1436 alloc_reg_temp(current,i,-1);
e1190b87 1437 minimum_free_regs[i]=1;
57871462 1438}
1439
1440void c1ls_alloc(struct regstat *current,int i)
1441{
1442 //clear_const(current,rs1[i]); // FIXME
1443 clear_const(current,rt1[i]);
1444 if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1445 alloc_reg(current,i,CSREG); // Status
1446 alloc_reg(current,i,FTEMP);
1447 if(opcode[i]==0x35||opcode[i]==0x3d) { // 64-bit LDC1/SDC1
1448 alloc_reg64(current,i,FTEMP);
1449 }
57871462 1450 #if defined(HOST_IMM8)
1451 // On CPUs without 32-bit immediates we need a pointer to invalid_code
1452 else if((opcode[i]&0x3b)==0x39) // SWC1/SDC1
1453 alloc_reg(current,i,INVCP);
1454 #endif
1455 // We need a temporary register for address generation
1456 alloc_reg_temp(current,i,-1);
1457}
1458
b9b61529 1459void c2ls_alloc(struct regstat *current,int i)
1460{
1461 clear_const(current,rt1[i]);
1462 if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1463 alloc_reg(current,i,FTEMP);
b9b61529 1464 #if defined(HOST_IMM8)
1465 // On CPUs without 32-bit immediates we need a pointer to invalid_code
1edfcc68 1466 if((opcode[i]&0x3b)==0x3a) // SWC2/SDC2
b9b61529 1467 alloc_reg(current,i,INVCP);
1468 #endif
1469 // We need a temporary register for address generation
1470 alloc_reg_temp(current,i,-1);
e1190b87 1471 minimum_free_regs[i]=1;
b9b61529 1472}
1473
57871462 1474#ifndef multdiv_alloc
1475void multdiv_alloc(struct regstat *current,int i)
1476{
1477 // case 0x18: MULT
1478 // case 0x19: MULTU
1479 // case 0x1A: DIV
1480 // case 0x1B: DIVU
1481 // case 0x1C: DMULT
1482 // case 0x1D: DMULTU
1483 // case 0x1E: DDIV
1484 // case 0x1F: DDIVU
1485 clear_const(current,rs1[i]);
1486 clear_const(current,rs2[i]);
1487 if(rs1[i]&&rs2[i])
1488 {
1489 if((opcode2[i]&4)==0) // 32-bit
1490 {
1491 current->u&=~(1LL<<HIREG);
1492 current->u&=~(1LL<<LOREG);
1493 alloc_reg(current,i,HIREG);
1494 alloc_reg(current,i,LOREG);
1495 alloc_reg(current,i,rs1[i]);
1496 alloc_reg(current,i,rs2[i]);
1497 current->is32|=1LL<<HIREG;
1498 current->is32|=1LL<<LOREG;
1499 dirty_reg(current,HIREG);
1500 dirty_reg(current,LOREG);
1501 }
1502 else // 64-bit
1503 {
1504 current->u&=~(1LL<<HIREG);
1505 current->u&=~(1LL<<LOREG);
1506 current->uu&=~(1LL<<HIREG);
1507 current->uu&=~(1LL<<LOREG);
1508 alloc_reg64(current,i,HIREG);
1509 //if(HOST_REGS>10) alloc_reg64(current,i,LOREG);
1510 alloc_reg64(current,i,rs1[i]);
1511 alloc_reg64(current,i,rs2[i]);
1512 alloc_all(current,i);
1513 current->is32&=~(1LL<<HIREG);
1514 current->is32&=~(1LL<<LOREG);
1515 dirty_reg(current,HIREG);
1516 dirty_reg(current,LOREG);
e1190b87 1517 minimum_free_regs[i]=HOST_REGS;
57871462 1518 }
1519 }
1520 else
1521 {
1522 // Multiply by zero is zero.
1523 // MIPS does not have a divide by zero exception.
1524 // The result is undefined, we return zero.
1525 alloc_reg(current,i,HIREG);
1526 alloc_reg(current,i,LOREG);
1527 current->is32|=1LL<<HIREG;
1528 current->is32|=1LL<<LOREG;
1529 dirty_reg(current,HIREG);
1530 dirty_reg(current,LOREG);
1531 }
1532}
1533#endif
1534
1535void cop0_alloc(struct regstat *current,int i)
1536{
1537 if(opcode2[i]==0) // MFC0
1538 {
1539 if(rt1[i]) {
1540 clear_const(current,rt1[i]);
1541 alloc_all(current,i);
1542 alloc_reg(current,i,rt1[i]);
1543 current->is32|=1LL<<rt1[i];
1544 dirty_reg(current,rt1[i]);
1545 }
1546 }
1547 else if(opcode2[i]==4) // MTC0
1548 {
1549 if(rs1[i]){
1550 clear_const(current,rs1[i]);
1551 alloc_reg(current,i,rs1[i]);
1552 alloc_all(current,i);
1553 }
1554 else {
1555 alloc_all(current,i); // FIXME: Keep r0
1556 current->u&=~1LL;
1557 alloc_reg(current,i,0);
1558 }
1559 }
1560 else
1561 {
1562 // TLBR/TLBWI/TLBWR/TLBP/ERET
1563 assert(opcode2[i]==0x10);
1564 alloc_all(current,i);
1565 }
e1190b87 1566 minimum_free_regs[i]=HOST_REGS;
57871462 1567}
1568
1569void cop1_alloc(struct regstat *current,int i)
1570{
1571 alloc_reg(current,i,CSREG); // Load status
1572 if(opcode2[i]<3) // MFC1/DMFC1/CFC1
1573 {
7de557a6 1574 if(rt1[i]){
1575 clear_const(current,rt1[i]);
1576 if(opcode2[i]==1) {
1577 alloc_reg64(current,i,rt1[i]); // DMFC1
1578 current->is32&=~(1LL<<rt1[i]);
1579 }else{
1580 alloc_reg(current,i,rt1[i]); // MFC1/CFC1
1581 current->is32|=1LL<<rt1[i];
1582 }
1583 dirty_reg(current,rt1[i]);
57871462 1584 }
57871462 1585 alloc_reg_temp(current,i,-1);
1586 }
1587 else if(opcode2[i]>3) // MTC1/DMTC1/CTC1
1588 {
1589 if(rs1[i]){
1590 clear_const(current,rs1[i]);
1591 if(opcode2[i]==5)
1592 alloc_reg64(current,i,rs1[i]); // DMTC1
1593 else
1594 alloc_reg(current,i,rs1[i]); // MTC1/CTC1
1595 alloc_reg_temp(current,i,-1);
1596 }
1597 else {
1598 current->u&=~1LL;
1599 alloc_reg(current,i,0);
1600 alloc_reg_temp(current,i,-1);
1601 }
1602 }
e1190b87 1603 minimum_free_regs[i]=1;
57871462 1604}
1605void fconv_alloc(struct regstat *current,int i)
1606{
1607 alloc_reg(current,i,CSREG); // Load status
1608 alloc_reg_temp(current,i,-1);
e1190b87 1609 minimum_free_regs[i]=1;
57871462 1610}
1611void float_alloc(struct regstat *current,int i)
1612{
1613 alloc_reg(current,i,CSREG); // Load status
1614 alloc_reg_temp(current,i,-1);
e1190b87 1615 minimum_free_regs[i]=1;
57871462 1616}
b9b61529 1617void c2op_alloc(struct regstat *current,int i)
1618{
1619 alloc_reg_temp(current,i,-1);
1620}
57871462 1621void fcomp_alloc(struct regstat *current,int i)
1622{
1623 alloc_reg(current,i,CSREG); // Load status
1624 alloc_reg(current,i,FSREG); // Load flags
1625 dirty_reg(current,FSREG); // Flag will be modified
1626 alloc_reg_temp(current,i,-1);
e1190b87 1627 minimum_free_regs[i]=1;
57871462 1628}
1629
1630void syscall_alloc(struct regstat *current,int i)
1631{
1632 alloc_cc(current,i);
1633 dirty_reg(current,CCREG);
1634 alloc_all(current,i);
e1190b87 1635 minimum_free_regs[i]=HOST_REGS;
57871462 1636 current->isconst=0;
1637}
1638
1639void delayslot_alloc(struct regstat *current,int i)
1640{
1641 switch(itype[i]) {
1642 case UJUMP:
1643 case CJUMP:
1644 case SJUMP:
1645 case RJUMP:
1646 case FJUMP:
1647 case SYSCALL:
7139f3c8 1648 case HLECALL:
57871462 1649 case SPAN:
1650 assem_debug("jump in the delay slot. this shouldn't happen.\n");//exit(1);
c43b5311 1651 SysPrintf("Disabled speculative precompilation\n");
57871462 1652 stop_after_jal=1;
1653 break;
1654 case IMM16:
1655 imm16_alloc(current,i);
1656 break;
1657 case LOAD:
1658 case LOADLR:
1659 load_alloc(current,i);
1660 break;
1661 case STORE:
1662 case STORELR:
1663 store_alloc(current,i);
1664 break;
1665 case ALU:
1666 alu_alloc(current,i);
1667 break;
1668 case SHIFT:
1669 shift_alloc(current,i);
1670 break;
1671 case MULTDIV:
1672 multdiv_alloc(current,i);
1673 break;
1674 case SHIFTIMM:
1675 shiftimm_alloc(current,i);
1676 break;
1677 case MOV:
1678 mov_alloc(current,i);
1679 break;
1680 case COP0:
1681 cop0_alloc(current,i);
1682 break;
1683 case COP1:
b9b61529 1684 case COP2:
57871462 1685 cop1_alloc(current,i);
1686 break;
1687 case C1LS:
1688 c1ls_alloc(current,i);
1689 break;
b9b61529 1690 case C2LS:
1691 c2ls_alloc(current,i);
1692 break;
57871462 1693 case FCONV:
1694 fconv_alloc(current,i);
1695 break;
1696 case FLOAT:
1697 float_alloc(current,i);
1698 break;
1699 case FCOMP:
1700 fcomp_alloc(current,i);
1701 break;
b9b61529 1702 case C2OP:
1703 c2op_alloc(current,i);
1704 break;
57871462 1705 }
1706}
1707
1708// Special case where a branch and delay slot span two pages in virtual memory
1709static void pagespan_alloc(struct regstat *current,int i)
1710{
1711 current->isconst=0;
1712 current->wasconst=0;
1713 regs[i].wasconst=0;
e1190b87 1714 minimum_free_regs[i]=HOST_REGS;
57871462 1715 alloc_all(current,i);
1716 alloc_cc(current,i);
1717 dirty_reg(current,CCREG);
1718 if(opcode[i]==3) // JAL
1719 {
1720 alloc_reg(current,i,31);
1721 dirty_reg(current,31);
1722 }
1723 if(opcode[i]==0&&(opcode2[i]&0x3E)==8) // JR/JALR
1724 {
1725 alloc_reg(current,i,rs1[i]);
5067f341 1726 if (rt1[i]!=0) {
1727 alloc_reg(current,i,rt1[i]);
1728 dirty_reg(current,rt1[i]);
57871462 1729 }
1730 }
1731 if((opcode[i]&0x2E)==4) // BEQ/BNE/BEQL/BNEL
1732 {
1733 if(rs1[i]) alloc_reg(current,i,rs1[i]);
1734 if(rs2[i]) alloc_reg(current,i,rs2[i]);
1735 if(!((current->is32>>rs1[i])&(current->is32>>rs2[i])&1))
1736 {
1737 if(rs1[i]) alloc_reg64(current,i,rs1[i]);
1738 if(rs2[i]) alloc_reg64(current,i,rs2[i]);
1739 }
1740 }
1741 else
1742 if((opcode[i]&0x2E)==6) // BLEZ/BGTZ/BLEZL/BGTZL
1743 {
1744 if(rs1[i]) alloc_reg(current,i,rs1[i]);
1745 if(!((current->is32>>rs1[i])&1))
1746 {
1747 if(rs1[i]) alloc_reg64(current,i,rs1[i]);
1748 }
1749 }
1750 else
1751 if(opcode[i]==0x11) // BC1
1752 {
1753 alloc_reg(current,i,FSREG);
1754 alloc_reg(current,i,CSREG);
1755 }
1756 //else ...
1757}
1758
e2b5e7aa 1759static void add_stub(int type,int addr,int retaddr,int a,int b,int c,int d,int e)
57871462 1760{
1761 stubs[stubcount][0]=type;
1762 stubs[stubcount][1]=addr;
1763 stubs[stubcount][2]=retaddr;
1764 stubs[stubcount][3]=a;
1765 stubs[stubcount][4]=b;
1766 stubs[stubcount][5]=c;
1767 stubs[stubcount][6]=d;
1768 stubs[stubcount][7]=e;
1769 stubcount++;
1770}
1771
1772// Write out a single register
1773void wb_register(signed char r,signed char regmap[],uint64_t dirty,uint64_t is32)
1774{
1775 int hr;
1776 for(hr=0;hr<HOST_REGS;hr++) {
1777 if(hr!=EXCLUDE_REG) {
1778 if((regmap[hr]&63)==r) {
1779 if((dirty>>hr)&1) {
1780 if(regmap[hr]<64) {
1781 emit_storereg(r,hr);
57871462 1782 }else{
1783 emit_storereg(r|64,hr);
1784 }
1785 }
1786 }
1787 }
1788 }
1789}
1790
1791int mchecksum()
1792{
1793 //if(!tracedebug) return 0;
1794 int i;
1795 int sum=0;
1796 for(i=0;i<2097152;i++) {
1797 unsigned int temp=sum;
1798 sum<<=1;
1799 sum|=(~temp)>>31;
1800 sum^=((u_int *)rdram)[i];
1801 }
1802 return sum;
1803}
1804int rchecksum()
1805{
1806 int i;
1807 int sum=0;
1808 for(i=0;i<64;i++)
1809 sum^=((u_int *)reg)[i];
1810 return sum;
1811}
57871462 1812void rlist()
1813{
1814 int i;
1815 printf("TRACE: ");
1816 for(i=0;i<32;i++)
1817 printf("r%d:%8x%8x ",i,((int *)(reg+i))[1],((int *)(reg+i))[0]);
1818 printf("\n");
57871462 1819}
1820
1821void enabletrace()
1822{
1823 tracedebug=1;
1824}
1825
1826void memdebug(int i)
1827{
1828 //printf("TRACE: count=%d next=%d (checksum %x) lo=%8x%8x\n",Count,next_interupt,mchecksum(),(int)(reg[LOREG]>>32),(int)reg[LOREG]);
1829 //printf("TRACE: count=%d next=%d (rchecksum %x)\n",Count,next_interupt,rchecksum());
1830 //rlist();
1831 //if(tracedebug) {
1832 //if(Count>=-2084597794) {
1833 if((signed int)Count>=-2084597794&&(signed int)Count<0) {
1834 //if(0) {
1835 printf("TRACE: count=%d next=%d (checksum %x)\n",Count,next_interupt,mchecksum());
1836 //printf("TRACE: count=%d next=%d (checksum %x) Status=%x\n",Count,next_interupt,mchecksum(),Status);
1837 //printf("TRACE: count=%d next=%d (checksum %x) hi=%8x%8x\n",Count,next_interupt,mchecksum(),(int)(reg[HIREG]>>32),(int)reg[HIREG]);
1838 rlist();
1839 #ifdef __i386__
1840 printf("TRACE: %x\n",(&i)[-1]);
1841 #endif
1842 #ifdef __arm__
1843 int j;
1844 printf("TRACE: %x \n",(&j)[10]);
1845 printf("TRACE: %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x\n",(&j)[1],(&j)[2],(&j)[3],(&j)[4],(&j)[5],(&j)[6],(&j)[7],(&j)[8],(&j)[9],(&j)[10],(&j)[11],(&j)[12],(&j)[13],(&j)[14],(&j)[15],(&j)[16],(&j)[17],(&j)[18],(&j)[19],(&j)[20]);
1846 #endif
1847 //fflush(stdout);
1848 }
1849 //printf("TRACE: %x\n",(&i)[-1]);
1850}
1851
57871462 1852void alu_assemble(int i,struct regstat *i_regs)
1853{
1854 if(opcode2[i]>=0x20&&opcode2[i]<=0x23) { // ADD/ADDU/SUB/SUBU
1855 if(rt1[i]) {
1856 signed char s1,s2,t;
1857 t=get_reg(i_regs->regmap,rt1[i]);
1858 if(t>=0) {
1859 s1=get_reg(i_regs->regmap,rs1[i]);
1860 s2=get_reg(i_regs->regmap,rs2[i]);
1861 if(rs1[i]&&rs2[i]) {
1862 assert(s1>=0);
1863 assert(s2>=0);
1864 if(opcode2[i]&2) emit_sub(s1,s2,t);
1865 else emit_add(s1,s2,t);
1866 }
1867 else if(rs1[i]) {
1868 if(s1>=0) emit_mov(s1,t);
1869 else emit_loadreg(rs1[i],t);
1870 }
1871 else if(rs2[i]) {
1872 if(s2>=0) {
1873 if(opcode2[i]&2) emit_neg(s2,t);
1874 else emit_mov(s2,t);
1875 }
1876 else {
1877 emit_loadreg(rs2[i],t);
1878 if(opcode2[i]&2) emit_neg(t,t);
1879 }
1880 }
1881 else emit_zeroreg(t);
1882 }
1883 }
1884 }
1885 if(opcode2[i]>=0x2c&&opcode2[i]<=0x2f) { // DADD/DADDU/DSUB/DSUBU
1886 if(rt1[i]) {
1887 signed char s1l,s2l,s1h,s2h,tl,th;
1888 tl=get_reg(i_regs->regmap,rt1[i]);
1889 th=get_reg(i_regs->regmap,rt1[i]|64);
1890 if(tl>=0) {
1891 s1l=get_reg(i_regs->regmap,rs1[i]);
1892 s2l=get_reg(i_regs->regmap,rs2[i]);
1893 s1h=get_reg(i_regs->regmap,rs1[i]|64);
1894 s2h=get_reg(i_regs->regmap,rs2[i]|64);
1895 if(rs1[i]&&rs2[i]) {
1896 assert(s1l>=0);
1897 assert(s2l>=0);
1898 if(opcode2[i]&2) emit_subs(s1l,s2l,tl);
1899 else emit_adds(s1l,s2l,tl);
1900 if(th>=0) {
1901 #ifdef INVERTED_CARRY
1902 if(opcode2[i]&2) {if(s1h!=th) emit_mov(s1h,th);emit_sbb(th,s2h);}
1903 #else
1904 if(opcode2[i]&2) emit_sbc(s1h,s2h,th);
1905 #endif
1906 else emit_add(s1h,s2h,th);
1907 }
1908 }
1909 else if(rs1[i]) {
1910 if(s1l>=0) emit_mov(s1l,tl);
1911 else emit_loadreg(rs1[i],tl);
1912 if(th>=0) {
1913 if(s1h>=0) emit_mov(s1h,th);
1914 else emit_loadreg(rs1[i]|64,th);
1915 }
1916 }
1917 else if(rs2[i]) {
1918 if(s2l>=0) {
1919 if(opcode2[i]&2) emit_negs(s2l,tl);
1920 else emit_mov(s2l,tl);
1921 }
1922 else {
1923 emit_loadreg(rs2[i],tl);
1924 if(opcode2[i]&2) emit_negs(tl,tl);
1925 }
1926 if(th>=0) {
1927 #ifdef INVERTED_CARRY
1928 if(s2h>=0) emit_mov(s2h,th);
1929 else emit_loadreg(rs2[i]|64,th);
1930 if(opcode2[i]&2) {
1931 emit_adcimm(-1,th); // x86 has inverted carry flag
1932 emit_not(th,th);
1933 }
1934 #else
1935 if(opcode2[i]&2) {
1936 if(s2h>=0) emit_rscimm(s2h,0,th);
1937 else {
1938 emit_loadreg(rs2[i]|64,th);
1939 emit_rscimm(th,0,th);
1940 }
1941 }else{
1942 if(s2h>=0) emit_mov(s2h,th);
1943 else emit_loadreg(rs2[i]|64,th);
1944 }
1945 #endif
1946 }
1947 }
1948 else {
1949 emit_zeroreg(tl);
1950 if(th>=0) emit_zeroreg(th);
1951 }
1952 }
1953 }
1954 }
1955 if(opcode2[i]==0x2a||opcode2[i]==0x2b) { // SLT/SLTU
1956 if(rt1[i]) {
1957 signed char s1l,s1h,s2l,s2h,t;
1958 if(!((i_regs->was32>>rs1[i])&(i_regs->was32>>rs2[i])&1))
1959 {
1960 t=get_reg(i_regs->regmap,rt1[i]);
1961 //assert(t>=0);
1962 if(t>=0) {
1963 s1l=get_reg(i_regs->regmap,rs1[i]);
1964 s1h=get_reg(i_regs->regmap,rs1[i]|64);
1965 s2l=get_reg(i_regs->regmap,rs2[i]);
1966 s2h=get_reg(i_regs->regmap,rs2[i]|64);
1967 if(rs2[i]==0) // rx<r0
1968 {
1969 assert(s1h>=0);
1970 if(opcode2[i]==0x2a) // SLT
1971 emit_shrimm(s1h,31,t);
1972 else // SLTU (unsigned can not be less than zero)
1973 emit_zeroreg(t);
1974 }
1975 else if(rs1[i]==0) // r0<rx
1976 {
1977 assert(s2h>=0);
1978 if(opcode2[i]==0x2a) // SLT
1979 emit_set_gz64_32(s2h,s2l,t);
1980 else // SLTU (set if not zero)
1981 emit_set_nz64_32(s2h,s2l,t);
1982 }
1983 else {
1984 assert(s1l>=0);assert(s1h>=0);
1985 assert(s2l>=0);assert(s2h>=0);
1986 if(opcode2[i]==0x2a) // SLT
1987 emit_set_if_less64_32(s1h,s1l,s2h,s2l,t);
1988 else // SLTU
1989 emit_set_if_carry64_32(s1h,s1l,s2h,s2l,t);
1990 }
1991 }
1992 } else {
1993 t=get_reg(i_regs->regmap,rt1[i]);
1994 //assert(t>=0);
1995 if(t>=0) {
1996 s1l=get_reg(i_regs->regmap,rs1[i]);
1997 s2l=get_reg(i_regs->regmap,rs2[i]);
1998 if(rs2[i]==0) // rx<r0
1999 {
2000 assert(s1l>=0);
2001 if(opcode2[i]==0x2a) // SLT
2002 emit_shrimm(s1l,31,t);
2003 else // SLTU (unsigned can not be less than zero)
2004 emit_zeroreg(t);
2005 }
2006 else if(rs1[i]==0) // r0<rx
2007 {
2008 assert(s2l>=0);
2009 if(opcode2[i]==0x2a) // SLT
2010 emit_set_gz32(s2l,t);
2011 else // SLTU (set if not zero)
2012 emit_set_nz32(s2l,t);
2013 }
2014 else{
2015 assert(s1l>=0);assert(s2l>=0);
2016 if(opcode2[i]==0x2a) // SLT
2017 emit_set_if_less32(s1l,s2l,t);
2018 else // SLTU
2019 emit_set_if_carry32(s1l,s2l,t);
2020 }
2021 }
2022 }
2023 }
2024 }
2025 if(opcode2[i]>=0x24&&opcode2[i]<=0x27) { // AND/OR/XOR/NOR
2026 if(rt1[i]) {
2027 signed char s1l,s1h,s2l,s2h,th,tl;
2028 tl=get_reg(i_regs->regmap,rt1[i]);
2029 th=get_reg(i_regs->regmap,rt1[i]|64);
2030 if(!((i_regs->was32>>rs1[i])&(i_regs->was32>>rs2[i])&1)&&th>=0)
2031 {
2032 assert(tl>=0);
2033 if(tl>=0) {
2034 s1l=get_reg(i_regs->regmap,rs1[i]);
2035 s1h=get_reg(i_regs->regmap,rs1[i]|64);
2036 s2l=get_reg(i_regs->regmap,rs2[i]);
2037 s2h=get_reg(i_regs->regmap,rs2[i]|64);
2038 if(rs1[i]&&rs2[i]) {
2039 assert(s1l>=0);assert(s1h>=0);
2040 assert(s2l>=0);assert(s2h>=0);
2041 if(opcode2[i]==0x24) { // AND
2042 emit_and(s1l,s2l,tl);
2043 emit_and(s1h,s2h,th);
2044 } else
2045 if(opcode2[i]==0x25) { // OR
2046 emit_or(s1l,s2l,tl);
2047 emit_or(s1h,s2h,th);
2048 } else
2049 if(opcode2[i]==0x26) { // XOR
2050 emit_xor(s1l,s2l,tl);
2051 emit_xor(s1h,s2h,th);
2052 } else
2053 if(opcode2[i]==0x27) { // NOR
2054 emit_or(s1l,s2l,tl);
2055 emit_or(s1h,s2h,th);
2056 emit_not(tl,tl);
2057 emit_not(th,th);
2058 }
2059 }
2060 else
2061 {
2062 if(opcode2[i]==0x24) { // AND
2063 emit_zeroreg(tl);
2064 emit_zeroreg(th);
2065 } else
2066 if(opcode2[i]==0x25||opcode2[i]==0x26) { // OR/XOR
2067 if(rs1[i]){
2068 if(s1l>=0) emit_mov(s1l,tl);
2069 else emit_loadreg(rs1[i],tl);
2070 if(s1h>=0) emit_mov(s1h,th);
2071 else emit_loadreg(rs1[i]|64,th);
2072 }
2073 else
2074 if(rs2[i]){
2075 if(s2l>=0) emit_mov(s2l,tl);
2076 else emit_loadreg(rs2[i],tl);
2077 if(s2h>=0) emit_mov(s2h,th);
2078 else emit_loadreg(rs2[i]|64,th);
2079 }
2080 else{
2081 emit_zeroreg(tl);
2082 emit_zeroreg(th);
2083 }
2084 } else
2085 if(opcode2[i]==0x27) { // NOR
2086 if(rs1[i]){
2087 if(s1l>=0) emit_not(s1l,tl);
2088 else{
2089 emit_loadreg(rs1[i],tl);
2090 emit_not(tl,tl);
2091 }
2092 if(s1h>=0) emit_not(s1h,th);
2093 else{
2094 emit_loadreg(rs1[i]|64,th);
2095 emit_not(th,th);
2096 }
2097 }
2098 else
2099 if(rs2[i]){
2100 if(s2l>=0) emit_not(s2l,tl);
2101 else{
2102 emit_loadreg(rs2[i],tl);
2103 emit_not(tl,tl);
2104 }
2105 if(s2h>=0) emit_not(s2h,th);
2106 else{
2107 emit_loadreg(rs2[i]|64,th);
2108 emit_not(th,th);
2109 }
2110 }
2111 else {
2112 emit_movimm(-1,tl);
2113 emit_movimm(-1,th);
2114 }
2115 }
2116 }
2117 }
2118 }
2119 else
2120 {
2121 // 32 bit
2122 if(tl>=0) {
2123 s1l=get_reg(i_regs->regmap,rs1[i]);
2124 s2l=get_reg(i_regs->regmap,rs2[i]);
2125 if(rs1[i]&&rs2[i]) {
2126 assert(s1l>=0);
2127 assert(s2l>=0);
2128 if(opcode2[i]==0x24) { // AND
2129 emit_and(s1l,s2l,tl);
2130 } else
2131 if(opcode2[i]==0x25) { // OR
2132 emit_or(s1l,s2l,tl);
2133 } else
2134 if(opcode2[i]==0x26) { // XOR
2135 emit_xor(s1l,s2l,tl);
2136 } else
2137 if(opcode2[i]==0x27) { // NOR
2138 emit_or(s1l,s2l,tl);
2139 emit_not(tl,tl);
2140 }
2141 }
2142 else
2143 {
2144 if(opcode2[i]==0x24) { // AND
2145 emit_zeroreg(tl);
2146 } else
2147 if(opcode2[i]==0x25||opcode2[i]==0x26) { // OR/XOR
2148 if(rs1[i]){
2149 if(s1l>=0) emit_mov(s1l,tl);
2150 else emit_loadreg(rs1[i],tl); // CHECK: regmap_entry?
2151 }
2152 else
2153 if(rs2[i]){
2154 if(s2l>=0) emit_mov(s2l,tl);
2155 else emit_loadreg(rs2[i],tl); // CHECK: regmap_entry?
2156 }
2157 else emit_zeroreg(tl);
2158 } else
2159 if(opcode2[i]==0x27) { // NOR
2160 if(rs1[i]){
2161 if(s1l>=0) emit_not(s1l,tl);
2162 else {
2163 emit_loadreg(rs1[i],tl);
2164 emit_not(tl,tl);
2165 }
2166 }
2167 else
2168 if(rs2[i]){
2169 if(s2l>=0) emit_not(s2l,tl);
2170 else {
2171 emit_loadreg(rs2[i],tl);
2172 emit_not(tl,tl);
2173 }
2174 }
2175 else emit_movimm(-1,tl);
2176 }
2177 }
2178 }
2179 }
2180 }
2181 }
2182}
2183
2184void imm16_assemble(int i,struct regstat *i_regs)
2185{
2186 if (opcode[i]==0x0f) { // LUI
2187 if(rt1[i]) {
2188 signed char t;
2189 t=get_reg(i_regs->regmap,rt1[i]);
2190 //assert(t>=0);
2191 if(t>=0) {
2192 if(!((i_regs->isconst>>t)&1))
2193 emit_movimm(imm[i]<<16,t);
2194 }
2195 }
2196 }
2197 if(opcode[i]==0x08||opcode[i]==0x09) { // ADDI/ADDIU
2198 if(rt1[i]) {
2199 signed char s,t;
2200 t=get_reg(i_regs->regmap,rt1[i]);
2201 s=get_reg(i_regs->regmap,rs1[i]);
2202 if(rs1[i]) {
2203 //assert(t>=0);
2204 //assert(s>=0);
2205 if(t>=0) {
2206 if(!((i_regs->isconst>>t)&1)) {
2207 if(s<0) {
2208 if(i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2209 emit_addimm(t,imm[i],t);
2210 }else{
2211 if(!((i_regs->wasconst>>s)&1))
2212 emit_addimm(s,imm[i],t);
2213 else
2214 emit_movimm(constmap[i][s]+imm[i],t);
2215 }
2216 }
2217 }
2218 } else {
2219 if(t>=0) {
2220 if(!((i_regs->isconst>>t)&1))
2221 emit_movimm(imm[i],t);
2222 }
2223 }
2224 }
2225 }
2226 if(opcode[i]==0x18||opcode[i]==0x19) { // DADDI/DADDIU
2227 if(rt1[i]) {
2228 signed char sh,sl,th,tl;
2229 th=get_reg(i_regs->regmap,rt1[i]|64);
2230 tl=get_reg(i_regs->regmap,rt1[i]);
2231 sh=get_reg(i_regs->regmap,rs1[i]|64);
2232 sl=get_reg(i_regs->regmap,rs1[i]);
2233 if(tl>=0) {
2234 if(rs1[i]) {
2235 assert(sh>=0);
2236 assert(sl>=0);
2237 if(th>=0) {
2238 emit_addimm64_32(sh,sl,imm[i],th,tl);
2239 }
2240 else {
2241 emit_addimm(sl,imm[i],tl);
2242 }
2243 } else {
2244 emit_movimm(imm[i],tl);
2245 if(th>=0) emit_movimm(((signed int)imm[i])>>31,th);
2246 }
2247 }
2248 }
2249 }
2250 else if(opcode[i]==0x0a||opcode[i]==0x0b) { // SLTI/SLTIU
2251 if(rt1[i]) {
2252 //assert(rs1[i]!=0); // r0 might be valid, but it's probably a bug
2253 signed char sh,sl,t;
2254 t=get_reg(i_regs->regmap,rt1[i]);
2255 sh=get_reg(i_regs->regmap,rs1[i]|64);
2256 sl=get_reg(i_regs->regmap,rs1[i]);
2257 //assert(t>=0);
2258 if(t>=0) {
2259 if(rs1[i]>0) {
2260 if(sh<0) assert((i_regs->was32>>rs1[i])&1);
2261 if(sh<0||((i_regs->was32>>rs1[i])&1)) {
2262 if(opcode[i]==0x0a) { // SLTI
2263 if(sl<0) {
2264 if(i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2265 emit_slti32(t,imm[i],t);
2266 }else{
2267 emit_slti32(sl,imm[i],t);
2268 }
2269 }
2270 else { // SLTIU
2271 if(sl<0) {
2272 if(i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2273 emit_sltiu32(t,imm[i],t);
2274 }else{
2275 emit_sltiu32(sl,imm[i],t);
2276 }
2277 }
2278 }else{ // 64-bit
2279 assert(sl>=0);
2280 if(opcode[i]==0x0a) // SLTI
2281 emit_slti64_32(sh,sl,imm[i],t);
2282 else // SLTIU
2283 emit_sltiu64_32(sh,sl,imm[i],t);
2284 }
2285 }else{
2286 // SLTI(U) with r0 is just stupid,
2287 // nonetheless examples can be found
2288 if(opcode[i]==0x0a) // SLTI
2289 if(0<imm[i]) emit_movimm(1,t);
2290 else emit_zeroreg(t);
2291 else // SLTIU
2292 {
2293 if(imm[i]) emit_movimm(1,t);
2294 else emit_zeroreg(t);
2295 }
2296 }
2297 }
2298 }
2299 }
2300 else if(opcode[i]>=0x0c&&opcode[i]<=0x0e) { // ANDI/ORI/XORI
2301 if(rt1[i]) {
2302 signed char sh,sl,th,tl;
2303 th=get_reg(i_regs->regmap,rt1[i]|64);
2304 tl=get_reg(i_regs->regmap,rt1[i]);
2305 sh=get_reg(i_regs->regmap,rs1[i]|64);
2306 sl=get_reg(i_regs->regmap,rs1[i]);
2307 if(tl>=0 && !((i_regs->isconst>>tl)&1)) {
2308 if(opcode[i]==0x0c) //ANDI
2309 {
2310 if(rs1[i]) {
2311 if(sl<0) {
2312 if(i_regs->regmap_entry[tl]!=rs1[i]) emit_loadreg(rs1[i],tl);
2313 emit_andimm(tl,imm[i],tl);
2314 }else{
2315 if(!((i_regs->wasconst>>sl)&1))
2316 emit_andimm(sl,imm[i],tl);
2317 else
2318 emit_movimm(constmap[i][sl]&imm[i],tl);
2319 }
2320 }
2321 else
2322 emit_zeroreg(tl);
2323 if(th>=0) emit_zeroreg(th);
2324 }
2325 else
2326 {
2327 if(rs1[i]) {
2328 if(sl<0) {
2329 if(i_regs->regmap_entry[tl]!=rs1[i]) emit_loadreg(rs1[i],tl);
2330 }
2331 if(th>=0) {
2332 if(sh<0) {
2333 emit_loadreg(rs1[i]|64,th);
2334 }else{
2335 emit_mov(sh,th);
2336 }
2337 }
581335b0 2338 if(opcode[i]==0x0d) { // ORI
2339 if(sl<0) {
2340 emit_orimm(tl,imm[i],tl);
2341 }else{
2342 if(!((i_regs->wasconst>>sl)&1))
2343 emit_orimm(sl,imm[i],tl);
2344 else
2345 emit_movimm(constmap[i][sl]|imm[i],tl);
2346 }
57871462 2347 }
581335b0 2348 if(opcode[i]==0x0e) { // XORI
2349 if(sl<0) {
2350 emit_xorimm(tl,imm[i],tl);
2351 }else{
2352 if(!((i_regs->wasconst>>sl)&1))
2353 emit_xorimm(sl,imm[i],tl);
2354 else
2355 emit_movimm(constmap[i][sl]^imm[i],tl);
2356 }
57871462 2357 }
2358 }
2359 else {
2360 emit_movimm(imm[i],tl);
2361 if(th>=0) emit_zeroreg(th);
2362 }
2363 }
2364 }
2365 }
2366 }
2367}
2368
2369void shiftimm_assemble(int i,struct regstat *i_regs)
2370{
2371 if(opcode2[i]<=0x3) // SLL/SRL/SRA
2372 {
2373 if(rt1[i]) {
2374 signed char s,t;
2375 t=get_reg(i_regs->regmap,rt1[i]);
2376 s=get_reg(i_regs->regmap,rs1[i]);
2377 //assert(t>=0);
dc49e339 2378 if(t>=0&&!((i_regs->isconst>>t)&1)){
57871462 2379 if(rs1[i]==0)
2380 {
2381 emit_zeroreg(t);
2382 }
2383 else
2384 {
2385 if(s<0&&i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2386 if(imm[i]) {
2387 if(opcode2[i]==0) // SLL
2388 {
2389 emit_shlimm(s<0?t:s,imm[i],t);
2390 }
2391 if(opcode2[i]==2) // SRL
2392 {
2393 emit_shrimm(s<0?t:s,imm[i],t);
2394 }
2395 if(opcode2[i]==3) // SRA
2396 {
2397 emit_sarimm(s<0?t:s,imm[i],t);
2398 }
2399 }else{
2400 // Shift by zero
2401 if(s>=0 && s!=t) emit_mov(s,t);
2402 }
2403 }
2404 }
2405 //emit_storereg(rt1[i],t); //DEBUG
2406 }
2407 }
2408 if(opcode2[i]>=0x38&&opcode2[i]<=0x3b) // DSLL/DSRL/DSRA
2409 {
2410 if(rt1[i]) {
2411 signed char sh,sl,th,tl;
2412 th=get_reg(i_regs->regmap,rt1[i]|64);
2413 tl=get_reg(i_regs->regmap,rt1[i]);
2414 sh=get_reg(i_regs->regmap,rs1[i]|64);
2415 sl=get_reg(i_regs->regmap,rs1[i]);
2416 if(tl>=0) {
2417 if(rs1[i]==0)
2418 {
2419 emit_zeroreg(tl);
2420 if(th>=0) emit_zeroreg(th);
2421 }
2422 else
2423 {
2424 assert(sl>=0);
2425 assert(sh>=0);
2426 if(imm[i]) {
2427 if(opcode2[i]==0x38) // DSLL
2428 {
2429 if(th>=0) emit_shldimm(sh,sl,imm[i],th);
2430 emit_shlimm(sl,imm[i],tl);
2431 }
2432 if(opcode2[i]==0x3a) // DSRL
2433 {
2434 emit_shrdimm(sl,sh,imm[i],tl);
2435 if(th>=0) emit_shrimm(sh,imm[i],th);
2436 }
2437 if(opcode2[i]==0x3b) // DSRA
2438 {
2439 emit_shrdimm(sl,sh,imm[i],tl);
2440 if(th>=0) emit_sarimm(sh,imm[i],th);
2441 }
2442 }else{
2443 // Shift by zero
2444 if(sl!=tl) emit_mov(sl,tl);
2445 if(th>=0&&sh!=th) emit_mov(sh,th);
2446 }
2447 }
2448 }
2449 }
2450 }
2451 if(opcode2[i]==0x3c) // DSLL32
2452 {
2453 if(rt1[i]) {
2454 signed char sl,tl,th;
2455 tl=get_reg(i_regs->regmap,rt1[i]);
2456 th=get_reg(i_regs->regmap,rt1[i]|64);
2457 sl=get_reg(i_regs->regmap,rs1[i]);
2458 if(th>=0||tl>=0){
2459 assert(tl>=0);
2460 assert(th>=0);
2461 assert(sl>=0);
2462 emit_mov(sl,th);
2463 emit_zeroreg(tl);
2464 if(imm[i]>32)
2465 {
2466 emit_shlimm(th,imm[i]&31,th);
2467 }
2468 }
2469 }
2470 }
2471 if(opcode2[i]==0x3e) // DSRL32
2472 {
2473 if(rt1[i]) {
2474 signed char sh,tl,th;
2475 tl=get_reg(i_regs->regmap,rt1[i]);
2476 th=get_reg(i_regs->regmap,rt1[i]|64);
2477 sh=get_reg(i_regs->regmap,rs1[i]|64);
2478 if(tl>=0){
2479 assert(sh>=0);
2480 emit_mov(sh,tl);
2481 if(th>=0) emit_zeroreg(th);
2482 if(imm[i]>32)
2483 {
2484 emit_shrimm(tl,imm[i]&31,tl);
2485 }
2486 }
2487 }
2488 }
2489 if(opcode2[i]==0x3f) // DSRA32
2490 {
2491 if(rt1[i]) {
2492 signed char sh,tl;
2493 tl=get_reg(i_regs->regmap,rt1[i]);
2494 sh=get_reg(i_regs->regmap,rs1[i]|64);
2495 if(tl>=0){
2496 assert(sh>=0);
2497 emit_mov(sh,tl);
2498 if(imm[i]>32)
2499 {
2500 emit_sarimm(tl,imm[i]&31,tl);
2501 }
2502 }
2503 }
2504 }
2505}
2506
2507#ifndef shift_assemble
2508void shift_assemble(int i,struct regstat *i_regs)
2509{
2510 printf("Need shift_assemble for this architecture.\n");
2511 exit(1);
2512}
2513#endif
2514
2515void load_assemble(int i,struct regstat *i_regs)
2516{
2517 int s,th,tl,addr,map=-1;
2518 int offset;
2519 int jaddr=0;
5bf843dc 2520 int memtarget=0,c=0;
b1570849 2521 int fastload_reg_override=0;
57871462 2522 u_int hr,reglist=0;
2523 th=get_reg(i_regs->regmap,rt1[i]|64);
2524 tl=get_reg(i_regs->regmap,rt1[i]);
2525 s=get_reg(i_regs->regmap,rs1[i]);
2526 offset=imm[i];
2527 for(hr=0;hr<HOST_REGS;hr++) {
2528 if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
2529 }
2530 if(i_regs->regmap[HOST_CCREG]==CCREG) reglist&=~(1<<HOST_CCREG);
2531 if(s>=0) {
2532 c=(i_regs->wasconst>>s)&1;
af4ee1fe 2533 if (c) {
2534 memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
af4ee1fe 2535 }
57871462 2536 }
57871462 2537 //printf("load_assemble: c=%d\n",c);
2538 //if(c) printf("load_assemble: const=%x\n",(int)constmap[i][s]+offset);
2539 // FIXME: Even if the load is a NOP, we should check for pagefaults...
581335b0 2540 if((tl<0&&(!c||(((u_int)constmap[i][s]+offset)>>16)==0x1f80))
f18c0f46 2541 ||rt1[i]==0) {
5bf843dc 2542 // could be FIFO, must perform the read
f18c0f46 2543 // ||dummy read
5bf843dc 2544 assem_debug("(forced read)\n");
2545 tl=get_reg(i_regs->regmap,-1);
2546 assert(tl>=0);
5bf843dc 2547 }
2548 if(offset||s<0||c) addr=tl;
2549 else addr=s;
535d208a 2550 //if(tl<0) tl=get_reg(i_regs->regmap,-1);
2551 if(tl>=0) {
2552 //printf("load_assemble: c=%d\n",c);
2553 //if(c) printf("load_assemble: const=%x\n",(int)constmap[i][s]+offset);
2554 assert(tl>=0); // Even if the load is a NOP, we must check for pagefaults and I/O
2555 reglist&=~(1<<tl);
2556 if(th>=0) reglist&=~(1<<th);
1edfcc68 2557 if(!c) {
2558 #ifdef RAM_OFFSET
2559 map=get_reg(i_regs->regmap,ROREG);
2560 if(map<0) emit_loadreg(ROREG,map=HOST_TEMPREG);
2561 #endif
2562 #ifdef R29_HACK
2563 // Strmnnrmn's speed hack
2564 if(rs1[i]!=29||start<0x80001000||start>=0x80000000+RAM_SIZE)
2565 #endif
2566 {
2567 jaddr=emit_fastpath_cmp_jump(i,addr,&fastload_reg_override);
535d208a 2568 }
1edfcc68 2569 }
2570 else if(ram_offset&&memtarget) {
2571 emit_addimm(addr,ram_offset,HOST_TEMPREG);
2572 fastload_reg_override=HOST_TEMPREG;
535d208a 2573 }
2574 int dummy=(rt1[i]==0)||(tl!=get_reg(i_regs->regmap,rt1[i])); // ignore loads to r0 and unneeded reg
2575 if (opcode[i]==0x20) { // LB
2576 if(!c||memtarget) {
2577 if(!dummy) {
57871462 2578 #ifdef HOST_IMM_ADDR32
2579 if(c)
2580 emit_movsbl_tlb((constmap[i][s]+offset)^3,map,tl);
2581 else
2582 #endif
2583 {
2584 //emit_xorimm(addr,3,tl);
57871462 2585 //emit_movsbl_indexed((int)rdram-0x80000000,tl,tl);
535d208a 2586 int x=0,a=tl;
2002a1db 2587#ifdef BIG_ENDIAN_MIPS
57871462 2588 if(!c) emit_xorimm(addr,3,tl);
2589 else x=((constmap[i][s]+offset)^3)-(constmap[i][s]+offset);
2002a1db 2590#else
535d208a 2591 if(!c) a=addr;
dadf55f2 2592#endif
b1570849 2593 if(fastload_reg_override) a=fastload_reg_override;
2594
535d208a 2595 emit_movsbl_indexed_tlb(x,a,map,tl);
57871462 2596 }
57871462 2597 }
535d208a 2598 if(jaddr)
2599 add_stub(LOADB_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
57871462 2600 }
535d208a 2601 else
2602 inline_readstub(LOADB_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2603 }
2604 if (opcode[i]==0x21) { // LH
2605 if(!c||memtarget) {
2606 if(!dummy) {
57871462 2607 #ifdef HOST_IMM_ADDR32
2608 if(c)
2609 emit_movswl_tlb((constmap[i][s]+offset)^2,map,tl);
2610 else
2611 #endif
2612 {
535d208a 2613 int x=0,a=tl;
2002a1db 2614#ifdef BIG_ENDIAN_MIPS
57871462 2615 if(!c) emit_xorimm(addr,2,tl);
2616 else x=((constmap[i][s]+offset)^2)-(constmap[i][s]+offset);
2002a1db 2617#else
535d208a 2618 if(!c) a=addr;
dadf55f2 2619#endif
b1570849 2620 if(fastload_reg_override) a=fastload_reg_override;
57871462 2621 //#ifdef
2622 //emit_movswl_indexed_tlb(x,tl,map,tl);
2623 //else
2624 if(map>=0) {
535d208a 2625 emit_movswl_indexed(x,a,tl);
2626 }else{
a327ad27 2627 #if 1 //def RAM_OFFSET
535d208a 2628 emit_movswl_indexed(x,a,tl);
2629 #else
2630 emit_movswl_indexed((int)rdram-0x80000000+x,a,tl);
2631 #endif
2632 }
57871462 2633 }
57871462 2634 }
535d208a 2635 if(jaddr)
2636 add_stub(LOADH_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
57871462 2637 }
535d208a 2638 else
2639 inline_readstub(LOADH_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2640 }
2641 if (opcode[i]==0x23) { // LW
2642 if(!c||memtarget) {
2643 if(!dummy) {
dadf55f2 2644 int a=addr;
b1570849 2645 if(fastload_reg_override) a=fastload_reg_override;
57871462 2646 //emit_readword_indexed((int)rdram-0x80000000,addr,tl);
2647 #ifdef HOST_IMM_ADDR32
2648 if(c)
2649 emit_readword_tlb(constmap[i][s]+offset,map,tl);
2650 else
2651 #endif
dadf55f2 2652 emit_readword_indexed_tlb(0,a,map,tl);
57871462 2653 }
535d208a 2654 if(jaddr)
2655 add_stub(LOADW_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
57871462 2656 }
535d208a 2657 else
2658 inline_readstub(LOADW_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2659 }
2660 if (opcode[i]==0x24) { // LBU
2661 if(!c||memtarget) {
2662 if(!dummy) {
57871462 2663 #ifdef HOST_IMM_ADDR32
2664 if(c)
2665 emit_movzbl_tlb((constmap[i][s]+offset)^3,map,tl);
2666 else
2667 #endif
2668 {
2669 //emit_xorimm(addr,3,tl);
57871462 2670 //emit_movzbl_indexed((int)rdram-0x80000000,tl,tl);
535d208a 2671 int x=0,a=tl;
2002a1db 2672#ifdef BIG_ENDIAN_MIPS
57871462 2673 if(!c) emit_xorimm(addr,3,tl);
2674 else x=((constmap[i][s]+offset)^3)-(constmap[i][s]+offset);
2002a1db 2675#else
535d208a 2676 if(!c) a=addr;
dadf55f2 2677#endif
b1570849 2678 if(fastload_reg_override) a=fastload_reg_override;
2679
535d208a 2680 emit_movzbl_indexed_tlb(x,a,map,tl);
57871462 2681 }
57871462 2682 }
535d208a 2683 if(jaddr)
2684 add_stub(LOADBU_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
57871462 2685 }
535d208a 2686 else
2687 inline_readstub(LOADBU_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2688 }
2689 if (opcode[i]==0x25) { // LHU
2690 if(!c||memtarget) {
2691 if(!dummy) {
57871462 2692 #ifdef HOST_IMM_ADDR32
2693 if(c)
2694 emit_movzwl_tlb((constmap[i][s]+offset)^2,map,tl);
2695 else
2696 #endif
2697 {
535d208a 2698 int x=0,a=tl;
2002a1db 2699#ifdef BIG_ENDIAN_MIPS
57871462 2700 if(!c) emit_xorimm(addr,2,tl);
2701 else x=((constmap[i][s]+offset)^2)-(constmap[i][s]+offset);
2002a1db 2702#else
535d208a 2703 if(!c) a=addr;
dadf55f2 2704#endif
b1570849 2705 if(fastload_reg_override) a=fastload_reg_override;
57871462 2706 //#ifdef
2707 //emit_movzwl_indexed_tlb(x,tl,map,tl);
2708 //#else
2709 if(map>=0) {
535d208a 2710 emit_movzwl_indexed(x,a,tl);
2711 }else{
a327ad27 2712 #if 1 //def RAM_OFFSET
535d208a 2713 emit_movzwl_indexed(x,a,tl);
2714 #else
2715 emit_movzwl_indexed((int)rdram-0x80000000+x,a,tl);
2716 #endif
2717 }
57871462 2718 }
2719 }
535d208a 2720 if(jaddr)
2721 add_stub(LOADHU_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
57871462 2722 }
535d208a 2723 else
2724 inline_readstub(LOADHU_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2725 }
2726 if (opcode[i]==0x27) { // LWU
2727 assert(th>=0);
2728 if(!c||memtarget) {
2729 if(!dummy) {
dadf55f2 2730 int a=addr;
b1570849 2731 if(fastload_reg_override) a=fastload_reg_override;
57871462 2732 //emit_readword_indexed((int)rdram-0x80000000,addr,tl);
2733 #ifdef HOST_IMM_ADDR32
2734 if(c)
2735 emit_readword_tlb(constmap[i][s]+offset,map,tl);
2736 else
2737 #endif
dadf55f2 2738 emit_readword_indexed_tlb(0,a,map,tl);
57871462 2739 }
535d208a 2740 if(jaddr)
2741 add_stub(LOADW_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
2742 }
2743 else {
2744 inline_readstub(LOADW_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
57871462 2745 }
535d208a 2746 emit_zeroreg(th);
2747 }
2748 if (opcode[i]==0x37) { // LD
2749 if(!c||memtarget) {
2750 if(!dummy) {
dadf55f2 2751 int a=addr;
b1570849 2752 if(fastload_reg_override) a=fastload_reg_override;
57871462 2753 //if(th>=0) emit_readword_indexed((int)rdram-0x80000000,addr,th);
2754 //emit_readword_indexed((int)rdram-0x7FFFFFFC,addr,tl);
2755 #ifdef HOST_IMM_ADDR32
2756 if(c)
2757 emit_readdword_tlb(constmap[i][s]+offset,map,th,tl);
2758 else
2759 #endif
dadf55f2 2760 emit_readdword_indexed_tlb(0,a,map,th,tl);
57871462 2761 }
535d208a 2762 if(jaddr)
2763 add_stub(LOADD_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
57871462 2764 }
535d208a 2765 else
2766 inline_readstub(LOADD_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
57871462 2767 }
535d208a 2768 }
2769 //emit_storereg(rt1[i],tl); // DEBUG
57871462 2770 //if(opcode[i]==0x23)
2771 //if(opcode[i]==0x24)
2772 //if(opcode[i]==0x23||opcode[i]==0x24)
2773 /*if(opcode[i]==0x21||opcode[i]==0x23||opcode[i]==0x24)
2774 {
2775 //emit_pusha();
2776 save_regs(0x100f);
2777 emit_readword((int)&last_count,ECX);
2778 #ifdef __i386__
2779 if(get_reg(i_regs->regmap,CCREG)<0)
2780 emit_loadreg(CCREG,HOST_CCREG);
2781 emit_add(HOST_CCREG,ECX,HOST_CCREG);
2782 emit_addimm(HOST_CCREG,2*ccadj[i],HOST_CCREG);
2783 emit_writeword(HOST_CCREG,(int)&Count);
2784 #endif
2785 #ifdef __arm__
2786 if(get_reg(i_regs->regmap,CCREG)<0)
2787 emit_loadreg(CCREG,0);
2788 else
2789 emit_mov(HOST_CCREG,0);
2790 emit_add(0,ECX,0);
2791 emit_addimm(0,2*ccadj[i],0);
2792 emit_writeword(0,(int)&Count);
2793 #endif
2794 emit_call((int)memdebug);
2795 //emit_popa();
2796 restore_regs(0x100f);
581335b0 2797 }*/
57871462 2798}
2799
2800#ifndef loadlr_assemble
2801void loadlr_assemble(int i,struct regstat *i_regs)
2802{
2803 printf("Need loadlr_assemble for this architecture.\n");
2804 exit(1);
2805}
2806#endif
2807
2808void store_assemble(int i,struct regstat *i_regs)
2809{
2810 int s,th,tl,map=-1;
2811 int addr,temp;
2812 int offset;
581335b0 2813 int jaddr=0,type;
666a299d 2814 int memtarget=0,c=0;
57871462 2815 int agr=AGEN1+(i&1);
b1570849 2816 int faststore_reg_override=0;
57871462 2817 u_int hr,reglist=0;
2818 th=get_reg(i_regs->regmap,rs2[i]|64);
2819 tl=get_reg(i_regs->regmap,rs2[i]);
2820 s=get_reg(i_regs->regmap,rs1[i]);
2821 temp=get_reg(i_regs->regmap,agr);
2822 if(temp<0) temp=get_reg(i_regs->regmap,-1);
2823 offset=imm[i];
2824 if(s>=0) {
2825 c=(i_regs->wasconst>>s)&1;
af4ee1fe 2826 if(c) {
2827 memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
af4ee1fe 2828 }
57871462 2829 }
2830 assert(tl>=0);
2831 assert(temp>=0);
2832 for(hr=0;hr<HOST_REGS;hr++) {
2833 if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
2834 }
2835 if(i_regs->regmap[HOST_CCREG]==CCREG) reglist&=~(1<<HOST_CCREG);
2836 if(offset||s<0||c) addr=temp;
2837 else addr=s;
1edfcc68 2838 if(!c) {
2839 jaddr=emit_fastpath_cmp_jump(i,addr,&faststore_reg_override);
2840 }
2841 else if(ram_offset&&memtarget) {
2842 emit_addimm(addr,ram_offset,HOST_TEMPREG);
2843 faststore_reg_override=HOST_TEMPREG;
57871462 2844 }
2845
2846 if (opcode[i]==0x28) { // SB
2847 if(!c||memtarget) {
97a238a6 2848 int x=0,a=temp;
2002a1db 2849#ifdef BIG_ENDIAN_MIPS
57871462 2850 if(!c) emit_xorimm(addr,3,temp);
2851 else x=((constmap[i][s]+offset)^3)-(constmap[i][s]+offset);
2002a1db 2852#else
97a238a6 2853 if(!c) a=addr;
dadf55f2 2854#endif
b1570849 2855 if(faststore_reg_override) a=faststore_reg_override;
57871462 2856 //emit_writebyte_indexed(tl,(int)rdram-0x80000000,temp);
97a238a6 2857 emit_writebyte_indexed_tlb(tl,x,a,map,a);
57871462 2858 }
2859 type=STOREB_STUB;
2860 }
2861 if (opcode[i]==0x29) { // SH
2862 if(!c||memtarget) {
97a238a6 2863 int x=0,a=temp;
2002a1db 2864#ifdef BIG_ENDIAN_MIPS
57871462 2865 if(!c) emit_xorimm(addr,2,temp);
2866 else x=((constmap[i][s]+offset)^2)-(constmap[i][s]+offset);
2002a1db 2867#else
97a238a6 2868 if(!c) a=addr;
dadf55f2 2869#endif
b1570849 2870 if(faststore_reg_override) a=faststore_reg_override;
57871462 2871 //#ifdef
2872 //emit_writehword_indexed_tlb(tl,x,temp,map,temp);
2873 //#else
2874 if(map>=0) {
97a238a6 2875 emit_writehword_indexed(tl,x,a);
57871462 2876 }else
a327ad27 2877 //emit_writehword_indexed(tl,(int)rdram-0x80000000+x,a);
2878 emit_writehword_indexed(tl,x,a);
57871462 2879 }
2880 type=STOREH_STUB;
2881 }
2882 if (opcode[i]==0x2B) { // SW
dadf55f2 2883 if(!c||memtarget) {
2884 int a=addr;
b1570849 2885 if(faststore_reg_override) a=faststore_reg_override;
57871462 2886 //emit_writeword_indexed(tl,(int)rdram-0x80000000,addr);
dadf55f2 2887 emit_writeword_indexed_tlb(tl,0,a,map,temp);
2888 }
57871462 2889 type=STOREW_STUB;
2890 }
2891 if (opcode[i]==0x3F) { // SD
2892 if(!c||memtarget) {
dadf55f2 2893 int a=addr;
b1570849 2894 if(faststore_reg_override) a=faststore_reg_override;
57871462 2895 if(rs2[i]) {
2896 assert(th>=0);
2897 //emit_writeword_indexed(th,(int)rdram-0x80000000,addr);
2898 //emit_writeword_indexed(tl,(int)rdram-0x7FFFFFFC,addr);
dadf55f2 2899 emit_writedword_indexed_tlb(th,tl,0,a,map,temp);
57871462 2900 }else{
2901 // Store zero
2902 //emit_writeword_indexed(tl,(int)rdram-0x80000000,temp);
2903 //emit_writeword_indexed(tl,(int)rdram-0x7FFFFFFC,temp);
dadf55f2 2904 emit_writedword_indexed_tlb(tl,tl,0,a,map,temp);
57871462 2905 }
2906 }
2907 type=STORED_STUB;
2908 }
b96d3df7 2909 if(jaddr) {
2910 // PCSX store handlers don't check invcode again
2911 reglist|=1<<addr;
2912 add_stub(type,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
2913 jaddr=0;
2914 }
1edfcc68 2915 if(!(i_regs->waswritten&(1<<rs1[i]))&&!(new_dynarec_hacks&NDHACK_NO_SMC_CHECK)) {
57871462 2916 if(!c||memtarget) {
2917 #ifdef DESTRUCTIVE_SHIFT
2918 // The x86 shift operation is 'destructive'; it overwrites the
2919 // source register, so we need to make a copy first and use that.
2920 addr=temp;
2921 #endif
2922 #if defined(HOST_IMM8)
2923 int ir=get_reg(i_regs->regmap,INVCP);
2924 assert(ir>=0);
2925 emit_cmpmem_indexedsr12_reg(ir,addr,1);
2926 #else
2927 emit_cmpmem_indexedsr12_imm((int)invalid_code,addr,1);
2928 #endif
0bbd1454 2929 #if defined(HAVE_CONDITIONAL_CALL) && !defined(DESTRUCTIVE_SHIFT)
2930 emit_callne(invalidate_addr_reg[addr]);
2931 #else
581335b0 2932 int jaddr2=(int)out;
57871462 2933 emit_jne(0);
2934 add_stub(INVCODE_STUB,jaddr2,(int)out,reglist|(1<<HOST_CCREG),addr,0,0,0);
0bbd1454 2935 #endif
57871462 2936 }
2937 }
7a518516 2938 u_int addr_val=constmap[i][s]+offset;
3eaa7048 2939 if(jaddr) {
2940 add_stub(type,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
2941 } else if(c&&!memtarget) {
7a518516 2942 inline_writestub(type,i,addr_val,i_regs->regmap,rs2[i],ccadj[i],reglist);
2943 }
2944 // basic current block modification detection..
2945 // not looking back as that should be in mips cache already
2946 if(c&&start+i*4<addr_val&&addr_val<start+slen*4) {
c43b5311 2947 SysPrintf("write to %08x hits block %08x, pc=%08x\n",addr_val,start,start+i*4);
7a518516 2948 assert(i_regs->regmap==regs[i].regmap); // not delay slot
2949 if(i_regs->regmap==regs[i].regmap) {
2950 load_all_consts(regs[i].regmap_entry,regs[i].was32,regs[i].wasdirty,i);
2951 wb_dirtys(regs[i].regmap_entry,regs[i].was32,regs[i].wasdirty);
2952 emit_movimm(start+i*4+4,0);
2953 emit_writeword(0,(int)&pcaddr);
2954 emit_jmp((int)do_interrupt);
2955 }
3eaa7048 2956 }
57871462 2957 //if(opcode[i]==0x2B || opcode[i]==0x3F)
2958 //if(opcode[i]==0x2B || opcode[i]==0x28)
2959 //if(opcode[i]==0x2B || opcode[i]==0x29)
2960 //if(opcode[i]==0x2B)
2961 /*if(opcode[i]==0x2B || opcode[i]==0x28 || opcode[i]==0x29 || opcode[i]==0x3F)
2962 {
28d74ee8 2963 #ifdef __i386__
2964 emit_pusha();
2965 #endif
2966 #ifdef __arm__
57871462 2967 save_regs(0x100f);
28d74ee8 2968 #endif
57871462 2969 emit_readword((int)&last_count,ECX);
2970 #ifdef __i386__
2971 if(get_reg(i_regs->regmap,CCREG)<0)
2972 emit_loadreg(CCREG,HOST_CCREG);
2973 emit_add(HOST_CCREG,ECX,HOST_CCREG);
2974 emit_addimm(HOST_CCREG,2*ccadj[i],HOST_CCREG);
2975 emit_writeword(HOST_CCREG,(int)&Count);
2976 #endif
2977 #ifdef __arm__
2978 if(get_reg(i_regs->regmap,CCREG)<0)
2979 emit_loadreg(CCREG,0);
2980 else
2981 emit_mov(HOST_CCREG,0);
2982 emit_add(0,ECX,0);
2983 emit_addimm(0,2*ccadj[i],0);
2984 emit_writeword(0,(int)&Count);
2985 #endif
2986 emit_call((int)memdebug);
28d74ee8 2987 #ifdef __i386__
2988 emit_popa();
2989 #endif
2990 #ifdef __arm__
57871462 2991 restore_regs(0x100f);
28d74ee8 2992 #endif
581335b0 2993 }*/
57871462 2994}
2995
2996void storelr_assemble(int i,struct regstat *i_regs)
2997{
2998 int s,th,tl;
2999 int temp;
581335b0 3000 int temp2=-1;
57871462 3001 int offset;
581335b0 3002 int jaddr=0;
57871462 3003 int case1,case2,case3;
3004 int done0,done1,done2;
af4ee1fe 3005 int memtarget=0,c=0;
fab5d06d 3006 int agr=AGEN1+(i&1);
57871462 3007 u_int hr,reglist=0;
3008 th=get_reg(i_regs->regmap,rs2[i]|64);
3009 tl=get_reg(i_regs->regmap,rs2[i]);
3010 s=get_reg(i_regs->regmap,rs1[i]);
fab5d06d 3011 temp=get_reg(i_regs->regmap,agr);
3012 if(temp<0) temp=get_reg(i_regs->regmap,-1);
57871462 3013 offset=imm[i];
3014 if(s>=0) {
3015 c=(i_regs->isconst>>s)&1;
af4ee1fe 3016 if(c) {
3017 memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
af4ee1fe 3018 }
57871462 3019 }
3020 assert(tl>=0);
3021 for(hr=0;hr<HOST_REGS;hr++) {
3022 if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
3023 }
535d208a 3024 assert(temp>=0);
1edfcc68 3025 if(!c) {
3026 emit_cmpimm(s<0||offset?temp:s,RAM_SIZE);
3027 if(!offset&&s!=temp) emit_mov(s,temp);
3028 jaddr=(int)out;
3029 emit_jno(0);
3030 }
3031 else
3032 {
3033 if(!memtarget||!rs1[i]) {
535d208a 3034 jaddr=(int)out;
3035 emit_jmp(0);
57871462 3036 }
535d208a 3037 }
1edfcc68 3038 #ifdef RAM_OFFSET
3039 int map=get_reg(i_regs->regmap,ROREG);
3040 if(map<0) emit_loadreg(ROREG,map=HOST_TEMPREG);
3041 #else
9f51b4b9 3042 if((u_int)rdram!=0x80000000)
1edfcc68 3043 emit_addimm_no_flags((u_int)rdram-(u_int)0x80000000,temp);
3044 #endif
535d208a 3045
3046 if (opcode[i]==0x2C||opcode[i]==0x2D) { // SDL/SDR
3047 temp2=get_reg(i_regs->regmap,FTEMP);
3048 if(!rs2[i]) temp2=th=tl;
3049 }
57871462 3050
2002a1db 3051#ifndef BIG_ENDIAN_MIPS
3052 emit_xorimm(temp,3,temp);
3053#endif
535d208a 3054 emit_testimm(temp,2);
3055 case2=(int)out;
3056 emit_jne(0);
3057 emit_testimm(temp,1);
3058 case1=(int)out;
3059 emit_jne(0);
3060 // 0
3061 if (opcode[i]==0x2A) { // SWL
3062 emit_writeword_indexed(tl,0,temp);
3063 }
3064 if (opcode[i]==0x2E) { // SWR
3065 emit_writebyte_indexed(tl,3,temp);
3066 }
3067 if (opcode[i]==0x2C) { // SDL
3068 emit_writeword_indexed(th,0,temp);
3069 if(rs2[i]) emit_mov(tl,temp2);
3070 }
3071 if (opcode[i]==0x2D) { // SDR
3072 emit_writebyte_indexed(tl,3,temp);
3073 if(rs2[i]) emit_shldimm(th,tl,24,temp2);
3074 }
3075 done0=(int)out;
3076 emit_jmp(0);
3077 // 1
3078 set_jump_target(case1,(int)out);
3079 if (opcode[i]==0x2A) { // SWL
3080 // Write 3 msb into three least significant bytes
3081 if(rs2[i]) emit_rorimm(tl,8,tl);
3082 emit_writehword_indexed(tl,-1,temp);
3083 if(rs2[i]) emit_rorimm(tl,16,tl);
3084 emit_writebyte_indexed(tl,1,temp);
3085 if(rs2[i]) emit_rorimm(tl,8,tl);
3086 }
3087 if (opcode[i]==0x2E) { // SWR
3088 // Write two lsb into two most significant bytes
3089 emit_writehword_indexed(tl,1,temp);
3090 }
3091 if (opcode[i]==0x2C) { // SDL
3092 if(rs2[i]) emit_shrdimm(tl,th,8,temp2);
3093 // Write 3 msb into three least significant bytes
3094 if(rs2[i]) emit_rorimm(th,8,th);
3095 emit_writehword_indexed(th,-1,temp);
3096 if(rs2[i]) emit_rorimm(th,16,th);
3097 emit_writebyte_indexed(th,1,temp);
3098 if(rs2[i]) emit_rorimm(th,8,th);
3099 }
3100 if (opcode[i]==0x2D) { // SDR
3101 if(rs2[i]) emit_shldimm(th,tl,16,temp2);
3102 // Write two lsb into two most significant bytes
3103 emit_writehword_indexed(tl,1,temp);
3104 }
3105 done1=(int)out;
3106 emit_jmp(0);
3107 // 2
3108 set_jump_target(case2,(int)out);
3109 emit_testimm(temp,1);
3110 case3=(int)out;
3111 emit_jne(0);
3112 if (opcode[i]==0x2A) { // SWL
3113 // Write two msb into two least significant bytes
3114 if(rs2[i]) emit_rorimm(tl,16,tl);
3115 emit_writehword_indexed(tl,-2,temp);
3116 if(rs2[i]) emit_rorimm(tl,16,tl);
3117 }
3118 if (opcode[i]==0x2E) { // SWR
3119 // Write 3 lsb into three most significant bytes
3120 emit_writebyte_indexed(tl,-1,temp);
3121 if(rs2[i]) emit_rorimm(tl,8,tl);
3122 emit_writehword_indexed(tl,0,temp);
3123 if(rs2[i]) emit_rorimm(tl,24,tl);
3124 }
3125 if (opcode[i]==0x2C) { // SDL
3126 if(rs2[i]) emit_shrdimm(tl,th,16,temp2);
3127 // Write two msb into two least significant bytes
3128 if(rs2[i]) emit_rorimm(th,16,th);
3129 emit_writehword_indexed(th,-2,temp);
3130 if(rs2[i]) emit_rorimm(th,16,th);
3131 }
3132 if (opcode[i]==0x2D) { // SDR
3133 if(rs2[i]) emit_shldimm(th,tl,8,temp2);
3134 // Write 3 lsb into three most significant bytes
3135 emit_writebyte_indexed(tl,-1,temp);
3136 if(rs2[i]) emit_rorimm(tl,8,tl);
3137 emit_writehword_indexed(tl,0,temp);
3138 if(rs2[i]) emit_rorimm(tl,24,tl);
3139 }
3140 done2=(int)out;
3141 emit_jmp(0);
3142 // 3
3143 set_jump_target(case3,(int)out);
3144 if (opcode[i]==0x2A) { // SWL
3145 // Write msb into least significant byte
3146 if(rs2[i]) emit_rorimm(tl,24,tl);
3147 emit_writebyte_indexed(tl,-3,temp);
3148 if(rs2[i]) emit_rorimm(tl,8,tl);
3149 }
3150 if (opcode[i]==0x2E) { // SWR
3151 // Write entire word
3152 emit_writeword_indexed(tl,-3,temp);
3153 }
3154 if (opcode[i]==0x2C) { // SDL
3155 if(rs2[i]) emit_shrdimm(tl,th,24,temp2);
3156 // Write msb into least significant byte
3157 if(rs2[i]) emit_rorimm(th,24,th);
3158 emit_writebyte_indexed(th,-3,temp);
3159 if(rs2[i]) emit_rorimm(th,8,th);
3160 }
3161 if (opcode[i]==0x2D) { // SDR
3162 if(rs2[i]) emit_mov(th,temp2);
3163 // Write entire word
3164 emit_writeword_indexed(tl,-3,temp);
3165 }
3166 set_jump_target(done0,(int)out);
3167 set_jump_target(done1,(int)out);
3168 set_jump_target(done2,(int)out);
3169 if (opcode[i]==0x2C) { // SDL
3170 emit_testimm(temp,4);
57871462 3171 done0=(int)out;
57871462 3172 emit_jne(0);
535d208a 3173 emit_andimm(temp,~3,temp);
3174 emit_writeword_indexed(temp2,4,temp);
3175 set_jump_target(done0,(int)out);
3176 }
3177 if (opcode[i]==0x2D) { // SDR
3178 emit_testimm(temp,4);
3179 done0=(int)out;
3180 emit_jeq(0);
3181 emit_andimm(temp,~3,temp);
3182 emit_writeword_indexed(temp2,-4,temp);
57871462 3183 set_jump_target(done0,(int)out);
57871462 3184 }
535d208a 3185 if(!c||!memtarget)
3186 add_stub(STORELR_STUB,jaddr,(int)out,i,(int)i_regs,temp,ccadj[i],reglist);
1edfcc68 3187 if(!(i_regs->waswritten&(1<<rs1[i]))&&!(new_dynarec_hacks&NDHACK_NO_SMC_CHECK)) {
535d208a 3188 #ifdef RAM_OFFSET
3189 int map=get_reg(i_regs->regmap,ROREG);
3190 if(map<0) map=HOST_TEMPREG;
3191 gen_orig_addr_w(temp,map);
3192 #else
57871462 3193 emit_addimm_no_flags((u_int)0x80000000-(u_int)rdram,temp);
535d208a 3194 #endif
57871462 3195 #if defined(HOST_IMM8)
3196 int ir=get_reg(i_regs->regmap,INVCP);
3197 assert(ir>=0);
3198 emit_cmpmem_indexedsr12_reg(ir,temp,1);
3199 #else
3200 emit_cmpmem_indexedsr12_imm((int)invalid_code,temp,1);
3201 #endif
535d208a 3202 #if defined(HAVE_CONDITIONAL_CALL) && !defined(DESTRUCTIVE_SHIFT)
3203 emit_callne(invalidate_addr_reg[temp]);
3204 #else
581335b0 3205 int jaddr2=(int)out;
57871462 3206 emit_jne(0);
3207 add_stub(INVCODE_STUB,jaddr2,(int)out,reglist|(1<<HOST_CCREG),temp,0,0,0);
535d208a 3208 #endif
57871462 3209 }
3210 /*
3211 emit_pusha();
3212 //save_regs(0x100f);
3213 emit_readword((int)&last_count,ECX);
3214 if(get_reg(i_regs->regmap,CCREG)<0)
3215 emit_loadreg(CCREG,HOST_CCREG);
3216 emit_add(HOST_CCREG,ECX,HOST_CCREG);
3217 emit_addimm(HOST_CCREG,2*ccadj[i],HOST_CCREG);
3218 emit_writeword(HOST_CCREG,(int)&Count);
3219 emit_call((int)memdebug);
3220 emit_popa();
3221 //restore_regs(0x100f);
581335b0 3222 */