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drc: a bit more sophisticated f1 hack
[pcsx_rearmed.git] / libpcsxcore / new_dynarec / new_dynarec.c
CommitLineData
57871462 1/* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
2 * Mupen64plus - new_dynarec.c *
20d507ba 3 * Copyright (C) 2009-2011 Ari64 *
57871462 4 * *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
9 * *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
14 * *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. *
19 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */
20
21#include <stdlib.h>
22#include <stdint.h> //include for uint64_t
23#include <assert.h>
d848b60a 24#include <errno.h>
4600ba03 25#include <sys/mman.h>
d148d265 26#ifdef __MACH__
27#include <libkern/OSCacheControl.h>
28#endif
1e212a25 29#ifdef _3DS
30#include <3ds_utils.h>
31#endif
57871462 32
d148d265 33#include "new_dynarec_config.h"
3968e69e 34#include "../psxhle.h"
35#include "../psxinterpreter.h"
81dbbf4c 36#include "../gte.h"
37#include "emu_if.h" // emulator interface
57871462 38
d1e4ebd9 39#define noinline __attribute__((noinline,noclone))
b14b6a8f 40#ifndef ARRAY_SIZE
41#define ARRAY_SIZE(x) (sizeof(x) / sizeof(x[0]))
42#endif
e3c6bdb5 43#ifndef min
44#define min(a, b) ((b) < (a) ? (b) : (a))
45#endif
32631e6a 46#ifndef max
47#define max(a, b) ((b) > (a) ? (b) : (a))
48#endif
b14b6a8f 49
4600ba03 50//#define DISASM
32631e6a 51//#define ASSEM_PRINT
52
53#ifdef ASSEM_PRINT
54#define assem_debug printf
55#else
4600ba03 56#define assem_debug(...)
32631e6a 57#endif
58//#define inv_debug printf
4600ba03 59#define inv_debug(...)
57871462 60
61#ifdef __i386__
62#include "assem_x86.h"
63#endif
64#ifdef __x86_64__
65#include "assem_x64.h"
66#endif
67#ifdef __arm__
68#include "assem_arm.h"
69#endif
be516ebe 70#ifdef __aarch64__
71#include "assem_arm64.h"
72#endif
57871462 73
81dbbf4c 74#define RAM_SIZE 0x200000
57871462 75#define MAXBLOCK 4096
76#define MAX_OUTPUT_BLOCK_SIZE 262144
2573466a 77
2a014d73 78struct ndrc_mem
79{
80 u_char translation_cache[1 << TARGET_SIZE_2];
81 struct
82 {
83 struct tramp_insns ops[2048 / sizeof(struct tramp_insns)];
84 const void *f[2048 / sizeof(void *)];
85 } tramp;
86};
87
88#ifdef BASE_ADDR_DYNAMIC
89static struct ndrc_mem *ndrc;
90#else
91static struct ndrc_mem ndrc_ __attribute__((aligned(4096)));
92static struct ndrc_mem *ndrc = &ndrc_;
93#endif
94
b14b6a8f 95// stubs
96enum stub_type {
97 CC_STUB = 1,
98 FP_STUB = 2,
99 LOADB_STUB = 3,
100 LOADH_STUB = 4,
101 LOADW_STUB = 5,
102 LOADD_STUB = 6,
103 LOADBU_STUB = 7,
104 LOADHU_STUB = 8,
105 STOREB_STUB = 9,
106 STOREH_STUB = 10,
107 STOREW_STUB = 11,
108 STORED_STUB = 12,
109 STORELR_STUB = 13,
110 INVCODE_STUB = 14,
111};
112
57871462 113struct regstat
114{
2330734f 115 signed char regmap_entry[HOST_REGS]; // pre-insn + loop preloaded regs?
57871462 116 signed char regmap[HOST_REGS];
57871462 117 uint64_t wasdirty;
118 uint64_t dirty;
119 uint64_t u;
24058131 120 u_int wasconst; // before; for example 'lw r2, (r2)' wasconst is true
121 u_int isconst; // ... but isconst is false when r2 is known
8575a877 122 u_int loadedconst; // host regs that have constants loaded
123 u_int waswritten; // MIPS regs that were used as store base before
57871462 124};
125
de5a60c3 126// note: asm depends on this layout
57871462 127struct ll_entry
128{
129 u_int vaddr;
de5a60c3 130 u_int reg_sv_flags;
57871462 131 void *addr;
132 struct ll_entry *next;
133};
134
df4dc2b1 135struct ht_entry
136{
137 u_int vaddr[2];
138 void *tcaddr[2];
139};
140
b14b6a8f 141struct code_stub
142{
143 enum stub_type type;
144 void *addr;
145 void *retaddr;
146 u_int a;
147 uintptr_t b;
148 uintptr_t c;
149 u_int d;
150 u_int e;
151};
152
643aeae3 153struct link_entry
154{
155 void *addr;
156 u_int target;
157 u_int ext;
158};
159
cf95b4f0 160static struct decoded_insn
161{
162 u_char itype;
163 u_char opcode;
164 u_char opcode2;
165 u_char rs1;
166 u_char rs2;
167 u_char rt1;
168 u_char rt2;
169 u_char lt1;
170 u_char bt:1;
cf95b4f0 171 u_char ooo:1;
172 u_char is_ds:1;
fe807a8a 173 u_char is_jump:1;
174 u_char is_ujump:1;
37387d8b 175 u_char is_load:1;
176 u_char is_store:1;
cf95b4f0 177} dops[MAXBLOCK];
178
e2b5e7aa 179 // used by asm:
180 u_char *out;
df4dc2b1 181 struct ht_entry hash_table[65536] __attribute__((aligned(16)));
e2b5e7aa 182 struct ll_entry *jump_in[4096] __attribute__((aligned(16)));
183 struct ll_entry *jump_dirty[4096];
184
185 static struct ll_entry *jump_out[4096];
186 static u_int start;
187 static u_int *source;
188 static char insn[MAXBLOCK][10];
bedfea38 189 static uint64_t gte_rs[MAXBLOCK]; // gte: 32 data and 32 ctl regs
190 static uint64_t gte_rt[MAXBLOCK];
191 static uint64_t gte_unneeded[MAXBLOCK];
ffb0b9e0 192 static u_int smrv[32]; // speculated MIPS register values
193 static u_int smrv_strong; // mask or regs that are likely to have correct values
194 static u_int smrv_weak; // same, but somewhat less likely
195 static u_int smrv_strong_next; // same, but after current insn executes
196 static u_int smrv_weak_next;
e2b5e7aa 197 static int imm[MAXBLOCK];
198 static u_int ba[MAXBLOCK];
e2b5e7aa 199 static uint64_t unneeded_reg[MAXBLOCK];
e2b5e7aa 200 static uint64_t branch_unneeded_reg[MAXBLOCK];
2330734f 201 // pre-instruction [i], excluding loop-preload regs?
202 static signed char regmap_pre[MAXBLOCK][HOST_REGS];
40fca85b 203 // contains 'real' consts at [i] insn, but may differ from what's actually
204 // loaded in host reg as 'final' value is always loaded, see get_final_value()
205 static uint32_t current_constmap[HOST_REGS];
206 static uint32_t constmap[MAXBLOCK][HOST_REGS];
956f3129 207 static struct regstat regs[MAXBLOCK];
208 static struct regstat branch_regs[MAXBLOCK];
e2b5e7aa 209 static signed char minimum_free_regs[MAXBLOCK];
210 static u_int needed_reg[MAXBLOCK];
211 static u_int wont_dirty[MAXBLOCK];
212 static u_int will_dirty[MAXBLOCK];
213 static int ccadj[MAXBLOCK];
214 static int slen;
df4dc2b1 215 static void *instr_addr[MAXBLOCK];
643aeae3 216 static struct link_entry link_addr[MAXBLOCK];
e2b5e7aa 217 static int linkcount;
b14b6a8f 218 static struct code_stub stubs[MAXBLOCK*3];
e2b5e7aa 219 static int stubcount;
220 static u_int literals[1024][2];
221 static int literalcount;
222 static int is_delayslot;
e2b5e7aa 223 static char shadow[1048576] __attribute__((aligned(16)));
224 static void *copy;
225 static int expirep;
226 static u_int stop_after_jal;
7f94b097 227 static u_int f1_hack;
e2b5e7aa 228
229 int new_dynarec_hacks;
d62c125a 230 int new_dynarec_hacks_pergame;
32631e6a 231 int new_dynarec_hacks_old;
e2b5e7aa 232 int new_dynarec_did_compile;
687b4580 233
d62c125a 234 #define HACK_ENABLED(x) ((new_dynarec_hacks | new_dynarec_hacks_pergame) & (x))
235
687b4580 236 extern int cycle_count; // ... until end of the timeslice, counts -N -> 0
237 extern int last_count; // last absolute target, often = next_interupt
238 extern int pcaddr;
239 extern int pending_exception;
240 extern int branch_target;
37387d8b 241 extern uintptr_t ram_offset;
d1e4ebd9 242 extern uintptr_t mini_ht[32][2];
57871462 243 extern u_char restore_candidate[512];
57871462 244
245 /* registers that may be allocated */
246 /* 1-31 gpr */
7c3a5182 247#define LOREG 32 // lo
248#define HIREG 33 // hi
00fa9369 249//#define FSREG 34 // FPU status (FCSR)
57871462 250#define CSREG 35 // Coprocessor status
251#define CCREG 36 // Cycle count
252#define INVCP 37 // Pointer to invalid_code
1edfcc68 253//#define MMREG 38 // Pointer to memory_map
37387d8b 254#define ROREG 39 // ram offset (if rdram!=0x80000000)
619e5ded 255#define TEMPREG 40
256#define FTEMP 40 // FPU temporary register
257#define PTEMP 41 // Prefetch temporary register
1edfcc68 258//#define TLREG 42 // TLB mapping offset
619e5ded 259#define RHASH 43 // Return address hash
260#define RHTBL 44 // Return address hash table address
261#define RTEMP 45 // JR/JALR address register
262#define MAXREG 45
263#define AGEN1 46 // Address generation temporary register
1edfcc68 264//#define AGEN2 47 // Address generation temporary register
265//#define MGEN1 48 // Maptable address generation temporary register
266//#define MGEN2 49 // Maptable address generation temporary register
619e5ded 267#define BTREG 50 // Branch target temporary register
57871462 268
269 /* instruction types */
270#define NOP 0 // No operation
271#define LOAD 1 // Load
272#define STORE 2 // Store
273#define LOADLR 3 // Unaligned load
274#define STORELR 4 // Unaligned store
9f51b4b9 275#define MOV 5 // Move
57871462 276#define ALU 6 // Arithmetic/logic
277#define MULTDIV 7 // Multiply/divide
278#define SHIFT 8 // Shift by register
279#define SHIFTIMM 9// Shift by immediate
280#define IMM16 10 // 16-bit immediate
281#define RJUMP 11 // Unconditional jump to register
282#define UJUMP 12 // Unconditional jump
283#define CJUMP 13 // Conditional branch (BEQ/BNE/BGTZ/BLEZ)
284#define SJUMP 14 // Conditional branch (regimm format)
285#define COP0 15 // Coprocessor 0
286#define COP1 16 // Coprocessor 1
287#define C1LS 17 // Coprocessor 1 load/store
ad49de89 288//#define FJUMP 18 // Conditional branch (floating point)
00fa9369 289//#define FLOAT 19 // Floating point unit
290//#define FCONV 20 // Convert integer to float
291//#define FCOMP 21 // Floating point compare (sets FSREG)
57871462 292#define SYSCALL 22// SYSCALL
293#define OTHER 23 // Other
294#define SPAN 24 // Branch/delay slot spans 2 pages
295#define NI 25 // Not implemented
7139f3c8 296#define HLECALL 26// PCSX fake opcodes for HLE
b9b61529 297#define COP2 27 // Coprocessor 2 move
298#define C2LS 28 // Coprocessor 2 load/store
299#define C2OP 29 // Coprocessor 2 operation
1e973cb0 300#define INTCALL 30// Call interpreter to handle rare corner cases
57871462 301
57871462 302 /* branch codes */
303#define TAKEN 1
304#define NOTTAKEN 2
305#define NULLDS 3
306
7c3a5182 307#define DJT_1 (void *)1l // no function, just a label in assem_debug log
308#define DJT_2 (void *)2l
309
57871462 310// asm linkage
3968e69e 311int new_recompile_block(u_int addr);
57871462 312void *get_addr_ht(u_int vaddr);
313void invalidate_block(u_int block);
314void invalidate_addr(u_int addr);
315void remove_hash(int vaddr);
57871462 316void dyna_linker();
317void dyna_linker_ds();
318void verify_code();
57871462 319void verify_code_ds();
320void cc_interrupt();
321void fp_exception();
322void fp_exception_ds();
3968e69e 323void jump_to_new_pc();
81dbbf4c 324void call_gteStall();
7139f3c8 325void new_dyna_leave();
57871462 326
57871462 327// Needed by assembler
2330734f 328static void wb_register(signed char r, const signed char regmap[], uint64_t dirty);
329static void wb_dirtys(const signed char i_regmap[], uint64_t i_dirty);
330static void wb_needed_dirtys(const signed char i_regmap[], uint64_t i_dirty, int addr);
331static void load_all_regs(const signed char i_regmap[]);
332static void load_needed_regs(const signed char i_regmap[], const signed char next_regmap[]);
e2b5e7aa 333static void load_regs_entry(int t);
2330734f 334static void load_all_consts(const signed char regmap[], u_int dirty, int i);
81dbbf4c 335static u_int get_host_reglist(const signed char *regmap);
e2b5e7aa 336
3968e69e 337static int verify_dirty(const u_int *ptr);
e2b5e7aa 338static int get_final_value(int hr, int i, int *value);
b14b6a8f 339static void add_stub(enum stub_type type, void *addr, void *retaddr,
340 u_int a, uintptr_t b, uintptr_t c, u_int d, u_int e);
341static void add_stub_r(enum stub_type type, void *addr, void *retaddr,
81dbbf4c 342 int i, int addr_reg, const struct regstat *i_regs, int ccadj, u_int reglist);
643aeae3 343static void add_to_linker(void *addr, u_int target, int ext);
37387d8b 344static void *emit_fastpath_cmp_jump(int i, const struct regstat *i_regs,
345 int addr, int *offset_reg, int *addr_reg_override);
687b4580 346static void *get_direct_memhandler(void *table, u_int addr,
347 enum stub_type type, uintptr_t *addr_host);
32631e6a 348static void cop2_do_stall_check(u_int op, int i, const struct regstat *i_regs, u_int reglist);
687b4580 349static void pass_args(int a0, int a1);
2a014d73 350static void emit_far_jump(const void *f);
351static void emit_far_call(const void *f);
57871462 352
9c67c98f 353#ifdef VITA
354#include <psp2/kernel/sysmem.h>
355static int sceBlock;
356// note: this interacts with RetroArch's Vita bootstrap code: bootstrap/vita/sbrk.c
357extern int getVMBlock();
358int _newlib_vm_size_user = sizeof(*ndrc);
359#endif
360
d148d265 361static void mprotect_w_x(void *start, void *end, int is_x)
362{
363#ifdef NO_WRITE_EXEC
1e212a25 364 #if defined(VITA)
365 // *Open* enables write on all memory that was
366 // allocated by sceKernelAllocMemBlockForVM()?
367 if (is_x)
368 sceKernelCloseVMDomain();
369 else
370 sceKernelOpenVMDomain();
371 #else
d148d265 372 u_long mstart = (u_long)start & ~4095ul;
373 u_long mend = (u_long)end;
374 if (mprotect((void *)mstart, mend - mstart,
375 PROT_READ | (is_x ? PROT_EXEC : PROT_WRITE)) != 0)
376 SysPrintf("mprotect(%c) failed: %s\n", is_x ? 'x' : 'w', strerror(errno));
1e212a25 377 #endif
d148d265 378#endif
379}
380
381static void start_tcache_write(void *start, void *end)
382{
383 mprotect_w_x(start, end, 0);
384}
385
386static void end_tcache_write(void *start, void *end)
387{
919981d0 388#if defined(__arm__) || defined(__aarch64__)
d148d265 389 size_t len = (char *)end - (char *)start;
390 #if defined(__BLACKBERRY_QNX__)
391 msync(start, len, MS_SYNC | MS_CACHE_ONLY | MS_INVALIDATE_ICACHE);
392 #elif defined(__MACH__)
393 sys_cache_control(kCacheFunctionPrepareForExecution, start, len);
394 #elif defined(VITA)
1e212a25 395 sceKernelSyncVMDomain(sceBlock, start, len);
396 #elif defined(_3DS)
397 ctr_flush_invalidate_cache();
919981d0 398 #elif defined(__aarch64__)
399 // as of 2021, __clear_cache() is still broken on arm64
400 // so here is a custom one :(
401 clear_cache_arm64(start, end);
d148d265 402 #else
403 __clear_cache(start, end);
404 #endif
405 (void)len;
406#endif
407
408 mprotect_w_x(start, end, 1);
409}
410
411static void *start_block(void)
412{
413 u_char *end = out + MAX_OUTPUT_BLOCK_SIZE;
2a014d73 414 if (end > ndrc->translation_cache + sizeof(ndrc->translation_cache))
415 end = ndrc->translation_cache + sizeof(ndrc->translation_cache);
d148d265 416 start_tcache_write(out, end);
417 return out;
418}
419
420static void end_block(void *start)
421{
422 end_tcache_write(start, out);
423}
424
919981d0 425// also takes care of w^x mappings when patching code
426static u_int needs_clear_cache[1<<(TARGET_SIZE_2-17)];
427
428static void mark_clear_cache(void *target)
429{
430 uintptr_t offset = (u_char *)target - ndrc->translation_cache;
431 u_int mask = 1u << ((offset >> 12) & 31);
432 if (!(needs_clear_cache[offset >> 17] & mask)) {
433 char *start = (char *)((uintptr_t)target & ~4095l);
434 start_tcache_write(start, start + 4095);
435 needs_clear_cache[offset >> 17] |= mask;
436 }
437}
438
439// Clearing the cache is rather slow on ARM Linux, so mark the areas
440// that need to be cleared, and then only clear these areas once.
441static void do_clear_cache(void)
442{
443 int i, j;
444 for (i = 0; i < (1<<(TARGET_SIZE_2-17)); i++)
445 {
446 u_int bitmap = needs_clear_cache[i];
447 if (!bitmap)
448 continue;
449 for (j = 0; j < 32; j++)
450 {
451 u_char *start, *end;
452 if (!(bitmap & (1<<j)))
453 continue;
454
455 start = ndrc->translation_cache + i*131072 + j*4096;
456 end = start + 4095;
457 for (j++; j < 32; j++) {
458 if (!(bitmap & (1<<j)))
459 break;
460 end += 4096;
461 }
462 end_tcache_write(start, end);
463 }
464 needs_clear_cache[i] = 0;
465 }
466}
467
57871462 468//#define DEBUG_CYCLE_COUNT 1
469
b6e87b2b 470#define NO_CYCLE_PENALTY_THR 12
471
26bd3dad 472int cycle_multiplier = CYCLE_MULT_DEFAULT; // 100 for 1.0
a3203cf4 473int cycle_multiplier_override;
32631e6a 474int cycle_multiplier_old;
24058131 475static int cycle_multiplier_active;
4e9dcd7f 476
477static int CLOCK_ADJUST(int x)
478{
24058131 479 int m = cycle_multiplier_active;
480 int s = (x >> 31) | 1;
a3203cf4 481 return (x * m + s * 50) / 100;
4e9dcd7f 482}
483
4919de1e 484static int ds_writes_rjump_rs(int i)
485{
cf95b4f0 486 return dops[i].rs1 != 0 && (dops[i].rs1 == dops[i+1].rt1 || dops[i].rs1 == dops[i+1].rt2);
4919de1e 487}
488
94d23bb9 489static u_int get_page(u_int vaddr)
57871462 490{
0ce47d46 491 u_int page=vaddr&~0xe0000000;
492 if (page < 0x1000000)
493 page &= ~0x0e00000; // RAM mirrors
494 page>>=12;
57871462 495 if(page>2048) page=2048+(page&2047);
94d23bb9 496 return page;
497}
498
d25604ca 499// no virtual mem in PCSX
500static u_int get_vpage(u_int vaddr)
501{
502 return get_page(vaddr);
503}
94d23bb9 504
df4dc2b1 505static struct ht_entry *hash_table_get(u_int vaddr)
506{
507 return &hash_table[((vaddr>>16)^vaddr)&0xFFFF];
508}
509
510static void hash_table_add(struct ht_entry *ht_bin, u_int vaddr, void *tcaddr)
511{
512 ht_bin->vaddr[1] = ht_bin->vaddr[0];
513 ht_bin->tcaddr[1] = ht_bin->tcaddr[0];
514 ht_bin->vaddr[0] = vaddr;
515 ht_bin->tcaddr[0] = tcaddr;
516}
517
518// some messy ari64's code, seems to rely on unsigned 32bit overflow
519static int doesnt_expire_soon(void *tcaddr)
520{
521 u_int diff = (u_int)((u_char *)tcaddr - out) << (32-TARGET_SIZE_2);
522 return diff > (u_int)(0x60000000 + (MAX_OUTPUT_BLOCK_SIZE << (32-TARGET_SIZE_2)));
523}
524
94d23bb9 525// Get address from virtual address
526// This is called from the recompiled JR/JALR instructions
d1e4ebd9 527void noinline *get_addr(u_int vaddr)
94d23bb9 528{
529 u_int page=get_page(vaddr);
530 u_int vpage=get_vpage(vaddr);
57871462 531 struct ll_entry *head;
532 //printf("TRACE: count=%d next=%d (get_addr %x,page %d)\n",Count,next_interupt,vaddr,page);
533 head=jump_in[page];
534 while(head!=NULL) {
de5a60c3 535 if(head->vaddr==vaddr) {
643aeae3 536 //printf("TRACE: count=%d next=%d (get_addr match %x: %p)\n",Count,next_interupt,vaddr,head->addr);
df4dc2b1 537 hash_table_add(hash_table_get(vaddr), vaddr, head->addr);
57871462 538 return head->addr;
539 }
540 head=head->next;
541 }
542 head=jump_dirty[vpage];
543 while(head!=NULL) {
de5a60c3 544 if(head->vaddr==vaddr) {
643aeae3 545 //printf("TRACE: count=%d next=%d (get_addr match dirty %x: %p)\n",Count,next_interupt,vaddr,head->addr);
57871462 546 // Don't restore blocks which are about to expire from the cache
df4dc2b1 547 if (doesnt_expire_soon(head->addr))
548 if (verify_dirty(head->addr)) {
57871462 549 //printf("restore candidate: %x (%d) d=%d\n",vaddr,page,invalid_code[vaddr>>12]);
550 invalid_code[vaddr>>12]=0;
9be4ba64 551 inv_code_start=inv_code_end=~0;
57871462 552 if(vpage<2048) {
57871462 553 restore_candidate[vpage>>3]|=1<<(vpage&7);
554 }
555 else restore_candidate[page>>3]|=1<<(page&7);
df4dc2b1 556 struct ht_entry *ht_bin = hash_table_get(vaddr);
557 if (ht_bin->vaddr[0] == vaddr)
558 ht_bin->tcaddr[0] = head->addr; // Replace existing entry
57871462 559 else
df4dc2b1 560 hash_table_add(ht_bin, vaddr, head->addr);
561
57871462 562 return head->addr;
563 }
564 }
565 head=head->next;
566 }
567 //printf("TRACE: count=%d next=%d (get_addr no-match %x)\n",Count,next_interupt,vaddr);
568 int r=new_recompile_block(vaddr);
569 if(r==0) return get_addr(vaddr);
570 // Execute in unmapped page, generate pagefault execption
571 Status|=2;
572 Cause=(vaddr<<31)|0x8;
573 EPC=(vaddr&1)?vaddr-5:vaddr;
574 BadVAddr=(vaddr&~1);
575 Context=(Context&0xFF80000F)|((BadVAddr>>9)&0x007FFFF0);
576 EntryHi=BadVAddr&0xFFFFE000;
577 return get_addr_ht(0x80000000);
578}
579// Look up address in hash table first
580void *get_addr_ht(u_int vaddr)
581{
582 //printf("TRACE: count=%d next=%d (get_addr_ht %x)\n",Count,next_interupt,vaddr);
df4dc2b1 583 const struct ht_entry *ht_bin = hash_table_get(vaddr);
584 if (ht_bin->vaddr[0] == vaddr) return ht_bin->tcaddr[0];
585 if (ht_bin->vaddr[1] == vaddr) return ht_bin->tcaddr[1];
57871462 586 return get_addr(vaddr);
587}
588
57871462 589void clear_all_regs(signed char regmap[])
590{
591 int hr;
592 for (hr=0;hr<HOST_REGS;hr++) regmap[hr]=-1;
593}
594
d1e4ebd9 595static signed char get_reg(const signed char regmap[],int r)
57871462 596{
597 int hr;
598 for (hr=0;hr<HOST_REGS;hr++) if(hr!=EXCLUDE_REG&&regmap[hr]==r) return hr;
599 return -1;
600}
601
602// Find a register that is available for two consecutive cycles
d1e4ebd9 603static signed char get_reg2(signed char regmap1[], const signed char regmap2[], int r)
57871462 604{
605 int hr;
606 for (hr=0;hr<HOST_REGS;hr++) if(hr!=EXCLUDE_REG&&regmap1[hr]==r&&regmap2[hr]==r) return hr;
607 return -1;
608}
609
610int count_free_regs(signed char regmap[])
611{
612 int count=0;
613 int hr;
614 for(hr=0;hr<HOST_REGS;hr++)
615 {
616 if(hr!=EXCLUDE_REG) {
617 if(regmap[hr]<0) count++;
618 }
619 }
620 return count;
621}
622
623void dirty_reg(struct regstat *cur,signed char reg)
624{
625 int hr;
626 if(!reg) return;
627 for (hr=0;hr<HOST_REGS;hr++) {
628 if((cur->regmap[hr]&63)==reg) {
629 cur->dirty|=1<<hr;
630 }
631 }
632}
633
40fca85b 634static void set_const(struct regstat *cur, signed char reg, uint32_t value)
57871462 635{
636 int hr;
637 if(!reg) return;
638 for (hr=0;hr<HOST_REGS;hr++) {
639 if(cur->regmap[hr]==reg) {
640 cur->isconst|=1<<hr;
956f3129 641 current_constmap[hr]=value;
57871462 642 }
57871462 643 }
644}
645
40fca85b 646static void clear_const(struct regstat *cur, signed char reg)
57871462 647{
648 int hr;
649 if(!reg) return;
650 for (hr=0;hr<HOST_REGS;hr++) {
651 if((cur->regmap[hr]&63)==reg) {
652 cur->isconst&=~(1<<hr);
653 }
654 }
655}
656
40fca85b 657static int is_const(struct regstat *cur, signed char reg)
57871462 658{
659 int hr;
79c75f1b 660 if(reg<0) return 0;
57871462 661 if(!reg) return 1;
662 for (hr=0;hr<HOST_REGS;hr++) {
663 if((cur->regmap[hr]&63)==reg) {
664 return (cur->isconst>>hr)&1;
665 }
666 }
667 return 0;
668}
40fca85b 669
670static uint32_t get_const(struct regstat *cur, signed char reg)
57871462 671{
672 int hr;
673 if(!reg) return 0;
674 for (hr=0;hr<HOST_REGS;hr++) {
675 if(cur->regmap[hr]==reg) {
956f3129 676 return current_constmap[hr];
57871462 677 }
678 }
c43b5311 679 SysPrintf("Unknown constant in r%d\n",reg);
7c3a5182 680 abort();
57871462 681}
682
683// Least soon needed registers
684// Look at the next ten instructions and see which registers
685// will be used. Try not to reallocate these.
686void lsn(u_char hsn[], int i, int *preferred_reg)
687{
688 int j;
689 int b=-1;
690 for(j=0;j<9;j++)
691 {
692 if(i+j>=slen) {
693 j=slen-i-1;
694 break;
695 }
fe807a8a 696 if (dops[i+j].is_ujump)
57871462 697 {
698 // Don't go past an unconditonal jump
699 j++;
700 break;
701 }
702 }
703 for(;j>=0;j--)
704 {
cf95b4f0 705 if(dops[i+j].rs1) hsn[dops[i+j].rs1]=j;
706 if(dops[i+j].rs2) hsn[dops[i+j].rs2]=j;
707 if(dops[i+j].rt1) hsn[dops[i+j].rt1]=j;
708 if(dops[i+j].rt2) hsn[dops[i+j].rt2]=j;
709 if(dops[i+j].itype==STORE || dops[i+j].itype==STORELR) {
57871462 710 // Stores can allocate zero
cf95b4f0 711 hsn[dops[i+j].rs1]=j;
712 hsn[dops[i+j].rs2]=j;
57871462 713 }
37387d8b 714 if (ram_offset && (dops[i+j].is_load || dops[i+j].is_store))
715 hsn[ROREG] = j;
57871462 716 // On some architectures stores need invc_ptr
717 #if defined(HOST_IMM8)
37387d8b 718 if (dops[i+j].is_store)
719 hsn[INVCP] = j;
57871462 720 #endif
cf95b4f0 721 if(i+j>=0&&(dops[i+j].itype==UJUMP||dops[i+j].itype==CJUMP||dops[i+j].itype==SJUMP))
57871462 722 {
723 hsn[CCREG]=j;
724 b=j;
725 }
726 }
727 if(b>=0)
728 {
729 if(ba[i+b]>=start && ba[i+b]<(start+slen*4))
730 {
731 // Follow first branch
732 int t=(ba[i+b]-start)>>2;
733 j=7-b;if(t+j>=slen) j=slen-t-1;
734 for(;j>=0;j--)
735 {
cf95b4f0 736 if(dops[t+j].rs1) if(hsn[dops[t+j].rs1]>j+b+2) hsn[dops[t+j].rs1]=j+b+2;
737 if(dops[t+j].rs2) if(hsn[dops[t+j].rs2]>j+b+2) hsn[dops[t+j].rs2]=j+b+2;
738 //if(dops[t+j].rt1) if(hsn[dops[t+j].rt1]>j+b+2) hsn[dops[t+j].rt1]=j+b+2;
739 //if(dops[t+j].rt2) if(hsn[dops[t+j].rt2]>j+b+2) hsn[dops[t+j].rt2]=j+b+2;
57871462 740 }
741 }
742 // TODO: preferred register based on backward branch
743 }
744 // Delay slot should preferably not overwrite branch conditions or cycle count
fe807a8a 745 if (i > 0 && dops[i-1].is_jump) {
cf95b4f0 746 if(dops[i-1].rs1) if(hsn[dops[i-1].rs1]>1) hsn[dops[i-1].rs1]=1;
747 if(dops[i-1].rs2) if(hsn[dops[i-1].rs2]>1) hsn[dops[i-1].rs2]=1;
57871462 748 hsn[CCREG]=1;
749 // ...or hash tables
750 hsn[RHASH]=1;
751 hsn[RHTBL]=1;
752 }
753 // Coprocessor load/store needs FTEMP, even if not declared
37387d8b 754 if(dops[i].itype==C2LS) {
57871462 755 hsn[FTEMP]=0;
756 }
757 // Load L/R also uses FTEMP as a temporary register
cf95b4f0 758 if(dops[i].itype==LOADLR) {
57871462 759 hsn[FTEMP]=0;
760 }
b7918751 761 // Also SWL/SWR/SDL/SDR
cf95b4f0 762 if(dops[i].opcode==0x2a||dops[i].opcode==0x2e||dops[i].opcode==0x2c||dops[i].opcode==0x2d) {
57871462 763 hsn[FTEMP]=0;
764 }
57871462 765 // Don't remove the miniht registers
cf95b4f0 766 if(dops[i].itype==UJUMP||dops[i].itype==RJUMP)
57871462 767 {
768 hsn[RHASH]=0;
769 hsn[RHTBL]=0;
770 }
771}
772
773// We only want to allocate registers if we're going to use them again soon
774int needed_again(int r, int i)
775{
776 int j;
777 int b=-1;
778 int rn=10;
9f51b4b9 779
fe807a8a 780 if (i > 0 && dops[i-1].is_ujump)
57871462 781 {
782 if(ba[i-1]<start || ba[i-1]>start+slen*4-4)
783 return 0; // Don't need any registers if exiting the block
784 }
785 for(j=0;j<9;j++)
786 {
787 if(i+j>=slen) {
788 j=slen-i-1;
789 break;
790 }
fe807a8a 791 if (dops[i+j].is_ujump)
57871462 792 {
793 // Don't go past an unconditonal jump
794 j++;
795 break;
796 }
cf95b4f0 797 if(dops[i+j].itype==SYSCALL||dops[i+j].itype==HLECALL||dops[i+j].itype==INTCALL||((source[i+j]&0xfc00003f)==0x0d))
57871462 798 {
799 break;
800 }
801 }
802 for(;j>=1;j--)
803 {
cf95b4f0 804 if(dops[i+j].rs1==r) rn=j;
805 if(dops[i+j].rs2==r) rn=j;
57871462 806 if((unneeded_reg[i+j]>>r)&1) rn=10;
cf95b4f0 807 if(i+j>=0&&(dops[i+j].itype==UJUMP||dops[i+j].itype==CJUMP||dops[i+j].itype==SJUMP))
57871462 808 {
809 b=j;
810 }
811 }
b7217e13 812 if(rn<10) return 1;
581335b0 813 (void)b;
57871462 814 return 0;
815}
816
817// Try to match register allocations at the end of a loop with those
818// at the beginning
819int loop_reg(int i, int r, int hr)
820{
821 int j,k;
822 for(j=0;j<9;j++)
823 {
824 if(i+j>=slen) {
825 j=slen-i-1;
826 break;
827 }
fe807a8a 828 if (dops[i+j].is_ujump)
57871462 829 {
830 // Don't go past an unconditonal jump
831 j++;
832 break;
833 }
834 }
835 k=0;
836 if(i>0){
cf95b4f0 837 if(dops[i-1].itype==UJUMP||dops[i-1].itype==CJUMP||dops[i-1].itype==SJUMP)
57871462 838 k--;
839 }
840 for(;k<j;k++)
841 {
00fa9369 842 assert(r < 64);
843 if((unneeded_reg[i+k]>>r)&1) return hr;
cf95b4f0 844 if(i+k>=0&&(dops[i+k].itype==UJUMP||dops[i+k].itype==CJUMP||dops[i+k].itype==SJUMP))
57871462 845 {
846 if(ba[i+k]>=start && ba[i+k]<(start+i*4))
847 {
848 int t=(ba[i+k]-start)>>2;
849 int reg=get_reg(regs[t].regmap_entry,r);
850 if(reg>=0) return reg;
851 //reg=get_reg(regs[t+1].regmap_entry,r);
852 //if(reg>=0) return reg;
853 }
854 }
855 }
856 return hr;
857}
858
859
860// Allocate every register, preserving source/target regs
861void alloc_all(struct regstat *cur,int i)
862{
863 int hr;
9f51b4b9 864
57871462 865 for(hr=0;hr<HOST_REGS;hr++) {
866 if(hr!=EXCLUDE_REG) {
cf95b4f0 867 if(((cur->regmap[hr]&63)!=dops[i].rs1)&&((cur->regmap[hr]&63)!=dops[i].rs2)&&
868 ((cur->regmap[hr]&63)!=dops[i].rt1)&&((cur->regmap[hr]&63)!=dops[i].rt2))
57871462 869 {
870 cur->regmap[hr]=-1;
871 cur->dirty&=~(1<<hr);
872 }
873 // Don't need zeros
874 if((cur->regmap[hr]&63)==0)
875 {
876 cur->regmap[hr]=-1;
877 cur->dirty&=~(1<<hr);
878 }
879 }
880 }
881}
882
d1e4ebd9 883#ifndef NDEBUG
884static int host_tempreg_in_use;
885
886static void host_tempreg_acquire(void)
887{
888 assert(!host_tempreg_in_use);
889 host_tempreg_in_use = 1;
890}
891
892static void host_tempreg_release(void)
893{
894 host_tempreg_in_use = 0;
895}
896#else
897static void host_tempreg_acquire(void) {}
898static void host_tempreg_release(void) {}
899#endif
900
32631e6a 901#ifdef ASSEM_PRINT
8062d65a 902extern void gen_interupt();
903extern void do_insn_cmp();
d1e4ebd9 904#define FUNCNAME(f) { f, " " #f }
8062d65a 905static const struct {
d1e4ebd9 906 void *addr;
8062d65a 907 const char *name;
908} function_names[] = {
909 FUNCNAME(cc_interrupt),
910 FUNCNAME(gen_interupt),
911 FUNCNAME(get_addr_ht),
912 FUNCNAME(get_addr),
913 FUNCNAME(jump_handler_read8),
914 FUNCNAME(jump_handler_read16),
915 FUNCNAME(jump_handler_read32),
916 FUNCNAME(jump_handler_write8),
917 FUNCNAME(jump_handler_write16),
918 FUNCNAME(jump_handler_write32),
919 FUNCNAME(invalidate_addr),
3968e69e 920 FUNCNAME(jump_to_new_pc),
81dbbf4c 921 FUNCNAME(call_gteStall),
8062d65a 922 FUNCNAME(new_dyna_leave),
923 FUNCNAME(pcsx_mtc0),
924 FUNCNAME(pcsx_mtc0_ds),
32631e6a 925#ifdef DRC_DBG
8062d65a 926 FUNCNAME(do_insn_cmp),
32631e6a 927#endif
3968e69e 928#ifdef __arm__
929 FUNCNAME(verify_code),
930#endif
8062d65a 931};
932
d1e4ebd9 933static const char *func_name(const void *a)
8062d65a 934{
935 int i;
936 for (i = 0; i < sizeof(function_names)/sizeof(function_names[0]); i++)
937 if (function_names[i].addr == a)
938 return function_names[i].name;
939 return "";
940}
941#else
942#define func_name(x) ""
943#endif
944
57871462 945#ifdef __i386__
946#include "assem_x86.c"
947#endif
948#ifdef __x86_64__
949#include "assem_x64.c"
950#endif
951#ifdef __arm__
952#include "assem_arm.c"
953#endif
be516ebe 954#ifdef __aarch64__
955#include "assem_arm64.c"
956#endif
57871462 957
2a014d73 958static void *get_trampoline(const void *f)
959{
960 size_t i;
961
962 for (i = 0; i < ARRAY_SIZE(ndrc->tramp.f); i++) {
963 if (ndrc->tramp.f[i] == f || ndrc->tramp.f[i] == NULL)
964 break;
965 }
966 if (i == ARRAY_SIZE(ndrc->tramp.f)) {
967 SysPrintf("trampoline table is full, last func %p\n", f);
968 abort();
969 }
970 if (ndrc->tramp.f[i] == NULL) {
971 start_tcache_write(&ndrc->tramp.f[i], &ndrc->tramp.f[i + 1]);
972 ndrc->tramp.f[i] = f;
973 end_tcache_write(&ndrc->tramp.f[i], &ndrc->tramp.f[i + 1]);
974 }
975 return &ndrc->tramp.ops[i];
976}
977
978static void emit_far_jump(const void *f)
979{
980 if (can_jump_or_call(f)) {
981 emit_jmp(f);
982 return;
983 }
984
985 f = get_trampoline(f);
986 emit_jmp(f);
987}
988
989static void emit_far_call(const void *f)
990{
991 if (can_jump_or_call(f)) {
992 emit_call(f);
993 return;
994 }
995
996 f = get_trampoline(f);
997 emit_call(f);
998}
999
57871462 1000// Add virtual address mapping to linked list
1001void ll_add(struct ll_entry **head,int vaddr,void *addr)
1002{
1003 struct ll_entry *new_entry;
1004 new_entry=malloc(sizeof(struct ll_entry));
1005 assert(new_entry!=NULL);
1006 new_entry->vaddr=vaddr;
de5a60c3 1007 new_entry->reg_sv_flags=0;
57871462 1008 new_entry->addr=addr;
1009 new_entry->next=*head;
1010 *head=new_entry;
1011}
1012
de5a60c3 1013void ll_add_flags(struct ll_entry **head,int vaddr,u_int reg_sv_flags,void *addr)
57871462 1014{
7139f3c8 1015 ll_add(head,vaddr,addr);
de5a60c3 1016 (*head)->reg_sv_flags=reg_sv_flags;
57871462 1017}
1018
1019// Check if an address is already compiled
1020// but don't return addresses which are about to expire from the cache
1021void *check_addr(u_int vaddr)
1022{
df4dc2b1 1023 struct ht_entry *ht_bin = hash_table_get(vaddr);
1024 size_t i;
b14b6a8f 1025 for (i = 0; i < ARRAY_SIZE(ht_bin->vaddr); i++) {
df4dc2b1 1026 if (ht_bin->vaddr[i] == vaddr)
1027 if (doesnt_expire_soon((u_char *)ht_bin->tcaddr[i] - MAX_OUTPUT_BLOCK_SIZE))
1028 if (isclean(ht_bin->tcaddr[i]))
1029 return ht_bin->tcaddr[i];
57871462 1030 }
94d23bb9 1031 u_int page=get_page(vaddr);
57871462 1032 struct ll_entry *head;
1033 head=jump_in[page];
df4dc2b1 1034 while (head != NULL) {
1035 if (head->vaddr == vaddr) {
1036 if (doesnt_expire_soon(head->addr)) {
57871462 1037 // Update existing entry with current address
df4dc2b1 1038 if (ht_bin->vaddr[0] == vaddr) {
1039 ht_bin->tcaddr[0] = head->addr;
57871462 1040 return head->addr;
1041 }
df4dc2b1 1042 if (ht_bin->vaddr[1] == vaddr) {
1043 ht_bin->tcaddr[1] = head->addr;
57871462 1044 return head->addr;
1045 }
1046 // Insert into hash table with low priority.
1047 // Don't evict existing entries, as they are probably
1048 // addresses that are being accessed frequently.
df4dc2b1 1049 if (ht_bin->vaddr[0] == -1) {
1050 ht_bin->vaddr[0] = vaddr;
1051 ht_bin->tcaddr[0] = head->addr;
1052 }
1053 else if (ht_bin->vaddr[1] == -1) {
1054 ht_bin->vaddr[1] = vaddr;
1055 ht_bin->tcaddr[1] = head->addr;
57871462 1056 }
1057 return head->addr;
1058 }
1059 }
1060 head=head->next;
1061 }
1062 return 0;
1063}
1064
1065void remove_hash(int vaddr)
1066{
1067 //printf("remove hash: %x\n",vaddr);
df4dc2b1 1068 struct ht_entry *ht_bin = hash_table_get(vaddr);
1069 if (ht_bin->vaddr[1] == vaddr) {
1070 ht_bin->vaddr[1] = -1;
1071 ht_bin->tcaddr[1] = NULL;
57871462 1072 }
df4dc2b1 1073 if (ht_bin->vaddr[0] == vaddr) {
1074 ht_bin->vaddr[0] = ht_bin->vaddr[1];
1075 ht_bin->tcaddr[0] = ht_bin->tcaddr[1];
1076 ht_bin->vaddr[1] = -1;
1077 ht_bin->tcaddr[1] = NULL;
57871462 1078 }
1079}
1080
943f42f3 1081static void ll_remove_matching_addrs(struct ll_entry **head,
1082 uintptr_t base_offs_s, int shift)
57871462 1083{
1084 struct ll_entry *next;
1085 while(*head) {
943f42f3 1086 uintptr_t o1 = (u_char *)(*head)->addr - ndrc->translation_cache;
1087 uintptr_t o2 = o1 - MAX_OUTPUT_BLOCK_SIZE;
1088 if ((o1 >> shift) == base_offs_s || (o2 >> shift) == base_offs_s)
57871462 1089 {
643aeae3 1090 inv_debug("EXP: Remove pointer to %p (%x)\n",(*head)->addr,(*head)->vaddr);
57871462 1091 remove_hash((*head)->vaddr);
1092 next=(*head)->next;
1093 free(*head);
1094 *head=next;
1095 }
1096 else
1097 {
1098 head=&((*head)->next);
1099 }
1100 }
1101}
1102
1103// Remove all entries from linked list
1104void ll_clear(struct ll_entry **head)
1105{
1106 struct ll_entry *cur;
1107 struct ll_entry *next;
581335b0 1108 if((cur=*head)) {
57871462 1109 *head=0;
1110 while(cur) {
1111 next=cur->next;
1112 free(cur);
1113 cur=next;
1114 }
1115 }
1116}
1117
1118// Dereference the pointers and remove if it matches
943f42f3 1119static void ll_kill_pointers(struct ll_entry *head,
1120 uintptr_t base_offs_s, int shift)
57871462 1121{
1122 while(head) {
943f42f3 1123 u_char *ptr = get_pointer(head->addr);
1124 uintptr_t o1 = ptr - ndrc->translation_cache;
1125 uintptr_t o2 = o1 - MAX_OUTPUT_BLOCK_SIZE;
1126 inv_debug("EXP: Lookup pointer to %p at %p (%x)\n",ptr,head->addr,head->vaddr);
1127 if ((o1 >> shift) == base_offs_s || (o2 >> shift) == base_offs_s)
57871462 1128 {
643aeae3 1129 inv_debug("EXP: Kill pointer at %p (%x)\n",head->addr,head->vaddr);
d148d265 1130 void *host_addr=find_extjump_insn(head->addr);
919981d0 1131 mark_clear_cache(host_addr);
df4dc2b1 1132 set_jump_target(host_addr, head->addr);
57871462 1133 }
1134 head=head->next;
1135 }
1136}
1137
1138// This is called when we write to a compiled block (see do_invstub)
d1e4ebd9 1139static void invalidate_page(u_int page)
57871462 1140{
57871462 1141 struct ll_entry *head;
1142 struct ll_entry *next;
1143 head=jump_in[page];
1144 jump_in[page]=0;
1145 while(head!=NULL) {
1146 inv_debug("INVALIDATE: %x\n",head->vaddr);
1147 remove_hash(head->vaddr);
1148 next=head->next;
1149 free(head);
1150 head=next;
1151 }
1152 head=jump_out[page];
1153 jump_out[page]=0;
1154 while(head!=NULL) {
643aeae3 1155 inv_debug("INVALIDATE: kill pointer to %x (%p)\n",head->vaddr,head->addr);
d148d265 1156 void *host_addr=find_extjump_insn(head->addr);
919981d0 1157 mark_clear_cache(host_addr);
3d680478 1158 set_jump_target(host_addr, head->addr); // point back to dyna_linker
57871462 1159 next=head->next;
1160 free(head);
1161 head=next;
1162 }
57871462 1163}
9be4ba64 1164
1165static void invalidate_block_range(u_int block, u_int first, u_int last)
57871462 1166{
94d23bb9 1167 u_int page=get_page(block<<12);
57871462 1168 //printf("first=%d last=%d\n",first,last);
f76eeef9 1169 invalidate_page(page);
57871462 1170 assert(first+5>page); // NB: this assumes MAXBLOCK<=4096 (4 pages)
1171 assert(last<page+5);
1172 // Invalidate the adjacent pages if a block crosses a 4K boundary
1173 while(first<page) {
1174 invalidate_page(first);
1175 first++;
1176 }
1177 for(first=page+1;first<last;first++) {
1178 invalidate_page(first);
1179 }
919981d0 1180 do_clear_cache();
9f51b4b9 1181
57871462 1182 // Don't trap writes
1183 invalid_code[block]=1;
f76eeef9 1184
57871462 1185 #ifdef USE_MINI_HT
1186 memset(mini_ht,-1,sizeof(mini_ht));
1187 #endif
1188}
9be4ba64 1189
1190void invalidate_block(u_int block)
1191{
1192 u_int page=get_page(block<<12);
1193 u_int vpage=get_vpage(block<<12);
1194 inv_debug("INVALIDATE: %x (%d)\n",block<<12,page);
1195 //inv_debug("invalid_code[block]=%d\n",invalid_code[block]);
1196 u_int first,last;
1197 first=last=page;
1198 struct ll_entry *head;
1199 head=jump_dirty[vpage];
1200 //printf("page=%d vpage=%d\n",page,vpage);
1201 while(head!=NULL) {
9be4ba64 1202 if(vpage>2047||(head->vaddr>>12)==block) { // Ignore vaddr hash collision
01d26796 1203 u_char *start, *end;
1204 get_bounds(head->addr, &start, &end);
1205 //printf("start: %p end: %p\n", start, end);
1206 if (page < 2048 && start >= rdram && end < rdram+RAM_SIZE) {
1207 if (((start-rdram)>>12) <= page && ((end-1-rdram)>>12) >= page) {
1208 if ((((start-rdram)>>12)&2047) < first) first = ((start-rdram)>>12)&2047;
1209 if ((((end-1-rdram)>>12)&2047) > last) last = ((end-1-rdram)>>12)&2047;
9be4ba64 1210 }
1211 }
9be4ba64 1212 }
1213 head=head->next;
1214 }
1215 invalidate_block_range(block,first,last);
1216}
1217
57871462 1218void invalidate_addr(u_int addr)
1219{
9be4ba64 1220 //static int rhits;
1221 // this check is done by the caller
1222 //if (inv_code_start<=addr&&addr<=inv_code_end) { rhits++; return; }
d25604ca 1223 u_int page=get_vpage(addr);
9be4ba64 1224 if(page<2048) { // RAM
1225 struct ll_entry *head;
1226 u_int addr_min=~0, addr_max=0;
4a35de07 1227 u_int mask=RAM_SIZE-1;
1228 u_int addr_main=0x80000000|(addr&mask);
9be4ba64 1229 int pg1;
4a35de07 1230 inv_code_start=addr_main&~0xfff;
1231 inv_code_end=addr_main|0xfff;
9be4ba64 1232 pg1=page;
1233 if (pg1>0) {
1234 // must check previous page too because of spans..
1235 pg1--;
1236 inv_code_start-=0x1000;
1237 }
1238 for(;pg1<=page;pg1++) {
1239 for(head=jump_dirty[pg1];head!=NULL;head=head->next) {
01d26796 1240 u_char *start_h, *end_h;
1241 u_int start, end;
1242 get_bounds(head->addr, &start_h, &end_h);
1243 start = (uintptr_t)start_h - ram_offset;
1244 end = (uintptr_t)end_h - ram_offset;
4a35de07 1245 if(start<=addr_main&&addr_main<end) {
9be4ba64 1246 if(start<addr_min) addr_min=start;
1247 if(end>addr_max) addr_max=end;
1248 }
4a35de07 1249 else if(addr_main<start) {
9be4ba64 1250 if(start<inv_code_end)
1251 inv_code_end=start-1;
1252 }
1253 else {
1254 if(end>inv_code_start)
1255 inv_code_start=end;
1256 }
1257 }
1258 }
1259 if (addr_min!=~0) {
1260 inv_debug("INV ADDR: %08x hit %08x-%08x\n", addr, addr_min, addr_max);
1261 inv_code_start=inv_code_end=~0;
1262 invalidate_block_range(addr>>12,(addr_min&mask)>>12,(addr_max&mask)>>12);
1263 return;
1264 }
1265 else {
4a35de07 1266 inv_code_start=(addr&~mask)|(inv_code_start&mask);
1267 inv_code_end=(addr&~mask)|(inv_code_end&mask);
d25604ca 1268 inv_debug("INV ADDR: %08x miss, inv %08x-%08x, sk %d\n", addr, inv_code_start, inv_code_end, 0);
9be4ba64 1269 return;
d25604ca 1270 }
9be4ba64 1271 }
57871462 1272 invalidate_block(addr>>12);
1273}
9be4ba64 1274
dd3a91a1 1275// This is called when loading a save state.
1276// Anything could have changed, so invalidate everything.
919981d0 1277void invalidate_all_pages(void)
57871462 1278{
581335b0 1279 u_int page;
57871462 1280 for(page=0;page<4096;page++)
1281 invalidate_page(page);
1282 for(page=0;page<1048576;page++)
1283 if(!invalid_code[page]) {
1284 restore_candidate[(page&2047)>>3]|=1<<(page&7);
1285 restore_candidate[((page&2047)>>3)+256]|=1<<(page&7);
1286 }
57871462 1287 #ifdef USE_MINI_HT
1288 memset(mini_ht,-1,sizeof(mini_ht));
1289 #endif
919981d0 1290 do_clear_cache();
57871462 1291}
1292
d1e4ebd9 1293static void do_invstub(int n)
1294{
1295 literal_pool(20);
1296 u_int reglist=stubs[n].a;
1297 set_jump_target(stubs[n].addr, out);
1298 save_regs(reglist);
1299 if(stubs[n].b!=0) emit_mov(stubs[n].b,0);
2a014d73 1300 emit_far_call(invalidate_addr);
d1e4ebd9 1301 restore_regs(reglist);
1302 emit_jmp(stubs[n].retaddr); // return address
1303}
1304
57871462 1305// Add an entry to jump_out after making a link
d1e4ebd9 1306// src should point to code by emit_extjump2()
3d680478 1307void add_jump_out(u_int vaddr,void *src)
57871462 1308{
94d23bb9 1309 u_int page=get_page(vaddr);
3d680478 1310 inv_debug("add_jump_out: %p -> %x (%d)\n",src,vaddr,page);
d1e4ebd9 1311 check_extjump2(src);
57871462 1312 ll_add(jump_out+page,vaddr,src);
3d680478 1313 //inv_debug("add_jump_out: to %p\n",get_pointer(src));
57871462 1314}
1315
1316// If a code block was found to be unmodified (bit was set in
1317// restore_candidate) and it remains unmodified (bit is clear
1318// in invalid_code) then move the entries for that 4K page from
1319// the dirty list to the clean list.
1320void clean_blocks(u_int page)
1321{
1322 struct ll_entry *head;
1323 inv_debug("INV: clean_blocks page=%d\n",page);
1324 head=jump_dirty[page];
1325 while(head!=NULL) {
1326 if(!invalid_code[head->vaddr>>12]) {
1327 // Don't restore blocks which are about to expire from the cache
df4dc2b1 1328 if (doesnt_expire_soon(head->addr)) {
581335b0 1329 if(verify_dirty(head->addr)) {
01d26796 1330 u_char *start, *end;
643aeae3 1331 //printf("Possibly Restore %x (%p)\n",head->vaddr, head->addr);
57871462 1332 u_int i;
1333 u_int inv=0;
01d26796 1334 get_bounds(head->addr, &start, &end);
1335 if (start - rdram < RAM_SIZE) {
1336 for (i = (start-rdram+0x80000000)>>12; i <= (end-1-rdram+0x80000000)>>12; i++) {
57871462 1337 inv|=invalid_code[i];
1338 }
1339 }
4cb76aa4 1340 else if((signed int)head->vaddr>=(signed int)0x80000000+RAM_SIZE) {
57871462 1341 inv=1;
1342 }
1343 if(!inv) {
df4dc2b1 1344 void *clean_addr = get_clean_addr(head->addr);
1345 if (doesnt_expire_soon(clean_addr)) {
57871462 1346 u_int ppage=page;
643aeae3 1347 inv_debug("INV: Restored %x (%p/%p)\n",head->vaddr, head->addr, clean_addr);
57871462 1348 //printf("page=%x, addr=%x\n",page,head->vaddr);
1349 //assert(head->vaddr>>12==(page|0x80000));
de5a60c3 1350 ll_add_flags(jump_in+ppage,head->vaddr,head->reg_sv_flags,clean_addr);
df4dc2b1 1351 struct ht_entry *ht_bin = hash_table_get(head->vaddr);
1352 if (ht_bin->vaddr[0] == head->vaddr)
1353 ht_bin->tcaddr[0] = clean_addr; // Replace existing entry
1354 if (ht_bin->vaddr[1] == head->vaddr)
1355 ht_bin->tcaddr[1] = clean_addr; // Replace existing entry
57871462 1356 }
1357 }
1358 }
1359 }
1360 }
1361 head=head->next;
1362 }
1363}
1364
8062d65a 1365/* Register allocation */
1366
1367// Note: registers are allocated clean (unmodified state)
1368// if you intend to modify the register, you must call dirty_reg().
1369static void alloc_reg(struct regstat *cur,int i,signed char reg)
1370{
1371 int r,hr;
b7ec323c 1372 int preferred_reg = PREFERRED_REG_FIRST
1373 + reg % (PREFERRED_REG_LAST - PREFERRED_REG_FIRST + 1);
1374 if (reg == CCREG) preferred_reg = HOST_CCREG;
1375 if (reg == PTEMP || reg == FTEMP) preferred_reg = 12;
1376 assert(PREFERRED_REG_FIRST != EXCLUDE_REG && EXCLUDE_REG != HOST_REGS);
8062d65a 1377
1378 // Don't allocate unused registers
1379 if((cur->u>>reg)&1) return;
1380
1381 // see if it's already allocated
1382 for(hr=0;hr<HOST_REGS;hr++)
1383 {
1384 if(cur->regmap[hr]==reg) return;
1385 }
1386
1387 // Keep the same mapping if the register was already allocated in a loop
1388 preferred_reg = loop_reg(i,reg,preferred_reg);
1389
1390 // Try to allocate the preferred register
1391 if(cur->regmap[preferred_reg]==-1) {
1392 cur->regmap[preferred_reg]=reg;
1393 cur->dirty&=~(1<<preferred_reg);
1394 cur->isconst&=~(1<<preferred_reg);
1395 return;
1396 }
1397 r=cur->regmap[preferred_reg];
1398 assert(r < 64);
1399 if((cur->u>>r)&1) {
1400 cur->regmap[preferred_reg]=reg;
1401 cur->dirty&=~(1<<preferred_reg);
1402 cur->isconst&=~(1<<preferred_reg);
1403 return;
1404 }
1405
1406 // Clear any unneeded registers
1407 // We try to keep the mapping consistent, if possible, because it
1408 // makes branches easier (especially loops). So we try to allocate
1409 // first (see above) before removing old mappings. If this is not
1410 // possible then go ahead and clear out the registers that are no
1411 // longer needed.
1412 for(hr=0;hr<HOST_REGS;hr++)
1413 {
1414 r=cur->regmap[hr];
1415 if(r>=0) {
1416 assert(r < 64);
1417 if((cur->u>>r)&1) {cur->regmap[hr]=-1;break;}
1418 }
1419 }
b7ec323c 1420
8062d65a 1421 // Try to allocate any available register, but prefer
1422 // registers that have not been used recently.
b7ec323c 1423 if (i > 0) {
1424 for (hr = PREFERRED_REG_FIRST; ; ) {
1425 if (cur->regmap[hr] < 0) {
1426 int oldreg = regs[i-1].regmap[hr];
1427 if (oldreg < 0 || (oldreg != dops[i-1].rs1 && oldreg != dops[i-1].rs2
1428 && oldreg != dops[i-1].rt1 && oldreg != dops[i-1].rt2))
1429 {
8062d65a 1430 cur->regmap[hr]=reg;
1431 cur->dirty&=~(1<<hr);
1432 cur->isconst&=~(1<<hr);
1433 return;
1434 }
1435 }
b7ec323c 1436 hr++;
1437 if (hr == EXCLUDE_REG)
1438 hr++;
1439 if (hr == HOST_REGS)
1440 hr = 0;
1441 if (hr == PREFERRED_REG_FIRST)
1442 break;
8062d65a 1443 }
1444 }
b7ec323c 1445
8062d65a 1446 // Try to allocate any available register
b7ec323c 1447 for (hr = PREFERRED_REG_FIRST; ; ) {
1448 if (cur->regmap[hr] < 0) {
8062d65a 1449 cur->regmap[hr]=reg;
1450 cur->dirty&=~(1<<hr);
1451 cur->isconst&=~(1<<hr);
1452 return;
1453 }
b7ec323c 1454 hr++;
1455 if (hr == EXCLUDE_REG)
1456 hr++;
1457 if (hr == HOST_REGS)
1458 hr = 0;
1459 if (hr == PREFERRED_REG_FIRST)
1460 break;
8062d65a 1461 }
1462
1463 // Ok, now we have to evict someone
1464 // Pick a register we hopefully won't need soon
1465 u_char hsn[MAXREG+1];
1466 memset(hsn,10,sizeof(hsn));
1467 int j;
1468 lsn(hsn,i,&preferred_reg);
1469 //printf("eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",cur->regmap[0],cur->regmap[1],cur->regmap[2],cur->regmap[3],cur->regmap[5],cur->regmap[6],cur->regmap[7]);
1470 //printf("hsn(%x): %d %d %d %d %d %d %d\n",start+i*4,hsn[cur->regmap[0]&63],hsn[cur->regmap[1]&63],hsn[cur->regmap[2]&63],hsn[cur->regmap[3]&63],hsn[cur->regmap[5]&63],hsn[cur->regmap[6]&63],hsn[cur->regmap[7]&63]);
1471 if(i>0) {
1472 // Don't evict the cycle count at entry points, otherwise the entry
1473 // stub will have to write it.
cf95b4f0 1474 if(dops[i].bt&&hsn[CCREG]>2) hsn[CCREG]=2;
fe807a8a 1475 if (i>1 && hsn[CCREG] > 2 && dops[i-2].is_jump) hsn[CCREG]=2;
8062d65a 1476 for(j=10;j>=3;j--)
1477 {
1478 // Alloc preferred register if available
1479 if(hsn[r=cur->regmap[preferred_reg]&63]==j) {
1480 for(hr=0;hr<HOST_REGS;hr++) {
1481 // Evict both parts of a 64-bit register
1482 if((cur->regmap[hr]&63)==r) {
1483 cur->regmap[hr]=-1;
1484 cur->dirty&=~(1<<hr);
1485 cur->isconst&=~(1<<hr);
1486 }
1487 }
1488 cur->regmap[preferred_reg]=reg;
1489 return;
1490 }
1491 for(r=1;r<=MAXREG;r++)
1492 {
cf95b4f0 1493 if(hsn[r]==j&&r!=dops[i-1].rs1&&r!=dops[i-1].rs2&&r!=dops[i-1].rt1&&r!=dops[i-1].rt2) {
8062d65a 1494 for(hr=0;hr<HOST_REGS;hr++) {
1495 if(hr!=HOST_CCREG||j<hsn[CCREG]) {
1496 if(cur->regmap[hr]==r) {
1497 cur->regmap[hr]=reg;
1498 cur->dirty&=~(1<<hr);
1499 cur->isconst&=~(1<<hr);
1500 return;
1501 }
1502 }
1503 }
1504 }
1505 }
1506 }
1507 }
1508 for(j=10;j>=0;j--)
1509 {
1510 for(r=1;r<=MAXREG;r++)
1511 {
1512 if(hsn[r]==j) {
8062d65a 1513 for(hr=0;hr<HOST_REGS;hr++) {
1514 if(cur->regmap[hr]==r) {
1515 cur->regmap[hr]=reg;
1516 cur->dirty&=~(1<<hr);
1517 cur->isconst&=~(1<<hr);
1518 return;
1519 }
1520 }
1521 }
1522 }
1523 }
7c3a5182 1524 SysPrintf("This shouldn't happen (alloc_reg)");abort();
8062d65a 1525}
1526
1527// Allocate a temporary register. This is done without regard to
1528// dirty status or whether the register we request is on the unneeded list
1529// Note: This will only allocate one register, even if called multiple times
1530static void alloc_reg_temp(struct regstat *cur,int i,signed char reg)
1531{
1532 int r,hr;
1533 int preferred_reg = -1;
1534
1535 // see if it's already allocated
1536 for(hr=0;hr<HOST_REGS;hr++)
1537 {
1538 if(hr!=EXCLUDE_REG&&cur->regmap[hr]==reg) return;
1539 }
1540
1541 // Try to allocate any available register
1542 for(hr=HOST_REGS-1;hr>=0;hr--) {
1543 if(hr!=EXCLUDE_REG&&cur->regmap[hr]==-1) {
1544 cur->regmap[hr]=reg;
1545 cur->dirty&=~(1<<hr);
1546 cur->isconst&=~(1<<hr);
1547 return;
1548 }
1549 }
1550
1551 // Find an unneeded register
1552 for(hr=HOST_REGS-1;hr>=0;hr--)
1553 {
1554 r=cur->regmap[hr];
1555 if(r>=0) {
1556 assert(r < 64);
1557 if((cur->u>>r)&1) {
1558 if(i==0||((unneeded_reg[i-1]>>r)&1)) {
1559 cur->regmap[hr]=reg;
1560 cur->dirty&=~(1<<hr);
1561 cur->isconst&=~(1<<hr);
1562 return;
1563 }
1564 }
1565 }
1566 }
1567
1568 // Ok, now we have to evict someone
1569 // Pick a register we hopefully won't need soon
1570 // TODO: we might want to follow unconditional jumps here
1571 // TODO: get rid of dupe code and make this into a function
1572 u_char hsn[MAXREG+1];
1573 memset(hsn,10,sizeof(hsn));
1574 int j;
1575 lsn(hsn,i,&preferred_reg);
1576 //printf("hsn: %d %d %d %d %d %d %d\n",hsn[cur->regmap[0]&63],hsn[cur->regmap[1]&63],hsn[cur->regmap[2]&63],hsn[cur->regmap[3]&63],hsn[cur->regmap[5]&63],hsn[cur->regmap[6]&63],hsn[cur->regmap[7]&63]);
1577 if(i>0) {
1578 // Don't evict the cycle count at entry points, otherwise the entry
1579 // stub will have to write it.
cf95b4f0 1580 if(dops[i].bt&&hsn[CCREG]>2) hsn[CCREG]=2;
fe807a8a 1581 if (i>1 && hsn[CCREG] > 2 && dops[i-2].is_jump) hsn[CCREG]=2;
8062d65a 1582 for(j=10;j>=3;j--)
1583 {
1584 for(r=1;r<=MAXREG;r++)
1585 {
cf95b4f0 1586 if(hsn[r]==j&&r!=dops[i-1].rs1&&r!=dops[i-1].rs2&&r!=dops[i-1].rt1&&r!=dops[i-1].rt2) {
8062d65a 1587 for(hr=0;hr<HOST_REGS;hr++) {
1588 if(hr!=HOST_CCREG||hsn[CCREG]>2) {
1589 if(cur->regmap[hr]==r) {
1590 cur->regmap[hr]=reg;
1591 cur->dirty&=~(1<<hr);
1592 cur->isconst&=~(1<<hr);
1593 return;
1594 }
1595 }
1596 }
1597 }
1598 }
1599 }
1600 }
1601 for(j=10;j>=0;j--)
1602 {
1603 for(r=1;r<=MAXREG;r++)
1604 {
1605 if(hsn[r]==j) {
8062d65a 1606 for(hr=0;hr<HOST_REGS;hr++) {
1607 if(cur->regmap[hr]==r) {
1608 cur->regmap[hr]=reg;
1609 cur->dirty&=~(1<<hr);
1610 cur->isconst&=~(1<<hr);
1611 return;
1612 }
1613 }
1614 }
1615 }
1616 }
7c3a5182 1617 SysPrintf("This shouldn't happen");abort();
8062d65a 1618}
1619
ad49de89 1620static void mov_alloc(struct regstat *current,int i)
57871462 1621{
cf95b4f0 1622 if (dops[i].rs1 == HIREG || dops[i].rs1 == LOREG) {
9a3ccfeb 1623 alloc_cc(current,i); // for stalls
1624 dirty_reg(current,CCREG);
32631e6a 1625 }
1626
57871462 1627 // Note: Don't need to actually alloc the source registers
cf95b4f0 1628 //alloc_reg(current,i,dops[i].rs1);
1629 alloc_reg(current,i,dops[i].rt1);
ad49de89 1630
cf95b4f0 1631 clear_const(current,dops[i].rs1);
1632 clear_const(current,dops[i].rt1);
1633 dirty_reg(current,dops[i].rt1);
57871462 1634}
1635
ad49de89 1636static void shiftimm_alloc(struct regstat *current,int i)
57871462 1637{
cf95b4f0 1638 if(dops[i].opcode2<=0x3) // SLL/SRL/SRA
57871462 1639 {
cf95b4f0 1640 if(dops[i].rt1) {
1641 if(dops[i].rs1&&needed_again(dops[i].rs1,i)) alloc_reg(current,i,dops[i].rs1);
1642 else dops[i].lt1=dops[i].rs1;
1643 alloc_reg(current,i,dops[i].rt1);
1644 dirty_reg(current,dops[i].rt1);
1645 if(is_const(current,dops[i].rs1)) {
1646 int v=get_const(current,dops[i].rs1);
1647 if(dops[i].opcode2==0x00) set_const(current,dops[i].rt1,v<<imm[i]);
1648 if(dops[i].opcode2==0x02) set_const(current,dops[i].rt1,(u_int)v>>imm[i]);
1649 if(dops[i].opcode2==0x03) set_const(current,dops[i].rt1,v>>imm[i]);
dc49e339 1650 }
cf95b4f0 1651 else clear_const(current,dops[i].rt1);
57871462 1652 }
1653 }
dc49e339 1654 else
1655 {
cf95b4f0 1656 clear_const(current,dops[i].rs1);
1657 clear_const(current,dops[i].rt1);
dc49e339 1658 }
1659
cf95b4f0 1660 if(dops[i].opcode2>=0x38&&dops[i].opcode2<=0x3b) // DSLL/DSRL/DSRA
57871462 1661 {
9c45ca93 1662 assert(0);
57871462 1663 }
cf95b4f0 1664 if(dops[i].opcode2==0x3c) // DSLL32
57871462 1665 {
9c45ca93 1666 assert(0);
57871462 1667 }
cf95b4f0 1668 if(dops[i].opcode2==0x3e) // DSRL32
57871462 1669 {
9c45ca93 1670 assert(0);
57871462 1671 }
cf95b4f0 1672 if(dops[i].opcode2==0x3f) // DSRA32
57871462 1673 {
9c45ca93 1674 assert(0);
57871462 1675 }
1676}
1677
ad49de89 1678static void shift_alloc(struct regstat *current,int i)
57871462 1679{
cf95b4f0 1680 if(dops[i].rt1) {
1681 if(dops[i].opcode2<=0x07) // SLLV/SRLV/SRAV
57871462 1682 {
cf95b4f0 1683 if(dops[i].rs1) alloc_reg(current,i,dops[i].rs1);
1684 if(dops[i].rs2) alloc_reg(current,i,dops[i].rs2);
1685 alloc_reg(current,i,dops[i].rt1);
1686 if(dops[i].rt1==dops[i].rs2) {
e1190b87 1687 alloc_reg_temp(current,i,-1);
1688 minimum_free_regs[i]=1;
1689 }
57871462 1690 } else { // DSLLV/DSRLV/DSRAV
00fa9369 1691 assert(0);
57871462 1692 }
cf95b4f0 1693 clear_const(current,dops[i].rs1);
1694 clear_const(current,dops[i].rs2);
1695 clear_const(current,dops[i].rt1);
1696 dirty_reg(current,dops[i].rt1);
57871462 1697 }
1698}
1699
ad49de89 1700static void alu_alloc(struct regstat *current,int i)
57871462 1701{
cf95b4f0 1702 if(dops[i].opcode2>=0x20&&dops[i].opcode2<=0x23) { // ADD/ADDU/SUB/SUBU
1703 if(dops[i].rt1) {
1704 if(dops[i].rs1&&dops[i].rs2) {
1705 alloc_reg(current,i,dops[i].rs1);
1706 alloc_reg(current,i,dops[i].rs2);
57871462 1707 }
1708 else {
cf95b4f0 1709 if(dops[i].rs1&&needed_again(dops[i].rs1,i)) alloc_reg(current,i,dops[i].rs1);
1710 if(dops[i].rs2&&needed_again(dops[i].rs2,i)) alloc_reg(current,i,dops[i].rs2);
57871462 1711 }
cf95b4f0 1712 alloc_reg(current,i,dops[i].rt1);
57871462 1713 }
57871462 1714 }
cf95b4f0 1715 if(dops[i].opcode2==0x2a||dops[i].opcode2==0x2b) { // SLT/SLTU
1716 if(dops[i].rt1) {
1717 alloc_reg(current,i,dops[i].rs1);
1718 alloc_reg(current,i,dops[i].rs2);
1719 alloc_reg(current,i,dops[i].rt1);
57871462 1720 }
57871462 1721 }
cf95b4f0 1722 if(dops[i].opcode2>=0x24&&dops[i].opcode2<=0x27) { // AND/OR/XOR/NOR
1723 if(dops[i].rt1) {
1724 if(dops[i].rs1&&dops[i].rs2) {
1725 alloc_reg(current,i,dops[i].rs1);
1726 alloc_reg(current,i,dops[i].rs2);
57871462 1727 }
1728 else
1729 {
cf95b4f0 1730 if(dops[i].rs1&&needed_again(dops[i].rs1,i)) alloc_reg(current,i,dops[i].rs1);
1731 if(dops[i].rs2&&needed_again(dops[i].rs2,i)) alloc_reg(current,i,dops[i].rs2);
57871462 1732 }
cf95b4f0 1733 alloc_reg(current,i,dops[i].rt1);
57871462 1734 }
1735 }
cf95b4f0 1736 if(dops[i].opcode2>=0x2c&&dops[i].opcode2<=0x2f) { // DADD/DADDU/DSUB/DSUBU
00fa9369 1737 assert(0);
57871462 1738 }
cf95b4f0 1739 clear_const(current,dops[i].rs1);
1740 clear_const(current,dops[i].rs2);
1741 clear_const(current,dops[i].rt1);
1742 dirty_reg(current,dops[i].rt1);
57871462 1743}
1744
ad49de89 1745static void imm16_alloc(struct regstat *current,int i)
57871462 1746{
cf95b4f0 1747 if(dops[i].rs1&&needed_again(dops[i].rs1,i)) alloc_reg(current,i,dops[i].rs1);
1748 else dops[i].lt1=dops[i].rs1;
1749 if(dops[i].rt1) alloc_reg(current,i,dops[i].rt1);
1750 if(dops[i].opcode==0x18||dops[i].opcode==0x19) { // DADDI/DADDIU
00fa9369 1751 assert(0);
57871462 1752 }
cf95b4f0 1753 else if(dops[i].opcode==0x0a||dops[i].opcode==0x0b) { // SLTI/SLTIU
1754 clear_const(current,dops[i].rs1);
1755 clear_const(current,dops[i].rt1);
57871462 1756 }
cf95b4f0 1757 else if(dops[i].opcode>=0x0c&&dops[i].opcode<=0x0e) { // ANDI/ORI/XORI
1758 if(is_const(current,dops[i].rs1)) {
1759 int v=get_const(current,dops[i].rs1);
1760 if(dops[i].opcode==0x0c) set_const(current,dops[i].rt1,v&imm[i]);
1761 if(dops[i].opcode==0x0d) set_const(current,dops[i].rt1,v|imm[i]);
1762 if(dops[i].opcode==0x0e) set_const(current,dops[i].rt1,v^imm[i]);
57871462 1763 }
cf95b4f0 1764 else clear_const(current,dops[i].rt1);
57871462 1765 }
cf95b4f0 1766 else if(dops[i].opcode==0x08||dops[i].opcode==0x09) { // ADDI/ADDIU
1767 if(is_const(current,dops[i].rs1)) {
1768 int v=get_const(current,dops[i].rs1);
1769 set_const(current,dops[i].rt1,v+imm[i]);
57871462 1770 }
cf95b4f0 1771 else clear_const(current,dops[i].rt1);
57871462 1772 }
1773 else {
cf95b4f0 1774 set_const(current,dops[i].rt1,imm[i]<<16); // LUI
57871462 1775 }
cf95b4f0 1776 dirty_reg(current,dops[i].rt1);
57871462 1777}
1778
ad49de89 1779static void load_alloc(struct regstat *current,int i)
57871462 1780{
cf95b4f0 1781 clear_const(current,dops[i].rt1);
1782 //if(dops[i].rs1!=dops[i].rt1&&needed_again(dops[i].rs1,i)) clear_const(current,dops[i].rs1); // Does this help or hurt?
1783 if(!dops[i].rs1) current->u&=~1LL; // Allow allocating r0 if it's the source register
37387d8b 1784 if (needed_again(dops[i].rs1, i))
1785 alloc_reg(current, i, dops[i].rs1);
1786 if (ram_offset)
1787 alloc_reg(current, i, ROREG);
cf95b4f0 1788 if(dops[i].rt1&&!((current->u>>dops[i].rt1)&1)) {
1789 alloc_reg(current,i,dops[i].rt1);
1790 assert(get_reg(current->regmap,dops[i].rt1)>=0);
1791 if(dops[i].opcode==0x27||dops[i].opcode==0x37) // LWU/LD
57871462 1792 {
ad49de89 1793 assert(0);
57871462 1794 }
cf95b4f0 1795 else if(dops[i].opcode==0x1A||dops[i].opcode==0x1B) // LDL/LDR
57871462 1796 {
ad49de89 1797 assert(0);
57871462 1798 }
cf95b4f0 1799 dirty_reg(current,dops[i].rt1);
57871462 1800 // LWL/LWR need a temporary register for the old value
cf95b4f0 1801 if(dops[i].opcode==0x22||dops[i].opcode==0x26)
57871462 1802 {
1803 alloc_reg(current,i,FTEMP);
1804 alloc_reg_temp(current,i,-1);
e1190b87 1805 minimum_free_regs[i]=1;
57871462 1806 }
1807 }
1808 else
1809 {
373d1d07 1810 // Load to r0 or unneeded register (dummy load)
57871462 1811 // but we still need a register to calculate the address
cf95b4f0 1812 if(dops[i].opcode==0x22||dops[i].opcode==0x26)
535d208a 1813 {
1814 alloc_reg(current,i,FTEMP); // LWL/LWR need another temporary
1815 }
57871462 1816 alloc_reg_temp(current,i,-1);
e1190b87 1817 minimum_free_regs[i]=1;
cf95b4f0 1818 if(dops[i].opcode==0x1A||dops[i].opcode==0x1B) // LDL/LDR
535d208a 1819 {
ad49de89 1820 assert(0);
535d208a 1821 }
57871462 1822 }
1823}
1824
1825void store_alloc(struct regstat *current,int i)
1826{
cf95b4f0 1827 clear_const(current,dops[i].rs2);
1828 if(!(dops[i].rs2)) current->u&=~1LL; // Allow allocating r0 if necessary
1829 if(needed_again(dops[i].rs1,i)) alloc_reg(current,i,dops[i].rs1);
1830 alloc_reg(current,i,dops[i].rs2);
1831 if(dops[i].opcode==0x2c||dops[i].opcode==0x2d||dops[i].opcode==0x3f) { // 64-bit SDL/SDR/SD
ad49de89 1832 assert(0);
57871462 1833 }
37387d8b 1834 if (ram_offset)
1835 alloc_reg(current, i, ROREG);
57871462 1836 #if defined(HOST_IMM8)
1837 // On CPUs without 32-bit immediates we need a pointer to invalid_code
37387d8b 1838 alloc_reg(current, i, INVCP);
57871462 1839 #endif
cf95b4f0 1840 if(dops[i].opcode==0x2a||dops[i].opcode==0x2e||dops[i].opcode==0x2c||dops[i].opcode==0x2d) { // SWL/SWL/SDL/SDR
57871462 1841 alloc_reg(current,i,FTEMP);
1842 }
1843 // We need a temporary register for address generation
1844 alloc_reg_temp(current,i,-1);
e1190b87 1845 minimum_free_regs[i]=1;
57871462 1846}
1847
1848void c1ls_alloc(struct regstat *current,int i)
1849{
cf95b4f0 1850 clear_const(current,dops[i].rt1);
57871462 1851 alloc_reg(current,i,CSREG); // Status
57871462 1852}
1853
b9b61529 1854void c2ls_alloc(struct regstat *current,int i)
1855{
cf95b4f0 1856 clear_const(current,dops[i].rt1);
1857 if(needed_again(dops[i].rs1,i)) alloc_reg(current,i,dops[i].rs1);
b9b61529 1858 alloc_reg(current,i,FTEMP);
37387d8b 1859 if (ram_offset)
1860 alloc_reg(current, i, ROREG);
b9b61529 1861 #if defined(HOST_IMM8)
1862 // On CPUs without 32-bit immediates we need a pointer to invalid_code
37387d8b 1863 if (dops[i].opcode == 0x3a) // SWC2
b9b61529 1864 alloc_reg(current,i,INVCP);
1865 #endif
1866 // We need a temporary register for address generation
1867 alloc_reg_temp(current,i,-1);
e1190b87 1868 minimum_free_regs[i]=1;
b9b61529 1869}
1870
57871462 1871#ifndef multdiv_alloc
1872void multdiv_alloc(struct regstat *current,int i)
1873{
1874 // case 0x18: MULT
1875 // case 0x19: MULTU
1876 // case 0x1A: DIV
1877 // case 0x1B: DIVU
1878 // case 0x1C: DMULT
1879 // case 0x1D: DMULTU
1880 // case 0x1E: DDIV
1881 // case 0x1F: DDIVU
cf95b4f0 1882 clear_const(current,dops[i].rs1);
1883 clear_const(current,dops[i].rs2);
32631e6a 1884 alloc_cc(current,i); // for stalls
cf95b4f0 1885 if(dops[i].rs1&&dops[i].rs2)
57871462 1886 {
cf95b4f0 1887 if((dops[i].opcode2&4)==0) // 32-bit
57871462 1888 {
1889 current->u&=~(1LL<<HIREG);
1890 current->u&=~(1LL<<LOREG);
1891 alloc_reg(current,i,HIREG);
1892 alloc_reg(current,i,LOREG);
cf95b4f0 1893 alloc_reg(current,i,dops[i].rs1);
1894 alloc_reg(current,i,dops[i].rs2);
57871462 1895 dirty_reg(current,HIREG);
1896 dirty_reg(current,LOREG);
1897 }
1898 else // 64-bit
1899 {
00fa9369 1900 assert(0);
57871462 1901 }
1902 }
1903 else
1904 {
1905 // Multiply by zero is zero.
1906 // MIPS does not have a divide by zero exception.
1907 // The result is undefined, we return zero.
1908 alloc_reg(current,i,HIREG);
1909 alloc_reg(current,i,LOREG);
57871462 1910 dirty_reg(current,HIREG);
1911 dirty_reg(current,LOREG);
1912 }
1913}
1914#endif
1915
1916void cop0_alloc(struct regstat *current,int i)
1917{
cf95b4f0 1918 if(dops[i].opcode2==0) // MFC0
57871462 1919 {
cf95b4f0 1920 if(dops[i].rt1) {
1921 clear_const(current,dops[i].rt1);
57871462 1922 alloc_all(current,i);
cf95b4f0 1923 alloc_reg(current,i,dops[i].rt1);
1924 dirty_reg(current,dops[i].rt1);
57871462 1925 }
1926 }
cf95b4f0 1927 else if(dops[i].opcode2==4) // MTC0
57871462 1928 {
cf95b4f0 1929 if(dops[i].rs1){
1930 clear_const(current,dops[i].rs1);
1931 alloc_reg(current,i,dops[i].rs1);
57871462 1932 alloc_all(current,i);
1933 }
1934 else {
1935 alloc_all(current,i); // FIXME: Keep r0
1936 current->u&=~1LL;
1937 alloc_reg(current,i,0);
1938 }
1939 }
1940 else
1941 {
1942 // TLBR/TLBWI/TLBWR/TLBP/ERET
cf95b4f0 1943 assert(dops[i].opcode2==0x10);
57871462 1944 alloc_all(current,i);
1945 }
e1190b87 1946 minimum_free_regs[i]=HOST_REGS;
57871462 1947}
1948
81dbbf4c 1949static void cop2_alloc(struct regstat *current,int i)
57871462 1950{
cf95b4f0 1951 if (dops[i].opcode2 < 3) // MFC2/CFC2
57871462 1952 {
81dbbf4c 1953 alloc_cc(current,i); // for stalls
1954 dirty_reg(current,CCREG);
cf95b4f0 1955 if(dops[i].rt1){
1956 clear_const(current,dops[i].rt1);
1957 alloc_reg(current,i,dops[i].rt1);
1958 dirty_reg(current,dops[i].rt1);
57871462 1959 }
57871462 1960 }
cf95b4f0 1961 else if (dops[i].opcode2 > 3) // MTC2/CTC2
57871462 1962 {
cf95b4f0 1963 if(dops[i].rs1){
1964 clear_const(current,dops[i].rs1);
1965 alloc_reg(current,i,dops[i].rs1);
57871462 1966 }
1967 else {
1968 current->u&=~1LL;
1969 alloc_reg(current,i,0);
57871462 1970 }
1971 }
81dbbf4c 1972 alloc_reg_temp(current,i,-1);
e1190b87 1973 minimum_free_regs[i]=1;
57871462 1974}
00fa9369 1975
b9b61529 1976void c2op_alloc(struct regstat *current,int i)
1977{
81dbbf4c 1978 alloc_cc(current,i); // for stalls
1979 dirty_reg(current,CCREG);
b9b61529 1980 alloc_reg_temp(current,i,-1);
1981}
57871462 1982
1983void syscall_alloc(struct regstat *current,int i)
1984{
1985 alloc_cc(current,i);
1986 dirty_reg(current,CCREG);
1987 alloc_all(current,i);
e1190b87 1988 minimum_free_regs[i]=HOST_REGS;
57871462 1989 current->isconst=0;
1990}
1991
1992void delayslot_alloc(struct regstat *current,int i)
1993{
cf95b4f0 1994 switch(dops[i].itype) {
57871462 1995 case UJUMP:
1996 case CJUMP:
1997 case SJUMP:
1998 case RJUMP:
57871462 1999 case SYSCALL:
7139f3c8 2000 case HLECALL:
57871462 2001 case SPAN:
7c3a5182 2002 assem_debug("jump in the delay slot. this shouldn't happen.\n");//abort();
c43b5311 2003 SysPrintf("Disabled speculative precompilation\n");
57871462 2004 stop_after_jal=1;
2005 break;
2006 case IMM16:
2007 imm16_alloc(current,i);
2008 break;
2009 case LOAD:
2010 case LOADLR:
2011 load_alloc(current,i);
2012 break;
2013 case STORE:
2014 case STORELR:
2015 store_alloc(current,i);
2016 break;
2017 case ALU:
2018 alu_alloc(current,i);
2019 break;
2020 case SHIFT:
2021 shift_alloc(current,i);
2022 break;
2023 case MULTDIV:
2024 multdiv_alloc(current,i);
2025 break;
2026 case SHIFTIMM:
2027 shiftimm_alloc(current,i);
2028 break;
2029 case MOV:
2030 mov_alloc(current,i);
2031 break;
2032 case COP0:
2033 cop0_alloc(current,i);
2034 break;
2035 case COP1:
81dbbf4c 2036 break;
b9b61529 2037 case COP2:
81dbbf4c 2038 cop2_alloc(current,i);
57871462 2039 break;
2040 case C1LS:
2041 c1ls_alloc(current,i);
2042 break;
b9b61529 2043 case C2LS:
2044 c2ls_alloc(current,i);
2045 break;
b9b61529 2046 case C2OP:
2047 c2op_alloc(current,i);
2048 break;
57871462 2049 }
2050}
2051
2052// Special case where a branch and delay slot span two pages in virtual memory
2053static void pagespan_alloc(struct regstat *current,int i)
2054{
2055 current->isconst=0;
2056 current->wasconst=0;
2057 regs[i].wasconst=0;
e1190b87 2058 minimum_free_regs[i]=HOST_REGS;
57871462 2059 alloc_all(current,i);
2060 alloc_cc(current,i);
2061 dirty_reg(current,CCREG);
cf95b4f0 2062 if(dops[i].opcode==3) // JAL
57871462 2063 {
2064 alloc_reg(current,i,31);
2065 dirty_reg(current,31);
2066 }
cf95b4f0 2067 if(dops[i].opcode==0&&(dops[i].opcode2&0x3E)==8) // JR/JALR
57871462 2068 {
cf95b4f0 2069 alloc_reg(current,i,dops[i].rs1);
2070 if (dops[i].rt1!=0) {
2071 alloc_reg(current,i,dops[i].rt1);
2072 dirty_reg(current,dops[i].rt1);
57871462 2073 }
2074 }
cf95b4f0 2075 if((dops[i].opcode&0x2E)==4) // BEQ/BNE/BEQL/BNEL
57871462 2076 {
cf95b4f0 2077 if(dops[i].rs1) alloc_reg(current,i,dops[i].rs1);
2078 if(dops[i].rs2) alloc_reg(current,i,dops[i].rs2);
57871462 2079 }
2080 else
cf95b4f0 2081 if((dops[i].opcode&0x2E)==6) // BLEZ/BGTZ/BLEZL/BGTZL
57871462 2082 {
cf95b4f0 2083 if(dops[i].rs1) alloc_reg(current,i,dops[i].rs1);
57871462 2084 }
57871462 2085 //else ...
2086}
2087
b14b6a8f 2088static void add_stub(enum stub_type type, void *addr, void *retaddr,
2089 u_int a, uintptr_t b, uintptr_t c, u_int d, u_int e)
2090{
d1e4ebd9 2091 assert(stubcount < ARRAY_SIZE(stubs));
b14b6a8f 2092 stubs[stubcount].type = type;
2093 stubs[stubcount].addr = addr;
2094 stubs[stubcount].retaddr = retaddr;
2095 stubs[stubcount].a = a;
2096 stubs[stubcount].b = b;
2097 stubs[stubcount].c = c;
2098 stubs[stubcount].d = d;
2099 stubs[stubcount].e = e;
57871462 2100 stubcount++;
2101}
2102
b14b6a8f 2103static void add_stub_r(enum stub_type type, void *addr, void *retaddr,
81dbbf4c 2104 int i, int addr_reg, const struct regstat *i_regs, int ccadj, u_int reglist)
b14b6a8f 2105{
2106 add_stub(type, addr, retaddr, i, addr_reg, (uintptr_t)i_regs, ccadj, reglist);
2107}
2108
57871462 2109// Write out a single register
2330734f 2110static void wb_register(signed char r, const signed char regmap[], uint64_t dirty)
57871462 2111{
2112 int hr;
2113 for(hr=0;hr<HOST_REGS;hr++) {
2114 if(hr!=EXCLUDE_REG) {
2115 if((regmap[hr]&63)==r) {
2116 if((dirty>>hr)&1) {
ad49de89 2117 assert(regmap[hr]<64);
2118 emit_storereg(r,hr);
57871462 2119 }
2120 }
2121 }
2122 }
2123}
2124
8062d65a 2125static void wb_valid(signed char pre[],signed char entry[],u_int dirty_pre,u_int dirty,uint64_t u)
2126{
2127 //if(dirty_pre==dirty) return;
2128 int hr,reg;
2129 for(hr=0;hr<HOST_REGS;hr++) {
2130 if(hr!=EXCLUDE_REG) {
2131 reg=pre[hr];
2132 if(((~u)>>(reg&63))&1) {
2133 if(reg>0) {
2134 if(((dirty_pre&~dirty)>>hr)&1) {
2135 if(reg>0&&reg<34) {
2136 emit_storereg(reg,hr);
2137 }
2138 else if(reg>=64) {
2139 assert(0);
2140 }
2141 }
2142 }
2143 }
2144 }
2145 }
2146}
2147
687b4580 2148// trashes r2
2149static void pass_args(int a0, int a1)
2150{
2151 if(a0==1&&a1==0) {
2152 // must swap
2153 emit_mov(a0,2); emit_mov(a1,1); emit_mov(2,0);
2154 }
2155 else if(a0!=0&&a1==0) {
2156 emit_mov(a1,1);
2157 if (a0>=0) emit_mov(a0,0);
2158 }
2159 else {
2160 if(a0>=0&&a0!=0) emit_mov(a0,0);
2161 if(a1>=0&&a1!=1) emit_mov(a1,1);
2162 }
2163}
2164
2330734f 2165static void alu_assemble(int i, const struct regstat *i_regs)
57871462 2166{
cf95b4f0 2167 if(dops[i].opcode2>=0x20&&dops[i].opcode2<=0x23) { // ADD/ADDU/SUB/SUBU
2168 if(dops[i].rt1) {
57871462 2169 signed char s1,s2,t;
cf95b4f0 2170 t=get_reg(i_regs->regmap,dops[i].rt1);
57871462 2171 if(t>=0) {
cf95b4f0 2172 s1=get_reg(i_regs->regmap,dops[i].rs1);
2173 s2=get_reg(i_regs->regmap,dops[i].rs2);
2174 if(dops[i].rs1&&dops[i].rs2) {
57871462 2175 assert(s1>=0);
2176 assert(s2>=0);
cf95b4f0 2177 if(dops[i].opcode2&2) emit_sub(s1,s2,t);
57871462 2178 else emit_add(s1,s2,t);
2179 }
cf95b4f0 2180 else if(dops[i].rs1) {
57871462 2181 if(s1>=0) emit_mov(s1,t);
cf95b4f0 2182 else emit_loadreg(dops[i].rs1,t);
57871462 2183 }
cf95b4f0 2184 else if(dops[i].rs2) {
57871462 2185 if(s2>=0) {
cf95b4f0 2186 if(dops[i].opcode2&2) emit_neg(s2,t);
57871462 2187 else emit_mov(s2,t);
2188 }
2189 else {
cf95b4f0 2190 emit_loadreg(dops[i].rs2,t);
2191 if(dops[i].opcode2&2) emit_neg(t,t);
57871462 2192 }
2193 }
2194 else emit_zeroreg(t);
2195 }
2196 }
2197 }
cf95b4f0 2198 if(dops[i].opcode2>=0x2c&&dops[i].opcode2<=0x2f) { // DADD/DADDU/DSUB/DSUBU
00fa9369 2199 assert(0);
57871462 2200 }
cf95b4f0 2201 if(dops[i].opcode2==0x2a||dops[i].opcode2==0x2b) { // SLT/SLTU
2202 if(dops[i].rt1) {
ad49de89 2203 signed char s1l,s2l,t;
57871462 2204 {
cf95b4f0 2205 t=get_reg(i_regs->regmap,dops[i].rt1);
57871462 2206 //assert(t>=0);
2207 if(t>=0) {
cf95b4f0 2208 s1l=get_reg(i_regs->regmap,dops[i].rs1);
2209 s2l=get_reg(i_regs->regmap,dops[i].rs2);
2210 if(dops[i].rs2==0) // rx<r0
57871462 2211 {
cf95b4f0 2212 if(dops[i].opcode2==0x2a&&dops[i].rs1!=0) { // SLT
06e425d7 2213 assert(s1l>=0);
57871462 2214 emit_shrimm(s1l,31,t);
06e425d7 2215 }
2216 else // SLTU (unsigned can not be less than zero, 0<0)
57871462 2217 emit_zeroreg(t);
2218 }
cf95b4f0 2219 else if(dops[i].rs1==0) // r0<rx
57871462 2220 {
2221 assert(s2l>=0);
cf95b4f0 2222 if(dops[i].opcode2==0x2a) // SLT
57871462 2223 emit_set_gz32(s2l,t);
2224 else // SLTU (set if not zero)
2225 emit_set_nz32(s2l,t);
2226 }
2227 else{
2228 assert(s1l>=0);assert(s2l>=0);
cf95b4f0 2229 if(dops[i].opcode2==0x2a) // SLT
57871462 2230 emit_set_if_less32(s1l,s2l,t);
2231 else // SLTU
2232 emit_set_if_carry32(s1l,s2l,t);
2233 }
2234 }
2235 }
2236 }
2237 }
cf95b4f0 2238 if(dops[i].opcode2>=0x24&&dops[i].opcode2<=0x27) { // AND/OR/XOR/NOR
2239 if(dops[i].rt1) {
ad49de89 2240 signed char s1l,s2l,tl;
cf95b4f0 2241 tl=get_reg(i_regs->regmap,dops[i].rt1);
57871462 2242 {
57871462 2243 if(tl>=0) {
cf95b4f0 2244 s1l=get_reg(i_regs->regmap,dops[i].rs1);
2245 s2l=get_reg(i_regs->regmap,dops[i].rs2);
2246 if(dops[i].rs1&&dops[i].rs2) {
57871462 2247 assert(s1l>=0);
2248 assert(s2l>=0);
cf95b4f0 2249 if(dops[i].opcode2==0x24) { // AND
57871462 2250 emit_and(s1l,s2l,tl);
2251 } else
cf95b4f0 2252 if(dops[i].opcode2==0x25) { // OR
57871462 2253 emit_or(s1l,s2l,tl);
2254 } else
cf95b4f0 2255 if(dops[i].opcode2==0x26) { // XOR
57871462 2256 emit_xor(s1l,s2l,tl);
2257 } else
cf95b4f0 2258 if(dops[i].opcode2==0x27) { // NOR
57871462 2259 emit_or(s1l,s2l,tl);
2260 emit_not(tl,tl);
2261 }
2262 }
2263 else
2264 {
cf95b4f0 2265 if(dops[i].opcode2==0x24) { // AND
57871462 2266 emit_zeroreg(tl);
2267 } else
cf95b4f0 2268 if(dops[i].opcode2==0x25||dops[i].opcode2==0x26) { // OR/XOR
2269 if(dops[i].rs1){
57871462 2270 if(s1l>=0) emit_mov(s1l,tl);
cf95b4f0 2271 else emit_loadreg(dops[i].rs1,tl); // CHECK: regmap_entry?
57871462 2272 }
2273 else
cf95b4f0 2274 if(dops[i].rs2){
57871462 2275 if(s2l>=0) emit_mov(s2l,tl);
cf95b4f0 2276 else emit_loadreg(dops[i].rs2,tl); // CHECK: regmap_entry?
57871462 2277 }
2278 else emit_zeroreg(tl);
2279 } else
cf95b4f0 2280 if(dops[i].opcode2==0x27) { // NOR
2281 if(dops[i].rs1){
57871462 2282 if(s1l>=0) emit_not(s1l,tl);
2283 else {
cf95b4f0 2284 emit_loadreg(dops[i].rs1,tl);
57871462 2285 emit_not(tl,tl);
2286 }
2287 }
2288 else
cf95b4f0 2289 if(dops[i].rs2){
57871462 2290 if(s2l>=0) emit_not(s2l,tl);
2291 else {
cf95b4f0 2292 emit_loadreg(dops[i].rs2,tl);
57871462 2293 emit_not(tl,tl);
2294 }
2295 }
2296 else emit_movimm(-1,tl);
2297 }
2298 }
2299 }
2300 }
2301 }
2302 }
2303}
2304
2330734f 2305static void imm16_assemble(int i, const struct regstat *i_regs)
57871462 2306{
cf95b4f0 2307 if (dops[i].opcode==0x0f) { // LUI
2308 if(dops[i].rt1) {
57871462 2309 signed char t;
cf95b4f0 2310 t=get_reg(i_regs->regmap,dops[i].rt1);
57871462 2311 //assert(t>=0);
2312 if(t>=0) {
2313 if(!((i_regs->isconst>>t)&1))
2314 emit_movimm(imm[i]<<16,t);
2315 }
2316 }
2317 }
cf95b4f0 2318 if(dops[i].opcode==0x08||dops[i].opcode==0x09) { // ADDI/ADDIU
2319 if(dops[i].rt1) {
57871462 2320 signed char s,t;
cf95b4f0 2321 t=get_reg(i_regs->regmap,dops[i].rt1);
2322 s=get_reg(i_regs->regmap,dops[i].rs1);
2323 if(dops[i].rs1) {
57871462 2324 //assert(t>=0);
2325 //assert(s>=0);
2326 if(t>=0) {
2327 if(!((i_regs->isconst>>t)&1)) {
2328 if(s<0) {
cf95b4f0 2329 if(i_regs->regmap_entry[t]!=dops[i].rs1) emit_loadreg(dops[i].rs1,t);
57871462 2330 emit_addimm(t,imm[i],t);
2331 }else{
2332 if(!((i_regs->wasconst>>s)&1))
2333 emit_addimm(s,imm[i],t);
2334 else
2335 emit_movimm(constmap[i][s]+imm[i],t);
2336 }
2337 }
2338 }
2339 } else {
2340 if(t>=0) {
2341 if(!((i_regs->isconst>>t)&1))
2342 emit_movimm(imm[i],t);
2343 }
2344 }
2345 }
2346 }
cf95b4f0 2347 if(dops[i].opcode==0x18||dops[i].opcode==0x19) { // DADDI/DADDIU
2348 if(dops[i].rt1) {
7c3a5182 2349 signed char sl,tl;
cf95b4f0 2350 tl=get_reg(i_regs->regmap,dops[i].rt1);
2351 sl=get_reg(i_regs->regmap,dops[i].rs1);
57871462 2352 if(tl>=0) {
cf95b4f0 2353 if(dops[i].rs1) {
57871462 2354 assert(sl>=0);
7c3a5182 2355 emit_addimm(sl,imm[i],tl);
57871462 2356 } else {
2357 emit_movimm(imm[i],tl);
57871462 2358 }
2359 }
2360 }
2361 }
cf95b4f0 2362 else if(dops[i].opcode==0x0a||dops[i].opcode==0x0b) { // SLTI/SLTIU
2363 if(dops[i].rt1) {
2364 //assert(dops[i].rs1!=0); // r0 might be valid, but it's probably a bug
ad49de89 2365 signed char sl,t;
cf95b4f0 2366 t=get_reg(i_regs->regmap,dops[i].rt1);
2367 sl=get_reg(i_regs->regmap,dops[i].rs1);
57871462 2368 //assert(t>=0);
2369 if(t>=0) {
cf95b4f0 2370 if(dops[i].rs1>0) {
2371 if(dops[i].opcode==0x0a) { // SLTI
57871462 2372 if(sl<0) {
cf95b4f0 2373 if(i_regs->regmap_entry[t]!=dops[i].rs1) emit_loadreg(dops[i].rs1,t);
57871462 2374 emit_slti32(t,imm[i],t);
2375 }else{
2376 emit_slti32(sl,imm[i],t);
2377 }
2378 }
2379 else { // SLTIU
2380 if(sl<0) {
cf95b4f0 2381 if(i_regs->regmap_entry[t]!=dops[i].rs1) emit_loadreg(dops[i].rs1,t);
57871462 2382 emit_sltiu32(t,imm[i],t);
2383 }else{
2384 emit_sltiu32(sl,imm[i],t);
2385 }
2386 }
57871462 2387 }else{
2388 // SLTI(U) with r0 is just stupid,
2389 // nonetheless examples can be found
cf95b4f0 2390 if(dops[i].opcode==0x0a) // SLTI
57871462 2391 if(0<imm[i]) emit_movimm(1,t);
2392 else emit_zeroreg(t);
2393 else // SLTIU
2394 {
2395 if(imm[i]) emit_movimm(1,t);
2396 else emit_zeroreg(t);
2397 }
2398 }
2399 }
2400 }
2401 }
cf95b4f0 2402 else if(dops[i].opcode>=0x0c&&dops[i].opcode<=0x0e) { // ANDI/ORI/XORI
2403 if(dops[i].rt1) {
7c3a5182 2404 signed char sl,tl;
cf95b4f0 2405 tl=get_reg(i_regs->regmap,dops[i].rt1);
2406 sl=get_reg(i_regs->regmap,dops[i].rs1);
57871462 2407 if(tl>=0 && !((i_regs->isconst>>tl)&1)) {
cf95b4f0 2408 if(dops[i].opcode==0x0c) //ANDI
57871462 2409 {
cf95b4f0 2410 if(dops[i].rs1) {
57871462 2411 if(sl<0) {
cf95b4f0 2412 if(i_regs->regmap_entry[tl]!=dops[i].rs1) emit_loadreg(dops[i].rs1,tl);
57871462 2413 emit_andimm(tl,imm[i],tl);
2414 }else{
2415 if(!((i_regs->wasconst>>sl)&1))
2416 emit_andimm(sl,imm[i],tl);
2417 else
2418 emit_movimm(constmap[i][sl]&imm[i],tl);
2419 }
2420 }
2421 else
2422 emit_zeroreg(tl);
57871462 2423 }
2424 else
2425 {
cf95b4f0 2426 if(dops[i].rs1) {
57871462 2427 if(sl<0) {
cf95b4f0 2428 if(i_regs->regmap_entry[tl]!=dops[i].rs1) emit_loadreg(dops[i].rs1,tl);
57871462 2429 }
cf95b4f0 2430 if(dops[i].opcode==0x0d) { // ORI
581335b0 2431 if(sl<0) {
2432 emit_orimm(tl,imm[i],tl);
2433 }else{
2434 if(!((i_regs->wasconst>>sl)&1))
2435 emit_orimm(sl,imm[i],tl);
2436 else
2437 emit_movimm(constmap[i][sl]|imm[i],tl);
2438 }
57871462 2439 }
cf95b4f0 2440 if(dops[i].opcode==0x0e) { // XORI
581335b0 2441 if(sl<0) {
2442 emit_xorimm(tl,imm[i],tl);
2443 }else{
2444 if(!((i_regs->wasconst>>sl)&1))
2445 emit_xorimm(sl,imm[i],tl);
2446 else
2447 emit_movimm(constmap[i][sl]^imm[i],tl);
2448 }
57871462 2449 }
2450 }
2451 else {
2452 emit_movimm(imm[i],tl);
57871462 2453 }
2454 }
2455 }
2456 }
2457 }
2458}
2459
2330734f 2460static void shiftimm_assemble(int i, const struct regstat *i_regs)
57871462 2461{
cf95b4f0 2462 if(dops[i].opcode2<=0x3) // SLL/SRL/SRA
57871462 2463 {
cf95b4f0 2464 if(dops[i].rt1) {
57871462 2465 signed char s,t;
cf95b4f0 2466 t=get_reg(i_regs->regmap,dops[i].rt1);
2467 s=get_reg(i_regs->regmap,dops[i].rs1);
57871462 2468 //assert(t>=0);
dc49e339 2469 if(t>=0&&!((i_regs->isconst>>t)&1)){
cf95b4f0 2470 if(dops[i].rs1==0)
57871462 2471 {
2472 emit_zeroreg(t);
2473 }
2474 else
2475 {
cf95b4f0 2476 if(s<0&&i_regs->regmap_entry[t]!=dops[i].rs1) emit_loadreg(dops[i].rs1,t);
57871462 2477 if(imm[i]) {
cf95b4f0 2478 if(dops[i].opcode2==0) // SLL
57871462 2479 {
2480 emit_shlimm(s<0?t:s,imm[i],t);
2481 }
cf95b4f0 2482 if(dops[i].opcode2==2) // SRL
57871462 2483 {
2484 emit_shrimm(s<0?t:s,imm[i],t);
2485 }
cf95b4f0 2486 if(dops[i].opcode2==3) // SRA
57871462 2487 {
2488 emit_sarimm(s<0?t:s,imm[i],t);
2489 }
2490 }else{
2491 // Shift by zero
2492 if(s>=0 && s!=t) emit_mov(s,t);
2493 }
2494 }
2495 }
cf95b4f0 2496 //emit_storereg(dops[i].rt1,t); //DEBUG
57871462 2497 }
2498 }
cf95b4f0 2499 if(dops[i].opcode2>=0x38&&dops[i].opcode2<=0x3b) // DSLL/DSRL/DSRA
57871462 2500 {
9c45ca93 2501 assert(0);
57871462 2502 }
cf95b4f0 2503 if(dops[i].opcode2==0x3c) // DSLL32
57871462 2504 {
9c45ca93 2505 assert(0);
57871462 2506 }
cf95b4f0 2507 if(dops[i].opcode2==0x3e) // DSRL32
57871462 2508 {
9c45ca93 2509 assert(0);
57871462 2510 }
cf95b4f0 2511 if(dops[i].opcode2==0x3f) // DSRA32
57871462 2512 {
9c45ca93 2513 assert(0);
57871462 2514 }
2515}
2516
2517#ifndef shift_assemble
2330734f 2518static void shift_assemble(int i, const struct regstat *i_regs)
57871462 2519{
3968e69e 2520 signed char s,t,shift;
cf95b4f0 2521 if (dops[i].rt1 == 0)
3968e69e 2522 return;
cf95b4f0 2523 assert(dops[i].opcode2<=0x07); // SLLV/SRLV/SRAV
2524 t = get_reg(i_regs->regmap, dops[i].rt1);
2525 s = get_reg(i_regs->regmap, dops[i].rs1);
2526 shift = get_reg(i_regs->regmap, dops[i].rs2);
3968e69e 2527 if (t < 0)
2528 return;
2529
cf95b4f0 2530 if(dops[i].rs1==0)
3968e69e 2531 emit_zeroreg(t);
cf95b4f0 2532 else if(dops[i].rs2==0) {
3968e69e 2533 assert(s>=0);
2534 if(s!=t) emit_mov(s,t);
2535 }
2536 else {
2537 host_tempreg_acquire();
2538 emit_andimm(shift,31,HOST_TEMPREG);
cf95b4f0 2539 switch(dops[i].opcode2) {
3968e69e 2540 case 4: // SLLV
2541 emit_shl(s,HOST_TEMPREG,t);
2542 break;
2543 case 6: // SRLV
2544 emit_shr(s,HOST_TEMPREG,t);
2545 break;
2546 case 7: // SRAV
2547 emit_sar(s,HOST_TEMPREG,t);
2548 break;
2549 default:
2550 assert(0);
2551 }
2552 host_tempreg_release();
2553 }
57871462 2554}
3968e69e 2555
57871462 2556#endif
2557
8062d65a 2558enum {
2559 MTYPE_8000 = 0,
2560 MTYPE_8020,
2561 MTYPE_0000,
2562 MTYPE_A000,
2563 MTYPE_1F80,
2564};
2565
2566static int get_ptr_mem_type(u_int a)
2567{
2568 if(a < 0x00200000) {
2569 if(a<0x1000&&((start>>20)==0xbfc||(start>>24)==0xa0))
2570 // return wrong, must use memhandler for BIOS self-test to pass
2571 // 007 does similar stuff from a00 mirror, weird stuff
2572 return MTYPE_8000;
2573 return MTYPE_0000;
2574 }
2575 if(0x1f800000 <= a && a < 0x1f801000)
2576 return MTYPE_1F80;
2577 if(0x80200000 <= a && a < 0x80800000)
2578 return MTYPE_8020;
2579 if(0xa0000000 <= a && a < 0xa0200000)
2580 return MTYPE_A000;
2581 return MTYPE_8000;
2582}
2583
37387d8b 2584static int get_ro_reg(const struct regstat *i_regs, int host_tempreg_free)
2585{
2586 int r = get_reg(i_regs->regmap, ROREG);
2587 if (r < 0 && host_tempreg_free) {
2588 host_tempreg_acquire();
2589 emit_loadreg(ROREG, r = HOST_TEMPREG);
2590 }
2591 if (r < 0)
2592 abort();
2593 return r;
2594}
2595
2596static void *emit_fastpath_cmp_jump(int i, const struct regstat *i_regs,
2597 int addr, int *offset_reg, int *addr_reg_override)
8062d65a 2598{
2599 void *jaddr = NULL;
37387d8b 2600 int type = 0;
2601 int mr = dops[i].rs1;
2602 *offset_reg = -1;
8062d65a 2603 if(((smrv_strong|smrv_weak)>>mr)&1) {
2604 type=get_ptr_mem_type(smrv[mr]);
2605 //printf("set %08x @%08x r%d %d\n", smrv[mr], start+i*4, mr, type);
2606 }
2607 else {
2608 // use the mirror we are running on
2609 type=get_ptr_mem_type(start);
2610 //printf("set nospec @%08x r%d %d\n", start+i*4, mr, type);
2611 }
2612
2613 if(type==MTYPE_8020) { // RAM 80200000+ mirror
d1e4ebd9 2614 host_tempreg_acquire();
8062d65a 2615 emit_andimm(addr,~0x00e00000,HOST_TEMPREG);
2616 addr=*addr_reg_override=HOST_TEMPREG;
2617 type=0;
2618 }
2619 else if(type==MTYPE_0000) { // RAM 0 mirror
d1e4ebd9 2620 host_tempreg_acquire();
8062d65a 2621 emit_orimm(addr,0x80000000,HOST_TEMPREG);
2622 addr=*addr_reg_override=HOST_TEMPREG;
2623 type=0;
2624 }
2625 else if(type==MTYPE_A000) { // RAM A mirror
d1e4ebd9 2626 host_tempreg_acquire();
8062d65a 2627 emit_andimm(addr,~0x20000000,HOST_TEMPREG);
2628 addr=*addr_reg_override=HOST_TEMPREG;
2629 type=0;
2630 }
2631 else if(type==MTYPE_1F80) { // scratchpad
2632 if (psxH == (void *)0x1f800000) {
d1e4ebd9 2633 host_tempreg_acquire();
3968e69e 2634 emit_xorimm(addr,0x1f800000,HOST_TEMPREG);
8062d65a 2635 emit_cmpimm(HOST_TEMPREG,0x1000);
d1e4ebd9 2636 host_tempreg_release();
8062d65a 2637 jaddr=out;
2638 emit_jc(0);
2639 }
2640 else {
2641 // do the usual RAM check, jump will go to the right handler
2642 type=0;
2643 }
2644 }
2645
37387d8b 2646 if (type == 0) // need ram check
8062d65a 2647 {
2648 emit_cmpimm(addr,RAM_SIZE);
37387d8b 2649 jaddr = out;
8062d65a 2650 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
2651 // Hint to branch predictor that the branch is unlikely to be taken
37387d8b 2652 if (dops[i].rs1 >= 28)
8062d65a 2653 emit_jno_unlikely(0);
2654 else
2655 #endif
2656 emit_jno(0);
37387d8b 2657 if (ram_offset != 0)
2658 *offset_reg = get_ro_reg(i_regs, 0);
8062d65a 2659 }
2660
2661 return jaddr;
2662}
2663
687b4580 2664// return memhandler, or get directly accessable address and return 0
2665static void *get_direct_memhandler(void *table, u_int addr,
2666 enum stub_type type, uintptr_t *addr_host)
2667{
c979e8c2 2668 uintptr_t msb = 1ull << (sizeof(uintptr_t)*8 - 1);
687b4580 2669 uintptr_t l1, l2 = 0;
2670 l1 = ((uintptr_t *)table)[addr>>12];
c979e8c2 2671 if (!(l1 & msb)) {
687b4580 2672 uintptr_t v = l1 << 1;
2673 *addr_host = v + addr;
2674 return NULL;
2675 }
2676 else {
2677 l1 <<= 1;
2678 if (type == LOADB_STUB || type == LOADBU_STUB || type == STOREB_STUB)
2679 l2 = ((uintptr_t *)l1)[0x1000/4 + 0x1000/2 + (addr&0xfff)];
2680 else if (type == LOADH_STUB || type == LOADHU_STUB || type == STOREH_STUB)
c979e8c2 2681 l2 = ((uintptr_t *)l1)[0x1000/4 + (addr&0xfff)/2];
687b4580 2682 else
c979e8c2 2683 l2 = ((uintptr_t *)l1)[(addr&0xfff)/4];
2684 if (!(l2 & msb)) {
687b4580 2685 uintptr_t v = l2 << 1;
2686 *addr_host = v + (addr&0xfff);
2687 return NULL;
2688 }
2689 return (void *)(l2 << 1);
2690 }
2691}
2692
81dbbf4c 2693static u_int get_host_reglist(const signed char *regmap)
2694{
2695 u_int reglist = 0, hr;
2696 for (hr = 0; hr < HOST_REGS; hr++) {
2697 if (hr != EXCLUDE_REG && regmap[hr] >= 0)
2698 reglist |= 1 << hr;
2699 }
2700 return reglist;
2701}
2702
2703static u_int reglist_exclude(u_int reglist, int r1, int r2)
2704{
2705 if (r1 >= 0)
2706 reglist &= ~(1u << r1);
2707 if (r2 >= 0)
2708 reglist &= ~(1u << r2);
2709 return reglist;
2710}
2711
e3c6bdb5 2712// find a temp caller-saved register not in reglist (so assumed to be free)
2713static int reglist_find_free(u_int reglist)
2714{
2715 u_int free_regs = ~reglist & CALLER_SAVE_REGS;
2716 if (free_regs == 0)
2717 return -1;
2718 return __builtin_ctz(free_regs);
2719}
2720
37387d8b 2721static void do_load_word(int a, int rt, int offset_reg)
2722{
2723 if (offset_reg >= 0)
2724 emit_ldr_dualindexed(offset_reg, a, rt);
2725 else
2726 emit_readword_indexed(0, a, rt);
2727}
2728
2729static void do_store_word(int a, int ofs, int rt, int offset_reg, int preseve_a)
2730{
2731 if (offset_reg < 0) {
2732 emit_writeword_indexed(rt, ofs, a);
2733 return;
2734 }
2735 if (ofs != 0)
2736 emit_addimm(a, ofs, a);
2737 emit_str_dualindexed(offset_reg, a, rt);
2738 if (ofs != 0 && preseve_a)
2739 emit_addimm(a, -ofs, a);
2740}
2741
2742static void do_store_hword(int a, int ofs, int rt, int offset_reg, int preseve_a)
2743{
2744 if (offset_reg < 0) {
2745 emit_writehword_indexed(rt, ofs, a);
2746 return;
2747 }
2748 if (ofs != 0)
2749 emit_addimm(a, ofs, a);
2750 emit_strh_dualindexed(offset_reg, a, rt);
2751 if (ofs != 0 && preseve_a)
2752 emit_addimm(a, -ofs, a);
2753}
2754
2755static void do_store_byte(int a, int rt, int offset_reg)
2756{
2757 if (offset_reg >= 0)
2758 emit_strb_dualindexed(offset_reg, a, rt);
2759 else
2760 emit_writebyte_indexed(rt, 0, a);
2761}
2762
2330734f 2763static void load_assemble(int i, const struct regstat *i_regs, int ccadj_)
57871462 2764{
7c3a5182 2765 int s,tl,addr;
57871462 2766 int offset;
b14b6a8f 2767 void *jaddr=0;
5bf843dc 2768 int memtarget=0,c=0;
37387d8b 2769 int offset_reg = -1;
2770 int fastio_reg_override = -1;
81dbbf4c 2771 u_int reglist=get_host_reglist(i_regs->regmap);
cf95b4f0 2772 tl=get_reg(i_regs->regmap,dops[i].rt1);
2773 s=get_reg(i_regs->regmap,dops[i].rs1);
57871462 2774 offset=imm[i];
57871462 2775 if(i_regs->regmap[HOST_CCREG]==CCREG) reglist&=~(1<<HOST_CCREG);
2776 if(s>=0) {
2777 c=(i_regs->wasconst>>s)&1;
af4ee1fe 2778 if (c) {
2779 memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
af4ee1fe 2780 }
57871462 2781 }
57871462 2782 //printf("load_assemble: c=%d\n",c);
643aeae3 2783 //if(c) printf("load_assemble: const=%lx\n",(long)constmap[i][s]+offset);
57871462 2784 // FIXME: Even if the load is a NOP, we should check for pagefaults...
581335b0 2785 if((tl<0&&(!c||(((u_int)constmap[i][s]+offset)>>16)==0x1f80))
cf95b4f0 2786 ||dops[i].rt1==0) {
5bf843dc 2787 // could be FIFO, must perform the read
f18c0f46 2788 // ||dummy read
5bf843dc 2789 assem_debug("(forced read)\n");
2790 tl=get_reg(i_regs->regmap,-1);
2791 assert(tl>=0);
5bf843dc 2792 }
2793 if(offset||s<0||c) addr=tl;
2794 else addr=s;
535d208a 2795 //if(tl<0) tl=get_reg(i_regs->regmap,-1);
2796 if(tl>=0) {
2797 //printf("load_assemble: c=%d\n",c);
643aeae3 2798 //if(c) printf("load_assemble: const=%lx\n",(long)constmap[i][s]+offset);
535d208a 2799 assert(tl>=0); // Even if the load is a NOP, we must check for pagefaults and I/O
2800 reglist&=~(1<<tl);
1edfcc68 2801 if(!c) {
1edfcc68 2802 #ifdef R29_HACK
2803 // Strmnnrmn's speed hack
cf95b4f0 2804 if(dops[i].rs1!=29||start<0x80001000||start>=0x80000000+RAM_SIZE)
1edfcc68 2805 #endif
2806 {
37387d8b 2807 jaddr = emit_fastpath_cmp_jump(i, i_regs, addr,
2808 &offset_reg, &fastio_reg_override);
535d208a 2809 }
1edfcc68 2810 }
37387d8b 2811 else if (ram_offset && memtarget) {
2812 offset_reg = get_ro_reg(i_regs, 0);
535d208a 2813 }
cf95b4f0 2814 int dummy=(dops[i].rt1==0)||(tl!=get_reg(i_regs->regmap,dops[i].rt1)); // ignore loads to r0 and unneeded reg
37387d8b 2815 switch (dops[i].opcode) {
2816 case 0x20: // LB
535d208a 2817 if(!c||memtarget) {
2818 if(!dummy) {
37387d8b 2819 int a = tl;
2820 if (!c) a = addr;
2821 if (fastio_reg_override >= 0)
2822 a = fastio_reg_override;
b1570849 2823
37387d8b 2824 if (offset_reg >= 0)
2825 emit_ldrsb_dualindexed(offset_reg, a, tl);
2826 else
2827 emit_movsbl_indexed(0, a, tl);
57871462 2828 }
535d208a 2829 if(jaddr)
2330734f 2830 add_stub_r(LOADB_STUB,jaddr,out,i,addr,i_regs,ccadj_,reglist);
57871462 2831 }
535d208a 2832 else
2330734f 2833 inline_readstub(LOADB_STUB,i,constmap[i][s]+offset,i_regs->regmap,dops[i].rt1,ccadj_,reglist);
37387d8b 2834 break;
2835 case 0x21: // LH
535d208a 2836 if(!c||memtarget) {
2837 if(!dummy) {
37387d8b 2838 int a = tl;
2839 if (!c) a = addr;
2840 if (fastio_reg_override >= 0)
2841 a = fastio_reg_override;
2842 if (offset_reg >= 0)
2843 emit_ldrsh_dualindexed(offset_reg, a, tl);
2844 else
2845 emit_movswl_indexed(0, a, tl);
57871462 2846 }
535d208a 2847 if(jaddr)
2330734f 2848 add_stub_r(LOADH_STUB,jaddr,out,i,addr,i_regs,ccadj_,reglist);
57871462 2849 }
535d208a 2850 else
2330734f 2851 inline_readstub(LOADH_STUB,i,constmap[i][s]+offset,i_regs->regmap,dops[i].rt1,ccadj_,reglist);
37387d8b 2852 break;
2853 case 0x23: // LW
535d208a 2854 if(!c||memtarget) {
2855 if(!dummy) {
37387d8b 2856 int a = addr;
2857 if (fastio_reg_override >= 0)
2858 a = fastio_reg_override;
2859 do_load_word(a, tl, offset_reg);
57871462 2860 }
535d208a 2861 if(jaddr)
2330734f 2862 add_stub_r(LOADW_STUB,jaddr,out,i,addr,i_regs,ccadj_,reglist);
57871462 2863 }
535d208a 2864 else
2330734f 2865 inline_readstub(LOADW_STUB,i,constmap[i][s]+offset,i_regs->regmap,dops[i].rt1,ccadj_,reglist);
37387d8b 2866 break;
2867 case 0x24: // LBU
535d208a 2868 if(!c||memtarget) {
2869 if(!dummy) {
37387d8b 2870 int a = tl;
2871 if (!c) a = addr;
2872 if (fastio_reg_override >= 0)
2873 a = fastio_reg_override;
b1570849 2874
37387d8b 2875 if (offset_reg >= 0)
2876 emit_ldrb_dualindexed(offset_reg, a, tl);
2877 else
2878 emit_movzbl_indexed(0, a, tl);
57871462 2879 }
535d208a 2880 if(jaddr)
2330734f 2881 add_stub_r(LOADBU_STUB,jaddr,out,i,addr,i_regs,ccadj_,reglist);
57871462 2882 }
535d208a 2883 else
2330734f 2884 inline_readstub(LOADBU_STUB,i,constmap[i][s]+offset,i_regs->regmap,dops[i].rt1,ccadj_,reglist);
37387d8b 2885 break;
2886 case 0x25: // LHU
535d208a 2887 if(!c||memtarget) {
2888 if(!dummy) {
37387d8b 2889 int a = tl;
2890 if(!c) a = addr;
2891 if (fastio_reg_override >= 0)
2892 a = fastio_reg_override;
2893 if (offset_reg >= 0)
2894 emit_ldrh_dualindexed(offset_reg, a, tl);
2895 else
2896 emit_movzwl_indexed(0, a, tl);
57871462 2897 }
535d208a 2898 if(jaddr)
2330734f 2899 add_stub_r(LOADHU_STUB,jaddr,out,i,addr,i_regs,ccadj_,reglist);
57871462 2900 }
535d208a 2901 else
2330734f 2902 inline_readstub(LOADHU_STUB,i,constmap[i][s]+offset,i_regs->regmap,dops[i].rt1,ccadj_,reglist);
37387d8b 2903 break;
2904 case 0x27: // LWU
2905 case 0x37: // LD
2906 default:
9c45ca93 2907 assert(0);
57871462 2908 }
535d208a 2909 }
37387d8b 2910 if (fastio_reg_override == HOST_TEMPREG || offset_reg == HOST_TEMPREG)
d1e4ebd9 2911 host_tempreg_release();
57871462 2912}
2913
2914#ifndef loadlr_assemble
2330734f 2915static void loadlr_assemble(int i, const struct regstat *i_regs, int ccadj_)
57871462 2916{
3968e69e 2917 int s,tl,temp,temp2,addr;
2918 int offset;
2919 void *jaddr=0;
2920 int memtarget=0,c=0;
37387d8b 2921 int offset_reg = -1;
2922 int fastio_reg_override = -1;
81dbbf4c 2923 u_int reglist=get_host_reglist(i_regs->regmap);
cf95b4f0 2924 tl=get_reg(i_regs->regmap,dops[i].rt1);
2925 s=get_reg(i_regs->regmap,dops[i].rs1);
3968e69e 2926 temp=get_reg(i_regs->regmap,-1);
2927 temp2=get_reg(i_regs->regmap,FTEMP);
2928 addr=get_reg(i_regs->regmap,AGEN1+(i&1));
2929 assert(addr<0);
2930 offset=imm[i];
3968e69e 2931 reglist|=1<<temp;
2932 if(offset||s<0||c) addr=temp2;
2933 else addr=s;
2934 if(s>=0) {
2935 c=(i_regs->wasconst>>s)&1;
2936 if(c) {
2937 memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
2938 }
2939 }
2940 if(!c) {
2941 emit_shlimm(addr,3,temp);
cf95b4f0 2942 if (dops[i].opcode==0x22||dops[i].opcode==0x26) {
3968e69e 2943 emit_andimm(addr,0xFFFFFFFC,temp2); // LWL/LWR
2944 }else{
2945 emit_andimm(addr,0xFFFFFFF8,temp2); // LDL/LDR
2946 }
37387d8b 2947 jaddr = emit_fastpath_cmp_jump(i, i_regs, temp2,
2948 &offset_reg, &fastio_reg_override);
3968e69e 2949 }
2950 else {
37387d8b 2951 if (ram_offset && memtarget) {
2952 offset_reg = get_ro_reg(i_regs, 0);
3968e69e 2953 }
cf95b4f0 2954 if (dops[i].opcode==0x22||dops[i].opcode==0x26) {
3968e69e 2955 emit_movimm(((constmap[i][s]+offset)<<3)&24,temp); // LWL/LWR
2956 }else{
2957 emit_movimm(((constmap[i][s]+offset)<<3)&56,temp); // LDL/LDR
2958 }
2959 }
cf95b4f0 2960 if (dops[i].opcode==0x22||dops[i].opcode==0x26) { // LWL/LWR
3968e69e 2961 if(!c||memtarget) {
37387d8b 2962 int a = temp2;
2963 if (fastio_reg_override >= 0)
2964 a = fastio_reg_override;
2965 do_load_word(a, temp2, offset_reg);
2966 if (fastio_reg_override == HOST_TEMPREG || offset_reg == HOST_TEMPREG)
2967 host_tempreg_release();
2330734f 2968 if(jaddr) add_stub_r(LOADW_STUB,jaddr,out,i,temp2,i_regs,ccadj_,reglist);
3968e69e 2969 }
2970 else
2330734f 2971 inline_readstub(LOADW_STUB,i,(constmap[i][s]+offset)&0xFFFFFFFC,i_regs->regmap,FTEMP,ccadj_,reglist);
cf95b4f0 2972 if(dops[i].rt1) {
3968e69e 2973 assert(tl>=0);
2974 emit_andimm(temp,24,temp);
cf95b4f0 2975 if (dops[i].opcode==0x22) // LWL
3968e69e 2976 emit_xorimm(temp,24,temp);
2977 host_tempreg_acquire();
2978 emit_movimm(-1,HOST_TEMPREG);
cf95b4f0 2979 if (dops[i].opcode==0x26) {
3968e69e 2980 emit_shr(temp2,temp,temp2);
2981 emit_bic_lsr(tl,HOST_TEMPREG,temp,tl);
2982 }else{
2983 emit_shl(temp2,temp,temp2);
2984 emit_bic_lsl(tl,HOST_TEMPREG,temp,tl);
2985 }
2986 host_tempreg_release();
2987 emit_or(temp2,tl,tl);
2988 }
cf95b4f0 2989 //emit_storereg(dops[i].rt1,tl); // DEBUG
3968e69e 2990 }
cf95b4f0 2991 if (dops[i].opcode==0x1A||dops[i].opcode==0x1B) { // LDL/LDR
3968e69e 2992 assert(0);
2993 }
57871462 2994}
2995#endif
2996
2330734f 2997static void store_assemble(int i, const struct regstat *i_regs, int ccadj_)
57871462 2998{
9c45ca93 2999 int s,tl;
57871462 3000 int addr,temp;
3001 int offset;
b14b6a8f 3002 void *jaddr=0;
37387d8b 3003 enum stub_type type=0;
666a299d 3004 int memtarget=0,c=0;
57871462 3005 int agr=AGEN1+(i&1);
37387d8b 3006 int offset_reg = -1;
3007 int fastio_reg_override = -1;
81dbbf4c 3008 u_int reglist=get_host_reglist(i_regs->regmap);
cf95b4f0 3009 tl=get_reg(i_regs->regmap,dops[i].rs2);
3010 s=get_reg(i_regs->regmap,dops[i].rs1);
57871462 3011 temp=get_reg(i_regs->regmap,agr);
3012 if(temp<0) temp=get_reg(i_regs->regmap,-1);
3013 offset=imm[i];
3014 if(s>=0) {
3015 c=(i_regs->wasconst>>s)&1;
af4ee1fe 3016 if(c) {
3017 memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
af4ee1fe 3018 }
57871462 3019 }
3020 assert(tl>=0);
3021 assert(temp>=0);
57871462 3022 if(i_regs->regmap[HOST_CCREG]==CCREG) reglist&=~(1<<HOST_CCREG);
3023 if(offset||s<0||c) addr=temp;
3024 else addr=s;
37387d8b 3025 if (!c) {
3026 jaddr = emit_fastpath_cmp_jump(i, i_regs, addr,
3027 &offset_reg, &fastio_reg_override);
1edfcc68 3028 }
37387d8b 3029 else if (ram_offset && memtarget) {
3030 offset_reg = get_ro_reg(i_regs, 0);
57871462 3031 }
3032
37387d8b 3033 switch (dops[i].opcode) {
3034 case 0x28: // SB
57871462 3035 if(!c||memtarget) {
37387d8b 3036 int a = temp;
3037 if (!c) a = addr;
3038 if (fastio_reg_override >= 0)
3039 a = fastio_reg_override;
3040 do_store_byte(a, tl, offset_reg);
3041 }
3042 type = STOREB_STUB;
3043 break;
3044 case 0x29: // SH
57871462 3045 if(!c||memtarget) {
37387d8b 3046 int a = temp;
3047 if (!c) a = addr;
3048 if (fastio_reg_override >= 0)
3049 a = fastio_reg_override;
3050 do_store_hword(a, 0, tl, offset_reg, 1);
3051 }
3052 type = STOREH_STUB;
3053 break;
3054 case 0x2B: // SW
dadf55f2 3055 if(!c||memtarget) {
37387d8b 3056 int a = addr;
3057 if (fastio_reg_override >= 0)
3058 a = fastio_reg_override;
3059 do_store_word(a, 0, tl, offset_reg, 1);
3060 }
3061 type = STOREW_STUB;
3062 break;
3063 case 0x3F: // SD
3064 default:
9c45ca93 3065 assert(0);
57871462 3066 }
37387d8b 3067 if (fastio_reg_override == HOST_TEMPREG || offset_reg == HOST_TEMPREG)
d1e4ebd9 3068 host_tempreg_release();
b96d3df7 3069 if(jaddr) {
3070 // PCSX store handlers don't check invcode again
3071 reglist|=1<<addr;
2330734f 3072 add_stub_r(type,jaddr,out,i,addr,i_regs,ccadj_,reglist);
b96d3df7 3073 jaddr=0;
3074 }
cf95b4f0 3075 if(!(i_regs->waswritten&(1<<dops[i].rs1)) && !HACK_ENABLED(NDHACK_NO_SMC_CHECK)) {
57871462 3076 if(!c||memtarget) {
3077 #ifdef DESTRUCTIVE_SHIFT
3078 // The x86 shift operation is 'destructive'; it overwrites the
3079 // source register, so we need to make a copy first and use that.
3080 addr=temp;
3081 #endif
3082 #if defined(HOST_IMM8)
3083 int ir=get_reg(i_regs->regmap,INVCP);
3084 assert(ir>=0);
3085 emit_cmpmem_indexedsr12_reg(ir,addr,1);
3086 #else
643aeae3 3087 emit_cmpmem_indexedsr12_imm(invalid_code,addr,1);
57871462 3088 #endif
0bbd1454 3089 #if defined(HAVE_CONDITIONAL_CALL) && !defined(DESTRUCTIVE_SHIFT)
3090 emit_callne(invalidate_addr_reg[addr]);
3091 #else
b14b6a8f 3092 void *jaddr2 = out;
57871462 3093 emit_jne(0);
b14b6a8f 3094 add_stub(INVCODE_STUB,jaddr2,out,reglist|(1<<HOST_CCREG),addr,0,0,0);
0bbd1454 3095 #endif
57871462 3096 }
3097 }
7a518516 3098 u_int addr_val=constmap[i][s]+offset;
3eaa7048 3099 if(jaddr) {
2330734f 3100 add_stub_r(type,jaddr,out,i,addr,i_regs,ccadj_,reglist);
3eaa7048 3101 } else if(c&&!memtarget) {
2330734f 3102 inline_writestub(type,i,addr_val,i_regs->regmap,dops[i].rs2,ccadj_,reglist);
7a518516 3103 }
3104 // basic current block modification detection..
3105 // not looking back as that should be in mips cache already
3968e69e 3106 // (see Spyro2 title->attract mode)
7a518516 3107 if(c&&start+i*4<addr_val&&addr_val<start+slen*4) {
c43b5311 3108 SysPrintf("write to %08x hits block %08x, pc=%08x\n",addr_val,start,start+i*4);
7a518516 3109 assert(i_regs->regmap==regs[i].regmap); // not delay slot
3110 if(i_regs->regmap==regs[i].regmap) {
ad49de89 3111 load_all_consts(regs[i].regmap_entry,regs[i].wasdirty,i);
3112 wb_dirtys(regs[i].regmap_entry,regs[i].wasdirty);
7a518516 3113 emit_movimm(start+i*4+4,0);
643aeae3 3114 emit_writeword(0,&pcaddr);
d1e4ebd9 3115 emit_addimm(HOST_CCREG,2,HOST_CCREG);
2a014d73 3116 emit_far_call(get_addr_ht);
d1e4ebd9 3117 emit_jmpreg(0);
7a518516 3118 }
3eaa7048 3119 }
57871462 3120}
3121
2330734f 3122static void storelr_assemble(int i, const struct regstat *i_regs, int ccadj_)
57871462 3123{
9c45ca93 3124 int s,tl;
57871462 3125 int temp;
57871462 3126 int offset;
b14b6a8f 3127 void *jaddr=0;
37387d8b 3128 void *case1, *case23, *case3;
df4dc2b1 3129 void *done0, *done1, *done2;
af4ee1fe 3130 int memtarget=0,c=0;
fab5d06d 3131 int agr=AGEN1+(i&1);
37387d8b 3132 int offset_reg = -1;
81dbbf4c 3133 u_int reglist=get_host_reglist(i_regs->regmap);
cf95b4f0 3134 tl=get_reg(i_regs->regmap,dops[i].rs2);
3135 s=get_reg(i_regs->regmap,dops[i].rs1);
fab5d06d 3136 temp=get_reg(i_regs->regmap,agr);
3137 if(temp<0) temp=get_reg(i_regs->regmap,-1);
57871462 3138 offset=imm[i];
3139 if(s>=0) {
3140 c=(i_regs->isconst>>s)&1;
af4ee1fe 3141 if(c) {
3142 memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
af4ee1fe 3143 }
57871462 3144 }
3145 assert(tl>=0);
535d208a 3146 assert(temp>=0);
1edfcc68 3147 if(!c) {
3148 emit_cmpimm(s<0||offset?temp:s,RAM_SIZE);
3149 if(!offset&&s!=temp) emit_mov(s,temp);
b14b6a8f 3150 jaddr=out;
1edfcc68 3151 emit_jno(0);
3152 }
3153 else
3154 {
cf95b4f0 3155 if(!memtarget||!dops[i].rs1) {
b14b6a8f 3156 jaddr=out;
535d208a 3157 emit_jmp(0);
57871462 3158 }
535d208a 3159 }
37387d8b 3160 if (ram_offset)
3161 offset_reg = get_ro_reg(i_regs, 0);
535d208a 3162
cf95b4f0 3163 if (dops[i].opcode==0x2C||dops[i].opcode==0x2D) { // SDL/SDR
9c45ca93 3164 assert(0);
535d208a 3165 }
57871462 3166
535d208a 3167 emit_testimm(temp,2);
37387d8b 3168 case23=out;
535d208a 3169 emit_jne(0);
3170 emit_testimm(temp,1);
df4dc2b1 3171 case1=out;
535d208a 3172 emit_jne(0);
3173 // 0
37387d8b 3174 if (dops[i].opcode == 0x2A) { // SWL
3175 // Write msb into least significant byte
3176 if (dops[i].rs2) emit_rorimm(tl, 24, tl);
3177 do_store_byte(temp, tl, offset_reg);
3178 if (dops[i].rs2) emit_rorimm(tl, 8, tl);
535d208a 3179 }
37387d8b 3180 else if (dops[i].opcode == 0x2E) { // SWR
3181 // Write entire word
3182 do_store_word(temp, 0, tl, offset_reg, 1);
535d208a 3183 }
37387d8b 3184 done0 = out;
535d208a 3185 emit_jmp(0);
3186 // 1
df4dc2b1 3187 set_jump_target(case1, out);
37387d8b 3188 if (dops[i].opcode == 0x2A) { // SWL
3189 // Write two msb into two least significant bytes
3190 if (dops[i].rs2) emit_rorimm(tl, 16, tl);
3191 do_store_hword(temp, -1, tl, offset_reg, 0);
3192 if (dops[i].rs2) emit_rorimm(tl, 16, tl);
535d208a 3193 }
37387d8b 3194 else if (dops[i].opcode == 0x2E) { // SWR
3195 // Write 3 lsb into three most significant bytes
3196 do_store_byte(temp, tl, offset_reg);
3197 if (dops[i].rs2) emit_rorimm(tl, 8, tl);
3198 do_store_hword(temp, 1, tl, offset_reg, 0);
3199 if (dops[i].rs2) emit_rorimm(tl, 24, tl);
535d208a 3200 }
df4dc2b1 3201 done1=out;
535d208a 3202 emit_jmp(0);
37387d8b 3203 // 2,3
3204 set_jump_target(case23, out);
535d208a 3205 emit_testimm(temp,1);
37387d8b 3206 case3 = out;
535d208a 3207 emit_jne(0);
37387d8b 3208 // 2
cf95b4f0 3209 if (dops[i].opcode==0x2A) { // SWL
37387d8b 3210 // Write 3 msb into three least significant bytes
3211 if (dops[i].rs2) emit_rorimm(tl, 8, tl);
3212 do_store_hword(temp, -2, tl, offset_reg, 1);
3213 if (dops[i].rs2) emit_rorimm(tl, 16, tl);
3214 do_store_byte(temp, tl, offset_reg);
3215 if (dops[i].rs2) emit_rorimm(tl, 8, tl);
535d208a 3216 }
37387d8b 3217 else if (dops[i].opcode == 0x2E) { // SWR
3218 // Write two lsb into two most significant bytes
3219 do_store_hword(temp, 0, tl, offset_reg, 1);
535d208a 3220 }
37387d8b 3221 done2 = out;
535d208a 3222 emit_jmp(0);
3223 // 3
df4dc2b1 3224 set_jump_target(case3, out);
37387d8b 3225 if (dops[i].opcode == 0x2A) { // SWL
3226 do_store_word(temp, -3, tl, offset_reg, 0);
535d208a 3227 }
37387d8b 3228 else if (dops[i].opcode == 0x2E) { // SWR
3229 do_store_byte(temp, tl, offset_reg);
535d208a 3230 }
df4dc2b1 3231 set_jump_target(done0, out);
3232 set_jump_target(done1, out);
3233 set_jump_target(done2, out);
37387d8b 3234 if (offset_reg == HOST_TEMPREG)
3235 host_tempreg_release();
535d208a 3236 if(!c||!memtarget)
2330734f 3237 add_stub_r(STORELR_STUB,jaddr,out,i,temp,i_regs,ccadj_,reglist);
cf95b4f0 3238 if(!(i_regs->waswritten&(1<<dops[i].rs1)) && !HACK_ENABLED(NDHACK_NO_SMC_CHECK)) {
57871462 3239 #if defined(HOST_IMM8)
3240 int ir=get_reg(i_regs->regmap,INVCP);
3241 assert(ir>=0);
3242 emit_cmpmem_indexedsr12_reg(ir,temp,1);
3243 #else
643aeae3 3244 emit_cmpmem_indexedsr12_imm(invalid_code,temp,1);
57871462 3245 #endif
535d208a 3246 #if defined(HAVE_CONDITIONAL_CALL) && !defined(DESTRUCTIVE_SHIFT)
3247 emit_callne(invalidate_addr_reg[temp]);
3248 #else
b14b6a8f 3249 void *jaddr2 = out;
57871462 3250 emit_jne(0);
b14b6a8f 3251 add_stub(INVCODE_STUB,jaddr2,out,reglist|(1<<HOST_CCREG),temp,0,0,0);
535d208a 3252 #endif
57871462 3253 }
57871462 3254}
3255
2330734f 3256static void cop0_assemble(int i, const struct regstat *i_regs, int ccadj_)
8062d65a 3257{
cf95b4f0 3258 if(dops[i].opcode2==0) // MFC0
8062d65a 3259 {
cf95b4f0 3260 signed char t=get_reg(i_regs->regmap,dops[i].rt1);
8062d65a 3261 u_int copr=(source[i]>>11)&0x1f;
3262 //assert(t>=0); // Why does this happen? OOT is weird
cf95b4f0 3263 if(t>=0&&dops[i].rt1!=0) {
8062d65a 3264 emit_readword(&reg_cop0[copr],t);
3265 }
3266 }
cf95b4f0 3267 else if(dops[i].opcode2==4) // MTC0
8062d65a 3268 {
cf95b4f0 3269 signed char s=get_reg(i_regs->regmap,dops[i].rs1);
8062d65a 3270 char copr=(source[i]>>11)&0x1f;
3271 assert(s>=0);
cf95b4f0 3272 wb_register(dops[i].rs1,i_regs->regmap,i_regs->dirty);
8062d65a 3273 if(copr==9||copr==11||copr==12||copr==13) {
3274 emit_readword(&last_count,HOST_TEMPREG);
3275 emit_loadreg(CCREG,HOST_CCREG); // TODO: do proper reg alloc
3276 emit_add(HOST_CCREG,HOST_TEMPREG,HOST_CCREG);
2330734f 3277 emit_addimm(HOST_CCREG,ccadj_,HOST_CCREG);
8062d65a 3278 emit_writeword(HOST_CCREG,&Count);
3279 }
3280 // What a mess. The status register (12) can enable interrupts,
3281 // so needs a special case to handle a pending interrupt.
3282 // The interrupt must be taken immediately, because a subsequent
3283 // instruction might disable interrupts again.
3284 if(copr==12||copr==13) {
3285 if (is_delayslot) {
3286 // burn cycles to cause cc_interrupt, which will
3287 // reschedule next_interupt. Relies on CCREG from above.
3288 assem_debug("MTC0 DS %d\n", copr);
3289 emit_writeword(HOST_CCREG,&last_count);
3290 emit_movimm(0,HOST_CCREG);
3291 emit_storereg(CCREG,HOST_CCREG);
cf95b4f0 3292 emit_loadreg(dops[i].rs1,1);
8062d65a 3293 emit_movimm(copr,0);
2a014d73 3294 emit_far_call(pcsx_mtc0_ds);
cf95b4f0 3295 emit_loadreg(dops[i].rs1,s);
8062d65a 3296 return;
3297 }
3298 emit_movimm(start+i*4+4,HOST_TEMPREG);
3299 emit_writeword(HOST_TEMPREG,&pcaddr);
3300 emit_movimm(0,HOST_TEMPREG);
3301 emit_writeword(HOST_TEMPREG,&pending_exception);
3302 }
8062d65a 3303 if(s==HOST_CCREG)
cf95b4f0 3304 emit_loadreg(dops[i].rs1,1);
8062d65a 3305 else if(s!=1)
3306 emit_mov(s,1);
3307 emit_movimm(copr,0);
2a014d73 3308 emit_far_call(pcsx_mtc0);
8062d65a 3309 if(copr==9||copr==11||copr==12||copr==13) {
3310 emit_readword(&Count,HOST_CCREG);
3311 emit_readword(&next_interupt,HOST_TEMPREG);
2330734f 3312 emit_addimm(HOST_CCREG,-ccadj_,HOST_CCREG);
8062d65a 3313 emit_sub(HOST_CCREG,HOST_TEMPREG,HOST_CCREG);
3314 emit_writeword(HOST_TEMPREG,&last_count);
3315 emit_storereg(CCREG,HOST_CCREG);
3316 }
3317 if(copr==12||copr==13) {
3318 assert(!is_delayslot);
3319 emit_readword(&pending_exception,14);
3320 emit_test(14,14);
d1e4ebd9 3321 void *jaddr = out;
3322 emit_jeq(0);
3323 emit_readword(&pcaddr, 0);
3324 emit_addimm(HOST_CCREG,2,HOST_CCREG);
2a014d73 3325 emit_far_call(get_addr_ht);
d1e4ebd9 3326 emit_jmpreg(0);
3327 set_jump_target(jaddr, out);
8062d65a 3328 }
cf95b4f0 3329 emit_loadreg(dops[i].rs1,s);
8062d65a 3330 }
3331 else
3332 {
cf95b4f0 3333 assert(dops[i].opcode2==0x10);
8062d65a 3334 //if((source[i]&0x3f)==0x10) // RFE
3335 {
3336 emit_readword(&Status,0);
3337 emit_andimm(0,0x3c,1);
3338 emit_andimm(0,~0xf,0);
3339 emit_orrshr_imm(1,2,0);
3340 emit_writeword(0,&Status);
3341 }
3342 }
3343}
3344
2330734f 3345static void cop1_unusable(int i, const struct regstat *i_regs)
8062d65a 3346{
3347 // XXX: should just just do the exception instead
3348 //if(!cop1_usable)
3349 {
3350 void *jaddr=out;
3351 emit_jmp(0);
3352 add_stub_r(FP_STUB,jaddr,out,i,0,i_regs,is_delayslot,0);
3353 }
3354}
3355
2330734f 3356static void cop1_assemble(int i, const struct regstat *i_regs)
8062d65a 3357{
3358 cop1_unusable(i, i_regs);
3359}
3360
2330734f 3361static void c1ls_assemble(int i, const struct regstat *i_regs)
57871462 3362{
3d624f89 3363 cop1_unusable(i, i_regs);
57871462 3364}
3365
8062d65a 3366// FP_STUB
3367static void do_cop1stub(int n)
3368{
3369 literal_pool(256);
3370 assem_debug("do_cop1stub %x\n",start+stubs[n].a*4);
3371 set_jump_target(stubs[n].addr, out);
3372 int i=stubs[n].a;
3373// int rs=stubs[n].b;
3374 struct regstat *i_regs=(struct regstat *)stubs[n].c;
3375 int ds=stubs[n].d;
3376 if(!ds) {
3377 load_all_consts(regs[i].regmap_entry,regs[i].wasdirty,i);
3378 //if(i_regs!=&regs[i]) printf("oops: regs[i]=%x i_regs=%x",(int)&regs[i],(int)i_regs);
3379 }
3380 //else {printf("fp exception in delay slot\n");}
3381 wb_dirtys(i_regs->regmap_entry,i_regs->wasdirty);
3382 if(regs[i].regmap_entry[HOST_CCREG]!=CCREG) emit_loadreg(CCREG,HOST_CCREG);
3383 emit_movimm(start+(i-ds)*4,EAX); // Get PC
2330734f 3384 emit_addimm(HOST_CCREG,ccadj[i],HOST_CCREG); // CHECK: is this right? There should probably be an extra cycle...
2a014d73 3385 emit_far_jump(ds?fp_exception_ds:fp_exception);
8062d65a 3386}
3387
e3c6bdb5 3388static int cop2_is_stalling_op(int i, int *cycles)
3389{
cf95b4f0 3390 if (dops[i].opcode == 0x3a) { // SWC2
e3c6bdb5 3391 *cycles = 0;
3392 return 1;
3393 }
cf95b4f0 3394 if (dops[i].itype == COP2 && (dops[i].opcode2 == 0 || dops[i].opcode2 == 2)) { // MFC2/CFC2
e3c6bdb5 3395 *cycles = 0;
3396 return 1;
3397 }
cf95b4f0 3398 if (dops[i].itype == C2OP) {
e3c6bdb5 3399 *cycles = gte_cycletab[source[i] & 0x3f];
3400 return 1;
3401 }
3402 // ... what about MTC2/CTC2/LWC2?
3403 return 0;
3404}
3405
3406#if 0
3407static void log_gte_stall(int stall, u_int cycle)
3408{
3409 if ((u_int)stall <= 44)
3410 printf("x stall %2d %u\n", stall, cycle + last_count);
e3c6bdb5 3411}
3412
3413static void emit_log_gte_stall(int i, int stall, u_int reglist)
3414{
3415 save_regs(reglist);
3416 if (stall > 0)
3417 emit_movimm(stall, 0);
3418 else
3419 emit_mov(HOST_TEMPREG, 0);
2330734f 3420 emit_addimm(HOST_CCREG, ccadj[i], 1);
e3c6bdb5 3421 emit_far_call(log_gte_stall);
3422 restore_regs(reglist);
3423}
3424#endif
3425
32631e6a 3426static void cop2_do_stall_check(u_int op, int i, const struct regstat *i_regs, u_int reglist)
81dbbf4c 3427{
e3c6bdb5 3428 int j = i, other_gte_op_cycles = -1, stall = -MAXBLOCK, cycles_passed;
3429 int rtmp = reglist_find_free(reglist);
3430
32631e6a 3431 if (HACK_ENABLED(NDHACK_NO_STALLS))
81dbbf4c 3432 return;
81dbbf4c 3433 if (get_reg(i_regs->regmap, CCREG) != HOST_CCREG) {
3434 // happens occasionally... cc evicted? Don't bother then
3435 //printf("no cc %08x\n", start + i*4);
3436 return;
3437 }
cf95b4f0 3438 if (!dops[i].bt) {
e3c6bdb5 3439 for (j = i - 1; j >= 0; j--) {
cf95b4f0 3440 //if (dops[j].is_ds) break;
3441 if (cop2_is_stalling_op(j, &other_gte_op_cycles) || dops[j].bt)
e3c6bdb5 3442 break;
2330734f 3443 if (j > 0 && ccadj[j - 1] > ccadj[j])
3444 break;
e3c6bdb5 3445 }
32631e6a 3446 j = max(j, 0);
e3c6bdb5 3447 }
2330734f 3448 cycles_passed = ccadj[i] - ccadj[j];
e3c6bdb5 3449 if (other_gte_op_cycles >= 0)
3450 stall = other_gte_op_cycles - cycles_passed;
3451 else if (cycles_passed >= 44)
3452 stall = 0; // can't stall
3453 if (stall == -MAXBLOCK && rtmp >= 0) {
3454 // unknown stall, do the expensive runtime check
32631e6a 3455 assem_debug("; cop2_do_stall_check\n");
e3c6bdb5 3456#if 0 // too slow
3457 save_regs(reglist);
3458 emit_movimm(gte_cycletab[op], 0);
2330734f 3459 emit_addimm(HOST_CCREG, ccadj[i], 1);
e3c6bdb5 3460 emit_far_call(call_gteStall);
3461 restore_regs(reglist);
3462#else
3463 host_tempreg_acquire();
3464 emit_readword(&psxRegs.gteBusyCycle, rtmp);
2330734f 3465 emit_addimm(rtmp, -ccadj[i], rtmp);
e3c6bdb5 3466 emit_sub(rtmp, HOST_CCREG, HOST_TEMPREG);
3467 emit_cmpimm(HOST_TEMPREG, 44);
3468 emit_cmovb_reg(rtmp, HOST_CCREG);
3469 //emit_log_gte_stall(i, 0, reglist);
3470 host_tempreg_release();
3471#endif
3472 }
3473 else if (stall > 0) {
3474 //emit_log_gte_stall(i, stall, reglist);
3475 emit_addimm(HOST_CCREG, stall, HOST_CCREG);
3476 }
3477
3478 // save gteBusyCycle, if needed
3479 if (gte_cycletab[op] == 0)
3480 return;
3481 other_gte_op_cycles = -1;
3482 for (j = i + 1; j < slen; j++) {
3483 if (cop2_is_stalling_op(j, &other_gte_op_cycles))
3484 break;
fe807a8a 3485 if (dops[j].is_jump) {
e3c6bdb5 3486 // check ds
3487 if (j + 1 < slen && cop2_is_stalling_op(j + 1, &other_gte_op_cycles))
3488 j++;
3489 break;
3490 }
3491 }
3492 if (other_gte_op_cycles >= 0)
3493 // will handle stall when assembling that op
3494 return;
2330734f 3495 cycles_passed = ccadj[min(j, slen -1)] - ccadj[i];
e3c6bdb5 3496 if (cycles_passed >= 44)
3497 return;
3498 assem_debug("; save gteBusyCycle\n");
3499 host_tempreg_acquire();
3500#if 0
3501 emit_readword(&last_count, HOST_TEMPREG);
3502 emit_add(HOST_TEMPREG, HOST_CCREG, HOST_TEMPREG);
2330734f 3503 emit_addimm(HOST_TEMPREG, ccadj[i], HOST_TEMPREG);
e3c6bdb5 3504 emit_addimm(HOST_TEMPREG, gte_cycletab[op]), HOST_TEMPREG);
3505 emit_writeword(HOST_TEMPREG, &psxRegs.gteBusyCycle);
3506#else
2330734f 3507 emit_addimm(HOST_CCREG, ccadj[i] + gte_cycletab[op], HOST_TEMPREG);
e3c6bdb5 3508 emit_writeword(HOST_TEMPREG, &psxRegs.gteBusyCycle);
3509#endif
3510 host_tempreg_release();
81dbbf4c 3511}
3512
32631e6a 3513static int is_mflohi(int i)
3514{
cf95b4f0 3515 return (dops[i].itype == MOV && (dops[i].rs1 == HIREG || dops[i].rs1 == LOREG));
32631e6a 3516}
3517
3518static int check_multdiv(int i, int *cycles)
3519{
cf95b4f0 3520 if (dops[i].itype != MULTDIV)
32631e6a 3521 return 0;
cf95b4f0 3522 if (dops[i].opcode2 == 0x18 || dops[i].opcode2 == 0x19) // MULT(U)
32631e6a 3523 *cycles = 11; // approx from 7 11 14
3524 else
3525 *cycles = 37;
3526 return 1;
3527}
3528
2330734f 3529static void multdiv_prepare_stall(int i, const struct regstat *i_regs, int ccadj_)
32631e6a 3530{
3531 int j, found = 0, c = 0;
3532 if (HACK_ENABLED(NDHACK_NO_STALLS))
3533 return;
3534 if (get_reg(i_regs->regmap, CCREG) != HOST_CCREG) {
3535 // happens occasionally... cc evicted? Don't bother then
3536 return;
3537 }
3538 for (j = i + 1; j < slen; j++) {
cf95b4f0 3539 if (dops[j].bt)
32631e6a 3540 break;
3541 if ((found = is_mflohi(j)))
3542 break;
fe807a8a 3543 if (dops[j].is_jump) {
32631e6a 3544 // check ds
3545 if (j + 1 < slen && (found = is_mflohi(j + 1)))
3546 j++;
3547 break;
3548 }
3549 }
3550 if (found)
3551 // handle all in multdiv_do_stall()
3552 return;
3553 check_multdiv(i, &c);
3554 assert(c > 0);
3555 assem_debug("; muldiv prepare stall %d\n", c);
3556 host_tempreg_acquire();
2330734f 3557 emit_addimm(HOST_CCREG, ccadj_ + c, HOST_TEMPREG);
32631e6a 3558 emit_writeword(HOST_TEMPREG, &psxRegs.muldivBusyCycle);
3559 host_tempreg_release();
3560}
3561
3562static void multdiv_do_stall(int i, const struct regstat *i_regs)
3563{
3564 int j, known_cycles = 0;
3565 u_int reglist = get_host_reglist(i_regs->regmap);
3566 int rtmp = get_reg(i_regs->regmap, -1);
3567 if (rtmp < 0)
3568 rtmp = reglist_find_free(reglist);
3569 if (HACK_ENABLED(NDHACK_NO_STALLS))
3570 return;
3571 if (get_reg(i_regs->regmap, CCREG) != HOST_CCREG || rtmp < 0) {
3572 // happens occasionally... cc evicted? Don't bother then
3573 //printf("no cc/rtmp %08x\n", start + i*4);
3574 return;
3575 }
cf95b4f0 3576 if (!dops[i].bt) {
32631e6a 3577 for (j = i - 1; j >= 0; j--) {
cf95b4f0 3578 if (dops[j].is_ds) break;
2330734f 3579 if (check_multdiv(j, &known_cycles))
32631e6a 3580 break;
3581 if (is_mflohi(j))
3582 // already handled by this op
3583 return;
2330734f 3584 if (dops[j].bt || (j > 0 && ccadj[j - 1] > ccadj[j]))
3585 break;
32631e6a 3586 }
3587 j = max(j, 0);
3588 }
3589 if (known_cycles > 0) {
2330734f 3590 known_cycles -= ccadj[i] - ccadj[j];
32631e6a 3591 assem_debug("; muldiv stall resolved %d\n", known_cycles);
3592 if (known_cycles > 0)
3593 emit_addimm(HOST_CCREG, known_cycles, HOST_CCREG);
3594 return;
3595 }
3596 assem_debug("; muldiv stall unresolved\n");
3597 host_tempreg_acquire();
3598 emit_readword(&psxRegs.muldivBusyCycle, rtmp);
2330734f 3599 emit_addimm(rtmp, -ccadj[i], rtmp);
32631e6a 3600 emit_sub(rtmp, HOST_CCREG, HOST_TEMPREG);
3601 emit_cmpimm(HOST_TEMPREG, 37);
3602 emit_cmovb_reg(rtmp, HOST_CCREG);
3603 //emit_log_gte_stall(i, 0, reglist);
3604 host_tempreg_release();
3605}
3606
8062d65a 3607static void cop2_get_dreg(u_int copr,signed char tl,signed char temp)
3608{
3609 switch (copr) {
3610 case 1:
3611 case 3:
3612 case 5:
3613 case 8:
3614 case 9:
3615 case 10:
3616 case 11:
3617 emit_readword(&reg_cop2d[copr],tl);
3618 emit_signextend16(tl,tl);
3619 emit_writeword(tl,&reg_cop2d[copr]); // hmh
3620 break;
3621 case 7:
3622 case 16:
3623 case 17:
3624 case 18:
3625 case 19:
3626 emit_readword(&reg_cop2d[copr],tl);
3627 emit_andimm(tl,0xffff,tl);
3628 emit_writeword(tl,&reg_cop2d[copr]);
3629 break;
3630 case 15:
3631 emit_readword(&reg_cop2d[14],tl); // SXY2
3632 emit_writeword(tl,&reg_cop2d[copr]);
3633 break;
3634 case 28:
3635 case 29:
3968e69e 3636 c2op_mfc2_29_assemble(tl,temp);
8062d65a 3637 break;
3638 default:
3639 emit_readword(&reg_cop2d[copr],tl);
3640 break;
3641 }
3642}
3643
3644static void cop2_put_dreg(u_int copr,signed char sl,signed char temp)
3645{
3646 switch (copr) {
3647 case 15:
3648 emit_readword(&reg_cop2d[13],temp); // SXY1
3649 emit_writeword(sl,&reg_cop2d[copr]);
3650 emit_writeword(temp,&reg_cop2d[12]); // SXY0
3651 emit_readword(&reg_cop2d[14],temp); // SXY2
3652 emit_writeword(sl,&reg_cop2d[14]);
3653 emit_writeword(temp,&reg_cop2d[13]); // SXY1
3654 break;
3655 case 28:
3656 emit_andimm(sl,0x001f,temp);
3657 emit_shlimm(temp,7,temp);
3658 emit_writeword(temp,&reg_cop2d[9]);
3659 emit_andimm(sl,0x03e0,temp);
3660 emit_shlimm(temp,2,temp);
3661 emit_writeword(temp,&reg_cop2d[10]);
3662 emit_andimm(sl,0x7c00,temp);
3663 emit_shrimm(temp,3,temp);
3664 emit_writeword(temp,&reg_cop2d[11]);
3665 emit_writeword(sl,&reg_cop2d[28]);
3666 break;
3667 case 30:
3968e69e 3668 emit_xorsar_imm(sl,sl,31,temp);
be516ebe 3669#if defined(HAVE_ARMV5) || defined(__aarch64__)
8062d65a 3670 emit_clz(temp,temp);
3671#else
3672 emit_movs(temp,HOST_TEMPREG);
3673 emit_movimm(0,temp);
3674 emit_jeq((int)out+4*4);
3675 emit_addpl_imm(temp,1,temp);
3676 emit_lslpls_imm(HOST_TEMPREG,1,HOST_TEMPREG);
3677 emit_jns((int)out-2*4);
3678#endif
3679 emit_writeword(sl,&reg_cop2d[30]);
3680 emit_writeword(temp,&reg_cop2d[31]);
3681 break;
3682 case 31:
3683 break;
3684 default:
3685 emit_writeword(sl,&reg_cop2d[copr]);
3686 break;
3687 }
3688}
3689
2330734f 3690static void c2ls_assemble(int i, const struct regstat *i_regs, int ccadj_)
b9b61529 3691{
3692 int s,tl;
3693 int ar;
3694 int offset;
1fd1aceb 3695 int memtarget=0,c=0;
b14b6a8f 3696 void *jaddr2=NULL;
3697 enum stub_type type;
b9b61529 3698 int agr=AGEN1+(i&1);
37387d8b 3699 int offset_reg = -1;
3700 int fastio_reg_override = -1;
81dbbf4c 3701 u_int reglist=get_host_reglist(i_regs->regmap);
b9b61529 3702 u_int copr=(source[i]>>16)&0x1f;
cf95b4f0 3703 s=get_reg(i_regs->regmap,dops[i].rs1);
b9b61529 3704 tl=get_reg(i_regs->regmap,FTEMP);
3705 offset=imm[i];
cf95b4f0 3706 assert(dops[i].rs1>0);
b9b61529 3707 assert(tl>=0);
b9b61529 3708
b9b61529 3709 if(i_regs->regmap[HOST_CCREG]==CCREG)
3710 reglist&=~(1<<HOST_CCREG);
3711
3712 // get the address
cf95b4f0 3713 if (dops[i].opcode==0x3a) { // SWC2
b9b61529 3714 ar=get_reg(i_regs->regmap,agr);
3715 if(ar<0) ar=get_reg(i_regs->regmap,-1);
3716 reglist|=1<<ar;
3717 } else { // LWC2
3718 ar=tl;
3719 }
1fd1aceb 3720 if(s>=0) c=(i_regs->wasconst>>s)&1;
3721 memtarget=c&&(((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE);
b9b61529 3722 if (!offset&&!c&&s>=0) ar=s;
3723 assert(ar>=0);
3724
32631e6a 3725 cop2_do_stall_check(0, i, i_regs, reglist);
3726
cf95b4f0 3727 if (dops[i].opcode==0x3a) { // SWC2
3968e69e 3728 cop2_get_dreg(copr,tl,-1);
1fd1aceb 3729 type=STOREW_STUB;
b9b61529 3730 }
1fd1aceb 3731 else
b9b61529 3732 type=LOADW_STUB;
1fd1aceb 3733
3734 if(c&&!memtarget) {
b14b6a8f 3735 jaddr2=out;
1fd1aceb 3736 emit_jmp(0); // inline_readstub/inline_writestub?
b9b61529 3737 }
1fd1aceb 3738 else {
3739 if(!c) {
37387d8b 3740 jaddr2 = emit_fastpath_cmp_jump(i, i_regs, ar,
3741 &offset_reg, &fastio_reg_override);
3742 }
3743 else if (ram_offset && memtarget) {
3744 offset_reg = get_ro_reg(i_regs, 0);
3745 }
3746 switch (dops[i].opcode) {
3747 case 0x32: { // LWC2
3748 int a = ar;
3749 if (fastio_reg_override >= 0)
3750 a = fastio_reg_override;
3751 do_load_word(a, tl, offset_reg);
3752 break;
1fd1aceb 3753 }
37387d8b 3754 case 0x3a: { // SWC2
1fd1aceb 3755 #ifdef DESTRUCTIVE_SHIFT
3756 if(!offset&&!c&&s>=0) emit_mov(s,ar);
3757 #endif
37387d8b 3758 int a = ar;
3759 if (fastio_reg_override >= 0)
3760 a = fastio_reg_override;
3761 do_store_word(a, 0, tl, offset_reg, 1);
3762 break;
3763 }
3764 default:
3765 assert(0);
1fd1aceb 3766 }
b9b61529 3767 }
37387d8b 3768 if (fastio_reg_override == HOST_TEMPREG || offset_reg == HOST_TEMPREG)
d1e4ebd9 3769 host_tempreg_release();
b9b61529 3770 if(jaddr2)
2330734f 3771 add_stub_r(type,jaddr2,out,i,ar,i_regs,ccadj_,reglist);
cf95b4f0 3772 if(dops[i].opcode==0x3a) // SWC2
3773 if(!(i_regs->waswritten&(1<<dops[i].rs1)) && !HACK_ENABLED(NDHACK_NO_SMC_CHECK)) {
b9b61529 3774#if defined(HOST_IMM8)
3775 int ir=get_reg(i_regs->regmap,INVCP);
3776 assert(ir>=0);
3777 emit_cmpmem_indexedsr12_reg(ir,ar,1);
3778#else
643aeae3 3779 emit_cmpmem_indexedsr12_imm(invalid_code,ar,1);
b9b61529 3780#endif
0bbd1454 3781 #if defined(HAVE_CONDITIONAL_CALL) && !defined(DESTRUCTIVE_SHIFT)
3782 emit_callne(invalidate_addr_reg[ar]);
3783 #else
b14b6a8f 3784 void *jaddr3 = out;
b9b61529 3785 emit_jne(0);
b14b6a8f 3786 add_stub(INVCODE_STUB,jaddr3,out,reglist|(1<<HOST_CCREG),ar,0,0,0);
0bbd1454 3787 #endif
b9b61529 3788 }
cf95b4f0 3789 if (dops[i].opcode==0x32) { // LWC2
d1e4ebd9 3790 host_tempreg_acquire();
b9b61529 3791 cop2_put_dreg(copr,tl,HOST_TEMPREG);
d1e4ebd9 3792 host_tempreg_release();
b9b61529 3793 }
3794}
3795
81dbbf4c 3796static void cop2_assemble(int i, const struct regstat *i_regs)
8062d65a 3797{
81dbbf4c 3798 u_int copr = (source[i]>>11) & 0x1f;
3799 signed char temp = get_reg(i_regs->regmap, -1);
3800
32631e6a 3801 if (!HACK_ENABLED(NDHACK_NO_STALLS)) {
3802 u_int reglist = reglist_exclude(get_host_reglist(i_regs->regmap), temp, -1);
cf95b4f0 3803 if (dops[i].opcode2 == 0 || dops[i].opcode2 == 2) { // MFC2/CFC2
3804 signed char tl = get_reg(i_regs->regmap, dops[i].rt1);
32631e6a 3805 reglist = reglist_exclude(reglist, tl, -1);
81dbbf4c 3806 }
32631e6a 3807 cop2_do_stall_check(0, i, i_regs, reglist);
81dbbf4c 3808 }
cf95b4f0 3809 if (dops[i].opcode2==0) { // MFC2
3810 signed char tl=get_reg(i_regs->regmap,dops[i].rt1);
3811 if(tl>=0&&dops[i].rt1!=0)
8062d65a 3812 cop2_get_dreg(copr,tl,temp);
3813 }
cf95b4f0 3814 else if (dops[i].opcode2==4) { // MTC2
3815 signed char sl=get_reg(i_regs->regmap,dops[i].rs1);
8062d65a 3816 cop2_put_dreg(copr,sl,temp);
3817 }
cf95b4f0 3818 else if (dops[i].opcode2==2) // CFC2
8062d65a 3819 {
cf95b4f0 3820 signed char tl=get_reg(i_regs->regmap,dops[i].rt1);
3821 if(tl>=0&&dops[i].rt1!=0)
8062d65a 3822 emit_readword(&reg_cop2c[copr],tl);
3823 }
cf95b4f0 3824 else if (dops[i].opcode2==6) // CTC2
8062d65a 3825 {
cf95b4f0 3826 signed char sl=get_reg(i_regs->regmap,dops[i].rs1);
8062d65a 3827 switch(copr) {
3828 case 4:
3829 case 12:
3830 case 20:
3831 case 26:
3832 case 27:
3833 case 29:
3834 case 30:
3835 emit_signextend16(sl,temp);
3836 break;
3837 case 31:
3968e69e 3838 c2op_ctc2_31_assemble(sl,temp);
8062d65a 3839 break;
3840 default:
3841 temp=sl;
3842 break;
3843 }
3844 emit_writeword(temp,&reg_cop2c[copr]);
3845 assert(sl>=0);
3846 }
3847}
3848
3968e69e 3849static void do_unalignedwritestub(int n)
3850{
3851 assem_debug("do_unalignedwritestub %x\n",start+stubs[n].a*4);
3852 literal_pool(256);
3853 set_jump_target(stubs[n].addr, out);
3854
3855 int i=stubs[n].a;
3856 struct regstat *i_regs=(struct regstat *)stubs[n].c;
3857 int addr=stubs[n].b;
3858 u_int reglist=stubs[n].e;
3859 signed char *i_regmap=i_regs->regmap;
3860 int temp2=get_reg(i_regmap,FTEMP);
3861 int rt;
cf95b4f0 3862 rt=get_reg(i_regmap,dops[i].rs2);
3968e69e 3863 assert(rt>=0);
3864 assert(addr>=0);
cf95b4f0 3865 assert(dops[i].opcode==0x2a||dops[i].opcode==0x2e); // SWL/SWR only implemented
3968e69e 3866 reglist|=(1<<addr);
3867 reglist&=~(1<<temp2);
3868
3968e69e 3869 // don't bother with it and call write handler
3870 save_regs(reglist);
3871 pass_args(addr,rt);
3872 int cc=get_reg(i_regmap,CCREG);
3873 if(cc<0)
3874 emit_loadreg(CCREG,2);
2330734f 3875 emit_addimm(cc<0?2:cc,(int)stubs[n].d+1,2);
cf95b4f0 3876 emit_far_call((dops[i].opcode==0x2a?jump_handle_swl:jump_handle_swr));
2330734f 3877 emit_addimm(0,-((int)stubs[n].d+1),cc<0?2:cc);
3968e69e 3878 if(cc<0)
3879 emit_storereg(CCREG,2);
3880 restore_regs(reglist);
3881 emit_jmp(stubs[n].retaddr); // return address
3968e69e 3882}
3883
57871462 3884#ifndef multdiv_assemble
3885void multdiv_assemble(int i,struct regstat *i_regs)
3886{
3887 printf("Need multdiv_assemble for this architecture.\n");
7c3a5182 3888 abort();
57871462 3889}
3890#endif
3891
2330734f 3892static void mov_assemble(int i, const struct regstat *i_regs)
57871462 3893{
cf95b4f0 3894 //if(dops[i].opcode2==0x10||dops[i].opcode2==0x12) { // MFHI/MFLO
3895 //if(dops[i].opcode2==0x11||dops[i].opcode2==0x13) { // MTHI/MTLO
3896 if(dops[i].rt1) {
7c3a5182 3897 signed char sl,tl;
cf95b4f0 3898 tl=get_reg(i_regs->regmap,dops[i].rt1);
57871462 3899 //assert(tl>=0);
3900 if(tl>=0) {
cf95b4f0 3901 sl=get_reg(i_regs->regmap,dops[i].rs1);
57871462 3902 if(sl>=0) emit_mov(sl,tl);
cf95b4f0 3903 else emit_loadreg(dops[i].rs1,tl);
57871462 3904 }
3905 }
cf95b4f0 3906 if (dops[i].rs1 == HIREG || dops[i].rs1 == LOREG) // MFHI/MFLO
32631e6a 3907 multdiv_do_stall(i, i_regs);
57871462 3908}
3909
3968e69e 3910// call interpreter, exception handler, things that change pc/regs/cycles ...
2330734f 3911static void call_c_cpu_handler(int i, const struct regstat *i_regs, int ccadj_, u_int pc, void *func)
57871462 3912{
3913 signed char ccreg=get_reg(i_regs->regmap,CCREG);
3914 assert(ccreg==HOST_CCREG);
3915 assert(!is_delayslot);
581335b0 3916 (void)ccreg;
3968e69e 3917
3918 emit_movimm(pc,3); // Get PC
3919 emit_readword(&last_count,2);
3920 emit_writeword(3,&psxRegs.pc);
2330734f 3921 emit_addimm(HOST_CCREG,ccadj_,HOST_CCREG);
3968e69e 3922 emit_add(2,HOST_CCREG,2);
3923 emit_writeword(2,&psxRegs.cycle);
2a014d73 3924 emit_far_call(func);
3925 emit_far_jump(jump_to_new_pc);
3968e69e 3926}
3927
2330734f 3928static void syscall_assemble(int i, const struct regstat *i_regs, int ccadj_)
3968e69e 3929{
3930 emit_movimm(0x20,0); // cause code
3931 emit_movimm(0,1); // not in delay slot
2330734f 3932 call_c_cpu_handler(i, i_regs, ccadj_, start+i*4, psxException);
7139f3c8 3933}
3934
2330734f 3935static void hlecall_assemble(int i, const struct regstat *i_regs, int ccadj_)
7139f3c8 3936{
3968e69e 3937 void *hlefunc = psxNULL;
dd79da89 3938 uint32_t hleCode = source[i] & 0x03ffffff;
3968e69e 3939 if (hleCode < ARRAY_SIZE(psxHLEt))
3940 hlefunc = psxHLEt[hleCode];
3941
2330734f 3942 call_c_cpu_handler(i, i_regs, ccadj_, start + i*4+4, hlefunc);
57871462 3943}
3944
2330734f 3945static void intcall_assemble(int i, const struct regstat *i_regs, int ccadj_)
1e973cb0 3946{
2330734f 3947 call_c_cpu_handler(i, i_regs, ccadj_, start + i*4, execI);
1e973cb0 3948}
3949
8062d65a 3950static void speculate_mov(int rs,int rt)
3951{
3952 if(rt!=0) {
3953 smrv_strong_next|=1<<rt;
3954 smrv[rt]=smrv[rs];
3955 }
3956}
3957
3958static void speculate_mov_weak(int rs,int rt)
3959{
3960 if(rt!=0) {
3961 smrv_weak_next|=1<<rt;
3962 smrv[rt]=smrv[rs];
3963 }
3964}
3965
3966static void speculate_register_values(int i)
3967{
3968 if(i==0) {
3969 memcpy(smrv,psxRegs.GPR.r,sizeof(smrv));
3970 // gp,sp are likely to stay the same throughout the block
3971 smrv_strong_next=(1<<28)|(1<<29)|(1<<30);
3972 smrv_weak_next=~smrv_strong_next;
3973 //printf(" llr %08x\n", smrv[4]);
3974 }
3975 smrv_strong=smrv_strong_next;
3976 smrv_weak=smrv_weak_next;
cf95b4f0 3977 switch(dops[i].itype) {
8062d65a 3978 case ALU:
cf95b4f0 3979 if ((smrv_strong>>dops[i].rs1)&1) speculate_mov(dops[i].rs1,dops[i].rt1);
3980 else if((smrv_strong>>dops[i].rs2)&1) speculate_mov(dops[i].rs2,dops[i].rt1);
3981 else if((smrv_weak>>dops[i].rs1)&1) speculate_mov_weak(dops[i].rs1,dops[i].rt1);
3982 else if((smrv_weak>>dops[i].rs2)&1) speculate_mov_weak(dops[i].rs2,dops[i].rt1);
8062d65a 3983 else {
cf95b4f0 3984 smrv_strong_next&=~(1<<dops[i].rt1);
3985 smrv_weak_next&=~(1<<dops[i].rt1);
8062d65a 3986 }
3987 break;
3988 case SHIFTIMM:
cf95b4f0 3989 smrv_strong_next&=~(1<<dops[i].rt1);
3990 smrv_weak_next&=~(1<<dops[i].rt1);
8062d65a 3991 // fallthrough
3992 case IMM16:
cf95b4f0 3993 if(dops[i].rt1&&is_const(&regs[i],dops[i].rt1)) {
3994 int value,hr=get_reg(regs[i].regmap,dops[i].rt1);
8062d65a 3995 if(hr>=0) {
3996 if(get_final_value(hr,i,&value))
cf95b4f0 3997 smrv[dops[i].rt1]=value;
3998 else smrv[dops[i].rt1]=constmap[i][hr];
3999 smrv_strong_next|=1<<dops[i].rt1;
8062d65a 4000 }
4001 }
4002 else {
cf95b4f0 4003 if ((smrv_strong>>dops[i].rs1)&1) speculate_mov(dops[i].rs1,dops[i].rt1);
4004 else if((smrv_weak>>dops[i].rs1)&1) speculate_mov_weak(dops[i].rs1,dops[i].rt1);
8062d65a 4005 }
4006 break;
4007 case LOAD:
cf95b4f0 4008 if(start<0x2000&&(dops[i].rt1==26||(smrv[dops[i].rt1]>>24)==0xa0)) {
8062d65a 4009 // special case for BIOS
cf95b4f0 4010 smrv[dops[i].rt1]=0xa0000000;
4011 smrv_strong_next|=1<<dops[i].rt1;
8062d65a 4012 break;
4013 }
4014 // fallthrough
4015 case SHIFT:
4016 case LOADLR:
4017 case MOV:
cf95b4f0 4018 smrv_strong_next&=~(1<<dops[i].rt1);
4019 smrv_weak_next&=~(1<<dops[i].rt1);
8062d65a 4020 break;
4021 case COP0:
4022 case COP2:
cf95b4f0 4023 if(dops[i].opcode2==0||dops[i].opcode2==2) { // MFC/CFC
4024 smrv_strong_next&=~(1<<dops[i].rt1);
4025 smrv_weak_next&=~(1<<dops[i].rt1);
8062d65a 4026 }
4027 break;
4028 case C2LS:
cf95b4f0 4029 if (dops[i].opcode==0x32) { // LWC2
4030 smrv_strong_next&=~(1<<dops[i].rt1);
4031 smrv_weak_next&=~(1<<dops[i].rt1);
8062d65a 4032 }
4033 break;
4034 }
4035#if 0
4036 int r=4;
4037 printf("x %08x %08x %d %d c %08x %08x\n",smrv[r],start+i*4,
4038 ((smrv_strong>>r)&1),(smrv_weak>>r)&1,regs[i].isconst,regs[i].wasconst);
4039#endif
4040}
4041
2330734f 4042static void ujump_assemble(int i, const struct regstat *i_regs);
4043static void rjump_assemble(int i, const struct regstat *i_regs);
4044static void cjump_assemble(int i, const struct regstat *i_regs);
4045static void sjump_assemble(int i, const struct regstat *i_regs);
4046static void pagespan_assemble(int i, const struct regstat *i_regs);
4047
4048static int assemble(int i, const struct regstat *i_regs, int ccadj_)
57871462 4049{
2330734f 4050 int ds = 0;
4051 switch (dops[i].itype) {
57871462 4052 case ALU:
2330734f 4053 alu_assemble(i, i_regs);
4054 break;
57871462 4055 case IMM16:
2330734f 4056 imm16_assemble(i, i_regs);
4057 break;
57871462 4058 case SHIFT:
2330734f 4059 shift_assemble(i, i_regs);
4060 break;
57871462 4061 case SHIFTIMM:
2330734f 4062 shiftimm_assemble(i, i_regs);
4063 break;
57871462 4064 case LOAD:
2330734f 4065 load_assemble(i, i_regs, ccadj_);
4066 break;
57871462 4067 case LOADLR:
2330734f 4068 loadlr_assemble(i, i_regs, ccadj_);
4069 break;
57871462 4070 case STORE:
2330734f 4071 store_assemble(i, i_regs, ccadj_);
4072 break;
57871462 4073 case STORELR:
2330734f 4074 storelr_assemble(i, i_regs, ccadj_);
4075 break;
57871462 4076 case COP0:
2330734f 4077 cop0_assemble(i, i_regs, ccadj_);
4078 break;
57871462 4079 case COP1:
2330734f 4080 cop1_assemble(i, i_regs);
4081 break;
57871462 4082 case C1LS:
2330734f 4083 c1ls_assemble(i, i_regs);
4084 break;
b9b61529 4085 case COP2:
2330734f 4086 cop2_assemble(i, i_regs);
4087 break;
b9b61529 4088 case C2LS:
2330734f 4089 c2ls_assemble(i, i_regs, ccadj_);
4090 break;
b9b61529 4091 case C2OP:
2330734f 4092 c2op_assemble(i, i_regs);
4093 break;
57871462 4094 case MULTDIV:
2330734f 4095 multdiv_assemble(i, i_regs);
4096 multdiv_prepare_stall(i, i_regs, ccadj_);
32631e6a 4097 break;
57871462 4098 case MOV:
2330734f 4099 mov_assemble(i, i_regs);
4100 break;
4101 case SYSCALL:
4102 syscall_assemble(i, i_regs, ccadj_);
4103 break;
4104 case HLECALL:
4105 hlecall_assemble(i, i_regs, ccadj_);
4106 break;
4107 case INTCALL:
4108 intcall_assemble(i, i_regs, ccadj_);
4109 break;
4110 case UJUMP:
4111 ujump_assemble(i, i_regs);
4112 ds = 1;
4113 break;
4114 case RJUMP:
4115 rjump_assemble(i, i_regs);
4116 ds = 1;
4117 break;
4118 case CJUMP:
4119 cjump_assemble(i, i_regs);
4120 ds = 1;
4121 break;
4122 case SJUMP:
4123 sjump_assemble(i, i_regs);
4124 ds = 1;
4125 break;
4126 case SPAN:
4127 pagespan_assemble(i, i_regs);
4128 break;
24058131 4129 case NOP:
2330734f 4130 case OTHER:
4131 case NI:
4132 // not handled, just skip
4133 break;
4134 default:
4135 assert(0);
4136 }
4137 return ds;
4138}
4139
4140static void ds_assemble(int i, const struct regstat *i_regs)
4141{
4142 speculate_register_values(i);
4143 is_delayslot = 1;
4144 switch (dops[i].itype) {
57871462 4145 case SYSCALL:
7139f3c8 4146 case HLECALL:
1e973cb0 4147 case INTCALL:
57871462 4148 case SPAN:
4149 case UJUMP:
4150 case RJUMP:
4151 case CJUMP:
4152 case SJUMP:
c43b5311 4153 SysPrintf("Jump in the delay slot. This is probably a bug.\n");
2330734f 4154 break;
4155 default:
4156 assemble(i, i_regs, ccadj[i]);
57871462 4157 }
2330734f 4158 is_delayslot = 0;
57871462 4159}
4160
4161// Is the branch target a valid internal jump?
ad49de89 4162static int internal_branch(int addr)
57871462 4163{
4164 if(addr&1) return 0; // Indirect (register) jump
4165 if(addr>=start && addr<start+slen*4-4)
4166 {
71e490c5 4167 return 1;
57871462 4168 }
4169 return 0;
4170}
4171
ad49de89 4172static void wb_invalidate(signed char pre[],signed char entry[],uint64_t dirty,uint64_t u)
57871462 4173{
4174 int hr;
4175 for(hr=0;hr<HOST_REGS;hr++) {
4176 if(hr!=EXCLUDE_REG) {
4177 if(pre[hr]!=entry[hr]) {
4178 if(pre[hr]>=0) {
4179 if((dirty>>hr)&1) {
4180 if(get_reg(entry,pre[hr])<0) {
00fa9369 4181 assert(pre[hr]<64);
4182 if(!((u>>pre[hr])&1))
4183 emit_storereg(pre[hr],hr);
57871462 4184 }
4185 }
4186 }
4187 }
4188 }
4189 }
4190 // Move from one register to another (no writeback)
4191 for(hr=0;hr<HOST_REGS;hr++) {
4192 if(hr!=EXCLUDE_REG) {
4193 if(pre[hr]!=entry[hr]) {
4194 if(pre[hr]>=0&&(pre[hr]&63)<TEMPREG) {
4195 int nr;
4196 if((nr=get_reg(entry,pre[hr]))>=0) {
4197 emit_mov(hr,nr);
4198 }
4199 }
4200 }
4201 }
4202 }
4203}
57871462 4204
4205// Load the specified registers
4206// This only loads the registers given as arguments because
4207// we don't want to load things that will be overwritten
ad49de89 4208static void load_regs(signed char entry[],signed char regmap[],int rs1,int rs2)
57871462 4209{
4210 int hr;
4211 // Load 32-bit regs
4212 for(hr=0;hr<HOST_REGS;hr++) {
4213 if(hr!=EXCLUDE_REG&&regmap[hr]>=0) {
4214 if(entry[hr]!=regmap[hr]) {
4215 if(regmap[hr]==rs1||regmap[hr]==rs2)
4216 {
4217 if(regmap[hr]==0) {
4218 emit_zeroreg(hr);
4219 }
4220 else
4221 {
4222 emit_loadreg(regmap[hr],hr);
4223 }
4224 }
4225 }
4226 }
4227 }
57871462 4228}
4229
4230// Load registers prior to the start of a loop
4231// so that they are not loaded within the loop
4232static void loop_preload(signed char pre[],signed char entry[])
4233{
4234 int hr;
4235 for(hr=0;hr<HOST_REGS;hr++) {
4236 if(hr!=EXCLUDE_REG) {
4237 if(pre[hr]!=entry[hr]) {
4238 if(entry[hr]>=0) {
4239 if(get_reg(pre,entry[hr])<0) {
4240 assem_debug("loop preload:\n");
4241 //printf("loop preload: %d\n",hr);
4242 if(entry[hr]==0) {
4243 emit_zeroreg(hr);
4244 }
4245 else if(entry[hr]<TEMPREG)
4246 {
4247 emit_loadreg(entry[hr],hr);
4248 }
4249 else if(entry[hr]-64<TEMPREG)
4250 {
4251 emit_loadreg(entry[hr],hr);
4252 }
4253 }
4254 }
4255 }
4256 }
4257 }
4258}
4259
4260// Generate address for load/store instruction
b9b61529 4261// goes to AGEN for writes, FTEMP for LOADLR and cop1/2 loads
2330734f 4262void address_generation(int i, const struct regstat *i_regs, signed char entry[])
57871462 4263{
37387d8b 4264 if (dops[i].is_load || dops[i].is_store) {
5194fb95 4265 int ra=-1;
57871462 4266 int agr=AGEN1+(i&1);
cf95b4f0 4267 if(dops[i].itype==LOAD) {
4268 ra=get_reg(i_regs->regmap,dops[i].rt1);
9f51b4b9 4269 if(ra<0) ra=get_reg(i_regs->regmap,-1);
535d208a 4270 assert(ra>=0);
57871462 4271 }
cf95b4f0 4272 if(dops[i].itype==LOADLR) {
57871462 4273 ra=get_reg(i_regs->regmap,FTEMP);
4274 }
cf95b4f0 4275 if(dops[i].itype==STORE||dops[i].itype==STORELR) {
57871462 4276 ra=get_reg(i_regs->regmap,agr);
4277 if(ra<0) ra=get_reg(i_regs->regmap,-1);
4278 }
37387d8b 4279 if(dops[i].itype==C2LS) {
cf95b4f0 4280 if ((dops[i].opcode&0x3b)==0x31||(dops[i].opcode&0x3b)==0x32) // LWC1/LDC1/LWC2/LDC2
57871462 4281 ra=get_reg(i_regs->regmap,FTEMP);
1fd1aceb 4282 else { // SWC1/SDC1/SWC2/SDC2
57871462 4283 ra=get_reg(i_regs->regmap,agr);
4284 if(ra<0) ra=get_reg(i_regs->regmap,-1);
4285 }
4286 }
cf95b4f0 4287 int rs=get_reg(i_regs->regmap,dops[i].rs1);
57871462 4288 if(ra>=0) {
4289 int offset=imm[i];
4290 int c=(i_regs->wasconst>>rs)&1;
cf95b4f0 4291 if(dops[i].rs1==0) {
57871462 4292 // Using r0 as a base address
57871462 4293 if(!entry||entry[ra]!=agr) {
cf95b4f0 4294 if (dops[i].opcode==0x22||dops[i].opcode==0x26) {
57871462 4295 emit_movimm(offset&0xFFFFFFFC,ra); // LWL/LWR
cf95b4f0 4296 }else if (dops[i].opcode==0x1a||dops[i].opcode==0x1b) {
57871462 4297 emit_movimm(offset&0xFFFFFFF8,ra); // LDL/LDR
4298 }else{
4299 emit_movimm(offset,ra);
4300 }
4301 } // else did it in the previous cycle
4302 }
4303 else if(rs<0) {
cf95b4f0 4304 if(!entry||entry[ra]!=dops[i].rs1)
4305 emit_loadreg(dops[i].rs1,ra);
4306 //if(!entry||entry[ra]!=dops[i].rs1)
57871462 4307 // printf("poor load scheduling!\n");
4308 }
4309 else if(c) {
cf95b4f0 4310 if(dops[i].rs1!=dops[i].rt1||dops[i].itype!=LOAD) {
57871462 4311 if(!entry||entry[ra]!=agr) {
cf95b4f0 4312 if (dops[i].opcode==0x22||dops[i].opcode==0x26) {
57871462 4313 emit_movimm((constmap[i][rs]+offset)&0xFFFFFFFC,ra); // LWL/LWR
cf95b4f0 4314 }else if (dops[i].opcode==0x1a||dops[i].opcode==0x1b) {
57871462 4315 emit_movimm((constmap[i][rs]+offset)&0xFFFFFFF8,ra); // LDL/LDR
4316 }else{
57871462 4317 emit_movimm(constmap[i][rs]+offset,ra);
8575a877 4318 regs[i].loadedconst|=1<<ra;
57871462 4319 }
4320 } // else did it in the previous cycle
4321 } // else load_consts already did it
4322 }
cf95b4f0 4323 if(offset&&!c&&dops[i].rs1) {
57871462 4324 if(rs>=0) {
4325 emit_addimm(rs,offset,ra);
4326 }else{
4327 emit_addimm(ra,offset,ra);
4328 }
4329 }
4330 }
4331 }
4332 // Preload constants for next instruction
37387d8b 4333 if (dops[i+1].is_load || dops[i+1].is_store) {
57871462 4334 int agr,ra;
57871462 4335 // Actual address
4336 agr=AGEN1+((i+1)&1);
4337 ra=get_reg(i_regs->regmap,agr);
4338 if(ra>=0) {
cf95b4f0 4339 int rs=get_reg(regs[i+1].regmap,dops[i+1].rs1);
57871462 4340 int offset=imm[i+1];
4341 int c=(regs[i+1].wasconst>>rs)&1;
cf95b4f0 4342 if(c&&(dops[i+1].rs1!=dops[i+1].rt1||dops[i+1].itype!=LOAD)) {
4343 if (dops[i+1].opcode==0x22||dops[i+1].opcode==0x26) {
57871462 4344 emit_movimm((constmap[i+1][rs]+offset)&0xFFFFFFFC,ra); // LWL/LWR
cf95b4f0 4345 }else if (dops[i+1].opcode==0x1a||dops[i+1].opcode==0x1b) {
57871462 4346 emit_movimm((constmap[i+1][rs]+offset)&0xFFFFFFF8,ra); // LDL/LDR
4347 }else{
57871462 4348 emit_movimm(constmap[i+1][rs]+offset,ra);
8575a877 4349 regs[i+1].loadedconst|=1<<ra;
57871462 4350 }
4351 }
cf95b4f0 4352 else if(dops[i+1].rs1==0) {
57871462 4353 // Using r0 as a base address
cf95b4f0 4354 if (dops[i+1].opcode==0x22||dops[i+1].opcode==0x26) {
57871462 4355 emit_movimm(offset&0xFFFFFFFC,ra); // LWL/LWR
cf95b4f0 4356 }else if (dops[i+1].opcode==0x1a||dops[i+1].opcode==0x1b) {
57871462 4357 emit_movimm(offset&0xFFFFFFF8,ra); // LDL/LDR
4358 }else{
4359 emit_movimm(offset,ra);
4360 }
4361 }
4362 }
4363 }
4364}
4365
e2b5e7aa 4366static int get_final_value(int hr, int i, int *value)
57871462 4367{
4368 int reg=regs[i].regmap[hr];
4369 while(i<slen-1) {
4370 if(regs[i+1].regmap[hr]!=reg) break;
4371 if(!((regs[i+1].isconst>>hr)&1)) break;
cf95b4f0 4372 if(dops[i+1].bt) break;
57871462 4373 i++;
4374 }
4375 if(i<slen-1) {
fe807a8a 4376 if (dops[i].is_jump) {
57871462 4377 *value=constmap[i][hr];
4378 return 1;
4379 }
cf95b4f0 4380 if(!dops[i+1].bt) {
fe807a8a 4381 if (dops[i+1].is_jump) {
57871462 4382 // Load in delay slot, out-of-order execution
cf95b4f0 4383 if(dops[i+2].itype==LOAD&&dops[i+2].rs1==reg&&dops[i+2].rt1==reg&&((regs[i+1].wasconst>>hr)&1))
57871462 4384 {
57871462 4385 // Precompute load address
4386 *value=constmap[i][hr]+imm[i+2];
4387 return 1;
4388 }
4389 }
cf95b4f0 4390 if(dops[i+1].itype==LOAD&&dops[i+1].rs1==reg&&dops[i+1].rt1==reg)
57871462 4391 {
57871462 4392 // Precompute load address
4393 *value=constmap[i][hr]+imm[i+1];
643aeae3 4394 //printf("c=%x imm=%lx\n",(long)constmap[i][hr],imm[i+1]);
57871462 4395 return 1;
4396 }
4397 }
4398 }
4399 *value=constmap[i][hr];
643aeae3 4400 //printf("c=%lx\n",(long)constmap[i][hr]);
57871462 4401 if(i==slen-1) return 1;
00fa9369 4402 assert(reg < 64);
4403 return !((unneeded_reg[i+1]>>reg)&1);
57871462 4404}
4405
4406// Load registers with known constants
ad49de89 4407static void load_consts(signed char pre[],signed char regmap[],int i)
57871462 4408{
8575a877 4409 int hr,hr2;
4410 // propagate loaded constant flags
cf95b4f0 4411 if(i==0||dops[i].bt)
8575a877 4412 regs[i].loadedconst=0;
4413 else {
4414 for(hr=0;hr<HOST_REGS;hr++) {
4415 if(hr!=EXCLUDE_REG&&regmap[hr]>=0&&((regs[i-1].isconst>>hr)&1)&&pre[hr]==regmap[hr]
4416 &&regmap[hr]==regs[i-1].regmap[hr]&&((regs[i-1].loadedconst>>hr)&1))
4417 {
4418 regs[i].loadedconst|=1<<hr;
4419 }
4420 }
4421 }
57871462 4422 // Load 32-bit regs
4423 for(hr=0;hr<HOST_REGS;hr++) {
4424 if(hr!=EXCLUDE_REG&&regmap[hr]>=0) {
4425 //if(entry[hr]!=regmap[hr]) {
8575a877 4426 if(!((regs[i].loadedconst>>hr)&1)) {
ad49de89 4427 assert(regmap[hr]<64);
4428 if(((regs[i].isconst>>hr)&1)&&regmap[hr]>0) {
8575a877 4429 int value,similar=0;
57871462 4430 if(get_final_value(hr,i,&value)) {
8575a877 4431 // see if some other register has similar value
4432 for(hr2=0;hr2<HOST_REGS;hr2++) {
4433 if(hr2!=EXCLUDE_REG&&((regs[i].loadedconst>>hr2)&1)) {
4434 if(is_similar_value(value,constmap[i][hr2])) {
4435 similar=1;
4436 break;
4437 }
4438 }
4439 }
4440 if(similar) {
4441 int value2;
4442 if(get_final_value(hr2,i,&value2)) // is this needed?
4443 emit_movimm_from(value2,hr2,value,hr);
4444 else
4445 emit_movimm(value,hr);
4446 }
4447 else if(value==0) {
57871462 4448 emit_zeroreg(hr);
4449 }
4450 else {
4451 emit_movimm(value,hr);
4452 }
4453 }
8575a877 4454 regs[i].loadedconst|=1<<hr;
57871462 4455 }
4456 }
4457 }
4458 }
57871462 4459}
ad49de89 4460
2330734f 4461static void load_all_consts(const signed char regmap[], u_int dirty, int i)
57871462 4462{
4463 int hr;
4464 // Load 32-bit regs
4465 for(hr=0;hr<HOST_REGS;hr++) {
4466 if(hr!=EXCLUDE_REG&&regmap[hr]>=0&&((dirty>>hr)&1)) {
ad49de89 4467 assert(regmap[hr] < 64);
4468 if(((regs[i].isconst>>hr)&1)&&regmap[hr]>0) {
57871462 4469 int value=constmap[i][hr];
4470 if(value==0) {
4471 emit_zeroreg(hr);
4472 }
4473 else {
4474 emit_movimm(value,hr);
4475 }
4476 }
4477 }
4478 }
57871462 4479}
4480
4481// Write out all dirty registers (except cycle count)
2330734f 4482static void wb_dirtys(const signed char i_regmap[], uint64_t i_dirty)
57871462 4483{
4484 int hr;
4485 for(hr=0;hr<HOST_REGS;hr++) {
4486 if(hr!=EXCLUDE_REG) {
4487 if(i_regmap[hr]>0) {
4488 if(i_regmap[hr]!=CCREG) {
4489 if((i_dirty>>hr)&1) {
00fa9369 4490 assert(i_regmap[hr]<64);
4491 emit_storereg(i_regmap[hr],hr);
57871462 4492 }
4493 }
4494 }
4495 }
4496 }
4497}
ad49de89 4498
57871462 4499// Write out dirty registers that we need to reload (pair with load_needed_regs)
4500// This writes the registers not written by store_regs_bt
2330734f 4501static void wb_needed_dirtys(const signed char i_regmap[], uint64_t i_dirty, int addr)
57871462 4502{
4503 int hr;
4504 int t=(addr-start)>>2;
4505 for(hr=0;hr<HOST_REGS;hr++) {
4506 if(hr!=EXCLUDE_REG) {
4507 if(i_regmap[hr]>0) {
4508 if(i_regmap[hr]!=CCREG) {
ad49de89 4509 if(i_regmap[hr]==regs[t].regmap_entry[hr] && ((regs[t].dirty>>hr)&1)) {
57871462 4510 if((i_dirty>>hr)&1) {
00fa9369 4511 assert(i_regmap[hr]<64);
4512 emit_storereg(i_regmap[hr],hr);
57871462 4513 }
4514 }
4515 }
4516 }
4517 }
4518 }
4519}
4520
4521// Load all registers (except cycle count)
2330734f 4522static void load_all_regs(const signed char i_regmap[])
57871462 4523{
4524 int hr;
4525 for(hr=0;hr<HOST_REGS;hr++) {
4526 if(hr!=EXCLUDE_REG) {
4527 if(i_regmap[hr]==0) {
4528 emit_zeroreg(hr);
4529 }
4530 else
ea3d2e6e 4531 if(i_regmap[hr]>0 && (i_regmap[hr]&63)<TEMPREG && i_regmap[hr]!=CCREG)
57871462 4532 {
4533 emit_loadreg(i_regmap[hr],hr);
4534 }
4535 }
4536 }
4537}
4538
4539// Load all current registers also needed by next instruction
2330734f 4540static void load_needed_regs(const signed char i_regmap[], const signed char next_regmap[])
57871462 4541{
4542 int hr;
4543 for(hr=0;hr<HOST_REGS;hr++) {
4544 if(hr!=EXCLUDE_REG) {
4545 if(get_reg(next_regmap,i_regmap[hr])>=0) {
4546 if(i_regmap[hr]==0) {
4547 emit_zeroreg(hr);
4548 }
4549 else
ea3d2e6e 4550 if(i_regmap[hr]>0 && (i_regmap[hr]&63)<TEMPREG && i_regmap[hr]!=CCREG)
57871462 4551 {
4552 emit_loadreg(i_regmap[hr],hr);
4553 }
4554 }
4555 }
4556 }
4557}
4558
4559// Load all regs, storing cycle count if necessary
2330734f 4560static void load_regs_entry(int t)
57871462 4561{
4562 int hr;
cf95b4f0 4563 if(dops[t].is_ds) emit_addimm(HOST_CCREG,CLOCK_ADJUST(1),HOST_CCREG);
2330734f 4564 else if(ccadj[t]) emit_addimm(HOST_CCREG,-ccadj[t],HOST_CCREG);
57871462 4565 if(regs[t].regmap_entry[HOST_CCREG]!=CCREG) {
4566 emit_storereg(CCREG,HOST_CCREG);
4567 }
4568 // Load 32-bit regs
4569 for(hr=0;hr<HOST_REGS;hr++) {
ea3d2e6e 4570 if(regs[t].regmap_entry[hr]>=0&&regs[t].regmap_entry[hr]<TEMPREG) {
57871462 4571 if(regs[t].regmap_entry[hr]==0) {
4572 emit_zeroreg(hr);
4573 }
4574 else if(regs[t].regmap_entry[hr]!=CCREG)
4575 {
4576 emit_loadreg(regs[t].regmap_entry[hr],hr);
4577 }
4578 }
4579 }
57871462 4580}
4581
4582// Store dirty registers prior to branch
ad49de89 4583void store_regs_bt(signed char i_regmap[],uint64_t i_dirty,int addr)
57871462 4584{
ad49de89 4585 if(internal_branch(addr))
57871462 4586 {
4587 int t=(addr-start)>>2;
4588 int hr;
4589 for(hr=0;hr<HOST_REGS;hr++) {
4590 if(hr!=EXCLUDE_REG) {
4591 if(i_regmap[hr]>0 && i_regmap[hr]!=CCREG) {
ad49de89 4592 if(i_regmap[hr]!=regs[t].regmap_entry[hr] || !((regs[t].dirty>>hr)&1)) {
57871462 4593 if((i_dirty>>hr)&1) {
00fa9369 4594 assert(i_regmap[hr]<64);
4595 if(!((unneeded_reg[t]>>i_regmap[hr])&1))
4596 emit_storereg(i_regmap[hr],hr);
57871462 4597 }
4598 }
4599 }
4600 }
4601 }
4602 }
4603 else
4604 {
4605 // Branch out of this block, write out all dirty regs
ad49de89 4606 wb_dirtys(i_regmap,i_dirty);
57871462 4607 }
4608}
4609
4610// Load all needed registers for branch target
ad49de89 4611static void load_regs_bt(signed char i_regmap[],uint64_t i_dirty,int addr)
57871462 4612{
4613 //if(addr>=start && addr<(start+slen*4))
ad49de89 4614 if(internal_branch(addr))
57871462 4615 {
4616 int t=(addr-start)>>2;
4617 int hr;
4618 // Store the cycle count before loading something else
4619 if(i_regmap[HOST_CCREG]!=CCREG) {
4620 assert(i_regmap[HOST_CCREG]==-1);
4621 }
4622 if(regs[t].regmap_entry[HOST_CCREG]!=CCREG) {
4623 emit_storereg(CCREG,HOST_CCREG);
4624 }
4625 // Load 32-bit regs
4626 for(hr=0;hr<HOST_REGS;hr++) {
ea3d2e6e 4627 if(hr!=EXCLUDE_REG&&regs[t].regmap_entry[hr]>=0&&regs[t].regmap_entry[hr]<TEMPREG) {
00fa9369 4628 if(i_regmap[hr]!=regs[t].regmap_entry[hr]) {
57871462 4629 if(regs[t].regmap_entry[hr]==0) {
4630 emit_zeroreg(hr);
4631 }
4632 else if(regs[t].regmap_entry[hr]!=CCREG)
4633 {
4634 emit_loadreg(regs[t].regmap_entry[hr],hr);
4635 }
4636 }
4637 }
4638 }
57871462 4639 }
4640}
4641
ad49de89 4642static int match_bt(signed char i_regmap[],uint64_t i_dirty,int addr)
57871462 4643{
4644 if(addr>=start && addr<start+slen*4-4)
4645 {
4646 int t=(addr-start)>>2;
4647 int hr;
4648 if(regs[t].regmap_entry[HOST_CCREG]!=CCREG) return 0;
4649 for(hr=0;hr<HOST_REGS;hr++)
4650 {
4651 if(hr!=EXCLUDE_REG)
4652 {
4653 if(i_regmap[hr]!=regs[t].regmap_entry[hr])
4654 {
ea3d2e6e 4655 if(regs[t].regmap_entry[hr]>=0&&(regs[t].regmap_entry[hr]|64)<TEMPREG+64)
57871462 4656 {
4657 return 0;
4658 }
9f51b4b9 4659 else
57871462 4660 if((i_dirty>>hr)&1)
4661 {
ea3d2e6e 4662 if(i_regmap[hr]<TEMPREG)
57871462 4663 {
4664 if(!((unneeded_reg[t]>>i_regmap[hr])&1))
4665 return 0;
4666 }
ea3d2e6e 4667 else if(i_regmap[hr]>=64&&i_regmap[hr]<TEMPREG+64)
57871462 4668 {
00fa9369 4669 assert(0);
57871462 4670 }
4671 }
4672 }
4673 else // Same register but is it 32-bit or dirty?
4674 if(i_regmap[hr]>=0)
4675 {
4676 if(!((regs[t].dirty>>hr)&1))
4677 {
4678 if((i_dirty>>hr)&1)
4679 {
4680 if(!((unneeded_reg[t]>>i_regmap[hr])&1))
4681 {
4682 //printf("%x: dirty no match\n",addr);
4683 return 0;
4684 }
4685 }
4686 }
57871462 4687 }
4688 }
4689 }
57871462 4690 // Delay slots are not valid branch targets
fe807a8a 4691 //if(t>0&&(dops[t-1].is_jump) return 0;
57871462 4692 // Delay slots require additional processing, so do not match
cf95b4f0 4693 if(dops[t].is_ds) return 0;
57871462 4694 }
4695 else
4696 {
4697 int hr;
4698 for(hr=0;hr<HOST_REGS;hr++)
4699 {
4700 if(hr!=EXCLUDE_REG)
4701 {
4702 if(i_regmap[hr]>=0)
4703 {
4704 if(hr!=HOST_CCREG||i_regmap[hr]!=CCREG)
4705 {
4706 if((i_dirty>>hr)&1)
4707 {
4708 return 0;
4709 }
4710 }
4711 }
4712 }
4713 }
4714 }
4715 return 1;
4716}
4717
dd114d7d 4718#ifdef DRC_DBG
2330734f 4719static void drc_dbg_emit_do_cmp(int i, int ccadj_)
dd114d7d 4720{
4721 extern void do_insn_cmp();
3968e69e 4722 //extern int cycle;
81dbbf4c 4723 u_int hr, reglist = get_host_reglist(regs[i].regmap);
dd114d7d 4724
40fca85b 4725 assem_debug("//do_insn_cmp %08x\n", start+i*4);
dd114d7d 4726 save_regs(reglist);
40fca85b 4727 // write out changed consts to match the interpreter
cf95b4f0 4728 if (i > 0 && !dops[i].bt) {
40fca85b 4729 for (hr = 0; hr < HOST_REGS; hr++) {
2330734f 4730 int reg = regs[i].regmap_entry[hr]; // regs[i-1].regmap[hr];
40fca85b 4731 if (hr == EXCLUDE_REG || reg < 0)
4732 continue;
4733 if (!((regs[i-1].isconst >> hr) & 1))
4734 continue;
4735 if (i > 1 && reg == regs[i-2].regmap[hr] && constmap[i-1][hr] == constmap[i-2][hr])
4736 continue;
4737 emit_movimm(constmap[i-1][hr],0);
4738 emit_storereg(reg, 0);
4739 }
4740 }
dd114d7d 4741 emit_movimm(start+i*4,0);
643aeae3 4742 emit_writeword(0,&pcaddr);
2330734f 4743 int cc = get_reg(regs[i].regmap_entry, CCREG);
4744 if (cc < 0)
4745 emit_loadreg(CCREG, cc = 0);
4746 emit_addimm(cc, ccadj_, 0);
4747 emit_writeword(0, &psxRegs.cycle);
2a014d73 4748 emit_far_call(do_insn_cmp);
643aeae3 4749 //emit_readword(&cycle,0);
dd114d7d 4750 //emit_addimm(0,2,0);
643aeae3 4751 //emit_writeword(0,&cycle);
3968e69e 4752 (void)get_reg2;
dd114d7d 4753 restore_regs(reglist);
40fca85b 4754 assem_debug("\\\\do_insn_cmp\n");
dd114d7d 4755}
4756#else
2330734f 4757#define drc_dbg_emit_do_cmp(x,y)
dd114d7d 4758#endif
4759
57871462 4760// Used when a branch jumps into the delay slot of another branch
7c3a5182 4761static void ds_assemble_entry(int i)
57871462 4762{
2330734f 4763 int t = (ba[i] - start) >> 2;
4764 int ccadj_ = -CLOCK_ADJUST(1);
df4dc2b1 4765 if (!instr_addr[t])
4766 instr_addr[t] = out;
57871462 4767 assem_debug("Assemble delay slot at %x\n",ba[i]);
4768 assem_debug("<->\n");
2330734f 4769 drc_dbg_emit_do_cmp(t, ccadj_);
57871462 4770 if(regs[t].regmap_entry[HOST_CCREG]==CCREG&&regs[t].regmap[HOST_CCREG]!=CCREG)
ad49de89 4771 wb_register(CCREG,regs[t].regmap_entry,regs[t].wasdirty);
cf95b4f0 4772 load_regs(regs[t].regmap_entry,regs[t].regmap,dops[t].rs1,dops[t].rs2);
57871462 4773 address_generation(t,&regs[t],regs[t].regmap_entry);
37387d8b 4774 if (ram_offset && (dops[t].is_load || dops[t].is_store))
4775 load_regs(regs[t].regmap_entry,regs[t].regmap,ROREG,ROREG);
4776 if (dops[t].is_store)
ad49de89 4777 load_regs(regs[t].regmap_entry,regs[t].regmap,INVCP,INVCP);
57871462 4778 is_delayslot=0;
2330734f 4779 switch (dops[t].itype) {
57871462 4780 case SYSCALL:
7139f3c8 4781 case HLECALL:
1e973cb0 4782 case INTCALL:
57871462 4783 case SPAN:
4784 case UJUMP:
4785 case RJUMP:
4786 case CJUMP:
4787 case SJUMP:
c43b5311 4788 SysPrintf("Jump in the delay slot. This is probably a bug.\n");
2330734f 4789 break;
4790 default:
4791 assemble(t, &regs[t], ccadj_);
57871462 4792 }
ad49de89 4793 store_regs_bt(regs[t].regmap,regs[t].dirty,ba[i]+4);
4794 load_regs_bt(regs[t].regmap,regs[t].dirty,ba[i]+4);
4795 if(internal_branch(ba[i]+4))
57871462 4796 assem_debug("branch: internal\n");
4797 else
4798 assem_debug("branch: external\n");
ad49de89 4799 assert(internal_branch(ba[i]+4));
4800 add_to_linker(out,ba[i]+4,internal_branch(ba[i]+4));
57871462 4801 emit_jmp(0);
4802}
4803
7c3a5182 4804static void emit_extjump(void *addr, u_int target)
4805{
4806 emit_extjump2(addr, target, dyna_linker);
4807}
4808
4809static void emit_extjump_ds(void *addr, u_int target)
4810{
4811 emit_extjump2(addr, target, dyna_linker_ds);
4812}
4813
d1e4ebd9 4814// Load 2 immediates optimizing for small code size
4815static void emit_mov2imm_compact(int imm1,u_int rt1,int imm2,u_int rt2)
4816{
4817 emit_movimm(imm1,rt1);
4818 emit_movimm_from(imm1,rt1,imm2,rt2);
4819}
4820
2330734f 4821static void do_cc(int i, const signed char i_regmap[], int *adj,
4822 int addr, int taken, int invert)
57871462 4823{
2330734f 4824 int count, count_plus2;
b14b6a8f 4825 void *jaddr;
4826 void *idle=NULL;
b6e87b2b 4827 int t=0;
cf95b4f0 4828 if(dops[i].itype==RJUMP)
57871462 4829 {
4830 *adj=0;
4831 }
4832 //if(ba[i]>=start && ba[i]<(start+slen*4))
ad49de89 4833 if(internal_branch(ba[i]))
57871462 4834 {
b6e87b2b 4835 t=(ba[i]-start)>>2;
2330734f 4836 if(dops[t].is_ds) *adj=-CLOCK_ADJUST(1); // Branch into delay slot adds an extra cycle
57871462 4837 else *adj=ccadj[t];
4838 }
4839 else
4840 {
4841 *adj=0;
4842 }
2330734f 4843 count = ccadj[i];
4844 count_plus2 = count + CLOCK_ADJUST(2);
57871462 4845 if(taken==TAKEN && i==(ba[i]-start)>>2 && source[i+1]==0) {
4846 // Idle loop
4847 if(count&1) emit_addimm_and_set_flags(2*(count+2),HOST_CCREG);
b14b6a8f 4848 idle=out;
57871462 4849 //emit_subfrommem(&idlecount,HOST_CCREG); // Count idle cycles
4850 emit_andimm(HOST_CCREG,3,HOST_CCREG);
b14b6a8f 4851 jaddr=out;
57871462 4852 emit_jmp(0);
4853 }
4854 else if(*adj==0||invert) {
2330734f 4855 int cycles = count_plus2;
b6e87b2b 4856 // faster loop HACK
bb4f300c 4857#if 0
b6e87b2b 4858 if (t&&*adj) {
4859 int rel=t-i;
4860 if(-NO_CYCLE_PENALTY_THR<rel&&rel<0)
2330734f 4861 cycles=*adj+count+2-*adj;
b6e87b2b 4862 }
bb4f300c 4863#endif
2330734f 4864 emit_addimm_and_set_flags(cycles, HOST_CCREG);
4865 jaddr = out;
57871462 4866 emit_jns(0);
4867 }
4868 else
4869 {
2330734f 4870 emit_cmpimm(HOST_CCREG, -count_plus2);
4871 jaddr = out;
57871462 4872 emit_jns(0);
4873 }
2330734f 4874 add_stub(CC_STUB,jaddr,idle?idle:out,(*adj==0||invert||idle)?0:count_plus2,i,addr,taken,0);
57871462 4875}
4876
b14b6a8f 4877static void do_ccstub(int n)
57871462 4878{
4879 literal_pool(256);
d1e4ebd9 4880 assem_debug("do_ccstub %x\n",start+(u_int)stubs[n].b*4);
b14b6a8f 4881 set_jump_target(stubs[n].addr, out);
4882 int i=stubs[n].b;
4883 if(stubs[n].d==NULLDS) {
57871462 4884 // Delay slot instruction is nullified ("likely" branch)
ad49de89 4885 wb_dirtys(regs[i].regmap,regs[i].dirty);
57871462 4886 }
b14b6a8f 4887 else if(stubs[n].d!=TAKEN) {
ad49de89 4888 wb_dirtys(branch_regs[i].regmap,branch_regs[i].dirty);
57871462 4889 }
4890 else {
ad49de89 4891 if(internal_branch(ba[i]))
4892 wb_needed_dirtys(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]);
57871462 4893 }
b14b6a8f 4894 if(stubs[n].c!=-1)
57871462 4895 {
4896 // Save PC as return address
b14b6a8f 4897 emit_movimm(stubs[n].c,EAX);
643aeae3 4898 emit_writeword(EAX,&pcaddr);
57871462 4899 }
4900 else
4901 {
4902 // Return address depends on which way the branch goes
cf95b4f0 4903 if(dops[i].itype==CJUMP||dops[i].itype==SJUMP)
57871462 4904 {
cf95b4f0 4905 int s1l=get_reg(branch_regs[i].regmap,dops[i].rs1);
4906 int s2l=get_reg(branch_regs[i].regmap,dops[i].rs2);
4907 if(dops[i].rs1==0)
57871462 4908 {
ad49de89 4909 s1l=s2l;
4910 s2l=-1;
57871462 4911 }
cf95b4f0 4912 else if(dops[i].rs2==0)
57871462 4913 {
ad49de89 4914 s2l=-1;
57871462 4915 }
4916 assert(s1l>=0);
4917 #ifdef DESTRUCTIVE_WRITEBACK
cf95b4f0 4918 if(dops[i].rs1) {
ad49de89 4919 if((branch_regs[i].dirty>>s1l)&&1)
cf95b4f0 4920 emit_loadreg(dops[i].rs1,s1l);
9f51b4b9 4921 }
57871462 4922 else {
ad49de89 4923 if((branch_regs[i].dirty>>s1l)&1)
cf95b4f0 4924 emit_loadreg(dops[i].rs2,s1l);
57871462 4925 }
4926 if(s2l>=0)
ad49de89 4927 if((branch_regs[i].dirty>>s2l)&1)
cf95b4f0 4928 emit_loadreg(dops[i].rs2,s2l);
57871462 4929 #endif
4930 int hr=0;
5194fb95 4931 int addr=-1,alt=-1,ntaddr=-1;
57871462 4932 while(hr<HOST_REGS)
4933 {
4934 if(hr!=EXCLUDE_REG && hr!=HOST_CCREG &&
cf95b4f0 4935 (branch_regs[i].regmap[hr]&63)!=dops[i].rs1 &&
4936 (branch_regs[i].regmap[hr]&63)!=dops[i].rs2 )
57871462 4937 {
4938 addr=hr++;break;
4939 }
4940 hr++;
4941 }
4942 while(hr<HOST_REGS)
4943 {
4944 if(hr!=EXCLUDE_REG && hr!=HOST_CCREG &&
cf95b4f0 4945 (branch_regs[i].regmap[hr]&63)!=dops[i].rs1 &&
4946 (branch_regs[i].regmap[hr]&63)!=dops[i].rs2 )
57871462 4947 {
4948 alt=hr++;break;
4949 }
4950 hr++;
4951 }
cf95b4f0 4952 if((dops[i].opcode&0x2E)==6) // BLEZ/BGTZ needs another register
57871462 4953 {
4954 while(hr<HOST_REGS)
4955 {
4956 if(hr!=EXCLUDE_REG && hr!=HOST_CCREG &&
cf95b4f0 4957 (branch_regs[i].regmap[hr]&63)!=dops[i].rs1 &&
4958 (branch_regs[i].regmap[hr]&63)!=dops[i].rs2 )
57871462 4959 {
4960 ntaddr=hr;break;
4961 }
4962 hr++;
4963 }
4964 assert(hr<HOST_REGS);
4965 }
cf95b4f0 4966 if((dops[i].opcode&0x2f)==4) // BEQ
57871462 4967 {
4968 #ifdef HAVE_CMOV_IMM
ad49de89 4969 if(s2l>=0) emit_cmp(s1l,s2l);
4970 else emit_test(s1l,s1l);
4971 emit_cmov2imm_e_ne_compact(ba[i],start+i*4+8,addr);
4972 #else
4973 emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
4974 if(s2l>=0) emit_cmp(s1l,s2l);
4975 else emit_test(s1l,s1l);
4976 emit_cmovne_reg(alt,addr);
57871462 4977 #endif
57871462 4978 }
cf95b4f0 4979 if((dops[i].opcode&0x2f)==5) // BNE
57871462 4980 {
4981 #ifdef HAVE_CMOV_IMM
ad49de89 4982 if(s2l>=0) emit_cmp(s1l,s2l);
4983 else emit_test(s1l,s1l);
4984 emit_cmov2imm_e_ne_compact(start+i*4+8,ba[i],addr);
4985 #else
4986 emit_mov2imm_compact(start+i*4+8,addr,ba[i],alt);
4987 if(s2l>=0) emit_cmp(s1l,s2l);
4988 else emit_test(s1l,s1l);
4989 emit_cmovne_reg(alt,addr);
57871462 4990 #endif
57871462 4991 }
cf95b4f0 4992 if((dops[i].opcode&0x2f)==6) // BLEZ
57871462 4993 {
4994 //emit_movimm(ba[i],alt);
4995 //emit_movimm(start+i*4+8,addr);
4996 emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
4997 emit_cmpimm(s1l,1);
57871462 4998 emit_cmovl_reg(alt,addr);
57871462 4999 }
cf95b4f0 5000 if((dops[i].opcode&0x2f)==7) // BGTZ
57871462 5001 {
5002 //emit_movimm(ba[i],addr);
5003 //emit_movimm(start+i*4+8,ntaddr);
5004 emit_mov2imm_compact(ba[i],addr,start+i*4+8,ntaddr);
5005 emit_cmpimm(s1l,1);
57871462 5006 emit_cmovl_reg(ntaddr,addr);
57871462 5007 }
cf95b4f0 5008 if((dops[i].opcode==1)&&(dops[i].opcode2&0x2D)==0) // BLTZ
57871462 5009 {
5010 //emit_movimm(ba[i],alt);
5011 //emit_movimm(start+i*4+8,addr);
5012 emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
ad49de89 5013 emit_test(s1l,s1l);
57871462 5014 emit_cmovs_reg(alt,addr);
5015 }
cf95b4f0 5016 if((dops[i].opcode==1)&&(dops[i].opcode2&0x2D)==1) // BGEZ
57871462 5017 {
5018 //emit_movimm(ba[i],addr);
5019 //emit_movimm(start+i*4+8,alt);
5020 emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
ad49de89 5021 emit_test(s1l,s1l);
57871462 5022 emit_cmovs_reg(alt,addr);
5023 }
cf95b4f0 5024 if(dops[i].opcode==0x11 && dops[i].opcode2==0x08 ) {
57871462 5025 if(source[i]&0x10000) // BC1T
5026 {
5027 //emit_movimm(ba[i],alt);
5028 //emit_movimm(start+i*4+8,addr);
5029 emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
5030 emit_testimm(s1l,0x800000);
5031 emit_cmovne_reg(alt,addr);
5032 }
5033 else // BC1F
5034 {
5035 //emit_movimm(ba[i],addr);
5036 //emit_movimm(start+i*4+8,alt);
5037 emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
5038 emit_testimm(s1l,0x800000);
5039 emit_cmovne_reg(alt,addr);
5040 }
5041 }
643aeae3 5042 emit_writeword(addr,&pcaddr);
57871462 5043 }
5044 else
cf95b4f0 5045 if(dops[i].itype==RJUMP)
57871462 5046 {
cf95b4f0 5047 int r=get_reg(branch_regs[i].regmap,dops[i].rs1);
4919de1e 5048 if (ds_writes_rjump_rs(i)) {
57871462 5049 r=get_reg(branch_regs[i].regmap,RTEMP);
5050 }
643aeae3 5051 emit_writeword(r,&pcaddr);
57871462 5052 }
7c3a5182 5053 else {SysPrintf("Unknown branch type in do_ccstub\n");abort();}
57871462 5054 }
5055 // Update cycle count
5056 assert(branch_regs[i].regmap[HOST_CCREG]==CCREG||branch_regs[i].regmap[HOST_CCREG]==-1);
2330734f 5057 if(stubs[n].a) emit_addimm(HOST_CCREG,(int)stubs[n].a,HOST_CCREG);
2a014d73 5058 emit_far_call(cc_interrupt);
2330734f 5059 if(stubs[n].a) emit_addimm(HOST_CCREG,-(int)stubs[n].a,HOST_CCREG);
b14b6a8f 5060 if(stubs[n].d==TAKEN) {
ad49de89 5061 if(internal_branch(ba[i]))
57871462 5062 load_needed_regs(branch_regs[i].regmap,regs[(ba[i]-start)>>2].regmap_entry);
cf95b4f0 5063 else if(dops[i].itype==RJUMP) {
57871462 5064 if(get_reg(branch_regs[i].regmap,RTEMP)>=0)
643aeae3 5065 emit_readword(&pcaddr,get_reg(branch_regs[i].regmap,RTEMP));
57871462 5066 else
cf95b4f0 5067 emit_loadreg(dops[i].rs1,get_reg(branch_regs[i].regmap,dops[i].rs1));
57871462 5068 }
b14b6a8f 5069 }else if(stubs[n].d==NOTTAKEN) {
57871462 5070 if(i<slen-2) load_needed_regs(branch_regs[i].regmap,regmap_pre[i+2]);
5071 else load_all_regs(branch_regs[i].regmap);
b14b6a8f 5072 }else if(stubs[n].d==NULLDS) {
57871462 5073 // Delay slot instruction is nullified ("likely" branch)
5074 if(i<slen-2) load_needed_regs(regs[i].regmap,regmap_pre[i+2]);
5075 else load_all_regs(regs[i].regmap);
5076 }else{
5077 load_all_regs(branch_regs[i].regmap);
5078 }
d1e4ebd9 5079 if (stubs[n].retaddr)
5080 emit_jmp(stubs[n].retaddr);
5081 else
5082 do_jump_vaddr(stubs[n].e);
57871462 5083}
5084
643aeae3 5085static void add_to_linker(void *addr, u_int target, int ext)
57871462 5086{
643aeae3 5087 assert(linkcount < ARRAY_SIZE(link_addr));
5088 link_addr[linkcount].addr = addr;
5089 link_addr[linkcount].target = target;
5090 link_addr[linkcount].ext = ext;
57871462 5091 linkcount++;
5092}
5093
eba830cd 5094static void ujump_assemble_write_ra(int i)
5095{
5096 int rt;
5097 unsigned int return_address;
5098 rt=get_reg(branch_regs[i].regmap,31);
5099 assem_debug("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5100 //assert(rt>=0);
5101 return_address=start+i*4+8;
5102 if(rt>=0) {
5103 #ifdef USE_MINI_HT
cf95b4f0 5104 if(internal_branch(return_address)&&dops[i+1].rt1!=31) {
eba830cd 5105 int temp=-1; // note: must be ds-safe
5106 #ifdef HOST_TEMPREG
5107 temp=HOST_TEMPREG;
5108 #endif
5109 if(temp>=0) do_miniht_insert(return_address,rt,temp);
5110 else emit_movimm(return_address,rt);
5111 }
5112 else
5113 #endif
5114 {
5115 #ifdef REG_PREFETCH
9f51b4b9 5116 if(temp>=0)
eba830cd 5117 {
643aeae3 5118 if(i_regmap[temp]!=PTEMP) emit_movimm((uintptr_t)hash_table_get(return_address),temp);
eba830cd 5119 }
5120 #endif
5121 emit_movimm(return_address,rt); // PC into link register
5122 #ifdef IMM_PREFETCH
df4dc2b1 5123 emit_prefetch(hash_table_get(return_address));
eba830cd 5124 #endif
5125 }
5126 }
5127}
5128
2330734f 5129static void ujump_assemble(int i, const struct regstat *i_regs)
57871462 5130{
eba830cd 5131 int ra_done=0;
57871462 5132 if(i==(ba[i]-start)>>2) assem_debug("idle loop\n");
5133 address_generation(i+1,i_regs,regs[i].regmap_entry);
5134 #ifdef REG_PREFETCH
5135 int temp=get_reg(branch_regs[i].regmap,PTEMP);
cf95b4f0 5136 if(dops[i].rt1==31&&temp>=0)
57871462 5137 {
581335b0 5138 signed char *i_regmap=i_regs->regmap;
57871462 5139 int return_address=start+i*4+8;
9f51b4b9 5140 if(get_reg(branch_regs[i].regmap,31)>0)
643aeae3 5141 if(i_regmap[temp]==PTEMP) emit_movimm((uintptr_t)hash_table_get(return_address),temp);
57871462 5142 }
5143 #endif
cf95b4f0 5144 if(dops[i].rt1==31&&(dops[i].rt1==dops[i+1].rs1||dops[i].rt1==dops[i+1].rs2)) {
eba830cd 5145 ujump_assemble_write_ra(i); // writeback ra for DS
5146 ra_done=1;
57871462 5147 }
4ef8f67d 5148 ds_assemble(i+1,i_regs);
5149 uint64_t bc_unneeded=branch_regs[i].u;
cf95b4f0 5150 bc_unneeded|=1|(1LL<<dops[i].rt1);
ad49de89 5151 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,bc_unneeded);
5152 load_regs(regs[i].regmap,branch_regs[i].regmap,CCREG,CCREG);
cf95b4f0 5153 if(!ra_done&&dops[i].rt1==31)
eba830cd 5154 ujump_assemble_write_ra(i);
57871462 5155 int cc,adj;
5156 cc=get_reg(branch_regs[i].regmap,CCREG);
5157 assert(cc==HOST_CCREG);
ad49de89 5158 store_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]);
57871462 5159 #ifdef REG_PREFETCH
cf95b4f0 5160 if(dops[i].rt1==31&&temp>=0) emit_prefetchreg(temp);
57871462 5161 #endif
5162 do_cc(i,branch_regs[i].regmap,&adj,ba[i],TAKEN,0);
2330734f 5163 if(adj) emit_addimm(cc, ccadj[i] + CLOCK_ADJUST(2) - adj, cc);
ad49de89 5164 load_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]);
5165 if(internal_branch(ba[i]))
57871462 5166 assem_debug("branch: internal\n");
5167 else
5168 assem_debug("branch: external\n");
cf95b4f0 5169 if (internal_branch(ba[i]) && dops[(ba[i]-start)>>2].is_ds) {
57871462 5170 ds_assemble_entry(i);
5171 }
5172 else {
ad49de89 5173 add_to_linker(out,ba[i],internal_branch(ba[i]));
57871462 5174 emit_jmp(0);
5175 }
5176}
5177
eba830cd 5178static void rjump_assemble_write_ra(int i)
5179{
5180 int rt,return_address;
cf95b4f0 5181 assert(dops[i+1].rt1!=dops[i].rt1);
5182 assert(dops[i+1].rt2!=dops[i].rt1);
5183 rt=get_reg(branch_regs[i].regmap,dops[i].rt1);
eba830cd 5184 assem_debug("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5185 assert(rt>=0);
5186 return_address=start+i*4+8;
5187 #ifdef REG_PREFETCH
9f51b4b9 5188 if(temp>=0)
eba830cd 5189 {
643aeae3 5190 if(i_regmap[temp]!=PTEMP) emit_movimm((uintptr_t)hash_table_get(return_address),temp);
eba830cd 5191 }
5192 #endif
5193 emit_movimm(return_address,rt); // PC into link register
5194 #ifdef IMM_PREFETCH
df4dc2b1 5195 emit_prefetch(hash_table_get(return_address));
eba830cd 5196 #endif
5197}
5198
2330734f 5199static void rjump_assemble(int i, const struct regstat *i_regs)
57871462 5200{
57871462 5201 int temp;
581335b0 5202 int rs,cc;
eba830cd 5203 int ra_done=0;
cf95b4f0 5204 rs=get_reg(branch_regs[i].regmap,dops[i].rs1);
57871462 5205 assert(rs>=0);
4919de1e 5206 if (ds_writes_rjump_rs(i)) {
57871462 5207 // Delay slot abuse, make a copy of the branch address register
5208 temp=get_reg(branch_regs[i].regmap,RTEMP);
5209 assert(temp>=0);
5210 assert(regs[i].regmap[temp]==RTEMP);
5211 emit_mov(rs,temp);
5212 rs=temp;
5213 }
5214 address_generation(i+1,i_regs,regs[i].regmap_entry);
5215 #ifdef REG_PREFETCH
cf95b4f0 5216 if(dops[i].rt1==31)
57871462 5217 {
5218 if((temp=get_reg(branch_regs[i].regmap,PTEMP))>=0) {
581335b0 5219 signed char *i_regmap=i_regs->regmap;
57871462 5220 int return_address=start+i*4+8;
643aeae3 5221 if(i_regmap[temp]==PTEMP) emit_movimm((uintptr_t)hash_table_get(return_address),temp);
57871462 5222 }
5223 }
5224 #endif
5225 #ifdef USE_MINI_HT
cf95b4f0 5226 if(dops[i].rs1==31) {
57871462 5227 int rh=get_reg(regs[i].regmap,RHASH);
5228 if(rh>=0) do_preload_rhash(rh);
5229 }
5230 #endif
cf95b4f0 5231 if(dops[i].rt1!=0&&(dops[i].rt1==dops[i+1].rs1||dops[i].rt1==dops[i+1].rs2)) {
eba830cd 5232 rjump_assemble_write_ra(i);
5233 ra_done=1;
57871462 5234 }
d5910d5d 5235 ds_assemble(i+1,i_regs);
5236 uint64_t bc_unneeded=branch_regs[i].u;
cf95b4f0 5237 bc_unneeded|=1|(1LL<<dops[i].rt1);
5238 bc_unneeded&=~(1LL<<dops[i].rs1);
ad49de89 5239 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,bc_unneeded);
cf95b4f0 5240 load_regs(regs[i].regmap,branch_regs[i].regmap,dops[i].rs1,CCREG);
5241 if(!ra_done&&dops[i].rt1!=0)
eba830cd 5242 rjump_assemble_write_ra(i);
57871462 5243 cc=get_reg(branch_regs[i].regmap,CCREG);
5244 assert(cc==HOST_CCREG);
581335b0 5245 (void)cc;
57871462 5246 #ifdef USE_MINI_HT
5247 int rh=get_reg(branch_regs[i].regmap,RHASH);
5248 int ht=get_reg(branch_regs[i].regmap,RHTBL);
cf95b4f0 5249 if(dops[i].rs1==31) {
57871462 5250 if(regs[i].regmap[rh]!=RHASH) do_preload_rhash(rh);
5251 do_preload_rhtbl(ht);
5252 do_rhash(rs,rh);
5253 }
5254 #endif
ad49de89 5255 store_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,-1);
57871462 5256 #ifdef DESTRUCTIVE_WRITEBACK
ad49de89 5257 if((branch_regs[i].dirty>>rs)&1) {
cf95b4f0 5258 if(dops[i].rs1!=dops[i+1].rt1&&dops[i].rs1!=dops[i+1].rt2) {
5259 emit_loadreg(dops[i].rs1,rs);
57871462 5260 }
5261 }
5262 #endif
5263 #ifdef REG_PREFETCH
cf95b4f0 5264 if(dops[i].rt1==31&&temp>=0) emit_prefetchreg(temp);
57871462 5265 #endif
5266 #ifdef USE_MINI_HT
cf95b4f0 5267 if(dops[i].rs1==31) {
57871462 5268 do_miniht_load(ht,rh);
5269 }
5270 #endif
5271 //do_cc(i,branch_regs[i].regmap,&adj,-1,TAKEN);
5272 //if(adj) emit_addimm(cc,2*(ccadj[i]+2-adj),cc); // ??? - Shouldn't happen
5273 //assert(adj==0);
2330734f 5274 emit_addimm_and_set_flags(ccadj[i] + CLOCK_ADJUST(2), HOST_CCREG);
d1e4ebd9 5275 add_stub(CC_STUB,out,NULL,0,i,-1,TAKEN,rs);
cf95b4f0 5276 if(dops[i+1].itype==COP0&&(source[i+1]&0x3f)==0x10)
911f2d55 5277 // special case for RFE
5278 emit_jmp(0);
5279 else
71e490c5 5280 emit_jns(0);
ad49de89 5281 //load_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,-1);
57871462 5282 #ifdef USE_MINI_HT
cf95b4f0 5283 if(dops[i].rs1==31) {
57871462 5284 do_miniht_jump(rs,rh,ht);
5285 }
5286 else
5287 #endif
5288 {
d1e4ebd9 5289 do_jump_vaddr(rs);
57871462 5290 }
57871462 5291 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
cf95b4f0 5292 if(dops[i].rt1!=31&&i<slen-2&&(((u_int)out)&7)) emit_mov(13,13);
57871462 5293 #endif
5294}
5295
2330734f 5296static void cjump_assemble(int i, const struct regstat *i_regs)
57871462 5297{
2330734f 5298 const signed char *i_regmap = i_regs->regmap;
57871462 5299 int cc;
5300 int match;
ad49de89 5301 match=match_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]);
57871462 5302 assem_debug("match=%d\n",match);
ad49de89 5303 int s1l,s2l;
57871462 5304 int unconditional=0,nop=0;
57871462 5305 int invert=0;
ad49de89 5306 int internal=internal_branch(ba[i]);
57871462 5307 if(i==(ba[i]-start)>>2) assem_debug("idle loop\n");
57871462 5308 if(!match) invert=1;
5309 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5310 if(i>(ba[i]-start)>>2) invert=1;
5311 #endif
3968e69e 5312 #ifdef __aarch64__
5313 invert=1; // because of near cond. branches
5314 #endif
9f51b4b9 5315
cf95b4f0 5316 if(dops[i].ooo) {
5317 s1l=get_reg(branch_regs[i].regmap,dops[i].rs1);
5318 s2l=get_reg(branch_regs[i].regmap,dops[i].rs2);
57871462 5319 }
5320 else {
cf95b4f0 5321 s1l=get_reg(i_regmap,dops[i].rs1);
5322 s2l=get_reg(i_regmap,dops[i].rs2);
57871462 5323 }
cf95b4f0 5324 if(dops[i].rs1==0&&dops[i].rs2==0)
57871462 5325 {
cf95b4f0 5326 if(dops[i].opcode&1) nop=1;
57871462 5327 else unconditional=1;
cf95b4f0 5328 //assert(dops[i].opcode!=5);
5329 //assert(dops[i].opcode!=7);
5330 //assert(dops[i].opcode!=0x15);
5331 //assert(dops[i].opcode!=0x17);
57871462 5332 }
cf95b4f0 5333 else if(dops[i].rs1==0)
57871462 5334 {
ad49de89 5335 s1l=s2l;
5336 s2l=-1;
57871462 5337 }
cf95b4f0 5338 else if(dops[i].rs2==0)
57871462 5339 {
ad49de89 5340 s2l=-1;
57871462 5341 }
5342
cf95b4f0 5343 if(dops[i].ooo) {
57871462 5344 // Out of order execution (delay slot first)
5345 //printf("OOOE\n");
5346 address_generation(i+1,i_regs,regs[i].regmap_entry);
5347 ds_assemble(i+1,i_regs);
5348 int adj;
5349 uint64_t bc_unneeded=branch_regs[i].u;
cf95b4f0 5350 bc_unneeded&=~((1LL<<dops[i].rs1)|(1LL<<dops[i].rs2));
57871462 5351 bc_unneeded|=1;
ad49de89 5352 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,bc_unneeded);
cf95b4f0 5353 load_regs(regs[i].regmap,branch_regs[i].regmap,dops[i].rs1,dops[i].rs2);
ad49de89 5354 load_regs(regs[i].regmap,branch_regs[i].regmap,CCREG,CCREG);
57871462 5355 cc=get_reg(branch_regs[i].regmap,CCREG);
5356 assert(cc==HOST_CCREG);
9f51b4b9 5357 if(unconditional)
ad49de89 5358 store_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]);
57871462 5359 //do_cc(i,branch_regs[i].regmap,&adj,unconditional?ba[i]:-1,unconditional);
5360 //assem_debug("cycle count (adj)\n");
5361 if(unconditional) {
5362 do_cc(i,branch_regs[i].regmap,&adj,ba[i],TAKEN,0);
5363 if(i!=(ba[i]-start)>>2 || source[i+1]!=0) {
2330734f 5364 if(adj) emit_addimm(cc, ccadj[i] + CLOCK_ADJUST(2) - adj, cc);
ad49de89 5365 load_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]);
57871462 5366 if(internal)
5367 assem_debug("branch: internal\n");
5368 else
5369 assem_debug("branch: external\n");
cf95b4f0 5370 if (internal && dops[(ba[i]-start)>>2].is_ds) {
57871462 5371 ds_assemble_entry(i);
5372 }
5373 else {
643aeae3 5374 add_to_linker(out,ba[i],internal);
57871462 5375 emit_jmp(0);
5376 }
5377 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5378 if(((u_int)out)&7) emit_addnop(0);
5379 #endif
5380 }
5381 }
5382 else if(nop) {
2330734f 5383 emit_addimm_and_set_flags(ccadj[i] + CLOCK_ADJUST(2), cc);
b14b6a8f 5384 void *jaddr=out;
57871462 5385 emit_jns(0);
b14b6a8f 5386 add_stub(CC_STUB,jaddr,out,0,i,start+i*4+8,NOTTAKEN,0);
57871462 5387 }
5388 else {
df4dc2b1 5389 void *taken = NULL, *nottaken = NULL, *nottaken1 = NULL;
57871462 5390 do_cc(i,branch_regs[i].regmap,&adj,-1,0,invert);
2330734f 5391 if(adj&&!invert) emit_addimm(cc, ccadj[i] + CLOCK_ADJUST(2) - adj, cc);
9f51b4b9 5392
57871462 5393 //printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5394 assert(s1l>=0);
cf95b4f0 5395 if(dops[i].opcode==4) // BEQ
57871462 5396 {
5397 if(s2l>=0) emit_cmp(s1l,s2l);
5398 else emit_test(s1l,s1l);
5399 if(invert){
df4dc2b1 5400 nottaken=out;
7c3a5182 5401 emit_jne(DJT_1);
57871462 5402 }else{
643aeae3 5403 add_to_linker(out,ba[i],internal);
57871462 5404 emit_jeq(0);
5405 }
5406 }
cf95b4f0 5407 if(dops[i].opcode==5) // BNE
57871462 5408 {
5409 if(s2l>=0) emit_cmp(s1l,s2l);
5410 else emit_test(s1l,s1l);
5411 if(invert){
df4dc2b1 5412 nottaken=out;
7c3a5182 5413 emit_jeq(DJT_1);
57871462 5414 }else{
643aeae3 5415 add_to_linker(out,ba[i],internal);
57871462 5416 emit_jne(0);
5417 }
5418 }
cf95b4f0 5419 if(dops[i].opcode==6) // BLEZ
57871462 5420 {
5421 emit_cmpimm(s1l,1);
5422 if(invert){
df4dc2b1 5423 nottaken=out;
7c3a5182 5424 emit_jge(DJT_1);
57871462 5425 }else{
643aeae3 5426 add_to_linker(out,ba[i],internal);
57871462 5427 emit_jl(0);
5428 }
5429 }
cf95b4f0 5430 if(dops[i].opcode==7) // BGTZ
57871462 5431 {
5432 emit_cmpimm(s1l,1);
5433 if(invert){
df4dc2b1 5434 nottaken=out;
7c3a5182 5435 emit_jl(DJT_1);
57871462 5436 }else{
643aeae3 5437 add_to_linker(out,ba[i],internal);
57871462 5438 emit_jge(0);
5439 }
5440 }
5441 if(invert) {
df4dc2b1 5442 if(taken) set_jump_target(taken, out);
57871462 5443 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
cf95b4f0 5444 if (match && (!internal || !dops[(ba[i]-start)>>2].is_ds)) {
57871462 5445 if(adj) {
2330734f 5446 emit_addimm(cc,-adj,cc);
643aeae3 5447 add_to_linker(out,ba[i],internal);
57871462 5448 }else{
5449 emit_addnop(13);
643aeae3 5450 add_to_linker(out,ba[i],internal*2);
57871462 5451 }
5452 emit_jmp(0);
5453 }else
5454 #endif
5455 {
2330734f 5456 if(adj) emit_addimm(cc,-adj,cc);
ad49de89 5457 store_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]);
5458 load_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]);
57871462 5459 if(internal)
5460 assem_debug("branch: internal\n");
5461 else
5462 assem_debug("branch: external\n");
cf95b4f0 5463 if (internal && dops[(ba[i] - start) >> 2].is_ds) {
57871462 5464 ds_assemble_entry(i);
5465 }
5466 else {
643aeae3 5467 add_to_linker(out,ba[i],internal);
57871462 5468 emit_jmp(0);
5469 }
5470 }
df4dc2b1 5471 set_jump_target(nottaken, out);
57871462 5472 }
5473
df4dc2b1 5474 if(nottaken1) set_jump_target(nottaken1, out);
57871462 5475 if(adj) {
2330734f 5476 if(!invert) emit_addimm(cc,adj,cc);
57871462 5477 }
5478 } // (!unconditional)
5479 } // if(ooo)
5480 else
5481 {
5482 // In-order execution (branch first)
df4dc2b1 5483 void *taken = NULL, *nottaken = NULL, *nottaken1 = NULL;
57871462 5484 if(!unconditional&&!nop) {
57871462 5485 //printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5486 assert(s1l>=0);
cf95b4f0 5487 if((dops[i].opcode&0x2f)==4) // BEQ
57871462 5488 {
5489 if(s2l>=0) emit_cmp(s1l,s2l);
5490 else emit_test(s1l,s1l);
df4dc2b1 5491 nottaken=out;
7c3a5182 5492 emit_jne(DJT_2);
57871462 5493 }
cf95b4f0 5494 if((dops[i].opcode&0x2f)==5) // BNE
57871462 5495 {
5496 if(s2l>=0) emit_cmp(s1l,s2l);
5497 else emit_test(s1l,s1l);
df4dc2b1 5498 nottaken=out;
7c3a5182 5499 emit_jeq(DJT_2);
57871462 5500 }
cf95b4f0 5501 if((dops[i].opcode&0x2f)==6) // BLEZ
57871462 5502 {
5503 emit_cmpimm(s1l,1);
df4dc2b1 5504 nottaken=out;
7c3a5182 5505 emit_jge(DJT_2);
57871462 5506 }
cf95b4f0 5507 if((dops[i].opcode&0x2f)==7) // BGTZ
57871462 5508 {
5509 emit_cmpimm(s1l,1);
df4dc2b1 5510 nottaken=out;
7c3a5182 5511 emit_jl(DJT_2);
57871462 5512 }
5513 } // if(!unconditional)
5514 int adj;
5515 uint64_t ds_unneeded=branch_regs[i].u;
cf95b4f0 5516 ds_unneeded&=~((1LL<<dops[i+1].rs1)|(1LL<<dops[i+1].rs2));
57871462 5517 ds_unneeded|=1;
57871462 5518 // branch taken
5519 if(!nop) {
df4dc2b1 5520 if(taken) set_jump_target(taken, out);
57871462 5521 assem_debug("1:\n");
ad49de89 5522 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,ds_unneeded);
57871462 5523 // load regs
cf95b4f0 5524 load_regs(regs[i].regmap,branch_regs[i].regmap,dops[i+1].rs1,dops[i+1].rs2);
57871462 5525 address_generation(i+1,&branch_regs[i],0);
37387d8b 5526 if (ram_offset)
5527 load_regs(regs[i].regmap,branch_regs[i].regmap,ROREG,ROREG);
ad49de89 5528 load_regs(regs[i].regmap,branch_regs[i].regmap,CCREG,INVCP);
57871462 5529 ds_assemble(i+1,&branch_regs[i]);
5530 cc=get_reg(branch_regs[i].regmap,CCREG);
5531 if(cc==-1) {
5532 emit_loadreg(CCREG,cc=HOST_CCREG);
5533 // CHECK: Is the following instruction (fall thru) allocated ok?
5534 }
5535 assert(cc==HOST_CCREG);
ad49de89 5536 store_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]);
57871462 5537 do_cc(i,i_regmap,&adj,ba[i],TAKEN,0);
5538 assem_debug("cycle count (adj)\n");
2330734f 5539 if(adj) emit_addimm(cc, ccadj[i] + CLOCK_ADJUST(2) - adj, cc);
ad49de89 5540 load_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]);
57871462 5541 if(internal)
5542 assem_debug("branch: internal\n");
5543 else
5544 assem_debug("branch: external\n");
cf95b4f0 5545 if (internal && dops[(ba[i] - start) >> 2].is_ds) {
57871462 5546 ds_assemble_entry(i);
5547 }
5548 else {
643aeae3 5549 add_to_linker(out,ba[i],internal);
57871462 5550 emit_jmp(0);
5551 }
5552 }
5553 // branch not taken
57871462 5554 if(!unconditional) {
df4dc2b1 5555 if(nottaken1) set_jump_target(nottaken1, out);
5556 set_jump_target(nottaken, out);
57871462 5557 assem_debug("2:\n");
fe807a8a 5558 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,ds_unneeded);
37387d8b 5559 // load regs
fe807a8a 5560 load_regs(regs[i].regmap,branch_regs[i].regmap,dops[i+1].rs1,dops[i+1].rs2);
5561 address_generation(i+1,&branch_regs[i],0);
37387d8b 5562 if (ram_offset)
5563 load_regs(regs[i].regmap,branch_regs[i].regmap,ROREG,ROREG);
5564 load_regs(regs[i].regmap,branch_regs[i].regmap,CCREG,INVCP);
fe807a8a 5565 ds_assemble(i+1,&branch_regs[i]);
57871462 5566 cc=get_reg(branch_regs[i].regmap,CCREG);
fe807a8a 5567 if (cc == -1) {
57871462 5568 // Cycle count isn't in a register, temporarily load it then write it out
5569 emit_loadreg(CCREG,HOST_CCREG);
2330734f 5570 emit_addimm_and_set_flags(ccadj[i] + CLOCK_ADJUST(2), HOST_CCREG);
b14b6a8f 5571 void *jaddr=out;
57871462 5572 emit_jns(0);
b14b6a8f 5573 add_stub(CC_STUB,jaddr,out,0,i,start+i*4+8,NOTTAKEN,0);
57871462 5574 emit_storereg(CCREG,HOST_CCREG);
5575 }
5576 else{
5577 cc=get_reg(i_regmap,CCREG);
5578 assert(cc==HOST_CCREG);
2330734f 5579 emit_addimm_and_set_flags(ccadj[i] + CLOCK_ADJUST(2), cc);
b14b6a8f 5580 void *jaddr=out;
57871462 5581 emit_jns(0);
fe807a8a 5582 add_stub(CC_STUB,jaddr,out,0,i,start+i*4+8,NOTTAKEN,0);
57871462 5583 }
5584 }
5585 }
5586}
5587
2330734f 5588static void sjump_assemble(int i, const struct regstat *i_regs)
57871462 5589{
2330734f 5590 const signed char *i_regmap = i_regs->regmap;
57871462 5591 int cc;
5592 int match;
ad49de89 5593 match=match_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]);
57871462 5594 assem_debug("smatch=%d\n",match);
ad49de89 5595 int s1l;
57871462 5596 int unconditional=0,nevertaken=0;
57871462 5597 int invert=0;
ad49de89 5598 int internal=internal_branch(ba[i]);
57871462 5599 if(i==(ba[i]-start)>>2) assem_debug("idle loop\n");
57871462 5600 if(!match) invert=1;
5601 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5602 if(i>(ba[i]-start)>>2) invert=1;
5603 #endif
3968e69e 5604 #ifdef __aarch64__
5605 invert=1; // because of near cond. branches
5606 #endif
57871462 5607
cf95b4f0 5608 //if(dops[i].opcode2>=0x10) return; // FIXME (BxxZAL)
5609 //assert(dops[i].opcode2<0x10||dops[i].rs1==0); // FIXME (BxxZAL)
57871462 5610
cf95b4f0 5611 if(dops[i].ooo) {
5612 s1l=get_reg(branch_regs[i].regmap,dops[i].rs1);
57871462 5613 }
5614 else {
cf95b4f0 5615 s1l=get_reg(i_regmap,dops[i].rs1);
57871462 5616 }
cf95b4f0 5617 if(dops[i].rs1==0)
57871462 5618 {
cf95b4f0 5619 if(dops[i].opcode2&1) unconditional=1;
57871462 5620 else nevertaken=1;
5621 // These are never taken (r0 is never less than zero)
cf95b4f0 5622 //assert(dops[i].opcode2!=0);
5623 //assert(dops[i].opcode2!=2);
5624 //assert(dops[i].opcode2!=0x10);
5625 //assert(dops[i].opcode2!=0x12);
57871462 5626 }
57871462 5627
cf95b4f0 5628 if(dops[i].ooo) {
57871462 5629 // Out of order execution (delay slot first)
5630 //printf("OOOE\n");
5631 address_generation(i+1,i_regs,regs[i].regmap_entry);
5632 ds_assemble(i+1,i_regs);
5633 int adj;
5634 uint64_t bc_unneeded=branch_regs[i].u;
cf95b4f0 5635 bc_unneeded&=~((1LL<<dops[i].rs1)|(1LL<<dops[i].rs2));
57871462 5636 bc_unneeded|=1;
ad49de89 5637 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,bc_unneeded);
cf95b4f0 5638 load_regs(regs[i].regmap,branch_regs[i].regmap,dops[i].rs1,dops[i].rs1);
ad49de89 5639 load_regs(regs[i].regmap,branch_regs[i].regmap,CCREG,CCREG);
cf95b4f0 5640 if(dops[i].rt1==31) {
57871462 5641 int rt,return_address;
57871462 5642 rt=get_reg(branch_regs[i].regmap,31);
5643 assem_debug("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5644 if(rt>=0) {
5645 // Save the PC even if the branch is not taken
5646 return_address=start+i*4+8;
5647 emit_movimm(return_address,rt); // PC into link register
5648 #ifdef IMM_PREFETCH
df4dc2b1 5649 if(!nevertaken) emit_prefetch(hash_table_get(return_address));
57871462 5650 #endif
5651 }
5652 }
5653 cc=get_reg(branch_regs[i].regmap,CCREG);
5654 assert(cc==HOST_CCREG);
9f51b4b9 5655 if(unconditional)
ad49de89 5656 store_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]);
57871462 5657 //do_cc(i,branch_regs[i].regmap,&adj,unconditional?ba[i]:-1,unconditional);
5658 assem_debug("cycle count (adj)\n");
5659 if(unconditional) {
5660 do_cc(i,branch_regs[i].regmap,&adj,ba[i],TAKEN,0);
5661 if(i!=(ba[i]-start)>>2 || source[i+1]!=0) {
2330734f 5662 if(adj) emit_addimm(cc, ccadj[i] + CLOCK_ADJUST(2) - adj, cc);
ad49de89 5663 load_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]);
57871462 5664 if(internal)
5665 assem_debug("branch: internal\n");
5666 else
5667 assem_debug("branch: external\n");
cf95b4f0 5668 if (internal && dops[(ba[i] - start) >> 2].is_ds) {
57871462 5669 ds_assemble_entry(i);
5670 }
5671 else {
643aeae3 5672 add_to_linker(out,ba[i],internal);
57871462 5673 emit_jmp(0);
5674 }
5675 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5676 if(((u_int)out)&7) emit_addnop(0);
5677 #endif
5678 }
5679 }
5680 else if(nevertaken) {
2330734f 5681 emit_addimm_and_set_flags(ccadj[i] + CLOCK_ADJUST(2), cc);
b14b6a8f 5682 void *jaddr=out;
57871462 5683 emit_jns(0);
b14b6a8f 5684 add_stub(CC_STUB,jaddr,out,0,i,start+i*4+8,NOTTAKEN,0);
57871462 5685 }
5686 else {
df4dc2b1 5687 void *nottaken = NULL;
57871462 5688 do_cc(i,branch_regs[i].regmap,&adj,-1,0,invert);
2330734f 5689 if(adj&&!invert) emit_addimm(cc, ccadj[i] + CLOCK_ADJUST(2) - adj, cc);
57871462 5690 {
5691 assert(s1l>=0);
cf95b4f0 5692 if((dops[i].opcode2&0xf)==0) // BLTZ/BLTZAL
57871462 5693 {
5694 emit_test(s1l,s1l);
5695 if(invert){
df4dc2b1 5696 nottaken=out;
7c3a5182 5697 emit_jns(DJT_1);
57871462 5698 }else{
643aeae3 5699 add_to_linker(out,ba[i],internal);
57871462 5700 emit_js(0);
5701 }
5702 }
cf95b4f0 5703 if((dops[i].opcode2&0xf)==1) // BGEZ/BLTZAL
57871462 5704 {
5705 emit_test(s1l,s1l);
5706 if(invert){
df4dc2b1 5707 nottaken=out;
7c3a5182 5708 emit_js(DJT_1);
57871462 5709 }else{
643aeae3 5710 add_to_linker(out,ba[i],internal);
57871462 5711 emit_jns(0);
5712 }
5713 }
ad49de89 5714 }
9f51b4b9 5715
57871462 5716 if(invert) {
5717 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
cf95b4f0 5718 if (match && (!internal || !dops[(ba[i] - start) >> 2].is_ds)) {
57871462 5719 if(adj) {
2330734f 5720 emit_addimm(cc,-adj,cc);
643aeae3 5721 add_to_linker(out,ba[i],internal);
57871462 5722 }else{
5723 emit_addnop(13);
643aeae3 5724 add_to_linker(out,ba[i],internal*2);
57871462 5725 }
5726 emit_jmp(0);
5727 }else
5728 #endif
5729 {
2330734f 5730 if(adj) emit_addimm(cc,-adj,cc);
ad49de89 5731 store_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]);
5732 load_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]);
57871462 5733 if(internal)
5734 assem_debug("branch: internal\n");
5735 else
5736 assem_debug("branch: external\n");
cf95b4f0 5737 if (internal && dops[(ba[i] - start) >> 2].is_ds) {
57871462 5738 ds_assemble_entry(i);
5739 }
5740 else {
643aeae3 5741 add_to_linker(out,ba[i],internal);
57871462 5742 emit_jmp(0);
5743 }
5744 }
df4dc2b1 5745 set_jump_target(nottaken, out);
57871462 5746 }
5747
5748 if(adj) {
2330734f 5749 if(!invert) emit_addimm(cc,adj,cc);
57871462 5750 }
5751 } // (!unconditional)
5752 } // if(ooo)
5753 else
5754 {
5755 // In-order execution (branch first)
5756 //printf("IOE\n");
df4dc2b1 5757 void *nottaken = NULL;
cf95b4f0 5758 if(dops[i].rt1==31) {
a6491170 5759 int rt,return_address;
a6491170 5760 rt=get_reg(branch_regs[i].regmap,31);
5761 if(rt>=0) {
5762 // Save the PC even if the branch is not taken
5763 return_address=start+i*4+8;
5764 emit_movimm(return_address,rt); // PC into link register
5765 #ifdef IMM_PREFETCH
df4dc2b1 5766 emit_prefetch(hash_table_get(return_address));
a6491170 5767 #endif
5768 }
5769 }
57871462 5770 if(!unconditional) {
5771 //printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
57871462 5772 assert(s1l>=0);
cf95b4f0 5773 if((dops[i].opcode2&0x0d)==0) // BLTZ/BLTZL/BLTZAL/BLTZALL
57871462 5774 {
5775 emit_test(s1l,s1l);
df4dc2b1 5776 nottaken=out;
7c3a5182 5777 emit_jns(DJT_1);
57871462 5778 }
cf95b4f0 5779 if((dops[i].opcode2&0x0d)==1) // BGEZ/BGEZL/BGEZAL/BGEZALL
57871462 5780 {
5781 emit_test(s1l,s1l);
df4dc2b1 5782 nottaken=out;
7c3a5182 5783 emit_js(DJT_1);
57871462 5784 }
57871462 5785 } // if(!unconditional)
5786 int adj;
5787 uint64_t ds_unneeded=branch_regs[i].u;
cf95b4f0 5788 ds_unneeded&=~((1LL<<dops[i+1].rs1)|(1LL<<dops[i+1].rs2));
57871462 5789 ds_unneeded|=1;
57871462 5790 // branch taken
5791 if(!nevertaken) {
5792 //assem_debug("1:\n");
ad49de89 5793 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,ds_unneeded);
57871462 5794 // load regs
cf95b4f0 5795 load_regs(regs[i].regmap,branch_regs[i].regmap,dops[i+1].rs1,dops[i+1].rs2);
57871462 5796 address_generation(i+1,&branch_regs[i],0);
37387d8b 5797 if (ram_offset)
5798 load_regs(regs[i].regmap,branch_regs[i].regmap,ROREG,ROREG);
ad49de89 5799 load_regs(regs[i].regmap,branch_regs[i].regmap,CCREG,INVCP);
57871462 5800 ds_assemble(i+1,&branch_regs[i]);
5801 cc=get_reg(branch_regs[i].regmap,CCREG);
5802 if(cc==-1) {
5803 emit_loadreg(CCREG,cc=HOST_CCREG);
5804 // CHECK: Is the following instruction (fall thru) allocated ok?
5805 }
5806 assert(cc==HOST_CCREG);
ad49de89 5807 store_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]);
57871462 5808 do_cc(i,i_regmap,&adj,ba[i],TAKEN,0);
5809 assem_debug("cycle count (adj)\n");
2330734f 5810 if(adj) emit_addimm(cc, ccadj[i] + CLOCK_ADJUST(2) - adj, cc);
ad49de89 5811 load_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]);
57871462 5812 if(internal)
5813 assem_debug("branch: internal\n");
5814 else
5815 assem_debug("branch: external\n");
cf95b4f0 5816 if (internal && dops[(ba[i] - start) >> 2].is_ds) {
57871462 5817 ds_assemble_entry(i);
5818 }
5819 else {
643aeae3 5820 add_to_linker(out,ba[i],internal);
57871462 5821 emit_jmp(0);
5822 }
5823 }
5824 // branch not taken
57871462 5825 if(!unconditional) {
df4dc2b1 5826 set_jump_target(nottaken, out);
57871462 5827 assem_debug("1:\n");
fe807a8a 5828 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,ds_unneeded);
5829 load_regs(regs[i].regmap,branch_regs[i].regmap,dops[i+1].rs1,dops[i+1].rs2);
5830 address_generation(i+1,&branch_regs[i],0);
5831 load_regs(regs[i].regmap,branch_regs[i].regmap,CCREG,CCREG);
5832 ds_assemble(i+1,&branch_regs[i]);
57871462 5833 cc=get_reg(branch_regs[i].regmap,CCREG);
fe807a8a 5834 if (cc == -1) {
57871462 5835 // Cycle count isn't in a register, temporarily load it then write it out
5836 emit_loadreg(CCREG,HOST_CCREG);
2330734f 5837 emit_addimm_and_set_flags(ccadj[i] + CLOCK_ADJUST(2), HOST_CCREG);
b14b6a8f 5838 void *jaddr=out;
57871462 5839 emit_jns(0);
b14b6a8f 5840 add_stub(CC_STUB,jaddr,out,0,i,start+i*4+8,NOTTAKEN,0);
57871462 5841 emit_storereg(CCREG,HOST_CCREG);
5842 }
5843 else{
5844 cc=get_reg(i_regmap,CCREG);
5845 assert(cc==HOST_CCREG);
2330734f 5846 emit_addimm_and_set_flags(ccadj[i] + CLOCK_ADJUST(2), cc);
b14b6a8f 5847 void *jaddr=out;
57871462 5848 emit_jns(0);
fe807a8a 5849 add_stub(CC_STUB,jaddr,out,0,i,start+i*4+8,NOTTAKEN,0);
57871462 5850 }
5851 }
5852 }
5853}
5854
2330734f 5855static void pagespan_assemble(int i, const struct regstat *i_regs)
57871462 5856{
cf95b4f0 5857 int s1l=get_reg(i_regs->regmap,dops[i].rs1);
5858 int s2l=get_reg(i_regs->regmap,dops[i].rs2);
df4dc2b1 5859 void *taken = NULL;
5860 void *nottaken = NULL;
57871462 5861 int unconditional=0;
cf95b4f0 5862 if(dops[i].rs1==0)
57871462 5863 {
ad49de89 5864 s1l=s2l;
5865 s2l=-1;
57871462 5866 }
cf95b4f0 5867 else if(dops[i].rs2==0)
57871462 5868 {
ad49de89 5869 s2l=-1;
57871462 5870 }
5871 int hr=0;
581335b0 5872 int addr=-1,alt=-1,ntaddr=-1;
57871462 5873 if(i_regs->regmap[HOST_BTREG]<0) {addr=HOST_BTREG;}
5874 else {
5875 while(hr<HOST_REGS)
5876 {
5877 if(hr!=EXCLUDE_REG && hr!=HOST_CCREG &&
cf95b4f0 5878 (i_regs->regmap[hr]&63)!=dops[i].rs1 &&
5879 (i_regs->regmap[hr]&63)!=dops[i].rs2 )
57871462 5880 {
5881 addr=hr++;break;
5882 }
5883 hr++;
5884 }
5885 }
5886 while(hr<HOST_REGS)
5887 {
5888 if(hr!=EXCLUDE_REG && hr!=HOST_CCREG && hr!=HOST_BTREG &&
cf95b4f0 5889 (i_regs->regmap[hr]&63)!=dops[i].rs1 &&
5890 (i_regs->regmap[hr]&63)!=dops[i].rs2 )
57871462 5891 {
5892 alt=hr++;break;
5893 }
5894 hr++;
5895 }
cf95b4f0 5896 if((dops[i].opcode&0x2E)==6) // BLEZ/BGTZ needs another register
57871462 5897 {
5898 while(hr<HOST_REGS)
5899 {
5900 if(hr!=EXCLUDE_REG && hr!=HOST_CCREG && hr!=HOST_BTREG &&
cf95b4f0 5901 (i_regs->regmap[hr]&63)!=dops[i].rs1 &&
5902 (i_regs->regmap[hr]&63)!=dops[i].rs2 )
57871462 5903 {
5904 ntaddr=hr;break;
5905 }
5906 hr++;
5907 }
5908 }
5909 assert(hr<HOST_REGS);
cf95b4f0 5910 if((dops[i].opcode&0x2e)==4||dops[i].opcode==0x11) { // BEQ/BNE/BEQL/BNEL/BC1
ad49de89 5911 load_regs(regs[i].regmap_entry,regs[i].regmap,CCREG,CCREG);
57871462 5912 }
2330734f 5913 emit_addimm(HOST_CCREG, ccadj[i] + CLOCK_ADJUST(2), HOST_CCREG);
cf95b4f0 5914 if(dops[i].opcode==2) // J
57871462 5915 {
5916 unconditional=1;
5917 }
cf95b4f0 5918 if(dops[i].opcode==3) // JAL
57871462 5919 {
5920 // TODO: mini_ht
5921 int rt=get_reg(i_regs->regmap,31);
5922 emit_movimm(start+i*4+8,rt);
5923 unconditional=1;
5924 }
cf95b4f0 5925 if(dops[i].opcode==0&&(dops[i].opcode2&0x3E)==8) // JR/JALR
57871462 5926 {
5927 emit_mov(s1l,addr);
cf95b4f0 5928 if(dops[i].opcode2==9) // JALR
57871462 5929 {
cf95b4f0 5930 int rt=get_reg(i_regs->regmap,dops[i].rt1);
57871462 5931 emit_movimm(start+i*4+8,rt);
5932 }
5933 }
cf95b4f0 5934 if((dops[i].opcode&0x3f)==4) // BEQ
57871462 5935 {
cf95b4f0 5936 if(dops[i].rs1==dops[i].rs2)
57871462 5937 {
5938 unconditional=1;
5939 }
5940 else
5941 #ifdef HAVE_CMOV_IMM
ad49de89 5942 if(1) {
57871462 5943 if(s2l>=0) emit_cmp(s1l,s2l);
5944 else emit_test(s1l,s1l);
5945 emit_cmov2imm_e_ne_compact(ba[i],start+i*4+8,addr);
5946 }
5947 else
5948 #endif
5949 {
5950 assert(s1l>=0);
5951 emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
57871462 5952 if(s2l>=0) emit_cmp(s1l,s2l);
5953 else emit_test(s1l,s1l);
5954 emit_cmovne_reg(alt,addr);
5955 }
5956 }
cf95b4f0 5957 if((dops[i].opcode&0x3f)==5) // BNE
57871462 5958 {
5959 #ifdef HAVE_CMOV_IMM
ad49de89 5960 if(s2l>=0) emit_cmp(s1l,s2l);
5961 else emit_test(s1l,s1l);
5962 emit_cmov2imm_e_ne_compact(start+i*4+8,ba[i],addr);
5963 #else
5964 assert(s1l>=0);
5965 emit_mov2imm_compact(start+i*4+8,addr,ba[i],alt);
5966 if(s2l>=0) emit_cmp(s1l,s2l);
5967 else emit_test(s1l,s1l);
5968 emit_cmovne_reg(alt,addr);
57871462 5969 #endif
57871462 5970 }
cf95b4f0 5971 if((dops[i].opcode&0x3f)==0x14) // BEQL
57871462 5972 {
57871462 5973 if(s2l>=0) emit_cmp(s1l,s2l);
5974 else emit_test(s1l,s1l);
df4dc2b1 5975 if(nottaken) set_jump_target(nottaken, out);
5976 nottaken=out;
57871462 5977 emit_jne(0);
5978 }
cf95b4f0 5979 if((dops[i].opcode&0x3f)==0x15) // BNEL
57871462 5980 {
57871462 5981 if(s2l>=0) emit_cmp(s1l,s2l);
5982 else emit_test(s1l,s1l);
df4dc2b1 5983 nottaken=out;
57871462 5984 emit_jeq(0);
df4dc2b1 5985 if(taken) set_jump_target(taken, out);
57871462 5986 }
cf95b4f0 5987 if((dops[i].opcode&0x3f)==6) // BLEZ
57871462 5988 {
5989 emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
5990 emit_cmpimm(s1l,1);
57871462 5991 emit_cmovl_reg(alt,addr);
57871462 5992 }
cf95b4f0 5993 if((dops[i].opcode&0x3f)==7) // BGTZ
57871462 5994 {
5995 emit_mov2imm_compact(ba[i],addr,start+i*4+8,ntaddr);
5996 emit_cmpimm(s1l,1);
57871462 5997 emit_cmovl_reg(ntaddr,addr);
57871462 5998 }
cf95b4f0 5999 if((dops[i].opcode&0x3f)==0x16) // BLEZL
57871462 6000 {
cf95b4f0 6001 assert((dops[i].opcode&0x3f)!=0x16);
57871462 6002 }
cf95b4f0 6003 if((dops[i].opcode&0x3f)==0x17) // BGTZL
57871462 6004 {
cf95b4f0 6005 assert((dops[i].opcode&0x3f)!=0x17);
57871462 6006 }
cf95b4f0 6007 assert(dops[i].opcode!=1); // BLTZ/BGEZ
57871462 6008
6009 //FIXME: Check CSREG
cf95b4f0 6010 if(dops[i].opcode==0x11 && dops[i].opcode2==0x08 ) {
57871462 6011 if((source[i]&0x30000)==0) // BC1F
6012 {
6013 emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
6014 emit_testimm(s1l,0x800000);
6015 emit_cmovne_reg(alt,addr);
6016 }
6017 if((source[i]&0x30000)==0x10000) // BC1T
6018 {
6019 emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
6020 emit_testimm(s1l,0x800000);
6021 emit_cmovne_reg(alt,addr);
6022 }
6023 if((source[i]&0x30000)==0x20000) // BC1FL
6024 {
6025 emit_testimm(s1l,0x800000);
df4dc2b1 6026 nottaken=out;
57871462 6027 emit_jne(0);
6028 }
6029 if((source[i]&0x30000)==0x30000) // BC1TL
6030 {
6031 emit_testimm(s1l,0x800000);
df4dc2b1 6032 nottaken=out;
57871462 6033 emit_jeq(0);
6034 }
6035 }
6036
6037 assert(i_regs->regmap[HOST_CCREG]==CCREG);
ad49de89 6038 wb_dirtys(regs[i].regmap,regs[i].dirty);
fe807a8a 6039 if(unconditional)
57871462 6040 {
6041 emit_movimm(ba[i],HOST_BTREG);
6042 }
6043 else if(addr!=HOST_BTREG)
6044 {
6045 emit_mov(addr,HOST_BTREG);
6046 }
6047 void *branch_addr=out;
6048 emit_jmp(0);
6049 int target_addr=start+i*4+5;
6050 void *stub=out;
6051 void *compiled_target_addr=check_addr(target_addr);
643aeae3 6052 emit_extjump_ds(branch_addr, target_addr);
57871462 6053 if(compiled_target_addr) {
df4dc2b1 6054 set_jump_target(branch_addr, compiled_target_addr);
3d680478 6055 add_jump_out(target_addr,stub);
57871462 6056 }
df4dc2b1 6057 else set_jump_target(branch_addr, stub);
57871462 6058}
6059
6060// Assemble the delay slot for the above
6061static void pagespan_ds()
6062{
6063 assem_debug("initial delay slot:\n");
6064 u_int vaddr=start+1;
94d23bb9 6065 u_int page=get_page(vaddr);
6066 u_int vpage=get_vpage(vaddr);
57871462 6067 ll_add(jump_dirty+vpage,vaddr,(void *)out);
3d680478 6068 do_dirty_stub_ds(slen*4);
57871462 6069 ll_add(jump_in+page,vaddr,(void *)out);
6070 assert(regs[0].regmap_entry[HOST_CCREG]==CCREG);
6071 if(regs[0].regmap[HOST_CCREG]!=CCREG)
ad49de89 6072 wb_register(CCREG,regs[0].regmap_entry,regs[0].wasdirty);
57871462 6073 if(regs[0].regmap[HOST_BTREG]!=BTREG)
643aeae3 6074 emit_writeword(HOST_BTREG,&branch_target);
cf95b4f0 6075 load_regs(regs[0].regmap_entry,regs[0].regmap,dops[0].rs1,dops[0].rs2);
57871462 6076 address_generation(0,&regs[0],regs[0].regmap_entry);
37387d8b 6077 if (ram_offset && (dops[0].is_load || dops[0].is_store))
6078 load_regs(regs[0].regmap_entry,regs[0].regmap,ROREG,ROREG);
6079 if (dops[0].is_store)
ad49de89 6080 load_regs(regs[0].regmap_entry,regs[0].regmap,INVCP,INVCP);
57871462 6081 is_delayslot=0;
2330734f 6082 switch (dops[0].itype) {
57871462 6083 case SYSCALL:
7139f3c8 6084 case HLECALL:
1e973cb0 6085 case INTCALL:
57871462 6086 case SPAN:
6087 case UJUMP:
6088 case RJUMP:
6089 case CJUMP:
6090 case SJUMP:
c43b5311 6091 SysPrintf("Jump in the delay slot. This is probably a bug.\n");
2330734f 6092 break;
6093 default:
6094 assemble(0, &regs[0], 0);
57871462 6095 }
6096 int btaddr=get_reg(regs[0].regmap,BTREG);
6097 if(btaddr<0) {
6098 btaddr=get_reg(regs[0].regmap,-1);
643aeae3 6099 emit_readword(&branch_target,btaddr);
57871462 6100 }
6101 assert(btaddr!=HOST_CCREG);
6102 if(regs[0].regmap[HOST_CCREG]!=CCREG) emit_loadreg(CCREG,HOST_CCREG);
6103#ifdef HOST_IMM8
d1e4ebd9 6104 host_tempreg_acquire();
57871462 6105 emit_movimm(start+4,HOST_TEMPREG);
6106 emit_cmp(btaddr,HOST_TEMPREG);
d1e4ebd9 6107 host_tempreg_release();
57871462 6108#else
6109 emit_cmpimm(btaddr,start+4);
6110#endif
df4dc2b1 6111 void *branch = out;
57871462 6112 emit_jeq(0);
ad49de89 6113 store_regs_bt(regs[0].regmap,regs[0].dirty,-1);
d1e4ebd9 6114 do_jump_vaddr(btaddr);
df4dc2b1 6115 set_jump_target(branch, out);
ad49de89 6116 store_regs_bt(regs[0].regmap,regs[0].dirty,start+4);
6117 load_regs_bt(regs[0].regmap,regs[0].dirty,start+4);
57871462 6118}
6119
6120// Basic liveness analysis for MIPS registers
6121void unneeded_registers(int istart,int iend,int r)
6122{
6123 int i;
00fa9369 6124 uint64_t u,gte_u,b,gte_b;
6125 uint64_t temp_u,temp_gte_u=0;
0ff8c62c 6126 uint64_t gte_u_unknown=0;
d62c125a 6127 if (HACK_ENABLED(NDHACK_GTE_UNNEEDED))
0ff8c62c 6128 gte_u_unknown=~0ll;
57871462 6129 if(iend==slen-1) {
00fa9369 6130 u=1;
0ff8c62c 6131 gte_u=gte_u_unknown;
57871462 6132 }else{
00fa9369 6133 //u=unneeded_reg[iend+1];
6134 u=1;
0ff8c62c 6135 gte_u=gte_unneeded[iend+1];
57871462 6136 }
bedfea38 6137
57871462 6138 for (i=iend;i>=istart;i--)
6139 {
6140 //printf("unneeded registers i=%d (%d,%d) r=%d\n",i,istart,iend,r);
fe807a8a 6141 if(dops[i].is_jump)
57871462 6142 {
6143 // If subroutine call, flag return address as a possible branch target
cf95b4f0 6144 if(dops[i].rt1==31 && i<slen-2) dops[i+2].bt=1;
9f51b4b9 6145
57871462 6146 if(ba[i]<start || ba[i]>=(start+slen*4))
6147 {
6148 // Branch out of this block, flush all regs
6149 u=1;
0ff8c62c 6150 gte_u=gte_u_unknown;
57871462 6151 branch_unneeded_reg[i]=u;
57871462 6152 // Merge in delay slot
cf95b4f0 6153 u|=(1LL<<dops[i+1].rt1)|(1LL<<dops[i+1].rt2);
6154 u&=~((1LL<<dops[i+1].rs1)|(1LL<<dops[i+1].rs2));
00fa9369 6155 u|=1;
bedfea38 6156 gte_u|=gte_rt[i+1];
6157 gte_u&=~gte_rs[i+1];
57871462 6158 }
6159 else
6160 {
6161 // Internal branch, flag target
cf95b4f0 6162 dops[(ba[i]-start)>>2].bt=1;
57871462 6163 if(ba[i]<=start+i*4) {
6164 // Backward branch
fe807a8a 6165 if(dops[i].is_ujump)
57871462 6166 {
6167 // Unconditional branch
00fa9369 6168 temp_u=1;
bedfea38 6169 temp_gte_u=0;
57871462 6170 } else {
6171 // Conditional branch (not taken case)
6172 temp_u=unneeded_reg[i+2];
bedfea38 6173 temp_gte_u&=gte_unneeded[i+2];
57871462 6174 }
6175 // Merge in delay slot
cf95b4f0 6176 temp_u|=(1LL<<dops[i+1].rt1)|(1LL<<dops[i+1].rt2);
6177 temp_u&=~((1LL<<dops[i+1].rs1)|(1LL<<dops[i+1].rs2));
00fa9369 6178 temp_u|=1;
bedfea38 6179 temp_gte_u|=gte_rt[i+1];
6180 temp_gte_u&=~gte_rs[i+1];
cf95b4f0 6181 temp_u|=(1LL<<dops[i].rt1)|(1LL<<dops[i].rt2);
6182 temp_u&=~((1LL<<dops[i].rs1)|(1LL<<dops[i].rs2));
00fa9369 6183 temp_u|=1;
bedfea38 6184 temp_gte_u|=gte_rt[i];
6185 temp_gte_u&=~gte_rs[i];
57871462 6186 unneeded_reg[i]=temp_u;
bedfea38 6187 gte_unneeded[i]=temp_gte_u;
57871462 6188 // Only go three levels deep. This recursion can take an
6189 // excessive amount of time if there are a lot of nested loops.
6190 if(r<2) {
6191 unneeded_registers((ba[i]-start)>>2,i-1,r+1);
6192 }else{
6193 unneeded_reg[(ba[i]-start)>>2]=1;
0ff8c62c 6194 gte_unneeded[(ba[i]-start)>>2]=gte_u_unknown;
57871462 6195 }
6196 } /*else*/ if(1) {
fe807a8a 6197 if (dops[i].is_ujump)
57871462 6198 {
6199 // Unconditional branch
6200 u=unneeded_reg[(ba[i]-start)>>2];
bedfea38 6201 gte_u=gte_unneeded[(ba[i]-start)>>2];
57871462 6202 branch_unneeded_reg[i]=u;
57871462 6203 // Merge in delay slot
cf95b4f0 6204 u|=(1LL<<dops[i+1].rt1)|(1LL<<dops[i+1].rt2);
6205 u&=~((1LL<<dops[i+1].rs1)|(1LL<<dops[i+1].rs2));
00fa9369 6206 u|=1;
bedfea38 6207 gte_u|=gte_rt[i+1];
6208 gte_u&=~gte_rs[i+1];
57871462 6209 } else {
6210 // Conditional branch
6211 b=unneeded_reg[(ba[i]-start)>>2];
00fa9369 6212 gte_b=gte_unneeded[(ba[i]-start)>>2];
57871462 6213 branch_unneeded_reg[i]=b;
57871462 6214 // Branch delay slot
cf95b4f0 6215 b|=(1LL<<dops[i+1].rt1)|(1LL<<dops[i+1].rt2);
6216 b&=~((1LL<<dops[i+1].rs1)|(1LL<<dops[i+1].rs2));
00fa9369 6217 b|=1;
6218 gte_b|=gte_rt[i+1];
6219 gte_b&=~gte_rs[i+1];
fe807a8a 6220 u&=b;
6221 gte_u&=gte_b;
57871462 6222 if(i<slen-1) {
6223 branch_unneeded_reg[i]&=unneeded_reg[i+2];
57871462 6224 } else {
6225 branch_unneeded_reg[i]=1;
57871462 6226 }
6227 }
6228 }
6229 }
6230 }
cf95b4f0 6231 else if(dops[i].itype==SYSCALL||dops[i].itype==HLECALL||dops[i].itype==INTCALL)
57871462 6232 {
6233 // SYSCALL instruction (software interrupt)
6234 u=1;
57871462 6235 }
cf95b4f0 6236 else if(dops[i].itype==COP0 && (source[i]&0x3f)==0x18)
57871462 6237 {
6238 // ERET instruction (return from interrupt)
6239 u=1;
57871462 6240 }
00fa9369 6241 //u=1; // DEBUG
57871462 6242 // Written registers are unneeded
cf95b4f0 6243 u|=1LL<<dops[i].rt1;
6244 u|=1LL<<dops[i].rt2;
bedfea38 6245 gte_u|=gte_rt[i];
57871462 6246 // Accessed registers are needed
cf95b4f0 6247 u&=~(1LL<<dops[i].rs1);
6248 u&=~(1LL<<dops[i].rs2);
bedfea38 6249 gte_u&=~gte_rs[i];
cf95b4f0 6250 if(gte_rs[i]&&dops[i].rt1&&(unneeded_reg[i+1]&(1ll<<dops[i].rt1)))
cbbd8dd7 6251 gte_u|=gte_rs[i]&gte_unneeded[i+1]; // MFC2/CFC2 to dead register, unneeded
57871462 6252 // Source-target dependencies
57871462 6253 // R0 is always unneeded
00fa9369 6254 u|=1;
57871462 6255 // Save it
6256 unneeded_reg[i]=u;
bedfea38 6257 gte_unneeded[i]=gte_u;
57871462 6258 /*
6259 printf("ur (%d,%d) %x: ",istart,iend,start+i*4);
6260 printf("U:");
6261 int r;
6262 for(r=1;r<=CCREG;r++) {
6263 if((unneeded_reg[i]>>r)&1) {
6264 if(r==HIREG) printf(" HI");
6265 else if(r==LOREG) printf(" LO");
6266 else printf(" r%d",r);
6267 }
6268 }
00fa9369 6269 printf("\n");
6270 */
252c20fc 6271 }
57871462 6272}
6273
71e490c5 6274// Write back dirty registers as soon as we will no longer modify them,
6275// so that we don't end up with lots of writes at the branches.
6276void clean_registers(int istart,int iend,int wr)
57871462 6277{
71e490c5 6278 int i;
6279 int r;
6280 u_int will_dirty_i,will_dirty_next,temp_will_dirty;
6281 u_int wont_dirty_i,wont_dirty_next,temp_wont_dirty;
6282 if(iend==slen-1) {
6283 will_dirty_i=will_dirty_next=0;
6284 wont_dirty_i=wont_dirty_next=0;
6285 }else{
6286 will_dirty_i=will_dirty_next=will_dirty[iend+1];
6287 wont_dirty_i=wont_dirty_next=wont_dirty[iend+1];
6288 }
6289 for (i=iend;i>=istart;i--)
57871462 6290 {
fe807a8a 6291 if(dops[i].is_jump)
57871462 6292 {
71e490c5 6293 if(ba[i]<start || ba[i]>=(start+slen*4))
57871462 6294 {
71e490c5 6295 // Branch out of this block, flush all regs
fe807a8a 6296 if (dops[i].is_ujump)
57871462 6297 {
6298 // Unconditional branch
6299 will_dirty_i=0;
6300 wont_dirty_i=0;
6301 // Merge in delay slot (will dirty)
6302 for(r=0;r<HOST_REGS;r++) {
6303 if(r!=EXCLUDE_REG) {
cf95b4f0 6304 if((branch_regs[i].regmap[r]&63)==dops[i].rt1) will_dirty_i|=1<<r;
6305 if((branch_regs[i].regmap[r]&63)==dops[i].rt2) will_dirty_i|=1<<r;
6306 if((branch_regs[i].regmap[r]&63)==dops[i+1].rt1) will_dirty_i|=1<<r;
6307 if((branch_regs[i].regmap[r]&63)==dops[i+1].rt2) will_dirty_i|=1<<r;
57871462 6308 if((branch_regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
6309 if(branch_regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
6310 if(branch_regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
cf95b4f0 6311 if((regs[i].regmap[r]&63)==dops[i].rt1) will_dirty_i|=1<<r;
6312 if((regs[i].regmap[r]&63)==dops[i].rt2) will_dirty_i|=1<<r;
6313 if((regs[i].regmap[r]&63)==dops[i+1].rt1) will_dirty_i|=1<<r;
6314 if((regs[i].regmap[r]&63)==dops[i+1].rt2) will_dirty_i|=1<<r;
57871462 6315 if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
6316 if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
6317 if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
6318 }
6319 }
6320 }
6321 else
6322 {
6323 // Conditional branch
6324 will_dirty_i=0;
6325 wont_dirty_i=wont_dirty_next;
6326 // Merge in delay slot (will dirty)
6327 for(r=0;r<HOST_REGS;r++) {
6328 if(r!=EXCLUDE_REG) {
fe807a8a 6329 if (1) { // !dops[i].likely) {
57871462 6330 // Might not dirty if likely branch is not taken
cf95b4f0 6331 if((branch_regs[i].regmap[r]&63)==dops[i].rt1) will_dirty_i|=1<<r;
6332 if((branch_regs[i].regmap[r]&63)==dops[i].rt2) will_dirty_i|=1<<r;
6333 if((branch_regs[i].regmap[r]&63)==dops[i+1].rt1) will_dirty_i|=1<<r;
6334 if((branch_regs[i].regmap[r]&63)==dops[i+1].rt2) will_dirty_i|=1<<r;
57871462 6335 if((branch_regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
6336 if(branch_regs[i].regmap[r]==0) will_dirty_i&=~(1<<r);
6337 if(branch_regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
cf95b4f0 6338 //if((regs[i].regmap[r]&63)==dops[i].rt1) will_dirty_i|=1<<r;
6339 //if((regs[i].regmap[r]&63)==dops[i].rt2) will_dirty_i|=1<<r;
6340 if((regs[i].regmap[r]&63)==dops[i+1].rt1) will_dirty_i|=1<<r;
6341 if((regs[i].regmap[r]&63)==dops[i+1].rt2) will_dirty_i|=1<<r;
57871462 6342 if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
6343 if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
6344 if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
6345 }
6346 }
6347 }
6348 }
6349 // Merge in delay slot (wont dirty)
6350 for(r=0;r<HOST_REGS;r++) {
6351 if(r!=EXCLUDE_REG) {
cf95b4f0 6352 if((regs[i].regmap[r]&63)==dops[i].rt1) wont_dirty_i|=1<<r;
6353 if((regs[i].regmap[r]&63)==dops[i].rt2) wont_dirty_i|=1<<r;
6354 if((regs[i].regmap[r]&63)==dops[i+1].rt1) wont_dirty_i|=1<<r;
6355 if((regs[i].regmap[r]&63)==dops[i+1].rt2) wont_dirty_i|=1<<r;
57871462 6356 if(regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
cf95b4f0 6357 if((branch_regs[i].regmap[r]&63)==dops[i].rt1) wont_dirty_i|=1<<r;
6358 if((branch_regs[i].regmap[r]&63)==dops[i].rt2) wont_dirty_i|=1<<r;
6359 if((branch_regs[i].regmap[r]&63)==dops[i+1].rt1) wont_dirty_i|=1<<r;
6360 if((branch_regs[i].regmap[r]&63)==dops[i+1].rt2) wont_dirty_i|=1<<r;
57871462 6361 if(branch_regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
6362 }
6363 }
6364 if(wr) {
6365 #ifndef DESTRUCTIVE_WRITEBACK
6366 branch_regs[i].dirty&=wont_dirty_i;
6367 #endif
6368 branch_regs[i].dirty|=will_dirty_i;
6369 }
6370 }
6371 else
6372 {
6373 // Internal branch
6374 if(ba[i]<=start+i*4) {
6375 // Backward branch
fe807a8a 6376 if (dops[i].is_ujump)
57871462 6377 {
6378 // Unconditional branch
6379 temp_will_dirty=0;
6380 temp_wont_dirty=0;
6381 // Merge in delay slot (will dirty)
6382 for(r=0;r<HOST_REGS;r++) {
6383 if(r!=EXCLUDE_REG) {
cf95b4f0 6384 if((branch_regs[i].regmap[r]&63)==dops[i].rt1) temp_will_dirty|=1<<r;
6385 if((branch_regs[i].regmap[r]&63)==dops[i].rt2) temp_will_dirty|=1<<r;
6386 if((branch_regs[i].regmap[r]&63)==dops[i+1].rt1) temp_will_dirty|=1<<r;
6387 if((branch_regs[i].regmap[r]&63)==dops[i+1].rt2) temp_will_dirty|=1<<r;
57871462 6388 if((branch_regs[i].regmap[r]&63)>33) temp_will_dirty&=~(1<<r);
6389 if(branch_regs[i].regmap[r]<=0) temp_will_dirty&=~(1<<r);
6390 if(branch_regs[i].regmap[r]==CCREG) temp_will_dirty|=1<<r;
cf95b4f0 6391 if((regs[i].regmap[r]&63)==dops[i].rt1) temp_will_dirty|=1<<r;
6392 if((regs[i].regmap[r]&63)==dops[i].rt2) temp_will_dirty|=1<<r;
6393 if((regs[i].regmap[r]&63)==dops[i+1].rt1) temp_will_dirty|=1<<r;
6394 if((regs[i].regmap[r]&63)==dops[i+1].rt2) temp_will_dirty|=1<<r;
57871462 6395 if((regs[i].regmap[r]&63)>33) temp_will_dirty&=~(1<<r);
6396 if(regs[i].regmap[r]<=0) temp_will_dirty&=~(1<<r);
6397 if(regs[i].regmap[r]==CCREG) temp_will_dirty|=1<<r;
6398 }
6399 }
6400 } else {
6401 // Conditional branch (not taken case)
6402 temp_will_dirty=will_dirty_next;
6403 temp_wont_dirty=wont_dirty_next;
6404 // Merge in delay slot (will dirty)
6405 for(r=0;r<HOST_REGS;r++) {
6406 if(r!=EXCLUDE_REG) {
fe807a8a 6407 if (1) { // !dops[i].likely) {
57871462 6408 // Will not dirty if likely branch is not taken
cf95b4f0 6409 if((branch_regs[i].regmap[r]&63)==dops[i].rt1) temp_will_dirty|=1<<r;
6410 if((branch_regs[i].regmap[r]&63)==dops[i].rt2) temp_will_dirty|=1<<r;
6411 if((branch_regs[i].regmap[r]&63)==dops[i+1].rt1) temp_will_dirty|=1<<r;
6412 if((branch_regs[i].regmap[r]&63)==dops[i+1].rt2) temp_will_dirty|=1<<r;
57871462 6413 if((branch_regs[i].regmap[r]&63)>33) temp_will_dirty&=~(1<<r);
6414 if(branch_regs[i].regmap[r]==0) temp_will_dirty&=~(1<<r);
6415 if(branch_regs[i].regmap[r]==CCREG) temp_will_dirty|=1<<r;
cf95b4f0 6416 //if((regs[i].regmap[r]&63)==dops[i].rt1) temp_will_dirty|=1<<r;
6417 //if((regs[i].regmap[r]&63)==dops[i].rt2) temp_will_dirty|=1<<r;
6418 if((regs[i].regmap[r]&63)==dops[i+1].rt1) temp_will_dirty|=1<<r;
6419 if((regs[i].regmap[r]&63)==dops[i+1].rt2) temp_will_dirty|=1<<r;
57871462 6420 if((regs[i].regmap[r]&63)>33) temp_will_dirty&=~(1<<r);
6421 if(regs[i].regmap[r]<=0) temp_will_dirty&=~(1<<r);
6422 if(regs[i].regmap[r]==CCREG) temp_will_dirty|=1<<r;
6423 }
6424 }
6425 }
6426 }
6427 // Merge in delay slot (wont dirty)
6428 for(r=0;r<HOST_REGS;r++) {
6429 if(r!=EXCLUDE_REG) {
cf95b4f0 6430 if((regs[i].regmap[r]&63)==dops[i].rt1) temp_wont_dirty|=1<<r;
6431 if((regs[i].regmap[r]&63)==dops[i].rt2) temp_wont_dirty|=1<<r;
6432 if((regs[i].regmap[r]&63)==dops[i+1].rt1) temp_wont_dirty|=1<<r;
6433 if((regs[i].regmap[r]&63)==dops[i+1].rt2) temp_wont_dirty|=1<<r;
57871462 6434 if(regs[i].regmap[r]==CCREG) temp_wont_dirty|=1<<r;
cf95b4f0 6435 if((branch_regs[i].regmap[r]&63)==dops[i].rt1) temp_wont_dirty|=1<<r;
6436 if((branch_regs[i].regmap[r]&63)==dops[i].rt2) temp_wont_dirty|=1<<r;
6437 if((branch_regs[i].regmap[r]&63)==dops[i+1].rt1) temp_wont_dirty|=1<<r;
6438 if((branch_regs[i].regmap[r]&63)==dops[i+1].rt2) temp_wont_dirty|=1<<r;
57871462 6439 if(branch_regs[i].regmap[r]==CCREG) temp_wont_dirty|=1<<r;
6440 }
6441 }
6442 // Deal with changed mappings
6443 if(i<iend) {
6444 for(r=0;r<HOST_REGS;r++) {
6445 if(r!=EXCLUDE_REG) {
6446 if(regs[i].regmap[r]!=regmap_pre[i][r]) {
6447 temp_will_dirty&=~(1<<r);
6448 temp_wont_dirty&=~(1<<r);
6449 if((regmap_pre[i][r]&63)>0 && (regmap_pre[i][r]&63)<34) {
6450 temp_will_dirty|=((unneeded_reg[i]>>(regmap_pre[i][r]&63))&1)<<r;
6451 temp_wont_dirty|=((unneeded_reg[i]>>(regmap_pre[i][r]&63))&1)<<r;
6452 } else {
6453 temp_will_dirty|=1<<r;
6454 temp_wont_dirty|=1<<r;
6455 }
6456 }
6457 }
6458 }
6459 }
6460 if(wr) {
6461 will_dirty[i]=temp_will_dirty;
6462 wont_dirty[i]=temp_wont_dirty;
6463 clean_registers((ba[i]-start)>>2,i-1,0);
6464 }else{
6465 // Limit recursion. It can take an excessive amount
6466 // of time if there are a lot of nested loops.
6467 will_dirty[(ba[i]-start)>>2]=0;
6468 wont_dirty[(ba[i]-start)>>2]=-1;
6469 }
6470 }
6471 /*else*/ if(1)
6472 {
fe807a8a 6473 if (dops[i].is_ujump)
57871462 6474 {
6475 // Unconditional branch
6476 will_dirty_i=0;
6477 wont_dirty_i=0;
6478 //if(ba[i]>start+i*4) { // Disable recursion (for debugging)
6479 for(r=0;r<HOST_REGS;r++) {
6480 if(r!=EXCLUDE_REG) {
6481 if(branch_regs[i].regmap[r]==regs[(ba[i]-start)>>2].regmap_entry[r]) {
6482 will_dirty_i|=will_dirty[(ba[i]-start)>>2]&(1<<r);
6483 wont_dirty_i|=wont_dirty[(ba[i]-start)>>2]&(1<<r);
6484 }
e3234ecf 6485 if(branch_regs[i].regmap[r]>=0) {
6486 will_dirty_i|=((unneeded_reg[(ba[i]-start)>>2]>>(branch_regs[i].regmap[r]&63))&1)<<r;
6487 wont_dirty_i|=((unneeded_reg[(ba[i]-start)>>2]>>(branch_regs[i].regmap[r]&63))&1)<<r;
6488 }
57871462 6489 }
6490 }
6491 //}
6492 // Merge in delay slot
6493 for(r=0;r<HOST_REGS;r++) {
6494 if(r!=EXCLUDE_REG) {
cf95b4f0 6495 if((branch_regs[i].regmap[r]&63)==dops[i].rt1) will_dirty_i|=1<<r;
6496 if((branch_regs[i].regmap[r]&63)==dops[i].rt2) will_dirty_i|=1<<r;
6497 if((branch_regs[i].regmap[r]&63)==dops[i+1].rt1) will_dirty_i|=1<<r;
6498 if((branch_regs[i].regmap[r]&63)==dops[i+1].rt2) will_dirty_i|=1<<r;
57871462 6499 if((branch_regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
6500 if(branch_regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
6501 if(branch_regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
cf95b4f0 6502 if((regs[i].regmap[r]&63)==dops[i].rt1) will_dirty_i|=1<<r;
6503 if((regs[i].regmap[r]&63)==dops[i].rt2) will_dirty_i|=1<<r;
6504 if((regs[i].regmap[r]&63)==dops[i+1].rt1) will_dirty_i|=1<<r;
6505 if((regs[i].regmap[r]&63)==dops[i+1].rt2) will_dirty_i|=1<<r;
57871462 6506 if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
6507 if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
6508 if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
6509 }
6510 }
6511 } else {
6512 // Conditional branch
6513 will_dirty_i=will_dirty_next;
6514 wont_dirty_i=wont_dirty_next;
6515 //if(ba[i]>start+i*4) { // Disable recursion (for debugging)
6516 for(r=0;r<HOST_REGS;r++) {
6517 if(r!=EXCLUDE_REG) {
e3234ecf 6518 signed char target_reg=branch_regs[i].regmap[r];
6519 if(target_reg==regs[(ba[i]-start)>>2].regmap_entry[r]) {
57871462 6520 will_dirty_i&=will_dirty[(ba[i]-start)>>2]&(1<<r);
6521 wont_dirty_i|=wont_dirty[(ba[i]-start)>>2]&(1<<r);
6522 }
e3234ecf 6523 else if(target_reg>=0) {
6524 will_dirty_i&=((unneeded_reg[(ba[i]-start)>>2]>>(target_reg&63))&1)<<r;
6525 wont_dirty_i|=((unneeded_reg[(ba[i]-start)>>2]>>(target_reg&63))&1)<<r;
57871462 6526 }
57871462 6527 }
6528 }
6529 //}
6530 // Merge in delay slot
6531 for(r=0;r<HOST_REGS;r++) {
6532 if(r!=EXCLUDE_REG) {
fe807a8a 6533 if (1) { // !dops[i].likely) {
57871462 6534 // Might not dirty if likely branch is not taken
cf95b4f0 6535 if((branch_regs[i].regmap[r]&63)==dops[i].rt1) will_dirty_i|=1<<r;
6536 if((branch_regs[i].regmap[r]&63)==dops[i].rt2) will_dirty_i|=1<<r;
6537 if((branch_regs[i].regmap[r]&63)==dops[i+1].rt1) will_dirty_i|=1<<r;
6538 if((branch_regs[i].regmap[r]&63)==dops[i+1].rt2) will_dirty_i|=1<<r;
57871462 6539 if((branch_regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
6540 if(branch_regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
6541 if(branch_regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
cf95b4f0 6542 //if((regs[i].regmap[r]&63)==dops[i].rt1) will_dirty_i|=1<<r;
6543 //if((regs[i].regmap[r]&63)==dops[i].rt2) will_dirty_i|=1<<r;
6544 if((regs[i].regmap[r]&63)==dops[i+1].rt1) will_dirty_i|=1<<r;
6545 if((regs[i].regmap[r]&63)==dops[i+1].rt2) will_dirty_i|=1<<r;
57871462 6546 if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
6547 if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
6548 if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
6549 }
6550 }
6551 }
6552 }
e3234ecf 6553 // Merge in delay slot (won't dirty)
57871462 6554 for(r=0;r<HOST_REGS;r++) {
6555 if(r!=EXCLUDE_REG) {
cf95b4f0 6556 if((regs[i].regmap[r]&63)==dops[i].rt1) wont_dirty_i|=1<<r;
6557 if((regs[i].regmap[r]&63)==dops[i].rt2) wont_dirty_i|=1<<r;
6558 if((regs[i].regmap[r]&63)==dops[i+1].rt1) wont_dirty_i|=1<<r;
6559 if((regs[i].regmap[r]&63)==dops[i+1].rt2) wont_dirty_i|=1<<r;
57871462 6560 if(regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
cf95b4f0 6561 if((branch_regs[i].regmap[r]&63)==dops[i].rt1) wont_dirty_i|=1<<r;
6562 if((branch_regs[i].regmap[r]&63)==dops[i].rt2) wont_dirty_i|=1<<r;
6563 if((branch_regs[i].regmap[r]&63)==dops[i+1].rt1) wont_dirty_i|=1<<r;
6564 if((branch_regs[i].regmap[r]&63)==dops[i+1].rt2) wont_dirty_i|=1<<r;
57871462 6565 if(branch_regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
6566 }
6567 }
6568 if(wr) {
6569 #ifndef DESTRUCTIVE_WRITEBACK
6570 branch_regs[i].dirty&=wont_dirty_i;
6571 #endif
6572 branch_regs[i].dirty|=will_dirty_i;
6573 }
6574 }
6575 }
6576 }
cf95b4f0 6577 else if(dops[i].itype==SYSCALL||dops[i].itype==HLECALL||dops[i].itype==INTCALL)
57871462 6578 {
6579 // SYSCALL instruction (software interrupt)
6580 will_dirty_i=0;
6581 wont_dirty_i=0;
6582 }
cf95b4f0 6583 else if(dops[i].itype==COP0 && (source[i]&0x3f)==0x18)
57871462 6584 {
6585 // ERET instruction (return from interrupt)
6586 will_dirty_i=0;
6587 wont_dirty_i=0;
6588 }
6589 will_dirty_next=will_dirty_i;
6590 wont_dirty_next=wont_dirty_i;
6591 for(r=0;r<HOST_REGS;r++) {
6592 if(r!=EXCLUDE_REG) {
cf95b4f0 6593 if((regs[i].regmap[r]&63)==dops[i].rt1) will_dirty_i|=1<<r;
6594 if((regs[i].regmap[r]&63)==dops[i].rt2) will_dirty_i|=1<<r;
57871462 6595 if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
6596 if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
6597 if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
cf95b4f0 6598 if((regs[i].regmap[r]&63)==dops[i].rt1) wont_dirty_i|=1<<r;
6599 if((regs[i].regmap[r]&63)==dops[i].rt2) wont_dirty_i|=1<<r;
57871462 6600 if(regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
6601 if(i>istart) {
fe807a8a 6602 if (!dops[i].is_jump)
57871462 6603 {
6604 // Don't store a register immediately after writing it,
6605 // may prevent dual-issue.
cf95b4f0 6606 if((regs[i].regmap[r]&63)==dops[i-1].rt1) wont_dirty_i|=1<<r;
6607 if((regs[i].regmap[r]&63)==dops[i-1].rt2) wont_dirty_i|=1<<r;
57871462 6608 }
6609 }
6610 }
6611 }
6612 // Save it
6613 will_dirty[i]=will_dirty_i;
6614 wont_dirty[i]=wont_dirty_i;
6615 // Mark registers that won't be dirtied as not dirty
6616 if(wr) {
57871462 6617 regs[i].dirty|=will_dirty_i;
6618 #ifndef DESTRUCTIVE_WRITEBACK
6619 regs[i].dirty&=wont_dirty_i;
fe807a8a 6620 if(dops[i].is_jump)
57871462 6621 {
fe807a8a 6622 if (i < iend-1 && !dops[i].is_ujump) {
57871462 6623 for(r=0;r<HOST_REGS;r++) {
6624 if(r!=EXCLUDE_REG) {
6625 if(regs[i].regmap[r]==regmap_pre[i+2][r]) {
6626 regs[i+2].wasdirty&=wont_dirty_i|~(1<<r);
581335b0 6627 }else {/*printf("i: %x (%d) mismatch(+2): %d\n",start+i*4,i,r);assert(!((wont_dirty_i>>r)&1));*/}
57871462 6628 }
6629 }
6630 }
6631 }
6632 else
6633 {
6634 if(i<iend) {
6635 for(r=0;r<HOST_REGS;r++) {
6636 if(r!=EXCLUDE_REG) {
6637 if(regs[i].regmap[r]==regmap_pre[i+1][r]) {
6638 regs[i+1].wasdirty&=wont_dirty_i|~(1<<r);
581335b0 6639 }else {/*printf("i: %x (%d) mismatch(+1): %d\n",start+i*4,i,r);assert(!((wont_dirty_i>>r)&1));*/}
57871462 6640 }
6641 }
6642 }
6643 }
6644 #endif
6645 //}
6646 }
6647 // Deal with changed mappings
6648 temp_will_dirty=will_dirty_i;
6649 temp_wont_dirty=wont_dirty_i;
6650 for(r=0;r<HOST_REGS;r++) {
6651 if(r!=EXCLUDE_REG) {
6652 int nr;
6653 if(regs[i].regmap[r]==regmap_pre[i][r]) {
6654 if(wr) {
6655 #ifndef DESTRUCTIVE_WRITEBACK
6656 regs[i].wasdirty&=wont_dirty_i|~(1<<r);
6657 #endif
6658 regs[i].wasdirty|=will_dirty_i&(1<<r);
6659 }
6660 }
f776eb14 6661 else if(regmap_pre[i][r]>=0&&(nr=get_reg(regs[i].regmap,regmap_pre[i][r]))>=0) {
57871462 6662 // Register moved to a different register
6663 will_dirty_i&=~(1<<r);
6664 wont_dirty_i&=~(1<<r);
6665 will_dirty_i|=((temp_will_dirty>>nr)&1)<<r;
6666 wont_dirty_i|=((temp_wont_dirty>>nr)&1)<<r;
6667 if(wr) {
6668 #ifndef DESTRUCTIVE_WRITEBACK
6669 regs[i].wasdirty&=wont_dirty_i|~(1<<r);
6670 #endif
6671 regs[i].wasdirty|=will_dirty_i&(1<<r);
6672 }
6673 }
6674 else {
6675 will_dirty_i&=~(1<<r);
6676 wont_dirty_i&=~(1<<r);
6677 if((regmap_pre[i][r]&63)>0 && (regmap_pre[i][r]&63)<34) {
6678 will_dirty_i|=((unneeded_reg[i]>>(regmap_pre[i][r]&63))&1)<<r;
6679 wont_dirty_i|=((unneeded_reg[i]>>(regmap_pre[i][r]&63))&1)<<r;
6680 } else {
6681 wont_dirty_i|=1<<r;
581335b0 6682 /*printf("i: %x (%d) mismatch: %d\n",start+i*4,i,r);assert(!((will_dirty>>r)&1));*/
57871462 6683 }
6684 }
6685 }
6686 }
6687 }
6688}
6689
4600ba03 6690#ifdef DISASM
57871462 6691 /* disassembly */
6692void disassemble_inst(int i)
6693{
cf95b4f0 6694 if (dops[i].bt) printf("*"); else printf(" ");
6695 switch(dops[i].itype) {
57871462 6696 case UJUMP:
6697 printf (" %x: %s %8x\n",start+i*4,insn[i],ba[i]);break;
6698 case CJUMP:
cf95b4f0 6699 printf (" %x: %s r%d,r%d,%8x\n",start+i*4,insn[i],dops[i].rs1,dops[i].rs2,i?start+i*4+4+((signed int)((unsigned int)source[i]<<16)>>14):*ba);break;
57871462 6700 case SJUMP:
cf95b4f0 6701 printf (" %x: %s r%d,%8x\n",start+i*4,insn[i],dops[i].rs1,start+i*4+4+((signed int)((unsigned int)source[i]<<16)>>14));break;
57871462 6702 case RJUMP:
cf95b4f0 6703 if (dops[i].opcode==0x9&&dops[i].rt1!=31)
6704 printf (" %x: %s r%d,r%d\n",start+i*4,insn[i],dops[i].rt1,dops[i].rs1);
5067f341 6705 else
cf95b4f0 6706 printf (" %x: %s r%d\n",start+i*4,insn[i],dops[i].rs1);
5067f341 6707 break;
57871462 6708 case SPAN:
cf95b4f0 6709 printf (" %x: %s (pagespan) r%d,r%d,%8x\n",start+i*4,insn[i],dops[i].rs1,dops[i].rs2,ba[i]);break;
57871462 6710 case IMM16:
cf95b4f0 6711 if(dops[i].opcode==0xf) //LUI
6712 printf (" %x: %s r%d,%4x0000\n",start+i*4,insn[i],dops[i].rt1,imm[i]&0xffff);
57871462 6713 else
cf95b4f0 6714 printf (" %x: %s r%d,r%d,%d\n",start+i*4,insn[i],dops[i].rt1,dops[i].rs1,imm[i]);
57871462 6715 break;
6716 case LOAD:
6717 case LOADLR:
cf95b4f0 6718 printf (" %x: %s r%d,r%d+%x\n",start+i*4,insn[i],dops[i].rt1,dops[i].rs1,imm[i]);
57871462 6719 break;
6720 case STORE:
6721 case STORELR:
cf95b4f0 6722 printf (" %x: %s r%d,r%d+%x\n",start+i*4,insn[i],dops[i].rs2,dops[i].rs1,imm[i]);
57871462 6723 break;
6724 case ALU:
6725 case SHIFT:
cf95b4f0 6726 printf (" %x: %s r%d,r%d,r%d\n",start+i*4,insn[i],dops[i].rt1,dops[i].rs1,dops[i].rs2);
57871462 6727 break;
6728 case MULTDIV:
cf95b4f0 6729 printf (" %x: %s r%d,r%d\n",start+i*4,insn[i],dops[i].rs1,dops[i].rs2);
57871462 6730 break;
6731 case SHIFTIMM:
cf95b4f0 6732 printf (" %x: %s r%d,r%d,%d\n",start+i*4,insn[i],dops[i].rt1,dops[i].rs1,imm[i]);
57871462 6733 break;
6734 case MOV:
cf95b4f0 6735 if((dops[i].opcode2&0x1d)==0x10)
6736 printf (" %x: %s r%d\n",start+i*4,insn[i],dops[i].rt1);
6737 else if((dops[i].opcode2&0x1d)==0x11)
6738 printf (" %x: %s r%d\n",start+i*4,insn[i],dops[i].rs1);
57871462 6739 else
6740 printf (" %x: %s\n",start+i*4,insn[i]);
6741 break;
6742 case COP0:
cf95b4f0 6743 if(dops[i].opcode2==0)
6744 printf (" %x: %s r%d,cpr0[%d]\n",start+i*4,insn[i],dops[i].rt1,(source[i]>>11)&0x1f); // MFC0
6745 else if(dops[i].opcode2==4)
6746 printf (" %x: %s r%d,cpr0[%d]\n",start+i*4,insn[i],dops[i].rs1,(source[i]>>11)&0x1f); // MTC0
57871462 6747 else printf (" %x: %s\n",start+i*4,insn[i]);
6748 break;
6749 case COP1:
cf95b4f0 6750 if(dops[i].opcode2<3)
6751 printf (" %x: %s r%d,cpr1[%d]\n",start+i*4,insn[i],dops[i].rt1,(source[i]>>11)&0x1f); // MFC1
6752 else if(dops[i].opcode2>3)
6753 printf (" %x: %s r%d,cpr1[%d]\n",start+i*4,insn[i],dops[i].rs1,(source[i]>>11)&0x1f); // MTC1
57871462 6754 else printf (" %x: %s\n",start+i*4,insn[i]);
6755 break;
b9b61529 6756 case COP2:
cf95b4f0 6757 if(dops[i].opcode2<3)
6758 printf (" %x: %s r%d,cpr2[%d]\n",start+i*4,insn[i],dops[i].rt1,(source[i]>>11)&0x1f); // MFC2
6759 else if(dops[i].opcode2>3)
6760 printf (" %x: %s r%d,cpr2[%d]\n",start+i*4,insn[i],dops[i].rs1,(source[i]>>11)&0x1f); // MTC2
b9b61529 6761 else printf (" %x: %s\n",start+i*4,insn[i]);
6762 break;
57871462 6763 case C1LS:
cf95b4f0 6764 printf (" %x: %s cpr1[%d],r%d+%x\n",start+i*4,insn[i],(source[i]>>16)&0x1f,dops[i].rs1,imm[i]);
57871462 6765 break;
b9b61529 6766 case C2LS:
cf95b4f0 6767 printf (" %x: %s cpr2[%d],r%d+%x\n",start+i*4,insn[i],(source[i]>>16)&0x1f,dops[i].rs1,imm[i]);
b9b61529 6768 break;
1e973cb0 6769 case INTCALL:
6770 printf (" %x: %s (INTCALL)\n",start+i*4,insn[i]);
6771 break;
57871462 6772 default:
6773 //printf (" %s %8x\n",insn[i],source[i]);
6774 printf (" %x: %s\n",start+i*4,insn[i]);
6775 }
6776}
4600ba03 6777#else
6778static void disassemble_inst(int i) {}
6779#endif // DISASM
57871462 6780
d848b60a 6781#define DRC_TEST_VAL 0x74657374
6782
be516ebe 6783static void new_dynarec_test(void)
d848b60a 6784{
be516ebe 6785 int (*testfunc)(void);
d148d265 6786 void *beginning;
be516ebe 6787 int ret[2];
6788 size_t i;
d148d265 6789
687b4580 6790 // check structure linkage
7c3a5182 6791 if ((u_char *)rcnts - (u_char *)&psxRegs != sizeof(psxRegs))
687b4580 6792 {
7c3a5182 6793 SysPrintf("linkage_arm* miscompilation/breakage detected.\n");
687b4580 6794 }
6795
761fdd0a 6796 SysPrintf("testing if we can run recompiled code @%p...\n", out);
be516ebe 6797 ((volatile u_int *)out)[0]++; // make cache dirty
6798
6799 for (i = 0; i < ARRAY_SIZE(ret); i++) {
2a014d73 6800 out = ndrc->translation_cache;
be516ebe 6801 beginning = start_block();
6802 emit_movimm(DRC_TEST_VAL + i, 0); // test
6803 emit_ret();
6804 literal_pool(0);
6805 end_block(beginning);
6806 testfunc = beginning;
6807 ret[i] = testfunc();
6808 }
6809
6810 if (ret[0] == DRC_TEST_VAL && ret[1] == DRC_TEST_VAL + 1)
d848b60a 6811 SysPrintf("test passed.\n");
6812 else
be516ebe 6813 SysPrintf("test failed, will likely crash soon (r=%08x %08x)\n", ret[0], ret[1]);
2a014d73 6814 out = ndrc->translation_cache;
d848b60a 6815}
6816
dc990066 6817// clear the state completely, instead of just marking
6818// things invalid like invalidate_all_pages() does
919981d0 6819void new_dynarec_clear_full(void)
57871462 6820{
57871462 6821 int n;
2a014d73 6822 out = ndrc->translation_cache;
35775df7 6823 memset(invalid_code,1,sizeof(invalid_code));
6824 memset(hash_table,0xff,sizeof(hash_table));
57871462 6825 memset(mini_ht,-1,sizeof(mini_ht));
6826 memset(restore_candidate,0,sizeof(restore_candidate));
dc990066 6827 memset(shadow,0,sizeof(shadow));
57871462 6828 copy=shadow;
6829 expirep=16384; // Expiry pointer, +2 blocks
6830 pending_exception=0;
6831 literalcount=0;
57871462 6832 stop_after_jal=0;
9be4ba64 6833 inv_code_start=inv_code_end=~0;
7f94b097 6834 hack_addr=0;
39b71d9a 6835 f1_hack=0;
57871462 6836 // TLB
dc990066 6837 for(n=0;n<4096;n++) ll_clear(jump_in+n);
6838 for(n=0;n<4096;n++) ll_clear(jump_out+n);
6839 for(n=0;n<4096;n++) ll_clear(jump_dirty+n);
32631e6a 6840
6841 cycle_multiplier_old = cycle_multiplier;
6842 new_dynarec_hacks_old = new_dynarec_hacks;
dc990066 6843}
6844
919981d0 6845void new_dynarec_init(void)
dc990066 6846{
d848b60a 6847 SysPrintf("Init new dynarec\n");
1e212a25 6848
0aeb0cb9 6849#ifdef _3DS
6850 check_rosalina();
6851#endif
2a014d73 6852#ifdef BASE_ADDR_DYNAMIC
1e212a25 6853 #ifdef VITA
0aeb0cb9 6854 sceBlock = getVMBlock(); //sceKernelAllocMemBlockForVM("code", sizeof(*ndrc));
1e212a25 6855 if (sceBlock < 0)
6856 SysPrintf("sceKernelAllocMemBlockForVM failed\n");
2a014d73 6857 int ret = sceKernelGetMemBlockBase(sceBlock, (void **)&ndrc);
1e212a25 6858 if (ret < 0)
6859 SysPrintf("sceKernelGetMemBlockBase failed\n");
0aeb0cb9 6860 sceKernelOpenVMDomain();
6861 sceClibPrintf("translation_cache = 0x%08lx\n ", (long)ndrc->translation_cache);
6862 #elif defined(_MSC_VER)
6863 ndrc = VirtualAlloc(NULL, sizeof(*ndrc), MEM_COMMIT | MEM_RESERVE,
6864 PAGE_EXECUTE_READWRITE);
1e212a25 6865 #else
2a014d73 6866 uintptr_t desired_addr = 0;
6867 #ifdef __ELF__
6868 extern char _end;
6869 desired_addr = ((uintptr_t)&_end + 0xffffff) & ~0xffffffl;
6870 #endif
6871 ndrc = mmap((void *)desired_addr, sizeof(*ndrc),
1e212a25 6872 PROT_READ | PROT_WRITE | PROT_EXEC,
6873 MAP_PRIVATE | MAP_ANONYMOUS, -1, 0);
2a014d73 6874 if (ndrc == MAP_FAILED) {
d848b60a 6875 SysPrintf("mmap() failed: %s\n", strerror(errno));
1e212a25 6876 abort();
d848b60a 6877 }
1e212a25 6878 #endif
6879#else
6880 #ifndef NO_WRITE_EXEC
bdeade46 6881 // not all systems allow execute in data segment by default
761fdd0a 6882 // size must be 4K aligned for 3DS?
6883 if (mprotect(ndrc, sizeof(*ndrc),
2a014d73 6884 PROT_READ | PROT_WRITE | PROT_EXEC) != 0)
d848b60a 6885 SysPrintf("mprotect() failed: %s\n", strerror(errno));
1e212a25 6886 #endif
dc990066 6887#endif
2a014d73 6888 out = ndrc->translation_cache;
2573466a 6889 cycle_multiplier=200;
dc990066 6890 new_dynarec_clear_full();
6891#ifdef HOST_IMM8
6892 // Copy this into local area so we don't have to put it in every literal pool
6893 invc_ptr=invalid_code;
6894#endif
57871462 6895 arch_init();
d848b60a 6896 new_dynarec_test();
01d26796 6897 ram_offset=(uintptr_t)rdram-0x80000000;
b105cf4f 6898 if (ram_offset!=0)
c43b5311 6899 SysPrintf("warning: RAM is not directly mapped, performance will suffer\n");
57871462 6900}
6901
919981d0 6902void new_dynarec_cleanup(void)
57871462 6903{
6904 int n;
2a014d73 6905#ifdef BASE_ADDR_DYNAMIC
1e212a25 6906 #ifdef VITA
9c67c98f 6907 //sceKernelFreeMemBlock(sceBlock);
6908 //sceBlock = -1;
1e212a25 6909 #else
2a014d73 6910 if (munmap(ndrc, sizeof(*ndrc)) < 0)
1e212a25 6911 SysPrintf("munmap() failed\n");
bdeade46 6912 #endif
1e212a25 6913#endif
57871462 6914 for(n=0;n<4096;n++) ll_clear(jump_in+n);
6915 for(n=0;n<4096;n++) ll_clear(jump_out+n);
6916 for(n=0;n<4096;n++) ll_clear(jump_dirty+n);
6917 #ifdef ROM_COPY
c43b5311 6918 if (munmap (ROM_COPY, 67108864) < 0) {SysPrintf("munmap() failed\n");}
57871462 6919 #endif
6920}
6921
03f55e6b 6922static u_int *get_source_start(u_int addr, u_int *limit)
57871462 6923{
03f55e6b 6924 if (addr < 0x00200000 ||
a3203cf4 6925 (0xa0000000 <= addr && addr < 0xa0200000))
6926 {
03f55e6b 6927 // used for BIOS calls mostly?
6928 *limit = (addr&0xa0000000)|0x00200000;
01d26796 6929 return (u_int *)(rdram + (addr&0x1fffff));
03f55e6b 6930 }
6931 else if (!Config.HLE && (
6932 /* (0x9fc00000 <= addr && addr < 0x9fc80000) ||*/
a3203cf4 6933 (0xbfc00000 <= addr && addr < 0xbfc80000)))
6934 {
6935 // BIOS. The multiplier should be much higher as it's uncached 8bit mem,
6936 // but timings in PCSX are too tied to the interpreter's BIAS
d62c125a 6937 if (!HACK_ENABLED(NDHACK_OVERRIDE_CYCLE_M))
24058131 6938 cycle_multiplier_active = 200;
a3203cf4 6939
03f55e6b 6940 *limit = (addr & 0xfff00000) | 0x80000;
01d26796 6941 return (u_int *)((u_char *)psxR + (addr&0x7ffff));
03f55e6b 6942 }
6943 else if (addr >= 0x80000000 && addr < 0x80000000+RAM_SIZE) {
6944 *limit = (addr & 0x80600000) + 0x00200000;
01d26796 6945 return (u_int *)(rdram + (addr&0x1fffff));
03f55e6b 6946 }
581335b0 6947 return NULL;
03f55e6b 6948}
6949
6950static u_int scan_for_ret(u_int addr)
6951{
6952 u_int limit = 0;
6953 u_int *mem;
6954
6955 mem = get_source_start(addr, &limit);
6956 if (mem == NULL)
6957 return addr;
6958
6959 if (limit > addr + 0x1000)
6960 limit = addr + 0x1000;
6961 for (; addr < limit; addr += 4, mem++) {
6962 if (*mem == 0x03e00008) // jr $ra
6963 return addr + 8;
57871462 6964 }
581335b0 6965 return addr;
03f55e6b 6966}
6967
6968struct savestate_block {
6969 uint32_t addr;
6970 uint32_t regflags;
6971};
6972
6973static int addr_cmp(const void *p1_, const void *p2_)
6974{
6975 const struct savestate_block *p1 = p1_, *p2 = p2_;
6976 return p1->addr - p2->addr;
6977}
6978
6979int new_dynarec_save_blocks(void *save, int size)
6980{
6981 struct savestate_block *blocks = save;
6982 int maxcount = size / sizeof(blocks[0]);
6983 struct savestate_block tmp_blocks[1024];
6984 struct ll_entry *head;
6985 int p, s, d, o, bcnt;
6986 u_int addr;
6987
6988 o = 0;
b14b6a8f 6989 for (p = 0; p < ARRAY_SIZE(jump_in); p++) {
03f55e6b 6990 bcnt = 0;
6991 for (head = jump_in[p]; head != NULL; head = head->next) {
6992 tmp_blocks[bcnt].addr = head->vaddr;
6993 tmp_blocks[bcnt].regflags = head->reg_sv_flags;
6994 bcnt++;
6995 }
6996 if (bcnt < 1)
6997 continue;
6998 qsort(tmp_blocks, bcnt, sizeof(tmp_blocks[0]), addr_cmp);
6999
7000 addr = tmp_blocks[0].addr;
7001 for (s = d = 0; s < bcnt; s++) {
7002 if (tmp_blocks[s].addr < addr)
7003 continue;
7004 if (d == 0 || tmp_blocks[d-1].addr != tmp_blocks[s].addr)
7005 tmp_blocks[d++] = tmp_blocks[s];
7006 addr = scan_for_ret(tmp_blocks[s].addr);
7007 }
7008
7009 if (o + d > maxcount)
7010 d = maxcount - o;
7011 memcpy(&blocks[o], tmp_blocks, d * sizeof(blocks[0]));
7012 o += d;
7013 }
7014
7015 return o * sizeof(blocks[0]);
7016}
7017
7018void new_dynarec_load_blocks(const void *save, int size)
7019{
7020 const struct savestate_block *blocks = save;
7021 int count = size / sizeof(blocks[0]);
7022 u_int regs_save[32];
7023 uint32_t f;
7024 int i, b;
7025
7026 get_addr(psxRegs.pc);
7027
7028 // change GPRs for speculation to at least partially work..
7029 memcpy(regs_save, &psxRegs.GPR, sizeof(regs_save));
7030 for (i = 1; i < 32; i++)
7031 psxRegs.GPR.r[i] = 0x80000000;
7032
7033 for (b = 0; b < count; b++) {
7034 for (f = blocks[b].regflags, i = 0; f; f >>= 1, i++) {
7035 if (f & 1)
7036 psxRegs.GPR.r[i] = 0x1f800000;
7037 }
7038
7039 get_addr(blocks[b].addr);
7040
7041 for (f = blocks[b].regflags, i = 0; f; f >>= 1, i++) {
7042 if (f & 1)
7043 psxRegs.GPR.r[i] = 0x80000000;
7044 }
7045 }
7046
7047 memcpy(&psxRegs.GPR, regs_save, sizeof(regs_save));
7048}
7049
7f94b097 7050static int apply_hacks(void)
24058131 7051{
7052 int i;
7053 if (HACK_ENABLED(NDHACK_NO_COMPAT_HACKS))
7f94b097 7054 return 0;
24058131 7055 /* special hack(s) */
7056 for (i = 0; i < slen - 4; i++)
7057 {
7058 // lui a4, 0xf200; jal <rcnt_read>; addu a0, 2; slti v0, 28224
7059 if (source[i] == 0x3c04f200 && dops[i+1].itype == UJUMP
7060 && source[i+2] == 0x34840002 && dops[i+3].opcode == 0x0a
7061 && imm[i+3] == 0x6e40 && dops[i+3].rs1 == 2)
7062 {
7063 SysPrintf("PE2 hack @%08x\n", start + (i+3)*4);
7064 dops[i + 3].itype = NOP;
7065 }
7066 }
7067 i = slen;
7068 if (i > 10 && source[i-1] == 0 && source[i-2] == 0x03e00008
7069 && source[i-4] == 0x8fbf0018 && source[i-6] == 0x00c0f809
7070 && dops[i-7].itype == STORE)
7071 {
7072 i = i-8;
7073 if (dops[i].itype == IMM16)
7074 i--;
7075 // swl r2, 15(r6); swr r2, 12(r6); sw r6, *; jalr r6
7076 if (dops[i].itype == STORELR && dops[i].rs1 == 6
7077 && dops[i-1].itype == STORELR && dops[i-1].rs1 == 6)
7078 {
7f94b097 7079 SysPrintf("F1 hack from %08x, old dst %08x\n", start, hack_addr);
7080 f1_hack = 1;
7081 return 1;
24058131 7082 }
7083 }
7f94b097 7084 return 0;
24058131 7085}
7086
3968e69e 7087int new_recompile_block(u_int addr)
03f55e6b 7088{
7089 u_int pagelimit = 0;
7090 u_int state_rflags = 0;
7091 int i;
7092
1a4301c4 7093 assem_debug("NOTCOMPILED: addr = %x -> %p\n", addr, out);
57871462 7094 //printf("TRACE: count=%d next=%d (compile %x)\n",Count,next_interupt,addr);
9f51b4b9 7095 //if(debug)
57871462 7096 //printf("fpu mapping=%x enabled=%x\n",(Status & 0x04000000)>>26,(Status & 0x20000000)>>29);
03f55e6b 7097
7098 // this is just for speculation
7099 for (i = 1; i < 32; i++) {
7100 if ((psxRegs.GPR.r[i] & 0xffff0000) == 0x1f800000)
7101 state_rflags |= 1 << i;
7102 }
7103
57871462 7104 start = (u_int)addr&~3;
7c3a5182 7105 //assert(((u_int)addr&1)==0); // start-in-delay-slot flag
2f546f9a 7106 new_dynarec_did_compile=1;
9ad4d757 7107 if (Config.HLE && start == 0x80001000) // hlecall
560e4a12 7108 {
7139f3c8 7109 // XXX: is this enough? Maybe check hleSoftCall?
d148d265 7110 void *beginning=start_block();
7139f3c8 7111 u_int page=get_page(start);
d148d265 7112
7139f3c8 7113 invalid_code[start>>12]=0;
7114 emit_movimm(start,0);
643aeae3 7115 emit_writeword(0,&pcaddr);
2a014d73 7116 emit_far_jump(new_dyna_leave);
15776b68 7117 literal_pool(0);
d148d265 7118 end_block(beginning);
03f55e6b 7119 ll_add_flags(jump_in+page,start,state_rflags,(void *)beginning);
7139f3c8 7120 return 0;
7121 }
7f94b097 7122 else if (f1_hack && hack_addr == 0) {
39b71d9a 7123 void *beginning = start_block();
7124 u_int page = get_page(start);
7f94b097 7125 emit_movimm(start, 0);
7126 emit_writeword(0, &hack_addr);
39b71d9a 7127 emit_readword(&psxRegs.GPR.n.sp, 0);
7128 emit_readptr(&mem_rtab, 1);
7129 emit_shrimm(0, 12, 2);
7130 emit_readptr_dualindexedx_ptrlen(1, 2, 1);
7131 emit_addimm(0, 0x18, 0);
7132 emit_adds_ptr(1, 1, 1);
7133 emit_ldr_dualindexed(1, 0, 0);
7134 emit_writeword(0, &psxRegs.GPR.r[26]); // lw k0, 0x18(sp)
7135 emit_far_call(get_addr_ht);
7136 emit_jmpreg(0); // jr k0
7137 literal_pool(0);
7138 end_block(beginning);
7139
7140 ll_add_flags(jump_in + page, start, state_rflags, beginning);
7141 SysPrintf("F1 hack to %08x\n", start);
39b71d9a 7142 return 0;
7143 }
03f55e6b 7144
24058131 7145 cycle_multiplier_active = cycle_multiplier_override && cycle_multiplier == CYCLE_MULT_DEFAULT
7146 ? cycle_multiplier_override : cycle_multiplier;
7147
03f55e6b 7148 source = get_source_start(start, &pagelimit);
7149 if (source == NULL) {
7150 SysPrintf("Compile at bogus memory address: %08x\n", addr);
7c3a5182 7151 abort();
57871462 7152 }
7153
7154 /* Pass 1: disassemble */
7155 /* Pass 2: register dependencies, branch targets */
7156 /* Pass 3: register allocation */
7157 /* Pass 4: branch dependencies */
7158 /* Pass 5: pre-alloc */
7159 /* Pass 6: optimize clean/dirty state */
7160 /* Pass 7: flag 32-bit registers */
7161 /* Pass 8: assembly */
7162 /* Pass 9: linker */
7163 /* Pass 10: garbage collection / free memory */
7164
03f55e6b 7165 int j;
57871462 7166 int done=0;
7167 unsigned int type,op,op2;
7168
7169 //printf("addr = %x source = %x %x\n", addr,source,source[0]);
9f51b4b9 7170
57871462 7171 /* Pass 1 disassembly */
7172
7ebfcedf 7173 for (i = 0; !done; i++)
7174 {
7175 memset(&dops[i], 0, sizeof(dops[i]));
cf95b4f0 7176 op2=0;
e1190b87 7177 minimum_free_regs[i]=0;
cf95b4f0 7178 dops[i].opcode=op=source[i]>>26;
57871462 7179 switch(op)
7180 {
7181 case 0x00: strcpy(insn[i],"special"); type=NI;
7182 op2=source[i]&0x3f;
7183 switch(op2)
7184 {
7185 case 0x00: strcpy(insn[i],"SLL"); type=SHIFTIMM; break;
7186 case 0x02: strcpy(insn[i],"SRL"); type=SHIFTIMM; break;
7187 case 0x03: strcpy(insn[i],"SRA"); type=SHIFTIMM; break;
7188 case 0x04: strcpy(insn[i],"SLLV"); type=SHIFT; break;
7189 case 0x06: strcpy(insn[i],"SRLV"); type=SHIFT; break;
7190 case 0x07: strcpy(insn[i],"SRAV"); type=SHIFT; break;
7191 case 0x08: strcpy(insn[i],"JR"); type=RJUMP; break;
7192 case 0x09: strcpy(insn[i],"JALR"); type=RJUMP; break;
7193 case 0x0C: strcpy(insn[i],"SYSCALL"); type=SYSCALL; break;
7194 case 0x0D: strcpy(insn[i],"BREAK"); type=OTHER; break;
7195 case 0x0F: strcpy(insn[i],"SYNC"); type=OTHER; break;
7196 case 0x10: strcpy(insn[i],"MFHI"); type=MOV; break;
7197 case 0x11: strcpy(insn[i],"MTHI"); type=MOV; break;
7198 case 0x12: strcpy(insn[i],"MFLO"); type=MOV; break;
7199 case 0x13: strcpy(insn[i],"MTLO"); type=MOV; break;
57871462 7200 case 0x18: strcpy(insn[i],"MULT"); type=MULTDIV; break;
7201 case 0x19: strcpy(insn[i],"MULTU"); type=MULTDIV; break;
7202 case 0x1A: strcpy(insn[i],"DIV"); type=MULTDIV; break;
7203 case 0x1B: strcpy(insn[i],"DIVU"); type=MULTDIV; break;
57871462 7204 case 0x20: strcpy(insn[i],"ADD"); type=ALU; break;
7205 case 0x21: strcpy(insn[i],"ADDU"); type=ALU; break;
7206 case 0x22: strcpy(insn[i],"SUB"); type=ALU; break;
7207 case 0x23: strcpy(insn[i],"SUBU"); type=ALU; break;
7208 case 0x24: strcpy(insn[i],"AND"); type=ALU; break;
7209 case 0x25: strcpy(insn[i],"OR"); type=ALU; break;
7210 case 0x26: strcpy(insn[i],"XOR"); type=ALU; break;
7211 case 0x27: strcpy(insn[i],"NOR"); type=ALU; break;
7212 case 0x2A: strcpy(insn[i],"SLT"); type=ALU; break;
7213 case 0x2B: strcpy(insn[i],"SLTU"); type=ALU; break;
57871462 7214 case 0x30: strcpy(insn[i],"TGE"); type=NI; break;
7215 case 0x31: strcpy(insn[i],"TGEU"); type=NI; break;
7216 case 0x32: strcpy(insn[i],"TLT"); type=NI; break;
7217 case 0x33: strcpy(insn[i],"TLTU"); type=NI; break;
7218 case 0x34: strcpy(insn[i],"TEQ"); type=NI; break;
7219 case 0x36: strcpy(insn[i],"TNE"); type=NI; break;
71e490c5 7220#if 0
7f2607ea 7221 case 0x14: strcpy(insn[i],"DSLLV"); type=SHIFT; break;
7222 case 0x16: strcpy(insn[i],"DSRLV"); type=SHIFT; break;
7223 case 0x17: strcpy(insn[i],"DSRAV"); type=SHIFT; break;
7224 case 0x1C: strcpy(insn[i],"DMULT"); type=MULTDIV; break;
7225 case 0x1D: strcpy(insn[i],"DMULTU"); type=MULTDIV; break;
7226 case 0x1E: strcpy(insn[i],"DDIV"); type=MULTDIV; break;
7227 case 0x1F: strcpy(insn[i],"DDIVU"); type=MULTDIV; break;
7228 case 0x2C: strcpy(insn[i],"DADD"); type=ALU; break;
7229 case 0x2D: strcpy(insn[i],"DADDU"); type=ALU; break;
7230 case 0x2E: strcpy(insn[i],"DSUB"); type=ALU; break;
7231 case 0x2F: strcpy(insn[i],"DSUBU"); type=ALU; break;
57871462 7232 case 0x38: strcpy(insn[i],"DSLL"); type=SHIFTIMM; break;
7233 case 0x3A: strcpy(insn[i],"DSRL"); type=SHIFTIMM; break;
7234 case 0x3B: strcpy(insn[i],"DSRA"); type=SHIFTIMM; break;
7235 case 0x3C: strcpy(insn[i],"DSLL32"); type=SHIFTIMM; break;
7236 case 0x3E: strcpy(insn[i],"DSRL32"); type=SHIFTIMM; break;
7237 case 0x3F: strcpy(insn[i],"DSRA32"); type=SHIFTIMM; break;
7f2607ea 7238#endif
57871462 7239 }
7240 break;
7241 case 0x01: strcpy(insn[i],"regimm"); type=NI;
7242 op2=(source[i]>>16)&0x1f;
7243 switch(op2)
7244 {
7245 case 0x00: strcpy(insn[i],"BLTZ"); type=SJUMP; break;
7246 case 0x01: strcpy(insn[i],"BGEZ"); type=SJUMP; break;
4919de1e 7247 //case 0x02: strcpy(insn[i],"BLTZL"); type=SJUMP; break;
7248 //case 0x03: strcpy(insn[i],"BGEZL"); type=SJUMP; break;
7249 //case 0x08: strcpy(insn[i],"TGEI"); type=NI; break;
7250 //case 0x09: strcpy(insn[i],"TGEIU"); type=NI; break;
7251 //case 0x0A: strcpy(insn[i],"TLTI"); type=NI; break;
7252 //case 0x0B: strcpy(insn[i],"TLTIU"); type=NI; break;
7253 //case 0x0C: strcpy(insn[i],"TEQI"); type=NI; break;
7254 //case 0x0E: strcpy(insn[i],"TNEI"); type=NI; break;
57871462 7255 case 0x10: strcpy(insn[i],"BLTZAL"); type=SJUMP; break;
7256 case 0x11: strcpy(insn[i],"BGEZAL"); type=SJUMP; break;
4919de1e 7257 //case 0x12: strcpy(insn[i],"BLTZALL"); type=SJUMP; break;
7258 //case 0x13: strcpy(insn[i],"BGEZALL"); type=SJUMP; break;
57871462 7259 }
7260 break;
7261 case 0x02: strcpy(insn[i],"J"); type=UJUMP; break;
7262 case 0x03: strcpy(insn[i],"JAL"); type=UJUMP; break;
7263 case 0x04: strcpy(insn[i],"BEQ"); type=CJUMP; break;
7264 case 0x05: strcpy(insn[i],"BNE"); type=CJUMP; break;
7265 case 0x06: strcpy(insn[i],"BLEZ"); type=CJUMP; break;
7266 case 0x07: strcpy(insn[i],"BGTZ"); type=CJUMP; break;
7267 case 0x08: strcpy(insn[i],"ADDI"); type=IMM16; break;
7268 case 0x09: strcpy(insn[i],"ADDIU"); type=IMM16; break;
7269 case 0x0A: strcpy(insn[i],"SLTI"); type=IMM16; break;
7270 case 0x0B: strcpy(insn[i],"SLTIU"); type=IMM16; break;
7271 case 0x0C: strcpy(insn[i],"ANDI"); type=IMM16; break;
7272 case 0x0D: strcpy(insn[i],"ORI"); type=IMM16; break;
7273 case 0x0E: strcpy(insn[i],"XORI"); type=IMM16; break;
7274 case 0x0F: strcpy(insn[i],"LUI"); type=IMM16; break;
7275 case 0x10: strcpy(insn[i],"cop0"); type=NI;
7276 op2=(source[i]>>21)&0x1f;
7277 switch(op2)
7278 {
7279 case 0x00: strcpy(insn[i],"MFC0"); type=COP0; break;
00fa9369 7280 case 0x02: strcpy(insn[i],"CFC0"); type=COP0; break;
57871462 7281 case 0x04: strcpy(insn[i],"MTC0"); type=COP0; break;
00fa9369 7282 case 0x06: strcpy(insn[i],"CTC0"); type=COP0; break;
7283 case 0x10: strcpy(insn[i],"RFE"); type=COP0; break;
57871462 7284 }
7285 break;
00fa9369 7286 case 0x11: strcpy(insn[i],"cop1"); type=COP1;
57871462 7287 op2=(source[i]>>21)&0x1f;
57871462 7288 break;
71e490c5 7289#if 0
57871462 7290 case 0x14: strcpy(insn[i],"BEQL"); type=CJUMP; break;
7291 case 0x15: strcpy(insn[i],"BNEL"); type=CJUMP; break;
7292 case 0x16: strcpy(insn[i],"BLEZL"); type=CJUMP; break;
7293 case 0x17: strcpy(insn[i],"BGTZL"); type=CJUMP; break;
7294 case 0x18: strcpy(insn[i],"DADDI"); type=IMM16; break;
7295 case 0x19: strcpy(insn[i],"DADDIU"); type=IMM16; break;
7296 case 0x1A: strcpy(insn[i],"LDL"); type=LOADLR; break;
7297 case 0x1B: strcpy(insn[i],"LDR"); type=LOADLR; break;
996cc15d 7298#endif
57871462 7299 case 0x20: strcpy(insn[i],"LB"); type=LOAD; break;
7300 case 0x21: strcpy(insn[i],"LH"); type=LOAD; break;
7301 case 0x22: strcpy(insn[i],"LWL"); type=LOADLR; break;
7302 case 0x23: strcpy(insn[i],"LW"); type=LOAD; break;
7303 case 0x24: strcpy(insn[i],"LBU"); type=LOAD; break;
7304 case 0x25: strcpy(insn[i],"LHU"); type=LOAD; break;
7305 case 0x26: strcpy(insn[i],"LWR"); type=LOADLR; break;
71e490c5 7306#if 0
57871462 7307 case 0x27: strcpy(insn[i],"LWU"); type=LOAD; break;
64bd6f82 7308#endif
57871462 7309 case 0x28: strcpy(insn[i],"SB"); type=STORE; break;
7310 case 0x29: strcpy(insn[i],"SH"); type=STORE; break;
7311 case 0x2A: strcpy(insn[i],"SWL"); type=STORELR; break;
7312 case 0x2B: strcpy(insn[i],"SW"); type=STORE; break;
71e490c5 7313#if 0
57871462 7314 case 0x2C: strcpy(insn[i],"SDL"); type=STORELR; break;
7315 case 0x2D: strcpy(insn[i],"SDR"); type=STORELR; break;
996cc15d 7316#endif
57871462 7317 case 0x2E: strcpy(insn[i],"SWR"); type=STORELR; break;
7318 case 0x2F: strcpy(insn[i],"CACHE"); type=NOP; break;
7319 case 0x30: strcpy(insn[i],"LL"); type=NI; break;
7320 case 0x31: strcpy(insn[i],"LWC1"); type=C1LS; break;
71e490c5 7321#if 0
57871462 7322 case 0x34: strcpy(insn[i],"LLD"); type=NI; break;
7323 case 0x35: strcpy(insn[i],"LDC1"); type=C1LS; break;
7324 case 0x37: strcpy(insn[i],"LD"); type=LOAD; break;
996cc15d 7325#endif
57871462 7326 case 0x38: strcpy(insn[i],"SC"); type=NI; break;
7327 case 0x39: strcpy(insn[i],"SWC1"); type=C1LS; break;
71e490c5 7328#if 0
57871462 7329 case 0x3C: strcpy(insn[i],"SCD"); type=NI; break;
7330 case 0x3D: strcpy(insn[i],"SDC1"); type=C1LS; break;
7331 case 0x3F: strcpy(insn[i],"SD"); type=STORE; break;
996cc15d 7332#endif
b9b61529 7333 case 0x12: strcpy(insn[i],"COP2"); type=NI;
7334 op2=(source[i]>>21)&0x1f;
be516ebe 7335 //if (op2 & 0x10)
bedfea38 7336 if (source[i]&0x3f) { // use this hack to support old savestates with patched gte insns
c7abc864 7337 if (gte_handlers[source[i]&0x3f]!=NULL) {
bedfea38 7338 if (gte_regnames[source[i]&0x3f]!=NULL)
7339 strcpy(insn[i],gte_regnames[source[i]&0x3f]);
7340 else
7341 snprintf(insn[i], sizeof(insn[i]), "COP2 %x", source[i]&0x3f);
c7abc864 7342 type=C2OP;
7343 }
7344 }
7345 else switch(op2)
b9b61529 7346 {
7347 case 0x00: strcpy(insn[i],"MFC2"); type=COP2; break;
7348 case 0x02: strcpy(insn[i],"CFC2"); type=COP2; break;
7349 case 0x04: strcpy(insn[i],"MTC2"); type=COP2; break;
7350 case 0x06: strcpy(insn[i],"CTC2"); type=COP2; break;
b9b61529 7351 }
7352 break;
7353 case 0x32: strcpy(insn[i],"LWC2"); type=C2LS; break;
7354 case 0x3A: strcpy(insn[i],"SWC2"); type=C2LS; break;
7355 case 0x3B: strcpy(insn[i],"HLECALL"); type=HLECALL; break;
90ae6d4e 7356 default: strcpy(insn[i],"???"); type=NI;
c43b5311 7357 SysPrintf("NI %08x @%08x (%08x)\n", source[i], addr + i*4, addr);
90ae6d4e 7358 break;
57871462 7359 }
cf95b4f0 7360 dops[i].itype=type;
7361 dops[i].opcode2=op2;
57871462 7362 /* Get registers/immediates */
cf95b4f0 7363 dops[i].lt1=0;
bedfea38 7364 gte_rs[i]=gte_rt[i]=0;
57871462 7365 switch(type) {
7366 case LOAD:
cf95b4f0 7367 dops[i].rs1=(source[i]>>21)&0x1f;
7368 dops[i].rs2=0;
7369 dops[i].rt1=(source[i]>>16)&0x1f;
7370 dops[i].rt2=0;
57871462 7371 imm[i]=(short)source[i];
7372 break;
7373 case STORE:
7374 case STORELR:
cf95b4f0 7375 dops[i].rs1=(source[i]>>21)&0x1f;
7376 dops[i].rs2=(source[i]>>16)&0x1f;
7377 dops[i].rt1=0;
7378 dops[i].rt2=0;
57871462 7379 imm[i]=(short)source[i];
57871462 7380 break;
7381 case LOADLR:
7382 // LWL/LWR only load part of the register,
7383 // therefore the target register must be treated as a source too
cf95b4f0 7384 dops[i].rs1=(source[i]>>21)&0x1f;
7385 dops[i].rs2=(source[i]>>16)&0x1f;
7386 dops[i].rt1=(source[i]>>16)&0x1f;
7387 dops[i].rt2=0;
57871462 7388 imm[i]=(short)source[i];
57871462 7389 break;
7390 case IMM16:
cf95b4f0 7391 if (op==0x0f) dops[i].rs1=0; // LUI instruction has no source register
7392 else dops[i].rs1=(source[i]>>21)&0x1f;
7393 dops[i].rs2=0;
7394 dops[i].rt1=(source[i]>>16)&0x1f;
7395 dops[i].rt2=0;
57871462 7396 if(op>=0x0c&&op<=0x0e) { // ANDI/ORI/XORI
7397 imm[i]=(unsigned short)source[i];
7398 }else{
7399 imm[i]=(short)source[i];
7400 }
57871462 7401 break;
7402 case UJUMP:
cf95b4f0 7403 dops[i].rs1=0;
7404 dops[i].rs2=0;
7405 dops[i].rt1=0;
7406 dops[i].rt2=0;
57871462 7407 // The JAL instruction writes to r31.
7408 if (op&1) {
cf95b4f0 7409 dops[i].rt1=31;
57871462 7410 }
cf95b4f0 7411 dops[i].rs2=CCREG;
57871462 7412 break;
7413 case RJUMP:
cf95b4f0 7414 dops[i].rs1=(source[i]>>21)&0x1f;
7415 dops[i].rs2=0;
7416 dops[i].rt1=0;
7417 dops[i].rt2=0;
5067f341 7418 // The JALR instruction writes to rd.
57871462 7419 if (op2&1) {
cf95b4f0 7420 dops[i].rt1=(source[i]>>11)&0x1f;
57871462 7421 }
cf95b4f0 7422 dops[i].rs2=CCREG;
57871462 7423 break;
7424 case CJUMP:
cf95b4f0 7425 dops[i].rs1=(source[i]>>21)&0x1f;
7426 dops[i].rs2=(source[i]>>16)&0x1f;
7427 dops[i].rt1=0;
7428 dops[i].rt2=0;
57871462 7429 if(op&2) { // BGTZ/BLEZ
cf95b4f0 7430 dops[i].rs2=0;
57871462 7431 }
57871462 7432 break;
7433 case SJUMP:
cf95b4f0 7434 dops[i].rs1=(source[i]>>21)&0x1f;
7435 dops[i].rs2=CCREG;
7436 dops[i].rt1=0;
7437 dops[i].rt2=0;
57871462 7438 if(op2&0x10) { // BxxAL
cf95b4f0 7439 dops[i].rt1=31;
57871462 7440 // NOTE: If the branch is not taken, r31 is still overwritten
7441 }
57871462 7442 break;
57871462 7443 case ALU:
cf95b4f0 7444 dops[i].rs1=(source[i]>>21)&0x1f; // source
7445 dops[i].rs2=(source[i]>>16)&0x1f; // subtract amount
7446 dops[i].rt1=(source[i]>>11)&0x1f; // destination
7447 dops[i].rt2=0;
57871462 7448 break;
7449 case MULTDIV:
cf95b4f0 7450 dops[i].rs1=(source[i]>>21)&0x1f; // source
7451 dops[i].rs2=(source[i]>>16)&0x1f; // divisor
7452 dops[i].rt1=HIREG;
7453 dops[i].rt2=LOREG;
57871462 7454 break;
7455 case MOV:
cf95b4f0 7456 dops[i].rs1=0;
7457 dops[i].rs2=0;
7458 dops[i].rt1=0;
7459 dops[i].rt2=0;
7460 if(op2==0x10) dops[i].rs1=HIREG; // MFHI
7461 if(op2==0x11) dops[i].rt1=HIREG; // MTHI
7462 if(op2==0x12) dops[i].rs1=LOREG; // MFLO
7463 if(op2==0x13) dops[i].rt1=LOREG; // MTLO
7464 if((op2&0x1d)==0x10) dops[i].rt1=(source[i]>>11)&0x1f; // MFxx
7465 if((op2&0x1d)==0x11) dops[i].rs1=(source[i]>>21)&0x1f; // MTxx
57871462 7466 break;
7467 case SHIFT:
cf95b4f0 7468 dops[i].rs1=(source[i]>>16)&0x1f; // target of shift
7469 dops[i].rs2=(source[i]>>21)&0x1f; // shift amount
7470 dops[i].rt1=(source[i]>>11)&0x1f; // destination
7471 dops[i].rt2=0;
57871462 7472 break;
7473 case SHIFTIMM:
cf95b4f0 7474 dops[i].rs1=(source[i]>>16)&0x1f;
7475 dops[i].rs2=0;
7476 dops[i].rt1=(source[i]>>11)&0x1f;
7477 dops[i].rt2=0;
57871462 7478 imm[i]=(source[i]>>6)&0x1f;
7479 // DSxx32 instructions
7480 if(op2>=0x3c) imm[i]|=0x20;
57871462 7481 break;
7482 case COP0:
cf95b4f0 7483 dops[i].rs1=0;
7484 dops[i].rs2=0;
7485 dops[i].rt1=0;
7486 dops[i].rt2=0;
7487 if(op2==0||op2==2) dops[i].rt1=(source[i]>>16)&0x1F; // MFC0/CFC0
7488 if(op2==4||op2==6) dops[i].rs1=(source[i]>>16)&0x1F; // MTC0/CTC0
7489 if(op2==4&&((source[i]>>11)&0x1f)==12) dops[i].rt2=CSREG; // Status
7490 if(op2==16) if((source[i]&0x3f)==0x18) dops[i].rs2=CCREG; // ERET
57871462 7491 break;
7492 case COP1:
cf95b4f0 7493 dops[i].rs1=0;
7494 dops[i].rs2=0;
7495 dops[i].rt1=0;
7496 dops[i].rt2=0;
7497 if(op2<3) dops[i].rt1=(source[i]>>16)&0x1F; // MFC1/DMFC1/CFC1
7498 if(op2>3) dops[i].rs1=(source[i]>>16)&0x1F; // MTC1/DMTC1/CTC1
7499 dops[i].rs2=CSREG;
57871462 7500 break;
bedfea38 7501 case COP2:
cf95b4f0 7502 dops[i].rs1=0;
7503 dops[i].rs2=0;
7504 dops[i].rt1=0;
7505 dops[i].rt2=0;
7506 if(op2<3) dops[i].rt1=(source[i]>>16)&0x1F; // MFC2/CFC2
7507 if(op2>3) dops[i].rs1=(source[i]>>16)&0x1F; // MTC2/CTC2
7508 dops[i].rs2=CSREG;
bedfea38 7509 int gr=(source[i]>>11)&0x1F;
7510 switch(op2)
7511 {
7512 case 0x00: gte_rs[i]=1ll<<gr; break; // MFC2
7513 case 0x04: gte_rt[i]=1ll<<gr; break; // MTC2
0ff8c62c 7514 case 0x02: gte_rs[i]=1ll<<(gr+32); break; // CFC2
bedfea38 7515 case 0x06: gte_rt[i]=1ll<<(gr+32); break; // CTC2
7516 }
7517 break;
57871462 7518 case C1LS:
cf95b4f0 7519 dops[i].rs1=(source[i]>>21)&0x1F;
7520 dops[i].rs2=CSREG;
7521 dops[i].rt1=0;
7522 dops[i].rt2=0;
57871462 7523 imm[i]=(short)source[i];
7524 break;
b9b61529 7525 case C2LS:
cf95b4f0 7526 dops[i].rs1=(source[i]>>21)&0x1F;
7527 dops[i].rs2=0;
7528 dops[i].rt1=0;
7529 dops[i].rt2=0;
b9b61529 7530 imm[i]=(short)source[i];
bedfea38 7531 if(op==0x32) gte_rt[i]=1ll<<((source[i]>>16)&0x1F); // LWC2
7532 else gte_rs[i]=1ll<<((source[i]>>16)&0x1F); // SWC2
7533 break;
7534 case C2OP:
cf95b4f0 7535 dops[i].rs1=0;
7536 dops[i].rs2=0;
7537 dops[i].rt1=0;
7538 dops[i].rt2=0;
2167bef6 7539 gte_rs[i]=gte_reg_reads[source[i]&0x3f];
7540 gte_rt[i]=gte_reg_writes[source[i]&0x3f];
7541 gte_rt[i]|=1ll<<63; // every op changes flags
587a5b1c 7542 if((source[i]&0x3f)==GTE_MVMVA) {
7543 int v = (source[i] >> 15) & 3;
7544 gte_rs[i]&=~0xe3fll;
7545 if(v==3) gte_rs[i]|=0xe00ll;
7546 else gte_rs[i]|=3ll<<(v*2);
7547 }
b9b61529 7548 break;
57871462 7549 case SYSCALL:
7139f3c8 7550 case HLECALL:
1e973cb0 7551 case INTCALL:
cf95b4f0 7552 dops[i].rs1=CCREG;
7553 dops[i].rs2=0;
7554 dops[i].rt1=0;
7555 dops[i].rt2=0;
57871462 7556 break;
7557 default:
cf95b4f0 7558 dops[i].rs1=0;
7559 dops[i].rs2=0;
7560 dops[i].rt1=0;
7561 dops[i].rt2=0;
57871462 7562 }
7563 /* Calculate branch target addresses */
7564 if(type==UJUMP)
7565 ba[i]=((start+i*4+4)&0xF0000000)|(((unsigned int)source[i]<<6)>>4);
cf95b4f0 7566 else if(type==CJUMP&&dops[i].rs1==dops[i].rs2&&(op&1))
57871462 7567 ba[i]=start+i*4+8; // Ignore never taken branch
cf95b4f0 7568 else if(type==SJUMP&&dops[i].rs1==0&&!(op2&1))
57871462 7569 ba[i]=start+i*4+8; // Ignore never taken branch
ad49de89 7570 else if(type==CJUMP||type==SJUMP)
57871462 7571 ba[i]=start+i*4+4+((signed int)((unsigned int)source[i]<<16)>>14);
7572 else ba[i]=-1;
4919de1e 7573
7574 /* simplify always (not)taken branches */
cf95b4f0 7575 if (type == CJUMP && dops[i].rs1 == dops[i].rs2) {
7576 dops[i].rs1 = dops[i].rs2 = 0;
4919de1e 7577 if (!(op & 1)) {
cf95b4f0 7578 dops[i].itype = type = UJUMP;
7579 dops[i].rs2 = CCREG;
4919de1e 7580 }
7581 }
cf95b4f0 7582 else if (type == SJUMP && dops[i].rs1 == 0 && (op2 & 1))
7583 dops[i].itype = type = UJUMP;
4919de1e 7584
fe807a8a 7585 dops[i].is_jump = (dops[i].itype == RJUMP || dops[i].itype == UJUMP || dops[i].itype == CJUMP || dops[i].itype == SJUMP);
7586 dops[i].is_ujump = (dops[i].itype == RJUMP || dops[i].itype == UJUMP); // || (source[i] >> 16) == 0x1000 // beq r0,r0
37387d8b 7587 dops[i].is_load = (dops[i].itype == LOAD || dops[i].itype == LOADLR || op == 0x32); // LWC2
7588 dops[i].is_store = (dops[i].itype == STORE || dops[i].itype == STORELR || op == 0x3a); // SWC2
fe807a8a 7589
4919de1e 7590 /* messy cases to just pass over to the interpreter */
fe807a8a 7591 if (i > 0 && dops[i-1].is_jump) {
3e535354 7592 int do_in_intrp=0;
7593 // branch in delay slot?
fe807a8a 7594 if (dops[i].is_jump) {
3e535354 7595 // don't handle first branch and call interpreter if it's hit
c43b5311 7596 SysPrintf("branch in delay slot @%08x (%08x)\n", addr + i*4, addr);
3e535354 7597 do_in_intrp=1;
7598 }
7599 // basic load delay detection
cf95b4f0 7600 else if((type==LOAD||type==LOADLR||type==COP0||type==COP2||type==C2LS)&&dops[i].rt1!=0) {
3e535354 7601 int t=(ba[i-1]-start)/4;
cf95b4f0 7602 if(0 <= t && t < i &&(dops[i].rt1==dops[t].rs1||dops[i].rt1==dops[t].rs2)&&dops[t].itype!=CJUMP&&dops[t].itype!=SJUMP) {
3e535354 7603 // jump target wants DS result - potential load delay effect
c43b5311 7604 SysPrintf("load delay @%08x (%08x)\n", addr + i*4, addr);
3e535354 7605 do_in_intrp=1;
cf95b4f0 7606 dops[t+1].bt=1; // expected return from interpreter
3e535354 7607 }
cf95b4f0 7608 else if(i>=2&&dops[i-2].rt1==2&&dops[i].rt1==2&&dops[i].rs1!=2&&dops[i].rs2!=2&&dops[i-1].rs1!=2&&dops[i-1].rs2!=2&&
fe807a8a 7609 !(i>=3&&dops[i-3].is_jump)) {
3e535354 7610 // v0 overwrite like this is a sign of trouble, bail out
c43b5311 7611 SysPrintf("v0 overwrite @%08x (%08x)\n", addr + i*4, addr);
3e535354 7612 do_in_intrp=1;
7613 }
7614 }
7ebfcedf 7615 if (do_in_intrp) {
7616 memset(&dops[i-1], 0, sizeof(dops[i-1]));
7617 dops[i-1].itype = INTCALL;
7618 dops[i-1].rs1 = CCREG;
7619 ba[i-1] = -1;
7620 done = 2;
3e535354 7621 i--; // don't compile the DS
26869094 7622 }
3e535354 7623 }
4919de1e 7624
3e535354 7625 /* Is this the end of the block? */
fe807a8a 7626 if (i > 0 && dops[i-1].is_ujump) {
cf95b4f0 7627 if(dops[i-1].rt1==0) { // Continue past subroutine call (JAL)
1e973cb0 7628 done=2;
57871462 7629 }
7630 else {
7631 if(stop_after_jal) done=1;
7632 // Stop on BREAK
7633 if((source[i+1]&0xfc00003f)==0x0d) done=1;
7634 }
7635 // Don't recompile stuff that's already compiled
7636 if(check_addr(start+i*4+4)) done=1;
7637 // Don't get too close to the limit
7638 if(i>MAXBLOCK/2) done=1;
7639 }
cf95b4f0 7640 if(dops[i].itype==SYSCALL&&stop_after_jal) done=1;
7641 if(dops[i].itype==HLECALL||dops[i].itype==INTCALL) done=2;
1e973cb0 7642 if(done==2) {
7643 // Does the block continue due to a branch?
7644 for(j=i-1;j>=0;j--)
7645 {
2a706964 7646 if(ba[j]==start+i*4) done=j=0; // Branch into delay slot
1e973cb0 7647 if(ba[j]==start+i*4+4) done=j=0;
7648 if(ba[j]==start+i*4+8) done=j=0;
7649 }
7650 }
75dec299 7651 //assert(i<MAXBLOCK-1);
57871462 7652 if(start+i*4==pagelimit-4) done=1;
7653 assert(start+i*4<pagelimit);
7654 if (i==MAXBLOCK-1) done=1;
7655 // Stop if we're compiling junk
cf95b4f0 7656 if(dops[i].itype==NI&&dops[i].opcode==0x11) {
57871462 7657 done=stop_after_jal=1;
c43b5311 7658 SysPrintf("Disabled speculative precompilation\n");
57871462 7659 }
7660 }
7661 slen=i;
fe807a8a 7662 if (dops[i-1].is_jump) {
57871462 7663 if(start+i*4==pagelimit) {
cf95b4f0 7664 dops[i-1].itype=SPAN;
57871462 7665 }
7666 }
7667 assert(slen>0);
7668
7f94b097 7669 int clear_hack_addr = apply_hacks();
39b71d9a 7670
57871462 7671 /* Pass 2 - Register dependencies and branch targets */
7672
7673 unneeded_registers(0,slen-1,0);
9f51b4b9 7674
57871462 7675 /* Pass 3 - Register allocation */
7676
7677 struct regstat current; // Current register allocations/status
57871462 7678 current.dirty=0;
7679 current.u=unneeded_reg[0];
57871462 7680 clear_all_regs(current.regmap);
7681 alloc_reg(&current,0,CCREG);
7682 dirty_reg(&current,CCREG);
7683 current.isconst=0;
7684 current.wasconst=0;
27727b63 7685 current.waswritten=0;
57871462 7686 int ds=0;
7687 int cc=0;
5194fb95 7688 int hr=-1;
6ebf4adf 7689
57871462 7690 if((u_int)addr&1) {
7691 // First instruction is delay slot
7692 cc=-1;
cf95b4f0 7693 dops[1].bt=1;
57871462 7694 ds=1;
7695 unneeded_reg[0]=1;
57871462 7696 current.regmap[HOST_BTREG]=BTREG;
7697 }
9f51b4b9 7698
57871462 7699 for(i=0;i<slen;i++)
7700 {
cf95b4f0 7701 if(dops[i].bt)
57871462 7702 {
7703 int hr;
7704 for(hr=0;hr<HOST_REGS;hr++)
7705 {
7706 // Is this really necessary?
7707 if(current.regmap[hr]==0) current.regmap[hr]=-1;
7708 }
7709 current.isconst=0;
27727b63 7710 current.waswritten=0;
57871462 7711 }
24385cae 7712
57871462 7713 memcpy(regmap_pre[i],current.regmap,sizeof(current.regmap));
7714 regs[i].wasconst=current.isconst;
57871462 7715 regs[i].wasdirty=current.dirty;
8575a877 7716 regs[i].loadedconst=0;
fe807a8a 7717 if (!dops[i].is_jump) {
57871462 7718 if(i+1<slen) {
cf95b4f0 7719 current.u=unneeded_reg[i+1]&~((1LL<<dops[i].rs1)|(1LL<<dops[i].rs2));
57871462 7720 current.u|=1;
57871462 7721 } else {
7722 current.u=1;
57871462 7723 }
7724 } else {
7725 if(i+1<slen) {
cf95b4f0 7726 current.u=branch_unneeded_reg[i]&~((1LL<<dops[i+1].rs1)|(1LL<<dops[i+1].rs2));
7727 current.u&=~((1LL<<dops[i].rs1)|(1LL<<dops[i].rs2));
57871462 7728 current.u|=1;
7ebfcedf 7729 } else {
7730 SysPrintf("oops, branch at end of block with no delay slot @%08x\n", start + i*4);
7731 abort();
7732 }
57871462 7733 }
cf95b4f0 7734 dops[i].is_ds=ds;
57871462 7735 if(ds) {
7736 ds=0; // Skip delay slot, already allocated as part of branch
7737 // ...but we need to alloc it in case something jumps here
7738 if(i+1<slen) {
7739 current.u=branch_unneeded_reg[i-1]&unneeded_reg[i+1];
57871462 7740 }else{
7741 current.u=branch_unneeded_reg[i-1];
57871462 7742 }
cf95b4f0 7743 current.u&=~((1LL<<dops[i].rs1)|(1LL<<dops[i].rs2));
57871462 7744 current.u|=1;
57871462 7745 struct regstat temp;
7746 memcpy(&temp,&current,sizeof(current));
7747 temp.wasdirty=temp.dirty;
57871462 7748 // TODO: Take into account unconditional branches, as below
7749 delayslot_alloc(&temp,i);
7750 memcpy(regs[i].regmap,temp.regmap,sizeof(temp.regmap));
7751 regs[i].wasdirty=temp.wasdirty;
57871462 7752 regs[i].dirty=temp.dirty;
57871462 7753 regs[i].isconst=0;
7754 regs[i].wasconst=0;
7755 current.isconst=0;
7756 // Create entry (branch target) regmap
7757 for(hr=0;hr<HOST_REGS;hr++)
7758 {
7759 int r=temp.regmap[hr];
7760 if(r>=0) {
7761 if(r!=regmap_pre[i][hr]) {
7762 regs[i].regmap_entry[hr]=-1;
7763 }
7764 else
7765 {
7c3a5182 7766 assert(r < 64);
57871462 7767 if((current.u>>r)&1) {
7768 regs[i].regmap_entry[hr]=-1;
7769 regs[i].regmap[hr]=-1;
7770 //Don't clear regs in the delay slot as the branch might need them
7771 //current.regmap[hr]=-1;
7772 }else
7773 regs[i].regmap_entry[hr]=r;
57871462 7774 }
7775 } else {
7776 // First instruction expects CCREG to be allocated
9f51b4b9 7777 if(i==0&&hr==HOST_CCREG)
57871462 7778 regs[i].regmap_entry[hr]=CCREG;
7779 else
7780 regs[i].regmap_entry[hr]=-1;
7781 }
7782 }
7783 }
7784 else { // Not delay slot
cf95b4f0 7785 switch(dops[i].itype) {
57871462 7786 case UJUMP:
7787 //current.isconst=0; // DEBUG
7788 //current.wasconst=0; // DEBUG
7789 //regs[i].wasconst=0; // DEBUG
cf95b4f0 7790 clear_const(&current,dops[i].rt1);
57871462 7791 alloc_cc(&current,i);
7792 dirty_reg(&current,CCREG);
cf95b4f0 7793 if (dops[i].rt1==31) {
57871462 7794 alloc_reg(&current,i,31);
7795 dirty_reg(&current,31);
cf95b4f0 7796 //assert(dops[i+1].rs1!=31&&dops[i+1].rs2!=31);
7797 //assert(dops[i+1].rt1!=dops[i].rt1);
57871462 7798 #ifdef REG_PREFETCH
7799 alloc_reg(&current,i,PTEMP);
7800 #endif
57871462 7801 }
cf95b4f0 7802 dops[i].ooo=1;
269bb29a 7803 delayslot_alloc(&current,i+1);
57871462 7804 //current.isconst=0; // DEBUG
7805 ds=1;
7806 //printf("i=%d, isconst=%x\n",i,current.isconst);
7807 break;
7808 case RJUMP:
7809 //current.isconst=0;
7810 //current.wasconst=0;
7811 //regs[i].wasconst=0;
cf95b4f0 7812 clear_const(&current,dops[i].rs1);
7813 clear_const(&current,dops[i].rt1);
57871462 7814 alloc_cc(&current,i);
7815 dirty_reg(&current,CCREG);
4919de1e 7816 if (!ds_writes_rjump_rs(i)) {
cf95b4f0 7817 alloc_reg(&current,i,dops[i].rs1);
7818 if (dops[i].rt1!=0) {
7819 alloc_reg(&current,i,dops[i].rt1);
7820 dirty_reg(&current,dops[i].rt1);
7821 assert(dops[i+1].rs1!=dops[i].rt1&&dops[i+1].rs2!=dops[i].rt1);
7822 assert(dops[i+1].rt1!=dops[i].rt1);
57871462 7823 #ifdef REG_PREFETCH
7824 alloc_reg(&current,i,PTEMP);
7825 #endif
7826 }
7827 #ifdef USE_MINI_HT
cf95b4f0 7828 if(dops[i].rs1==31) { // JALR
57871462 7829 alloc_reg(&current,i,RHASH);
57871462 7830 alloc_reg(&current,i,RHTBL);
57871462 7831 }
7832 #endif
7833 delayslot_alloc(&current,i+1);
7834 } else {
7835 // The delay slot overwrites our source register,
7836 // allocate a temporary register to hold the old value.
7837 current.isconst=0;
7838 current.wasconst=0;
7839 regs[i].wasconst=0;
7840 delayslot_alloc(&current,i+1);
7841 current.isconst=0;
7842 alloc_reg(&current,i,RTEMP);
7843 }
7844 //current.isconst=0; // DEBUG
cf95b4f0 7845 dops[i].ooo=1;
57871462 7846 ds=1;
7847 break;
7848 case CJUMP:
7849 //current.isconst=0;
7850 //current.wasconst=0;
7851 //regs[i].wasconst=0;
cf95b4f0 7852 clear_const(&current,dops[i].rs1);
7853 clear_const(&current,dops[i].rs2);
7854 if((dops[i].opcode&0x3E)==4) // BEQ/BNE
57871462 7855 {
7856 alloc_cc(&current,i);
7857 dirty_reg(&current,CCREG);
cf95b4f0 7858 if(dops[i].rs1) alloc_reg(&current,i,dops[i].rs1);
7859 if(dops[i].rs2) alloc_reg(&current,i,dops[i].rs2);
7860 if((dops[i].rs1&&(dops[i].rs1==dops[i+1].rt1||dops[i].rs1==dops[i+1].rt2))||
7861 (dops[i].rs2&&(dops[i].rs2==dops[i+1].rt1||dops[i].rs2==dops[i+1].rt2))) {
57871462 7862 // The delay slot overwrites one of our conditions.
7863 // Allocate the branch condition registers instead.
57871462 7864 current.isconst=0;
7865 current.wasconst=0;
7866 regs[i].wasconst=0;
cf95b4f0 7867 if(dops[i].rs1) alloc_reg(&current,i,dops[i].rs1);
7868 if(dops[i].rs2) alloc_reg(&current,i,dops[i].rs2);
57871462 7869 }
e1190b87 7870 else
7871 {
cf95b4f0 7872 dops[i].ooo=1;
e1190b87 7873 delayslot_alloc(&current,i+1);
7874 }
57871462 7875 }
7876 else
cf95b4f0 7877 if((dops[i].opcode&0x3E)==6) // BLEZ/BGTZ
57871462 7878 {
7879 alloc_cc(&current,i);
7880 dirty_reg(&current,CCREG);
cf95b4f0 7881 alloc_reg(&current,i,dops[i].rs1);
7882 if(dops[i].rs1&&(dops[i].rs1==dops[i+1].rt1||dops[i].rs1==dops[i+1].rt2)) {
57871462 7883 // The delay slot overwrites one of our conditions.
7884 // Allocate the branch condition registers instead.
57871462 7885 current.isconst=0;
7886 current.wasconst=0;
7887 regs[i].wasconst=0;
cf95b4f0 7888 if(dops[i].rs1) alloc_reg(&current,i,dops[i].rs1);
57871462 7889 }
e1190b87 7890 else
7891 {
cf95b4f0 7892 dops[i].ooo=1;
e1190b87 7893 delayslot_alloc(&current,i+1);
7894 }
57871462 7895 }
7896 else
7897 // Don't alloc the delay slot yet because we might not execute it
cf95b4f0 7898 if((dops[i].opcode&0x3E)==0x14) // BEQL/BNEL
57871462 7899 {
7900 current.isconst=0;
7901 current.wasconst=0;
7902 regs[i].wasconst=0;
7903 alloc_cc(&current,i);
7904 dirty_reg(&current,CCREG);
cf95b4f0 7905 alloc_reg(&current,i,dops[i].rs1);
7906 alloc_reg(&current,i,dops[i].rs2);
57871462 7907 }
7908 else
cf95b4f0 7909 if((dops[i].opcode&0x3E)==0x16) // BLEZL/BGTZL
57871462 7910 {
7911 current.isconst=0;
7912 current.wasconst=0;
7913 regs[i].wasconst=0;
7914 alloc_cc(&current,i);
7915 dirty_reg(&current,CCREG);
cf95b4f0 7916 alloc_reg(&current,i,dops[i].rs1);
57871462 7917 }
7918 ds=1;
7919 //current.isconst=0;
7920 break;
7921 case SJUMP:
7922 //current.isconst=0;
7923 //current.wasconst=0;
7924 //regs[i].wasconst=0;
cf95b4f0 7925 clear_const(&current,dops[i].rs1);
7926 clear_const(&current,dops[i].rt1);
7927 //if((dops[i].opcode2&0x1E)==0x0) // BLTZ/BGEZ
7928 if((dops[i].opcode2&0x0E)==0x0) // BLTZ/BGEZ
57871462 7929 {
7930 alloc_cc(&current,i);
7931 dirty_reg(&current,CCREG);
cf95b4f0 7932 alloc_reg(&current,i,dops[i].rs1);
7933 if (dops[i].rt1==31) { // BLTZAL/BGEZAL
57871462 7934 alloc_reg(&current,i,31);
7935 dirty_reg(&current,31);
57871462 7936 //#ifdef REG_PREFETCH
7937 //alloc_reg(&current,i,PTEMP);
7938 //#endif
57871462 7939 }
cf95b4f0 7940 if((dops[i].rs1&&(dops[i].rs1==dops[i+1].rt1||dops[i].rs1==dops[i+1].rt2)) // The delay slot overwrites the branch condition.
7941 ||(dops[i].rt1==31&&(dops[i+1].rs1==31||dops[i+1].rs2==31||dops[i+1].rt1==31||dops[i+1].rt2==31))) { // DS touches $ra
57871462 7942 // Allocate the branch condition registers instead.
57871462 7943 current.isconst=0;
7944 current.wasconst=0;
7945 regs[i].wasconst=0;
cf95b4f0 7946 if(dops[i].rs1) alloc_reg(&current,i,dops[i].rs1);
57871462 7947 }
e1190b87 7948 else
7949 {
cf95b4f0 7950 dops[i].ooo=1;
e1190b87 7951 delayslot_alloc(&current,i+1);
7952 }
57871462 7953 }
7954 else
7955 // Don't alloc the delay slot yet because we might not execute it
cf95b4f0 7956 if((dops[i].opcode2&0x1E)==0x2) // BLTZL/BGEZL
57871462 7957 {
7958 current.isconst=0;
7959 current.wasconst=0;
7960 regs[i].wasconst=0;
7961 alloc_cc(&current,i);
7962 dirty_reg(&current,CCREG);
cf95b4f0 7963 alloc_reg(&current,i,dops[i].rs1);
57871462 7964 }
7965 ds=1;
7966 //current.isconst=0;
7967 break;
57871462 7968 case IMM16:
7969 imm16_alloc(&current,i);
7970 break;
7971 case LOAD:
7972 case LOADLR:
7973 load_alloc(&current,i);
7974 break;
7975 case STORE:
7976 case STORELR:
7977 store_alloc(&current,i);
7978 break;
7979 case ALU:
7980 alu_alloc(&current,i);
7981 break;
7982 case SHIFT:
7983 shift_alloc(&current,i);
7984 break;
7985 case MULTDIV:
7986 multdiv_alloc(&current,i);
7987 break;
7988 case SHIFTIMM:
7989 shiftimm_alloc(&current,i);
7990 break;
7991 case MOV:
7992 mov_alloc(&current,i);
7993 break;
7994 case COP0:
7995 cop0_alloc(&current,i);
7996 break;
7997 case COP1:
81dbbf4c 7998 break;
b9b61529 7999 case COP2:
81dbbf4c 8000 cop2_alloc(&current,i);
57871462 8001 break;
8002 case C1LS:
8003 c1ls_alloc(&current,i);
8004 break;
b9b61529 8005 case C2LS:
8006 c2ls_alloc(&current,i);
8007 break;
8008 case C2OP:
8009 c2op_alloc(&current,i);
8010 break;
57871462 8011 case SYSCALL:
7139f3c8 8012 case HLECALL:
1e973cb0 8013 case INTCALL:
57871462 8014 syscall_alloc(&current,i);
8015 break;
8016 case SPAN:
8017 pagespan_alloc(&current,i);
8018 break;
8019 }
9f51b4b9 8020
57871462 8021 // Create entry (branch target) regmap
8022 for(hr=0;hr<HOST_REGS;hr++)
8023 {
581335b0 8024 int r,or;
57871462 8025 r=current.regmap[hr];
8026 if(r>=0) {
8027 if(r!=regmap_pre[i][hr]) {
8028 // TODO: delay slot (?)
8029 or=get_reg(regmap_pre[i],r); // Get old mapping for this register
8030 if(or<0||(r&63)>=TEMPREG){
8031 regs[i].regmap_entry[hr]=-1;
8032 }
8033 else
8034 {
8035 // Just move it to a different register
8036 regs[i].regmap_entry[hr]=r;
8037 // If it was dirty before, it's still dirty
8038 if((regs[i].wasdirty>>or)&1) dirty_reg(&current,r&63);
8039 }
8040 }
8041 else
8042 {
8043 // Unneeded
8044 if(r==0){
8045 regs[i].regmap_entry[hr]=0;
8046 }
8047 else
7c3a5182 8048 {
8049 assert(r<64);
57871462 8050 if((current.u>>r)&1) {
8051 regs[i].regmap_entry[hr]=-1;
8052 //regs[i].regmap[hr]=-1;
8053 current.regmap[hr]=-1;
8054 }else
8055 regs[i].regmap_entry[hr]=r;
8056 }
57871462 8057 }
8058 } else {
8059 // Branches expect CCREG to be allocated at the target
9f51b4b9 8060 if(regmap_pre[i][hr]==CCREG)
57871462 8061 regs[i].regmap_entry[hr]=CCREG;
8062 else
8063 regs[i].regmap_entry[hr]=-1;
8064 }
8065 }
8066 memcpy(regs[i].regmap,current.regmap,sizeof(current.regmap));
8067 }
27727b63 8068
cf95b4f0 8069 if(i>0&&(dops[i-1].itype==STORE||dops[i-1].itype==STORELR||(dops[i-1].itype==C2LS&&dops[i-1].opcode==0x3a))&&(u_int)imm[i-1]<0x800)
8070 current.waswritten|=1<<dops[i-1].rs1;
8071 current.waswritten&=~(1<<dops[i].rt1);
8072 current.waswritten&=~(1<<dops[i].rt2);
8073 if((dops[i].itype==STORE||dops[i].itype==STORELR||(dops[i].itype==C2LS&&dops[i].opcode==0x3a))&&(u_int)imm[i]>=0x800)
8074 current.waswritten&=~(1<<dops[i].rs1);
27727b63 8075
57871462 8076 /* Branch post-alloc */
8077 if(i>0)
8078 {
57871462 8079 current.wasdirty=current.dirty;
cf95b4f0 8080 switch(dops[i-1].itype) {
57871462 8081 case UJUMP:
8082 memcpy(&branch_regs[i-1],&current,sizeof(current));
8083 branch_regs[i-1].isconst=0;
8084 branch_regs[i-1].wasconst=0;
cf95b4f0 8085 branch_regs[i-1].u=branch_unneeded_reg[i-1]&~((1LL<<dops[i-1].rs1)|(1LL<<dops[i-1].rs2));
57871462 8086 alloc_cc(&branch_regs[i-1],i-1);
8087 dirty_reg(&branch_regs[i-1],CCREG);
cf95b4f0 8088 if(dops[i-1].rt1==31) { // JAL
57871462 8089 alloc_reg(&branch_regs[i-1],i-1,31);
8090 dirty_reg(&branch_regs[i-1],31);
57871462 8091 }
8092 memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
40fca85b 8093 memcpy(constmap[i],constmap[i-1],sizeof(constmap[i]));
57871462 8094 break;
8095 case RJUMP:
8096 memcpy(&branch_regs[i-1],&current,sizeof(current));
8097 branch_regs[i-1].isconst=0;
8098 branch_regs[i-1].wasconst=0;
cf95b4f0 8099 branch_regs[i-1].u=branch_unneeded_reg[i-1]&~((1LL<<dops[i-1].rs1)|(1LL<<dops[i-1].rs2));
57871462 8100 alloc_cc(&branch_regs[i-1],i-1);
8101 dirty_reg(&branch_regs[i-1],CCREG);
cf95b4f0 8102 alloc_reg(&branch_regs[i-1],i-1,dops[i-1].rs1);
8103 if(dops[i-1].rt1!=0) { // JALR
8104 alloc_reg(&branch_regs[i-1],i-1,dops[i-1].rt1);
8105 dirty_reg(&branch_regs[i-1],dops[i-1].rt1);
57871462 8106 }
8107 #ifdef USE_MINI_HT
cf95b4f0 8108 if(dops[i-1].rs1==31) { // JALR
57871462 8109 alloc_reg(&branch_regs[i-1],i-1,RHASH);
57871462 8110 alloc_reg(&branch_regs[i-1],i-1,RHTBL);
57871462 8111 }
8112 #endif
8113 memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
40fca85b 8114 memcpy(constmap[i],constmap[i-1],sizeof(constmap[i]));
57871462 8115 break;
8116 case CJUMP:
cf95b4f0 8117 if((dops[i-1].opcode&0x3E)==4) // BEQ/BNE
57871462 8118 {
8119 alloc_cc(&current,i-1);
8120 dirty_reg(&current,CCREG);
cf95b4f0 8121 if((dops[i-1].rs1&&(dops[i-1].rs1==dops[i].rt1||dops[i-1].rs1==dops[i].rt2))||
8122 (dops[i-1].rs2&&(dops[i-1].rs2==dops[i].rt1||dops[i-1].rs2==dops[i].rt2))) {
57871462 8123 // The delay slot overwrote one of our conditions
8124 // Delay slot goes after the test (in order)
cf95b4f0 8125 current.u=branch_unneeded_reg[i-1]&~((1LL<<dops[i].rs1)|(1LL<<dops[i].rs2));
57871462 8126 current.u|=1;
57871462 8127 delayslot_alloc(&current,i);
8128 current.isconst=0;
8129 }
8130 else
8131 {
cf95b4f0 8132 current.u=branch_unneeded_reg[i-1]&~((1LL<<dops[i-1].rs1)|(1LL<<dops[i-1].rs2));
57871462 8133 // Alloc the branch condition registers
cf95b4f0 8134 if(dops[i-1].rs1) alloc_reg(&current,i-1,dops[i-1].rs1);
8135 if(dops[i-1].rs2) alloc_reg(&current,i-1,dops[i-1].rs2);
57871462 8136 }
8137 memcpy(&branch_regs[i-1],&current,sizeof(current));
8138 branch_regs[i-1].isconst=0;
8139 branch_regs[i-1].wasconst=0;
8140 memcpy(&branch_regs[i-1].regmap_entry,&current.regmap,sizeof(current.regmap));
40fca85b 8141 memcpy(constmap[i],constmap[i-1],sizeof(constmap[i]));
57871462 8142 }
8143 else
cf95b4f0 8144 if((dops[i-1].opcode&0x3E)==6) // BLEZ/BGTZ
57871462 8145 {
8146 alloc_cc(&current,i-1);
8147 dirty_reg(&current,CCREG);
cf95b4f0 8148 if(dops[i-1].rs1==dops[i].rt1||dops[i-1].rs1==dops[i].rt2) {
57871462 8149 // The delay slot overwrote the branch condition
8150 // Delay slot goes after the test (in order)
cf95b4f0 8151 current.u=branch_unneeded_reg[i-1]&~((1LL<<dops[i].rs1)|(1LL<<dops[i].rs2));
57871462 8152 current.u|=1;
57871462 8153 delayslot_alloc(&current,i);
8154 current.isconst=0;
8155 }
8156 else
8157 {
cf95b4f0 8158 current.u=branch_unneeded_reg[i-1]&~(1LL<<dops[i-1].rs1);
57871462 8159 // Alloc the branch condition register
cf95b4f0 8160 alloc_reg(&current,i-1,dops[i-1].rs1);
57871462 8161 }
8162 memcpy(&branch_regs[i-1],&current,sizeof(current));
8163 branch_regs[i-1].isconst=0;
8164 branch_regs[i-1].wasconst=0;
8165 memcpy(&branch_regs[i-1].regmap_entry,&current.regmap,sizeof(current.regmap));
40fca85b 8166 memcpy(constmap[i],constmap[i-1],sizeof(constmap[i]));
57871462 8167 }
8168 else
8169 // Alloc the delay slot in case the branch is taken
cf95b4f0 8170 if((dops[i-1].opcode&0x3E)==0x14) // BEQL/BNEL
57871462 8171 {
8172 memcpy(&branch_regs[i-1],&current,sizeof(current));
cf95b4f0 8173 branch_regs[i-1].u=(branch_unneeded_reg[i-1]&~((1LL<<dops[i].rs1)|(1LL<<dops[i].rs2)|(1LL<<dops[i].rt1)|(1LL<<dops[i].rt2)))|1;
57871462 8174 alloc_cc(&branch_regs[i-1],i);
8175 dirty_reg(&branch_regs[i-1],CCREG);
8176 delayslot_alloc(&branch_regs[i-1],i);
8177 branch_regs[i-1].isconst=0;
8178 alloc_reg(&current,i,CCREG); // Not taken path
8179 dirty_reg(&current,CCREG);
8180 memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
8181 }
8182 else
cf95b4f0 8183 if((dops[i-1].opcode&0x3E)==0x16) // BLEZL/BGTZL
57871462 8184 {
8185 memcpy(&branch_regs[i-1],&current,sizeof(current));
cf95b4f0 8186 branch_regs[i-1].u=(branch_unneeded_reg[i-1]&~((1LL<<dops[i].rs1)|(1LL<<dops[i].rs2)|(1LL<<dops[i].rt1)|(1LL<<dops[i].rt2)))|1;
57871462 8187 alloc_cc(&branch_regs[i-1],i);
8188 dirty_reg(&branch_regs[i-1],CCREG);
8189 delayslot_alloc(&branch_regs[i-1],i);
8190 branch_regs[i-1].isconst=0;
8191 alloc_reg(&current,i,CCREG); // Not taken path
8192 dirty_reg(&current,CCREG);
8193 memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
8194 }
8195 break;
8196 case SJUMP:
cf95b4f0 8197 //if((dops[i-1].opcode2&0x1E)==0) // BLTZ/BGEZ
8198 if((dops[i-1].opcode2&0x0E)==0) // BLTZ/BGEZ
57871462 8199 {
8200 alloc_cc(&current,i-1);
8201 dirty_reg(&current,CCREG);
cf95b4f0 8202 if(dops[i-1].rs1==dops[i].rt1||dops[i-1].rs1==dops[i].rt2) {
57871462 8203 // The delay slot overwrote the branch condition
8204 // Delay slot goes after the test (in order)
cf95b4f0 8205 current.u=branch_unneeded_reg[i-1]&~((1LL<<dops[i].rs1)|(1LL<<dops[i].rs2));
57871462 8206 current.u|=1;
57871462 8207 delayslot_alloc(&current,i);
8208 current.isconst=0;
8209 }
8210 else
8211 {
cf95b4f0 8212 current.u=branch_unneeded_reg[i-1]&~(1LL<<dops[i-1].rs1);
57871462 8213 // Alloc the branch condition register
cf95b4f0 8214 alloc_reg(&current,i-1,dops[i-1].rs1);
57871462 8215 }
8216 memcpy(&branch_regs[i-1],&current,sizeof(current));
8217 branch_regs[i-1].isconst=0;
8218 branch_regs[i-1].wasconst=0;
8219 memcpy(&branch_regs[i-1].regmap_entry,&current.regmap,sizeof(current.regmap));
40fca85b 8220 memcpy(constmap[i],constmap[i-1],sizeof(constmap[i]));
57871462 8221 }
8222 else
8223 // Alloc the delay slot in case the branch is taken
cf95b4f0 8224 if((dops[i-1].opcode2&0x1E)==2) // BLTZL/BGEZL
57871462 8225 {
8226 memcpy(&branch_regs[i-1],&current,sizeof(current));
cf95b4f0 8227 branch_regs[i-1].u=(branch_unneeded_reg[i-1]&~((1LL<<dops[i].rs1)|(1LL<<dops[i].rs2)|(1LL<<dops[i].rt1)|(1LL<<dops[i].rt2)))|1;
57871462 8228 alloc_cc(&branch_regs[i-1],i);
8229 dirty_reg(&branch_regs[i-1],CCREG);
8230 delayslot_alloc(&branch_regs[i-1],i);
8231 branch_regs[i-1].isconst=0;
8232 alloc_reg(&current,i,CCREG); // Not taken path
8233 dirty_reg(&current,CCREG);
8234 memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
8235 }
8236 // FIXME: BLTZAL/BGEZAL
cf95b4f0 8237 if(dops[i-1].opcode2&0x10) { // BxxZAL
57871462 8238 alloc_reg(&branch_regs[i-1],i-1,31);
8239 dirty_reg(&branch_regs[i-1],31);
57871462 8240 }
8241 break;
57871462 8242 }
8243
fe807a8a 8244 if (dops[i-1].is_ujump)
57871462 8245 {
cf95b4f0 8246 if(dops[i-1].rt1==31) // JAL/JALR
57871462 8247 {
8248 // Subroutine call will return here, don't alloc any registers
57871462 8249 current.dirty=0;
8250 clear_all_regs(current.regmap);
8251 alloc_reg(&current,i,CCREG);
8252 dirty_reg(&current,CCREG);
8253 }
8254 else if(i+1<slen)
8255 {
8256 // Internal branch will jump here, match registers to caller
57871462 8257 current.dirty=0;
8258 clear_all_regs(current.regmap);
8259 alloc_reg(&current,i,CCREG);
8260 dirty_reg(&current,CCREG);
8261 for(j=i-1;j>=0;j--)
8262 {
8263 if(ba[j]==start+i*4+4) {
8264 memcpy(current.regmap,branch_regs[j].regmap,sizeof(current.regmap));
57871462 8265 current.dirty=branch_regs[j].dirty;
8266 break;
8267 }
8268 }
8269 while(j>=0) {
8270 if(ba[j]==start+i*4+4) {
8271 for(hr=0;hr<HOST_REGS;hr++) {
8272 if(current.regmap[hr]!=branch_regs[j].regmap[hr]) {
8273 current.regmap[hr]=-1;
8274 }
57871462 8275 current.dirty&=branch_regs[j].dirty;
8276 }
8277 }
8278 j--;
8279 }
8280 }
8281 }
8282 }
8283
8284 // Count cycles in between branches
2330734f 8285 ccadj[i] = CLOCK_ADJUST(cc);
fe807a8a 8286 if (i > 0 && (dops[i-1].is_jump || dops[i].itype == SYSCALL || dops[i].itype == HLECALL))
57871462 8287 {
8288 cc=0;
8289 }
71e490c5 8290#if !defined(DRC_DBG)
cf95b4f0 8291 else if(dops[i].itype==C2OP&&gte_cycletab[source[i]&0x3f]>2)
054175e9 8292 {
81dbbf4c 8293 // this should really be removed since the real stalls have been implemented,
8294 // but doing so causes sizeable perf regression against the older version
8295 u_int gtec = gte_cycletab[source[i] & 0x3f];
32631e6a 8296 cc += HACK_ENABLED(NDHACK_NO_STALLS) ? gtec/2 : 2;
fb407447 8297 }
cf95b4f0 8298 else if(i>1&&dops[i].itype==STORE&&dops[i-1].itype==STORE&&dops[i-2].itype==STORE&&!dops[i].bt)
5fdcbb5a 8299 {
8300 cc+=4;
8301 }
cf95b4f0 8302 else if(dops[i].itype==C2LS)
fb407447 8303 {
81dbbf4c 8304 // same as with C2OP
32631e6a 8305 cc += HACK_ENABLED(NDHACK_NO_STALLS) ? 4 : 2;
fb407447 8306 }
8307#endif
57871462 8308 else
8309 {
8310 cc++;
8311 }
8312
cf95b4f0 8313 if(!dops[i].is_ds) {
57871462 8314 regs[i].dirty=current.dirty;
8315 regs[i].isconst=current.isconst;
40fca85b 8316 memcpy(constmap[i],current_constmap,sizeof(constmap[i]));
57871462 8317 }
8318 for(hr=0;hr<HOST_REGS;hr++) {
8319 if(hr!=EXCLUDE_REG&&regs[i].regmap[hr]>=0) {
8320 if(regmap_pre[i][hr]!=regs[i].regmap[hr]) {
8321 regs[i].wasconst&=~(1<<hr);
8322 }
8323 }
8324 }
8325 if(current.regmap[HOST_BTREG]==BTREG) current.regmap[HOST_BTREG]=-1;
27727b63 8326 regs[i].waswritten=current.waswritten;
57871462 8327 }
9f51b4b9 8328
57871462 8329 /* Pass 4 - Cull unused host registers */
9f51b4b9 8330
57871462 8331 uint64_t nr=0;
9f51b4b9 8332
57871462 8333 for (i=slen-1;i>=0;i--)
8334 {
8335 int hr;
fe807a8a 8336 if(dops[i].is_jump)
57871462 8337 {
8338 if(ba[i]<start || ba[i]>=(start+slen*4))
8339 {
8340 // Branch out of this block, don't need anything
8341 nr=0;
8342 }
8343 else
8344 {
8345 // Internal branch
8346 // Need whatever matches the target
8347 nr=0;
8348 int t=(ba[i]-start)>>2;
8349 for(hr=0;hr<HOST_REGS;hr++)
8350 {
8351 if(regs[i].regmap_entry[hr]>=0) {
8352 if(regs[i].regmap_entry[hr]==regs[t].regmap_entry[hr]) nr|=1<<hr;
8353 }
8354 }
8355 }
8356 // Conditional branch may need registers for following instructions
fe807a8a 8357 if (!dops[i].is_ujump)
57871462 8358 {
8359 if(i<slen-2) {
8360 nr|=needed_reg[i+2];
8361 for(hr=0;hr<HOST_REGS;hr++)
8362 {
8363 if(regmap_pre[i+2][hr]>=0&&get_reg(regs[i+2].regmap_entry,regmap_pre[i+2][hr])<0) nr&=~(1<<hr);
8364 //if((regmap_entry[i+2][hr])>=0) if(!((nr>>hr)&1)) printf("%x-bogus(%d=%d)\n",start+i*4,hr,regmap_entry[i+2][hr]);
8365 }
8366 }
8367 }
8368 // Don't need stuff which is overwritten
f5955059 8369 //if(regs[i].regmap[hr]!=regmap_pre[i][hr]) nr&=~(1<<hr);
8370 //if(regs[i].regmap[hr]<0) nr&=~(1<<hr);
57871462 8371 // Merge in delay slot
8372 for(hr=0;hr<HOST_REGS;hr++)
8373 {
fe807a8a 8374 if(dops[i+1].rt1&&dops[i+1].rt1==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
8375 if(dops[i+1].rt2&&dops[i+1].rt2==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
cf95b4f0 8376 if(dops[i+1].rs1==regmap_pre[i][hr]) nr|=1<<hr;
8377 if(dops[i+1].rs2==regmap_pre[i][hr]) nr|=1<<hr;
8378 if(dops[i+1].rs1==regs[i].regmap_entry[hr]) nr|=1<<hr;
8379 if(dops[i+1].rs2==regs[i].regmap_entry[hr]) nr|=1<<hr;
37387d8b 8380 if(ram_offset && (dops[i+1].is_load || dops[i+1].is_store)) {
8381 if(regmap_pre[i][hr]==ROREG) nr|=1<<hr;
8382 if(regs[i].regmap_entry[hr]==ROREG) nr|=1<<hr;
8383 }
8384 if(dops[i+1].is_store) {
57871462 8385 if(regmap_pre[i][hr]==INVCP) nr|=1<<hr;
8386 if(regs[i].regmap_entry[hr]==INVCP) nr|=1<<hr;
8387 }
8388 }
8389 }
cf95b4f0 8390 else if(dops[i].itype==SYSCALL||dops[i].itype==HLECALL||dops[i].itype==INTCALL)
57871462 8391 {
8392 // SYSCALL instruction (software interrupt)
8393 nr=0;
8394 }
cf95b4f0 8395 else if(dops[i].itype==COP0 && (source[i]&0x3f)==0x18)
57871462 8396 {
8397 // ERET instruction (return from interrupt)
8398 nr=0;
8399 }
8400 else // Non-branch
8401 {
8402 if(i<slen-1) {
8403 for(hr=0;hr<HOST_REGS;hr++) {
8404 if(regmap_pre[i+1][hr]>=0&&get_reg(regs[i+1].regmap_entry,regmap_pre[i+1][hr])<0) nr&=~(1<<hr);
8405 if(regs[i].regmap[hr]!=regmap_pre[i+1][hr]) nr&=~(1<<hr);
8406 if(regs[i].regmap[hr]!=regmap_pre[i][hr]) nr&=~(1<<hr);
8407 if(regs[i].regmap[hr]<0) nr&=~(1<<hr);
8408 }
8409 }
8410 }
8411 for(hr=0;hr<HOST_REGS;hr++)
8412 {
8413 // Overwritten registers are not needed
cf95b4f0 8414 if(dops[i].rt1&&dops[i].rt1==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
8415 if(dops[i].rt2&&dops[i].rt2==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
57871462 8416 if(FTEMP==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
8417 // Source registers are needed
cf95b4f0 8418 if(dops[i].rs1==regmap_pre[i][hr]) nr|=1<<hr;
8419 if(dops[i].rs2==regmap_pre[i][hr]) nr|=1<<hr;
8420 if(dops[i].rs1==regs[i].regmap_entry[hr]) nr|=1<<hr;
8421 if(dops[i].rs2==regs[i].regmap_entry[hr]) nr|=1<<hr;
37387d8b 8422 if(ram_offset && (dops[i].is_load || dops[i].is_store)) {
8423 if(regmap_pre[i][hr]==ROREG) nr|=1<<hr;
8424 if(regs[i].regmap_entry[hr]==ROREG) nr|=1<<hr;
8425 }
8426 if(dops[i].is_store) {
57871462 8427 if(regmap_pre[i][hr]==INVCP) nr|=1<<hr;
8428 if(regs[i].regmap_entry[hr]==INVCP) nr|=1<<hr;
8429 }
8430 // Don't store a register immediately after writing it,
8431 // may prevent dual-issue.
8432 // But do so if this is a branch target, otherwise we
8433 // might have to load the register before the branch.
cf95b4f0 8434 if(i>0&&!dops[i].bt&&((regs[i].wasdirty>>hr)&1)) {
7c3a5182 8435 if((regmap_pre[i][hr]>0&&!((unneeded_reg[i]>>regmap_pre[i][hr])&1))) {
cf95b4f0 8436 if(dops[i-1].rt1==(regmap_pre[i][hr]&63)) nr|=1<<hr;
8437 if(dops[i-1].rt2==(regmap_pre[i][hr]&63)) nr|=1<<hr;
57871462 8438 }
7c3a5182 8439 if((regs[i].regmap_entry[hr]>0&&!((unneeded_reg[i]>>regs[i].regmap_entry[hr])&1))) {
cf95b4f0 8440 if(dops[i-1].rt1==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
8441 if(dops[i-1].rt2==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
57871462 8442 }
8443 }
8444 }
8445 // Cycle count is needed at branches. Assume it is needed at the target too.
cf95b4f0 8446 if(i==0||dops[i].bt||dops[i].itype==CJUMP||dops[i].itype==SPAN) {
57871462 8447 if(regmap_pre[i][HOST_CCREG]==CCREG) nr|=1<<HOST_CCREG;
8448 if(regs[i].regmap_entry[HOST_CCREG]==CCREG) nr|=1<<HOST_CCREG;
8449 }
8450 // Save it
8451 needed_reg[i]=nr;
9f51b4b9 8452
57871462 8453 // Deallocate unneeded registers
8454 for(hr=0;hr<HOST_REGS;hr++)
8455 {
8456 if(!((nr>>hr)&1)) {
8457 if(regs[i].regmap_entry[hr]!=CCREG) regs[i].regmap_entry[hr]=-1;
fe807a8a 8458 if(dops[i].is_jump)
57871462 8459 {
37387d8b 8460 int map1 = 0, map2 = 0, temp = 0; // or -1 ??
8461 if (dops[i+1].is_load || dops[i+1].is_store)
8462 map1 = ROREG;
8463 if (dops[i+1].is_store)
8464 map2 = INVCP;
8465 if(dops[i+1].itype==LOADLR || dops[i+1].itype==STORELR || dops[i+1].itype==C2LS)
8466 temp = FTEMP;
cf95b4f0 8467 if((regs[i].regmap[hr]&63)!=dops[i].rs1 && (regs[i].regmap[hr]&63)!=dops[i].rs2 &&
8468 (regs[i].regmap[hr]&63)!=dops[i].rt1 && (regs[i].regmap[hr]&63)!=dops[i].rt2 &&
8469 (regs[i].regmap[hr]&63)!=dops[i+1].rt1 && (regs[i].regmap[hr]&63)!=dops[i+1].rt2 &&
8470 regs[i].regmap[hr]!=dops[i+1].rs1 && regs[i].regmap[hr]!=dops[i+1].rs2 &&
57871462 8471 (regs[i].regmap[hr]&63)!=temp && regs[i].regmap[hr]!=PTEMP &&
8472 regs[i].regmap[hr]!=RHASH && regs[i].regmap[hr]!=RHTBL &&
8473 regs[i].regmap[hr]!=RTEMP && regs[i].regmap[hr]!=CCREG &&
37387d8b 8474 regs[i].regmap[hr]!=map1 && regs[i].regmap[hr]!=map2)
57871462 8475 {
8476 regs[i].regmap[hr]=-1;
8477 regs[i].isconst&=~(1<<hr);
cf95b4f0 8478 if((branch_regs[i].regmap[hr]&63)!=dops[i].rs1 && (branch_regs[i].regmap[hr]&63)!=dops[i].rs2 &&
8479 (branch_regs[i].regmap[hr]&63)!=dops[i].rt1 && (branch_regs[i].regmap[hr]&63)!=dops[i].rt2 &&
8480 (branch_regs[i].regmap[hr]&63)!=dops[i+1].rt1 && (branch_regs[i].regmap[hr]&63)!=dops[i+1].rt2 &&
8481 branch_regs[i].regmap[hr]!=dops[i+1].rs1 && branch_regs[i].regmap[hr]!=dops[i+1].rs2 &&
57871462 8482 (branch_regs[i].regmap[hr]&63)!=temp && branch_regs[i].regmap[hr]!=PTEMP &&
8483 branch_regs[i].regmap[hr]!=RHASH && branch_regs[i].regmap[hr]!=RHTBL &&
8484 branch_regs[i].regmap[hr]!=RTEMP && branch_regs[i].regmap[hr]!=CCREG &&
37387d8b 8485 branch_regs[i].regmap[hr]!=map1 && branch_regs[i].regmap[hr]!=map2)
57871462 8486 {
8487 branch_regs[i].regmap[hr]=-1;
8488 branch_regs[i].regmap_entry[hr]=-1;
fe807a8a 8489 if (!dops[i].is_ujump)
57871462 8490 {
fe807a8a 8491 if (i < slen-2) {
57871462 8492 regmap_pre[i+2][hr]=-1;
79c75f1b 8493 regs[i+2].wasconst&=~(1<<hr);
57871462 8494 }
8495 }
8496 }
8497 }
8498 }
8499 else
8500 {
8501 // Non-branch
8502 if(i>0)
8503 {
37387d8b 8504 int map1 = -1, map2 = -1, temp=-1;
8505 if (dops[i].is_load || dops[i].is_store)
8506 map1 = ROREG;
8507 if (dops[i].is_store)
8508 map2 = INVCP;
8509 if (dops[i].itype==LOADLR || dops[i].itype==STORELR || dops[i].itype==C2LS)
8510 temp = FTEMP;
cf95b4f0 8511 if((regs[i].regmap[hr]&63)!=dops[i].rt1 && (regs[i].regmap[hr]&63)!=dops[i].rt2 &&
8512 regs[i].regmap[hr]!=dops[i].rs1 && regs[i].regmap[hr]!=dops[i].rs2 &&
37387d8b 8513 (regs[i].regmap[hr]&63)!=temp && regs[i].regmap[hr]!=map1 && regs[i].regmap[hr]!=map2 &&
4b1c7cd1 8514 //(dops[i].itype!=SPAN||regs[i].regmap[hr]!=CCREG)
8515 regs[i].regmap[hr] != CCREG)
57871462 8516 {
cf95b4f0 8517 if(i<slen-1&&!dops[i].is_ds) {
ad49de89 8518 assert(regs[i].regmap[hr]<64);
afec9d44 8519 if(regmap_pre[i+1][hr]!=-1 || regs[i].regmap[hr]>0)
57871462 8520 if(regmap_pre[i+1][hr]!=regs[i].regmap[hr])
57871462 8521 {
c43b5311 8522 SysPrintf("fail: %x (%d %d!=%d)\n",start+i*4,hr,regmap_pre[i+1][hr],regs[i].regmap[hr]);
57871462 8523 assert(regmap_pre[i+1][hr]==regs[i].regmap[hr]);
8524 }
8525 regmap_pre[i+1][hr]=-1;
8526 if(regs[i+1].regmap_entry[hr]==CCREG) regs[i+1].regmap_entry[hr]=-1;
79c75f1b 8527 regs[i+1].wasconst&=~(1<<hr);
57871462 8528 }
8529 regs[i].regmap[hr]=-1;
8530 regs[i].isconst&=~(1<<hr);
8531 }
8532 }
8533 }
3968e69e 8534 } // if needed
8535 } // for hr
57871462 8536 }
9f51b4b9 8537
57871462 8538 /* Pass 5 - Pre-allocate registers */
9f51b4b9 8539
57871462 8540 // If a register is allocated during a loop, try to allocate it for the
8541 // entire loop, if possible. This avoids loading/storing registers
8542 // inside of the loop.
9f51b4b9 8543
57871462 8544 signed char f_regmap[HOST_REGS];
8545 clear_all_regs(f_regmap);
8546 for(i=0;i<slen-1;i++)
8547 {
cf95b4f0 8548 if(dops[i].itype==UJUMP||dops[i].itype==CJUMP||dops[i].itype==SJUMP)
57871462 8549 {
9f51b4b9 8550 if(ba[i]>=start && ba[i]<(start+i*4))
cf95b4f0 8551 if(dops[i+1].itype==NOP||dops[i+1].itype==MOV||dops[i+1].itype==ALU
8552 ||dops[i+1].itype==SHIFTIMM||dops[i+1].itype==IMM16||dops[i+1].itype==LOAD
8553 ||dops[i+1].itype==STORE||dops[i+1].itype==STORELR||dops[i+1].itype==C1LS
8554 ||dops[i+1].itype==SHIFT||dops[i+1].itype==COP1
8555 ||dops[i+1].itype==COP2||dops[i+1].itype==C2LS||dops[i+1].itype==C2OP)
57871462 8556 {
8557 int t=(ba[i]-start)>>2;
fe807a8a 8558 if(t > 0 && !dops[t-1].is_jump) // loop_preload can't handle jumps into delay slots
cf95b4f0 8559 if(t<2||(dops[t-2].itype!=UJUMP&&dops[t-2].itype!=RJUMP)||dops[t-2].rt1!=31) // call/ret assumes no registers allocated
57871462 8560 for(hr=0;hr<HOST_REGS;hr++)
8561 {
7c3a5182 8562 if(regs[i].regmap[hr]>=0) {
b372a952 8563 if(f_regmap[hr]!=regs[i].regmap[hr]) {
8564 // dealloc old register
8565 int n;
8566 for(n=0;n<HOST_REGS;n++)
8567 {
8568 if(f_regmap[n]==regs[i].regmap[hr]) {f_regmap[n]=-1;}
8569 }
8570 // and alloc new one
8571 f_regmap[hr]=regs[i].regmap[hr];
8572 }
8573 }
7c3a5182 8574 if(branch_regs[i].regmap[hr]>=0) {
b372a952 8575 if(f_regmap[hr]!=branch_regs[i].regmap[hr]) {
8576 // dealloc old register
8577 int n;
8578 for(n=0;n<HOST_REGS;n++)
8579 {
8580 if(f_regmap[n]==branch_regs[i].regmap[hr]) {f_regmap[n]=-1;}
8581 }
8582 // and alloc new one
8583 f_regmap[hr]=branch_regs[i].regmap[hr];
8584 }
8585 }
cf95b4f0 8586 if(dops[i].ooo) {
9f51b4b9 8587 if(count_free_regs(regs[i].regmap)<=minimum_free_regs[i+1])
e1190b87 8588 f_regmap[hr]=branch_regs[i].regmap[hr];
8589 }else{
9f51b4b9 8590 if(count_free_regs(branch_regs[i].regmap)<=minimum_free_regs[i+1])
57871462 8591 f_regmap[hr]=branch_regs[i].regmap[hr];
8592 }
8593 // Avoid dirty->clean transition
e1190b87 8594 #ifdef DESTRUCTIVE_WRITEBACK
57871462 8595 if(t>0) if(get_reg(regmap_pre[t],f_regmap[hr])>=0) if((regs[t].wasdirty>>get_reg(regmap_pre[t],f_regmap[hr]))&1) f_regmap[hr]=-1;
e1190b87 8596 #endif
8597 // This check is only strictly required in the DESTRUCTIVE_WRITEBACK
8598 // case above, however it's always a good idea. We can't hoist the
8599 // load if the register was already allocated, so there's no point
8600 // wasting time analyzing most of these cases. It only "succeeds"
8601 // when the mapping was different and the load can be replaced with
8602 // a mov, which is of negligible benefit. So such cases are
8603 // skipped below.
57871462 8604 if(f_regmap[hr]>0) {
198df76f 8605 if(regs[t].regmap[hr]==f_regmap[hr]||(regs[t].regmap_entry[hr]<0&&get_reg(regmap_pre[t],f_regmap[hr])<0)) {
57871462 8606 int r=f_regmap[hr];
8607 for(j=t;j<=i;j++)
8608 {
8609 //printf("Test %x -> %x, %x %d/%d\n",start+i*4,ba[i],start+j*4,hr,r);
8610 if(r<34&&((unneeded_reg[j]>>r)&1)) break;
00fa9369 8611 assert(r < 64);
57871462 8612 if(regs[j].regmap[hr]==f_regmap[hr]&&(f_regmap[hr]&63)<TEMPREG) {
8613 //printf("Hit %x -> %x, %x %d/%d\n",start+i*4,ba[i],start+j*4,hr,r);
8614 int k;
8615 if(regs[i].regmap[hr]==-1&&branch_regs[i].regmap[hr]==-1) {
8616 if(get_reg(regs[i+2].regmap,f_regmap[hr])>=0) break;
8617 if(r>63) {
8618 if(get_reg(regs[i].regmap,r&63)<0) break;
8619 if(get_reg(branch_regs[i].regmap,r&63)<0) break;
8620 }
8621 k=i;
8622 while(k>1&&regs[k-1].regmap[hr]==-1) {
e1190b87 8623 if(count_free_regs(regs[k-1].regmap)<=minimum_free_regs[k-1]) {
8624 //printf("no free regs for store %x\n",start+(k-1)*4);
8625 break;
57871462 8626 }
57871462 8627 if(get_reg(regs[k-1].regmap,f_regmap[hr])>=0) {
8628 //printf("no-match due to different register\n");
8629 break;
8630 }
fe807a8a 8631 if (dops[k-2].is_jump) {
57871462 8632 //printf("no-match due to branch\n");
8633 break;
8634 }
8635 // call/ret fast path assumes no registers allocated
cf95b4f0 8636 if(k>2&&(dops[k-3].itype==UJUMP||dops[k-3].itype==RJUMP)&&dops[k-3].rt1==31) {
57871462 8637 break;
8638 }
ad49de89 8639 assert(r < 64);
57871462 8640 k--;
8641 }
57871462 8642 if(regs[k-1].regmap[hr]==f_regmap[hr]&&regmap_pre[k][hr]==f_regmap[hr]) {
8643 //printf("Extend r%d, %x ->\n",hr,start+k*4);
8644 while(k<i) {
8645 regs[k].regmap_entry[hr]=f_regmap[hr];
8646 regs[k].regmap[hr]=f_regmap[hr];
8647 regmap_pre[k+1][hr]=f_regmap[hr];
8648 regs[k].wasdirty&=~(1<<hr);
8649 regs[k].dirty&=~(1<<hr);
8650 regs[k].wasdirty|=(1<<hr)&regs[k-1].dirty;
8651 regs[k].dirty|=(1<<hr)&regs[k].wasdirty;
8652 regs[k].wasconst&=~(1<<hr);
8653 regs[k].isconst&=~(1<<hr);
8654 k++;
8655 }
8656 }
8657 else {
8658 //printf("Fail Extend r%d, %x ->\n",hr,start+k*4);
8659 break;
8660 }
8661 assert(regs[i-1].regmap[hr]==f_regmap[hr]);
8662 if(regs[i-1].regmap[hr]==f_regmap[hr]&&regmap_pre[i][hr]==f_regmap[hr]) {
8663 //printf("OK fill %x (r%d)\n",start+i*4,hr);
8664 regs[i].regmap_entry[hr]=f_regmap[hr];
8665 regs[i].regmap[hr]=f_regmap[hr];
8666 regs[i].wasdirty&=~(1<<hr);
8667 regs[i].dirty&=~(1<<hr);
8668 regs[i].wasdirty|=(1<<hr)&regs[i-1].dirty;
8669 regs[i].dirty|=(1<<hr)&regs[i-1].dirty;
8670 regs[i].wasconst&=~(1<<hr);
8671 regs[i].isconst&=~(1<<hr);
8672 branch_regs[i].regmap_entry[hr]=f_regmap[hr];
8673 branch_regs[i].wasdirty&=~(1<<hr);
8674 branch_regs[i].wasdirty|=(1<<hr)&regs[i].dirty;
8675 branch_regs[i].regmap[hr]=f_regmap[hr];
8676 branch_regs[i].dirty&=~(1<<hr);
8677 branch_regs[i].dirty|=(1<<hr)&regs[i].dirty;
8678 branch_regs[i].wasconst&=~(1<<hr);
8679 branch_regs[i].isconst&=~(1<<hr);
fe807a8a 8680 if (!dops[i].is_ujump) {
57871462 8681 regmap_pre[i+2][hr]=f_regmap[hr];
8682 regs[i+2].wasdirty&=~(1<<hr);
8683 regs[i+2].wasdirty|=(1<<hr)&regs[i].dirty;
57871462 8684 }
8685 }
8686 }
8687 for(k=t;k<j;k++) {
e1190b87 8688 // Alloc register clean at beginning of loop,
8689 // but may dirty it in pass 6
57871462 8690 regs[k].regmap_entry[hr]=f_regmap[hr];
8691 regs[k].regmap[hr]=f_regmap[hr];
57871462 8692 regs[k].dirty&=~(1<<hr);
8693 regs[k].wasconst&=~(1<<hr);
8694 regs[k].isconst&=~(1<<hr);
fe807a8a 8695 if (dops[k].is_jump) {
e1190b87 8696 branch_regs[k].regmap_entry[hr]=f_regmap[hr];
8697 branch_regs[k].regmap[hr]=f_regmap[hr];
8698 branch_regs[k].dirty&=~(1<<hr);
8699 branch_regs[k].wasconst&=~(1<<hr);
8700 branch_regs[k].isconst&=~(1<<hr);
fe807a8a 8701 if (!dops[k].is_ujump) {
e1190b87 8702 regmap_pre[k+2][hr]=f_regmap[hr];
8703 regs[k+2].wasdirty&=~(1<<hr);
e1190b87 8704 }
8705 }
8706 else
8707 {
8708 regmap_pre[k+1][hr]=f_regmap[hr];
8709 regs[k+1].wasdirty&=~(1<<hr);
8710 }
57871462 8711 }
8712 if(regs[j].regmap[hr]==f_regmap[hr])
8713 regs[j].regmap_entry[hr]=f_regmap[hr];
8714 break;
8715 }
8716 if(j==i) break;
8717 if(regs[j].regmap[hr]>=0)
8718 break;
8719 if(get_reg(regs[j].regmap,f_regmap[hr])>=0) {
8720 //printf("no-match due to different register\n");
8721 break;
8722 }
fe807a8a 8723 if (dops[j].is_ujump)
e1190b87 8724 {
8725 // Stop on unconditional branch
8726 break;
8727 }
cf95b4f0 8728 if(dops[j].itype==CJUMP||dops[j].itype==SJUMP)
e1190b87 8729 {
cf95b4f0 8730 if(dops[j].ooo) {
9f51b4b9 8731 if(count_free_regs(regs[j].regmap)<=minimum_free_regs[j+1])
e1190b87 8732 break;
8733 }else{
9f51b4b9 8734 if(count_free_regs(branch_regs[j].regmap)<=minimum_free_regs[j+1])
e1190b87 8735 break;
8736 }
8737 if(get_reg(branch_regs[j].regmap,f_regmap[hr])>=0) {
8738 //printf("no-match due to different register (branch)\n");
57871462 8739 break;
8740 }
8741 }
e1190b87 8742 if(count_free_regs(regs[j].regmap)<=minimum_free_regs[j]) {
8743 //printf("No free regs for store %x\n",start+j*4);
8744 break;
8745 }
ad49de89 8746 assert(f_regmap[hr]<64);
57871462 8747 }
8748 }
8749 }
8750 }
8751 }
8752 }else{
198df76f 8753 // Non branch or undetermined branch target
57871462 8754 for(hr=0;hr<HOST_REGS;hr++)
8755 {
8756 if(hr!=EXCLUDE_REG) {
7c3a5182 8757 if(regs[i].regmap[hr]>=0) {
b372a952 8758 if(f_regmap[hr]!=regs[i].regmap[hr]) {
8759 // dealloc old register
8760 int n;
8761 for(n=0;n<HOST_REGS;n++)
8762 {
8763 if(f_regmap[n]==regs[i].regmap[hr]) {f_regmap[n]=-1;}
8764 }
8765 // and alloc new one
8766 f_regmap[hr]=regs[i].regmap[hr];
8767 }
8768 }
57871462 8769 }
8770 }
8771 // Try to restore cycle count at branch targets
cf95b4f0 8772 if(dops[i].bt) {
57871462 8773 for(j=i;j<slen-1;j++) {
8774 if(regs[j].regmap[HOST_CCREG]!=-1) break;
e1190b87 8775 if(count_free_regs(regs[j].regmap)<=minimum_free_regs[j]) {
8776 //printf("no free regs for store %x\n",start+j*4);
8777 break;
57871462 8778 }
57871462 8779 }
8780 if(regs[j].regmap[HOST_CCREG]==CCREG) {
8781 int k=i;
8782 //printf("Extend CC, %x -> %x\n",start+k*4,start+j*4);
8783 while(k<j) {
8784 regs[k].regmap_entry[HOST_CCREG]=CCREG;
8785 regs[k].regmap[HOST_CCREG]=CCREG;
8786 regmap_pre[k+1][HOST_CCREG]=CCREG;
8787 regs[k+1].wasdirty|=1<<HOST_CCREG;
8788 regs[k].dirty|=1<<HOST_CCREG;
8789 regs[k].wasconst&=~(1<<HOST_CCREG);
8790 regs[k].isconst&=~(1<<HOST_CCREG);
8791 k++;
8792 }
9f51b4b9 8793 regs[j].regmap_entry[HOST_CCREG]=CCREG;
57871462 8794 }
8795 // Work backwards from the branch target
8796 if(j>i&&f_regmap[HOST_CCREG]==CCREG)
8797 {
8798 //printf("Extend backwards\n");
8799 int k;
8800 k=i;
8801 while(regs[k-1].regmap[HOST_CCREG]==-1) {
e1190b87 8802 if(count_free_regs(regs[k-1].regmap)<=minimum_free_regs[k-1]) {
8803 //printf("no free regs for store %x\n",start+(k-1)*4);
8804 break;
57871462 8805 }
57871462 8806 k--;
8807 }
8808 if(regs[k-1].regmap[HOST_CCREG]==CCREG) {
8809 //printf("Extend CC, %x ->\n",start+k*4);
8810 while(k<=i) {
8811 regs[k].regmap_entry[HOST_CCREG]=CCREG;
8812 regs[k].regmap[HOST_CCREG]=CCREG;
8813 regmap_pre[k+1][HOST_CCREG]=CCREG;
8814 regs[k+1].wasdirty|=1<<HOST_CCREG;
8815 regs[k].dirty|=1<<HOST_CCREG;
8816 regs[k].wasconst&=~(1<<HOST_CCREG);
8817 regs[k].isconst&=~(1<<HOST_CCREG);
8818 k++;
8819 }
8820 }
8821 else {
8822 //printf("Fail Extend CC, %x ->\n",start+k*4);
8823 }
8824 }
8825 }
cf95b4f0 8826 if(dops[i].itype!=STORE&&dops[i].itype!=STORELR&&dops[i].itype!=C1LS&&dops[i].itype!=SHIFT&&
8827 dops[i].itype!=NOP&&dops[i].itype!=MOV&&dops[i].itype!=ALU&&dops[i].itype!=SHIFTIMM&&
8828 dops[i].itype!=IMM16&&dops[i].itype!=LOAD&&dops[i].itype!=COP1)
57871462 8829 {
8830 memcpy(f_regmap,regs[i].regmap,sizeof(f_regmap));
8831 }
8832 }
8833 }
9f51b4b9 8834
57871462 8835 // This allocates registers (if possible) one instruction prior
8836 // to use, which can avoid a load-use penalty on certain CPUs.
8837 for(i=0;i<slen-1;i++)
8838 {
fe807a8a 8839 if (!i || !dops[i-1].is_jump)
57871462 8840 {
cf95b4f0 8841 if(!dops[i+1].bt)
57871462 8842 {
cf95b4f0 8843 if(dops[i].itype==ALU||dops[i].itype==MOV||dops[i].itype==LOAD||dops[i].itype==SHIFTIMM||dops[i].itype==IMM16
8844 ||((dops[i].itype==COP1||dops[i].itype==COP2)&&dops[i].opcode2<3))
57871462 8845 {
cf95b4f0 8846 if(dops[i+1].rs1) {
8847 if((hr=get_reg(regs[i+1].regmap,dops[i+1].rs1))>=0)
57871462 8848 {
8849 if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
8850 {
8851 regs[i].regmap[hr]=regs[i+1].regmap[hr];
8852 regmap_pre[i+1][hr]=regs[i+1].regmap[hr];
8853 regs[i+1].regmap_entry[hr]=regs[i+1].regmap[hr];
8854 regs[i].isconst&=~(1<<hr);
8855 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
8856 constmap[i][hr]=constmap[i+1][hr];
8857 regs[i+1].wasdirty&=~(1<<hr);
8858 regs[i].dirty&=~(1<<hr);
8859 }
8860 }
8861 }
cf95b4f0 8862 if(dops[i+1].rs2) {
8863 if((hr=get_reg(regs[i+1].regmap,dops[i+1].rs2))>=0)
57871462 8864 {
8865 if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
8866 {
8867 regs[i].regmap[hr]=regs[i+1].regmap[hr];
8868 regmap_pre[i+1][hr]=regs[i+1].regmap[hr];
8869 regs[i+1].regmap_entry[hr]=regs[i+1].regmap[hr];
8870 regs[i].isconst&=~(1<<hr);
8871 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
8872 constmap[i][hr]=constmap[i+1][hr];
8873 regs[i+1].wasdirty&=~(1<<hr);
8874 regs[i].dirty&=~(1<<hr);
8875 }
8876 }
8877 }
198df76f 8878 // Preload target address for load instruction (non-constant)
cf95b4f0 8879 if(dops[i+1].itype==LOAD&&dops[i+1].rs1&&get_reg(regs[i+1].regmap,dops[i+1].rs1)<0) {
8880 if((hr=get_reg(regs[i+1].regmap,dops[i+1].rt1))>=0)
57871462 8881 {
8882 if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
8883 {
cf95b4f0 8884 regs[i].regmap[hr]=dops[i+1].rs1;
8885 regmap_pre[i+1][hr]=dops[i+1].rs1;
8886 regs[i+1].regmap_entry[hr]=dops[i+1].rs1;
57871462 8887 regs[i].isconst&=~(1<<hr);
8888 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
8889 constmap[i][hr]=constmap[i+1][hr];
8890 regs[i+1].wasdirty&=~(1<<hr);
8891 regs[i].dirty&=~(1<<hr);
8892 }
8893 }
8894 }
9f51b4b9 8895 // Load source into target register
cf95b4f0 8896 if(dops[i+1].lt1&&get_reg(regs[i+1].regmap,dops[i+1].rs1)<0) {
8897 if((hr=get_reg(regs[i+1].regmap,dops[i+1].rt1))>=0)
57871462 8898 {
8899 if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
8900 {
cf95b4f0 8901 regs[i].regmap[hr]=dops[i+1].rs1;
8902 regmap_pre[i+1][hr]=dops[i+1].rs1;
8903 regs[i+1].regmap_entry[hr]=dops[i+1].rs1;
57871462 8904 regs[i].isconst&=~(1<<hr);
8905 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
8906 constmap[i][hr]=constmap[i+1][hr];
8907 regs[i+1].wasdirty&=~(1<<hr);
8908 regs[i].dirty&=~(1<<hr);
8909 }
8910 }
8911 }
198df76f 8912 // Address for store instruction (non-constant)
cf95b4f0 8913 if(dops[i+1].itype==STORE||dops[i+1].itype==STORELR
8914 ||(dops[i+1].opcode&0x3b)==0x39||(dops[i+1].opcode&0x3b)==0x3a) { // SB/SH/SW/SD/SWC1/SDC1/SWC2/SDC2
8915 if(get_reg(regs[i+1].regmap,dops[i+1].rs1)<0) {
57871462 8916 hr=get_reg2(regs[i].regmap,regs[i+1].regmap,-1);
8917 if(hr<0) hr=get_reg(regs[i+1].regmap,-1);
8918 else {regs[i+1].regmap[hr]=AGEN1+((i+1)&1);regs[i+1].isconst&=~(1<<hr);}
8919 assert(hr>=0);
8920 if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
8921 {
cf95b4f0 8922 regs[i].regmap[hr]=dops[i+1].rs1;
8923 regmap_pre[i+1][hr]=dops[i+1].rs1;
8924 regs[i+1].regmap_entry[hr]=dops[i+1].rs1;
57871462 8925 regs[i].isconst&=~(1<<hr);
8926 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
8927 constmap[i][hr]=constmap[i+1][hr];
8928 regs[i+1].wasdirty&=~(1<<hr);
8929 regs[i].dirty&=~(1<<hr);
8930 }
8931 }
8932 }
cf95b4f0 8933 if(dops[i+1].itype==LOADLR||(dops[i+1].opcode&0x3b)==0x31||(dops[i+1].opcode&0x3b)==0x32) { // LWC1/LDC1, LWC2/LDC2
8934 if(get_reg(regs[i+1].regmap,dops[i+1].rs1)<0) {
57871462 8935 int nr;
8936 hr=get_reg(regs[i+1].regmap,FTEMP);
8937 assert(hr>=0);
8938 if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
8939 {
cf95b4f0 8940 regs[i].regmap[hr]=dops[i+1].rs1;
8941 regmap_pre[i+1][hr]=dops[i+1].rs1;
8942 regs[i+1].regmap_entry[hr]=dops[i+1].rs1;
57871462 8943 regs[i].isconst&=~(1<<hr);
8944 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
8945 constmap[i][hr]=constmap[i+1][hr];
8946 regs[i+1].wasdirty&=~(1<<hr);
8947 regs[i].dirty&=~(1<<hr);
8948 }
8949 else if((nr=get_reg2(regs[i].regmap,regs[i+1].regmap,-1))>=0)
8950 {
8951 // move it to another register
8952 regs[i+1].regmap[hr]=-1;
8953 regmap_pre[i+2][hr]=-1;
8954 regs[i+1].regmap[nr]=FTEMP;
8955 regmap_pre[i+2][nr]=FTEMP;
cf95b4f0 8956 regs[i].regmap[nr]=dops[i+1].rs1;
8957 regmap_pre[i+1][nr]=dops[i+1].rs1;
8958 regs[i+1].regmap_entry[nr]=dops[i+1].rs1;
57871462 8959 regs[i].isconst&=~(1<<nr);
8960 regs[i+1].isconst&=~(1<<nr);
8961 regs[i].dirty&=~(1<<nr);
8962 regs[i+1].wasdirty&=~(1<<nr);
8963 regs[i+1].dirty&=~(1<<nr);
8964 regs[i+2].wasdirty&=~(1<<nr);
8965 }
8966 }
8967 }
cf95b4f0 8968 if(dops[i+1].itype==LOAD||dops[i+1].itype==LOADLR||dops[i+1].itype==STORE||dops[i+1].itype==STORELR/*||dops[i+1].itype==C1LS||||dops[i+1].itype==C2LS*/) {
8969 if(dops[i+1].itype==LOAD)
8970 hr=get_reg(regs[i+1].regmap,dops[i+1].rt1);
8971 if(dops[i+1].itype==LOADLR||(dops[i+1].opcode&0x3b)==0x31||(dops[i+1].opcode&0x3b)==0x32) // LWC1/LDC1, LWC2/LDC2
57871462 8972 hr=get_reg(regs[i+1].regmap,FTEMP);
cf95b4f0 8973 if(dops[i+1].itype==STORE||dops[i+1].itype==STORELR||(dops[i+1].opcode&0x3b)==0x39||(dops[i+1].opcode&0x3b)==0x3a) { // SWC1/SDC1/SWC2/SDC2
57871462 8974 hr=get_reg(regs[i+1].regmap,AGEN1+((i+1)&1));
8975 if(hr<0) hr=get_reg(regs[i+1].regmap,-1);
8976 }
8977 if(hr>=0&&regs[i].regmap[hr]<0) {
cf95b4f0 8978 int rs=get_reg(regs[i+1].regmap,dops[i+1].rs1);
57871462 8979 if(rs>=0&&((regs[i+1].wasconst>>rs)&1)) {
8980 regs[i].regmap[hr]=AGEN1+((i+1)&1);
8981 regmap_pre[i+1][hr]=AGEN1+((i+1)&1);
8982 regs[i+1].regmap_entry[hr]=AGEN1+((i+1)&1);
8983 regs[i].isconst&=~(1<<hr);
8984 regs[i+1].wasdirty&=~(1<<hr);
8985 regs[i].dirty&=~(1<<hr);
8986 }
8987 }
8988 }
8989 }
8990 }
8991 }
8992 }
9f51b4b9 8993
57871462 8994 /* Pass 6 - Optimize clean/dirty state */
8995 clean_registers(0,slen-1,1);
9f51b4b9 8996
57871462 8997 /* Pass 7 - Identify 32-bit registers */
04fd948a 8998 for (i=slen-1;i>=0;i--)
8999 {
cf95b4f0 9000 if(dops[i].itype==CJUMP||dops[i].itype==SJUMP)
04fd948a 9001 {
9002 // Conditional branch
9003 if((source[i]>>16)!=0x1000&&i<slen-2) {
9004 // Mark this address as a branch target since it may be called
9005 // upon return from interrupt
cf95b4f0 9006 dops[i+2].bt=1;
04fd948a 9007 }
9008 }
9009 }
57871462 9010
cf95b4f0 9011 if(dops[slen-1].itype==SPAN) {
9012 dops[slen-1].bt=1; // Mark as a branch target so instruction can restart after exception
57871462 9013 }
4600ba03 9014
9015#ifdef DISASM
57871462 9016 /* Debug/disassembly */
57871462 9017 for(i=0;i<slen;i++)
9018 {
9019 printf("U:");
9020 int r;
9021 for(r=1;r<=CCREG;r++) {
9022 if((unneeded_reg[i]>>r)&1) {
9023 if(r==HIREG) printf(" HI");
9024 else if(r==LOREG) printf(" LO");
9025 else printf(" r%d",r);
9026 }
9027 }
57871462 9028 printf("\n");
9029 #if defined(__i386__) || defined(__x86_64__)
9030 printf("pre: eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",regmap_pre[i][0],regmap_pre[i][1],regmap_pre[i][2],regmap_pre[i][3],regmap_pre[i][5],regmap_pre[i][6],regmap_pre[i][7]);
9031 #endif
9032 #ifdef __arm__
9033 printf("pre: r0=%d r1=%d r2=%d r3=%d r4=%d r5=%d r6=%d r7=%d r8=%d r9=%d r10=%d r12=%d\n",regmap_pre[i][0],regmap_pre[i][1],regmap_pre[i][2],regmap_pre[i][3],regmap_pre[i][4],regmap_pre[i][5],regmap_pre[i][6],regmap_pre[i][7],regmap_pre[i][8],regmap_pre[i][9],regmap_pre[i][10],regmap_pre[i][12]);
9034 #endif
7c3a5182 9035 #if defined(__i386__) || defined(__x86_64__)
57871462 9036 printf("needs: ");
9037 if(needed_reg[i]&1) printf("eax ");
9038 if((needed_reg[i]>>1)&1) printf("ecx ");
9039 if((needed_reg[i]>>2)&1) printf("edx ");
9040 if((needed_reg[i]>>3)&1) printf("ebx ");
9041 if((needed_reg[i]>>5)&1) printf("ebp ");
9042 if((needed_reg[i]>>6)&1) printf("esi ");
9043 if((needed_reg[i]>>7)&1) printf("edi ");
57871462 9044 printf("\n");
57871462 9045 printf("entry: eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",regs[i].regmap_entry[0],regs[i].regmap_entry[1],regs[i].regmap_entry[2],regs[i].regmap_entry[3],regs[i].regmap_entry[5],regs[i].regmap_entry[6],regs[i].regmap_entry[7]);
9046 printf("dirty: ");
9047 if(regs[i].wasdirty&1) printf("eax ");
9048 if((regs[i].wasdirty>>1)&1) printf("ecx ");
9049 if((regs[i].wasdirty>>2)&1) printf("edx ");
9050 if((regs[i].wasdirty>>3)&1) printf("ebx ");
9051 if((regs[i].wasdirty>>5)&1) printf("ebp ");
9052 if((regs[i].wasdirty>>6)&1) printf("esi ");
9053 if((regs[i].wasdirty>>7)&1) printf("edi ");
9054 #endif
9055 #ifdef __arm__
9056 printf("entry: r0=%d r1=%d r2=%d r3=%d r4=%d r5=%d r6=%d r7=%d r8=%d r9=%d r10=%d r12=%d\n",regs[i].regmap_entry[0],regs[i].regmap_entry[1],regs[i].regmap_entry[2],regs[i].regmap_entry[3],regs[i].regmap_entry[4],regs[i].regmap_entry[5],regs[i].regmap_entry[6],regs[i].regmap_entry[7],regs[i].regmap_entry[8],regs[i].regmap_entry[9],regs[i].regmap_entry[10],regs[i].regmap_entry[12]);
9057 printf("dirty: ");
9058 if(regs[i].wasdirty&1) printf("r0 ");
9059 if((regs[i].wasdirty>>1)&1) printf("r1 ");
9060 if((regs[i].wasdirty>>2)&1) printf("r2 ");
9061 if((regs[i].wasdirty>>3)&1) printf("r3 ");
9062 if((regs[i].wasdirty>>4)&1) printf("r4 ");
9063 if((regs[i].wasdirty>>5)&1) printf("r5 ");
9064 if((regs[i].wasdirty>>6)&1) printf("r6 ");
9065 if((regs[i].wasdirty>>7)&1) printf("r7 ");
9066 if((regs[i].wasdirty>>8)&1) printf("r8 ");
9067 if((regs[i].wasdirty>>9)&1) printf("r9 ");
9068 if((regs[i].wasdirty>>10)&1) printf("r10 ");
9069 if((regs[i].wasdirty>>12)&1) printf("r12 ");
9070 #endif
9071 printf("\n");
9072 disassemble_inst(i);
9073 //printf ("ccadj[%d] = %d\n",i,ccadj[i]);
9074 #if defined(__i386__) || defined(__x86_64__)
9075 printf("eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d dirty: ",regs[i].regmap[0],regs[i].regmap[1],regs[i].regmap[2],regs[i].regmap[3],regs[i].regmap[5],regs[i].regmap[6],regs[i].regmap[7]);
9076 if(regs[i].dirty&1) printf("eax ");
9077 if((regs[i].dirty>>1)&1) printf("ecx ");
9078 if((regs[i].dirty>>2)&1) printf("edx ");
9079 if((regs[i].dirty>>3)&1) printf("ebx ");
9080 if((regs[i].dirty>>5)&1) printf("ebp ");
9081 if((regs[i].dirty>>6)&1) printf("esi ");
9082 if((regs[i].dirty>>7)&1) printf("edi ");
9083 #endif
9084 #ifdef __arm__
9085 printf("r0=%d r1=%d r2=%d r3=%d r4=%d r5=%d r6=%d r7=%d r8=%d r9=%d r10=%d r12=%d dirty: ",regs[i].regmap[0],regs[i].regmap[1],regs[i].regmap[2],regs[i].regmap[3],regs[i].regmap[4],regs[i].regmap[5],regs[i].regmap[6],regs[i].regmap[7],regs[i].regmap[8],regs[i].regmap[9],regs[i].regmap[10],regs[i].regmap[12]);
9086 if(regs[i].dirty&1) printf("r0 ");
9087 if((regs[i].dirty>>1)&1) printf("r1 ");
9088 if((regs[i].dirty>>2)&1) printf("r2 ");
9089 if((regs[i].dirty>>3)&1) printf("r3 ");
9090 if((regs[i].dirty>>4)&1) printf("r4 ");
9091 if((regs[i].dirty>>5)&1) printf("r5 ");
9092 if((regs[i].dirty>>6)&1) printf("r6 ");
9093 if((regs[i].dirty>>7)&1) printf("r7 ");
9094 if((regs[i].dirty>>8)&1) printf("r8 ");
9095 if((regs[i].dirty>>9)&1) printf("r9 ");
9096 if((regs[i].dirty>>10)&1) printf("r10 ");
9097 if((regs[i].dirty>>12)&1) printf("r12 ");
9098 #endif
9099 printf("\n");
9100 if(regs[i].isconst) {
9101 printf("constants: ");
9102 #if defined(__i386__) || defined(__x86_64__)
643aeae3 9103 if(regs[i].isconst&1) printf("eax=%x ",(u_int)constmap[i][0]);
9104 if((regs[i].isconst>>1)&1) printf("ecx=%x ",(u_int)constmap[i][1]);
9105 if((regs[i].isconst>>2)&1) printf("edx=%x ",(u_int)constmap[i][2]);
9106 if((regs[i].isconst>>3)&1) printf("ebx=%x ",(u_int)constmap[i][3]);
9107 if((regs[i].isconst>>5)&1) printf("ebp=%x ",(u_int)constmap[i][5]);
9108 if((regs[i].isconst>>6)&1) printf("esi=%x ",(u_int)constmap[i][6]);
9109 if((regs[i].isconst>>7)&1) printf("edi=%x ",(u_int)constmap[i][7]);
57871462 9110 #endif
7c3a5182 9111 #if defined(__arm__) || defined(__aarch64__)
643aeae3 9112 int r;
9113 for (r = 0; r < ARRAY_SIZE(constmap[i]); r++)
9114 if ((regs[i].isconst >> r) & 1)
9115 printf(" r%d=%x", r, (u_int)constmap[i][r]);
57871462 9116 #endif
9117 printf("\n");
9118 }
fe807a8a 9119 if(dops[i].is_jump) {
57871462 9120 #if defined(__i386__) || defined(__x86_64__)
9121 printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d dirty: ",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
9122 if(branch_regs[i].dirty&1) printf("eax ");
9123 if((branch_regs[i].dirty>>1)&1) printf("ecx ");
9124 if((branch_regs[i].dirty>>2)&1) printf("edx ");
9125 if((branch_regs[i].dirty>>3)&1) printf("ebx ");
9126 if((branch_regs[i].dirty>>5)&1) printf("ebp ");
9127 if((branch_regs[i].dirty>>6)&1) printf("esi ");
9128 if((branch_regs[i].dirty>>7)&1) printf("edi ");
9129 #endif
9130 #ifdef __arm__
9131 printf("branch(%d): r0=%d r1=%d r2=%d r3=%d r4=%d r5=%d r6=%d r7=%d r8=%d r9=%d r10=%d r12=%d dirty: ",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[4],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7],branch_regs[i].regmap[8],branch_regs[i].regmap[9],branch_regs[i].regmap[10],branch_regs[i].regmap[12]);
9132 if(branch_regs[i].dirty&1) printf("r0 ");
9133 if((branch_regs[i].dirty>>1)&1) printf("r1 ");
9134 if((branch_regs[i].dirty>>2)&1) printf("r2 ");
9135 if((branch_regs[i].dirty>>3)&1) printf("r3 ");
9136 if((branch_regs[i].dirty>>4)&1) printf("r4 ");
9137 if((branch_regs[i].dirty>>5)&1) printf("r5 ");
9138 if((branch_regs[i].dirty>>6)&1) printf("r6 ");
9139 if((branch_regs[i].dirty>>7)&1) printf("r7 ");
9140 if((branch_regs[i].dirty>>8)&1) printf("r8 ");
9141 if((branch_regs[i].dirty>>9)&1) printf("r9 ");
9142 if((branch_regs[i].dirty>>10)&1) printf("r10 ");
9143 if((branch_regs[i].dirty>>12)&1) printf("r12 ");
9144 #endif
57871462 9145 }
9146 }
4600ba03 9147#endif // DISASM
57871462 9148
9149 /* Pass 8 - Assembly */
9150 linkcount=0;stubcount=0;
9151 ds=0;is_delayslot=0;
57871462 9152 u_int dirty_pre=0;
d148d265 9153 void *beginning=start_block();
57871462 9154 if((u_int)addr&1) {
9155 ds=1;
9156 pagespan_ds();
9157 }
df4dc2b1 9158 void *instr_addr0_override = NULL;
9ad4d757 9159
9ad4d757 9160 if (start == 0x80030000) {
3968e69e 9161 // nasty hack for the fastbios thing
96186eba 9162 // override block entry to this code
df4dc2b1 9163 instr_addr0_override = out;
9ad4d757 9164 emit_movimm(start,0);
96186eba 9165 // abuse io address var as a flag that we
9166 // have already returned here once
643aeae3 9167 emit_readword(&address,1);
9168 emit_writeword(0,&pcaddr);
9169 emit_writeword(0,&address);
9ad4d757 9170 emit_cmp(0,1);
3968e69e 9171 #ifdef __aarch64__
9172 emit_jeq(out + 4*2);
2a014d73 9173 emit_far_jump(new_dyna_leave);
3968e69e 9174 #else
643aeae3 9175 emit_jne(new_dyna_leave);
3968e69e 9176 #endif
9ad4d757 9177 }
57871462 9178 for(i=0;i<slen;i++)
9179 {
9180 //if(ds) printf("ds: ");
4600ba03 9181 disassemble_inst(i);
57871462 9182 if(ds) {
9183 ds=0; // Skip delay slot
cf95b4f0 9184 if(dops[i].bt) assem_debug("OOPS - branch into delay slot\n");
df4dc2b1 9185 instr_addr[i] = NULL;
57871462 9186 } else {
ffb0b9e0 9187 speculate_register_values(i);
57871462 9188 #ifndef DESTRUCTIVE_WRITEBACK
fe807a8a 9189 if (i < 2 || !dops[i-2].is_ujump)
57871462 9190 {
ad49de89 9191 wb_valid(regmap_pre[i],regs[i].regmap_entry,dirty_pre,regs[i].wasdirty,unneeded_reg[i]);
57871462 9192 }
fe807a8a 9193 if((dops[i].itype==CJUMP||dops[i].itype==SJUMP)) {
f776eb14 9194 dirty_pre=branch_regs[i].dirty;
9195 }else{
f776eb14 9196 dirty_pre=regs[i].dirty;
9197 }
57871462 9198 #endif
9199 // write back
fe807a8a 9200 if (i < 2 || !dops[i-2].is_ujump)
57871462 9201 {
ad49de89 9202 wb_invalidate(regmap_pre[i],regs[i].regmap_entry,regs[i].wasdirty,unneeded_reg[i]);
57871462 9203 loop_preload(regmap_pre[i],regs[i].regmap_entry);
9204 }
9205 // branch target entry point
df4dc2b1 9206 instr_addr[i] = out;
57871462 9207 assem_debug("<->\n");
2330734f 9208 drc_dbg_emit_do_cmp(i, ccadj[i]);
7f94b097 9209 if (clear_hack_addr) {
9210 emit_movimm(0, 0);
9211 emit_writeword(0, &hack_addr);
9212 clear_hack_addr = 0;
9213 }
dd114d7d 9214
57871462 9215 // load regs
9216 if(regs[i].regmap_entry[HOST_CCREG]==CCREG&&regs[i].regmap[HOST_CCREG]!=CCREG)
ad49de89 9217 wb_register(CCREG,regs[i].regmap_entry,regs[i].wasdirty);
cf95b4f0 9218 load_regs(regs[i].regmap_entry,regs[i].regmap,dops[i].rs1,dops[i].rs2);
57871462 9219 address_generation(i,&regs[i],regs[i].regmap_entry);
ad49de89 9220 load_consts(regmap_pre[i],regs[i].regmap,i);
fe807a8a 9221 if(dops[i].is_jump)
57871462 9222 {
9223 // Load the delay slot registers if necessary
cf95b4f0 9224 if(dops[i+1].rs1!=dops[i].rs1&&dops[i+1].rs1!=dops[i].rs2&&(dops[i+1].rs1!=dops[i].rt1||dops[i].rt1==0))
9225 load_regs(regs[i].regmap_entry,regs[i].regmap,dops[i+1].rs1,dops[i+1].rs1);
9226 if(dops[i+1].rs2!=dops[i+1].rs1&&dops[i+1].rs2!=dops[i].rs1&&dops[i+1].rs2!=dops[i].rs2&&(dops[i+1].rs2!=dops[i].rt1||dops[i].rt1==0))
9227 load_regs(regs[i].regmap_entry,regs[i].regmap,dops[i+1].rs2,dops[i+1].rs2);
37387d8b 9228 if (ram_offset && (dops[i+1].is_load || dops[i+1].is_store))
9229 load_regs(regs[i].regmap_entry,regs[i].regmap,ROREG,ROREG);
9230 if (dops[i+1].is_store)
ad49de89 9231 load_regs(regs[i].regmap_entry,regs[i].regmap,INVCP,INVCP);
57871462 9232 }
9233 else if(i+1<slen)
9234 {
9235 // Preload registers for following instruction
cf95b4f0 9236 if(dops[i+1].rs1!=dops[i].rs1&&dops[i+1].rs1!=dops[i].rs2)
9237 if(dops[i+1].rs1!=dops[i].rt1&&dops[i+1].rs1!=dops[i].rt2)
9238 load_regs(regs[i].regmap_entry,regs[i].regmap,dops[i+1].rs1,dops[i+1].rs1);
9239 if(dops[i+1].rs2!=dops[i+1].rs1&&dops[i+1].rs2!=dops[i].rs1&&dops[i+1].rs2!=dops[i].rs2)
9240 if(dops[i+1].rs2!=dops[i].rt1&&dops[i+1].rs2!=dops[i].rt2)
9241 load_regs(regs[i].regmap_entry,regs[i].regmap,dops[i+1].rs2,dops[i+1].rs2);
57871462 9242 }
9243 // TODO: if(is_ooo(i)) address_generation(i+1);
9a3ccfeb 9244 if (!dops[i].is_jump || dops[i].itype == CJUMP)
ad49de89 9245 load_regs(regs[i].regmap_entry,regs[i].regmap,CCREG,CCREG);
37387d8b 9246 if (ram_offset && (dops[i].is_load || dops[i].is_store))
9247 load_regs(regs[i].regmap_entry,regs[i].regmap,ROREG,ROREG);
9248 if (dops[i].is_store)
ad49de89 9249 load_regs(regs[i].regmap_entry,regs[i].regmap,INVCP,INVCP);
2330734f 9250
9251 ds = assemble(i, &regs[i], ccadj[i]);
9252
fe807a8a 9253 if (dops[i].is_ujump)
57871462 9254 literal_pool(1024);
9255 else
9256 literal_pool_jumpover(256);
9257 }
9258 }
3d680478 9259
9260 assert(slen > 0);
cf95b4f0 9261 if (slen > 0 && dops[slen-1].itype == INTCALL) {
3d680478 9262 // no ending needed for this block since INTCALL never returns
9263 }
57871462 9264 // If the block did not end with an unconditional branch,
9265 // add a jump to the next instruction.
3d680478 9266 else if (i > 1) {
fe807a8a 9267 if (!dops[i-2].is_ujump && dops[i-1].itype != SPAN) {
9268 assert(!dops[i-1].is_jump);
57871462 9269 assert(i==slen);
cf95b4f0 9270 if(dops[i-2].itype!=CJUMP&&dops[i-2].itype!=SJUMP) {
ad49de89 9271 store_regs_bt(regs[i-1].regmap,regs[i-1].dirty,start+i*4);
57871462 9272 if(regs[i-1].regmap[HOST_CCREG]!=CCREG)
9273 emit_loadreg(CCREG,HOST_CCREG);
2330734f 9274 emit_addimm(HOST_CCREG, ccadj[i-1] + CLOCK_ADJUST(1), HOST_CCREG);
57871462 9275 }
fe807a8a 9276 else
57871462 9277 {
ad49de89 9278 store_regs_bt(branch_regs[i-2].regmap,branch_regs[i-2].dirty,start+i*4);
57871462 9279 assert(branch_regs[i-2].regmap[HOST_CCREG]==CCREG);
9280 }
643aeae3 9281 add_to_linker(out,start+i*4,0);
57871462 9282 emit_jmp(0);
9283 }
9284 }
9285 else
9286 {
9287 assert(i>0);
fe807a8a 9288 assert(!dops[i-1].is_jump);
ad49de89 9289 store_regs_bt(regs[i-1].regmap,regs[i-1].dirty,start+i*4);
57871462 9290 if(regs[i-1].regmap[HOST_CCREG]!=CCREG)
9291 emit_loadreg(CCREG,HOST_CCREG);
2330734f 9292 emit_addimm(HOST_CCREG, ccadj[i-1] + CLOCK_ADJUST(1), HOST_CCREG);
643aeae3 9293 add_to_linker(out,start+i*4,0);
57871462 9294 emit_jmp(0);
9295 }
9296
9297 // TODO: delay slot stubs?
9298 // Stubs
9299 for(i=0;i<stubcount;i++)
9300 {
b14b6a8f 9301 switch(stubs[i].type)
57871462 9302 {
9303 case LOADB_STUB:
9304 case LOADH_STUB:
9305 case LOADW_STUB:
9306 case LOADD_STUB:
9307 case LOADBU_STUB:
9308 case LOADHU_STUB:
9309 do_readstub(i);break;
9310 case STOREB_STUB:
9311 case STOREH_STUB:
9312 case STOREW_STUB:
9313 case STORED_STUB:
9314 do_writestub(i);break;
9315 case CC_STUB:
9316 do_ccstub(i);break;
9317 case INVCODE_STUB:
9318 do_invstub(i);break;
9319 case FP_STUB:
9320 do_cop1stub(i);break;
9321 case STORELR_STUB:
9322 do_unalignedwritestub(i);break;
9323 }
9324 }
9325
9ad4d757 9326 if (instr_addr0_override)
9327 instr_addr[0] = instr_addr0_override;
9328
57871462 9329 /* Pass 9 - Linker */
9330 for(i=0;i<linkcount;i++)
9331 {
643aeae3 9332 assem_debug("%p -> %8x\n",link_addr[i].addr,link_addr[i].target);
57871462 9333 literal_pool(64);
643aeae3 9334 if (!link_addr[i].ext)
57871462 9335 {
643aeae3 9336 void *stub = out;
9337 void *addr = check_addr(link_addr[i].target);
9338 emit_extjump(link_addr[i].addr, link_addr[i].target);
9339 if (addr) {
9340 set_jump_target(link_addr[i].addr, addr);
3d680478 9341 add_jump_out(link_addr[i].target,stub);
57871462 9342 }
643aeae3 9343 else
9344 set_jump_target(link_addr[i].addr, stub);
57871462 9345 }
9346 else
9347 {
9348 // Internal branch
643aeae3 9349 int target=(link_addr[i].target-start)>>2;
57871462 9350 assert(target>=0&&target<slen);
9351 assert(instr_addr[target]);
9352 //#ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
643aeae3 9353 //set_jump_target_fillslot(link_addr[i].addr,instr_addr[target],link_addr[i].ext>>1);
57871462 9354 //#else
643aeae3 9355 set_jump_target(link_addr[i].addr, instr_addr[target]);
57871462 9356 //#endif
9357 }
9358 }
3d680478 9359
9360 u_int source_len = slen*4;
cf95b4f0 9361 if (dops[slen-1].itype == INTCALL && source_len > 4)
3d680478 9362 // no need to treat the last instruction as compiled
9363 // as interpreter fully handles it
9364 source_len -= 4;
9365
9366 if ((u_char *)copy + source_len > (u_char *)shadow + sizeof(shadow))
9367 copy = shadow;
9368
57871462 9369 // External Branch Targets (jump_in)
57871462 9370 for(i=0;i<slen;i++)
9371 {
cf95b4f0 9372 if(dops[i].bt||i==0)
57871462 9373 {
9374 if(instr_addr[i]) // TODO - delay slots (=null)
9375 {
9376 u_int vaddr=start+i*4;
94d23bb9 9377 u_int page=get_page(vaddr);
9378 u_int vpage=get_vpage(vaddr);
57871462 9379 literal_pool(256);
57871462 9380 {
df4dc2b1 9381 assem_debug("%p (%d) <- %8x\n",instr_addr[i],i,start+i*4);
57871462 9382 assem_debug("jump_in: %x\n",start+i*4);
df4dc2b1 9383 ll_add(jump_dirty+vpage,vaddr,out);
3d680478 9384 void *entry_point = do_dirty_stub(i, source_len);
df4dc2b1 9385 ll_add_flags(jump_in+page,vaddr,state_rflags,entry_point);
57871462 9386 // If there was an existing entry in the hash table,
9387 // replace it with the new address.
9388 // Don't add new entries. We'll insert the
9389 // ones that actually get used in check_addr().
df4dc2b1 9390 struct ht_entry *ht_bin = hash_table_get(vaddr);
9391 if (ht_bin->vaddr[0] == vaddr)
9392 ht_bin->tcaddr[0] = entry_point;
9393 if (ht_bin->vaddr[1] == vaddr)
9394 ht_bin->tcaddr[1] = entry_point;
57871462 9395 }
57871462 9396 }
9397 }
9398 }
9399 // Write out the literal pool if necessary
9400 literal_pool(0);
9401 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
9402 // Align code
9403 if(((u_int)out)&7) emit_addnop(13);
9404 #endif
01d26796 9405 assert(out - (u_char *)beginning < MAX_OUTPUT_BLOCK_SIZE);
643aeae3 9406 //printf("shadow buffer: %p-%p\n",copy,(u_char *)copy+slen*4);
3d680478 9407 memcpy(copy, source, source_len);
9408 copy += source_len;
9f51b4b9 9409
d148d265 9410 end_block(beginning);
9f51b4b9 9411
57871462 9412 // If we're within 256K of the end of the buffer,
9413 // start over from the beginning. (Is 256K enough?)
2a014d73 9414 if (out > ndrc->translation_cache + sizeof(ndrc->translation_cache) - MAX_OUTPUT_BLOCK_SIZE)
9415 out = ndrc->translation_cache;
9f51b4b9 9416
57871462 9417 // Trap writes to any of the pages we compiled
9418 for(i=start>>12;i<=(start+slen*4)>>12;i++) {
9419 invalid_code[i]=0;
57871462 9420 }
9be4ba64 9421 inv_code_start=inv_code_end=~0;
71e490c5 9422
b96d3df7 9423 // for PCSX we need to mark all mirrors too
b12c9fb8 9424 if(get_page(start)<(RAM_SIZE>>12))
9425 for(i=start>>12;i<=(start+slen*4)>>12;i++)
b96d3df7 9426 invalid_code[((u_int)0x00000000>>12)|(i&0x1ff)]=
9427 invalid_code[((u_int)0x80000000>>12)|(i&0x1ff)]=
9428 invalid_code[((u_int)0xa0000000>>12)|(i&0x1ff)]=0;
9f51b4b9 9429
57871462 9430 /* Pass 10 - Free memory by expiring oldest blocks */
9f51b4b9 9431
2a014d73 9432 int end=(((out-ndrc->translation_cache)>>(TARGET_SIZE_2-16))+16384)&65535;
57871462 9433 while(expirep!=end)
9434 {
9435 int shift=TARGET_SIZE_2-3; // Divide into 8 blocks
943f42f3 9436 uintptr_t base_offs = ((uintptr_t)(expirep >> 13) << shift); // Base offset of this block
9437 uintptr_t base_offs_s = base_offs >> shift;
57871462 9438 inv_debug("EXP: Phase %d\n",expirep);
9439 switch((expirep>>11)&3)
9440 {
9441 case 0:
9442 // Clear jump_in and jump_dirty
943f42f3 9443 ll_remove_matching_addrs(jump_in+(expirep&2047),base_offs_s,shift);
9444 ll_remove_matching_addrs(jump_dirty+(expirep&2047),base_offs_s,shift);
9445 ll_remove_matching_addrs(jump_in+2048+(expirep&2047),base_offs_s,shift);
9446 ll_remove_matching_addrs(jump_dirty+2048+(expirep&2047),base_offs_s,shift);
57871462 9447 break;
9448 case 1:
9449 // Clear pointers
943f42f3 9450 ll_kill_pointers(jump_out[expirep&2047],base_offs_s,shift);
9451 ll_kill_pointers(jump_out[(expirep&2047)+2048],base_offs_s,shift);
57871462 9452 break;
9453 case 2:
9454 // Clear hash table
9455 for(i=0;i<32;i++) {
df4dc2b1 9456 struct ht_entry *ht_bin = &hash_table[((expirep&2047)<<5)+i];
943f42f3 9457 uintptr_t o1 = (u_char *)ht_bin->tcaddr[1] - ndrc->translation_cache;
9458 uintptr_t o2 = o1 - MAX_OUTPUT_BLOCK_SIZE;
9459 if ((o1 >> shift) == base_offs_s || (o2 >> shift) == base_offs_s) {
df4dc2b1 9460 inv_debug("EXP: Remove hash %x -> %p\n",ht_bin->vaddr[1],ht_bin->tcaddr[1]);
9461 ht_bin->vaddr[1] = -1;
9462 ht_bin->tcaddr[1] = NULL;
9463 }
943f42f3 9464 o1 = (u_char *)ht_bin->tcaddr[0] - ndrc->translation_cache;
9465 o2 = o1 - MAX_OUTPUT_BLOCK_SIZE;
9466 if ((o1 >> shift) == base_offs_s || (o2 >> shift) == base_offs_s) {
df4dc2b1 9467 inv_debug("EXP: Remove hash %x -> %p\n",ht_bin->vaddr[0],ht_bin->tcaddr[0]);
9468 ht_bin->vaddr[0] = ht_bin->vaddr[1];
9469 ht_bin->tcaddr[0] = ht_bin->tcaddr[1];
9470 ht_bin->vaddr[1] = -1;
9471 ht_bin->tcaddr[1] = NULL;
57871462 9472 }
9473 }
9474 break;
9475 case 3:
9476 // Clear jump_out
9f51b4b9 9477 if((expirep&2047)==0)
dd3a91a1 9478 do_clear_cache();
943f42f3 9479 ll_remove_matching_addrs(jump_out+(expirep&2047),base_offs_s,shift);
9480 ll_remove_matching_addrs(jump_out+2048+(expirep&2047),base_offs_s,shift);
57871462 9481 break;
9482 }
9483 expirep=(expirep+1)&65535;
9484 }
37387d8b 9485#ifdef ASSEM_PRINT
9486 fflush(stdout);
9487#endif
57871462 9488 return 0;
9489}
b9b61529 9490
9491// vim:shiftwidth=2:expandtab
ARM optimized PCSX fork