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32x: handle FEN quirk
[picodrive.git] / pico / pico_int.h
CommitLineData
cff531af 1/*\r
2 * PicoDrive - Internal Header File\r
3 * (c) Copyright Dave, 2004\r
4 * (C) notaz, 2006-2010\r
5 *\r
6 * This work is licensed under the terms of MAME license.\r
7 * See COPYING file in the top-level directory.\r
8 */\r
cc68a136 9\r
eff55556 10#ifndef PICO_INTERNAL_INCLUDED\r
11#define PICO_INTERNAL_INCLUDED\r
cc68a136 12\r
13#include <stdio.h>\r
14#include <stdlib.h>\r
15#include <string.h>\r
efcba75f 16#include "pico.h"\r
f53f286a 17#include "carthw/carthw.h"\r
cc68a136 18\r
89fa852d 19//\r
20#define USE_POLL_DETECT\r
21\r
eff55556 22#ifndef PICO_INTERNAL\r
23#define PICO_INTERNAL\r
24#endif\r
25#ifndef PICO_INTERNAL_ASM\r
26#define PICO_INTERNAL_ASM\r
27#endif\r
cc68a136 28\r
70357ce5 29// to select core, define EMU_C68K, EMU_M68K or EMU_F68K in your makefile or project\r
cc68a136 30\r
31#ifdef __cplusplus\r
32extern "C" {\r
33#endif\r
34\r
35\r
36// ----------------------- 68000 CPU -----------------------\r
37#ifdef EMU_C68K\r
d4d62665 38#include "../cpu/cyclone/Cyclone.h"\r
3aa1e148 39extern struct Cyclone PicoCpuCM68k, PicoCpuCS68k;\r
40#define SekCyclesLeftNoMCD PicoCpuCM68k.cycles // cycles left for this run\r
7336a99a 41#define SekCyclesLeft \\r
602133e1 42 (((PicoAHW&1) && (PicoOpt & POPT_EN_MCD_PSYNC)) ? (SekCycleAim-SekCycleCnt) : SekCyclesLeftNoMCD)\r
7a1f6e45 43#define SekCyclesLeftS68k \\r
602133e1 44 ((PicoOpt & POPT_EN_MCD_PSYNC) ? (SekCycleAimS68k-SekCycleCntS68k) : PicoCpuCS68k.cycles)\r
ef090115 45#define SekEndTimeslice(after) PicoCpuCM68k.cycles=after\r
07ceafdb 46#define SekEndTimesliceS68k(after) PicoCpuCS68k.cycles=after\r
3aa1e148 47#define SekPc (PicoCpuCM68k.pc-PicoCpuCM68k.membase)\r
48#define SekPcS68k (PicoCpuCS68k.pc-PicoCpuCS68k.membase)\r
12da51c2 49#define SekDar(x) (x < 8 ? PicoCpuCM68k.d[x] : PicoCpuCM68k.a[x - 8])\r
50#define SekDarS68k(x) (x < 8 ? PicoCpuCS68k.d[x] : PicoCpuCS68k.a[x - 8])\r
5fadfb1c 51#define SekSr CycloneGetSr(&PicoCpuCM68k)\r
12da51c2 52#define SekSrS68k CycloneGetSr(&PicoCpuCS68k)\r
3aa1e148 53#define SekSetStop(x) { PicoCpuCM68k.state_flags&=~1; if (x) { PicoCpuCM68k.state_flags|=1; PicoCpuCM68k.cycles=0; } }\r
54#define SekSetStopS68k(x) { PicoCpuCS68k.state_flags&=~1; if (x) { PicoCpuCS68k.state_flags|=1; PicoCpuCS68k.cycles=0; } }\r
ed4402a7 55#define SekIsStoppedM68k() (PicoCpuCM68k.state_flags&1)\r
ca61ee42 56#define SekIsStoppedS68k() (PicoCpuCS68k.state_flags&1)\r
03e4f2a3 57#define SekShouldInterrupt (PicoCpuCM68k.irq > (PicoCpuCM68k.srh&7))\r
b542be46 58\r
59#define SekInterrupt(i) PicoCpuCM68k.irq=i\r
5fadfb1c 60#define SekIrqLevel PicoCpuCM68k.irq\r
b542be46 61\r
03e4f2a3 62#ifdef EMU_M68K\r
63#define EMU_CORE_DEBUG\r
64#endif\r
cc68a136 65#endif\r
66\r
70357ce5 67#ifdef EMU_F68K\r
68#include "../cpu/fame/fame.h"\r
b542be46 69extern M68K_CONTEXT PicoCpuFM68k, PicoCpuFS68k;\r
3aa1e148 70#define SekCyclesLeftNoMCD PicoCpuFM68k.io_cycle_counter\r
70357ce5 71#define SekCyclesLeft \\r
602133e1 72 (((PicoAHW&1) && (PicoOpt & POPT_EN_MCD_PSYNC)) ? (SekCycleAim-SekCycleCnt) : SekCyclesLeftNoMCD)\r
70357ce5 73#define SekCyclesLeftS68k \\r
602133e1 74 ((PicoOpt & POPT_EN_MCD_PSYNC) ? (SekCycleAimS68k-SekCycleCntS68k) : PicoCpuFS68k.io_cycle_counter)\r
ef090115 75#define SekEndTimeslice(after) PicoCpuFM68k.io_cycle_counter=after\r
07ceafdb 76#define SekEndTimesliceS68k(after) PicoCpuFS68k.io_cycle_counter=after\r
03e4f2a3 77#define SekPc fm68k_get_pc(&PicoCpuFM68k)\r
78#define SekPcS68k fm68k_get_pc(&PicoCpuFS68k)\r
12da51c2 79#define SekDar(x) (x < 8 ? PicoCpuFM68k.dreg[x].D : PicoCpuFM68k.areg[x - 8].D)\r
80#define SekDarS68k(x) (x < 8 ? PicoCpuFS68k.dreg[x].D : PicoCpuFS68k.areg[x - 8].D)\r
5fadfb1c 81#define SekSr PicoCpuFM68k.sr\r
12da51c2 82#define SekSrS68k PicoCpuFS68k.sr\r
70357ce5 83#define SekSetStop(x) { \\r
03e4f2a3 84 PicoCpuFM68k.execinfo &= ~FM68K_HALTED; \\r
85 if (x) { PicoCpuFM68k.execinfo |= FM68K_HALTED; PicoCpuFM68k.io_cycle_counter = 0; } \\r
70357ce5 86}\r
87#define SekSetStopS68k(x) { \\r
03e4f2a3 88 PicoCpuFS68k.execinfo &= ~FM68K_HALTED; \\r
89 if (x) { PicoCpuFS68k.execinfo |= FM68K_HALTED; PicoCpuFS68k.io_cycle_counter = 0; } \\r
70357ce5 90}\r
ed4402a7 91#define SekIsStoppedM68k() (PicoCpuFM68k.execinfo&FM68K_HALTED)\r
ca61ee42 92#define SekIsStoppedS68k() (PicoCpuFS68k.execinfo&FM68K_HALTED)\r
03e4f2a3 93#define SekShouldInterrupt fm68k_would_interrupt()\r
b542be46 94\r
95#define SekInterrupt(irq) PicoCpuFM68k.interrupts[0]=irq\r
5fadfb1c 96#define SekIrqLevel PicoCpuFM68k.interrupts[0]\r
b542be46 97\r
03e4f2a3 98#ifdef EMU_M68K\r
99#define EMU_CORE_DEBUG\r
100#endif\r
cc68a136 101#endif\r
102\r
103#ifdef EMU_M68K\r
104#include "../cpu/musashi/m68kcpu.h"\r
3aa1e148 105extern m68ki_cpu_core PicoCpuMM68k, PicoCpuMS68k;\r
cc68a136 106#ifndef SekCyclesLeft\r
3aa1e148 107#define SekCyclesLeftNoMCD PicoCpuMM68k.cyc_remaining_cycles\r
7336a99a 108#define SekCyclesLeft \\r
602133e1 109 (((PicoAHW&1) && (PicoOpt & POPT_EN_MCD_PSYNC)) ? (SekCycleAim-SekCycleCnt) : SekCyclesLeftNoMCD)\r
7a1f6e45 110#define SekCyclesLeftS68k \\r
602133e1 111 ((PicoOpt & POPT_EN_MCD_PSYNC) ? (SekCycleAimS68k-SekCycleCntS68k) : PicoCpuMS68k.cyc_remaining_cycles)\r
ef090115 112#define SekEndTimeslice(after) SET_CYCLES(after)\r
07ceafdb 113#define SekEndTimesliceS68k(after) PicoCpuMS68k.cyc_remaining_cycles=after\r
3aa1e148 114#define SekPc m68k_get_reg(&PicoCpuMM68k, M68K_REG_PC)\r
115#define SekPcS68k m68k_get_reg(&PicoCpuMS68k, M68K_REG_PC)\r
12da51c2 116#define SekDar(x) PicoCpuMM68k.dar[x]\r
117#define SekDarS68k(x) PicoCpuMS68k.dar[x]\r
118#define SekSr m68k_get_reg(&PicoCpuMM68k, M68K_REG_SR)\r
119#define SekSrS68k m68k_get_reg(&PicoCpuMS68k, M68K_REG_SR)\r
7a1f6e45 120#define SekSetStop(x) { \\r
3aa1e148 121 if(x) { SET_CYCLES(0); PicoCpuMM68k.stopped=STOP_LEVEL_STOP; } \\r
122 else PicoCpuMM68k.stopped=0; \\r
7a1f6e45 123}\r
124#define SekSetStopS68k(x) { \\r
3aa1e148 125 if(x) { SET_CYCLES(0); PicoCpuMS68k.stopped=STOP_LEVEL_STOP; } \\r
126 else PicoCpuMS68k.stopped=0; \\r
7a1f6e45 127}\r
ed4402a7 128#define SekIsStoppedM68k() (PicoCpuMM68k.stopped==STOP_LEVEL_STOP)\r
ca61ee42 129#define SekIsStoppedS68k() (PicoCpuMS68k.stopped==STOP_LEVEL_STOP)\r
03e4f2a3 130#define SekShouldInterrupt (CPU_INT_LEVEL > FLAG_INT_MASK)\r
b542be46 131\r
71de3cd9 132#define SekInterrupt(irq) { \\r
b542be46 133 void *oldcontext = m68ki_cpu_p; \\r
134 m68k_set_context(&PicoCpuMM68k); \\r
135 m68k_set_irq(irq); \\r
136 m68k_set_context(oldcontext); \\r
137}\r
5fadfb1c 138#define SekIrqLevel (PicoCpuMM68k.int_level >> 8)\r
b542be46 139\r
cc68a136 140#endif\r
ef090115 141#endif // EMU_M68K\r
cc68a136 142\r
143extern int SekCycleCnt; // cycles done in this frame\r
144extern int SekCycleAim; // cycle aim\r
145extern unsigned int SekCycleCntT; // total cycle counter, updated once per frame\r
146\r
b8cbd802 147#define SekCyclesReset() { \\r
148 SekCycleCntT+=SekCycleAim; \\r
149 SekCycleCnt-=SekCycleAim; \\r
150 SekCycleAim=0; \\r
151}\r
cc68a136 152#define SekCyclesBurn(c) SekCycleCnt+=c\r
4b9c5888 153#define SekCyclesDone() (SekCycleAim-SekCyclesLeft) // number of cycles done in this frame (can be checked anywhere)\r
cc68a136 154#define SekCyclesDoneT() (SekCycleCntT+SekCyclesDone()) // total nuber of cycles done for this rom\r
19886062 155#define SekCyclesDoneT2() (SekCycleCntT + SekCycleCnt) // same as above but not from memhandlers\r
cc68a136 156\r
157#define SekEndRun(after) { \\r
ef090115 158 SekCycleCnt -= SekCyclesLeft - (after); \\r
159 if (SekCycleCnt < 0) SekCycleCnt = 0; \\r
160 SekEndTimeslice(after); \\r
cc68a136 161}\r
162\r
07ceafdb 163#define SekEndRunS68k(after) { \\r
164 SekCycleCntS68k -= SekCyclesLeftS68k - (after); \\r
165 if (SekCycleCntS68k < 0) SekCycleCntS68k = 0; \\r
166 SekEndTimesliceS68k(after); \\r
167}\r
168\r
cc68a136 169extern int SekCycleCntS68k;\r
170extern int SekCycleAimS68k;\r
171\r
bf5fbbb4 172#define SekCyclesResetS68k() { \\r
173 SekCycleCntS68k-=SekCycleAimS68k; \\r
174 SekCycleAimS68k=0; \\r
175}\r
7a1f6e45 176#define SekCyclesDoneS68k() (SekCycleAimS68k-SekCyclesLeftS68k)\r
cc68a136 177\r
03e4f2a3 178#ifdef EMU_CORE_DEBUG\r
99464b62 179extern int dbg_irq_level;\r
ef090115 180#undef SekEndTimeslice\r
2d0b15bb 181#undef SekCyclesBurn\r
182#undef SekEndRun\r
99464b62 183#undef SekInterrupt\r
ef090115 184#define SekEndTimeslice(c)\r
2270612a 185#define SekCyclesBurn(c) c\r
2d0b15bb 186#define SekEndRun(c)\r
99464b62 187#define SekInterrupt(irq) dbg_irq_level=irq\r
2d0b15bb 188#endif\r
cc68a136 189\r
b542be46 190// ----------------------- Z80 CPU -----------------------\r
191\r
b4db550e 192#if defined(_USE_DRZ80)\r
dca310c4 193#include "../cpu/DrZ80/drz80.h"\r
b542be46 194\r
195extern struct DrZ80 drZ80;\r
196\r
197#define z80_run(cycles) ((cycles) - DrZ80Run(&drZ80, cycles))\r
198#define z80_run_nr(cycles) DrZ80Run(&drZ80, cycles)\r
4936aac1 199#define z80_int() drZ80.Z80_IRQ = 1\r
4b9c5888 200\r
201#define z80_cyclesLeft drZ80.cycles\r
19954be1 202#define z80_pc() (drZ80.Z80PC - drZ80.Z80PC_BASE)\r
b542be46 203\r
204#elif defined(_USE_CZ80)\r
dca310c4 205#include "../cpu/cz80/cz80.h"\r
b542be46 206\r
207#define z80_run(cycles) Cz80_Exec(&CZ80, cycles)\r
208#define z80_run_nr(cycles) Cz80_Exec(&CZ80, cycles)\r
209#define z80_int() Cz80_Set_IRQ(&CZ80, 0, HOLD_LINE)\r
4b9c5888 210\r
211#define z80_cyclesLeft (CZ80.ICount - CZ80.ExtraCycles)\r
19954be1 212#define z80_pc() Cz80_Get_Reg(&CZ80, CZ80_PC)\r
b542be46 213\r
214#else\r
215\r
216#define z80_run(cycles) (cycles)\r
217#define z80_run_nr(cycles)\r
218#define z80_int()\r
b542be46 219\r
220#endif\r
221\r
b4db550e 222#define Z80_STATE_SIZE 0x60\r
223\r
4b9c5888 224extern int z80stopCycle; /* in 68k cycles */\r
225extern int z80_cycle_cnt; /* 'done' z80 cycles before z80_run() */\r
226extern int z80_cycle_aim;\r
227extern int z80_scanline;\r
228extern int z80_scanline_cycles; /* cycles done until z80_scanline */\r
229\r
230#define z80_resetCycles() \\r
231 z80_cycle_cnt = z80_cycle_aim = z80_scanline = z80_scanline_cycles = 0;\r
232\r
233#define z80_cyclesDone() \\r
234 (z80_cycle_aim - z80_cyclesLeft)\r
235\r
236#define cycles_68k_to_z80(x) ((x)*957 >> 11)\r
237\r
acd35d4c 238// ----------------------- SH2 CPU -----------------------\r
239\r
41397701 240#include "cpu/sh2/sh2.h"\r
acd35d4c 241\r
1d7a28a7 242extern SH2 sh2s[2];\r
243#define msh2 sh2s[0]\r
244#define ssh2 sh2s[1]\r
245\r
679af8a3 246#ifndef DRC_SH2\r
19886062 247# define sh2_end_run(sh2, after_) do { \\r
248 if ((sh2)->icount > (after_)) { \\r
c1931173 249 (sh2)->cycles_timeslice -= (sh2)->icount - (after_); \\r
19886062 250 (sh2)->icount = after_; \\r
a8fd6e37 251 } \\r
252} while (0)\r
19886062 253# define sh2_cycles_left(sh2) (sh2)->icount\r
f81107f5 254# define sh2_pc(sh2) (sh2)->ppc\r
679af8a3 255#else\r
19886062 256# define sh2_end_run(sh2, after_) do { \\r
257 int left_ = (signed int)(sh2)->sr >> 12; \\r
258 if (left_ > (after_)) { \\r
c1931173 259 (sh2)->cycles_timeslice -= left_ - (after_); \\r
f4c0720c 260 (sh2)->sr &= 0xfff; \\r
19886062 261 (sh2)->sr |= (after_) << 12; \\r
a8fd6e37 262 } \\r
263} while (0)\r
19886062 264# define sh2_cycles_left(sh2) ((signed int)(sh2)->sr >> 12)\r
f81107f5 265# define sh2_pc(sh2) (sh2)->pc\r
679af8a3 266#endif\r
266c6afa 267\r
19886062 268#define sh2_cycles_done(sh2) ((int)(sh2)->cycles_timeslice - sh2_cycles_left(sh2))\r
a7f82a77 269#define sh2_cycles_done_t(sh2) \\r
270 ((sh2)->m68krcycles_done * 3 + sh2_cycles_done(sh2))\r
19886062 271#define sh2_cycles_done_m68k(sh2) \\r
272 ((sh2)->m68krcycles_done + (sh2_cycles_done(sh2) / 3))\r
273\r
4ea707e1 274#define sh2_reg(c, x) (c) ? ssh2.r[x] : msh2.r[x]\r
275#define sh2_gbr(c) (c) ? ssh2.gbr : msh2.gbr\r
276#define sh2_vbr(c) (c) ? ssh2.vbr : msh2.vbr\r
6add7875 277#define sh2_sr(c) (((c) ? ssh2.sr : msh2.sr) & 0xfff)\r
acd35d4c 278\r
83ff19ec 279#define sh2_set_gbr(c, v) \\r
280 { if (c) ssh2.gbr = v; else msh2.gbr = v; }\r
281#define sh2_set_vbr(c, v) \\r
282 { if (c) ssh2.vbr = v; else msh2.vbr = v; }\r
283\r
cc68a136 284// ---------------------------------------------------------\r
285\r
286// main oscillator clock which controls timing\r
287#define OSC_NTSC 53693100\r
b8cbd802 288#define OSC_PAL 53203424\r
cc68a136 289\r
290struct PicoVideo\r
291{\r
292 unsigned char reg[0x20];\r
b8cbd802 293 unsigned int command; // 32-bit Command\r
294 unsigned char pending; // 1 if waiting for second half of 32-bit command\r
295 unsigned char type; // Command type (v/c/vsram read/write)\r
296 unsigned short addr; // Read/Write address\r
297 int status; // Status bits\r
cc68a136 298 unsigned char pending_ints; // pending interrupts: ??VH????\r
b8cbd802 299 signed char lwrite_cnt; // VDP write count during active display line\r
9761a7d0 300 unsigned short v_counter; // V-counter\r
301 unsigned char pad[0x10];\r
cc68a136 302};\r
303\r
304struct PicoMisc\r
305{\r
306 unsigned char rotate;\r
307 unsigned char z80Run;\r
e5503e2f 308 unsigned char padTHPhase[2]; // 02 phase of gamepad TH switches\r
2aa27095 309 unsigned short scanline; // 04 0 to 261||311\r
e5503e2f 310 char dirtyPal; // 06 Is the palette dirty (1 - change @ this frame, 2 - some time before)\r
311 unsigned char hardware; // 07 Hardware value for country\r
312 unsigned char pal; // 08 1=PAL 0=NTSC\r
45f2f245 313 unsigned char sram_reg; // 09 SRAM reg. See SRR_* below\r
e5503e2f 314 unsigned short z80_bank68k; // 0a\r
be2c4208 315 unsigned short pad0;\r
316 unsigned char pad1;\r
0ace9b9a 317 unsigned char z80_reset; // 0f z80 reset held\r
e5503e2f 318 unsigned char padDelay[2]; // 10 gamepad phase time outs, so we count a delay\r
1dceadae 319 unsigned short eeprom_addr; // EEPROM address register\r
45f2f245 320 unsigned char eeprom_cycle; // EEPROM cycle number\r
1dceadae 321 unsigned char eeprom_slave; // EEPROM slave word for X24C02 and better SRAMs\r
45f2f245 322 unsigned char eeprom_status;\r
be2c4208 323 unsigned char pad2;\r
053fd9b4 324 unsigned short dma_xfers; // 18\r
45f2f245 325 unsigned char eeprom_wb[2]; // EEPROM latch/write buffer\r
053fd9b4 326 unsigned int frame_count; // 1c for movies and idle det\r
cc68a136 327};\r
328\r
b4db550e 329struct PicoMS\r
330{\r
331 unsigned char carthw[0x10];\r
332 unsigned char io_ctl;\r
333 unsigned char pad[0x4f];\r
334};\r
335\r
cc68a136 336// some assembly stuff depend on these, do not touch!\r
337struct Pico\r
338{\r
339 unsigned char ram[0x10000]; // 0x00000 scratch ram\r
200772b7 340 union { // vram is byteswapped for easier reads when drawing\r
2ec9bec5 341 unsigned short vram[0x8000]; // 0x10000\r
342 unsigned char vramb[0x4000]; // VRAM in SMS mode\r
343 };\r
cc68a136 344 unsigned char zram[0x2000]; // 0x20000 Z80 ram\r
b4db550e 345 unsigned char ioports[0x10]; // XXX: fix asm and mv\r
346 unsigned char pad[0xf0]; // unused\r
cc68a136 347 unsigned short cram[0x40]; // 0x22100\r
348 unsigned short vsram[0x40]; // 0x22180\r
349\r
350 unsigned char *rom; // 0x22200\r
351 unsigned int romsize; // 0x22204\r
352\r
353 struct PicoMisc m;\r
354 struct PicoVideo video;\r
b4db550e 355 struct PicoMS ms;\r
cc68a136 356};\r
357\r
358// sram\r
45f2f245 359#define SRR_MAPPED (1 << 0)\r
360#define SRR_READONLY (1 << 1)\r
361\r
362#define SRF_ENABLED (1 << 0)\r
363#define SRF_EEPROM (1 << 1)\r
af37bca8 364\r
cc68a136 365struct PicoSRAM\r
366{\r
4ff2d527 367 unsigned char *data; // actual data\r
368 unsigned int start; // start address in 68k address space\r
cc68a136 369 unsigned int end;\r
45f2f245 370 unsigned char flags; // 0c: SRF_*\r
1dceadae 371 unsigned char unused2;\r
cc68a136 372 unsigned char changed;\r
45f2f245 373 unsigned char eeprom_type; // eeprom type: 0: 7bit (24C01), 2: 2 addr words (X24C02+), 3: 3 addr words\r
374 unsigned char unused3;\r
1dceadae 375 unsigned char eeprom_bit_cl; // bit number for cl\r
376 unsigned char eeprom_bit_in; // bit number for in\r
377 unsigned char eeprom_bit_out; // bit number for out\r
45f2f245 378 unsigned int size;\r
cc68a136 379};\r
380\r
381// MCD\r
382#include "cd/cd_sys.h"\r
383#include "cd/LC89510.h"\r
d1df8786 384#include "cd/gfx_cd.h"\r
cc68a136 385\r
4f265db7 386struct mcd_pcm\r
387{\r
388 unsigned char control; // reg7\r
389 unsigned char enabled; // reg8\r
390 unsigned char cur_ch;\r
391 unsigned char bank;\r
392 int pad1;\r
393\r
4ff2d527 394 struct pcm_chan // 08, size 0x10\r
4f265db7 395 {\r
396 unsigned char regs[8];\r
4ff2d527 397 unsigned int addr; // .08: played sample address\r
4f265db7 398 int pad;\r
399 } ch[8];\r
400};\r
401\r
c459aefd 402struct mcd_misc\r
403{\r
404 unsigned short hint_vector;\r
405 unsigned char busreq;\r
51a902ae 406 unsigned char s68k_pend_ints;\r
ef090115 407 unsigned int state_flags; // 04: emu state: reset_pending\r
51a902ae 408 unsigned int counter75hz;\r
c9e1affc 409 unsigned int pad0;\r
4ff2d527 410 int timer_int3; // 10\r
4f265db7 411 unsigned int timer_stopwatch;\r
6cadc2da 412 unsigned char bcram_reg; // 18: battery-backed RAM cart register\r
413 unsigned char pad2;\r
414 unsigned short pad3;\r
415 int pad[9];\r
c459aefd 416};\r
417\r
cc68a136 418typedef struct\r
419{\r
4ff2d527 420 unsigned char bios[0x20000]; // 000000: 128K\r
421 union { // 020000: 512K\r
fa1e5e29 422 unsigned char prg_ram[0x80000];\r
cc68a136 423 unsigned char prg_ram_b[4][0x20000];\r
424 };\r
4ff2d527 425 union { // 0a0000: 256K\r
fa1e5e29 426 struct {\r
427 unsigned char word_ram2M[0x40000];\r
dca310c4 428 unsigned char unused0[0x20000];\r
fa1e5e29 429 };\r
430 struct {\r
dca310c4 431 unsigned char unused1[0x20000];\r
fa1e5e29 432 unsigned char word_ram1M[2][0x20000];\r
433 };\r
434 };\r
4ff2d527 435 union { // 100000: 64K\r
fa1e5e29 436 unsigned char pcm_ram[0x10000];\r
4f265db7 437 unsigned char pcm_ram_b[0x10][0x1000];\r
438 };\r
4ff2d527 439 unsigned char s68k_regs[0x200]; // 110000: GA, not CPU regs\r
440 unsigned char bram[0x2000]; // 110200: 8K\r
441 struct mcd_misc m; // 112200: misc\r
442 struct mcd_pcm pcm; // 112240:\r
75736070 443 _scd_toc TOC; // not to be saved\r
cc68a136 444 CDD cdd;\r
445 CDC cdc;\r
446 _scd scd;\r
d1df8786 447 Rot_Comp rot_comp;\r
cc68a136 448} mcd_state;\r
449\r
be2c4208 450// XXX: this will need to be reworked for cart+cd support.\r
cc68a136 451#define Pico_mcd ((mcd_state *)Pico.rom)\r
452\r
be2c4208 453// 32X\r
acd35d4c 454#define P32XS_FM (1<<15)\r
83ff19ec 455#define P32XS_REN (1<< 7)\r
456#define P32XS_nRES (1<< 1)\r
457#define P32XS_ADEN (1<< 0)\r
acd35d4c 458#define P32XS2_ADEN (1<< 9)\r
5e128c6d 459#define P32XS_FULL (1<< 7) // DREQ FIFO full\r
4ea707e1 460#define P32XS_68S (1<< 2)\r
97d3f47f 461#define P32XS_DMA (1<< 1)\r
4ea707e1 462#define P32XS_RV (1<< 0)\r
acd35d4c 463\r
5e128c6d 464#define P32XV_nPAL (1<<15) // VDP\r
acd35d4c 465#define P32XV_PRI (1<< 7)\r
4ea707e1 466#define P32XV_Mx (3<< 0) // display mode mask\r
974fdb5b 467\r
e51e5983 468#define P32XV_SFT (1<< 0)\r
469\r
acd35d4c 470#define P32XV_VBLK (1<<15)\r
471#define P32XV_HBLK (1<<14)\r
472#define P32XV_PEN (1<<13)\r
473#define P32XV_nFEN (1<< 1)\r
474#define P32XV_FS (1<< 0)\r
974fdb5b 475\r
df63f1a6 476#define P32XP_RTP (1<<7) // PWM control\r
477#define P32XP_FULL (1<<15) // PWM pulse\r
db1d3564 478#define P32XP_EMPTY (1<<14)\r
479\r
19886062 480#define P32XF_68KCPOLL (1 << 0)\r
481#define P32XF_68KVPOLL (1 << 1)\r
4ea707e1 482\r
483#define P32XI_VRES (1 << 14/2) // IRL/2\r
484#define P32XI_VINT (1 << 12/2)\r
485#define P32XI_HINT (1 << 10/2)\r
486#define P32XI_CMD (1 << 8/2)\r
487#define P32XI_PWM (1 << 6/2)\r
488\r
1d7a28a7 489// peripheral reg access\r
490#define PREG8(regs,offs) ((unsigned char *)regs)[offs ^ 3]\r
491\r
4ea707e1 492// real one is 4*2, but we use more because we don't lockstep\r
493#define DMAC_FIFO_LEN (4*4)\r
db1d3564 494#define PWM_BUFF_LEN 1024 // in one channel samples\r
266c6afa 495\r
f4bb5d6b 496#define SH2_DRCBLK_RAM_SHIFT 1\r
497#define SH2_DRCBLK_DA_SHIFT 1\r
498\r
f81107f5 499#define SH2_READ_SHIFT 25\r
e05b81fc 500#define SH2_WRITE_SHIFT 25\r
501\r
be2c4208 502struct Pico32x\r
503{\r
504 unsigned short regs[0x20];\r
5a681086 505 unsigned short vdp_regs[0x10]; // 0x40\r
506 unsigned short sh2_regs[3]; // 0x60\r
be2c4208 507 unsigned char pending_fb;\r
974fdb5b 508 unsigned char dirty_pal;\r
266c6afa 509 unsigned int emu_flags;\r
4ea707e1 510 unsigned char sh2irq_mask[2];\r
511 unsigned char sh2irqi[2]; // individual\r
512 unsigned int sh2irqs; // common irqs\r
513 unsigned short dmac_fifo[DMAC_FIFO_LEN];\r
df63f1a6 514 unsigned int dmac0_fifo_ptr;\r
4a1fb183 515 unsigned short vdp_fbcr_fake;\r
516 unsigned short pad;\r
a8fd6e37 517 unsigned char comm_dirty_68k;\r
518 unsigned char comm_dirty_sh2;\r
df63f1a6 519 unsigned char pwm_irq_cnt;\r
520 unsigned char pad1;\r
a7f82a77 521 unsigned short pwm_p[2]; // pwm pos in fifo\r
522 unsigned int pwm_cycle_p; // pwm play cursor (32x cycles)\r
523 unsigned int reserved[6];\r
974fdb5b 524};\r
525\r
526struct Pico32xMem\r
527{\r
528 unsigned char sdram[0x40000];\r
f4bb5d6b 529#ifdef DRC_SH2\r
530 unsigned short drcblk_ram[1 << (18 - SH2_DRCBLK_RAM_SHIFT)];\r
531#endif\r
b78efee2 532 unsigned short dram[2][0x20000/2]; // AKA fb\r
b4db550e 533 union {\r
534 unsigned char m68k_rom[0x100];\r
535 unsigned char m68k_rom_bank[0x10000]; // M68K_BANK_SIZE\r
536 };\r
f4bb5d6b 537#ifdef DRC_SH2\r
538 unsigned short drcblk_da[2][1 << (12 - SH2_DRCBLK_DA_SHIFT)];\r
539#endif\r
acd35d4c 540 unsigned char sh2_rom_m[0x800];\r
541 unsigned char sh2_rom_s[0x400];\r
974fdb5b 542 unsigned short pal[0x100];\r
5e128c6d 543 unsigned short pal_native[0x100]; // converted to native (for renderer)\r
db1d3564 544 signed short pwm[2*PWM_BUFF_LEN]; // PWM buffer for current frame\r
a7f82a77 545 signed short pwm_fifo[2][4]; // [0] - current, others - fifo entries\r
be2c4208 546};\r
d49b10c2 547\r
c8d1e9b6 548// area.c\r
fad24893 549extern void (*PicoLoadStateHook)(void);\r
51a902ae 550\r
945c2fdc 551typedef struct {\r
552 int chunk;\r
553 int size;\r
554 void *ptr;\r
555} carthw_state_chunk;\r
556extern carthw_state_chunk *carthw_chunks;\r
557#define CHUNK_CARTHW 64\r
558\r
c8d1e9b6 559// cart.c\r
b4db550e 560extern int PicoCartResize(int newsize);\r
561extern void Byteswap(void *dst, const void *src, int len);\r
45f2f245 562extern void (*PicoCartMemSetup)(void);\r
e807ac75 563extern void (*PicoCartUnloadHook)(void);\r
1dceadae 564\r
c8d1e9b6 565// debug.c\r
b5e5172d 566int CM_compareRun(int cyc, int is_sub);\r
03e4f2a3 567\r
c8d1e9b6 568// draw.c\r
eff55556 569PICO_INTERNAL void PicoFrameStart(void);\r
b6d7ac70 570void PicoDrawSync(int to, int blank_last_line);\r
200772b7 571void BackFill(int reg7, int sh);\r
5a681086 572void FinalizeLine555(int sh, int line);\r
f4750ee0 573extern int (*PicoScanBegin)(unsigned int num);\r
574extern int (*PicoScanEnd)(unsigned int num);\r
b6d7ac70 575extern int DrawScanline;\r
f579f7b8 576#define MAX_LINE_SPRITES 29\r
577extern unsigned char HighLnSpr[240][3 + MAX_LINE_SPRITES];\r
5a681086 578extern void *DrawLineDestBase;\r
579extern int DrawLineDestIncrement;\r
cc68a136 580\r
c8d1e9b6 581// draw2.c\r
eff55556 582PICO_INTERNAL void PicoFrameFull();\r
cc68a136 583\r
200772b7 584// mode4.c\r
585void PicoFrameStartMode4(void);\r
586void PicoLineMode4(int line);\r
587void PicoDoHighPal555M4(void);\r
5a681086 588void PicoDrawSetOutputMode4(pdso_t which);\r
200772b7 589\r
c8d1e9b6 590// memory.c\r
eff55556 591PICO_INTERNAL void PicoMemSetup(void);\r
af37bca8 592unsigned int PicoRead8_io(unsigned int a);\r
593unsigned int PicoRead16_io(unsigned int a);\r
594void PicoWrite8_io(unsigned int a, unsigned int d);\r
595void PicoWrite16_io(unsigned int a, unsigned int d);\r
df63f1a6 596void p32x_dreq1_trigger(void);\r
af37bca8 597\r
598// pico/memory.c\r
599PICO_INTERNAL void PicoMemSetupPico(void);\r
cc68a136 600\r
c8d1e9b6 601// cd/memory.c\r
eff55556 602PICO_INTERNAL void PicoMemSetupCD(void);\r
0ace9b9a 603void PicoMemStateLoaded(void);\r
cc68a136 604\r
c8d1e9b6 605// pico.c\r
cc68a136 606extern struct Pico Pico;\r
607extern struct PicoSRAM SRam;\r
5f9a0d16 608extern int PicoPadInt[2];\r
cc68a136 609extern int emustatus;\r
5e128c6d 610extern int scanlines_total;\r
f8ef8ff7 611extern void (*PicoResetHook)(void);\r
b0677887 612extern void (*PicoLineHook)(void);\r
1e6b5e39 613PICO_INTERNAL int CheckDMA(void);\r
614PICO_INTERNAL void PicoDetectRegion(void);\r
4b9c5888 615PICO_INTERNAL void PicoSyncZ80(int m68k_cycles_done);\r
cc68a136 616\r
c8d1e9b6 617// cd/pico.c\r
2aa27095 618PICO_INTERNAL void PicoInitMCD(void);\r
e5f426aa 619PICO_INTERNAL void PicoExitMCD(void);\r
1cb1584b 620PICO_INTERNAL void PicoPowerMCD(void);\r
2aa27095 621PICO_INTERNAL int PicoResetMCD(void);\r
622PICO_INTERNAL void PicoFrameMCD(void);\r
cc68a136 623\r
c8d1e9b6 624// pico/pico.c\r
2aa27095 625PICO_INTERNAL void PicoInitPico(void);\r
ed367a3f 626PICO_INTERNAL void PicoReratePico(void);\r
9037e45d 627\r
c8d1e9b6 628// pico/xpcm.c\r
ef4eb506 629PICO_INTERNAL void PicoPicoPCMUpdate(short *buffer, int length, int stereo);\r
630PICO_INTERNAL void PicoPicoPCMReset(void);\r
213c16ad 631PICO_INTERNAL void PicoPicoPCMRerate(int xpcm_rate);\r
ef4eb506 632\r
c8d1e9b6 633// sek.c\r
2aa27095 634PICO_INTERNAL void SekInit(void);\r
635PICO_INTERNAL int SekReset(void);\r
3aa1e148 636PICO_INTERNAL void SekState(int *data);\r
eff55556 637PICO_INTERNAL void SekSetRealTAS(int use_real);\r
b4db550e 638PICO_INTERNAL void SekPackCpu(unsigned char *cpu, int is_sub);\r
639PICO_INTERNAL void SekUnpackCpu(const unsigned char *cpu, int is_sub);\r
5f9a0d16 640void SekStepM68k(void);\r
053fd9b4 641void SekInitIdleDet(void);\r
642void SekFinishIdleDet(void);\r
12da51c2 643#if defined(CPU_CMP_R) || defined(CPU_CMP_W)\r
644void SekTrace(int is_s68k);\r
645#else\r
646#define SekTrace(x)\r
647#endif\r
cc68a136 648\r
c8d1e9b6 649// cd/sek.c\r
2aa27095 650PICO_INTERNAL void SekInitS68k(void);\r
651PICO_INTERNAL int SekResetS68k(void);\r
652PICO_INTERNAL int SekInterruptS68k(int irq);\r
cc68a136 653\r
7a93adeb 654// sound/sound.c\r
c9e1affc 655PICO_INTERNAL void cdda_start_play();\r
656extern short cdda_out_buffer[2*1152];\r
7a93adeb 657extern int PsndLen_exc_cnt;\r
658extern int PsndLen_exc_add;\r
48dc74f2 659extern int timer_a_next_oflow, timer_a_step; // in z80 cycles\r
660extern int timer_b_next_oflow, timer_b_step;\r
43e6eaad 661\r
662void ym2612_sync_timers(int z80_cycles, int mode_old, int mode_new);\r
d2721b08 663void ym2612_pack_state(void);\r
453d2a6e 664void ym2612_unpack_state(void);\r
4b9c5888 665\r
e53704e6 666#define TIMER_NO_OFLOW 0x70000000\r
45a1ef71 667// tA = 72 * (1024 - NA) / M\r
668#define TIMER_A_TICK_ZCYCLES 17203\r
669// tB = 1152 * (256 - NA) / M\r
670#define TIMER_B_TICK_ZCYCLES 262800 // 275251 broken, see Dai Makaimura\r
e53704e6 671\r
4b9c5888 672#define timers_cycle() \\r
e53704e6 673 if (timer_a_next_oflow > 0 && timer_a_next_oflow < TIMER_NO_OFLOW) \\r
43e6eaad 674 timer_a_next_oflow -= Pico.m.pal ? 70938*256 : 59659*256; \\r
e53704e6 675 if (timer_b_next_oflow > 0 && timer_b_next_oflow < TIMER_NO_OFLOW) \\r
43e6eaad 676 timer_b_next_oflow -= Pico.m.pal ? 70938*256 : 59659*256; \\r
677 ym2612_sync_timers(0, ym2612.OPN.ST.mode, ym2612.OPN.ST.mode);\r
4b9c5888 678\r
679#define timers_reset() \\r
e53704e6 680 timer_a_next_oflow = timer_b_next_oflow = TIMER_NO_OFLOW; \\r
48dc74f2 681 timer_a_step = TIMER_A_TICK_ZCYCLES * 1024; \\r
682 timer_b_step = TIMER_B_TICK_ZCYCLES * 256;\r
43e6eaad 683\r
7a93adeb 684\r
c8d1e9b6 685// videoport.c\r
eff55556 686PICO_INTERNAL_ASM void PicoVideoWrite(unsigned int a,unsigned short d);\r
687PICO_INTERNAL_ASM unsigned int PicoVideoRead(unsigned int a);\r
9761a7d0 688PICO_INTERNAL_ASM unsigned int PicoVideoRead8(unsigned int a);\r
5de27868 689extern int (*PicoDmaHook)(unsigned int source, int len, unsigned short **srcp, unsigned short **limitp);\r
cc68a136 690\r
c8d1e9b6 691// misc.c\r
eff55556 692PICO_INTERNAL_ASM void memcpy16(unsigned short *dest, unsigned short *src, int count);\r
693PICO_INTERNAL_ASM void memcpy16bswap(unsigned short *dest, void *src, int count);\r
694PICO_INTERNAL_ASM void memcpy32(int *dest, int *src, int count); // 32bit word count\r
695PICO_INTERNAL_ASM void memset32(int *dest, int c, int count);\r
cc68a136 696\r
45f2f245 697// eeprom.c\r
698void EEPROM_write8(unsigned int a, unsigned int d);\r
699void EEPROM_write16(unsigned int d);\r
700unsigned int EEPROM_read(void);\r
701\r
c8d1e9b6 702// z80 functionality wrappers\r
703PICO_INTERNAL void z80_init(void);\r
b4db550e 704PICO_INTERNAL void z80_pack(void *data);\r
705PICO_INTERNAL int z80_unpack(const void *data);\r
c8d1e9b6 706PICO_INTERNAL void z80_reset(void);\r
707PICO_INTERNAL void z80_exit(void);\r
c8d1e9b6 708\r
709// cd/misc.c\r
eff55556 710PICO_INTERNAL_ASM void wram_2M_to_1M(unsigned char *m);\r
711PICO_INTERNAL_ASM void wram_1M_to_2M(unsigned char *m);\r
712\r
713// cd/buffering.c\r
714PICO_INTERNAL void PicoCDBufferRead(void *dest, int lba);\r
715\r
716// sound/sound.c\r
9d917eea 717PICO_INTERNAL void PsndReset(void);\r
4b9c5888 718PICO_INTERNAL void PsndDoDAC(int line_to);\r
9d917eea 719PICO_INTERNAL void PsndClear(void);\r
7b3f44c6 720PICO_INTERNAL void PsndGetSamples(int y);\r
2ec9bec5 721PICO_INTERNAL void PsndGetSamplesMS(void);\r
4b9c5888 722extern int PsndDacLine;\r
cc68a136 723\r
3e49ffd0 724// sms.c\r
f3a57b2d 725#ifndef NO_SMS\r
3e49ffd0 726void PicoPowerMS(void);\r
2ec9bec5 727void PicoResetMS(void);\r
3e49ffd0 728void PicoMemSetupMS(void);\r
b4db550e 729void PicoStateLoadedMS(void);\r
3e49ffd0 730void PicoFrameMS(void);\r
87b0845f 731void PicoFrameDrawOnlyMS(void);\r
f3a57b2d 732#else\r
733#define PicoPowerMS()\r
734#define PicoResetMS()\r
735#define PicoMemSetupMS()\r
736#define PicoStateLoadedMS()\r
737#define PicoFrameMS()\r
738#define PicoFrameDrawOnlyMS()\r
739#endif\r
3e49ffd0 740\r
be2c4208 741// 32x/32x.c\r
f3a57b2d 742#ifndef NO_32X\r
be2c4208 743extern struct Pico32x Pico32x;\r
6a98f03e 744enum p32x_event {\r
745 P32X_EVENT_PWM,\r
746 P32X_EVENT_FILLEND,\r
747 P32X_EVENT_COUNT,\r
748};\r
749extern unsigned int event_times[P32X_EVENT_COUNT];\r
750\r
be2c4208 751void Pico32xInit(void);\r
974fdb5b 752void PicoPower32x(void);\r
be2c4208 753void PicoReset32x(void);\r
974fdb5b 754void Pico32xStartup(void);\r
5e49c3a8 755void PicoUnload32x(void);\r
974fdb5b 756void PicoFrame32x(void);\r
27e26273 757void Pico32xStateLoaded(int is_early);\r
ed4402a7 758void p32x_sync_sh2s(unsigned int m68k_target);\r
19886062 759void p32x_sync_other_sh2(SH2 *sh2, unsigned int m68k_target);\r
4d5dfee8 760void p32x_update_irls(SH2 *active_sh2, int m68k_cycles);\r
83ff19ec 761void p32x_reset_sh2s(void);\r
19886062 762void p32x_event_schedule(unsigned int now, enum p32x_event event, int after);\r
763void p32x_event_schedule_sh2(SH2 *sh2, enum p32x_event event, int after);\r
a8fd6e37 764\r
be2c4208 765// 32x/memory.c\r
974fdb5b 766struct Pico32xMem *Pico32xMem;\r
be2c4208 767unsigned int PicoRead8_32x(unsigned int a);\r
768unsigned int PicoRead16_32x(unsigned int a);\r
769void PicoWrite8_32x(unsigned int a, unsigned int d);\r
770void PicoWrite16_32x(unsigned int a, unsigned int d);\r
771void PicoMemSetup32x(void);\r
974fdb5b 772void Pico32xSwapDRAM(int b);\r
27e26273 773void Pico32xMemStateLoaded(void);\r
19886062 774void p32x_m68k_poll_event(unsigned int flags);\r
775void p32x_sh2_poll_event(SH2 *sh2, unsigned int flags, unsigned int m68k_cycles);\r
974fdb5b 776\r
777// 32x/draw.c\r
41946d70 778void PicoDrawSetOutFormat32x(pdso_t which, int use_32x_line_mode);\r
974fdb5b 779void FinalizeLine32xRGB555(int sh, int line);\r
5a681086 780void PicoDraw32xLayer(int offs, int lines, int mdbg);\r
7a961c19 781void PicoDraw32xLayerMdOnly(int offs, int lines);\r
f4750ee0 782extern int (*PicoScan32xBegin)(unsigned int num);\r
783extern int (*PicoScan32xEnd)(unsigned int num);\r
7a961c19 784enum {\r
785 PDM32X_OFF,\r
786 PDM32X_32X_ONLY,\r
787 PDM32X_BOTH,\r
788};\r
5a681086 789extern int Pico32xDrawMode;\r
be2c4208 790\r
db1d3564 791// 32x/pwm.c\r
c1931173 792unsigned int p32x_pwm_read16(unsigned int a, SH2 *sh2,\r
793 unsigned int m68k_cycles);\r
794void p32x_pwm_write16(unsigned int a, unsigned int d,\r
795 SH2 *sh2, unsigned int m68k_cycles);\r
db1d3564 796void p32x_pwm_update(int *buf32, int length, int stereo);\r
045a4c52 797void p32x_pwm_ctl_changed(void);\r
df63f1a6 798void p32x_pwm_schedule(unsigned int m68k_now);\r
19886062 799void p32x_pwm_schedule_sh2(SH2 *sh2);\r
df63f1a6 800void p32x_pwm_irq_event(unsigned int m68k_now);\r
801void p32x_pwm_state_loaded(void);\r
045a4c52 802\r
803// 32x/sh2soc.c\r
804void p32x_dreq0_trigger(void);\r
805void p32x_dreq1_trigger(void);\r
806void p32x_timers_recalc(void);\r
807void p32x_timers_do(unsigned int m68k_slice);\r
cd0ace28 808void sh2_peripheral_reset(SH2 *sh2);\r
f81107f5 809unsigned int sh2_peripheral_read8(unsigned int a, SH2 *sh2);\r
810unsigned int sh2_peripheral_read16(unsigned int a, SH2 *sh2);\r
811unsigned int sh2_peripheral_read32(unsigned int a, SH2 *sh2);\r
812void sh2_peripheral_write8(unsigned int a, unsigned int d, SH2 *sh2);\r
813void sh2_peripheral_write16(unsigned int a, unsigned int d, SH2 *sh2);\r
814void sh2_peripheral_write32(unsigned int a, unsigned int d, SH2 *sh2);\r
045a4c52 815\r
f3a57b2d 816#else\r
817#define Pico32xInit()\r
818#define PicoPower32x()\r
819#define PicoReset32x()\r
820#define PicoFrame32x()\r
821#define PicoUnload32x()\r
822#define Pico32xStateLoaded()\r
f3a57b2d 823#define FinalizeLine32xRGB555 NULL\r
824#define p32x_pwm_update(...)\r
825#define p32x_timers_recalc()\r
826#endif\r
db1d3564 827\r
45f2f245 828/* avoid dependency on newer glibc */\r
829static __inline int isspace_(int c)\r
830{\r
831 return (0x09 <= c && c <= 0x0d) || c == ' ';\r
832}\r
833\r
f4bb5d6b 834#ifndef ARRAY_SIZE\r
835#define ARRAY_SIZE(x) (sizeof(x) / sizeof(x[0]))\r
836#endif\r
837\r
b8cbd802 838// emulation event logging\r
839#ifndef EL_LOGMASK\r
9c9cda8c 840# ifdef __x86_64__ // HACK\r
841# define EL_LOGMASK (EL_STATUS|EL_IDLE|EL_ANOMALY)\r
842# else\r
1555935b 843# define EL_LOGMASK (EL_STATUS)\r
9c9cda8c 844# endif\r
b8cbd802 845#endif\r
846\r
017512f2 847#define EL_HVCNT 0x00000001 /* hv counter reads */\r
848#define EL_SR 0x00000002 /* SR reads */\r
849#define EL_INTS 0x00000004 /* ints and acks */\r
43e6eaad 850#define EL_YMTIMER 0x00000008 /* ym2612 timer stuff */\r
017512f2 851#define EL_INTSW 0x00000010 /* log irq switching on/off */\r
852#define EL_ASVDP 0x00000020 /* VDP accesses during active scan */\r
853#define EL_VDPDMA 0x00000040 /* VDP DMA transfers and their timing */\r
854#define EL_BUSREQ 0x00000080 /* z80 busreq r/w or reset w */\r
855#define EL_Z80BNK 0x00000100 /* z80 i/o through bank area */\r
856#define EL_SRAMIO 0x00000200 /* sram i/o */\r
857#define EL_EEPROM 0x00000400 /* eeprom debug */\r
858#define EL_UIO 0x00000800 /* unmapped i/o */\r
859#define EL_IO 0x00001000 /* all i/o */\r
860#define EL_CDPOLL 0x00002000 /* MCD: log poll detection */\r
861#define EL_SVP 0x00004000 /* SVP stuff */\r
fa22af4c 862#define EL_PICOHW 0x00008000 /* Pico stuff */\r
053fd9b4 863#define EL_IDLE 0x00010000 /* idle loop det. */\r
af37bca8 864#define EL_CDREGS 0x00020000 /* MCD: register access */\r
865#define EL_CDREG3 0x00040000 /* MCD: register 3 only */\r
be2c4208 866#define EL_32X 0x00080000\r
1b3f5844 867#define EL_PWM 0x00100000 /* 32X PWM stuff (LOTS of output) */\r
045a4c52 868#define EL_32XP 0x00200000 /* 32X peripherals */\r
017512f2 869\r
870#define EL_STATUS 0x40000000 /* status messages */\r
871#define EL_ANOMALY 0x80000000 /* some unexpected conditions (during emulation) */\r
b8cbd802 872\r
873#if EL_LOGMASK\r
874#define elprintf(w,f,...) \\r
a8fd6e37 875do { \\r
b8cbd802 876 if ((w) & EL_LOGMASK) \\r
7d0143a2 877 lprintf("%05i:%03i: " f "\n",Pico.m.frame_count,Pico.m.scanline,##__VA_ARGS__); \\r
a8fd6e37 878} while (0)\r
dca310c4 879#elif defined(_MSC_VER)\r
880#define elprintf\r
b8cbd802 881#else\r
882#define elprintf(w,f,...)\r
883#endif\r
884\r
f6c49d38 885// profiling\r
886#ifdef PPROF\r
887#include <platform/linux/pprof.h>\r
888#else\r
889#define pprof_init()\r
890#define pprof_finish()\r
891#define pprof_start(x)\r
892#define pprof_end(...)\r
893#define pprof_end_sub(...)\r
894#endif\r
895\r
19886062 896#ifdef EVT_LOG\r
897enum evt {\r
898 EVT_FRAME_START,\r
899 EVT_NEXT_LINE,\r
900 EVT_RUN_START,\r
901 EVT_RUN_END,\r
902 EVT_POLL_START,\r
903 EVT_POLL_END,\r
904 EVT_CNT\r
905};\r
906\r
907enum evt_cpu {\r
908 EVT_M68K,\r
909 EVT_S68K,\r
910 EVT_MSH2,\r
911 EVT_SSH2,\r
912 EVT_CPU_CNT\r
913};\r
914\r
915void pevt_log(unsigned int cycles, enum evt_cpu c, enum evt e);\r
916void pevt_dump(void);\r
917\r
918#define pevt_log_m68k(e) \\r
919 pevt_log(SekCyclesDoneT(), EVT_M68K, e)\r
920#define pevt_log_m68k_o(e) \\r
921 pevt_log(SekCyclesDoneT2(), EVT_M68K, e)\r
922#define pevt_log_sh2(sh2, e) \\r
923 pevt_log(sh2_cycles_done_m68k(sh2), EVT_MSH2 + (sh2)->is_slave, e)\r
924#define pevt_log_sh2_o(sh2, e) \\r
925 pevt_log((sh2)->m68krcycles_done, EVT_MSH2 + (sh2)->is_slave, e)\r
926#else\r
927#define pevt_log(c, e)\r
928#define pevt_log_m68k(e)\r
929#define pevt_log_m68k_o(e)\r
930#define pevt_log_sh2(sh2, e)\r
931#define pevt_log_sh2_o(sh2, e)\r
932#define pevt_dump()\r
933#endif\r
934\r
f6c49d38 935// misc\r
dca310c4 936#ifdef _MSC_VER\r
937#define cdprintf\r
938#else\r
939#define cdprintf(x...)\r
940#endif\r
941\r
553c3eaa 942#ifdef __i386__\r
943#define REGPARM(x) __attribute__((regparm(x)))\r
c8d1e9b6 944#else\r
553c3eaa 945#define REGPARM(x)\r
c8d1e9b6 946#endif\r
947\r
5e89f0f5 948#ifdef __GNUC__\r
949#define NOINLINE __attribute__((noinline))\r
950#else\r
951#define NOINLINE\r
952#endif\r
953\r
f8af9634 954#ifdef __cplusplus\r
955} // End of extern "C"\r
956#endif\r
957\r
eff55556 958#endif // PICO_INTERNAL_INCLUDED\r
959\r
fast MegaDrive/MegaCD/32X emulator