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fix yet another portability issue
[picodrive.git] / pico / pico_int.h
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cff531af 1/*\r
2 * PicoDrive - Internal Header File\r
3 * (c) Copyright Dave, 2004\r
4 * (C) notaz, 2006-2010\r
5 *\r
6 * This work is licensed under the terms of MAME license.\r
7 * See COPYING file in the top-level directory.\r
8 */\r
cc68a136 9\r
eff55556 10#ifndef PICO_INTERNAL_INCLUDED\r
11#define PICO_INTERNAL_INCLUDED\r
cc68a136 12\r
13#include <stdio.h>\r
14#include <stdlib.h>\r
15#include <string.h>\r
efcba75f 16#include "pico.h"\r
f53f286a 17#include "carthw/carthw.h"\r
cc68a136 18\r
89fa852d 19//\r
20#define USE_POLL_DETECT\r
21\r
eff55556 22#ifndef PICO_INTERNAL\r
23#define PICO_INTERNAL\r
24#endif\r
25#ifndef PICO_INTERNAL_ASM\r
26#define PICO_INTERNAL_ASM\r
27#endif\r
cc68a136 28\r
70357ce5 29// to select core, define EMU_C68K, EMU_M68K or EMU_F68K in your makefile or project\r
cc68a136 30\r
31#ifdef __cplusplus\r
32extern "C" {\r
33#endif\r
34\r
35\r
36// ----------------------- 68000 CPU -----------------------\r
37#ifdef EMU_C68K\r
d4d62665 38#include "../cpu/cyclone/Cyclone.h"\r
3aa1e148 39extern struct Cyclone PicoCpuCM68k, PicoCpuCS68k;\r
ae214f1c 40#define SekCyclesLeft PicoCpuCM68k.cycles // cycles left for this run\r
41#define SekCyclesLeftS68k PicoCpuCS68k.cycles\r
3aa1e148 42#define SekPc (PicoCpuCM68k.pc-PicoCpuCM68k.membase)\r
43#define SekPcS68k (PicoCpuCS68k.pc-PicoCpuCS68k.membase)\r
12da51c2 44#define SekDar(x) (x < 8 ? PicoCpuCM68k.d[x] : PicoCpuCM68k.a[x - 8])\r
45#define SekDarS68k(x) (x < 8 ? PicoCpuCS68k.d[x] : PicoCpuCS68k.a[x - 8])\r
5fadfb1c 46#define SekSr CycloneGetSr(&PicoCpuCM68k)\r
12da51c2 47#define SekSrS68k CycloneGetSr(&PicoCpuCS68k)\r
3aa1e148 48#define SekSetStop(x) { PicoCpuCM68k.state_flags&=~1; if (x) { PicoCpuCM68k.state_flags|=1; PicoCpuCM68k.cycles=0; } }\r
49#define SekSetStopS68k(x) { PicoCpuCS68k.state_flags&=~1; if (x) { PicoCpuCS68k.state_flags|=1; PicoCpuCS68k.cycles=0; } }\r
ed4402a7 50#define SekIsStoppedM68k() (PicoCpuCM68k.state_flags&1)\r
ca61ee42 51#define SekIsStoppedS68k() (PicoCpuCS68k.state_flags&1)\r
03e4f2a3 52#define SekShouldInterrupt (PicoCpuCM68k.irq > (PicoCpuCM68k.srh&7))\r
b542be46 53\r
54#define SekInterrupt(i) PicoCpuCM68k.irq=i\r
5fadfb1c 55#define SekIrqLevel PicoCpuCM68k.irq\r
b542be46 56\r
cc68a136 57#endif\r
58\r
70357ce5 59#ifdef EMU_F68K\r
60#include "../cpu/fame/fame.h"\r
b542be46 61extern M68K_CONTEXT PicoCpuFM68k, PicoCpuFS68k;\r
ae214f1c 62#define SekCyclesLeft PicoCpuFM68k.io_cycle_counter\r
63#define SekCyclesLeftS68k PicoCpuFS68k.io_cycle_counter\r
03e4f2a3 64#define SekPc fm68k_get_pc(&PicoCpuFM68k)\r
65#define SekPcS68k fm68k_get_pc(&PicoCpuFS68k)\r
12da51c2 66#define SekDar(x) (x < 8 ? PicoCpuFM68k.dreg[x].D : PicoCpuFM68k.areg[x - 8].D)\r
67#define SekDarS68k(x) (x < 8 ? PicoCpuFS68k.dreg[x].D : PicoCpuFS68k.areg[x - 8].D)\r
5fadfb1c 68#define SekSr PicoCpuFM68k.sr\r
12da51c2 69#define SekSrS68k PicoCpuFS68k.sr\r
70357ce5 70#define SekSetStop(x) { \\r
03e4f2a3 71 PicoCpuFM68k.execinfo &= ~FM68K_HALTED; \\r
72 if (x) { PicoCpuFM68k.execinfo |= FM68K_HALTED; PicoCpuFM68k.io_cycle_counter = 0; } \\r
70357ce5 73}\r
74#define SekSetStopS68k(x) { \\r
03e4f2a3 75 PicoCpuFS68k.execinfo &= ~FM68K_HALTED; \\r
76 if (x) { PicoCpuFS68k.execinfo |= FM68K_HALTED; PicoCpuFS68k.io_cycle_counter = 0; } \\r
70357ce5 77}\r
ed4402a7 78#define SekIsStoppedM68k() (PicoCpuFM68k.execinfo&FM68K_HALTED)\r
ca61ee42 79#define SekIsStoppedS68k() (PicoCpuFS68k.execinfo&FM68K_HALTED)\r
03e4f2a3 80#define SekShouldInterrupt fm68k_would_interrupt()\r
b542be46 81\r
82#define SekInterrupt(irq) PicoCpuFM68k.interrupts[0]=irq\r
5fadfb1c 83#define SekIrqLevel PicoCpuFM68k.interrupts[0]\r
b542be46 84\r
cc68a136 85#endif\r
86\r
87#ifdef EMU_M68K\r
88#include "../cpu/musashi/m68kcpu.h"\r
3aa1e148 89extern m68ki_cpu_core PicoCpuMM68k, PicoCpuMS68k;\r
cc68a136 90#ifndef SekCyclesLeft\r
ae214f1c 91#define SekCyclesLeft PicoCpuMM68k.cyc_remaining_cycles\r
92#define SekCyclesLeftS68k PicoCpuMS68k.cyc_remaining_cycles\r
3aa1e148 93#define SekPc m68k_get_reg(&PicoCpuMM68k, M68K_REG_PC)\r
94#define SekPcS68k m68k_get_reg(&PicoCpuMS68k, M68K_REG_PC)\r
12da51c2 95#define SekDar(x) PicoCpuMM68k.dar[x]\r
96#define SekDarS68k(x) PicoCpuMS68k.dar[x]\r
97#define SekSr m68k_get_reg(&PicoCpuMM68k, M68K_REG_SR)\r
98#define SekSrS68k m68k_get_reg(&PicoCpuMS68k, M68K_REG_SR)\r
7a1f6e45 99#define SekSetStop(x) { \\r
3aa1e148 100 if(x) { SET_CYCLES(0); PicoCpuMM68k.stopped=STOP_LEVEL_STOP; } \\r
101 else PicoCpuMM68k.stopped=0; \\r
7a1f6e45 102}\r
103#define SekSetStopS68k(x) { \\r
3aa1e148 104 if(x) { SET_CYCLES(0); PicoCpuMS68k.stopped=STOP_LEVEL_STOP; } \\r
105 else PicoCpuMS68k.stopped=0; \\r
7a1f6e45 106}\r
ed4402a7 107#define SekIsStoppedM68k() (PicoCpuMM68k.stopped==STOP_LEVEL_STOP)\r
ca61ee42 108#define SekIsStoppedS68k() (PicoCpuMS68k.stopped==STOP_LEVEL_STOP)\r
03e4f2a3 109#define SekShouldInterrupt (CPU_INT_LEVEL > FLAG_INT_MASK)\r
b542be46 110\r
71de3cd9 111#define SekInterrupt(irq) { \\r
b542be46 112 void *oldcontext = m68ki_cpu_p; \\r
113 m68k_set_context(&PicoCpuMM68k); \\r
114 m68k_set_irq(irq); \\r
115 m68k_set_context(oldcontext); \\r
116}\r
5fadfb1c 117#define SekIrqLevel (PicoCpuMM68k.int_level >> 8)\r
b542be46 118\r
cc68a136 119#endif\r
ef090115 120#endif // EMU_M68K\r
cc68a136 121\r
ae214f1c 122// while running, cnt represents target of current timeslice\r
123// while not in SekRun(), it's actual cycles done\r
124// (but always use SekCyclesDone() if you need current position)\r
125// cnt may change if timeslice is ended prematurely or extended,\r
126// so we use SekCycleAim for the actual target\r
127extern unsigned int SekCycleCnt;\r
128extern unsigned int SekCycleAim;\r
cc68a136 129\r
ae214f1c 130// number of cycles done (can be checked anywhere)\r
131#define SekCyclesDone() (SekCycleCnt - SekCyclesLeft)\r
132\r
133// burn cycles while not in SekRun() and while in\r
134#define SekCyclesBurn(c) SekCycleCnt += c\r
135#define SekCyclesBurnRun(c) SekCyclesLeft -= c\r
cc68a136 136\r
ae214f1c 137// note: sometimes may extend timeslice to delay an irq\r
cc68a136 138#define SekEndRun(after) { \\r
ae214f1c 139 SekCycleCnt -= SekCyclesLeft - (after); \\r
140 SekCyclesLeft = after; \\r
cc68a136 141}\r
142\r
ae214f1c 143extern unsigned int SekCycleCntS68k;\r
144extern unsigned int SekCycleAimS68k;\r
145\r
07ceafdb 146#define SekEndRunS68k(after) { \\r
ae214f1c 147 if (SekCyclesLeftS68k > (after)) { \\r
148 SekCycleCntS68k -= SekCyclesLeftS68k - (after); \\r
149 SekCyclesLeftS68k = after; \\r
150 } \\r
07ceafdb 151}\r
152\r
ae214f1c 153#define SekCyclesDoneS68k() (SekCycleCntS68k - SekCyclesLeftS68k)\r
cc68a136 154\r
ae214f1c 155// compare cycles, handling overflows\r
156// check if a > b\r
157#define CYCLES_GT(a, b) \\r
158 ((int)((a) - (b)) > 0)\r
159// check if a >= b\r
160#define CYCLES_GE(a, b) \\r
161 ((int)((a) - (b)) >= 0)\r
cc68a136 162\r
b542be46 163// ----------------------- Z80 CPU -----------------------\r
164\r
b4db550e 165#if defined(_USE_DRZ80)\r
dca310c4 166#include "../cpu/DrZ80/drz80.h"\r
b542be46 167\r
168extern struct DrZ80 drZ80;\r
169\r
170#define z80_run(cycles) ((cycles) - DrZ80Run(&drZ80, cycles))\r
171#define z80_run_nr(cycles) DrZ80Run(&drZ80, cycles)\r
4936aac1 172#define z80_int() drZ80.Z80_IRQ = 1\r
4b9c5888 173\r
174#define z80_cyclesLeft drZ80.cycles\r
19954be1 175#define z80_pc() (drZ80.Z80PC - drZ80.Z80PC_BASE)\r
b542be46 176\r
177#elif defined(_USE_CZ80)\r
dca310c4 178#include "../cpu/cz80/cz80.h"\r
b542be46 179\r
180#define z80_run(cycles) Cz80_Exec(&CZ80, cycles)\r
181#define z80_run_nr(cycles) Cz80_Exec(&CZ80, cycles)\r
182#define z80_int() Cz80_Set_IRQ(&CZ80, 0, HOLD_LINE)\r
4b9c5888 183\r
184#define z80_cyclesLeft (CZ80.ICount - CZ80.ExtraCycles)\r
19954be1 185#define z80_pc() Cz80_Get_Reg(&CZ80, CZ80_PC)\r
b542be46 186\r
187#else\r
188\r
189#define z80_run(cycles) (cycles)\r
190#define z80_run_nr(cycles)\r
191#define z80_int()\r
b542be46 192\r
193#endif\r
194\r
b4db550e 195#define Z80_STATE_SIZE 0x60\r
196\r
ae214f1c 197extern unsigned int last_z80_sync;\r
4b9c5888 198extern int z80_cycle_cnt; /* 'done' z80 cycles before z80_run() */\r
199extern int z80_cycle_aim;\r
200extern int z80_scanline;\r
201extern int z80_scanline_cycles; /* cycles done until z80_scanline */\r
202\r
203#define z80_resetCycles() \\r
ae214f1c 204 last_z80_sync = SekCyclesDone(); \\r
4b9c5888 205 z80_cycle_cnt = z80_cycle_aim = z80_scanline = z80_scanline_cycles = 0;\r
206\r
207#define z80_cyclesDone() \\r
208 (z80_cycle_aim - z80_cyclesLeft)\r
209\r
210#define cycles_68k_to_z80(x) ((x)*957 >> 11)\r
211\r
acd35d4c 212// ----------------------- SH2 CPU -----------------------\r
213\r
41397701 214#include "cpu/sh2/sh2.h"\r
acd35d4c 215\r
1d7a28a7 216extern SH2 sh2s[2];\r
217#define msh2 sh2s[0]\r
218#define ssh2 sh2s[1]\r
219\r
679af8a3 220#ifndef DRC_SH2\r
19886062 221# define sh2_end_run(sh2, after_) do { \\r
222 if ((sh2)->icount > (after_)) { \\r
c1931173 223 (sh2)->cycles_timeslice -= (sh2)->icount - (after_); \\r
19886062 224 (sh2)->icount = after_; \\r
a8fd6e37 225 } \\r
226} while (0)\r
19886062 227# define sh2_cycles_left(sh2) (sh2)->icount\r
8a847c12 228# define sh2_burn_cycles(sh2, n) (sh2)->icount -= n\r
f81107f5 229# define sh2_pc(sh2) (sh2)->ppc\r
679af8a3 230#else\r
19886062 231# define sh2_end_run(sh2, after_) do { \\r
232 int left_ = (signed int)(sh2)->sr >> 12; \\r
233 if (left_ > (after_)) { \\r
c1931173 234 (sh2)->cycles_timeslice -= left_ - (after_); \\r
f4c0720c 235 (sh2)->sr &= 0xfff; \\r
19886062 236 (sh2)->sr |= (after_) << 12; \\r
a8fd6e37 237 } \\r
238} while (0)\r
19886062 239# define sh2_cycles_left(sh2) ((signed int)(sh2)->sr >> 12)\r
8a847c12 240# define sh2_burn_cycles(sh2, n) (sh2)->sr -= ((n) << 12)\r
f81107f5 241# define sh2_pc(sh2) (sh2)->pc\r
679af8a3 242#endif\r
266c6afa 243\r
19886062 244#define sh2_cycles_done(sh2) ((int)(sh2)->cycles_timeslice - sh2_cycles_left(sh2))\r
a7f82a77 245#define sh2_cycles_done_t(sh2) \\r
246 ((sh2)->m68krcycles_done * 3 + sh2_cycles_done(sh2))\r
19886062 247#define sh2_cycles_done_m68k(sh2) \\r
248 ((sh2)->m68krcycles_done + (sh2_cycles_done(sh2) / 3))\r
249\r
4ea707e1 250#define sh2_reg(c, x) (c) ? ssh2.r[x] : msh2.r[x]\r
251#define sh2_gbr(c) (c) ? ssh2.gbr : msh2.gbr\r
252#define sh2_vbr(c) (c) ? ssh2.vbr : msh2.vbr\r
6add7875 253#define sh2_sr(c) (((c) ? ssh2.sr : msh2.sr) & 0xfff)\r
acd35d4c 254\r
83ff19ec 255#define sh2_set_gbr(c, v) \\r
256 { if (c) ssh2.gbr = v; else msh2.gbr = v; }\r
257#define sh2_set_vbr(c, v) \\r
258 { if (c) ssh2.vbr = v; else msh2.vbr = v; }\r
259\r
f8675e28 260#define elprintf_sh2(sh2, w, f, ...) \\r
261 elprintf(w,"%csh2 "f,(sh2)->is_slave?'s':'m',##__VA_ARGS__)\r
262\r
cc68a136 263// ---------------------------------------------------------\r
264\r
265// main oscillator clock which controls timing\r
266#define OSC_NTSC 53693100\r
b8cbd802 267#define OSC_PAL 53203424\r
cc68a136 268\r
269struct PicoVideo\r
270{\r
271 unsigned char reg[0x20];\r
b8cbd802 272 unsigned int command; // 32-bit Command\r
273 unsigned char pending; // 1 if waiting for second half of 32-bit command\r
274 unsigned char type; // Command type (v/c/vsram read/write)\r
275 unsigned short addr; // Read/Write address\r
276 int status; // Status bits\r
cc68a136 277 unsigned char pending_ints; // pending interrupts: ??VH????\r
b8cbd802 278 signed char lwrite_cnt; // VDP write count during active display line\r
9761a7d0 279 unsigned short v_counter; // V-counter\r
280 unsigned char pad[0x10];\r
cc68a136 281};\r
282\r
283struct PicoMisc\r
284{\r
285 unsigned char rotate;\r
286 unsigned char z80Run;\r
e5503e2f 287 unsigned char padTHPhase[2]; // 02 phase of gamepad TH switches\r
2aa27095 288 unsigned short scanline; // 04 0 to 261||311\r
e5503e2f 289 char dirtyPal; // 06 Is the palette dirty (1 - change @ this frame, 2 - some time before)\r
290 unsigned char hardware; // 07 Hardware value for country\r
291 unsigned char pal; // 08 1=PAL 0=NTSC\r
45f2f245 292 unsigned char sram_reg; // 09 SRAM reg. See SRR_* below\r
e5503e2f 293 unsigned short z80_bank68k; // 0a\r
be2c4208 294 unsigned short pad0;\r
295 unsigned char pad1;\r
0ace9b9a 296 unsigned char z80_reset; // 0f z80 reset held\r
e5503e2f 297 unsigned char padDelay[2]; // 10 gamepad phase time outs, so we count a delay\r
1dceadae 298 unsigned short eeprom_addr; // EEPROM address register\r
45f2f245 299 unsigned char eeprom_cycle; // EEPROM cycle number\r
1dceadae 300 unsigned char eeprom_slave; // EEPROM slave word for X24C02 and better SRAMs\r
45f2f245 301 unsigned char eeprom_status;\r
be2c4208 302 unsigned char pad2;\r
053fd9b4 303 unsigned short dma_xfers; // 18\r
45f2f245 304 unsigned char eeprom_wb[2]; // EEPROM latch/write buffer\r
053fd9b4 305 unsigned int frame_count; // 1c for movies and idle det\r
cc68a136 306};\r
307\r
b4db550e 308struct PicoMS\r
309{\r
310 unsigned char carthw[0x10];\r
311 unsigned char io_ctl;\r
312 unsigned char pad[0x4f];\r
313};\r
314\r
cc68a136 315// some assembly stuff depend on these, do not touch!\r
316struct Pico\r
317{\r
318 unsigned char ram[0x10000]; // 0x00000 scratch ram\r
200772b7 319 union { // vram is byteswapped for easier reads when drawing\r
2ec9bec5 320 unsigned short vram[0x8000]; // 0x10000\r
321 unsigned char vramb[0x4000]; // VRAM in SMS mode\r
322 };\r
cc68a136 323 unsigned char zram[0x2000]; // 0x20000 Z80 ram\r
b4db550e 324 unsigned char ioports[0x10]; // XXX: fix asm and mv\r
325 unsigned char pad[0xf0]; // unused\r
cc68a136 326 unsigned short cram[0x40]; // 0x22100\r
327 unsigned short vsram[0x40]; // 0x22180\r
328\r
329 unsigned char *rom; // 0x22200\r
0219d379 330 unsigned int romsize; // 0x22204 (on 32bits)\r
cc68a136 331\r
332 struct PicoMisc m;\r
333 struct PicoVideo video;\r
b4db550e 334 struct PicoMS ms;\r
cc68a136 335};\r
336\r
337// sram\r
45f2f245 338#define SRR_MAPPED (1 << 0)\r
339#define SRR_READONLY (1 << 1)\r
340\r
341#define SRF_ENABLED (1 << 0)\r
342#define SRF_EEPROM (1 << 1)\r
af37bca8 343\r
cc68a136 344struct PicoSRAM\r
345{\r
4ff2d527 346 unsigned char *data; // actual data\r
347 unsigned int start; // start address in 68k address space\r
cc68a136 348 unsigned int end;\r
45f2f245 349 unsigned char flags; // 0c: SRF_*\r
1dceadae 350 unsigned char unused2;\r
cc68a136 351 unsigned char changed;\r
45f2f245 352 unsigned char eeprom_type; // eeprom type: 0: 7bit (24C01), 2: 2 addr words (X24C02+), 3: 3 addr words\r
353 unsigned char unused3;\r
1dceadae 354 unsigned char eeprom_bit_cl; // bit number for cl\r
355 unsigned char eeprom_bit_in; // bit number for in\r
356 unsigned char eeprom_bit_out; // bit number for out\r
45f2f245 357 unsigned int size;\r
cc68a136 358};\r
359\r
360// MCD\r
361#include "cd/cd_sys.h"\r
362#include "cd/LC89510.h"\r
d1df8786 363#include "cd/gfx_cd.h"\r
cc68a136 364\r
4f265db7 365struct mcd_pcm\r
366{\r
367 unsigned char control; // reg7\r
368 unsigned char enabled; // reg8\r
369 unsigned char cur_ch;\r
370 unsigned char bank;\r
371 int pad1;\r
372\r
4ff2d527 373 struct pcm_chan // 08, size 0x10\r
4f265db7 374 {\r
375 unsigned char regs[8];\r
4ff2d527 376 unsigned int addr; // .08: played sample address\r
4f265db7 377 int pad;\r
378 } ch[8];\r
379};\r
380\r
c459aefd 381struct mcd_misc\r
382{\r
383 unsigned short hint_vector;\r
384 unsigned char busreq;\r
51a902ae 385 unsigned char s68k_pend_ints;\r
ef090115 386 unsigned int state_flags; // 04: emu state: reset_pending\r
ae214f1c 387 unsigned int stopwatch_base_c;\r
388 unsigned int pad[3];\r
6cadc2da 389 unsigned char bcram_reg; // 18: battery-backed RAM cart register\r
390 unsigned char pad2;\r
391 unsigned short pad3;\r
ae214f1c 392 int pad4[9];\r
c459aefd 393};\r
394\r
cc68a136 395typedef struct\r
396{\r
4ff2d527 397 unsigned char bios[0x20000]; // 000000: 128K\r
398 union { // 020000: 512K\r
fa1e5e29 399 unsigned char prg_ram[0x80000];\r
cc68a136 400 unsigned char prg_ram_b[4][0x20000];\r
401 };\r
4ff2d527 402 union { // 0a0000: 256K\r
fa1e5e29 403 struct {\r
404 unsigned char word_ram2M[0x40000];\r
dca310c4 405 unsigned char unused0[0x20000];\r
fa1e5e29 406 };\r
407 struct {\r
dca310c4 408 unsigned char unused1[0x20000];\r
fa1e5e29 409 unsigned char word_ram1M[2][0x20000];\r
410 };\r
411 };\r
4ff2d527 412 union { // 100000: 64K\r
fa1e5e29 413 unsigned char pcm_ram[0x10000];\r
4f265db7 414 unsigned char pcm_ram_b[0x10][0x1000];\r
415 };\r
895d1512 416 // FIXME: should be short\r
4ff2d527 417 unsigned char s68k_regs[0x200]; // 110000: GA, not CPU regs\r
418 unsigned char bram[0x2000]; // 110200: 8K\r
419 struct mcd_misc m; // 112200: misc\r
420 struct mcd_pcm pcm; // 112240:\r
75736070 421 _scd_toc TOC; // not to be saved\r
cc68a136 422 CDD cdd;\r
423 CDC cdc;\r
424 _scd scd;\r
d1df8786 425 Rot_Comp rot_comp;\r
cc68a136 426} mcd_state;\r
427\r
be2c4208 428// XXX: this will need to be reworked for cart+cd support.\r
cc68a136 429#define Pico_mcd ((mcd_state *)Pico.rom)\r
430\r
be2c4208 431// 32X\r
acd35d4c 432#define P32XS_FM (1<<15)\r
83ff19ec 433#define P32XS_REN (1<< 7)\r
434#define P32XS_nRES (1<< 1)\r
435#define P32XS_ADEN (1<< 0)\r
acd35d4c 436#define P32XS2_ADEN (1<< 9)\r
5e128c6d 437#define P32XS_FULL (1<< 7) // DREQ FIFO full\r
4ea707e1 438#define P32XS_68S (1<< 2)\r
97d3f47f 439#define P32XS_DMA (1<< 1)\r
4ea707e1 440#define P32XS_RV (1<< 0)\r
acd35d4c 441\r
5e128c6d 442#define P32XV_nPAL (1<<15) // VDP\r
acd35d4c 443#define P32XV_PRI (1<< 7)\r
4ea707e1 444#define P32XV_Mx (3<< 0) // display mode mask\r
974fdb5b 445\r
e51e5983 446#define P32XV_SFT (1<< 0)\r
447\r
acd35d4c 448#define P32XV_VBLK (1<<15)\r
449#define P32XV_HBLK (1<<14)\r
450#define P32XV_PEN (1<<13)\r
451#define P32XV_nFEN (1<< 1)\r
452#define P32XV_FS (1<< 0)\r
974fdb5b 453\r
df63f1a6 454#define P32XP_RTP (1<<7) // PWM control\r
455#define P32XP_FULL (1<<15) // PWM pulse\r
db1d3564 456#define P32XP_EMPTY (1<<14)\r
457\r
419973a6 458#define P32XF_68KCPOLL (1 << 0)\r
459#define P32XF_68KVPOLL (1 << 1)\r
460#define P32XF_Z80_32X_IO (1 << 7) // z80 does 32x io\r
4ea707e1 461\r
462#define P32XI_VRES (1 << 14/2) // IRL/2\r
463#define P32XI_VINT (1 << 12/2)\r
464#define P32XI_HINT (1 << 10/2)\r
465#define P32XI_CMD (1 << 8/2)\r
466#define P32XI_PWM (1 << 6/2)\r
467\r
1d7a28a7 468// peripheral reg access\r
469#define PREG8(regs,offs) ((unsigned char *)regs)[offs ^ 3]\r
470\r
7eaa3812 471#define DMAC_FIFO_LEN (4*2)\r
db1d3564 472#define PWM_BUFF_LEN 1024 // in one channel samples\r
266c6afa 473\r
f4bb5d6b 474#define SH2_DRCBLK_RAM_SHIFT 1\r
475#define SH2_DRCBLK_DA_SHIFT 1\r
476\r
f81107f5 477#define SH2_READ_SHIFT 25\r
e05b81fc 478#define SH2_WRITE_SHIFT 25\r
479\r
be2c4208 480struct Pico32x\r
481{\r
482 unsigned short regs[0x20];\r
5a681086 483 unsigned short vdp_regs[0x10]; // 0x40\r
484 unsigned short sh2_regs[3]; // 0x60\r
be2c4208 485 unsigned char pending_fb;\r
974fdb5b 486 unsigned char dirty_pal;\r
266c6afa 487 unsigned int emu_flags;\r
4ea707e1 488 unsigned char sh2irq_mask[2];\r
489 unsigned char sh2irqi[2]; // individual\r
490 unsigned int sh2irqs; // common irqs\r
491 unsigned short dmac_fifo[DMAC_FIFO_LEN];\r
7eaa3812 492 unsigned int pad[4];\r
df63f1a6 493 unsigned int dmac0_fifo_ptr;\r
4a1fb183 494 unsigned short vdp_fbcr_fake;\r
7eaa3812 495 unsigned short pad2;\r
a8fd6e37 496 unsigned char comm_dirty_68k;\r
497 unsigned char comm_dirty_sh2;\r
df63f1a6 498 unsigned char pwm_irq_cnt;\r
499 unsigned char pad1;\r
a7f82a77 500 unsigned short pwm_p[2]; // pwm pos in fifo\r
501 unsigned int pwm_cycle_p; // pwm play cursor (32x cycles)\r
502 unsigned int reserved[6];\r
974fdb5b 503};\r
504\r
505struct Pico32xMem\r
506{\r
507 unsigned char sdram[0x40000];\r
f4bb5d6b 508#ifdef DRC_SH2\r
509 unsigned short drcblk_ram[1 << (18 - SH2_DRCBLK_RAM_SHIFT)];\r
510#endif\r
b78efee2 511 unsigned short dram[2][0x20000/2]; // AKA fb\r
b4db550e 512 union {\r
513 unsigned char m68k_rom[0x100];\r
514 unsigned char m68k_rom_bank[0x10000]; // M68K_BANK_SIZE\r
515 };\r
f4bb5d6b 516#ifdef DRC_SH2\r
517 unsigned short drcblk_da[2][1 << (12 - SH2_DRCBLK_DA_SHIFT)];\r
518#endif\r
895d1512 519 union {\r
520 unsigned char b[0x800];\r
521 unsigned short w[0x800/2];\r
522 } sh2_rom_m;\r
523 union {\r
524 unsigned char b[0x400];\r
525 unsigned short w[0x400/2];\r
526 } sh2_rom_s;\r
974fdb5b 527 unsigned short pal[0x100];\r
5e128c6d 528 unsigned short pal_native[0x100]; // converted to native (for renderer)\r
db1d3564 529 signed short pwm[2*PWM_BUFF_LEN]; // PWM buffer for current frame\r
8ce9c3a7 530 signed short pwm_current[2]; // current converted samples\r
531 unsigned short pwm_fifo[2][4]; // [0] - current raw, others - fifo entries\r
be2c4208 532};\r
d49b10c2 533\r
c8d1e9b6 534// area.c\r
fad24893 535extern void (*PicoLoadStateHook)(void);\r
51a902ae 536\r
945c2fdc 537typedef struct {\r
538 int chunk;\r
539 int size;\r
540 void *ptr;\r
541} carthw_state_chunk;\r
542extern carthw_state_chunk *carthw_chunks;\r
543#define CHUNK_CARTHW 64\r
544\r
c8d1e9b6 545// cart.c\r
b4db550e 546extern int PicoCartResize(int newsize);\r
547extern void Byteswap(void *dst, const void *src, int len);\r
45f2f245 548extern void (*PicoCartMemSetup)(void);\r
e807ac75 549extern void (*PicoCartUnloadHook)(void);\r
1dceadae 550\r
c8d1e9b6 551// debug.c\r
b5e5172d 552int CM_compareRun(int cyc, int is_sub);\r
03e4f2a3 553\r
c8d1e9b6 554// draw.c\r
eff55556 555PICO_INTERNAL void PicoFrameStart(void);\r
b6d7ac70 556void PicoDrawSync(int to, int blank_last_line);\r
200772b7 557void BackFill(int reg7, int sh);\r
5a681086 558void FinalizeLine555(int sh, int line);\r
f4750ee0 559extern int (*PicoScanBegin)(unsigned int num);\r
560extern int (*PicoScanEnd)(unsigned int num);\r
b6d7ac70 561extern int DrawScanline;\r
f579f7b8 562#define MAX_LINE_SPRITES 29\r
563extern unsigned char HighLnSpr[240][3 + MAX_LINE_SPRITES];\r
5a681086 564extern void *DrawLineDestBase;\r
565extern int DrawLineDestIncrement;\r
cc68a136 566\r
c8d1e9b6 567// draw2.c\r
eff55556 568PICO_INTERNAL void PicoFrameFull();\r
cc68a136 569\r
200772b7 570// mode4.c\r
571void PicoFrameStartMode4(void);\r
572void PicoLineMode4(int line);\r
573void PicoDoHighPal555M4(void);\r
5a681086 574void PicoDrawSetOutputMode4(pdso_t which);\r
200772b7 575\r
c8d1e9b6 576// memory.c\r
eff55556 577PICO_INTERNAL void PicoMemSetup(void);\r
af37bca8 578unsigned int PicoRead8_io(unsigned int a);\r
579unsigned int PicoRead16_io(unsigned int a);\r
580void PicoWrite8_io(unsigned int a, unsigned int d);\r
581void PicoWrite16_io(unsigned int a, unsigned int d);\r
582\r
583// pico/memory.c\r
584PICO_INTERNAL void PicoMemSetupPico(void);\r
cc68a136 585\r
c8d1e9b6 586// cd/memory.c\r
eff55556 587PICO_INTERNAL void PicoMemSetupCD(void);\r
ae214f1c 588void pcd_state_loaded_mem(void);\r
cc68a136 589\r
c8d1e9b6 590// pico.c\r
cc68a136 591extern struct Pico Pico;\r
592extern struct PicoSRAM SRam;\r
5f9a0d16 593extern int PicoPadInt[2];\r
cc68a136 594extern int emustatus;\r
5e128c6d 595extern int scanlines_total;\r
f8ef8ff7 596extern void (*PicoResetHook)(void);\r
b0677887 597extern void (*PicoLineHook)(void);\r
1e6b5e39 598PICO_INTERNAL int CheckDMA(void);\r
599PICO_INTERNAL void PicoDetectRegion(void);\r
ae214f1c 600PICO_INTERNAL void PicoSyncZ80(unsigned int m68k_cycles_done);\r
cc68a136 601\r
c8d1e9b6 602// cd/pico.c\r
ae214f1c 603#define PCDS_IEN1 (1<<1)\r
604#define PCDS_IEN2 (1<<2)\r
605#define PCDS_IEN3 (1<<3)\r
606#define PCDS_IEN4 (1<<4)\r
607#define PCDS_IEN5 (1<<5)\r
608#define PCDS_IEN6 (1<<6)\r
609\r
2aa27095 610PICO_INTERNAL void PicoInitMCD(void);\r
e5f426aa 611PICO_INTERNAL void PicoExitMCD(void);\r
1cb1584b 612PICO_INTERNAL void PicoPowerMCD(void);\r
2aa27095 613PICO_INTERNAL int PicoResetMCD(void);\r
614PICO_INTERNAL void PicoFrameMCD(void);\r
cc68a136 615\r
ae214f1c 616enum pcd_event {\r
617 PCD_EVENT_CDC,\r
618 PCD_EVENT_TIMER3,\r
619 PCD_EVENT_GFX,\r
620 PCD_EVENT_DMA,\r
621 PCD_EVENT_COUNT,\r
622};\r
623extern unsigned int pcd_event_times[PCD_EVENT_COUNT];\r
624void pcd_event_schedule(unsigned int now, enum pcd_event event, int after);\r
625void pcd_event_schedule_s68k(enum pcd_event event, int after);\r
626unsigned int pcd_cycles_m68k_to_s68k(unsigned int c);\r
627void pcd_state_loaded(void);\r
628\r
c8d1e9b6 629// pico/pico.c\r
2aa27095 630PICO_INTERNAL void PicoInitPico(void);\r
ed367a3f 631PICO_INTERNAL void PicoReratePico(void);\r
9037e45d 632\r
c8d1e9b6 633// pico/xpcm.c\r
ef4eb506 634PICO_INTERNAL void PicoPicoPCMUpdate(short *buffer, int length, int stereo);\r
635PICO_INTERNAL void PicoPicoPCMReset(void);\r
213c16ad 636PICO_INTERNAL void PicoPicoPCMRerate(int xpcm_rate);\r
ef4eb506 637\r
c8d1e9b6 638// sek.c\r
2aa27095 639PICO_INTERNAL void SekInit(void);\r
640PICO_INTERNAL int SekReset(void);\r
3aa1e148 641PICO_INTERNAL void SekState(int *data);\r
eff55556 642PICO_INTERNAL void SekSetRealTAS(int use_real);\r
b4db550e 643PICO_INTERNAL void SekPackCpu(unsigned char *cpu, int is_sub);\r
644PICO_INTERNAL void SekUnpackCpu(const unsigned char *cpu, int is_sub);\r
5f9a0d16 645void SekStepM68k(void);\r
053fd9b4 646void SekInitIdleDet(void);\r
647void SekFinishIdleDet(void);\r
12da51c2 648#if defined(CPU_CMP_R) || defined(CPU_CMP_W)\r
649void SekTrace(int is_s68k);\r
650#else\r
651#define SekTrace(x)\r
652#endif\r
cc68a136 653\r
c8d1e9b6 654// cd/sek.c\r
2aa27095 655PICO_INTERNAL void SekInitS68k(void);\r
656PICO_INTERNAL int SekResetS68k(void);\r
657PICO_INTERNAL int SekInterruptS68k(int irq);\r
cc68a136 658\r
7a93adeb 659// sound/sound.c\r
c9e1affc 660PICO_INTERNAL void cdda_start_play();\r
661extern short cdda_out_buffer[2*1152];\r
7a93adeb 662extern int PsndLen_exc_cnt;\r
663extern int PsndLen_exc_add;\r
48dc74f2 664extern int timer_a_next_oflow, timer_a_step; // in z80 cycles\r
665extern int timer_b_next_oflow, timer_b_step;\r
43e6eaad 666\r
667void ym2612_sync_timers(int z80_cycles, int mode_old, int mode_new);\r
d2721b08 668void ym2612_pack_state(void);\r
453d2a6e 669void ym2612_unpack_state(void);\r
4b9c5888 670\r
e53704e6 671#define TIMER_NO_OFLOW 0x70000000\r
45a1ef71 672// tA = 72 * (1024 - NA) / M\r
673#define TIMER_A_TICK_ZCYCLES 17203\r
674// tB = 1152 * (256 - NA) / M\r
675#define TIMER_B_TICK_ZCYCLES 262800 // 275251 broken, see Dai Makaimura\r
e53704e6 676\r
4b9c5888 677#define timers_cycle() \\r
e53704e6 678 if (timer_a_next_oflow > 0 && timer_a_next_oflow < TIMER_NO_OFLOW) \\r
43e6eaad 679 timer_a_next_oflow -= Pico.m.pal ? 70938*256 : 59659*256; \\r
e53704e6 680 if (timer_b_next_oflow > 0 && timer_b_next_oflow < TIMER_NO_OFLOW) \\r
43e6eaad 681 timer_b_next_oflow -= Pico.m.pal ? 70938*256 : 59659*256; \\r
682 ym2612_sync_timers(0, ym2612.OPN.ST.mode, ym2612.OPN.ST.mode);\r
4b9c5888 683\r
684#define timers_reset() \\r
e53704e6 685 timer_a_next_oflow = timer_b_next_oflow = TIMER_NO_OFLOW; \\r
48dc74f2 686 timer_a_step = TIMER_A_TICK_ZCYCLES * 1024; \\r
687 timer_b_step = TIMER_B_TICK_ZCYCLES * 256;\r
43e6eaad 688\r
7a93adeb 689\r
c8d1e9b6 690// videoport.c\r
eff55556 691PICO_INTERNAL_ASM void PicoVideoWrite(unsigned int a,unsigned short d);\r
692PICO_INTERNAL_ASM unsigned int PicoVideoRead(unsigned int a);\r
9761a7d0 693PICO_INTERNAL_ASM unsigned int PicoVideoRead8(unsigned int a);\r
5de27868 694extern int (*PicoDmaHook)(unsigned int source, int len, unsigned short **srcp, unsigned short **limitp);\r
cc68a136 695\r
c8d1e9b6 696// misc.c\r
eff55556 697PICO_INTERNAL_ASM void memcpy16(unsigned short *dest, unsigned short *src, int count);\r
698PICO_INTERNAL_ASM void memcpy16bswap(unsigned short *dest, void *src, int count);\r
699PICO_INTERNAL_ASM void memcpy32(int *dest, int *src, int count); // 32bit word count\r
700PICO_INTERNAL_ASM void memset32(int *dest, int c, int count);\r
cc68a136 701\r
45f2f245 702// eeprom.c\r
703void EEPROM_write8(unsigned int a, unsigned int d);\r
704void EEPROM_write16(unsigned int d);\r
705unsigned int EEPROM_read(void);\r
706\r
c8d1e9b6 707// z80 functionality wrappers\r
708PICO_INTERNAL void z80_init(void);\r
b4db550e 709PICO_INTERNAL void z80_pack(void *data);\r
710PICO_INTERNAL int z80_unpack(const void *data);\r
c8d1e9b6 711PICO_INTERNAL void z80_reset(void);\r
712PICO_INTERNAL void z80_exit(void);\r
c8d1e9b6 713\r
714// cd/misc.c\r
eff55556 715PICO_INTERNAL_ASM void wram_2M_to_1M(unsigned char *m);\r
716PICO_INTERNAL_ASM void wram_1M_to_2M(unsigned char *m);\r
717\r
718// cd/buffering.c\r
719PICO_INTERNAL void PicoCDBufferRead(void *dest, int lba);\r
720\r
721// sound/sound.c\r
9d917eea 722PICO_INTERNAL void PsndReset(void);\r
4b9c5888 723PICO_INTERNAL void PsndDoDAC(int line_to);\r
9d917eea 724PICO_INTERNAL void PsndClear(void);\r
7b3f44c6 725PICO_INTERNAL void PsndGetSamples(int y);\r
2ec9bec5 726PICO_INTERNAL void PsndGetSamplesMS(void);\r
4b9c5888 727extern int PsndDacLine;\r
cc68a136 728\r
3e49ffd0 729// sms.c\r
f3a57b2d 730#ifndef NO_SMS\r
3e49ffd0 731void PicoPowerMS(void);\r
2ec9bec5 732void PicoResetMS(void);\r
3e49ffd0 733void PicoMemSetupMS(void);\r
b4db550e 734void PicoStateLoadedMS(void);\r
3e49ffd0 735void PicoFrameMS(void);\r
87b0845f 736void PicoFrameDrawOnlyMS(void);\r
f3a57b2d 737#else\r
738#define PicoPowerMS()\r
739#define PicoResetMS()\r
740#define PicoMemSetupMS()\r
741#define PicoStateLoadedMS()\r
742#define PicoFrameMS()\r
743#define PicoFrameDrawOnlyMS()\r
744#endif\r
3e49ffd0 745\r
be2c4208 746// 32x/32x.c\r
f3a57b2d 747#ifndef NO_32X\r
be2c4208 748extern struct Pico32x Pico32x;\r
6a98f03e 749enum p32x_event {\r
750 P32X_EVENT_PWM,\r
751 P32X_EVENT_FILLEND,\r
5ac99d9a 752 P32X_EVENT_HINT,\r
6a98f03e 753 P32X_EVENT_COUNT,\r
754};\r
ae214f1c 755extern unsigned int p32x_event_times[P32X_EVENT_COUNT];\r
6a98f03e 756\r
be2c4208 757void Pico32xInit(void);\r
974fdb5b 758void PicoPower32x(void);\r
be2c4208 759void PicoReset32x(void);\r
974fdb5b 760void Pico32xStartup(void);\r
5e49c3a8 761void PicoUnload32x(void);\r
974fdb5b 762void PicoFrame32x(void);\r
27e26273 763void Pico32xStateLoaded(int is_early);\r
ed4402a7 764void p32x_sync_sh2s(unsigned int m68k_target);\r
19886062 765void p32x_sync_other_sh2(SH2 *sh2, unsigned int m68k_target);\r
4d5dfee8 766void p32x_update_irls(SH2 *active_sh2, int m68k_cycles);\r
9e1fa0a6 767void p32x_trigger_irq(SH2 *sh2, int m68k_cycles, unsigned int mask);\r
768void p32x_update_cmd_irq(SH2 *sh2, int m68k_cycles);\r
83ff19ec 769void p32x_reset_sh2s(void);\r
19886062 770void p32x_event_schedule(unsigned int now, enum p32x_event event, int after);\r
771void p32x_event_schedule_sh2(SH2 *sh2, enum p32x_event event, int after);\r
5ac99d9a 772void p32x_schedule_hint(SH2 *sh2, int m68k_cycles);\r
a8fd6e37 773\r
be2c4208 774// 32x/memory.c\r
974fdb5b 775struct Pico32xMem *Pico32xMem;\r
be2c4208 776unsigned int PicoRead8_32x(unsigned int a);\r
777unsigned int PicoRead16_32x(unsigned int a);\r
778void PicoWrite8_32x(unsigned int a, unsigned int d);\r
779void PicoWrite16_32x(unsigned int a, unsigned int d);\r
780void PicoMemSetup32x(void);\r
974fdb5b 781void Pico32xSwapDRAM(int b);\r
27e26273 782void Pico32xMemStateLoaded(void);\r
19886062 783void p32x_m68k_poll_event(unsigned int flags);\r
784void p32x_sh2_poll_event(SH2 *sh2, unsigned int flags, unsigned int m68k_cycles);\r
974fdb5b 785\r
786// 32x/draw.c\r
41946d70 787void PicoDrawSetOutFormat32x(pdso_t which, int use_32x_line_mode);\r
974fdb5b 788void FinalizeLine32xRGB555(int sh, int line);\r
5a681086 789void PicoDraw32xLayer(int offs, int lines, int mdbg);\r
7a961c19 790void PicoDraw32xLayerMdOnly(int offs, int lines);\r
f4750ee0 791extern int (*PicoScan32xBegin)(unsigned int num);\r
792extern int (*PicoScan32xEnd)(unsigned int num);\r
7a961c19 793enum {\r
794 PDM32X_OFF,\r
795 PDM32X_32X_ONLY,\r
796 PDM32X_BOTH,\r
797};\r
5a681086 798extern int Pico32xDrawMode;\r
be2c4208 799\r
db1d3564 800// 32x/pwm.c\r
c1931173 801unsigned int p32x_pwm_read16(unsigned int a, SH2 *sh2,\r
802 unsigned int m68k_cycles);\r
803void p32x_pwm_write16(unsigned int a, unsigned int d,\r
804 SH2 *sh2, unsigned int m68k_cycles);\r
db1d3564 805void p32x_pwm_update(int *buf32, int length, int stereo);\r
045a4c52 806void p32x_pwm_ctl_changed(void);\r
df63f1a6 807void p32x_pwm_schedule(unsigned int m68k_now);\r
19886062 808void p32x_pwm_schedule_sh2(SH2 *sh2);\r
9e1fa0a6 809void p32x_pwm_sync_to_sh2(SH2 *sh2);\r
df63f1a6 810void p32x_pwm_irq_event(unsigned int m68k_now);\r
811void p32x_pwm_state_loaded(void);\r
045a4c52 812\r
813// 32x/sh2soc.c\r
814void p32x_dreq0_trigger(void);\r
815void p32x_dreq1_trigger(void);\r
816void p32x_timers_recalc(void);\r
817void p32x_timers_do(unsigned int m68k_slice);\r
cd0ace28 818void sh2_peripheral_reset(SH2 *sh2);\r
f81107f5 819unsigned int sh2_peripheral_read8(unsigned int a, SH2 *sh2);\r
820unsigned int sh2_peripheral_read16(unsigned int a, SH2 *sh2);\r
821unsigned int sh2_peripheral_read32(unsigned int a, SH2 *sh2);\r
822void sh2_peripheral_write8(unsigned int a, unsigned int d, SH2 *sh2);\r
823void sh2_peripheral_write16(unsigned int a, unsigned int d, SH2 *sh2);\r
824void sh2_peripheral_write32(unsigned int a, unsigned int d, SH2 *sh2);\r
045a4c52 825\r
f3a57b2d 826#else\r
827#define Pico32xInit()\r
828#define PicoPower32x()\r
829#define PicoReset32x()\r
830#define PicoFrame32x()\r
831#define PicoUnload32x()\r
832#define Pico32xStateLoaded()\r
f3a57b2d 833#define FinalizeLine32xRGB555 NULL\r
834#define p32x_pwm_update(...)\r
835#define p32x_timers_recalc()\r
836#endif\r
db1d3564 837\r
45f2f245 838/* avoid dependency on newer glibc */\r
839static __inline int isspace_(int c)\r
840{\r
841 return (0x09 <= c && c <= 0x0d) || c == ' ';\r
842}\r
843\r
f4bb5d6b 844#ifndef ARRAY_SIZE\r
845#define ARRAY_SIZE(x) (sizeof(x) / sizeof(x[0]))\r
846#endif\r
847\r
b8cbd802 848// emulation event logging\r
849#ifndef EL_LOGMASK\r
9c9cda8c 850# ifdef __x86_64__ // HACK\r
851# define EL_LOGMASK (EL_STATUS|EL_IDLE|EL_ANOMALY)\r
852# else\r
1555935b 853# define EL_LOGMASK (EL_STATUS)\r
9c9cda8c 854# endif\r
b8cbd802 855#endif\r
856\r
017512f2 857#define EL_HVCNT 0x00000001 /* hv counter reads */\r
858#define EL_SR 0x00000002 /* SR reads */\r
859#define EL_INTS 0x00000004 /* ints and acks */\r
43e6eaad 860#define EL_YMTIMER 0x00000008 /* ym2612 timer stuff */\r
017512f2 861#define EL_INTSW 0x00000010 /* log irq switching on/off */\r
862#define EL_ASVDP 0x00000020 /* VDP accesses during active scan */\r
863#define EL_VDPDMA 0x00000040 /* VDP DMA transfers and their timing */\r
864#define EL_BUSREQ 0x00000080 /* z80 busreq r/w or reset w */\r
865#define EL_Z80BNK 0x00000100 /* z80 i/o through bank area */\r
866#define EL_SRAMIO 0x00000200 /* sram i/o */\r
867#define EL_EEPROM 0x00000400 /* eeprom debug */\r
868#define EL_UIO 0x00000800 /* unmapped i/o */\r
869#define EL_IO 0x00001000 /* all i/o */\r
870#define EL_CDPOLL 0x00002000 /* MCD: log poll detection */\r
871#define EL_SVP 0x00004000 /* SVP stuff */\r
fa22af4c 872#define EL_PICOHW 0x00008000 /* Pico stuff */\r
053fd9b4 873#define EL_IDLE 0x00010000 /* idle loop det. */\r
af37bca8 874#define EL_CDREGS 0x00020000 /* MCD: register access */\r
875#define EL_CDREG3 0x00040000 /* MCD: register 3 only */\r
be2c4208 876#define EL_32X 0x00080000\r
1b3f5844 877#define EL_PWM 0x00100000 /* 32X PWM stuff (LOTS of output) */\r
045a4c52 878#define EL_32XP 0x00200000 /* 32X peripherals */\r
ae214f1c 879#define EL_CD 0x00400000 /* MCD */\r
017512f2 880\r
881#define EL_STATUS 0x40000000 /* status messages */\r
882#define EL_ANOMALY 0x80000000 /* some unexpected conditions (during emulation) */\r
b8cbd802 883\r
884#if EL_LOGMASK\r
885#define elprintf(w,f,...) \\r
a8fd6e37 886do { \\r
b8cbd802 887 if ((w) & EL_LOGMASK) \\r
7d0143a2 888 lprintf("%05i:%03i: " f "\n",Pico.m.frame_count,Pico.m.scanline,##__VA_ARGS__); \\r
a8fd6e37 889} while (0)\r
dca310c4 890#elif defined(_MSC_VER)\r
891#define elprintf\r
b8cbd802 892#else\r
893#define elprintf(w,f,...)\r
894#endif\r
895\r
f6c49d38 896// profiling\r
897#ifdef PPROF\r
898#include <platform/linux/pprof.h>\r
899#else\r
900#define pprof_init()\r
901#define pprof_finish()\r
902#define pprof_start(x)\r
903#define pprof_end(...)\r
904#define pprof_end_sub(...)\r
905#endif\r
906\r
19886062 907#ifdef EVT_LOG\r
908enum evt {\r
909 EVT_FRAME_START,\r
910 EVT_NEXT_LINE,\r
911 EVT_RUN_START,\r
912 EVT_RUN_END,\r
913 EVT_POLL_START,\r
914 EVT_POLL_END,\r
915 EVT_CNT\r
916};\r
917\r
918enum evt_cpu {\r
919 EVT_M68K,\r
920 EVT_S68K,\r
921 EVT_MSH2,\r
922 EVT_SSH2,\r
923 EVT_CPU_CNT\r
924};\r
925\r
926void pevt_log(unsigned int cycles, enum evt_cpu c, enum evt e);\r
927void pevt_dump(void);\r
928\r
929#define pevt_log_m68k(e) \\r
930 pevt_log(SekCyclesDoneT(), EVT_M68K, e)\r
931#define pevt_log_m68k_o(e) \\r
932 pevt_log(SekCyclesDoneT2(), EVT_M68K, e)\r
933#define pevt_log_sh2(sh2, e) \\r
934 pevt_log(sh2_cycles_done_m68k(sh2), EVT_MSH2 + (sh2)->is_slave, e)\r
935#define pevt_log_sh2_o(sh2, e) \\r
936 pevt_log((sh2)->m68krcycles_done, EVT_MSH2 + (sh2)->is_slave, e)\r
937#else\r
938#define pevt_log(c, e)\r
939#define pevt_log_m68k(e)\r
940#define pevt_log_m68k_o(e)\r
941#define pevt_log_sh2(sh2, e)\r
942#define pevt_log_sh2_o(sh2, e)\r
943#define pevt_dump()\r
944#endif\r
945\r
f6c49d38 946// misc\r
dca310c4 947#ifdef _MSC_VER\r
948#define cdprintf\r
949#else\r
950#define cdprintf(x...)\r
951#endif\r
952\r
553c3eaa 953#ifdef __i386__\r
954#define REGPARM(x) __attribute__((regparm(x)))\r
c8d1e9b6 955#else\r
553c3eaa 956#define REGPARM(x)\r
c8d1e9b6 957#endif\r
958\r
5e89f0f5 959#ifdef __GNUC__\r
960#define NOINLINE __attribute__((noinline))\r
961#else\r
962#define NOINLINE\r
963#endif\r
964\r
f8af9634 965#ifdef __cplusplus\r
966} // End of extern "C"\r
967#endif\r
968\r
eff55556 969#endif // PICO_INTERNAL_INCLUDED\r
970\r
fast MegaDrive/MegaCD/32X emulator