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drc: add seemingly missing double-alloc check
[pcsx_rearmed.git] / libpcsxcore / new_dynarec / new_dynarec.c
CommitLineData
57871462 1/* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
2 * Mupen64plus - new_dynarec.c *
20d507ba 3 * Copyright (C) 2009-2011 Ari64 *
57871462 4 * *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
9 * *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
14 * *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. *
19 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */
20
21#include <stdlib.h>
22#include <stdint.h> //include for uint64_t
23#include <assert.h>
d848b60a 24#include <errno.h>
4600ba03 25#include <sys/mman.h>
d148d265 26#ifdef __MACH__
27#include <libkern/OSCacheControl.h>
28#endif
1e212a25 29#ifdef _3DS
30#include <3ds_utils.h>
31#endif
57871462 32
d148d265 33#include "new_dynarec_config.h"
3968e69e 34#include "../psxhle.h"
35#include "../psxinterpreter.h"
81dbbf4c 36#include "../gte.h"
37#include "emu_if.h" // emulator interface
57871462 38
d1e4ebd9 39#define noinline __attribute__((noinline,noclone))
b14b6a8f 40#ifndef ARRAY_SIZE
41#define ARRAY_SIZE(x) (sizeof(x) / sizeof(x[0]))
42#endif
e3c6bdb5 43#ifndef min
44#define min(a, b) ((b) < (a) ? (b) : (a))
45#endif
32631e6a 46#ifndef max
47#define max(a, b) ((b) > (a) ? (b) : (a))
48#endif
b14b6a8f 49
4600ba03 50//#define DISASM
32631e6a 51//#define ASSEM_PRINT
d1150cd6 52//#define REG_ALLOC_PRINT
32631e6a 53
54#ifdef ASSEM_PRINT
55#define assem_debug printf
56#else
4600ba03 57#define assem_debug(...)
32631e6a 58#endif
59//#define inv_debug printf
4600ba03 60#define inv_debug(...)
57871462 61
62#ifdef __i386__
63#include "assem_x86.h"
64#endif
65#ifdef __x86_64__
66#include "assem_x64.h"
67#endif
68#ifdef __arm__
69#include "assem_arm.h"
70#endif
be516ebe 71#ifdef __aarch64__
72#include "assem_arm64.h"
73#endif
57871462 74
81dbbf4c 75#define RAM_SIZE 0x200000
57871462 76#define MAXBLOCK 4096
77#define MAX_OUTPUT_BLOCK_SIZE 262144
2573466a 78
66ea165f 79#ifdef VITA
80// apparently Vita has a 16MB limit, so either we cut tc in half,
81// or use this hack (it's a hack because tc size was designed to be power-of-2)
82#define TC_REDUCE_BYTES 4096
83#else
84#define TC_REDUCE_BYTES 0
85#endif
86
2a014d73 87struct ndrc_mem
88{
66ea165f 89 u_char translation_cache[(1 << TARGET_SIZE_2) - TC_REDUCE_BYTES];
2a014d73 90 struct
91 {
92 struct tramp_insns ops[2048 / sizeof(struct tramp_insns)];
93 const void *f[2048 / sizeof(void *)];
94 } tramp;
95};
96
97#ifdef BASE_ADDR_DYNAMIC
98static struct ndrc_mem *ndrc;
99#else
100static struct ndrc_mem ndrc_ __attribute__((aligned(4096)));
101static struct ndrc_mem *ndrc = &ndrc_;
102#endif
103
b14b6a8f 104// stubs
105enum stub_type {
106 CC_STUB = 1,
107 FP_STUB = 2,
108 LOADB_STUB = 3,
109 LOADH_STUB = 4,
110 LOADW_STUB = 5,
111 LOADD_STUB = 6,
112 LOADBU_STUB = 7,
113 LOADHU_STUB = 8,
114 STOREB_STUB = 9,
115 STOREH_STUB = 10,
116 STOREW_STUB = 11,
117 STORED_STUB = 12,
118 STORELR_STUB = 13,
119 INVCODE_STUB = 14,
120};
121
6cc8d23c 122// regmap_pre[i] - regs before [i] insn starts; dirty things here that
123// don't match .regmap will be written back
124// [i].regmap_entry - regs that must be set up if someone jumps here
125// [i].regmap - regs [i] insn will read/(over)write
57871462 126struct regstat
127{
6cc8d23c 128 signed char regmap_entry[HOST_REGS];
57871462 129 signed char regmap[HOST_REGS];
57871462 130 uint64_t wasdirty;
131 uint64_t dirty;
132 uint64_t u;
24058131 133 u_int wasconst; // before; for example 'lw r2, (r2)' wasconst is true
134 u_int isconst; // ... but isconst is false when r2 is known
8575a877 135 u_int loadedconst; // host regs that have constants loaded
136 u_int waswritten; // MIPS regs that were used as store base before
57871462 137};
138
de5a60c3 139// note: asm depends on this layout
57871462 140struct ll_entry
141{
142 u_int vaddr;
de5a60c3 143 u_int reg_sv_flags;
57871462 144 void *addr;
145 struct ll_entry *next;
146};
147
df4dc2b1 148struct ht_entry
149{
150 u_int vaddr[2];
151 void *tcaddr[2];
152};
153
b14b6a8f 154struct code_stub
155{
156 enum stub_type type;
157 void *addr;
158 void *retaddr;
159 u_int a;
160 uintptr_t b;
161 uintptr_t c;
162 u_int d;
163 u_int e;
164};
165
643aeae3 166struct link_entry
167{
168 void *addr;
169 u_int target;
170 u_int ext;
171};
172
cf95b4f0 173static struct decoded_insn
174{
175 u_char itype;
176 u_char opcode;
177 u_char opcode2;
178 u_char rs1;
179 u_char rs2;
180 u_char rt1;
181 u_char rt2;
182 u_char lt1;
183 u_char bt:1;
cf95b4f0 184 u_char ooo:1;
185 u_char is_ds:1;
fe807a8a 186 u_char is_jump:1;
187 u_char is_ujump:1;
37387d8b 188 u_char is_load:1;
189 u_char is_store:1;
cf95b4f0 190} dops[MAXBLOCK];
191
e2b5e7aa 192 // used by asm:
193 u_char *out;
df4dc2b1 194 struct ht_entry hash_table[65536] __attribute__((aligned(16)));
e2b5e7aa 195 struct ll_entry *jump_in[4096] __attribute__((aligned(16)));
196 struct ll_entry *jump_dirty[4096];
197
198 static struct ll_entry *jump_out[4096];
199 static u_int start;
200 static u_int *source;
201 static char insn[MAXBLOCK][10];
bedfea38 202 static uint64_t gte_rs[MAXBLOCK]; // gte: 32 data and 32 ctl regs
203 static uint64_t gte_rt[MAXBLOCK];
204 static uint64_t gte_unneeded[MAXBLOCK];
ffb0b9e0 205 static u_int smrv[32]; // speculated MIPS register values
206 static u_int smrv_strong; // mask or regs that are likely to have correct values
207 static u_int smrv_weak; // same, but somewhat less likely
208 static u_int smrv_strong_next; // same, but after current insn executes
209 static u_int smrv_weak_next;
e2b5e7aa 210 static int imm[MAXBLOCK];
211 static u_int ba[MAXBLOCK];
e2b5e7aa 212 static uint64_t unneeded_reg[MAXBLOCK];
e2b5e7aa 213 static uint64_t branch_unneeded_reg[MAXBLOCK];
6cc8d23c 214 // see 'struct regstat' for a description
2330734f 215 static signed char regmap_pre[MAXBLOCK][HOST_REGS];
40fca85b 216 // contains 'real' consts at [i] insn, but may differ from what's actually
217 // loaded in host reg as 'final' value is always loaded, see get_final_value()
218 static uint32_t current_constmap[HOST_REGS];
219 static uint32_t constmap[MAXBLOCK][HOST_REGS];
956f3129 220 static struct regstat regs[MAXBLOCK];
221 static struct regstat branch_regs[MAXBLOCK];
e2b5e7aa 222 static signed char minimum_free_regs[MAXBLOCK];
223 static u_int needed_reg[MAXBLOCK];
224 static u_int wont_dirty[MAXBLOCK];
225 static u_int will_dirty[MAXBLOCK];
226 static int ccadj[MAXBLOCK];
227 static int slen;
df4dc2b1 228 static void *instr_addr[MAXBLOCK];
643aeae3 229 static struct link_entry link_addr[MAXBLOCK];
e2b5e7aa 230 static int linkcount;
b14b6a8f 231 static struct code_stub stubs[MAXBLOCK*3];
e2b5e7aa 232 static int stubcount;
233 static u_int literals[1024][2];
234 static int literalcount;
235 static int is_delayslot;
e2b5e7aa 236 static char shadow[1048576] __attribute__((aligned(16)));
237 static void *copy;
238 static int expirep;
239 static u_int stop_after_jal;
7f94b097 240 static u_int f1_hack;
e2b5e7aa 241
242 int new_dynarec_hacks;
d62c125a 243 int new_dynarec_hacks_pergame;
32631e6a 244 int new_dynarec_hacks_old;
e2b5e7aa 245 int new_dynarec_did_compile;
687b4580 246
d62c125a 247 #define HACK_ENABLED(x) ((new_dynarec_hacks | new_dynarec_hacks_pergame) & (x))
248
687b4580 249 extern int cycle_count; // ... until end of the timeslice, counts -N -> 0
250 extern int last_count; // last absolute target, often = next_interupt
251 extern int pcaddr;
252 extern int pending_exception;
253 extern int branch_target;
37387d8b 254 extern uintptr_t ram_offset;
d1e4ebd9 255 extern uintptr_t mini_ht[32][2];
57871462 256 extern u_char restore_candidate[512];
57871462 257
258 /* registers that may be allocated */
259 /* 1-31 gpr */
7c3a5182 260#define LOREG 32 // lo
261#define HIREG 33 // hi
00fa9369 262//#define FSREG 34 // FPU status (FCSR)
57871462 263#define CSREG 35 // Coprocessor status
264#define CCREG 36 // Cycle count
265#define INVCP 37 // Pointer to invalid_code
1edfcc68 266//#define MMREG 38 // Pointer to memory_map
37387d8b 267#define ROREG 39 // ram offset (if rdram!=0x80000000)
619e5ded 268#define TEMPREG 40
269#define FTEMP 40 // FPU temporary register
270#define PTEMP 41 // Prefetch temporary register
1edfcc68 271//#define TLREG 42 // TLB mapping offset
619e5ded 272#define RHASH 43 // Return address hash
273#define RHTBL 44 // Return address hash table address
274#define RTEMP 45 // JR/JALR address register
275#define MAXREG 45
276#define AGEN1 46 // Address generation temporary register
1edfcc68 277//#define AGEN2 47 // Address generation temporary register
278//#define MGEN1 48 // Maptable address generation temporary register
279//#define MGEN2 49 // Maptable address generation temporary register
619e5ded 280#define BTREG 50 // Branch target temporary register
57871462 281
282 /* instruction types */
283#define NOP 0 // No operation
284#define LOAD 1 // Load
285#define STORE 2 // Store
286#define LOADLR 3 // Unaligned load
287#define STORELR 4 // Unaligned store
9f51b4b9 288#define MOV 5 // Move
57871462 289#define ALU 6 // Arithmetic/logic
290#define MULTDIV 7 // Multiply/divide
291#define SHIFT 8 // Shift by register
292#define SHIFTIMM 9// Shift by immediate
293#define IMM16 10 // 16-bit immediate
294#define RJUMP 11 // Unconditional jump to register
295#define UJUMP 12 // Unconditional jump
296#define CJUMP 13 // Conditional branch (BEQ/BNE/BGTZ/BLEZ)
297#define SJUMP 14 // Conditional branch (regimm format)
298#define COP0 15 // Coprocessor 0
299#define COP1 16 // Coprocessor 1
300#define C1LS 17 // Coprocessor 1 load/store
ad49de89 301//#define FJUMP 18 // Conditional branch (floating point)
00fa9369 302//#define FLOAT 19 // Floating point unit
303//#define FCONV 20 // Convert integer to float
304//#define FCOMP 21 // Floating point compare (sets FSREG)
d1150cd6 305#define SYSCALL 22// SYSCALL,BREAK
57871462 306#define OTHER 23 // Other
307#define SPAN 24 // Branch/delay slot spans 2 pages
308#define NI 25 // Not implemented
7139f3c8 309#define HLECALL 26// PCSX fake opcodes for HLE
b9b61529 310#define COP2 27 // Coprocessor 2 move
311#define C2LS 28 // Coprocessor 2 load/store
312#define C2OP 29 // Coprocessor 2 operation
1e973cb0 313#define INTCALL 30// Call interpreter to handle rare corner cases
57871462 314
57871462 315 /* branch codes */
316#define TAKEN 1
317#define NOTTAKEN 2
318#define NULLDS 3
319
7c3a5182 320#define DJT_1 (void *)1l // no function, just a label in assem_debug log
321#define DJT_2 (void *)2l
322
57871462 323// asm linkage
3968e69e 324int new_recompile_block(u_int addr);
57871462 325void *get_addr_ht(u_int vaddr);
326void invalidate_block(u_int block);
327void invalidate_addr(u_int addr);
328void remove_hash(int vaddr);
57871462 329void dyna_linker();
330void dyna_linker_ds();
331void verify_code();
57871462 332void verify_code_ds();
333void cc_interrupt();
334void fp_exception();
335void fp_exception_ds();
d1150cd6 336void jump_syscall (u_int u0, u_int u1, u_int pc);
337void jump_syscall_ds(u_int u0, u_int u1, u_int pc);
338void jump_break (u_int u0, u_int u1, u_int pc);
339void jump_break_ds(u_int u0, u_int u1, u_int pc);
3968e69e 340void jump_to_new_pc();
81dbbf4c 341void call_gteStall();
7139f3c8 342void new_dyna_leave();
57871462 343
57871462 344// Needed by assembler
2330734f 345static void wb_register(signed char r, const signed char regmap[], uint64_t dirty);
346static void wb_dirtys(const signed char i_regmap[], uint64_t i_dirty);
347static void wb_needed_dirtys(const signed char i_regmap[], uint64_t i_dirty, int addr);
348static void load_all_regs(const signed char i_regmap[]);
349static void load_needed_regs(const signed char i_regmap[], const signed char next_regmap[]);
e2b5e7aa 350static void load_regs_entry(int t);
2330734f 351static void load_all_consts(const signed char regmap[], u_int dirty, int i);
81dbbf4c 352static u_int get_host_reglist(const signed char *regmap);
e2b5e7aa 353
3968e69e 354static int verify_dirty(const u_int *ptr);
e2b5e7aa 355static int get_final_value(int hr, int i, int *value);
b14b6a8f 356static void add_stub(enum stub_type type, void *addr, void *retaddr,
357 u_int a, uintptr_t b, uintptr_t c, u_int d, u_int e);
358static void add_stub_r(enum stub_type type, void *addr, void *retaddr,
81dbbf4c 359 int i, int addr_reg, const struct regstat *i_regs, int ccadj, u_int reglist);
643aeae3 360static void add_to_linker(void *addr, u_int target, int ext);
37387d8b 361static void *emit_fastpath_cmp_jump(int i, const struct regstat *i_regs,
362 int addr, int *offset_reg, int *addr_reg_override);
687b4580 363static void *get_direct_memhandler(void *table, u_int addr,
364 enum stub_type type, uintptr_t *addr_host);
32631e6a 365static void cop2_do_stall_check(u_int op, int i, const struct regstat *i_regs, u_int reglist);
687b4580 366static void pass_args(int a0, int a1);
2a014d73 367static void emit_far_jump(const void *f);
368static void emit_far_call(const void *f);
57871462 369
9c67c98f 370#ifdef VITA
371#include <psp2/kernel/sysmem.h>
372static int sceBlock;
373// note: this interacts with RetroArch's Vita bootstrap code: bootstrap/vita/sbrk.c
374extern int getVMBlock();
375int _newlib_vm_size_user = sizeof(*ndrc);
376#endif
377
d148d265 378static void mprotect_w_x(void *start, void *end, int is_x)
379{
380#ifdef NO_WRITE_EXEC
1e212a25 381 #if defined(VITA)
382 // *Open* enables write on all memory that was
383 // allocated by sceKernelAllocMemBlockForVM()?
384 if (is_x)
385 sceKernelCloseVMDomain();
386 else
387 sceKernelOpenVMDomain();
388 #else
d148d265 389 u_long mstart = (u_long)start & ~4095ul;
390 u_long mend = (u_long)end;
391 if (mprotect((void *)mstart, mend - mstart,
392 PROT_READ | (is_x ? PROT_EXEC : PROT_WRITE)) != 0)
393 SysPrintf("mprotect(%c) failed: %s\n", is_x ? 'x' : 'w', strerror(errno));
1e212a25 394 #endif
d148d265 395#endif
396}
397
398static void start_tcache_write(void *start, void *end)
399{
400 mprotect_w_x(start, end, 0);
401}
402
403static void end_tcache_write(void *start, void *end)
404{
919981d0 405#if defined(__arm__) || defined(__aarch64__)
d148d265 406 size_t len = (char *)end - (char *)start;
407 #if defined(__BLACKBERRY_QNX__)
408 msync(start, len, MS_SYNC | MS_CACHE_ONLY | MS_INVALIDATE_ICACHE);
409 #elif defined(__MACH__)
410 sys_cache_control(kCacheFunctionPrepareForExecution, start, len);
411 #elif defined(VITA)
1e212a25 412 sceKernelSyncVMDomain(sceBlock, start, len);
413 #elif defined(_3DS)
414 ctr_flush_invalidate_cache();
919981d0 415 #elif defined(__aarch64__)
416 // as of 2021, __clear_cache() is still broken on arm64
417 // so here is a custom one :(
418 clear_cache_arm64(start, end);
d148d265 419 #else
420 __clear_cache(start, end);
421 #endif
422 (void)len;
423#endif
424
425 mprotect_w_x(start, end, 1);
426}
427
428static void *start_block(void)
429{
430 u_char *end = out + MAX_OUTPUT_BLOCK_SIZE;
2a014d73 431 if (end > ndrc->translation_cache + sizeof(ndrc->translation_cache))
432 end = ndrc->translation_cache + sizeof(ndrc->translation_cache);
d148d265 433 start_tcache_write(out, end);
434 return out;
435}
436
437static void end_block(void *start)
438{
439 end_tcache_write(start, out);
440}
441
919981d0 442// also takes care of w^x mappings when patching code
443static u_int needs_clear_cache[1<<(TARGET_SIZE_2-17)];
444
445static void mark_clear_cache(void *target)
446{
447 uintptr_t offset = (u_char *)target - ndrc->translation_cache;
448 u_int mask = 1u << ((offset >> 12) & 31);
449 if (!(needs_clear_cache[offset >> 17] & mask)) {
450 char *start = (char *)((uintptr_t)target & ~4095l);
451 start_tcache_write(start, start + 4095);
452 needs_clear_cache[offset >> 17] |= mask;
453 }
454}
455
456// Clearing the cache is rather slow on ARM Linux, so mark the areas
457// that need to be cleared, and then only clear these areas once.
458static void do_clear_cache(void)
459{
460 int i, j;
461 for (i = 0; i < (1<<(TARGET_SIZE_2-17)); i++)
462 {
463 u_int bitmap = needs_clear_cache[i];
464 if (!bitmap)
465 continue;
466 for (j = 0; j < 32; j++)
467 {
468 u_char *start, *end;
469 if (!(bitmap & (1<<j)))
470 continue;
471
472 start = ndrc->translation_cache + i*131072 + j*4096;
473 end = start + 4095;
474 for (j++; j < 32; j++) {
475 if (!(bitmap & (1<<j)))
476 break;
477 end += 4096;
478 }
479 end_tcache_write(start, end);
480 }
481 needs_clear_cache[i] = 0;
482 }
483}
484
57871462 485//#define DEBUG_CYCLE_COUNT 1
486
b6e87b2b 487#define NO_CYCLE_PENALTY_THR 12
488
26bd3dad 489int cycle_multiplier = CYCLE_MULT_DEFAULT; // 100 for 1.0
a3203cf4 490int cycle_multiplier_override;
32631e6a 491int cycle_multiplier_old;
24058131 492static int cycle_multiplier_active;
4e9dcd7f 493
494static int CLOCK_ADJUST(int x)
495{
24058131 496 int m = cycle_multiplier_active;
497 int s = (x >> 31) | 1;
a3203cf4 498 return (x * m + s * 50) / 100;
4e9dcd7f 499}
500
4919de1e 501static int ds_writes_rjump_rs(int i)
502{
cf95b4f0 503 return dops[i].rs1 != 0 && (dops[i].rs1 == dops[i+1].rt1 || dops[i].rs1 == dops[i+1].rt2);
4919de1e 504}
505
94d23bb9 506static u_int get_page(u_int vaddr)
57871462 507{
0ce47d46 508 u_int page=vaddr&~0xe0000000;
509 if (page < 0x1000000)
510 page &= ~0x0e00000; // RAM mirrors
511 page>>=12;
57871462 512 if(page>2048) page=2048+(page&2047);
94d23bb9 513 return page;
514}
515
d25604ca 516// no virtual mem in PCSX
517static u_int get_vpage(u_int vaddr)
518{
519 return get_page(vaddr);
520}
94d23bb9 521
df4dc2b1 522static struct ht_entry *hash_table_get(u_int vaddr)
523{
524 return &hash_table[((vaddr>>16)^vaddr)&0xFFFF];
525}
526
527static void hash_table_add(struct ht_entry *ht_bin, u_int vaddr, void *tcaddr)
528{
529 ht_bin->vaddr[1] = ht_bin->vaddr[0];
530 ht_bin->tcaddr[1] = ht_bin->tcaddr[0];
531 ht_bin->vaddr[0] = vaddr;
532 ht_bin->tcaddr[0] = tcaddr;
533}
534
535// some messy ari64's code, seems to rely on unsigned 32bit overflow
536static int doesnt_expire_soon(void *tcaddr)
537{
538 u_int diff = (u_int)((u_char *)tcaddr - out) << (32-TARGET_SIZE_2);
539 return diff > (u_int)(0x60000000 + (MAX_OUTPUT_BLOCK_SIZE << (32-TARGET_SIZE_2)));
540}
541
94d23bb9 542// Get address from virtual address
543// This is called from the recompiled JR/JALR instructions
d1e4ebd9 544void noinline *get_addr(u_int vaddr)
94d23bb9 545{
546 u_int page=get_page(vaddr);
547 u_int vpage=get_vpage(vaddr);
57871462 548 struct ll_entry *head;
549 //printf("TRACE: count=%d next=%d (get_addr %x,page %d)\n",Count,next_interupt,vaddr,page);
550 head=jump_in[page];
551 while(head!=NULL) {
de5a60c3 552 if(head->vaddr==vaddr) {
643aeae3 553 //printf("TRACE: count=%d next=%d (get_addr match %x: %p)\n",Count,next_interupt,vaddr,head->addr);
df4dc2b1 554 hash_table_add(hash_table_get(vaddr), vaddr, head->addr);
57871462 555 return head->addr;
556 }
557 head=head->next;
558 }
559 head=jump_dirty[vpage];
560 while(head!=NULL) {
de5a60c3 561 if(head->vaddr==vaddr) {
643aeae3 562 //printf("TRACE: count=%d next=%d (get_addr match dirty %x: %p)\n",Count,next_interupt,vaddr,head->addr);
57871462 563 // Don't restore blocks which are about to expire from the cache
df4dc2b1 564 if (doesnt_expire_soon(head->addr))
565 if (verify_dirty(head->addr)) {
57871462 566 //printf("restore candidate: %x (%d) d=%d\n",vaddr,page,invalid_code[vaddr>>12]);
567 invalid_code[vaddr>>12]=0;
9be4ba64 568 inv_code_start=inv_code_end=~0;
57871462 569 if(vpage<2048) {
57871462 570 restore_candidate[vpage>>3]|=1<<(vpage&7);
571 }
572 else restore_candidate[page>>3]|=1<<(page&7);
df4dc2b1 573 struct ht_entry *ht_bin = hash_table_get(vaddr);
574 if (ht_bin->vaddr[0] == vaddr)
575 ht_bin->tcaddr[0] = head->addr; // Replace existing entry
57871462 576 else
df4dc2b1 577 hash_table_add(ht_bin, vaddr, head->addr);
578
57871462 579 return head->addr;
580 }
581 }
582 head=head->next;
583 }
584 //printf("TRACE: count=%d next=%d (get_addr no-match %x)\n",Count,next_interupt,vaddr);
585 int r=new_recompile_block(vaddr);
586 if(r==0) return get_addr(vaddr);
587 // Execute in unmapped page, generate pagefault execption
588 Status|=2;
589 Cause=(vaddr<<31)|0x8;
590 EPC=(vaddr&1)?vaddr-5:vaddr;
591 BadVAddr=(vaddr&~1);
592 Context=(Context&0xFF80000F)|((BadVAddr>>9)&0x007FFFF0);
593 EntryHi=BadVAddr&0xFFFFE000;
594 return get_addr_ht(0x80000000);
595}
596// Look up address in hash table first
597void *get_addr_ht(u_int vaddr)
598{
599 //printf("TRACE: count=%d next=%d (get_addr_ht %x)\n",Count,next_interupt,vaddr);
df4dc2b1 600 const struct ht_entry *ht_bin = hash_table_get(vaddr);
601 if (ht_bin->vaddr[0] == vaddr) return ht_bin->tcaddr[0];
602 if (ht_bin->vaddr[1] == vaddr) return ht_bin->tcaddr[1];
57871462 603 return get_addr(vaddr);
604}
605
6cc8d23c 606static void clear_all_regs(signed char regmap[])
57871462 607{
6cc8d23c 608 memset(regmap, -1, sizeof(regmap[0]) * HOST_REGS);
57871462 609}
610
d1e4ebd9 611static signed char get_reg(const signed char regmap[],int r)
57871462 612{
613 int hr;
614 for (hr=0;hr<HOST_REGS;hr++) if(hr!=EXCLUDE_REG&&regmap[hr]==r) return hr;
615 return -1;
616}
617
618// Find a register that is available for two consecutive cycles
d1e4ebd9 619static signed char get_reg2(signed char regmap1[], const signed char regmap2[], int r)
57871462 620{
621 int hr;
622 for (hr=0;hr<HOST_REGS;hr++) if(hr!=EXCLUDE_REG&&regmap1[hr]==r&&regmap2[hr]==r) return hr;
623 return -1;
624}
625
626int count_free_regs(signed char regmap[])
627{
628 int count=0;
629 int hr;
630 for(hr=0;hr<HOST_REGS;hr++)
631 {
632 if(hr!=EXCLUDE_REG) {
633 if(regmap[hr]<0) count++;
634 }
635 }
636 return count;
637}
638
639void dirty_reg(struct regstat *cur,signed char reg)
640{
641 int hr;
642 if(!reg) return;
643 for (hr=0;hr<HOST_REGS;hr++) {
644 if((cur->regmap[hr]&63)==reg) {
645 cur->dirty|=1<<hr;
646 }
647 }
648}
649
40fca85b 650static void set_const(struct regstat *cur, signed char reg, uint32_t value)
57871462 651{
652 int hr;
653 if(!reg) return;
654 for (hr=0;hr<HOST_REGS;hr++) {
655 if(cur->regmap[hr]==reg) {
656 cur->isconst|=1<<hr;
956f3129 657 current_constmap[hr]=value;
57871462 658 }
57871462 659 }
660}
661
40fca85b 662static void clear_const(struct regstat *cur, signed char reg)
57871462 663{
664 int hr;
665 if(!reg) return;
666 for (hr=0;hr<HOST_REGS;hr++) {
667 if((cur->regmap[hr]&63)==reg) {
668 cur->isconst&=~(1<<hr);
669 }
670 }
671}
672
40fca85b 673static int is_const(struct regstat *cur, signed char reg)
57871462 674{
675 int hr;
79c75f1b 676 if(reg<0) return 0;
57871462 677 if(!reg) return 1;
678 for (hr=0;hr<HOST_REGS;hr++) {
679 if((cur->regmap[hr]&63)==reg) {
680 return (cur->isconst>>hr)&1;
681 }
682 }
683 return 0;
684}
40fca85b 685
686static uint32_t get_const(struct regstat *cur, signed char reg)
57871462 687{
688 int hr;
689 if(!reg) return 0;
690 for (hr=0;hr<HOST_REGS;hr++) {
691 if(cur->regmap[hr]==reg) {
956f3129 692 return current_constmap[hr];
57871462 693 }
694 }
c43b5311 695 SysPrintf("Unknown constant in r%d\n",reg);
7c3a5182 696 abort();
57871462 697}
698
699// Least soon needed registers
700// Look at the next ten instructions and see which registers
701// will be used. Try not to reallocate these.
702void lsn(u_char hsn[], int i, int *preferred_reg)
703{
704 int j;
705 int b=-1;
706 for(j=0;j<9;j++)
707 {
708 if(i+j>=slen) {
709 j=slen-i-1;
710 break;
711 }
fe807a8a 712 if (dops[i+j].is_ujump)
57871462 713 {
714 // Don't go past an unconditonal jump
715 j++;
716 break;
717 }
718 }
719 for(;j>=0;j--)
720 {
cf95b4f0 721 if(dops[i+j].rs1) hsn[dops[i+j].rs1]=j;
722 if(dops[i+j].rs2) hsn[dops[i+j].rs2]=j;
723 if(dops[i+j].rt1) hsn[dops[i+j].rt1]=j;
724 if(dops[i+j].rt2) hsn[dops[i+j].rt2]=j;
725 if(dops[i+j].itype==STORE || dops[i+j].itype==STORELR) {
57871462 726 // Stores can allocate zero
cf95b4f0 727 hsn[dops[i+j].rs1]=j;
728 hsn[dops[i+j].rs2]=j;
57871462 729 }
37387d8b 730 if (ram_offset && (dops[i+j].is_load || dops[i+j].is_store))
731 hsn[ROREG] = j;
57871462 732 // On some architectures stores need invc_ptr
733 #if defined(HOST_IMM8)
37387d8b 734 if (dops[i+j].is_store)
735 hsn[INVCP] = j;
57871462 736 #endif
cf95b4f0 737 if(i+j>=0&&(dops[i+j].itype==UJUMP||dops[i+j].itype==CJUMP||dops[i+j].itype==SJUMP))
57871462 738 {
739 hsn[CCREG]=j;
740 b=j;
741 }
742 }
743 if(b>=0)
744 {
745 if(ba[i+b]>=start && ba[i+b]<(start+slen*4))
746 {
747 // Follow first branch
748 int t=(ba[i+b]-start)>>2;
749 j=7-b;if(t+j>=slen) j=slen-t-1;
750 for(;j>=0;j--)
751 {
cf95b4f0 752 if(dops[t+j].rs1) if(hsn[dops[t+j].rs1]>j+b+2) hsn[dops[t+j].rs1]=j+b+2;
753 if(dops[t+j].rs2) if(hsn[dops[t+j].rs2]>j+b+2) hsn[dops[t+j].rs2]=j+b+2;
754 //if(dops[t+j].rt1) if(hsn[dops[t+j].rt1]>j+b+2) hsn[dops[t+j].rt1]=j+b+2;
755 //if(dops[t+j].rt2) if(hsn[dops[t+j].rt2]>j+b+2) hsn[dops[t+j].rt2]=j+b+2;
57871462 756 }
757 }
758 // TODO: preferred register based on backward branch
759 }
760 // Delay slot should preferably not overwrite branch conditions or cycle count
fe807a8a 761 if (i > 0 && dops[i-1].is_jump) {
cf95b4f0 762 if(dops[i-1].rs1) if(hsn[dops[i-1].rs1]>1) hsn[dops[i-1].rs1]=1;
763 if(dops[i-1].rs2) if(hsn[dops[i-1].rs2]>1) hsn[dops[i-1].rs2]=1;
57871462 764 hsn[CCREG]=1;
765 // ...or hash tables
766 hsn[RHASH]=1;
767 hsn[RHTBL]=1;
768 }
769 // Coprocessor load/store needs FTEMP, even if not declared
37387d8b 770 if(dops[i].itype==C2LS) {
57871462 771 hsn[FTEMP]=0;
772 }
773 // Load L/R also uses FTEMP as a temporary register
cf95b4f0 774 if(dops[i].itype==LOADLR) {
57871462 775 hsn[FTEMP]=0;
776 }
b7918751 777 // Also SWL/SWR/SDL/SDR
cf95b4f0 778 if(dops[i].opcode==0x2a||dops[i].opcode==0x2e||dops[i].opcode==0x2c||dops[i].opcode==0x2d) {
57871462 779 hsn[FTEMP]=0;
780 }
57871462 781 // Don't remove the miniht registers
cf95b4f0 782 if(dops[i].itype==UJUMP||dops[i].itype==RJUMP)
57871462 783 {
784 hsn[RHASH]=0;
785 hsn[RHTBL]=0;
786 }
787}
788
789// We only want to allocate registers if we're going to use them again soon
790int needed_again(int r, int i)
791{
792 int j;
793 int b=-1;
794 int rn=10;
9f51b4b9 795
fe807a8a 796 if (i > 0 && dops[i-1].is_ujump)
57871462 797 {
798 if(ba[i-1]<start || ba[i-1]>start+slen*4-4)
799 return 0; // Don't need any registers if exiting the block
800 }
801 for(j=0;j<9;j++)
802 {
803 if(i+j>=slen) {
804 j=slen-i-1;
805 break;
806 }
fe807a8a 807 if (dops[i+j].is_ujump)
57871462 808 {
809 // Don't go past an unconditonal jump
810 j++;
811 break;
812 }
cf95b4f0 813 if(dops[i+j].itype==SYSCALL||dops[i+j].itype==HLECALL||dops[i+j].itype==INTCALL||((source[i+j]&0xfc00003f)==0x0d))
57871462 814 {
815 break;
816 }
817 }
818 for(;j>=1;j--)
819 {
cf95b4f0 820 if(dops[i+j].rs1==r) rn=j;
821 if(dops[i+j].rs2==r) rn=j;
57871462 822 if((unneeded_reg[i+j]>>r)&1) rn=10;
cf95b4f0 823 if(i+j>=0&&(dops[i+j].itype==UJUMP||dops[i+j].itype==CJUMP||dops[i+j].itype==SJUMP))
57871462 824 {
825 b=j;
826 }
827 }
b7217e13 828 if(rn<10) return 1;
581335b0 829 (void)b;
57871462 830 return 0;
831}
832
833// Try to match register allocations at the end of a loop with those
834// at the beginning
835int loop_reg(int i, int r, int hr)
836{
837 int j,k;
838 for(j=0;j<9;j++)
839 {
840 if(i+j>=slen) {
841 j=slen-i-1;
842 break;
843 }
fe807a8a 844 if (dops[i+j].is_ujump)
57871462 845 {
846 // Don't go past an unconditonal jump
847 j++;
848 break;
849 }
850 }
851 k=0;
852 if(i>0){
cf95b4f0 853 if(dops[i-1].itype==UJUMP||dops[i-1].itype==CJUMP||dops[i-1].itype==SJUMP)
57871462 854 k--;
855 }
856 for(;k<j;k++)
857 {
00fa9369 858 assert(r < 64);
859 if((unneeded_reg[i+k]>>r)&1) return hr;
cf95b4f0 860 if(i+k>=0&&(dops[i+k].itype==UJUMP||dops[i+k].itype==CJUMP||dops[i+k].itype==SJUMP))
57871462 861 {
862 if(ba[i+k]>=start && ba[i+k]<(start+i*4))
863 {
864 int t=(ba[i+k]-start)>>2;
865 int reg=get_reg(regs[t].regmap_entry,r);
866 if(reg>=0) return reg;
867 //reg=get_reg(regs[t+1].regmap_entry,r);
868 //if(reg>=0) return reg;
869 }
870 }
871 }
872 return hr;
873}
874
875
876// Allocate every register, preserving source/target regs
877void alloc_all(struct regstat *cur,int i)
878{
879 int hr;
9f51b4b9 880
57871462 881 for(hr=0;hr<HOST_REGS;hr++) {
882 if(hr!=EXCLUDE_REG) {
cf95b4f0 883 if(((cur->regmap[hr]&63)!=dops[i].rs1)&&((cur->regmap[hr]&63)!=dops[i].rs2)&&
884 ((cur->regmap[hr]&63)!=dops[i].rt1)&&((cur->regmap[hr]&63)!=dops[i].rt2))
57871462 885 {
886 cur->regmap[hr]=-1;
887 cur->dirty&=~(1<<hr);
888 }
889 // Don't need zeros
890 if((cur->regmap[hr]&63)==0)
891 {
892 cur->regmap[hr]=-1;
893 cur->dirty&=~(1<<hr);
894 }
895 }
896 }
897}
898
d1e4ebd9 899#ifndef NDEBUG
900static int host_tempreg_in_use;
901
902static void host_tempreg_acquire(void)
903{
904 assert(!host_tempreg_in_use);
905 host_tempreg_in_use = 1;
906}
907
908static void host_tempreg_release(void)
909{
910 host_tempreg_in_use = 0;
911}
912#else
913static void host_tempreg_acquire(void) {}
914static void host_tempreg_release(void) {}
915#endif
916
32631e6a 917#ifdef ASSEM_PRINT
8062d65a 918extern void gen_interupt();
919extern void do_insn_cmp();
d1e4ebd9 920#define FUNCNAME(f) { f, " " #f }
8062d65a 921static const struct {
d1e4ebd9 922 void *addr;
8062d65a 923 const char *name;
924} function_names[] = {
925 FUNCNAME(cc_interrupt),
926 FUNCNAME(gen_interupt),
927 FUNCNAME(get_addr_ht),
928 FUNCNAME(get_addr),
929 FUNCNAME(jump_handler_read8),
930 FUNCNAME(jump_handler_read16),
931 FUNCNAME(jump_handler_read32),
932 FUNCNAME(jump_handler_write8),
933 FUNCNAME(jump_handler_write16),
934 FUNCNAME(jump_handler_write32),
935 FUNCNAME(invalidate_addr),
3968e69e 936 FUNCNAME(jump_to_new_pc),
d1150cd6 937 FUNCNAME(jump_break),
938 FUNCNAME(jump_break_ds),
939 FUNCNAME(jump_syscall),
940 FUNCNAME(jump_syscall_ds),
81dbbf4c 941 FUNCNAME(call_gteStall),
8062d65a 942 FUNCNAME(new_dyna_leave),
943 FUNCNAME(pcsx_mtc0),
944 FUNCNAME(pcsx_mtc0_ds),
32631e6a 945#ifdef DRC_DBG
8062d65a 946 FUNCNAME(do_insn_cmp),
32631e6a 947#endif
3968e69e 948#ifdef __arm__
949 FUNCNAME(verify_code),
950#endif
8062d65a 951};
952
d1e4ebd9 953static const char *func_name(const void *a)
8062d65a 954{
955 int i;
956 for (i = 0; i < sizeof(function_names)/sizeof(function_names[0]); i++)
957 if (function_names[i].addr == a)
958 return function_names[i].name;
959 return "";
960}
961#else
962#define func_name(x) ""
963#endif
964
57871462 965#ifdef __i386__
966#include "assem_x86.c"
967#endif
968#ifdef __x86_64__
969#include "assem_x64.c"
970#endif
971#ifdef __arm__
972#include "assem_arm.c"
973#endif
be516ebe 974#ifdef __aarch64__
975#include "assem_arm64.c"
976#endif
57871462 977
2a014d73 978static void *get_trampoline(const void *f)
979{
980 size_t i;
981
982 for (i = 0; i < ARRAY_SIZE(ndrc->tramp.f); i++) {
983 if (ndrc->tramp.f[i] == f || ndrc->tramp.f[i] == NULL)
984 break;
985 }
986 if (i == ARRAY_SIZE(ndrc->tramp.f)) {
987 SysPrintf("trampoline table is full, last func %p\n", f);
988 abort();
989 }
990 if (ndrc->tramp.f[i] == NULL) {
991 start_tcache_write(&ndrc->tramp.f[i], &ndrc->tramp.f[i + 1]);
992 ndrc->tramp.f[i] = f;
993 end_tcache_write(&ndrc->tramp.f[i], &ndrc->tramp.f[i + 1]);
994 }
995 return &ndrc->tramp.ops[i];
996}
997
998static void emit_far_jump(const void *f)
999{
1000 if (can_jump_or_call(f)) {
1001 emit_jmp(f);
1002 return;
1003 }
1004
1005 f = get_trampoline(f);
1006 emit_jmp(f);
1007}
1008
1009static void emit_far_call(const void *f)
1010{
1011 if (can_jump_or_call(f)) {
1012 emit_call(f);
1013 return;
1014 }
1015
1016 f = get_trampoline(f);
1017 emit_call(f);
1018}
1019
57871462 1020// Add virtual address mapping to linked list
1021void ll_add(struct ll_entry **head,int vaddr,void *addr)
1022{
1023 struct ll_entry *new_entry;
1024 new_entry=malloc(sizeof(struct ll_entry));
1025 assert(new_entry!=NULL);
1026 new_entry->vaddr=vaddr;
de5a60c3 1027 new_entry->reg_sv_flags=0;
57871462 1028 new_entry->addr=addr;
1029 new_entry->next=*head;
1030 *head=new_entry;
1031}
1032
de5a60c3 1033void ll_add_flags(struct ll_entry **head,int vaddr,u_int reg_sv_flags,void *addr)
57871462 1034{
7139f3c8 1035 ll_add(head,vaddr,addr);
de5a60c3 1036 (*head)->reg_sv_flags=reg_sv_flags;
57871462 1037}
1038
1039// Check if an address is already compiled
1040// but don't return addresses which are about to expire from the cache
1041void *check_addr(u_int vaddr)
1042{
df4dc2b1 1043 struct ht_entry *ht_bin = hash_table_get(vaddr);
1044 size_t i;
b14b6a8f 1045 for (i = 0; i < ARRAY_SIZE(ht_bin->vaddr); i++) {
df4dc2b1 1046 if (ht_bin->vaddr[i] == vaddr)
1047 if (doesnt_expire_soon((u_char *)ht_bin->tcaddr[i] - MAX_OUTPUT_BLOCK_SIZE))
1048 if (isclean(ht_bin->tcaddr[i]))
1049 return ht_bin->tcaddr[i];
57871462 1050 }
94d23bb9 1051 u_int page=get_page(vaddr);
57871462 1052 struct ll_entry *head;
1053 head=jump_in[page];
df4dc2b1 1054 while (head != NULL) {
1055 if (head->vaddr == vaddr) {
1056 if (doesnt_expire_soon(head->addr)) {
57871462 1057 // Update existing entry with current address
df4dc2b1 1058 if (ht_bin->vaddr[0] == vaddr) {
1059 ht_bin->tcaddr[0] = head->addr;
57871462 1060 return head->addr;
1061 }
df4dc2b1 1062 if (ht_bin->vaddr[1] == vaddr) {
1063 ht_bin->tcaddr[1] = head->addr;
57871462 1064 return head->addr;
1065 }
1066 // Insert into hash table with low priority.
1067 // Don't evict existing entries, as they are probably
1068 // addresses that are being accessed frequently.
df4dc2b1 1069 if (ht_bin->vaddr[0] == -1) {
1070 ht_bin->vaddr[0] = vaddr;
1071 ht_bin->tcaddr[0] = head->addr;
1072 }
1073 else if (ht_bin->vaddr[1] == -1) {
1074 ht_bin->vaddr[1] = vaddr;
1075 ht_bin->tcaddr[1] = head->addr;
57871462 1076 }
1077 return head->addr;
1078 }
1079 }
1080 head=head->next;
1081 }
1082 return 0;
1083}
1084
1085void remove_hash(int vaddr)
1086{
1087 //printf("remove hash: %x\n",vaddr);
df4dc2b1 1088 struct ht_entry *ht_bin = hash_table_get(vaddr);
1089 if (ht_bin->vaddr[1] == vaddr) {
1090 ht_bin->vaddr[1] = -1;
1091 ht_bin->tcaddr[1] = NULL;
57871462 1092 }
df4dc2b1 1093 if (ht_bin->vaddr[0] == vaddr) {
1094 ht_bin->vaddr[0] = ht_bin->vaddr[1];
1095 ht_bin->tcaddr[0] = ht_bin->tcaddr[1];
1096 ht_bin->vaddr[1] = -1;
1097 ht_bin->tcaddr[1] = NULL;
57871462 1098 }
1099}
1100
943f42f3 1101static void ll_remove_matching_addrs(struct ll_entry **head,
1102 uintptr_t base_offs_s, int shift)
57871462 1103{
1104 struct ll_entry *next;
1105 while(*head) {
943f42f3 1106 uintptr_t o1 = (u_char *)(*head)->addr - ndrc->translation_cache;
1107 uintptr_t o2 = o1 - MAX_OUTPUT_BLOCK_SIZE;
1108 if ((o1 >> shift) == base_offs_s || (o2 >> shift) == base_offs_s)
57871462 1109 {
643aeae3 1110 inv_debug("EXP: Remove pointer to %p (%x)\n",(*head)->addr,(*head)->vaddr);
57871462 1111 remove_hash((*head)->vaddr);
1112 next=(*head)->next;
1113 free(*head);
1114 *head=next;
1115 }
1116 else
1117 {
1118 head=&((*head)->next);
1119 }
1120 }
1121}
1122
1123// Remove all entries from linked list
1124void ll_clear(struct ll_entry **head)
1125{
1126 struct ll_entry *cur;
1127 struct ll_entry *next;
581335b0 1128 if((cur=*head)) {
57871462 1129 *head=0;
1130 while(cur) {
1131 next=cur->next;
1132 free(cur);
1133 cur=next;
1134 }
1135 }
1136}
1137
1138// Dereference the pointers and remove if it matches
943f42f3 1139static void ll_kill_pointers(struct ll_entry *head,
1140 uintptr_t base_offs_s, int shift)
57871462 1141{
1142 while(head) {
943f42f3 1143 u_char *ptr = get_pointer(head->addr);
1144 uintptr_t o1 = ptr - ndrc->translation_cache;
1145 uintptr_t o2 = o1 - MAX_OUTPUT_BLOCK_SIZE;
1146 inv_debug("EXP: Lookup pointer to %p at %p (%x)\n",ptr,head->addr,head->vaddr);
1147 if ((o1 >> shift) == base_offs_s || (o2 >> shift) == base_offs_s)
57871462 1148 {
643aeae3 1149 inv_debug("EXP: Kill pointer at %p (%x)\n",head->addr,head->vaddr);
d148d265 1150 void *host_addr=find_extjump_insn(head->addr);
919981d0 1151 mark_clear_cache(host_addr);
df4dc2b1 1152 set_jump_target(host_addr, head->addr);
57871462 1153 }
1154 head=head->next;
1155 }
1156}
1157
1158// This is called when we write to a compiled block (see do_invstub)
d1e4ebd9 1159static void invalidate_page(u_int page)
57871462 1160{
57871462 1161 struct ll_entry *head;
1162 struct ll_entry *next;
1163 head=jump_in[page];
1164 jump_in[page]=0;
1165 while(head!=NULL) {
1166 inv_debug("INVALIDATE: %x\n",head->vaddr);
1167 remove_hash(head->vaddr);
1168 next=head->next;
1169 free(head);
1170 head=next;
1171 }
1172 head=jump_out[page];
1173 jump_out[page]=0;
1174 while(head!=NULL) {
643aeae3 1175 inv_debug("INVALIDATE: kill pointer to %x (%p)\n",head->vaddr,head->addr);
d148d265 1176 void *host_addr=find_extjump_insn(head->addr);
919981d0 1177 mark_clear_cache(host_addr);
3d680478 1178 set_jump_target(host_addr, head->addr); // point back to dyna_linker
57871462 1179 next=head->next;
1180 free(head);
1181 head=next;
1182 }
57871462 1183}
9be4ba64 1184
1185static void invalidate_block_range(u_int block, u_int first, u_int last)
57871462 1186{
94d23bb9 1187 u_int page=get_page(block<<12);
57871462 1188 //printf("first=%d last=%d\n",first,last);
f76eeef9 1189 invalidate_page(page);
57871462 1190 assert(first+5>page); // NB: this assumes MAXBLOCK<=4096 (4 pages)
1191 assert(last<page+5);
1192 // Invalidate the adjacent pages if a block crosses a 4K boundary
1193 while(first<page) {
1194 invalidate_page(first);
1195 first++;
1196 }
1197 for(first=page+1;first<last;first++) {
1198 invalidate_page(first);
1199 }
919981d0 1200 do_clear_cache();
9f51b4b9 1201
57871462 1202 // Don't trap writes
1203 invalid_code[block]=1;
f76eeef9 1204
57871462 1205 #ifdef USE_MINI_HT
1206 memset(mini_ht,-1,sizeof(mini_ht));
1207 #endif
1208}
9be4ba64 1209
1210void invalidate_block(u_int block)
1211{
1212 u_int page=get_page(block<<12);
1213 u_int vpage=get_vpage(block<<12);
1214 inv_debug("INVALIDATE: %x (%d)\n",block<<12,page);
1215 //inv_debug("invalid_code[block]=%d\n",invalid_code[block]);
1216 u_int first,last;
1217 first=last=page;
1218 struct ll_entry *head;
1219 head=jump_dirty[vpage];
1220 //printf("page=%d vpage=%d\n",page,vpage);
1221 while(head!=NULL) {
9be4ba64 1222 if(vpage>2047||(head->vaddr>>12)==block) { // Ignore vaddr hash collision
01d26796 1223 u_char *start, *end;
1224 get_bounds(head->addr, &start, &end);
1225 //printf("start: %p end: %p\n", start, end);
1226 if (page < 2048 && start >= rdram && end < rdram+RAM_SIZE) {
1227 if (((start-rdram)>>12) <= page && ((end-1-rdram)>>12) >= page) {
1228 if ((((start-rdram)>>12)&2047) < first) first = ((start-rdram)>>12)&2047;
1229 if ((((end-1-rdram)>>12)&2047) > last) last = ((end-1-rdram)>>12)&2047;
9be4ba64 1230 }
1231 }
9be4ba64 1232 }
1233 head=head->next;
1234 }
1235 invalidate_block_range(block,first,last);
1236}
1237
57871462 1238void invalidate_addr(u_int addr)
1239{
9be4ba64 1240 //static int rhits;
1241 // this check is done by the caller
1242 //if (inv_code_start<=addr&&addr<=inv_code_end) { rhits++; return; }
d25604ca 1243 u_int page=get_vpage(addr);
9be4ba64 1244 if(page<2048) { // RAM
1245 struct ll_entry *head;
1246 u_int addr_min=~0, addr_max=0;
4a35de07 1247 u_int mask=RAM_SIZE-1;
1248 u_int addr_main=0x80000000|(addr&mask);
9be4ba64 1249 int pg1;
4a35de07 1250 inv_code_start=addr_main&~0xfff;
1251 inv_code_end=addr_main|0xfff;
9be4ba64 1252 pg1=page;
1253 if (pg1>0) {
1254 // must check previous page too because of spans..
1255 pg1--;
1256 inv_code_start-=0x1000;
1257 }
1258 for(;pg1<=page;pg1++) {
1259 for(head=jump_dirty[pg1];head!=NULL;head=head->next) {
01d26796 1260 u_char *start_h, *end_h;
1261 u_int start, end;
1262 get_bounds(head->addr, &start_h, &end_h);
1263 start = (uintptr_t)start_h - ram_offset;
1264 end = (uintptr_t)end_h - ram_offset;
4a35de07 1265 if(start<=addr_main&&addr_main<end) {
9be4ba64 1266 if(start<addr_min) addr_min=start;
1267 if(end>addr_max) addr_max=end;
1268 }
4a35de07 1269 else if(addr_main<start) {
9be4ba64 1270 if(start<inv_code_end)
1271 inv_code_end=start-1;
1272 }
1273 else {
1274 if(end>inv_code_start)
1275 inv_code_start=end;
1276 }
1277 }
1278 }
1279 if (addr_min!=~0) {
1280 inv_debug("INV ADDR: %08x hit %08x-%08x\n", addr, addr_min, addr_max);
1281 inv_code_start=inv_code_end=~0;
1282 invalidate_block_range(addr>>12,(addr_min&mask)>>12,(addr_max&mask)>>12);
1283 return;
1284 }
1285 else {
4a35de07 1286 inv_code_start=(addr&~mask)|(inv_code_start&mask);
1287 inv_code_end=(addr&~mask)|(inv_code_end&mask);
d25604ca 1288 inv_debug("INV ADDR: %08x miss, inv %08x-%08x, sk %d\n", addr, inv_code_start, inv_code_end, 0);
9be4ba64 1289 return;
d25604ca 1290 }
9be4ba64 1291 }
57871462 1292 invalidate_block(addr>>12);
1293}
9be4ba64 1294
dd3a91a1 1295// This is called when loading a save state.
1296// Anything could have changed, so invalidate everything.
919981d0 1297void invalidate_all_pages(void)
57871462 1298{
581335b0 1299 u_int page;
57871462 1300 for(page=0;page<4096;page++)
1301 invalidate_page(page);
1302 for(page=0;page<1048576;page++)
1303 if(!invalid_code[page]) {
1304 restore_candidate[(page&2047)>>3]|=1<<(page&7);
1305 restore_candidate[((page&2047)>>3)+256]|=1<<(page&7);
1306 }
57871462 1307 #ifdef USE_MINI_HT
1308 memset(mini_ht,-1,sizeof(mini_ht));
1309 #endif
919981d0 1310 do_clear_cache();
57871462 1311}
1312
d1e4ebd9 1313static void do_invstub(int n)
1314{
1315 literal_pool(20);
1316 u_int reglist=stubs[n].a;
1317 set_jump_target(stubs[n].addr, out);
1318 save_regs(reglist);
1319 if(stubs[n].b!=0) emit_mov(stubs[n].b,0);
2a014d73 1320 emit_far_call(invalidate_addr);
d1e4ebd9 1321 restore_regs(reglist);
1322 emit_jmp(stubs[n].retaddr); // return address
1323}
1324
57871462 1325// Add an entry to jump_out after making a link
d1e4ebd9 1326// src should point to code by emit_extjump2()
3d680478 1327void add_jump_out(u_int vaddr,void *src)
57871462 1328{
94d23bb9 1329 u_int page=get_page(vaddr);
3d680478 1330 inv_debug("add_jump_out: %p -> %x (%d)\n",src,vaddr,page);
d1e4ebd9 1331 check_extjump2(src);
57871462 1332 ll_add(jump_out+page,vaddr,src);
3d680478 1333 //inv_debug("add_jump_out: to %p\n",get_pointer(src));
57871462 1334}
1335
1336// If a code block was found to be unmodified (bit was set in
1337// restore_candidate) and it remains unmodified (bit is clear
1338// in invalid_code) then move the entries for that 4K page from
1339// the dirty list to the clean list.
1340void clean_blocks(u_int page)
1341{
1342 struct ll_entry *head;
1343 inv_debug("INV: clean_blocks page=%d\n",page);
1344 head=jump_dirty[page];
1345 while(head!=NULL) {
1346 if(!invalid_code[head->vaddr>>12]) {
1347 // Don't restore blocks which are about to expire from the cache
df4dc2b1 1348 if (doesnt_expire_soon(head->addr)) {
581335b0 1349 if(verify_dirty(head->addr)) {
01d26796 1350 u_char *start, *end;
643aeae3 1351 //printf("Possibly Restore %x (%p)\n",head->vaddr, head->addr);
57871462 1352 u_int i;
1353 u_int inv=0;
01d26796 1354 get_bounds(head->addr, &start, &end);
1355 if (start - rdram < RAM_SIZE) {
1356 for (i = (start-rdram+0x80000000)>>12; i <= (end-1-rdram+0x80000000)>>12; i++) {
57871462 1357 inv|=invalid_code[i];
1358 }
1359 }
4cb76aa4 1360 else if((signed int)head->vaddr>=(signed int)0x80000000+RAM_SIZE) {
57871462 1361 inv=1;
1362 }
1363 if(!inv) {
df4dc2b1 1364 void *clean_addr = get_clean_addr(head->addr);
1365 if (doesnt_expire_soon(clean_addr)) {
57871462 1366 u_int ppage=page;
643aeae3 1367 inv_debug("INV: Restored %x (%p/%p)\n",head->vaddr, head->addr, clean_addr);
57871462 1368 //printf("page=%x, addr=%x\n",page,head->vaddr);
1369 //assert(head->vaddr>>12==(page|0x80000));
de5a60c3 1370 ll_add_flags(jump_in+ppage,head->vaddr,head->reg_sv_flags,clean_addr);
df4dc2b1 1371 struct ht_entry *ht_bin = hash_table_get(head->vaddr);
1372 if (ht_bin->vaddr[0] == head->vaddr)
1373 ht_bin->tcaddr[0] = clean_addr; // Replace existing entry
1374 if (ht_bin->vaddr[1] == head->vaddr)
1375 ht_bin->tcaddr[1] = clean_addr; // Replace existing entry
57871462 1376 }
1377 }
1378 }
1379 }
1380 }
1381 head=head->next;
1382 }
1383}
1384
8062d65a 1385/* Register allocation */
1386
1387// Note: registers are allocated clean (unmodified state)
1388// if you intend to modify the register, you must call dirty_reg().
1389static void alloc_reg(struct regstat *cur,int i,signed char reg)
1390{
1391 int r,hr;
b7ec323c 1392 int preferred_reg = PREFERRED_REG_FIRST
1393 + reg % (PREFERRED_REG_LAST - PREFERRED_REG_FIRST + 1);
1394 if (reg == CCREG) preferred_reg = HOST_CCREG;
1395 if (reg == PTEMP || reg == FTEMP) preferred_reg = 12;
1396 assert(PREFERRED_REG_FIRST != EXCLUDE_REG && EXCLUDE_REG != HOST_REGS);
8062d65a 1397
1398 // Don't allocate unused registers
1399 if((cur->u>>reg)&1) return;
1400
1401 // see if it's already allocated
1402 for(hr=0;hr<HOST_REGS;hr++)
1403 {
1404 if(cur->regmap[hr]==reg) return;
1405 }
1406
1407 // Keep the same mapping if the register was already allocated in a loop
1408 preferred_reg = loop_reg(i,reg,preferred_reg);
1409
1410 // Try to allocate the preferred register
1411 if(cur->regmap[preferred_reg]==-1) {
1412 cur->regmap[preferred_reg]=reg;
1413 cur->dirty&=~(1<<preferred_reg);
1414 cur->isconst&=~(1<<preferred_reg);
1415 return;
1416 }
1417 r=cur->regmap[preferred_reg];
1418 assert(r < 64);
1419 if((cur->u>>r)&1) {
1420 cur->regmap[preferred_reg]=reg;
1421 cur->dirty&=~(1<<preferred_reg);
1422 cur->isconst&=~(1<<preferred_reg);
1423 return;
1424 }
1425
1426 // Clear any unneeded registers
1427 // We try to keep the mapping consistent, if possible, because it
1428 // makes branches easier (especially loops). So we try to allocate
1429 // first (see above) before removing old mappings. If this is not
1430 // possible then go ahead and clear out the registers that are no
1431 // longer needed.
1432 for(hr=0;hr<HOST_REGS;hr++)
1433 {
1434 r=cur->regmap[hr];
1435 if(r>=0) {
1436 assert(r < 64);
1437 if((cur->u>>r)&1) {cur->regmap[hr]=-1;break;}
1438 }
1439 }
b7ec323c 1440
8062d65a 1441 // Try to allocate any available register, but prefer
1442 // registers that have not been used recently.
b7ec323c 1443 if (i > 0) {
1444 for (hr = PREFERRED_REG_FIRST; ; ) {
1445 if (cur->regmap[hr] < 0) {
1446 int oldreg = regs[i-1].regmap[hr];
1447 if (oldreg < 0 || (oldreg != dops[i-1].rs1 && oldreg != dops[i-1].rs2
1448 && oldreg != dops[i-1].rt1 && oldreg != dops[i-1].rt2))
1449 {
8062d65a 1450 cur->regmap[hr]=reg;
1451 cur->dirty&=~(1<<hr);
1452 cur->isconst&=~(1<<hr);
1453 return;
1454 }
1455 }
b7ec323c 1456 hr++;
1457 if (hr == EXCLUDE_REG)
1458 hr++;
1459 if (hr == HOST_REGS)
1460 hr = 0;
1461 if (hr == PREFERRED_REG_FIRST)
1462 break;
8062d65a 1463 }
1464 }
b7ec323c 1465
8062d65a 1466 // Try to allocate any available register
b7ec323c 1467 for (hr = PREFERRED_REG_FIRST; ; ) {
1468 if (cur->regmap[hr] < 0) {
8062d65a 1469 cur->regmap[hr]=reg;
1470 cur->dirty&=~(1<<hr);
1471 cur->isconst&=~(1<<hr);
1472 return;
1473 }
b7ec323c 1474 hr++;
1475 if (hr == EXCLUDE_REG)
1476 hr++;
1477 if (hr == HOST_REGS)
1478 hr = 0;
1479 if (hr == PREFERRED_REG_FIRST)
1480 break;
8062d65a 1481 }
1482
1483 // Ok, now we have to evict someone
1484 // Pick a register we hopefully won't need soon
1485 u_char hsn[MAXREG+1];
1486 memset(hsn,10,sizeof(hsn));
1487 int j;
1488 lsn(hsn,i,&preferred_reg);
1489 //printf("eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",cur->regmap[0],cur->regmap[1],cur->regmap[2],cur->regmap[3],cur->regmap[5],cur->regmap[6],cur->regmap[7]);
1490 //printf("hsn(%x): %d %d %d %d %d %d %d\n",start+i*4,hsn[cur->regmap[0]&63],hsn[cur->regmap[1]&63],hsn[cur->regmap[2]&63],hsn[cur->regmap[3]&63],hsn[cur->regmap[5]&63],hsn[cur->regmap[6]&63],hsn[cur->regmap[7]&63]);
1491 if(i>0) {
1492 // Don't evict the cycle count at entry points, otherwise the entry
1493 // stub will have to write it.
cf95b4f0 1494 if(dops[i].bt&&hsn[CCREG]>2) hsn[CCREG]=2;
fe807a8a 1495 if (i>1 && hsn[CCREG] > 2 && dops[i-2].is_jump) hsn[CCREG]=2;
8062d65a 1496 for(j=10;j>=3;j--)
1497 {
1498 // Alloc preferred register if available
1499 if(hsn[r=cur->regmap[preferred_reg]&63]==j) {
1500 for(hr=0;hr<HOST_REGS;hr++) {
1501 // Evict both parts of a 64-bit register
1502 if((cur->regmap[hr]&63)==r) {
1503 cur->regmap[hr]=-1;
1504 cur->dirty&=~(1<<hr);
1505 cur->isconst&=~(1<<hr);
1506 }
1507 }
1508 cur->regmap[preferred_reg]=reg;
1509 return;
1510 }
1511 for(r=1;r<=MAXREG;r++)
1512 {
cf95b4f0 1513 if(hsn[r]==j&&r!=dops[i-1].rs1&&r!=dops[i-1].rs2&&r!=dops[i-1].rt1&&r!=dops[i-1].rt2) {
8062d65a 1514 for(hr=0;hr<HOST_REGS;hr++) {
1515 if(hr!=HOST_CCREG||j<hsn[CCREG]) {
1516 if(cur->regmap[hr]==r) {
1517 cur->regmap[hr]=reg;
1518 cur->dirty&=~(1<<hr);
1519 cur->isconst&=~(1<<hr);
1520 return;
1521 }
1522 }
1523 }
1524 }
1525 }
1526 }
1527 }
1528 for(j=10;j>=0;j--)
1529 {
1530 for(r=1;r<=MAXREG;r++)
1531 {
1532 if(hsn[r]==j) {
8062d65a 1533 for(hr=0;hr<HOST_REGS;hr++) {
1534 if(cur->regmap[hr]==r) {
1535 cur->regmap[hr]=reg;
1536 cur->dirty&=~(1<<hr);
1537 cur->isconst&=~(1<<hr);
1538 return;
1539 }
1540 }
1541 }
1542 }
1543 }
7c3a5182 1544 SysPrintf("This shouldn't happen (alloc_reg)");abort();
8062d65a 1545}
1546
1547// Allocate a temporary register. This is done without regard to
1548// dirty status or whether the register we request is on the unneeded list
1549// Note: This will only allocate one register, even if called multiple times
1550static void alloc_reg_temp(struct regstat *cur,int i,signed char reg)
1551{
1552 int r,hr;
1553 int preferred_reg = -1;
1554
1555 // see if it's already allocated
1556 for(hr=0;hr<HOST_REGS;hr++)
1557 {
1558 if(hr!=EXCLUDE_REG&&cur->regmap[hr]==reg) return;
1559 }
1560
1561 // Try to allocate any available register
1562 for(hr=HOST_REGS-1;hr>=0;hr--) {
1563 if(hr!=EXCLUDE_REG&&cur->regmap[hr]==-1) {
1564 cur->regmap[hr]=reg;
1565 cur->dirty&=~(1<<hr);
1566 cur->isconst&=~(1<<hr);
1567 return;
1568 }
1569 }
1570
1571 // Find an unneeded register
1572 for(hr=HOST_REGS-1;hr>=0;hr--)
1573 {
1574 r=cur->regmap[hr];
1575 if(r>=0) {
1576 assert(r < 64);
1577 if((cur->u>>r)&1) {
1578 if(i==0||((unneeded_reg[i-1]>>r)&1)) {
1579 cur->regmap[hr]=reg;
1580 cur->dirty&=~(1<<hr);
1581 cur->isconst&=~(1<<hr);
1582 return;
1583 }
1584 }
1585 }
1586 }
1587
1588 // Ok, now we have to evict someone
1589 // Pick a register we hopefully won't need soon
1590 // TODO: we might want to follow unconditional jumps here
1591 // TODO: get rid of dupe code and make this into a function
1592 u_char hsn[MAXREG+1];
1593 memset(hsn,10,sizeof(hsn));
1594 int j;
1595 lsn(hsn,i,&preferred_reg);
1596 //printf("hsn: %d %d %d %d %d %d %d\n",hsn[cur->regmap[0]&63],hsn[cur->regmap[1]&63],hsn[cur->regmap[2]&63],hsn[cur->regmap[3]&63],hsn[cur->regmap[5]&63],hsn[cur->regmap[6]&63],hsn[cur->regmap[7]&63]);
1597 if(i>0) {
1598 // Don't evict the cycle count at entry points, otherwise the entry
1599 // stub will have to write it.
cf95b4f0 1600 if(dops[i].bt&&hsn[CCREG]>2) hsn[CCREG]=2;
fe807a8a 1601 if (i>1 && hsn[CCREG] > 2 && dops[i-2].is_jump) hsn[CCREG]=2;
8062d65a 1602 for(j=10;j>=3;j--)
1603 {
1604 for(r=1;r<=MAXREG;r++)
1605 {
cf95b4f0 1606 if(hsn[r]==j&&r!=dops[i-1].rs1&&r!=dops[i-1].rs2&&r!=dops[i-1].rt1&&r!=dops[i-1].rt2) {
8062d65a 1607 for(hr=0;hr<HOST_REGS;hr++) {
1608 if(hr!=HOST_CCREG||hsn[CCREG]>2) {
1609 if(cur->regmap[hr]==r) {
1610 cur->regmap[hr]=reg;
1611 cur->dirty&=~(1<<hr);
1612 cur->isconst&=~(1<<hr);
1613 return;
1614 }
1615 }
1616 }
1617 }
1618 }
1619 }
1620 }
1621 for(j=10;j>=0;j--)
1622 {
1623 for(r=1;r<=MAXREG;r++)
1624 {
1625 if(hsn[r]==j) {
8062d65a 1626 for(hr=0;hr<HOST_REGS;hr++) {
1627 if(cur->regmap[hr]==r) {
1628 cur->regmap[hr]=reg;
1629 cur->dirty&=~(1<<hr);
1630 cur->isconst&=~(1<<hr);
1631 return;
1632 }
1633 }
1634 }
1635 }
1636 }
7c3a5182 1637 SysPrintf("This shouldn't happen");abort();
8062d65a 1638}
1639
ad49de89 1640static void mov_alloc(struct regstat *current,int i)
57871462 1641{
cf95b4f0 1642 if (dops[i].rs1 == HIREG || dops[i].rs1 == LOREG) {
9a3ccfeb 1643 alloc_cc(current,i); // for stalls
1644 dirty_reg(current,CCREG);
32631e6a 1645 }
1646
57871462 1647 // Note: Don't need to actually alloc the source registers
cf95b4f0 1648 //alloc_reg(current,i,dops[i].rs1);
1649 alloc_reg(current,i,dops[i].rt1);
ad49de89 1650
cf95b4f0 1651 clear_const(current,dops[i].rs1);
1652 clear_const(current,dops[i].rt1);
1653 dirty_reg(current,dops[i].rt1);
57871462 1654}
1655
ad49de89 1656static void shiftimm_alloc(struct regstat *current,int i)
57871462 1657{
cf95b4f0 1658 if(dops[i].opcode2<=0x3) // SLL/SRL/SRA
57871462 1659 {
cf95b4f0 1660 if(dops[i].rt1) {
1661 if(dops[i].rs1&&needed_again(dops[i].rs1,i)) alloc_reg(current,i,dops[i].rs1);
1662 else dops[i].lt1=dops[i].rs1;
1663 alloc_reg(current,i,dops[i].rt1);
1664 dirty_reg(current,dops[i].rt1);
1665 if(is_const(current,dops[i].rs1)) {
1666 int v=get_const(current,dops[i].rs1);
1667 if(dops[i].opcode2==0x00) set_const(current,dops[i].rt1,v<<imm[i]);
1668 if(dops[i].opcode2==0x02) set_const(current,dops[i].rt1,(u_int)v>>imm[i]);
1669 if(dops[i].opcode2==0x03) set_const(current,dops[i].rt1,v>>imm[i]);
dc49e339 1670 }
cf95b4f0 1671 else clear_const(current,dops[i].rt1);
57871462 1672 }
1673 }
dc49e339 1674 else
1675 {
cf95b4f0 1676 clear_const(current,dops[i].rs1);
1677 clear_const(current,dops[i].rt1);
dc49e339 1678 }
1679
cf95b4f0 1680 if(dops[i].opcode2>=0x38&&dops[i].opcode2<=0x3b) // DSLL/DSRL/DSRA
57871462 1681 {
9c45ca93 1682 assert(0);
57871462 1683 }
cf95b4f0 1684 if(dops[i].opcode2==0x3c) // DSLL32
57871462 1685 {
9c45ca93 1686 assert(0);
57871462 1687 }
cf95b4f0 1688 if(dops[i].opcode2==0x3e) // DSRL32
57871462 1689 {
9c45ca93 1690 assert(0);
57871462 1691 }
cf95b4f0 1692 if(dops[i].opcode2==0x3f) // DSRA32
57871462 1693 {
9c45ca93 1694 assert(0);
57871462 1695 }
1696}
1697
ad49de89 1698static void shift_alloc(struct regstat *current,int i)
57871462 1699{
cf95b4f0 1700 if(dops[i].rt1) {
1701 if(dops[i].opcode2<=0x07) // SLLV/SRLV/SRAV
57871462 1702 {
cf95b4f0 1703 if(dops[i].rs1) alloc_reg(current,i,dops[i].rs1);
1704 if(dops[i].rs2) alloc_reg(current,i,dops[i].rs2);
1705 alloc_reg(current,i,dops[i].rt1);
1706 if(dops[i].rt1==dops[i].rs2) {
e1190b87 1707 alloc_reg_temp(current,i,-1);
1708 minimum_free_regs[i]=1;
1709 }
57871462 1710 } else { // DSLLV/DSRLV/DSRAV
00fa9369 1711 assert(0);
57871462 1712 }
cf95b4f0 1713 clear_const(current,dops[i].rs1);
1714 clear_const(current,dops[i].rs2);
1715 clear_const(current,dops[i].rt1);
1716 dirty_reg(current,dops[i].rt1);
57871462 1717 }
1718}
1719
ad49de89 1720static void alu_alloc(struct regstat *current,int i)
57871462 1721{
cf95b4f0 1722 if(dops[i].opcode2>=0x20&&dops[i].opcode2<=0x23) { // ADD/ADDU/SUB/SUBU
1723 if(dops[i].rt1) {
1724 if(dops[i].rs1&&dops[i].rs2) {
1725 alloc_reg(current,i,dops[i].rs1);
1726 alloc_reg(current,i,dops[i].rs2);
57871462 1727 }
1728 else {
cf95b4f0 1729 if(dops[i].rs1&&needed_again(dops[i].rs1,i)) alloc_reg(current,i,dops[i].rs1);
1730 if(dops[i].rs2&&needed_again(dops[i].rs2,i)) alloc_reg(current,i,dops[i].rs2);
57871462 1731 }
cf95b4f0 1732 alloc_reg(current,i,dops[i].rt1);
57871462 1733 }
57871462 1734 }
cf95b4f0 1735 if(dops[i].opcode2==0x2a||dops[i].opcode2==0x2b) { // SLT/SLTU
1736 if(dops[i].rt1) {
1737 alloc_reg(current,i,dops[i].rs1);
1738 alloc_reg(current,i,dops[i].rs2);
1739 alloc_reg(current,i,dops[i].rt1);
57871462 1740 }
57871462 1741 }
cf95b4f0 1742 if(dops[i].opcode2>=0x24&&dops[i].opcode2<=0x27) { // AND/OR/XOR/NOR
1743 if(dops[i].rt1) {
1744 if(dops[i].rs1&&dops[i].rs2) {
1745 alloc_reg(current,i,dops[i].rs1);
1746 alloc_reg(current,i,dops[i].rs2);
57871462 1747 }
1748 else
1749 {
cf95b4f0 1750 if(dops[i].rs1&&needed_again(dops[i].rs1,i)) alloc_reg(current,i,dops[i].rs1);
1751 if(dops[i].rs2&&needed_again(dops[i].rs2,i)) alloc_reg(current,i,dops[i].rs2);
57871462 1752 }
cf95b4f0 1753 alloc_reg(current,i,dops[i].rt1);
57871462 1754 }
1755 }
cf95b4f0 1756 if(dops[i].opcode2>=0x2c&&dops[i].opcode2<=0x2f) { // DADD/DADDU/DSUB/DSUBU
00fa9369 1757 assert(0);
57871462 1758 }
cf95b4f0 1759 clear_const(current,dops[i].rs1);
1760 clear_const(current,dops[i].rs2);
1761 clear_const(current,dops[i].rt1);
1762 dirty_reg(current,dops[i].rt1);
57871462 1763}
1764
ad49de89 1765static void imm16_alloc(struct regstat *current,int i)
57871462 1766{
cf95b4f0 1767 if(dops[i].rs1&&needed_again(dops[i].rs1,i)) alloc_reg(current,i,dops[i].rs1);
1768 else dops[i].lt1=dops[i].rs1;
1769 if(dops[i].rt1) alloc_reg(current,i,dops[i].rt1);
1770 if(dops[i].opcode==0x18||dops[i].opcode==0x19) { // DADDI/DADDIU
00fa9369 1771 assert(0);
57871462 1772 }
cf95b4f0 1773 else if(dops[i].opcode==0x0a||dops[i].opcode==0x0b) { // SLTI/SLTIU
1774 clear_const(current,dops[i].rs1);
1775 clear_const(current,dops[i].rt1);
57871462 1776 }
cf95b4f0 1777 else if(dops[i].opcode>=0x0c&&dops[i].opcode<=0x0e) { // ANDI/ORI/XORI
1778 if(is_const(current,dops[i].rs1)) {
1779 int v=get_const(current,dops[i].rs1);
1780 if(dops[i].opcode==0x0c) set_const(current,dops[i].rt1,v&imm[i]);
1781 if(dops[i].opcode==0x0d) set_const(current,dops[i].rt1,v|imm[i]);
1782 if(dops[i].opcode==0x0e) set_const(current,dops[i].rt1,v^imm[i]);
57871462 1783 }
cf95b4f0 1784 else clear_const(current,dops[i].rt1);
57871462 1785 }
cf95b4f0 1786 else if(dops[i].opcode==0x08||dops[i].opcode==0x09) { // ADDI/ADDIU
1787 if(is_const(current,dops[i].rs1)) {
1788 int v=get_const(current,dops[i].rs1);
1789 set_const(current,dops[i].rt1,v+imm[i]);
57871462 1790 }
cf95b4f0 1791 else clear_const(current,dops[i].rt1);
57871462 1792 }
1793 else {
cf95b4f0 1794 set_const(current,dops[i].rt1,imm[i]<<16); // LUI
57871462 1795 }
cf95b4f0 1796 dirty_reg(current,dops[i].rt1);
57871462 1797}
1798
ad49de89 1799static void load_alloc(struct regstat *current,int i)
57871462 1800{
cf95b4f0 1801 clear_const(current,dops[i].rt1);
1802 //if(dops[i].rs1!=dops[i].rt1&&needed_again(dops[i].rs1,i)) clear_const(current,dops[i].rs1); // Does this help or hurt?
1803 if(!dops[i].rs1) current->u&=~1LL; // Allow allocating r0 if it's the source register
37387d8b 1804 if (needed_again(dops[i].rs1, i))
1805 alloc_reg(current, i, dops[i].rs1);
1806 if (ram_offset)
1807 alloc_reg(current, i, ROREG);
cf95b4f0 1808 if(dops[i].rt1&&!((current->u>>dops[i].rt1)&1)) {
1809 alloc_reg(current,i,dops[i].rt1);
1810 assert(get_reg(current->regmap,dops[i].rt1)>=0);
1811 if(dops[i].opcode==0x27||dops[i].opcode==0x37) // LWU/LD
57871462 1812 {
ad49de89 1813 assert(0);
57871462 1814 }
cf95b4f0 1815 else if(dops[i].opcode==0x1A||dops[i].opcode==0x1B) // LDL/LDR
57871462 1816 {
ad49de89 1817 assert(0);
57871462 1818 }
cf95b4f0 1819 dirty_reg(current,dops[i].rt1);
57871462 1820 // LWL/LWR need a temporary register for the old value
cf95b4f0 1821 if(dops[i].opcode==0x22||dops[i].opcode==0x26)
57871462 1822 {
1823 alloc_reg(current,i,FTEMP);
1824 alloc_reg_temp(current,i,-1);
e1190b87 1825 minimum_free_regs[i]=1;
57871462 1826 }
1827 }
1828 else
1829 {
373d1d07 1830 // Load to r0 or unneeded register (dummy load)
57871462 1831 // but we still need a register to calculate the address
cf95b4f0 1832 if(dops[i].opcode==0x22||dops[i].opcode==0x26)
535d208a 1833 {
1834 alloc_reg(current,i,FTEMP); // LWL/LWR need another temporary
1835 }
57871462 1836 alloc_reg_temp(current,i,-1);
e1190b87 1837 minimum_free_regs[i]=1;
cf95b4f0 1838 if(dops[i].opcode==0x1A||dops[i].opcode==0x1B) // LDL/LDR
535d208a 1839 {
ad49de89 1840 assert(0);
535d208a 1841 }
57871462 1842 }
1843}
1844
1845void store_alloc(struct regstat *current,int i)
1846{
cf95b4f0 1847 clear_const(current,dops[i].rs2);
1848 if(!(dops[i].rs2)) current->u&=~1LL; // Allow allocating r0 if necessary
1849 if(needed_again(dops[i].rs1,i)) alloc_reg(current,i,dops[i].rs1);
1850 alloc_reg(current,i,dops[i].rs2);
1851 if(dops[i].opcode==0x2c||dops[i].opcode==0x2d||dops[i].opcode==0x3f) { // 64-bit SDL/SDR/SD
ad49de89 1852 assert(0);
57871462 1853 }
37387d8b 1854 if (ram_offset)
1855 alloc_reg(current, i, ROREG);
57871462 1856 #if defined(HOST_IMM8)
1857 // On CPUs without 32-bit immediates we need a pointer to invalid_code
37387d8b 1858 alloc_reg(current, i, INVCP);
57871462 1859 #endif
cf95b4f0 1860 if(dops[i].opcode==0x2a||dops[i].opcode==0x2e||dops[i].opcode==0x2c||dops[i].opcode==0x2d) { // SWL/SWL/SDL/SDR
57871462 1861 alloc_reg(current,i,FTEMP);
1862 }
1863 // We need a temporary register for address generation
1864 alloc_reg_temp(current,i,-1);
e1190b87 1865 minimum_free_regs[i]=1;
57871462 1866}
1867
1868void c1ls_alloc(struct regstat *current,int i)
1869{
cf95b4f0 1870 clear_const(current,dops[i].rt1);
57871462 1871 alloc_reg(current,i,CSREG); // Status
57871462 1872}
1873
b9b61529 1874void c2ls_alloc(struct regstat *current,int i)
1875{
cf95b4f0 1876 clear_const(current,dops[i].rt1);
1877 if(needed_again(dops[i].rs1,i)) alloc_reg(current,i,dops[i].rs1);
b9b61529 1878 alloc_reg(current,i,FTEMP);
37387d8b 1879 if (ram_offset)
1880 alloc_reg(current, i, ROREG);
b9b61529 1881 #if defined(HOST_IMM8)
1882 // On CPUs without 32-bit immediates we need a pointer to invalid_code
37387d8b 1883 if (dops[i].opcode == 0x3a) // SWC2
b9b61529 1884 alloc_reg(current,i,INVCP);
1885 #endif
1886 // We need a temporary register for address generation
1887 alloc_reg_temp(current,i,-1);
e1190b87 1888 minimum_free_regs[i]=1;
b9b61529 1889}
1890
57871462 1891#ifndef multdiv_alloc
1892void multdiv_alloc(struct regstat *current,int i)
1893{
1894 // case 0x18: MULT
1895 // case 0x19: MULTU
1896 // case 0x1A: DIV
1897 // case 0x1B: DIVU
1898 // case 0x1C: DMULT
1899 // case 0x1D: DMULTU
1900 // case 0x1E: DDIV
1901 // case 0x1F: DDIVU
cf95b4f0 1902 clear_const(current,dops[i].rs1);
1903 clear_const(current,dops[i].rs2);
32631e6a 1904 alloc_cc(current,i); // for stalls
cf95b4f0 1905 if(dops[i].rs1&&dops[i].rs2)
57871462 1906 {
cf95b4f0 1907 if((dops[i].opcode2&4)==0) // 32-bit
57871462 1908 {
1909 current->u&=~(1LL<<HIREG);
1910 current->u&=~(1LL<<LOREG);
1911 alloc_reg(current,i,HIREG);
1912 alloc_reg(current,i,LOREG);
cf95b4f0 1913 alloc_reg(current,i,dops[i].rs1);
1914 alloc_reg(current,i,dops[i].rs2);
57871462 1915 dirty_reg(current,HIREG);
1916 dirty_reg(current,LOREG);
1917 }
1918 else // 64-bit
1919 {
00fa9369 1920 assert(0);
57871462 1921 }
1922 }
1923 else
1924 {
1925 // Multiply by zero is zero.
1926 // MIPS does not have a divide by zero exception.
1927 // The result is undefined, we return zero.
1928 alloc_reg(current,i,HIREG);
1929 alloc_reg(current,i,LOREG);
57871462 1930 dirty_reg(current,HIREG);
1931 dirty_reg(current,LOREG);
1932 }
1933}
1934#endif
1935
1936void cop0_alloc(struct regstat *current,int i)
1937{
cf95b4f0 1938 if(dops[i].opcode2==0) // MFC0
57871462 1939 {
cf95b4f0 1940 if(dops[i].rt1) {
1941 clear_const(current,dops[i].rt1);
57871462 1942 alloc_all(current,i);
cf95b4f0 1943 alloc_reg(current,i,dops[i].rt1);
1944 dirty_reg(current,dops[i].rt1);
57871462 1945 }
1946 }
cf95b4f0 1947 else if(dops[i].opcode2==4) // MTC0
57871462 1948 {
cf95b4f0 1949 if(dops[i].rs1){
1950 clear_const(current,dops[i].rs1);
1951 alloc_reg(current,i,dops[i].rs1);
57871462 1952 alloc_all(current,i);
1953 }
1954 else {
1955 alloc_all(current,i); // FIXME: Keep r0
1956 current->u&=~1LL;
1957 alloc_reg(current,i,0);
1958 }
1959 }
1960 else
1961 {
1962 // TLBR/TLBWI/TLBWR/TLBP/ERET
cf95b4f0 1963 assert(dops[i].opcode2==0x10);
57871462 1964 alloc_all(current,i);
1965 }
e1190b87 1966 minimum_free_regs[i]=HOST_REGS;
57871462 1967}
1968
81dbbf4c 1969static void cop2_alloc(struct regstat *current,int i)
57871462 1970{
cf95b4f0 1971 if (dops[i].opcode2 < 3) // MFC2/CFC2
57871462 1972 {
81dbbf4c 1973 alloc_cc(current,i); // for stalls
1974 dirty_reg(current,CCREG);
cf95b4f0 1975 if(dops[i].rt1){
1976 clear_const(current,dops[i].rt1);
1977 alloc_reg(current,i,dops[i].rt1);
1978 dirty_reg(current,dops[i].rt1);
57871462 1979 }
57871462 1980 }
cf95b4f0 1981 else if (dops[i].opcode2 > 3) // MTC2/CTC2
57871462 1982 {
cf95b4f0 1983 if(dops[i].rs1){
1984 clear_const(current,dops[i].rs1);
1985 alloc_reg(current,i,dops[i].rs1);
57871462 1986 }
1987 else {
1988 current->u&=~1LL;
1989 alloc_reg(current,i,0);
57871462 1990 }
1991 }
81dbbf4c 1992 alloc_reg_temp(current,i,-1);
e1190b87 1993 minimum_free_regs[i]=1;
57871462 1994}
00fa9369 1995
b9b61529 1996void c2op_alloc(struct regstat *current,int i)
1997{
81dbbf4c 1998 alloc_cc(current,i); // for stalls
1999 dirty_reg(current,CCREG);
b9b61529 2000 alloc_reg_temp(current,i,-1);
2001}
57871462 2002
2003void syscall_alloc(struct regstat *current,int i)
2004{
2005 alloc_cc(current,i);
2006 dirty_reg(current,CCREG);
2007 alloc_all(current,i);
e1190b87 2008 minimum_free_regs[i]=HOST_REGS;
57871462 2009 current->isconst=0;
2010}
2011
2012void delayslot_alloc(struct regstat *current,int i)
2013{
cf95b4f0 2014 switch(dops[i].itype) {
57871462 2015 case UJUMP:
2016 case CJUMP:
2017 case SJUMP:
2018 case RJUMP:
57871462 2019 case SYSCALL:
7139f3c8 2020 case HLECALL:
57871462 2021 case SPAN:
7c3a5182 2022 assem_debug("jump in the delay slot. this shouldn't happen.\n");//abort();
c43b5311 2023 SysPrintf("Disabled speculative precompilation\n");
57871462 2024 stop_after_jal=1;
2025 break;
2026 case IMM16:
2027 imm16_alloc(current,i);
2028 break;
2029 case LOAD:
2030 case LOADLR:
2031 load_alloc(current,i);
2032 break;
2033 case STORE:
2034 case STORELR:
2035 store_alloc(current,i);
2036 break;
2037 case ALU:
2038 alu_alloc(current,i);
2039 break;
2040 case SHIFT:
2041 shift_alloc(current,i);
2042 break;
2043 case MULTDIV:
2044 multdiv_alloc(current,i);
2045 break;
2046 case SHIFTIMM:
2047 shiftimm_alloc(current,i);
2048 break;
2049 case MOV:
2050 mov_alloc(current,i);
2051 break;
2052 case COP0:
2053 cop0_alloc(current,i);
2054 break;
2055 case COP1:
81dbbf4c 2056 break;
b9b61529 2057 case COP2:
81dbbf4c 2058 cop2_alloc(current,i);
57871462 2059 break;
2060 case C1LS:
2061 c1ls_alloc(current,i);
2062 break;
b9b61529 2063 case C2LS:
2064 c2ls_alloc(current,i);
2065 break;
b9b61529 2066 case C2OP:
2067 c2op_alloc(current,i);
2068 break;
57871462 2069 }
2070}
2071
2072// Special case where a branch and delay slot span two pages in virtual memory
2073static void pagespan_alloc(struct regstat *current,int i)
2074{
2075 current->isconst=0;
2076 current->wasconst=0;
2077 regs[i].wasconst=0;
e1190b87 2078 minimum_free_regs[i]=HOST_REGS;
57871462 2079 alloc_all(current,i);
2080 alloc_cc(current,i);
2081 dirty_reg(current,CCREG);
cf95b4f0 2082 if(dops[i].opcode==3) // JAL
57871462 2083 {
2084 alloc_reg(current,i,31);
2085 dirty_reg(current,31);
2086 }
cf95b4f0 2087 if(dops[i].opcode==0&&(dops[i].opcode2&0x3E)==8) // JR/JALR
57871462 2088 {
cf95b4f0 2089 alloc_reg(current,i,dops[i].rs1);
2090 if (dops[i].rt1!=0) {
2091 alloc_reg(current,i,dops[i].rt1);
2092 dirty_reg(current,dops[i].rt1);
57871462 2093 }
2094 }
cf95b4f0 2095 if((dops[i].opcode&0x2E)==4) // BEQ/BNE/BEQL/BNEL
57871462 2096 {
cf95b4f0 2097 if(dops[i].rs1) alloc_reg(current,i,dops[i].rs1);
2098 if(dops[i].rs2) alloc_reg(current,i,dops[i].rs2);
57871462 2099 }
2100 else
cf95b4f0 2101 if((dops[i].opcode&0x2E)==6) // BLEZ/BGTZ/BLEZL/BGTZL
57871462 2102 {
cf95b4f0 2103 if(dops[i].rs1) alloc_reg(current,i,dops[i].rs1);
57871462 2104 }
57871462 2105 //else ...
2106}
2107
b14b6a8f 2108static void add_stub(enum stub_type type, void *addr, void *retaddr,
2109 u_int a, uintptr_t b, uintptr_t c, u_int d, u_int e)
2110{
d1e4ebd9 2111 assert(stubcount < ARRAY_SIZE(stubs));
b14b6a8f 2112 stubs[stubcount].type = type;
2113 stubs[stubcount].addr = addr;
2114 stubs[stubcount].retaddr = retaddr;
2115 stubs[stubcount].a = a;
2116 stubs[stubcount].b = b;
2117 stubs[stubcount].c = c;
2118 stubs[stubcount].d = d;
2119 stubs[stubcount].e = e;
57871462 2120 stubcount++;
2121}
2122
b14b6a8f 2123static void add_stub_r(enum stub_type type, void *addr, void *retaddr,
81dbbf4c 2124 int i, int addr_reg, const struct regstat *i_regs, int ccadj, u_int reglist)
b14b6a8f 2125{
2126 add_stub(type, addr, retaddr, i, addr_reg, (uintptr_t)i_regs, ccadj, reglist);
2127}
2128
57871462 2129// Write out a single register
2330734f 2130static void wb_register(signed char r, const signed char regmap[], uint64_t dirty)
57871462 2131{
2132 int hr;
2133 for(hr=0;hr<HOST_REGS;hr++) {
2134 if(hr!=EXCLUDE_REG) {
2135 if((regmap[hr]&63)==r) {
2136 if((dirty>>hr)&1) {
ad49de89 2137 assert(regmap[hr]<64);
2138 emit_storereg(r,hr);
57871462 2139 }
2140 }
2141 }
2142 }
2143}
2144
8062d65a 2145static void wb_valid(signed char pre[],signed char entry[],u_int dirty_pre,u_int dirty,uint64_t u)
2146{
2147 //if(dirty_pre==dirty) return;
2148 int hr,reg;
2149 for(hr=0;hr<HOST_REGS;hr++) {
2150 if(hr!=EXCLUDE_REG) {
2151 reg=pre[hr];
2152 if(((~u)>>(reg&63))&1) {
2153 if(reg>0) {
2154 if(((dirty_pre&~dirty)>>hr)&1) {
2155 if(reg>0&&reg<34) {
2156 emit_storereg(reg,hr);
2157 }
2158 else if(reg>=64) {
2159 assert(0);
2160 }
2161 }
2162 }
2163 }
2164 }
2165 }
2166}
2167
687b4580 2168// trashes r2
2169static void pass_args(int a0, int a1)
2170{
2171 if(a0==1&&a1==0) {
2172 // must swap
2173 emit_mov(a0,2); emit_mov(a1,1); emit_mov(2,0);
2174 }
2175 else if(a0!=0&&a1==0) {
2176 emit_mov(a1,1);
2177 if (a0>=0) emit_mov(a0,0);
2178 }
2179 else {
2180 if(a0>=0&&a0!=0) emit_mov(a0,0);
2181 if(a1>=0&&a1!=1) emit_mov(a1,1);
2182 }
2183}
2184
2330734f 2185static void alu_assemble(int i, const struct regstat *i_regs)
57871462 2186{
cf95b4f0 2187 if(dops[i].opcode2>=0x20&&dops[i].opcode2<=0x23) { // ADD/ADDU/SUB/SUBU
2188 if(dops[i].rt1) {
57871462 2189 signed char s1,s2,t;
cf95b4f0 2190 t=get_reg(i_regs->regmap,dops[i].rt1);
57871462 2191 if(t>=0) {
cf95b4f0 2192 s1=get_reg(i_regs->regmap,dops[i].rs1);
2193 s2=get_reg(i_regs->regmap,dops[i].rs2);
2194 if(dops[i].rs1&&dops[i].rs2) {
57871462 2195 assert(s1>=0);
2196 assert(s2>=0);
cf95b4f0 2197 if(dops[i].opcode2&2) emit_sub(s1,s2,t);
57871462 2198 else emit_add(s1,s2,t);
2199 }
cf95b4f0 2200 else if(dops[i].rs1) {
57871462 2201 if(s1>=0) emit_mov(s1,t);
cf95b4f0 2202 else emit_loadreg(dops[i].rs1,t);
57871462 2203 }
cf95b4f0 2204 else if(dops[i].rs2) {
57871462 2205 if(s2>=0) {
cf95b4f0 2206 if(dops[i].opcode2&2) emit_neg(s2,t);
57871462 2207 else emit_mov(s2,t);
2208 }
2209 else {
cf95b4f0 2210 emit_loadreg(dops[i].rs2,t);
2211 if(dops[i].opcode2&2) emit_neg(t,t);
57871462 2212 }
2213 }
2214 else emit_zeroreg(t);
2215 }
2216 }
2217 }
cf95b4f0 2218 if(dops[i].opcode2>=0x2c&&dops[i].opcode2<=0x2f) { // DADD/DADDU/DSUB/DSUBU
00fa9369 2219 assert(0);
57871462 2220 }
cf95b4f0 2221 if(dops[i].opcode2==0x2a||dops[i].opcode2==0x2b) { // SLT/SLTU
2222 if(dops[i].rt1) {
ad49de89 2223 signed char s1l,s2l,t;
57871462 2224 {
cf95b4f0 2225 t=get_reg(i_regs->regmap,dops[i].rt1);
57871462 2226 //assert(t>=0);
2227 if(t>=0) {
cf95b4f0 2228 s1l=get_reg(i_regs->regmap,dops[i].rs1);
2229 s2l=get_reg(i_regs->regmap,dops[i].rs2);
2230 if(dops[i].rs2==0) // rx<r0
57871462 2231 {
cf95b4f0 2232 if(dops[i].opcode2==0x2a&&dops[i].rs1!=0) { // SLT
06e425d7 2233 assert(s1l>=0);
57871462 2234 emit_shrimm(s1l,31,t);
06e425d7 2235 }
2236 else // SLTU (unsigned can not be less than zero, 0<0)
57871462 2237 emit_zeroreg(t);
2238 }
cf95b4f0 2239 else if(dops[i].rs1==0) // r0<rx
57871462 2240 {
2241 assert(s2l>=0);
cf95b4f0 2242 if(dops[i].opcode2==0x2a) // SLT
57871462 2243 emit_set_gz32(s2l,t);
2244 else // SLTU (set if not zero)
2245 emit_set_nz32(s2l,t);
2246 }
2247 else{
2248 assert(s1l>=0);assert(s2l>=0);
cf95b4f0 2249 if(dops[i].opcode2==0x2a) // SLT
57871462 2250 emit_set_if_less32(s1l,s2l,t);
2251 else // SLTU
2252 emit_set_if_carry32(s1l,s2l,t);
2253 }
2254 }
2255 }
2256 }
2257 }
cf95b4f0 2258 if(dops[i].opcode2>=0x24&&dops[i].opcode2<=0x27) { // AND/OR/XOR/NOR
2259 if(dops[i].rt1) {
ad49de89 2260 signed char s1l,s2l,tl;
cf95b4f0 2261 tl=get_reg(i_regs->regmap,dops[i].rt1);
57871462 2262 {
57871462 2263 if(tl>=0) {
cf95b4f0 2264 s1l=get_reg(i_regs->regmap,dops[i].rs1);
2265 s2l=get_reg(i_regs->regmap,dops[i].rs2);
2266 if(dops[i].rs1&&dops[i].rs2) {
57871462 2267 assert(s1l>=0);
2268 assert(s2l>=0);
cf95b4f0 2269 if(dops[i].opcode2==0x24) { // AND
57871462 2270 emit_and(s1l,s2l,tl);
2271 } else
cf95b4f0 2272 if(dops[i].opcode2==0x25) { // OR
57871462 2273 emit_or(s1l,s2l,tl);
2274 } else
cf95b4f0 2275 if(dops[i].opcode2==0x26) { // XOR
57871462 2276 emit_xor(s1l,s2l,tl);
2277 } else
cf95b4f0 2278 if(dops[i].opcode2==0x27) { // NOR
57871462 2279 emit_or(s1l,s2l,tl);
2280 emit_not(tl,tl);
2281 }
2282 }
2283 else
2284 {
cf95b4f0 2285 if(dops[i].opcode2==0x24) { // AND
57871462 2286 emit_zeroreg(tl);
2287 } else
cf95b4f0 2288 if(dops[i].opcode2==0x25||dops[i].opcode2==0x26) { // OR/XOR
2289 if(dops[i].rs1){
57871462 2290 if(s1l>=0) emit_mov(s1l,tl);
cf95b4f0 2291 else emit_loadreg(dops[i].rs1,tl); // CHECK: regmap_entry?
57871462 2292 }
2293 else
cf95b4f0 2294 if(dops[i].rs2){
57871462 2295 if(s2l>=0) emit_mov(s2l,tl);
cf95b4f0 2296 else emit_loadreg(dops[i].rs2,tl); // CHECK: regmap_entry?
57871462 2297 }
2298 else emit_zeroreg(tl);
2299 } else
cf95b4f0 2300 if(dops[i].opcode2==0x27) { // NOR
2301 if(dops[i].rs1){
57871462 2302 if(s1l>=0) emit_not(s1l,tl);
2303 else {
cf95b4f0 2304 emit_loadreg(dops[i].rs1,tl);
57871462 2305 emit_not(tl,tl);
2306 }
2307 }
2308 else
cf95b4f0 2309 if(dops[i].rs2){
57871462 2310 if(s2l>=0) emit_not(s2l,tl);
2311 else {
cf95b4f0 2312 emit_loadreg(dops[i].rs2,tl);
57871462 2313 emit_not(tl,tl);
2314 }
2315 }
2316 else emit_movimm(-1,tl);
2317 }
2318 }
2319 }
2320 }
2321 }
2322 }
2323}
2324
2330734f 2325static void imm16_assemble(int i, const struct regstat *i_regs)
57871462 2326{
cf95b4f0 2327 if (dops[i].opcode==0x0f) { // LUI
2328 if(dops[i].rt1) {
57871462 2329 signed char t;
cf95b4f0 2330 t=get_reg(i_regs->regmap,dops[i].rt1);
57871462 2331 //assert(t>=0);
2332 if(t>=0) {
2333 if(!((i_regs->isconst>>t)&1))
2334 emit_movimm(imm[i]<<16,t);
2335 }
2336 }
2337 }
cf95b4f0 2338 if(dops[i].opcode==0x08||dops[i].opcode==0x09) { // ADDI/ADDIU
2339 if(dops[i].rt1) {
57871462 2340 signed char s,t;
cf95b4f0 2341 t=get_reg(i_regs->regmap,dops[i].rt1);
2342 s=get_reg(i_regs->regmap,dops[i].rs1);
2343 if(dops[i].rs1) {
57871462 2344 //assert(t>=0);
2345 //assert(s>=0);
2346 if(t>=0) {
2347 if(!((i_regs->isconst>>t)&1)) {
2348 if(s<0) {
cf95b4f0 2349 if(i_regs->regmap_entry[t]!=dops[i].rs1) emit_loadreg(dops[i].rs1,t);
57871462 2350 emit_addimm(t,imm[i],t);
2351 }else{
2352 if(!((i_regs->wasconst>>s)&1))
2353 emit_addimm(s,imm[i],t);
2354 else
2355 emit_movimm(constmap[i][s]+imm[i],t);
2356 }
2357 }
2358 }
2359 } else {
2360 if(t>=0) {
2361 if(!((i_regs->isconst>>t)&1))
2362 emit_movimm(imm[i],t);
2363 }
2364 }
2365 }
2366 }
cf95b4f0 2367 if(dops[i].opcode==0x18||dops[i].opcode==0x19) { // DADDI/DADDIU
2368 if(dops[i].rt1) {
7c3a5182 2369 signed char sl,tl;
cf95b4f0 2370 tl=get_reg(i_regs->regmap,dops[i].rt1);
2371 sl=get_reg(i_regs->regmap,dops[i].rs1);
57871462 2372 if(tl>=0) {
cf95b4f0 2373 if(dops[i].rs1) {
57871462 2374 assert(sl>=0);
7c3a5182 2375 emit_addimm(sl,imm[i],tl);
57871462 2376 } else {
2377 emit_movimm(imm[i],tl);
57871462 2378 }
2379 }
2380 }
2381 }
cf95b4f0 2382 else if(dops[i].opcode==0x0a||dops[i].opcode==0x0b) { // SLTI/SLTIU
2383 if(dops[i].rt1) {
2384 //assert(dops[i].rs1!=0); // r0 might be valid, but it's probably a bug
ad49de89 2385 signed char sl,t;
cf95b4f0 2386 t=get_reg(i_regs->regmap,dops[i].rt1);
2387 sl=get_reg(i_regs->regmap,dops[i].rs1);
57871462 2388 //assert(t>=0);
2389 if(t>=0) {
cf95b4f0 2390 if(dops[i].rs1>0) {
2391 if(dops[i].opcode==0x0a) { // SLTI
57871462 2392 if(sl<0) {
cf95b4f0 2393 if(i_regs->regmap_entry[t]!=dops[i].rs1) emit_loadreg(dops[i].rs1,t);
57871462 2394 emit_slti32(t,imm[i],t);
2395 }else{
2396 emit_slti32(sl,imm[i],t);
2397 }
2398 }
2399 else { // SLTIU
2400 if(sl<0) {
cf95b4f0 2401 if(i_regs->regmap_entry[t]!=dops[i].rs1) emit_loadreg(dops[i].rs1,t);
57871462 2402 emit_sltiu32(t,imm[i],t);
2403 }else{
2404 emit_sltiu32(sl,imm[i],t);
2405 }
2406 }
57871462 2407 }else{
2408 // SLTI(U) with r0 is just stupid,
2409 // nonetheless examples can be found
cf95b4f0 2410 if(dops[i].opcode==0x0a) // SLTI
57871462 2411 if(0<imm[i]) emit_movimm(1,t);
2412 else emit_zeroreg(t);
2413 else // SLTIU
2414 {
2415 if(imm[i]) emit_movimm(1,t);
2416 else emit_zeroreg(t);
2417 }
2418 }
2419 }
2420 }
2421 }
cf95b4f0 2422 else if(dops[i].opcode>=0x0c&&dops[i].opcode<=0x0e) { // ANDI/ORI/XORI
2423 if(dops[i].rt1) {
7c3a5182 2424 signed char sl,tl;
cf95b4f0 2425 tl=get_reg(i_regs->regmap,dops[i].rt1);
2426 sl=get_reg(i_regs->regmap,dops[i].rs1);
57871462 2427 if(tl>=0 && !((i_regs->isconst>>tl)&1)) {
cf95b4f0 2428 if(dops[i].opcode==0x0c) //ANDI
57871462 2429 {
cf95b4f0 2430 if(dops[i].rs1) {
57871462 2431 if(sl<0) {
cf95b4f0 2432 if(i_regs->regmap_entry[tl]!=dops[i].rs1) emit_loadreg(dops[i].rs1,tl);
57871462 2433 emit_andimm(tl,imm[i],tl);
2434 }else{
2435 if(!((i_regs->wasconst>>sl)&1))
2436 emit_andimm(sl,imm[i],tl);
2437 else
2438 emit_movimm(constmap[i][sl]&imm[i],tl);
2439 }
2440 }
2441 else
2442 emit_zeroreg(tl);
57871462 2443 }
2444 else
2445 {
cf95b4f0 2446 if(dops[i].rs1) {
57871462 2447 if(sl<0) {
cf95b4f0 2448 if(i_regs->regmap_entry[tl]!=dops[i].rs1) emit_loadreg(dops[i].rs1,tl);
57871462 2449 }
cf95b4f0 2450 if(dops[i].opcode==0x0d) { // ORI
581335b0 2451 if(sl<0) {
2452 emit_orimm(tl,imm[i],tl);
2453 }else{
2454 if(!((i_regs->wasconst>>sl)&1))
2455 emit_orimm(sl,imm[i],tl);
2456 else
2457 emit_movimm(constmap[i][sl]|imm[i],tl);
2458 }
57871462 2459 }
cf95b4f0 2460 if(dops[i].opcode==0x0e) { // XORI
581335b0 2461 if(sl<0) {
2462 emit_xorimm(tl,imm[i],tl);
2463 }else{
2464 if(!((i_regs->wasconst>>sl)&1))
2465 emit_xorimm(sl,imm[i],tl);
2466 else
2467 emit_movimm(constmap[i][sl]^imm[i],tl);
2468 }
57871462 2469 }
2470 }
2471 else {
2472 emit_movimm(imm[i],tl);
57871462 2473 }
2474 }
2475 }
2476 }
2477 }
2478}
2479
2330734f 2480static void shiftimm_assemble(int i, const struct regstat *i_regs)
57871462 2481{
cf95b4f0 2482 if(dops[i].opcode2<=0x3) // SLL/SRL/SRA
57871462 2483 {
cf95b4f0 2484 if(dops[i].rt1) {
57871462 2485 signed char s,t;
cf95b4f0 2486 t=get_reg(i_regs->regmap,dops[i].rt1);
2487 s=get_reg(i_regs->regmap,dops[i].rs1);
57871462 2488 //assert(t>=0);
dc49e339 2489 if(t>=0&&!((i_regs->isconst>>t)&1)){
cf95b4f0 2490 if(dops[i].rs1==0)
57871462 2491 {
2492 emit_zeroreg(t);
2493 }
2494 else
2495 {
cf95b4f0 2496 if(s<0&&i_regs->regmap_entry[t]!=dops[i].rs1) emit_loadreg(dops[i].rs1,t);
57871462 2497 if(imm[i]) {
cf95b4f0 2498 if(dops[i].opcode2==0) // SLL
57871462 2499 {
2500 emit_shlimm(s<0?t:s,imm[i],t);
2501 }
cf95b4f0 2502 if(dops[i].opcode2==2) // SRL
57871462 2503 {
2504 emit_shrimm(s<0?t:s,imm[i],t);
2505 }
cf95b4f0 2506 if(dops[i].opcode2==3) // SRA
57871462 2507 {
2508 emit_sarimm(s<0?t:s,imm[i],t);
2509 }
2510 }else{
2511 // Shift by zero
2512 if(s>=0 && s!=t) emit_mov(s,t);
2513 }
2514 }
2515 }
cf95b4f0 2516 //emit_storereg(dops[i].rt1,t); //DEBUG
57871462 2517 }
2518 }
cf95b4f0 2519 if(dops[i].opcode2>=0x38&&dops[i].opcode2<=0x3b) // DSLL/DSRL/DSRA
57871462 2520 {
9c45ca93 2521 assert(0);
57871462 2522 }
cf95b4f0 2523 if(dops[i].opcode2==0x3c) // DSLL32
57871462 2524 {
9c45ca93 2525 assert(0);
57871462 2526 }
cf95b4f0 2527 if(dops[i].opcode2==0x3e) // DSRL32
57871462 2528 {
9c45ca93 2529 assert(0);
57871462 2530 }
cf95b4f0 2531 if(dops[i].opcode2==0x3f) // DSRA32
57871462 2532 {
9c45ca93 2533 assert(0);
57871462 2534 }
2535}
2536
2537#ifndef shift_assemble
2330734f 2538static void shift_assemble(int i, const struct regstat *i_regs)
57871462 2539{
3968e69e 2540 signed char s,t,shift;
cf95b4f0 2541 if (dops[i].rt1 == 0)
3968e69e 2542 return;
cf95b4f0 2543 assert(dops[i].opcode2<=0x07); // SLLV/SRLV/SRAV
2544 t = get_reg(i_regs->regmap, dops[i].rt1);
2545 s = get_reg(i_regs->regmap, dops[i].rs1);
2546 shift = get_reg(i_regs->regmap, dops[i].rs2);
3968e69e 2547 if (t < 0)
2548 return;
2549
cf95b4f0 2550 if(dops[i].rs1==0)
3968e69e 2551 emit_zeroreg(t);
cf95b4f0 2552 else if(dops[i].rs2==0) {
3968e69e 2553 assert(s>=0);
2554 if(s!=t) emit_mov(s,t);
2555 }
2556 else {
2557 host_tempreg_acquire();
2558 emit_andimm(shift,31,HOST_TEMPREG);
cf95b4f0 2559 switch(dops[i].opcode2) {
3968e69e 2560 case 4: // SLLV
2561 emit_shl(s,HOST_TEMPREG,t);
2562 break;
2563 case 6: // SRLV
2564 emit_shr(s,HOST_TEMPREG,t);
2565 break;
2566 case 7: // SRAV
2567 emit_sar(s,HOST_TEMPREG,t);
2568 break;
2569 default:
2570 assert(0);
2571 }
2572 host_tempreg_release();
2573 }
57871462 2574}
3968e69e 2575
57871462 2576#endif
2577
8062d65a 2578enum {
2579 MTYPE_8000 = 0,
2580 MTYPE_8020,
2581 MTYPE_0000,
2582 MTYPE_A000,
2583 MTYPE_1F80,
2584};
2585
2586static int get_ptr_mem_type(u_int a)
2587{
2588 if(a < 0x00200000) {
2589 if(a<0x1000&&((start>>20)==0xbfc||(start>>24)==0xa0))
2590 // return wrong, must use memhandler for BIOS self-test to pass
2591 // 007 does similar stuff from a00 mirror, weird stuff
2592 return MTYPE_8000;
2593 return MTYPE_0000;
2594 }
2595 if(0x1f800000 <= a && a < 0x1f801000)
2596 return MTYPE_1F80;
2597 if(0x80200000 <= a && a < 0x80800000)
2598 return MTYPE_8020;
2599 if(0xa0000000 <= a && a < 0xa0200000)
2600 return MTYPE_A000;
2601 return MTYPE_8000;
2602}
2603
37387d8b 2604static int get_ro_reg(const struct regstat *i_regs, int host_tempreg_free)
2605{
2606 int r = get_reg(i_regs->regmap, ROREG);
2607 if (r < 0 && host_tempreg_free) {
2608 host_tempreg_acquire();
2609 emit_loadreg(ROREG, r = HOST_TEMPREG);
2610 }
2611 if (r < 0)
2612 abort();
2613 return r;
2614}
2615
2616static void *emit_fastpath_cmp_jump(int i, const struct regstat *i_regs,
2617 int addr, int *offset_reg, int *addr_reg_override)
8062d65a 2618{
2619 void *jaddr = NULL;
37387d8b 2620 int type = 0;
2621 int mr = dops[i].rs1;
2622 *offset_reg = -1;
8062d65a 2623 if(((smrv_strong|smrv_weak)>>mr)&1) {
2624 type=get_ptr_mem_type(smrv[mr]);
2625 //printf("set %08x @%08x r%d %d\n", smrv[mr], start+i*4, mr, type);
2626 }
2627 else {
2628 // use the mirror we are running on
2629 type=get_ptr_mem_type(start);
2630 //printf("set nospec @%08x r%d %d\n", start+i*4, mr, type);
2631 }
2632
2633 if(type==MTYPE_8020) { // RAM 80200000+ mirror
d1e4ebd9 2634 host_tempreg_acquire();
8062d65a 2635 emit_andimm(addr,~0x00e00000,HOST_TEMPREG);
2636 addr=*addr_reg_override=HOST_TEMPREG;
2637 type=0;
2638 }
2639 else if(type==MTYPE_0000) { // RAM 0 mirror
d1e4ebd9 2640 host_tempreg_acquire();
8062d65a 2641 emit_orimm(addr,0x80000000,HOST_TEMPREG);
2642 addr=*addr_reg_override=HOST_TEMPREG;
2643 type=0;
2644 }
2645 else if(type==MTYPE_A000) { // RAM A mirror
d1e4ebd9 2646 host_tempreg_acquire();
8062d65a 2647 emit_andimm(addr,~0x20000000,HOST_TEMPREG);
2648 addr=*addr_reg_override=HOST_TEMPREG;
2649 type=0;
2650 }
2651 else if(type==MTYPE_1F80) { // scratchpad
2652 if (psxH == (void *)0x1f800000) {
d1e4ebd9 2653 host_tempreg_acquire();
3968e69e 2654 emit_xorimm(addr,0x1f800000,HOST_TEMPREG);
8062d65a 2655 emit_cmpimm(HOST_TEMPREG,0x1000);
d1e4ebd9 2656 host_tempreg_release();
8062d65a 2657 jaddr=out;
2658 emit_jc(0);
2659 }
2660 else {
2661 // do the usual RAM check, jump will go to the right handler
2662 type=0;
2663 }
2664 }
2665
37387d8b 2666 if (type == 0) // need ram check
8062d65a 2667 {
2668 emit_cmpimm(addr,RAM_SIZE);
37387d8b 2669 jaddr = out;
8062d65a 2670 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
2671 // Hint to branch predictor that the branch is unlikely to be taken
37387d8b 2672 if (dops[i].rs1 >= 28)
8062d65a 2673 emit_jno_unlikely(0);
2674 else
2675 #endif
2676 emit_jno(0);
37387d8b 2677 if (ram_offset != 0)
2678 *offset_reg = get_ro_reg(i_regs, 0);
8062d65a 2679 }
2680
2681 return jaddr;
2682}
2683
687b4580 2684// return memhandler, or get directly accessable address and return 0
2685static void *get_direct_memhandler(void *table, u_int addr,
2686 enum stub_type type, uintptr_t *addr_host)
2687{
c979e8c2 2688 uintptr_t msb = 1ull << (sizeof(uintptr_t)*8 - 1);
687b4580 2689 uintptr_t l1, l2 = 0;
2690 l1 = ((uintptr_t *)table)[addr>>12];
c979e8c2 2691 if (!(l1 & msb)) {
687b4580 2692 uintptr_t v = l1 << 1;
2693 *addr_host = v + addr;
2694 return NULL;
2695 }
2696 else {
2697 l1 <<= 1;
2698 if (type == LOADB_STUB || type == LOADBU_STUB || type == STOREB_STUB)
2699 l2 = ((uintptr_t *)l1)[0x1000/4 + 0x1000/2 + (addr&0xfff)];
2700 else if (type == LOADH_STUB || type == LOADHU_STUB || type == STOREH_STUB)
c979e8c2 2701 l2 = ((uintptr_t *)l1)[0x1000/4 + (addr&0xfff)/2];
687b4580 2702 else
c979e8c2 2703 l2 = ((uintptr_t *)l1)[(addr&0xfff)/4];
2704 if (!(l2 & msb)) {
687b4580 2705 uintptr_t v = l2 << 1;
2706 *addr_host = v + (addr&0xfff);
2707 return NULL;
2708 }
2709 return (void *)(l2 << 1);
2710 }
2711}
2712
81dbbf4c 2713static u_int get_host_reglist(const signed char *regmap)
2714{
2715 u_int reglist = 0, hr;
2716 for (hr = 0; hr < HOST_REGS; hr++) {
2717 if (hr != EXCLUDE_REG && regmap[hr] >= 0)
2718 reglist |= 1 << hr;
2719 }
2720 return reglist;
2721}
2722
2723static u_int reglist_exclude(u_int reglist, int r1, int r2)
2724{
2725 if (r1 >= 0)
2726 reglist &= ~(1u << r1);
2727 if (r2 >= 0)
2728 reglist &= ~(1u << r2);
2729 return reglist;
2730}
2731
e3c6bdb5 2732// find a temp caller-saved register not in reglist (so assumed to be free)
2733static int reglist_find_free(u_int reglist)
2734{
2735 u_int free_regs = ~reglist & CALLER_SAVE_REGS;
2736 if (free_regs == 0)
2737 return -1;
2738 return __builtin_ctz(free_regs);
2739}
2740
37387d8b 2741static void do_load_word(int a, int rt, int offset_reg)
2742{
2743 if (offset_reg >= 0)
2744 emit_ldr_dualindexed(offset_reg, a, rt);
2745 else
2746 emit_readword_indexed(0, a, rt);
2747}
2748
2749static void do_store_word(int a, int ofs, int rt, int offset_reg, int preseve_a)
2750{
2751 if (offset_reg < 0) {
2752 emit_writeword_indexed(rt, ofs, a);
2753 return;
2754 }
2755 if (ofs != 0)
2756 emit_addimm(a, ofs, a);
2757 emit_str_dualindexed(offset_reg, a, rt);
2758 if (ofs != 0 && preseve_a)
2759 emit_addimm(a, -ofs, a);
2760}
2761
2762static void do_store_hword(int a, int ofs, int rt, int offset_reg, int preseve_a)
2763{
2764 if (offset_reg < 0) {
2765 emit_writehword_indexed(rt, ofs, a);
2766 return;
2767 }
2768 if (ofs != 0)
2769 emit_addimm(a, ofs, a);
2770 emit_strh_dualindexed(offset_reg, a, rt);
2771 if (ofs != 0 && preseve_a)
2772 emit_addimm(a, -ofs, a);
2773}
2774
2775static void do_store_byte(int a, int rt, int offset_reg)
2776{
2777 if (offset_reg >= 0)
2778 emit_strb_dualindexed(offset_reg, a, rt);
2779 else
2780 emit_writebyte_indexed(rt, 0, a);
2781}
2782
2330734f 2783static void load_assemble(int i, const struct regstat *i_regs, int ccadj_)
57871462 2784{
7c3a5182 2785 int s,tl,addr;
57871462 2786 int offset;
b14b6a8f 2787 void *jaddr=0;
5bf843dc 2788 int memtarget=0,c=0;
37387d8b 2789 int offset_reg = -1;
2790 int fastio_reg_override = -1;
81dbbf4c 2791 u_int reglist=get_host_reglist(i_regs->regmap);
cf95b4f0 2792 tl=get_reg(i_regs->regmap,dops[i].rt1);
2793 s=get_reg(i_regs->regmap,dops[i].rs1);
57871462 2794 offset=imm[i];
57871462 2795 if(i_regs->regmap[HOST_CCREG]==CCREG) reglist&=~(1<<HOST_CCREG);
2796 if(s>=0) {
2797 c=(i_regs->wasconst>>s)&1;
af4ee1fe 2798 if (c) {
2799 memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
af4ee1fe 2800 }
57871462 2801 }
57871462 2802 //printf("load_assemble: c=%d\n",c);
643aeae3 2803 //if(c) printf("load_assemble: const=%lx\n",(long)constmap[i][s]+offset);
57871462 2804 // FIXME: Even if the load is a NOP, we should check for pagefaults...
581335b0 2805 if((tl<0&&(!c||(((u_int)constmap[i][s]+offset)>>16)==0x1f80))
cf95b4f0 2806 ||dops[i].rt1==0) {
5bf843dc 2807 // could be FIFO, must perform the read
f18c0f46 2808 // ||dummy read
5bf843dc 2809 assem_debug("(forced read)\n");
2810 tl=get_reg(i_regs->regmap,-1);
2811 assert(tl>=0);
5bf843dc 2812 }
2813 if(offset||s<0||c) addr=tl;
2814 else addr=s;
535d208a 2815 //if(tl<0) tl=get_reg(i_regs->regmap,-1);
2816 if(tl>=0) {
2817 //printf("load_assemble: c=%d\n",c);
643aeae3 2818 //if(c) printf("load_assemble: const=%lx\n",(long)constmap[i][s]+offset);
535d208a 2819 assert(tl>=0); // Even if the load is a NOP, we must check for pagefaults and I/O
2820 reglist&=~(1<<tl);
1edfcc68 2821 if(!c) {
1edfcc68 2822 #ifdef R29_HACK
2823 // Strmnnrmn's speed hack
cf95b4f0 2824 if(dops[i].rs1!=29||start<0x80001000||start>=0x80000000+RAM_SIZE)
1edfcc68 2825 #endif
2826 {
37387d8b 2827 jaddr = emit_fastpath_cmp_jump(i, i_regs, addr,
2828 &offset_reg, &fastio_reg_override);
535d208a 2829 }
1edfcc68 2830 }
37387d8b 2831 else if (ram_offset && memtarget) {
2832 offset_reg = get_ro_reg(i_regs, 0);
535d208a 2833 }
cf95b4f0 2834 int dummy=(dops[i].rt1==0)||(tl!=get_reg(i_regs->regmap,dops[i].rt1)); // ignore loads to r0 and unneeded reg
37387d8b 2835 switch (dops[i].opcode) {
2836 case 0x20: // LB
535d208a 2837 if(!c||memtarget) {
2838 if(!dummy) {
37387d8b 2839 int a = tl;
2840 if (!c) a = addr;
2841 if (fastio_reg_override >= 0)
2842 a = fastio_reg_override;
b1570849 2843
37387d8b 2844 if (offset_reg >= 0)
2845 emit_ldrsb_dualindexed(offset_reg, a, tl);
2846 else
2847 emit_movsbl_indexed(0, a, tl);
57871462 2848 }
535d208a 2849 if(jaddr)
2330734f 2850 add_stub_r(LOADB_STUB,jaddr,out,i,addr,i_regs,ccadj_,reglist);
57871462 2851 }
535d208a 2852 else
2330734f 2853 inline_readstub(LOADB_STUB,i,constmap[i][s]+offset,i_regs->regmap,dops[i].rt1,ccadj_,reglist);
37387d8b 2854 break;
2855 case 0x21: // LH
535d208a 2856 if(!c||memtarget) {
2857 if(!dummy) {
37387d8b 2858 int a = tl;
2859 if (!c) a = addr;
2860 if (fastio_reg_override >= 0)
2861 a = fastio_reg_override;
2862 if (offset_reg >= 0)
2863 emit_ldrsh_dualindexed(offset_reg, a, tl);
2864 else
2865 emit_movswl_indexed(0, a, tl);
57871462 2866 }
535d208a 2867 if(jaddr)
2330734f 2868 add_stub_r(LOADH_STUB,jaddr,out,i,addr,i_regs,ccadj_,reglist);
57871462 2869 }
535d208a 2870 else
2330734f 2871 inline_readstub(LOADH_STUB,i,constmap[i][s]+offset,i_regs->regmap,dops[i].rt1,ccadj_,reglist);
37387d8b 2872 break;
2873 case 0x23: // LW
535d208a 2874 if(!c||memtarget) {
2875 if(!dummy) {
37387d8b 2876 int a = addr;
2877 if (fastio_reg_override >= 0)
2878 a = fastio_reg_override;
2879 do_load_word(a, tl, offset_reg);
57871462 2880 }
535d208a 2881 if(jaddr)
2330734f 2882 add_stub_r(LOADW_STUB,jaddr,out,i,addr,i_regs,ccadj_,reglist);
57871462 2883 }
535d208a 2884 else
2330734f 2885 inline_readstub(LOADW_STUB,i,constmap[i][s]+offset,i_regs->regmap,dops[i].rt1,ccadj_,reglist);
37387d8b 2886 break;
2887 case 0x24: // LBU
535d208a 2888 if(!c||memtarget) {
2889 if(!dummy) {
37387d8b 2890 int a = tl;
2891 if (!c) a = addr;
2892 if (fastio_reg_override >= 0)
2893 a = fastio_reg_override;
b1570849 2894
37387d8b 2895 if (offset_reg >= 0)
2896 emit_ldrb_dualindexed(offset_reg, a, tl);
2897 else
2898 emit_movzbl_indexed(0, a, tl);
57871462 2899 }
535d208a 2900 if(jaddr)
2330734f 2901 add_stub_r(LOADBU_STUB,jaddr,out,i,addr,i_regs,ccadj_,reglist);
57871462 2902 }
535d208a 2903 else
2330734f 2904 inline_readstub(LOADBU_STUB,i,constmap[i][s]+offset,i_regs->regmap,dops[i].rt1,ccadj_,reglist);
37387d8b 2905 break;
2906 case 0x25: // LHU
535d208a 2907 if(!c||memtarget) {
2908 if(!dummy) {
37387d8b 2909 int a = tl;
2910 if(!c) a = addr;
2911 if (fastio_reg_override >= 0)
2912 a = fastio_reg_override;
2913 if (offset_reg >= 0)
2914 emit_ldrh_dualindexed(offset_reg, a, tl);
2915 else
2916 emit_movzwl_indexed(0, a, tl);
57871462 2917 }
535d208a 2918 if(jaddr)
2330734f 2919 add_stub_r(LOADHU_STUB,jaddr,out,i,addr,i_regs,ccadj_,reglist);
57871462 2920 }
535d208a 2921 else
2330734f 2922 inline_readstub(LOADHU_STUB,i,constmap[i][s]+offset,i_regs->regmap,dops[i].rt1,ccadj_,reglist);
37387d8b 2923 break;
2924 case 0x27: // LWU
2925 case 0x37: // LD
2926 default:
9c45ca93 2927 assert(0);
57871462 2928 }
535d208a 2929 }
37387d8b 2930 if (fastio_reg_override == HOST_TEMPREG || offset_reg == HOST_TEMPREG)
d1e4ebd9 2931 host_tempreg_release();
57871462 2932}
2933
2934#ifndef loadlr_assemble
2330734f 2935static void loadlr_assemble(int i, const struct regstat *i_regs, int ccadj_)
57871462 2936{
3968e69e 2937 int s,tl,temp,temp2,addr;
2938 int offset;
2939 void *jaddr=0;
2940 int memtarget=0,c=0;
37387d8b 2941 int offset_reg = -1;
2942 int fastio_reg_override = -1;
81dbbf4c 2943 u_int reglist=get_host_reglist(i_regs->regmap);
cf95b4f0 2944 tl=get_reg(i_regs->regmap,dops[i].rt1);
2945 s=get_reg(i_regs->regmap,dops[i].rs1);
3968e69e 2946 temp=get_reg(i_regs->regmap,-1);
2947 temp2=get_reg(i_regs->regmap,FTEMP);
2948 addr=get_reg(i_regs->regmap,AGEN1+(i&1));
2949 assert(addr<0);
2950 offset=imm[i];
3968e69e 2951 reglist|=1<<temp;
2952 if(offset||s<0||c) addr=temp2;
2953 else addr=s;
2954 if(s>=0) {
2955 c=(i_regs->wasconst>>s)&1;
2956 if(c) {
2957 memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
2958 }
2959 }
2960 if(!c) {
2961 emit_shlimm(addr,3,temp);
cf95b4f0 2962 if (dops[i].opcode==0x22||dops[i].opcode==0x26) {
3968e69e 2963 emit_andimm(addr,0xFFFFFFFC,temp2); // LWL/LWR
2964 }else{
2965 emit_andimm(addr,0xFFFFFFF8,temp2); // LDL/LDR
2966 }
37387d8b 2967 jaddr = emit_fastpath_cmp_jump(i, i_regs, temp2,
2968 &offset_reg, &fastio_reg_override);
3968e69e 2969 }
2970 else {
37387d8b 2971 if (ram_offset && memtarget) {
2972 offset_reg = get_ro_reg(i_regs, 0);
3968e69e 2973 }
cf95b4f0 2974 if (dops[i].opcode==0x22||dops[i].opcode==0x26) {
3968e69e 2975 emit_movimm(((constmap[i][s]+offset)<<3)&24,temp); // LWL/LWR
2976 }else{
2977 emit_movimm(((constmap[i][s]+offset)<<3)&56,temp); // LDL/LDR
2978 }
2979 }
cf95b4f0 2980 if (dops[i].opcode==0x22||dops[i].opcode==0x26) { // LWL/LWR
3968e69e 2981 if(!c||memtarget) {
37387d8b 2982 int a = temp2;
2983 if (fastio_reg_override >= 0)
2984 a = fastio_reg_override;
2985 do_load_word(a, temp2, offset_reg);
2986 if (fastio_reg_override == HOST_TEMPREG || offset_reg == HOST_TEMPREG)
2987 host_tempreg_release();
2330734f 2988 if(jaddr) add_stub_r(LOADW_STUB,jaddr,out,i,temp2,i_regs,ccadj_,reglist);
3968e69e 2989 }
2990 else
2330734f 2991 inline_readstub(LOADW_STUB,i,(constmap[i][s]+offset)&0xFFFFFFFC,i_regs->regmap,FTEMP,ccadj_,reglist);
cf95b4f0 2992 if(dops[i].rt1) {
3968e69e 2993 assert(tl>=0);
2994 emit_andimm(temp,24,temp);
cf95b4f0 2995 if (dops[i].opcode==0x22) // LWL
3968e69e 2996 emit_xorimm(temp,24,temp);
2997 host_tempreg_acquire();
2998 emit_movimm(-1,HOST_TEMPREG);
cf95b4f0 2999 if (dops[i].opcode==0x26) {
3968e69e 3000 emit_shr(temp2,temp,temp2);
3001 emit_bic_lsr(tl,HOST_TEMPREG,temp,tl);
3002 }else{
3003 emit_shl(temp2,temp,temp2);
3004 emit_bic_lsl(tl,HOST_TEMPREG,temp,tl);
3005 }
3006 host_tempreg_release();
3007 emit_or(temp2,tl,tl);
3008 }
cf95b4f0 3009 //emit_storereg(dops[i].rt1,tl); // DEBUG
3968e69e 3010 }
cf95b4f0 3011 if (dops[i].opcode==0x1A||dops[i].opcode==0x1B) { // LDL/LDR
3968e69e 3012 assert(0);
3013 }
57871462 3014}
3015#endif
3016
2330734f 3017static void store_assemble(int i, const struct regstat *i_regs, int ccadj_)
57871462 3018{
9c45ca93 3019 int s,tl;
57871462 3020 int addr,temp;
3021 int offset;
b14b6a8f 3022 void *jaddr=0;
37387d8b 3023 enum stub_type type=0;
666a299d 3024 int memtarget=0,c=0;
57871462 3025 int agr=AGEN1+(i&1);
37387d8b 3026 int offset_reg = -1;
3027 int fastio_reg_override = -1;
81dbbf4c 3028 u_int reglist=get_host_reglist(i_regs->regmap);
cf95b4f0 3029 tl=get_reg(i_regs->regmap,dops[i].rs2);
3030 s=get_reg(i_regs->regmap,dops[i].rs1);
57871462 3031 temp=get_reg(i_regs->regmap,agr);
3032 if(temp<0) temp=get_reg(i_regs->regmap,-1);
3033 offset=imm[i];
3034 if(s>=0) {
3035 c=(i_regs->wasconst>>s)&1;
af4ee1fe 3036 if(c) {
3037 memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
af4ee1fe 3038 }
57871462 3039 }
3040 assert(tl>=0);
3041 assert(temp>=0);
57871462 3042 if(i_regs->regmap[HOST_CCREG]==CCREG) reglist&=~(1<<HOST_CCREG);
3043 if(offset||s<0||c) addr=temp;
3044 else addr=s;
37387d8b 3045 if (!c) {
3046 jaddr = emit_fastpath_cmp_jump(i, i_regs, addr,
3047 &offset_reg, &fastio_reg_override);
1edfcc68 3048 }
37387d8b 3049 else if (ram_offset && memtarget) {
3050 offset_reg = get_ro_reg(i_regs, 0);
57871462 3051 }
3052
37387d8b 3053 switch (dops[i].opcode) {
3054 case 0x28: // SB
57871462 3055 if(!c||memtarget) {
37387d8b 3056 int a = temp;
3057 if (!c) a = addr;
3058 if (fastio_reg_override >= 0)
3059 a = fastio_reg_override;
3060 do_store_byte(a, tl, offset_reg);
3061 }
3062 type = STOREB_STUB;
3063 break;
3064 case 0x29: // SH
57871462 3065 if(!c||memtarget) {
37387d8b 3066 int a = temp;
3067 if (!c) a = addr;
3068 if (fastio_reg_override >= 0)
3069 a = fastio_reg_override;
3070 do_store_hword(a, 0, tl, offset_reg, 1);
3071 }
3072 type = STOREH_STUB;
3073 break;
3074 case 0x2B: // SW
dadf55f2 3075 if(!c||memtarget) {
37387d8b 3076 int a = addr;
3077 if (fastio_reg_override >= 0)
3078 a = fastio_reg_override;
3079 do_store_word(a, 0, tl, offset_reg, 1);
3080 }
3081 type = STOREW_STUB;
3082 break;
3083 case 0x3F: // SD
3084 default:
9c45ca93 3085 assert(0);
57871462 3086 }
37387d8b 3087 if (fastio_reg_override == HOST_TEMPREG || offset_reg == HOST_TEMPREG)
d1e4ebd9 3088 host_tempreg_release();
b96d3df7 3089 if(jaddr) {
3090 // PCSX store handlers don't check invcode again
3091 reglist|=1<<addr;
2330734f 3092 add_stub_r(type,jaddr,out,i,addr,i_regs,ccadj_,reglist);
b96d3df7 3093 jaddr=0;
3094 }
cf95b4f0 3095 if(!(i_regs->waswritten&(1<<dops[i].rs1)) && !HACK_ENABLED(NDHACK_NO_SMC_CHECK)) {
57871462 3096 if(!c||memtarget) {
3097 #ifdef DESTRUCTIVE_SHIFT
3098 // The x86 shift operation is 'destructive'; it overwrites the
3099 // source register, so we need to make a copy first and use that.
3100 addr=temp;
3101 #endif
3102 #if defined(HOST_IMM8)
3103 int ir=get_reg(i_regs->regmap,INVCP);
3104 assert(ir>=0);
3105 emit_cmpmem_indexedsr12_reg(ir,addr,1);
3106 #else
643aeae3 3107 emit_cmpmem_indexedsr12_imm(invalid_code,addr,1);
57871462 3108 #endif
0bbd1454 3109 #if defined(HAVE_CONDITIONAL_CALL) && !defined(DESTRUCTIVE_SHIFT)
3110 emit_callne(invalidate_addr_reg[addr]);
3111 #else
b14b6a8f 3112 void *jaddr2 = out;
57871462 3113 emit_jne(0);
b14b6a8f 3114 add_stub(INVCODE_STUB,jaddr2,out,reglist|(1<<HOST_CCREG),addr,0,0,0);
0bbd1454 3115 #endif
57871462 3116 }
3117 }
7a518516 3118 u_int addr_val=constmap[i][s]+offset;
3eaa7048 3119 if(jaddr) {
2330734f 3120 add_stub_r(type,jaddr,out,i,addr,i_regs,ccadj_,reglist);
3eaa7048 3121 } else if(c&&!memtarget) {
2330734f 3122 inline_writestub(type,i,addr_val,i_regs->regmap,dops[i].rs2,ccadj_,reglist);
7a518516 3123 }
3124 // basic current block modification detection..
3125 // not looking back as that should be in mips cache already
3968e69e 3126 // (see Spyro2 title->attract mode)
7a518516 3127 if(c&&start+i*4<addr_val&&addr_val<start+slen*4) {
c43b5311 3128 SysPrintf("write to %08x hits block %08x, pc=%08x\n",addr_val,start,start+i*4);
7a518516 3129 assert(i_regs->regmap==regs[i].regmap); // not delay slot
3130 if(i_regs->regmap==regs[i].regmap) {
ad49de89 3131 load_all_consts(regs[i].regmap_entry,regs[i].wasdirty,i);
3132 wb_dirtys(regs[i].regmap_entry,regs[i].wasdirty);
7a518516 3133 emit_movimm(start+i*4+4,0);
643aeae3 3134 emit_writeword(0,&pcaddr);
d1e4ebd9 3135 emit_addimm(HOST_CCREG,2,HOST_CCREG);
2a014d73 3136 emit_far_call(get_addr_ht);
d1e4ebd9 3137 emit_jmpreg(0);
7a518516 3138 }
3eaa7048 3139 }
57871462 3140}
3141
2330734f 3142static void storelr_assemble(int i, const struct regstat *i_regs, int ccadj_)
57871462 3143{
9c45ca93 3144 int s,tl;
57871462 3145 int temp;
57871462 3146 int offset;
b14b6a8f 3147 void *jaddr=0;
37387d8b 3148 void *case1, *case23, *case3;
df4dc2b1 3149 void *done0, *done1, *done2;
af4ee1fe 3150 int memtarget=0,c=0;
fab5d06d 3151 int agr=AGEN1+(i&1);
37387d8b 3152 int offset_reg = -1;
81dbbf4c 3153 u_int reglist=get_host_reglist(i_regs->regmap);
cf95b4f0 3154 tl=get_reg(i_regs->regmap,dops[i].rs2);
3155 s=get_reg(i_regs->regmap,dops[i].rs1);
fab5d06d 3156 temp=get_reg(i_regs->regmap,agr);
3157 if(temp<0) temp=get_reg(i_regs->regmap,-1);
57871462 3158 offset=imm[i];
3159 if(s>=0) {
3160 c=(i_regs->isconst>>s)&1;
af4ee1fe 3161 if(c) {
3162 memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
af4ee1fe 3163 }
57871462 3164 }
3165 assert(tl>=0);
535d208a 3166 assert(temp>=0);
1edfcc68 3167 if(!c) {
3168 emit_cmpimm(s<0||offset?temp:s,RAM_SIZE);
3169 if(!offset&&s!=temp) emit_mov(s,temp);
b14b6a8f 3170 jaddr=out;
1edfcc68 3171 emit_jno(0);
3172 }
3173 else
3174 {
cf95b4f0 3175 if(!memtarget||!dops[i].rs1) {
b14b6a8f 3176 jaddr=out;
535d208a 3177 emit_jmp(0);
57871462 3178 }
535d208a 3179 }
37387d8b 3180 if (ram_offset)
3181 offset_reg = get_ro_reg(i_regs, 0);
535d208a 3182
cf95b4f0 3183 if (dops[i].opcode==0x2C||dops[i].opcode==0x2D) { // SDL/SDR
9c45ca93 3184 assert(0);
535d208a 3185 }
57871462 3186
535d208a 3187 emit_testimm(temp,2);
37387d8b 3188 case23=out;
535d208a 3189 emit_jne(0);
3190 emit_testimm(temp,1);
df4dc2b1 3191 case1=out;
535d208a 3192 emit_jne(0);
3193 // 0
37387d8b 3194 if (dops[i].opcode == 0x2A) { // SWL
3195 // Write msb into least significant byte
3196 if (dops[i].rs2) emit_rorimm(tl, 24, tl);
3197 do_store_byte(temp, tl, offset_reg);
3198 if (dops[i].rs2) emit_rorimm(tl, 8, tl);
535d208a 3199 }
37387d8b 3200 else if (dops[i].opcode == 0x2E) { // SWR
3201 // Write entire word
3202 do_store_word(temp, 0, tl, offset_reg, 1);
535d208a 3203 }
37387d8b 3204 done0 = out;
535d208a 3205 emit_jmp(0);
3206 // 1
df4dc2b1 3207 set_jump_target(case1, out);
37387d8b 3208 if (dops[i].opcode == 0x2A) { // SWL
3209 // Write two msb into two least significant bytes
3210 if (dops[i].rs2) emit_rorimm(tl, 16, tl);
3211 do_store_hword(temp, -1, tl, offset_reg, 0);
3212 if (dops[i].rs2) emit_rorimm(tl, 16, tl);
535d208a 3213 }
37387d8b 3214 else if (dops[i].opcode == 0x2E) { // SWR
3215 // Write 3 lsb into three most significant bytes
3216 do_store_byte(temp, tl, offset_reg);
3217 if (dops[i].rs2) emit_rorimm(tl, 8, tl);
3218 do_store_hword(temp, 1, tl, offset_reg, 0);
3219 if (dops[i].rs2) emit_rorimm(tl, 24, tl);
535d208a 3220 }
df4dc2b1 3221 done1=out;
535d208a 3222 emit_jmp(0);
37387d8b 3223 // 2,3
3224 set_jump_target(case23, out);
535d208a 3225 emit_testimm(temp,1);
37387d8b 3226 case3 = out;
535d208a 3227 emit_jne(0);
37387d8b 3228 // 2
cf95b4f0 3229 if (dops[i].opcode==0x2A) { // SWL
37387d8b 3230 // Write 3 msb into three least significant bytes
3231 if (dops[i].rs2) emit_rorimm(tl, 8, tl);
3232 do_store_hword(temp, -2, tl, offset_reg, 1);
3233 if (dops[i].rs2) emit_rorimm(tl, 16, tl);
3234 do_store_byte(temp, tl, offset_reg);
3235 if (dops[i].rs2) emit_rorimm(tl, 8, tl);
535d208a 3236 }
37387d8b 3237 else if (dops[i].opcode == 0x2E) { // SWR
3238 // Write two lsb into two most significant bytes
3239 do_store_hword(temp, 0, tl, offset_reg, 1);
535d208a 3240 }
37387d8b 3241 done2 = out;
535d208a 3242 emit_jmp(0);
3243 // 3
df4dc2b1 3244 set_jump_target(case3, out);
37387d8b 3245 if (dops[i].opcode == 0x2A) { // SWL
3246 do_store_word(temp, -3, tl, offset_reg, 0);
535d208a 3247 }
37387d8b 3248 else if (dops[i].opcode == 0x2E) { // SWR
3249 do_store_byte(temp, tl, offset_reg);
535d208a 3250 }
df4dc2b1 3251 set_jump_target(done0, out);
3252 set_jump_target(done1, out);
3253 set_jump_target(done2, out);
37387d8b 3254 if (offset_reg == HOST_TEMPREG)
3255 host_tempreg_release();
535d208a 3256 if(!c||!memtarget)
2330734f 3257 add_stub_r(STORELR_STUB,jaddr,out,i,temp,i_regs,ccadj_,reglist);
cf95b4f0 3258 if(!(i_regs->waswritten&(1<<dops[i].rs1)) && !HACK_ENABLED(NDHACK_NO_SMC_CHECK)) {
57871462 3259 #if defined(HOST_IMM8)
3260 int ir=get_reg(i_regs->regmap,INVCP);
3261 assert(ir>=0);
3262 emit_cmpmem_indexedsr12_reg(ir,temp,1);
3263 #else
643aeae3 3264 emit_cmpmem_indexedsr12_imm(invalid_code,temp,1);
57871462 3265 #endif
535d208a 3266 #if defined(HAVE_CONDITIONAL_CALL) && !defined(DESTRUCTIVE_SHIFT)
3267 emit_callne(invalidate_addr_reg[temp]);
3268 #else
b14b6a8f 3269 void *jaddr2 = out;
57871462 3270 emit_jne(0);
b14b6a8f 3271 add_stub(INVCODE_STUB,jaddr2,out,reglist|(1<<HOST_CCREG),temp,0,0,0);
535d208a 3272 #endif
57871462 3273 }
57871462 3274}
3275
2330734f 3276static void cop0_assemble(int i, const struct regstat *i_regs, int ccadj_)
8062d65a 3277{
cf95b4f0 3278 if(dops[i].opcode2==0) // MFC0
8062d65a 3279 {
cf95b4f0 3280 signed char t=get_reg(i_regs->regmap,dops[i].rt1);
8062d65a 3281 u_int copr=(source[i]>>11)&0x1f;
3282 //assert(t>=0); // Why does this happen? OOT is weird
cf95b4f0 3283 if(t>=0&&dops[i].rt1!=0) {
8062d65a 3284 emit_readword(&reg_cop0[copr],t);
3285 }
3286 }
cf95b4f0 3287 else if(dops[i].opcode2==4) // MTC0
8062d65a 3288 {
cf95b4f0 3289 signed char s=get_reg(i_regs->regmap,dops[i].rs1);
8062d65a 3290 char copr=(source[i]>>11)&0x1f;
3291 assert(s>=0);
cf95b4f0 3292 wb_register(dops[i].rs1,i_regs->regmap,i_regs->dirty);
8062d65a 3293 if(copr==9||copr==11||copr==12||copr==13) {
3294 emit_readword(&last_count,HOST_TEMPREG);
3295 emit_loadreg(CCREG,HOST_CCREG); // TODO: do proper reg alloc
3296 emit_add(HOST_CCREG,HOST_TEMPREG,HOST_CCREG);
2330734f 3297 emit_addimm(HOST_CCREG,ccadj_,HOST_CCREG);
8062d65a 3298 emit_writeword(HOST_CCREG,&Count);
3299 }
3300 // What a mess. The status register (12) can enable interrupts,
3301 // so needs a special case to handle a pending interrupt.
3302 // The interrupt must be taken immediately, because a subsequent
3303 // instruction might disable interrupts again.
3304 if(copr==12||copr==13) {
3305 if (is_delayslot) {
3306 // burn cycles to cause cc_interrupt, which will
3307 // reschedule next_interupt. Relies on CCREG from above.
3308 assem_debug("MTC0 DS %d\n", copr);
3309 emit_writeword(HOST_CCREG,&last_count);
3310 emit_movimm(0,HOST_CCREG);
3311 emit_storereg(CCREG,HOST_CCREG);
cf95b4f0 3312 emit_loadreg(dops[i].rs1,1);
8062d65a 3313 emit_movimm(copr,0);
2a014d73 3314 emit_far_call(pcsx_mtc0_ds);
cf95b4f0 3315 emit_loadreg(dops[i].rs1,s);
8062d65a 3316 return;
3317 }
3318 emit_movimm(start+i*4+4,HOST_TEMPREG);
3319 emit_writeword(HOST_TEMPREG,&pcaddr);
3320 emit_movimm(0,HOST_TEMPREG);
3321 emit_writeword(HOST_TEMPREG,&pending_exception);
3322 }
8062d65a 3323 if(s==HOST_CCREG)
cf95b4f0 3324 emit_loadreg(dops[i].rs1,1);
8062d65a 3325 else if(s!=1)
3326 emit_mov(s,1);
3327 emit_movimm(copr,0);
2a014d73 3328 emit_far_call(pcsx_mtc0);
8062d65a 3329 if(copr==9||copr==11||copr==12||copr==13) {
3330 emit_readword(&Count,HOST_CCREG);
3331 emit_readword(&next_interupt,HOST_TEMPREG);
2330734f 3332 emit_addimm(HOST_CCREG,-ccadj_,HOST_CCREG);
8062d65a 3333 emit_sub(HOST_CCREG,HOST_TEMPREG,HOST_CCREG);
3334 emit_writeword(HOST_TEMPREG,&last_count);
3335 emit_storereg(CCREG,HOST_CCREG);
3336 }
3337 if(copr==12||copr==13) {
3338 assert(!is_delayslot);
3339 emit_readword(&pending_exception,14);
3340 emit_test(14,14);
d1e4ebd9 3341 void *jaddr = out;
3342 emit_jeq(0);
3343 emit_readword(&pcaddr, 0);
3344 emit_addimm(HOST_CCREG,2,HOST_CCREG);
2a014d73 3345 emit_far_call(get_addr_ht);
d1e4ebd9 3346 emit_jmpreg(0);
3347 set_jump_target(jaddr, out);
8062d65a 3348 }
cf95b4f0 3349 emit_loadreg(dops[i].rs1,s);
8062d65a 3350 }
3351 else
3352 {
cf95b4f0 3353 assert(dops[i].opcode2==0x10);
8062d65a 3354 //if((source[i]&0x3f)==0x10) // RFE
3355 {
3356 emit_readword(&Status,0);
3357 emit_andimm(0,0x3c,1);
3358 emit_andimm(0,~0xf,0);
3359 emit_orrshr_imm(1,2,0);
3360 emit_writeword(0,&Status);
3361 }
3362 }
3363}
3364
2330734f 3365static void cop1_unusable(int i, const struct regstat *i_regs)
8062d65a 3366{
3367 // XXX: should just just do the exception instead
3368 //if(!cop1_usable)
3369 {
3370 void *jaddr=out;
3371 emit_jmp(0);
3372 add_stub_r(FP_STUB,jaddr,out,i,0,i_regs,is_delayslot,0);
3373 }
3374}
3375
2330734f 3376static void cop1_assemble(int i, const struct regstat *i_regs)
8062d65a 3377{
3378 cop1_unusable(i, i_regs);
3379}
3380
2330734f 3381static void c1ls_assemble(int i, const struct regstat *i_regs)
57871462 3382{
3d624f89 3383 cop1_unusable(i, i_regs);
57871462 3384}
3385
8062d65a 3386// FP_STUB
3387static void do_cop1stub(int n)
3388{
3389 literal_pool(256);
3390 assem_debug("do_cop1stub %x\n",start+stubs[n].a*4);
3391 set_jump_target(stubs[n].addr, out);
3392 int i=stubs[n].a;
3393// int rs=stubs[n].b;
3394 struct regstat *i_regs=(struct regstat *)stubs[n].c;
3395 int ds=stubs[n].d;
3396 if(!ds) {
3397 load_all_consts(regs[i].regmap_entry,regs[i].wasdirty,i);
3398 //if(i_regs!=&regs[i]) printf("oops: regs[i]=%x i_regs=%x",(int)&regs[i],(int)i_regs);
3399 }
3400 //else {printf("fp exception in delay slot\n");}
3401 wb_dirtys(i_regs->regmap_entry,i_regs->wasdirty);
3402 if(regs[i].regmap_entry[HOST_CCREG]!=CCREG) emit_loadreg(CCREG,HOST_CCREG);
3403 emit_movimm(start+(i-ds)*4,EAX); // Get PC
2330734f 3404 emit_addimm(HOST_CCREG,ccadj[i],HOST_CCREG); // CHECK: is this right? There should probably be an extra cycle...
2a014d73 3405 emit_far_jump(ds?fp_exception_ds:fp_exception);
8062d65a 3406}
3407
e3c6bdb5 3408static int cop2_is_stalling_op(int i, int *cycles)
3409{
cf95b4f0 3410 if (dops[i].opcode == 0x3a) { // SWC2
e3c6bdb5 3411 *cycles = 0;
3412 return 1;
3413 }
cf95b4f0 3414 if (dops[i].itype == COP2 && (dops[i].opcode2 == 0 || dops[i].opcode2 == 2)) { // MFC2/CFC2
e3c6bdb5 3415 *cycles = 0;
3416 return 1;
3417 }
cf95b4f0 3418 if (dops[i].itype == C2OP) {
e3c6bdb5 3419 *cycles = gte_cycletab[source[i] & 0x3f];
3420 return 1;
3421 }
3422 // ... what about MTC2/CTC2/LWC2?
3423 return 0;
3424}
3425
3426#if 0
3427static void log_gte_stall(int stall, u_int cycle)
3428{
3429 if ((u_int)stall <= 44)
3430 printf("x stall %2d %u\n", stall, cycle + last_count);
e3c6bdb5 3431}
3432
3433static void emit_log_gte_stall(int i, int stall, u_int reglist)
3434{
3435 save_regs(reglist);
3436 if (stall > 0)
3437 emit_movimm(stall, 0);
3438 else
3439 emit_mov(HOST_TEMPREG, 0);
2330734f 3440 emit_addimm(HOST_CCREG, ccadj[i], 1);
e3c6bdb5 3441 emit_far_call(log_gte_stall);
3442 restore_regs(reglist);
3443}
3444#endif
3445
32631e6a 3446static void cop2_do_stall_check(u_int op, int i, const struct regstat *i_regs, u_int reglist)
81dbbf4c 3447{
e3c6bdb5 3448 int j = i, other_gte_op_cycles = -1, stall = -MAXBLOCK, cycles_passed;
3449 int rtmp = reglist_find_free(reglist);
3450
32631e6a 3451 if (HACK_ENABLED(NDHACK_NO_STALLS))
81dbbf4c 3452 return;
81dbbf4c 3453 if (get_reg(i_regs->regmap, CCREG) != HOST_CCREG) {
3454 // happens occasionally... cc evicted? Don't bother then
3455 //printf("no cc %08x\n", start + i*4);
3456 return;
3457 }
cf95b4f0 3458 if (!dops[i].bt) {
e3c6bdb5 3459 for (j = i - 1; j >= 0; j--) {
cf95b4f0 3460 //if (dops[j].is_ds) break;
3461 if (cop2_is_stalling_op(j, &other_gte_op_cycles) || dops[j].bt)
e3c6bdb5 3462 break;
2330734f 3463 if (j > 0 && ccadj[j - 1] > ccadj[j])
3464 break;
e3c6bdb5 3465 }
32631e6a 3466 j = max(j, 0);
e3c6bdb5 3467 }
2330734f 3468 cycles_passed = ccadj[i] - ccadj[j];
e3c6bdb5 3469 if (other_gte_op_cycles >= 0)
3470 stall = other_gte_op_cycles - cycles_passed;
3471 else if (cycles_passed >= 44)
3472 stall = 0; // can't stall
3473 if (stall == -MAXBLOCK && rtmp >= 0) {
3474 // unknown stall, do the expensive runtime check
32631e6a 3475 assem_debug("; cop2_do_stall_check\n");
e3c6bdb5 3476#if 0 // too slow
3477 save_regs(reglist);
3478 emit_movimm(gte_cycletab[op], 0);
2330734f 3479 emit_addimm(HOST_CCREG, ccadj[i], 1);
e3c6bdb5 3480 emit_far_call(call_gteStall);
3481 restore_regs(reglist);
3482#else
3483 host_tempreg_acquire();
3484 emit_readword(&psxRegs.gteBusyCycle, rtmp);
2330734f 3485 emit_addimm(rtmp, -ccadj[i], rtmp);
e3c6bdb5 3486 emit_sub(rtmp, HOST_CCREG, HOST_TEMPREG);
3487 emit_cmpimm(HOST_TEMPREG, 44);
3488 emit_cmovb_reg(rtmp, HOST_CCREG);
3489 //emit_log_gte_stall(i, 0, reglist);
3490 host_tempreg_release();
3491#endif
3492 }
3493 else if (stall > 0) {
3494 //emit_log_gte_stall(i, stall, reglist);
3495 emit_addimm(HOST_CCREG, stall, HOST_CCREG);
3496 }
3497
3498 // save gteBusyCycle, if needed
3499 if (gte_cycletab[op] == 0)
3500 return;
3501 other_gte_op_cycles = -1;
3502 for (j = i + 1; j < slen; j++) {
3503 if (cop2_is_stalling_op(j, &other_gte_op_cycles))
3504 break;
fe807a8a 3505 if (dops[j].is_jump) {
e3c6bdb5 3506 // check ds
3507 if (j + 1 < slen && cop2_is_stalling_op(j + 1, &other_gte_op_cycles))
3508 j++;
3509 break;
3510 }
3511 }
3512 if (other_gte_op_cycles >= 0)
3513 // will handle stall when assembling that op
3514 return;
2330734f 3515 cycles_passed = ccadj[min(j, slen -1)] - ccadj[i];
e3c6bdb5 3516 if (cycles_passed >= 44)
3517 return;
3518 assem_debug("; save gteBusyCycle\n");
3519 host_tempreg_acquire();
3520#if 0
3521 emit_readword(&last_count, HOST_TEMPREG);
3522 emit_add(HOST_TEMPREG, HOST_CCREG, HOST_TEMPREG);
2330734f 3523 emit_addimm(HOST_TEMPREG, ccadj[i], HOST_TEMPREG);
e3c6bdb5 3524 emit_addimm(HOST_TEMPREG, gte_cycletab[op]), HOST_TEMPREG);
3525 emit_writeword(HOST_TEMPREG, &psxRegs.gteBusyCycle);
3526#else
2330734f 3527 emit_addimm(HOST_CCREG, ccadj[i] + gte_cycletab[op], HOST_TEMPREG);
e3c6bdb5 3528 emit_writeword(HOST_TEMPREG, &psxRegs.gteBusyCycle);
3529#endif
3530 host_tempreg_release();
81dbbf4c 3531}
3532
32631e6a 3533static int is_mflohi(int i)
3534{
cf95b4f0 3535 return (dops[i].itype == MOV && (dops[i].rs1 == HIREG || dops[i].rs1 == LOREG));
32631e6a 3536}
3537
3538static int check_multdiv(int i, int *cycles)
3539{
cf95b4f0 3540 if (dops[i].itype != MULTDIV)
32631e6a 3541 return 0;
cf95b4f0 3542 if (dops[i].opcode2 == 0x18 || dops[i].opcode2 == 0x19) // MULT(U)
32631e6a 3543 *cycles = 11; // approx from 7 11 14
3544 else
3545 *cycles = 37;
3546 return 1;
3547}
3548
2330734f 3549static void multdiv_prepare_stall(int i, const struct regstat *i_regs, int ccadj_)
32631e6a 3550{
3551 int j, found = 0, c = 0;
3552 if (HACK_ENABLED(NDHACK_NO_STALLS))
3553 return;
3554 if (get_reg(i_regs->regmap, CCREG) != HOST_CCREG) {
3555 // happens occasionally... cc evicted? Don't bother then
3556 return;
3557 }
3558 for (j = i + 1; j < slen; j++) {
cf95b4f0 3559 if (dops[j].bt)
32631e6a 3560 break;
3561 if ((found = is_mflohi(j)))
3562 break;
fe807a8a 3563 if (dops[j].is_jump) {
32631e6a 3564 // check ds
3565 if (j + 1 < slen && (found = is_mflohi(j + 1)))
3566 j++;
3567 break;
3568 }
3569 }
3570 if (found)
3571 // handle all in multdiv_do_stall()
3572 return;
3573 check_multdiv(i, &c);
3574 assert(c > 0);
3575 assem_debug("; muldiv prepare stall %d\n", c);
3576 host_tempreg_acquire();
2330734f 3577 emit_addimm(HOST_CCREG, ccadj_ + c, HOST_TEMPREG);
32631e6a 3578 emit_writeword(HOST_TEMPREG, &psxRegs.muldivBusyCycle);
3579 host_tempreg_release();
3580}
3581
3582static void multdiv_do_stall(int i, const struct regstat *i_regs)
3583{
3584 int j, known_cycles = 0;
3585 u_int reglist = get_host_reglist(i_regs->regmap);
3586 int rtmp = get_reg(i_regs->regmap, -1);
3587 if (rtmp < 0)
3588 rtmp = reglist_find_free(reglist);
3589 if (HACK_ENABLED(NDHACK_NO_STALLS))
3590 return;
3591 if (get_reg(i_regs->regmap, CCREG) != HOST_CCREG || rtmp < 0) {
3592 // happens occasionally... cc evicted? Don't bother then
3593 //printf("no cc/rtmp %08x\n", start + i*4);
3594 return;
3595 }
cf95b4f0 3596 if (!dops[i].bt) {
32631e6a 3597 for (j = i - 1; j >= 0; j--) {
cf95b4f0 3598 if (dops[j].is_ds) break;
2330734f 3599 if (check_multdiv(j, &known_cycles))
32631e6a 3600 break;
3601 if (is_mflohi(j))
3602 // already handled by this op
3603 return;
2330734f 3604 if (dops[j].bt || (j > 0 && ccadj[j - 1] > ccadj[j]))
3605 break;
32631e6a 3606 }
3607 j = max(j, 0);
3608 }
3609 if (known_cycles > 0) {
2330734f 3610 known_cycles -= ccadj[i] - ccadj[j];
32631e6a 3611 assem_debug("; muldiv stall resolved %d\n", known_cycles);
3612 if (known_cycles > 0)
3613 emit_addimm(HOST_CCREG, known_cycles, HOST_CCREG);
3614 return;
3615 }
3616 assem_debug("; muldiv stall unresolved\n");
3617 host_tempreg_acquire();
3618 emit_readword(&psxRegs.muldivBusyCycle, rtmp);
2330734f 3619 emit_addimm(rtmp, -ccadj[i], rtmp);
32631e6a 3620 emit_sub(rtmp, HOST_CCREG, HOST_TEMPREG);
3621 emit_cmpimm(HOST_TEMPREG, 37);
3622 emit_cmovb_reg(rtmp, HOST_CCREG);
3623 //emit_log_gte_stall(i, 0, reglist);
3624 host_tempreg_release();
3625}
3626
8062d65a 3627static void cop2_get_dreg(u_int copr,signed char tl,signed char temp)
3628{
3629 switch (copr) {
3630 case 1:
3631 case 3:
3632 case 5:
3633 case 8:
3634 case 9:
3635 case 10:
3636 case 11:
3637 emit_readword(&reg_cop2d[copr],tl);
3638 emit_signextend16(tl,tl);
3639 emit_writeword(tl,&reg_cop2d[copr]); // hmh
3640 break;
3641 case 7:
3642 case 16:
3643 case 17:
3644 case 18:
3645 case 19:
3646 emit_readword(&reg_cop2d[copr],tl);
3647 emit_andimm(tl,0xffff,tl);
3648 emit_writeword(tl,&reg_cop2d[copr]);
3649 break;
3650 case 15:
3651 emit_readword(&reg_cop2d[14],tl); // SXY2
3652 emit_writeword(tl,&reg_cop2d[copr]);
3653 break;
3654 case 28:
3655 case 29:
3968e69e 3656 c2op_mfc2_29_assemble(tl,temp);
8062d65a 3657 break;
3658 default:
3659 emit_readword(&reg_cop2d[copr],tl);
3660 break;
3661 }
3662}
3663
3664static void cop2_put_dreg(u_int copr,signed char sl,signed char temp)
3665{
3666 switch (copr) {
3667 case 15:
3668 emit_readword(&reg_cop2d[13],temp); // SXY1
3669 emit_writeword(sl,&reg_cop2d[copr]);
3670 emit_writeword(temp,&reg_cop2d[12]); // SXY0
3671 emit_readword(&reg_cop2d[14],temp); // SXY2
3672 emit_writeword(sl,&reg_cop2d[14]);
3673 emit_writeword(temp,&reg_cop2d[13]); // SXY1
3674 break;
3675 case 28:
3676 emit_andimm(sl,0x001f,temp);
3677 emit_shlimm(temp,7,temp);
3678 emit_writeword(temp,&reg_cop2d[9]);
3679 emit_andimm(sl,0x03e0,temp);
3680 emit_shlimm(temp,2,temp);
3681 emit_writeword(temp,&reg_cop2d[10]);
3682 emit_andimm(sl,0x7c00,temp);
3683 emit_shrimm(temp,3,temp);
3684 emit_writeword(temp,&reg_cop2d[11]);
3685 emit_writeword(sl,&reg_cop2d[28]);
3686 break;
3687 case 30:
3968e69e 3688 emit_xorsar_imm(sl,sl,31,temp);
be516ebe 3689#if defined(HAVE_ARMV5) || defined(__aarch64__)
8062d65a 3690 emit_clz(temp,temp);
3691#else
3692 emit_movs(temp,HOST_TEMPREG);
3693 emit_movimm(0,temp);
3694 emit_jeq((int)out+4*4);
3695 emit_addpl_imm(temp,1,temp);
3696 emit_lslpls_imm(HOST_TEMPREG,1,HOST_TEMPREG);
3697 emit_jns((int)out-2*4);
3698#endif
3699 emit_writeword(sl,&reg_cop2d[30]);
3700 emit_writeword(temp,&reg_cop2d[31]);
3701 break;
3702 case 31:
3703 break;
3704 default:
3705 emit_writeword(sl,&reg_cop2d[copr]);
3706 break;
3707 }
3708}
3709
2330734f 3710static void c2ls_assemble(int i, const struct regstat *i_regs, int ccadj_)
b9b61529 3711{
3712 int s,tl;
3713 int ar;
3714 int offset;
1fd1aceb 3715 int memtarget=0,c=0;
b14b6a8f 3716 void *jaddr2=NULL;
3717 enum stub_type type;
b9b61529 3718 int agr=AGEN1+(i&1);
37387d8b 3719 int offset_reg = -1;
3720 int fastio_reg_override = -1;
81dbbf4c 3721 u_int reglist=get_host_reglist(i_regs->regmap);
b9b61529 3722 u_int copr=(source[i]>>16)&0x1f;
cf95b4f0 3723 s=get_reg(i_regs->regmap,dops[i].rs1);
b9b61529 3724 tl=get_reg(i_regs->regmap,FTEMP);
3725 offset=imm[i];
cf95b4f0 3726 assert(dops[i].rs1>0);
b9b61529 3727 assert(tl>=0);
b9b61529 3728
b9b61529 3729 if(i_regs->regmap[HOST_CCREG]==CCREG)
3730 reglist&=~(1<<HOST_CCREG);
3731
3732 // get the address
cf95b4f0 3733 if (dops[i].opcode==0x3a) { // SWC2
b9b61529 3734 ar=get_reg(i_regs->regmap,agr);
3735 if(ar<0) ar=get_reg(i_regs->regmap,-1);
3736 reglist|=1<<ar;
3737 } else { // LWC2
3738 ar=tl;
3739 }
1fd1aceb 3740 if(s>=0) c=(i_regs->wasconst>>s)&1;
3741 memtarget=c&&(((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE);
b9b61529 3742 if (!offset&&!c&&s>=0) ar=s;
3743 assert(ar>=0);
3744
32631e6a 3745 cop2_do_stall_check(0, i, i_regs, reglist);
3746
cf95b4f0 3747 if (dops[i].opcode==0x3a) { // SWC2
3968e69e 3748 cop2_get_dreg(copr,tl,-1);
1fd1aceb 3749 type=STOREW_STUB;
b9b61529 3750 }
1fd1aceb 3751 else
b9b61529 3752 type=LOADW_STUB;
1fd1aceb 3753
3754 if(c&&!memtarget) {
b14b6a8f 3755 jaddr2=out;
1fd1aceb 3756 emit_jmp(0); // inline_readstub/inline_writestub?
b9b61529 3757 }
1fd1aceb 3758 else {
3759 if(!c) {
37387d8b 3760 jaddr2 = emit_fastpath_cmp_jump(i, i_regs, ar,
3761 &offset_reg, &fastio_reg_override);
3762 }
3763 else if (ram_offset && memtarget) {
3764 offset_reg = get_ro_reg(i_regs, 0);
3765 }
3766 switch (dops[i].opcode) {
3767 case 0x32: { // LWC2
3768 int a = ar;
3769 if (fastio_reg_override >= 0)
3770 a = fastio_reg_override;
3771 do_load_word(a, tl, offset_reg);
3772 break;
1fd1aceb 3773 }
37387d8b 3774 case 0x3a: { // SWC2
1fd1aceb 3775 #ifdef DESTRUCTIVE_SHIFT
3776 if(!offset&&!c&&s>=0) emit_mov(s,ar);
3777 #endif
37387d8b 3778 int a = ar;
3779 if (fastio_reg_override >= 0)
3780 a = fastio_reg_override;
3781 do_store_word(a, 0, tl, offset_reg, 1);
3782 break;
3783 }
3784 default:
3785 assert(0);
1fd1aceb 3786 }
b9b61529 3787 }
37387d8b 3788 if (fastio_reg_override == HOST_TEMPREG || offset_reg == HOST_TEMPREG)
d1e4ebd9 3789 host_tempreg_release();
b9b61529 3790 if(jaddr2)
2330734f 3791 add_stub_r(type,jaddr2,out,i,ar,i_regs,ccadj_,reglist);
cf95b4f0 3792 if(dops[i].opcode==0x3a) // SWC2
3793 if(!(i_regs->waswritten&(1<<dops[i].rs1)) && !HACK_ENABLED(NDHACK_NO_SMC_CHECK)) {
b9b61529 3794#if defined(HOST_IMM8)
3795 int ir=get_reg(i_regs->regmap,INVCP);
3796 assert(ir>=0);
3797 emit_cmpmem_indexedsr12_reg(ir,ar,1);
3798#else
643aeae3 3799 emit_cmpmem_indexedsr12_imm(invalid_code,ar,1);
b9b61529 3800#endif
0bbd1454 3801 #if defined(HAVE_CONDITIONAL_CALL) && !defined(DESTRUCTIVE_SHIFT)
3802 emit_callne(invalidate_addr_reg[ar]);
3803 #else
b14b6a8f 3804 void *jaddr3 = out;
b9b61529 3805 emit_jne(0);
b14b6a8f 3806 add_stub(INVCODE_STUB,jaddr3,out,reglist|(1<<HOST_CCREG),ar,0,0,0);
0bbd1454 3807 #endif
b9b61529 3808 }
cf95b4f0 3809 if (dops[i].opcode==0x32) { // LWC2
d1e4ebd9 3810 host_tempreg_acquire();
b9b61529 3811 cop2_put_dreg(copr,tl,HOST_TEMPREG);
d1e4ebd9 3812 host_tempreg_release();
b9b61529 3813 }
3814}
3815
81dbbf4c 3816static void cop2_assemble(int i, const struct regstat *i_regs)
8062d65a 3817{
81dbbf4c 3818 u_int copr = (source[i]>>11) & 0x1f;
3819 signed char temp = get_reg(i_regs->regmap, -1);
3820
32631e6a 3821 if (!HACK_ENABLED(NDHACK_NO_STALLS)) {
3822 u_int reglist = reglist_exclude(get_host_reglist(i_regs->regmap), temp, -1);
cf95b4f0 3823 if (dops[i].opcode2 == 0 || dops[i].opcode2 == 2) { // MFC2/CFC2
3824 signed char tl = get_reg(i_regs->regmap, dops[i].rt1);
32631e6a 3825 reglist = reglist_exclude(reglist, tl, -1);
81dbbf4c 3826 }
32631e6a 3827 cop2_do_stall_check(0, i, i_regs, reglist);
81dbbf4c 3828 }
cf95b4f0 3829 if (dops[i].opcode2==0) { // MFC2
3830 signed char tl=get_reg(i_regs->regmap,dops[i].rt1);
3831 if(tl>=0&&dops[i].rt1!=0)
8062d65a 3832 cop2_get_dreg(copr,tl,temp);
3833 }
cf95b4f0 3834 else if (dops[i].opcode2==4) { // MTC2
3835 signed char sl=get_reg(i_regs->regmap,dops[i].rs1);
8062d65a 3836 cop2_put_dreg(copr,sl,temp);
3837 }
cf95b4f0 3838 else if (dops[i].opcode2==2) // CFC2
8062d65a 3839 {
cf95b4f0 3840 signed char tl=get_reg(i_regs->regmap,dops[i].rt1);
3841 if(tl>=0&&dops[i].rt1!=0)
8062d65a 3842 emit_readword(&reg_cop2c[copr],tl);
3843 }
cf95b4f0 3844 else if (dops[i].opcode2==6) // CTC2
8062d65a 3845 {
cf95b4f0 3846 signed char sl=get_reg(i_regs->regmap,dops[i].rs1);
8062d65a 3847 switch(copr) {
3848 case 4:
3849 case 12:
3850 case 20:
3851 case 26:
3852 case 27:
3853 case 29:
3854 case 30:
3855 emit_signextend16(sl,temp);
3856 break;
3857 case 31:
3968e69e 3858 c2op_ctc2_31_assemble(sl,temp);
8062d65a 3859 break;
3860 default:
3861 temp=sl;
3862 break;
3863 }
3864 emit_writeword(temp,&reg_cop2c[copr]);
3865 assert(sl>=0);
3866 }
3867}
3868
3968e69e 3869static void do_unalignedwritestub(int n)
3870{
3871 assem_debug("do_unalignedwritestub %x\n",start+stubs[n].a*4);
3872 literal_pool(256);
3873 set_jump_target(stubs[n].addr, out);
3874
3875 int i=stubs[n].a;
3876 struct regstat *i_regs=(struct regstat *)stubs[n].c;
3877 int addr=stubs[n].b;
3878 u_int reglist=stubs[n].e;
3879 signed char *i_regmap=i_regs->regmap;
3880 int temp2=get_reg(i_regmap,FTEMP);
3881 int rt;
cf95b4f0 3882 rt=get_reg(i_regmap,dops[i].rs2);
3968e69e 3883 assert(rt>=0);
3884 assert(addr>=0);
cf95b4f0 3885 assert(dops[i].opcode==0x2a||dops[i].opcode==0x2e); // SWL/SWR only implemented
3968e69e 3886 reglist|=(1<<addr);
3887 reglist&=~(1<<temp2);
3888
3968e69e 3889 // don't bother with it and call write handler
3890 save_regs(reglist);
3891 pass_args(addr,rt);
3892 int cc=get_reg(i_regmap,CCREG);
3893 if(cc<0)
3894 emit_loadreg(CCREG,2);
2330734f 3895 emit_addimm(cc<0?2:cc,(int)stubs[n].d+1,2);
cf95b4f0 3896 emit_far_call((dops[i].opcode==0x2a?jump_handle_swl:jump_handle_swr));
2330734f 3897 emit_addimm(0,-((int)stubs[n].d+1),cc<0?2:cc);
3968e69e 3898 if(cc<0)
3899 emit_storereg(CCREG,2);
3900 restore_regs(reglist);
3901 emit_jmp(stubs[n].retaddr); // return address
3968e69e 3902}
3903
57871462 3904#ifndef multdiv_assemble
3905void multdiv_assemble(int i,struct regstat *i_regs)
3906{
3907 printf("Need multdiv_assemble for this architecture.\n");
7c3a5182 3908 abort();
57871462 3909}
3910#endif
3911
2330734f 3912static void mov_assemble(int i, const struct regstat *i_regs)
57871462 3913{
cf95b4f0 3914 //if(dops[i].opcode2==0x10||dops[i].opcode2==0x12) { // MFHI/MFLO
3915 //if(dops[i].opcode2==0x11||dops[i].opcode2==0x13) { // MTHI/MTLO
3916 if(dops[i].rt1) {
7c3a5182 3917 signed char sl,tl;
cf95b4f0 3918 tl=get_reg(i_regs->regmap,dops[i].rt1);
57871462 3919 //assert(tl>=0);
3920 if(tl>=0) {
cf95b4f0 3921 sl=get_reg(i_regs->regmap,dops[i].rs1);
57871462 3922 if(sl>=0) emit_mov(sl,tl);
cf95b4f0 3923 else emit_loadreg(dops[i].rs1,tl);
57871462 3924 }
3925 }
cf95b4f0 3926 if (dops[i].rs1 == HIREG || dops[i].rs1 == LOREG) // MFHI/MFLO
32631e6a 3927 multdiv_do_stall(i, i_regs);
57871462 3928}
3929
3968e69e 3930// call interpreter, exception handler, things that change pc/regs/cycles ...
2330734f 3931static void call_c_cpu_handler(int i, const struct regstat *i_regs, int ccadj_, u_int pc, void *func)
57871462 3932{
3933 signed char ccreg=get_reg(i_regs->regmap,CCREG);
3934 assert(ccreg==HOST_CCREG);
3935 assert(!is_delayslot);
581335b0 3936 (void)ccreg;
3968e69e 3937
3938 emit_movimm(pc,3); // Get PC
3939 emit_readword(&last_count,2);
3940 emit_writeword(3,&psxRegs.pc);
2330734f 3941 emit_addimm(HOST_CCREG,ccadj_,HOST_CCREG);
3968e69e 3942 emit_add(2,HOST_CCREG,2);
3943 emit_writeword(2,&psxRegs.cycle);
2a014d73 3944 emit_far_call(func);
3945 emit_far_jump(jump_to_new_pc);
3968e69e 3946}
3947
2330734f 3948static void syscall_assemble(int i, const struct regstat *i_regs, int ccadj_)
3968e69e 3949{
d1150cd6 3950 // 'break' tends to be littered around to catch things like
3951 // division by 0 and is almost never executed, so don't emit much code here
3952 void *func = (dops[i].opcode2 == 0x0C)
3953 ? (is_delayslot ? jump_syscall_ds : jump_syscall)
3954 : (is_delayslot ? jump_break_ds : jump_break);
3955 signed char ccreg = get_reg(i_regs->regmap, CCREG);
3956 assert(ccreg == HOST_CCREG);
3957 emit_movimm(start + i*4, 2); // pc
3958 emit_addimm(HOST_CCREG, ccadj_ + CLOCK_ADJUST(1), HOST_CCREG);
3959 emit_far_jump(func);
7139f3c8 3960}
3961
2330734f 3962static void hlecall_assemble(int i, const struct regstat *i_regs, int ccadj_)
7139f3c8 3963{
3968e69e 3964 void *hlefunc = psxNULL;
dd79da89 3965 uint32_t hleCode = source[i] & 0x03ffffff;
3968e69e 3966 if (hleCode < ARRAY_SIZE(psxHLEt))
3967 hlefunc = psxHLEt[hleCode];
3968
2330734f 3969 call_c_cpu_handler(i, i_regs, ccadj_, start + i*4+4, hlefunc);
57871462 3970}
3971
2330734f 3972static void intcall_assemble(int i, const struct regstat *i_regs, int ccadj_)
1e973cb0 3973{
2330734f 3974 call_c_cpu_handler(i, i_regs, ccadj_, start + i*4, execI);
1e973cb0 3975}
3976
8062d65a 3977static void speculate_mov(int rs,int rt)
3978{
3979 if(rt!=0) {
3980 smrv_strong_next|=1<<rt;
3981 smrv[rt]=smrv[rs];
3982 }
3983}
3984
3985static void speculate_mov_weak(int rs,int rt)
3986{
3987 if(rt!=0) {
3988 smrv_weak_next|=1<<rt;
3989 smrv[rt]=smrv[rs];
3990 }
3991}
3992
3993static void speculate_register_values(int i)
3994{
3995 if(i==0) {
3996 memcpy(smrv,psxRegs.GPR.r,sizeof(smrv));
3997 // gp,sp are likely to stay the same throughout the block
3998 smrv_strong_next=(1<<28)|(1<<29)|(1<<30);
3999 smrv_weak_next=~smrv_strong_next;
4000 //printf(" llr %08x\n", smrv[4]);
4001 }
4002 smrv_strong=smrv_strong_next;
4003 smrv_weak=smrv_weak_next;
cf95b4f0 4004 switch(dops[i].itype) {
8062d65a 4005 case ALU:
cf95b4f0 4006 if ((smrv_strong>>dops[i].rs1)&1) speculate_mov(dops[i].rs1,dops[i].rt1);
4007 else if((smrv_strong>>dops[i].rs2)&1) speculate_mov(dops[i].rs2,dops[i].rt1);
4008 else if((smrv_weak>>dops[i].rs1)&1) speculate_mov_weak(dops[i].rs1,dops[i].rt1);
4009 else if((smrv_weak>>dops[i].rs2)&1) speculate_mov_weak(dops[i].rs2,dops[i].rt1);
8062d65a 4010 else {
cf95b4f0 4011 smrv_strong_next&=~(1<<dops[i].rt1);
4012 smrv_weak_next&=~(1<<dops[i].rt1);
8062d65a 4013 }
4014 break;
4015 case SHIFTIMM:
cf95b4f0 4016 smrv_strong_next&=~(1<<dops[i].rt1);
4017 smrv_weak_next&=~(1<<dops[i].rt1);
8062d65a 4018 // fallthrough
4019 case IMM16:
cf95b4f0 4020 if(dops[i].rt1&&is_const(&regs[i],dops[i].rt1)) {
4021 int value,hr=get_reg(regs[i].regmap,dops[i].rt1);
8062d65a 4022 if(hr>=0) {
4023 if(get_final_value(hr,i,&value))
cf95b4f0 4024 smrv[dops[i].rt1]=value;
4025 else smrv[dops[i].rt1]=constmap[i][hr];
4026 smrv_strong_next|=1<<dops[i].rt1;
8062d65a 4027 }
4028 }
4029 else {
cf95b4f0 4030 if ((smrv_strong>>dops[i].rs1)&1) speculate_mov(dops[i].rs1,dops[i].rt1);
4031 else if((smrv_weak>>dops[i].rs1)&1) speculate_mov_weak(dops[i].rs1,dops[i].rt1);
8062d65a 4032 }
4033 break;
4034 case LOAD:
cf95b4f0 4035 if(start<0x2000&&(dops[i].rt1==26||(smrv[dops[i].rt1]>>24)==0xa0)) {
8062d65a 4036 // special case for BIOS
cf95b4f0 4037 smrv[dops[i].rt1]=0xa0000000;
4038 smrv_strong_next|=1<<dops[i].rt1;
8062d65a 4039 break;
4040 }
4041 // fallthrough
4042 case SHIFT:
4043 case LOADLR:
4044 case MOV:
cf95b4f0 4045 smrv_strong_next&=~(1<<dops[i].rt1);
4046 smrv_weak_next&=~(1<<dops[i].rt1);
8062d65a 4047 break;
4048 case COP0:
4049 case COP2:
cf95b4f0 4050 if(dops[i].opcode2==0||dops[i].opcode2==2) { // MFC/CFC
4051 smrv_strong_next&=~(1<<dops[i].rt1);
4052 smrv_weak_next&=~(1<<dops[i].rt1);
8062d65a 4053 }
4054 break;
4055 case C2LS:
cf95b4f0 4056 if (dops[i].opcode==0x32) { // LWC2
4057 smrv_strong_next&=~(1<<dops[i].rt1);
4058 smrv_weak_next&=~(1<<dops[i].rt1);
8062d65a 4059 }
4060 break;
4061 }
4062#if 0
4063 int r=4;
4064 printf("x %08x %08x %d %d c %08x %08x\n",smrv[r],start+i*4,
4065 ((smrv_strong>>r)&1),(smrv_weak>>r)&1,regs[i].isconst,regs[i].wasconst);
4066#endif
4067}
4068
2330734f 4069static void ujump_assemble(int i, const struct regstat *i_regs);
4070static void rjump_assemble(int i, const struct regstat *i_regs);
4071static void cjump_assemble(int i, const struct regstat *i_regs);
4072static void sjump_assemble(int i, const struct regstat *i_regs);
4073static void pagespan_assemble(int i, const struct regstat *i_regs);
4074
4075static int assemble(int i, const struct regstat *i_regs, int ccadj_)
57871462 4076{
2330734f 4077 int ds = 0;
4078 switch (dops[i].itype) {
57871462 4079 case ALU:
2330734f 4080 alu_assemble(i, i_regs);
4081 break;
57871462 4082 case IMM16:
2330734f 4083 imm16_assemble(i, i_regs);
4084 break;
57871462 4085 case SHIFT:
2330734f 4086 shift_assemble(i, i_regs);
4087 break;
57871462 4088 case SHIFTIMM:
2330734f 4089 shiftimm_assemble(i, i_regs);
4090 break;
57871462 4091 case LOAD:
2330734f 4092 load_assemble(i, i_regs, ccadj_);
4093 break;
57871462 4094 case LOADLR:
2330734f 4095 loadlr_assemble(i, i_regs, ccadj_);
4096 break;
57871462 4097 case STORE:
2330734f 4098 store_assemble(i, i_regs, ccadj_);
4099 break;
57871462 4100 case STORELR:
2330734f 4101 storelr_assemble(i, i_regs, ccadj_);
4102 break;
57871462 4103 case COP0:
2330734f 4104 cop0_assemble(i, i_regs, ccadj_);
4105 break;
57871462 4106 case COP1:
2330734f 4107 cop1_assemble(i, i_regs);
4108 break;
57871462 4109 case C1LS:
2330734f 4110 c1ls_assemble(i, i_regs);
4111 break;
b9b61529 4112 case COP2:
2330734f 4113 cop2_assemble(i, i_regs);
4114 break;
b9b61529 4115 case C2LS:
2330734f 4116 c2ls_assemble(i, i_regs, ccadj_);
4117 break;
b9b61529 4118 case C2OP:
2330734f 4119 c2op_assemble(i, i_regs);
4120 break;
57871462 4121 case MULTDIV:
2330734f 4122 multdiv_assemble(i, i_regs);
4123 multdiv_prepare_stall(i, i_regs, ccadj_);
32631e6a 4124 break;
57871462 4125 case MOV:
2330734f 4126 mov_assemble(i, i_regs);
4127 break;
4128 case SYSCALL:
4129 syscall_assemble(i, i_regs, ccadj_);
4130 break;
4131 case HLECALL:
4132 hlecall_assemble(i, i_regs, ccadj_);
4133 break;
4134 case INTCALL:
4135 intcall_assemble(i, i_regs, ccadj_);
4136 break;
4137 case UJUMP:
4138 ujump_assemble(i, i_regs);
4139 ds = 1;
4140 break;
4141 case RJUMP:
4142 rjump_assemble(i, i_regs);
4143 ds = 1;
4144 break;
4145 case CJUMP:
4146 cjump_assemble(i, i_regs);
4147 ds = 1;
4148 break;
4149 case SJUMP:
4150 sjump_assemble(i, i_regs);
4151 ds = 1;
4152 break;
4153 case SPAN:
4154 pagespan_assemble(i, i_regs);
4155 break;
24058131 4156 case NOP:
2330734f 4157 case OTHER:
4158 case NI:
4159 // not handled, just skip
4160 break;
4161 default:
4162 assert(0);
4163 }
4164 return ds;
4165}
4166
4167static void ds_assemble(int i, const struct regstat *i_regs)
4168{
4169 speculate_register_values(i);
4170 is_delayslot = 1;
4171 switch (dops[i].itype) {
57871462 4172 case SYSCALL:
7139f3c8 4173 case HLECALL:
1e973cb0 4174 case INTCALL:
57871462 4175 case SPAN:
4176 case UJUMP:
4177 case RJUMP:
4178 case CJUMP:
4179 case SJUMP:
c43b5311 4180 SysPrintf("Jump in the delay slot. This is probably a bug.\n");
2330734f 4181 break;
4182 default:
4183 assemble(i, i_regs, ccadj[i]);
57871462 4184 }
2330734f 4185 is_delayslot = 0;
57871462 4186}
4187
4188// Is the branch target a valid internal jump?
ad49de89 4189static int internal_branch(int addr)
57871462 4190{
4191 if(addr&1) return 0; // Indirect (register) jump
4192 if(addr>=start && addr<start+slen*4-4)
4193 {
71e490c5 4194 return 1;
57871462 4195 }
4196 return 0;
4197}
4198
ad49de89 4199static void wb_invalidate(signed char pre[],signed char entry[],uint64_t dirty,uint64_t u)
57871462 4200{
4201 int hr;
4202 for(hr=0;hr<HOST_REGS;hr++) {
4203 if(hr!=EXCLUDE_REG) {
4204 if(pre[hr]!=entry[hr]) {
4205 if(pre[hr]>=0) {
4206 if((dirty>>hr)&1) {
4207 if(get_reg(entry,pre[hr])<0) {
00fa9369 4208 assert(pre[hr]<64);
4209 if(!((u>>pre[hr])&1))
4210 emit_storereg(pre[hr],hr);
57871462 4211 }
4212 }
4213 }
4214 }
4215 }
4216 }
4217 // Move from one register to another (no writeback)
4218 for(hr=0;hr<HOST_REGS;hr++) {
4219 if(hr!=EXCLUDE_REG) {
4220 if(pre[hr]!=entry[hr]) {
4221 if(pre[hr]>=0&&(pre[hr]&63)<TEMPREG) {
4222 int nr;
4223 if((nr=get_reg(entry,pre[hr]))>=0) {
4224 emit_mov(hr,nr);
4225 }
4226 }
4227 }
4228 }
4229 }
4230}
57871462 4231
4232// Load the specified registers
4233// This only loads the registers given as arguments because
4234// we don't want to load things that will be overwritten
ad49de89 4235static void load_regs(signed char entry[],signed char regmap[],int rs1,int rs2)
57871462 4236{
4237 int hr;
4238 // Load 32-bit regs
4239 for(hr=0;hr<HOST_REGS;hr++) {
4240 if(hr!=EXCLUDE_REG&&regmap[hr]>=0) {
4241 if(entry[hr]!=regmap[hr]) {
4242 if(regmap[hr]==rs1||regmap[hr]==rs2)
4243 {
4244 if(regmap[hr]==0) {
4245 emit_zeroreg(hr);
4246 }
4247 else
4248 {
4249 emit_loadreg(regmap[hr],hr);
4250 }
4251 }
4252 }
4253 }
4254 }
57871462 4255}
4256
4257// Load registers prior to the start of a loop
4258// so that they are not loaded within the loop
4259static void loop_preload(signed char pre[],signed char entry[])
4260{
4261 int hr;
4262 for(hr=0;hr<HOST_REGS;hr++) {
4263 if(hr!=EXCLUDE_REG) {
4264 if(pre[hr]!=entry[hr]) {
4265 if(entry[hr]>=0) {
4266 if(get_reg(pre,entry[hr])<0) {
4267 assem_debug("loop preload:\n");
4268 //printf("loop preload: %d\n",hr);
4269 if(entry[hr]==0) {
4270 emit_zeroreg(hr);
4271 }
4272 else if(entry[hr]<TEMPREG)
4273 {
4274 emit_loadreg(entry[hr],hr);
4275 }
4276 else if(entry[hr]-64<TEMPREG)
4277 {
4278 emit_loadreg(entry[hr],hr);
4279 }
4280 }
4281 }
4282 }
4283 }
4284 }
4285}
4286
4287// Generate address for load/store instruction
b9b61529 4288// goes to AGEN for writes, FTEMP for LOADLR and cop1/2 loads
2330734f 4289void address_generation(int i, const struct regstat *i_regs, signed char entry[])
57871462 4290{
37387d8b 4291 if (dops[i].is_load || dops[i].is_store) {
5194fb95 4292 int ra=-1;
57871462 4293 int agr=AGEN1+(i&1);
cf95b4f0 4294 if(dops[i].itype==LOAD) {
4295 ra=get_reg(i_regs->regmap,dops[i].rt1);
9f51b4b9 4296 if(ra<0) ra=get_reg(i_regs->regmap,-1);
535d208a 4297 assert(ra>=0);
57871462 4298 }
cf95b4f0 4299 if(dops[i].itype==LOADLR) {
57871462 4300 ra=get_reg(i_regs->regmap,FTEMP);
4301 }
cf95b4f0 4302 if(dops[i].itype==STORE||dops[i].itype==STORELR) {
57871462 4303 ra=get_reg(i_regs->regmap,agr);
4304 if(ra<0) ra=get_reg(i_regs->regmap,-1);
4305 }
37387d8b 4306 if(dops[i].itype==C2LS) {
cf95b4f0 4307 if ((dops[i].opcode&0x3b)==0x31||(dops[i].opcode&0x3b)==0x32) // LWC1/LDC1/LWC2/LDC2
57871462 4308 ra=get_reg(i_regs->regmap,FTEMP);
1fd1aceb 4309 else { // SWC1/SDC1/SWC2/SDC2
57871462 4310 ra=get_reg(i_regs->regmap,agr);
4311 if(ra<0) ra=get_reg(i_regs->regmap,-1);
4312 }
4313 }
cf95b4f0 4314 int rs=get_reg(i_regs->regmap,dops[i].rs1);
57871462 4315 if(ra>=0) {
4316 int offset=imm[i];
4317 int c=(i_regs->wasconst>>rs)&1;
cf95b4f0 4318 if(dops[i].rs1==0) {
57871462 4319 // Using r0 as a base address
57871462 4320 if(!entry||entry[ra]!=agr) {
cf95b4f0 4321 if (dops[i].opcode==0x22||dops[i].opcode==0x26) {
57871462 4322 emit_movimm(offset&0xFFFFFFFC,ra); // LWL/LWR
cf95b4f0 4323 }else if (dops[i].opcode==0x1a||dops[i].opcode==0x1b) {
57871462 4324 emit_movimm(offset&0xFFFFFFF8,ra); // LDL/LDR
4325 }else{
4326 emit_movimm(offset,ra);
4327 }
4328 } // else did it in the previous cycle
4329 }
4330 else if(rs<0) {
cf95b4f0 4331 if(!entry||entry[ra]!=dops[i].rs1)
4332 emit_loadreg(dops[i].rs1,ra);
4333 //if(!entry||entry[ra]!=dops[i].rs1)
57871462 4334 // printf("poor load scheduling!\n");
4335 }
4336 else if(c) {
cf95b4f0 4337 if(dops[i].rs1!=dops[i].rt1||dops[i].itype!=LOAD) {
57871462 4338 if(!entry||entry[ra]!=agr) {
cf95b4f0 4339 if (dops[i].opcode==0x22||dops[i].opcode==0x26) {
57871462 4340 emit_movimm((constmap[i][rs]+offset)&0xFFFFFFFC,ra); // LWL/LWR
cf95b4f0 4341 }else if (dops[i].opcode==0x1a||dops[i].opcode==0x1b) {
57871462 4342 emit_movimm((constmap[i][rs]+offset)&0xFFFFFFF8,ra); // LDL/LDR
4343 }else{
57871462 4344 emit_movimm(constmap[i][rs]+offset,ra);
8575a877 4345 regs[i].loadedconst|=1<<ra;
57871462 4346 }
4347 } // else did it in the previous cycle
4348 } // else load_consts already did it
4349 }
cf95b4f0 4350 if(offset&&!c&&dops[i].rs1) {
57871462 4351 if(rs>=0) {
4352 emit_addimm(rs,offset,ra);
4353 }else{
4354 emit_addimm(ra,offset,ra);
4355 }
4356 }
4357 }
4358 }
4359 // Preload constants for next instruction
37387d8b 4360 if (dops[i+1].is_load || dops[i+1].is_store) {
57871462 4361 int agr,ra;
57871462 4362 // Actual address
4363 agr=AGEN1+((i+1)&1);
4364 ra=get_reg(i_regs->regmap,agr);
4365 if(ra>=0) {
cf95b4f0 4366 int rs=get_reg(regs[i+1].regmap,dops[i+1].rs1);
57871462 4367 int offset=imm[i+1];
4368 int c=(regs[i+1].wasconst>>rs)&1;
cf95b4f0 4369 if(c&&(dops[i+1].rs1!=dops[i+1].rt1||dops[i+1].itype!=LOAD)) {
4370 if (dops[i+1].opcode==0x22||dops[i+1].opcode==0x26) {
57871462 4371 emit_movimm((constmap[i+1][rs]+offset)&0xFFFFFFFC,ra); // LWL/LWR
cf95b4f0 4372 }else if (dops[i+1].opcode==0x1a||dops[i+1].opcode==0x1b) {
57871462 4373 emit_movimm((constmap[i+1][rs]+offset)&0xFFFFFFF8,ra); // LDL/LDR
4374 }else{
57871462 4375 emit_movimm(constmap[i+1][rs]+offset,ra);
8575a877 4376 regs[i+1].loadedconst|=1<<ra;
57871462 4377 }
4378 }
cf95b4f0 4379 else if(dops[i+1].rs1==0) {
57871462 4380 // Using r0 as a base address
cf95b4f0 4381 if (dops[i+1].opcode==0x22||dops[i+1].opcode==0x26) {
57871462 4382 emit_movimm(offset&0xFFFFFFFC,ra); // LWL/LWR
cf95b4f0 4383 }else if (dops[i+1].opcode==0x1a||dops[i+1].opcode==0x1b) {
57871462 4384 emit_movimm(offset&0xFFFFFFF8,ra); // LDL/LDR
4385 }else{
4386 emit_movimm(offset,ra);
4387 }
4388 }
4389 }
4390 }
4391}
4392
e2b5e7aa 4393static int get_final_value(int hr, int i, int *value)
57871462 4394{
4395 int reg=regs[i].regmap[hr];
4396 while(i<slen-1) {
4397 if(regs[i+1].regmap[hr]!=reg) break;
4398 if(!((regs[i+1].isconst>>hr)&1)) break;
cf95b4f0 4399 if(dops[i+1].bt) break;
57871462 4400 i++;
4401 }
4402 if(i<slen-1) {
fe807a8a 4403 if (dops[i].is_jump) {
57871462 4404 *value=constmap[i][hr];
4405 return 1;
4406 }
cf95b4f0 4407 if(!dops[i+1].bt) {
fe807a8a 4408 if (dops[i+1].is_jump) {
57871462 4409 // Load in delay slot, out-of-order execution
cf95b4f0 4410 if(dops[i+2].itype==LOAD&&dops[i+2].rs1==reg&&dops[i+2].rt1==reg&&((regs[i+1].wasconst>>hr)&1))
57871462 4411 {
57871462 4412 // Precompute load address
4413 *value=constmap[i][hr]+imm[i+2];
4414 return 1;
4415 }
4416 }
cf95b4f0 4417 if(dops[i+1].itype==LOAD&&dops[i+1].rs1==reg&&dops[i+1].rt1==reg)
57871462 4418 {
57871462 4419 // Precompute load address
4420 *value=constmap[i][hr]+imm[i+1];
643aeae3 4421 //printf("c=%x imm=%lx\n",(long)constmap[i][hr],imm[i+1]);
57871462 4422 return 1;
4423 }
4424 }
4425 }
4426 *value=constmap[i][hr];
643aeae3 4427 //printf("c=%lx\n",(long)constmap[i][hr]);
57871462 4428 if(i==slen-1) return 1;
00fa9369 4429 assert(reg < 64);
4430 return !((unneeded_reg[i+1]>>reg)&1);
57871462 4431}
4432
4433// Load registers with known constants
ad49de89 4434static void load_consts(signed char pre[],signed char regmap[],int i)
57871462 4435{
8575a877 4436 int hr,hr2;
4437 // propagate loaded constant flags
cf95b4f0 4438 if(i==0||dops[i].bt)
8575a877 4439 regs[i].loadedconst=0;
4440 else {
4441 for(hr=0;hr<HOST_REGS;hr++) {
4442 if(hr!=EXCLUDE_REG&&regmap[hr]>=0&&((regs[i-1].isconst>>hr)&1)&&pre[hr]==regmap[hr]
4443 &&regmap[hr]==regs[i-1].regmap[hr]&&((regs[i-1].loadedconst>>hr)&1))
4444 {
4445 regs[i].loadedconst|=1<<hr;
4446 }
4447 }
4448 }
57871462 4449 // Load 32-bit regs
4450 for(hr=0;hr<HOST_REGS;hr++) {
4451 if(hr!=EXCLUDE_REG&&regmap[hr]>=0) {
4452 //if(entry[hr]!=regmap[hr]) {
8575a877 4453 if(!((regs[i].loadedconst>>hr)&1)) {
ad49de89 4454 assert(regmap[hr]<64);
4455 if(((regs[i].isconst>>hr)&1)&&regmap[hr]>0) {
8575a877 4456 int value,similar=0;
57871462 4457 if(get_final_value(hr,i,&value)) {
8575a877 4458 // see if some other register has similar value
4459 for(hr2=0;hr2<HOST_REGS;hr2++) {
4460 if(hr2!=EXCLUDE_REG&&((regs[i].loadedconst>>hr2)&1)) {
4461 if(is_similar_value(value,constmap[i][hr2])) {
4462 similar=1;
4463 break;
4464 }
4465 }
4466 }
4467 if(similar) {
4468 int value2;
4469 if(get_final_value(hr2,i,&value2)) // is this needed?
4470 emit_movimm_from(value2,hr2,value,hr);
4471 else
4472 emit_movimm(value,hr);
4473 }
4474 else if(value==0) {
57871462 4475 emit_zeroreg(hr);
4476 }
4477 else {
4478 emit_movimm(value,hr);
4479 }
4480 }
8575a877 4481 regs[i].loadedconst|=1<<hr;
57871462 4482 }
4483 }
4484 }
4485 }
57871462 4486}
ad49de89 4487
2330734f 4488static void load_all_consts(const signed char regmap[], u_int dirty, int i)
57871462 4489{
4490 int hr;
4491 // Load 32-bit regs
4492 for(hr=0;hr<HOST_REGS;hr++) {
4493 if(hr!=EXCLUDE_REG&&regmap[hr]>=0&&((dirty>>hr)&1)) {
ad49de89 4494 assert(regmap[hr] < 64);
4495 if(((regs[i].isconst>>hr)&1)&&regmap[hr]>0) {
57871462 4496 int value=constmap[i][hr];
4497 if(value==0) {
4498 emit_zeroreg(hr);
4499 }
4500 else {
4501 emit_movimm(value,hr);
4502 }
4503 }
4504 }
4505 }
57871462 4506}
4507
4508// Write out all dirty registers (except cycle count)
2330734f 4509static void wb_dirtys(const signed char i_regmap[], uint64_t i_dirty)
57871462 4510{
4511 int hr;
4512 for(hr=0;hr<HOST_REGS;hr++) {
4513 if(hr!=EXCLUDE_REG) {
4514 if(i_regmap[hr]>0) {
4515 if(i_regmap[hr]!=CCREG) {
4516 if((i_dirty>>hr)&1) {
00fa9369 4517 assert(i_regmap[hr]<64);
4518 emit_storereg(i_regmap[hr],hr);
57871462 4519 }
4520 }
4521 }
4522 }
4523 }
4524}
ad49de89 4525
57871462 4526// Write out dirty registers that we need to reload (pair with load_needed_regs)
4527// This writes the registers not written by store_regs_bt
2330734f 4528static void wb_needed_dirtys(const signed char i_regmap[], uint64_t i_dirty, int addr)
57871462 4529{
4530 int hr;
4531 int t=(addr-start)>>2;
4532 for(hr=0;hr<HOST_REGS;hr++) {
4533 if(hr!=EXCLUDE_REG) {
4534 if(i_regmap[hr]>0) {
4535 if(i_regmap[hr]!=CCREG) {
ad49de89 4536 if(i_regmap[hr]==regs[t].regmap_entry[hr] && ((regs[t].dirty>>hr)&1)) {
57871462 4537 if((i_dirty>>hr)&1) {
00fa9369 4538 assert(i_regmap[hr]<64);
4539 emit_storereg(i_regmap[hr],hr);
57871462 4540 }
4541 }
4542 }
4543 }
4544 }
4545 }
4546}
4547
4548// Load all registers (except cycle count)
2330734f 4549static void load_all_regs(const signed char i_regmap[])
57871462 4550{
4551 int hr;
4552 for(hr=0;hr<HOST_REGS;hr++) {
4553 if(hr!=EXCLUDE_REG) {
4554 if(i_regmap[hr]==0) {
4555 emit_zeroreg(hr);
4556 }
4557 else
ea3d2e6e 4558 if(i_regmap[hr]>0 && (i_regmap[hr]&63)<TEMPREG && i_regmap[hr]!=CCREG)
57871462 4559 {
4560 emit_loadreg(i_regmap[hr],hr);
4561 }
4562 }
4563 }
4564}
4565
4566// Load all current registers also needed by next instruction
2330734f 4567static void load_needed_regs(const signed char i_regmap[], const signed char next_regmap[])
57871462 4568{
4569 int hr;
4570 for(hr=0;hr<HOST_REGS;hr++) {
4571 if(hr!=EXCLUDE_REG) {
4572 if(get_reg(next_regmap,i_regmap[hr])>=0) {
4573 if(i_regmap[hr]==0) {
4574 emit_zeroreg(hr);
4575 }
4576 else
ea3d2e6e 4577 if(i_regmap[hr]>0 && (i_regmap[hr]&63)<TEMPREG && i_regmap[hr]!=CCREG)
57871462 4578 {
4579 emit_loadreg(i_regmap[hr],hr);
4580 }
4581 }
4582 }
4583 }
4584}
4585
4586// Load all regs, storing cycle count if necessary
2330734f 4587static void load_regs_entry(int t)
57871462 4588{
4589 int hr;
cf95b4f0 4590 if(dops[t].is_ds) emit_addimm(HOST_CCREG,CLOCK_ADJUST(1),HOST_CCREG);
2330734f 4591 else if(ccadj[t]) emit_addimm(HOST_CCREG,-ccadj[t],HOST_CCREG);
57871462 4592 if(regs[t].regmap_entry[HOST_CCREG]!=CCREG) {
4593 emit_storereg(CCREG,HOST_CCREG);
4594 }
4595 // Load 32-bit regs
4596 for(hr=0;hr<HOST_REGS;hr++) {
ea3d2e6e 4597 if(regs[t].regmap_entry[hr]>=0&&regs[t].regmap_entry[hr]<TEMPREG) {
57871462 4598 if(regs[t].regmap_entry[hr]==0) {
4599 emit_zeroreg(hr);
4600 }
4601 else if(regs[t].regmap_entry[hr]!=CCREG)
4602 {
4603 emit_loadreg(regs[t].regmap_entry[hr],hr);
4604 }
4605 }
4606 }
57871462 4607}
4608
4609// Store dirty registers prior to branch
ad49de89 4610void store_regs_bt(signed char i_regmap[],uint64_t i_dirty,int addr)
57871462 4611{
ad49de89 4612 if(internal_branch(addr))
57871462 4613 {
4614 int t=(addr-start)>>2;
4615 int hr;
4616 for(hr=0;hr<HOST_REGS;hr++) {
4617 if(hr!=EXCLUDE_REG) {
4618 if(i_regmap[hr]>0 && i_regmap[hr]!=CCREG) {
ad49de89 4619 if(i_regmap[hr]!=regs[t].regmap_entry[hr] || !((regs[t].dirty>>hr)&1)) {
57871462 4620 if((i_dirty>>hr)&1) {
00fa9369 4621 assert(i_regmap[hr]<64);
4622 if(!((unneeded_reg[t]>>i_regmap[hr])&1))
4623 emit_storereg(i_regmap[hr],hr);
57871462 4624 }
4625 }
4626 }
4627 }
4628 }
4629 }
4630 else
4631 {
4632 // Branch out of this block, write out all dirty regs
ad49de89 4633 wb_dirtys(i_regmap,i_dirty);
57871462 4634 }
4635}
4636
4637// Load all needed registers for branch target
ad49de89 4638static void load_regs_bt(signed char i_regmap[],uint64_t i_dirty,int addr)
57871462 4639{
4640 //if(addr>=start && addr<(start+slen*4))
ad49de89 4641 if(internal_branch(addr))
57871462 4642 {
4643 int t=(addr-start)>>2;
4644 int hr;
4645 // Store the cycle count before loading something else
4646 if(i_regmap[HOST_CCREG]!=CCREG) {
4647 assert(i_regmap[HOST_CCREG]==-1);
4648 }
4649 if(regs[t].regmap_entry[HOST_CCREG]!=CCREG) {
4650 emit_storereg(CCREG,HOST_CCREG);
4651 }
4652 // Load 32-bit regs
4653 for(hr=0;hr<HOST_REGS;hr++) {
ea3d2e6e 4654 if(hr!=EXCLUDE_REG&&regs[t].regmap_entry[hr]>=0&&regs[t].regmap_entry[hr]<TEMPREG) {
00fa9369 4655 if(i_regmap[hr]!=regs[t].regmap_entry[hr]) {
57871462 4656 if(regs[t].regmap_entry[hr]==0) {
4657 emit_zeroreg(hr);
4658 }
4659 else if(regs[t].regmap_entry[hr]!=CCREG)
4660 {
4661 emit_loadreg(regs[t].regmap_entry[hr],hr);
4662 }
4663 }
4664 }
4665 }
57871462 4666 }
4667}
4668
ad49de89 4669static int match_bt(signed char i_regmap[],uint64_t i_dirty,int addr)
57871462 4670{
4671 if(addr>=start && addr<start+slen*4-4)
4672 {
4673 int t=(addr-start)>>2;
4674 int hr;
4675 if(regs[t].regmap_entry[HOST_CCREG]!=CCREG) return 0;
4676 for(hr=0;hr<HOST_REGS;hr++)
4677 {
4678 if(hr!=EXCLUDE_REG)
4679 {
4680 if(i_regmap[hr]!=regs[t].regmap_entry[hr])
4681 {
ea3d2e6e 4682 if(regs[t].regmap_entry[hr]>=0&&(regs[t].regmap_entry[hr]|64)<TEMPREG+64)
57871462 4683 {
4684 return 0;
4685 }
9f51b4b9 4686 else
57871462 4687 if((i_dirty>>hr)&1)
4688 {
ea3d2e6e 4689 if(i_regmap[hr]<TEMPREG)
57871462 4690 {
4691 if(!((unneeded_reg[t]>>i_regmap[hr])&1))
4692 return 0;
4693 }
ea3d2e6e 4694 else if(i_regmap[hr]>=64&&i_regmap[hr]<TEMPREG+64)
57871462 4695 {
00fa9369 4696 assert(0);
57871462 4697 }
4698 }
4699 }
4700 else // Same register but is it 32-bit or dirty?
4701 if(i_regmap[hr]>=0)
4702 {
4703 if(!((regs[t].dirty>>hr)&1))
4704 {
4705 if((i_dirty>>hr)&1)
4706 {
4707 if(!((unneeded_reg[t]>>i_regmap[hr])&1))
4708 {
4709 //printf("%x: dirty no match\n",addr);
4710 return 0;
4711 }
4712 }
4713 }
57871462 4714 }
4715 }
4716 }
57871462 4717 // Delay slots are not valid branch targets
fe807a8a 4718 //if(t>0&&(dops[t-1].is_jump) return 0;
57871462 4719 // Delay slots require additional processing, so do not match
cf95b4f0 4720 if(dops[t].is_ds) return 0;
57871462 4721 }
4722 else
4723 {
4724 int hr;
4725 for(hr=0;hr<HOST_REGS;hr++)
4726 {
4727 if(hr!=EXCLUDE_REG)
4728 {
4729 if(i_regmap[hr]>=0)
4730 {
4731 if(hr!=HOST_CCREG||i_regmap[hr]!=CCREG)
4732 {
4733 if((i_dirty>>hr)&1)
4734 {
4735 return 0;
4736 }
4737 }
4738 }
4739 }
4740 }
4741 }
4742 return 1;
4743}
4744
dd114d7d 4745#ifdef DRC_DBG
2330734f 4746static void drc_dbg_emit_do_cmp(int i, int ccadj_)
dd114d7d 4747{
4748 extern void do_insn_cmp();
3968e69e 4749 //extern int cycle;
81dbbf4c 4750 u_int hr, reglist = get_host_reglist(regs[i].regmap);
dd114d7d 4751
40fca85b 4752 assem_debug("//do_insn_cmp %08x\n", start+i*4);
dd114d7d 4753 save_regs(reglist);
40fca85b 4754 // write out changed consts to match the interpreter
cf95b4f0 4755 if (i > 0 && !dops[i].bt) {
40fca85b 4756 for (hr = 0; hr < HOST_REGS; hr++) {
2330734f 4757 int reg = regs[i].regmap_entry[hr]; // regs[i-1].regmap[hr];
40fca85b 4758 if (hr == EXCLUDE_REG || reg < 0)
4759 continue;
4760 if (!((regs[i-1].isconst >> hr) & 1))
4761 continue;
4762 if (i > 1 && reg == regs[i-2].regmap[hr] && constmap[i-1][hr] == constmap[i-2][hr])
4763 continue;
4764 emit_movimm(constmap[i-1][hr],0);
4765 emit_storereg(reg, 0);
4766 }
4767 }
dd114d7d 4768 emit_movimm(start+i*4,0);
643aeae3 4769 emit_writeword(0,&pcaddr);
2330734f 4770 int cc = get_reg(regs[i].regmap_entry, CCREG);
4771 if (cc < 0)
4772 emit_loadreg(CCREG, cc = 0);
4773 emit_addimm(cc, ccadj_, 0);
4774 emit_writeword(0, &psxRegs.cycle);
2a014d73 4775 emit_far_call(do_insn_cmp);
643aeae3 4776 //emit_readword(&cycle,0);
dd114d7d 4777 //emit_addimm(0,2,0);
643aeae3 4778 //emit_writeword(0,&cycle);
3968e69e 4779 (void)get_reg2;
dd114d7d 4780 restore_regs(reglist);
40fca85b 4781 assem_debug("\\\\do_insn_cmp\n");
dd114d7d 4782}
4783#else
2330734f 4784#define drc_dbg_emit_do_cmp(x,y)
dd114d7d 4785#endif
4786
57871462 4787// Used when a branch jumps into the delay slot of another branch
7c3a5182 4788static void ds_assemble_entry(int i)
57871462 4789{
2330734f 4790 int t = (ba[i] - start) >> 2;
4791 int ccadj_ = -CLOCK_ADJUST(1);
df4dc2b1 4792 if (!instr_addr[t])
4793 instr_addr[t] = out;
57871462 4794 assem_debug("Assemble delay slot at %x\n",ba[i]);
4795 assem_debug("<->\n");
2330734f 4796 drc_dbg_emit_do_cmp(t, ccadj_);
57871462 4797 if(regs[t].regmap_entry[HOST_CCREG]==CCREG&&regs[t].regmap[HOST_CCREG]!=CCREG)
ad49de89 4798 wb_register(CCREG,regs[t].regmap_entry,regs[t].wasdirty);
cf95b4f0 4799 load_regs(regs[t].regmap_entry,regs[t].regmap,dops[t].rs1,dops[t].rs2);
57871462 4800 address_generation(t,&regs[t],regs[t].regmap_entry);
37387d8b 4801 if (ram_offset && (dops[t].is_load || dops[t].is_store))
4802 load_regs(regs[t].regmap_entry,regs[t].regmap,ROREG,ROREG);
4803 if (dops[t].is_store)
ad49de89 4804 load_regs(regs[t].regmap_entry,regs[t].regmap,INVCP,INVCP);
57871462 4805 is_delayslot=0;
2330734f 4806 switch (dops[t].itype) {
57871462 4807 case SYSCALL:
7139f3c8 4808 case HLECALL:
1e973cb0 4809 case INTCALL:
57871462 4810 case SPAN:
4811 case UJUMP:
4812 case RJUMP:
4813 case CJUMP:
4814 case SJUMP:
c43b5311 4815 SysPrintf("Jump in the delay slot. This is probably a bug.\n");
2330734f 4816 break;
4817 default:
4818 assemble(t, &regs[t], ccadj_);
57871462 4819 }
ad49de89 4820 store_regs_bt(regs[t].regmap,regs[t].dirty,ba[i]+4);
4821 load_regs_bt(regs[t].regmap,regs[t].dirty,ba[i]+4);
4822 if(internal_branch(ba[i]+4))
57871462 4823 assem_debug("branch: internal\n");
4824 else
4825 assem_debug("branch: external\n");
ad49de89 4826 assert(internal_branch(ba[i]+4));
4827 add_to_linker(out,ba[i]+4,internal_branch(ba[i]+4));
57871462 4828 emit_jmp(0);
4829}
4830
7c3a5182 4831static void emit_extjump(void *addr, u_int target)
4832{
4833 emit_extjump2(addr, target, dyna_linker);
4834}
4835
4836static void emit_extjump_ds(void *addr, u_int target)
4837{
4838 emit_extjump2(addr, target, dyna_linker_ds);
4839}
4840
d1e4ebd9 4841// Load 2 immediates optimizing for small code size
4842static void emit_mov2imm_compact(int imm1,u_int rt1,int imm2,u_int rt2)
4843{
4844 emit_movimm(imm1,rt1);
4845 emit_movimm_from(imm1,rt1,imm2,rt2);
4846}
4847
2330734f 4848static void do_cc(int i, const signed char i_regmap[], int *adj,
4849 int addr, int taken, int invert)
57871462 4850{
2330734f 4851 int count, count_plus2;
b14b6a8f 4852 void *jaddr;
4853 void *idle=NULL;
b6e87b2b 4854 int t=0;
cf95b4f0 4855 if(dops[i].itype==RJUMP)
57871462 4856 {
4857 *adj=0;
4858 }
4859 //if(ba[i]>=start && ba[i]<(start+slen*4))
ad49de89 4860 if(internal_branch(ba[i]))
57871462 4861 {
b6e87b2b 4862 t=(ba[i]-start)>>2;
2330734f 4863 if(dops[t].is_ds) *adj=-CLOCK_ADJUST(1); // Branch into delay slot adds an extra cycle
57871462 4864 else *adj=ccadj[t];
4865 }
4866 else
4867 {
4868 *adj=0;
4869 }
2330734f 4870 count = ccadj[i];
4871 count_plus2 = count + CLOCK_ADJUST(2);
57871462 4872 if(taken==TAKEN && i==(ba[i]-start)>>2 && source[i+1]==0) {
4873 // Idle loop
4874 if(count&1) emit_addimm_and_set_flags(2*(count+2),HOST_CCREG);
b14b6a8f 4875 idle=out;
57871462 4876 //emit_subfrommem(&idlecount,HOST_CCREG); // Count idle cycles
4877 emit_andimm(HOST_CCREG,3,HOST_CCREG);
b14b6a8f 4878 jaddr=out;
57871462 4879 emit_jmp(0);
4880 }
4881 else if(*adj==0||invert) {
2330734f 4882 int cycles = count_plus2;
b6e87b2b 4883 // faster loop HACK
bb4f300c 4884#if 0
b6e87b2b 4885 if (t&&*adj) {
4886 int rel=t-i;
4887 if(-NO_CYCLE_PENALTY_THR<rel&&rel<0)
2330734f 4888 cycles=*adj+count+2-*adj;
b6e87b2b 4889 }
bb4f300c 4890#endif
2330734f 4891 emit_addimm_and_set_flags(cycles, HOST_CCREG);
4892 jaddr = out;
57871462 4893 emit_jns(0);
4894 }
4895 else
4896 {
2330734f 4897 emit_cmpimm(HOST_CCREG, -count_plus2);
4898 jaddr = out;
57871462 4899 emit_jns(0);
4900 }
2330734f 4901 add_stub(CC_STUB,jaddr,idle?idle:out,(*adj==0||invert||idle)?0:count_plus2,i,addr,taken,0);
57871462 4902}
4903
b14b6a8f 4904static void do_ccstub(int n)
57871462 4905{
4906 literal_pool(256);
d1e4ebd9 4907 assem_debug("do_ccstub %x\n",start+(u_int)stubs[n].b*4);
b14b6a8f 4908 set_jump_target(stubs[n].addr, out);
4909 int i=stubs[n].b;
4910 if(stubs[n].d==NULLDS) {
57871462 4911 // Delay slot instruction is nullified ("likely" branch)
ad49de89 4912 wb_dirtys(regs[i].regmap,regs[i].dirty);
57871462 4913 }
b14b6a8f 4914 else if(stubs[n].d!=TAKEN) {
ad49de89 4915 wb_dirtys(branch_regs[i].regmap,branch_regs[i].dirty);
57871462 4916 }
4917 else {
ad49de89 4918 if(internal_branch(ba[i]))
4919 wb_needed_dirtys(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]);
57871462 4920 }
b14b6a8f 4921 if(stubs[n].c!=-1)
57871462 4922 {
4923 // Save PC as return address
b14b6a8f 4924 emit_movimm(stubs[n].c,EAX);
643aeae3 4925 emit_writeword(EAX,&pcaddr);
57871462 4926 }
4927 else
4928 {
4929 // Return address depends on which way the branch goes
cf95b4f0 4930 if(dops[i].itype==CJUMP||dops[i].itype==SJUMP)
57871462 4931 {
cf95b4f0 4932 int s1l=get_reg(branch_regs[i].regmap,dops[i].rs1);
4933 int s2l=get_reg(branch_regs[i].regmap,dops[i].rs2);
4934 if(dops[i].rs1==0)
57871462 4935 {
ad49de89 4936 s1l=s2l;
4937 s2l=-1;
57871462 4938 }
cf95b4f0 4939 else if(dops[i].rs2==0)
57871462 4940 {
ad49de89 4941 s2l=-1;
57871462 4942 }
4943 assert(s1l>=0);
4944 #ifdef DESTRUCTIVE_WRITEBACK
cf95b4f0 4945 if(dops[i].rs1) {
ad49de89 4946 if((branch_regs[i].dirty>>s1l)&&1)
cf95b4f0 4947 emit_loadreg(dops[i].rs1,s1l);
9f51b4b9 4948 }
57871462 4949 else {
ad49de89 4950 if((branch_regs[i].dirty>>s1l)&1)
cf95b4f0 4951 emit_loadreg(dops[i].rs2,s1l);
57871462 4952 }
4953 if(s2l>=0)
ad49de89 4954 if((branch_regs[i].dirty>>s2l)&1)
cf95b4f0 4955 emit_loadreg(dops[i].rs2,s2l);
57871462 4956 #endif
4957 int hr=0;
5194fb95 4958 int addr=-1,alt=-1,ntaddr=-1;
57871462 4959 while(hr<HOST_REGS)
4960 {
4961 if(hr!=EXCLUDE_REG && hr!=HOST_CCREG &&
cf95b4f0 4962 (branch_regs[i].regmap[hr]&63)!=dops[i].rs1 &&
4963 (branch_regs[i].regmap[hr]&63)!=dops[i].rs2 )
57871462 4964 {
4965 addr=hr++;break;
4966 }
4967 hr++;
4968 }
4969 while(hr<HOST_REGS)
4970 {
4971 if(hr!=EXCLUDE_REG && hr!=HOST_CCREG &&
cf95b4f0 4972 (branch_regs[i].regmap[hr]&63)!=dops[i].rs1 &&
4973 (branch_regs[i].regmap[hr]&63)!=dops[i].rs2 )
57871462 4974 {
4975 alt=hr++;break;
4976 }
4977 hr++;
4978 }
cf95b4f0 4979 if((dops[i].opcode&0x2E)==6) // BLEZ/BGTZ needs another register
57871462 4980 {
4981 while(hr<HOST_REGS)
4982 {
4983 if(hr!=EXCLUDE_REG && hr!=HOST_CCREG &&
cf95b4f0 4984 (branch_regs[i].regmap[hr]&63)!=dops[i].rs1 &&
4985 (branch_regs[i].regmap[hr]&63)!=dops[i].rs2 )
57871462 4986 {
4987 ntaddr=hr;break;
4988 }
4989 hr++;
4990 }
4991 assert(hr<HOST_REGS);
4992 }
cf95b4f0 4993 if((dops[i].opcode&0x2f)==4) // BEQ
57871462 4994 {
4995 #ifdef HAVE_CMOV_IMM
ad49de89 4996 if(s2l>=0) emit_cmp(s1l,s2l);
4997 else emit_test(s1l,s1l);
4998 emit_cmov2imm_e_ne_compact(ba[i],start+i*4+8,addr);
4999 #else
5000 emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
5001 if(s2l>=0) emit_cmp(s1l,s2l);
5002 else emit_test(s1l,s1l);
5003 emit_cmovne_reg(alt,addr);
57871462 5004 #endif
57871462 5005 }
cf95b4f0 5006 if((dops[i].opcode&0x2f)==5) // BNE
57871462 5007 {
5008 #ifdef HAVE_CMOV_IMM
ad49de89 5009 if(s2l>=0) emit_cmp(s1l,s2l);
5010 else emit_test(s1l,s1l);
5011 emit_cmov2imm_e_ne_compact(start+i*4+8,ba[i],addr);
5012 #else
5013 emit_mov2imm_compact(start+i*4+8,addr,ba[i],alt);
5014 if(s2l>=0) emit_cmp(s1l,s2l);
5015 else emit_test(s1l,s1l);
5016 emit_cmovne_reg(alt,addr);
57871462 5017 #endif
57871462 5018 }
cf95b4f0 5019 if((dops[i].opcode&0x2f)==6) // BLEZ
57871462 5020 {
5021 //emit_movimm(ba[i],alt);
5022 //emit_movimm(start+i*4+8,addr);
5023 emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
5024 emit_cmpimm(s1l,1);
57871462 5025 emit_cmovl_reg(alt,addr);
57871462 5026 }
cf95b4f0 5027 if((dops[i].opcode&0x2f)==7) // BGTZ
57871462 5028 {
5029 //emit_movimm(ba[i],addr);
5030 //emit_movimm(start+i*4+8,ntaddr);
5031 emit_mov2imm_compact(ba[i],addr,start+i*4+8,ntaddr);
5032 emit_cmpimm(s1l,1);
57871462 5033 emit_cmovl_reg(ntaddr,addr);
57871462 5034 }
cf95b4f0 5035 if((dops[i].opcode==1)&&(dops[i].opcode2&0x2D)==0) // BLTZ
57871462 5036 {
5037 //emit_movimm(ba[i],alt);
5038 //emit_movimm(start+i*4+8,addr);
5039 emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
ad49de89 5040 emit_test(s1l,s1l);
57871462 5041 emit_cmovs_reg(alt,addr);
5042 }
cf95b4f0 5043 if((dops[i].opcode==1)&&(dops[i].opcode2&0x2D)==1) // BGEZ
57871462 5044 {
5045 //emit_movimm(ba[i],addr);
5046 //emit_movimm(start+i*4+8,alt);
5047 emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
ad49de89 5048 emit_test(s1l,s1l);
57871462 5049 emit_cmovs_reg(alt,addr);
5050 }
cf95b4f0 5051 if(dops[i].opcode==0x11 && dops[i].opcode2==0x08 ) {
57871462 5052 if(source[i]&0x10000) // BC1T
5053 {
5054 //emit_movimm(ba[i],alt);
5055 //emit_movimm(start+i*4+8,addr);
5056 emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
5057 emit_testimm(s1l,0x800000);
5058 emit_cmovne_reg(alt,addr);
5059 }
5060 else // BC1F
5061 {
5062 //emit_movimm(ba[i],addr);
5063 //emit_movimm(start+i*4+8,alt);
5064 emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
5065 emit_testimm(s1l,0x800000);
5066 emit_cmovne_reg(alt,addr);
5067 }
5068 }
643aeae3 5069 emit_writeword(addr,&pcaddr);
57871462 5070 }
5071 else
cf95b4f0 5072 if(dops[i].itype==RJUMP)
57871462 5073 {
cf95b4f0 5074 int r=get_reg(branch_regs[i].regmap,dops[i].rs1);
4919de1e 5075 if (ds_writes_rjump_rs(i)) {
57871462 5076 r=get_reg(branch_regs[i].regmap,RTEMP);
5077 }
643aeae3 5078 emit_writeword(r,&pcaddr);
57871462 5079 }
7c3a5182 5080 else {SysPrintf("Unknown branch type in do_ccstub\n");abort();}
57871462 5081 }
5082 // Update cycle count
5083 assert(branch_regs[i].regmap[HOST_CCREG]==CCREG||branch_regs[i].regmap[HOST_CCREG]==-1);
2330734f 5084 if(stubs[n].a) emit_addimm(HOST_CCREG,(int)stubs[n].a,HOST_CCREG);
2a014d73 5085 emit_far_call(cc_interrupt);
2330734f 5086 if(stubs[n].a) emit_addimm(HOST_CCREG,-(int)stubs[n].a,HOST_CCREG);
b14b6a8f 5087 if(stubs[n].d==TAKEN) {
ad49de89 5088 if(internal_branch(ba[i]))
57871462 5089 load_needed_regs(branch_regs[i].regmap,regs[(ba[i]-start)>>2].regmap_entry);
cf95b4f0 5090 else if(dops[i].itype==RJUMP) {
57871462 5091 if(get_reg(branch_regs[i].regmap,RTEMP)>=0)
643aeae3 5092 emit_readword(&pcaddr,get_reg(branch_regs[i].regmap,RTEMP));
57871462 5093 else
cf95b4f0 5094 emit_loadreg(dops[i].rs1,get_reg(branch_regs[i].regmap,dops[i].rs1));
57871462 5095 }
b14b6a8f 5096 }else if(stubs[n].d==NOTTAKEN) {
57871462 5097 if(i<slen-2) load_needed_regs(branch_regs[i].regmap,regmap_pre[i+2]);
5098 else load_all_regs(branch_regs[i].regmap);
b14b6a8f 5099 }else if(stubs[n].d==NULLDS) {
57871462 5100 // Delay slot instruction is nullified ("likely" branch)
5101 if(i<slen-2) load_needed_regs(regs[i].regmap,regmap_pre[i+2]);
5102 else load_all_regs(regs[i].regmap);
5103 }else{
5104 load_all_regs(branch_regs[i].regmap);
5105 }
d1e4ebd9 5106 if (stubs[n].retaddr)
5107 emit_jmp(stubs[n].retaddr);
5108 else
5109 do_jump_vaddr(stubs[n].e);
57871462 5110}
5111
643aeae3 5112static void add_to_linker(void *addr, u_int target, int ext)
57871462 5113{
643aeae3 5114 assert(linkcount < ARRAY_SIZE(link_addr));
5115 link_addr[linkcount].addr = addr;
5116 link_addr[linkcount].target = target;
5117 link_addr[linkcount].ext = ext;
57871462 5118 linkcount++;
5119}
5120
eba830cd 5121static void ujump_assemble_write_ra(int i)
5122{
5123 int rt;
5124 unsigned int return_address;
5125 rt=get_reg(branch_regs[i].regmap,31);
5126 assem_debug("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5127 //assert(rt>=0);
5128 return_address=start+i*4+8;
5129 if(rt>=0) {
5130 #ifdef USE_MINI_HT
cf95b4f0 5131 if(internal_branch(return_address)&&dops[i+1].rt1!=31) {
eba830cd 5132 int temp=-1; // note: must be ds-safe
5133 #ifdef HOST_TEMPREG
5134 temp=HOST_TEMPREG;
5135 #endif
5136 if(temp>=0) do_miniht_insert(return_address,rt,temp);
5137 else emit_movimm(return_address,rt);
5138 }
5139 else
5140 #endif
5141 {
5142 #ifdef REG_PREFETCH
9f51b4b9 5143 if(temp>=0)
eba830cd 5144 {
643aeae3 5145 if(i_regmap[temp]!=PTEMP) emit_movimm((uintptr_t)hash_table_get(return_address),temp);
eba830cd 5146 }
5147 #endif
5148 emit_movimm(return_address,rt); // PC into link register
5149 #ifdef IMM_PREFETCH
df4dc2b1 5150 emit_prefetch(hash_table_get(return_address));
eba830cd 5151 #endif
5152 }
5153 }
5154}
5155
2330734f 5156static void ujump_assemble(int i, const struct regstat *i_regs)
57871462 5157{
eba830cd 5158 int ra_done=0;
57871462 5159 if(i==(ba[i]-start)>>2) assem_debug("idle loop\n");
5160 address_generation(i+1,i_regs,regs[i].regmap_entry);
5161 #ifdef REG_PREFETCH
5162 int temp=get_reg(branch_regs[i].regmap,PTEMP);
cf95b4f0 5163 if(dops[i].rt1==31&&temp>=0)
57871462 5164 {
581335b0 5165 signed char *i_regmap=i_regs->regmap;
57871462 5166 int return_address=start+i*4+8;
9f51b4b9 5167 if(get_reg(branch_regs[i].regmap,31)>0)
643aeae3 5168 if(i_regmap[temp]==PTEMP) emit_movimm((uintptr_t)hash_table_get(return_address),temp);
57871462 5169 }
5170 #endif
cf95b4f0 5171 if(dops[i].rt1==31&&(dops[i].rt1==dops[i+1].rs1||dops[i].rt1==dops[i+1].rs2)) {
eba830cd 5172 ujump_assemble_write_ra(i); // writeback ra for DS
5173 ra_done=1;
57871462 5174 }
4ef8f67d 5175 ds_assemble(i+1,i_regs);
5176 uint64_t bc_unneeded=branch_regs[i].u;
cf95b4f0 5177 bc_unneeded|=1|(1LL<<dops[i].rt1);
ad49de89 5178 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,bc_unneeded);
5179 load_regs(regs[i].regmap,branch_regs[i].regmap,CCREG,CCREG);
cf95b4f0 5180 if(!ra_done&&dops[i].rt1==31)
eba830cd 5181 ujump_assemble_write_ra(i);
57871462 5182 int cc,adj;
5183 cc=get_reg(branch_regs[i].regmap,CCREG);
5184 assert(cc==HOST_CCREG);
ad49de89 5185 store_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]);
57871462 5186 #ifdef REG_PREFETCH
cf95b4f0 5187 if(dops[i].rt1==31&&temp>=0) emit_prefetchreg(temp);
57871462 5188 #endif
5189 do_cc(i,branch_regs[i].regmap,&adj,ba[i],TAKEN,0);
2330734f 5190 if(adj) emit_addimm(cc, ccadj[i] + CLOCK_ADJUST(2) - adj, cc);
ad49de89 5191 load_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]);
5192 if(internal_branch(ba[i]))
57871462 5193 assem_debug("branch: internal\n");
5194 else
5195 assem_debug("branch: external\n");
cf95b4f0 5196 if (internal_branch(ba[i]) && dops[(ba[i]-start)>>2].is_ds) {
57871462 5197 ds_assemble_entry(i);
5198 }
5199 else {
ad49de89 5200 add_to_linker(out,ba[i],internal_branch(ba[i]));
57871462 5201 emit_jmp(0);
5202 }
5203}
5204
eba830cd 5205static void rjump_assemble_write_ra(int i)
5206{
5207 int rt,return_address;
cf95b4f0 5208 assert(dops[i+1].rt1!=dops[i].rt1);
5209 assert(dops[i+1].rt2!=dops[i].rt1);
5210 rt=get_reg(branch_regs[i].regmap,dops[i].rt1);
eba830cd 5211 assem_debug("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5212 assert(rt>=0);
5213 return_address=start+i*4+8;
5214 #ifdef REG_PREFETCH
9f51b4b9 5215 if(temp>=0)
eba830cd 5216 {
643aeae3 5217 if(i_regmap[temp]!=PTEMP) emit_movimm((uintptr_t)hash_table_get(return_address),temp);
eba830cd 5218 }
5219 #endif
5220 emit_movimm(return_address,rt); // PC into link register
5221 #ifdef IMM_PREFETCH
df4dc2b1 5222 emit_prefetch(hash_table_get(return_address));
eba830cd 5223 #endif
5224}
5225
2330734f 5226static void rjump_assemble(int i, const struct regstat *i_regs)
57871462 5227{
57871462 5228 int temp;
581335b0 5229 int rs,cc;
eba830cd 5230 int ra_done=0;
cf95b4f0 5231 rs=get_reg(branch_regs[i].regmap,dops[i].rs1);
57871462 5232 assert(rs>=0);
4919de1e 5233 if (ds_writes_rjump_rs(i)) {
57871462 5234 // Delay slot abuse, make a copy of the branch address register
5235 temp=get_reg(branch_regs[i].regmap,RTEMP);
5236 assert(temp>=0);
5237 assert(regs[i].regmap[temp]==RTEMP);
5238 emit_mov(rs,temp);
5239 rs=temp;
5240 }
5241 address_generation(i+1,i_regs,regs[i].regmap_entry);
5242 #ifdef REG_PREFETCH
cf95b4f0 5243 if(dops[i].rt1==31)
57871462 5244 {
5245 if((temp=get_reg(branch_regs[i].regmap,PTEMP))>=0) {
581335b0 5246 signed char *i_regmap=i_regs->regmap;
57871462 5247 int return_address=start+i*4+8;
643aeae3 5248 if(i_regmap[temp]==PTEMP) emit_movimm((uintptr_t)hash_table_get(return_address),temp);
57871462 5249 }
5250 }
5251 #endif
5252 #ifdef USE_MINI_HT
cf95b4f0 5253 if(dops[i].rs1==31) {
57871462 5254 int rh=get_reg(regs[i].regmap,RHASH);
5255 if(rh>=0) do_preload_rhash(rh);
5256 }
5257 #endif
cf95b4f0 5258 if(dops[i].rt1!=0&&(dops[i].rt1==dops[i+1].rs1||dops[i].rt1==dops[i+1].rs2)) {
eba830cd 5259 rjump_assemble_write_ra(i);
5260 ra_done=1;
57871462 5261 }
d5910d5d 5262 ds_assemble(i+1,i_regs);
5263 uint64_t bc_unneeded=branch_regs[i].u;
cf95b4f0 5264 bc_unneeded|=1|(1LL<<dops[i].rt1);
5265 bc_unneeded&=~(1LL<<dops[i].rs1);
ad49de89 5266 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,bc_unneeded);
cf95b4f0 5267 load_regs(regs[i].regmap,branch_regs[i].regmap,dops[i].rs1,CCREG);
5268 if(!ra_done&&dops[i].rt1!=0)
eba830cd 5269 rjump_assemble_write_ra(i);
57871462 5270 cc=get_reg(branch_regs[i].regmap,CCREG);
5271 assert(cc==HOST_CCREG);
581335b0 5272 (void)cc;
57871462 5273 #ifdef USE_MINI_HT
5274 int rh=get_reg(branch_regs[i].regmap,RHASH);
5275 int ht=get_reg(branch_regs[i].regmap,RHTBL);
cf95b4f0 5276 if(dops[i].rs1==31) {
57871462 5277 if(regs[i].regmap[rh]!=RHASH) do_preload_rhash(rh);
5278 do_preload_rhtbl(ht);
5279 do_rhash(rs,rh);
5280 }
5281 #endif
ad49de89 5282 store_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,-1);
57871462 5283 #ifdef DESTRUCTIVE_WRITEBACK
ad49de89 5284 if((branch_regs[i].dirty>>rs)&1) {
cf95b4f0 5285 if(dops[i].rs1!=dops[i+1].rt1&&dops[i].rs1!=dops[i+1].rt2) {
5286 emit_loadreg(dops[i].rs1,rs);
57871462 5287 }
5288 }
5289 #endif
5290 #ifdef REG_PREFETCH
cf95b4f0 5291 if(dops[i].rt1==31&&temp>=0) emit_prefetchreg(temp);
57871462 5292 #endif
5293 #ifdef USE_MINI_HT
cf95b4f0 5294 if(dops[i].rs1==31) {
57871462 5295 do_miniht_load(ht,rh);
5296 }
5297 #endif
5298 //do_cc(i,branch_regs[i].regmap,&adj,-1,TAKEN);
5299 //if(adj) emit_addimm(cc,2*(ccadj[i]+2-adj),cc); // ??? - Shouldn't happen
5300 //assert(adj==0);
2330734f 5301 emit_addimm_and_set_flags(ccadj[i] + CLOCK_ADJUST(2), HOST_CCREG);
d1e4ebd9 5302 add_stub(CC_STUB,out,NULL,0,i,-1,TAKEN,rs);
cf95b4f0 5303 if(dops[i+1].itype==COP0&&(source[i+1]&0x3f)==0x10)
911f2d55 5304 // special case for RFE
5305 emit_jmp(0);
5306 else
71e490c5 5307 emit_jns(0);
ad49de89 5308 //load_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,-1);
57871462 5309 #ifdef USE_MINI_HT
cf95b4f0 5310 if(dops[i].rs1==31) {
57871462 5311 do_miniht_jump(rs,rh,ht);
5312 }
5313 else
5314 #endif
5315 {
d1e4ebd9 5316 do_jump_vaddr(rs);
57871462 5317 }
57871462 5318 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
cf95b4f0 5319 if(dops[i].rt1!=31&&i<slen-2&&(((u_int)out)&7)) emit_mov(13,13);
57871462 5320 #endif
5321}
5322
2330734f 5323static void cjump_assemble(int i, const struct regstat *i_regs)
57871462 5324{
2330734f 5325 const signed char *i_regmap = i_regs->regmap;
57871462 5326 int cc;
5327 int match;
ad49de89 5328 match=match_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]);
57871462 5329 assem_debug("match=%d\n",match);
ad49de89 5330 int s1l,s2l;
57871462 5331 int unconditional=0,nop=0;
57871462 5332 int invert=0;
ad49de89 5333 int internal=internal_branch(ba[i]);
57871462 5334 if(i==(ba[i]-start)>>2) assem_debug("idle loop\n");
57871462 5335 if(!match) invert=1;
5336 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5337 if(i>(ba[i]-start)>>2) invert=1;
5338 #endif
3968e69e 5339 #ifdef __aarch64__
5340 invert=1; // because of near cond. branches
5341 #endif
9f51b4b9 5342
cf95b4f0 5343 if(dops[i].ooo) {
5344 s1l=get_reg(branch_regs[i].regmap,dops[i].rs1);
5345 s2l=get_reg(branch_regs[i].regmap,dops[i].rs2);
57871462 5346 }
5347 else {
cf95b4f0 5348 s1l=get_reg(i_regmap,dops[i].rs1);
5349 s2l=get_reg(i_regmap,dops[i].rs2);
57871462 5350 }
cf95b4f0 5351 if(dops[i].rs1==0&&dops[i].rs2==0)
57871462 5352 {
cf95b4f0 5353 if(dops[i].opcode&1) nop=1;
57871462 5354 else unconditional=1;
cf95b4f0 5355 //assert(dops[i].opcode!=5);
5356 //assert(dops[i].opcode!=7);
5357 //assert(dops[i].opcode!=0x15);
5358 //assert(dops[i].opcode!=0x17);
57871462 5359 }
cf95b4f0 5360 else if(dops[i].rs1==0)
57871462 5361 {
ad49de89 5362 s1l=s2l;
5363 s2l=-1;
57871462 5364 }
cf95b4f0 5365 else if(dops[i].rs2==0)
57871462 5366 {
ad49de89 5367 s2l=-1;
57871462 5368 }
5369
cf95b4f0 5370 if(dops[i].ooo) {
57871462 5371 // Out of order execution (delay slot first)
5372 //printf("OOOE\n");
5373 address_generation(i+1,i_regs,regs[i].regmap_entry);
5374 ds_assemble(i+1,i_regs);
5375 int adj;
5376 uint64_t bc_unneeded=branch_regs[i].u;
cf95b4f0 5377 bc_unneeded&=~((1LL<<dops[i].rs1)|(1LL<<dops[i].rs2));
57871462 5378 bc_unneeded|=1;
ad49de89 5379 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,bc_unneeded);
cf95b4f0 5380 load_regs(regs[i].regmap,branch_regs[i].regmap,dops[i].rs1,dops[i].rs2);
ad49de89 5381 load_regs(regs[i].regmap,branch_regs[i].regmap,CCREG,CCREG);
57871462 5382 cc=get_reg(branch_regs[i].regmap,CCREG);
5383 assert(cc==HOST_CCREG);
9f51b4b9 5384 if(unconditional)
ad49de89 5385 store_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]);
57871462 5386 //do_cc(i,branch_regs[i].regmap,&adj,unconditional?ba[i]:-1,unconditional);
5387 //assem_debug("cycle count (adj)\n");
5388 if(unconditional) {
5389 do_cc(i,branch_regs[i].regmap,&adj,ba[i],TAKEN,0);
5390 if(i!=(ba[i]-start)>>2 || source[i+1]!=0) {
2330734f 5391 if(adj) emit_addimm(cc, ccadj[i] + CLOCK_ADJUST(2) - adj, cc);
ad49de89 5392 load_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]);
57871462 5393 if(internal)
5394 assem_debug("branch: internal\n");
5395 else
5396 assem_debug("branch: external\n");
cf95b4f0 5397 if (internal && dops[(ba[i]-start)>>2].is_ds) {
57871462 5398 ds_assemble_entry(i);
5399 }
5400 else {
643aeae3 5401 add_to_linker(out,ba[i],internal);
57871462 5402 emit_jmp(0);
5403 }
5404 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5405 if(((u_int)out)&7) emit_addnop(0);
5406 #endif
5407 }
5408 }
5409 else if(nop) {
2330734f 5410 emit_addimm_and_set_flags(ccadj[i] + CLOCK_ADJUST(2), cc);
b14b6a8f 5411 void *jaddr=out;
57871462 5412 emit_jns(0);
b14b6a8f 5413 add_stub(CC_STUB,jaddr,out,0,i,start+i*4+8,NOTTAKEN,0);
57871462 5414 }
5415 else {
df4dc2b1 5416 void *taken = NULL, *nottaken = NULL, *nottaken1 = NULL;
57871462 5417 do_cc(i,branch_regs[i].regmap,&adj,-1,0,invert);
2330734f 5418 if(adj&&!invert) emit_addimm(cc, ccadj[i] + CLOCK_ADJUST(2) - adj, cc);
9f51b4b9 5419
57871462 5420 //printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5421 assert(s1l>=0);
cf95b4f0 5422 if(dops[i].opcode==4) // BEQ
57871462 5423 {
5424 if(s2l>=0) emit_cmp(s1l,s2l);
5425 else emit_test(s1l,s1l);
5426 if(invert){
df4dc2b1 5427 nottaken=out;
7c3a5182 5428 emit_jne(DJT_1);
57871462 5429 }else{
643aeae3 5430 add_to_linker(out,ba[i],internal);
57871462 5431 emit_jeq(0);
5432 }
5433 }
cf95b4f0 5434 if(dops[i].opcode==5) // BNE
57871462 5435 {
5436 if(s2l>=0) emit_cmp(s1l,s2l);
5437 else emit_test(s1l,s1l);
5438 if(invert){
df4dc2b1 5439 nottaken=out;
7c3a5182 5440 emit_jeq(DJT_1);
57871462 5441 }else{
643aeae3 5442 add_to_linker(out,ba[i],internal);
57871462 5443 emit_jne(0);
5444 }
5445 }
cf95b4f0 5446 if(dops[i].opcode==6) // BLEZ
57871462 5447 {
5448 emit_cmpimm(s1l,1);
5449 if(invert){
df4dc2b1 5450 nottaken=out;
7c3a5182 5451 emit_jge(DJT_1);
57871462 5452 }else{
643aeae3 5453 add_to_linker(out,ba[i],internal);
57871462 5454 emit_jl(0);
5455 }
5456 }
cf95b4f0 5457 if(dops[i].opcode==7) // BGTZ
57871462 5458 {
5459 emit_cmpimm(s1l,1);
5460 if(invert){
df4dc2b1 5461 nottaken=out;
7c3a5182 5462 emit_jl(DJT_1);
57871462 5463 }else{
643aeae3 5464 add_to_linker(out,ba[i],internal);
57871462 5465 emit_jge(0);
5466 }
5467 }
5468 if(invert) {
df4dc2b1 5469 if(taken) set_jump_target(taken, out);
57871462 5470 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
cf95b4f0 5471 if (match && (!internal || !dops[(ba[i]-start)>>2].is_ds)) {
57871462 5472 if(adj) {
2330734f 5473 emit_addimm(cc,-adj,cc);
643aeae3 5474 add_to_linker(out,ba[i],internal);
57871462 5475 }else{
5476 emit_addnop(13);
643aeae3 5477 add_to_linker(out,ba[i],internal*2);
57871462 5478 }
5479 emit_jmp(0);
5480 }else
5481 #endif
5482 {
2330734f 5483 if(adj) emit_addimm(cc,-adj,cc);
ad49de89 5484 store_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]);
5485 load_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]);
57871462 5486 if(internal)
5487 assem_debug("branch: internal\n");
5488 else
5489 assem_debug("branch: external\n");
cf95b4f0 5490 if (internal && dops[(ba[i] - start) >> 2].is_ds) {
57871462 5491 ds_assemble_entry(i);
5492 }
5493 else {
643aeae3 5494 add_to_linker(out,ba[i],internal);
57871462 5495 emit_jmp(0);
5496 }
5497 }
df4dc2b1 5498 set_jump_target(nottaken, out);
57871462 5499 }
5500
df4dc2b1 5501 if(nottaken1) set_jump_target(nottaken1, out);
57871462 5502 if(adj) {
2330734f 5503 if(!invert) emit_addimm(cc,adj,cc);
57871462 5504 }
5505 } // (!unconditional)
5506 } // if(ooo)
5507 else
5508 {
5509 // In-order execution (branch first)
df4dc2b1 5510 void *taken = NULL, *nottaken = NULL, *nottaken1 = NULL;
57871462 5511 if(!unconditional&&!nop) {
57871462 5512 //printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5513 assert(s1l>=0);
cf95b4f0 5514 if((dops[i].opcode&0x2f)==4) // BEQ
57871462 5515 {
5516 if(s2l>=0) emit_cmp(s1l,s2l);
5517 else emit_test(s1l,s1l);
df4dc2b1 5518 nottaken=out;
7c3a5182 5519 emit_jne(DJT_2);
57871462 5520 }
cf95b4f0 5521 if((dops[i].opcode&0x2f)==5) // BNE
57871462 5522 {
5523 if(s2l>=0) emit_cmp(s1l,s2l);
5524 else emit_test(s1l,s1l);
df4dc2b1 5525 nottaken=out;
7c3a5182 5526 emit_jeq(DJT_2);
57871462 5527 }
cf95b4f0 5528 if((dops[i].opcode&0x2f)==6) // BLEZ
57871462 5529 {
5530 emit_cmpimm(s1l,1);
df4dc2b1 5531 nottaken=out;
7c3a5182 5532 emit_jge(DJT_2);
57871462 5533 }
cf95b4f0 5534 if((dops[i].opcode&0x2f)==7) // BGTZ
57871462 5535 {
5536 emit_cmpimm(s1l,1);
df4dc2b1 5537 nottaken=out;
7c3a5182 5538 emit_jl(DJT_2);
57871462 5539 }
5540 } // if(!unconditional)
5541 int adj;
5542 uint64_t ds_unneeded=branch_regs[i].u;
cf95b4f0 5543 ds_unneeded&=~((1LL<<dops[i+1].rs1)|(1LL<<dops[i+1].rs2));
57871462 5544 ds_unneeded|=1;
57871462 5545 // branch taken
5546 if(!nop) {
df4dc2b1 5547 if(taken) set_jump_target(taken, out);
57871462 5548 assem_debug("1:\n");
ad49de89 5549 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,ds_unneeded);
57871462 5550 // load regs
cf95b4f0 5551 load_regs(regs[i].regmap,branch_regs[i].regmap,dops[i+1].rs1,dops[i+1].rs2);
57871462 5552 address_generation(i+1,&branch_regs[i],0);
37387d8b 5553 if (ram_offset)
5554 load_regs(regs[i].regmap,branch_regs[i].regmap,ROREG,ROREG);
ad49de89 5555 load_regs(regs[i].regmap,branch_regs[i].regmap,CCREG,INVCP);
57871462 5556 ds_assemble(i+1,&branch_regs[i]);
5557 cc=get_reg(branch_regs[i].regmap,CCREG);
5558 if(cc==-1) {
5559 emit_loadreg(CCREG,cc=HOST_CCREG);
5560 // CHECK: Is the following instruction (fall thru) allocated ok?
5561 }
5562 assert(cc==HOST_CCREG);
ad49de89 5563 store_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]);
57871462 5564 do_cc(i,i_regmap,&adj,ba[i],TAKEN,0);
5565 assem_debug("cycle count (adj)\n");
2330734f 5566 if(adj) emit_addimm(cc, ccadj[i] + CLOCK_ADJUST(2) - adj, cc);
ad49de89 5567 load_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]);
57871462 5568 if(internal)
5569 assem_debug("branch: internal\n");
5570 else
5571 assem_debug("branch: external\n");
cf95b4f0 5572 if (internal && dops[(ba[i] - start) >> 2].is_ds) {
57871462 5573 ds_assemble_entry(i);
5574 }
5575 else {
643aeae3 5576 add_to_linker(out,ba[i],internal);
57871462 5577 emit_jmp(0);
5578 }
5579 }
5580 // branch not taken
57871462 5581 if(!unconditional) {
df4dc2b1 5582 if(nottaken1) set_jump_target(nottaken1, out);
5583 set_jump_target(nottaken, out);
57871462 5584 assem_debug("2:\n");
fe807a8a 5585 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,ds_unneeded);
37387d8b 5586 // load regs
fe807a8a 5587 load_regs(regs[i].regmap,branch_regs[i].regmap,dops[i+1].rs1,dops[i+1].rs2);
5588 address_generation(i+1,&branch_regs[i],0);
37387d8b 5589 if (ram_offset)
5590 load_regs(regs[i].regmap,branch_regs[i].regmap,ROREG,ROREG);
5591 load_regs(regs[i].regmap,branch_regs[i].regmap,CCREG,INVCP);
fe807a8a 5592 ds_assemble(i+1,&branch_regs[i]);
57871462 5593 cc=get_reg(branch_regs[i].regmap,CCREG);
fe807a8a 5594 if (cc == -1) {
57871462 5595 // Cycle count isn't in a register, temporarily load it then write it out
5596 emit_loadreg(CCREG,HOST_CCREG);
2330734f 5597 emit_addimm_and_set_flags(ccadj[i] + CLOCK_ADJUST(2), HOST_CCREG);
b14b6a8f 5598 void *jaddr=out;
57871462 5599 emit_jns(0);
b14b6a8f 5600 add_stub(CC_STUB,jaddr,out,0,i,start+i*4+8,NOTTAKEN,0);
57871462 5601 emit_storereg(CCREG,HOST_CCREG);
5602 }
5603 else{
5604 cc=get_reg(i_regmap,CCREG);
5605 assert(cc==HOST_CCREG);
2330734f 5606 emit_addimm_and_set_flags(ccadj[i] + CLOCK_ADJUST(2), cc);
b14b6a8f 5607 void *jaddr=out;
57871462 5608 emit_jns(0);
fe807a8a 5609 add_stub(CC_STUB,jaddr,out,0,i,start+i*4+8,NOTTAKEN,0);
57871462 5610 }
5611 }
5612 }
5613}
5614
2330734f 5615static void sjump_assemble(int i, const struct regstat *i_regs)
57871462 5616{
2330734f 5617 const signed char *i_regmap = i_regs->regmap;
57871462 5618 int cc;
5619 int match;
ad49de89 5620 match=match_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]);
57871462 5621 assem_debug("smatch=%d\n",match);
ad49de89 5622 int s1l;
57871462 5623 int unconditional=0,nevertaken=0;
57871462 5624 int invert=0;
ad49de89 5625 int internal=internal_branch(ba[i]);
57871462 5626 if(i==(ba[i]-start)>>2) assem_debug("idle loop\n");
57871462 5627 if(!match) invert=1;
5628 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5629 if(i>(ba[i]-start)>>2) invert=1;
5630 #endif
3968e69e 5631 #ifdef __aarch64__
5632 invert=1; // because of near cond. branches
5633 #endif
57871462 5634
cf95b4f0 5635 //if(dops[i].opcode2>=0x10) return; // FIXME (BxxZAL)
5636 //assert(dops[i].opcode2<0x10||dops[i].rs1==0); // FIXME (BxxZAL)
57871462 5637
cf95b4f0 5638 if(dops[i].ooo) {
5639 s1l=get_reg(branch_regs[i].regmap,dops[i].rs1);
57871462 5640 }
5641 else {
cf95b4f0 5642 s1l=get_reg(i_regmap,dops[i].rs1);
57871462 5643 }
cf95b4f0 5644 if(dops[i].rs1==0)
57871462 5645 {
cf95b4f0 5646 if(dops[i].opcode2&1) unconditional=1;
57871462 5647 else nevertaken=1;
5648 // These are never taken (r0 is never less than zero)
cf95b4f0 5649 //assert(dops[i].opcode2!=0);
5650 //assert(dops[i].opcode2!=2);
5651 //assert(dops[i].opcode2!=0x10);
5652 //assert(dops[i].opcode2!=0x12);
57871462 5653 }
57871462 5654
cf95b4f0 5655 if(dops[i].ooo) {
57871462 5656 // Out of order execution (delay slot first)
5657 //printf("OOOE\n");
5658 address_generation(i+1,i_regs,regs[i].regmap_entry);
5659 ds_assemble(i+1,i_regs);
5660 int adj;
5661 uint64_t bc_unneeded=branch_regs[i].u;
cf95b4f0 5662 bc_unneeded&=~((1LL<<dops[i].rs1)|(1LL<<dops[i].rs2));
57871462 5663 bc_unneeded|=1;
ad49de89 5664 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,bc_unneeded);
cf95b4f0 5665 load_regs(regs[i].regmap,branch_regs[i].regmap,dops[i].rs1,dops[i].rs1);
ad49de89 5666 load_regs(regs[i].regmap,branch_regs[i].regmap,CCREG,CCREG);
cf95b4f0 5667 if(dops[i].rt1==31) {
57871462 5668 int rt,return_address;
57871462 5669 rt=get_reg(branch_regs[i].regmap,31);
5670 assem_debug("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5671 if(rt>=0) {
5672 // Save the PC even if the branch is not taken
5673 return_address=start+i*4+8;
5674 emit_movimm(return_address,rt); // PC into link register
5675 #ifdef IMM_PREFETCH
df4dc2b1 5676 if(!nevertaken) emit_prefetch(hash_table_get(return_address));
57871462 5677 #endif
5678 }
5679 }
5680 cc=get_reg(branch_regs[i].regmap,CCREG);
5681 assert(cc==HOST_CCREG);
9f51b4b9 5682 if(unconditional)
ad49de89 5683 store_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]);
57871462 5684 //do_cc(i,branch_regs[i].regmap,&adj,unconditional?ba[i]:-1,unconditional);
5685 assem_debug("cycle count (adj)\n");
5686 if(unconditional) {
5687 do_cc(i,branch_regs[i].regmap,&adj,ba[i],TAKEN,0);
5688 if(i!=(ba[i]-start)>>2 || source[i+1]!=0) {
2330734f 5689 if(adj) emit_addimm(cc, ccadj[i] + CLOCK_ADJUST(2) - adj, cc);
ad49de89 5690 load_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]);
57871462 5691 if(internal)
5692 assem_debug("branch: internal\n");
5693 else
5694 assem_debug("branch: external\n");
cf95b4f0 5695 if (internal && dops[(ba[i] - start) >> 2].is_ds) {
57871462 5696 ds_assemble_entry(i);
5697 }
5698 else {
643aeae3 5699 add_to_linker(out,ba[i],internal);
57871462 5700 emit_jmp(0);
5701 }
5702 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5703 if(((u_int)out)&7) emit_addnop(0);
5704 #endif
5705 }
5706 }
5707 else if(nevertaken) {
2330734f 5708 emit_addimm_and_set_flags(ccadj[i] + CLOCK_ADJUST(2), cc);
b14b6a8f 5709 void *jaddr=out;
57871462 5710 emit_jns(0);
b14b6a8f 5711 add_stub(CC_STUB,jaddr,out,0,i,start+i*4+8,NOTTAKEN,0);
57871462 5712 }
5713 else {
df4dc2b1 5714 void *nottaken = NULL;
57871462 5715 do_cc(i,branch_regs[i].regmap,&adj,-1,0,invert);
2330734f 5716 if(adj&&!invert) emit_addimm(cc, ccadj[i] + CLOCK_ADJUST(2) - adj, cc);
57871462 5717 {
5718 assert(s1l>=0);
cf95b4f0 5719 if((dops[i].opcode2&0xf)==0) // BLTZ/BLTZAL
57871462 5720 {
5721 emit_test(s1l,s1l);
5722 if(invert){
df4dc2b1 5723 nottaken=out;
7c3a5182 5724 emit_jns(DJT_1);
57871462 5725 }else{
643aeae3 5726 add_to_linker(out,ba[i],internal);
57871462 5727 emit_js(0);
5728 }
5729 }
cf95b4f0 5730 if((dops[i].opcode2&0xf)==1) // BGEZ/BLTZAL
57871462 5731 {
5732 emit_test(s1l,s1l);
5733 if(invert){
df4dc2b1 5734 nottaken=out;
7c3a5182 5735 emit_js(DJT_1);
57871462 5736 }else{
643aeae3 5737 add_to_linker(out,ba[i],internal);
57871462 5738 emit_jns(0);
5739 }
5740 }
ad49de89 5741 }
9f51b4b9 5742
57871462 5743 if(invert) {
5744 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
cf95b4f0 5745 if (match && (!internal || !dops[(ba[i] - start) >> 2].is_ds)) {
57871462 5746 if(adj) {
2330734f 5747 emit_addimm(cc,-adj,cc);
643aeae3 5748 add_to_linker(out,ba[i],internal);
57871462 5749 }else{
5750 emit_addnop(13);
643aeae3 5751 add_to_linker(out,ba[i],internal*2);
57871462 5752 }
5753 emit_jmp(0);
5754 }else
5755 #endif
5756 {
2330734f 5757 if(adj) emit_addimm(cc,-adj,cc);
ad49de89 5758 store_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]);
5759 load_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]);
57871462 5760 if(internal)
5761 assem_debug("branch: internal\n");
5762 else
5763 assem_debug("branch: external\n");
cf95b4f0 5764 if (internal && dops[(ba[i] - start) >> 2].is_ds) {
57871462 5765 ds_assemble_entry(i);
5766 }
5767 else {
643aeae3 5768 add_to_linker(out,ba[i],internal);
57871462 5769 emit_jmp(0);
5770 }
5771 }
df4dc2b1 5772 set_jump_target(nottaken, out);
57871462 5773 }
5774
5775 if(adj) {
2330734f 5776 if(!invert) emit_addimm(cc,adj,cc);
57871462 5777 }
5778 } // (!unconditional)
5779 } // if(ooo)
5780 else
5781 {
5782 // In-order execution (branch first)
5783 //printf("IOE\n");
df4dc2b1 5784 void *nottaken = NULL;
cf95b4f0 5785 if(dops[i].rt1==31) {
a6491170 5786 int rt,return_address;
a6491170 5787 rt=get_reg(branch_regs[i].regmap,31);
5788 if(rt>=0) {
5789 // Save the PC even if the branch is not taken
5790 return_address=start+i*4+8;
5791 emit_movimm(return_address,rt); // PC into link register
5792 #ifdef IMM_PREFETCH
df4dc2b1 5793 emit_prefetch(hash_table_get(return_address));
a6491170 5794 #endif
5795 }
5796 }
57871462 5797 if(!unconditional) {
5798 //printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
57871462 5799 assert(s1l>=0);
cf95b4f0 5800 if((dops[i].opcode2&0x0d)==0) // BLTZ/BLTZL/BLTZAL/BLTZALL
57871462 5801 {
5802 emit_test(s1l,s1l);
df4dc2b1 5803 nottaken=out;
7c3a5182 5804 emit_jns(DJT_1);
57871462 5805 }
cf95b4f0 5806 if((dops[i].opcode2&0x0d)==1) // BGEZ/BGEZL/BGEZAL/BGEZALL
57871462 5807 {
5808 emit_test(s1l,s1l);
df4dc2b1 5809 nottaken=out;
7c3a5182 5810 emit_js(DJT_1);
57871462 5811 }
57871462 5812 } // if(!unconditional)
5813 int adj;
5814 uint64_t ds_unneeded=branch_regs[i].u;
cf95b4f0 5815 ds_unneeded&=~((1LL<<dops[i+1].rs1)|(1LL<<dops[i+1].rs2));
57871462 5816 ds_unneeded|=1;
57871462 5817 // branch taken
5818 if(!nevertaken) {
5819 //assem_debug("1:\n");
ad49de89 5820 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,ds_unneeded);
57871462 5821 // load regs
cf95b4f0 5822 load_regs(regs[i].regmap,branch_regs[i].regmap,dops[i+1].rs1,dops[i+1].rs2);
57871462 5823 address_generation(i+1,&branch_regs[i],0);
37387d8b 5824 if (ram_offset)
5825 load_regs(regs[i].regmap,branch_regs[i].regmap,ROREG,ROREG);
ad49de89 5826 load_regs(regs[i].regmap,branch_regs[i].regmap,CCREG,INVCP);
57871462 5827 ds_assemble(i+1,&branch_regs[i]);
5828 cc=get_reg(branch_regs[i].regmap,CCREG);
5829 if(cc==-1) {
5830 emit_loadreg(CCREG,cc=HOST_CCREG);
5831 // CHECK: Is the following instruction (fall thru) allocated ok?
5832 }
5833 assert(cc==HOST_CCREG);
ad49de89 5834 store_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]);
57871462 5835 do_cc(i,i_regmap,&adj,ba[i],TAKEN,0);
5836 assem_debug("cycle count (adj)\n");
2330734f 5837 if(adj) emit_addimm(cc, ccadj[i] + CLOCK_ADJUST(2) - adj, cc);
ad49de89 5838 load_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]);
57871462 5839 if(internal)
5840 assem_debug("branch: internal\n");
5841 else
5842 assem_debug("branch: external\n");
cf95b4f0 5843 if (internal && dops[(ba[i] - start) >> 2].is_ds) {
57871462 5844 ds_assemble_entry(i);
5845 }
5846 else {
643aeae3 5847 add_to_linker(out,ba[i],internal);
57871462 5848 emit_jmp(0);
5849 }
5850 }
5851 // branch not taken
57871462 5852 if(!unconditional) {
df4dc2b1 5853 set_jump_target(nottaken, out);
57871462 5854 assem_debug("1:\n");
fe807a8a 5855 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,ds_unneeded);
5856 load_regs(regs[i].regmap,branch_regs[i].regmap,dops[i+1].rs1,dops[i+1].rs2);
5857 address_generation(i+1,&branch_regs[i],0);
5858 load_regs(regs[i].regmap,branch_regs[i].regmap,CCREG,CCREG);
5859 ds_assemble(i+1,&branch_regs[i]);
57871462 5860 cc=get_reg(branch_regs[i].regmap,CCREG);
fe807a8a 5861 if (cc == -1) {
57871462 5862 // Cycle count isn't in a register, temporarily load it then write it out
5863 emit_loadreg(CCREG,HOST_CCREG);
2330734f 5864 emit_addimm_and_set_flags(ccadj[i] + CLOCK_ADJUST(2), HOST_CCREG);
b14b6a8f 5865 void *jaddr=out;
57871462 5866 emit_jns(0);
b14b6a8f 5867 add_stub(CC_STUB,jaddr,out,0,i,start+i*4+8,NOTTAKEN,0);
57871462 5868 emit_storereg(CCREG,HOST_CCREG);
5869 }
5870 else{
5871 cc=get_reg(i_regmap,CCREG);
5872 assert(cc==HOST_CCREG);
2330734f 5873 emit_addimm_and_set_flags(ccadj[i] + CLOCK_ADJUST(2), cc);
b14b6a8f 5874 void *jaddr=out;
57871462 5875 emit_jns(0);
fe807a8a 5876 add_stub(CC_STUB,jaddr,out,0,i,start+i*4+8,NOTTAKEN,0);
57871462 5877 }
5878 }
5879 }
5880}
5881
2330734f 5882static void pagespan_assemble(int i, const struct regstat *i_regs)
57871462 5883{
cf95b4f0 5884 int s1l=get_reg(i_regs->regmap,dops[i].rs1);
5885 int s2l=get_reg(i_regs->regmap,dops[i].rs2);
df4dc2b1 5886 void *taken = NULL;
5887 void *nottaken = NULL;
57871462 5888 int unconditional=0;
cf95b4f0 5889 if(dops[i].rs1==0)
57871462 5890 {
ad49de89 5891 s1l=s2l;
5892 s2l=-1;
57871462 5893 }
cf95b4f0 5894 else if(dops[i].rs2==0)
57871462 5895 {
ad49de89 5896 s2l=-1;
57871462 5897 }
5898 int hr=0;
581335b0 5899 int addr=-1,alt=-1,ntaddr=-1;
57871462 5900 if(i_regs->regmap[HOST_BTREG]<0) {addr=HOST_BTREG;}
5901 else {
5902 while(hr<HOST_REGS)
5903 {
5904 if(hr!=EXCLUDE_REG && hr!=HOST_CCREG &&
cf95b4f0 5905 (i_regs->regmap[hr]&63)!=dops[i].rs1 &&
5906 (i_regs->regmap[hr]&63)!=dops[i].rs2 )
57871462 5907 {
5908 addr=hr++;break;
5909 }
5910 hr++;
5911 }
5912 }
5913 while(hr<HOST_REGS)
5914 {
5915 if(hr!=EXCLUDE_REG && hr!=HOST_CCREG && hr!=HOST_BTREG &&
cf95b4f0 5916 (i_regs->regmap[hr]&63)!=dops[i].rs1 &&
5917 (i_regs->regmap[hr]&63)!=dops[i].rs2 )
57871462 5918 {
5919 alt=hr++;break;
5920 }
5921 hr++;
5922 }
cf95b4f0 5923 if((dops[i].opcode&0x2E)==6) // BLEZ/BGTZ needs another register
57871462 5924 {
5925 while(hr<HOST_REGS)
5926 {
5927 if(hr!=EXCLUDE_REG && hr!=HOST_CCREG && hr!=HOST_BTREG &&
cf95b4f0 5928 (i_regs->regmap[hr]&63)!=dops[i].rs1 &&
5929 (i_regs->regmap[hr]&63)!=dops[i].rs2 )
57871462 5930 {
5931 ntaddr=hr;break;
5932 }
5933 hr++;
5934 }
5935 }
5936 assert(hr<HOST_REGS);
cf95b4f0 5937 if((dops[i].opcode&0x2e)==4||dops[i].opcode==0x11) { // BEQ/BNE/BEQL/BNEL/BC1
ad49de89 5938 load_regs(regs[i].regmap_entry,regs[i].regmap,CCREG,CCREG);
57871462 5939 }
2330734f 5940 emit_addimm(HOST_CCREG, ccadj[i] + CLOCK_ADJUST(2), HOST_CCREG);
cf95b4f0 5941 if(dops[i].opcode==2) // J
57871462 5942 {
5943 unconditional=1;
5944 }
cf95b4f0 5945 if(dops[i].opcode==3) // JAL
57871462 5946 {
5947 // TODO: mini_ht
5948 int rt=get_reg(i_regs->regmap,31);
5949 emit_movimm(start+i*4+8,rt);
5950 unconditional=1;
5951 }
cf95b4f0 5952 if(dops[i].opcode==0&&(dops[i].opcode2&0x3E)==8) // JR/JALR
57871462 5953 {
5954 emit_mov(s1l,addr);
cf95b4f0 5955 if(dops[i].opcode2==9) // JALR
57871462 5956 {
cf95b4f0 5957 int rt=get_reg(i_regs->regmap,dops[i].rt1);
57871462 5958 emit_movimm(start+i*4+8,rt);
5959 }
5960 }
cf95b4f0 5961 if((dops[i].opcode&0x3f)==4) // BEQ
57871462 5962 {
cf95b4f0 5963 if(dops[i].rs1==dops[i].rs2)
57871462 5964 {
5965 unconditional=1;
5966 }
5967 else
5968 #ifdef HAVE_CMOV_IMM
ad49de89 5969 if(1) {
57871462 5970 if(s2l>=0) emit_cmp(s1l,s2l);
5971 else emit_test(s1l,s1l);
5972 emit_cmov2imm_e_ne_compact(ba[i],start+i*4+8,addr);
5973 }
5974 else
5975 #endif
5976 {
5977 assert(s1l>=0);
5978 emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
57871462 5979 if(s2l>=0) emit_cmp(s1l,s2l);
5980 else emit_test(s1l,s1l);
5981 emit_cmovne_reg(alt,addr);
5982 }
5983 }
cf95b4f0 5984 if((dops[i].opcode&0x3f)==5) // BNE
57871462 5985 {
5986 #ifdef HAVE_CMOV_IMM
ad49de89 5987 if(s2l>=0) emit_cmp(s1l,s2l);
5988 else emit_test(s1l,s1l);
5989 emit_cmov2imm_e_ne_compact(start+i*4+8,ba[i],addr);
5990 #else
5991 assert(s1l>=0);
5992 emit_mov2imm_compact(start+i*4+8,addr,ba[i],alt);
5993 if(s2l>=0) emit_cmp(s1l,s2l);
5994 else emit_test(s1l,s1l);
5995 emit_cmovne_reg(alt,addr);
57871462 5996 #endif
57871462 5997 }
cf95b4f0 5998 if((dops[i].opcode&0x3f)==0x14) // BEQL
57871462 5999 {
57871462 6000 if(s2l>=0) emit_cmp(s1l,s2l);
6001 else emit_test(s1l,s1l);
df4dc2b1 6002 if(nottaken) set_jump_target(nottaken, out);
6003 nottaken=out;
57871462 6004 emit_jne(0);
6005 }
cf95b4f0 6006 if((dops[i].opcode&0x3f)==0x15) // BNEL
57871462 6007 {
57871462 6008 if(s2l>=0) emit_cmp(s1l,s2l);
6009 else emit_test(s1l,s1l);
df4dc2b1 6010 nottaken=out;
57871462 6011 emit_jeq(0);
df4dc2b1 6012 if(taken) set_jump_target(taken, out);
57871462 6013 }
cf95b4f0 6014 if((dops[i].opcode&0x3f)==6) // BLEZ
57871462 6015 {
6016 emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
6017 emit_cmpimm(s1l,1);
57871462 6018 emit_cmovl_reg(alt,addr);
57871462 6019 }
cf95b4f0 6020 if((dops[i].opcode&0x3f)==7) // BGTZ
57871462 6021 {
6022 emit_mov2imm_compact(ba[i],addr,start+i*4+8,ntaddr);
6023 emit_cmpimm(s1l,1);
57871462 6024 emit_cmovl_reg(ntaddr,addr);
57871462 6025 }
cf95b4f0 6026 if((dops[i].opcode&0x3f)==0x16) // BLEZL
57871462 6027 {
cf95b4f0 6028 assert((dops[i].opcode&0x3f)!=0x16);
57871462 6029 }
cf95b4f0 6030 if((dops[i].opcode&0x3f)==0x17) // BGTZL
57871462 6031 {
cf95b4f0 6032 assert((dops[i].opcode&0x3f)!=0x17);
57871462 6033 }
cf95b4f0 6034 assert(dops[i].opcode!=1); // BLTZ/BGEZ
57871462 6035
6036 //FIXME: Check CSREG
cf95b4f0 6037 if(dops[i].opcode==0x11 && dops[i].opcode2==0x08 ) {
57871462 6038 if((source[i]&0x30000)==0) // BC1F
6039 {
6040 emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
6041 emit_testimm(s1l,0x800000);
6042 emit_cmovne_reg(alt,addr);
6043 }
6044 if((source[i]&0x30000)==0x10000) // BC1T
6045 {
6046 emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
6047 emit_testimm(s1l,0x800000);
6048 emit_cmovne_reg(alt,addr);
6049 }
6050 if((source[i]&0x30000)==0x20000) // BC1FL
6051 {
6052 emit_testimm(s1l,0x800000);
df4dc2b1 6053 nottaken=out;
57871462 6054 emit_jne(0);
6055 }
6056 if((source[i]&0x30000)==0x30000) // BC1TL
6057 {
6058 emit_testimm(s1l,0x800000);
df4dc2b1 6059 nottaken=out;
57871462 6060 emit_jeq(0);
6061 }
6062 }
6063
6064 assert(i_regs->regmap[HOST_CCREG]==CCREG);
ad49de89 6065 wb_dirtys(regs[i].regmap,regs[i].dirty);
fe807a8a 6066 if(unconditional)
57871462 6067 {
6068 emit_movimm(ba[i],HOST_BTREG);
6069 }
6070 else if(addr!=HOST_BTREG)
6071 {
6072 emit_mov(addr,HOST_BTREG);
6073 }
6074 void *branch_addr=out;
6075 emit_jmp(0);
6076 int target_addr=start+i*4+5;
6077 void *stub=out;
6078 void *compiled_target_addr=check_addr(target_addr);
643aeae3 6079 emit_extjump_ds(branch_addr, target_addr);
57871462 6080 if(compiled_target_addr) {
df4dc2b1 6081 set_jump_target(branch_addr, compiled_target_addr);
3d680478 6082 add_jump_out(target_addr,stub);
57871462 6083 }
df4dc2b1 6084 else set_jump_target(branch_addr, stub);
57871462 6085}
6086
6087// Assemble the delay slot for the above
6088static void pagespan_ds()
6089{
6090 assem_debug("initial delay slot:\n");
6091 u_int vaddr=start+1;
94d23bb9 6092 u_int page=get_page(vaddr);
6093 u_int vpage=get_vpage(vaddr);
57871462 6094 ll_add(jump_dirty+vpage,vaddr,(void *)out);
3d680478 6095 do_dirty_stub_ds(slen*4);
57871462 6096 ll_add(jump_in+page,vaddr,(void *)out);
6097 assert(regs[0].regmap_entry[HOST_CCREG]==CCREG);
6098 if(regs[0].regmap[HOST_CCREG]!=CCREG)
ad49de89 6099 wb_register(CCREG,regs[0].regmap_entry,regs[0].wasdirty);
57871462 6100 if(regs[0].regmap[HOST_BTREG]!=BTREG)
643aeae3 6101 emit_writeword(HOST_BTREG,&branch_target);
cf95b4f0 6102 load_regs(regs[0].regmap_entry,regs[0].regmap,dops[0].rs1,dops[0].rs2);
57871462 6103 address_generation(0,&regs[0],regs[0].regmap_entry);
37387d8b 6104 if (ram_offset && (dops[0].is_load || dops[0].is_store))
6105 load_regs(regs[0].regmap_entry,regs[0].regmap,ROREG,ROREG);
6106 if (dops[0].is_store)
ad49de89 6107 load_regs(regs[0].regmap_entry,regs[0].regmap,INVCP,INVCP);
57871462 6108 is_delayslot=0;
2330734f 6109 switch (dops[0].itype) {
57871462 6110 case SYSCALL:
7139f3c8 6111 case HLECALL:
1e973cb0 6112 case INTCALL:
57871462 6113 case SPAN:
6114 case UJUMP:
6115 case RJUMP:
6116 case CJUMP:
6117 case SJUMP:
c43b5311 6118 SysPrintf("Jump in the delay slot. This is probably a bug.\n");
2330734f 6119 break;
6120 default:
6121 assemble(0, &regs[0], 0);
57871462 6122 }
6123 int btaddr=get_reg(regs[0].regmap,BTREG);
6124 if(btaddr<0) {
6125 btaddr=get_reg(regs[0].regmap,-1);
643aeae3 6126 emit_readword(&branch_target,btaddr);
57871462 6127 }
6128 assert(btaddr!=HOST_CCREG);
6129 if(regs[0].regmap[HOST_CCREG]!=CCREG) emit_loadreg(CCREG,HOST_CCREG);
6130#ifdef HOST_IMM8
d1e4ebd9 6131 host_tempreg_acquire();
57871462 6132 emit_movimm(start+4,HOST_TEMPREG);
6133 emit_cmp(btaddr,HOST_TEMPREG);
d1e4ebd9 6134 host_tempreg_release();
57871462 6135#else
6136 emit_cmpimm(btaddr,start+4);
6137#endif
df4dc2b1 6138 void *branch = out;
57871462 6139 emit_jeq(0);
ad49de89 6140 store_regs_bt(regs[0].regmap,regs[0].dirty,-1);
d1e4ebd9 6141 do_jump_vaddr(btaddr);
df4dc2b1 6142 set_jump_target(branch, out);
ad49de89 6143 store_regs_bt(regs[0].regmap,regs[0].dirty,start+4);
6144 load_regs_bt(regs[0].regmap,regs[0].dirty,start+4);
57871462 6145}
6146
670c0f22 6147static void check_regmap(signed char *regmap)
6148{
6149#ifndef NDEBUG
6150 int i,j;
6151 for (i = 0; i < HOST_REGS; i++) {
6152 if (regmap[i] < 0)
6153 continue;
6154 for (j = i + 1; j < HOST_REGS; j++)
6155 assert(regmap[i] != regmap[j]);
6156 }
6157#endif
6158}
6159
57871462 6160// Basic liveness analysis for MIPS registers
670c0f22 6161static void unneeded_registers(int istart,int iend,int r)
57871462 6162{
6163 int i;
00fa9369 6164 uint64_t u,gte_u,b,gte_b;
6165 uint64_t temp_u,temp_gte_u=0;
0ff8c62c 6166 uint64_t gte_u_unknown=0;
d62c125a 6167 if (HACK_ENABLED(NDHACK_GTE_UNNEEDED))
0ff8c62c 6168 gte_u_unknown=~0ll;
57871462 6169 if(iend==slen-1) {
00fa9369 6170 u=1;
0ff8c62c 6171 gte_u=gte_u_unknown;
57871462 6172 }else{
00fa9369 6173 //u=unneeded_reg[iend+1];
6174 u=1;
0ff8c62c 6175 gte_u=gte_unneeded[iend+1];
57871462 6176 }
bedfea38 6177
57871462 6178 for (i=iend;i>=istart;i--)
6179 {
6180 //printf("unneeded registers i=%d (%d,%d) r=%d\n",i,istart,iend,r);
fe807a8a 6181 if(dops[i].is_jump)
57871462 6182 {
6183 // If subroutine call, flag return address as a possible branch target
cf95b4f0 6184 if(dops[i].rt1==31 && i<slen-2) dops[i+2].bt=1;
9f51b4b9 6185
57871462 6186 if(ba[i]<start || ba[i]>=(start+slen*4))
6187 {
6188 // Branch out of this block, flush all regs
6189 u=1;
0ff8c62c 6190 gte_u=gte_u_unknown;
57871462 6191 branch_unneeded_reg[i]=u;
57871462 6192 // Merge in delay slot
cf95b4f0 6193 u|=(1LL<<dops[i+1].rt1)|(1LL<<dops[i+1].rt2);
6194 u&=~((1LL<<dops[i+1].rs1)|(1LL<<dops[i+1].rs2));
00fa9369 6195 u|=1;
bedfea38 6196 gte_u|=gte_rt[i+1];
6197 gte_u&=~gte_rs[i+1];
57871462 6198 }
6199 else
6200 {
6201 // Internal branch, flag target
cf95b4f0 6202 dops[(ba[i]-start)>>2].bt=1;
57871462 6203 if(ba[i]<=start+i*4) {
6204 // Backward branch
fe807a8a 6205 if(dops[i].is_ujump)
57871462 6206 {
6207 // Unconditional branch
00fa9369 6208 temp_u=1;
bedfea38 6209 temp_gte_u=0;
57871462 6210 } else {
6211 // Conditional branch (not taken case)
6212 temp_u=unneeded_reg[i+2];
bedfea38 6213 temp_gte_u&=gte_unneeded[i+2];
57871462 6214 }
6215 // Merge in delay slot
cf95b4f0 6216 temp_u|=(1LL<<dops[i+1].rt1)|(1LL<<dops[i+1].rt2);
6217 temp_u&=~((1LL<<dops[i+1].rs1)|(1LL<<dops[i+1].rs2));
00fa9369 6218 temp_u|=1;
bedfea38 6219 temp_gte_u|=gte_rt[i+1];
6220 temp_gte_u&=~gte_rs[i+1];
cf95b4f0 6221 temp_u|=(1LL<<dops[i].rt1)|(1LL<<dops[i].rt2);
6222 temp_u&=~((1LL<<dops[i].rs1)|(1LL<<dops[i].rs2));
00fa9369 6223 temp_u|=1;
bedfea38 6224 temp_gte_u|=gte_rt[i];
6225 temp_gte_u&=~gte_rs[i];
57871462 6226 unneeded_reg[i]=temp_u;
bedfea38 6227 gte_unneeded[i]=temp_gte_u;
57871462 6228 // Only go three levels deep. This recursion can take an
6229 // excessive amount of time if there are a lot of nested loops.
6230 if(r<2) {
6231 unneeded_registers((ba[i]-start)>>2,i-1,r+1);
6232 }else{
6233 unneeded_reg[(ba[i]-start)>>2]=1;
0ff8c62c 6234 gte_unneeded[(ba[i]-start)>>2]=gte_u_unknown;
57871462 6235 }
6236 } /*else*/ if(1) {
fe807a8a 6237 if (dops[i].is_ujump)
57871462 6238 {
6239 // Unconditional branch
6240 u=unneeded_reg[(ba[i]-start)>>2];
bedfea38 6241 gte_u=gte_unneeded[(ba[i]-start)>>2];
57871462 6242 branch_unneeded_reg[i]=u;
57871462 6243 // Merge in delay slot
cf95b4f0 6244 u|=(1LL<<dops[i+1].rt1)|(1LL<<dops[i+1].rt2);
6245 u&=~((1LL<<dops[i+1].rs1)|(1LL<<dops[i+1].rs2));
00fa9369 6246 u|=1;
bedfea38 6247 gte_u|=gte_rt[i+1];
6248 gte_u&=~gte_rs[i+1];
57871462 6249 } else {
6250 // Conditional branch
6251 b=unneeded_reg[(ba[i]-start)>>2];
00fa9369 6252 gte_b=gte_unneeded[(ba[i]-start)>>2];
57871462 6253 branch_unneeded_reg[i]=b;
57871462 6254 // Branch delay slot
cf95b4f0 6255 b|=(1LL<<dops[i+1].rt1)|(1LL<<dops[i+1].rt2);
6256 b&=~((1LL<<dops[i+1].rs1)|(1LL<<dops[i+1].rs2));
00fa9369 6257 b|=1;
6258 gte_b|=gte_rt[i+1];
6259 gte_b&=~gte_rs[i+1];
fe807a8a 6260 u&=b;
6261 gte_u&=gte_b;
57871462 6262 if(i<slen-1) {
6263 branch_unneeded_reg[i]&=unneeded_reg[i+2];
57871462 6264 } else {
6265 branch_unneeded_reg[i]=1;
57871462 6266 }
6267 }
6268 }
6269 }
6270 }
cf95b4f0 6271 else if(dops[i].itype==SYSCALL||dops[i].itype==HLECALL||dops[i].itype==INTCALL)
57871462 6272 {
6273 // SYSCALL instruction (software interrupt)
6274 u=1;
57871462 6275 }
cf95b4f0 6276 else if(dops[i].itype==COP0 && (source[i]&0x3f)==0x18)
57871462 6277 {
6278 // ERET instruction (return from interrupt)
6279 u=1;
57871462 6280 }
00fa9369 6281 //u=1; // DEBUG
57871462 6282 // Written registers are unneeded
cf95b4f0 6283 u|=1LL<<dops[i].rt1;
6284 u|=1LL<<dops[i].rt2;
bedfea38 6285 gte_u|=gte_rt[i];
57871462 6286 // Accessed registers are needed
cf95b4f0 6287 u&=~(1LL<<dops[i].rs1);
6288 u&=~(1LL<<dops[i].rs2);
bedfea38 6289 gte_u&=~gte_rs[i];
cf95b4f0 6290 if(gte_rs[i]&&dops[i].rt1&&(unneeded_reg[i+1]&(1ll<<dops[i].rt1)))
cbbd8dd7 6291 gte_u|=gte_rs[i]&gte_unneeded[i+1]; // MFC2/CFC2 to dead register, unneeded
57871462 6292 // Source-target dependencies
57871462 6293 // R0 is always unneeded
00fa9369 6294 u|=1;
57871462 6295 // Save it
6296 unneeded_reg[i]=u;
bedfea38 6297 gte_unneeded[i]=gte_u;
57871462 6298 /*
6299 printf("ur (%d,%d) %x: ",istart,iend,start+i*4);
6300 printf("U:");
6301 int r;
6302 for(r=1;r<=CCREG;r++) {
6303 if((unneeded_reg[i]>>r)&1) {
6304 if(r==HIREG) printf(" HI");
6305 else if(r==LOREG) printf(" LO");
6306 else printf(" r%d",r);
6307 }
6308 }
00fa9369 6309 printf("\n");
6310 */
252c20fc 6311 }
57871462 6312}
6313
71e490c5 6314// Write back dirty registers as soon as we will no longer modify them,
6315// so that we don't end up with lots of writes at the branches.
6316void clean_registers(int istart,int iend,int wr)
57871462 6317{
71e490c5 6318 int i;
6319 int r;
6320 u_int will_dirty_i,will_dirty_next,temp_will_dirty;
6321 u_int wont_dirty_i,wont_dirty_next,temp_wont_dirty;
6322 if(iend==slen-1) {
6323 will_dirty_i=will_dirty_next=0;
6324 wont_dirty_i=wont_dirty_next=0;
6325 }else{
6326 will_dirty_i=will_dirty_next=will_dirty[iend+1];
6327 wont_dirty_i=wont_dirty_next=wont_dirty[iend+1];
6328 }
6329 for (i=iend;i>=istart;i--)
57871462 6330 {
fe807a8a 6331 if(dops[i].is_jump)
57871462 6332 {
71e490c5 6333 if(ba[i]<start || ba[i]>=(start+slen*4))
57871462 6334 {
71e490c5 6335 // Branch out of this block, flush all regs
fe807a8a 6336 if (dops[i].is_ujump)
57871462 6337 {
6338 // Unconditional branch
6339 will_dirty_i=0;
6340 wont_dirty_i=0;
6341 // Merge in delay slot (will dirty)
6342 for(r=0;r<HOST_REGS;r++) {
6343 if(r!=EXCLUDE_REG) {
cf95b4f0 6344 if((branch_regs[i].regmap[r]&63)==dops[i].rt1) will_dirty_i|=1<<r;
6345 if((branch_regs[i].regmap[r]&63)==dops[i].rt2) will_dirty_i|=1<<r;
6346 if((branch_regs[i].regmap[r]&63)==dops[i+1].rt1) will_dirty_i|=1<<r;
6347 if((branch_regs[i].regmap[r]&63)==dops[i+1].rt2) will_dirty_i|=1<<r;
57871462 6348 if((branch_regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
6349 if(branch_regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
6350 if(branch_regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
cf95b4f0 6351 if((regs[i].regmap[r]&63)==dops[i].rt1) will_dirty_i|=1<<r;
6352 if((regs[i].regmap[r]&63)==dops[i].rt2) will_dirty_i|=1<<r;
6353 if((regs[i].regmap[r]&63)==dops[i+1].rt1) will_dirty_i|=1<<r;
6354 if((regs[i].regmap[r]&63)==dops[i+1].rt2) will_dirty_i|=1<<r;
57871462 6355 if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
6356 if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
6357 if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
6358 }
6359 }
6360 }
6361 else
6362 {
6363 // Conditional branch
6364 will_dirty_i=0;
6365 wont_dirty_i=wont_dirty_next;
6366 // Merge in delay slot (will dirty)
6367 for(r=0;r<HOST_REGS;r++) {
6368 if(r!=EXCLUDE_REG) {
fe807a8a 6369 if (1) { // !dops[i].likely) {
57871462 6370 // Might not dirty if likely branch is not taken
cf95b4f0 6371 if((branch_regs[i].regmap[r]&63)==dops[i].rt1) will_dirty_i|=1<<r;
6372 if((branch_regs[i].regmap[r]&63)==dops[i].rt2) will_dirty_i|=1<<r;
6373 if((branch_regs[i].regmap[r]&63)==dops[i+1].rt1) will_dirty_i|=1<<r;
6374 if((branch_regs[i].regmap[r]&63)==dops[i+1].rt2) will_dirty_i|=1<<r;
57871462 6375 if((branch_regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
6376 if(branch_regs[i].regmap[r]==0) will_dirty_i&=~(1<<r);
6377 if(branch_regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
cf95b4f0 6378 //if((regs[i].regmap[r]&63)==dops[i].rt1) will_dirty_i|=1<<r;
6379 //if((regs[i].regmap[r]&63)==dops[i].rt2) will_dirty_i|=1<<r;
6380 if((regs[i].regmap[r]&63)==dops[i+1].rt1) will_dirty_i|=1<<r;
6381 if((regs[i].regmap[r]&63)==dops[i+1].rt2) will_dirty_i|=1<<r;
57871462 6382 if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
6383 if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
6384 if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
6385 }
6386 }
6387 }
6388 }
6389 // Merge in delay slot (wont dirty)
6390 for(r=0;r<HOST_REGS;r++) {
6391 if(r!=EXCLUDE_REG) {
cf95b4f0 6392 if((regs[i].regmap[r]&63)==dops[i].rt1) wont_dirty_i|=1<<r;
6393 if((regs[i].regmap[r]&63)==dops[i].rt2) wont_dirty_i|=1<<r;
6394 if((regs[i].regmap[r]&63)==dops[i+1].rt1) wont_dirty_i|=1<<r;
6395 if((regs[i].regmap[r]&63)==dops[i+1].rt2) wont_dirty_i|=1<<r;
57871462 6396 if(regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
cf95b4f0 6397 if((branch_regs[i].regmap[r]&63)==dops[i].rt1) wont_dirty_i|=1<<r;
6398 if((branch_regs[i].regmap[r]&63)==dops[i].rt2) wont_dirty_i|=1<<r;
6399 if((branch_regs[i].regmap[r]&63)==dops[i+1].rt1) wont_dirty_i|=1<<r;
6400 if((branch_regs[i].regmap[r]&63)==dops[i+1].rt2) wont_dirty_i|=1<<r;
57871462 6401 if(branch_regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
6402 }
6403 }
6404 if(wr) {
6405 #ifndef DESTRUCTIVE_WRITEBACK
6406 branch_regs[i].dirty&=wont_dirty_i;
6407 #endif
6408 branch_regs[i].dirty|=will_dirty_i;
6409 }
6410 }
6411 else
6412 {
6413 // Internal branch
6414 if(ba[i]<=start+i*4) {
6415 // Backward branch
fe807a8a 6416 if (dops[i].is_ujump)
57871462 6417 {
6418 // Unconditional branch
6419 temp_will_dirty=0;
6420 temp_wont_dirty=0;
6421 // Merge in delay slot (will dirty)
6422 for(r=0;r<HOST_REGS;r++) {
6423 if(r!=EXCLUDE_REG) {
cf95b4f0 6424 if((branch_regs[i].regmap[r]&63)==dops[i].rt1) temp_will_dirty|=1<<r;
6425 if((branch_regs[i].regmap[r]&63)==dops[i].rt2) temp_will_dirty|=1<<r;
6426 if((branch_regs[i].regmap[r]&63)==dops[i+1].rt1) temp_will_dirty|=1<<r;
6427 if((branch_regs[i].regmap[r]&63)==dops[i+1].rt2) temp_will_dirty|=1<<r;
57871462 6428 if((branch_regs[i].regmap[r]&63)>33) temp_will_dirty&=~(1<<r);
6429 if(branch_regs[i].regmap[r]<=0) temp_will_dirty&=~(1<<r);
6430 if(branch_regs[i].regmap[r]==CCREG) temp_will_dirty|=1<<r;
cf95b4f0 6431 if((regs[i].regmap[r]&63)==dops[i].rt1) temp_will_dirty|=1<<r;
6432 if((regs[i].regmap[r]&63)==dops[i].rt2) temp_will_dirty|=1<<r;
6433 if((regs[i].regmap[r]&63)==dops[i+1].rt1) temp_will_dirty|=1<<r;
6434 if((regs[i].regmap[r]&63)==dops[i+1].rt2) temp_will_dirty|=1<<r;
57871462 6435 if((regs[i].regmap[r]&63)>33) temp_will_dirty&=~(1<<r);
6436 if(regs[i].regmap[r]<=0) temp_will_dirty&=~(1<<r);
6437 if(regs[i].regmap[r]==CCREG) temp_will_dirty|=1<<r;
6438 }
6439 }
6440 } else {
6441 // Conditional branch (not taken case)
6442 temp_will_dirty=will_dirty_next;
6443 temp_wont_dirty=wont_dirty_next;
6444 // Merge in delay slot (will dirty)
6445 for(r=0;r<HOST_REGS;r++) {
6446 if(r!=EXCLUDE_REG) {
fe807a8a 6447 if (1) { // !dops[i].likely) {
57871462 6448 // Will not dirty if likely branch is not taken
cf95b4f0 6449 if((branch_regs[i].regmap[r]&63)==dops[i].rt1) temp_will_dirty|=1<<r;
6450 if((branch_regs[i].regmap[r]&63)==dops[i].rt2) temp_will_dirty|=1<<r;
6451 if((branch_regs[i].regmap[r]&63)==dops[i+1].rt1) temp_will_dirty|=1<<r;
6452 if((branch_regs[i].regmap[r]&63)==dops[i+1].rt2) temp_will_dirty|=1<<r;
57871462 6453 if((branch_regs[i].regmap[r]&63)>33) temp_will_dirty&=~(1<<r);
6454 if(branch_regs[i].regmap[r]==0) temp_will_dirty&=~(1<<r);
6455 if(branch_regs[i].regmap[r]==CCREG) temp_will_dirty|=1<<r;
cf95b4f0 6456 //if((regs[i].regmap[r]&63)==dops[i].rt1) temp_will_dirty|=1<<r;
6457 //if((regs[i].regmap[r]&63)==dops[i].rt2) temp_will_dirty|=1<<r;
6458 if((regs[i].regmap[r]&63)==dops[i+1].rt1) temp_will_dirty|=1<<r;
6459 if((regs[i].regmap[r]&63)==dops[i+1].rt2) temp_will_dirty|=1<<r;
57871462 6460 if((regs[i].regmap[r]&63)>33) temp_will_dirty&=~(1<<r);
6461 if(regs[i].regmap[r]<=0) temp_will_dirty&=~(1<<r);
6462 if(regs[i].regmap[r]==CCREG) temp_will_dirty|=1<<r;
6463 }
6464 }
6465 }
6466 }
6467 // Merge in delay slot (wont dirty)
6468 for(r=0;r<HOST_REGS;r++) {
6469 if(r!=EXCLUDE_REG) {
cf95b4f0 6470 if((regs[i].regmap[r]&63)==dops[i].rt1) temp_wont_dirty|=1<<r;
6471 if((regs[i].regmap[r]&63)==dops[i].rt2) temp_wont_dirty|=1<<r;
6472 if((regs[i].regmap[r]&63)==dops[i+1].rt1) temp_wont_dirty|=1<<r;
6473 if((regs[i].regmap[r]&63)==dops[i+1].rt2) temp_wont_dirty|=1<<r;
57871462 6474 if(regs[i].regmap[r]==CCREG) temp_wont_dirty|=1<<r;
cf95b4f0 6475 if((branch_regs[i].regmap[r]&63)==dops[i].rt1) temp_wont_dirty|=1<<r;
6476 if((branch_regs[i].regmap[r]&63)==dops[i].rt2) temp_wont_dirty|=1<<r;
6477 if((branch_regs[i].regmap[r]&63)==dops[i+1].rt1) temp_wont_dirty|=1<<r;
6478 if((branch_regs[i].regmap[r]&63)==dops[i+1].rt2) temp_wont_dirty|=1<<r;
57871462 6479 if(branch_regs[i].regmap[r]==CCREG) temp_wont_dirty|=1<<r;
6480 }
6481 }
6482 // Deal with changed mappings
6483 if(i<iend) {
6484 for(r=0;r<HOST_REGS;r++) {
6485 if(r!=EXCLUDE_REG) {
6486 if(regs[i].regmap[r]!=regmap_pre[i][r]) {
6487 temp_will_dirty&=~(1<<r);
6488 temp_wont_dirty&=~(1<<r);
6489 if((regmap_pre[i][r]&63)>0 && (regmap_pre[i][r]&63)<34) {
6490 temp_will_dirty|=((unneeded_reg[i]>>(regmap_pre[i][r]&63))&1)<<r;
6491 temp_wont_dirty|=((unneeded_reg[i]>>(regmap_pre[i][r]&63))&1)<<r;
6492 } else {
6493 temp_will_dirty|=1<<r;
6494 temp_wont_dirty|=1<<r;
6495 }
6496 }
6497 }
6498 }
6499 }
6500 if(wr) {
6501 will_dirty[i]=temp_will_dirty;
6502 wont_dirty[i]=temp_wont_dirty;
6503 clean_registers((ba[i]-start)>>2,i-1,0);
6504 }else{
6505 // Limit recursion. It can take an excessive amount
6506 // of time if there are a lot of nested loops.
6507 will_dirty[(ba[i]-start)>>2]=0;
6508 wont_dirty[(ba[i]-start)>>2]=-1;
6509 }
6510 }
6511 /*else*/ if(1)
6512 {
fe807a8a 6513 if (dops[i].is_ujump)
57871462 6514 {
6515 // Unconditional branch
6516 will_dirty_i=0;
6517 wont_dirty_i=0;
6518 //if(ba[i]>start+i*4) { // Disable recursion (for debugging)
6519 for(r=0;r<HOST_REGS;r++) {
6520 if(r!=EXCLUDE_REG) {
6521 if(branch_regs[i].regmap[r]==regs[(ba[i]-start)>>2].regmap_entry[r]) {
6522 will_dirty_i|=will_dirty[(ba[i]-start)>>2]&(1<<r);
6523 wont_dirty_i|=wont_dirty[(ba[i]-start)>>2]&(1<<r);
6524 }
e3234ecf 6525 if(branch_regs[i].regmap[r]>=0) {
6526 will_dirty_i|=((unneeded_reg[(ba[i]-start)>>2]>>(branch_regs[i].regmap[r]&63))&1)<<r;
6527 wont_dirty_i|=((unneeded_reg[(ba[i]-start)>>2]>>(branch_regs[i].regmap[r]&63))&1)<<r;
6528 }
57871462 6529 }
6530 }
6531 //}
6532 // Merge in delay slot
6533 for(r=0;r<HOST_REGS;r++) {
6534 if(r!=EXCLUDE_REG) {
cf95b4f0 6535 if((branch_regs[i].regmap[r]&63)==dops[i].rt1) will_dirty_i|=1<<r;
6536 if((branch_regs[i].regmap[r]&63)==dops[i].rt2) will_dirty_i|=1<<r;
6537 if((branch_regs[i].regmap[r]&63)==dops[i+1].rt1) will_dirty_i|=1<<r;
6538 if((branch_regs[i].regmap[r]&63)==dops[i+1].rt2) will_dirty_i|=1<<r;
57871462 6539 if((branch_regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
6540 if(branch_regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
6541 if(branch_regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
cf95b4f0 6542 if((regs[i].regmap[r]&63)==dops[i].rt1) will_dirty_i|=1<<r;
6543 if((regs[i].regmap[r]&63)==dops[i].rt2) will_dirty_i|=1<<r;
6544 if((regs[i].regmap[r]&63)==dops[i+1].rt1) will_dirty_i|=1<<r;
6545 if((regs[i].regmap[r]&63)==dops[i+1].rt2) will_dirty_i|=1<<r;
57871462 6546 if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
6547 if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
6548 if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
6549 }
6550 }
6551 } else {
6552 // Conditional branch
6553 will_dirty_i=will_dirty_next;
6554 wont_dirty_i=wont_dirty_next;
6555 //if(ba[i]>start+i*4) { // Disable recursion (for debugging)
6556 for(r=0;r<HOST_REGS;r++) {
6557 if(r!=EXCLUDE_REG) {
e3234ecf 6558 signed char target_reg=branch_regs[i].regmap[r];
6559 if(target_reg==regs[(ba[i]-start)>>2].regmap_entry[r]) {
57871462 6560 will_dirty_i&=will_dirty[(ba[i]-start)>>2]&(1<<r);
6561 wont_dirty_i|=wont_dirty[(ba[i]-start)>>2]&(1<<r);
6562 }
e3234ecf 6563 else if(target_reg>=0) {
6564 will_dirty_i&=((unneeded_reg[(ba[i]-start)>>2]>>(target_reg&63))&1)<<r;
6565 wont_dirty_i|=((unneeded_reg[(ba[i]-start)>>2]>>(target_reg&63))&1)<<r;
57871462 6566 }
57871462 6567 }
6568 }
6569 //}
6570 // Merge in delay slot
6571 for(r=0;r<HOST_REGS;r++) {
6572 if(r!=EXCLUDE_REG) {
fe807a8a 6573 if (1) { // !dops[i].likely) {
57871462 6574 // Might not dirty if likely branch is not taken
cf95b4f0 6575 if((branch_regs[i].regmap[r]&63)==dops[i].rt1) will_dirty_i|=1<<r;
6576 if((branch_regs[i].regmap[r]&63)==dops[i].rt2) will_dirty_i|=1<<r;
6577 if((branch_regs[i].regmap[r]&63)==dops[i+1].rt1) will_dirty_i|=1<<r;
6578 if((branch_regs[i].regmap[r]&63)==dops[i+1].rt2) will_dirty_i|=1<<r;
57871462 6579 if((branch_regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
6580 if(branch_regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
6581 if(branch_regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
cf95b4f0 6582 //if((regs[i].regmap[r]&63)==dops[i].rt1) will_dirty_i|=1<<r;
6583 //if((regs[i].regmap[r]&63)==dops[i].rt2) will_dirty_i|=1<<r;
6584 if((regs[i].regmap[r]&63)==dops[i+1].rt1) will_dirty_i|=1<<r;
6585 if((regs[i].regmap[r]&63)==dops[i+1].rt2) will_dirty_i|=1<<r;
57871462 6586 if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
6587 if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
6588 if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
6589 }
6590 }
6591 }
6592 }
e3234ecf 6593 // Merge in delay slot (won't dirty)
57871462 6594 for(r=0;r<HOST_REGS;r++) {
6595 if(r!=EXCLUDE_REG) {
cf95b4f0 6596 if((regs[i].regmap[r]&63)==dops[i].rt1) wont_dirty_i|=1<<r;
6597 if((regs[i].regmap[r]&63)==dops[i].rt2) wont_dirty_i|=1<<r;
6598 if((regs[i].regmap[r]&63)==dops[i+1].rt1) wont_dirty_i|=1<<r;
6599 if((regs[i].regmap[r]&63)==dops[i+1].rt2) wont_dirty_i|=1<<r;
57871462 6600 if(regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
cf95b4f0 6601 if((branch_regs[i].regmap[r]&63)==dops[i].rt1) wont_dirty_i|=1<<r;
6602 if((branch_regs[i].regmap[r]&63)==dops[i].rt2) wont_dirty_i|=1<<r;
6603 if((branch_regs[i].regmap[r]&63)==dops[i+1].rt1) wont_dirty_i|=1<<r;
6604 if((branch_regs[i].regmap[r]&63)==dops[i+1].rt2) wont_dirty_i|=1<<r;
57871462 6605 if(branch_regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
6606 }
6607 }
6608 if(wr) {
6609 #ifndef DESTRUCTIVE_WRITEBACK
6610 branch_regs[i].dirty&=wont_dirty_i;
6611 #endif
6612 branch_regs[i].dirty|=will_dirty_i;
6613 }
6614 }
6615 }
6616 }
cf95b4f0 6617 else if(dops[i].itype==SYSCALL||dops[i].itype==HLECALL||dops[i].itype==INTCALL)
57871462 6618 {
6619 // SYSCALL instruction (software interrupt)
6620 will_dirty_i=0;
6621 wont_dirty_i=0;
6622 }
cf95b4f0 6623 else if(dops[i].itype==COP0 && (source[i]&0x3f)==0x18)
57871462 6624 {
6625 // ERET instruction (return from interrupt)
6626 will_dirty_i=0;
6627 wont_dirty_i=0;
6628 }
6629 will_dirty_next=will_dirty_i;
6630 wont_dirty_next=wont_dirty_i;
6631 for(r=0;r<HOST_REGS;r++) {
6632 if(r!=EXCLUDE_REG) {
cf95b4f0 6633 if((regs[i].regmap[r]&63)==dops[i].rt1) will_dirty_i|=1<<r;
6634 if((regs[i].regmap[r]&63)==dops[i].rt2) will_dirty_i|=1<<r;
57871462 6635 if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
6636 if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
6637 if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
cf95b4f0 6638 if((regs[i].regmap[r]&63)==dops[i].rt1) wont_dirty_i|=1<<r;
6639 if((regs[i].regmap[r]&63)==dops[i].rt2) wont_dirty_i|=1<<r;
57871462 6640 if(regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
6641 if(i>istart) {
fe807a8a 6642 if (!dops[i].is_jump)
57871462 6643 {
6644 // Don't store a register immediately after writing it,
6645 // may prevent dual-issue.
cf95b4f0 6646 if((regs[i].regmap[r]&63)==dops[i-1].rt1) wont_dirty_i|=1<<r;
6647 if((regs[i].regmap[r]&63)==dops[i-1].rt2) wont_dirty_i|=1<<r;
57871462 6648 }
6649 }
6650 }
6651 }
6652 // Save it
6653 will_dirty[i]=will_dirty_i;
6654 wont_dirty[i]=wont_dirty_i;
6655 // Mark registers that won't be dirtied as not dirty
6656 if(wr) {
57871462 6657 regs[i].dirty|=will_dirty_i;
6658 #ifndef DESTRUCTIVE_WRITEBACK
6659 regs[i].dirty&=wont_dirty_i;
fe807a8a 6660 if(dops[i].is_jump)
57871462 6661 {
fe807a8a 6662 if (i < iend-1 && !dops[i].is_ujump) {
57871462 6663 for(r=0;r<HOST_REGS;r++) {
6664 if(r!=EXCLUDE_REG) {
6665 if(regs[i].regmap[r]==regmap_pre[i+2][r]) {
6666 regs[i+2].wasdirty&=wont_dirty_i|~(1<<r);
581335b0 6667 }else {/*printf("i: %x (%d) mismatch(+2): %d\n",start+i*4,i,r);assert(!((wont_dirty_i>>r)&1));*/}
57871462 6668 }
6669 }
6670 }
6671 }
6672 else
6673 {
6674 if(i<iend) {
6675 for(r=0;r<HOST_REGS;r++) {
6676 if(r!=EXCLUDE_REG) {
6677 if(regs[i].regmap[r]==regmap_pre[i+1][r]) {
6678 regs[i+1].wasdirty&=wont_dirty_i|~(1<<r);
581335b0 6679 }else {/*printf("i: %x (%d) mismatch(+1): %d\n",start+i*4,i,r);assert(!((wont_dirty_i>>r)&1));*/}
57871462 6680 }
6681 }
6682 }
6683 }
6684 #endif
6685 //}
6686 }
6687 // Deal with changed mappings
6688 temp_will_dirty=will_dirty_i;
6689 temp_wont_dirty=wont_dirty_i;
6690 for(r=0;r<HOST_REGS;r++) {
6691 if(r!=EXCLUDE_REG) {
6692 int nr;
6693 if(regs[i].regmap[r]==regmap_pre[i][r]) {
6694 if(wr) {
6695 #ifndef DESTRUCTIVE_WRITEBACK
6696 regs[i].wasdirty&=wont_dirty_i|~(1<<r);
6697 #endif
6698 regs[i].wasdirty|=will_dirty_i&(1<<r);
6699 }
6700 }
f776eb14 6701 else if(regmap_pre[i][r]>=0&&(nr=get_reg(regs[i].regmap,regmap_pre[i][r]))>=0) {
57871462 6702 // Register moved to a different register
6703 will_dirty_i&=~(1<<r);
6704 wont_dirty_i&=~(1<<r);
6705 will_dirty_i|=((temp_will_dirty>>nr)&1)<<r;
6706 wont_dirty_i|=((temp_wont_dirty>>nr)&1)<<r;
6707 if(wr) {
6708 #ifndef DESTRUCTIVE_WRITEBACK
6709 regs[i].wasdirty&=wont_dirty_i|~(1<<r);
6710 #endif
6711 regs[i].wasdirty|=will_dirty_i&(1<<r);
6712 }
6713 }
6714 else {
6715 will_dirty_i&=~(1<<r);
6716 wont_dirty_i&=~(1<<r);
6717 if((regmap_pre[i][r]&63)>0 && (regmap_pre[i][r]&63)<34) {
6718 will_dirty_i|=((unneeded_reg[i]>>(regmap_pre[i][r]&63))&1)<<r;
6719 wont_dirty_i|=((unneeded_reg[i]>>(regmap_pre[i][r]&63))&1)<<r;
6720 } else {
6721 wont_dirty_i|=1<<r;
581335b0 6722 /*printf("i: %x (%d) mismatch: %d\n",start+i*4,i,r);assert(!((will_dirty>>r)&1));*/
57871462 6723 }
6724 }
6725 }
6726 }
6727 }
6728}
6729
4600ba03 6730#ifdef DISASM
57871462 6731 /* disassembly */
6732void disassemble_inst(int i)
6733{
cf95b4f0 6734 if (dops[i].bt) printf("*"); else printf(" ");
6735 switch(dops[i].itype) {
57871462 6736 case UJUMP:
6737 printf (" %x: %s %8x\n",start+i*4,insn[i],ba[i]);break;
6738 case CJUMP:
cf95b4f0 6739 printf (" %x: %s r%d,r%d,%8x\n",start+i*4,insn[i],dops[i].rs1,dops[i].rs2,i?start+i*4+4+((signed int)((unsigned int)source[i]<<16)>>14):*ba);break;
57871462 6740 case SJUMP:
cf95b4f0 6741 printf (" %x: %s r%d,%8x\n",start+i*4,insn[i],dops[i].rs1,start+i*4+4+((signed int)((unsigned int)source[i]<<16)>>14));break;
57871462 6742 case RJUMP:
cf95b4f0 6743 if (dops[i].opcode==0x9&&dops[i].rt1!=31)
6744 printf (" %x: %s r%d,r%d\n",start+i*4,insn[i],dops[i].rt1,dops[i].rs1);
5067f341 6745 else
cf95b4f0 6746 printf (" %x: %s r%d\n",start+i*4,insn[i],dops[i].rs1);
5067f341 6747 break;
57871462 6748 case SPAN:
cf95b4f0 6749 printf (" %x: %s (pagespan) r%d,r%d,%8x\n",start+i*4,insn[i],dops[i].rs1,dops[i].rs2,ba[i]);break;
57871462 6750 case IMM16:
cf95b4f0 6751 if(dops[i].opcode==0xf) //LUI
6752 printf (" %x: %s r%d,%4x0000\n",start+i*4,insn[i],dops[i].rt1,imm[i]&0xffff);
57871462 6753 else
cf95b4f0 6754 printf (" %x: %s r%d,r%d,%d\n",start+i*4,insn[i],dops[i].rt1,dops[i].rs1,imm[i]);
57871462 6755 break;
6756 case LOAD:
6757 case LOADLR:
cf95b4f0 6758 printf (" %x: %s r%d,r%d+%x\n",start+i*4,insn[i],dops[i].rt1,dops[i].rs1,imm[i]);
57871462 6759 break;
6760 case STORE:
6761 case STORELR:
cf95b4f0 6762 printf (" %x: %s r%d,r%d+%x\n",start+i*4,insn[i],dops[i].rs2,dops[i].rs1,imm[i]);
57871462 6763 break;
6764 case ALU:
6765 case SHIFT:
cf95b4f0 6766 printf (" %x: %s r%d,r%d,r%d\n",start+i*4,insn[i],dops[i].rt1,dops[i].rs1,dops[i].rs2);
57871462 6767 break;
6768 case MULTDIV:
cf95b4f0 6769 printf (" %x: %s r%d,r%d\n",start+i*4,insn[i],dops[i].rs1,dops[i].rs2);
57871462 6770 break;
6771 case SHIFTIMM:
cf95b4f0 6772 printf (" %x: %s r%d,r%d,%d\n",start+i*4,insn[i],dops[i].rt1,dops[i].rs1,imm[i]);
57871462 6773 break;
6774 case MOV:
cf95b4f0 6775 if((dops[i].opcode2&0x1d)==0x10)
6776 printf (" %x: %s r%d\n",start+i*4,insn[i],dops[i].rt1);
6777 else if((dops[i].opcode2&0x1d)==0x11)
6778 printf (" %x: %s r%d\n",start+i*4,insn[i],dops[i].rs1);
57871462 6779 else
6780 printf (" %x: %s\n",start+i*4,insn[i]);
6781 break;
6782 case COP0:
cf95b4f0 6783 if(dops[i].opcode2==0)
6784 printf (" %x: %s r%d,cpr0[%d]\n",start+i*4,insn[i],dops[i].rt1,(source[i]>>11)&0x1f); // MFC0
6785 else if(dops[i].opcode2==4)
6786 printf (" %x: %s r%d,cpr0[%d]\n",start+i*4,insn[i],dops[i].rs1,(source[i]>>11)&0x1f); // MTC0
57871462 6787 else printf (" %x: %s\n",start+i*4,insn[i]);
6788 break;
6789 case COP1:
cf95b4f0 6790 if(dops[i].opcode2<3)
6791 printf (" %x: %s r%d,cpr1[%d]\n",start+i*4,insn[i],dops[i].rt1,(source[i]>>11)&0x1f); // MFC1
6792 else if(dops[i].opcode2>3)
6793 printf (" %x: %s r%d,cpr1[%d]\n",start+i*4,insn[i],dops[i].rs1,(source[i]>>11)&0x1f); // MTC1
57871462 6794 else printf (" %x: %s\n",start+i*4,insn[i]);
6795 break;
b9b61529 6796 case COP2:
cf95b4f0 6797 if(dops[i].opcode2<3)
6798 printf (" %x: %s r%d,cpr2[%d]\n",start+i*4,insn[i],dops[i].rt1,(source[i]>>11)&0x1f); // MFC2
6799 else if(dops[i].opcode2>3)
6800 printf (" %x: %s r%d,cpr2[%d]\n",start+i*4,insn[i],dops[i].rs1,(source[i]>>11)&0x1f); // MTC2
b9b61529 6801 else printf (" %x: %s\n",start+i*4,insn[i]);
6802 break;
57871462 6803 case C1LS:
cf95b4f0 6804 printf (" %x: %s cpr1[%d],r%d+%x\n",start+i*4,insn[i],(source[i]>>16)&0x1f,dops[i].rs1,imm[i]);
57871462 6805 break;
b9b61529 6806 case C2LS:
cf95b4f0 6807 printf (" %x: %s cpr2[%d],r%d+%x\n",start+i*4,insn[i],(source[i]>>16)&0x1f,dops[i].rs1,imm[i]);
b9b61529 6808 break;
1e973cb0 6809 case INTCALL:
6810 printf (" %x: %s (INTCALL)\n",start+i*4,insn[i]);
6811 break;
57871462 6812 default:
6813 //printf (" %s %8x\n",insn[i],source[i]);
6814 printf (" %x: %s\n",start+i*4,insn[i]);
6815 }
6816}
4600ba03 6817#else
6818static void disassemble_inst(int i) {}
6819#endif // DISASM
57871462 6820
d848b60a 6821#define DRC_TEST_VAL 0x74657374
6822
be516ebe 6823static void new_dynarec_test(void)
d848b60a 6824{
be516ebe 6825 int (*testfunc)(void);
d148d265 6826 void *beginning;
be516ebe 6827 int ret[2];
6828 size_t i;
d148d265 6829
687b4580 6830 // check structure linkage
7c3a5182 6831 if ((u_char *)rcnts - (u_char *)&psxRegs != sizeof(psxRegs))
687b4580 6832 {
7c3a5182 6833 SysPrintf("linkage_arm* miscompilation/breakage detected.\n");
687b4580 6834 }
6835
761fdd0a 6836 SysPrintf("testing if we can run recompiled code @%p...\n", out);
be516ebe 6837 ((volatile u_int *)out)[0]++; // make cache dirty
6838
6839 for (i = 0; i < ARRAY_SIZE(ret); i++) {
2a014d73 6840 out = ndrc->translation_cache;
be516ebe 6841 beginning = start_block();
6842 emit_movimm(DRC_TEST_VAL + i, 0); // test
6843 emit_ret();
6844 literal_pool(0);
6845 end_block(beginning);
6846 testfunc = beginning;
6847 ret[i] = testfunc();
6848 }
6849
6850 if (ret[0] == DRC_TEST_VAL && ret[1] == DRC_TEST_VAL + 1)
d848b60a 6851 SysPrintf("test passed.\n");
6852 else
be516ebe 6853 SysPrintf("test failed, will likely crash soon (r=%08x %08x)\n", ret[0], ret[1]);
2a014d73 6854 out = ndrc->translation_cache;
d848b60a 6855}
6856
dc990066 6857// clear the state completely, instead of just marking
6858// things invalid like invalidate_all_pages() does
919981d0 6859void new_dynarec_clear_full(void)
57871462 6860{
57871462 6861 int n;
2a014d73 6862 out = ndrc->translation_cache;
35775df7 6863 memset(invalid_code,1,sizeof(invalid_code));
6864 memset(hash_table,0xff,sizeof(hash_table));
57871462 6865 memset(mini_ht,-1,sizeof(mini_ht));
6866 memset(restore_candidate,0,sizeof(restore_candidate));
dc990066 6867 memset(shadow,0,sizeof(shadow));
57871462 6868 copy=shadow;
6869 expirep=16384; // Expiry pointer, +2 blocks
6870 pending_exception=0;
6871 literalcount=0;
57871462 6872 stop_after_jal=0;
9be4ba64 6873 inv_code_start=inv_code_end=~0;
7f94b097 6874 hack_addr=0;
39b71d9a 6875 f1_hack=0;
57871462 6876 // TLB
dc990066 6877 for(n=0;n<4096;n++) ll_clear(jump_in+n);
6878 for(n=0;n<4096;n++) ll_clear(jump_out+n);
6879 for(n=0;n<4096;n++) ll_clear(jump_dirty+n);
32631e6a 6880
6881 cycle_multiplier_old = cycle_multiplier;
6882 new_dynarec_hacks_old = new_dynarec_hacks;
dc990066 6883}
6884
919981d0 6885void new_dynarec_init(void)
dc990066 6886{
66ea165f 6887 SysPrintf("Init new dynarec, ndrc size %x\n", (int)sizeof(*ndrc));
1e212a25 6888
0aeb0cb9 6889#ifdef _3DS
6890 check_rosalina();
6891#endif
2a014d73 6892#ifdef BASE_ADDR_DYNAMIC
1e212a25 6893 #ifdef VITA
0aeb0cb9 6894 sceBlock = getVMBlock(); //sceKernelAllocMemBlockForVM("code", sizeof(*ndrc));
66ea165f 6895 if (sceBlock <= 0)
6896 SysPrintf("sceKernelAllocMemBlockForVM failed: %x\n", sceBlock);
2a014d73 6897 int ret = sceKernelGetMemBlockBase(sceBlock, (void **)&ndrc);
1e212a25 6898 if (ret < 0)
66ea165f 6899 SysPrintf("sceKernelGetMemBlockBase failed: %x\n", ret);
0aeb0cb9 6900 sceKernelOpenVMDomain();
6901 sceClibPrintf("translation_cache = 0x%08lx\n ", (long)ndrc->translation_cache);
6902 #elif defined(_MSC_VER)
6903 ndrc = VirtualAlloc(NULL, sizeof(*ndrc), MEM_COMMIT | MEM_RESERVE,
6904 PAGE_EXECUTE_READWRITE);
1e212a25 6905 #else
2a014d73 6906 uintptr_t desired_addr = 0;
6907 #ifdef __ELF__
6908 extern char _end;
6909 desired_addr = ((uintptr_t)&_end + 0xffffff) & ~0xffffffl;
6910 #endif
6911 ndrc = mmap((void *)desired_addr, sizeof(*ndrc),
1e212a25 6912 PROT_READ | PROT_WRITE | PROT_EXEC,
6913 MAP_PRIVATE | MAP_ANONYMOUS, -1, 0);
2a014d73 6914 if (ndrc == MAP_FAILED) {
d848b60a 6915 SysPrintf("mmap() failed: %s\n", strerror(errno));
1e212a25 6916 abort();
d848b60a 6917 }
1e212a25 6918 #endif
6919#else
6920 #ifndef NO_WRITE_EXEC
bdeade46 6921 // not all systems allow execute in data segment by default
761fdd0a 6922 // size must be 4K aligned for 3DS?
6923 if (mprotect(ndrc, sizeof(*ndrc),
2a014d73 6924 PROT_READ | PROT_WRITE | PROT_EXEC) != 0)
d848b60a 6925 SysPrintf("mprotect() failed: %s\n", strerror(errno));
1e212a25 6926 #endif
dc990066 6927#endif
2a014d73 6928 out = ndrc->translation_cache;
2573466a 6929 cycle_multiplier=200;
dc990066 6930 new_dynarec_clear_full();
6931#ifdef HOST_IMM8
6932 // Copy this into local area so we don't have to put it in every literal pool
6933 invc_ptr=invalid_code;
6934#endif
57871462 6935 arch_init();
d848b60a 6936 new_dynarec_test();
01d26796 6937 ram_offset=(uintptr_t)rdram-0x80000000;
b105cf4f 6938 if (ram_offset!=0)
c43b5311 6939 SysPrintf("warning: RAM is not directly mapped, performance will suffer\n");
57871462 6940}
6941
919981d0 6942void new_dynarec_cleanup(void)
57871462 6943{
6944 int n;
2a014d73 6945#ifdef BASE_ADDR_DYNAMIC
1e212a25 6946 #ifdef VITA
66ea165f 6947 // sceBlock is managed by retroarch's bootstrap code
9c67c98f 6948 //sceKernelFreeMemBlock(sceBlock);
6949 //sceBlock = -1;
1e212a25 6950 #else
2a014d73 6951 if (munmap(ndrc, sizeof(*ndrc)) < 0)
1e212a25 6952 SysPrintf("munmap() failed\n");
bdeade46 6953 #endif
1e212a25 6954#endif
57871462 6955 for(n=0;n<4096;n++) ll_clear(jump_in+n);
6956 for(n=0;n<4096;n++) ll_clear(jump_out+n);
6957 for(n=0;n<4096;n++) ll_clear(jump_dirty+n);
6958 #ifdef ROM_COPY
c43b5311 6959 if (munmap (ROM_COPY, 67108864) < 0) {SysPrintf("munmap() failed\n");}
57871462 6960 #endif
6961}
6962
03f55e6b 6963static u_int *get_source_start(u_int addr, u_int *limit)
57871462 6964{
03f55e6b 6965 if (addr < 0x00200000 ||
a3203cf4 6966 (0xa0000000 <= addr && addr < 0xa0200000))
6967 {
03f55e6b 6968 // used for BIOS calls mostly?
6969 *limit = (addr&0xa0000000)|0x00200000;
01d26796 6970 return (u_int *)(rdram + (addr&0x1fffff));
03f55e6b 6971 }
6972 else if (!Config.HLE && (
6973 /* (0x9fc00000 <= addr && addr < 0x9fc80000) ||*/
a3203cf4 6974 (0xbfc00000 <= addr && addr < 0xbfc80000)))
6975 {
6976 // BIOS. The multiplier should be much higher as it's uncached 8bit mem,
6977 // but timings in PCSX are too tied to the interpreter's BIAS
d62c125a 6978 if (!HACK_ENABLED(NDHACK_OVERRIDE_CYCLE_M))
24058131 6979 cycle_multiplier_active = 200;
a3203cf4 6980
03f55e6b 6981 *limit = (addr & 0xfff00000) | 0x80000;
01d26796 6982 return (u_int *)((u_char *)psxR + (addr&0x7ffff));
03f55e6b 6983 }
6984 else if (addr >= 0x80000000 && addr < 0x80000000+RAM_SIZE) {
6985 *limit = (addr & 0x80600000) + 0x00200000;
01d26796 6986 return (u_int *)(rdram + (addr&0x1fffff));
03f55e6b 6987 }
581335b0 6988 return NULL;
03f55e6b 6989}
6990
6991static u_int scan_for_ret(u_int addr)
6992{
6993 u_int limit = 0;
6994 u_int *mem;
6995
6996 mem = get_source_start(addr, &limit);
6997 if (mem == NULL)
6998 return addr;
6999
7000 if (limit > addr + 0x1000)
7001 limit = addr + 0x1000;
7002 for (; addr < limit; addr += 4, mem++) {
7003 if (*mem == 0x03e00008) // jr $ra
7004 return addr + 8;
57871462 7005 }
581335b0 7006 return addr;
03f55e6b 7007}
7008
7009struct savestate_block {
7010 uint32_t addr;
7011 uint32_t regflags;
7012};
7013
7014static int addr_cmp(const void *p1_, const void *p2_)
7015{
7016 const struct savestate_block *p1 = p1_, *p2 = p2_;
7017 return p1->addr - p2->addr;
7018}
7019
7020int new_dynarec_save_blocks(void *save, int size)
7021{
7022 struct savestate_block *blocks = save;
7023 int maxcount = size / sizeof(blocks[0]);
7024 struct savestate_block tmp_blocks[1024];
7025 struct ll_entry *head;
7026 int p, s, d, o, bcnt;
7027 u_int addr;
7028
7029 o = 0;
b14b6a8f 7030 for (p = 0; p < ARRAY_SIZE(jump_in); p++) {
03f55e6b 7031 bcnt = 0;
7032 for (head = jump_in[p]; head != NULL; head = head->next) {
7033 tmp_blocks[bcnt].addr = head->vaddr;
7034 tmp_blocks[bcnt].regflags = head->reg_sv_flags;
7035 bcnt++;
7036 }
7037 if (bcnt < 1)
7038 continue;
7039 qsort(tmp_blocks, bcnt, sizeof(tmp_blocks[0]), addr_cmp);
7040
7041 addr = tmp_blocks[0].addr;
7042 for (s = d = 0; s < bcnt; s++) {
7043 if (tmp_blocks[s].addr < addr)
7044 continue;
7045 if (d == 0 || tmp_blocks[d-1].addr != tmp_blocks[s].addr)
7046 tmp_blocks[d++] = tmp_blocks[s];
7047 addr = scan_for_ret(tmp_blocks[s].addr);
7048 }
7049
7050 if (o + d > maxcount)
7051 d = maxcount - o;
7052 memcpy(&blocks[o], tmp_blocks, d * sizeof(blocks[0]));
7053 o += d;
7054 }
7055
7056 return o * sizeof(blocks[0]);
7057}
7058
7059void new_dynarec_load_blocks(const void *save, int size)
7060{
7061 const struct savestate_block *blocks = save;
7062 int count = size / sizeof(blocks[0]);
7063 u_int regs_save[32];
7064 uint32_t f;
7065 int i, b;
7066
7067 get_addr(psxRegs.pc);
7068
7069 // change GPRs for speculation to at least partially work..
7070 memcpy(regs_save, &psxRegs.GPR, sizeof(regs_save));
7071 for (i = 1; i < 32; i++)
7072 psxRegs.GPR.r[i] = 0x80000000;
7073
7074 for (b = 0; b < count; b++) {
7075 for (f = blocks[b].regflags, i = 0; f; f >>= 1, i++) {
7076 if (f & 1)
7077 psxRegs.GPR.r[i] = 0x1f800000;
7078 }
7079
7080 get_addr(blocks[b].addr);
7081
7082 for (f = blocks[b].regflags, i = 0; f; f >>= 1, i++) {
7083 if (f & 1)
7084 psxRegs.GPR.r[i] = 0x80000000;
7085 }
7086 }
7087
7088 memcpy(&psxRegs.GPR, regs_save, sizeof(regs_save));
7089}
7090
7f94b097 7091static int apply_hacks(void)
24058131 7092{
7093 int i;
7094 if (HACK_ENABLED(NDHACK_NO_COMPAT_HACKS))
7f94b097 7095 return 0;
24058131 7096 /* special hack(s) */
7097 for (i = 0; i < slen - 4; i++)
7098 {
7099 // lui a4, 0xf200; jal <rcnt_read>; addu a0, 2; slti v0, 28224
7100 if (source[i] == 0x3c04f200 && dops[i+1].itype == UJUMP
7101 && source[i+2] == 0x34840002 && dops[i+3].opcode == 0x0a
7102 && imm[i+3] == 0x6e40 && dops[i+3].rs1 == 2)
7103 {
7104 SysPrintf("PE2 hack @%08x\n", start + (i+3)*4);
7105 dops[i + 3].itype = NOP;
7106 }
7107 }
7108 i = slen;
7109 if (i > 10 && source[i-1] == 0 && source[i-2] == 0x03e00008
7110 && source[i-4] == 0x8fbf0018 && source[i-6] == 0x00c0f809
7111 && dops[i-7].itype == STORE)
7112 {
7113 i = i-8;
7114 if (dops[i].itype == IMM16)
7115 i--;
7116 // swl r2, 15(r6); swr r2, 12(r6); sw r6, *; jalr r6
7117 if (dops[i].itype == STORELR && dops[i].rs1 == 6
7118 && dops[i-1].itype == STORELR && dops[i-1].rs1 == 6)
7119 {
7f94b097 7120 SysPrintf("F1 hack from %08x, old dst %08x\n", start, hack_addr);
7121 f1_hack = 1;
7122 return 1;
24058131 7123 }
7124 }
7f94b097 7125 return 0;
24058131 7126}
7127
3968e69e 7128int new_recompile_block(u_int addr)
03f55e6b 7129{
7130 u_int pagelimit = 0;
7131 u_int state_rflags = 0;
7132 int i;
7133
1a4301c4 7134 assem_debug("NOTCOMPILED: addr = %x -> %p\n", addr, out);
57871462 7135 //printf("TRACE: count=%d next=%d (compile %x)\n",Count,next_interupt,addr);
9f51b4b9 7136 //if(debug)
57871462 7137 //printf("fpu mapping=%x enabled=%x\n",(Status & 0x04000000)>>26,(Status & 0x20000000)>>29);
03f55e6b 7138
7139 // this is just for speculation
7140 for (i = 1; i < 32; i++) {
7141 if ((psxRegs.GPR.r[i] & 0xffff0000) == 0x1f800000)
7142 state_rflags |= 1 << i;
7143 }
7144
57871462 7145 start = (u_int)addr&~3;
7c3a5182 7146 //assert(((u_int)addr&1)==0); // start-in-delay-slot flag
2f546f9a 7147 new_dynarec_did_compile=1;
9ad4d757 7148 if (Config.HLE && start == 0x80001000) // hlecall
560e4a12 7149 {
7139f3c8 7150 // XXX: is this enough? Maybe check hleSoftCall?
d148d265 7151 void *beginning=start_block();
7139f3c8 7152 u_int page=get_page(start);
d148d265 7153
7139f3c8 7154 invalid_code[start>>12]=0;
7155 emit_movimm(start,0);
643aeae3 7156 emit_writeword(0,&pcaddr);
2a014d73 7157 emit_far_jump(new_dyna_leave);
15776b68 7158 literal_pool(0);
d148d265 7159 end_block(beginning);
03f55e6b 7160 ll_add_flags(jump_in+page,start,state_rflags,(void *)beginning);
7139f3c8 7161 return 0;
7162 }
7f94b097 7163 else if (f1_hack && hack_addr == 0) {
39b71d9a 7164 void *beginning = start_block();
7165 u_int page = get_page(start);
7f94b097 7166 emit_movimm(start, 0);
7167 emit_writeword(0, &hack_addr);
39b71d9a 7168 emit_readword(&psxRegs.GPR.n.sp, 0);
7169 emit_readptr(&mem_rtab, 1);
7170 emit_shrimm(0, 12, 2);
7171 emit_readptr_dualindexedx_ptrlen(1, 2, 1);
7172 emit_addimm(0, 0x18, 0);
7173 emit_adds_ptr(1, 1, 1);
7174 emit_ldr_dualindexed(1, 0, 0);
7175 emit_writeword(0, &psxRegs.GPR.r[26]); // lw k0, 0x18(sp)
7176 emit_far_call(get_addr_ht);
7177 emit_jmpreg(0); // jr k0
7178 literal_pool(0);
7179 end_block(beginning);
7180
7181 ll_add_flags(jump_in + page, start, state_rflags, beginning);
7182 SysPrintf("F1 hack to %08x\n", start);
39b71d9a 7183 return 0;
7184 }
03f55e6b 7185
24058131 7186 cycle_multiplier_active = cycle_multiplier_override && cycle_multiplier == CYCLE_MULT_DEFAULT
7187 ? cycle_multiplier_override : cycle_multiplier;
7188
03f55e6b 7189 source = get_source_start(start, &pagelimit);
7190 if (source == NULL) {
7191 SysPrintf("Compile at bogus memory address: %08x\n", addr);
7c3a5182 7192 abort();
57871462 7193 }
7194
7195 /* Pass 1: disassemble */
7196 /* Pass 2: register dependencies, branch targets */
7197 /* Pass 3: register allocation */
7198 /* Pass 4: branch dependencies */
7199 /* Pass 5: pre-alloc */
7200 /* Pass 6: optimize clean/dirty state */
7201 /* Pass 7: flag 32-bit registers */
7202 /* Pass 8: assembly */
7203 /* Pass 9: linker */
7204 /* Pass 10: garbage collection / free memory */
7205
03f55e6b 7206 int j;
57871462 7207 int done=0;
7208 unsigned int type,op,op2;
7209
7210 //printf("addr = %x source = %x %x\n", addr,source,source[0]);
9f51b4b9 7211
57871462 7212 /* Pass 1 disassembly */
7213
7ebfcedf 7214 for (i = 0; !done; i++)
7215 {
7216 memset(&dops[i], 0, sizeof(dops[i]));
cf95b4f0 7217 op2=0;
e1190b87 7218 minimum_free_regs[i]=0;
cf95b4f0 7219 dops[i].opcode=op=source[i]>>26;
57871462 7220 switch(op)
7221 {
7222 case 0x00: strcpy(insn[i],"special"); type=NI;
7223 op2=source[i]&0x3f;
7224 switch(op2)
7225 {
7226 case 0x00: strcpy(insn[i],"SLL"); type=SHIFTIMM; break;
7227 case 0x02: strcpy(insn[i],"SRL"); type=SHIFTIMM; break;
7228 case 0x03: strcpy(insn[i],"SRA"); type=SHIFTIMM; break;
7229 case 0x04: strcpy(insn[i],"SLLV"); type=SHIFT; break;
7230 case 0x06: strcpy(insn[i],"SRLV"); type=SHIFT; break;
7231 case 0x07: strcpy(insn[i],"SRAV"); type=SHIFT; break;
7232 case 0x08: strcpy(insn[i],"JR"); type=RJUMP; break;
7233 case 0x09: strcpy(insn[i],"JALR"); type=RJUMP; break;
7234 case 0x0C: strcpy(insn[i],"SYSCALL"); type=SYSCALL; break;
d1150cd6 7235 case 0x0D: strcpy(insn[i],"BREAK"); type=SYSCALL; break;
57871462 7236 case 0x0F: strcpy(insn[i],"SYNC"); type=OTHER; break;
7237 case 0x10: strcpy(insn[i],"MFHI"); type=MOV; break;
7238 case 0x11: strcpy(insn[i],"MTHI"); type=MOV; break;
7239 case 0x12: strcpy(insn[i],"MFLO"); type=MOV; break;
7240 case 0x13: strcpy(insn[i],"MTLO"); type=MOV; break;
57871462 7241 case 0x18: strcpy(insn[i],"MULT"); type=MULTDIV; break;
7242 case 0x19: strcpy(insn[i],"MULTU"); type=MULTDIV; break;
7243 case 0x1A: strcpy(insn[i],"DIV"); type=MULTDIV; break;
7244 case 0x1B: strcpy(insn[i],"DIVU"); type=MULTDIV; break;
57871462 7245 case 0x20: strcpy(insn[i],"ADD"); type=ALU; break;
7246 case 0x21: strcpy(insn[i],"ADDU"); type=ALU; break;
7247 case 0x22: strcpy(insn[i],"SUB"); type=ALU; break;
7248 case 0x23: strcpy(insn[i],"SUBU"); type=ALU; break;
7249 case 0x24: strcpy(insn[i],"AND"); type=ALU; break;
7250 case 0x25: strcpy(insn[i],"OR"); type=ALU; break;
7251 case 0x26: strcpy(insn[i],"XOR"); type=ALU; break;
7252 case 0x27: strcpy(insn[i],"NOR"); type=ALU; break;
7253 case 0x2A: strcpy(insn[i],"SLT"); type=ALU; break;
7254 case 0x2B: strcpy(insn[i],"SLTU"); type=ALU; break;
57871462 7255 case 0x30: strcpy(insn[i],"TGE"); type=NI; break;
7256 case 0x31: strcpy(insn[i],"TGEU"); type=NI; break;
7257 case 0x32: strcpy(insn[i],"TLT"); type=NI; break;
7258 case 0x33: strcpy(insn[i],"TLTU"); type=NI; break;
7259 case 0x34: strcpy(insn[i],"TEQ"); type=NI; break;
7260 case 0x36: strcpy(insn[i],"TNE"); type=NI; break;
71e490c5 7261#if 0
7f2607ea 7262 case 0x14: strcpy(insn[i],"DSLLV"); type=SHIFT; break;
7263 case 0x16: strcpy(insn[i],"DSRLV"); type=SHIFT; break;
7264 case 0x17: strcpy(insn[i],"DSRAV"); type=SHIFT; break;
7265 case 0x1C: strcpy(insn[i],"DMULT"); type=MULTDIV; break;
7266 case 0x1D: strcpy(insn[i],"DMULTU"); type=MULTDIV; break;
7267 case 0x1E: strcpy(insn[i],"DDIV"); type=MULTDIV; break;
7268 case 0x1F: strcpy(insn[i],"DDIVU"); type=MULTDIV; break;
7269 case 0x2C: strcpy(insn[i],"DADD"); type=ALU; break;
7270 case 0x2D: strcpy(insn[i],"DADDU"); type=ALU; break;
7271 case 0x2E: strcpy(insn[i],"DSUB"); type=ALU; break;
7272 case 0x2F: strcpy(insn[i],"DSUBU"); type=ALU; break;
57871462 7273 case 0x38: strcpy(insn[i],"DSLL"); type=SHIFTIMM; break;
7274 case 0x3A: strcpy(insn[i],"DSRL"); type=SHIFTIMM; break;
7275 case 0x3B: strcpy(insn[i],"DSRA"); type=SHIFTIMM; break;
7276 case 0x3C: strcpy(insn[i],"DSLL32"); type=SHIFTIMM; break;
7277 case 0x3E: strcpy(insn[i],"DSRL32"); type=SHIFTIMM; break;
7278 case 0x3F: strcpy(insn[i],"DSRA32"); type=SHIFTIMM; break;
7f2607ea 7279#endif
57871462 7280 }
7281 break;
7282 case 0x01: strcpy(insn[i],"regimm"); type=NI;
7283 op2=(source[i]>>16)&0x1f;
7284 switch(op2)
7285 {
7286 case 0x00: strcpy(insn[i],"BLTZ"); type=SJUMP; break;
7287 case 0x01: strcpy(insn[i],"BGEZ"); type=SJUMP; break;
4919de1e 7288 //case 0x02: strcpy(insn[i],"BLTZL"); type=SJUMP; break;
7289 //case 0x03: strcpy(insn[i],"BGEZL"); type=SJUMP; break;
7290 //case 0x08: strcpy(insn[i],"TGEI"); type=NI; break;
7291 //case 0x09: strcpy(insn[i],"TGEIU"); type=NI; break;
7292 //case 0x0A: strcpy(insn[i],"TLTI"); type=NI; break;
7293 //case 0x0B: strcpy(insn[i],"TLTIU"); type=NI; break;
7294 //case 0x0C: strcpy(insn[i],"TEQI"); type=NI; break;
7295 //case 0x0E: strcpy(insn[i],"TNEI"); type=NI; break;
57871462 7296 case 0x10: strcpy(insn[i],"BLTZAL"); type=SJUMP; break;
7297 case 0x11: strcpy(insn[i],"BGEZAL"); type=SJUMP; break;
4919de1e 7298 //case 0x12: strcpy(insn[i],"BLTZALL"); type=SJUMP; break;
7299 //case 0x13: strcpy(insn[i],"BGEZALL"); type=SJUMP; break;
57871462 7300 }
7301 break;
7302 case 0x02: strcpy(insn[i],"J"); type=UJUMP; break;
7303 case 0x03: strcpy(insn[i],"JAL"); type=UJUMP; break;
7304 case 0x04: strcpy(insn[i],"BEQ"); type=CJUMP; break;
7305 case 0x05: strcpy(insn[i],"BNE"); type=CJUMP; break;
7306 case 0x06: strcpy(insn[i],"BLEZ"); type=CJUMP; break;
7307 case 0x07: strcpy(insn[i],"BGTZ"); type=CJUMP; break;
7308 case 0x08: strcpy(insn[i],"ADDI"); type=IMM16; break;
7309 case 0x09: strcpy(insn[i],"ADDIU"); type=IMM16; break;
7310 case 0x0A: strcpy(insn[i],"SLTI"); type=IMM16; break;
7311 case 0x0B: strcpy(insn[i],"SLTIU"); type=IMM16; break;
7312 case 0x0C: strcpy(insn[i],"ANDI"); type=IMM16; break;
7313 case 0x0D: strcpy(insn[i],"ORI"); type=IMM16; break;
7314 case 0x0E: strcpy(insn[i],"XORI"); type=IMM16; break;
7315 case 0x0F: strcpy(insn[i],"LUI"); type=IMM16; break;
7316 case 0x10: strcpy(insn[i],"cop0"); type=NI;
7317 op2=(source[i]>>21)&0x1f;
7318 switch(op2)
7319 {
7320 case 0x00: strcpy(insn[i],"MFC0"); type=COP0; break;
00fa9369 7321 case 0x02: strcpy(insn[i],"CFC0"); type=COP0; break;
57871462 7322 case 0x04: strcpy(insn[i],"MTC0"); type=COP0; break;
00fa9369 7323 case 0x06: strcpy(insn[i],"CTC0"); type=COP0; break;
7324 case 0x10: strcpy(insn[i],"RFE"); type=COP0; break;
57871462 7325 }
7326 break;
00fa9369 7327 case 0x11: strcpy(insn[i],"cop1"); type=COP1;
57871462 7328 op2=(source[i]>>21)&0x1f;
57871462 7329 break;
71e490c5 7330#if 0
57871462 7331 case 0x14: strcpy(insn[i],"BEQL"); type=CJUMP; break;
7332 case 0x15: strcpy(insn[i],"BNEL"); type=CJUMP; break;
7333 case 0x16: strcpy(insn[i],"BLEZL"); type=CJUMP; break;
7334 case 0x17: strcpy(insn[i],"BGTZL"); type=CJUMP; break;
7335 case 0x18: strcpy(insn[i],"DADDI"); type=IMM16; break;
7336 case 0x19: strcpy(insn[i],"DADDIU"); type=IMM16; break;
7337 case 0x1A: strcpy(insn[i],"LDL"); type=LOADLR; break;
7338 case 0x1B: strcpy(insn[i],"LDR"); type=LOADLR; break;
996cc15d 7339#endif
57871462 7340 case 0x20: strcpy(insn[i],"LB"); type=LOAD; break;
7341 case 0x21: strcpy(insn[i],"LH"); type=LOAD; break;
7342 case 0x22: strcpy(insn[i],"LWL"); type=LOADLR; break;
7343 case 0x23: strcpy(insn[i],"LW"); type=LOAD; break;
7344 case 0x24: strcpy(insn[i],"LBU"); type=LOAD; break;
7345 case 0x25: strcpy(insn[i],"LHU"); type=LOAD; break;
7346 case 0x26: strcpy(insn[i],"LWR"); type=LOADLR; break;
71e490c5 7347#if 0
57871462 7348 case 0x27: strcpy(insn[i],"LWU"); type=LOAD; break;
64bd6f82 7349#endif
57871462 7350 case 0x28: strcpy(insn[i],"SB"); type=STORE; break;
7351 case 0x29: strcpy(insn[i],"SH"); type=STORE; break;
7352 case 0x2A: strcpy(insn[i],"SWL"); type=STORELR; break;
7353 case 0x2B: strcpy(insn[i],"SW"); type=STORE; break;
71e490c5 7354#if 0
57871462 7355 case 0x2C: strcpy(insn[i],"SDL"); type=STORELR; break;
7356 case 0x2D: strcpy(insn[i],"SDR"); type=STORELR; break;
996cc15d 7357#endif
57871462 7358 case 0x2E: strcpy(insn[i],"SWR"); type=STORELR; break;
7359 case 0x2F: strcpy(insn[i],"CACHE"); type=NOP; break;
7360 case 0x30: strcpy(insn[i],"LL"); type=NI; break;
7361 case 0x31: strcpy(insn[i],"LWC1"); type=C1LS; break;
71e490c5 7362#if 0
57871462 7363 case 0x34: strcpy(insn[i],"LLD"); type=NI; break;
7364 case 0x35: strcpy(insn[i],"LDC1"); type=C1LS; break;
7365 case 0x37: strcpy(insn[i],"LD"); type=LOAD; break;
996cc15d 7366#endif
57871462 7367 case 0x38: strcpy(insn[i],"SC"); type=NI; break;
7368 case 0x39: strcpy(insn[i],"SWC1"); type=C1LS; break;
71e490c5 7369#if 0
57871462 7370 case 0x3C: strcpy(insn[i],"SCD"); type=NI; break;
7371 case 0x3D: strcpy(insn[i],"SDC1"); type=C1LS; break;
7372 case 0x3F: strcpy(insn[i],"SD"); type=STORE; break;
996cc15d 7373#endif
b9b61529 7374 case 0x12: strcpy(insn[i],"COP2"); type=NI;
7375 op2=(source[i]>>21)&0x1f;
be516ebe 7376 //if (op2 & 0x10)
bedfea38 7377 if (source[i]&0x3f) { // use this hack to support old savestates with patched gte insns
c7abc864 7378 if (gte_handlers[source[i]&0x3f]!=NULL) {
bedfea38 7379 if (gte_regnames[source[i]&0x3f]!=NULL)
7380 strcpy(insn[i],gte_regnames[source[i]&0x3f]);
7381 else
7382 snprintf(insn[i], sizeof(insn[i]), "COP2 %x", source[i]&0x3f);
c7abc864 7383 type=C2OP;
7384 }
7385 }
7386 else switch(op2)
b9b61529 7387 {
7388 case 0x00: strcpy(insn[i],"MFC2"); type=COP2; break;
7389 case 0x02: strcpy(insn[i],"CFC2"); type=COP2; break;
7390 case 0x04: strcpy(insn[i],"MTC2"); type=COP2; break;
7391 case 0x06: strcpy(insn[i],"CTC2"); type=COP2; break;
b9b61529 7392 }
7393 break;
7394 case 0x32: strcpy(insn[i],"LWC2"); type=C2LS; break;
7395 case 0x3A: strcpy(insn[i],"SWC2"); type=C2LS; break;
7396 case 0x3B: strcpy(insn[i],"HLECALL"); type=HLECALL; break;
90ae6d4e 7397 default: strcpy(insn[i],"???"); type=NI;
c43b5311 7398 SysPrintf("NI %08x @%08x (%08x)\n", source[i], addr + i*4, addr);
90ae6d4e 7399 break;
57871462 7400 }
cf95b4f0 7401 dops[i].itype=type;
7402 dops[i].opcode2=op2;
57871462 7403 /* Get registers/immediates */
cf95b4f0 7404 dops[i].lt1=0;
bedfea38 7405 gte_rs[i]=gte_rt[i]=0;
57871462 7406 switch(type) {
7407 case LOAD:
cf95b4f0 7408 dops[i].rs1=(source[i]>>21)&0x1f;
7409 dops[i].rs2=0;
7410 dops[i].rt1=(source[i]>>16)&0x1f;
7411 dops[i].rt2=0;
57871462 7412 imm[i]=(short)source[i];
7413 break;
7414 case STORE:
7415 case STORELR:
cf95b4f0 7416 dops[i].rs1=(source[i]>>21)&0x1f;
7417 dops[i].rs2=(source[i]>>16)&0x1f;
7418 dops[i].rt1=0;
7419 dops[i].rt2=0;
57871462 7420 imm[i]=(short)source[i];
57871462 7421 break;
7422 case LOADLR:
7423 // LWL/LWR only load part of the register,
7424 // therefore the target register must be treated as a source too
cf95b4f0 7425 dops[i].rs1=(source[i]>>21)&0x1f;
7426 dops[i].rs2=(source[i]>>16)&0x1f;
7427 dops[i].rt1=(source[i]>>16)&0x1f;
7428 dops[i].rt2=0;
57871462 7429 imm[i]=(short)source[i];
57871462 7430 break;
7431 case IMM16:
cf95b4f0 7432 if (op==0x0f) dops[i].rs1=0; // LUI instruction has no source register
7433 else dops[i].rs1=(source[i]>>21)&0x1f;
7434 dops[i].rs2=0;
7435 dops[i].rt1=(source[i]>>16)&0x1f;
7436 dops[i].rt2=0;
57871462 7437 if(op>=0x0c&&op<=0x0e) { // ANDI/ORI/XORI
7438 imm[i]=(unsigned short)source[i];
7439 }else{
7440 imm[i]=(short)source[i];
7441 }
57871462 7442 break;
7443 case UJUMP:
cf95b4f0 7444 dops[i].rs1=0;
7445 dops[i].rs2=0;
7446 dops[i].rt1=0;
7447 dops[i].rt2=0;
57871462 7448 // The JAL instruction writes to r31.
7449 if (op&1) {
cf95b4f0 7450 dops[i].rt1=31;
57871462 7451 }
cf95b4f0 7452 dops[i].rs2=CCREG;
57871462 7453 break;
7454 case RJUMP:
cf95b4f0 7455 dops[i].rs1=(source[i]>>21)&0x1f;
7456 dops[i].rs2=0;
7457 dops[i].rt1=0;
7458 dops[i].rt2=0;
5067f341 7459 // The JALR instruction writes to rd.
57871462 7460 if (op2&1) {
cf95b4f0 7461 dops[i].rt1=(source[i]>>11)&0x1f;
57871462 7462 }
cf95b4f0 7463 dops[i].rs2=CCREG;
57871462 7464 break;
7465 case CJUMP:
cf95b4f0 7466 dops[i].rs1=(source[i]>>21)&0x1f;
7467 dops[i].rs2=(source[i]>>16)&0x1f;
7468 dops[i].rt1=0;
7469 dops[i].rt2=0;
57871462 7470 if(op&2) { // BGTZ/BLEZ
cf95b4f0 7471 dops[i].rs2=0;
57871462 7472 }
57871462 7473 break;
7474 case SJUMP:
cf95b4f0 7475 dops[i].rs1=(source[i]>>21)&0x1f;
7476 dops[i].rs2=CCREG;
7477 dops[i].rt1=0;
7478 dops[i].rt2=0;
57871462 7479 if(op2&0x10) { // BxxAL
cf95b4f0 7480 dops[i].rt1=31;
57871462 7481 // NOTE: If the branch is not taken, r31 is still overwritten
7482 }
57871462 7483 break;
57871462 7484 case ALU:
cf95b4f0 7485 dops[i].rs1=(source[i]>>21)&0x1f; // source
7486 dops[i].rs2=(source[i]>>16)&0x1f; // subtract amount
7487 dops[i].rt1=(source[i]>>11)&0x1f; // destination
7488 dops[i].rt2=0;
57871462 7489 break;
7490 case MULTDIV:
cf95b4f0 7491 dops[i].rs1=(source[i]>>21)&0x1f; // source
7492 dops[i].rs2=(source[i]>>16)&0x1f; // divisor
7493 dops[i].rt1=HIREG;
7494 dops[i].rt2=LOREG;
57871462 7495 break;
7496 case MOV:
cf95b4f0 7497 dops[i].rs1=0;
7498 dops[i].rs2=0;
7499 dops[i].rt1=0;
7500 dops[i].rt2=0;
7501 if(op2==0x10) dops[i].rs1=HIREG; // MFHI
7502 if(op2==0x11) dops[i].rt1=HIREG; // MTHI
7503 if(op2==0x12) dops[i].rs1=LOREG; // MFLO
7504 if(op2==0x13) dops[i].rt1=LOREG; // MTLO
7505 if((op2&0x1d)==0x10) dops[i].rt1=(source[i]>>11)&0x1f; // MFxx
7506 if((op2&0x1d)==0x11) dops[i].rs1=(source[i]>>21)&0x1f; // MTxx
57871462 7507 break;
7508 case SHIFT:
cf95b4f0 7509 dops[i].rs1=(source[i]>>16)&0x1f; // target of shift
7510 dops[i].rs2=(source[i]>>21)&0x1f; // shift amount
7511 dops[i].rt1=(source[i]>>11)&0x1f; // destination
7512 dops[i].rt2=0;
57871462 7513 break;
7514 case SHIFTIMM:
cf95b4f0 7515 dops[i].rs1=(source[i]>>16)&0x1f;
7516 dops[i].rs2=0;
7517 dops[i].rt1=(source[i]>>11)&0x1f;
7518 dops[i].rt2=0;
57871462 7519 imm[i]=(source[i]>>6)&0x1f;
7520 // DSxx32 instructions
7521 if(op2>=0x3c) imm[i]|=0x20;
57871462 7522 break;
7523 case COP0:
cf95b4f0 7524 dops[i].rs1=0;
7525 dops[i].rs2=0;
7526 dops[i].rt1=0;
7527 dops[i].rt2=0;
7528 if(op2==0||op2==2) dops[i].rt1=(source[i]>>16)&0x1F; // MFC0/CFC0
7529 if(op2==4||op2==6) dops[i].rs1=(source[i]>>16)&0x1F; // MTC0/CTC0
7530 if(op2==4&&((source[i]>>11)&0x1f)==12) dops[i].rt2=CSREG; // Status
7531 if(op2==16) if((source[i]&0x3f)==0x18) dops[i].rs2=CCREG; // ERET
57871462 7532 break;
7533 case COP1:
cf95b4f0 7534 dops[i].rs1=0;
7535 dops[i].rs2=0;
7536 dops[i].rt1=0;
7537 dops[i].rt2=0;
7538 if(op2<3) dops[i].rt1=(source[i]>>16)&0x1F; // MFC1/DMFC1/CFC1
7539 if(op2>3) dops[i].rs1=(source[i]>>16)&0x1F; // MTC1/DMTC1/CTC1
7540 dops[i].rs2=CSREG;
57871462 7541 break;
bedfea38 7542 case COP2:
cf95b4f0 7543 dops[i].rs1=0;
7544 dops[i].rs2=0;
7545 dops[i].rt1=0;
7546 dops[i].rt2=0;
7547 if(op2<3) dops[i].rt1=(source[i]>>16)&0x1F; // MFC2/CFC2
7548 if(op2>3) dops[i].rs1=(source[i]>>16)&0x1F; // MTC2/CTC2
7549 dops[i].rs2=CSREG;
bedfea38 7550 int gr=(source[i]>>11)&0x1F;
7551 switch(op2)
7552 {
7553 case 0x00: gte_rs[i]=1ll<<gr; break; // MFC2
7554 case 0x04: gte_rt[i]=1ll<<gr; break; // MTC2
0ff8c62c 7555 case 0x02: gte_rs[i]=1ll<<(gr+32); break; // CFC2
bedfea38 7556 case 0x06: gte_rt[i]=1ll<<(gr+32); break; // CTC2
7557 }
7558 break;
57871462 7559 case C1LS:
cf95b4f0 7560 dops[i].rs1=(source[i]>>21)&0x1F;
7561 dops[i].rs2=CSREG;
7562 dops[i].rt1=0;
7563 dops[i].rt2=0;
57871462 7564 imm[i]=(short)source[i];
7565 break;
b9b61529 7566 case C2LS:
cf95b4f0 7567 dops[i].rs1=(source[i]>>21)&0x1F;
7568 dops[i].rs2=0;
7569 dops[i].rt1=0;
7570 dops[i].rt2=0;
b9b61529 7571 imm[i]=(short)source[i];
bedfea38 7572 if(op==0x32) gte_rt[i]=1ll<<((source[i]>>16)&0x1F); // LWC2
7573 else gte_rs[i]=1ll<<((source[i]>>16)&0x1F); // SWC2
7574 break;
7575 case C2OP:
cf95b4f0 7576 dops[i].rs1=0;
7577 dops[i].rs2=0;
7578 dops[i].rt1=0;
7579 dops[i].rt2=0;
2167bef6 7580 gte_rs[i]=gte_reg_reads[source[i]&0x3f];
7581 gte_rt[i]=gte_reg_writes[source[i]&0x3f];
7582 gte_rt[i]|=1ll<<63; // every op changes flags
587a5b1c 7583 if((source[i]&0x3f)==GTE_MVMVA) {
7584 int v = (source[i] >> 15) & 3;
7585 gte_rs[i]&=~0xe3fll;
7586 if(v==3) gte_rs[i]|=0xe00ll;
7587 else gte_rs[i]|=3ll<<(v*2);
7588 }
b9b61529 7589 break;
57871462 7590 case SYSCALL:
7139f3c8 7591 case HLECALL:
1e973cb0 7592 case INTCALL:
cf95b4f0 7593 dops[i].rs1=CCREG;
7594 dops[i].rs2=0;
7595 dops[i].rt1=0;
7596 dops[i].rt2=0;
57871462 7597 break;
7598 default:
cf95b4f0 7599 dops[i].rs1=0;
7600 dops[i].rs2=0;
7601 dops[i].rt1=0;
7602 dops[i].rt2=0;
57871462 7603 }
7604 /* Calculate branch target addresses */
7605 if(type==UJUMP)
7606 ba[i]=((start+i*4+4)&0xF0000000)|(((unsigned int)source[i]<<6)>>4);
cf95b4f0 7607 else if(type==CJUMP&&dops[i].rs1==dops[i].rs2&&(op&1))
57871462 7608 ba[i]=start+i*4+8; // Ignore never taken branch
cf95b4f0 7609 else if(type==SJUMP&&dops[i].rs1==0&&!(op2&1))
57871462 7610 ba[i]=start+i*4+8; // Ignore never taken branch
ad49de89 7611 else if(type==CJUMP||type==SJUMP)
57871462 7612 ba[i]=start+i*4+4+((signed int)((unsigned int)source[i]<<16)>>14);
7613 else ba[i]=-1;
4919de1e 7614
7615 /* simplify always (not)taken branches */
cf95b4f0 7616 if (type == CJUMP && dops[i].rs1 == dops[i].rs2) {
7617 dops[i].rs1 = dops[i].rs2 = 0;
4919de1e 7618 if (!(op & 1)) {
cf95b4f0 7619 dops[i].itype = type = UJUMP;
7620 dops[i].rs2 = CCREG;
4919de1e 7621 }
7622 }
cf95b4f0 7623 else if (type == SJUMP && dops[i].rs1 == 0 && (op2 & 1))
7624 dops[i].itype = type = UJUMP;
4919de1e 7625
fe807a8a 7626 dops[i].is_jump = (dops[i].itype == RJUMP || dops[i].itype == UJUMP || dops[i].itype == CJUMP || dops[i].itype == SJUMP);
7627 dops[i].is_ujump = (dops[i].itype == RJUMP || dops[i].itype == UJUMP); // || (source[i] >> 16) == 0x1000 // beq r0,r0
37387d8b 7628 dops[i].is_load = (dops[i].itype == LOAD || dops[i].itype == LOADLR || op == 0x32); // LWC2
7629 dops[i].is_store = (dops[i].itype == STORE || dops[i].itype == STORELR || op == 0x3a); // SWC2
fe807a8a 7630
4919de1e 7631 /* messy cases to just pass over to the interpreter */
fe807a8a 7632 if (i > 0 && dops[i-1].is_jump) {
3e535354 7633 int do_in_intrp=0;
7634 // branch in delay slot?
fe807a8a 7635 if (dops[i].is_jump) {
3e535354 7636 // don't handle first branch and call interpreter if it's hit
c43b5311 7637 SysPrintf("branch in delay slot @%08x (%08x)\n", addr + i*4, addr);
3e535354 7638 do_in_intrp=1;
7639 }
7640 // basic load delay detection
cf95b4f0 7641 else if((type==LOAD||type==LOADLR||type==COP0||type==COP2||type==C2LS)&&dops[i].rt1!=0) {
3e535354 7642 int t=(ba[i-1]-start)/4;
cf95b4f0 7643 if(0 <= t && t < i &&(dops[i].rt1==dops[t].rs1||dops[i].rt1==dops[t].rs2)&&dops[t].itype!=CJUMP&&dops[t].itype!=SJUMP) {
3e535354 7644 // jump target wants DS result - potential load delay effect
c43b5311 7645 SysPrintf("load delay @%08x (%08x)\n", addr + i*4, addr);
3e535354 7646 do_in_intrp=1;
cf95b4f0 7647 dops[t+1].bt=1; // expected return from interpreter
3e535354 7648 }
cf95b4f0 7649 else if(i>=2&&dops[i-2].rt1==2&&dops[i].rt1==2&&dops[i].rs1!=2&&dops[i].rs2!=2&&dops[i-1].rs1!=2&&dops[i-1].rs2!=2&&
fe807a8a 7650 !(i>=3&&dops[i-3].is_jump)) {
3e535354 7651 // v0 overwrite like this is a sign of trouble, bail out
c43b5311 7652 SysPrintf("v0 overwrite @%08x (%08x)\n", addr + i*4, addr);
3e535354 7653 do_in_intrp=1;
7654 }
7655 }
7ebfcedf 7656 if (do_in_intrp) {
7657 memset(&dops[i-1], 0, sizeof(dops[i-1]));
7658 dops[i-1].itype = INTCALL;
7659 dops[i-1].rs1 = CCREG;
7660 ba[i-1] = -1;
7661 done = 2;
3e535354 7662 i--; // don't compile the DS
26869094 7663 }
3e535354 7664 }
4919de1e 7665
3e535354 7666 /* Is this the end of the block? */
fe807a8a 7667 if (i > 0 && dops[i-1].is_ujump) {
cf95b4f0 7668 if(dops[i-1].rt1==0) { // Continue past subroutine call (JAL)
1e973cb0 7669 done=2;
57871462 7670 }
7671 else {
7672 if(stop_after_jal) done=1;
7673 // Stop on BREAK
7674 if((source[i+1]&0xfc00003f)==0x0d) done=1;
7675 }
7676 // Don't recompile stuff that's already compiled
7677 if(check_addr(start+i*4+4)) done=1;
7678 // Don't get too close to the limit
7679 if(i>MAXBLOCK/2) done=1;
7680 }
d1150cd6 7681 if (dops[i].itype == SYSCALL || dops[i].itype == HLECALL || dops[i].itype == INTCALL)
7682 done = stop_after_jal ? 1 : 2;
7683 if (done == 2) {
1e973cb0 7684 // Does the block continue due to a branch?
7685 for(j=i-1;j>=0;j--)
7686 {
2a706964 7687 if(ba[j]==start+i*4) done=j=0; // Branch into delay slot
1e973cb0 7688 if(ba[j]==start+i*4+4) done=j=0;
7689 if(ba[j]==start+i*4+8) done=j=0;
7690 }
7691 }
75dec299 7692 //assert(i<MAXBLOCK-1);
57871462 7693 if(start+i*4==pagelimit-4) done=1;
7694 assert(start+i*4<pagelimit);
7695 if (i==MAXBLOCK-1) done=1;
7696 // Stop if we're compiling junk
cf95b4f0 7697 if(dops[i].itype==NI&&dops[i].opcode==0x11) {
57871462 7698 done=stop_after_jal=1;
c43b5311 7699 SysPrintf("Disabled speculative precompilation\n");
57871462 7700 }
7701 }
7702 slen=i;
fe807a8a 7703 if (dops[i-1].is_jump) {
57871462 7704 if(start+i*4==pagelimit) {
cf95b4f0 7705 dops[i-1].itype=SPAN;
57871462 7706 }
7707 }
7708 assert(slen>0);
7709
7f94b097 7710 int clear_hack_addr = apply_hacks();
39b71d9a 7711
57871462 7712 /* Pass 2 - Register dependencies and branch targets */
7713
7714 unneeded_registers(0,slen-1,0);
9f51b4b9 7715
57871462 7716 /* Pass 3 - Register allocation */
7717
7718 struct regstat current; // Current register allocations/status
6cc8d23c 7719 clear_all_regs(current.regmap_entry);
57871462 7720 clear_all_regs(current.regmap);
6cc8d23c 7721 current.wasdirty = current.dirty = 0;
7722 current.u = unneeded_reg[0];
7723 alloc_reg(&current, 0, CCREG);
7724 dirty_reg(&current, CCREG);
7725 current.wasconst = 0;
7726 current.isconst = 0;
7727 current.loadedconst = 0;
7728 current.waswritten = 0;
57871462 7729 int ds=0;
7730 int cc=0;
5194fb95 7731 int hr=-1;
6ebf4adf 7732
57871462 7733 if((u_int)addr&1) {
7734 // First instruction is delay slot
7735 cc=-1;
cf95b4f0 7736 dops[1].bt=1;
57871462 7737 ds=1;
7738 unneeded_reg[0]=1;
57871462 7739 current.regmap[HOST_BTREG]=BTREG;
7740 }
9f51b4b9 7741
57871462 7742 for(i=0;i<slen;i++)
7743 {
cf95b4f0 7744 if(dops[i].bt)
57871462 7745 {
7746 int hr;
7747 for(hr=0;hr<HOST_REGS;hr++)
7748 {
7749 // Is this really necessary?
7750 if(current.regmap[hr]==0) current.regmap[hr]=-1;
7751 }
7752 current.isconst=0;
27727b63 7753 current.waswritten=0;
57871462 7754 }
24385cae 7755
57871462 7756 memcpy(regmap_pre[i],current.regmap,sizeof(current.regmap));
7757 regs[i].wasconst=current.isconst;
57871462 7758 regs[i].wasdirty=current.dirty;
6cc8d23c 7759 regs[i].dirty=0;
7760 regs[i].u=0;
7761 regs[i].isconst=0;
8575a877 7762 regs[i].loadedconst=0;
fe807a8a 7763 if (!dops[i].is_jump) {
57871462 7764 if(i+1<slen) {
cf95b4f0 7765 current.u=unneeded_reg[i+1]&~((1LL<<dops[i].rs1)|(1LL<<dops[i].rs2));
57871462 7766 current.u|=1;
57871462 7767 } else {
7768 current.u=1;
57871462 7769 }
7770 } else {
7771 if(i+1<slen) {
cf95b4f0 7772 current.u=branch_unneeded_reg[i]&~((1LL<<dops[i+1].rs1)|(1LL<<dops[i+1].rs2));
7773 current.u&=~((1LL<<dops[i].rs1)|(1LL<<dops[i].rs2));
57871462 7774 current.u|=1;
7ebfcedf 7775 } else {
7776 SysPrintf("oops, branch at end of block with no delay slot @%08x\n", start + i*4);
7777 abort();
7778 }
57871462 7779 }
cf95b4f0 7780 dops[i].is_ds=ds;
57871462 7781 if(ds) {
7782 ds=0; // Skip delay slot, already allocated as part of branch
7783 // ...but we need to alloc it in case something jumps here
7784 if(i+1<slen) {
7785 current.u=branch_unneeded_reg[i-1]&unneeded_reg[i+1];
57871462 7786 }else{
7787 current.u=branch_unneeded_reg[i-1];
57871462 7788 }
cf95b4f0 7789 current.u&=~((1LL<<dops[i].rs1)|(1LL<<dops[i].rs2));
57871462 7790 current.u|=1;
57871462 7791 struct regstat temp;
7792 memcpy(&temp,&current,sizeof(current));
7793 temp.wasdirty=temp.dirty;
57871462 7794 // TODO: Take into account unconditional branches, as below
7795 delayslot_alloc(&temp,i);
7796 memcpy(regs[i].regmap,temp.regmap,sizeof(temp.regmap));
7797 regs[i].wasdirty=temp.wasdirty;
57871462 7798 regs[i].dirty=temp.dirty;
57871462 7799 regs[i].isconst=0;
7800 regs[i].wasconst=0;
7801 current.isconst=0;
7802 // Create entry (branch target) regmap
7803 for(hr=0;hr<HOST_REGS;hr++)
7804 {
7805 int r=temp.regmap[hr];
7806 if(r>=0) {
7807 if(r!=regmap_pre[i][hr]) {
7808 regs[i].regmap_entry[hr]=-1;
7809 }
7810 else
7811 {
7c3a5182 7812 assert(r < 64);
57871462 7813 if((current.u>>r)&1) {
7814 regs[i].regmap_entry[hr]=-1;
7815 regs[i].regmap[hr]=-1;
7816 //Don't clear regs in the delay slot as the branch might need them
7817 //current.regmap[hr]=-1;
7818 }else
7819 regs[i].regmap_entry[hr]=r;
57871462 7820 }
7821 } else {
7822 // First instruction expects CCREG to be allocated
9f51b4b9 7823 if(i==0&&hr==HOST_CCREG)
57871462 7824 regs[i].regmap_entry[hr]=CCREG;
7825 else
7826 regs[i].regmap_entry[hr]=-1;
7827 }
7828 }
7829 }
7830 else { // Not delay slot
cf95b4f0 7831 switch(dops[i].itype) {
57871462 7832 case UJUMP:
7833 //current.isconst=0; // DEBUG
7834 //current.wasconst=0; // DEBUG
7835 //regs[i].wasconst=0; // DEBUG
cf95b4f0 7836 clear_const(&current,dops[i].rt1);
57871462 7837 alloc_cc(&current,i);
7838 dirty_reg(&current,CCREG);
cf95b4f0 7839 if (dops[i].rt1==31) {
57871462 7840 alloc_reg(&current,i,31);
7841 dirty_reg(&current,31);
cf95b4f0 7842 //assert(dops[i+1].rs1!=31&&dops[i+1].rs2!=31);
7843 //assert(dops[i+1].rt1!=dops[i].rt1);
57871462 7844 #ifdef REG_PREFETCH
7845 alloc_reg(&current,i,PTEMP);
7846 #endif
57871462 7847 }
cf95b4f0 7848 dops[i].ooo=1;
269bb29a 7849 delayslot_alloc(&current,i+1);
57871462 7850 //current.isconst=0; // DEBUG
7851 ds=1;
7852 //printf("i=%d, isconst=%x\n",i,current.isconst);
7853 break;
7854 case RJUMP:
7855 //current.isconst=0;
7856 //current.wasconst=0;
7857 //regs[i].wasconst=0;
cf95b4f0 7858 clear_const(&current,dops[i].rs1);
7859 clear_const(&current,dops[i].rt1);
57871462 7860 alloc_cc(&current,i);
7861 dirty_reg(&current,CCREG);
4919de1e 7862 if (!ds_writes_rjump_rs(i)) {
cf95b4f0 7863 alloc_reg(&current,i,dops[i].rs1);
7864 if (dops[i].rt1!=0) {
7865 alloc_reg(&current,i,dops[i].rt1);
7866 dirty_reg(&current,dops[i].rt1);
7867 assert(dops[i+1].rs1!=dops[i].rt1&&dops[i+1].rs2!=dops[i].rt1);
7868 assert(dops[i+1].rt1!=dops[i].rt1);
57871462 7869 #ifdef REG_PREFETCH
7870 alloc_reg(&current,i,PTEMP);
7871 #endif
7872 }
7873 #ifdef USE_MINI_HT
cf95b4f0 7874 if(dops[i].rs1==31) { // JALR
57871462 7875 alloc_reg(&current,i,RHASH);
57871462 7876 alloc_reg(&current,i,RHTBL);
57871462 7877 }
7878 #endif
7879 delayslot_alloc(&current,i+1);
7880 } else {
7881 // The delay slot overwrites our source register,
7882 // allocate a temporary register to hold the old value.
7883 current.isconst=0;
7884 current.wasconst=0;
7885 regs[i].wasconst=0;
7886 delayslot_alloc(&current,i+1);
7887 current.isconst=0;
7888 alloc_reg(&current,i,RTEMP);
7889 }
7890 //current.isconst=0; // DEBUG
cf95b4f0 7891 dops[i].ooo=1;
57871462 7892 ds=1;
7893 break;
7894 case CJUMP:
7895 //current.isconst=0;
7896 //current.wasconst=0;
7897 //regs[i].wasconst=0;
cf95b4f0 7898 clear_const(&current,dops[i].rs1);
7899 clear_const(&current,dops[i].rs2);
7900 if((dops[i].opcode&0x3E)==4) // BEQ/BNE
57871462 7901 {
7902 alloc_cc(&current,i);
7903 dirty_reg(&current,CCREG);
cf95b4f0 7904 if(dops[i].rs1) alloc_reg(&current,i,dops[i].rs1);
7905 if(dops[i].rs2) alloc_reg(&current,i,dops[i].rs2);
7906 if((dops[i].rs1&&(dops[i].rs1==dops[i+1].rt1||dops[i].rs1==dops[i+1].rt2))||
7907 (dops[i].rs2&&(dops[i].rs2==dops[i+1].rt1||dops[i].rs2==dops[i+1].rt2))) {
57871462 7908 // The delay slot overwrites one of our conditions.
7909 // Allocate the branch condition registers instead.
57871462 7910 current.isconst=0;
7911 current.wasconst=0;
7912 regs[i].wasconst=0;
cf95b4f0 7913 if(dops[i].rs1) alloc_reg(&current,i,dops[i].rs1);
7914 if(dops[i].rs2) alloc_reg(&current,i,dops[i].rs2);
57871462 7915 }
e1190b87 7916 else
7917 {
cf95b4f0 7918 dops[i].ooo=1;
e1190b87 7919 delayslot_alloc(&current,i+1);
7920 }
57871462 7921 }
7922 else
cf95b4f0 7923 if((dops[i].opcode&0x3E)==6) // BLEZ/BGTZ
57871462 7924 {
7925 alloc_cc(&current,i);
7926 dirty_reg(&current,CCREG);
cf95b4f0 7927 alloc_reg(&current,i,dops[i].rs1);
7928 if(dops[i].rs1&&(dops[i].rs1==dops[i+1].rt1||dops[i].rs1==dops[i+1].rt2)) {
57871462 7929 // The delay slot overwrites one of our conditions.
7930 // Allocate the branch condition registers instead.
57871462 7931 current.isconst=0;
7932 current.wasconst=0;
7933 regs[i].wasconst=0;
cf95b4f0 7934 if(dops[i].rs1) alloc_reg(&current,i,dops[i].rs1);
57871462 7935 }
e1190b87 7936 else
7937 {
cf95b4f0 7938 dops[i].ooo=1;
e1190b87 7939 delayslot_alloc(&current,i+1);
7940 }
57871462 7941 }
7942 else
7943 // Don't alloc the delay slot yet because we might not execute it
cf95b4f0 7944 if((dops[i].opcode&0x3E)==0x14) // BEQL/BNEL
57871462 7945 {
7946 current.isconst=0;
7947 current.wasconst=0;
7948 regs[i].wasconst=0;
7949 alloc_cc(&current,i);
7950 dirty_reg(&current,CCREG);
cf95b4f0 7951 alloc_reg(&current,i,dops[i].rs1);
7952 alloc_reg(&current,i,dops[i].rs2);
57871462 7953 }
7954 else
cf95b4f0 7955 if((dops[i].opcode&0x3E)==0x16) // BLEZL/BGTZL
57871462 7956 {
7957 current.isconst=0;
7958 current.wasconst=0;
7959 regs[i].wasconst=0;
7960 alloc_cc(&current,i);
7961 dirty_reg(&current,CCREG);
cf95b4f0 7962 alloc_reg(&current,i,dops[i].rs1);
57871462 7963 }
7964 ds=1;
7965 //current.isconst=0;
7966 break;
7967 case SJUMP:
7968 //current.isconst=0;
7969 //current.wasconst=0;
7970 //regs[i].wasconst=0;
cf95b4f0 7971 clear_const(&current,dops[i].rs1);
7972 clear_const(&current,dops[i].rt1);
7973 //if((dops[i].opcode2&0x1E)==0x0) // BLTZ/BGEZ
7974 if((dops[i].opcode2&0x0E)==0x0) // BLTZ/BGEZ
57871462 7975 {
7976 alloc_cc(&current,i);
7977 dirty_reg(&current,CCREG);
cf95b4f0 7978 alloc_reg(&current,i,dops[i].rs1);
7979 if (dops[i].rt1==31) { // BLTZAL/BGEZAL
57871462 7980 alloc_reg(&current,i,31);
7981 dirty_reg(&current,31);
57871462 7982 //#ifdef REG_PREFETCH
7983 //alloc_reg(&current,i,PTEMP);
7984 //#endif
57871462 7985 }
cf95b4f0 7986 if((dops[i].rs1&&(dops[i].rs1==dops[i+1].rt1||dops[i].rs1==dops[i+1].rt2)) // The delay slot overwrites the branch condition.
7987 ||(dops[i].rt1==31&&(dops[i+1].rs1==31||dops[i+1].rs2==31||dops[i+1].rt1==31||dops[i+1].rt2==31))) { // DS touches $ra
57871462 7988 // Allocate the branch condition registers instead.
57871462 7989 current.isconst=0;
7990 current.wasconst=0;
7991 regs[i].wasconst=0;
cf95b4f0 7992 if(dops[i].rs1) alloc_reg(&current,i,dops[i].rs1);
57871462 7993 }
e1190b87 7994 else
7995 {
cf95b4f0 7996 dops[i].ooo=1;
e1190b87 7997 delayslot_alloc(&current,i+1);
7998 }
57871462 7999 }
8000 else
8001 // Don't alloc the delay slot yet because we might not execute it
cf95b4f0 8002 if((dops[i].opcode2&0x1E)==0x2) // BLTZL/BGEZL
57871462 8003 {
8004 current.isconst=0;
8005 current.wasconst=0;
8006 regs[i].wasconst=0;
8007 alloc_cc(&current,i);
8008 dirty_reg(&current,CCREG);
cf95b4f0 8009 alloc_reg(&current,i,dops[i].rs1);
57871462 8010 }
8011 ds=1;
8012 //current.isconst=0;
8013 break;
57871462 8014 case IMM16:
8015 imm16_alloc(&current,i);
8016 break;
8017 case LOAD:
8018 case LOADLR:
8019 load_alloc(&current,i);
8020 break;
8021 case STORE:
8022 case STORELR:
8023 store_alloc(&current,i);
8024 break;
8025 case ALU:
8026 alu_alloc(&current,i);
8027 break;
8028 case SHIFT:
8029 shift_alloc(&current,i);
8030 break;
8031 case MULTDIV:
8032 multdiv_alloc(&current,i);
8033 break;
8034 case SHIFTIMM:
8035 shiftimm_alloc(&current,i);
8036 break;
8037 case MOV:
8038 mov_alloc(&current,i);
8039 break;
8040 case COP0:
8041 cop0_alloc(&current,i);
8042 break;
8043 case COP1:
81dbbf4c 8044 break;
b9b61529 8045 case COP2:
81dbbf4c 8046 cop2_alloc(&current,i);
57871462 8047 break;
8048 case C1LS:
8049 c1ls_alloc(&current,i);
8050 break;
b9b61529 8051 case C2LS:
8052 c2ls_alloc(&current,i);
8053 break;
8054 case C2OP:
8055 c2op_alloc(&current,i);
8056 break;
57871462 8057 case SYSCALL:
7139f3c8 8058 case HLECALL:
1e973cb0 8059 case INTCALL:
57871462 8060 syscall_alloc(&current,i);
8061 break;
8062 case SPAN:
8063 pagespan_alloc(&current,i);
8064 break;
8065 }
9f51b4b9 8066
57871462 8067 // Create entry (branch target) regmap
8068 for(hr=0;hr<HOST_REGS;hr++)
8069 {
581335b0 8070 int r,or;
57871462 8071 r=current.regmap[hr];
8072 if(r>=0) {
8073 if(r!=regmap_pre[i][hr]) {
8074 // TODO: delay slot (?)
8075 or=get_reg(regmap_pre[i],r); // Get old mapping for this register
8076 if(or<0||(r&63)>=TEMPREG){
8077 regs[i].regmap_entry[hr]=-1;
8078 }
8079 else
8080 {
8081 // Just move it to a different register
8082 regs[i].regmap_entry[hr]=r;
8083 // If it was dirty before, it's still dirty
8084 if((regs[i].wasdirty>>or)&1) dirty_reg(&current,r&63);
8085 }
8086 }
8087 else
8088 {
8089 // Unneeded
8090 if(r==0){
8091 regs[i].regmap_entry[hr]=0;
8092 }
8093 else
7c3a5182 8094 {
8095 assert(r<64);
57871462 8096 if((current.u>>r)&1) {
8097 regs[i].regmap_entry[hr]=-1;
8098 //regs[i].regmap[hr]=-1;
8099 current.regmap[hr]=-1;
8100 }else
8101 regs[i].regmap_entry[hr]=r;
8102 }
57871462 8103 }
8104 } else {
8105 // Branches expect CCREG to be allocated at the target
9f51b4b9 8106 if(regmap_pre[i][hr]==CCREG)
57871462 8107 regs[i].regmap_entry[hr]=CCREG;
8108 else
8109 regs[i].regmap_entry[hr]=-1;
8110 }
8111 }
8112 memcpy(regs[i].regmap,current.regmap,sizeof(current.regmap));
8113 }
27727b63 8114
cf95b4f0 8115 if(i>0&&(dops[i-1].itype==STORE||dops[i-1].itype==STORELR||(dops[i-1].itype==C2LS&&dops[i-1].opcode==0x3a))&&(u_int)imm[i-1]<0x800)
8116 current.waswritten|=1<<dops[i-1].rs1;
8117 current.waswritten&=~(1<<dops[i].rt1);
8118 current.waswritten&=~(1<<dops[i].rt2);
8119 if((dops[i].itype==STORE||dops[i].itype==STORELR||(dops[i].itype==C2LS&&dops[i].opcode==0x3a))&&(u_int)imm[i]>=0x800)
8120 current.waswritten&=~(1<<dops[i].rs1);
27727b63 8121
57871462 8122 /* Branch post-alloc */
8123 if(i>0)
8124 {
57871462 8125 current.wasdirty=current.dirty;
cf95b4f0 8126 switch(dops[i-1].itype) {
57871462 8127 case UJUMP:
8128 memcpy(&branch_regs[i-1],&current,sizeof(current));
8129 branch_regs[i-1].isconst=0;
8130 branch_regs[i-1].wasconst=0;
cf95b4f0 8131 branch_regs[i-1].u=branch_unneeded_reg[i-1]&~((1LL<<dops[i-1].rs1)|(1LL<<dops[i-1].rs2));
57871462 8132 alloc_cc(&branch_regs[i-1],i-1);
8133 dirty_reg(&branch_regs[i-1],CCREG);
cf95b4f0 8134 if(dops[i-1].rt1==31) { // JAL
57871462 8135 alloc_reg(&branch_regs[i-1],i-1,31);
8136 dirty_reg(&branch_regs[i-1],31);
57871462 8137 }
8138 memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
40fca85b 8139 memcpy(constmap[i],constmap[i-1],sizeof(constmap[i]));
57871462 8140 break;
8141 case RJUMP:
8142 memcpy(&branch_regs[i-1],&current,sizeof(current));
8143 branch_regs[i-1].isconst=0;
8144 branch_regs[i-1].wasconst=0;
cf95b4f0 8145 branch_regs[i-1].u=branch_unneeded_reg[i-1]&~((1LL<<dops[i-1].rs1)|(1LL<<dops[i-1].rs2));
57871462 8146 alloc_cc(&branch_regs[i-1],i-1);
8147 dirty_reg(&branch_regs[i-1],CCREG);
cf95b4f0 8148 alloc_reg(&branch_regs[i-1],i-1,dops[i-1].rs1);
8149 if(dops[i-1].rt1!=0) { // JALR
8150 alloc_reg(&branch_regs[i-1],i-1,dops[i-1].rt1);
8151 dirty_reg(&branch_regs[i-1],dops[i-1].rt1);
57871462 8152 }
8153 #ifdef USE_MINI_HT
cf95b4f0 8154 if(dops[i-1].rs1==31) { // JALR
57871462 8155 alloc_reg(&branch_regs[i-1],i-1,RHASH);
57871462 8156 alloc_reg(&branch_regs[i-1],i-1,RHTBL);
57871462 8157 }
8158 #endif
8159 memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
40fca85b 8160 memcpy(constmap[i],constmap[i-1],sizeof(constmap[i]));
57871462 8161 break;
8162 case CJUMP:
cf95b4f0 8163 if((dops[i-1].opcode&0x3E)==4) // BEQ/BNE
57871462 8164 {
8165 alloc_cc(&current,i-1);
8166 dirty_reg(&current,CCREG);
cf95b4f0 8167 if((dops[i-1].rs1&&(dops[i-1].rs1==dops[i].rt1||dops[i-1].rs1==dops[i].rt2))||
8168 (dops[i-1].rs2&&(dops[i-1].rs2==dops[i].rt1||dops[i-1].rs2==dops[i].rt2))) {
57871462 8169 // The delay slot overwrote one of our conditions
8170 // Delay slot goes after the test (in order)
cf95b4f0 8171 current.u=branch_unneeded_reg[i-1]&~((1LL<<dops[i].rs1)|(1LL<<dops[i].rs2));
57871462 8172 current.u|=1;
57871462 8173 delayslot_alloc(&current,i);
8174 current.isconst=0;
8175 }
8176 else
8177 {
cf95b4f0 8178 current.u=branch_unneeded_reg[i-1]&~((1LL<<dops[i-1].rs1)|(1LL<<dops[i-1].rs2));
57871462 8179 // Alloc the branch condition registers
cf95b4f0 8180 if(dops[i-1].rs1) alloc_reg(&current,i-1,dops[i-1].rs1);
8181 if(dops[i-1].rs2) alloc_reg(&current,i-1,dops[i-1].rs2);
57871462 8182 }
8183 memcpy(&branch_regs[i-1],&current,sizeof(current));
8184 branch_regs[i-1].isconst=0;
8185 branch_regs[i-1].wasconst=0;
8186 memcpy(&branch_regs[i-1].regmap_entry,&current.regmap,sizeof(current.regmap));
40fca85b 8187 memcpy(constmap[i],constmap[i-1],sizeof(constmap[i]));
57871462 8188 }
8189 else
cf95b4f0 8190 if((dops[i-1].opcode&0x3E)==6) // BLEZ/BGTZ
57871462 8191 {
8192 alloc_cc(&current,i-1);
8193 dirty_reg(&current,CCREG);
cf95b4f0 8194 if(dops[i-1].rs1==dops[i].rt1||dops[i-1].rs1==dops[i].rt2) {
57871462 8195 // The delay slot overwrote the branch condition
8196 // Delay slot goes after the test (in order)
cf95b4f0 8197 current.u=branch_unneeded_reg[i-1]&~((1LL<<dops[i].rs1)|(1LL<<dops[i].rs2));
57871462 8198 current.u|=1;
57871462 8199 delayslot_alloc(&current,i);
8200 current.isconst=0;
8201 }
8202 else
8203 {
cf95b4f0 8204 current.u=branch_unneeded_reg[i-1]&~(1LL<<dops[i-1].rs1);
57871462 8205 // Alloc the branch condition register
cf95b4f0 8206 alloc_reg(&current,i-1,dops[i-1].rs1);
57871462 8207 }
8208 memcpy(&branch_regs[i-1],&current,sizeof(current));
8209 branch_regs[i-1].isconst=0;
8210 branch_regs[i-1].wasconst=0;
8211 memcpy(&branch_regs[i-1].regmap_entry,&current.regmap,sizeof(current.regmap));
40fca85b 8212 memcpy(constmap[i],constmap[i-1],sizeof(constmap[i]));
57871462 8213 }
8214 else
8215 // Alloc the delay slot in case the branch is taken
cf95b4f0 8216 if((dops[i-1].opcode&0x3E)==0x14) // BEQL/BNEL
57871462 8217 {
8218 memcpy(&branch_regs[i-1],&current,sizeof(current));
cf95b4f0 8219 branch_regs[i-1].u=(branch_unneeded_reg[i-1]&~((1LL<<dops[i].rs1)|(1LL<<dops[i].rs2)|(1LL<<dops[i].rt1)|(1LL<<dops[i].rt2)))|1;
57871462 8220 alloc_cc(&branch_regs[i-1],i);
8221 dirty_reg(&branch_regs[i-1],CCREG);
8222 delayslot_alloc(&branch_regs[i-1],i);
8223 branch_regs[i-1].isconst=0;
8224 alloc_reg(&current,i,CCREG); // Not taken path
8225 dirty_reg(&current,CCREG);
8226 memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
8227 }
8228 else
cf95b4f0 8229 if((dops[i-1].opcode&0x3E)==0x16) // BLEZL/BGTZL
57871462 8230 {
8231 memcpy(&branch_regs[i-1],&current,sizeof(current));
cf95b4f0 8232 branch_regs[i-1].u=(branch_unneeded_reg[i-1]&~((1LL<<dops[i].rs1)|(1LL<<dops[i].rs2)|(1LL<<dops[i].rt1)|(1LL<<dops[i].rt2)))|1;
57871462 8233 alloc_cc(&branch_regs[i-1],i);
8234 dirty_reg(&branch_regs[i-1],CCREG);
8235 delayslot_alloc(&branch_regs[i-1],i);
8236 branch_regs[i-1].isconst=0;
8237 alloc_reg(&current,i,CCREG); // Not taken path
8238 dirty_reg(&current,CCREG);
8239 memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
8240 }
8241 break;
8242 case SJUMP:
cf95b4f0 8243 //if((dops[i-1].opcode2&0x1E)==0) // BLTZ/BGEZ
8244 if((dops[i-1].opcode2&0x0E)==0) // BLTZ/BGEZ
57871462 8245 {
8246 alloc_cc(&current,i-1);
8247 dirty_reg(&current,CCREG);
cf95b4f0 8248 if(dops[i-1].rs1==dops[i].rt1||dops[i-1].rs1==dops[i].rt2) {
57871462 8249 // The delay slot overwrote the branch condition
8250 // Delay slot goes after the test (in order)
cf95b4f0 8251 current.u=branch_unneeded_reg[i-1]&~((1LL<<dops[i].rs1)|(1LL<<dops[i].rs2));
57871462 8252 current.u|=1;
57871462 8253 delayslot_alloc(&current,i);
8254 current.isconst=0;
8255 }
8256 else
8257 {
cf95b4f0 8258 current.u=branch_unneeded_reg[i-1]&~(1LL<<dops[i-1].rs1);
57871462 8259 // Alloc the branch condition register
cf95b4f0 8260 alloc_reg(&current,i-1,dops[i-1].rs1);
57871462 8261 }
8262 memcpy(&branch_regs[i-1],&current,sizeof(current));
8263 branch_regs[i-1].isconst=0;
8264 branch_regs[i-1].wasconst=0;
8265 memcpy(&branch_regs[i-1].regmap_entry,&current.regmap,sizeof(current.regmap));
40fca85b 8266 memcpy(constmap[i],constmap[i-1],sizeof(constmap[i]));
57871462 8267 }
8268 else
8269 // Alloc the delay slot in case the branch is taken
cf95b4f0 8270 if((dops[i-1].opcode2&0x1E)==2) // BLTZL/BGEZL
57871462 8271 {
8272 memcpy(&branch_regs[i-1],&current,sizeof(current));
cf95b4f0 8273 branch_regs[i-1].u=(branch_unneeded_reg[i-1]&~((1LL<<dops[i].rs1)|(1LL<<dops[i].rs2)|(1LL<<dops[i].rt1)|(1LL<<dops[i].rt2)))|1;
57871462 8274 alloc_cc(&branch_regs[i-1],i);
8275 dirty_reg(&branch_regs[i-1],CCREG);
8276 delayslot_alloc(&branch_regs[i-1],i);
8277 branch_regs[i-1].isconst=0;
8278 alloc_reg(&current,i,CCREG); // Not taken path
8279 dirty_reg(&current,CCREG);
8280 memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
8281 }
8282 // FIXME: BLTZAL/BGEZAL
cf95b4f0 8283 if(dops[i-1].opcode2&0x10) { // BxxZAL
57871462 8284 alloc_reg(&branch_regs[i-1],i-1,31);
8285 dirty_reg(&branch_regs[i-1],31);
57871462 8286 }
8287 break;
57871462 8288 }
8289
fe807a8a 8290 if (dops[i-1].is_ujump)
57871462 8291 {
cf95b4f0 8292 if(dops[i-1].rt1==31) // JAL/JALR
57871462 8293 {
8294 // Subroutine call will return here, don't alloc any registers
57871462 8295 current.dirty=0;
8296 clear_all_regs(current.regmap);
8297 alloc_reg(&current,i,CCREG);
8298 dirty_reg(&current,CCREG);
8299 }
8300 else if(i+1<slen)
8301 {
8302 // Internal branch will jump here, match registers to caller
57871462 8303 current.dirty=0;
8304 clear_all_regs(current.regmap);
8305 alloc_reg(&current,i,CCREG);
8306 dirty_reg(&current,CCREG);
8307 for(j=i-1;j>=0;j--)
8308 {
8309 if(ba[j]==start+i*4+4) {
8310 memcpy(current.regmap,branch_regs[j].regmap,sizeof(current.regmap));
57871462 8311 current.dirty=branch_regs[j].dirty;
8312 break;
8313 }
8314 }
8315 while(j>=0) {
8316 if(ba[j]==start+i*4+4) {
8317 for(hr=0;hr<HOST_REGS;hr++) {
8318 if(current.regmap[hr]!=branch_regs[j].regmap[hr]) {
8319 current.regmap[hr]=-1;
8320 }
57871462 8321 current.dirty&=branch_regs[j].dirty;
8322 }
8323 }
8324 j--;
8325 }
8326 }
8327 }
8328 }
8329
8330 // Count cycles in between branches
2330734f 8331 ccadj[i] = CLOCK_ADJUST(cc);
fe807a8a 8332 if (i > 0 && (dops[i-1].is_jump || dops[i].itype == SYSCALL || dops[i].itype == HLECALL))
57871462 8333 {
8334 cc=0;
8335 }
71e490c5 8336#if !defined(DRC_DBG)
cf95b4f0 8337 else if(dops[i].itype==C2OP&&gte_cycletab[source[i]&0x3f]>2)
054175e9 8338 {
81dbbf4c 8339 // this should really be removed since the real stalls have been implemented,
8340 // but doing so causes sizeable perf regression against the older version
8341 u_int gtec = gte_cycletab[source[i] & 0x3f];
32631e6a 8342 cc += HACK_ENABLED(NDHACK_NO_STALLS) ? gtec/2 : 2;
fb407447 8343 }
cf95b4f0 8344 else if(i>1&&dops[i].itype==STORE&&dops[i-1].itype==STORE&&dops[i-2].itype==STORE&&!dops[i].bt)
5fdcbb5a 8345 {
8346 cc+=4;
8347 }
cf95b4f0 8348 else if(dops[i].itype==C2LS)
fb407447 8349 {
81dbbf4c 8350 // same as with C2OP
32631e6a 8351 cc += HACK_ENABLED(NDHACK_NO_STALLS) ? 4 : 2;
fb407447 8352 }
8353#endif
57871462 8354 else
8355 {
8356 cc++;
8357 }
8358
cf95b4f0 8359 if(!dops[i].is_ds) {
57871462 8360 regs[i].dirty=current.dirty;
8361 regs[i].isconst=current.isconst;
40fca85b 8362 memcpy(constmap[i],current_constmap,sizeof(constmap[i]));
57871462 8363 }
8364 for(hr=0;hr<HOST_REGS;hr++) {
8365 if(hr!=EXCLUDE_REG&&regs[i].regmap[hr]>=0) {
8366 if(regmap_pre[i][hr]!=regs[i].regmap[hr]) {
8367 regs[i].wasconst&=~(1<<hr);
8368 }
8369 }
8370 }
8371 if(current.regmap[HOST_BTREG]==BTREG) current.regmap[HOST_BTREG]=-1;
27727b63 8372 regs[i].waswritten=current.waswritten;
57871462 8373 }
9f51b4b9 8374
57871462 8375 /* Pass 4 - Cull unused host registers */
9f51b4b9 8376
57871462 8377 uint64_t nr=0;
9f51b4b9 8378
57871462 8379 for (i=slen-1;i>=0;i--)
8380 {
8381 int hr;
fe807a8a 8382 if(dops[i].is_jump)
57871462 8383 {
8384 if(ba[i]<start || ba[i]>=(start+slen*4))
8385 {
8386 // Branch out of this block, don't need anything
8387 nr=0;
8388 }
8389 else
8390 {
8391 // Internal branch
8392 // Need whatever matches the target
8393 nr=0;
8394 int t=(ba[i]-start)>>2;
8395 for(hr=0;hr<HOST_REGS;hr++)
8396 {
8397 if(regs[i].regmap_entry[hr]>=0) {
8398 if(regs[i].regmap_entry[hr]==regs[t].regmap_entry[hr]) nr|=1<<hr;
8399 }
8400 }
8401 }
8402 // Conditional branch may need registers for following instructions
fe807a8a 8403 if (!dops[i].is_ujump)
57871462 8404 {
8405 if(i<slen-2) {
8406 nr|=needed_reg[i+2];
8407 for(hr=0;hr<HOST_REGS;hr++)
8408 {
8409 if(regmap_pre[i+2][hr]>=0&&get_reg(regs[i+2].regmap_entry,regmap_pre[i+2][hr])<0) nr&=~(1<<hr);
8410 //if((regmap_entry[i+2][hr])>=0) if(!((nr>>hr)&1)) printf("%x-bogus(%d=%d)\n",start+i*4,hr,regmap_entry[i+2][hr]);
8411 }
8412 }
8413 }
8414 // Don't need stuff which is overwritten
f5955059 8415 //if(regs[i].regmap[hr]!=regmap_pre[i][hr]) nr&=~(1<<hr);
8416 //if(regs[i].regmap[hr]<0) nr&=~(1<<hr);
57871462 8417 // Merge in delay slot
8418 for(hr=0;hr<HOST_REGS;hr++)
8419 {
fe807a8a 8420 if(dops[i+1].rt1&&dops[i+1].rt1==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
8421 if(dops[i+1].rt2&&dops[i+1].rt2==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
cf95b4f0 8422 if(dops[i+1].rs1==regmap_pre[i][hr]) nr|=1<<hr;
8423 if(dops[i+1].rs2==regmap_pre[i][hr]) nr|=1<<hr;
8424 if(dops[i+1].rs1==regs[i].regmap_entry[hr]) nr|=1<<hr;
8425 if(dops[i+1].rs2==regs[i].regmap_entry[hr]) nr|=1<<hr;
37387d8b 8426 if(ram_offset && (dops[i+1].is_load || dops[i+1].is_store)) {
8427 if(regmap_pre[i][hr]==ROREG) nr|=1<<hr;
8428 if(regs[i].regmap_entry[hr]==ROREG) nr|=1<<hr;
8429 }
8430 if(dops[i+1].is_store) {
57871462 8431 if(regmap_pre[i][hr]==INVCP) nr|=1<<hr;
8432 if(regs[i].regmap_entry[hr]==INVCP) nr|=1<<hr;
8433 }
8434 }
8435 }
cf95b4f0 8436 else if(dops[i].itype==SYSCALL||dops[i].itype==HLECALL||dops[i].itype==INTCALL)
57871462 8437 {
8438 // SYSCALL instruction (software interrupt)
8439 nr=0;
8440 }
cf95b4f0 8441 else if(dops[i].itype==COP0 && (source[i]&0x3f)==0x18)
57871462 8442 {
8443 // ERET instruction (return from interrupt)
8444 nr=0;
8445 }
8446 else // Non-branch
8447 {
8448 if(i<slen-1) {
8449 for(hr=0;hr<HOST_REGS;hr++) {
8450 if(regmap_pre[i+1][hr]>=0&&get_reg(regs[i+1].regmap_entry,regmap_pre[i+1][hr])<0) nr&=~(1<<hr);
8451 if(regs[i].regmap[hr]!=regmap_pre[i+1][hr]) nr&=~(1<<hr);
8452 if(regs[i].regmap[hr]!=regmap_pre[i][hr]) nr&=~(1<<hr);
8453 if(regs[i].regmap[hr]<0) nr&=~(1<<hr);
8454 }
8455 }
8456 }
8457 for(hr=0;hr<HOST_REGS;hr++)
8458 {
8459 // Overwritten registers are not needed
cf95b4f0 8460 if(dops[i].rt1&&dops[i].rt1==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
8461 if(dops[i].rt2&&dops[i].rt2==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
57871462 8462 if(FTEMP==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
8463 // Source registers are needed
cf95b4f0 8464 if(dops[i].rs1==regmap_pre[i][hr]) nr|=1<<hr;
8465 if(dops[i].rs2==regmap_pre[i][hr]) nr|=1<<hr;
8466 if(dops[i].rs1==regs[i].regmap_entry[hr]) nr|=1<<hr;
8467 if(dops[i].rs2==regs[i].regmap_entry[hr]) nr|=1<<hr;
37387d8b 8468 if(ram_offset && (dops[i].is_load || dops[i].is_store)) {
8469 if(regmap_pre[i][hr]==ROREG) nr|=1<<hr;
8470 if(regs[i].regmap_entry[hr]==ROREG) nr|=1<<hr;
8471 }
8472 if(dops[i].is_store) {
57871462 8473 if(regmap_pre[i][hr]==INVCP) nr|=1<<hr;
8474 if(regs[i].regmap_entry[hr]==INVCP) nr|=1<<hr;
8475 }
8476 // Don't store a register immediately after writing it,
8477 // may prevent dual-issue.
8478 // But do so if this is a branch target, otherwise we
8479 // might have to load the register before the branch.
cf95b4f0 8480 if(i>0&&!dops[i].bt&&((regs[i].wasdirty>>hr)&1)) {
7c3a5182 8481 if((regmap_pre[i][hr]>0&&!((unneeded_reg[i]>>regmap_pre[i][hr])&1))) {
cf95b4f0 8482 if(dops[i-1].rt1==(regmap_pre[i][hr]&63)) nr|=1<<hr;
8483 if(dops[i-1].rt2==(regmap_pre[i][hr]&63)) nr|=1<<hr;
57871462 8484 }
7c3a5182 8485 if((regs[i].regmap_entry[hr]>0&&!((unneeded_reg[i]>>regs[i].regmap_entry[hr])&1))) {
cf95b4f0 8486 if(dops[i-1].rt1==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
8487 if(dops[i-1].rt2==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
57871462 8488 }
8489 }
8490 }
8491 // Cycle count is needed at branches. Assume it is needed at the target too.
cf95b4f0 8492 if(i==0||dops[i].bt||dops[i].itype==CJUMP||dops[i].itype==SPAN) {
57871462 8493 if(regmap_pre[i][HOST_CCREG]==CCREG) nr|=1<<HOST_CCREG;
8494 if(regs[i].regmap_entry[HOST_CCREG]==CCREG) nr|=1<<HOST_CCREG;
8495 }
8496 // Save it
8497 needed_reg[i]=nr;
9f51b4b9 8498
57871462 8499 // Deallocate unneeded registers
8500 for(hr=0;hr<HOST_REGS;hr++)
8501 {
8502 if(!((nr>>hr)&1)) {
8503 if(regs[i].regmap_entry[hr]!=CCREG) regs[i].regmap_entry[hr]=-1;
fe807a8a 8504 if(dops[i].is_jump)
57871462 8505 {
37387d8b 8506 int map1 = 0, map2 = 0, temp = 0; // or -1 ??
8507 if (dops[i+1].is_load || dops[i+1].is_store)
8508 map1 = ROREG;
8509 if (dops[i+1].is_store)
8510 map2 = INVCP;
8511 if(dops[i+1].itype==LOADLR || dops[i+1].itype==STORELR || dops[i+1].itype==C2LS)
8512 temp = FTEMP;
cf95b4f0 8513 if((regs[i].regmap[hr]&63)!=dops[i].rs1 && (regs[i].regmap[hr]&63)!=dops[i].rs2 &&
8514 (regs[i].regmap[hr]&63)!=dops[i].rt1 && (regs[i].regmap[hr]&63)!=dops[i].rt2 &&
8515 (regs[i].regmap[hr]&63)!=dops[i+1].rt1 && (regs[i].regmap[hr]&63)!=dops[i+1].rt2 &&
8516 regs[i].regmap[hr]!=dops[i+1].rs1 && regs[i].regmap[hr]!=dops[i+1].rs2 &&
57871462 8517 (regs[i].regmap[hr]&63)!=temp && regs[i].regmap[hr]!=PTEMP &&
8518 regs[i].regmap[hr]!=RHASH && regs[i].regmap[hr]!=RHTBL &&
8519 regs[i].regmap[hr]!=RTEMP && regs[i].regmap[hr]!=CCREG &&
37387d8b 8520 regs[i].regmap[hr]!=map1 && regs[i].regmap[hr]!=map2)
57871462 8521 {
8522 regs[i].regmap[hr]=-1;
8523 regs[i].isconst&=~(1<<hr);
a550c61c 8524 regs[i].dirty&=~(1<<hr);
8525 regs[i+1].wasdirty&=~(1<<hr);
cf95b4f0 8526 if((branch_regs[i].regmap[hr]&63)!=dops[i].rs1 && (branch_regs[i].regmap[hr]&63)!=dops[i].rs2 &&
8527 (branch_regs[i].regmap[hr]&63)!=dops[i].rt1 && (branch_regs[i].regmap[hr]&63)!=dops[i].rt2 &&
8528 (branch_regs[i].regmap[hr]&63)!=dops[i+1].rt1 && (branch_regs[i].regmap[hr]&63)!=dops[i+1].rt2 &&
8529 branch_regs[i].regmap[hr]!=dops[i+1].rs1 && branch_regs[i].regmap[hr]!=dops[i+1].rs2 &&
57871462 8530 (branch_regs[i].regmap[hr]&63)!=temp && branch_regs[i].regmap[hr]!=PTEMP &&
8531 branch_regs[i].regmap[hr]!=RHASH && branch_regs[i].regmap[hr]!=RHTBL &&
8532 branch_regs[i].regmap[hr]!=RTEMP && branch_regs[i].regmap[hr]!=CCREG &&
37387d8b 8533 branch_regs[i].regmap[hr]!=map1 && branch_regs[i].regmap[hr]!=map2)
57871462 8534 {
8535 branch_regs[i].regmap[hr]=-1;
8536 branch_regs[i].regmap_entry[hr]=-1;
fe807a8a 8537 if (!dops[i].is_ujump)
57871462 8538 {
fe807a8a 8539 if (i < slen-2) {
57871462 8540 regmap_pre[i+2][hr]=-1;
79c75f1b 8541 regs[i+2].wasconst&=~(1<<hr);
57871462 8542 }
8543 }
8544 }
8545 }
8546 }
8547 else
8548 {
8549 // Non-branch
8550 if(i>0)
8551 {
37387d8b 8552 int map1 = -1, map2 = -1, temp=-1;
8553 if (dops[i].is_load || dops[i].is_store)
8554 map1 = ROREG;
8555 if (dops[i].is_store)
8556 map2 = INVCP;
8557 if (dops[i].itype==LOADLR || dops[i].itype==STORELR || dops[i].itype==C2LS)
8558 temp = FTEMP;
cf95b4f0 8559 if((regs[i].regmap[hr]&63)!=dops[i].rt1 && (regs[i].regmap[hr]&63)!=dops[i].rt2 &&
8560 regs[i].regmap[hr]!=dops[i].rs1 && regs[i].regmap[hr]!=dops[i].rs2 &&
37387d8b 8561 (regs[i].regmap[hr]&63)!=temp && regs[i].regmap[hr]!=map1 && regs[i].regmap[hr]!=map2 &&
4b1c7cd1 8562 //(dops[i].itype!=SPAN||regs[i].regmap[hr]!=CCREG)
8563 regs[i].regmap[hr] != CCREG)
57871462 8564 {
cf95b4f0 8565 if(i<slen-1&&!dops[i].is_ds) {
ad49de89 8566 assert(regs[i].regmap[hr]<64);
afec9d44 8567 if(regmap_pre[i+1][hr]!=-1 || regs[i].regmap[hr]>0)
57871462 8568 if(regmap_pre[i+1][hr]!=regs[i].regmap[hr])
57871462 8569 {
c43b5311 8570 SysPrintf("fail: %x (%d %d!=%d)\n",start+i*4,hr,regmap_pre[i+1][hr],regs[i].regmap[hr]);
57871462 8571 assert(regmap_pre[i+1][hr]==regs[i].regmap[hr]);
8572 }
8573 regmap_pre[i+1][hr]=-1;
8574 if(regs[i+1].regmap_entry[hr]==CCREG) regs[i+1].regmap_entry[hr]=-1;
79c75f1b 8575 regs[i+1].wasconst&=~(1<<hr);
57871462 8576 }
8577 regs[i].regmap[hr]=-1;
8578 regs[i].isconst&=~(1<<hr);
a550c61c 8579 regs[i].dirty&=~(1<<hr);
8580 regs[i+1].wasdirty&=~(1<<hr);
57871462 8581 }
8582 }
8583 }
3968e69e 8584 } // if needed
8585 } // for hr
57871462 8586 }
9f51b4b9 8587
57871462 8588 /* Pass 5 - Pre-allocate registers */
9f51b4b9 8589
57871462 8590 // If a register is allocated during a loop, try to allocate it for the
8591 // entire loop, if possible. This avoids loading/storing registers
8592 // inside of the loop.
9f51b4b9 8593
57871462 8594 signed char f_regmap[HOST_REGS];
8595 clear_all_regs(f_regmap);
8596 for(i=0;i<slen-1;i++)
8597 {
cf95b4f0 8598 if(dops[i].itype==UJUMP||dops[i].itype==CJUMP||dops[i].itype==SJUMP)
57871462 8599 {
9f51b4b9 8600 if(ba[i]>=start && ba[i]<(start+i*4))
cf95b4f0 8601 if(dops[i+1].itype==NOP||dops[i+1].itype==MOV||dops[i+1].itype==ALU
8602 ||dops[i+1].itype==SHIFTIMM||dops[i+1].itype==IMM16||dops[i+1].itype==LOAD
8603 ||dops[i+1].itype==STORE||dops[i+1].itype==STORELR||dops[i+1].itype==C1LS
8604 ||dops[i+1].itype==SHIFT||dops[i+1].itype==COP1
8605 ||dops[i+1].itype==COP2||dops[i+1].itype==C2LS||dops[i+1].itype==C2OP)
57871462 8606 {
8607 int t=(ba[i]-start)>>2;
fe807a8a 8608 if(t > 0 && !dops[t-1].is_jump) // loop_preload can't handle jumps into delay slots
cf95b4f0 8609 if(t<2||(dops[t-2].itype!=UJUMP&&dops[t-2].itype!=RJUMP)||dops[t-2].rt1!=31) // call/ret assumes no registers allocated
57871462 8610 for(hr=0;hr<HOST_REGS;hr++)
8611 {
7c3a5182 8612 if(regs[i].regmap[hr]>=0) {
b372a952 8613 if(f_regmap[hr]!=regs[i].regmap[hr]) {
8614 // dealloc old register
8615 int n;
8616 for(n=0;n<HOST_REGS;n++)
8617 {
8618 if(f_regmap[n]==regs[i].regmap[hr]) {f_regmap[n]=-1;}
8619 }
8620 // and alloc new one
8621 f_regmap[hr]=regs[i].regmap[hr];
8622 }
8623 }
7c3a5182 8624 if(branch_regs[i].regmap[hr]>=0) {
b372a952 8625 if(f_regmap[hr]!=branch_regs[i].regmap[hr]) {
8626 // dealloc old register
8627 int n;
8628 for(n=0;n<HOST_REGS;n++)
8629 {
8630 if(f_regmap[n]==branch_regs[i].regmap[hr]) {f_regmap[n]=-1;}
8631 }
8632 // and alloc new one
8633 f_regmap[hr]=branch_regs[i].regmap[hr];
8634 }
8635 }
cf95b4f0 8636 if(dops[i].ooo) {
9f51b4b9 8637 if(count_free_regs(regs[i].regmap)<=minimum_free_regs[i+1])
e1190b87 8638 f_regmap[hr]=branch_regs[i].regmap[hr];
8639 }else{
9f51b4b9 8640 if(count_free_regs(branch_regs[i].regmap)<=minimum_free_regs[i+1])
57871462 8641 f_regmap[hr]=branch_regs[i].regmap[hr];
8642 }
8643 // Avoid dirty->clean transition
e1190b87 8644 #ifdef DESTRUCTIVE_WRITEBACK
57871462 8645 if(t>0) if(get_reg(regmap_pre[t],f_regmap[hr])>=0) if((regs[t].wasdirty>>get_reg(regmap_pre[t],f_regmap[hr]))&1) f_regmap[hr]=-1;
e1190b87 8646 #endif
8647 // This check is only strictly required in the DESTRUCTIVE_WRITEBACK
8648 // case above, however it's always a good idea. We can't hoist the
8649 // load if the register was already allocated, so there's no point
8650 // wasting time analyzing most of these cases. It only "succeeds"
8651 // when the mapping was different and the load can be replaced with
8652 // a mov, which is of negligible benefit. So such cases are
8653 // skipped below.
57871462 8654 if(f_regmap[hr]>0) {
198df76f 8655 if(regs[t].regmap[hr]==f_regmap[hr]||(regs[t].regmap_entry[hr]<0&&get_reg(regmap_pre[t],f_regmap[hr])<0)) {
57871462 8656 int r=f_regmap[hr];
8657 for(j=t;j<=i;j++)
8658 {
8659 //printf("Test %x -> %x, %x %d/%d\n",start+i*4,ba[i],start+j*4,hr,r);
8660 if(r<34&&((unneeded_reg[j]>>r)&1)) break;
00fa9369 8661 assert(r < 64);
57871462 8662 if(regs[j].regmap[hr]==f_regmap[hr]&&(f_regmap[hr]&63)<TEMPREG) {
8663 //printf("Hit %x -> %x, %x %d/%d\n",start+i*4,ba[i],start+j*4,hr,r);
8664 int k;
8665 if(regs[i].regmap[hr]==-1&&branch_regs[i].regmap[hr]==-1) {
670c0f22 8666 if(get_reg(regs[i].regmap,f_regmap[hr])>=0) break;
57871462 8667 if(get_reg(regs[i+2].regmap,f_regmap[hr])>=0) break;
57871462 8668 k=i;
8669 while(k>1&&regs[k-1].regmap[hr]==-1) {
e1190b87 8670 if(count_free_regs(regs[k-1].regmap)<=minimum_free_regs[k-1]) {
8671 //printf("no free regs for store %x\n",start+(k-1)*4);
8672 break;
57871462 8673 }
57871462 8674 if(get_reg(regs[k-1].regmap,f_regmap[hr])>=0) {
8675 //printf("no-match due to different register\n");
8676 break;
8677 }
fe807a8a 8678 if (dops[k-2].is_jump) {
57871462 8679 //printf("no-match due to branch\n");
8680 break;
8681 }
8682 // call/ret fast path assumes no registers allocated
cf95b4f0 8683 if(k>2&&(dops[k-3].itype==UJUMP||dops[k-3].itype==RJUMP)&&dops[k-3].rt1==31) {
57871462 8684 break;
8685 }
57871462 8686 k--;
8687 }
57871462 8688 if(regs[k-1].regmap[hr]==f_regmap[hr]&&regmap_pre[k][hr]==f_regmap[hr]) {
8689 //printf("Extend r%d, %x ->\n",hr,start+k*4);
8690 while(k<i) {
8691 regs[k].regmap_entry[hr]=f_regmap[hr];
8692 regs[k].regmap[hr]=f_regmap[hr];
8693 regmap_pre[k+1][hr]=f_regmap[hr];
8694 regs[k].wasdirty&=~(1<<hr);
8695 regs[k].dirty&=~(1<<hr);
8696 regs[k].wasdirty|=(1<<hr)&regs[k-1].dirty;
8697 regs[k].dirty|=(1<<hr)&regs[k].wasdirty;
8698 regs[k].wasconst&=~(1<<hr);
8699 regs[k].isconst&=~(1<<hr);
8700 k++;
8701 }
8702 }
8703 else {
8704 //printf("Fail Extend r%d, %x ->\n",hr,start+k*4);
8705 break;
8706 }
8707 assert(regs[i-1].regmap[hr]==f_regmap[hr]);
8708 if(regs[i-1].regmap[hr]==f_regmap[hr]&&regmap_pre[i][hr]==f_regmap[hr]) {
8709 //printf("OK fill %x (r%d)\n",start+i*4,hr);
8710 regs[i].regmap_entry[hr]=f_regmap[hr];
8711 regs[i].regmap[hr]=f_regmap[hr];
8712 regs[i].wasdirty&=~(1<<hr);
8713 regs[i].dirty&=~(1<<hr);
8714 regs[i].wasdirty|=(1<<hr)&regs[i-1].dirty;
8715 regs[i].dirty|=(1<<hr)&regs[i-1].dirty;
8716 regs[i].wasconst&=~(1<<hr);
8717 regs[i].isconst&=~(1<<hr);
8718 branch_regs[i].regmap_entry[hr]=f_regmap[hr];
8719 branch_regs[i].wasdirty&=~(1<<hr);
8720 branch_regs[i].wasdirty|=(1<<hr)&regs[i].dirty;
8721 branch_regs[i].regmap[hr]=f_regmap[hr];
8722 branch_regs[i].dirty&=~(1<<hr);
8723 branch_regs[i].dirty|=(1<<hr)&regs[i].dirty;
8724 branch_regs[i].wasconst&=~(1<<hr);
8725 branch_regs[i].isconst&=~(1<<hr);
fe807a8a 8726 if (!dops[i].is_ujump) {
57871462 8727 regmap_pre[i+2][hr]=f_regmap[hr];
8728 regs[i+2].wasdirty&=~(1<<hr);
8729 regs[i+2].wasdirty|=(1<<hr)&regs[i].dirty;
57871462 8730 }
8731 }
8732 }
8733 for(k=t;k<j;k++) {
e1190b87 8734 // Alloc register clean at beginning of loop,
8735 // but may dirty it in pass 6
57871462 8736 regs[k].regmap_entry[hr]=f_regmap[hr];
8737 regs[k].regmap[hr]=f_regmap[hr];
57871462 8738 regs[k].dirty&=~(1<<hr);
8739 regs[k].wasconst&=~(1<<hr);
8740 regs[k].isconst&=~(1<<hr);
fe807a8a 8741 if (dops[k].is_jump) {
e1190b87 8742 branch_regs[k].regmap_entry[hr]=f_regmap[hr];
8743 branch_regs[k].regmap[hr]=f_regmap[hr];
8744 branch_regs[k].dirty&=~(1<<hr);
8745 branch_regs[k].wasconst&=~(1<<hr);
8746 branch_regs[k].isconst&=~(1<<hr);
fe807a8a 8747 if (!dops[k].is_ujump) {
e1190b87 8748 regmap_pre[k+2][hr]=f_regmap[hr];
8749 regs[k+2].wasdirty&=~(1<<hr);
e1190b87 8750 }
8751 }
8752 else
8753 {
8754 regmap_pre[k+1][hr]=f_regmap[hr];
8755 regs[k+1].wasdirty&=~(1<<hr);
8756 }
57871462 8757 }
8758 if(regs[j].regmap[hr]==f_regmap[hr])
8759 regs[j].regmap_entry[hr]=f_regmap[hr];
8760 break;
8761 }
8762 if(j==i) break;
8763 if(regs[j].regmap[hr]>=0)
8764 break;
8765 if(get_reg(regs[j].regmap,f_regmap[hr])>=0) {
8766 //printf("no-match due to different register\n");
8767 break;
8768 }
fe807a8a 8769 if (dops[j].is_ujump)
e1190b87 8770 {
8771 // Stop on unconditional branch
8772 break;
8773 }
cf95b4f0 8774 if(dops[j].itype==CJUMP||dops[j].itype==SJUMP)
e1190b87 8775 {
cf95b4f0 8776 if(dops[j].ooo) {
9f51b4b9 8777 if(count_free_regs(regs[j].regmap)<=minimum_free_regs[j+1])
e1190b87 8778 break;
8779 }else{
9f51b4b9 8780 if(count_free_regs(branch_regs[j].regmap)<=minimum_free_regs[j+1])
e1190b87 8781 break;
8782 }
8783 if(get_reg(branch_regs[j].regmap,f_regmap[hr])>=0) {
8784 //printf("no-match due to different register (branch)\n");
57871462 8785 break;
8786 }
8787 }
e1190b87 8788 if(count_free_regs(regs[j].regmap)<=minimum_free_regs[j]) {
8789 //printf("No free regs for store %x\n",start+j*4);
8790 break;
8791 }
ad49de89 8792 assert(f_regmap[hr]<64);
57871462 8793 }
8794 }
8795 }
8796 }
8797 }
8798 }else{
198df76f 8799 // Non branch or undetermined branch target
57871462 8800 for(hr=0;hr<HOST_REGS;hr++)
8801 {
8802 if(hr!=EXCLUDE_REG) {
7c3a5182 8803 if(regs[i].regmap[hr]>=0) {
b372a952 8804 if(f_regmap[hr]!=regs[i].regmap[hr]) {
8805 // dealloc old register
8806 int n;
8807 for(n=0;n<HOST_REGS;n++)
8808 {
8809 if(f_regmap[n]==regs[i].regmap[hr]) {f_regmap[n]=-1;}
8810 }
8811 // and alloc new one
8812 f_regmap[hr]=regs[i].regmap[hr];
8813 }
8814 }
57871462 8815 }
8816 }
8817 // Try to restore cycle count at branch targets
cf95b4f0 8818 if(dops[i].bt) {
57871462 8819 for(j=i;j<slen-1;j++) {
8820 if(regs[j].regmap[HOST_CCREG]!=-1) break;
e1190b87 8821 if(count_free_regs(regs[j].regmap)<=minimum_free_regs[j]) {
8822 //printf("no free regs for store %x\n",start+j*4);
8823 break;
57871462 8824 }
57871462 8825 }
8826 if(regs[j].regmap[HOST_CCREG]==CCREG) {
8827 int k=i;
8828 //printf("Extend CC, %x -> %x\n",start+k*4,start+j*4);
8829 while(k<j) {
8830 regs[k].regmap_entry[HOST_CCREG]=CCREG;
8831 regs[k].regmap[HOST_CCREG]=CCREG;
8832 regmap_pre[k+1][HOST_CCREG]=CCREG;
8833 regs[k+1].wasdirty|=1<<HOST_CCREG;
8834 regs[k].dirty|=1<<HOST_CCREG;
8835 regs[k].wasconst&=~(1<<HOST_CCREG);
8836 regs[k].isconst&=~(1<<HOST_CCREG);
8837 k++;
8838 }
9f51b4b9 8839 regs[j].regmap_entry[HOST_CCREG]=CCREG;
57871462 8840 }
8841 // Work backwards from the branch target
8842 if(j>i&&f_regmap[HOST_CCREG]==CCREG)
8843 {
8844 //printf("Extend backwards\n");
8845 int k;
8846 k=i;
8847 while(regs[k-1].regmap[HOST_CCREG]==-1) {
e1190b87 8848 if(count_free_regs(regs[k-1].regmap)<=minimum_free_regs[k-1]) {
8849 //printf("no free regs for store %x\n",start+(k-1)*4);
8850 break;
57871462 8851 }
57871462 8852 k--;
8853 }
8854 if(regs[k-1].regmap[HOST_CCREG]==CCREG) {
8855 //printf("Extend CC, %x ->\n",start+k*4);
8856 while(k<=i) {
8857 regs[k].regmap_entry[HOST_CCREG]=CCREG;
8858 regs[k].regmap[HOST_CCREG]=CCREG;
8859 regmap_pre[k+1][HOST_CCREG]=CCREG;
8860 regs[k+1].wasdirty|=1<<HOST_CCREG;
8861 regs[k].dirty|=1<<HOST_CCREG;
8862 regs[k].wasconst&=~(1<<HOST_CCREG);
8863 regs[k].isconst&=~(1<<HOST_CCREG);
8864 k++;
8865 }
8866 }
8867 else {
8868 //printf("Fail Extend CC, %x ->\n",start+k*4);
8869 }
8870 }
8871 }
cf95b4f0 8872 if(dops[i].itype!=STORE&&dops[i].itype!=STORELR&&dops[i].itype!=C1LS&&dops[i].itype!=SHIFT&&
8873 dops[i].itype!=NOP&&dops[i].itype!=MOV&&dops[i].itype!=ALU&&dops[i].itype!=SHIFTIMM&&
8874 dops[i].itype!=IMM16&&dops[i].itype!=LOAD&&dops[i].itype!=COP1)
57871462 8875 {
8876 memcpy(f_regmap,regs[i].regmap,sizeof(f_regmap));
8877 }
8878 }
8879 }
9f51b4b9 8880
57871462 8881 // This allocates registers (if possible) one instruction prior
8882 // to use, which can avoid a load-use penalty on certain CPUs.
8883 for(i=0;i<slen-1;i++)
8884 {
fe807a8a 8885 if (!i || !dops[i-1].is_jump)
57871462 8886 {
cf95b4f0 8887 if(!dops[i+1].bt)
57871462 8888 {
cf95b4f0 8889 if(dops[i].itype==ALU||dops[i].itype==MOV||dops[i].itype==LOAD||dops[i].itype==SHIFTIMM||dops[i].itype==IMM16
8890 ||((dops[i].itype==COP1||dops[i].itype==COP2)&&dops[i].opcode2<3))
57871462 8891 {
cf95b4f0 8892 if(dops[i+1].rs1) {
8893 if((hr=get_reg(regs[i+1].regmap,dops[i+1].rs1))>=0)
57871462 8894 {
8895 if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
8896 {
8897 regs[i].regmap[hr]=regs[i+1].regmap[hr];
8898 regmap_pre[i+1][hr]=regs[i+1].regmap[hr];
8899 regs[i+1].regmap_entry[hr]=regs[i+1].regmap[hr];
8900 regs[i].isconst&=~(1<<hr);
8901 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
8902 constmap[i][hr]=constmap[i+1][hr];
8903 regs[i+1].wasdirty&=~(1<<hr);
8904 regs[i].dirty&=~(1<<hr);
8905 }
8906 }
8907 }
cf95b4f0 8908 if(dops[i+1].rs2) {
8909 if((hr=get_reg(regs[i+1].regmap,dops[i+1].rs2))>=0)
57871462 8910 {
8911 if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
8912 {
8913 regs[i].regmap[hr]=regs[i+1].regmap[hr];
8914 regmap_pre[i+1][hr]=regs[i+1].regmap[hr];
8915 regs[i+1].regmap_entry[hr]=regs[i+1].regmap[hr];
8916 regs[i].isconst&=~(1<<hr);
8917 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
8918 constmap[i][hr]=constmap[i+1][hr];
8919 regs[i+1].wasdirty&=~(1<<hr);
8920 regs[i].dirty&=~(1<<hr);
8921 }
8922 }
8923 }
198df76f 8924 // Preload target address for load instruction (non-constant)
cf95b4f0 8925 if(dops[i+1].itype==LOAD&&dops[i+1].rs1&&get_reg(regs[i+1].regmap,dops[i+1].rs1)<0) {
8926 if((hr=get_reg(regs[i+1].regmap,dops[i+1].rt1))>=0)
57871462 8927 {
8928 if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
8929 {
cf95b4f0 8930 regs[i].regmap[hr]=dops[i+1].rs1;
8931 regmap_pre[i+1][hr]=dops[i+1].rs1;
8932 regs[i+1].regmap_entry[hr]=dops[i+1].rs1;
57871462 8933 regs[i].isconst&=~(1<<hr);
8934 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
8935 constmap[i][hr]=constmap[i+1][hr];
8936 regs[i+1].wasdirty&=~(1<<hr);
8937 regs[i].dirty&=~(1<<hr);
8938 }
8939 }
8940 }
9f51b4b9 8941 // Load source into target register
cf95b4f0 8942 if(dops[i+1].lt1&&get_reg(regs[i+1].regmap,dops[i+1].rs1)<0) {
8943 if((hr=get_reg(regs[i+1].regmap,dops[i+1].rt1))>=0)
57871462 8944 {
8945 if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
8946 {
cf95b4f0 8947 regs[i].regmap[hr]=dops[i+1].rs1;
8948 regmap_pre[i+1][hr]=dops[i+1].rs1;
8949 regs[i+1].regmap_entry[hr]=dops[i+1].rs1;
57871462 8950 regs[i].isconst&=~(1<<hr);
8951 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
8952 constmap[i][hr]=constmap[i+1][hr];
8953 regs[i+1].wasdirty&=~(1<<hr);
8954 regs[i].dirty&=~(1<<hr);
8955 }
8956 }
8957 }
198df76f 8958 // Address for store instruction (non-constant)
cf95b4f0 8959 if(dops[i+1].itype==STORE||dops[i+1].itype==STORELR
8960 ||(dops[i+1].opcode&0x3b)==0x39||(dops[i+1].opcode&0x3b)==0x3a) { // SB/SH/SW/SD/SWC1/SDC1/SWC2/SDC2
8961 if(get_reg(regs[i+1].regmap,dops[i+1].rs1)<0) {
57871462 8962 hr=get_reg2(regs[i].regmap,regs[i+1].regmap,-1);
8963 if(hr<0) hr=get_reg(regs[i+1].regmap,-1);
6cc8d23c 8964 else {
8965 regs[i+1].regmap[hr]=AGEN1+((i+1)&1);
8966 regs[i+1].isconst&=~(1<<hr);
8967 }
57871462 8968 assert(hr>=0);
8969 if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
8970 {
cf95b4f0 8971 regs[i].regmap[hr]=dops[i+1].rs1;
8972 regmap_pre[i+1][hr]=dops[i+1].rs1;
8973 regs[i+1].regmap_entry[hr]=dops[i+1].rs1;
57871462 8974 regs[i].isconst&=~(1<<hr);
8975 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
8976 constmap[i][hr]=constmap[i+1][hr];
8977 regs[i+1].wasdirty&=~(1<<hr);
8978 regs[i].dirty&=~(1<<hr);
8979 }
8980 }
8981 }
cf95b4f0 8982 if(dops[i+1].itype==LOADLR||(dops[i+1].opcode&0x3b)==0x31||(dops[i+1].opcode&0x3b)==0x32) { // LWC1/LDC1, LWC2/LDC2
8983 if(get_reg(regs[i+1].regmap,dops[i+1].rs1)<0) {
57871462 8984 int nr;
8985 hr=get_reg(regs[i+1].regmap,FTEMP);
8986 assert(hr>=0);
8987 if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
8988 {
cf95b4f0 8989 regs[i].regmap[hr]=dops[i+1].rs1;
8990 regmap_pre[i+1][hr]=dops[i+1].rs1;
8991 regs[i+1].regmap_entry[hr]=dops[i+1].rs1;
57871462 8992 regs[i].isconst&=~(1<<hr);
8993 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
8994 constmap[i][hr]=constmap[i+1][hr];
8995 regs[i+1].wasdirty&=~(1<<hr);
8996 regs[i].dirty&=~(1<<hr);
8997 }
8998 else if((nr=get_reg2(regs[i].regmap,regs[i+1].regmap,-1))>=0)
8999 {
9000 // move it to another register
9001 regs[i+1].regmap[hr]=-1;
9002 regmap_pre[i+2][hr]=-1;
9003 regs[i+1].regmap[nr]=FTEMP;
9004 regmap_pre[i+2][nr]=FTEMP;
cf95b4f0 9005 regs[i].regmap[nr]=dops[i+1].rs1;
9006 regmap_pre[i+1][nr]=dops[i+1].rs1;
9007 regs[i+1].regmap_entry[nr]=dops[i+1].rs1;
57871462 9008 regs[i].isconst&=~(1<<nr);
9009 regs[i+1].isconst&=~(1<<nr);
9010 regs[i].dirty&=~(1<<nr);
9011 regs[i+1].wasdirty&=~(1<<nr);
9012 regs[i+1].dirty&=~(1<<nr);
9013 regs[i+2].wasdirty&=~(1<<nr);
9014 }
9015 }
9016 }
cf95b4f0 9017 if(dops[i+1].itype==LOAD||dops[i+1].itype==LOADLR||dops[i+1].itype==STORE||dops[i+1].itype==STORELR/*||dops[i+1].itype==C1LS||||dops[i+1].itype==C2LS*/) {
9018 if(dops[i+1].itype==LOAD)
9019 hr=get_reg(regs[i+1].regmap,dops[i+1].rt1);
9020 if(dops[i+1].itype==LOADLR||(dops[i+1].opcode&0x3b)==0x31||(dops[i+1].opcode&0x3b)==0x32) // LWC1/LDC1, LWC2/LDC2
57871462 9021 hr=get_reg(regs[i+1].regmap,FTEMP);
cf95b4f0 9022 if(dops[i+1].itype==STORE||dops[i+1].itype==STORELR||(dops[i+1].opcode&0x3b)==0x39||(dops[i+1].opcode&0x3b)==0x3a) { // SWC1/SDC1/SWC2/SDC2
57871462 9023 hr=get_reg(regs[i+1].regmap,AGEN1+((i+1)&1));
9024 if(hr<0) hr=get_reg(regs[i+1].regmap,-1);
9025 }
9026 if(hr>=0&&regs[i].regmap[hr]<0) {
cf95b4f0 9027 int rs=get_reg(regs[i+1].regmap,dops[i+1].rs1);
57871462 9028 if(rs>=0&&((regs[i+1].wasconst>>rs)&1)) {
9029 regs[i].regmap[hr]=AGEN1+((i+1)&1);
9030 regmap_pre[i+1][hr]=AGEN1+((i+1)&1);
9031 regs[i+1].regmap_entry[hr]=AGEN1+((i+1)&1);
9032 regs[i].isconst&=~(1<<hr);
9033 regs[i+1].wasdirty&=~(1<<hr);
9034 regs[i].dirty&=~(1<<hr);
9035 }
9036 }
9037 }
9038 }
9039 }
9040 }
9041 }
9f51b4b9 9042
57871462 9043 /* Pass 6 - Optimize clean/dirty state */
9044 clean_registers(0,slen-1,1);
9f51b4b9 9045
57871462 9046 /* Pass 7 - Identify 32-bit registers */
04fd948a 9047 for (i=slen-1;i>=0;i--)
9048 {
cf95b4f0 9049 if(dops[i].itype==CJUMP||dops[i].itype==SJUMP)
04fd948a 9050 {
9051 // Conditional branch
9052 if((source[i]>>16)!=0x1000&&i<slen-2) {
9053 // Mark this address as a branch target since it may be called
9054 // upon return from interrupt
cf95b4f0 9055 dops[i+2].bt=1;
04fd948a 9056 }
9057 }
9058 }
57871462 9059
cf95b4f0 9060 if(dops[slen-1].itype==SPAN) {
9061 dops[slen-1].bt=1; // Mark as a branch target so instruction can restart after exception
57871462 9062 }
4600ba03 9063
d1150cd6 9064#ifdef REG_ALLOC_PRINT
57871462 9065 /* Debug/disassembly */
57871462 9066 for(i=0;i<slen;i++)
9067 {
9068 printf("U:");
9069 int r;
9070 for(r=1;r<=CCREG;r++) {
9071 if((unneeded_reg[i]>>r)&1) {
9072 if(r==HIREG) printf(" HI");
9073 else if(r==LOREG) printf(" LO");
9074 else printf(" r%d",r);
9075 }
9076 }
57871462 9077 printf("\n");
9078 #if defined(__i386__) || defined(__x86_64__)
9079 printf("pre: eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",regmap_pre[i][0],regmap_pre[i][1],regmap_pre[i][2],regmap_pre[i][3],regmap_pre[i][5],regmap_pre[i][6],regmap_pre[i][7]);
9080 #endif
9081 #ifdef __arm__
9082 printf("pre: r0=%d r1=%d r2=%d r3=%d r4=%d r5=%d r6=%d r7=%d r8=%d r9=%d r10=%d r12=%d\n",regmap_pre[i][0],regmap_pre[i][1],regmap_pre[i][2],regmap_pre[i][3],regmap_pre[i][4],regmap_pre[i][5],regmap_pre[i][6],regmap_pre[i][7],regmap_pre[i][8],regmap_pre[i][9],regmap_pre[i][10],regmap_pre[i][12]);
9083 #endif
7c3a5182 9084 #if defined(__i386__) || defined(__x86_64__)
57871462 9085 printf("needs: ");
9086 if(needed_reg[i]&1) printf("eax ");
9087 if((needed_reg[i]>>1)&1) printf("ecx ");
9088 if((needed_reg[i]>>2)&1) printf("edx ");
9089 if((needed_reg[i]>>3)&1) printf("ebx ");
9090 if((needed_reg[i]>>5)&1) printf("ebp ");
9091 if((needed_reg[i]>>6)&1) printf("esi ");
9092 if((needed_reg[i]>>7)&1) printf("edi ");
57871462 9093 printf("\n");
57871462 9094 printf("entry: eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",regs[i].regmap_entry[0],regs[i].regmap_entry[1],regs[i].regmap_entry[2],regs[i].regmap_entry[3],regs[i].regmap_entry[5],regs[i].regmap_entry[6],regs[i].regmap_entry[7]);
9095 printf("dirty: ");
9096 if(regs[i].wasdirty&1) printf("eax ");
9097 if((regs[i].wasdirty>>1)&1) printf("ecx ");
9098 if((regs[i].wasdirty>>2)&1) printf("edx ");
9099 if((regs[i].wasdirty>>3)&1) printf("ebx ");
9100 if((regs[i].wasdirty>>5)&1) printf("ebp ");
9101 if((regs[i].wasdirty>>6)&1) printf("esi ");
9102 if((regs[i].wasdirty>>7)&1) printf("edi ");
9103 #endif
9104 #ifdef __arm__
9105 printf("entry: r0=%d r1=%d r2=%d r3=%d r4=%d r5=%d r6=%d r7=%d r8=%d r9=%d r10=%d r12=%d\n",regs[i].regmap_entry[0],regs[i].regmap_entry[1],regs[i].regmap_entry[2],regs[i].regmap_entry[3],regs[i].regmap_entry[4],regs[i].regmap_entry[5],regs[i].regmap_entry[6],regs[i].regmap_entry[7],regs[i].regmap_entry[8],regs[i].regmap_entry[9],regs[i].regmap_entry[10],regs[i].regmap_entry[12]);
9106 printf("dirty: ");
9107 if(regs[i].wasdirty&1) printf("r0 ");
9108 if((regs[i].wasdirty>>1)&1) printf("r1 ");
9109 if((regs[i].wasdirty>>2)&1) printf("r2 ");
9110 if((regs[i].wasdirty>>3)&1) printf("r3 ");
9111 if((regs[i].wasdirty>>4)&1) printf("r4 ");
9112 if((regs[i].wasdirty>>5)&1) printf("r5 ");
9113 if((regs[i].wasdirty>>6)&1) printf("r6 ");
9114 if((regs[i].wasdirty>>7)&1) printf("r7 ");
9115 if((regs[i].wasdirty>>8)&1) printf("r8 ");
9116 if((regs[i].wasdirty>>9)&1) printf("r9 ");
9117 if((regs[i].wasdirty>>10)&1) printf("r10 ");
9118 if((regs[i].wasdirty>>12)&1) printf("r12 ");
9119 #endif
9120 printf("\n");
9121 disassemble_inst(i);
9122 //printf ("ccadj[%d] = %d\n",i,ccadj[i]);
9123 #if defined(__i386__) || defined(__x86_64__)
9124 printf("eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d dirty: ",regs[i].regmap[0],regs[i].regmap[1],regs[i].regmap[2],regs[i].regmap[3],regs[i].regmap[5],regs[i].regmap[6],regs[i].regmap[7]);
9125 if(regs[i].dirty&1) printf("eax ");
9126 if((regs[i].dirty>>1)&1) printf("ecx ");
9127 if((regs[i].dirty>>2)&1) printf("edx ");
9128 if((regs[i].dirty>>3)&1) printf("ebx ");
9129 if((regs[i].dirty>>5)&1) printf("ebp ");
9130 if((regs[i].dirty>>6)&1) printf("esi ");
9131 if((regs[i].dirty>>7)&1) printf("edi ");
9132 #endif
9133 #ifdef __arm__
9134 printf("r0=%d r1=%d r2=%d r3=%d r4=%d r5=%d r6=%d r7=%d r8=%d r9=%d r10=%d r12=%d dirty: ",regs[i].regmap[0],regs[i].regmap[1],regs[i].regmap[2],regs[i].regmap[3],regs[i].regmap[4],regs[i].regmap[5],regs[i].regmap[6],regs[i].regmap[7],regs[i].regmap[8],regs[i].regmap[9],regs[i].regmap[10],regs[i].regmap[12]);
9135 if(regs[i].dirty&1) printf("r0 ");
9136 if((regs[i].dirty>>1)&1) printf("r1 ");
9137 if((regs[i].dirty>>2)&1) printf("r2 ");
9138 if((regs[i].dirty>>3)&1) printf("r3 ");
9139 if((regs[i].dirty>>4)&1) printf("r4 ");
9140 if((regs[i].dirty>>5)&1) printf("r5 ");
9141 if((regs[i].dirty>>6)&1) printf("r6 ");
9142 if((regs[i].dirty>>7)&1) printf("r7 ");
9143 if((regs[i].dirty>>8)&1) printf("r8 ");
9144 if((regs[i].dirty>>9)&1) printf("r9 ");
9145 if((regs[i].dirty>>10)&1) printf("r10 ");
9146 if((regs[i].dirty>>12)&1) printf("r12 ");
9147 #endif
9148 printf("\n");
9149 if(regs[i].isconst) {
9150 printf("constants: ");
9151 #if defined(__i386__) || defined(__x86_64__)
643aeae3 9152 if(regs[i].isconst&1) printf("eax=%x ",(u_int)constmap[i][0]);
9153 if((regs[i].isconst>>1)&1) printf("ecx=%x ",(u_int)constmap[i][1]);
9154 if((regs[i].isconst>>2)&1) printf("edx=%x ",(u_int)constmap[i][2]);
9155 if((regs[i].isconst>>3)&1) printf("ebx=%x ",(u_int)constmap[i][3]);
9156 if((regs[i].isconst>>5)&1) printf("ebp=%x ",(u_int)constmap[i][5]);
9157 if((regs[i].isconst>>6)&1) printf("esi=%x ",(u_int)constmap[i][6]);
9158 if((regs[i].isconst>>7)&1) printf("edi=%x ",(u_int)constmap[i][7]);
57871462 9159 #endif
7c3a5182 9160 #if defined(__arm__) || defined(__aarch64__)
643aeae3 9161 int r;
9162 for (r = 0; r < ARRAY_SIZE(constmap[i]); r++)
9163 if ((regs[i].isconst >> r) & 1)
9164 printf(" r%d=%x", r, (u_int)constmap[i][r]);
57871462 9165 #endif
9166 printf("\n");
9167 }
fe807a8a 9168 if(dops[i].is_jump) {
57871462 9169 #if defined(__i386__) || defined(__x86_64__)
9170 printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d dirty: ",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
9171 if(branch_regs[i].dirty&1) printf("eax ");
9172 if((branch_regs[i].dirty>>1)&1) printf("ecx ");
9173 if((branch_regs[i].dirty>>2)&1) printf("edx ");
9174 if((branch_regs[i].dirty>>3)&1) printf("ebx ");
9175 if((branch_regs[i].dirty>>5)&1) printf("ebp ");
9176 if((branch_regs[i].dirty>>6)&1) printf("esi ");
9177 if((branch_regs[i].dirty>>7)&1) printf("edi ");
9178 #endif
9179 #ifdef __arm__
9180 printf("branch(%d): r0=%d r1=%d r2=%d r3=%d r4=%d r5=%d r6=%d r7=%d r8=%d r9=%d r10=%d r12=%d dirty: ",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[4],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7],branch_regs[i].regmap[8],branch_regs[i].regmap[9],branch_regs[i].regmap[10],branch_regs[i].regmap[12]);
9181 if(branch_regs[i].dirty&1) printf("r0 ");
9182 if((branch_regs[i].dirty>>1)&1) printf("r1 ");
9183 if((branch_regs[i].dirty>>2)&1) printf("r2 ");
9184 if((branch_regs[i].dirty>>3)&1) printf("r3 ");
9185 if((branch_regs[i].dirty>>4)&1) printf("r4 ");
9186 if((branch_regs[i].dirty>>5)&1) printf("r5 ");
9187 if((branch_regs[i].dirty>>6)&1) printf("r6 ");
9188 if((branch_regs[i].dirty>>7)&1) printf("r7 ");
9189 if((branch_regs[i].dirty>>8)&1) printf("r8 ");
9190 if((branch_regs[i].dirty>>9)&1) printf("r9 ");
9191 if((branch_regs[i].dirty>>10)&1) printf("r10 ");
9192 if((branch_regs[i].dirty>>12)&1) printf("r12 ");
9193 #endif
57871462 9194 }
9195 }
d1150cd6 9196#endif // REG_ALLOC_PRINT
57871462 9197
9198 /* Pass 8 - Assembly */
9199 linkcount=0;stubcount=0;
9200 ds=0;is_delayslot=0;
57871462 9201 u_int dirty_pre=0;
d148d265 9202 void *beginning=start_block();
57871462 9203 if((u_int)addr&1) {
9204 ds=1;
9205 pagespan_ds();
9206 }
df4dc2b1 9207 void *instr_addr0_override = NULL;
9ad4d757 9208
9ad4d757 9209 if (start == 0x80030000) {
3968e69e 9210 // nasty hack for the fastbios thing
96186eba 9211 // override block entry to this code
df4dc2b1 9212 instr_addr0_override = out;
9ad4d757 9213 emit_movimm(start,0);
96186eba 9214 // abuse io address var as a flag that we
9215 // have already returned here once
643aeae3 9216 emit_readword(&address,1);
9217 emit_writeword(0,&pcaddr);
9218 emit_writeword(0,&address);
9ad4d757 9219 emit_cmp(0,1);
3968e69e 9220 #ifdef __aarch64__
9221 emit_jeq(out + 4*2);
2a014d73 9222 emit_far_jump(new_dyna_leave);
3968e69e 9223 #else
643aeae3 9224 emit_jne(new_dyna_leave);
3968e69e 9225 #endif
9ad4d757 9226 }
57871462 9227 for(i=0;i<slen;i++)
9228 {
670c0f22 9229 check_regmap(regmap_pre[i]);
9230 check_regmap(regs[i].regmap_entry);
9231 check_regmap(regs[i].regmap);
57871462 9232 //if(ds) printf("ds: ");
4600ba03 9233 disassemble_inst(i);
57871462 9234 if(ds) {
9235 ds=0; // Skip delay slot
cf95b4f0 9236 if(dops[i].bt) assem_debug("OOPS - branch into delay slot\n");
df4dc2b1 9237 instr_addr[i] = NULL;
57871462 9238 } else {
ffb0b9e0 9239 speculate_register_values(i);
57871462 9240 #ifndef DESTRUCTIVE_WRITEBACK
fe807a8a 9241 if (i < 2 || !dops[i-2].is_ujump)
57871462 9242 {
ad49de89 9243 wb_valid(regmap_pre[i],regs[i].regmap_entry,dirty_pre,regs[i].wasdirty,unneeded_reg[i]);
57871462 9244 }
fe807a8a 9245 if((dops[i].itype==CJUMP||dops[i].itype==SJUMP)) {
f776eb14 9246 dirty_pre=branch_regs[i].dirty;
9247 }else{
f776eb14 9248 dirty_pre=regs[i].dirty;
9249 }
57871462 9250 #endif
9251 // write back
fe807a8a 9252 if (i < 2 || !dops[i-2].is_ujump)
57871462 9253 {
ad49de89 9254 wb_invalidate(regmap_pre[i],regs[i].regmap_entry,regs[i].wasdirty,unneeded_reg[i]);
57871462 9255 loop_preload(regmap_pre[i],regs[i].regmap_entry);
9256 }
9257 // branch target entry point
df4dc2b1 9258 instr_addr[i] = out;
57871462 9259 assem_debug("<->\n");
2330734f 9260 drc_dbg_emit_do_cmp(i, ccadj[i]);
7f94b097 9261 if (clear_hack_addr) {
9262 emit_movimm(0, 0);
9263 emit_writeword(0, &hack_addr);
9264 clear_hack_addr = 0;
9265 }
dd114d7d 9266
57871462 9267 // load regs
9268 if(regs[i].regmap_entry[HOST_CCREG]==CCREG&&regs[i].regmap[HOST_CCREG]!=CCREG)
ad49de89 9269 wb_register(CCREG,regs[i].regmap_entry,regs[i].wasdirty);
cf95b4f0 9270 load_regs(regs[i].regmap_entry,regs[i].regmap,dops[i].rs1,dops[i].rs2);
57871462 9271 address_generation(i,&regs[i],regs[i].regmap_entry);
ad49de89 9272 load_consts(regmap_pre[i],regs[i].regmap,i);
fe807a8a 9273 if(dops[i].is_jump)
57871462 9274 {
9275 // Load the delay slot registers if necessary
cf95b4f0 9276 if(dops[i+1].rs1!=dops[i].rs1&&dops[i+1].rs1!=dops[i].rs2&&(dops[i+1].rs1!=dops[i].rt1||dops[i].rt1==0))
9277 load_regs(regs[i].regmap_entry,regs[i].regmap,dops[i+1].rs1,dops[i+1].rs1);
9278 if(dops[i+1].rs2!=dops[i+1].rs1&&dops[i+1].rs2!=dops[i].rs1&&dops[i+1].rs2!=dops[i].rs2&&(dops[i+1].rs2!=dops[i].rt1||dops[i].rt1==0))
9279 load_regs(regs[i].regmap_entry,regs[i].regmap,dops[i+1].rs2,dops[i+1].rs2);
37387d8b 9280 if (ram_offset && (dops[i+1].is_load || dops[i+1].is_store))
9281 load_regs(regs[i].regmap_entry,regs[i].regmap,ROREG,ROREG);
9282 if (dops[i+1].is_store)
ad49de89 9283 load_regs(regs[i].regmap_entry,regs[i].regmap,INVCP,INVCP);
57871462 9284 }
9285 else if(i+1<slen)
9286 {
9287 // Preload registers for following instruction
cf95b4f0 9288 if(dops[i+1].rs1!=dops[i].rs1&&dops[i+1].rs1!=dops[i].rs2)
9289 if(dops[i+1].rs1!=dops[i].rt1&&dops[i+1].rs1!=dops[i].rt2)
9290 load_regs(regs[i].regmap_entry,regs[i].regmap,dops[i+1].rs1,dops[i+1].rs1);
9291 if(dops[i+1].rs2!=dops[i+1].rs1&&dops[i+1].rs2!=dops[i].rs1&&dops[i+1].rs2!=dops[i].rs2)
9292 if(dops[i+1].rs2!=dops[i].rt1&&dops[i+1].rs2!=dops[i].rt2)
9293 load_regs(regs[i].regmap_entry,regs[i].regmap,dops[i+1].rs2,dops[i+1].rs2);
57871462 9294 }
9295 // TODO: if(is_ooo(i)) address_generation(i+1);
9a3ccfeb 9296 if (!dops[i].is_jump || dops[i].itype == CJUMP)
ad49de89 9297 load_regs(regs[i].regmap_entry,regs[i].regmap,CCREG,CCREG);
37387d8b 9298 if (ram_offset && (dops[i].is_load || dops[i].is_store))
9299 load_regs(regs[i].regmap_entry,regs[i].regmap,ROREG,ROREG);
9300 if (dops[i].is_store)
ad49de89 9301 load_regs(regs[i].regmap_entry,regs[i].regmap,INVCP,INVCP);
2330734f 9302
9303 ds = assemble(i, &regs[i], ccadj[i]);
9304
fe807a8a 9305 if (dops[i].is_ujump)
57871462 9306 literal_pool(1024);
9307 else
9308 literal_pool_jumpover(256);
9309 }
9310 }
3d680478 9311
9312 assert(slen > 0);
cf95b4f0 9313 if (slen > 0 && dops[slen-1].itype == INTCALL) {
3d680478 9314 // no ending needed for this block since INTCALL never returns
9315 }
57871462 9316 // If the block did not end with an unconditional branch,
9317 // add a jump to the next instruction.
3d680478 9318 else if (i > 1) {
fe807a8a 9319 if (!dops[i-2].is_ujump && dops[i-1].itype != SPAN) {
9320 assert(!dops[i-1].is_jump);
57871462 9321 assert(i==slen);
cf95b4f0 9322 if(dops[i-2].itype!=CJUMP&&dops[i-2].itype!=SJUMP) {
ad49de89 9323 store_regs_bt(regs[i-1].regmap,regs[i-1].dirty,start+i*4);
57871462 9324 if(regs[i-1].regmap[HOST_CCREG]!=CCREG)
9325 emit_loadreg(CCREG,HOST_CCREG);
2330734f 9326 emit_addimm(HOST_CCREG, ccadj[i-1] + CLOCK_ADJUST(1), HOST_CCREG);
57871462 9327 }
fe807a8a 9328 else
57871462 9329 {
ad49de89 9330 store_regs_bt(branch_regs[i-2].regmap,branch_regs[i-2].dirty,start+i*4);
57871462 9331 assert(branch_regs[i-2].regmap[HOST_CCREG]==CCREG);
9332 }
643aeae3 9333 add_to_linker(out,start+i*4,0);
57871462 9334 emit_jmp(0);
9335 }
9336 }
9337 else
9338 {
9339 assert(i>0);
fe807a8a 9340 assert(!dops[i-1].is_jump);
ad49de89 9341 store_regs_bt(regs[i-1].regmap,regs[i-1].dirty,start+i*4);
57871462 9342 if(regs[i-1].regmap[HOST_CCREG]!=CCREG)
9343 emit_loadreg(CCREG,HOST_CCREG);
2330734f 9344 emit_addimm(HOST_CCREG, ccadj[i-1] + CLOCK_ADJUST(1), HOST_CCREG);
643aeae3 9345 add_to_linker(out,start+i*4,0);
57871462 9346 emit_jmp(0);
9347 }
9348
9349 // TODO: delay slot stubs?
9350 // Stubs
9351 for(i=0;i<stubcount;i++)
9352 {
b14b6a8f 9353 switch(stubs[i].type)
57871462 9354 {
9355 case LOADB_STUB:
9356 case LOADH_STUB:
9357 case LOADW_STUB:
9358 case LOADD_STUB:
9359 case LOADBU_STUB:
9360 case LOADHU_STUB:
9361 do_readstub(i);break;
9362 case STOREB_STUB:
9363 case STOREH_STUB:
9364 case STOREW_STUB:
9365 case STORED_STUB:
9366 do_writestub(i);break;
9367 case CC_STUB:
9368 do_ccstub(i);break;
9369 case INVCODE_STUB:
9370 do_invstub(i);break;
9371 case FP_STUB:
9372 do_cop1stub(i);break;
9373 case STORELR_STUB:
9374 do_unalignedwritestub(i);break;
9375 }
9376 }
9377
9ad4d757 9378 if (instr_addr0_override)
9379 instr_addr[0] = instr_addr0_override;
9380
57871462 9381 /* Pass 9 - Linker */
9382 for(i=0;i<linkcount;i++)
9383 {
643aeae3 9384 assem_debug("%p -> %8x\n",link_addr[i].addr,link_addr[i].target);
57871462 9385 literal_pool(64);
643aeae3 9386 if (!link_addr[i].ext)
57871462 9387 {
643aeae3 9388 void *stub = out;
9389 void *addr = check_addr(link_addr[i].target);
9390 emit_extjump(link_addr[i].addr, link_addr[i].target);
9391 if (addr) {
9392 set_jump_target(link_addr[i].addr, addr);
3d680478 9393 add_jump_out(link_addr[i].target,stub);
57871462 9394 }
643aeae3 9395 else
9396 set_jump_target(link_addr[i].addr, stub);
57871462 9397 }
9398 else
9399 {
9400 // Internal branch
643aeae3 9401 int target=(link_addr[i].target-start)>>2;
57871462 9402 assert(target>=0&&target<slen);
9403 assert(instr_addr[target]);
9404 //#ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
643aeae3 9405 //set_jump_target_fillslot(link_addr[i].addr,instr_addr[target],link_addr[i].ext>>1);
57871462 9406 //#else
643aeae3 9407 set_jump_target(link_addr[i].addr, instr_addr[target]);
57871462 9408 //#endif
9409 }
9410 }
3d680478 9411
9412 u_int source_len = slen*4;
cf95b4f0 9413 if (dops[slen-1].itype == INTCALL && source_len > 4)
3d680478 9414 // no need to treat the last instruction as compiled
9415 // as interpreter fully handles it
9416 source_len -= 4;
9417
9418 if ((u_char *)copy + source_len > (u_char *)shadow + sizeof(shadow))
9419 copy = shadow;
9420
57871462 9421 // External Branch Targets (jump_in)
57871462 9422 for(i=0;i<slen;i++)
9423 {
cf95b4f0 9424 if(dops[i].bt||i==0)
57871462 9425 {
9426 if(instr_addr[i]) // TODO - delay slots (=null)
9427 {
9428 u_int vaddr=start+i*4;
94d23bb9 9429 u_int page=get_page(vaddr);
9430 u_int vpage=get_vpage(vaddr);
57871462 9431 literal_pool(256);
57871462 9432 {
df4dc2b1 9433 assem_debug("%p (%d) <- %8x\n",instr_addr[i],i,start+i*4);
57871462 9434 assem_debug("jump_in: %x\n",start+i*4);
df4dc2b1 9435 ll_add(jump_dirty+vpage,vaddr,out);
3d680478 9436 void *entry_point = do_dirty_stub(i, source_len);
df4dc2b1 9437 ll_add_flags(jump_in+page,vaddr,state_rflags,entry_point);
57871462 9438 // If there was an existing entry in the hash table,
9439 // replace it with the new address.
9440 // Don't add new entries. We'll insert the
9441 // ones that actually get used in check_addr().
df4dc2b1 9442 struct ht_entry *ht_bin = hash_table_get(vaddr);
9443 if (ht_bin->vaddr[0] == vaddr)
9444 ht_bin->tcaddr[0] = entry_point;
9445 if (ht_bin->vaddr[1] == vaddr)
9446 ht_bin->tcaddr[1] = entry_point;
57871462 9447 }
57871462 9448 }
9449 }
9450 }
9451 // Write out the literal pool if necessary
9452 literal_pool(0);
9453 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
9454 // Align code
9455 if(((u_int)out)&7) emit_addnop(13);
9456 #endif
01d26796 9457 assert(out - (u_char *)beginning < MAX_OUTPUT_BLOCK_SIZE);
643aeae3 9458 //printf("shadow buffer: %p-%p\n",copy,(u_char *)copy+slen*4);
3d680478 9459 memcpy(copy, source, source_len);
9460 copy += source_len;
9f51b4b9 9461
d148d265 9462 end_block(beginning);
9f51b4b9 9463
57871462 9464 // If we're within 256K of the end of the buffer,
9465 // start over from the beginning. (Is 256K enough?)
2a014d73 9466 if (out > ndrc->translation_cache + sizeof(ndrc->translation_cache) - MAX_OUTPUT_BLOCK_SIZE)
9467 out = ndrc->translation_cache;
9f51b4b9 9468
57871462 9469 // Trap writes to any of the pages we compiled
9470 for(i=start>>12;i<=(start+slen*4)>>12;i++) {
9471 invalid_code[i]=0;
57871462 9472 }
9be4ba64 9473 inv_code_start=inv_code_end=~0;
71e490c5 9474
b96d3df7 9475 // for PCSX we need to mark all mirrors too
b12c9fb8 9476 if(get_page(start)<(RAM_SIZE>>12))
9477 for(i=start>>12;i<=(start+slen*4)>>12;i++)
b96d3df7 9478 invalid_code[((u_int)0x00000000>>12)|(i&0x1ff)]=
9479 invalid_code[((u_int)0x80000000>>12)|(i&0x1ff)]=
9480 invalid_code[((u_int)0xa0000000>>12)|(i&0x1ff)]=0;
9f51b4b9 9481
57871462 9482 /* Pass 10 - Free memory by expiring oldest blocks */
9f51b4b9 9483
2a014d73 9484 int end=(((out-ndrc->translation_cache)>>(TARGET_SIZE_2-16))+16384)&65535;
57871462 9485 while(expirep!=end)
9486 {
9487 int shift=TARGET_SIZE_2-3; // Divide into 8 blocks
943f42f3 9488 uintptr_t base_offs = ((uintptr_t)(expirep >> 13) << shift); // Base offset of this block
9489 uintptr_t base_offs_s = base_offs >> shift;
57871462 9490 inv_debug("EXP: Phase %d\n",expirep);
9491 switch((expirep>>11)&3)
9492 {
9493 case 0:
9494 // Clear jump_in and jump_dirty
943f42f3 9495 ll_remove_matching_addrs(jump_in+(expirep&2047),base_offs_s,shift);
9496 ll_remove_matching_addrs(jump_dirty+(expirep&2047),base_offs_s,shift);
9497 ll_remove_matching_addrs(jump_in+2048+(expirep&2047),base_offs_s,shift);
9498 ll_remove_matching_addrs(jump_dirty+2048+(expirep&2047),base_offs_s,shift);
57871462 9499 break;
9500 case 1:
9501 // Clear pointers
943f42f3 9502 ll_kill_pointers(jump_out[expirep&2047],base_offs_s,shift);
9503 ll_kill_pointers(jump_out[(expirep&2047)+2048],base_offs_s,shift);
57871462 9504 break;
9505 case 2:
9506 // Clear hash table
9507 for(i=0;i<32;i++) {
df4dc2b1 9508 struct ht_entry *ht_bin = &hash_table[((expirep&2047)<<5)+i];
943f42f3 9509 uintptr_t o1 = (u_char *)ht_bin->tcaddr[1] - ndrc->translation_cache;
9510 uintptr_t o2 = o1 - MAX_OUTPUT_BLOCK_SIZE;
9511 if ((o1 >> shift) == base_offs_s || (o2 >> shift) == base_offs_s) {
df4dc2b1 9512 inv_debug("EXP: Remove hash %x -> %p\n",ht_bin->vaddr[1],ht_bin->tcaddr[1]);
9513 ht_bin->vaddr[1] = -1;
9514 ht_bin->tcaddr[1] = NULL;
9515 }
943f42f3 9516 o1 = (u_char *)ht_bin->tcaddr[0] - ndrc->translation_cache;
9517 o2 = o1 - MAX_OUTPUT_BLOCK_SIZE;
9518 if ((o1 >> shift) == base_offs_s || (o2 >> shift) == base_offs_s) {
df4dc2b1 9519 inv_debug("EXP: Remove hash %x -> %p\n",ht_bin->vaddr[0],ht_bin->tcaddr[0]);
9520 ht_bin->vaddr[0] = ht_bin->vaddr[1];
9521 ht_bin->tcaddr[0] = ht_bin->tcaddr[1];
9522 ht_bin->vaddr[1] = -1;
9523 ht_bin->tcaddr[1] = NULL;
57871462 9524 }
9525 }
9526 break;
9527 case 3:
9528 // Clear jump_out
9f51b4b9 9529 if((expirep&2047)==0)
dd3a91a1 9530 do_clear_cache();
943f42f3 9531 ll_remove_matching_addrs(jump_out+(expirep&2047),base_offs_s,shift);
9532 ll_remove_matching_addrs(jump_out+2048+(expirep&2047),base_offs_s,shift);
57871462 9533 break;
9534 }
9535 expirep=(expirep+1)&65535;
9536 }
37387d8b 9537#ifdef ASSEM_PRINT
9538 fflush(stdout);
9539#endif
57871462 9540 return 0;
9541}
b9b61529 9542
9543// vim:shiftwidth=2:expandtab
ARM optimized PCSX fork