notaz.gp2x.de / pcsx_rearmed.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
drc: adjust load/store checks
[pcsx_rearmed.git] / libpcsxcore / new_dynarec / new_dynarec.c
CommitLineData
57871462 1/* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
2 * Mupen64plus - new_dynarec.c *
20d507ba 3 * Copyright (C) 2009-2011 Ari64 *
57871462 4 * *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
9 * *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
14 * *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. *
19 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */
20
21#include <stdlib.h>
22#include <stdint.h> //include for uint64_t
23#include <assert.h>
d848b60a 24#include <errno.h>
4600ba03 25#include <sys/mman.h>
d148d265 26#ifdef __MACH__
27#include <libkern/OSCacheControl.h>
28#endif
1e212a25 29#ifdef _3DS
30#include <3ds_utils.h>
31#endif
3039c914 32#ifdef HAVE_LIBNX
33#include <switch.h>
34static Jit g_jit;
35#endif
57871462 36
d148d265 37#include "new_dynarec_config.h"
3968e69e 38#include "../psxhle.h"
39#include "../psxinterpreter.h"
81dbbf4c 40#include "../gte.h"
41#include "emu_if.h" // emulator interface
a5cd72d0 42#include "linkage_offsets.h"
43#include "compiler_features.h"
cdc2da64 44#include "arm_features.h"
57871462 45
b14b6a8f 46#ifndef ARRAY_SIZE
47#define ARRAY_SIZE(x) (sizeof(x) / sizeof(x[0]))
48#endif
e3c6bdb5 49#ifndef min
50#define min(a, b) ((b) < (a) ? (b) : (a))
51#endif
32631e6a 52#ifndef max
53#define max(a, b) ((b) > (a) ? (b) : (a))
54#endif
b14b6a8f 55
4600ba03 56//#define DISASM
32631e6a 57//#define ASSEM_PRINT
a5cd72d0 58//#define REGMAP_PRINT // with DISASM only
9b495f6e 59//#define INV_DEBUG_W
ece032e6 60//#define STAT_PRINT
32631e6a 61
62#ifdef ASSEM_PRINT
63#define assem_debug printf
64#else
4600ba03 65#define assem_debug(...)
32631e6a 66#endif
67//#define inv_debug printf
4600ba03 68#define inv_debug(...)
57871462 69
70#ifdef __i386__
71#include "assem_x86.h"
72#endif
73#ifdef __x86_64__
74#include "assem_x64.h"
75#endif
76#ifdef __arm__
77#include "assem_arm.h"
78#endif
be516ebe 79#ifdef __aarch64__
80#include "assem_arm64.h"
81#endif
57871462 82
81dbbf4c 83#define RAM_SIZE 0x200000
d3201e39 84#define MAXBLOCK 2048
57871462 85#define MAX_OUTPUT_BLOCK_SIZE 262144
93c0345b 86#define EXPIRITY_OFFSET (MAX_OUTPUT_BLOCK_SIZE * 2)
87#define PAGE_COUNT 1024
2573466a 88
882a08fc 89#if defined(HAVE_CONDITIONAL_CALL) && !defined(DESTRUCTIVE_SHIFT)
90#define INVALIDATE_USE_COND_CALL
91#endif
92
66ea165f 93#ifdef VITA
94// apparently Vita has a 16MB limit, so either we cut tc in half,
95// or use this hack (it's a hack because tc size was designed to be power-of-2)
96#define TC_REDUCE_BYTES 4096
97#else
98#define TC_REDUCE_BYTES 0
99#endif
100
d9e2b173 101struct ndrc_tramp
102{
103 struct tramp_insns ops[2048 / sizeof(struct tramp_insns)];
104 const void *f[2048 / sizeof(void *)];
105};
106
2a014d73 107struct ndrc_mem
108{
66ea165f 109 u_char translation_cache[(1 << TARGET_SIZE_2) - TC_REDUCE_BYTES];
d9e2b173 110 struct ndrc_tramp tramp;
2a014d73 111};
112
113#ifdef BASE_ADDR_DYNAMIC
114static struct ndrc_mem *ndrc;
115#else
116static struct ndrc_mem ndrc_ __attribute__((aligned(4096)));
117static struct ndrc_mem *ndrc = &ndrc_;
118#endif
d9e2b173 119#ifdef TC_WRITE_OFFSET
3039c914 120# ifdef __GLIBC__
121# include <sys/types.h>
122# include <sys/stat.h>
123# include <fcntl.h>
124# include <unistd.h>
125# endif
126static long ndrc_write_ofs;
d9e2b173 127#define NDRC_WRITE_OFFSET(x) (void *)((char *)(x) + ndrc_write_ofs)
3039c914 128#else
d9e2b173 129#define NDRC_WRITE_OFFSET(x) (x)
3039c914 130#endif
2a014d73 131
b14b6a8f 132// stubs
133enum stub_type {
134 CC_STUB = 1,
a5cd72d0 135 //FP_STUB = 2,
b14b6a8f 136 LOADB_STUB = 3,
137 LOADH_STUB = 4,
138 LOADW_STUB = 5,
a5cd72d0 139 //LOADD_STUB = 6,
b14b6a8f 140 LOADBU_STUB = 7,
141 LOADHU_STUB = 8,
142 STOREB_STUB = 9,
143 STOREH_STUB = 10,
144 STOREW_STUB = 11,
a5cd72d0 145 //STORED_STUB = 12,
b14b6a8f 146 STORELR_STUB = 13,
147 INVCODE_STUB = 14,
a5cd72d0 148 OVERFLOW_STUB = 15,
277718fa 149 ALIGNMENT_STUB = 16,
b14b6a8f 150};
151
6cc8d23c 152// regmap_pre[i] - regs before [i] insn starts; dirty things here that
153// don't match .regmap will be written back
154// [i].regmap_entry - regs that must be set up if someone jumps here
155// [i].regmap - regs [i] insn will read/(over)write
2acc46cd 156// branch_regs[i].* - same as above but for branches, takes delay slot into account
57871462 157struct regstat
158{
6cc8d23c 159 signed char regmap_entry[HOST_REGS];
57871462 160 signed char regmap[HOST_REGS];
a22ccd6a 161 u_int wasdirty;
162 u_int dirty;
24058131 163 u_int wasconst; // before; for example 'lw r2, (r2)' wasconst is true
a5cd72d0 164 u_int isconst; // ... but isconst is false when r2 is known (hr)
8575a877 165 u_int loadedconst; // host regs that have constants loaded
90f98e7c 166 u_int noevict; // can't evict this hr (alloced by current op)
9b495f6e 167 //u_int waswritten; // MIPS regs that were used as store base before
a22ccd6a 168 uint64_t u;
57871462 169};
170
df4dc2b1 171struct ht_entry
172{
173 u_int vaddr[2];
174 void *tcaddr[2];
175};
176
b14b6a8f 177struct code_stub
178{
179 enum stub_type type;
180 void *addr;
181 void *retaddr;
182 u_int a;
183 uintptr_t b;
184 uintptr_t c;
185 u_int d;
186 u_int e;
187};
188
643aeae3 189struct link_entry
190{
191 void *addr;
192 u_int target;
104df9d3 193 u_int internal;
194};
195
196struct block_info
197{
198 struct block_info *next;
199 const void *source;
200 const void *copy;
201 u_int start; // vaddr of the block start
202 u_int len; // of the whole block source
203 u_int tc_offs;
204 //u_int tc_len;
205 u_int reg_sv_flags;
3280e616 206 u_char is_dirty;
207 u_char inv_near_misses;
104df9d3 208 u_short jump_in_cnt;
209 struct {
210 u_int vaddr;
211 void *addr;
212 } jump_in[0];
643aeae3 213};
214
b7ad2f2c 215struct jump_info
216{
217 int alloc;
218 int count;
219 struct {
220 u_int target_vaddr;
221 void *stub;
222 } e[0];
223};
224
cf95b4f0 225static struct decoded_insn
226{
227 u_char itype;
a5cd72d0 228 u_char opcode; // bits 31-26
229 u_char opcode2; // (depends on opcode)
cf95b4f0 230 u_char rs1;
231 u_char rs2;
232 u_char rt1;
233 u_char rt2;
53dc27f6 234 u_char use_lt1:1;
cf95b4f0 235 u_char bt:1;
cf95b4f0 236 u_char ooo:1;
237 u_char is_ds:1;
fe807a8a 238 u_char is_jump:1;
239 u_char is_ujump:1;
37387d8b 240 u_char is_load:1;
241 u_char is_store:1;
a5cd72d0 242 u_char is_delay_load:1; // is_load + MFC/CFC
243 u_char is_exception:1; // unconditional, also interp. fallback
244 u_char may_except:1; // might generate an exception
f9e9616e 245 u_char ls_type:2; // load/store type (ls_width_type)
cf95b4f0 246} dops[MAXBLOCK];
247
f9e9616e 248enum ls_width_type {
249 LS_8 = 0, LS_16, LS_32, LS_LR
250};
251
277718fa 252static struct compile_info
253{
254 int imm;
255 u_int ba;
256 int ccadj;
257 signed char min_free_regs;
258 signed char addr;
259 signed char reserved[2];
260} cinfo[MAXBLOCK];
261
398d6924 262 static u_char *out;
6d75addf 263 static char invalid_code[0x100000];
104df9d3 264 static struct ht_entry hash_table[65536];
93c0345b 265 static struct block_info *blocks[PAGE_COUNT];
b7ad2f2c 266 static struct jump_info *jumps[PAGE_COUNT];
e2b5e7aa 267 static u_int start;
268 static u_int *source;
bedfea38 269 static uint64_t gte_rs[MAXBLOCK]; // gte: 32 data and 32 ctl regs
270 static uint64_t gte_rt[MAXBLOCK];
271 static uint64_t gte_unneeded[MAXBLOCK];
ffb0b9e0 272 static u_int smrv[32]; // speculated MIPS register values
273 static u_int smrv_strong; // mask or regs that are likely to have correct values
274 static u_int smrv_weak; // same, but somewhat less likely
275 static u_int smrv_strong_next; // same, but after current insn executes
276 static u_int smrv_weak_next;
e2b5e7aa 277 static uint64_t unneeded_reg[MAXBLOCK];
e2b5e7aa 278 static uint64_t branch_unneeded_reg[MAXBLOCK];
6cc8d23c 279 // see 'struct regstat' for a description
2330734f 280 static signed char regmap_pre[MAXBLOCK][HOST_REGS];
40fca85b 281 // contains 'real' consts at [i] insn, but may differ from what's actually
282 // loaded in host reg as 'final' value is always loaded, see get_final_value()
283 static uint32_t current_constmap[HOST_REGS];
284 static uint32_t constmap[MAXBLOCK][HOST_REGS];
956f3129 285 static struct regstat regs[MAXBLOCK];
286 static struct regstat branch_regs[MAXBLOCK];
e2b5e7aa 287 static int slen;
df4dc2b1 288 static void *instr_addr[MAXBLOCK];
643aeae3 289 static struct link_entry link_addr[MAXBLOCK];
e2b5e7aa 290 static int linkcount;
b14b6a8f 291 static struct code_stub stubs[MAXBLOCK*3];
e2b5e7aa 292 static int stubcount;
293 static u_int literals[1024][2];
294 static int literalcount;
295 static int is_delayslot;
e2b5e7aa 296 static char shadow[1048576] __attribute__((aligned(16)));
297 static void *copy;
93c0345b 298 static u_int expirep;
e2b5e7aa 299 static u_int stop_after_jal;
7f94b097 300 static u_int f1_hack;
ece032e6 301#ifdef STAT_PRINT
302 static int stat_bc_direct;
303 static int stat_bc_pre;
304 static int stat_bc_restore;
104df9d3 305 static int stat_ht_lookups;
ece032e6 306 static int stat_jump_in_lookups;
307 static int stat_restore_tries;
308 static int stat_restore_compares;
309 static int stat_inv_addr_calls;
310 static int stat_inv_hits;
104df9d3 311 static int stat_blocks;
312 static int stat_links;
ece032e6 313 #define stat_inc(s) s++
104df9d3 314 #define stat_dec(s) s--
315 #define stat_clear(s) s = 0
ece032e6 316#else
317 #define stat_inc(s)
104df9d3 318 #define stat_dec(s)
319 #define stat_clear(s)
ece032e6 320#endif
e2b5e7aa 321
322 int new_dynarec_hacks;
d62c125a 323 int new_dynarec_hacks_pergame;
32631e6a 324 int new_dynarec_hacks_old;
e2b5e7aa 325 int new_dynarec_did_compile;
687b4580 326
d62c125a 327 #define HACK_ENABLED(x) ((new_dynarec_hacks | new_dynarec_hacks_pergame) & (x))
328
de6dbc52 329 extern int cycle_count; // ... until end of the timeslice, counts -N -> 0 (CCREG)
687b4580 330 extern int last_count; // last absolute target, often = next_interupt
331 extern int pcaddr;
332 extern int pending_exception;
333 extern int branch_target;
37387d8b 334 extern uintptr_t ram_offset;
d1e4ebd9 335 extern uintptr_t mini_ht[32][2];
57871462 336
337 /* registers that may be allocated */
338 /* 1-31 gpr */
7c3a5182 339#define LOREG 32 // lo
340#define HIREG 33 // hi
00fa9369 341//#define FSREG 34 // FPU status (FCSR)
de6dbc52 342//#define CSREG 35 // Coprocessor status
57871462 343#define CCREG 36 // Cycle count
344#define INVCP 37 // Pointer to invalid_code
1edfcc68 345//#define MMREG 38 // Pointer to memory_map
33a1eda1 346#define ROREG 39 // ram offset (if psxM != 0x80000000)
619e5ded 347#define TEMPREG 40
33a1eda1 348#define FTEMP 40 // Load/store temporary register (was fpu)
619e5ded 349#define PTEMP 41 // Prefetch temporary register
1edfcc68 350//#define TLREG 42 // TLB mapping offset
619e5ded 351#define RHASH 43 // Return address hash
352#define RHTBL 44 // Return address hash table address
353#define RTEMP 45 // JR/JALR address register
354#define MAXREG 45
277718fa 355#define AGEN1 46 // Address generation temporary register (pass5b_preallocate2)
1edfcc68 356//#define AGEN2 47 // Address generation temporary register
57871462 357
358 /* instruction types */
359#define NOP 0 // No operation
360#define LOAD 1 // Load
361#define STORE 2 // Store
362#define LOADLR 3 // Unaligned load
363#define STORELR 4 // Unaligned store
a5cd72d0 364#define MOV 5 // Move (hi/lo only)
57871462 365#define ALU 6 // Arithmetic/logic
366#define MULTDIV 7 // Multiply/divide
367#define SHIFT 8 // Shift by register
368#define SHIFTIMM 9// Shift by immediate
369#define IMM16 10 // 16-bit immediate
370#define RJUMP 11 // Unconditional jump to register
371#define UJUMP 12 // Unconditional jump
372#define CJUMP 13 // Conditional branch (BEQ/BNE/BGTZ/BLEZ)
373#define SJUMP 14 // Conditional branch (regimm format)
374#define COP0 15 // Coprocessor 0
a5cd72d0 375#define RFE 16
d1150cd6 376#define SYSCALL 22// SYSCALL,BREAK
a5cd72d0 377#define OTHER 23 // Other/unknown - do nothing
7139f3c8 378#define HLECALL 26// PCSX fake opcodes for HLE
b9b61529 379#define COP2 27 // Coprocessor 2 move
380#define C2LS 28 // Coprocessor 2 load/store
381#define C2OP 29 // Coprocessor 2 operation
1e973cb0 382#define INTCALL 30// Call interpreter to handle rare corner cases
57871462 383
57871462 384 /* branch codes */
385#define TAKEN 1
386#define NOTTAKEN 2
57871462 387
7c3a5182 388#define DJT_1 (void *)1l // no function, just a label in assem_debug log
389#define DJT_2 (void *)2l
390
57871462 391// asm linkage
57871462 392void dyna_linker();
57871462 393void cc_interrupt();
d1150cd6 394void jump_syscall (u_int u0, u_int u1, u_int pc);
395void jump_syscall_ds(u_int u0, u_int u1, u_int pc);
396void jump_break (u_int u0, u_int u1, u_int pc);
397void jump_break_ds(u_int u0, u_int u1, u_int pc);
a5cd72d0 398void jump_overflow (u_int u0, u_int u1, u_int pc);
399void jump_overflow_ds(u_int u0, u_int u1, u_int pc);
277718fa 400void jump_addrerror (u_int cause, u_int addr, u_int pc);
401void jump_addrerror_ds(u_int cause, u_int addr, u_int pc);
3968e69e 402void jump_to_new_pc();
81dbbf4c 403void call_gteStall();
7139f3c8 404void new_dyna_leave();
57871462 405
104df9d3 406void *ndrc_get_addr_ht_param(u_int vaddr, int can_compile);
407void *ndrc_get_addr_ht(u_int vaddr);
104df9d3 408void ndrc_add_jump_out(u_int vaddr, void *src);
9b495f6e 409void ndrc_write_invalidate_one(u_int addr);
410static void ndrc_write_invalidate_many(u_int addr, u_int end);
104df9d3 411
412static int new_recompile_block(u_int addr);
413static void invalidate_block(struct block_info *block);
a5cd72d0 414static void exception_assemble(int i, const struct regstat *i_regs, int ccadj_);
398d6924 415
57871462 416// Needed by assembler
a22ccd6a 417static void wb_register(signed char r, const signed char regmap[], u_int dirty);
418static void wb_dirtys(const signed char i_regmap[], u_int i_dirty);
419static void wb_needed_dirtys(const signed char i_regmap[], u_int i_dirty, int addr);
2330734f 420static void load_all_regs(const signed char i_regmap[]);
421static void load_needed_regs(const signed char i_regmap[], const signed char next_regmap[]);
e2b5e7aa 422static void load_regs_entry(int t);
2330734f 423static void load_all_consts(const signed char regmap[], u_int dirty, int i);
81dbbf4c 424static u_int get_host_reglist(const signed char *regmap);
e2b5e7aa 425
de6dbc52 426static int get_final_value(int hr, int i, u_int *value);
b14b6a8f 427static void add_stub(enum stub_type type, void *addr, void *retaddr,
428 u_int a, uintptr_t b, uintptr_t c, u_int d, u_int e);
429static void add_stub_r(enum stub_type type, void *addr, void *retaddr,
81dbbf4c 430 int i, int addr_reg, const struct regstat *i_regs, int ccadj, u_int reglist);
643aeae3 431static void add_to_linker(void *addr, u_int target, int ext);
687b4580 432static void *get_direct_memhandler(void *table, u_int addr,
433 enum stub_type type, uintptr_t *addr_host);
32631e6a 434static void cop2_do_stall_check(u_int op, int i, const struct regstat *i_regs, u_int reglist);
687b4580 435static void pass_args(int a0, int a1);
2a014d73 436static void emit_far_jump(const void *f);
437static void emit_far_call(const void *f);
57871462 438
9c67c98f 439#ifdef VITA
440#include <psp2/kernel/sysmem.h>
441static int sceBlock;
442// note: this interacts with RetroArch's Vita bootstrap code: bootstrap/vita/sbrk.c
443extern int getVMBlock();
444int _newlib_vm_size_user = sizeof(*ndrc);
445#endif
446
d148d265 447static void mprotect_w_x(void *start, void *end, int is_x)
448{
449#ifdef NO_WRITE_EXEC
1e212a25 450 #if defined(VITA)
451 // *Open* enables write on all memory that was
452 // allocated by sceKernelAllocMemBlockForVM()?
453 if (is_x)
454 sceKernelCloseVMDomain();
455 else
456 sceKernelOpenVMDomain();
3039c914 457 #elif defined(HAVE_LIBNX)
458 Result rc;
d9e2b173 459 // check to avoid the full flush in jitTransitionToExecutable()
460 if (g_jit.type != JitType_CodeMemory) {
461 if (is_x)
462 rc = jitTransitionToExecutable(&g_jit);
463 else
464 rc = jitTransitionToWritable(&g_jit);
465 if (R_FAILED(rc))
466 ;//SysPrintf("jitTransition %d %08x\n", is_x, rc);
467 }
468 #elif defined(TC_WRITE_OFFSET)
3039c914 469 // separated rx and rw areas are always available
1e212a25 470 #else
d148d265 471 u_long mstart = (u_long)start & ~4095ul;
472 u_long mend = (u_long)end;
473 if (mprotect((void *)mstart, mend - mstart,
474 PROT_READ | (is_x ? PROT_EXEC : PROT_WRITE)) != 0)
475 SysPrintf("mprotect(%c) failed: %s\n", is_x ? 'x' : 'w', strerror(errno));
1e212a25 476 #endif
d148d265 477#endif
478}
479
d9e2b173 480static void start_tcache_write(void *start, void *end)
d148d265 481{
482 mprotect_w_x(start, end, 0);
483}
484
485static void end_tcache_write(void *start, void *end)
486{
919981d0 487#if defined(__arm__) || defined(__aarch64__)
d148d265 488 size_t len = (char *)end - (char *)start;
489 #if defined(__BLACKBERRY_QNX__)
490 msync(start, len, MS_SYNC | MS_CACHE_ONLY | MS_INVALIDATE_ICACHE);
491 #elif defined(__MACH__)
492 sys_cache_control(kCacheFunctionPrepareForExecution, start, len);
493 #elif defined(VITA)
1e212a25 494 sceKernelSyncVMDomain(sceBlock, start, len);
495 #elif defined(_3DS)
496 ctr_flush_invalidate_cache();
3039c914 497 #elif defined(HAVE_LIBNX)
d9e2b173 498 if (g_jit.type == JitType_CodeMemory) {
499 armDCacheClean(start, len);
500 armICacheInvalidate((char *)start - ndrc_write_ofs, len);
aaece508 501 // as of v4.2.1 libnx lacks isb
502 __asm__ volatile("isb" ::: "memory");
d9e2b173 503 }
919981d0 504 #elif defined(__aarch64__)
505 // as of 2021, __clear_cache() is still broken on arm64
506 // so here is a custom one :(
507 clear_cache_arm64(start, end);
d148d265 508 #else
509 __clear_cache(start, end);
510 #endif
511 (void)len;
512#endif
513
514 mprotect_w_x(start, end, 1);
515}
516
517static void *start_block(void)
518{
519 u_char *end = out + MAX_OUTPUT_BLOCK_SIZE;
2a014d73 520 if (end > ndrc->translation_cache + sizeof(ndrc->translation_cache))
521 end = ndrc->translation_cache + sizeof(ndrc->translation_cache);
d9e2b173 522 start_tcache_write(NDRC_WRITE_OFFSET(out), NDRC_WRITE_OFFSET(end));
d148d265 523 return out;
524}
525
526static void end_block(void *start)
527{
d9e2b173 528 end_tcache_write(NDRC_WRITE_OFFSET(start), NDRC_WRITE_OFFSET(out));
d148d265 529}
530
af700b41 531#ifdef NDRC_CACHE_FLUSH_ALL
532
533static int needs_clear_cache;
534
535static void mark_clear_cache(void *target)
536{
537 if (!needs_clear_cache) {
d9e2b173 538 start_tcache_write(NDRC_WRITE_OFFSET(ndrc), NDRC_WRITE_OFFSET(ndrc + 1));
af700b41 539 needs_clear_cache = 1;
540 }
541}
542
543static void do_clear_cache(void)
544{
545 if (needs_clear_cache) {
d9e2b173 546 end_tcache_write(NDRC_WRITE_OFFSET(ndrc), NDRC_WRITE_OFFSET(ndrc + 1));
af700b41 547 needs_clear_cache = 0;
548 }
549}
550
551#else
552
919981d0 553// also takes care of w^x mappings when patching code
554static u_int needs_clear_cache[1<<(TARGET_SIZE_2-17)];
555
556static void mark_clear_cache(void *target)
557{
558 uintptr_t offset = (u_char *)target - ndrc->translation_cache;
559 u_int mask = 1u << ((offset >> 12) & 31);
560 if (!(needs_clear_cache[offset >> 17] & mask)) {
d9e2b173 561 char *start = (char *)NDRC_WRITE_OFFSET((uintptr_t)target & ~4095l);
919981d0 562 start_tcache_write(start, start + 4095);
563 needs_clear_cache[offset >> 17] |= mask;
564 }
565}
566
567// Clearing the cache is rather slow on ARM Linux, so mark the areas
568// that need to be cleared, and then only clear these areas once.
569static void do_clear_cache(void)
570{
571 int i, j;
572 for (i = 0; i < (1<<(TARGET_SIZE_2-17)); i++)
573 {
574 u_int bitmap = needs_clear_cache[i];
575 if (!bitmap)
576 continue;
577 for (j = 0; j < 32; j++)
578 {
579 u_char *start, *end;
93c0345b 580 if (!(bitmap & (1u << j)))
919981d0 581 continue;
582
583 start = ndrc->translation_cache + i*131072 + j*4096;
584 end = start + 4095;
585 for (j++; j < 32; j++) {
93c0345b 586 if (!(bitmap & (1u << j)))
919981d0 587 break;
588 end += 4096;
589 }
d9e2b173 590 end_tcache_write(NDRC_WRITE_OFFSET(start), NDRC_WRITE_OFFSET(end));
919981d0 591 }
592 needs_clear_cache[i] = 0;
593 }
594}
595
af700b41 596#endif // NDRC_CACHE_FLUSH_ALL
57871462 597
b6e87b2b 598#define NO_CYCLE_PENALTY_THR 12
599
32631e6a 600int cycle_multiplier_old;
24058131 601static int cycle_multiplier_active;
4e9dcd7f 602
603static int CLOCK_ADJUST(int x)
604{
24058131 605 int m = cycle_multiplier_active;
606 int s = (x >> 31) | 1;
a3203cf4 607 return (x * m + s * 50) / 100;
4e9dcd7f 608}
609
4919de1e 610static int ds_writes_rjump_rs(int i)
611{
ecca05e3 612 return dops[i].rs1 != 0
613 && (dops[i].rs1 == dops[i+1].rt1 || dops[i].rs1 == dops[i+1].rt2
614 || dops[i].rs1 == dops[i].rt1); // overwrites itself - same effect
4919de1e 615}
616
104df9d3 617// psx addr mirror masking (for invalidation)
618static u_int pmmask(u_int vaddr)
619{
620 vaddr &= ~0xe0000000;
621 if (vaddr < 0x01000000)
622 vaddr &= ~0x00e00000; // RAM mirrors
623 return vaddr;
624}
625
94d23bb9 626static u_int get_page(u_int vaddr)
57871462 627{
104df9d3 628 u_int page = pmmask(vaddr) >> 12;
93c0345b 629 if (page >= PAGE_COUNT / 2)
630 page = PAGE_COUNT / 2 + (page & (PAGE_COUNT / 2 - 1));
94d23bb9 631 return page;
632}
633
104df9d3 634// get a page for looking for a block that has vaddr
635// (needed because the block may start in previous page)
636static u_int get_page_prev(u_int vaddr)
d25604ca 637{
104df9d3 638 assert(MAXBLOCK <= (1 << 12));
639 u_int page = get_page(vaddr);
640 if (page & 511)
641 page--;
642 return page;
d25604ca 643}
94d23bb9 644
df4dc2b1 645static struct ht_entry *hash_table_get(u_int vaddr)
646{
647 return &hash_table[((vaddr>>16)^vaddr)&0xFFFF];
648}
649
104df9d3 650static void hash_table_add(u_int vaddr, void *tcaddr)
df4dc2b1 651{
104df9d3 652 struct ht_entry *ht_bin = hash_table_get(vaddr);
653 assert(tcaddr);
df4dc2b1 654 ht_bin->vaddr[1] = ht_bin->vaddr[0];
655 ht_bin->tcaddr[1] = ht_bin->tcaddr[0];
656 ht_bin->vaddr[0] = vaddr;
657 ht_bin->tcaddr[0] = tcaddr;
658}
659
104df9d3 660static void hash_table_remove(int vaddr)
661{
662 //printf("remove hash: %x\n",vaddr);
663 struct ht_entry *ht_bin = hash_table_get(vaddr);
664 if (ht_bin->vaddr[1] == vaddr) {
665 ht_bin->vaddr[1] = -1;
666 ht_bin->tcaddr[1] = NULL;
667 }
668 if (ht_bin->vaddr[0] == vaddr) {
669 ht_bin->vaddr[0] = ht_bin->vaddr[1];
670 ht_bin->tcaddr[0] = ht_bin->tcaddr[1];
671 ht_bin->vaddr[1] = -1;
672 ht_bin->tcaddr[1] = NULL;
673 }
674}
675
676static void mark_invalid_code(u_int vaddr, u_int len, char invalid)
398d6924 677{
ab4377be 678 u_int vaddr_m = vaddr & 0x1fffffff;
398d6924 679 u_int i, j;
ab4377be 680 for (i = vaddr_m & ~0xfff; i < vaddr_m + len; i += 0x1000) {
398d6924 681 // ram mirrors, but should not hurt bios
682 for (j = 0; j < 0x800000; j += 0x200000) {
683 invalid_code[(i|j) >> 12] =
684 invalid_code[(i|j|0x80000000u) >> 12] =
104df9d3 685 invalid_code[(i|j|0xa0000000u) >> 12] = invalid;
398d6924 686 }
687 }
882a08fc 688 if (!invalid && vaddr + len > inv_code_start && vaddr <= inv_code_end)
104df9d3 689 inv_code_start = inv_code_end = ~0;
398d6924 690}
691
93c0345b 692static int doesnt_expire_soon(u_char *tcaddr)
df4dc2b1 693{
93c0345b 694 u_int diff = (u_int)(tcaddr - out) & ((1u << TARGET_SIZE_2) - 1u);
695 return diff > EXPIRITY_OFFSET + MAX_OUTPUT_BLOCK_SIZE;
df4dc2b1 696}
697
9b495f6e 698static unused void check_for_block_changes(u_int start, u_int end)
699{
700 u_int start_page = get_page_prev(start);
701 u_int end_page = get_page(end - 1);
702 u_int page;
703
704 for (page = start_page; page <= end_page; page++) {
705 struct block_info *block;
706 for (block = blocks[page]; block != NULL; block = block->next) {
707 if (block->is_dirty)
708 continue;
709 if (memcmp(block->source, block->copy, block->len)) {
710 printf("bad block %08x-%08x %016llx %016llx @%08x\n",
711 block->start, block->start + block->len,
712 *(long long *)block->source, *(long long *)block->copy, psxRegs.pc);
713 fflush(stdout);
714 abort();
715 }
716 }
717 }
718}
719
104df9d3 720static void *try_restore_block(u_int vaddr, u_int start_page, u_int end_page)
398d6924 721{
104df9d3 722 void *found_clean = NULL;
723 u_int i, page;
398d6924 724
ece032e6 725 stat_inc(stat_restore_tries);
104df9d3 726 for (page = start_page; page <= end_page; page++) {
727 struct block_info *block;
728 for (block = blocks[page]; block != NULL; block = block->next) {
729 if (vaddr < block->start)
730 break;
731 if (!block->is_dirty || vaddr >= block->start + block->len)
732 continue;
733 for (i = 0; i < block->jump_in_cnt; i++)
734 if (block->jump_in[i].vaddr == vaddr)
735 break;
736 if (i == block->jump_in_cnt)
737 continue;
738 assert(block->source && block->copy);
739 stat_inc(stat_restore_compares);
740 if (memcmp(block->source, block->copy, block->len))
741 continue;
398d6924 742
3280e616 743 block->is_dirty = block->inv_near_misses = 0;
104df9d3 744 found_clean = block->jump_in[i].addr;
745 hash_table_add(vaddr, found_clean);
746 mark_invalid_code(block->start, block->len, 0);
747 stat_inc(stat_bc_restore);
748 inv_debug("INV: restored %08x %p (%d)\n", vaddr, found_clean, block->jump_in_cnt);
749 return found_clean;
398d6924 750 }
398d6924 751 }
104df9d3 752 return NULL;
398d6924 753}
754
de6dbc52 755// this doesn't normally happen
756static noinline u_int generate_exception(u_int pc)
757{
758 //if (execBreakCheck(&psxRegs, pc))
759 // return psxRegs.pc;
760
761 // generate an address or bus error
762 psxRegs.CP0.n.Cause &= 0x300;
763 psxRegs.CP0.n.EPC = pc;
764 if (pc & 3) {
765 psxRegs.CP0.n.Cause |= R3000E_AdEL << 2;
766 psxRegs.CP0.n.BadVAddr = pc;
767#ifdef DRC_DBG
768 last_count -= 2;
769#endif
770 } else
771 psxRegs.CP0.n.Cause |= R3000E_IBE << 2;
772 return (psxRegs.pc = 0x80000080);
773}
774
94d23bb9 775// Get address from virtual address
776// This is called from the recompiled JR/JALR instructions
104df9d3 777static void noinline *get_addr(u_int vaddr, int can_compile)
94d23bb9 778{
104df9d3 779 u_int start_page = get_page_prev(vaddr);
780 u_int i, page, end_page = get_page(vaddr);
781 void *found_clean = NULL;
398d6924 782
ece032e6 783 stat_inc(stat_jump_in_lookups);
104df9d3 784 for (page = start_page; page <= end_page; page++) {
785 const struct block_info *block;
786 for (block = blocks[page]; block != NULL; block = block->next) {
787 if (vaddr < block->start)
788 break;
789 if (block->is_dirty || vaddr >= block->start + block->len)
790 continue;
791 for (i = 0; i < block->jump_in_cnt; i++)
792 if (block->jump_in[i].vaddr == vaddr)
793 break;
794 if (i == block->jump_in_cnt)
795 continue;
796 found_clean = block->jump_in[i].addr;
797 hash_table_add(vaddr, found_clean);
798 return found_clean;
57871462 799 }
57871462 800 }
104df9d3 801 found_clean = try_restore_block(vaddr, start_page, end_page);
802 if (found_clean)
803 return found_clean;
804
805 if (!can_compile)
806 return NULL;
398d6924 807
808 int r = new_recompile_block(vaddr);
de6dbc52 809 if (likely(r == 0))
104df9d3 810 return ndrc_get_addr_ht(vaddr);
df4dc2b1 811
de6dbc52 812 return ndrc_get_addr_ht(generate_exception(vaddr));
57871462 813}
104df9d3 814
57871462 815// Look up address in hash table first
104df9d3 816void *ndrc_get_addr_ht_param(u_int vaddr, int can_compile)
57871462 817{
9b495f6e 818 //check_for_block_changes(vaddr, vaddr + MAXBLOCK);
df4dc2b1 819 const struct ht_entry *ht_bin = hash_table_get(vaddr);
277718fa 820 u_int vaddr_a = vaddr & ~3;
104df9d3 821 stat_inc(stat_ht_lookups);
277718fa 822 if (ht_bin->vaddr[0] == vaddr_a) return ht_bin->tcaddr[0];
823 if (ht_bin->vaddr[1] == vaddr_a) return ht_bin->tcaddr[1];
104df9d3 824 return get_addr(vaddr, can_compile);
825}
826
827void *ndrc_get_addr_ht(u_int vaddr)
828{
829 return ndrc_get_addr_ht_param(vaddr, 1);
57871462 830}
831
6cc8d23c 832static void clear_all_regs(signed char regmap[])
57871462 833{
6cc8d23c 834 memset(regmap, -1, sizeof(regmap[0]) * HOST_REGS);
57871462 835}
836
53358c1d 837// get_reg: get allocated host reg from mips reg
838// returns -1 if no such mips reg was allocated
cdc2da64 839#if defined(__arm__) && defined(HAVE_ARMV6) && HOST_REGS == 13 && EXCLUDE_REG == 11
840
841extern signed char get_reg(const signed char regmap[], signed char r);
842
843#else
844
9de8a0c3 845static signed char get_reg(const signed char regmap[], signed char r)
57871462 846{
847 int hr;
9de8a0c3 848 for (hr = 0; hr < HOST_REGS; hr++) {
849 if (hr == EXCLUDE_REG)
850 continue;
851 if (regmap[hr] == r)
852 return hr;
853 }
854 return -1;
855}
856
cdc2da64 857#endif
858
a5cd72d0 859// get reg suitable for writing
860static signed char get_reg_w(const signed char regmap[], signed char r)
861{
862 return r == 0 ? -1 : get_reg(regmap, r);
863}
864
53358c1d 865// get reg as mask bit (1 << hr)
866static u_int get_regm(const signed char regmap[], signed char r)
867{
868 return (1u << (get_reg(regmap, r) & 31)) & ~(1u << 31);
869}
870
9de8a0c3 871static signed char get_reg_temp(const signed char regmap[])
872{
873 int hr;
874 for (hr = 0; hr < HOST_REGS; hr++) {
875 if (hr == EXCLUDE_REG)
876 continue;
877 if (regmap[hr] == (signed char)-1)
878 return hr;
879 }
57871462 880 return -1;
881}
882
883// Find a register that is available for two consecutive cycles
d1e4ebd9 884static signed char get_reg2(signed char regmap1[], const signed char regmap2[], int r)
57871462 885{
886 int hr;
887 for (hr=0;hr<HOST_REGS;hr++) if(hr!=EXCLUDE_REG&&regmap1[hr]==r&&regmap2[hr]==r) return hr;
888 return -1;
889}
890
53dc27f6 891// reverse reg map: mips -> host
892#define RRMAP_SIZE 64
893static void make_rregs(const signed char regmap[], signed char rrmap[RRMAP_SIZE],
894 u_int *regs_can_change)
895{
896 u_int r, hr, hr_can_change = 0;
897 memset(rrmap, -1, RRMAP_SIZE);
898 for (hr = 0; hr < HOST_REGS; )
899 {
900 r = regmap[hr];
901 rrmap[r & (RRMAP_SIZE - 1)] = hr;
902 // only add mips $1-$31+$lo, others shifted out
903 hr_can_change |= (uint64_t)1 << (hr + ((r - 1) & 32));
904 hr++;
905 if (hr == EXCLUDE_REG)
906 hr++;
907 }
908 hr_can_change |= 1u << (rrmap[33] & 31);
909 hr_can_change |= 1u << (rrmap[CCREG] & 31);
910 hr_can_change &= ~(1u << 31);
911 *regs_can_change = hr_can_change;
912}
913
914// same as get_reg, but takes rrmap
915static signed char get_rreg(signed char rrmap[RRMAP_SIZE], signed char r)
916{
917 assert(0 <= r && r < RRMAP_SIZE);
918 return rrmap[r];
919}
920
9de8a0c3 921static int count_free_regs(const signed char regmap[])
57871462 922{
923 int count=0;
924 int hr;
925 for(hr=0;hr<HOST_REGS;hr++)
926 {
927 if(hr!=EXCLUDE_REG) {
928 if(regmap[hr]<0) count++;
929 }
930 }
931 return count;
932}
933
9de8a0c3 934static void dirty_reg(struct regstat *cur, signed char reg)
57871462 935{
936 int hr;
9de8a0c3 937 if (!reg) return;
938 hr = get_reg(cur->regmap, reg);
939 if (hr >= 0)
940 cur->dirty |= 1<<hr;
57871462 941}
942
40fca85b 943static void set_const(struct regstat *cur, signed char reg, uint32_t value)
57871462 944{
945 int hr;
9de8a0c3 946 if (!reg) return;
947 hr = get_reg(cur->regmap, reg);
948 if (hr >= 0) {
949 cur->isconst |= 1<<hr;
950 current_constmap[hr] = value;
57871462 951 }
952}
953
40fca85b 954static void clear_const(struct regstat *cur, signed char reg)
57871462 955{
956 int hr;
9de8a0c3 957 if (!reg) return;
958 hr = get_reg(cur->regmap, reg);
959 if (hr >= 0)
960 cur->isconst &= ~(1<<hr);
57871462 961}
962
9de8a0c3 963static int is_const(const struct regstat *cur, signed char reg)
57871462 964{
965 int hr;
9de8a0c3 966 if (reg < 0) return 0;
967 if (!reg) return 1;
968 hr = get_reg(cur->regmap, reg);
969 if (hr >= 0)
970 return (cur->isconst>>hr)&1;
57871462 971 return 0;
972}
40fca85b 973
9de8a0c3 974static uint32_t get_const(const struct regstat *cur, signed char reg)
57871462 975{
976 int hr;
9de8a0c3 977 if (!reg) return 0;
978 hr = get_reg(cur->regmap, reg);
979 if (hr >= 0)
980 return current_constmap[hr];
981
982 SysPrintf("Unknown constant in r%d\n", reg);
7c3a5182 983 abort();
57871462 984}
985
986// Least soon needed registers
987// Look at the next ten instructions and see which registers
988// will be used. Try not to reallocate these.
90f98e7c 989static void lsn(u_char hsn[], int i)
57871462 990{
991 int j;
992 int b=-1;
993 for(j=0;j<9;j++)
994 {
995 if(i+j>=slen) {
996 j=slen-i-1;
997 break;
998 }
fe807a8a 999 if (dops[i+j].is_ujump)
57871462 1000 {
1001 // Don't go past an unconditonal jump
1002 j++;
1003 break;
1004 }
1005 }
1006 for(;j>=0;j--)
1007 {
cf95b4f0 1008 if(dops[i+j].rs1) hsn[dops[i+j].rs1]=j;
1009 if(dops[i+j].rs2) hsn[dops[i+j].rs2]=j;
1010 if(dops[i+j].rt1) hsn[dops[i+j].rt1]=j;
1011 if(dops[i+j].rt2) hsn[dops[i+j].rt2]=j;
1012 if(dops[i+j].itype==STORE || dops[i+j].itype==STORELR) {
57871462 1013 // Stores can allocate zero
cf95b4f0 1014 hsn[dops[i+j].rs1]=j;
1015 hsn[dops[i+j].rs2]=j;
57871462 1016 }
37387d8b 1017 if (ram_offset && (dops[i+j].is_load || dops[i+j].is_store))
1018 hsn[ROREG] = j;
57871462 1019 // On some architectures stores need invc_ptr
1020 #if defined(HOST_IMM8)
37387d8b 1021 if (dops[i+j].is_store)
1022 hsn[INVCP] = j;
57871462 1023 #endif
cf95b4f0 1024 if(i+j>=0&&(dops[i+j].itype==UJUMP||dops[i+j].itype==CJUMP||dops[i+j].itype==SJUMP))
57871462 1025 {
1026 hsn[CCREG]=j;
1027 b=j;
1028 }
1029 }
1030 if(b>=0)
1031 {
277718fa 1032 if(cinfo[i+b].ba>=start && cinfo[i+b].ba<(start+slen*4))
57871462 1033 {
1034 // Follow first branch
277718fa 1035 int t=(cinfo[i+b].ba-start)>>2;
57871462 1036 j=7-b;if(t+j>=slen) j=slen-t-1;
1037 for(;j>=0;j--)
1038 {
cf95b4f0 1039 if(dops[t+j].rs1) if(hsn[dops[t+j].rs1]>j+b+2) hsn[dops[t+j].rs1]=j+b+2;
1040 if(dops[t+j].rs2) if(hsn[dops[t+j].rs2]>j+b+2) hsn[dops[t+j].rs2]=j+b+2;
1041 //if(dops[t+j].rt1) if(hsn[dops[t+j].rt1]>j+b+2) hsn[dops[t+j].rt1]=j+b+2;
1042 //if(dops[t+j].rt2) if(hsn[dops[t+j].rt2]>j+b+2) hsn[dops[t+j].rt2]=j+b+2;
57871462 1043 }
1044 }
1045 // TODO: preferred register based on backward branch
1046 }
1047 // Delay slot should preferably not overwrite branch conditions or cycle count
fe807a8a 1048 if (i > 0 && dops[i-1].is_jump) {
cf95b4f0 1049 if(dops[i-1].rs1) if(hsn[dops[i-1].rs1]>1) hsn[dops[i-1].rs1]=1;
1050 if(dops[i-1].rs2) if(hsn[dops[i-1].rs2]>1) hsn[dops[i-1].rs2]=1;
57871462 1051 hsn[CCREG]=1;
1052 // ...or hash tables
1053 hsn[RHASH]=1;
1054 hsn[RHTBL]=1;
1055 }
1056 // Coprocessor load/store needs FTEMP, even if not declared
37387d8b 1057 if(dops[i].itype==C2LS) {
57871462 1058 hsn[FTEMP]=0;
1059 }
33a1eda1 1060 // Load/store L/R also uses FTEMP as a temporary register
1061 if (dops[i].itype == LOADLR || dops[i].itype == STORELR) {
57871462 1062 hsn[FTEMP]=0;
1063 }
57871462 1064 // Don't remove the miniht registers
cf95b4f0 1065 if(dops[i].itype==UJUMP||dops[i].itype==RJUMP)
57871462 1066 {
1067 hsn[RHASH]=0;
1068 hsn[RHTBL]=0;
1069 }
1070}
1071
1072// We only want to allocate registers if we're going to use them again soon
4149788d 1073static int needed_again(int r, int i)
57871462 1074{
1075 int j;
1076 int b=-1;
1077 int rn=10;
9f51b4b9 1078
fe807a8a 1079 if (i > 0 && dops[i-1].is_ujump)
57871462 1080 {
277718fa 1081 if(cinfo[i-1].ba<start || cinfo[i-1].ba>start+slen*4-4)
57871462 1082 return 0; // Don't need any registers if exiting the block
1083 }
1084 for(j=0;j<9;j++)
1085 {
1086 if(i+j>=slen) {
1087 j=slen-i-1;
1088 break;
1089 }
fe807a8a 1090 if (dops[i+j].is_ujump)
57871462 1091 {
1092 // Don't go past an unconditonal jump
1093 j++;
1094 break;
1095 }
a5cd72d0 1096 if (dops[i+j].is_exception)
57871462 1097 {
1098 break;
1099 }
1100 }
1101 for(;j>=1;j--)
1102 {
cf95b4f0 1103 if(dops[i+j].rs1==r) rn=j;
1104 if(dops[i+j].rs2==r) rn=j;
57871462 1105 if((unneeded_reg[i+j]>>r)&1) rn=10;
cf95b4f0 1106 if(i+j>=0&&(dops[i+j].itype==UJUMP||dops[i+j].itype==CJUMP||dops[i+j].itype==SJUMP))
57871462 1107 {
1108 b=j;
1109 }
1110 }
b7217e13 1111 if(rn<10) return 1;
581335b0 1112 (void)b;
57871462 1113 return 0;
1114}
1115
1116// Try to match register allocations at the end of a loop with those
1117// at the beginning
4149788d 1118static int loop_reg(int i, int r, int hr)
57871462 1119{
1120 int j,k;
1121 for(j=0;j<9;j++)
1122 {
1123 if(i+j>=slen) {
1124 j=slen-i-1;
1125 break;
1126 }
fe807a8a 1127 if (dops[i+j].is_ujump)
57871462 1128 {
1129 // Don't go past an unconditonal jump
1130 j++;
1131 break;
1132 }
1133 }
1134 k=0;
1135 if(i>0){
cf95b4f0 1136 if(dops[i-1].itype==UJUMP||dops[i-1].itype==CJUMP||dops[i-1].itype==SJUMP)
57871462 1137 k--;
1138 }
1139 for(;k<j;k++)
1140 {
00fa9369 1141 assert(r < 64);
1142 if((unneeded_reg[i+k]>>r)&1) return hr;
cf95b4f0 1143 if(i+k>=0&&(dops[i+k].itype==UJUMP||dops[i+k].itype==CJUMP||dops[i+k].itype==SJUMP))
57871462 1144 {
277718fa 1145 if(cinfo[i+k].ba>=start && cinfo[i+k].ba<(start+i*4))
57871462 1146 {
277718fa 1147 int t=(cinfo[i+k].ba-start)>>2;
57871462 1148 int reg=get_reg(regs[t].regmap_entry,r);
1149 if(reg>=0) return reg;
1150 //reg=get_reg(regs[t+1].regmap_entry,r);
1151 //if(reg>=0) return reg;
1152 }
1153 }
1154 }
1155 return hr;
1156}
1157
1158
1159// Allocate every register, preserving source/target regs
4149788d 1160static void alloc_all(struct regstat *cur,int i)
57871462 1161{
1162 int hr;
9f51b4b9 1163
57871462 1164 for(hr=0;hr<HOST_REGS;hr++) {
1165 if(hr!=EXCLUDE_REG) {
9de8a0c3 1166 if((cur->regmap[hr]!=dops[i].rs1)&&(cur->regmap[hr]!=dops[i].rs2)&&
1167 (cur->regmap[hr]!=dops[i].rt1)&&(cur->regmap[hr]!=dops[i].rt2))
57871462 1168 {
1169 cur->regmap[hr]=-1;
1170 cur->dirty&=~(1<<hr);
1171 }
1172 // Don't need zeros
9de8a0c3 1173 if(cur->regmap[hr]==0)
57871462 1174 {
1175 cur->regmap[hr]=-1;
1176 cur->dirty&=~(1<<hr);
1177 }
1178 }
1179 }
1180}
1181
d1e4ebd9 1182#ifndef NDEBUG
1183static int host_tempreg_in_use;
1184
1185static void host_tempreg_acquire(void)
1186{
1187 assert(!host_tempreg_in_use);
1188 host_tempreg_in_use = 1;
1189}
1190
1191static void host_tempreg_release(void)
1192{
1193 host_tempreg_in_use = 0;
1194}
1195#else
1196static void host_tempreg_acquire(void) {}
1197static void host_tempreg_release(void) {}
1198#endif
1199
32631e6a 1200#ifdef ASSEM_PRINT
8062d65a 1201extern void gen_interupt();
1202extern void do_insn_cmp();
d1e4ebd9 1203#define FUNCNAME(f) { f, " " #f }
8062d65a 1204static const struct {
d1e4ebd9 1205 void *addr;
8062d65a 1206 const char *name;
1207} function_names[] = {
1208 FUNCNAME(cc_interrupt),
1209 FUNCNAME(gen_interupt),
104df9d3 1210 FUNCNAME(ndrc_get_addr_ht),
8062d65a 1211 FUNCNAME(jump_handler_read8),
1212 FUNCNAME(jump_handler_read16),
1213 FUNCNAME(jump_handler_read32),
1214 FUNCNAME(jump_handler_write8),
1215 FUNCNAME(jump_handler_write16),
1216 FUNCNAME(jump_handler_write32),
9b495f6e 1217 FUNCNAME(ndrc_write_invalidate_one),
1218 FUNCNAME(ndrc_write_invalidate_many),
3968e69e 1219 FUNCNAME(jump_to_new_pc),
d1150cd6 1220 FUNCNAME(jump_break),
1221 FUNCNAME(jump_break_ds),
1222 FUNCNAME(jump_syscall),
1223 FUNCNAME(jump_syscall_ds),
a5cd72d0 1224 FUNCNAME(jump_overflow),
1225 FUNCNAME(jump_overflow_ds),
277718fa 1226 FUNCNAME(jump_addrerror),
1227 FUNCNAME(jump_addrerror_ds),
81dbbf4c 1228 FUNCNAME(call_gteStall),
8062d65a 1229 FUNCNAME(new_dyna_leave),
1230 FUNCNAME(pcsx_mtc0),
1231 FUNCNAME(pcsx_mtc0_ds),
277718fa 1232 FUNCNAME(execI),
1233#ifdef __aarch64__
1234 FUNCNAME(do_memhandler_pre),
1235 FUNCNAME(do_memhandler_post),
1236#endif
32631e6a 1237#ifdef DRC_DBG
33a1eda1 1238# ifdef __aarch64__
1239 FUNCNAME(do_insn_cmp_arm64),
1240# else
8062d65a 1241 FUNCNAME(do_insn_cmp),
33a1eda1 1242# endif
32631e6a 1243#endif
8062d65a 1244};
1245
d1e4ebd9 1246static const char *func_name(const void *a)
8062d65a 1247{
1248 int i;
1249 for (i = 0; i < sizeof(function_names)/sizeof(function_names[0]); i++)
1250 if (function_names[i].addr == a)
1251 return function_names[i].name;
1252 return "";
1253}
a5cd72d0 1254
1255static const char *fpofs_name(u_int ofs)
1256{
1257 u_int *p = (u_int *)&dynarec_local + ofs/sizeof(u_int);
1258 static char buf[64];
1259 switch (ofs) {
1260 #define ofscase(x) case LO_##x: return " ; " #x
1261 ofscase(next_interupt);
de6dbc52 1262 ofscase(cycle_count);
a5cd72d0 1263 ofscase(last_count);
1264 ofscase(pending_exception);
1265 ofscase(stop);
1266 ofscase(address);
1267 ofscase(lo);
1268 ofscase(hi);
1269 ofscase(PC);
1270 ofscase(cycle);
1271 ofscase(mem_rtab);
1272 ofscase(mem_wtab);
1273 ofscase(psxH_ptr);
1274 ofscase(invc_ptr);
1275 ofscase(ram_offset);
1276 #undef ofscase
1277 }
1278 buf[0] = 0;
1279 if (psxRegs.GPR.r <= p && p < &psxRegs.GPR.r[32])
1280 snprintf(buf, sizeof(buf), " ; r%d", (int)(p - psxRegs.GPR.r));
1281 else if (psxRegs.CP0.r <= p && p < &psxRegs.CP0.r[32])
1282 snprintf(buf, sizeof(buf), " ; cp0 $%d", (int)(p - psxRegs.CP0.r));
1283 else if (psxRegs.CP2D.r <= p && p < &psxRegs.CP2D.r[32])
1284 snprintf(buf, sizeof(buf), " ; cp2d $%d", (int)(p - psxRegs.CP2D.r));
1285 else if (psxRegs.CP2C.r <= p && p < &psxRegs.CP2C.r[32])
1286 snprintf(buf, sizeof(buf), " ; cp2c $%d", (int)(p - psxRegs.CP2C.r));
1287 return buf;
1288}
8062d65a 1289#else
1290#define func_name(x) ""
a5cd72d0 1291#define fpofs_name(x) ""
8062d65a 1292#endif
1293
57871462 1294#ifdef __i386__
1295#include "assem_x86.c"
1296#endif
1297#ifdef __x86_64__
1298#include "assem_x64.c"
1299#endif
1300#ifdef __arm__
1301#include "assem_arm.c"
1302#endif
be516ebe 1303#ifdef __aarch64__
1304#include "assem_arm64.c"
1305#endif
57871462 1306
2a014d73 1307static void *get_trampoline(const void *f)
1308{
d9e2b173 1309 struct ndrc_tramp *tramp = NDRC_WRITE_OFFSET(&ndrc->tramp);
2a014d73 1310 size_t i;
1311
d9e2b173 1312 for (i = 0; i < ARRAY_SIZE(tramp->f); i++) {
1313 if (tramp->f[i] == f || tramp->f[i] == NULL)
2a014d73 1314 break;
1315 }
d9e2b173 1316 if (i == ARRAY_SIZE(tramp->f)) {
2a014d73 1317 SysPrintf("trampoline table is full, last func %p\n", f);
1318 abort();
1319 }
d9e2b173 1320 if (tramp->f[i] == NULL) {
1321 start_tcache_write(&tramp->f[i], &tramp->f[i + 1]);
1322 tramp->f[i] = f;
1323 end_tcache_write(&tramp->f[i], &tramp->f[i + 1]);
1324#ifdef HAVE_LIBNX
1325 // invalidate the RX mirror (unsure if necessary, but just in case...)
1326 armDCacheFlush(&ndrc->tramp.f[i], sizeof(ndrc->tramp.f[i]));
1327#endif
2a014d73 1328 }
1329 return &ndrc->tramp.ops[i];
1330}
1331
1332static void emit_far_jump(const void *f)
1333{
1334 if (can_jump_or_call(f)) {
1335 emit_jmp(f);
1336 return;
1337 }
1338
1339 f = get_trampoline(f);
1340 emit_jmp(f);
1341}
1342
1343static void emit_far_call(const void *f)
1344{
1345 if (can_jump_or_call(f)) {
1346 emit_call(f);
1347 return;
1348 }
1349
1350 f = get_trampoline(f);
1351 emit_call(f);
1352}
1353
57871462 1354// Check if an address is already compiled
1355// but don't return addresses which are about to expire from the cache
4149788d 1356static void *check_addr(u_int vaddr)
57871462 1357{
df4dc2b1 1358 struct ht_entry *ht_bin = hash_table_get(vaddr);
1359 size_t i;
b14b6a8f 1360 for (i = 0; i < ARRAY_SIZE(ht_bin->vaddr); i++) {
df4dc2b1 1361 if (ht_bin->vaddr[i] == vaddr)
93c0345b 1362 if (doesnt_expire_soon(ht_bin->tcaddr[i]))
104df9d3 1363 return ht_bin->tcaddr[i];
57871462 1364 }
104df9d3 1365
1366 // refactor to get_addr_nocompile?
1367 u_int start_page = get_page_prev(vaddr);
1368 u_int page, end_page = get_page(vaddr);
1369
1370 stat_inc(stat_jump_in_lookups);
1371 for (page = start_page; page <= end_page; page++) {
1372 const struct block_info *block;
1373 for (block = blocks[page]; block != NULL; block = block->next) {
1374 if (vaddr < block->start)
1375 break;
1376 if (block->is_dirty || vaddr >= block->start + block->len)
1377 continue;
1378 if (!doesnt_expire_soon(ndrc->translation_cache + block->tc_offs))
1379 continue;
1380 for (i = 0; i < block->jump_in_cnt; i++)
1381 if (block->jump_in[i].vaddr == vaddr)
1382 break;
1383 if (i == block->jump_in_cnt)
1384 continue;
1385
1386 // Update existing entry with current address
1387 void *addr = block->jump_in[i].addr;
1388 if (ht_bin->vaddr[0] == vaddr) {
1389 ht_bin->tcaddr[0] = addr;
1390 return addr;
1391 }
1392 if (ht_bin->vaddr[1] == vaddr) {
1393 ht_bin->tcaddr[1] = addr;
1394 return addr;
1395 }
1396 // Insert into hash table with low priority.
1397 // Don't evict existing entries, as they are probably
1398 // addresses that are being accessed frequently.
1399 if (ht_bin->vaddr[0] == -1) {
1400 ht_bin->vaddr[0] = vaddr;
1401 ht_bin->tcaddr[0] = addr;
57871462 1402 }
104df9d3 1403 else if (ht_bin->vaddr[1] == -1) {
1404 ht_bin->vaddr[1] = vaddr;
1405 ht_bin->tcaddr[1] = addr;
1406 }
1407 return addr;
57871462 1408 }
57871462 1409 }
104df9d3 1410 return NULL;
57871462 1411}
1412
104df9d3 1413static void blocks_clear(struct block_info **head)
1414{
1415 struct block_info *cur, *next;
1416
1417 if ((cur = *head)) {
1418 *head = NULL;
1419 while (cur) {
1420 next = cur->next;
1421 free(cur);
1422 cur = next;
1423 }
1424 }
1425}
1426
93c0345b 1427static int blocks_remove_matching_addrs(struct block_info **head,
1428 u_int base_offs, int shift)
104df9d3 1429{
1430 struct block_info *next;
93c0345b 1431 int hit = 0;
104df9d3 1432 while (*head) {
93c0345b 1433 if ((((*head)->tc_offs ^ base_offs) >> shift) == 0) {
9b495f6e 1434 inv_debug("EXP: rm block %08x (tc_offs %x)\n", (*head)->start, (*head)->tc_offs);
104df9d3 1435 invalidate_block(*head);
1436 next = (*head)->next;
1437 free(*head);
1438 *head = next;
1439 stat_dec(stat_blocks);
93c0345b 1440 hit = 1;
104df9d3 1441 }
1442 else
1443 {
1444 head = &((*head)->next);
1445 }
1446 }
93c0345b 1447 return hit;
104df9d3 1448}
57871462 1449
1450// This is called when we write to a compiled block (see do_invstub)
b7ad2f2c 1451static void unlink_jumps_vaddr_range(u_int start, u_int end)
57871462 1452{
104df9d3 1453 u_int page, start_page = get_page(start), end_page = get_page(end - 1);
b7ad2f2c 1454 int i;
104df9d3 1455
1456 for (page = start_page; page <= end_page; page++) {
b7ad2f2c 1457 struct jump_info *ji = jumps[page];
1458 if (ji == NULL)
1459 continue;
1460 for (i = 0; i < ji->count; ) {
1461 if (ji->e[i].target_vaddr < start || ji->e[i].target_vaddr >= end) {
1462 i++;
104df9d3 1463 continue;
1464 }
b7ad2f2c 1465
1466 inv_debug("INV: rm link to %08x (tc_offs %zx)\n", ji->e[i].target_vaddr,
1467 (u_char *)ji->e[i].stub - ndrc->translation_cache);
1468 void *host_addr = find_extjump_insn(ji->e[i].stub);
104df9d3 1469 mark_clear_cache(host_addr);
b7ad2f2c 1470 set_jump_target(host_addr, ji->e[i].stub); // point back to dyna_linker stub
104df9d3 1471
104df9d3 1472 stat_dec(stat_links);
b7ad2f2c 1473 ji->count--;
1474 if (i < ji->count) {
1475 ji->e[i] = ji->e[ji->count];
1476 continue;
1477 }
1478 i++;
1479 }
1480 }
1481}
1482
1483static void unlink_jumps_tc_range(struct jump_info *ji, u_int base_offs, int shift)
1484{
1485 int i;
1486 if (ji == NULL)
1487 return;
1488 for (i = 0; i < ji->count; ) {
1489 u_int tc_offs = (u_char *)ji->e[i].stub - ndrc->translation_cache;
1490 if (((tc_offs ^ base_offs) >> shift) != 0) {
1491 i++;
1492 continue;
1493 }
1494
9b495f6e 1495 inv_debug("EXP: rm link to %08x (tc_offs %x)\n", ji->e[i].target_vaddr, tc_offs);
b7ad2f2c 1496 stat_dec(stat_links);
1497 ji->count--;
1498 if (i < ji->count) {
1499 ji->e[i] = ji->e[ji->count];
1500 continue;
104df9d3 1501 }
b7ad2f2c 1502 i++;
57871462 1503 }
104df9d3 1504}
9f51b4b9 1505
104df9d3 1506static void invalidate_block(struct block_info *block)
1507{
1508 u_int i;
f76eeef9 1509
104df9d3 1510 block->is_dirty = 1;
b7ad2f2c 1511 unlink_jumps_vaddr_range(block->start, block->start + block->len);
104df9d3 1512 for (i = 0; i < block->jump_in_cnt; i++)
1513 hash_table_remove(block->jump_in[i].vaddr);
57871462 1514}
9be4ba64 1515
104df9d3 1516static int invalidate_range(u_int start, u_int end,
1517 u32 *inv_start_ret, u32 *inv_end_ret)
9be4ba64 1518{
3280e616 1519 struct block_info *last_block = NULL;
104df9d3 1520 u_int start_page = get_page_prev(start);
1521 u_int end_page = get_page(end - 1);
1522 u_int start_m = pmmask(start);
ab4377be 1523 u_int end_m = pmmask(end - 1);
104df9d3 1524 u_int inv_start, inv_end;
1525 u_int blk_start_m, blk_end_m;
1526 u_int page;
1527 int hit = 0;
1528
1529 // additional area without code (to supplement invalid_code[]), [start, end)
9b495f6e 1530 // avoids excessive ndrc_write_invalidate*() calls
104df9d3 1531 inv_start = start_m & ~0xfff;
1532 inv_end = end_m | 0xfff;
1533
1534 for (page = start_page; page <= end_page; page++) {
1535 struct block_info *block;
1536 for (block = blocks[page]; block != NULL; block = block->next) {
1537 if (block->is_dirty)
1538 continue;
3280e616 1539 last_block = block;
104df9d3 1540 blk_end_m = pmmask(block->start + block->len);
1541 if (blk_end_m <= start_m) {
1542 inv_start = max(inv_start, blk_end_m);
1543 continue;
1544 }
1545 blk_start_m = pmmask(block->start);
1546 if (end_m <= blk_start_m) {
1547 inv_end = min(inv_end, blk_start_m - 1);
1548 continue;
9be4ba64 1549 }
104df9d3 1550 if (!block->source) // "hack" block - leave it alone
1551 continue;
1552
1553 hit++;
1554 invalidate_block(block);
1555 stat_inc(stat_inv_hits);
9be4ba64 1556 }
9be4ba64 1557 }
104df9d3 1558
3280e616 1559 if (!hit && last_block && last_block->source) {
1560 // could be some leftover unused block, uselessly trapping writes
1561 last_block->inv_near_misses++;
1562 if (last_block->inv_near_misses > 128) {
1563 invalidate_block(last_block);
1564 stat_inc(stat_inv_hits);
1565 hit++;
1566 }
1567 }
104df9d3 1568 if (hit) {
1569 do_clear_cache();
1570#ifdef USE_MINI_HT
1571 memset(mini_ht, -1, sizeof(mini_ht));
1572#endif
1573 }
3280e616 1574
104df9d3 1575 if (inv_start <= (start_m & ~0xfff) && inv_end >= (start_m | 0xfff))
1576 // the whole page is empty now
1577 mark_invalid_code(start, 1, 1);
1578
1579 if (inv_start_ret) *inv_start_ret = inv_start | (start & 0xe0000000);
1580 if (inv_end_ret) *inv_end_ret = inv_end | (end & 0xe0000000);
1581 return hit;
9be4ba64 1582}
1583
104df9d3 1584void new_dynarec_invalidate_range(unsigned int start, unsigned int end)
1585{
1586 invalidate_range(start, end, NULL, NULL);
1587}
1588
9b495f6e 1589static void ndrc_write_invalidate_many(u_int start, u_int end)
57871462 1590{
9be4ba64 1591 // this check is done by the caller
1592 //if (inv_code_start<=addr&&addr<=inv_code_end) { rhits++; return; }
9b495f6e 1593 int ret = invalidate_range(start, end, &inv_code_start, &inv_code_end);
1594#ifdef INV_DEBUG_W
1595 int invc = invalid_code[start >> 12];
1596 u_int len = end - start;
104df9d3 1597 if (ret)
9b495f6e 1598 printf("INV ADDR: %08x/%02x hit %d blocks\n", start, len, ret);
104df9d3 1599 else
9b495f6e 1600 printf("INV ADDR: %08x/%02x miss, inv %08x-%08x invc %d->%d\n", start, len,
1601 inv_code_start, inv_code_end, invc, invalid_code[start >> 12]);
1602 check_for_block_changes(start, end);
1603#endif
ece032e6 1604 stat_inc(stat_inv_addr_calls);
9b495f6e 1605 (void)ret;
1606}
1607
1608void ndrc_write_invalidate_one(u_int addr)
1609{
1610 ndrc_write_invalidate_many(addr, addr + 4);
57871462 1611}
9be4ba64 1612
dd3a91a1 1613// This is called when loading a save state.
1614// Anything could have changed, so invalidate everything.
104df9d3 1615void new_dynarec_invalidate_all_pages(void)
57871462 1616{
104df9d3 1617 struct block_info *block;
581335b0 1618 u_int page;
104df9d3 1619 for (page = 0; page < ARRAY_SIZE(blocks); page++) {
1620 for (block = blocks[page]; block != NULL; block = block->next) {
1621 if (block->is_dirty)
1622 continue;
1623 if (!block->source) // hack block?
1624 continue;
1625 invalidate_block(block);
1626 }
1627 }
1628
57871462 1629 #ifdef USE_MINI_HT
93c0345b 1630 memset(mini_ht, -1, sizeof(mini_ht));
57871462 1631 #endif
919981d0 1632 do_clear_cache();
57871462 1633}
1634
1635// Add an entry to jump_out after making a link
104df9d3 1636// src should point to code by emit_extjump()
b7ad2f2c 1637void ndrc_add_jump_out(u_int vaddr, void *src)
57871462 1638{
b7ad2f2c 1639 inv_debug("ndrc_add_jump_out: %p -> %x\n", src, vaddr);
1640 u_int page = get_page(vaddr);
1641 struct jump_info *ji;
1642
104df9d3 1643 stat_inc(stat_links);
b7ad2f2c 1644 check_extjump2(src);
1645 ji = jumps[page];
1646 if (ji == NULL) {
1647 ji = malloc(sizeof(*ji) + sizeof(ji->e[0]) * 16);
1648 ji->alloc = 16;
1649 ji->count = 0;
1650 }
1651 else if (ji->count >= ji->alloc) {
1652 ji->alloc += 16;
1653 ji = realloc(ji, sizeof(*ji) + sizeof(ji->e[0]) * ji->alloc);
1654 }
1655 jumps[page] = ji;
1656 ji->e[ji->count].target_vaddr = vaddr;
1657 ji->e[ji->count].stub = src;
1658 ji->count++;
57871462 1659}
1660
8062d65a 1661/* Register allocation */
1662
90f98e7c 1663static void alloc_set(struct regstat *cur, int reg, int hr)
1664{
1665 cur->regmap[hr] = reg;
1666 cur->dirty &= ~(1u << hr);
1667 cur->isconst &= ~(1u << hr);
1668 cur->noevict |= 1u << hr;
1669}
1670
1671static void evict_alloc_reg(struct regstat *cur, int i, int reg, int preferred_hr)
1672{
1673 u_char hsn[MAXREG+1];
1674 int j, r, hr;
1675 memset(hsn, 10, sizeof(hsn));
1676 lsn(hsn, i);
1677 //printf("hsn(%x): %d %d %d %d %d %d %d\n",start+i*4,hsn[cur->regmap[0]&63],hsn[cur->regmap[1]&63],hsn[cur->regmap[2]&63],hsn[cur->regmap[3]&63],hsn[cur->regmap[5]&63],hsn[cur->regmap[6]&63],hsn[cur->regmap[7]&63]);
1678 if(i>0) {
1679 // Don't evict the cycle count at entry points, otherwise the entry
1680 // stub will have to write it.
1681 if(dops[i].bt&&hsn[CCREG]>2) hsn[CCREG]=2;
1682 if (i>1 && hsn[CCREG] > 2 && dops[i-2].is_jump) hsn[CCREG]=2;
1683 for(j=10;j>=3;j--)
1684 {
1685 // Alloc preferred register if available
1686 if (!((cur->noevict >> preferred_hr) & 1)
1687 && hsn[cur->regmap[preferred_hr]] == j)
1688 {
1689 alloc_set(cur, reg, preferred_hr);
1690 return;
1691 }
1692 for(r=1;r<=MAXREG;r++)
1693 {
1694 if(hsn[r]==j&&r!=dops[i-1].rs1&&r!=dops[i-1].rs2&&r!=dops[i-1].rt1&&r!=dops[i-1].rt2) {
1695 for(hr=0;hr<HOST_REGS;hr++) {
1696 if (hr == EXCLUDE_REG || ((cur->noevict >> hr) & 1))
1697 continue;
1698 if(hr!=HOST_CCREG||j<hsn[CCREG]) {
1699 if(cur->regmap[hr]==r) {
1700 alloc_set(cur, reg, hr);
1701 return;
1702 }
1703 }
1704 }
1705 }
1706 }
1707 }
1708 }
1709 for(j=10;j>=0;j--)
1710 {
1711 for(r=1;r<=MAXREG;r++)
1712 {
1713 if(hsn[r]==j) {
1714 for(hr=0;hr<HOST_REGS;hr++) {
1715 if (hr == EXCLUDE_REG || ((cur->noevict >> hr) & 1))
1716 continue;
1717 if(cur->regmap[hr]==r) {
1718 alloc_set(cur, reg, hr);
1719 return;
1720 }
1721 }
1722 }
1723 }
1724 }
1725 SysPrintf("This shouldn't happen (evict_alloc_reg)\n");
1726 abort();
1727}
1728
8062d65a 1729// Note: registers are allocated clean (unmodified state)
1730// if you intend to modify the register, you must call dirty_reg().
1731static void alloc_reg(struct regstat *cur,int i,signed char reg)
1732{
1733 int r,hr;
b7ec323c 1734 int preferred_reg = PREFERRED_REG_FIRST
1735 + reg % (PREFERRED_REG_LAST - PREFERRED_REG_FIRST + 1);
1736 if (reg == CCREG) preferred_reg = HOST_CCREG;
1737 if (reg == PTEMP || reg == FTEMP) preferred_reg = 12;
1738 assert(PREFERRED_REG_FIRST != EXCLUDE_REG && EXCLUDE_REG != HOST_REGS);
53358c1d 1739 assert(reg >= 0);
8062d65a 1740
1741 // Don't allocate unused registers
1742 if((cur->u>>reg)&1) return;
1743
1744 // see if it's already allocated
90f98e7c 1745 if ((hr = get_reg(cur->regmap, reg)) >= 0) {
1746 cur->noevict |= 1u << hr;
53358c1d 1747 return;
90f98e7c 1748 }
8062d65a 1749
1750 // Keep the same mapping if the register was already allocated in a loop
1751 preferred_reg = loop_reg(i,reg,preferred_reg);
1752
1753 // Try to allocate the preferred register
90f98e7c 1754 if (cur->regmap[preferred_reg] == -1) {
1755 alloc_set(cur, reg, preferred_reg);
8062d65a 1756 return;
1757 }
1758 r=cur->regmap[preferred_reg];
1759 assert(r < 64);
1760 if((cur->u>>r)&1) {
90f98e7c 1761 alloc_set(cur, reg, preferred_reg);
8062d65a 1762 return;
1763 }
1764
1765 // Clear any unneeded registers
1766 // We try to keep the mapping consistent, if possible, because it
1767 // makes branches easier (especially loops). So we try to allocate
1768 // first (see above) before removing old mappings. If this is not
1769 // possible then go ahead and clear out the registers that are no
1770 // longer needed.
1771 for(hr=0;hr<HOST_REGS;hr++)
1772 {
1773 r=cur->regmap[hr];
1774 if(r>=0) {
1775 assert(r < 64);
1776 if((cur->u>>r)&1) {cur->regmap[hr]=-1;break;}
1777 }
1778 }
b7ec323c 1779
8062d65a 1780 // Try to allocate any available register, but prefer
1781 // registers that have not been used recently.
b7ec323c 1782 if (i > 0) {
1783 for (hr = PREFERRED_REG_FIRST; ; ) {
1784 if (cur->regmap[hr] < 0) {
1785 int oldreg = regs[i-1].regmap[hr];
1786 if (oldreg < 0 || (oldreg != dops[i-1].rs1 && oldreg != dops[i-1].rs2
1787 && oldreg != dops[i-1].rt1 && oldreg != dops[i-1].rt2))
1788 {
90f98e7c 1789 alloc_set(cur, reg, hr);
8062d65a 1790 return;
1791 }
1792 }
b7ec323c 1793 hr++;
1794 if (hr == EXCLUDE_REG)
1795 hr++;
1796 if (hr == HOST_REGS)
1797 hr = 0;
1798 if (hr == PREFERRED_REG_FIRST)
1799 break;
8062d65a 1800 }
1801 }
b7ec323c 1802
8062d65a 1803 // Try to allocate any available register
b7ec323c 1804 for (hr = PREFERRED_REG_FIRST; ; ) {
1805 if (cur->regmap[hr] < 0) {
90f98e7c 1806 alloc_set(cur, reg, hr);
8062d65a 1807 return;
1808 }
b7ec323c 1809 hr++;
1810 if (hr == EXCLUDE_REG)
1811 hr++;
1812 if (hr == HOST_REGS)
1813 hr = 0;
1814 if (hr == PREFERRED_REG_FIRST)
1815 break;
8062d65a 1816 }
1817
1818 // Ok, now we have to evict someone
1819 // Pick a register we hopefully won't need soon
90f98e7c 1820 evict_alloc_reg(cur, i, reg, preferred_reg);
8062d65a 1821}
1822
1823// Allocate a temporary register. This is done without regard to
1824// dirty status or whether the register we request is on the unneeded list
1825// Note: This will only allocate one register, even if called multiple times
1826static void alloc_reg_temp(struct regstat *cur,int i,signed char reg)
1827{
1828 int r,hr;
8062d65a 1829
1830 // see if it's already allocated
90f98e7c 1831 for (hr = 0; hr < HOST_REGS; hr++)
8062d65a 1832 {
90f98e7c 1833 if (hr != EXCLUDE_REG && cur->regmap[hr] == reg) {
1834 cur->noevict |= 1u << hr;
1835 return;
1836 }
8062d65a 1837 }
1838
1839 // Try to allocate any available register
1840 for(hr=HOST_REGS-1;hr>=0;hr--) {
1841 if(hr!=EXCLUDE_REG&&cur->regmap[hr]==-1) {
90f98e7c 1842 alloc_set(cur, reg, hr);
8062d65a 1843 return;
1844 }
1845 }
1846
1847 // Find an unneeded register
1848 for(hr=HOST_REGS-1;hr>=0;hr--)
1849 {
1850 r=cur->regmap[hr];
1851 if(r>=0) {
1852 assert(r < 64);
1853 if((cur->u>>r)&1) {
1854 if(i==0||((unneeded_reg[i-1]>>r)&1)) {
90f98e7c 1855 alloc_set(cur, reg, hr);
8062d65a 1856 return;
1857 }
1858 }
1859 }
1860 }
1861
1862 // Ok, now we have to evict someone
1863 // Pick a register we hopefully won't need soon
90f98e7c 1864 evict_alloc_reg(cur, i, reg, 0);
8062d65a 1865}
1866
ad49de89 1867static void mov_alloc(struct regstat *current,int i)
57871462 1868{
cf95b4f0 1869 if (dops[i].rs1 == HIREG || dops[i].rs1 == LOREG) {
9a3ccfeb 1870 alloc_cc(current,i); // for stalls
1871 dirty_reg(current,CCREG);
32631e6a 1872 }
1873
57871462 1874 // Note: Don't need to actually alloc the source registers
cf95b4f0 1875 //alloc_reg(current,i,dops[i].rs1);
1876 alloc_reg(current,i,dops[i].rt1);
ad49de89 1877
cf95b4f0 1878 clear_const(current,dops[i].rs1);
1879 clear_const(current,dops[i].rt1);
1880 dirty_reg(current,dops[i].rt1);
57871462 1881}
1882
ad49de89 1883static void shiftimm_alloc(struct regstat *current,int i)
57871462 1884{
cf95b4f0 1885 if(dops[i].opcode2<=0x3) // SLL/SRL/SRA
57871462 1886 {
cf95b4f0 1887 if(dops[i].rt1) {
1888 if(dops[i].rs1&&needed_again(dops[i].rs1,i)) alloc_reg(current,i,dops[i].rs1);
53dc27f6 1889 else dops[i].use_lt1=!!dops[i].rs1;
cf95b4f0 1890 alloc_reg(current,i,dops[i].rt1);
1891 dirty_reg(current,dops[i].rt1);
1892 if(is_const(current,dops[i].rs1)) {
1893 int v=get_const(current,dops[i].rs1);
277718fa 1894 if(dops[i].opcode2==0x00) set_const(current,dops[i].rt1,v<<cinfo[i].imm);
1895 if(dops[i].opcode2==0x02) set_const(current,dops[i].rt1,(u_int)v>>cinfo[i].imm);
1896 if(dops[i].opcode2==0x03) set_const(current,dops[i].rt1,v>>cinfo[i].imm);
dc49e339 1897 }
cf95b4f0 1898 else clear_const(current,dops[i].rt1);
57871462 1899 }
1900 }
dc49e339 1901 else
1902 {
cf95b4f0 1903 clear_const(current,dops[i].rs1);
1904 clear_const(current,dops[i].rt1);
dc49e339 1905 }
1906
cf95b4f0 1907 if(dops[i].opcode2>=0x38&&dops[i].opcode2<=0x3b) // DSLL/DSRL/DSRA
57871462 1908 {
9c45ca93 1909 assert(0);
57871462 1910 }
cf95b4f0 1911 if(dops[i].opcode2==0x3c) // DSLL32
57871462 1912 {
9c45ca93 1913 assert(0);
57871462 1914 }
cf95b4f0 1915 if(dops[i].opcode2==0x3e) // DSRL32
57871462 1916 {
9c45ca93 1917 assert(0);
57871462 1918 }
cf95b4f0 1919 if(dops[i].opcode2==0x3f) // DSRA32
57871462 1920 {
9c45ca93 1921 assert(0);
57871462 1922 }
1923}
1924
ad49de89 1925static void shift_alloc(struct regstat *current,int i)
57871462 1926{
cf95b4f0 1927 if(dops[i].rt1) {
cf95b4f0 1928 if(dops[i].rs1) alloc_reg(current,i,dops[i].rs1);
1929 if(dops[i].rs2) alloc_reg(current,i,dops[i].rs2);
1930 alloc_reg(current,i,dops[i].rt1);
1931 if(dops[i].rt1==dops[i].rs2) {
e1190b87 1932 alloc_reg_temp(current,i,-1);
277718fa 1933 cinfo[i].min_free_regs=1;
e1190b87 1934 }
cf95b4f0 1935 clear_const(current,dops[i].rs1);
1936 clear_const(current,dops[i].rs2);
1937 clear_const(current,dops[i].rt1);
1938 dirty_reg(current,dops[i].rt1);
57871462 1939 }
1940}
1941
ad49de89 1942static void alu_alloc(struct regstat *current,int i)
57871462 1943{
cf95b4f0 1944 if(dops[i].opcode2>=0x20&&dops[i].opcode2<=0x23) { // ADD/ADDU/SUB/SUBU
1945 if(dops[i].rt1) {
1946 if(dops[i].rs1&&dops[i].rs2) {
1947 alloc_reg(current,i,dops[i].rs1);
1948 alloc_reg(current,i,dops[i].rs2);
57871462 1949 }
1950 else {
cf95b4f0 1951 if(dops[i].rs1&&needed_again(dops[i].rs1,i)) alloc_reg(current,i,dops[i].rs1);
1952 if(dops[i].rs2&&needed_again(dops[i].rs2,i)) alloc_reg(current,i,dops[i].rs2);
57871462 1953 }
cf95b4f0 1954 alloc_reg(current,i,dops[i].rt1);
57871462 1955 }
277718fa 1956 if (dops[i].may_except) {
90f98e7c 1957 alloc_cc_optional(current, i); // for exceptions
277718fa 1958 alloc_reg_temp(current, i, -1);
1959 cinfo[i].min_free_regs = 1;
a5cd72d0 1960 }
57871462 1961 }
277718fa 1962 else if(dops[i].opcode2==0x2a||dops[i].opcode2==0x2b) { // SLT/SLTU
cf95b4f0 1963 if(dops[i].rt1) {
1964 alloc_reg(current,i,dops[i].rs1);
1965 alloc_reg(current,i,dops[i].rs2);
1966 alloc_reg(current,i,dops[i].rt1);
57871462 1967 }
57871462 1968 }
277718fa 1969 else if(dops[i].opcode2>=0x24&&dops[i].opcode2<=0x27) { // AND/OR/XOR/NOR
cf95b4f0 1970 if(dops[i].rt1) {
1971 if(dops[i].rs1&&dops[i].rs2) {
1972 alloc_reg(current,i,dops[i].rs1);
1973 alloc_reg(current,i,dops[i].rs2);
57871462 1974 }
1975 else
1976 {
cf95b4f0 1977 if(dops[i].rs1&&needed_again(dops[i].rs1,i)) alloc_reg(current,i,dops[i].rs1);
1978 if(dops[i].rs2&&needed_again(dops[i].rs2,i)) alloc_reg(current,i,dops[i].rs2);
57871462 1979 }
cf95b4f0 1980 alloc_reg(current,i,dops[i].rt1);
57871462 1981 }
1982 }
cf95b4f0 1983 clear_const(current,dops[i].rs1);
1984 clear_const(current,dops[i].rs2);
1985 clear_const(current,dops[i].rt1);
1986 dirty_reg(current,dops[i].rt1);
57871462 1987}
1988
ad49de89 1989static void imm16_alloc(struct regstat *current,int i)
57871462 1990{
cf95b4f0 1991 if(dops[i].rs1&&needed_again(dops[i].rs1,i)) alloc_reg(current,i,dops[i].rs1);
53dc27f6 1992 else dops[i].use_lt1=!!dops[i].rs1;
cf95b4f0 1993 if(dops[i].rt1) alloc_reg(current,i,dops[i].rt1);
a5cd72d0 1994 if(dops[i].opcode==0x0a||dops[i].opcode==0x0b) { // SLTI/SLTIU
cf95b4f0 1995 clear_const(current,dops[i].rs1);
1996 clear_const(current,dops[i].rt1);
57871462 1997 }
cf95b4f0 1998 else if(dops[i].opcode>=0x0c&&dops[i].opcode<=0x0e) { // ANDI/ORI/XORI
1999 if(is_const(current,dops[i].rs1)) {
2000 int v=get_const(current,dops[i].rs1);
277718fa 2001 if(dops[i].opcode==0x0c) set_const(current,dops[i].rt1,v&cinfo[i].imm);
2002 if(dops[i].opcode==0x0d) set_const(current,dops[i].rt1,v|cinfo[i].imm);
2003 if(dops[i].opcode==0x0e) set_const(current,dops[i].rt1,v^cinfo[i].imm);
57871462 2004 }
cf95b4f0 2005 else clear_const(current,dops[i].rt1);
57871462 2006 }
cf95b4f0 2007 else if(dops[i].opcode==0x08||dops[i].opcode==0x09) { // ADDI/ADDIU
2008 if(is_const(current,dops[i].rs1)) {
2009 int v=get_const(current,dops[i].rs1);
277718fa 2010 set_const(current,dops[i].rt1,v+cinfo[i].imm);
57871462 2011 }
cf95b4f0 2012 else clear_const(current,dops[i].rt1);
277718fa 2013 if (dops[i].may_except) {
90f98e7c 2014 alloc_cc_optional(current, i); // for exceptions
277718fa 2015 alloc_reg_temp(current, i, -1);
2016 cinfo[i].min_free_regs = 1;
a5cd72d0 2017 }
57871462 2018 }
2019 else {
277718fa 2020 set_const(current,dops[i].rt1,cinfo[i].imm<<16); // LUI
57871462 2021 }
cf95b4f0 2022 dirty_reg(current,dops[i].rt1);
57871462 2023}
2024
ad49de89 2025static void load_alloc(struct regstat *current,int i)
57871462 2026{
277718fa 2027 int need_temp = 0;
cf95b4f0 2028 clear_const(current,dops[i].rt1);
2029 //if(dops[i].rs1!=dops[i].rt1&&needed_again(dops[i].rs1,i)) clear_const(current,dops[i].rs1); // Does this help or hurt?
2030 if(!dops[i].rs1) current->u&=~1LL; // Allow allocating r0 if it's the source register
37387d8b 2031 if (needed_again(dops[i].rs1, i))
2032 alloc_reg(current, i, dops[i].rs1);
2033 if (ram_offset)
2034 alloc_reg(current, i, ROREG);
277718fa 2035 if (dops[i].may_except) {
90f98e7c 2036 alloc_cc_optional(current, i); // for exceptions
277718fa 2037 need_temp = 1;
2038 }
cf95b4f0 2039 if(dops[i].rt1&&!((current->u>>dops[i].rt1)&1)) {
2040 alloc_reg(current,i,dops[i].rt1);
a5cd72d0 2041 assert(get_reg_w(current->regmap, dops[i].rt1)>=0);
cf95b4f0 2042 dirty_reg(current,dops[i].rt1);
57871462 2043 // LWL/LWR need a temporary register for the old value
cf95b4f0 2044 if(dops[i].opcode==0x22||dops[i].opcode==0x26)
57871462 2045 {
2046 alloc_reg(current,i,FTEMP);
277718fa 2047 need_temp = 1;
57871462 2048 }
2049 }
2050 else
2051 {
373d1d07 2052 // Load to r0 or unneeded register (dummy load)
57871462 2053 // but we still need a register to calculate the address
cf95b4f0 2054 if(dops[i].opcode==0x22||dops[i].opcode==0x26)
535d208a 2055 alloc_reg(current,i,FTEMP); // LWL/LWR need another temporary
277718fa 2056 need_temp = 1;
2057 }
2058 if (need_temp) {
2059 alloc_reg_temp(current, i, -1);
2060 cinfo[i].min_free_regs = 1;
57871462 2061 }
2062}
2063
90f98e7c 2064// this may eat up to 7 registers
2065static void store_alloc(struct regstat *current, int i)
57871462 2066{
cf95b4f0 2067 clear_const(current,dops[i].rs2);
2068 if(!(dops[i].rs2)) current->u&=~1LL; // Allow allocating r0 if necessary
2069 if(needed_again(dops[i].rs1,i)) alloc_reg(current,i,dops[i].rs1);
2070 alloc_reg(current,i,dops[i].rs2);
37387d8b 2071 if (ram_offset)
2072 alloc_reg(current, i, ROREG);
57871462 2073 #if defined(HOST_IMM8)
2074 // On CPUs without 32-bit immediates we need a pointer to invalid_code
37387d8b 2075 alloc_reg(current, i, INVCP);
57871462 2076 #endif
277718fa 2077 if (dops[i].opcode == 0x2a || dops[i].opcode == 0x2e) { // SWL/SWL
57871462 2078 alloc_reg(current,i,FTEMP);
2079 }
90f98e7c 2080 if (dops[i].may_except)
2081 alloc_cc_optional(current, i); // for exceptions
57871462 2082 // We need a temporary register for address generation
2083 alloc_reg_temp(current,i,-1);
277718fa 2084 cinfo[i].min_free_regs=1;
57871462 2085}
2086
90f98e7c 2087static void c2ls_alloc(struct regstat *current, int i)
b9b61529 2088{
cf95b4f0 2089 clear_const(current,dops[i].rt1);
2090 if(needed_again(dops[i].rs1,i)) alloc_reg(current,i,dops[i].rs1);
b9b61529 2091 alloc_reg(current,i,FTEMP);
37387d8b 2092 if (ram_offset)
2093 alloc_reg(current, i, ROREG);
b9b61529 2094 #if defined(HOST_IMM8)
2095 // On CPUs without 32-bit immediates we need a pointer to invalid_code
37387d8b 2096 if (dops[i].opcode == 0x3a) // SWC2
b9b61529 2097 alloc_reg(current,i,INVCP);
2098 #endif
90f98e7c 2099 if (dops[i].may_except)
2100 alloc_cc_optional(current, i); // for exceptions
b9b61529 2101 // We need a temporary register for address generation
2102 alloc_reg_temp(current,i,-1);
277718fa 2103 cinfo[i].min_free_regs=1;
b9b61529 2104}
2105
57871462 2106#ifndef multdiv_alloc
4149788d 2107static void multdiv_alloc(struct regstat *current,int i)
57871462 2108{
2109 // case 0x18: MULT
2110 // case 0x19: MULTU
2111 // case 0x1A: DIV
2112 // case 0x1B: DIVU
cf95b4f0 2113 clear_const(current,dops[i].rs1);
2114 clear_const(current,dops[i].rs2);
32631e6a 2115 alloc_cc(current,i); // for stalls
90f98e7c 2116 dirty_reg(current,CCREG);
cf95b4f0 2117 if(dops[i].rs1&&dops[i].rs2)
57871462 2118 {
57871462 2119 current->u&=~(1LL<<HIREG);
2120 current->u&=~(1LL<<LOREG);
2121 alloc_reg(current,i,HIREG);
2122 alloc_reg(current,i,LOREG);
cf95b4f0 2123 alloc_reg(current,i,dops[i].rs1);
2124 alloc_reg(current,i,dops[i].rs2);
57871462 2125 dirty_reg(current,HIREG);
2126 dirty_reg(current,LOREG);
57871462 2127 }
2128 else
2129 {
2130 // Multiply by zero is zero.
2131 // MIPS does not have a divide by zero exception.
57871462 2132 alloc_reg(current,i,HIREG);
2133 alloc_reg(current,i,LOREG);
57871462 2134 dirty_reg(current,HIREG);
2135 dirty_reg(current,LOREG);
de6dbc52 2136 if (dops[i].rs1 && ((dops[i].opcode2 & 0x3e) == 0x1a)) // div(u) 0
2137 alloc_reg(current, i, dops[i].rs1);
57871462 2138 }
2139}
2140#endif
2141
4149788d 2142static void cop0_alloc(struct regstat *current,int i)
57871462 2143{
cf95b4f0 2144 if(dops[i].opcode2==0) // MFC0
57871462 2145 {
cf95b4f0 2146 if(dops[i].rt1) {
2147 clear_const(current,dops[i].rt1);
cf95b4f0 2148 alloc_reg(current,i,dops[i].rt1);
2149 dirty_reg(current,dops[i].rt1);
57871462 2150 }
2151 }
cf95b4f0 2152 else if(dops[i].opcode2==4) // MTC0
57871462 2153 {
de6dbc52 2154 if (((source[i]>>11)&0x1e) == 12) {
2155 alloc_cc(current, i);
2156 dirty_reg(current, CCREG);
2157 }
cf95b4f0 2158 if(dops[i].rs1){
2159 clear_const(current,dops[i].rs1);
2160 alloc_reg(current,i,dops[i].rs1);
57871462 2161 alloc_all(current,i);
2162 }
2163 else {
2164 alloc_all(current,i); // FIXME: Keep r0
2165 current->u&=~1LL;
2166 alloc_reg(current,i,0);
2167 }
277718fa 2168 cinfo[i].min_free_regs = HOST_REGS;
57871462 2169 }
a5cd72d0 2170}
2171
2172static void rfe_alloc(struct regstat *current, int i)
2173{
2174 alloc_all(current, i);
277718fa 2175 cinfo[i].min_free_regs = HOST_REGS;
57871462 2176}
2177
81dbbf4c 2178static void cop2_alloc(struct regstat *current,int i)
57871462 2179{
cf95b4f0 2180 if (dops[i].opcode2 < 3) // MFC2/CFC2
57871462 2181 {
81dbbf4c 2182 alloc_cc(current,i); // for stalls
2183 dirty_reg(current,CCREG);
cf95b4f0 2184 if(dops[i].rt1){
2185 clear_const(current,dops[i].rt1);
2186 alloc_reg(current,i,dops[i].rt1);
2187 dirty_reg(current,dops[i].rt1);
57871462 2188 }
57871462 2189 }
cf95b4f0 2190 else if (dops[i].opcode2 > 3) // MTC2/CTC2
57871462 2191 {
cf95b4f0 2192 if(dops[i].rs1){
2193 clear_const(current,dops[i].rs1);
2194 alloc_reg(current,i,dops[i].rs1);
57871462 2195 }
2196 else {
2197 current->u&=~1LL;
2198 alloc_reg(current,i,0);
57871462 2199 }
2200 }
81dbbf4c 2201 alloc_reg_temp(current,i,-1);
277718fa 2202 cinfo[i].min_free_regs=1;
57871462 2203}
00fa9369 2204
4149788d 2205static void c2op_alloc(struct regstat *current,int i)
b9b61529 2206{
81dbbf4c 2207 alloc_cc(current,i); // for stalls
2208 dirty_reg(current,CCREG);
b9b61529 2209 alloc_reg_temp(current,i,-1);
2210}
57871462 2211
4149788d 2212static void syscall_alloc(struct regstat *current,int i)
57871462 2213{
2214 alloc_cc(current,i);
2215 dirty_reg(current,CCREG);
2216 alloc_all(current,i);
277718fa 2217 cinfo[i].min_free_regs=HOST_REGS;
57871462 2218 current->isconst=0;
2219}
2220
4149788d 2221static void delayslot_alloc(struct regstat *current,int i)
57871462 2222{
cf95b4f0 2223 switch(dops[i].itype) {
57871462 2224 case UJUMP:
2225 case CJUMP:
2226 case SJUMP:
2227 case RJUMP:
57871462 2228 case SYSCALL:
7139f3c8 2229 case HLECALL:
57871462 2230 case IMM16:
2231 imm16_alloc(current,i);
2232 break;
2233 case LOAD:
2234 case LOADLR:
2235 load_alloc(current,i);
2236 break;
2237 case STORE:
2238 case STORELR:
2239 store_alloc(current,i);
2240 break;
2241 case ALU:
2242 alu_alloc(current,i);
2243 break;
2244 case SHIFT:
2245 shift_alloc(current,i);
2246 break;
2247 case MULTDIV:
2248 multdiv_alloc(current,i);
2249 break;
2250 case SHIFTIMM:
2251 shiftimm_alloc(current,i);
2252 break;
2253 case MOV:
2254 mov_alloc(current,i);
2255 break;
2256 case COP0:
2257 cop0_alloc(current,i);
2258 break;
a5cd72d0 2259 case RFE:
2260 rfe_alloc(current,i);
81dbbf4c 2261 break;
b9b61529 2262 case COP2:
81dbbf4c 2263 cop2_alloc(current,i);
57871462 2264 break;
b9b61529 2265 case C2LS:
2266 c2ls_alloc(current,i);
2267 break;
b9b61529 2268 case C2OP:
2269 c2op_alloc(current,i);
2270 break;
57871462 2271 }
2272}
2273
b14b6a8f 2274static void add_stub(enum stub_type type, void *addr, void *retaddr,
2275 u_int a, uintptr_t b, uintptr_t c, u_int d, u_int e)
2276{
d1e4ebd9 2277 assert(stubcount < ARRAY_SIZE(stubs));
b14b6a8f 2278 stubs[stubcount].type = type;
2279 stubs[stubcount].addr = addr;
2280 stubs[stubcount].retaddr = retaddr;
2281 stubs[stubcount].a = a;
2282 stubs[stubcount].b = b;
2283 stubs[stubcount].c = c;
2284 stubs[stubcount].d = d;
2285 stubs[stubcount].e = e;
57871462 2286 stubcount++;
2287}
2288
b14b6a8f 2289static void add_stub_r(enum stub_type type, void *addr, void *retaddr,
81dbbf4c 2290 int i, int addr_reg, const struct regstat *i_regs, int ccadj, u_int reglist)
b14b6a8f 2291{
2292 add_stub(type, addr, retaddr, i, addr_reg, (uintptr_t)i_regs, ccadj, reglist);
2293}
2294
57871462 2295// Write out a single register
a22ccd6a 2296static void wb_register(signed char r, const signed char regmap[], u_int dirty)
57871462 2297{
2298 int hr;
2299 for(hr=0;hr<HOST_REGS;hr++) {
2300 if(hr!=EXCLUDE_REG) {
9de8a0c3 2301 if(regmap[hr]==r) {
57871462 2302 if((dirty>>hr)&1) {
ad49de89 2303 assert(regmap[hr]<64);
2304 emit_storereg(r,hr);
57871462 2305 }
a22ccd6a 2306 break;
57871462 2307 }
2308 }
2309 }
2310}
2311
8062d65a 2312static void wb_valid(signed char pre[],signed char entry[],u_int dirty_pre,u_int dirty,uint64_t u)
2313{
2314 //if(dirty_pre==dirty) return;
53358c1d 2315 int hr, r;
2316 for (hr = 0; hr < HOST_REGS; hr++) {
2317 r = pre[hr];
2318 if (r < 1 || r > 33 || ((u >> r) & 1))
2319 continue;
2320 if (((dirty_pre & ~dirty) >> hr) & 1)
2321 emit_storereg(r, hr);
8062d65a 2322 }
2323}
2324
687b4580 2325// trashes r2
2326static void pass_args(int a0, int a1)
2327{
2328 if(a0==1&&a1==0) {
2329 // must swap
2330 emit_mov(a0,2); emit_mov(a1,1); emit_mov(2,0);
2331 }
2332 else if(a0!=0&&a1==0) {
2333 emit_mov(a1,1);
2334 if (a0>=0) emit_mov(a0,0);
2335 }
2336 else {
2337 if(a0>=0&&a0!=0) emit_mov(a0,0);
2338 if(a1>=0&&a1!=1) emit_mov(a1,1);
2339 }
2340}
2341
a5cd72d0 2342static void alu_assemble(int i, const struct regstat *i_regs, int ccadj_)
57871462 2343{
cf95b4f0 2344 if(dops[i].opcode2>=0x20&&dops[i].opcode2<=0x23) { // ADD/ADDU/SUB/SUBU
a5cd72d0 2345 int do_oflow = dops[i].may_except; // ADD/SUB with exceptions enabled
2346 if (dops[i].rt1 || do_oflow) {
2347 int do_exception_check = 0;
2348 signed char s1, s2, t, tmp;
2349 t = get_reg_w(i_regs->regmap, dops[i].rt1);
2350 tmp = get_reg_temp(i_regs->regmap);
277718fa 2351 if (do_oflow)
2352 assert(tmp >= 0);
90f98e7c 2353 if (t < 0 && do_oflow)
2354 t = tmp;
a5cd72d0 2355 if (t >= 0) {
2356 s1 = get_reg(i_regs->regmap, dops[i].rs1);
2357 s2 = get_reg(i_regs->regmap, dops[i].rs2);
2358 if (dops[i].rs1 && dops[i].rs2) {
57871462 2359 assert(s1>=0);
2360 assert(s2>=0);
a5cd72d0 2361 if (dops[i].opcode2 & 2) {
2362 if (do_oflow) {
2363 emit_subs(s1, s2, tmp);
2364 do_exception_check = 1;
2365 }
2366 else
2367 emit_sub(s1,s2,t);
2368 }
2369 else {
2370 if (do_oflow) {
2371 emit_adds(s1, s2, tmp);
2372 do_exception_check = 1;
2373 }
2374 else
2375 emit_add(s1,s2,t);
2376 }
57871462 2377 }
cf95b4f0 2378 else if(dops[i].rs1) {
57871462 2379 if(s1>=0) emit_mov(s1,t);
cf95b4f0 2380 else emit_loadreg(dops[i].rs1,t);
57871462 2381 }
cf95b4f0 2382 else if(dops[i].rs2) {
a5cd72d0 2383 if (s2 < 0) {
2384 emit_loadreg(dops[i].rs2, t);
2385 s2 = t;
57871462 2386 }
a5cd72d0 2387 if (dops[i].opcode2 & 2) {
2388 if (do_oflow) {
2389 emit_negs(s2, tmp);
2390 do_exception_check = 1;
2391 }
2392 else
2393 emit_neg(s2, t);
57871462 2394 }
a5cd72d0 2395 else if (s2 != t)
2396 emit_mov(s2, t);
57871462 2397 }
a5cd72d0 2398 else
2399 emit_zeroreg(t);
2400 }
2401 if (do_exception_check) {
2402 void *jaddr = out;
2403 emit_jo(0);
2404 if (t >= 0 && tmp != t)
2405 emit_mov(tmp, t);
2406 add_stub_r(OVERFLOW_STUB, jaddr, out, i, 0, i_regs, ccadj_, 0);
57871462 2407 }
2408 }
2409 }
a5cd72d0 2410 else if(dops[i].opcode2==0x2a||dops[i].opcode2==0x2b) { // SLT/SLTU
cf95b4f0 2411 if(dops[i].rt1) {
ad49de89 2412 signed char s1l,s2l,t;
57871462 2413 {
a5cd72d0 2414 t=get_reg_w(i_regs->regmap, dops[i].rt1);
57871462 2415 //assert(t>=0);
2416 if(t>=0) {
cf95b4f0 2417 s1l=get_reg(i_regs->regmap,dops[i].rs1);
2418 s2l=get_reg(i_regs->regmap,dops[i].rs2);
2419 if(dops[i].rs2==0) // rx<r0
57871462 2420 {
cf95b4f0 2421 if(dops[i].opcode2==0x2a&&dops[i].rs1!=0) { // SLT
06e425d7 2422 assert(s1l>=0);
57871462 2423 emit_shrimm(s1l,31,t);
06e425d7 2424 }
2425 else // SLTU (unsigned can not be less than zero, 0<0)
57871462 2426 emit_zeroreg(t);
2427 }
cf95b4f0 2428 else if(dops[i].rs1==0) // r0<rx
57871462 2429 {
2430 assert(s2l>=0);
cf95b4f0 2431 if(dops[i].opcode2==0x2a) // SLT
57871462 2432 emit_set_gz32(s2l,t);
2433 else // SLTU (set if not zero)
2434 emit_set_nz32(s2l,t);
2435 }
2436 else{
2437 assert(s1l>=0);assert(s2l>=0);
cf95b4f0 2438 if(dops[i].opcode2==0x2a) // SLT
57871462 2439 emit_set_if_less32(s1l,s2l,t);
2440 else // SLTU
2441 emit_set_if_carry32(s1l,s2l,t);
2442 }
2443 }
2444 }
2445 }
2446 }
a5cd72d0 2447 else if(dops[i].opcode2>=0x24&&dops[i].opcode2<=0x27) { // AND/OR/XOR/NOR
cf95b4f0 2448 if(dops[i].rt1) {
ad49de89 2449 signed char s1l,s2l,tl;
a5cd72d0 2450 tl=get_reg_w(i_regs->regmap, dops[i].rt1);
57871462 2451 {
57871462 2452 if(tl>=0) {
cf95b4f0 2453 s1l=get_reg(i_regs->regmap,dops[i].rs1);
2454 s2l=get_reg(i_regs->regmap,dops[i].rs2);
2455 if(dops[i].rs1&&dops[i].rs2) {
57871462 2456 assert(s1l>=0);
2457 assert(s2l>=0);
cf95b4f0 2458 if(dops[i].opcode2==0x24) { // AND
57871462 2459 emit_and(s1l,s2l,tl);
2460 } else
cf95b4f0 2461 if(dops[i].opcode2==0x25) { // OR
57871462 2462 emit_or(s1l,s2l,tl);
2463 } else
cf95b4f0 2464 if(dops[i].opcode2==0x26) { // XOR
57871462 2465 emit_xor(s1l,s2l,tl);
2466 } else
cf95b4f0 2467 if(dops[i].opcode2==0x27) { // NOR
57871462 2468 emit_or(s1l,s2l,tl);
2469 emit_not(tl,tl);
2470 }
2471 }
2472 else
2473 {
cf95b4f0 2474 if(dops[i].opcode2==0x24) { // AND
57871462 2475 emit_zeroreg(tl);
2476 } else
cf95b4f0 2477 if(dops[i].opcode2==0x25||dops[i].opcode2==0x26) { // OR/XOR
2478 if(dops[i].rs1){
57871462 2479 if(s1l>=0) emit_mov(s1l,tl);
cf95b4f0 2480 else emit_loadreg(dops[i].rs1,tl); // CHECK: regmap_entry?
57871462 2481 }
2482 else
cf95b4f0 2483 if(dops[i].rs2){
57871462 2484 if(s2l>=0) emit_mov(s2l,tl);
cf95b4f0 2485 else emit_loadreg(dops[i].rs2,tl); // CHECK: regmap_entry?
57871462 2486 }
2487 else emit_zeroreg(tl);
2488 } else
cf95b4f0 2489 if(dops[i].opcode2==0x27) { // NOR
2490 if(dops[i].rs1){
57871462 2491 if(s1l>=0) emit_not(s1l,tl);
2492 else {
cf95b4f0 2493 emit_loadreg(dops[i].rs1,tl);
57871462 2494 emit_not(tl,tl);
2495 }
2496 }
2497 else
cf95b4f0 2498 if(dops[i].rs2){
57871462 2499 if(s2l>=0) emit_not(s2l,tl);
2500 else {
cf95b4f0 2501 emit_loadreg(dops[i].rs2,tl);
57871462 2502 emit_not(tl,tl);
2503 }
2504 }
2505 else emit_movimm(-1,tl);
2506 }
2507 }
2508 }
2509 }
2510 }
2511 }
2512}
2513
a5cd72d0 2514static void imm16_assemble(int i, const struct regstat *i_regs, int ccadj_)
57871462 2515{
cf95b4f0 2516 if (dops[i].opcode==0x0f) { // LUI
2517 if(dops[i].rt1) {
57871462 2518 signed char t;
a5cd72d0 2519 t=get_reg_w(i_regs->regmap, dops[i].rt1);
57871462 2520 //assert(t>=0);
2521 if(t>=0) {
2522 if(!((i_regs->isconst>>t)&1))
277718fa 2523 emit_movimm(cinfo[i].imm<<16,t);
57871462 2524 }
2525 }
2526 }
cf95b4f0 2527 if(dops[i].opcode==0x08||dops[i].opcode==0x09) { // ADDI/ADDIU
277718fa 2528 int is_addi = dops[i].may_except;
a5cd72d0 2529 if (dops[i].rt1 || is_addi) {
2530 signed char s, t, tmp;
2531 t=get_reg_w(i_regs->regmap, dops[i].rt1);
cf95b4f0 2532 s=get_reg(i_regs->regmap,dops[i].rs1);
2533 if(dops[i].rs1) {
a5cd72d0 2534 tmp = get_reg_temp(i_regs->regmap);
2535 if (is_addi) {
2536 assert(tmp >= 0);
2537 if (t < 0) t = tmp;
2538 }
57871462 2539 if(t>=0) {
2540 if(!((i_regs->isconst>>t)&1)) {
a5cd72d0 2541 int sum, do_exception_check = 0;
2542 if (s < 0) {
cf95b4f0 2543 if(i_regs->regmap_entry[t]!=dops[i].rs1) emit_loadreg(dops[i].rs1,t);
a5cd72d0 2544 if (is_addi) {
277718fa 2545 emit_addimm_and_set_flags3(t, cinfo[i].imm, tmp);
a5cd72d0 2546 do_exception_check = 1;
2547 }
57871462 2548 else
277718fa 2549 emit_addimm(t, cinfo[i].imm, t);
a5cd72d0 2550 } else {
2551 if (!((i_regs->wasconst >> s) & 1)) {
2552 if (is_addi) {
277718fa 2553 emit_addimm_and_set_flags3(s, cinfo[i].imm, tmp);
a5cd72d0 2554 do_exception_check = 1;
2555 }
2556 else
277718fa 2557 emit_addimm(s, cinfo[i].imm, t);
a5cd72d0 2558 }
2559 else {
277718fa 2560 int oflow = add_overflow(constmap[i][s], cinfo[i].imm, sum);
a5cd72d0 2561 if (is_addi && oflow)
2562 do_exception_check = 2;
2563 else
2564 emit_movimm(sum, t);
2565 }
2566 }
2567 if (do_exception_check) {
2568 void *jaddr = out;
2569 if (do_exception_check == 2)
2570 emit_jmp(0);
2571 else {
2572 emit_jo(0);
2573 if (tmp != t)
2574 emit_mov(tmp, t);
2575 }
2576 add_stub_r(OVERFLOW_STUB, jaddr, out, i, 0, i_regs, ccadj_, 0);
57871462 2577 }
2578 }
2579 }
2580 } else {
2581 if(t>=0) {
2582 if(!((i_regs->isconst>>t)&1))
277718fa 2583 emit_movimm(cinfo[i].imm,t);
57871462 2584 }
2585 }
2586 }
2587 }
cf95b4f0 2588 else if(dops[i].opcode==0x0a||dops[i].opcode==0x0b) { // SLTI/SLTIU
2589 if(dops[i].rt1) {
2590 //assert(dops[i].rs1!=0); // r0 might be valid, but it's probably a bug
ad49de89 2591 signed char sl,t;
a5cd72d0 2592 t=get_reg_w(i_regs->regmap, dops[i].rt1);
cf95b4f0 2593 sl=get_reg(i_regs->regmap,dops[i].rs1);
57871462 2594 //assert(t>=0);
2595 if(t>=0) {
cf95b4f0 2596 if(dops[i].rs1>0) {
2597 if(dops[i].opcode==0x0a) { // SLTI
57871462 2598 if(sl<0) {
cf95b4f0 2599 if(i_regs->regmap_entry[t]!=dops[i].rs1) emit_loadreg(dops[i].rs1,t);
277718fa 2600 emit_slti32(t,cinfo[i].imm,t);
57871462 2601 }else{
277718fa 2602 emit_slti32(sl,cinfo[i].imm,t);
57871462 2603 }
2604 }
2605 else { // SLTIU
2606 if(sl<0) {
cf95b4f0 2607 if(i_regs->regmap_entry[t]!=dops[i].rs1) emit_loadreg(dops[i].rs1,t);
277718fa 2608 emit_sltiu32(t,cinfo[i].imm,t);
57871462 2609 }else{
277718fa 2610 emit_sltiu32(sl,cinfo[i].imm,t);
57871462 2611 }
2612 }
57871462 2613 }else{
2614 // SLTI(U) with r0 is just stupid,
2615 // nonetheless examples can be found
cf95b4f0 2616 if(dops[i].opcode==0x0a) // SLTI
277718fa 2617 if(0<cinfo[i].imm) emit_movimm(1,t);
57871462 2618 else emit_zeroreg(t);
2619 else // SLTIU
2620 {
277718fa 2621 if(cinfo[i].imm) emit_movimm(1,t);
57871462 2622 else emit_zeroreg(t);
2623 }
2624 }
2625 }
2626 }
2627 }
cf95b4f0 2628 else if(dops[i].opcode>=0x0c&&dops[i].opcode<=0x0e) { // ANDI/ORI/XORI
2629 if(dops[i].rt1) {
7c3a5182 2630 signed char sl,tl;
a5cd72d0 2631 tl=get_reg_w(i_regs->regmap, dops[i].rt1);
cf95b4f0 2632 sl=get_reg(i_regs->regmap,dops[i].rs1);
57871462 2633 if(tl>=0 && !((i_regs->isconst>>tl)&1)) {
cf95b4f0 2634 if(dops[i].opcode==0x0c) //ANDI
57871462 2635 {
cf95b4f0 2636 if(dops[i].rs1) {
57871462 2637 if(sl<0) {
cf95b4f0 2638 if(i_regs->regmap_entry[tl]!=dops[i].rs1) emit_loadreg(dops[i].rs1,tl);
277718fa 2639 emit_andimm(tl,cinfo[i].imm,tl);
57871462 2640 }else{
2641 if(!((i_regs->wasconst>>sl)&1))
277718fa 2642 emit_andimm(sl,cinfo[i].imm,tl);
57871462 2643 else
277718fa 2644 emit_movimm(constmap[i][sl]&cinfo[i].imm,tl);
57871462 2645 }
2646 }
2647 else
2648 emit_zeroreg(tl);
57871462 2649 }
2650 else
2651 {
cf95b4f0 2652 if(dops[i].rs1) {
57871462 2653 if(sl<0) {
cf95b4f0 2654 if(i_regs->regmap_entry[tl]!=dops[i].rs1) emit_loadreg(dops[i].rs1,tl);
57871462 2655 }
cf95b4f0 2656 if(dops[i].opcode==0x0d) { // ORI
581335b0 2657 if(sl<0) {
277718fa 2658 emit_orimm(tl,cinfo[i].imm,tl);
581335b0 2659 }else{
2660 if(!((i_regs->wasconst>>sl)&1))
277718fa 2661 emit_orimm(sl,cinfo[i].imm,tl);
581335b0 2662 else
277718fa 2663 emit_movimm(constmap[i][sl]|cinfo[i].imm,tl);
581335b0 2664 }
57871462 2665 }
cf95b4f0 2666 if(dops[i].opcode==0x0e) { // XORI
581335b0 2667 if(sl<0) {
277718fa 2668 emit_xorimm(tl,cinfo[i].imm,tl);
581335b0 2669 }else{
2670 if(!((i_regs->wasconst>>sl)&1))
277718fa 2671 emit_xorimm(sl,cinfo[i].imm,tl);
581335b0 2672 else
277718fa 2673 emit_movimm(constmap[i][sl]^cinfo[i].imm,tl);
581335b0 2674 }
57871462 2675 }
2676 }
2677 else {
277718fa 2678 emit_movimm(cinfo[i].imm,tl);
57871462 2679 }
2680 }
2681 }
2682 }
2683 }
2684}
2685
2330734f 2686static void shiftimm_assemble(int i, const struct regstat *i_regs)
57871462 2687{
cf95b4f0 2688 if(dops[i].opcode2<=0x3) // SLL/SRL/SRA
57871462 2689 {
cf95b4f0 2690 if(dops[i].rt1) {
57871462 2691 signed char s,t;
a5cd72d0 2692 t=get_reg_w(i_regs->regmap, dops[i].rt1);
cf95b4f0 2693 s=get_reg(i_regs->regmap,dops[i].rs1);
57871462 2694 //assert(t>=0);
dc49e339 2695 if(t>=0&&!((i_regs->isconst>>t)&1)){
cf95b4f0 2696 if(dops[i].rs1==0)
57871462 2697 {
2698 emit_zeroreg(t);
2699 }
2700 else
2701 {
cf95b4f0 2702 if(s<0&&i_regs->regmap_entry[t]!=dops[i].rs1) emit_loadreg(dops[i].rs1,t);
277718fa 2703 if(cinfo[i].imm) {
cf95b4f0 2704 if(dops[i].opcode2==0) // SLL
57871462 2705 {
277718fa 2706 emit_shlimm(s<0?t:s,cinfo[i].imm,t);
57871462 2707 }
cf95b4f0 2708 if(dops[i].opcode2==2) // SRL
57871462 2709 {
277718fa 2710 emit_shrimm(s<0?t:s,cinfo[i].imm,t);
57871462 2711 }
cf95b4f0 2712 if(dops[i].opcode2==3) // SRA
57871462 2713 {
277718fa 2714 emit_sarimm(s<0?t:s,cinfo[i].imm,t);
57871462 2715 }
2716 }else{
2717 // Shift by zero
2718 if(s>=0 && s!=t) emit_mov(s,t);
2719 }
2720 }
2721 }
cf95b4f0 2722 //emit_storereg(dops[i].rt1,t); //DEBUG
57871462 2723 }
2724 }
cf95b4f0 2725 if(dops[i].opcode2>=0x38&&dops[i].opcode2<=0x3b) // DSLL/DSRL/DSRA
57871462 2726 {
9c45ca93 2727 assert(0);
57871462 2728 }
cf95b4f0 2729 if(dops[i].opcode2==0x3c) // DSLL32
57871462 2730 {
9c45ca93 2731 assert(0);
57871462 2732 }
cf95b4f0 2733 if(dops[i].opcode2==0x3e) // DSRL32
57871462 2734 {
9c45ca93 2735 assert(0);
57871462 2736 }
cf95b4f0 2737 if(dops[i].opcode2==0x3f) // DSRA32
57871462 2738 {
9c45ca93 2739 assert(0);
57871462 2740 }
2741}
2742
2743#ifndef shift_assemble
2330734f 2744static void shift_assemble(int i, const struct regstat *i_regs)
57871462 2745{
3968e69e 2746 signed char s,t,shift;
cf95b4f0 2747 if (dops[i].rt1 == 0)
3968e69e 2748 return;
cf95b4f0 2749 assert(dops[i].opcode2<=0x07); // SLLV/SRLV/SRAV
2750 t = get_reg(i_regs->regmap, dops[i].rt1);
2751 s = get_reg(i_regs->regmap, dops[i].rs1);
2752 shift = get_reg(i_regs->regmap, dops[i].rs2);
3968e69e 2753 if (t < 0)
2754 return;
2755
cf95b4f0 2756 if(dops[i].rs1==0)
3968e69e 2757 emit_zeroreg(t);
cf95b4f0 2758 else if(dops[i].rs2==0) {
3968e69e 2759 assert(s>=0);
2760 if(s!=t) emit_mov(s,t);
2761 }
2762 else {
2763 host_tempreg_acquire();
2764 emit_andimm(shift,31,HOST_TEMPREG);
cf95b4f0 2765 switch(dops[i].opcode2) {
3968e69e 2766 case 4: // SLLV
2767 emit_shl(s,HOST_TEMPREG,t);
2768 break;
2769 case 6: // SRLV
2770 emit_shr(s,HOST_TEMPREG,t);
2771 break;
2772 case 7: // SRAV
2773 emit_sar(s,HOST_TEMPREG,t);
2774 break;
2775 default:
2776 assert(0);
2777 }
2778 host_tempreg_release();
2779 }
57871462 2780}
3968e69e 2781
57871462 2782#endif
2783
8062d65a 2784enum {
2785 MTYPE_8000 = 0,
2786 MTYPE_8020,
2787 MTYPE_0000,
2788 MTYPE_A000,
2789 MTYPE_1F80,
2790};
2791
2792static int get_ptr_mem_type(u_int a)
2793{
2794 if(a < 0x00200000) {
2795 if(a<0x1000&&((start>>20)==0xbfc||(start>>24)==0xa0))
2796 // return wrong, must use memhandler for BIOS self-test to pass
2797 // 007 does similar stuff from a00 mirror, weird stuff
2798 return MTYPE_8000;
2799 return MTYPE_0000;
2800 }
2801 if(0x1f800000 <= a && a < 0x1f801000)
2802 return MTYPE_1F80;
2803 if(0x80200000 <= a && a < 0x80800000)
2804 return MTYPE_8020;
2805 if(0xa0000000 <= a && a < 0xa0200000)
2806 return MTYPE_A000;
2807 return MTYPE_8000;
2808}
2809
37387d8b 2810static int get_ro_reg(const struct regstat *i_regs, int host_tempreg_free)
2811{
2812 int r = get_reg(i_regs->regmap, ROREG);
2813 if (r < 0 && host_tempreg_free) {
2814 host_tempreg_acquire();
2815 emit_loadreg(ROREG, r = HOST_TEMPREG);
2816 }
2817 if (r < 0)
2818 abort();
2819 return r;
2820}
2821
2822static void *emit_fastpath_cmp_jump(int i, const struct regstat *i_regs,
277718fa 2823 int addr, int *offset_reg, int *addr_reg_override, int ccadj_)
8062d65a 2824{
2825 void *jaddr = NULL;
37387d8b 2826 int type = 0;
2827 int mr = dops[i].rs1;
277718fa 2828 assert(addr >= 0);
37387d8b 2829 *offset_reg = -1;
8062d65a 2830 if(((smrv_strong|smrv_weak)>>mr)&1) {
2831 type=get_ptr_mem_type(smrv[mr]);
2832 //printf("set %08x @%08x r%d %d\n", smrv[mr], start+i*4, mr, type);
2833 }
2834 else {
2835 // use the mirror we are running on
2836 type=get_ptr_mem_type(start);
2837 //printf("set nospec @%08x r%d %d\n", start+i*4, mr, type);
2838 }
2839
277718fa 2840 if (dops[i].may_except) {
2841 // alignment check
2842 u_int op = dops[i].opcode;
2843 int mask = ((op & 0x37) == 0x21 || op == 0x25) ? 1 : 3; // LH/SH/LHU
33a1eda1 2844 void *jaddr2;
277718fa 2845 emit_testimm(addr, mask);
33a1eda1 2846 jaddr2 = out;
277718fa 2847 emit_jne(0);
33a1eda1 2848 add_stub_r(ALIGNMENT_STUB, jaddr2, out, i, addr, i_regs, ccadj_, 0);
277718fa 2849 }
2850
8062d65a 2851 if(type==MTYPE_8020) { // RAM 80200000+ mirror
d1e4ebd9 2852 host_tempreg_acquire();
8062d65a 2853 emit_andimm(addr,~0x00e00000,HOST_TEMPREG);
2854 addr=*addr_reg_override=HOST_TEMPREG;
2855 type=0;
2856 }
2857 else if(type==MTYPE_0000) { // RAM 0 mirror
d1e4ebd9 2858 host_tempreg_acquire();
8062d65a 2859 emit_orimm(addr,0x80000000,HOST_TEMPREG);
2860 addr=*addr_reg_override=HOST_TEMPREG;
2861 type=0;
2862 }
2863 else if(type==MTYPE_A000) { // RAM A mirror
d1e4ebd9 2864 host_tempreg_acquire();
8062d65a 2865 emit_andimm(addr,~0x20000000,HOST_TEMPREG);
2866 addr=*addr_reg_override=HOST_TEMPREG;
2867 type=0;
2868 }
2869 else if(type==MTYPE_1F80) { // scratchpad
2870 if (psxH == (void *)0x1f800000) {
d1e4ebd9 2871 host_tempreg_acquire();
3968e69e 2872 emit_xorimm(addr,0x1f800000,HOST_TEMPREG);
8062d65a 2873 emit_cmpimm(HOST_TEMPREG,0x1000);
d1e4ebd9 2874 host_tempreg_release();
8062d65a 2875 jaddr=out;
2876 emit_jc(0);
2877 }
2878 else {
2879 // do the usual RAM check, jump will go to the right handler
2880 type=0;
2881 }
2882 }
2883
37387d8b 2884 if (type == 0) // need ram check
8062d65a 2885 {
2886 emit_cmpimm(addr,RAM_SIZE);
37387d8b 2887 jaddr = out;
8062d65a 2888 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
2889 // Hint to branch predictor that the branch is unlikely to be taken
37387d8b 2890 if (dops[i].rs1 >= 28)
8062d65a 2891 emit_jno_unlikely(0);
2892 else
2893 #endif
2894 emit_jno(0);
37387d8b 2895 if (ram_offset != 0)
2896 *offset_reg = get_ro_reg(i_regs, 0);
8062d65a 2897 }
2898
2899 return jaddr;
2900}
2901
687b4580 2902// return memhandler, or get directly accessable address and return 0
2903static void *get_direct_memhandler(void *table, u_int addr,
2904 enum stub_type type, uintptr_t *addr_host)
2905{
c979e8c2 2906 uintptr_t msb = 1ull << (sizeof(uintptr_t)*8 - 1);
687b4580 2907 uintptr_t l1, l2 = 0;
2908 l1 = ((uintptr_t *)table)[addr>>12];
c979e8c2 2909 if (!(l1 & msb)) {
687b4580 2910 uintptr_t v = l1 << 1;
2911 *addr_host = v + addr;
2912 return NULL;
2913 }
2914 else {
2915 l1 <<= 1;
2916 if (type == LOADB_STUB || type == LOADBU_STUB || type == STOREB_STUB)
2917 l2 = ((uintptr_t *)l1)[0x1000/4 + 0x1000/2 + (addr&0xfff)];
2918 else if (type == LOADH_STUB || type == LOADHU_STUB || type == STOREH_STUB)
c979e8c2 2919 l2 = ((uintptr_t *)l1)[0x1000/4 + (addr&0xfff)/2];
687b4580 2920 else
c979e8c2 2921 l2 = ((uintptr_t *)l1)[(addr&0xfff)/4];
2922 if (!(l2 & msb)) {
687b4580 2923 uintptr_t v = l2 << 1;
2924 *addr_host = v + (addr&0xfff);
2925 return NULL;
2926 }
2927 return (void *)(l2 << 1);
2928 }
2929}
2930
81dbbf4c 2931static u_int get_host_reglist(const signed char *regmap)
2932{
2933 u_int reglist = 0, hr;
2934 for (hr = 0; hr < HOST_REGS; hr++) {
2935 if (hr != EXCLUDE_REG && regmap[hr] >= 0)
2936 reglist |= 1 << hr;
2937 }
2938 return reglist;
2939}
2940
2941static u_int reglist_exclude(u_int reglist, int r1, int r2)
2942{
2943 if (r1 >= 0)
2944 reglist &= ~(1u << r1);
2945 if (r2 >= 0)
2946 reglist &= ~(1u << r2);
2947 return reglist;
2948}
2949
e3c6bdb5 2950// find a temp caller-saved register not in reglist (so assumed to be free)
2951static int reglist_find_free(u_int reglist)
2952{
2953 u_int free_regs = ~reglist & CALLER_SAVE_REGS;
2954 if (free_regs == 0)
2955 return -1;
2956 return __builtin_ctz(free_regs);
2957}
2958
37387d8b 2959static void do_load_word(int a, int rt, int offset_reg)
2960{
2961 if (offset_reg >= 0)
2962 emit_ldr_dualindexed(offset_reg, a, rt);
2963 else
2964 emit_readword_indexed(0, a, rt);
2965}
2966
2967static void do_store_word(int a, int ofs, int rt, int offset_reg, int preseve_a)
2968{
2969 if (offset_reg < 0) {
2970 emit_writeword_indexed(rt, ofs, a);
2971 return;
2972 }
2973 if (ofs != 0)
2974 emit_addimm(a, ofs, a);
2975 emit_str_dualindexed(offset_reg, a, rt);
2976 if (ofs != 0 && preseve_a)
2977 emit_addimm(a, -ofs, a);
2978}
2979
2980static void do_store_hword(int a, int ofs, int rt, int offset_reg, int preseve_a)
2981{
2982 if (offset_reg < 0) {
2983 emit_writehword_indexed(rt, ofs, a);
2984 return;
2985 }
2986 if (ofs != 0)
2987 emit_addimm(a, ofs, a);
2988 emit_strh_dualindexed(offset_reg, a, rt);
2989 if (ofs != 0 && preseve_a)
2990 emit_addimm(a, -ofs, a);
2991}
2992
2993static void do_store_byte(int a, int rt, int offset_reg)
2994{
2995 if (offset_reg >= 0)
2996 emit_strb_dualindexed(offset_reg, a, rt);
2997 else
2998 emit_writebyte_indexed(rt, 0, a);
2999}
3000
2330734f 3001static void load_assemble(int i, const struct regstat *i_regs, int ccadj_)
57871462 3002{
277718fa 3003 int addr = cinfo[i].addr;
3004 int s,tl;
57871462 3005 int offset;
b14b6a8f 3006 void *jaddr=0;
5bf843dc 3007 int memtarget=0,c=0;
37387d8b 3008 int offset_reg = -1;
3009 int fastio_reg_override = -1;
81dbbf4c 3010 u_int reglist=get_host_reglist(i_regs->regmap);
a5cd72d0 3011 tl=get_reg_w(i_regs->regmap, dops[i].rt1);
cf95b4f0 3012 s=get_reg(i_regs->regmap,dops[i].rs1);
277718fa 3013 offset=cinfo[i].imm;
57871462 3014 if(i_regs->regmap[HOST_CCREG]==CCREG) reglist&=~(1<<HOST_CCREG);
3015 if(s>=0) {
3016 c=(i_regs->wasconst>>s)&1;
af4ee1fe 3017 if (c) {
3018 memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
af4ee1fe 3019 }
57871462 3020 }
57871462 3021 //printf("load_assemble: c=%d\n",c);
643aeae3 3022 //if(c) printf("load_assemble: const=%lx\n",(long)constmap[i][s]+offset);
a5cd72d0 3023 if(tl<0 && ((!c||(((u_int)constmap[i][s]+offset)>>16)==0x1f80) || dops[i].rt1==0)) {
5bf843dc 3024 // could be FIFO, must perform the read
f18c0f46 3025 // ||dummy read
5bf843dc 3026 assem_debug("(forced read)\n");
277718fa 3027 tl = get_reg_temp(i_regs->regmap); // may be == addr
5bf843dc 3028 assert(tl>=0);
5bf843dc 3029 }
277718fa 3030 assert(addr >= 0);
535d208a 3031 if(tl>=0) {
3032 //printf("load_assemble: c=%d\n",c);
643aeae3 3033 //if(c) printf("load_assemble: const=%lx\n",(long)constmap[i][s]+offset);
535d208a 3034 reglist&=~(1<<tl);
1edfcc68 3035 if(!c) {
1edfcc68 3036 #ifdef R29_HACK
3037 // Strmnnrmn's speed hack
cf95b4f0 3038 if(dops[i].rs1!=29||start<0x80001000||start>=0x80000000+RAM_SIZE)
1edfcc68 3039 #endif
3040 {
37387d8b 3041 jaddr = emit_fastpath_cmp_jump(i, i_regs, addr,
277718fa 3042 &offset_reg, &fastio_reg_override, ccadj_);
535d208a 3043 }
1edfcc68 3044 }
37387d8b 3045 else if (ram_offset && memtarget) {
3046 offset_reg = get_ro_reg(i_regs, 0);
535d208a 3047 }
a5cd72d0 3048 int dummy=(dops[i].rt1==0)||(tl!=get_reg_w(i_regs->regmap, dops[i].rt1)); // ignore loads to r0 and unneeded reg
37387d8b 3049 switch (dops[i].opcode) {
3050 case 0x20: // LB
535d208a 3051 if(!c||memtarget) {
3052 if(!dummy) {
277718fa 3053 int a = addr;
37387d8b 3054 if (fastio_reg_override >= 0)
3055 a = fastio_reg_override;
b1570849 3056
37387d8b 3057 if (offset_reg >= 0)
3058 emit_ldrsb_dualindexed(offset_reg, a, tl);
3059 else
3060 emit_movsbl_indexed(0, a, tl);
57871462 3061 }
535d208a 3062 if(jaddr)
2330734f 3063 add_stub_r(LOADB_STUB,jaddr,out,i,addr,i_regs,ccadj_,reglist);
57871462 3064 }
535d208a 3065 else
2330734f 3066 inline_readstub(LOADB_STUB,i,constmap[i][s]+offset,i_regs->regmap,dops[i].rt1,ccadj_,reglist);
37387d8b 3067 break;
3068 case 0x21: // LH
535d208a 3069 if(!c||memtarget) {
3070 if(!dummy) {
277718fa 3071 int a = addr;
37387d8b 3072 if (fastio_reg_override >= 0)
3073 a = fastio_reg_override;
3074 if (offset_reg >= 0)
3075 emit_ldrsh_dualindexed(offset_reg, a, tl);
3076 else
3077 emit_movswl_indexed(0, a, tl);
57871462 3078 }
535d208a 3079 if(jaddr)
2330734f 3080 add_stub_r(LOADH_STUB,jaddr,out,i,addr,i_regs,ccadj_,reglist);
57871462 3081 }
535d208a 3082 else
2330734f 3083 inline_readstub(LOADH_STUB,i,constmap[i][s]+offset,i_regs->regmap,dops[i].rt1,ccadj_,reglist);
37387d8b 3084 break;
3085 case 0x23: // LW
535d208a 3086 if(!c||memtarget) {
3087 if(!dummy) {
37387d8b 3088 int a = addr;
3089 if (fastio_reg_override >= 0)
3090 a = fastio_reg_override;
3091 do_load_word(a, tl, offset_reg);
57871462 3092 }
535d208a 3093 if(jaddr)
2330734f 3094 add_stub_r(LOADW_STUB,jaddr,out,i,addr,i_regs,ccadj_,reglist);
57871462 3095 }
535d208a 3096 else
2330734f 3097 inline_readstub(LOADW_STUB,i,constmap[i][s]+offset,i_regs->regmap,dops[i].rt1,ccadj_,reglist);
37387d8b 3098 break;
3099 case 0x24: // LBU
535d208a 3100 if(!c||memtarget) {
3101 if(!dummy) {
277718fa 3102 int a = addr;
37387d8b 3103 if (fastio_reg_override >= 0)
3104 a = fastio_reg_override;
b1570849 3105
37387d8b 3106 if (offset_reg >= 0)
3107 emit_ldrb_dualindexed(offset_reg, a, tl);
3108 else
3109 emit_movzbl_indexed(0, a, tl);
57871462 3110 }
535d208a 3111 if(jaddr)
2330734f 3112 add_stub_r(LOADBU_STUB,jaddr,out,i,addr,i_regs,ccadj_,reglist);
57871462 3113 }
535d208a 3114 else
2330734f 3115 inline_readstub(LOADBU_STUB,i,constmap[i][s]+offset,i_regs->regmap,dops[i].rt1,ccadj_,reglist);
37387d8b 3116 break;
3117 case 0x25: // LHU
535d208a 3118 if(!c||memtarget) {
3119 if(!dummy) {
277718fa 3120 int a = addr;
37387d8b 3121 if (fastio_reg_override >= 0)
3122 a = fastio_reg_override;
3123 if (offset_reg >= 0)
3124 emit_ldrh_dualindexed(offset_reg, a, tl);
3125 else
3126 emit_movzwl_indexed(0, a, tl);
57871462 3127 }
535d208a 3128 if(jaddr)
2330734f 3129 add_stub_r(LOADHU_STUB,jaddr,out,i,addr,i_regs,ccadj_,reglist);
57871462 3130 }
535d208a 3131 else
2330734f 3132 inline_readstub(LOADHU_STUB,i,constmap[i][s]+offset,i_regs->regmap,dops[i].rt1,ccadj_,reglist);
37387d8b 3133 break;
37387d8b 3134 default:
9c45ca93 3135 assert(0);
57871462 3136 }
a5cd72d0 3137 } // tl >= 0
37387d8b 3138 if (fastio_reg_override == HOST_TEMPREG || offset_reg == HOST_TEMPREG)
d1e4ebd9 3139 host_tempreg_release();
57871462 3140}
3141
3142#ifndef loadlr_assemble
2330734f 3143static void loadlr_assemble(int i, const struct regstat *i_regs, int ccadj_)
57871462 3144{
277718fa 3145 int addr = cinfo[i].addr;
3146 int s,tl,temp,temp2;
3968e69e 3147 int offset;
3148 void *jaddr=0;
3149 int memtarget=0,c=0;
37387d8b 3150 int offset_reg = -1;
3151 int fastio_reg_override = -1;
81dbbf4c 3152 u_int reglist=get_host_reglist(i_regs->regmap);
a5cd72d0 3153 tl=get_reg_w(i_regs->regmap, dops[i].rt1);
cf95b4f0 3154 s=get_reg(i_regs->regmap,dops[i].rs1);
9de8a0c3 3155 temp=get_reg_temp(i_regs->regmap);
3968e69e 3156 temp2=get_reg(i_regs->regmap,FTEMP);
277718fa 3157 offset=cinfo[i].imm;
3968e69e 3158 reglist|=1<<temp;
277718fa 3159 assert(addr >= 0);
3968e69e 3160 if(s>=0) {
3161 c=(i_regs->wasconst>>s)&1;
3162 if(c) {
3163 memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
3164 }
3165 }
3166 if(!c) {
3167 emit_shlimm(addr,3,temp);
cf95b4f0 3168 if (dops[i].opcode==0x22||dops[i].opcode==0x26) {
3968e69e 3169 emit_andimm(addr,0xFFFFFFFC,temp2); // LWL/LWR
3170 }else{
3171 emit_andimm(addr,0xFFFFFFF8,temp2); // LDL/LDR
3172 }
37387d8b 3173 jaddr = emit_fastpath_cmp_jump(i, i_regs, temp2,
277718fa 3174 &offset_reg, &fastio_reg_override, ccadj_);
3968e69e 3175 }
3176 else {
37387d8b 3177 if (ram_offset && memtarget) {
3178 offset_reg = get_ro_reg(i_regs, 0);
3968e69e 3179 }
cf95b4f0 3180 if (dops[i].opcode==0x22||dops[i].opcode==0x26) {
3968e69e 3181 emit_movimm(((constmap[i][s]+offset)<<3)&24,temp); // LWL/LWR
3182 }else{
3183 emit_movimm(((constmap[i][s]+offset)<<3)&56,temp); // LDL/LDR
3184 }
3185 }
cf95b4f0 3186 if (dops[i].opcode==0x22||dops[i].opcode==0x26) { // LWL/LWR
3968e69e 3187 if(!c||memtarget) {
37387d8b 3188 int a = temp2;
3189 if (fastio_reg_override >= 0)
3190 a = fastio_reg_override;
3191 do_load_word(a, temp2, offset_reg);
3192 if (fastio_reg_override == HOST_TEMPREG || offset_reg == HOST_TEMPREG)
3193 host_tempreg_release();
2330734f 3194 if(jaddr) add_stub_r(LOADW_STUB,jaddr,out,i,temp2,i_regs,ccadj_,reglist);
3968e69e 3195 }
3196 else
2330734f 3197 inline_readstub(LOADW_STUB,i,(constmap[i][s]+offset)&0xFFFFFFFC,i_regs->regmap,FTEMP,ccadj_,reglist);
cf95b4f0 3198 if(dops[i].rt1) {
3968e69e 3199 assert(tl>=0);
3200 emit_andimm(temp,24,temp);
cf95b4f0 3201 if (dops[i].opcode==0x22) // LWL
3968e69e 3202 emit_xorimm(temp,24,temp);
3203 host_tempreg_acquire();
3204 emit_movimm(-1,HOST_TEMPREG);
cf95b4f0 3205 if (dops[i].opcode==0x26) {
3968e69e 3206 emit_shr(temp2,temp,temp2);
3207 emit_bic_lsr(tl,HOST_TEMPREG,temp,tl);
3208 }else{
3209 emit_shl(temp2,temp,temp2);
3210 emit_bic_lsl(tl,HOST_TEMPREG,temp,tl);
3211 }
3212 host_tempreg_release();
3213 emit_or(temp2,tl,tl);
3214 }
cf95b4f0 3215 //emit_storereg(dops[i].rt1,tl); // DEBUG
3968e69e 3216 }
cf95b4f0 3217 if (dops[i].opcode==0x1A||dops[i].opcode==0x1B) { // LDL/LDR
3968e69e 3218 assert(0);
3219 }
57871462 3220}
3221#endif
3222
9b495f6e 3223static void do_invstub(int n)
3224{
3225 literal_pool(20);
684b6816 3226 assem_debug("do_invstub %x\n", start + stubs[n].e*4);
9b495f6e 3227 u_int reglist = stubs[n].a;
3228 u_int addrr = stubs[n].b;
3229 int ofs_start = stubs[n].c;
3230 int ofs_end = stubs[n].d;
3231 int len = ofs_end - ofs_start;
3232 u_int rightr = 0;
3233
3234 set_jump_target(stubs[n].addr, out);
3235 save_regs(reglist);
9b495f6e 3236 if (addrr != 0 || ofs_start != 0)
3237 emit_addimm(addrr, ofs_start, 0);
3033d898 3238 emit_readword(&inv_code_start, 2);
3239 emit_readword(&inv_code_end, 3);
9b495f6e 3240 if (len != 0)
3241 emit_addimm(0, len + 4, (rightr = 1));
3242 emit_cmp(0, 2);
3243 emit_cmpcs(3, rightr);
3244 void *jaddr = out;
3245 emit_jc(0);
3246 void *func = (len != 0)
3247 ? (void *)ndrc_write_invalidate_many
3248 : (void *)ndrc_write_invalidate_one;
3249 emit_far_call(func);
3250 set_jump_target(jaddr, out);
3251 restore_regs(reglist);
3252 emit_jmp(stubs[n].retaddr);
3253}
3254
3255static void do_store_smc_check(int i, const struct regstat *i_regs, u_int reglist, int addr)
3256{
3257 if (HACK_ENABLED(NDHACK_NO_SMC_CHECK))
3258 return;
3259 // this can't be used any more since we started to check exact
3260 // block boundaries in invalidate_range()
3261 //if (i_regs->waswritten & (1<<dops[i].rs1))
3262 // return;
3263 // (naively) assume nobody will run code from stack
3264 if (dops[i].rs1 == 29)
3265 return;
3266
277718fa 3267 int j, imm_maxdiff = 32, imm_min = cinfo[i].imm, imm_max = cinfo[i].imm, count = 1;
9b495f6e 3268 if (i < slen - 1 && dops[i+1].is_store && dops[i+1].rs1 == dops[i].rs1
277718fa 3269 && abs(cinfo[i+1].imm - cinfo[i].imm) <= imm_maxdiff)
9b495f6e 3270 return;
3271 for (j = i - 1; j >= 0; j--) {
3272 if (!dops[j].is_store || dops[j].rs1 != dops[i].rs1
277718fa 3273 || abs(cinfo[j].imm - cinfo[j+1].imm) > imm_maxdiff)
9b495f6e 3274 break;
3275 count++;
277718fa 3276 if (imm_min > cinfo[j].imm)
3277 imm_min = cinfo[j].imm;
3278 if (imm_max < cinfo[j].imm)
3279 imm_max = cinfo[j].imm;
9b495f6e 3280 }
3281#if defined(HOST_IMM8)
3282 int ir = get_reg(i_regs->regmap, INVCP);
3283 assert(ir >= 0);
3284 host_tempreg_acquire();
3285 emit_ldrb_indexedsr12_reg(ir, addr, HOST_TEMPREG);
3286#else
3287 emit_cmpmem_indexedsr12_imm(invalid_code, addr, 1);
3288 #error not handled
3289#endif
3290#ifdef INVALIDATE_USE_COND_CALL
3291 if (count == 1) {
3292 emit_cmpimm(HOST_TEMPREG, 1);
3293 emit_callne(invalidate_addr_reg[addr]);
3294 host_tempreg_release();
3295 return;
3296 }
3297#endif
3298 void *jaddr = emit_cbz(HOST_TEMPREG, 0);
3299 host_tempreg_release();
277718fa 3300 imm_min -= cinfo[i].imm;
3301 imm_max -= cinfo[i].imm;
9b495f6e 3302 add_stub(INVCODE_STUB, jaddr, out, reglist|(1<<HOST_CCREG),
684b6816 3303 addr, imm_min, imm_max, i);
9b495f6e 3304}
3305
684b6816 3306// determines if code overwrite checking is needed only
3307// (also true non-existent 0x20000000 mirror that shouldn't matter)
3308#define is_ram_addr(a) !((a) & 0x5f800000)
3309
2330734f 3310static void store_assemble(int i, const struct regstat *i_regs, int ccadj_)
57871462 3311{
9c45ca93 3312 int s,tl;
277718fa 3313 int addr = cinfo[i].addr;
57871462 3314 int offset;
b14b6a8f 3315 void *jaddr=0;
37387d8b 3316 enum stub_type type=0;
666a299d 3317 int memtarget=0,c=0;
37387d8b 3318 int offset_reg = -1;
3319 int fastio_reg_override = -1;
684b6816 3320 u_int addr_const = ~0;
81dbbf4c 3321 u_int reglist=get_host_reglist(i_regs->regmap);
cf95b4f0 3322 tl=get_reg(i_regs->regmap,dops[i].rs2);
3323 s=get_reg(i_regs->regmap,dops[i].rs1);
277718fa 3324 offset=cinfo[i].imm;
57871462 3325 if(s>=0) {
3326 c=(i_regs->wasconst>>s)&1;
684b6816 3327 if (c) {
3328 addr_const = constmap[i][s] + offset;
3329 memtarget = ((signed int)addr_const) < (signed int)(0x80000000 + RAM_SIZE);
af4ee1fe 3330 }
57871462 3331 }
3332 assert(tl>=0);
277718fa 3333 assert(addr >= 0);
57871462 3334 if(i_regs->regmap[HOST_CCREG]==CCREG) reglist&=~(1<<HOST_CCREG);
684b6816 3335 reglist |= 1u << addr;
37387d8b 3336 if (!c) {
3337 jaddr = emit_fastpath_cmp_jump(i, i_regs, addr,
277718fa 3338 &offset_reg, &fastio_reg_override, ccadj_);
1edfcc68 3339 }
37387d8b 3340 else if (ram_offset && memtarget) {
3341 offset_reg = get_ro_reg(i_regs, 0);
57871462 3342 }
3343
37387d8b 3344 switch (dops[i].opcode) {
3345 case 0x28: // SB
57871462 3346 if(!c||memtarget) {
277718fa 3347 int a = addr;
37387d8b 3348 if (fastio_reg_override >= 0)
3349 a = fastio_reg_override;
3350 do_store_byte(a, tl, offset_reg);
3351 }
3352 type = STOREB_STUB;
3353 break;
3354 case 0x29: // SH
57871462 3355 if(!c||memtarget) {
277718fa 3356 int a = addr;
37387d8b 3357 if (fastio_reg_override >= 0)
3358 a = fastio_reg_override;
3359 do_store_hword(a, 0, tl, offset_reg, 1);
3360 }
3361 type = STOREH_STUB;
3362 break;
3363 case 0x2B: // SW
dadf55f2 3364 if(!c||memtarget) {
37387d8b 3365 int a = addr;
3366 if (fastio_reg_override >= 0)
3367 a = fastio_reg_override;
3368 do_store_word(a, 0, tl, offset_reg, 1);
3369 }
3370 type = STOREW_STUB;
3371 break;
37387d8b 3372 default:
9c45ca93 3373 assert(0);
57871462 3374 }
37387d8b 3375 if (fastio_reg_override == HOST_TEMPREG || offset_reg == HOST_TEMPREG)
d1e4ebd9 3376 host_tempreg_release();
684b6816 3377 if (jaddr) {
b96d3df7 3378 // PCSX store handlers don't check invcode again
2330734f 3379 add_stub_r(type,jaddr,out,i,addr,i_regs,ccadj_,reglist);
7a518516 3380 }
684b6816 3381 if (!c || is_ram_addr(addr_const))
3382 do_store_smc_check(i, i_regs, reglist, addr);
3383 if (c && !memtarget)
3384 inline_writestub(type, i, addr_const, i_regs->regmap, dops[i].rs2, ccadj_, reglist);
7a518516 3385 // basic current block modification detection..
3386 // not looking back as that should be in mips cache already
3968e69e 3387 // (see Spyro2 title->attract mode)
684b6816 3388 if (start + i*4 < addr_const && addr_const < start + slen*4) {
3389 SysPrintf("write to %08x hits block %08x, pc=%08x\n", addr_const, start, start+i*4);
7a518516 3390 assert(i_regs->regmap==regs[i].regmap); // not delay slot
3391 if(i_regs->regmap==regs[i].regmap) {
ad49de89 3392 load_all_consts(regs[i].regmap_entry,regs[i].wasdirty,i);
3393 wb_dirtys(regs[i].regmap_entry,regs[i].wasdirty);
7a518516 3394 emit_movimm(start+i*4+4,0);
643aeae3 3395 emit_writeword(0,&pcaddr);
d1e4ebd9 3396 emit_addimm(HOST_CCREG,2,HOST_CCREG);
104df9d3 3397 emit_far_call(ndrc_get_addr_ht);
d1e4ebd9 3398 emit_jmpreg(0);
7a518516 3399 }
3eaa7048 3400 }
57871462 3401}
3402
2330734f 3403static void storelr_assemble(int i, const struct regstat *i_regs, int ccadj_)
57871462 3404{
277718fa 3405 int addr = cinfo[i].addr;
9c45ca93 3406 int s,tl;
57871462 3407 int offset;
b14b6a8f 3408 void *jaddr=0;
37387d8b 3409 void *case1, *case23, *case3;
df4dc2b1 3410 void *done0, *done1, *done2;
af4ee1fe 3411 int memtarget=0,c=0;
37387d8b 3412 int offset_reg = -1;
684b6816 3413 u_int addr_const = ~0;
3414 u_int reglist = get_host_reglist(i_regs->regmap);
cf95b4f0 3415 tl=get_reg(i_regs->regmap,dops[i].rs2);
3416 s=get_reg(i_regs->regmap,dops[i].rs1);
277718fa 3417 offset=cinfo[i].imm;
57871462 3418 if(s>=0) {
684b6816 3419 c = (i_regs->isconst >> s) & 1;
3420 if (c) {
3421 addr_const = constmap[i][s] + offset;
3422 memtarget = ((signed int)addr_const) < (signed int)(0x80000000 + RAM_SIZE);
af4ee1fe 3423 }
57871462 3424 }
3425 assert(tl>=0);
277718fa 3426 assert(addr >= 0);
684b6816 3427 reglist |= 1u << addr;
1edfcc68 3428 if(!c) {
277718fa 3429 emit_cmpimm(addr, RAM_SIZE);
b14b6a8f 3430 jaddr=out;
1edfcc68 3431 emit_jno(0);
3432 }
3433 else
3434 {
cf95b4f0 3435 if(!memtarget||!dops[i].rs1) {
b14b6a8f 3436 jaddr=out;
535d208a 3437 emit_jmp(0);
57871462 3438 }
535d208a 3439 }
37387d8b 3440 if (ram_offset)
3441 offset_reg = get_ro_reg(i_regs, 0);
535d208a 3442
277718fa 3443 emit_testimm(addr,2);
37387d8b 3444 case23=out;
535d208a 3445 emit_jne(0);
277718fa 3446 emit_testimm(addr,1);
df4dc2b1 3447 case1=out;
535d208a 3448 emit_jne(0);
3449 // 0
37387d8b 3450 if (dops[i].opcode == 0x2A) { // SWL
3451 // Write msb into least significant byte
3452 if (dops[i].rs2) emit_rorimm(tl, 24, tl);
277718fa 3453 do_store_byte(addr, tl, offset_reg);
37387d8b 3454 if (dops[i].rs2) emit_rorimm(tl, 8, tl);
535d208a 3455 }
37387d8b 3456 else if (dops[i].opcode == 0x2E) { // SWR
3457 // Write entire word
277718fa 3458 do_store_word(addr, 0, tl, offset_reg, 1);
535d208a 3459 }
37387d8b 3460 done0 = out;
535d208a 3461 emit_jmp(0);
3462 // 1
df4dc2b1 3463 set_jump_target(case1, out);
37387d8b 3464 if (dops[i].opcode == 0x2A) { // SWL
3465 // Write two msb into two least significant bytes
3466 if (dops[i].rs2) emit_rorimm(tl, 16, tl);
684b6816 3467 do_store_hword(addr, -1, tl, offset_reg, 1);
37387d8b 3468 if (dops[i].rs2) emit_rorimm(tl, 16, tl);
535d208a 3469 }
37387d8b 3470 else if (dops[i].opcode == 0x2E) { // SWR
3471 // Write 3 lsb into three most significant bytes
277718fa 3472 do_store_byte(addr, tl, offset_reg);
37387d8b 3473 if (dops[i].rs2) emit_rorimm(tl, 8, tl);
684b6816 3474 do_store_hword(addr, 1, tl, offset_reg, 1);
37387d8b 3475 if (dops[i].rs2) emit_rorimm(tl, 24, tl);
535d208a 3476 }
df4dc2b1 3477 done1=out;
535d208a 3478 emit_jmp(0);
37387d8b 3479 // 2,3
3480 set_jump_target(case23, out);
277718fa 3481 emit_testimm(addr,1);
37387d8b 3482 case3 = out;
535d208a 3483 emit_jne(0);
37387d8b 3484 // 2
cf95b4f0 3485 if (dops[i].opcode==0x2A) { // SWL
37387d8b 3486 // Write 3 msb into three least significant bytes
3487 if (dops[i].rs2) emit_rorimm(tl, 8, tl);
277718fa 3488 do_store_hword(addr, -2, tl, offset_reg, 1);
37387d8b 3489 if (dops[i].rs2) emit_rorimm(tl, 16, tl);
277718fa 3490 do_store_byte(addr, tl, offset_reg);
37387d8b 3491 if (dops[i].rs2) emit_rorimm(tl, 8, tl);
535d208a 3492 }
37387d8b 3493 else if (dops[i].opcode == 0x2E) { // SWR
3494 // Write two lsb into two most significant bytes
277718fa 3495 do_store_hword(addr, 0, tl, offset_reg, 1);
535d208a 3496 }
37387d8b 3497 done2 = out;
535d208a 3498 emit_jmp(0);
3499 // 3
df4dc2b1 3500 set_jump_target(case3, out);
37387d8b 3501 if (dops[i].opcode == 0x2A) { // SWL
684b6816 3502 do_store_word(addr, -3, tl, offset_reg, 1);
535d208a 3503 }
37387d8b 3504 else if (dops[i].opcode == 0x2E) { // SWR
277718fa 3505 do_store_byte(addr, tl, offset_reg);
535d208a 3506 }
df4dc2b1 3507 set_jump_target(done0, out);
3508 set_jump_target(done1, out);
3509 set_jump_target(done2, out);
37387d8b 3510 if (offset_reg == HOST_TEMPREG)
3511 host_tempreg_release();
684b6816 3512 if (!c || !memtarget)
277718fa 3513 add_stub_r(STORELR_STUB,jaddr,out,i,addr,i_regs,ccadj_,reglist);
684b6816 3514 if (!c || is_ram_addr(addr_const))
3515 do_store_smc_check(i, i_regs, reglist, addr);
57871462 3516}
3517
2330734f 3518static void cop0_assemble(int i, const struct regstat *i_regs, int ccadj_)
8062d65a 3519{
cf95b4f0 3520 if(dops[i].opcode2==0) // MFC0
8062d65a 3521 {
a5cd72d0 3522 signed char t=get_reg_w(i_regs->regmap, dops[i].rt1);
8062d65a 3523 u_int copr=(source[i]>>11)&0x1f;
cf95b4f0 3524 if(t>=0&&dops[i].rt1!=0) {
8062d65a 3525 emit_readword(&reg_cop0[copr],t);
3526 }
3527 }
cf95b4f0 3528 else if(dops[i].opcode2==4) // MTC0
8062d65a 3529 {
de6dbc52 3530 int s = get_reg(i_regs->regmap, dops[i].rs1);
3531 int cc = get_reg(i_regs->regmap, CCREG);
8062d65a 3532 char copr=(source[i]>>11)&0x1f;
3533 assert(s>=0);
cf95b4f0 3534 wb_register(dops[i].rs1,i_regs->regmap,i_regs->dirty);
de6dbc52 3535 if (copr == 12 || copr == 13) {
8062d65a 3536 emit_readword(&last_count,HOST_TEMPREG);
de6dbc52 3537 if (cc != HOST_CCREG)
3538 emit_loadreg(CCREG, HOST_CCREG);
3539 emit_add(HOST_CCREG, HOST_TEMPREG, HOST_CCREG);
3540 emit_addimm(HOST_CCREG, ccadj_ + 2, HOST_CCREG);
3541 emit_writeword(HOST_CCREG, &psxRegs.cycle);
8062d65a 3542 if (is_delayslot) {
3543 // burn cycles to cause cc_interrupt, which will
3544 // reschedule next_interupt. Relies on CCREG from above.
3545 assem_debug("MTC0 DS %d\n", copr);
3546 emit_writeword(HOST_CCREG,&last_count);
3547 emit_movimm(0,HOST_CCREG);
3548 emit_storereg(CCREG,HOST_CCREG);
cf95b4f0 3549 emit_loadreg(dops[i].rs1,1);
8062d65a 3550 emit_movimm(copr,0);
2a014d73 3551 emit_far_call(pcsx_mtc0_ds);
cf95b4f0 3552 emit_loadreg(dops[i].rs1,s);
8062d65a 3553 return;
3554 }
3555 emit_movimm(start+i*4+4,HOST_TEMPREG);
3556 emit_writeword(HOST_TEMPREG,&pcaddr);
3557 emit_movimm(0,HOST_TEMPREG);
3558 emit_writeword(HOST_TEMPREG,&pending_exception);
3559 }
de6dbc52 3560 if( s != 1)
3561 emit_mov(s, 1);
3562 emit_movimm(copr, 0);
2a014d73 3563 emit_far_call(pcsx_mtc0);
de6dbc52 3564 if (copr == 12 || copr == 13) {
d7546062 3565 emit_readword(&psxRegs.cycle,HOST_CCREG);
de6dbc52 3566 emit_readword(&last_count,HOST_TEMPREG);
8062d65a 3567 emit_sub(HOST_CCREG,HOST_TEMPREG,HOST_CCREG);
de6dbc52 3568 //emit_writeword(HOST_TEMPREG,&last_count);
8062d65a 3569 assert(!is_delayslot);
9b495f6e 3570 emit_readword(&pending_exception,HOST_TEMPREG);
3571 emit_test(HOST_TEMPREG,HOST_TEMPREG);
d1e4ebd9 3572 void *jaddr = out;
3573 emit_jeq(0);
3574 emit_readword(&pcaddr, 0);
104df9d3 3575 emit_far_call(ndrc_get_addr_ht);
d1e4ebd9 3576 emit_jmpreg(0);
3577 set_jump_target(jaddr, out);
de6dbc52 3578 emit_addimm(HOST_CCREG, -ccadj_ - 2, HOST_CCREG);
3579 if (cc != HOST_CCREG)
3580 emit_storereg(CCREG, HOST_CCREG);
8062d65a 3581 }
cf95b4f0 3582 emit_loadreg(dops[i].rs1,s);
8062d65a 3583 }
8062d65a 3584}
3585
277718fa 3586static void rfe_assemble(int i, const struct regstat *i_regs)
8062d65a 3587{
a5cd72d0 3588 emit_readword(&psxRegs.CP0.n.SR, 0);
3589 emit_andimm(0, 0x3c, 1);
3590 emit_andimm(0, ~0xf, 0);
3591 emit_orrshr_imm(1, 2, 0);
3592 emit_writeword(0, &psxRegs.CP0.n.SR);
8062d65a 3593}
3594
e3c6bdb5 3595static int cop2_is_stalling_op(int i, int *cycles)
3596{
cf95b4f0 3597 if (dops[i].opcode == 0x3a) { // SWC2
e3c6bdb5 3598 *cycles = 0;
3599 return 1;
3600 }
cf95b4f0 3601 if (dops[i].itype == COP2 && (dops[i].opcode2 == 0 || dops[i].opcode2 == 2)) { // MFC2/CFC2
e3c6bdb5 3602 *cycles = 0;
3603 return 1;
3604 }
cf95b4f0 3605 if (dops[i].itype == C2OP) {
e3c6bdb5 3606 *cycles = gte_cycletab[source[i] & 0x3f];
3607 return 1;
3608 }
3609 // ... what about MTC2/CTC2/LWC2?
3610 return 0;
3611}
3612
3613#if 0
3614static void log_gte_stall(int stall, u_int cycle)
3615{
3616 if ((u_int)stall <= 44)
3617 printf("x stall %2d %u\n", stall, cycle + last_count);
e3c6bdb5 3618}
3619
3620static void emit_log_gte_stall(int i, int stall, u_int reglist)
3621{
3622 save_regs(reglist);
3623 if (stall > 0)
3624 emit_movimm(stall, 0);
3625 else
3626 emit_mov(HOST_TEMPREG, 0);
277718fa 3627 emit_addimm(HOST_CCREG, cinfo[i].ccadj, 1);
e3c6bdb5 3628 emit_far_call(log_gte_stall);
3629 restore_regs(reglist);
3630}
3631#endif
3632
32631e6a 3633static void cop2_do_stall_check(u_int op, int i, const struct regstat *i_regs, u_int reglist)
81dbbf4c 3634{
e3c6bdb5 3635 int j = i, other_gte_op_cycles = -1, stall = -MAXBLOCK, cycles_passed;
3636 int rtmp = reglist_find_free(reglist);
3637
32631e6a 3638 if (HACK_ENABLED(NDHACK_NO_STALLS))
81dbbf4c 3639 return;
81dbbf4c 3640 if (get_reg(i_regs->regmap, CCREG) != HOST_CCREG) {
3641 // happens occasionally... cc evicted? Don't bother then
3642 //printf("no cc %08x\n", start + i*4);
3643 return;
3644 }
cf95b4f0 3645 if (!dops[i].bt) {
e3c6bdb5 3646 for (j = i - 1; j >= 0; j--) {
cf95b4f0 3647 //if (dops[j].is_ds) break;
3648 if (cop2_is_stalling_op(j, &other_gte_op_cycles) || dops[j].bt)
e3c6bdb5 3649 break;
277718fa 3650 if (j > 0 && cinfo[j - 1].ccadj > cinfo[j].ccadj)
2330734f 3651 break;
e3c6bdb5 3652 }
32631e6a 3653 j = max(j, 0);
e3c6bdb5 3654 }
277718fa 3655 cycles_passed = cinfo[i].ccadj - cinfo[j].ccadj;
e3c6bdb5 3656 if (other_gte_op_cycles >= 0)
3657 stall = other_gte_op_cycles - cycles_passed;
3658 else if (cycles_passed >= 44)
3659 stall = 0; // can't stall
3660 if (stall == -MAXBLOCK && rtmp >= 0) {
3661 // unknown stall, do the expensive runtime check
32631e6a 3662 assem_debug("; cop2_do_stall_check\n");
e3c6bdb5 3663#if 0 // too slow
3664 save_regs(reglist);
3665 emit_movimm(gte_cycletab[op], 0);
277718fa 3666 emit_addimm(HOST_CCREG, cinfo[i].ccadj, 1);
e3c6bdb5 3667 emit_far_call(call_gteStall);
3668 restore_regs(reglist);
3669#else
3670 host_tempreg_acquire();
3671 emit_readword(&psxRegs.gteBusyCycle, rtmp);
277718fa 3672 emit_addimm(rtmp, -cinfo[i].ccadj, rtmp);
e3c6bdb5 3673 emit_sub(rtmp, HOST_CCREG, HOST_TEMPREG);
3674 emit_cmpimm(HOST_TEMPREG, 44);
3675 emit_cmovb_reg(rtmp, HOST_CCREG);
3676 //emit_log_gte_stall(i, 0, reglist);
3677 host_tempreg_release();
3678#endif
3679 }
3680 else if (stall > 0) {
3681 //emit_log_gte_stall(i, stall, reglist);
3682 emit_addimm(HOST_CCREG, stall, HOST_CCREG);
3683 }
3684
3685 // save gteBusyCycle, if needed
3686 if (gte_cycletab[op] == 0)
3687 return;
3688 other_gte_op_cycles = -1;
3689 for (j = i + 1; j < slen; j++) {
3690 if (cop2_is_stalling_op(j, &other_gte_op_cycles))
3691 break;
fe807a8a 3692 if (dops[j].is_jump) {
e3c6bdb5 3693 // check ds
3694 if (j + 1 < slen && cop2_is_stalling_op(j + 1, &other_gte_op_cycles))
3695 j++;
3696 break;
3697 }
3698 }
3699 if (other_gte_op_cycles >= 0)
3700 // will handle stall when assembling that op
3701 return;
277718fa 3702 cycles_passed = cinfo[min(j, slen -1)].ccadj - cinfo[i].ccadj;
e3c6bdb5 3703 if (cycles_passed >= 44)
3704 return;
3705 assem_debug("; save gteBusyCycle\n");
3706 host_tempreg_acquire();
3707#if 0
3708 emit_readword(&last_count, HOST_TEMPREG);
3709 emit_add(HOST_TEMPREG, HOST_CCREG, HOST_TEMPREG);
277718fa 3710 emit_addimm(HOST_TEMPREG, cinfo[i].ccadj, HOST_TEMPREG);
e3c6bdb5 3711 emit_addimm(HOST_TEMPREG, gte_cycletab[op]), HOST_TEMPREG);
3712 emit_writeword(HOST_TEMPREG, &psxRegs.gteBusyCycle);
3713#else
277718fa 3714 emit_addimm(HOST_CCREG, cinfo[i].ccadj + gte_cycletab[op], HOST_TEMPREG);
e3c6bdb5 3715 emit_writeword(HOST_TEMPREG, &psxRegs.gteBusyCycle);
3716#endif
3717 host_tempreg_release();
81dbbf4c 3718}
3719
32631e6a 3720static int is_mflohi(int i)
3721{
cf95b4f0 3722 return (dops[i].itype == MOV && (dops[i].rs1 == HIREG || dops[i].rs1 == LOREG));
32631e6a 3723}
3724
3725static int check_multdiv(int i, int *cycles)
3726{
cf95b4f0 3727 if (dops[i].itype != MULTDIV)
32631e6a 3728 return 0;
cf95b4f0 3729 if (dops[i].opcode2 == 0x18 || dops[i].opcode2 == 0x19) // MULT(U)
32631e6a 3730 *cycles = 11; // approx from 7 11 14
3731 else
3732 *cycles = 37;
3733 return 1;
3734}
3735
2330734f 3736static void multdiv_prepare_stall(int i, const struct regstat *i_regs, int ccadj_)
32631e6a 3737{
3738 int j, found = 0, c = 0;
3739 if (HACK_ENABLED(NDHACK_NO_STALLS))
3740 return;
3741 if (get_reg(i_regs->regmap, CCREG) != HOST_CCREG) {
3742 // happens occasionally... cc evicted? Don't bother then
3743 return;
3744 }
3745 for (j = i + 1; j < slen; j++) {
cf95b4f0 3746 if (dops[j].bt)
32631e6a 3747 break;
3748 if ((found = is_mflohi(j)))
3749 break;
fe807a8a 3750 if (dops[j].is_jump) {
32631e6a 3751 // check ds
3752 if (j + 1 < slen && (found = is_mflohi(j + 1)))
3753 j++;
3754 break;
3755 }
3756 }
3757 if (found)
3758 // handle all in multdiv_do_stall()
3759 return;
3760 check_multdiv(i, &c);
3761 assert(c > 0);
3762 assem_debug("; muldiv prepare stall %d\n", c);
3763 host_tempreg_acquire();
2330734f 3764 emit_addimm(HOST_CCREG, ccadj_ + c, HOST_TEMPREG);
32631e6a 3765 emit_writeword(HOST_TEMPREG, &psxRegs.muldivBusyCycle);
3766 host_tempreg_release();
3767}
3768
3769static void multdiv_do_stall(int i, const struct regstat *i_regs)
3770{
3771 int j, known_cycles = 0;
3772 u_int reglist = get_host_reglist(i_regs->regmap);
9de8a0c3 3773 int rtmp = get_reg_temp(i_regs->regmap);
32631e6a 3774 if (rtmp < 0)
3775 rtmp = reglist_find_free(reglist);
3776 if (HACK_ENABLED(NDHACK_NO_STALLS))
3777 return;
3778 if (get_reg(i_regs->regmap, CCREG) != HOST_CCREG || rtmp < 0) {
3779 // happens occasionally... cc evicted? Don't bother then
3780 //printf("no cc/rtmp %08x\n", start + i*4);
3781 return;
3782 }
cf95b4f0 3783 if (!dops[i].bt) {
32631e6a 3784 for (j = i - 1; j >= 0; j--) {
cf95b4f0 3785 if (dops[j].is_ds) break;
2330734f 3786 if (check_multdiv(j, &known_cycles))
32631e6a 3787 break;
3788 if (is_mflohi(j))
3789 // already handled by this op
3790 return;
277718fa 3791 if (dops[j].bt || (j > 0 && cinfo[j - 1].ccadj > cinfo[j].ccadj))
2330734f 3792 break;
32631e6a 3793 }
3794 j = max(j, 0);
3795 }
3796 if (known_cycles > 0) {
277718fa 3797 known_cycles -= cinfo[i].ccadj - cinfo[j].ccadj;
32631e6a 3798 assem_debug("; muldiv stall resolved %d\n", known_cycles);
3799 if (known_cycles > 0)
3800 emit_addimm(HOST_CCREG, known_cycles, HOST_CCREG);
3801 return;
3802 }
3803 assem_debug("; muldiv stall unresolved\n");
3804 host_tempreg_acquire();
3805 emit_readword(&psxRegs.muldivBusyCycle, rtmp);
277718fa 3806 emit_addimm(rtmp, -cinfo[i].ccadj, rtmp);
32631e6a 3807 emit_sub(rtmp, HOST_CCREG, HOST_TEMPREG);
3808 emit_cmpimm(HOST_TEMPREG, 37);
3809 emit_cmovb_reg(rtmp, HOST_CCREG);
3810 //emit_log_gte_stall(i, 0, reglist);
3811 host_tempreg_release();
3812}
3813
8062d65a 3814static void cop2_get_dreg(u_int copr,signed char tl,signed char temp)
3815{
3816 switch (copr) {
3817 case 1:
3818 case 3:
3819 case 5:
3820 case 8:
3821 case 9:
3822 case 10:
3823 case 11:
3824 emit_readword(&reg_cop2d[copr],tl);
3825 emit_signextend16(tl,tl);
3826 emit_writeword(tl,&reg_cop2d[copr]); // hmh
3827 break;
3828 case 7:
3829 case 16:
3830 case 17:
3831 case 18:
3832 case 19:
3833 emit_readword(&reg_cop2d[copr],tl);
3834 emit_andimm(tl,0xffff,tl);
3835 emit_writeword(tl,&reg_cop2d[copr]);
3836 break;
3837 case 15:
3838 emit_readword(&reg_cop2d[14],tl); // SXY2
3839 emit_writeword(tl,&reg_cop2d[copr]);
3840 break;
3841 case 28:
3842 case 29:
3968e69e 3843 c2op_mfc2_29_assemble(tl,temp);
8062d65a 3844 break;
3845 default:
3846 emit_readword(&reg_cop2d[copr],tl);
3847 break;
3848 }
3849}
3850
3851static void cop2_put_dreg(u_int copr,signed char sl,signed char temp)
3852{
3853 switch (copr) {
3854 case 15:
3855 emit_readword(&reg_cop2d[13],temp); // SXY1
3856 emit_writeword(sl,&reg_cop2d[copr]);
3857 emit_writeword(temp,&reg_cop2d[12]); // SXY0
3858 emit_readword(&reg_cop2d[14],temp); // SXY2
3859 emit_writeword(sl,&reg_cop2d[14]);
3860 emit_writeword(temp,&reg_cop2d[13]); // SXY1
3861 break;
3862 case 28:
3863 emit_andimm(sl,0x001f,temp);
3864 emit_shlimm(temp,7,temp);
3865 emit_writeword(temp,&reg_cop2d[9]);
3866 emit_andimm(sl,0x03e0,temp);
3867 emit_shlimm(temp,2,temp);
3868 emit_writeword(temp,&reg_cop2d[10]);
3869 emit_andimm(sl,0x7c00,temp);
3870 emit_shrimm(temp,3,temp);
3871 emit_writeword(temp,&reg_cop2d[11]);
3872 emit_writeword(sl,&reg_cop2d[28]);
3873 break;
3874 case 30:
3968e69e 3875 emit_xorsar_imm(sl,sl,31,temp);
be516ebe 3876#if defined(HAVE_ARMV5) || defined(__aarch64__)
8062d65a 3877 emit_clz(temp,temp);
3878#else
3879 emit_movs(temp,HOST_TEMPREG);
3880 emit_movimm(0,temp);
3881 emit_jeq((int)out+4*4);
3882 emit_addpl_imm(temp,1,temp);
3883 emit_lslpls_imm(HOST_TEMPREG,1,HOST_TEMPREG);
3884 emit_jns((int)out-2*4);
3885#endif
3886 emit_writeword(sl,&reg_cop2d[30]);
3887 emit_writeword(temp,&reg_cop2d[31]);
3888 break;
3889 case 31:
3890 break;
3891 default:
3892 emit_writeword(sl,&reg_cop2d[copr]);
3893 break;
3894 }
3895}
3896
2330734f 3897static void c2ls_assemble(int i, const struct regstat *i_regs, int ccadj_)
b9b61529 3898{
3899 int s,tl;
3900 int ar;
3901 int offset;
1fd1aceb 3902 int memtarget=0,c=0;
b14b6a8f 3903 void *jaddr2=NULL;
3904 enum stub_type type;
37387d8b 3905 int offset_reg = -1;
3906 int fastio_reg_override = -1;
684b6816 3907 u_int addr_const = ~0;
81dbbf4c 3908 u_int reglist=get_host_reglist(i_regs->regmap);
b9b61529 3909 u_int copr=(source[i]>>16)&0x1f;
cf95b4f0 3910 s=get_reg(i_regs->regmap,dops[i].rs1);
b9b61529 3911 tl=get_reg(i_regs->regmap,FTEMP);
277718fa 3912 offset=cinfo[i].imm;
b9b61529 3913 assert(tl>=0);
b9b61529 3914
b9b61529 3915 if(i_regs->regmap[HOST_CCREG]==CCREG)
3916 reglist&=~(1<<HOST_CCREG);
3917
3918 // get the address
277718fa 3919 ar = cinfo[i].addr;
3920 assert(ar >= 0);
cf95b4f0 3921 if (dops[i].opcode==0x3a) { // SWC2
277718fa 3922 reglist |= 1<<ar;
b9b61529 3923 }
684b6816 3924 if (s >= 0) {
3925 c = (i_regs->isconst >> s) & 1;
3926 if (c) {
3927 addr_const = constmap[i][s] + offset;
3928 memtarget = ((signed int)addr_const) < (signed int)(0x80000000 + RAM_SIZE);
3929 }
3930 }
b9b61529 3931
32631e6a 3932 cop2_do_stall_check(0, i, i_regs, reglist);
3933
cf95b4f0 3934 if (dops[i].opcode==0x3a) { // SWC2
3968e69e 3935 cop2_get_dreg(copr,tl,-1);
1fd1aceb 3936 type=STOREW_STUB;
b9b61529 3937 }
1fd1aceb 3938 else
b9b61529 3939 type=LOADW_STUB;
1fd1aceb 3940
3941 if(c&&!memtarget) {
b14b6a8f 3942 jaddr2=out;
1fd1aceb 3943 emit_jmp(0); // inline_readstub/inline_writestub?
b9b61529 3944 }
1fd1aceb 3945 else {
3946 if(!c) {
37387d8b 3947 jaddr2 = emit_fastpath_cmp_jump(i, i_regs, ar,
277718fa 3948 &offset_reg, &fastio_reg_override, ccadj_);
37387d8b 3949 }
3950 else if (ram_offset && memtarget) {
3951 offset_reg = get_ro_reg(i_regs, 0);
3952 }
3953 switch (dops[i].opcode) {
3954 case 0x32: { // LWC2
3955 int a = ar;
3956 if (fastio_reg_override >= 0)
3957 a = fastio_reg_override;
3958 do_load_word(a, tl, offset_reg);
3959 break;
1fd1aceb 3960 }
37387d8b 3961 case 0x3a: { // SWC2
1fd1aceb 3962 #ifdef DESTRUCTIVE_SHIFT
3963 if(!offset&&!c&&s>=0) emit_mov(s,ar);
3964 #endif
37387d8b 3965 int a = ar;
3966 if (fastio_reg_override >= 0)
3967 a = fastio_reg_override;
3968 do_store_word(a, 0, tl, offset_reg, 1);
3969 break;
3970 }
3971 default:
3972 assert(0);
1fd1aceb 3973 }
b9b61529 3974 }
37387d8b 3975 if (fastio_reg_override == HOST_TEMPREG || offset_reg == HOST_TEMPREG)
d1e4ebd9 3976 host_tempreg_release();
b9b61529 3977 if(jaddr2)
2330734f 3978 add_stub_r(type,jaddr2,out,i,ar,i_regs,ccadj_,reglist);
684b6816 3979 if (dops[i].opcode == 0x3a && (!c || is_ram_addr(addr_const))) // SWC2
9b495f6e 3980 do_store_smc_check(i, i_regs, reglist, ar);
684b6816 3981 if (dops[i].opcode == 0x32) { // LWC2
d1e4ebd9 3982 host_tempreg_acquire();
b9b61529 3983 cop2_put_dreg(copr,tl,HOST_TEMPREG);
d1e4ebd9 3984 host_tempreg_release();
b9b61529 3985 }
3986}
3987
81dbbf4c 3988static void cop2_assemble(int i, const struct regstat *i_regs)
8062d65a 3989{
81dbbf4c 3990 u_int copr = (source[i]>>11) & 0x1f;
9de8a0c3 3991 signed char temp = get_reg_temp(i_regs->regmap);
81dbbf4c 3992
32631e6a 3993 if (!HACK_ENABLED(NDHACK_NO_STALLS)) {
3994 u_int reglist = reglist_exclude(get_host_reglist(i_regs->regmap), temp, -1);
cf95b4f0 3995 if (dops[i].opcode2 == 0 || dops[i].opcode2 == 2) { // MFC2/CFC2
3996 signed char tl = get_reg(i_regs->regmap, dops[i].rt1);
32631e6a 3997 reglist = reglist_exclude(reglist, tl, -1);
81dbbf4c 3998 }
32631e6a 3999 cop2_do_stall_check(0, i, i_regs, reglist);
81dbbf4c 4000 }
cf95b4f0 4001 if (dops[i].opcode2==0) { // MFC2
a5cd72d0 4002 signed char tl=get_reg_w(i_regs->regmap, dops[i].rt1);
cf95b4f0 4003 if(tl>=0&&dops[i].rt1!=0)
8062d65a 4004 cop2_get_dreg(copr,tl,temp);
4005 }
cf95b4f0 4006 else if (dops[i].opcode2==4) { // MTC2
4007 signed char sl=get_reg(i_regs->regmap,dops[i].rs1);
8062d65a 4008 cop2_put_dreg(copr,sl,temp);
4009 }
cf95b4f0 4010 else if (dops[i].opcode2==2) // CFC2
8062d65a 4011 {
a5cd72d0 4012 signed char tl=get_reg_w(i_regs->regmap, dops[i].rt1);
cf95b4f0 4013 if(tl>=0&&dops[i].rt1!=0)
8062d65a 4014 emit_readword(&reg_cop2c[copr],tl);
4015 }
cf95b4f0 4016 else if (dops[i].opcode2==6) // CTC2
8062d65a 4017 {
cf95b4f0 4018 signed char sl=get_reg(i_regs->regmap,dops[i].rs1);
8062d65a 4019 switch(copr) {
4020 case 4:
4021 case 12:
4022 case 20:
4023 case 26:
4024 case 27:
4025 case 29:
4026 case 30:
4027 emit_signextend16(sl,temp);
4028 break;
4029 case 31:
3968e69e 4030 c2op_ctc2_31_assemble(sl,temp);
8062d65a 4031 break;
4032 default:
4033 temp=sl;
4034 break;
4035 }
4036 emit_writeword(temp,&reg_cop2c[copr]);
4037 assert(sl>=0);
4038 }
4039}
4040
3968e69e 4041static void do_unalignedwritestub(int n)
4042{
4043 assem_debug("do_unalignedwritestub %x\n",start+stubs[n].a*4);
4044 literal_pool(256);
4045 set_jump_target(stubs[n].addr, out);
4046
4047 int i=stubs[n].a;
4048 struct regstat *i_regs=(struct regstat *)stubs[n].c;
4049 int addr=stubs[n].b;
4050 u_int reglist=stubs[n].e;
4051 signed char *i_regmap=i_regs->regmap;
4052 int temp2=get_reg(i_regmap,FTEMP);
4053 int rt;
cf95b4f0 4054 rt=get_reg(i_regmap,dops[i].rs2);
3968e69e 4055 assert(rt>=0);
4056 assert(addr>=0);
cf95b4f0 4057 assert(dops[i].opcode==0x2a||dops[i].opcode==0x2e); // SWL/SWR only implemented
3968e69e 4058 reglist|=(1<<addr);
4059 reglist&=~(1<<temp2);
4060
3968e69e 4061 // don't bother with it and call write handler
4062 save_regs(reglist);
4063 pass_args(addr,rt);
4064 int cc=get_reg(i_regmap,CCREG);
4065 if(cc<0)
4066 emit_loadreg(CCREG,2);
2330734f 4067 emit_addimm(cc<0?2:cc,(int)stubs[n].d+1,2);
de6dbc52 4068 emit_movimm(start + i*4,3);
4069 emit_writeword(3,&psxRegs.pc);
cf95b4f0 4070 emit_far_call((dops[i].opcode==0x2a?jump_handle_swl:jump_handle_swr));
2330734f 4071 emit_addimm(0,-((int)stubs[n].d+1),cc<0?2:cc);
3968e69e 4072 if(cc<0)
4073 emit_storereg(CCREG,2);
4074 restore_regs(reglist);
4075 emit_jmp(stubs[n].retaddr); // return address
3968e69e 4076}
4077
a5cd72d0 4078static void do_overflowstub(int n)
4079{
4080 assem_debug("do_overflowstub %x\n", start + (u_int)stubs[n].a * 4);
4081 literal_pool(24);
4082 int i = stubs[n].a;
4083 struct regstat *i_regs = (struct regstat *)stubs[n].c;
4084 int ccadj = stubs[n].d;
4085 set_jump_target(stubs[n].addr, out);
4086 wb_dirtys(regs[i].regmap, regs[i].dirty);
4087 exception_assemble(i, i_regs, ccadj);
4088}
4089
277718fa 4090static void do_alignmentstub(int n)
4091{
4092 assem_debug("do_alignmentstub %x\n", start + (u_int)stubs[n].a * 4);
4093 literal_pool(24);
4094 int i = stubs[n].a;
4095 struct regstat *i_regs = (struct regstat *)stubs[n].c;
4096 int ccadj = stubs[n].d;
4097 int is_store = dops[i].itype == STORE || dops[i].opcode == 0x3A; // SWC2
4098 int cause = (dops[i].opcode & 3) << 28;
4099 cause |= is_store ? (R3000E_AdES << 2) : (R3000E_AdEL << 2);
4100 set_jump_target(stubs[n].addr, out);
4101 wb_dirtys(regs[i].regmap, regs[i].dirty);
4102 if (stubs[n].b != 1)
4103 emit_mov(stubs[n].b, 1); // faulting address
4104 emit_movimm(cause, 0);
4105 exception_assemble(i, i_regs, ccadj);
4106}
4107
57871462 4108#ifndef multdiv_assemble
4109void multdiv_assemble(int i,struct regstat *i_regs)
4110{
4111 printf("Need multdiv_assemble for this architecture.\n");
7c3a5182 4112 abort();
57871462 4113}
4114#endif
4115
2330734f 4116static void mov_assemble(int i, const struct regstat *i_regs)
57871462 4117{
cf95b4f0 4118 //if(dops[i].opcode2==0x10||dops[i].opcode2==0x12) { // MFHI/MFLO
4119 //if(dops[i].opcode2==0x11||dops[i].opcode2==0x13) { // MTHI/MTLO
4120 if(dops[i].rt1) {
7c3a5182 4121 signed char sl,tl;
a5cd72d0 4122 tl=get_reg_w(i_regs->regmap, dops[i].rt1);
57871462 4123 //assert(tl>=0);
4124 if(tl>=0) {
cf95b4f0 4125 sl=get_reg(i_regs->regmap,dops[i].rs1);
57871462 4126 if(sl>=0) emit_mov(sl,tl);
cf95b4f0 4127 else emit_loadreg(dops[i].rs1,tl);
57871462 4128 }
4129 }
cf95b4f0 4130 if (dops[i].rs1 == HIREG || dops[i].rs1 == LOREG) // MFHI/MFLO
32631e6a 4131 multdiv_do_stall(i, i_regs);
57871462 4132}
4133
3968e69e 4134// call interpreter, exception handler, things that change pc/regs/cycles ...
2330734f 4135static void call_c_cpu_handler(int i, const struct regstat *i_regs, int ccadj_, u_int pc, void *func)
57871462 4136{
4137 signed char ccreg=get_reg(i_regs->regmap,CCREG);
4138 assert(ccreg==HOST_CCREG);
4139 assert(!is_delayslot);
581335b0 4140 (void)ccreg;
3968e69e 4141
4142 emit_movimm(pc,3); // Get PC
4143 emit_readword(&last_count,2);
4144 emit_writeword(3,&psxRegs.pc);
2330734f 4145 emit_addimm(HOST_CCREG,ccadj_,HOST_CCREG);
3968e69e 4146 emit_add(2,HOST_CCREG,2);
4147 emit_writeword(2,&psxRegs.cycle);
bc7c5acb 4148 emit_addimm_ptr(FP,(u_char *)&psxRegs - (u_char *)&dynarec_local,0);
2a014d73 4149 emit_far_call(func);
4150 emit_far_jump(jump_to_new_pc);
3968e69e 4151}
4152
a5cd72d0 4153static void exception_assemble(int i, const struct regstat *i_regs, int ccadj_)
3968e69e 4154{
d1150cd6 4155 // 'break' tends to be littered around to catch things like
4156 // division by 0 and is almost never executed, so don't emit much code here
a5cd72d0 4157 void *func;
4158 if (dops[i].itype == ALU || dops[i].itype == IMM16)
4159 func = is_delayslot ? jump_overflow_ds : jump_overflow;
277718fa 4160 else if (dops[i].itype == LOAD || dops[i].itype == STORE)
4161 func = is_delayslot ? jump_addrerror_ds : jump_addrerror;
a5cd72d0 4162 else if (dops[i].opcode2 == 0x0C)
4163 func = is_delayslot ? jump_syscall_ds : jump_syscall;
4164 else
4165 func = is_delayslot ? jump_break_ds : jump_break;
277718fa 4166 if (get_reg(i_regs->regmap, CCREG) != HOST_CCREG) // evicted
4167 emit_loadreg(CCREG, HOST_CCREG);
d1150cd6 4168 emit_movimm(start + i*4, 2); // pc
4169 emit_addimm(HOST_CCREG, ccadj_ + CLOCK_ADJUST(1), HOST_CCREG);
4170 emit_far_jump(func);
7139f3c8 4171}
4172
bc7c5acb 4173static void hlecall_bad()
4174{
a5cd72d0 4175 assert(0);
bc7c5acb 4176}
4177
2330734f 4178static void hlecall_assemble(int i, const struct regstat *i_regs, int ccadj_)
7139f3c8 4179{
bc7c5acb 4180 void *hlefunc = hlecall_bad;
dd79da89 4181 uint32_t hleCode = source[i] & 0x03ffffff;
3968e69e 4182 if (hleCode < ARRAY_SIZE(psxHLEt))
4183 hlefunc = psxHLEt[hleCode];
4184
2330734f 4185 call_c_cpu_handler(i, i_regs, ccadj_, start + i*4+4, hlefunc);
57871462 4186}
4187
2330734f 4188static void intcall_assemble(int i, const struct regstat *i_regs, int ccadj_)
1e973cb0 4189{
2330734f 4190 call_c_cpu_handler(i, i_regs, ccadj_, start + i*4, execI);
1e973cb0 4191}
4192
8062d65a 4193static void speculate_mov(int rs,int rt)
4194{
4195 if(rt!=0) {
4196 smrv_strong_next|=1<<rt;
4197 smrv[rt]=smrv[rs];
4198 }
4199}
4200
4201static void speculate_mov_weak(int rs,int rt)
4202{
4203 if(rt!=0) {
4204 smrv_weak_next|=1<<rt;
4205 smrv[rt]=smrv[rs];
4206 }
4207}
4208
4209static void speculate_register_values(int i)
4210{
4211 if(i==0) {
4212 memcpy(smrv,psxRegs.GPR.r,sizeof(smrv));
4213 // gp,sp are likely to stay the same throughout the block
4214 smrv_strong_next=(1<<28)|(1<<29)|(1<<30);
4215 smrv_weak_next=~smrv_strong_next;
4216 //printf(" llr %08x\n", smrv[4]);
4217 }
4218 smrv_strong=smrv_strong_next;
4219 smrv_weak=smrv_weak_next;
cf95b4f0 4220 switch(dops[i].itype) {
8062d65a 4221 case ALU:
cf95b4f0 4222 if ((smrv_strong>>dops[i].rs1)&1) speculate_mov(dops[i].rs1,dops[i].rt1);
4223 else if((smrv_strong>>dops[i].rs2)&1) speculate_mov(dops[i].rs2,dops[i].rt1);
4224 else if((smrv_weak>>dops[i].rs1)&1) speculate_mov_weak(dops[i].rs1,dops[i].rt1);
4225 else if((smrv_weak>>dops[i].rs2)&1) speculate_mov_weak(dops[i].rs2,dops[i].rt1);
8062d65a 4226 else {
cf95b4f0 4227 smrv_strong_next&=~(1<<dops[i].rt1);
4228 smrv_weak_next&=~(1<<dops[i].rt1);
8062d65a 4229 }
4230 break;
4231 case SHIFTIMM:
cf95b4f0 4232 smrv_strong_next&=~(1<<dops[i].rt1);
4233 smrv_weak_next&=~(1<<dops[i].rt1);
8062d65a 4234 // fallthrough
4235 case IMM16:
cf95b4f0 4236 if(dops[i].rt1&&is_const(&regs[i],dops[i].rt1)) {
de6dbc52 4237 int hr = get_reg_w(regs[i].regmap, dops[i].rt1);
4238 u_int value;
8062d65a 4239 if(hr>=0) {
4240 if(get_final_value(hr,i,&value))
cf95b4f0 4241 smrv[dops[i].rt1]=value;
4242 else smrv[dops[i].rt1]=constmap[i][hr];
4243 smrv_strong_next|=1<<dops[i].rt1;
8062d65a 4244 }
4245 }
4246 else {
cf95b4f0 4247 if ((smrv_strong>>dops[i].rs1)&1) speculate_mov(dops[i].rs1,dops[i].rt1);
4248 else if((smrv_weak>>dops[i].rs1)&1) speculate_mov_weak(dops[i].rs1,dops[i].rt1);
8062d65a 4249 }
4250 break;
4251 case LOAD:
cf95b4f0 4252 if(start<0x2000&&(dops[i].rt1==26||(smrv[dops[i].rt1]>>24)==0xa0)) {
8062d65a 4253 // special case for BIOS
cf95b4f0 4254 smrv[dops[i].rt1]=0xa0000000;
4255 smrv_strong_next|=1<<dops[i].rt1;
8062d65a 4256 break;
4257 }
4258 // fallthrough
4259 case SHIFT:
4260 case LOADLR:
4261 case MOV:
cf95b4f0 4262 smrv_strong_next&=~(1<<dops[i].rt1);
4263 smrv_weak_next&=~(1<<dops[i].rt1);
8062d65a 4264 break;
4265 case COP0:
4266 case COP2:
cf95b4f0 4267 if(dops[i].opcode2==0||dops[i].opcode2==2) { // MFC/CFC
4268 smrv_strong_next&=~(1<<dops[i].rt1);
4269 smrv_weak_next&=~(1<<dops[i].rt1);
8062d65a 4270 }
4271 break;
4272 case C2LS:
cf95b4f0 4273 if (dops[i].opcode==0x32) { // LWC2
4274 smrv_strong_next&=~(1<<dops[i].rt1);
4275 smrv_weak_next&=~(1<<dops[i].rt1);
8062d65a 4276 }
4277 break;
4278 }
4279#if 0
4280 int r=4;
4281 printf("x %08x %08x %d %d c %08x %08x\n",smrv[r],start+i*4,
4282 ((smrv_strong>>r)&1),(smrv_weak>>r)&1,regs[i].isconst,regs[i].wasconst);
4283#endif
4284}
4285
2330734f 4286static void ujump_assemble(int i, const struct regstat *i_regs);
4287static void rjump_assemble(int i, const struct regstat *i_regs);
4288static void cjump_assemble(int i, const struct regstat *i_regs);
4289static void sjump_assemble(int i, const struct regstat *i_regs);
2330734f 4290
4291static int assemble(int i, const struct regstat *i_regs, int ccadj_)
57871462 4292{
2330734f 4293 int ds = 0;
4294 switch (dops[i].itype) {
57871462 4295 case ALU:
a5cd72d0 4296 alu_assemble(i, i_regs, ccadj_);
2330734f 4297 break;
57871462 4298 case IMM16:
a5cd72d0 4299 imm16_assemble(i, i_regs, ccadj_);
2330734f 4300 break;
57871462 4301 case SHIFT:
2330734f 4302 shift_assemble(i, i_regs);
4303 break;
57871462 4304 case SHIFTIMM:
2330734f 4305 shiftimm_assemble(i, i_regs);
4306 break;
57871462 4307 case LOAD:
2330734f 4308 load_assemble(i, i_regs, ccadj_);
4309 break;
57871462 4310 case LOADLR:
2330734f 4311 loadlr_assemble(i, i_regs, ccadj_);
4312 break;
57871462 4313 case STORE:
2330734f 4314 store_assemble(i, i_regs, ccadj_);
4315 break;
57871462 4316 case STORELR:
2330734f 4317 storelr_assemble(i, i_regs, ccadj_);
4318 break;
57871462 4319 case COP0:
2330734f 4320 cop0_assemble(i, i_regs, ccadj_);
4321 break;
a5cd72d0 4322 case RFE:
277718fa 4323 rfe_assemble(i, i_regs);
2330734f 4324 break;
b9b61529 4325 case COP2:
2330734f 4326 cop2_assemble(i, i_regs);
4327 break;
b9b61529 4328 case C2LS:
2330734f 4329 c2ls_assemble(i, i_regs, ccadj_);
4330 break;
b9b61529 4331 case C2OP:
2330734f 4332 c2op_assemble(i, i_regs);
4333 break;
57871462 4334 case MULTDIV:
2330734f 4335 multdiv_assemble(i, i_regs);
4336 multdiv_prepare_stall(i, i_regs, ccadj_);
32631e6a 4337 break;
57871462 4338 case MOV:
2330734f 4339 mov_assemble(i, i_regs);
4340 break;
4341 case SYSCALL:
a5cd72d0 4342 exception_assemble(i, i_regs, ccadj_);
2330734f 4343 break;
4344 case HLECALL:
4345 hlecall_assemble(i, i_regs, ccadj_);
4346 break;
4347 case INTCALL:
4348 intcall_assemble(i, i_regs, ccadj_);
4349 break;
4350 case UJUMP:
4351 ujump_assemble(i, i_regs);
4352 ds = 1;
4353 break;
4354 case RJUMP:
4355 rjump_assemble(i, i_regs);
4356 ds = 1;
4357 break;
4358 case CJUMP:
4359 cjump_assemble(i, i_regs);
4360 ds = 1;
4361 break;
4362 case SJUMP:
4363 sjump_assemble(i, i_regs);
4364 ds = 1;
4365 break;
24058131 4366 case NOP:
2330734f 4367 case OTHER:
2330734f 4368 // not handled, just skip
4369 break;
4370 default:
4371 assert(0);
4372 }
4373 return ds;
4374}
4375
4376static void ds_assemble(int i, const struct regstat *i_regs)
4377{
4378 speculate_register_values(i);
4379 is_delayslot = 1;
4380 switch (dops[i].itype) {
57871462 4381 case SYSCALL:
7139f3c8 4382 case HLECALL:
1e973cb0 4383 case INTCALL:
57871462 4384 case UJUMP:
4385 case RJUMP:
4386 case CJUMP:
4387 case SJUMP:
c43b5311 4388 SysPrintf("Jump in the delay slot. This is probably a bug.\n");
2330734f 4389 break;
4390 default:
277718fa 4391 assemble(i, i_regs, cinfo[i].ccadj);
57871462 4392 }
2330734f 4393 is_delayslot = 0;
57871462 4394}
4395
4396// Is the branch target a valid internal jump?
ad49de89 4397static int internal_branch(int addr)
57871462 4398{
4399 if(addr&1) return 0; // Indirect (register) jump
4400 if(addr>=start && addr<start+slen*4-4)
4401 {
71e490c5 4402 return 1;
57871462 4403 }
4404 return 0;
4405}
4406
ad49de89 4407static void wb_invalidate(signed char pre[],signed char entry[],uint64_t dirty,uint64_t u)
57871462 4408{
4409 int hr;
4410 for(hr=0;hr<HOST_REGS;hr++) {
4411 if(hr!=EXCLUDE_REG) {
4412 if(pre[hr]!=entry[hr]) {
4413 if(pre[hr]>=0) {
4414 if((dirty>>hr)&1) {
4415 if(get_reg(entry,pre[hr])<0) {
00fa9369 4416 assert(pre[hr]<64);
4417 if(!((u>>pre[hr])&1))
4418 emit_storereg(pre[hr],hr);
57871462 4419 }
4420 }
4421 }
4422 }
4423 }
4424 }
4425 // Move from one register to another (no writeback)
4426 for(hr=0;hr<HOST_REGS;hr++) {
4427 if(hr!=EXCLUDE_REG) {
4428 if(pre[hr]!=entry[hr]) {
9de8a0c3 4429 if(pre[hr]>=0&&pre[hr]<TEMPREG) {
57871462 4430 int nr;
4431 if((nr=get_reg(entry,pre[hr]))>=0) {
4432 emit_mov(hr,nr);
4433 }
4434 }
4435 }
4436 }
4437 }
4438}
57871462 4439
4440// Load the specified registers
4441// This only loads the registers given as arguments because
4442// we don't want to load things that will be overwritten
53358c1d 4443static inline void load_reg(signed char entry[], signed char regmap[], int rs)
57871462 4444{
53358c1d 4445 int hr = get_reg(regmap, rs);
4446 if (hr >= 0 && entry[hr] != regmap[hr])
4447 emit_loadreg(regmap[hr], hr);
4448}
4449
4450static void load_regs(signed char entry[], signed char regmap[], int rs1, int rs2)
4451{
4452 load_reg(entry, regmap, rs1);
4453 if (rs1 != rs2)
4454 load_reg(entry, regmap, rs2);
57871462 4455}
4456
4457// Load registers prior to the start of a loop
4458// so that they are not loaded within the loop
4459static void loop_preload(signed char pre[],signed char entry[])
4460{
4461 int hr;
53358c1d 4462 for (hr = 0; hr < HOST_REGS; hr++) {
4463 int r = entry[hr];
4464 if (r >= 0 && pre[hr] != r && get_reg(pre, r) < 0) {
4465 assem_debug("loop preload:\n");
4466 if (r < TEMPREG)
4467 emit_loadreg(r, hr);
57871462 4468 }
4469 }
4470}
4471
4472// Generate address for load/store instruction
277718fa 4473// goes to AGEN (or temp) for writes, FTEMP for LOADLR and cop1/2 loads
4474// AGEN is assigned by pass5b_preallocate2
4149788d 4475static void address_generation(int i, const struct regstat *i_regs, signed char entry[])
57871462 4476{
37387d8b 4477 if (dops[i].is_load || dops[i].is_store) {
277718fa 4478 int ra = -1;
4479 int agr = AGEN1 + (i&1);
cf95b4f0 4480 if(dops[i].itype==LOAD) {
277718fa 4481 if (!dops[i].may_except)
4482 ra = get_reg_w(i_regs->regmap, dops[i].rt1); // reuse dest for agen
4483 if (ra < 0)
4484 ra = get_reg_temp(i_regs->regmap);
57871462 4485 }
cf95b4f0 4486 if(dops[i].itype==LOADLR) {
57871462 4487 ra=get_reg(i_regs->regmap,FTEMP);
4488 }
cf95b4f0 4489 if(dops[i].itype==STORE||dops[i].itype==STORELR) {
57871462 4490 ra=get_reg(i_regs->regmap,agr);
9de8a0c3 4491 if(ra<0) ra=get_reg_temp(i_regs->regmap);
57871462 4492 }
37387d8b 4493 if(dops[i].itype==C2LS) {
277718fa 4494 if (dops[i].opcode == 0x32) // LWC2
57871462 4495 ra=get_reg(i_regs->regmap,FTEMP);
277718fa 4496 else { // SWC2
57871462 4497 ra=get_reg(i_regs->regmap,agr);
9de8a0c3 4498 if(ra<0) ra=get_reg_temp(i_regs->regmap);
57871462 4499 }
4500 }
277718fa 4501 int rs = get_reg(i_regs->regmap, dops[i].rs1);
4502 //if(ra>=0)
4503 {
4504 int offset = cinfo[i].imm;
4505 int add_offset = offset != 0;
33a1eda1 4506 int c = rs >= 0 && ((i_regs->wasconst >> rs) & 1);
cf95b4f0 4507 if(dops[i].rs1==0) {
57871462 4508 // Using r0 as a base address
277718fa 4509 assert(ra >= 0);
57871462 4510 if(!entry||entry[ra]!=agr) {
cf95b4f0 4511 if (dops[i].opcode==0x22||dops[i].opcode==0x26) {
57871462 4512 emit_movimm(offset&0xFFFFFFFC,ra); // LWL/LWR
57871462 4513 }else{
4514 emit_movimm(offset,ra);
4515 }
4516 } // else did it in the previous cycle
277718fa 4517 cinfo[i].addr = ra;
4518 add_offset = 0;
4519 }
4520 else if (rs < 0) {
4521 assert(ra >= 0);
4522 if (!entry || entry[ra] != dops[i].rs1)
4523 emit_loadreg(dops[i].rs1, ra);
4524 cinfo[i].addr = ra;
cf95b4f0 4525 //if(!entry||entry[ra]!=dops[i].rs1)
57871462 4526 // printf("poor load scheduling!\n");
4527 }
4528 else if(c) {
cf95b4f0 4529 if(dops[i].rs1!=dops[i].rt1||dops[i].itype!=LOAD) {
277718fa 4530 assert(ra >= 0);
57871462 4531 if(!entry||entry[ra]!=agr) {
cf95b4f0 4532 if (dops[i].opcode==0x22||dops[i].opcode==0x26) {
57871462 4533 emit_movimm((constmap[i][rs]+offset)&0xFFFFFFFC,ra); // LWL/LWR
57871462 4534 }else{
57871462 4535 emit_movimm(constmap[i][rs]+offset,ra);
8575a877 4536 regs[i].loadedconst|=1<<ra;
57871462 4537 }
4538 } // else did it in the previous cycle
277718fa 4539 cinfo[i].addr = ra;
4540 }
4541 else // else load_consts already did it
4542 cinfo[i].addr = rs;
4543 add_offset = 0;
57871462 4544 }
277718fa 4545 else
4546 cinfo[i].addr = rs;
4547 if (add_offset) {
4548 assert(ra >= 0);
57871462 4549 if(rs>=0) {
4550 emit_addimm(rs,offset,ra);
4551 }else{
4552 emit_addimm(ra,offset,ra);
4553 }
277718fa 4554 cinfo[i].addr = ra;
57871462 4555 }
4556 }
277718fa 4557 assert(cinfo[i].addr >= 0);
57871462 4558 }
4559 // Preload constants for next instruction
37387d8b 4560 if (dops[i+1].is_load || dops[i+1].is_store) {
57871462 4561 int agr,ra;
57871462 4562 // Actual address
4563 agr=AGEN1+((i+1)&1);
4564 ra=get_reg(i_regs->regmap,agr);
4565 if(ra>=0) {
cf95b4f0 4566 int rs=get_reg(regs[i+1].regmap,dops[i+1].rs1);
277718fa 4567 int offset=cinfo[i+1].imm;
57871462 4568 int c=(regs[i+1].wasconst>>rs)&1;
cf95b4f0 4569 if(c&&(dops[i+1].rs1!=dops[i+1].rt1||dops[i+1].itype!=LOAD)) {
4570 if (dops[i+1].opcode==0x22||dops[i+1].opcode==0x26) {
57871462 4571 emit_movimm((constmap[i+1][rs]+offset)&0xFFFFFFFC,ra); // LWL/LWR
cf95b4f0 4572 }else if (dops[i+1].opcode==0x1a||dops[i+1].opcode==0x1b) {
57871462 4573 emit_movimm((constmap[i+1][rs]+offset)&0xFFFFFFF8,ra); // LDL/LDR
4574 }else{
57871462 4575 emit_movimm(constmap[i+1][rs]+offset,ra);
8575a877 4576 regs[i+1].loadedconst|=1<<ra;
57871462 4577 }
4578 }
cf95b4f0 4579 else if(dops[i+1].rs1==0) {
57871462 4580 // Using r0 as a base address
cf95b4f0 4581 if (dops[i+1].opcode==0x22||dops[i+1].opcode==0x26) {
57871462 4582 emit_movimm(offset&0xFFFFFFFC,ra); // LWL/LWR
cf95b4f0 4583 }else if (dops[i+1].opcode==0x1a||dops[i+1].opcode==0x1b) {
57871462 4584 emit_movimm(offset&0xFFFFFFF8,ra); // LDL/LDR
4585 }else{
4586 emit_movimm(offset,ra);
4587 }
4588 }
4589 }
4590 }
4591}
4592
de6dbc52 4593static int get_final_value(int hr, int i, u_int *value)
57871462 4594{
4595 int reg=regs[i].regmap[hr];
4596 while(i<slen-1) {
4597 if(regs[i+1].regmap[hr]!=reg) break;
4598 if(!((regs[i+1].isconst>>hr)&1)) break;
cf95b4f0 4599 if(dops[i+1].bt) break;
57871462 4600 i++;
4601 }
4602 if(i<slen-1) {
fe807a8a 4603 if (dops[i].is_jump) {
57871462 4604 *value=constmap[i][hr];
4605 return 1;
4606 }
cf95b4f0 4607 if(!dops[i+1].bt) {
fe807a8a 4608 if (dops[i+1].is_jump) {
57871462 4609 // Load in delay slot, out-of-order execution
cf95b4f0 4610 if(dops[i+2].itype==LOAD&&dops[i+2].rs1==reg&&dops[i+2].rt1==reg&&((regs[i+1].wasconst>>hr)&1))
57871462 4611 {
57871462 4612 // Precompute load address
277718fa 4613 *value=constmap[i][hr]+cinfo[i+2].imm;
57871462 4614 return 1;
4615 }
4616 }
cf95b4f0 4617 if(dops[i+1].itype==LOAD&&dops[i+1].rs1==reg&&dops[i+1].rt1==reg)
57871462 4618 {
57871462 4619 // Precompute load address
277718fa 4620 *value=constmap[i][hr]+cinfo[i+1].imm;
4621 //printf("c=%x imm=%lx\n",(long)constmap[i][hr],cinfo[i+1].imm);
57871462 4622 return 1;
4623 }
4624 }
4625 }
4626 *value=constmap[i][hr];
643aeae3 4627 //printf("c=%lx\n",(long)constmap[i][hr]);
57871462 4628 if(i==slen-1) return 1;
00fa9369 4629 assert(reg < 64);
4630 return !((unneeded_reg[i+1]>>reg)&1);
57871462 4631}
4632
4633// Load registers with known constants
ad49de89 4634static void load_consts(signed char pre[],signed char regmap[],int i)
57871462 4635{
8575a877 4636 int hr,hr2;
4637 // propagate loaded constant flags
cf95b4f0 4638 if(i==0||dops[i].bt)
8575a877 4639 regs[i].loadedconst=0;
4640 else {
684b6816 4641 for (hr = 0; hr < HOST_REGS; hr++) {
4642 if (hr == EXCLUDE_REG || regmap[hr] < 0 || pre[hr] != regmap[hr])
4643 continue;
4644 if ((((regs[i-1].isconst & regs[i-1].loadedconst) >> hr) & 1)
4645 && regmap[hr] == regs[i-1].regmap[hr])
8575a877 4646 {
684b6816 4647 regs[i].loadedconst |= 1u << hr;
8575a877 4648 }
4649 }
4650 }
57871462 4651 // Load 32-bit regs
4652 for(hr=0;hr<HOST_REGS;hr++) {
4653 if(hr!=EXCLUDE_REG&&regmap[hr]>=0) {
4654 //if(entry[hr]!=regmap[hr]) {
8575a877 4655 if(!((regs[i].loadedconst>>hr)&1)) {
ad49de89 4656 assert(regmap[hr]<64);
4657 if(((regs[i].isconst>>hr)&1)&&regmap[hr]>0) {
de6dbc52 4658 u_int value, similar=0;
57871462 4659 if(get_final_value(hr,i,&value)) {
8575a877 4660 // see if some other register has similar value
4661 for(hr2=0;hr2<HOST_REGS;hr2++) {
4662 if(hr2!=EXCLUDE_REG&&((regs[i].loadedconst>>hr2)&1)) {
4663 if(is_similar_value(value,constmap[i][hr2])) {
4664 similar=1;
4665 break;
4666 }
4667 }
4668 }
4669 if(similar) {
de6dbc52 4670 u_int value2;
8575a877 4671 if(get_final_value(hr2,i,&value2)) // is this needed?
4672 emit_movimm_from(value2,hr2,value,hr);
4673 else
4674 emit_movimm(value,hr);
4675 }
4676 else if(value==0) {
57871462 4677 emit_zeroreg(hr);
4678 }
4679 else {
4680 emit_movimm(value,hr);
4681 }
4682 }
8575a877 4683 regs[i].loadedconst|=1<<hr;
57871462 4684 }
4685 }
4686 }
4687 }
57871462 4688}
ad49de89 4689
2330734f 4690static void load_all_consts(const signed char regmap[], u_int dirty, int i)
57871462 4691{
4692 int hr;
4693 // Load 32-bit regs
4694 for(hr=0;hr<HOST_REGS;hr++) {
4695 if(hr!=EXCLUDE_REG&&regmap[hr]>=0&&((dirty>>hr)&1)) {
ad49de89 4696 assert(regmap[hr] < 64);
4697 if(((regs[i].isconst>>hr)&1)&&regmap[hr]>0) {
57871462 4698 int value=constmap[i][hr];
4699 if(value==0) {
4700 emit_zeroreg(hr);
4701 }
4702 else {
4703 emit_movimm(value,hr);
4704 }
4705 }
4706 }
4707 }
57871462 4708}
4709
4710// Write out all dirty registers (except cycle count)
a22ccd6a 4711#ifndef wb_dirtys
4712static void wb_dirtys(const signed char i_regmap[], u_int i_dirty)
57871462 4713{
4714 int hr;
4715 for(hr=0;hr<HOST_REGS;hr++) {
4716 if(hr!=EXCLUDE_REG) {
4717 if(i_regmap[hr]>0) {
4718 if(i_regmap[hr]!=CCREG) {
4719 if((i_dirty>>hr)&1) {
00fa9369 4720 assert(i_regmap[hr]<64);
4721 emit_storereg(i_regmap[hr],hr);
57871462 4722 }
4723 }
4724 }
4725 }
4726 }
4727}
a22ccd6a 4728#endif
ad49de89 4729
57871462 4730// Write out dirty registers that we need to reload (pair with load_needed_regs)
4731// This writes the registers not written by store_regs_bt
a22ccd6a 4732static void wb_needed_dirtys(const signed char i_regmap[], u_int i_dirty, int addr)
57871462 4733{
4734 int hr;
4735 int t=(addr-start)>>2;
4736 for(hr=0;hr<HOST_REGS;hr++) {
4737 if(hr!=EXCLUDE_REG) {
4738 if(i_regmap[hr]>0) {
4739 if(i_regmap[hr]!=CCREG) {
ad49de89 4740 if(i_regmap[hr]==regs[t].regmap_entry[hr] && ((regs[t].dirty>>hr)&1)) {
57871462 4741 if((i_dirty>>hr)&1) {
00fa9369 4742 assert(i_regmap[hr]<64);
4743 emit_storereg(i_regmap[hr],hr);
57871462 4744 }
4745 }
4746 }
4747 }
4748 }
4749 }
4750}
4751
4752// Load all registers (except cycle count)
a22ccd6a 4753#ifndef load_all_regs
2330734f 4754static void load_all_regs(const signed char i_regmap[])
57871462 4755{
4756 int hr;
4757 for(hr=0;hr<HOST_REGS;hr++) {
4758 if(hr!=EXCLUDE_REG) {
4759 if(i_regmap[hr]==0) {
4760 emit_zeroreg(hr);
4761 }
4762 else
9de8a0c3 4763 if(i_regmap[hr]>0 && i_regmap[hr]<TEMPREG && i_regmap[hr]!=CCREG)
57871462 4764 {
4765 emit_loadreg(i_regmap[hr],hr);
4766 }
4767 }
4768 }
4769}
a22ccd6a 4770#endif
57871462 4771
4772// Load all current registers also needed by next instruction
2330734f 4773static void load_needed_regs(const signed char i_regmap[], const signed char next_regmap[])
57871462 4774{
a22ccd6a 4775 signed char regmap_sel[HOST_REGS];
57871462 4776 int hr;
a22ccd6a 4777 for (hr = 0; hr < HOST_REGS; hr++) {
4778 regmap_sel[hr] = -1;
4779 if (hr != EXCLUDE_REG)
4780 if (next_regmap[hr] == i_regmap[hr] || get_reg(next_regmap, i_regmap[hr]) >= 0)
4781 regmap_sel[hr] = i_regmap[hr];
57871462 4782 }
a22ccd6a 4783 load_all_regs(regmap_sel);
57871462 4784}
4785
4786// Load all regs, storing cycle count if necessary
2330734f 4787static void load_regs_entry(int t)
57871462 4788{
cf95b4f0 4789 if(dops[t].is_ds) emit_addimm(HOST_CCREG,CLOCK_ADJUST(1),HOST_CCREG);
277718fa 4790 else if(cinfo[t].ccadj) emit_addimm(HOST_CCREG,-cinfo[t].ccadj,HOST_CCREG);
57871462 4791 if(regs[t].regmap_entry[HOST_CCREG]!=CCREG) {
4792 emit_storereg(CCREG,HOST_CCREG);
4793 }
a22ccd6a 4794 load_all_regs(regs[t].regmap_entry);
57871462 4795}
4796
4797// Store dirty registers prior to branch
4149788d 4798static void store_regs_bt(signed char i_regmap[],uint64_t i_dirty,int addr)
57871462 4799{
ad49de89 4800 if(internal_branch(addr))
57871462 4801 {
4802 int t=(addr-start)>>2;
4803 int hr;
4804 for(hr=0;hr<HOST_REGS;hr++) {
4805 if(hr!=EXCLUDE_REG) {
4806 if(i_regmap[hr]>0 && i_regmap[hr]!=CCREG) {
ad49de89 4807 if(i_regmap[hr]!=regs[t].regmap_entry[hr] || !((regs[t].dirty>>hr)&1)) {
57871462 4808 if((i_dirty>>hr)&1) {
00fa9369 4809 assert(i_regmap[hr]<64);
4810 if(!((unneeded_reg[t]>>i_regmap[hr])&1))
4811 emit_storereg(i_regmap[hr],hr);
57871462 4812 }
4813 }
4814 }
4815 }
4816 }
4817 }
4818 else
4819 {
4820 // Branch out of this block, write out all dirty regs
ad49de89 4821 wb_dirtys(i_regmap,i_dirty);
57871462 4822 }
4823}
4824
4825// Load all needed registers for branch target
ad49de89 4826static void load_regs_bt(signed char i_regmap[],uint64_t i_dirty,int addr)
57871462 4827{
4828 //if(addr>=start && addr<(start+slen*4))
ad49de89 4829 if(internal_branch(addr))
57871462 4830 {
4831 int t=(addr-start)>>2;
4832 int hr;
4833 // Store the cycle count before loading something else
4834 if(i_regmap[HOST_CCREG]!=CCREG) {
4835 assert(i_regmap[HOST_CCREG]==-1);
4836 }
4837 if(regs[t].regmap_entry[HOST_CCREG]!=CCREG) {
4838 emit_storereg(CCREG,HOST_CCREG);
4839 }
4840 // Load 32-bit regs
4841 for(hr=0;hr<HOST_REGS;hr++) {
ea3d2e6e 4842 if(hr!=EXCLUDE_REG&&regs[t].regmap_entry[hr]>=0&&regs[t].regmap_entry[hr]<TEMPREG) {
00fa9369 4843 if(i_regmap[hr]!=regs[t].regmap_entry[hr]) {
57871462 4844 if(regs[t].regmap_entry[hr]==0) {
4845 emit_zeroreg(hr);
4846 }
4847 else if(regs[t].regmap_entry[hr]!=CCREG)
4848 {
4849 emit_loadreg(regs[t].regmap_entry[hr],hr);
4850 }
4851 }
4852 }
4853 }
57871462 4854 }
4855}
4856
ad49de89 4857static int match_bt(signed char i_regmap[],uint64_t i_dirty,int addr)
57871462 4858{
4859 if(addr>=start && addr<start+slen*4-4)
4860 {
4861 int t=(addr-start)>>2;
4862 int hr;
4863 if(regs[t].regmap_entry[HOST_CCREG]!=CCREG) return 0;
4864 for(hr=0;hr<HOST_REGS;hr++)
4865 {
4866 if(hr!=EXCLUDE_REG)
4867 {
4868 if(i_regmap[hr]!=regs[t].regmap_entry[hr])
4869 {
ea3d2e6e 4870 if(regs[t].regmap_entry[hr]>=0&&(regs[t].regmap_entry[hr]|64)<TEMPREG+64)
57871462 4871 {
4872 return 0;
4873 }
9f51b4b9 4874 else
57871462 4875 if((i_dirty>>hr)&1)
4876 {
ea3d2e6e 4877 if(i_regmap[hr]<TEMPREG)
57871462 4878 {
4879 if(!((unneeded_reg[t]>>i_regmap[hr])&1))
4880 return 0;
4881 }
ea3d2e6e 4882 else if(i_regmap[hr]>=64&&i_regmap[hr]<TEMPREG+64)
57871462 4883 {
00fa9369 4884 assert(0);
57871462 4885 }
4886 }
4887 }
4888 else // Same register but is it 32-bit or dirty?
4889 if(i_regmap[hr]>=0)
4890 {
4891 if(!((regs[t].dirty>>hr)&1))
4892 {
4893 if((i_dirty>>hr)&1)
4894 {
4895 if(!((unneeded_reg[t]>>i_regmap[hr])&1))
4896 {
4897 //printf("%x: dirty no match\n",addr);
4898 return 0;
4899 }
4900 }
4901 }
57871462 4902 }
4903 }
4904 }
57871462 4905 // Delay slots are not valid branch targets
fe807a8a 4906 //if(t>0&&(dops[t-1].is_jump) return 0;
57871462 4907 // Delay slots require additional processing, so do not match
cf95b4f0 4908 if(dops[t].is_ds) return 0;
57871462 4909 }
4910 else
4911 {
4912 int hr;
4913 for(hr=0;hr<HOST_REGS;hr++)
4914 {
4915 if(hr!=EXCLUDE_REG)
4916 {
4917 if(i_regmap[hr]>=0)
4918 {
4919 if(hr!=HOST_CCREG||i_regmap[hr]!=CCREG)
4920 {
4921 if((i_dirty>>hr)&1)
4922 {
4923 return 0;
4924 }
4925 }
4926 }
4927 }
4928 }
4929 }
4930 return 1;
4931}
4932
dd114d7d 4933#ifdef DRC_DBG
2330734f 4934static void drc_dbg_emit_do_cmp(int i, int ccadj_)
dd114d7d 4935{
4936 extern void do_insn_cmp();
3968e69e 4937 //extern int cycle;
81dbbf4c 4938 u_int hr, reglist = get_host_reglist(regs[i].regmap);
33a1eda1 4939 reglist |= get_host_reglist(regs[i].regmap_entry);
4940 reglist &= DRC_DBG_REGMASK;
dd114d7d 4941
40fca85b 4942 assem_debug("//do_insn_cmp %08x\n", start+i*4);
dd114d7d 4943 save_regs(reglist);
40fca85b 4944 // write out changed consts to match the interpreter
cf95b4f0 4945 if (i > 0 && !dops[i].bt) {
40fca85b 4946 for (hr = 0; hr < HOST_REGS; hr++) {
2330734f 4947 int reg = regs[i].regmap_entry[hr]; // regs[i-1].regmap[hr];
277718fa 4948 if (hr == EXCLUDE_REG || reg <= 0)
40fca85b 4949 continue;
4950 if (!((regs[i-1].isconst >> hr) & 1))
4951 continue;
4952 if (i > 1 && reg == regs[i-2].regmap[hr] && constmap[i-1][hr] == constmap[i-2][hr])
4953 continue;
4954 emit_movimm(constmap[i-1][hr],0);
4955 emit_storereg(reg, 0);
4956 }
4957 }
dd114d7d 4958 emit_movimm(start+i*4,0);
643aeae3 4959 emit_writeword(0,&pcaddr);
2330734f 4960 int cc = get_reg(regs[i].regmap_entry, CCREG);
4961 if (cc < 0)
4962 emit_loadreg(CCREG, cc = 0);
4963 emit_addimm(cc, ccadj_, 0);
4964 emit_writeword(0, &psxRegs.cycle);
2a014d73 4965 emit_far_call(do_insn_cmp);
643aeae3 4966 //emit_readword(&cycle,0);
dd114d7d 4967 //emit_addimm(0,2,0);
643aeae3 4968 //emit_writeword(0,&cycle);
3968e69e 4969 (void)get_reg2;
dd114d7d 4970 restore_regs(reglist);
40fca85b 4971 assem_debug("\\\\do_insn_cmp\n");
dd114d7d 4972}
4973#else
2330734f 4974#define drc_dbg_emit_do_cmp(x,y)
dd114d7d 4975#endif
4976
57871462 4977// Used when a branch jumps into the delay slot of another branch
7c3a5182 4978static void ds_assemble_entry(int i)
57871462 4979{
277718fa 4980 int t = (cinfo[i].ba - start) >> 2;
2330734f 4981 int ccadj_ = -CLOCK_ADJUST(1);
df4dc2b1 4982 if (!instr_addr[t])
4983 instr_addr[t] = out;
277718fa 4984 assem_debug("Assemble delay slot at %x\n",cinfo[i].ba);
57871462 4985 assem_debug("<->\n");
2330734f 4986 drc_dbg_emit_do_cmp(t, ccadj_);
57871462 4987 if(regs[t].regmap_entry[HOST_CCREG]==CCREG&&regs[t].regmap[HOST_CCREG]!=CCREG)
ad49de89 4988 wb_register(CCREG,regs[t].regmap_entry,regs[t].wasdirty);
cf95b4f0 4989 load_regs(regs[t].regmap_entry,regs[t].regmap,dops[t].rs1,dops[t].rs2);
57871462 4990 address_generation(t,&regs[t],regs[t].regmap_entry);
37387d8b 4991 if (ram_offset && (dops[t].is_load || dops[t].is_store))
53358c1d 4992 load_reg(regs[t].regmap_entry,regs[t].regmap,ROREG);
37387d8b 4993 if (dops[t].is_store)
53358c1d 4994 load_reg(regs[t].regmap_entry,regs[t].regmap,INVCP);
57871462 4995 is_delayslot=0;
2330734f 4996 switch (dops[t].itype) {
57871462 4997 case SYSCALL:
7139f3c8 4998 case HLECALL:
1e973cb0 4999 case INTCALL:
57871462 5000 case UJUMP:
5001 case RJUMP:
5002 case CJUMP:
5003 case SJUMP:
c43b5311 5004 SysPrintf("Jump in the delay slot. This is probably a bug.\n");
2330734f 5005 break;
5006 default:
5007 assemble(t, &regs[t], ccadj_);
57871462 5008 }
277718fa 5009 store_regs_bt(regs[t].regmap,regs[t].dirty,cinfo[i].ba+4);
5010 load_regs_bt(regs[t].regmap,regs[t].dirty,cinfo[i].ba+4);
5011 if(internal_branch(cinfo[i].ba+4))
57871462 5012 assem_debug("branch: internal\n");
5013 else
5014 assem_debug("branch: external\n");
277718fa 5015 assert(internal_branch(cinfo[i].ba+4));
5016 add_to_linker(out,cinfo[i].ba+4,internal_branch(cinfo[i].ba+4));
57871462 5017 emit_jmp(0);
5018}
5019
d1e4ebd9 5020// Load 2 immediates optimizing for small code size
5021static void emit_mov2imm_compact(int imm1,u_int rt1,int imm2,u_int rt2)
5022{
5023 emit_movimm(imm1,rt1);
5024 emit_movimm_from(imm1,rt1,imm2,rt2);
5025}
5026
2330734f 5027static void do_cc(int i, const signed char i_regmap[], int *adj,
5028 int addr, int taken, int invert)
57871462 5029{
2330734f 5030 int count, count_plus2;
b14b6a8f 5031 void *jaddr;
5032 void *idle=NULL;
b6e87b2b 5033 int t=0;
cf95b4f0 5034 if(dops[i].itype==RJUMP)
57871462 5035 {
5036 *adj=0;
5037 }
277718fa 5038 //if(cinfo[i].ba>=start && cinfo[i].ba<(start+slen*4))
5039 if(internal_branch(cinfo[i].ba))
57871462 5040 {
277718fa 5041 t=(cinfo[i].ba-start)>>2;
2330734f 5042 if(dops[t].is_ds) *adj=-CLOCK_ADJUST(1); // Branch into delay slot adds an extra cycle
277718fa 5043 else *adj=cinfo[t].ccadj;
57871462 5044 }
5045 else
5046 {
5047 *adj=0;
5048 }
277718fa 5049 count = cinfo[i].ccadj;
2330734f 5050 count_plus2 = count + CLOCK_ADJUST(2);
277718fa 5051 if(taken==TAKEN && i==(cinfo[i].ba-start)>>2 && source[i+1]==0) {
57871462 5052 // Idle loop
5053 if(count&1) emit_addimm_and_set_flags(2*(count+2),HOST_CCREG);
b14b6a8f 5054 idle=out;
57871462 5055 //emit_subfrommem(&idlecount,HOST_CCREG); // Count idle cycles
5056 emit_andimm(HOST_CCREG,3,HOST_CCREG);
b14b6a8f 5057 jaddr=out;
57871462 5058 emit_jmp(0);
5059 }
5060 else if(*adj==0||invert) {
2330734f 5061 int cycles = count_plus2;
b6e87b2b 5062 // faster loop HACK
bb4f300c 5063#if 0
b6e87b2b 5064 if (t&&*adj) {
5065 int rel=t-i;
5066 if(-NO_CYCLE_PENALTY_THR<rel&&rel<0)
2330734f 5067 cycles=*adj+count+2-*adj;
b6e87b2b 5068 }
bb4f300c 5069#endif
2330734f 5070 emit_addimm_and_set_flags(cycles, HOST_CCREG);
5071 jaddr = out;
57871462 5072 emit_jns(0);
5073 }
5074 else
5075 {
2330734f 5076 emit_cmpimm(HOST_CCREG, -count_plus2);
5077 jaddr = out;
57871462 5078 emit_jns(0);
5079 }
2330734f 5080 add_stub(CC_STUB,jaddr,idle?idle:out,(*adj==0||invert||idle)?0:count_plus2,i,addr,taken,0);
57871462 5081}
5082
b14b6a8f 5083static void do_ccstub(int n)
57871462 5084{
5085 literal_pool(256);
d1e4ebd9 5086 assem_debug("do_ccstub %x\n",start+(u_int)stubs[n].b*4);
b14b6a8f 5087 set_jump_target(stubs[n].addr, out);
5088 int i=stubs[n].b;
33a1eda1 5089 if (stubs[n].d != TAKEN) {
ad49de89 5090 wb_dirtys(branch_regs[i].regmap,branch_regs[i].dirty);
57871462 5091 }
5092 else {
277718fa 5093 if(internal_branch(cinfo[i].ba))
5094 wb_needed_dirtys(branch_regs[i].regmap,branch_regs[i].dirty,cinfo[i].ba);
57871462 5095 }
b14b6a8f 5096 if(stubs[n].c!=-1)
57871462 5097 {
5098 // Save PC as return address
6d75addf 5099 emit_movimm(stubs[n].c,0);
5100 emit_writeword(0,&pcaddr);
57871462 5101 }
5102 else
5103 {
5104 // Return address depends on which way the branch goes
cf95b4f0 5105 if(dops[i].itype==CJUMP||dops[i].itype==SJUMP)
57871462 5106 {
cf95b4f0 5107 int s1l=get_reg(branch_regs[i].regmap,dops[i].rs1);
5108 int s2l=get_reg(branch_regs[i].regmap,dops[i].rs2);
5109 if(dops[i].rs1==0)
57871462 5110 {
ad49de89 5111 s1l=s2l;
5112 s2l=-1;
57871462 5113 }
cf95b4f0 5114 else if(dops[i].rs2==0)
57871462 5115 {
ad49de89 5116 s2l=-1;
57871462 5117 }
5118 assert(s1l>=0);
5119 #ifdef DESTRUCTIVE_WRITEBACK
cf95b4f0 5120 if(dops[i].rs1) {
ad49de89 5121 if((branch_regs[i].dirty>>s1l)&&1)
cf95b4f0 5122 emit_loadreg(dops[i].rs1,s1l);
9f51b4b9 5123 }
57871462 5124 else {
ad49de89 5125 if((branch_regs[i].dirty>>s1l)&1)
cf95b4f0 5126 emit_loadreg(dops[i].rs2,s1l);
57871462 5127 }
5128 if(s2l>=0)
ad49de89 5129 if((branch_regs[i].dirty>>s2l)&1)
cf95b4f0 5130 emit_loadreg(dops[i].rs2,s2l);
57871462 5131 #endif
5132 int hr=0;
5194fb95 5133 int addr=-1,alt=-1,ntaddr=-1;
57871462 5134 while(hr<HOST_REGS)
5135 {
5136 if(hr!=EXCLUDE_REG && hr!=HOST_CCREG &&
9de8a0c3 5137 branch_regs[i].regmap[hr]!=dops[i].rs1 &&
5138 branch_regs[i].regmap[hr]!=dops[i].rs2 )
57871462 5139 {
5140 addr=hr++;break;
5141 }
5142 hr++;
5143 }
5144 while(hr<HOST_REGS)
5145 {
5146 if(hr!=EXCLUDE_REG && hr!=HOST_CCREG &&
9de8a0c3 5147 branch_regs[i].regmap[hr]!=dops[i].rs1 &&
5148 branch_regs[i].regmap[hr]!=dops[i].rs2 )
57871462 5149 {
5150 alt=hr++;break;
5151 }
5152 hr++;
5153 }
ecca05e3 5154 if ((dops[i].opcode & 0x3e) == 6) // BLEZ/BGTZ needs another register
57871462 5155 {
5156 while(hr<HOST_REGS)
5157 {
5158 if(hr!=EXCLUDE_REG && hr!=HOST_CCREG &&
9de8a0c3 5159 branch_regs[i].regmap[hr]!=dops[i].rs1 &&
5160 branch_regs[i].regmap[hr]!=dops[i].rs2 )
57871462 5161 {
5162 ntaddr=hr;break;
5163 }
5164 hr++;
5165 }
5166 assert(hr<HOST_REGS);
5167 }
ecca05e3 5168 if (dops[i].opcode == 4) // BEQ
57871462 5169 {
5170 #ifdef HAVE_CMOV_IMM
ad49de89 5171 if(s2l>=0) emit_cmp(s1l,s2l);
5172 else emit_test(s1l,s1l);
277718fa 5173 emit_cmov2imm_e_ne_compact(cinfo[i].ba,start+i*4+8,addr);
ad49de89 5174 #else
277718fa 5175 emit_mov2imm_compact(cinfo[i].ba,addr,start+i*4+8,alt);
ad49de89 5176 if(s2l>=0) emit_cmp(s1l,s2l);
5177 else emit_test(s1l,s1l);
5178 emit_cmovne_reg(alt,addr);
57871462 5179 #endif
57871462 5180 }
ecca05e3 5181 else if (dops[i].opcode == 5) // BNE
57871462 5182 {
5183 #ifdef HAVE_CMOV_IMM
ad49de89 5184 if(s2l>=0) emit_cmp(s1l,s2l);
5185 else emit_test(s1l,s1l);
277718fa 5186 emit_cmov2imm_e_ne_compact(start+i*4+8,cinfo[i].ba,addr);
ad49de89 5187 #else
277718fa 5188 emit_mov2imm_compact(start+i*4+8,addr,cinfo[i].ba,alt);
ad49de89 5189 if(s2l>=0) emit_cmp(s1l,s2l);
5190 else emit_test(s1l,s1l);
5191 emit_cmovne_reg(alt,addr);
57871462 5192 #endif
57871462 5193 }
ecca05e3 5194 else if (dops[i].opcode == 6) // BLEZ
57871462 5195 {
277718fa 5196 //emit_movimm(cinfo[i].ba,alt);
57871462 5197 //emit_movimm(start+i*4+8,addr);
277718fa 5198 emit_mov2imm_compact(cinfo[i].ba,alt,start+i*4+8,addr);
57871462 5199 emit_cmpimm(s1l,1);
57871462 5200 emit_cmovl_reg(alt,addr);
57871462 5201 }
ecca05e3 5202 else if (dops[i].opcode == 7) // BGTZ
57871462 5203 {
277718fa 5204 //emit_movimm(cinfo[i].ba,addr);
57871462 5205 //emit_movimm(start+i*4+8,ntaddr);
277718fa 5206 emit_mov2imm_compact(cinfo[i].ba,addr,start+i*4+8,ntaddr);
57871462 5207 emit_cmpimm(s1l,1);
57871462 5208 emit_cmovl_reg(ntaddr,addr);
57871462 5209 }
ecca05e3 5210 else if (dops[i].itype == SJUMP) // BLTZ/BGEZ
57871462 5211 {
277718fa 5212 //emit_movimm(cinfo[i].ba,alt);
57871462 5213 //emit_movimm(start+i*4+8,addr);
de6dbc52 5214 if (dops[i].rs1) {
5215 emit_mov2imm_compact(cinfo[i].ba,
5216 (dops[i].opcode2 & 1) ? addr : alt, start + i*4 + 8,
5217 (dops[i].opcode2 & 1) ? alt : addr);
5218 emit_test(s1l,s1l);
5219 emit_cmovs_reg(alt,addr);
5220 }
5221 else
5222 emit_movimm((dops[i].opcode2 & 1) ? cinfo[i].ba : start + i*4 + 8, addr);
57871462 5223 }
ecca05e3 5224 emit_writeword(addr, &pcaddr);
57871462 5225 }
5226 else
cf95b4f0 5227 if(dops[i].itype==RJUMP)
57871462 5228 {
cf95b4f0 5229 int r=get_reg(branch_regs[i].regmap,dops[i].rs1);
4919de1e 5230 if (ds_writes_rjump_rs(i)) {
57871462 5231 r=get_reg(branch_regs[i].regmap,RTEMP);
5232 }
643aeae3 5233 emit_writeword(r,&pcaddr);
57871462 5234 }
7c3a5182 5235 else {SysPrintf("Unknown branch type in do_ccstub\n");abort();}
57871462 5236 }
5237 // Update cycle count
5238 assert(branch_regs[i].regmap[HOST_CCREG]==CCREG||branch_regs[i].regmap[HOST_CCREG]==-1);
2330734f 5239 if(stubs[n].a) emit_addimm(HOST_CCREG,(int)stubs[n].a,HOST_CCREG);
2a014d73 5240 emit_far_call(cc_interrupt);
2330734f 5241 if(stubs[n].a) emit_addimm(HOST_CCREG,-(int)stubs[n].a,HOST_CCREG);
b14b6a8f 5242 if(stubs[n].d==TAKEN) {
277718fa 5243 if(internal_branch(cinfo[i].ba))
5244 load_needed_regs(branch_regs[i].regmap,regs[(cinfo[i].ba-start)>>2].regmap_entry);
cf95b4f0 5245 else if(dops[i].itype==RJUMP) {
57871462 5246 if(get_reg(branch_regs[i].regmap,RTEMP)>=0)
643aeae3 5247 emit_readword(&pcaddr,get_reg(branch_regs[i].regmap,RTEMP));
57871462 5248 else
cf95b4f0 5249 emit_loadreg(dops[i].rs1,get_reg(branch_regs[i].regmap,dops[i].rs1));
57871462 5250 }
b14b6a8f 5251 }else if(stubs[n].d==NOTTAKEN) {
57871462 5252 if(i<slen-2) load_needed_regs(branch_regs[i].regmap,regmap_pre[i+2]);
5253 else load_all_regs(branch_regs[i].regmap);
57871462 5254 }else{
5255 load_all_regs(branch_regs[i].regmap);
5256 }
d1e4ebd9 5257 if (stubs[n].retaddr)
5258 emit_jmp(stubs[n].retaddr);
5259 else
5260 do_jump_vaddr(stubs[n].e);
57871462 5261}
5262
104df9d3 5263static void add_to_linker(void *addr, u_int target, int is_internal)
57871462 5264{
643aeae3 5265 assert(linkcount < ARRAY_SIZE(link_addr));
5266 link_addr[linkcount].addr = addr;
5267 link_addr[linkcount].target = target;
104df9d3 5268 link_addr[linkcount].internal = is_internal;
57871462 5269 linkcount++;
5270}
5271
eba830cd 5272static void ujump_assemble_write_ra(int i)
5273{
5274 int rt;
5275 unsigned int return_address;
5276 rt=get_reg(branch_regs[i].regmap,31);
de6dbc52 5277 //assem_debug("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
eba830cd 5278 //assert(rt>=0);
5279 return_address=start+i*4+8;
5280 if(rt>=0) {
5281 #ifdef USE_MINI_HT
cf95b4f0 5282 if(internal_branch(return_address)&&dops[i+1].rt1!=31) {
eba830cd 5283 int temp=-1; // note: must be ds-safe
5284 #ifdef HOST_TEMPREG
5285 temp=HOST_TEMPREG;
5286 #endif
5287 if(temp>=0) do_miniht_insert(return_address,rt,temp);
5288 else emit_movimm(return_address,rt);
5289 }
5290 else
5291 #endif
5292 {
5293 #ifdef REG_PREFETCH
9f51b4b9 5294 if(temp>=0)
eba830cd 5295 {
643aeae3 5296 if(i_regmap[temp]!=PTEMP) emit_movimm((uintptr_t)hash_table_get(return_address),temp);
eba830cd 5297 }
5298 #endif
de6dbc52 5299 if (!((regs[i].loadedconst >> rt) & 1))
5300 emit_movimm(return_address, rt); // PC into link register
eba830cd 5301 #ifdef IMM_PREFETCH
df4dc2b1 5302 emit_prefetch(hash_table_get(return_address));
eba830cd 5303 #endif
5304 }
5305 }
5306}
5307
2330734f 5308static void ujump_assemble(int i, const struct regstat *i_regs)
57871462 5309{
277718fa 5310 if(i==(cinfo[i].ba-start)>>2) assem_debug("idle loop\n");
57871462 5311 address_generation(i+1,i_regs,regs[i].regmap_entry);
5312 #ifdef REG_PREFETCH
5313 int temp=get_reg(branch_regs[i].regmap,PTEMP);
cf95b4f0 5314 if(dops[i].rt1==31&&temp>=0)
57871462 5315 {
581335b0 5316 signed char *i_regmap=i_regs->regmap;
57871462 5317 int return_address=start+i*4+8;
9f51b4b9 5318 if(get_reg(branch_regs[i].regmap,31)>0)
643aeae3 5319 if(i_regmap[temp]==PTEMP) emit_movimm((uintptr_t)hash_table_get(return_address),temp);
57871462 5320 }
5321 #endif
de6dbc52 5322 if (dops[i].rt1 == 31)
eba830cd 5323 ujump_assemble_write_ra(i); // writeback ra for DS
4ef8f67d 5324 ds_assemble(i+1,i_regs);
5325 uint64_t bc_unneeded=branch_regs[i].u;
cf95b4f0 5326 bc_unneeded|=1|(1LL<<dops[i].rt1);
ad49de89 5327 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,bc_unneeded);
53358c1d 5328 load_reg(regs[i].regmap,branch_regs[i].regmap,CCREG);
57871462 5329 int cc,adj;
5330 cc=get_reg(branch_regs[i].regmap,CCREG);
5331 assert(cc==HOST_CCREG);
277718fa 5332 store_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,cinfo[i].ba);
57871462 5333 #ifdef REG_PREFETCH
cf95b4f0 5334 if(dops[i].rt1==31&&temp>=0) emit_prefetchreg(temp);
57871462 5335 #endif
277718fa 5336 do_cc(i,branch_regs[i].regmap,&adj,cinfo[i].ba,TAKEN,0);
5337 if(adj) emit_addimm(cc, cinfo[i].ccadj + CLOCK_ADJUST(2) - adj, cc);
5338 load_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,cinfo[i].ba);
5339 if(internal_branch(cinfo[i].ba))
57871462 5340 assem_debug("branch: internal\n");
5341 else
5342 assem_debug("branch: external\n");
277718fa 5343 if (internal_branch(cinfo[i].ba) && dops[(cinfo[i].ba-start)>>2].is_ds) {
57871462 5344 ds_assemble_entry(i);
5345 }
5346 else {
277718fa 5347 add_to_linker(out,cinfo[i].ba,internal_branch(cinfo[i].ba));
57871462 5348 emit_jmp(0);
5349 }
5350}
5351
eba830cd 5352static void rjump_assemble_write_ra(int i)
5353{
5354 int rt,return_address;
a5cd72d0 5355 rt=get_reg_w(branch_regs[i].regmap, dops[i].rt1);
de6dbc52 5356 //assem_debug("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
eba830cd 5357 assert(rt>=0);
5358 return_address=start+i*4+8;
5359 #ifdef REG_PREFETCH
9f51b4b9 5360 if(temp>=0)
eba830cd 5361 {
643aeae3 5362 if(i_regmap[temp]!=PTEMP) emit_movimm((uintptr_t)hash_table_get(return_address),temp);
eba830cd 5363 }
5364 #endif
de6dbc52 5365 if (!((regs[i].loadedconst >> rt) & 1))
5366 emit_movimm(return_address, rt); // PC into link register
eba830cd 5367 #ifdef IMM_PREFETCH
df4dc2b1 5368 emit_prefetch(hash_table_get(return_address));
eba830cd 5369 #endif
5370}
5371
2330734f 5372static void rjump_assemble(int i, const struct regstat *i_regs)
57871462 5373{
57871462 5374 int temp;
581335b0 5375 int rs,cc;
cf95b4f0 5376 rs=get_reg(branch_regs[i].regmap,dops[i].rs1);
57871462 5377 assert(rs>=0);
4919de1e 5378 if (ds_writes_rjump_rs(i)) {
57871462 5379 // Delay slot abuse, make a copy of the branch address register
5380 temp=get_reg(branch_regs[i].regmap,RTEMP);
5381 assert(temp>=0);
5382 assert(regs[i].regmap[temp]==RTEMP);
5383 emit_mov(rs,temp);
5384 rs=temp;
5385 }
5386 address_generation(i+1,i_regs,regs[i].regmap_entry);
5387 #ifdef REG_PREFETCH
cf95b4f0 5388 if(dops[i].rt1==31)
57871462 5389 {
5390 if((temp=get_reg(branch_regs[i].regmap,PTEMP))>=0) {
581335b0 5391 signed char *i_regmap=i_regs->regmap;
57871462 5392 int return_address=start+i*4+8;
643aeae3 5393 if(i_regmap[temp]==PTEMP) emit_movimm((uintptr_t)hash_table_get(return_address),temp);
57871462 5394 }
5395 }
5396 #endif
5397 #ifdef USE_MINI_HT
cf95b4f0 5398 if(dops[i].rs1==31) {
57871462 5399 int rh=get_reg(regs[i].regmap,RHASH);
5400 if(rh>=0) do_preload_rhash(rh);
5401 }
5402 #endif
de6dbc52 5403 if (dops[i].rt1 != 0)
eba830cd 5404 rjump_assemble_write_ra(i);
d5910d5d 5405 ds_assemble(i+1,i_regs);
5406 uint64_t bc_unneeded=branch_regs[i].u;
cf95b4f0 5407 bc_unneeded|=1|(1LL<<dops[i].rt1);
5408 bc_unneeded&=~(1LL<<dops[i].rs1);
ad49de89 5409 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,bc_unneeded);
cf95b4f0 5410 load_regs(regs[i].regmap,branch_regs[i].regmap,dops[i].rs1,CCREG);
57871462 5411 cc=get_reg(branch_regs[i].regmap,CCREG);
5412 assert(cc==HOST_CCREG);
581335b0 5413 (void)cc;
57871462 5414 #ifdef USE_MINI_HT
5415 int rh=get_reg(branch_regs[i].regmap,RHASH);
5416 int ht=get_reg(branch_regs[i].regmap,RHTBL);
cf95b4f0 5417 if(dops[i].rs1==31) {
57871462 5418 if(regs[i].regmap[rh]!=RHASH) do_preload_rhash(rh);
5419 do_preload_rhtbl(ht);
5420 do_rhash(rs,rh);
5421 }
5422 #endif
ad49de89 5423 store_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,-1);
57871462 5424 #ifdef DESTRUCTIVE_WRITEBACK
ad49de89 5425 if((branch_regs[i].dirty>>rs)&1) {
cf95b4f0 5426 if(dops[i].rs1!=dops[i+1].rt1&&dops[i].rs1!=dops[i+1].rt2) {
5427 emit_loadreg(dops[i].rs1,rs);
57871462 5428 }
5429 }
5430 #endif
5431 #ifdef REG_PREFETCH
cf95b4f0 5432 if(dops[i].rt1==31&&temp>=0) emit_prefetchreg(temp);
57871462 5433 #endif
5434 #ifdef USE_MINI_HT
cf95b4f0 5435 if(dops[i].rs1==31) {
57871462 5436 do_miniht_load(ht,rh);
5437 }
5438 #endif
5439 //do_cc(i,branch_regs[i].regmap,&adj,-1,TAKEN);
277718fa 5440 //if(adj) emit_addimm(cc,2*(cinfo[i].ccadj+2-adj),cc); // ??? - Shouldn't happen
57871462 5441 //assert(adj==0);
277718fa 5442 emit_addimm_and_set_flags(cinfo[i].ccadj + CLOCK_ADJUST(2), HOST_CCREG);
d1e4ebd9 5443 add_stub(CC_STUB,out,NULL,0,i,-1,TAKEN,rs);
a5cd72d0 5444 if (dops[i+1].itype == RFE)
911f2d55 5445 // special case for RFE
5446 emit_jmp(0);
5447 else
71e490c5 5448 emit_jns(0);
ad49de89 5449 //load_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,-1);
57871462 5450 #ifdef USE_MINI_HT
cf95b4f0 5451 if(dops[i].rs1==31) {
57871462 5452 do_miniht_jump(rs,rh,ht);
5453 }
5454 else
5455 #endif
5456 {
d1e4ebd9 5457 do_jump_vaddr(rs);
57871462 5458 }
57871462 5459 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
cf95b4f0 5460 if(dops[i].rt1!=31&&i<slen-2&&(((u_int)out)&7)) emit_mov(13,13);
57871462 5461 #endif
5462}
5463
2330734f 5464static void cjump_assemble(int i, const struct regstat *i_regs)
57871462 5465{
2330734f 5466 const signed char *i_regmap = i_regs->regmap;
57871462 5467 int cc;
5468 int match;
277718fa 5469 match=match_bt(branch_regs[i].regmap,branch_regs[i].dirty,cinfo[i].ba);
57871462 5470 assem_debug("match=%d\n",match);
ad49de89 5471 int s1l,s2l;
57871462 5472 int unconditional=0,nop=0;
57871462 5473 int invert=0;
277718fa 5474 int internal=internal_branch(cinfo[i].ba);
5475 if(i==(cinfo[i].ba-start)>>2) assem_debug("idle loop\n");
57871462 5476 if(!match) invert=1;
5477 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
277718fa 5478 if(i>(cinfo[i].ba-start)>>2) invert=1;
57871462 5479 #endif
3968e69e 5480 #ifdef __aarch64__
5481 invert=1; // because of near cond. branches
5482 #endif
9f51b4b9 5483
cf95b4f0 5484 if(dops[i].ooo) {
5485 s1l=get_reg(branch_regs[i].regmap,dops[i].rs1);
5486 s2l=get_reg(branch_regs[i].regmap,dops[i].rs2);
57871462 5487 }
5488 else {
cf95b4f0 5489 s1l=get_reg(i_regmap,dops[i].rs1);
5490 s2l=get_reg(i_regmap,dops[i].rs2);
57871462 5491 }
cf95b4f0 5492 if(dops[i].rs1==0&&dops[i].rs2==0)
57871462 5493 {
cf95b4f0 5494 if(dops[i].opcode&1) nop=1;
57871462 5495 else unconditional=1;
cf95b4f0 5496 //assert(dops[i].opcode!=5);
5497 //assert(dops[i].opcode!=7);
5498 //assert(dops[i].opcode!=0x15);
5499 //assert(dops[i].opcode!=0x17);
57871462 5500 }
cf95b4f0 5501 else if(dops[i].rs1==0)
57871462 5502 {
ad49de89 5503 s1l=s2l;
5504 s2l=-1;
57871462 5505 }
cf95b4f0 5506 else if(dops[i].rs2==0)
57871462 5507 {
ad49de89 5508 s2l=-1;
57871462 5509 }
5510
cf95b4f0 5511 if(dops[i].ooo) {
57871462 5512 // Out of order execution (delay slot first)
5513 //printf("OOOE\n");
5514 address_generation(i+1,i_regs,regs[i].regmap_entry);
5515 ds_assemble(i+1,i_regs);
5516 int adj;
5517 uint64_t bc_unneeded=branch_regs[i].u;
cf95b4f0 5518 bc_unneeded&=~((1LL<<dops[i].rs1)|(1LL<<dops[i].rs2));
57871462 5519 bc_unneeded|=1;
ad49de89 5520 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,bc_unneeded);
cf95b4f0 5521 load_regs(regs[i].regmap,branch_regs[i].regmap,dops[i].rs1,dops[i].rs2);
53358c1d 5522 load_reg(regs[i].regmap,branch_regs[i].regmap,CCREG);
57871462 5523 cc=get_reg(branch_regs[i].regmap,CCREG);
5524 assert(cc==HOST_CCREG);
9f51b4b9 5525 if(unconditional)
277718fa 5526 store_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,cinfo[i].ba);
5527 //do_cc(i,branch_regs[i].regmap,&adj,unconditional?cinfo[i].ba:-1,unconditional);
57871462 5528 //assem_debug("cycle count (adj)\n");
5529 if(unconditional) {
277718fa 5530 do_cc(i,branch_regs[i].regmap,&adj,cinfo[i].ba,TAKEN,0);
5531 if(i!=(cinfo[i].ba-start)>>2 || source[i+1]!=0) {
5532 if(adj) emit_addimm(cc, cinfo[i].ccadj + CLOCK_ADJUST(2) - adj, cc);
5533 load_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,cinfo[i].ba);
57871462 5534 if(internal)
5535 assem_debug("branch: internal\n");
5536 else
5537 assem_debug("branch: external\n");
277718fa 5538 if (internal && dops[(cinfo[i].ba-start)>>2].is_ds) {
57871462 5539 ds_assemble_entry(i);
5540 }
5541 else {
277718fa 5542 add_to_linker(out,cinfo[i].ba,internal);
57871462 5543 emit_jmp(0);
5544 }
5545 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5546 if(((u_int)out)&7) emit_addnop(0);
5547 #endif
5548 }
5549 }
5550 else if(nop) {
277718fa 5551 emit_addimm_and_set_flags(cinfo[i].ccadj + CLOCK_ADJUST(2), cc);
b14b6a8f 5552 void *jaddr=out;
57871462 5553 emit_jns(0);
b14b6a8f 5554 add_stub(CC_STUB,jaddr,out,0,i,start+i*4+8,NOTTAKEN,0);
57871462 5555 }
5556 else {
df4dc2b1 5557 void *taken = NULL, *nottaken = NULL, *nottaken1 = NULL;
57871462 5558 do_cc(i,branch_regs[i].regmap,&adj,-1,0,invert);
277718fa 5559 if(adj&&!invert) emit_addimm(cc, cinfo[i].ccadj + CLOCK_ADJUST(2) - adj, cc);
9f51b4b9 5560
57871462 5561 //printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5562 assert(s1l>=0);
cf95b4f0 5563 if(dops[i].opcode==4) // BEQ
57871462 5564 {
5565 if(s2l>=0) emit_cmp(s1l,s2l);
5566 else emit_test(s1l,s1l);
5567 if(invert){
df4dc2b1 5568 nottaken=out;
7c3a5182 5569 emit_jne(DJT_1);
57871462 5570 }else{
277718fa 5571 add_to_linker(out,cinfo[i].ba,internal);
57871462 5572 emit_jeq(0);
5573 }
5574 }
cf95b4f0 5575 if(dops[i].opcode==5) // BNE
57871462 5576 {
5577 if(s2l>=0) emit_cmp(s1l,s2l);
5578 else emit_test(s1l,s1l);
5579 if(invert){
df4dc2b1 5580 nottaken=out;
7c3a5182 5581 emit_jeq(DJT_1);
57871462 5582 }else{
277718fa 5583 add_to_linker(out,cinfo[i].ba,internal);
57871462 5584 emit_jne(0);
5585 }
5586 }
cf95b4f0 5587 if(dops[i].opcode==6) // BLEZ
57871462 5588 {
5589 emit_cmpimm(s1l,1);
5590 if(invert){
df4dc2b1 5591 nottaken=out;
7c3a5182 5592 emit_jge(DJT_1);
57871462 5593 }else{
277718fa 5594 add_to_linker(out,cinfo[i].ba,internal);
57871462 5595 emit_jl(0);
5596 }
5597 }
cf95b4f0 5598 if(dops[i].opcode==7) // BGTZ
57871462 5599 {
5600 emit_cmpimm(s1l,1);
5601 if(invert){
df4dc2b1 5602 nottaken=out;
7c3a5182 5603 emit_jl(DJT_1);
57871462 5604 }else{
277718fa 5605 add_to_linker(out,cinfo[i].ba,internal);
57871462 5606 emit_jge(0);
5607 }
5608 }
5609 if(invert) {
df4dc2b1 5610 if(taken) set_jump_target(taken, out);
57871462 5611 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
277718fa 5612 if (match && (!internal || !dops[(cinfo[i].ba-start)>>2].is_ds)) {
57871462 5613 if(adj) {
2330734f 5614 emit_addimm(cc,-adj,cc);
277718fa 5615 add_to_linker(out,cinfo[i].ba,internal);
57871462 5616 }else{
5617 emit_addnop(13);
277718fa 5618 add_to_linker(out,cinfo[i].ba,internal*2);
57871462 5619 }
5620 emit_jmp(0);
5621 }else
5622 #endif
5623 {
2330734f 5624 if(adj) emit_addimm(cc,-adj,cc);
277718fa 5625 store_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,cinfo[i].ba);
5626 load_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,cinfo[i].ba);
57871462 5627 if(internal)
5628 assem_debug("branch: internal\n");
5629 else
5630 assem_debug("branch: external\n");
277718fa 5631 if (internal && dops[(cinfo[i].ba - start) >> 2].is_ds) {
57871462 5632 ds_assemble_entry(i);
5633 }
5634 else {
277718fa 5635 add_to_linker(out,cinfo[i].ba,internal);
57871462 5636 emit_jmp(0);
5637 }
5638 }
df4dc2b1 5639 set_jump_target(nottaken, out);
57871462 5640 }
5641
df4dc2b1 5642 if(nottaken1) set_jump_target(nottaken1, out);
57871462 5643 if(adj) {
2330734f 5644 if(!invert) emit_addimm(cc,adj,cc);
57871462 5645 }
5646 } // (!unconditional)
5647 } // if(ooo)
5648 else
5649 {
5650 // In-order execution (branch first)
df4dc2b1 5651 void *taken = NULL, *nottaken = NULL, *nottaken1 = NULL;
57871462 5652 if(!unconditional&&!nop) {
57871462 5653 //printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5654 assert(s1l>=0);
cf95b4f0 5655 if((dops[i].opcode&0x2f)==4) // BEQ
57871462 5656 {
5657 if(s2l>=0) emit_cmp(s1l,s2l);
5658 else emit_test(s1l,s1l);
df4dc2b1 5659 nottaken=out;
7c3a5182 5660 emit_jne(DJT_2);
57871462 5661 }
cf95b4f0 5662 if((dops[i].opcode&0x2f)==5) // BNE
57871462 5663 {
5664 if(s2l>=0) emit_cmp(s1l,s2l);
5665 else emit_test(s1l,s1l);
df4dc2b1 5666 nottaken=out;
7c3a5182 5667 emit_jeq(DJT_2);
57871462 5668 }
cf95b4f0 5669 if((dops[i].opcode&0x2f)==6) // BLEZ
57871462 5670 {
5671 emit_cmpimm(s1l,1);
df4dc2b1 5672 nottaken=out;
7c3a5182 5673 emit_jge(DJT_2);
57871462 5674 }
cf95b4f0 5675 if((dops[i].opcode&0x2f)==7) // BGTZ
57871462 5676 {
5677 emit_cmpimm(s1l,1);
df4dc2b1 5678 nottaken=out;
7c3a5182 5679 emit_jl(DJT_2);
57871462 5680 }
5681 } // if(!unconditional)
5682 int adj;
5683 uint64_t ds_unneeded=branch_regs[i].u;
cf95b4f0 5684 ds_unneeded&=~((1LL<<dops[i+1].rs1)|(1LL<<dops[i+1].rs2));
57871462 5685 ds_unneeded|=1;
57871462 5686 // branch taken
5687 if(!nop) {
df4dc2b1 5688 if(taken) set_jump_target(taken, out);
57871462 5689 assem_debug("1:\n");
ad49de89 5690 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,ds_unneeded);
57871462 5691 // load regs
cf95b4f0 5692 load_regs(regs[i].regmap,branch_regs[i].regmap,dops[i+1].rs1,dops[i+1].rs2);
57871462 5693 address_generation(i+1,&branch_regs[i],0);
37387d8b 5694 if (ram_offset)
53358c1d 5695 load_reg(regs[i].regmap,branch_regs[i].regmap,ROREG);
ad49de89 5696 load_regs(regs[i].regmap,branch_regs[i].regmap,CCREG,INVCP);
57871462 5697 ds_assemble(i+1,&branch_regs[i]);
5698 cc=get_reg(branch_regs[i].regmap,CCREG);
5699 if(cc==-1) {
5700 emit_loadreg(CCREG,cc=HOST_CCREG);
5701 // CHECK: Is the following instruction (fall thru) allocated ok?
5702 }
5703 assert(cc==HOST_CCREG);
277718fa 5704 store_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,cinfo[i].ba);
5705 do_cc(i,i_regmap,&adj,cinfo[i].ba,TAKEN,0);
57871462 5706 assem_debug("cycle count (adj)\n");
277718fa 5707 if(adj) emit_addimm(cc, cinfo[i].ccadj + CLOCK_ADJUST(2) - adj, cc);
5708 load_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,cinfo[i].ba);
57871462 5709 if(internal)
5710 assem_debug("branch: internal\n");
5711 else
5712 assem_debug("branch: external\n");
277718fa 5713 if (internal && dops[(cinfo[i].ba - start) >> 2].is_ds) {
57871462 5714 ds_assemble_entry(i);
5715 }
5716 else {
277718fa 5717 add_to_linker(out,cinfo[i].ba,internal);
57871462 5718 emit_jmp(0);
5719 }
5720 }
5721 // branch not taken
57871462 5722 if(!unconditional) {
df4dc2b1 5723 if(nottaken1) set_jump_target(nottaken1, out);
5724 set_jump_target(nottaken, out);
57871462 5725 assem_debug("2:\n");
fe807a8a 5726 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,ds_unneeded);
37387d8b 5727 // load regs
fe807a8a 5728 load_regs(regs[i].regmap,branch_regs[i].regmap,dops[i+1].rs1,dops[i+1].rs2);
5729 address_generation(i+1,&branch_regs[i],0);
37387d8b 5730 if (ram_offset)
53358c1d 5731 load_reg(regs[i].regmap,branch_regs[i].regmap,ROREG);
37387d8b 5732 load_regs(regs[i].regmap,branch_regs[i].regmap,CCREG,INVCP);
fe807a8a 5733 ds_assemble(i+1,&branch_regs[i]);
57871462 5734 cc=get_reg(branch_regs[i].regmap,CCREG);
fe807a8a 5735 if (cc == -1) {
57871462 5736 // Cycle count isn't in a register, temporarily load it then write it out
5737 emit_loadreg(CCREG,HOST_CCREG);
277718fa 5738 emit_addimm_and_set_flags(cinfo[i].ccadj + CLOCK_ADJUST(2), HOST_CCREG);
b14b6a8f 5739 void *jaddr=out;
57871462 5740 emit_jns(0);
b14b6a8f 5741 add_stub(CC_STUB,jaddr,out,0,i,start+i*4+8,NOTTAKEN,0);
57871462 5742 emit_storereg(CCREG,HOST_CCREG);
5743 }
5744 else{
5745 cc=get_reg(i_regmap,CCREG);
5746 assert(cc==HOST_CCREG);
277718fa 5747 emit_addimm_and_set_flags(cinfo[i].ccadj + CLOCK_ADJUST(2), cc);
b14b6a8f 5748 void *jaddr=out;
57871462 5749 emit_jns(0);
fe807a8a 5750 add_stub(CC_STUB,jaddr,out,0,i,start+i*4+8,NOTTAKEN,0);
57871462 5751 }
5752 }
5753 }
5754}
5755
2330734f 5756static void sjump_assemble(int i, const struct regstat *i_regs)
57871462 5757{
2330734f 5758 const signed char *i_regmap = i_regs->regmap;
57871462 5759 int cc;
5760 int match;
277718fa 5761 match=match_bt(branch_regs[i].regmap,branch_regs[i].dirty,cinfo[i].ba);
2acc46cd 5762 assem_debug("smatch=%d ooo=%d\n", match, dops[i].ooo);
ad49de89 5763 int s1l;
57871462 5764 int unconditional=0,nevertaken=0;
57871462 5765 int invert=0;
277718fa 5766 int internal=internal_branch(cinfo[i].ba);
5767 if(i==(cinfo[i].ba-start)>>2) assem_debug("idle loop\n");
57871462 5768 if(!match) invert=1;
5769 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
277718fa 5770 if(i>(cinfo[i].ba-start)>>2) invert=1;
57871462 5771 #endif
3968e69e 5772 #ifdef __aarch64__
5773 invert=1; // because of near cond. branches
5774 #endif
57871462 5775
cf95b4f0 5776 //if(dops[i].opcode2>=0x10) return; // FIXME (BxxZAL)
5777 //assert(dops[i].opcode2<0x10||dops[i].rs1==0); // FIXME (BxxZAL)
57871462 5778
cf95b4f0 5779 if(dops[i].ooo) {
5780 s1l=get_reg(branch_regs[i].regmap,dops[i].rs1);
57871462 5781 }
5782 else {
cf95b4f0 5783 s1l=get_reg(i_regmap,dops[i].rs1);
57871462 5784 }
cf95b4f0 5785 if(dops[i].rs1==0)
57871462 5786 {
cf95b4f0 5787 if(dops[i].opcode2&1) unconditional=1;
57871462 5788 else nevertaken=1;
5789 // These are never taken (r0 is never less than zero)
cf95b4f0 5790 //assert(dops[i].opcode2!=0);
5791 //assert(dops[i].opcode2!=2);
5792 //assert(dops[i].opcode2!=0x10);
5793 //assert(dops[i].opcode2!=0x12);
57871462 5794 }
57871462 5795
cf95b4f0 5796 if(dops[i].ooo) {
57871462 5797 // Out of order execution (delay slot first)
5798 //printf("OOOE\n");
5799 address_generation(i+1,i_regs,regs[i].regmap_entry);
5800 ds_assemble(i+1,i_regs);
5801 int adj;
5802 uint64_t bc_unneeded=branch_regs[i].u;
cf95b4f0 5803 bc_unneeded&=~((1LL<<dops[i].rs1)|(1LL<<dops[i].rs2));
57871462 5804 bc_unneeded|=1;
ad49de89 5805 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,bc_unneeded);
cf95b4f0 5806 load_regs(regs[i].regmap,branch_regs[i].regmap,dops[i].rs1,dops[i].rs1);
53358c1d 5807 load_reg(regs[i].regmap,branch_regs[i].regmap,CCREG);
cf95b4f0 5808 if(dops[i].rt1==31) {
57871462 5809 int rt,return_address;
57871462 5810 rt=get_reg(branch_regs[i].regmap,31);
de6dbc52 5811 //assem_debug("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
57871462 5812 if(rt>=0) {
5813 // Save the PC even if the branch is not taken
5814 return_address=start+i*4+8;
5815 emit_movimm(return_address,rt); // PC into link register
5816 #ifdef IMM_PREFETCH
df4dc2b1 5817 if(!nevertaken) emit_prefetch(hash_table_get(return_address));
57871462 5818 #endif
5819 }
5820 }
5821 cc=get_reg(branch_regs[i].regmap,CCREG);
5822 assert(cc==HOST_CCREG);
9f51b4b9 5823 if(unconditional)
277718fa 5824 store_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,cinfo[i].ba);
5825 //do_cc(i,branch_regs[i].regmap,&adj,unconditional?cinfo[i].ba:-1,unconditional);
57871462 5826 assem_debug("cycle count (adj)\n");
5827 if(unconditional) {
277718fa 5828 do_cc(i,branch_regs[i].regmap,&adj,cinfo[i].ba,TAKEN,0);
5829 if(i!=(cinfo[i].ba-start)>>2 || source[i+1]!=0) {
5830 if(adj) emit_addimm(cc, cinfo[i].ccadj + CLOCK_ADJUST(2) - adj, cc);
5831 load_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,cinfo[i].ba);
57871462 5832 if(internal)
5833 assem_debug("branch: internal\n");
5834 else
5835 assem_debug("branch: external\n");
277718fa 5836 if (internal && dops[(cinfo[i].ba - start) >> 2].is_ds) {
57871462 5837 ds_assemble_entry(i);
5838 }
5839 else {
277718fa 5840 add_to_linker(out,cinfo[i].ba,internal);
57871462 5841 emit_jmp(0);
5842 }
5843 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5844 if(((u_int)out)&7) emit_addnop(0);
5845 #endif
5846 }
5847 }
5848 else if(nevertaken) {
277718fa 5849 emit_addimm_and_set_flags(cinfo[i].ccadj + CLOCK_ADJUST(2), cc);
b14b6a8f 5850 void *jaddr=out;
57871462 5851 emit_jns(0);
b14b6a8f 5852 add_stub(CC_STUB,jaddr,out,0,i,start+i*4+8,NOTTAKEN,0);
57871462 5853 }
5854 else {
df4dc2b1 5855 void *nottaken = NULL;
57871462 5856 do_cc(i,branch_regs[i].regmap,&adj,-1,0,invert);
277718fa 5857 if(adj&&!invert) emit_addimm(cc, cinfo[i].ccadj + CLOCK_ADJUST(2) - adj, cc);
57871462 5858 {
5859 assert(s1l>=0);
ecca05e3 5860 if ((dops[i].opcode2 & 1) == 0) // BLTZ/BLTZAL
57871462 5861 {
5862 emit_test(s1l,s1l);
5863 if(invert){
df4dc2b1 5864 nottaken=out;
7c3a5182 5865 emit_jns(DJT_1);
57871462 5866 }else{
277718fa 5867 add_to_linker(out,cinfo[i].ba,internal);
57871462 5868 emit_js(0);
5869 }
5870 }
ecca05e3 5871 else // BGEZ/BGEZAL
57871462 5872 {
5873 emit_test(s1l,s1l);
5874 if(invert){
df4dc2b1 5875 nottaken=out;
7c3a5182 5876 emit_js(DJT_1);
57871462 5877 }else{
277718fa 5878 add_to_linker(out,cinfo[i].ba,internal);
57871462 5879 emit_jns(0);
5880 }
5881 }
ad49de89 5882 }
9f51b4b9 5883
57871462 5884 if(invert) {
5885 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
277718fa 5886 if (match && (!internal || !dops[(cinfo[i].ba - start) >> 2].is_ds)) {
57871462 5887 if(adj) {
2330734f 5888 emit_addimm(cc,-adj,cc);
277718fa 5889 add_to_linker(out,cinfo[i].ba,internal);
57871462 5890 }else{
5891 emit_addnop(13);
277718fa 5892 add_to_linker(out,cinfo[i].ba,internal*2);
57871462 5893 }
5894 emit_jmp(0);
5895 }else
5896 #endif
5897 {
2330734f 5898 if(adj) emit_addimm(cc,-adj,cc);
277718fa 5899 store_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,cinfo[i].ba);
5900 load_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,cinfo[i].ba);
57871462 5901 if(internal)
5902 assem_debug("branch: internal\n");
5903 else
5904 assem_debug("branch: external\n");
277718fa 5905 if (internal && dops[(cinfo[i].ba - start) >> 2].is_ds) {
57871462 5906 ds_assemble_entry(i);
5907 }
5908 else {
277718fa 5909 add_to_linker(out,cinfo[i].ba,internal);
57871462 5910 emit_jmp(0);
5911 }
5912 }
df4dc2b1 5913 set_jump_target(nottaken, out);
57871462 5914 }
5915
5916 if(adj) {
2330734f 5917 if(!invert) emit_addimm(cc,adj,cc);
57871462 5918 }
5919 } // (!unconditional)
5920 } // if(ooo)
5921 else
5922 {
5923 // In-order execution (branch first)
5924 //printf("IOE\n");
df4dc2b1 5925 void *nottaken = NULL;
de6dbc52 5926 if (!unconditional && !nevertaken) {
ecca05e3 5927 assert(s1l >= 0);
5928 emit_test(s1l, s1l);
5929 }
5930 if (dops[i].rt1 == 31) {
5931 int rt, return_address;
5932 rt = get_reg(branch_regs[i].regmap,31);
5933 if(rt >= 0) {
a6491170 5934 // Save the PC even if the branch is not taken
ecca05e3 5935 return_address = start + i*4+8;
5936 emit_movimm(return_address, rt); // PC into link register
a6491170 5937 #ifdef IMM_PREFETCH
df4dc2b1 5938 emit_prefetch(hash_table_get(return_address));
a6491170 5939 #endif
5940 }
5941 }
de6dbc52 5942 if (!unconditional && !nevertaken) {
ecca05e3 5943 nottaken = out;
5944 if (!(dops[i].opcode2 & 1)) // BLTZ/BLTZAL
5945 emit_jns(DJT_1);
5946 else // BGEZ/BGEZAL
5947 emit_js(DJT_1);
5948 }
57871462 5949 int adj;
5950 uint64_t ds_unneeded=branch_regs[i].u;
cf95b4f0 5951 ds_unneeded&=~((1LL<<dops[i+1].rs1)|(1LL<<dops[i+1].rs2));
57871462 5952 ds_unneeded|=1;
57871462 5953 // branch taken
5954 if(!nevertaken) {
5955 //assem_debug("1:\n");
ad49de89 5956 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,ds_unneeded);
57871462 5957 // load regs
cf95b4f0 5958 load_regs(regs[i].regmap,branch_regs[i].regmap,dops[i+1].rs1,dops[i+1].rs2);
57871462 5959 address_generation(i+1,&branch_regs[i],0);
37387d8b 5960 if (ram_offset)
53358c1d 5961 load_reg(regs[i].regmap,branch_regs[i].regmap,ROREG);
ad49de89 5962 load_regs(regs[i].regmap,branch_regs[i].regmap,CCREG,INVCP);
57871462 5963 ds_assemble(i+1,&branch_regs[i]);
5964 cc=get_reg(branch_regs[i].regmap,CCREG);
5965 if(cc==-1) {
5966 emit_loadreg(CCREG,cc=HOST_CCREG);
5967 // CHECK: Is the following instruction (fall thru) allocated ok?
5968 }
5969 assert(cc==HOST_CCREG);
277718fa 5970 store_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,cinfo[i].ba);
5971 do_cc(i,i_regmap,&adj,cinfo[i].ba,TAKEN,0);
57871462 5972 assem_debug("cycle count (adj)\n");
277718fa 5973 if(adj) emit_addimm(cc, cinfo[i].ccadj + CLOCK_ADJUST(2) - adj, cc);
5974 load_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,cinfo[i].ba);
57871462 5975 if(internal)
5976 assem_debug("branch: internal\n");
5977 else
5978 assem_debug("branch: external\n");
277718fa 5979 if (internal && dops[(cinfo[i].ba - start) >> 2].is_ds) {
57871462 5980 ds_assemble_entry(i);
5981 }
5982 else {
277718fa 5983 add_to_linker(out,cinfo[i].ba,internal);
57871462 5984 emit_jmp(0);
5985 }
5986 }
5987 // branch not taken
57871462 5988 if(!unconditional) {
de6dbc52 5989 if (!nevertaken) {
5990 assert(nottaken);
5991 set_jump_target(nottaken, out);
5992 }
57871462 5993 assem_debug("1:\n");
fe807a8a 5994 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,ds_unneeded);
5995 load_regs(regs[i].regmap,branch_regs[i].regmap,dops[i+1].rs1,dops[i+1].rs2);
5996 address_generation(i+1,&branch_regs[i],0);
5a18ce2e 5997 if (ram_offset)
53358c1d 5998 load_reg(regs[i].regmap,branch_regs[i].regmap,ROREG);
5a18ce2e 5999 load_regs(regs[i].regmap,branch_regs[i].regmap,CCREG,INVCP);
fe807a8a 6000 ds_assemble(i+1,&branch_regs[i]);
57871462 6001 cc=get_reg(branch_regs[i].regmap,CCREG);
fe807a8a 6002 if (cc == -1) {
57871462 6003 // Cycle count isn't in a register, temporarily load it then write it out
6004 emit_loadreg(CCREG,HOST_CCREG);
277718fa 6005 emit_addimm_and_set_flags(cinfo[i].ccadj + CLOCK_ADJUST(2), HOST_CCREG);
b14b6a8f 6006 void *jaddr=out;
57871462 6007 emit_jns(0);
b14b6a8f 6008 add_stub(CC_STUB,jaddr,out,0,i,start+i*4+8,NOTTAKEN,0);
57871462 6009 emit_storereg(CCREG,HOST_CCREG);
6010 }
6011 else{
6012 cc=get_reg(i_regmap,CCREG);
6013 assert(cc==HOST_CCREG);
277718fa 6014 emit_addimm_and_set_flags(cinfo[i].ccadj + CLOCK_ADJUST(2), cc);
b14b6a8f 6015 void *jaddr=out;
57871462 6016 emit_jns(0);
fe807a8a 6017 add_stub(CC_STUB,jaddr,out,0,i,start+i*4+8,NOTTAKEN,0);
57871462 6018 }
6019 }
6020 }
6021}
6022
670c0f22 6023static void check_regmap(signed char *regmap)
6024{
6025#ifndef NDEBUG
6026 int i,j;
6027 for (i = 0; i < HOST_REGS; i++) {
6028 if (regmap[i] < 0)
6029 continue;
6030 for (j = i + 1; j < HOST_REGS; j++)
6031 assert(regmap[i] != regmap[j]);
6032 }
6033#endif
6034}
6035
4600ba03 6036#ifdef DISASM
2acc46cd 6037#include <inttypes.h>
53dc27f6 6038static char insn[MAXBLOCK][10];
6039
6040#define set_mnemonic(i_, n_) \
6041 strcpy(insn[i_], n_)
6042
2acc46cd 6043void print_regmap(const char *name, const signed char *regmap)
6044{
6045 char buf[5];
6046 int i, l;
6047 fputs(name, stdout);
6048 for (i = 0; i < HOST_REGS; i++) {
6049 l = 0;
6050 if (regmap[i] >= 0)
6051 l = snprintf(buf, sizeof(buf), "$%d", regmap[i]);
6052 for (; l < 3; l++)
6053 buf[l] = ' ';
6054 buf[l] = 0;
6055 printf(" r%d=%s", i, buf);
6056 }
6057 fputs("\n", stdout);
6058}
6059
57871462 6060 /* disassembly */
6061void disassemble_inst(int i)
6062{
cf95b4f0 6063 if (dops[i].bt) printf("*"); else printf(" ");
6064 switch(dops[i].itype) {
57871462 6065 case UJUMP:
277718fa 6066 printf (" %x: %s %8x\n",start+i*4,insn[i],cinfo[i].ba);break;
57871462 6067 case CJUMP:
277718fa 6068 printf (" %x: %s r%d,r%d,%8x\n",start+i*4,insn[i],dops[i].rs1,dops[i].rs2,i?start+i*4+4+((signed int)((unsigned int)source[i]<<16)>>14):cinfo[i].ba);break;
57871462 6069 case SJUMP:
cf95b4f0 6070 printf (" %x: %s r%d,%8x\n",start+i*4,insn[i],dops[i].rs1,start+i*4+4+((signed int)((unsigned int)source[i]<<16)>>14));break;
57871462 6071 case RJUMP:
ecca05e3 6072 if (dops[i].opcode2 == 9 && dops[i].rt1 != 31)
cf95b4f0 6073 printf (" %x: %s r%d,r%d\n",start+i*4,insn[i],dops[i].rt1,dops[i].rs1);
5067f341 6074 else
cf95b4f0 6075 printf (" %x: %s r%d\n",start+i*4,insn[i],dops[i].rs1);
5067f341 6076 break;
57871462 6077 case IMM16:
cf95b4f0 6078 if(dops[i].opcode==0xf) //LUI
277718fa 6079 printf (" %x: %s r%d,%4x0000\n",start+i*4,insn[i],dops[i].rt1,cinfo[i].imm&0xffff);
57871462 6080 else
277718fa 6081 printf (" %x: %s r%d,r%d,%d\n",start+i*4,insn[i],dops[i].rt1,dops[i].rs1,cinfo[i].imm);
57871462 6082 break;
6083 case LOAD:
6084 case LOADLR:
277718fa 6085 printf (" %x: %s r%d,r%d+%x\n",start+i*4,insn[i],dops[i].rt1,dops[i].rs1,cinfo[i].imm);
57871462 6086 break;
6087 case STORE:
6088 case STORELR:
277718fa 6089 printf (" %x: %s r%d,r%d+%x\n",start+i*4,insn[i],dops[i].rs2,dops[i].rs1,cinfo[i].imm);
57871462 6090 break;
6091 case ALU:
6092 case SHIFT:
cf95b4f0 6093 printf (" %x: %s r%d,r%d,r%d\n",start+i*4,insn[i],dops[i].rt1,dops[i].rs1,dops[i].rs2);
57871462 6094 break;
6095 case MULTDIV:
cf95b4f0 6096 printf (" %x: %s r%d,r%d\n",start+i*4,insn[i],dops[i].rs1,dops[i].rs2);
57871462 6097 break;
6098 case SHIFTIMM:
277718fa 6099 printf (" %x: %s r%d,r%d,%d\n",start+i*4,insn[i],dops[i].rt1,dops[i].rs1,cinfo[i].imm);
57871462 6100 break;
6101 case MOV:
cf95b4f0 6102 if((dops[i].opcode2&0x1d)==0x10)
6103 printf (" %x: %s r%d\n",start+i*4,insn[i],dops[i].rt1);
6104 else if((dops[i].opcode2&0x1d)==0x11)
6105 printf (" %x: %s r%d\n",start+i*4,insn[i],dops[i].rs1);
57871462 6106 else
6107 printf (" %x: %s\n",start+i*4,insn[i]);
6108 break;
6109 case COP0:
cf95b4f0 6110 if(dops[i].opcode2==0)
6111 printf (" %x: %s r%d,cpr0[%d]\n",start+i*4,insn[i],dops[i].rt1,(source[i]>>11)&0x1f); // MFC0
6112 else if(dops[i].opcode2==4)
6113 printf (" %x: %s r%d,cpr0[%d]\n",start+i*4,insn[i],dops[i].rs1,(source[i]>>11)&0x1f); // MTC0
57871462 6114 else printf (" %x: %s\n",start+i*4,insn[i]);
6115 break;
b9b61529 6116 case COP2:
cf95b4f0 6117 if(dops[i].opcode2<3)
6118 printf (" %x: %s r%d,cpr2[%d]\n",start+i*4,insn[i],dops[i].rt1,(source[i]>>11)&0x1f); // MFC2
6119 else if(dops[i].opcode2>3)
6120 printf (" %x: %s r%d,cpr2[%d]\n",start+i*4,insn[i],dops[i].rs1,(source[i]>>11)&0x1f); // MTC2
b9b61529 6121 else printf (" %x: %s\n",start+i*4,insn[i]);
6122 break;
b9b61529 6123 case C2LS:
277718fa 6124 printf (" %x: %s cpr2[%d],r%d+%x\n",start+i*4,insn[i],(source[i]>>16)&0x1f,dops[i].rs1,cinfo[i].imm);
b9b61529 6125 break;
1e973cb0 6126 case INTCALL:
6127 printf (" %x: %s (INTCALL)\n",start+i*4,insn[i]);
6128 break;
57871462 6129 default:
6130 //printf (" %s %8x\n",insn[i],source[i]);
6131 printf (" %x: %s\n",start+i*4,insn[i]);
6132 }
a5cd72d0 6133 #ifndef REGMAP_PRINT
2acc46cd 6134 return;
a5cd72d0 6135 #endif
33a1eda1 6136 printf("D: %x WD: %x U: %"PRIx64" hC: %x hWC: %x hLC: %x\n",
a5cd72d0 6137 regs[i].dirty, regs[i].wasdirty, unneeded_reg[i],
6138 regs[i].isconst, regs[i].wasconst, regs[i].loadedconst);
2acc46cd 6139 print_regmap("pre: ", regmap_pre[i]);
6140 print_regmap("entry: ", regs[i].regmap_entry);
6141 print_regmap("map: ", regs[i].regmap);
6142 if (dops[i].is_jump) {
6143 print_regmap("bentry:", branch_regs[i].regmap_entry);
6144 print_regmap("bmap: ", branch_regs[i].regmap);
6145 }
57871462 6146}
4600ba03 6147#else
53dc27f6 6148#define set_mnemonic(i_, n_)
4600ba03 6149static void disassemble_inst(int i) {}
6150#endif // DISASM
57871462 6151
d848b60a 6152#define DRC_TEST_VAL 0x74657374
6153
d9e2b173 6154static noinline void new_dynarec_test(void)
d848b60a 6155{
be516ebe 6156 int (*testfunc)(void);
d148d265 6157 void *beginning;
be516ebe 6158 int ret[2];
6159 size_t i;
d148d265 6160
687b4580 6161 // check structure linkage
7c3a5182 6162 if ((u_char *)rcnts - (u_char *)&psxRegs != sizeof(psxRegs))
687b4580 6163 {
7c3a5182 6164 SysPrintf("linkage_arm* miscompilation/breakage detected.\n");
687b4580 6165 }
6166
d9e2b173 6167 SysPrintf("(%p) testing if we can run recompiled code @%p...\n",
6168 new_dynarec_test, out);
6169 ((volatile u_int *)NDRC_WRITE_OFFSET(out))[0]++; // make the cache dirty
be516ebe 6170
6171 for (i = 0; i < ARRAY_SIZE(ret); i++) {
2a014d73 6172 out = ndrc->translation_cache;
be516ebe 6173 beginning = start_block();
6174 emit_movimm(DRC_TEST_VAL + i, 0); // test
6175 emit_ret();
6176 literal_pool(0);
6177 end_block(beginning);
6178 testfunc = beginning;
6179 ret[i] = testfunc();
6180 }
6181
6182 if (ret[0] == DRC_TEST_VAL && ret[1] == DRC_TEST_VAL + 1)
d848b60a 6183 SysPrintf("test passed.\n");
6184 else
be516ebe 6185 SysPrintf("test failed, will likely crash soon (r=%08x %08x)\n", ret[0], ret[1]);
2a014d73 6186 out = ndrc->translation_cache;
d848b60a 6187}
6188
dc990066 6189// clear the state completely, instead of just marking
6190// things invalid like invalidate_all_pages() does
919981d0 6191void new_dynarec_clear_full(void)
57871462 6192{
57871462 6193 int n;
2a014d73 6194 out = ndrc->translation_cache;
35775df7 6195 memset(invalid_code,1,sizeof(invalid_code));
6196 memset(hash_table,0xff,sizeof(hash_table));
57871462 6197 memset(mini_ht,-1,sizeof(mini_ht));
dc990066 6198 memset(shadow,0,sizeof(shadow));
57871462 6199 copy=shadow;
93c0345b 6200 expirep = EXPIRITY_OFFSET;
57871462 6201 pending_exception=0;
6202 literalcount=0;
57871462 6203 stop_after_jal=0;
9be4ba64 6204 inv_code_start=inv_code_end=~0;
7f94b097 6205 hack_addr=0;
39b71d9a 6206 f1_hack=0;
93c0345b 6207 for (n = 0; n < ARRAY_SIZE(blocks); n++)
6208 blocks_clear(&blocks[n]);
b7ad2f2c 6209 for (n = 0; n < ARRAY_SIZE(jumps); n++) {
6210 free(jumps[n]);
6211 jumps[n] = NULL;
6212 }
104df9d3 6213 stat_clear(stat_blocks);
6214 stat_clear(stat_links);
32631e6a 6215
d5aeda23 6216 cycle_multiplier_old = Config.cycle_multiplier;
32631e6a 6217 new_dynarec_hacks_old = new_dynarec_hacks;
dc990066 6218}
6219
919981d0 6220void new_dynarec_init(void)
dc990066 6221{
66ea165f 6222 SysPrintf("Init new dynarec, ndrc size %x\n", (int)sizeof(*ndrc));
1e212a25 6223
0aeb0cb9 6224#ifdef _3DS
6225 check_rosalina();
6226#endif
2a014d73 6227#ifdef BASE_ADDR_DYNAMIC
1e212a25 6228 #ifdef VITA
0aeb0cb9 6229 sceBlock = getVMBlock(); //sceKernelAllocMemBlockForVM("code", sizeof(*ndrc));
66ea165f 6230 if (sceBlock <= 0)
6231 SysPrintf("sceKernelAllocMemBlockForVM failed: %x\n", sceBlock);
2a014d73 6232 int ret = sceKernelGetMemBlockBase(sceBlock, (void **)&ndrc);
1e212a25 6233 if (ret < 0)
66ea165f 6234 SysPrintf("sceKernelGetMemBlockBase failed: %x\n", ret);
0aeb0cb9 6235 sceKernelOpenVMDomain();
6236 sceClibPrintf("translation_cache = 0x%08lx\n ", (long)ndrc->translation_cache);
6237 #elif defined(_MSC_VER)
6238 ndrc = VirtualAlloc(NULL, sizeof(*ndrc), MEM_COMMIT | MEM_RESERVE,
6239 PAGE_EXECUTE_READWRITE);
3039c914 6240 #elif defined(HAVE_LIBNX)
6241 Result rc = jitCreate(&g_jit, sizeof(*ndrc));
6242 if (R_FAILED(rc))
6243 SysPrintf("jitCreate failed: %08x\n", rc);
6244 SysPrintf("jitCreate: RX: %p RW: %p type: %d\n", g_jit.rx_addr, g_jit.rw_addr, g_jit.type);
d9e2b173 6245 jitTransitionToWritable(&g_jit);
3039c914 6246 ndrc = g_jit.rx_addr;
6247 ndrc_write_ofs = (char *)g_jit.rw_addr - (char *)ndrc;
d9e2b173 6248 memset(NDRC_WRITE_OFFSET(&ndrc->tramp), 0, sizeof(ndrc->tramp));
1e212a25 6249 #else
2a014d73 6250 uintptr_t desired_addr = 0;
3039c914 6251 int prot = PROT_READ | PROT_WRITE | PROT_EXEC;
6252 int flags = MAP_PRIVATE | MAP_ANONYMOUS;
6253 int fd = -1;
2a014d73 6254 #ifdef __ELF__
6255 extern char _end;
6256 desired_addr = ((uintptr_t)&_end + 0xffffff) & ~0xffffffl;
6257 #endif
d9e2b173 6258 #ifdef TC_WRITE_OFFSET
3039c914 6259 // mostly for testing
6260 fd = open("/dev/shm/pcsxr", O_CREAT | O_RDWR, 0600);
6261 ftruncate(fd, sizeof(*ndrc));
6262 void *mw = mmap(NULL, sizeof(*ndrc), PROT_READ | PROT_WRITE,
6263 (flags = MAP_SHARED), fd, 0);
6264 assert(mw != MAP_FAILED);
6265 prot = PROT_READ | PROT_EXEC;
6266 #endif
6267 ndrc = mmap((void *)desired_addr, sizeof(*ndrc), prot, flags, fd, 0);
2a014d73 6268 if (ndrc == MAP_FAILED) {
d848b60a 6269 SysPrintf("mmap() failed: %s\n", strerror(errno));
1e212a25 6270 abort();
d848b60a 6271 }
d9e2b173 6272 #ifdef TC_WRITE_OFFSET
3039c914 6273 ndrc_write_ofs = (char *)mw - (char *)ndrc;
6274 #endif
1e212a25 6275 #endif
6276#else
6277 #ifndef NO_WRITE_EXEC
bdeade46 6278 // not all systems allow execute in data segment by default
761fdd0a 6279 // size must be 4K aligned for 3DS?
6280 if (mprotect(ndrc, sizeof(*ndrc),
2a014d73 6281 PROT_READ | PROT_WRITE | PROT_EXEC) != 0)
d848b60a 6282 SysPrintf("mprotect() failed: %s\n", strerror(errno));
1e212a25 6283 #endif
dc990066 6284#endif
2a014d73 6285 out = ndrc->translation_cache;
dc990066 6286 new_dynarec_clear_full();
6287#ifdef HOST_IMM8
6288 // Copy this into local area so we don't have to put it in every literal pool
6289 invc_ptr=invalid_code;
6290#endif
57871462 6291 arch_init();
d848b60a 6292 new_dynarec_test();
33a1eda1 6293 ram_offset = (uintptr_t)psxM - 0x80000000;
b105cf4f 6294 if (ram_offset!=0)
c43b5311 6295 SysPrintf("warning: RAM is not directly mapped, performance will suffer\n");
398d6924 6296 SysPrintf("Mapped (RAM/scrp/ROM/LUTs/TC):\n");
6297 SysPrintf("%p/%p/%p/%p/%p\n", psxM, psxH, psxR, mem_rtab, out);
57871462 6298}
6299
919981d0 6300void new_dynarec_cleanup(void)
57871462 6301{
6302 int n;
2a014d73 6303#ifdef BASE_ADDR_DYNAMIC
1e212a25 6304 #ifdef VITA
66ea165f 6305 // sceBlock is managed by retroarch's bootstrap code
9c67c98f 6306 //sceKernelFreeMemBlock(sceBlock);
6307 //sceBlock = -1;
3039c914 6308 #elif defined(HAVE_LIBNX)
6309 jitClose(&g_jit);
6310 ndrc = NULL;
1e212a25 6311 #else
2a014d73 6312 if (munmap(ndrc, sizeof(*ndrc)) < 0)
1e212a25 6313 SysPrintf("munmap() failed\n");
3039c914 6314 ndrc = NULL;
bdeade46 6315 #endif
1e212a25 6316#endif
93c0345b 6317 for (n = 0; n < ARRAY_SIZE(blocks); n++)
6318 blocks_clear(&blocks[n]);
b7ad2f2c 6319 for (n = 0; n < ARRAY_SIZE(jumps); n++) {
6320 free(jumps[n]);
6321 jumps[n] = NULL;
6322 }
104df9d3 6323 stat_clear(stat_blocks);
6324 stat_clear(stat_links);
ece032e6 6325 new_dynarec_print_stats();
57871462 6326}
6327
03f55e6b 6328static u_int *get_source_start(u_int addr, u_int *limit)
57871462 6329{
33a1eda1 6330 if (addr < 0x00800000
6331 || (0x80000000 <= addr && addr < 0x80800000)
6332 || (0xa0000000 <= addr && addr < 0xa0800000))
a3203cf4 6333 {
03f55e6b 6334 // used for BIOS calls mostly?
33a1eda1 6335 *limit = (addr & 0xa0600000) + 0x00200000;
6336 return (u_int *)(psxM + (addr & 0x1fffff));
03f55e6b 6337 }
6338 else if (!Config.HLE && (
6339 /* (0x9fc00000 <= addr && addr < 0x9fc80000) ||*/
a3203cf4 6340 (0xbfc00000 <= addr && addr < 0xbfc80000)))
6341 {
6342 // BIOS. The multiplier should be much higher as it's uncached 8bit mem,
d5aeda23 6343 // but timings in PCSX are too tied to the interpreter's 2-per-insn assumption
d62c125a 6344 if (!HACK_ENABLED(NDHACK_OVERRIDE_CYCLE_M))
24058131 6345 cycle_multiplier_active = 200;
a3203cf4 6346
03f55e6b 6347 *limit = (addr & 0xfff00000) | 0x80000;
01d26796 6348 return (u_int *)((u_char *)psxR + (addr&0x7ffff));
03f55e6b 6349 }
581335b0 6350 return NULL;
03f55e6b 6351}
6352
6353static u_int scan_for_ret(u_int addr)
6354{
6355 u_int limit = 0;
6356 u_int *mem;
6357
6358 mem = get_source_start(addr, &limit);
6359 if (mem == NULL)
6360 return addr;
6361
6362 if (limit > addr + 0x1000)
6363 limit = addr + 0x1000;
6364 for (; addr < limit; addr += 4, mem++) {
6365 if (*mem == 0x03e00008) // jr $ra
6366 return addr + 8;
57871462 6367 }
581335b0 6368 return addr;
03f55e6b 6369}
6370
6371struct savestate_block {
6372 uint32_t addr;
6373 uint32_t regflags;
6374};
6375
6376static int addr_cmp(const void *p1_, const void *p2_)
6377{
6378 const struct savestate_block *p1 = p1_, *p2 = p2_;
6379 return p1->addr - p2->addr;
6380}
6381
6382int new_dynarec_save_blocks(void *save, int size)
6383{
104df9d3 6384 struct savestate_block *sblocks = save;
6385 int maxcount = size / sizeof(sblocks[0]);
03f55e6b 6386 struct savestate_block tmp_blocks[1024];
104df9d3 6387 struct block_info *block;
03f55e6b 6388 int p, s, d, o, bcnt;
6389 u_int addr;
6390
6391 o = 0;
104df9d3 6392 for (p = 0; p < ARRAY_SIZE(blocks); p++) {
03f55e6b 6393 bcnt = 0;
104df9d3 6394 for (block = blocks[p]; block != NULL; block = block->next) {
6395 if (block->is_dirty)
6396 continue;
6397 tmp_blocks[bcnt].addr = block->start;
6398 tmp_blocks[bcnt].regflags = block->reg_sv_flags;
03f55e6b 6399 bcnt++;
6400 }
6401 if (bcnt < 1)
6402 continue;
6403 qsort(tmp_blocks, bcnt, sizeof(tmp_blocks[0]), addr_cmp);
6404
6405 addr = tmp_blocks[0].addr;
6406 for (s = d = 0; s < bcnt; s++) {
6407 if (tmp_blocks[s].addr < addr)
6408 continue;
6409 if (d == 0 || tmp_blocks[d-1].addr != tmp_blocks[s].addr)
6410 tmp_blocks[d++] = tmp_blocks[s];
6411 addr = scan_for_ret(tmp_blocks[s].addr);
6412 }
6413
6414 if (o + d > maxcount)
6415 d = maxcount - o;
104df9d3 6416 memcpy(&sblocks[o], tmp_blocks, d * sizeof(sblocks[0]));
03f55e6b 6417 o += d;
6418 }
6419
104df9d3 6420 return o * sizeof(sblocks[0]);
03f55e6b 6421}
6422
6423void new_dynarec_load_blocks(const void *save, int size)
6424{
104df9d3 6425 const struct savestate_block *sblocks = save;
6426 int count = size / sizeof(sblocks[0]);
6427 struct block_info *block;
03f55e6b 6428 u_int regs_save[32];
104df9d3 6429 u_int page;
03f55e6b 6430 uint32_t f;
6431 int i, b;
6432
104df9d3 6433 // restore clean blocks, if any
6434 for (page = 0, b = i = 0; page < ARRAY_SIZE(blocks); page++) {
6435 for (block = blocks[page]; block != NULL; block = block->next, b++) {
6436 if (!block->is_dirty)
6437 continue;
6438 assert(block->source && block->copy);
6439 if (memcmp(block->source, block->copy, block->len))
6440 continue;
6441
6442 // see try_restore_block
6443 block->is_dirty = 0;
6444 mark_invalid_code(block->start, block->len, 0);
6445 i++;
6446 }
6447 }
6448 inv_debug("load_blocks: %d/%d clean blocks\n", i, b);
03f55e6b 6449
6450 // change GPRs for speculation to at least partially work..
6451 memcpy(regs_save, &psxRegs.GPR, sizeof(regs_save));
6452 for (i = 1; i < 32; i++)
6453 psxRegs.GPR.r[i] = 0x80000000;
6454
6455 for (b = 0; b < count; b++) {
104df9d3 6456 for (f = sblocks[b].regflags, i = 0; f; f >>= 1, i++) {
03f55e6b 6457 if (f & 1)
6458 psxRegs.GPR.r[i] = 0x1f800000;
6459 }
6460
104df9d3 6461 ndrc_get_addr_ht(sblocks[b].addr);
03f55e6b 6462
104df9d3 6463 for (f = sblocks[b].regflags, i = 0; f; f >>= 1, i++) {
03f55e6b 6464 if (f & 1)
6465 psxRegs.GPR.r[i] = 0x80000000;
6466 }
6467 }
6468
6469 memcpy(&psxRegs.GPR, regs_save, sizeof(regs_save));
6470}
6471
ece032e6 6472void new_dynarec_print_stats(void)
6473{
6474#ifdef STAT_PRINT
104df9d3 6475 printf("cc %3d,%3d,%3d lu%6d,%3d,%3d c%3d inv%3d,%3d tc_offs %zu b %u,%u\n",
ece032e6 6476 stat_bc_pre, stat_bc_direct, stat_bc_restore,
104df9d3 6477 stat_ht_lookups, stat_jump_in_lookups, stat_restore_tries,
6478 stat_restore_compares, stat_inv_addr_calls, stat_inv_hits,
6479 out - ndrc->translation_cache, stat_blocks, stat_links);
ece032e6 6480 stat_bc_direct = stat_bc_pre = stat_bc_restore =
104df9d3 6481 stat_ht_lookups = stat_jump_in_lookups = stat_restore_tries =
6482 stat_restore_compares = stat_inv_addr_calls = stat_inv_hits = 0;
ece032e6 6483#endif
6484}
6485
7f94b097 6486static int apply_hacks(void)
24058131 6487{
6488 int i;
6489 if (HACK_ENABLED(NDHACK_NO_COMPAT_HACKS))
7f94b097 6490 return 0;
24058131 6491 /* special hack(s) */
6492 for (i = 0; i < slen - 4; i++)
6493 {
6494 // lui a4, 0xf200; jal <rcnt_read>; addu a0, 2; slti v0, 28224
6495 if (source[i] == 0x3c04f200 && dops[i+1].itype == UJUMP
6496 && source[i+2] == 0x34840002 && dops[i+3].opcode == 0x0a
277718fa 6497 && cinfo[i+3].imm == 0x6e40 && dops[i+3].rs1 == 2)
24058131 6498 {
6499 SysPrintf("PE2 hack @%08x\n", start + (i+3)*4);
6500 dops[i + 3].itype = NOP;
6501 }
6502 }
6503 i = slen;
6504 if (i > 10 && source[i-1] == 0 && source[i-2] == 0x03e00008
6505 && source[i-4] == 0x8fbf0018 && source[i-6] == 0x00c0f809
6506 && dops[i-7].itype == STORE)
6507 {
6508 i = i-8;
6509 if (dops[i].itype == IMM16)
6510 i--;
6511 // swl r2, 15(r6); swr r2, 12(r6); sw r6, *; jalr r6
6512 if (dops[i].itype == STORELR && dops[i].rs1 == 6
6513 && dops[i-1].itype == STORELR && dops[i-1].rs1 == 6)
6514 {
7f94b097 6515 SysPrintf("F1 hack from %08x, old dst %08x\n", start, hack_addr);
6516 f1_hack = 1;
6517 return 1;
24058131 6518 }
6519 }
7f94b097 6520 return 0;
24058131 6521}
6522
de6dbc52 6523static int is_ld_use_hazard(int ld_rt, const struct decoded_insn *op)
03f55e6b 6524{
de6dbc52 6525 return ld_rt != 0 && (ld_rt == op->rs1 || ld_rt == op->rs2)
6526 && op->itype != LOADLR && op->itype != CJUMP && op->itype != SJUMP;
6527}
57871462 6528
de6dbc52 6529static void force_intcall(int i)
6530{
6531 memset(&dops[i], 0, sizeof(dops[i]));
6532 dops[i].itype = INTCALL;
6533 dops[i].rs1 = CCREG;
6534 dops[i].is_exception = 1;
6535 cinfo[i].ba = -1;
6536}
6537
6538static void disassemble_one(int i, u_int src)
6539{
6540 unsigned int type, op, op2, op3;
a22ccd6a 6541 enum ls_width_type ls_type = LS_32;
7ebfcedf 6542 memset(&dops[i], 0, sizeof(dops[i]));
277718fa 6543 memset(&cinfo[i], 0, sizeof(cinfo[i]));
6544 cinfo[i].ba = -1;
6545 cinfo[i].addr = -1;
de6dbc52 6546 dops[i].opcode = op = src >> 26;
277718fa 6547 op2 = 0;
a5cd72d0 6548 type = INTCALL;
6549 set_mnemonic(i, "???");
57871462 6550 switch(op)
6551 {
a5cd72d0 6552 case 0x00: set_mnemonic(i, "special");
de6dbc52 6553 op2 = src & 0x3f;
57871462 6554 switch(op2)
6555 {
53dc27f6 6556 case 0x00: set_mnemonic(i, "SLL"); type=SHIFTIMM; break;
6557 case 0x02: set_mnemonic(i, "SRL"); type=SHIFTIMM; break;
6558 case 0x03: set_mnemonic(i, "SRA"); type=SHIFTIMM; break;
6559 case 0x04: set_mnemonic(i, "SLLV"); type=SHIFT; break;
6560 case 0x06: set_mnemonic(i, "SRLV"); type=SHIFT; break;
6561 case 0x07: set_mnemonic(i, "SRAV"); type=SHIFT; break;
6562 case 0x08: set_mnemonic(i, "JR"); type=RJUMP; break;
6563 case 0x09: set_mnemonic(i, "JALR"); type=RJUMP; break;
6564 case 0x0C: set_mnemonic(i, "SYSCALL"); type=SYSCALL; break;
6565 case 0x0D: set_mnemonic(i, "BREAK"); type=SYSCALL; break;
53dc27f6 6566 case 0x10: set_mnemonic(i, "MFHI"); type=MOV; break;
6567 case 0x11: set_mnemonic(i, "MTHI"); type=MOV; break;
6568 case 0x12: set_mnemonic(i, "MFLO"); type=MOV; break;
6569 case 0x13: set_mnemonic(i, "MTLO"); type=MOV; break;
6570 case 0x18: set_mnemonic(i, "MULT"); type=MULTDIV; break;
6571 case 0x19: set_mnemonic(i, "MULTU"); type=MULTDIV; break;
6572 case 0x1A: set_mnemonic(i, "DIV"); type=MULTDIV; break;
6573 case 0x1B: set_mnemonic(i, "DIVU"); type=MULTDIV; break;
6574 case 0x20: set_mnemonic(i, "ADD"); type=ALU; break;
6575 case 0x21: set_mnemonic(i, "ADDU"); type=ALU; break;
6576 case 0x22: set_mnemonic(i, "SUB"); type=ALU; break;
6577 case 0x23: set_mnemonic(i, "SUBU"); type=ALU; break;
6578 case 0x24: set_mnemonic(i, "AND"); type=ALU; break;
6579 case 0x25: set_mnemonic(i, "OR"); type=ALU; break;
6580 case 0x26: set_mnemonic(i, "XOR"); type=ALU; break;
6581 case 0x27: set_mnemonic(i, "NOR"); type=ALU; break;
6582 case 0x2A: set_mnemonic(i, "SLT"); type=ALU; break;
6583 case 0x2B: set_mnemonic(i, "SLTU"); type=ALU; break;
57871462 6584 }
6585 break;
a5cd72d0 6586 case 0x01: set_mnemonic(i, "regimm");
6587 type = SJUMP;
de6dbc52 6588 op2 = (src >> 16) & 0x1f;
57871462 6589 switch(op2)
6590 {
a5cd72d0 6591 case 0x10: set_mnemonic(i, "BLTZAL"); break;
6592 case 0x11: set_mnemonic(i, "BGEZAL"); break;
6593 default:
6594 if (op2 & 1)
6595 set_mnemonic(i, "BGEZ");
6596 else
6597 set_mnemonic(i, "BLTZ");
57871462 6598 }
6599 break;
53dc27f6 6600 case 0x02: set_mnemonic(i, "J"); type=UJUMP; break;
6601 case 0x03: set_mnemonic(i, "JAL"); type=UJUMP; break;
6602 case 0x04: set_mnemonic(i, "BEQ"); type=CJUMP; break;
6603 case 0x05: set_mnemonic(i, "BNE"); type=CJUMP; break;
6604 case 0x06: set_mnemonic(i, "BLEZ"); type=CJUMP; break;
6605 case 0x07: set_mnemonic(i, "BGTZ"); type=CJUMP; break;
6606 case 0x08: set_mnemonic(i, "ADDI"); type=IMM16; break;
6607 case 0x09: set_mnemonic(i, "ADDIU"); type=IMM16; break;
6608 case 0x0A: set_mnemonic(i, "SLTI"); type=IMM16; break;
6609 case 0x0B: set_mnemonic(i, "SLTIU"); type=IMM16; break;
6610 case 0x0C: set_mnemonic(i, "ANDI"); type=IMM16; break;
6611 case 0x0D: set_mnemonic(i, "ORI"); type=IMM16; break;
6612 case 0x0E: set_mnemonic(i, "XORI"); type=IMM16; break;
6613 case 0x0F: set_mnemonic(i, "LUI"); type=IMM16; break;
a5cd72d0 6614 case 0x10: set_mnemonic(i, "COP0");
de6dbc52 6615 op2 = (src >> 21) & 0x1f;
a5cd72d0 6616 if (op2 & 0x10) {
de6dbc52 6617 op3 = src & 0x1f;
a5cd72d0 6618 switch (op3)
6619 {
6620 case 0x01: case 0x02: case 0x06: case 0x08: type = INTCALL; break;
6621 case 0x10: set_mnemonic(i, "RFE"); type=RFE; break;
6622 default: type = OTHER; break;
6623 }
6624 break;
6625 }
57871462 6626 switch(op2)
6627 {
a5cd72d0 6628 u32 rd;
6629 case 0x00:
6630 set_mnemonic(i, "MFC0");
de6dbc52 6631 rd = (src >> 11) & 0x1F;
a5cd72d0 6632 if (!(0x00000417u & (1u << rd)))
6633 type = COP0;
6634 break;
53dc27f6 6635 case 0x04: set_mnemonic(i, "MTC0"); type=COP0; break;
a5cd72d0 6636 case 0x02:
6637 case 0x06: type = INTCALL; break;
6638 default: type = OTHER; break;
57871462 6639 }
6640 break;
a5cd72d0 6641 case 0x11: set_mnemonic(i, "COP1");
de6dbc52 6642 op2 = (src >> 21) & 0x1f;
57871462 6643 break;
a5cd72d0 6644 case 0x12: set_mnemonic(i, "COP2");
de6dbc52 6645 op2 = (src >> 21) & 0x1f;
a5cd72d0 6646 if (op2 & 0x10) {
6647 type = OTHER;
de6dbc52 6648 if (gte_handlers[src & 0x3f] != NULL) {
53dc27f6 6649#ifdef DISASM
de6dbc52 6650 if (gte_regnames[src & 0x3f] != NULL)
6651 strcpy(insn[i], gte_regnames[src & 0x3f]);
bedfea38 6652 else
de6dbc52 6653 snprintf(insn[i], sizeof(insn[i]), "COP2 %x", src & 0x3f);
53dc27f6 6654#endif
a5cd72d0 6655 type = C2OP;
c7abc864 6656 }
6657 }
6658 else switch(op2)
b9b61529 6659 {
53dc27f6 6660 case 0x00: set_mnemonic(i, "MFC2"); type=COP2; break;
6661 case 0x02: set_mnemonic(i, "CFC2"); type=COP2; break;
6662 case 0x04: set_mnemonic(i, "MTC2"); type=COP2; break;
6663 case 0x06: set_mnemonic(i, "CTC2"); type=COP2; break;
b9b61529 6664 }
6665 break;
a5cd72d0 6666 case 0x13: set_mnemonic(i, "COP3");
de6dbc52 6667 op2 = (src >> 21) & 0x1f;
a5cd72d0 6668 break;
f9e9616e 6669 case 0x20: set_mnemonic(i, "LB"); type=LOAD; ls_type = LS_8; break;
6670 case 0x21: set_mnemonic(i, "LH"); type=LOAD; ls_type = LS_16; break;
6671 case 0x22: set_mnemonic(i, "LWL"); type=LOADLR; ls_type = LS_LR; break;
6672 case 0x23: set_mnemonic(i, "LW"); type=LOAD; ls_type = LS_32; break;
6673 case 0x24: set_mnemonic(i, "LBU"); type=LOAD; ls_type = LS_8; break;
6674 case 0x25: set_mnemonic(i, "LHU"); type=LOAD; ls_type = LS_16; break;
6675 case 0x26: set_mnemonic(i, "LWR"); type=LOADLR; ls_type = LS_LR; break;
6676 case 0x28: set_mnemonic(i, "SB"); type=STORE; ls_type = LS_8; break;
6677 case 0x29: set_mnemonic(i, "SH"); type=STORE; ls_type = LS_16; break;
6678 case 0x2A: set_mnemonic(i, "SWL"); type=STORELR; ls_type = LS_LR; break;
6679 case 0x2B: set_mnemonic(i, "SW"); type=STORE; ls_type = LS_32; break;
6680 case 0x2E: set_mnemonic(i, "SWR"); type=STORELR; ls_type = LS_LR; break;
6681 case 0x32: set_mnemonic(i, "LWC2"); type=C2LS; ls_type = LS_32; break;
6682 case 0x3A: set_mnemonic(i, "SWC2"); type=C2LS; ls_type = LS_32; break;
a5cd72d0 6683 case 0x3B:
de6dbc52 6684 if (Config.HLE && (src & 0x03ffffff) < ARRAY_SIZE(psxHLEt)) {
a5cd72d0 6685 set_mnemonic(i, "HLECALL");
6686 type = HLECALL;
6687 }
6688 break;
6689 default:
90ae6d4e 6690 break;
57871462 6691 }
a5cd72d0 6692 if (type == INTCALL)
de6dbc52 6693 SysPrintf("NI %08x @%08x (%08x)\n", src, start + i*4, start);
f9e9616e 6694 dops[i].itype = type;
6695 dops[i].opcode2 = op2;
6696 dops[i].ls_type = ls_type;
57871462 6697 /* Get registers/immediates */
53dc27f6 6698 dops[i].use_lt1=0;
bedfea38 6699 gte_rs[i]=gte_rt[i]=0;
a5cd72d0 6700 dops[i].rs1 = 0;
6701 dops[i].rs2 = 0;
6702 dops[i].rt1 = 0;
6703 dops[i].rt2 = 0;
57871462 6704 switch(type) {
6705 case LOAD:
de6dbc52 6706 dops[i].rs1 = (src >> 21) & 0x1f;
6707 dops[i].rt1 = (src >> 16) & 0x1f;
6708 cinfo[i].imm = (short)src;
57871462 6709 break;
6710 case STORE:
6711 case STORELR:
de6dbc52 6712 dops[i].rs1 = (src >> 21) & 0x1f;
6713 dops[i].rs2 = (src >> 16) & 0x1f;
6714 cinfo[i].imm = (short)src;
57871462 6715 break;
6716 case LOADLR:
6717 // LWL/LWR only load part of the register,
6718 // therefore the target register must be treated as a source too
de6dbc52 6719 dops[i].rs1 = (src >> 21) & 0x1f;
6720 dops[i].rs2 = (src >> 16) & 0x1f;
6721 dops[i].rt1 = (src >> 16) & 0x1f;
6722 cinfo[i].imm = (short)src;
57871462 6723 break;
6724 case IMM16:
cf95b4f0 6725 if (op==0x0f) dops[i].rs1=0; // LUI instruction has no source register
de6dbc52 6726 else dops[i].rs1 = (src >> 21) & 0x1f;
6727 dops[i].rs2 = 0;
6728 dops[i].rt1 = (src >> 16) & 0x1f;
57871462 6729 if(op>=0x0c&&op<=0x0e) { // ANDI/ORI/XORI
de6dbc52 6730 cinfo[i].imm = (unsigned short)src;
57871462 6731 }else{
de6dbc52 6732 cinfo[i].imm = (short)src;
57871462 6733 }
57871462 6734 break;
6735 case UJUMP:
57871462 6736 // The JAL instruction writes to r31.
6737 if (op&1) {
cf95b4f0 6738 dops[i].rt1=31;
57871462 6739 }
cf95b4f0 6740 dops[i].rs2=CCREG;
57871462 6741 break;
6742 case RJUMP:
de6dbc52 6743 dops[i].rs1 = (src >> 21) & 0x1f;
5067f341 6744 // The JALR instruction writes to rd.
57871462 6745 if (op2&1) {
de6dbc52 6746 dops[i].rt1 = (src >> 11) & 0x1f;
57871462 6747 }
cf95b4f0 6748 dops[i].rs2=CCREG;
57871462 6749 break;
6750 case CJUMP:
de6dbc52 6751 dops[i].rs1 = (src >> 21) & 0x1f;
6752 dops[i].rs2 = (src >> 16) & 0x1f;
57871462 6753 if(op&2) { // BGTZ/BLEZ
cf95b4f0 6754 dops[i].rs2=0;
57871462 6755 }
57871462 6756 break;
6757 case SJUMP:
de6dbc52 6758 dops[i].rs1 = (src >> 21) & 0x1f;
6759 dops[i].rs2 = CCREG;
a5cd72d0 6760 if (op2 == 0x10 || op2 == 0x11) { // BxxAL
6761 dops[i].rt1 = 31;
57871462 6762 // NOTE: If the branch is not taken, r31 is still overwritten
6763 }
57871462 6764 break;
57871462 6765 case ALU:
de6dbc52 6766 dops[i].rs1=(src>>21)&0x1f; // source
6767 dops[i].rs2=(src>>16)&0x1f; // subtract amount
6768 dops[i].rt1=(src>>11)&0x1f; // destination
57871462 6769 break;
6770 case MULTDIV:
de6dbc52 6771 dops[i].rs1=(src>>21)&0x1f; // source
6772 dops[i].rs2=(src>>16)&0x1f; // divisor
cf95b4f0 6773 dops[i].rt1=HIREG;
6774 dops[i].rt2=LOREG;
57871462 6775 break;
6776 case MOV:
cf95b4f0 6777 if(op2==0x10) dops[i].rs1=HIREG; // MFHI
6778 if(op2==0x11) dops[i].rt1=HIREG; // MTHI
6779 if(op2==0x12) dops[i].rs1=LOREG; // MFLO
6780 if(op2==0x13) dops[i].rt1=LOREG; // MTLO
de6dbc52 6781 if((op2&0x1d)==0x10) dops[i].rt1=(src>>11)&0x1f; // MFxx
6782 if((op2&0x1d)==0x11) dops[i].rs1=(src>>21)&0x1f; // MTxx
57871462 6783 break;
6784 case SHIFT:
de6dbc52 6785 dops[i].rs1=(src>>16)&0x1f; // target of shift
6786 dops[i].rs2=(src>>21)&0x1f; // shift amount
6787 dops[i].rt1=(src>>11)&0x1f; // destination
57871462 6788 break;
6789 case SHIFTIMM:
de6dbc52 6790 dops[i].rs1=(src>>16)&0x1f;
cf95b4f0 6791 dops[i].rs2=0;
de6dbc52 6792 dops[i].rt1=(src>>11)&0x1f;
6793 cinfo[i].imm=(src>>6)&0x1f;
57871462 6794 break;
6795 case COP0:
de6dbc52 6796 if(op2==0) dops[i].rt1=(src>>16)&0x1F; // MFC0
6797 if(op2==4) dops[i].rs1=(src>>16)&0x1F; // MTC0
6798 if(op2==4&&((src>>11)&0x1e)==12) dops[i].rs2=CCREG;
57871462 6799 break;
bedfea38 6800 case COP2:
de6dbc52 6801 if(op2<3) dops[i].rt1=(src>>16)&0x1F; // MFC2/CFC2
6802 if(op2>3) dops[i].rs1=(src>>16)&0x1F; // MTC2/CTC2
6803 int gr=(src>>11)&0x1F;
bedfea38 6804 switch(op2)
6805 {
6806 case 0x00: gte_rs[i]=1ll<<gr; break; // MFC2
6807 case 0x04: gte_rt[i]=1ll<<gr; break; // MTC2
0ff8c62c 6808 case 0x02: gte_rs[i]=1ll<<(gr+32); break; // CFC2
bedfea38 6809 case 0x06: gte_rt[i]=1ll<<(gr+32); break; // CTC2
6810 }
6811 break;
b9b61529 6812 case C2LS:
de6dbc52 6813 dops[i].rs1=(src>>21)&0x1F;
6814 cinfo[i].imm=(short)src;
6815 if(op==0x32) gte_rt[i]=1ll<<((src>>16)&0x1F); // LWC2
6816 else gte_rs[i]=1ll<<((src>>16)&0x1F); // SWC2
bedfea38 6817 break;
6818 case C2OP:
de6dbc52 6819 gte_rs[i]=gte_reg_reads[src&0x3f];
6820 gte_rt[i]=gte_reg_writes[src&0x3f];
2167bef6 6821 gte_rt[i]|=1ll<<63; // every op changes flags
de6dbc52 6822 if((src&0x3f)==GTE_MVMVA) {
6823 int v = (src >> 15) & 3;
587a5b1c 6824 gte_rs[i]&=~0xe3fll;
6825 if(v==3) gte_rs[i]|=0xe00ll;
6826 else gte_rs[i]|=3ll<<(v*2);
6827 }
b9b61529 6828 break;
57871462 6829 case SYSCALL:
7139f3c8 6830 case HLECALL:
1e973cb0 6831 case INTCALL:
cf95b4f0 6832 dops[i].rs1=CCREG;
57871462 6833 break;
6834 default:
a5cd72d0 6835 break;
57871462 6836 }
de6dbc52 6837}
6838
6839static noinline void pass1_disassemble(u_int pagelimit)
6840{
6841 int i, j, done = 0, ni_count = 0;
f9e9616e 6842 int ds_next = 0;
de6dbc52 6843
6844 for (i = 0; !done; i++)
6845 {
6846 int force_j_to_interpreter = 0;
6847 unsigned int type, op, op2;
6848
6849 disassemble_one(i, source[i]);
f9e9616e 6850 dops[i].is_ds = ds_next; ds_next = 0;
de6dbc52 6851 type = dops[i].itype;
6852 op = dops[i].opcode;
6853 op2 = dops[i].opcode2;
6854
57871462 6855 /* Calculate branch target addresses */
6856 if(type==UJUMP)
277718fa 6857 cinfo[i].ba=((start+i*4+4)&0xF0000000)|(((unsigned int)source[i]<<6)>>4);
cf95b4f0 6858 else if(type==CJUMP&&dops[i].rs1==dops[i].rs2&&(op&1))
277718fa 6859 cinfo[i].ba=start+i*4+8; // Ignore never taken branch
cf95b4f0 6860 else if(type==SJUMP&&dops[i].rs1==0&&!(op2&1))
277718fa 6861 cinfo[i].ba=start+i*4+8; // Ignore never taken branch
ad49de89 6862 else if(type==CJUMP||type==SJUMP)
277718fa 6863 cinfo[i].ba=start+i*4+4+((signed int)((unsigned int)source[i]<<16)>>14);
4919de1e 6864
6865 /* simplify always (not)taken branches */
cf95b4f0 6866 if (type == CJUMP && dops[i].rs1 == dops[i].rs2) {
6867 dops[i].rs1 = dops[i].rs2 = 0;
4919de1e 6868 if (!(op & 1)) {
cf95b4f0 6869 dops[i].itype = type = UJUMP;
6870 dops[i].rs2 = CCREG;
4919de1e 6871 }
6872 }
cf95b4f0 6873 else if (type == SJUMP && dops[i].rs1 == 0 && (op2 & 1))
6874 dops[i].itype = type = UJUMP;
4919de1e 6875
277718fa 6876 dops[i].is_jump = type == RJUMP || type == UJUMP || type == CJUMP || type == SJUMP;
6877 dops[i].is_ujump = type == RJUMP || type == UJUMP;
6878 dops[i].is_load = type == LOAD || type == LOADLR || op == 0x32; // LWC2
a5cd72d0 6879 dops[i].is_delay_load = (dops[i].is_load || (source[i] & 0xf3d00000) == 0x40000000); // MFC/CFC
277718fa 6880 dops[i].is_store = type == STORE || type == STORELR || op == 0x3a; // SWC2
6881 dops[i].is_exception = type == SYSCALL || type == HLECALL || type == INTCALL;
6882 dops[i].may_except = dops[i].is_exception || (type == ALU && (op2 == 0x20 || op2 == 0x22)) || op == 8;
f9e9616e 6883 ds_next = dops[i].is_jump;
277718fa 6884
6885 if (((op & 0x37) == 0x21 || op == 0x25) // LH/SH/LHU
6886 && ((cinfo[i].imm & 1) || Config.PreciseExceptions))
6887 dops[i].may_except = 1;
6888 if (((op & 0x37) == 0x23 || (op & 0x37) == 0x32) // LW/SW/LWC2/SWC2
6889 && ((cinfo[i].imm & 3) || Config.PreciseExceptions))
6890 dops[i].may_except = 1;
fe807a8a 6891
a5cd72d0 6892 /* rare messy cases to just pass over to the interpreter */
fe807a8a 6893 if (i > 0 && dops[i-1].is_jump) {
ecca05e3 6894 j = i - 1;
3e535354 6895 // branch in delay slot?
fe807a8a 6896 if (dops[i].is_jump) {
3e535354 6897 // don't handle first branch and call interpreter if it's hit
a5cd72d0 6898 SysPrintf("branch in DS @%08x (%08x)\n", start + i*4, start);
ecca05e3 6899 force_j_to_interpreter = 1;
3e535354 6900 }
de6dbc52 6901 // load delay detection through a branch
a5cd72d0 6902 else if (dops[i].is_delay_load && dops[i].rt1 != 0) {
de6dbc52 6903 const struct decoded_insn *dop = NULL;
6904 int t = -1;
6905 if (cinfo[i-1].ba != -1) {
6906 t = (cinfo[i-1].ba - start) / 4;
6907 if (t < 0 || t > i) {
6908 u_int limit = 0;
6909 u_int *mem = get_source_start(cinfo[i-1].ba, &limit);
6910 if (mem != NULL) {
6911 disassemble_one(MAXBLOCK - 1, mem[0]);
6912 dop = &dops[MAXBLOCK - 1];
6913 }
6914 }
6915 else
6916 dop = &dops[t];
6917 }
6918 if ((dop && is_ld_use_hazard(dops[i].rt1, dop))
6919 || (!dop && Config.PreciseExceptions)) {
3e535354 6920 // jump target wants DS result - potential load delay effect
a5cd72d0 6921 SysPrintf("load delay in DS @%08x (%08x)\n", start + i*4, start);
ecca05e3 6922 force_j_to_interpreter = 1;
de6dbc52 6923 if (0 <= t && t < i)
6924 dops[t + 1].bt = 1; // expected return from interpreter
3e535354 6925 }
cf95b4f0 6926 else if(i>=2&&dops[i-2].rt1==2&&dops[i].rt1==2&&dops[i].rs1!=2&&dops[i].rs2!=2&&dops[i-1].rs1!=2&&dops[i-1].rs2!=2&&
fe807a8a 6927 !(i>=3&&dops[i-3].is_jump)) {
3e535354 6928 // v0 overwrite like this is a sign of trouble, bail out
4149788d 6929 SysPrintf("v0 overwrite @%08x (%08x)\n", start + i*4, start);
ecca05e3 6930 force_j_to_interpreter = 1;
3e535354 6931 }
6932 }
a5cd72d0 6933 }
de6dbc52 6934 else if (i > 0 && dops[i-1].is_delay_load
6935 && is_ld_use_hazard(dops[i-1].rt1, &dops[i])
6936 && (i < 2 || !dops[i-2].is_ujump)) {
a5cd72d0 6937 SysPrintf("load delay @%08x (%08x)\n", start + i*4, start);
ecca05e3 6938 for (j = i - 1; j > 0 && dops[j-1].is_delay_load; j--)
6939 if (dops[j-1].rt1 != dops[i-1].rt1)
6940 break;
6941 force_j_to_interpreter = 1;
a5cd72d0 6942 }
ecca05e3 6943 if (force_j_to_interpreter) {
de6dbc52 6944 force_intcall(j);
a5cd72d0 6945 done = 2;
ecca05e3 6946 i = j; // don't compile the problematic branch/load/etc
3e535354 6947 }
de6dbc52 6948 if (dops[i].is_exception && i > 0 && dops[i-1].is_jump) {
6949 SysPrintf("exception in DS @%08x (%08x)\n", start + i*4, start);
6950 i--;
6951 force_intcall(i);
6952 done = 2;
6953 }
6954 if (i >= 2 && (source[i-2] & 0xffe0f800) == 0x40806000) // MTC0 $12
6955 dops[i].bt = 1;
6956 if (i >= 1 && (source[i-1] & 0xffe0f800) == 0x40806800) // MTC0 $13
6957 dops[i].bt = 1;
4919de1e 6958
3e535354 6959 /* Is this the end of the block? */
fe807a8a 6960 if (i > 0 && dops[i-1].is_ujump) {
0787af86 6961 if (dops[i-1].rt1 == 0) { // not jal
277718fa 6962 int found_bbranch = 0, t = (cinfo[i-1].ba - start) / 4;
0787af86 6963 if ((u_int)(t - i) < 64 && start + (t+64)*4 < pagelimit) {
6964 // scan for a branch back to i+1
6965 for (j = t; j < t + 64; j++) {
6966 int tmpop = source[j] >> 26;
6967 if (tmpop == 1 || ((tmpop & ~3) == 4)) {
6968 int t2 = j + 1 + (int)(signed short)source[j];
6969 if (t2 == i + 1) {
6970 //printf("blk expand %08x<-%08x\n", start + (i+1)*4, start + j*4);
6971 found_bbranch = 1;
6972 break;
6973 }
6974 }
6975 }
6976 }
6977 if (!found_bbranch)
6978 done = 2;
57871462 6979 }
6980 else {
6981 if(stop_after_jal) done=1;
6982 // Stop on BREAK
6983 if((source[i+1]&0xfc00003f)==0x0d) done=1;
6984 }
6985 // Don't recompile stuff that's already compiled
6986 if(check_addr(start+i*4+4)) done=1;
6987 // Don't get too close to the limit
d3201e39 6988 if (i > MAXBLOCK - 64)
6989 done = 1;
57871462 6990 }
a5cd72d0 6991 if (dops[i].itype == HLECALL)
6992 stop = 1;
6993 else if (dops[i].itype == INTCALL)
6994 stop = 2;
6995 else if (dops[i].is_exception)
d1150cd6 6996 done = stop_after_jal ? 1 : 2;
6997 if (done == 2) {
1e973cb0 6998 // Does the block continue due to a branch?
6999 for(j=i-1;j>=0;j--)
7000 {
277718fa 7001 if(cinfo[j].ba==start+i*4) done=j=0; // Branch into delay slot
7002 if(cinfo[j].ba==start+i*4+4) done=j=0;
7003 if(cinfo[j].ba==start+i*4+8) done=j=0;
1e973cb0 7004 }
7005 }
75dec299 7006 //assert(i<MAXBLOCK-1);
57871462 7007 if(start+i*4==pagelimit-4) done=1;
7008 assert(start+i*4<pagelimit);
d3201e39 7009 if (i == MAXBLOCK - 2)
7010 done = 1;
57871462 7011 // Stop if we're compiling junk
a5cd72d0 7012 if (dops[i].itype == INTCALL && (++ni_count > 8 || dops[i].opcode == 0x11)) {
57871462 7013 done=stop_after_jal=1;
c43b5311 7014 SysPrintf("Disabled speculative precompilation\n");
57871462 7015 }
7016 }
4bdc30ab 7017 while (i > 0 && dops[i-1].is_jump)
7018 i--;
7019 assert(i > 0);
7020 assert(!dops[i-1].is_jump);
7021 slen = i;
4149788d 7022}
7023
7024// Basic liveness analysis for MIPS registers
7025static noinline void pass2_unneeded_regs(int istart,int iend,int r)
7026{
7027 int i;
7028 uint64_t u,gte_u,b,gte_b;
7029 uint64_t temp_u,temp_gte_u=0;
7030 uint64_t gte_u_unknown=0;
7031 if (HACK_ENABLED(NDHACK_GTE_UNNEEDED))
7032 gte_u_unknown=~0ll;
7033 if(iend==slen-1) {
7034 u=1;
7035 gte_u=gte_u_unknown;
7036 }else{
7037 //u=unneeded_reg[iend+1];
7038 u=1;
7039 gte_u=gte_unneeded[iend+1];
7040 }
7041
7042 for (i=iend;i>=istart;i--)
7043 {
7044 //printf("unneeded registers i=%d (%d,%d) r=%d\n",i,istart,iend,r);
7045 if(dops[i].is_jump)
7046 {
7047 // If subroutine call, flag return address as a possible branch target
7048 if(dops[i].rt1==31 && i<slen-2) dops[i+2].bt=1;
7049
277718fa 7050 if(cinfo[i].ba<start || cinfo[i].ba>=(start+slen*4))
4149788d 7051 {
7052 // Branch out of this block, flush all regs
7053 u=1;
7054 gte_u=gte_u_unknown;
7055 branch_unneeded_reg[i]=u;
7056 // Merge in delay slot
7057 u|=(1LL<<dops[i+1].rt1)|(1LL<<dops[i+1].rt2);
7058 u&=~((1LL<<dops[i+1].rs1)|(1LL<<dops[i+1].rs2));
7059 u|=1;
7060 gte_u|=gte_rt[i+1];
7061 gte_u&=~gte_rs[i+1];
7062 }
7063 else
7064 {
7065 // Internal branch, flag target
277718fa 7066 dops[(cinfo[i].ba-start)>>2].bt=1;
7067 if(cinfo[i].ba<=start+i*4) {
4149788d 7068 // Backward branch
7069 if(dops[i].is_ujump)
7070 {
7071 // Unconditional branch
7072 temp_u=1;
7073 temp_gte_u=0;
7074 } else {
7075 // Conditional branch (not taken case)
7076 temp_u=unneeded_reg[i+2];
7077 temp_gte_u&=gte_unneeded[i+2];
7078 }
7079 // Merge in delay slot
7080 temp_u|=(1LL<<dops[i+1].rt1)|(1LL<<dops[i+1].rt2);
7081 temp_u&=~((1LL<<dops[i+1].rs1)|(1LL<<dops[i+1].rs2));
7082 temp_u|=1;
7083 temp_gte_u|=gte_rt[i+1];
7084 temp_gte_u&=~gte_rs[i+1];
7085 temp_u|=(1LL<<dops[i].rt1)|(1LL<<dops[i].rt2);
7086 temp_u&=~((1LL<<dops[i].rs1)|(1LL<<dops[i].rs2));
7087 temp_u|=1;
7088 temp_gte_u|=gte_rt[i];
7089 temp_gte_u&=~gte_rs[i];
7090 unneeded_reg[i]=temp_u;
7091 gte_unneeded[i]=temp_gte_u;
7092 // Only go three levels deep. This recursion can take an
7093 // excessive amount of time if there are a lot of nested loops.
7094 if(r<2) {
277718fa 7095 pass2_unneeded_regs((cinfo[i].ba-start)>>2,i-1,r+1);
4149788d 7096 }else{
277718fa 7097 unneeded_reg[(cinfo[i].ba-start)>>2]=1;
7098 gte_unneeded[(cinfo[i].ba-start)>>2]=gte_u_unknown;
4149788d 7099 }
7100 } /*else*/ if(1) {
7101 if (dops[i].is_ujump)
7102 {
7103 // Unconditional branch
277718fa 7104 u=unneeded_reg[(cinfo[i].ba-start)>>2];
7105 gte_u=gte_unneeded[(cinfo[i].ba-start)>>2];
4149788d 7106 branch_unneeded_reg[i]=u;
7107 // Merge in delay slot
7108 u|=(1LL<<dops[i+1].rt1)|(1LL<<dops[i+1].rt2);
7109 u&=~((1LL<<dops[i+1].rs1)|(1LL<<dops[i+1].rs2));
7110 u|=1;
7111 gte_u|=gte_rt[i+1];
7112 gte_u&=~gte_rs[i+1];
7113 } else {
7114 // Conditional branch
277718fa 7115 b=unneeded_reg[(cinfo[i].ba-start)>>2];
7116 gte_b=gte_unneeded[(cinfo[i].ba-start)>>2];
4149788d 7117 branch_unneeded_reg[i]=b;
7118 // Branch delay slot
7119 b|=(1LL<<dops[i+1].rt1)|(1LL<<dops[i+1].rt2);
7120 b&=~((1LL<<dops[i+1].rs1)|(1LL<<dops[i+1].rs2));
7121 b|=1;
7122 gte_b|=gte_rt[i+1];
7123 gte_b&=~gte_rs[i+1];
7124 u&=b;
7125 gte_u&=gte_b;
7126 if(i<slen-1) {
7127 branch_unneeded_reg[i]&=unneeded_reg[i+2];
7128 } else {
7129 branch_unneeded_reg[i]=1;
7130 }
7131 }
7132 }
7133 }
7134 }
4149788d 7135 //u=1; // DEBUG
7136 // Written registers are unneeded
7137 u|=1LL<<dops[i].rt1;
7138 u|=1LL<<dops[i].rt2;
7139 gte_u|=gte_rt[i];
7140 // Accessed registers are needed
7141 u&=~(1LL<<dops[i].rs1);
7142 u&=~(1LL<<dops[i].rs2);
7143 gte_u&=~gte_rs[i];
7144 if(gte_rs[i]&&dops[i].rt1&&(unneeded_reg[i+1]&(1ll<<dops[i].rt1)))
7145 gte_u|=gte_rs[i]&gte_unneeded[i+1]; // MFC2/CFC2 to dead register, unneeded
90f98e7c 7146 if (dops[i].may_except || dops[i].itype == RFE)
7147 {
7148 // SYSCALL instruction, etc or conditional exception
7149 u=1;
7150 }
4149788d 7151 // Source-target dependencies
7152 // R0 is always unneeded
7153 u|=1;
7154 // Save it
7155 unneeded_reg[i]=u;
7156 gte_unneeded[i]=gte_u;
7157 /*
7158 printf("ur (%d,%d) %x: ",istart,iend,start+i*4);
7159 printf("U:");
7160 int r;
7161 for(r=1;r<=CCREG;r++) {
7162 if((unneeded_reg[i]>>r)&1) {
7163 if(r==HIREG) printf(" HI");
7164 else if(r==LOREG) printf(" LO");
7165 else printf(" r%d",r);
7166 }
7167 }
7168 printf("\n");
7169 */
7170 }
7171}
57871462 7172
f9e9616e 7173static noinline void pass2a_unneeded_other(void)
7174{
7175 int i, j;
7176 for (i = 0; i < slen; i++)
7177 {
7178 // remove redundant alignment checks
7179 if (dops[i].may_except && (dops[i].is_load || dops[i].is_store)
7180 && dops[i].rt1 != dops[i].rs1 && !dops[i].is_ds)
7181 {
7182 int base = dops[i].rs1, lsb = cinfo[i].imm, ls_type = dops[i].ls_type;
7183 int mask = ls_type == LS_32 ? 3 : 1;
7184 lsb &= mask;
7185 for (j = i + 1; j < slen; j++) {
7186 if (dops[j].bt || dops[j].is_jump)
7187 break;
7188 if ((dops[j].is_load || dops[j].is_store) && dops[j].rs1 == base
7189 && dops[j].ls_type == ls_type && (cinfo[j].imm & mask) == lsb)
7190 dops[j].may_except = 0;
7191 if (dops[j].rt1 == base)
7192 break;
7193 }
7194 }
7195 }
7196}
7197
4149788d 7198static noinline void pass3_register_alloc(u_int addr)
7199{
57871462 7200 struct regstat current; // Current register allocations/status
6cc8d23c 7201 clear_all_regs(current.regmap_entry);
57871462 7202 clear_all_regs(current.regmap);
6cc8d23c 7203 current.wasdirty = current.dirty = 0;
7204 current.u = unneeded_reg[0];
7205 alloc_reg(&current, 0, CCREG);
7206 dirty_reg(&current, CCREG);
7207 current.wasconst = 0;
7208 current.isconst = 0;
7209 current.loadedconst = 0;
90f98e7c 7210 current.noevict = 0;
9b495f6e 7211 //current.waswritten = 0;
57871462 7212 int ds=0;
7213 int cc=0;
4149788d 7214 int hr;
7215 int i, j;
6ebf4adf 7216
4149788d 7217 if (addr & 1) {
57871462 7218 // First instruction is delay slot
7219 cc=-1;
cf95b4f0 7220 dops[1].bt=1;
57871462 7221 ds=1;
7222 unneeded_reg[0]=1;
57871462 7223 }
9f51b4b9 7224
57871462 7225 for(i=0;i<slen;i++)
7226 {
cf95b4f0 7227 if(dops[i].bt)
57871462 7228 {
57871462 7229 for(hr=0;hr<HOST_REGS;hr++)
7230 {
7231 // Is this really necessary?
7232 if(current.regmap[hr]==0) current.regmap[hr]=-1;
7233 }
7234 current.isconst=0;
9b495f6e 7235 //current.waswritten=0;
57871462 7236 }
24385cae 7237
57871462 7238 memcpy(regmap_pre[i],current.regmap,sizeof(current.regmap));
7239 regs[i].wasconst=current.isconst;
57871462 7240 regs[i].wasdirty=current.dirty;
6cc8d23c 7241 regs[i].dirty=0;
7242 regs[i].u=0;
7243 regs[i].isconst=0;
8575a877 7244 regs[i].loadedconst=0;
fe807a8a 7245 if (!dops[i].is_jump) {
57871462 7246 if(i+1<slen) {
cf95b4f0 7247 current.u=unneeded_reg[i+1]&~((1LL<<dops[i].rs1)|(1LL<<dops[i].rs2));
57871462 7248 current.u|=1;
57871462 7249 } else {
7250 current.u=1;
57871462 7251 }
7252 } else {
7253 if(i+1<slen) {
cf95b4f0 7254 current.u=branch_unneeded_reg[i]&~((1LL<<dops[i+1].rs1)|(1LL<<dops[i+1].rs2));
7255 current.u&=~((1LL<<dops[i].rs1)|(1LL<<dops[i].rs2));
57871462 7256 current.u|=1;
7ebfcedf 7257 } else {
7258 SysPrintf("oops, branch at end of block with no delay slot @%08x\n", start + i*4);
7259 abort();
7260 }
57871462 7261 }
f9e9616e 7262 assert(dops[i].is_ds == ds);
57871462 7263 if(ds) {
7264 ds=0; // Skip delay slot, already allocated as part of branch
7265 // ...but we need to alloc it in case something jumps here
7266 if(i+1<slen) {
7267 current.u=branch_unneeded_reg[i-1]&unneeded_reg[i+1];
57871462 7268 }else{
7269 current.u=branch_unneeded_reg[i-1];
57871462 7270 }
cf95b4f0 7271 current.u&=~((1LL<<dops[i].rs1)|(1LL<<dops[i].rs2));
57871462 7272 current.u|=1;
57871462 7273 struct regstat temp;
7274 memcpy(&temp,&current,sizeof(current));
7275 temp.wasdirty=temp.dirty;
57871462 7276 // TODO: Take into account unconditional branches, as below
7277 delayslot_alloc(&temp,i);
7278 memcpy(regs[i].regmap,temp.regmap,sizeof(temp.regmap));
7279 regs[i].wasdirty=temp.wasdirty;
57871462 7280 regs[i].dirty=temp.dirty;
57871462 7281 regs[i].isconst=0;
7282 regs[i].wasconst=0;
7283 current.isconst=0;
7284 // Create entry (branch target) regmap
7285 for(hr=0;hr<HOST_REGS;hr++)
7286 {
7287 int r=temp.regmap[hr];
7288 if(r>=0) {
7289 if(r!=regmap_pre[i][hr]) {
7290 regs[i].regmap_entry[hr]=-1;
7291 }
7292 else
7293 {
7c3a5182 7294 assert(r < 64);
57871462 7295 if((current.u>>r)&1) {
7296 regs[i].regmap_entry[hr]=-1;
7297 regs[i].regmap[hr]=-1;
7298 //Don't clear regs in the delay slot as the branch might need them
7299 //current.regmap[hr]=-1;
7300 }else
7301 regs[i].regmap_entry[hr]=r;
57871462 7302 }
7303 } else {
7304 // First instruction expects CCREG to be allocated
9f51b4b9 7305 if(i==0&&hr==HOST_CCREG)
57871462 7306 regs[i].regmap_entry[hr]=CCREG;
7307 else
7308 regs[i].regmap_entry[hr]=-1;
7309 }
7310 }
7311 }
7312 else { // Not delay slot
90f98e7c 7313 current.noevict = 0;
cf95b4f0 7314 switch(dops[i].itype) {
57871462 7315 case UJUMP:
7316 //current.isconst=0; // DEBUG
7317 //current.wasconst=0; // DEBUG
7318 //regs[i].wasconst=0; // DEBUG
cf95b4f0 7319 clear_const(&current,dops[i].rt1);
57871462 7320 alloc_cc(&current,i);
7321 dirty_reg(&current,CCREG);
cf95b4f0 7322 if (dops[i].rt1==31) {
57871462 7323 alloc_reg(&current,i,31);
7324 dirty_reg(&current,31);
cf95b4f0 7325 //assert(dops[i+1].rs1!=31&&dops[i+1].rs2!=31);
7326 //assert(dops[i+1].rt1!=dops[i].rt1);
57871462 7327 #ifdef REG_PREFETCH
7328 alloc_reg(&current,i,PTEMP);
7329 #endif
57871462 7330 }
cf95b4f0 7331 dops[i].ooo=1;
269bb29a 7332 delayslot_alloc(&current,i+1);
57871462 7333 //current.isconst=0; // DEBUG
7334 ds=1;
57871462 7335 break;
7336 case RJUMP:
7337 //current.isconst=0;
7338 //current.wasconst=0;
7339 //regs[i].wasconst=0;
cf95b4f0 7340 clear_const(&current,dops[i].rs1);
7341 clear_const(&current,dops[i].rt1);
57871462 7342 alloc_cc(&current,i);
7343 dirty_reg(&current,CCREG);
4919de1e 7344 if (!ds_writes_rjump_rs(i)) {
cf95b4f0 7345 alloc_reg(&current,i,dops[i].rs1);
7346 if (dops[i].rt1!=0) {
7347 alloc_reg(&current,i,dops[i].rt1);
7348 dirty_reg(&current,dops[i].rt1);
57871462 7349 #ifdef REG_PREFETCH
7350 alloc_reg(&current,i,PTEMP);
7351 #endif
7352 }
7353 #ifdef USE_MINI_HT
cf95b4f0 7354 if(dops[i].rs1==31) { // JALR
57871462 7355 alloc_reg(&current,i,RHASH);
57871462 7356 alloc_reg(&current,i,RHTBL);
57871462 7357 }
7358 #endif
7359 delayslot_alloc(&current,i+1);
7360 } else {
7361 // The delay slot overwrites our source register,
7362 // allocate a temporary register to hold the old value.
7363 current.isconst=0;
7364 current.wasconst=0;
7365 regs[i].wasconst=0;
7366 delayslot_alloc(&current,i+1);
7367 current.isconst=0;
7368 alloc_reg(&current,i,RTEMP);
7369 }
7370 //current.isconst=0; // DEBUG
cf95b4f0 7371 dops[i].ooo=1;
57871462 7372 ds=1;
7373 break;
7374 case CJUMP:
7375 //current.isconst=0;
7376 //current.wasconst=0;
7377 //regs[i].wasconst=0;
cf95b4f0 7378 clear_const(&current,dops[i].rs1);
7379 clear_const(&current,dops[i].rs2);
7380 if((dops[i].opcode&0x3E)==4) // BEQ/BNE
57871462 7381 {
7382 alloc_cc(&current,i);
7383 dirty_reg(&current,CCREG);
cf95b4f0 7384 if(dops[i].rs1) alloc_reg(&current,i,dops[i].rs1);
7385 if(dops[i].rs2) alloc_reg(&current,i,dops[i].rs2);
7386 if((dops[i].rs1&&(dops[i].rs1==dops[i+1].rt1||dops[i].rs1==dops[i+1].rt2))||
7387 (dops[i].rs2&&(dops[i].rs2==dops[i+1].rt1||dops[i].rs2==dops[i+1].rt2))) {
57871462 7388 // The delay slot overwrites one of our conditions.
7389 // Allocate the branch condition registers instead.
57871462 7390 current.isconst=0;
7391 current.wasconst=0;
7392 regs[i].wasconst=0;
cf95b4f0 7393 if(dops[i].rs1) alloc_reg(&current,i,dops[i].rs1);
7394 if(dops[i].rs2) alloc_reg(&current,i,dops[i].rs2);
57871462 7395 }
e1190b87 7396 else
7397 {
cf95b4f0 7398 dops[i].ooo=1;
e1190b87 7399 delayslot_alloc(&current,i+1);
7400 }
57871462 7401 }
7402 else
cf95b4f0 7403 if((dops[i].opcode&0x3E)==6) // BLEZ/BGTZ
57871462 7404 {
7405 alloc_cc(&current,i);
7406 dirty_reg(&current,CCREG);
cf95b4f0 7407 alloc_reg(&current,i,dops[i].rs1);
7408 if(dops[i].rs1&&(dops[i].rs1==dops[i+1].rt1||dops[i].rs1==dops[i+1].rt2)) {
57871462 7409 // The delay slot overwrites one of our conditions.
7410 // Allocate the branch condition registers instead.
57871462 7411 current.isconst=0;
7412 current.wasconst=0;
7413 regs[i].wasconst=0;
cf95b4f0 7414 if(dops[i].rs1) alloc_reg(&current,i,dops[i].rs1);
57871462 7415 }
e1190b87 7416 else
7417 {
cf95b4f0 7418 dops[i].ooo=1;
e1190b87 7419 delayslot_alloc(&current,i+1);
7420 }
57871462 7421 }
7422 else
7423 // Don't alloc the delay slot yet because we might not execute it
cf95b4f0 7424 if((dops[i].opcode&0x3E)==0x14) // BEQL/BNEL
57871462 7425 {
7426 current.isconst=0;
7427 current.wasconst=0;
7428 regs[i].wasconst=0;
7429 alloc_cc(&current,i);
7430 dirty_reg(&current,CCREG);
cf95b4f0 7431 alloc_reg(&current,i,dops[i].rs1);
7432 alloc_reg(&current,i,dops[i].rs2);
57871462 7433 }
7434 else
cf95b4f0 7435 if((dops[i].opcode&0x3E)==0x16) // BLEZL/BGTZL
57871462 7436 {
7437 current.isconst=0;
7438 current.wasconst=0;
7439 regs[i].wasconst=0;
7440 alloc_cc(&current,i);
7441 dirty_reg(&current,CCREG);
cf95b4f0 7442 alloc_reg(&current,i,dops[i].rs1);
57871462 7443 }
7444 ds=1;
7445 //current.isconst=0;
7446 break;
7447 case SJUMP:
cf95b4f0 7448 clear_const(&current,dops[i].rs1);
7449 clear_const(&current,dops[i].rt1);
57871462 7450 {
7451 alloc_cc(&current,i);
7452 dirty_reg(&current,CCREG);
cf95b4f0 7453 alloc_reg(&current,i,dops[i].rs1);
ecca05e3 7454 if (dops[i].rt1 == 31) { // BLTZAL/BGEZAL
57871462 7455 alloc_reg(&current,i,31);
7456 dirty_reg(&current,31);
57871462 7457 }
ecca05e3 7458 if ((dops[i].rs1 &&
7459 (dops[i].rs1==dops[i+1].rt1||dops[i].rs1==dops[i+1].rt2)) // The delay slot overwrites the branch condition.
7460 ||(dops[i].rt1 == 31 && dops[i].rs1 == 31) // overwrites it's own condition
cf95b4f0 7461 ||(dops[i].rt1==31&&(dops[i+1].rs1==31||dops[i+1].rs2==31||dops[i+1].rt1==31||dops[i+1].rt2==31))) { // DS touches $ra
57871462 7462 // Allocate the branch condition registers instead.
57871462 7463 current.isconst=0;
7464 current.wasconst=0;
7465 regs[i].wasconst=0;
cf95b4f0 7466 if(dops[i].rs1) alloc_reg(&current,i,dops[i].rs1);
57871462 7467 }
e1190b87 7468 else
7469 {
cf95b4f0 7470 dops[i].ooo=1;
e1190b87 7471 delayslot_alloc(&current,i+1);
7472 }
57871462 7473 }
57871462 7474 ds=1;
7475 //current.isconst=0;
7476 break;
57871462 7477 case IMM16:
7478 imm16_alloc(&current,i);
7479 break;
7480 case LOAD:
7481 case LOADLR:
7482 load_alloc(&current,i);
7483 break;
7484 case STORE:
7485 case STORELR:
7486 store_alloc(&current,i);
7487 break;
7488 case ALU:
7489 alu_alloc(&current,i);
7490 break;
7491 case SHIFT:
7492 shift_alloc(&current,i);
7493 break;
7494 case MULTDIV:
7495 multdiv_alloc(&current,i);
7496 break;
7497 case SHIFTIMM:
7498 shiftimm_alloc(&current,i);
7499 break;
7500 case MOV:
7501 mov_alloc(&current,i);
7502 break;
7503 case COP0:
7504 cop0_alloc(&current,i);
7505 break;
a5cd72d0 7506 case RFE:
7507 rfe_alloc(&current,i);
81dbbf4c 7508 break;
b9b61529 7509 case COP2:
81dbbf4c 7510 cop2_alloc(&current,i);
57871462 7511 break;
b9b61529 7512 case C2LS:
7513 c2ls_alloc(&current,i);
7514 break;
7515 case C2OP:
7516 c2op_alloc(&current,i);
7517 break;
57871462 7518 case SYSCALL:
7139f3c8 7519 case HLECALL:
1e973cb0 7520 case INTCALL:
57871462 7521 syscall_alloc(&current,i);
7522 break;
57871462 7523 }
9f51b4b9 7524
57871462 7525 // Create entry (branch target) regmap
7526 for(hr=0;hr<HOST_REGS;hr++)
7527 {
581335b0 7528 int r,or;
57871462 7529 r=current.regmap[hr];
7530 if(r>=0) {
7531 if(r!=regmap_pre[i][hr]) {
7532 // TODO: delay slot (?)
7533 or=get_reg(regmap_pre[i],r); // Get old mapping for this register
9de8a0c3 7534 if(or<0||r>=TEMPREG){
57871462 7535 regs[i].regmap_entry[hr]=-1;
7536 }
7537 else
7538 {
7539 // Just move it to a different register
7540 regs[i].regmap_entry[hr]=r;
7541 // If it was dirty before, it's still dirty
9de8a0c3 7542 if((regs[i].wasdirty>>or)&1) dirty_reg(&current,r);
57871462 7543 }
7544 }
7545 else
7546 {
7547 // Unneeded
7548 if(r==0){
7549 regs[i].regmap_entry[hr]=0;
7550 }
7551 else
7c3a5182 7552 {
7553 assert(r<64);
57871462 7554 if((current.u>>r)&1) {
7555 regs[i].regmap_entry[hr]=-1;
7556 //regs[i].regmap[hr]=-1;
7557 current.regmap[hr]=-1;
7558 }else
7559 regs[i].regmap_entry[hr]=r;
7560 }
57871462 7561 }
7562 } else {
7563 // Branches expect CCREG to be allocated at the target
9f51b4b9 7564 if(regmap_pre[i][hr]==CCREG)
57871462 7565 regs[i].regmap_entry[hr]=CCREG;
7566 else
7567 regs[i].regmap_entry[hr]=-1;
7568 }
7569 }
7570 memcpy(regs[i].regmap,current.regmap,sizeof(current.regmap));
7571 }
27727b63 7572
9b495f6e 7573#if 0 // see do_store_smc_check()
277718fa 7574 if(i>0&&(dops[i-1].itype==STORE||dops[i-1].itype==STORELR||(dops[i-1].itype==C2LS&&dops[i-1].opcode==0x3a))&&(u_int)cinfo[i-1].imm<0x800)
cf95b4f0 7575 current.waswritten|=1<<dops[i-1].rs1;
7576 current.waswritten&=~(1<<dops[i].rt1);
7577 current.waswritten&=~(1<<dops[i].rt2);
277718fa 7578 if((dops[i].itype==STORE||dops[i].itype==STORELR||(dops[i].itype==C2LS&&dops[i].opcode==0x3a))&&(u_int)cinfo[i].imm>=0x800)
cf95b4f0 7579 current.waswritten&=~(1<<dops[i].rs1);
9b495f6e 7580#endif
27727b63 7581
57871462 7582 /* Branch post-alloc */
7583 if(i>0)
7584 {
57871462 7585 current.wasdirty=current.dirty;
cf95b4f0 7586 switch(dops[i-1].itype) {
57871462 7587 case UJUMP:
7588 memcpy(&branch_regs[i-1],&current,sizeof(current));
7589 branch_regs[i-1].isconst=0;
7590 branch_regs[i-1].wasconst=0;
cf95b4f0 7591 branch_regs[i-1].u=branch_unneeded_reg[i-1]&~((1LL<<dops[i-1].rs1)|(1LL<<dops[i-1].rs2));
57871462 7592 alloc_cc(&branch_regs[i-1],i-1);
7593 dirty_reg(&branch_regs[i-1],CCREG);
cf95b4f0 7594 if(dops[i-1].rt1==31) { // JAL
57871462 7595 alloc_reg(&branch_regs[i-1],i-1,31);
7596 dirty_reg(&branch_regs[i-1],31);
57871462 7597 }
7598 memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
40fca85b 7599 memcpy(constmap[i],constmap[i-1],sizeof(constmap[i]));
57871462 7600 break;
7601 case RJUMP:
7602 memcpy(&branch_regs[i-1],&current,sizeof(current));
7603 branch_regs[i-1].isconst=0;
7604 branch_regs[i-1].wasconst=0;
cf95b4f0 7605 branch_regs[i-1].u=branch_unneeded_reg[i-1]&~((1LL<<dops[i-1].rs1)|(1LL<<dops[i-1].rs2));
57871462 7606 alloc_cc(&branch_regs[i-1],i-1);
7607 dirty_reg(&branch_regs[i-1],CCREG);
cf95b4f0 7608 alloc_reg(&branch_regs[i-1],i-1,dops[i-1].rs1);
7609 if(dops[i-1].rt1!=0) { // JALR
7610 alloc_reg(&branch_regs[i-1],i-1,dops[i-1].rt1);
7611 dirty_reg(&branch_regs[i-1],dops[i-1].rt1);
57871462 7612 }
7613 #ifdef USE_MINI_HT
cf95b4f0 7614 if(dops[i-1].rs1==31) { // JALR
57871462 7615 alloc_reg(&branch_regs[i-1],i-1,RHASH);
57871462 7616 alloc_reg(&branch_regs[i-1],i-1,RHTBL);
57871462 7617 }
7618 #endif
7619 memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
40fca85b 7620 memcpy(constmap[i],constmap[i-1],sizeof(constmap[i]));
57871462 7621 break;
7622 case CJUMP:
cf95b4f0 7623 if((dops[i-1].opcode&0x3E)==4) // BEQ/BNE
57871462 7624 {
7625 alloc_cc(&current,i-1);
7626 dirty_reg(&current,CCREG);
cf95b4f0 7627 if((dops[i-1].rs1&&(dops[i-1].rs1==dops[i].rt1||dops[i-1].rs1==dops[i].rt2))||
7628 (dops[i-1].rs2&&(dops[i-1].rs2==dops[i].rt1||dops[i-1].rs2==dops[i].rt2))) {
57871462 7629 // The delay slot overwrote one of our conditions
7630 // Delay slot goes after the test (in order)
cf95b4f0 7631 current.u=branch_unneeded_reg[i-1]&~((1LL<<dops[i].rs1)|(1LL<<dops[i].rs2));
57871462 7632 current.u|=1;
57871462 7633 delayslot_alloc(&current,i);
7634 current.isconst=0;
7635 }
7636 else
7637 {
cf95b4f0 7638 current.u=branch_unneeded_reg[i-1]&~((1LL<<dops[i-1].rs1)|(1LL<<dops[i-1].rs2));
57871462 7639 // Alloc the branch condition registers
cf95b4f0 7640 if(dops[i-1].rs1) alloc_reg(&current,i-1,dops[i-1].rs1);
7641 if(dops[i-1].rs2) alloc_reg(&current,i-1,dops[i-1].rs2);
57871462 7642 }
7643 memcpy(&branch_regs[i-1],&current,sizeof(current));
7644 branch_regs[i-1].isconst=0;
7645 branch_regs[i-1].wasconst=0;
7646 memcpy(&branch_regs[i-1].regmap_entry,&current.regmap,sizeof(current.regmap));
40fca85b 7647 memcpy(constmap[i],constmap[i-1],sizeof(constmap[i]));
57871462 7648 }
7649 else
cf95b4f0 7650 if((dops[i-1].opcode&0x3E)==6) // BLEZ/BGTZ
57871462 7651 {
7652 alloc_cc(&current,i-1);
7653 dirty_reg(&current,CCREG);
cf95b4f0 7654 if(dops[i-1].rs1==dops[i].rt1||dops[i-1].rs1==dops[i].rt2) {
57871462 7655 // The delay slot overwrote the branch condition
7656 // Delay slot goes after the test (in order)
cf95b4f0 7657 current.u=branch_unneeded_reg[i-1]&~((1LL<<dops[i].rs1)|(1LL<<dops[i].rs2));
57871462 7658 current.u|=1;
57871462 7659 delayslot_alloc(&current,i);
7660 current.isconst=0;
7661 }
7662 else
7663 {
cf95b4f0 7664 current.u=branch_unneeded_reg[i-1]&~(1LL<<dops[i-1].rs1);
57871462 7665 // Alloc the branch condition register
cf95b4f0 7666 alloc_reg(&current,i-1,dops[i-1].rs1);
57871462 7667 }
7668 memcpy(&branch_regs[i-1],&current,sizeof(current));
7669 branch_regs[i-1].isconst=0;
7670 branch_regs[i-1].wasconst=0;
7671 memcpy(&branch_regs[i-1].regmap_entry,&current.regmap,sizeof(current.regmap));
40fca85b 7672 memcpy(constmap[i],constmap[i-1],sizeof(constmap[i]));
57871462 7673 }
57871462 7674 break;
7675 case SJUMP:
57871462 7676 {
7677 alloc_cc(&current,i-1);
7678 dirty_reg(&current,CCREG);
cf95b4f0 7679 if(dops[i-1].rs1==dops[i].rt1||dops[i-1].rs1==dops[i].rt2) {
57871462 7680 // The delay slot overwrote the branch condition
7681 // Delay slot goes after the test (in order)
cf95b4f0 7682 current.u=branch_unneeded_reg[i-1]&~((1LL<<dops[i].rs1)|(1LL<<dops[i].rs2));
57871462 7683 current.u|=1;
57871462 7684 delayslot_alloc(&current,i);
7685 current.isconst=0;
7686 }
7687 else
7688 {
cf95b4f0 7689 current.u=branch_unneeded_reg[i-1]&~(1LL<<dops[i-1].rs1);
57871462 7690 // Alloc the branch condition register
cf95b4f0 7691 alloc_reg(&current,i-1,dops[i-1].rs1);
57871462 7692 }
7693 memcpy(&branch_regs[i-1],&current,sizeof(current));
7694 branch_regs[i-1].isconst=0;
7695 branch_regs[i-1].wasconst=0;
7696 memcpy(&branch_regs[i-1].regmap_entry,&current.regmap,sizeof(current.regmap));
40fca85b 7697 memcpy(constmap[i],constmap[i-1],sizeof(constmap[i]));
57871462 7698 }
57871462 7699 break;
57871462 7700 }
7701
fe807a8a 7702 if (dops[i-1].is_ujump)
57871462 7703 {
cf95b4f0 7704 if(dops[i-1].rt1==31) // JAL/JALR
57871462 7705 {
7706 // Subroutine call will return here, don't alloc any registers
57871462 7707 current.dirty=0;
7708 clear_all_regs(current.regmap);
7709 alloc_reg(&current,i,CCREG);
7710 dirty_reg(&current,CCREG);
7711 }
7712 else if(i+1<slen)
7713 {
7714 // Internal branch will jump here, match registers to caller
57871462 7715 current.dirty=0;
7716 clear_all_regs(current.regmap);
7717 alloc_reg(&current,i,CCREG);
7718 dirty_reg(&current,CCREG);
7719 for(j=i-1;j>=0;j--)
7720 {
277718fa 7721 if(cinfo[j].ba==start+i*4+4) {
57871462 7722 memcpy(current.regmap,branch_regs[j].regmap,sizeof(current.regmap));
57871462 7723 current.dirty=branch_regs[j].dirty;
7724 break;
7725 }
7726 }
7727 while(j>=0) {
277718fa 7728 if(cinfo[j].ba==start+i*4+4) {
57871462 7729 for(hr=0;hr<HOST_REGS;hr++) {
7730 if(current.regmap[hr]!=branch_regs[j].regmap[hr]) {
7731 current.regmap[hr]=-1;
7732 }
57871462 7733 current.dirty&=branch_regs[j].dirty;
7734 }
7735 }
7736 j--;
7737 }
7738 }
7739 }
7740 }
7741
7742 // Count cycles in between branches
277718fa 7743 cinfo[i].ccadj = CLOCK_ADJUST(cc);
a5cd72d0 7744 if (i > 0 && (dops[i-1].is_jump || dops[i].is_exception))
57871462 7745 {
7746 cc=0;
7747 }
71e490c5 7748#if !defined(DRC_DBG)
cf95b4f0 7749 else if(dops[i].itype==C2OP&&gte_cycletab[source[i]&0x3f]>2)
054175e9 7750 {
81dbbf4c 7751 // this should really be removed since the real stalls have been implemented,
7752 // but doing so causes sizeable perf regression against the older version
7753 u_int gtec = gte_cycletab[source[i] & 0x3f];
32631e6a 7754 cc += HACK_ENABLED(NDHACK_NO_STALLS) ? gtec/2 : 2;
fb407447 7755 }
cf95b4f0 7756 else if(i>1&&dops[i].itype==STORE&&dops[i-1].itype==STORE&&dops[i-2].itype==STORE&&!dops[i].bt)
5fdcbb5a 7757 {
7758 cc+=4;
7759 }
cf95b4f0 7760 else if(dops[i].itype==C2LS)
fb407447 7761 {
81dbbf4c 7762 // same as with C2OP
32631e6a 7763 cc += HACK_ENABLED(NDHACK_NO_STALLS) ? 4 : 2;
fb407447 7764 }
7765#endif
57871462 7766 else
7767 {
7768 cc++;
7769 }
7770
cf95b4f0 7771 if(!dops[i].is_ds) {
57871462 7772 regs[i].dirty=current.dirty;
7773 regs[i].isconst=current.isconst;
40fca85b 7774 memcpy(constmap[i],current_constmap,sizeof(constmap[i]));
57871462 7775 }
7776 for(hr=0;hr<HOST_REGS;hr++) {
7777 if(hr!=EXCLUDE_REG&&regs[i].regmap[hr]>=0) {
7778 if(regmap_pre[i][hr]!=regs[i].regmap[hr]) {
7779 regs[i].wasconst&=~(1<<hr);
7780 }
7781 }
7782 }
9b495f6e 7783 //regs[i].waswritten=current.waswritten;
57871462 7784 }
4149788d 7785}
9f51b4b9 7786
4149788d 7787static noinline void pass4_cull_unused_regs(void)
7788{
53358c1d 7789 u_int last_needed_regs[4] = {0,0,0,0};
4149788d 7790 u_int nr=0;
7791 int i;
9f51b4b9 7792
57871462 7793 for (i=slen-1;i>=0;i--)
7794 {
7795 int hr;
53358c1d 7796 __builtin_prefetch(regs[i-2].regmap);
fe807a8a 7797 if(dops[i].is_jump)
57871462 7798 {
277718fa 7799 if(cinfo[i].ba<start || cinfo[i].ba>=(start+slen*4))
57871462 7800 {
7801 // Branch out of this block, don't need anything
7802 nr=0;
7803 }
7804 else
7805 {
7806 // Internal branch
7807 // Need whatever matches the target
7808 nr=0;
277718fa 7809 int t=(cinfo[i].ba-start)>>2;
57871462 7810 for(hr=0;hr<HOST_REGS;hr++)
7811 {
7812 if(regs[i].regmap_entry[hr]>=0) {
7813 if(regs[i].regmap_entry[hr]==regs[t].regmap_entry[hr]) nr|=1<<hr;
7814 }
7815 }
7816 }
7817 // Conditional branch may need registers for following instructions
fe807a8a 7818 if (!dops[i].is_ujump)
57871462 7819 {
7820 if(i<slen-2) {
53358c1d 7821 nr |= last_needed_regs[(i+2) & 3];
57871462 7822 for(hr=0;hr<HOST_REGS;hr++)
7823 {
7824 if(regmap_pre[i+2][hr]>=0&&get_reg(regs[i+2].regmap_entry,regmap_pre[i+2][hr])<0) nr&=~(1<<hr);
7825 //if((regmap_entry[i+2][hr])>=0) if(!((nr>>hr)&1)) printf("%x-bogus(%d=%d)\n",start+i*4,hr,regmap_entry[i+2][hr]);
7826 }
7827 }
7828 }
7829 // Don't need stuff which is overwritten
f5955059 7830 //if(regs[i].regmap[hr]!=regmap_pre[i][hr]) nr&=~(1<<hr);
7831 //if(regs[i].regmap[hr]<0) nr&=~(1<<hr);
57871462 7832 // Merge in delay slot
53358c1d 7833 if (dops[i+1].rt1) nr &= ~get_regm(regs[i].regmap, dops[i+1].rt1);
7834 if (dops[i+1].rt2) nr &= ~get_regm(regs[i].regmap, dops[i+1].rt2);
7835 nr |= get_regm(regmap_pre[i], dops[i+1].rs1);
7836 nr |= get_regm(regmap_pre[i], dops[i+1].rs2);
7837 nr |= get_regm(regs[i].regmap_entry, dops[i+1].rs1);
7838 nr |= get_regm(regs[i].regmap_entry, dops[i+1].rs2);
7839 if (ram_offset && (dops[i+1].is_load || dops[i+1].is_store)) {
7840 nr |= get_regm(regmap_pre[i], ROREG);
7841 nr |= get_regm(regs[i].regmap_entry, ROREG);
7842 }
7843 if (dops[i+1].is_store) {
7844 nr |= get_regm(regmap_pre[i], INVCP);
7845 nr |= get_regm(regs[i].regmap_entry, INVCP);
57871462 7846 }
7847 }
277718fa 7848 else if (dops[i].is_exception)
57871462 7849 {
277718fa 7850 // SYSCALL instruction, etc
57871462 7851 nr=0;
7852 }
7853 else // Non-branch
7854 {
7855 if(i<slen-1) {
7856 for(hr=0;hr<HOST_REGS;hr++) {
7857 if(regmap_pre[i+1][hr]>=0&&get_reg(regs[i+1].regmap_entry,regmap_pre[i+1][hr])<0) nr&=~(1<<hr);
7858 if(regs[i].regmap[hr]!=regmap_pre[i+1][hr]) nr&=~(1<<hr);
7859 if(regs[i].regmap[hr]!=regmap_pre[i][hr]) nr&=~(1<<hr);
7860 if(regs[i].regmap[hr]<0) nr&=~(1<<hr);
7861 }
7862 }
7863 }
53358c1d 7864 // Overwritten registers are not needed
7865 if (dops[i].rt1) nr &= ~get_regm(regs[i].regmap, dops[i].rt1);
7866 if (dops[i].rt2) nr &= ~get_regm(regs[i].regmap, dops[i].rt2);
7867 nr &= ~get_regm(regs[i].regmap, FTEMP);
7868 // Source registers are needed
7869 nr |= get_regm(regmap_pre[i], dops[i].rs1);
7870 nr |= get_regm(regmap_pre[i], dops[i].rs2);
7871 nr |= get_regm(regs[i].regmap_entry, dops[i].rs1);
7872 nr |= get_regm(regs[i].regmap_entry, dops[i].rs2);
7873 if (ram_offset && (dops[i].is_load || dops[i].is_store)) {
7874 nr |= get_regm(regmap_pre[i], ROREG);
7875 nr |= get_regm(regs[i].regmap_entry, ROREG);
7876 }
7877 if (dops[i].is_store) {
7878 nr |= get_regm(regmap_pre[i], INVCP);
7879 nr |= get_regm(regs[i].regmap_entry, INVCP);
7880 }
7881
7882 if (i > 0 && !dops[i].bt && regs[i].wasdirty)
57871462 7883 for(hr=0;hr<HOST_REGS;hr++)
7884 {
57871462 7885 // Don't store a register immediately after writing it,
7886 // may prevent dual-issue.
7887 // But do so if this is a branch target, otherwise we
7888 // might have to load the register before the branch.
53358c1d 7889 if((regs[i].wasdirty>>hr)&1) {
7c3a5182 7890 if((regmap_pre[i][hr]>0&&!((unneeded_reg[i]>>regmap_pre[i][hr])&1))) {
9de8a0c3 7891 if(dops[i-1].rt1==regmap_pre[i][hr]) nr|=1<<hr;
7892 if(dops[i-1].rt2==regmap_pre[i][hr]) nr|=1<<hr;
57871462 7893 }
7c3a5182 7894 if((regs[i].regmap_entry[hr]>0&&!((unneeded_reg[i]>>regs[i].regmap_entry[hr])&1))) {
9de8a0c3 7895 if(dops[i-1].rt1==regs[i].regmap_entry[hr]) nr|=1<<hr;
7896 if(dops[i-1].rt2==regs[i].regmap_entry[hr]) nr|=1<<hr;
57871462 7897 }
7898 }
7899 }
7900 // Cycle count is needed at branches. Assume it is needed at the target too.
de6dbc52 7901 if (i == 0 || dops[i].bt || dops[i].may_except || dops[i].itype == CJUMP) {
57871462 7902 if(regmap_pre[i][HOST_CCREG]==CCREG) nr|=1<<HOST_CCREG;
7903 if(regs[i].regmap_entry[HOST_CCREG]==CCREG) nr|=1<<HOST_CCREG;
7904 }
7905 // Save it
53358c1d 7906 last_needed_regs[i & 3] = nr;
9f51b4b9 7907
57871462 7908 // Deallocate unneeded registers
7909 for(hr=0;hr<HOST_REGS;hr++)
7910 {
7911 if(!((nr>>hr)&1)) {
7912 if(regs[i].regmap_entry[hr]!=CCREG) regs[i].regmap_entry[hr]=-1;
fe807a8a 7913 if(dops[i].is_jump)
57871462 7914 {
37387d8b 7915 int map1 = 0, map2 = 0, temp = 0; // or -1 ??
7916 if (dops[i+1].is_load || dops[i+1].is_store)
7917 map1 = ROREG;
7918 if (dops[i+1].is_store)
7919 map2 = INVCP;
7920 if(dops[i+1].itype==LOADLR || dops[i+1].itype==STORELR || dops[i+1].itype==C2LS)
7921 temp = FTEMP;
9de8a0c3 7922 if(regs[i].regmap[hr]!=dops[i].rs1 && regs[i].regmap[hr]!=dops[i].rs2 &&
7923 regs[i].regmap[hr]!=dops[i].rt1 && regs[i].regmap[hr]!=dops[i].rt2 &&
7924 regs[i].regmap[hr]!=dops[i+1].rt1 && regs[i].regmap[hr]!=dops[i+1].rt2 &&
cf95b4f0 7925 regs[i].regmap[hr]!=dops[i+1].rs1 && regs[i].regmap[hr]!=dops[i+1].rs2 &&
9de8a0c3 7926 regs[i].regmap[hr]!=temp && regs[i].regmap[hr]!=PTEMP &&
57871462 7927 regs[i].regmap[hr]!=RHASH && regs[i].regmap[hr]!=RHTBL &&
7928 regs[i].regmap[hr]!=RTEMP && regs[i].regmap[hr]!=CCREG &&
37387d8b 7929 regs[i].regmap[hr]!=map1 && regs[i].regmap[hr]!=map2)
57871462 7930 {
7931 regs[i].regmap[hr]=-1;
7932 regs[i].isconst&=~(1<<hr);
a550c61c 7933 regs[i].dirty&=~(1<<hr);
7934 regs[i+1].wasdirty&=~(1<<hr);
9de8a0c3 7935 if(branch_regs[i].regmap[hr]!=dops[i].rs1 && branch_regs[i].regmap[hr]!=dops[i].rs2 &&
7936 branch_regs[i].regmap[hr]!=dops[i].rt1 && branch_regs[i].regmap[hr]!=dops[i].rt2 &&
7937 branch_regs[i].regmap[hr]!=dops[i+1].rt1 && branch_regs[i].regmap[hr]!=dops[i+1].rt2 &&
cf95b4f0 7938 branch_regs[i].regmap[hr]!=dops[i+1].rs1 && branch_regs[i].regmap[hr]!=dops[i+1].rs2 &&
9de8a0c3 7939 branch_regs[i].regmap[hr]!=temp && branch_regs[i].regmap[hr]!=PTEMP &&
57871462 7940 branch_regs[i].regmap[hr]!=RHASH && branch_regs[i].regmap[hr]!=RHTBL &&
7941 branch_regs[i].regmap[hr]!=RTEMP && branch_regs[i].regmap[hr]!=CCREG &&
37387d8b 7942 branch_regs[i].regmap[hr]!=map1 && branch_regs[i].regmap[hr]!=map2)
57871462 7943 {
7944 branch_regs[i].regmap[hr]=-1;
7945 branch_regs[i].regmap_entry[hr]=-1;
fe807a8a 7946 if (!dops[i].is_ujump)
57871462 7947 {
fe807a8a 7948 if (i < slen-2) {
57871462 7949 regmap_pre[i+2][hr]=-1;
79c75f1b 7950 regs[i+2].wasconst&=~(1<<hr);
57871462 7951 }
7952 }
7953 }
7954 }
7955 }
7956 else
7957 {
7958 // Non-branch
7959 if(i>0)
7960 {
37387d8b 7961 int map1 = -1, map2 = -1, temp=-1;
7962 if (dops[i].is_load || dops[i].is_store)
7963 map1 = ROREG;
7964 if (dops[i].is_store)
7965 map2 = INVCP;
7966 if (dops[i].itype==LOADLR || dops[i].itype==STORELR || dops[i].itype==C2LS)
7967 temp = FTEMP;
9de8a0c3 7968 if(regs[i].regmap[hr]!=dops[i].rt1 && regs[i].regmap[hr]!=dops[i].rt2 &&
cf95b4f0 7969 regs[i].regmap[hr]!=dops[i].rs1 && regs[i].regmap[hr]!=dops[i].rs2 &&
9de8a0c3 7970 regs[i].regmap[hr]!=temp && regs[i].regmap[hr]!=map1 && regs[i].regmap[hr]!=map2 &&
4b1c7cd1 7971 //(dops[i].itype!=SPAN||regs[i].regmap[hr]!=CCREG)
7972 regs[i].regmap[hr] != CCREG)
57871462 7973 {
cf95b4f0 7974 if(i<slen-1&&!dops[i].is_ds) {
ad49de89 7975 assert(regs[i].regmap[hr]<64);
afec9d44 7976 if(regmap_pre[i+1][hr]!=-1 || regs[i].regmap[hr]>0)
57871462 7977 if(regmap_pre[i+1][hr]!=regs[i].regmap[hr])
57871462 7978 {
c43b5311 7979 SysPrintf("fail: %x (%d %d!=%d)\n",start+i*4,hr,regmap_pre[i+1][hr],regs[i].regmap[hr]);
57871462 7980 assert(regmap_pre[i+1][hr]==regs[i].regmap[hr]);
7981 }
7982 regmap_pre[i+1][hr]=-1;
7983 if(regs[i+1].regmap_entry[hr]==CCREG) regs[i+1].regmap_entry[hr]=-1;
79c75f1b 7984 regs[i+1].wasconst&=~(1<<hr);
57871462 7985 }
7986 regs[i].regmap[hr]=-1;
7987 regs[i].isconst&=~(1<<hr);
a550c61c 7988 regs[i].dirty&=~(1<<hr);
7989 regs[i+1].wasdirty&=~(1<<hr);
57871462 7990 }
7991 }
7992 }
3968e69e 7993 } // if needed
7994 } // for hr
57871462 7995 }
4149788d 7996}
9f51b4b9 7997
4149788d 7998// If a register is allocated during a loop, try to allocate it for the
7999// entire loop, if possible. This avoids loading/storing registers
8000// inside of the loop.
8001static noinline void pass5a_preallocate1(void)
8002{
8003 int i, j, hr;
57871462 8004 signed char f_regmap[HOST_REGS];
8005 clear_all_regs(f_regmap);
8006 for(i=0;i<slen-1;i++)
8007 {
cf95b4f0 8008 if(dops[i].itype==UJUMP||dops[i].itype==CJUMP||dops[i].itype==SJUMP)
57871462 8009 {
277718fa 8010 if(cinfo[i].ba>=start && cinfo[i].ba<(start+i*4))
cf95b4f0 8011 if(dops[i+1].itype==NOP||dops[i+1].itype==MOV||dops[i+1].itype==ALU
8012 ||dops[i+1].itype==SHIFTIMM||dops[i+1].itype==IMM16||dops[i+1].itype==LOAD
a5cd72d0 8013 ||dops[i+1].itype==STORE||dops[i+1].itype==STORELR
8014 ||dops[i+1].itype==SHIFT
cf95b4f0 8015 ||dops[i+1].itype==COP2||dops[i+1].itype==C2LS||dops[i+1].itype==C2OP)
57871462 8016 {
277718fa 8017 int t=(cinfo[i].ba-start)>>2;
fe807a8a 8018 if(t > 0 && !dops[t-1].is_jump) // loop_preload can't handle jumps into delay slots
cf95b4f0 8019 if(t<2||(dops[t-2].itype!=UJUMP&&dops[t-2].itype!=RJUMP)||dops[t-2].rt1!=31) // call/ret assumes no registers allocated
57871462 8020 for(hr=0;hr<HOST_REGS;hr++)
8021 {
7c3a5182 8022 if(regs[i].regmap[hr]>=0) {
b372a952 8023 if(f_regmap[hr]!=regs[i].regmap[hr]) {
8024 // dealloc old register
8025 int n;
8026 for(n=0;n<HOST_REGS;n++)
8027 {
8028 if(f_regmap[n]==regs[i].regmap[hr]) {f_regmap[n]=-1;}
8029 }
8030 // and alloc new one
8031 f_regmap[hr]=regs[i].regmap[hr];
8032 }
8033 }
7c3a5182 8034 if(branch_regs[i].regmap[hr]>=0) {
b372a952 8035 if(f_regmap[hr]!=branch_regs[i].regmap[hr]) {
8036 // dealloc old register
8037 int n;
8038 for(n=0;n<HOST_REGS;n++)
8039 {
8040 if(f_regmap[n]==branch_regs[i].regmap[hr]) {f_regmap[n]=-1;}
8041 }
8042 // and alloc new one
8043 f_regmap[hr]=branch_regs[i].regmap[hr];
8044 }
8045 }
cf95b4f0 8046 if(dops[i].ooo) {
277718fa 8047 if(count_free_regs(regs[i].regmap)<=cinfo[i+1].min_free_regs)
e1190b87 8048 f_regmap[hr]=branch_regs[i].regmap[hr];
8049 }else{
277718fa 8050 if(count_free_regs(branch_regs[i].regmap)<=cinfo[i+1].min_free_regs)
57871462 8051 f_regmap[hr]=branch_regs[i].regmap[hr];
8052 }
8053 // Avoid dirty->clean transition
e1190b87 8054 #ifdef DESTRUCTIVE_WRITEBACK
57871462 8055 if(t>0) if(get_reg(regmap_pre[t],f_regmap[hr])>=0) if((regs[t].wasdirty>>get_reg(regmap_pre[t],f_regmap[hr]))&1) f_regmap[hr]=-1;
e1190b87 8056 #endif
8057 // This check is only strictly required in the DESTRUCTIVE_WRITEBACK
8058 // case above, however it's always a good idea. We can't hoist the
8059 // load if the register was already allocated, so there's no point
8060 // wasting time analyzing most of these cases. It only "succeeds"
8061 // when the mapping was different and the load can be replaced with
8062 // a mov, which is of negligible benefit. So such cases are
8063 // skipped below.
57871462 8064 if(f_regmap[hr]>0) {
198df76f 8065 if(regs[t].regmap[hr]==f_regmap[hr]||(regs[t].regmap_entry[hr]<0&&get_reg(regmap_pre[t],f_regmap[hr])<0)) {
57871462 8066 int r=f_regmap[hr];
8067 for(j=t;j<=i;j++)
8068 {
277718fa 8069 //printf("Test %x -> %x, %x %d/%d\n",start+i*4,cinfo[i].ba,start+j*4,hr,r);
57871462 8070 if(r<34&&((unneeded_reg[j]>>r)&1)) break;
00fa9369 8071 assert(r < 64);
9de8a0c3 8072 if(regs[j].regmap[hr]==f_regmap[hr]&&f_regmap[hr]<TEMPREG) {
277718fa 8073 //printf("Hit %x -> %x, %x %d/%d\n",start+i*4,cinfo[i].ba,start+j*4,hr,r);
57871462 8074 int k;
8075 if(regs[i].regmap[hr]==-1&&branch_regs[i].regmap[hr]==-1) {
670c0f22 8076 if(get_reg(regs[i].regmap,f_regmap[hr])>=0) break;
57871462 8077 if(get_reg(regs[i+2].regmap,f_regmap[hr])>=0) break;
57871462 8078 k=i;
8079 while(k>1&&regs[k-1].regmap[hr]==-1) {
277718fa 8080 if(count_free_regs(regs[k-1].regmap)<=cinfo[k-1].min_free_regs) {
e1190b87 8081 //printf("no free regs for store %x\n",start+(k-1)*4);
8082 break;
57871462 8083 }
57871462 8084 if(get_reg(regs[k-1].regmap,f_regmap[hr])>=0) {
8085 //printf("no-match due to different register\n");
8086 break;
8087 }
fe807a8a 8088 if (dops[k-2].is_jump) {
57871462 8089 //printf("no-match due to branch\n");
8090 break;
8091 }
8092 // call/ret fast path assumes no registers allocated
cf95b4f0 8093 if(k>2&&(dops[k-3].itype==UJUMP||dops[k-3].itype==RJUMP)&&dops[k-3].rt1==31) {
57871462 8094 break;
8095 }
57871462 8096 k--;
8097 }
57871462 8098 if(regs[k-1].regmap[hr]==f_regmap[hr]&&regmap_pre[k][hr]==f_regmap[hr]) {
8099 //printf("Extend r%d, %x ->\n",hr,start+k*4);
8100 while(k<i) {
8101 regs[k].regmap_entry[hr]=f_regmap[hr];
8102 regs[k].regmap[hr]=f_regmap[hr];
8103 regmap_pre[k+1][hr]=f_regmap[hr];
8104 regs[k].wasdirty&=~(1<<hr);
8105 regs[k].dirty&=~(1<<hr);
8106 regs[k].wasdirty|=(1<<hr)&regs[k-1].dirty;
8107 regs[k].dirty|=(1<<hr)&regs[k].wasdirty;
8108 regs[k].wasconst&=~(1<<hr);
8109 regs[k].isconst&=~(1<<hr);
8110 k++;
8111 }
8112 }
8113 else {
8114 //printf("Fail Extend r%d, %x ->\n",hr,start+k*4);
8115 break;
8116 }
8117 assert(regs[i-1].regmap[hr]==f_regmap[hr]);
8118 if(regs[i-1].regmap[hr]==f_regmap[hr]&&regmap_pre[i][hr]==f_regmap[hr]) {
8119 //printf("OK fill %x (r%d)\n",start+i*4,hr);
8120 regs[i].regmap_entry[hr]=f_regmap[hr];
8121 regs[i].regmap[hr]=f_regmap[hr];
8122 regs[i].wasdirty&=~(1<<hr);
8123 regs[i].dirty&=~(1<<hr);
8124 regs[i].wasdirty|=(1<<hr)&regs[i-1].dirty;
8125 regs[i].dirty|=(1<<hr)&regs[i-1].dirty;
8126 regs[i].wasconst&=~(1<<hr);
8127 regs[i].isconst&=~(1<<hr);
8128 branch_regs[i].regmap_entry[hr]=f_regmap[hr];
8129 branch_regs[i].wasdirty&=~(1<<hr);
8130 branch_regs[i].wasdirty|=(1<<hr)&regs[i].dirty;
8131 branch_regs[i].regmap[hr]=f_regmap[hr];
8132 branch_regs[i].dirty&=~(1<<hr);
8133 branch_regs[i].dirty|=(1<<hr)&regs[i].dirty;
8134 branch_regs[i].wasconst&=~(1<<hr);
8135 branch_regs[i].isconst&=~(1<<hr);
fe807a8a 8136 if (!dops[i].is_ujump) {
57871462 8137 regmap_pre[i+2][hr]=f_regmap[hr];
8138 regs[i+2].wasdirty&=~(1<<hr);
8139 regs[i+2].wasdirty|=(1<<hr)&regs[i].dirty;
57871462 8140 }
8141 }
8142 }
8143 for(k=t;k<j;k++) {
e1190b87 8144 // Alloc register clean at beginning of loop,
8145 // but may dirty it in pass 6
57871462 8146 regs[k].regmap_entry[hr]=f_regmap[hr];
8147 regs[k].regmap[hr]=f_regmap[hr];
57871462 8148 regs[k].dirty&=~(1<<hr);
8149 regs[k].wasconst&=~(1<<hr);
8150 regs[k].isconst&=~(1<<hr);
fe807a8a 8151 if (dops[k].is_jump) {
e1190b87 8152 branch_regs[k].regmap_entry[hr]=f_regmap[hr];
8153 branch_regs[k].regmap[hr]=f_regmap[hr];
8154 branch_regs[k].dirty&=~(1<<hr);
8155 branch_regs[k].wasconst&=~(1<<hr);
8156 branch_regs[k].isconst&=~(1<<hr);
fe807a8a 8157 if (!dops[k].is_ujump) {
e1190b87 8158 regmap_pre[k+2][hr]=f_regmap[hr];
8159 regs[k+2].wasdirty&=~(1<<hr);
e1190b87 8160 }
8161 }
8162 else
8163 {
8164 regmap_pre[k+1][hr]=f_regmap[hr];
8165 regs[k+1].wasdirty&=~(1<<hr);
8166 }
57871462 8167 }
8168 if(regs[j].regmap[hr]==f_regmap[hr])
8169 regs[j].regmap_entry[hr]=f_regmap[hr];
8170 break;
8171 }
8172 if(j==i) break;
8173 if(regs[j].regmap[hr]>=0)
8174 break;
8175 if(get_reg(regs[j].regmap,f_regmap[hr])>=0) {
8176 //printf("no-match due to different register\n");
8177 break;
8178 }
fe807a8a 8179 if (dops[j].is_ujump)
e1190b87 8180 {
8181 // Stop on unconditional branch
8182 break;
8183 }
cf95b4f0 8184 if(dops[j].itype==CJUMP||dops[j].itype==SJUMP)
e1190b87 8185 {
cf95b4f0 8186 if(dops[j].ooo) {
277718fa 8187 if(count_free_regs(regs[j].regmap)<=cinfo[j+1].min_free_regs)
e1190b87 8188 break;
8189 }else{
277718fa 8190 if(count_free_regs(branch_regs[j].regmap)<=cinfo[j+1].min_free_regs)
e1190b87 8191 break;
8192 }
8193 if(get_reg(branch_regs[j].regmap,f_regmap[hr])>=0) {
8194 //printf("no-match due to different register (branch)\n");
57871462 8195 break;
8196 }
8197 }
277718fa 8198 if(count_free_regs(regs[j].regmap)<=cinfo[j].min_free_regs) {
e1190b87 8199 //printf("No free regs for store %x\n",start+j*4);
8200 break;
8201 }
ad49de89 8202 assert(f_regmap[hr]<64);
57871462 8203 }
8204 }
8205 }
8206 }
8207 }
8208 }else{
198df76f 8209 // Non branch or undetermined branch target
57871462 8210 for(hr=0;hr<HOST_REGS;hr++)
8211 {
8212 if(hr!=EXCLUDE_REG) {
7c3a5182 8213 if(regs[i].regmap[hr]>=0) {
b372a952 8214 if(f_regmap[hr]!=regs[i].regmap[hr]) {
8215 // dealloc old register
8216 int n;
8217 for(n=0;n<HOST_REGS;n++)
8218 {
8219 if(f_regmap[n]==regs[i].regmap[hr]) {f_regmap[n]=-1;}
8220 }
4149788d 8221 // and alloc new one
8222 f_regmap[hr]=regs[i].regmap[hr];
8223 }
8224 }
8225 }
8226 }
8227 // Try to restore cycle count at branch targets
8228 if(dops[i].bt) {
8229 for(j=i;j<slen-1;j++) {
8230 if(regs[j].regmap[HOST_CCREG]!=-1) break;
277718fa 8231 if(count_free_regs(regs[j].regmap)<=cinfo[j].min_free_regs) {
4149788d 8232 //printf("no free regs for store %x\n",start+j*4);
8233 break;
8234 }
8235 }
8236 if(regs[j].regmap[HOST_CCREG]==CCREG) {
8237 int k=i;
8238 //printf("Extend CC, %x -> %x\n",start+k*4,start+j*4);
8239 while(k<j) {
8240 regs[k].regmap_entry[HOST_CCREG]=CCREG;
8241 regs[k].regmap[HOST_CCREG]=CCREG;
8242 regmap_pre[k+1][HOST_CCREG]=CCREG;
8243 regs[k+1].wasdirty|=1<<HOST_CCREG;
8244 regs[k].dirty|=1<<HOST_CCREG;
8245 regs[k].wasconst&=~(1<<HOST_CCREG);
8246 regs[k].isconst&=~(1<<HOST_CCREG);
8247 k++;
8248 }
8249 regs[j].regmap_entry[HOST_CCREG]=CCREG;
8250 }
8251 // Work backwards from the branch target
8252 if(j>i&&f_regmap[HOST_CCREG]==CCREG)
8253 {
8254 //printf("Extend backwards\n");
8255 int k;
8256 k=i;
8257 while(regs[k-1].regmap[HOST_CCREG]==-1) {
277718fa 8258 if(count_free_regs(regs[k-1].regmap)<=cinfo[k-1].min_free_regs) {
4149788d 8259 //printf("no free regs for store %x\n",start+(k-1)*4);
8260 break;
8261 }
8262 k--;
8263 }
8264 if(regs[k-1].regmap[HOST_CCREG]==CCREG) {
8265 //printf("Extend CC, %x ->\n",start+k*4);
8266 while(k<=i) {
8267 regs[k].regmap_entry[HOST_CCREG]=CCREG;
8268 regs[k].regmap[HOST_CCREG]=CCREG;
8269 regmap_pre[k+1][HOST_CCREG]=CCREG;
8270 regs[k+1].wasdirty|=1<<HOST_CCREG;
8271 regs[k].dirty|=1<<HOST_CCREG;
8272 regs[k].wasconst&=~(1<<HOST_CCREG);
8273 regs[k].isconst&=~(1<<HOST_CCREG);
8274 k++;
8275 }
8276 }
8277 else {
8278 //printf("Fail Extend CC, %x ->\n",start+k*4);
8279 }
8280 }
8281 }
a5cd72d0 8282 if(dops[i].itype!=STORE&&dops[i].itype!=STORELR&&dops[i].itype!=SHIFT&&
4149788d 8283 dops[i].itype!=NOP&&dops[i].itype!=MOV&&dops[i].itype!=ALU&&dops[i].itype!=SHIFTIMM&&
a5cd72d0 8284 dops[i].itype!=IMM16&&dops[i].itype!=LOAD)
4149788d 8285 {
8286 memcpy(f_regmap,regs[i].regmap,sizeof(f_regmap));
8287 }
8288 }
8289 }
8290}
8291
8292// This allocates registers (if possible) one instruction prior
8293// to use, which can avoid a load-use penalty on certain CPUs.
8294static noinline void pass5b_preallocate2(void)
8295{
8296 int i, hr;
8297 for(i=0;i<slen-1;i++)
8298 {
8299 if (!i || !dops[i-1].is_jump)
8300 {
8301 if(!dops[i+1].bt)
8302 {
277718fa 8303 int j, can_steal = 1;
8304 for (j = i; j < i + 2; j++) {
8305 int free_regs = 0;
8306 if (cinfo[j].min_free_regs == 0)
8307 continue;
8308 for (hr = 0; hr < HOST_REGS; hr++)
8309 if (hr != EXCLUDE_REG && regs[j].regmap[hr] < 0)
8310 free_regs++;
8311 if (free_regs <= cinfo[j].min_free_regs) {
8312 can_steal = 0;
8313 break;
8314 }
8315 }
8316 if (!can_steal)
8317 continue;
4149788d 8318 if(dops[i].itype==ALU||dops[i].itype==MOV||dops[i].itype==LOAD||dops[i].itype==SHIFTIMM||dops[i].itype==IMM16
a5cd72d0 8319 ||(dops[i].itype==COP2&&dops[i].opcode2<3))
4149788d 8320 {
8321 if(dops[i+1].rs1) {
8322 if((hr=get_reg(regs[i+1].regmap,dops[i+1].rs1))>=0)
8323 {
8324 if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
8325 {
8326 regs[i].regmap[hr]=regs[i+1].regmap[hr];
8327 regmap_pre[i+1][hr]=regs[i+1].regmap[hr];
8328 regs[i+1].regmap_entry[hr]=regs[i+1].regmap[hr];
8329 regs[i].isconst&=~(1<<hr);
8330 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
8331 constmap[i][hr]=constmap[i+1][hr];
8332 regs[i+1].wasdirty&=~(1<<hr);
8333 regs[i].dirty&=~(1<<hr);
8334 }
8335 }
8336 }
8337 if(dops[i+1].rs2) {
8338 if((hr=get_reg(regs[i+1].regmap,dops[i+1].rs2))>=0)
8339 {
8340 if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
8341 {
8342 regs[i].regmap[hr]=regs[i+1].regmap[hr];
8343 regmap_pre[i+1][hr]=regs[i+1].regmap[hr];
8344 regs[i+1].regmap_entry[hr]=regs[i+1].regmap[hr];
8345 regs[i].isconst&=~(1<<hr);
8346 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
8347 constmap[i][hr]=constmap[i+1][hr];
8348 regs[i+1].wasdirty&=~(1<<hr);
8349 regs[i].dirty&=~(1<<hr);
8350 }
8351 }
8352 }
8353 // Preload target address for load instruction (non-constant)
8354 if(dops[i+1].itype==LOAD&&dops[i+1].rs1&&get_reg(regs[i+1].regmap,dops[i+1].rs1)<0) {
a5cd72d0 8355 if((hr=get_reg_w(regs[i+1].regmap, dops[i+1].rt1))>=0)
4149788d 8356 {
8357 if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
8358 {
8359 regs[i].regmap[hr]=dops[i+1].rs1;
8360 regmap_pre[i+1][hr]=dops[i+1].rs1;
8361 regs[i+1].regmap_entry[hr]=dops[i+1].rs1;
8362 regs[i].isconst&=~(1<<hr);
8363 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
8364 constmap[i][hr]=constmap[i+1][hr];
8365 regs[i+1].wasdirty&=~(1<<hr);
8366 regs[i].dirty&=~(1<<hr);
8367 }
8368 }
8369 }
8370 // Load source into target register
8371 if(dops[i+1].use_lt1&&get_reg(regs[i+1].regmap,dops[i+1].rs1)<0) {
a5cd72d0 8372 if((hr=get_reg_w(regs[i+1].regmap, dops[i+1].rt1))>=0)
4149788d 8373 {
8374 if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
8375 {
8376 regs[i].regmap[hr]=dops[i+1].rs1;
8377 regmap_pre[i+1][hr]=dops[i+1].rs1;
8378 regs[i+1].regmap_entry[hr]=dops[i+1].rs1;
8379 regs[i].isconst&=~(1<<hr);
8380 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
8381 constmap[i][hr]=constmap[i+1][hr];
8382 regs[i+1].wasdirty&=~(1<<hr);
8383 regs[i].dirty&=~(1<<hr);
8384 }
8385 }
8386 }
8387 // Address for store instruction (non-constant)
277718fa 8388 if (dops[i+1].is_store) { // SB/SH/SW/SWC2
4149788d 8389 if(get_reg(regs[i+1].regmap,dops[i+1].rs1)<0) {
8390 hr=get_reg2(regs[i].regmap,regs[i+1].regmap,-1);
8391 if(hr<0) hr=get_reg_temp(regs[i+1].regmap);
8392 else {
8393 regs[i+1].regmap[hr]=AGEN1+((i+1)&1);
8394 regs[i+1].isconst&=~(1<<hr);
277718fa 8395 regs[i+1].dirty&=~(1<<hr);
8396 regs[i+2].wasdirty&=~(1<<hr);
4149788d 8397 }
8398 assert(hr>=0);
8399 if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
8400 {
8401 regs[i].regmap[hr]=dops[i+1].rs1;
8402 regmap_pre[i+1][hr]=dops[i+1].rs1;
8403 regs[i+1].regmap_entry[hr]=dops[i+1].rs1;
8404 regs[i].isconst&=~(1<<hr);
8405 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
8406 constmap[i][hr]=constmap[i+1][hr];
8407 regs[i+1].wasdirty&=~(1<<hr);
8408 regs[i].dirty&=~(1<<hr);
8409 }
8410 }
8411 }
277718fa 8412 if (dops[i+1].itype == LOADLR || dops[i+1].opcode == 0x32) { // LWC2
4149788d 8413 if(get_reg(regs[i+1].regmap,dops[i+1].rs1)<0) {
8414 int nr;
8415 hr=get_reg(regs[i+1].regmap,FTEMP);
8416 assert(hr>=0);
8417 if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
8418 {
8419 regs[i].regmap[hr]=dops[i+1].rs1;
8420 regmap_pre[i+1][hr]=dops[i+1].rs1;
8421 regs[i+1].regmap_entry[hr]=dops[i+1].rs1;
8422 regs[i].isconst&=~(1<<hr);
8423 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
8424 constmap[i][hr]=constmap[i+1][hr];
8425 regs[i+1].wasdirty&=~(1<<hr);
8426 regs[i].dirty&=~(1<<hr);
8427 }
8428 else if((nr=get_reg2(regs[i].regmap,regs[i+1].regmap,-1))>=0)
8429 {
8430 // move it to another register
8431 regs[i+1].regmap[hr]=-1;
8432 regmap_pre[i+2][hr]=-1;
8433 regs[i+1].regmap[nr]=FTEMP;
8434 regmap_pre[i+2][nr]=FTEMP;
8435 regs[i].regmap[nr]=dops[i+1].rs1;
8436 regmap_pre[i+1][nr]=dops[i+1].rs1;
8437 regs[i+1].regmap_entry[nr]=dops[i+1].rs1;
8438 regs[i].isconst&=~(1<<nr);
8439 regs[i+1].isconst&=~(1<<nr);
8440 regs[i].dirty&=~(1<<nr);
8441 regs[i+1].wasdirty&=~(1<<nr);
8442 regs[i+1].dirty&=~(1<<nr);
8443 regs[i+2].wasdirty&=~(1<<nr);
8444 }
8445 }
8446 }
a5cd72d0 8447 if(dops[i+1].itype==LOAD||dops[i+1].itype==LOADLR||dops[i+1].itype==STORE||dops[i+1].itype==STORELR/*||dops[i+1].itype==C2LS*/) {
4149788d 8448 hr = -1;
8449 if(dops[i+1].itype==LOAD)
a5cd72d0 8450 hr=get_reg_w(regs[i+1].regmap, dops[i+1].rt1);
277718fa 8451 if (dops[i+1].itype == LOADLR || dops[i+1].opcode == 0x32) // LWC2
4149788d 8452 hr=get_reg(regs[i+1].regmap,FTEMP);
277718fa 8453 if (dops[i+1].is_store) {
4149788d 8454 hr=get_reg(regs[i+1].regmap,AGEN1+((i+1)&1));
8455 if(hr<0) hr=get_reg_temp(regs[i+1].regmap);
8456 }
8457 if(hr>=0&&regs[i].regmap[hr]<0) {
8458 int rs=get_reg(regs[i+1].regmap,dops[i+1].rs1);
8459 if(rs>=0&&((regs[i+1].wasconst>>rs)&1)) {
8460 regs[i].regmap[hr]=AGEN1+((i+1)&1);
8461 regmap_pre[i+1][hr]=AGEN1+((i+1)&1);
8462 regs[i+1].regmap_entry[hr]=AGEN1+((i+1)&1);
8463 regs[i].isconst&=~(1<<hr);
8464 regs[i+1].wasdirty&=~(1<<hr);
8465 regs[i].dirty&=~(1<<hr);
8466 }
b372a952 8467 }
8468 }
57871462 8469 }
8470 }
4149788d 8471 }
8472 }
8473}
8474
8475// Write back dirty registers as soon as we will no longer modify them,
8476// so that we don't end up with lots of writes at the branches.
8477static noinline void pass6_clean_registers(int istart, int iend, int wr)
8478{
53358c1d 8479 static u_int wont_dirty[MAXBLOCK];
8480 static u_int will_dirty[MAXBLOCK];
4149788d 8481 int i;
8482 int r;
8483 u_int will_dirty_i,will_dirty_next,temp_will_dirty;
8484 u_int wont_dirty_i,wont_dirty_next,temp_wont_dirty;
8485 if(iend==slen-1) {
8486 will_dirty_i=will_dirty_next=0;
8487 wont_dirty_i=wont_dirty_next=0;
8488 }else{
8489 will_dirty_i=will_dirty_next=will_dirty[iend+1];
8490 wont_dirty_i=wont_dirty_next=wont_dirty[iend+1];
8491 }
8492 for (i=iend;i>=istart;i--)
8493 {
8494 signed char rregmap_i[RRMAP_SIZE];
8495 u_int hr_candirty = 0;
8496 assert(HOST_REGS < 32);
8497 make_rregs(regs[i].regmap, rregmap_i, &hr_candirty);
8498 __builtin_prefetch(regs[i-1].regmap);
8499 if(dops[i].is_jump)
8500 {
8501 signed char branch_rregmap_i[RRMAP_SIZE];
8502 u_int branch_hr_candirty = 0;
8503 make_rregs(branch_regs[i].regmap, branch_rregmap_i, &branch_hr_candirty);
277718fa 8504 if(cinfo[i].ba<start || cinfo[i].ba>=(start+slen*4))
4149788d 8505 {
8506 // Branch out of this block, flush all regs
8507 will_dirty_i = 0;
8508 will_dirty_i |= 1u << (get_rreg(branch_rregmap_i, dops[i].rt1) & 31);
8509 will_dirty_i |= 1u << (get_rreg(branch_rregmap_i, dops[i].rt2) & 31);
8510 will_dirty_i |= 1u << (get_rreg(branch_rregmap_i, dops[i+1].rt1) & 31);
8511 will_dirty_i |= 1u << (get_rreg(branch_rregmap_i, dops[i+1].rt2) & 31);
8512 will_dirty_i |= 1u << (get_rreg(branch_rregmap_i, CCREG) & 31);
8513 will_dirty_i &= branch_hr_candirty;
8514 if (dops[i].is_ujump)
8515 {
8516 // Unconditional branch
8517 wont_dirty_i = 0;
8518 // Merge in delay slot (will dirty)
8519 will_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i].rt1) & 31);
8520 will_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i].rt2) & 31);
8521 will_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i+1].rt1) & 31);
8522 will_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i+1].rt2) & 31);
8523 will_dirty_i |= 1u << (get_rreg(rregmap_i, CCREG) & 31);
8524 will_dirty_i &= hr_candirty;
57871462 8525 }
4149788d 8526 else
8527 {
8528 // Conditional branch
8529 wont_dirty_i = wont_dirty_next;
8530 // Merge in delay slot (will dirty)
8531 // (the original code had no explanation why these 2 are commented out)
8532 //will_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i].rt1) & 31);
8533 //will_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i].rt2) & 31);
8534 will_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i+1].rt1) & 31);
8535 will_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i+1].rt2) & 31);
8536 will_dirty_i |= 1u << (get_rreg(rregmap_i, CCREG) & 31);
8537 will_dirty_i &= hr_candirty;
8538 }
8539 // Merge in delay slot (wont dirty)
8540 wont_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i].rt1) & 31);
8541 wont_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i].rt2) & 31);
8542 wont_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i+1].rt1) & 31);
8543 wont_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i+1].rt2) & 31);
8544 wont_dirty_i |= 1u << (get_rreg(rregmap_i, CCREG) & 31);
8545 wont_dirty_i |= 1u << (get_rreg(branch_rregmap_i, dops[i].rt1) & 31);
8546 wont_dirty_i |= 1u << (get_rreg(branch_rregmap_i, dops[i].rt2) & 31);
8547 wont_dirty_i |= 1u << (get_rreg(branch_rregmap_i, dops[i+1].rt1) & 31);
8548 wont_dirty_i |= 1u << (get_rreg(branch_rregmap_i, dops[i+1].rt2) & 31);
8549 wont_dirty_i |= 1u << (get_rreg(branch_rregmap_i, CCREG) & 31);
8550 wont_dirty_i &= ~(1u << 31);
8551 if(wr) {
8552 #ifndef DESTRUCTIVE_WRITEBACK
8553 branch_regs[i].dirty&=wont_dirty_i;
8554 #endif
8555 branch_regs[i].dirty|=will_dirty_i;
8556 }
8557 }
8558 else
8559 {
8560 // Internal branch
277718fa 8561 if(cinfo[i].ba<=start+i*4) {
4149788d 8562 // Backward branch
8563 if (dops[i].is_ujump)
8564 {
8565 // Unconditional branch
8566 temp_will_dirty=0;
8567 temp_wont_dirty=0;
8568 // Merge in delay slot (will dirty)
8569 temp_will_dirty |= 1u << (get_rreg(branch_rregmap_i, dops[i].rt1) & 31);
8570 temp_will_dirty |= 1u << (get_rreg(branch_rregmap_i, dops[i].rt2) & 31);
8571 temp_will_dirty |= 1u << (get_rreg(branch_rregmap_i, dops[i+1].rt1) & 31);
8572 temp_will_dirty |= 1u << (get_rreg(branch_rregmap_i, dops[i+1].rt2) & 31);
8573 temp_will_dirty |= 1u << (get_rreg(branch_rregmap_i, CCREG) & 31);
8574 temp_will_dirty &= branch_hr_candirty;
8575 temp_will_dirty |= 1u << (get_rreg(rregmap_i, dops[i].rt1) & 31);
8576 temp_will_dirty |= 1u << (get_rreg(rregmap_i, dops[i].rt2) & 31);
8577 temp_will_dirty |= 1u << (get_rreg(rregmap_i, dops[i+1].rt1) & 31);
8578 temp_will_dirty |= 1u << (get_rreg(rregmap_i, dops[i+1].rt2) & 31);
8579 temp_will_dirty |= 1u << (get_rreg(rregmap_i, CCREG) & 31);
8580 temp_will_dirty &= hr_candirty;
8581 } else {
8582 // Conditional branch (not taken case)
8583 temp_will_dirty=will_dirty_next;
8584 temp_wont_dirty=wont_dirty_next;
8585 // Merge in delay slot (will dirty)
8586 temp_will_dirty |= 1u << (get_rreg(branch_rregmap_i, dops[i].rt1) & 31);
8587 temp_will_dirty |= 1u << (get_rreg(branch_rregmap_i, dops[i].rt2) & 31);
8588 temp_will_dirty |= 1u << (get_rreg(branch_rregmap_i, dops[i+1].rt1) & 31);
8589 temp_will_dirty |= 1u << (get_rreg(branch_rregmap_i, dops[i+1].rt2) & 31);
8590 temp_will_dirty |= 1u << (get_rreg(branch_rregmap_i, CCREG) & 31);
8591 temp_will_dirty &= branch_hr_candirty;
8592 //temp_will_dirty |= 1u << (get_rreg(rregmap_i, dops[i].rt1) & 31);
8593 //temp_will_dirty |= 1u << (get_rreg(rregmap_i, dops[i].rt2) & 31);
8594 temp_will_dirty |= 1u << (get_rreg(rregmap_i, dops[i+1].rt1) & 31);
8595 temp_will_dirty |= 1u << (get_rreg(rregmap_i, dops[i+1].rt2) & 31);
8596 temp_will_dirty |= 1u << (get_rreg(rregmap_i, CCREG) & 31);
8597 temp_will_dirty &= hr_candirty;
8598 }
8599 // Merge in delay slot (wont dirty)
8600 temp_wont_dirty |= 1u << (get_rreg(rregmap_i, dops[i].rt1) & 31);
8601 temp_wont_dirty |= 1u << (get_rreg(rregmap_i, dops[i].rt2) & 31);
8602 temp_wont_dirty |= 1u << (get_rreg(rregmap_i, dops[i+1].rt1) & 31);
8603 temp_wont_dirty |= 1u << (get_rreg(rregmap_i, dops[i+1].rt2) & 31);
8604 temp_wont_dirty |= 1u << (get_rreg(rregmap_i, CCREG) & 31);
8605 temp_wont_dirty |= 1u << (get_rreg(branch_rregmap_i, dops[i].rt1) & 31);
8606 temp_wont_dirty |= 1u << (get_rreg(branch_rregmap_i, dops[i].rt2) & 31);
8607 temp_wont_dirty |= 1u << (get_rreg(branch_rregmap_i, dops[i+1].rt1) & 31);
8608 temp_wont_dirty |= 1u << (get_rreg(branch_rregmap_i, dops[i+1].rt2) & 31);
8609 temp_wont_dirty |= 1u << (get_rreg(branch_rregmap_i, CCREG) & 31);
8610 temp_wont_dirty &= ~(1u << 31);
8611 // Deal with changed mappings
8612 if(i<iend) {
8613 for(r=0;r<HOST_REGS;r++) {
8614 if(r!=EXCLUDE_REG) {
8615 if(regs[i].regmap[r]!=regmap_pre[i][r]) {
8616 temp_will_dirty&=~(1<<r);
8617 temp_wont_dirty&=~(1<<r);
8618 if(regmap_pre[i][r]>0 && regmap_pre[i][r]<34) {
8619 temp_will_dirty|=((unneeded_reg[i]>>regmap_pre[i][r])&1)<<r;
8620 temp_wont_dirty|=((unneeded_reg[i]>>regmap_pre[i][r])&1)<<r;
8621 } else {
8622 temp_will_dirty|=1<<r;
8623 temp_wont_dirty|=1<<r;
8624 }
8625 }
8626 }
8627 }
8628 }
8629 if(wr) {
8630 will_dirty[i]=temp_will_dirty;
8631 wont_dirty[i]=temp_wont_dirty;
277718fa 8632 pass6_clean_registers((cinfo[i].ba-start)>>2,i-1,0);
4149788d 8633 }else{
8634 // Limit recursion. It can take an excessive amount
8635 // of time if there are a lot of nested loops.
277718fa 8636 will_dirty[(cinfo[i].ba-start)>>2]=0;
8637 wont_dirty[(cinfo[i].ba-start)>>2]=-1;
57871462 8638 }
57871462 8639 }
4149788d 8640 /*else*/ if(1)
57871462 8641 {
4149788d 8642 if (dops[i].is_ujump)
8643 {
8644 // Unconditional branch
8645 will_dirty_i=0;
8646 wont_dirty_i=0;
277718fa 8647 //if(cinfo[i].ba>start+i*4) { // Disable recursion (for debugging)
4149788d 8648 for(r=0;r<HOST_REGS;r++) {
8649 if(r!=EXCLUDE_REG) {
277718fa 8650 if(branch_regs[i].regmap[r]==regs[(cinfo[i].ba-start)>>2].regmap_entry[r]) {
8651 will_dirty_i|=will_dirty[(cinfo[i].ba-start)>>2]&(1<<r);
8652 wont_dirty_i|=wont_dirty[(cinfo[i].ba-start)>>2]&(1<<r);
4149788d 8653 }
8654 if(branch_regs[i].regmap[r]>=0) {
277718fa 8655 will_dirty_i|=((unneeded_reg[(cinfo[i].ba-start)>>2]>>branch_regs[i].regmap[r])&1)<<r;
8656 wont_dirty_i|=((unneeded_reg[(cinfo[i].ba-start)>>2]>>branch_regs[i].regmap[r])&1)<<r;
4149788d 8657 }
8658 }
57871462 8659 }
4149788d 8660 //}
8661 // Merge in delay slot
8662 will_dirty_i |= 1u << (get_rreg(branch_rregmap_i, dops[i].rt1) & 31);
8663 will_dirty_i |= 1u << (get_rreg(branch_rregmap_i, dops[i].rt2) & 31);
8664 will_dirty_i |= 1u << (get_rreg(branch_rregmap_i, dops[i+1].rt1) & 31);
8665 will_dirty_i |= 1u << (get_rreg(branch_rregmap_i, dops[i+1].rt2) & 31);
8666 will_dirty_i |= 1u << (get_rreg(branch_rregmap_i, CCREG) & 31);
8667 will_dirty_i &= branch_hr_candirty;
8668 will_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i].rt1) & 31);
8669 will_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i].rt2) & 31);
8670 will_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i+1].rt1) & 31);
8671 will_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i+1].rt2) & 31);
8672 will_dirty_i |= 1u << (get_rreg(rregmap_i, CCREG) & 31);
8673 will_dirty_i &= hr_candirty;
8674 } else {
8675 // Conditional branch
8676 will_dirty_i=will_dirty_next;
8677 wont_dirty_i=wont_dirty_next;
277718fa 8678 //if(cinfo[i].ba>start+i*4) // Disable recursion (for debugging)
4149788d 8679 for(r=0;r<HOST_REGS;r++) {
8680 if(r!=EXCLUDE_REG) {
8681 signed char target_reg=branch_regs[i].regmap[r];
277718fa 8682 if(target_reg==regs[(cinfo[i].ba-start)>>2].regmap_entry[r]) {
8683 will_dirty_i&=will_dirty[(cinfo[i].ba-start)>>2]&(1<<r);
8684 wont_dirty_i|=wont_dirty[(cinfo[i].ba-start)>>2]&(1<<r);
4149788d 8685 }
8686 else if(target_reg>=0) {
277718fa 8687 will_dirty_i&=((unneeded_reg[(cinfo[i].ba-start)>>2]>>target_reg)&1)<<r;
8688 wont_dirty_i|=((unneeded_reg[(cinfo[i].ba-start)>>2]>>target_reg)&1)<<r;
4149788d 8689 }
8690 }
57871462 8691 }
4149788d 8692 // Merge in delay slot
8693 will_dirty_i |= 1u << (get_rreg(branch_rregmap_i, dops[i].rt1) & 31);
8694 will_dirty_i |= 1u << (get_rreg(branch_rregmap_i, dops[i].rt2) & 31);
8695 will_dirty_i |= 1u << (get_rreg(branch_rregmap_i, dops[i+1].rt1) & 31);
8696 will_dirty_i |= 1u << (get_rreg(branch_rregmap_i, dops[i+1].rt2) & 31);
8697 will_dirty_i |= 1u << (get_rreg(branch_rregmap_i, CCREG) & 31);
8698 will_dirty_i &= branch_hr_candirty;
8699 //will_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i].rt1) & 31);
8700 //will_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i].rt2) & 31);
8701 will_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i+1].rt1) & 31);
8702 will_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i+1].rt2) & 31);
8703 will_dirty_i |= 1u << (get_rreg(rregmap_i, CCREG) & 31);
8704 will_dirty_i &= hr_candirty;
57871462 8705 }
4149788d 8706 // Merge in delay slot (won't dirty)
8707 wont_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i].rt1) & 31);
8708 wont_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i].rt2) & 31);
8709 wont_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i+1].rt1) & 31);
8710 wont_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i+1].rt2) & 31);
8711 wont_dirty_i |= 1u << (get_rreg(rregmap_i, CCREG) & 31);
8712 wont_dirty_i |= 1u << (get_rreg(branch_rregmap_i, dops[i].rt1) & 31);
8713 wont_dirty_i |= 1u << (get_rreg(branch_rregmap_i, dops[i].rt2) & 31);
8714 wont_dirty_i |= 1u << (get_rreg(branch_rregmap_i, dops[i+1].rt1) & 31);
8715 wont_dirty_i |= 1u << (get_rreg(branch_rregmap_i, dops[i+1].rt2) & 31);
8716 wont_dirty_i |= 1u << (get_rreg(branch_rregmap_i, CCREG) & 31);
8717 wont_dirty_i &= ~(1u << 31);
8718 if(wr) {
8719 #ifndef DESTRUCTIVE_WRITEBACK
8720 branch_regs[i].dirty&=wont_dirty_i;
8721 #endif
8722 branch_regs[i].dirty|=will_dirty_i;
57871462 8723 }
8724 }
8725 }
57871462 8726 }
277718fa 8727 else if (dops[i].is_exception)
4149788d 8728 {
277718fa 8729 // SYSCALL instruction, etc
4149788d 8730 will_dirty_i=0;
8731 wont_dirty_i=0;
8732 }
8733 will_dirty_next=will_dirty_i;
8734 wont_dirty_next=wont_dirty_i;
8735 will_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i].rt1) & 31);
8736 will_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i].rt2) & 31);
8737 will_dirty_i |= 1u << (get_rreg(rregmap_i, CCREG) & 31);
8738 will_dirty_i &= hr_candirty;
8739 wont_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i].rt1) & 31);
8740 wont_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i].rt2) & 31);
8741 wont_dirty_i |= 1u << (get_rreg(rregmap_i, CCREG) & 31);
8742 wont_dirty_i &= ~(1u << 31);
8743 if (i > istart && !dops[i].is_jump) {
8744 // Don't store a register immediately after writing it,
8745 // may prevent dual-issue.
8746 wont_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i-1].rt1) & 31);
8747 wont_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i-1].rt2) & 31);
8748 }
8749 // Save it
8750 will_dirty[i]=will_dirty_i;
8751 wont_dirty[i]=wont_dirty_i;
8752 // Mark registers that won't be dirtied as not dirty
8753 if(wr) {
8754 regs[i].dirty|=will_dirty_i;
8755 #ifndef DESTRUCTIVE_WRITEBACK
8756 regs[i].dirty&=wont_dirty_i;
8757 if(dops[i].is_jump)
57871462 8758 {
4149788d 8759 if (i < iend-1 && !dops[i].is_ujump) {
8760 for(r=0;r<HOST_REGS;r++) {
8761 if(r!=EXCLUDE_REG) {
8762 if(regs[i].regmap[r]==regmap_pre[i+2][r]) {
8763 regs[i+2].wasdirty&=wont_dirty_i|~(1<<r);
8764 }else {/*printf("i: %x (%d) mismatch(+2): %d\n",start+i*4,i,r);assert(!((wont_dirty_i>>r)&1));*/}
57871462 8765 }
8766 }
8767 }
4149788d 8768 }
8769 else
8770 {
8771 if(i<iend) {
8772 for(r=0;r<HOST_REGS;r++) {
8773 if(r!=EXCLUDE_REG) {
8774 if(regs[i].regmap[r]==regmap_pre[i+1][r]) {
8775 regs[i+1].wasdirty&=wont_dirty_i|~(1<<r);
8776 }else {/*printf("i: %x (%d) mismatch(+1): %d\n",start+i*4,i,r);assert(!((wont_dirty_i>>r)&1));*/}
57871462 8777 }
8778 }
8779 }
4149788d 8780 }
8781 #endif
8782 }
8783 // Deal with changed mappings
8784 temp_will_dirty=will_dirty_i;
8785 temp_wont_dirty=wont_dirty_i;
8786 for(r=0;r<HOST_REGS;r++) {
8787 if(r!=EXCLUDE_REG) {
8788 int nr;
8789 if(regs[i].regmap[r]==regmap_pre[i][r]) {
8790 if(wr) {
8791 #ifndef DESTRUCTIVE_WRITEBACK
8792 regs[i].wasdirty&=wont_dirty_i|~(1<<r);
8793 #endif
8794 regs[i].wasdirty|=will_dirty_i&(1<<r);
57871462 8795 }
4149788d 8796 }
8797 else if(regmap_pre[i][r]>=0&&(nr=get_rreg(rregmap_i,regmap_pre[i][r]))>=0) {
8798 // Register moved to a different register
8799 will_dirty_i&=~(1<<r);
8800 wont_dirty_i&=~(1<<r);
8801 will_dirty_i|=((temp_will_dirty>>nr)&1)<<r;
8802 wont_dirty_i|=((temp_wont_dirty>>nr)&1)<<r;
8803 if(wr) {
8804 #ifndef DESTRUCTIVE_WRITEBACK
8805 regs[i].wasdirty&=wont_dirty_i|~(1<<r);
8806 #endif
8807 regs[i].wasdirty|=will_dirty_i&(1<<r);
8808 }
8809 }
8810 else {
8811 will_dirty_i&=~(1<<r);
8812 wont_dirty_i&=~(1<<r);
8813 if(regmap_pre[i][r]>0 && regmap_pre[i][r]<34) {
8814 will_dirty_i|=((unneeded_reg[i]>>regmap_pre[i][r])&1)<<r;
8815 wont_dirty_i|=((unneeded_reg[i]>>regmap_pre[i][r])&1)<<r;
8816 } else {
8817 wont_dirty_i|=1<<r;
8818 /*printf("i: %x (%d) mismatch: %d\n",start+i*4,i,r);assert(!((will_dirty>>r)&1));*/
57871462 8819 }
8820 }
8821 }
8822 }
8823 }
4149788d 8824}
8825
8826static noinline void pass10_expire_blocks(void)
8827{
93c0345b 8828 u_int step = MAX_OUTPUT_BLOCK_SIZE / PAGE_COUNT / 2;
8829 // not sizeof(ndrc->translation_cache) due to vita hack
8830 u_int step_mask = ((1u << TARGET_SIZE_2) - 1u) & ~(step - 1u);
8831 u_int end = (out - ndrc->translation_cache + EXPIRITY_OFFSET) & step_mask;
8832 u_int base_shift = __builtin_ctz(MAX_OUTPUT_BLOCK_SIZE);
8833 int hit;
8834
8835 for (; expirep != end; expirep = ((expirep + step) & step_mask))
4149788d 8836 {
93c0345b 8837 u_int base_offs = expirep & ~(MAX_OUTPUT_BLOCK_SIZE - 1);
8838 u_int block_i = expirep / step & (PAGE_COUNT - 1);
8839 u_int phase = (expirep >> (base_shift - 1)) & 1u;
8840 if (!(expirep & (MAX_OUTPUT_BLOCK_SIZE / 2 - 1))) {
9b495f6e 8841 inv_debug("EXP: base_offs %x/%lx phase %u\n", base_offs,
8842 (long)(out - ndrc->translation_cache), phase);
93c0345b 8843 }
8844
8845 if (!phase) {
8846 hit = blocks_remove_matching_addrs(&blocks[block_i], base_offs, base_shift);
8847 if (hit) {
8848 do_clear_cache();
8849 #ifdef USE_MINI_HT
8850 memset(mini_ht, -1, sizeof(mini_ht));
8851 #endif
8852 }
4149788d 8853 }
93c0345b 8854 else
b7ad2f2c 8855 unlink_jumps_tc_range(jumps[block_i], base_offs, base_shift);
4149788d 8856 }
8857}
8858
104df9d3 8859static struct block_info *new_block_info(u_int start, u_int len,
8860 const void *source, const void *copy, u_char *beginning, u_short jump_in_count)
8861{
8862 struct block_info **b_pptr;
8863 struct block_info *block;
8864 u_int page = get_page(start);
8865
8866 block = malloc(sizeof(*block) + jump_in_count * sizeof(block->jump_in[0]));
8867 assert(block);
8868 assert(jump_in_count > 0);
8869 block->source = source;
8870 block->copy = copy;
8871 block->start = start;
8872 block->len = len;
8873 block->reg_sv_flags = 0;
8874 block->tc_offs = beginning - ndrc->translation_cache;
8875 //block->tc_len = out - beginning;
8876 block->is_dirty = 0;
3280e616 8877 block->inv_near_misses = 0;
104df9d3 8878 block->jump_in_cnt = jump_in_count;
8879
93c0345b 8880 // insert sorted by start mirror-unmasked vaddr
104df9d3 8881 for (b_pptr = &blocks[page]; ; b_pptr = &((*b_pptr)->next)) {
8882 if (*b_pptr == NULL || (*b_pptr)->start >= start) {
8883 block->next = *b_pptr;
8884 *b_pptr = block;
8885 break;
8886 }
8887 }
8888 stat_inc(stat_blocks);
8889 return block;
8890}
8891
8892static int new_recompile_block(u_int addr)
4149788d 8893{
8894 u_int pagelimit = 0;
8895 u_int state_rflags = 0;
8896 int i;
8897
8898 assem_debug("NOTCOMPILED: addr = %x -> %p\n", addr, out);
8899
a5cd72d0 8900 if (addr & 3) {
8901 if (addr != hack_addr) {
8902 SysPrintf("game crash @%08x, ra=%08x\n", addr, psxRegs.GPR.n.ra);
8903 hack_addr = addr;
8904 }
8905 return -1;
8906 }
8907
4149788d 8908 // this is just for speculation
8909 for (i = 1; i < 32; i++) {
8910 if ((psxRegs.GPR.r[i] & 0xffff0000) == 0x1f800000)
8911 state_rflags |= 1 << i;
8912 }
8913
a5cd72d0 8914 start = addr;
4149788d 8915 new_dynarec_did_compile=1;
8916 if (Config.HLE && start == 0x80001000) // hlecall
8917 {
8918 // XXX: is this enough? Maybe check hleSoftCall?
104df9d3 8919 void *beginning = start_block();
4149788d 8920
4149788d 8921 emit_movimm(start,0);
8922 emit_writeword(0,&pcaddr);
8923 emit_far_jump(new_dyna_leave);
8924 literal_pool(0);
8925 end_block(beginning);
104df9d3 8926 struct block_info *block = new_block_info(start, 4, NULL, NULL, beginning, 1);
8927 block->jump_in[0].vaddr = start;
8928 block->jump_in[0].addr = beginning;
4149788d 8929 return 0;
8930 }
8931 else if (f1_hack && hack_addr == 0) {
8932 void *beginning = start_block();
4149788d 8933 emit_movimm(start, 0);
8934 emit_writeword(0, &hack_addr);
8935 emit_readword(&psxRegs.GPR.n.sp, 0);
8936 emit_readptr(&mem_rtab, 1);
8937 emit_shrimm(0, 12, 2);
8938 emit_readptr_dualindexedx_ptrlen(1, 2, 1);
8939 emit_addimm(0, 0x18, 0);
8940 emit_adds_ptr(1, 1, 1);
8941 emit_ldr_dualindexed(1, 0, 0);
8942 emit_writeword(0, &psxRegs.GPR.r[26]); // lw k0, 0x18(sp)
104df9d3 8943 emit_far_call(ndrc_get_addr_ht);
4149788d 8944 emit_jmpreg(0); // jr k0
8945 literal_pool(0);
8946 end_block(beginning);
8947
104df9d3 8948 struct block_info *block = new_block_info(start, 4, NULL, NULL, beginning, 1);
8949 block->jump_in[0].vaddr = start;
8950 block->jump_in[0].addr = beginning;
4149788d 8951 SysPrintf("F1 hack to %08x\n", start);
8952 return 0;
8953 }
8954
d5aeda23 8955 cycle_multiplier_active = Config.cycle_multiplier_override && Config.cycle_multiplier == CYCLE_MULT_DEFAULT
8956 ? Config.cycle_multiplier_override : Config.cycle_multiplier;
4149788d 8957
8958 source = get_source_start(start, &pagelimit);
8959 if (source == NULL) {
8960 if (addr != hack_addr) {
8961 SysPrintf("Compile at bogus memory address: %08x\n", addr);
8962 hack_addr = addr;
8963 }
8964 //abort();
8965 return -1;
8966 }
8967
8968 /* Pass 1: disassemble */
8969 /* Pass 2: register dependencies, branch targets */
8970 /* Pass 3: register allocation */
8971 /* Pass 4: branch dependencies */
8972 /* Pass 5: pre-alloc */
8973 /* Pass 6: optimize clean/dirty state */
8974 /* Pass 7: flag 32-bit registers */
8975 /* Pass 8: assembly */
8976 /* Pass 9: linker */
8977 /* Pass 10: garbage collection / free memory */
8978
8979 /* Pass 1 disassembly */
8980
8981 pass1_disassemble(pagelimit);
8982
8983 int clear_hack_addr = apply_hacks();
8984
8985 /* Pass 2 - Register dependencies and branch targets */
8986
8987 pass2_unneeded_regs(0,slen-1,0);
8988
f9e9616e 8989 pass2a_unneeded_other();
8990
4149788d 8991 /* Pass 3 - Register allocation */
8992
8993 pass3_register_alloc(addr);
8994
8995 /* Pass 4 - Cull unused host registers */
8996
8997 pass4_cull_unused_regs();
8998
8999 /* Pass 5 - Pre-allocate registers */
9000
9001 pass5a_preallocate1();
9002 pass5b_preallocate2();
9f51b4b9 9003
57871462 9004 /* Pass 6 - Optimize clean/dirty state */
4149788d 9005 pass6_clean_registers(0, slen-1, 1);
9f51b4b9 9006
33a1eda1 9007 /* Pass 7 */
04fd948a 9008 for (i=slen-1;i>=0;i--)
9009 {
cf95b4f0 9010 if(dops[i].itype==CJUMP||dops[i].itype==SJUMP)
04fd948a 9011 {
9012 // Conditional branch
9013 if((source[i]>>16)!=0x1000&&i<slen-2) {
9014 // Mark this address as a branch target since it may be called
9015 // upon return from interrupt
cf95b4f0 9016 dops[i+2].bt=1;
04fd948a 9017 }
9018 }
9019 }
57871462 9020
57871462 9021 /* Pass 8 - Assembly */
9022 linkcount=0;stubcount=0;
4149788d 9023 is_delayslot=0;
57871462 9024 u_int dirty_pre=0;
d148d265 9025 void *beginning=start_block();
df4dc2b1 9026 void *instr_addr0_override = NULL;
4bdc30ab 9027 int ds = 0;
9ad4d757 9028
9ad4d757 9029 if (start == 0x80030000) {
3968e69e 9030 // nasty hack for the fastbios thing
96186eba 9031 // override block entry to this code
df4dc2b1 9032 instr_addr0_override = out;
9ad4d757 9033 emit_movimm(start,0);
96186eba 9034 // abuse io address var as a flag that we
9035 // have already returned here once
643aeae3 9036 emit_readword(&address,1);
9037 emit_writeword(0,&pcaddr);
9038 emit_writeword(0,&address);
9ad4d757 9039 emit_cmp(0,1);
3968e69e 9040 #ifdef __aarch64__
9041 emit_jeq(out + 4*2);
2a014d73 9042 emit_far_jump(new_dyna_leave);
3968e69e 9043 #else
643aeae3 9044 emit_jne(new_dyna_leave);
3968e69e 9045 #endif
9ad4d757 9046 }
57871462 9047 for(i=0;i<slen;i++)
9048 {
9de8a0c3 9049 __builtin_prefetch(regs[i+1].regmap);
670c0f22 9050 check_regmap(regmap_pre[i]);
9051 check_regmap(regs[i].regmap_entry);
9052 check_regmap(regs[i].regmap);
57871462 9053 //if(ds) printf("ds: ");
4600ba03 9054 disassemble_inst(i);
57871462 9055 if(ds) {
9056 ds=0; // Skip delay slot
cf95b4f0 9057 if(dops[i].bt) assem_debug("OOPS - branch into delay slot\n");
df4dc2b1 9058 instr_addr[i] = NULL;
57871462 9059 } else {
ffb0b9e0 9060 speculate_register_values(i);
57871462 9061 #ifndef DESTRUCTIVE_WRITEBACK
fe807a8a 9062 if (i < 2 || !dops[i-2].is_ujump)
57871462 9063 {
ad49de89 9064 wb_valid(regmap_pre[i],regs[i].regmap_entry,dirty_pre,regs[i].wasdirty,unneeded_reg[i]);
57871462 9065 }
fe807a8a 9066 if((dops[i].itype==CJUMP||dops[i].itype==SJUMP)) {
f776eb14 9067 dirty_pre=branch_regs[i].dirty;
9068 }else{
f776eb14 9069 dirty_pre=regs[i].dirty;
9070 }
57871462 9071 #endif
9072 // write back
fe807a8a 9073 if (i < 2 || !dops[i-2].is_ujump)
57871462 9074 {
ad49de89 9075 wb_invalidate(regmap_pre[i],regs[i].regmap_entry,regs[i].wasdirty,unneeded_reg[i]);
57871462 9076 loop_preload(regmap_pre[i],regs[i].regmap_entry);
9077 }
9078 // branch target entry point
df4dc2b1 9079 instr_addr[i] = out;
57871462 9080 assem_debug("<->\n");
277718fa 9081 drc_dbg_emit_do_cmp(i, cinfo[i].ccadj);
7f94b097 9082 if (clear_hack_addr) {
9083 emit_movimm(0, 0);
9084 emit_writeword(0, &hack_addr);
9085 clear_hack_addr = 0;
9086 }
dd114d7d 9087
57871462 9088 // load regs
9089 if(regs[i].regmap_entry[HOST_CCREG]==CCREG&&regs[i].regmap[HOST_CCREG]!=CCREG)
ad49de89 9090 wb_register(CCREG,regs[i].regmap_entry,regs[i].wasdirty);
cf95b4f0 9091 load_regs(regs[i].regmap_entry,regs[i].regmap,dops[i].rs1,dops[i].rs2);
57871462 9092 address_generation(i,&regs[i],regs[i].regmap_entry);
ad49de89 9093 load_consts(regmap_pre[i],regs[i].regmap,i);
fe807a8a 9094 if(dops[i].is_jump)
57871462 9095 {
9096 // Load the delay slot registers if necessary
cf95b4f0 9097 if(dops[i+1].rs1!=dops[i].rs1&&dops[i+1].rs1!=dops[i].rs2&&(dops[i+1].rs1!=dops[i].rt1||dops[i].rt1==0))
9098 load_regs(regs[i].regmap_entry,regs[i].regmap,dops[i+1].rs1,dops[i+1].rs1);
9099 if(dops[i+1].rs2!=dops[i+1].rs1&&dops[i+1].rs2!=dops[i].rs1&&dops[i+1].rs2!=dops[i].rs2&&(dops[i+1].rs2!=dops[i].rt1||dops[i].rt1==0))
9100 load_regs(regs[i].regmap_entry,regs[i].regmap,dops[i+1].rs2,dops[i+1].rs2);
37387d8b 9101 if (ram_offset && (dops[i+1].is_load || dops[i+1].is_store))
53358c1d 9102 load_reg(regs[i].regmap_entry,regs[i].regmap,ROREG);
37387d8b 9103 if (dops[i+1].is_store)
53358c1d 9104 load_reg(regs[i].regmap_entry,regs[i].regmap,INVCP);
57871462 9105 }
9106 else if(i+1<slen)
9107 {
9108 // Preload registers for following instruction
cf95b4f0 9109 if(dops[i+1].rs1!=dops[i].rs1&&dops[i+1].rs1!=dops[i].rs2)
9110 if(dops[i+1].rs1!=dops[i].rt1&&dops[i+1].rs1!=dops[i].rt2)
9111 load_regs(regs[i].regmap_entry,regs[i].regmap,dops[i+1].rs1,dops[i+1].rs1);
9112 if(dops[i+1].rs2!=dops[i+1].rs1&&dops[i+1].rs2!=dops[i].rs1&&dops[i+1].rs2!=dops[i].rs2)
9113 if(dops[i+1].rs2!=dops[i].rt1&&dops[i+1].rs2!=dops[i].rt2)
9114 load_regs(regs[i].regmap_entry,regs[i].regmap,dops[i+1].rs2,dops[i+1].rs2);
57871462 9115 }
9116 // TODO: if(is_ooo(i)) address_generation(i+1);
9a3ccfeb 9117 if (!dops[i].is_jump || dops[i].itype == CJUMP)
53358c1d 9118 load_reg(regs[i].regmap_entry,regs[i].regmap,CCREG);
37387d8b 9119 if (ram_offset && (dops[i].is_load || dops[i].is_store))
53358c1d 9120 load_reg(regs[i].regmap_entry,regs[i].regmap,ROREG);
37387d8b 9121 if (dops[i].is_store)
53358c1d 9122 load_reg(regs[i].regmap_entry,regs[i].regmap,INVCP);
2330734f 9123
277718fa 9124 ds = assemble(i, &regs[i], cinfo[i].ccadj);
2330734f 9125
fe807a8a 9126 if (dops[i].is_ujump)
57871462 9127 literal_pool(1024);
9128 else
9129 literal_pool_jumpover(256);
9130 }
9131 }
3d680478 9132
9133 assert(slen > 0);
cf95b4f0 9134 if (slen > 0 && dops[slen-1].itype == INTCALL) {
3d680478 9135 // no ending needed for this block since INTCALL never returns
9136 }
57871462 9137 // If the block did not end with an unconditional branch,
9138 // add a jump to the next instruction.
3d680478 9139 else if (i > 1) {
4bdc30ab 9140 if (!dops[i-2].is_ujump) {
fe807a8a 9141 assert(!dops[i-1].is_jump);
57871462 9142 assert(i==slen);
cf95b4f0 9143 if(dops[i-2].itype!=CJUMP&&dops[i-2].itype!=SJUMP) {
ad49de89 9144 store_regs_bt(regs[i-1].regmap,regs[i-1].dirty,start+i*4);
57871462 9145 if(regs[i-1].regmap[HOST_CCREG]!=CCREG)
9146 emit_loadreg(CCREG,HOST_CCREG);
277718fa 9147 emit_addimm(HOST_CCREG, cinfo[i-1].ccadj + CLOCK_ADJUST(1), HOST_CCREG);
57871462 9148 }
fe807a8a 9149 else
57871462 9150 {
ad49de89 9151 store_regs_bt(branch_regs[i-2].regmap,branch_regs[i-2].dirty,start+i*4);
57871462 9152 assert(branch_regs[i-2].regmap[HOST_CCREG]==CCREG);
9153 }
643aeae3 9154 add_to_linker(out,start+i*4,0);
57871462 9155 emit_jmp(0);
9156 }
9157 }
9158 else
9159 {
9160 assert(i>0);
fe807a8a 9161 assert(!dops[i-1].is_jump);
ad49de89 9162 store_regs_bt(regs[i-1].regmap,regs[i-1].dirty,start+i*4);
57871462 9163 if(regs[i-1].regmap[HOST_CCREG]!=CCREG)
9164 emit_loadreg(CCREG,HOST_CCREG);
277718fa 9165 emit_addimm(HOST_CCREG, cinfo[i-1].ccadj + CLOCK_ADJUST(1), HOST_CCREG);
643aeae3 9166 add_to_linker(out,start+i*4,0);
57871462 9167 emit_jmp(0);
9168 }
9169
57871462 9170 // Stubs
a5cd72d0 9171 for(i = 0; i < stubcount; i++)
57871462 9172 {
b14b6a8f 9173 switch(stubs[i].type)
57871462 9174 {
9175 case LOADB_STUB:
9176 case LOADH_STUB:
9177 case LOADW_STUB:
57871462 9178 case LOADBU_STUB:
9179 case LOADHU_STUB:
9180 do_readstub(i);break;
9181 case STOREB_STUB:
9182 case STOREH_STUB:
9183 case STOREW_STUB:
57871462 9184 do_writestub(i);break;
9185 case CC_STUB:
9186 do_ccstub(i);break;
9187 case INVCODE_STUB:
9188 do_invstub(i);break;
57871462 9189 case STORELR_STUB:
9190 do_unalignedwritestub(i);break;
a5cd72d0 9191 case OVERFLOW_STUB:
9192 do_overflowstub(i); break;
277718fa 9193 case ALIGNMENT_STUB:
9194 do_alignmentstub(i); break;
a5cd72d0 9195 default:
9196 assert(0);
57871462 9197 }
9198 }
9199
9ad4d757 9200 if (instr_addr0_override)
9201 instr_addr[0] = instr_addr0_override;
9202
93c0345b 9203#if 0
9204 /* check for improper expiration */
9205 for (i = 0; i < ARRAY_SIZE(jumps); i++) {
9206 int j;
9207 if (!jumps[i])
9208 continue;
9209 for (j = 0; j < jumps[i]->count; j++)
9210 assert(jumps[i]->e[j].stub < beginning || (u_char *)jumps[i]->e[j].stub > out);
9211 }
9212#endif
9213
57871462 9214 /* Pass 9 - Linker */
9215 for(i=0;i<linkcount;i++)
9216 {
643aeae3 9217 assem_debug("%p -> %8x\n",link_addr[i].addr,link_addr[i].target);
57871462 9218 literal_pool(64);
104df9d3 9219 if (!link_addr[i].internal)
57871462 9220 {
643aeae3 9221 void *stub = out;
9222 void *addr = check_addr(link_addr[i].target);
9223 emit_extjump(link_addr[i].addr, link_addr[i].target);
9224 if (addr) {
9225 set_jump_target(link_addr[i].addr, addr);
104df9d3 9226 ndrc_add_jump_out(link_addr[i].target,stub);
57871462 9227 }
643aeae3 9228 else
9229 set_jump_target(link_addr[i].addr, stub);
57871462 9230 }
9231 else
9232 {
9233 // Internal branch
643aeae3 9234 int target=(link_addr[i].target-start)>>2;
57871462 9235 assert(target>=0&&target<slen);
9236 assert(instr_addr[target]);
9237 //#ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
643aeae3 9238 //set_jump_target_fillslot(link_addr[i].addr,instr_addr[target],link_addr[i].ext>>1);
57871462 9239 //#else
643aeae3 9240 set_jump_target(link_addr[i].addr, instr_addr[target]);
57871462 9241 //#endif
9242 }
9243 }
3d680478 9244
9245 u_int source_len = slen*4;
cf95b4f0 9246 if (dops[slen-1].itype == INTCALL && source_len > 4)
3d680478 9247 // no need to treat the last instruction as compiled
9248 // as interpreter fully handles it
9249 source_len -= 4;
9250
9251 if ((u_char *)copy + source_len > (u_char *)shadow + sizeof(shadow))
9252 copy = shadow;
9253
57871462 9254 // External Branch Targets (jump_in)
104df9d3 9255 int jump_in_count = 1;
9256 assert(instr_addr[0]);
9257 for (i = 1; i < slen; i++)
9258 {
9259 if (dops[i].bt && instr_addr[i])
9260 jump_in_count++;
9261 }
9262
9263 struct block_info *block =
9264 new_block_info(start, slen * 4, source, copy, beginning, jump_in_count);
9265 block->reg_sv_flags = state_rflags;
9266
9267 int jump_in_i = 0;
9268 for (i = 0; i < slen; i++)
57871462 9269 {
104df9d3 9270 if ((i == 0 || dops[i].bt) && instr_addr[i])
57871462 9271 {
104df9d3 9272 assem_debug("%p (%d) <- %8x\n", instr_addr[i], i, start + i*4);
9273 u_int vaddr = start + i*4;
9274
9275 literal_pool(256);
9276 void *entry = out;
9277 load_regs_entry(i);
9278 if (entry == out)
9279 entry = instr_addr[i];
9280 else
9281 emit_jmp(instr_addr[i]);
9282
9283 block->jump_in[jump_in_i].vaddr = vaddr;
9284 block->jump_in[jump_in_i].addr = entry;
9285 jump_in_i++;
57871462 9286 }
9287 }
104df9d3 9288 assert(jump_in_i == jump_in_count);
9289 hash_table_add(block->jump_in[0].vaddr, block->jump_in[0].addr);
57871462 9290 // Write out the literal pool if necessary
9291 literal_pool(0);
9292 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
9293 // Align code
9294 if(((u_int)out)&7) emit_addnop(13);
9295 #endif
01d26796 9296 assert(out - (u_char *)beginning < MAX_OUTPUT_BLOCK_SIZE);
643aeae3 9297 //printf("shadow buffer: %p-%p\n",copy,(u_char *)copy+slen*4);
3d680478 9298 memcpy(copy, source, source_len);
9299 copy += source_len;
9f51b4b9 9300
d148d265 9301 end_block(beginning);
9f51b4b9 9302
57871462 9303 // If we're within 256K of the end of the buffer,
9304 // start over from the beginning. (Is 256K enough?)
2a014d73 9305 if (out > ndrc->translation_cache + sizeof(ndrc->translation_cache) - MAX_OUTPUT_BLOCK_SIZE)
9306 out = ndrc->translation_cache;
9f51b4b9 9307
57871462 9308 // Trap writes to any of the pages we compiled
104df9d3 9309 mark_invalid_code(start, slen*4, 0);
9f51b4b9 9310
57871462 9311 /* Pass 10 - Free memory by expiring oldest blocks */
9f51b4b9 9312
4149788d 9313 pass10_expire_blocks();
9314
37387d8b 9315#ifdef ASSEM_PRINT
9316 fflush(stdout);
9317#endif
ece032e6 9318 stat_inc(stat_bc_direct);
57871462 9319 return 0;
9320}
b9b61529 9321
9322// vim:shiftwidth=2:expandtab
ARM optimized PCSX fork