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drc: some more libnx support
[pcsx_rearmed.git] / libpcsxcore / new_dynarec / new_dynarec.c
CommitLineData
57871462 1/* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
2 * Mupen64plus - new_dynarec.c *
20d507ba 3 * Copyright (C) 2009-2011 Ari64 *
57871462 4 * *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
9 * *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
14 * *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. *
19 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */
20
21#include <stdlib.h>
22#include <stdint.h> //include for uint64_t
23#include <assert.h>
d848b60a 24#include <errno.h>
4600ba03 25#include <sys/mman.h>
d148d265 26#ifdef __MACH__
27#include <libkern/OSCacheControl.h>
28#endif
1e212a25 29#ifdef _3DS
30#include <3ds_utils.h>
31#endif
3039c914 32#ifdef HAVE_LIBNX
33#include <switch.h>
34static Jit g_jit;
35#endif
57871462 36
d148d265 37#include "new_dynarec_config.h"
3968e69e 38#include "../psxhle.h"
39#include "../psxinterpreter.h"
81dbbf4c 40#include "../gte.h"
41#include "emu_if.h" // emulator interface
cdc2da64 42#include "arm_features.h"
57871462 43
d9e2b173 44#ifdef __clang__
45#define noinline __attribute__((noinline))
46#else
d1e4ebd9 47#define noinline __attribute__((noinline,noclone))
d9e2b173 48#endif
b14b6a8f 49#ifndef ARRAY_SIZE
50#define ARRAY_SIZE(x) (sizeof(x) / sizeof(x[0]))
51#endif
e3c6bdb5 52#ifndef min
53#define min(a, b) ((b) < (a) ? (b) : (a))
54#endif
32631e6a 55#ifndef max
56#define max(a, b) ((b) > (a) ? (b) : (a))
57#endif
b14b6a8f 58
4600ba03 59//#define DISASM
32631e6a 60//#define ASSEM_PRINT
ece032e6 61//#define STAT_PRINT
32631e6a 62
63#ifdef ASSEM_PRINT
64#define assem_debug printf
65#else
4600ba03 66#define assem_debug(...)
32631e6a 67#endif
68//#define inv_debug printf
4600ba03 69#define inv_debug(...)
57871462 70
71#ifdef __i386__
72#include "assem_x86.h"
73#endif
74#ifdef __x86_64__
75#include "assem_x64.h"
76#endif
77#ifdef __arm__
78#include "assem_arm.h"
79#endif
be516ebe 80#ifdef __aarch64__
81#include "assem_arm64.h"
82#endif
57871462 83
81dbbf4c 84#define RAM_SIZE 0x200000
57871462 85#define MAXBLOCK 4096
86#define MAX_OUTPUT_BLOCK_SIZE 262144
93c0345b 87#define EXPIRITY_OFFSET (MAX_OUTPUT_BLOCK_SIZE * 2)
88#define PAGE_COUNT 1024
2573466a 89
882a08fc 90#if defined(HAVE_CONDITIONAL_CALL) && !defined(DESTRUCTIVE_SHIFT)
91#define INVALIDATE_USE_COND_CALL
92#endif
93
66ea165f 94#ifdef VITA
95// apparently Vita has a 16MB limit, so either we cut tc in half,
96// or use this hack (it's a hack because tc size was designed to be power-of-2)
97#define TC_REDUCE_BYTES 4096
98#else
99#define TC_REDUCE_BYTES 0
100#endif
101
d9e2b173 102struct ndrc_tramp
103{
104 struct tramp_insns ops[2048 / sizeof(struct tramp_insns)];
105 const void *f[2048 / sizeof(void *)];
106};
107
2a014d73 108struct ndrc_mem
109{
66ea165f 110 u_char translation_cache[(1 << TARGET_SIZE_2) - TC_REDUCE_BYTES];
d9e2b173 111 struct ndrc_tramp tramp;
2a014d73 112};
113
114#ifdef BASE_ADDR_DYNAMIC
115static struct ndrc_mem *ndrc;
116#else
117static struct ndrc_mem ndrc_ __attribute__((aligned(4096)));
118static struct ndrc_mem *ndrc = &ndrc_;
119#endif
d9e2b173 120#ifdef TC_WRITE_OFFSET
3039c914 121# ifdef __GLIBC__
122# include <sys/types.h>
123# include <sys/stat.h>
124# include <fcntl.h>
125# include <unistd.h>
126# endif
127static long ndrc_write_ofs;
d9e2b173 128#define NDRC_WRITE_OFFSET(x) (void *)((char *)(x) + ndrc_write_ofs)
3039c914 129#else
d9e2b173 130#define NDRC_WRITE_OFFSET(x) (x)
3039c914 131#endif
2a014d73 132
b14b6a8f 133// stubs
134enum stub_type {
135 CC_STUB = 1,
136 FP_STUB = 2,
137 LOADB_STUB = 3,
138 LOADH_STUB = 4,
139 LOADW_STUB = 5,
140 LOADD_STUB = 6,
141 LOADBU_STUB = 7,
142 LOADHU_STUB = 8,
143 STOREB_STUB = 9,
144 STOREH_STUB = 10,
145 STOREW_STUB = 11,
146 STORED_STUB = 12,
147 STORELR_STUB = 13,
148 INVCODE_STUB = 14,
149};
150
6cc8d23c 151// regmap_pre[i] - regs before [i] insn starts; dirty things here that
152// don't match .regmap will be written back
153// [i].regmap_entry - regs that must be set up if someone jumps here
154// [i].regmap - regs [i] insn will read/(over)write
2acc46cd 155// branch_regs[i].* - same as above but for branches, takes delay slot into account
57871462 156struct regstat
157{
6cc8d23c 158 signed char regmap_entry[HOST_REGS];
57871462 159 signed char regmap[HOST_REGS];
57871462 160 uint64_t wasdirty;
161 uint64_t dirty;
162 uint64_t u;
24058131 163 u_int wasconst; // before; for example 'lw r2, (r2)' wasconst is true
164 u_int isconst; // ... but isconst is false when r2 is known
8575a877 165 u_int loadedconst; // host regs that have constants loaded
166 u_int waswritten; // MIPS regs that were used as store base before
57871462 167};
168
df4dc2b1 169struct ht_entry
170{
171 u_int vaddr[2];
172 void *tcaddr[2];
173};
174
b14b6a8f 175struct code_stub
176{
177 enum stub_type type;
178 void *addr;
179 void *retaddr;
180 u_int a;
181 uintptr_t b;
182 uintptr_t c;
183 u_int d;
184 u_int e;
185};
186
643aeae3 187struct link_entry
188{
189 void *addr;
190 u_int target;
104df9d3 191 u_int internal;
192};
193
194struct block_info
195{
196 struct block_info *next;
197 const void *source;
198 const void *copy;
199 u_int start; // vaddr of the block start
200 u_int len; // of the whole block source
201 u_int tc_offs;
202 //u_int tc_len;
203 u_int reg_sv_flags;
3280e616 204 u_char is_dirty;
205 u_char inv_near_misses;
104df9d3 206 u_short jump_in_cnt;
207 struct {
208 u_int vaddr;
209 void *addr;
210 } jump_in[0];
643aeae3 211};
212
b7ad2f2c 213struct jump_info
214{
215 int alloc;
216 int count;
217 struct {
218 u_int target_vaddr;
219 void *stub;
220 } e[0];
221};
222
cf95b4f0 223static struct decoded_insn
224{
225 u_char itype;
226 u_char opcode;
227 u_char opcode2;
228 u_char rs1;
229 u_char rs2;
230 u_char rt1;
231 u_char rt2;
53dc27f6 232 u_char use_lt1:1;
cf95b4f0 233 u_char bt:1;
cf95b4f0 234 u_char ooo:1;
235 u_char is_ds:1;
fe807a8a 236 u_char is_jump:1;
237 u_char is_ujump:1;
37387d8b 238 u_char is_load:1;
239 u_char is_store:1;
cf95b4f0 240} dops[MAXBLOCK];
241
398d6924 242 static u_char *out;
104df9d3 243 static struct ht_entry hash_table[65536];
93c0345b 244 static struct block_info *blocks[PAGE_COUNT];
b7ad2f2c 245 static struct jump_info *jumps[PAGE_COUNT];
e2b5e7aa 246 static u_int start;
247 static u_int *source;
bedfea38 248 static uint64_t gte_rs[MAXBLOCK]; // gte: 32 data and 32 ctl regs
249 static uint64_t gte_rt[MAXBLOCK];
250 static uint64_t gte_unneeded[MAXBLOCK];
ffb0b9e0 251 static u_int smrv[32]; // speculated MIPS register values
252 static u_int smrv_strong; // mask or regs that are likely to have correct values
253 static u_int smrv_weak; // same, but somewhat less likely
254 static u_int smrv_strong_next; // same, but after current insn executes
255 static u_int smrv_weak_next;
e2b5e7aa 256 static int imm[MAXBLOCK];
257 static u_int ba[MAXBLOCK];
e2b5e7aa 258 static uint64_t unneeded_reg[MAXBLOCK];
e2b5e7aa 259 static uint64_t branch_unneeded_reg[MAXBLOCK];
6cc8d23c 260 // see 'struct regstat' for a description
2330734f 261 static signed char regmap_pre[MAXBLOCK][HOST_REGS];
40fca85b 262 // contains 'real' consts at [i] insn, but may differ from what's actually
263 // loaded in host reg as 'final' value is always loaded, see get_final_value()
264 static uint32_t current_constmap[HOST_REGS];
265 static uint32_t constmap[MAXBLOCK][HOST_REGS];
956f3129 266 static struct regstat regs[MAXBLOCK];
267 static struct regstat branch_regs[MAXBLOCK];
e2b5e7aa 268 static signed char minimum_free_regs[MAXBLOCK];
e2b5e7aa 269 static int ccadj[MAXBLOCK];
270 static int slen;
df4dc2b1 271 static void *instr_addr[MAXBLOCK];
643aeae3 272 static struct link_entry link_addr[MAXBLOCK];
e2b5e7aa 273 static int linkcount;
b14b6a8f 274 static struct code_stub stubs[MAXBLOCK*3];
e2b5e7aa 275 static int stubcount;
276 static u_int literals[1024][2];
277 static int literalcount;
278 static int is_delayslot;
e2b5e7aa 279 static char shadow[1048576] __attribute__((aligned(16)));
280 static void *copy;
93c0345b 281 static u_int expirep;
e2b5e7aa 282 static u_int stop_after_jal;
7f94b097 283 static u_int f1_hack;
ece032e6 284#ifdef STAT_PRINT
285 static int stat_bc_direct;
286 static int stat_bc_pre;
287 static int stat_bc_restore;
104df9d3 288 static int stat_ht_lookups;
ece032e6 289 static int stat_jump_in_lookups;
290 static int stat_restore_tries;
291 static int stat_restore_compares;
292 static int stat_inv_addr_calls;
293 static int stat_inv_hits;
104df9d3 294 static int stat_blocks;
295 static int stat_links;
ece032e6 296 #define stat_inc(s) s++
104df9d3 297 #define stat_dec(s) s--
298 #define stat_clear(s) s = 0
ece032e6 299#else
300 #define stat_inc(s)
104df9d3 301 #define stat_dec(s)
302 #define stat_clear(s)
ece032e6 303#endif
e2b5e7aa 304
305 int new_dynarec_hacks;
d62c125a 306 int new_dynarec_hacks_pergame;
32631e6a 307 int new_dynarec_hacks_old;
e2b5e7aa 308 int new_dynarec_did_compile;
687b4580 309
d62c125a 310 #define HACK_ENABLED(x) ((new_dynarec_hacks | new_dynarec_hacks_pergame) & (x))
311
687b4580 312 extern int cycle_count; // ... until end of the timeslice, counts -N -> 0
313 extern int last_count; // last absolute target, often = next_interupt
314 extern int pcaddr;
315 extern int pending_exception;
316 extern int branch_target;
37387d8b 317 extern uintptr_t ram_offset;
d1e4ebd9 318 extern uintptr_t mini_ht[32][2];
57871462 319
320 /* registers that may be allocated */
321 /* 1-31 gpr */
7c3a5182 322#define LOREG 32 // lo
323#define HIREG 33 // hi
00fa9369 324//#define FSREG 34 // FPU status (FCSR)
57871462 325#define CSREG 35 // Coprocessor status
326#define CCREG 36 // Cycle count
327#define INVCP 37 // Pointer to invalid_code
1edfcc68 328//#define MMREG 38 // Pointer to memory_map
37387d8b 329#define ROREG 39 // ram offset (if rdram!=0x80000000)
619e5ded 330#define TEMPREG 40
331#define FTEMP 40 // FPU temporary register
332#define PTEMP 41 // Prefetch temporary register
1edfcc68 333//#define TLREG 42 // TLB mapping offset
619e5ded 334#define RHASH 43 // Return address hash
335#define RHTBL 44 // Return address hash table address
336#define RTEMP 45 // JR/JALR address register
337#define MAXREG 45
338#define AGEN1 46 // Address generation temporary register
1edfcc68 339//#define AGEN2 47 // Address generation temporary register
340//#define MGEN1 48 // Maptable address generation temporary register
341//#define MGEN2 49 // Maptable address generation temporary register
619e5ded 342#define BTREG 50 // Branch target temporary register
57871462 343
344 /* instruction types */
345#define NOP 0 // No operation
346#define LOAD 1 // Load
347#define STORE 2 // Store
348#define LOADLR 3 // Unaligned load
349#define STORELR 4 // Unaligned store
9f51b4b9 350#define MOV 5 // Move
57871462 351#define ALU 6 // Arithmetic/logic
352#define MULTDIV 7 // Multiply/divide
353#define SHIFT 8 // Shift by register
354#define SHIFTIMM 9// Shift by immediate
355#define IMM16 10 // 16-bit immediate
356#define RJUMP 11 // Unconditional jump to register
357#define UJUMP 12 // Unconditional jump
358#define CJUMP 13 // Conditional branch (BEQ/BNE/BGTZ/BLEZ)
359#define SJUMP 14 // Conditional branch (regimm format)
360#define COP0 15 // Coprocessor 0
361#define COP1 16 // Coprocessor 1
362#define C1LS 17 // Coprocessor 1 load/store
ad49de89 363//#define FJUMP 18 // Conditional branch (floating point)
00fa9369 364//#define FLOAT 19 // Floating point unit
365//#define FCONV 20 // Convert integer to float
366//#define FCOMP 21 // Floating point compare (sets FSREG)
d1150cd6 367#define SYSCALL 22// SYSCALL,BREAK
57871462 368#define OTHER 23 // Other
4bdc30ab 369//#define SPAN 24 // Branch/delay slot spans 2 pages
57871462 370#define NI 25 // Not implemented
7139f3c8 371#define HLECALL 26// PCSX fake opcodes for HLE
b9b61529 372#define COP2 27 // Coprocessor 2 move
373#define C2LS 28 // Coprocessor 2 load/store
374#define C2OP 29 // Coprocessor 2 operation
1e973cb0 375#define INTCALL 30// Call interpreter to handle rare corner cases
57871462 376
57871462 377 /* branch codes */
378#define TAKEN 1
379#define NOTTAKEN 2
380#define NULLDS 3
381
7c3a5182 382#define DJT_1 (void *)1l // no function, just a label in assem_debug log
383#define DJT_2 (void *)2l
384
57871462 385// asm linkage
57871462 386void dyna_linker();
57871462 387void cc_interrupt();
388void fp_exception();
389void fp_exception_ds();
d1150cd6 390void jump_syscall (u_int u0, u_int u1, u_int pc);
391void jump_syscall_ds(u_int u0, u_int u1, u_int pc);
392void jump_break (u_int u0, u_int u1, u_int pc);
393void jump_break_ds(u_int u0, u_int u1, u_int pc);
3968e69e 394void jump_to_new_pc();
81dbbf4c 395void call_gteStall();
7139f3c8 396void new_dyna_leave();
57871462 397
104df9d3 398void *ndrc_get_addr_ht_param(u_int vaddr, int can_compile);
399void *ndrc_get_addr_ht(u_int vaddr);
400void ndrc_invalidate_addr(u_int addr);
401void ndrc_add_jump_out(u_int vaddr, void *src);
402
403static int new_recompile_block(u_int addr);
404static void invalidate_block(struct block_info *block);
398d6924 405
57871462 406// Needed by assembler
2330734f 407static void wb_register(signed char r, const signed char regmap[], uint64_t dirty);
408static void wb_dirtys(const signed char i_regmap[], uint64_t i_dirty);
409static void wb_needed_dirtys(const signed char i_regmap[], uint64_t i_dirty, int addr);
410static void load_all_regs(const signed char i_regmap[]);
411static void load_needed_regs(const signed char i_regmap[], const signed char next_regmap[]);
e2b5e7aa 412static void load_regs_entry(int t);
2330734f 413static void load_all_consts(const signed char regmap[], u_int dirty, int i);
81dbbf4c 414static u_int get_host_reglist(const signed char *regmap);
e2b5e7aa 415
e2b5e7aa 416static int get_final_value(int hr, int i, int *value);
b14b6a8f 417static void add_stub(enum stub_type type, void *addr, void *retaddr,
418 u_int a, uintptr_t b, uintptr_t c, u_int d, u_int e);
419static void add_stub_r(enum stub_type type, void *addr, void *retaddr,
81dbbf4c 420 int i, int addr_reg, const struct regstat *i_regs, int ccadj, u_int reglist);
643aeae3 421static void add_to_linker(void *addr, u_int target, int ext);
37387d8b 422static void *emit_fastpath_cmp_jump(int i, const struct regstat *i_regs,
423 int addr, int *offset_reg, int *addr_reg_override);
687b4580 424static void *get_direct_memhandler(void *table, u_int addr,
425 enum stub_type type, uintptr_t *addr_host);
32631e6a 426static void cop2_do_stall_check(u_int op, int i, const struct regstat *i_regs, u_int reglist);
687b4580 427static void pass_args(int a0, int a1);
2a014d73 428static void emit_far_jump(const void *f);
429static void emit_far_call(const void *f);
57871462 430
9c67c98f 431#ifdef VITA
432#include <psp2/kernel/sysmem.h>
433static int sceBlock;
434// note: this interacts with RetroArch's Vita bootstrap code: bootstrap/vita/sbrk.c
435extern int getVMBlock();
436int _newlib_vm_size_user = sizeof(*ndrc);
437#endif
438
d148d265 439static void mprotect_w_x(void *start, void *end, int is_x)
440{
441#ifdef NO_WRITE_EXEC
1e212a25 442 #if defined(VITA)
443 // *Open* enables write on all memory that was
444 // allocated by sceKernelAllocMemBlockForVM()?
445 if (is_x)
446 sceKernelCloseVMDomain();
447 else
448 sceKernelOpenVMDomain();
3039c914 449 #elif defined(HAVE_LIBNX)
450 Result rc;
d9e2b173 451 // check to avoid the full flush in jitTransitionToExecutable()
452 if (g_jit.type != JitType_CodeMemory) {
453 if (is_x)
454 rc = jitTransitionToExecutable(&g_jit);
455 else
456 rc = jitTransitionToWritable(&g_jit);
457 if (R_FAILED(rc))
458 ;//SysPrintf("jitTransition %d %08x\n", is_x, rc);
459 }
460 #elif defined(TC_WRITE_OFFSET)
3039c914 461 // separated rx and rw areas are always available
1e212a25 462 #else
d148d265 463 u_long mstart = (u_long)start & ~4095ul;
464 u_long mend = (u_long)end;
465 if (mprotect((void *)mstart, mend - mstart,
466 PROT_READ | (is_x ? PROT_EXEC : PROT_WRITE)) != 0)
467 SysPrintf("mprotect(%c) failed: %s\n", is_x ? 'x' : 'w', strerror(errno));
1e212a25 468 #endif
d148d265 469#endif
470}
471
d9e2b173 472static void start_tcache_write(void *start, void *end)
d148d265 473{
474 mprotect_w_x(start, end, 0);
475}
476
477static void end_tcache_write(void *start, void *end)
478{
919981d0 479#if defined(__arm__) || defined(__aarch64__)
d148d265 480 size_t len = (char *)end - (char *)start;
481 #if defined(__BLACKBERRY_QNX__)
482 msync(start, len, MS_SYNC | MS_CACHE_ONLY | MS_INVALIDATE_ICACHE);
483 #elif defined(__MACH__)
484 sys_cache_control(kCacheFunctionPrepareForExecution, start, len);
485 #elif defined(VITA)
1e212a25 486 sceKernelSyncVMDomain(sceBlock, start, len);
487 #elif defined(_3DS)
488 ctr_flush_invalidate_cache();
3039c914 489 #elif defined(HAVE_LIBNX)
d9e2b173 490 if (g_jit.type == JitType_CodeMemory) {
491 armDCacheClean(start, len);
492 armICacheInvalidate((char *)start - ndrc_write_ofs, len);
493 }
919981d0 494 #elif defined(__aarch64__)
495 // as of 2021, __clear_cache() is still broken on arm64
496 // so here is a custom one :(
497 clear_cache_arm64(start, end);
d148d265 498 #else
499 __clear_cache(start, end);
500 #endif
501 (void)len;
502#endif
503
504 mprotect_w_x(start, end, 1);
505}
506
507static void *start_block(void)
508{
509 u_char *end = out + MAX_OUTPUT_BLOCK_SIZE;
2a014d73 510 if (end > ndrc->translation_cache + sizeof(ndrc->translation_cache))
511 end = ndrc->translation_cache + sizeof(ndrc->translation_cache);
d9e2b173 512 start_tcache_write(NDRC_WRITE_OFFSET(out), NDRC_WRITE_OFFSET(end));
d148d265 513 return out;
514}
515
516static void end_block(void *start)
517{
d9e2b173 518 end_tcache_write(NDRC_WRITE_OFFSET(start), NDRC_WRITE_OFFSET(out));
d148d265 519}
520
af700b41 521#ifdef NDRC_CACHE_FLUSH_ALL
522
523static int needs_clear_cache;
524
525static void mark_clear_cache(void *target)
526{
527 if (!needs_clear_cache) {
d9e2b173 528 start_tcache_write(NDRC_WRITE_OFFSET(ndrc), NDRC_WRITE_OFFSET(ndrc + 1));
af700b41 529 needs_clear_cache = 1;
530 }
531}
532
533static void do_clear_cache(void)
534{
535 if (needs_clear_cache) {
d9e2b173 536 end_tcache_write(NDRC_WRITE_OFFSET(ndrc), NDRC_WRITE_OFFSET(ndrc + 1));
af700b41 537 needs_clear_cache = 0;
538 }
539}
540
541#else
542
919981d0 543// also takes care of w^x mappings when patching code
544static u_int needs_clear_cache[1<<(TARGET_SIZE_2-17)];
545
546static void mark_clear_cache(void *target)
547{
548 uintptr_t offset = (u_char *)target - ndrc->translation_cache;
549 u_int mask = 1u << ((offset >> 12) & 31);
550 if (!(needs_clear_cache[offset >> 17] & mask)) {
d9e2b173 551 char *start = (char *)NDRC_WRITE_OFFSET((uintptr_t)target & ~4095l);
919981d0 552 start_tcache_write(start, start + 4095);
553 needs_clear_cache[offset >> 17] |= mask;
554 }
555}
556
557// Clearing the cache is rather slow on ARM Linux, so mark the areas
558// that need to be cleared, and then only clear these areas once.
559static void do_clear_cache(void)
560{
561 int i, j;
562 for (i = 0; i < (1<<(TARGET_SIZE_2-17)); i++)
563 {
564 u_int bitmap = needs_clear_cache[i];
565 if (!bitmap)
566 continue;
567 for (j = 0; j < 32; j++)
568 {
569 u_char *start, *end;
93c0345b 570 if (!(bitmap & (1u << j)))
919981d0 571 continue;
572
573 start = ndrc->translation_cache + i*131072 + j*4096;
574 end = start + 4095;
575 for (j++; j < 32; j++) {
93c0345b 576 if (!(bitmap & (1u << j)))
919981d0 577 break;
578 end += 4096;
579 }
d9e2b173 580 end_tcache_write(NDRC_WRITE_OFFSET(start), NDRC_WRITE_OFFSET(end));
919981d0 581 }
582 needs_clear_cache[i] = 0;
583 }
584}
585
af700b41 586#endif // NDRC_CACHE_FLUSH_ALL
57871462 587
b6e87b2b 588#define NO_CYCLE_PENALTY_THR 12
589
26bd3dad 590int cycle_multiplier = CYCLE_MULT_DEFAULT; // 100 for 1.0
a3203cf4 591int cycle_multiplier_override;
32631e6a 592int cycle_multiplier_old;
24058131 593static int cycle_multiplier_active;
4e9dcd7f 594
595static int CLOCK_ADJUST(int x)
596{
24058131 597 int m = cycle_multiplier_active;
598 int s = (x >> 31) | 1;
a3203cf4 599 return (x * m + s * 50) / 100;
4e9dcd7f 600}
601
4919de1e 602static int ds_writes_rjump_rs(int i)
603{
cf95b4f0 604 return dops[i].rs1 != 0 && (dops[i].rs1 == dops[i+1].rt1 || dops[i].rs1 == dops[i+1].rt2);
4919de1e 605}
606
104df9d3 607// psx addr mirror masking (for invalidation)
608static u_int pmmask(u_int vaddr)
609{
610 vaddr &= ~0xe0000000;
611 if (vaddr < 0x01000000)
612 vaddr &= ~0x00e00000; // RAM mirrors
613 return vaddr;
614}
615
94d23bb9 616static u_int get_page(u_int vaddr)
57871462 617{
104df9d3 618 u_int page = pmmask(vaddr) >> 12;
93c0345b 619 if (page >= PAGE_COUNT / 2)
620 page = PAGE_COUNT / 2 + (page & (PAGE_COUNT / 2 - 1));
94d23bb9 621 return page;
622}
623
104df9d3 624// get a page for looking for a block that has vaddr
625// (needed because the block may start in previous page)
626static u_int get_page_prev(u_int vaddr)
d25604ca 627{
104df9d3 628 assert(MAXBLOCK <= (1 << 12));
629 u_int page = get_page(vaddr);
630 if (page & 511)
631 page--;
632 return page;
d25604ca 633}
94d23bb9 634
df4dc2b1 635static struct ht_entry *hash_table_get(u_int vaddr)
636{
637 return &hash_table[((vaddr>>16)^vaddr)&0xFFFF];
638}
639
104df9d3 640static void hash_table_add(u_int vaddr, void *tcaddr)
df4dc2b1 641{
104df9d3 642 struct ht_entry *ht_bin = hash_table_get(vaddr);
643 assert(tcaddr);
df4dc2b1 644 ht_bin->vaddr[1] = ht_bin->vaddr[0];
645 ht_bin->tcaddr[1] = ht_bin->tcaddr[0];
646 ht_bin->vaddr[0] = vaddr;
647 ht_bin->tcaddr[0] = tcaddr;
648}
649
104df9d3 650static void hash_table_remove(int vaddr)
651{
652 //printf("remove hash: %x\n",vaddr);
653 struct ht_entry *ht_bin = hash_table_get(vaddr);
654 if (ht_bin->vaddr[1] == vaddr) {
655 ht_bin->vaddr[1] = -1;
656 ht_bin->tcaddr[1] = NULL;
657 }
658 if (ht_bin->vaddr[0] == vaddr) {
659 ht_bin->vaddr[0] = ht_bin->vaddr[1];
660 ht_bin->tcaddr[0] = ht_bin->tcaddr[1];
661 ht_bin->vaddr[1] = -1;
662 ht_bin->tcaddr[1] = NULL;
663 }
664}
665
666static void mark_invalid_code(u_int vaddr, u_int len, char invalid)
398d6924 667{
ab4377be 668 u_int vaddr_m = vaddr & 0x1fffffff;
398d6924 669 u_int i, j;
ab4377be 670 for (i = vaddr_m & ~0xfff; i < vaddr_m + len; i += 0x1000) {
398d6924 671 // ram mirrors, but should not hurt bios
672 for (j = 0; j < 0x800000; j += 0x200000) {
673 invalid_code[(i|j) >> 12] =
674 invalid_code[(i|j|0x80000000u) >> 12] =
104df9d3 675 invalid_code[(i|j|0xa0000000u) >> 12] = invalid;
398d6924 676 }
677 }
882a08fc 678 if (!invalid && vaddr + len > inv_code_start && vaddr <= inv_code_end)
104df9d3 679 inv_code_start = inv_code_end = ~0;
398d6924 680}
681
93c0345b 682static int doesnt_expire_soon(u_char *tcaddr)
df4dc2b1 683{
93c0345b 684 u_int diff = (u_int)(tcaddr - out) & ((1u << TARGET_SIZE_2) - 1u);
685 return diff > EXPIRITY_OFFSET + MAX_OUTPUT_BLOCK_SIZE;
df4dc2b1 686}
687
104df9d3 688static void *try_restore_block(u_int vaddr, u_int start_page, u_int end_page)
398d6924 689{
104df9d3 690 void *found_clean = NULL;
691 u_int i, page;
398d6924 692
ece032e6 693 stat_inc(stat_restore_tries);
104df9d3 694 for (page = start_page; page <= end_page; page++) {
695 struct block_info *block;
696 for (block = blocks[page]; block != NULL; block = block->next) {
697 if (vaddr < block->start)
698 break;
699 if (!block->is_dirty || vaddr >= block->start + block->len)
700 continue;
701 for (i = 0; i < block->jump_in_cnt; i++)
702 if (block->jump_in[i].vaddr == vaddr)
703 break;
704 if (i == block->jump_in_cnt)
705 continue;
706 assert(block->source && block->copy);
707 stat_inc(stat_restore_compares);
708 if (memcmp(block->source, block->copy, block->len))
709 continue;
398d6924 710
3280e616 711 block->is_dirty = block->inv_near_misses = 0;
104df9d3 712 found_clean = block->jump_in[i].addr;
713 hash_table_add(vaddr, found_clean);
714 mark_invalid_code(block->start, block->len, 0);
715 stat_inc(stat_bc_restore);
716 inv_debug("INV: restored %08x %p (%d)\n", vaddr, found_clean, block->jump_in_cnt);
717 return found_clean;
398d6924 718 }
398d6924 719 }
104df9d3 720 return NULL;
398d6924 721}
722
94d23bb9 723// Get address from virtual address
724// This is called from the recompiled JR/JALR instructions
104df9d3 725static void noinline *get_addr(u_int vaddr, int can_compile)
94d23bb9 726{
104df9d3 727 u_int start_page = get_page_prev(vaddr);
728 u_int i, page, end_page = get_page(vaddr);
729 void *found_clean = NULL;
398d6924 730
ece032e6 731 stat_inc(stat_jump_in_lookups);
104df9d3 732 for (page = start_page; page <= end_page; page++) {
733 const struct block_info *block;
734 for (block = blocks[page]; block != NULL; block = block->next) {
735 if (vaddr < block->start)
736 break;
737 if (block->is_dirty || vaddr >= block->start + block->len)
738 continue;
739 for (i = 0; i < block->jump_in_cnt; i++)
740 if (block->jump_in[i].vaddr == vaddr)
741 break;
742 if (i == block->jump_in_cnt)
743 continue;
744 found_clean = block->jump_in[i].addr;
745 hash_table_add(vaddr, found_clean);
746 return found_clean;
57871462 747 }
57871462 748 }
104df9d3 749 found_clean = try_restore_block(vaddr, start_page, end_page);
750 if (found_clean)
751 return found_clean;
752
753 if (!can_compile)
754 return NULL;
398d6924 755
756 int r = new_recompile_block(vaddr);
757 if (r == 0)
104df9d3 758 return ndrc_get_addr_ht(vaddr);
df4dc2b1 759
b4ab351d 760 // generate an address error
57871462 761 Status|=2;
b4ab351d 762 Cause=(vaddr<<31)|(4<<2);
57871462 763 EPC=(vaddr&1)?vaddr-5:vaddr;
764 BadVAddr=(vaddr&~1);
104df9d3 765 return ndrc_get_addr_ht(0x80000080);
57871462 766}
104df9d3 767
57871462 768// Look up address in hash table first
104df9d3 769void *ndrc_get_addr_ht_param(u_int vaddr, int can_compile)
57871462 770{
df4dc2b1 771 const struct ht_entry *ht_bin = hash_table_get(vaddr);
104df9d3 772 stat_inc(stat_ht_lookups);
df4dc2b1 773 if (ht_bin->vaddr[0] == vaddr) return ht_bin->tcaddr[0];
774 if (ht_bin->vaddr[1] == vaddr) return ht_bin->tcaddr[1];
104df9d3 775 return get_addr(vaddr, can_compile);
776}
777
778void *ndrc_get_addr_ht(u_int vaddr)
779{
780 return ndrc_get_addr_ht_param(vaddr, 1);
57871462 781}
782
6cc8d23c 783static void clear_all_regs(signed char regmap[])
57871462 784{
6cc8d23c 785 memset(regmap, -1, sizeof(regmap[0]) * HOST_REGS);
57871462 786}
787
53358c1d 788// get_reg: get allocated host reg from mips reg
789// returns -1 if no such mips reg was allocated
cdc2da64 790#if defined(__arm__) && defined(HAVE_ARMV6) && HOST_REGS == 13 && EXCLUDE_REG == 11
791
792extern signed char get_reg(const signed char regmap[], signed char r);
793
794#else
795
9de8a0c3 796static signed char get_reg(const signed char regmap[], signed char r)
57871462 797{
798 int hr;
9de8a0c3 799 for (hr = 0; hr < HOST_REGS; hr++) {
800 if (hr == EXCLUDE_REG)
801 continue;
802 if (regmap[hr] == r)
803 return hr;
804 }
805 return -1;
806}
807
cdc2da64 808#endif
809
53358c1d 810// get reg as mask bit (1 << hr)
811static u_int get_regm(const signed char regmap[], signed char r)
812{
813 return (1u << (get_reg(regmap, r) & 31)) & ~(1u << 31);
814}
815
9de8a0c3 816static signed char get_reg_temp(const signed char regmap[])
817{
818 int hr;
819 for (hr = 0; hr < HOST_REGS; hr++) {
820 if (hr == EXCLUDE_REG)
821 continue;
822 if (regmap[hr] == (signed char)-1)
823 return hr;
824 }
57871462 825 return -1;
826}
827
828// Find a register that is available for two consecutive cycles
d1e4ebd9 829static signed char get_reg2(signed char regmap1[], const signed char regmap2[], int r)
57871462 830{
831 int hr;
832 for (hr=0;hr<HOST_REGS;hr++) if(hr!=EXCLUDE_REG&&regmap1[hr]==r&&regmap2[hr]==r) return hr;
833 return -1;
834}
835
53dc27f6 836// reverse reg map: mips -> host
837#define RRMAP_SIZE 64
838static void make_rregs(const signed char regmap[], signed char rrmap[RRMAP_SIZE],
839 u_int *regs_can_change)
840{
841 u_int r, hr, hr_can_change = 0;
842 memset(rrmap, -1, RRMAP_SIZE);
843 for (hr = 0; hr < HOST_REGS; )
844 {
845 r = regmap[hr];
846 rrmap[r & (RRMAP_SIZE - 1)] = hr;
847 // only add mips $1-$31+$lo, others shifted out
848 hr_can_change |= (uint64_t)1 << (hr + ((r - 1) & 32));
849 hr++;
850 if (hr == EXCLUDE_REG)
851 hr++;
852 }
853 hr_can_change |= 1u << (rrmap[33] & 31);
854 hr_can_change |= 1u << (rrmap[CCREG] & 31);
855 hr_can_change &= ~(1u << 31);
856 *regs_can_change = hr_can_change;
857}
858
859// same as get_reg, but takes rrmap
860static signed char get_rreg(signed char rrmap[RRMAP_SIZE], signed char r)
861{
862 assert(0 <= r && r < RRMAP_SIZE);
863 return rrmap[r];
864}
865
9de8a0c3 866static int count_free_regs(const signed char regmap[])
57871462 867{
868 int count=0;
869 int hr;
870 for(hr=0;hr<HOST_REGS;hr++)
871 {
872 if(hr!=EXCLUDE_REG) {
873 if(regmap[hr]<0) count++;
874 }
875 }
876 return count;
877}
878
9de8a0c3 879static void dirty_reg(struct regstat *cur, signed char reg)
57871462 880{
881 int hr;
9de8a0c3 882 if (!reg) return;
883 hr = get_reg(cur->regmap, reg);
884 if (hr >= 0)
885 cur->dirty |= 1<<hr;
57871462 886}
887
40fca85b 888static void set_const(struct regstat *cur, signed char reg, uint32_t value)
57871462 889{
890 int hr;
9de8a0c3 891 if (!reg) return;
892 hr = get_reg(cur->regmap, reg);
893 if (hr >= 0) {
894 cur->isconst |= 1<<hr;
895 current_constmap[hr] = value;
57871462 896 }
897}
898
40fca85b 899static void clear_const(struct regstat *cur, signed char reg)
57871462 900{
901 int hr;
9de8a0c3 902 if (!reg) return;
903 hr = get_reg(cur->regmap, reg);
904 if (hr >= 0)
905 cur->isconst &= ~(1<<hr);
57871462 906}
907
9de8a0c3 908static int is_const(const struct regstat *cur, signed char reg)
57871462 909{
910 int hr;
9de8a0c3 911 if (reg < 0) return 0;
912 if (!reg) return 1;
913 hr = get_reg(cur->regmap, reg);
914 if (hr >= 0)
915 return (cur->isconst>>hr)&1;
57871462 916 return 0;
917}
40fca85b 918
9de8a0c3 919static uint32_t get_const(const struct regstat *cur, signed char reg)
57871462 920{
921 int hr;
9de8a0c3 922 if (!reg) return 0;
923 hr = get_reg(cur->regmap, reg);
924 if (hr >= 0)
925 return current_constmap[hr];
926
927 SysPrintf("Unknown constant in r%d\n", reg);
7c3a5182 928 abort();
57871462 929}
930
931// Least soon needed registers
932// Look at the next ten instructions and see which registers
933// will be used. Try not to reallocate these.
4149788d 934static void lsn(u_char hsn[], int i, int *preferred_reg)
57871462 935{
936 int j;
937 int b=-1;
938 for(j=0;j<9;j++)
939 {
940 if(i+j>=slen) {
941 j=slen-i-1;
942 break;
943 }
fe807a8a 944 if (dops[i+j].is_ujump)
57871462 945 {
946 // Don't go past an unconditonal jump
947 j++;
948 break;
949 }
950 }
951 for(;j>=0;j--)
952 {
cf95b4f0 953 if(dops[i+j].rs1) hsn[dops[i+j].rs1]=j;
954 if(dops[i+j].rs2) hsn[dops[i+j].rs2]=j;
955 if(dops[i+j].rt1) hsn[dops[i+j].rt1]=j;
956 if(dops[i+j].rt2) hsn[dops[i+j].rt2]=j;
957 if(dops[i+j].itype==STORE || dops[i+j].itype==STORELR) {
57871462 958 // Stores can allocate zero
cf95b4f0 959 hsn[dops[i+j].rs1]=j;
960 hsn[dops[i+j].rs2]=j;
57871462 961 }
37387d8b 962 if (ram_offset && (dops[i+j].is_load || dops[i+j].is_store))
963 hsn[ROREG] = j;
57871462 964 // On some architectures stores need invc_ptr
965 #if defined(HOST_IMM8)
37387d8b 966 if (dops[i+j].is_store)
967 hsn[INVCP] = j;
57871462 968 #endif
cf95b4f0 969 if(i+j>=0&&(dops[i+j].itype==UJUMP||dops[i+j].itype==CJUMP||dops[i+j].itype==SJUMP))
57871462 970 {
971 hsn[CCREG]=j;
972 b=j;
973 }
974 }
975 if(b>=0)
976 {
977 if(ba[i+b]>=start && ba[i+b]<(start+slen*4))
978 {
979 // Follow first branch
980 int t=(ba[i+b]-start)>>2;
981 j=7-b;if(t+j>=slen) j=slen-t-1;
982 for(;j>=0;j--)
983 {
cf95b4f0 984 if(dops[t+j].rs1) if(hsn[dops[t+j].rs1]>j+b+2) hsn[dops[t+j].rs1]=j+b+2;
985 if(dops[t+j].rs2) if(hsn[dops[t+j].rs2]>j+b+2) hsn[dops[t+j].rs2]=j+b+2;
986 //if(dops[t+j].rt1) if(hsn[dops[t+j].rt1]>j+b+2) hsn[dops[t+j].rt1]=j+b+2;
987 //if(dops[t+j].rt2) if(hsn[dops[t+j].rt2]>j+b+2) hsn[dops[t+j].rt2]=j+b+2;
57871462 988 }
989 }
990 // TODO: preferred register based on backward branch
991 }
992 // Delay slot should preferably not overwrite branch conditions or cycle count
fe807a8a 993 if (i > 0 && dops[i-1].is_jump) {
cf95b4f0 994 if(dops[i-1].rs1) if(hsn[dops[i-1].rs1]>1) hsn[dops[i-1].rs1]=1;
995 if(dops[i-1].rs2) if(hsn[dops[i-1].rs2]>1) hsn[dops[i-1].rs2]=1;
57871462 996 hsn[CCREG]=1;
997 // ...or hash tables
998 hsn[RHASH]=1;
999 hsn[RHTBL]=1;
1000 }
1001 // Coprocessor load/store needs FTEMP, even if not declared
37387d8b 1002 if(dops[i].itype==C2LS) {
57871462 1003 hsn[FTEMP]=0;
1004 }
1005 // Load L/R also uses FTEMP as a temporary register
cf95b4f0 1006 if(dops[i].itype==LOADLR) {
57871462 1007 hsn[FTEMP]=0;
1008 }
b7918751 1009 // Also SWL/SWR/SDL/SDR
cf95b4f0 1010 if(dops[i].opcode==0x2a||dops[i].opcode==0x2e||dops[i].opcode==0x2c||dops[i].opcode==0x2d) {
57871462 1011 hsn[FTEMP]=0;
1012 }
57871462 1013 // Don't remove the miniht registers
cf95b4f0 1014 if(dops[i].itype==UJUMP||dops[i].itype==RJUMP)
57871462 1015 {
1016 hsn[RHASH]=0;
1017 hsn[RHTBL]=0;
1018 }
1019}
1020
1021// We only want to allocate registers if we're going to use them again soon
4149788d 1022static int needed_again(int r, int i)
57871462 1023{
1024 int j;
1025 int b=-1;
1026 int rn=10;
9f51b4b9 1027
fe807a8a 1028 if (i > 0 && dops[i-1].is_ujump)
57871462 1029 {
1030 if(ba[i-1]<start || ba[i-1]>start+slen*4-4)
1031 return 0; // Don't need any registers if exiting the block
1032 }
1033 for(j=0;j<9;j++)
1034 {
1035 if(i+j>=slen) {
1036 j=slen-i-1;
1037 break;
1038 }
fe807a8a 1039 if (dops[i+j].is_ujump)
57871462 1040 {
1041 // Don't go past an unconditonal jump
1042 j++;
1043 break;
1044 }
cf95b4f0 1045 if(dops[i+j].itype==SYSCALL||dops[i+j].itype==HLECALL||dops[i+j].itype==INTCALL||((source[i+j]&0xfc00003f)==0x0d))
57871462 1046 {
1047 break;
1048 }
1049 }
1050 for(;j>=1;j--)
1051 {
cf95b4f0 1052 if(dops[i+j].rs1==r) rn=j;
1053 if(dops[i+j].rs2==r) rn=j;
57871462 1054 if((unneeded_reg[i+j]>>r)&1) rn=10;
cf95b4f0 1055 if(i+j>=0&&(dops[i+j].itype==UJUMP||dops[i+j].itype==CJUMP||dops[i+j].itype==SJUMP))
57871462 1056 {
1057 b=j;
1058 }
1059 }
b7217e13 1060 if(rn<10) return 1;
581335b0 1061 (void)b;
57871462 1062 return 0;
1063}
1064
1065// Try to match register allocations at the end of a loop with those
1066// at the beginning
4149788d 1067static int loop_reg(int i, int r, int hr)
57871462 1068{
1069 int j,k;
1070 for(j=0;j<9;j++)
1071 {
1072 if(i+j>=slen) {
1073 j=slen-i-1;
1074 break;
1075 }
fe807a8a 1076 if (dops[i+j].is_ujump)
57871462 1077 {
1078 // Don't go past an unconditonal jump
1079 j++;
1080 break;
1081 }
1082 }
1083 k=0;
1084 if(i>0){
cf95b4f0 1085 if(dops[i-1].itype==UJUMP||dops[i-1].itype==CJUMP||dops[i-1].itype==SJUMP)
57871462 1086 k--;
1087 }
1088 for(;k<j;k++)
1089 {
00fa9369 1090 assert(r < 64);
1091 if((unneeded_reg[i+k]>>r)&1) return hr;
cf95b4f0 1092 if(i+k>=0&&(dops[i+k].itype==UJUMP||dops[i+k].itype==CJUMP||dops[i+k].itype==SJUMP))
57871462 1093 {
1094 if(ba[i+k]>=start && ba[i+k]<(start+i*4))
1095 {
1096 int t=(ba[i+k]-start)>>2;
1097 int reg=get_reg(regs[t].regmap_entry,r);
1098 if(reg>=0) return reg;
1099 //reg=get_reg(regs[t+1].regmap_entry,r);
1100 //if(reg>=0) return reg;
1101 }
1102 }
1103 }
1104 return hr;
1105}
1106
1107
1108// Allocate every register, preserving source/target regs
4149788d 1109static void alloc_all(struct regstat *cur,int i)
57871462 1110{
1111 int hr;
9f51b4b9 1112
57871462 1113 for(hr=0;hr<HOST_REGS;hr++) {
1114 if(hr!=EXCLUDE_REG) {
9de8a0c3 1115 if((cur->regmap[hr]!=dops[i].rs1)&&(cur->regmap[hr]!=dops[i].rs2)&&
1116 (cur->regmap[hr]!=dops[i].rt1)&&(cur->regmap[hr]!=dops[i].rt2))
57871462 1117 {
1118 cur->regmap[hr]=-1;
1119 cur->dirty&=~(1<<hr);
1120 }
1121 // Don't need zeros
9de8a0c3 1122 if(cur->regmap[hr]==0)
57871462 1123 {
1124 cur->regmap[hr]=-1;
1125 cur->dirty&=~(1<<hr);
1126 }
1127 }
1128 }
1129}
1130
d1e4ebd9 1131#ifndef NDEBUG
1132static int host_tempreg_in_use;
1133
1134static void host_tempreg_acquire(void)
1135{
1136 assert(!host_tempreg_in_use);
1137 host_tempreg_in_use = 1;
1138}
1139
1140static void host_tempreg_release(void)
1141{
1142 host_tempreg_in_use = 0;
1143}
1144#else
1145static void host_tempreg_acquire(void) {}
1146static void host_tempreg_release(void) {}
1147#endif
1148
32631e6a 1149#ifdef ASSEM_PRINT
8062d65a 1150extern void gen_interupt();
1151extern void do_insn_cmp();
d1e4ebd9 1152#define FUNCNAME(f) { f, " " #f }
8062d65a 1153static const struct {
d1e4ebd9 1154 void *addr;
8062d65a 1155 const char *name;
1156} function_names[] = {
1157 FUNCNAME(cc_interrupt),
1158 FUNCNAME(gen_interupt),
104df9d3 1159 FUNCNAME(ndrc_get_addr_ht),
8062d65a 1160 FUNCNAME(jump_handler_read8),
1161 FUNCNAME(jump_handler_read16),
1162 FUNCNAME(jump_handler_read32),
1163 FUNCNAME(jump_handler_write8),
1164 FUNCNAME(jump_handler_write16),
1165 FUNCNAME(jump_handler_write32),
104df9d3 1166 FUNCNAME(ndrc_invalidate_addr),
3968e69e 1167 FUNCNAME(jump_to_new_pc),
d1150cd6 1168 FUNCNAME(jump_break),
1169 FUNCNAME(jump_break_ds),
1170 FUNCNAME(jump_syscall),
1171 FUNCNAME(jump_syscall_ds),
81dbbf4c 1172 FUNCNAME(call_gteStall),
8062d65a 1173 FUNCNAME(new_dyna_leave),
1174 FUNCNAME(pcsx_mtc0),
1175 FUNCNAME(pcsx_mtc0_ds),
32631e6a 1176#ifdef DRC_DBG
8062d65a 1177 FUNCNAME(do_insn_cmp),
32631e6a 1178#endif
8062d65a 1179};
1180
d1e4ebd9 1181static const char *func_name(const void *a)
8062d65a 1182{
1183 int i;
1184 for (i = 0; i < sizeof(function_names)/sizeof(function_names[0]); i++)
1185 if (function_names[i].addr == a)
1186 return function_names[i].name;
1187 return "";
1188}
1189#else
1190#define func_name(x) ""
1191#endif
1192
57871462 1193#ifdef __i386__
1194#include "assem_x86.c"
1195#endif
1196#ifdef __x86_64__
1197#include "assem_x64.c"
1198#endif
1199#ifdef __arm__
1200#include "assem_arm.c"
1201#endif
be516ebe 1202#ifdef __aarch64__
1203#include "assem_arm64.c"
1204#endif
57871462 1205
2a014d73 1206static void *get_trampoline(const void *f)
1207{
d9e2b173 1208 struct ndrc_tramp *tramp = NDRC_WRITE_OFFSET(&ndrc->tramp);
2a014d73 1209 size_t i;
1210
d9e2b173 1211 for (i = 0; i < ARRAY_SIZE(tramp->f); i++) {
1212 if (tramp->f[i] == f || tramp->f[i] == NULL)
2a014d73 1213 break;
1214 }
d9e2b173 1215 if (i == ARRAY_SIZE(tramp->f)) {
2a014d73 1216 SysPrintf("trampoline table is full, last func %p\n", f);
1217 abort();
1218 }
d9e2b173 1219 if (tramp->f[i] == NULL) {
1220 start_tcache_write(&tramp->f[i], &tramp->f[i + 1]);
1221 tramp->f[i] = f;
1222 end_tcache_write(&tramp->f[i], &tramp->f[i + 1]);
1223#ifdef HAVE_LIBNX
1224 // invalidate the RX mirror (unsure if necessary, but just in case...)
1225 armDCacheFlush(&ndrc->tramp.f[i], sizeof(ndrc->tramp.f[i]));
1226#endif
2a014d73 1227 }
1228 return &ndrc->tramp.ops[i];
1229}
1230
1231static void emit_far_jump(const void *f)
1232{
1233 if (can_jump_or_call(f)) {
1234 emit_jmp(f);
1235 return;
1236 }
1237
1238 f = get_trampoline(f);
1239 emit_jmp(f);
1240}
1241
1242static void emit_far_call(const void *f)
1243{
1244 if (can_jump_or_call(f)) {
1245 emit_call(f);
1246 return;
1247 }
1248
1249 f = get_trampoline(f);
1250 emit_call(f);
1251}
1252
57871462 1253// Check if an address is already compiled
1254// but don't return addresses which are about to expire from the cache
4149788d 1255static void *check_addr(u_int vaddr)
57871462 1256{
df4dc2b1 1257 struct ht_entry *ht_bin = hash_table_get(vaddr);
1258 size_t i;
b14b6a8f 1259 for (i = 0; i < ARRAY_SIZE(ht_bin->vaddr); i++) {
df4dc2b1 1260 if (ht_bin->vaddr[i] == vaddr)
93c0345b 1261 if (doesnt_expire_soon(ht_bin->tcaddr[i]))
104df9d3 1262 return ht_bin->tcaddr[i];
57871462 1263 }
104df9d3 1264
1265 // refactor to get_addr_nocompile?
1266 u_int start_page = get_page_prev(vaddr);
1267 u_int page, end_page = get_page(vaddr);
1268
1269 stat_inc(stat_jump_in_lookups);
1270 for (page = start_page; page <= end_page; page++) {
1271 const struct block_info *block;
1272 for (block = blocks[page]; block != NULL; block = block->next) {
1273 if (vaddr < block->start)
1274 break;
1275 if (block->is_dirty || vaddr >= block->start + block->len)
1276 continue;
1277 if (!doesnt_expire_soon(ndrc->translation_cache + block->tc_offs))
1278 continue;
1279 for (i = 0; i < block->jump_in_cnt; i++)
1280 if (block->jump_in[i].vaddr == vaddr)
1281 break;
1282 if (i == block->jump_in_cnt)
1283 continue;
1284
1285 // Update existing entry with current address
1286 void *addr = block->jump_in[i].addr;
1287 if (ht_bin->vaddr[0] == vaddr) {
1288 ht_bin->tcaddr[0] = addr;
1289 return addr;
1290 }
1291 if (ht_bin->vaddr[1] == vaddr) {
1292 ht_bin->tcaddr[1] = addr;
1293 return addr;
1294 }
1295 // Insert into hash table with low priority.
1296 // Don't evict existing entries, as they are probably
1297 // addresses that are being accessed frequently.
1298 if (ht_bin->vaddr[0] == -1) {
1299 ht_bin->vaddr[0] = vaddr;
1300 ht_bin->tcaddr[0] = addr;
57871462 1301 }
104df9d3 1302 else if (ht_bin->vaddr[1] == -1) {
1303 ht_bin->vaddr[1] = vaddr;
1304 ht_bin->tcaddr[1] = addr;
1305 }
1306 return addr;
57871462 1307 }
57871462 1308 }
104df9d3 1309 return NULL;
57871462 1310}
1311
104df9d3 1312static void blocks_clear(struct block_info **head)
1313{
1314 struct block_info *cur, *next;
1315
1316 if ((cur = *head)) {
1317 *head = NULL;
1318 while (cur) {
1319 next = cur->next;
1320 free(cur);
1321 cur = next;
1322 }
1323 }
1324}
1325
93c0345b 1326static int blocks_remove_matching_addrs(struct block_info **head,
1327 u_int base_offs, int shift)
104df9d3 1328{
1329 struct block_info *next;
93c0345b 1330 int hit = 0;
104df9d3 1331 while (*head) {
93c0345b 1332 if ((((*head)->tc_offs ^ base_offs) >> shift) == 0) {
1333 inv_debug("EXP: rm block %08x (tc_offs %zx)\n", (*head)->start, (*head)->tc_offs);
104df9d3 1334 invalidate_block(*head);
1335 next = (*head)->next;
1336 free(*head);
1337 *head = next;
1338 stat_dec(stat_blocks);
93c0345b 1339 hit = 1;
104df9d3 1340 }
1341 else
1342 {
1343 head = &((*head)->next);
1344 }
1345 }
93c0345b 1346 return hit;
104df9d3 1347}
57871462 1348
1349// This is called when we write to a compiled block (see do_invstub)
b7ad2f2c 1350static void unlink_jumps_vaddr_range(u_int start, u_int end)
57871462 1351{
104df9d3 1352 u_int page, start_page = get_page(start), end_page = get_page(end - 1);
b7ad2f2c 1353 int i;
104df9d3 1354
1355 for (page = start_page; page <= end_page; page++) {
b7ad2f2c 1356 struct jump_info *ji = jumps[page];
1357 if (ji == NULL)
1358 continue;
1359 for (i = 0; i < ji->count; ) {
1360 if (ji->e[i].target_vaddr < start || ji->e[i].target_vaddr >= end) {
1361 i++;
104df9d3 1362 continue;
1363 }
b7ad2f2c 1364
1365 inv_debug("INV: rm link to %08x (tc_offs %zx)\n", ji->e[i].target_vaddr,
1366 (u_char *)ji->e[i].stub - ndrc->translation_cache);
1367 void *host_addr = find_extjump_insn(ji->e[i].stub);
104df9d3 1368 mark_clear_cache(host_addr);
b7ad2f2c 1369 set_jump_target(host_addr, ji->e[i].stub); // point back to dyna_linker stub
104df9d3 1370
104df9d3 1371 stat_dec(stat_links);
b7ad2f2c 1372 ji->count--;
1373 if (i < ji->count) {
1374 ji->e[i] = ji->e[ji->count];
1375 continue;
1376 }
1377 i++;
1378 }
1379 }
1380}
1381
1382static void unlink_jumps_tc_range(struct jump_info *ji, u_int base_offs, int shift)
1383{
1384 int i;
1385 if (ji == NULL)
1386 return;
1387 for (i = 0; i < ji->count; ) {
1388 u_int tc_offs = (u_char *)ji->e[i].stub - ndrc->translation_cache;
1389 if (((tc_offs ^ base_offs) >> shift) != 0) {
1390 i++;
1391 continue;
1392 }
1393
1394 inv_debug("EXP: rm link to %08x (tc_offs %zx)\n", ji->e[i].target_vaddr, tc_offs);
1395 stat_dec(stat_links);
1396 ji->count--;
1397 if (i < ji->count) {
1398 ji->e[i] = ji->e[ji->count];
1399 continue;
104df9d3 1400 }
b7ad2f2c 1401 i++;
57871462 1402 }
104df9d3 1403}
9f51b4b9 1404
104df9d3 1405static void invalidate_block(struct block_info *block)
1406{
1407 u_int i;
f76eeef9 1408
104df9d3 1409 block->is_dirty = 1;
b7ad2f2c 1410 unlink_jumps_vaddr_range(block->start, block->start + block->len);
104df9d3 1411 for (i = 0; i < block->jump_in_cnt; i++)
1412 hash_table_remove(block->jump_in[i].vaddr);
57871462 1413}
9be4ba64 1414
104df9d3 1415static int invalidate_range(u_int start, u_int end,
1416 u32 *inv_start_ret, u32 *inv_end_ret)
9be4ba64 1417{
3280e616 1418 struct block_info *last_block = NULL;
104df9d3 1419 u_int start_page = get_page_prev(start);
1420 u_int end_page = get_page(end - 1);
1421 u_int start_m = pmmask(start);
ab4377be 1422 u_int end_m = pmmask(end - 1);
104df9d3 1423 u_int inv_start, inv_end;
1424 u_int blk_start_m, blk_end_m;
1425 u_int page;
1426 int hit = 0;
1427
1428 // additional area without code (to supplement invalid_code[]), [start, end)
1429 // avoids excessive ndrc_invalidate_addr() calls
1430 inv_start = start_m & ~0xfff;
1431 inv_end = end_m | 0xfff;
1432
1433 for (page = start_page; page <= end_page; page++) {
1434 struct block_info *block;
1435 for (block = blocks[page]; block != NULL; block = block->next) {
1436 if (block->is_dirty)
1437 continue;
3280e616 1438 last_block = block;
104df9d3 1439 blk_end_m = pmmask(block->start + block->len);
1440 if (blk_end_m <= start_m) {
1441 inv_start = max(inv_start, blk_end_m);
1442 continue;
1443 }
1444 blk_start_m = pmmask(block->start);
1445 if (end_m <= blk_start_m) {
1446 inv_end = min(inv_end, blk_start_m - 1);
1447 continue;
9be4ba64 1448 }
104df9d3 1449 if (!block->source) // "hack" block - leave it alone
1450 continue;
1451
1452 hit++;
1453 invalidate_block(block);
1454 stat_inc(stat_inv_hits);
9be4ba64 1455 }
9be4ba64 1456 }
104df9d3 1457
3280e616 1458 if (!hit && last_block && last_block->source) {
1459 // could be some leftover unused block, uselessly trapping writes
1460 last_block->inv_near_misses++;
1461 if (last_block->inv_near_misses > 128) {
1462 invalidate_block(last_block);
1463 stat_inc(stat_inv_hits);
1464 hit++;
1465 }
1466 }
104df9d3 1467 if (hit) {
1468 do_clear_cache();
1469#ifdef USE_MINI_HT
1470 memset(mini_ht, -1, sizeof(mini_ht));
1471#endif
1472 }
3280e616 1473
104df9d3 1474 if (inv_start <= (start_m & ~0xfff) && inv_end >= (start_m | 0xfff))
1475 // the whole page is empty now
1476 mark_invalid_code(start, 1, 1);
1477
1478 if (inv_start_ret) *inv_start_ret = inv_start | (start & 0xe0000000);
1479 if (inv_end_ret) *inv_end_ret = inv_end | (end & 0xe0000000);
1480 return hit;
9be4ba64 1481}
1482
104df9d3 1483void new_dynarec_invalidate_range(unsigned int start, unsigned int end)
1484{
1485 invalidate_range(start, end, NULL, NULL);
1486}
1487
1488void ndrc_invalidate_addr(u_int addr)
57871462 1489{
9be4ba64 1490 // this check is done by the caller
1491 //if (inv_code_start<=addr&&addr<=inv_code_end) { rhits++; return; }
104df9d3 1492 int ret = invalidate_range(addr, addr + 4, &inv_code_start, &inv_code_end);
1493 if (ret)
1494 inv_debug("INV ADDR: %08x hit %d blocks\n", addr, ret);
1495 else
1496 inv_debug("INV ADDR: %08x miss, inv %08x-%08x\n", addr, inv_code_start, inv_code_end);
ece032e6 1497 stat_inc(stat_inv_addr_calls);
57871462 1498}
9be4ba64 1499
dd3a91a1 1500// This is called when loading a save state.
1501// Anything could have changed, so invalidate everything.
104df9d3 1502void new_dynarec_invalidate_all_pages(void)
57871462 1503{
104df9d3 1504 struct block_info *block;
581335b0 1505 u_int page;
104df9d3 1506 for (page = 0; page < ARRAY_SIZE(blocks); page++) {
1507 for (block = blocks[page]; block != NULL; block = block->next) {
1508 if (block->is_dirty)
1509 continue;
1510 if (!block->source) // hack block?
1511 continue;
1512 invalidate_block(block);
1513 }
1514 }
1515
57871462 1516 #ifdef USE_MINI_HT
93c0345b 1517 memset(mini_ht, -1, sizeof(mini_ht));
57871462 1518 #endif
919981d0 1519 do_clear_cache();
57871462 1520}
1521
d1e4ebd9 1522static void do_invstub(int n)
1523{
1524 literal_pool(20);
882a08fc 1525 u_int reglist = stubs[n].a;
d1e4ebd9 1526 set_jump_target(stubs[n].addr, out);
1527 save_regs(reglist);
882a08fc 1528 if (stubs[n].b != 0)
1529 emit_mov(stubs[n].b, 0);
1530 emit_readword(&inv_code_start, 1);
1531 emit_readword(&inv_code_end, 2);
1532 emit_cmp(0, 1);
1533 emit_cmpcs(2, 0);
1534 void *jaddr = out;
1535 emit_jc(0);
104df9d3 1536 emit_far_call(ndrc_invalidate_addr);
882a08fc 1537 set_jump_target(jaddr, out);
d1e4ebd9 1538 restore_regs(reglist);
1539 emit_jmp(stubs[n].retaddr); // return address
1540}
1541
57871462 1542// Add an entry to jump_out after making a link
104df9d3 1543// src should point to code by emit_extjump()
b7ad2f2c 1544void ndrc_add_jump_out(u_int vaddr, void *src)
57871462 1545{
b7ad2f2c 1546 inv_debug("ndrc_add_jump_out: %p -> %x\n", src, vaddr);
1547 u_int page = get_page(vaddr);
1548 struct jump_info *ji;
1549
104df9d3 1550 stat_inc(stat_links);
b7ad2f2c 1551 check_extjump2(src);
1552 ji = jumps[page];
1553 if (ji == NULL) {
1554 ji = malloc(sizeof(*ji) + sizeof(ji->e[0]) * 16);
1555 ji->alloc = 16;
1556 ji->count = 0;
1557 }
1558 else if (ji->count >= ji->alloc) {
1559 ji->alloc += 16;
1560 ji = realloc(ji, sizeof(*ji) + sizeof(ji->e[0]) * ji->alloc);
1561 }
1562 jumps[page] = ji;
1563 ji->e[ji->count].target_vaddr = vaddr;
1564 ji->e[ji->count].stub = src;
1565 ji->count++;
57871462 1566}
1567
8062d65a 1568/* Register allocation */
1569
1570// Note: registers are allocated clean (unmodified state)
1571// if you intend to modify the register, you must call dirty_reg().
1572static void alloc_reg(struct regstat *cur,int i,signed char reg)
1573{
1574 int r,hr;
b7ec323c 1575 int preferred_reg = PREFERRED_REG_FIRST
1576 + reg % (PREFERRED_REG_LAST - PREFERRED_REG_FIRST + 1);
1577 if (reg == CCREG) preferred_reg = HOST_CCREG;
1578 if (reg == PTEMP || reg == FTEMP) preferred_reg = 12;
1579 assert(PREFERRED_REG_FIRST != EXCLUDE_REG && EXCLUDE_REG != HOST_REGS);
53358c1d 1580 assert(reg >= 0);
8062d65a 1581
1582 // Don't allocate unused registers
1583 if((cur->u>>reg)&1) return;
1584
1585 // see if it's already allocated
53358c1d 1586 if (get_reg(cur->regmap, reg) >= 0)
1587 return;
8062d65a 1588
1589 // Keep the same mapping if the register was already allocated in a loop
1590 preferred_reg = loop_reg(i,reg,preferred_reg);
1591
1592 // Try to allocate the preferred register
1593 if(cur->regmap[preferred_reg]==-1) {
1594 cur->regmap[preferred_reg]=reg;
1595 cur->dirty&=~(1<<preferred_reg);
1596 cur->isconst&=~(1<<preferred_reg);
1597 return;
1598 }
1599 r=cur->regmap[preferred_reg];
1600 assert(r < 64);
1601 if((cur->u>>r)&1) {
1602 cur->regmap[preferred_reg]=reg;
1603 cur->dirty&=~(1<<preferred_reg);
1604 cur->isconst&=~(1<<preferred_reg);
1605 return;
1606 }
1607
1608 // Clear any unneeded registers
1609 // We try to keep the mapping consistent, if possible, because it
1610 // makes branches easier (especially loops). So we try to allocate
1611 // first (see above) before removing old mappings. If this is not
1612 // possible then go ahead and clear out the registers that are no
1613 // longer needed.
1614 for(hr=0;hr<HOST_REGS;hr++)
1615 {
1616 r=cur->regmap[hr];
1617 if(r>=0) {
1618 assert(r < 64);
1619 if((cur->u>>r)&1) {cur->regmap[hr]=-1;break;}
1620 }
1621 }
b7ec323c 1622
8062d65a 1623 // Try to allocate any available register, but prefer
1624 // registers that have not been used recently.
b7ec323c 1625 if (i > 0) {
1626 for (hr = PREFERRED_REG_FIRST; ; ) {
1627 if (cur->regmap[hr] < 0) {
1628 int oldreg = regs[i-1].regmap[hr];
1629 if (oldreg < 0 || (oldreg != dops[i-1].rs1 && oldreg != dops[i-1].rs2
1630 && oldreg != dops[i-1].rt1 && oldreg != dops[i-1].rt2))
1631 {
8062d65a 1632 cur->regmap[hr]=reg;
1633 cur->dirty&=~(1<<hr);
1634 cur->isconst&=~(1<<hr);
1635 return;
1636 }
1637 }
b7ec323c 1638 hr++;
1639 if (hr == EXCLUDE_REG)
1640 hr++;
1641 if (hr == HOST_REGS)
1642 hr = 0;
1643 if (hr == PREFERRED_REG_FIRST)
1644 break;
8062d65a 1645 }
1646 }
b7ec323c 1647
8062d65a 1648 // Try to allocate any available register
b7ec323c 1649 for (hr = PREFERRED_REG_FIRST; ; ) {
1650 if (cur->regmap[hr] < 0) {
8062d65a 1651 cur->regmap[hr]=reg;
1652 cur->dirty&=~(1<<hr);
1653 cur->isconst&=~(1<<hr);
1654 return;
1655 }
b7ec323c 1656 hr++;
1657 if (hr == EXCLUDE_REG)
1658 hr++;
1659 if (hr == HOST_REGS)
1660 hr = 0;
1661 if (hr == PREFERRED_REG_FIRST)
1662 break;
8062d65a 1663 }
1664
1665 // Ok, now we have to evict someone
1666 // Pick a register we hopefully won't need soon
1667 u_char hsn[MAXREG+1];
1668 memset(hsn,10,sizeof(hsn));
1669 int j;
1670 lsn(hsn,i,&preferred_reg);
1671 //printf("eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",cur->regmap[0],cur->regmap[1],cur->regmap[2],cur->regmap[3],cur->regmap[5],cur->regmap[6],cur->regmap[7]);
1672 //printf("hsn(%x): %d %d %d %d %d %d %d\n",start+i*4,hsn[cur->regmap[0]&63],hsn[cur->regmap[1]&63],hsn[cur->regmap[2]&63],hsn[cur->regmap[3]&63],hsn[cur->regmap[5]&63],hsn[cur->regmap[6]&63],hsn[cur->regmap[7]&63]);
1673 if(i>0) {
1674 // Don't evict the cycle count at entry points, otherwise the entry
1675 // stub will have to write it.
cf95b4f0 1676 if(dops[i].bt&&hsn[CCREG]>2) hsn[CCREG]=2;
fe807a8a 1677 if (i>1 && hsn[CCREG] > 2 && dops[i-2].is_jump) hsn[CCREG]=2;
8062d65a 1678 for(j=10;j>=3;j--)
1679 {
1680 // Alloc preferred register if available
1681 if(hsn[r=cur->regmap[preferred_reg]&63]==j) {
1682 for(hr=0;hr<HOST_REGS;hr++) {
1683 // Evict both parts of a 64-bit register
9de8a0c3 1684 if(cur->regmap[hr]==r) {
8062d65a 1685 cur->regmap[hr]=-1;
1686 cur->dirty&=~(1<<hr);
1687 cur->isconst&=~(1<<hr);
1688 }
1689 }
1690 cur->regmap[preferred_reg]=reg;
1691 return;
1692 }
1693 for(r=1;r<=MAXREG;r++)
1694 {
cf95b4f0 1695 if(hsn[r]==j&&r!=dops[i-1].rs1&&r!=dops[i-1].rs2&&r!=dops[i-1].rt1&&r!=dops[i-1].rt2) {
8062d65a 1696 for(hr=0;hr<HOST_REGS;hr++) {
1697 if(hr!=HOST_CCREG||j<hsn[CCREG]) {
1698 if(cur->regmap[hr]==r) {
1699 cur->regmap[hr]=reg;
1700 cur->dirty&=~(1<<hr);
1701 cur->isconst&=~(1<<hr);
1702 return;
1703 }
1704 }
1705 }
1706 }
1707 }
1708 }
1709 }
1710 for(j=10;j>=0;j--)
1711 {
1712 for(r=1;r<=MAXREG;r++)
1713 {
1714 if(hsn[r]==j) {
8062d65a 1715 for(hr=0;hr<HOST_REGS;hr++) {
1716 if(cur->regmap[hr]==r) {
1717 cur->regmap[hr]=reg;
1718 cur->dirty&=~(1<<hr);
1719 cur->isconst&=~(1<<hr);
1720 return;
1721 }
1722 }
1723 }
1724 }
1725 }
7c3a5182 1726 SysPrintf("This shouldn't happen (alloc_reg)");abort();
8062d65a 1727}
1728
1729// Allocate a temporary register. This is done without regard to
1730// dirty status or whether the register we request is on the unneeded list
1731// Note: This will only allocate one register, even if called multiple times
1732static void alloc_reg_temp(struct regstat *cur,int i,signed char reg)
1733{
1734 int r,hr;
1735 int preferred_reg = -1;
1736
1737 // see if it's already allocated
1738 for(hr=0;hr<HOST_REGS;hr++)
1739 {
1740 if(hr!=EXCLUDE_REG&&cur->regmap[hr]==reg) return;
1741 }
1742
1743 // Try to allocate any available register
1744 for(hr=HOST_REGS-1;hr>=0;hr--) {
1745 if(hr!=EXCLUDE_REG&&cur->regmap[hr]==-1) {
1746 cur->regmap[hr]=reg;
1747 cur->dirty&=~(1<<hr);
1748 cur->isconst&=~(1<<hr);
1749 return;
1750 }
1751 }
1752
1753 // Find an unneeded register
1754 for(hr=HOST_REGS-1;hr>=0;hr--)
1755 {
1756 r=cur->regmap[hr];
1757 if(r>=0) {
1758 assert(r < 64);
1759 if((cur->u>>r)&1) {
1760 if(i==0||((unneeded_reg[i-1]>>r)&1)) {
1761 cur->regmap[hr]=reg;
1762 cur->dirty&=~(1<<hr);
1763 cur->isconst&=~(1<<hr);
1764 return;
1765 }
1766 }
1767 }
1768 }
1769
1770 // Ok, now we have to evict someone
1771 // Pick a register we hopefully won't need soon
1772 // TODO: we might want to follow unconditional jumps here
1773 // TODO: get rid of dupe code and make this into a function
1774 u_char hsn[MAXREG+1];
1775 memset(hsn,10,sizeof(hsn));
1776 int j;
1777 lsn(hsn,i,&preferred_reg);
1778 //printf("hsn: %d %d %d %d %d %d %d\n",hsn[cur->regmap[0]&63],hsn[cur->regmap[1]&63],hsn[cur->regmap[2]&63],hsn[cur->regmap[3]&63],hsn[cur->regmap[5]&63],hsn[cur->regmap[6]&63],hsn[cur->regmap[7]&63]);
1779 if(i>0) {
1780 // Don't evict the cycle count at entry points, otherwise the entry
1781 // stub will have to write it.
cf95b4f0 1782 if(dops[i].bt&&hsn[CCREG]>2) hsn[CCREG]=2;
fe807a8a 1783 if (i>1 && hsn[CCREG] > 2 && dops[i-2].is_jump) hsn[CCREG]=2;
8062d65a 1784 for(j=10;j>=3;j--)
1785 {
1786 for(r=1;r<=MAXREG;r++)
1787 {
cf95b4f0 1788 if(hsn[r]==j&&r!=dops[i-1].rs1&&r!=dops[i-1].rs2&&r!=dops[i-1].rt1&&r!=dops[i-1].rt2) {
8062d65a 1789 for(hr=0;hr<HOST_REGS;hr++) {
1790 if(hr!=HOST_CCREG||hsn[CCREG]>2) {
1791 if(cur->regmap[hr]==r) {
1792 cur->regmap[hr]=reg;
1793 cur->dirty&=~(1<<hr);
1794 cur->isconst&=~(1<<hr);
1795 return;
1796 }
1797 }
1798 }
1799 }
1800 }
1801 }
1802 }
1803 for(j=10;j>=0;j--)
1804 {
1805 for(r=1;r<=MAXREG;r++)
1806 {
1807 if(hsn[r]==j) {
8062d65a 1808 for(hr=0;hr<HOST_REGS;hr++) {
1809 if(cur->regmap[hr]==r) {
1810 cur->regmap[hr]=reg;
1811 cur->dirty&=~(1<<hr);
1812 cur->isconst&=~(1<<hr);
1813 return;
1814 }
1815 }
1816 }
1817 }
1818 }
7c3a5182 1819 SysPrintf("This shouldn't happen");abort();
8062d65a 1820}
1821
ad49de89 1822static void mov_alloc(struct regstat *current,int i)
57871462 1823{
cf95b4f0 1824 if (dops[i].rs1 == HIREG || dops[i].rs1 == LOREG) {
9a3ccfeb 1825 alloc_cc(current,i); // for stalls
1826 dirty_reg(current,CCREG);
32631e6a 1827 }
1828
57871462 1829 // Note: Don't need to actually alloc the source registers
cf95b4f0 1830 //alloc_reg(current,i,dops[i].rs1);
1831 alloc_reg(current,i,dops[i].rt1);
ad49de89 1832
cf95b4f0 1833 clear_const(current,dops[i].rs1);
1834 clear_const(current,dops[i].rt1);
1835 dirty_reg(current,dops[i].rt1);
57871462 1836}
1837
ad49de89 1838static void shiftimm_alloc(struct regstat *current,int i)
57871462 1839{
cf95b4f0 1840 if(dops[i].opcode2<=0x3) // SLL/SRL/SRA
57871462 1841 {
cf95b4f0 1842 if(dops[i].rt1) {
1843 if(dops[i].rs1&&needed_again(dops[i].rs1,i)) alloc_reg(current,i,dops[i].rs1);
53dc27f6 1844 else dops[i].use_lt1=!!dops[i].rs1;
cf95b4f0 1845 alloc_reg(current,i,dops[i].rt1);
1846 dirty_reg(current,dops[i].rt1);
1847 if(is_const(current,dops[i].rs1)) {
1848 int v=get_const(current,dops[i].rs1);
1849 if(dops[i].opcode2==0x00) set_const(current,dops[i].rt1,v<<imm[i]);
1850 if(dops[i].opcode2==0x02) set_const(current,dops[i].rt1,(u_int)v>>imm[i]);
1851 if(dops[i].opcode2==0x03) set_const(current,dops[i].rt1,v>>imm[i]);
dc49e339 1852 }
cf95b4f0 1853 else clear_const(current,dops[i].rt1);
57871462 1854 }
1855 }
dc49e339 1856 else
1857 {
cf95b4f0 1858 clear_const(current,dops[i].rs1);
1859 clear_const(current,dops[i].rt1);
dc49e339 1860 }
1861
cf95b4f0 1862 if(dops[i].opcode2>=0x38&&dops[i].opcode2<=0x3b) // DSLL/DSRL/DSRA
57871462 1863 {
9c45ca93 1864 assert(0);
57871462 1865 }
cf95b4f0 1866 if(dops[i].opcode2==0x3c) // DSLL32
57871462 1867 {
9c45ca93 1868 assert(0);
57871462 1869 }
cf95b4f0 1870 if(dops[i].opcode2==0x3e) // DSRL32
57871462 1871 {
9c45ca93 1872 assert(0);
57871462 1873 }
cf95b4f0 1874 if(dops[i].opcode2==0x3f) // DSRA32
57871462 1875 {
9c45ca93 1876 assert(0);
57871462 1877 }
1878}
1879
ad49de89 1880static void shift_alloc(struct regstat *current,int i)
57871462 1881{
cf95b4f0 1882 if(dops[i].rt1) {
1883 if(dops[i].opcode2<=0x07) // SLLV/SRLV/SRAV
57871462 1884 {
cf95b4f0 1885 if(dops[i].rs1) alloc_reg(current,i,dops[i].rs1);
1886 if(dops[i].rs2) alloc_reg(current,i,dops[i].rs2);
1887 alloc_reg(current,i,dops[i].rt1);
1888 if(dops[i].rt1==dops[i].rs2) {
e1190b87 1889 alloc_reg_temp(current,i,-1);
1890 minimum_free_regs[i]=1;
1891 }
57871462 1892 } else { // DSLLV/DSRLV/DSRAV
00fa9369 1893 assert(0);
57871462 1894 }
cf95b4f0 1895 clear_const(current,dops[i].rs1);
1896 clear_const(current,dops[i].rs2);
1897 clear_const(current,dops[i].rt1);
1898 dirty_reg(current,dops[i].rt1);
57871462 1899 }
1900}
1901
ad49de89 1902static void alu_alloc(struct regstat *current,int i)
57871462 1903{
cf95b4f0 1904 if(dops[i].opcode2>=0x20&&dops[i].opcode2<=0x23) { // ADD/ADDU/SUB/SUBU
1905 if(dops[i].rt1) {
1906 if(dops[i].rs1&&dops[i].rs2) {
1907 alloc_reg(current,i,dops[i].rs1);
1908 alloc_reg(current,i,dops[i].rs2);
57871462 1909 }
1910 else {
cf95b4f0 1911 if(dops[i].rs1&&needed_again(dops[i].rs1,i)) alloc_reg(current,i,dops[i].rs1);
1912 if(dops[i].rs2&&needed_again(dops[i].rs2,i)) alloc_reg(current,i,dops[i].rs2);
57871462 1913 }
cf95b4f0 1914 alloc_reg(current,i,dops[i].rt1);
57871462 1915 }
57871462 1916 }
cf95b4f0 1917 if(dops[i].opcode2==0x2a||dops[i].opcode2==0x2b) { // SLT/SLTU
1918 if(dops[i].rt1) {
1919 alloc_reg(current,i,dops[i].rs1);
1920 alloc_reg(current,i,dops[i].rs2);
1921 alloc_reg(current,i,dops[i].rt1);
57871462 1922 }
57871462 1923 }
cf95b4f0 1924 if(dops[i].opcode2>=0x24&&dops[i].opcode2<=0x27) { // AND/OR/XOR/NOR
1925 if(dops[i].rt1) {
1926 if(dops[i].rs1&&dops[i].rs2) {
1927 alloc_reg(current,i,dops[i].rs1);
1928 alloc_reg(current,i,dops[i].rs2);
57871462 1929 }
1930 else
1931 {
cf95b4f0 1932 if(dops[i].rs1&&needed_again(dops[i].rs1,i)) alloc_reg(current,i,dops[i].rs1);
1933 if(dops[i].rs2&&needed_again(dops[i].rs2,i)) alloc_reg(current,i,dops[i].rs2);
57871462 1934 }
cf95b4f0 1935 alloc_reg(current,i,dops[i].rt1);
57871462 1936 }
1937 }
cf95b4f0 1938 if(dops[i].opcode2>=0x2c&&dops[i].opcode2<=0x2f) { // DADD/DADDU/DSUB/DSUBU
00fa9369 1939 assert(0);
57871462 1940 }
cf95b4f0 1941 clear_const(current,dops[i].rs1);
1942 clear_const(current,dops[i].rs2);
1943 clear_const(current,dops[i].rt1);
1944 dirty_reg(current,dops[i].rt1);
57871462 1945}
1946
ad49de89 1947static void imm16_alloc(struct regstat *current,int i)
57871462 1948{
cf95b4f0 1949 if(dops[i].rs1&&needed_again(dops[i].rs1,i)) alloc_reg(current,i,dops[i].rs1);
53dc27f6 1950 else dops[i].use_lt1=!!dops[i].rs1;
cf95b4f0 1951 if(dops[i].rt1) alloc_reg(current,i,dops[i].rt1);
1952 if(dops[i].opcode==0x18||dops[i].opcode==0x19) { // DADDI/DADDIU
00fa9369 1953 assert(0);
57871462 1954 }
cf95b4f0 1955 else if(dops[i].opcode==0x0a||dops[i].opcode==0x0b) { // SLTI/SLTIU
1956 clear_const(current,dops[i].rs1);
1957 clear_const(current,dops[i].rt1);
57871462 1958 }
cf95b4f0 1959 else if(dops[i].opcode>=0x0c&&dops[i].opcode<=0x0e) { // ANDI/ORI/XORI
1960 if(is_const(current,dops[i].rs1)) {
1961 int v=get_const(current,dops[i].rs1);
1962 if(dops[i].opcode==0x0c) set_const(current,dops[i].rt1,v&imm[i]);
1963 if(dops[i].opcode==0x0d) set_const(current,dops[i].rt1,v|imm[i]);
1964 if(dops[i].opcode==0x0e) set_const(current,dops[i].rt1,v^imm[i]);
57871462 1965 }
cf95b4f0 1966 else clear_const(current,dops[i].rt1);
57871462 1967 }
cf95b4f0 1968 else if(dops[i].opcode==0x08||dops[i].opcode==0x09) { // ADDI/ADDIU
1969 if(is_const(current,dops[i].rs1)) {
1970 int v=get_const(current,dops[i].rs1);
1971 set_const(current,dops[i].rt1,v+imm[i]);
57871462 1972 }
cf95b4f0 1973 else clear_const(current,dops[i].rt1);
57871462 1974 }
1975 else {
cf95b4f0 1976 set_const(current,dops[i].rt1,imm[i]<<16); // LUI
57871462 1977 }
cf95b4f0 1978 dirty_reg(current,dops[i].rt1);
57871462 1979}
1980
ad49de89 1981static void load_alloc(struct regstat *current,int i)
57871462 1982{
cf95b4f0 1983 clear_const(current,dops[i].rt1);
1984 //if(dops[i].rs1!=dops[i].rt1&&needed_again(dops[i].rs1,i)) clear_const(current,dops[i].rs1); // Does this help or hurt?
1985 if(!dops[i].rs1) current->u&=~1LL; // Allow allocating r0 if it's the source register
37387d8b 1986 if (needed_again(dops[i].rs1, i))
1987 alloc_reg(current, i, dops[i].rs1);
1988 if (ram_offset)
1989 alloc_reg(current, i, ROREG);
cf95b4f0 1990 if(dops[i].rt1&&!((current->u>>dops[i].rt1)&1)) {
1991 alloc_reg(current,i,dops[i].rt1);
1992 assert(get_reg(current->regmap,dops[i].rt1)>=0);
1993 if(dops[i].opcode==0x27||dops[i].opcode==0x37) // LWU/LD
57871462 1994 {
ad49de89 1995 assert(0);
57871462 1996 }
cf95b4f0 1997 else if(dops[i].opcode==0x1A||dops[i].opcode==0x1B) // LDL/LDR
57871462 1998 {
ad49de89 1999 assert(0);
57871462 2000 }
cf95b4f0 2001 dirty_reg(current,dops[i].rt1);
57871462 2002 // LWL/LWR need a temporary register for the old value
cf95b4f0 2003 if(dops[i].opcode==0x22||dops[i].opcode==0x26)
57871462 2004 {
2005 alloc_reg(current,i,FTEMP);
2006 alloc_reg_temp(current,i,-1);
e1190b87 2007 minimum_free_regs[i]=1;
57871462 2008 }
2009 }
2010 else
2011 {
373d1d07 2012 // Load to r0 or unneeded register (dummy load)
57871462 2013 // but we still need a register to calculate the address
cf95b4f0 2014 if(dops[i].opcode==0x22||dops[i].opcode==0x26)
535d208a 2015 {
2016 alloc_reg(current,i,FTEMP); // LWL/LWR need another temporary
2017 }
57871462 2018 alloc_reg_temp(current,i,-1);
e1190b87 2019 minimum_free_regs[i]=1;
cf95b4f0 2020 if(dops[i].opcode==0x1A||dops[i].opcode==0x1B) // LDL/LDR
535d208a 2021 {
ad49de89 2022 assert(0);
535d208a 2023 }
57871462 2024 }
2025}
2026
4149788d 2027static void store_alloc(struct regstat *current,int i)
57871462 2028{
cf95b4f0 2029 clear_const(current,dops[i].rs2);
2030 if(!(dops[i].rs2)) current->u&=~1LL; // Allow allocating r0 if necessary
2031 if(needed_again(dops[i].rs1,i)) alloc_reg(current,i,dops[i].rs1);
2032 alloc_reg(current,i,dops[i].rs2);
2033 if(dops[i].opcode==0x2c||dops[i].opcode==0x2d||dops[i].opcode==0x3f) { // 64-bit SDL/SDR/SD
ad49de89 2034 assert(0);
57871462 2035 }
37387d8b 2036 if (ram_offset)
2037 alloc_reg(current, i, ROREG);
57871462 2038 #if defined(HOST_IMM8)
2039 // On CPUs without 32-bit immediates we need a pointer to invalid_code
37387d8b 2040 alloc_reg(current, i, INVCP);
57871462 2041 #endif
cf95b4f0 2042 if(dops[i].opcode==0x2a||dops[i].opcode==0x2e||dops[i].opcode==0x2c||dops[i].opcode==0x2d) { // SWL/SWL/SDL/SDR
57871462 2043 alloc_reg(current,i,FTEMP);
2044 }
2045 // We need a temporary register for address generation
2046 alloc_reg_temp(current,i,-1);
e1190b87 2047 minimum_free_regs[i]=1;
57871462 2048}
2049
4149788d 2050static void c1ls_alloc(struct regstat *current,int i)
57871462 2051{
cf95b4f0 2052 clear_const(current,dops[i].rt1);
57871462 2053 alloc_reg(current,i,CSREG); // Status
57871462 2054}
2055
4149788d 2056static void c2ls_alloc(struct regstat *current,int i)
b9b61529 2057{
cf95b4f0 2058 clear_const(current,dops[i].rt1);
2059 if(needed_again(dops[i].rs1,i)) alloc_reg(current,i,dops[i].rs1);
b9b61529 2060 alloc_reg(current,i,FTEMP);
37387d8b 2061 if (ram_offset)
2062 alloc_reg(current, i, ROREG);
b9b61529 2063 #if defined(HOST_IMM8)
2064 // On CPUs without 32-bit immediates we need a pointer to invalid_code
37387d8b 2065 if (dops[i].opcode == 0x3a) // SWC2
b9b61529 2066 alloc_reg(current,i,INVCP);
2067 #endif
2068 // We need a temporary register for address generation
2069 alloc_reg_temp(current,i,-1);
e1190b87 2070 minimum_free_regs[i]=1;
b9b61529 2071}
2072
57871462 2073#ifndef multdiv_alloc
4149788d 2074static void multdiv_alloc(struct regstat *current,int i)
57871462 2075{
2076 // case 0x18: MULT
2077 // case 0x19: MULTU
2078 // case 0x1A: DIV
2079 // case 0x1B: DIVU
2080 // case 0x1C: DMULT
2081 // case 0x1D: DMULTU
2082 // case 0x1E: DDIV
2083 // case 0x1F: DDIVU
cf95b4f0 2084 clear_const(current,dops[i].rs1);
2085 clear_const(current,dops[i].rs2);
32631e6a 2086 alloc_cc(current,i); // for stalls
cf95b4f0 2087 if(dops[i].rs1&&dops[i].rs2)
57871462 2088 {
cf95b4f0 2089 if((dops[i].opcode2&4)==0) // 32-bit
57871462 2090 {
2091 current->u&=~(1LL<<HIREG);
2092 current->u&=~(1LL<<LOREG);
2093 alloc_reg(current,i,HIREG);
2094 alloc_reg(current,i,LOREG);
cf95b4f0 2095 alloc_reg(current,i,dops[i].rs1);
2096 alloc_reg(current,i,dops[i].rs2);
57871462 2097 dirty_reg(current,HIREG);
2098 dirty_reg(current,LOREG);
2099 }
2100 else // 64-bit
2101 {
00fa9369 2102 assert(0);
57871462 2103 }
2104 }
2105 else
2106 {
2107 // Multiply by zero is zero.
2108 // MIPS does not have a divide by zero exception.
2109 // The result is undefined, we return zero.
2110 alloc_reg(current,i,HIREG);
2111 alloc_reg(current,i,LOREG);
57871462 2112 dirty_reg(current,HIREG);
2113 dirty_reg(current,LOREG);
2114 }
2115}
2116#endif
2117
4149788d 2118static void cop0_alloc(struct regstat *current,int i)
57871462 2119{
cf95b4f0 2120 if(dops[i].opcode2==0) // MFC0
57871462 2121 {
cf95b4f0 2122 if(dops[i].rt1) {
2123 clear_const(current,dops[i].rt1);
57871462 2124 alloc_all(current,i);
cf95b4f0 2125 alloc_reg(current,i,dops[i].rt1);
2126 dirty_reg(current,dops[i].rt1);
57871462 2127 }
2128 }
cf95b4f0 2129 else if(dops[i].opcode2==4) // MTC0
57871462 2130 {
cf95b4f0 2131 if(dops[i].rs1){
2132 clear_const(current,dops[i].rs1);
2133 alloc_reg(current,i,dops[i].rs1);
57871462 2134 alloc_all(current,i);
2135 }
2136 else {
2137 alloc_all(current,i); // FIXME: Keep r0
2138 current->u&=~1LL;
2139 alloc_reg(current,i,0);
2140 }
2141 }
2142 else
2143 {
55a695d9 2144 // RFE
cf95b4f0 2145 assert(dops[i].opcode2==0x10);
57871462 2146 alloc_all(current,i);
2147 }
e1190b87 2148 minimum_free_regs[i]=HOST_REGS;
57871462 2149}
2150
81dbbf4c 2151static void cop2_alloc(struct regstat *current,int i)
57871462 2152{
cf95b4f0 2153 if (dops[i].opcode2 < 3) // MFC2/CFC2
57871462 2154 {
81dbbf4c 2155 alloc_cc(current,i); // for stalls
2156 dirty_reg(current,CCREG);
cf95b4f0 2157 if(dops[i].rt1){
2158 clear_const(current,dops[i].rt1);
2159 alloc_reg(current,i,dops[i].rt1);
2160 dirty_reg(current,dops[i].rt1);
57871462 2161 }
57871462 2162 }
cf95b4f0 2163 else if (dops[i].opcode2 > 3) // MTC2/CTC2
57871462 2164 {
cf95b4f0 2165 if(dops[i].rs1){
2166 clear_const(current,dops[i].rs1);
2167 alloc_reg(current,i,dops[i].rs1);
57871462 2168 }
2169 else {
2170 current->u&=~1LL;
2171 alloc_reg(current,i,0);
57871462 2172 }
2173 }
81dbbf4c 2174 alloc_reg_temp(current,i,-1);
e1190b87 2175 minimum_free_regs[i]=1;
57871462 2176}
00fa9369 2177
4149788d 2178static void c2op_alloc(struct regstat *current,int i)
b9b61529 2179{
81dbbf4c 2180 alloc_cc(current,i); // for stalls
2181 dirty_reg(current,CCREG);
b9b61529 2182 alloc_reg_temp(current,i,-1);
2183}
57871462 2184
4149788d 2185static void syscall_alloc(struct regstat *current,int i)
57871462 2186{
2187 alloc_cc(current,i);
2188 dirty_reg(current,CCREG);
2189 alloc_all(current,i);
e1190b87 2190 minimum_free_regs[i]=HOST_REGS;
57871462 2191 current->isconst=0;
2192}
2193
4149788d 2194static void delayslot_alloc(struct regstat *current,int i)
57871462 2195{
cf95b4f0 2196 switch(dops[i].itype) {
57871462 2197 case UJUMP:
2198 case CJUMP:
2199 case SJUMP:
2200 case RJUMP:
57871462 2201 case SYSCALL:
7139f3c8 2202 case HLECALL:
57871462 2203 case IMM16:
2204 imm16_alloc(current,i);
2205 break;
2206 case LOAD:
2207 case LOADLR:
2208 load_alloc(current,i);
2209 break;
2210 case STORE:
2211 case STORELR:
2212 store_alloc(current,i);
2213 break;
2214 case ALU:
2215 alu_alloc(current,i);
2216 break;
2217 case SHIFT:
2218 shift_alloc(current,i);
2219 break;
2220 case MULTDIV:
2221 multdiv_alloc(current,i);
2222 break;
2223 case SHIFTIMM:
2224 shiftimm_alloc(current,i);
2225 break;
2226 case MOV:
2227 mov_alloc(current,i);
2228 break;
2229 case COP0:
2230 cop0_alloc(current,i);
2231 break;
2232 case COP1:
81dbbf4c 2233 break;
b9b61529 2234 case COP2:
81dbbf4c 2235 cop2_alloc(current,i);
57871462 2236 break;
2237 case C1LS:
2238 c1ls_alloc(current,i);
2239 break;
b9b61529 2240 case C2LS:
2241 c2ls_alloc(current,i);
2242 break;
b9b61529 2243 case C2OP:
2244 c2op_alloc(current,i);
2245 break;
57871462 2246 }
2247}
2248
b14b6a8f 2249static void add_stub(enum stub_type type, void *addr, void *retaddr,
2250 u_int a, uintptr_t b, uintptr_t c, u_int d, u_int e)
2251{
d1e4ebd9 2252 assert(stubcount < ARRAY_SIZE(stubs));
b14b6a8f 2253 stubs[stubcount].type = type;
2254 stubs[stubcount].addr = addr;
2255 stubs[stubcount].retaddr = retaddr;
2256 stubs[stubcount].a = a;
2257 stubs[stubcount].b = b;
2258 stubs[stubcount].c = c;
2259 stubs[stubcount].d = d;
2260 stubs[stubcount].e = e;
57871462 2261 stubcount++;
2262}
2263
b14b6a8f 2264static void add_stub_r(enum stub_type type, void *addr, void *retaddr,
81dbbf4c 2265 int i, int addr_reg, const struct regstat *i_regs, int ccadj, u_int reglist)
b14b6a8f 2266{
2267 add_stub(type, addr, retaddr, i, addr_reg, (uintptr_t)i_regs, ccadj, reglist);
2268}
2269
57871462 2270// Write out a single register
2330734f 2271static void wb_register(signed char r, const signed char regmap[], uint64_t dirty)
57871462 2272{
2273 int hr;
2274 for(hr=0;hr<HOST_REGS;hr++) {
2275 if(hr!=EXCLUDE_REG) {
9de8a0c3 2276 if(regmap[hr]==r) {
57871462 2277 if((dirty>>hr)&1) {
ad49de89 2278 assert(regmap[hr]<64);
2279 emit_storereg(r,hr);
57871462 2280 }
2281 }
2282 }
2283 }
2284}
2285
8062d65a 2286static void wb_valid(signed char pre[],signed char entry[],u_int dirty_pre,u_int dirty,uint64_t u)
2287{
2288 //if(dirty_pre==dirty) return;
53358c1d 2289 int hr, r;
2290 for (hr = 0; hr < HOST_REGS; hr++) {
2291 r = pre[hr];
2292 if (r < 1 || r > 33 || ((u >> r) & 1))
2293 continue;
2294 if (((dirty_pre & ~dirty) >> hr) & 1)
2295 emit_storereg(r, hr);
8062d65a 2296 }
2297}
2298
687b4580 2299// trashes r2
2300static void pass_args(int a0, int a1)
2301{
2302 if(a0==1&&a1==0) {
2303 // must swap
2304 emit_mov(a0,2); emit_mov(a1,1); emit_mov(2,0);
2305 }
2306 else if(a0!=0&&a1==0) {
2307 emit_mov(a1,1);
2308 if (a0>=0) emit_mov(a0,0);
2309 }
2310 else {
2311 if(a0>=0&&a0!=0) emit_mov(a0,0);
2312 if(a1>=0&&a1!=1) emit_mov(a1,1);
2313 }
2314}
2315
2330734f 2316static void alu_assemble(int i, const struct regstat *i_regs)
57871462 2317{
cf95b4f0 2318 if(dops[i].opcode2>=0x20&&dops[i].opcode2<=0x23) { // ADD/ADDU/SUB/SUBU
2319 if(dops[i].rt1) {
57871462 2320 signed char s1,s2,t;
cf95b4f0 2321 t=get_reg(i_regs->regmap,dops[i].rt1);
57871462 2322 if(t>=0) {
cf95b4f0 2323 s1=get_reg(i_regs->regmap,dops[i].rs1);
2324 s2=get_reg(i_regs->regmap,dops[i].rs2);
2325 if(dops[i].rs1&&dops[i].rs2) {
57871462 2326 assert(s1>=0);
2327 assert(s2>=0);
cf95b4f0 2328 if(dops[i].opcode2&2) emit_sub(s1,s2,t);
57871462 2329 else emit_add(s1,s2,t);
2330 }
cf95b4f0 2331 else if(dops[i].rs1) {
57871462 2332 if(s1>=0) emit_mov(s1,t);
cf95b4f0 2333 else emit_loadreg(dops[i].rs1,t);
57871462 2334 }
cf95b4f0 2335 else if(dops[i].rs2) {
57871462 2336 if(s2>=0) {
cf95b4f0 2337 if(dops[i].opcode2&2) emit_neg(s2,t);
57871462 2338 else emit_mov(s2,t);
2339 }
2340 else {
cf95b4f0 2341 emit_loadreg(dops[i].rs2,t);
2342 if(dops[i].opcode2&2) emit_neg(t,t);
57871462 2343 }
2344 }
2345 else emit_zeroreg(t);
2346 }
2347 }
2348 }
cf95b4f0 2349 if(dops[i].opcode2>=0x2c&&dops[i].opcode2<=0x2f) { // DADD/DADDU/DSUB/DSUBU
00fa9369 2350 assert(0);
57871462 2351 }
cf95b4f0 2352 if(dops[i].opcode2==0x2a||dops[i].opcode2==0x2b) { // SLT/SLTU
2353 if(dops[i].rt1) {
ad49de89 2354 signed char s1l,s2l,t;
57871462 2355 {
cf95b4f0 2356 t=get_reg(i_regs->regmap,dops[i].rt1);
57871462 2357 //assert(t>=0);
2358 if(t>=0) {
cf95b4f0 2359 s1l=get_reg(i_regs->regmap,dops[i].rs1);
2360 s2l=get_reg(i_regs->regmap,dops[i].rs2);
2361 if(dops[i].rs2==0) // rx<r0
57871462 2362 {
cf95b4f0 2363 if(dops[i].opcode2==0x2a&&dops[i].rs1!=0) { // SLT
06e425d7 2364 assert(s1l>=0);
57871462 2365 emit_shrimm(s1l,31,t);
06e425d7 2366 }
2367 else // SLTU (unsigned can not be less than zero, 0<0)
57871462 2368 emit_zeroreg(t);
2369 }
cf95b4f0 2370 else if(dops[i].rs1==0) // r0<rx
57871462 2371 {
2372 assert(s2l>=0);
cf95b4f0 2373 if(dops[i].opcode2==0x2a) // SLT
57871462 2374 emit_set_gz32(s2l,t);
2375 else // SLTU (set if not zero)
2376 emit_set_nz32(s2l,t);
2377 }
2378 else{
2379 assert(s1l>=0);assert(s2l>=0);
cf95b4f0 2380 if(dops[i].opcode2==0x2a) // SLT
57871462 2381 emit_set_if_less32(s1l,s2l,t);
2382 else // SLTU
2383 emit_set_if_carry32(s1l,s2l,t);
2384 }
2385 }
2386 }
2387 }
2388 }
cf95b4f0 2389 if(dops[i].opcode2>=0x24&&dops[i].opcode2<=0x27) { // AND/OR/XOR/NOR
2390 if(dops[i].rt1) {
ad49de89 2391 signed char s1l,s2l,tl;
cf95b4f0 2392 tl=get_reg(i_regs->regmap,dops[i].rt1);
57871462 2393 {
57871462 2394 if(tl>=0) {
cf95b4f0 2395 s1l=get_reg(i_regs->regmap,dops[i].rs1);
2396 s2l=get_reg(i_regs->regmap,dops[i].rs2);
2397 if(dops[i].rs1&&dops[i].rs2) {
57871462 2398 assert(s1l>=0);
2399 assert(s2l>=0);
cf95b4f0 2400 if(dops[i].opcode2==0x24) { // AND
57871462 2401 emit_and(s1l,s2l,tl);
2402 } else
cf95b4f0 2403 if(dops[i].opcode2==0x25) { // OR
57871462 2404 emit_or(s1l,s2l,tl);
2405 } else
cf95b4f0 2406 if(dops[i].opcode2==0x26) { // XOR
57871462 2407 emit_xor(s1l,s2l,tl);
2408 } else
cf95b4f0 2409 if(dops[i].opcode2==0x27) { // NOR
57871462 2410 emit_or(s1l,s2l,tl);
2411 emit_not(tl,tl);
2412 }
2413 }
2414 else
2415 {
cf95b4f0 2416 if(dops[i].opcode2==0x24) { // AND
57871462 2417 emit_zeroreg(tl);
2418 } else
cf95b4f0 2419 if(dops[i].opcode2==0x25||dops[i].opcode2==0x26) { // OR/XOR
2420 if(dops[i].rs1){
57871462 2421 if(s1l>=0) emit_mov(s1l,tl);
cf95b4f0 2422 else emit_loadreg(dops[i].rs1,tl); // CHECK: regmap_entry?
57871462 2423 }
2424 else
cf95b4f0 2425 if(dops[i].rs2){
57871462 2426 if(s2l>=0) emit_mov(s2l,tl);
cf95b4f0 2427 else emit_loadreg(dops[i].rs2,tl); // CHECK: regmap_entry?
57871462 2428 }
2429 else emit_zeroreg(tl);
2430 } else
cf95b4f0 2431 if(dops[i].opcode2==0x27) { // NOR
2432 if(dops[i].rs1){
57871462 2433 if(s1l>=0) emit_not(s1l,tl);
2434 else {
cf95b4f0 2435 emit_loadreg(dops[i].rs1,tl);
57871462 2436 emit_not(tl,tl);
2437 }
2438 }
2439 else
cf95b4f0 2440 if(dops[i].rs2){
57871462 2441 if(s2l>=0) emit_not(s2l,tl);
2442 else {
cf95b4f0 2443 emit_loadreg(dops[i].rs2,tl);
57871462 2444 emit_not(tl,tl);
2445 }
2446 }
2447 else emit_movimm(-1,tl);
2448 }
2449 }
2450 }
2451 }
2452 }
2453 }
2454}
2455
2330734f 2456static void imm16_assemble(int i, const struct regstat *i_regs)
57871462 2457{
cf95b4f0 2458 if (dops[i].opcode==0x0f) { // LUI
2459 if(dops[i].rt1) {
57871462 2460 signed char t;
cf95b4f0 2461 t=get_reg(i_regs->regmap,dops[i].rt1);
57871462 2462 //assert(t>=0);
2463 if(t>=0) {
2464 if(!((i_regs->isconst>>t)&1))
2465 emit_movimm(imm[i]<<16,t);
2466 }
2467 }
2468 }
cf95b4f0 2469 if(dops[i].opcode==0x08||dops[i].opcode==0x09) { // ADDI/ADDIU
2470 if(dops[i].rt1) {
57871462 2471 signed char s,t;
cf95b4f0 2472 t=get_reg(i_regs->regmap,dops[i].rt1);
2473 s=get_reg(i_regs->regmap,dops[i].rs1);
2474 if(dops[i].rs1) {
57871462 2475 //assert(t>=0);
2476 //assert(s>=0);
2477 if(t>=0) {
2478 if(!((i_regs->isconst>>t)&1)) {
2479 if(s<0) {
cf95b4f0 2480 if(i_regs->regmap_entry[t]!=dops[i].rs1) emit_loadreg(dops[i].rs1,t);
57871462 2481 emit_addimm(t,imm[i],t);
2482 }else{
2483 if(!((i_regs->wasconst>>s)&1))
2484 emit_addimm(s,imm[i],t);
2485 else
2486 emit_movimm(constmap[i][s]+imm[i],t);
2487 }
2488 }
2489 }
2490 } else {
2491 if(t>=0) {
2492 if(!((i_regs->isconst>>t)&1))
2493 emit_movimm(imm[i],t);
2494 }
2495 }
2496 }
2497 }
cf95b4f0 2498 if(dops[i].opcode==0x18||dops[i].opcode==0x19) { // DADDI/DADDIU
2499 if(dops[i].rt1) {
7c3a5182 2500 signed char sl,tl;
cf95b4f0 2501 tl=get_reg(i_regs->regmap,dops[i].rt1);
2502 sl=get_reg(i_regs->regmap,dops[i].rs1);
57871462 2503 if(tl>=0) {
cf95b4f0 2504 if(dops[i].rs1) {
57871462 2505 assert(sl>=0);
7c3a5182 2506 emit_addimm(sl,imm[i],tl);
57871462 2507 } else {
2508 emit_movimm(imm[i],tl);
57871462 2509 }
2510 }
2511 }
2512 }
cf95b4f0 2513 else if(dops[i].opcode==0x0a||dops[i].opcode==0x0b) { // SLTI/SLTIU
2514 if(dops[i].rt1) {
2515 //assert(dops[i].rs1!=0); // r0 might be valid, but it's probably a bug
ad49de89 2516 signed char sl,t;
cf95b4f0 2517 t=get_reg(i_regs->regmap,dops[i].rt1);
2518 sl=get_reg(i_regs->regmap,dops[i].rs1);
57871462 2519 //assert(t>=0);
2520 if(t>=0) {
cf95b4f0 2521 if(dops[i].rs1>0) {
2522 if(dops[i].opcode==0x0a) { // SLTI
57871462 2523 if(sl<0) {
cf95b4f0 2524 if(i_regs->regmap_entry[t]!=dops[i].rs1) emit_loadreg(dops[i].rs1,t);
57871462 2525 emit_slti32(t,imm[i],t);
2526 }else{
2527 emit_slti32(sl,imm[i],t);
2528 }
2529 }
2530 else { // SLTIU
2531 if(sl<0) {
cf95b4f0 2532 if(i_regs->regmap_entry[t]!=dops[i].rs1) emit_loadreg(dops[i].rs1,t);
57871462 2533 emit_sltiu32(t,imm[i],t);
2534 }else{
2535 emit_sltiu32(sl,imm[i],t);
2536 }
2537 }
57871462 2538 }else{
2539 // SLTI(U) with r0 is just stupid,
2540 // nonetheless examples can be found
cf95b4f0 2541 if(dops[i].opcode==0x0a) // SLTI
57871462 2542 if(0<imm[i]) emit_movimm(1,t);
2543 else emit_zeroreg(t);
2544 else // SLTIU
2545 {
2546 if(imm[i]) emit_movimm(1,t);
2547 else emit_zeroreg(t);
2548 }
2549 }
2550 }
2551 }
2552 }
cf95b4f0 2553 else if(dops[i].opcode>=0x0c&&dops[i].opcode<=0x0e) { // ANDI/ORI/XORI
2554 if(dops[i].rt1) {
7c3a5182 2555 signed char sl,tl;
cf95b4f0 2556 tl=get_reg(i_regs->regmap,dops[i].rt1);
2557 sl=get_reg(i_regs->regmap,dops[i].rs1);
57871462 2558 if(tl>=0 && !((i_regs->isconst>>tl)&1)) {
cf95b4f0 2559 if(dops[i].opcode==0x0c) //ANDI
57871462 2560 {
cf95b4f0 2561 if(dops[i].rs1) {
57871462 2562 if(sl<0) {
cf95b4f0 2563 if(i_regs->regmap_entry[tl]!=dops[i].rs1) emit_loadreg(dops[i].rs1,tl);
57871462 2564 emit_andimm(tl,imm[i],tl);
2565 }else{
2566 if(!((i_regs->wasconst>>sl)&1))
2567 emit_andimm(sl,imm[i],tl);
2568 else
2569 emit_movimm(constmap[i][sl]&imm[i],tl);
2570 }
2571 }
2572 else
2573 emit_zeroreg(tl);
57871462 2574 }
2575 else
2576 {
cf95b4f0 2577 if(dops[i].rs1) {
57871462 2578 if(sl<0) {
cf95b4f0 2579 if(i_regs->regmap_entry[tl]!=dops[i].rs1) emit_loadreg(dops[i].rs1,tl);
57871462 2580 }
cf95b4f0 2581 if(dops[i].opcode==0x0d) { // ORI
581335b0 2582 if(sl<0) {
2583 emit_orimm(tl,imm[i],tl);
2584 }else{
2585 if(!((i_regs->wasconst>>sl)&1))
2586 emit_orimm(sl,imm[i],tl);
2587 else
2588 emit_movimm(constmap[i][sl]|imm[i],tl);
2589 }
57871462 2590 }
cf95b4f0 2591 if(dops[i].opcode==0x0e) { // XORI
581335b0 2592 if(sl<0) {
2593 emit_xorimm(tl,imm[i],tl);
2594 }else{
2595 if(!((i_regs->wasconst>>sl)&1))
2596 emit_xorimm(sl,imm[i],tl);
2597 else
2598 emit_movimm(constmap[i][sl]^imm[i],tl);
2599 }
57871462 2600 }
2601 }
2602 else {
2603 emit_movimm(imm[i],tl);
57871462 2604 }
2605 }
2606 }
2607 }
2608 }
2609}
2610
2330734f 2611static void shiftimm_assemble(int i, const struct regstat *i_regs)
57871462 2612{
cf95b4f0 2613 if(dops[i].opcode2<=0x3) // SLL/SRL/SRA
57871462 2614 {
cf95b4f0 2615 if(dops[i].rt1) {
57871462 2616 signed char s,t;
cf95b4f0 2617 t=get_reg(i_regs->regmap,dops[i].rt1);
2618 s=get_reg(i_regs->regmap,dops[i].rs1);
57871462 2619 //assert(t>=0);
dc49e339 2620 if(t>=0&&!((i_regs->isconst>>t)&1)){
cf95b4f0 2621 if(dops[i].rs1==0)
57871462 2622 {
2623 emit_zeroreg(t);
2624 }
2625 else
2626 {
cf95b4f0 2627 if(s<0&&i_regs->regmap_entry[t]!=dops[i].rs1) emit_loadreg(dops[i].rs1,t);
57871462 2628 if(imm[i]) {
cf95b4f0 2629 if(dops[i].opcode2==0) // SLL
57871462 2630 {
2631 emit_shlimm(s<0?t:s,imm[i],t);
2632 }
cf95b4f0 2633 if(dops[i].opcode2==2) // SRL
57871462 2634 {
2635 emit_shrimm(s<0?t:s,imm[i],t);
2636 }
cf95b4f0 2637 if(dops[i].opcode2==3) // SRA
57871462 2638 {
2639 emit_sarimm(s<0?t:s,imm[i],t);
2640 }
2641 }else{
2642 // Shift by zero
2643 if(s>=0 && s!=t) emit_mov(s,t);
2644 }
2645 }
2646 }
cf95b4f0 2647 //emit_storereg(dops[i].rt1,t); //DEBUG
57871462 2648 }
2649 }
cf95b4f0 2650 if(dops[i].opcode2>=0x38&&dops[i].opcode2<=0x3b) // DSLL/DSRL/DSRA
57871462 2651 {
9c45ca93 2652 assert(0);
57871462 2653 }
cf95b4f0 2654 if(dops[i].opcode2==0x3c) // DSLL32
57871462 2655 {
9c45ca93 2656 assert(0);
57871462 2657 }
cf95b4f0 2658 if(dops[i].opcode2==0x3e) // DSRL32
57871462 2659 {
9c45ca93 2660 assert(0);
57871462 2661 }
cf95b4f0 2662 if(dops[i].opcode2==0x3f) // DSRA32
57871462 2663 {
9c45ca93 2664 assert(0);
57871462 2665 }
2666}
2667
2668#ifndef shift_assemble
2330734f 2669static void shift_assemble(int i, const struct regstat *i_regs)
57871462 2670{
3968e69e 2671 signed char s,t,shift;
cf95b4f0 2672 if (dops[i].rt1 == 0)
3968e69e 2673 return;
cf95b4f0 2674 assert(dops[i].opcode2<=0x07); // SLLV/SRLV/SRAV
2675 t = get_reg(i_regs->regmap, dops[i].rt1);
2676 s = get_reg(i_regs->regmap, dops[i].rs1);
2677 shift = get_reg(i_regs->regmap, dops[i].rs2);
3968e69e 2678 if (t < 0)
2679 return;
2680
cf95b4f0 2681 if(dops[i].rs1==0)
3968e69e 2682 emit_zeroreg(t);
cf95b4f0 2683 else if(dops[i].rs2==0) {
3968e69e 2684 assert(s>=0);
2685 if(s!=t) emit_mov(s,t);
2686 }
2687 else {
2688 host_tempreg_acquire();
2689 emit_andimm(shift,31,HOST_TEMPREG);
cf95b4f0 2690 switch(dops[i].opcode2) {
3968e69e 2691 case 4: // SLLV
2692 emit_shl(s,HOST_TEMPREG,t);
2693 break;
2694 case 6: // SRLV
2695 emit_shr(s,HOST_TEMPREG,t);
2696 break;
2697 case 7: // SRAV
2698 emit_sar(s,HOST_TEMPREG,t);
2699 break;
2700 default:
2701 assert(0);
2702 }
2703 host_tempreg_release();
2704 }
57871462 2705}
3968e69e 2706
57871462 2707#endif
2708
8062d65a 2709enum {
2710 MTYPE_8000 = 0,
2711 MTYPE_8020,
2712 MTYPE_0000,
2713 MTYPE_A000,
2714 MTYPE_1F80,
2715};
2716
2717static int get_ptr_mem_type(u_int a)
2718{
2719 if(a < 0x00200000) {
2720 if(a<0x1000&&((start>>20)==0xbfc||(start>>24)==0xa0))
2721 // return wrong, must use memhandler for BIOS self-test to pass
2722 // 007 does similar stuff from a00 mirror, weird stuff
2723 return MTYPE_8000;
2724 return MTYPE_0000;
2725 }
2726 if(0x1f800000 <= a && a < 0x1f801000)
2727 return MTYPE_1F80;
2728 if(0x80200000 <= a && a < 0x80800000)
2729 return MTYPE_8020;
2730 if(0xa0000000 <= a && a < 0xa0200000)
2731 return MTYPE_A000;
2732 return MTYPE_8000;
2733}
2734
37387d8b 2735static int get_ro_reg(const struct regstat *i_regs, int host_tempreg_free)
2736{
2737 int r = get_reg(i_regs->regmap, ROREG);
2738 if (r < 0 && host_tempreg_free) {
2739 host_tempreg_acquire();
2740 emit_loadreg(ROREG, r = HOST_TEMPREG);
2741 }
2742 if (r < 0)
2743 abort();
2744 return r;
2745}
2746
2747static void *emit_fastpath_cmp_jump(int i, const struct regstat *i_regs,
2748 int addr, int *offset_reg, int *addr_reg_override)
8062d65a 2749{
2750 void *jaddr = NULL;
37387d8b 2751 int type = 0;
2752 int mr = dops[i].rs1;
2753 *offset_reg = -1;
8062d65a 2754 if(((smrv_strong|smrv_weak)>>mr)&1) {
2755 type=get_ptr_mem_type(smrv[mr]);
2756 //printf("set %08x @%08x r%d %d\n", smrv[mr], start+i*4, mr, type);
2757 }
2758 else {
2759 // use the mirror we are running on
2760 type=get_ptr_mem_type(start);
2761 //printf("set nospec @%08x r%d %d\n", start+i*4, mr, type);
2762 }
2763
2764 if(type==MTYPE_8020) { // RAM 80200000+ mirror
d1e4ebd9 2765 host_tempreg_acquire();
8062d65a 2766 emit_andimm(addr,~0x00e00000,HOST_TEMPREG);
2767 addr=*addr_reg_override=HOST_TEMPREG;
2768 type=0;
2769 }
2770 else if(type==MTYPE_0000) { // RAM 0 mirror
d1e4ebd9 2771 host_tempreg_acquire();
8062d65a 2772 emit_orimm(addr,0x80000000,HOST_TEMPREG);
2773 addr=*addr_reg_override=HOST_TEMPREG;
2774 type=0;
2775 }
2776 else if(type==MTYPE_A000) { // RAM A mirror
d1e4ebd9 2777 host_tempreg_acquire();
8062d65a 2778 emit_andimm(addr,~0x20000000,HOST_TEMPREG);
2779 addr=*addr_reg_override=HOST_TEMPREG;
2780 type=0;
2781 }
2782 else if(type==MTYPE_1F80) { // scratchpad
2783 if (psxH == (void *)0x1f800000) {
d1e4ebd9 2784 host_tempreg_acquire();
3968e69e 2785 emit_xorimm(addr,0x1f800000,HOST_TEMPREG);
8062d65a 2786 emit_cmpimm(HOST_TEMPREG,0x1000);
d1e4ebd9 2787 host_tempreg_release();
8062d65a 2788 jaddr=out;
2789 emit_jc(0);
2790 }
2791 else {
2792 // do the usual RAM check, jump will go to the right handler
2793 type=0;
2794 }
2795 }
2796
37387d8b 2797 if (type == 0) // need ram check
8062d65a 2798 {
2799 emit_cmpimm(addr,RAM_SIZE);
37387d8b 2800 jaddr = out;
8062d65a 2801 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
2802 // Hint to branch predictor that the branch is unlikely to be taken
37387d8b 2803 if (dops[i].rs1 >= 28)
8062d65a 2804 emit_jno_unlikely(0);
2805 else
2806 #endif
2807 emit_jno(0);
37387d8b 2808 if (ram_offset != 0)
2809 *offset_reg = get_ro_reg(i_regs, 0);
8062d65a 2810 }
2811
2812 return jaddr;
2813}
2814
687b4580 2815// return memhandler, or get directly accessable address and return 0
2816static void *get_direct_memhandler(void *table, u_int addr,
2817 enum stub_type type, uintptr_t *addr_host)
2818{
c979e8c2 2819 uintptr_t msb = 1ull << (sizeof(uintptr_t)*8 - 1);
687b4580 2820 uintptr_t l1, l2 = 0;
2821 l1 = ((uintptr_t *)table)[addr>>12];
c979e8c2 2822 if (!(l1 & msb)) {
687b4580 2823 uintptr_t v = l1 << 1;
2824 *addr_host = v + addr;
2825 return NULL;
2826 }
2827 else {
2828 l1 <<= 1;
2829 if (type == LOADB_STUB || type == LOADBU_STUB || type == STOREB_STUB)
2830 l2 = ((uintptr_t *)l1)[0x1000/4 + 0x1000/2 + (addr&0xfff)];
2831 else if (type == LOADH_STUB || type == LOADHU_STUB || type == STOREH_STUB)
c979e8c2 2832 l2 = ((uintptr_t *)l1)[0x1000/4 + (addr&0xfff)/2];
687b4580 2833 else
c979e8c2 2834 l2 = ((uintptr_t *)l1)[(addr&0xfff)/4];
2835 if (!(l2 & msb)) {
687b4580 2836 uintptr_t v = l2 << 1;
2837 *addr_host = v + (addr&0xfff);
2838 return NULL;
2839 }
2840 return (void *)(l2 << 1);
2841 }
2842}
2843
81dbbf4c 2844static u_int get_host_reglist(const signed char *regmap)
2845{
2846 u_int reglist = 0, hr;
2847 for (hr = 0; hr < HOST_REGS; hr++) {
2848 if (hr != EXCLUDE_REG && regmap[hr] >= 0)
2849 reglist |= 1 << hr;
2850 }
2851 return reglist;
2852}
2853
2854static u_int reglist_exclude(u_int reglist, int r1, int r2)
2855{
2856 if (r1 >= 0)
2857 reglist &= ~(1u << r1);
2858 if (r2 >= 0)
2859 reglist &= ~(1u << r2);
2860 return reglist;
2861}
2862
e3c6bdb5 2863// find a temp caller-saved register not in reglist (so assumed to be free)
2864static int reglist_find_free(u_int reglist)
2865{
2866 u_int free_regs = ~reglist & CALLER_SAVE_REGS;
2867 if (free_regs == 0)
2868 return -1;
2869 return __builtin_ctz(free_regs);
2870}
2871
37387d8b 2872static void do_load_word(int a, int rt, int offset_reg)
2873{
2874 if (offset_reg >= 0)
2875 emit_ldr_dualindexed(offset_reg, a, rt);
2876 else
2877 emit_readword_indexed(0, a, rt);
2878}
2879
2880static void do_store_word(int a, int ofs, int rt, int offset_reg, int preseve_a)
2881{
2882 if (offset_reg < 0) {
2883 emit_writeword_indexed(rt, ofs, a);
2884 return;
2885 }
2886 if (ofs != 0)
2887 emit_addimm(a, ofs, a);
2888 emit_str_dualindexed(offset_reg, a, rt);
2889 if (ofs != 0 && preseve_a)
2890 emit_addimm(a, -ofs, a);
2891}
2892
2893static void do_store_hword(int a, int ofs, int rt, int offset_reg, int preseve_a)
2894{
2895 if (offset_reg < 0) {
2896 emit_writehword_indexed(rt, ofs, a);
2897 return;
2898 }
2899 if (ofs != 0)
2900 emit_addimm(a, ofs, a);
2901 emit_strh_dualindexed(offset_reg, a, rt);
2902 if (ofs != 0 && preseve_a)
2903 emit_addimm(a, -ofs, a);
2904}
2905
2906static void do_store_byte(int a, int rt, int offset_reg)
2907{
2908 if (offset_reg >= 0)
2909 emit_strb_dualindexed(offset_reg, a, rt);
2910 else
2911 emit_writebyte_indexed(rt, 0, a);
2912}
2913
2330734f 2914static void load_assemble(int i, const struct regstat *i_regs, int ccadj_)
57871462 2915{
7c3a5182 2916 int s,tl,addr;
57871462 2917 int offset;
b14b6a8f 2918 void *jaddr=0;
5bf843dc 2919 int memtarget=0,c=0;
37387d8b 2920 int offset_reg = -1;
2921 int fastio_reg_override = -1;
81dbbf4c 2922 u_int reglist=get_host_reglist(i_regs->regmap);
cf95b4f0 2923 tl=get_reg(i_regs->regmap,dops[i].rt1);
2924 s=get_reg(i_regs->regmap,dops[i].rs1);
57871462 2925 offset=imm[i];
57871462 2926 if(i_regs->regmap[HOST_CCREG]==CCREG) reglist&=~(1<<HOST_CCREG);
2927 if(s>=0) {
2928 c=(i_regs->wasconst>>s)&1;
af4ee1fe 2929 if (c) {
2930 memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
af4ee1fe 2931 }
57871462 2932 }
57871462 2933 //printf("load_assemble: c=%d\n",c);
643aeae3 2934 //if(c) printf("load_assemble: const=%lx\n",(long)constmap[i][s]+offset);
57871462 2935 // FIXME: Even if the load is a NOP, we should check for pagefaults...
581335b0 2936 if((tl<0&&(!c||(((u_int)constmap[i][s]+offset)>>16)==0x1f80))
cf95b4f0 2937 ||dops[i].rt1==0) {
5bf843dc 2938 // could be FIFO, must perform the read
f18c0f46 2939 // ||dummy read
5bf843dc 2940 assem_debug("(forced read)\n");
9de8a0c3 2941 tl=get_reg_temp(i_regs->regmap);
5bf843dc 2942 assert(tl>=0);
5bf843dc 2943 }
2944 if(offset||s<0||c) addr=tl;
2945 else addr=s;
9de8a0c3 2946 //if(tl<0) tl=get_reg_temp(i_regs->regmap);
535d208a 2947 if(tl>=0) {
2948 //printf("load_assemble: c=%d\n",c);
643aeae3 2949 //if(c) printf("load_assemble: const=%lx\n",(long)constmap[i][s]+offset);
535d208a 2950 assert(tl>=0); // Even if the load is a NOP, we must check for pagefaults and I/O
2951 reglist&=~(1<<tl);
1edfcc68 2952 if(!c) {
1edfcc68 2953 #ifdef R29_HACK
2954 // Strmnnrmn's speed hack
cf95b4f0 2955 if(dops[i].rs1!=29||start<0x80001000||start>=0x80000000+RAM_SIZE)
1edfcc68 2956 #endif
2957 {
37387d8b 2958 jaddr = emit_fastpath_cmp_jump(i, i_regs, addr,
2959 &offset_reg, &fastio_reg_override);
535d208a 2960 }
1edfcc68 2961 }
37387d8b 2962 else if (ram_offset && memtarget) {
2963 offset_reg = get_ro_reg(i_regs, 0);
535d208a 2964 }
cf95b4f0 2965 int dummy=(dops[i].rt1==0)||(tl!=get_reg(i_regs->regmap,dops[i].rt1)); // ignore loads to r0 and unneeded reg
37387d8b 2966 switch (dops[i].opcode) {
2967 case 0x20: // LB
535d208a 2968 if(!c||memtarget) {
2969 if(!dummy) {
37387d8b 2970 int a = tl;
2971 if (!c) a = addr;
2972 if (fastio_reg_override >= 0)
2973 a = fastio_reg_override;
b1570849 2974
37387d8b 2975 if (offset_reg >= 0)
2976 emit_ldrsb_dualindexed(offset_reg, a, tl);
2977 else
2978 emit_movsbl_indexed(0, a, tl);
57871462 2979 }
535d208a 2980 if(jaddr)
2330734f 2981 add_stub_r(LOADB_STUB,jaddr,out,i,addr,i_regs,ccadj_,reglist);
57871462 2982 }
535d208a 2983 else
2330734f 2984 inline_readstub(LOADB_STUB,i,constmap[i][s]+offset,i_regs->regmap,dops[i].rt1,ccadj_,reglist);
37387d8b 2985 break;
2986 case 0x21: // LH
535d208a 2987 if(!c||memtarget) {
2988 if(!dummy) {
37387d8b 2989 int a = tl;
2990 if (!c) a = addr;
2991 if (fastio_reg_override >= 0)
2992 a = fastio_reg_override;
2993 if (offset_reg >= 0)
2994 emit_ldrsh_dualindexed(offset_reg, a, tl);
2995 else
2996 emit_movswl_indexed(0, a, tl);
57871462 2997 }
535d208a 2998 if(jaddr)
2330734f 2999 add_stub_r(LOADH_STUB,jaddr,out,i,addr,i_regs,ccadj_,reglist);
57871462 3000 }
535d208a 3001 else
2330734f 3002 inline_readstub(LOADH_STUB,i,constmap[i][s]+offset,i_regs->regmap,dops[i].rt1,ccadj_,reglist);
37387d8b 3003 break;
3004 case 0x23: // LW
535d208a 3005 if(!c||memtarget) {
3006 if(!dummy) {
37387d8b 3007 int a = addr;
3008 if (fastio_reg_override >= 0)
3009 a = fastio_reg_override;
3010 do_load_word(a, tl, offset_reg);
57871462 3011 }
535d208a 3012 if(jaddr)
2330734f 3013 add_stub_r(LOADW_STUB,jaddr,out,i,addr,i_regs,ccadj_,reglist);
57871462 3014 }
535d208a 3015 else
2330734f 3016 inline_readstub(LOADW_STUB,i,constmap[i][s]+offset,i_regs->regmap,dops[i].rt1,ccadj_,reglist);
37387d8b 3017 break;
3018 case 0x24: // LBU
535d208a 3019 if(!c||memtarget) {
3020 if(!dummy) {
37387d8b 3021 int a = tl;
3022 if (!c) a = addr;
3023 if (fastio_reg_override >= 0)
3024 a = fastio_reg_override;
b1570849 3025
37387d8b 3026 if (offset_reg >= 0)
3027 emit_ldrb_dualindexed(offset_reg, a, tl);
3028 else
3029 emit_movzbl_indexed(0, a, tl);
57871462 3030 }
535d208a 3031 if(jaddr)
2330734f 3032 add_stub_r(LOADBU_STUB,jaddr,out,i,addr,i_regs,ccadj_,reglist);
57871462 3033 }
535d208a 3034 else
2330734f 3035 inline_readstub(LOADBU_STUB,i,constmap[i][s]+offset,i_regs->regmap,dops[i].rt1,ccadj_,reglist);
37387d8b 3036 break;
3037 case 0x25: // LHU
535d208a 3038 if(!c||memtarget) {
3039 if(!dummy) {
37387d8b 3040 int a = tl;
3041 if(!c) a = addr;
3042 if (fastio_reg_override >= 0)
3043 a = fastio_reg_override;
3044 if (offset_reg >= 0)
3045 emit_ldrh_dualindexed(offset_reg, a, tl);
3046 else
3047 emit_movzwl_indexed(0, a, tl);
57871462 3048 }
535d208a 3049 if(jaddr)
2330734f 3050 add_stub_r(LOADHU_STUB,jaddr,out,i,addr,i_regs,ccadj_,reglist);
57871462 3051 }
535d208a 3052 else
2330734f 3053 inline_readstub(LOADHU_STUB,i,constmap[i][s]+offset,i_regs->regmap,dops[i].rt1,ccadj_,reglist);
37387d8b 3054 break;
3055 case 0x27: // LWU
3056 case 0x37: // LD
3057 default:
9c45ca93 3058 assert(0);
57871462 3059 }
535d208a 3060 }
37387d8b 3061 if (fastio_reg_override == HOST_TEMPREG || offset_reg == HOST_TEMPREG)
d1e4ebd9 3062 host_tempreg_release();
57871462 3063}
3064
3065#ifndef loadlr_assemble
2330734f 3066static void loadlr_assemble(int i, const struct regstat *i_regs, int ccadj_)
57871462 3067{
3968e69e 3068 int s,tl,temp,temp2,addr;
3069 int offset;
3070 void *jaddr=0;
3071 int memtarget=0,c=0;
37387d8b 3072 int offset_reg = -1;
3073 int fastio_reg_override = -1;
81dbbf4c 3074 u_int reglist=get_host_reglist(i_regs->regmap);
cf95b4f0 3075 tl=get_reg(i_regs->regmap,dops[i].rt1);
3076 s=get_reg(i_regs->regmap,dops[i].rs1);
9de8a0c3 3077 temp=get_reg_temp(i_regs->regmap);
3968e69e 3078 temp2=get_reg(i_regs->regmap,FTEMP);
3079 addr=get_reg(i_regs->regmap,AGEN1+(i&1));
3080 assert(addr<0);
3081 offset=imm[i];
3968e69e 3082 reglist|=1<<temp;
3083 if(offset||s<0||c) addr=temp2;
3084 else addr=s;
3085 if(s>=0) {
3086 c=(i_regs->wasconst>>s)&1;
3087 if(c) {
3088 memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
3089 }
3090 }
3091 if(!c) {
3092 emit_shlimm(addr,3,temp);
cf95b4f0 3093 if (dops[i].opcode==0x22||dops[i].opcode==0x26) {
3968e69e 3094 emit_andimm(addr,0xFFFFFFFC,temp2); // LWL/LWR
3095 }else{
3096 emit_andimm(addr,0xFFFFFFF8,temp2); // LDL/LDR
3097 }
37387d8b 3098 jaddr = emit_fastpath_cmp_jump(i, i_regs, temp2,
3099 &offset_reg, &fastio_reg_override);
3968e69e 3100 }
3101 else {
37387d8b 3102 if (ram_offset && memtarget) {
3103 offset_reg = get_ro_reg(i_regs, 0);
3968e69e 3104 }
cf95b4f0 3105 if (dops[i].opcode==0x22||dops[i].opcode==0x26) {
3968e69e 3106 emit_movimm(((constmap[i][s]+offset)<<3)&24,temp); // LWL/LWR
3107 }else{
3108 emit_movimm(((constmap[i][s]+offset)<<3)&56,temp); // LDL/LDR
3109 }
3110 }
cf95b4f0 3111 if (dops[i].opcode==0x22||dops[i].opcode==0x26) { // LWL/LWR
3968e69e 3112 if(!c||memtarget) {
37387d8b 3113 int a = temp2;
3114 if (fastio_reg_override >= 0)
3115 a = fastio_reg_override;
3116 do_load_word(a, temp2, offset_reg);
3117 if (fastio_reg_override == HOST_TEMPREG || offset_reg == HOST_TEMPREG)
3118 host_tempreg_release();
2330734f 3119 if(jaddr) add_stub_r(LOADW_STUB,jaddr,out,i,temp2,i_regs,ccadj_,reglist);
3968e69e 3120 }
3121 else
2330734f 3122 inline_readstub(LOADW_STUB,i,(constmap[i][s]+offset)&0xFFFFFFFC,i_regs->regmap,FTEMP,ccadj_,reglist);
cf95b4f0 3123 if(dops[i].rt1) {
3968e69e 3124 assert(tl>=0);
3125 emit_andimm(temp,24,temp);
cf95b4f0 3126 if (dops[i].opcode==0x22) // LWL
3968e69e 3127 emit_xorimm(temp,24,temp);
3128 host_tempreg_acquire();
3129 emit_movimm(-1,HOST_TEMPREG);
cf95b4f0 3130 if (dops[i].opcode==0x26) {
3968e69e 3131 emit_shr(temp2,temp,temp2);
3132 emit_bic_lsr(tl,HOST_TEMPREG,temp,tl);
3133 }else{
3134 emit_shl(temp2,temp,temp2);
3135 emit_bic_lsl(tl,HOST_TEMPREG,temp,tl);
3136 }
3137 host_tempreg_release();
3138 emit_or(temp2,tl,tl);
3139 }
cf95b4f0 3140 //emit_storereg(dops[i].rt1,tl); // DEBUG
3968e69e 3141 }
cf95b4f0 3142 if (dops[i].opcode==0x1A||dops[i].opcode==0x1B) { // LDL/LDR
3968e69e 3143 assert(0);
3144 }
57871462 3145}
3146#endif
3147
2330734f 3148static void store_assemble(int i, const struct regstat *i_regs, int ccadj_)
57871462 3149{
9c45ca93 3150 int s,tl;
57871462 3151 int addr,temp;
3152 int offset;
b14b6a8f 3153 void *jaddr=0;
37387d8b 3154 enum stub_type type=0;
666a299d 3155 int memtarget=0,c=0;
57871462 3156 int agr=AGEN1+(i&1);
37387d8b 3157 int offset_reg = -1;
3158 int fastio_reg_override = -1;
81dbbf4c 3159 u_int reglist=get_host_reglist(i_regs->regmap);
cf95b4f0 3160 tl=get_reg(i_regs->regmap,dops[i].rs2);
3161 s=get_reg(i_regs->regmap,dops[i].rs1);
57871462 3162 temp=get_reg(i_regs->regmap,agr);
9de8a0c3 3163 if(temp<0) temp=get_reg_temp(i_regs->regmap);
57871462 3164 offset=imm[i];
3165 if(s>=0) {
3166 c=(i_regs->wasconst>>s)&1;
af4ee1fe 3167 if(c) {
3168 memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
af4ee1fe 3169 }
57871462 3170 }
3171 assert(tl>=0);
3172 assert(temp>=0);
57871462 3173 if(i_regs->regmap[HOST_CCREG]==CCREG) reglist&=~(1<<HOST_CCREG);
3174 if(offset||s<0||c) addr=temp;
3175 else addr=s;
37387d8b 3176 if (!c) {
3177 jaddr = emit_fastpath_cmp_jump(i, i_regs, addr,
3178 &offset_reg, &fastio_reg_override);
1edfcc68 3179 }
37387d8b 3180 else if (ram_offset && memtarget) {
3181 offset_reg = get_ro_reg(i_regs, 0);
57871462 3182 }
3183
37387d8b 3184 switch (dops[i].opcode) {
3185 case 0x28: // SB
57871462 3186 if(!c||memtarget) {
37387d8b 3187 int a = temp;
3188 if (!c) a = addr;
3189 if (fastio_reg_override >= 0)
3190 a = fastio_reg_override;
3191 do_store_byte(a, tl, offset_reg);
3192 }
3193 type = STOREB_STUB;
3194 break;
3195 case 0x29: // SH
57871462 3196 if(!c||memtarget) {
37387d8b 3197 int a = temp;
3198 if (!c) a = addr;
3199 if (fastio_reg_override >= 0)
3200 a = fastio_reg_override;
3201 do_store_hword(a, 0, tl, offset_reg, 1);
3202 }
3203 type = STOREH_STUB;
3204 break;
3205 case 0x2B: // SW
dadf55f2 3206 if(!c||memtarget) {
37387d8b 3207 int a = addr;
3208 if (fastio_reg_override >= 0)
3209 a = fastio_reg_override;
3210 do_store_word(a, 0, tl, offset_reg, 1);
3211 }
3212 type = STOREW_STUB;
3213 break;
3214 case 0x3F: // SD
3215 default:
9c45ca93 3216 assert(0);
57871462 3217 }
37387d8b 3218 if (fastio_reg_override == HOST_TEMPREG || offset_reg == HOST_TEMPREG)
d1e4ebd9 3219 host_tempreg_release();
b96d3df7 3220 if(jaddr) {
3221 // PCSX store handlers don't check invcode again
3222 reglist|=1<<addr;
2330734f 3223 add_stub_r(type,jaddr,out,i,addr,i_regs,ccadj_,reglist);
b96d3df7 3224 jaddr=0;
3225 }
cf95b4f0 3226 if(!(i_regs->waswritten&(1<<dops[i].rs1)) && !HACK_ENABLED(NDHACK_NO_SMC_CHECK)) {
57871462 3227 if(!c||memtarget) {
3228 #ifdef DESTRUCTIVE_SHIFT
3229 // The x86 shift operation is 'destructive'; it overwrites the
3230 // source register, so we need to make a copy first and use that.
3231 addr=temp;
3232 #endif
3233 #if defined(HOST_IMM8)
3234 int ir=get_reg(i_regs->regmap,INVCP);
3235 assert(ir>=0);
3236 emit_cmpmem_indexedsr12_reg(ir,addr,1);
3237 #else
643aeae3 3238 emit_cmpmem_indexedsr12_imm(invalid_code,addr,1);
57871462 3239 #endif
882a08fc 3240 #ifdef INVALIDATE_USE_COND_CALL
0bbd1454 3241 emit_callne(invalidate_addr_reg[addr]);
3242 #else
b14b6a8f 3243 void *jaddr2 = out;
57871462 3244 emit_jne(0);
b14b6a8f 3245 add_stub(INVCODE_STUB,jaddr2,out,reglist|(1<<HOST_CCREG),addr,0,0,0);
0bbd1454 3246 #endif
57871462 3247 }
3248 }
7a518516 3249 u_int addr_val=constmap[i][s]+offset;
3eaa7048 3250 if(jaddr) {
2330734f 3251 add_stub_r(type,jaddr,out,i,addr,i_regs,ccadj_,reglist);
3eaa7048 3252 } else if(c&&!memtarget) {
2330734f 3253 inline_writestub(type,i,addr_val,i_regs->regmap,dops[i].rs2,ccadj_,reglist);
7a518516 3254 }
3255 // basic current block modification detection..
3256 // not looking back as that should be in mips cache already
3968e69e 3257 // (see Spyro2 title->attract mode)
7a518516 3258 if(c&&start+i*4<addr_val&&addr_val<start+slen*4) {
c43b5311 3259 SysPrintf("write to %08x hits block %08x, pc=%08x\n",addr_val,start,start+i*4);
7a518516 3260 assert(i_regs->regmap==regs[i].regmap); // not delay slot
3261 if(i_regs->regmap==regs[i].regmap) {
ad49de89 3262 load_all_consts(regs[i].regmap_entry,regs[i].wasdirty,i);
3263 wb_dirtys(regs[i].regmap_entry,regs[i].wasdirty);
7a518516 3264 emit_movimm(start+i*4+4,0);
643aeae3 3265 emit_writeword(0,&pcaddr);
d1e4ebd9 3266 emit_addimm(HOST_CCREG,2,HOST_CCREG);
104df9d3 3267 emit_far_call(ndrc_get_addr_ht);
d1e4ebd9 3268 emit_jmpreg(0);
7a518516 3269 }
3eaa7048 3270 }
57871462 3271}
3272
2330734f 3273static void storelr_assemble(int i, const struct regstat *i_regs, int ccadj_)
57871462 3274{
9c45ca93 3275 int s,tl;
57871462 3276 int temp;
57871462 3277 int offset;
b14b6a8f 3278 void *jaddr=0;
37387d8b 3279 void *case1, *case23, *case3;
df4dc2b1 3280 void *done0, *done1, *done2;
af4ee1fe 3281 int memtarget=0,c=0;
fab5d06d 3282 int agr=AGEN1+(i&1);
37387d8b 3283 int offset_reg = -1;
81dbbf4c 3284 u_int reglist=get_host_reglist(i_regs->regmap);
cf95b4f0 3285 tl=get_reg(i_regs->regmap,dops[i].rs2);
3286 s=get_reg(i_regs->regmap,dops[i].rs1);
fab5d06d 3287 temp=get_reg(i_regs->regmap,agr);
9de8a0c3 3288 if(temp<0) temp=get_reg_temp(i_regs->regmap);
57871462 3289 offset=imm[i];
3290 if(s>=0) {
3291 c=(i_regs->isconst>>s)&1;
af4ee1fe 3292 if(c) {
3293 memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
af4ee1fe 3294 }
57871462 3295 }
3296 assert(tl>=0);
535d208a 3297 assert(temp>=0);
1edfcc68 3298 if(!c) {
3299 emit_cmpimm(s<0||offset?temp:s,RAM_SIZE);
3300 if(!offset&&s!=temp) emit_mov(s,temp);
b14b6a8f 3301 jaddr=out;
1edfcc68 3302 emit_jno(0);
3303 }
3304 else
3305 {
cf95b4f0 3306 if(!memtarget||!dops[i].rs1) {
b14b6a8f 3307 jaddr=out;
535d208a 3308 emit_jmp(0);
57871462 3309 }
535d208a 3310 }
37387d8b 3311 if (ram_offset)
3312 offset_reg = get_ro_reg(i_regs, 0);
535d208a 3313
cf95b4f0 3314 if (dops[i].opcode==0x2C||dops[i].opcode==0x2D) { // SDL/SDR
9c45ca93 3315 assert(0);
535d208a 3316 }
57871462 3317
535d208a 3318 emit_testimm(temp,2);
37387d8b 3319 case23=out;
535d208a 3320 emit_jne(0);
3321 emit_testimm(temp,1);
df4dc2b1 3322 case1=out;
535d208a 3323 emit_jne(0);
3324 // 0
37387d8b 3325 if (dops[i].opcode == 0x2A) { // SWL
3326 // Write msb into least significant byte
3327 if (dops[i].rs2) emit_rorimm(tl, 24, tl);
3328 do_store_byte(temp, tl, offset_reg);
3329 if (dops[i].rs2) emit_rorimm(tl, 8, tl);
535d208a 3330 }
37387d8b 3331 else if (dops[i].opcode == 0x2E) { // SWR
3332 // Write entire word
3333 do_store_word(temp, 0, tl, offset_reg, 1);
535d208a 3334 }
37387d8b 3335 done0 = out;
535d208a 3336 emit_jmp(0);
3337 // 1
df4dc2b1 3338 set_jump_target(case1, out);
37387d8b 3339 if (dops[i].opcode == 0x2A) { // SWL
3340 // Write two msb into two least significant bytes
3341 if (dops[i].rs2) emit_rorimm(tl, 16, tl);
3342 do_store_hword(temp, -1, tl, offset_reg, 0);
3343 if (dops[i].rs2) emit_rorimm(tl, 16, tl);
535d208a 3344 }
37387d8b 3345 else if (dops[i].opcode == 0x2E) { // SWR
3346 // Write 3 lsb into three most significant bytes
3347 do_store_byte(temp, tl, offset_reg);
3348 if (dops[i].rs2) emit_rorimm(tl, 8, tl);
3349 do_store_hword(temp, 1, tl, offset_reg, 0);
3350 if (dops[i].rs2) emit_rorimm(tl, 24, tl);
535d208a 3351 }
df4dc2b1 3352 done1=out;
535d208a 3353 emit_jmp(0);
37387d8b 3354 // 2,3
3355 set_jump_target(case23, out);
535d208a 3356 emit_testimm(temp,1);
37387d8b 3357 case3 = out;
535d208a 3358 emit_jne(0);
37387d8b 3359 // 2
cf95b4f0 3360 if (dops[i].opcode==0x2A) { // SWL
37387d8b 3361 // Write 3 msb into three least significant bytes
3362 if (dops[i].rs2) emit_rorimm(tl, 8, tl);
3363 do_store_hword(temp, -2, tl, offset_reg, 1);
3364 if (dops[i].rs2) emit_rorimm(tl, 16, tl);
3365 do_store_byte(temp, tl, offset_reg);
3366 if (dops[i].rs2) emit_rorimm(tl, 8, tl);
535d208a 3367 }
37387d8b 3368 else if (dops[i].opcode == 0x2E) { // SWR
3369 // Write two lsb into two most significant bytes
3370 do_store_hword(temp, 0, tl, offset_reg, 1);
535d208a 3371 }
37387d8b 3372 done2 = out;
535d208a 3373 emit_jmp(0);
3374 // 3
df4dc2b1 3375 set_jump_target(case3, out);
37387d8b 3376 if (dops[i].opcode == 0x2A) { // SWL
3377 do_store_word(temp, -3, tl, offset_reg, 0);
535d208a 3378 }
37387d8b 3379 else if (dops[i].opcode == 0x2E) { // SWR
3380 do_store_byte(temp, tl, offset_reg);
535d208a 3381 }
df4dc2b1 3382 set_jump_target(done0, out);
3383 set_jump_target(done1, out);
3384 set_jump_target(done2, out);
37387d8b 3385 if (offset_reg == HOST_TEMPREG)
3386 host_tempreg_release();
535d208a 3387 if(!c||!memtarget)
2330734f 3388 add_stub_r(STORELR_STUB,jaddr,out,i,temp,i_regs,ccadj_,reglist);
cf95b4f0 3389 if(!(i_regs->waswritten&(1<<dops[i].rs1)) && !HACK_ENABLED(NDHACK_NO_SMC_CHECK)) {
57871462 3390 #if defined(HOST_IMM8)
3391 int ir=get_reg(i_regs->regmap,INVCP);
3392 assert(ir>=0);
3393 emit_cmpmem_indexedsr12_reg(ir,temp,1);
3394 #else
643aeae3 3395 emit_cmpmem_indexedsr12_imm(invalid_code,temp,1);
57871462 3396 #endif
882a08fc 3397 #ifdef INVALIDATE_USE_COND_CALL
535d208a 3398 emit_callne(invalidate_addr_reg[temp]);
3399 #else
b14b6a8f 3400 void *jaddr2 = out;
57871462 3401 emit_jne(0);
b14b6a8f 3402 add_stub(INVCODE_STUB,jaddr2,out,reglist|(1<<HOST_CCREG),temp,0,0,0);
535d208a 3403 #endif
57871462 3404 }
57871462 3405}
3406
2330734f 3407static void cop0_assemble(int i, const struct regstat *i_regs, int ccadj_)
8062d65a 3408{
cf95b4f0 3409 if(dops[i].opcode2==0) // MFC0
8062d65a 3410 {
cf95b4f0 3411 signed char t=get_reg(i_regs->regmap,dops[i].rt1);
8062d65a 3412 u_int copr=(source[i]>>11)&0x1f;
3413 //assert(t>=0); // Why does this happen? OOT is weird
cf95b4f0 3414 if(t>=0&&dops[i].rt1!=0) {
8062d65a 3415 emit_readword(&reg_cop0[copr],t);
3416 }
3417 }
cf95b4f0 3418 else if(dops[i].opcode2==4) // MTC0
8062d65a 3419 {
cf95b4f0 3420 signed char s=get_reg(i_regs->regmap,dops[i].rs1);
8062d65a 3421 char copr=(source[i]>>11)&0x1f;
3422 assert(s>=0);
cf95b4f0 3423 wb_register(dops[i].rs1,i_regs->regmap,i_regs->dirty);
8062d65a 3424 if(copr==9||copr==11||copr==12||copr==13) {
3425 emit_readword(&last_count,HOST_TEMPREG);
3426 emit_loadreg(CCREG,HOST_CCREG); // TODO: do proper reg alloc
3427 emit_add(HOST_CCREG,HOST_TEMPREG,HOST_CCREG);
2330734f 3428 emit_addimm(HOST_CCREG,ccadj_,HOST_CCREG);
8062d65a 3429 emit_writeword(HOST_CCREG,&Count);
3430 }
3431 // What a mess. The status register (12) can enable interrupts,
3432 // so needs a special case to handle a pending interrupt.
3433 // The interrupt must be taken immediately, because a subsequent
3434 // instruction might disable interrupts again.
3435 if(copr==12||copr==13) {
3436 if (is_delayslot) {
3437 // burn cycles to cause cc_interrupt, which will
3438 // reschedule next_interupt. Relies on CCREG from above.
3439 assem_debug("MTC0 DS %d\n", copr);
3440 emit_writeword(HOST_CCREG,&last_count);
3441 emit_movimm(0,HOST_CCREG);
3442 emit_storereg(CCREG,HOST_CCREG);
cf95b4f0 3443 emit_loadreg(dops[i].rs1,1);
8062d65a 3444 emit_movimm(copr,0);
2a014d73 3445 emit_far_call(pcsx_mtc0_ds);
cf95b4f0 3446 emit_loadreg(dops[i].rs1,s);
8062d65a 3447 return;
3448 }
3449 emit_movimm(start+i*4+4,HOST_TEMPREG);
3450 emit_writeword(HOST_TEMPREG,&pcaddr);
3451 emit_movimm(0,HOST_TEMPREG);
3452 emit_writeword(HOST_TEMPREG,&pending_exception);
3453 }
8062d65a 3454 if(s==HOST_CCREG)
cf95b4f0 3455 emit_loadreg(dops[i].rs1,1);
8062d65a 3456 else if(s!=1)
3457 emit_mov(s,1);
3458 emit_movimm(copr,0);
2a014d73 3459 emit_far_call(pcsx_mtc0);
8062d65a 3460 if(copr==9||copr==11||copr==12||copr==13) {
3461 emit_readword(&Count,HOST_CCREG);
3462 emit_readword(&next_interupt,HOST_TEMPREG);
2330734f 3463 emit_addimm(HOST_CCREG,-ccadj_,HOST_CCREG);
8062d65a 3464 emit_sub(HOST_CCREG,HOST_TEMPREG,HOST_CCREG);
3465 emit_writeword(HOST_TEMPREG,&last_count);
3466 emit_storereg(CCREG,HOST_CCREG);
3467 }
3468 if(copr==12||copr==13) {
3469 assert(!is_delayslot);
3470 emit_readword(&pending_exception,14);
3471 emit_test(14,14);
d1e4ebd9 3472 void *jaddr = out;
3473 emit_jeq(0);
3474 emit_readword(&pcaddr, 0);
3475 emit_addimm(HOST_CCREG,2,HOST_CCREG);
104df9d3 3476 emit_far_call(ndrc_get_addr_ht);
d1e4ebd9 3477 emit_jmpreg(0);
3478 set_jump_target(jaddr, out);
8062d65a 3479 }
cf95b4f0 3480 emit_loadreg(dops[i].rs1,s);
8062d65a 3481 }
3482 else
3483 {
cf95b4f0 3484 assert(dops[i].opcode2==0x10);
8062d65a 3485 //if((source[i]&0x3f)==0x10) // RFE
3486 {
3487 emit_readword(&Status,0);
3488 emit_andimm(0,0x3c,1);
3489 emit_andimm(0,~0xf,0);
3490 emit_orrshr_imm(1,2,0);
3491 emit_writeword(0,&Status);
3492 }
3493 }
3494}
3495
2330734f 3496static void cop1_unusable(int i, const struct regstat *i_regs)
8062d65a 3497{
3498 // XXX: should just just do the exception instead
3499 //if(!cop1_usable)
3500 {
3501 void *jaddr=out;
3502 emit_jmp(0);
3503 add_stub_r(FP_STUB,jaddr,out,i,0,i_regs,is_delayslot,0);
3504 }
3505}
3506
2330734f 3507static void cop1_assemble(int i, const struct regstat *i_regs)
8062d65a 3508{
3509 cop1_unusable(i, i_regs);
3510}
3511
2330734f 3512static void c1ls_assemble(int i, const struct regstat *i_regs)
57871462 3513{
3d624f89 3514 cop1_unusable(i, i_regs);
57871462 3515}
3516
8062d65a 3517// FP_STUB
3518static void do_cop1stub(int n)
3519{
3520 literal_pool(256);
3521 assem_debug("do_cop1stub %x\n",start+stubs[n].a*4);
3522 set_jump_target(stubs[n].addr, out);
3523 int i=stubs[n].a;
3524// int rs=stubs[n].b;
3525 struct regstat *i_regs=(struct regstat *)stubs[n].c;
3526 int ds=stubs[n].d;
3527 if(!ds) {
3528 load_all_consts(regs[i].regmap_entry,regs[i].wasdirty,i);
3529 //if(i_regs!=&regs[i]) printf("oops: regs[i]=%x i_regs=%x",(int)&regs[i],(int)i_regs);
3530 }
3531 //else {printf("fp exception in delay slot\n");}
3532 wb_dirtys(i_regs->regmap_entry,i_regs->wasdirty);
3533 if(regs[i].regmap_entry[HOST_CCREG]!=CCREG) emit_loadreg(CCREG,HOST_CCREG);
3534 emit_movimm(start+(i-ds)*4,EAX); // Get PC
2330734f 3535 emit_addimm(HOST_CCREG,ccadj[i],HOST_CCREG); // CHECK: is this right? There should probably be an extra cycle...
2a014d73 3536 emit_far_jump(ds?fp_exception_ds:fp_exception);
8062d65a 3537}
3538
e3c6bdb5 3539static int cop2_is_stalling_op(int i, int *cycles)
3540{
cf95b4f0 3541 if (dops[i].opcode == 0x3a) { // SWC2
e3c6bdb5 3542 *cycles = 0;
3543 return 1;
3544 }
cf95b4f0 3545 if (dops[i].itype == COP2 && (dops[i].opcode2 == 0 || dops[i].opcode2 == 2)) { // MFC2/CFC2
e3c6bdb5 3546 *cycles = 0;
3547 return 1;
3548 }
cf95b4f0 3549 if (dops[i].itype == C2OP) {
e3c6bdb5 3550 *cycles = gte_cycletab[source[i] & 0x3f];
3551 return 1;
3552 }
3553 // ... what about MTC2/CTC2/LWC2?
3554 return 0;
3555}
3556
3557#if 0
3558static void log_gte_stall(int stall, u_int cycle)
3559{
3560 if ((u_int)stall <= 44)
3561 printf("x stall %2d %u\n", stall, cycle + last_count);
e3c6bdb5 3562}
3563
3564static void emit_log_gte_stall(int i, int stall, u_int reglist)
3565{
3566 save_regs(reglist);
3567 if (stall > 0)
3568 emit_movimm(stall, 0);
3569 else
3570 emit_mov(HOST_TEMPREG, 0);
2330734f 3571 emit_addimm(HOST_CCREG, ccadj[i], 1);
e3c6bdb5 3572 emit_far_call(log_gte_stall);
3573 restore_regs(reglist);
3574}
3575#endif
3576
32631e6a 3577static void cop2_do_stall_check(u_int op, int i, const struct regstat *i_regs, u_int reglist)
81dbbf4c 3578{
e3c6bdb5 3579 int j = i, other_gte_op_cycles = -1, stall = -MAXBLOCK, cycles_passed;
3580 int rtmp = reglist_find_free(reglist);
3581
32631e6a 3582 if (HACK_ENABLED(NDHACK_NO_STALLS))
81dbbf4c 3583 return;
81dbbf4c 3584 if (get_reg(i_regs->regmap, CCREG) != HOST_CCREG) {
3585 // happens occasionally... cc evicted? Don't bother then
3586 //printf("no cc %08x\n", start + i*4);
3587 return;
3588 }
cf95b4f0 3589 if (!dops[i].bt) {
e3c6bdb5 3590 for (j = i - 1; j >= 0; j--) {
cf95b4f0 3591 //if (dops[j].is_ds) break;
3592 if (cop2_is_stalling_op(j, &other_gte_op_cycles) || dops[j].bt)
e3c6bdb5 3593 break;
2330734f 3594 if (j > 0 && ccadj[j - 1] > ccadj[j])
3595 break;
e3c6bdb5 3596 }
32631e6a 3597 j = max(j, 0);
e3c6bdb5 3598 }
2330734f 3599 cycles_passed = ccadj[i] - ccadj[j];
e3c6bdb5 3600 if (other_gte_op_cycles >= 0)
3601 stall = other_gte_op_cycles - cycles_passed;
3602 else if (cycles_passed >= 44)
3603 stall = 0; // can't stall
3604 if (stall == -MAXBLOCK && rtmp >= 0) {
3605 // unknown stall, do the expensive runtime check
32631e6a 3606 assem_debug("; cop2_do_stall_check\n");
e3c6bdb5 3607#if 0 // too slow
3608 save_regs(reglist);
3609 emit_movimm(gte_cycletab[op], 0);
2330734f 3610 emit_addimm(HOST_CCREG, ccadj[i], 1);
e3c6bdb5 3611 emit_far_call(call_gteStall);
3612 restore_regs(reglist);
3613#else
3614 host_tempreg_acquire();
3615 emit_readword(&psxRegs.gteBusyCycle, rtmp);
2330734f 3616 emit_addimm(rtmp, -ccadj[i], rtmp);
e3c6bdb5 3617 emit_sub(rtmp, HOST_CCREG, HOST_TEMPREG);
3618 emit_cmpimm(HOST_TEMPREG, 44);
3619 emit_cmovb_reg(rtmp, HOST_CCREG);
3620 //emit_log_gte_stall(i, 0, reglist);
3621 host_tempreg_release();
3622#endif
3623 }
3624 else if (stall > 0) {
3625 //emit_log_gte_stall(i, stall, reglist);
3626 emit_addimm(HOST_CCREG, stall, HOST_CCREG);
3627 }
3628
3629 // save gteBusyCycle, if needed
3630 if (gte_cycletab[op] == 0)
3631 return;
3632 other_gte_op_cycles = -1;
3633 for (j = i + 1; j < slen; j++) {
3634 if (cop2_is_stalling_op(j, &other_gte_op_cycles))
3635 break;
fe807a8a 3636 if (dops[j].is_jump) {
e3c6bdb5 3637 // check ds
3638 if (j + 1 < slen && cop2_is_stalling_op(j + 1, &other_gte_op_cycles))
3639 j++;
3640 break;
3641 }
3642 }
3643 if (other_gte_op_cycles >= 0)
3644 // will handle stall when assembling that op
3645 return;
2330734f 3646 cycles_passed = ccadj[min(j, slen -1)] - ccadj[i];
e3c6bdb5 3647 if (cycles_passed >= 44)
3648 return;
3649 assem_debug("; save gteBusyCycle\n");
3650 host_tempreg_acquire();
3651#if 0
3652 emit_readword(&last_count, HOST_TEMPREG);
3653 emit_add(HOST_TEMPREG, HOST_CCREG, HOST_TEMPREG);
2330734f 3654 emit_addimm(HOST_TEMPREG, ccadj[i], HOST_TEMPREG);
e3c6bdb5 3655 emit_addimm(HOST_TEMPREG, gte_cycletab[op]), HOST_TEMPREG);
3656 emit_writeword(HOST_TEMPREG, &psxRegs.gteBusyCycle);
3657#else
2330734f 3658 emit_addimm(HOST_CCREG, ccadj[i] + gte_cycletab[op], HOST_TEMPREG);
e3c6bdb5 3659 emit_writeword(HOST_TEMPREG, &psxRegs.gteBusyCycle);
3660#endif
3661 host_tempreg_release();
81dbbf4c 3662}
3663
32631e6a 3664static int is_mflohi(int i)
3665{
cf95b4f0 3666 return (dops[i].itype == MOV && (dops[i].rs1 == HIREG || dops[i].rs1 == LOREG));
32631e6a 3667}
3668
3669static int check_multdiv(int i, int *cycles)
3670{
cf95b4f0 3671 if (dops[i].itype != MULTDIV)
32631e6a 3672 return 0;
cf95b4f0 3673 if (dops[i].opcode2 == 0x18 || dops[i].opcode2 == 0x19) // MULT(U)
32631e6a 3674 *cycles = 11; // approx from 7 11 14
3675 else
3676 *cycles = 37;
3677 return 1;
3678}
3679
2330734f 3680static void multdiv_prepare_stall(int i, const struct regstat *i_regs, int ccadj_)
32631e6a 3681{
3682 int j, found = 0, c = 0;
3683 if (HACK_ENABLED(NDHACK_NO_STALLS))
3684 return;
3685 if (get_reg(i_regs->regmap, CCREG) != HOST_CCREG) {
3686 // happens occasionally... cc evicted? Don't bother then
3687 return;
3688 }
3689 for (j = i + 1; j < slen; j++) {
cf95b4f0 3690 if (dops[j].bt)
32631e6a 3691 break;
3692 if ((found = is_mflohi(j)))
3693 break;
fe807a8a 3694 if (dops[j].is_jump) {
32631e6a 3695 // check ds
3696 if (j + 1 < slen && (found = is_mflohi(j + 1)))
3697 j++;
3698 break;
3699 }
3700 }
3701 if (found)
3702 // handle all in multdiv_do_stall()
3703 return;
3704 check_multdiv(i, &c);
3705 assert(c > 0);
3706 assem_debug("; muldiv prepare stall %d\n", c);
3707 host_tempreg_acquire();
2330734f 3708 emit_addimm(HOST_CCREG, ccadj_ + c, HOST_TEMPREG);
32631e6a 3709 emit_writeword(HOST_TEMPREG, &psxRegs.muldivBusyCycle);
3710 host_tempreg_release();
3711}
3712
3713static void multdiv_do_stall(int i, const struct regstat *i_regs)
3714{
3715 int j, known_cycles = 0;
3716 u_int reglist = get_host_reglist(i_regs->regmap);
9de8a0c3 3717 int rtmp = get_reg_temp(i_regs->regmap);
32631e6a 3718 if (rtmp < 0)
3719 rtmp = reglist_find_free(reglist);
3720 if (HACK_ENABLED(NDHACK_NO_STALLS))
3721 return;
3722 if (get_reg(i_regs->regmap, CCREG) != HOST_CCREG || rtmp < 0) {
3723 // happens occasionally... cc evicted? Don't bother then
3724 //printf("no cc/rtmp %08x\n", start + i*4);
3725 return;
3726 }
cf95b4f0 3727 if (!dops[i].bt) {
32631e6a 3728 for (j = i - 1; j >= 0; j--) {
cf95b4f0 3729 if (dops[j].is_ds) break;
2330734f 3730 if (check_multdiv(j, &known_cycles))
32631e6a 3731 break;
3732 if (is_mflohi(j))
3733 // already handled by this op
3734 return;
2330734f 3735 if (dops[j].bt || (j > 0 && ccadj[j - 1] > ccadj[j]))
3736 break;
32631e6a 3737 }
3738 j = max(j, 0);
3739 }
3740 if (known_cycles > 0) {
2330734f 3741 known_cycles -= ccadj[i] - ccadj[j];
32631e6a 3742 assem_debug("; muldiv stall resolved %d\n", known_cycles);
3743 if (known_cycles > 0)
3744 emit_addimm(HOST_CCREG, known_cycles, HOST_CCREG);
3745 return;
3746 }
3747 assem_debug("; muldiv stall unresolved\n");
3748 host_tempreg_acquire();
3749 emit_readword(&psxRegs.muldivBusyCycle, rtmp);
2330734f 3750 emit_addimm(rtmp, -ccadj[i], rtmp);
32631e6a 3751 emit_sub(rtmp, HOST_CCREG, HOST_TEMPREG);
3752 emit_cmpimm(HOST_TEMPREG, 37);
3753 emit_cmovb_reg(rtmp, HOST_CCREG);
3754 //emit_log_gte_stall(i, 0, reglist);
3755 host_tempreg_release();
3756}
3757
8062d65a 3758static void cop2_get_dreg(u_int copr,signed char tl,signed char temp)
3759{
3760 switch (copr) {
3761 case 1:
3762 case 3:
3763 case 5:
3764 case 8:
3765 case 9:
3766 case 10:
3767 case 11:
3768 emit_readword(&reg_cop2d[copr],tl);
3769 emit_signextend16(tl,tl);
3770 emit_writeword(tl,&reg_cop2d[copr]); // hmh
3771 break;
3772 case 7:
3773 case 16:
3774 case 17:
3775 case 18:
3776 case 19:
3777 emit_readword(&reg_cop2d[copr],tl);
3778 emit_andimm(tl,0xffff,tl);
3779 emit_writeword(tl,&reg_cop2d[copr]);
3780 break;
3781 case 15:
3782 emit_readword(&reg_cop2d[14],tl); // SXY2
3783 emit_writeword(tl,&reg_cop2d[copr]);
3784 break;
3785 case 28:
3786 case 29:
3968e69e 3787 c2op_mfc2_29_assemble(tl,temp);
8062d65a 3788 break;
3789 default:
3790 emit_readword(&reg_cop2d[copr],tl);
3791 break;
3792 }
3793}
3794
3795static void cop2_put_dreg(u_int copr,signed char sl,signed char temp)
3796{
3797 switch (copr) {
3798 case 15:
3799 emit_readword(&reg_cop2d[13],temp); // SXY1
3800 emit_writeword(sl,&reg_cop2d[copr]);
3801 emit_writeword(temp,&reg_cop2d[12]); // SXY0
3802 emit_readword(&reg_cop2d[14],temp); // SXY2
3803 emit_writeword(sl,&reg_cop2d[14]);
3804 emit_writeword(temp,&reg_cop2d[13]); // SXY1
3805 break;
3806 case 28:
3807 emit_andimm(sl,0x001f,temp);
3808 emit_shlimm(temp,7,temp);
3809 emit_writeword(temp,&reg_cop2d[9]);
3810 emit_andimm(sl,0x03e0,temp);
3811 emit_shlimm(temp,2,temp);
3812 emit_writeword(temp,&reg_cop2d[10]);
3813 emit_andimm(sl,0x7c00,temp);
3814 emit_shrimm(temp,3,temp);
3815 emit_writeword(temp,&reg_cop2d[11]);
3816 emit_writeword(sl,&reg_cop2d[28]);
3817 break;
3818 case 30:
3968e69e 3819 emit_xorsar_imm(sl,sl,31,temp);
be516ebe 3820#if defined(HAVE_ARMV5) || defined(__aarch64__)
8062d65a 3821 emit_clz(temp,temp);
3822#else
3823 emit_movs(temp,HOST_TEMPREG);
3824 emit_movimm(0,temp);
3825 emit_jeq((int)out+4*4);
3826 emit_addpl_imm(temp,1,temp);
3827 emit_lslpls_imm(HOST_TEMPREG,1,HOST_TEMPREG);
3828 emit_jns((int)out-2*4);
3829#endif
3830 emit_writeword(sl,&reg_cop2d[30]);
3831 emit_writeword(temp,&reg_cop2d[31]);
3832 break;
3833 case 31:
3834 break;
3835 default:
3836 emit_writeword(sl,&reg_cop2d[copr]);
3837 break;
3838 }
3839}
3840
2330734f 3841static void c2ls_assemble(int i, const struct regstat *i_regs, int ccadj_)
b9b61529 3842{
3843 int s,tl;
3844 int ar;
3845 int offset;
1fd1aceb 3846 int memtarget=0,c=0;
b14b6a8f 3847 void *jaddr2=NULL;
3848 enum stub_type type;
b9b61529 3849 int agr=AGEN1+(i&1);
37387d8b 3850 int offset_reg = -1;
3851 int fastio_reg_override = -1;
81dbbf4c 3852 u_int reglist=get_host_reglist(i_regs->regmap);
b9b61529 3853 u_int copr=(source[i]>>16)&0x1f;
cf95b4f0 3854 s=get_reg(i_regs->regmap,dops[i].rs1);
b9b61529 3855 tl=get_reg(i_regs->regmap,FTEMP);
3856 offset=imm[i];
cf95b4f0 3857 assert(dops[i].rs1>0);
b9b61529 3858 assert(tl>=0);
b9b61529 3859
b9b61529 3860 if(i_regs->regmap[HOST_CCREG]==CCREG)
3861 reglist&=~(1<<HOST_CCREG);
3862
3863 // get the address
cf95b4f0 3864 if (dops[i].opcode==0x3a) { // SWC2
b9b61529 3865 ar=get_reg(i_regs->regmap,agr);
9de8a0c3 3866 if(ar<0) ar=get_reg_temp(i_regs->regmap);
b9b61529 3867 reglist|=1<<ar;
3868 } else { // LWC2
3869 ar=tl;
3870 }
1fd1aceb 3871 if(s>=0) c=(i_regs->wasconst>>s)&1;
3872 memtarget=c&&(((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE);
b9b61529 3873 if (!offset&&!c&&s>=0) ar=s;
3874 assert(ar>=0);
3875
32631e6a 3876 cop2_do_stall_check(0, i, i_regs, reglist);
3877
cf95b4f0 3878 if (dops[i].opcode==0x3a) { // SWC2
3968e69e 3879 cop2_get_dreg(copr,tl,-1);
1fd1aceb 3880 type=STOREW_STUB;
b9b61529 3881 }
1fd1aceb 3882 else
b9b61529 3883 type=LOADW_STUB;
1fd1aceb 3884
3885 if(c&&!memtarget) {
b14b6a8f 3886 jaddr2=out;
1fd1aceb 3887 emit_jmp(0); // inline_readstub/inline_writestub?
b9b61529 3888 }
1fd1aceb 3889 else {
3890 if(!c) {
37387d8b 3891 jaddr2 = emit_fastpath_cmp_jump(i, i_regs, ar,
3892 &offset_reg, &fastio_reg_override);
3893 }
3894 else if (ram_offset && memtarget) {
3895 offset_reg = get_ro_reg(i_regs, 0);
3896 }
3897 switch (dops[i].opcode) {
3898 case 0x32: { // LWC2
3899 int a = ar;
3900 if (fastio_reg_override >= 0)
3901 a = fastio_reg_override;
3902 do_load_word(a, tl, offset_reg);
3903 break;
1fd1aceb 3904 }
37387d8b 3905 case 0x3a: { // SWC2
1fd1aceb 3906 #ifdef DESTRUCTIVE_SHIFT
3907 if(!offset&&!c&&s>=0) emit_mov(s,ar);
3908 #endif
37387d8b 3909 int a = ar;
3910 if (fastio_reg_override >= 0)
3911 a = fastio_reg_override;
3912 do_store_word(a, 0, tl, offset_reg, 1);
3913 break;
3914 }
3915 default:
3916 assert(0);
1fd1aceb 3917 }
b9b61529 3918 }
37387d8b 3919 if (fastio_reg_override == HOST_TEMPREG || offset_reg == HOST_TEMPREG)
d1e4ebd9 3920 host_tempreg_release();
b9b61529 3921 if(jaddr2)
2330734f 3922 add_stub_r(type,jaddr2,out,i,ar,i_regs,ccadj_,reglist);
cf95b4f0 3923 if(dops[i].opcode==0x3a) // SWC2
3924 if(!(i_regs->waswritten&(1<<dops[i].rs1)) && !HACK_ENABLED(NDHACK_NO_SMC_CHECK)) {
b9b61529 3925#if defined(HOST_IMM8)
3926 int ir=get_reg(i_regs->regmap,INVCP);
3927 assert(ir>=0);
3928 emit_cmpmem_indexedsr12_reg(ir,ar,1);
3929#else
643aeae3 3930 emit_cmpmem_indexedsr12_imm(invalid_code,ar,1);
b9b61529 3931#endif
882a08fc 3932 #ifdef INVALIDATE_USE_COND_CALL
0bbd1454 3933 emit_callne(invalidate_addr_reg[ar]);
3934 #else
b14b6a8f 3935 void *jaddr3 = out;
b9b61529 3936 emit_jne(0);
b14b6a8f 3937 add_stub(INVCODE_STUB,jaddr3,out,reglist|(1<<HOST_CCREG),ar,0,0,0);
0bbd1454 3938 #endif
b9b61529 3939 }
cf95b4f0 3940 if (dops[i].opcode==0x32) { // LWC2
d1e4ebd9 3941 host_tempreg_acquire();
b9b61529 3942 cop2_put_dreg(copr,tl,HOST_TEMPREG);
d1e4ebd9 3943 host_tempreg_release();
b9b61529 3944 }
3945}
3946
81dbbf4c 3947static void cop2_assemble(int i, const struct regstat *i_regs)
8062d65a 3948{
81dbbf4c 3949 u_int copr = (source[i]>>11) & 0x1f;
9de8a0c3 3950 signed char temp = get_reg_temp(i_regs->regmap);
81dbbf4c 3951
32631e6a 3952 if (!HACK_ENABLED(NDHACK_NO_STALLS)) {
3953 u_int reglist = reglist_exclude(get_host_reglist(i_regs->regmap), temp, -1);
cf95b4f0 3954 if (dops[i].opcode2 == 0 || dops[i].opcode2 == 2) { // MFC2/CFC2
3955 signed char tl = get_reg(i_regs->regmap, dops[i].rt1);
32631e6a 3956 reglist = reglist_exclude(reglist, tl, -1);
81dbbf4c 3957 }
32631e6a 3958 cop2_do_stall_check(0, i, i_regs, reglist);
81dbbf4c 3959 }
cf95b4f0 3960 if (dops[i].opcode2==0) { // MFC2
3961 signed char tl=get_reg(i_regs->regmap,dops[i].rt1);
3962 if(tl>=0&&dops[i].rt1!=0)
8062d65a 3963 cop2_get_dreg(copr,tl,temp);
3964 }
cf95b4f0 3965 else if (dops[i].opcode2==4) { // MTC2
3966 signed char sl=get_reg(i_regs->regmap,dops[i].rs1);
8062d65a 3967 cop2_put_dreg(copr,sl,temp);
3968 }
cf95b4f0 3969 else if (dops[i].opcode2==2) // CFC2
8062d65a 3970 {
cf95b4f0 3971 signed char tl=get_reg(i_regs->regmap,dops[i].rt1);
3972 if(tl>=0&&dops[i].rt1!=0)
8062d65a 3973 emit_readword(&reg_cop2c[copr],tl);
3974 }
cf95b4f0 3975 else if (dops[i].opcode2==6) // CTC2
8062d65a 3976 {
cf95b4f0 3977 signed char sl=get_reg(i_regs->regmap,dops[i].rs1);
8062d65a 3978 switch(copr) {
3979 case 4:
3980 case 12:
3981 case 20:
3982 case 26:
3983 case 27:
3984 case 29:
3985 case 30:
3986 emit_signextend16(sl,temp);
3987 break;
3988 case 31:
3968e69e 3989 c2op_ctc2_31_assemble(sl,temp);
8062d65a 3990 break;
3991 default:
3992 temp=sl;
3993 break;
3994 }
3995 emit_writeword(temp,&reg_cop2c[copr]);
3996 assert(sl>=0);
3997 }
3998}
3999
3968e69e 4000static void do_unalignedwritestub(int n)
4001{
4002 assem_debug("do_unalignedwritestub %x\n",start+stubs[n].a*4);
4003 literal_pool(256);
4004 set_jump_target(stubs[n].addr, out);
4005
4006 int i=stubs[n].a;
4007 struct regstat *i_regs=(struct regstat *)stubs[n].c;
4008 int addr=stubs[n].b;
4009 u_int reglist=stubs[n].e;
4010 signed char *i_regmap=i_regs->regmap;
4011 int temp2=get_reg(i_regmap,FTEMP);
4012 int rt;
cf95b4f0 4013 rt=get_reg(i_regmap,dops[i].rs2);
3968e69e 4014 assert(rt>=0);
4015 assert(addr>=0);
cf95b4f0 4016 assert(dops[i].opcode==0x2a||dops[i].opcode==0x2e); // SWL/SWR only implemented
3968e69e 4017 reglist|=(1<<addr);
4018 reglist&=~(1<<temp2);
4019
3968e69e 4020 // don't bother with it and call write handler
4021 save_regs(reglist);
4022 pass_args(addr,rt);
4023 int cc=get_reg(i_regmap,CCREG);
4024 if(cc<0)
4025 emit_loadreg(CCREG,2);
2330734f 4026 emit_addimm(cc<0?2:cc,(int)stubs[n].d+1,2);
cf95b4f0 4027 emit_far_call((dops[i].opcode==0x2a?jump_handle_swl:jump_handle_swr));
2330734f 4028 emit_addimm(0,-((int)stubs[n].d+1),cc<0?2:cc);
3968e69e 4029 if(cc<0)
4030 emit_storereg(CCREG,2);
4031 restore_regs(reglist);
4032 emit_jmp(stubs[n].retaddr); // return address
3968e69e 4033}
4034
57871462 4035#ifndef multdiv_assemble
4036void multdiv_assemble(int i,struct regstat *i_regs)
4037{
4038 printf("Need multdiv_assemble for this architecture.\n");
7c3a5182 4039 abort();
57871462 4040}
4041#endif
4042
2330734f 4043static void mov_assemble(int i, const struct regstat *i_regs)
57871462 4044{
cf95b4f0 4045 //if(dops[i].opcode2==0x10||dops[i].opcode2==0x12) { // MFHI/MFLO
4046 //if(dops[i].opcode2==0x11||dops[i].opcode2==0x13) { // MTHI/MTLO
4047 if(dops[i].rt1) {
7c3a5182 4048 signed char sl,tl;
cf95b4f0 4049 tl=get_reg(i_regs->regmap,dops[i].rt1);
57871462 4050 //assert(tl>=0);
4051 if(tl>=0) {
cf95b4f0 4052 sl=get_reg(i_regs->regmap,dops[i].rs1);
57871462 4053 if(sl>=0) emit_mov(sl,tl);
cf95b4f0 4054 else emit_loadreg(dops[i].rs1,tl);
57871462 4055 }
4056 }
cf95b4f0 4057 if (dops[i].rs1 == HIREG || dops[i].rs1 == LOREG) // MFHI/MFLO
32631e6a 4058 multdiv_do_stall(i, i_regs);
57871462 4059}
4060
3968e69e 4061// call interpreter, exception handler, things that change pc/regs/cycles ...
2330734f 4062static void call_c_cpu_handler(int i, const struct regstat *i_regs, int ccadj_, u_int pc, void *func)
57871462 4063{
4064 signed char ccreg=get_reg(i_regs->regmap,CCREG);
4065 assert(ccreg==HOST_CCREG);
4066 assert(!is_delayslot);
581335b0 4067 (void)ccreg;
3968e69e 4068
4069 emit_movimm(pc,3); // Get PC
4070 emit_readword(&last_count,2);
4071 emit_writeword(3,&psxRegs.pc);
2330734f 4072 emit_addimm(HOST_CCREG,ccadj_,HOST_CCREG);
3968e69e 4073 emit_add(2,HOST_CCREG,2);
4074 emit_writeword(2,&psxRegs.cycle);
2a014d73 4075 emit_far_call(func);
4076 emit_far_jump(jump_to_new_pc);
3968e69e 4077}
4078
2330734f 4079static void syscall_assemble(int i, const struct regstat *i_regs, int ccadj_)
3968e69e 4080{
d1150cd6 4081 // 'break' tends to be littered around to catch things like
4082 // division by 0 and is almost never executed, so don't emit much code here
4083 void *func = (dops[i].opcode2 == 0x0C)
4084 ? (is_delayslot ? jump_syscall_ds : jump_syscall)
4085 : (is_delayslot ? jump_break_ds : jump_break);
2acc46cd 4086 assert(get_reg(i_regs->regmap, CCREG) == HOST_CCREG);
d1150cd6 4087 emit_movimm(start + i*4, 2); // pc
4088 emit_addimm(HOST_CCREG, ccadj_ + CLOCK_ADJUST(1), HOST_CCREG);
4089 emit_far_jump(func);
7139f3c8 4090}
4091
2330734f 4092static void hlecall_assemble(int i, const struct regstat *i_regs, int ccadj_)
7139f3c8 4093{
3968e69e 4094 void *hlefunc = psxNULL;
dd79da89 4095 uint32_t hleCode = source[i] & 0x03ffffff;
3968e69e 4096 if (hleCode < ARRAY_SIZE(psxHLEt))
4097 hlefunc = psxHLEt[hleCode];
4098
2330734f 4099 call_c_cpu_handler(i, i_regs, ccadj_, start + i*4+4, hlefunc);
57871462 4100}
4101
2330734f 4102static void intcall_assemble(int i, const struct regstat *i_regs, int ccadj_)
1e973cb0 4103{
2330734f 4104 call_c_cpu_handler(i, i_regs, ccadj_, start + i*4, execI);
1e973cb0 4105}
4106
8062d65a 4107static void speculate_mov(int rs,int rt)
4108{
4109 if(rt!=0) {
4110 smrv_strong_next|=1<<rt;
4111 smrv[rt]=smrv[rs];
4112 }
4113}
4114
4115static void speculate_mov_weak(int rs,int rt)
4116{
4117 if(rt!=0) {
4118 smrv_weak_next|=1<<rt;
4119 smrv[rt]=smrv[rs];
4120 }
4121}
4122
4123static void speculate_register_values(int i)
4124{
4125 if(i==0) {
4126 memcpy(smrv,psxRegs.GPR.r,sizeof(smrv));
4127 // gp,sp are likely to stay the same throughout the block
4128 smrv_strong_next=(1<<28)|(1<<29)|(1<<30);
4129 smrv_weak_next=~smrv_strong_next;
4130 //printf(" llr %08x\n", smrv[4]);
4131 }
4132 smrv_strong=smrv_strong_next;
4133 smrv_weak=smrv_weak_next;
cf95b4f0 4134 switch(dops[i].itype) {
8062d65a 4135 case ALU:
cf95b4f0 4136 if ((smrv_strong>>dops[i].rs1)&1) speculate_mov(dops[i].rs1,dops[i].rt1);
4137 else if((smrv_strong>>dops[i].rs2)&1) speculate_mov(dops[i].rs2,dops[i].rt1);
4138 else if((smrv_weak>>dops[i].rs1)&1) speculate_mov_weak(dops[i].rs1,dops[i].rt1);
4139 else if((smrv_weak>>dops[i].rs2)&1) speculate_mov_weak(dops[i].rs2,dops[i].rt1);
8062d65a 4140 else {
cf95b4f0 4141 smrv_strong_next&=~(1<<dops[i].rt1);
4142 smrv_weak_next&=~(1<<dops[i].rt1);
8062d65a 4143 }
4144 break;
4145 case SHIFTIMM:
cf95b4f0 4146 smrv_strong_next&=~(1<<dops[i].rt1);
4147 smrv_weak_next&=~(1<<dops[i].rt1);
8062d65a 4148 // fallthrough
4149 case IMM16:
cf95b4f0 4150 if(dops[i].rt1&&is_const(&regs[i],dops[i].rt1)) {
4151 int value,hr=get_reg(regs[i].regmap,dops[i].rt1);
8062d65a 4152 if(hr>=0) {
4153 if(get_final_value(hr,i,&value))
cf95b4f0 4154 smrv[dops[i].rt1]=value;
4155 else smrv[dops[i].rt1]=constmap[i][hr];
4156 smrv_strong_next|=1<<dops[i].rt1;
8062d65a 4157 }
4158 }
4159 else {
cf95b4f0 4160 if ((smrv_strong>>dops[i].rs1)&1) speculate_mov(dops[i].rs1,dops[i].rt1);
4161 else if((smrv_weak>>dops[i].rs1)&1) speculate_mov_weak(dops[i].rs1,dops[i].rt1);
8062d65a 4162 }
4163 break;
4164 case LOAD:
cf95b4f0 4165 if(start<0x2000&&(dops[i].rt1==26||(smrv[dops[i].rt1]>>24)==0xa0)) {
8062d65a 4166 // special case for BIOS
cf95b4f0 4167 smrv[dops[i].rt1]=0xa0000000;
4168 smrv_strong_next|=1<<dops[i].rt1;
8062d65a 4169 break;
4170 }
4171 // fallthrough
4172 case SHIFT:
4173 case LOADLR:
4174 case MOV:
cf95b4f0 4175 smrv_strong_next&=~(1<<dops[i].rt1);
4176 smrv_weak_next&=~(1<<dops[i].rt1);
8062d65a 4177 break;
4178 case COP0:
4179 case COP2:
cf95b4f0 4180 if(dops[i].opcode2==0||dops[i].opcode2==2) { // MFC/CFC
4181 smrv_strong_next&=~(1<<dops[i].rt1);
4182 smrv_weak_next&=~(1<<dops[i].rt1);
8062d65a 4183 }
4184 break;
4185 case C2LS:
cf95b4f0 4186 if (dops[i].opcode==0x32) { // LWC2
4187 smrv_strong_next&=~(1<<dops[i].rt1);
4188 smrv_weak_next&=~(1<<dops[i].rt1);
8062d65a 4189 }
4190 break;
4191 }
4192#if 0
4193 int r=4;
4194 printf("x %08x %08x %d %d c %08x %08x\n",smrv[r],start+i*4,
4195 ((smrv_strong>>r)&1),(smrv_weak>>r)&1,regs[i].isconst,regs[i].wasconst);
4196#endif
4197}
4198
2330734f 4199static void ujump_assemble(int i, const struct regstat *i_regs);
4200static void rjump_assemble(int i, const struct regstat *i_regs);
4201static void cjump_assemble(int i, const struct regstat *i_regs);
4202static void sjump_assemble(int i, const struct regstat *i_regs);
2330734f 4203
4204static int assemble(int i, const struct regstat *i_regs, int ccadj_)
57871462 4205{
2330734f 4206 int ds = 0;
4207 switch (dops[i].itype) {
57871462 4208 case ALU:
2330734f 4209 alu_assemble(i, i_regs);
4210 break;
57871462 4211 case IMM16:
2330734f 4212 imm16_assemble(i, i_regs);
4213 break;
57871462 4214 case SHIFT:
2330734f 4215 shift_assemble(i, i_regs);
4216 break;
57871462 4217 case SHIFTIMM:
2330734f 4218 shiftimm_assemble(i, i_regs);
4219 break;
57871462 4220 case LOAD:
2330734f 4221 load_assemble(i, i_regs, ccadj_);
4222 break;
57871462 4223 case LOADLR:
2330734f 4224 loadlr_assemble(i, i_regs, ccadj_);
4225 break;
57871462 4226 case STORE:
2330734f 4227 store_assemble(i, i_regs, ccadj_);
4228 break;
57871462 4229 case STORELR:
2330734f 4230 storelr_assemble(i, i_regs, ccadj_);
4231 break;
57871462 4232 case COP0:
2330734f 4233 cop0_assemble(i, i_regs, ccadj_);
4234 break;
57871462 4235 case COP1:
2330734f 4236 cop1_assemble(i, i_regs);
4237 break;
57871462 4238 case C1LS:
2330734f 4239 c1ls_assemble(i, i_regs);
4240 break;
b9b61529 4241 case COP2:
2330734f 4242 cop2_assemble(i, i_regs);
4243 break;
b9b61529 4244 case C2LS:
2330734f 4245 c2ls_assemble(i, i_regs, ccadj_);
4246 break;
b9b61529 4247 case C2OP:
2330734f 4248 c2op_assemble(i, i_regs);
4249 break;
57871462 4250 case MULTDIV:
2330734f 4251 multdiv_assemble(i, i_regs);
4252 multdiv_prepare_stall(i, i_regs, ccadj_);
32631e6a 4253 break;
57871462 4254 case MOV:
2330734f 4255 mov_assemble(i, i_regs);
4256 break;
4257 case SYSCALL:
4258 syscall_assemble(i, i_regs, ccadj_);
4259 break;
4260 case HLECALL:
4261 hlecall_assemble(i, i_regs, ccadj_);
4262 break;
4263 case INTCALL:
4264 intcall_assemble(i, i_regs, ccadj_);
4265 break;
4266 case UJUMP:
4267 ujump_assemble(i, i_regs);
4268 ds = 1;
4269 break;
4270 case RJUMP:
4271 rjump_assemble(i, i_regs);
4272 ds = 1;
4273 break;
4274 case CJUMP:
4275 cjump_assemble(i, i_regs);
4276 ds = 1;
4277 break;
4278 case SJUMP:
4279 sjump_assemble(i, i_regs);
4280 ds = 1;
4281 break;
24058131 4282 case NOP:
2330734f 4283 case OTHER:
4284 case NI:
4285 // not handled, just skip
4286 break;
4287 default:
4288 assert(0);
4289 }
4290 return ds;
4291}
4292
4293static void ds_assemble(int i, const struct regstat *i_regs)
4294{
4295 speculate_register_values(i);
4296 is_delayslot = 1;
4297 switch (dops[i].itype) {
57871462 4298 case SYSCALL:
7139f3c8 4299 case HLECALL:
1e973cb0 4300 case INTCALL:
57871462 4301 case UJUMP:
4302 case RJUMP:
4303 case CJUMP:
4304 case SJUMP:
c43b5311 4305 SysPrintf("Jump in the delay slot. This is probably a bug.\n");
2330734f 4306 break;
4307 default:
4308 assemble(i, i_regs, ccadj[i]);
57871462 4309 }
2330734f 4310 is_delayslot = 0;
57871462 4311}
4312
4313// Is the branch target a valid internal jump?
ad49de89 4314static int internal_branch(int addr)
57871462 4315{
4316 if(addr&1) return 0; // Indirect (register) jump
4317 if(addr>=start && addr<start+slen*4-4)
4318 {
71e490c5 4319 return 1;
57871462 4320 }
4321 return 0;
4322}
4323
ad49de89 4324static void wb_invalidate(signed char pre[],signed char entry[],uint64_t dirty,uint64_t u)
57871462 4325{
4326 int hr;
4327 for(hr=0;hr<HOST_REGS;hr++) {
4328 if(hr!=EXCLUDE_REG) {
4329 if(pre[hr]!=entry[hr]) {
4330 if(pre[hr]>=0) {
4331 if((dirty>>hr)&1) {
4332 if(get_reg(entry,pre[hr])<0) {
00fa9369 4333 assert(pre[hr]<64);
4334 if(!((u>>pre[hr])&1))
4335 emit_storereg(pre[hr],hr);
57871462 4336 }
4337 }
4338 }
4339 }
4340 }
4341 }
4342 // Move from one register to another (no writeback)
4343 for(hr=0;hr<HOST_REGS;hr++) {
4344 if(hr!=EXCLUDE_REG) {
4345 if(pre[hr]!=entry[hr]) {
9de8a0c3 4346 if(pre[hr]>=0&&pre[hr]<TEMPREG) {
57871462 4347 int nr;
4348 if((nr=get_reg(entry,pre[hr]))>=0) {
4349 emit_mov(hr,nr);
4350 }
4351 }
4352 }
4353 }
4354 }
4355}
57871462 4356
4357// Load the specified registers
4358// This only loads the registers given as arguments because
4359// we don't want to load things that will be overwritten
53358c1d 4360static inline void load_reg(signed char entry[], signed char regmap[], int rs)
57871462 4361{
53358c1d 4362 int hr = get_reg(regmap, rs);
4363 if (hr >= 0 && entry[hr] != regmap[hr])
4364 emit_loadreg(regmap[hr], hr);
4365}
4366
4367static void load_regs(signed char entry[], signed char regmap[], int rs1, int rs2)
4368{
4369 load_reg(entry, regmap, rs1);
4370 if (rs1 != rs2)
4371 load_reg(entry, regmap, rs2);
57871462 4372}
4373
4374// Load registers prior to the start of a loop
4375// so that they are not loaded within the loop
4376static void loop_preload(signed char pre[],signed char entry[])
4377{
4378 int hr;
53358c1d 4379 for (hr = 0; hr < HOST_REGS; hr++) {
4380 int r = entry[hr];
4381 if (r >= 0 && pre[hr] != r && get_reg(pre, r) < 0) {
4382 assem_debug("loop preload:\n");
4383 if (r < TEMPREG)
4384 emit_loadreg(r, hr);
57871462 4385 }
4386 }
4387}
4388
4389// Generate address for load/store instruction
b9b61529 4390// goes to AGEN for writes, FTEMP for LOADLR and cop1/2 loads
4149788d 4391static void address_generation(int i, const struct regstat *i_regs, signed char entry[])
57871462 4392{
37387d8b 4393 if (dops[i].is_load || dops[i].is_store) {
5194fb95 4394 int ra=-1;
57871462 4395 int agr=AGEN1+(i&1);
cf95b4f0 4396 if(dops[i].itype==LOAD) {
4397 ra=get_reg(i_regs->regmap,dops[i].rt1);
9de8a0c3 4398 if(ra<0) ra=get_reg_temp(i_regs->regmap);
535d208a 4399 assert(ra>=0);
57871462 4400 }
cf95b4f0 4401 if(dops[i].itype==LOADLR) {
57871462 4402 ra=get_reg(i_regs->regmap,FTEMP);
4403 }
cf95b4f0 4404 if(dops[i].itype==STORE||dops[i].itype==STORELR) {
57871462 4405 ra=get_reg(i_regs->regmap,agr);
9de8a0c3 4406 if(ra<0) ra=get_reg_temp(i_regs->regmap);
57871462 4407 }
37387d8b 4408 if(dops[i].itype==C2LS) {
cf95b4f0 4409 if ((dops[i].opcode&0x3b)==0x31||(dops[i].opcode&0x3b)==0x32) // LWC1/LDC1/LWC2/LDC2
57871462 4410 ra=get_reg(i_regs->regmap,FTEMP);
1fd1aceb 4411 else { // SWC1/SDC1/SWC2/SDC2
57871462 4412 ra=get_reg(i_regs->regmap,agr);
9de8a0c3 4413 if(ra<0) ra=get_reg_temp(i_regs->regmap);
57871462 4414 }
4415 }
cf95b4f0 4416 int rs=get_reg(i_regs->regmap,dops[i].rs1);
57871462 4417 if(ra>=0) {
4418 int offset=imm[i];
4419 int c=(i_regs->wasconst>>rs)&1;
cf95b4f0 4420 if(dops[i].rs1==0) {
57871462 4421 // Using r0 as a base address
57871462 4422 if(!entry||entry[ra]!=agr) {
cf95b4f0 4423 if (dops[i].opcode==0x22||dops[i].opcode==0x26) {
57871462 4424 emit_movimm(offset&0xFFFFFFFC,ra); // LWL/LWR
cf95b4f0 4425 }else if (dops[i].opcode==0x1a||dops[i].opcode==0x1b) {
57871462 4426 emit_movimm(offset&0xFFFFFFF8,ra); // LDL/LDR
4427 }else{
4428 emit_movimm(offset,ra);
4429 }
4430 } // else did it in the previous cycle
4431 }
4432 else if(rs<0) {
cf95b4f0 4433 if(!entry||entry[ra]!=dops[i].rs1)
4434 emit_loadreg(dops[i].rs1,ra);
4435 //if(!entry||entry[ra]!=dops[i].rs1)
57871462 4436 // printf("poor load scheduling!\n");
4437 }
4438 else if(c) {
cf95b4f0 4439 if(dops[i].rs1!=dops[i].rt1||dops[i].itype!=LOAD) {
57871462 4440 if(!entry||entry[ra]!=agr) {
cf95b4f0 4441 if (dops[i].opcode==0x22||dops[i].opcode==0x26) {
57871462 4442 emit_movimm((constmap[i][rs]+offset)&0xFFFFFFFC,ra); // LWL/LWR
cf95b4f0 4443 }else if (dops[i].opcode==0x1a||dops[i].opcode==0x1b) {
57871462 4444 emit_movimm((constmap[i][rs]+offset)&0xFFFFFFF8,ra); // LDL/LDR
4445 }else{
57871462 4446 emit_movimm(constmap[i][rs]+offset,ra);
8575a877 4447 regs[i].loadedconst|=1<<ra;
57871462 4448 }
4449 } // else did it in the previous cycle
4450 } // else load_consts already did it
4451 }
cf95b4f0 4452 if(offset&&!c&&dops[i].rs1) {
57871462 4453 if(rs>=0) {
4454 emit_addimm(rs,offset,ra);
4455 }else{
4456 emit_addimm(ra,offset,ra);
4457 }
4458 }
4459 }
4460 }
4461 // Preload constants for next instruction
37387d8b 4462 if (dops[i+1].is_load || dops[i+1].is_store) {
57871462 4463 int agr,ra;
57871462 4464 // Actual address
4465 agr=AGEN1+((i+1)&1);
4466 ra=get_reg(i_regs->regmap,agr);
4467 if(ra>=0) {
cf95b4f0 4468 int rs=get_reg(regs[i+1].regmap,dops[i+1].rs1);
57871462 4469 int offset=imm[i+1];
4470 int c=(regs[i+1].wasconst>>rs)&1;
cf95b4f0 4471 if(c&&(dops[i+1].rs1!=dops[i+1].rt1||dops[i+1].itype!=LOAD)) {
4472 if (dops[i+1].opcode==0x22||dops[i+1].opcode==0x26) {
57871462 4473 emit_movimm((constmap[i+1][rs]+offset)&0xFFFFFFFC,ra); // LWL/LWR
cf95b4f0 4474 }else if (dops[i+1].opcode==0x1a||dops[i+1].opcode==0x1b) {
57871462 4475 emit_movimm((constmap[i+1][rs]+offset)&0xFFFFFFF8,ra); // LDL/LDR
4476 }else{
57871462 4477 emit_movimm(constmap[i+1][rs]+offset,ra);
8575a877 4478 regs[i+1].loadedconst|=1<<ra;
57871462 4479 }
4480 }
cf95b4f0 4481 else if(dops[i+1].rs1==0) {
57871462 4482 // Using r0 as a base address
cf95b4f0 4483 if (dops[i+1].opcode==0x22||dops[i+1].opcode==0x26) {
57871462 4484 emit_movimm(offset&0xFFFFFFFC,ra); // LWL/LWR
cf95b4f0 4485 }else if (dops[i+1].opcode==0x1a||dops[i+1].opcode==0x1b) {
57871462 4486 emit_movimm(offset&0xFFFFFFF8,ra); // LDL/LDR
4487 }else{
4488 emit_movimm(offset,ra);
4489 }
4490 }
4491 }
4492 }
4493}
4494
e2b5e7aa 4495static int get_final_value(int hr, int i, int *value)
57871462 4496{
4497 int reg=regs[i].regmap[hr];
4498 while(i<slen-1) {
4499 if(regs[i+1].regmap[hr]!=reg) break;
4500 if(!((regs[i+1].isconst>>hr)&1)) break;
cf95b4f0 4501 if(dops[i+1].bt) break;
57871462 4502 i++;
4503 }
4504 if(i<slen-1) {
fe807a8a 4505 if (dops[i].is_jump) {
57871462 4506 *value=constmap[i][hr];
4507 return 1;
4508 }
cf95b4f0 4509 if(!dops[i+1].bt) {
fe807a8a 4510 if (dops[i+1].is_jump) {
57871462 4511 // Load in delay slot, out-of-order execution
cf95b4f0 4512 if(dops[i+2].itype==LOAD&&dops[i+2].rs1==reg&&dops[i+2].rt1==reg&&((regs[i+1].wasconst>>hr)&1))
57871462 4513 {
57871462 4514 // Precompute load address
4515 *value=constmap[i][hr]+imm[i+2];
4516 return 1;
4517 }
4518 }
cf95b4f0 4519 if(dops[i+1].itype==LOAD&&dops[i+1].rs1==reg&&dops[i+1].rt1==reg)
57871462 4520 {
57871462 4521 // Precompute load address
4522 *value=constmap[i][hr]+imm[i+1];
643aeae3 4523 //printf("c=%x imm=%lx\n",(long)constmap[i][hr],imm[i+1]);
57871462 4524 return 1;
4525 }
4526 }
4527 }
4528 *value=constmap[i][hr];
643aeae3 4529 //printf("c=%lx\n",(long)constmap[i][hr]);
57871462 4530 if(i==slen-1) return 1;
00fa9369 4531 assert(reg < 64);
4532 return !((unneeded_reg[i+1]>>reg)&1);
57871462 4533}
4534
4535// Load registers with known constants
ad49de89 4536static void load_consts(signed char pre[],signed char regmap[],int i)
57871462 4537{
8575a877 4538 int hr,hr2;
4539 // propagate loaded constant flags
cf95b4f0 4540 if(i==0||dops[i].bt)
8575a877 4541 regs[i].loadedconst=0;
4542 else {
4543 for(hr=0;hr<HOST_REGS;hr++) {
4544 if(hr!=EXCLUDE_REG&&regmap[hr]>=0&&((regs[i-1].isconst>>hr)&1)&&pre[hr]==regmap[hr]
4545 &&regmap[hr]==regs[i-1].regmap[hr]&&((regs[i-1].loadedconst>>hr)&1))
4546 {
4547 regs[i].loadedconst|=1<<hr;
4548 }
4549 }
4550 }
57871462 4551 // Load 32-bit regs
4552 for(hr=0;hr<HOST_REGS;hr++) {
4553 if(hr!=EXCLUDE_REG&&regmap[hr]>=0) {
4554 //if(entry[hr]!=regmap[hr]) {
8575a877 4555 if(!((regs[i].loadedconst>>hr)&1)) {
ad49de89 4556 assert(regmap[hr]<64);
4557 if(((regs[i].isconst>>hr)&1)&&regmap[hr]>0) {
8575a877 4558 int value,similar=0;
57871462 4559 if(get_final_value(hr,i,&value)) {
8575a877 4560 // see if some other register has similar value
4561 for(hr2=0;hr2<HOST_REGS;hr2++) {
4562 if(hr2!=EXCLUDE_REG&&((regs[i].loadedconst>>hr2)&1)) {
4563 if(is_similar_value(value,constmap[i][hr2])) {
4564 similar=1;
4565 break;
4566 }
4567 }
4568 }
4569 if(similar) {
4570 int value2;
4571 if(get_final_value(hr2,i,&value2)) // is this needed?
4572 emit_movimm_from(value2,hr2,value,hr);
4573 else
4574 emit_movimm(value,hr);
4575 }
4576 else if(value==0) {
57871462 4577 emit_zeroreg(hr);
4578 }
4579 else {
4580 emit_movimm(value,hr);
4581 }
4582 }
8575a877 4583 regs[i].loadedconst|=1<<hr;
57871462 4584 }
4585 }
4586 }
4587 }
57871462 4588}
ad49de89 4589
2330734f 4590static void load_all_consts(const signed char regmap[], u_int dirty, int i)
57871462 4591{
4592 int hr;
4593 // Load 32-bit regs
4594 for(hr=0;hr<HOST_REGS;hr++) {
4595 if(hr!=EXCLUDE_REG&&regmap[hr]>=0&&((dirty>>hr)&1)) {
ad49de89 4596 assert(regmap[hr] < 64);
4597 if(((regs[i].isconst>>hr)&1)&&regmap[hr]>0) {
57871462 4598 int value=constmap[i][hr];
4599 if(value==0) {
4600 emit_zeroreg(hr);
4601 }
4602 else {
4603 emit_movimm(value,hr);
4604 }
4605 }
4606 }
4607 }
57871462 4608}
4609
4610// Write out all dirty registers (except cycle count)
2330734f 4611static void wb_dirtys(const signed char i_regmap[], uint64_t i_dirty)
57871462 4612{
4613 int hr;
4614 for(hr=0;hr<HOST_REGS;hr++) {
4615 if(hr!=EXCLUDE_REG) {
4616 if(i_regmap[hr]>0) {
4617 if(i_regmap[hr]!=CCREG) {
4618 if((i_dirty>>hr)&1) {
00fa9369 4619 assert(i_regmap[hr]<64);
4620 emit_storereg(i_regmap[hr],hr);
57871462 4621 }
4622 }
4623 }
4624 }
4625 }
4626}
ad49de89 4627
57871462 4628// Write out dirty registers that we need to reload (pair with load_needed_regs)
4629// This writes the registers not written by store_regs_bt
2330734f 4630static void wb_needed_dirtys(const signed char i_regmap[], uint64_t i_dirty, int addr)
57871462 4631{
4632 int hr;
4633 int t=(addr-start)>>2;
4634 for(hr=0;hr<HOST_REGS;hr++) {
4635 if(hr!=EXCLUDE_REG) {
4636 if(i_regmap[hr]>0) {
4637 if(i_regmap[hr]!=CCREG) {
ad49de89 4638 if(i_regmap[hr]==regs[t].regmap_entry[hr] && ((regs[t].dirty>>hr)&1)) {
57871462 4639 if((i_dirty>>hr)&1) {
00fa9369 4640 assert(i_regmap[hr]<64);
4641 emit_storereg(i_regmap[hr],hr);
57871462 4642 }
4643 }
4644 }
4645 }
4646 }
4647 }
4648}
4649
4650// Load all registers (except cycle count)
2330734f 4651static void load_all_regs(const signed char i_regmap[])
57871462 4652{
4653 int hr;
4654 for(hr=0;hr<HOST_REGS;hr++) {
4655 if(hr!=EXCLUDE_REG) {
4656 if(i_regmap[hr]==0) {
4657 emit_zeroreg(hr);
4658 }
4659 else
9de8a0c3 4660 if(i_regmap[hr]>0 && i_regmap[hr]<TEMPREG && i_regmap[hr]!=CCREG)
57871462 4661 {
4662 emit_loadreg(i_regmap[hr],hr);
4663 }
4664 }
4665 }
4666}
4667
4668// Load all current registers also needed by next instruction
2330734f 4669static void load_needed_regs(const signed char i_regmap[], const signed char next_regmap[])
57871462 4670{
4671 int hr;
4672 for(hr=0;hr<HOST_REGS;hr++) {
4673 if(hr!=EXCLUDE_REG) {
4674 if(get_reg(next_regmap,i_regmap[hr])>=0) {
4675 if(i_regmap[hr]==0) {
4676 emit_zeroreg(hr);
4677 }
4678 else
9de8a0c3 4679 if(i_regmap[hr]>0 && i_regmap[hr]<TEMPREG && i_regmap[hr]!=CCREG)
57871462 4680 {
4681 emit_loadreg(i_regmap[hr],hr);
4682 }
4683 }
4684 }
4685 }
4686}
4687
4688// Load all regs, storing cycle count if necessary
2330734f 4689static void load_regs_entry(int t)
57871462 4690{
4691 int hr;
cf95b4f0 4692 if(dops[t].is_ds) emit_addimm(HOST_CCREG,CLOCK_ADJUST(1),HOST_CCREG);
2330734f 4693 else if(ccadj[t]) emit_addimm(HOST_CCREG,-ccadj[t],HOST_CCREG);
57871462 4694 if(regs[t].regmap_entry[HOST_CCREG]!=CCREG) {
4695 emit_storereg(CCREG,HOST_CCREG);
4696 }
4697 // Load 32-bit regs
4698 for(hr=0;hr<HOST_REGS;hr++) {
ea3d2e6e 4699 if(regs[t].regmap_entry[hr]>=0&&regs[t].regmap_entry[hr]<TEMPREG) {
57871462 4700 if(regs[t].regmap_entry[hr]==0) {
4701 emit_zeroreg(hr);
4702 }
4703 else if(regs[t].regmap_entry[hr]!=CCREG)
4704 {
4705 emit_loadreg(regs[t].regmap_entry[hr],hr);
4706 }
4707 }
4708 }
57871462 4709}
4710
4711// Store dirty registers prior to branch
4149788d 4712static void store_regs_bt(signed char i_regmap[],uint64_t i_dirty,int addr)
57871462 4713{
ad49de89 4714 if(internal_branch(addr))
57871462 4715 {
4716 int t=(addr-start)>>2;
4717 int hr;
4718 for(hr=0;hr<HOST_REGS;hr++) {
4719 if(hr!=EXCLUDE_REG) {
4720 if(i_regmap[hr]>0 && i_regmap[hr]!=CCREG) {
ad49de89 4721 if(i_regmap[hr]!=regs[t].regmap_entry[hr] || !((regs[t].dirty>>hr)&1)) {
57871462 4722 if((i_dirty>>hr)&1) {
00fa9369 4723 assert(i_regmap[hr]<64);
4724 if(!((unneeded_reg[t]>>i_regmap[hr])&1))
4725 emit_storereg(i_regmap[hr],hr);
57871462 4726 }
4727 }
4728 }
4729 }
4730 }
4731 }
4732 else
4733 {
4734 // Branch out of this block, write out all dirty regs
ad49de89 4735 wb_dirtys(i_regmap,i_dirty);
57871462 4736 }
4737}
4738
4739// Load all needed registers for branch target
ad49de89 4740static void load_regs_bt(signed char i_regmap[],uint64_t i_dirty,int addr)
57871462 4741{
4742 //if(addr>=start && addr<(start+slen*4))
ad49de89 4743 if(internal_branch(addr))
57871462 4744 {
4745 int t=(addr-start)>>2;
4746 int hr;
4747 // Store the cycle count before loading something else
4748 if(i_regmap[HOST_CCREG]!=CCREG) {
4749 assert(i_regmap[HOST_CCREG]==-1);
4750 }
4751 if(regs[t].regmap_entry[HOST_CCREG]!=CCREG) {
4752 emit_storereg(CCREG,HOST_CCREG);
4753 }
4754 // Load 32-bit regs
4755 for(hr=0;hr<HOST_REGS;hr++) {
ea3d2e6e 4756 if(hr!=EXCLUDE_REG&&regs[t].regmap_entry[hr]>=0&&regs[t].regmap_entry[hr]<TEMPREG) {
00fa9369 4757 if(i_regmap[hr]!=regs[t].regmap_entry[hr]) {
57871462 4758 if(regs[t].regmap_entry[hr]==0) {
4759 emit_zeroreg(hr);
4760 }
4761 else if(regs[t].regmap_entry[hr]!=CCREG)
4762 {
4763 emit_loadreg(regs[t].regmap_entry[hr],hr);
4764 }
4765 }
4766 }
4767 }
57871462 4768 }
4769}
4770
ad49de89 4771static int match_bt(signed char i_regmap[],uint64_t i_dirty,int addr)
57871462 4772{
4773 if(addr>=start && addr<start+slen*4-4)
4774 {
4775 int t=(addr-start)>>2;
4776 int hr;
4777 if(regs[t].regmap_entry[HOST_CCREG]!=CCREG) return 0;
4778 for(hr=0;hr<HOST_REGS;hr++)
4779 {
4780 if(hr!=EXCLUDE_REG)
4781 {
4782 if(i_regmap[hr]!=regs[t].regmap_entry[hr])
4783 {
ea3d2e6e 4784 if(regs[t].regmap_entry[hr]>=0&&(regs[t].regmap_entry[hr]|64)<TEMPREG+64)
57871462 4785 {
4786 return 0;
4787 }
9f51b4b9 4788 else
57871462 4789 if((i_dirty>>hr)&1)
4790 {
ea3d2e6e 4791 if(i_regmap[hr]<TEMPREG)
57871462 4792 {
4793 if(!((unneeded_reg[t]>>i_regmap[hr])&1))
4794 return 0;
4795 }
ea3d2e6e 4796 else if(i_regmap[hr]>=64&&i_regmap[hr]<TEMPREG+64)
57871462 4797 {
00fa9369 4798 assert(0);
57871462 4799 }
4800 }
4801 }
4802 else // Same register but is it 32-bit or dirty?
4803 if(i_regmap[hr]>=0)
4804 {
4805 if(!((regs[t].dirty>>hr)&1))
4806 {
4807 if((i_dirty>>hr)&1)
4808 {
4809 if(!((unneeded_reg[t]>>i_regmap[hr])&1))
4810 {
4811 //printf("%x: dirty no match\n",addr);
4812 return 0;
4813 }
4814 }
4815 }
57871462 4816 }
4817 }
4818 }
57871462 4819 // Delay slots are not valid branch targets
fe807a8a 4820 //if(t>0&&(dops[t-1].is_jump) return 0;
57871462 4821 // Delay slots require additional processing, so do not match
cf95b4f0 4822 if(dops[t].is_ds) return 0;
57871462 4823 }
4824 else
4825 {
4826 int hr;
4827 for(hr=0;hr<HOST_REGS;hr++)
4828 {
4829 if(hr!=EXCLUDE_REG)
4830 {
4831 if(i_regmap[hr]>=0)
4832 {
4833 if(hr!=HOST_CCREG||i_regmap[hr]!=CCREG)
4834 {
4835 if((i_dirty>>hr)&1)
4836 {
4837 return 0;
4838 }
4839 }
4840 }
4841 }
4842 }
4843 }
4844 return 1;
4845}
4846
dd114d7d 4847#ifdef DRC_DBG
2330734f 4848static void drc_dbg_emit_do_cmp(int i, int ccadj_)
dd114d7d 4849{
4850 extern void do_insn_cmp();
3968e69e 4851 //extern int cycle;
81dbbf4c 4852 u_int hr, reglist = get_host_reglist(regs[i].regmap);
dd114d7d 4853
40fca85b 4854 assem_debug("//do_insn_cmp %08x\n", start+i*4);
dd114d7d 4855 save_regs(reglist);
40fca85b 4856 // write out changed consts to match the interpreter
cf95b4f0 4857 if (i > 0 && !dops[i].bt) {
40fca85b 4858 for (hr = 0; hr < HOST_REGS; hr++) {
2330734f 4859 int reg = regs[i].regmap_entry[hr]; // regs[i-1].regmap[hr];
40fca85b 4860 if (hr == EXCLUDE_REG || reg < 0)
4861 continue;
4862 if (!((regs[i-1].isconst >> hr) & 1))
4863 continue;
4864 if (i > 1 && reg == regs[i-2].regmap[hr] && constmap[i-1][hr] == constmap[i-2][hr])
4865 continue;
4866 emit_movimm(constmap[i-1][hr],0);
4867 emit_storereg(reg, 0);
4868 }
4869 }
dd114d7d 4870 emit_movimm(start+i*4,0);
643aeae3 4871 emit_writeword(0,&pcaddr);
2330734f 4872 int cc = get_reg(regs[i].regmap_entry, CCREG);
4873 if (cc < 0)
4874 emit_loadreg(CCREG, cc = 0);
4875 emit_addimm(cc, ccadj_, 0);
4876 emit_writeword(0, &psxRegs.cycle);
2a014d73 4877 emit_far_call(do_insn_cmp);
643aeae3 4878 //emit_readword(&cycle,0);
dd114d7d 4879 //emit_addimm(0,2,0);
643aeae3 4880 //emit_writeword(0,&cycle);
3968e69e 4881 (void)get_reg2;
dd114d7d 4882 restore_regs(reglist);
40fca85b 4883 assem_debug("\\\\do_insn_cmp\n");
dd114d7d 4884}
4885#else
2330734f 4886#define drc_dbg_emit_do_cmp(x,y)
dd114d7d 4887#endif
4888
57871462 4889// Used when a branch jumps into the delay slot of another branch
7c3a5182 4890static void ds_assemble_entry(int i)
57871462 4891{
2330734f 4892 int t = (ba[i] - start) >> 2;
4893 int ccadj_ = -CLOCK_ADJUST(1);
df4dc2b1 4894 if (!instr_addr[t])
4895 instr_addr[t] = out;
57871462 4896 assem_debug("Assemble delay slot at %x\n",ba[i]);
4897 assem_debug("<->\n");
2330734f 4898 drc_dbg_emit_do_cmp(t, ccadj_);
57871462 4899 if(regs[t].regmap_entry[HOST_CCREG]==CCREG&&regs[t].regmap[HOST_CCREG]!=CCREG)
ad49de89 4900 wb_register(CCREG,regs[t].regmap_entry,regs[t].wasdirty);
cf95b4f0 4901 load_regs(regs[t].regmap_entry,regs[t].regmap,dops[t].rs1,dops[t].rs2);
57871462 4902 address_generation(t,&regs[t],regs[t].regmap_entry);
37387d8b 4903 if (ram_offset && (dops[t].is_load || dops[t].is_store))
53358c1d 4904 load_reg(regs[t].regmap_entry,regs[t].regmap,ROREG);
37387d8b 4905 if (dops[t].is_store)
53358c1d 4906 load_reg(regs[t].regmap_entry,regs[t].regmap,INVCP);
57871462 4907 is_delayslot=0;
2330734f 4908 switch (dops[t].itype) {
57871462 4909 case SYSCALL:
7139f3c8 4910 case HLECALL:
1e973cb0 4911 case INTCALL:
57871462 4912 case UJUMP:
4913 case RJUMP:
4914 case CJUMP:
4915 case SJUMP:
c43b5311 4916 SysPrintf("Jump in the delay slot. This is probably a bug.\n");
2330734f 4917 break;
4918 default:
4919 assemble(t, &regs[t], ccadj_);
57871462 4920 }
ad49de89 4921 store_regs_bt(regs[t].regmap,regs[t].dirty,ba[i]+4);
4922 load_regs_bt(regs[t].regmap,regs[t].dirty,ba[i]+4);
4923 if(internal_branch(ba[i]+4))
57871462 4924 assem_debug("branch: internal\n");
4925 else
4926 assem_debug("branch: external\n");
ad49de89 4927 assert(internal_branch(ba[i]+4));
4928 add_to_linker(out,ba[i]+4,internal_branch(ba[i]+4));
57871462 4929 emit_jmp(0);
4930}
4931
d1e4ebd9 4932// Load 2 immediates optimizing for small code size
4933static void emit_mov2imm_compact(int imm1,u_int rt1,int imm2,u_int rt2)
4934{
4935 emit_movimm(imm1,rt1);
4936 emit_movimm_from(imm1,rt1,imm2,rt2);
4937}
4938
2330734f 4939static void do_cc(int i, const signed char i_regmap[], int *adj,
4940 int addr, int taken, int invert)
57871462 4941{
2330734f 4942 int count, count_plus2;
b14b6a8f 4943 void *jaddr;
4944 void *idle=NULL;
b6e87b2b 4945 int t=0;
cf95b4f0 4946 if(dops[i].itype==RJUMP)
57871462 4947 {
4948 *adj=0;
4949 }
4950 //if(ba[i]>=start && ba[i]<(start+slen*4))
ad49de89 4951 if(internal_branch(ba[i]))
57871462 4952 {
b6e87b2b 4953 t=(ba[i]-start)>>2;
2330734f 4954 if(dops[t].is_ds) *adj=-CLOCK_ADJUST(1); // Branch into delay slot adds an extra cycle
57871462 4955 else *adj=ccadj[t];
4956 }
4957 else
4958 {
4959 *adj=0;
4960 }
2330734f 4961 count = ccadj[i];
4962 count_plus2 = count + CLOCK_ADJUST(2);
57871462 4963 if(taken==TAKEN && i==(ba[i]-start)>>2 && source[i+1]==0) {
4964 // Idle loop
4965 if(count&1) emit_addimm_and_set_flags(2*(count+2),HOST_CCREG);
b14b6a8f 4966 idle=out;
57871462 4967 //emit_subfrommem(&idlecount,HOST_CCREG); // Count idle cycles
4968 emit_andimm(HOST_CCREG,3,HOST_CCREG);
b14b6a8f 4969 jaddr=out;
57871462 4970 emit_jmp(0);
4971 }
4972 else if(*adj==0||invert) {
2330734f 4973 int cycles = count_plus2;
b6e87b2b 4974 // faster loop HACK
bb4f300c 4975#if 0
b6e87b2b 4976 if (t&&*adj) {
4977 int rel=t-i;
4978 if(-NO_CYCLE_PENALTY_THR<rel&&rel<0)
2330734f 4979 cycles=*adj+count+2-*adj;
b6e87b2b 4980 }
bb4f300c 4981#endif
2330734f 4982 emit_addimm_and_set_flags(cycles, HOST_CCREG);
4983 jaddr = out;
57871462 4984 emit_jns(0);
4985 }
4986 else
4987 {
2330734f 4988 emit_cmpimm(HOST_CCREG, -count_plus2);
4989 jaddr = out;
57871462 4990 emit_jns(0);
4991 }
2330734f 4992 add_stub(CC_STUB,jaddr,idle?idle:out,(*adj==0||invert||idle)?0:count_plus2,i,addr,taken,0);
57871462 4993}
4994
b14b6a8f 4995static void do_ccstub(int n)
57871462 4996{
4997 literal_pool(256);
d1e4ebd9 4998 assem_debug("do_ccstub %x\n",start+(u_int)stubs[n].b*4);
b14b6a8f 4999 set_jump_target(stubs[n].addr, out);
5000 int i=stubs[n].b;
5001 if(stubs[n].d==NULLDS) {
57871462 5002 // Delay slot instruction is nullified ("likely" branch)
ad49de89 5003 wb_dirtys(regs[i].regmap,regs[i].dirty);
57871462 5004 }
b14b6a8f 5005 else if(stubs[n].d!=TAKEN) {
ad49de89 5006 wb_dirtys(branch_regs[i].regmap,branch_regs[i].dirty);
57871462 5007 }
5008 else {
ad49de89 5009 if(internal_branch(ba[i]))
5010 wb_needed_dirtys(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]);
57871462 5011 }
b14b6a8f 5012 if(stubs[n].c!=-1)
57871462 5013 {
5014 // Save PC as return address
b14b6a8f 5015 emit_movimm(stubs[n].c,EAX);
643aeae3 5016 emit_writeword(EAX,&pcaddr);
57871462 5017 }
5018 else
5019 {
5020 // Return address depends on which way the branch goes
cf95b4f0 5021 if(dops[i].itype==CJUMP||dops[i].itype==SJUMP)
57871462 5022 {
cf95b4f0 5023 int s1l=get_reg(branch_regs[i].regmap,dops[i].rs1);
5024 int s2l=get_reg(branch_regs[i].regmap,dops[i].rs2);
5025 if(dops[i].rs1==0)
57871462 5026 {
ad49de89 5027 s1l=s2l;
5028 s2l=-1;
57871462 5029 }
cf95b4f0 5030 else if(dops[i].rs2==0)
57871462 5031 {
ad49de89 5032 s2l=-1;
57871462 5033 }
5034 assert(s1l>=0);
5035 #ifdef DESTRUCTIVE_WRITEBACK
cf95b4f0 5036 if(dops[i].rs1) {
ad49de89 5037 if((branch_regs[i].dirty>>s1l)&&1)
cf95b4f0 5038 emit_loadreg(dops[i].rs1,s1l);
9f51b4b9 5039 }
57871462 5040 else {
ad49de89 5041 if((branch_regs[i].dirty>>s1l)&1)
cf95b4f0 5042 emit_loadreg(dops[i].rs2,s1l);
57871462 5043 }
5044 if(s2l>=0)
ad49de89 5045 if((branch_regs[i].dirty>>s2l)&1)
cf95b4f0 5046 emit_loadreg(dops[i].rs2,s2l);
57871462 5047 #endif
5048 int hr=0;
5194fb95 5049 int addr=-1,alt=-1,ntaddr=-1;
57871462 5050 while(hr<HOST_REGS)
5051 {
5052 if(hr!=EXCLUDE_REG && hr!=HOST_CCREG &&
9de8a0c3 5053 branch_regs[i].regmap[hr]!=dops[i].rs1 &&
5054 branch_regs[i].regmap[hr]!=dops[i].rs2 )
57871462 5055 {
5056 addr=hr++;break;
5057 }
5058 hr++;
5059 }
5060 while(hr<HOST_REGS)
5061 {
5062 if(hr!=EXCLUDE_REG && hr!=HOST_CCREG &&
9de8a0c3 5063 branch_regs[i].regmap[hr]!=dops[i].rs1 &&
5064 branch_regs[i].regmap[hr]!=dops[i].rs2 )
57871462 5065 {
5066 alt=hr++;break;
5067 }
5068 hr++;
5069 }
cf95b4f0 5070 if((dops[i].opcode&0x2E)==6) // BLEZ/BGTZ needs another register
57871462 5071 {
5072 while(hr<HOST_REGS)
5073 {
5074 if(hr!=EXCLUDE_REG && hr!=HOST_CCREG &&
9de8a0c3 5075 branch_regs[i].regmap[hr]!=dops[i].rs1 &&
5076 branch_regs[i].regmap[hr]!=dops[i].rs2 )
57871462 5077 {
5078 ntaddr=hr;break;
5079 }
5080 hr++;
5081 }
5082 assert(hr<HOST_REGS);
5083 }
cf95b4f0 5084 if((dops[i].opcode&0x2f)==4) // BEQ
57871462 5085 {
5086 #ifdef HAVE_CMOV_IMM
ad49de89 5087 if(s2l>=0) emit_cmp(s1l,s2l);
5088 else emit_test(s1l,s1l);
5089 emit_cmov2imm_e_ne_compact(ba[i],start+i*4+8,addr);
5090 #else
5091 emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
5092 if(s2l>=0) emit_cmp(s1l,s2l);
5093 else emit_test(s1l,s1l);
5094 emit_cmovne_reg(alt,addr);
57871462 5095 #endif
57871462 5096 }
cf95b4f0 5097 if((dops[i].opcode&0x2f)==5) // BNE
57871462 5098 {
5099 #ifdef HAVE_CMOV_IMM
ad49de89 5100 if(s2l>=0) emit_cmp(s1l,s2l);
5101 else emit_test(s1l,s1l);
5102 emit_cmov2imm_e_ne_compact(start+i*4+8,ba[i],addr);
5103 #else
5104 emit_mov2imm_compact(start+i*4+8,addr,ba[i],alt);
5105 if(s2l>=0) emit_cmp(s1l,s2l);
5106 else emit_test(s1l,s1l);
5107 emit_cmovne_reg(alt,addr);
57871462 5108 #endif
57871462 5109 }
cf95b4f0 5110 if((dops[i].opcode&0x2f)==6) // BLEZ
57871462 5111 {
5112 //emit_movimm(ba[i],alt);
5113 //emit_movimm(start+i*4+8,addr);
5114 emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
5115 emit_cmpimm(s1l,1);
57871462 5116 emit_cmovl_reg(alt,addr);
57871462 5117 }
cf95b4f0 5118 if((dops[i].opcode&0x2f)==7) // BGTZ
57871462 5119 {
5120 //emit_movimm(ba[i],addr);
5121 //emit_movimm(start+i*4+8,ntaddr);
5122 emit_mov2imm_compact(ba[i],addr,start+i*4+8,ntaddr);
5123 emit_cmpimm(s1l,1);
57871462 5124 emit_cmovl_reg(ntaddr,addr);
57871462 5125 }
cf95b4f0 5126 if((dops[i].opcode==1)&&(dops[i].opcode2&0x2D)==0) // BLTZ
57871462 5127 {
5128 //emit_movimm(ba[i],alt);
5129 //emit_movimm(start+i*4+8,addr);
5130 emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
ad49de89 5131 emit_test(s1l,s1l);
57871462 5132 emit_cmovs_reg(alt,addr);
5133 }
cf95b4f0 5134 if((dops[i].opcode==1)&&(dops[i].opcode2&0x2D)==1) // BGEZ
57871462 5135 {
5136 //emit_movimm(ba[i],addr);
5137 //emit_movimm(start+i*4+8,alt);
5138 emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
ad49de89 5139 emit_test(s1l,s1l);
57871462 5140 emit_cmovs_reg(alt,addr);
5141 }
cf95b4f0 5142 if(dops[i].opcode==0x11 && dops[i].opcode2==0x08 ) {
57871462 5143 if(source[i]&0x10000) // BC1T
5144 {
5145 //emit_movimm(ba[i],alt);
5146 //emit_movimm(start+i*4+8,addr);
5147 emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
5148 emit_testimm(s1l,0x800000);
5149 emit_cmovne_reg(alt,addr);
5150 }
5151 else // BC1F
5152 {
5153 //emit_movimm(ba[i],addr);
5154 //emit_movimm(start+i*4+8,alt);
5155 emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
5156 emit_testimm(s1l,0x800000);
5157 emit_cmovne_reg(alt,addr);
5158 }
5159 }
643aeae3 5160 emit_writeword(addr,&pcaddr);
57871462 5161 }
5162 else
cf95b4f0 5163 if(dops[i].itype==RJUMP)
57871462 5164 {
cf95b4f0 5165 int r=get_reg(branch_regs[i].regmap,dops[i].rs1);
4919de1e 5166 if (ds_writes_rjump_rs(i)) {
57871462 5167 r=get_reg(branch_regs[i].regmap,RTEMP);
5168 }
643aeae3 5169 emit_writeword(r,&pcaddr);
57871462 5170 }
7c3a5182 5171 else {SysPrintf("Unknown branch type in do_ccstub\n");abort();}
57871462 5172 }
5173 // Update cycle count
5174 assert(branch_regs[i].regmap[HOST_CCREG]==CCREG||branch_regs[i].regmap[HOST_CCREG]==-1);
2330734f 5175 if(stubs[n].a) emit_addimm(HOST_CCREG,(int)stubs[n].a,HOST_CCREG);
2a014d73 5176 emit_far_call(cc_interrupt);
2330734f 5177 if(stubs[n].a) emit_addimm(HOST_CCREG,-(int)stubs[n].a,HOST_CCREG);
b14b6a8f 5178 if(stubs[n].d==TAKEN) {
ad49de89 5179 if(internal_branch(ba[i]))
57871462 5180 load_needed_regs(branch_regs[i].regmap,regs[(ba[i]-start)>>2].regmap_entry);
cf95b4f0 5181 else if(dops[i].itype==RJUMP) {
57871462 5182 if(get_reg(branch_regs[i].regmap,RTEMP)>=0)
643aeae3 5183 emit_readword(&pcaddr,get_reg(branch_regs[i].regmap,RTEMP));
57871462 5184 else
cf95b4f0 5185 emit_loadreg(dops[i].rs1,get_reg(branch_regs[i].regmap,dops[i].rs1));
57871462 5186 }
b14b6a8f 5187 }else if(stubs[n].d==NOTTAKEN) {
57871462 5188 if(i<slen-2) load_needed_regs(branch_regs[i].regmap,regmap_pre[i+2]);
5189 else load_all_regs(branch_regs[i].regmap);
b14b6a8f 5190 }else if(stubs[n].d==NULLDS) {
57871462 5191 // Delay slot instruction is nullified ("likely" branch)
5192 if(i<slen-2) load_needed_regs(regs[i].regmap,regmap_pre[i+2]);
5193 else load_all_regs(regs[i].regmap);
5194 }else{
5195 load_all_regs(branch_regs[i].regmap);
5196 }
d1e4ebd9 5197 if (stubs[n].retaddr)
5198 emit_jmp(stubs[n].retaddr);
5199 else
5200 do_jump_vaddr(stubs[n].e);
57871462 5201}
5202
104df9d3 5203static void add_to_linker(void *addr, u_int target, int is_internal)
57871462 5204{
643aeae3 5205 assert(linkcount < ARRAY_SIZE(link_addr));
5206 link_addr[linkcount].addr = addr;
5207 link_addr[linkcount].target = target;
104df9d3 5208 link_addr[linkcount].internal = is_internal;
57871462 5209 linkcount++;
5210}
5211
eba830cd 5212static void ujump_assemble_write_ra(int i)
5213{
5214 int rt;
5215 unsigned int return_address;
5216 rt=get_reg(branch_regs[i].regmap,31);
5217 assem_debug("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5218 //assert(rt>=0);
5219 return_address=start+i*4+8;
5220 if(rt>=0) {
5221 #ifdef USE_MINI_HT
cf95b4f0 5222 if(internal_branch(return_address)&&dops[i+1].rt1!=31) {
eba830cd 5223 int temp=-1; // note: must be ds-safe
5224 #ifdef HOST_TEMPREG
5225 temp=HOST_TEMPREG;
5226 #endif
5227 if(temp>=0) do_miniht_insert(return_address,rt,temp);
5228 else emit_movimm(return_address,rt);
5229 }
5230 else
5231 #endif
5232 {
5233 #ifdef REG_PREFETCH
9f51b4b9 5234 if(temp>=0)
eba830cd 5235 {
643aeae3 5236 if(i_regmap[temp]!=PTEMP) emit_movimm((uintptr_t)hash_table_get(return_address),temp);
eba830cd 5237 }
5238 #endif
5239 emit_movimm(return_address,rt); // PC into link register
5240 #ifdef IMM_PREFETCH
df4dc2b1 5241 emit_prefetch(hash_table_get(return_address));
eba830cd 5242 #endif
5243 }
5244 }
5245}
5246
2330734f 5247static void ujump_assemble(int i, const struct regstat *i_regs)
57871462 5248{
eba830cd 5249 int ra_done=0;
57871462 5250 if(i==(ba[i]-start)>>2) assem_debug("idle loop\n");
5251 address_generation(i+1,i_regs,regs[i].regmap_entry);
5252 #ifdef REG_PREFETCH
5253 int temp=get_reg(branch_regs[i].regmap,PTEMP);
cf95b4f0 5254 if(dops[i].rt1==31&&temp>=0)
57871462 5255 {
581335b0 5256 signed char *i_regmap=i_regs->regmap;
57871462 5257 int return_address=start+i*4+8;
9f51b4b9 5258 if(get_reg(branch_regs[i].regmap,31)>0)
643aeae3 5259 if(i_regmap[temp]==PTEMP) emit_movimm((uintptr_t)hash_table_get(return_address),temp);
57871462 5260 }
5261 #endif
cf95b4f0 5262 if(dops[i].rt1==31&&(dops[i].rt1==dops[i+1].rs1||dops[i].rt1==dops[i+1].rs2)) {
eba830cd 5263 ujump_assemble_write_ra(i); // writeback ra for DS
5264 ra_done=1;
57871462 5265 }
4ef8f67d 5266 ds_assemble(i+1,i_regs);
5267 uint64_t bc_unneeded=branch_regs[i].u;
cf95b4f0 5268 bc_unneeded|=1|(1LL<<dops[i].rt1);
ad49de89 5269 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,bc_unneeded);
53358c1d 5270 load_reg(regs[i].regmap,branch_regs[i].regmap,CCREG);
cf95b4f0 5271 if(!ra_done&&dops[i].rt1==31)
eba830cd 5272 ujump_assemble_write_ra(i);
57871462 5273 int cc,adj;
5274 cc=get_reg(branch_regs[i].regmap,CCREG);
5275 assert(cc==HOST_CCREG);
ad49de89 5276 store_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]);
57871462 5277 #ifdef REG_PREFETCH
cf95b4f0 5278 if(dops[i].rt1==31&&temp>=0) emit_prefetchreg(temp);
57871462 5279 #endif
5280 do_cc(i,branch_regs[i].regmap,&adj,ba[i],TAKEN,0);
2330734f 5281 if(adj) emit_addimm(cc, ccadj[i] + CLOCK_ADJUST(2) - adj, cc);
ad49de89 5282 load_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]);
5283 if(internal_branch(ba[i]))
57871462 5284 assem_debug("branch: internal\n");
5285 else
5286 assem_debug("branch: external\n");
cf95b4f0 5287 if (internal_branch(ba[i]) && dops[(ba[i]-start)>>2].is_ds) {
57871462 5288 ds_assemble_entry(i);
5289 }
5290 else {
ad49de89 5291 add_to_linker(out,ba[i],internal_branch(ba[i]));
57871462 5292 emit_jmp(0);
5293 }
5294}
5295
eba830cd 5296static void rjump_assemble_write_ra(int i)
5297{
5298 int rt,return_address;
cf95b4f0 5299 assert(dops[i+1].rt1!=dops[i].rt1);
5300 assert(dops[i+1].rt2!=dops[i].rt1);
5301 rt=get_reg(branch_regs[i].regmap,dops[i].rt1);
eba830cd 5302 assem_debug("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5303 assert(rt>=0);
5304 return_address=start+i*4+8;
5305 #ifdef REG_PREFETCH
9f51b4b9 5306 if(temp>=0)
eba830cd 5307 {
643aeae3 5308 if(i_regmap[temp]!=PTEMP) emit_movimm((uintptr_t)hash_table_get(return_address),temp);
eba830cd 5309 }
5310 #endif
5311 emit_movimm(return_address,rt); // PC into link register
5312 #ifdef IMM_PREFETCH
df4dc2b1 5313 emit_prefetch(hash_table_get(return_address));
eba830cd 5314 #endif
5315}
5316
2330734f 5317static void rjump_assemble(int i, const struct regstat *i_regs)
57871462 5318{
57871462 5319 int temp;
581335b0 5320 int rs,cc;
eba830cd 5321 int ra_done=0;
cf95b4f0 5322 rs=get_reg(branch_regs[i].regmap,dops[i].rs1);
57871462 5323 assert(rs>=0);
4919de1e 5324 if (ds_writes_rjump_rs(i)) {
57871462 5325 // Delay slot abuse, make a copy of the branch address register
5326 temp=get_reg(branch_regs[i].regmap,RTEMP);
5327 assert(temp>=0);
5328 assert(regs[i].regmap[temp]==RTEMP);
5329 emit_mov(rs,temp);
5330 rs=temp;
5331 }
5332 address_generation(i+1,i_regs,regs[i].regmap_entry);
5333 #ifdef REG_PREFETCH
cf95b4f0 5334 if(dops[i].rt1==31)
57871462 5335 {
5336 if((temp=get_reg(branch_regs[i].regmap,PTEMP))>=0) {
581335b0 5337 signed char *i_regmap=i_regs->regmap;
57871462 5338 int return_address=start+i*4+8;
643aeae3 5339 if(i_regmap[temp]==PTEMP) emit_movimm((uintptr_t)hash_table_get(return_address),temp);
57871462 5340 }
5341 }
5342 #endif
5343 #ifdef USE_MINI_HT
cf95b4f0 5344 if(dops[i].rs1==31) {
57871462 5345 int rh=get_reg(regs[i].regmap,RHASH);
5346 if(rh>=0) do_preload_rhash(rh);
5347 }
5348 #endif
cf95b4f0 5349 if(dops[i].rt1!=0&&(dops[i].rt1==dops[i+1].rs1||dops[i].rt1==dops[i+1].rs2)) {
eba830cd 5350 rjump_assemble_write_ra(i);
5351 ra_done=1;
57871462 5352 }
d5910d5d 5353 ds_assemble(i+1,i_regs);
5354 uint64_t bc_unneeded=branch_regs[i].u;
cf95b4f0 5355 bc_unneeded|=1|(1LL<<dops[i].rt1);
5356 bc_unneeded&=~(1LL<<dops[i].rs1);
ad49de89 5357 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,bc_unneeded);
cf95b4f0 5358 load_regs(regs[i].regmap,branch_regs[i].regmap,dops[i].rs1,CCREG);
5359 if(!ra_done&&dops[i].rt1!=0)
eba830cd 5360 rjump_assemble_write_ra(i);
57871462 5361 cc=get_reg(branch_regs[i].regmap,CCREG);
5362 assert(cc==HOST_CCREG);
581335b0 5363 (void)cc;
57871462 5364 #ifdef USE_MINI_HT
5365 int rh=get_reg(branch_regs[i].regmap,RHASH);
5366 int ht=get_reg(branch_regs[i].regmap,RHTBL);
cf95b4f0 5367 if(dops[i].rs1==31) {
57871462 5368 if(regs[i].regmap[rh]!=RHASH) do_preload_rhash(rh);
5369 do_preload_rhtbl(ht);
5370 do_rhash(rs,rh);
5371 }
5372 #endif
ad49de89 5373 store_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,-1);
57871462 5374 #ifdef DESTRUCTIVE_WRITEBACK
ad49de89 5375 if((branch_regs[i].dirty>>rs)&1) {
cf95b4f0 5376 if(dops[i].rs1!=dops[i+1].rt1&&dops[i].rs1!=dops[i+1].rt2) {
5377 emit_loadreg(dops[i].rs1,rs);
57871462 5378 }
5379 }
5380 #endif
5381 #ifdef REG_PREFETCH
cf95b4f0 5382 if(dops[i].rt1==31&&temp>=0) emit_prefetchreg(temp);
57871462 5383 #endif
5384 #ifdef USE_MINI_HT
cf95b4f0 5385 if(dops[i].rs1==31) {
57871462 5386 do_miniht_load(ht,rh);
5387 }
5388 #endif
5389 //do_cc(i,branch_regs[i].regmap,&adj,-1,TAKEN);
5390 //if(adj) emit_addimm(cc,2*(ccadj[i]+2-adj),cc); // ??? - Shouldn't happen
5391 //assert(adj==0);
2330734f 5392 emit_addimm_and_set_flags(ccadj[i] + CLOCK_ADJUST(2), HOST_CCREG);
d1e4ebd9 5393 add_stub(CC_STUB,out,NULL,0,i,-1,TAKEN,rs);
55a695d9 5394 if(dops[i+1].itype==COP0 && dops[i+1].opcode2==0x10)
911f2d55 5395 // special case for RFE
5396 emit_jmp(0);
5397 else
71e490c5 5398 emit_jns(0);
ad49de89 5399 //load_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,-1);
57871462 5400 #ifdef USE_MINI_HT
cf95b4f0 5401 if(dops[i].rs1==31) {
57871462 5402 do_miniht_jump(rs,rh,ht);
5403 }
5404 else
5405 #endif
5406 {
d1e4ebd9 5407 do_jump_vaddr(rs);
57871462 5408 }
57871462 5409 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
cf95b4f0 5410 if(dops[i].rt1!=31&&i<slen-2&&(((u_int)out)&7)) emit_mov(13,13);
57871462 5411 #endif
5412}
5413
2330734f 5414static void cjump_assemble(int i, const struct regstat *i_regs)
57871462 5415{
2330734f 5416 const signed char *i_regmap = i_regs->regmap;
57871462 5417 int cc;
5418 int match;
ad49de89 5419 match=match_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]);
57871462 5420 assem_debug("match=%d\n",match);
ad49de89 5421 int s1l,s2l;
57871462 5422 int unconditional=0,nop=0;
57871462 5423 int invert=0;
ad49de89 5424 int internal=internal_branch(ba[i]);
57871462 5425 if(i==(ba[i]-start)>>2) assem_debug("idle loop\n");
57871462 5426 if(!match) invert=1;
5427 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5428 if(i>(ba[i]-start)>>2) invert=1;
5429 #endif
3968e69e 5430 #ifdef __aarch64__
5431 invert=1; // because of near cond. branches
5432 #endif
9f51b4b9 5433
cf95b4f0 5434 if(dops[i].ooo) {
5435 s1l=get_reg(branch_regs[i].regmap,dops[i].rs1);
5436 s2l=get_reg(branch_regs[i].regmap,dops[i].rs2);
57871462 5437 }
5438 else {
cf95b4f0 5439 s1l=get_reg(i_regmap,dops[i].rs1);
5440 s2l=get_reg(i_regmap,dops[i].rs2);
57871462 5441 }
cf95b4f0 5442 if(dops[i].rs1==0&&dops[i].rs2==0)
57871462 5443 {
cf95b4f0 5444 if(dops[i].opcode&1) nop=1;
57871462 5445 else unconditional=1;
cf95b4f0 5446 //assert(dops[i].opcode!=5);
5447 //assert(dops[i].opcode!=7);
5448 //assert(dops[i].opcode!=0x15);
5449 //assert(dops[i].opcode!=0x17);
57871462 5450 }
cf95b4f0 5451 else if(dops[i].rs1==0)
57871462 5452 {
ad49de89 5453 s1l=s2l;
5454 s2l=-1;
57871462 5455 }
cf95b4f0 5456 else if(dops[i].rs2==0)
57871462 5457 {
ad49de89 5458 s2l=-1;
57871462 5459 }
5460
cf95b4f0 5461 if(dops[i].ooo) {
57871462 5462 // Out of order execution (delay slot first)
5463 //printf("OOOE\n");
5464 address_generation(i+1,i_regs,regs[i].regmap_entry);
5465 ds_assemble(i+1,i_regs);
5466 int adj;
5467 uint64_t bc_unneeded=branch_regs[i].u;
cf95b4f0 5468 bc_unneeded&=~((1LL<<dops[i].rs1)|(1LL<<dops[i].rs2));
57871462 5469 bc_unneeded|=1;
ad49de89 5470 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,bc_unneeded);
cf95b4f0 5471 load_regs(regs[i].regmap,branch_regs[i].regmap,dops[i].rs1,dops[i].rs2);
53358c1d 5472 load_reg(regs[i].regmap,branch_regs[i].regmap,CCREG);
57871462 5473 cc=get_reg(branch_regs[i].regmap,CCREG);
5474 assert(cc==HOST_CCREG);
9f51b4b9 5475 if(unconditional)
ad49de89 5476 store_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]);
57871462 5477 //do_cc(i,branch_regs[i].regmap,&adj,unconditional?ba[i]:-1,unconditional);
5478 //assem_debug("cycle count (adj)\n");
5479 if(unconditional) {
5480 do_cc(i,branch_regs[i].regmap,&adj,ba[i],TAKEN,0);
5481 if(i!=(ba[i]-start)>>2 || source[i+1]!=0) {
2330734f 5482 if(adj) emit_addimm(cc, ccadj[i] + CLOCK_ADJUST(2) - adj, cc);
ad49de89 5483 load_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]);
57871462 5484 if(internal)
5485 assem_debug("branch: internal\n");
5486 else
5487 assem_debug("branch: external\n");
cf95b4f0 5488 if (internal && dops[(ba[i]-start)>>2].is_ds) {
57871462 5489 ds_assemble_entry(i);
5490 }
5491 else {
643aeae3 5492 add_to_linker(out,ba[i],internal);
57871462 5493 emit_jmp(0);
5494 }
5495 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5496 if(((u_int)out)&7) emit_addnop(0);
5497 #endif
5498 }
5499 }
5500 else if(nop) {
2330734f 5501 emit_addimm_and_set_flags(ccadj[i] + CLOCK_ADJUST(2), cc);
b14b6a8f 5502 void *jaddr=out;
57871462 5503 emit_jns(0);
b14b6a8f 5504 add_stub(CC_STUB,jaddr,out,0,i,start+i*4+8,NOTTAKEN,0);
57871462 5505 }
5506 else {
df4dc2b1 5507 void *taken = NULL, *nottaken = NULL, *nottaken1 = NULL;
57871462 5508 do_cc(i,branch_regs[i].regmap,&adj,-1,0,invert);
2330734f 5509 if(adj&&!invert) emit_addimm(cc, ccadj[i] + CLOCK_ADJUST(2) - adj, cc);
9f51b4b9 5510
57871462 5511 //printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5512 assert(s1l>=0);
cf95b4f0 5513 if(dops[i].opcode==4) // BEQ
57871462 5514 {
5515 if(s2l>=0) emit_cmp(s1l,s2l);
5516 else emit_test(s1l,s1l);
5517 if(invert){
df4dc2b1 5518 nottaken=out;
7c3a5182 5519 emit_jne(DJT_1);
57871462 5520 }else{
643aeae3 5521 add_to_linker(out,ba[i],internal);
57871462 5522 emit_jeq(0);
5523 }
5524 }
cf95b4f0 5525 if(dops[i].opcode==5) // BNE
57871462 5526 {
5527 if(s2l>=0) emit_cmp(s1l,s2l);
5528 else emit_test(s1l,s1l);
5529 if(invert){
df4dc2b1 5530 nottaken=out;
7c3a5182 5531 emit_jeq(DJT_1);
57871462 5532 }else{
643aeae3 5533 add_to_linker(out,ba[i],internal);
57871462 5534 emit_jne(0);
5535 }
5536 }
cf95b4f0 5537 if(dops[i].opcode==6) // BLEZ
57871462 5538 {
5539 emit_cmpimm(s1l,1);
5540 if(invert){
df4dc2b1 5541 nottaken=out;
7c3a5182 5542 emit_jge(DJT_1);
57871462 5543 }else{
643aeae3 5544 add_to_linker(out,ba[i],internal);
57871462 5545 emit_jl(0);
5546 }
5547 }
cf95b4f0 5548 if(dops[i].opcode==7) // BGTZ
57871462 5549 {
5550 emit_cmpimm(s1l,1);
5551 if(invert){
df4dc2b1 5552 nottaken=out;
7c3a5182 5553 emit_jl(DJT_1);
57871462 5554 }else{
643aeae3 5555 add_to_linker(out,ba[i],internal);
57871462 5556 emit_jge(0);
5557 }
5558 }
5559 if(invert) {
df4dc2b1 5560 if(taken) set_jump_target(taken, out);
57871462 5561 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
cf95b4f0 5562 if (match && (!internal || !dops[(ba[i]-start)>>2].is_ds)) {
57871462 5563 if(adj) {
2330734f 5564 emit_addimm(cc,-adj,cc);
643aeae3 5565 add_to_linker(out,ba[i],internal);
57871462 5566 }else{
5567 emit_addnop(13);
643aeae3 5568 add_to_linker(out,ba[i],internal*2);
57871462 5569 }
5570 emit_jmp(0);
5571 }else
5572 #endif
5573 {
2330734f 5574 if(adj) emit_addimm(cc,-adj,cc);
ad49de89 5575 store_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]);
5576 load_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]);
57871462 5577 if(internal)
5578 assem_debug("branch: internal\n");
5579 else
5580 assem_debug("branch: external\n");
cf95b4f0 5581 if (internal && dops[(ba[i] - start) >> 2].is_ds) {
57871462 5582 ds_assemble_entry(i);
5583 }
5584 else {
643aeae3 5585 add_to_linker(out,ba[i],internal);
57871462 5586 emit_jmp(0);
5587 }
5588 }
df4dc2b1 5589 set_jump_target(nottaken, out);
57871462 5590 }
5591
df4dc2b1 5592 if(nottaken1) set_jump_target(nottaken1, out);
57871462 5593 if(adj) {
2330734f 5594 if(!invert) emit_addimm(cc,adj,cc);
57871462 5595 }
5596 } // (!unconditional)
5597 } // if(ooo)
5598 else
5599 {
5600 // In-order execution (branch first)
df4dc2b1 5601 void *taken = NULL, *nottaken = NULL, *nottaken1 = NULL;
57871462 5602 if(!unconditional&&!nop) {
57871462 5603 //printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5604 assert(s1l>=0);
cf95b4f0 5605 if((dops[i].opcode&0x2f)==4) // BEQ
57871462 5606 {
5607 if(s2l>=0) emit_cmp(s1l,s2l);
5608 else emit_test(s1l,s1l);
df4dc2b1 5609 nottaken=out;
7c3a5182 5610 emit_jne(DJT_2);
57871462 5611 }
cf95b4f0 5612 if((dops[i].opcode&0x2f)==5) // BNE
57871462 5613 {
5614 if(s2l>=0) emit_cmp(s1l,s2l);
5615 else emit_test(s1l,s1l);
df4dc2b1 5616 nottaken=out;
7c3a5182 5617 emit_jeq(DJT_2);
57871462 5618 }
cf95b4f0 5619 if((dops[i].opcode&0x2f)==6) // BLEZ
57871462 5620 {
5621 emit_cmpimm(s1l,1);
df4dc2b1 5622 nottaken=out;
7c3a5182 5623 emit_jge(DJT_2);
57871462 5624 }
cf95b4f0 5625 if((dops[i].opcode&0x2f)==7) // BGTZ
57871462 5626 {
5627 emit_cmpimm(s1l,1);
df4dc2b1 5628 nottaken=out;
7c3a5182 5629 emit_jl(DJT_2);
57871462 5630 }
5631 } // if(!unconditional)
5632 int adj;
5633 uint64_t ds_unneeded=branch_regs[i].u;
cf95b4f0 5634 ds_unneeded&=~((1LL<<dops[i+1].rs1)|(1LL<<dops[i+1].rs2));
57871462 5635 ds_unneeded|=1;
57871462 5636 // branch taken
5637 if(!nop) {
df4dc2b1 5638 if(taken) set_jump_target(taken, out);
57871462 5639 assem_debug("1:\n");
ad49de89 5640 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,ds_unneeded);
57871462 5641 // load regs
cf95b4f0 5642 load_regs(regs[i].regmap,branch_regs[i].regmap,dops[i+1].rs1,dops[i+1].rs2);
57871462 5643 address_generation(i+1,&branch_regs[i],0);
37387d8b 5644 if (ram_offset)
53358c1d 5645 load_reg(regs[i].regmap,branch_regs[i].regmap,ROREG);
ad49de89 5646 load_regs(regs[i].regmap,branch_regs[i].regmap,CCREG,INVCP);
57871462 5647 ds_assemble(i+1,&branch_regs[i]);
5648 cc=get_reg(branch_regs[i].regmap,CCREG);
5649 if(cc==-1) {
5650 emit_loadreg(CCREG,cc=HOST_CCREG);
5651 // CHECK: Is the following instruction (fall thru) allocated ok?
5652 }
5653 assert(cc==HOST_CCREG);
ad49de89 5654 store_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]);
57871462 5655 do_cc(i,i_regmap,&adj,ba[i],TAKEN,0);
5656 assem_debug("cycle count (adj)\n");
2330734f 5657 if(adj) emit_addimm(cc, ccadj[i] + CLOCK_ADJUST(2) - adj, cc);
ad49de89 5658 load_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]);
57871462 5659 if(internal)
5660 assem_debug("branch: internal\n");
5661 else
5662 assem_debug("branch: external\n");
cf95b4f0 5663 if (internal && dops[(ba[i] - start) >> 2].is_ds) {
57871462 5664 ds_assemble_entry(i);
5665 }
5666 else {
643aeae3 5667 add_to_linker(out,ba[i],internal);
57871462 5668 emit_jmp(0);
5669 }
5670 }
5671 // branch not taken
57871462 5672 if(!unconditional) {
df4dc2b1 5673 if(nottaken1) set_jump_target(nottaken1, out);
5674 set_jump_target(nottaken, out);
57871462 5675 assem_debug("2:\n");
fe807a8a 5676 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,ds_unneeded);
37387d8b 5677 // load regs
fe807a8a 5678 load_regs(regs[i].regmap,branch_regs[i].regmap,dops[i+1].rs1,dops[i+1].rs2);
5679 address_generation(i+1,&branch_regs[i],0);
37387d8b 5680 if (ram_offset)
53358c1d 5681 load_reg(regs[i].regmap,branch_regs[i].regmap,ROREG);
37387d8b 5682 load_regs(regs[i].regmap,branch_regs[i].regmap,CCREG,INVCP);
fe807a8a 5683 ds_assemble(i+1,&branch_regs[i]);
57871462 5684 cc=get_reg(branch_regs[i].regmap,CCREG);
fe807a8a 5685 if (cc == -1) {
57871462 5686 // Cycle count isn't in a register, temporarily load it then write it out
5687 emit_loadreg(CCREG,HOST_CCREG);
2330734f 5688 emit_addimm_and_set_flags(ccadj[i] + CLOCK_ADJUST(2), HOST_CCREG);
b14b6a8f 5689 void *jaddr=out;
57871462 5690 emit_jns(0);
b14b6a8f 5691 add_stub(CC_STUB,jaddr,out,0,i,start+i*4+8,NOTTAKEN,0);
57871462 5692 emit_storereg(CCREG,HOST_CCREG);
5693 }
5694 else{
5695 cc=get_reg(i_regmap,CCREG);
5696 assert(cc==HOST_CCREG);
2330734f 5697 emit_addimm_and_set_flags(ccadj[i] + CLOCK_ADJUST(2), cc);
b14b6a8f 5698 void *jaddr=out;
57871462 5699 emit_jns(0);
fe807a8a 5700 add_stub(CC_STUB,jaddr,out,0,i,start+i*4+8,NOTTAKEN,0);
57871462 5701 }
5702 }
5703 }
5704}
5705
2330734f 5706static void sjump_assemble(int i, const struct regstat *i_regs)
57871462 5707{
2330734f 5708 const signed char *i_regmap = i_regs->regmap;
57871462 5709 int cc;
5710 int match;
ad49de89 5711 match=match_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]);
2acc46cd 5712 assem_debug("smatch=%d ooo=%d\n", match, dops[i].ooo);
ad49de89 5713 int s1l;
57871462 5714 int unconditional=0,nevertaken=0;
57871462 5715 int invert=0;
ad49de89 5716 int internal=internal_branch(ba[i]);
57871462 5717 if(i==(ba[i]-start)>>2) assem_debug("idle loop\n");
57871462 5718 if(!match) invert=1;
5719 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5720 if(i>(ba[i]-start)>>2) invert=1;
5721 #endif
3968e69e 5722 #ifdef __aarch64__
5723 invert=1; // because of near cond. branches
5724 #endif
57871462 5725
cf95b4f0 5726 //if(dops[i].opcode2>=0x10) return; // FIXME (BxxZAL)
5727 //assert(dops[i].opcode2<0x10||dops[i].rs1==0); // FIXME (BxxZAL)
57871462 5728
cf95b4f0 5729 if(dops[i].ooo) {
5730 s1l=get_reg(branch_regs[i].regmap,dops[i].rs1);
57871462 5731 }
5732 else {
cf95b4f0 5733 s1l=get_reg(i_regmap,dops[i].rs1);
57871462 5734 }
cf95b4f0 5735 if(dops[i].rs1==0)
57871462 5736 {
cf95b4f0 5737 if(dops[i].opcode2&1) unconditional=1;
57871462 5738 else nevertaken=1;
5739 // These are never taken (r0 is never less than zero)
cf95b4f0 5740 //assert(dops[i].opcode2!=0);
5741 //assert(dops[i].opcode2!=2);
5742 //assert(dops[i].opcode2!=0x10);
5743 //assert(dops[i].opcode2!=0x12);
57871462 5744 }
57871462 5745
cf95b4f0 5746 if(dops[i].ooo) {
57871462 5747 // Out of order execution (delay slot first)
5748 //printf("OOOE\n");
5749 address_generation(i+1,i_regs,regs[i].regmap_entry);
5750 ds_assemble(i+1,i_regs);
5751 int adj;
5752 uint64_t bc_unneeded=branch_regs[i].u;
cf95b4f0 5753 bc_unneeded&=~((1LL<<dops[i].rs1)|(1LL<<dops[i].rs2));
57871462 5754 bc_unneeded|=1;
ad49de89 5755 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,bc_unneeded);
cf95b4f0 5756 load_regs(regs[i].regmap,branch_regs[i].regmap,dops[i].rs1,dops[i].rs1);
53358c1d 5757 load_reg(regs[i].regmap,branch_regs[i].regmap,CCREG);
cf95b4f0 5758 if(dops[i].rt1==31) {
57871462 5759 int rt,return_address;
57871462 5760 rt=get_reg(branch_regs[i].regmap,31);
5761 assem_debug("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5762 if(rt>=0) {
5763 // Save the PC even if the branch is not taken
5764 return_address=start+i*4+8;
5765 emit_movimm(return_address,rt); // PC into link register
5766 #ifdef IMM_PREFETCH
df4dc2b1 5767 if(!nevertaken) emit_prefetch(hash_table_get(return_address));
57871462 5768 #endif
5769 }
5770 }
5771 cc=get_reg(branch_regs[i].regmap,CCREG);
5772 assert(cc==HOST_CCREG);
9f51b4b9 5773 if(unconditional)
ad49de89 5774 store_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]);
57871462 5775 //do_cc(i,branch_regs[i].regmap,&adj,unconditional?ba[i]:-1,unconditional);
5776 assem_debug("cycle count (adj)\n");
5777 if(unconditional) {
5778 do_cc(i,branch_regs[i].regmap,&adj,ba[i],TAKEN,0);
5779 if(i!=(ba[i]-start)>>2 || source[i+1]!=0) {
2330734f 5780 if(adj) emit_addimm(cc, ccadj[i] + CLOCK_ADJUST(2) - adj, cc);
ad49de89 5781 load_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]);
57871462 5782 if(internal)
5783 assem_debug("branch: internal\n");
5784 else
5785 assem_debug("branch: external\n");
cf95b4f0 5786 if (internal && dops[(ba[i] - start) >> 2].is_ds) {
57871462 5787 ds_assemble_entry(i);
5788 }
5789 else {
643aeae3 5790 add_to_linker(out,ba[i],internal);
57871462 5791 emit_jmp(0);
5792 }
5793 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5794 if(((u_int)out)&7) emit_addnop(0);
5795 #endif
5796 }
5797 }
5798 else if(nevertaken) {
2330734f 5799 emit_addimm_and_set_flags(ccadj[i] + CLOCK_ADJUST(2), cc);
b14b6a8f 5800 void *jaddr=out;
57871462 5801 emit_jns(0);
b14b6a8f 5802 add_stub(CC_STUB,jaddr,out,0,i,start+i*4+8,NOTTAKEN,0);
57871462 5803 }
5804 else {
df4dc2b1 5805 void *nottaken = NULL;
57871462 5806 do_cc(i,branch_regs[i].regmap,&adj,-1,0,invert);
2330734f 5807 if(adj&&!invert) emit_addimm(cc, ccadj[i] + CLOCK_ADJUST(2) - adj, cc);
57871462 5808 {
5809 assert(s1l>=0);
cf95b4f0 5810 if((dops[i].opcode2&0xf)==0) // BLTZ/BLTZAL
57871462 5811 {
5812 emit_test(s1l,s1l);
5813 if(invert){
df4dc2b1 5814 nottaken=out;
7c3a5182 5815 emit_jns(DJT_1);
57871462 5816 }else{
643aeae3 5817 add_to_linker(out,ba[i],internal);
57871462 5818 emit_js(0);
5819 }
5820 }
cf95b4f0 5821 if((dops[i].opcode2&0xf)==1) // BGEZ/BLTZAL
57871462 5822 {
5823 emit_test(s1l,s1l);
5824 if(invert){
df4dc2b1 5825 nottaken=out;
7c3a5182 5826 emit_js(DJT_1);
57871462 5827 }else{
643aeae3 5828 add_to_linker(out,ba[i],internal);
57871462 5829 emit_jns(0);
5830 }
5831 }
ad49de89 5832 }
9f51b4b9 5833
57871462 5834 if(invert) {
5835 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
cf95b4f0 5836 if (match && (!internal || !dops[(ba[i] - start) >> 2].is_ds)) {
57871462 5837 if(adj) {
2330734f 5838 emit_addimm(cc,-adj,cc);
643aeae3 5839 add_to_linker(out,ba[i],internal);
57871462 5840 }else{
5841 emit_addnop(13);
643aeae3 5842 add_to_linker(out,ba[i],internal*2);
57871462 5843 }
5844 emit_jmp(0);
5845 }else
5846 #endif
5847 {
2330734f 5848 if(adj) emit_addimm(cc,-adj,cc);
ad49de89 5849 store_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]);
5850 load_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]);
57871462 5851 if(internal)
5852 assem_debug("branch: internal\n");
5853 else
5854 assem_debug("branch: external\n");
cf95b4f0 5855 if (internal && dops[(ba[i] - start) >> 2].is_ds) {
57871462 5856 ds_assemble_entry(i);
5857 }
5858 else {
643aeae3 5859 add_to_linker(out,ba[i],internal);
57871462 5860 emit_jmp(0);
5861 }
5862 }
df4dc2b1 5863 set_jump_target(nottaken, out);
57871462 5864 }
5865
5866 if(adj) {
2330734f 5867 if(!invert) emit_addimm(cc,adj,cc);
57871462 5868 }
5869 } // (!unconditional)
5870 } // if(ooo)
5871 else
5872 {
5873 // In-order execution (branch first)
5874 //printf("IOE\n");
df4dc2b1 5875 void *nottaken = NULL;
cf95b4f0 5876 if(dops[i].rt1==31) {
a6491170 5877 int rt,return_address;
a6491170 5878 rt=get_reg(branch_regs[i].regmap,31);
5879 if(rt>=0) {
5880 // Save the PC even if the branch is not taken
5881 return_address=start+i*4+8;
5882 emit_movimm(return_address,rt); // PC into link register
5883 #ifdef IMM_PREFETCH
df4dc2b1 5884 emit_prefetch(hash_table_get(return_address));
a6491170 5885 #endif
5886 }
5887 }
57871462 5888 if(!unconditional) {
5889 //printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
57871462 5890 assert(s1l>=0);
cf95b4f0 5891 if((dops[i].opcode2&0x0d)==0) // BLTZ/BLTZL/BLTZAL/BLTZALL
57871462 5892 {
5893 emit_test(s1l,s1l);
df4dc2b1 5894 nottaken=out;
7c3a5182 5895 emit_jns(DJT_1);
57871462 5896 }
cf95b4f0 5897 if((dops[i].opcode2&0x0d)==1) // BGEZ/BGEZL/BGEZAL/BGEZALL
57871462 5898 {
5899 emit_test(s1l,s1l);
df4dc2b1 5900 nottaken=out;
7c3a5182 5901 emit_js(DJT_1);
57871462 5902 }
57871462 5903 } // if(!unconditional)
5904 int adj;
5905 uint64_t ds_unneeded=branch_regs[i].u;
cf95b4f0 5906 ds_unneeded&=~((1LL<<dops[i+1].rs1)|(1LL<<dops[i+1].rs2));
57871462 5907 ds_unneeded|=1;
57871462 5908 // branch taken
5909 if(!nevertaken) {
5910 //assem_debug("1:\n");
ad49de89 5911 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,ds_unneeded);
57871462 5912 // load regs
cf95b4f0 5913 load_regs(regs[i].regmap,branch_regs[i].regmap,dops[i+1].rs1,dops[i+1].rs2);
57871462 5914 address_generation(i+1,&branch_regs[i],0);
37387d8b 5915 if (ram_offset)
53358c1d 5916 load_reg(regs[i].regmap,branch_regs[i].regmap,ROREG);
ad49de89 5917 load_regs(regs[i].regmap,branch_regs[i].regmap,CCREG,INVCP);
57871462 5918 ds_assemble(i+1,&branch_regs[i]);
5919 cc=get_reg(branch_regs[i].regmap,CCREG);
5920 if(cc==-1) {
5921 emit_loadreg(CCREG,cc=HOST_CCREG);
5922 // CHECK: Is the following instruction (fall thru) allocated ok?
5923 }
5924 assert(cc==HOST_CCREG);
ad49de89 5925 store_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]);
57871462 5926 do_cc(i,i_regmap,&adj,ba[i],TAKEN,0);
5927 assem_debug("cycle count (adj)\n");
2330734f 5928 if(adj) emit_addimm(cc, ccadj[i] + CLOCK_ADJUST(2) - adj, cc);
ad49de89 5929 load_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]);
57871462 5930 if(internal)
5931 assem_debug("branch: internal\n");
5932 else
5933 assem_debug("branch: external\n");
cf95b4f0 5934 if (internal && dops[(ba[i] - start) >> 2].is_ds) {
57871462 5935 ds_assemble_entry(i);
5936 }
5937 else {
643aeae3 5938 add_to_linker(out,ba[i],internal);
57871462 5939 emit_jmp(0);
5940 }
5941 }
5942 // branch not taken
57871462 5943 if(!unconditional) {
df4dc2b1 5944 set_jump_target(nottaken, out);
57871462 5945 assem_debug("1:\n");
fe807a8a 5946 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,ds_unneeded);
5947 load_regs(regs[i].regmap,branch_regs[i].regmap,dops[i+1].rs1,dops[i+1].rs2);
5948 address_generation(i+1,&branch_regs[i],0);
5a18ce2e 5949 if (ram_offset)
53358c1d 5950 load_reg(regs[i].regmap,branch_regs[i].regmap,ROREG);
5a18ce2e 5951 load_regs(regs[i].regmap,branch_regs[i].regmap,CCREG,INVCP);
fe807a8a 5952 ds_assemble(i+1,&branch_regs[i]);
57871462 5953 cc=get_reg(branch_regs[i].regmap,CCREG);
fe807a8a 5954 if (cc == -1) {
57871462 5955 // Cycle count isn't in a register, temporarily load it then write it out
5956 emit_loadreg(CCREG,HOST_CCREG);
2330734f 5957 emit_addimm_and_set_flags(ccadj[i] + CLOCK_ADJUST(2), HOST_CCREG);
b14b6a8f 5958 void *jaddr=out;
57871462 5959 emit_jns(0);
b14b6a8f 5960 add_stub(CC_STUB,jaddr,out,0,i,start+i*4+8,NOTTAKEN,0);
57871462 5961 emit_storereg(CCREG,HOST_CCREG);
5962 }
5963 else{
5964 cc=get_reg(i_regmap,CCREG);
5965 assert(cc==HOST_CCREG);
2330734f 5966 emit_addimm_and_set_flags(ccadj[i] + CLOCK_ADJUST(2), cc);
b14b6a8f 5967 void *jaddr=out;
57871462 5968 emit_jns(0);
fe807a8a 5969 add_stub(CC_STUB,jaddr,out,0,i,start+i*4+8,NOTTAKEN,0);
57871462 5970 }
5971 }
5972 }
5973}
5974
670c0f22 5975static void check_regmap(signed char *regmap)
5976{
5977#ifndef NDEBUG
5978 int i,j;
5979 for (i = 0; i < HOST_REGS; i++) {
5980 if (regmap[i] < 0)
5981 continue;
5982 for (j = i + 1; j < HOST_REGS; j++)
5983 assert(regmap[i] != regmap[j]);
5984 }
5985#endif
5986}
5987
4600ba03 5988#ifdef DISASM
2acc46cd 5989#include <inttypes.h>
53dc27f6 5990static char insn[MAXBLOCK][10];
5991
5992#define set_mnemonic(i_, n_) \
5993 strcpy(insn[i_], n_)
5994
2acc46cd 5995void print_regmap(const char *name, const signed char *regmap)
5996{
5997 char buf[5];
5998 int i, l;
5999 fputs(name, stdout);
6000 for (i = 0; i < HOST_REGS; i++) {
6001 l = 0;
6002 if (regmap[i] >= 0)
6003 l = snprintf(buf, sizeof(buf), "$%d", regmap[i]);
6004 for (; l < 3; l++)
6005 buf[l] = ' ';
6006 buf[l] = 0;
6007 printf(" r%d=%s", i, buf);
6008 }
6009 fputs("\n", stdout);
6010}
6011
57871462 6012 /* disassembly */
6013void disassemble_inst(int i)
6014{
cf95b4f0 6015 if (dops[i].bt) printf("*"); else printf(" ");
6016 switch(dops[i].itype) {
57871462 6017 case UJUMP:
6018 printf (" %x: %s %8x\n",start+i*4,insn[i],ba[i]);break;
6019 case CJUMP:
cf95b4f0 6020 printf (" %x: %s r%d,r%d,%8x\n",start+i*4,insn[i],dops[i].rs1,dops[i].rs2,i?start+i*4+4+((signed int)((unsigned int)source[i]<<16)>>14):*ba);break;
57871462 6021 case SJUMP:
cf95b4f0 6022 printf (" %x: %s r%d,%8x\n",start+i*4,insn[i],dops[i].rs1,start+i*4+4+((signed int)((unsigned int)source[i]<<16)>>14));break;
57871462 6023 case RJUMP:
cf95b4f0 6024 if (dops[i].opcode==0x9&&dops[i].rt1!=31)
6025 printf (" %x: %s r%d,r%d\n",start+i*4,insn[i],dops[i].rt1,dops[i].rs1);
5067f341 6026 else
cf95b4f0 6027 printf (" %x: %s r%d\n",start+i*4,insn[i],dops[i].rs1);
5067f341 6028 break;
57871462 6029 case IMM16:
cf95b4f0 6030 if(dops[i].opcode==0xf) //LUI
6031 printf (" %x: %s r%d,%4x0000\n",start+i*4,insn[i],dops[i].rt1,imm[i]&0xffff);
57871462 6032 else
cf95b4f0 6033 printf (" %x: %s r%d,r%d,%d\n",start+i*4,insn[i],dops[i].rt1,dops[i].rs1,imm[i]);
57871462 6034 break;
6035 case LOAD:
6036 case LOADLR:
cf95b4f0 6037 printf (" %x: %s r%d,r%d+%x\n",start+i*4,insn[i],dops[i].rt1,dops[i].rs1,imm[i]);
57871462 6038 break;
6039 case STORE:
6040 case STORELR:
cf95b4f0 6041 printf (" %x: %s r%d,r%d+%x\n",start+i*4,insn[i],dops[i].rs2,dops[i].rs1,imm[i]);
57871462 6042 break;
6043 case ALU:
6044 case SHIFT:
cf95b4f0 6045 printf (" %x: %s r%d,r%d,r%d\n",start+i*4,insn[i],dops[i].rt1,dops[i].rs1,dops[i].rs2);
57871462 6046 break;
6047 case MULTDIV:
cf95b4f0 6048 printf (" %x: %s r%d,r%d\n",start+i*4,insn[i],dops[i].rs1,dops[i].rs2);
57871462 6049 break;
6050 case SHIFTIMM:
cf95b4f0 6051 printf (" %x: %s r%d,r%d,%d\n",start+i*4,insn[i],dops[i].rt1,dops[i].rs1,imm[i]);
57871462 6052 break;
6053 case MOV:
cf95b4f0 6054 if((dops[i].opcode2&0x1d)==0x10)
6055 printf (" %x: %s r%d\n",start+i*4,insn[i],dops[i].rt1);
6056 else if((dops[i].opcode2&0x1d)==0x11)
6057 printf (" %x: %s r%d\n",start+i*4,insn[i],dops[i].rs1);
57871462 6058 else
6059 printf (" %x: %s\n",start+i*4,insn[i]);
6060 break;
6061 case COP0:
cf95b4f0 6062 if(dops[i].opcode2==0)
6063 printf (" %x: %s r%d,cpr0[%d]\n",start+i*4,insn[i],dops[i].rt1,(source[i]>>11)&0x1f); // MFC0
6064 else if(dops[i].opcode2==4)
6065 printf (" %x: %s r%d,cpr0[%d]\n",start+i*4,insn[i],dops[i].rs1,(source[i]>>11)&0x1f); // MTC0
57871462 6066 else printf (" %x: %s\n",start+i*4,insn[i]);
6067 break;
6068 case COP1:
cf95b4f0 6069 if(dops[i].opcode2<3)
6070 printf (" %x: %s r%d,cpr1[%d]\n",start+i*4,insn[i],dops[i].rt1,(source[i]>>11)&0x1f); // MFC1
6071 else if(dops[i].opcode2>3)
6072 printf (" %x: %s r%d,cpr1[%d]\n",start+i*4,insn[i],dops[i].rs1,(source[i]>>11)&0x1f); // MTC1
57871462 6073 else printf (" %x: %s\n",start+i*4,insn[i]);
6074 break;
b9b61529 6075 case COP2:
cf95b4f0 6076 if(dops[i].opcode2<3)
6077 printf (" %x: %s r%d,cpr2[%d]\n",start+i*4,insn[i],dops[i].rt1,(source[i]>>11)&0x1f); // MFC2
6078 else if(dops[i].opcode2>3)
6079 printf (" %x: %s r%d,cpr2[%d]\n",start+i*4,insn[i],dops[i].rs1,(source[i]>>11)&0x1f); // MTC2
b9b61529 6080 else printf (" %x: %s\n",start+i*4,insn[i]);
6081 break;
57871462 6082 case C1LS:
cf95b4f0 6083 printf (" %x: %s cpr1[%d],r%d+%x\n",start+i*4,insn[i],(source[i]>>16)&0x1f,dops[i].rs1,imm[i]);
57871462 6084 break;
b9b61529 6085 case C2LS:
cf95b4f0 6086 printf (" %x: %s cpr2[%d],r%d+%x\n",start+i*4,insn[i],(source[i]>>16)&0x1f,dops[i].rs1,imm[i]);
b9b61529 6087 break;
1e973cb0 6088 case INTCALL:
6089 printf (" %x: %s (INTCALL)\n",start+i*4,insn[i]);
6090 break;
57871462 6091 default:
6092 //printf (" %s %8x\n",insn[i],source[i]);
6093 printf (" %x: %s\n",start+i*4,insn[i]);
6094 }
2acc46cd 6095 return;
6096 printf("D: %"PRIu64" WD: %"PRIu64" U: %"PRIu64"\n",
6097 regs[i].dirty, regs[i].wasdirty, unneeded_reg[i]);
6098 print_regmap("pre: ", regmap_pre[i]);
6099 print_regmap("entry: ", regs[i].regmap_entry);
6100 print_regmap("map: ", regs[i].regmap);
6101 if (dops[i].is_jump) {
6102 print_regmap("bentry:", branch_regs[i].regmap_entry);
6103 print_regmap("bmap: ", branch_regs[i].regmap);
6104 }
57871462 6105}
4600ba03 6106#else
53dc27f6 6107#define set_mnemonic(i_, n_)
4600ba03 6108static void disassemble_inst(int i) {}
6109#endif // DISASM
57871462 6110
d848b60a 6111#define DRC_TEST_VAL 0x74657374
6112
d9e2b173 6113static noinline void new_dynarec_test(void)
d848b60a 6114{
be516ebe 6115 int (*testfunc)(void);
d148d265 6116 void *beginning;
be516ebe 6117 int ret[2];
6118 size_t i;
d148d265 6119
687b4580 6120 // check structure linkage
7c3a5182 6121 if ((u_char *)rcnts - (u_char *)&psxRegs != sizeof(psxRegs))
687b4580 6122 {
7c3a5182 6123 SysPrintf("linkage_arm* miscompilation/breakage detected.\n");
687b4580 6124 }
6125
d9e2b173 6126 SysPrintf("(%p) testing if we can run recompiled code @%p...\n",
6127 new_dynarec_test, out);
6128 ((volatile u_int *)NDRC_WRITE_OFFSET(out))[0]++; // make the cache dirty
be516ebe 6129
6130 for (i = 0; i < ARRAY_SIZE(ret); i++) {
2a014d73 6131 out = ndrc->translation_cache;
be516ebe 6132 beginning = start_block();
6133 emit_movimm(DRC_TEST_VAL + i, 0); // test
6134 emit_ret();
6135 literal_pool(0);
6136 end_block(beginning);
6137 testfunc = beginning;
6138 ret[i] = testfunc();
6139 }
6140
6141 if (ret[0] == DRC_TEST_VAL && ret[1] == DRC_TEST_VAL + 1)
d848b60a 6142 SysPrintf("test passed.\n");
6143 else
be516ebe 6144 SysPrintf("test failed, will likely crash soon (r=%08x %08x)\n", ret[0], ret[1]);
2a014d73 6145 out = ndrc->translation_cache;
d848b60a 6146}
6147
dc990066 6148// clear the state completely, instead of just marking
6149// things invalid like invalidate_all_pages() does
919981d0 6150void new_dynarec_clear_full(void)
57871462 6151{
57871462 6152 int n;
2a014d73 6153 out = ndrc->translation_cache;
35775df7 6154 memset(invalid_code,1,sizeof(invalid_code));
6155 memset(hash_table,0xff,sizeof(hash_table));
57871462 6156 memset(mini_ht,-1,sizeof(mini_ht));
dc990066 6157 memset(shadow,0,sizeof(shadow));
57871462 6158 copy=shadow;
93c0345b 6159 expirep = EXPIRITY_OFFSET;
57871462 6160 pending_exception=0;
6161 literalcount=0;
57871462 6162 stop_after_jal=0;
9be4ba64 6163 inv_code_start=inv_code_end=~0;
7f94b097 6164 hack_addr=0;
39b71d9a 6165 f1_hack=0;
93c0345b 6166 for (n = 0; n < ARRAY_SIZE(blocks); n++)
6167 blocks_clear(&blocks[n]);
b7ad2f2c 6168 for (n = 0; n < ARRAY_SIZE(jumps); n++) {
6169 free(jumps[n]);
6170 jumps[n] = NULL;
6171 }
104df9d3 6172 stat_clear(stat_blocks);
6173 stat_clear(stat_links);
32631e6a 6174
6175 cycle_multiplier_old = cycle_multiplier;
6176 new_dynarec_hacks_old = new_dynarec_hacks;
dc990066 6177}
6178
919981d0 6179void new_dynarec_init(void)
dc990066 6180{
66ea165f 6181 SysPrintf("Init new dynarec, ndrc size %x\n", (int)sizeof(*ndrc));
1e212a25 6182
0aeb0cb9 6183#ifdef _3DS
6184 check_rosalina();
6185#endif
2a014d73 6186#ifdef BASE_ADDR_DYNAMIC
1e212a25 6187 #ifdef VITA
0aeb0cb9 6188 sceBlock = getVMBlock(); //sceKernelAllocMemBlockForVM("code", sizeof(*ndrc));
66ea165f 6189 if (sceBlock <= 0)
6190 SysPrintf("sceKernelAllocMemBlockForVM failed: %x\n", sceBlock);
2a014d73 6191 int ret = sceKernelGetMemBlockBase(sceBlock, (void **)&ndrc);
1e212a25 6192 if (ret < 0)
66ea165f 6193 SysPrintf("sceKernelGetMemBlockBase failed: %x\n", ret);
0aeb0cb9 6194 sceKernelOpenVMDomain();
6195 sceClibPrintf("translation_cache = 0x%08lx\n ", (long)ndrc->translation_cache);
6196 #elif defined(_MSC_VER)
6197 ndrc = VirtualAlloc(NULL, sizeof(*ndrc), MEM_COMMIT | MEM_RESERVE,
6198 PAGE_EXECUTE_READWRITE);
3039c914 6199 #elif defined(HAVE_LIBNX)
6200 Result rc = jitCreate(&g_jit, sizeof(*ndrc));
6201 if (R_FAILED(rc))
6202 SysPrintf("jitCreate failed: %08x\n", rc);
6203 SysPrintf("jitCreate: RX: %p RW: %p type: %d\n", g_jit.rx_addr, g_jit.rw_addr, g_jit.type);
d9e2b173 6204 jitTransitionToWritable(&g_jit);
3039c914 6205 ndrc = g_jit.rx_addr;
6206 ndrc_write_ofs = (char *)g_jit.rw_addr - (char *)ndrc;
d9e2b173 6207 memset(NDRC_WRITE_OFFSET(&ndrc->tramp), 0, sizeof(ndrc->tramp));
1e212a25 6208 #else
2a014d73 6209 uintptr_t desired_addr = 0;
3039c914 6210 int prot = PROT_READ | PROT_WRITE | PROT_EXEC;
6211 int flags = MAP_PRIVATE | MAP_ANONYMOUS;
6212 int fd = -1;
2a014d73 6213 #ifdef __ELF__
6214 extern char _end;
6215 desired_addr = ((uintptr_t)&_end + 0xffffff) & ~0xffffffl;
6216 #endif
d9e2b173 6217 #ifdef TC_WRITE_OFFSET
3039c914 6218 // mostly for testing
6219 fd = open("/dev/shm/pcsxr", O_CREAT | O_RDWR, 0600);
6220 ftruncate(fd, sizeof(*ndrc));
6221 void *mw = mmap(NULL, sizeof(*ndrc), PROT_READ | PROT_WRITE,
6222 (flags = MAP_SHARED), fd, 0);
6223 assert(mw != MAP_FAILED);
6224 prot = PROT_READ | PROT_EXEC;
6225 #endif
6226 ndrc = mmap((void *)desired_addr, sizeof(*ndrc), prot, flags, fd, 0);
2a014d73 6227 if (ndrc == MAP_FAILED) {
d848b60a 6228 SysPrintf("mmap() failed: %s\n", strerror(errno));
1e212a25 6229 abort();
d848b60a 6230 }
d9e2b173 6231 #ifdef TC_WRITE_OFFSET
3039c914 6232 ndrc_write_ofs = (char *)mw - (char *)ndrc;
6233 #endif
1e212a25 6234 #endif
6235#else
6236 #ifndef NO_WRITE_EXEC
bdeade46 6237 // not all systems allow execute in data segment by default
761fdd0a 6238 // size must be 4K aligned for 3DS?
6239 if (mprotect(ndrc, sizeof(*ndrc),
2a014d73 6240 PROT_READ | PROT_WRITE | PROT_EXEC) != 0)
d848b60a 6241 SysPrintf("mprotect() failed: %s\n", strerror(errno));
1e212a25 6242 #endif
dc990066 6243#endif
2a014d73 6244 out = ndrc->translation_cache;
2573466a 6245 cycle_multiplier=200;
dc990066 6246 new_dynarec_clear_full();
6247#ifdef HOST_IMM8
6248 // Copy this into local area so we don't have to put it in every literal pool
6249 invc_ptr=invalid_code;
6250#endif
57871462 6251 arch_init();
d848b60a 6252 new_dynarec_test();
01d26796 6253 ram_offset=(uintptr_t)rdram-0x80000000;
b105cf4f 6254 if (ram_offset!=0)
c43b5311 6255 SysPrintf("warning: RAM is not directly mapped, performance will suffer\n");
398d6924 6256 SysPrintf("Mapped (RAM/scrp/ROM/LUTs/TC):\n");
6257 SysPrintf("%p/%p/%p/%p/%p\n", psxM, psxH, psxR, mem_rtab, out);
57871462 6258}
6259
919981d0 6260void new_dynarec_cleanup(void)
57871462 6261{
6262 int n;
2a014d73 6263#ifdef BASE_ADDR_DYNAMIC
1e212a25 6264 #ifdef VITA
66ea165f 6265 // sceBlock is managed by retroarch's bootstrap code
9c67c98f 6266 //sceKernelFreeMemBlock(sceBlock);
6267 //sceBlock = -1;
3039c914 6268 #elif defined(HAVE_LIBNX)
6269 jitClose(&g_jit);
6270 ndrc = NULL;
1e212a25 6271 #else
2a014d73 6272 if (munmap(ndrc, sizeof(*ndrc)) < 0)
1e212a25 6273 SysPrintf("munmap() failed\n");
3039c914 6274 ndrc = NULL;
bdeade46 6275 #endif
1e212a25 6276#endif
93c0345b 6277 for (n = 0; n < ARRAY_SIZE(blocks); n++)
6278 blocks_clear(&blocks[n]);
b7ad2f2c 6279 for (n = 0; n < ARRAY_SIZE(jumps); n++) {
6280 free(jumps[n]);
6281 jumps[n] = NULL;
6282 }
104df9d3 6283 stat_clear(stat_blocks);
6284 stat_clear(stat_links);
ece032e6 6285 new_dynarec_print_stats();
57871462 6286}
6287
03f55e6b 6288static u_int *get_source_start(u_int addr, u_int *limit)
57871462 6289{
03f55e6b 6290 if (addr < 0x00200000 ||
a3203cf4 6291 (0xa0000000 <= addr && addr < 0xa0200000))
6292 {
03f55e6b 6293 // used for BIOS calls mostly?
6294 *limit = (addr&0xa0000000)|0x00200000;
01d26796 6295 return (u_int *)(rdram + (addr&0x1fffff));
03f55e6b 6296 }
6297 else if (!Config.HLE && (
6298 /* (0x9fc00000 <= addr && addr < 0x9fc80000) ||*/
a3203cf4 6299 (0xbfc00000 <= addr && addr < 0xbfc80000)))
6300 {
6301 // BIOS. The multiplier should be much higher as it's uncached 8bit mem,
6302 // but timings in PCSX are too tied to the interpreter's BIAS
d62c125a 6303 if (!HACK_ENABLED(NDHACK_OVERRIDE_CYCLE_M))
24058131 6304 cycle_multiplier_active = 200;
a3203cf4 6305
03f55e6b 6306 *limit = (addr & 0xfff00000) | 0x80000;
01d26796 6307 return (u_int *)((u_char *)psxR + (addr&0x7ffff));
03f55e6b 6308 }
6309 else if (addr >= 0x80000000 && addr < 0x80000000+RAM_SIZE) {
6310 *limit = (addr & 0x80600000) + 0x00200000;
01d26796 6311 return (u_int *)(rdram + (addr&0x1fffff));
03f55e6b 6312 }
581335b0 6313 return NULL;
03f55e6b 6314}
6315
6316static u_int scan_for_ret(u_int addr)
6317{
6318 u_int limit = 0;
6319 u_int *mem;
6320
6321 mem = get_source_start(addr, &limit);
6322 if (mem == NULL)
6323 return addr;
6324
6325 if (limit > addr + 0x1000)
6326 limit = addr + 0x1000;
6327 for (; addr < limit; addr += 4, mem++) {
6328 if (*mem == 0x03e00008) // jr $ra
6329 return addr + 8;
57871462 6330 }
581335b0 6331 return addr;
03f55e6b 6332}
6333
6334struct savestate_block {
6335 uint32_t addr;
6336 uint32_t regflags;
6337};
6338
6339static int addr_cmp(const void *p1_, const void *p2_)
6340{
6341 const struct savestate_block *p1 = p1_, *p2 = p2_;
6342 return p1->addr - p2->addr;
6343}
6344
6345int new_dynarec_save_blocks(void *save, int size)
6346{
104df9d3 6347 struct savestate_block *sblocks = save;
6348 int maxcount = size / sizeof(sblocks[0]);
03f55e6b 6349 struct savestate_block tmp_blocks[1024];
104df9d3 6350 struct block_info *block;
03f55e6b 6351 int p, s, d, o, bcnt;
6352 u_int addr;
6353
6354 o = 0;
104df9d3 6355 for (p = 0; p < ARRAY_SIZE(blocks); p++) {
03f55e6b 6356 bcnt = 0;
104df9d3 6357 for (block = blocks[p]; block != NULL; block = block->next) {
6358 if (block->is_dirty)
6359 continue;
6360 tmp_blocks[bcnt].addr = block->start;
6361 tmp_blocks[bcnt].regflags = block->reg_sv_flags;
03f55e6b 6362 bcnt++;
6363 }
6364 if (bcnt < 1)
6365 continue;
6366 qsort(tmp_blocks, bcnt, sizeof(tmp_blocks[0]), addr_cmp);
6367
6368 addr = tmp_blocks[0].addr;
6369 for (s = d = 0; s < bcnt; s++) {
6370 if (tmp_blocks[s].addr < addr)
6371 continue;
6372 if (d == 0 || tmp_blocks[d-1].addr != tmp_blocks[s].addr)
6373 tmp_blocks[d++] = tmp_blocks[s];
6374 addr = scan_for_ret(tmp_blocks[s].addr);
6375 }
6376
6377 if (o + d > maxcount)
6378 d = maxcount - o;
104df9d3 6379 memcpy(&sblocks[o], tmp_blocks, d * sizeof(sblocks[0]));
03f55e6b 6380 o += d;
6381 }
6382
104df9d3 6383 return o * sizeof(sblocks[0]);
03f55e6b 6384}
6385
6386void new_dynarec_load_blocks(const void *save, int size)
6387{
104df9d3 6388 const struct savestate_block *sblocks = save;
6389 int count = size / sizeof(sblocks[0]);
6390 struct block_info *block;
03f55e6b 6391 u_int regs_save[32];
104df9d3 6392 u_int page;
03f55e6b 6393 uint32_t f;
6394 int i, b;
6395
104df9d3 6396 // restore clean blocks, if any
6397 for (page = 0, b = i = 0; page < ARRAY_SIZE(blocks); page++) {
6398 for (block = blocks[page]; block != NULL; block = block->next, b++) {
6399 if (!block->is_dirty)
6400 continue;
6401 assert(block->source && block->copy);
6402 if (memcmp(block->source, block->copy, block->len))
6403 continue;
6404
6405 // see try_restore_block
6406 block->is_dirty = 0;
6407 mark_invalid_code(block->start, block->len, 0);
6408 i++;
6409 }
6410 }
6411 inv_debug("load_blocks: %d/%d clean blocks\n", i, b);
03f55e6b 6412
6413 // change GPRs for speculation to at least partially work..
6414 memcpy(regs_save, &psxRegs.GPR, sizeof(regs_save));
6415 for (i = 1; i < 32; i++)
6416 psxRegs.GPR.r[i] = 0x80000000;
6417
6418 for (b = 0; b < count; b++) {
104df9d3 6419 for (f = sblocks[b].regflags, i = 0; f; f >>= 1, i++) {
03f55e6b 6420 if (f & 1)
6421 psxRegs.GPR.r[i] = 0x1f800000;
6422 }
6423
104df9d3 6424 ndrc_get_addr_ht(sblocks[b].addr);
03f55e6b 6425
104df9d3 6426 for (f = sblocks[b].regflags, i = 0; f; f >>= 1, i++) {
03f55e6b 6427 if (f & 1)
6428 psxRegs.GPR.r[i] = 0x80000000;
6429 }
6430 }
6431
6432 memcpy(&psxRegs.GPR, regs_save, sizeof(regs_save));
6433}
6434
ece032e6 6435void new_dynarec_print_stats(void)
6436{
6437#ifdef STAT_PRINT
104df9d3 6438 printf("cc %3d,%3d,%3d lu%6d,%3d,%3d c%3d inv%3d,%3d tc_offs %zu b %u,%u\n",
ece032e6 6439 stat_bc_pre, stat_bc_direct, stat_bc_restore,
104df9d3 6440 stat_ht_lookups, stat_jump_in_lookups, stat_restore_tries,
6441 stat_restore_compares, stat_inv_addr_calls, stat_inv_hits,
6442 out - ndrc->translation_cache, stat_blocks, stat_links);
ece032e6 6443 stat_bc_direct = stat_bc_pre = stat_bc_restore =
104df9d3 6444 stat_ht_lookups = stat_jump_in_lookups = stat_restore_tries =
6445 stat_restore_compares = stat_inv_addr_calls = stat_inv_hits = 0;
ece032e6 6446#endif
6447}
6448
7f94b097 6449static int apply_hacks(void)
24058131 6450{
6451 int i;
6452 if (HACK_ENABLED(NDHACK_NO_COMPAT_HACKS))
7f94b097 6453 return 0;
24058131 6454 /* special hack(s) */
6455 for (i = 0; i < slen - 4; i++)
6456 {
6457 // lui a4, 0xf200; jal <rcnt_read>; addu a0, 2; slti v0, 28224
6458 if (source[i] == 0x3c04f200 && dops[i+1].itype == UJUMP
6459 && source[i+2] == 0x34840002 && dops[i+3].opcode == 0x0a
6460 && imm[i+3] == 0x6e40 && dops[i+3].rs1 == 2)
6461 {
6462 SysPrintf("PE2 hack @%08x\n", start + (i+3)*4);
6463 dops[i + 3].itype = NOP;
6464 }
6465 }
6466 i = slen;
6467 if (i > 10 && source[i-1] == 0 && source[i-2] == 0x03e00008
6468 && source[i-4] == 0x8fbf0018 && source[i-6] == 0x00c0f809
6469 && dops[i-7].itype == STORE)
6470 {
6471 i = i-8;
6472 if (dops[i].itype == IMM16)
6473 i--;
6474 // swl r2, 15(r6); swr r2, 12(r6); sw r6, *; jalr r6
6475 if (dops[i].itype == STORELR && dops[i].rs1 == 6
6476 && dops[i-1].itype == STORELR && dops[i-1].rs1 == 6)
6477 {
7f94b097 6478 SysPrintf("F1 hack from %08x, old dst %08x\n", start, hack_addr);
6479 f1_hack = 1;
6480 return 1;
24058131 6481 }
6482 }
7f94b097 6483 return 0;
24058131 6484}
6485
4149788d 6486static noinline void pass1_disassemble(u_int pagelimit)
03f55e6b 6487{
4149788d 6488 int i, j, done = 0, ni_count = 0;
57871462 6489 unsigned int type,op,op2;
6490
7ebfcedf 6491 for (i = 0; !done; i++)
6492 {
6493 memset(&dops[i], 0, sizeof(dops[i]));
cf95b4f0 6494 op2=0;
e1190b87 6495 minimum_free_regs[i]=0;
cf95b4f0 6496 dops[i].opcode=op=source[i]>>26;
57871462 6497 switch(op)
6498 {
53dc27f6 6499 case 0x00: set_mnemonic(i, "special"); type=NI;
57871462 6500 op2=source[i]&0x3f;
6501 switch(op2)
6502 {
53dc27f6 6503 case 0x00: set_mnemonic(i, "SLL"); type=SHIFTIMM; break;
6504 case 0x02: set_mnemonic(i, "SRL"); type=SHIFTIMM; break;
6505 case 0x03: set_mnemonic(i, "SRA"); type=SHIFTIMM; break;
6506 case 0x04: set_mnemonic(i, "SLLV"); type=SHIFT; break;
6507 case 0x06: set_mnemonic(i, "SRLV"); type=SHIFT; break;
6508 case 0x07: set_mnemonic(i, "SRAV"); type=SHIFT; break;
6509 case 0x08: set_mnemonic(i, "JR"); type=RJUMP; break;
6510 case 0x09: set_mnemonic(i, "JALR"); type=RJUMP; break;
6511 case 0x0C: set_mnemonic(i, "SYSCALL"); type=SYSCALL; break;
6512 case 0x0D: set_mnemonic(i, "BREAK"); type=SYSCALL; break;
6513 case 0x0F: set_mnemonic(i, "SYNC"); type=OTHER; break;
6514 case 0x10: set_mnemonic(i, "MFHI"); type=MOV; break;
6515 case 0x11: set_mnemonic(i, "MTHI"); type=MOV; break;
6516 case 0x12: set_mnemonic(i, "MFLO"); type=MOV; break;
6517 case 0x13: set_mnemonic(i, "MTLO"); type=MOV; break;
6518 case 0x18: set_mnemonic(i, "MULT"); type=MULTDIV; break;
6519 case 0x19: set_mnemonic(i, "MULTU"); type=MULTDIV; break;
6520 case 0x1A: set_mnemonic(i, "DIV"); type=MULTDIV; break;
6521 case 0x1B: set_mnemonic(i, "DIVU"); type=MULTDIV; break;
6522 case 0x20: set_mnemonic(i, "ADD"); type=ALU; break;
6523 case 0x21: set_mnemonic(i, "ADDU"); type=ALU; break;
6524 case 0x22: set_mnemonic(i, "SUB"); type=ALU; break;
6525 case 0x23: set_mnemonic(i, "SUBU"); type=ALU; break;
6526 case 0x24: set_mnemonic(i, "AND"); type=ALU; break;
6527 case 0x25: set_mnemonic(i, "OR"); type=ALU; break;
6528 case 0x26: set_mnemonic(i, "XOR"); type=ALU; break;
6529 case 0x27: set_mnemonic(i, "NOR"); type=ALU; break;
6530 case 0x2A: set_mnemonic(i, "SLT"); type=ALU; break;
6531 case 0x2B: set_mnemonic(i, "SLTU"); type=ALU; break;
6532 case 0x30: set_mnemonic(i, "TGE"); type=NI; break;
6533 case 0x31: set_mnemonic(i, "TGEU"); type=NI; break;
6534 case 0x32: set_mnemonic(i, "TLT"); type=NI; break;
6535 case 0x33: set_mnemonic(i, "TLTU"); type=NI; break;
6536 case 0x34: set_mnemonic(i, "TEQ"); type=NI; break;
6537 case 0x36: set_mnemonic(i, "TNE"); type=NI; break;
71e490c5 6538#if 0
53dc27f6 6539 case 0x14: set_mnemonic(i, "DSLLV"); type=SHIFT; break;
6540 case 0x16: set_mnemonic(i, "DSRLV"); type=SHIFT; break;
6541 case 0x17: set_mnemonic(i, "DSRAV"); type=SHIFT; break;
6542 case 0x1C: set_mnemonic(i, "DMULT"); type=MULTDIV; break;
6543 case 0x1D: set_mnemonic(i, "DMULTU"); type=MULTDIV; break;
6544 case 0x1E: set_mnemonic(i, "DDIV"); type=MULTDIV; break;
6545 case 0x1F: set_mnemonic(i, "DDIVU"); type=MULTDIV; break;
6546 case 0x2C: set_mnemonic(i, "DADD"); type=ALU; break;
6547 case 0x2D: set_mnemonic(i, "DADDU"); type=ALU; break;
6548 case 0x2E: set_mnemonic(i, "DSUB"); type=ALU; break;
6549 case 0x2F: set_mnemonic(i, "DSUBU"); type=ALU; break;
6550 case 0x38: set_mnemonic(i, "DSLL"); type=SHIFTIMM; break;
6551 case 0x3A: set_mnemonic(i, "DSRL"); type=SHIFTIMM; break;
6552 case 0x3B: set_mnemonic(i, "DSRA"); type=SHIFTIMM; break;
6553 case 0x3C: set_mnemonic(i, "DSLL32"); type=SHIFTIMM; break;
6554 case 0x3E: set_mnemonic(i, "DSRL32"); type=SHIFTIMM; break;
6555 case 0x3F: set_mnemonic(i, "DSRA32"); type=SHIFTIMM; break;
7f2607ea 6556#endif
57871462 6557 }
6558 break;
53dc27f6 6559 case 0x01: set_mnemonic(i, "regimm"); type=NI;
57871462 6560 op2=(source[i]>>16)&0x1f;
6561 switch(op2)
6562 {
53dc27f6 6563 case 0x00: set_mnemonic(i, "BLTZ"); type=SJUMP; break;
6564 case 0x01: set_mnemonic(i, "BGEZ"); type=SJUMP; break;
6565 //case 0x02: set_mnemonic(i, "BLTZL"); type=SJUMP; break;
6566 //case 0x03: set_mnemonic(i, "BGEZL"); type=SJUMP; break;
6567 //case 0x08: set_mnemonic(i, "TGEI"); type=NI; break;
6568 //case 0x09: set_mnemonic(i, "TGEIU"); type=NI; break;
6569 //case 0x0A: set_mnemonic(i, "TLTI"); type=NI; break;
6570 //case 0x0B: set_mnemonic(i, "TLTIU"); type=NI; break;
6571 //case 0x0C: set_mnemonic(i, "TEQI"); type=NI; break;
6572 //case 0x0E: set_mnemonic(i, "TNEI"); type=NI; break;
6573 case 0x10: set_mnemonic(i, "BLTZAL"); type=SJUMP; break;
6574 case 0x11: set_mnemonic(i, "BGEZAL"); type=SJUMP; break;
6575 //case 0x12: set_mnemonic(i, "BLTZALL"); type=SJUMP; break;
6576 //case 0x13: set_mnemonic(i, "BGEZALL"); type=SJUMP; break;
57871462 6577 }
6578 break;
53dc27f6 6579 case 0x02: set_mnemonic(i, "J"); type=UJUMP; break;
6580 case 0x03: set_mnemonic(i, "JAL"); type=UJUMP; break;
6581 case 0x04: set_mnemonic(i, "BEQ"); type=CJUMP; break;
6582 case 0x05: set_mnemonic(i, "BNE"); type=CJUMP; break;
6583 case 0x06: set_mnemonic(i, "BLEZ"); type=CJUMP; break;
6584 case 0x07: set_mnemonic(i, "BGTZ"); type=CJUMP; break;
6585 case 0x08: set_mnemonic(i, "ADDI"); type=IMM16; break;
6586 case 0x09: set_mnemonic(i, "ADDIU"); type=IMM16; break;
6587 case 0x0A: set_mnemonic(i, "SLTI"); type=IMM16; break;
6588 case 0x0B: set_mnemonic(i, "SLTIU"); type=IMM16; break;
6589 case 0x0C: set_mnemonic(i, "ANDI"); type=IMM16; break;
6590 case 0x0D: set_mnemonic(i, "ORI"); type=IMM16; break;
6591 case 0x0E: set_mnemonic(i, "XORI"); type=IMM16; break;
6592 case 0x0F: set_mnemonic(i, "LUI"); type=IMM16; break;
6593 case 0x10: set_mnemonic(i, "cop0"); type=NI;
57871462 6594 op2=(source[i]>>21)&0x1f;
6595 switch(op2)
6596 {
53dc27f6 6597 case 0x00: set_mnemonic(i, "MFC0"); type=COP0; break;
6598 case 0x02: set_mnemonic(i, "CFC0"); type=COP0; break;
6599 case 0x04: set_mnemonic(i, "MTC0"); type=COP0; break;
6600 case 0x06: set_mnemonic(i, "CTC0"); type=COP0; break;
6601 case 0x10: set_mnemonic(i, "RFE"); type=COP0; break;
57871462 6602 }
6603 break;
53dc27f6 6604 case 0x11: set_mnemonic(i, "cop1"); type=COP1;
57871462 6605 op2=(source[i]>>21)&0x1f;
57871462 6606 break;
71e490c5 6607#if 0
53dc27f6 6608 case 0x14: set_mnemonic(i, "BEQL"); type=CJUMP; break;
6609 case 0x15: set_mnemonic(i, "BNEL"); type=CJUMP; break;
6610 case 0x16: set_mnemonic(i, "BLEZL"); type=CJUMP; break;
6611 case 0x17: set_mnemonic(i, "BGTZL"); type=CJUMP; break;
6612 case 0x18: set_mnemonic(i, "DADDI"); type=IMM16; break;
6613 case 0x19: set_mnemonic(i, "DADDIU"); type=IMM16; break;
6614 case 0x1A: set_mnemonic(i, "LDL"); type=LOADLR; break;
6615 case 0x1B: set_mnemonic(i, "LDR"); type=LOADLR; break;
996cc15d 6616#endif
53dc27f6 6617 case 0x20: set_mnemonic(i, "LB"); type=LOAD; break;
6618 case 0x21: set_mnemonic(i, "LH"); type=LOAD; break;
6619 case 0x22: set_mnemonic(i, "LWL"); type=LOADLR; break;
6620 case 0x23: set_mnemonic(i, "LW"); type=LOAD; break;
6621 case 0x24: set_mnemonic(i, "LBU"); type=LOAD; break;
6622 case 0x25: set_mnemonic(i, "LHU"); type=LOAD; break;
6623 case 0x26: set_mnemonic(i, "LWR"); type=LOADLR; break;
71e490c5 6624#if 0
53dc27f6 6625 case 0x27: set_mnemonic(i, "LWU"); type=LOAD; break;
64bd6f82 6626#endif
53dc27f6 6627 case 0x28: set_mnemonic(i, "SB"); type=STORE; break;
6628 case 0x29: set_mnemonic(i, "SH"); type=STORE; break;
6629 case 0x2A: set_mnemonic(i, "SWL"); type=STORELR; break;
6630 case 0x2B: set_mnemonic(i, "SW"); type=STORE; break;
71e490c5 6631#if 0
53dc27f6 6632 case 0x2C: set_mnemonic(i, "SDL"); type=STORELR; break;
6633 case 0x2D: set_mnemonic(i, "SDR"); type=STORELR; break;
996cc15d 6634#endif
53dc27f6 6635 case 0x2E: set_mnemonic(i, "SWR"); type=STORELR; break;
6636 case 0x2F: set_mnemonic(i, "CACHE"); type=NOP; break;
6637 case 0x30: set_mnemonic(i, "LL"); type=NI; break;
6638 case 0x31: set_mnemonic(i, "LWC1"); type=C1LS; break;
71e490c5 6639#if 0
53dc27f6 6640 case 0x34: set_mnemonic(i, "LLD"); type=NI; break;
6641 case 0x35: set_mnemonic(i, "LDC1"); type=C1LS; break;
6642 case 0x37: set_mnemonic(i, "LD"); type=LOAD; break;
996cc15d 6643#endif
53dc27f6 6644 case 0x38: set_mnemonic(i, "SC"); type=NI; break;
6645 case 0x39: set_mnemonic(i, "SWC1"); type=C1LS; break;
71e490c5 6646#if 0
53dc27f6 6647 case 0x3C: set_mnemonic(i, "SCD"); type=NI; break;
6648 case 0x3D: set_mnemonic(i, "SDC1"); type=C1LS; break;
6649 case 0x3F: set_mnemonic(i, "SD"); type=STORE; break;
996cc15d 6650#endif
53dc27f6 6651 case 0x12: set_mnemonic(i, "COP2"); type=NI;
b9b61529 6652 op2=(source[i]>>21)&0x1f;
be516ebe 6653 //if (op2 & 0x10)
bedfea38 6654 if (source[i]&0x3f) { // use this hack to support old savestates with patched gte insns
c7abc864 6655 if (gte_handlers[source[i]&0x3f]!=NULL) {
53dc27f6 6656#ifdef DISASM
bedfea38 6657 if (gte_regnames[source[i]&0x3f]!=NULL)
6658 strcpy(insn[i],gte_regnames[source[i]&0x3f]);
6659 else
6660 snprintf(insn[i], sizeof(insn[i]), "COP2 %x", source[i]&0x3f);
53dc27f6 6661#endif
c7abc864 6662 type=C2OP;
6663 }
6664 }
6665 else switch(op2)
b9b61529 6666 {
53dc27f6 6667 case 0x00: set_mnemonic(i, "MFC2"); type=COP2; break;
6668 case 0x02: set_mnemonic(i, "CFC2"); type=COP2; break;
6669 case 0x04: set_mnemonic(i, "MTC2"); type=COP2; break;
6670 case 0x06: set_mnemonic(i, "CTC2"); type=COP2; break;
b9b61529 6671 }
6672 break;
53dc27f6 6673 case 0x32: set_mnemonic(i, "LWC2"); type=C2LS; break;
6674 case 0x3A: set_mnemonic(i, "SWC2"); type=C2LS; break;
6675 case 0x3B: set_mnemonic(i, "HLECALL"); type=HLECALL; break;
6676 default: set_mnemonic(i, "???"); type=NI;
4149788d 6677 SysPrintf("NI %08x @%08x (%08x)\n", source[i], start + i*4, start);
90ae6d4e 6678 break;
57871462 6679 }
cf95b4f0 6680 dops[i].itype=type;
6681 dops[i].opcode2=op2;
57871462 6682 /* Get registers/immediates */
53dc27f6 6683 dops[i].use_lt1=0;
bedfea38 6684 gte_rs[i]=gte_rt[i]=0;
57871462 6685 switch(type) {
6686 case LOAD:
cf95b4f0 6687 dops[i].rs1=(source[i]>>21)&0x1f;
6688 dops[i].rs2=0;
6689 dops[i].rt1=(source[i]>>16)&0x1f;
6690 dops[i].rt2=0;
57871462 6691 imm[i]=(short)source[i];
6692 break;
6693 case STORE:
6694 case STORELR:
cf95b4f0 6695 dops[i].rs1=(source[i]>>21)&0x1f;
6696 dops[i].rs2=(source[i]>>16)&0x1f;
6697 dops[i].rt1=0;
6698 dops[i].rt2=0;
57871462 6699 imm[i]=(short)source[i];
57871462 6700 break;
6701 case LOADLR:
6702 // LWL/LWR only load part of the register,
6703 // therefore the target register must be treated as a source too
cf95b4f0 6704 dops[i].rs1=(source[i]>>21)&0x1f;
6705 dops[i].rs2=(source[i]>>16)&0x1f;
6706 dops[i].rt1=(source[i]>>16)&0x1f;
6707 dops[i].rt2=0;
57871462 6708 imm[i]=(short)source[i];
57871462 6709 break;
6710 case IMM16:
cf95b4f0 6711 if (op==0x0f) dops[i].rs1=0; // LUI instruction has no source register
6712 else dops[i].rs1=(source[i]>>21)&0x1f;
6713 dops[i].rs2=0;
6714 dops[i].rt1=(source[i]>>16)&0x1f;
6715 dops[i].rt2=0;
57871462 6716 if(op>=0x0c&&op<=0x0e) { // ANDI/ORI/XORI
6717 imm[i]=(unsigned short)source[i];
6718 }else{
6719 imm[i]=(short)source[i];
6720 }
57871462 6721 break;
6722 case UJUMP:
cf95b4f0 6723 dops[i].rs1=0;
6724 dops[i].rs2=0;
6725 dops[i].rt1=0;
6726 dops[i].rt2=0;
57871462 6727 // The JAL instruction writes to r31.
6728 if (op&1) {
cf95b4f0 6729 dops[i].rt1=31;
57871462 6730 }
cf95b4f0 6731 dops[i].rs2=CCREG;
57871462 6732 break;
6733 case RJUMP:
cf95b4f0 6734 dops[i].rs1=(source[i]>>21)&0x1f;
6735 dops[i].rs2=0;
6736 dops[i].rt1=0;
6737 dops[i].rt2=0;
5067f341 6738 // The JALR instruction writes to rd.
57871462 6739 if (op2&1) {
cf95b4f0 6740 dops[i].rt1=(source[i]>>11)&0x1f;
57871462 6741 }
cf95b4f0 6742 dops[i].rs2=CCREG;
57871462 6743 break;
6744 case CJUMP:
cf95b4f0 6745 dops[i].rs1=(source[i]>>21)&0x1f;
6746 dops[i].rs2=(source[i]>>16)&0x1f;
6747 dops[i].rt1=0;
6748 dops[i].rt2=0;
57871462 6749 if(op&2) { // BGTZ/BLEZ
cf95b4f0 6750 dops[i].rs2=0;
57871462 6751 }
57871462 6752 break;
6753 case SJUMP:
cf95b4f0 6754 dops[i].rs1=(source[i]>>21)&0x1f;
6755 dops[i].rs2=CCREG;
6756 dops[i].rt1=0;
6757 dops[i].rt2=0;
57871462 6758 if(op2&0x10) { // BxxAL
cf95b4f0 6759 dops[i].rt1=31;
57871462 6760 // NOTE: If the branch is not taken, r31 is still overwritten
6761 }
57871462 6762 break;
57871462 6763 case ALU:
cf95b4f0 6764 dops[i].rs1=(source[i]>>21)&0x1f; // source
6765 dops[i].rs2=(source[i]>>16)&0x1f; // subtract amount
6766 dops[i].rt1=(source[i]>>11)&0x1f; // destination
6767 dops[i].rt2=0;
57871462 6768 break;
6769 case MULTDIV:
cf95b4f0 6770 dops[i].rs1=(source[i]>>21)&0x1f; // source
6771 dops[i].rs2=(source[i]>>16)&0x1f; // divisor
6772 dops[i].rt1=HIREG;
6773 dops[i].rt2=LOREG;
57871462 6774 break;
6775 case MOV:
cf95b4f0 6776 dops[i].rs1=0;
6777 dops[i].rs2=0;
6778 dops[i].rt1=0;
6779 dops[i].rt2=0;
6780 if(op2==0x10) dops[i].rs1=HIREG; // MFHI
6781 if(op2==0x11) dops[i].rt1=HIREG; // MTHI
6782 if(op2==0x12) dops[i].rs1=LOREG; // MFLO
6783 if(op2==0x13) dops[i].rt1=LOREG; // MTLO
6784 if((op2&0x1d)==0x10) dops[i].rt1=(source[i]>>11)&0x1f; // MFxx
6785 if((op2&0x1d)==0x11) dops[i].rs1=(source[i]>>21)&0x1f; // MTxx
57871462 6786 break;
6787 case SHIFT:
cf95b4f0 6788 dops[i].rs1=(source[i]>>16)&0x1f; // target of shift
6789 dops[i].rs2=(source[i]>>21)&0x1f; // shift amount
6790 dops[i].rt1=(source[i]>>11)&0x1f; // destination
6791 dops[i].rt2=0;
57871462 6792 break;
6793 case SHIFTIMM:
cf95b4f0 6794 dops[i].rs1=(source[i]>>16)&0x1f;
6795 dops[i].rs2=0;
6796 dops[i].rt1=(source[i]>>11)&0x1f;
6797 dops[i].rt2=0;
57871462 6798 imm[i]=(source[i]>>6)&0x1f;
6799 // DSxx32 instructions
6800 if(op2>=0x3c) imm[i]|=0x20;
57871462 6801 break;
6802 case COP0:
cf95b4f0 6803 dops[i].rs1=0;
6804 dops[i].rs2=0;
6805 dops[i].rt1=0;
6806 dops[i].rt2=0;
6807 if(op2==0||op2==2) dops[i].rt1=(source[i]>>16)&0x1F; // MFC0/CFC0
6808 if(op2==4||op2==6) dops[i].rs1=(source[i]>>16)&0x1F; // MTC0/CTC0
6809 if(op2==4&&((source[i]>>11)&0x1f)==12) dops[i].rt2=CSREG; // Status
6810 if(op2==16) if((source[i]&0x3f)==0x18) dops[i].rs2=CCREG; // ERET
57871462 6811 break;
6812 case COP1:
cf95b4f0 6813 dops[i].rs1=0;
6814 dops[i].rs2=0;
6815 dops[i].rt1=0;
6816 dops[i].rt2=0;
6817 if(op2<3) dops[i].rt1=(source[i]>>16)&0x1F; // MFC1/DMFC1/CFC1
6818 if(op2>3) dops[i].rs1=(source[i]>>16)&0x1F; // MTC1/DMTC1/CTC1
6819 dops[i].rs2=CSREG;
57871462 6820 break;
bedfea38 6821 case COP2:
cf95b4f0 6822 dops[i].rs1=0;
6823 dops[i].rs2=0;
6824 dops[i].rt1=0;
6825 dops[i].rt2=0;
6826 if(op2<3) dops[i].rt1=(source[i]>>16)&0x1F; // MFC2/CFC2
6827 if(op2>3) dops[i].rs1=(source[i]>>16)&0x1F; // MTC2/CTC2
6828 dops[i].rs2=CSREG;
bedfea38 6829 int gr=(source[i]>>11)&0x1F;
6830 switch(op2)
6831 {
6832 case 0x00: gte_rs[i]=1ll<<gr; break; // MFC2
6833 case 0x04: gte_rt[i]=1ll<<gr; break; // MTC2
0ff8c62c 6834 case 0x02: gte_rs[i]=1ll<<(gr+32); break; // CFC2
bedfea38 6835 case 0x06: gte_rt[i]=1ll<<(gr+32); break; // CTC2
6836 }
6837 break;
57871462 6838 case C1LS:
cf95b4f0 6839 dops[i].rs1=(source[i]>>21)&0x1F;
6840 dops[i].rs2=CSREG;
6841 dops[i].rt1=0;
6842 dops[i].rt2=0;
57871462 6843 imm[i]=(short)source[i];
6844 break;
b9b61529 6845 case C2LS:
cf95b4f0 6846 dops[i].rs1=(source[i]>>21)&0x1F;
6847 dops[i].rs2=0;
6848 dops[i].rt1=0;
6849 dops[i].rt2=0;
b9b61529 6850 imm[i]=(short)source[i];
bedfea38 6851 if(op==0x32) gte_rt[i]=1ll<<((source[i]>>16)&0x1F); // LWC2
6852 else gte_rs[i]=1ll<<((source[i]>>16)&0x1F); // SWC2
6853 break;
6854 case C2OP:
cf95b4f0 6855 dops[i].rs1=0;
6856 dops[i].rs2=0;
6857 dops[i].rt1=0;
6858 dops[i].rt2=0;
2167bef6 6859 gte_rs[i]=gte_reg_reads[source[i]&0x3f];
6860 gte_rt[i]=gte_reg_writes[source[i]&0x3f];
6861 gte_rt[i]|=1ll<<63; // every op changes flags
587a5b1c 6862 if((source[i]&0x3f)==GTE_MVMVA) {
6863 int v = (source[i] >> 15) & 3;
6864 gte_rs[i]&=~0xe3fll;
6865 if(v==3) gte_rs[i]|=0xe00ll;
6866 else gte_rs[i]|=3ll<<(v*2);
6867 }
b9b61529 6868 break;
57871462 6869 case SYSCALL:
7139f3c8 6870 case HLECALL:
1e973cb0 6871 case INTCALL:
cf95b4f0 6872 dops[i].rs1=CCREG;
6873 dops[i].rs2=0;
6874 dops[i].rt1=0;
6875 dops[i].rt2=0;
57871462 6876 break;
6877 default:
cf95b4f0 6878 dops[i].rs1=0;
6879 dops[i].rs2=0;
6880 dops[i].rt1=0;
6881 dops[i].rt2=0;
57871462 6882 }
6883 /* Calculate branch target addresses */
6884 if(type==UJUMP)
6885 ba[i]=((start+i*4+4)&0xF0000000)|(((unsigned int)source[i]<<6)>>4);
cf95b4f0 6886 else if(type==CJUMP&&dops[i].rs1==dops[i].rs2&&(op&1))
57871462 6887 ba[i]=start+i*4+8; // Ignore never taken branch
cf95b4f0 6888 else if(type==SJUMP&&dops[i].rs1==0&&!(op2&1))
57871462 6889 ba[i]=start+i*4+8; // Ignore never taken branch
ad49de89 6890 else if(type==CJUMP||type==SJUMP)
57871462 6891 ba[i]=start+i*4+4+((signed int)((unsigned int)source[i]<<16)>>14);
6892 else ba[i]=-1;
4919de1e 6893
6894 /* simplify always (not)taken branches */
cf95b4f0 6895 if (type == CJUMP && dops[i].rs1 == dops[i].rs2) {
6896 dops[i].rs1 = dops[i].rs2 = 0;
4919de1e 6897 if (!(op & 1)) {
cf95b4f0 6898 dops[i].itype = type = UJUMP;
6899 dops[i].rs2 = CCREG;
4919de1e 6900 }
6901 }
cf95b4f0 6902 else if (type == SJUMP && dops[i].rs1 == 0 && (op2 & 1))
6903 dops[i].itype = type = UJUMP;
4919de1e 6904
fe807a8a 6905 dops[i].is_jump = (dops[i].itype == RJUMP || dops[i].itype == UJUMP || dops[i].itype == CJUMP || dops[i].itype == SJUMP);
6906 dops[i].is_ujump = (dops[i].itype == RJUMP || dops[i].itype == UJUMP); // || (source[i] >> 16) == 0x1000 // beq r0,r0
37387d8b 6907 dops[i].is_load = (dops[i].itype == LOAD || dops[i].itype == LOADLR || op == 0x32); // LWC2
6908 dops[i].is_store = (dops[i].itype == STORE || dops[i].itype == STORELR || op == 0x3a); // SWC2
fe807a8a 6909
4919de1e 6910 /* messy cases to just pass over to the interpreter */
fe807a8a 6911 if (i > 0 && dops[i-1].is_jump) {
3e535354 6912 int do_in_intrp=0;
6913 // branch in delay slot?
fe807a8a 6914 if (dops[i].is_jump) {
3e535354 6915 // don't handle first branch and call interpreter if it's hit
4149788d 6916 SysPrintf("branch in delay slot @%08x (%08x)\n", start + i*4, start);
3e535354 6917 do_in_intrp=1;
6918 }
6919 // basic load delay detection
cf95b4f0 6920 else if((type==LOAD||type==LOADLR||type==COP0||type==COP2||type==C2LS)&&dops[i].rt1!=0) {
3e535354 6921 int t=(ba[i-1]-start)/4;
cf95b4f0 6922 if(0 <= t && t < i &&(dops[i].rt1==dops[t].rs1||dops[i].rt1==dops[t].rs2)&&dops[t].itype!=CJUMP&&dops[t].itype!=SJUMP) {
3e535354 6923 // jump target wants DS result - potential load delay effect
4149788d 6924 SysPrintf("load delay @%08x (%08x)\n", start + i*4, start);
3e535354 6925 do_in_intrp=1;
cf95b4f0 6926 dops[t+1].bt=1; // expected return from interpreter
3e535354 6927 }
cf95b4f0 6928 else if(i>=2&&dops[i-2].rt1==2&&dops[i].rt1==2&&dops[i].rs1!=2&&dops[i].rs2!=2&&dops[i-1].rs1!=2&&dops[i-1].rs2!=2&&
fe807a8a 6929 !(i>=3&&dops[i-3].is_jump)) {
3e535354 6930 // v0 overwrite like this is a sign of trouble, bail out
4149788d 6931 SysPrintf("v0 overwrite @%08x (%08x)\n", start + i*4, start);
3e535354 6932 do_in_intrp=1;
6933 }
6934 }
7ebfcedf 6935 if (do_in_intrp) {
6936 memset(&dops[i-1], 0, sizeof(dops[i-1]));
6937 dops[i-1].itype = INTCALL;
6938 dops[i-1].rs1 = CCREG;
6939 ba[i-1] = -1;
6940 done = 2;
3e535354 6941 i--; // don't compile the DS
26869094 6942 }
3e535354 6943 }
4919de1e 6944
3e535354 6945 /* Is this the end of the block? */
fe807a8a 6946 if (i > 0 && dops[i-1].is_ujump) {
0787af86 6947 if (dops[i-1].rt1 == 0) { // not jal
6948 int found_bbranch = 0, t = (ba[i-1] - start) / 4;
6949 if ((u_int)(t - i) < 64 && start + (t+64)*4 < pagelimit) {
6950 // scan for a branch back to i+1
6951 for (j = t; j < t + 64; j++) {
6952 int tmpop = source[j] >> 26;
6953 if (tmpop == 1 || ((tmpop & ~3) == 4)) {
6954 int t2 = j + 1 + (int)(signed short)source[j];
6955 if (t2 == i + 1) {
6956 //printf("blk expand %08x<-%08x\n", start + (i+1)*4, start + j*4);
6957 found_bbranch = 1;
6958 break;
6959 }
6960 }
6961 }
6962 }
6963 if (!found_bbranch)
6964 done = 2;
57871462 6965 }
6966 else {
6967 if(stop_after_jal) done=1;
6968 // Stop on BREAK
6969 if((source[i+1]&0xfc00003f)==0x0d) done=1;
6970 }
6971 // Don't recompile stuff that's already compiled
6972 if(check_addr(start+i*4+4)) done=1;
6973 // Don't get too close to the limit
6974 if(i>MAXBLOCK/2) done=1;
6975 }
d1150cd6 6976 if (dops[i].itype == SYSCALL || dops[i].itype == HLECALL || dops[i].itype == INTCALL)
6977 done = stop_after_jal ? 1 : 2;
6978 if (done == 2) {
1e973cb0 6979 // Does the block continue due to a branch?
6980 for(j=i-1;j>=0;j--)
6981 {
2a706964 6982 if(ba[j]==start+i*4) done=j=0; // Branch into delay slot
1e973cb0 6983 if(ba[j]==start+i*4+4) done=j=0;
6984 if(ba[j]==start+i*4+8) done=j=0;
6985 }
6986 }
75dec299 6987 //assert(i<MAXBLOCK-1);
57871462 6988 if(start+i*4==pagelimit-4) done=1;
6989 assert(start+i*4<pagelimit);
6990 if (i==MAXBLOCK-1) done=1;
6991 // Stop if we're compiling junk
b4ab351d 6992 if(dops[i].itype == NI && (++ni_count > 8 || dops[i].opcode == 0x11)) {
57871462 6993 done=stop_after_jal=1;
c43b5311 6994 SysPrintf("Disabled speculative precompilation\n");
57871462 6995 }
6996 }
4bdc30ab 6997 while (i > 0 && dops[i-1].is_jump)
6998 i--;
6999 assert(i > 0);
7000 assert(!dops[i-1].is_jump);
7001 slen = i;
4149788d 7002}
7003
7004// Basic liveness analysis for MIPS registers
7005static noinline void pass2_unneeded_regs(int istart,int iend,int r)
7006{
7007 int i;
7008 uint64_t u,gte_u,b,gte_b;
7009 uint64_t temp_u,temp_gte_u=0;
7010 uint64_t gte_u_unknown=0;
7011 if (HACK_ENABLED(NDHACK_GTE_UNNEEDED))
7012 gte_u_unknown=~0ll;
7013 if(iend==slen-1) {
7014 u=1;
7015 gte_u=gte_u_unknown;
7016 }else{
7017 //u=unneeded_reg[iend+1];
7018 u=1;
7019 gte_u=gte_unneeded[iend+1];
7020 }
7021
7022 for (i=iend;i>=istart;i--)
7023 {
7024 //printf("unneeded registers i=%d (%d,%d) r=%d\n",i,istart,iend,r);
7025 if(dops[i].is_jump)
7026 {
7027 // If subroutine call, flag return address as a possible branch target
7028 if(dops[i].rt1==31 && i<slen-2) dops[i+2].bt=1;
7029
7030 if(ba[i]<start || ba[i]>=(start+slen*4))
7031 {
7032 // Branch out of this block, flush all regs
7033 u=1;
7034 gte_u=gte_u_unknown;
7035 branch_unneeded_reg[i]=u;
7036 // Merge in delay slot
7037 u|=(1LL<<dops[i+1].rt1)|(1LL<<dops[i+1].rt2);
7038 u&=~((1LL<<dops[i+1].rs1)|(1LL<<dops[i+1].rs2));
7039 u|=1;
7040 gte_u|=gte_rt[i+1];
7041 gte_u&=~gte_rs[i+1];
7042 }
7043 else
7044 {
7045 // Internal branch, flag target
7046 dops[(ba[i]-start)>>2].bt=1;
7047 if(ba[i]<=start+i*4) {
7048 // Backward branch
7049 if(dops[i].is_ujump)
7050 {
7051 // Unconditional branch
7052 temp_u=1;
7053 temp_gte_u=0;
7054 } else {
7055 // Conditional branch (not taken case)
7056 temp_u=unneeded_reg[i+2];
7057 temp_gte_u&=gte_unneeded[i+2];
7058 }
7059 // Merge in delay slot
7060 temp_u|=(1LL<<dops[i+1].rt1)|(1LL<<dops[i+1].rt2);
7061 temp_u&=~((1LL<<dops[i+1].rs1)|(1LL<<dops[i+1].rs2));
7062 temp_u|=1;
7063 temp_gte_u|=gte_rt[i+1];
7064 temp_gte_u&=~gte_rs[i+1];
7065 temp_u|=(1LL<<dops[i].rt1)|(1LL<<dops[i].rt2);
7066 temp_u&=~((1LL<<dops[i].rs1)|(1LL<<dops[i].rs2));
7067 temp_u|=1;
7068 temp_gte_u|=gte_rt[i];
7069 temp_gte_u&=~gte_rs[i];
7070 unneeded_reg[i]=temp_u;
7071 gte_unneeded[i]=temp_gte_u;
7072 // Only go three levels deep. This recursion can take an
7073 // excessive amount of time if there are a lot of nested loops.
7074 if(r<2) {
7075 pass2_unneeded_regs((ba[i]-start)>>2,i-1,r+1);
7076 }else{
7077 unneeded_reg[(ba[i]-start)>>2]=1;
7078 gte_unneeded[(ba[i]-start)>>2]=gte_u_unknown;
7079 }
7080 } /*else*/ if(1) {
7081 if (dops[i].is_ujump)
7082 {
7083 // Unconditional branch
7084 u=unneeded_reg[(ba[i]-start)>>2];
7085 gte_u=gte_unneeded[(ba[i]-start)>>2];
7086 branch_unneeded_reg[i]=u;
7087 // Merge in delay slot
7088 u|=(1LL<<dops[i+1].rt1)|(1LL<<dops[i+1].rt2);
7089 u&=~((1LL<<dops[i+1].rs1)|(1LL<<dops[i+1].rs2));
7090 u|=1;
7091 gte_u|=gte_rt[i+1];
7092 gte_u&=~gte_rs[i+1];
7093 } else {
7094 // Conditional branch
7095 b=unneeded_reg[(ba[i]-start)>>2];
7096 gte_b=gte_unneeded[(ba[i]-start)>>2];
7097 branch_unneeded_reg[i]=b;
7098 // Branch delay slot
7099 b|=(1LL<<dops[i+1].rt1)|(1LL<<dops[i+1].rt2);
7100 b&=~((1LL<<dops[i+1].rs1)|(1LL<<dops[i+1].rs2));
7101 b|=1;
7102 gte_b|=gte_rt[i+1];
7103 gte_b&=~gte_rs[i+1];
7104 u&=b;
7105 gte_u&=gte_b;
7106 if(i<slen-1) {
7107 branch_unneeded_reg[i]&=unneeded_reg[i+2];
7108 } else {
7109 branch_unneeded_reg[i]=1;
7110 }
7111 }
7112 }
7113 }
7114 }
7115 else if(dops[i].itype==SYSCALL||dops[i].itype==HLECALL||dops[i].itype==INTCALL)
7116 {
7117 // SYSCALL instruction (software interrupt)
7118 u=1;
7119 }
55a695d9 7120 else if(dops[i].itype==COP0 && dops[i].opcode2==0x10)
4149788d 7121 {
55a695d9 7122 // RFE
4149788d 7123 u=1;
7124 }
7125 //u=1; // DEBUG
7126 // Written registers are unneeded
7127 u|=1LL<<dops[i].rt1;
7128 u|=1LL<<dops[i].rt2;
7129 gte_u|=gte_rt[i];
7130 // Accessed registers are needed
7131 u&=~(1LL<<dops[i].rs1);
7132 u&=~(1LL<<dops[i].rs2);
7133 gte_u&=~gte_rs[i];
7134 if(gte_rs[i]&&dops[i].rt1&&(unneeded_reg[i+1]&(1ll<<dops[i].rt1)))
7135 gte_u|=gte_rs[i]&gte_unneeded[i+1]; // MFC2/CFC2 to dead register, unneeded
7136 // Source-target dependencies
7137 // R0 is always unneeded
7138 u|=1;
7139 // Save it
7140 unneeded_reg[i]=u;
7141 gte_unneeded[i]=gte_u;
7142 /*
7143 printf("ur (%d,%d) %x: ",istart,iend,start+i*4);
7144 printf("U:");
7145 int r;
7146 for(r=1;r<=CCREG;r++) {
7147 if((unneeded_reg[i]>>r)&1) {
7148 if(r==HIREG) printf(" HI");
7149 else if(r==LOREG) printf(" LO");
7150 else printf(" r%d",r);
7151 }
7152 }
7153 printf("\n");
7154 */
7155 }
7156}
57871462 7157
4149788d 7158static noinline void pass3_register_alloc(u_int addr)
7159{
57871462 7160 struct regstat current; // Current register allocations/status
6cc8d23c 7161 clear_all_regs(current.regmap_entry);
57871462 7162 clear_all_regs(current.regmap);
6cc8d23c 7163 current.wasdirty = current.dirty = 0;
7164 current.u = unneeded_reg[0];
7165 alloc_reg(&current, 0, CCREG);
7166 dirty_reg(&current, CCREG);
7167 current.wasconst = 0;
7168 current.isconst = 0;
7169 current.loadedconst = 0;
7170 current.waswritten = 0;
57871462 7171 int ds=0;
7172 int cc=0;
4149788d 7173 int hr;
7174 int i, j;
6ebf4adf 7175
4149788d 7176 if (addr & 1) {
57871462 7177 // First instruction is delay slot
7178 cc=-1;
cf95b4f0 7179 dops[1].bt=1;
57871462 7180 ds=1;
7181 unneeded_reg[0]=1;
57871462 7182 current.regmap[HOST_BTREG]=BTREG;
7183 }
9f51b4b9 7184
57871462 7185 for(i=0;i<slen;i++)
7186 {
cf95b4f0 7187 if(dops[i].bt)
57871462 7188 {
57871462 7189 for(hr=0;hr<HOST_REGS;hr++)
7190 {
7191 // Is this really necessary?
7192 if(current.regmap[hr]==0) current.regmap[hr]=-1;
7193 }
7194 current.isconst=0;
27727b63 7195 current.waswritten=0;
57871462 7196 }
24385cae 7197
57871462 7198 memcpy(regmap_pre[i],current.regmap,sizeof(current.regmap));
7199 regs[i].wasconst=current.isconst;
57871462 7200 regs[i].wasdirty=current.dirty;
6cc8d23c 7201 regs[i].dirty=0;
7202 regs[i].u=0;
7203 regs[i].isconst=0;
8575a877 7204 regs[i].loadedconst=0;
fe807a8a 7205 if (!dops[i].is_jump) {
57871462 7206 if(i+1<slen) {
cf95b4f0 7207 current.u=unneeded_reg[i+1]&~((1LL<<dops[i].rs1)|(1LL<<dops[i].rs2));
57871462 7208 current.u|=1;
57871462 7209 } else {
7210 current.u=1;
57871462 7211 }
7212 } else {
7213 if(i+1<slen) {
cf95b4f0 7214 current.u=branch_unneeded_reg[i]&~((1LL<<dops[i+1].rs1)|(1LL<<dops[i+1].rs2));
7215 current.u&=~((1LL<<dops[i].rs1)|(1LL<<dops[i].rs2));
57871462 7216 current.u|=1;
7ebfcedf 7217 } else {
7218 SysPrintf("oops, branch at end of block with no delay slot @%08x\n", start + i*4);
7219 abort();
7220 }
57871462 7221 }
cf95b4f0 7222 dops[i].is_ds=ds;
57871462 7223 if(ds) {
7224 ds=0; // Skip delay slot, already allocated as part of branch
7225 // ...but we need to alloc it in case something jumps here
7226 if(i+1<slen) {
7227 current.u=branch_unneeded_reg[i-1]&unneeded_reg[i+1];
57871462 7228 }else{
7229 current.u=branch_unneeded_reg[i-1];
57871462 7230 }
cf95b4f0 7231 current.u&=~((1LL<<dops[i].rs1)|(1LL<<dops[i].rs2));
57871462 7232 current.u|=1;
57871462 7233 struct regstat temp;
7234 memcpy(&temp,&current,sizeof(current));
7235 temp.wasdirty=temp.dirty;
57871462 7236 // TODO: Take into account unconditional branches, as below
7237 delayslot_alloc(&temp,i);
7238 memcpy(regs[i].regmap,temp.regmap,sizeof(temp.regmap));
7239 regs[i].wasdirty=temp.wasdirty;
57871462 7240 regs[i].dirty=temp.dirty;
57871462 7241 regs[i].isconst=0;
7242 regs[i].wasconst=0;
7243 current.isconst=0;
7244 // Create entry (branch target) regmap
7245 for(hr=0;hr<HOST_REGS;hr++)
7246 {
7247 int r=temp.regmap[hr];
7248 if(r>=0) {
7249 if(r!=regmap_pre[i][hr]) {
7250 regs[i].regmap_entry[hr]=-1;
7251 }
7252 else
7253 {
7c3a5182 7254 assert(r < 64);
57871462 7255 if((current.u>>r)&1) {
7256 regs[i].regmap_entry[hr]=-1;
7257 regs[i].regmap[hr]=-1;
7258 //Don't clear regs in the delay slot as the branch might need them
7259 //current.regmap[hr]=-1;
7260 }else
7261 regs[i].regmap_entry[hr]=r;
57871462 7262 }
7263 } else {
7264 // First instruction expects CCREG to be allocated
9f51b4b9 7265 if(i==0&&hr==HOST_CCREG)
57871462 7266 regs[i].regmap_entry[hr]=CCREG;
7267 else
7268 regs[i].regmap_entry[hr]=-1;
7269 }
7270 }
7271 }
7272 else { // Not delay slot
cf95b4f0 7273 switch(dops[i].itype) {
57871462 7274 case UJUMP:
7275 //current.isconst=0; // DEBUG
7276 //current.wasconst=0; // DEBUG
7277 //regs[i].wasconst=0; // DEBUG
cf95b4f0 7278 clear_const(&current,dops[i].rt1);
57871462 7279 alloc_cc(&current,i);
7280 dirty_reg(&current,CCREG);
cf95b4f0 7281 if (dops[i].rt1==31) {
57871462 7282 alloc_reg(&current,i,31);
7283 dirty_reg(&current,31);
cf95b4f0 7284 //assert(dops[i+1].rs1!=31&&dops[i+1].rs2!=31);
7285 //assert(dops[i+1].rt1!=dops[i].rt1);
57871462 7286 #ifdef REG_PREFETCH
7287 alloc_reg(&current,i,PTEMP);
7288 #endif
57871462 7289 }
cf95b4f0 7290 dops[i].ooo=1;
269bb29a 7291 delayslot_alloc(&current,i+1);
57871462 7292 //current.isconst=0; // DEBUG
7293 ds=1;
7294 //printf("i=%d, isconst=%x\n",i,current.isconst);
7295 break;
7296 case RJUMP:
7297 //current.isconst=0;
7298 //current.wasconst=0;
7299 //regs[i].wasconst=0;
cf95b4f0 7300 clear_const(&current,dops[i].rs1);
7301 clear_const(&current,dops[i].rt1);
57871462 7302 alloc_cc(&current,i);
7303 dirty_reg(&current,CCREG);
4919de1e 7304 if (!ds_writes_rjump_rs(i)) {
cf95b4f0 7305 alloc_reg(&current,i,dops[i].rs1);
7306 if (dops[i].rt1!=0) {
7307 alloc_reg(&current,i,dops[i].rt1);
7308 dirty_reg(&current,dops[i].rt1);
7309 assert(dops[i+1].rs1!=dops[i].rt1&&dops[i+1].rs2!=dops[i].rt1);
7310 assert(dops[i+1].rt1!=dops[i].rt1);
57871462 7311 #ifdef REG_PREFETCH
7312 alloc_reg(&current,i,PTEMP);
7313 #endif
7314 }
7315 #ifdef USE_MINI_HT
cf95b4f0 7316 if(dops[i].rs1==31) { // JALR
57871462 7317 alloc_reg(&current,i,RHASH);
57871462 7318 alloc_reg(&current,i,RHTBL);
57871462 7319 }
7320 #endif
7321 delayslot_alloc(&current,i+1);
7322 } else {
7323 // The delay slot overwrites our source register,
7324 // allocate a temporary register to hold the old value.
7325 current.isconst=0;
7326 current.wasconst=0;
7327 regs[i].wasconst=0;
7328 delayslot_alloc(&current,i+1);
7329 current.isconst=0;
7330 alloc_reg(&current,i,RTEMP);
7331 }
7332 //current.isconst=0; // DEBUG
cf95b4f0 7333 dops[i].ooo=1;
57871462 7334 ds=1;
7335 break;
7336 case CJUMP:
7337 //current.isconst=0;
7338 //current.wasconst=0;
7339 //regs[i].wasconst=0;
cf95b4f0 7340 clear_const(&current,dops[i].rs1);
7341 clear_const(&current,dops[i].rs2);
7342 if((dops[i].opcode&0x3E)==4) // BEQ/BNE
57871462 7343 {
7344 alloc_cc(&current,i);
7345 dirty_reg(&current,CCREG);
cf95b4f0 7346 if(dops[i].rs1) alloc_reg(&current,i,dops[i].rs1);
7347 if(dops[i].rs2) alloc_reg(&current,i,dops[i].rs2);
7348 if((dops[i].rs1&&(dops[i].rs1==dops[i+1].rt1||dops[i].rs1==dops[i+1].rt2))||
7349 (dops[i].rs2&&(dops[i].rs2==dops[i+1].rt1||dops[i].rs2==dops[i+1].rt2))) {
57871462 7350 // The delay slot overwrites one of our conditions.
7351 // Allocate the branch condition registers instead.
57871462 7352 current.isconst=0;
7353 current.wasconst=0;
7354 regs[i].wasconst=0;
cf95b4f0 7355 if(dops[i].rs1) alloc_reg(&current,i,dops[i].rs1);
7356 if(dops[i].rs2) alloc_reg(&current,i,dops[i].rs2);
57871462 7357 }
e1190b87 7358 else
7359 {
cf95b4f0 7360 dops[i].ooo=1;
e1190b87 7361 delayslot_alloc(&current,i+1);
7362 }
57871462 7363 }
7364 else
cf95b4f0 7365 if((dops[i].opcode&0x3E)==6) // BLEZ/BGTZ
57871462 7366 {
7367 alloc_cc(&current,i);
7368 dirty_reg(&current,CCREG);
cf95b4f0 7369 alloc_reg(&current,i,dops[i].rs1);
7370 if(dops[i].rs1&&(dops[i].rs1==dops[i+1].rt1||dops[i].rs1==dops[i+1].rt2)) {
57871462 7371 // The delay slot overwrites one of our conditions.
7372 // Allocate the branch condition registers instead.
57871462 7373 current.isconst=0;
7374 current.wasconst=0;
7375 regs[i].wasconst=0;
cf95b4f0 7376 if(dops[i].rs1) alloc_reg(&current,i,dops[i].rs1);
57871462 7377 }
e1190b87 7378 else
7379 {
cf95b4f0 7380 dops[i].ooo=1;
e1190b87 7381 delayslot_alloc(&current,i+1);
7382 }
57871462 7383 }
7384 else
7385 // Don't alloc the delay slot yet because we might not execute it
cf95b4f0 7386 if((dops[i].opcode&0x3E)==0x14) // BEQL/BNEL
57871462 7387 {
7388 current.isconst=0;
7389 current.wasconst=0;
7390 regs[i].wasconst=0;
7391 alloc_cc(&current,i);
7392 dirty_reg(&current,CCREG);
cf95b4f0 7393 alloc_reg(&current,i,dops[i].rs1);
7394 alloc_reg(&current,i,dops[i].rs2);
57871462 7395 }
7396 else
cf95b4f0 7397 if((dops[i].opcode&0x3E)==0x16) // BLEZL/BGTZL
57871462 7398 {
7399 current.isconst=0;
7400 current.wasconst=0;
7401 regs[i].wasconst=0;
7402 alloc_cc(&current,i);
7403 dirty_reg(&current,CCREG);
cf95b4f0 7404 alloc_reg(&current,i,dops[i].rs1);
57871462 7405 }
7406 ds=1;
7407 //current.isconst=0;
7408 break;
7409 case SJUMP:
7410 //current.isconst=0;
7411 //current.wasconst=0;
7412 //regs[i].wasconst=0;
cf95b4f0 7413 clear_const(&current,dops[i].rs1);
7414 clear_const(&current,dops[i].rt1);
7415 //if((dops[i].opcode2&0x1E)==0x0) // BLTZ/BGEZ
7416 if((dops[i].opcode2&0x0E)==0x0) // BLTZ/BGEZ
57871462 7417 {
7418 alloc_cc(&current,i);
7419 dirty_reg(&current,CCREG);
cf95b4f0 7420 alloc_reg(&current,i,dops[i].rs1);
7421 if (dops[i].rt1==31) { // BLTZAL/BGEZAL
57871462 7422 alloc_reg(&current,i,31);
7423 dirty_reg(&current,31);
57871462 7424 //#ifdef REG_PREFETCH
7425 //alloc_reg(&current,i,PTEMP);
7426 //#endif
57871462 7427 }
cf95b4f0 7428 if((dops[i].rs1&&(dops[i].rs1==dops[i+1].rt1||dops[i].rs1==dops[i+1].rt2)) // The delay slot overwrites the branch condition.
7429 ||(dops[i].rt1==31&&(dops[i+1].rs1==31||dops[i+1].rs2==31||dops[i+1].rt1==31||dops[i+1].rt2==31))) { // DS touches $ra
57871462 7430 // Allocate the branch condition registers instead.
57871462 7431 current.isconst=0;
7432 current.wasconst=0;
7433 regs[i].wasconst=0;
cf95b4f0 7434 if(dops[i].rs1) alloc_reg(&current,i,dops[i].rs1);
57871462 7435 }
e1190b87 7436 else
7437 {
cf95b4f0 7438 dops[i].ooo=1;
e1190b87 7439 delayslot_alloc(&current,i+1);
7440 }
57871462 7441 }
7442 else
7443 // Don't alloc the delay slot yet because we might not execute it
cf95b4f0 7444 if((dops[i].opcode2&0x1E)==0x2) // BLTZL/BGEZL
57871462 7445 {
7446 current.isconst=0;
7447 current.wasconst=0;
7448 regs[i].wasconst=0;
7449 alloc_cc(&current,i);
7450 dirty_reg(&current,CCREG);
cf95b4f0 7451 alloc_reg(&current,i,dops[i].rs1);
57871462 7452 }
7453 ds=1;
7454 //current.isconst=0;
7455 break;
57871462 7456 case IMM16:
7457 imm16_alloc(&current,i);
7458 break;
7459 case LOAD:
7460 case LOADLR:
7461 load_alloc(&current,i);
7462 break;
7463 case STORE:
7464 case STORELR:
7465 store_alloc(&current,i);
7466 break;
7467 case ALU:
7468 alu_alloc(&current,i);
7469 break;
7470 case SHIFT:
7471 shift_alloc(&current,i);
7472 break;
7473 case MULTDIV:
7474 multdiv_alloc(&current,i);
7475 break;
7476 case SHIFTIMM:
7477 shiftimm_alloc(&current,i);
7478 break;
7479 case MOV:
7480 mov_alloc(&current,i);
7481 break;
7482 case COP0:
7483 cop0_alloc(&current,i);
7484 break;
7485 case COP1:
81dbbf4c 7486 break;
b9b61529 7487 case COP2:
81dbbf4c 7488 cop2_alloc(&current,i);
57871462 7489 break;
7490 case C1LS:
7491 c1ls_alloc(&current,i);
7492 break;
b9b61529 7493 case C2LS:
7494 c2ls_alloc(&current,i);
7495 break;
7496 case C2OP:
7497 c2op_alloc(&current,i);
7498 break;
57871462 7499 case SYSCALL:
7139f3c8 7500 case HLECALL:
1e973cb0 7501 case INTCALL:
57871462 7502 syscall_alloc(&current,i);
7503 break;
57871462 7504 }
9f51b4b9 7505
57871462 7506 // Create entry (branch target) regmap
7507 for(hr=0;hr<HOST_REGS;hr++)
7508 {
581335b0 7509 int r,or;
57871462 7510 r=current.regmap[hr];
7511 if(r>=0) {
7512 if(r!=regmap_pre[i][hr]) {
7513 // TODO: delay slot (?)
7514 or=get_reg(regmap_pre[i],r); // Get old mapping for this register
9de8a0c3 7515 if(or<0||r>=TEMPREG){
57871462 7516 regs[i].regmap_entry[hr]=-1;
7517 }
7518 else
7519 {
7520 // Just move it to a different register
7521 regs[i].regmap_entry[hr]=r;
7522 // If it was dirty before, it's still dirty
9de8a0c3 7523 if((regs[i].wasdirty>>or)&1) dirty_reg(&current,r);
57871462 7524 }
7525 }
7526 else
7527 {
7528 // Unneeded
7529 if(r==0){
7530 regs[i].regmap_entry[hr]=0;
7531 }
7532 else
7c3a5182 7533 {
7534 assert(r<64);
57871462 7535 if((current.u>>r)&1) {
7536 regs[i].regmap_entry[hr]=-1;
7537 //regs[i].regmap[hr]=-1;
7538 current.regmap[hr]=-1;
7539 }else
7540 regs[i].regmap_entry[hr]=r;
7541 }
57871462 7542 }
7543 } else {
7544 // Branches expect CCREG to be allocated at the target
9f51b4b9 7545 if(regmap_pre[i][hr]==CCREG)
57871462 7546 regs[i].regmap_entry[hr]=CCREG;
7547 else
7548 regs[i].regmap_entry[hr]=-1;
7549 }
7550 }
7551 memcpy(regs[i].regmap,current.regmap,sizeof(current.regmap));
7552 }
27727b63 7553
cf95b4f0 7554 if(i>0&&(dops[i-1].itype==STORE||dops[i-1].itype==STORELR||(dops[i-1].itype==C2LS&&dops[i-1].opcode==0x3a))&&(u_int)imm[i-1]<0x800)
7555 current.waswritten|=1<<dops[i-1].rs1;
7556 current.waswritten&=~(1<<dops[i].rt1);
7557 current.waswritten&=~(1<<dops[i].rt2);
7558 if((dops[i].itype==STORE||dops[i].itype==STORELR||(dops[i].itype==C2LS&&dops[i].opcode==0x3a))&&(u_int)imm[i]>=0x800)
7559 current.waswritten&=~(1<<dops[i].rs1);
27727b63 7560
57871462 7561 /* Branch post-alloc */
7562 if(i>0)
7563 {
57871462 7564 current.wasdirty=current.dirty;
cf95b4f0 7565 switch(dops[i-1].itype) {
57871462 7566 case UJUMP:
7567 memcpy(&branch_regs[i-1],&current,sizeof(current));
7568 branch_regs[i-1].isconst=0;
7569 branch_regs[i-1].wasconst=0;
cf95b4f0 7570 branch_regs[i-1].u=branch_unneeded_reg[i-1]&~((1LL<<dops[i-1].rs1)|(1LL<<dops[i-1].rs2));
57871462 7571 alloc_cc(&branch_regs[i-1],i-1);
7572 dirty_reg(&branch_regs[i-1],CCREG);
cf95b4f0 7573 if(dops[i-1].rt1==31) { // JAL
57871462 7574 alloc_reg(&branch_regs[i-1],i-1,31);
7575 dirty_reg(&branch_regs[i-1],31);
57871462 7576 }
7577 memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
40fca85b 7578 memcpy(constmap[i],constmap[i-1],sizeof(constmap[i]));
57871462 7579 break;
7580 case RJUMP:
7581 memcpy(&branch_regs[i-1],&current,sizeof(current));
7582 branch_regs[i-1].isconst=0;
7583 branch_regs[i-1].wasconst=0;
cf95b4f0 7584 branch_regs[i-1].u=branch_unneeded_reg[i-1]&~((1LL<<dops[i-1].rs1)|(1LL<<dops[i-1].rs2));
57871462 7585 alloc_cc(&branch_regs[i-1],i-1);
7586 dirty_reg(&branch_regs[i-1],CCREG);
cf95b4f0 7587 alloc_reg(&branch_regs[i-1],i-1,dops[i-1].rs1);
7588 if(dops[i-1].rt1!=0) { // JALR
7589 alloc_reg(&branch_regs[i-1],i-1,dops[i-1].rt1);
7590 dirty_reg(&branch_regs[i-1],dops[i-1].rt1);
57871462 7591 }
7592 #ifdef USE_MINI_HT
cf95b4f0 7593 if(dops[i-1].rs1==31) { // JALR
57871462 7594 alloc_reg(&branch_regs[i-1],i-1,RHASH);
57871462 7595 alloc_reg(&branch_regs[i-1],i-1,RHTBL);
57871462 7596 }
7597 #endif
7598 memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
40fca85b 7599 memcpy(constmap[i],constmap[i-1],sizeof(constmap[i]));
57871462 7600 break;
7601 case CJUMP:
cf95b4f0 7602 if((dops[i-1].opcode&0x3E)==4) // BEQ/BNE
57871462 7603 {
7604 alloc_cc(&current,i-1);
7605 dirty_reg(&current,CCREG);
cf95b4f0 7606 if((dops[i-1].rs1&&(dops[i-1].rs1==dops[i].rt1||dops[i-1].rs1==dops[i].rt2))||
7607 (dops[i-1].rs2&&(dops[i-1].rs2==dops[i].rt1||dops[i-1].rs2==dops[i].rt2))) {
57871462 7608 // The delay slot overwrote one of our conditions
7609 // Delay slot goes after the test (in order)
cf95b4f0 7610 current.u=branch_unneeded_reg[i-1]&~((1LL<<dops[i].rs1)|(1LL<<dops[i].rs2));
57871462 7611 current.u|=1;
57871462 7612 delayslot_alloc(&current,i);
7613 current.isconst=0;
7614 }
7615 else
7616 {
cf95b4f0 7617 current.u=branch_unneeded_reg[i-1]&~((1LL<<dops[i-1].rs1)|(1LL<<dops[i-1].rs2));
57871462 7618 // Alloc the branch condition registers
cf95b4f0 7619 if(dops[i-1].rs1) alloc_reg(&current,i-1,dops[i-1].rs1);
7620 if(dops[i-1].rs2) alloc_reg(&current,i-1,dops[i-1].rs2);
57871462 7621 }
7622 memcpy(&branch_regs[i-1],&current,sizeof(current));
7623 branch_regs[i-1].isconst=0;
7624 branch_regs[i-1].wasconst=0;
7625 memcpy(&branch_regs[i-1].regmap_entry,&current.regmap,sizeof(current.regmap));
40fca85b 7626 memcpy(constmap[i],constmap[i-1],sizeof(constmap[i]));
57871462 7627 }
7628 else
cf95b4f0 7629 if((dops[i-1].opcode&0x3E)==6) // BLEZ/BGTZ
57871462 7630 {
7631 alloc_cc(&current,i-1);
7632 dirty_reg(&current,CCREG);
cf95b4f0 7633 if(dops[i-1].rs1==dops[i].rt1||dops[i-1].rs1==dops[i].rt2) {
57871462 7634 // The delay slot overwrote the branch condition
7635 // Delay slot goes after the test (in order)
cf95b4f0 7636 current.u=branch_unneeded_reg[i-1]&~((1LL<<dops[i].rs1)|(1LL<<dops[i].rs2));
57871462 7637 current.u|=1;
57871462 7638 delayslot_alloc(&current,i);
7639 current.isconst=0;
7640 }
7641 else
7642 {
cf95b4f0 7643 current.u=branch_unneeded_reg[i-1]&~(1LL<<dops[i-1].rs1);
57871462 7644 // Alloc the branch condition register
cf95b4f0 7645 alloc_reg(&current,i-1,dops[i-1].rs1);
57871462 7646 }
7647 memcpy(&branch_regs[i-1],&current,sizeof(current));
7648 branch_regs[i-1].isconst=0;
7649 branch_regs[i-1].wasconst=0;
7650 memcpy(&branch_regs[i-1].regmap_entry,&current.regmap,sizeof(current.regmap));
40fca85b 7651 memcpy(constmap[i],constmap[i-1],sizeof(constmap[i]));
57871462 7652 }
7653 else
7654 // Alloc the delay slot in case the branch is taken
cf95b4f0 7655 if((dops[i-1].opcode&0x3E)==0x14) // BEQL/BNEL
57871462 7656 {
7657 memcpy(&branch_regs[i-1],&current,sizeof(current));
cf95b4f0 7658 branch_regs[i-1].u=(branch_unneeded_reg[i-1]&~((1LL<<dops[i].rs1)|(1LL<<dops[i].rs2)|(1LL<<dops[i].rt1)|(1LL<<dops[i].rt2)))|1;
57871462 7659 alloc_cc(&branch_regs[i-1],i);
7660 dirty_reg(&branch_regs[i-1],CCREG);
7661 delayslot_alloc(&branch_regs[i-1],i);
7662 branch_regs[i-1].isconst=0;
7663 alloc_reg(&current,i,CCREG); // Not taken path
7664 dirty_reg(&current,CCREG);
7665 memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
7666 }
7667 else
cf95b4f0 7668 if((dops[i-1].opcode&0x3E)==0x16) // BLEZL/BGTZL
57871462 7669 {
7670 memcpy(&branch_regs[i-1],&current,sizeof(current));
cf95b4f0 7671 branch_regs[i-1].u=(branch_unneeded_reg[i-1]&~((1LL<<dops[i].rs1)|(1LL<<dops[i].rs2)|(1LL<<dops[i].rt1)|(1LL<<dops[i].rt2)))|1;
57871462 7672 alloc_cc(&branch_regs[i-1],i);
7673 dirty_reg(&branch_regs[i-1],CCREG);
7674 delayslot_alloc(&branch_regs[i-1],i);
7675 branch_regs[i-1].isconst=0;
7676 alloc_reg(&current,i,CCREG); // Not taken path
7677 dirty_reg(&current,CCREG);
7678 memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
7679 }
7680 break;
7681 case SJUMP:
cf95b4f0 7682 //if((dops[i-1].opcode2&0x1E)==0) // BLTZ/BGEZ
7683 if((dops[i-1].opcode2&0x0E)==0) // BLTZ/BGEZ
57871462 7684 {
7685 alloc_cc(&current,i-1);
7686 dirty_reg(&current,CCREG);
cf95b4f0 7687 if(dops[i-1].rs1==dops[i].rt1||dops[i-1].rs1==dops[i].rt2) {
57871462 7688 // The delay slot overwrote the branch condition
7689 // Delay slot goes after the test (in order)
cf95b4f0 7690 current.u=branch_unneeded_reg[i-1]&~((1LL<<dops[i].rs1)|(1LL<<dops[i].rs2));
57871462 7691 current.u|=1;
57871462 7692 delayslot_alloc(&current,i);
7693 current.isconst=0;
7694 }
7695 else
7696 {
cf95b4f0 7697 current.u=branch_unneeded_reg[i-1]&~(1LL<<dops[i-1].rs1);
57871462 7698 // Alloc the branch condition register
cf95b4f0 7699 alloc_reg(&current,i-1,dops[i-1].rs1);
57871462 7700 }
7701 memcpy(&branch_regs[i-1],&current,sizeof(current));
7702 branch_regs[i-1].isconst=0;
7703 branch_regs[i-1].wasconst=0;
7704 memcpy(&branch_regs[i-1].regmap_entry,&current.regmap,sizeof(current.regmap));
40fca85b 7705 memcpy(constmap[i],constmap[i-1],sizeof(constmap[i]));
57871462 7706 }
7707 else
7708 // Alloc the delay slot in case the branch is taken
cf95b4f0 7709 if((dops[i-1].opcode2&0x1E)==2) // BLTZL/BGEZL
57871462 7710 {
7711 memcpy(&branch_regs[i-1],&current,sizeof(current));
cf95b4f0 7712 branch_regs[i-1].u=(branch_unneeded_reg[i-1]&~((1LL<<dops[i].rs1)|(1LL<<dops[i].rs2)|(1LL<<dops[i].rt1)|(1LL<<dops[i].rt2)))|1;
57871462 7713 alloc_cc(&branch_regs[i-1],i);
7714 dirty_reg(&branch_regs[i-1],CCREG);
7715 delayslot_alloc(&branch_regs[i-1],i);
7716 branch_regs[i-1].isconst=0;
7717 alloc_reg(&current,i,CCREG); // Not taken path
7718 dirty_reg(&current,CCREG);
7719 memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
7720 }
7721 // FIXME: BLTZAL/BGEZAL
cf95b4f0 7722 if(dops[i-1].opcode2&0x10) { // BxxZAL
57871462 7723 alloc_reg(&branch_regs[i-1],i-1,31);
7724 dirty_reg(&branch_regs[i-1],31);
57871462 7725 }
7726 break;
57871462 7727 }
7728
fe807a8a 7729 if (dops[i-1].is_ujump)
57871462 7730 {
cf95b4f0 7731 if(dops[i-1].rt1==31) // JAL/JALR
57871462 7732 {
7733 // Subroutine call will return here, don't alloc any registers
57871462 7734 current.dirty=0;
7735 clear_all_regs(current.regmap);
7736 alloc_reg(&current,i,CCREG);
7737 dirty_reg(&current,CCREG);
7738 }
7739 else if(i+1<slen)
7740 {
7741 // Internal branch will jump here, match registers to caller
57871462 7742 current.dirty=0;
7743 clear_all_regs(current.regmap);
7744 alloc_reg(&current,i,CCREG);
7745 dirty_reg(&current,CCREG);
7746 for(j=i-1;j>=0;j--)
7747 {
7748 if(ba[j]==start+i*4+4) {
7749 memcpy(current.regmap,branch_regs[j].regmap,sizeof(current.regmap));
57871462 7750 current.dirty=branch_regs[j].dirty;
7751 break;
7752 }
7753 }
7754 while(j>=0) {
7755 if(ba[j]==start+i*4+4) {
7756 for(hr=0;hr<HOST_REGS;hr++) {
7757 if(current.regmap[hr]!=branch_regs[j].regmap[hr]) {
7758 current.regmap[hr]=-1;
7759 }
57871462 7760 current.dirty&=branch_regs[j].dirty;
7761 }
7762 }
7763 j--;
7764 }
7765 }
7766 }
7767 }
7768
7769 // Count cycles in between branches
2330734f 7770 ccadj[i] = CLOCK_ADJUST(cc);
fe807a8a 7771 if (i > 0 && (dops[i-1].is_jump || dops[i].itype == SYSCALL || dops[i].itype == HLECALL))
57871462 7772 {
7773 cc=0;
7774 }
71e490c5 7775#if !defined(DRC_DBG)
cf95b4f0 7776 else if(dops[i].itype==C2OP&&gte_cycletab[source[i]&0x3f]>2)
054175e9 7777 {
81dbbf4c 7778 // this should really be removed since the real stalls have been implemented,
7779 // but doing so causes sizeable perf regression against the older version
7780 u_int gtec = gte_cycletab[source[i] & 0x3f];
32631e6a 7781 cc += HACK_ENABLED(NDHACK_NO_STALLS) ? gtec/2 : 2;
fb407447 7782 }
cf95b4f0 7783 else if(i>1&&dops[i].itype==STORE&&dops[i-1].itype==STORE&&dops[i-2].itype==STORE&&!dops[i].bt)
5fdcbb5a 7784 {
7785 cc+=4;
7786 }
cf95b4f0 7787 else if(dops[i].itype==C2LS)
fb407447 7788 {
81dbbf4c 7789 // same as with C2OP
32631e6a 7790 cc += HACK_ENABLED(NDHACK_NO_STALLS) ? 4 : 2;
fb407447 7791 }
7792#endif
57871462 7793 else
7794 {
7795 cc++;
7796 }
7797
cf95b4f0 7798 if(!dops[i].is_ds) {
57871462 7799 regs[i].dirty=current.dirty;
7800 regs[i].isconst=current.isconst;
40fca85b 7801 memcpy(constmap[i],current_constmap,sizeof(constmap[i]));
57871462 7802 }
7803 for(hr=0;hr<HOST_REGS;hr++) {
7804 if(hr!=EXCLUDE_REG&&regs[i].regmap[hr]>=0) {
7805 if(regmap_pre[i][hr]!=regs[i].regmap[hr]) {
7806 regs[i].wasconst&=~(1<<hr);
7807 }
7808 }
7809 }
7810 if(current.regmap[HOST_BTREG]==BTREG) current.regmap[HOST_BTREG]=-1;
27727b63 7811 regs[i].waswritten=current.waswritten;
57871462 7812 }
4149788d 7813}
9f51b4b9 7814
4149788d 7815static noinline void pass4_cull_unused_regs(void)
7816{
53358c1d 7817 u_int last_needed_regs[4] = {0,0,0,0};
4149788d 7818 u_int nr=0;
7819 int i;
9f51b4b9 7820
57871462 7821 for (i=slen-1;i>=0;i--)
7822 {
7823 int hr;
53358c1d 7824 __builtin_prefetch(regs[i-2].regmap);
fe807a8a 7825 if(dops[i].is_jump)
57871462 7826 {
7827 if(ba[i]<start || ba[i]>=(start+slen*4))
7828 {
7829 // Branch out of this block, don't need anything
7830 nr=0;
7831 }
7832 else
7833 {
7834 // Internal branch
7835 // Need whatever matches the target
7836 nr=0;
7837 int t=(ba[i]-start)>>2;
7838 for(hr=0;hr<HOST_REGS;hr++)
7839 {
7840 if(regs[i].regmap_entry[hr]>=0) {
7841 if(regs[i].regmap_entry[hr]==regs[t].regmap_entry[hr]) nr|=1<<hr;
7842 }
7843 }
7844 }
7845 // Conditional branch may need registers for following instructions
fe807a8a 7846 if (!dops[i].is_ujump)
57871462 7847 {
7848 if(i<slen-2) {
53358c1d 7849 nr |= last_needed_regs[(i+2) & 3];
57871462 7850 for(hr=0;hr<HOST_REGS;hr++)
7851 {
7852 if(regmap_pre[i+2][hr]>=0&&get_reg(regs[i+2].regmap_entry,regmap_pre[i+2][hr])<0) nr&=~(1<<hr);
7853 //if((regmap_entry[i+2][hr])>=0) if(!((nr>>hr)&1)) printf("%x-bogus(%d=%d)\n",start+i*4,hr,regmap_entry[i+2][hr]);
7854 }
7855 }
7856 }
7857 // Don't need stuff which is overwritten
f5955059 7858 //if(regs[i].regmap[hr]!=regmap_pre[i][hr]) nr&=~(1<<hr);
7859 //if(regs[i].regmap[hr]<0) nr&=~(1<<hr);
57871462 7860 // Merge in delay slot
53358c1d 7861 if (dops[i+1].rt1) nr &= ~get_regm(regs[i].regmap, dops[i+1].rt1);
7862 if (dops[i+1].rt2) nr &= ~get_regm(regs[i].regmap, dops[i+1].rt2);
7863 nr |= get_regm(regmap_pre[i], dops[i+1].rs1);
7864 nr |= get_regm(regmap_pre[i], dops[i+1].rs2);
7865 nr |= get_regm(regs[i].regmap_entry, dops[i+1].rs1);
7866 nr |= get_regm(regs[i].regmap_entry, dops[i+1].rs2);
7867 if (ram_offset && (dops[i+1].is_load || dops[i+1].is_store)) {
7868 nr |= get_regm(regmap_pre[i], ROREG);
7869 nr |= get_regm(regs[i].regmap_entry, ROREG);
7870 }
7871 if (dops[i+1].is_store) {
7872 nr |= get_regm(regmap_pre[i], INVCP);
7873 nr |= get_regm(regs[i].regmap_entry, INVCP);
57871462 7874 }
7875 }
cf95b4f0 7876 else if(dops[i].itype==SYSCALL||dops[i].itype==HLECALL||dops[i].itype==INTCALL)
57871462 7877 {
7878 // SYSCALL instruction (software interrupt)
7879 nr=0;
7880 }
cf95b4f0 7881 else if(dops[i].itype==COP0 && (source[i]&0x3f)==0x18)
57871462 7882 {
7883 // ERET instruction (return from interrupt)
7884 nr=0;
7885 }
7886 else // Non-branch
7887 {
7888 if(i<slen-1) {
7889 for(hr=0;hr<HOST_REGS;hr++) {
7890 if(regmap_pre[i+1][hr]>=0&&get_reg(regs[i+1].regmap_entry,regmap_pre[i+1][hr])<0) nr&=~(1<<hr);
7891 if(regs[i].regmap[hr]!=regmap_pre[i+1][hr]) nr&=~(1<<hr);
7892 if(regs[i].regmap[hr]!=regmap_pre[i][hr]) nr&=~(1<<hr);
7893 if(regs[i].regmap[hr]<0) nr&=~(1<<hr);
7894 }
7895 }
7896 }
53358c1d 7897 // Overwritten registers are not needed
7898 if (dops[i].rt1) nr &= ~get_regm(regs[i].regmap, dops[i].rt1);
7899 if (dops[i].rt2) nr &= ~get_regm(regs[i].regmap, dops[i].rt2);
7900 nr &= ~get_regm(regs[i].regmap, FTEMP);
7901 // Source registers are needed
7902 nr |= get_regm(regmap_pre[i], dops[i].rs1);
7903 nr |= get_regm(regmap_pre[i], dops[i].rs2);
7904 nr |= get_regm(regs[i].regmap_entry, dops[i].rs1);
7905 nr |= get_regm(regs[i].regmap_entry, dops[i].rs2);
7906 if (ram_offset && (dops[i].is_load || dops[i].is_store)) {
7907 nr |= get_regm(regmap_pre[i], ROREG);
7908 nr |= get_regm(regs[i].regmap_entry, ROREG);
7909 }
7910 if (dops[i].is_store) {
7911 nr |= get_regm(regmap_pre[i], INVCP);
7912 nr |= get_regm(regs[i].regmap_entry, INVCP);
7913 }
7914
7915 if (i > 0 && !dops[i].bt && regs[i].wasdirty)
57871462 7916 for(hr=0;hr<HOST_REGS;hr++)
7917 {
57871462 7918 // Don't store a register immediately after writing it,
7919 // may prevent dual-issue.
7920 // But do so if this is a branch target, otherwise we
7921 // might have to load the register before the branch.
53358c1d 7922 if((regs[i].wasdirty>>hr)&1) {
7c3a5182 7923 if((regmap_pre[i][hr]>0&&!((unneeded_reg[i]>>regmap_pre[i][hr])&1))) {
9de8a0c3 7924 if(dops[i-1].rt1==regmap_pre[i][hr]) nr|=1<<hr;
7925 if(dops[i-1].rt2==regmap_pre[i][hr]) nr|=1<<hr;
57871462 7926 }
7c3a5182 7927 if((regs[i].regmap_entry[hr]>0&&!((unneeded_reg[i]>>regs[i].regmap_entry[hr])&1))) {
9de8a0c3 7928 if(dops[i-1].rt1==regs[i].regmap_entry[hr]) nr|=1<<hr;
7929 if(dops[i-1].rt2==regs[i].regmap_entry[hr]) nr|=1<<hr;
57871462 7930 }
7931 }
7932 }
7933 // Cycle count is needed at branches. Assume it is needed at the target too.
4bdc30ab 7934 if(i==0||dops[i].bt||dops[i].itype==CJUMP) {
57871462 7935 if(regmap_pre[i][HOST_CCREG]==CCREG) nr|=1<<HOST_CCREG;
7936 if(regs[i].regmap_entry[HOST_CCREG]==CCREG) nr|=1<<HOST_CCREG;
7937 }
7938 // Save it
53358c1d 7939 last_needed_regs[i & 3] = nr;
9f51b4b9 7940
57871462 7941 // Deallocate unneeded registers
7942 for(hr=0;hr<HOST_REGS;hr++)
7943 {
7944 if(!((nr>>hr)&1)) {
7945 if(regs[i].regmap_entry[hr]!=CCREG) regs[i].regmap_entry[hr]=-1;
fe807a8a 7946 if(dops[i].is_jump)
57871462 7947 {
37387d8b 7948 int map1 = 0, map2 = 0, temp = 0; // or -1 ??
7949 if (dops[i+1].is_load || dops[i+1].is_store)
7950 map1 = ROREG;
7951 if (dops[i+1].is_store)
7952 map2 = INVCP;
7953 if(dops[i+1].itype==LOADLR || dops[i+1].itype==STORELR || dops[i+1].itype==C2LS)
7954 temp = FTEMP;
9de8a0c3 7955 if(regs[i].regmap[hr]!=dops[i].rs1 && regs[i].regmap[hr]!=dops[i].rs2 &&
7956 regs[i].regmap[hr]!=dops[i].rt1 && regs[i].regmap[hr]!=dops[i].rt2 &&
7957 regs[i].regmap[hr]!=dops[i+1].rt1 && regs[i].regmap[hr]!=dops[i+1].rt2 &&
cf95b4f0 7958 regs[i].regmap[hr]!=dops[i+1].rs1 && regs[i].regmap[hr]!=dops[i+1].rs2 &&
9de8a0c3 7959 regs[i].regmap[hr]!=temp && regs[i].regmap[hr]!=PTEMP &&
57871462 7960 regs[i].regmap[hr]!=RHASH && regs[i].regmap[hr]!=RHTBL &&
7961 regs[i].regmap[hr]!=RTEMP && regs[i].regmap[hr]!=CCREG &&
37387d8b 7962 regs[i].regmap[hr]!=map1 && regs[i].regmap[hr]!=map2)
57871462 7963 {
7964 regs[i].regmap[hr]=-1;
7965 regs[i].isconst&=~(1<<hr);
a550c61c 7966 regs[i].dirty&=~(1<<hr);
7967 regs[i+1].wasdirty&=~(1<<hr);
9de8a0c3 7968 if(branch_regs[i].regmap[hr]!=dops[i].rs1 && branch_regs[i].regmap[hr]!=dops[i].rs2 &&
7969 branch_regs[i].regmap[hr]!=dops[i].rt1 && branch_regs[i].regmap[hr]!=dops[i].rt2 &&
7970 branch_regs[i].regmap[hr]!=dops[i+1].rt1 && branch_regs[i].regmap[hr]!=dops[i+1].rt2 &&
cf95b4f0 7971 branch_regs[i].regmap[hr]!=dops[i+1].rs1 && branch_regs[i].regmap[hr]!=dops[i+1].rs2 &&
9de8a0c3 7972 branch_regs[i].regmap[hr]!=temp && branch_regs[i].regmap[hr]!=PTEMP &&
57871462 7973 branch_regs[i].regmap[hr]!=RHASH && branch_regs[i].regmap[hr]!=RHTBL &&
7974 branch_regs[i].regmap[hr]!=RTEMP && branch_regs[i].regmap[hr]!=CCREG &&
37387d8b 7975 branch_regs[i].regmap[hr]!=map1 && branch_regs[i].regmap[hr]!=map2)
57871462 7976 {
7977 branch_regs[i].regmap[hr]=-1;
7978 branch_regs[i].regmap_entry[hr]=-1;
fe807a8a 7979 if (!dops[i].is_ujump)
57871462 7980 {
fe807a8a 7981 if (i < slen-2) {
57871462 7982 regmap_pre[i+2][hr]=-1;
79c75f1b 7983 regs[i+2].wasconst&=~(1<<hr);
57871462 7984 }
7985 }
7986 }
7987 }
7988 }
7989 else
7990 {
7991 // Non-branch
7992 if(i>0)
7993 {
37387d8b 7994 int map1 = -1, map2 = -1, temp=-1;
7995 if (dops[i].is_load || dops[i].is_store)
7996 map1 = ROREG;
7997 if (dops[i].is_store)
7998 map2 = INVCP;
7999 if (dops[i].itype==LOADLR || dops[i].itype==STORELR || dops[i].itype==C2LS)
8000 temp = FTEMP;
9de8a0c3 8001 if(regs[i].regmap[hr]!=dops[i].rt1 && regs[i].regmap[hr]!=dops[i].rt2 &&
cf95b4f0 8002 regs[i].regmap[hr]!=dops[i].rs1 && regs[i].regmap[hr]!=dops[i].rs2 &&
9de8a0c3 8003 regs[i].regmap[hr]!=temp && regs[i].regmap[hr]!=map1 && regs[i].regmap[hr]!=map2 &&
4b1c7cd1 8004 //(dops[i].itype!=SPAN||regs[i].regmap[hr]!=CCREG)
8005 regs[i].regmap[hr] != CCREG)
57871462 8006 {
cf95b4f0 8007 if(i<slen-1&&!dops[i].is_ds) {
ad49de89 8008 assert(regs[i].regmap[hr]<64);
afec9d44 8009 if(regmap_pre[i+1][hr]!=-1 || regs[i].regmap[hr]>0)
57871462 8010 if(regmap_pre[i+1][hr]!=regs[i].regmap[hr])
57871462 8011 {
c43b5311 8012 SysPrintf("fail: %x (%d %d!=%d)\n",start+i*4,hr,regmap_pre[i+1][hr],regs[i].regmap[hr]);
57871462 8013 assert(regmap_pre[i+1][hr]==regs[i].regmap[hr]);
8014 }
8015 regmap_pre[i+1][hr]=-1;
8016 if(regs[i+1].regmap_entry[hr]==CCREG) regs[i+1].regmap_entry[hr]=-1;
79c75f1b 8017 regs[i+1].wasconst&=~(1<<hr);
57871462 8018 }
8019 regs[i].regmap[hr]=-1;
8020 regs[i].isconst&=~(1<<hr);
a550c61c 8021 regs[i].dirty&=~(1<<hr);
8022 regs[i+1].wasdirty&=~(1<<hr);
57871462 8023 }
8024 }
8025 }
3968e69e 8026 } // if needed
8027 } // for hr
57871462 8028 }
4149788d 8029}
9f51b4b9 8030
4149788d 8031// If a register is allocated during a loop, try to allocate it for the
8032// entire loop, if possible. This avoids loading/storing registers
8033// inside of the loop.
8034static noinline void pass5a_preallocate1(void)
8035{
8036 int i, j, hr;
57871462 8037 signed char f_regmap[HOST_REGS];
8038 clear_all_regs(f_regmap);
8039 for(i=0;i<slen-1;i++)
8040 {
cf95b4f0 8041 if(dops[i].itype==UJUMP||dops[i].itype==CJUMP||dops[i].itype==SJUMP)
57871462 8042 {
9f51b4b9 8043 if(ba[i]>=start && ba[i]<(start+i*4))
cf95b4f0 8044 if(dops[i+1].itype==NOP||dops[i+1].itype==MOV||dops[i+1].itype==ALU
8045 ||dops[i+1].itype==SHIFTIMM||dops[i+1].itype==IMM16||dops[i+1].itype==LOAD
8046 ||dops[i+1].itype==STORE||dops[i+1].itype==STORELR||dops[i+1].itype==C1LS
8047 ||dops[i+1].itype==SHIFT||dops[i+1].itype==COP1
8048 ||dops[i+1].itype==COP2||dops[i+1].itype==C2LS||dops[i+1].itype==C2OP)
57871462 8049 {
8050 int t=(ba[i]-start)>>2;
fe807a8a 8051 if(t > 0 && !dops[t-1].is_jump) // loop_preload can't handle jumps into delay slots
cf95b4f0 8052 if(t<2||(dops[t-2].itype!=UJUMP&&dops[t-2].itype!=RJUMP)||dops[t-2].rt1!=31) // call/ret assumes no registers allocated
57871462 8053 for(hr=0;hr<HOST_REGS;hr++)
8054 {
7c3a5182 8055 if(regs[i].regmap[hr]>=0) {
b372a952 8056 if(f_regmap[hr]!=regs[i].regmap[hr]) {
8057 // dealloc old register
8058 int n;
8059 for(n=0;n<HOST_REGS;n++)
8060 {
8061 if(f_regmap[n]==regs[i].regmap[hr]) {f_regmap[n]=-1;}
8062 }
8063 // and alloc new one
8064 f_regmap[hr]=regs[i].regmap[hr];
8065 }
8066 }
7c3a5182 8067 if(branch_regs[i].regmap[hr]>=0) {
b372a952 8068 if(f_regmap[hr]!=branch_regs[i].regmap[hr]) {
8069 // dealloc old register
8070 int n;
8071 for(n=0;n<HOST_REGS;n++)
8072 {
8073 if(f_regmap[n]==branch_regs[i].regmap[hr]) {f_regmap[n]=-1;}
8074 }
8075 // and alloc new one
8076 f_regmap[hr]=branch_regs[i].regmap[hr];
8077 }
8078 }
cf95b4f0 8079 if(dops[i].ooo) {
9f51b4b9 8080 if(count_free_regs(regs[i].regmap)<=minimum_free_regs[i+1])
e1190b87 8081 f_regmap[hr]=branch_regs[i].regmap[hr];
8082 }else{
9f51b4b9 8083 if(count_free_regs(branch_regs[i].regmap)<=minimum_free_regs[i+1])
57871462 8084 f_regmap[hr]=branch_regs[i].regmap[hr];
8085 }
8086 // Avoid dirty->clean transition
e1190b87 8087 #ifdef DESTRUCTIVE_WRITEBACK
57871462 8088 if(t>0) if(get_reg(regmap_pre[t],f_regmap[hr])>=0) if((regs[t].wasdirty>>get_reg(regmap_pre[t],f_regmap[hr]))&1) f_regmap[hr]=-1;
e1190b87 8089 #endif
8090 // This check is only strictly required in the DESTRUCTIVE_WRITEBACK
8091 // case above, however it's always a good idea. We can't hoist the
8092 // load if the register was already allocated, so there's no point
8093 // wasting time analyzing most of these cases. It only "succeeds"
8094 // when the mapping was different and the load can be replaced with
8095 // a mov, which is of negligible benefit. So such cases are
8096 // skipped below.
57871462 8097 if(f_regmap[hr]>0) {
198df76f 8098 if(regs[t].regmap[hr]==f_regmap[hr]||(regs[t].regmap_entry[hr]<0&&get_reg(regmap_pre[t],f_regmap[hr])<0)) {
57871462 8099 int r=f_regmap[hr];
8100 for(j=t;j<=i;j++)
8101 {
8102 //printf("Test %x -> %x, %x %d/%d\n",start+i*4,ba[i],start+j*4,hr,r);
8103 if(r<34&&((unneeded_reg[j]>>r)&1)) break;
00fa9369 8104 assert(r < 64);
9de8a0c3 8105 if(regs[j].regmap[hr]==f_regmap[hr]&&f_regmap[hr]<TEMPREG) {
57871462 8106 //printf("Hit %x -> %x, %x %d/%d\n",start+i*4,ba[i],start+j*4,hr,r);
8107 int k;
8108 if(regs[i].regmap[hr]==-1&&branch_regs[i].regmap[hr]==-1) {
670c0f22 8109 if(get_reg(regs[i].regmap,f_regmap[hr])>=0) break;
57871462 8110 if(get_reg(regs[i+2].regmap,f_regmap[hr])>=0) break;
57871462 8111 k=i;
8112 while(k>1&&regs[k-1].regmap[hr]==-1) {
e1190b87 8113 if(count_free_regs(regs[k-1].regmap)<=minimum_free_regs[k-1]) {
8114 //printf("no free regs for store %x\n",start+(k-1)*4);
8115 break;
57871462 8116 }
57871462 8117 if(get_reg(regs[k-1].regmap,f_regmap[hr])>=0) {
8118 //printf("no-match due to different register\n");
8119 break;
8120 }
fe807a8a 8121 if (dops[k-2].is_jump) {
57871462 8122 //printf("no-match due to branch\n");
8123 break;
8124 }
8125 // call/ret fast path assumes no registers allocated
cf95b4f0 8126 if(k>2&&(dops[k-3].itype==UJUMP||dops[k-3].itype==RJUMP)&&dops[k-3].rt1==31) {
57871462 8127 break;
8128 }
57871462 8129 k--;
8130 }
57871462 8131 if(regs[k-1].regmap[hr]==f_regmap[hr]&&regmap_pre[k][hr]==f_regmap[hr]) {
8132 //printf("Extend r%d, %x ->\n",hr,start+k*4);
8133 while(k<i) {
8134 regs[k].regmap_entry[hr]=f_regmap[hr];
8135 regs[k].regmap[hr]=f_regmap[hr];
8136 regmap_pre[k+1][hr]=f_regmap[hr];
8137 regs[k].wasdirty&=~(1<<hr);
8138 regs[k].dirty&=~(1<<hr);
8139 regs[k].wasdirty|=(1<<hr)&regs[k-1].dirty;
8140 regs[k].dirty|=(1<<hr)&regs[k].wasdirty;
8141 regs[k].wasconst&=~(1<<hr);
8142 regs[k].isconst&=~(1<<hr);
8143 k++;
8144 }
8145 }
8146 else {
8147 //printf("Fail Extend r%d, %x ->\n",hr,start+k*4);
8148 break;
8149 }
8150 assert(regs[i-1].regmap[hr]==f_regmap[hr]);
8151 if(regs[i-1].regmap[hr]==f_regmap[hr]&&regmap_pre[i][hr]==f_regmap[hr]) {
8152 //printf("OK fill %x (r%d)\n",start+i*4,hr);
8153 regs[i].regmap_entry[hr]=f_regmap[hr];
8154 regs[i].regmap[hr]=f_regmap[hr];
8155 regs[i].wasdirty&=~(1<<hr);
8156 regs[i].dirty&=~(1<<hr);
8157 regs[i].wasdirty|=(1<<hr)&regs[i-1].dirty;
8158 regs[i].dirty|=(1<<hr)&regs[i-1].dirty;
8159 regs[i].wasconst&=~(1<<hr);
8160 regs[i].isconst&=~(1<<hr);
8161 branch_regs[i].regmap_entry[hr]=f_regmap[hr];
8162 branch_regs[i].wasdirty&=~(1<<hr);
8163 branch_regs[i].wasdirty|=(1<<hr)&regs[i].dirty;
8164 branch_regs[i].regmap[hr]=f_regmap[hr];
8165 branch_regs[i].dirty&=~(1<<hr);
8166 branch_regs[i].dirty|=(1<<hr)&regs[i].dirty;
8167 branch_regs[i].wasconst&=~(1<<hr);
8168 branch_regs[i].isconst&=~(1<<hr);
fe807a8a 8169 if (!dops[i].is_ujump) {
57871462 8170 regmap_pre[i+2][hr]=f_regmap[hr];
8171 regs[i+2].wasdirty&=~(1<<hr);
8172 regs[i+2].wasdirty|=(1<<hr)&regs[i].dirty;
57871462 8173 }
8174 }
8175 }
8176 for(k=t;k<j;k++) {
e1190b87 8177 // Alloc register clean at beginning of loop,
8178 // but may dirty it in pass 6
57871462 8179 regs[k].regmap_entry[hr]=f_regmap[hr];
8180 regs[k].regmap[hr]=f_regmap[hr];
57871462 8181 regs[k].dirty&=~(1<<hr);
8182 regs[k].wasconst&=~(1<<hr);
8183 regs[k].isconst&=~(1<<hr);
fe807a8a 8184 if (dops[k].is_jump) {
e1190b87 8185 branch_regs[k].regmap_entry[hr]=f_regmap[hr];
8186 branch_regs[k].regmap[hr]=f_regmap[hr];
8187 branch_regs[k].dirty&=~(1<<hr);
8188 branch_regs[k].wasconst&=~(1<<hr);
8189 branch_regs[k].isconst&=~(1<<hr);
fe807a8a 8190 if (!dops[k].is_ujump) {
e1190b87 8191 regmap_pre[k+2][hr]=f_regmap[hr];
8192 regs[k+2].wasdirty&=~(1<<hr);
e1190b87 8193 }
8194 }
8195 else
8196 {
8197 regmap_pre[k+1][hr]=f_regmap[hr];
8198 regs[k+1].wasdirty&=~(1<<hr);
8199 }
57871462 8200 }
8201 if(regs[j].regmap[hr]==f_regmap[hr])
8202 regs[j].regmap_entry[hr]=f_regmap[hr];
8203 break;
8204 }
8205 if(j==i) break;
8206 if(regs[j].regmap[hr]>=0)
8207 break;
8208 if(get_reg(regs[j].regmap,f_regmap[hr])>=0) {
8209 //printf("no-match due to different register\n");
8210 break;
8211 }
fe807a8a 8212 if (dops[j].is_ujump)
e1190b87 8213 {
8214 // Stop on unconditional branch
8215 break;
8216 }
cf95b4f0 8217 if(dops[j].itype==CJUMP||dops[j].itype==SJUMP)
e1190b87 8218 {
cf95b4f0 8219 if(dops[j].ooo) {
9f51b4b9 8220 if(count_free_regs(regs[j].regmap)<=minimum_free_regs[j+1])
e1190b87 8221 break;
8222 }else{
9f51b4b9 8223 if(count_free_regs(branch_regs[j].regmap)<=minimum_free_regs[j+1])
e1190b87 8224 break;
8225 }
8226 if(get_reg(branch_regs[j].regmap,f_regmap[hr])>=0) {
8227 //printf("no-match due to different register (branch)\n");
57871462 8228 break;
8229 }
8230 }
e1190b87 8231 if(count_free_regs(regs[j].regmap)<=minimum_free_regs[j]) {
8232 //printf("No free regs for store %x\n",start+j*4);
8233 break;
8234 }
ad49de89 8235 assert(f_regmap[hr]<64);
57871462 8236 }
8237 }
8238 }
8239 }
8240 }
8241 }else{
198df76f 8242 // Non branch or undetermined branch target
57871462 8243 for(hr=0;hr<HOST_REGS;hr++)
8244 {
8245 if(hr!=EXCLUDE_REG) {
7c3a5182 8246 if(regs[i].regmap[hr]>=0) {
b372a952 8247 if(f_regmap[hr]!=regs[i].regmap[hr]) {
8248 // dealloc old register
8249 int n;
8250 for(n=0;n<HOST_REGS;n++)
8251 {
8252 if(f_regmap[n]==regs[i].regmap[hr]) {f_regmap[n]=-1;}
8253 }
4149788d 8254 // and alloc new one
8255 f_regmap[hr]=regs[i].regmap[hr];
8256 }
8257 }
8258 }
8259 }
8260 // Try to restore cycle count at branch targets
8261 if(dops[i].bt) {
8262 for(j=i;j<slen-1;j++) {
8263 if(regs[j].regmap[HOST_CCREG]!=-1) break;
8264 if(count_free_regs(regs[j].regmap)<=minimum_free_regs[j]) {
8265 //printf("no free regs for store %x\n",start+j*4);
8266 break;
8267 }
8268 }
8269 if(regs[j].regmap[HOST_CCREG]==CCREG) {
8270 int k=i;
8271 //printf("Extend CC, %x -> %x\n",start+k*4,start+j*4);
8272 while(k<j) {
8273 regs[k].regmap_entry[HOST_CCREG]=CCREG;
8274 regs[k].regmap[HOST_CCREG]=CCREG;
8275 regmap_pre[k+1][HOST_CCREG]=CCREG;
8276 regs[k+1].wasdirty|=1<<HOST_CCREG;
8277 regs[k].dirty|=1<<HOST_CCREG;
8278 regs[k].wasconst&=~(1<<HOST_CCREG);
8279 regs[k].isconst&=~(1<<HOST_CCREG);
8280 k++;
8281 }
8282 regs[j].regmap_entry[HOST_CCREG]=CCREG;
8283 }
8284 // Work backwards from the branch target
8285 if(j>i&&f_regmap[HOST_CCREG]==CCREG)
8286 {
8287 //printf("Extend backwards\n");
8288 int k;
8289 k=i;
8290 while(regs[k-1].regmap[HOST_CCREG]==-1) {
8291 if(count_free_regs(regs[k-1].regmap)<=minimum_free_regs[k-1]) {
8292 //printf("no free regs for store %x\n",start+(k-1)*4);
8293 break;
8294 }
8295 k--;
8296 }
8297 if(regs[k-1].regmap[HOST_CCREG]==CCREG) {
8298 //printf("Extend CC, %x ->\n",start+k*4);
8299 while(k<=i) {
8300 regs[k].regmap_entry[HOST_CCREG]=CCREG;
8301 regs[k].regmap[HOST_CCREG]=CCREG;
8302 regmap_pre[k+1][HOST_CCREG]=CCREG;
8303 regs[k+1].wasdirty|=1<<HOST_CCREG;
8304 regs[k].dirty|=1<<HOST_CCREG;
8305 regs[k].wasconst&=~(1<<HOST_CCREG);
8306 regs[k].isconst&=~(1<<HOST_CCREG);
8307 k++;
8308 }
8309 }
8310 else {
8311 //printf("Fail Extend CC, %x ->\n",start+k*4);
8312 }
8313 }
8314 }
8315 if(dops[i].itype!=STORE&&dops[i].itype!=STORELR&&dops[i].itype!=C1LS&&dops[i].itype!=SHIFT&&
8316 dops[i].itype!=NOP&&dops[i].itype!=MOV&&dops[i].itype!=ALU&&dops[i].itype!=SHIFTIMM&&
8317 dops[i].itype!=IMM16&&dops[i].itype!=LOAD&&dops[i].itype!=COP1)
8318 {
8319 memcpy(f_regmap,regs[i].regmap,sizeof(f_regmap));
8320 }
8321 }
8322 }
8323}
8324
8325// This allocates registers (if possible) one instruction prior
8326// to use, which can avoid a load-use penalty on certain CPUs.
8327static noinline void pass5b_preallocate2(void)
8328{
8329 int i, hr;
8330 for(i=0;i<slen-1;i++)
8331 {
8332 if (!i || !dops[i-1].is_jump)
8333 {
8334 if(!dops[i+1].bt)
8335 {
8336 if(dops[i].itype==ALU||dops[i].itype==MOV||dops[i].itype==LOAD||dops[i].itype==SHIFTIMM||dops[i].itype==IMM16
8337 ||((dops[i].itype==COP1||dops[i].itype==COP2)&&dops[i].opcode2<3))
8338 {
8339 if(dops[i+1].rs1) {
8340 if((hr=get_reg(regs[i+1].regmap,dops[i+1].rs1))>=0)
8341 {
8342 if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
8343 {
8344 regs[i].regmap[hr]=regs[i+1].regmap[hr];
8345 regmap_pre[i+1][hr]=regs[i+1].regmap[hr];
8346 regs[i+1].regmap_entry[hr]=regs[i+1].regmap[hr];
8347 regs[i].isconst&=~(1<<hr);
8348 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
8349 constmap[i][hr]=constmap[i+1][hr];
8350 regs[i+1].wasdirty&=~(1<<hr);
8351 regs[i].dirty&=~(1<<hr);
8352 }
8353 }
8354 }
8355 if(dops[i+1].rs2) {
8356 if((hr=get_reg(regs[i+1].regmap,dops[i+1].rs2))>=0)
8357 {
8358 if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
8359 {
8360 regs[i].regmap[hr]=regs[i+1].regmap[hr];
8361 regmap_pre[i+1][hr]=regs[i+1].regmap[hr];
8362 regs[i+1].regmap_entry[hr]=regs[i+1].regmap[hr];
8363 regs[i].isconst&=~(1<<hr);
8364 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
8365 constmap[i][hr]=constmap[i+1][hr];
8366 regs[i+1].wasdirty&=~(1<<hr);
8367 regs[i].dirty&=~(1<<hr);
8368 }
8369 }
8370 }
8371 // Preload target address for load instruction (non-constant)
8372 if(dops[i+1].itype==LOAD&&dops[i+1].rs1&&get_reg(regs[i+1].regmap,dops[i+1].rs1)<0) {
8373 if((hr=get_reg(regs[i+1].regmap,dops[i+1].rt1))>=0)
8374 {
8375 if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
8376 {
8377 regs[i].regmap[hr]=dops[i+1].rs1;
8378 regmap_pre[i+1][hr]=dops[i+1].rs1;
8379 regs[i+1].regmap_entry[hr]=dops[i+1].rs1;
8380 regs[i].isconst&=~(1<<hr);
8381 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
8382 constmap[i][hr]=constmap[i+1][hr];
8383 regs[i+1].wasdirty&=~(1<<hr);
8384 regs[i].dirty&=~(1<<hr);
8385 }
8386 }
8387 }
8388 // Load source into target register
8389 if(dops[i+1].use_lt1&&get_reg(regs[i+1].regmap,dops[i+1].rs1)<0) {
8390 if((hr=get_reg(regs[i+1].regmap,dops[i+1].rt1))>=0)
8391 {
8392 if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
8393 {
8394 regs[i].regmap[hr]=dops[i+1].rs1;
8395 regmap_pre[i+1][hr]=dops[i+1].rs1;
8396 regs[i+1].regmap_entry[hr]=dops[i+1].rs1;
8397 regs[i].isconst&=~(1<<hr);
8398 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
8399 constmap[i][hr]=constmap[i+1][hr];
8400 regs[i+1].wasdirty&=~(1<<hr);
8401 regs[i].dirty&=~(1<<hr);
8402 }
8403 }
8404 }
8405 // Address for store instruction (non-constant)
8406 if(dops[i+1].itype==STORE||dops[i+1].itype==STORELR
8407 ||(dops[i+1].opcode&0x3b)==0x39||(dops[i+1].opcode&0x3b)==0x3a) { // SB/SH/SW/SD/SWC1/SDC1/SWC2/SDC2
8408 if(get_reg(regs[i+1].regmap,dops[i+1].rs1)<0) {
8409 hr=get_reg2(regs[i].regmap,regs[i+1].regmap,-1);
8410 if(hr<0) hr=get_reg_temp(regs[i+1].regmap);
8411 else {
8412 regs[i+1].regmap[hr]=AGEN1+((i+1)&1);
8413 regs[i+1].isconst&=~(1<<hr);
8414 }
8415 assert(hr>=0);
8416 if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
8417 {
8418 regs[i].regmap[hr]=dops[i+1].rs1;
8419 regmap_pre[i+1][hr]=dops[i+1].rs1;
8420 regs[i+1].regmap_entry[hr]=dops[i+1].rs1;
8421 regs[i].isconst&=~(1<<hr);
8422 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
8423 constmap[i][hr]=constmap[i+1][hr];
8424 regs[i+1].wasdirty&=~(1<<hr);
8425 regs[i].dirty&=~(1<<hr);
8426 }
8427 }
8428 }
8429 if(dops[i+1].itype==LOADLR||(dops[i+1].opcode&0x3b)==0x31||(dops[i+1].opcode&0x3b)==0x32) { // LWC1/LDC1, LWC2/LDC2
8430 if(get_reg(regs[i+1].regmap,dops[i+1].rs1)<0) {
8431 int nr;
8432 hr=get_reg(regs[i+1].regmap,FTEMP);
8433 assert(hr>=0);
8434 if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
8435 {
8436 regs[i].regmap[hr]=dops[i+1].rs1;
8437 regmap_pre[i+1][hr]=dops[i+1].rs1;
8438 regs[i+1].regmap_entry[hr]=dops[i+1].rs1;
8439 regs[i].isconst&=~(1<<hr);
8440 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
8441 constmap[i][hr]=constmap[i+1][hr];
8442 regs[i+1].wasdirty&=~(1<<hr);
8443 regs[i].dirty&=~(1<<hr);
8444 }
8445 else if((nr=get_reg2(regs[i].regmap,regs[i+1].regmap,-1))>=0)
8446 {
8447 // move it to another register
8448 regs[i+1].regmap[hr]=-1;
8449 regmap_pre[i+2][hr]=-1;
8450 regs[i+1].regmap[nr]=FTEMP;
8451 regmap_pre[i+2][nr]=FTEMP;
8452 regs[i].regmap[nr]=dops[i+1].rs1;
8453 regmap_pre[i+1][nr]=dops[i+1].rs1;
8454 regs[i+1].regmap_entry[nr]=dops[i+1].rs1;
8455 regs[i].isconst&=~(1<<nr);
8456 regs[i+1].isconst&=~(1<<nr);
8457 regs[i].dirty&=~(1<<nr);
8458 regs[i+1].wasdirty&=~(1<<nr);
8459 regs[i+1].dirty&=~(1<<nr);
8460 regs[i+2].wasdirty&=~(1<<nr);
8461 }
8462 }
8463 }
8464 if(dops[i+1].itype==LOAD||dops[i+1].itype==LOADLR||dops[i+1].itype==STORE||dops[i+1].itype==STORELR/*||dops[i+1].itype==C1LS||||dops[i+1].itype==C2LS*/) {
8465 hr = -1;
8466 if(dops[i+1].itype==LOAD)
8467 hr=get_reg(regs[i+1].regmap,dops[i+1].rt1);
8468 if(dops[i+1].itype==LOADLR||(dops[i+1].opcode&0x3b)==0x31||(dops[i+1].opcode&0x3b)==0x32) // LWC1/LDC1, LWC2/LDC2
8469 hr=get_reg(regs[i+1].regmap,FTEMP);
8470 if(dops[i+1].itype==STORE||dops[i+1].itype==STORELR||(dops[i+1].opcode&0x3b)==0x39||(dops[i+1].opcode&0x3b)==0x3a) { // SWC1/SDC1/SWC2/SDC2
8471 hr=get_reg(regs[i+1].regmap,AGEN1+((i+1)&1));
8472 if(hr<0) hr=get_reg_temp(regs[i+1].regmap);
8473 }
8474 if(hr>=0&&regs[i].regmap[hr]<0) {
8475 int rs=get_reg(regs[i+1].regmap,dops[i+1].rs1);
8476 if(rs>=0&&((regs[i+1].wasconst>>rs)&1)) {
8477 regs[i].regmap[hr]=AGEN1+((i+1)&1);
8478 regmap_pre[i+1][hr]=AGEN1+((i+1)&1);
8479 regs[i+1].regmap_entry[hr]=AGEN1+((i+1)&1);
8480 regs[i].isconst&=~(1<<hr);
8481 regs[i+1].wasdirty&=~(1<<hr);
8482 regs[i].dirty&=~(1<<hr);
8483 }
b372a952 8484 }
8485 }
57871462 8486 }
8487 }
4149788d 8488 }
8489 }
8490}
8491
8492// Write back dirty registers as soon as we will no longer modify them,
8493// so that we don't end up with lots of writes at the branches.
8494static noinline void pass6_clean_registers(int istart, int iend, int wr)
8495{
53358c1d 8496 static u_int wont_dirty[MAXBLOCK];
8497 static u_int will_dirty[MAXBLOCK];
4149788d 8498 int i;
8499 int r;
8500 u_int will_dirty_i,will_dirty_next,temp_will_dirty;
8501 u_int wont_dirty_i,wont_dirty_next,temp_wont_dirty;
8502 if(iend==slen-1) {
8503 will_dirty_i=will_dirty_next=0;
8504 wont_dirty_i=wont_dirty_next=0;
8505 }else{
8506 will_dirty_i=will_dirty_next=will_dirty[iend+1];
8507 wont_dirty_i=wont_dirty_next=wont_dirty[iend+1];
8508 }
8509 for (i=iend;i>=istart;i--)
8510 {
8511 signed char rregmap_i[RRMAP_SIZE];
8512 u_int hr_candirty = 0;
8513 assert(HOST_REGS < 32);
8514 make_rregs(regs[i].regmap, rregmap_i, &hr_candirty);
8515 __builtin_prefetch(regs[i-1].regmap);
8516 if(dops[i].is_jump)
8517 {
8518 signed char branch_rregmap_i[RRMAP_SIZE];
8519 u_int branch_hr_candirty = 0;
8520 make_rregs(branch_regs[i].regmap, branch_rregmap_i, &branch_hr_candirty);
8521 if(ba[i]<start || ba[i]>=(start+slen*4))
8522 {
8523 // Branch out of this block, flush all regs
8524 will_dirty_i = 0;
8525 will_dirty_i |= 1u << (get_rreg(branch_rregmap_i, dops[i].rt1) & 31);
8526 will_dirty_i |= 1u << (get_rreg(branch_rregmap_i, dops[i].rt2) & 31);
8527 will_dirty_i |= 1u << (get_rreg(branch_rregmap_i, dops[i+1].rt1) & 31);
8528 will_dirty_i |= 1u << (get_rreg(branch_rregmap_i, dops[i+1].rt2) & 31);
8529 will_dirty_i |= 1u << (get_rreg(branch_rregmap_i, CCREG) & 31);
8530 will_dirty_i &= branch_hr_candirty;
8531 if (dops[i].is_ujump)
8532 {
8533 // Unconditional branch
8534 wont_dirty_i = 0;
8535 // Merge in delay slot (will dirty)
8536 will_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i].rt1) & 31);
8537 will_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i].rt2) & 31);
8538 will_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i+1].rt1) & 31);
8539 will_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i+1].rt2) & 31);
8540 will_dirty_i |= 1u << (get_rreg(rregmap_i, CCREG) & 31);
8541 will_dirty_i &= hr_candirty;
57871462 8542 }
4149788d 8543 else
8544 {
8545 // Conditional branch
8546 wont_dirty_i = wont_dirty_next;
8547 // Merge in delay slot (will dirty)
8548 // (the original code had no explanation why these 2 are commented out)
8549 //will_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i].rt1) & 31);
8550 //will_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i].rt2) & 31);
8551 will_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i+1].rt1) & 31);
8552 will_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i+1].rt2) & 31);
8553 will_dirty_i |= 1u << (get_rreg(rregmap_i, CCREG) & 31);
8554 will_dirty_i &= hr_candirty;
8555 }
8556 // Merge in delay slot (wont dirty)
8557 wont_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i].rt1) & 31);
8558 wont_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i].rt2) & 31);
8559 wont_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i+1].rt1) & 31);
8560 wont_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i+1].rt2) & 31);
8561 wont_dirty_i |= 1u << (get_rreg(rregmap_i, CCREG) & 31);
8562 wont_dirty_i |= 1u << (get_rreg(branch_rregmap_i, dops[i].rt1) & 31);
8563 wont_dirty_i |= 1u << (get_rreg(branch_rregmap_i, dops[i].rt2) & 31);
8564 wont_dirty_i |= 1u << (get_rreg(branch_rregmap_i, dops[i+1].rt1) & 31);
8565 wont_dirty_i |= 1u << (get_rreg(branch_rregmap_i, dops[i+1].rt2) & 31);
8566 wont_dirty_i |= 1u << (get_rreg(branch_rregmap_i, CCREG) & 31);
8567 wont_dirty_i &= ~(1u << 31);
8568 if(wr) {
8569 #ifndef DESTRUCTIVE_WRITEBACK
8570 branch_regs[i].dirty&=wont_dirty_i;
8571 #endif
8572 branch_regs[i].dirty|=will_dirty_i;
8573 }
8574 }
8575 else
8576 {
8577 // Internal branch
8578 if(ba[i]<=start+i*4) {
8579 // Backward branch
8580 if (dops[i].is_ujump)
8581 {
8582 // Unconditional branch
8583 temp_will_dirty=0;
8584 temp_wont_dirty=0;
8585 // Merge in delay slot (will dirty)
8586 temp_will_dirty |= 1u << (get_rreg(branch_rregmap_i, dops[i].rt1) & 31);
8587 temp_will_dirty |= 1u << (get_rreg(branch_rregmap_i, dops[i].rt2) & 31);
8588 temp_will_dirty |= 1u << (get_rreg(branch_rregmap_i, dops[i+1].rt1) & 31);
8589 temp_will_dirty |= 1u << (get_rreg(branch_rregmap_i, dops[i+1].rt2) & 31);
8590 temp_will_dirty |= 1u << (get_rreg(branch_rregmap_i, CCREG) & 31);
8591 temp_will_dirty &= branch_hr_candirty;
8592 temp_will_dirty |= 1u << (get_rreg(rregmap_i, dops[i].rt1) & 31);
8593 temp_will_dirty |= 1u << (get_rreg(rregmap_i, dops[i].rt2) & 31);
8594 temp_will_dirty |= 1u << (get_rreg(rregmap_i, dops[i+1].rt1) & 31);
8595 temp_will_dirty |= 1u << (get_rreg(rregmap_i, dops[i+1].rt2) & 31);
8596 temp_will_dirty |= 1u << (get_rreg(rregmap_i, CCREG) & 31);
8597 temp_will_dirty &= hr_candirty;
8598 } else {
8599 // Conditional branch (not taken case)
8600 temp_will_dirty=will_dirty_next;
8601 temp_wont_dirty=wont_dirty_next;
8602 // Merge in delay slot (will dirty)
8603 temp_will_dirty |= 1u << (get_rreg(branch_rregmap_i, dops[i].rt1) & 31);
8604 temp_will_dirty |= 1u << (get_rreg(branch_rregmap_i, dops[i].rt2) & 31);
8605 temp_will_dirty |= 1u << (get_rreg(branch_rregmap_i, dops[i+1].rt1) & 31);
8606 temp_will_dirty |= 1u << (get_rreg(branch_rregmap_i, dops[i+1].rt2) & 31);
8607 temp_will_dirty |= 1u << (get_rreg(branch_rregmap_i, CCREG) & 31);
8608 temp_will_dirty &= branch_hr_candirty;
8609 //temp_will_dirty |= 1u << (get_rreg(rregmap_i, dops[i].rt1) & 31);
8610 //temp_will_dirty |= 1u << (get_rreg(rregmap_i, dops[i].rt2) & 31);
8611 temp_will_dirty |= 1u << (get_rreg(rregmap_i, dops[i+1].rt1) & 31);
8612 temp_will_dirty |= 1u << (get_rreg(rregmap_i, dops[i+1].rt2) & 31);
8613 temp_will_dirty |= 1u << (get_rreg(rregmap_i, CCREG) & 31);
8614 temp_will_dirty &= hr_candirty;
8615 }
8616 // Merge in delay slot (wont dirty)
8617 temp_wont_dirty |= 1u << (get_rreg(rregmap_i, dops[i].rt1) & 31);
8618 temp_wont_dirty |= 1u << (get_rreg(rregmap_i, dops[i].rt2) & 31);
8619 temp_wont_dirty |= 1u << (get_rreg(rregmap_i, dops[i+1].rt1) & 31);
8620 temp_wont_dirty |= 1u << (get_rreg(rregmap_i, dops[i+1].rt2) & 31);
8621 temp_wont_dirty |= 1u << (get_rreg(rregmap_i, CCREG) & 31);
8622 temp_wont_dirty |= 1u << (get_rreg(branch_rregmap_i, dops[i].rt1) & 31);
8623 temp_wont_dirty |= 1u << (get_rreg(branch_rregmap_i, dops[i].rt2) & 31);
8624 temp_wont_dirty |= 1u << (get_rreg(branch_rregmap_i, dops[i+1].rt1) & 31);
8625 temp_wont_dirty |= 1u << (get_rreg(branch_rregmap_i, dops[i+1].rt2) & 31);
8626 temp_wont_dirty |= 1u << (get_rreg(branch_rregmap_i, CCREG) & 31);
8627 temp_wont_dirty &= ~(1u << 31);
8628 // Deal with changed mappings
8629 if(i<iend) {
8630 for(r=0;r<HOST_REGS;r++) {
8631 if(r!=EXCLUDE_REG) {
8632 if(regs[i].regmap[r]!=regmap_pre[i][r]) {
8633 temp_will_dirty&=~(1<<r);
8634 temp_wont_dirty&=~(1<<r);
8635 if(regmap_pre[i][r]>0 && regmap_pre[i][r]<34) {
8636 temp_will_dirty|=((unneeded_reg[i]>>regmap_pre[i][r])&1)<<r;
8637 temp_wont_dirty|=((unneeded_reg[i]>>regmap_pre[i][r])&1)<<r;
8638 } else {
8639 temp_will_dirty|=1<<r;
8640 temp_wont_dirty|=1<<r;
8641 }
8642 }
8643 }
8644 }
8645 }
8646 if(wr) {
8647 will_dirty[i]=temp_will_dirty;
8648 wont_dirty[i]=temp_wont_dirty;
8649 pass6_clean_registers((ba[i]-start)>>2,i-1,0);
8650 }else{
8651 // Limit recursion. It can take an excessive amount
8652 // of time if there are a lot of nested loops.
8653 will_dirty[(ba[i]-start)>>2]=0;
8654 wont_dirty[(ba[i]-start)>>2]=-1;
57871462 8655 }
57871462 8656 }
4149788d 8657 /*else*/ if(1)
57871462 8658 {
4149788d 8659 if (dops[i].is_ujump)
8660 {
8661 // Unconditional branch
8662 will_dirty_i=0;
8663 wont_dirty_i=0;
8664 //if(ba[i]>start+i*4) { // Disable recursion (for debugging)
8665 for(r=0;r<HOST_REGS;r++) {
8666 if(r!=EXCLUDE_REG) {
8667 if(branch_regs[i].regmap[r]==regs[(ba[i]-start)>>2].regmap_entry[r]) {
8668 will_dirty_i|=will_dirty[(ba[i]-start)>>2]&(1<<r);
8669 wont_dirty_i|=wont_dirty[(ba[i]-start)>>2]&(1<<r);
8670 }
8671 if(branch_regs[i].regmap[r]>=0) {
8672 will_dirty_i|=((unneeded_reg[(ba[i]-start)>>2]>>branch_regs[i].regmap[r])&1)<<r;
8673 wont_dirty_i|=((unneeded_reg[(ba[i]-start)>>2]>>branch_regs[i].regmap[r])&1)<<r;
8674 }
8675 }
57871462 8676 }
4149788d 8677 //}
8678 // Merge in delay slot
8679 will_dirty_i |= 1u << (get_rreg(branch_rregmap_i, dops[i].rt1) & 31);
8680 will_dirty_i |= 1u << (get_rreg(branch_rregmap_i, dops[i].rt2) & 31);
8681 will_dirty_i |= 1u << (get_rreg(branch_rregmap_i, dops[i+1].rt1) & 31);
8682 will_dirty_i |= 1u << (get_rreg(branch_rregmap_i, dops[i+1].rt2) & 31);
8683 will_dirty_i |= 1u << (get_rreg(branch_rregmap_i, CCREG) & 31);
8684 will_dirty_i &= branch_hr_candirty;
8685 will_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i].rt1) & 31);
8686 will_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i].rt2) & 31);
8687 will_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i+1].rt1) & 31);
8688 will_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i+1].rt2) & 31);
8689 will_dirty_i |= 1u << (get_rreg(rregmap_i, CCREG) & 31);
8690 will_dirty_i &= hr_candirty;
8691 } else {
8692 // Conditional branch
8693 will_dirty_i=will_dirty_next;
8694 wont_dirty_i=wont_dirty_next;
8695 //if(ba[i]>start+i*4) // Disable recursion (for debugging)
8696 for(r=0;r<HOST_REGS;r++) {
8697 if(r!=EXCLUDE_REG) {
8698 signed char target_reg=branch_regs[i].regmap[r];
8699 if(target_reg==regs[(ba[i]-start)>>2].regmap_entry[r]) {
8700 will_dirty_i&=will_dirty[(ba[i]-start)>>2]&(1<<r);
8701 wont_dirty_i|=wont_dirty[(ba[i]-start)>>2]&(1<<r);
8702 }
8703 else if(target_reg>=0) {
8704 will_dirty_i&=((unneeded_reg[(ba[i]-start)>>2]>>target_reg)&1)<<r;
8705 wont_dirty_i|=((unneeded_reg[(ba[i]-start)>>2]>>target_reg)&1)<<r;
8706 }
8707 }
57871462 8708 }
4149788d 8709 // Merge in delay slot
8710 will_dirty_i |= 1u << (get_rreg(branch_rregmap_i, dops[i].rt1) & 31);
8711 will_dirty_i |= 1u << (get_rreg(branch_rregmap_i, dops[i].rt2) & 31);
8712 will_dirty_i |= 1u << (get_rreg(branch_rregmap_i, dops[i+1].rt1) & 31);
8713 will_dirty_i |= 1u << (get_rreg(branch_rregmap_i, dops[i+1].rt2) & 31);
8714 will_dirty_i |= 1u << (get_rreg(branch_rregmap_i, CCREG) & 31);
8715 will_dirty_i &= branch_hr_candirty;
8716 //will_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i].rt1) & 31);
8717 //will_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i].rt2) & 31);
8718 will_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i+1].rt1) & 31);
8719 will_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i+1].rt2) & 31);
8720 will_dirty_i |= 1u << (get_rreg(rregmap_i, CCREG) & 31);
8721 will_dirty_i &= hr_candirty;
57871462 8722 }
4149788d 8723 // Merge in delay slot (won't dirty)
8724 wont_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i].rt1) & 31);
8725 wont_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i].rt2) & 31);
8726 wont_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i+1].rt1) & 31);
8727 wont_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i+1].rt2) & 31);
8728 wont_dirty_i |= 1u << (get_rreg(rregmap_i, CCREG) & 31);
8729 wont_dirty_i |= 1u << (get_rreg(branch_rregmap_i, dops[i].rt1) & 31);
8730 wont_dirty_i |= 1u << (get_rreg(branch_rregmap_i, dops[i].rt2) & 31);
8731 wont_dirty_i |= 1u << (get_rreg(branch_rregmap_i, dops[i+1].rt1) & 31);
8732 wont_dirty_i |= 1u << (get_rreg(branch_rregmap_i, dops[i+1].rt2) & 31);
8733 wont_dirty_i |= 1u << (get_rreg(branch_rregmap_i, CCREG) & 31);
8734 wont_dirty_i &= ~(1u << 31);
8735 if(wr) {
8736 #ifndef DESTRUCTIVE_WRITEBACK
8737 branch_regs[i].dirty&=wont_dirty_i;
8738 #endif
8739 branch_regs[i].dirty|=will_dirty_i;
57871462 8740 }
8741 }
8742 }
57871462 8743 }
4149788d 8744 else if(dops[i].itype==SYSCALL||dops[i].itype==HLECALL||dops[i].itype==INTCALL)
57871462 8745 {
4149788d 8746 // SYSCALL instruction (software interrupt)
8747 will_dirty_i=0;
8748 wont_dirty_i=0;
8749 }
8750 else if(dops[i].itype==COP0 && (source[i]&0x3f)==0x18)
8751 {
8752 // ERET instruction (return from interrupt)
8753 will_dirty_i=0;
8754 wont_dirty_i=0;
8755 }
8756 will_dirty_next=will_dirty_i;
8757 wont_dirty_next=wont_dirty_i;
8758 will_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i].rt1) & 31);
8759 will_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i].rt2) & 31);
8760 will_dirty_i |= 1u << (get_rreg(rregmap_i, CCREG) & 31);
8761 will_dirty_i &= hr_candirty;
8762 wont_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i].rt1) & 31);
8763 wont_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i].rt2) & 31);
8764 wont_dirty_i |= 1u << (get_rreg(rregmap_i, CCREG) & 31);
8765 wont_dirty_i &= ~(1u << 31);
8766 if (i > istart && !dops[i].is_jump) {
8767 // Don't store a register immediately after writing it,
8768 // may prevent dual-issue.
8769 wont_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i-1].rt1) & 31);
8770 wont_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i-1].rt2) & 31);
8771 }
8772 // Save it
8773 will_dirty[i]=will_dirty_i;
8774 wont_dirty[i]=wont_dirty_i;
8775 // Mark registers that won't be dirtied as not dirty
8776 if(wr) {
8777 regs[i].dirty|=will_dirty_i;
8778 #ifndef DESTRUCTIVE_WRITEBACK
8779 regs[i].dirty&=wont_dirty_i;
8780 if(dops[i].is_jump)
57871462 8781 {
4149788d 8782 if (i < iend-1 && !dops[i].is_ujump) {
8783 for(r=0;r<HOST_REGS;r++) {
8784 if(r!=EXCLUDE_REG) {
8785 if(regs[i].regmap[r]==regmap_pre[i+2][r]) {
8786 regs[i+2].wasdirty&=wont_dirty_i|~(1<<r);
8787 }else {/*printf("i: %x (%d) mismatch(+2): %d\n",start+i*4,i,r);assert(!((wont_dirty_i>>r)&1));*/}
57871462 8788 }
8789 }
8790 }
4149788d 8791 }
8792 else
8793 {
8794 if(i<iend) {
8795 for(r=0;r<HOST_REGS;r++) {
8796 if(r!=EXCLUDE_REG) {
8797 if(regs[i].regmap[r]==regmap_pre[i+1][r]) {
8798 regs[i+1].wasdirty&=wont_dirty_i|~(1<<r);
8799 }else {/*printf("i: %x (%d) mismatch(+1): %d\n",start+i*4,i,r);assert(!((wont_dirty_i>>r)&1));*/}
57871462 8800 }
8801 }
8802 }
4149788d 8803 }
8804 #endif
8805 }
8806 // Deal with changed mappings
8807 temp_will_dirty=will_dirty_i;
8808 temp_wont_dirty=wont_dirty_i;
8809 for(r=0;r<HOST_REGS;r++) {
8810 if(r!=EXCLUDE_REG) {
8811 int nr;
8812 if(regs[i].regmap[r]==regmap_pre[i][r]) {
8813 if(wr) {
8814 #ifndef DESTRUCTIVE_WRITEBACK
8815 regs[i].wasdirty&=wont_dirty_i|~(1<<r);
8816 #endif
8817 regs[i].wasdirty|=will_dirty_i&(1<<r);
57871462 8818 }
4149788d 8819 }
8820 else if(regmap_pre[i][r]>=0&&(nr=get_rreg(rregmap_i,regmap_pre[i][r]))>=0) {
8821 // Register moved to a different register
8822 will_dirty_i&=~(1<<r);
8823 wont_dirty_i&=~(1<<r);
8824 will_dirty_i|=((temp_will_dirty>>nr)&1)<<r;
8825 wont_dirty_i|=((temp_wont_dirty>>nr)&1)<<r;
8826 if(wr) {
8827 #ifndef DESTRUCTIVE_WRITEBACK
8828 regs[i].wasdirty&=wont_dirty_i|~(1<<r);
8829 #endif
8830 regs[i].wasdirty|=will_dirty_i&(1<<r);
8831 }
8832 }
8833 else {
8834 will_dirty_i&=~(1<<r);
8835 wont_dirty_i&=~(1<<r);
8836 if(regmap_pre[i][r]>0 && regmap_pre[i][r]<34) {
8837 will_dirty_i|=((unneeded_reg[i]>>regmap_pre[i][r])&1)<<r;
8838 wont_dirty_i|=((unneeded_reg[i]>>regmap_pre[i][r])&1)<<r;
8839 } else {
8840 wont_dirty_i|=1<<r;
8841 /*printf("i: %x (%d) mismatch: %d\n",start+i*4,i,r);assert(!((will_dirty>>r)&1));*/
57871462 8842 }
8843 }
8844 }
8845 }
8846 }
4149788d 8847}
8848
8849static noinline void pass10_expire_blocks(void)
8850{
93c0345b 8851 u_int step = MAX_OUTPUT_BLOCK_SIZE / PAGE_COUNT / 2;
8852 // not sizeof(ndrc->translation_cache) due to vita hack
8853 u_int step_mask = ((1u << TARGET_SIZE_2) - 1u) & ~(step - 1u);
8854 u_int end = (out - ndrc->translation_cache + EXPIRITY_OFFSET) & step_mask;
8855 u_int base_shift = __builtin_ctz(MAX_OUTPUT_BLOCK_SIZE);
8856 int hit;
8857
8858 for (; expirep != end; expirep = ((expirep + step) & step_mask))
4149788d 8859 {
93c0345b 8860 u_int base_offs = expirep & ~(MAX_OUTPUT_BLOCK_SIZE - 1);
8861 u_int block_i = expirep / step & (PAGE_COUNT - 1);
8862 u_int phase = (expirep >> (base_shift - 1)) & 1u;
8863 if (!(expirep & (MAX_OUTPUT_BLOCK_SIZE / 2 - 1))) {
8864 inv_debug("EXP: base_offs %x/%x phase %u\n", base_offs,
55a695d9 8865 out - ndrc->translation_cache, phase);
93c0345b 8866 }
8867
8868 if (!phase) {
8869 hit = blocks_remove_matching_addrs(&blocks[block_i], base_offs, base_shift);
8870 if (hit) {
8871 do_clear_cache();
8872 #ifdef USE_MINI_HT
8873 memset(mini_ht, -1, sizeof(mini_ht));
8874 #endif
8875 }
4149788d 8876 }
93c0345b 8877 else
b7ad2f2c 8878 unlink_jumps_tc_range(jumps[block_i], base_offs, base_shift);
4149788d 8879 }
8880}
8881
104df9d3 8882static struct block_info *new_block_info(u_int start, u_int len,
8883 const void *source, const void *copy, u_char *beginning, u_short jump_in_count)
8884{
8885 struct block_info **b_pptr;
8886 struct block_info *block;
8887 u_int page = get_page(start);
8888
8889 block = malloc(sizeof(*block) + jump_in_count * sizeof(block->jump_in[0]));
8890 assert(block);
8891 assert(jump_in_count > 0);
8892 block->source = source;
8893 block->copy = copy;
8894 block->start = start;
8895 block->len = len;
8896 block->reg_sv_flags = 0;
8897 block->tc_offs = beginning - ndrc->translation_cache;
8898 //block->tc_len = out - beginning;
8899 block->is_dirty = 0;
3280e616 8900 block->inv_near_misses = 0;
104df9d3 8901 block->jump_in_cnt = jump_in_count;
8902
93c0345b 8903 // insert sorted by start mirror-unmasked vaddr
104df9d3 8904 for (b_pptr = &blocks[page]; ; b_pptr = &((*b_pptr)->next)) {
8905 if (*b_pptr == NULL || (*b_pptr)->start >= start) {
8906 block->next = *b_pptr;
8907 *b_pptr = block;
8908 break;
8909 }
8910 }
8911 stat_inc(stat_blocks);
8912 return block;
8913}
8914
8915static int new_recompile_block(u_int addr)
4149788d 8916{
8917 u_int pagelimit = 0;
8918 u_int state_rflags = 0;
8919 int i;
8920
8921 assem_debug("NOTCOMPILED: addr = %x -> %p\n", addr, out);
8922
8923 // this is just for speculation
8924 for (i = 1; i < 32; i++) {
8925 if ((psxRegs.GPR.r[i] & 0xffff0000) == 0x1f800000)
8926 state_rflags |= 1 << i;
8927 }
8928
4bdc30ab 8929 assert(!(addr & 3));
8930 start = addr & ~3;
4149788d 8931 new_dynarec_did_compile=1;
8932 if (Config.HLE && start == 0x80001000) // hlecall
8933 {
8934 // XXX: is this enough? Maybe check hleSoftCall?
104df9d3 8935 void *beginning = start_block();
4149788d 8936
4149788d 8937 emit_movimm(start,0);
8938 emit_writeword(0,&pcaddr);
8939 emit_far_jump(new_dyna_leave);
8940 literal_pool(0);
8941 end_block(beginning);
104df9d3 8942 struct block_info *block = new_block_info(start, 4, NULL, NULL, beginning, 1);
8943 block->jump_in[0].vaddr = start;
8944 block->jump_in[0].addr = beginning;
4149788d 8945 return 0;
8946 }
8947 else if (f1_hack && hack_addr == 0) {
8948 void *beginning = start_block();
4149788d 8949 emit_movimm(start, 0);
8950 emit_writeword(0, &hack_addr);
8951 emit_readword(&psxRegs.GPR.n.sp, 0);
8952 emit_readptr(&mem_rtab, 1);
8953 emit_shrimm(0, 12, 2);
8954 emit_readptr_dualindexedx_ptrlen(1, 2, 1);
8955 emit_addimm(0, 0x18, 0);
8956 emit_adds_ptr(1, 1, 1);
8957 emit_ldr_dualindexed(1, 0, 0);
8958 emit_writeword(0, &psxRegs.GPR.r[26]); // lw k0, 0x18(sp)
104df9d3 8959 emit_far_call(ndrc_get_addr_ht);
4149788d 8960 emit_jmpreg(0); // jr k0
8961 literal_pool(0);
8962 end_block(beginning);
8963
104df9d3 8964 struct block_info *block = new_block_info(start, 4, NULL, NULL, beginning, 1);
8965 block->jump_in[0].vaddr = start;
8966 block->jump_in[0].addr = beginning;
4149788d 8967 SysPrintf("F1 hack to %08x\n", start);
8968 return 0;
8969 }
8970
8971 cycle_multiplier_active = cycle_multiplier_override && cycle_multiplier == CYCLE_MULT_DEFAULT
8972 ? cycle_multiplier_override : cycle_multiplier;
8973
8974 source = get_source_start(start, &pagelimit);
8975 if (source == NULL) {
8976 if (addr != hack_addr) {
8977 SysPrintf("Compile at bogus memory address: %08x\n", addr);
8978 hack_addr = addr;
8979 }
8980 //abort();
8981 return -1;
8982 }
8983
8984 /* Pass 1: disassemble */
8985 /* Pass 2: register dependencies, branch targets */
8986 /* Pass 3: register allocation */
8987 /* Pass 4: branch dependencies */
8988 /* Pass 5: pre-alloc */
8989 /* Pass 6: optimize clean/dirty state */
8990 /* Pass 7: flag 32-bit registers */
8991 /* Pass 8: assembly */
8992 /* Pass 9: linker */
8993 /* Pass 10: garbage collection / free memory */
8994
8995 /* Pass 1 disassembly */
8996
8997 pass1_disassemble(pagelimit);
8998
8999 int clear_hack_addr = apply_hacks();
9000
9001 /* Pass 2 - Register dependencies and branch targets */
9002
9003 pass2_unneeded_regs(0,slen-1,0);
9004
9005 /* Pass 3 - Register allocation */
9006
9007 pass3_register_alloc(addr);
9008
9009 /* Pass 4 - Cull unused host registers */
9010
9011 pass4_cull_unused_regs();
9012
9013 /* Pass 5 - Pre-allocate registers */
9014
9015 pass5a_preallocate1();
9016 pass5b_preallocate2();
9f51b4b9 9017
57871462 9018 /* Pass 6 - Optimize clean/dirty state */
4149788d 9019 pass6_clean_registers(0, slen-1, 1);
9f51b4b9 9020
57871462 9021 /* Pass 7 - Identify 32-bit registers */
04fd948a 9022 for (i=slen-1;i>=0;i--)
9023 {
cf95b4f0 9024 if(dops[i].itype==CJUMP||dops[i].itype==SJUMP)
04fd948a 9025 {
9026 // Conditional branch
9027 if((source[i]>>16)!=0x1000&&i<slen-2) {
9028 // Mark this address as a branch target since it may be called
9029 // upon return from interrupt
cf95b4f0 9030 dops[i+2].bt=1;
04fd948a 9031 }
9032 }
9033 }
57871462 9034
57871462 9035 /* Pass 8 - Assembly */
9036 linkcount=0;stubcount=0;
4149788d 9037 is_delayslot=0;
57871462 9038 u_int dirty_pre=0;
d148d265 9039 void *beginning=start_block();
df4dc2b1 9040 void *instr_addr0_override = NULL;
4bdc30ab 9041 int ds = 0;
9ad4d757 9042
9ad4d757 9043 if (start == 0x80030000) {
3968e69e 9044 // nasty hack for the fastbios thing
96186eba 9045 // override block entry to this code
df4dc2b1 9046 instr_addr0_override = out;
9ad4d757 9047 emit_movimm(start,0);
96186eba 9048 // abuse io address var as a flag that we
9049 // have already returned here once
643aeae3 9050 emit_readword(&address,1);
9051 emit_writeword(0,&pcaddr);
9052 emit_writeword(0,&address);
9ad4d757 9053 emit_cmp(0,1);
3968e69e 9054 #ifdef __aarch64__
9055 emit_jeq(out + 4*2);
2a014d73 9056 emit_far_jump(new_dyna_leave);
3968e69e 9057 #else
643aeae3 9058 emit_jne(new_dyna_leave);
3968e69e 9059 #endif
9ad4d757 9060 }
57871462 9061 for(i=0;i<slen;i++)
9062 {
9de8a0c3 9063 __builtin_prefetch(regs[i+1].regmap);
670c0f22 9064 check_regmap(regmap_pre[i]);
9065 check_regmap(regs[i].regmap_entry);
9066 check_regmap(regs[i].regmap);
57871462 9067 //if(ds) printf("ds: ");
4600ba03 9068 disassemble_inst(i);
57871462 9069 if(ds) {
9070 ds=0; // Skip delay slot
cf95b4f0 9071 if(dops[i].bt) assem_debug("OOPS - branch into delay slot\n");
df4dc2b1 9072 instr_addr[i] = NULL;
57871462 9073 } else {
ffb0b9e0 9074 speculate_register_values(i);
57871462 9075 #ifndef DESTRUCTIVE_WRITEBACK
fe807a8a 9076 if (i < 2 || !dops[i-2].is_ujump)
57871462 9077 {
ad49de89 9078 wb_valid(regmap_pre[i],regs[i].regmap_entry,dirty_pre,regs[i].wasdirty,unneeded_reg[i]);
57871462 9079 }
fe807a8a 9080 if((dops[i].itype==CJUMP||dops[i].itype==SJUMP)) {
f776eb14 9081 dirty_pre=branch_regs[i].dirty;
9082 }else{
f776eb14 9083 dirty_pre=regs[i].dirty;
9084 }
57871462 9085 #endif
9086 // write back
fe807a8a 9087 if (i < 2 || !dops[i-2].is_ujump)
57871462 9088 {
ad49de89 9089 wb_invalidate(regmap_pre[i],regs[i].regmap_entry,regs[i].wasdirty,unneeded_reg[i]);
57871462 9090 loop_preload(regmap_pre[i],regs[i].regmap_entry);
9091 }
9092 // branch target entry point
df4dc2b1 9093 instr_addr[i] = out;
57871462 9094 assem_debug("<->\n");
2330734f 9095 drc_dbg_emit_do_cmp(i, ccadj[i]);
7f94b097 9096 if (clear_hack_addr) {
9097 emit_movimm(0, 0);
9098 emit_writeword(0, &hack_addr);
9099 clear_hack_addr = 0;
9100 }
dd114d7d 9101
57871462 9102 // load regs
9103 if(regs[i].regmap_entry[HOST_CCREG]==CCREG&&regs[i].regmap[HOST_CCREG]!=CCREG)
ad49de89 9104 wb_register(CCREG,regs[i].regmap_entry,regs[i].wasdirty);
cf95b4f0 9105 load_regs(regs[i].regmap_entry,regs[i].regmap,dops[i].rs1,dops[i].rs2);
57871462 9106 address_generation(i,&regs[i],regs[i].regmap_entry);
ad49de89 9107 load_consts(regmap_pre[i],regs[i].regmap,i);
fe807a8a 9108 if(dops[i].is_jump)
57871462 9109 {
9110 // Load the delay slot registers if necessary
cf95b4f0 9111 if(dops[i+1].rs1!=dops[i].rs1&&dops[i+1].rs1!=dops[i].rs2&&(dops[i+1].rs1!=dops[i].rt1||dops[i].rt1==0))
9112 load_regs(regs[i].regmap_entry,regs[i].regmap,dops[i+1].rs1,dops[i+1].rs1);
9113 if(dops[i+1].rs2!=dops[i+1].rs1&&dops[i+1].rs2!=dops[i].rs1&&dops[i+1].rs2!=dops[i].rs2&&(dops[i+1].rs2!=dops[i].rt1||dops[i].rt1==0))
9114 load_regs(regs[i].regmap_entry,regs[i].regmap,dops[i+1].rs2,dops[i+1].rs2);
37387d8b 9115 if (ram_offset && (dops[i+1].is_load || dops[i+1].is_store))
53358c1d 9116 load_reg(regs[i].regmap_entry,regs[i].regmap,ROREG);
37387d8b 9117 if (dops[i+1].is_store)
53358c1d 9118 load_reg(regs[i].regmap_entry,regs[i].regmap,INVCP);
57871462 9119 }
9120 else if(i+1<slen)
9121 {
9122 // Preload registers for following instruction
cf95b4f0 9123 if(dops[i+1].rs1!=dops[i].rs1&&dops[i+1].rs1!=dops[i].rs2)
9124 if(dops[i+1].rs1!=dops[i].rt1&&dops[i+1].rs1!=dops[i].rt2)
9125 load_regs(regs[i].regmap_entry,regs[i].regmap,dops[i+1].rs1,dops[i+1].rs1);
9126 if(dops[i+1].rs2!=dops[i+1].rs1&&dops[i+1].rs2!=dops[i].rs1&&dops[i+1].rs2!=dops[i].rs2)
9127 if(dops[i+1].rs2!=dops[i].rt1&&dops[i+1].rs2!=dops[i].rt2)
9128 load_regs(regs[i].regmap_entry,regs[i].regmap,dops[i+1].rs2,dops[i+1].rs2);
57871462 9129 }
9130 // TODO: if(is_ooo(i)) address_generation(i+1);
9a3ccfeb 9131 if (!dops[i].is_jump || dops[i].itype == CJUMP)
53358c1d 9132 load_reg(regs[i].regmap_entry,regs[i].regmap,CCREG);
37387d8b 9133 if (ram_offset && (dops[i].is_load || dops[i].is_store))
53358c1d 9134 load_reg(regs[i].regmap_entry,regs[i].regmap,ROREG);
37387d8b 9135 if (dops[i].is_store)
53358c1d 9136 load_reg(regs[i].regmap_entry,regs[i].regmap,INVCP);
2330734f 9137
9138 ds = assemble(i, &regs[i], ccadj[i]);
9139
fe807a8a 9140 if (dops[i].is_ujump)
57871462 9141 literal_pool(1024);
9142 else
9143 literal_pool_jumpover(256);
9144 }
9145 }
3d680478 9146
9147 assert(slen > 0);
cf95b4f0 9148 if (slen > 0 && dops[slen-1].itype == INTCALL) {
3d680478 9149 // no ending needed for this block since INTCALL never returns
9150 }
57871462 9151 // If the block did not end with an unconditional branch,
9152 // add a jump to the next instruction.
3d680478 9153 else if (i > 1) {
4bdc30ab 9154 if (!dops[i-2].is_ujump) {
fe807a8a 9155 assert(!dops[i-1].is_jump);
57871462 9156 assert(i==slen);
cf95b4f0 9157 if(dops[i-2].itype!=CJUMP&&dops[i-2].itype!=SJUMP) {
ad49de89 9158 store_regs_bt(regs[i-1].regmap,regs[i-1].dirty,start+i*4);
57871462 9159 if(regs[i-1].regmap[HOST_CCREG]!=CCREG)
9160 emit_loadreg(CCREG,HOST_CCREG);
2330734f 9161 emit_addimm(HOST_CCREG, ccadj[i-1] + CLOCK_ADJUST(1), HOST_CCREG);
57871462 9162 }
fe807a8a 9163 else
57871462 9164 {
ad49de89 9165 store_regs_bt(branch_regs[i-2].regmap,branch_regs[i-2].dirty,start+i*4);
57871462 9166 assert(branch_regs[i-2].regmap[HOST_CCREG]==CCREG);
9167 }
643aeae3 9168 add_to_linker(out,start+i*4,0);
57871462 9169 emit_jmp(0);
9170 }
9171 }
9172 else
9173 {
9174 assert(i>0);
fe807a8a 9175 assert(!dops[i-1].is_jump);
ad49de89 9176 store_regs_bt(regs[i-1].regmap,regs[i-1].dirty,start+i*4);
57871462 9177 if(regs[i-1].regmap[HOST_CCREG]!=CCREG)
9178 emit_loadreg(CCREG,HOST_CCREG);
2330734f 9179 emit_addimm(HOST_CCREG, ccadj[i-1] + CLOCK_ADJUST(1), HOST_CCREG);
643aeae3 9180 add_to_linker(out,start+i*4,0);
57871462 9181 emit_jmp(0);
9182 }
9183
9184 // TODO: delay slot stubs?
9185 // Stubs
9186 for(i=0;i<stubcount;i++)
9187 {
b14b6a8f 9188 switch(stubs[i].type)
57871462 9189 {
9190 case LOADB_STUB:
9191 case LOADH_STUB:
9192 case LOADW_STUB:
9193 case LOADD_STUB:
9194 case LOADBU_STUB:
9195 case LOADHU_STUB:
9196 do_readstub(i);break;
9197 case STOREB_STUB:
9198 case STOREH_STUB:
9199 case STOREW_STUB:
9200 case STORED_STUB:
9201 do_writestub(i);break;
9202 case CC_STUB:
9203 do_ccstub(i);break;
9204 case INVCODE_STUB:
9205 do_invstub(i);break;
9206 case FP_STUB:
9207 do_cop1stub(i);break;
9208 case STORELR_STUB:
9209 do_unalignedwritestub(i);break;
9210 }
9211 }
9212
9ad4d757 9213 if (instr_addr0_override)
9214 instr_addr[0] = instr_addr0_override;
9215
93c0345b 9216#if 0
9217 /* check for improper expiration */
9218 for (i = 0; i < ARRAY_SIZE(jumps); i++) {
9219 int j;
9220 if (!jumps[i])
9221 continue;
9222 for (j = 0; j < jumps[i]->count; j++)
9223 assert(jumps[i]->e[j].stub < beginning || (u_char *)jumps[i]->e[j].stub > out);
9224 }
9225#endif
9226
57871462 9227 /* Pass 9 - Linker */
9228 for(i=0;i<linkcount;i++)
9229 {
643aeae3 9230 assem_debug("%p -> %8x\n",link_addr[i].addr,link_addr[i].target);
57871462 9231 literal_pool(64);
104df9d3 9232 if (!link_addr[i].internal)
57871462 9233 {
643aeae3 9234 void *stub = out;
9235 void *addr = check_addr(link_addr[i].target);
9236 emit_extjump(link_addr[i].addr, link_addr[i].target);
9237 if (addr) {
9238 set_jump_target(link_addr[i].addr, addr);
104df9d3 9239 ndrc_add_jump_out(link_addr[i].target,stub);
57871462 9240 }
643aeae3 9241 else
9242 set_jump_target(link_addr[i].addr, stub);
57871462 9243 }
9244 else
9245 {
9246 // Internal branch
643aeae3 9247 int target=(link_addr[i].target-start)>>2;
57871462 9248 assert(target>=0&&target<slen);
9249 assert(instr_addr[target]);
9250 //#ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
643aeae3 9251 //set_jump_target_fillslot(link_addr[i].addr,instr_addr[target],link_addr[i].ext>>1);
57871462 9252 //#else
643aeae3 9253 set_jump_target(link_addr[i].addr, instr_addr[target]);
57871462 9254 //#endif
9255 }
9256 }
3d680478 9257
9258 u_int source_len = slen*4;
cf95b4f0 9259 if (dops[slen-1].itype == INTCALL && source_len > 4)
3d680478 9260 // no need to treat the last instruction as compiled
9261 // as interpreter fully handles it
9262 source_len -= 4;
9263
9264 if ((u_char *)copy + source_len > (u_char *)shadow + sizeof(shadow))
9265 copy = shadow;
9266
57871462 9267 // External Branch Targets (jump_in)
104df9d3 9268 int jump_in_count = 1;
9269 assert(instr_addr[0]);
9270 for (i = 1; i < slen; i++)
9271 {
9272 if (dops[i].bt && instr_addr[i])
9273 jump_in_count++;
9274 }
9275
9276 struct block_info *block =
9277 new_block_info(start, slen * 4, source, copy, beginning, jump_in_count);
9278 block->reg_sv_flags = state_rflags;
9279
9280 int jump_in_i = 0;
9281 for (i = 0; i < slen; i++)
57871462 9282 {
104df9d3 9283 if ((i == 0 || dops[i].bt) && instr_addr[i])
57871462 9284 {
104df9d3 9285 assem_debug("%p (%d) <- %8x\n", instr_addr[i], i, start + i*4);
9286 u_int vaddr = start + i*4;
9287
9288 literal_pool(256);
9289 void *entry = out;
9290 load_regs_entry(i);
9291 if (entry == out)
9292 entry = instr_addr[i];
9293 else
9294 emit_jmp(instr_addr[i]);
9295
9296 block->jump_in[jump_in_i].vaddr = vaddr;
9297 block->jump_in[jump_in_i].addr = entry;
9298 jump_in_i++;
57871462 9299 }
9300 }
104df9d3 9301 assert(jump_in_i == jump_in_count);
9302 hash_table_add(block->jump_in[0].vaddr, block->jump_in[0].addr);
57871462 9303 // Write out the literal pool if necessary
9304 literal_pool(0);
9305 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
9306 // Align code
9307 if(((u_int)out)&7) emit_addnop(13);
9308 #endif
01d26796 9309 assert(out - (u_char *)beginning < MAX_OUTPUT_BLOCK_SIZE);
643aeae3 9310 //printf("shadow buffer: %p-%p\n",copy,(u_char *)copy+slen*4);
3d680478 9311 memcpy(copy, source, source_len);
9312 copy += source_len;
9f51b4b9 9313
d148d265 9314 end_block(beginning);
9f51b4b9 9315
57871462 9316 // If we're within 256K of the end of the buffer,
9317 // start over from the beginning. (Is 256K enough?)
2a014d73 9318 if (out > ndrc->translation_cache + sizeof(ndrc->translation_cache) - MAX_OUTPUT_BLOCK_SIZE)
9319 out = ndrc->translation_cache;
9f51b4b9 9320
57871462 9321 // Trap writes to any of the pages we compiled
104df9d3 9322 mark_invalid_code(start, slen*4, 0);
9f51b4b9 9323
57871462 9324 /* Pass 10 - Free memory by expiring oldest blocks */
9f51b4b9 9325
4149788d 9326 pass10_expire_blocks();
9327
37387d8b 9328#ifdef ASSEM_PRINT
9329 fflush(stdout);
9330#endif
ece032e6 9331 stat_inc(stat_bc_direct);
57871462 9332 return 0;
9333}
b9b61529 9334
9335// vim:shiftwidth=2:expandtab
ARM optimized PCSX fork