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pandora: workaround some reported problems
[picodrive.git] / pico / pico_int.h
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cff531af 1/*\r
2 * PicoDrive - Internal Header File\r
3 * (c) Copyright Dave, 2004\r
4 * (C) notaz, 2006-2010\r
5 *\r
6 * This work is licensed under the terms of MAME license.\r
7 * See COPYING file in the top-level directory.\r
8 */\r
cc68a136 9\r
eff55556 10#ifndef PICO_INTERNAL_INCLUDED\r
11#define PICO_INTERNAL_INCLUDED\r
cc68a136 12\r
13#include <stdio.h>\r
14#include <stdlib.h>\r
15#include <string.h>\r
efcba75f 16#include "pico.h"\r
f53f286a 17#include "carthw/carthw.h"\r
cc68a136 18\r
89fa852d 19//\r
20#define USE_POLL_DETECT\r
21\r
eff55556 22#ifndef PICO_INTERNAL\r
23#define PICO_INTERNAL\r
24#endif\r
25#ifndef PICO_INTERNAL_ASM\r
26#define PICO_INTERNAL_ASM\r
27#endif\r
cc68a136 28\r
70357ce5 29// to select core, define EMU_C68K, EMU_M68K or EMU_F68K in your makefile or project\r
cc68a136 30\r
31#ifdef __cplusplus\r
32extern "C" {\r
33#endif\r
34\r
35\r
36// ----------------------- 68000 CPU -----------------------\r
37#ifdef EMU_C68K\r
d4d62665 38#include "../cpu/cyclone/Cyclone.h"\r
3aa1e148 39extern struct Cyclone PicoCpuCM68k, PicoCpuCS68k;\r
ae214f1c 40#define SekCyclesLeft PicoCpuCM68k.cycles // cycles left for this run\r
41#define SekCyclesLeftS68k PicoCpuCS68k.cycles\r
3aa1e148 42#define SekPc (PicoCpuCM68k.pc-PicoCpuCM68k.membase)\r
43#define SekPcS68k (PicoCpuCS68k.pc-PicoCpuCS68k.membase)\r
12da51c2 44#define SekDar(x) (x < 8 ? PicoCpuCM68k.d[x] : PicoCpuCM68k.a[x - 8])\r
45#define SekDarS68k(x) (x < 8 ? PicoCpuCS68k.d[x] : PicoCpuCS68k.a[x - 8])\r
5fadfb1c 46#define SekSr CycloneGetSr(&PicoCpuCM68k)\r
12da51c2 47#define SekSrS68k CycloneGetSr(&PicoCpuCS68k)\r
3aa1e148 48#define SekSetStop(x) { PicoCpuCM68k.state_flags&=~1; if (x) { PicoCpuCM68k.state_flags|=1; PicoCpuCM68k.cycles=0; } }\r
49#define SekSetStopS68k(x) { PicoCpuCS68k.state_flags&=~1; if (x) { PicoCpuCS68k.state_flags|=1; PicoCpuCS68k.cycles=0; } }\r
ed4402a7 50#define SekIsStoppedM68k() (PicoCpuCM68k.state_flags&1)\r
ca61ee42 51#define SekIsStoppedS68k() (PicoCpuCS68k.state_flags&1)\r
08769494 52#define SekShouldInterrupt() (PicoCpuCM68k.irq > (PicoCpuCM68k.srh&7))\r
b542be46 53\r
54#define SekInterrupt(i) PicoCpuCM68k.irq=i\r
5fadfb1c 55#define SekIrqLevel PicoCpuCM68k.irq\r
b542be46 56\r
cc68a136 57#endif\r
58\r
70357ce5 59#ifdef EMU_F68K\r
60#include "../cpu/fame/fame.h"\r
b542be46 61extern M68K_CONTEXT PicoCpuFM68k, PicoCpuFS68k;\r
ae214f1c 62#define SekCyclesLeft PicoCpuFM68k.io_cycle_counter\r
63#define SekCyclesLeftS68k PicoCpuFS68k.io_cycle_counter\r
03e4f2a3 64#define SekPc fm68k_get_pc(&PicoCpuFM68k)\r
65#define SekPcS68k fm68k_get_pc(&PicoCpuFS68k)\r
12da51c2 66#define SekDar(x) (x < 8 ? PicoCpuFM68k.dreg[x].D : PicoCpuFM68k.areg[x - 8].D)\r
67#define SekDarS68k(x) (x < 8 ? PicoCpuFS68k.dreg[x].D : PicoCpuFS68k.areg[x - 8].D)\r
5fadfb1c 68#define SekSr PicoCpuFM68k.sr\r
12da51c2 69#define SekSrS68k PicoCpuFS68k.sr\r
70357ce5 70#define SekSetStop(x) { \\r
03e4f2a3 71 PicoCpuFM68k.execinfo &= ~FM68K_HALTED; \\r
72 if (x) { PicoCpuFM68k.execinfo |= FM68K_HALTED; PicoCpuFM68k.io_cycle_counter = 0; } \\r
70357ce5 73}\r
74#define SekSetStopS68k(x) { \\r
03e4f2a3 75 PicoCpuFS68k.execinfo &= ~FM68K_HALTED; \\r
76 if (x) { PicoCpuFS68k.execinfo |= FM68K_HALTED; PicoCpuFS68k.io_cycle_counter = 0; } \\r
70357ce5 77}\r
ed4402a7 78#define SekIsStoppedM68k() (PicoCpuFM68k.execinfo&FM68K_HALTED)\r
ca61ee42 79#define SekIsStoppedS68k() (PicoCpuFS68k.execinfo&FM68K_HALTED)\r
08769494 80#define SekShouldInterrupt() fm68k_would_interrupt()\r
b542be46 81\r
82#define SekInterrupt(irq) PicoCpuFM68k.interrupts[0]=irq\r
5fadfb1c 83#define SekIrqLevel PicoCpuFM68k.interrupts[0]\r
b542be46 84\r
cc68a136 85#endif\r
86\r
87#ifdef EMU_M68K\r
88#include "../cpu/musashi/m68kcpu.h"\r
3aa1e148 89extern m68ki_cpu_core PicoCpuMM68k, PicoCpuMS68k;\r
cc68a136 90#ifndef SekCyclesLeft\r
ae214f1c 91#define SekCyclesLeft PicoCpuMM68k.cyc_remaining_cycles\r
92#define SekCyclesLeftS68k PicoCpuMS68k.cyc_remaining_cycles\r
3aa1e148 93#define SekPc m68k_get_reg(&PicoCpuMM68k, M68K_REG_PC)\r
94#define SekPcS68k m68k_get_reg(&PicoCpuMS68k, M68K_REG_PC)\r
12da51c2 95#define SekDar(x) PicoCpuMM68k.dar[x]\r
96#define SekDarS68k(x) PicoCpuMS68k.dar[x]\r
97#define SekSr m68k_get_reg(&PicoCpuMM68k, M68K_REG_SR)\r
98#define SekSrS68k m68k_get_reg(&PicoCpuMS68k, M68K_REG_SR)\r
7a1f6e45 99#define SekSetStop(x) { \\r
3aa1e148 100 if(x) { SET_CYCLES(0); PicoCpuMM68k.stopped=STOP_LEVEL_STOP; } \\r
101 else PicoCpuMM68k.stopped=0; \\r
7a1f6e45 102}\r
103#define SekSetStopS68k(x) { \\r
3aa1e148 104 if(x) { SET_CYCLES(0); PicoCpuMS68k.stopped=STOP_LEVEL_STOP; } \\r
105 else PicoCpuMS68k.stopped=0; \\r
7a1f6e45 106}\r
ed4402a7 107#define SekIsStoppedM68k() (PicoCpuMM68k.stopped==STOP_LEVEL_STOP)\r
ca61ee42 108#define SekIsStoppedS68k() (PicoCpuMS68k.stopped==STOP_LEVEL_STOP)\r
08769494 109#define SekShouldInterrupt() (CPU_INT_LEVEL > FLAG_INT_MASK)\r
b542be46 110\r
71de3cd9 111#define SekInterrupt(irq) { \\r
b542be46 112 void *oldcontext = m68ki_cpu_p; \\r
113 m68k_set_context(&PicoCpuMM68k); \\r
114 m68k_set_irq(irq); \\r
115 m68k_set_context(oldcontext); \\r
116}\r
5fadfb1c 117#define SekIrqLevel (PicoCpuMM68k.int_level >> 8)\r
b542be46 118\r
cc68a136 119#endif\r
ef090115 120#endif // EMU_M68K\r
cc68a136 121\r
ae214f1c 122// while running, cnt represents target of current timeslice\r
123// while not in SekRun(), it's actual cycles done\r
124// (but always use SekCyclesDone() if you need current position)\r
125// cnt may change if timeslice is ended prematurely or extended,\r
126// so we use SekCycleAim for the actual target\r
127extern unsigned int SekCycleCnt;\r
128extern unsigned int SekCycleAim;\r
cc68a136 129\r
ae214f1c 130// number of cycles done (can be checked anywhere)\r
131#define SekCyclesDone() (SekCycleCnt - SekCyclesLeft)\r
132\r
133// burn cycles while not in SekRun() and while in\r
134#define SekCyclesBurn(c) SekCycleCnt += c\r
bc3c13d3 135#define SekCyclesBurnRun(c) { \\r
136 SekCyclesLeft -= c; \\r
137 if (SekCyclesLeft < 0) \\r
138 SekCyclesLeft = 0; \\r
b8cbd802 139}\r
cc68a136 140\r
ae214f1c 141// note: sometimes may extend timeslice to delay an irq\r
cc68a136 142#define SekEndRun(after) { \\r
ae214f1c 143 SekCycleCnt -= SekCyclesLeft - (after); \\r
144 SekCyclesLeft = after; \\r
cc68a136 145}\r
146\r
ae214f1c 147extern unsigned int SekCycleCntS68k;\r
148extern unsigned int SekCycleAimS68k;\r
149\r
07ceafdb 150#define SekEndRunS68k(after) { \\r
ae214f1c 151 if (SekCyclesLeftS68k > (after)) { \\r
152 SekCycleCntS68k -= SekCyclesLeftS68k - (after); \\r
153 SekCyclesLeftS68k = after; \\r
154 } \\r
07ceafdb 155}\r
156\r
ae214f1c 157#define SekCyclesDoneS68k() (SekCycleCntS68k - SekCyclesLeftS68k)\r
cc68a136 158\r
ae214f1c 159// compare cycles, handling overflows\r
160// check if a > b\r
161#define CYCLES_GT(a, b) \\r
162 ((int)((a) - (b)) > 0)\r
163// check if a >= b\r
164#define CYCLES_GE(a, b) \\r
165 ((int)((a) - (b)) >= 0)\r
cc68a136 166\r
b542be46 167// ----------------------- Z80 CPU -----------------------\r
168\r
b4db550e 169#if defined(_USE_DRZ80)\r
dca310c4 170#include "../cpu/DrZ80/drz80.h"\r
b542be46 171\r
172extern struct DrZ80 drZ80;\r
173\r
174#define z80_run(cycles) ((cycles) - DrZ80Run(&drZ80, cycles))\r
175#define z80_run_nr(cycles) DrZ80Run(&drZ80, cycles)\r
4936aac1 176#define z80_int() drZ80.Z80_IRQ = 1\r
835122bc 177#define z80_int() drZ80.Z80_IRQ = 1\r
178#define z80_nmi() drZ80.Z80IF |= 8\r
4b9c5888 179\r
180#define z80_cyclesLeft drZ80.cycles\r
19954be1 181#define z80_pc() (drZ80.Z80PC - drZ80.Z80PC_BASE)\r
b542be46 182\r
183#elif defined(_USE_CZ80)\r
dca310c4 184#include "../cpu/cz80/cz80.h"\r
b542be46 185\r
186#define z80_run(cycles) Cz80_Exec(&CZ80, cycles)\r
187#define z80_run_nr(cycles) Cz80_Exec(&CZ80, cycles)\r
188#define z80_int() Cz80_Set_IRQ(&CZ80, 0, HOLD_LINE)\r
835122bc 189#define z80_nmi() Cz80_Set_IRQ(&CZ80, IRQ_LINE_NMI, 0)\r
4b9c5888 190\r
191#define z80_cyclesLeft (CZ80.ICount - CZ80.ExtraCycles)\r
19954be1 192#define z80_pc() Cz80_Get_Reg(&CZ80, CZ80_PC)\r
b542be46 193\r
194#else\r
195\r
196#define z80_run(cycles) (cycles)\r
197#define z80_run_nr(cycles)\r
198#define z80_int()\r
835122bc 199#define z80_nmi()\r
b542be46 200\r
201#endif\r
202\r
b4db550e 203#define Z80_STATE_SIZE 0x60\r
204\r
ae214f1c 205extern unsigned int last_z80_sync;\r
4b9c5888 206extern int z80_cycle_cnt; /* 'done' z80 cycles before z80_run() */\r
207extern int z80_cycle_aim;\r
208extern int z80_scanline;\r
209extern int z80_scanline_cycles; /* cycles done until z80_scanline */\r
210\r
211#define z80_resetCycles() \\r
ae214f1c 212 last_z80_sync = SekCyclesDone(); \\r
4b9c5888 213 z80_cycle_cnt = z80_cycle_aim = z80_scanline = z80_scanline_cycles = 0;\r
214\r
215#define z80_cyclesDone() \\r
216 (z80_cycle_aim - z80_cyclesLeft)\r
217\r
218#define cycles_68k_to_z80(x) ((x)*957 >> 11)\r
219\r
acd35d4c 220// ----------------------- SH2 CPU -----------------------\r
221\r
41397701 222#include "cpu/sh2/sh2.h"\r
acd35d4c 223\r
1d7a28a7 224extern SH2 sh2s[2];\r
225#define msh2 sh2s[0]\r
226#define ssh2 sh2s[1]\r
227\r
679af8a3 228#ifndef DRC_SH2\r
19886062 229# define sh2_end_run(sh2, after_) do { \\r
230 if ((sh2)->icount > (after_)) { \\r
c1931173 231 (sh2)->cycles_timeslice -= (sh2)->icount - (after_); \\r
19886062 232 (sh2)->icount = after_; \\r
a8fd6e37 233 } \\r
234} while (0)\r
19886062 235# define sh2_cycles_left(sh2) (sh2)->icount\r
8a847c12 236# define sh2_burn_cycles(sh2, n) (sh2)->icount -= n\r
f81107f5 237# define sh2_pc(sh2) (sh2)->ppc\r
679af8a3 238#else\r
19886062 239# define sh2_end_run(sh2, after_) do { \\r
240 int left_ = (signed int)(sh2)->sr >> 12; \\r
241 if (left_ > (after_)) { \\r
c1931173 242 (sh2)->cycles_timeslice -= left_ - (after_); \\r
f4c0720c 243 (sh2)->sr &= 0xfff; \\r
19886062 244 (sh2)->sr |= (after_) << 12; \\r
a8fd6e37 245 } \\r
246} while (0)\r
19886062 247# define sh2_cycles_left(sh2) ((signed int)(sh2)->sr >> 12)\r
8a847c12 248# define sh2_burn_cycles(sh2, n) (sh2)->sr -= ((n) << 12)\r
f81107f5 249# define sh2_pc(sh2) (sh2)->pc\r
679af8a3 250#endif\r
266c6afa 251\r
19886062 252#define sh2_cycles_done(sh2) ((int)(sh2)->cycles_timeslice - sh2_cycles_left(sh2))\r
a7f82a77 253#define sh2_cycles_done_t(sh2) \\r
254 ((sh2)->m68krcycles_done * 3 + sh2_cycles_done(sh2))\r
19886062 255#define sh2_cycles_done_m68k(sh2) \\r
256 ((sh2)->m68krcycles_done + (sh2_cycles_done(sh2) / 3))\r
257\r
4ea707e1 258#define sh2_reg(c, x) (c) ? ssh2.r[x] : msh2.r[x]\r
259#define sh2_gbr(c) (c) ? ssh2.gbr : msh2.gbr\r
260#define sh2_vbr(c) (c) ? ssh2.vbr : msh2.vbr\r
6add7875 261#define sh2_sr(c) (((c) ? ssh2.sr : msh2.sr) & 0xfff)\r
acd35d4c 262\r
83ff19ec 263#define sh2_set_gbr(c, v) \\r
264 { if (c) ssh2.gbr = v; else msh2.gbr = v; }\r
265#define sh2_set_vbr(c, v) \\r
266 { if (c) ssh2.vbr = v; else msh2.vbr = v; }\r
267\r
f8675e28 268#define elprintf_sh2(sh2, w, f, ...) \\r
269 elprintf(w,"%csh2 "f,(sh2)->is_slave?'s':'m',##__VA_ARGS__)\r
270\r
cc68a136 271// ---------------------------------------------------------\r
272\r
273// main oscillator clock which controls timing\r
274#define OSC_NTSC 53693100\r
b8cbd802 275#define OSC_PAL 53203424\r
cc68a136 276\r
277struct PicoVideo\r
278{\r
279 unsigned char reg[0x20];\r
b8cbd802 280 unsigned int command; // 32-bit Command\r
281 unsigned char pending; // 1 if waiting for second half of 32-bit command\r
282 unsigned char type; // Command type (v/c/vsram read/write)\r
283 unsigned short addr; // Read/Write address\r
284 int status; // Status bits\r
cc68a136 285 unsigned char pending_ints; // pending interrupts: ??VH????\r
b8cbd802 286 signed char lwrite_cnt; // VDP write count during active display line\r
9761a7d0 287 unsigned short v_counter; // V-counter\r
288 unsigned char pad[0x10];\r
cc68a136 289};\r
290\r
291struct PicoMisc\r
292{\r
293 unsigned char rotate;\r
294 unsigned char z80Run;\r
e5503e2f 295 unsigned char padTHPhase[2]; // 02 phase of gamepad TH switches\r
2aa27095 296 unsigned short scanline; // 04 0 to 261||311\r
e5503e2f 297 char dirtyPal; // 06 Is the palette dirty (1 - change @ this frame, 2 - some time before)\r
298 unsigned char hardware; // 07 Hardware value for country\r
299 unsigned char pal; // 08 1=PAL 0=NTSC\r
45f2f245 300 unsigned char sram_reg; // 09 SRAM reg. See SRR_* below\r
e5503e2f 301 unsigned short z80_bank68k; // 0a\r
be2c4208 302 unsigned short pad0;\r
303 unsigned char pad1;\r
0ace9b9a 304 unsigned char z80_reset; // 0f z80 reset held\r
e5503e2f 305 unsigned char padDelay[2]; // 10 gamepad phase time outs, so we count a delay\r
1dceadae 306 unsigned short eeprom_addr; // EEPROM address register\r
45f2f245 307 unsigned char eeprom_cycle; // EEPROM cycle number\r
1dceadae 308 unsigned char eeprom_slave; // EEPROM slave word for X24C02 and better SRAMs\r
45f2f245 309 unsigned char eeprom_status;\r
be2c4208 310 unsigned char pad2;\r
053fd9b4 311 unsigned short dma_xfers; // 18\r
45f2f245 312 unsigned char eeprom_wb[2]; // EEPROM latch/write buffer\r
053fd9b4 313 unsigned int frame_count; // 1c for movies and idle det\r
cc68a136 314};\r
315\r
b4db550e 316struct PicoMS\r
317{\r
318 unsigned char carthw[0x10];\r
319 unsigned char io_ctl;\r
835122bc 320 unsigned char nmi_state;\r
321 unsigned char pad[0x4e];\r
b4db550e 322};\r
323\r
cc68a136 324// some assembly stuff depend on these, do not touch!\r
325struct Pico\r
326{\r
327 unsigned char ram[0x10000]; // 0x00000 scratch ram\r
200772b7 328 union { // vram is byteswapped for easier reads when drawing\r
2ec9bec5 329 unsigned short vram[0x8000]; // 0x10000\r
330 unsigned char vramb[0x4000]; // VRAM in SMS mode\r
331 };\r
cc68a136 332 unsigned char zram[0x2000]; // 0x20000 Z80 ram\r
b4db550e 333 unsigned char ioports[0x10]; // XXX: fix asm and mv\r
334 unsigned char pad[0xf0]; // unused\r
cc68a136 335 unsigned short cram[0x40]; // 0x22100\r
336 unsigned short vsram[0x40]; // 0x22180\r
337\r
338 unsigned char *rom; // 0x22200\r
0219d379 339 unsigned int romsize; // 0x22204 (on 32bits)\r
cc68a136 340\r
341 struct PicoMisc m;\r
342 struct PicoVideo video;\r
b4db550e 343 struct PicoMS ms;\r
cc68a136 344};\r
345\r
346// sram\r
45f2f245 347#define SRR_MAPPED (1 << 0)\r
348#define SRR_READONLY (1 << 1)\r
349\r
350#define SRF_ENABLED (1 << 0)\r
351#define SRF_EEPROM (1 << 1)\r
af37bca8 352\r
cc68a136 353struct PicoSRAM\r
354{\r
4ff2d527 355 unsigned char *data; // actual data\r
356 unsigned int start; // start address in 68k address space\r
cc68a136 357 unsigned int end;\r
45f2f245 358 unsigned char flags; // 0c: SRF_*\r
1dceadae 359 unsigned char unused2;\r
cc68a136 360 unsigned char changed;\r
45f2f245 361 unsigned char eeprom_type; // eeprom type: 0: 7bit (24C01), 2: 2 addr words (X24C02+), 3: 3 addr words\r
362 unsigned char unused3;\r
1dceadae 363 unsigned char eeprom_bit_cl; // bit number for cl\r
364 unsigned char eeprom_bit_in; // bit number for in\r
365 unsigned char eeprom_bit_out; // bit number for out\r
45f2f245 366 unsigned int size;\r
cc68a136 367};\r
368\r
369// MCD\r
370#include "cd/cd_sys.h"\r
371#include "cd/LC89510.h"\r
d1df8786 372#include "cd/gfx_cd.h"\r
cc68a136 373\r
4f265db7 374struct mcd_pcm\r
375{\r
376 unsigned char control; // reg7\r
377 unsigned char enabled; // reg8\r
378 unsigned char cur_ch;\r
379 unsigned char bank;\r
380 int pad1;\r
381\r
4ff2d527 382 struct pcm_chan // 08, size 0x10\r
4f265db7 383 {\r
384 unsigned char regs[8];\r
4ff2d527 385 unsigned int addr; // .08: played sample address\r
4f265db7 386 int pad;\r
387 } ch[8];\r
388};\r
389\r
4fb43555 390#define PCD_ST_S68K_RST 1\r
391\r
c459aefd 392struct mcd_misc\r
393{\r
394 unsigned short hint_vector;\r
4fb43555 395 unsigned char busreq; // not s68k_regs[1]\r
51a902ae 396 unsigned char s68k_pend_ints;\r
bc3c13d3 397 unsigned int state_flags; // 04\r
ae214f1c 398 unsigned int stopwatch_base_c;\r
bc3c13d3 399 unsigned short m68k_poll_a;\r
400 unsigned short m68k_poll_cnt;\r
08769494 401 unsigned short s68k_poll_a;\r
402 unsigned short s68k_poll_cnt;\r
403 unsigned int s68k_poll_clk;\r
6cadc2da 404 unsigned char bcram_reg; // 18: battery-backed RAM cart register\r
ba6e8bfd 405 unsigned char dmna_ret_2m;\r
6cadc2da 406 unsigned short pad3;\r
ae214f1c 407 int pad4[9];\r
c459aefd 408};\r
409\r
cc68a136 410typedef struct\r
411{\r
4ff2d527 412 unsigned char bios[0x20000]; // 000000: 128K\r
413 union { // 020000: 512K\r
fa1e5e29 414 unsigned char prg_ram[0x80000];\r
cc68a136 415 unsigned char prg_ram_b[4][0x20000];\r
416 };\r
4ff2d527 417 union { // 0a0000: 256K\r
fa1e5e29 418 struct {\r
419 unsigned char word_ram2M[0x40000];\r
dca310c4 420 unsigned char unused0[0x20000];\r
fa1e5e29 421 };\r
422 struct {\r
dca310c4 423 unsigned char unused1[0x20000];\r
fa1e5e29 424 unsigned char word_ram1M[2][0x20000];\r
425 };\r
426 };\r
4ff2d527 427 union { // 100000: 64K\r
fa1e5e29 428 unsigned char pcm_ram[0x10000];\r
4f265db7 429 unsigned char pcm_ram_b[0x10][0x1000];\r
430 };\r
895d1512 431 // FIXME: should be short\r
4ff2d527 432 unsigned char s68k_regs[0x200]; // 110000: GA, not CPU regs\r
433 unsigned char bram[0x2000]; // 110200: 8K\r
434 struct mcd_misc m; // 112200: misc\r
435 struct mcd_pcm pcm; // 112240:\r
75736070 436 _scd_toc TOC; // not to be saved\r
cc68a136 437 CDD cdd;\r
438 CDC cdc;\r
439 _scd scd;\r
d1df8786 440 Rot_Comp rot_comp;\r
cc68a136 441} mcd_state;\r
442\r
be2c4208 443// XXX: this will need to be reworked for cart+cd support.\r
cc68a136 444#define Pico_mcd ((mcd_state *)Pico.rom)\r
445\r
be2c4208 446// 32X\r
acd35d4c 447#define P32XS_FM (1<<15)\r
83ff19ec 448#define P32XS_REN (1<< 7)\r
449#define P32XS_nRES (1<< 1)\r
450#define P32XS_ADEN (1<< 0)\r
acd35d4c 451#define P32XS2_ADEN (1<< 9)\r
5e128c6d 452#define P32XS_FULL (1<< 7) // DREQ FIFO full\r
4ea707e1 453#define P32XS_68S (1<< 2)\r
97d3f47f 454#define P32XS_DMA (1<< 1)\r
4ea707e1 455#define P32XS_RV (1<< 0)\r
acd35d4c 456\r
5e128c6d 457#define P32XV_nPAL (1<<15) // VDP\r
acd35d4c 458#define P32XV_PRI (1<< 7)\r
4ea707e1 459#define P32XV_Mx (3<< 0) // display mode mask\r
974fdb5b 460\r
e51e5983 461#define P32XV_SFT (1<< 0)\r
462\r
acd35d4c 463#define P32XV_VBLK (1<<15)\r
464#define P32XV_HBLK (1<<14)\r
465#define P32XV_PEN (1<<13)\r
466#define P32XV_nFEN (1<< 1)\r
467#define P32XV_FS (1<< 0)\r
974fdb5b 468\r
df63f1a6 469#define P32XP_RTP (1<<7) // PWM control\r
470#define P32XP_FULL (1<<15) // PWM pulse\r
db1d3564 471#define P32XP_EMPTY (1<<14)\r
472\r
419973a6 473#define P32XF_68KCPOLL (1 << 0)\r
474#define P32XF_68KVPOLL (1 << 1)\r
475#define P32XF_Z80_32X_IO (1 << 7) // z80 does 32x io\r
4ea707e1 476\r
477#define P32XI_VRES (1 << 14/2) // IRL/2\r
478#define P32XI_VINT (1 << 12/2)\r
479#define P32XI_HINT (1 << 10/2)\r
480#define P32XI_CMD (1 << 8/2)\r
481#define P32XI_PWM (1 << 6/2)\r
482\r
1d7a28a7 483// peripheral reg access\r
484#define PREG8(regs,offs) ((unsigned char *)regs)[offs ^ 3]\r
485\r
7eaa3812 486#define DMAC_FIFO_LEN (4*2)\r
db1d3564 487#define PWM_BUFF_LEN 1024 // in one channel samples\r
266c6afa 488\r
f4bb5d6b 489#define SH2_DRCBLK_RAM_SHIFT 1\r
490#define SH2_DRCBLK_DA_SHIFT 1\r
491\r
f81107f5 492#define SH2_READ_SHIFT 25\r
e05b81fc 493#define SH2_WRITE_SHIFT 25\r
494\r
be2c4208 495struct Pico32x\r
496{\r
497 unsigned short regs[0x20];\r
5a681086 498 unsigned short vdp_regs[0x10]; // 0x40\r
499 unsigned short sh2_regs[3]; // 0x60\r
be2c4208 500 unsigned char pending_fb;\r
974fdb5b 501 unsigned char dirty_pal;\r
266c6afa 502 unsigned int emu_flags;\r
4ea707e1 503 unsigned char sh2irq_mask[2];\r
504 unsigned char sh2irqi[2]; // individual\r
505 unsigned int sh2irqs; // common irqs\r
506 unsigned short dmac_fifo[DMAC_FIFO_LEN];\r
7eaa3812 507 unsigned int pad[4];\r
df63f1a6 508 unsigned int dmac0_fifo_ptr;\r
4a1fb183 509 unsigned short vdp_fbcr_fake;\r
7eaa3812 510 unsigned short pad2;\r
a8fd6e37 511 unsigned char comm_dirty_68k;\r
512 unsigned char comm_dirty_sh2;\r
df63f1a6 513 unsigned char pwm_irq_cnt;\r
514 unsigned char pad1;\r
a7f82a77 515 unsigned short pwm_p[2]; // pwm pos in fifo\r
516 unsigned int pwm_cycle_p; // pwm play cursor (32x cycles)\r
517 unsigned int reserved[6];\r
974fdb5b 518};\r
519\r
520struct Pico32xMem\r
521{\r
522 unsigned char sdram[0x40000];\r
f4bb5d6b 523#ifdef DRC_SH2\r
524 unsigned short drcblk_ram[1 << (18 - SH2_DRCBLK_RAM_SHIFT)];\r
525#endif\r
b78efee2 526 unsigned short dram[2][0x20000/2]; // AKA fb\r
b4db550e 527 union {\r
528 unsigned char m68k_rom[0x100];\r
529 unsigned char m68k_rom_bank[0x10000]; // M68K_BANK_SIZE\r
530 };\r
f4bb5d6b 531#ifdef DRC_SH2\r
532 unsigned short drcblk_da[2][1 << (12 - SH2_DRCBLK_DA_SHIFT)];\r
533#endif\r
895d1512 534 union {\r
535 unsigned char b[0x800];\r
536 unsigned short w[0x800/2];\r
537 } sh2_rom_m;\r
538 union {\r
539 unsigned char b[0x400];\r
540 unsigned short w[0x400/2];\r
541 } sh2_rom_s;\r
974fdb5b 542 unsigned short pal[0x100];\r
5e128c6d 543 unsigned short pal_native[0x100]; // converted to native (for renderer)\r
db1d3564 544 signed short pwm[2*PWM_BUFF_LEN]; // PWM buffer for current frame\r
8ce9c3a7 545 signed short pwm_current[2]; // current converted samples\r
546 unsigned short pwm_fifo[2][4]; // [0] - current raw, others - fifo entries\r
be2c4208 547};\r
d49b10c2 548\r
c8d1e9b6 549// area.c\r
fad24893 550extern void (*PicoLoadStateHook)(void);\r
51a902ae 551\r
945c2fdc 552typedef struct {\r
553 int chunk;\r
554 int size;\r
555 void *ptr;\r
556} carthw_state_chunk;\r
557extern carthw_state_chunk *carthw_chunks;\r
558#define CHUNK_CARTHW 64\r
559\r
c8d1e9b6 560// cart.c\r
b4db550e 561extern int PicoCartResize(int newsize);\r
562extern void Byteswap(void *dst, const void *src, int len);\r
45f2f245 563extern void (*PicoCartMemSetup)(void);\r
e807ac75 564extern void (*PicoCartUnloadHook)(void);\r
1dceadae 565\r
c8d1e9b6 566// debug.c\r
b5e5172d 567int CM_compareRun(int cyc, int is_sub);\r
03e4f2a3 568\r
c8d1e9b6 569// draw.c\r
eff55556 570PICO_INTERNAL void PicoFrameStart(void);\r
b6d7ac70 571void PicoDrawSync(int to, int blank_last_line);\r
200772b7 572void BackFill(int reg7, int sh);\r
5a681086 573void FinalizeLine555(int sh, int line);\r
f4750ee0 574extern int (*PicoScanBegin)(unsigned int num);\r
575extern int (*PicoScanEnd)(unsigned int num);\r
b6d7ac70 576extern int DrawScanline;\r
f579f7b8 577#define MAX_LINE_SPRITES 29\r
578extern unsigned char HighLnSpr[240][3 + MAX_LINE_SPRITES];\r
5a681086 579extern void *DrawLineDestBase;\r
580extern int DrawLineDestIncrement;\r
cc68a136 581\r
c8d1e9b6 582// draw2.c\r
eff55556 583PICO_INTERNAL void PicoFrameFull();\r
cc68a136 584\r
200772b7 585// mode4.c\r
586void PicoFrameStartMode4(void);\r
587void PicoLineMode4(int line);\r
588void PicoDoHighPal555M4(void);\r
5a681086 589void PicoDrawSetOutputMode4(pdso_t which);\r
200772b7 590\r
c8d1e9b6 591// memory.c\r
eff55556 592PICO_INTERNAL void PicoMemSetup(void);\r
af37bca8 593unsigned int PicoRead8_io(unsigned int a);\r
594unsigned int PicoRead16_io(unsigned int a);\r
595void PicoWrite8_io(unsigned int a, unsigned int d);\r
596void PicoWrite16_io(unsigned int a, unsigned int d);\r
597\r
598// pico/memory.c\r
599PICO_INTERNAL void PicoMemSetupPico(void);\r
cc68a136 600\r
c8d1e9b6 601// cd/memory.c\r
eff55556 602PICO_INTERNAL void PicoMemSetupCD(void);\r
ae214f1c 603void pcd_state_loaded_mem(void);\r
cc68a136 604\r
c8d1e9b6 605// pico.c\r
cc68a136 606extern struct Pico Pico;\r
607extern struct PicoSRAM SRam;\r
5f9a0d16 608extern int PicoPadInt[2];\r
cc68a136 609extern int emustatus;\r
5e128c6d 610extern int scanlines_total;\r
f8ef8ff7 611extern void (*PicoResetHook)(void);\r
b0677887 612extern void (*PicoLineHook)(void);\r
1e6b5e39 613PICO_INTERNAL int CheckDMA(void);\r
614PICO_INTERNAL void PicoDetectRegion(void);\r
ae214f1c 615PICO_INTERNAL void PicoSyncZ80(unsigned int m68k_cycles_done);\r
cc68a136 616\r
89dbbf2b 617// cd/mcd.c\r
ae214f1c 618#define PCDS_IEN1 (1<<1)\r
619#define PCDS_IEN2 (1<<2)\r
620#define PCDS_IEN3 (1<<3)\r
621#define PCDS_IEN4 (1<<4)\r
622#define PCDS_IEN5 (1<<5)\r
623#define PCDS_IEN6 (1<<6)\r
cc68a136 624\r
2aa27095 625PICO_INTERNAL void PicoInitMCD(void);\r
e5f426aa 626PICO_INTERNAL void PicoExitMCD(void);\r
1cb1584b 627PICO_INTERNAL void PicoPowerMCD(void);\r
2aa27095 628PICO_INTERNAL int PicoResetMCD(void);\r
629PICO_INTERNAL void PicoFrameMCD(void);\r
cc68a136 630\r
ae214f1c 631enum pcd_event {\r
632 PCD_EVENT_CDC,\r
633 PCD_EVENT_TIMER3,\r
634 PCD_EVENT_GFX,\r
635 PCD_EVENT_DMA,\r
636 PCD_EVENT_COUNT,\r
637};\r
638extern unsigned int pcd_event_times[PCD_EVENT_COUNT];\r
639void pcd_event_schedule(unsigned int now, enum pcd_event event, int after);\r
640void pcd_event_schedule_s68k(enum pcd_event event, int after);\r
641unsigned int pcd_cycles_m68k_to_s68k(unsigned int c);\r
08769494 642int pcd_sync_s68k(unsigned int m68k_target, int m68k_poll_sync);\r
ae214f1c 643void pcd_state_loaded(void);\r
644\r
c8d1e9b6 645// pico/pico.c\r
2aa27095 646PICO_INTERNAL void PicoInitPico(void);\r
ed367a3f 647PICO_INTERNAL void PicoReratePico(void);\r
9037e45d 648\r
c8d1e9b6 649// pico/xpcm.c\r
ef4eb506 650PICO_INTERNAL void PicoPicoPCMUpdate(short *buffer, int length, int stereo);\r
651PICO_INTERNAL void PicoPicoPCMReset(void);\r
213c16ad 652PICO_INTERNAL void PicoPicoPCMRerate(int xpcm_rate);\r
ef4eb506 653\r
c8d1e9b6 654// sek.c\r
2aa27095 655PICO_INTERNAL void SekInit(void);\r
656PICO_INTERNAL int SekReset(void);\r
3aa1e148 657PICO_INTERNAL void SekState(int *data);\r
eff55556 658PICO_INTERNAL void SekSetRealTAS(int use_real);\r
b4db550e 659PICO_INTERNAL void SekPackCpu(unsigned char *cpu, int is_sub);\r
660PICO_INTERNAL void SekUnpackCpu(const unsigned char *cpu, int is_sub);\r
5f9a0d16 661void SekStepM68k(void);\r
053fd9b4 662void SekInitIdleDet(void);\r
663void SekFinishIdleDet(void);\r
12da51c2 664#if defined(CPU_CMP_R) || defined(CPU_CMP_W)\r
665void SekTrace(int is_s68k);\r
666#else\r
667#define SekTrace(x)\r
668#endif\r
cc68a136 669\r
c8d1e9b6 670// cd/sek.c\r
2aa27095 671PICO_INTERNAL void SekInitS68k(void);\r
672PICO_INTERNAL int SekResetS68k(void);\r
673PICO_INTERNAL int SekInterruptS68k(int irq);\r
cc68a136 674\r
7a93adeb 675// sound/sound.c\r
c9e1affc 676PICO_INTERNAL void cdda_start_play();\r
677extern short cdda_out_buffer[2*1152];\r
7a93adeb 678extern int PsndLen_exc_cnt;\r
679extern int PsndLen_exc_add;\r
48dc74f2 680extern int timer_a_next_oflow, timer_a_step; // in z80 cycles\r
681extern int timer_b_next_oflow, timer_b_step;\r
43e6eaad 682\r
683void ym2612_sync_timers(int z80_cycles, int mode_old, int mode_new);\r
d2721b08 684void ym2612_pack_state(void);\r
453d2a6e 685void ym2612_unpack_state(void);\r
4b9c5888 686\r
e53704e6 687#define TIMER_NO_OFLOW 0x70000000\r
45a1ef71 688// tA = 72 * (1024 - NA) / M\r
689#define TIMER_A_TICK_ZCYCLES 17203\r
690// tB = 1152 * (256 - NA) / M\r
691#define TIMER_B_TICK_ZCYCLES 262800 // 275251 broken, see Dai Makaimura\r
e53704e6 692\r
4b9c5888 693#define timers_cycle() \\r
e53704e6 694 if (timer_a_next_oflow > 0 && timer_a_next_oflow < TIMER_NO_OFLOW) \\r
43e6eaad 695 timer_a_next_oflow -= Pico.m.pal ? 70938*256 : 59659*256; \\r
e53704e6 696 if (timer_b_next_oflow > 0 && timer_b_next_oflow < TIMER_NO_OFLOW) \\r
43e6eaad 697 timer_b_next_oflow -= Pico.m.pal ? 70938*256 : 59659*256; \\r
698 ym2612_sync_timers(0, ym2612.OPN.ST.mode, ym2612.OPN.ST.mode);\r
4b9c5888 699\r
700#define timers_reset() \\r
e53704e6 701 timer_a_next_oflow = timer_b_next_oflow = TIMER_NO_OFLOW; \\r
48dc74f2 702 timer_a_step = TIMER_A_TICK_ZCYCLES * 1024; \\r
703 timer_b_step = TIMER_B_TICK_ZCYCLES * 256;\r
43e6eaad 704\r
7a93adeb 705\r
c8d1e9b6 706// videoport.c\r
eff55556 707PICO_INTERNAL_ASM void PicoVideoWrite(unsigned int a,unsigned short d);\r
708PICO_INTERNAL_ASM unsigned int PicoVideoRead(unsigned int a);\r
9761a7d0 709PICO_INTERNAL_ASM unsigned int PicoVideoRead8(unsigned int a);\r
5de27868 710extern int (*PicoDmaHook)(unsigned int source, int len, unsigned short **srcp, unsigned short **limitp);\r
cc68a136 711\r
c8d1e9b6 712// misc.c\r
eff55556 713PICO_INTERNAL_ASM void memcpy16(unsigned short *dest, unsigned short *src, int count);\r
714PICO_INTERNAL_ASM void memcpy16bswap(unsigned short *dest, void *src, int count);\r
715PICO_INTERNAL_ASM void memcpy32(int *dest, int *src, int count); // 32bit word count\r
716PICO_INTERNAL_ASM void memset32(int *dest, int c, int count);\r
cc68a136 717\r
45f2f245 718// eeprom.c\r
719void EEPROM_write8(unsigned int a, unsigned int d);\r
720void EEPROM_write16(unsigned int d);\r
721unsigned int EEPROM_read(void);\r
722\r
c8d1e9b6 723// z80 functionality wrappers\r
724PICO_INTERNAL void z80_init(void);\r
b4db550e 725PICO_INTERNAL void z80_pack(void *data);\r
726PICO_INTERNAL int z80_unpack(const void *data);\r
c8d1e9b6 727PICO_INTERNAL void z80_reset(void);\r
728PICO_INTERNAL void z80_exit(void);\r
c8d1e9b6 729\r
730// cd/misc.c\r
eff55556 731PICO_INTERNAL_ASM void wram_2M_to_1M(unsigned char *m);\r
732PICO_INTERNAL_ASM void wram_1M_to_2M(unsigned char *m);\r
733\r
734// cd/buffering.c\r
735PICO_INTERNAL void PicoCDBufferRead(void *dest, int lba);\r
736\r
737// sound/sound.c\r
9d917eea 738PICO_INTERNAL void PsndReset(void);\r
4b9c5888 739PICO_INTERNAL void PsndDoDAC(int line_to);\r
9d917eea 740PICO_INTERNAL void PsndClear(void);\r
7b3f44c6 741PICO_INTERNAL void PsndGetSamples(int y);\r
2ec9bec5 742PICO_INTERNAL void PsndGetSamplesMS(void);\r
4b9c5888 743extern int PsndDacLine;\r
cc68a136 744\r
3e49ffd0 745// sms.c\r
f3a57b2d 746#ifndef NO_SMS\r
3e49ffd0 747void PicoPowerMS(void);\r
2ec9bec5 748void PicoResetMS(void);\r
3e49ffd0 749void PicoMemSetupMS(void);\r
b4db550e 750void PicoStateLoadedMS(void);\r
3e49ffd0 751void PicoFrameMS(void);\r
87b0845f 752void PicoFrameDrawOnlyMS(void);\r
f3a57b2d 753#else\r
754#define PicoPowerMS()\r
755#define PicoResetMS()\r
756#define PicoMemSetupMS()\r
757#define PicoStateLoadedMS()\r
758#define PicoFrameMS()\r
759#define PicoFrameDrawOnlyMS()\r
760#endif\r
3e49ffd0 761\r
be2c4208 762// 32x/32x.c\r
f3a57b2d 763#ifndef NO_32X\r
be2c4208 764extern struct Pico32x Pico32x;\r
6a98f03e 765enum p32x_event {\r
766 P32X_EVENT_PWM,\r
767 P32X_EVENT_FILLEND,\r
5ac99d9a 768 P32X_EVENT_HINT,\r
6a98f03e 769 P32X_EVENT_COUNT,\r
770};\r
ae214f1c 771extern unsigned int p32x_event_times[P32X_EVENT_COUNT];\r
6a98f03e 772\r
be2c4208 773void Pico32xInit(void);\r
974fdb5b 774void PicoPower32x(void);\r
be2c4208 775void PicoReset32x(void);\r
974fdb5b 776void Pico32xStartup(void);\r
5e49c3a8 777void PicoUnload32x(void);\r
974fdb5b 778void PicoFrame32x(void);\r
27e26273 779void Pico32xStateLoaded(int is_early);\r
ed4402a7 780void p32x_sync_sh2s(unsigned int m68k_target);\r
19886062 781void p32x_sync_other_sh2(SH2 *sh2, unsigned int m68k_target);\r
4d5dfee8 782void p32x_update_irls(SH2 *active_sh2, int m68k_cycles);\r
9e1fa0a6 783void p32x_trigger_irq(SH2 *sh2, int m68k_cycles, unsigned int mask);\r
784void p32x_update_cmd_irq(SH2 *sh2, int m68k_cycles);\r
83ff19ec 785void p32x_reset_sh2s(void);\r
19886062 786void p32x_event_schedule(unsigned int now, enum p32x_event event, int after);\r
787void p32x_event_schedule_sh2(SH2 *sh2, enum p32x_event event, int after);\r
5ac99d9a 788void p32x_schedule_hint(SH2 *sh2, int m68k_cycles);\r
a8fd6e37 789\r
be2c4208 790// 32x/memory.c\r
974fdb5b 791struct Pico32xMem *Pico32xMem;\r
be2c4208 792unsigned int PicoRead8_32x(unsigned int a);\r
793unsigned int PicoRead16_32x(unsigned int a);\r
794void PicoWrite8_32x(unsigned int a, unsigned int d);\r
795void PicoWrite16_32x(unsigned int a, unsigned int d);\r
796void PicoMemSetup32x(void);\r
974fdb5b 797void Pico32xSwapDRAM(int b);\r
27e26273 798void Pico32xMemStateLoaded(void);\r
19886062 799void p32x_m68k_poll_event(unsigned int flags);\r
800void p32x_sh2_poll_event(SH2 *sh2, unsigned int flags, unsigned int m68k_cycles);\r
974fdb5b 801\r
802// 32x/draw.c\r
41946d70 803void PicoDrawSetOutFormat32x(pdso_t which, int use_32x_line_mode);\r
974fdb5b 804void FinalizeLine32xRGB555(int sh, int line);\r
5a681086 805void PicoDraw32xLayer(int offs, int lines, int mdbg);\r
7a961c19 806void PicoDraw32xLayerMdOnly(int offs, int lines);\r
f4750ee0 807extern int (*PicoScan32xBegin)(unsigned int num);\r
808extern int (*PicoScan32xEnd)(unsigned int num);\r
7a961c19 809enum {\r
810 PDM32X_OFF,\r
811 PDM32X_32X_ONLY,\r
812 PDM32X_BOTH,\r
813};\r
5a681086 814extern int Pico32xDrawMode;\r
be2c4208 815\r
db1d3564 816// 32x/pwm.c\r
c1931173 817unsigned int p32x_pwm_read16(unsigned int a, SH2 *sh2,\r
818 unsigned int m68k_cycles);\r
819void p32x_pwm_write16(unsigned int a, unsigned int d,\r
820 SH2 *sh2, unsigned int m68k_cycles);\r
db1d3564 821void p32x_pwm_update(int *buf32, int length, int stereo);\r
045a4c52 822void p32x_pwm_ctl_changed(void);\r
df63f1a6 823void p32x_pwm_schedule(unsigned int m68k_now);\r
19886062 824void p32x_pwm_schedule_sh2(SH2 *sh2);\r
9e1fa0a6 825void p32x_pwm_sync_to_sh2(SH2 *sh2);\r
df63f1a6 826void p32x_pwm_irq_event(unsigned int m68k_now);\r
827void p32x_pwm_state_loaded(void);\r
045a4c52 828\r
829// 32x/sh2soc.c\r
830void p32x_dreq0_trigger(void);\r
831void p32x_dreq1_trigger(void);\r
832void p32x_timers_recalc(void);\r
833void p32x_timers_do(unsigned int m68k_slice);\r
cd0ace28 834void sh2_peripheral_reset(SH2 *sh2);\r
f81107f5 835unsigned int sh2_peripheral_read8(unsigned int a, SH2 *sh2);\r
836unsigned int sh2_peripheral_read16(unsigned int a, SH2 *sh2);\r
837unsigned int sh2_peripheral_read32(unsigned int a, SH2 *sh2);\r
8b43bc73 838void REGPARM(3) sh2_peripheral_write8(unsigned int a, unsigned int d, SH2 *sh2);\r
839void REGPARM(3) sh2_peripheral_write16(unsigned int a, unsigned int d, SH2 *sh2);\r
840void REGPARM(3) sh2_peripheral_write32(unsigned int a, unsigned int d, SH2 *sh2);\r
045a4c52 841\r
f3a57b2d 842#else\r
843#define Pico32xInit()\r
844#define PicoPower32x()\r
845#define PicoReset32x()\r
846#define PicoFrame32x()\r
847#define PicoUnload32x()\r
848#define Pico32xStateLoaded()\r
f3a57b2d 849#define FinalizeLine32xRGB555 NULL\r
850#define p32x_pwm_update(...)\r
851#define p32x_timers_recalc()\r
852#endif\r
db1d3564 853\r
45f2f245 854/* avoid dependency on newer glibc */\r
855static __inline int isspace_(int c)\r
856{\r
857 return (0x09 <= c && c <= 0x0d) || c == ' ';\r
858}\r
859\r
f4bb5d6b 860#ifndef ARRAY_SIZE\r
861#define ARRAY_SIZE(x) (sizeof(x) / sizeof(x[0]))\r
862#endif\r
863\r
b8cbd802 864// emulation event logging\r
865#ifndef EL_LOGMASK\r
9c9cda8c 866# ifdef __x86_64__ // HACK\r
867# define EL_LOGMASK (EL_STATUS|EL_IDLE|EL_ANOMALY)\r
868# else\r
1555935b 869# define EL_LOGMASK (EL_STATUS)\r
9c9cda8c 870# endif\r
b8cbd802 871#endif\r
872\r
017512f2 873#define EL_HVCNT 0x00000001 /* hv counter reads */\r
874#define EL_SR 0x00000002 /* SR reads */\r
875#define EL_INTS 0x00000004 /* ints and acks */\r
43e6eaad 876#define EL_YMTIMER 0x00000008 /* ym2612 timer stuff */\r
017512f2 877#define EL_INTSW 0x00000010 /* log irq switching on/off */\r
878#define EL_ASVDP 0x00000020 /* VDP accesses during active scan */\r
879#define EL_VDPDMA 0x00000040 /* VDP DMA transfers and their timing */\r
880#define EL_BUSREQ 0x00000080 /* z80 busreq r/w or reset w */\r
881#define EL_Z80BNK 0x00000100 /* z80 i/o through bank area */\r
882#define EL_SRAMIO 0x00000200 /* sram i/o */\r
883#define EL_EEPROM 0x00000400 /* eeprom debug */\r
884#define EL_UIO 0x00000800 /* unmapped i/o */\r
885#define EL_IO 0x00001000 /* all i/o */\r
886#define EL_CDPOLL 0x00002000 /* MCD: log poll detection */\r
887#define EL_SVP 0x00004000 /* SVP stuff */\r
fa22af4c 888#define EL_PICOHW 0x00008000 /* Pico stuff */\r
053fd9b4 889#define EL_IDLE 0x00010000 /* idle loop det. */\r
af37bca8 890#define EL_CDREGS 0x00020000 /* MCD: register access */\r
891#define EL_CDREG3 0x00040000 /* MCD: register 3 only */\r
be2c4208 892#define EL_32X 0x00080000\r
1b3f5844 893#define EL_PWM 0x00100000 /* 32X PWM stuff (LOTS of output) */\r
045a4c52 894#define EL_32XP 0x00200000 /* 32X peripherals */\r
ae214f1c 895#define EL_CD 0x00400000 /* MCD */\r
017512f2 896\r
897#define EL_STATUS 0x40000000 /* status messages */\r
898#define EL_ANOMALY 0x80000000 /* some unexpected conditions (during emulation) */\r
b8cbd802 899\r
900#if EL_LOGMASK\r
901#define elprintf(w,f,...) \\r
a8fd6e37 902do { \\r
b8cbd802 903 if ((w) & EL_LOGMASK) \\r
7d0143a2 904 lprintf("%05i:%03i: " f "\n",Pico.m.frame_count,Pico.m.scanline,##__VA_ARGS__); \\r
a8fd6e37 905} while (0)\r
dca310c4 906#elif defined(_MSC_VER)\r
907#define elprintf\r
b8cbd802 908#else\r
909#define elprintf(w,f,...)\r
910#endif\r
911\r
f6c49d38 912// profiling\r
913#ifdef PPROF\r
914#include <platform/linux/pprof.h>\r
915#else\r
916#define pprof_init()\r
917#define pprof_finish()\r
918#define pprof_start(x)\r
919#define pprof_end(...)\r
920#define pprof_end_sub(...)\r
921#endif\r
922\r
19886062 923#ifdef EVT_LOG\r
924enum evt {\r
925 EVT_FRAME_START,\r
926 EVT_NEXT_LINE,\r
927 EVT_RUN_START,\r
928 EVT_RUN_END,\r
929 EVT_POLL_START,\r
930 EVT_POLL_END,\r
931 EVT_CNT\r
932};\r
933\r
934enum evt_cpu {\r
935 EVT_M68K,\r
936 EVT_S68K,\r
937 EVT_MSH2,\r
938 EVT_SSH2,\r
939 EVT_CPU_CNT\r
940};\r
941\r
942void pevt_log(unsigned int cycles, enum evt_cpu c, enum evt e);\r
943void pevt_dump(void);\r
944\r
945#define pevt_log_m68k(e) \\r
08769494 946 pevt_log(SekCyclesDone(), EVT_M68K, e)\r
19886062 947#define pevt_log_m68k_o(e) \\r
08769494 948 pevt_log(SekCyclesDone(), EVT_M68K, e)\r
19886062 949#define pevt_log_sh2(sh2, e) \\r
950 pevt_log(sh2_cycles_done_m68k(sh2), EVT_MSH2 + (sh2)->is_slave, e)\r
951#define pevt_log_sh2_o(sh2, e) \\r
952 pevt_log((sh2)->m68krcycles_done, EVT_MSH2 + (sh2)->is_slave, e)\r
953#else\r
954#define pevt_log(c, e)\r
955#define pevt_log_m68k(e)\r
956#define pevt_log_m68k_o(e)\r
957#define pevt_log_sh2(sh2, e)\r
958#define pevt_log_sh2_o(sh2, e)\r
959#define pevt_dump()\r
960#endif\r
961\r
f6c49d38 962// misc\r
dca310c4 963#ifdef _MSC_VER\r
964#define cdprintf\r
965#else\r
966#define cdprintf(x...)\r
967#endif\r
968\r
8b43bc73 969#if defined(__GNUC__) && defined(__i386__)\r
553c3eaa 970#define REGPARM(x) __attribute__((regparm(x)))\r
c8d1e9b6 971#else\r
553c3eaa 972#define REGPARM(x)\r
c8d1e9b6 973#endif\r
974\r
5e89f0f5 975#ifdef __GNUC__\r
976#define NOINLINE __attribute__((noinline))\r
977#else\r
978#define NOINLINE\r
979#endif\r
980\r
f8af9634 981#ifdef __cplusplus\r
982} // End of extern "C"\r
983#endif\r
984\r
eff55556 985#endif // PICO_INTERNAL_INCLUDED\r
986\r
fast MegaDrive/MegaCD/32X emulator