cff531af |
1 | /*\r |
2 | * PicoDrive - Internal Header File\r |
3 | * (c) Copyright Dave, 2004\r |
4 | * (C) notaz, 2006-2010\r |
5 | *\r |
6 | * This work is licensed under the terms of MAME license.\r |
7 | * See COPYING file in the top-level directory.\r |
8 | */\r |
cc68a136 |
9 | \r |
eff55556 |
10 | #ifndef PICO_INTERNAL_INCLUDED\r |
11 | #define PICO_INTERNAL_INCLUDED\r |
cc68a136 |
12 | #include <stdio.h>\r |
cc68a136 |
13 | #include <string.h>\r |
f821bb70 |
14 | #include "pico_types.h"\r |
bce14421 |
15 | #include "pico_port.h"\r |
efcba75f |
16 | #include "pico.h"\r |
f53f286a |
17 | #include "carthw/carthw.h"\r |
cc68a136 |
18 | \r |
89fa852d |
19 | //\r |
20 | #define USE_POLL_DETECT\r |
21 | \r |
eff55556 |
22 | #ifndef PICO_INTERNAL\r |
23 | #define PICO_INTERNAL\r |
24 | #endif\r |
25 | #ifndef PICO_INTERNAL_ASM\r |
26 | #define PICO_INTERNAL_ASM\r |
27 | #endif\r |
cc68a136 |
28 | \r |
70357ce5 |
29 | // to select core, define EMU_C68K, EMU_M68K or EMU_F68K in your makefile or project\r |
cc68a136 |
30 | \r |
31 | #ifdef __cplusplus\r |
32 | extern "C" {\r |
33 | #endif\r |
34 | \r |
cc68a136 |
35 | // ----------------------- 68000 CPU -----------------------\r |
36 | #ifdef EMU_C68K\r |
f821bb70 |
37 | #include <cpu/cyclone/Cyclone.h>\r |
3aa1e148 |
38 | extern struct Cyclone PicoCpuCM68k, PicoCpuCS68k;\r |
ae214f1c |
39 | #define SekCyclesLeft PicoCpuCM68k.cycles // cycles left for this run\r |
40 | #define SekCyclesLeftS68k PicoCpuCS68k.cycles\r |
3aa1e148 |
41 | #define SekPc (PicoCpuCM68k.pc-PicoCpuCM68k.membase)\r |
42 | #define SekPcS68k (PicoCpuCS68k.pc-PicoCpuCS68k.membase)\r |
12da51c2 |
43 | #define SekDar(x) (x < 8 ? PicoCpuCM68k.d[x] : PicoCpuCM68k.a[x - 8])\r |
44 | #define SekDarS68k(x) (x < 8 ? PicoCpuCS68k.d[x] : PicoCpuCS68k.a[x - 8])\r |
5fadfb1c |
45 | #define SekSr CycloneGetSr(&PicoCpuCM68k)\r |
12da51c2 |
46 | #define SekSrS68k CycloneGetSr(&PicoCpuCS68k)\r |
805fbe6f |
47 | #define SekSetStop(x) { PicoCpuCM68k.state_flags&=~1; if (x) { PicoCpuCM68k.state_flags|=1; SekEndRun(0); } }\r |
48 | #define SekSetStopS68k(x) { PicoCpuCS68k.state_flags&=~1; if (x) { PicoCpuCS68k.state_flags|=1; SekEndRunS68k(0); } }\r |
ed4402a7 |
49 | #define SekIsStoppedM68k() (PicoCpuCM68k.state_flags&1)\r |
ca61ee42 |
50 | #define SekIsStoppedS68k() (PicoCpuCS68k.state_flags&1)\r |
08769494 |
51 | #define SekShouldInterrupt() (PicoCpuCM68k.irq > (PicoCpuCM68k.srh&7))\r |
b542be46 |
52 | \r |
ecc8036e |
53 | #define SekNotPolling PicoCpuCM68k.not_pol\r |
54 | #define SekNotPollingS68k PicoCpuCS68k.not_pol\r |
55 | \r |
b542be46 |
56 | #define SekInterrupt(i) PicoCpuCM68k.irq=i\r |
5fadfb1c |
57 | #define SekIrqLevel PicoCpuCM68k.irq\r |
b542be46 |
58 | \r |
cc68a136 |
59 | #endif\r |
60 | \r |
70357ce5 |
61 | #ifdef EMU_F68K\r |
f821bb70 |
62 | #include <cpu/fame/fame.h>\r |
b542be46 |
63 | extern M68K_CONTEXT PicoCpuFM68k, PicoCpuFS68k;\r |
ae214f1c |
64 | #define SekCyclesLeft PicoCpuFM68k.io_cycle_counter\r |
65 | #define SekCyclesLeftS68k PicoCpuFS68k.io_cycle_counter\r |
03e4f2a3 |
66 | #define SekPc fm68k_get_pc(&PicoCpuFM68k)\r |
67 | #define SekPcS68k fm68k_get_pc(&PicoCpuFS68k)\r |
12da51c2 |
68 | #define SekDar(x) (x < 8 ? PicoCpuFM68k.dreg[x].D : PicoCpuFM68k.areg[x - 8].D)\r |
69 | #define SekDarS68k(x) (x < 8 ? PicoCpuFS68k.dreg[x].D : PicoCpuFS68k.areg[x - 8].D)\r |
5fadfb1c |
70 | #define SekSr PicoCpuFM68k.sr\r |
12da51c2 |
71 | #define SekSrS68k PicoCpuFS68k.sr\r |
70357ce5 |
72 | #define SekSetStop(x) { \\r |
03e4f2a3 |
73 | PicoCpuFM68k.execinfo &= ~FM68K_HALTED; \\r |
805fbe6f |
74 | if (x) { PicoCpuFM68k.execinfo |= FM68K_HALTED; SekEndRun(0); } \\r |
70357ce5 |
75 | }\r |
76 | #define SekSetStopS68k(x) { \\r |
03e4f2a3 |
77 | PicoCpuFS68k.execinfo &= ~FM68K_HALTED; \\r |
805fbe6f |
78 | if (x) { PicoCpuFS68k.execinfo |= FM68K_HALTED; SekEndRunS68k(0); } \\r |
70357ce5 |
79 | }\r |
ed4402a7 |
80 | #define SekIsStoppedM68k() (PicoCpuFM68k.execinfo&FM68K_HALTED)\r |
ca61ee42 |
81 | #define SekIsStoppedS68k() (PicoCpuFS68k.execinfo&FM68K_HALTED)\r |
12f23dac |
82 | #define SekShouldInterrupt() fm68k_would_interrupt(&PicoCpuFM68k)\r |
b542be46 |
83 | \r |
ecc8036e |
84 | #define SekNotPolling PicoCpuFM68k.not_polling\r |
85 | #define SekNotPollingS68k PicoCpuFS68k.not_polling\r |
86 | \r |
b542be46 |
87 | #define SekInterrupt(irq) PicoCpuFM68k.interrupts[0]=irq\r |
5fadfb1c |
88 | #define SekIrqLevel PicoCpuFM68k.interrupts[0]\r |
b542be46 |
89 | \r |
cc68a136 |
90 | #endif\r |
91 | \r |
92 | #ifdef EMU_M68K\r |
f821bb70 |
93 | #include <cpu/musashi/m68kcpu.h>\r |
5adcc165 |
94 | #undef INLINE\r |
95 | #undef USE_CYCLES\r |
96 | #undef ADD_CYCLES\r |
3aa1e148 |
97 | extern m68ki_cpu_core PicoCpuMM68k, PicoCpuMS68k;\r |
cc68a136 |
98 | #ifndef SekCyclesLeft\r |
ae214f1c |
99 | #define SekCyclesLeft PicoCpuMM68k.cyc_remaining_cycles\r |
100 | #define SekCyclesLeftS68k PicoCpuMS68k.cyc_remaining_cycles\r |
3aa1e148 |
101 | #define SekPc m68k_get_reg(&PicoCpuMM68k, M68K_REG_PC)\r |
102 | #define SekPcS68k m68k_get_reg(&PicoCpuMS68k, M68K_REG_PC)\r |
12da51c2 |
103 | #define SekDar(x) PicoCpuMM68k.dar[x]\r |
104 | #define SekDarS68k(x) PicoCpuMS68k.dar[x]\r |
105 | #define SekSr m68k_get_reg(&PicoCpuMM68k, M68K_REG_SR)\r |
106 | #define SekSrS68k m68k_get_reg(&PicoCpuMS68k, M68K_REG_SR)\r |
7a1f6e45 |
107 | #define SekSetStop(x) { \\r |
805fbe6f |
108 | if(x) { PicoCpuMM68k.stopped=STOP_LEVEL_STOP; SekEndRun(0)} \\r |
3aa1e148 |
109 | else PicoCpuMM68k.stopped=0; \\r |
7a1f6e45 |
110 | }\r |
111 | #define SekSetStopS68k(x) { \\r |
805fbe6f |
112 | if(x) { PicoCpuMS68k.stopped=STOP_LEVEL_STOP; SekEndRunS68k(0); } \\r |
3aa1e148 |
113 | else PicoCpuMS68k.stopped=0; \\r |
7a1f6e45 |
114 | }\r |
ed4402a7 |
115 | #define SekIsStoppedM68k() (PicoCpuMM68k.stopped==STOP_LEVEL_STOP)\r |
ca61ee42 |
116 | #define SekIsStoppedS68k() (PicoCpuMS68k.stopped==STOP_LEVEL_STOP)\r |
5e04c2f3 |
117 | #define SekShouldInterrupt() (PicoCpuMM68k.int_level > PicoCpuMM68k.int_mask)\r |
b542be46 |
118 | \r |
ecc8036e |
119 | #define SekNotPolling PicoCpuMM68k.not_polling\r |
120 | #define SekNotPollingS68k PicoCpuMS68k.not_polling\r |
121 | \r |
22814963 |
122 | // avoid m68k_set_irq() for delaying to work\r |
123 | #define SekInterrupt(irq) PicoCpuMM68k.int_level = (irq) << 8\r |
124 | #define SekIrqLevel (PicoCpuMM68k.int_level >> 8)\r |
b542be46 |
125 | \r |
cc68a136 |
126 | #endif\r |
ef090115 |
127 | #endif // EMU_M68K\r |
cc68a136 |
128 | \r |
ae214f1c |
129 | // number of cycles done (can be checked anywhere)\r |
88fd63ad |
130 | #define SekCyclesDone() (Pico.t.m68c_cnt - SekCyclesLeft)\r |
ae214f1c |
131 | \r |
132 | // burn cycles while not in SekRun() and while in\r |
88fd63ad |
133 | #define SekCyclesBurn(c) Pico.t.m68c_cnt += c\r |
1259ac4f |
134 | #define SekCyclesBurnRun(c) SekCyclesLeft -= c\r |
cc68a136 |
135 | \r |
ae214f1c |
136 | // note: sometimes may extend timeslice to delay an irq\r |
b02b3923 |
137 | #define SekEndRun(after) if (SekCyclesLeft > (after)) { \\r |
88fd63ad |
138 | Pico.t.m68c_cnt -= SekCyclesLeft - (after); \\r |
ae214f1c |
139 | SekCyclesLeft = after; \\r |
cc68a136 |
140 | }\r |
141 | \r |
ae214f1c |
142 | extern unsigned int SekCycleCntS68k;\r |
143 | extern unsigned int SekCycleAimS68k;\r |
144 | \r |
07ceafdb |
145 | #define SekEndRunS68k(after) { \\r |
ae214f1c |
146 | if (SekCyclesLeftS68k > (after)) { \\r |
147 | SekCycleCntS68k -= SekCyclesLeftS68k - (after); \\r |
148 | SekCyclesLeftS68k = after; \\r |
149 | } \\r |
07ceafdb |
150 | }\r |
151 | \r |
ae214f1c |
152 | #define SekCyclesDoneS68k() (SekCycleCntS68k - SekCyclesLeftS68k)\r |
cc68a136 |
153 | \r |
ae214f1c |
154 | // compare cycles, handling overflows\r |
155 | // check if a > b\r |
156 | #define CYCLES_GT(a, b) \\r |
157 | ((int)((a) - (b)) > 0)\r |
158 | // check if a >= b\r |
159 | #define CYCLES_GE(a, b) \\r |
160 | ((int)((a) - (b)) >= 0)\r |
cc68a136 |
161 | \r |
b542be46 |
162 | // ----------------------- Z80 CPU -----------------------\r |
163 | \r |
b4db550e |
164 | #if defined(_USE_DRZ80)\r |
f821bb70 |
165 | #include <cpu/DrZ80/drz80.h>\r |
b542be46 |
166 | \r |
167 | extern struct DrZ80 drZ80;\r |
168 | \r |
169 | #define z80_run(cycles) ((cycles) - DrZ80Run(&drZ80, cycles))\r |
170 | #define z80_run_nr(cycles) DrZ80Run(&drZ80, cycles)\r |
4936aac1 |
171 | #define z80_int() drZ80.Z80_IRQ = 1\r |
ad43165a |
172 | #define z80_int_assert(a) drZ80.Z80_IRQ = (a ? 2 : 0)\r |
835122bc |
173 | #define z80_nmi() drZ80.Z80IF |= 8\r |
4b9c5888 |
174 | \r |
175 | #define z80_cyclesLeft drZ80.cycles\r |
d1b8bcc6 |
176 | #define z80_subCLeft(c) drZ80.cycles -= c\r |
19954be1 |
177 | #define z80_pc() (drZ80.Z80PC - drZ80.Z80PC_BASE)\r |
b542be46 |
178 | \r |
179 | #elif defined(_USE_CZ80)\r |
f821bb70 |
180 | #include <cpu/cz80/cz80.h>\r |
b542be46 |
181 | \r |
182 | #define z80_run(cycles) Cz80_Exec(&CZ80, cycles)\r |
183 | #define z80_run_nr(cycles) Cz80_Exec(&CZ80, cycles)\r |
184 | #define z80_int() Cz80_Set_IRQ(&CZ80, 0, HOLD_LINE)\r |
cf83610b |
185 | #define z80_int_assert(a) Cz80_Set_IRQ(&CZ80, 0, (a) ? ASSERT_LINE : CLEAR_LINE)\r |
02e2ce33 |
186 | #define z80_nmi() Cz80_Set_IRQ(&CZ80, IRQ_LINE_NMI, ASSERT_LINE)\r |
4b9c5888 |
187 | \r |
85894ad4 |
188 | #define z80_cyclesLeft (CZ80.ICount - CZ80.ExtraCycles)\r |
d1b8bcc6 |
189 | #define z80_subCLeft(c) CZ80.ICount -= c\r |
19954be1 |
190 | #define z80_pc() Cz80_Get_Reg(&CZ80, CZ80_PC)\r |
b542be46 |
191 | \r |
192 | #else\r |
193 | \r |
194 | #define z80_run(cycles) (cycles)\r |
195 | #define z80_run_nr(cycles)\r |
196 | #define z80_int()\r |
cf83610b |
197 | #define z80_int_assert(a)\r |
835122bc |
198 | #define z80_nmi()\r |
b542be46 |
199 | \r |
200 | #endif\r |
201 | \r |
b4db550e |
202 | #define Z80_STATE_SIZE 0x60\r |
203 | \r |
2f0c5639 |
204 | #define z80_resetCycles() { \\r |
205 | Pico.t.z80c_cnt -= Pico.t.z80c_aim, Pico.t.z80c_aim = Pico.t.z80_scanline = 0; \\r |
977e5db8 |
206 | if (!Pico.m.z80Run || Pico.m.z80_reset) Pico.t.z80c_cnt = 0; \\r |
2f0c5639 |
207 | }\r |
4b9c5888 |
208 | \r |
209 | #define z80_cyclesDone() \\r |
88fd63ad |
210 | (Pico.t.z80c_aim - z80_cyclesLeft)\r |
4b9c5888 |
211 | \r |
7263343d |
212 | // 68k clock = OSC/7, z80 clock = OSC/15, 68k:z80 ratio = 7/15 = 3822.9/8192\r |
e0c4dac1 |
213 | #define cycles_68k_to_z80(x) ((x) * 3823 >> 13)\r |
f5c022a8 |
214 | #define cycles_z80_to_68k(x) ((x) * 8777 >> 12)\r |
4b9c5888 |
215 | \r |
acd35d4c |
216 | // ----------------------- SH2 CPU -----------------------\r |
217 | \r |
f821bb70 |
218 | #include <cpu/sh2/sh2.h>\r |
acd35d4c |
219 | \r |
1d7a28a7 |
220 | extern SH2 sh2s[2];\r |
221 | #define msh2 sh2s[0]\r |
222 | #define ssh2 sh2s[1]\r |
223 | \r |
679af8a3 |
224 | #ifndef DRC_SH2\r |
19886062 |
225 | # define sh2_end_run(sh2, after_) do { \\r |
226 | if ((sh2)->icount > (after_)) { \\r |
c1931173 |
227 | (sh2)->cycles_timeslice -= (sh2)->icount - (after_); \\r |
19886062 |
228 | (sh2)->icount = after_; \\r |
a8fd6e37 |
229 | } \\r |
230 | } while (0)\r |
19886062 |
231 | # define sh2_cycles_left(sh2) (sh2)->icount\r |
8a847c12 |
232 | # define sh2_burn_cycles(sh2, n) (sh2)->icount -= n\r |
f81107f5 |
233 | # define sh2_pc(sh2) (sh2)->ppc\r |
bd078083 |
234 | # define sh2_not_polling(sh2) (sh2)->no_polling\r |
235 | # define sh2_set_polling(sh2) (sh2)->no_polling = 0\r |
679af8a3 |
236 | #else\r |
19886062 |
237 | # define sh2_end_run(sh2, after_) do { \\r |
2eb21331 |
238 | int left_ = ((signed int)(sh2)->sr >> 12) - (after_); \\r |
239 | if (left_ > 0) { \\r |
240 | (sh2)->cycles_timeslice -= left_; \\r |
241 | (sh2)->sr -= (left_ << 12); \\r |
a8fd6e37 |
242 | } \\r |
243 | } while (0)\r |
19886062 |
244 | # define sh2_cycles_left(sh2) ((signed int)(sh2)->sr >> 12)\r |
8a847c12 |
245 | # define sh2_burn_cycles(sh2, n) (sh2)->sr -= ((n) << 12)\r |
f81107f5 |
246 | # define sh2_pc(sh2) (sh2)->pc\r |
bd078083 |
247 | # define sh2_not_polling(sh2) ((sh2)->sr & SH2_NO_POLLING)\r |
248 | # define sh2_set_polling(sh2) ((sh2)->sr &= ~SH2_NO_POLLING)\r |
679af8a3 |
249 | #endif\r |
266c6afa |
250 | \r |
32feba74 |
251 | #define sh2_cycles_done(sh2) (unsigned)((int)(sh2)->cycles_timeslice - sh2_cycles_left(sh2))\r |
a7f82a77 |
252 | #define sh2_cycles_done_t(sh2) \\r |
2fa02d5a |
253 | (unsigned)(C_M68K_TO_SH2(sh2, (sh2)->m68krcycles_done) + sh2_cycles_done(sh2))\r |
19886062 |
254 | #define sh2_cycles_done_m68k(sh2) \\r |
2fa02d5a |
255 | (unsigned)((sh2)->m68krcycles_done + C_SH2_TO_M68K(sh2, sh2_cycles_done(sh2)))\r |
19886062 |
256 | \r |
4cc0fcaf |
257 | #define sh2_reg(c, x) ((c) ? ssh2.r[x] : msh2.r[x])\r |
258 | #define sh2_gbr(c) ((c) ? ssh2.gbr : msh2.gbr)\r |
259 | #define sh2_vbr(c) ((c) ? ssh2.vbr : msh2.vbr)\r |
260 | #define sh2_sr(c) (((c) ? ssh2.sr : msh2.sr) & 0xfff)\r |
acd35d4c |
261 | \r |
83ff19ec |
262 | #define sh2_set_gbr(c, v) \\r |
263 | { if (c) ssh2.gbr = v; else msh2.gbr = v; }\r |
264 | #define sh2_set_vbr(c, v) \\r |
265 | { if (c) ssh2.vbr = v; else msh2.vbr = v; }\r |
266 | \r |
f8675e28 |
267 | #define elprintf_sh2(sh2, w, f, ...) \\r |
268 | elprintf(w,"%csh2 "f,(sh2)->is_slave?'s':'m',##__VA_ARGS__)\r |
269 | \r |
cc68a136 |
270 | // ---------------------------------------------------------\r |
271 | \r |
272 | // main oscillator clock which controls timing\r |
588881c4 |
273 | #define OSC_NTSC 53693175\r |
b8cbd802 |
274 | #define OSC_PAL 53203424\r |
cc68a136 |
275 | \r |
e42a47e2 |
276 | // PicoVideo.debug_p\r |
e0bcb7a9 |
277 | #define PVD_KILL_A (1 << 0)\r |
278 | #define PVD_KILL_B (1 << 1)\r |
279 | #define PVD_KILL_S_LO (1 << 2)\r |
280 | #define PVD_KILL_S_HI (1 << 3)\r |
281 | #define PVD_KILL_32X (1 << 4)\r |
282 | #define PVD_FORCE_A (1 << 5)\r |
283 | #define PVD_FORCE_B (1 << 6)\r |
284 | #define PVD_FORCE_S (1 << 7)\r |
285 | \r |
e42a47e2 |
286 | // PicoVideo.status, not part of real SR\r |
287 | #define SR_PAL (1 << 0)\r |
288 | #define SR_DMA (1 << 1)\r |
289 | #define SR_HB (1 << 2)\r |
290 | #define SR_VB (1 << 3)\r |
291 | #define SR_ODD (1 << 4)\r |
292 | #define SR_C (1 << 5)\r |
293 | #define SR_SOVR (1 << 6)\r |
294 | #define SR_F (1 << 7)\r |
295 | #define SR_FULL (1 << 8)\r |
296 | #define SR_EMPT (1 << 9)\r |
297 | // not part of real SR\r |
298 | #define PVS_ACTIVE (1 << 16)\r |
0e4bde9b |
299 | #define PVS_VB2 (1 << 17) // ignores forced blanking\r |
787a0af9 |
300 | #define PVS_CPUWR (1 << 18) // CPU write blocked by FIFO full\r |
301 | #define PVS_CPURD (1 << 19) // CPU read blocked by FIFO not empty\r |
302 | #define PVS_DMAFILL (1 << 20) // DMA fill is waiting for fill data\r |
c55a44a8 |
303 | #define PVS_DMABG (1 << 21) // background DMA operation is running\r |
304 | #define PVS_FIFORUN (1 << 22) // FIFO is processing\r |
e42a47e2 |
305 | \r |
cc68a136 |
306 | struct PicoVideo\r |
307 | {\r |
308 | unsigned char reg[0x20];\r |
b8cbd802 |
309 | unsigned int command; // 32-bit Command\r |
310 | unsigned char pending; // 1 if waiting for second half of 32-bit command\r |
311 | unsigned char type; // Command type (v/c/vsram read/write)\r |
312 | unsigned short addr; // Read/Write address\r |
e42a47e2 |
313 | unsigned int status; // Status bits (SR) and extra flags\r |
cc68a136 |
314 | unsigned char pending_ints; // pending interrupts: ??VH????\r |
17bd69ad |
315 | signed char pad1; // was VDP write count\r |
9761a7d0 |
316 | unsigned short v_counter; // V-counter\r |
e0bcb7a9 |
317 | unsigned short debug; // raw debug register\r |
318 | unsigned char debug_p; // ... parsed: PVD_*\r |
e42a47e2 |
319 | unsigned char addr_u; // bit16 of .addr\r |
320 | unsigned char hint_cnt;\r |
ba2b97dc |
321 | unsigned char hint_irq; // irq# of HINT (4 on MD, 5 on Pico)\r |
daf29df9 |
322 | unsigned short hv_latch; // latched hvcounter value\r |
e45908d7 |
323 | signed int fifo_cnt; // pending xfers for blocking FIFO queue entries\r |
324 | signed int fifo_bgcnt; // pending xfers for background FIFO queue entries\r |
cc68a136 |
325 | };\r |
326 | \r |
327 | struct PicoMisc\r |
328 | {\r |
329 | unsigned char rotate;\r |
330 | unsigned char z80Run;\r |
e5503e2f |
331 | unsigned char padTHPhase[2]; // 02 phase of gamepad TH switches\r |
2aa27095 |
332 | unsigned short scanline; // 04 0 to 261||311\r |
e5503e2f |
333 | char dirtyPal; // 06 Is the palette dirty (1 - change @ this frame, 2 - some time before)\r |
334 | unsigned char hardware; // 07 Hardware value for country\r |
335 | unsigned char pal; // 08 1=PAL 0=NTSC\r |
45f2f245 |
336 | unsigned char sram_reg; // 09 SRAM reg. See SRR_* below\r |
e5503e2f |
337 | unsigned short z80_bank68k; // 0a\r |
be2c4208 |
338 | unsigned short pad0;\r |
fa8fb754 |
339 | unsigned char ncart_in; // 0e !cart_in\r |
0ace9b9a |
340 | unsigned char z80_reset; // 0f z80 reset held\r |
e5503e2f |
341 | unsigned char padDelay[2]; // 10 gamepad phase time outs, so we count a delay\r |
1dceadae |
342 | unsigned short eeprom_addr; // EEPROM address register\r |
45f2f245 |
343 | unsigned char eeprom_cycle; // EEPROM cycle number\r |
1dceadae |
344 | unsigned char eeprom_slave; // EEPROM slave word for X24C02 and better SRAMs\r |
45f2f245 |
345 | unsigned char eeprom_status;\r |
8ac9ab7f |
346 | unsigned char pad1; // was ym2612 status\r |
daf29df9 |
347 | unsigned short dma_xfers; // 18 unused (was VDP DMA transfer count)\r |
45f2f245 |
348 | unsigned char eeprom_wb[2]; // EEPROM latch/write buffer\r |
053fd9b4 |
349 | unsigned int frame_count; // 1c for movies and idle det\r |
cc68a136 |
350 | };\r |
351 | \r |
3611781e |
352 | #define PMS_HW_LCD 0x2 // GG LCD\r |
353 | #define PMS_HW_JAP 0x4 // japanese system\r |
c9076db9 |
354 | #define PMS_HW_FM 0x8 // FM sound\r |
214a6c62 |
355 | #define PMS_HW_TMS 0x10 // assume TMS9918\r |
721f2651 |
356 | #define PMS_HW_3D 0x20 // 3D glasses\r |
214a6c62 |
357 | #define PMS_HW_FMUSED 0x80 // FM sound accessed\r |
3611781e |
358 | \r |
1cdc3f84 |
359 | #define PMS_MAP_AUTO 0\r |
360 | #define PMS_MAP_SEGA 1\r |
361 | #define PMS_MAP_CODEM 2\r |
362 | #define PMS_MAP_KOREA 3\r |
363 | #define PMS_MAP_MSX 4\r |
364 | #define PMS_MAP_N32K 5\r |
365 | #define PMS_MAP_N16K 6\r |
f9ea940f |
366 | #define PMS_MAP_JANGGUN 7\r |
367 | #define PMS_MAP_NEMESIS 8\r |
171fb8cc |
368 | #define PMS_MAP_8KBRAM 9\r |
7c6f7914 |
369 | #define PMS_MAP_XOR 10\r |
cab84f29 |
370 | #define PMS_MAP_32KBRAM 11\r |
1cdc3f84 |
371 | \r |
b4db550e |
372 | struct PicoMS\r |
373 | {\r |
374 | unsigned char carthw[0x10];\r |
375 | unsigned char io_ctl;\r |
835122bc |
376 | unsigned char nmi_state;\r |
032c76a3 |
377 | unsigned char mapper;\r |
3039d6d8 |
378 | unsigned char fm_ctl;\r |
379 | unsigned char vdp_buffer;\r |
380 | unsigned char vdp_hlatch;\r |
381 | unsigned char io_gg[0x08];\r |
df6c895c |
382 | unsigned char mapcnt;\r |
cab84f29 |
383 | unsigned char io_sg;\r |
384 | unsigned char pad[0x40];\r |
b4db550e |
385 | };\r |
386 | \r |
ea38612f |
387 | // emu state and data for the asm code\r |
388 | struct PicoEState\r |
389 | {\r |
390 | int DrawScanline;\r |
391 | int rendstatus;\r |
98a27142 |
392 | void *DrawLineDest; // draw destination\r |
d5d17782 |
393 | int DrawLineDestIncr;\r |
99bdfd31 |
394 | unsigned char *HighCol;\r |
583c4840 |
395 | s32 *HighPreSpr;\r |
88fd63ad |
396 | struct Pico *Pico;\r |
959ea39b |
397 | unsigned short *PicoMem_vram;\r |
398 | unsigned short *PicoMem_cram;\r |
93f9619e |
399 | unsigned int *PicoOpt;\r |
98a27142 |
400 | unsigned char *Draw2FB;\r |
f55fb314 |
401 | int Draw2Width;\r |
402 | int Draw2Start;\r |
98a27142 |
403 | unsigned short HighPal[0x100];\r |
b1a047c9 |
404 | unsigned short SonicPal[0x100];\r |
405 | int SonicPalCount;\r |
ea38612f |
406 | };\r |
407 | \r |
88fd63ad |
408 | struct PicoMem\r |
cc68a136 |
409 | {\r |
410 | unsigned char ram[0x10000]; // 0x00000 scratch ram\r |
200772b7 |
411 | union { // vram is byteswapped for easier reads when drawing\r |
2ec9bec5 |
412 | unsigned short vram[0x8000]; // 0x10000\r |
413 | unsigned char vramb[0x4000]; // VRAM in SMS mode\r |
414 | };\r |
cc68a136 |
415 | unsigned char zram[0x2000]; // 0x20000 Z80 ram\r |
b4db550e |
416 | unsigned char ioports[0x10]; // XXX: fix asm and mv\r |
cf07a88d |
417 | unsigned short cram[0x40]; // 0x22010\r |
418 | unsigned char pad[0x70]; // 0x22050 DrawStripVSRam reads 0 from here\r |
419 | unsigned short vsram[0x40]; // 0x22100\r |
cc68a136 |
420 | };\r |
421 | \r |
422 | // sram\r |
45f2f245 |
423 | #define SRR_MAPPED (1 << 0)\r |
424 | #define SRR_READONLY (1 << 1)\r |
425 | \r |
426 | #define SRF_ENABLED (1 << 0)\r |
427 | #define SRF_EEPROM (1 << 1)\r |
af37bca8 |
428 | \r |
88fd63ad |
429 | struct PicoCartSave\r |
cc68a136 |
430 | {\r |
4ff2d527 |
431 | unsigned char *data; // actual data\r |
432 | unsigned int start; // start address in 68k address space\r |
cc68a136 |
433 | unsigned int end;\r |
45f2f245 |
434 | unsigned char flags; // 0c: SRF_*\r |
1dceadae |
435 | unsigned char unused2;\r |
cc68a136 |
436 | unsigned char changed;\r |
45f2f245 |
437 | unsigned char eeprom_type; // eeprom type: 0: 7bit (24C01), 2: 2 addr words (X24C02+), 3: 3 addr words\r |
438 | unsigned char unused3;\r |
1dceadae |
439 | unsigned char eeprom_bit_cl; // bit number for cl\r |
440 | unsigned char eeprom_bit_in; // bit number for in\r |
441 | unsigned char eeprom_bit_out; // bit number for out\r |
45f2f245 |
442 | unsigned int size;\r |
cc68a136 |
443 | };\r |
444 | \r |
88fd63ad |
445 | struct PicoTiming\r |
446 | {\r |
447 | // while running, cnt represents target of current timeslice\r |
448 | // while not in SekRun(), it's actual cycles done\r |
449 | // (but always use SekCyclesDone() if you need current position)\r |
450 | // _cnt may change if timeslice is ended prematurely or extended,\r |
451 | // so we use _aim for the actual target\r |
452 | unsigned int m68c_cnt;\r |
453 | unsigned int m68c_aim;\r |
454 | unsigned int m68c_frame_start; // m68k cycles\r |
455 | unsigned int m68c_line_start;\r |
7263343d |
456 | int refresh_delay;\r |
88fd63ad |
457 | \r |
458 | unsigned int z80c_cnt; // z80 cycles done (this frame)\r |
459 | unsigned int z80c_aim;\r |
7eeb85be |
460 | unsigned int z80c_line_start;\r |
88fd63ad |
461 | int z80_scanline;\r |
134092fe |
462 | int z80_buscycles;\r |
e0c4dac1 |
463 | int z80_busdelay;\r |
6311a3ba |
464 | \r |
465 | int timer_a_next_oflow, timer_a_step; // in z80 cycles\r |
466 | int timer_b_next_oflow, timer_b_step;\r |
83025d7a |
467 | int ym2612_busy;\r |
70216221 |
468 | \r |
469 | int vcnt_wrap, vcnt_adj;\r |
6311a3ba |
470 | };\r |
471 | \r |
472 | struct PicoSound\r |
473 | {\r |
474 | short len; // number of mono samples\r |
475 | short len_use; // adjusted\r |
476 | int len_e_add; // for non-int samples/frame\r |
477 | int len_e_cnt;\r |
588881c4 |
478 | unsigned int clkz_mult; // z80 clocks per sample in Q20\r |
09b96f99 |
479 | unsigned int smpl_mult; // samples per line in Q16\r |
f7741cac |
480 | unsigned int cdda_mult, cdda_div; // 44.1 KHz resampling factor in Q16\r |
09b96f99 |
481 | short dac_val, dac_val2; // last DAC sample\r |
482 | unsigned int dac_pos; // last DAC position in Q20\r |
483 | unsigned int fm_pos; // last FM position in Q20\r |
484 | unsigned int psg_pos; // last PSG position in Q16\r |
a2f24bfa |
485 | unsigned int ym2413_pos; // last YM2413 position\r |
e348af76 |
486 | unsigned int pcm_pos; // last PCM position in Q16\r |
e2e2b6ad |
487 | unsigned int fm_fir_mul, fm_fir_div; // ratio for FM resampling FIR\r |
88fd63ad |
488 | };\r |
489 | \r |
d40a5af4 |
490 | // run tools/mkoffsets pico/pico_int_offs.h if you change these\r |
88fd63ad |
491 | // careful with savestate compat\r |
492 | struct Pico\r |
493 | {\r |
494 | struct PicoVideo video;\r |
495 | struct PicoMisc m;\r |
496 | struct PicoTiming t;\r |
497 | struct PicoCartSave sv;\r |
6311a3ba |
498 | struct PicoSound snd;\r |
88fd63ad |
499 | struct PicoEState est;\r |
500 | struct PicoMS ms;\r |
501 | \r |
502 | unsigned char *rom;\r |
503 | unsigned int romsize;\r |
504 | };\r |
505 | \r |
cc68a136 |
506 | // MCD\r |
33be04ca |
507 | #define PCM_MIXBUF_LEN ((12500000 / 384) / 50 + 1)\r |
508 | \r |
4f265db7 |
509 | struct mcd_pcm\r |
510 | {\r |
511 | unsigned char control; // reg7\r |
512 | unsigned char enabled; // reg8\r |
513 | unsigned char cur_ch;\r |
514 | unsigned char bank;\r |
33be04ca |
515 | unsigned int update_cycles;\r |
4f265db7 |
516 | \r |
4ff2d527 |
517 | struct pcm_chan // 08, size 0x10\r |
4f265db7 |
518 | {\r |
519 | unsigned char regs[8];\r |
4ff2d527 |
520 | unsigned int addr; // .08: played sample address\r |
4f265db7 |
521 | int pad;\r |
522 | } ch[8];\r |
523 | };\r |
524 | \r |
8eeb3426 |
525 | #define PCD_ST_S68K_RST 1\r |
526 | #define PCD_ST_S68K_SYNC 2\r |
527 | #define PCD_ST_S68K_SLEEP 4\r |
8eeb3426 |
528 | #define PCD_ST_S68K_POLL 16\r |
529 | #define PCD_ST_M68K_POLL 32\r |
ce5c904a |
530 | #define PCD_ST_CDD_CMD 64\r |
178a9b68 |
531 | #define PCD_ST_S68K_IFL2 0x100\r |
4fb43555 |
532 | \r |
c459aefd |
533 | struct mcd_misc\r |
534 | {\r |
6901d0e4 |
535 | unsigned short hint_vector;\r |
536 | unsigned char busreq; // not s68k_regs[1]\r |
537 | unsigned char s68k_pend_ints;\r |
538 | unsigned int state_flags; // 04\r |
539 | unsigned int stopwatch_base_c;\r |
540 | unsigned short m68k_poll_a;\r |
541 | unsigned short m68k_poll_cnt;\r |
7263343d |
542 | unsigned short s68k_poll_a; // 10\r |
6901d0e4 |
543 | unsigned short s68k_poll_cnt;\r |
544 | unsigned int s68k_poll_clk;\r |
545 | unsigned char bcram_reg; // 18: battery-backed RAM cart register\r |
546 | unsigned char dmna_ret_2m;\r |
547 | unsigned char need_sync;\r |
548 | unsigned char pad3;\r |
54022234 |
549 | unsigned int m68k_poll_clk;\r |
588881c4 |
550 | unsigned int cdda_lba_offset; // 20\r |
551 | int pad4[7];\r |
c459aefd |
552 | };\r |
553 | \r |
cc68a136 |
554 | typedef struct\r |
555 | {\r |
3f23709e |
556 | unsigned char bios[0x20000]; // 000000: 128K\r |
557 | union { // 020000: 512K\r |
558 | unsigned char prg_ram[0x80000];\r |
559 | unsigned char prg_ram_b[4][0x20000];\r |
560 | };\r |
561 | union { // 0a0000: 256K\r |
562 | struct {\r |
563 | unsigned char word_ram2M[0x40000];\r |
564 | unsigned char unused0[0x20000];\r |
565 | };\r |
566 | struct {\r |
567 | unsigned char unused1[0x20000];\r |
568 | unsigned char word_ram1M[2][0x20000];\r |
569 | };\r |
570 | };\r |
571 | union { // 100000: 64K\r |
572 | unsigned char pcm_ram[0x10000];\r |
573 | unsigned char pcm_ram_b[0x10][0x1000];\r |
574 | };\r |
f47d0a28 |
575 | unsigned char s68k_regs[0x200]; // 110000: GA, not CPU regs\r |
3f23709e |
576 | unsigned char bram[0x2000]; // 110200: 8K\r |
577 | struct mcd_misc m; // 112200: misc\r |
578 | struct mcd_pcm pcm; // 112240:\r |
274fcc35 |
579 | void *cdda_stream;\r |
580 | int cdda_type;\r |
588881c4 |
581 | unsigned int cdda_frame_offs;\r |
3f23709e |
582 | int pcm_mixbuf[PCM_MIXBUF_LEN * 2];\r |
583 | int pcm_mixpos;\r |
584 | char pcm_mixbuf_dirty;\r |
585 | char pcm_regs_dirty;\r |
cc68a136 |
586 | } mcd_state;\r |
587 | \r |
be2c4208 |
588 | // 32X\r |
acd35d4c |
589 | #define P32XS_FM (1<<15)\r |
83ff19ec |
590 | #define P32XS_REN (1<< 7)\r |
591 | #define P32XS_nRES (1<< 1)\r |
592 | #define P32XS_ADEN (1<< 0)\r |
fa23e7cc |
593 | \r |
594 | #define P32XS2_FM (1<<15)\r |
595 | #define P32XS2_nCART (1<< 8)\r |
acd35d4c |
596 | #define P32XS2_ADEN (1<< 9)\r |
fa23e7cc |
597 | \r |
5e128c6d |
598 | #define P32XS_FULL (1<< 7) // DREQ FIFO full\r |
4ea707e1 |
599 | #define P32XS_68S (1<< 2)\r |
97d3f47f |
600 | #define P32XS_DMA (1<< 1)\r |
4ea707e1 |
601 | #define P32XS_RV (1<< 0)\r |
acd35d4c |
602 | \r |
5e128c6d |
603 | #define P32XV_nPAL (1<<15) // VDP\r |
acd35d4c |
604 | #define P32XV_PRI (1<< 7)\r |
4ea707e1 |
605 | #define P32XV_Mx (3<< 0) // display mode mask\r |
974fdb5b |
606 | \r |
e51e5983 |
607 | #define P32XV_SFT (1<< 0)\r |
608 | \r |
acd35d4c |
609 | #define P32XV_VBLK (1<<15)\r |
610 | #define P32XV_HBLK (1<<14)\r |
611 | #define P32XV_PEN (1<<13)\r |
612 | #define P32XV_nFEN (1<< 1)\r |
613 | #define P32XV_FS (1<< 0)\r |
974fdb5b |
614 | \r |
df63f1a6 |
615 | #define P32XP_RTP (1<<7) // PWM control\r |
616 | #define P32XP_FULL (1<<15) // PWM pulse\r |
db1d3564 |
617 | #define P32XP_EMPTY (1<<14)\r |
618 | \r |
419973a6 |
619 | #define P32XF_68KCPOLL (1 << 0)\r |
620 | #define P32XF_68KVPOLL (1 << 1)\r |
621 | #define P32XF_Z80_32X_IO (1 << 7) // z80 does 32x io\r |
8b9dbcde |
622 | #define P32XF_DRC_ROM_C (1 << 8) // cached code from ROM\r |
4ea707e1 |
623 | \r |
624 | #define P32XI_VRES (1 << 14/2) // IRL/2\r |
625 | #define P32XI_VINT (1 << 12/2)\r |
626 | #define P32XI_HINT (1 << 10/2)\r |
627 | #define P32XI_CMD (1 << 8/2)\r |
628 | #define P32XI_PWM (1 << 6/2)\r |
629 | \r |
57c5a5e5 |
630 | // peripheral reg access (32 bit regs)\r |
631 | #define PREG8(regs,offs) ((unsigned char *)regs)[MEM_BE4(offs)]\r |
1d7a28a7 |
632 | \r |
7eaa3812 |
633 | #define DMAC_FIFO_LEN (4*2)\r |
db1d3564 |
634 | #define PWM_BUFF_LEN 1024 // in one channel samples\r |
266c6afa |
635 | \r |
f4bb5d6b |
636 | #define SH2_DRCBLK_RAM_SHIFT 1\r |
637 | #define SH2_DRCBLK_DA_SHIFT 1\r |
638 | \r |
f81107f5 |
639 | #define SH2_READ_SHIFT 25\r |
e05b81fc |
640 | #define SH2_WRITE_SHIFT 25\r |
641 | \r |
be2c4208 |
642 | struct Pico32x\r |
643 | {\r |
644 | unsigned short regs[0x20];\r |
5a681086 |
645 | unsigned short vdp_regs[0x10]; // 0x40\r |
646 | unsigned short sh2_regs[3]; // 0x60\r |
be2c4208 |
647 | unsigned char pending_fb;\r |
974fdb5b |
648 | unsigned char dirty_pal;\r |
266c6afa |
649 | unsigned int emu_flags;\r |
4ea707e1 |
650 | unsigned char sh2irq_mask[2];\r |
651 | unsigned char sh2irqi[2]; // individual\r |
83416730 |
652 | unsigned int pad4; // was sh2irqs\r |
4ea707e1 |
653 | unsigned short dmac_fifo[DMAC_FIFO_LEN];\r |
7eaa3812 |
654 | unsigned int pad[4];\r |
df63f1a6 |
655 | unsigned int dmac0_fifo_ptr;\r |
4a1fb183 |
656 | unsigned short vdp_fbcr_fake;\r |
7eaa3812 |
657 | unsigned short pad2;\r |
31fbc691 |
658 | unsigned char comm_dirty;\r |
659 | unsigned char pad3; // was comm_dirty_sh2\r |
df63f1a6 |
660 | unsigned char pwm_irq_cnt;\r |
661 | unsigned char pad1;\r |
a7f82a77 |
662 | unsigned short pwm_p[2]; // pwm pos in fifo\r |
663 | unsigned int pwm_cycle_p; // pwm play cursor (32x cycles)\r |
7263343d |
664 | unsigned int hint_counter;\r |
2322260c |
665 | unsigned int sync_line;\r |
666 | unsigned int reserved[4];\r |
974fdb5b |
667 | };\r |
668 | \r |
669 | struct Pico32xMem\r |
670 | {\r |
671 | unsigned char sdram[0x40000];\r |
f4bb5d6b |
672 | #ifdef DRC_SH2\r |
f133766f |
673 | unsigned char drcblk_ram[1 << (18 - SH2_DRCBLK_RAM_SHIFT)];\r |
674 | unsigned char drclit_ram[1 << (18 - SH2_DRCBLK_RAM_SHIFT)];\r |
f4bb5d6b |
675 | #endif\r |
b78efee2 |
676 | unsigned short dram[2][0x20000/2]; // AKA fb\r |
b4db550e |
677 | union {\r |
678 | unsigned char m68k_rom[0x100];\r |
679 | unsigned char m68k_rom_bank[0x10000]; // M68K_BANK_SIZE\r |
680 | };\r |
f4bb5d6b |
681 | #ifdef DRC_SH2\r |
f133766f |
682 | unsigned char drcblk_da[2][1 << (12 - SH2_DRCBLK_DA_SHIFT)];\r |
683 | unsigned char drclit_da[2][1 << (12 - SH2_DRCBLK_DA_SHIFT)];\r |
f4bb5d6b |
684 | #endif\r |
895d1512 |
685 | union {\r |
686 | unsigned char b[0x800];\r |
687 | unsigned short w[0x800/2];\r |
688 | } sh2_rom_m;\r |
689 | union {\r |
690 | unsigned char b[0x400];\r |
691 | unsigned short w[0x400/2];\r |
692 | } sh2_rom_s;\r |
974fdb5b |
693 | unsigned short pal[0x100];\r |
5e128c6d |
694 | unsigned short pal_native[0x100]; // converted to native (for renderer)\r |
db1d3564 |
695 | signed short pwm[2*PWM_BUFF_LEN]; // PWM buffer for current frame\r |
8ce9c3a7 |
696 | unsigned short pwm_fifo[2][4]; // [0] - current raw, others - fifo entries\r |
fe344bd3 |
697 | unsigned pwm_index[2]; // ringbuffer index for pwm_fifo\r |
be2c4208 |
698 | };\r |
d49b10c2 |
699 | \r |
c8d1e9b6 |
700 | // area.c\r |
fad24893 |
701 | extern void (*PicoLoadStateHook)(void);\r |
51a902ae |
702 | \r |
945c2fdc |
703 | typedef struct {\r |
704 | int chunk;\r |
705 | int size;\r |
706 | void *ptr;\r |
707 | } carthw_state_chunk;\r |
708 | extern carthw_state_chunk *carthw_chunks;\r |
709 | #define CHUNK_CARTHW 64\r |
710 | \r |
c8d1e9b6 |
711 | // cart.c\r |
549dd407 |
712 | extern int rom_strcmp(void *rom, int size, int offset, const char *s1);\r |
b4db550e |
713 | extern int PicoCartResize(int newsize);\r |
714 | extern void Byteswap(void *dst, const void *src, int len);\r |
45f2f245 |
715 | extern void (*PicoCartMemSetup)(void);\r |
e807ac75 |
716 | extern void (*PicoCartUnloadHook)(void);\r |
1dceadae |
717 | \r |
c8d1e9b6 |
718 | // debug.c\r |
b5e5172d |
719 | int CM_compareRun(int cyc, int is_sub);\r |
03e4f2a3 |
720 | \r |
c8d1e9b6 |
721 | // draw.c\r |
99bdfd31 |
722 | void PicoDrawInit(void);\r |
eff55556 |
723 | PICO_INTERNAL void PicoFrameStart(void);\r |
0c9c8e47 |
724 | void PicoDrawRefreshSprites(void);\r |
724db457 |
725 | void PicoDrawBgcDMA(u16 *base, u32 source, u32 mask, int len, int sl);\r |
d515a352 |
726 | void PicoDrawSync(int to, int blank_last_line, int limit_sprites);\r |
99bdfd31 |
727 | void BackFill(int reg7, int sh, struct PicoEState *est);\r |
ea38612f |
728 | void FinalizeLine555(int sh, int line, struct PicoEState *est);\r |
466fa079 |
729 | void FinalizeLine8bit(int sh, int line, struct PicoEState *est);\r |
32feba74 |
730 | void PicoDrawSetOutBufMD(void *dest, int increment);\r |
f4750ee0 |
731 | extern int (*PicoScanBegin)(unsigned int num);\r |
732 | extern int (*PicoScanEnd)(unsigned int num);\r |
5f0d224e |
733 | #define MAX_LINE_SPRITES 27 // +1 last sprite width, +4 hdr; total 32\r |
734 | extern unsigned char HighLnSpr[240][4+MAX_LINE_SPRITES+1];\r |
7980d477 |
735 | extern unsigned char *HighColBase;\r |
736 | extern int HighColIncrement;\r |
5a681086 |
737 | extern void *DrawLineDestBase;\r |
738 | extern int DrawLineDestIncrement;\r |
ac891449 |
739 | extern u32 VdpSATCache[2*128];\r |
cc68a136 |
740 | \r |
c8d1e9b6 |
741 | // draw2.c\r |
f55fb314 |
742 | void PicoDraw2SetOutBuf(void *dest, int incr);\r |
98a27142 |
743 | void PicoDraw2Init(void);\r |
043ccbf4 |
744 | PICO_INTERNAL void PicoFrameFull(void);\r |
cc68a136 |
745 | \r |
200772b7 |
746 | // mode4.c\r |
0df7401c |
747 | void PicoFrameStartSMS(void);\r |
1ce2b092 |
748 | void PicoParseSATSMS(int line);\r |
0df7401c |
749 | void PicoLineSMS(int line);\r |
750 | void PicoDoHighPal555SMS(void);\r |
751 | void PicoDrawSetOutputSMS(pdso_t which);\r |
200772b7 |
752 | \r |
c8d1e9b6 |
753 | // memory.c\r |
eff55556 |
754 | PICO_INTERNAL void PicoMemSetup(void);\r |
9f29605f |
755 | PICO_INTERNAL u32 PicoRead16_floating(u32 a);\r |
15eed405 |
756 | u32 PicoRead8_io(u32 a);\r |
757 | u32 PicoRead16_io(u32 a);\r |
758 | void PicoWrite8_io(u32 a, u32 d);\r |
759 | void PicoWrite16_io(u32 a, u32 d);\r |
99bd61f8 |
760 | u32 PicoReadPad(int i, u32 mask);\r |
4a521146 |
761 | int io_ports_pack(void *buf, size_t size);\r |
762 | void io_ports_unpack(const void *buf, size_t size);\r |
af37bca8 |
763 | \r |
764 | // pico/memory.c\r |
765 | PICO_INTERNAL void PicoMemSetupPico(void);\r |
cc68a136 |
766 | \r |
3f23709e |
767 | // cd/cdc.c\r |
768 | void cdc_init(void);\r |
769 | void cdc_reset(void);\r |
770 | int cdc_context_save(unsigned char *state);\r |
771 | int cdc_context_load(unsigned char *state);\r |
772 | int cdc_context_load_old(unsigned char *state);\r |
773 | void cdc_dma_update(void);\r |
774 | int cdc_decoder_update(unsigned char header[4]);\r |
775 | void cdc_reg_w(unsigned char data);\r |
776 | unsigned char cdc_reg_r(void);\r |
dd7c8c05 |
777 | unsigned short cdc_host_r(int sub);\r |
3f23709e |
778 | \r |
274fcc35 |
779 | // cd/cdd.c\r |
780 | void cdd_reset(void);\r |
b0be121b |
781 | void cdd_play_audio(int index, int lba);\r |
274fcc35 |
782 | int cdd_context_save(unsigned char *state);\r |
783 | int cdd_context_load(unsigned char *state);\r |
784 | int cdd_context_load_old(unsigned char *state);\r |
785 | void cdd_read_data(unsigned char *dst);\r |
786 | void cdd_read_audio(unsigned int samples);\r |
787 | void cdd_update(void);\r |
788 | void cdd_process(void);\r |
789 | \r |
790 | // cd/cd_image.c\r |
791 | int load_cd_image(const char *cd_img_name, int *type);\r |
792 | \r |
a93a80de |
793 | // cd/gfx.c\r |
794 | void gfx_init(void);\r |
f821bb70 |
795 | void gfx_start(u32 base);\r |
a93a80de |
796 | void gfx_update(unsigned int cycles);\r |
797 | int gfx_context_save(unsigned char *state);\r |
798 | int gfx_context_load(const unsigned char *state);\r |
799 | \r |
800 | // cd/gfx_dma.c\r |
15eed405 |
801 | void DmaSlowCell(u32 source, u32 a, int len, unsigned char inc);\r |
a93a80de |
802 | \r |
c8d1e9b6 |
803 | // cd/memory.c\r |
69d69a4f |
804 | extern u32 pcd_base_address;\r |
eff55556 |
805 | PICO_INTERNAL void PicoMemSetupCD(void);\r |
15eed405 |
806 | u32 PicoRead8_mcd_io(u32 a);\r |
807 | u32 PicoRead16_mcd_io(u32 a);\r |
808 | void PicoWrite8_mcd_io(u32 a, u32 d);\r |
809 | void PicoWrite16_mcd_io(u32 a, u32 d);\r |
ae214f1c |
810 | void pcd_state_loaded_mem(void);\r |
cc68a136 |
811 | \r |
c8d1e9b6 |
812 | // pico.c\r |
cc68a136 |
813 | extern struct Pico Pico;\r |
88fd63ad |
814 | extern struct PicoMem PicoMem;\r |
f8ef8ff7 |
815 | extern void (*PicoResetHook)(void);\r |
b0677887 |
816 | extern void (*PicoLineHook)(void);\r |
43e14010 |
817 | PICO_INTERNAL int CheckDMA(int cycles);\r |
1e6b5e39 |
818 | PICO_INTERNAL void PicoDetectRegion(void);\r |
ae214f1c |
819 | PICO_INTERNAL void PicoSyncZ80(unsigned int m68k_cycles_done);\r |
cc68a136 |
820 | \r |
89dbbf2b |
821 | // cd/mcd.c\r |
ae214f1c |
822 | #define PCDS_IEN1 (1<<1)\r |
823 | #define PCDS_IEN2 (1<<2)\r |
824 | #define PCDS_IEN3 (1<<3)\r |
825 | #define PCDS_IEN4 (1<<4)\r |
826 | #define PCDS_IEN5 (1<<5)\r |
827 | #define PCDS_IEN6 (1<<6)\r |
cc68a136 |
828 | \r |
02ff0254 |
829 | extern mcd_state *Pico_mcd;\r |
830 | \r |
549dd407 |
831 | PICO_INTERNAL void PicoCreateMCD(unsigned char *bios_data, int bios_size);\r |
2aa27095 |
832 | PICO_INTERNAL void PicoInitMCD(void);\r |
e5f426aa |
833 | PICO_INTERNAL void PicoExitMCD(void);\r |
1cb1584b |
834 | PICO_INTERNAL void PicoPowerMCD(void);\r |
2aa27095 |
835 | PICO_INTERNAL int PicoResetMCD(void);\r |
836 | PICO_INTERNAL void PicoFrameMCD(void);\r |
7263343d |
837 | PICO_INTERNAL void PicoMCDPrepare(void);\r |
cc68a136 |
838 | \r |
ae214f1c |
839 | enum pcd_event {\r |
840 | PCD_EVENT_CDC,\r |
841 | PCD_EVENT_TIMER3,\r |
842 | PCD_EVENT_GFX,\r |
843 | PCD_EVENT_DMA,\r |
844 | PCD_EVENT_COUNT,\r |
845 | };\r |
846 | extern unsigned int pcd_event_times[PCD_EVENT_COUNT];\r |
02ff0254 |
847 | \r |
ae214f1c |
848 | void pcd_event_schedule(unsigned int now, enum pcd_event event, int after);\r |
849 | void pcd_event_schedule_s68k(enum pcd_event event, int after);\r |
a6523294 |
850 | void pcd_prepare_frame(void);\r |
ae214f1c |
851 | unsigned int pcd_cycles_m68k_to_s68k(unsigned int c);\r |
eb36d9c7 |
852 | void pcd_irq_s68k(int irq, int state);\r |
08769494 |
853 | int pcd_sync_s68k(unsigned int m68k_target, int m68k_poll_sync);\r |
fa8fb754 |
854 | void pcd_run_cpus(int m68k_cycles);\r |
d0132772 |
855 | void pcd_soft_reset(void);\r |
ae214f1c |
856 | void pcd_state_loaded(void);\r |
857 | \r |
33be04ca |
858 | // cd/pcm.c\r |
859 | void pcd_pcm_sync(unsigned int to);\r |
91ea9406 |
860 | void pcd_pcm_update(s32 *buffer, int length, int stereo);\r |
33be04ca |
861 | void pcd_pcm_write(unsigned int a, unsigned int d);\r |
862 | unsigned int pcd_pcm_read(unsigned int a);\r |
863 | \r |
c8d1e9b6 |
864 | // pico/pico.c\r |
2aa27095 |
865 | PICO_INTERNAL void PicoInitPico(void);\r |
ed367a3f |
866 | PICO_INTERNAL void PicoReratePico(void);\r |
f1b425e3 |
867 | PICO_INTERNAL int PicoPicoIrqAck(int level);\r |
9037e45d |
868 | \r |
c8d1e9b6 |
869 | // pico/xpcm.c\r |
ef4eb506 |
870 | PICO_INTERNAL void PicoPicoPCMUpdate(short *buffer, int length, int stereo);\r |
f1b425e3 |
871 | PICO_INTERNAL void PicoPicoPCMResetN(int pin);\r |
872 | PICO_INTERNAL void PicoPicoPCMStartN(int pin);\r |
873 | PICO_INTERNAL int PicoPicoPCMBusyN(void);\r |
874 | PICO_INTERNAL void PicoPicoPCMGain(int gain);\r |
875 | PICO_INTERNAL void PicoPicoPCMFilter(int index);\r |
876 | PICO_INTERNAL void PicoPicoPCMIrqEn(int enable);\r |
877 | PICO_INTERNAL void PicoPicoPCMRerate(void);\r |
fa4e0531 |
878 | PICO_INTERNAL int PicoPicoPCMSave(void *buffer, int length);\r |
879 | PICO_INTERNAL void PicoPicoPCMLoad(void *buffer, int length);\r |
ef4eb506 |
880 | \r |
c8d1e9b6 |
881 | // sek.c\r |
2aa27095 |
882 | PICO_INTERNAL void SekInit(void);\r |
883 | PICO_INTERNAL int SekReset(void);\r |
3aa1e148 |
884 | PICO_INTERNAL void SekState(int *data);\r |
eff55556 |
885 | PICO_INTERNAL void SekSetRealTAS(int use_real);\r |
b4db550e |
886 | PICO_INTERNAL void SekPackCpu(unsigned char *cpu, int is_sub);\r |
887 | PICO_INTERNAL void SekUnpackCpu(const unsigned char *cpu, int is_sub);\r |
5f9a0d16 |
888 | void SekStepM68k(void);\r |
053fd9b4 |
889 | void SekInitIdleDet(void);\r |
890 | void SekFinishIdleDet(void);\r |
12da51c2 |
891 | #if defined(CPU_CMP_R) || defined(CPU_CMP_W)\r |
892 | void SekTrace(int is_s68k);\r |
893 | #else\r |
894 | #define SekTrace(x)\r |
895 | #endif\r |
cc68a136 |
896 | \r |
c8d1e9b6 |
897 | // cd/sek.c\r |
2aa27095 |
898 | PICO_INTERNAL void SekInitS68k(void);\r |
899 | PICO_INTERNAL int SekResetS68k(void);\r |
900 | PICO_INTERNAL int SekInterruptS68k(int irq);\r |
3f23709e |
901 | void SekInterruptClearS68k(int irq);\r |
cc68a136 |
902 | \r |
7a93adeb |
903 | // sound/sound.c\r |
c9e1affc |
904 | extern short cdda_out_buffer[2*1152];\r |
43e6eaad |
905 | \r |
274fcc35 |
906 | void cdda_start_play(int lba_base, int lba_offset, int lb_len);\r |
907 | \r |
882f697a |
908 | #define YM2612_NATIVE_RATE() (((Pico.m.pal?OSC_PAL:OSC_NTSC)/7 + 3*24) / (6*24))\r |
909 | \r |
43e6eaad |
910 | void ym2612_sync_timers(int z80_cycles, int mode_old, int mode_new);\r |
ccce7ee7 |
911 | int ym2612_pack_timers(void *buf_, size_t size);\r |
912 | void ym2612_unpack_timers(const void *buf_, size_t size);\r |
bcf8175e |
913 | void ym2612_pack_state_old(void);\r |
ccce7ee7 |
914 | void ym2612_unpack_state_old(void);\r |
4b9c5888 |
915 | \r |
e53704e6 |
916 | #define TIMER_NO_OFLOW 0x70000000\r |
917 | \r |
f5c022a8 |
918 | // tA = 24*3 * (1024 - TA) / M, with M = mclock/2\r |
919 | #define TIMER_A_TICK_ZCYCLES cycles_68k_to_z80(256LL* 24*3*2) // Q8\r |
920 | // tB = 16*24*3 * ( 256 - TB) / M\r |
921 | #define TIMER_B_TICK_ZCYCLES cycles_68k_to_z80(256LL*16*24*3*2) // Q8\r |
922 | // busy = 32*3 / M\r |
923 | #define YMBUSY_ZCYCLES cycles_68k_to_z80(256LL* 32*3*2) // Q8\r |
c3d70d13 |
924 | \r |
925 | #define timers_cycle(ticks) \\r |
83025d7a |
926 | if (Pico.t.ym2612_busy > 0) \\r |
927 | Pico.t.ym2612_busy -= ticks << 8; \\r |
0e2e188e |
928 | if (Pico.t.timer_a_next_oflow < TIMER_NO_OFLOW) \\r |
c3d70d13 |
929 | Pico.t.timer_a_next_oflow -= ticks << 8; \\r |
0e2e188e |
930 | if (Pico.t.timer_b_next_oflow < TIMER_NO_OFLOW) \\r |
c3d70d13 |
931 | Pico.t.timer_b_next_oflow -= ticks << 8; \\r |
43e6eaad |
932 | ym2612_sync_timers(0, ym2612.OPN.ST.mode, ym2612.OPN.ST.mode);\r |
4b9c5888 |
933 | \r |
934 | #define timers_reset() \\r |
83025d7a |
935 | Pico.t.ym2612_busy = 0; \\r |
6311a3ba |
936 | Pico.t.timer_a_next_oflow = Pico.t.timer_b_next_oflow = TIMER_NO_OFLOW; \\r |
937 | Pico.t.timer_a_step = TIMER_A_TICK_ZCYCLES * 1024; \\r |
7aab4768 |
938 | Pico.t.timer_b_step = TIMER_B_TICK_ZCYCLES * 256; \\r |
939 | ym2612.OPN.ST.status &= ~3;\r |
43e6eaad |
940 | \r |
c8d1e9b6 |
941 | // videoport.c\r |
15eed405 |
942 | extern u32 SATaddr, SATmask;\r |
bd73e6ee |
943 | static __inline void UpdateSAT(u32 a, u32 d)\r |
944 | {\r |
e721f801 |
945 | unsigned num = (a^SATaddr) >> 3;\r |
bd73e6ee |
946 | \r |
947 | Pico.est.rendstatus |= PDRAW_DIRTY_SPRITES;\r |
ac891449 |
948 | ((u16 *)&VdpSATCache[2*num])[(a&7) >> 1] = d;\r |
bd73e6ee |
949 | }\r |
950 | static __inline void VideoWriteVRAM(u32 a, u16 d)\r |
951 | {\r |
952 | PicoMem.vram [(u16)a >> 1] = d;\r |
953 | \r |
3618d636 |
954 | if (((a^SATaddr) & SATmask) == 0)\r |
bd73e6ee |
955 | UpdateSAT(a, d);\r |
956 | }\r |
957 | \r |
46b4c1d3 |
958 | static __inline u8 PicoVideoGetV(int scanline, int maywrap)\r |
70216221 |
959 | {\r |
46b4c1d3 |
960 | if (maywrap && scanline >= Pico.t.vcnt_wrap) scanline -= Pico.t.vcnt_adj;\r |
424c5f20 |
961 | if ((Pico.video.reg[12]&6) == 6) scanline = (scanline<<1)|(scanline>>8);\r |
70216221 |
962 | return scanline;\r |
963 | }\r |
964 | \r |
15eed405 |
965 | PICO_INTERNAL_ASM void PicoVideoWrite(u32 a,unsigned short d);\r |
966 | PICO_INTERNAL_ASM u32 PicoVideoRead(u32 a);\r |
1613ec6c |
967 | unsigned char PicoVideoRead8DataH(int is_from_z80);\r |
968 | unsigned char PicoVideoRead8DataL(int is_from_z80);\r |
969 | unsigned char PicoVideoRead8CtlH(int is_from_z80);\r |
970 | unsigned char PicoVideoRead8CtlL(int is_from_z80);\r |
971 | unsigned char PicoVideoRead8HV_H(int is_from_z80);\r |
972 | unsigned char PicoVideoRead8HV_L(int is_from_z80);\r |
4cc0fcaf |
973 | extern int (*PicoDmaHook)(u32 source, int len, unsigned short **base, u32 *mask);\r |
17bd69ad |
974 | void PicoVideoFIFOSync(int cycles);\r |
975 | int PicoVideoFIFOHint(void);\r |
c55a44a8 |
976 | void PicoVideoFIFOMode(int active, int h40);\r |
17bd69ad |
977 | int PicoVideoFIFOWrite(int count, int byte_p, unsigned sr_mask, unsigned sr_flags);\r |
1886ac5f |
978 | void PicoVideoInit(void);\r |
51d6248b |
979 | void PicoVideoReset(void);\r |
f9ed9446 |
980 | void PicoVideoSync(int skip);\r |
d4b5888a |
981 | int PicoVideoSave(void *buf);\r |
982 | void PicoVideoLoad(void *buf, int len);\r |
4496577e |
983 | void PicoVideoCacheSAT(int load);\r |
cc68a136 |
984 | \r |
c8d1e9b6 |
985 | // misc.c\r |
eff55556 |
986 | PICO_INTERNAL_ASM void memcpy16bswap(unsigned short *dest, void *src, int count);\r |
fbba0ff6 |
987 | PICO_INTERNAL_ASM void memset32(void *dest, int c, int count);\r |
257baf15 |
988 | PICO_INTERNAL_ASM void memset32_uncached(int *dest, int c, int count);\r |
cc68a136 |
989 | \r |
45f2f245 |
990 | // eeprom.c\r |
991 | void EEPROM_write8(unsigned int a, unsigned int d);\r |
992 | void EEPROM_write16(unsigned int d);\r |
993 | unsigned int EEPROM_read(void);\r |
994 | \r |
c8d1e9b6 |
995 | // z80 functionality wrappers\r |
996 | PICO_INTERNAL void z80_init(void);\r |
b4db550e |
997 | PICO_INTERNAL void z80_pack(void *data);\r |
998 | PICO_INTERNAL int z80_unpack(const void *data);\r |
c8d1e9b6 |
999 | PICO_INTERNAL void z80_reset(void);\r |
1000 | PICO_INTERNAL void z80_exit(void);\r |
c8d1e9b6 |
1001 | \r |
1002 | // cd/misc.c\r |
eff55556 |
1003 | PICO_INTERNAL_ASM void wram_2M_to_1M(unsigned char *m);\r |
1004 | PICO_INTERNAL_ASM void wram_1M_to_2M(unsigned char *m);\r |
1005 | \r |
eff55556 |
1006 | // sound/sound.c\r |
a2f24bfa |
1007 | PICO_INTERNAL void PsndInit(void);\r |
1008 | PICO_INTERNAL void PsndExit(void);\r |
9d917eea |
1009 | PICO_INTERNAL void PsndReset(void);\r |
4f2cdbf5 |
1010 | PICO_INTERNAL void PsndStartFrame(void);\r |
43e14010 |
1011 | PICO_INTERNAL void PsndDoDAC(int cycle_to);\r |
86d6fb9a |
1012 | PICO_INTERNAL void PsndDoPSG(int cyc_to);\r |
1013 | PICO_INTERNAL void PsndDoYM2413(int cyc_to);\r |
1014 | PICO_INTERNAL void PsndDoFM(int cyc_to);\r |
e348af76 |
1015 | PICO_INTERNAL void PsndDoPCM(int cyc_to);\r |
9d917eea |
1016 | PICO_INTERNAL void PsndClear(void);\r |
7b3f44c6 |
1017 | PICO_INTERNAL void PsndGetSamples(int y);\r |
8ac9ab7f |
1018 | PICO_INTERNAL void PsndGetSamplesMS(int y);\r |
cc68a136 |
1019 | \r |
3e49ffd0 |
1020 | // sms.c\r |
f3a57b2d |
1021 | #ifndef NO_SMS\r |
3e49ffd0 |
1022 | void PicoPowerMS(void);\r |
2ec9bec5 |
1023 | void PicoResetMS(void);\r |
3e49ffd0 |
1024 | void PicoMemSetupMS(void);\r |
b4db550e |
1025 | void PicoStateLoadedMS(void);\r |
3e49ffd0 |
1026 | void PicoFrameMS(void);\r |
87b0845f |
1027 | void PicoFrameDrawOnlyMS(void);\r |
92064e2f |
1028 | int PicoPlayTape(const char *fname);\r |
1029 | int PicoRecordTape(const char *fname);\r |
1030 | void PicoCloseTape(void);\r |
f3a57b2d |
1031 | #else\r |
1032 | #define PicoPowerMS()\r |
1033 | #define PicoResetMS()\r |
1034 | #define PicoMemSetupMS()\r |
1035 | #define PicoStateLoadedMS()\r |
1036 | #define PicoFrameMS()\r |
1037 | #define PicoFrameDrawOnlyMS()\r |
92064e2f |
1038 | #define PicoPlayTape(f) 1\r |
1039 | #define PicoRecordTape(f) 1\r |
1040 | #define PicoCloseTape()\r |
f3a57b2d |
1041 | #endif\r |
3e49ffd0 |
1042 | \r |
be2c4208 |
1043 | // 32x/32x.c\r |
f3a57b2d |
1044 | #ifndef NO_32X\r |
be2c4208 |
1045 | extern struct Pico32x Pico32x;\r |
6a98f03e |
1046 | enum p32x_event {\r |
1047 | P32X_EVENT_PWM,\r |
1048 | P32X_EVENT_FILLEND,\r |
5ac99d9a |
1049 | P32X_EVENT_HINT,\r |
6a98f03e |
1050 | P32X_EVENT_COUNT,\r |
1051 | };\r |
ae214f1c |
1052 | extern unsigned int p32x_event_times[P32X_EVENT_COUNT];\r |
6a98f03e |
1053 | \r |
be2c4208 |
1054 | void Pico32xInit(void);\r |
974fdb5b |
1055 | void PicoPower32x(void);\r |
be2c4208 |
1056 | void PicoReset32x(void);\r |
974fdb5b |
1057 | void Pico32xStartup(void);\r |
9961d9fd |
1058 | void Pico32xShutdown(void);\r |
5e49c3a8 |
1059 | void PicoUnload32x(void);\r |
974fdb5b |
1060 | void PicoFrame32x(void);\r |
2322260c |
1061 | void Pico32xDrawSync(SH2 *sh2);\r |
27e26273 |
1062 | void Pico32xStateLoaded(int is_early);\r |
3d7abd69 |
1063 | void Pico32xPrepare(void);\r |
ed4402a7 |
1064 | void p32x_sync_sh2s(unsigned int m68k_target);\r |
19886062 |
1065 | void p32x_sync_other_sh2(SH2 *sh2, unsigned int m68k_target);\r |
d40a5af4 |
1066 | void p32x_update_irls(SH2 *active_sh2, unsigned int m68k_cycles);\r |
1067 | void p32x_trigger_irq(SH2 *sh2, unsigned int m68k_cycles, unsigned int mask);\r |
1068 | void p32x_update_cmd_irq(SH2 *sh2, unsigned int m68k_cycles);\r |
83ff19ec |
1069 | void p32x_reset_sh2s(void);\r |
19886062 |
1070 | void p32x_event_schedule(unsigned int now, enum p32x_event event, int after);\r |
1071 | void p32x_event_schedule_sh2(SH2 *sh2, enum p32x_event event, int after);\r |
d40a5af4 |
1072 | void p32x_schedule_hint(SH2 *sh2, unsigned int m68k_cycles);\r |
a8fd6e37 |
1073 | \r |
52055c13 |
1074 | #define p32x_sh2_ready(sh2, cycles) \\r |
1075 | (CYCLES_GT(cycles,sh2->m68krcycles_done) && \\r |
1076 | !(sh2->state&(SH2_STATE_CPOLL|SH2_STATE_VPOLL|SH2_STATE_RPOLL)))\r |
1077 | \r |
be2c4208 |
1078 | // 32x/memory.c\r |
88fd63ad |
1079 | extern struct Pico32xMem *Pico32xMem;\r |
1bee7148 |
1080 | u32 PicoRead8_32x(u32 a);\r |
1081 | u32 PicoRead16_32x(u32 a);\r |
182b8d01 |
1082 | void PicoWrite8_32x(u32 a, u32 d);\r |
1083 | void PicoWrite16_32x(u32 a, u32 d);\r |
be2c4208 |
1084 | void PicoMemSetup32x(void);\r |
974fdb5b |
1085 | void Pico32xSwapDRAM(int b);\r |
27e26273 |
1086 | void Pico32xMemStateLoaded(void);\r |
8b9dbcde |
1087 | void p32x_update_banks(void);\r |
d8a897a6 |
1088 | void p32x_m68k_poll_event(u32 a, u32 flags);\r |
1bee7148 |
1089 | u32 REGPARM(3) p32x_sh2_poll_memory8(u32 a, u32 d, SH2 *sh2);\r |
1090 | u32 REGPARM(3) p32x_sh2_poll_memory16(u32 a, u32 d, SH2 *sh2);\r |
1091 | u32 REGPARM(3) p32x_sh2_poll_memory32(u32 a, u32 d, SH2 *sh2);\r |
1092 | void *p32x_sh2_get_mem_ptr(u32 a, u32 *mask, SH2 *sh2);\r |
fe8f2d96 |
1093 | int p32x_sh2_mem_is_rom(u32 a, SH2 *sh2);\r |
182b8d01 |
1094 | void p32x_sh2_poll_detect(u32 a, SH2 *sh2, u32 flags, int maxcnt);\r |
d8a897a6 |
1095 | void p32x_sh2_poll_event(u32 a, SH2 *sh2, u32 flags, u32 m68k_cycles);\r |
182b8d01 |
1096 | int p32x_sh2_memcpy(u32 dst, u32 src, int count, int size, SH2 *sh2);\r |
974fdb5b |
1097 | \r |
1098 | // 32x/draw.c\r |
41946d70 |
1099 | void PicoDrawSetOutFormat32x(pdso_t which, int use_32x_line_mode);\r |
b1a047c9 |
1100 | void PicoDrawSetOutBuf32X(void *dest, int increment);\r |
ea38612f |
1101 | void FinalizeLine32xRGB555(int sh, int line, struct PicoEState *est);\r |
5a681086 |
1102 | void PicoDraw32xLayer(int offs, int lines, int mdbg);\r |
7a961c19 |
1103 | void PicoDraw32xLayerMdOnly(int offs, int lines);\r |
f4750ee0 |
1104 | extern int (*PicoScan32xBegin)(unsigned int num);\r |
1105 | extern int (*PicoScan32xEnd)(unsigned int num);\r |
7a961c19 |
1106 | enum {\r |
1107 | PDM32X_OFF,\r |
1108 | PDM32X_32X_ONLY,\r |
1109 | PDM32X_BOTH,\r |
1110 | };\r |
5a681086 |
1111 | extern int Pico32xDrawMode;\r |
be2c4208 |
1112 | \r |
db1d3564 |
1113 | // 32x/pwm.c\r |
15eed405 |
1114 | unsigned int p32x_pwm_read16(u32 a, SH2 *sh2, unsigned int m68k_cycles);\r |
1115 | void p32x_pwm_write16(u32 a, unsigned int d, SH2 *sh2, unsigned int m68k_cycles);\r |
f7741cac |
1116 | void p32x_pwm_update(s32 *buf32, int length, int stereo);\r |
045a4c52 |
1117 | void p32x_pwm_ctl_changed(void);\r |
df63f1a6 |
1118 | void p32x_pwm_schedule(unsigned int m68k_now);\r |
19886062 |
1119 | void p32x_pwm_schedule_sh2(SH2 *sh2);\r |
9e1fa0a6 |
1120 | void p32x_pwm_sync_to_sh2(SH2 *sh2);\r |
df63f1a6 |
1121 | void p32x_pwm_irq_event(unsigned int m68k_now);\r |
1122 | void p32x_pwm_state_loaded(void);\r |
045a4c52 |
1123 | \r |
1124 | // 32x/sh2soc.c\r |
1125 | void p32x_dreq0_trigger(void);\r |
1126 | void p32x_dreq1_trigger(void);\r |
1127 | void p32x_timers_recalc(void);\r |
74cc7aeb |
1128 | void p32x_timer_do(SH2 *sh2, unsigned int m68k_slice);\r |
cd0ace28 |
1129 | void sh2_peripheral_reset(SH2 *sh2);\r |
182b8d01 |
1130 | u32 REGPARM(2) sh2_peripheral_read8(u32 a, SH2 *sh2);\r |
1131 | u32 REGPARM(2) sh2_peripheral_read16(u32 a, SH2 *sh2);\r |
1132 | u32 REGPARM(2) sh2_peripheral_read32(u32 a, SH2 *sh2);\r |
1133 | void REGPARM(3) sh2_peripheral_write8(u32 a, u32 d, SH2 *sh2);\r |
1134 | void REGPARM(3) sh2_peripheral_write16(u32 a, u32 d, SH2 *sh2);\r |
1135 | void REGPARM(3) sh2_peripheral_write32(u32 a, u32 d, SH2 *sh2);\r |
045a4c52 |
1136 | \r |
f3a57b2d |
1137 | #else\r |
1138 | #define Pico32xInit()\r |
1139 | #define PicoPower32x()\r |
1140 | #define PicoReset32x()\r |
1141 | #define PicoFrame32x()\r |
1142 | #define PicoUnload32x()\r |
1143 | #define Pico32xStateLoaded()\r |
f3a57b2d |
1144 | #define FinalizeLine32xRGB555 NULL\r |
1145 | #define p32x_pwm_update(...)\r |
1146 | #define p32x_timers_recalc()\r |
1147 | #endif\r |
db1d3564 |
1148 | \r |
45f2f245 |
1149 | /* avoid dependency on newer glibc */\r |
1150 | static __inline int isspace_(int c)\r |
1151 | {\r |
1152 | return (0x09 <= c && c <= 0x0d) || c == ' ';\r |
1153 | }\r |
1154 | \r |
f4bb5d6b |
1155 | #ifndef ARRAY_SIZE\r |
1156 | #define ARRAY_SIZE(x) (sizeof(x) / sizeof(x[0]))\r |
1157 | #endif\r |
1158 | \r |
b8cbd802 |
1159 | // emulation event logging\r |
1160 | #ifndef EL_LOGMASK\r |
9c9cda8c |
1161 | # ifdef __x86_64__ // HACK\r |
91be5ebd |
1162 | # define EL_LOGMASK (EL_STATUS|EL_ANOMALY)\r |
9c9cda8c |
1163 | # else\r |
1555935b |
1164 | # define EL_LOGMASK (EL_STATUS)\r |
9c9cda8c |
1165 | # endif\r |
b8cbd802 |
1166 | #endif\r |
1167 | \r |
017512f2 |
1168 | #define EL_HVCNT 0x00000001 /* hv counter reads */\r |
1169 | #define EL_SR 0x00000002 /* SR reads */\r |
1170 | #define EL_INTS 0x00000004 /* ints and acks */\r |
43e6eaad |
1171 | #define EL_YMTIMER 0x00000008 /* ym2612 timer stuff */\r |
017512f2 |
1172 | #define EL_INTSW 0x00000010 /* log irq switching on/off */\r |
1173 | #define EL_ASVDP 0x00000020 /* VDP accesses during active scan */\r |
1174 | #define EL_VDPDMA 0x00000040 /* VDP DMA transfers and their timing */\r |
1175 | #define EL_BUSREQ 0x00000080 /* z80 busreq r/w or reset w */\r |
1176 | #define EL_Z80BNK 0x00000100 /* z80 i/o through bank area */\r |
1177 | #define EL_SRAMIO 0x00000200 /* sram i/o */\r |
1178 | #define EL_EEPROM 0x00000400 /* eeprom debug */\r |
1179 | #define EL_UIO 0x00000800 /* unmapped i/o */\r |
1180 | #define EL_IO 0x00001000 /* all i/o */\r |
1181 | #define EL_CDPOLL 0x00002000 /* MCD: log poll detection */\r |
1182 | #define EL_SVP 0x00004000 /* SVP stuff */\r |
fa22af4c |
1183 | #define EL_PICOHW 0x00008000 /* Pico stuff */\r |
053fd9b4 |
1184 | #define EL_IDLE 0x00010000 /* idle loop det. */\r |
af37bca8 |
1185 | #define EL_CDREGS 0x00020000 /* MCD: register access */\r |
1186 | #define EL_CDREG3 0x00040000 /* MCD: register 3 only */\r |
be2c4208 |
1187 | #define EL_32X 0x00080000\r |
1b3f5844 |
1188 | #define EL_PWM 0x00100000 /* 32X PWM stuff (LOTS of output) */\r |
045a4c52 |
1189 | #define EL_32XP 0x00200000 /* 32X peripherals */\r |
ae214f1c |
1190 | #define EL_CD 0x00400000 /* MCD */\r |
017512f2 |
1191 | \r |
1192 | #define EL_STATUS 0x40000000 /* status messages */\r |
1193 | #define EL_ANOMALY 0x80000000 /* some unexpected conditions (during emulation) */\r |
b8cbd802 |
1194 | \r |
1195 | #if EL_LOGMASK\r |
1196 | #define elprintf(w,f,...) \\r |
a8fd6e37 |
1197 | do { \\r |
b8cbd802 |
1198 | if ((w) & EL_LOGMASK) \\r |
7d0143a2 |
1199 | lprintf("%05i:%03i: " f "\n",Pico.m.frame_count,Pico.m.scanline,##__VA_ARGS__); \\r |
a8fd6e37 |
1200 | } while (0)\r |
dca310c4 |
1201 | #elif defined(_MSC_VER)\r |
1202 | #define elprintf\r |
b8cbd802 |
1203 | #else\r |
1204 | #define elprintf(w,f,...)\r |
1205 | #endif\r |
1206 | \r |
f6c49d38 |
1207 | // profiling\r |
1208 | #ifdef PPROF\r |
1209 | #include <platform/linux/pprof.h>\r |
1210 | #else\r |
1211 | #define pprof_init()\r |
1212 | #define pprof_finish()\r |
1213 | #define pprof_start(x)\r |
1214 | #define pprof_end(...)\r |
1215 | #define pprof_end_sub(...)\r |
1216 | #endif\r |
1217 | \r |
19886062 |
1218 | #ifdef EVT_LOG\r |
1219 | enum evt {\r |
1220 | EVT_FRAME_START,\r |
1221 | EVT_NEXT_LINE,\r |
1222 | EVT_RUN_START,\r |
1223 | EVT_RUN_END,\r |
1224 | EVT_POLL_START,\r |
1225 | EVT_POLL_END,\r |
1226 | EVT_CNT\r |
1227 | };\r |
1228 | \r |
1229 | enum evt_cpu {\r |
1230 | EVT_M68K,\r |
1231 | EVT_S68K,\r |
1232 | EVT_MSH2,\r |
1233 | EVT_SSH2,\r |
1234 | EVT_CPU_CNT\r |
1235 | };\r |
1236 | \r |
1237 | void pevt_log(unsigned int cycles, enum evt_cpu c, enum evt e);\r |
1238 | void pevt_dump(void);\r |
1239 | \r |
1240 | #define pevt_log_m68k(e) \\r |
08769494 |
1241 | pevt_log(SekCyclesDone(), EVT_M68K, e)\r |
19886062 |
1242 | #define pevt_log_m68k_o(e) \\r |
08769494 |
1243 | pevt_log(SekCyclesDone(), EVT_M68K, e)\r |
19886062 |
1244 | #define pevt_log_sh2(sh2, e) \\r |
1245 | pevt_log(sh2_cycles_done_m68k(sh2), EVT_MSH2 + (sh2)->is_slave, e)\r |
1246 | #define pevt_log_sh2_o(sh2, e) \\r |
1247 | pevt_log((sh2)->m68krcycles_done, EVT_MSH2 + (sh2)->is_slave, e)\r |
1248 | #else\r |
1249 | #define pevt_log(c, e)\r |
1250 | #define pevt_log_m68k(e)\r |
1251 | #define pevt_log_m68k_o(e)\r |
1252 | #define pevt_log_sh2(sh2, e)\r |
1253 | #define pevt_log_sh2_o(sh2, e)\r |
1254 | #define pevt_dump()\r |
1255 | #endif\r |
1256 | \r |
f8af9634 |
1257 | #ifdef __cplusplus\r |
1258 | } // End of extern "C"\r |
1259 | #endif\r |
1260 | \r |
eff55556 |
1261 | #endif // PICO_INTERNAL_INCLUDED\r |
1262 | \r |
3162a710 |
1263 | // vim:shiftwidth=2:ts=2:expandtab\r |