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improve cue handling a bit
[picodrive.git] / pico / pico_int.h
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cff531af 1/*\r
2 * PicoDrive - Internal Header File\r
3 * (c) Copyright Dave, 2004\r
4 * (C) notaz, 2006-2010\r
5 *\r
6 * This work is licensed under the terms of MAME license.\r
7 * See COPYING file in the top-level directory.\r
8 */\r
cc68a136 9\r
eff55556 10#ifndef PICO_INTERNAL_INCLUDED\r
11#define PICO_INTERNAL_INCLUDED\r
cc68a136 12\r
13#include <stdio.h>\r
14#include <stdlib.h>\r
15#include <string.h>\r
efcba75f 16#include "pico.h"\r
f53f286a 17#include "carthw/carthw.h"\r
cc68a136 18\r
89fa852d 19//\r
20#define USE_POLL_DETECT\r
21\r
eff55556 22#ifndef PICO_INTERNAL\r
23#define PICO_INTERNAL\r
24#endif\r
25#ifndef PICO_INTERNAL_ASM\r
26#define PICO_INTERNAL_ASM\r
27#endif\r
cc68a136 28\r
70357ce5 29// to select core, define EMU_C68K, EMU_M68K or EMU_F68K in your makefile or project\r
cc68a136 30\r
31#ifdef __cplusplus\r
32extern "C" {\r
33#endif\r
34\r
35\r
36// ----------------------- 68000 CPU -----------------------\r
37#ifdef EMU_C68K\r
d4d62665 38#include "../cpu/cyclone/Cyclone.h"\r
3aa1e148 39extern struct Cyclone PicoCpuCM68k, PicoCpuCS68k;\r
ae214f1c 40#define SekCyclesLeft PicoCpuCM68k.cycles // cycles left for this run\r
41#define SekCyclesLeftS68k PicoCpuCS68k.cycles\r
3aa1e148 42#define SekPc (PicoCpuCM68k.pc-PicoCpuCM68k.membase)\r
43#define SekPcS68k (PicoCpuCS68k.pc-PicoCpuCS68k.membase)\r
12da51c2 44#define SekDar(x) (x < 8 ? PicoCpuCM68k.d[x] : PicoCpuCM68k.a[x - 8])\r
45#define SekDarS68k(x) (x < 8 ? PicoCpuCS68k.d[x] : PicoCpuCS68k.a[x - 8])\r
5fadfb1c 46#define SekSr CycloneGetSr(&PicoCpuCM68k)\r
12da51c2 47#define SekSrS68k CycloneGetSr(&PicoCpuCS68k)\r
3aa1e148 48#define SekSetStop(x) { PicoCpuCM68k.state_flags&=~1; if (x) { PicoCpuCM68k.state_flags|=1; PicoCpuCM68k.cycles=0; } }\r
49#define SekSetStopS68k(x) { PicoCpuCS68k.state_flags&=~1; if (x) { PicoCpuCS68k.state_flags|=1; PicoCpuCS68k.cycles=0; } }\r
ed4402a7 50#define SekIsStoppedM68k() (PicoCpuCM68k.state_flags&1)\r
ca61ee42 51#define SekIsStoppedS68k() (PicoCpuCS68k.state_flags&1)\r
08769494 52#define SekShouldInterrupt() (PicoCpuCM68k.irq > (PicoCpuCM68k.srh&7))\r
b542be46 53\r
54#define SekInterrupt(i) PicoCpuCM68k.irq=i\r
5fadfb1c 55#define SekIrqLevel PicoCpuCM68k.irq\r
b542be46 56\r
cc68a136 57#endif\r
58\r
70357ce5 59#ifdef EMU_F68K\r
60#include "../cpu/fame/fame.h"\r
b542be46 61extern M68K_CONTEXT PicoCpuFM68k, PicoCpuFS68k;\r
ae214f1c 62#define SekCyclesLeft PicoCpuFM68k.io_cycle_counter\r
63#define SekCyclesLeftS68k PicoCpuFS68k.io_cycle_counter\r
03e4f2a3 64#define SekPc fm68k_get_pc(&PicoCpuFM68k)\r
65#define SekPcS68k fm68k_get_pc(&PicoCpuFS68k)\r
12da51c2 66#define SekDar(x) (x < 8 ? PicoCpuFM68k.dreg[x].D : PicoCpuFM68k.areg[x - 8].D)\r
67#define SekDarS68k(x) (x < 8 ? PicoCpuFS68k.dreg[x].D : PicoCpuFS68k.areg[x - 8].D)\r
5fadfb1c 68#define SekSr PicoCpuFM68k.sr\r
12da51c2 69#define SekSrS68k PicoCpuFS68k.sr\r
70357ce5 70#define SekSetStop(x) { \\r
03e4f2a3 71 PicoCpuFM68k.execinfo &= ~FM68K_HALTED; \\r
72 if (x) { PicoCpuFM68k.execinfo |= FM68K_HALTED; PicoCpuFM68k.io_cycle_counter = 0; } \\r
70357ce5 73}\r
74#define SekSetStopS68k(x) { \\r
03e4f2a3 75 PicoCpuFS68k.execinfo &= ~FM68K_HALTED; \\r
76 if (x) { PicoCpuFS68k.execinfo |= FM68K_HALTED; PicoCpuFS68k.io_cycle_counter = 0; } \\r
70357ce5 77}\r
ed4402a7 78#define SekIsStoppedM68k() (PicoCpuFM68k.execinfo&FM68K_HALTED)\r
ca61ee42 79#define SekIsStoppedS68k() (PicoCpuFS68k.execinfo&FM68K_HALTED)\r
08769494 80#define SekShouldInterrupt() fm68k_would_interrupt()\r
b542be46 81\r
82#define SekInterrupt(irq) PicoCpuFM68k.interrupts[0]=irq\r
5fadfb1c 83#define SekIrqLevel PicoCpuFM68k.interrupts[0]\r
b542be46 84\r
cc68a136 85#endif\r
86\r
87#ifdef EMU_M68K\r
88#include "../cpu/musashi/m68kcpu.h"\r
3aa1e148 89extern m68ki_cpu_core PicoCpuMM68k, PicoCpuMS68k;\r
cc68a136 90#ifndef SekCyclesLeft\r
ae214f1c 91#define SekCyclesLeft PicoCpuMM68k.cyc_remaining_cycles\r
92#define SekCyclesLeftS68k PicoCpuMS68k.cyc_remaining_cycles\r
3aa1e148 93#define SekPc m68k_get_reg(&PicoCpuMM68k, M68K_REG_PC)\r
94#define SekPcS68k m68k_get_reg(&PicoCpuMS68k, M68K_REG_PC)\r
12da51c2 95#define SekDar(x) PicoCpuMM68k.dar[x]\r
96#define SekDarS68k(x) PicoCpuMS68k.dar[x]\r
97#define SekSr m68k_get_reg(&PicoCpuMM68k, M68K_REG_SR)\r
98#define SekSrS68k m68k_get_reg(&PicoCpuMS68k, M68K_REG_SR)\r
7a1f6e45 99#define SekSetStop(x) { \\r
3aa1e148 100 if(x) { SET_CYCLES(0); PicoCpuMM68k.stopped=STOP_LEVEL_STOP; } \\r
101 else PicoCpuMM68k.stopped=0; \\r
7a1f6e45 102}\r
103#define SekSetStopS68k(x) { \\r
3aa1e148 104 if(x) { SET_CYCLES(0); PicoCpuMS68k.stopped=STOP_LEVEL_STOP; } \\r
105 else PicoCpuMS68k.stopped=0; \\r
7a1f6e45 106}\r
ed4402a7 107#define SekIsStoppedM68k() (PicoCpuMM68k.stopped==STOP_LEVEL_STOP)\r
ca61ee42 108#define SekIsStoppedS68k() (PicoCpuMS68k.stopped==STOP_LEVEL_STOP)\r
08769494 109#define SekShouldInterrupt() (CPU_INT_LEVEL > FLAG_INT_MASK)\r
b542be46 110\r
71de3cd9 111#define SekInterrupt(irq) { \\r
b542be46 112 void *oldcontext = m68ki_cpu_p; \\r
113 m68k_set_context(&PicoCpuMM68k); \\r
114 m68k_set_irq(irq); \\r
115 m68k_set_context(oldcontext); \\r
116}\r
5fadfb1c 117#define SekIrqLevel (PicoCpuMM68k.int_level >> 8)\r
b542be46 118\r
cc68a136 119#endif\r
ef090115 120#endif // EMU_M68K\r
cc68a136 121\r
ae214f1c 122// while running, cnt represents target of current timeslice\r
123// while not in SekRun(), it's actual cycles done\r
124// (but always use SekCyclesDone() if you need current position)\r
125// cnt may change if timeslice is ended prematurely or extended,\r
126// so we use SekCycleAim for the actual target\r
127extern unsigned int SekCycleCnt;\r
128extern unsigned int SekCycleAim;\r
cc68a136 129\r
ae214f1c 130// number of cycles done (can be checked anywhere)\r
131#define SekCyclesDone() (SekCycleCnt - SekCyclesLeft)\r
132\r
133// burn cycles while not in SekRun() and while in\r
134#define SekCyclesBurn(c) SekCycleCnt += c\r
bc3c13d3 135#define SekCyclesBurnRun(c) { \\r
136 SekCyclesLeft -= c; \\r
b8cbd802 137}\r
cc68a136 138\r
ae214f1c 139// note: sometimes may extend timeslice to delay an irq\r
cc68a136 140#define SekEndRun(after) { \\r
ae214f1c 141 SekCycleCnt -= SekCyclesLeft - (after); \\r
142 SekCyclesLeft = after; \\r
cc68a136 143}\r
144\r
ae214f1c 145extern unsigned int SekCycleCntS68k;\r
146extern unsigned int SekCycleAimS68k;\r
147\r
07ceafdb 148#define SekEndRunS68k(after) { \\r
ae214f1c 149 if (SekCyclesLeftS68k > (after)) { \\r
150 SekCycleCntS68k -= SekCyclesLeftS68k - (after); \\r
151 SekCyclesLeftS68k = after; \\r
152 } \\r
07ceafdb 153}\r
154\r
ae214f1c 155#define SekCyclesDoneS68k() (SekCycleCntS68k - SekCyclesLeftS68k)\r
cc68a136 156\r
ae214f1c 157// compare cycles, handling overflows\r
158// check if a > b\r
159#define CYCLES_GT(a, b) \\r
160 ((int)((a) - (b)) > 0)\r
161// check if a >= b\r
162#define CYCLES_GE(a, b) \\r
163 ((int)((a) - (b)) >= 0)\r
cc68a136 164\r
b542be46 165// ----------------------- Z80 CPU -----------------------\r
166\r
b4db550e 167#if defined(_USE_DRZ80)\r
dca310c4 168#include "../cpu/DrZ80/drz80.h"\r
b542be46 169\r
170extern struct DrZ80 drZ80;\r
171\r
172#define z80_run(cycles) ((cycles) - DrZ80Run(&drZ80, cycles))\r
173#define z80_run_nr(cycles) DrZ80Run(&drZ80, cycles)\r
4936aac1 174#define z80_int() drZ80.Z80_IRQ = 1\r
835122bc 175#define z80_int() drZ80.Z80_IRQ = 1\r
176#define z80_nmi() drZ80.Z80IF |= 8\r
4b9c5888 177\r
178#define z80_cyclesLeft drZ80.cycles\r
19954be1 179#define z80_pc() (drZ80.Z80PC - drZ80.Z80PC_BASE)\r
b542be46 180\r
181#elif defined(_USE_CZ80)\r
dca310c4 182#include "../cpu/cz80/cz80.h"\r
b542be46 183\r
184#define z80_run(cycles) Cz80_Exec(&CZ80, cycles)\r
185#define z80_run_nr(cycles) Cz80_Exec(&CZ80, cycles)\r
186#define z80_int() Cz80_Set_IRQ(&CZ80, 0, HOLD_LINE)\r
835122bc 187#define z80_nmi() Cz80_Set_IRQ(&CZ80, IRQ_LINE_NMI, 0)\r
4b9c5888 188\r
189#define z80_cyclesLeft (CZ80.ICount - CZ80.ExtraCycles)\r
19954be1 190#define z80_pc() Cz80_Get_Reg(&CZ80, CZ80_PC)\r
b542be46 191\r
192#else\r
193\r
194#define z80_run(cycles) (cycles)\r
195#define z80_run_nr(cycles)\r
196#define z80_int()\r
835122bc 197#define z80_nmi()\r
b542be46 198\r
199#endif\r
200\r
b4db550e 201#define Z80_STATE_SIZE 0x60\r
202\r
ae214f1c 203extern unsigned int last_z80_sync;\r
4b9c5888 204extern int z80_cycle_cnt; /* 'done' z80 cycles before z80_run() */\r
205extern int z80_cycle_aim;\r
206extern int z80_scanline;\r
207extern int z80_scanline_cycles; /* cycles done until z80_scanline */\r
208\r
209#define z80_resetCycles() \\r
ae214f1c 210 last_z80_sync = SekCyclesDone(); \\r
4b9c5888 211 z80_cycle_cnt = z80_cycle_aim = z80_scanline = z80_scanline_cycles = 0;\r
212\r
213#define z80_cyclesDone() \\r
214 (z80_cycle_aim - z80_cyclesLeft)\r
215\r
216#define cycles_68k_to_z80(x) ((x)*957 >> 11)\r
217\r
acd35d4c 218// ----------------------- SH2 CPU -----------------------\r
219\r
41397701 220#include "cpu/sh2/sh2.h"\r
acd35d4c 221\r
1d7a28a7 222extern SH2 sh2s[2];\r
223#define msh2 sh2s[0]\r
224#define ssh2 sh2s[1]\r
225\r
679af8a3 226#ifndef DRC_SH2\r
19886062 227# define sh2_end_run(sh2, after_) do { \\r
228 if ((sh2)->icount > (after_)) { \\r
c1931173 229 (sh2)->cycles_timeslice -= (sh2)->icount - (after_); \\r
19886062 230 (sh2)->icount = after_; \\r
a8fd6e37 231 } \\r
232} while (0)\r
19886062 233# define sh2_cycles_left(sh2) (sh2)->icount\r
8a847c12 234# define sh2_burn_cycles(sh2, n) (sh2)->icount -= n\r
f81107f5 235# define sh2_pc(sh2) (sh2)->ppc\r
679af8a3 236#else\r
19886062 237# define sh2_end_run(sh2, after_) do { \\r
238 int left_ = (signed int)(sh2)->sr >> 12; \\r
239 if (left_ > (after_)) { \\r
c1931173 240 (sh2)->cycles_timeslice -= left_ - (after_); \\r
f4c0720c 241 (sh2)->sr &= 0xfff; \\r
19886062 242 (sh2)->sr |= (after_) << 12; \\r
a8fd6e37 243 } \\r
244} while (0)\r
19886062 245# define sh2_cycles_left(sh2) ((signed int)(sh2)->sr >> 12)\r
8a847c12 246# define sh2_burn_cycles(sh2, n) (sh2)->sr -= ((n) << 12)\r
f81107f5 247# define sh2_pc(sh2) (sh2)->pc\r
679af8a3 248#endif\r
266c6afa 249\r
19886062 250#define sh2_cycles_done(sh2) ((int)(sh2)->cycles_timeslice - sh2_cycles_left(sh2))\r
a7f82a77 251#define sh2_cycles_done_t(sh2) \\r
252 ((sh2)->m68krcycles_done * 3 + sh2_cycles_done(sh2))\r
19886062 253#define sh2_cycles_done_m68k(sh2) \\r
254 ((sh2)->m68krcycles_done + (sh2_cycles_done(sh2) / 3))\r
255\r
4ea707e1 256#define sh2_reg(c, x) (c) ? ssh2.r[x] : msh2.r[x]\r
257#define sh2_gbr(c) (c) ? ssh2.gbr : msh2.gbr\r
258#define sh2_vbr(c) (c) ? ssh2.vbr : msh2.vbr\r
6add7875 259#define sh2_sr(c) (((c) ? ssh2.sr : msh2.sr) & 0xfff)\r
acd35d4c 260\r
83ff19ec 261#define sh2_set_gbr(c, v) \\r
262 { if (c) ssh2.gbr = v; else msh2.gbr = v; }\r
263#define sh2_set_vbr(c, v) \\r
264 { if (c) ssh2.vbr = v; else msh2.vbr = v; }\r
265\r
f8675e28 266#define elprintf_sh2(sh2, w, f, ...) \\r
267 elprintf(w,"%csh2 "f,(sh2)->is_slave?'s':'m',##__VA_ARGS__)\r
268\r
cc68a136 269// ---------------------------------------------------------\r
270\r
271// main oscillator clock which controls timing\r
272#define OSC_NTSC 53693100\r
b8cbd802 273#define OSC_PAL 53203424\r
cc68a136 274\r
275struct PicoVideo\r
276{\r
277 unsigned char reg[0x20];\r
b8cbd802 278 unsigned int command; // 32-bit Command\r
279 unsigned char pending; // 1 if waiting for second half of 32-bit command\r
280 unsigned char type; // Command type (v/c/vsram read/write)\r
281 unsigned short addr; // Read/Write address\r
282 int status; // Status bits\r
cc68a136 283 unsigned char pending_ints; // pending interrupts: ??VH????\r
b8cbd802 284 signed char lwrite_cnt; // VDP write count during active display line\r
9761a7d0 285 unsigned short v_counter; // V-counter\r
286 unsigned char pad[0x10];\r
cc68a136 287};\r
288\r
289struct PicoMisc\r
290{\r
291 unsigned char rotate;\r
292 unsigned char z80Run;\r
e5503e2f 293 unsigned char padTHPhase[2]; // 02 phase of gamepad TH switches\r
2aa27095 294 unsigned short scanline; // 04 0 to 261||311\r
e5503e2f 295 char dirtyPal; // 06 Is the palette dirty (1 - change @ this frame, 2 - some time before)\r
296 unsigned char hardware; // 07 Hardware value for country\r
297 unsigned char pal; // 08 1=PAL 0=NTSC\r
45f2f245 298 unsigned char sram_reg; // 09 SRAM reg. See SRR_* below\r
e5503e2f 299 unsigned short z80_bank68k; // 0a\r
be2c4208 300 unsigned short pad0;\r
301 unsigned char pad1;\r
0ace9b9a 302 unsigned char z80_reset; // 0f z80 reset held\r
e5503e2f 303 unsigned char padDelay[2]; // 10 gamepad phase time outs, so we count a delay\r
1dceadae 304 unsigned short eeprom_addr; // EEPROM address register\r
45f2f245 305 unsigned char eeprom_cycle; // EEPROM cycle number\r
1dceadae 306 unsigned char eeprom_slave; // EEPROM slave word for X24C02 and better SRAMs\r
45f2f245 307 unsigned char eeprom_status;\r
be2c4208 308 unsigned char pad2;\r
053fd9b4 309 unsigned short dma_xfers; // 18\r
45f2f245 310 unsigned char eeprom_wb[2]; // EEPROM latch/write buffer\r
053fd9b4 311 unsigned int frame_count; // 1c for movies and idle det\r
cc68a136 312};\r
313\r
b4db550e 314struct PicoMS\r
315{\r
316 unsigned char carthw[0x10];\r
317 unsigned char io_ctl;\r
835122bc 318 unsigned char nmi_state;\r
319 unsigned char pad[0x4e];\r
b4db550e 320};\r
321\r
cc68a136 322// some assembly stuff depend on these, do not touch!\r
323struct Pico\r
324{\r
325 unsigned char ram[0x10000]; // 0x00000 scratch ram\r
200772b7 326 union { // vram is byteswapped for easier reads when drawing\r
2ec9bec5 327 unsigned short vram[0x8000]; // 0x10000\r
328 unsigned char vramb[0x4000]; // VRAM in SMS mode\r
329 };\r
cc68a136 330 unsigned char zram[0x2000]; // 0x20000 Z80 ram\r
b4db550e 331 unsigned char ioports[0x10]; // XXX: fix asm and mv\r
332 unsigned char pad[0xf0]; // unused\r
cc68a136 333 unsigned short cram[0x40]; // 0x22100\r
334 unsigned short vsram[0x40]; // 0x22180\r
335\r
336 unsigned char *rom; // 0x22200\r
0219d379 337 unsigned int romsize; // 0x22204 (on 32bits)\r
cc68a136 338\r
339 struct PicoMisc m;\r
340 struct PicoVideo video;\r
b4db550e 341 struct PicoMS ms;\r
cc68a136 342};\r
343\r
344// sram\r
45f2f245 345#define SRR_MAPPED (1 << 0)\r
346#define SRR_READONLY (1 << 1)\r
347\r
348#define SRF_ENABLED (1 << 0)\r
349#define SRF_EEPROM (1 << 1)\r
af37bca8 350\r
cc68a136 351struct PicoSRAM\r
352{\r
4ff2d527 353 unsigned char *data; // actual data\r
354 unsigned int start; // start address in 68k address space\r
cc68a136 355 unsigned int end;\r
45f2f245 356 unsigned char flags; // 0c: SRF_*\r
1dceadae 357 unsigned char unused2;\r
cc68a136 358 unsigned char changed;\r
45f2f245 359 unsigned char eeprom_type; // eeprom type: 0: 7bit (24C01), 2: 2 addr words (X24C02+), 3: 3 addr words\r
360 unsigned char unused3;\r
1dceadae 361 unsigned char eeprom_bit_cl; // bit number for cl\r
362 unsigned char eeprom_bit_in; // bit number for in\r
363 unsigned char eeprom_bit_out; // bit number for out\r
45f2f245 364 unsigned int size;\r
cc68a136 365};\r
366\r
367// MCD\r
368#include "cd/cd_sys.h"\r
369#include "cd/LC89510.h"\r
d1df8786 370#include "cd/gfx_cd.h"\r
cc68a136 371\r
4f265db7 372struct mcd_pcm\r
373{\r
374 unsigned char control; // reg7\r
375 unsigned char enabled; // reg8\r
376 unsigned char cur_ch;\r
377 unsigned char bank;\r
378 int pad1;\r
379\r
4ff2d527 380 struct pcm_chan // 08, size 0x10\r
4f265db7 381 {\r
382 unsigned char regs[8];\r
4ff2d527 383 unsigned int addr; // .08: played sample address\r
4f265db7 384 int pad;\r
385 } ch[8];\r
386};\r
387\r
4fb43555 388#define PCD_ST_S68K_RST 1\r
389\r
c459aefd 390struct mcd_misc\r
391{\r
392 unsigned short hint_vector;\r
4fb43555 393 unsigned char busreq; // not s68k_regs[1]\r
51a902ae 394 unsigned char s68k_pend_ints;\r
bc3c13d3 395 unsigned int state_flags; // 04\r
ae214f1c 396 unsigned int stopwatch_base_c;\r
bc3c13d3 397 unsigned short m68k_poll_a;\r
398 unsigned short m68k_poll_cnt;\r
08769494 399 unsigned short s68k_poll_a;\r
400 unsigned short s68k_poll_cnt;\r
401 unsigned int s68k_poll_clk;\r
6cadc2da 402 unsigned char bcram_reg; // 18: battery-backed RAM cart register\r
ba6e8bfd 403 unsigned char dmna_ret_2m;\r
6cadc2da 404 unsigned short pad3;\r
ae214f1c 405 int pad4[9];\r
c459aefd 406};\r
407\r
cc68a136 408typedef struct\r
409{\r
4ff2d527 410 unsigned char bios[0x20000]; // 000000: 128K\r
411 union { // 020000: 512K\r
fa1e5e29 412 unsigned char prg_ram[0x80000];\r
cc68a136 413 unsigned char prg_ram_b[4][0x20000];\r
414 };\r
4ff2d527 415 union { // 0a0000: 256K\r
fa1e5e29 416 struct {\r
417 unsigned char word_ram2M[0x40000];\r
dca310c4 418 unsigned char unused0[0x20000];\r
fa1e5e29 419 };\r
420 struct {\r
dca310c4 421 unsigned char unused1[0x20000];\r
fa1e5e29 422 unsigned char word_ram1M[2][0x20000];\r
423 };\r
424 };\r
4ff2d527 425 union { // 100000: 64K\r
fa1e5e29 426 unsigned char pcm_ram[0x10000];\r
4f265db7 427 unsigned char pcm_ram_b[0x10][0x1000];\r
428 };\r
895d1512 429 // FIXME: should be short\r
4ff2d527 430 unsigned char s68k_regs[0x200]; // 110000: GA, not CPU regs\r
431 unsigned char bram[0x2000]; // 110200: 8K\r
432 struct mcd_misc m; // 112200: misc\r
433 struct mcd_pcm pcm; // 112240:\r
75736070 434 _scd_toc TOC; // not to be saved\r
cc68a136 435 CDD cdd;\r
436 CDC cdc;\r
437 _scd scd;\r
d1df8786 438 Rot_Comp rot_comp;\r
cc68a136 439} mcd_state;\r
440\r
be2c4208 441// XXX: this will need to be reworked for cart+cd support.\r
cc68a136 442#define Pico_mcd ((mcd_state *)Pico.rom)\r
443\r
be2c4208 444// 32X\r
acd35d4c 445#define P32XS_FM (1<<15)\r
83ff19ec 446#define P32XS_REN (1<< 7)\r
447#define P32XS_nRES (1<< 1)\r
448#define P32XS_ADEN (1<< 0)\r
acd35d4c 449#define P32XS2_ADEN (1<< 9)\r
5e128c6d 450#define P32XS_FULL (1<< 7) // DREQ FIFO full\r
4ea707e1 451#define P32XS_68S (1<< 2)\r
97d3f47f 452#define P32XS_DMA (1<< 1)\r
4ea707e1 453#define P32XS_RV (1<< 0)\r
acd35d4c 454\r
5e128c6d 455#define P32XV_nPAL (1<<15) // VDP\r
acd35d4c 456#define P32XV_PRI (1<< 7)\r
4ea707e1 457#define P32XV_Mx (3<< 0) // display mode mask\r
974fdb5b 458\r
e51e5983 459#define P32XV_SFT (1<< 0)\r
460\r
acd35d4c 461#define P32XV_VBLK (1<<15)\r
462#define P32XV_HBLK (1<<14)\r
463#define P32XV_PEN (1<<13)\r
464#define P32XV_nFEN (1<< 1)\r
465#define P32XV_FS (1<< 0)\r
974fdb5b 466\r
df63f1a6 467#define P32XP_RTP (1<<7) // PWM control\r
468#define P32XP_FULL (1<<15) // PWM pulse\r
db1d3564 469#define P32XP_EMPTY (1<<14)\r
470\r
419973a6 471#define P32XF_68KCPOLL (1 << 0)\r
472#define P32XF_68KVPOLL (1 << 1)\r
473#define P32XF_Z80_32X_IO (1 << 7) // z80 does 32x io\r
4ea707e1 474\r
475#define P32XI_VRES (1 << 14/2) // IRL/2\r
476#define P32XI_VINT (1 << 12/2)\r
477#define P32XI_HINT (1 << 10/2)\r
478#define P32XI_CMD (1 << 8/2)\r
479#define P32XI_PWM (1 << 6/2)\r
480\r
1d7a28a7 481// peripheral reg access\r
482#define PREG8(regs,offs) ((unsigned char *)regs)[offs ^ 3]\r
483\r
7eaa3812 484#define DMAC_FIFO_LEN (4*2)\r
db1d3564 485#define PWM_BUFF_LEN 1024 // in one channel samples\r
266c6afa 486\r
f4bb5d6b 487#define SH2_DRCBLK_RAM_SHIFT 1\r
488#define SH2_DRCBLK_DA_SHIFT 1\r
489\r
f81107f5 490#define SH2_READ_SHIFT 25\r
e05b81fc 491#define SH2_WRITE_SHIFT 25\r
492\r
be2c4208 493struct Pico32x\r
494{\r
495 unsigned short regs[0x20];\r
5a681086 496 unsigned short vdp_regs[0x10]; // 0x40\r
497 unsigned short sh2_regs[3]; // 0x60\r
be2c4208 498 unsigned char pending_fb;\r
974fdb5b 499 unsigned char dirty_pal;\r
266c6afa 500 unsigned int emu_flags;\r
4ea707e1 501 unsigned char sh2irq_mask[2];\r
502 unsigned char sh2irqi[2]; // individual\r
503 unsigned int sh2irqs; // common irqs\r
504 unsigned short dmac_fifo[DMAC_FIFO_LEN];\r
7eaa3812 505 unsigned int pad[4];\r
df63f1a6 506 unsigned int dmac0_fifo_ptr;\r
4a1fb183 507 unsigned short vdp_fbcr_fake;\r
7eaa3812 508 unsigned short pad2;\r
a8fd6e37 509 unsigned char comm_dirty_68k;\r
510 unsigned char comm_dirty_sh2;\r
df63f1a6 511 unsigned char pwm_irq_cnt;\r
512 unsigned char pad1;\r
a7f82a77 513 unsigned short pwm_p[2]; // pwm pos in fifo\r
514 unsigned int pwm_cycle_p; // pwm play cursor (32x cycles)\r
515 unsigned int reserved[6];\r
974fdb5b 516};\r
517\r
518struct Pico32xMem\r
519{\r
520 unsigned char sdram[0x40000];\r
f4bb5d6b 521#ifdef DRC_SH2\r
522 unsigned short drcblk_ram[1 << (18 - SH2_DRCBLK_RAM_SHIFT)];\r
523#endif\r
b78efee2 524 unsigned short dram[2][0x20000/2]; // AKA fb\r
b4db550e 525 union {\r
526 unsigned char m68k_rom[0x100];\r
527 unsigned char m68k_rom_bank[0x10000]; // M68K_BANK_SIZE\r
528 };\r
f4bb5d6b 529#ifdef DRC_SH2\r
530 unsigned short drcblk_da[2][1 << (12 - SH2_DRCBLK_DA_SHIFT)];\r
531#endif\r
895d1512 532 union {\r
533 unsigned char b[0x800];\r
534 unsigned short w[0x800/2];\r
535 } sh2_rom_m;\r
536 union {\r
537 unsigned char b[0x400];\r
538 unsigned short w[0x400/2];\r
539 } sh2_rom_s;\r
974fdb5b 540 unsigned short pal[0x100];\r
5e128c6d 541 unsigned short pal_native[0x100]; // converted to native (for renderer)\r
db1d3564 542 signed short pwm[2*PWM_BUFF_LEN]; // PWM buffer for current frame\r
8ce9c3a7 543 signed short pwm_current[2]; // current converted samples\r
544 unsigned short pwm_fifo[2][4]; // [0] - current raw, others - fifo entries\r
be2c4208 545};\r
d49b10c2 546\r
c8d1e9b6 547// area.c\r
fad24893 548extern void (*PicoLoadStateHook)(void);\r
51a902ae 549\r
945c2fdc 550typedef struct {\r
551 int chunk;\r
552 int size;\r
553 void *ptr;\r
554} carthw_state_chunk;\r
555extern carthw_state_chunk *carthw_chunks;\r
556#define CHUNK_CARTHW 64\r
557\r
c8d1e9b6 558// cart.c\r
b4db550e 559extern int PicoCartResize(int newsize);\r
560extern void Byteswap(void *dst, const void *src, int len);\r
45f2f245 561extern void (*PicoCartMemSetup)(void);\r
e807ac75 562extern void (*PicoCartUnloadHook)(void);\r
1dceadae 563\r
c8d1e9b6 564// debug.c\r
b5e5172d 565int CM_compareRun(int cyc, int is_sub);\r
03e4f2a3 566\r
c8d1e9b6 567// draw.c\r
eff55556 568PICO_INTERNAL void PicoFrameStart(void);\r
b6d7ac70 569void PicoDrawSync(int to, int blank_last_line);\r
200772b7 570void BackFill(int reg7, int sh);\r
5a681086 571void FinalizeLine555(int sh, int line);\r
f4750ee0 572extern int (*PicoScanBegin)(unsigned int num);\r
573extern int (*PicoScanEnd)(unsigned int num);\r
b6d7ac70 574extern int DrawScanline;\r
f579f7b8 575#define MAX_LINE_SPRITES 29\r
576extern unsigned char HighLnSpr[240][3 + MAX_LINE_SPRITES];\r
5a681086 577extern void *DrawLineDestBase;\r
578extern int DrawLineDestIncrement;\r
cc68a136 579\r
c8d1e9b6 580// draw2.c\r
eff55556 581PICO_INTERNAL void PicoFrameFull();\r
cc68a136 582\r
200772b7 583// mode4.c\r
584void PicoFrameStartMode4(void);\r
585void PicoLineMode4(int line);\r
586void PicoDoHighPal555M4(void);\r
5a681086 587void PicoDrawSetOutputMode4(pdso_t which);\r
200772b7 588\r
c8d1e9b6 589// memory.c\r
eff55556 590PICO_INTERNAL void PicoMemSetup(void);\r
af37bca8 591unsigned int PicoRead8_io(unsigned int a);\r
592unsigned int PicoRead16_io(unsigned int a);\r
593void PicoWrite8_io(unsigned int a, unsigned int d);\r
594void PicoWrite16_io(unsigned int a, unsigned int d);\r
595\r
596// pico/memory.c\r
597PICO_INTERNAL void PicoMemSetupPico(void);\r
cc68a136 598\r
c8d1e9b6 599// cd/memory.c\r
eff55556 600PICO_INTERNAL void PicoMemSetupCD(void);\r
ae214f1c 601void pcd_state_loaded_mem(void);\r
cc68a136 602\r
c8d1e9b6 603// pico.c\r
cc68a136 604extern struct Pico Pico;\r
605extern struct PicoSRAM SRam;\r
5f9a0d16 606extern int PicoPadInt[2];\r
cc68a136 607extern int emustatus;\r
5e128c6d 608extern int scanlines_total;\r
f8ef8ff7 609extern void (*PicoResetHook)(void);\r
b0677887 610extern void (*PicoLineHook)(void);\r
1e6b5e39 611PICO_INTERNAL int CheckDMA(void);\r
612PICO_INTERNAL void PicoDetectRegion(void);\r
ae214f1c 613PICO_INTERNAL void PicoSyncZ80(unsigned int m68k_cycles_done);\r
cc68a136 614\r
89dbbf2b 615// cd/mcd.c\r
ae214f1c 616#define PCDS_IEN1 (1<<1)\r
617#define PCDS_IEN2 (1<<2)\r
618#define PCDS_IEN3 (1<<3)\r
619#define PCDS_IEN4 (1<<4)\r
620#define PCDS_IEN5 (1<<5)\r
621#define PCDS_IEN6 (1<<6)\r
cc68a136 622\r
2aa27095 623PICO_INTERNAL void PicoInitMCD(void);\r
e5f426aa 624PICO_INTERNAL void PicoExitMCD(void);\r
1cb1584b 625PICO_INTERNAL void PicoPowerMCD(void);\r
2aa27095 626PICO_INTERNAL int PicoResetMCD(void);\r
627PICO_INTERNAL void PicoFrameMCD(void);\r
cc68a136 628\r
ae214f1c 629enum pcd_event {\r
630 PCD_EVENT_CDC,\r
631 PCD_EVENT_TIMER3,\r
632 PCD_EVENT_GFX,\r
633 PCD_EVENT_DMA,\r
634 PCD_EVENT_COUNT,\r
635};\r
636extern unsigned int pcd_event_times[PCD_EVENT_COUNT];\r
637void pcd_event_schedule(unsigned int now, enum pcd_event event, int after);\r
638void pcd_event_schedule_s68k(enum pcd_event event, int after);\r
639unsigned int pcd_cycles_m68k_to_s68k(unsigned int c);\r
08769494 640int pcd_sync_s68k(unsigned int m68k_target, int m68k_poll_sync);\r
ae214f1c 641void pcd_state_loaded(void);\r
642\r
c8d1e9b6 643// pico/pico.c\r
2aa27095 644PICO_INTERNAL void PicoInitPico(void);\r
ed367a3f 645PICO_INTERNAL void PicoReratePico(void);\r
9037e45d 646\r
c8d1e9b6 647// pico/xpcm.c\r
ef4eb506 648PICO_INTERNAL void PicoPicoPCMUpdate(short *buffer, int length, int stereo);\r
649PICO_INTERNAL void PicoPicoPCMReset(void);\r
213c16ad 650PICO_INTERNAL void PicoPicoPCMRerate(int xpcm_rate);\r
ef4eb506 651\r
c8d1e9b6 652// sek.c\r
2aa27095 653PICO_INTERNAL void SekInit(void);\r
654PICO_INTERNAL int SekReset(void);\r
3aa1e148 655PICO_INTERNAL void SekState(int *data);\r
eff55556 656PICO_INTERNAL void SekSetRealTAS(int use_real);\r
b4db550e 657PICO_INTERNAL void SekPackCpu(unsigned char *cpu, int is_sub);\r
658PICO_INTERNAL void SekUnpackCpu(const unsigned char *cpu, int is_sub);\r
5f9a0d16 659void SekStepM68k(void);\r
053fd9b4 660void SekInitIdleDet(void);\r
661void SekFinishIdleDet(void);\r
12da51c2 662#if defined(CPU_CMP_R) || defined(CPU_CMP_W)\r
663void SekTrace(int is_s68k);\r
664#else\r
665#define SekTrace(x)\r
666#endif\r
cc68a136 667\r
c8d1e9b6 668// cd/sek.c\r
2aa27095 669PICO_INTERNAL void SekInitS68k(void);\r
670PICO_INTERNAL int SekResetS68k(void);\r
671PICO_INTERNAL int SekInterruptS68k(int irq);\r
cc68a136 672\r
7a93adeb 673// sound/sound.c\r
c9e1affc 674PICO_INTERNAL void cdda_start_play();\r
675extern short cdda_out_buffer[2*1152];\r
7a93adeb 676extern int PsndLen_exc_cnt;\r
677extern int PsndLen_exc_add;\r
48dc74f2 678extern int timer_a_next_oflow, timer_a_step; // in z80 cycles\r
679extern int timer_b_next_oflow, timer_b_step;\r
43e6eaad 680\r
681void ym2612_sync_timers(int z80_cycles, int mode_old, int mode_new);\r
d2721b08 682void ym2612_pack_state(void);\r
453d2a6e 683void ym2612_unpack_state(void);\r
4b9c5888 684\r
e53704e6 685#define TIMER_NO_OFLOW 0x70000000\r
45a1ef71 686// tA = 72 * (1024 - NA) / M\r
687#define TIMER_A_TICK_ZCYCLES 17203\r
688// tB = 1152 * (256 - NA) / M\r
689#define TIMER_B_TICK_ZCYCLES 262800 // 275251 broken, see Dai Makaimura\r
e53704e6 690\r
4b9c5888 691#define timers_cycle() \\r
e53704e6 692 if (timer_a_next_oflow > 0 && timer_a_next_oflow < TIMER_NO_OFLOW) \\r
43e6eaad 693 timer_a_next_oflow -= Pico.m.pal ? 70938*256 : 59659*256; \\r
e53704e6 694 if (timer_b_next_oflow > 0 && timer_b_next_oflow < TIMER_NO_OFLOW) \\r
43e6eaad 695 timer_b_next_oflow -= Pico.m.pal ? 70938*256 : 59659*256; \\r
696 ym2612_sync_timers(0, ym2612.OPN.ST.mode, ym2612.OPN.ST.mode);\r
4b9c5888 697\r
698#define timers_reset() \\r
e53704e6 699 timer_a_next_oflow = timer_b_next_oflow = TIMER_NO_OFLOW; \\r
48dc74f2 700 timer_a_step = TIMER_A_TICK_ZCYCLES * 1024; \\r
701 timer_b_step = TIMER_B_TICK_ZCYCLES * 256;\r
43e6eaad 702\r
7a93adeb 703\r
c8d1e9b6 704// videoport.c\r
53f948c9 705extern int line_base_cycles;\r
eff55556 706PICO_INTERNAL_ASM void PicoVideoWrite(unsigned int a,unsigned short d);\r
707PICO_INTERNAL_ASM unsigned int PicoVideoRead(unsigned int a);\r
9761a7d0 708PICO_INTERNAL_ASM unsigned int PicoVideoRead8(unsigned int a);\r
5de27868 709extern int (*PicoDmaHook)(unsigned int source, int len, unsigned short **srcp, unsigned short **limitp);\r
cc68a136 710\r
c8d1e9b6 711// misc.c\r
eff55556 712PICO_INTERNAL_ASM void memcpy16(unsigned short *dest, unsigned short *src, int count);\r
713PICO_INTERNAL_ASM void memcpy16bswap(unsigned short *dest, void *src, int count);\r
714PICO_INTERNAL_ASM void memcpy32(int *dest, int *src, int count); // 32bit word count\r
715PICO_INTERNAL_ASM void memset32(int *dest, int c, int count);\r
cc68a136 716\r
45f2f245 717// eeprom.c\r
718void EEPROM_write8(unsigned int a, unsigned int d);\r
719void EEPROM_write16(unsigned int d);\r
720unsigned int EEPROM_read(void);\r
721\r
c8d1e9b6 722// z80 functionality wrappers\r
723PICO_INTERNAL void z80_init(void);\r
b4db550e 724PICO_INTERNAL void z80_pack(void *data);\r
725PICO_INTERNAL int z80_unpack(const void *data);\r
c8d1e9b6 726PICO_INTERNAL void z80_reset(void);\r
727PICO_INTERNAL void z80_exit(void);\r
c8d1e9b6 728\r
729// cd/misc.c\r
eff55556 730PICO_INTERNAL_ASM void wram_2M_to_1M(unsigned char *m);\r
731PICO_INTERNAL_ASM void wram_1M_to_2M(unsigned char *m);\r
732\r
733// cd/buffering.c\r
734PICO_INTERNAL void PicoCDBufferRead(void *dest, int lba);\r
735\r
736// sound/sound.c\r
9d917eea 737PICO_INTERNAL void PsndReset(void);\r
4b9c5888 738PICO_INTERNAL void PsndDoDAC(int line_to);\r
9d917eea 739PICO_INTERNAL void PsndClear(void);\r
7b3f44c6 740PICO_INTERNAL void PsndGetSamples(int y);\r
2ec9bec5 741PICO_INTERNAL void PsndGetSamplesMS(void);\r
4b9c5888 742extern int PsndDacLine;\r
cc68a136 743\r
3e49ffd0 744// sms.c\r
f3a57b2d 745#ifndef NO_SMS\r
3e49ffd0 746void PicoPowerMS(void);\r
2ec9bec5 747void PicoResetMS(void);\r
3e49ffd0 748void PicoMemSetupMS(void);\r
b4db550e 749void PicoStateLoadedMS(void);\r
3e49ffd0 750void PicoFrameMS(void);\r
87b0845f 751void PicoFrameDrawOnlyMS(void);\r
f3a57b2d 752#else\r
753#define PicoPowerMS()\r
754#define PicoResetMS()\r
755#define PicoMemSetupMS()\r
756#define PicoStateLoadedMS()\r
757#define PicoFrameMS()\r
758#define PicoFrameDrawOnlyMS()\r
759#endif\r
3e49ffd0 760\r
be2c4208 761// 32x/32x.c\r
f3a57b2d 762#ifndef NO_32X\r
be2c4208 763extern struct Pico32x Pico32x;\r
6a98f03e 764enum p32x_event {\r
765 P32X_EVENT_PWM,\r
766 P32X_EVENT_FILLEND,\r
5ac99d9a 767 P32X_EVENT_HINT,\r
6a98f03e 768 P32X_EVENT_COUNT,\r
769};\r
ae214f1c 770extern unsigned int p32x_event_times[P32X_EVENT_COUNT];\r
6a98f03e 771\r
be2c4208 772void Pico32xInit(void);\r
974fdb5b 773void PicoPower32x(void);\r
be2c4208 774void PicoReset32x(void);\r
974fdb5b 775void Pico32xStartup(void);\r
5e49c3a8 776void PicoUnload32x(void);\r
974fdb5b 777void PicoFrame32x(void);\r
27e26273 778void Pico32xStateLoaded(int is_early);\r
ed4402a7 779void p32x_sync_sh2s(unsigned int m68k_target);\r
19886062 780void p32x_sync_other_sh2(SH2 *sh2, unsigned int m68k_target);\r
4d5dfee8 781void p32x_update_irls(SH2 *active_sh2, int m68k_cycles);\r
9e1fa0a6 782void p32x_trigger_irq(SH2 *sh2, int m68k_cycles, unsigned int mask);\r
783void p32x_update_cmd_irq(SH2 *sh2, int m68k_cycles);\r
83ff19ec 784void p32x_reset_sh2s(void);\r
19886062 785void p32x_event_schedule(unsigned int now, enum p32x_event event, int after);\r
786void p32x_event_schedule_sh2(SH2 *sh2, enum p32x_event event, int after);\r
5ac99d9a 787void p32x_schedule_hint(SH2 *sh2, int m68k_cycles);\r
a8fd6e37 788\r
be2c4208 789// 32x/memory.c\r
974fdb5b 790struct Pico32xMem *Pico32xMem;\r
be2c4208 791unsigned int PicoRead8_32x(unsigned int a);\r
792unsigned int PicoRead16_32x(unsigned int a);\r
793void PicoWrite8_32x(unsigned int a, unsigned int d);\r
794void PicoWrite16_32x(unsigned int a, unsigned int d);\r
795void PicoMemSetup32x(void);\r
974fdb5b 796void Pico32xSwapDRAM(int b);\r
27e26273 797void Pico32xMemStateLoaded(void);\r
19886062 798void p32x_m68k_poll_event(unsigned int flags);\r
799void p32x_sh2_poll_event(SH2 *sh2, unsigned int flags, unsigned int m68k_cycles);\r
974fdb5b 800\r
801// 32x/draw.c\r
41946d70 802void PicoDrawSetOutFormat32x(pdso_t which, int use_32x_line_mode);\r
974fdb5b 803void FinalizeLine32xRGB555(int sh, int line);\r
5a681086 804void PicoDraw32xLayer(int offs, int lines, int mdbg);\r
7a961c19 805void PicoDraw32xLayerMdOnly(int offs, int lines);\r
f4750ee0 806extern int (*PicoScan32xBegin)(unsigned int num);\r
807extern int (*PicoScan32xEnd)(unsigned int num);\r
7a961c19 808enum {\r
809 PDM32X_OFF,\r
810 PDM32X_32X_ONLY,\r
811 PDM32X_BOTH,\r
812};\r
5a681086 813extern int Pico32xDrawMode;\r
be2c4208 814\r
db1d3564 815// 32x/pwm.c\r
c1931173 816unsigned int p32x_pwm_read16(unsigned int a, SH2 *sh2,\r
817 unsigned int m68k_cycles);\r
818void p32x_pwm_write16(unsigned int a, unsigned int d,\r
819 SH2 *sh2, unsigned int m68k_cycles);\r
db1d3564 820void p32x_pwm_update(int *buf32, int length, int stereo);\r
045a4c52 821void p32x_pwm_ctl_changed(void);\r
df63f1a6 822void p32x_pwm_schedule(unsigned int m68k_now);\r
19886062 823void p32x_pwm_schedule_sh2(SH2 *sh2);\r
9e1fa0a6 824void p32x_pwm_sync_to_sh2(SH2 *sh2);\r
df63f1a6 825void p32x_pwm_irq_event(unsigned int m68k_now);\r
826void p32x_pwm_state_loaded(void);\r
045a4c52 827\r
828// 32x/sh2soc.c\r
829void p32x_dreq0_trigger(void);\r
830void p32x_dreq1_trigger(void);\r
831void p32x_timers_recalc(void);\r
832void p32x_timers_do(unsigned int m68k_slice);\r
cd0ace28 833void sh2_peripheral_reset(SH2 *sh2);\r
f81107f5 834unsigned int sh2_peripheral_read8(unsigned int a, SH2 *sh2);\r
835unsigned int sh2_peripheral_read16(unsigned int a, SH2 *sh2);\r
836unsigned int sh2_peripheral_read32(unsigned int a, SH2 *sh2);\r
8b43bc73 837void REGPARM(3) sh2_peripheral_write8(unsigned int a, unsigned int d, SH2 *sh2);\r
838void REGPARM(3) sh2_peripheral_write16(unsigned int a, unsigned int d, SH2 *sh2);\r
839void REGPARM(3) sh2_peripheral_write32(unsigned int a, unsigned int d, SH2 *sh2);\r
045a4c52 840\r
f3a57b2d 841#else\r
842#define Pico32xInit()\r
843#define PicoPower32x()\r
844#define PicoReset32x()\r
845#define PicoFrame32x()\r
846#define PicoUnload32x()\r
847#define Pico32xStateLoaded()\r
f3a57b2d 848#define FinalizeLine32xRGB555 NULL\r
849#define p32x_pwm_update(...)\r
850#define p32x_timers_recalc()\r
851#endif\r
db1d3564 852\r
45f2f245 853/* avoid dependency on newer glibc */\r
854static __inline int isspace_(int c)\r
855{\r
856 return (0x09 <= c && c <= 0x0d) || c == ' ';\r
857}\r
858\r
f4bb5d6b 859#ifndef ARRAY_SIZE\r
860#define ARRAY_SIZE(x) (sizeof(x) / sizeof(x[0]))\r
861#endif\r
862\r
b8cbd802 863// emulation event logging\r
864#ifndef EL_LOGMASK\r
9c9cda8c 865# ifdef __x86_64__ // HACK\r
866# define EL_LOGMASK (EL_STATUS|EL_IDLE|EL_ANOMALY)\r
867# else\r
1555935b 868# define EL_LOGMASK (EL_STATUS)\r
9c9cda8c 869# endif\r
b8cbd802 870#endif\r
871\r
017512f2 872#define EL_HVCNT 0x00000001 /* hv counter reads */\r
873#define EL_SR 0x00000002 /* SR reads */\r
874#define EL_INTS 0x00000004 /* ints and acks */\r
43e6eaad 875#define EL_YMTIMER 0x00000008 /* ym2612 timer stuff */\r
017512f2 876#define EL_INTSW 0x00000010 /* log irq switching on/off */\r
877#define EL_ASVDP 0x00000020 /* VDP accesses during active scan */\r
878#define EL_VDPDMA 0x00000040 /* VDP DMA transfers and their timing */\r
879#define EL_BUSREQ 0x00000080 /* z80 busreq r/w or reset w */\r
880#define EL_Z80BNK 0x00000100 /* z80 i/o through bank area */\r
881#define EL_SRAMIO 0x00000200 /* sram i/o */\r
882#define EL_EEPROM 0x00000400 /* eeprom debug */\r
883#define EL_UIO 0x00000800 /* unmapped i/o */\r
884#define EL_IO 0x00001000 /* all i/o */\r
885#define EL_CDPOLL 0x00002000 /* MCD: log poll detection */\r
886#define EL_SVP 0x00004000 /* SVP stuff */\r
fa22af4c 887#define EL_PICOHW 0x00008000 /* Pico stuff */\r
053fd9b4 888#define EL_IDLE 0x00010000 /* idle loop det. */\r
af37bca8 889#define EL_CDREGS 0x00020000 /* MCD: register access */\r
890#define EL_CDREG3 0x00040000 /* MCD: register 3 only */\r
be2c4208 891#define EL_32X 0x00080000\r
1b3f5844 892#define EL_PWM 0x00100000 /* 32X PWM stuff (LOTS of output) */\r
045a4c52 893#define EL_32XP 0x00200000 /* 32X peripherals */\r
ae214f1c 894#define EL_CD 0x00400000 /* MCD */\r
017512f2 895\r
896#define EL_STATUS 0x40000000 /* status messages */\r
897#define EL_ANOMALY 0x80000000 /* some unexpected conditions (during emulation) */\r
b8cbd802 898\r
899#if EL_LOGMASK\r
900#define elprintf(w,f,...) \\r
a8fd6e37 901do { \\r
b8cbd802 902 if ((w) & EL_LOGMASK) \\r
7d0143a2 903 lprintf("%05i:%03i: " f "\n",Pico.m.frame_count,Pico.m.scanline,##__VA_ARGS__); \\r
a8fd6e37 904} while (0)\r
dca310c4 905#elif defined(_MSC_VER)\r
906#define elprintf\r
b8cbd802 907#else\r
908#define elprintf(w,f,...)\r
909#endif\r
910\r
f6c49d38 911// profiling\r
912#ifdef PPROF\r
913#include <platform/linux/pprof.h>\r
914#else\r
915#define pprof_init()\r
916#define pprof_finish()\r
917#define pprof_start(x)\r
918#define pprof_end(...)\r
919#define pprof_end_sub(...)\r
920#endif\r
921\r
19886062 922#ifdef EVT_LOG\r
923enum evt {\r
924 EVT_FRAME_START,\r
925 EVT_NEXT_LINE,\r
926 EVT_RUN_START,\r
927 EVT_RUN_END,\r
928 EVT_POLL_START,\r
929 EVT_POLL_END,\r
930 EVT_CNT\r
931};\r
932\r
933enum evt_cpu {\r
934 EVT_M68K,\r
935 EVT_S68K,\r
936 EVT_MSH2,\r
937 EVT_SSH2,\r
938 EVT_CPU_CNT\r
939};\r
940\r
941void pevt_log(unsigned int cycles, enum evt_cpu c, enum evt e);\r
942void pevt_dump(void);\r
943\r
944#define pevt_log_m68k(e) \\r
08769494 945 pevt_log(SekCyclesDone(), EVT_M68K, e)\r
19886062 946#define pevt_log_m68k_o(e) \\r
08769494 947 pevt_log(SekCyclesDone(), EVT_M68K, e)\r
19886062 948#define pevt_log_sh2(sh2, e) \\r
949 pevt_log(sh2_cycles_done_m68k(sh2), EVT_MSH2 + (sh2)->is_slave, e)\r
950#define pevt_log_sh2_o(sh2, e) \\r
951 pevt_log((sh2)->m68krcycles_done, EVT_MSH2 + (sh2)->is_slave, e)\r
952#else\r
953#define pevt_log(c, e)\r
954#define pevt_log_m68k(e)\r
955#define pevt_log_m68k_o(e)\r
956#define pevt_log_sh2(sh2, e)\r
957#define pevt_log_sh2_o(sh2, e)\r
958#define pevt_dump()\r
959#endif\r
960\r
f6c49d38 961// misc\r
dca310c4 962#ifdef _MSC_VER\r
963#define cdprintf\r
964#else\r
965#define cdprintf(x...)\r
966#endif\r
967\r
8b43bc73 968#if defined(__GNUC__) && defined(__i386__)\r
553c3eaa 969#define REGPARM(x) __attribute__((regparm(x)))\r
c8d1e9b6 970#else\r
553c3eaa 971#define REGPARM(x)\r
c8d1e9b6 972#endif\r
973\r
5e89f0f5 974#ifdef __GNUC__\r
975#define NOINLINE __attribute__((noinline))\r
976#else\r
977#define NOINLINE\r
978#endif\r
979\r
f8af9634 980#ifdef __cplusplus\r
981} // End of extern "C"\r
982#endif\r
983\r
eff55556 984#endif // PICO_INTERNAL_INCLUDED\r
985\r
fast MegaDrive/MegaCD/32X emulator