notaz.gp2x.de / picodrive.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
cd: pull in Genesis-Plus-GX CD gfx code
[picodrive.git] / pico / pico_int.h
CommitLineData
cff531af 1/*\r
2 * PicoDrive - Internal Header File\r
3 * (c) Copyright Dave, 2004\r
4 * (C) notaz, 2006-2010\r
5 *\r
6 * This work is licensed under the terms of MAME license.\r
7 * See COPYING file in the top-level directory.\r
8 */\r
cc68a136 9\r
eff55556 10#ifndef PICO_INTERNAL_INCLUDED\r
11#define PICO_INTERNAL_INCLUDED\r
cc68a136 12\r
13#include <stdio.h>\r
14#include <stdlib.h>\r
15#include <string.h>\r
efcba75f 16#include "pico.h"\r
f53f286a 17#include "carthw/carthw.h"\r
cc68a136 18\r
89fa852d 19//\r
20#define USE_POLL_DETECT\r
21\r
eff55556 22#ifndef PICO_INTERNAL\r
23#define PICO_INTERNAL\r
24#endif\r
25#ifndef PICO_INTERNAL_ASM\r
26#define PICO_INTERNAL_ASM\r
27#endif\r
cc68a136 28\r
70357ce5 29// to select core, define EMU_C68K, EMU_M68K or EMU_F68K in your makefile or project\r
cc68a136 30\r
31#ifdef __cplusplus\r
32extern "C" {\r
33#endif\r
34\r
35\r
36// ----------------------- 68000 CPU -----------------------\r
37#ifdef EMU_C68K\r
d4d62665 38#include "../cpu/cyclone/Cyclone.h"\r
3aa1e148 39extern struct Cyclone PicoCpuCM68k, PicoCpuCS68k;\r
ae214f1c 40#define SekCyclesLeft PicoCpuCM68k.cycles // cycles left for this run\r
41#define SekCyclesLeftS68k PicoCpuCS68k.cycles\r
3aa1e148 42#define SekPc (PicoCpuCM68k.pc-PicoCpuCM68k.membase)\r
43#define SekPcS68k (PicoCpuCS68k.pc-PicoCpuCS68k.membase)\r
12da51c2 44#define SekDar(x) (x < 8 ? PicoCpuCM68k.d[x] : PicoCpuCM68k.a[x - 8])\r
45#define SekDarS68k(x) (x < 8 ? PicoCpuCS68k.d[x] : PicoCpuCS68k.a[x - 8])\r
5fadfb1c 46#define SekSr CycloneGetSr(&PicoCpuCM68k)\r
12da51c2 47#define SekSrS68k CycloneGetSr(&PicoCpuCS68k)\r
3aa1e148 48#define SekSetStop(x) { PicoCpuCM68k.state_flags&=~1; if (x) { PicoCpuCM68k.state_flags|=1; PicoCpuCM68k.cycles=0; } }\r
49#define SekSetStopS68k(x) { PicoCpuCS68k.state_flags&=~1; if (x) { PicoCpuCS68k.state_flags|=1; PicoCpuCS68k.cycles=0; } }\r
ed4402a7 50#define SekIsStoppedM68k() (PicoCpuCM68k.state_flags&1)\r
ca61ee42 51#define SekIsStoppedS68k() (PicoCpuCS68k.state_flags&1)\r
08769494 52#define SekShouldInterrupt() (PicoCpuCM68k.irq > (PicoCpuCM68k.srh&7))\r
b542be46 53\r
ecc8036e 54#define SekNotPolling PicoCpuCM68k.not_pol\r
55#define SekNotPollingS68k PicoCpuCS68k.not_pol\r
56\r
b542be46 57#define SekInterrupt(i) PicoCpuCM68k.irq=i\r
5fadfb1c 58#define SekIrqLevel PicoCpuCM68k.irq\r
b542be46 59\r
cc68a136 60#endif\r
61\r
70357ce5 62#ifdef EMU_F68K\r
63#include "../cpu/fame/fame.h"\r
b542be46 64extern M68K_CONTEXT PicoCpuFM68k, PicoCpuFS68k;\r
ae214f1c 65#define SekCyclesLeft PicoCpuFM68k.io_cycle_counter\r
66#define SekCyclesLeftS68k PicoCpuFS68k.io_cycle_counter\r
03e4f2a3 67#define SekPc fm68k_get_pc(&PicoCpuFM68k)\r
68#define SekPcS68k fm68k_get_pc(&PicoCpuFS68k)\r
12da51c2 69#define SekDar(x) (x < 8 ? PicoCpuFM68k.dreg[x].D : PicoCpuFM68k.areg[x - 8].D)\r
70#define SekDarS68k(x) (x < 8 ? PicoCpuFS68k.dreg[x].D : PicoCpuFS68k.areg[x - 8].D)\r
5fadfb1c 71#define SekSr PicoCpuFM68k.sr\r
12da51c2 72#define SekSrS68k PicoCpuFS68k.sr\r
70357ce5 73#define SekSetStop(x) { \\r
03e4f2a3 74 PicoCpuFM68k.execinfo &= ~FM68K_HALTED; \\r
75 if (x) { PicoCpuFM68k.execinfo |= FM68K_HALTED; PicoCpuFM68k.io_cycle_counter = 0; } \\r
70357ce5 76}\r
77#define SekSetStopS68k(x) { \\r
03e4f2a3 78 PicoCpuFS68k.execinfo &= ~FM68K_HALTED; \\r
79 if (x) { PicoCpuFS68k.execinfo |= FM68K_HALTED; PicoCpuFS68k.io_cycle_counter = 0; } \\r
70357ce5 80}\r
ed4402a7 81#define SekIsStoppedM68k() (PicoCpuFM68k.execinfo&FM68K_HALTED)\r
ca61ee42 82#define SekIsStoppedS68k() (PicoCpuFS68k.execinfo&FM68K_HALTED)\r
08769494 83#define SekShouldInterrupt() fm68k_would_interrupt()\r
b542be46 84\r
ecc8036e 85#define SekNotPolling PicoCpuFM68k.not_polling\r
86#define SekNotPollingS68k PicoCpuFS68k.not_polling\r
87\r
b542be46 88#define SekInterrupt(irq) PicoCpuFM68k.interrupts[0]=irq\r
5fadfb1c 89#define SekIrqLevel PicoCpuFM68k.interrupts[0]\r
b542be46 90\r
cc68a136 91#endif\r
92\r
93#ifdef EMU_M68K\r
94#include "../cpu/musashi/m68kcpu.h"\r
3aa1e148 95extern m68ki_cpu_core PicoCpuMM68k, PicoCpuMS68k;\r
cc68a136 96#ifndef SekCyclesLeft\r
ae214f1c 97#define SekCyclesLeft PicoCpuMM68k.cyc_remaining_cycles\r
98#define SekCyclesLeftS68k PicoCpuMS68k.cyc_remaining_cycles\r
3aa1e148 99#define SekPc m68k_get_reg(&PicoCpuMM68k, M68K_REG_PC)\r
100#define SekPcS68k m68k_get_reg(&PicoCpuMS68k, M68K_REG_PC)\r
12da51c2 101#define SekDar(x) PicoCpuMM68k.dar[x]\r
102#define SekDarS68k(x) PicoCpuMS68k.dar[x]\r
103#define SekSr m68k_get_reg(&PicoCpuMM68k, M68K_REG_SR)\r
104#define SekSrS68k m68k_get_reg(&PicoCpuMS68k, M68K_REG_SR)\r
7a1f6e45 105#define SekSetStop(x) { \\r
3aa1e148 106 if(x) { SET_CYCLES(0); PicoCpuMM68k.stopped=STOP_LEVEL_STOP; } \\r
107 else PicoCpuMM68k.stopped=0; \\r
7a1f6e45 108}\r
109#define SekSetStopS68k(x) { \\r
3aa1e148 110 if(x) { SET_CYCLES(0); PicoCpuMS68k.stopped=STOP_LEVEL_STOP; } \\r
111 else PicoCpuMS68k.stopped=0; \\r
7a1f6e45 112}\r
ed4402a7 113#define SekIsStoppedM68k() (PicoCpuMM68k.stopped==STOP_LEVEL_STOP)\r
ca61ee42 114#define SekIsStoppedS68k() (PicoCpuMS68k.stopped==STOP_LEVEL_STOP)\r
08769494 115#define SekShouldInterrupt() (CPU_INT_LEVEL > FLAG_INT_MASK)\r
b542be46 116\r
ecc8036e 117#define SekNotPolling PicoCpuMM68k.not_polling\r
118#define SekNotPollingS68k PicoCpuMS68k.not_polling\r
119\r
71de3cd9 120#define SekInterrupt(irq) { \\r
b542be46 121 void *oldcontext = m68ki_cpu_p; \\r
122 m68k_set_context(&PicoCpuMM68k); \\r
123 m68k_set_irq(irq); \\r
124 m68k_set_context(oldcontext); \\r
125}\r
5fadfb1c 126#define SekIrqLevel (PicoCpuMM68k.int_level >> 8)\r
b542be46 127\r
cc68a136 128#endif\r
ef090115 129#endif // EMU_M68K\r
cc68a136 130\r
ae214f1c 131// while running, cnt represents target of current timeslice\r
132// while not in SekRun(), it's actual cycles done\r
133// (but always use SekCyclesDone() if you need current position)\r
134// cnt may change if timeslice is ended prematurely or extended,\r
135// so we use SekCycleAim for the actual target\r
136extern unsigned int SekCycleCnt;\r
137extern unsigned int SekCycleAim;\r
cc68a136 138\r
ae214f1c 139// number of cycles done (can be checked anywhere)\r
140#define SekCyclesDone() (SekCycleCnt - SekCyclesLeft)\r
141\r
142// burn cycles while not in SekRun() and while in\r
143#define SekCyclesBurn(c) SekCycleCnt += c\r
bc3c13d3 144#define SekCyclesBurnRun(c) { \\r
145 SekCyclesLeft -= c; \\r
b8cbd802 146}\r
cc68a136 147\r
ae214f1c 148// note: sometimes may extend timeslice to delay an irq\r
cc68a136 149#define SekEndRun(after) { \\r
ae214f1c 150 SekCycleCnt -= SekCyclesLeft - (after); \\r
151 SekCyclesLeft = after; \\r
cc68a136 152}\r
153\r
ae214f1c 154extern unsigned int SekCycleCntS68k;\r
155extern unsigned int SekCycleAimS68k;\r
156\r
07ceafdb 157#define SekEndRunS68k(after) { \\r
ae214f1c 158 if (SekCyclesLeftS68k > (after)) { \\r
159 SekCycleCntS68k -= SekCyclesLeftS68k - (after); \\r
160 SekCyclesLeftS68k = after; \\r
161 } \\r
07ceafdb 162}\r
163\r
ae214f1c 164#define SekCyclesDoneS68k() (SekCycleCntS68k - SekCyclesLeftS68k)\r
cc68a136 165\r
ae214f1c 166// compare cycles, handling overflows\r
167// check if a > b\r
168#define CYCLES_GT(a, b) \\r
169 ((int)((a) - (b)) > 0)\r
170// check if a >= b\r
171#define CYCLES_GE(a, b) \\r
172 ((int)((a) - (b)) >= 0)\r
cc68a136 173\r
b542be46 174// ----------------------- Z80 CPU -----------------------\r
175\r
b4db550e 176#if defined(_USE_DRZ80)\r
dca310c4 177#include "../cpu/DrZ80/drz80.h"\r
b542be46 178\r
179extern struct DrZ80 drZ80;\r
180\r
181#define z80_run(cycles) ((cycles) - DrZ80Run(&drZ80, cycles))\r
182#define z80_run_nr(cycles) DrZ80Run(&drZ80, cycles)\r
4936aac1 183#define z80_int() drZ80.Z80_IRQ = 1\r
835122bc 184#define z80_int() drZ80.Z80_IRQ = 1\r
185#define z80_nmi() drZ80.Z80IF |= 8\r
4b9c5888 186\r
187#define z80_cyclesLeft drZ80.cycles\r
19954be1 188#define z80_pc() (drZ80.Z80PC - drZ80.Z80PC_BASE)\r
b542be46 189\r
190#elif defined(_USE_CZ80)\r
dca310c4 191#include "../cpu/cz80/cz80.h"\r
b542be46 192\r
193#define z80_run(cycles) Cz80_Exec(&CZ80, cycles)\r
194#define z80_run_nr(cycles) Cz80_Exec(&CZ80, cycles)\r
195#define z80_int() Cz80_Set_IRQ(&CZ80, 0, HOLD_LINE)\r
835122bc 196#define z80_nmi() Cz80_Set_IRQ(&CZ80, IRQ_LINE_NMI, 0)\r
4b9c5888 197\r
198#define z80_cyclesLeft (CZ80.ICount - CZ80.ExtraCycles)\r
19954be1 199#define z80_pc() Cz80_Get_Reg(&CZ80, CZ80_PC)\r
b542be46 200\r
201#else\r
202\r
203#define z80_run(cycles) (cycles)\r
204#define z80_run_nr(cycles)\r
205#define z80_int()\r
835122bc 206#define z80_nmi()\r
b542be46 207\r
208#endif\r
209\r
b4db550e 210#define Z80_STATE_SIZE 0x60\r
211\r
ae214f1c 212extern unsigned int last_z80_sync;\r
4b9c5888 213extern int z80_cycle_cnt; /* 'done' z80 cycles before z80_run() */\r
214extern int z80_cycle_aim;\r
215extern int z80_scanline;\r
216extern int z80_scanline_cycles; /* cycles done until z80_scanline */\r
217\r
218#define z80_resetCycles() \\r
ae214f1c 219 last_z80_sync = SekCyclesDone(); \\r
4b9c5888 220 z80_cycle_cnt = z80_cycle_aim = z80_scanline = z80_scanline_cycles = 0;\r
221\r
222#define z80_cyclesDone() \\r
223 (z80_cycle_aim - z80_cyclesLeft)\r
224\r
225#define cycles_68k_to_z80(x) ((x)*957 >> 11)\r
226\r
acd35d4c 227// ----------------------- SH2 CPU -----------------------\r
228\r
41397701 229#include "cpu/sh2/sh2.h"\r
acd35d4c 230\r
1d7a28a7 231extern SH2 sh2s[2];\r
232#define msh2 sh2s[0]\r
233#define ssh2 sh2s[1]\r
234\r
679af8a3 235#ifndef DRC_SH2\r
19886062 236# define sh2_end_run(sh2, after_) do { \\r
237 if ((sh2)->icount > (after_)) { \\r
c1931173 238 (sh2)->cycles_timeslice -= (sh2)->icount - (after_); \\r
19886062 239 (sh2)->icount = after_; \\r
a8fd6e37 240 } \\r
241} while (0)\r
19886062 242# define sh2_cycles_left(sh2) (sh2)->icount\r
8a847c12 243# define sh2_burn_cycles(sh2, n) (sh2)->icount -= n\r
f81107f5 244# define sh2_pc(sh2) (sh2)->ppc\r
679af8a3 245#else\r
19886062 246# define sh2_end_run(sh2, after_) do { \\r
247 int left_ = (signed int)(sh2)->sr >> 12; \\r
248 if (left_ > (after_)) { \\r
c1931173 249 (sh2)->cycles_timeslice -= left_ - (after_); \\r
f4c0720c 250 (sh2)->sr &= 0xfff; \\r
19886062 251 (sh2)->sr |= (after_) << 12; \\r
a8fd6e37 252 } \\r
253} while (0)\r
19886062 254# define sh2_cycles_left(sh2) ((signed int)(sh2)->sr >> 12)\r
8a847c12 255# define sh2_burn_cycles(sh2, n) (sh2)->sr -= ((n) << 12)\r
f81107f5 256# define sh2_pc(sh2) (sh2)->pc\r
679af8a3 257#endif\r
266c6afa 258\r
19886062 259#define sh2_cycles_done(sh2) ((int)(sh2)->cycles_timeslice - sh2_cycles_left(sh2))\r
a7f82a77 260#define sh2_cycles_done_t(sh2) \\r
261 ((sh2)->m68krcycles_done * 3 + sh2_cycles_done(sh2))\r
19886062 262#define sh2_cycles_done_m68k(sh2) \\r
263 ((sh2)->m68krcycles_done + (sh2_cycles_done(sh2) / 3))\r
264\r
4ea707e1 265#define sh2_reg(c, x) (c) ? ssh2.r[x] : msh2.r[x]\r
266#define sh2_gbr(c) (c) ? ssh2.gbr : msh2.gbr\r
267#define sh2_vbr(c) (c) ? ssh2.vbr : msh2.vbr\r
6add7875 268#define sh2_sr(c) (((c) ? ssh2.sr : msh2.sr) & 0xfff)\r
acd35d4c 269\r
83ff19ec 270#define sh2_set_gbr(c, v) \\r
271 { if (c) ssh2.gbr = v; else msh2.gbr = v; }\r
272#define sh2_set_vbr(c, v) \\r
273 { if (c) ssh2.vbr = v; else msh2.vbr = v; }\r
274\r
f8675e28 275#define elprintf_sh2(sh2, w, f, ...) \\r
276 elprintf(w,"%csh2 "f,(sh2)->is_slave?'s':'m',##__VA_ARGS__)\r
277\r
cc68a136 278// ---------------------------------------------------------\r
279\r
280// main oscillator clock which controls timing\r
281#define OSC_NTSC 53693100\r
b8cbd802 282#define OSC_PAL 53203424\r
cc68a136 283\r
284struct PicoVideo\r
285{\r
286 unsigned char reg[0x20];\r
b8cbd802 287 unsigned int command; // 32-bit Command\r
288 unsigned char pending; // 1 if waiting for second half of 32-bit command\r
289 unsigned char type; // Command type (v/c/vsram read/write)\r
290 unsigned short addr; // Read/Write address\r
291 int status; // Status bits\r
cc68a136 292 unsigned char pending_ints; // pending interrupts: ??VH????\r
b8cbd802 293 signed char lwrite_cnt; // VDP write count during active display line\r
9761a7d0 294 unsigned short v_counter; // V-counter\r
295 unsigned char pad[0x10];\r
cc68a136 296};\r
297\r
298struct PicoMisc\r
299{\r
300 unsigned char rotate;\r
301 unsigned char z80Run;\r
e5503e2f 302 unsigned char padTHPhase[2]; // 02 phase of gamepad TH switches\r
2aa27095 303 unsigned short scanline; // 04 0 to 261||311\r
e5503e2f 304 char dirtyPal; // 06 Is the palette dirty (1 - change @ this frame, 2 - some time before)\r
305 unsigned char hardware; // 07 Hardware value for country\r
306 unsigned char pal; // 08 1=PAL 0=NTSC\r
45f2f245 307 unsigned char sram_reg; // 09 SRAM reg. See SRR_* below\r
e5503e2f 308 unsigned short z80_bank68k; // 0a\r
be2c4208 309 unsigned short pad0;\r
fa8fb754 310 unsigned char ncart_in; // 0e !cart_in\r
0ace9b9a 311 unsigned char z80_reset; // 0f z80 reset held\r
e5503e2f 312 unsigned char padDelay[2]; // 10 gamepad phase time outs, so we count a delay\r
1dceadae 313 unsigned short eeprom_addr; // EEPROM address register\r
45f2f245 314 unsigned char eeprom_cycle; // EEPROM cycle number\r
1dceadae 315 unsigned char eeprom_slave; // EEPROM slave word for X24C02 and better SRAMs\r
45f2f245 316 unsigned char eeprom_status;\r
be2c4208 317 unsigned char pad2;\r
053fd9b4 318 unsigned short dma_xfers; // 18\r
45f2f245 319 unsigned char eeprom_wb[2]; // EEPROM latch/write buffer\r
053fd9b4 320 unsigned int frame_count; // 1c for movies and idle det\r
cc68a136 321};\r
322\r
b4db550e 323struct PicoMS\r
324{\r
325 unsigned char carthw[0x10];\r
326 unsigned char io_ctl;\r
835122bc 327 unsigned char nmi_state;\r
328 unsigned char pad[0x4e];\r
b4db550e 329};\r
330\r
cc68a136 331// some assembly stuff depend on these, do not touch!\r
332struct Pico\r
333{\r
334 unsigned char ram[0x10000]; // 0x00000 scratch ram\r
200772b7 335 union { // vram is byteswapped for easier reads when drawing\r
2ec9bec5 336 unsigned short vram[0x8000]; // 0x10000\r
337 unsigned char vramb[0x4000]; // VRAM in SMS mode\r
338 };\r
cc68a136 339 unsigned char zram[0x2000]; // 0x20000 Z80 ram\r
b4db550e 340 unsigned char ioports[0x10]; // XXX: fix asm and mv\r
341 unsigned char pad[0xf0]; // unused\r
cc68a136 342 unsigned short cram[0x40]; // 0x22100\r
343 unsigned short vsram[0x40]; // 0x22180\r
344\r
345 unsigned char *rom; // 0x22200\r
0219d379 346 unsigned int romsize; // 0x22204 (on 32bits)\r
cc68a136 347\r
348 struct PicoMisc m;\r
349 struct PicoVideo video;\r
b4db550e 350 struct PicoMS ms;\r
cc68a136 351};\r
352\r
353// sram\r
45f2f245 354#define SRR_MAPPED (1 << 0)\r
355#define SRR_READONLY (1 << 1)\r
356\r
357#define SRF_ENABLED (1 << 0)\r
358#define SRF_EEPROM (1 << 1)\r
af37bca8 359\r
cc68a136 360struct PicoSRAM\r
361{\r
4ff2d527 362 unsigned char *data; // actual data\r
363 unsigned int start; // start address in 68k address space\r
cc68a136 364 unsigned int end;\r
45f2f245 365 unsigned char flags; // 0c: SRF_*\r
1dceadae 366 unsigned char unused2;\r
cc68a136 367 unsigned char changed;\r
45f2f245 368 unsigned char eeprom_type; // eeprom type: 0: 7bit (24C01), 2: 2 addr words (X24C02+), 3: 3 addr words\r
369 unsigned char unused3;\r
1dceadae 370 unsigned char eeprom_bit_cl; // bit number for cl\r
371 unsigned char eeprom_bit_in; // bit number for in\r
372 unsigned char eeprom_bit_out; // bit number for out\r
45f2f245 373 unsigned int size;\r
cc68a136 374};\r
375\r
376// MCD\r
377#include "cd/cd_sys.h"\r
378#include "cd/LC89510.h"\r
d1df8786 379#include "cd/gfx_cd.h"\r
cc68a136 380\r
33be04ca 381#define PCM_MIXBUF_LEN ((12500000 / 384) / 50 + 1)\r
382\r
4f265db7 383struct mcd_pcm\r
384{\r
385 unsigned char control; // reg7\r
386 unsigned char enabled; // reg8\r
387 unsigned char cur_ch;\r
388 unsigned char bank;\r
33be04ca 389 unsigned int update_cycles;\r
4f265db7 390\r
4ff2d527 391 struct pcm_chan // 08, size 0x10\r
4f265db7 392 {\r
393 unsigned char regs[8];\r
4ff2d527 394 unsigned int addr; // .08: played sample address\r
4f265db7 395 int pad;\r
396 } ch[8];\r
397};\r
398\r
4fb43555 399#define PCD_ST_S68K_RST 1\r
400\r
c459aefd 401struct mcd_misc\r
402{\r
403 unsigned short hint_vector;\r
4fb43555 404 unsigned char busreq; // not s68k_regs[1]\r
51a902ae 405 unsigned char s68k_pend_ints;\r
bc3c13d3 406 unsigned int state_flags; // 04\r
ae214f1c 407 unsigned int stopwatch_base_c;\r
bc3c13d3 408 unsigned short m68k_poll_a;\r
409 unsigned short m68k_poll_cnt;\r
08769494 410 unsigned short s68k_poll_a;\r
411 unsigned short s68k_poll_cnt;\r
412 unsigned int s68k_poll_clk;\r
6cadc2da 413 unsigned char bcram_reg; // 18: battery-backed RAM cart register\r
ba6e8bfd 414 unsigned char dmna_ret_2m;\r
6cadc2da 415 unsigned short pad3;\r
ae214f1c 416 int pad4[9];\r
c459aefd 417};\r
418\r
cc68a136 419typedef struct\r
420{\r
4ff2d527 421 unsigned char bios[0x20000]; // 000000: 128K\r
422 union { // 020000: 512K\r
fa1e5e29 423 unsigned char prg_ram[0x80000];\r
cc68a136 424 unsigned char prg_ram_b[4][0x20000];\r
425 };\r
4ff2d527 426 union { // 0a0000: 256K\r
fa1e5e29 427 struct {\r
428 unsigned char word_ram2M[0x40000];\r
dca310c4 429 unsigned char unused0[0x20000];\r
fa1e5e29 430 };\r
431 struct {\r
dca310c4 432 unsigned char unused1[0x20000];\r
fa1e5e29 433 unsigned char word_ram1M[2][0x20000];\r
434 };\r
435 };\r
4ff2d527 436 union { // 100000: 64K\r
fa1e5e29 437 unsigned char pcm_ram[0x10000];\r
4f265db7 438 unsigned char pcm_ram_b[0x10][0x1000];\r
439 };\r
895d1512 440 // FIXME: should be short\r
4ff2d527 441 unsigned char s68k_regs[0x200]; // 110000: GA, not CPU regs\r
442 unsigned char bram[0x2000]; // 110200: 8K\r
443 struct mcd_misc m; // 112200: misc\r
444 struct mcd_pcm pcm; // 112240:\r
75736070 445 _scd_toc TOC; // not to be saved\r
cc68a136 446 CDD cdd;\r
447 CDC cdc;\r
448 _scd scd;\r
d1df8786 449 Rot_Comp rot_comp;\r
33be04ca 450 int pcm_mixbuf[PCM_MIXBUF_LEN * 2];\r
451 int pcm_mixpos;\r
452 int pcm_mixbuf_dirty;\r
cc68a136 453} mcd_state;\r
454\r
be2c4208 455// XXX: this will need to be reworked for cart+cd support.\r
cc68a136 456#define Pico_mcd ((mcd_state *)Pico.rom)\r
457\r
be2c4208 458// 32X\r
acd35d4c 459#define P32XS_FM (1<<15)\r
fa8fb754 460#define P32XS_nCART (1<< 8)\r
83ff19ec 461#define P32XS_REN (1<< 7)\r
462#define P32XS_nRES (1<< 1)\r
463#define P32XS_ADEN (1<< 0)\r
acd35d4c 464#define P32XS2_ADEN (1<< 9)\r
5e128c6d 465#define P32XS_FULL (1<< 7) // DREQ FIFO full\r
4ea707e1 466#define P32XS_68S (1<< 2)\r
97d3f47f 467#define P32XS_DMA (1<< 1)\r
4ea707e1 468#define P32XS_RV (1<< 0)\r
acd35d4c 469\r
5e128c6d 470#define P32XV_nPAL (1<<15) // VDP\r
acd35d4c 471#define P32XV_PRI (1<< 7)\r
4ea707e1 472#define P32XV_Mx (3<< 0) // display mode mask\r
974fdb5b 473\r
e51e5983 474#define P32XV_SFT (1<< 0)\r
475\r
acd35d4c 476#define P32XV_VBLK (1<<15)\r
477#define P32XV_HBLK (1<<14)\r
478#define P32XV_PEN (1<<13)\r
479#define P32XV_nFEN (1<< 1)\r
480#define P32XV_FS (1<< 0)\r
974fdb5b 481\r
df63f1a6 482#define P32XP_RTP (1<<7) // PWM control\r
483#define P32XP_FULL (1<<15) // PWM pulse\r
db1d3564 484#define P32XP_EMPTY (1<<14)\r
485\r
419973a6 486#define P32XF_68KCPOLL (1 << 0)\r
487#define P32XF_68KVPOLL (1 << 1)\r
488#define P32XF_Z80_32X_IO (1 << 7) // z80 does 32x io\r
4ea707e1 489\r
490#define P32XI_VRES (1 << 14/2) // IRL/2\r
491#define P32XI_VINT (1 << 12/2)\r
492#define P32XI_HINT (1 << 10/2)\r
493#define P32XI_CMD (1 << 8/2)\r
494#define P32XI_PWM (1 << 6/2)\r
495\r
1d7a28a7 496// peripheral reg access\r
497#define PREG8(regs,offs) ((unsigned char *)regs)[offs ^ 3]\r
498\r
7eaa3812 499#define DMAC_FIFO_LEN (4*2)\r
db1d3564 500#define PWM_BUFF_LEN 1024 // in one channel samples\r
266c6afa 501\r
f4bb5d6b 502#define SH2_DRCBLK_RAM_SHIFT 1\r
503#define SH2_DRCBLK_DA_SHIFT 1\r
504\r
f81107f5 505#define SH2_READ_SHIFT 25\r
e05b81fc 506#define SH2_WRITE_SHIFT 25\r
507\r
be2c4208 508struct Pico32x\r
509{\r
510 unsigned short regs[0x20];\r
5a681086 511 unsigned short vdp_regs[0x10]; // 0x40\r
512 unsigned short sh2_regs[3]; // 0x60\r
be2c4208 513 unsigned char pending_fb;\r
974fdb5b 514 unsigned char dirty_pal;\r
266c6afa 515 unsigned int emu_flags;\r
4ea707e1 516 unsigned char sh2irq_mask[2];\r
517 unsigned char sh2irqi[2]; // individual\r
518 unsigned int sh2irqs; // common irqs\r
519 unsigned short dmac_fifo[DMAC_FIFO_LEN];\r
7eaa3812 520 unsigned int pad[4];\r
df63f1a6 521 unsigned int dmac0_fifo_ptr;\r
4a1fb183 522 unsigned short vdp_fbcr_fake;\r
7eaa3812 523 unsigned short pad2;\r
a8fd6e37 524 unsigned char comm_dirty_68k;\r
525 unsigned char comm_dirty_sh2;\r
df63f1a6 526 unsigned char pwm_irq_cnt;\r
527 unsigned char pad1;\r
a7f82a77 528 unsigned short pwm_p[2]; // pwm pos in fifo\r
529 unsigned int pwm_cycle_p; // pwm play cursor (32x cycles)\r
530 unsigned int reserved[6];\r
974fdb5b 531};\r
532\r
533struct Pico32xMem\r
534{\r
535 unsigned char sdram[0x40000];\r
f4bb5d6b 536#ifdef DRC_SH2\r
537 unsigned short drcblk_ram[1 << (18 - SH2_DRCBLK_RAM_SHIFT)];\r
538#endif\r
b78efee2 539 unsigned short dram[2][0x20000/2]; // AKA fb\r
b4db550e 540 union {\r
541 unsigned char m68k_rom[0x100];\r
542 unsigned char m68k_rom_bank[0x10000]; // M68K_BANK_SIZE\r
543 };\r
f4bb5d6b 544#ifdef DRC_SH2\r
545 unsigned short drcblk_da[2][1 << (12 - SH2_DRCBLK_DA_SHIFT)];\r
546#endif\r
895d1512 547 union {\r
548 unsigned char b[0x800];\r
549 unsigned short w[0x800/2];\r
550 } sh2_rom_m;\r
551 union {\r
552 unsigned char b[0x400];\r
553 unsigned short w[0x400/2];\r
554 } sh2_rom_s;\r
974fdb5b 555 unsigned short pal[0x100];\r
5e128c6d 556 unsigned short pal_native[0x100]; // converted to native (for renderer)\r
db1d3564 557 signed short pwm[2*PWM_BUFF_LEN]; // PWM buffer for current frame\r
8ce9c3a7 558 signed short pwm_current[2]; // current converted samples\r
559 unsigned short pwm_fifo[2][4]; // [0] - current raw, others - fifo entries\r
be2c4208 560};\r
d49b10c2 561\r
c8d1e9b6 562// area.c\r
fad24893 563extern void (*PicoLoadStateHook)(void);\r
51a902ae 564\r
945c2fdc 565typedef struct {\r
566 int chunk;\r
567 int size;\r
568 void *ptr;\r
569} carthw_state_chunk;\r
570extern carthw_state_chunk *carthw_chunks;\r
571#define CHUNK_CARTHW 64\r
572\r
c8d1e9b6 573// cart.c\r
b4db550e 574extern int PicoCartResize(int newsize);\r
575extern void Byteswap(void *dst, const void *src, int len);\r
45f2f245 576extern void (*PicoCartMemSetup)(void);\r
e807ac75 577extern void (*PicoCartUnloadHook)(void);\r
1dceadae 578\r
c8d1e9b6 579// debug.c\r
b5e5172d 580int CM_compareRun(int cyc, int is_sub);\r
03e4f2a3 581\r
c8d1e9b6 582// draw.c\r
eff55556 583PICO_INTERNAL void PicoFrameStart(void);\r
b6d7ac70 584void PicoDrawSync(int to, int blank_last_line);\r
200772b7 585void BackFill(int reg7, int sh);\r
5a681086 586void FinalizeLine555(int sh, int line);\r
f4750ee0 587extern int (*PicoScanBegin)(unsigned int num);\r
588extern int (*PicoScanEnd)(unsigned int num);\r
b6d7ac70 589extern int DrawScanline;\r
f579f7b8 590#define MAX_LINE_SPRITES 29\r
591extern unsigned char HighLnSpr[240][3 + MAX_LINE_SPRITES];\r
5a681086 592extern void *DrawLineDestBase;\r
593extern int DrawLineDestIncrement;\r
cc68a136 594\r
c8d1e9b6 595// draw2.c\r
eff55556 596PICO_INTERNAL void PicoFrameFull();\r
cc68a136 597\r
200772b7 598// mode4.c\r
599void PicoFrameStartMode4(void);\r
600void PicoLineMode4(int line);\r
601void PicoDoHighPal555M4(void);\r
5a681086 602void PicoDrawSetOutputMode4(pdso_t which);\r
200772b7 603\r
c8d1e9b6 604// memory.c\r
eff55556 605PICO_INTERNAL void PicoMemSetup(void);\r
af37bca8 606unsigned int PicoRead8_io(unsigned int a);\r
607unsigned int PicoRead16_io(unsigned int a);\r
608void PicoWrite8_io(unsigned int a, unsigned int d);\r
609void PicoWrite16_io(unsigned int a, unsigned int d);\r
610\r
611// pico/memory.c\r
612PICO_INTERNAL void PicoMemSetupPico(void);\r
cc68a136 613\r
c8d1e9b6 614// cd/memory.c\r
eff55556 615PICO_INTERNAL void PicoMemSetupCD(void);\r
fa8fb754 616unsigned int PicoRead8_mcd_io(unsigned int a);\r
617unsigned int PicoRead16_mcd_io(unsigned int a);\r
618void PicoWrite8_mcd_io(unsigned int a, unsigned int d);\r
619void PicoWrite16_mcd_io(unsigned int a, unsigned int d);\r
ae214f1c 620void pcd_state_loaded_mem(void);\r
cc68a136 621\r
c8d1e9b6 622// pico.c\r
cc68a136 623extern struct Pico Pico;\r
624extern struct PicoSRAM SRam;\r
5f9a0d16 625extern int PicoPadInt[2];\r
cc68a136 626extern int emustatus;\r
5e128c6d 627extern int scanlines_total;\r
f8ef8ff7 628extern void (*PicoResetHook)(void);\r
b0677887 629extern void (*PicoLineHook)(void);\r
1e6b5e39 630PICO_INTERNAL int CheckDMA(void);\r
631PICO_INTERNAL void PicoDetectRegion(void);\r
ae214f1c 632PICO_INTERNAL void PicoSyncZ80(unsigned int m68k_cycles_done);\r
cc68a136 633\r
89dbbf2b 634// cd/mcd.c\r
ae214f1c 635#define PCDS_IEN1 (1<<1)\r
636#define PCDS_IEN2 (1<<2)\r
637#define PCDS_IEN3 (1<<3)\r
638#define PCDS_IEN4 (1<<4)\r
639#define PCDS_IEN5 (1<<5)\r
640#define PCDS_IEN6 (1<<6)\r
cc68a136 641\r
2aa27095 642PICO_INTERNAL void PicoInitMCD(void);\r
e5f426aa 643PICO_INTERNAL void PicoExitMCD(void);\r
1cb1584b 644PICO_INTERNAL void PicoPowerMCD(void);\r
2aa27095 645PICO_INTERNAL int PicoResetMCD(void);\r
646PICO_INTERNAL void PicoFrameMCD(void);\r
cc68a136 647\r
ae214f1c 648enum pcd_event {\r
649 PCD_EVENT_CDC,\r
650 PCD_EVENT_TIMER3,\r
651 PCD_EVENT_GFX,\r
652 PCD_EVENT_DMA,\r
653 PCD_EVENT_COUNT,\r
654};\r
655extern unsigned int pcd_event_times[PCD_EVENT_COUNT];\r
656void pcd_event_schedule(unsigned int now, enum pcd_event event, int after);\r
657void pcd_event_schedule_s68k(enum pcd_event event, int after);\r
658unsigned int pcd_cycles_m68k_to_s68k(unsigned int c);\r
08769494 659int pcd_sync_s68k(unsigned int m68k_target, int m68k_poll_sync);\r
fa8fb754 660void pcd_run_cpus(int m68k_cycles);\r
d0132772 661void pcd_soft_reset(void);\r
ae214f1c 662void pcd_state_loaded(void);\r
663\r
33be04ca 664// cd/pcm.c\r
665void pcd_pcm_sync(unsigned int to);\r
666void pcd_pcm_update(int *buffer, int length, int stereo);\r
667void pcd_pcm_write(unsigned int a, unsigned int d);\r
668unsigned int pcd_pcm_read(unsigned int a);\r
669\r
c8d1e9b6 670// pico/pico.c\r
2aa27095 671PICO_INTERNAL void PicoInitPico(void);\r
ed367a3f 672PICO_INTERNAL void PicoReratePico(void);\r
9037e45d 673\r
c8d1e9b6 674// pico/xpcm.c\r
ef4eb506 675PICO_INTERNAL void PicoPicoPCMUpdate(short *buffer, int length, int stereo);\r
676PICO_INTERNAL void PicoPicoPCMReset(void);\r
213c16ad 677PICO_INTERNAL void PicoPicoPCMRerate(int xpcm_rate);\r
ef4eb506 678\r
c8d1e9b6 679// sek.c\r
2aa27095 680PICO_INTERNAL void SekInit(void);\r
681PICO_INTERNAL int SekReset(void);\r
3aa1e148 682PICO_INTERNAL void SekState(int *data);\r
eff55556 683PICO_INTERNAL void SekSetRealTAS(int use_real);\r
b4db550e 684PICO_INTERNAL void SekPackCpu(unsigned char *cpu, int is_sub);\r
685PICO_INTERNAL void SekUnpackCpu(const unsigned char *cpu, int is_sub);\r
5f9a0d16 686void SekStepM68k(void);\r
053fd9b4 687void SekInitIdleDet(void);\r
688void SekFinishIdleDet(void);\r
12da51c2 689#if defined(CPU_CMP_R) || defined(CPU_CMP_W)\r
690void SekTrace(int is_s68k);\r
691#else\r
692#define SekTrace(x)\r
693#endif\r
cc68a136 694\r
c8d1e9b6 695// cd/sek.c\r
2aa27095 696PICO_INTERNAL void SekInitS68k(void);\r
697PICO_INTERNAL int SekResetS68k(void);\r
698PICO_INTERNAL int SekInterruptS68k(int irq);\r
cc68a136 699\r
7a93adeb 700// sound/sound.c\r
c9e1affc 701PICO_INTERNAL void cdda_start_play();\r
702extern short cdda_out_buffer[2*1152];\r
7a93adeb 703extern int PsndLen_exc_cnt;\r
704extern int PsndLen_exc_add;\r
48dc74f2 705extern int timer_a_next_oflow, timer_a_step; // in z80 cycles\r
706extern int timer_b_next_oflow, timer_b_step;\r
43e6eaad 707\r
708void ym2612_sync_timers(int z80_cycles, int mode_old, int mode_new);\r
d2721b08 709void ym2612_pack_state(void);\r
453d2a6e 710void ym2612_unpack_state(void);\r
4b9c5888 711\r
e53704e6 712#define TIMER_NO_OFLOW 0x70000000\r
45a1ef71 713// tA = 72 * (1024 - NA) / M\r
714#define TIMER_A_TICK_ZCYCLES 17203\r
715// tB = 1152 * (256 - NA) / M\r
716#define TIMER_B_TICK_ZCYCLES 262800 // 275251 broken, see Dai Makaimura\r
e53704e6 717\r
4b9c5888 718#define timers_cycle() \\r
e53704e6 719 if (timer_a_next_oflow > 0 && timer_a_next_oflow < TIMER_NO_OFLOW) \\r
43e6eaad 720 timer_a_next_oflow -= Pico.m.pal ? 70938*256 : 59659*256; \\r
e53704e6 721 if (timer_b_next_oflow > 0 && timer_b_next_oflow < TIMER_NO_OFLOW) \\r
43e6eaad 722 timer_b_next_oflow -= Pico.m.pal ? 70938*256 : 59659*256; \\r
723 ym2612_sync_timers(0, ym2612.OPN.ST.mode, ym2612.OPN.ST.mode);\r
4b9c5888 724\r
725#define timers_reset() \\r
e53704e6 726 timer_a_next_oflow = timer_b_next_oflow = TIMER_NO_OFLOW; \\r
48dc74f2 727 timer_a_step = TIMER_A_TICK_ZCYCLES * 1024; \\r
728 timer_b_step = TIMER_B_TICK_ZCYCLES * 256;\r
43e6eaad 729\r
7a93adeb 730\r
c8d1e9b6 731// videoport.c\r
53f948c9 732extern int line_base_cycles;\r
eff55556 733PICO_INTERNAL_ASM void PicoVideoWrite(unsigned int a,unsigned short d);\r
734PICO_INTERNAL_ASM unsigned int PicoVideoRead(unsigned int a);\r
9761a7d0 735PICO_INTERNAL_ASM unsigned int PicoVideoRead8(unsigned int a);\r
5de27868 736extern int (*PicoDmaHook)(unsigned int source, int len, unsigned short **srcp, unsigned short **limitp);\r
cc68a136 737\r
c8d1e9b6 738// misc.c\r
eff55556 739PICO_INTERNAL_ASM void memcpy16(unsigned short *dest, unsigned short *src, int count);\r
740PICO_INTERNAL_ASM void memcpy16bswap(unsigned short *dest, void *src, int count);\r
741PICO_INTERNAL_ASM void memcpy32(int *dest, int *src, int count); // 32bit word count\r
742PICO_INTERNAL_ASM void memset32(int *dest, int c, int count);\r
cc68a136 743\r
45f2f245 744// eeprom.c\r
745void EEPROM_write8(unsigned int a, unsigned int d);\r
746void EEPROM_write16(unsigned int d);\r
747unsigned int EEPROM_read(void);\r
748\r
c8d1e9b6 749// z80 functionality wrappers\r
750PICO_INTERNAL void z80_init(void);\r
b4db550e 751PICO_INTERNAL void z80_pack(void *data);\r
752PICO_INTERNAL int z80_unpack(const void *data);\r
c8d1e9b6 753PICO_INTERNAL void z80_reset(void);\r
754PICO_INTERNAL void z80_exit(void);\r
c8d1e9b6 755\r
756// cd/misc.c\r
eff55556 757PICO_INTERNAL_ASM void wram_2M_to_1M(unsigned char *m);\r
758PICO_INTERNAL_ASM void wram_1M_to_2M(unsigned char *m);\r
759\r
760// cd/buffering.c\r
761PICO_INTERNAL void PicoCDBufferRead(void *dest, int lba);\r
762\r
763// sound/sound.c\r
9d917eea 764PICO_INTERNAL void PsndReset(void);\r
4b9c5888 765PICO_INTERNAL void PsndDoDAC(int line_to);\r
9d917eea 766PICO_INTERNAL void PsndClear(void);\r
7b3f44c6 767PICO_INTERNAL void PsndGetSamples(int y);\r
2ec9bec5 768PICO_INTERNAL void PsndGetSamplesMS(void);\r
4b9c5888 769extern int PsndDacLine;\r
cc68a136 770\r
3e49ffd0 771// sms.c\r
f3a57b2d 772#ifndef NO_SMS\r
3e49ffd0 773void PicoPowerMS(void);\r
2ec9bec5 774void PicoResetMS(void);\r
3e49ffd0 775void PicoMemSetupMS(void);\r
b4db550e 776void PicoStateLoadedMS(void);\r
3e49ffd0 777void PicoFrameMS(void);\r
87b0845f 778void PicoFrameDrawOnlyMS(void);\r
f3a57b2d 779#else\r
780#define PicoPowerMS()\r
781#define PicoResetMS()\r
782#define PicoMemSetupMS()\r
783#define PicoStateLoadedMS()\r
784#define PicoFrameMS()\r
785#define PicoFrameDrawOnlyMS()\r
786#endif\r
3e49ffd0 787\r
be2c4208 788// 32x/32x.c\r
f3a57b2d 789#ifndef NO_32X\r
be2c4208 790extern struct Pico32x Pico32x;\r
6a98f03e 791enum p32x_event {\r
792 P32X_EVENT_PWM,\r
793 P32X_EVENT_FILLEND,\r
5ac99d9a 794 P32X_EVENT_HINT,\r
6a98f03e 795 P32X_EVENT_COUNT,\r
796};\r
ae214f1c 797extern unsigned int p32x_event_times[P32X_EVENT_COUNT];\r
6a98f03e 798\r
be2c4208 799void Pico32xInit(void);\r
974fdb5b 800void PicoPower32x(void);\r
be2c4208 801void PicoReset32x(void);\r
974fdb5b 802void Pico32xStartup(void);\r
5e49c3a8 803void PicoUnload32x(void);\r
974fdb5b 804void PicoFrame32x(void);\r
27e26273 805void Pico32xStateLoaded(int is_early);\r
ed4402a7 806void p32x_sync_sh2s(unsigned int m68k_target);\r
19886062 807void p32x_sync_other_sh2(SH2 *sh2, unsigned int m68k_target);\r
4d5dfee8 808void p32x_update_irls(SH2 *active_sh2, int m68k_cycles);\r
9e1fa0a6 809void p32x_trigger_irq(SH2 *sh2, int m68k_cycles, unsigned int mask);\r
810void p32x_update_cmd_irq(SH2 *sh2, int m68k_cycles);\r
83ff19ec 811void p32x_reset_sh2s(void);\r
19886062 812void p32x_event_schedule(unsigned int now, enum p32x_event event, int after);\r
813void p32x_event_schedule_sh2(SH2 *sh2, enum p32x_event event, int after);\r
5ac99d9a 814void p32x_schedule_hint(SH2 *sh2, int m68k_cycles);\r
a8fd6e37 815\r
be2c4208 816// 32x/memory.c\r
974fdb5b 817struct Pico32xMem *Pico32xMem;\r
be2c4208 818unsigned int PicoRead8_32x(unsigned int a);\r
819unsigned int PicoRead16_32x(unsigned int a);\r
820void PicoWrite8_32x(unsigned int a, unsigned int d);\r
821void PicoWrite16_32x(unsigned int a, unsigned int d);\r
822void PicoMemSetup32x(void);\r
974fdb5b 823void Pico32xSwapDRAM(int b);\r
27e26273 824void Pico32xMemStateLoaded(void);\r
19886062 825void p32x_m68k_poll_event(unsigned int flags);\r
826void p32x_sh2_poll_event(SH2 *sh2, unsigned int flags, unsigned int m68k_cycles);\r
974fdb5b 827\r
828// 32x/draw.c\r
41946d70 829void PicoDrawSetOutFormat32x(pdso_t which, int use_32x_line_mode);\r
974fdb5b 830void FinalizeLine32xRGB555(int sh, int line);\r
5a681086 831void PicoDraw32xLayer(int offs, int lines, int mdbg);\r
7a961c19 832void PicoDraw32xLayerMdOnly(int offs, int lines);\r
f4750ee0 833extern int (*PicoScan32xBegin)(unsigned int num);\r
834extern int (*PicoScan32xEnd)(unsigned int num);\r
7a961c19 835enum {\r
836 PDM32X_OFF,\r
837 PDM32X_32X_ONLY,\r
838 PDM32X_BOTH,\r
839};\r
5a681086 840extern int Pico32xDrawMode;\r
be2c4208 841\r
db1d3564 842// 32x/pwm.c\r
c1931173 843unsigned int p32x_pwm_read16(unsigned int a, SH2 *sh2,\r
844 unsigned int m68k_cycles);\r
845void p32x_pwm_write16(unsigned int a, unsigned int d,\r
846 SH2 *sh2, unsigned int m68k_cycles);\r
db1d3564 847void p32x_pwm_update(int *buf32, int length, int stereo);\r
045a4c52 848void p32x_pwm_ctl_changed(void);\r
df63f1a6 849void p32x_pwm_schedule(unsigned int m68k_now);\r
19886062 850void p32x_pwm_schedule_sh2(SH2 *sh2);\r
9e1fa0a6 851void p32x_pwm_sync_to_sh2(SH2 *sh2);\r
df63f1a6 852void p32x_pwm_irq_event(unsigned int m68k_now);\r
853void p32x_pwm_state_loaded(void);\r
045a4c52 854\r
855// 32x/sh2soc.c\r
856void p32x_dreq0_trigger(void);\r
857void p32x_dreq1_trigger(void);\r
858void p32x_timers_recalc(void);\r
859void p32x_timers_do(unsigned int m68k_slice);\r
cd0ace28 860void sh2_peripheral_reset(SH2 *sh2);\r
f81107f5 861unsigned int sh2_peripheral_read8(unsigned int a, SH2 *sh2);\r
862unsigned int sh2_peripheral_read16(unsigned int a, SH2 *sh2);\r
863unsigned int sh2_peripheral_read32(unsigned int a, SH2 *sh2);\r
8b43bc73 864void REGPARM(3) sh2_peripheral_write8(unsigned int a, unsigned int d, SH2 *sh2);\r
865void REGPARM(3) sh2_peripheral_write16(unsigned int a, unsigned int d, SH2 *sh2);\r
866void REGPARM(3) sh2_peripheral_write32(unsigned int a, unsigned int d, SH2 *sh2);\r
045a4c52 867\r
f3a57b2d 868#else\r
869#define Pico32xInit()\r
870#define PicoPower32x()\r
871#define PicoReset32x()\r
872#define PicoFrame32x()\r
873#define PicoUnload32x()\r
874#define Pico32xStateLoaded()\r
f3a57b2d 875#define FinalizeLine32xRGB555 NULL\r
876#define p32x_pwm_update(...)\r
877#define p32x_timers_recalc()\r
878#endif\r
db1d3564 879\r
45f2f245 880/* avoid dependency on newer glibc */\r
881static __inline int isspace_(int c)\r
882{\r
883 return (0x09 <= c && c <= 0x0d) || c == ' ';\r
884}\r
885\r
f4bb5d6b 886#ifndef ARRAY_SIZE\r
887#define ARRAY_SIZE(x) (sizeof(x) / sizeof(x[0]))\r
888#endif\r
889\r
b8cbd802 890// emulation event logging\r
891#ifndef EL_LOGMASK\r
9c9cda8c 892# ifdef __x86_64__ // HACK\r
893# define EL_LOGMASK (EL_STATUS|EL_IDLE|EL_ANOMALY)\r
894# else\r
1555935b 895# define EL_LOGMASK (EL_STATUS)\r
9c9cda8c 896# endif\r
b8cbd802 897#endif\r
898\r
017512f2 899#define EL_HVCNT 0x00000001 /* hv counter reads */\r
900#define EL_SR 0x00000002 /* SR reads */\r
901#define EL_INTS 0x00000004 /* ints and acks */\r
43e6eaad 902#define EL_YMTIMER 0x00000008 /* ym2612 timer stuff */\r
017512f2 903#define EL_INTSW 0x00000010 /* log irq switching on/off */\r
904#define EL_ASVDP 0x00000020 /* VDP accesses during active scan */\r
905#define EL_VDPDMA 0x00000040 /* VDP DMA transfers and their timing */\r
906#define EL_BUSREQ 0x00000080 /* z80 busreq r/w or reset w */\r
907#define EL_Z80BNK 0x00000100 /* z80 i/o through bank area */\r
908#define EL_SRAMIO 0x00000200 /* sram i/o */\r
909#define EL_EEPROM 0x00000400 /* eeprom debug */\r
910#define EL_UIO 0x00000800 /* unmapped i/o */\r
911#define EL_IO 0x00001000 /* all i/o */\r
912#define EL_CDPOLL 0x00002000 /* MCD: log poll detection */\r
913#define EL_SVP 0x00004000 /* SVP stuff */\r
fa22af4c 914#define EL_PICOHW 0x00008000 /* Pico stuff */\r
053fd9b4 915#define EL_IDLE 0x00010000 /* idle loop det. */\r
af37bca8 916#define EL_CDREGS 0x00020000 /* MCD: register access */\r
917#define EL_CDREG3 0x00040000 /* MCD: register 3 only */\r
be2c4208 918#define EL_32X 0x00080000\r
1b3f5844 919#define EL_PWM 0x00100000 /* 32X PWM stuff (LOTS of output) */\r
045a4c52 920#define EL_32XP 0x00200000 /* 32X peripherals */\r
ae214f1c 921#define EL_CD 0x00400000 /* MCD */\r
017512f2 922\r
923#define EL_STATUS 0x40000000 /* status messages */\r
924#define EL_ANOMALY 0x80000000 /* some unexpected conditions (during emulation) */\r
b8cbd802 925\r
926#if EL_LOGMASK\r
927#define elprintf(w,f,...) \\r
a8fd6e37 928do { \\r
b8cbd802 929 if ((w) & EL_LOGMASK) \\r
7d0143a2 930 lprintf("%05i:%03i: " f "\n",Pico.m.frame_count,Pico.m.scanline,##__VA_ARGS__); \\r
a8fd6e37 931} while (0)\r
dca310c4 932#elif defined(_MSC_VER)\r
933#define elprintf\r
b8cbd802 934#else\r
935#define elprintf(w,f,...)\r
936#endif\r
937\r
f6c49d38 938// profiling\r
939#ifdef PPROF\r
940#include <platform/linux/pprof.h>\r
941#else\r
942#define pprof_init()\r
943#define pprof_finish()\r
944#define pprof_start(x)\r
945#define pprof_end(...)\r
946#define pprof_end_sub(...)\r
947#endif\r
948\r
19886062 949#ifdef EVT_LOG\r
950enum evt {\r
951 EVT_FRAME_START,\r
952 EVT_NEXT_LINE,\r
953 EVT_RUN_START,\r
954 EVT_RUN_END,\r
955 EVT_POLL_START,\r
956 EVT_POLL_END,\r
957 EVT_CNT\r
958};\r
959\r
960enum evt_cpu {\r
961 EVT_M68K,\r
962 EVT_S68K,\r
963 EVT_MSH2,\r
964 EVT_SSH2,\r
965 EVT_CPU_CNT\r
966};\r
967\r
968void pevt_log(unsigned int cycles, enum evt_cpu c, enum evt e);\r
969void pevt_dump(void);\r
970\r
971#define pevt_log_m68k(e) \\r
08769494 972 pevt_log(SekCyclesDone(), EVT_M68K, e)\r
19886062 973#define pevt_log_m68k_o(e) \\r
08769494 974 pevt_log(SekCyclesDone(), EVT_M68K, e)\r
19886062 975#define pevt_log_sh2(sh2, e) \\r
976 pevt_log(sh2_cycles_done_m68k(sh2), EVT_MSH2 + (sh2)->is_slave, e)\r
977#define pevt_log_sh2_o(sh2, e) \\r
978 pevt_log((sh2)->m68krcycles_done, EVT_MSH2 + (sh2)->is_slave, e)\r
979#else\r
980#define pevt_log(c, e)\r
981#define pevt_log_m68k(e)\r
982#define pevt_log_m68k_o(e)\r
983#define pevt_log_sh2(sh2, e)\r
984#define pevt_log_sh2_o(sh2, e)\r
985#define pevt_dump()\r
986#endif\r
987\r
f6c49d38 988// misc\r
dca310c4 989#ifdef _MSC_VER\r
990#define cdprintf\r
991#else\r
992#define cdprintf(x...)\r
993#endif\r
994\r
8b43bc73 995#if defined(__GNUC__) && defined(__i386__)\r
553c3eaa 996#define REGPARM(x) __attribute__((regparm(x)))\r
c8d1e9b6 997#else\r
553c3eaa 998#define REGPARM(x)\r
c8d1e9b6 999#endif\r
1000\r
5e89f0f5 1001#ifdef __GNUC__\r
1002#define NOINLINE __attribute__((noinline))\r
1003#else\r
1004#define NOINLINE\r
1005#endif\r
1006\r
f8af9634 1007#ifdef __cplusplus\r
1008} // End of extern "C"\r
1009#endif\r
1010\r
eff55556 1011#endif // PICO_INTERNAL_INCLUDED\r
1012\r
fast MegaDrive/MegaCD/32X emulator