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drc: restore all block entry points at once
[pcsx_rearmed.git] / libpcsxcore / new_dynarec / new_dynarec.c
CommitLineData
57871462 1/* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
2 * Mupen64plus - new_dynarec.c *
20d507ba 3 * Copyright (C) 2009-2011 Ari64 *
57871462 4 * *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
9 * *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
14 * *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. *
19 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */
20
21#include <stdlib.h>
22#include <stdint.h> //include for uint64_t
23#include <assert.h>
d848b60a 24#include <errno.h>
4600ba03 25#include <sys/mman.h>
d148d265 26#ifdef __MACH__
27#include <libkern/OSCacheControl.h>
28#endif
1e212a25 29#ifdef _3DS
30#include <3ds_utils.h>
31#endif
57871462 32
d148d265 33#include "new_dynarec_config.h"
3968e69e 34#include "../psxhle.h"
35#include "../psxinterpreter.h"
81dbbf4c 36#include "../gte.h"
37#include "emu_if.h" // emulator interface
cdc2da64 38#include "arm_features.h"
57871462 39
d1e4ebd9 40#define noinline __attribute__((noinline,noclone))
b14b6a8f 41#ifndef ARRAY_SIZE
42#define ARRAY_SIZE(x) (sizeof(x) / sizeof(x[0]))
43#endif
e3c6bdb5 44#ifndef min
45#define min(a, b) ((b) < (a) ? (b) : (a))
46#endif
32631e6a 47#ifndef max
48#define max(a, b) ((b) > (a) ? (b) : (a))
49#endif
b14b6a8f 50
4600ba03 51//#define DISASM
32631e6a 52//#define ASSEM_PRINT
ece032e6 53//#define STAT_PRINT
32631e6a 54
55#ifdef ASSEM_PRINT
56#define assem_debug printf
57#else
4600ba03 58#define assem_debug(...)
32631e6a 59#endif
60//#define inv_debug printf
4600ba03 61#define inv_debug(...)
57871462 62
63#ifdef __i386__
64#include "assem_x86.h"
65#endif
66#ifdef __x86_64__
67#include "assem_x64.h"
68#endif
69#ifdef __arm__
70#include "assem_arm.h"
71#endif
be516ebe 72#ifdef __aarch64__
73#include "assem_arm64.h"
74#endif
57871462 75
81dbbf4c 76#define RAM_SIZE 0x200000
57871462 77#define MAXBLOCK 4096
78#define MAX_OUTPUT_BLOCK_SIZE 262144
2573466a 79
66ea165f 80#ifdef VITA
81// apparently Vita has a 16MB limit, so either we cut tc in half,
82// or use this hack (it's a hack because tc size was designed to be power-of-2)
83#define TC_REDUCE_BYTES 4096
84#else
85#define TC_REDUCE_BYTES 0
86#endif
87
2a014d73 88struct ndrc_mem
89{
66ea165f 90 u_char translation_cache[(1 << TARGET_SIZE_2) - TC_REDUCE_BYTES];
2a014d73 91 struct
92 {
93 struct tramp_insns ops[2048 / sizeof(struct tramp_insns)];
94 const void *f[2048 / sizeof(void *)];
95 } tramp;
96};
97
98#ifdef BASE_ADDR_DYNAMIC
99static struct ndrc_mem *ndrc;
100#else
101static struct ndrc_mem ndrc_ __attribute__((aligned(4096)));
102static struct ndrc_mem *ndrc = &ndrc_;
103#endif
104
b14b6a8f 105// stubs
106enum stub_type {
107 CC_STUB = 1,
108 FP_STUB = 2,
109 LOADB_STUB = 3,
110 LOADH_STUB = 4,
111 LOADW_STUB = 5,
112 LOADD_STUB = 6,
113 LOADBU_STUB = 7,
114 LOADHU_STUB = 8,
115 STOREB_STUB = 9,
116 STOREH_STUB = 10,
117 STOREW_STUB = 11,
118 STORED_STUB = 12,
119 STORELR_STUB = 13,
120 INVCODE_STUB = 14,
121};
122
6cc8d23c 123// regmap_pre[i] - regs before [i] insn starts; dirty things here that
124// don't match .regmap will be written back
125// [i].regmap_entry - regs that must be set up if someone jumps here
126// [i].regmap - regs [i] insn will read/(over)write
2acc46cd 127// branch_regs[i].* - same as above but for branches, takes delay slot into account
57871462 128struct regstat
129{
6cc8d23c 130 signed char regmap_entry[HOST_REGS];
57871462 131 signed char regmap[HOST_REGS];
57871462 132 uint64_t wasdirty;
133 uint64_t dirty;
134 uint64_t u;
24058131 135 u_int wasconst; // before; for example 'lw r2, (r2)' wasconst is true
136 u_int isconst; // ... but isconst is false when r2 is known
8575a877 137 u_int loadedconst; // host regs that have constants loaded
138 u_int waswritten; // MIPS regs that were used as store base before
57871462 139};
140
de5a60c3 141// note: asm depends on this layout
57871462 142struct ll_entry
143{
144 u_int vaddr;
de5a60c3 145 u_int reg_sv_flags;
57871462 146 void *addr;
147 struct ll_entry *next;
148};
149
df4dc2b1 150struct ht_entry
151{
152 u_int vaddr[2];
153 void *tcaddr[2];
154};
155
b14b6a8f 156struct code_stub
157{
158 enum stub_type type;
159 void *addr;
160 void *retaddr;
161 u_int a;
162 uintptr_t b;
163 uintptr_t c;
164 u_int d;
165 u_int e;
166};
167
643aeae3 168struct link_entry
169{
170 void *addr;
171 u_int target;
172 u_int ext;
173};
174
cf95b4f0 175static struct decoded_insn
176{
177 u_char itype;
178 u_char opcode;
179 u_char opcode2;
180 u_char rs1;
181 u_char rs2;
182 u_char rt1;
183 u_char rt2;
53dc27f6 184 u_char use_lt1:1;
cf95b4f0 185 u_char bt:1;
cf95b4f0 186 u_char ooo:1;
187 u_char is_ds:1;
fe807a8a 188 u_char is_jump:1;
189 u_char is_ujump:1;
37387d8b 190 u_char is_load:1;
191 u_char is_store:1;
cf95b4f0 192} dops[MAXBLOCK];
193
e2b5e7aa 194 // used by asm:
df4dc2b1 195 struct ht_entry hash_table[65536] __attribute__((aligned(16)));
e2b5e7aa 196 struct ll_entry *jump_in[4096] __attribute__((aligned(16)));
e2b5e7aa 197
398d6924 198 static u_char *out;
199 static struct ll_entry *jump_dirty[4096];
e2b5e7aa 200 static struct ll_entry *jump_out[4096];
201 static u_int start;
202 static u_int *source;
bedfea38 203 static uint64_t gte_rs[MAXBLOCK]; // gte: 32 data and 32 ctl regs
204 static uint64_t gte_rt[MAXBLOCK];
205 static uint64_t gte_unneeded[MAXBLOCK];
ffb0b9e0 206 static u_int smrv[32]; // speculated MIPS register values
207 static u_int smrv_strong; // mask or regs that are likely to have correct values
208 static u_int smrv_weak; // same, but somewhat less likely
209 static u_int smrv_strong_next; // same, but after current insn executes
210 static u_int smrv_weak_next;
e2b5e7aa 211 static int imm[MAXBLOCK];
212 static u_int ba[MAXBLOCK];
e2b5e7aa 213 static uint64_t unneeded_reg[MAXBLOCK];
e2b5e7aa 214 static uint64_t branch_unneeded_reg[MAXBLOCK];
6cc8d23c 215 // see 'struct regstat' for a description
2330734f 216 static signed char regmap_pre[MAXBLOCK][HOST_REGS];
40fca85b 217 // contains 'real' consts at [i] insn, but may differ from what's actually
218 // loaded in host reg as 'final' value is always loaded, see get_final_value()
219 static uint32_t current_constmap[HOST_REGS];
220 static uint32_t constmap[MAXBLOCK][HOST_REGS];
956f3129 221 static struct regstat regs[MAXBLOCK];
222 static struct regstat branch_regs[MAXBLOCK];
e2b5e7aa 223 static signed char minimum_free_regs[MAXBLOCK];
e2b5e7aa 224 static int ccadj[MAXBLOCK];
225 static int slen;
df4dc2b1 226 static void *instr_addr[MAXBLOCK];
643aeae3 227 static struct link_entry link_addr[MAXBLOCK];
e2b5e7aa 228 static int linkcount;
b14b6a8f 229 static struct code_stub stubs[MAXBLOCK*3];
e2b5e7aa 230 static int stubcount;
231 static u_int literals[1024][2];
232 static int literalcount;
233 static int is_delayslot;
e2b5e7aa 234 static char shadow[1048576] __attribute__((aligned(16)));
235 static void *copy;
236 static int expirep;
237 static u_int stop_after_jal;
7f94b097 238 static u_int f1_hack;
ece032e6 239#ifdef STAT_PRINT
240 static int stat_bc_direct;
241 static int stat_bc_pre;
242 static int stat_bc_restore;
243 static int stat_jump_in_lookups;
244 static int stat_restore_tries;
245 static int stat_restore_compares;
246 static int stat_inv_addr_calls;
247 static int stat_inv_hits;
248 #define stat_inc(s) s++
249#else
250 #define stat_inc(s)
251#endif
e2b5e7aa 252
253 int new_dynarec_hacks;
d62c125a 254 int new_dynarec_hacks_pergame;
32631e6a 255 int new_dynarec_hacks_old;
e2b5e7aa 256 int new_dynarec_did_compile;
687b4580 257
d62c125a 258 #define HACK_ENABLED(x) ((new_dynarec_hacks | new_dynarec_hacks_pergame) & (x))
259
687b4580 260 extern int cycle_count; // ... until end of the timeslice, counts -N -> 0
261 extern int last_count; // last absolute target, often = next_interupt
262 extern int pcaddr;
263 extern int pending_exception;
264 extern int branch_target;
37387d8b 265 extern uintptr_t ram_offset;
d1e4ebd9 266 extern uintptr_t mini_ht[32][2];
57871462 267
268 /* registers that may be allocated */
269 /* 1-31 gpr */
7c3a5182 270#define LOREG 32 // lo
271#define HIREG 33 // hi
00fa9369 272//#define FSREG 34 // FPU status (FCSR)
57871462 273#define CSREG 35 // Coprocessor status
274#define CCREG 36 // Cycle count
275#define INVCP 37 // Pointer to invalid_code
1edfcc68 276//#define MMREG 38 // Pointer to memory_map
37387d8b 277#define ROREG 39 // ram offset (if rdram!=0x80000000)
619e5ded 278#define TEMPREG 40
279#define FTEMP 40 // FPU temporary register
280#define PTEMP 41 // Prefetch temporary register
1edfcc68 281//#define TLREG 42 // TLB mapping offset
619e5ded 282#define RHASH 43 // Return address hash
283#define RHTBL 44 // Return address hash table address
284#define RTEMP 45 // JR/JALR address register
285#define MAXREG 45
286#define AGEN1 46 // Address generation temporary register
1edfcc68 287//#define AGEN2 47 // Address generation temporary register
288//#define MGEN1 48 // Maptable address generation temporary register
289//#define MGEN2 49 // Maptable address generation temporary register
619e5ded 290#define BTREG 50 // Branch target temporary register
57871462 291
292 /* instruction types */
293#define NOP 0 // No operation
294#define LOAD 1 // Load
295#define STORE 2 // Store
296#define LOADLR 3 // Unaligned load
297#define STORELR 4 // Unaligned store
9f51b4b9 298#define MOV 5 // Move
57871462 299#define ALU 6 // Arithmetic/logic
300#define MULTDIV 7 // Multiply/divide
301#define SHIFT 8 // Shift by register
302#define SHIFTIMM 9// Shift by immediate
303#define IMM16 10 // 16-bit immediate
304#define RJUMP 11 // Unconditional jump to register
305#define UJUMP 12 // Unconditional jump
306#define CJUMP 13 // Conditional branch (BEQ/BNE/BGTZ/BLEZ)
307#define SJUMP 14 // Conditional branch (regimm format)
308#define COP0 15 // Coprocessor 0
309#define COP1 16 // Coprocessor 1
310#define C1LS 17 // Coprocessor 1 load/store
ad49de89 311//#define FJUMP 18 // Conditional branch (floating point)
00fa9369 312//#define FLOAT 19 // Floating point unit
313//#define FCONV 20 // Convert integer to float
314//#define FCOMP 21 // Floating point compare (sets FSREG)
d1150cd6 315#define SYSCALL 22// SYSCALL,BREAK
57871462 316#define OTHER 23 // Other
317#define SPAN 24 // Branch/delay slot spans 2 pages
318#define NI 25 // Not implemented
7139f3c8 319#define HLECALL 26// PCSX fake opcodes for HLE
b9b61529 320#define COP2 27 // Coprocessor 2 move
321#define C2LS 28 // Coprocessor 2 load/store
322#define C2OP 29 // Coprocessor 2 operation
1e973cb0 323#define INTCALL 30// Call interpreter to handle rare corner cases
57871462 324
57871462 325 /* branch codes */
326#define TAKEN 1
327#define NOTTAKEN 2
328#define NULLDS 3
329
7c3a5182 330#define DJT_1 (void *)1l // no function, just a label in assem_debug log
331#define DJT_2 (void *)2l
332
57871462 333// asm linkage
3968e69e 334int new_recompile_block(u_int addr);
57871462 335void *get_addr_ht(u_int vaddr);
336void invalidate_block(u_int block);
337void invalidate_addr(u_int addr);
57871462 338void dyna_linker();
339void dyna_linker_ds();
340void verify_code();
57871462 341void verify_code_ds();
342void cc_interrupt();
343void fp_exception();
344void fp_exception_ds();
d1150cd6 345void jump_syscall (u_int u0, u_int u1, u_int pc);
346void jump_syscall_ds(u_int u0, u_int u1, u_int pc);
347void jump_break (u_int u0, u_int u1, u_int pc);
348void jump_break_ds(u_int u0, u_int u1, u_int pc);
3968e69e 349void jump_to_new_pc();
81dbbf4c 350void call_gteStall();
4149788d 351void add_jump_out(u_int vaddr, void *src);
7139f3c8 352void new_dyna_leave();
57871462 353
398d6924 354static void *get_clean_addr(void *addr);
355static void get_bounds(void *addr, u_char **start, u_char **end);
356static void ll_add_flags(struct ll_entry **head,int vaddr,u_int reg_sv_flags,void *addr);
357
57871462 358// Needed by assembler
2330734f 359static void wb_register(signed char r, const signed char regmap[], uint64_t dirty);
360static void wb_dirtys(const signed char i_regmap[], uint64_t i_dirty);
361static void wb_needed_dirtys(const signed char i_regmap[], uint64_t i_dirty, int addr);
362static void load_all_regs(const signed char i_regmap[]);
363static void load_needed_regs(const signed char i_regmap[], const signed char next_regmap[]);
e2b5e7aa 364static void load_regs_entry(int t);
2330734f 365static void load_all_consts(const signed char regmap[], u_int dirty, int i);
81dbbf4c 366static u_int get_host_reglist(const signed char *regmap);
e2b5e7aa 367
3968e69e 368static int verify_dirty(const u_int *ptr);
e2b5e7aa 369static int get_final_value(int hr, int i, int *value);
b14b6a8f 370static void add_stub(enum stub_type type, void *addr, void *retaddr,
371 u_int a, uintptr_t b, uintptr_t c, u_int d, u_int e);
372static void add_stub_r(enum stub_type type, void *addr, void *retaddr,
81dbbf4c 373 int i, int addr_reg, const struct regstat *i_regs, int ccadj, u_int reglist);
643aeae3 374static void add_to_linker(void *addr, u_int target, int ext);
37387d8b 375static void *emit_fastpath_cmp_jump(int i, const struct regstat *i_regs,
376 int addr, int *offset_reg, int *addr_reg_override);
687b4580 377static void *get_direct_memhandler(void *table, u_int addr,
378 enum stub_type type, uintptr_t *addr_host);
32631e6a 379static void cop2_do_stall_check(u_int op, int i, const struct regstat *i_regs, u_int reglist);
687b4580 380static void pass_args(int a0, int a1);
2a014d73 381static void emit_far_jump(const void *f);
382static void emit_far_call(const void *f);
57871462 383
9c67c98f 384#ifdef VITA
385#include <psp2/kernel/sysmem.h>
386static int sceBlock;
387// note: this interacts with RetroArch's Vita bootstrap code: bootstrap/vita/sbrk.c
388extern int getVMBlock();
389int _newlib_vm_size_user = sizeof(*ndrc);
390#endif
391
d148d265 392static void mprotect_w_x(void *start, void *end, int is_x)
393{
394#ifdef NO_WRITE_EXEC
1e212a25 395 #if defined(VITA)
396 // *Open* enables write on all memory that was
397 // allocated by sceKernelAllocMemBlockForVM()?
398 if (is_x)
399 sceKernelCloseVMDomain();
400 else
401 sceKernelOpenVMDomain();
402 #else
d148d265 403 u_long mstart = (u_long)start & ~4095ul;
404 u_long mend = (u_long)end;
405 if (mprotect((void *)mstart, mend - mstart,
406 PROT_READ | (is_x ? PROT_EXEC : PROT_WRITE)) != 0)
407 SysPrintf("mprotect(%c) failed: %s\n", is_x ? 'x' : 'w', strerror(errno));
1e212a25 408 #endif
d148d265 409#endif
410}
411
412static void start_tcache_write(void *start, void *end)
413{
414 mprotect_w_x(start, end, 0);
415}
416
417static void end_tcache_write(void *start, void *end)
418{
919981d0 419#if defined(__arm__) || defined(__aarch64__)
d148d265 420 size_t len = (char *)end - (char *)start;
421 #if defined(__BLACKBERRY_QNX__)
422 msync(start, len, MS_SYNC | MS_CACHE_ONLY | MS_INVALIDATE_ICACHE);
423 #elif defined(__MACH__)
424 sys_cache_control(kCacheFunctionPrepareForExecution, start, len);
425 #elif defined(VITA)
1e212a25 426 sceKernelSyncVMDomain(sceBlock, start, len);
427 #elif defined(_3DS)
428 ctr_flush_invalidate_cache();
919981d0 429 #elif defined(__aarch64__)
430 // as of 2021, __clear_cache() is still broken on arm64
431 // so here is a custom one :(
432 clear_cache_arm64(start, end);
d148d265 433 #else
434 __clear_cache(start, end);
435 #endif
436 (void)len;
437#endif
438
439 mprotect_w_x(start, end, 1);
440}
441
442static void *start_block(void)
443{
444 u_char *end = out + MAX_OUTPUT_BLOCK_SIZE;
2a014d73 445 if (end > ndrc->translation_cache + sizeof(ndrc->translation_cache))
446 end = ndrc->translation_cache + sizeof(ndrc->translation_cache);
d148d265 447 start_tcache_write(out, end);
448 return out;
449}
450
451static void end_block(void *start)
452{
453 end_tcache_write(start, out);
454}
455
919981d0 456// also takes care of w^x mappings when patching code
457static u_int needs_clear_cache[1<<(TARGET_SIZE_2-17)];
458
459static void mark_clear_cache(void *target)
460{
461 uintptr_t offset = (u_char *)target - ndrc->translation_cache;
462 u_int mask = 1u << ((offset >> 12) & 31);
463 if (!(needs_clear_cache[offset >> 17] & mask)) {
464 char *start = (char *)((uintptr_t)target & ~4095l);
465 start_tcache_write(start, start + 4095);
466 needs_clear_cache[offset >> 17] |= mask;
467 }
468}
469
470// Clearing the cache is rather slow on ARM Linux, so mark the areas
471// that need to be cleared, and then only clear these areas once.
472static void do_clear_cache(void)
473{
474 int i, j;
475 for (i = 0; i < (1<<(TARGET_SIZE_2-17)); i++)
476 {
477 u_int bitmap = needs_clear_cache[i];
478 if (!bitmap)
479 continue;
480 for (j = 0; j < 32; j++)
481 {
482 u_char *start, *end;
483 if (!(bitmap & (1<<j)))
484 continue;
485
486 start = ndrc->translation_cache + i*131072 + j*4096;
487 end = start + 4095;
488 for (j++; j < 32; j++) {
489 if (!(bitmap & (1<<j)))
490 break;
491 end += 4096;
492 }
493 end_tcache_write(start, end);
494 }
495 needs_clear_cache[i] = 0;
496 }
497}
498
57871462 499//#define DEBUG_CYCLE_COUNT 1
500
b6e87b2b 501#define NO_CYCLE_PENALTY_THR 12
502
26bd3dad 503int cycle_multiplier = CYCLE_MULT_DEFAULT; // 100 for 1.0
a3203cf4 504int cycle_multiplier_override;
32631e6a 505int cycle_multiplier_old;
24058131 506static int cycle_multiplier_active;
4e9dcd7f 507
508static int CLOCK_ADJUST(int x)
509{
24058131 510 int m = cycle_multiplier_active;
511 int s = (x >> 31) | 1;
a3203cf4 512 return (x * m + s * 50) / 100;
4e9dcd7f 513}
514
4919de1e 515static int ds_writes_rjump_rs(int i)
516{
cf95b4f0 517 return dops[i].rs1 != 0 && (dops[i].rs1 == dops[i+1].rt1 || dops[i].rs1 == dops[i+1].rt2);
4919de1e 518}
519
94d23bb9 520static u_int get_page(u_int vaddr)
57871462 521{
0ce47d46 522 u_int page=vaddr&~0xe0000000;
523 if (page < 0x1000000)
524 page &= ~0x0e00000; // RAM mirrors
525 page>>=12;
57871462 526 if(page>2048) page=2048+(page&2047);
94d23bb9 527 return page;
528}
529
d25604ca 530// no virtual mem in PCSX
531static u_int get_vpage(u_int vaddr)
532{
533 return get_page(vaddr);
534}
94d23bb9 535
df4dc2b1 536static struct ht_entry *hash_table_get(u_int vaddr)
537{
538 return &hash_table[((vaddr>>16)^vaddr)&0xFFFF];
539}
540
541static void hash_table_add(struct ht_entry *ht_bin, u_int vaddr, void *tcaddr)
542{
543 ht_bin->vaddr[1] = ht_bin->vaddr[0];
544 ht_bin->tcaddr[1] = ht_bin->tcaddr[0];
545 ht_bin->vaddr[0] = vaddr;
546 ht_bin->tcaddr[0] = tcaddr;
547}
548
398d6924 549static void mark_valid_code(u_int vaddr, u_int len)
550{
551 u_int i, j;
552 vaddr &= 0x1fffffff;
553 for (i = vaddr & ~0xfff; i < vaddr + len; i += 0x1000) {
554 // ram mirrors, but should not hurt bios
555 for (j = 0; j < 0x800000; j += 0x200000) {
556 invalid_code[(i|j) >> 12] =
557 invalid_code[(i|j|0x80000000u) >> 12] =
558 invalid_code[(i|j|0xa0000000u) >> 12] = 0;
559 }
560 }
561 inv_code_start = inv_code_end = ~0;
562}
563
df4dc2b1 564// some messy ari64's code, seems to rely on unsigned 32bit overflow
565static int doesnt_expire_soon(void *tcaddr)
566{
567 u_int diff = (u_int)((u_char *)tcaddr - out) << (32-TARGET_SIZE_2);
568 return diff > (u_int)(0x60000000 + (MAX_OUTPUT_BLOCK_SIZE << (32-TARGET_SIZE_2)));
569}
570
398d6924 571void *ndrc_try_restore_block(u_int vaddr)
572{
ece032e6 573 u_char *source_start = NULL, *source_end = NULL;
574 void *found_stub = NULL, *found_clean = NULL;
575 u_int len, page = get_page(vaddr);
576 const struct ll_entry *head;
577 int ep_count = 0;
398d6924 578
ece032e6 579 stat_inc(stat_restore_tries);
398d6924 580 for (head = jump_dirty[page]; head != NULL; head = head->next)
581 {
582 if (head->vaddr != vaddr)
583 continue;
584 // don't restore blocks which are about to expire from the cache
585 if (!doesnt_expire_soon(head->addr))
586 continue;
ece032e6 587 stat_inc(stat_restore_compares);
398d6924 588 if (!verify_dirty(head->addr))
589 continue;
590
ece032e6 591 found_stub = head->addr;
592 break;
593 }
594 if (!found_stub)
595 return NULL;
596
597 found_clean = get_clean_addr(found_stub);
598 get_bounds(found_stub, &source_start, &source_end);
599 assert(source_start < source_end);
600 len = source_end - source_start;
601 mark_valid_code(vaddr, len);
602
603 // restore all entry points
604 for (head = jump_dirty[page]; head != NULL; head = head->next)
605 {
606 if (head->vaddr < vaddr || head->vaddr >= vaddr + len)
607 continue;
608
609 u_char *start = NULL, *end = NULL;
398d6924 610 get_bounds(head->addr, &start, &end);
ece032e6 611 if (start != source_start || end != source_end)
612 continue;
398d6924 613
614 void *clean_addr = get_clean_addr(head->addr);
ece032e6 615 ll_add_flags(jump_in + page, head->vaddr, head->reg_sv_flags, clean_addr);
398d6924 616
398d6924 617 int in_ht = 0;
ece032e6 618 struct ht_entry *ht_bin = hash_table_get(head->vaddr);
619 if (ht_bin->vaddr[0] == head->vaddr) {
398d6924 620 ht_bin->tcaddr[0] = clean_addr; // Replace existing entry
621 in_ht = 1;
622 }
ece032e6 623 if (ht_bin->vaddr[1] == head->vaddr) {
398d6924 624 ht_bin->tcaddr[1] = clean_addr; // Replace existing entry
625 in_ht = 1;
626 }
627 if (!in_ht)
ece032e6 628 hash_table_add(ht_bin, head->vaddr, clean_addr);
629 ep_count++;
398d6924 630 }
ece032e6 631 inv_debug("INV: Restored %08x %p (%d)\n", vaddr, found_stub, ep_count);
632 stat_inc(stat_bc_restore);
633 return found_clean;
398d6924 634}
635
94d23bb9 636// Get address from virtual address
637// This is called from the recompiled JR/JALR instructions
d1e4ebd9 638void noinline *get_addr(u_int vaddr)
94d23bb9 639{
398d6924 640 u_int page = get_page(vaddr);
57871462 641 struct ll_entry *head;
398d6924 642 void *code;
643
ece032e6 644 stat_inc(stat_jump_in_lookups);
398d6924 645 for (head = jump_in[page]; head != NULL; head = head->next) {
646 if (head->vaddr == vaddr) {
df4dc2b1 647 hash_table_add(hash_table_get(vaddr), vaddr, head->addr);
57871462 648 return head->addr;
649 }
57871462 650 }
398d6924 651 code = ndrc_try_restore_block(vaddr);
652 if (code)
653 return code;
654
655 int r = new_recompile_block(vaddr);
656 if (r == 0)
657 return get_addr(vaddr);
df4dc2b1 658
b4ab351d 659 // generate an address error
57871462 660 Status|=2;
b4ab351d 661 Cause=(vaddr<<31)|(4<<2);
57871462 662 EPC=(vaddr&1)?vaddr-5:vaddr;
663 BadVAddr=(vaddr&~1);
b4ab351d 664 return get_addr_ht(0x80000080);
57871462 665}
666// Look up address in hash table first
667void *get_addr_ht(u_int vaddr)
668{
669 //printf("TRACE: count=%d next=%d (get_addr_ht %x)\n",Count,next_interupt,vaddr);
df4dc2b1 670 const struct ht_entry *ht_bin = hash_table_get(vaddr);
671 if (ht_bin->vaddr[0] == vaddr) return ht_bin->tcaddr[0];
672 if (ht_bin->vaddr[1] == vaddr) return ht_bin->tcaddr[1];
57871462 673 return get_addr(vaddr);
674}
675
6cc8d23c 676static void clear_all_regs(signed char regmap[])
57871462 677{
6cc8d23c 678 memset(regmap, -1, sizeof(regmap[0]) * HOST_REGS);
57871462 679}
680
53358c1d 681// get_reg: get allocated host reg from mips reg
682// returns -1 if no such mips reg was allocated
cdc2da64 683#if defined(__arm__) && defined(HAVE_ARMV6) && HOST_REGS == 13 && EXCLUDE_REG == 11
684
685extern signed char get_reg(const signed char regmap[], signed char r);
686
687#else
688
9de8a0c3 689static signed char get_reg(const signed char regmap[], signed char r)
57871462 690{
691 int hr;
9de8a0c3 692 for (hr = 0; hr < HOST_REGS; hr++) {
693 if (hr == EXCLUDE_REG)
694 continue;
695 if (regmap[hr] == r)
696 return hr;
697 }
698 return -1;
699}
700
cdc2da64 701#endif
702
53358c1d 703// get reg as mask bit (1 << hr)
704static u_int get_regm(const signed char regmap[], signed char r)
705{
706 return (1u << (get_reg(regmap, r) & 31)) & ~(1u << 31);
707}
708
9de8a0c3 709static signed char get_reg_temp(const signed char regmap[])
710{
711 int hr;
712 for (hr = 0; hr < HOST_REGS; hr++) {
713 if (hr == EXCLUDE_REG)
714 continue;
715 if (regmap[hr] == (signed char)-1)
716 return hr;
717 }
57871462 718 return -1;
719}
720
721// Find a register that is available for two consecutive cycles
d1e4ebd9 722static signed char get_reg2(signed char regmap1[], const signed char regmap2[], int r)
57871462 723{
724 int hr;
725 for (hr=0;hr<HOST_REGS;hr++) if(hr!=EXCLUDE_REG&&regmap1[hr]==r&&regmap2[hr]==r) return hr;
726 return -1;
727}
728
53dc27f6 729// reverse reg map: mips -> host
730#define RRMAP_SIZE 64
731static void make_rregs(const signed char regmap[], signed char rrmap[RRMAP_SIZE],
732 u_int *regs_can_change)
733{
734 u_int r, hr, hr_can_change = 0;
735 memset(rrmap, -1, RRMAP_SIZE);
736 for (hr = 0; hr < HOST_REGS; )
737 {
738 r = regmap[hr];
739 rrmap[r & (RRMAP_SIZE - 1)] = hr;
740 // only add mips $1-$31+$lo, others shifted out
741 hr_can_change |= (uint64_t)1 << (hr + ((r - 1) & 32));
742 hr++;
743 if (hr == EXCLUDE_REG)
744 hr++;
745 }
746 hr_can_change |= 1u << (rrmap[33] & 31);
747 hr_can_change |= 1u << (rrmap[CCREG] & 31);
748 hr_can_change &= ~(1u << 31);
749 *regs_can_change = hr_can_change;
750}
751
752// same as get_reg, but takes rrmap
753static signed char get_rreg(signed char rrmap[RRMAP_SIZE], signed char r)
754{
755 assert(0 <= r && r < RRMAP_SIZE);
756 return rrmap[r];
757}
758
9de8a0c3 759static int count_free_regs(const signed char regmap[])
57871462 760{
761 int count=0;
762 int hr;
763 for(hr=0;hr<HOST_REGS;hr++)
764 {
765 if(hr!=EXCLUDE_REG) {
766 if(regmap[hr]<0) count++;
767 }
768 }
769 return count;
770}
771
9de8a0c3 772static void dirty_reg(struct regstat *cur, signed char reg)
57871462 773{
774 int hr;
9de8a0c3 775 if (!reg) return;
776 hr = get_reg(cur->regmap, reg);
777 if (hr >= 0)
778 cur->dirty |= 1<<hr;
57871462 779}
780
40fca85b 781static void set_const(struct regstat *cur, signed char reg, uint32_t value)
57871462 782{
783 int hr;
9de8a0c3 784 if (!reg) return;
785 hr = get_reg(cur->regmap, reg);
786 if (hr >= 0) {
787 cur->isconst |= 1<<hr;
788 current_constmap[hr] = value;
57871462 789 }
790}
791
40fca85b 792static void clear_const(struct regstat *cur, signed char reg)
57871462 793{
794 int hr;
9de8a0c3 795 if (!reg) return;
796 hr = get_reg(cur->regmap, reg);
797 if (hr >= 0)
798 cur->isconst &= ~(1<<hr);
57871462 799}
800
9de8a0c3 801static int is_const(const struct regstat *cur, signed char reg)
57871462 802{
803 int hr;
9de8a0c3 804 if (reg < 0) return 0;
805 if (!reg) return 1;
806 hr = get_reg(cur->regmap, reg);
807 if (hr >= 0)
808 return (cur->isconst>>hr)&1;
57871462 809 return 0;
810}
40fca85b 811
9de8a0c3 812static uint32_t get_const(const struct regstat *cur, signed char reg)
57871462 813{
814 int hr;
9de8a0c3 815 if (!reg) return 0;
816 hr = get_reg(cur->regmap, reg);
817 if (hr >= 0)
818 return current_constmap[hr];
819
820 SysPrintf("Unknown constant in r%d\n", reg);
7c3a5182 821 abort();
57871462 822}
823
824// Least soon needed registers
825// Look at the next ten instructions and see which registers
826// will be used. Try not to reallocate these.
4149788d 827static void lsn(u_char hsn[], int i, int *preferred_reg)
57871462 828{
829 int j;
830 int b=-1;
831 for(j=0;j<9;j++)
832 {
833 if(i+j>=slen) {
834 j=slen-i-1;
835 break;
836 }
fe807a8a 837 if (dops[i+j].is_ujump)
57871462 838 {
839 // Don't go past an unconditonal jump
840 j++;
841 break;
842 }
843 }
844 for(;j>=0;j--)
845 {
cf95b4f0 846 if(dops[i+j].rs1) hsn[dops[i+j].rs1]=j;
847 if(dops[i+j].rs2) hsn[dops[i+j].rs2]=j;
848 if(dops[i+j].rt1) hsn[dops[i+j].rt1]=j;
849 if(dops[i+j].rt2) hsn[dops[i+j].rt2]=j;
850 if(dops[i+j].itype==STORE || dops[i+j].itype==STORELR) {
57871462 851 // Stores can allocate zero
cf95b4f0 852 hsn[dops[i+j].rs1]=j;
853 hsn[dops[i+j].rs2]=j;
57871462 854 }
37387d8b 855 if (ram_offset && (dops[i+j].is_load || dops[i+j].is_store))
856 hsn[ROREG] = j;
57871462 857 // On some architectures stores need invc_ptr
858 #if defined(HOST_IMM8)
37387d8b 859 if (dops[i+j].is_store)
860 hsn[INVCP] = j;
57871462 861 #endif
cf95b4f0 862 if(i+j>=0&&(dops[i+j].itype==UJUMP||dops[i+j].itype==CJUMP||dops[i+j].itype==SJUMP))
57871462 863 {
864 hsn[CCREG]=j;
865 b=j;
866 }
867 }
868 if(b>=0)
869 {
870 if(ba[i+b]>=start && ba[i+b]<(start+slen*4))
871 {
872 // Follow first branch
873 int t=(ba[i+b]-start)>>2;
874 j=7-b;if(t+j>=slen) j=slen-t-1;
875 for(;j>=0;j--)
876 {
cf95b4f0 877 if(dops[t+j].rs1) if(hsn[dops[t+j].rs1]>j+b+2) hsn[dops[t+j].rs1]=j+b+2;
878 if(dops[t+j].rs2) if(hsn[dops[t+j].rs2]>j+b+2) hsn[dops[t+j].rs2]=j+b+2;
879 //if(dops[t+j].rt1) if(hsn[dops[t+j].rt1]>j+b+2) hsn[dops[t+j].rt1]=j+b+2;
880 //if(dops[t+j].rt2) if(hsn[dops[t+j].rt2]>j+b+2) hsn[dops[t+j].rt2]=j+b+2;
57871462 881 }
882 }
883 // TODO: preferred register based on backward branch
884 }
885 // Delay slot should preferably not overwrite branch conditions or cycle count
fe807a8a 886 if (i > 0 && dops[i-1].is_jump) {
cf95b4f0 887 if(dops[i-1].rs1) if(hsn[dops[i-1].rs1]>1) hsn[dops[i-1].rs1]=1;
888 if(dops[i-1].rs2) if(hsn[dops[i-1].rs2]>1) hsn[dops[i-1].rs2]=1;
57871462 889 hsn[CCREG]=1;
890 // ...or hash tables
891 hsn[RHASH]=1;
892 hsn[RHTBL]=1;
893 }
894 // Coprocessor load/store needs FTEMP, even if not declared
37387d8b 895 if(dops[i].itype==C2LS) {
57871462 896 hsn[FTEMP]=0;
897 }
898 // Load L/R also uses FTEMP as a temporary register
cf95b4f0 899 if(dops[i].itype==LOADLR) {
57871462 900 hsn[FTEMP]=0;
901 }
b7918751 902 // Also SWL/SWR/SDL/SDR
cf95b4f0 903 if(dops[i].opcode==0x2a||dops[i].opcode==0x2e||dops[i].opcode==0x2c||dops[i].opcode==0x2d) {
57871462 904 hsn[FTEMP]=0;
905 }
57871462 906 // Don't remove the miniht registers
cf95b4f0 907 if(dops[i].itype==UJUMP||dops[i].itype==RJUMP)
57871462 908 {
909 hsn[RHASH]=0;
910 hsn[RHTBL]=0;
911 }
912}
913
914// We only want to allocate registers if we're going to use them again soon
4149788d 915static int needed_again(int r, int i)
57871462 916{
917 int j;
918 int b=-1;
919 int rn=10;
9f51b4b9 920
fe807a8a 921 if (i > 0 && dops[i-1].is_ujump)
57871462 922 {
923 if(ba[i-1]<start || ba[i-1]>start+slen*4-4)
924 return 0; // Don't need any registers if exiting the block
925 }
926 for(j=0;j<9;j++)
927 {
928 if(i+j>=slen) {
929 j=slen-i-1;
930 break;
931 }
fe807a8a 932 if (dops[i+j].is_ujump)
57871462 933 {
934 // Don't go past an unconditonal jump
935 j++;
936 break;
937 }
cf95b4f0 938 if(dops[i+j].itype==SYSCALL||dops[i+j].itype==HLECALL||dops[i+j].itype==INTCALL||((source[i+j]&0xfc00003f)==0x0d))
57871462 939 {
940 break;
941 }
942 }
943 for(;j>=1;j--)
944 {
cf95b4f0 945 if(dops[i+j].rs1==r) rn=j;
946 if(dops[i+j].rs2==r) rn=j;
57871462 947 if((unneeded_reg[i+j]>>r)&1) rn=10;
cf95b4f0 948 if(i+j>=0&&(dops[i+j].itype==UJUMP||dops[i+j].itype==CJUMP||dops[i+j].itype==SJUMP))
57871462 949 {
950 b=j;
951 }
952 }
b7217e13 953 if(rn<10) return 1;
581335b0 954 (void)b;
57871462 955 return 0;
956}
957
958// Try to match register allocations at the end of a loop with those
959// at the beginning
4149788d 960static int loop_reg(int i, int r, int hr)
57871462 961{
962 int j,k;
963 for(j=0;j<9;j++)
964 {
965 if(i+j>=slen) {
966 j=slen-i-1;
967 break;
968 }
fe807a8a 969 if (dops[i+j].is_ujump)
57871462 970 {
971 // Don't go past an unconditonal jump
972 j++;
973 break;
974 }
975 }
976 k=0;
977 if(i>0){
cf95b4f0 978 if(dops[i-1].itype==UJUMP||dops[i-1].itype==CJUMP||dops[i-1].itype==SJUMP)
57871462 979 k--;
980 }
981 for(;k<j;k++)
982 {
00fa9369 983 assert(r < 64);
984 if((unneeded_reg[i+k]>>r)&1) return hr;
cf95b4f0 985 if(i+k>=0&&(dops[i+k].itype==UJUMP||dops[i+k].itype==CJUMP||dops[i+k].itype==SJUMP))
57871462 986 {
987 if(ba[i+k]>=start && ba[i+k]<(start+i*4))
988 {
989 int t=(ba[i+k]-start)>>2;
990 int reg=get_reg(regs[t].regmap_entry,r);
991 if(reg>=0) return reg;
992 //reg=get_reg(regs[t+1].regmap_entry,r);
993 //if(reg>=0) return reg;
994 }
995 }
996 }
997 return hr;
998}
999
1000
1001// Allocate every register, preserving source/target regs
4149788d 1002static void alloc_all(struct regstat *cur,int i)
57871462 1003{
1004 int hr;
9f51b4b9 1005
57871462 1006 for(hr=0;hr<HOST_REGS;hr++) {
1007 if(hr!=EXCLUDE_REG) {
9de8a0c3 1008 if((cur->regmap[hr]!=dops[i].rs1)&&(cur->regmap[hr]!=dops[i].rs2)&&
1009 (cur->regmap[hr]!=dops[i].rt1)&&(cur->regmap[hr]!=dops[i].rt2))
57871462 1010 {
1011 cur->regmap[hr]=-1;
1012 cur->dirty&=~(1<<hr);
1013 }
1014 // Don't need zeros
9de8a0c3 1015 if(cur->regmap[hr]==0)
57871462 1016 {
1017 cur->regmap[hr]=-1;
1018 cur->dirty&=~(1<<hr);
1019 }
1020 }
1021 }
1022}
1023
d1e4ebd9 1024#ifndef NDEBUG
1025static int host_tempreg_in_use;
1026
1027static void host_tempreg_acquire(void)
1028{
1029 assert(!host_tempreg_in_use);
1030 host_tempreg_in_use = 1;
1031}
1032
1033static void host_tempreg_release(void)
1034{
1035 host_tempreg_in_use = 0;
1036}
1037#else
1038static void host_tempreg_acquire(void) {}
1039static void host_tempreg_release(void) {}
1040#endif
1041
32631e6a 1042#ifdef ASSEM_PRINT
8062d65a 1043extern void gen_interupt();
1044extern void do_insn_cmp();
d1e4ebd9 1045#define FUNCNAME(f) { f, " " #f }
8062d65a 1046static const struct {
d1e4ebd9 1047 void *addr;
8062d65a 1048 const char *name;
1049} function_names[] = {
1050 FUNCNAME(cc_interrupt),
1051 FUNCNAME(gen_interupt),
1052 FUNCNAME(get_addr_ht),
1053 FUNCNAME(get_addr),
1054 FUNCNAME(jump_handler_read8),
1055 FUNCNAME(jump_handler_read16),
1056 FUNCNAME(jump_handler_read32),
1057 FUNCNAME(jump_handler_write8),
1058 FUNCNAME(jump_handler_write16),
1059 FUNCNAME(jump_handler_write32),
1060 FUNCNAME(invalidate_addr),
3968e69e 1061 FUNCNAME(jump_to_new_pc),
d1150cd6 1062 FUNCNAME(jump_break),
1063 FUNCNAME(jump_break_ds),
1064 FUNCNAME(jump_syscall),
1065 FUNCNAME(jump_syscall_ds),
81dbbf4c 1066 FUNCNAME(call_gteStall),
8062d65a 1067 FUNCNAME(new_dyna_leave),
1068 FUNCNAME(pcsx_mtc0),
1069 FUNCNAME(pcsx_mtc0_ds),
32631e6a 1070#ifdef DRC_DBG
8062d65a 1071 FUNCNAME(do_insn_cmp),
32631e6a 1072#endif
3968e69e 1073#ifdef __arm__
1074 FUNCNAME(verify_code),
1075#endif
8062d65a 1076};
1077
d1e4ebd9 1078static const char *func_name(const void *a)
8062d65a 1079{
1080 int i;
1081 for (i = 0; i < sizeof(function_names)/sizeof(function_names[0]); i++)
1082 if (function_names[i].addr == a)
1083 return function_names[i].name;
1084 return "";
1085}
1086#else
1087#define func_name(x) ""
1088#endif
1089
57871462 1090#ifdef __i386__
1091#include "assem_x86.c"
1092#endif
1093#ifdef __x86_64__
1094#include "assem_x64.c"
1095#endif
1096#ifdef __arm__
1097#include "assem_arm.c"
1098#endif
be516ebe 1099#ifdef __aarch64__
1100#include "assem_arm64.c"
1101#endif
57871462 1102
2a014d73 1103static void *get_trampoline(const void *f)
1104{
1105 size_t i;
1106
1107 for (i = 0; i < ARRAY_SIZE(ndrc->tramp.f); i++) {
1108 if (ndrc->tramp.f[i] == f || ndrc->tramp.f[i] == NULL)
1109 break;
1110 }
1111 if (i == ARRAY_SIZE(ndrc->tramp.f)) {
1112 SysPrintf("trampoline table is full, last func %p\n", f);
1113 abort();
1114 }
1115 if (ndrc->tramp.f[i] == NULL) {
1116 start_tcache_write(&ndrc->tramp.f[i], &ndrc->tramp.f[i + 1]);
1117 ndrc->tramp.f[i] = f;
1118 end_tcache_write(&ndrc->tramp.f[i], &ndrc->tramp.f[i + 1]);
1119 }
1120 return &ndrc->tramp.ops[i];
1121}
1122
1123static void emit_far_jump(const void *f)
1124{
1125 if (can_jump_or_call(f)) {
1126 emit_jmp(f);
1127 return;
1128 }
1129
1130 f = get_trampoline(f);
1131 emit_jmp(f);
1132}
1133
1134static void emit_far_call(const void *f)
1135{
1136 if (can_jump_or_call(f)) {
1137 emit_call(f);
1138 return;
1139 }
1140
1141 f = get_trampoline(f);
1142 emit_call(f);
1143}
1144
57871462 1145// Add virtual address mapping to linked list
4149788d 1146static void ll_add(struct ll_entry **head,int vaddr,void *addr)
57871462 1147{
1148 struct ll_entry *new_entry;
1149 new_entry=malloc(sizeof(struct ll_entry));
1150 assert(new_entry!=NULL);
1151 new_entry->vaddr=vaddr;
de5a60c3 1152 new_entry->reg_sv_flags=0;
57871462 1153 new_entry->addr=addr;
1154 new_entry->next=*head;
1155 *head=new_entry;
1156}
1157
4149788d 1158static void ll_add_flags(struct ll_entry **head,int vaddr,u_int reg_sv_flags,void *addr)
57871462 1159{
7139f3c8 1160 ll_add(head,vaddr,addr);
de5a60c3 1161 (*head)->reg_sv_flags=reg_sv_flags;
57871462 1162}
1163
1164// Check if an address is already compiled
1165// but don't return addresses which are about to expire from the cache
4149788d 1166static void *check_addr(u_int vaddr)
57871462 1167{
df4dc2b1 1168 struct ht_entry *ht_bin = hash_table_get(vaddr);
1169 size_t i;
b14b6a8f 1170 for (i = 0; i < ARRAY_SIZE(ht_bin->vaddr); i++) {
df4dc2b1 1171 if (ht_bin->vaddr[i] == vaddr)
1172 if (doesnt_expire_soon((u_char *)ht_bin->tcaddr[i] - MAX_OUTPUT_BLOCK_SIZE))
1173 if (isclean(ht_bin->tcaddr[i]))
1174 return ht_bin->tcaddr[i];
57871462 1175 }
94d23bb9 1176 u_int page=get_page(vaddr);
57871462 1177 struct ll_entry *head;
1178 head=jump_in[page];
df4dc2b1 1179 while (head != NULL) {
1180 if (head->vaddr == vaddr) {
1181 if (doesnt_expire_soon(head->addr)) {
57871462 1182 // Update existing entry with current address
df4dc2b1 1183 if (ht_bin->vaddr[0] == vaddr) {
1184 ht_bin->tcaddr[0] = head->addr;
57871462 1185 return head->addr;
1186 }
df4dc2b1 1187 if (ht_bin->vaddr[1] == vaddr) {
1188 ht_bin->tcaddr[1] = head->addr;
57871462 1189 return head->addr;
1190 }
1191 // Insert into hash table with low priority.
1192 // Don't evict existing entries, as they are probably
1193 // addresses that are being accessed frequently.
df4dc2b1 1194 if (ht_bin->vaddr[0] == -1) {
1195 ht_bin->vaddr[0] = vaddr;
1196 ht_bin->tcaddr[0] = head->addr;
1197 }
1198 else if (ht_bin->vaddr[1] == -1) {
1199 ht_bin->vaddr[1] = vaddr;
1200 ht_bin->tcaddr[1] = head->addr;
57871462 1201 }
1202 return head->addr;
1203 }
1204 }
1205 head=head->next;
1206 }
1207 return 0;
1208}
1209
ece032e6 1210static void remove_hash(int vaddr)
57871462 1211{
1212 //printf("remove hash: %x\n",vaddr);
df4dc2b1 1213 struct ht_entry *ht_bin = hash_table_get(vaddr);
1214 if (ht_bin->vaddr[1] == vaddr) {
1215 ht_bin->vaddr[1] = -1;
1216 ht_bin->tcaddr[1] = NULL;
57871462 1217 }
df4dc2b1 1218 if (ht_bin->vaddr[0] == vaddr) {
1219 ht_bin->vaddr[0] = ht_bin->vaddr[1];
1220 ht_bin->tcaddr[0] = ht_bin->tcaddr[1];
1221 ht_bin->vaddr[1] = -1;
1222 ht_bin->tcaddr[1] = NULL;
57871462 1223 }
1224}
1225
943f42f3 1226static void ll_remove_matching_addrs(struct ll_entry **head,
1227 uintptr_t base_offs_s, int shift)
57871462 1228{
1229 struct ll_entry *next;
1230 while(*head) {
943f42f3 1231 uintptr_t o1 = (u_char *)(*head)->addr - ndrc->translation_cache;
1232 uintptr_t o2 = o1 - MAX_OUTPUT_BLOCK_SIZE;
1233 if ((o1 >> shift) == base_offs_s || (o2 >> shift) == base_offs_s)
57871462 1234 {
643aeae3 1235 inv_debug("EXP: Remove pointer to %p (%x)\n",(*head)->addr,(*head)->vaddr);
57871462 1236 remove_hash((*head)->vaddr);
1237 next=(*head)->next;
1238 free(*head);
1239 *head=next;
1240 }
1241 else
1242 {
1243 head=&((*head)->next);
1244 }
1245 }
1246}
1247
1248// Remove all entries from linked list
4149788d 1249static void ll_clear(struct ll_entry **head)
57871462 1250{
1251 struct ll_entry *cur;
1252 struct ll_entry *next;
581335b0 1253 if((cur=*head)) {
57871462 1254 *head=0;
1255 while(cur) {
1256 next=cur->next;
1257 free(cur);
1258 cur=next;
1259 }
1260 }
1261}
1262
1263// Dereference the pointers and remove if it matches
943f42f3 1264static void ll_kill_pointers(struct ll_entry *head,
1265 uintptr_t base_offs_s, int shift)
57871462 1266{
1267 while(head) {
943f42f3 1268 u_char *ptr = get_pointer(head->addr);
1269 uintptr_t o1 = ptr - ndrc->translation_cache;
1270 uintptr_t o2 = o1 - MAX_OUTPUT_BLOCK_SIZE;
1271 inv_debug("EXP: Lookup pointer to %p at %p (%x)\n",ptr,head->addr,head->vaddr);
1272 if ((o1 >> shift) == base_offs_s || (o2 >> shift) == base_offs_s)
57871462 1273 {
643aeae3 1274 inv_debug("EXP: Kill pointer at %p (%x)\n",head->addr,head->vaddr);
d148d265 1275 void *host_addr=find_extjump_insn(head->addr);
919981d0 1276 mark_clear_cache(host_addr);
df4dc2b1 1277 set_jump_target(host_addr, head->addr);
57871462 1278 }
1279 head=head->next;
1280 }
1281}
1282
1283// This is called when we write to a compiled block (see do_invstub)
d1e4ebd9 1284static void invalidate_page(u_int page)
57871462 1285{
57871462 1286 struct ll_entry *head;
1287 struct ll_entry *next;
1288 head=jump_in[page];
ece032e6 1289 if (head) stat_inc(stat_inv_hits);
57871462 1290 jump_in[page]=0;
1291 while(head!=NULL) {
1292 inv_debug("INVALIDATE: %x\n",head->vaddr);
1293 remove_hash(head->vaddr);
1294 next=head->next;
1295 free(head);
1296 head=next;
1297 }
1298 head=jump_out[page];
1299 jump_out[page]=0;
1300 while(head!=NULL) {
643aeae3 1301 inv_debug("INVALIDATE: kill pointer to %x (%p)\n",head->vaddr,head->addr);
d148d265 1302 void *host_addr=find_extjump_insn(head->addr);
919981d0 1303 mark_clear_cache(host_addr);
3d680478 1304 set_jump_target(host_addr, head->addr); // point back to dyna_linker
57871462 1305 next=head->next;
1306 free(head);
1307 head=next;
1308 }
57871462 1309}
9be4ba64 1310
1311static void invalidate_block_range(u_int block, u_int first, u_int last)
57871462 1312{
94d23bb9 1313 u_int page=get_page(block<<12);
57871462 1314 //printf("first=%d last=%d\n",first,last);
f76eeef9 1315 invalidate_page(page);
57871462 1316 assert(first+5>page); // NB: this assumes MAXBLOCK<=4096 (4 pages)
1317 assert(last<page+5);
1318 // Invalidate the adjacent pages if a block crosses a 4K boundary
1319 while(first<page) {
1320 invalidate_page(first);
1321 first++;
1322 }
1323 for(first=page+1;first<last;first++) {
1324 invalidate_page(first);
1325 }
919981d0 1326 do_clear_cache();
9f51b4b9 1327
57871462 1328 // Don't trap writes
1329 invalid_code[block]=1;
f76eeef9 1330
57871462 1331 #ifdef USE_MINI_HT
1332 memset(mini_ht,-1,sizeof(mini_ht));
1333 #endif
1334}
9be4ba64 1335
1336void invalidate_block(u_int block)
1337{
1338 u_int page=get_page(block<<12);
1339 u_int vpage=get_vpage(block<<12);
1340 inv_debug("INVALIDATE: %x (%d)\n",block<<12,page);
1341 //inv_debug("invalid_code[block]=%d\n",invalid_code[block]);
1342 u_int first,last;
1343 first=last=page;
1344 struct ll_entry *head;
1345 head=jump_dirty[vpage];
1346 //printf("page=%d vpage=%d\n",page,vpage);
1347 while(head!=NULL) {
9be4ba64 1348 if(vpage>2047||(head->vaddr>>12)==block) { // Ignore vaddr hash collision
01d26796 1349 u_char *start, *end;
1350 get_bounds(head->addr, &start, &end);
1351 //printf("start: %p end: %p\n", start, end);
1352 if (page < 2048 && start >= rdram && end < rdram+RAM_SIZE) {
1353 if (((start-rdram)>>12) <= page && ((end-1-rdram)>>12) >= page) {
1354 if ((((start-rdram)>>12)&2047) < first) first = ((start-rdram)>>12)&2047;
1355 if ((((end-1-rdram)>>12)&2047) > last) last = ((end-1-rdram)>>12)&2047;
9be4ba64 1356 }
1357 }
9be4ba64 1358 }
1359 head=head->next;
1360 }
1361 invalidate_block_range(block,first,last);
1362}
1363
57871462 1364void invalidate_addr(u_int addr)
1365{
9be4ba64 1366 //static int rhits;
1367 // this check is done by the caller
1368 //if (inv_code_start<=addr&&addr<=inv_code_end) { rhits++; return; }
ece032e6 1369 stat_inc(stat_inv_addr_calls);
d25604ca 1370 u_int page=get_vpage(addr);
9be4ba64 1371 if(page<2048) { // RAM
1372 struct ll_entry *head;
1373 u_int addr_min=~0, addr_max=0;
4a35de07 1374 u_int mask=RAM_SIZE-1;
1375 u_int addr_main=0x80000000|(addr&mask);
9be4ba64 1376 int pg1;
4a35de07 1377 inv_code_start=addr_main&~0xfff;
1378 inv_code_end=addr_main|0xfff;
9be4ba64 1379 pg1=page;
1380 if (pg1>0) {
1381 // must check previous page too because of spans..
1382 pg1--;
1383 inv_code_start-=0x1000;
1384 }
1385 for(;pg1<=page;pg1++) {
1386 for(head=jump_dirty[pg1];head!=NULL;head=head->next) {
01d26796 1387 u_char *start_h, *end_h;
1388 u_int start, end;
1389 get_bounds(head->addr, &start_h, &end_h);
1390 start = (uintptr_t)start_h - ram_offset;
1391 end = (uintptr_t)end_h - ram_offset;
4a35de07 1392 if(start<=addr_main&&addr_main<end) {
9be4ba64 1393 if(start<addr_min) addr_min=start;
1394 if(end>addr_max) addr_max=end;
1395 }
4a35de07 1396 else if(addr_main<start) {
9be4ba64 1397 if(start<inv_code_end)
1398 inv_code_end=start-1;
1399 }
1400 else {
1401 if(end>inv_code_start)
1402 inv_code_start=end;
1403 }
1404 }
1405 }
1406 if (addr_min!=~0) {
1407 inv_debug("INV ADDR: %08x hit %08x-%08x\n", addr, addr_min, addr_max);
1408 inv_code_start=inv_code_end=~0;
1409 invalidate_block_range(addr>>12,(addr_min&mask)>>12,(addr_max&mask)>>12);
1410 return;
1411 }
1412 else {
4a35de07 1413 inv_code_start=(addr&~mask)|(inv_code_start&mask);
1414 inv_code_end=(addr&~mask)|(inv_code_end&mask);
d25604ca 1415 inv_debug("INV ADDR: %08x miss, inv %08x-%08x, sk %d\n", addr, inv_code_start, inv_code_end, 0);
9be4ba64 1416 return;
d25604ca 1417 }
9be4ba64 1418 }
57871462 1419 invalidate_block(addr>>12);
1420}
9be4ba64 1421
dd3a91a1 1422// This is called when loading a save state.
1423// Anything could have changed, so invalidate everything.
919981d0 1424void invalidate_all_pages(void)
57871462 1425{
581335b0 1426 u_int page;
57871462 1427 for(page=0;page<4096;page++)
1428 invalidate_page(page);
57871462 1429 #ifdef USE_MINI_HT
1430 memset(mini_ht,-1,sizeof(mini_ht));
1431 #endif
919981d0 1432 do_clear_cache();
57871462 1433}
1434
d1e4ebd9 1435static void do_invstub(int n)
1436{
1437 literal_pool(20);
1438 u_int reglist=stubs[n].a;
1439 set_jump_target(stubs[n].addr, out);
1440 save_regs(reglist);
1441 if(stubs[n].b!=0) emit_mov(stubs[n].b,0);
2a014d73 1442 emit_far_call(invalidate_addr);
d1e4ebd9 1443 restore_regs(reglist);
1444 emit_jmp(stubs[n].retaddr); // return address
1445}
1446
57871462 1447// Add an entry to jump_out after making a link
d1e4ebd9 1448// src should point to code by emit_extjump2()
3d680478 1449void add_jump_out(u_int vaddr,void *src)
57871462 1450{
94d23bb9 1451 u_int page=get_page(vaddr);
3d680478 1452 inv_debug("add_jump_out: %p -> %x (%d)\n",src,vaddr,page);
d1e4ebd9 1453 check_extjump2(src);
57871462 1454 ll_add(jump_out+page,vaddr,src);
3d680478 1455 //inv_debug("add_jump_out: to %p\n",get_pointer(src));
57871462 1456}
1457
8062d65a 1458/* Register allocation */
1459
1460// Note: registers are allocated clean (unmodified state)
1461// if you intend to modify the register, you must call dirty_reg().
1462static void alloc_reg(struct regstat *cur,int i,signed char reg)
1463{
1464 int r,hr;
b7ec323c 1465 int preferred_reg = PREFERRED_REG_FIRST
1466 + reg % (PREFERRED_REG_LAST - PREFERRED_REG_FIRST + 1);
1467 if (reg == CCREG) preferred_reg = HOST_CCREG;
1468 if (reg == PTEMP || reg == FTEMP) preferred_reg = 12;
1469 assert(PREFERRED_REG_FIRST != EXCLUDE_REG && EXCLUDE_REG != HOST_REGS);
53358c1d 1470 assert(reg >= 0);
8062d65a 1471
1472 // Don't allocate unused registers
1473 if((cur->u>>reg)&1) return;
1474
1475 // see if it's already allocated
53358c1d 1476 if (get_reg(cur->regmap, reg) >= 0)
1477 return;
8062d65a 1478
1479 // Keep the same mapping if the register was already allocated in a loop
1480 preferred_reg = loop_reg(i,reg,preferred_reg);
1481
1482 // Try to allocate the preferred register
1483 if(cur->regmap[preferred_reg]==-1) {
1484 cur->regmap[preferred_reg]=reg;
1485 cur->dirty&=~(1<<preferred_reg);
1486 cur->isconst&=~(1<<preferred_reg);
1487 return;
1488 }
1489 r=cur->regmap[preferred_reg];
1490 assert(r < 64);
1491 if((cur->u>>r)&1) {
1492 cur->regmap[preferred_reg]=reg;
1493 cur->dirty&=~(1<<preferred_reg);
1494 cur->isconst&=~(1<<preferred_reg);
1495 return;
1496 }
1497
1498 // Clear any unneeded registers
1499 // We try to keep the mapping consistent, if possible, because it
1500 // makes branches easier (especially loops). So we try to allocate
1501 // first (see above) before removing old mappings. If this is not
1502 // possible then go ahead and clear out the registers that are no
1503 // longer needed.
1504 for(hr=0;hr<HOST_REGS;hr++)
1505 {
1506 r=cur->regmap[hr];
1507 if(r>=0) {
1508 assert(r < 64);
1509 if((cur->u>>r)&1) {cur->regmap[hr]=-1;break;}
1510 }
1511 }
b7ec323c 1512
8062d65a 1513 // Try to allocate any available register, but prefer
1514 // registers that have not been used recently.
b7ec323c 1515 if (i > 0) {
1516 for (hr = PREFERRED_REG_FIRST; ; ) {
1517 if (cur->regmap[hr] < 0) {
1518 int oldreg = regs[i-1].regmap[hr];
1519 if (oldreg < 0 || (oldreg != dops[i-1].rs1 && oldreg != dops[i-1].rs2
1520 && oldreg != dops[i-1].rt1 && oldreg != dops[i-1].rt2))
1521 {
8062d65a 1522 cur->regmap[hr]=reg;
1523 cur->dirty&=~(1<<hr);
1524 cur->isconst&=~(1<<hr);
1525 return;
1526 }
1527 }
b7ec323c 1528 hr++;
1529 if (hr == EXCLUDE_REG)
1530 hr++;
1531 if (hr == HOST_REGS)
1532 hr = 0;
1533 if (hr == PREFERRED_REG_FIRST)
1534 break;
8062d65a 1535 }
1536 }
b7ec323c 1537
8062d65a 1538 // Try to allocate any available register
b7ec323c 1539 for (hr = PREFERRED_REG_FIRST; ; ) {
1540 if (cur->regmap[hr] < 0) {
8062d65a 1541 cur->regmap[hr]=reg;
1542 cur->dirty&=~(1<<hr);
1543 cur->isconst&=~(1<<hr);
1544 return;
1545 }
b7ec323c 1546 hr++;
1547 if (hr == EXCLUDE_REG)
1548 hr++;
1549 if (hr == HOST_REGS)
1550 hr = 0;
1551 if (hr == PREFERRED_REG_FIRST)
1552 break;
8062d65a 1553 }
1554
1555 // Ok, now we have to evict someone
1556 // Pick a register we hopefully won't need soon
1557 u_char hsn[MAXREG+1];
1558 memset(hsn,10,sizeof(hsn));
1559 int j;
1560 lsn(hsn,i,&preferred_reg);
1561 //printf("eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",cur->regmap[0],cur->regmap[1],cur->regmap[2],cur->regmap[3],cur->regmap[5],cur->regmap[6],cur->regmap[7]);
1562 //printf("hsn(%x): %d %d %d %d %d %d %d\n",start+i*4,hsn[cur->regmap[0]&63],hsn[cur->regmap[1]&63],hsn[cur->regmap[2]&63],hsn[cur->regmap[3]&63],hsn[cur->regmap[5]&63],hsn[cur->regmap[6]&63],hsn[cur->regmap[7]&63]);
1563 if(i>0) {
1564 // Don't evict the cycle count at entry points, otherwise the entry
1565 // stub will have to write it.
cf95b4f0 1566 if(dops[i].bt&&hsn[CCREG]>2) hsn[CCREG]=2;
fe807a8a 1567 if (i>1 && hsn[CCREG] > 2 && dops[i-2].is_jump) hsn[CCREG]=2;
8062d65a 1568 for(j=10;j>=3;j--)
1569 {
1570 // Alloc preferred register if available
1571 if(hsn[r=cur->regmap[preferred_reg]&63]==j) {
1572 for(hr=0;hr<HOST_REGS;hr++) {
1573 // Evict both parts of a 64-bit register
9de8a0c3 1574 if(cur->regmap[hr]==r) {
8062d65a 1575 cur->regmap[hr]=-1;
1576 cur->dirty&=~(1<<hr);
1577 cur->isconst&=~(1<<hr);
1578 }
1579 }
1580 cur->regmap[preferred_reg]=reg;
1581 return;
1582 }
1583 for(r=1;r<=MAXREG;r++)
1584 {
cf95b4f0 1585 if(hsn[r]==j&&r!=dops[i-1].rs1&&r!=dops[i-1].rs2&&r!=dops[i-1].rt1&&r!=dops[i-1].rt2) {
8062d65a 1586 for(hr=0;hr<HOST_REGS;hr++) {
1587 if(hr!=HOST_CCREG||j<hsn[CCREG]) {
1588 if(cur->regmap[hr]==r) {
1589 cur->regmap[hr]=reg;
1590 cur->dirty&=~(1<<hr);
1591 cur->isconst&=~(1<<hr);
1592 return;
1593 }
1594 }
1595 }
1596 }
1597 }
1598 }
1599 }
1600 for(j=10;j>=0;j--)
1601 {
1602 for(r=1;r<=MAXREG;r++)
1603 {
1604 if(hsn[r]==j) {
8062d65a 1605 for(hr=0;hr<HOST_REGS;hr++) {
1606 if(cur->regmap[hr]==r) {
1607 cur->regmap[hr]=reg;
1608 cur->dirty&=~(1<<hr);
1609 cur->isconst&=~(1<<hr);
1610 return;
1611 }
1612 }
1613 }
1614 }
1615 }
7c3a5182 1616 SysPrintf("This shouldn't happen (alloc_reg)");abort();
8062d65a 1617}
1618
1619// Allocate a temporary register. This is done without regard to
1620// dirty status or whether the register we request is on the unneeded list
1621// Note: This will only allocate one register, even if called multiple times
1622static void alloc_reg_temp(struct regstat *cur,int i,signed char reg)
1623{
1624 int r,hr;
1625 int preferred_reg = -1;
1626
1627 // see if it's already allocated
1628 for(hr=0;hr<HOST_REGS;hr++)
1629 {
1630 if(hr!=EXCLUDE_REG&&cur->regmap[hr]==reg) return;
1631 }
1632
1633 // Try to allocate any available register
1634 for(hr=HOST_REGS-1;hr>=0;hr--) {
1635 if(hr!=EXCLUDE_REG&&cur->regmap[hr]==-1) {
1636 cur->regmap[hr]=reg;
1637 cur->dirty&=~(1<<hr);
1638 cur->isconst&=~(1<<hr);
1639 return;
1640 }
1641 }
1642
1643 // Find an unneeded register
1644 for(hr=HOST_REGS-1;hr>=0;hr--)
1645 {
1646 r=cur->regmap[hr];
1647 if(r>=0) {
1648 assert(r < 64);
1649 if((cur->u>>r)&1) {
1650 if(i==0||((unneeded_reg[i-1]>>r)&1)) {
1651 cur->regmap[hr]=reg;
1652 cur->dirty&=~(1<<hr);
1653 cur->isconst&=~(1<<hr);
1654 return;
1655 }
1656 }
1657 }
1658 }
1659
1660 // Ok, now we have to evict someone
1661 // Pick a register we hopefully won't need soon
1662 // TODO: we might want to follow unconditional jumps here
1663 // TODO: get rid of dupe code and make this into a function
1664 u_char hsn[MAXREG+1];
1665 memset(hsn,10,sizeof(hsn));
1666 int j;
1667 lsn(hsn,i,&preferred_reg);
1668 //printf("hsn: %d %d %d %d %d %d %d\n",hsn[cur->regmap[0]&63],hsn[cur->regmap[1]&63],hsn[cur->regmap[2]&63],hsn[cur->regmap[3]&63],hsn[cur->regmap[5]&63],hsn[cur->regmap[6]&63],hsn[cur->regmap[7]&63]);
1669 if(i>0) {
1670 // Don't evict the cycle count at entry points, otherwise the entry
1671 // stub will have to write it.
cf95b4f0 1672 if(dops[i].bt&&hsn[CCREG]>2) hsn[CCREG]=2;
fe807a8a 1673 if (i>1 && hsn[CCREG] > 2 && dops[i-2].is_jump) hsn[CCREG]=2;
8062d65a 1674 for(j=10;j>=3;j--)
1675 {
1676 for(r=1;r<=MAXREG;r++)
1677 {
cf95b4f0 1678 if(hsn[r]==j&&r!=dops[i-1].rs1&&r!=dops[i-1].rs2&&r!=dops[i-1].rt1&&r!=dops[i-1].rt2) {
8062d65a 1679 for(hr=0;hr<HOST_REGS;hr++) {
1680 if(hr!=HOST_CCREG||hsn[CCREG]>2) {
1681 if(cur->regmap[hr]==r) {
1682 cur->regmap[hr]=reg;
1683 cur->dirty&=~(1<<hr);
1684 cur->isconst&=~(1<<hr);
1685 return;
1686 }
1687 }
1688 }
1689 }
1690 }
1691 }
1692 }
1693 for(j=10;j>=0;j--)
1694 {
1695 for(r=1;r<=MAXREG;r++)
1696 {
1697 if(hsn[r]==j) {
8062d65a 1698 for(hr=0;hr<HOST_REGS;hr++) {
1699 if(cur->regmap[hr]==r) {
1700 cur->regmap[hr]=reg;
1701 cur->dirty&=~(1<<hr);
1702 cur->isconst&=~(1<<hr);
1703 return;
1704 }
1705 }
1706 }
1707 }
1708 }
7c3a5182 1709 SysPrintf("This shouldn't happen");abort();
8062d65a 1710}
1711
ad49de89 1712static void mov_alloc(struct regstat *current,int i)
57871462 1713{
cf95b4f0 1714 if (dops[i].rs1 == HIREG || dops[i].rs1 == LOREG) {
9a3ccfeb 1715 alloc_cc(current,i); // for stalls
1716 dirty_reg(current,CCREG);
32631e6a 1717 }
1718
57871462 1719 // Note: Don't need to actually alloc the source registers
cf95b4f0 1720 //alloc_reg(current,i,dops[i].rs1);
1721 alloc_reg(current,i,dops[i].rt1);
ad49de89 1722
cf95b4f0 1723 clear_const(current,dops[i].rs1);
1724 clear_const(current,dops[i].rt1);
1725 dirty_reg(current,dops[i].rt1);
57871462 1726}
1727
ad49de89 1728static void shiftimm_alloc(struct regstat *current,int i)
57871462 1729{
cf95b4f0 1730 if(dops[i].opcode2<=0x3) // SLL/SRL/SRA
57871462 1731 {
cf95b4f0 1732 if(dops[i].rt1) {
1733 if(dops[i].rs1&&needed_again(dops[i].rs1,i)) alloc_reg(current,i,dops[i].rs1);
53dc27f6 1734 else dops[i].use_lt1=!!dops[i].rs1;
cf95b4f0 1735 alloc_reg(current,i,dops[i].rt1);
1736 dirty_reg(current,dops[i].rt1);
1737 if(is_const(current,dops[i].rs1)) {
1738 int v=get_const(current,dops[i].rs1);
1739 if(dops[i].opcode2==0x00) set_const(current,dops[i].rt1,v<<imm[i]);
1740 if(dops[i].opcode2==0x02) set_const(current,dops[i].rt1,(u_int)v>>imm[i]);
1741 if(dops[i].opcode2==0x03) set_const(current,dops[i].rt1,v>>imm[i]);
dc49e339 1742 }
cf95b4f0 1743 else clear_const(current,dops[i].rt1);
57871462 1744 }
1745 }
dc49e339 1746 else
1747 {
cf95b4f0 1748 clear_const(current,dops[i].rs1);
1749 clear_const(current,dops[i].rt1);
dc49e339 1750 }
1751
cf95b4f0 1752 if(dops[i].opcode2>=0x38&&dops[i].opcode2<=0x3b) // DSLL/DSRL/DSRA
57871462 1753 {
9c45ca93 1754 assert(0);
57871462 1755 }
cf95b4f0 1756 if(dops[i].opcode2==0x3c) // DSLL32
57871462 1757 {
9c45ca93 1758 assert(0);
57871462 1759 }
cf95b4f0 1760 if(dops[i].opcode2==0x3e) // DSRL32
57871462 1761 {
9c45ca93 1762 assert(0);
57871462 1763 }
cf95b4f0 1764 if(dops[i].opcode2==0x3f) // DSRA32
57871462 1765 {
9c45ca93 1766 assert(0);
57871462 1767 }
1768}
1769
ad49de89 1770static void shift_alloc(struct regstat *current,int i)
57871462 1771{
cf95b4f0 1772 if(dops[i].rt1) {
1773 if(dops[i].opcode2<=0x07) // SLLV/SRLV/SRAV
57871462 1774 {
cf95b4f0 1775 if(dops[i].rs1) alloc_reg(current,i,dops[i].rs1);
1776 if(dops[i].rs2) alloc_reg(current,i,dops[i].rs2);
1777 alloc_reg(current,i,dops[i].rt1);
1778 if(dops[i].rt1==dops[i].rs2) {
e1190b87 1779 alloc_reg_temp(current,i,-1);
1780 minimum_free_regs[i]=1;
1781 }
57871462 1782 } else { // DSLLV/DSRLV/DSRAV
00fa9369 1783 assert(0);
57871462 1784 }
cf95b4f0 1785 clear_const(current,dops[i].rs1);
1786 clear_const(current,dops[i].rs2);
1787 clear_const(current,dops[i].rt1);
1788 dirty_reg(current,dops[i].rt1);
57871462 1789 }
1790}
1791
ad49de89 1792static void alu_alloc(struct regstat *current,int i)
57871462 1793{
cf95b4f0 1794 if(dops[i].opcode2>=0x20&&dops[i].opcode2<=0x23) { // ADD/ADDU/SUB/SUBU
1795 if(dops[i].rt1) {
1796 if(dops[i].rs1&&dops[i].rs2) {
1797 alloc_reg(current,i,dops[i].rs1);
1798 alloc_reg(current,i,dops[i].rs2);
57871462 1799 }
1800 else {
cf95b4f0 1801 if(dops[i].rs1&&needed_again(dops[i].rs1,i)) alloc_reg(current,i,dops[i].rs1);
1802 if(dops[i].rs2&&needed_again(dops[i].rs2,i)) alloc_reg(current,i,dops[i].rs2);
57871462 1803 }
cf95b4f0 1804 alloc_reg(current,i,dops[i].rt1);
57871462 1805 }
57871462 1806 }
cf95b4f0 1807 if(dops[i].opcode2==0x2a||dops[i].opcode2==0x2b) { // SLT/SLTU
1808 if(dops[i].rt1) {
1809 alloc_reg(current,i,dops[i].rs1);
1810 alloc_reg(current,i,dops[i].rs2);
1811 alloc_reg(current,i,dops[i].rt1);
57871462 1812 }
57871462 1813 }
cf95b4f0 1814 if(dops[i].opcode2>=0x24&&dops[i].opcode2<=0x27) { // AND/OR/XOR/NOR
1815 if(dops[i].rt1) {
1816 if(dops[i].rs1&&dops[i].rs2) {
1817 alloc_reg(current,i,dops[i].rs1);
1818 alloc_reg(current,i,dops[i].rs2);
57871462 1819 }
1820 else
1821 {
cf95b4f0 1822 if(dops[i].rs1&&needed_again(dops[i].rs1,i)) alloc_reg(current,i,dops[i].rs1);
1823 if(dops[i].rs2&&needed_again(dops[i].rs2,i)) alloc_reg(current,i,dops[i].rs2);
57871462 1824 }
cf95b4f0 1825 alloc_reg(current,i,dops[i].rt1);
57871462 1826 }
1827 }
cf95b4f0 1828 if(dops[i].opcode2>=0x2c&&dops[i].opcode2<=0x2f) { // DADD/DADDU/DSUB/DSUBU
00fa9369 1829 assert(0);
57871462 1830 }
cf95b4f0 1831 clear_const(current,dops[i].rs1);
1832 clear_const(current,dops[i].rs2);
1833 clear_const(current,dops[i].rt1);
1834 dirty_reg(current,dops[i].rt1);
57871462 1835}
1836
ad49de89 1837static void imm16_alloc(struct regstat *current,int i)
57871462 1838{
cf95b4f0 1839 if(dops[i].rs1&&needed_again(dops[i].rs1,i)) alloc_reg(current,i,dops[i].rs1);
53dc27f6 1840 else dops[i].use_lt1=!!dops[i].rs1;
cf95b4f0 1841 if(dops[i].rt1) alloc_reg(current,i,dops[i].rt1);
1842 if(dops[i].opcode==0x18||dops[i].opcode==0x19) { // DADDI/DADDIU
00fa9369 1843 assert(0);
57871462 1844 }
cf95b4f0 1845 else if(dops[i].opcode==0x0a||dops[i].opcode==0x0b) { // SLTI/SLTIU
1846 clear_const(current,dops[i].rs1);
1847 clear_const(current,dops[i].rt1);
57871462 1848 }
cf95b4f0 1849 else if(dops[i].opcode>=0x0c&&dops[i].opcode<=0x0e) { // ANDI/ORI/XORI
1850 if(is_const(current,dops[i].rs1)) {
1851 int v=get_const(current,dops[i].rs1);
1852 if(dops[i].opcode==0x0c) set_const(current,dops[i].rt1,v&imm[i]);
1853 if(dops[i].opcode==0x0d) set_const(current,dops[i].rt1,v|imm[i]);
1854 if(dops[i].opcode==0x0e) set_const(current,dops[i].rt1,v^imm[i]);
57871462 1855 }
cf95b4f0 1856 else clear_const(current,dops[i].rt1);
57871462 1857 }
cf95b4f0 1858 else if(dops[i].opcode==0x08||dops[i].opcode==0x09) { // ADDI/ADDIU
1859 if(is_const(current,dops[i].rs1)) {
1860 int v=get_const(current,dops[i].rs1);
1861 set_const(current,dops[i].rt1,v+imm[i]);
57871462 1862 }
cf95b4f0 1863 else clear_const(current,dops[i].rt1);
57871462 1864 }
1865 else {
cf95b4f0 1866 set_const(current,dops[i].rt1,imm[i]<<16); // LUI
57871462 1867 }
cf95b4f0 1868 dirty_reg(current,dops[i].rt1);
57871462 1869}
1870
ad49de89 1871static void load_alloc(struct regstat *current,int i)
57871462 1872{
cf95b4f0 1873 clear_const(current,dops[i].rt1);
1874 //if(dops[i].rs1!=dops[i].rt1&&needed_again(dops[i].rs1,i)) clear_const(current,dops[i].rs1); // Does this help or hurt?
1875 if(!dops[i].rs1) current->u&=~1LL; // Allow allocating r0 if it's the source register
37387d8b 1876 if (needed_again(dops[i].rs1, i))
1877 alloc_reg(current, i, dops[i].rs1);
1878 if (ram_offset)
1879 alloc_reg(current, i, ROREG);
cf95b4f0 1880 if(dops[i].rt1&&!((current->u>>dops[i].rt1)&1)) {
1881 alloc_reg(current,i,dops[i].rt1);
1882 assert(get_reg(current->regmap,dops[i].rt1)>=0);
1883 if(dops[i].opcode==0x27||dops[i].opcode==0x37) // LWU/LD
57871462 1884 {
ad49de89 1885 assert(0);
57871462 1886 }
cf95b4f0 1887 else if(dops[i].opcode==0x1A||dops[i].opcode==0x1B) // LDL/LDR
57871462 1888 {
ad49de89 1889 assert(0);
57871462 1890 }
cf95b4f0 1891 dirty_reg(current,dops[i].rt1);
57871462 1892 // LWL/LWR need a temporary register for the old value
cf95b4f0 1893 if(dops[i].opcode==0x22||dops[i].opcode==0x26)
57871462 1894 {
1895 alloc_reg(current,i,FTEMP);
1896 alloc_reg_temp(current,i,-1);
e1190b87 1897 minimum_free_regs[i]=1;
57871462 1898 }
1899 }
1900 else
1901 {
373d1d07 1902 // Load to r0 or unneeded register (dummy load)
57871462 1903 // but we still need a register to calculate the address
cf95b4f0 1904 if(dops[i].opcode==0x22||dops[i].opcode==0x26)
535d208a 1905 {
1906 alloc_reg(current,i,FTEMP); // LWL/LWR need another temporary
1907 }
57871462 1908 alloc_reg_temp(current,i,-1);
e1190b87 1909 minimum_free_regs[i]=1;
cf95b4f0 1910 if(dops[i].opcode==0x1A||dops[i].opcode==0x1B) // LDL/LDR
535d208a 1911 {
ad49de89 1912 assert(0);
535d208a 1913 }
57871462 1914 }
1915}
1916
4149788d 1917static void store_alloc(struct regstat *current,int i)
57871462 1918{
cf95b4f0 1919 clear_const(current,dops[i].rs2);
1920 if(!(dops[i].rs2)) current->u&=~1LL; // Allow allocating r0 if necessary
1921 if(needed_again(dops[i].rs1,i)) alloc_reg(current,i,dops[i].rs1);
1922 alloc_reg(current,i,dops[i].rs2);
1923 if(dops[i].opcode==0x2c||dops[i].opcode==0x2d||dops[i].opcode==0x3f) { // 64-bit SDL/SDR/SD
ad49de89 1924 assert(0);
57871462 1925 }
37387d8b 1926 if (ram_offset)
1927 alloc_reg(current, i, ROREG);
57871462 1928 #if defined(HOST_IMM8)
1929 // On CPUs without 32-bit immediates we need a pointer to invalid_code
37387d8b 1930 alloc_reg(current, i, INVCP);
57871462 1931 #endif
cf95b4f0 1932 if(dops[i].opcode==0x2a||dops[i].opcode==0x2e||dops[i].opcode==0x2c||dops[i].opcode==0x2d) { // SWL/SWL/SDL/SDR
57871462 1933 alloc_reg(current,i,FTEMP);
1934 }
1935 // We need a temporary register for address generation
1936 alloc_reg_temp(current,i,-1);
e1190b87 1937 minimum_free_regs[i]=1;
57871462 1938}
1939
4149788d 1940static void c1ls_alloc(struct regstat *current,int i)
57871462 1941{
cf95b4f0 1942 clear_const(current,dops[i].rt1);
57871462 1943 alloc_reg(current,i,CSREG); // Status
57871462 1944}
1945
4149788d 1946static void c2ls_alloc(struct regstat *current,int i)
b9b61529 1947{
cf95b4f0 1948 clear_const(current,dops[i].rt1);
1949 if(needed_again(dops[i].rs1,i)) alloc_reg(current,i,dops[i].rs1);
b9b61529 1950 alloc_reg(current,i,FTEMP);
37387d8b 1951 if (ram_offset)
1952 alloc_reg(current, i, ROREG);
b9b61529 1953 #if defined(HOST_IMM8)
1954 // On CPUs without 32-bit immediates we need a pointer to invalid_code
37387d8b 1955 if (dops[i].opcode == 0x3a) // SWC2
b9b61529 1956 alloc_reg(current,i,INVCP);
1957 #endif
1958 // We need a temporary register for address generation
1959 alloc_reg_temp(current,i,-1);
e1190b87 1960 minimum_free_regs[i]=1;
b9b61529 1961}
1962
57871462 1963#ifndef multdiv_alloc
4149788d 1964static void multdiv_alloc(struct regstat *current,int i)
57871462 1965{
1966 // case 0x18: MULT
1967 // case 0x19: MULTU
1968 // case 0x1A: DIV
1969 // case 0x1B: DIVU
1970 // case 0x1C: DMULT
1971 // case 0x1D: DMULTU
1972 // case 0x1E: DDIV
1973 // case 0x1F: DDIVU
cf95b4f0 1974 clear_const(current,dops[i].rs1);
1975 clear_const(current,dops[i].rs2);
32631e6a 1976 alloc_cc(current,i); // for stalls
cf95b4f0 1977 if(dops[i].rs1&&dops[i].rs2)
57871462 1978 {
cf95b4f0 1979 if((dops[i].opcode2&4)==0) // 32-bit
57871462 1980 {
1981 current->u&=~(1LL<<HIREG);
1982 current->u&=~(1LL<<LOREG);
1983 alloc_reg(current,i,HIREG);
1984 alloc_reg(current,i,LOREG);
cf95b4f0 1985 alloc_reg(current,i,dops[i].rs1);
1986 alloc_reg(current,i,dops[i].rs2);
57871462 1987 dirty_reg(current,HIREG);
1988 dirty_reg(current,LOREG);
1989 }
1990 else // 64-bit
1991 {
00fa9369 1992 assert(0);
57871462 1993 }
1994 }
1995 else
1996 {
1997 // Multiply by zero is zero.
1998 // MIPS does not have a divide by zero exception.
1999 // The result is undefined, we return zero.
2000 alloc_reg(current,i,HIREG);
2001 alloc_reg(current,i,LOREG);
57871462 2002 dirty_reg(current,HIREG);
2003 dirty_reg(current,LOREG);
2004 }
2005}
2006#endif
2007
4149788d 2008static void cop0_alloc(struct regstat *current,int i)
57871462 2009{
cf95b4f0 2010 if(dops[i].opcode2==0) // MFC0
57871462 2011 {
cf95b4f0 2012 if(dops[i].rt1) {
2013 clear_const(current,dops[i].rt1);
57871462 2014 alloc_all(current,i);
cf95b4f0 2015 alloc_reg(current,i,dops[i].rt1);
2016 dirty_reg(current,dops[i].rt1);
57871462 2017 }
2018 }
cf95b4f0 2019 else if(dops[i].opcode2==4) // MTC0
57871462 2020 {
cf95b4f0 2021 if(dops[i].rs1){
2022 clear_const(current,dops[i].rs1);
2023 alloc_reg(current,i,dops[i].rs1);
57871462 2024 alloc_all(current,i);
2025 }
2026 else {
2027 alloc_all(current,i); // FIXME: Keep r0
2028 current->u&=~1LL;
2029 alloc_reg(current,i,0);
2030 }
2031 }
2032 else
2033 {
2034 // TLBR/TLBWI/TLBWR/TLBP/ERET
cf95b4f0 2035 assert(dops[i].opcode2==0x10);
57871462 2036 alloc_all(current,i);
2037 }
e1190b87 2038 minimum_free_regs[i]=HOST_REGS;
57871462 2039}
2040
81dbbf4c 2041static void cop2_alloc(struct regstat *current,int i)
57871462 2042{
cf95b4f0 2043 if (dops[i].opcode2 < 3) // MFC2/CFC2
57871462 2044 {
81dbbf4c 2045 alloc_cc(current,i); // for stalls
2046 dirty_reg(current,CCREG);
cf95b4f0 2047 if(dops[i].rt1){
2048 clear_const(current,dops[i].rt1);
2049 alloc_reg(current,i,dops[i].rt1);
2050 dirty_reg(current,dops[i].rt1);
57871462 2051 }
57871462 2052 }
cf95b4f0 2053 else if (dops[i].opcode2 > 3) // MTC2/CTC2
57871462 2054 {
cf95b4f0 2055 if(dops[i].rs1){
2056 clear_const(current,dops[i].rs1);
2057 alloc_reg(current,i,dops[i].rs1);
57871462 2058 }
2059 else {
2060 current->u&=~1LL;
2061 alloc_reg(current,i,0);
57871462 2062 }
2063 }
81dbbf4c 2064 alloc_reg_temp(current,i,-1);
e1190b87 2065 minimum_free_regs[i]=1;
57871462 2066}
00fa9369 2067
4149788d 2068static void c2op_alloc(struct regstat *current,int i)
b9b61529 2069{
81dbbf4c 2070 alloc_cc(current,i); // for stalls
2071 dirty_reg(current,CCREG);
b9b61529 2072 alloc_reg_temp(current,i,-1);
2073}
57871462 2074
4149788d 2075static void syscall_alloc(struct regstat *current,int i)
57871462 2076{
2077 alloc_cc(current,i);
2078 dirty_reg(current,CCREG);
2079 alloc_all(current,i);
e1190b87 2080 minimum_free_regs[i]=HOST_REGS;
57871462 2081 current->isconst=0;
2082}
2083
4149788d 2084static void delayslot_alloc(struct regstat *current,int i)
57871462 2085{
cf95b4f0 2086 switch(dops[i].itype) {
57871462 2087 case UJUMP:
2088 case CJUMP:
2089 case SJUMP:
2090 case RJUMP:
57871462 2091 case SYSCALL:
7139f3c8 2092 case HLECALL:
57871462 2093 case SPAN:
7c3a5182 2094 assem_debug("jump in the delay slot. this shouldn't happen.\n");//abort();
c43b5311 2095 SysPrintf("Disabled speculative precompilation\n");
57871462 2096 stop_after_jal=1;
2097 break;
2098 case IMM16:
2099 imm16_alloc(current,i);
2100 break;
2101 case LOAD:
2102 case LOADLR:
2103 load_alloc(current,i);
2104 break;
2105 case STORE:
2106 case STORELR:
2107 store_alloc(current,i);
2108 break;
2109 case ALU:
2110 alu_alloc(current,i);
2111 break;
2112 case SHIFT:
2113 shift_alloc(current,i);
2114 break;
2115 case MULTDIV:
2116 multdiv_alloc(current,i);
2117 break;
2118 case SHIFTIMM:
2119 shiftimm_alloc(current,i);
2120 break;
2121 case MOV:
2122 mov_alloc(current,i);
2123 break;
2124 case COP0:
2125 cop0_alloc(current,i);
2126 break;
2127 case COP1:
81dbbf4c 2128 break;
b9b61529 2129 case COP2:
81dbbf4c 2130 cop2_alloc(current,i);
57871462 2131 break;
2132 case C1LS:
2133 c1ls_alloc(current,i);
2134 break;
b9b61529 2135 case C2LS:
2136 c2ls_alloc(current,i);
2137 break;
b9b61529 2138 case C2OP:
2139 c2op_alloc(current,i);
2140 break;
57871462 2141 }
2142}
2143
2144// Special case where a branch and delay slot span two pages in virtual memory
2145static void pagespan_alloc(struct regstat *current,int i)
2146{
2147 current->isconst=0;
2148 current->wasconst=0;
2149 regs[i].wasconst=0;
e1190b87 2150 minimum_free_regs[i]=HOST_REGS;
57871462 2151 alloc_all(current,i);
2152 alloc_cc(current,i);
2153 dirty_reg(current,CCREG);
cf95b4f0 2154 if(dops[i].opcode==3) // JAL
57871462 2155 {
2156 alloc_reg(current,i,31);
2157 dirty_reg(current,31);
2158 }
cf95b4f0 2159 if(dops[i].opcode==0&&(dops[i].opcode2&0x3E)==8) // JR/JALR
57871462 2160 {
cf95b4f0 2161 alloc_reg(current,i,dops[i].rs1);
2162 if (dops[i].rt1!=0) {
2163 alloc_reg(current,i,dops[i].rt1);
2164 dirty_reg(current,dops[i].rt1);
57871462 2165 }
2166 }
cf95b4f0 2167 if((dops[i].opcode&0x2E)==4) // BEQ/BNE/BEQL/BNEL
57871462 2168 {
cf95b4f0 2169 if(dops[i].rs1) alloc_reg(current,i,dops[i].rs1);
2170 if(dops[i].rs2) alloc_reg(current,i,dops[i].rs2);
57871462 2171 }
2172 else
cf95b4f0 2173 if((dops[i].opcode&0x2E)==6) // BLEZ/BGTZ/BLEZL/BGTZL
57871462 2174 {
cf95b4f0 2175 if(dops[i].rs1) alloc_reg(current,i,dops[i].rs1);
57871462 2176 }
57871462 2177 //else ...
2178}
2179
b14b6a8f 2180static void add_stub(enum stub_type type, void *addr, void *retaddr,
2181 u_int a, uintptr_t b, uintptr_t c, u_int d, u_int e)
2182{
d1e4ebd9 2183 assert(stubcount < ARRAY_SIZE(stubs));
b14b6a8f 2184 stubs[stubcount].type = type;
2185 stubs[stubcount].addr = addr;
2186 stubs[stubcount].retaddr = retaddr;
2187 stubs[stubcount].a = a;
2188 stubs[stubcount].b = b;
2189 stubs[stubcount].c = c;
2190 stubs[stubcount].d = d;
2191 stubs[stubcount].e = e;
57871462 2192 stubcount++;
2193}
2194
b14b6a8f 2195static void add_stub_r(enum stub_type type, void *addr, void *retaddr,
81dbbf4c 2196 int i, int addr_reg, const struct regstat *i_regs, int ccadj, u_int reglist)
b14b6a8f 2197{
2198 add_stub(type, addr, retaddr, i, addr_reg, (uintptr_t)i_regs, ccadj, reglist);
2199}
2200
57871462 2201// Write out a single register
2330734f 2202static void wb_register(signed char r, const signed char regmap[], uint64_t dirty)
57871462 2203{
2204 int hr;
2205 for(hr=0;hr<HOST_REGS;hr++) {
2206 if(hr!=EXCLUDE_REG) {
9de8a0c3 2207 if(regmap[hr]==r) {
57871462 2208 if((dirty>>hr)&1) {
ad49de89 2209 assert(regmap[hr]<64);
2210 emit_storereg(r,hr);
57871462 2211 }
2212 }
2213 }
2214 }
2215}
2216
8062d65a 2217static void wb_valid(signed char pre[],signed char entry[],u_int dirty_pre,u_int dirty,uint64_t u)
2218{
2219 //if(dirty_pre==dirty) return;
53358c1d 2220 int hr, r;
2221 for (hr = 0; hr < HOST_REGS; hr++) {
2222 r = pre[hr];
2223 if (r < 1 || r > 33 || ((u >> r) & 1))
2224 continue;
2225 if (((dirty_pre & ~dirty) >> hr) & 1)
2226 emit_storereg(r, hr);
8062d65a 2227 }
2228}
2229
687b4580 2230// trashes r2
2231static void pass_args(int a0, int a1)
2232{
2233 if(a0==1&&a1==0) {
2234 // must swap
2235 emit_mov(a0,2); emit_mov(a1,1); emit_mov(2,0);
2236 }
2237 else if(a0!=0&&a1==0) {
2238 emit_mov(a1,1);
2239 if (a0>=0) emit_mov(a0,0);
2240 }
2241 else {
2242 if(a0>=0&&a0!=0) emit_mov(a0,0);
2243 if(a1>=0&&a1!=1) emit_mov(a1,1);
2244 }
2245}
2246
2330734f 2247static void alu_assemble(int i, const struct regstat *i_regs)
57871462 2248{
cf95b4f0 2249 if(dops[i].opcode2>=0x20&&dops[i].opcode2<=0x23) { // ADD/ADDU/SUB/SUBU
2250 if(dops[i].rt1) {
57871462 2251 signed char s1,s2,t;
cf95b4f0 2252 t=get_reg(i_regs->regmap,dops[i].rt1);
57871462 2253 if(t>=0) {
cf95b4f0 2254 s1=get_reg(i_regs->regmap,dops[i].rs1);
2255 s2=get_reg(i_regs->regmap,dops[i].rs2);
2256 if(dops[i].rs1&&dops[i].rs2) {
57871462 2257 assert(s1>=0);
2258 assert(s2>=0);
cf95b4f0 2259 if(dops[i].opcode2&2) emit_sub(s1,s2,t);
57871462 2260 else emit_add(s1,s2,t);
2261 }
cf95b4f0 2262 else if(dops[i].rs1) {
57871462 2263 if(s1>=0) emit_mov(s1,t);
cf95b4f0 2264 else emit_loadreg(dops[i].rs1,t);
57871462 2265 }
cf95b4f0 2266 else if(dops[i].rs2) {
57871462 2267 if(s2>=0) {
cf95b4f0 2268 if(dops[i].opcode2&2) emit_neg(s2,t);
57871462 2269 else emit_mov(s2,t);
2270 }
2271 else {
cf95b4f0 2272 emit_loadreg(dops[i].rs2,t);
2273 if(dops[i].opcode2&2) emit_neg(t,t);
57871462 2274 }
2275 }
2276 else emit_zeroreg(t);
2277 }
2278 }
2279 }
cf95b4f0 2280 if(dops[i].opcode2>=0x2c&&dops[i].opcode2<=0x2f) { // DADD/DADDU/DSUB/DSUBU
00fa9369 2281 assert(0);
57871462 2282 }
cf95b4f0 2283 if(dops[i].opcode2==0x2a||dops[i].opcode2==0x2b) { // SLT/SLTU
2284 if(dops[i].rt1) {
ad49de89 2285 signed char s1l,s2l,t;
57871462 2286 {
cf95b4f0 2287 t=get_reg(i_regs->regmap,dops[i].rt1);
57871462 2288 //assert(t>=0);
2289 if(t>=0) {
cf95b4f0 2290 s1l=get_reg(i_regs->regmap,dops[i].rs1);
2291 s2l=get_reg(i_regs->regmap,dops[i].rs2);
2292 if(dops[i].rs2==0) // rx<r0
57871462 2293 {
cf95b4f0 2294 if(dops[i].opcode2==0x2a&&dops[i].rs1!=0) { // SLT
06e425d7 2295 assert(s1l>=0);
57871462 2296 emit_shrimm(s1l,31,t);
06e425d7 2297 }
2298 else // SLTU (unsigned can not be less than zero, 0<0)
57871462 2299 emit_zeroreg(t);
2300 }
cf95b4f0 2301 else if(dops[i].rs1==0) // r0<rx
57871462 2302 {
2303 assert(s2l>=0);
cf95b4f0 2304 if(dops[i].opcode2==0x2a) // SLT
57871462 2305 emit_set_gz32(s2l,t);
2306 else // SLTU (set if not zero)
2307 emit_set_nz32(s2l,t);
2308 }
2309 else{
2310 assert(s1l>=0);assert(s2l>=0);
cf95b4f0 2311 if(dops[i].opcode2==0x2a) // SLT
57871462 2312 emit_set_if_less32(s1l,s2l,t);
2313 else // SLTU
2314 emit_set_if_carry32(s1l,s2l,t);
2315 }
2316 }
2317 }
2318 }
2319 }
cf95b4f0 2320 if(dops[i].opcode2>=0x24&&dops[i].opcode2<=0x27) { // AND/OR/XOR/NOR
2321 if(dops[i].rt1) {
ad49de89 2322 signed char s1l,s2l,tl;
cf95b4f0 2323 tl=get_reg(i_regs->regmap,dops[i].rt1);
57871462 2324 {
57871462 2325 if(tl>=0) {
cf95b4f0 2326 s1l=get_reg(i_regs->regmap,dops[i].rs1);
2327 s2l=get_reg(i_regs->regmap,dops[i].rs2);
2328 if(dops[i].rs1&&dops[i].rs2) {
57871462 2329 assert(s1l>=0);
2330 assert(s2l>=0);
cf95b4f0 2331 if(dops[i].opcode2==0x24) { // AND
57871462 2332 emit_and(s1l,s2l,tl);
2333 } else
cf95b4f0 2334 if(dops[i].opcode2==0x25) { // OR
57871462 2335 emit_or(s1l,s2l,tl);
2336 } else
cf95b4f0 2337 if(dops[i].opcode2==0x26) { // XOR
57871462 2338 emit_xor(s1l,s2l,tl);
2339 } else
cf95b4f0 2340 if(dops[i].opcode2==0x27) { // NOR
57871462 2341 emit_or(s1l,s2l,tl);
2342 emit_not(tl,tl);
2343 }
2344 }
2345 else
2346 {
cf95b4f0 2347 if(dops[i].opcode2==0x24) { // AND
57871462 2348 emit_zeroreg(tl);
2349 } else
cf95b4f0 2350 if(dops[i].opcode2==0x25||dops[i].opcode2==0x26) { // OR/XOR
2351 if(dops[i].rs1){
57871462 2352 if(s1l>=0) emit_mov(s1l,tl);
cf95b4f0 2353 else emit_loadreg(dops[i].rs1,tl); // CHECK: regmap_entry?
57871462 2354 }
2355 else
cf95b4f0 2356 if(dops[i].rs2){
57871462 2357 if(s2l>=0) emit_mov(s2l,tl);
cf95b4f0 2358 else emit_loadreg(dops[i].rs2,tl); // CHECK: regmap_entry?
57871462 2359 }
2360 else emit_zeroreg(tl);
2361 } else
cf95b4f0 2362 if(dops[i].opcode2==0x27) { // NOR
2363 if(dops[i].rs1){
57871462 2364 if(s1l>=0) emit_not(s1l,tl);
2365 else {
cf95b4f0 2366 emit_loadreg(dops[i].rs1,tl);
57871462 2367 emit_not(tl,tl);
2368 }
2369 }
2370 else
cf95b4f0 2371 if(dops[i].rs2){
57871462 2372 if(s2l>=0) emit_not(s2l,tl);
2373 else {
cf95b4f0 2374 emit_loadreg(dops[i].rs2,tl);
57871462 2375 emit_not(tl,tl);
2376 }
2377 }
2378 else emit_movimm(-1,tl);
2379 }
2380 }
2381 }
2382 }
2383 }
2384 }
2385}
2386
2330734f 2387static void imm16_assemble(int i, const struct regstat *i_regs)
57871462 2388{
cf95b4f0 2389 if (dops[i].opcode==0x0f) { // LUI
2390 if(dops[i].rt1) {
57871462 2391 signed char t;
cf95b4f0 2392 t=get_reg(i_regs->regmap,dops[i].rt1);
57871462 2393 //assert(t>=0);
2394 if(t>=0) {
2395 if(!((i_regs->isconst>>t)&1))
2396 emit_movimm(imm[i]<<16,t);
2397 }
2398 }
2399 }
cf95b4f0 2400 if(dops[i].opcode==0x08||dops[i].opcode==0x09) { // ADDI/ADDIU
2401 if(dops[i].rt1) {
57871462 2402 signed char s,t;
cf95b4f0 2403 t=get_reg(i_regs->regmap,dops[i].rt1);
2404 s=get_reg(i_regs->regmap,dops[i].rs1);
2405 if(dops[i].rs1) {
57871462 2406 //assert(t>=0);
2407 //assert(s>=0);
2408 if(t>=0) {
2409 if(!((i_regs->isconst>>t)&1)) {
2410 if(s<0) {
cf95b4f0 2411 if(i_regs->regmap_entry[t]!=dops[i].rs1) emit_loadreg(dops[i].rs1,t);
57871462 2412 emit_addimm(t,imm[i],t);
2413 }else{
2414 if(!((i_regs->wasconst>>s)&1))
2415 emit_addimm(s,imm[i],t);
2416 else
2417 emit_movimm(constmap[i][s]+imm[i],t);
2418 }
2419 }
2420 }
2421 } else {
2422 if(t>=0) {
2423 if(!((i_regs->isconst>>t)&1))
2424 emit_movimm(imm[i],t);
2425 }
2426 }
2427 }
2428 }
cf95b4f0 2429 if(dops[i].opcode==0x18||dops[i].opcode==0x19) { // DADDI/DADDIU
2430 if(dops[i].rt1) {
7c3a5182 2431 signed char sl,tl;
cf95b4f0 2432 tl=get_reg(i_regs->regmap,dops[i].rt1);
2433 sl=get_reg(i_regs->regmap,dops[i].rs1);
57871462 2434 if(tl>=0) {
cf95b4f0 2435 if(dops[i].rs1) {
57871462 2436 assert(sl>=0);
7c3a5182 2437 emit_addimm(sl,imm[i],tl);
57871462 2438 } else {
2439 emit_movimm(imm[i],tl);
57871462 2440 }
2441 }
2442 }
2443 }
cf95b4f0 2444 else if(dops[i].opcode==0x0a||dops[i].opcode==0x0b) { // SLTI/SLTIU
2445 if(dops[i].rt1) {
2446 //assert(dops[i].rs1!=0); // r0 might be valid, but it's probably a bug
ad49de89 2447 signed char sl,t;
cf95b4f0 2448 t=get_reg(i_regs->regmap,dops[i].rt1);
2449 sl=get_reg(i_regs->regmap,dops[i].rs1);
57871462 2450 //assert(t>=0);
2451 if(t>=0) {
cf95b4f0 2452 if(dops[i].rs1>0) {
2453 if(dops[i].opcode==0x0a) { // SLTI
57871462 2454 if(sl<0) {
cf95b4f0 2455 if(i_regs->regmap_entry[t]!=dops[i].rs1) emit_loadreg(dops[i].rs1,t);
57871462 2456 emit_slti32(t,imm[i],t);
2457 }else{
2458 emit_slti32(sl,imm[i],t);
2459 }
2460 }
2461 else { // SLTIU
2462 if(sl<0) {
cf95b4f0 2463 if(i_regs->regmap_entry[t]!=dops[i].rs1) emit_loadreg(dops[i].rs1,t);
57871462 2464 emit_sltiu32(t,imm[i],t);
2465 }else{
2466 emit_sltiu32(sl,imm[i],t);
2467 }
2468 }
57871462 2469 }else{
2470 // SLTI(U) with r0 is just stupid,
2471 // nonetheless examples can be found
cf95b4f0 2472 if(dops[i].opcode==0x0a) // SLTI
57871462 2473 if(0<imm[i]) emit_movimm(1,t);
2474 else emit_zeroreg(t);
2475 else // SLTIU
2476 {
2477 if(imm[i]) emit_movimm(1,t);
2478 else emit_zeroreg(t);
2479 }
2480 }
2481 }
2482 }
2483 }
cf95b4f0 2484 else if(dops[i].opcode>=0x0c&&dops[i].opcode<=0x0e) { // ANDI/ORI/XORI
2485 if(dops[i].rt1) {
7c3a5182 2486 signed char sl,tl;
cf95b4f0 2487 tl=get_reg(i_regs->regmap,dops[i].rt1);
2488 sl=get_reg(i_regs->regmap,dops[i].rs1);
57871462 2489 if(tl>=0 && !((i_regs->isconst>>tl)&1)) {
cf95b4f0 2490 if(dops[i].opcode==0x0c) //ANDI
57871462 2491 {
cf95b4f0 2492 if(dops[i].rs1) {
57871462 2493 if(sl<0) {
cf95b4f0 2494 if(i_regs->regmap_entry[tl]!=dops[i].rs1) emit_loadreg(dops[i].rs1,tl);
57871462 2495 emit_andimm(tl,imm[i],tl);
2496 }else{
2497 if(!((i_regs->wasconst>>sl)&1))
2498 emit_andimm(sl,imm[i],tl);
2499 else
2500 emit_movimm(constmap[i][sl]&imm[i],tl);
2501 }
2502 }
2503 else
2504 emit_zeroreg(tl);
57871462 2505 }
2506 else
2507 {
cf95b4f0 2508 if(dops[i].rs1) {
57871462 2509 if(sl<0) {
cf95b4f0 2510 if(i_regs->regmap_entry[tl]!=dops[i].rs1) emit_loadreg(dops[i].rs1,tl);
57871462 2511 }
cf95b4f0 2512 if(dops[i].opcode==0x0d) { // ORI
581335b0 2513 if(sl<0) {
2514 emit_orimm(tl,imm[i],tl);
2515 }else{
2516 if(!((i_regs->wasconst>>sl)&1))
2517 emit_orimm(sl,imm[i],tl);
2518 else
2519 emit_movimm(constmap[i][sl]|imm[i],tl);
2520 }
57871462 2521 }
cf95b4f0 2522 if(dops[i].opcode==0x0e) { // XORI
581335b0 2523 if(sl<0) {
2524 emit_xorimm(tl,imm[i],tl);
2525 }else{
2526 if(!((i_regs->wasconst>>sl)&1))
2527 emit_xorimm(sl,imm[i],tl);
2528 else
2529 emit_movimm(constmap[i][sl]^imm[i],tl);
2530 }
57871462 2531 }
2532 }
2533 else {
2534 emit_movimm(imm[i],tl);
57871462 2535 }
2536 }
2537 }
2538 }
2539 }
2540}
2541
2330734f 2542static void shiftimm_assemble(int i, const struct regstat *i_regs)
57871462 2543{
cf95b4f0 2544 if(dops[i].opcode2<=0x3) // SLL/SRL/SRA
57871462 2545 {
cf95b4f0 2546 if(dops[i].rt1) {
57871462 2547 signed char s,t;
cf95b4f0 2548 t=get_reg(i_regs->regmap,dops[i].rt1);
2549 s=get_reg(i_regs->regmap,dops[i].rs1);
57871462 2550 //assert(t>=0);
dc49e339 2551 if(t>=0&&!((i_regs->isconst>>t)&1)){
cf95b4f0 2552 if(dops[i].rs1==0)
57871462 2553 {
2554 emit_zeroreg(t);
2555 }
2556 else
2557 {
cf95b4f0 2558 if(s<0&&i_regs->regmap_entry[t]!=dops[i].rs1) emit_loadreg(dops[i].rs1,t);
57871462 2559 if(imm[i]) {
cf95b4f0 2560 if(dops[i].opcode2==0) // SLL
57871462 2561 {
2562 emit_shlimm(s<0?t:s,imm[i],t);
2563 }
cf95b4f0 2564 if(dops[i].opcode2==2) // SRL
57871462 2565 {
2566 emit_shrimm(s<0?t:s,imm[i],t);
2567 }
cf95b4f0 2568 if(dops[i].opcode2==3) // SRA
57871462 2569 {
2570 emit_sarimm(s<0?t:s,imm[i],t);
2571 }
2572 }else{
2573 // Shift by zero
2574 if(s>=0 && s!=t) emit_mov(s,t);
2575 }
2576 }
2577 }
cf95b4f0 2578 //emit_storereg(dops[i].rt1,t); //DEBUG
57871462 2579 }
2580 }
cf95b4f0 2581 if(dops[i].opcode2>=0x38&&dops[i].opcode2<=0x3b) // DSLL/DSRL/DSRA
57871462 2582 {
9c45ca93 2583 assert(0);
57871462 2584 }
cf95b4f0 2585 if(dops[i].opcode2==0x3c) // DSLL32
57871462 2586 {
9c45ca93 2587 assert(0);
57871462 2588 }
cf95b4f0 2589 if(dops[i].opcode2==0x3e) // DSRL32
57871462 2590 {
9c45ca93 2591 assert(0);
57871462 2592 }
cf95b4f0 2593 if(dops[i].opcode2==0x3f) // DSRA32
57871462 2594 {
9c45ca93 2595 assert(0);
57871462 2596 }
2597}
2598
2599#ifndef shift_assemble
2330734f 2600static void shift_assemble(int i, const struct regstat *i_regs)
57871462 2601{
3968e69e 2602 signed char s,t,shift;
cf95b4f0 2603 if (dops[i].rt1 == 0)
3968e69e 2604 return;
cf95b4f0 2605 assert(dops[i].opcode2<=0x07); // SLLV/SRLV/SRAV
2606 t = get_reg(i_regs->regmap, dops[i].rt1);
2607 s = get_reg(i_regs->regmap, dops[i].rs1);
2608 shift = get_reg(i_regs->regmap, dops[i].rs2);
3968e69e 2609 if (t < 0)
2610 return;
2611
cf95b4f0 2612 if(dops[i].rs1==0)
3968e69e 2613 emit_zeroreg(t);
cf95b4f0 2614 else if(dops[i].rs2==0) {
3968e69e 2615 assert(s>=0);
2616 if(s!=t) emit_mov(s,t);
2617 }
2618 else {
2619 host_tempreg_acquire();
2620 emit_andimm(shift,31,HOST_TEMPREG);
cf95b4f0 2621 switch(dops[i].opcode2) {
3968e69e 2622 case 4: // SLLV
2623 emit_shl(s,HOST_TEMPREG,t);
2624 break;
2625 case 6: // SRLV
2626 emit_shr(s,HOST_TEMPREG,t);
2627 break;
2628 case 7: // SRAV
2629 emit_sar(s,HOST_TEMPREG,t);
2630 break;
2631 default:
2632 assert(0);
2633 }
2634 host_tempreg_release();
2635 }
57871462 2636}
3968e69e 2637
57871462 2638#endif
2639
8062d65a 2640enum {
2641 MTYPE_8000 = 0,
2642 MTYPE_8020,
2643 MTYPE_0000,
2644 MTYPE_A000,
2645 MTYPE_1F80,
2646};
2647
2648static int get_ptr_mem_type(u_int a)
2649{
2650 if(a < 0x00200000) {
2651 if(a<0x1000&&((start>>20)==0xbfc||(start>>24)==0xa0))
2652 // return wrong, must use memhandler for BIOS self-test to pass
2653 // 007 does similar stuff from a00 mirror, weird stuff
2654 return MTYPE_8000;
2655 return MTYPE_0000;
2656 }
2657 if(0x1f800000 <= a && a < 0x1f801000)
2658 return MTYPE_1F80;
2659 if(0x80200000 <= a && a < 0x80800000)
2660 return MTYPE_8020;
2661 if(0xa0000000 <= a && a < 0xa0200000)
2662 return MTYPE_A000;
2663 return MTYPE_8000;
2664}
2665
37387d8b 2666static int get_ro_reg(const struct regstat *i_regs, int host_tempreg_free)
2667{
2668 int r = get_reg(i_regs->regmap, ROREG);
2669 if (r < 0 && host_tempreg_free) {
2670 host_tempreg_acquire();
2671 emit_loadreg(ROREG, r = HOST_TEMPREG);
2672 }
2673 if (r < 0)
2674 abort();
2675 return r;
2676}
2677
2678static void *emit_fastpath_cmp_jump(int i, const struct regstat *i_regs,
2679 int addr, int *offset_reg, int *addr_reg_override)
8062d65a 2680{
2681 void *jaddr = NULL;
37387d8b 2682 int type = 0;
2683 int mr = dops[i].rs1;
2684 *offset_reg = -1;
8062d65a 2685 if(((smrv_strong|smrv_weak)>>mr)&1) {
2686 type=get_ptr_mem_type(smrv[mr]);
2687 //printf("set %08x @%08x r%d %d\n", smrv[mr], start+i*4, mr, type);
2688 }
2689 else {
2690 // use the mirror we are running on
2691 type=get_ptr_mem_type(start);
2692 //printf("set nospec @%08x r%d %d\n", start+i*4, mr, type);
2693 }
2694
2695 if(type==MTYPE_8020) { // RAM 80200000+ mirror
d1e4ebd9 2696 host_tempreg_acquire();
8062d65a 2697 emit_andimm(addr,~0x00e00000,HOST_TEMPREG);
2698 addr=*addr_reg_override=HOST_TEMPREG;
2699 type=0;
2700 }
2701 else if(type==MTYPE_0000) { // RAM 0 mirror
d1e4ebd9 2702 host_tempreg_acquire();
8062d65a 2703 emit_orimm(addr,0x80000000,HOST_TEMPREG);
2704 addr=*addr_reg_override=HOST_TEMPREG;
2705 type=0;
2706 }
2707 else if(type==MTYPE_A000) { // RAM A mirror
d1e4ebd9 2708 host_tempreg_acquire();
8062d65a 2709 emit_andimm(addr,~0x20000000,HOST_TEMPREG);
2710 addr=*addr_reg_override=HOST_TEMPREG;
2711 type=0;
2712 }
2713 else if(type==MTYPE_1F80) { // scratchpad
2714 if (psxH == (void *)0x1f800000) {
d1e4ebd9 2715 host_tempreg_acquire();
3968e69e 2716 emit_xorimm(addr,0x1f800000,HOST_TEMPREG);
8062d65a 2717 emit_cmpimm(HOST_TEMPREG,0x1000);
d1e4ebd9 2718 host_tempreg_release();
8062d65a 2719 jaddr=out;
2720 emit_jc(0);
2721 }
2722 else {
2723 // do the usual RAM check, jump will go to the right handler
2724 type=0;
2725 }
2726 }
2727
37387d8b 2728 if (type == 0) // need ram check
8062d65a 2729 {
2730 emit_cmpimm(addr,RAM_SIZE);
37387d8b 2731 jaddr = out;
8062d65a 2732 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
2733 // Hint to branch predictor that the branch is unlikely to be taken
37387d8b 2734 if (dops[i].rs1 >= 28)
8062d65a 2735 emit_jno_unlikely(0);
2736 else
2737 #endif
2738 emit_jno(0);
37387d8b 2739 if (ram_offset != 0)
2740 *offset_reg = get_ro_reg(i_regs, 0);
8062d65a 2741 }
2742
2743 return jaddr;
2744}
2745
687b4580 2746// return memhandler, or get directly accessable address and return 0
2747static void *get_direct_memhandler(void *table, u_int addr,
2748 enum stub_type type, uintptr_t *addr_host)
2749{
c979e8c2 2750 uintptr_t msb = 1ull << (sizeof(uintptr_t)*8 - 1);
687b4580 2751 uintptr_t l1, l2 = 0;
2752 l1 = ((uintptr_t *)table)[addr>>12];
c979e8c2 2753 if (!(l1 & msb)) {
687b4580 2754 uintptr_t v = l1 << 1;
2755 *addr_host = v + addr;
2756 return NULL;
2757 }
2758 else {
2759 l1 <<= 1;
2760 if (type == LOADB_STUB || type == LOADBU_STUB || type == STOREB_STUB)
2761 l2 = ((uintptr_t *)l1)[0x1000/4 + 0x1000/2 + (addr&0xfff)];
2762 else if (type == LOADH_STUB || type == LOADHU_STUB || type == STOREH_STUB)
c979e8c2 2763 l2 = ((uintptr_t *)l1)[0x1000/4 + (addr&0xfff)/2];
687b4580 2764 else
c979e8c2 2765 l2 = ((uintptr_t *)l1)[(addr&0xfff)/4];
2766 if (!(l2 & msb)) {
687b4580 2767 uintptr_t v = l2 << 1;
2768 *addr_host = v + (addr&0xfff);
2769 return NULL;
2770 }
2771 return (void *)(l2 << 1);
2772 }
2773}
2774
81dbbf4c 2775static u_int get_host_reglist(const signed char *regmap)
2776{
2777 u_int reglist = 0, hr;
2778 for (hr = 0; hr < HOST_REGS; hr++) {
2779 if (hr != EXCLUDE_REG && regmap[hr] >= 0)
2780 reglist |= 1 << hr;
2781 }
2782 return reglist;
2783}
2784
2785static u_int reglist_exclude(u_int reglist, int r1, int r2)
2786{
2787 if (r1 >= 0)
2788 reglist &= ~(1u << r1);
2789 if (r2 >= 0)
2790 reglist &= ~(1u << r2);
2791 return reglist;
2792}
2793
e3c6bdb5 2794// find a temp caller-saved register not in reglist (so assumed to be free)
2795static int reglist_find_free(u_int reglist)
2796{
2797 u_int free_regs = ~reglist & CALLER_SAVE_REGS;
2798 if (free_regs == 0)
2799 return -1;
2800 return __builtin_ctz(free_regs);
2801}
2802
37387d8b 2803static void do_load_word(int a, int rt, int offset_reg)
2804{
2805 if (offset_reg >= 0)
2806 emit_ldr_dualindexed(offset_reg, a, rt);
2807 else
2808 emit_readword_indexed(0, a, rt);
2809}
2810
2811static void do_store_word(int a, int ofs, int rt, int offset_reg, int preseve_a)
2812{
2813 if (offset_reg < 0) {
2814 emit_writeword_indexed(rt, ofs, a);
2815 return;
2816 }
2817 if (ofs != 0)
2818 emit_addimm(a, ofs, a);
2819 emit_str_dualindexed(offset_reg, a, rt);
2820 if (ofs != 0 && preseve_a)
2821 emit_addimm(a, -ofs, a);
2822}
2823
2824static void do_store_hword(int a, int ofs, int rt, int offset_reg, int preseve_a)
2825{
2826 if (offset_reg < 0) {
2827 emit_writehword_indexed(rt, ofs, a);
2828 return;
2829 }
2830 if (ofs != 0)
2831 emit_addimm(a, ofs, a);
2832 emit_strh_dualindexed(offset_reg, a, rt);
2833 if (ofs != 0 && preseve_a)
2834 emit_addimm(a, -ofs, a);
2835}
2836
2837static void do_store_byte(int a, int rt, int offset_reg)
2838{
2839 if (offset_reg >= 0)
2840 emit_strb_dualindexed(offset_reg, a, rt);
2841 else
2842 emit_writebyte_indexed(rt, 0, a);
2843}
2844
2330734f 2845static void load_assemble(int i, const struct regstat *i_regs, int ccadj_)
57871462 2846{
7c3a5182 2847 int s,tl,addr;
57871462 2848 int offset;
b14b6a8f 2849 void *jaddr=0;
5bf843dc 2850 int memtarget=0,c=0;
37387d8b 2851 int offset_reg = -1;
2852 int fastio_reg_override = -1;
81dbbf4c 2853 u_int reglist=get_host_reglist(i_regs->regmap);
cf95b4f0 2854 tl=get_reg(i_regs->regmap,dops[i].rt1);
2855 s=get_reg(i_regs->regmap,dops[i].rs1);
57871462 2856 offset=imm[i];
57871462 2857 if(i_regs->regmap[HOST_CCREG]==CCREG) reglist&=~(1<<HOST_CCREG);
2858 if(s>=0) {
2859 c=(i_regs->wasconst>>s)&1;
af4ee1fe 2860 if (c) {
2861 memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
af4ee1fe 2862 }
57871462 2863 }
57871462 2864 //printf("load_assemble: c=%d\n",c);
643aeae3 2865 //if(c) printf("load_assemble: const=%lx\n",(long)constmap[i][s]+offset);
57871462 2866 // FIXME: Even if the load is a NOP, we should check for pagefaults...
581335b0 2867 if((tl<0&&(!c||(((u_int)constmap[i][s]+offset)>>16)==0x1f80))
cf95b4f0 2868 ||dops[i].rt1==0) {
5bf843dc 2869 // could be FIFO, must perform the read
f18c0f46 2870 // ||dummy read
5bf843dc 2871 assem_debug("(forced read)\n");
9de8a0c3 2872 tl=get_reg_temp(i_regs->regmap);
5bf843dc 2873 assert(tl>=0);
5bf843dc 2874 }
2875 if(offset||s<0||c) addr=tl;
2876 else addr=s;
9de8a0c3 2877 //if(tl<0) tl=get_reg_temp(i_regs->regmap);
535d208a 2878 if(tl>=0) {
2879 //printf("load_assemble: c=%d\n",c);
643aeae3 2880 //if(c) printf("load_assemble: const=%lx\n",(long)constmap[i][s]+offset);
535d208a 2881 assert(tl>=0); // Even if the load is a NOP, we must check for pagefaults and I/O
2882 reglist&=~(1<<tl);
1edfcc68 2883 if(!c) {
1edfcc68 2884 #ifdef R29_HACK
2885 // Strmnnrmn's speed hack
cf95b4f0 2886 if(dops[i].rs1!=29||start<0x80001000||start>=0x80000000+RAM_SIZE)
1edfcc68 2887 #endif
2888 {
37387d8b 2889 jaddr = emit_fastpath_cmp_jump(i, i_regs, addr,
2890 &offset_reg, &fastio_reg_override);
535d208a 2891 }
1edfcc68 2892 }
37387d8b 2893 else if (ram_offset && memtarget) {
2894 offset_reg = get_ro_reg(i_regs, 0);
535d208a 2895 }
cf95b4f0 2896 int dummy=(dops[i].rt1==0)||(tl!=get_reg(i_regs->regmap,dops[i].rt1)); // ignore loads to r0 and unneeded reg
37387d8b 2897 switch (dops[i].opcode) {
2898 case 0x20: // LB
535d208a 2899 if(!c||memtarget) {
2900 if(!dummy) {
37387d8b 2901 int a = tl;
2902 if (!c) a = addr;
2903 if (fastio_reg_override >= 0)
2904 a = fastio_reg_override;
b1570849 2905
37387d8b 2906 if (offset_reg >= 0)
2907 emit_ldrsb_dualindexed(offset_reg, a, tl);
2908 else
2909 emit_movsbl_indexed(0, a, tl);
57871462 2910 }
535d208a 2911 if(jaddr)
2330734f 2912 add_stub_r(LOADB_STUB,jaddr,out,i,addr,i_regs,ccadj_,reglist);
57871462 2913 }
535d208a 2914 else
2330734f 2915 inline_readstub(LOADB_STUB,i,constmap[i][s]+offset,i_regs->regmap,dops[i].rt1,ccadj_,reglist);
37387d8b 2916 break;
2917 case 0x21: // LH
535d208a 2918 if(!c||memtarget) {
2919 if(!dummy) {
37387d8b 2920 int a = tl;
2921 if (!c) a = addr;
2922 if (fastio_reg_override >= 0)
2923 a = fastio_reg_override;
2924 if (offset_reg >= 0)
2925 emit_ldrsh_dualindexed(offset_reg, a, tl);
2926 else
2927 emit_movswl_indexed(0, a, tl);
57871462 2928 }
535d208a 2929 if(jaddr)
2330734f 2930 add_stub_r(LOADH_STUB,jaddr,out,i,addr,i_regs,ccadj_,reglist);
57871462 2931 }
535d208a 2932 else
2330734f 2933 inline_readstub(LOADH_STUB,i,constmap[i][s]+offset,i_regs->regmap,dops[i].rt1,ccadj_,reglist);
37387d8b 2934 break;
2935 case 0x23: // LW
535d208a 2936 if(!c||memtarget) {
2937 if(!dummy) {
37387d8b 2938 int a = addr;
2939 if (fastio_reg_override >= 0)
2940 a = fastio_reg_override;
2941 do_load_word(a, tl, offset_reg);
57871462 2942 }
535d208a 2943 if(jaddr)
2330734f 2944 add_stub_r(LOADW_STUB,jaddr,out,i,addr,i_regs,ccadj_,reglist);
57871462 2945 }
535d208a 2946 else
2330734f 2947 inline_readstub(LOADW_STUB,i,constmap[i][s]+offset,i_regs->regmap,dops[i].rt1,ccadj_,reglist);
37387d8b 2948 break;
2949 case 0x24: // LBU
535d208a 2950 if(!c||memtarget) {
2951 if(!dummy) {
37387d8b 2952 int a = tl;
2953 if (!c) a = addr;
2954 if (fastio_reg_override >= 0)
2955 a = fastio_reg_override;
b1570849 2956
37387d8b 2957 if (offset_reg >= 0)
2958 emit_ldrb_dualindexed(offset_reg, a, tl);
2959 else
2960 emit_movzbl_indexed(0, a, tl);
57871462 2961 }
535d208a 2962 if(jaddr)
2330734f 2963 add_stub_r(LOADBU_STUB,jaddr,out,i,addr,i_regs,ccadj_,reglist);
57871462 2964 }
535d208a 2965 else
2330734f 2966 inline_readstub(LOADBU_STUB,i,constmap[i][s]+offset,i_regs->regmap,dops[i].rt1,ccadj_,reglist);
37387d8b 2967 break;
2968 case 0x25: // LHU
535d208a 2969 if(!c||memtarget) {
2970 if(!dummy) {
37387d8b 2971 int a = tl;
2972 if(!c) a = addr;
2973 if (fastio_reg_override >= 0)
2974 a = fastio_reg_override;
2975 if (offset_reg >= 0)
2976 emit_ldrh_dualindexed(offset_reg, a, tl);
2977 else
2978 emit_movzwl_indexed(0, a, tl);
57871462 2979 }
535d208a 2980 if(jaddr)
2330734f 2981 add_stub_r(LOADHU_STUB,jaddr,out,i,addr,i_regs,ccadj_,reglist);
57871462 2982 }
535d208a 2983 else
2330734f 2984 inline_readstub(LOADHU_STUB,i,constmap[i][s]+offset,i_regs->regmap,dops[i].rt1,ccadj_,reglist);
37387d8b 2985 break;
2986 case 0x27: // LWU
2987 case 0x37: // LD
2988 default:
9c45ca93 2989 assert(0);
57871462 2990 }
535d208a 2991 }
37387d8b 2992 if (fastio_reg_override == HOST_TEMPREG || offset_reg == HOST_TEMPREG)
d1e4ebd9 2993 host_tempreg_release();
57871462 2994}
2995
2996#ifndef loadlr_assemble
2330734f 2997static void loadlr_assemble(int i, const struct regstat *i_regs, int ccadj_)
57871462 2998{
3968e69e 2999 int s,tl,temp,temp2,addr;
3000 int offset;
3001 void *jaddr=0;
3002 int memtarget=0,c=0;
37387d8b 3003 int offset_reg = -1;
3004 int fastio_reg_override = -1;
81dbbf4c 3005 u_int reglist=get_host_reglist(i_regs->regmap);
cf95b4f0 3006 tl=get_reg(i_regs->regmap,dops[i].rt1);
3007 s=get_reg(i_regs->regmap,dops[i].rs1);
9de8a0c3 3008 temp=get_reg_temp(i_regs->regmap);
3968e69e 3009 temp2=get_reg(i_regs->regmap,FTEMP);
3010 addr=get_reg(i_regs->regmap,AGEN1+(i&1));
3011 assert(addr<0);
3012 offset=imm[i];
3968e69e 3013 reglist|=1<<temp;
3014 if(offset||s<0||c) addr=temp2;
3015 else addr=s;
3016 if(s>=0) {
3017 c=(i_regs->wasconst>>s)&1;
3018 if(c) {
3019 memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
3020 }
3021 }
3022 if(!c) {
3023 emit_shlimm(addr,3,temp);
cf95b4f0 3024 if (dops[i].opcode==0x22||dops[i].opcode==0x26) {
3968e69e 3025 emit_andimm(addr,0xFFFFFFFC,temp2); // LWL/LWR
3026 }else{
3027 emit_andimm(addr,0xFFFFFFF8,temp2); // LDL/LDR
3028 }
37387d8b 3029 jaddr = emit_fastpath_cmp_jump(i, i_regs, temp2,
3030 &offset_reg, &fastio_reg_override);
3968e69e 3031 }
3032 else {
37387d8b 3033 if (ram_offset && memtarget) {
3034 offset_reg = get_ro_reg(i_regs, 0);
3968e69e 3035 }
cf95b4f0 3036 if (dops[i].opcode==0x22||dops[i].opcode==0x26) {
3968e69e 3037 emit_movimm(((constmap[i][s]+offset)<<3)&24,temp); // LWL/LWR
3038 }else{
3039 emit_movimm(((constmap[i][s]+offset)<<3)&56,temp); // LDL/LDR
3040 }
3041 }
cf95b4f0 3042 if (dops[i].opcode==0x22||dops[i].opcode==0x26) { // LWL/LWR
3968e69e 3043 if(!c||memtarget) {
37387d8b 3044 int a = temp2;
3045 if (fastio_reg_override >= 0)
3046 a = fastio_reg_override;
3047 do_load_word(a, temp2, offset_reg);
3048 if (fastio_reg_override == HOST_TEMPREG || offset_reg == HOST_TEMPREG)
3049 host_tempreg_release();
2330734f 3050 if(jaddr) add_stub_r(LOADW_STUB,jaddr,out,i,temp2,i_regs,ccadj_,reglist);
3968e69e 3051 }
3052 else
2330734f 3053 inline_readstub(LOADW_STUB,i,(constmap[i][s]+offset)&0xFFFFFFFC,i_regs->regmap,FTEMP,ccadj_,reglist);
cf95b4f0 3054 if(dops[i].rt1) {
3968e69e 3055 assert(tl>=0);
3056 emit_andimm(temp,24,temp);
cf95b4f0 3057 if (dops[i].opcode==0x22) // LWL
3968e69e 3058 emit_xorimm(temp,24,temp);
3059 host_tempreg_acquire();
3060 emit_movimm(-1,HOST_TEMPREG);
cf95b4f0 3061 if (dops[i].opcode==0x26) {
3968e69e 3062 emit_shr(temp2,temp,temp2);
3063 emit_bic_lsr(tl,HOST_TEMPREG,temp,tl);
3064 }else{
3065 emit_shl(temp2,temp,temp2);
3066 emit_bic_lsl(tl,HOST_TEMPREG,temp,tl);
3067 }
3068 host_tempreg_release();
3069 emit_or(temp2,tl,tl);
3070 }
cf95b4f0 3071 //emit_storereg(dops[i].rt1,tl); // DEBUG
3968e69e 3072 }
cf95b4f0 3073 if (dops[i].opcode==0x1A||dops[i].opcode==0x1B) { // LDL/LDR
3968e69e 3074 assert(0);
3075 }
57871462 3076}
3077#endif
3078
2330734f 3079static void store_assemble(int i, const struct regstat *i_regs, int ccadj_)
57871462 3080{
9c45ca93 3081 int s,tl;
57871462 3082 int addr,temp;
3083 int offset;
b14b6a8f 3084 void *jaddr=0;
37387d8b 3085 enum stub_type type=0;
666a299d 3086 int memtarget=0,c=0;
57871462 3087 int agr=AGEN1+(i&1);
37387d8b 3088 int offset_reg = -1;
3089 int fastio_reg_override = -1;
81dbbf4c 3090 u_int reglist=get_host_reglist(i_regs->regmap);
cf95b4f0 3091 tl=get_reg(i_regs->regmap,dops[i].rs2);
3092 s=get_reg(i_regs->regmap,dops[i].rs1);
57871462 3093 temp=get_reg(i_regs->regmap,agr);
9de8a0c3 3094 if(temp<0) temp=get_reg_temp(i_regs->regmap);
57871462 3095 offset=imm[i];
3096 if(s>=0) {
3097 c=(i_regs->wasconst>>s)&1;
af4ee1fe 3098 if(c) {
3099 memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
af4ee1fe 3100 }
57871462 3101 }
3102 assert(tl>=0);
3103 assert(temp>=0);
57871462 3104 if(i_regs->regmap[HOST_CCREG]==CCREG) reglist&=~(1<<HOST_CCREG);
3105 if(offset||s<0||c) addr=temp;
3106 else addr=s;
37387d8b 3107 if (!c) {
3108 jaddr = emit_fastpath_cmp_jump(i, i_regs, addr,
3109 &offset_reg, &fastio_reg_override);
1edfcc68 3110 }
37387d8b 3111 else if (ram_offset && memtarget) {
3112 offset_reg = get_ro_reg(i_regs, 0);
57871462 3113 }
3114
37387d8b 3115 switch (dops[i].opcode) {
3116 case 0x28: // SB
57871462 3117 if(!c||memtarget) {
37387d8b 3118 int a = temp;
3119 if (!c) a = addr;
3120 if (fastio_reg_override >= 0)
3121 a = fastio_reg_override;
3122 do_store_byte(a, tl, offset_reg);
3123 }
3124 type = STOREB_STUB;
3125 break;
3126 case 0x29: // SH
57871462 3127 if(!c||memtarget) {
37387d8b 3128 int a = temp;
3129 if (!c) a = addr;
3130 if (fastio_reg_override >= 0)
3131 a = fastio_reg_override;
3132 do_store_hword(a, 0, tl, offset_reg, 1);
3133 }
3134 type = STOREH_STUB;
3135 break;
3136 case 0x2B: // SW
dadf55f2 3137 if(!c||memtarget) {
37387d8b 3138 int a = addr;
3139 if (fastio_reg_override >= 0)
3140 a = fastio_reg_override;
3141 do_store_word(a, 0, tl, offset_reg, 1);
3142 }
3143 type = STOREW_STUB;
3144 break;
3145 case 0x3F: // SD
3146 default:
9c45ca93 3147 assert(0);
57871462 3148 }
37387d8b 3149 if (fastio_reg_override == HOST_TEMPREG || offset_reg == HOST_TEMPREG)
d1e4ebd9 3150 host_tempreg_release();
b96d3df7 3151 if(jaddr) {
3152 // PCSX store handlers don't check invcode again
3153 reglist|=1<<addr;
2330734f 3154 add_stub_r(type,jaddr,out,i,addr,i_regs,ccadj_,reglist);
b96d3df7 3155 jaddr=0;
3156 }
cf95b4f0 3157 if(!(i_regs->waswritten&(1<<dops[i].rs1)) && !HACK_ENABLED(NDHACK_NO_SMC_CHECK)) {
57871462 3158 if(!c||memtarget) {
3159 #ifdef DESTRUCTIVE_SHIFT
3160 // The x86 shift operation is 'destructive'; it overwrites the
3161 // source register, so we need to make a copy first and use that.
3162 addr=temp;
3163 #endif
3164 #if defined(HOST_IMM8)
3165 int ir=get_reg(i_regs->regmap,INVCP);
3166 assert(ir>=0);
3167 emit_cmpmem_indexedsr12_reg(ir,addr,1);
3168 #else
643aeae3 3169 emit_cmpmem_indexedsr12_imm(invalid_code,addr,1);
57871462 3170 #endif
0bbd1454 3171 #if defined(HAVE_CONDITIONAL_CALL) && !defined(DESTRUCTIVE_SHIFT)
3172 emit_callne(invalidate_addr_reg[addr]);
3173 #else
b14b6a8f 3174 void *jaddr2 = out;
57871462 3175 emit_jne(0);
b14b6a8f 3176 add_stub(INVCODE_STUB,jaddr2,out,reglist|(1<<HOST_CCREG),addr,0,0,0);
0bbd1454 3177 #endif
57871462 3178 }
3179 }
7a518516 3180 u_int addr_val=constmap[i][s]+offset;
3eaa7048 3181 if(jaddr) {
2330734f 3182 add_stub_r(type,jaddr,out,i,addr,i_regs,ccadj_,reglist);
3eaa7048 3183 } else if(c&&!memtarget) {
2330734f 3184 inline_writestub(type,i,addr_val,i_regs->regmap,dops[i].rs2,ccadj_,reglist);
7a518516 3185 }
3186 // basic current block modification detection..
3187 // not looking back as that should be in mips cache already
3968e69e 3188 // (see Spyro2 title->attract mode)
7a518516 3189 if(c&&start+i*4<addr_val&&addr_val<start+slen*4) {
c43b5311 3190 SysPrintf("write to %08x hits block %08x, pc=%08x\n",addr_val,start,start+i*4);
7a518516 3191 assert(i_regs->regmap==regs[i].regmap); // not delay slot
3192 if(i_regs->regmap==regs[i].regmap) {
ad49de89 3193 load_all_consts(regs[i].regmap_entry,regs[i].wasdirty,i);
3194 wb_dirtys(regs[i].regmap_entry,regs[i].wasdirty);
7a518516 3195 emit_movimm(start+i*4+4,0);
643aeae3 3196 emit_writeword(0,&pcaddr);
d1e4ebd9 3197 emit_addimm(HOST_CCREG,2,HOST_CCREG);
2a014d73 3198 emit_far_call(get_addr_ht);
d1e4ebd9 3199 emit_jmpreg(0);
7a518516 3200 }
3eaa7048 3201 }
57871462 3202}
3203
2330734f 3204static void storelr_assemble(int i, const struct regstat *i_regs, int ccadj_)
57871462 3205{
9c45ca93 3206 int s,tl;
57871462 3207 int temp;
57871462 3208 int offset;
b14b6a8f 3209 void *jaddr=0;
37387d8b 3210 void *case1, *case23, *case3;
df4dc2b1 3211 void *done0, *done1, *done2;
af4ee1fe 3212 int memtarget=0,c=0;
fab5d06d 3213 int agr=AGEN1+(i&1);
37387d8b 3214 int offset_reg = -1;
81dbbf4c 3215 u_int reglist=get_host_reglist(i_regs->regmap);
cf95b4f0 3216 tl=get_reg(i_regs->regmap,dops[i].rs2);
3217 s=get_reg(i_regs->regmap,dops[i].rs1);
fab5d06d 3218 temp=get_reg(i_regs->regmap,agr);
9de8a0c3 3219 if(temp<0) temp=get_reg_temp(i_regs->regmap);
57871462 3220 offset=imm[i];
3221 if(s>=0) {
3222 c=(i_regs->isconst>>s)&1;
af4ee1fe 3223 if(c) {
3224 memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
af4ee1fe 3225 }
57871462 3226 }
3227 assert(tl>=0);
535d208a 3228 assert(temp>=0);
1edfcc68 3229 if(!c) {
3230 emit_cmpimm(s<0||offset?temp:s,RAM_SIZE);
3231 if(!offset&&s!=temp) emit_mov(s,temp);
b14b6a8f 3232 jaddr=out;
1edfcc68 3233 emit_jno(0);
3234 }
3235 else
3236 {
cf95b4f0 3237 if(!memtarget||!dops[i].rs1) {
b14b6a8f 3238 jaddr=out;
535d208a 3239 emit_jmp(0);
57871462 3240 }
535d208a 3241 }
37387d8b 3242 if (ram_offset)
3243 offset_reg = get_ro_reg(i_regs, 0);
535d208a 3244
cf95b4f0 3245 if (dops[i].opcode==0x2C||dops[i].opcode==0x2D) { // SDL/SDR
9c45ca93 3246 assert(0);
535d208a 3247 }
57871462 3248
535d208a 3249 emit_testimm(temp,2);
37387d8b 3250 case23=out;
535d208a 3251 emit_jne(0);
3252 emit_testimm(temp,1);
df4dc2b1 3253 case1=out;
535d208a 3254 emit_jne(0);
3255 // 0
37387d8b 3256 if (dops[i].opcode == 0x2A) { // SWL
3257 // Write msb into least significant byte
3258 if (dops[i].rs2) emit_rorimm(tl, 24, tl);
3259 do_store_byte(temp, tl, offset_reg);
3260 if (dops[i].rs2) emit_rorimm(tl, 8, tl);
535d208a 3261 }
37387d8b 3262 else if (dops[i].opcode == 0x2E) { // SWR
3263 // Write entire word
3264 do_store_word(temp, 0, tl, offset_reg, 1);
535d208a 3265 }
37387d8b 3266 done0 = out;
535d208a 3267 emit_jmp(0);
3268 // 1
df4dc2b1 3269 set_jump_target(case1, out);
37387d8b 3270 if (dops[i].opcode == 0x2A) { // SWL
3271 // Write two msb into two least significant bytes
3272 if (dops[i].rs2) emit_rorimm(tl, 16, tl);
3273 do_store_hword(temp, -1, tl, offset_reg, 0);
3274 if (dops[i].rs2) emit_rorimm(tl, 16, tl);
535d208a 3275 }
37387d8b 3276 else if (dops[i].opcode == 0x2E) { // SWR
3277 // Write 3 lsb into three most significant bytes
3278 do_store_byte(temp, tl, offset_reg);
3279 if (dops[i].rs2) emit_rorimm(tl, 8, tl);
3280 do_store_hword(temp, 1, tl, offset_reg, 0);
3281 if (dops[i].rs2) emit_rorimm(tl, 24, tl);
535d208a 3282 }
df4dc2b1 3283 done1=out;
535d208a 3284 emit_jmp(0);
37387d8b 3285 // 2,3
3286 set_jump_target(case23, out);
535d208a 3287 emit_testimm(temp,1);
37387d8b 3288 case3 = out;
535d208a 3289 emit_jne(0);
37387d8b 3290 // 2
cf95b4f0 3291 if (dops[i].opcode==0x2A) { // SWL
37387d8b 3292 // Write 3 msb into three least significant bytes
3293 if (dops[i].rs2) emit_rorimm(tl, 8, tl);
3294 do_store_hword(temp, -2, tl, offset_reg, 1);
3295 if (dops[i].rs2) emit_rorimm(tl, 16, tl);
3296 do_store_byte(temp, tl, offset_reg);
3297 if (dops[i].rs2) emit_rorimm(tl, 8, tl);
535d208a 3298 }
37387d8b 3299 else if (dops[i].opcode == 0x2E) { // SWR
3300 // Write two lsb into two most significant bytes
3301 do_store_hword(temp, 0, tl, offset_reg, 1);
535d208a 3302 }
37387d8b 3303 done2 = out;
535d208a 3304 emit_jmp(0);
3305 // 3
df4dc2b1 3306 set_jump_target(case3, out);
37387d8b 3307 if (dops[i].opcode == 0x2A) { // SWL
3308 do_store_word(temp, -3, tl, offset_reg, 0);
535d208a 3309 }
37387d8b 3310 else if (dops[i].opcode == 0x2E) { // SWR
3311 do_store_byte(temp, tl, offset_reg);
535d208a 3312 }
df4dc2b1 3313 set_jump_target(done0, out);
3314 set_jump_target(done1, out);
3315 set_jump_target(done2, out);
37387d8b 3316 if (offset_reg == HOST_TEMPREG)
3317 host_tempreg_release();
535d208a 3318 if(!c||!memtarget)
2330734f 3319 add_stub_r(STORELR_STUB,jaddr,out,i,temp,i_regs,ccadj_,reglist);
cf95b4f0 3320 if(!(i_regs->waswritten&(1<<dops[i].rs1)) && !HACK_ENABLED(NDHACK_NO_SMC_CHECK)) {
57871462 3321 #if defined(HOST_IMM8)
3322 int ir=get_reg(i_regs->regmap,INVCP);
3323 assert(ir>=0);
3324 emit_cmpmem_indexedsr12_reg(ir,temp,1);
3325 #else
643aeae3 3326 emit_cmpmem_indexedsr12_imm(invalid_code,temp,1);
57871462 3327 #endif
535d208a 3328 #if defined(HAVE_CONDITIONAL_CALL) && !defined(DESTRUCTIVE_SHIFT)
3329 emit_callne(invalidate_addr_reg[temp]);
3330 #else
b14b6a8f 3331 void *jaddr2 = out;
57871462 3332 emit_jne(0);
b14b6a8f 3333 add_stub(INVCODE_STUB,jaddr2,out,reglist|(1<<HOST_CCREG),temp,0,0,0);
535d208a 3334 #endif
57871462 3335 }
57871462 3336}
3337
2330734f 3338static void cop0_assemble(int i, const struct regstat *i_regs, int ccadj_)
8062d65a 3339{
cf95b4f0 3340 if(dops[i].opcode2==0) // MFC0
8062d65a 3341 {
cf95b4f0 3342 signed char t=get_reg(i_regs->regmap,dops[i].rt1);
8062d65a 3343 u_int copr=(source[i]>>11)&0x1f;
3344 //assert(t>=0); // Why does this happen? OOT is weird
cf95b4f0 3345 if(t>=0&&dops[i].rt1!=0) {
8062d65a 3346 emit_readword(&reg_cop0[copr],t);
3347 }
3348 }
cf95b4f0 3349 else if(dops[i].opcode2==4) // MTC0
8062d65a 3350 {
cf95b4f0 3351 signed char s=get_reg(i_regs->regmap,dops[i].rs1);
8062d65a 3352 char copr=(source[i]>>11)&0x1f;
3353 assert(s>=0);
cf95b4f0 3354 wb_register(dops[i].rs1,i_regs->regmap,i_regs->dirty);
8062d65a 3355 if(copr==9||copr==11||copr==12||copr==13) {
3356 emit_readword(&last_count,HOST_TEMPREG);
3357 emit_loadreg(CCREG,HOST_CCREG); // TODO: do proper reg alloc
3358 emit_add(HOST_CCREG,HOST_TEMPREG,HOST_CCREG);
2330734f 3359 emit_addimm(HOST_CCREG,ccadj_,HOST_CCREG);
8062d65a 3360 emit_writeword(HOST_CCREG,&Count);
3361 }
3362 // What a mess. The status register (12) can enable interrupts,
3363 // so needs a special case to handle a pending interrupt.
3364 // The interrupt must be taken immediately, because a subsequent
3365 // instruction might disable interrupts again.
3366 if(copr==12||copr==13) {
3367 if (is_delayslot) {
3368 // burn cycles to cause cc_interrupt, which will
3369 // reschedule next_interupt. Relies on CCREG from above.
3370 assem_debug("MTC0 DS %d\n", copr);
3371 emit_writeword(HOST_CCREG,&last_count);
3372 emit_movimm(0,HOST_CCREG);
3373 emit_storereg(CCREG,HOST_CCREG);
cf95b4f0 3374 emit_loadreg(dops[i].rs1,1);
8062d65a 3375 emit_movimm(copr,0);
2a014d73 3376 emit_far_call(pcsx_mtc0_ds);
cf95b4f0 3377 emit_loadreg(dops[i].rs1,s);
8062d65a 3378 return;
3379 }
3380 emit_movimm(start+i*4+4,HOST_TEMPREG);
3381 emit_writeword(HOST_TEMPREG,&pcaddr);
3382 emit_movimm(0,HOST_TEMPREG);
3383 emit_writeword(HOST_TEMPREG,&pending_exception);
3384 }
8062d65a 3385 if(s==HOST_CCREG)
cf95b4f0 3386 emit_loadreg(dops[i].rs1,1);
8062d65a 3387 else if(s!=1)
3388 emit_mov(s,1);
3389 emit_movimm(copr,0);
2a014d73 3390 emit_far_call(pcsx_mtc0);
8062d65a 3391 if(copr==9||copr==11||copr==12||copr==13) {
3392 emit_readword(&Count,HOST_CCREG);
3393 emit_readword(&next_interupt,HOST_TEMPREG);
2330734f 3394 emit_addimm(HOST_CCREG,-ccadj_,HOST_CCREG);
8062d65a 3395 emit_sub(HOST_CCREG,HOST_TEMPREG,HOST_CCREG);
3396 emit_writeword(HOST_TEMPREG,&last_count);
3397 emit_storereg(CCREG,HOST_CCREG);
3398 }
3399 if(copr==12||copr==13) {
3400 assert(!is_delayslot);
3401 emit_readword(&pending_exception,14);
3402 emit_test(14,14);
d1e4ebd9 3403 void *jaddr = out;
3404 emit_jeq(0);
3405 emit_readword(&pcaddr, 0);
3406 emit_addimm(HOST_CCREG,2,HOST_CCREG);
2a014d73 3407 emit_far_call(get_addr_ht);
d1e4ebd9 3408 emit_jmpreg(0);
3409 set_jump_target(jaddr, out);
8062d65a 3410 }
cf95b4f0 3411 emit_loadreg(dops[i].rs1,s);
8062d65a 3412 }
3413 else
3414 {
cf95b4f0 3415 assert(dops[i].opcode2==0x10);
8062d65a 3416 //if((source[i]&0x3f)==0x10) // RFE
3417 {
3418 emit_readword(&Status,0);
3419 emit_andimm(0,0x3c,1);
3420 emit_andimm(0,~0xf,0);
3421 emit_orrshr_imm(1,2,0);
3422 emit_writeword(0,&Status);
3423 }
3424 }
3425}
3426
2330734f 3427static void cop1_unusable(int i, const struct regstat *i_regs)
8062d65a 3428{
3429 // XXX: should just just do the exception instead
3430 //if(!cop1_usable)
3431 {
3432 void *jaddr=out;
3433 emit_jmp(0);
3434 add_stub_r(FP_STUB,jaddr,out,i,0,i_regs,is_delayslot,0);
3435 }
3436}
3437
2330734f 3438static void cop1_assemble(int i, const struct regstat *i_regs)
8062d65a 3439{
3440 cop1_unusable(i, i_regs);
3441}
3442
2330734f 3443static void c1ls_assemble(int i, const struct regstat *i_regs)
57871462 3444{
3d624f89 3445 cop1_unusable(i, i_regs);
57871462 3446}
3447
8062d65a 3448// FP_STUB
3449static void do_cop1stub(int n)
3450{
3451 literal_pool(256);
3452 assem_debug("do_cop1stub %x\n",start+stubs[n].a*4);
3453 set_jump_target(stubs[n].addr, out);
3454 int i=stubs[n].a;
3455// int rs=stubs[n].b;
3456 struct regstat *i_regs=(struct regstat *)stubs[n].c;
3457 int ds=stubs[n].d;
3458 if(!ds) {
3459 load_all_consts(regs[i].regmap_entry,regs[i].wasdirty,i);
3460 //if(i_regs!=&regs[i]) printf("oops: regs[i]=%x i_regs=%x",(int)&regs[i],(int)i_regs);
3461 }
3462 //else {printf("fp exception in delay slot\n");}
3463 wb_dirtys(i_regs->regmap_entry,i_regs->wasdirty);
3464 if(regs[i].regmap_entry[HOST_CCREG]!=CCREG) emit_loadreg(CCREG,HOST_CCREG);
3465 emit_movimm(start+(i-ds)*4,EAX); // Get PC
2330734f 3466 emit_addimm(HOST_CCREG,ccadj[i],HOST_CCREG); // CHECK: is this right? There should probably be an extra cycle...
2a014d73 3467 emit_far_jump(ds?fp_exception_ds:fp_exception);
8062d65a 3468}
3469
e3c6bdb5 3470static int cop2_is_stalling_op(int i, int *cycles)
3471{
cf95b4f0 3472 if (dops[i].opcode == 0x3a) { // SWC2
e3c6bdb5 3473 *cycles = 0;
3474 return 1;
3475 }
cf95b4f0 3476 if (dops[i].itype == COP2 && (dops[i].opcode2 == 0 || dops[i].opcode2 == 2)) { // MFC2/CFC2
e3c6bdb5 3477 *cycles = 0;
3478 return 1;
3479 }
cf95b4f0 3480 if (dops[i].itype == C2OP) {
e3c6bdb5 3481 *cycles = gte_cycletab[source[i] & 0x3f];
3482 return 1;
3483 }
3484 // ... what about MTC2/CTC2/LWC2?
3485 return 0;
3486}
3487
3488#if 0
3489static void log_gte_stall(int stall, u_int cycle)
3490{
3491 if ((u_int)stall <= 44)
3492 printf("x stall %2d %u\n", stall, cycle + last_count);
e3c6bdb5 3493}
3494
3495static void emit_log_gte_stall(int i, int stall, u_int reglist)
3496{
3497 save_regs(reglist);
3498 if (stall > 0)
3499 emit_movimm(stall, 0);
3500 else
3501 emit_mov(HOST_TEMPREG, 0);
2330734f 3502 emit_addimm(HOST_CCREG, ccadj[i], 1);
e3c6bdb5 3503 emit_far_call(log_gte_stall);
3504 restore_regs(reglist);
3505}
3506#endif
3507
32631e6a 3508static void cop2_do_stall_check(u_int op, int i, const struct regstat *i_regs, u_int reglist)
81dbbf4c 3509{
e3c6bdb5 3510 int j = i, other_gte_op_cycles = -1, stall = -MAXBLOCK, cycles_passed;
3511 int rtmp = reglist_find_free(reglist);
3512
32631e6a 3513 if (HACK_ENABLED(NDHACK_NO_STALLS))
81dbbf4c 3514 return;
81dbbf4c 3515 if (get_reg(i_regs->regmap, CCREG) != HOST_CCREG) {
3516 // happens occasionally... cc evicted? Don't bother then
3517 //printf("no cc %08x\n", start + i*4);
3518 return;
3519 }
cf95b4f0 3520 if (!dops[i].bt) {
e3c6bdb5 3521 for (j = i - 1; j >= 0; j--) {
cf95b4f0 3522 //if (dops[j].is_ds) break;
3523 if (cop2_is_stalling_op(j, &other_gte_op_cycles) || dops[j].bt)
e3c6bdb5 3524 break;
2330734f 3525 if (j > 0 && ccadj[j - 1] > ccadj[j])
3526 break;
e3c6bdb5 3527 }
32631e6a 3528 j = max(j, 0);
e3c6bdb5 3529 }
2330734f 3530 cycles_passed = ccadj[i] - ccadj[j];
e3c6bdb5 3531 if (other_gte_op_cycles >= 0)
3532 stall = other_gte_op_cycles - cycles_passed;
3533 else if (cycles_passed >= 44)
3534 stall = 0; // can't stall
3535 if (stall == -MAXBLOCK && rtmp >= 0) {
3536 // unknown stall, do the expensive runtime check
32631e6a 3537 assem_debug("; cop2_do_stall_check\n");
e3c6bdb5 3538#if 0 // too slow
3539 save_regs(reglist);
3540 emit_movimm(gte_cycletab[op], 0);
2330734f 3541 emit_addimm(HOST_CCREG, ccadj[i], 1);
e3c6bdb5 3542 emit_far_call(call_gteStall);
3543 restore_regs(reglist);
3544#else
3545 host_tempreg_acquire();
3546 emit_readword(&psxRegs.gteBusyCycle, rtmp);
2330734f 3547 emit_addimm(rtmp, -ccadj[i], rtmp);
e3c6bdb5 3548 emit_sub(rtmp, HOST_CCREG, HOST_TEMPREG);
3549 emit_cmpimm(HOST_TEMPREG, 44);
3550 emit_cmovb_reg(rtmp, HOST_CCREG);
3551 //emit_log_gte_stall(i, 0, reglist);
3552 host_tempreg_release();
3553#endif
3554 }
3555 else if (stall > 0) {
3556 //emit_log_gte_stall(i, stall, reglist);
3557 emit_addimm(HOST_CCREG, stall, HOST_CCREG);
3558 }
3559
3560 // save gteBusyCycle, if needed
3561 if (gte_cycletab[op] == 0)
3562 return;
3563 other_gte_op_cycles = -1;
3564 for (j = i + 1; j < slen; j++) {
3565 if (cop2_is_stalling_op(j, &other_gte_op_cycles))
3566 break;
fe807a8a 3567 if (dops[j].is_jump) {
e3c6bdb5 3568 // check ds
3569 if (j + 1 < slen && cop2_is_stalling_op(j + 1, &other_gte_op_cycles))
3570 j++;
3571 break;
3572 }
3573 }
3574 if (other_gte_op_cycles >= 0)
3575 // will handle stall when assembling that op
3576 return;
2330734f 3577 cycles_passed = ccadj[min(j, slen -1)] - ccadj[i];
e3c6bdb5 3578 if (cycles_passed >= 44)
3579 return;
3580 assem_debug("; save gteBusyCycle\n");
3581 host_tempreg_acquire();
3582#if 0
3583 emit_readword(&last_count, HOST_TEMPREG);
3584 emit_add(HOST_TEMPREG, HOST_CCREG, HOST_TEMPREG);
2330734f 3585 emit_addimm(HOST_TEMPREG, ccadj[i], HOST_TEMPREG);
e3c6bdb5 3586 emit_addimm(HOST_TEMPREG, gte_cycletab[op]), HOST_TEMPREG);
3587 emit_writeword(HOST_TEMPREG, &psxRegs.gteBusyCycle);
3588#else
2330734f 3589 emit_addimm(HOST_CCREG, ccadj[i] + gte_cycletab[op], HOST_TEMPREG);
e3c6bdb5 3590 emit_writeword(HOST_TEMPREG, &psxRegs.gteBusyCycle);
3591#endif
3592 host_tempreg_release();
81dbbf4c 3593}
3594
32631e6a 3595static int is_mflohi(int i)
3596{
cf95b4f0 3597 return (dops[i].itype == MOV && (dops[i].rs1 == HIREG || dops[i].rs1 == LOREG));
32631e6a 3598}
3599
3600static int check_multdiv(int i, int *cycles)
3601{
cf95b4f0 3602 if (dops[i].itype != MULTDIV)
32631e6a 3603 return 0;
cf95b4f0 3604 if (dops[i].opcode2 == 0x18 || dops[i].opcode2 == 0x19) // MULT(U)
32631e6a 3605 *cycles = 11; // approx from 7 11 14
3606 else
3607 *cycles = 37;
3608 return 1;
3609}
3610
2330734f 3611static void multdiv_prepare_stall(int i, const struct regstat *i_regs, int ccadj_)
32631e6a 3612{
3613 int j, found = 0, c = 0;
3614 if (HACK_ENABLED(NDHACK_NO_STALLS))
3615 return;
3616 if (get_reg(i_regs->regmap, CCREG) != HOST_CCREG) {
3617 // happens occasionally... cc evicted? Don't bother then
3618 return;
3619 }
3620 for (j = i + 1; j < slen; j++) {
cf95b4f0 3621 if (dops[j].bt)
32631e6a 3622 break;
3623 if ((found = is_mflohi(j)))
3624 break;
fe807a8a 3625 if (dops[j].is_jump) {
32631e6a 3626 // check ds
3627 if (j + 1 < slen && (found = is_mflohi(j + 1)))
3628 j++;
3629 break;
3630 }
3631 }
3632 if (found)
3633 // handle all in multdiv_do_stall()
3634 return;
3635 check_multdiv(i, &c);
3636 assert(c > 0);
3637 assem_debug("; muldiv prepare stall %d\n", c);
3638 host_tempreg_acquire();
2330734f 3639 emit_addimm(HOST_CCREG, ccadj_ + c, HOST_TEMPREG);
32631e6a 3640 emit_writeword(HOST_TEMPREG, &psxRegs.muldivBusyCycle);
3641 host_tempreg_release();
3642}
3643
3644static void multdiv_do_stall(int i, const struct regstat *i_regs)
3645{
3646 int j, known_cycles = 0;
3647 u_int reglist = get_host_reglist(i_regs->regmap);
9de8a0c3 3648 int rtmp = get_reg_temp(i_regs->regmap);
32631e6a 3649 if (rtmp < 0)
3650 rtmp = reglist_find_free(reglist);
3651 if (HACK_ENABLED(NDHACK_NO_STALLS))
3652 return;
3653 if (get_reg(i_regs->regmap, CCREG) != HOST_CCREG || rtmp < 0) {
3654 // happens occasionally... cc evicted? Don't bother then
3655 //printf("no cc/rtmp %08x\n", start + i*4);
3656 return;
3657 }
cf95b4f0 3658 if (!dops[i].bt) {
32631e6a 3659 for (j = i - 1; j >= 0; j--) {
cf95b4f0 3660 if (dops[j].is_ds) break;
2330734f 3661 if (check_multdiv(j, &known_cycles))
32631e6a 3662 break;
3663 if (is_mflohi(j))
3664 // already handled by this op
3665 return;
2330734f 3666 if (dops[j].bt || (j > 0 && ccadj[j - 1] > ccadj[j]))
3667 break;
32631e6a 3668 }
3669 j = max(j, 0);
3670 }
3671 if (known_cycles > 0) {
2330734f 3672 known_cycles -= ccadj[i] - ccadj[j];
32631e6a 3673 assem_debug("; muldiv stall resolved %d\n", known_cycles);
3674 if (known_cycles > 0)
3675 emit_addimm(HOST_CCREG, known_cycles, HOST_CCREG);
3676 return;
3677 }
3678 assem_debug("; muldiv stall unresolved\n");
3679 host_tempreg_acquire();
3680 emit_readword(&psxRegs.muldivBusyCycle, rtmp);
2330734f 3681 emit_addimm(rtmp, -ccadj[i], rtmp);
32631e6a 3682 emit_sub(rtmp, HOST_CCREG, HOST_TEMPREG);
3683 emit_cmpimm(HOST_TEMPREG, 37);
3684 emit_cmovb_reg(rtmp, HOST_CCREG);
3685 //emit_log_gte_stall(i, 0, reglist);
3686 host_tempreg_release();
3687}
3688
8062d65a 3689static void cop2_get_dreg(u_int copr,signed char tl,signed char temp)
3690{
3691 switch (copr) {
3692 case 1:
3693 case 3:
3694 case 5:
3695 case 8:
3696 case 9:
3697 case 10:
3698 case 11:
3699 emit_readword(&reg_cop2d[copr],tl);
3700 emit_signextend16(tl,tl);
3701 emit_writeword(tl,&reg_cop2d[copr]); // hmh
3702 break;
3703 case 7:
3704 case 16:
3705 case 17:
3706 case 18:
3707 case 19:
3708 emit_readword(&reg_cop2d[copr],tl);
3709 emit_andimm(tl,0xffff,tl);
3710 emit_writeword(tl,&reg_cop2d[copr]);
3711 break;
3712 case 15:
3713 emit_readword(&reg_cop2d[14],tl); // SXY2
3714 emit_writeword(tl,&reg_cop2d[copr]);
3715 break;
3716 case 28:
3717 case 29:
3968e69e 3718 c2op_mfc2_29_assemble(tl,temp);
8062d65a 3719 break;
3720 default:
3721 emit_readword(&reg_cop2d[copr],tl);
3722 break;
3723 }
3724}
3725
3726static void cop2_put_dreg(u_int copr,signed char sl,signed char temp)
3727{
3728 switch (copr) {
3729 case 15:
3730 emit_readword(&reg_cop2d[13],temp); // SXY1
3731 emit_writeword(sl,&reg_cop2d[copr]);
3732 emit_writeword(temp,&reg_cop2d[12]); // SXY0
3733 emit_readword(&reg_cop2d[14],temp); // SXY2
3734 emit_writeword(sl,&reg_cop2d[14]);
3735 emit_writeword(temp,&reg_cop2d[13]); // SXY1
3736 break;
3737 case 28:
3738 emit_andimm(sl,0x001f,temp);
3739 emit_shlimm(temp,7,temp);
3740 emit_writeword(temp,&reg_cop2d[9]);
3741 emit_andimm(sl,0x03e0,temp);
3742 emit_shlimm(temp,2,temp);
3743 emit_writeword(temp,&reg_cop2d[10]);
3744 emit_andimm(sl,0x7c00,temp);
3745 emit_shrimm(temp,3,temp);
3746 emit_writeword(temp,&reg_cop2d[11]);
3747 emit_writeword(sl,&reg_cop2d[28]);
3748 break;
3749 case 30:
3968e69e 3750 emit_xorsar_imm(sl,sl,31,temp);
be516ebe 3751#if defined(HAVE_ARMV5) || defined(__aarch64__)
8062d65a 3752 emit_clz(temp,temp);
3753#else
3754 emit_movs(temp,HOST_TEMPREG);
3755 emit_movimm(0,temp);
3756 emit_jeq((int)out+4*4);
3757 emit_addpl_imm(temp,1,temp);
3758 emit_lslpls_imm(HOST_TEMPREG,1,HOST_TEMPREG);
3759 emit_jns((int)out-2*4);
3760#endif
3761 emit_writeword(sl,&reg_cop2d[30]);
3762 emit_writeword(temp,&reg_cop2d[31]);
3763 break;
3764 case 31:
3765 break;
3766 default:
3767 emit_writeword(sl,&reg_cop2d[copr]);
3768 break;
3769 }
3770}
3771
2330734f 3772static void c2ls_assemble(int i, const struct regstat *i_regs, int ccadj_)
b9b61529 3773{
3774 int s,tl;
3775 int ar;
3776 int offset;
1fd1aceb 3777 int memtarget=0,c=0;
b14b6a8f 3778 void *jaddr2=NULL;
3779 enum stub_type type;
b9b61529 3780 int agr=AGEN1+(i&1);
37387d8b 3781 int offset_reg = -1;
3782 int fastio_reg_override = -1;
81dbbf4c 3783 u_int reglist=get_host_reglist(i_regs->regmap);
b9b61529 3784 u_int copr=(source[i]>>16)&0x1f;
cf95b4f0 3785 s=get_reg(i_regs->regmap,dops[i].rs1);
b9b61529 3786 tl=get_reg(i_regs->regmap,FTEMP);
3787 offset=imm[i];
cf95b4f0 3788 assert(dops[i].rs1>0);
b9b61529 3789 assert(tl>=0);
b9b61529 3790
b9b61529 3791 if(i_regs->regmap[HOST_CCREG]==CCREG)
3792 reglist&=~(1<<HOST_CCREG);
3793
3794 // get the address
cf95b4f0 3795 if (dops[i].opcode==0x3a) { // SWC2
b9b61529 3796 ar=get_reg(i_regs->regmap,agr);
9de8a0c3 3797 if(ar<0) ar=get_reg_temp(i_regs->regmap);
b9b61529 3798 reglist|=1<<ar;
3799 } else { // LWC2
3800 ar=tl;
3801 }
1fd1aceb 3802 if(s>=0) c=(i_regs->wasconst>>s)&1;
3803 memtarget=c&&(((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE);
b9b61529 3804 if (!offset&&!c&&s>=0) ar=s;
3805 assert(ar>=0);
3806
32631e6a 3807 cop2_do_stall_check(0, i, i_regs, reglist);
3808
cf95b4f0 3809 if (dops[i].opcode==0x3a) { // SWC2
3968e69e 3810 cop2_get_dreg(copr,tl,-1);
1fd1aceb 3811 type=STOREW_STUB;
b9b61529 3812 }
1fd1aceb 3813 else
b9b61529 3814 type=LOADW_STUB;
1fd1aceb 3815
3816 if(c&&!memtarget) {
b14b6a8f 3817 jaddr2=out;
1fd1aceb 3818 emit_jmp(0); // inline_readstub/inline_writestub?
b9b61529 3819 }
1fd1aceb 3820 else {
3821 if(!c) {
37387d8b 3822 jaddr2 = emit_fastpath_cmp_jump(i, i_regs, ar,
3823 &offset_reg, &fastio_reg_override);
3824 }
3825 else if (ram_offset && memtarget) {
3826 offset_reg = get_ro_reg(i_regs, 0);
3827 }
3828 switch (dops[i].opcode) {
3829 case 0x32: { // LWC2
3830 int a = ar;
3831 if (fastio_reg_override >= 0)
3832 a = fastio_reg_override;
3833 do_load_word(a, tl, offset_reg);
3834 break;
1fd1aceb 3835 }
37387d8b 3836 case 0x3a: { // SWC2
1fd1aceb 3837 #ifdef DESTRUCTIVE_SHIFT
3838 if(!offset&&!c&&s>=0) emit_mov(s,ar);
3839 #endif
37387d8b 3840 int a = ar;
3841 if (fastio_reg_override >= 0)
3842 a = fastio_reg_override;
3843 do_store_word(a, 0, tl, offset_reg, 1);
3844 break;
3845 }
3846 default:
3847 assert(0);
1fd1aceb 3848 }
b9b61529 3849 }
37387d8b 3850 if (fastio_reg_override == HOST_TEMPREG || offset_reg == HOST_TEMPREG)
d1e4ebd9 3851 host_tempreg_release();
b9b61529 3852 if(jaddr2)
2330734f 3853 add_stub_r(type,jaddr2,out,i,ar,i_regs,ccadj_,reglist);
cf95b4f0 3854 if(dops[i].opcode==0x3a) // SWC2
3855 if(!(i_regs->waswritten&(1<<dops[i].rs1)) && !HACK_ENABLED(NDHACK_NO_SMC_CHECK)) {
b9b61529 3856#if defined(HOST_IMM8)
3857 int ir=get_reg(i_regs->regmap,INVCP);
3858 assert(ir>=0);
3859 emit_cmpmem_indexedsr12_reg(ir,ar,1);
3860#else
643aeae3 3861 emit_cmpmem_indexedsr12_imm(invalid_code,ar,1);
b9b61529 3862#endif
0bbd1454 3863 #if defined(HAVE_CONDITIONAL_CALL) && !defined(DESTRUCTIVE_SHIFT)
3864 emit_callne(invalidate_addr_reg[ar]);
3865 #else
b14b6a8f 3866 void *jaddr3 = out;
b9b61529 3867 emit_jne(0);
b14b6a8f 3868 add_stub(INVCODE_STUB,jaddr3,out,reglist|(1<<HOST_CCREG),ar,0,0,0);
0bbd1454 3869 #endif
b9b61529 3870 }
cf95b4f0 3871 if (dops[i].opcode==0x32) { // LWC2
d1e4ebd9 3872 host_tempreg_acquire();
b9b61529 3873 cop2_put_dreg(copr,tl,HOST_TEMPREG);
d1e4ebd9 3874 host_tempreg_release();
b9b61529 3875 }
3876}
3877
81dbbf4c 3878static void cop2_assemble(int i, const struct regstat *i_regs)
8062d65a 3879{
81dbbf4c 3880 u_int copr = (source[i]>>11) & 0x1f;
9de8a0c3 3881 signed char temp = get_reg_temp(i_regs->regmap);
81dbbf4c 3882
32631e6a 3883 if (!HACK_ENABLED(NDHACK_NO_STALLS)) {
3884 u_int reglist = reglist_exclude(get_host_reglist(i_regs->regmap), temp, -1);
cf95b4f0 3885 if (dops[i].opcode2 == 0 || dops[i].opcode2 == 2) { // MFC2/CFC2
3886 signed char tl = get_reg(i_regs->regmap, dops[i].rt1);
32631e6a 3887 reglist = reglist_exclude(reglist, tl, -1);
81dbbf4c 3888 }
32631e6a 3889 cop2_do_stall_check(0, i, i_regs, reglist);
81dbbf4c 3890 }
cf95b4f0 3891 if (dops[i].opcode2==0) { // MFC2
3892 signed char tl=get_reg(i_regs->regmap,dops[i].rt1);
3893 if(tl>=0&&dops[i].rt1!=0)
8062d65a 3894 cop2_get_dreg(copr,tl,temp);
3895 }
cf95b4f0 3896 else if (dops[i].opcode2==4) { // MTC2
3897 signed char sl=get_reg(i_regs->regmap,dops[i].rs1);
8062d65a 3898 cop2_put_dreg(copr,sl,temp);
3899 }
cf95b4f0 3900 else if (dops[i].opcode2==2) // CFC2
8062d65a 3901 {
cf95b4f0 3902 signed char tl=get_reg(i_regs->regmap,dops[i].rt1);
3903 if(tl>=0&&dops[i].rt1!=0)
8062d65a 3904 emit_readword(&reg_cop2c[copr],tl);
3905 }
cf95b4f0 3906 else if (dops[i].opcode2==6) // CTC2
8062d65a 3907 {
cf95b4f0 3908 signed char sl=get_reg(i_regs->regmap,dops[i].rs1);
8062d65a 3909 switch(copr) {
3910 case 4:
3911 case 12:
3912 case 20:
3913 case 26:
3914 case 27:
3915 case 29:
3916 case 30:
3917 emit_signextend16(sl,temp);
3918 break;
3919 case 31:
3968e69e 3920 c2op_ctc2_31_assemble(sl,temp);
8062d65a 3921 break;
3922 default:
3923 temp=sl;
3924 break;
3925 }
3926 emit_writeword(temp,&reg_cop2c[copr]);
3927 assert(sl>=0);
3928 }
3929}
3930
3968e69e 3931static void do_unalignedwritestub(int n)
3932{
3933 assem_debug("do_unalignedwritestub %x\n",start+stubs[n].a*4);
3934 literal_pool(256);
3935 set_jump_target(stubs[n].addr, out);
3936
3937 int i=stubs[n].a;
3938 struct regstat *i_regs=(struct regstat *)stubs[n].c;
3939 int addr=stubs[n].b;
3940 u_int reglist=stubs[n].e;
3941 signed char *i_regmap=i_regs->regmap;
3942 int temp2=get_reg(i_regmap,FTEMP);
3943 int rt;
cf95b4f0 3944 rt=get_reg(i_regmap,dops[i].rs2);
3968e69e 3945 assert(rt>=0);
3946 assert(addr>=0);
cf95b4f0 3947 assert(dops[i].opcode==0x2a||dops[i].opcode==0x2e); // SWL/SWR only implemented
3968e69e 3948 reglist|=(1<<addr);
3949 reglist&=~(1<<temp2);
3950
3968e69e 3951 // don't bother with it and call write handler
3952 save_regs(reglist);
3953 pass_args(addr,rt);
3954 int cc=get_reg(i_regmap,CCREG);
3955 if(cc<0)
3956 emit_loadreg(CCREG,2);
2330734f 3957 emit_addimm(cc<0?2:cc,(int)stubs[n].d+1,2);
cf95b4f0 3958 emit_far_call((dops[i].opcode==0x2a?jump_handle_swl:jump_handle_swr));
2330734f 3959 emit_addimm(0,-((int)stubs[n].d+1),cc<0?2:cc);
3968e69e 3960 if(cc<0)
3961 emit_storereg(CCREG,2);
3962 restore_regs(reglist);
3963 emit_jmp(stubs[n].retaddr); // return address
3968e69e 3964}
3965
57871462 3966#ifndef multdiv_assemble
3967void multdiv_assemble(int i,struct regstat *i_regs)
3968{
3969 printf("Need multdiv_assemble for this architecture.\n");
7c3a5182 3970 abort();
57871462 3971}
3972#endif
3973
2330734f 3974static void mov_assemble(int i, const struct regstat *i_regs)
57871462 3975{
cf95b4f0 3976 //if(dops[i].opcode2==0x10||dops[i].opcode2==0x12) { // MFHI/MFLO
3977 //if(dops[i].opcode2==0x11||dops[i].opcode2==0x13) { // MTHI/MTLO
3978 if(dops[i].rt1) {
7c3a5182 3979 signed char sl,tl;
cf95b4f0 3980 tl=get_reg(i_regs->regmap,dops[i].rt1);
57871462 3981 //assert(tl>=0);
3982 if(tl>=0) {
cf95b4f0 3983 sl=get_reg(i_regs->regmap,dops[i].rs1);
57871462 3984 if(sl>=0) emit_mov(sl,tl);
cf95b4f0 3985 else emit_loadreg(dops[i].rs1,tl);
57871462 3986 }
3987 }
cf95b4f0 3988 if (dops[i].rs1 == HIREG || dops[i].rs1 == LOREG) // MFHI/MFLO
32631e6a 3989 multdiv_do_stall(i, i_regs);
57871462 3990}
3991
3968e69e 3992// call interpreter, exception handler, things that change pc/regs/cycles ...
2330734f 3993static void call_c_cpu_handler(int i, const struct regstat *i_regs, int ccadj_, u_int pc, void *func)
57871462 3994{
3995 signed char ccreg=get_reg(i_regs->regmap,CCREG);
3996 assert(ccreg==HOST_CCREG);
3997 assert(!is_delayslot);
581335b0 3998 (void)ccreg;
3968e69e 3999
4000 emit_movimm(pc,3); // Get PC
4001 emit_readword(&last_count,2);
4002 emit_writeword(3,&psxRegs.pc);
2330734f 4003 emit_addimm(HOST_CCREG,ccadj_,HOST_CCREG);
3968e69e 4004 emit_add(2,HOST_CCREG,2);
4005 emit_writeword(2,&psxRegs.cycle);
2a014d73 4006 emit_far_call(func);
4007 emit_far_jump(jump_to_new_pc);
3968e69e 4008}
4009
2330734f 4010static void syscall_assemble(int i, const struct regstat *i_regs, int ccadj_)
3968e69e 4011{
d1150cd6 4012 // 'break' tends to be littered around to catch things like
4013 // division by 0 and is almost never executed, so don't emit much code here
4014 void *func = (dops[i].opcode2 == 0x0C)
4015 ? (is_delayslot ? jump_syscall_ds : jump_syscall)
4016 : (is_delayslot ? jump_break_ds : jump_break);
2acc46cd 4017 assert(get_reg(i_regs->regmap, CCREG) == HOST_CCREG);
d1150cd6 4018 emit_movimm(start + i*4, 2); // pc
4019 emit_addimm(HOST_CCREG, ccadj_ + CLOCK_ADJUST(1), HOST_CCREG);
4020 emit_far_jump(func);
7139f3c8 4021}
4022
2330734f 4023static void hlecall_assemble(int i, const struct regstat *i_regs, int ccadj_)
7139f3c8 4024{
3968e69e 4025 void *hlefunc = psxNULL;
dd79da89 4026 uint32_t hleCode = source[i] & 0x03ffffff;
3968e69e 4027 if (hleCode < ARRAY_SIZE(psxHLEt))
4028 hlefunc = psxHLEt[hleCode];
4029
2330734f 4030 call_c_cpu_handler(i, i_regs, ccadj_, start + i*4+4, hlefunc);
57871462 4031}
4032
2330734f 4033static void intcall_assemble(int i, const struct regstat *i_regs, int ccadj_)
1e973cb0 4034{
2330734f 4035 call_c_cpu_handler(i, i_regs, ccadj_, start + i*4, execI);
1e973cb0 4036}
4037
8062d65a 4038static void speculate_mov(int rs,int rt)
4039{
4040 if(rt!=0) {
4041 smrv_strong_next|=1<<rt;
4042 smrv[rt]=smrv[rs];
4043 }
4044}
4045
4046static void speculate_mov_weak(int rs,int rt)
4047{
4048 if(rt!=0) {
4049 smrv_weak_next|=1<<rt;
4050 smrv[rt]=smrv[rs];
4051 }
4052}
4053
4054static void speculate_register_values(int i)
4055{
4056 if(i==0) {
4057 memcpy(smrv,psxRegs.GPR.r,sizeof(smrv));
4058 // gp,sp are likely to stay the same throughout the block
4059 smrv_strong_next=(1<<28)|(1<<29)|(1<<30);
4060 smrv_weak_next=~smrv_strong_next;
4061 //printf(" llr %08x\n", smrv[4]);
4062 }
4063 smrv_strong=smrv_strong_next;
4064 smrv_weak=smrv_weak_next;
cf95b4f0 4065 switch(dops[i].itype) {
8062d65a 4066 case ALU:
cf95b4f0 4067 if ((smrv_strong>>dops[i].rs1)&1) speculate_mov(dops[i].rs1,dops[i].rt1);
4068 else if((smrv_strong>>dops[i].rs2)&1) speculate_mov(dops[i].rs2,dops[i].rt1);
4069 else if((smrv_weak>>dops[i].rs1)&1) speculate_mov_weak(dops[i].rs1,dops[i].rt1);
4070 else if((smrv_weak>>dops[i].rs2)&1) speculate_mov_weak(dops[i].rs2,dops[i].rt1);
8062d65a 4071 else {
cf95b4f0 4072 smrv_strong_next&=~(1<<dops[i].rt1);
4073 smrv_weak_next&=~(1<<dops[i].rt1);
8062d65a 4074 }
4075 break;
4076 case SHIFTIMM:
cf95b4f0 4077 smrv_strong_next&=~(1<<dops[i].rt1);
4078 smrv_weak_next&=~(1<<dops[i].rt1);
8062d65a 4079 // fallthrough
4080 case IMM16:
cf95b4f0 4081 if(dops[i].rt1&&is_const(&regs[i],dops[i].rt1)) {
4082 int value,hr=get_reg(regs[i].regmap,dops[i].rt1);
8062d65a 4083 if(hr>=0) {
4084 if(get_final_value(hr,i,&value))
cf95b4f0 4085 smrv[dops[i].rt1]=value;
4086 else smrv[dops[i].rt1]=constmap[i][hr];
4087 smrv_strong_next|=1<<dops[i].rt1;
8062d65a 4088 }
4089 }
4090 else {
cf95b4f0 4091 if ((smrv_strong>>dops[i].rs1)&1) speculate_mov(dops[i].rs1,dops[i].rt1);
4092 else if((smrv_weak>>dops[i].rs1)&1) speculate_mov_weak(dops[i].rs1,dops[i].rt1);
8062d65a 4093 }
4094 break;
4095 case LOAD:
cf95b4f0 4096 if(start<0x2000&&(dops[i].rt1==26||(smrv[dops[i].rt1]>>24)==0xa0)) {
8062d65a 4097 // special case for BIOS
cf95b4f0 4098 smrv[dops[i].rt1]=0xa0000000;
4099 smrv_strong_next|=1<<dops[i].rt1;
8062d65a 4100 break;
4101 }
4102 // fallthrough
4103 case SHIFT:
4104 case LOADLR:
4105 case MOV:
cf95b4f0 4106 smrv_strong_next&=~(1<<dops[i].rt1);
4107 smrv_weak_next&=~(1<<dops[i].rt1);
8062d65a 4108 break;
4109 case COP0:
4110 case COP2:
cf95b4f0 4111 if(dops[i].opcode2==0||dops[i].opcode2==2) { // MFC/CFC
4112 smrv_strong_next&=~(1<<dops[i].rt1);
4113 smrv_weak_next&=~(1<<dops[i].rt1);
8062d65a 4114 }
4115 break;
4116 case C2LS:
cf95b4f0 4117 if (dops[i].opcode==0x32) { // LWC2
4118 smrv_strong_next&=~(1<<dops[i].rt1);
4119 smrv_weak_next&=~(1<<dops[i].rt1);
8062d65a 4120 }
4121 break;
4122 }
4123#if 0
4124 int r=4;
4125 printf("x %08x %08x %d %d c %08x %08x\n",smrv[r],start+i*4,
4126 ((smrv_strong>>r)&1),(smrv_weak>>r)&1,regs[i].isconst,regs[i].wasconst);
4127#endif
4128}
4129
2330734f 4130static void ujump_assemble(int i, const struct regstat *i_regs);
4131static void rjump_assemble(int i, const struct regstat *i_regs);
4132static void cjump_assemble(int i, const struct regstat *i_regs);
4133static void sjump_assemble(int i, const struct regstat *i_regs);
4134static void pagespan_assemble(int i, const struct regstat *i_regs);
4135
4136static int assemble(int i, const struct regstat *i_regs, int ccadj_)
57871462 4137{
2330734f 4138 int ds = 0;
4139 switch (dops[i].itype) {
57871462 4140 case ALU:
2330734f 4141 alu_assemble(i, i_regs);
4142 break;
57871462 4143 case IMM16:
2330734f 4144 imm16_assemble(i, i_regs);
4145 break;
57871462 4146 case SHIFT:
2330734f 4147 shift_assemble(i, i_regs);
4148 break;
57871462 4149 case SHIFTIMM:
2330734f 4150 shiftimm_assemble(i, i_regs);
4151 break;
57871462 4152 case LOAD:
2330734f 4153 load_assemble(i, i_regs, ccadj_);
4154 break;
57871462 4155 case LOADLR:
2330734f 4156 loadlr_assemble(i, i_regs, ccadj_);
4157 break;
57871462 4158 case STORE:
2330734f 4159 store_assemble(i, i_regs, ccadj_);
4160 break;
57871462 4161 case STORELR:
2330734f 4162 storelr_assemble(i, i_regs, ccadj_);
4163 break;
57871462 4164 case COP0:
2330734f 4165 cop0_assemble(i, i_regs, ccadj_);
4166 break;
57871462 4167 case COP1:
2330734f 4168 cop1_assemble(i, i_regs);
4169 break;
57871462 4170 case C1LS:
2330734f 4171 c1ls_assemble(i, i_regs);
4172 break;
b9b61529 4173 case COP2:
2330734f 4174 cop2_assemble(i, i_regs);
4175 break;
b9b61529 4176 case C2LS:
2330734f 4177 c2ls_assemble(i, i_regs, ccadj_);
4178 break;
b9b61529 4179 case C2OP:
2330734f 4180 c2op_assemble(i, i_regs);
4181 break;
57871462 4182 case MULTDIV:
2330734f 4183 multdiv_assemble(i, i_regs);
4184 multdiv_prepare_stall(i, i_regs, ccadj_);
32631e6a 4185 break;
57871462 4186 case MOV:
2330734f 4187 mov_assemble(i, i_regs);
4188 break;
4189 case SYSCALL:
4190 syscall_assemble(i, i_regs, ccadj_);
4191 break;
4192 case HLECALL:
4193 hlecall_assemble(i, i_regs, ccadj_);
4194 break;
4195 case INTCALL:
4196 intcall_assemble(i, i_regs, ccadj_);
4197 break;
4198 case UJUMP:
4199 ujump_assemble(i, i_regs);
4200 ds = 1;
4201 break;
4202 case RJUMP:
4203 rjump_assemble(i, i_regs);
4204 ds = 1;
4205 break;
4206 case CJUMP:
4207 cjump_assemble(i, i_regs);
4208 ds = 1;
4209 break;
4210 case SJUMP:
4211 sjump_assemble(i, i_regs);
4212 ds = 1;
4213 break;
4214 case SPAN:
4215 pagespan_assemble(i, i_regs);
4216 break;
24058131 4217 case NOP:
2330734f 4218 case OTHER:
4219 case NI:
4220 // not handled, just skip
4221 break;
4222 default:
4223 assert(0);
4224 }
4225 return ds;
4226}
4227
4228static void ds_assemble(int i, const struct regstat *i_regs)
4229{
4230 speculate_register_values(i);
4231 is_delayslot = 1;
4232 switch (dops[i].itype) {
57871462 4233 case SYSCALL:
7139f3c8 4234 case HLECALL:
1e973cb0 4235 case INTCALL:
57871462 4236 case SPAN:
4237 case UJUMP:
4238 case RJUMP:
4239 case CJUMP:
4240 case SJUMP:
c43b5311 4241 SysPrintf("Jump in the delay slot. This is probably a bug.\n");
2330734f 4242 break;
4243 default:
4244 assemble(i, i_regs, ccadj[i]);
57871462 4245 }
2330734f 4246 is_delayslot = 0;
57871462 4247}
4248
4249// Is the branch target a valid internal jump?
ad49de89 4250static int internal_branch(int addr)
57871462 4251{
4252 if(addr&1) return 0; // Indirect (register) jump
4253 if(addr>=start && addr<start+slen*4-4)
4254 {
71e490c5 4255 return 1;
57871462 4256 }
4257 return 0;
4258}
4259
ad49de89 4260static void wb_invalidate(signed char pre[],signed char entry[],uint64_t dirty,uint64_t u)
57871462 4261{
4262 int hr;
4263 for(hr=0;hr<HOST_REGS;hr++) {
4264 if(hr!=EXCLUDE_REG) {
4265 if(pre[hr]!=entry[hr]) {
4266 if(pre[hr]>=0) {
4267 if((dirty>>hr)&1) {
4268 if(get_reg(entry,pre[hr])<0) {
00fa9369 4269 assert(pre[hr]<64);
4270 if(!((u>>pre[hr])&1))
4271 emit_storereg(pre[hr],hr);
57871462 4272 }
4273 }
4274 }
4275 }
4276 }
4277 }
4278 // Move from one register to another (no writeback)
4279 for(hr=0;hr<HOST_REGS;hr++) {
4280 if(hr!=EXCLUDE_REG) {
4281 if(pre[hr]!=entry[hr]) {
9de8a0c3 4282 if(pre[hr]>=0&&pre[hr]<TEMPREG) {
57871462 4283 int nr;
4284 if((nr=get_reg(entry,pre[hr]))>=0) {
4285 emit_mov(hr,nr);
4286 }
4287 }
4288 }
4289 }
4290 }
4291}
57871462 4292
4293// Load the specified registers
4294// This only loads the registers given as arguments because
4295// we don't want to load things that will be overwritten
53358c1d 4296static inline void load_reg(signed char entry[], signed char regmap[], int rs)
57871462 4297{
53358c1d 4298 int hr = get_reg(regmap, rs);
4299 if (hr >= 0 && entry[hr] != regmap[hr])
4300 emit_loadreg(regmap[hr], hr);
4301}
4302
4303static void load_regs(signed char entry[], signed char regmap[], int rs1, int rs2)
4304{
4305 load_reg(entry, regmap, rs1);
4306 if (rs1 != rs2)
4307 load_reg(entry, regmap, rs2);
57871462 4308}
4309
4310// Load registers prior to the start of a loop
4311// so that they are not loaded within the loop
4312static void loop_preload(signed char pre[],signed char entry[])
4313{
4314 int hr;
53358c1d 4315 for (hr = 0; hr < HOST_REGS; hr++) {
4316 int r = entry[hr];
4317 if (r >= 0 && pre[hr] != r && get_reg(pre, r) < 0) {
4318 assem_debug("loop preload:\n");
4319 if (r < TEMPREG)
4320 emit_loadreg(r, hr);
57871462 4321 }
4322 }
4323}
4324
4325// Generate address for load/store instruction
b9b61529 4326// goes to AGEN for writes, FTEMP for LOADLR and cop1/2 loads
4149788d 4327static void address_generation(int i, const struct regstat *i_regs, signed char entry[])
57871462 4328{
37387d8b 4329 if (dops[i].is_load || dops[i].is_store) {
5194fb95 4330 int ra=-1;
57871462 4331 int agr=AGEN1+(i&1);
cf95b4f0 4332 if(dops[i].itype==LOAD) {
4333 ra=get_reg(i_regs->regmap,dops[i].rt1);
9de8a0c3 4334 if(ra<0) ra=get_reg_temp(i_regs->regmap);
535d208a 4335 assert(ra>=0);
57871462 4336 }
cf95b4f0 4337 if(dops[i].itype==LOADLR) {
57871462 4338 ra=get_reg(i_regs->regmap,FTEMP);
4339 }
cf95b4f0 4340 if(dops[i].itype==STORE||dops[i].itype==STORELR) {
57871462 4341 ra=get_reg(i_regs->regmap,agr);
9de8a0c3 4342 if(ra<0) ra=get_reg_temp(i_regs->regmap);
57871462 4343 }
37387d8b 4344 if(dops[i].itype==C2LS) {
cf95b4f0 4345 if ((dops[i].opcode&0x3b)==0x31||(dops[i].opcode&0x3b)==0x32) // LWC1/LDC1/LWC2/LDC2
57871462 4346 ra=get_reg(i_regs->regmap,FTEMP);
1fd1aceb 4347 else { // SWC1/SDC1/SWC2/SDC2
57871462 4348 ra=get_reg(i_regs->regmap,agr);
9de8a0c3 4349 if(ra<0) ra=get_reg_temp(i_regs->regmap);
57871462 4350 }
4351 }
cf95b4f0 4352 int rs=get_reg(i_regs->regmap,dops[i].rs1);
57871462 4353 if(ra>=0) {
4354 int offset=imm[i];
4355 int c=(i_regs->wasconst>>rs)&1;
cf95b4f0 4356 if(dops[i].rs1==0) {
57871462 4357 // Using r0 as a base address
57871462 4358 if(!entry||entry[ra]!=agr) {
cf95b4f0 4359 if (dops[i].opcode==0x22||dops[i].opcode==0x26) {
57871462 4360 emit_movimm(offset&0xFFFFFFFC,ra); // LWL/LWR
cf95b4f0 4361 }else if (dops[i].opcode==0x1a||dops[i].opcode==0x1b) {
57871462 4362 emit_movimm(offset&0xFFFFFFF8,ra); // LDL/LDR
4363 }else{
4364 emit_movimm(offset,ra);
4365 }
4366 } // else did it in the previous cycle
4367 }
4368 else if(rs<0) {
cf95b4f0 4369 if(!entry||entry[ra]!=dops[i].rs1)
4370 emit_loadreg(dops[i].rs1,ra);
4371 //if(!entry||entry[ra]!=dops[i].rs1)
57871462 4372 // printf("poor load scheduling!\n");
4373 }
4374 else if(c) {
cf95b4f0 4375 if(dops[i].rs1!=dops[i].rt1||dops[i].itype!=LOAD) {
57871462 4376 if(!entry||entry[ra]!=agr) {
cf95b4f0 4377 if (dops[i].opcode==0x22||dops[i].opcode==0x26) {
57871462 4378 emit_movimm((constmap[i][rs]+offset)&0xFFFFFFFC,ra); // LWL/LWR
cf95b4f0 4379 }else if (dops[i].opcode==0x1a||dops[i].opcode==0x1b) {
57871462 4380 emit_movimm((constmap[i][rs]+offset)&0xFFFFFFF8,ra); // LDL/LDR
4381 }else{
57871462 4382 emit_movimm(constmap[i][rs]+offset,ra);
8575a877 4383 regs[i].loadedconst|=1<<ra;
57871462 4384 }
4385 } // else did it in the previous cycle
4386 } // else load_consts already did it
4387 }
cf95b4f0 4388 if(offset&&!c&&dops[i].rs1) {
57871462 4389 if(rs>=0) {
4390 emit_addimm(rs,offset,ra);
4391 }else{
4392 emit_addimm(ra,offset,ra);
4393 }
4394 }
4395 }
4396 }
4397 // Preload constants for next instruction
37387d8b 4398 if (dops[i+1].is_load || dops[i+1].is_store) {
57871462 4399 int agr,ra;
57871462 4400 // Actual address
4401 agr=AGEN1+((i+1)&1);
4402 ra=get_reg(i_regs->regmap,agr);
4403 if(ra>=0) {
cf95b4f0 4404 int rs=get_reg(regs[i+1].regmap,dops[i+1].rs1);
57871462 4405 int offset=imm[i+1];
4406 int c=(regs[i+1].wasconst>>rs)&1;
cf95b4f0 4407 if(c&&(dops[i+1].rs1!=dops[i+1].rt1||dops[i+1].itype!=LOAD)) {
4408 if (dops[i+1].opcode==0x22||dops[i+1].opcode==0x26) {
57871462 4409 emit_movimm((constmap[i+1][rs]+offset)&0xFFFFFFFC,ra); // LWL/LWR
cf95b4f0 4410 }else if (dops[i+1].opcode==0x1a||dops[i+1].opcode==0x1b) {
57871462 4411 emit_movimm((constmap[i+1][rs]+offset)&0xFFFFFFF8,ra); // LDL/LDR
4412 }else{
57871462 4413 emit_movimm(constmap[i+1][rs]+offset,ra);
8575a877 4414 regs[i+1].loadedconst|=1<<ra;
57871462 4415 }
4416 }
cf95b4f0 4417 else if(dops[i+1].rs1==0) {
57871462 4418 // Using r0 as a base address
cf95b4f0 4419 if (dops[i+1].opcode==0x22||dops[i+1].opcode==0x26) {
57871462 4420 emit_movimm(offset&0xFFFFFFFC,ra); // LWL/LWR
cf95b4f0 4421 }else if (dops[i+1].opcode==0x1a||dops[i+1].opcode==0x1b) {
57871462 4422 emit_movimm(offset&0xFFFFFFF8,ra); // LDL/LDR
4423 }else{
4424 emit_movimm(offset,ra);
4425 }
4426 }
4427 }
4428 }
4429}
4430
e2b5e7aa 4431static int get_final_value(int hr, int i, int *value)
57871462 4432{
4433 int reg=regs[i].regmap[hr];
4434 while(i<slen-1) {
4435 if(regs[i+1].regmap[hr]!=reg) break;
4436 if(!((regs[i+1].isconst>>hr)&1)) break;
cf95b4f0 4437 if(dops[i+1].bt) break;
57871462 4438 i++;
4439 }
4440 if(i<slen-1) {
fe807a8a 4441 if (dops[i].is_jump) {
57871462 4442 *value=constmap[i][hr];
4443 return 1;
4444 }
cf95b4f0 4445 if(!dops[i+1].bt) {
fe807a8a 4446 if (dops[i+1].is_jump) {
57871462 4447 // Load in delay slot, out-of-order execution
cf95b4f0 4448 if(dops[i+2].itype==LOAD&&dops[i+2].rs1==reg&&dops[i+2].rt1==reg&&((regs[i+1].wasconst>>hr)&1))
57871462 4449 {
57871462 4450 // Precompute load address
4451 *value=constmap[i][hr]+imm[i+2];
4452 return 1;
4453 }
4454 }
cf95b4f0 4455 if(dops[i+1].itype==LOAD&&dops[i+1].rs1==reg&&dops[i+1].rt1==reg)
57871462 4456 {
57871462 4457 // Precompute load address
4458 *value=constmap[i][hr]+imm[i+1];
643aeae3 4459 //printf("c=%x imm=%lx\n",(long)constmap[i][hr],imm[i+1]);
57871462 4460 return 1;
4461 }
4462 }
4463 }
4464 *value=constmap[i][hr];
643aeae3 4465 //printf("c=%lx\n",(long)constmap[i][hr]);
57871462 4466 if(i==slen-1) return 1;
00fa9369 4467 assert(reg < 64);
4468 return !((unneeded_reg[i+1]>>reg)&1);
57871462 4469}
4470
4471// Load registers with known constants
ad49de89 4472static void load_consts(signed char pre[],signed char regmap[],int i)
57871462 4473{
8575a877 4474 int hr,hr2;
4475 // propagate loaded constant flags
cf95b4f0 4476 if(i==0||dops[i].bt)
8575a877 4477 regs[i].loadedconst=0;
4478 else {
4479 for(hr=0;hr<HOST_REGS;hr++) {
4480 if(hr!=EXCLUDE_REG&&regmap[hr]>=0&&((regs[i-1].isconst>>hr)&1)&&pre[hr]==regmap[hr]
4481 &&regmap[hr]==regs[i-1].regmap[hr]&&((regs[i-1].loadedconst>>hr)&1))
4482 {
4483 regs[i].loadedconst|=1<<hr;
4484 }
4485 }
4486 }
57871462 4487 // Load 32-bit regs
4488 for(hr=0;hr<HOST_REGS;hr++) {
4489 if(hr!=EXCLUDE_REG&&regmap[hr]>=0) {
4490 //if(entry[hr]!=regmap[hr]) {
8575a877 4491 if(!((regs[i].loadedconst>>hr)&1)) {
ad49de89 4492 assert(regmap[hr]<64);
4493 if(((regs[i].isconst>>hr)&1)&&regmap[hr]>0) {
8575a877 4494 int value,similar=0;
57871462 4495 if(get_final_value(hr,i,&value)) {
8575a877 4496 // see if some other register has similar value
4497 for(hr2=0;hr2<HOST_REGS;hr2++) {
4498 if(hr2!=EXCLUDE_REG&&((regs[i].loadedconst>>hr2)&1)) {
4499 if(is_similar_value(value,constmap[i][hr2])) {
4500 similar=1;
4501 break;
4502 }
4503 }
4504 }
4505 if(similar) {
4506 int value2;
4507 if(get_final_value(hr2,i,&value2)) // is this needed?
4508 emit_movimm_from(value2,hr2,value,hr);
4509 else
4510 emit_movimm(value,hr);
4511 }
4512 else if(value==0) {
57871462 4513 emit_zeroreg(hr);
4514 }
4515 else {
4516 emit_movimm(value,hr);
4517 }
4518 }
8575a877 4519 regs[i].loadedconst|=1<<hr;
57871462 4520 }
4521 }
4522 }
4523 }
57871462 4524}
ad49de89 4525
2330734f 4526static void load_all_consts(const signed char regmap[], u_int dirty, int i)
57871462 4527{
4528 int hr;
4529 // Load 32-bit regs
4530 for(hr=0;hr<HOST_REGS;hr++) {
4531 if(hr!=EXCLUDE_REG&&regmap[hr]>=0&&((dirty>>hr)&1)) {
ad49de89 4532 assert(regmap[hr] < 64);
4533 if(((regs[i].isconst>>hr)&1)&&regmap[hr]>0) {
57871462 4534 int value=constmap[i][hr];
4535 if(value==0) {
4536 emit_zeroreg(hr);
4537 }
4538 else {
4539 emit_movimm(value,hr);
4540 }
4541 }
4542 }
4543 }
57871462 4544}
4545
4546// Write out all dirty registers (except cycle count)
2330734f 4547static void wb_dirtys(const signed char i_regmap[], uint64_t i_dirty)
57871462 4548{
4549 int hr;
4550 for(hr=0;hr<HOST_REGS;hr++) {
4551 if(hr!=EXCLUDE_REG) {
4552 if(i_regmap[hr]>0) {
4553 if(i_regmap[hr]!=CCREG) {
4554 if((i_dirty>>hr)&1) {
00fa9369 4555 assert(i_regmap[hr]<64);
4556 emit_storereg(i_regmap[hr],hr);
57871462 4557 }
4558 }
4559 }
4560 }
4561 }
4562}
ad49de89 4563
57871462 4564// Write out dirty registers that we need to reload (pair with load_needed_regs)
4565// This writes the registers not written by store_regs_bt
2330734f 4566static void wb_needed_dirtys(const signed char i_regmap[], uint64_t i_dirty, int addr)
57871462 4567{
4568 int hr;
4569 int t=(addr-start)>>2;
4570 for(hr=0;hr<HOST_REGS;hr++) {
4571 if(hr!=EXCLUDE_REG) {
4572 if(i_regmap[hr]>0) {
4573 if(i_regmap[hr]!=CCREG) {
ad49de89 4574 if(i_regmap[hr]==regs[t].regmap_entry[hr] && ((regs[t].dirty>>hr)&1)) {
57871462 4575 if((i_dirty>>hr)&1) {
00fa9369 4576 assert(i_regmap[hr]<64);
4577 emit_storereg(i_regmap[hr],hr);
57871462 4578 }
4579 }
4580 }
4581 }
4582 }
4583 }
4584}
4585
4586// Load all registers (except cycle count)
2330734f 4587static void load_all_regs(const signed char i_regmap[])
57871462 4588{
4589 int hr;
4590 for(hr=0;hr<HOST_REGS;hr++) {
4591 if(hr!=EXCLUDE_REG) {
4592 if(i_regmap[hr]==0) {
4593 emit_zeroreg(hr);
4594 }
4595 else
9de8a0c3 4596 if(i_regmap[hr]>0 && i_regmap[hr]<TEMPREG && i_regmap[hr]!=CCREG)
57871462 4597 {
4598 emit_loadreg(i_regmap[hr],hr);
4599 }
4600 }
4601 }
4602}
4603
4604// Load all current registers also needed by next instruction
2330734f 4605static void load_needed_regs(const signed char i_regmap[], const signed char next_regmap[])
57871462 4606{
4607 int hr;
4608 for(hr=0;hr<HOST_REGS;hr++) {
4609 if(hr!=EXCLUDE_REG) {
4610 if(get_reg(next_regmap,i_regmap[hr])>=0) {
4611 if(i_regmap[hr]==0) {
4612 emit_zeroreg(hr);
4613 }
4614 else
9de8a0c3 4615 if(i_regmap[hr]>0 && i_regmap[hr]<TEMPREG && i_regmap[hr]!=CCREG)
57871462 4616 {
4617 emit_loadreg(i_regmap[hr],hr);
4618 }
4619 }
4620 }
4621 }
4622}
4623
4624// Load all regs, storing cycle count if necessary
2330734f 4625static void load_regs_entry(int t)
57871462 4626{
4627 int hr;
cf95b4f0 4628 if(dops[t].is_ds) emit_addimm(HOST_CCREG,CLOCK_ADJUST(1),HOST_CCREG);
2330734f 4629 else if(ccadj[t]) emit_addimm(HOST_CCREG,-ccadj[t],HOST_CCREG);
57871462 4630 if(regs[t].regmap_entry[HOST_CCREG]!=CCREG) {
4631 emit_storereg(CCREG,HOST_CCREG);
4632 }
4633 // Load 32-bit regs
4634 for(hr=0;hr<HOST_REGS;hr++) {
ea3d2e6e 4635 if(regs[t].regmap_entry[hr]>=0&&regs[t].regmap_entry[hr]<TEMPREG) {
57871462 4636 if(regs[t].regmap_entry[hr]==0) {
4637 emit_zeroreg(hr);
4638 }
4639 else if(regs[t].regmap_entry[hr]!=CCREG)
4640 {
4641 emit_loadreg(regs[t].regmap_entry[hr],hr);
4642 }
4643 }
4644 }
57871462 4645}
4646
4647// Store dirty registers prior to branch
4149788d 4648static void store_regs_bt(signed char i_regmap[],uint64_t i_dirty,int addr)
57871462 4649{
ad49de89 4650 if(internal_branch(addr))
57871462 4651 {
4652 int t=(addr-start)>>2;
4653 int hr;
4654 for(hr=0;hr<HOST_REGS;hr++) {
4655 if(hr!=EXCLUDE_REG) {
4656 if(i_regmap[hr]>0 && i_regmap[hr]!=CCREG) {
ad49de89 4657 if(i_regmap[hr]!=regs[t].regmap_entry[hr] || !((regs[t].dirty>>hr)&1)) {
57871462 4658 if((i_dirty>>hr)&1) {
00fa9369 4659 assert(i_regmap[hr]<64);
4660 if(!((unneeded_reg[t]>>i_regmap[hr])&1))
4661 emit_storereg(i_regmap[hr],hr);
57871462 4662 }
4663 }
4664 }
4665 }
4666 }
4667 }
4668 else
4669 {
4670 // Branch out of this block, write out all dirty regs
ad49de89 4671 wb_dirtys(i_regmap,i_dirty);
57871462 4672 }
4673}
4674
4675// Load all needed registers for branch target
ad49de89 4676static void load_regs_bt(signed char i_regmap[],uint64_t i_dirty,int addr)
57871462 4677{
4678 //if(addr>=start && addr<(start+slen*4))
ad49de89 4679 if(internal_branch(addr))
57871462 4680 {
4681 int t=(addr-start)>>2;
4682 int hr;
4683 // Store the cycle count before loading something else
4684 if(i_regmap[HOST_CCREG]!=CCREG) {
4685 assert(i_regmap[HOST_CCREG]==-1);
4686 }
4687 if(regs[t].regmap_entry[HOST_CCREG]!=CCREG) {
4688 emit_storereg(CCREG,HOST_CCREG);
4689 }
4690 // Load 32-bit regs
4691 for(hr=0;hr<HOST_REGS;hr++) {
ea3d2e6e 4692 if(hr!=EXCLUDE_REG&&regs[t].regmap_entry[hr]>=0&&regs[t].regmap_entry[hr]<TEMPREG) {
00fa9369 4693 if(i_regmap[hr]!=regs[t].regmap_entry[hr]) {
57871462 4694 if(regs[t].regmap_entry[hr]==0) {
4695 emit_zeroreg(hr);
4696 }
4697 else if(regs[t].regmap_entry[hr]!=CCREG)
4698 {
4699 emit_loadreg(regs[t].regmap_entry[hr],hr);
4700 }
4701 }
4702 }
4703 }
57871462 4704 }
4705}
4706
ad49de89 4707static int match_bt(signed char i_regmap[],uint64_t i_dirty,int addr)
57871462 4708{
4709 if(addr>=start && addr<start+slen*4-4)
4710 {
4711 int t=(addr-start)>>2;
4712 int hr;
4713 if(regs[t].regmap_entry[HOST_CCREG]!=CCREG) return 0;
4714 for(hr=0;hr<HOST_REGS;hr++)
4715 {
4716 if(hr!=EXCLUDE_REG)
4717 {
4718 if(i_regmap[hr]!=regs[t].regmap_entry[hr])
4719 {
ea3d2e6e 4720 if(regs[t].regmap_entry[hr]>=0&&(regs[t].regmap_entry[hr]|64)<TEMPREG+64)
57871462 4721 {
4722 return 0;
4723 }
9f51b4b9 4724 else
57871462 4725 if((i_dirty>>hr)&1)
4726 {
ea3d2e6e 4727 if(i_regmap[hr]<TEMPREG)
57871462 4728 {
4729 if(!((unneeded_reg[t]>>i_regmap[hr])&1))
4730 return 0;
4731 }
ea3d2e6e 4732 else if(i_regmap[hr]>=64&&i_regmap[hr]<TEMPREG+64)
57871462 4733 {
00fa9369 4734 assert(0);
57871462 4735 }
4736 }
4737 }
4738 else // Same register but is it 32-bit or dirty?
4739 if(i_regmap[hr]>=0)
4740 {
4741 if(!((regs[t].dirty>>hr)&1))
4742 {
4743 if((i_dirty>>hr)&1)
4744 {
4745 if(!((unneeded_reg[t]>>i_regmap[hr])&1))
4746 {
4747 //printf("%x: dirty no match\n",addr);
4748 return 0;
4749 }
4750 }
4751 }
57871462 4752 }
4753 }
4754 }
57871462 4755 // Delay slots are not valid branch targets
fe807a8a 4756 //if(t>0&&(dops[t-1].is_jump) return 0;
57871462 4757 // Delay slots require additional processing, so do not match
cf95b4f0 4758 if(dops[t].is_ds) return 0;
57871462 4759 }
4760 else
4761 {
4762 int hr;
4763 for(hr=0;hr<HOST_REGS;hr++)
4764 {
4765 if(hr!=EXCLUDE_REG)
4766 {
4767 if(i_regmap[hr]>=0)
4768 {
4769 if(hr!=HOST_CCREG||i_regmap[hr]!=CCREG)
4770 {
4771 if((i_dirty>>hr)&1)
4772 {
4773 return 0;
4774 }
4775 }
4776 }
4777 }
4778 }
4779 }
4780 return 1;
4781}
4782
dd114d7d 4783#ifdef DRC_DBG
2330734f 4784static void drc_dbg_emit_do_cmp(int i, int ccadj_)
dd114d7d 4785{
4786 extern void do_insn_cmp();
3968e69e 4787 //extern int cycle;
81dbbf4c 4788 u_int hr, reglist = get_host_reglist(regs[i].regmap);
dd114d7d 4789
40fca85b 4790 assem_debug("//do_insn_cmp %08x\n", start+i*4);
dd114d7d 4791 save_regs(reglist);
40fca85b 4792 // write out changed consts to match the interpreter
cf95b4f0 4793 if (i > 0 && !dops[i].bt) {
40fca85b 4794 for (hr = 0; hr < HOST_REGS; hr++) {
2330734f 4795 int reg = regs[i].regmap_entry[hr]; // regs[i-1].regmap[hr];
40fca85b 4796 if (hr == EXCLUDE_REG || reg < 0)
4797 continue;
4798 if (!((regs[i-1].isconst >> hr) & 1))
4799 continue;
4800 if (i > 1 && reg == regs[i-2].regmap[hr] && constmap[i-1][hr] == constmap[i-2][hr])
4801 continue;
4802 emit_movimm(constmap[i-1][hr],0);
4803 emit_storereg(reg, 0);
4804 }
4805 }
dd114d7d 4806 emit_movimm(start+i*4,0);
643aeae3 4807 emit_writeword(0,&pcaddr);
2330734f 4808 int cc = get_reg(regs[i].regmap_entry, CCREG);
4809 if (cc < 0)
4810 emit_loadreg(CCREG, cc = 0);
4811 emit_addimm(cc, ccadj_, 0);
4812 emit_writeword(0, &psxRegs.cycle);
2a014d73 4813 emit_far_call(do_insn_cmp);
643aeae3 4814 //emit_readword(&cycle,0);
dd114d7d 4815 //emit_addimm(0,2,0);
643aeae3 4816 //emit_writeword(0,&cycle);
3968e69e 4817 (void)get_reg2;
dd114d7d 4818 restore_regs(reglist);
40fca85b 4819 assem_debug("\\\\do_insn_cmp\n");
dd114d7d 4820}
4821#else
2330734f 4822#define drc_dbg_emit_do_cmp(x,y)
dd114d7d 4823#endif
4824
57871462 4825// Used when a branch jumps into the delay slot of another branch
7c3a5182 4826static void ds_assemble_entry(int i)
57871462 4827{
2330734f 4828 int t = (ba[i] - start) >> 2;
4829 int ccadj_ = -CLOCK_ADJUST(1);
df4dc2b1 4830 if (!instr_addr[t])
4831 instr_addr[t] = out;
57871462 4832 assem_debug("Assemble delay slot at %x\n",ba[i]);
4833 assem_debug("<->\n");
2330734f 4834 drc_dbg_emit_do_cmp(t, ccadj_);
57871462 4835 if(regs[t].regmap_entry[HOST_CCREG]==CCREG&&regs[t].regmap[HOST_CCREG]!=CCREG)
ad49de89 4836 wb_register(CCREG,regs[t].regmap_entry,regs[t].wasdirty);
cf95b4f0 4837 load_regs(regs[t].regmap_entry,regs[t].regmap,dops[t].rs1,dops[t].rs2);
57871462 4838 address_generation(t,&regs[t],regs[t].regmap_entry);
37387d8b 4839 if (ram_offset && (dops[t].is_load || dops[t].is_store))
53358c1d 4840 load_reg(regs[t].regmap_entry,regs[t].regmap,ROREG);
37387d8b 4841 if (dops[t].is_store)
53358c1d 4842 load_reg(regs[t].regmap_entry,regs[t].regmap,INVCP);
57871462 4843 is_delayslot=0;
2330734f 4844 switch (dops[t].itype) {
57871462 4845 case SYSCALL:
7139f3c8 4846 case HLECALL:
1e973cb0 4847 case INTCALL:
57871462 4848 case SPAN:
4849 case UJUMP:
4850 case RJUMP:
4851 case CJUMP:
4852 case SJUMP:
c43b5311 4853 SysPrintf("Jump in the delay slot. This is probably a bug.\n");
2330734f 4854 break;
4855 default:
4856 assemble(t, &regs[t], ccadj_);
57871462 4857 }
ad49de89 4858 store_regs_bt(regs[t].regmap,regs[t].dirty,ba[i]+4);
4859 load_regs_bt(regs[t].regmap,regs[t].dirty,ba[i]+4);
4860 if(internal_branch(ba[i]+4))
57871462 4861 assem_debug("branch: internal\n");
4862 else
4863 assem_debug("branch: external\n");
ad49de89 4864 assert(internal_branch(ba[i]+4));
4865 add_to_linker(out,ba[i]+4,internal_branch(ba[i]+4));
57871462 4866 emit_jmp(0);
4867}
4868
7c3a5182 4869static void emit_extjump(void *addr, u_int target)
4870{
4871 emit_extjump2(addr, target, dyna_linker);
4872}
4873
4874static void emit_extjump_ds(void *addr, u_int target)
4875{
4876 emit_extjump2(addr, target, dyna_linker_ds);
4877}
4878
d1e4ebd9 4879// Load 2 immediates optimizing for small code size
4880static void emit_mov2imm_compact(int imm1,u_int rt1,int imm2,u_int rt2)
4881{
4882 emit_movimm(imm1,rt1);
4883 emit_movimm_from(imm1,rt1,imm2,rt2);
4884}
4885
2330734f 4886static void do_cc(int i, const signed char i_regmap[], int *adj,
4887 int addr, int taken, int invert)
57871462 4888{
2330734f 4889 int count, count_plus2;
b14b6a8f 4890 void *jaddr;
4891 void *idle=NULL;
b6e87b2b 4892 int t=0;
cf95b4f0 4893 if(dops[i].itype==RJUMP)
57871462 4894 {
4895 *adj=0;
4896 }
4897 //if(ba[i]>=start && ba[i]<(start+slen*4))
ad49de89 4898 if(internal_branch(ba[i]))
57871462 4899 {
b6e87b2b 4900 t=(ba[i]-start)>>2;
2330734f 4901 if(dops[t].is_ds) *adj=-CLOCK_ADJUST(1); // Branch into delay slot adds an extra cycle
57871462 4902 else *adj=ccadj[t];
4903 }
4904 else
4905 {
4906 *adj=0;
4907 }
2330734f 4908 count = ccadj[i];
4909 count_plus2 = count + CLOCK_ADJUST(2);
57871462 4910 if(taken==TAKEN && i==(ba[i]-start)>>2 && source[i+1]==0) {
4911 // Idle loop
4912 if(count&1) emit_addimm_and_set_flags(2*(count+2),HOST_CCREG);
b14b6a8f 4913 idle=out;
57871462 4914 //emit_subfrommem(&idlecount,HOST_CCREG); // Count idle cycles
4915 emit_andimm(HOST_CCREG,3,HOST_CCREG);
b14b6a8f 4916 jaddr=out;
57871462 4917 emit_jmp(0);
4918 }
4919 else if(*adj==0||invert) {
2330734f 4920 int cycles = count_plus2;
b6e87b2b 4921 // faster loop HACK
bb4f300c 4922#if 0
b6e87b2b 4923 if (t&&*adj) {
4924 int rel=t-i;
4925 if(-NO_CYCLE_PENALTY_THR<rel&&rel<0)
2330734f 4926 cycles=*adj+count+2-*adj;
b6e87b2b 4927 }
bb4f300c 4928#endif
2330734f 4929 emit_addimm_and_set_flags(cycles, HOST_CCREG);
4930 jaddr = out;
57871462 4931 emit_jns(0);
4932 }
4933 else
4934 {
2330734f 4935 emit_cmpimm(HOST_CCREG, -count_plus2);
4936 jaddr = out;
57871462 4937 emit_jns(0);
4938 }
2330734f 4939 add_stub(CC_STUB,jaddr,idle?idle:out,(*adj==0||invert||idle)?0:count_plus2,i,addr,taken,0);
57871462 4940}
4941
b14b6a8f 4942static void do_ccstub(int n)
57871462 4943{
4944 literal_pool(256);
d1e4ebd9 4945 assem_debug("do_ccstub %x\n",start+(u_int)stubs[n].b*4);
b14b6a8f 4946 set_jump_target(stubs[n].addr, out);
4947 int i=stubs[n].b;
4948 if(stubs[n].d==NULLDS) {
57871462 4949 // Delay slot instruction is nullified ("likely" branch)
ad49de89 4950 wb_dirtys(regs[i].regmap,regs[i].dirty);
57871462 4951 }
b14b6a8f 4952 else if(stubs[n].d!=TAKEN) {
ad49de89 4953 wb_dirtys(branch_regs[i].regmap,branch_regs[i].dirty);
57871462 4954 }
4955 else {
ad49de89 4956 if(internal_branch(ba[i]))
4957 wb_needed_dirtys(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]);
57871462 4958 }
b14b6a8f 4959 if(stubs[n].c!=-1)
57871462 4960 {
4961 // Save PC as return address
b14b6a8f 4962 emit_movimm(stubs[n].c,EAX);
643aeae3 4963 emit_writeword(EAX,&pcaddr);
57871462 4964 }
4965 else
4966 {
4967 // Return address depends on which way the branch goes
cf95b4f0 4968 if(dops[i].itype==CJUMP||dops[i].itype==SJUMP)
57871462 4969 {
cf95b4f0 4970 int s1l=get_reg(branch_regs[i].regmap,dops[i].rs1);
4971 int s2l=get_reg(branch_regs[i].regmap,dops[i].rs2);
4972 if(dops[i].rs1==0)
57871462 4973 {
ad49de89 4974 s1l=s2l;
4975 s2l=-1;
57871462 4976 }
cf95b4f0 4977 else if(dops[i].rs2==0)
57871462 4978 {
ad49de89 4979 s2l=-1;
57871462 4980 }
4981 assert(s1l>=0);
4982 #ifdef DESTRUCTIVE_WRITEBACK
cf95b4f0 4983 if(dops[i].rs1) {
ad49de89 4984 if((branch_regs[i].dirty>>s1l)&&1)
cf95b4f0 4985 emit_loadreg(dops[i].rs1,s1l);
9f51b4b9 4986 }
57871462 4987 else {
ad49de89 4988 if((branch_regs[i].dirty>>s1l)&1)
cf95b4f0 4989 emit_loadreg(dops[i].rs2,s1l);
57871462 4990 }
4991 if(s2l>=0)
ad49de89 4992 if((branch_regs[i].dirty>>s2l)&1)
cf95b4f0 4993 emit_loadreg(dops[i].rs2,s2l);
57871462 4994 #endif
4995 int hr=0;
5194fb95 4996 int addr=-1,alt=-1,ntaddr=-1;
57871462 4997 while(hr<HOST_REGS)
4998 {
4999 if(hr!=EXCLUDE_REG && hr!=HOST_CCREG &&
9de8a0c3 5000 branch_regs[i].regmap[hr]!=dops[i].rs1 &&
5001 branch_regs[i].regmap[hr]!=dops[i].rs2 )
57871462 5002 {
5003 addr=hr++;break;
5004 }
5005 hr++;
5006 }
5007 while(hr<HOST_REGS)
5008 {
5009 if(hr!=EXCLUDE_REG && hr!=HOST_CCREG &&
9de8a0c3 5010 branch_regs[i].regmap[hr]!=dops[i].rs1 &&
5011 branch_regs[i].regmap[hr]!=dops[i].rs2 )
57871462 5012 {
5013 alt=hr++;break;
5014 }
5015 hr++;
5016 }
cf95b4f0 5017 if((dops[i].opcode&0x2E)==6) // BLEZ/BGTZ needs another register
57871462 5018 {
5019 while(hr<HOST_REGS)
5020 {
5021 if(hr!=EXCLUDE_REG && hr!=HOST_CCREG &&
9de8a0c3 5022 branch_regs[i].regmap[hr]!=dops[i].rs1 &&
5023 branch_regs[i].regmap[hr]!=dops[i].rs2 )
57871462 5024 {
5025 ntaddr=hr;break;
5026 }
5027 hr++;
5028 }
5029 assert(hr<HOST_REGS);
5030 }
cf95b4f0 5031 if((dops[i].opcode&0x2f)==4) // BEQ
57871462 5032 {
5033 #ifdef HAVE_CMOV_IMM
ad49de89 5034 if(s2l>=0) emit_cmp(s1l,s2l);
5035 else emit_test(s1l,s1l);
5036 emit_cmov2imm_e_ne_compact(ba[i],start+i*4+8,addr);
5037 #else
5038 emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
5039 if(s2l>=0) emit_cmp(s1l,s2l);
5040 else emit_test(s1l,s1l);
5041 emit_cmovne_reg(alt,addr);
57871462 5042 #endif
57871462 5043 }
cf95b4f0 5044 if((dops[i].opcode&0x2f)==5) // BNE
57871462 5045 {
5046 #ifdef HAVE_CMOV_IMM
ad49de89 5047 if(s2l>=0) emit_cmp(s1l,s2l);
5048 else emit_test(s1l,s1l);
5049 emit_cmov2imm_e_ne_compact(start+i*4+8,ba[i],addr);
5050 #else
5051 emit_mov2imm_compact(start+i*4+8,addr,ba[i],alt);
5052 if(s2l>=0) emit_cmp(s1l,s2l);
5053 else emit_test(s1l,s1l);
5054 emit_cmovne_reg(alt,addr);
57871462 5055 #endif
57871462 5056 }
cf95b4f0 5057 if((dops[i].opcode&0x2f)==6) // BLEZ
57871462 5058 {
5059 //emit_movimm(ba[i],alt);
5060 //emit_movimm(start+i*4+8,addr);
5061 emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
5062 emit_cmpimm(s1l,1);
57871462 5063 emit_cmovl_reg(alt,addr);
57871462 5064 }
cf95b4f0 5065 if((dops[i].opcode&0x2f)==7) // BGTZ
57871462 5066 {
5067 //emit_movimm(ba[i],addr);
5068 //emit_movimm(start+i*4+8,ntaddr);
5069 emit_mov2imm_compact(ba[i],addr,start+i*4+8,ntaddr);
5070 emit_cmpimm(s1l,1);
57871462 5071 emit_cmovl_reg(ntaddr,addr);
57871462 5072 }
cf95b4f0 5073 if((dops[i].opcode==1)&&(dops[i].opcode2&0x2D)==0) // BLTZ
57871462 5074 {
5075 //emit_movimm(ba[i],alt);
5076 //emit_movimm(start+i*4+8,addr);
5077 emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
ad49de89 5078 emit_test(s1l,s1l);
57871462 5079 emit_cmovs_reg(alt,addr);
5080 }
cf95b4f0 5081 if((dops[i].opcode==1)&&(dops[i].opcode2&0x2D)==1) // BGEZ
57871462 5082 {
5083 //emit_movimm(ba[i],addr);
5084 //emit_movimm(start+i*4+8,alt);
5085 emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
ad49de89 5086 emit_test(s1l,s1l);
57871462 5087 emit_cmovs_reg(alt,addr);
5088 }
cf95b4f0 5089 if(dops[i].opcode==0x11 && dops[i].opcode2==0x08 ) {
57871462 5090 if(source[i]&0x10000) // BC1T
5091 {
5092 //emit_movimm(ba[i],alt);
5093 //emit_movimm(start+i*4+8,addr);
5094 emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
5095 emit_testimm(s1l,0x800000);
5096 emit_cmovne_reg(alt,addr);
5097 }
5098 else // BC1F
5099 {
5100 //emit_movimm(ba[i],addr);
5101 //emit_movimm(start+i*4+8,alt);
5102 emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
5103 emit_testimm(s1l,0x800000);
5104 emit_cmovne_reg(alt,addr);
5105 }
5106 }
643aeae3 5107 emit_writeword(addr,&pcaddr);
57871462 5108 }
5109 else
cf95b4f0 5110 if(dops[i].itype==RJUMP)
57871462 5111 {
cf95b4f0 5112 int r=get_reg(branch_regs[i].regmap,dops[i].rs1);
4919de1e 5113 if (ds_writes_rjump_rs(i)) {
57871462 5114 r=get_reg(branch_regs[i].regmap,RTEMP);
5115 }
643aeae3 5116 emit_writeword(r,&pcaddr);
57871462 5117 }
7c3a5182 5118 else {SysPrintf("Unknown branch type in do_ccstub\n");abort();}
57871462 5119 }
5120 // Update cycle count
5121 assert(branch_regs[i].regmap[HOST_CCREG]==CCREG||branch_regs[i].regmap[HOST_CCREG]==-1);
2330734f 5122 if(stubs[n].a) emit_addimm(HOST_CCREG,(int)stubs[n].a,HOST_CCREG);
2a014d73 5123 emit_far_call(cc_interrupt);
2330734f 5124 if(stubs[n].a) emit_addimm(HOST_CCREG,-(int)stubs[n].a,HOST_CCREG);
b14b6a8f 5125 if(stubs[n].d==TAKEN) {
ad49de89 5126 if(internal_branch(ba[i]))
57871462 5127 load_needed_regs(branch_regs[i].regmap,regs[(ba[i]-start)>>2].regmap_entry);
cf95b4f0 5128 else if(dops[i].itype==RJUMP) {
57871462 5129 if(get_reg(branch_regs[i].regmap,RTEMP)>=0)
643aeae3 5130 emit_readword(&pcaddr,get_reg(branch_regs[i].regmap,RTEMP));
57871462 5131 else
cf95b4f0 5132 emit_loadreg(dops[i].rs1,get_reg(branch_regs[i].regmap,dops[i].rs1));
57871462 5133 }
b14b6a8f 5134 }else if(stubs[n].d==NOTTAKEN) {
57871462 5135 if(i<slen-2) load_needed_regs(branch_regs[i].regmap,regmap_pre[i+2]);
5136 else load_all_regs(branch_regs[i].regmap);
b14b6a8f 5137 }else if(stubs[n].d==NULLDS) {
57871462 5138 // Delay slot instruction is nullified ("likely" branch)
5139 if(i<slen-2) load_needed_regs(regs[i].regmap,regmap_pre[i+2]);
5140 else load_all_regs(regs[i].regmap);
5141 }else{
5142 load_all_regs(branch_regs[i].regmap);
5143 }
d1e4ebd9 5144 if (stubs[n].retaddr)
5145 emit_jmp(stubs[n].retaddr);
5146 else
5147 do_jump_vaddr(stubs[n].e);
57871462 5148}
5149
643aeae3 5150static void add_to_linker(void *addr, u_int target, int ext)
57871462 5151{
643aeae3 5152 assert(linkcount < ARRAY_SIZE(link_addr));
5153 link_addr[linkcount].addr = addr;
5154 link_addr[linkcount].target = target;
5155 link_addr[linkcount].ext = ext;
57871462 5156 linkcount++;
5157}
5158
eba830cd 5159static void ujump_assemble_write_ra(int i)
5160{
5161 int rt;
5162 unsigned int return_address;
5163 rt=get_reg(branch_regs[i].regmap,31);
5164 assem_debug("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5165 //assert(rt>=0);
5166 return_address=start+i*4+8;
5167 if(rt>=0) {
5168 #ifdef USE_MINI_HT
cf95b4f0 5169 if(internal_branch(return_address)&&dops[i+1].rt1!=31) {
eba830cd 5170 int temp=-1; // note: must be ds-safe
5171 #ifdef HOST_TEMPREG
5172 temp=HOST_TEMPREG;
5173 #endif
5174 if(temp>=0) do_miniht_insert(return_address,rt,temp);
5175 else emit_movimm(return_address,rt);
5176 }
5177 else
5178 #endif
5179 {
5180 #ifdef REG_PREFETCH
9f51b4b9 5181 if(temp>=0)
eba830cd 5182 {
643aeae3 5183 if(i_regmap[temp]!=PTEMP) emit_movimm((uintptr_t)hash_table_get(return_address),temp);
eba830cd 5184 }
5185 #endif
5186 emit_movimm(return_address,rt); // PC into link register
5187 #ifdef IMM_PREFETCH
df4dc2b1 5188 emit_prefetch(hash_table_get(return_address));
eba830cd 5189 #endif
5190 }
5191 }
5192}
5193
2330734f 5194static void ujump_assemble(int i, const struct regstat *i_regs)
57871462 5195{
eba830cd 5196 int ra_done=0;
57871462 5197 if(i==(ba[i]-start)>>2) assem_debug("idle loop\n");
5198 address_generation(i+1,i_regs,regs[i].regmap_entry);
5199 #ifdef REG_PREFETCH
5200 int temp=get_reg(branch_regs[i].regmap,PTEMP);
cf95b4f0 5201 if(dops[i].rt1==31&&temp>=0)
57871462 5202 {
581335b0 5203 signed char *i_regmap=i_regs->regmap;
57871462 5204 int return_address=start+i*4+8;
9f51b4b9 5205 if(get_reg(branch_regs[i].regmap,31)>0)
643aeae3 5206 if(i_regmap[temp]==PTEMP) emit_movimm((uintptr_t)hash_table_get(return_address),temp);
57871462 5207 }
5208 #endif
cf95b4f0 5209 if(dops[i].rt1==31&&(dops[i].rt1==dops[i+1].rs1||dops[i].rt1==dops[i+1].rs2)) {
eba830cd 5210 ujump_assemble_write_ra(i); // writeback ra for DS
5211 ra_done=1;
57871462 5212 }
4ef8f67d 5213 ds_assemble(i+1,i_regs);
5214 uint64_t bc_unneeded=branch_regs[i].u;
cf95b4f0 5215 bc_unneeded|=1|(1LL<<dops[i].rt1);
ad49de89 5216 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,bc_unneeded);
53358c1d 5217 load_reg(regs[i].regmap,branch_regs[i].regmap,CCREG);
cf95b4f0 5218 if(!ra_done&&dops[i].rt1==31)
eba830cd 5219 ujump_assemble_write_ra(i);
57871462 5220 int cc,adj;
5221 cc=get_reg(branch_regs[i].regmap,CCREG);
5222 assert(cc==HOST_CCREG);
ad49de89 5223 store_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]);
57871462 5224 #ifdef REG_PREFETCH
cf95b4f0 5225 if(dops[i].rt1==31&&temp>=0) emit_prefetchreg(temp);
57871462 5226 #endif
5227 do_cc(i,branch_regs[i].regmap,&adj,ba[i],TAKEN,0);
2330734f 5228 if(adj) emit_addimm(cc, ccadj[i] + CLOCK_ADJUST(2) - adj, cc);
ad49de89 5229 load_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]);
5230 if(internal_branch(ba[i]))
57871462 5231 assem_debug("branch: internal\n");
5232 else
5233 assem_debug("branch: external\n");
cf95b4f0 5234 if (internal_branch(ba[i]) && dops[(ba[i]-start)>>2].is_ds) {
57871462 5235 ds_assemble_entry(i);
5236 }
5237 else {
ad49de89 5238 add_to_linker(out,ba[i],internal_branch(ba[i]));
57871462 5239 emit_jmp(0);
5240 }
5241}
5242
eba830cd 5243static void rjump_assemble_write_ra(int i)
5244{
5245 int rt,return_address;
cf95b4f0 5246 assert(dops[i+1].rt1!=dops[i].rt1);
5247 assert(dops[i+1].rt2!=dops[i].rt1);
5248 rt=get_reg(branch_regs[i].regmap,dops[i].rt1);
eba830cd 5249 assem_debug("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5250 assert(rt>=0);
5251 return_address=start+i*4+8;
5252 #ifdef REG_PREFETCH
9f51b4b9 5253 if(temp>=0)
eba830cd 5254 {
643aeae3 5255 if(i_regmap[temp]!=PTEMP) emit_movimm((uintptr_t)hash_table_get(return_address),temp);
eba830cd 5256 }
5257 #endif
5258 emit_movimm(return_address,rt); // PC into link register
5259 #ifdef IMM_PREFETCH
df4dc2b1 5260 emit_prefetch(hash_table_get(return_address));
eba830cd 5261 #endif
5262}
5263
2330734f 5264static void rjump_assemble(int i, const struct regstat *i_regs)
57871462 5265{
57871462 5266 int temp;
581335b0 5267 int rs,cc;
eba830cd 5268 int ra_done=0;
cf95b4f0 5269 rs=get_reg(branch_regs[i].regmap,dops[i].rs1);
57871462 5270 assert(rs>=0);
4919de1e 5271 if (ds_writes_rjump_rs(i)) {
57871462 5272 // Delay slot abuse, make a copy of the branch address register
5273 temp=get_reg(branch_regs[i].regmap,RTEMP);
5274 assert(temp>=0);
5275 assert(regs[i].regmap[temp]==RTEMP);
5276 emit_mov(rs,temp);
5277 rs=temp;
5278 }
5279 address_generation(i+1,i_regs,regs[i].regmap_entry);
5280 #ifdef REG_PREFETCH
cf95b4f0 5281 if(dops[i].rt1==31)
57871462 5282 {
5283 if((temp=get_reg(branch_regs[i].regmap,PTEMP))>=0) {
581335b0 5284 signed char *i_regmap=i_regs->regmap;
57871462 5285 int return_address=start+i*4+8;
643aeae3 5286 if(i_regmap[temp]==PTEMP) emit_movimm((uintptr_t)hash_table_get(return_address),temp);
57871462 5287 }
5288 }
5289 #endif
5290 #ifdef USE_MINI_HT
cf95b4f0 5291 if(dops[i].rs1==31) {
57871462 5292 int rh=get_reg(regs[i].regmap,RHASH);
5293 if(rh>=0) do_preload_rhash(rh);
5294 }
5295 #endif
cf95b4f0 5296 if(dops[i].rt1!=0&&(dops[i].rt1==dops[i+1].rs1||dops[i].rt1==dops[i+1].rs2)) {
eba830cd 5297 rjump_assemble_write_ra(i);
5298 ra_done=1;
57871462 5299 }
d5910d5d 5300 ds_assemble(i+1,i_regs);
5301 uint64_t bc_unneeded=branch_regs[i].u;
cf95b4f0 5302 bc_unneeded|=1|(1LL<<dops[i].rt1);
5303 bc_unneeded&=~(1LL<<dops[i].rs1);
ad49de89 5304 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,bc_unneeded);
cf95b4f0 5305 load_regs(regs[i].regmap,branch_regs[i].regmap,dops[i].rs1,CCREG);
5306 if(!ra_done&&dops[i].rt1!=0)
eba830cd 5307 rjump_assemble_write_ra(i);
57871462 5308 cc=get_reg(branch_regs[i].regmap,CCREG);
5309 assert(cc==HOST_CCREG);
581335b0 5310 (void)cc;
57871462 5311 #ifdef USE_MINI_HT
5312 int rh=get_reg(branch_regs[i].regmap,RHASH);
5313 int ht=get_reg(branch_regs[i].regmap,RHTBL);
cf95b4f0 5314 if(dops[i].rs1==31) {
57871462 5315 if(regs[i].regmap[rh]!=RHASH) do_preload_rhash(rh);
5316 do_preload_rhtbl(ht);
5317 do_rhash(rs,rh);
5318 }
5319 #endif
ad49de89 5320 store_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,-1);
57871462 5321 #ifdef DESTRUCTIVE_WRITEBACK
ad49de89 5322 if((branch_regs[i].dirty>>rs)&1) {
cf95b4f0 5323 if(dops[i].rs1!=dops[i+1].rt1&&dops[i].rs1!=dops[i+1].rt2) {
5324 emit_loadreg(dops[i].rs1,rs);
57871462 5325 }
5326 }
5327 #endif
5328 #ifdef REG_PREFETCH
cf95b4f0 5329 if(dops[i].rt1==31&&temp>=0) emit_prefetchreg(temp);
57871462 5330 #endif
5331 #ifdef USE_MINI_HT
cf95b4f0 5332 if(dops[i].rs1==31) {
57871462 5333 do_miniht_load(ht,rh);
5334 }
5335 #endif
5336 //do_cc(i,branch_regs[i].regmap,&adj,-1,TAKEN);
5337 //if(adj) emit_addimm(cc,2*(ccadj[i]+2-adj),cc); // ??? - Shouldn't happen
5338 //assert(adj==0);
2330734f 5339 emit_addimm_and_set_flags(ccadj[i] + CLOCK_ADJUST(2), HOST_CCREG);
d1e4ebd9 5340 add_stub(CC_STUB,out,NULL,0,i,-1,TAKEN,rs);
cf95b4f0 5341 if(dops[i+1].itype==COP0&&(source[i+1]&0x3f)==0x10)
911f2d55 5342 // special case for RFE
5343 emit_jmp(0);
5344 else
71e490c5 5345 emit_jns(0);
ad49de89 5346 //load_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,-1);
57871462 5347 #ifdef USE_MINI_HT
cf95b4f0 5348 if(dops[i].rs1==31) {
57871462 5349 do_miniht_jump(rs,rh,ht);
5350 }
5351 else
5352 #endif
5353 {
d1e4ebd9 5354 do_jump_vaddr(rs);
57871462 5355 }
57871462 5356 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
cf95b4f0 5357 if(dops[i].rt1!=31&&i<slen-2&&(((u_int)out)&7)) emit_mov(13,13);
57871462 5358 #endif
5359}
5360
2330734f 5361static void cjump_assemble(int i, const struct regstat *i_regs)
57871462 5362{
2330734f 5363 const signed char *i_regmap = i_regs->regmap;
57871462 5364 int cc;
5365 int match;
ad49de89 5366 match=match_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]);
57871462 5367 assem_debug("match=%d\n",match);
ad49de89 5368 int s1l,s2l;
57871462 5369 int unconditional=0,nop=0;
57871462 5370 int invert=0;
ad49de89 5371 int internal=internal_branch(ba[i]);
57871462 5372 if(i==(ba[i]-start)>>2) assem_debug("idle loop\n");
57871462 5373 if(!match) invert=1;
5374 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5375 if(i>(ba[i]-start)>>2) invert=1;
5376 #endif
3968e69e 5377 #ifdef __aarch64__
5378 invert=1; // because of near cond. branches
5379 #endif
9f51b4b9 5380
cf95b4f0 5381 if(dops[i].ooo) {
5382 s1l=get_reg(branch_regs[i].regmap,dops[i].rs1);
5383 s2l=get_reg(branch_regs[i].regmap,dops[i].rs2);
57871462 5384 }
5385 else {
cf95b4f0 5386 s1l=get_reg(i_regmap,dops[i].rs1);
5387 s2l=get_reg(i_regmap,dops[i].rs2);
57871462 5388 }
cf95b4f0 5389 if(dops[i].rs1==0&&dops[i].rs2==0)
57871462 5390 {
cf95b4f0 5391 if(dops[i].opcode&1) nop=1;
57871462 5392 else unconditional=1;
cf95b4f0 5393 //assert(dops[i].opcode!=5);
5394 //assert(dops[i].opcode!=7);
5395 //assert(dops[i].opcode!=0x15);
5396 //assert(dops[i].opcode!=0x17);
57871462 5397 }
cf95b4f0 5398 else if(dops[i].rs1==0)
57871462 5399 {
ad49de89 5400 s1l=s2l;
5401 s2l=-1;
57871462 5402 }
cf95b4f0 5403 else if(dops[i].rs2==0)
57871462 5404 {
ad49de89 5405 s2l=-1;
57871462 5406 }
5407
cf95b4f0 5408 if(dops[i].ooo) {
57871462 5409 // Out of order execution (delay slot first)
5410 //printf("OOOE\n");
5411 address_generation(i+1,i_regs,regs[i].regmap_entry);
5412 ds_assemble(i+1,i_regs);
5413 int adj;
5414 uint64_t bc_unneeded=branch_regs[i].u;
cf95b4f0 5415 bc_unneeded&=~((1LL<<dops[i].rs1)|(1LL<<dops[i].rs2));
57871462 5416 bc_unneeded|=1;
ad49de89 5417 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,bc_unneeded);
cf95b4f0 5418 load_regs(regs[i].regmap,branch_regs[i].regmap,dops[i].rs1,dops[i].rs2);
53358c1d 5419 load_reg(regs[i].regmap,branch_regs[i].regmap,CCREG);
57871462 5420 cc=get_reg(branch_regs[i].regmap,CCREG);
5421 assert(cc==HOST_CCREG);
9f51b4b9 5422 if(unconditional)
ad49de89 5423 store_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]);
57871462 5424 //do_cc(i,branch_regs[i].regmap,&adj,unconditional?ba[i]:-1,unconditional);
5425 //assem_debug("cycle count (adj)\n");
5426 if(unconditional) {
5427 do_cc(i,branch_regs[i].regmap,&adj,ba[i],TAKEN,0);
5428 if(i!=(ba[i]-start)>>2 || source[i+1]!=0) {
2330734f 5429 if(adj) emit_addimm(cc, ccadj[i] + CLOCK_ADJUST(2) - adj, cc);
ad49de89 5430 load_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]);
57871462 5431 if(internal)
5432 assem_debug("branch: internal\n");
5433 else
5434 assem_debug("branch: external\n");
cf95b4f0 5435 if (internal && dops[(ba[i]-start)>>2].is_ds) {
57871462 5436 ds_assemble_entry(i);
5437 }
5438 else {
643aeae3 5439 add_to_linker(out,ba[i],internal);
57871462 5440 emit_jmp(0);
5441 }
5442 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5443 if(((u_int)out)&7) emit_addnop(0);
5444 #endif
5445 }
5446 }
5447 else if(nop) {
2330734f 5448 emit_addimm_and_set_flags(ccadj[i] + CLOCK_ADJUST(2), cc);
b14b6a8f 5449 void *jaddr=out;
57871462 5450 emit_jns(0);
b14b6a8f 5451 add_stub(CC_STUB,jaddr,out,0,i,start+i*4+8,NOTTAKEN,0);
57871462 5452 }
5453 else {
df4dc2b1 5454 void *taken = NULL, *nottaken = NULL, *nottaken1 = NULL;
57871462 5455 do_cc(i,branch_regs[i].regmap,&adj,-1,0,invert);
2330734f 5456 if(adj&&!invert) emit_addimm(cc, ccadj[i] + CLOCK_ADJUST(2) - adj, cc);
9f51b4b9 5457
57871462 5458 //printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5459 assert(s1l>=0);
cf95b4f0 5460 if(dops[i].opcode==4) // BEQ
57871462 5461 {
5462 if(s2l>=0) emit_cmp(s1l,s2l);
5463 else emit_test(s1l,s1l);
5464 if(invert){
df4dc2b1 5465 nottaken=out;
7c3a5182 5466 emit_jne(DJT_1);
57871462 5467 }else{
643aeae3 5468 add_to_linker(out,ba[i],internal);
57871462 5469 emit_jeq(0);
5470 }
5471 }
cf95b4f0 5472 if(dops[i].opcode==5) // BNE
57871462 5473 {
5474 if(s2l>=0) emit_cmp(s1l,s2l);
5475 else emit_test(s1l,s1l);
5476 if(invert){
df4dc2b1 5477 nottaken=out;
7c3a5182 5478 emit_jeq(DJT_1);
57871462 5479 }else{
643aeae3 5480 add_to_linker(out,ba[i],internal);
57871462 5481 emit_jne(0);
5482 }
5483 }
cf95b4f0 5484 if(dops[i].opcode==6) // BLEZ
57871462 5485 {
5486 emit_cmpimm(s1l,1);
5487 if(invert){
df4dc2b1 5488 nottaken=out;
7c3a5182 5489 emit_jge(DJT_1);
57871462 5490 }else{
643aeae3 5491 add_to_linker(out,ba[i],internal);
57871462 5492 emit_jl(0);
5493 }
5494 }
cf95b4f0 5495 if(dops[i].opcode==7) // BGTZ
57871462 5496 {
5497 emit_cmpimm(s1l,1);
5498 if(invert){
df4dc2b1 5499 nottaken=out;
7c3a5182 5500 emit_jl(DJT_1);
57871462 5501 }else{
643aeae3 5502 add_to_linker(out,ba[i],internal);
57871462 5503 emit_jge(0);
5504 }
5505 }
5506 if(invert) {
df4dc2b1 5507 if(taken) set_jump_target(taken, out);
57871462 5508 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
cf95b4f0 5509 if (match && (!internal || !dops[(ba[i]-start)>>2].is_ds)) {
57871462 5510 if(adj) {
2330734f 5511 emit_addimm(cc,-adj,cc);
643aeae3 5512 add_to_linker(out,ba[i],internal);
57871462 5513 }else{
5514 emit_addnop(13);
643aeae3 5515 add_to_linker(out,ba[i],internal*2);
57871462 5516 }
5517 emit_jmp(0);
5518 }else
5519 #endif
5520 {
2330734f 5521 if(adj) emit_addimm(cc,-adj,cc);
ad49de89 5522 store_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]);
5523 load_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]);
57871462 5524 if(internal)
5525 assem_debug("branch: internal\n");
5526 else
5527 assem_debug("branch: external\n");
cf95b4f0 5528 if (internal && dops[(ba[i] - start) >> 2].is_ds) {
57871462 5529 ds_assemble_entry(i);
5530 }
5531 else {
643aeae3 5532 add_to_linker(out,ba[i],internal);
57871462 5533 emit_jmp(0);
5534 }
5535 }
df4dc2b1 5536 set_jump_target(nottaken, out);
57871462 5537 }
5538
df4dc2b1 5539 if(nottaken1) set_jump_target(nottaken1, out);
57871462 5540 if(adj) {
2330734f 5541 if(!invert) emit_addimm(cc,adj,cc);
57871462 5542 }
5543 } // (!unconditional)
5544 } // if(ooo)
5545 else
5546 {
5547 // In-order execution (branch first)
df4dc2b1 5548 void *taken = NULL, *nottaken = NULL, *nottaken1 = NULL;
57871462 5549 if(!unconditional&&!nop) {
57871462 5550 //printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5551 assert(s1l>=0);
cf95b4f0 5552 if((dops[i].opcode&0x2f)==4) // BEQ
57871462 5553 {
5554 if(s2l>=0) emit_cmp(s1l,s2l);
5555 else emit_test(s1l,s1l);
df4dc2b1 5556 nottaken=out;
7c3a5182 5557 emit_jne(DJT_2);
57871462 5558 }
cf95b4f0 5559 if((dops[i].opcode&0x2f)==5) // BNE
57871462 5560 {
5561 if(s2l>=0) emit_cmp(s1l,s2l);
5562 else emit_test(s1l,s1l);
df4dc2b1 5563 nottaken=out;
7c3a5182 5564 emit_jeq(DJT_2);
57871462 5565 }
cf95b4f0 5566 if((dops[i].opcode&0x2f)==6) // BLEZ
57871462 5567 {
5568 emit_cmpimm(s1l,1);
df4dc2b1 5569 nottaken=out;
7c3a5182 5570 emit_jge(DJT_2);
57871462 5571 }
cf95b4f0 5572 if((dops[i].opcode&0x2f)==7) // BGTZ
57871462 5573 {
5574 emit_cmpimm(s1l,1);
df4dc2b1 5575 nottaken=out;
7c3a5182 5576 emit_jl(DJT_2);
57871462 5577 }
5578 } // if(!unconditional)
5579 int adj;
5580 uint64_t ds_unneeded=branch_regs[i].u;
cf95b4f0 5581 ds_unneeded&=~((1LL<<dops[i+1].rs1)|(1LL<<dops[i+1].rs2));
57871462 5582 ds_unneeded|=1;
57871462 5583 // branch taken
5584 if(!nop) {
df4dc2b1 5585 if(taken) set_jump_target(taken, out);
57871462 5586 assem_debug("1:\n");
ad49de89 5587 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,ds_unneeded);
57871462 5588 // load regs
cf95b4f0 5589 load_regs(regs[i].regmap,branch_regs[i].regmap,dops[i+1].rs1,dops[i+1].rs2);
57871462 5590 address_generation(i+1,&branch_regs[i],0);
37387d8b 5591 if (ram_offset)
53358c1d 5592 load_reg(regs[i].regmap,branch_regs[i].regmap,ROREG);
ad49de89 5593 load_regs(regs[i].regmap,branch_regs[i].regmap,CCREG,INVCP);
57871462 5594 ds_assemble(i+1,&branch_regs[i]);
5595 cc=get_reg(branch_regs[i].regmap,CCREG);
5596 if(cc==-1) {
5597 emit_loadreg(CCREG,cc=HOST_CCREG);
5598 // CHECK: Is the following instruction (fall thru) allocated ok?
5599 }
5600 assert(cc==HOST_CCREG);
ad49de89 5601 store_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]);
57871462 5602 do_cc(i,i_regmap,&adj,ba[i],TAKEN,0);
5603 assem_debug("cycle count (adj)\n");
2330734f 5604 if(adj) emit_addimm(cc, ccadj[i] + CLOCK_ADJUST(2) - adj, cc);
ad49de89 5605 load_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]);
57871462 5606 if(internal)
5607 assem_debug("branch: internal\n");
5608 else
5609 assem_debug("branch: external\n");
cf95b4f0 5610 if (internal && dops[(ba[i] - start) >> 2].is_ds) {
57871462 5611 ds_assemble_entry(i);
5612 }
5613 else {
643aeae3 5614 add_to_linker(out,ba[i],internal);
57871462 5615 emit_jmp(0);
5616 }
5617 }
5618 // branch not taken
57871462 5619 if(!unconditional) {
df4dc2b1 5620 if(nottaken1) set_jump_target(nottaken1, out);
5621 set_jump_target(nottaken, out);
57871462 5622 assem_debug("2:\n");
fe807a8a 5623 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,ds_unneeded);
37387d8b 5624 // load regs
fe807a8a 5625 load_regs(regs[i].regmap,branch_regs[i].regmap,dops[i+1].rs1,dops[i+1].rs2);
5626 address_generation(i+1,&branch_regs[i],0);
37387d8b 5627 if (ram_offset)
53358c1d 5628 load_reg(regs[i].regmap,branch_regs[i].regmap,ROREG);
37387d8b 5629 load_regs(regs[i].regmap,branch_regs[i].regmap,CCREG,INVCP);
fe807a8a 5630 ds_assemble(i+1,&branch_regs[i]);
57871462 5631 cc=get_reg(branch_regs[i].regmap,CCREG);
fe807a8a 5632 if (cc == -1) {
57871462 5633 // Cycle count isn't in a register, temporarily load it then write it out
5634 emit_loadreg(CCREG,HOST_CCREG);
2330734f 5635 emit_addimm_and_set_flags(ccadj[i] + CLOCK_ADJUST(2), HOST_CCREG);
b14b6a8f 5636 void *jaddr=out;
57871462 5637 emit_jns(0);
b14b6a8f 5638 add_stub(CC_STUB,jaddr,out,0,i,start+i*4+8,NOTTAKEN,0);
57871462 5639 emit_storereg(CCREG,HOST_CCREG);
5640 }
5641 else{
5642 cc=get_reg(i_regmap,CCREG);
5643 assert(cc==HOST_CCREG);
2330734f 5644 emit_addimm_and_set_flags(ccadj[i] + CLOCK_ADJUST(2), cc);
b14b6a8f 5645 void *jaddr=out;
57871462 5646 emit_jns(0);
fe807a8a 5647 add_stub(CC_STUB,jaddr,out,0,i,start+i*4+8,NOTTAKEN,0);
57871462 5648 }
5649 }
5650 }
5651}
5652
2330734f 5653static void sjump_assemble(int i, const struct regstat *i_regs)
57871462 5654{
2330734f 5655 const signed char *i_regmap = i_regs->regmap;
57871462 5656 int cc;
5657 int match;
ad49de89 5658 match=match_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]);
2acc46cd 5659 assem_debug("smatch=%d ooo=%d\n", match, dops[i].ooo);
ad49de89 5660 int s1l;
57871462 5661 int unconditional=0,nevertaken=0;
57871462 5662 int invert=0;
ad49de89 5663 int internal=internal_branch(ba[i]);
57871462 5664 if(i==(ba[i]-start)>>2) assem_debug("idle loop\n");
57871462 5665 if(!match) invert=1;
5666 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5667 if(i>(ba[i]-start)>>2) invert=1;
5668 #endif
3968e69e 5669 #ifdef __aarch64__
5670 invert=1; // because of near cond. branches
5671 #endif
57871462 5672
cf95b4f0 5673 //if(dops[i].opcode2>=0x10) return; // FIXME (BxxZAL)
5674 //assert(dops[i].opcode2<0x10||dops[i].rs1==0); // FIXME (BxxZAL)
57871462 5675
cf95b4f0 5676 if(dops[i].ooo) {
5677 s1l=get_reg(branch_regs[i].regmap,dops[i].rs1);
57871462 5678 }
5679 else {
cf95b4f0 5680 s1l=get_reg(i_regmap,dops[i].rs1);
57871462 5681 }
cf95b4f0 5682 if(dops[i].rs1==0)
57871462 5683 {
cf95b4f0 5684 if(dops[i].opcode2&1) unconditional=1;
57871462 5685 else nevertaken=1;
5686 // These are never taken (r0 is never less than zero)
cf95b4f0 5687 //assert(dops[i].opcode2!=0);
5688 //assert(dops[i].opcode2!=2);
5689 //assert(dops[i].opcode2!=0x10);
5690 //assert(dops[i].opcode2!=0x12);
57871462 5691 }
57871462 5692
cf95b4f0 5693 if(dops[i].ooo) {
57871462 5694 // Out of order execution (delay slot first)
5695 //printf("OOOE\n");
5696 address_generation(i+1,i_regs,regs[i].regmap_entry);
5697 ds_assemble(i+1,i_regs);
5698 int adj;
5699 uint64_t bc_unneeded=branch_regs[i].u;
cf95b4f0 5700 bc_unneeded&=~((1LL<<dops[i].rs1)|(1LL<<dops[i].rs2));
57871462 5701 bc_unneeded|=1;
ad49de89 5702 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,bc_unneeded);
cf95b4f0 5703 load_regs(regs[i].regmap,branch_regs[i].regmap,dops[i].rs1,dops[i].rs1);
53358c1d 5704 load_reg(regs[i].regmap,branch_regs[i].regmap,CCREG);
cf95b4f0 5705 if(dops[i].rt1==31) {
57871462 5706 int rt,return_address;
57871462 5707 rt=get_reg(branch_regs[i].regmap,31);
5708 assem_debug("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5709 if(rt>=0) {
5710 // Save the PC even if the branch is not taken
5711 return_address=start+i*4+8;
5712 emit_movimm(return_address,rt); // PC into link register
5713 #ifdef IMM_PREFETCH
df4dc2b1 5714 if(!nevertaken) emit_prefetch(hash_table_get(return_address));
57871462 5715 #endif
5716 }
5717 }
5718 cc=get_reg(branch_regs[i].regmap,CCREG);
5719 assert(cc==HOST_CCREG);
9f51b4b9 5720 if(unconditional)
ad49de89 5721 store_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]);
57871462 5722 //do_cc(i,branch_regs[i].regmap,&adj,unconditional?ba[i]:-1,unconditional);
5723 assem_debug("cycle count (adj)\n");
5724 if(unconditional) {
5725 do_cc(i,branch_regs[i].regmap,&adj,ba[i],TAKEN,0);
5726 if(i!=(ba[i]-start)>>2 || source[i+1]!=0) {
2330734f 5727 if(adj) emit_addimm(cc, ccadj[i] + CLOCK_ADJUST(2) - adj, cc);
ad49de89 5728 load_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]);
57871462 5729 if(internal)
5730 assem_debug("branch: internal\n");
5731 else
5732 assem_debug("branch: external\n");
cf95b4f0 5733 if (internal && dops[(ba[i] - start) >> 2].is_ds) {
57871462 5734 ds_assemble_entry(i);
5735 }
5736 else {
643aeae3 5737 add_to_linker(out,ba[i],internal);
57871462 5738 emit_jmp(0);
5739 }
5740 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5741 if(((u_int)out)&7) emit_addnop(0);
5742 #endif
5743 }
5744 }
5745 else if(nevertaken) {
2330734f 5746 emit_addimm_and_set_flags(ccadj[i] + CLOCK_ADJUST(2), cc);
b14b6a8f 5747 void *jaddr=out;
57871462 5748 emit_jns(0);
b14b6a8f 5749 add_stub(CC_STUB,jaddr,out,0,i,start+i*4+8,NOTTAKEN,0);
57871462 5750 }
5751 else {
df4dc2b1 5752 void *nottaken = NULL;
57871462 5753 do_cc(i,branch_regs[i].regmap,&adj,-1,0,invert);
2330734f 5754 if(adj&&!invert) emit_addimm(cc, ccadj[i] + CLOCK_ADJUST(2) - adj, cc);
57871462 5755 {
5756 assert(s1l>=0);
cf95b4f0 5757 if((dops[i].opcode2&0xf)==0) // BLTZ/BLTZAL
57871462 5758 {
5759 emit_test(s1l,s1l);
5760 if(invert){
df4dc2b1 5761 nottaken=out;
7c3a5182 5762 emit_jns(DJT_1);
57871462 5763 }else{
643aeae3 5764 add_to_linker(out,ba[i],internal);
57871462 5765 emit_js(0);
5766 }
5767 }
cf95b4f0 5768 if((dops[i].opcode2&0xf)==1) // BGEZ/BLTZAL
57871462 5769 {
5770 emit_test(s1l,s1l);
5771 if(invert){
df4dc2b1 5772 nottaken=out;
7c3a5182 5773 emit_js(DJT_1);
57871462 5774 }else{
643aeae3 5775 add_to_linker(out,ba[i],internal);
57871462 5776 emit_jns(0);
5777 }
5778 }
ad49de89 5779 }
9f51b4b9 5780
57871462 5781 if(invert) {
5782 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
cf95b4f0 5783 if (match && (!internal || !dops[(ba[i] - start) >> 2].is_ds)) {
57871462 5784 if(adj) {
2330734f 5785 emit_addimm(cc,-adj,cc);
643aeae3 5786 add_to_linker(out,ba[i],internal);
57871462 5787 }else{
5788 emit_addnop(13);
643aeae3 5789 add_to_linker(out,ba[i],internal*2);
57871462 5790 }
5791 emit_jmp(0);
5792 }else
5793 #endif
5794 {
2330734f 5795 if(adj) emit_addimm(cc,-adj,cc);
ad49de89 5796 store_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]);
5797 load_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]);
57871462 5798 if(internal)
5799 assem_debug("branch: internal\n");
5800 else
5801 assem_debug("branch: external\n");
cf95b4f0 5802 if (internal && dops[(ba[i] - start) >> 2].is_ds) {
57871462 5803 ds_assemble_entry(i);
5804 }
5805 else {
643aeae3 5806 add_to_linker(out,ba[i],internal);
57871462 5807 emit_jmp(0);
5808 }
5809 }
df4dc2b1 5810 set_jump_target(nottaken, out);
57871462 5811 }
5812
5813 if(adj) {
2330734f 5814 if(!invert) emit_addimm(cc,adj,cc);
57871462 5815 }
5816 } // (!unconditional)
5817 } // if(ooo)
5818 else
5819 {
5820 // In-order execution (branch first)
5821 //printf("IOE\n");
df4dc2b1 5822 void *nottaken = NULL;
cf95b4f0 5823 if(dops[i].rt1==31) {
a6491170 5824 int rt,return_address;
a6491170 5825 rt=get_reg(branch_regs[i].regmap,31);
5826 if(rt>=0) {
5827 // Save the PC even if the branch is not taken
5828 return_address=start+i*4+8;
5829 emit_movimm(return_address,rt); // PC into link register
5830 #ifdef IMM_PREFETCH
df4dc2b1 5831 emit_prefetch(hash_table_get(return_address));
a6491170 5832 #endif
5833 }
5834 }
57871462 5835 if(!unconditional) {
5836 //printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
57871462 5837 assert(s1l>=0);
cf95b4f0 5838 if((dops[i].opcode2&0x0d)==0) // BLTZ/BLTZL/BLTZAL/BLTZALL
57871462 5839 {
5840 emit_test(s1l,s1l);
df4dc2b1 5841 nottaken=out;
7c3a5182 5842 emit_jns(DJT_1);
57871462 5843 }
cf95b4f0 5844 if((dops[i].opcode2&0x0d)==1) // BGEZ/BGEZL/BGEZAL/BGEZALL
57871462 5845 {
5846 emit_test(s1l,s1l);
df4dc2b1 5847 nottaken=out;
7c3a5182 5848 emit_js(DJT_1);
57871462 5849 }
57871462 5850 } // if(!unconditional)
5851 int adj;
5852 uint64_t ds_unneeded=branch_regs[i].u;
cf95b4f0 5853 ds_unneeded&=~((1LL<<dops[i+1].rs1)|(1LL<<dops[i+1].rs2));
57871462 5854 ds_unneeded|=1;
57871462 5855 // branch taken
5856 if(!nevertaken) {
5857 //assem_debug("1:\n");
ad49de89 5858 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,ds_unneeded);
57871462 5859 // load regs
cf95b4f0 5860 load_regs(regs[i].regmap,branch_regs[i].regmap,dops[i+1].rs1,dops[i+1].rs2);
57871462 5861 address_generation(i+1,&branch_regs[i],0);
37387d8b 5862 if (ram_offset)
53358c1d 5863 load_reg(regs[i].regmap,branch_regs[i].regmap,ROREG);
ad49de89 5864 load_regs(regs[i].regmap,branch_regs[i].regmap,CCREG,INVCP);
57871462 5865 ds_assemble(i+1,&branch_regs[i]);
5866 cc=get_reg(branch_regs[i].regmap,CCREG);
5867 if(cc==-1) {
5868 emit_loadreg(CCREG,cc=HOST_CCREG);
5869 // CHECK: Is the following instruction (fall thru) allocated ok?
5870 }
5871 assert(cc==HOST_CCREG);
ad49de89 5872 store_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]);
57871462 5873 do_cc(i,i_regmap,&adj,ba[i],TAKEN,0);
5874 assem_debug("cycle count (adj)\n");
2330734f 5875 if(adj) emit_addimm(cc, ccadj[i] + CLOCK_ADJUST(2) - adj, cc);
ad49de89 5876 load_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]);
57871462 5877 if(internal)
5878 assem_debug("branch: internal\n");
5879 else
5880 assem_debug("branch: external\n");
cf95b4f0 5881 if (internal && dops[(ba[i] - start) >> 2].is_ds) {
57871462 5882 ds_assemble_entry(i);
5883 }
5884 else {
643aeae3 5885 add_to_linker(out,ba[i],internal);
57871462 5886 emit_jmp(0);
5887 }
5888 }
5889 // branch not taken
57871462 5890 if(!unconditional) {
df4dc2b1 5891 set_jump_target(nottaken, out);
57871462 5892 assem_debug("1:\n");
fe807a8a 5893 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,ds_unneeded);
5894 load_regs(regs[i].regmap,branch_regs[i].regmap,dops[i+1].rs1,dops[i+1].rs2);
5895 address_generation(i+1,&branch_regs[i],0);
5a18ce2e 5896 if (ram_offset)
53358c1d 5897 load_reg(regs[i].regmap,branch_regs[i].regmap,ROREG);
5a18ce2e 5898 load_regs(regs[i].regmap,branch_regs[i].regmap,CCREG,INVCP);
fe807a8a 5899 ds_assemble(i+1,&branch_regs[i]);
57871462 5900 cc=get_reg(branch_regs[i].regmap,CCREG);
fe807a8a 5901 if (cc == -1) {
57871462 5902 // Cycle count isn't in a register, temporarily load it then write it out
5903 emit_loadreg(CCREG,HOST_CCREG);
2330734f 5904 emit_addimm_and_set_flags(ccadj[i] + CLOCK_ADJUST(2), HOST_CCREG);
b14b6a8f 5905 void *jaddr=out;
57871462 5906 emit_jns(0);
b14b6a8f 5907 add_stub(CC_STUB,jaddr,out,0,i,start+i*4+8,NOTTAKEN,0);
57871462 5908 emit_storereg(CCREG,HOST_CCREG);
5909 }
5910 else{
5911 cc=get_reg(i_regmap,CCREG);
5912 assert(cc==HOST_CCREG);
2330734f 5913 emit_addimm_and_set_flags(ccadj[i] + CLOCK_ADJUST(2), cc);
b14b6a8f 5914 void *jaddr=out;
57871462 5915 emit_jns(0);
fe807a8a 5916 add_stub(CC_STUB,jaddr,out,0,i,start+i*4+8,NOTTAKEN,0);
57871462 5917 }
5918 }
5919 }
5920}
5921
2330734f 5922static void pagespan_assemble(int i, const struct regstat *i_regs)
57871462 5923{
cf95b4f0 5924 int s1l=get_reg(i_regs->regmap,dops[i].rs1);
5925 int s2l=get_reg(i_regs->regmap,dops[i].rs2);
df4dc2b1 5926 void *taken = NULL;
5927 void *nottaken = NULL;
57871462 5928 int unconditional=0;
cf95b4f0 5929 if(dops[i].rs1==0)
57871462 5930 {
ad49de89 5931 s1l=s2l;
5932 s2l=-1;
57871462 5933 }
cf95b4f0 5934 else if(dops[i].rs2==0)
57871462 5935 {
ad49de89 5936 s2l=-1;
57871462 5937 }
5938 int hr=0;
581335b0 5939 int addr=-1,alt=-1,ntaddr=-1;
57871462 5940 if(i_regs->regmap[HOST_BTREG]<0) {addr=HOST_BTREG;}
5941 else {
5942 while(hr<HOST_REGS)
5943 {
5944 if(hr!=EXCLUDE_REG && hr!=HOST_CCREG &&
9de8a0c3 5945 i_regs->regmap[hr]!=dops[i].rs1 &&
5946 i_regs->regmap[hr]!=dops[i].rs2 )
57871462 5947 {
5948 addr=hr++;break;
5949 }
5950 hr++;
5951 }
5952 }
5953 while(hr<HOST_REGS)
5954 {
5955 if(hr!=EXCLUDE_REG && hr!=HOST_CCREG && hr!=HOST_BTREG &&
9de8a0c3 5956 i_regs->regmap[hr]!=dops[i].rs1 &&
5957 i_regs->regmap[hr]!=dops[i].rs2 )
57871462 5958 {
5959 alt=hr++;break;
5960 }
5961 hr++;
5962 }
cf95b4f0 5963 if((dops[i].opcode&0x2E)==6) // BLEZ/BGTZ needs another register
57871462 5964 {
5965 while(hr<HOST_REGS)
5966 {
5967 if(hr!=EXCLUDE_REG && hr!=HOST_CCREG && hr!=HOST_BTREG &&
9de8a0c3 5968 i_regs->regmap[hr]!=dops[i].rs1 &&
5969 i_regs->regmap[hr]!=dops[i].rs2 )
57871462 5970 {
5971 ntaddr=hr;break;
5972 }
5973 hr++;
5974 }
5975 }
5976 assert(hr<HOST_REGS);
cf95b4f0 5977 if((dops[i].opcode&0x2e)==4||dops[i].opcode==0x11) { // BEQ/BNE/BEQL/BNEL/BC1
53358c1d 5978 load_reg(regs[i].regmap_entry,regs[i].regmap,CCREG);
57871462 5979 }
2330734f 5980 emit_addimm(HOST_CCREG, ccadj[i] + CLOCK_ADJUST(2), HOST_CCREG);
cf95b4f0 5981 if(dops[i].opcode==2) // J
57871462 5982 {
5983 unconditional=1;
5984 }
cf95b4f0 5985 if(dops[i].opcode==3) // JAL
57871462 5986 {
5987 // TODO: mini_ht
5988 int rt=get_reg(i_regs->regmap,31);
5989 emit_movimm(start+i*4+8,rt);
5990 unconditional=1;
5991 }
cf95b4f0 5992 if(dops[i].opcode==0&&(dops[i].opcode2&0x3E)==8) // JR/JALR
57871462 5993 {
5994 emit_mov(s1l,addr);
cf95b4f0 5995 if(dops[i].opcode2==9) // JALR
57871462 5996 {
cf95b4f0 5997 int rt=get_reg(i_regs->regmap,dops[i].rt1);
57871462 5998 emit_movimm(start+i*4+8,rt);
5999 }
6000 }
cf95b4f0 6001 if((dops[i].opcode&0x3f)==4) // BEQ
57871462 6002 {
cf95b4f0 6003 if(dops[i].rs1==dops[i].rs2)
57871462 6004 {
6005 unconditional=1;
6006 }
6007 else
6008 #ifdef HAVE_CMOV_IMM
ad49de89 6009 if(1) {
57871462 6010 if(s2l>=0) emit_cmp(s1l,s2l);
6011 else emit_test(s1l,s1l);
6012 emit_cmov2imm_e_ne_compact(ba[i],start+i*4+8,addr);
6013 }
6014 else
6015 #endif
6016 {
6017 assert(s1l>=0);
6018 emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
57871462 6019 if(s2l>=0) emit_cmp(s1l,s2l);
6020 else emit_test(s1l,s1l);
6021 emit_cmovne_reg(alt,addr);
6022 }
6023 }
cf95b4f0 6024 if((dops[i].opcode&0x3f)==5) // BNE
57871462 6025 {
6026 #ifdef HAVE_CMOV_IMM
ad49de89 6027 if(s2l>=0) emit_cmp(s1l,s2l);
6028 else emit_test(s1l,s1l);
6029 emit_cmov2imm_e_ne_compact(start+i*4+8,ba[i],addr);
6030 #else
6031 assert(s1l>=0);
6032 emit_mov2imm_compact(start+i*4+8,addr,ba[i],alt);
6033 if(s2l>=0) emit_cmp(s1l,s2l);
6034 else emit_test(s1l,s1l);
6035 emit_cmovne_reg(alt,addr);
57871462 6036 #endif
57871462 6037 }
cf95b4f0 6038 if((dops[i].opcode&0x3f)==0x14) // BEQL
57871462 6039 {
57871462 6040 if(s2l>=0) emit_cmp(s1l,s2l);
6041 else emit_test(s1l,s1l);
df4dc2b1 6042 if(nottaken) set_jump_target(nottaken, out);
6043 nottaken=out;
57871462 6044 emit_jne(0);
6045 }
cf95b4f0 6046 if((dops[i].opcode&0x3f)==0x15) // BNEL
57871462 6047 {
57871462 6048 if(s2l>=0) emit_cmp(s1l,s2l);
6049 else emit_test(s1l,s1l);
df4dc2b1 6050 nottaken=out;
57871462 6051 emit_jeq(0);
df4dc2b1 6052 if(taken) set_jump_target(taken, out);
57871462 6053 }
cf95b4f0 6054 if((dops[i].opcode&0x3f)==6) // BLEZ
57871462 6055 {
6056 emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
6057 emit_cmpimm(s1l,1);
57871462 6058 emit_cmovl_reg(alt,addr);
57871462 6059 }
cf95b4f0 6060 if((dops[i].opcode&0x3f)==7) // BGTZ
57871462 6061 {
6062 emit_mov2imm_compact(ba[i],addr,start+i*4+8,ntaddr);
6063 emit_cmpimm(s1l,1);
57871462 6064 emit_cmovl_reg(ntaddr,addr);
57871462 6065 }
cf95b4f0 6066 if((dops[i].opcode&0x3f)==0x16) // BLEZL
57871462 6067 {
cf95b4f0 6068 assert((dops[i].opcode&0x3f)!=0x16);
57871462 6069 }
cf95b4f0 6070 if((dops[i].opcode&0x3f)==0x17) // BGTZL
57871462 6071 {
cf95b4f0 6072 assert((dops[i].opcode&0x3f)!=0x17);
57871462 6073 }
cf95b4f0 6074 assert(dops[i].opcode!=1); // BLTZ/BGEZ
57871462 6075
6076 //FIXME: Check CSREG
cf95b4f0 6077 if(dops[i].opcode==0x11 && dops[i].opcode2==0x08 ) {
57871462 6078 if((source[i]&0x30000)==0) // BC1F
6079 {
6080 emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
6081 emit_testimm(s1l,0x800000);
6082 emit_cmovne_reg(alt,addr);
6083 }
6084 if((source[i]&0x30000)==0x10000) // BC1T
6085 {
6086 emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
6087 emit_testimm(s1l,0x800000);
6088 emit_cmovne_reg(alt,addr);
6089 }
6090 if((source[i]&0x30000)==0x20000) // BC1FL
6091 {
6092 emit_testimm(s1l,0x800000);
df4dc2b1 6093 nottaken=out;
57871462 6094 emit_jne(0);
6095 }
6096 if((source[i]&0x30000)==0x30000) // BC1TL
6097 {
6098 emit_testimm(s1l,0x800000);
df4dc2b1 6099 nottaken=out;
57871462 6100 emit_jeq(0);
6101 }
6102 }
6103
6104 assert(i_regs->regmap[HOST_CCREG]==CCREG);
ad49de89 6105 wb_dirtys(regs[i].regmap,regs[i].dirty);
fe807a8a 6106 if(unconditional)
57871462 6107 {
6108 emit_movimm(ba[i],HOST_BTREG);
6109 }
6110 else if(addr!=HOST_BTREG)
6111 {
6112 emit_mov(addr,HOST_BTREG);
6113 }
6114 void *branch_addr=out;
6115 emit_jmp(0);
6116 int target_addr=start+i*4+5;
6117 void *stub=out;
6118 void *compiled_target_addr=check_addr(target_addr);
643aeae3 6119 emit_extjump_ds(branch_addr, target_addr);
57871462 6120 if(compiled_target_addr) {
df4dc2b1 6121 set_jump_target(branch_addr, compiled_target_addr);
3d680478 6122 add_jump_out(target_addr,stub);
57871462 6123 }
df4dc2b1 6124 else set_jump_target(branch_addr, stub);
57871462 6125}
6126
6127// Assemble the delay slot for the above
6128static void pagespan_ds()
6129{
6130 assem_debug("initial delay slot:\n");
6131 u_int vaddr=start+1;
94d23bb9 6132 u_int page=get_page(vaddr);
6133 u_int vpage=get_vpage(vaddr);
57871462 6134 ll_add(jump_dirty+vpage,vaddr,(void *)out);
3d680478 6135 do_dirty_stub_ds(slen*4);
57871462 6136 ll_add(jump_in+page,vaddr,(void *)out);
6137 assert(regs[0].regmap_entry[HOST_CCREG]==CCREG);
6138 if(regs[0].regmap[HOST_CCREG]!=CCREG)
ad49de89 6139 wb_register(CCREG,regs[0].regmap_entry,regs[0].wasdirty);
57871462 6140 if(regs[0].regmap[HOST_BTREG]!=BTREG)
643aeae3 6141 emit_writeword(HOST_BTREG,&branch_target);
cf95b4f0 6142 load_regs(regs[0].regmap_entry,regs[0].regmap,dops[0].rs1,dops[0].rs2);
57871462 6143 address_generation(0,&regs[0],regs[0].regmap_entry);
37387d8b 6144 if (ram_offset && (dops[0].is_load || dops[0].is_store))
53358c1d 6145 load_reg(regs[0].regmap_entry,regs[0].regmap,ROREG);
37387d8b 6146 if (dops[0].is_store)
53358c1d 6147 load_reg(regs[0].regmap_entry,regs[0].regmap,INVCP);
57871462 6148 is_delayslot=0;
2330734f 6149 switch (dops[0].itype) {
57871462 6150 case SYSCALL:
7139f3c8 6151 case HLECALL:
1e973cb0 6152 case INTCALL:
57871462 6153 case SPAN:
6154 case UJUMP:
6155 case RJUMP:
6156 case CJUMP:
6157 case SJUMP:
c43b5311 6158 SysPrintf("Jump in the delay slot. This is probably a bug.\n");
2330734f 6159 break;
6160 default:
6161 assemble(0, &regs[0], 0);
57871462 6162 }
6163 int btaddr=get_reg(regs[0].regmap,BTREG);
6164 if(btaddr<0) {
9de8a0c3 6165 btaddr=get_reg_temp(regs[0].regmap);
643aeae3 6166 emit_readword(&branch_target,btaddr);
57871462 6167 }
6168 assert(btaddr!=HOST_CCREG);
6169 if(regs[0].regmap[HOST_CCREG]!=CCREG) emit_loadreg(CCREG,HOST_CCREG);
6170#ifdef HOST_IMM8
d1e4ebd9 6171 host_tempreg_acquire();
57871462 6172 emit_movimm(start+4,HOST_TEMPREG);
6173 emit_cmp(btaddr,HOST_TEMPREG);
d1e4ebd9 6174 host_tempreg_release();
57871462 6175#else
6176 emit_cmpimm(btaddr,start+4);
6177#endif
df4dc2b1 6178 void *branch = out;
57871462 6179 emit_jeq(0);
ad49de89 6180 store_regs_bt(regs[0].regmap,regs[0].dirty,-1);
d1e4ebd9 6181 do_jump_vaddr(btaddr);
df4dc2b1 6182 set_jump_target(branch, out);
ad49de89 6183 store_regs_bt(regs[0].regmap,regs[0].dirty,start+4);
6184 load_regs_bt(regs[0].regmap,regs[0].dirty,start+4);
57871462 6185}
6186
670c0f22 6187static void check_regmap(signed char *regmap)
6188{
6189#ifndef NDEBUG
6190 int i,j;
6191 for (i = 0; i < HOST_REGS; i++) {
6192 if (regmap[i] < 0)
6193 continue;
6194 for (j = i + 1; j < HOST_REGS; j++)
6195 assert(regmap[i] != regmap[j]);
6196 }
6197#endif
6198}
6199
4600ba03 6200#ifdef DISASM
2acc46cd 6201#include <inttypes.h>
53dc27f6 6202static char insn[MAXBLOCK][10];
6203
6204#define set_mnemonic(i_, n_) \
6205 strcpy(insn[i_], n_)
6206
2acc46cd 6207void print_regmap(const char *name, const signed char *regmap)
6208{
6209 char buf[5];
6210 int i, l;
6211 fputs(name, stdout);
6212 for (i = 0; i < HOST_REGS; i++) {
6213 l = 0;
6214 if (regmap[i] >= 0)
6215 l = snprintf(buf, sizeof(buf), "$%d", regmap[i]);
6216 for (; l < 3; l++)
6217 buf[l] = ' ';
6218 buf[l] = 0;
6219 printf(" r%d=%s", i, buf);
6220 }
6221 fputs("\n", stdout);
6222}
6223
57871462 6224 /* disassembly */
6225void disassemble_inst(int i)
6226{
cf95b4f0 6227 if (dops[i].bt) printf("*"); else printf(" ");
6228 switch(dops[i].itype) {
57871462 6229 case UJUMP:
6230 printf (" %x: %s %8x\n",start+i*4,insn[i],ba[i]);break;
6231 case CJUMP:
cf95b4f0 6232 printf (" %x: %s r%d,r%d,%8x\n",start+i*4,insn[i],dops[i].rs1,dops[i].rs2,i?start+i*4+4+((signed int)((unsigned int)source[i]<<16)>>14):*ba);break;
57871462 6233 case SJUMP:
cf95b4f0 6234 printf (" %x: %s r%d,%8x\n",start+i*4,insn[i],dops[i].rs1,start+i*4+4+((signed int)((unsigned int)source[i]<<16)>>14));break;
57871462 6235 case RJUMP:
cf95b4f0 6236 if (dops[i].opcode==0x9&&dops[i].rt1!=31)
6237 printf (" %x: %s r%d,r%d\n",start+i*4,insn[i],dops[i].rt1,dops[i].rs1);
5067f341 6238 else
cf95b4f0 6239 printf (" %x: %s r%d\n",start+i*4,insn[i],dops[i].rs1);
5067f341 6240 break;
57871462 6241 case SPAN:
cf95b4f0 6242 printf (" %x: %s (pagespan) r%d,r%d,%8x\n",start+i*4,insn[i],dops[i].rs1,dops[i].rs2,ba[i]);break;
57871462 6243 case IMM16:
cf95b4f0 6244 if(dops[i].opcode==0xf) //LUI
6245 printf (" %x: %s r%d,%4x0000\n",start+i*4,insn[i],dops[i].rt1,imm[i]&0xffff);
57871462 6246 else
cf95b4f0 6247 printf (" %x: %s r%d,r%d,%d\n",start+i*4,insn[i],dops[i].rt1,dops[i].rs1,imm[i]);
57871462 6248 break;
6249 case LOAD:
6250 case LOADLR:
cf95b4f0 6251 printf (" %x: %s r%d,r%d+%x\n",start+i*4,insn[i],dops[i].rt1,dops[i].rs1,imm[i]);
57871462 6252 break;
6253 case STORE:
6254 case STORELR:
cf95b4f0 6255 printf (" %x: %s r%d,r%d+%x\n",start+i*4,insn[i],dops[i].rs2,dops[i].rs1,imm[i]);
57871462 6256 break;
6257 case ALU:
6258 case SHIFT:
cf95b4f0 6259 printf (" %x: %s r%d,r%d,r%d\n",start+i*4,insn[i],dops[i].rt1,dops[i].rs1,dops[i].rs2);
57871462 6260 break;
6261 case MULTDIV:
cf95b4f0 6262 printf (" %x: %s r%d,r%d\n",start+i*4,insn[i],dops[i].rs1,dops[i].rs2);
57871462 6263 break;
6264 case SHIFTIMM:
cf95b4f0 6265 printf (" %x: %s r%d,r%d,%d\n",start+i*4,insn[i],dops[i].rt1,dops[i].rs1,imm[i]);
57871462 6266 break;
6267 case MOV:
cf95b4f0 6268 if((dops[i].opcode2&0x1d)==0x10)
6269 printf (" %x: %s r%d\n",start+i*4,insn[i],dops[i].rt1);
6270 else if((dops[i].opcode2&0x1d)==0x11)
6271 printf (" %x: %s r%d\n",start+i*4,insn[i],dops[i].rs1);
57871462 6272 else
6273 printf (" %x: %s\n",start+i*4,insn[i]);
6274 break;
6275 case COP0:
cf95b4f0 6276 if(dops[i].opcode2==0)
6277 printf (" %x: %s r%d,cpr0[%d]\n",start+i*4,insn[i],dops[i].rt1,(source[i]>>11)&0x1f); // MFC0
6278 else if(dops[i].opcode2==4)
6279 printf (" %x: %s r%d,cpr0[%d]\n",start+i*4,insn[i],dops[i].rs1,(source[i]>>11)&0x1f); // MTC0
57871462 6280 else printf (" %x: %s\n",start+i*4,insn[i]);
6281 break;
6282 case COP1:
cf95b4f0 6283 if(dops[i].opcode2<3)
6284 printf (" %x: %s r%d,cpr1[%d]\n",start+i*4,insn[i],dops[i].rt1,(source[i]>>11)&0x1f); // MFC1
6285 else if(dops[i].opcode2>3)
6286 printf (" %x: %s r%d,cpr1[%d]\n",start+i*4,insn[i],dops[i].rs1,(source[i]>>11)&0x1f); // MTC1
57871462 6287 else printf (" %x: %s\n",start+i*4,insn[i]);
6288 break;
b9b61529 6289 case COP2:
cf95b4f0 6290 if(dops[i].opcode2<3)
6291 printf (" %x: %s r%d,cpr2[%d]\n",start+i*4,insn[i],dops[i].rt1,(source[i]>>11)&0x1f); // MFC2
6292 else if(dops[i].opcode2>3)
6293 printf (" %x: %s r%d,cpr2[%d]\n",start+i*4,insn[i],dops[i].rs1,(source[i]>>11)&0x1f); // MTC2
b9b61529 6294 else printf (" %x: %s\n",start+i*4,insn[i]);
6295 break;
57871462 6296 case C1LS:
cf95b4f0 6297 printf (" %x: %s cpr1[%d],r%d+%x\n",start+i*4,insn[i],(source[i]>>16)&0x1f,dops[i].rs1,imm[i]);
57871462 6298 break;
b9b61529 6299 case C2LS:
cf95b4f0 6300 printf (" %x: %s cpr2[%d],r%d+%x\n",start+i*4,insn[i],(source[i]>>16)&0x1f,dops[i].rs1,imm[i]);
b9b61529 6301 break;
1e973cb0 6302 case INTCALL:
6303 printf (" %x: %s (INTCALL)\n",start+i*4,insn[i]);
6304 break;
57871462 6305 default:
6306 //printf (" %s %8x\n",insn[i],source[i]);
6307 printf (" %x: %s\n",start+i*4,insn[i]);
6308 }
2acc46cd 6309 return;
6310 printf("D: %"PRIu64" WD: %"PRIu64" U: %"PRIu64"\n",
6311 regs[i].dirty, regs[i].wasdirty, unneeded_reg[i]);
6312 print_regmap("pre: ", regmap_pre[i]);
6313 print_regmap("entry: ", regs[i].regmap_entry);
6314 print_regmap("map: ", regs[i].regmap);
6315 if (dops[i].is_jump) {
6316 print_regmap("bentry:", branch_regs[i].regmap_entry);
6317 print_regmap("bmap: ", branch_regs[i].regmap);
6318 }
57871462 6319}
4600ba03 6320#else
53dc27f6 6321#define set_mnemonic(i_, n_)
4600ba03 6322static void disassemble_inst(int i) {}
6323#endif // DISASM
57871462 6324
d848b60a 6325#define DRC_TEST_VAL 0x74657374
6326
be516ebe 6327static void new_dynarec_test(void)
d848b60a 6328{
be516ebe 6329 int (*testfunc)(void);
d148d265 6330 void *beginning;
be516ebe 6331 int ret[2];
6332 size_t i;
d148d265 6333
687b4580 6334 // check structure linkage
7c3a5182 6335 if ((u_char *)rcnts - (u_char *)&psxRegs != sizeof(psxRegs))
687b4580 6336 {
7c3a5182 6337 SysPrintf("linkage_arm* miscompilation/breakage detected.\n");
687b4580 6338 }
6339
761fdd0a 6340 SysPrintf("testing if we can run recompiled code @%p...\n", out);
be516ebe 6341 ((volatile u_int *)out)[0]++; // make cache dirty
6342
6343 for (i = 0; i < ARRAY_SIZE(ret); i++) {
2a014d73 6344 out = ndrc->translation_cache;
be516ebe 6345 beginning = start_block();
6346 emit_movimm(DRC_TEST_VAL + i, 0); // test
6347 emit_ret();
6348 literal_pool(0);
6349 end_block(beginning);
6350 testfunc = beginning;
6351 ret[i] = testfunc();
6352 }
6353
6354 if (ret[0] == DRC_TEST_VAL && ret[1] == DRC_TEST_VAL + 1)
d848b60a 6355 SysPrintf("test passed.\n");
6356 else
be516ebe 6357 SysPrintf("test failed, will likely crash soon (r=%08x %08x)\n", ret[0], ret[1]);
2a014d73 6358 out = ndrc->translation_cache;
d848b60a 6359}
6360
dc990066 6361// clear the state completely, instead of just marking
6362// things invalid like invalidate_all_pages() does
919981d0 6363void new_dynarec_clear_full(void)
57871462 6364{
57871462 6365 int n;
2a014d73 6366 out = ndrc->translation_cache;
35775df7 6367 memset(invalid_code,1,sizeof(invalid_code));
6368 memset(hash_table,0xff,sizeof(hash_table));
57871462 6369 memset(mini_ht,-1,sizeof(mini_ht));
dc990066 6370 memset(shadow,0,sizeof(shadow));
57871462 6371 copy=shadow;
6372 expirep=16384; // Expiry pointer, +2 blocks
6373 pending_exception=0;
6374 literalcount=0;
57871462 6375 stop_after_jal=0;
9be4ba64 6376 inv_code_start=inv_code_end=~0;
7f94b097 6377 hack_addr=0;
39b71d9a 6378 f1_hack=0;
57871462 6379 // TLB
dc990066 6380 for(n=0;n<4096;n++) ll_clear(jump_in+n);
6381 for(n=0;n<4096;n++) ll_clear(jump_out+n);
6382 for(n=0;n<4096;n++) ll_clear(jump_dirty+n);
32631e6a 6383
6384 cycle_multiplier_old = cycle_multiplier;
6385 new_dynarec_hacks_old = new_dynarec_hacks;
dc990066 6386}
6387
919981d0 6388void new_dynarec_init(void)
dc990066 6389{
66ea165f 6390 SysPrintf("Init new dynarec, ndrc size %x\n", (int)sizeof(*ndrc));
1e212a25 6391
0aeb0cb9 6392#ifdef _3DS
6393 check_rosalina();
6394#endif
2a014d73 6395#ifdef BASE_ADDR_DYNAMIC
1e212a25 6396 #ifdef VITA
0aeb0cb9 6397 sceBlock = getVMBlock(); //sceKernelAllocMemBlockForVM("code", sizeof(*ndrc));
66ea165f 6398 if (sceBlock <= 0)
6399 SysPrintf("sceKernelAllocMemBlockForVM failed: %x\n", sceBlock);
2a014d73 6400 int ret = sceKernelGetMemBlockBase(sceBlock, (void **)&ndrc);
1e212a25 6401 if (ret < 0)
66ea165f 6402 SysPrintf("sceKernelGetMemBlockBase failed: %x\n", ret);
0aeb0cb9 6403 sceKernelOpenVMDomain();
6404 sceClibPrintf("translation_cache = 0x%08lx\n ", (long)ndrc->translation_cache);
6405 #elif defined(_MSC_VER)
6406 ndrc = VirtualAlloc(NULL, sizeof(*ndrc), MEM_COMMIT | MEM_RESERVE,
6407 PAGE_EXECUTE_READWRITE);
1e212a25 6408 #else
2a014d73 6409 uintptr_t desired_addr = 0;
6410 #ifdef __ELF__
6411 extern char _end;
6412 desired_addr = ((uintptr_t)&_end + 0xffffff) & ~0xffffffl;
6413 #endif
6414 ndrc = mmap((void *)desired_addr, sizeof(*ndrc),
1e212a25 6415 PROT_READ | PROT_WRITE | PROT_EXEC,
6416 MAP_PRIVATE | MAP_ANONYMOUS, -1, 0);
2a014d73 6417 if (ndrc == MAP_FAILED) {
d848b60a 6418 SysPrintf("mmap() failed: %s\n", strerror(errno));
1e212a25 6419 abort();
d848b60a 6420 }
1e212a25 6421 #endif
6422#else
6423 #ifndef NO_WRITE_EXEC
bdeade46 6424 // not all systems allow execute in data segment by default
761fdd0a 6425 // size must be 4K aligned for 3DS?
6426 if (mprotect(ndrc, sizeof(*ndrc),
2a014d73 6427 PROT_READ | PROT_WRITE | PROT_EXEC) != 0)
d848b60a 6428 SysPrintf("mprotect() failed: %s\n", strerror(errno));
1e212a25 6429 #endif
dc990066 6430#endif
2a014d73 6431 out = ndrc->translation_cache;
2573466a 6432 cycle_multiplier=200;
dc990066 6433 new_dynarec_clear_full();
6434#ifdef HOST_IMM8
6435 // Copy this into local area so we don't have to put it in every literal pool
6436 invc_ptr=invalid_code;
6437#endif
57871462 6438 arch_init();
d848b60a 6439 new_dynarec_test();
01d26796 6440 ram_offset=(uintptr_t)rdram-0x80000000;
b105cf4f 6441 if (ram_offset!=0)
c43b5311 6442 SysPrintf("warning: RAM is not directly mapped, performance will suffer\n");
398d6924 6443 SysPrintf("Mapped (RAM/scrp/ROM/LUTs/TC):\n");
6444 SysPrintf("%p/%p/%p/%p/%p\n", psxM, psxH, psxR, mem_rtab, out);
57871462 6445}
6446
919981d0 6447void new_dynarec_cleanup(void)
57871462 6448{
6449 int n;
2a014d73 6450#ifdef BASE_ADDR_DYNAMIC
1e212a25 6451 #ifdef VITA
66ea165f 6452 // sceBlock is managed by retroarch's bootstrap code
9c67c98f 6453 //sceKernelFreeMemBlock(sceBlock);
6454 //sceBlock = -1;
1e212a25 6455 #else
2a014d73 6456 if (munmap(ndrc, sizeof(*ndrc)) < 0)
1e212a25 6457 SysPrintf("munmap() failed\n");
bdeade46 6458 #endif
1e212a25 6459#endif
57871462 6460 for(n=0;n<4096;n++) ll_clear(jump_in+n);
6461 for(n=0;n<4096;n++) ll_clear(jump_out+n);
6462 for(n=0;n<4096;n++) ll_clear(jump_dirty+n);
6463 #ifdef ROM_COPY
c43b5311 6464 if (munmap (ROM_COPY, 67108864) < 0) {SysPrintf("munmap() failed\n");}
57871462 6465 #endif
ece032e6 6466 new_dynarec_print_stats();
57871462 6467}
6468
03f55e6b 6469static u_int *get_source_start(u_int addr, u_int *limit)
57871462 6470{
03f55e6b 6471 if (addr < 0x00200000 ||
a3203cf4 6472 (0xa0000000 <= addr && addr < 0xa0200000))
6473 {
03f55e6b 6474 // used for BIOS calls mostly?
6475 *limit = (addr&0xa0000000)|0x00200000;
01d26796 6476 return (u_int *)(rdram + (addr&0x1fffff));
03f55e6b 6477 }
6478 else if (!Config.HLE && (
6479 /* (0x9fc00000 <= addr && addr < 0x9fc80000) ||*/
a3203cf4 6480 (0xbfc00000 <= addr && addr < 0xbfc80000)))
6481 {
6482 // BIOS. The multiplier should be much higher as it's uncached 8bit mem,
6483 // but timings in PCSX are too tied to the interpreter's BIAS
d62c125a 6484 if (!HACK_ENABLED(NDHACK_OVERRIDE_CYCLE_M))
24058131 6485 cycle_multiplier_active = 200;
a3203cf4 6486
03f55e6b 6487 *limit = (addr & 0xfff00000) | 0x80000;
01d26796 6488 return (u_int *)((u_char *)psxR + (addr&0x7ffff));
03f55e6b 6489 }
6490 else if (addr >= 0x80000000 && addr < 0x80000000+RAM_SIZE) {
6491 *limit = (addr & 0x80600000) + 0x00200000;
01d26796 6492 return (u_int *)(rdram + (addr&0x1fffff));
03f55e6b 6493 }
581335b0 6494 return NULL;
03f55e6b 6495}
6496
6497static u_int scan_for_ret(u_int addr)
6498{
6499 u_int limit = 0;
6500 u_int *mem;
6501
6502 mem = get_source_start(addr, &limit);
6503 if (mem == NULL)
6504 return addr;
6505
6506 if (limit > addr + 0x1000)
6507 limit = addr + 0x1000;
6508 for (; addr < limit; addr += 4, mem++) {
6509 if (*mem == 0x03e00008) // jr $ra
6510 return addr + 8;
57871462 6511 }
581335b0 6512 return addr;
03f55e6b 6513}
6514
6515struct savestate_block {
6516 uint32_t addr;
6517 uint32_t regflags;
6518};
6519
6520static int addr_cmp(const void *p1_, const void *p2_)
6521{
6522 const struct savestate_block *p1 = p1_, *p2 = p2_;
6523 return p1->addr - p2->addr;
6524}
6525
6526int new_dynarec_save_blocks(void *save, int size)
6527{
6528 struct savestate_block *blocks = save;
6529 int maxcount = size / sizeof(blocks[0]);
6530 struct savestate_block tmp_blocks[1024];
6531 struct ll_entry *head;
6532 int p, s, d, o, bcnt;
6533 u_int addr;
6534
6535 o = 0;
b14b6a8f 6536 for (p = 0; p < ARRAY_SIZE(jump_in); p++) {
03f55e6b 6537 bcnt = 0;
6538 for (head = jump_in[p]; head != NULL; head = head->next) {
6539 tmp_blocks[bcnt].addr = head->vaddr;
6540 tmp_blocks[bcnt].regflags = head->reg_sv_flags;
6541 bcnt++;
6542 }
6543 if (bcnt < 1)
6544 continue;
6545 qsort(tmp_blocks, bcnt, sizeof(tmp_blocks[0]), addr_cmp);
6546
6547 addr = tmp_blocks[0].addr;
6548 for (s = d = 0; s < bcnt; s++) {
6549 if (tmp_blocks[s].addr < addr)
6550 continue;
6551 if (d == 0 || tmp_blocks[d-1].addr != tmp_blocks[s].addr)
6552 tmp_blocks[d++] = tmp_blocks[s];
6553 addr = scan_for_ret(tmp_blocks[s].addr);
6554 }
6555
6556 if (o + d > maxcount)
6557 d = maxcount - o;
6558 memcpy(&blocks[o], tmp_blocks, d * sizeof(blocks[0]));
6559 o += d;
6560 }
6561
6562 return o * sizeof(blocks[0]);
6563}
6564
6565void new_dynarec_load_blocks(const void *save, int size)
6566{
6567 const struct savestate_block *blocks = save;
6568 int count = size / sizeof(blocks[0]);
6569 u_int regs_save[32];
6570 uint32_t f;
6571 int i, b;
6572
6573 get_addr(psxRegs.pc);
6574
6575 // change GPRs for speculation to at least partially work..
6576 memcpy(regs_save, &psxRegs.GPR, sizeof(regs_save));
6577 for (i = 1; i < 32; i++)
6578 psxRegs.GPR.r[i] = 0x80000000;
6579
6580 for (b = 0; b < count; b++) {
6581 for (f = blocks[b].regflags, i = 0; f; f >>= 1, i++) {
6582 if (f & 1)
6583 psxRegs.GPR.r[i] = 0x1f800000;
6584 }
6585
6586 get_addr(blocks[b].addr);
6587
6588 for (f = blocks[b].regflags, i = 0; f; f >>= 1, i++) {
6589 if (f & 1)
6590 psxRegs.GPR.r[i] = 0x80000000;
6591 }
6592 }
6593
6594 memcpy(&psxRegs.GPR, regs_save, sizeof(regs_save));
6595}
6596
ece032e6 6597void new_dynarec_print_stats(void)
6598{
6599#ifdef STAT_PRINT
6600 printf("cc %3d,%3d,%3d lu%3d,%3d c%3d inv%3d,%3d tc_offs %zu\n",
6601 stat_bc_pre, stat_bc_direct, stat_bc_restore,
6602 stat_jump_in_lookups, stat_restore_tries, stat_restore_compares,
6603 stat_inv_addr_calls, stat_inv_hits,
6604 out - ndrc->translation_cache);
6605 stat_bc_direct = stat_bc_pre = stat_bc_restore =
6606 stat_jump_in_lookups = stat_restore_tries = stat_restore_compares =
6607 stat_inv_addr_calls = stat_inv_hits = 0;
6608#endif
6609}
6610
7f94b097 6611static int apply_hacks(void)
24058131 6612{
6613 int i;
6614 if (HACK_ENABLED(NDHACK_NO_COMPAT_HACKS))
7f94b097 6615 return 0;
24058131 6616 /* special hack(s) */
6617 for (i = 0; i < slen - 4; i++)
6618 {
6619 // lui a4, 0xf200; jal <rcnt_read>; addu a0, 2; slti v0, 28224
6620 if (source[i] == 0x3c04f200 && dops[i+1].itype == UJUMP
6621 && source[i+2] == 0x34840002 && dops[i+3].opcode == 0x0a
6622 && imm[i+3] == 0x6e40 && dops[i+3].rs1 == 2)
6623 {
6624 SysPrintf("PE2 hack @%08x\n", start + (i+3)*4);
6625 dops[i + 3].itype = NOP;
6626 }
6627 }
6628 i = slen;
6629 if (i > 10 && source[i-1] == 0 && source[i-2] == 0x03e00008
6630 && source[i-4] == 0x8fbf0018 && source[i-6] == 0x00c0f809
6631 && dops[i-7].itype == STORE)
6632 {
6633 i = i-8;
6634 if (dops[i].itype == IMM16)
6635 i--;
6636 // swl r2, 15(r6); swr r2, 12(r6); sw r6, *; jalr r6
6637 if (dops[i].itype == STORELR && dops[i].rs1 == 6
6638 && dops[i-1].itype == STORELR && dops[i-1].rs1 == 6)
6639 {
7f94b097 6640 SysPrintf("F1 hack from %08x, old dst %08x\n", start, hack_addr);
6641 f1_hack = 1;
6642 return 1;
24058131 6643 }
6644 }
7f94b097 6645 return 0;
24058131 6646}
6647
4149788d 6648static noinline void pass1_disassemble(u_int pagelimit)
03f55e6b 6649{
4149788d 6650 int i, j, done = 0, ni_count = 0;
57871462 6651 unsigned int type,op,op2;
6652
7ebfcedf 6653 for (i = 0; !done; i++)
6654 {
6655 memset(&dops[i], 0, sizeof(dops[i]));
cf95b4f0 6656 op2=0;
e1190b87 6657 minimum_free_regs[i]=0;
cf95b4f0 6658 dops[i].opcode=op=source[i]>>26;
57871462 6659 switch(op)
6660 {
53dc27f6 6661 case 0x00: set_mnemonic(i, "special"); type=NI;
57871462 6662 op2=source[i]&0x3f;
6663 switch(op2)
6664 {
53dc27f6 6665 case 0x00: set_mnemonic(i, "SLL"); type=SHIFTIMM; break;
6666 case 0x02: set_mnemonic(i, "SRL"); type=SHIFTIMM; break;
6667 case 0x03: set_mnemonic(i, "SRA"); type=SHIFTIMM; break;
6668 case 0x04: set_mnemonic(i, "SLLV"); type=SHIFT; break;
6669 case 0x06: set_mnemonic(i, "SRLV"); type=SHIFT; break;
6670 case 0x07: set_mnemonic(i, "SRAV"); type=SHIFT; break;
6671 case 0x08: set_mnemonic(i, "JR"); type=RJUMP; break;
6672 case 0x09: set_mnemonic(i, "JALR"); type=RJUMP; break;
6673 case 0x0C: set_mnemonic(i, "SYSCALL"); type=SYSCALL; break;
6674 case 0x0D: set_mnemonic(i, "BREAK"); type=SYSCALL; break;
6675 case 0x0F: set_mnemonic(i, "SYNC"); type=OTHER; break;
6676 case 0x10: set_mnemonic(i, "MFHI"); type=MOV; break;
6677 case 0x11: set_mnemonic(i, "MTHI"); type=MOV; break;
6678 case 0x12: set_mnemonic(i, "MFLO"); type=MOV; break;
6679 case 0x13: set_mnemonic(i, "MTLO"); type=MOV; break;
6680 case 0x18: set_mnemonic(i, "MULT"); type=MULTDIV; break;
6681 case 0x19: set_mnemonic(i, "MULTU"); type=MULTDIV; break;
6682 case 0x1A: set_mnemonic(i, "DIV"); type=MULTDIV; break;
6683 case 0x1B: set_mnemonic(i, "DIVU"); type=MULTDIV; break;
6684 case 0x20: set_mnemonic(i, "ADD"); type=ALU; break;
6685 case 0x21: set_mnemonic(i, "ADDU"); type=ALU; break;
6686 case 0x22: set_mnemonic(i, "SUB"); type=ALU; break;
6687 case 0x23: set_mnemonic(i, "SUBU"); type=ALU; break;
6688 case 0x24: set_mnemonic(i, "AND"); type=ALU; break;
6689 case 0x25: set_mnemonic(i, "OR"); type=ALU; break;
6690 case 0x26: set_mnemonic(i, "XOR"); type=ALU; break;
6691 case 0x27: set_mnemonic(i, "NOR"); type=ALU; break;
6692 case 0x2A: set_mnemonic(i, "SLT"); type=ALU; break;
6693 case 0x2B: set_mnemonic(i, "SLTU"); type=ALU; break;
6694 case 0x30: set_mnemonic(i, "TGE"); type=NI; break;
6695 case 0x31: set_mnemonic(i, "TGEU"); type=NI; break;
6696 case 0x32: set_mnemonic(i, "TLT"); type=NI; break;
6697 case 0x33: set_mnemonic(i, "TLTU"); type=NI; break;
6698 case 0x34: set_mnemonic(i, "TEQ"); type=NI; break;
6699 case 0x36: set_mnemonic(i, "TNE"); type=NI; break;
71e490c5 6700#if 0
53dc27f6 6701 case 0x14: set_mnemonic(i, "DSLLV"); type=SHIFT; break;
6702 case 0x16: set_mnemonic(i, "DSRLV"); type=SHIFT; break;
6703 case 0x17: set_mnemonic(i, "DSRAV"); type=SHIFT; break;
6704 case 0x1C: set_mnemonic(i, "DMULT"); type=MULTDIV; break;
6705 case 0x1D: set_mnemonic(i, "DMULTU"); type=MULTDIV; break;
6706 case 0x1E: set_mnemonic(i, "DDIV"); type=MULTDIV; break;
6707 case 0x1F: set_mnemonic(i, "DDIVU"); type=MULTDIV; break;
6708 case 0x2C: set_mnemonic(i, "DADD"); type=ALU; break;
6709 case 0x2D: set_mnemonic(i, "DADDU"); type=ALU; break;
6710 case 0x2E: set_mnemonic(i, "DSUB"); type=ALU; break;
6711 case 0x2F: set_mnemonic(i, "DSUBU"); type=ALU; break;
6712 case 0x38: set_mnemonic(i, "DSLL"); type=SHIFTIMM; break;
6713 case 0x3A: set_mnemonic(i, "DSRL"); type=SHIFTIMM; break;
6714 case 0x3B: set_mnemonic(i, "DSRA"); type=SHIFTIMM; break;
6715 case 0x3C: set_mnemonic(i, "DSLL32"); type=SHIFTIMM; break;
6716 case 0x3E: set_mnemonic(i, "DSRL32"); type=SHIFTIMM; break;
6717 case 0x3F: set_mnemonic(i, "DSRA32"); type=SHIFTIMM; break;
7f2607ea 6718#endif
57871462 6719 }
6720 break;
53dc27f6 6721 case 0x01: set_mnemonic(i, "regimm"); type=NI;
57871462 6722 op2=(source[i]>>16)&0x1f;
6723 switch(op2)
6724 {
53dc27f6 6725 case 0x00: set_mnemonic(i, "BLTZ"); type=SJUMP; break;
6726 case 0x01: set_mnemonic(i, "BGEZ"); type=SJUMP; break;
6727 //case 0x02: set_mnemonic(i, "BLTZL"); type=SJUMP; break;
6728 //case 0x03: set_mnemonic(i, "BGEZL"); type=SJUMP; break;
6729 //case 0x08: set_mnemonic(i, "TGEI"); type=NI; break;
6730 //case 0x09: set_mnemonic(i, "TGEIU"); type=NI; break;
6731 //case 0x0A: set_mnemonic(i, "TLTI"); type=NI; break;
6732 //case 0x0B: set_mnemonic(i, "TLTIU"); type=NI; break;
6733 //case 0x0C: set_mnemonic(i, "TEQI"); type=NI; break;
6734 //case 0x0E: set_mnemonic(i, "TNEI"); type=NI; break;
6735 case 0x10: set_mnemonic(i, "BLTZAL"); type=SJUMP; break;
6736 case 0x11: set_mnemonic(i, "BGEZAL"); type=SJUMP; break;
6737 //case 0x12: set_mnemonic(i, "BLTZALL"); type=SJUMP; break;
6738 //case 0x13: set_mnemonic(i, "BGEZALL"); type=SJUMP; break;
57871462 6739 }
6740 break;
53dc27f6 6741 case 0x02: set_mnemonic(i, "J"); type=UJUMP; break;
6742 case 0x03: set_mnemonic(i, "JAL"); type=UJUMP; break;
6743 case 0x04: set_mnemonic(i, "BEQ"); type=CJUMP; break;
6744 case 0x05: set_mnemonic(i, "BNE"); type=CJUMP; break;
6745 case 0x06: set_mnemonic(i, "BLEZ"); type=CJUMP; break;
6746 case 0x07: set_mnemonic(i, "BGTZ"); type=CJUMP; break;
6747 case 0x08: set_mnemonic(i, "ADDI"); type=IMM16; break;
6748 case 0x09: set_mnemonic(i, "ADDIU"); type=IMM16; break;
6749 case 0x0A: set_mnemonic(i, "SLTI"); type=IMM16; break;
6750 case 0x0B: set_mnemonic(i, "SLTIU"); type=IMM16; break;
6751 case 0x0C: set_mnemonic(i, "ANDI"); type=IMM16; break;
6752 case 0x0D: set_mnemonic(i, "ORI"); type=IMM16; break;
6753 case 0x0E: set_mnemonic(i, "XORI"); type=IMM16; break;
6754 case 0x0F: set_mnemonic(i, "LUI"); type=IMM16; break;
6755 case 0x10: set_mnemonic(i, "cop0"); type=NI;
57871462 6756 op2=(source[i]>>21)&0x1f;
6757 switch(op2)
6758 {
53dc27f6 6759 case 0x00: set_mnemonic(i, "MFC0"); type=COP0; break;
6760 case 0x02: set_mnemonic(i, "CFC0"); type=COP0; break;
6761 case 0x04: set_mnemonic(i, "MTC0"); type=COP0; break;
6762 case 0x06: set_mnemonic(i, "CTC0"); type=COP0; break;
6763 case 0x10: set_mnemonic(i, "RFE"); type=COP0; break;
57871462 6764 }
6765 break;
53dc27f6 6766 case 0x11: set_mnemonic(i, "cop1"); type=COP1;
57871462 6767 op2=(source[i]>>21)&0x1f;
57871462 6768 break;
71e490c5 6769#if 0
53dc27f6 6770 case 0x14: set_mnemonic(i, "BEQL"); type=CJUMP; break;
6771 case 0x15: set_mnemonic(i, "BNEL"); type=CJUMP; break;
6772 case 0x16: set_mnemonic(i, "BLEZL"); type=CJUMP; break;
6773 case 0x17: set_mnemonic(i, "BGTZL"); type=CJUMP; break;
6774 case 0x18: set_mnemonic(i, "DADDI"); type=IMM16; break;
6775 case 0x19: set_mnemonic(i, "DADDIU"); type=IMM16; break;
6776 case 0x1A: set_mnemonic(i, "LDL"); type=LOADLR; break;
6777 case 0x1B: set_mnemonic(i, "LDR"); type=LOADLR; break;
996cc15d 6778#endif
53dc27f6 6779 case 0x20: set_mnemonic(i, "LB"); type=LOAD; break;
6780 case 0x21: set_mnemonic(i, "LH"); type=LOAD; break;
6781 case 0x22: set_mnemonic(i, "LWL"); type=LOADLR; break;
6782 case 0x23: set_mnemonic(i, "LW"); type=LOAD; break;
6783 case 0x24: set_mnemonic(i, "LBU"); type=LOAD; break;
6784 case 0x25: set_mnemonic(i, "LHU"); type=LOAD; break;
6785 case 0x26: set_mnemonic(i, "LWR"); type=LOADLR; break;
71e490c5 6786#if 0
53dc27f6 6787 case 0x27: set_mnemonic(i, "LWU"); type=LOAD; break;
64bd6f82 6788#endif
53dc27f6 6789 case 0x28: set_mnemonic(i, "SB"); type=STORE; break;
6790 case 0x29: set_mnemonic(i, "SH"); type=STORE; break;
6791 case 0x2A: set_mnemonic(i, "SWL"); type=STORELR; break;
6792 case 0x2B: set_mnemonic(i, "SW"); type=STORE; break;
71e490c5 6793#if 0
53dc27f6 6794 case 0x2C: set_mnemonic(i, "SDL"); type=STORELR; break;
6795 case 0x2D: set_mnemonic(i, "SDR"); type=STORELR; break;
996cc15d 6796#endif
53dc27f6 6797 case 0x2E: set_mnemonic(i, "SWR"); type=STORELR; break;
6798 case 0x2F: set_mnemonic(i, "CACHE"); type=NOP; break;
6799 case 0x30: set_mnemonic(i, "LL"); type=NI; break;
6800 case 0x31: set_mnemonic(i, "LWC1"); type=C1LS; break;
71e490c5 6801#if 0
53dc27f6 6802 case 0x34: set_mnemonic(i, "LLD"); type=NI; break;
6803 case 0x35: set_mnemonic(i, "LDC1"); type=C1LS; break;
6804 case 0x37: set_mnemonic(i, "LD"); type=LOAD; break;
996cc15d 6805#endif
53dc27f6 6806 case 0x38: set_mnemonic(i, "SC"); type=NI; break;
6807 case 0x39: set_mnemonic(i, "SWC1"); type=C1LS; break;
71e490c5 6808#if 0
53dc27f6 6809 case 0x3C: set_mnemonic(i, "SCD"); type=NI; break;
6810 case 0x3D: set_mnemonic(i, "SDC1"); type=C1LS; break;
6811 case 0x3F: set_mnemonic(i, "SD"); type=STORE; break;
996cc15d 6812#endif
53dc27f6 6813 case 0x12: set_mnemonic(i, "COP2"); type=NI;
b9b61529 6814 op2=(source[i]>>21)&0x1f;
be516ebe 6815 //if (op2 & 0x10)
bedfea38 6816 if (source[i]&0x3f) { // use this hack to support old savestates with patched gte insns
c7abc864 6817 if (gte_handlers[source[i]&0x3f]!=NULL) {
53dc27f6 6818#ifdef DISASM
bedfea38 6819 if (gte_regnames[source[i]&0x3f]!=NULL)
6820 strcpy(insn[i],gte_regnames[source[i]&0x3f]);
6821 else
6822 snprintf(insn[i], sizeof(insn[i]), "COP2 %x", source[i]&0x3f);
53dc27f6 6823#endif
c7abc864 6824 type=C2OP;
6825 }
6826 }
6827 else switch(op2)
b9b61529 6828 {
53dc27f6 6829 case 0x00: set_mnemonic(i, "MFC2"); type=COP2; break;
6830 case 0x02: set_mnemonic(i, "CFC2"); type=COP2; break;
6831 case 0x04: set_mnemonic(i, "MTC2"); type=COP2; break;
6832 case 0x06: set_mnemonic(i, "CTC2"); type=COP2; break;
b9b61529 6833 }
6834 break;
53dc27f6 6835 case 0x32: set_mnemonic(i, "LWC2"); type=C2LS; break;
6836 case 0x3A: set_mnemonic(i, "SWC2"); type=C2LS; break;
6837 case 0x3B: set_mnemonic(i, "HLECALL"); type=HLECALL; break;
6838 default: set_mnemonic(i, "???"); type=NI;
4149788d 6839 SysPrintf("NI %08x @%08x (%08x)\n", source[i], start + i*4, start);
90ae6d4e 6840 break;
57871462 6841 }
cf95b4f0 6842 dops[i].itype=type;
6843 dops[i].opcode2=op2;
57871462 6844 /* Get registers/immediates */
53dc27f6 6845 dops[i].use_lt1=0;
bedfea38 6846 gte_rs[i]=gte_rt[i]=0;
57871462 6847 switch(type) {
6848 case LOAD:
cf95b4f0 6849 dops[i].rs1=(source[i]>>21)&0x1f;
6850 dops[i].rs2=0;
6851 dops[i].rt1=(source[i]>>16)&0x1f;
6852 dops[i].rt2=0;
57871462 6853 imm[i]=(short)source[i];
6854 break;
6855 case STORE:
6856 case STORELR:
cf95b4f0 6857 dops[i].rs1=(source[i]>>21)&0x1f;
6858 dops[i].rs2=(source[i]>>16)&0x1f;
6859 dops[i].rt1=0;
6860 dops[i].rt2=0;
57871462 6861 imm[i]=(short)source[i];
57871462 6862 break;
6863 case LOADLR:
6864 // LWL/LWR only load part of the register,
6865 // therefore the target register must be treated as a source too
cf95b4f0 6866 dops[i].rs1=(source[i]>>21)&0x1f;
6867 dops[i].rs2=(source[i]>>16)&0x1f;
6868 dops[i].rt1=(source[i]>>16)&0x1f;
6869 dops[i].rt2=0;
57871462 6870 imm[i]=(short)source[i];
57871462 6871 break;
6872 case IMM16:
cf95b4f0 6873 if (op==0x0f) dops[i].rs1=0; // LUI instruction has no source register
6874 else dops[i].rs1=(source[i]>>21)&0x1f;
6875 dops[i].rs2=0;
6876 dops[i].rt1=(source[i]>>16)&0x1f;
6877 dops[i].rt2=0;
57871462 6878 if(op>=0x0c&&op<=0x0e) { // ANDI/ORI/XORI
6879 imm[i]=(unsigned short)source[i];
6880 }else{
6881 imm[i]=(short)source[i];
6882 }
57871462 6883 break;
6884 case UJUMP:
cf95b4f0 6885 dops[i].rs1=0;
6886 dops[i].rs2=0;
6887 dops[i].rt1=0;
6888 dops[i].rt2=0;
57871462 6889 // The JAL instruction writes to r31.
6890 if (op&1) {
cf95b4f0 6891 dops[i].rt1=31;
57871462 6892 }
cf95b4f0 6893 dops[i].rs2=CCREG;
57871462 6894 break;
6895 case RJUMP:
cf95b4f0 6896 dops[i].rs1=(source[i]>>21)&0x1f;
6897 dops[i].rs2=0;
6898 dops[i].rt1=0;
6899 dops[i].rt2=0;
5067f341 6900 // The JALR instruction writes to rd.
57871462 6901 if (op2&1) {
cf95b4f0 6902 dops[i].rt1=(source[i]>>11)&0x1f;
57871462 6903 }
cf95b4f0 6904 dops[i].rs2=CCREG;
57871462 6905 break;
6906 case CJUMP:
cf95b4f0 6907 dops[i].rs1=(source[i]>>21)&0x1f;
6908 dops[i].rs2=(source[i]>>16)&0x1f;
6909 dops[i].rt1=0;
6910 dops[i].rt2=0;
57871462 6911 if(op&2) { // BGTZ/BLEZ
cf95b4f0 6912 dops[i].rs2=0;
57871462 6913 }
57871462 6914 break;
6915 case SJUMP:
cf95b4f0 6916 dops[i].rs1=(source[i]>>21)&0x1f;
6917 dops[i].rs2=CCREG;
6918 dops[i].rt1=0;
6919 dops[i].rt2=0;
57871462 6920 if(op2&0x10) { // BxxAL
cf95b4f0 6921 dops[i].rt1=31;
57871462 6922 // NOTE: If the branch is not taken, r31 is still overwritten
6923 }
57871462 6924 break;
57871462 6925 case ALU:
cf95b4f0 6926 dops[i].rs1=(source[i]>>21)&0x1f; // source
6927 dops[i].rs2=(source[i]>>16)&0x1f; // subtract amount
6928 dops[i].rt1=(source[i]>>11)&0x1f; // destination
6929 dops[i].rt2=0;
57871462 6930 break;
6931 case MULTDIV:
cf95b4f0 6932 dops[i].rs1=(source[i]>>21)&0x1f; // source
6933 dops[i].rs2=(source[i]>>16)&0x1f; // divisor
6934 dops[i].rt1=HIREG;
6935 dops[i].rt2=LOREG;
57871462 6936 break;
6937 case MOV:
cf95b4f0 6938 dops[i].rs1=0;
6939 dops[i].rs2=0;
6940 dops[i].rt1=0;
6941 dops[i].rt2=0;
6942 if(op2==0x10) dops[i].rs1=HIREG; // MFHI
6943 if(op2==0x11) dops[i].rt1=HIREG; // MTHI
6944 if(op2==0x12) dops[i].rs1=LOREG; // MFLO
6945 if(op2==0x13) dops[i].rt1=LOREG; // MTLO
6946 if((op2&0x1d)==0x10) dops[i].rt1=(source[i]>>11)&0x1f; // MFxx
6947 if((op2&0x1d)==0x11) dops[i].rs1=(source[i]>>21)&0x1f; // MTxx
57871462 6948 break;
6949 case SHIFT:
cf95b4f0 6950 dops[i].rs1=(source[i]>>16)&0x1f; // target of shift
6951 dops[i].rs2=(source[i]>>21)&0x1f; // shift amount
6952 dops[i].rt1=(source[i]>>11)&0x1f; // destination
6953 dops[i].rt2=0;
57871462 6954 break;
6955 case SHIFTIMM:
cf95b4f0 6956 dops[i].rs1=(source[i]>>16)&0x1f;
6957 dops[i].rs2=0;
6958 dops[i].rt1=(source[i]>>11)&0x1f;
6959 dops[i].rt2=0;
57871462 6960 imm[i]=(source[i]>>6)&0x1f;
6961 // DSxx32 instructions
6962 if(op2>=0x3c) imm[i]|=0x20;
57871462 6963 break;
6964 case COP0:
cf95b4f0 6965 dops[i].rs1=0;
6966 dops[i].rs2=0;
6967 dops[i].rt1=0;
6968 dops[i].rt2=0;
6969 if(op2==0||op2==2) dops[i].rt1=(source[i]>>16)&0x1F; // MFC0/CFC0
6970 if(op2==4||op2==6) dops[i].rs1=(source[i]>>16)&0x1F; // MTC0/CTC0
6971 if(op2==4&&((source[i]>>11)&0x1f)==12) dops[i].rt2=CSREG; // Status
6972 if(op2==16) if((source[i]&0x3f)==0x18) dops[i].rs2=CCREG; // ERET
57871462 6973 break;
6974 case COP1:
cf95b4f0 6975 dops[i].rs1=0;
6976 dops[i].rs2=0;
6977 dops[i].rt1=0;
6978 dops[i].rt2=0;
6979 if(op2<3) dops[i].rt1=(source[i]>>16)&0x1F; // MFC1/DMFC1/CFC1
6980 if(op2>3) dops[i].rs1=(source[i]>>16)&0x1F; // MTC1/DMTC1/CTC1
6981 dops[i].rs2=CSREG;
57871462 6982 break;
bedfea38 6983 case COP2:
cf95b4f0 6984 dops[i].rs1=0;
6985 dops[i].rs2=0;
6986 dops[i].rt1=0;
6987 dops[i].rt2=0;
6988 if(op2<3) dops[i].rt1=(source[i]>>16)&0x1F; // MFC2/CFC2
6989 if(op2>3) dops[i].rs1=(source[i]>>16)&0x1F; // MTC2/CTC2
6990 dops[i].rs2=CSREG;
bedfea38 6991 int gr=(source[i]>>11)&0x1F;
6992 switch(op2)
6993 {
6994 case 0x00: gte_rs[i]=1ll<<gr; break; // MFC2
6995 case 0x04: gte_rt[i]=1ll<<gr; break; // MTC2
0ff8c62c 6996 case 0x02: gte_rs[i]=1ll<<(gr+32); break; // CFC2
bedfea38 6997 case 0x06: gte_rt[i]=1ll<<(gr+32); break; // CTC2
6998 }
6999 break;
57871462 7000 case C1LS:
cf95b4f0 7001 dops[i].rs1=(source[i]>>21)&0x1F;
7002 dops[i].rs2=CSREG;
7003 dops[i].rt1=0;
7004 dops[i].rt2=0;
57871462 7005 imm[i]=(short)source[i];
7006 break;
b9b61529 7007 case C2LS:
cf95b4f0 7008 dops[i].rs1=(source[i]>>21)&0x1F;
7009 dops[i].rs2=0;
7010 dops[i].rt1=0;
7011 dops[i].rt2=0;
b9b61529 7012 imm[i]=(short)source[i];
bedfea38 7013 if(op==0x32) gte_rt[i]=1ll<<((source[i]>>16)&0x1F); // LWC2
7014 else gte_rs[i]=1ll<<((source[i]>>16)&0x1F); // SWC2
7015 break;
7016 case C2OP:
cf95b4f0 7017 dops[i].rs1=0;
7018 dops[i].rs2=0;
7019 dops[i].rt1=0;
7020 dops[i].rt2=0;
2167bef6 7021 gte_rs[i]=gte_reg_reads[source[i]&0x3f];
7022 gte_rt[i]=gte_reg_writes[source[i]&0x3f];
7023 gte_rt[i]|=1ll<<63; // every op changes flags
587a5b1c 7024 if((source[i]&0x3f)==GTE_MVMVA) {
7025 int v = (source[i] >> 15) & 3;
7026 gte_rs[i]&=~0xe3fll;
7027 if(v==3) gte_rs[i]|=0xe00ll;
7028 else gte_rs[i]|=3ll<<(v*2);
7029 }
b9b61529 7030 break;
57871462 7031 case SYSCALL:
7139f3c8 7032 case HLECALL:
1e973cb0 7033 case INTCALL:
cf95b4f0 7034 dops[i].rs1=CCREG;
7035 dops[i].rs2=0;
7036 dops[i].rt1=0;
7037 dops[i].rt2=0;
57871462 7038 break;
7039 default:
cf95b4f0 7040 dops[i].rs1=0;
7041 dops[i].rs2=0;
7042 dops[i].rt1=0;
7043 dops[i].rt2=0;
57871462 7044 }
7045 /* Calculate branch target addresses */
7046 if(type==UJUMP)
7047 ba[i]=((start+i*4+4)&0xF0000000)|(((unsigned int)source[i]<<6)>>4);
cf95b4f0 7048 else if(type==CJUMP&&dops[i].rs1==dops[i].rs2&&(op&1))
57871462 7049 ba[i]=start+i*4+8; // Ignore never taken branch
cf95b4f0 7050 else if(type==SJUMP&&dops[i].rs1==0&&!(op2&1))
57871462 7051 ba[i]=start+i*4+8; // Ignore never taken branch
ad49de89 7052 else if(type==CJUMP||type==SJUMP)
57871462 7053 ba[i]=start+i*4+4+((signed int)((unsigned int)source[i]<<16)>>14);
7054 else ba[i]=-1;
4919de1e 7055
7056 /* simplify always (not)taken branches */
cf95b4f0 7057 if (type == CJUMP && dops[i].rs1 == dops[i].rs2) {
7058 dops[i].rs1 = dops[i].rs2 = 0;
4919de1e 7059 if (!(op & 1)) {
cf95b4f0 7060 dops[i].itype = type = UJUMP;
7061 dops[i].rs2 = CCREG;
4919de1e 7062 }
7063 }
cf95b4f0 7064 else if (type == SJUMP && dops[i].rs1 == 0 && (op2 & 1))
7065 dops[i].itype = type = UJUMP;
4919de1e 7066
fe807a8a 7067 dops[i].is_jump = (dops[i].itype == RJUMP || dops[i].itype == UJUMP || dops[i].itype == CJUMP || dops[i].itype == SJUMP);
7068 dops[i].is_ujump = (dops[i].itype == RJUMP || dops[i].itype == UJUMP); // || (source[i] >> 16) == 0x1000 // beq r0,r0
37387d8b 7069 dops[i].is_load = (dops[i].itype == LOAD || dops[i].itype == LOADLR || op == 0x32); // LWC2
7070 dops[i].is_store = (dops[i].itype == STORE || dops[i].itype == STORELR || op == 0x3a); // SWC2
fe807a8a 7071
4919de1e 7072 /* messy cases to just pass over to the interpreter */
fe807a8a 7073 if (i > 0 && dops[i-1].is_jump) {
3e535354 7074 int do_in_intrp=0;
7075 // branch in delay slot?
fe807a8a 7076 if (dops[i].is_jump) {
3e535354 7077 // don't handle first branch and call interpreter if it's hit
4149788d 7078 SysPrintf("branch in delay slot @%08x (%08x)\n", start + i*4, start);
3e535354 7079 do_in_intrp=1;
7080 }
7081 // basic load delay detection
cf95b4f0 7082 else if((type==LOAD||type==LOADLR||type==COP0||type==COP2||type==C2LS)&&dops[i].rt1!=0) {
3e535354 7083 int t=(ba[i-1]-start)/4;
cf95b4f0 7084 if(0 <= t && t < i &&(dops[i].rt1==dops[t].rs1||dops[i].rt1==dops[t].rs2)&&dops[t].itype!=CJUMP&&dops[t].itype!=SJUMP) {
3e535354 7085 // jump target wants DS result - potential load delay effect
4149788d 7086 SysPrintf("load delay @%08x (%08x)\n", start + i*4, start);
3e535354 7087 do_in_intrp=1;
cf95b4f0 7088 dops[t+1].bt=1; // expected return from interpreter
3e535354 7089 }
cf95b4f0 7090 else if(i>=2&&dops[i-2].rt1==2&&dops[i].rt1==2&&dops[i].rs1!=2&&dops[i].rs2!=2&&dops[i-1].rs1!=2&&dops[i-1].rs2!=2&&
fe807a8a 7091 !(i>=3&&dops[i-3].is_jump)) {
3e535354 7092 // v0 overwrite like this is a sign of trouble, bail out
4149788d 7093 SysPrintf("v0 overwrite @%08x (%08x)\n", start + i*4, start);
3e535354 7094 do_in_intrp=1;
7095 }
7096 }
7ebfcedf 7097 if (do_in_intrp) {
7098 memset(&dops[i-1], 0, sizeof(dops[i-1]));
7099 dops[i-1].itype = INTCALL;
7100 dops[i-1].rs1 = CCREG;
7101 ba[i-1] = -1;
7102 done = 2;
3e535354 7103 i--; // don't compile the DS
26869094 7104 }
3e535354 7105 }
4919de1e 7106
3e535354 7107 /* Is this the end of the block? */
fe807a8a 7108 if (i > 0 && dops[i-1].is_ujump) {
0787af86 7109 if (dops[i-1].rt1 == 0) { // not jal
7110 int found_bbranch = 0, t = (ba[i-1] - start) / 4;
7111 if ((u_int)(t - i) < 64 && start + (t+64)*4 < pagelimit) {
7112 // scan for a branch back to i+1
7113 for (j = t; j < t + 64; j++) {
7114 int tmpop = source[j] >> 26;
7115 if (tmpop == 1 || ((tmpop & ~3) == 4)) {
7116 int t2 = j + 1 + (int)(signed short)source[j];
7117 if (t2 == i + 1) {
7118 //printf("blk expand %08x<-%08x\n", start + (i+1)*4, start + j*4);
7119 found_bbranch = 1;
7120 break;
7121 }
7122 }
7123 }
7124 }
7125 if (!found_bbranch)
7126 done = 2;
57871462 7127 }
7128 else {
7129 if(stop_after_jal) done=1;
7130 // Stop on BREAK
7131 if((source[i+1]&0xfc00003f)==0x0d) done=1;
7132 }
7133 // Don't recompile stuff that's already compiled
7134 if(check_addr(start+i*4+4)) done=1;
7135 // Don't get too close to the limit
7136 if(i>MAXBLOCK/2) done=1;
7137 }
d1150cd6 7138 if (dops[i].itype == SYSCALL || dops[i].itype == HLECALL || dops[i].itype == INTCALL)
7139 done = stop_after_jal ? 1 : 2;
7140 if (done == 2) {
1e973cb0 7141 // Does the block continue due to a branch?
7142 for(j=i-1;j>=0;j--)
7143 {
2a706964 7144 if(ba[j]==start+i*4) done=j=0; // Branch into delay slot
1e973cb0 7145 if(ba[j]==start+i*4+4) done=j=0;
7146 if(ba[j]==start+i*4+8) done=j=0;
7147 }
7148 }
75dec299 7149 //assert(i<MAXBLOCK-1);
57871462 7150 if(start+i*4==pagelimit-4) done=1;
7151 assert(start+i*4<pagelimit);
7152 if (i==MAXBLOCK-1) done=1;
7153 // Stop if we're compiling junk
b4ab351d 7154 if(dops[i].itype == NI && (++ni_count > 8 || dops[i].opcode == 0x11)) {
57871462 7155 done=stop_after_jal=1;
c43b5311 7156 SysPrintf("Disabled speculative precompilation\n");
57871462 7157 }
7158 }
7159 slen=i;
fe807a8a 7160 if (dops[i-1].is_jump) {
57871462 7161 if(start+i*4==pagelimit) {
cf95b4f0 7162 dops[i-1].itype=SPAN;
57871462 7163 }
7164 }
4149788d 7165 assert(slen>0);
7166}
7167
7168// Basic liveness analysis for MIPS registers
7169static noinline void pass2_unneeded_regs(int istart,int iend,int r)
7170{
7171 int i;
7172 uint64_t u,gte_u,b,gte_b;
7173 uint64_t temp_u,temp_gte_u=0;
7174 uint64_t gte_u_unknown=0;
7175 if (HACK_ENABLED(NDHACK_GTE_UNNEEDED))
7176 gte_u_unknown=~0ll;
7177 if(iend==slen-1) {
7178 u=1;
7179 gte_u=gte_u_unknown;
7180 }else{
7181 //u=unneeded_reg[iend+1];
7182 u=1;
7183 gte_u=gte_unneeded[iend+1];
7184 }
7185
7186 for (i=iend;i>=istart;i--)
7187 {
7188 //printf("unneeded registers i=%d (%d,%d) r=%d\n",i,istart,iend,r);
7189 if(dops[i].is_jump)
7190 {
7191 // If subroutine call, flag return address as a possible branch target
7192 if(dops[i].rt1==31 && i<slen-2) dops[i+2].bt=1;
7193
7194 if(ba[i]<start || ba[i]>=(start+slen*4))
7195 {
7196 // Branch out of this block, flush all regs
7197 u=1;
7198 gte_u=gte_u_unknown;
7199 branch_unneeded_reg[i]=u;
7200 // Merge in delay slot
7201 u|=(1LL<<dops[i+1].rt1)|(1LL<<dops[i+1].rt2);
7202 u&=~((1LL<<dops[i+1].rs1)|(1LL<<dops[i+1].rs2));
7203 u|=1;
7204 gte_u|=gte_rt[i+1];
7205 gte_u&=~gte_rs[i+1];
7206 }
7207 else
7208 {
7209 // Internal branch, flag target
7210 dops[(ba[i]-start)>>2].bt=1;
7211 if(ba[i]<=start+i*4) {
7212 // Backward branch
7213 if(dops[i].is_ujump)
7214 {
7215 // Unconditional branch
7216 temp_u=1;
7217 temp_gte_u=0;
7218 } else {
7219 // Conditional branch (not taken case)
7220 temp_u=unneeded_reg[i+2];
7221 temp_gte_u&=gte_unneeded[i+2];
7222 }
7223 // Merge in delay slot
7224 temp_u|=(1LL<<dops[i+1].rt1)|(1LL<<dops[i+1].rt2);
7225 temp_u&=~((1LL<<dops[i+1].rs1)|(1LL<<dops[i+1].rs2));
7226 temp_u|=1;
7227 temp_gte_u|=gte_rt[i+1];
7228 temp_gte_u&=~gte_rs[i+1];
7229 temp_u|=(1LL<<dops[i].rt1)|(1LL<<dops[i].rt2);
7230 temp_u&=~((1LL<<dops[i].rs1)|(1LL<<dops[i].rs2));
7231 temp_u|=1;
7232 temp_gte_u|=gte_rt[i];
7233 temp_gte_u&=~gte_rs[i];
7234 unneeded_reg[i]=temp_u;
7235 gte_unneeded[i]=temp_gte_u;
7236 // Only go three levels deep. This recursion can take an
7237 // excessive amount of time if there are a lot of nested loops.
7238 if(r<2) {
7239 pass2_unneeded_regs((ba[i]-start)>>2,i-1,r+1);
7240 }else{
7241 unneeded_reg[(ba[i]-start)>>2]=1;
7242 gte_unneeded[(ba[i]-start)>>2]=gte_u_unknown;
7243 }
7244 } /*else*/ if(1) {
7245 if (dops[i].is_ujump)
7246 {
7247 // Unconditional branch
7248 u=unneeded_reg[(ba[i]-start)>>2];
7249 gte_u=gte_unneeded[(ba[i]-start)>>2];
7250 branch_unneeded_reg[i]=u;
7251 // Merge in delay slot
7252 u|=(1LL<<dops[i+1].rt1)|(1LL<<dops[i+1].rt2);
7253 u&=~((1LL<<dops[i+1].rs1)|(1LL<<dops[i+1].rs2));
7254 u|=1;
7255 gte_u|=gte_rt[i+1];
7256 gte_u&=~gte_rs[i+1];
7257 } else {
7258 // Conditional branch
7259 b=unneeded_reg[(ba[i]-start)>>2];
7260 gte_b=gte_unneeded[(ba[i]-start)>>2];
7261 branch_unneeded_reg[i]=b;
7262 // Branch delay slot
7263 b|=(1LL<<dops[i+1].rt1)|(1LL<<dops[i+1].rt2);
7264 b&=~((1LL<<dops[i+1].rs1)|(1LL<<dops[i+1].rs2));
7265 b|=1;
7266 gte_b|=gte_rt[i+1];
7267 gte_b&=~gte_rs[i+1];
7268 u&=b;
7269 gte_u&=gte_b;
7270 if(i<slen-1) {
7271 branch_unneeded_reg[i]&=unneeded_reg[i+2];
7272 } else {
7273 branch_unneeded_reg[i]=1;
7274 }
7275 }
7276 }
7277 }
7278 }
7279 else if(dops[i].itype==SYSCALL||dops[i].itype==HLECALL||dops[i].itype==INTCALL)
7280 {
7281 // SYSCALL instruction (software interrupt)
7282 u=1;
7283 }
7284 else if(dops[i].itype==COP0 && (source[i]&0x3f)==0x18)
7285 {
7286 // ERET instruction (return from interrupt)
7287 u=1;
7288 }
7289 //u=1; // DEBUG
7290 // Written registers are unneeded
7291 u|=1LL<<dops[i].rt1;
7292 u|=1LL<<dops[i].rt2;
7293 gte_u|=gte_rt[i];
7294 // Accessed registers are needed
7295 u&=~(1LL<<dops[i].rs1);
7296 u&=~(1LL<<dops[i].rs2);
7297 gte_u&=~gte_rs[i];
7298 if(gte_rs[i]&&dops[i].rt1&&(unneeded_reg[i+1]&(1ll<<dops[i].rt1)))
7299 gte_u|=gte_rs[i]&gte_unneeded[i+1]; // MFC2/CFC2 to dead register, unneeded
7300 // Source-target dependencies
7301 // R0 is always unneeded
7302 u|=1;
7303 // Save it
7304 unneeded_reg[i]=u;
7305 gte_unneeded[i]=gte_u;
7306 /*
7307 printf("ur (%d,%d) %x: ",istart,iend,start+i*4);
7308 printf("U:");
7309 int r;
7310 for(r=1;r<=CCREG;r++) {
7311 if((unneeded_reg[i]>>r)&1) {
7312 if(r==HIREG) printf(" HI");
7313 else if(r==LOREG) printf(" LO");
7314 else printf(" r%d",r);
7315 }
7316 }
7317 printf("\n");
7318 */
7319 }
7320}
57871462 7321
4149788d 7322static noinline void pass3_register_alloc(u_int addr)
7323{
57871462 7324 struct regstat current; // Current register allocations/status
6cc8d23c 7325 clear_all_regs(current.regmap_entry);
57871462 7326 clear_all_regs(current.regmap);
6cc8d23c 7327 current.wasdirty = current.dirty = 0;
7328 current.u = unneeded_reg[0];
7329 alloc_reg(&current, 0, CCREG);
7330 dirty_reg(&current, CCREG);
7331 current.wasconst = 0;
7332 current.isconst = 0;
7333 current.loadedconst = 0;
7334 current.waswritten = 0;
57871462 7335 int ds=0;
7336 int cc=0;
4149788d 7337 int hr;
7338 int i, j;
6ebf4adf 7339
4149788d 7340 if (addr & 1) {
57871462 7341 // First instruction is delay slot
7342 cc=-1;
cf95b4f0 7343 dops[1].bt=1;
57871462 7344 ds=1;
7345 unneeded_reg[0]=1;
57871462 7346 current.regmap[HOST_BTREG]=BTREG;
7347 }
9f51b4b9 7348
57871462 7349 for(i=0;i<slen;i++)
7350 {
cf95b4f0 7351 if(dops[i].bt)
57871462 7352 {
57871462 7353 for(hr=0;hr<HOST_REGS;hr++)
7354 {
7355 // Is this really necessary?
7356 if(current.regmap[hr]==0) current.regmap[hr]=-1;
7357 }
7358 current.isconst=0;
27727b63 7359 current.waswritten=0;
57871462 7360 }
24385cae 7361
57871462 7362 memcpy(regmap_pre[i],current.regmap,sizeof(current.regmap));
7363 regs[i].wasconst=current.isconst;
57871462 7364 regs[i].wasdirty=current.dirty;
6cc8d23c 7365 regs[i].dirty=0;
7366 regs[i].u=0;
7367 regs[i].isconst=0;
8575a877 7368 regs[i].loadedconst=0;
fe807a8a 7369 if (!dops[i].is_jump) {
57871462 7370 if(i+1<slen) {
cf95b4f0 7371 current.u=unneeded_reg[i+1]&~((1LL<<dops[i].rs1)|(1LL<<dops[i].rs2));
57871462 7372 current.u|=1;
57871462 7373 } else {
7374 current.u=1;
57871462 7375 }
7376 } else {
7377 if(i+1<slen) {
cf95b4f0 7378 current.u=branch_unneeded_reg[i]&~((1LL<<dops[i+1].rs1)|(1LL<<dops[i+1].rs2));
7379 current.u&=~((1LL<<dops[i].rs1)|(1LL<<dops[i].rs2));
57871462 7380 current.u|=1;
7ebfcedf 7381 } else {
7382 SysPrintf("oops, branch at end of block with no delay slot @%08x\n", start + i*4);
7383 abort();
7384 }
57871462 7385 }
cf95b4f0 7386 dops[i].is_ds=ds;
57871462 7387 if(ds) {
7388 ds=0; // Skip delay slot, already allocated as part of branch
7389 // ...but we need to alloc it in case something jumps here
7390 if(i+1<slen) {
7391 current.u=branch_unneeded_reg[i-1]&unneeded_reg[i+1];
57871462 7392 }else{
7393 current.u=branch_unneeded_reg[i-1];
57871462 7394 }
cf95b4f0 7395 current.u&=~((1LL<<dops[i].rs1)|(1LL<<dops[i].rs2));
57871462 7396 current.u|=1;
57871462 7397 struct regstat temp;
7398 memcpy(&temp,&current,sizeof(current));
7399 temp.wasdirty=temp.dirty;
57871462 7400 // TODO: Take into account unconditional branches, as below
7401 delayslot_alloc(&temp,i);
7402 memcpy(regs[i].regmap,temp.regmap,sizeof(temp.regmap));
7403 regs[i].wasdirty=temp.wasdirty;
57871462 7404 regs[i].dirty=temp.dirty;
57871462 7405 regs[i].isconst=0;
7406 regs[i].wasconst=0;
7407 current.isconst=0;
7408 // Create entry (branch target) regmap
7409 for(hr=0;hr<HOST_REGS;hr++)
7410 {
7411 int r=temp.regmap[hr];
7412 if(r>=0) {
7413 if(r!=regmap_pre[i][hr]) {
7414 regs[i].regmap_entry[hr]=-1;
7415 }
7416 else
7417 {
7c3a5182 7418 assert(r < 64);
57871462 7419 if((current.u>>r)&1) {
7420 regs[i].regmap_entry[hr]=-1;
7421 regs[i].regmap[hr]=-1;
7422 //Don't clear regs in the delay slot as the branch might need them
7423 //current.regmap[hr]=-1;
7424 }else
7425 regs[i].regmap_entry[hr]=r;
57871462 7426 }
7427 } else {
7428 // First instruction expects CCREG to be allocated
9f51b4b9 7429 if(i==0&&hr==HOST_CCREG)
57871462 7430 regs[i].regmap_entry[hr]=CCREG;
7431 else
7432 regs[i].regmap_entry[hr]=-1;
7433 }
7434 }
7435 }
7436 else { // Not delay slot
cf95b4f0 7437 switch(dops[i].itype) {
57871462 7438 case UJUMP:
7439 //current.isconst=0; // DEBUG
7440 //current.wasconst=0; // DEBUG
7441 //regs[i].wasconst=0; // DEBUG
cf95b4f0 7442 clear_const(&current,dops[i].rt1);
57871462 7443 alloc_cc(&current,i);
7444 dirty_reg(&current,CCREG);
cf95b4f0 7445 if (dops[i].rt1==31) {
57871462 7446 alloc_reg(&current,i,31);
7447 dirty_reg(&current,31);
cf95b4f0 7448 //assert(dops[i+1].rs1!=31&&dops[i+1].rs2!=31);
7449 //assert(dops[i+1].rt1!=dops[i].rt1);
57871462 7450 #ifdef REG_PREFETCH
7451 alloc_reg(&current,i,PTEMP);
7452 #endif
57871462 7453 }
cf95b4f0 7454 dops[i].ooo=1;
269bb29a 7455 delayslot_alloc(&current,i+1);
57871462 7456 //current.isconst=0; // DEBUG
7457 ds=1;
7458 //printf("i=%d, isconst=%x\n",i,current.isconst);
7459 break;
7460 case RJUMP:
7461 //current.isconst=0;
7462 //current.wasconst=0;
7463 //regs[i].wasconst=0;
cf95b4f0 7464 clear_const(&current,dops[i].rs1);
7465 clear_const(&current,dops[i].rt1);
57871462 7466 alloc_cc(&current,i);
7467 dirty_reg(&current,CCREG);
4919de1e 7468 if (!ds_writes_rjump_rs(i)) {
cf95b4f0 7469 alloc_reg(&current,i,dops[i].rs1);
7470 if (dops[i].rt1!=0) {
7471 alloc_reg(&current,i,dops[i].rt1);
7472 dirty_reg(&current,dops[i].rt1);
7473 assert(dops[i+1].rs1!=dops[i].rt1&&dops[i+1].rs2!=dops[i].rt1);
7474 assert(dops[i+1].rt1!=dops[i].rt1);
57871462 7475 #ifdef REG_PREFETCH
7476 alloc_reg(&current,i,PTEMP);
7477 #endif
7478 }
7479 #ifdef USE_MINI_HT
cf95b4f0 7480 if(dops[i].rs1==31) { // JALR
57871462 7481 alloc_reg(&current,i,RHASH);
57871462 7482 alloc_reg(&current,i,RHTBL);
57871462 7483 }
7484 #endif
7485 delayslot_alloc(&current,i+1);
7486 } else {
7487 // The delay slot overwrites our source register,
7488 // allocate a temporary register to hold the old value.
7489 current.isconst=0;
7490 current.wasconst=0;
7491 regs[i].wasconst=0;
7492 delayslot_alloc(&current,i+1);
7493 current.isconst=0;
7494 alloc_reg(&current,i,RTEMP);
7495 }
7496 //current.isconst=0; // DEBUG
cf95b4f0 7497 dops[i].ooo=1;
57871462 7498 ds=1;
7499 break;
7500 case CJUMP:
7501 //current.isconst=0;
7502 //current.wasconst=0;
7503 //regs[i].wasconst=0;
cf95b4f0 7504 clear_const(&current,dops[i].rs1);
7505 clear_const(&current,dops[i].rs2);
7506 if((dops[i].opcode&0x3E)==4) // BEQ/BNE
57871462 7507 {
7508 alloc_cc(&current,i);
7509 dirty_reg(&current,CCREG);
cf95b4f0 7510 if(dops[i].rs1) alloc_reg(&current,i,dops[i].rs1);
7511 if(dops[i].rs2) alloc_reg(&current,i,dops[i].rs2);
7512 if((dops[i].rs1&&(dops[i].rs1==dops[i+1].rt1||dops[i].rs1==dops[i+1].rt2))||
7513 (dops[i].rs2&&(dops[i].rs2==dops[i+1].rt1||dops[i].rs2==dops[i+1].rt2))) {
57871462 7514 // The delay slot overwrites one of our conditions.
7515 // Allocate the branch condition registers instead.
57871462 7516 current.isconst=0;
7517 current.wasconst=0;
7518 regs[i].wasconst=0;
cf95b4f0 7519 if(dops[i].rs1) alloc_reg(&current,i,dops[i].rs1);
7520 if(dops[i].rs2) alloc_reg(&current,i,dops[i].rs2);
57871462 7521 }
e1190b87 7522 else
7523 {
cf95b4f0 7524 dops[i].ooo=1;
e1190b87 7525 delayslot_alloc(&current,i+1);
7526 }
57871462 7527 }
7528 else
cf95b4f0 7529 if((dops[i].opcode&0x3E)==6) // BLEZ/BGTZ
57871462 7530 {
7531 alloc_cc(&current,i);
7532 dirty_reg(&current,CCREG);
cf95b4f0 7533 alloc_reg(&current,i,dops[i].rs1);
7534 if(dops[i].rs1&&(dops[i].rs1==dops[i+1].rt1||dops[i].rs1==dops[i+1].rt2)) {
57871462 7535 // The delay slot overwrites one of our conditions.
7536 // Allocate the branch condition registers instead.
57871462 7537 current.isconst=0;
7538 current.wasconst=0;
7539 regs[i].wasconst=0;
cf95b4f0 7540 if(dops[i].rs1) alloc_reg(&current,i,dops[i].rs1);
57871462 7541 }
e1190b87 7542 else
7543 {
cf95b4f0 7544 dops[i].ooo=1;
e1190b87 7545 delayslot_alloc(&current,i+1);
7546 }
57871462 7547 }
7548 else
7549 // Don't alloc the delay slot yet because we might not execute it
cf95b4f0 7550 if((dops[i].opcode&0x3E)==0x14) // BEQL/BNEL
57871462 7551 {
7552 current.isconst=0;
7553 current.wasconst=0;
7554 regs[i].wasconst=0;
7555 alloc_cc(&current,i);
7556 dirty_reg(&current,CCREG);
cf95b4f0 7557 alloc_reg(&current,i,dops[i].rs1);
7558 alloc_reg(&current,i,dops[i].rs2);
57871462 7559 }
7560 else
cf95b4f0 7561 if((dops[i].opcode&0x3E)==0x16) // BLEZL/BGTZL
57871462 7562 {
7563 current.isconst=0;
7564 current.wasconst=0;
7565 regs[i].wasconst=0;
7566 alloc_cc(&current,i);
7567 dirty_reg(&current,CCREG);
cf95b4f0 7568 alloc_reg(&current,i,dops[i].rs1);
57871462 7569 }
7570 ds=1;
7571 //current.isconst=0;
7572 break;
7573 case SJUMP:
7574 //current.isconst=0;
7575 //current.wasconst=0;
7576 //regs[i].wasconst=0;
cf95b4f0 7577 clear_const(&current,dops[i].rs1);
7578 clear_const(&current,dops[i].rt1);
7579 //if((dops[i].opcode2&0x1E)==0x0) // BLTZ/BGEZ
7580 if((dops[i].opcode2&0x0E)==0x0) // BLTZ/BGEZ
57871462 7581 {
7582 alloc_cc(&current,i);
7583 dirty_reg(&current,CCREG);
cf95b4f0 7584 alloc_reg(&current,i,dops[i].rs1);
7585 if (dops[i].rt1==31) { // BLTZAL/BGEZAL
57871462 7586 alloc_reg(&current,i,31);
7587 dirty_reg(&current,31);
57871462 7588 //#ifdef REG_PREFETCH
7589 //alloc_reg(&current,i,PTEMP);
7590 //#endif
57871462 7591 }
cf95b4f0 7592 if((dops[i].rs1&&(dops[i].rs1==dops[i+1].rt1||dops[i].rs1==dops[i+1].rt2)) // The delay slot overwrites the branch condition.
7593 ||(dops[i].rt1==31&&(dops[i+1].rs1==31||dops[i+1].rs2==31||dops[i+1].rt1==31||dops[i+1].rt2==31))) { // DS touches $ra
57871462 7594 // Allocate the branch condition registers instead.
57871462 7595 current.isconst=0;
7596 current.wasconst=0;
7597 regs[i].wasconst=0;
cf95b4f0 7598 if(dops[i].rs1) alloc_reg(&current,i,dops[i].rs1);
57871462 7599 }
e1190b87 7600 else
7601 {
cf95b4f0 7602 dops[i].ooo=1;
e1190b87 7603 delayslot_alloc(&current,i+1);
7604 }
57871462 7605 }
7606 else
7607 // Don't alloc the delay slot yet because we might not execute it
cf95b4f0 7608 if((dops[i].opcode2&0x1E)==0x2) // BLTZL/BGEZL
57871462 7609 {
7610 current.isconst=0;
7611 current.wasconst=0;
7612 regs[i].wasconst=0;
7613 alloc_cc(&current,i);
7614 dirty_reg(&current,CCREG);
cf95b4f0 7615 alloc_reg(&current,i,dops[i].rs1);
57871462 7616 }
7617 ds=1;
7618 //current.isconst=0;
7619 break;
57871462 7620 case IMM16:
7621 imm16_alloc(&current,i);
7622 break;
7623 case LOAD:
7624 case LOADLR:
7625 load_alloc(&current,i);
7626 break;
7627 case STORE:
7628 case STORELR:
7629 store_alloc(&current,i);
7630 break;
7631 case ALU:
7632 alu_alloc(&current,i);
7633 break;
7634 case SHIFT:
7635 shift_alloc(&current,i);
7636 break;
7637 case MULTDIV:
7638 multdiv_alloc(&current,i);
7639 break;
7640 case SHIFTIMM:
7641 shiftimm_alloc(&current,i);
7642 break;
7643 case MOV:
7644 mov_alloc(&current,i);
7645 break;
7646 case COP0:
7647 cop0_alloc(&current,i);
7648 break;
7649 case COP1:
81dbbf4c 7650 break;
b9b61529 7651 case COP2:
81dbbf4c 7652 cop2_alloc(&current,i);
57871462 7653 break;
7654 case C1LS:
7655 c1ls_alloc(&current,i);
7656 break;
b9b61529 7657 case C2LS:
7658 c2ls_alloc(&current,i);
7659 break;
7660 case C2OP:
7661 c2op_alloc(&current,i);
7662 break;
57871462 7663 case SYSCALL:
7139f3c8 7664 case HLECALL:
1e973cb0 7665 case INTCALL:
57871462 7666 syscall_alloc(&current,i);
7667 break;
7668 case SPAN:
7669 pagespan_alloc(&current,i);
7670 break;
7671 }
9f51b4b9 7672
57871462 7673 // Create entry (branch target) regmap
7674 for(hr=0;hr<HOST_REGS;hr++)
7675 {
581335b0 7676 int r,or;
57871462 7677 r=current.regmap[hr];
7678 if(r>=0) {
7679 if(r!=regmap_pre[i][hr]) {
7680 // TODO: delay slot (?)
7681 or=get_reg(regmap_pre[i],r); // Get old mapping for this register
9de8a0c3 7682 if(or<0||r>=TEMPREG){
57871462 7683 regs[i].regmap_entry[hr]=-1;
7684 }
7685 else
7686 {
7687 // Just move it to a different register
7688 regs[i].regmap_entry[hr]=r;
7689 // If it was dirty before, it's still dirty
9de8a0c3 7690 if((regs[i].wasdirty>>or)&1) dirty_reg(&current,r);
57871462 7691 }
7692 }
7693 else
7694 {
7695 // Unneeded
7696 if(r==0){
7697 regs[i].regmap_entry[hr]=0;
7698 }
7699 else
7c3a5182 7700 {
7701 assert(r<64);
57871462 7702 if((current.u>>r)&1) {
7703 regs[i].regmap_entry[hr]=-1;
7704 //regs[i].regmap[hr]=-1;
7705 current.regmap[hr]=-1;
7706 }else
7707 regs[i].regmap_entry[hr]=r;
7708 }
57871462 7709 }
7710 } else {
7711 // Branches expect CCREG to be allocated at the target
9f51b4b9 7712 if(regmap_pre[i][hr]==CCREG)
57871462 7713 regs[i].regmap_entry[hr]=CCREG;
7714 else
7715 regs[i].regmap_entry[hr]=-1;
7716 }
7717 }
7718 memcpy(regs[i].regmap,current.regmap,sizeof(current.regmap));
7719 }
27727b63 7720
cf95b4f0 7721 if(i>0&&(dops[i-1].itype==STORE||dops[i-1].itype==STORELR||(dops[i-1].itype==C2LS&&dops[i-1].opcode==0x3a))&&(u_int)imm[i-1]<0x800)
7722 current.waswritten|=1<<dops[i-1].rs1;
7723 current.waswritten&=~(1<<dops[i].rt1);
7724 current.waswritten&=~(1<<dops[i].rt2);
7725 if((dops[i].itype==STORE||dops[i].itype==STORELR||(dops[i].itype==C2LS&&dops[i].opcode==0x3a))&&(u_int)imm[i]>=0x800)
7726 current.waswritten&=~(1<<dops[i].rs1);
27727b63 7727
57871462 7728 /* Branch post-alloc */
7729 if(i>0)
7730 {
57871462 7731 current.wasdirty=current.dirty;
cf95b4f0 7732 switch(dops[i-1].itype) {
57871462 7733 case UJUMP:
7734 memcpy(&branch_regs[i-1],&current,sizeof(current));
7735 branch_regs[i-1].isconst=0;
7736 branch_regs[i-1].wasconst=0;
cf95b4f0 7737 branch_regs[i-1].u=branch_unneeded_reg[i-1]&~((1LL<<dops[i-1].rs1)|(1LL<<dops[i-1].rs2));
57871462 7738 alloc_cc(&branch_regs[i-1],i-1);
7739 dirty_reg(&branch_regs[i-1],CCREG);
cf95b4f0 7740 if(dops[i-1].rt1==31) { // JAL
57871462 7741 alloc_reg(&branch_regs[i-1],i-1,31);
7742 dirty_reg(&branch_regs[i-1],31);
57871462 7743 }
7744 memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
40fca85b 7745 memcpy(constmap[i],constmap[i-1],sizeof(constmap[i]));
57871462 7746 break;
7747 case RJUMP:
7748 memcpy(&branch_regs[i-1],&current,sizeof(current));
7749 branch_regs[i-1].isconst=0;
7750 branch_regs[i-1].wasconst=0;
cf95b4f0 7751 branch_regs[i-1].u=branch_unneeded_reg[i-1]&~((1LL<<dops[i-1].rs1)|(1LL<<dops[i-1].rs2));
57871462 7752 alloc_cc(&branch_regs[i-1],i-1);
7753 dirty_reg(&branch_regs[i-1],CCREG);
cf95b4f0 7754 alloc_reg(&branch_regs[i-1],i-1,dops[i-1].rs1);
7755 if(dops[i-1].rt1!=0) { // JALR
7756 alloc_reg(&branch_regs[i-1],i-1,dops[i-1].rt1);
7757 dirty_reg(&branch_regs[i-1],dops[i-1].rt1);
57871462 7758 }
7759 #ifdef USE_MINI_HT
cf95b4f0 7760 if(dops[i-1].rs1==31) { // JALR
57871462 7761 alloc_reg(&branch_regs[i-1],i-1,RHASH);
57871462 7762 alloc_reg(&branch_regs[i-1],i-1,RHTBL);
57871462 7763 }
7764 #endif
7765 memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
40fca85b 7766 memcpy(constmap[i],constmap[i-1],sizeof(constmap[i]));
57871462 7767 break;
7768 case CJUMP:
cf95b4f0 7769 if((dops[i-1].opcode&0x3E)==4) // BEQ/BNE
57871462 7770 {
7771 alloc_cc(&current,i-1);
7772 dirty_reg(&current,CCREG);
cf95b4f0 7773 if((dops[i-1].rs1&&(dops[i-1].rs1==dops[i].rt1||dops[i-1].rs1==dops[i].rt2))||
7774 (dops[i-1].rs2&&(dops[i-1].rs2==dops[i].rt1||dops[i-1].rs2==dops[i].rt2))) {
57871462 7775 // The delay slot overwrote one of our conditions
7776 // Delay slot goes after the test (in order)
cf95b4f0 7777 current.u=branch_unneeded_reg[i-1]&~((1LL<<dops[i].rs1)|(1LL<<dops[i].rs2));
57871462 7778 current.u|=1;
57871462 7779 delayslot_alloc(&current,i);
7780 current.isconst=0;
7781 }
7782 else
7783 {
cf95b4f0 7784 current.u=branch_unneeded_reg[i-1]&~((1LL<<dops[i-1].rs1)|(1LL<<dops[i-1].rs2));
57871462 7785 // Alloc the branch condition registers
cf95b4f0 7786 if(dops[i-1].rs1) alloc_reg(&current,i-1,dops[i-1].rs1);
7787 if(dops[i-1].rs2) alloc_reg(&current,i-1,dops[i-1].rs2);
57871462 7788 }
7789 memcpy(&branch_regs[i-1],&current,sizeof(current));
7790 branch_regs[i-1].isconst=0;
7791 branch_regs[i-1].wasconst=0;
7792 memcpy(&branch_regs[i-1].regmap_entry,&current.regmap,sizeof(current.regmap));
40fca85b 7793 memcpy(constmap[i],constmap[i-1],sizeof(constmap[i]));
57871462 7794 }
7795 else
cf95b4f0 7796 if((dops[i-1].opcode&0x3E)==6) // BLEZ/BGTZ
57871462 7797 {
7798 alloc_cc(&current,i-1);
7799 dirty_reg(&current,CCREG);
cf95b4f0 7800 if(dops[i-1].rs1==dops[i].rt1||dops[i-1].rs1==dops[i].rt2) {
57871462 7801 // The delay slot overwrote the branch condition
7802 // Delay slot goes after the test (in order)
cf95b4f0 7803 current.u=branch_unneeded_reg[i-1]&~((1LL<<dops[i].rs1)|(1LL<<dops[i].rs2));
57871462 7804 current.u|=1;
57871462 7805 delayslot_alloc(&current,i);
7806 current.isconst=0;
7807 }
7808 else
7809 {
cf95b4f0 7810 current.u=branch_unneeded_reg[i-1]&~(1LL<<dops[i-1].rs1);
57871462 7811 // Alloc the branch condition register
cf95b4f0 7812 alloc_reg(&current,i-1,dops[i-1].rs1);
57871462 7813 }
7814 memcpy(&branch_regs[i-1],&current,sizeof(current));
7815 branch_regs[i-1].isconst=0;
7816 branch_regs[i-1].wasconst=0;
7817 memcpy(&branch_regs[i-1].regmap_entry,&current.regmap,sizeof(current.regmap));
40fca85b 7818 memcpy(constmap[i],constmap[i-1],sizeof(constmap[i]));
57871462 7819 }
7820 else
7821 // Alloc the delay slot in case the branch is taken
cf95b4f0 7822 if((dops[i-1].opcode&0x3E)==0x14) // BEQL/BNEL
57871462 7823 {
7824 memcpy(&branch_regs[i-1],&current,sizeof(current));
cf95b4f0 7825 branch_regs[i-1].u=(branch_unneeded_reg[i-1]&~((1LL<<dops[i].rs1)|(1LL<<dops[i].rs2)|(1LL<<dops[i].rt1)|(1LL<<dops[i].rt2)))|1;
57871462 7826 alloc_cc(&branch_regs[i-1],i);
7827 dirty_reg(&branch_regs[i-1],CCREG);
7828 delayslot_alloc(&branch_regs[i-1],i);
7829 branch_regs[i-1].isconst=0;
7830 alloc_reg(&current,i,CCREG); // Not taken path
7831 dirty_reg(&current,CCREG);
7832 memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
7833 }
7834 else
cf95b4f0 7835 if((dops[i-1].opcode&0x3E)==0x16) // BLEZL/BGTZL
57871462 7836 {
7837 memcpy(&branch_regs[i-1],&current,sizeof(current));
cf95b4f0 7838 branch_regs[i-1].u=(branch_unneeded_reg[i-1]&~((1LL<<dops[i].rs1)|(1LL<<dops[i].rs2)|(1LL<<dops[i].rt1)|(1LL<<dops[i].rt2)))|1;
57871462 7839 alloc_cc(&branch_regs[i-1],i);
7840 dirty_reg(&branch_regs[i-1],CCREG);
7841 delayslot_alloc(&branch_regs[i-1],i);
7842 branch_regs[i-1].isconst=0;
7843 alloc_reg(&current,i,CCREG); // Not taken path
7844 dirty_reg(&current,CCREG);
7845 memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
7846 }
7847 break;
7848 case SJUMP:
cf95b4f0 7849 //if((dops[i-1].opcode2&0x1E)==0) // BLTZ/BGEZ
7850 if((dops[i-1].opcode2&0x0E)==0) // BLTZ/BGEZ
57871462 7851 {
7852 alloc_cc(&current,i-1);
7853 dirty_reg(&current,CCREG);
cf95b4f0 7854 if(dops[i-1].rs1==dops[i].rt1||dops[i-1].rs1==dops[i].rt2) {
57871462 7855 // The delay slot overwrote the branch condition
7856 // Delay slot goes after the test (in order)
cf95b4f0 7857 current.u=branch_unneeded_reg[i-1]&~((1LL<<dops[i].rs1)|(1LL<<dops[i].rs2));
57871462 7858 current.u|=1;
57871462 7859 delayslot_alloc(&current,i);
7860 current.isconst=0;
7861 }
7862 else
7863 {
cf95b4f0 7864 current.u=branch_unneeded_reg[i-1]&~(1LL<<dops[i-1].rs1);
57871462 7865 // Alloc the branch condition register
cf95b4f0 7866 alloc_reg(&current,i-1,dops[i-1].rs1);
57871462 7867 }
7868 memcpy(&branch_regs[i-1],&current,sizeof(current));
7869 branch_regs[i-1].isconst=0;
7870 branch_regs[i-1].wasconst=0;
7871 memcpy(&branch_regs[i-1].regmap_entry,&current.regmap,sizeof(current.regmap));
40fca85b 7872 memcpy(constmap[i],constmap[i-1],sizeof(constmap[i]));
57871462 7873 }
7874 else
7875 // Alloc the delay slot in case the branch is taken
cf95b4f0 7876 if((dops[i-1].opcode2&0x1E)==2) // BLTZL/BGEZL
57871462 7877 {
7878 memcpy(&branch_regs[i-1],&current,sizeof(current));
cf95b4f0 7879 branch_regs[i-1].u=(branch_unneeded_reg[i-1]&~((1LL<<dops[i].rs1)|(1LL<<dops[i].rs2)|(1LL<<dops[i].rt1)|(1LL<<dops[i].rt2)))|1;
57871462 7880 alloc_cc(&branch_regs[i-1],i);
7881 dirty_reg(&branch_regs[i-1],CCREG);
7882 delayslot_alloc(&branch_regs[i-1],i);
7883 branch_regs[i-1].isconst=0;
7884 alloc_reg(&current,i,CCREG); // Not taken path
7885 dirty_reg(&current,CCREG);
7886 memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
7887 }
7888 // FIXME: BLTZAL/BGEZAL
cf95b4f0 7889 if(dops[i-1].opcode2&0x10) { // BxxZAL
57871462 7890 alloc_reg(&branch_regs[i-1],i-1,31);
7891 dirty_reg(&branch_regs[i-1],31);
57871462 7892 }
7893 break;
57871462 7894 }
7895
fe807a8a 7896 if (dops[i-1].is_ujump)
57871462 7897 {
cf95b4f0 7898 if(dops[i-1].rt1==31) // JAL/JALR
57871462 7899 {
7900 // Subroutine call will return here, don't alloc any registers
57871462 7901 current.dirty=0;
7902 clear_all_regs(current.regmap);
7903 alloc_reg(&current,i,CCREG);
7904 dirty_reg(&current,CCREG);
7905 }
7906 else if(i+1<slen)
7907 {
7908 // Internal branch will jump here, match registers to caller
57871462 7909 current.dirty=0;
7910 clear_all_regs(current.regmap);
7911 alloc_reg(&current,i,CCREG);
7912 dirty_reg(&current,CCREG);
7913 for(j=i-1;j>=0;j--)
7914 {
7915 if(ba[j]==start+i*4+4) {
7916 memcpy(current.regmap,branch_regs[j].regmap,sizeof(current.regmap));
57871462 7917 current.dirty=branch_regs[j].dirty;
7918 break;
7919 }
7920 }
7921 while(j>=0) {
7922 if(ba[j]==start+i*4+4) {
7923 for(hr=0;hr<HOST_REGS;hr++) {
7924 if(current.regmap[hr]!=branch_regs[j].regmap[hr]) {
7925 current.regmap[hr]=-1;
7926 }
57871462 7927 current.dirty&=branch_regs[j].dirty;
7928 }
7929 }
7930 j--;
7931 }
7932 }
7933 }
7934 }
7935
7936 // Count cycles in between branches
2330734f 7937 ccadj[i] = CLOCK_ADJUST(cc);
fe807a8a 7938 if (i > 0 && (dops[i-1].is_jump || dops[i].itype == SYSCALL || dops[i].itype == HLECALL))
57871462 7939 {
7940 cc=0;
7941 }
71e490c5 7942#if !defined(DRC_DBG)
cf95b4f0 7943 else if(dops[i].itype==C2OP&&gte_cycletab[source[i]&0x3f]>2)
054175e9 7944 {
81dbbf4c 7945 // this should really be removed since the real stalls have been implemented,
7946 // but doing so causes sizeable perf regression against the older version
7947 u_int gtec = gte_cycletab[source[i] & 0x3f];
32631e6a 7948 cc += HACK_ENABLED(NDHACK_NO_STALLS) ? gtec/2 : 2;
fb407447 7949 }
cf95b4f0 7950 else if(i>1&&dops[i].itype==STORE&&dops[i-1].itype==STORE&&dops[i-2].itype==STORE&&!dops[i].bt)
5fdcbb5a 7951 {
7952 cc+=4;
7953 }
cf95b4f0 7954 else if(dops[i].itype==C2LS)
fb407447 7955 {
81dbbf4c 7956 // same as with C2OP
32631e6a 7957 cc += HACK_ENABLED(NDHACK_NO_STALLS) ? 4 : 2;
fb407447 7958 }
7959#endif
57871462 7960 else
7961 {
7962 cc++;
7963 }
7964
cf95b4f0 7965 if(!dops[i].is_ds) {
57871462 7966 regs[i].dirty=current.dirty;
7967 regs[i].isconst=current.isconst;
40fca85b 7968 memcpy(constmap[i],current_constmap,sizeof(constmap[i]));
57871462 7969 }
7970 for(hr=0;hr<HOST_REGS;hr++) {
7971 if(hr!=EXCLUDE_REG&&regs[i].regmap[hr]>=0) {
7972 if(regmap_pre[i][hr]!=regs[i].regmap[hr]) {
7973 regs[i].wasconst&=~(1<<hr);
7974 }
7975 }
7976 }
7977 if(current.regmap[HOST_BTREG]==BTREG) current.regmap[HOST_BTREG]=-1;
27727b63 7978 regs[i].waswritten=current.waswritten;
57871462 7979 }
4149788d 7980}
9f51b4b9 7981
4149788d 7982static noinline void pass4_cull_unused_regs(void)
7983{
53358c1d 7984 u_int last_needed_regs[4] = {0,0,0,0};
4149788d 7985 u_int nr=0;
7986 int i;
9f51b4b9 7987
57871462 7988 for (i=slen-1;i>=0;i--)
7989 {
7990 int hr;
53358c1d 7991 __builtin_prefetch(regs[i-2].regmap);
fe807a8a 7992 if(dops[i].is_jump)
57871462 7993 {
7994 if(ba[i]<start || ba[i]>=(start+slen*4))
7995 {
7996 // Branch out of this block, don't need anything
7997 nr=0;
7998 }
7999 else
8000 {
8001 // Internal branch
8002 // Need whatever matches the target
8003 nr=0;
8004 int t=(ba[i]-start)>>2;
8005 for(hr=0;hr<HOST_REGS;hr++)
8006 {
8007 if(regs[i].regmap_entry[hr]>=0) {
8008 if(regs[i].regmap_entry[hr]==regs[t].regmap_entry[hr]) nr|=1<<hr;
8009 }
8010 }
8011 }
8012 // Conditional branch may need registers for following instructions
fe807a8a 8013 if (!dops[i].is_ujump)
57871462 8014 {
8015 if(i<slen-2) {
53358c1d 8016 nr |= last_needed_regs[(i+2) & 3];
57871462 8017 for(hr=0;hr<HOST_REGS;hr++)
8018 {
8019 if(regmap_pre[i+2][hr]>=0&&get_reg(regs[i+2].regmap_entry,regmap_pre[i+2][hr])<0) nr&=~(1<<hr);
8020 //if((regmap_entry[i+2][hr])>=0) if(!((nr>>hr)&1)) printf("%x-bogus(%d=%d)\n",start+i*4,hr,regmap_entry[i+2][hr]);
8021 }
8022 }
8023 }
8024 // Don't need stuff which is overwritten
f5955059 8025 //if(regs[i].regmap[hr]!=regmap_pre[i][hr]) nr&=~(1<<hr);
8026 //if(regs[i].regmap[hr]<0) nr&=~(1<<hr);
57871462 8027 // Merge in delay slot
53358c1d 8028 if (dops[i+1].rt1) nr &= ~get_regm(regs[i].regmap, dops[i+1].rt1);
8029 if (dops[i+1].rt2) nr &= ~get_regm(regs[i].regmap, dops[i+1].rt2);
8030 nr |= get_regm(regmap_pre[i], dops[i+1].rs1);
8031 nr |= get_regm(regmap_pre[i], dops[i+1].rs2);
8032 nr |= get_regm(regs[i].regmap_entry, dops[i+1].rs1);
8033 nr |= get_regm(regs[i].regmap_entry, dops[i+1].rs2);
8034 if (ram_offset && (dops[i+1].is_load || dops[i+1].is_store)) {
8035 nr |= get_regm(regmap_pre[i], ROREG);
8036 nr |= get_regm(regs[i].regmap_entry, ROREG);
8037 }
8038 if (dops[i+1].is_store) {
8039 nr |= get_regm(regmap_pre[i], INVCP);
8040 nr |= get_regm(regs[i].regmap_entry, INVCP);
57871462 8041 }
8042 }
cf95b4f0 8043 else if(dops[i].itype==SYSCALL||dops[i].itype==HLECALL||dops[i].itype==INTCALL)
57871462 8044 {
8045 // SYSCALL instruction (software interrupt)
8046 nr=0;
8047 }
cf95b4f0 8048 else if(dops[i].itype==COP0 && (source[i]&0x3f)==0x18)
57871462 8049 {
8050 // ERET instruction (return from interrupt)
8051 nr=0;
8052 }
8053 else // Non-branch
8054 {
8055 if(i<slen-1) {
8056 for(hr=0;hr<HOST_REGS;hr++) {
8057 if(regmap_pre[i+1][hr]>=0&&get_reg(regs[i+1].regmap_entry,regmap_pre[i+1][hr])<0) nr&=~(1<<hr);
8058 if(regs[i].regmap[hr]!=regmap_pre[i+1][hr]) nr&=~(1<<hr);
8059 if(regs[i].regmap[hr]!=regmap_pre[i][hr]) nr&=~(1<<hr);
8060 if(regs[i].regmap[hr]<0) nr&=~(1<<hr);
8061 }
8062 }
8063 }
53358c1d 8064 // Overwritten registers are not needed
8065 if (dops[i].rt1) nr &= ~get_regm(regs[i].regmap, dops[i].rt1);
8066 if (dops[i].rt2) nr &= ~get_regm(regs[i].regmap, dops[i].rt2);
8067 nr &= ~get_regm(regs[i].regmap, FTEMP);
8068 // Source registers are needed
8069 nr |= get_regm(regmap_pre[i], dops[i].rs1);
8070 nr |= get_regm(regmap_pre[i], dops[i].rs2);
8071 nr |= get_regm(regs[i].regmap_entry, dops[i].rs1);
8072 nr |= get_regm(regs[i].regmap_entry, dops[i].rs2);
8073 if (ram_offset && (dops[i].is_load || dops[i].is_store)) {
8074 nr |= get_regm(regmap_pre[i], ROREG);
8075 nr |= get_regm(regs[i].regmap_entry, ROREG);
8076 }
8077 if (dops[i].is_store) {
8078 nr |= get_regm(regmap_pre[i], INVCP);
8079 nr |= get_regm(regs[i].regmap_entry, INVCP);
8080 }
8081
8082 if (i > 0 && !dops[i].bt && regs[i].wasdirty)
57871462 8083 for(hr=0;hr<HOST_REGS;hr++)
8084 {
57871462 8085 // Don't store a register immediately after writing it,
8086 // may prevent dual-issue.
8087 // But do so if this is a branch target, otherwise we
8088 // might have to load the register before the branch.
53358c1d 8089 if((regs[i].wasdirty>>hr)&1) {
7c3a5182 8090 if((regmap_pre[i][hr]>0&&!((unneeded_reg[i]>>regmap_pre[i][hr])&1))) {
9de8a0c3 8091 if(dops[i-1].rt1==regmap_pre[i][hr]) nr|=1<<hr;
8092 if(dops[i-1].rt2==regmap_pre[i][hr]) nr|=1<<hr;
57871462 8093 }
7c3a5182 8094 if((regs[i].regmap_entry[hr]>0&&!((unneeded_reg[i]>>regs[i].regmap_entry[hr])&1))) {
9de8a0c3 8095 if(dops[i-1].rt1==regs[i].regmap_entry[hr]) nr|=1<<hr;
8096 if(dops[i-1].rt2==regs[i].regmap_entry[hr]) nr|=1<<hr;
57871462 8097 }
8098 }
8099 }
8100 // Cycle count is needed at branches. Assume it is needed at the target too.
cf95b4f0 8101 if(i==0||dops[i].bt||dops[i].itype==CJUMP||dops[i].itype==SPAN) {
57871462 8102 if(regmap_pre[i][HOST_CCREG]==CCREG) nr|=1<<HOST_CCREG;
8103 if(regs[i].regmap_entry[HOST_CCREG]==CCREG) nr|=1<<HOST_CCREG;
8104 }
8105 // Save it
53358c1d 8106 last_needed_regs[i & 3] = nr;
9f51b4b9 8107
57871462 8108 // Deallocate unneeded registers
8109 for(hr=0;hr<HOST_REGS;hr++)
8110 {
8111 if(!((nr>>hr)&1)) {
8112 if(regs[i].regmap_entry[hr]!=CCREG) regs[i].regmap_entry[hr]=-1;
fe807a8a 8113 if(dops[i].is_jump)
57871462 8114 {
37387d8b 8115 int map1 = 0, map2 = 0, temp = 0; // or -1 ??
8116 if (dops[i+1].is_load || dops[i+1].is_store)
8117 map1 = ROREG;
8118 if (dops[i+1].is_store)
8119 map2 = INVCP;
8120 if(dops[i+1].itype==LOADLR || dops[i+1].itype==STORELR || dops[i+1].itype==C2LS)
8121 temp = FTEMP;
9de8a0c3 8122 if(regs[i].regmap[hr]!=dops[i].rs1 && regs[i].regmap[hr]!=dops[i].rs2 &&
8123 regs[i].regmap[hr]!=dops[i].rt1 && regs[i].regmap[hr]!=dops[i].rt2 &&
8124 regs[i].regmap[hr]!=dops[i+1].rt1 && regs[i].regmap[hr]!=dops[i+1].rt2 &&
cf95b4f0 8125 regs[i].regmap[hr]!=dops[i+1].rs1 && regs[i].regmap[hr]!=dops[i+1].rs2 &&
9de8a0c3 8126 regs[i].regmap[hr]!=temp && regs[i].regmap[hr]!=PTEMP &&
57871462 8127 regs[i].regmap[hr]!=RHASH && regs[i].regmap[hr]!=RHTBL &&
8128 regs[i].regmap[hr]!=RTEMP && regs[i].regmap[hr]!=CCREG &&
37387d8b 8129 regs[i].regmap[hr]!=map1 && regs[i].regmap[hr]!=map2)
57871462 8130 {
8131 regs[i].regmap[hr]=-1;
8132 regs[i].isconst&=~(1<<hr);
a550c61c 8133 regs[i].dirty&=~(1<<hr);
8134 regs[i+1].wasdirty&=~(1<<hr);
9de8a0c3 8135 if(branch_regs[i].regmap[hr]!=dops[i].rs1 && branch_regs[i].regmap[hr]!=dops[i].rs2 &&
8136 branch_regs[i].regmap[hr]!=dops[i].rt1 && branch_regs[i].regmap[hr]!=dops[i].rt2 &&
8137 branch_regs[i].regmap[hr]!=dops[i+1].rt1 && branch_regs[i].regmap[hr]!=dops[i+1].rt2 &&
cf95b4f0 8138 branch_regs[i].regmap[hr]!=dops[i+1].rs1 && branch_regs[i].regmap[hr]!=dops[i+1].rs2 &&
9de8a0c3 8139 branch_regs[i].regmap[hr]!=temp && branch_regs[i].regmap[hr]!=PTEMP &&
57871462 8140 branch_regs[i].regmap[hr]!=RHASH && branch_regs[i].regmap[hr]!=RHTBL &&
8141 branch_regs[i].regmap[hr]!=RTEMP && branch_regs[i].regmap[hr]!=CCREG &&
37387d8b 8142 branch_regs[i].regmap[hr]!=map1 && branch_regs[i].regmap[hr]!=map2)
57871462 8143 {
8144 branch_regs[i].regmap[hr]=-1;
8145 branch_regs[i].regmap_entry[hr]=-1;
fe807a8a 8146 if (!dops[i].is_ujump)
57871462 8147 {
fe807a8a 8148 if (i < slen-2) {
57871462 8149 regmap_pre[i+2][hr]=-1;
79c75f1b 8150 regs[i+2].wasconst&=~(1<<hr);
57871462 8151 }
8152 }
8153 }
8154 }
8155 }
8156 else
8157 {
8158 // Non-branch
8159 if(i>0)
8160 {
37387d8b 8161 int map1 = -1, map2 = -1, temp=-1;
8162 if (dops[i].is_load || dops[i].is_store)
8163 map1 = ROREG;
8164 if (dops[i].is_store)
8165 map2 = INVCP;
8166 if (dops[i].itype==LOADLR || dops[i].itype==STORELR || dops[i].itype==C2LS)
8167 temp = FTEMP;
9de8a0c3 8168 if(regs[i].regmap[hr]!=dops[i].rt1 && regs[i].regmap[hr]!=dops[i].rt2 &&
cf95b4f0 8169 regs[i].regmap[hr]!=dops[i].rs1 && regs[i].regmap[hr]!=dops[i].rs2 &&
9de8a0c3 8170 regs[i].regmap[hr]!=temp && regs[i].regmap[hr]!=map1 && regs[i].regmap[hr]!=map2 &&
4b1c7cd1 8171 //(dops[i].itype!=SPAN||regs[i].regmap[hr]!=CCREG)
8172 regs[i].regmap[hr] != CCREG)
57871462 8173 {
cf95b4f0 8174 if(i<slen-1&&!dops[i].is_ds) {
ad49de89 8175 assert(regs[i].regmap[hr]<64);
afec9d44 8176 if(regmap_pre[i+1][hr]!=-1 || regs[i].regmap[hr]>0)
57871462 8177 if(regmap_pre[i+1][hr]!=regs[i].regmap[hr])
57871462 8178 {
c43b5311 8179 SysPrintf("fail: %x (%d %d!=%d)\n",start+i*4,hr,regmap_pre[i+1][hr],regs[i].regmap[hr]);
57871462 8180 assert(regmap_pre[i+1][hr]==regs[i].regmap[hr]);
8181 }
8182 regmap_pre[i+1][hr]=-1;
8183 if(regs[i+1].regmap_entry[hr]==CCREG) regs[i+1].regmap_entry[hr]=-1;
79c75f1b 8184 regs[i+1].wasconst&=~(1<<hr);
57871462 8185 }
8186 regs[i].regmap[hr]=-1;
8187 regs[i].isconst&=~(1<<hr);
a550c61c 8188 regs[i].dirty&=~(1<<hr);
8189 regs[i+1].wasdirty&=~(1<<hr);
57871462 8190 }
8191 }
8192 }
3968e69e 8193 } // if needed
8194 } // for hr
57871462 8195 }
4149788d 8196}
9f51b4b9 8197
4149788d 8198// If a register is allocated during a loop, try to allocate it for the
8199// entire loop, if possible. This avoids loading/storing registers
8200// inside of the loop.
8201static noinline void pass5a_preallocate1(void)
8202{
8203 int i, j, hr;
57871462 8204 signed char f_regmap[HOST_REGS];
8205 clear_all_regs(f_regmap);
8206 for(i=0;i<slen-1;i++)
8207 {
cf95b4f0 8208 if(dops[i].itype==UJUMP||dops[i].itype==CJUMP||dops[i].itype==SJUMP)
57871462 8209 {
9f51b4b9 8210 if(ba[i]>=start && ba[i]<(start+i*4))
cf95b4f0 8211 if(dops[i+1].itype==NOP||dops[i+1].itype==MOV||dops[i+1].itype==ALU
8212 ||dops[i+1].itype==SHIFTIMM||dops[i+1].itype==IMM16||dops[i+1].itype==LOAD
8213 ||dops[i+1].itype==STORE||dops[i+1].itype==STORELR||dops[i+1].itype==C1LS
8214 ||dops[i+1].itype==SHIFT||dops[i+1].itype==COP1
8215 ||dops[i+1].itype==COP2||dops[i+1].itype==C2LS||dops[i+1].itype==C2OP)
57871462 8216 {
8217 int t=(ba[i]-start)>>2;
fe807a8a 8218 if(t > 0 && !dops[t-1].is_jump) // loop_preload can't handle jumps into delay slots
cf95b4f0 8219 if(t<2||(dops[t-2].itype!=UJUMP&&dops[t-2].itype!=RJUMP)||dops[t-2].rt1!=31) // call/ret assumes no registers allocated
57871462 8220 for(hr=0;hr<HOST_REGS;hr++)
8221 {
7c3a5182 8222 if(regs[i].regmap[hr]>=0) {
b372a952 8223 if(f_regmap[hr]!=regs[i].regmap[hr]) {
8224 // dealloc old register
8225 int n;
8226 for(n=0;n<HOST_REGS;n++)
8227 {
8228 if(f_regmap[n]==regs[i].regmap[hr]) {f_regmap[n]=-1;}
8229 }
8230 // and alloc new one
8231 f_regmap[hr]=regs[i].regmap[hr];
8232 }
8233 }
7c3a5182 8234 if(branch_regs[i].regmap[hr]>=0) {
b372a952 8235 if(f_regmap[hr]!=branch_regs[i].regmap[hr]) {
8236 // dealloc old register
8237 int n;
8238 for(n=0;n<HOST_REGS;n++)
8239 {
8240 if(f_regmap[n]==branch_regs[i].regmap[hr]) {f_regmap[n]=-1;}
8241 }
8242 // and alloc new one
8243 f_regmap[hr]=branch_regs[i].regmap[hr];
8244 }
8245 }
cf95b4f0 8246 if(dops[i].ooo) {
9f51b4b9 8247 if(count_free_regs(regs[i].regmap)<=minimum_free_regs[i+1])
e1190b87 8248 f_regmap[hr]=branch_regs[i].regmap[hr];
8249 }else{
9f51b4b9 8250 if(count_free_regs(branch_regs[i].regmap)<=minimum_free_regs[i+1])
57871462 8251 f_regmap[hr]=branch_regs[i].regmap[hr];
8252 }
8253 // Avoid dirty->clean transition
e1190b87 8254 #ifdef DESTRUCTIVE_WRITEBACK
57871462 8255 if(t>0) if(get_reg(regmap_pre[t],f_regmap[hr])>=0) if((regs[t].wasdirty>>get_reg(regmap_pre[t],f_regmap[hr]))&1) f_regmap[hr]=-1;
e1190b87 8256 #endif
8257 // This check is only strictly required in the DESTRUCTIVE_WRITEBACK
8258 // case above, however it's always a good idea. We can't hoist the
8259 // load if the register was already allocated, so there's no point
8260 // wasting time analyzing most of these cases. It only "succeeds"
8261 // when the mapping was different and the load can be replaced with
8262 // a mov, which is of negligible benefit. So such cases are
8263 // skipped below.
57871462 8264 if(f_regmap[hr]>0) {
198df76f 8265 if(regs[t].regmap[hr]==f_regmap[hr]||(regs[t].regmap_entry[hr]<0&&get_reg(regmap_pre[t],f_regmap[hr])<0)) {
57871462 8266 int r=f_regmap[hr];
8267 for(j=t;j<=i;j++)
8268 {
8269 //printf("Test %x -> %x, %x %d/%d\n",start+i*4,ba[i],start+j*4,hr,r);
8270 if(r<34&&((unneeded_reg[j]>>r)&1)) break;
00fa9369 8271 assert(r < 64);
9de8a0c3 8272 if(regs[j].regmap[hr]==f_regmap[hr]&&f_regmap[hr]<TEMPREG) {
57871462 8273 //printf("Hit %x -> %x, %x %d/%d\n",start+i*4,ba[i],start+j*4,hr,r);
8274 int k;
8275 if(regs[i].regmap[hr]==-1&&branch_regs[i].regmap[hr]==-1) {
670c0f22 8276 if(get_reg(regs[i].regmap,f_regmap[hr])>=0) break;
57871462 8277 if(get_reg(regs[i+2].regmap,f_regmap[hr])>=0) break;
57871462 8278 k=i;
8279 while(k>1&&regs[k-1].regmap[hr]==-1) {
e1190b87 8280 if(count_free_regs(regs[k-1].regmap)<=minimum_free_regs[k-1]) {
8281 //printf("no free regs for store %x\n",start+(k-1)*4);
8282 break;
57871462 8283 }
57871462 8284 if(get_reg(regs[k-1].regmap,f_regmap[hr])>=0) {
8285 //printf("no-match due to different register\n");
8286 break;
8287 }
fe807a8a 8288 if (dops[k-2].is_jump) {
57871462 8289 //printf("no-match due to branch\n");
8290 break;
8291 }
8292 // call/ret fast path assumes no registers allocated
cf95b4f0 8293 if(k>2&&(dops[k-3].itype==UJUMP||dops[k-3].itype==RJUMP)&&dops[k-3].rt1==31) {
57871462 8294 break;
8295 }
57871462 8296 k--;
8297 }
57871462 8298 if(regs[k-1].regmap[hr]==f_regmap[hr]&&regmap_pre[k][hr]==f_regmap[hr]) {
8299 //printf("Extend r%d, %x ->\n",hr,start+k*4);
8300 while(k<i) {
8301 regs[k].regmap_entry[hr]=f_regmap[hr];
8302 regs[k].regmap[hr]=f_regmap[hr];
8303 regmap_pre[k+1][hr]=f_regmap[hr];
8304 regs[k].wasdirty&=~(1<<hr);
8305 regs[k].dirty&=~(1<<hr);
8306 regs[k].wasdirty|=(1<<hr)&regs[k-1].dirty;
8307 regs[k].dirty|=(1<<hr)&regs[k].wasdirty;
8308 regs[k].wasconst&=~(1<<hr);
8309 regs[k].isconst&=~(1<<hr);
8310 k++;
8311 }
8312 }
8313 else {
8314 //printf("Fail Extend r%d, %x ->\n",hr,start+k*4);
8315 break;
8316 }
8317 assert(regs[i-1].regmap[hr]==f_regmap[hr]);
8318 if(regs[i-1].regmap[hr]==f_regmap[hr]&&regmap_pre[i][hr]==f_regmap[hr]) {
8319 //printf("OK fill %x (r%d)\n",start+i*4,hr);
8320 regs[i].regmap_entry[hr]=f_regmap[hr];
8321 regs[i].regmap[hr]=f_regmap[hr];
8322 regs[i].wasdirty&=~(1<<hr);
8323 regs[i].dirty&=~(1<<hr);
8324 regs[i].wasdirty|=(1<<hr)&regs[i-1].dirty;
8325 regs[i].dirty|=(1<<hr)&regs[i-1].dirty;
8326 regs[i].wasconst&=~(1<<hr);
8327 regs[i].isconst&=~(1<<hr);
8328 branch_regs[i].regmap_entry[hr]=f_regmap[hr];
8329 branch_regs[i].wasdirty&=~(1<<hr);
8330 branch_regs[i].wasdirty|=(1<<hr)&regs[i].dirty;
8331 branch_regs[i].regmap[hr]=f_regmap[hr];
8332 branch_regs[i].dirty&=~(1<<hr);
8333 branch_regs[i].dirty|=(1<<hr)&regs[i].dirty;
8334 branch_regs[i].wasconst&=~(1<<hr);
8335 branch_regs[i].isconst&=~(1<<hr);
fe807a8a 8336 if (!dops[i].is_ujump) {
57871462 8337 regmap_pre[i+2][hr]=f_regmap[hr];
8338 regs[i+2].wasdirty&=~(1<<hr);
8339 regs[i+2].wasdirty|=(1<<hr)&regs[i].dirty;
57871462 8340 }
8341 }
8342 }
8343 for(k=t;k<j;k++) {
e1190b87 8344 // Alloc register clean at beginning of loop,
8345 // but may dirty it in pass 6
57871462 8346 regs[k].regmap_entry[hr]=f_regmap[hr];
8347 regs[k].regmap[hr]=f_regmap[hr];
57871462 8348 regs[k].dirty&=~(1<<hr);
8349 regs[k].wasconst&=~(1<<hr);
8350 regs[k].isconst&=~(1<<hr);
fe807a8a 8351 if (dops[k].is_jump) {
e1190b87 8352 branch_regs[k].regmap_entry[hr]=f_regmap[hr];
8353 branch_regs[k].regmap[hr]=f_regmap[hr];
8354 branch_regs[k].dirty&=~(1<<hr);
8355 branch_regs[k].wasconst&=~(1<<hr);
8356 branch_regs[k].isconst&=~(1<<hr);
fe807a8a 8357 if (!dops[k].is_ujump) {
e1190b87 8358 regmap_pre[k+2][hr]=f_regmap[hr];
8359 regs[k+2].wasdirty&=~(1<<hr);
e1190b87 8360 }
8361 }
8362 else
8363 {
8364 regmap_pre[k+1][hr]=f_regmap[hr];
8365 regs[k+1].wasdirty&=~(1<<hr);
8366 }
57871462 8367 }
8368 if(regs[j].regmap[hr]==f_regmap[hr])
8369 regs[j].regmap_entry[hr]=f_regmap[hr];
8370 break;
8371 }
8372 if(j==i) break;
8373 if(regs[j].regmap[hr]>=0)
8374 break;
8375 if(get_reg(regs[j].regmap,f_regmap[hr])>=0) {
8376 //printf("no-match due to different register\n");
8377 break;
8378 }
fe807a8a 8379 if (dops[j].is_ujump)
e1190b87 8380 {
8381 // Stop on unconditional branch
8382 break;
8383 }
cf95b4f0 8384 if(dops[j].itype==CJUMP||dops[j].itype==SJUMP)
e1190b87 8385 {
cf95b4f0 8386 if(dops[j].ooo) {
9f51b4b9 8387 if(count_free_regs(regs[j].regmap)<=minimum_free_regs[j+1])
e1190b87 8388 break;
8389 }else{
9f51b4b9 8390 if(count_free_regs(branch_regs[j].regmap)<=minimum_free_regs[j+1])
e1190b87 8391 break;
8392 }
8393 if(get_reg(branch_regs[j].regmap,f_regmap[hr])>=0) {
8394 //printf("no-match due to different register (branch)\n");
57871462 8395 break;
8396 }
8397 }
e1190b87 8398 if(count_free_regs(regs[j].regmap)<=minimum_free_regs[j]) {
8399 //printf("No free regs for store %x\n",start+j*4);
8400 break;
8401 }
ad49de89 8402 assert(f_regmap[hr]<64);
57871462 8403 }
8404 }
8405 }
8406 }
8407 }
8408 }else{
198df76f 8409 // Non branch or undetermined branch target
57871462 8410 for(hr=0;hr<HOST_REGS;hr++)
8411 {
8412 if(hr!=EXCLUDE_REG) {
7c3a5182 8413 if(regs[i].regmap[hr]>=0) {
b372a952 8414 if(f_regmap[hr]!=regs[i].regmap[hr]) {
8415 // dealloc old register
8416 int n;
8417 for(n=0;n<HOST_REGS;n++)
8418 {
8419 if(f_regmap[n]==regs[i].regmap[hr]) {f_regmap[n]=-1;}
8420 }
4149788d 8421 // and alloc new one
8422 f_regmap[hr]=regs[i].regmap[hr];
8423 }
8424 }
8425 }
8426 }
8427 // Try to restore cycle count at branch targets
8428 if(dops[i].bt) {
8429 for(j=i;j<slen-1;j++) {
8430 if(regs[j].regmap[HOST_CCREG]!=-1) break;
8431 if(count_free_regs(regs[j].regmap)<=minimum_free_regs[j]) {
8432 //printf("no free regs for store %x\n",start+j*4);
8433 break;
8434 }
8435 }
8436 if(regs[j].regmap[HOST_CCREG]==CCREG) {
8437 int k=i;
8438 //printf("Extend CC, %x -> %x\n",start+k*4,start+j*4);
8439 while(k<j) {
8440 regs[k].regmap_entry[HOST_CCREG]=CCREG;
8441 regs[k].regmap[HOST_CCREG]=CCREG;
8442 regmap_pre[k+1][HOST_CCREG]=CCREG;
8443 regs[k+1].wasdirty|=1<<HOST_CCREG;
8444 regs[k].dirty|=1<<HOST_CCREG;
8445 regs[k].wasconst&=~(1<<HOST_CCREG);
8446 regs[k].isconst&=~(1<<HOST_CCREG);
8447 k++;
8448 }
8449 regs[j].regmap_entry[HOST_CCREG]=CCREG;
8450 }
8451 // Work backwards from the branch target
8452 if(j>i&&f_regmap[HOST_CCREG]==CCREG)
8453 {
8454 //printf("Extend backwards\n");
8455 int k;
8456 k=i;
8457 while(regs[k-1].regmap[HOST_CCREG]==-1) {
8458 if(count_free_regs(regs[k-1].regmap)<=minimum_free_regs[k-1]) {
8459 //printf("no free regs for store %x\n",start+(k-1)*4);
8460 break;
8461 }
8462 k--;
8463 }
8464 if(regs[k-1].regmap[HOST_CCREG]==CCREG) {
8465 //printf("Extend CC, %x ->\n",start+k*4);
8466 while(k<=i) {
8467 regs[k].regmap_entry[HOST_CCREG]=CCREG;
8468 regs[k].regmap[HOST_CCREG]=CCREG;
8469 regmap_pre[k+1][HOST_CCREG]=CCREG;
8470 regs[k+1].wasdirty|=1<<HOST_CCREG;
8471 regs[k].dirty|=1<<HOST_CCREG;
8472 regs[k].wasconst&=~(1<<HOST_CCREG);
8473 regs[k].isconst&=~(1<<HOST_CCREG);
8474 k++;
8475 }
8476 }
8477 else {
8478 //printf("Fail Extend CC, %x ->\n",start+k*4);
8479 }
8480 }
8481 }
8482 if(dops[i].itype!=STORE&&dops[i].itype!=STORELR&&dops[i].itype!=C1LS&&dops[i].itype!=SHIFT&&
8483 dops[i].itype!=NOP&&dops[i].itype!=MOV&&dops[i].itype!=ALU&&dops[i].itype!=SHIFTIMM&&
8484 dops[i].itype!=IMM16&&dops[i].itype!=LOAD&&dops[i].itype!=COP1)
8485 {
8486 memcpy(f_regmap,regs[i].regmap,sizeof(f_regmap));
8487 }
8488 }
8489 }
8490}
8491
8492// This allocates registers (if possible) one instruction prior
8493// to use, which can avoid a load-use penalty on certain CPUs.
8494static noinline void pass5b_preallocate2(void)
8495{
8496 int i, hr;
8497 for(i=0;i<slen-1;i++)
8498 {
8499 if (!i || !dops[i-1].is_jump)
8500 {
8501 if(!dops[i+1].bt)
8502 {
8503 if(dops[i].itype==ALU||dops[i].itype==MOV||dops[i].itype==LOAD||dops[i].itype==SHIFTIMM||dops[i].itype==IMM16
8504 ||((dops[i].itype==COP1||dops[i].itype==COP2)&&dops[i].opcode2<3))
8505 {
8506 if(dops[i+1].rs1) {
8507 if((hr=get_reg(regs[i+1].regmap,dops[i+1].rs1))>=0)
8508 {
8509 if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
8510 {
8511 regs[i].regmap[hr]=regs[i+1].regmap[hr];
8512 regmap_pre[i+1][hr]=regs[i+1].regmap[hr];
8513 regs[i+1].regmap_entry[hr]=regs[i+1].regmap[hr];
8514 regs[i].isconst&=~(1<<hr);
8515 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
8516 constmap[i][hr]=constmap[i+1][hr];
8517 regs[i+1].wasdirty&=~(1<<hr);
8518 regs[i].dirty&=~(1<<hr);
8519 }
8520 }
8521 }
8522 if(dops[i+1].rs2) {
8523 if((hr=get_reg(regs[i+1].regmap,dops[i+1].rs2))>=0)
8524 {
8525 if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
8526 {
8527 regs[i].regmap[hr]=regs[i+1].regmap[hr];
8528 regmap_pre[i+1][hr]=regs[i+1].regmap[hr];
8529 regs[i+1].regmap_entry[hr]=regs[i+1].regmap[hr];
8530 regs[i].isconst&=~(1<<hr);
8531 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
8532 constmap[i][hr]=constmap[i+1][hr];
8533 regs[i+1].wasdirty&=~(1<<hr);
8534 regs[i].dirty&=~(1<<hr);
8535 }
8536 }
8537 }
8538 // Preload target address for load instruction (non-constant)
8539 if(dops[i+1].itype==LOAD&&dops[i+1].rs1&&get_reg(regs[i+1].regmap,dops[i+1].rs1)<0) {
8540 if((hr=get_reg(regs[i+1].regmap,dops[i+1].rt1))>=0)
8541 {
8542 if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
8543 {
8544 regs[i].regmap[hr]=dops[i+1].rs1;
8545 regmap_pre[i+1][hr]=dops[i+1].rs1;
8546 regs[i+1].regmap_entry[hr]=dops[i+1].rs1;
8547 regs[i].isconst&=~(1<<hr);
8548 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
8549 constmap[i][hr]=constmap[i+1][hr];
8550 regs[i+1].wasdirty&=~(1<<hr);
8551 regs[i].dirty&=~(1<<hr);
8552 }
8553 }
8554 }
8555 // Load source into target register
8556 if(dops[i+1].use_lt1&&get_reg(regs[i+1].regmap,dops[i+1].rs1)<0) {
8557 if((hr=get_reg(regs[i+1].regmap,dops[i+1].rt1))>=0)
8558 {
8559 if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
8560 {
8561 regs[i].regmap[hr]=dops[i+1].rs1;
8562 regmap_pre[i+1][hr]=dops[i+1].rs1;
8563 regs[i+1].regmap_entry[hr]=dops[i+1].rs1;
8564 regs[i].isconst&=~(1<<hr);
8565 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
8566 constmap[i][hr]=constmap[i+1][hr];
8567 regs[i+1].wasdirty&=~(1<<hr);
8568 regs[i].dirty&=~(1<<hr);
8569 }
8570 }
8571 }
8572 // Address for store instruction (non-constant)
8573 if(dops[i+1].itype==STORE||dops[i+1].itype==STORELR
8574 ||(dops[i+1].opcode&0x3b)==0x39||(dops[i+1].opcode&0x3b)==0x3a) { // SB/SH/SW/SD/SWC1/SDC1/SWC2/SDC2
8575 if(get_reg(regs[i+1].regmap,dops[i+1].rs1)<0) {
8576 hr=get_reg2(regs[i].regmap,regs[i+1].regmap,-1);
8577 if(hr<0) hr=get_reg_temp(regs[i+1].regmap);
8578 else {
8579 regs[i+1].regmap[hr]=AGEN1+((i+1)&1);
8580 regs[i+1].isconst&=~(1<<hr);
8581 }
8582 assert(hr>=0);
8583 if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
8584 {
8585 regs[i].regmap[hr]=dops[i+1].rs1;
8586 regmap_pre[i+1][hr]=dops[i+1].rs1;
8587 regs[i+1].regmap_entry[hr]=dops[i+1].rs1;
8588 regs[i].isconst&=~(1<<hr);
8589 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
8590 constmap[i][hr]=constmap[i+1][hr];
8591 regs[i+1].wasdirty&=~(1<<hr);
8592 regs[i].dirty&=~(1<<hr);
8593 }
8594 }
8595 }
8596 if(dops[i+1].itype==LOADLR||(dops[i+1].opcode&0x3b)==0x31||(dops[i+1].opcode&0x3b)==0x32) { // LWC1/LDC1, LWC2/LDC2
8597 if(get_reg(regs[i+1].regmap,dops[i+1].rs1)<0) {
8598 int nr;
8599 hr=get_reg(regs[i+1].regmap,FTEMP);
8600 assert(hr>=0);
8601 if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
8602 {
8603 regs[i].regmap[hr]=dops[i+1].rs1;
8604 regmap_pre[i+1][hr]=dops[i+1].rs1;
8605 regs[i+1].regmap_entry[hr]=dops[i+1].rs1;
8606 regs[i].isconst&=~(1<<hr);
8607 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
8608 constmap[i][hr]=constmap[i+1][hr];
8609 regs[i+1].wasdirty&=~(1<<hr);
8610 regs[i].dirty&=~(1<<hr);
8611 }
8612 else if((nr=get_reg2(regs[i].regmap,regs[i+1].regmap,-1))>=0)
8613 {
8614 // move it to another register
8615 regs[i+1].regmap[hr]=-1;
8616 regmap_pre[i+2][hr]=-1;
8617 regs[i+1].regmap[nr]=FTEMP;
8618 regmap_pre[i+2][nr]=FTEMP;
8619 regs[i].regmap[nr]=dops[i+1].rs1;
8620 regmap_pre[i+1][nr]=dops[i+1].rs1;
8621 regs[i+1].regmap_entry[nr]=dops[i+1].rs1;
8622 regs[i].isconst&=~(1<<nr);
8623 regs[i+1].isconst&=~(1<<nr);
8624 regs[i].dirty&=~(1<<nr);
8625 regs[i+1].wasdirty&=~(1<<nr);
8626 regs[i+1].dirty&=~(1<<nr);
8627 regs[i+2].wasdirty&=~(1<<nr);
8628 }
8629 }
8630 }
8631 if(dops[i+1].itype==LOAD||dops[i+1].itype==LOADLR||dops[i+1].itype==STORE||dops[i+1].itype==STORELR/*||dops[i+1].itype==C1LS||||dops[i+1].itype==C2LS*/) {
8632 hr = -1;
8633 if(dops[i+1].itype==LOAD)
8634 hr=get_reg(regs[i+1].regmap,dops[i+1].rt1);
8635 if(dops[i+1].itype==LOADLR||(dops[i+1].opcode&0x3b)==0x31||(dops[i+1].opcode&0x3b)==0x32) // LWC1/LDC1, LWC2/LDC2
8636 hr=get_reg(regs[i+1].regmap,FTEMP);
8637 if(dops[i+1].itype==STORE||dops[i+1].itype==STORELR||(dops[i+1].opcode&0x3b)==0x39||(dops[i+1].opcode&0x3b)==0x3a) { // SWC1/SDC1/SWC2/SDC2
8638 hr=get_reg(regs[i+1].regmap,AGEN1+((i+1)&1));
8639 if(hr<0) hr=get_reg_temp(regs[i+1].regmap);
8640 }
8641 if(hr>=0&&regs[i].regmap[hr]<0) {
8642 int rs=get_reg(regs[i+1].regmap,dops[i+1].rs1);
8643 if(rs>=0&&((regs[i+1].wasconst>>rs)&1)) {
8644 regs[i].regmap[hr]=AGEN1+((i+1)&1);
8645 regmap_pre[i+1][hr]=AGEN1+((i+1)&1);
8646 regs[i+1].regmap_entry[hr]=AGEN1+((i+1)&1);
8647 regs[i].isconst&=~(1<<hr);
8648 regs[i+1].wasdirty&=~(1<<hr);
8649 regs[i].dirty&=~(1<<hr);
8650 }
b372a952 8651 }
8652 }
57871462 8653 }
8654 }
4149788d 8655 }
8656 }
8657}
8658
8659// Write back dirty registers as soon as we will no longer modify them,
8660// so that we don't end up with lots of writes at the branches.
8661static noinline void pass6_clean_registers(int istart, int iend, int wr)
8662{
53358c1d 8663 static u_int wont_dirty[MAXBLOCK];
8664 static u_int will_dirty[MAXBLOCK];
4149788d 8665 int i;
8666 int r;
8667 u_int will_dirty_i,will_dirty_next,temp_will_dirty;
8668 u_int wont_dirty_i,wont_dirty_next,temp_wont_dirty;
8669 if(iend==slen-1) {
8670 will_dirty_i=will_dirty_next=0;
8671 wont_dirty_i=wont_dirty_next=0;
8672 }else{
8673 will_dirty_i=will_dirty_next=will_dirty[iend+1];
8674 wont_dirty_i=wont_dirty_next=wont_dirty[iend+1];
8675 }
8676 for (i=iend;i>=istart;i--)
8677 {
8678 signed char rregmap_i[RRMAP_SIZE];
8679 u_int hr_candirty = 0;
8680 assert(HOST_REGS < 32);
8681 make_rregs(regs[i].regmap, rregmap_i, &hr_candirty);
8682 __builtin_prefetch(regs[i-1].regmap);
8683 if(dops[i].is_jump)
8684 {
8685 signed char branch_rregmap_i[RRMAP_SIZE];
8686 u_int branch_hr_candirty = 0;
8687 make_rregs(branch_regs[i].regmap, branch_rregmap_i, &branch_hr_candirty);
8688 if(ba[i]<start || ba[i]>=(start+slen*4))
8689 {
8690 // Branch out of this block, flush all regs
8691 will_dirty_i = 0;
8692 will_dirty_i |= 1u << (get_rreg(branch_rregmap_i, dops[i].rt1) & 31);
8693 will_dirty_i |= 1u << (get_rreg(branch_rregmap_i, dops[i].rt2) & 31);
8694 will_dirty_i |= 1u << (get_rreg(branch_rregmap_i, dops[i+1].rt1) & 31);
8695 will_dirty_i |= 1u << (get_rreg(branch_rregmap_i, dops[i+1].rt2) & 31);
8696 will_dirty_i |= 1u << (get_rreg(branch_rregmap_i, CCREG) & 31);
8697 will_dirty_i &= branch_hr_candirty;
8698 if (dops[i].is_ujump)
8699 {
8700 // Unconditional branch
8701 wont_dirty_i = 0;
8702 // Merge in delay slot (will dirty)
8703 will_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i].rt1) & 31);
8704 will_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i].rt2) & 31);
8705 will_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i+1].rt1) & 31);
8706 will_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i+1].rt2) & 31);
8707 will_dirty_i |= 1u << (get_rreg(rregmap_i, CCREG) & 31);
8708 will_dirty_i &= hr_candirty;
57871462 8709 }
4149788d 8710 else
8711 {
8712 // Conditional branch
8713 wont_dirty_i = wont_dirty_next;
8714 // Merge in delay slot (will dirty)
8715 // (the original code had no explanation why these 2 are commented out)
8716 //will_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i].rt1) & 31);
8717 //will_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i].rt2) & 31);
8718 will_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i+1].rt1) & 31);
8719 will_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i+1].rt2) & 31);
8720 will_dirty_i |= 1u << (get_rreg(rregmap_i, CCREG) & 31);
8721 will_dirty_i &= hr_candirty;
8722 }
8723 // Merge in delay slot (wont dirty)
8724 wont_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i].rt1) & 31);
8725 wont_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i].rt2) & 31);
8726 wont_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i+1].rt1) & 31);
8727 wont_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i+1].rt2) & 31);
8728 wont_dirty_i |= 1u << (get_rreg(rregmap_i, CCREG) & 31);
8729 wont_dirty_i |= 1u << (get_rreg(branch_rregmap_i, dops[i].rt1) & 31);
8730 wont_dirty_i |= 1u << (get_rreg(branch_rregmap_i, dops[i].rt2) & 31);
8731 wont_dirty_i |= 1u << (get_rreg(branch_rregmap_i, dops[i+1].rt1) & 31);
8732 wont_dirty_i |= 1u << (get_rreg(branch_rregmap_i, dops[i+1].rt2) & 31);
8733 wont_dirty_i |= 1u << (get_rreg(branch_rregmap_i, CCREG) & 31);
8734 wont_dirty_i &= ~(1u << 31);
8735 if(wr) {
8736 #ifndef DESTRUCTIVE_WRITEBACK
8737 branch_regs[i].dirty&=wont_dirty_i;
8738 #endif
8739 branch_regs[i].dirty|=will_dirty_i;
8740 }
8741 }
8742 else
8743 {
8744 // Internal branch
8745 if(ba[i]<=start+i*4) {
8746 // Backward branch
8747 if (dops[i].is_ujump)
8748 {
8749 // Unconditional branch
8750 temp_will_dirty=0;
8751 temp_wont_dirty=0;
8752 // Merge in delay slot (will dirty)
8753 temp_will_dirty |= 1u << (get_rreg(branch_rregmap_i, dops[i].rt1) & 31);
8754 temp_will_dirty |= 1u << (get_rreg(branch_rregmap_i, dops[i].rt2) & 31);
8755 temp_will_dirty |= 1u << (get_rreg(branch_rregmap_i, dops[i+1].rt1) & 31);
8756 temp_will_dirty |= 1u << (get_rreg(branch_rregmap_i, dops[i+1].rt2) & 31);
8757 temp_will_dirty |= 1u << (get_rreg(branch_rregmap_i, CCREG) & 31);
8758 temp_will_dirty &= branch_hr_candirty;
8759 temp_will_dirty |= 1u << (get_rreg(rregmap_i, dops[i].rt1) & 31);
8760 temp_will_dirty |= 1u << (get_rreg(rregmap_i, dops[i].rt2) & 31);
8761 temp_will_dirty |= 1u << (get_rreg(rregmap_i, dops[i+1].rt1) & 31);
8762 temp_will_dirty |= 1u << (get_rreg(rregmap_i, dops[i+1].rt2) & 31);
8763 temp_will_dirty |= 1u << (get_rreg(rregmap_i, CCREG) & 31);
8764 temp_will_dirty &= hr_candirty;
8765 } else {
8766 // Conditional branch (not taken case)
8767 temp_will_dirty=will_dirty_next;
8768 temp_wont_dirty=wont_dirty_next;
8769 // Merge in delay slot (will dirty)
8770 temp_will_dirty |= 1u << (get_rreg(branch_rregmap_i, dops[i].rt1) & 31);
8771 temp_will_dirty |= 1u << (get_rreg(branch_rregmap_i, dops[i].rt2) & 31);
8772 temp_will_dirty |= 1u << (get_rreg(branch_rregmap_i, dops[i+1].rt1) & 31);
8773 temp_will_dirty |= 1u << (get_rreg(branch_rregmap_i, dops[i+1].rt2) & 31);
8774 temp_will_dirty |= 1u << (get_rreg(branch_rregmap_i, CCREG) & 31);
8775 temp_will_dirty &= branch_hr_candirty;
8776 //temp_will_dirty |= 1u << (get_rreg(rregmap_i, dops[i].rt1) & 31);
8777 //temp_will_dirty |= 1u << (get_rreg(rregmap_i, dops[i].rt2) & 31);
8778 temp_will_dirty |= 1u << (get_rreg(rregmap_i, dops[i+1].rt1) & 31);
8779 temp_will_dirty |= 1u << (get_rreg(rregmap_i, dops[i+1].rt2) & 31);
8780 temp_will_dirty |= 1u << (get_rreg(rregmap_i, CCREG) & 31);
8781 temp_will_dirty &= hr_candirty;
8782 }
8783 // Merge in delay slot (wont dirty)
8784 temp_wont_dirty |= 1u << (get_rreg(rregmap_i, dops[i].rt1) & 31);
8785 temp_wont_dirty |= 1u << (get_rreg(rregmap_i, dops[i].rt2) & 31);
8786 temp_wont_dirty |= 1u << (get_rreg(rregmap_i, dops[i+1].rt1) & 31);
8787 temp_wont_dirty |= 1u << (get_rreg(rregmap_i, dops[i+1].rt2) & 31);
8788 temp_wont_dirty |= 1u << (get_rreg(rregmap_i, CCREG) & 31);
8789 temp_wont_dirty |= 1u << (get_rreg(branch_rregmap_i, dops[i].rt1) & 31);
8790 temp_wont_dirty |= 1u << (get_rreg(branch_rregmap_i, dops[i].rt2) & 31);
8791 temp_wont_dirty |= 1u << (get_rreg(branch_rregmap_i, dops[i+1].rt1) & 31);
8792 temp_wont_dirty |= 1u << (get_rreg(branch_rregmap_i, dops[i+1].rt2) & 31);
8793 temp_wont_dirty |= 1u << (get_rreg(branch_rregmap_i, CCREG) & 31);
8794 temp_wont_dirty &= ~(1u << 31);
8795 // Deal with changed mappings
8796 if(i<iend) {
8797 for(r=0;r<HOST_REGS;r++) {
8798 if(r!=EXCLUDE_REG) {
8799 if(regs[i].regmap[r]!=regmap_pre[i][r]) {
8800 temp_will_dirty&=~(1<<r);
8801 temp_wont_dirty&=~(1<<r);
8802 if(regmap_pre[i][r]>0 && regmap_pre[i][r]<34) {
8803 temp_will_dirty|=((unneeded_reg[i]>>regmap_pre[i][r])&1)<<r;
8804 temp_wont_dirty|=((unneeded_reg[i]>>regmap_pre[i][r])&1)<<r;
8805 } else {
8806 temp_will_dirty|=1<<r;
8807 temp_wont_dirty|=1<<r;
8808 }
8809 }
8810 }
8811 }
8812 }
8813 if(wr) {
8814 will_dirty[i]=temp_will_dirty;
8815 wont_dirty[i]=temp_wont_dirty;
8816 pass6_clean_registers((ba[i]-start)>>2,i-1,0);
8817 }else{
8818 // Limit recursion. It can take an excessive amount
8819 // of time if there are a lot of nested loops.
8820 will_dirty[(ba[i]-start)>>2]=0;
8821 wont_dirty[(ba[i]-start)>>2]=-1;
57871462 8822 }
57871462 8823 }
4149788d 8824 /*else*/ if(1)
57871462 8825 {
4149788d 8826 if (dops[i].is_ujump)
8827 {
8828 // Unconditional branch
8829 will_dirty_i=0;
8830 wont_dirty_i=0;
8831 //if(ba[i]>start+i*4) { // Disable recursion (for debugging)
8832 for(r=0;r<HOST_REGS;r++) {
8833 if(r!=EXCLUDE_REG) {
8834 if(branch_regs[i].regmap[r]==regs[(ba[i]-start)>>2].regmap_entry[r]) {
8835 will_dirty_i|=will_dirty[(ba[i]-start)>>2]&(1<<r);
8836 wont_dirty_i|=wont_dirty[(ba[i]-start)>>2]&(1<<r);
8837 }
8838 if(branch_regs[i].regmap[r]>=0) {
8839 will_dirty_i|=((unneeded_reg[(ba[i]-start)>>2]>>branch_regs[i].regmap[r])&1)<<r;
8840 wont_dirty_i|=((unneeded_reg[(ba[i]-start)>>2]>>branch_regs[i].regmap[r])&1)<<r;
8841 }
8842 }
57871462 8843 }
4149788d 8844 //}
8845 // Merge in delay slot
8846 will_dirty_i |= 1u << (get_rreg(branch_rregmap_i, dops[i].rt1) & 31);
8847 will_dirty_i |= 1u << (get_rreg(branch_rregmap_i, dops[i].rt2) & 31);
8848 will_dirty_i |= 1u << (get_rreg(branch_rregmap_i, dops[i+1].rt1) & 31);
8849 will_dirty_i |= 1u << (get_rreg(branch_rregmap_i, dops[i+1].rt2) & 31);
8850 will_dirty_i |= 1u << (get_rreg(branch_rregmap_i, CCREG) & 31);
8851 will_dirty_i &= branch_hr_candirty;
8852 will_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i].rt1) & 31);
8853 will_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i].rt2) & 31);
8854 will_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i+1].rt1) & 31);
8855 will_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i+1].rt2) & 31);
8856 will_dirty_i |= 1u << (get_rreg(rregmap_i, CCREG) & 31);
8857 will_dirty_i &= hr_candirty;
8858 } else {
8859 // Conditional branch
8860 will_dirty_i=will_dirty_next;
8861 wont_dirty_i=wont_dirty_next;
8862 //if(ba[i]>start+i*4) // Disable recursion (for debugging)
8863 for(r=0;r<HOST_REGS;r++) {
8864 if(r!=EXCLUDE_REG) {
8865 signed char target_reg=branch_regs[i].regmap[r];
8866 if(target_reg==regs[(ba[i]-start)>>2].regmap_entry[r]) {
8867 will_dirty_i&=will_dirty[(ba[i]-start)>>2]&(1<<r);
8868 wont_dirty_i|=wont_dirty[(ba[i]-start)>>2]&(1<<r);
8869 }
8870 else if(target_reg>=0) {
8871 will_dirty_i&=((unneeded_reg[(ba[i]-start)>>2]>>target_reg)&1)<<r;
8872 wont_dirty_i|=((unneeded_reg[(ba[i]-start)>>2]>>target_reg)&1)<<r;
8873 }
8874 }
57871462 8875 }
4149788d 8876 // Merge in delay slot
8877 will_dirty_i |= 1u << (get_rreg(branch_rregmap_i, dops[i].rt1) & 31);
8878 will_dirty_i |= 1u << (get_rreg(branch_rregmap_i, dops[i].rt2) & 31);
8879 will_dirty_i |= 1u << (get_rreg(branch_rregmap_i, dops[i+1].rt1) & 31);
8880 will_dirty_i |= 1u << (get_rreg(branch_rregmap_i, dops[i+1].rt2) & 31);
8881 will_dirty_i |= 1u << (get_rreg(branch_rregmap_i, CCREG) & 31);
8882 will_dirty_i &= branch_hr_candirty;
8883 //will_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i].rt1) & 31);
8884 //will_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i].rt2) & 31);
8885 will_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i+1].rt1) & 31);
8886 will_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i+1].rt2) & 31);
8887 will_dirty_i |= 1u << (get_rreg(rregmap_i, CCREG) & 31);
8888 will_dirty_i &= hr_candirty;
57871462 8889 }
4149788d 8890 // Merge in delay slot (won't dirty)
8891 wont_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i].rt1) & 31);
8892 wont_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i].rt2) & 31);
8893 wont_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i+1].rt1) & 31);
8894 wont_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i+1].rt2) & 31);
8895 wont_dirty_i |= 1u << (get_rreg(rregmap_i, CCREG) & 31);
8896 wont_dirty_i |= 1u << (get_rreg(branch_rregmap_i, dops[i].rt1) & 31);
8897 wont_dirty_i |= 1u << (get_rreg(branch_rregmap_i, dops[i].rt2) & 31);
8898 wont_dirty_i |= 1u << (get_rreg(branch_rregmap_i, dops[i+1].rt1) & 31);
8899 wont_dirty_i |= 1u << (get_rreg(branch_rregmap_i, dops[i+1].rt2) & 31);
8900 wont_dirty_i |= 1u << (get_rreg(branch_rregmap_i, CCREG) & 31);
8901 wont_dirty_i &= ~(1u << 31);
8902 if(wr) {
8903 #ifndef DESTRUCTIVE_WRITEBACK
8904 branch_regs[i].dirty&=wont_dirty_i;
8905 #endif
8906 branch_regs[i].dirty|=will_dirty_i;
57871462 8907 }
8908 }
8909 }
57871462 8910 }
4149788d 8911 else if(dops[i].itype==SYSCALL||dops[i].itype==HLECALL||dops[i].itype==INTCALL)
57871462 8912 {
4149788d 8913 // SYSCALL instruction (software interrupt)
8914 will_dirty_i=0;
8915 wont_dirty_i=0;
8916 }
8917 else if(dops[i].itype==COP0 && (source[i]&0x3f)==0x18)
8918 {
8919 // ERET instruction (return from interrupt)
8920 will_dirty_i=0;
8921 wont_dirty_i=0;
8922 }
8923 will_dirty_next=will_dirty_i;
8924 wont_dirty_next=wont_dirty_i;
8925 will_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i].rt1) & 31);
8926 will_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i].rt2) & 31);
8927 will_dirty_i |= 1u << (get_rreg(rregmap_i, CCREG) & 31);
8928 will_dirty_i &= hr_candirty;
8929 wont_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i].rt1) & 31);
8930 wont_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i].rt2) & 31);
8931 wont_dirty_i |= 1u << (get_rreg(rregmap_i, CCREG) & 31);
8932 wont_dirty_i &= ~(1u << 31);
8933 if (i > istart && !dops[i].is_jump) {
8934 // Don't store a register immediately after writing it,
8935 // may prevent dual-issue.
8936 wont_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i-1].rt1) & 31);
8937 wont_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i-1].rt2) & 31);
8938 }
8939 // Save it
8940 will_dirty[i]=will_dirty_i;
8941 wont_dirty[i]=wont_dirty_i;
8942 // Mark registers that won't be dirtied as not dirty
8943 if(wr) {
8944 regs[i].dirty|=will_dirty_i;
8945 #ifndef DESTRUCTIVE_WRITEBACK
8946 regs[i].dirty&=wont_dirty_i;
8947 if(dops[i].is_jump)
57871462 8948 {
4149788d 8949 if (i < iend-1 && !dops[i].is_ujump) {
8950 for(r=0;r<HOST_REGS;r++) {
8951 if(r!=EXCLUDE_REG) {
8952 if(regs[i].regmap[r]==regmap_pre[i+2][r]) {
8953 regs[i+2].wasdirty&=wont_dirty_i|~(1<<r);
8954 }else {/*printf("i: %x (%d) mismatch(+2): %d\n",start+i*4,i,r);assert(!((wont_dirty_i>>r)&1));*/}
57871462 8955 }
8956 }
8957 }
4149788d 8958 }
8959 else
8960 {
8961 if(i<iend) {
8962 for(r=0;r<HOST_REGS;r++) {
8963 if(r!=EXCLUDE_REG) {
8964 if(regs[i].regmap[r]==regmap_pre[i+1][r]) {
8965 regs[i+1].wasdirty&=wont_dirty_i|~(1<<r);
8966 }else {/*printf("i: %x (%d) mismatch(+1): %d\n",start+i*4,i,r);assert(!((wont_dirty_i>>r)&1));*/}
57871462 8967 }
8968 }
8969 }
4149788d 8970 }
8971 #endif
8972 }
8973 // Deal with changed mappings
8974 temp_will_dirty=will_dirty_i;
8975 temp_wont_dirty=wont_dirty_i;
8976 for(r=0;r<HOST_REGS;r++) {
8977 if(r!=EXCLUDE_REG) {
8978 int nr;
8979 if(regs[i].regmap[r]==regmap_pre[i][r]) {
8980 if(wr) {
8981 #ifndef DESTRUCTIVE_WRITEBACK
8982 regs[i].wasdirty&=wont_dirty_i|~(1<<r);
8983 #endif
8984 regs[i].wasdirty|=will_dirty_i&(1<<r);
57871462 8985 }
4149788d 8986 }
8987 else if(regmap_pre[i][r]>=0&&(nr=get_rreg(rregmap_i,regmap_pre[i][r]))>=0) {
8988 // Register moved to a different register
8989 will_dirty_i&=~(1<<r);
8990 wont_dirty_i&=~(1<<r);
8991 will_dirty_i|=((temp_will_dirty>>nr)&1)<<r;
8992 wont_dirty_i|=((temp_wont_dirty>>nr)&1)<<r;
8993 if(wr) {
8994 #ifndef DESTRUCTIVE_WRITEBACK
8995 regs[i].wasdirty&=wont_dirty_i|~(1<<r);
8996 #endif
8997 regs[i].wasdirty|=will_dirty_i&(1<<r);
8998 }
8999 }
9000 else {
9001 will_dirty_i&=~(1<<r);
9002 wont_dirty_i&=~(1<<r);
9003 if(regmap_pre[i][r]>0 && regmap_pre[i][r]<34) {
9004 will_dirty_i|=((unneeded_reg[i]>>regmap_pre[i][r])&1)<<r;
9005 wont_dirty_i|=((unneeded_reg[i]>>regmap_pre[i][r])&1)<<r;
9006 } else {
9007 wont_dirty_i|=1<<r;
9008 /*printf("i: %x (%d) mismatch: %d\n",start+i*4,i,r);assert(!((will_dirty>>r)&1));*/
57871462 9009 }
9010 }
9011 }
9012 }
9013 }
4149788d 9014}
9015
9016static noinline void pass10_expire_blocks(void)
9017{
9018 int i, end;
9019 end = (((out-ndrc->translation_cache)>>(TARGET_SIZE_2-16)) + 16384) & 65535;
9020 while (expirep != end)
9021 {
9022 int shift=TARGET_SIZE_2-3; // Divide into 8 blocks
9023 uintptr_t base_offs = ((uintptr_t)(expirep >> 13) << shift); // Base offset of this block
9024 uintptr_t base_offs_s = base_offs >> shift;
9025 inv_debug("EXP: Phase %d\n",expirep);
9026 switch((expirep>>11)&3)
9027 {
9028 case 0:
9029 // Clear jump_in and jump_dirty
9030 ll_remove_matching_addrs(jump_in+(expirep&2047),base_offs_s,shift);
9031 ll_remove_matching_addrs(jump_dirty+(expirep&2047),base_offs_s,shift);
9032 ll_remove_matching_addrs(jump_in+2048+(expirep&2047),base_offs_s,shift);
9033 ll_remove_matching_addrs(jump_dirty+2048+(expirep&2047),base_offs_s,shift);
9034 break;
9035 case 1:
9036 // Clear pointers
9037 ll_kill_pointers(jump_out[expirep&2047],base_offs_s,shift);
9038 ll_kill_pointers(jump_out[(expirep&2047)+2048],base_offs_s,shift);
9039 break;
9040 case 2:
9041 // Clear hash table
9042 for(i=0;i<32;i++) {
9043 struct ht_entry *ht_bin = &hash_table[((expirep&2047)<<5)+i];
9044 uintptr_t o1 = (u_char *)ht_bin->tcaddr[1] - ndrc->translation_cache;
9045 uintptr_t o2 = o1 - MAX_OUTPUT_BLOCK_SIZE;
9046 if ((o1 >> shift) == base_offs_s || (o2 >> shift) == base_offs_s) {
9047 inv_debug("EXP: Remove hash %x -> %p\n",ht_bin->vaddr[1],ht_bin->tcaddr[1]);
9048 ht_bin->vaddr[1] = -1;
9049 ht_bin->tcaddr[1] = NULL;
9050 }
9051 o1 = (u_char *)ht_bin->tcaddr[0] - ndrc->translation_cache;
9052 o2 = o1 - MAX_OUTPUT_BLOCK_SIZE;
9053 if ((o1 >> shift) == base_offs_s || (o2 >> shift) == base_offs_s) {
9054 inv_debug("EXP: Remove hash %x -> %p\n",ht_bin->vaddr[0],ht_bin->tcaddr[0]);
9055 ht_bin->vaddr[0] = ht_bin->vaddr[1];
9056 ht_bin->tcaddr[0] = ht_bin->tcaddr[1];
9057 ht_bin->vaddr[1] = -1;
9058 ht_bin->tcaddr[1] = NULL;
9059 }
9060 }
9061 break;
9062 case 3:
9063 // Clear jump_out
9064 if((expirep&2047)==0)
9065 do_clear_cache();
9066 ll_remove_matching_addrs(jump_out+(expirep&2047),base_offs_s,shift);
9067 ll_remove_matching_addrs(jump_out+2048+(expirep&2047),base_offs_s,shift);
9068 break;
9069 }
9070 expirep=(expirep+1)&65535;
9071 }
9072}
9073
9074int new_recompile_block(u_int addr)
9075{
9076 u_int pagelimit = 0;
9077 u_int state_rflags = 0;
9078 int i;
9079
9080 assem_debug("NOTCOMPILED: addr = %x -> %p\n", addr, out);
9081
9082 // this is just for speculation
9083 for (i = 1; i < 32; i++) {
9084 if ((psxRegs.GPR.r[i] & 0xffff0000) == 0x1f800000)
9085 state_rflags |= 1 << i;
9086 }
9087
9088 start = (u_int)addr&~3;
9089 //assert(((u_int)addr&1)==0); // start-in-delay-slot flag
9090 new_dynarec_did_compile=1;
9091 if (Config.HLE && start == 0x80001000) // hlecall
9092 {
9093 // XXX: is this enough? Maybe check hleSoftCall?
9094 void *beginning=start_block();
9095 u_int page=get_page(start);
9096
9097 invalid_code[start>>12]=0;
9098 emit_movimm(start,0);
9099 emit_writeword(0,&pcaddr);
9100 emit_far_jump(new_dyna_leave);
9101 literal_pool(0);
9102 end_block(beginning);
9103 ll_add_flags(jump_in+page,start,state_rflags,(void *)beginning);
9104 return 0;
9105 }
9106 else if (f1_hack && hack_addr == 0) {
9107 void *beginning = start_block();
9108 u_int page = get_page(start);
9109 emit_movimm(start, 0);
9110 emit_writeword(0, &hack_addr);
9111 emit_readword(&psxRegs.GPR.n.sp, 0);
9112 emit_readptr(&mem_rtab, 1);
9113 emit_shrimm(0, 12, 2);
9114 emit_readptr_dualindexedx_ptrlen(1, 2, 1);
9115 emit_addimm(0, 0x18, 0);
9116 emit_adds_ptr(1, 1, 1);
9117 emit_ldr_dualindexed(1, 0, 0);
9118 emit_writeword(0, &psxRegs.GPR.r[26]); // lw k0, 0x18(sp)
9119 emit_far_call(get_addr_ht);
9120 emit_jmpreg(0); // jr k0
9121 literal_pool(0);
9122 end_block(beginning);
9123
9124 ll_add_flags(jump_in + page, start, state_rflags, beginning);
9125 SysPrintf("F1 hack to %08x\n", start);
9126 return 0;
9127 }
9128
9129 cycle_multiplier_active = cycle_multiplier_override && cycle_multiplier == CYCLE_MULT_DEFAULT
9130 ? cycle_multiplier_override : cycle_multiplier;
9131
9132 source = get_source_start(start, &pagelimit);
9133 if (source == NULL) {
9134 if (addr != hack_addr) {
9135 SysPrintf("Compile at bogus memory address: %08x\n", addr);
9136 hack_addr = addr;
9137 }
9138 //abort();
9139 return -1;
9140 }
9141
9142 /* Pass 1: disassemble */
9143 /* Pass 2: register dependencies, branch targets */
9144 /* Pass 3: register allocation */
9145 /* Pass 4: branch dependencies */
9146 /* Pass 5: pre-alloc */
9147 /* Pass 6: optimize clean/dirty state */
9148 /* Pass 7: flag 32-bit registers */
9149 /* Pass 8: assembly */
9150 /* Pass 9: linker */
9151 /* Pass 10: garbage collection / free memory */
9152
9153 /* Pass 1 disassembly */
9154
9155 pass1_disassemble(pagelimit);
9156
9157 int clear_hack_addr = apply_hacks();
9158
9159 /* Pass 2 - Register dependencies and branch targets */
9160
9161 pass2_unneeded_regs(0,slen-1,0);
9162
9163 /* Pass 3 - Register allocation */
9164
9165 pass3_register_alloc(addr);
9166
9167 /* Pass 4 - Cull unused host registers */
9168
9169 pass4_cull_unused_regs();
9170
9171 /* Pass 5 - Pre-allocate registers */
9172
9173 pass5a_preallocate1();
9174 pass5b_preallocate2();
9f51b4b9 9175
57871462 9176 /* Pass 6 - Optimize clean/dirty state */
4149788d 9177 pass6_clean_registers(0, slen-1, 1);
9f51b4b9 9178
57871462 9179 /* Pass 7 - Identify 32-bit registers */
04fd948a 9180 for (i=slen-1;i>=0;i--)
9181 {
cf95b4f0 9182 if(dops[i].itype==CJUMP||dops[i].itype==SJUMP)
04fd948a 9183 {
9184 // Conditional branch
9185 if((source[i]>>16)!=0x1000&&i<slen-2) {
9186 // Mark this address as a branch target since it may be called
9187 // upon return from interrupt
cf95b4f0 9188 dops[i+2].bt=1;
04fd948a 9189 }
9190 }
9191 }
57871462 9192
cf95b4f0 9193 if(dops[slen-1].itype==SPAN) {
9194 dops[slen-1].bt=1; // Mark as a branch target so instruction can restart after exception
57871462 9195 }
4600ba03 9196
57871462 9197 /* Pass 8 - Assembly */
9198 linkcount=0;stubcount=0;
4149788d 9199 is_delayslot=0;
57871462 9200 u_int dirty_pre=0;
d148d265 9201 void *beginning=start_block();
4149788d 9202 int ds = 0;
57871462 9203 if((u_int)addr&1) {
9204 ds=1;
9205 pagespan_ds();
9206 }
df4dc2b1 9207 void *instr_addr0_override = NULL;
9ad4d757 9208
9ad4d757 9209 if (start == 0x80030000) {
3968e69e 9210 // nasty hack for the fastbios thing
96186eba 9211 // override block entry to this code
df4dc2b1 9212 instr_addr0_override = out;
9ad4d757 9213 emit_movimm(start,0);
96186eba 9214 // abuse io address var as a flag that we
9215 // have already returned here once
643aeae3 9216 emit_readword(&address,1);
9217 emit_writeword(0,&pcaddr);
9218 emit_writeword(0,&address);
9ad4d757 9219 emit_cmp(0,1);
3968e69e 9220 #ifdef __aarch64__
9221 emit_jeq(out + 4*2);
2a014d73 9222 emit_far_jump(new_dyna_leave);
3968e69e 9223 #else
643aeae3 9224 emit_jne(new_dyna_leave);
3968e69e 9225 #endif
9ad4d757 9226 }
57871462 9227 for(i=0;i<slen;i++)
9228 {
9de8a0c3 9229 __builtin_prefetch(regs[i+1].regmap);
670c0f22 9230 check_regmap(regmap_pre[i]);
9231 check_regmap(regs[i].regmap_entry);
9232 check_regmap(regs[i].regmap);
57871462 9233 //if(ds) printf("ds: ");
4600ba03 9234 disassemble_inst(i);
57871462 9235 if(ds) {
9236 ds=0; // Skip delay slot
cf95b4f0 9237 if(dops[i].bt) assem_debug("OOPS - branch into delay slot\n");
df4dc2b1 9238 instr_addr[i] = NULL;
57871462 9239 } else {
ffb0b9e0 9240 speculate_register_values(i);
57871462 9241 #ifndef DESTRUCTIVE_WRITEBACK
fe807a8a 9242 if (i < 2 || !dops[i-2].is_ujump)
57871462 9243 {
ad49de89 9244 wb_valid(regmap_pre[i],regs[i].regmap_entry,dirty_pre,regs[i].wasdirty,unneeded_reg[i]);
57871462 9245 }
fe807a8a 9246 if((dops[i].itype==CJUMP||dops[i].itype==SJUMP)) {
f776eb14 9247 dirty_pre=branch_regs[i].dirty;
9248 }else{
f776eb14 9249 dirty_pre=regs[i].dirty;
9250 }
57871462 9251 #endif
9252 // write back
fe807a8a 9253 if (i < 2 || !dops[i-2].is_ujump)
57871462 9254 {
ad49de89 9255 wb_invalidate(regmap_pre[i],regs[i].regmap_entry,regs[i].wasdirty,unneeded_reg[i]);
57871462 9256 loop_preload(regmap_pre[i],regs[i].regmap_entry);
9257 }
9258 // branch target entry point
df4dc2b1 9259 instr_addr[i] = out;
57871462 9260 assem_debug("<->\n");
2330734f 9261 drc_dbg_emit_do_cmp(i, ccadj[i]);
7f94b097 9262 if (clear_hack_addr) {
9263 emit_movimm(0, 0);
9264 emit_writeword(0, &hack_addr);
9265 clear_hack_addr = 0;
9266 }
dd114d7d 9267
57871462 9268 // load regs
9269 if(regs[i].regmap_entry[HOST_CCREG]==CCREG&&regs[i].regmap[HOST_CCREG]!=CCREG)
ad49de89 9270 wb_register(CCREG,regs[i].regmap_entry,regs[i].wasdirty);
cf95b4f0 9271 load_regs(regs[i].regmap_entry,regs[i].regmap,dops[i].rs1,dops[i].rs2);
57871462 9272 address_generation(i,&regs[i],regs[i].regmap_entry);
ad49de89 9273 load_consts(regmap_pre[i],regs[i].regmap,i);
fe807a8a 9274 if(dops[i].is_jump)
57871462 9275 {
9276 // Load the delay slot registers if necessary
cf95b4f0 9277 if(dops[i+1].rs1!=dops[i].rs1&&dops[i+1].rs1!=dops[i].rs2&&(dops[i+1].rs1!=dops[i].rt1||dops[i].rt1==0))
9278 load_regs(regs[i].regmap_entry,regs[i].regmap,dops[i+1].rs1,dops[i+1].rs1);
9279 if(dops[i+1].rs2!=dops[i+1].rs1&&dops[i+1].rs2!=dops[i].rs1&&dops[i+1].rs2!=dops[i].rs2&&(dops[i+1].rs2!=dops[i].rt1||dops[i].rt1==0))
9280 load_regs(regs[i].regmap_entry,regs[i].regmap,dops[i+1].rs2,dops[i+1].rs2);
37387d8b 9281 if (ram_offset && (dops[i+1].is_load || dops[i+1].is_store))
53358c1d 9282 load_reg(regs[i].regmap_entry,regs[i].regmap,ROREG);
37387d8b 9283 if (dops[i+1].is_store)
53358c1d 9284 load_reg(regs[i].regmap_entry,regs[i].regmap,INVCP);
57871462 9285 }
9286 else if(i+1<slen)
9287 {
9288 // Preload registers for following instruction
cf95b4f0 9289 if(dops[i+1].rs1!=dops[i].rs1&&dops[i+1].rs1!=dops[i].rs2)
9290 if(dops[i+1].rs1!=dops[i].rt1&&dops[i+1].rs1!=dops[i].rt2)
9291 load_regs(regs[i].regmap_entry,regs[i].regmap,dops[i+1].rs1,dops[i+1].rs1);
9292 if(dops[i+1].rs2!=dops[i+1].rs1&&dops[i+1].rs2!=dops[i].rs1&&dops[i+1].rs2!=dops[i].rs2)
9293 if(dops[i+1].rs2!=dops[i].rt1&&dops[i+1].rs2!=dops[i].rt2)
9294 load_regs(regs[i].regmap_entry,regs[i].regmap,dops[i+1].rs2,dops[i+1].rs2);
57871462 9295 }
9296 // TODO: if(is_ooo(i)) address_generation(i+1);
9a3ccfeb 9297 if (!dops[i].is_jump || dops[i].itype == CJUMP)
53358c1d 9298 load_reg(regs[i].regmap_entry,regs[i].regmap,CCREG);
37387d8b 9299 if (ram_offset && (dops[i].is_load || dops[i].is_store))
53358c1d 9300 load_reg(regs[i].regmap_entry,regs[i].regmap,ROREG);
37387d8b 9301 if (dops[i].is_store)
53358c1d 9302 load_reg(regs[i].regmap_entry,regs[i].regmap,INVCP);
2330734f 9303
9304 ds = assemble(i, &regs[i], ccadj[i]);
9305
fe807a8a 9306 if (dops[i].is_ujump)
57871462 9307 literal_pool(1024);
9308 else
9309 literal_pool_jumpover(256);
9310 }
9311 }
3d680478 9312
9313 assert(slen > 0);
cf95b4f0 9314 if (slen > 0 && dops[slen-1].itype == INTCALL) {
3d680478 9315 // no ending needed for this block since INTCALL never returns
9316 }
57871462 9317 // If the block did not end with an unconditional branch,
9318 // add a jump to the next instruction.
3d680478 9319 else if (i > 1) {
fe807a8a 9320 if (!dops[i-2].is_ujump && dops[i-1].itype != SPAN) {
9321 assert(!dops[i-1].is_jump);
57871462 9322 assert(i==slen);
cf95b4f0 9323 if(dops[i-2].itype!=CJUMP&&dops[i-2].itype!=SJUMP) {
ad49de89 9324 store_regs_bt(regs[i-1].regmap,regs[i-1].dirty,start+i*4);
57871462 9325 if(regs[i-1].regmap[HOST_CCREG]!=CCREG)
9326 emit_loadreg(CCREG,HOST_CCREG);
2330734f 9327 emit_addimm(HOST_CCREG, ccadj[i-1] + CLOCK_ADJUST(1), HOST_CCREG);
57871462 9328 }
fe807a8a 9329 else
57871462 9330 {
ad49de89 9331 store_regs_bt(branch_regs[i-2].regmap,branch_regs[i-2].dirty,start+i*4);
57871462 9332 assert(branch_regs[i-2].regmap[HOST_CCREG]==CCREG);
9333 }
643aeae3 9334 add_to_linker(out,start+i*4,0);
57871462 9335 emit_jmp(0);
9336 }
9337 }
9338 else
9339 {
9340 assert(i>0);
fe807a8a 9341 assert(!dops[i-1].is_jump);
ad49de89 9342 store_regs_bt(regs[i-1].regmap,regs[i-1].dirty,start+i*4);
57871462 9343 if(regs[i-1].regmap[HOST_CCREG]!=CCREG)
9344 emit_loadreg(CCREG,HOST_CCREG);
2330734f 9345 emit_addimm(HOST_CCREG, ccadj[i-1] + CLOCK_ADJUST(1), HOST_CCREG);
643aeae3 9346 add_to_linker(out,start+i*4,0);
57871462 9347 emit_jmp(0);
9348 }
9349
9350 // TODO: delay slot stubs?
9351 // Stubs
9352 for(i=0;i<stubcount;i++)
9353 {
b14b6a8f 9354 switch(stubs[i].type)
57871462 9355 {
9356 case LOADB_STUB:
9357 case LOADH_STUB:
9358 case LOADW_STUB:
9359 case LOADD_STUB:
9360 case LOADBU_STUB:
9361 case LOADHU_STUB:
9362 do_readstub(i);break;
9363 case STOREB_STUB:
9364 case STOREH_STUB:
9365 case STOREW_STUB:
9366 case STORED_STUB:
9367 do_writestub(i);break;
9368 case CC_STUB:
9369 do_ccstub(i);break;
9370 case INVCODE_STUB:
9371 do_invstub(i);break;
9372 case FP_STUB:
9373 do_cop1stub(i);break;
9374 case STORELR_STUB:
9375 do_unalignedwritestub(i);break;
9376 }
9377 }
9378
9ad4d757 9379 if (instr_addr0_override)
9380 instr_addr[0] = instr_addr0_override;
9381
57871462 9382 /* Pass 9 - Linker */
9383 for(i=0;i<linkcount;i++)
9384 {
643aeae3 9385 assem_debug("%p -> %8x\n",link_addr[i].addr,link_addr[i].target);
57871462 9386 literal_pool(64);
643aeae3 9387 if (!link_addr[i].ext)
57871462 9388 {
643aeae3 9389 void *stub = out;
9390 void *addr = check_addr(link_addr[i].target);
9391 emit_extjump(link_addr[i].addr, link_addr[i].target);
9392 if (addr) {
9393 set_jump_target(link_addr[i].addr, addr);
3d680478 9394 add_jump_out(link_addr[i].target,stub);
57871462 9395 }
643aeae3 9396 else
9397 set_jump_target(link_addr[i].addr, stub);
57871462 9398 }
9399 else
9400 {
9401 // Internal branch
643aeae3 9402 int target=(link_addr[i].target-start)>>2;
57871462 9403 assert(target>=0&&target<slen);
9404 assert(instr_addr[target]);
9405 //#ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
643aeae3 9406 //set_jump_target_fillslot(link_addr[i].addr,instr_addr[target],link_addr[i].ext>>1);
57871462 9407 //#else
643aeae3 9408 set_jump_target(link_addr[i].addr, instr_addr[target]);
57871462 9409 //#endif
9410 }
9411 }
3d680478 9412
9413 u_int source_len = slen*4;
cf95b4f0 9414 if (dops[slen-1].itype == INTCALL && source_len > 4)
3d680478 9415 // no need to treat the last instruction as compiled
9416 // as interpreter fully handles it
9417 source_len -= 4;
9418
9419 if ((u_char *)copy + source_len > (u_char *)shadow + sizeof(shadow))
9420 copy = shadow;
9421
57871462 9422 // External Branch Targets (jump_in)
57871462 9423 for(i=0;i<slen;i++)
9424 {
cf95b4f0 9425 if(dops[i].bt||i==0)
57871462 9426 {
9427 if(instr_addr[i]) // TODO - delay slots (=null)
9428 {
9429 u_int vaddr=start+i*4;
94d23bb9 9430 u_int page=get_page(vaddr);
9431 u_int vpage=get_vpage(vaddr);
57871462 9432 literal_pool(256);
57871462 9433 {
df4dc2b1 9434 assem_debug("%p (%d) <- %8x\n",instr_addr[i],i,start+i*4);
57871462 9435 assem_debug("jump_in: %x\n",start+i*4);
df4dc2b1 9436 ll_add(jump_dirty+vpage,vaddr,out);
3d680478 9437 void *entry_point = do_dirty_stub(i, source_len);
df4dc2b1 9438 ll_add_flags(jump_in+page,vaddr,state_rflags,entry_point);
57871462 9439 // If there was an existing entry in the hash table,
9440 // replace it with the new address.
9441 // Don't add new entries. We'll insert the
9442 // ones that actually get used in check_addr().
df4dc2b1 9443 struct ht_entry *ht_bin = hash_table_get(vaddr);
9444 if (ht_bin->vaddr[0] == vaddr)
9445 ht_bin->tcaddr[0] = entry_point;
9446 if (ht_bin->vaddr[1] == vaddr)
9447 ht_bin->tcaddr[1] = entry_point;
57871462 9448 }
57871462 9449 }
9450 }
9451 }
9452 // Write out the literal pool if necessary
9453 literal_pool(0);
9454 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
9455 // Align code
9456 if(((u_int)out)&7) emit_addnop(13);
9457 #endif
01d26796 9458 assert(out - (u_char *)beginning < MAX_OUTPUT_BLOCK_SIZE);
643aeae3 9459 //printf("shadow buffer: %p-%p\n",copy,(u_char *)copy+slen*4);
3d680478 9460 memcpy(copy, source, source_len);
9461 copy += source_len;
9f51b4b9 9462
d148d265 9463 end_block(beginning);
9f51b4b9 9464
57871462 9465 // If we're within 256K of the end of the buffer,
9466 // start over from the beginning. (Is 256K enough?)
2a014d73 9467 if (out > ndrc->translation_cache + sizeof(ndrc->translation_cache) - MAX_OUTPUT_BLOCK_SIZE)
9468 out = ndrc->translation_cache;
9f51b4b9 9469
57871462 9470 // Trap writes to any of the pages we compiled
398d6924 9471 mark_valid_code(start, slen*4);
9f51b4b9 9472
57871462 9473 /* Pass 10 - Free memory by expiring oldest blocks */
9f51b4b9 9474
4149788d 9475 pass10_expire_blocks();
9476
37387d8b 9477#ifdef ASSEM_PRINT
9478 fflush(stdout);
9479#endif
ece032e6 9480 stat_inc(stat_bc_direct);
57871462 9481 return 0;
9482}
b9b61529 9483
9484// vim:shiftwidth=2:expandtab
ARM optimized PCSX fork