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reduce some code duplication
[pcsx_rearmed.git] / libpcsxcore / new_dynarec / new_dynarec.c
CommitLineData
57871462 1/* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
2 * Mupen64plus - new_dynarec.c *
20d507ba 3 * Copyright (C) 2009-2011 Ari64 *
57871462 4 * *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
9 * *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
14 * *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. *
19 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */
20
21#include <stdlib.h>
22#include <stdint.h> //include for uint64_t
23#include <assert.h>
d848b60a 24#include <errno.h>
4600ba03 25#include <sys/mman.h>
d148d265 26#ifdef __MACH__
27#include <libkern/OSCacheControl.h>
28#endif
1e212a25 29#ifdef _3DS
30#include <3ds_utils.h>
31#endif
3039c914 32#ifdef HAVE_LIBNX
33#include <switch.h>
34static Jit g_jit;
35#endif
57871462 36
d148d265 37#include "new_dynarec_config.h"
3968e69e 38#include "../psxhle.h"
39#include "../psxinterpreter.h"
81dbbf4c 40#include "../gte.h"
41#include "emu_if.h" // emulator interface
a5cd72d0 42#include "linkage_offsets.h"
43#include "compiler_features.h"
cdc2da64 44#include "arm_features.h"
57871462 45
b14b6a8f 46#ifndef ARRAY_SIZE
47#define ARRAY_SIZE(x) (sizeof(x) / sizeof(x[0]))
48#endif
e3c6bdb5 49#ifndef min
50#define min(a, b) ((b) < (a) ? (b) : (a))
51#endif
32631e6a 52#ifndef max
53#define max(a, b) ((b) > (a) ? (b) : (a))
54#endif
b14b6a8f 55
4600ba03 56//#define DISASM
32631e6a 57//#define ASSEM_PRINT
a5cd72d0 58//#define REGMAP_PRINT // with DISASM only
9b495f6e 59//#define INV_DEBUG_W
ece032e6 60//#define STAT_PRINT
32631e6a 61
62#ifdef ASSEM_PRINT
63#define assem_debug printf
64#else
4600ba03 65#define assem_debug(...)
32631e6a 66#endif
67//#define inv_debug printf
4600ba03 68#define inv_debug(...)
57871462 69
70#ifdef __i386__
71#include "assem_x86.h"
72#endif
73#ifdef __x86_64__
74#include "assem_x64.h"
75#endif
76#ifdef __arm__
77#include "assem_arm.h"
78#endif
be516ebe 79#ifdef __aarch64__
80#include "assem_arm64.h"
81#endif
57871462 82
81dbbf4c 83#define RAM_SIZE 0x200000
d3201e39 84#define MAXBLOCK 2048
57871462 85#define MAX_OUTPUT_BLOCK_SIZE 262144
93c0345b 86#define EXPIRITY_OFFSET (MAX_OUTPUT_BLOCK_SIZE * 2)
87#define PAGE_COUNT 1024
2573466a 88
882a08fc 89#if defined(HAVE_CONDITIONAL_CALL) && !defined(DESTRUCTIVE_SHIFT)
90#define INVALIDATE_USE_COND_CALL
91#endif
92
66ea165f 93#ifdef VITA
94// apparently Vita has a 16MB limit, so either we cut tc in half,
95// or use this hack (it's a hack because tc size was designed to be power-of-2)
96#define TC_REDUCE_BYTES 4096
97#else
98#define TC_REDUCE_BYTES 0
99#endif
100
d9e2b173 101struct ndrc_tramp
102{
103 struct tramp_insns ops[2048 / sizeof(struct tramp_insns)];
104 const void *f[2048 / sizeof(void *)];
105};
106
2a014d73 107struct ndrc_mem
108{
66ea165f 109 u_char translation_cache[(1 << TARGET_SIZE_2) - TC_REDUCE_BYTES];
d9e2b173 110 struct ndrc_tramp tramp;
2a014d73 111};
112
113#ifdef BASE_ADDR_DYNAMIC
114static struct ndrc_mem *ndrc;
115#else
116static struct ndrc_mem ndrc_ __attribute__((aligned(4096)));
117static struct ndrc_mem *ndrc = &ndrc_;
118#endif
d9e2b173 119#ifdef TC_WRITE_OFFSET
3039c914 120# ifdef __GLIBC__
121# include <sys/types.h>
122# include <sys/stat.h>
123# include <fcntl.h>
124# include <unistd.h>
125# endif
126static long ndrc_write_ofs;
d9e2b173 127#define NDRC_WRITE_OFFSET(x) (void *)((char *)(x) + ndrc_write_ofs)
3039c914 128#else
d9e2b173 129#define NDRC_WRITE_OFFSET(x) (x)
3039c914 130#endif
2a014d73 131
b14b6a8f 132// stubs
133enum stub_type {
134 CC_STUB = 1,
a5cd72d0 135 //FP_STUB = 2,
b14b6a8f 136 LOADB_STUB = 3,
137 LOADH_STUB = 4,
138 LOADW_STUB = 5,
a5cd72d0 139 //LOADD_STUB = 6,
b14b6a8f 140 LOADBU_STUB = 7,
141 LOADHU_STUB = 8,
142 STOREB_STUB = 9,
143 STOREH_STUB = 10,
144 STOREW_STUB = 11,
a5cd72d0 145 //STORED_STUB = 12,
b14b6a8f 146 STORELR_STUB = 13,
147 INVCODE_STUB = 14,
a5cd72d0 148 OVERFLOW_STUB = 15,
277718fa 149 ALIGNMENT_STUB = 16,
b14b6a8f 150};
151
6cc8d23c 152// regmap_pre[i] - regs before [i] insn starts; dirty things here that
153// don't match .regmap will be written back
154// [i].regmap_entry - regs that must be set up if someone jumps here
155// [i].regmap - regs [i] insn will read/(over)write
2acc46cd 156// branch_regs[i].* - same as above but for branches, takes delay slot into account
57871462 157struct regstat
158{
6cc8d23c 159 signed char regmap_entry[HOST_REGS];
57871462 160 signed char regmap[HOST_REGS];
a22ccd6a 161 u_int wasdirty;
162 u_int dirty;
24058131 163 u_int wasconst; // before; for example 'lw r2, (r2)' wasconst is true
a5cd72d0 164 u_int isconst; // ... but isconst is false when r2 is known (hr)
8575a877 165 u_int loadedconst; // host regs that have constants loaded
90f98e7c 166 u_int noevict; // can't evict this hr (alloced by current op)
9b495f6e 167 //u_int waswritten; // MIPS regs that were used as store base before
a22ccd6a 168 uint64_t u;
57871462 169};
170
df4dc2b1 171struct ht_entry
172{
173 u_int vaddr[2];
174 void *tcaddr[2];
175};
176
b14b6a8f 177struct code_stub
178{
179 enum stub_type type;
180 void *addr;
181 void *retaddr;
182 u_int a;
183 uintptr_t b;
184 uintptr_t c;
185 u_int d;
186 u_int e;
187};
188
643aeae3 189struct link_entry
190{
191 void *addr;
192 u_int target;
104df9d3 193 u_int internal;
194};
195
196struct block_info
197{
198 struct block_info *next;
199 const void *source;
200 const void *copy;
201 u_int start; // vaddr of the block start
202 u_int len; // of the whole block source
203 u_int tc_offs;
204 //u_int tc_len;
205 u_int reg_sv_flags;
3280e616 206 u_char is_dirty;
207 u_char inv_near_misses;
104df9d3 208 u_short jump_in_cnt;
209 struct {
210 u_int vaddr;
211 void *addr;
212 } jump_in[0];
643aeae3 213};
214
b7ad2f2c 215struct jump_info
216{
217 int alloc;
218 int count;
219 struct {
220 u_int target_vaddr;
221 void *stub;
222 } e[0];
223};
224
cf95b4f0 225static struct decoded_insn
226{
227 u_char itype;
a5cd72d0 228 u_char opcode; // bits 31-26
229 u_char opcode2; // (depends on opcode)
cf95b4f0 230 u_char rs1;
231 u_char rs2;
232 u_char rt1;
233 u_char rt2;
53dc27f6 234 u_char use_lt1:1;
cf95b4f0 235 u_char bt:1;
cf95b4f0 236 u_char ooo:1;
237 u_char is_ds:1;
fe807a8a 238 u_char is_jump:1;
239 u_char is_ujump:1;
37387d8b 240 u_char is_load:1;
241 u_char is_store:1;
a5cd72d0 242 u_char is_delay_load:1; // is_load + MFC/CFC
243 u_char is_exception:1; // unconditional, also interp. fallback
244 u_char may_except:1; // might generate an exception
f9e9616e 245 u_char ls_type:2; // load/store type (ls_width_type)
cf95b4f0 246} dops[MAXBLOCK];
247
f9e9616e 248enum ls_width_type {
249 LS_8 = 0, LS_16, LS_32, LS_LR
250};
251
277718fa 252static struct compile_info
253{
254 int imm;
255 u_int ba;
256 int ccadj;
257 signed char min_free_regs;
258 signed char addr;
259 signed char reserved[2];
260} cinfo[MAXBLOCK];
261
398d6924 262 static u_char *out;
6d75addf 263 static char invalid_code[0x100000];
104df9d3 264 static struct ht_entry hash_table[65536];
93c0345b 265 static struct block_info *blocks[PAGE_COUNT];
b7ad2f2c 266 static struct jump_info *jumps[PAGE_COUNT];
e2b5e7aa 267 static u_int start;
268 static u_int *source;
bedfea38 269 static uint64_t gte_rs[MAXBLOCK]; // gte: 32 data and 32 ctl regs
270 static uint64_t gte_rt[MAXBLOCK];
271 static uint64_t gte_unneeded[MAXBLOCK];
ffb0b9e0 272 static u_int smrv[32]; // speculated MIPS register values
273 static u_int smrv_strong; // mask or regs that are likely to have correct values
274 static u_int smrv_weak; // same, but somewhat less likely
275 static u_int smrv_strong_next; // same, but after current insn executes
276 static u_int smrv_weak_next;
e2b5e7aa 277 static uint64_t unneeded_reg[MAXBLOCK];
e2b5e7aa 278 static uint64_t branch_unneeded_reg[MAXBLOCK];
6cc8d23c 279 // see 'struct regstat' for a description
2330734f 280 static signed char regmap_pre[MAXBLOCK][HOST_REGS];
40fca85b 281 // contains 'real' consts at [i] insn, but may differ from what's actually
282 // loaded in host reg as 'final' value is always loaded, see get_final_value()
283 static uint32_t current_constmap[HOST_REGS];
284 static uint32_t constmap[MAXBLOCK][HOST_REGS];
956f3129 285 static struct regstat regs[MAXBLOCK];
286 static struct regstat branch_regs[MAXBLOCK];
e2b5e7aa 287 static int slen;
df4dc2b1 288 static void *instr_addr[MAXBLOCK];
643aeae3 289 static struct link_entry link_addr[MAXBLOCK];
e2b5e7aa 290 static int linkcount;
b14b6a8f 291 static struct code_stub stubs[MAXBLOCK*3];
e2b5e7aa 292 static int stubcount;
293 static u_int literals[1024][2];
294 static int literalcount;
295 static int is_delayslot;
e2b5e7aa 296 static char shadow[1048576] __attribute__((aligned(16)));
297 static void *copy;
93c0345b 298 static u_int expirep;
e2b5e7aa 299 static u_int stop_after_jal;
7f94b097 300 static u_int f1_hack;
ece032e6 301#ifdef STAT_PRINT
302 static int stat_bc_direct;
303 static int stat_bc_pre;
304 static int stat_bc_restore;
104df9d3 305 static int stat_ht_lookups;
ece032e6 306 static int stat_jump_in_lookups;
307 static int stat_restore_tries;
308 static int stat_restore_compares;
309 static int stat_inv_addr_calls;
310 static int stat_inv_hits;
104df9d3 311 static int stat_blocks;
312 static int stat_links;
ece032e6 313 #define stat_inc(s) s++
104df9d3 314 #define stat_dec(s) s--
315 #define stat_clear(s) s = 0
ece032e6 316#else
317 #define stat_inc(s)
104df9d3 318 #define stat_dec(s)
319 #define stat_clear(s)
ece032e6 320#endif
e2b5e7aa 321
322 int new_dynarec_hacks;
d62c125a 323 int new_dynarec_hacks_pergame;
32631e6a 324 int new_dynarec_hacks_old;
e2b5e7aa 325 int new_dynarec_did_compile;
687b4580 326
d62c125a 327 #define HACK_ENABLED(x) ((new_dynarec_hacks | new_dynarec_hacks_pergame) & (x))
328
de6dbc52 329 extern int cycle_count; // ... until end of the timeslice, counts -N -> 0 (CCREG)
687b4580 330 extern int last_count; // last absolute target, often = next_interupt
331 extern int pcaddr;
332 extern int pending_exception;
333 extern int branch_target;
37387d8b 334 extern uintptr_t ram_offset;
d1e4ebd9 335 extern uintptr_t mini_ht[32][2];
57871462 336
337 /* registers that may be allocated */
338 /* 1-31 gpr */
7c3a5182 339#define LOREG 32 // lo
340#define HIREG 33 // hi
00fa9369 341//#define FSREG 34 // FPU status (FCSR)
de6dbc52 342//#define CSREG 35 // Coprocessor status
57871462 343#define CCREG 36 // Cycle count
344#define INVCP 37 // Pointer to invalid_code
1edfcc68 345//#define MMREG 38 // Pointer to memory_map
33a1eda1 346#define ROREG 39 // ram offset (if psxM != 0x80000000)
619e5ded 347#define TEMPREG 40
33a1eda1 348#define FTEMP 40 // Load/store temporary register (was fpu)
619e5ded 349#define PTEMP 41 // Prefetch temporary register
1edfcc68 350//#define TLREG 42 // TLB mapping offset
619e5ded 351#define RHASH 43 // Return address hash
352#define RHTBL 44 // Return address hash table address
353#define RTEMP 45 // JR/JALR address register
354#define MAXREG 45
277718fa 355#define AGEN1 46 // Address generation temporary register (pass5b_preallocate2)
1edfcc68 356//#define AGEN2 47 // Address generation temporary register
57871462 357
358 /* instruction types */
359#define NOP 0 // No operation
360#define LOAD 1 // Load
361#define STORE 2 // Store
362#define LOADLR 3 // Unaligned load
363#define STORELR 4 // Unaligned store
a5cd72d0 364#define MOV 5 // Move (hi/lo only)
57871462 365#define ALU 6 // Arithmetic/logic
366#define MULTDIV 7 // Multiply/divide
367#define SHIFT 8 // Shift by register
368#define SHIFTIMM 9// Shift by immediate
369#define IMM16 10 // 16-bit immediate
370#define RJUMP 11 // Unconditional jump to register
371#define UJUMP 12 // Unconditional jump
372#define CJUMP 13 // Conditional branch (BEQ/BNE/BGTZ/BLEZ)
373#define SJUMP 14 // Conditional branch (regimm format)
374#define COP0 15 // Coprocessor 0
a5cd72d0 375#define RFE 16
d1150cd6 376#define SYSCALL 22// SYSCALL,BREAK
a5cd72d0 377#define OTHER 23 // Other/unknown - do nothing
7139f3c8 378#define HLECALL 26// PCSX fake opcodes for HLE
b9b61529 379#define COP2 27 // Coprocessor 2 move
380#define C2LS 28 // Coprocessor 2 load/store
381#define C2OP 29 // Coprocessor 2 operation
1e973cb0 382#define INTCALL 30// Call interpreter to handle rare corner cases
57871462 383
57871462 384 /* branch codes */
385#define TAKEN 1
386#define NOTTAKEN 2
57871462 387
7c3a5182 388#define DJT_1 (void *)1l // no function, just a label in assem_debug log
389#define DJT_2 (void *)2l
390
57871462 391// asm linkage
57871462 392void dyna_linker();
57871462 393void cc_interrupt();
d1150cd6 394void jump_syscall (u_int u0, u_int u1, u_int pc);
395void jump_syscall_ds(u_int u0, u_int u1, u_int pc);
396void jump_break (u_int u0, u_int u1, u_int pc);
397void jump_break_ds(u_int u0, u_int u1, u_int pc);
a5cd72d0 398void jump_overflow (u_int u0, u_int u1, u_int pc);
399void jump_overflow_ds(u_int u0, u_int u1, u_int pc);
277718fa 400void jump_addrerror (u_int cause, u_int addr, u_int pc);
401void jump_addrerror_ds(u_int cause, u_int addr, u_int pc);
3968e69e 402void jump_to_new_pc();
81dbbf4c 403void call_gteStall();
7139f3c8 404void new_dyna_leave();
57871462 405
104df9d3 406void *ndrc_get_addr_ht_param(u_int vaddr, int can_compile);
407void *ndrc_get_addr_ht(u_int vaddr);
104df9d3 408void ndrc_add_jump_out(u_int vaddr, void *src);
9b495f6e 409void ndrc_write_invalidate_one(u_int addr);
410static void ndrc_write_invalidate_many(u_int addr, u_int end);
104df9d3 411
412static int new_recompile_block(u_int addr);
413static void invalidate_block(struct block_info *block);
a5cd72d0 414static void exception_assemble(int i, const struct regstat *i_regs, int ccadj_);
398d6924 415
57871462 416// Needed by assembler
a22ccd6a 417static void wb_register(signed char r, const signed char regmap[], u_int dirty);
418static void wb_dirtys(const signed char i_regmap[], u_int i_dirty);
419static void wb_needed_dirtys(const signed char i_regmap[], u_int i_dirty, int addr);
2330734f 420static void load_all_regs(const signed char i_regmap[]);
421static void load_needed_regs(const signed char i_regmap[], const signed char next_regmap[]);
e2b5e7aa 422static void load_regs_entry(int t);
2330734f 423static void load_all_consts(const signed char regmap[], u_int dirty, int i);
81dbbf4c 424static u_int get_host_reglist(const signed char *regmap);
e2b5e7aa 425
de6dbc52 426static int get_final_value(int hr, int i, u_int *value);
b14b6a8f 427static void add_stub(enum stub_type type, void *addr, void *retaddr,
428 u_int a, uintptr_t b, uintptr_t c, u_int d, u_int e);
429static void add_stub_r(enum stub_type type, void *addr, void *retaddr,
81dbbf4c 430 int i, int addr_reg, const struct regstat *i_regs, int ccadj, u_int reglist);
643aeae3 431static void add_to_linker(void *addr, u_int target, int ext);
687b4580 432static void *get_direct_memhandler(void *table, u_int addr,
433 enum stub_type type, uintptr_t *addr_host);
32631e6a 434static void cop2_do_stall_check(u_int op, int i, const struct regstat *i_regs, u_int reglist);
687b4580 435static void pass_args(int a0, int a1);
2a014d73 436static void emit_far_jump(const void *f);
437static void emit_far_call(const void *f);
57871462 438
9c67c98f 439#ifdef VITA
440#include <psp2/kernel/sysmem.h>
441static int sceBlock;
442// note: this interacts with RetroArch's Vita bootstrap code: bootstrap/vita/sbrk.c
443extern int getVMBlock();
444int _newlib_vm_size_user = sizeof(*ndrc);
445#endif
446
d148d265 447static void mprotect_w_x(void *start, void *end, int is_x)
448{
449#ifdef NO_WRITE_EXEC
1e212a25 450 #if defined(VITA)
451 // *Open* enables write on all memory that was
452 // allocated by sceKernelAllocMemBlockForVM()?
453 if (is_x)
454 sceKernelCloseVMDomain();
455 else
456 sceKernelOpenVMDomain();
3039c914 457 #elif defined(HAVE_LIBNX)
458 Result rc;
d9e2b173 459 // check to avoid the full flush in jitTransitionToExecutable()
460 if (g_jit.type != JitType_CodeMemory) {
461 if (is_x)
462 rc = jitTransitionToExecutable(&g_jit);
463 else
464 rc = jitTransitionToWritable(&g_jit);
465 if (R_FAILED(rc))
466 ;//SysPrintf("jitTransition %d %08x\n", is_x, rc);
467 }
468 #elif defined(TC_WRITE_OFFSET)
3039c914 469 // separated rx and rw areas are always available
1e212a25 470 #else
d148d265 471 u_long mstart = (u_long)start & ~4095ul;
472 u_long mend = (u_long)end;
473 if (mprotect((void *)mstart, mend - mstart,
474 PROT_READ | (is_x ? PROT_EXEC : PROT_WRITE)) != 0)
475 SysPrintf("mprotect(%c) failed: %s\n", is_x ? 'x' : 'w', strerror(errno));
1e212a25 476 #endif
d148d265 477#endif
478}
479
d9e2b173 480static void start_tcache_write(void *start, void *end)
d148d265 481{
482 mprotect_w_x(start, end, 0);
483}
484
485static void end_tcache_write(void *start, void *end)
486{
919981d0 487#if defined(__arm__) || defined(__aarch64__)
d148d265 488 size_t len = (char *)end - (char *)start;
489 #if defined(__BLACKBERRY_QNX__)
490 msync(start, len, MS_SYNC | MS_CACHE_ONLY | MS_INVALIDATE_ICACHE);
491 #elif defined(__MACH__)
492 sys_cache_control(kCacheFunctionPrepareForExecution, start, len);
493 #elif defined(VITA)
1e212a25 494 sceKernelSyncVMDomain(sceBlock, start, len);
495 #elif defined(_3DS)
496 ctr_flush_invalidate_cache();
3039c914 497 #elif defined(HAVE_LIBNX)
d9e2b173 498 if (g_jit.type == JitType_CodeMemory) {
499 armDCacheClean(start, len);
500 armICacheInvalidate((char *)start - ndrc_write_ofs, len);
aaece508 501 // as of v4.2.1 libnx lacks isb
502 __asm__ volatile("isb" ::: "memory");
d9e2b173 503 }
919981d0 504 #elif defined(__aarch64__)
505 // as of 2021, __clear_cache() is still broken on arm64
506 // so here is a custom one :(
507 clear_cache_arm64(start, end);
d148d265 508 #else
509 __clear_cache(start, end);
510 #endif
511 (void)len;
512#endif
513
514 mprotect_w_x(start, end, 1);
515}
516
517static void *start_block(void)
518{
519 u_char *end = out + MAX_OUTPUT_BLOCK_SIZE;
2a014d73 520 if (end > ndrc->translation_cache + sizeof(ndrc->translation_cache))
521 end = ndrc->translation_cache + sizeof(ndrc->translation_cache);
d9e2b173 522 start_tcache_write(NDRC_WRITE_OFFSET(out), NDRC_WRITE_OFFSET(end));
d148d265 523 return out;
524}
525
526static void end_block(void *start)
527{
d9e2b173 528 end_tcache_write(NDRC_WRITE_OFFSET(start), NDRC_WRITE_OFFSET(out));
d148d265 529}
530
af700b41 531#ifdef NDRC_CACHE_FLUSH_ALL
532
533static int needs_clear_cache;
534
535static void mark_clear_cache(void *target)
536{
537 if (!needs_clear_cache) {
d9e2b173 538 start_tcache_write(NDRC_WRITE_OFFSET(ndrc), NDRC_WRITE_OFFSET(ndrc + 1));
af700b41 539 needs_clear_cache = 1;
540 }
541}
542
543static void do_clear_cache(void)
544{
545 if (needs_clear_cache) {
d9e2b173 546 end_tcache_write(NDRC_WRITE_OFFSET(ndrc), NDRC_WRITE_OFFSET(ndrc + 1));
af700b41 547 needs_clear_cache = 0;
548 }
549}
550
551#else
552
919981d0 553// also takes care of w^x mappings when patching code
554static u_int needs_clear_cache[1<<(TARGET_SIZE_2-17)];
555
556static void mark_clear_cache(void *target)
557{
558 uintptr_t offset = (u_char *)target - ndrc->translation_cache;
559 u_int mask = 1u << ((offset >> 12) & 31);
560 if (!(needs_clear_cache[offset >> 17] & mask)) {
d9e2b173 561 char *start = (char *)NDRC_WRITE_OFFSET((uintptr_t)target & ~4095l);
919981d0 562 start_tcache_write(start, start + 4095);
563 needs_clear_cache[offset >> 17] |= mask;
564 }
565}
566
567// Clearing the cache is rather slow on ARM Linux, so mark the areas
568// that need to be cleared, and then only clear these areas once.
569static void do_clear_cache(void)
570{
571 int i, j;
572 for (i = 0; i < (1<<(TARGET_SIZE_2-17)); i++)
573 {
574 u_int bitmap = needs_clear_cache[i];
575 if (!bitmap)
576 continue;
577 for (j = 0; j < 32; j++)
578 {
579 u_char *start, *end;
93c0345b 580 if (!(bitmap & (1u << j)))
919981d0 581 continue;
582
583 start = ndrc->translation_cache + i*131072 + j*4096;
584 end = start + 4095;
585 for (j++; j < 32; j++) {
93c0345b 586 if (!(bitmap & (1u << j)))
919981d0 587 break;
588 end += 4096;
589 }
d9e2b173 590 end_tcache_write(NDRC_WRITE_OFFSET(start), NDRC_WRITE_OFFSET(end));
919981d0 591 }
592 needs_clear_cache[i] = 0;
593 }
594}
595
af700b41 596#endif // NDRC_CACHE_FLUSH_ALL
57871462 597
b6e87b2b 598#define NO_CYCLE_PENALTY_THR 12
599
32631e6a 600int cycle_multiplier_old;
24058131 601static int cycle_multiplier_active;
4e9dcd7f 602
603static int CLOCK_ADJUST(int x)
604{
24058131 605 int m = cycle_multiplier_active;
606 int s = (x >> 31) | 1;
a3203cf4 607 return (x * m + s * 50) / 100;
4e9dcd7f 608}
609
4919de1e 610static int ds_writes_rjump_rs(int i)
611{
ecca05e3 612 return dops[i].rs1 != 0
613 && (dops[i].rs1 == dops[i+1].rt1 || dops[i].rs1 == dops[i+1].rt2
614 || dops[i].rs1 == dops[i].rt1); // overwrites itself - same effect
4919de1e 615}
616
104df9d3 617// psx addr mirror masking (for invalidation)
618static u_int pmmask(u_int vaddr)
619{
620 vaddr &= ~0xe0000000;
621 if (vaddr < 0x01000000)
622 vaddr &= ~0x00e00000; // RAM mirrors
623 return vaddr;
624}
625
94d23bb9 626static u_int get_page(u_int vaddr)
57871462 627{
104df9d3 628 u_int page = pmmask(vaddr) >> 12;
93c0345b 629 if (page >= PAGE_COUNT / 2)
630 page = PAGE_COUNT / 2 + (page & (PAGE_COUNT / 2 - 1));
94d23bb9 631 return page;
632}
633
104df9d3 634// get a page for looking for a block that has vaddr
635// (needed because the block may start in previous page)
636static u_int get_page_prev(u_int vaddr)
d25604ca 637{
104df9d3 638 assert(MAXBLOCK <= (1 << 12));
639 u_int page = get_page(vaddr);
640 if (page & 511)
641 page--;
642 return page;
d25604ca 643}
94d23bb9 644
df4dc2b1 645static struct ht_entry *hash_table_get(u_int vaddr)
646{
647 return &hash_table[((vaddr>>16)^vaddr)&0xFFFF];
648}
649
104df9d3 650static void hash_table_add(u_int vaddr, void *tcaddr)
df4dc2b1 651{
104df9d3 652 struct ht_entry *ht_bin = hash_table_get(vaddr);
653 assert(tcaddr);
df4dc2b1 654 ht_bin->vaddr[1] = ht_bin->vaddr[0];
655 ht_bin->tcaddr[1] = ht_bin->tcaddr[0];
656 ht_bin->vaddr[0] = vaddr;
657 ht_bin->tcaddr[0] = tcaddr;
658}
659
104df9d3 660static void hash_table_remove(int vaddr)
661{
662 //printf("remove hash: %x\n",vaddr);
663 struct ht_entry *ht_bin = hash_table_get(vaddr);
664 if (ht_bin->vaddr[1] == vaddr) {
665 ht_bin->vaddr[1] = -1;
666 ht_bin->tcaddr[1] = NULL;
667 }
668 if (ht_bin->vaddr[0] == vaddr) {
669 ht_bin->vaddr[0] = ht_bin->vaddr[1];
670 ht_bin->tcaddr[0] = ht_bin->tcaddr[1];
671 ht_bin->vaddr[1] = -1;
672 ht_bin->tcaddr[1] = NULL;
673 }
674}
675
676static void mark_invalid_code(u_int vaddr, u_int len, char invalid)
398d6924 677{
ab4377be 678 u_int vaddr_m = vaddr & 0x1fffffff;
398d6924 679 u_int i, j;
ab4377be 680 for (i = vaddr_m & ~0xfff; i < vaddr_m + len; i += 0x1000) {
398d6924 681 // ram mirrors, but should not hurt bios
682 for (j = 0; j < 0x800000; j += 0x200000) {
683 invalid_code[(i|j) >> 12] =
684 invalid_code[(i|j|0x80000000u) >> 12] =
104df9d3 685 invalid_code[(i|j|0xa0000000u) >> 12] = invalid;
398d6924 686 }
687 }
882a08fc 688 if (!invalid && vaddr + len > inv_code_start && vaddr <= inv_code_end)
104df9d3 689 inv_code_start = inv_code_end = ~0;
398d6924 690}
691
93c0345b 692static int doesnt_expire_soon(u_char *tcaddr)
df4dc2b1 693{
93c0345b 694 u_int diff = (u_int)(tcaddr - out) & ((1u << TARGET_SIZE_2) - 1u);
695 return diff > EXPIRITY_OFFSET + MAX_OUTPUT_BLOCK_SIZE;
df4dc2b1 696}
697
9b495f6e 698static unused void check_for_block_changes(u_int start, u_int end)
699{
700 u_int start_page = get_page_prev(start);
701 u_int end_page = get_page(end - 1);
702 u_int page;
703
704 for (page = start_page; page <= end_page; page++) {
705 struct block_info *block;
706 for (block = blocks[page]; block != NULL; block = block->next) {
707 if (block->is_dirty)
708 continue;
709 if (memcmp(block->source, block->copy, block->len)) {
710 printf("bad block %08x-%08x %016llx %016llx @%08x\n",
711 block->start, block->start + block->len,
712 *(long long *)block->source, *(long long *)block->copy, psxRegs.pc);
713 fflush(stdout);
714 abort();
715 }
716 }
717 }
718}
719
104df9d3 720static void *try_restore_block(u_int vaddr, u_int start_page, u_int end_page)
398d6924 721{
104df9d3 722 void *found_clean = NULL;
723 u_int i, page;
398d6924 724
ece032e6 725 stat_inc(stat_restore_tries);
104df9d3 726 for (page = start_page; page <= end_page; page++) {
727 struct block_info *block;
728 for (block = blocks[page]; block != NULL; block = block->next) {
729 if (vaddr < block->start)
730 break;
731 if (!block->is_dirty || vaddr >= block->start + block->len)
732 continue;
733 for (i = 0; i < block->jump_in_cnt; i++)
734 if (block->jump_in[i].vaddr == vaddr)
735 break;
736 if (i == block->jump_in_cnt)
737 continue;
738 assert(block->source && block->copy);
739 stat_inc(stat_restore_compares);
740 if (memcmp(block->source, block->copy, block->len))
741 continue;
398d6924 742
3280e616 743 block->is_dirty = block->inv_near_misses = 0;
104df9d3 744 found_clean = block->jump_in[i].addr;
745 hash_table_add(vaddr, found_clean);
746 mark_invalid_code(block->start, block->len, 0);
747 stat_inc(stat_bc_restore);
748 inv_debug("INV: restored %08x %p (%d)\n", vaddr, found_clean, block->jump_in_cnt);
749 return found_clean;
398d6924 750 }
398d6924 751 }
104df9d3 752 return NULL;
398d6924 753}
754
de6dbc52 755// this doesn't normally happen
756static noinline u_int generate_exception(u_int pc)
757{
758 //if (execBreakCheck(&psxRegs, pc))
759 // return psxRegs.pc;
760
761 // generate an address or bus error
762 psxRegs.CP0.n.Cause &= 0x300;
763 psxRegs.CP0.n.EPC = pc;
764 if (pc & 3) {
765 psxRegs.CP0.n.Cause |= R3000E_AdEL << 2;
766 psxRegs.CP0.n.BadVAddr = pc;
767#ifdef DRC_DBG
768 last_count -= 2;
769#endif
770 } else
771 psxRegs.CP0.n.Cause |= R3000E_IBE << 2;
772 return (psxRegs.pc = 0x80000080);
773}
774
94d23bb9 775// Get address from virtual address
776// This is called from the recompiled JR/JALR instructions
104df9d3 777static void noinline *get_addr(u_int vaddr, int can_compile)
94d23bb9 778{
104df9d3 779 u_int start_page = get_page_prev(vaddr);
780 u_int i, page, end_page = get_page(vaddr);
781 void *found_clean = NULL;
398d6924 782
ece032e6 783 stat_inc(stat_jump_in_lookups);
104df9d3 784 for (page = start_page; page <= end_page; page++) {
785 const struct block_info *block;
786 for (block = blocks[page]; block != NULL; block = block->next) {
787 if (vaddr < block->start)
788 break;
789 if (block->is_dirty || vaddr >= block->start + block->len)
790 continue;
791 for (i = 0; i < block->jump_in_cnt; i++)
792 if (block->jump_in[i].vaddr == vaddr)
793 break;
794 if (i == block->jump_in_cnt)
795 continue;
796 found_clean = block->jump_in[i].addr;
797 hash_table_add(vaddr, found_clean);
798 return found_clean;
57871462 799 }
57871462 800 }
104df9d3 801 found_clean = try_restore_block(vaddr, start_page, end_page);
802 if (found_clean)
803 return found_clean;
804
805 if (!can_compile)
806 return NULL;
398d6924 807
808 int r = new_recompile_block(vaddr);
de6dbc52 809 if (likely(r == 0))
104df9d3 810 return ndrc_get_addr_ht(vaddr);
df4dc2b1 811
de6dbc52 812 return ndrc_get_addr_ht(generate_exception(vaddr));
57871462 813}
104df9d3 814
57871462 815// Look up address in hash table first
104df9d3 816void *ndrc_get_addr_ht_param(u_int vaddr, int can_compile)
57871462 817{
9b495f6e 818 //check_for_block_changes(vaddr, vaddr + MAXBLOCK);
df4dc2b1 819 const struct ht_entry *ht_bin = hash_table_get(vaddr);
277718fa 820 u_int vaddr_a = vaddr & ~3;
104df9d3 821 stat_inc(stat_ht_lookups);
277718fa 822 if (ht_bin->vaddr[0] == vaddr_a) return ht_bin->tcaddr[0];
823 if (ht_bin->vaddr[1] == vaddr_a) return ht_bin->tcaddr[1];
104df9d3 824 return get_addr(vaddr, can_compile);
825}
826
827void *ndrc_get_addr_ht(u_int vaddr)
828{
829 return ndrc_get_addr_ht_param(vaddr, 1);
57871462 830}
831
6cc8d23c 832static void clear_all_regs(signed char regmap[])
57871462 833{
6cc8d23c 834 memset(regmap, -1, sizeof(regmap[0]) * HOST_REGS);
57871462 835}
836
53358c1d 837// get_reg: get allocated host reg from mips reg
838// returns -1 if no such mips reg was allocated
cdc2da64 839#if defined(__arm__) && defined(HAVE_ARMV6) && HOST_REGS == 13 && EXCLUDE_REG == 11
840
841extern signed char get_reg(const signed char regmap[], signed char r);
842
843#else
844
9de8a0c3 845static signed char get_reg(const signed char regmap[], signed char r)
57871462 846{
847 int hr;
9de8a0c3 848 for (hr = 0; hr < HOST_REGS; hr++) {
849 if (hr == EXCLUDE_REG)
850 continue;
851 if (regmap[hr] == r)
852 return hr;
853 }
854 return -1;
855}
856
cdc2da64 857#endif
858
a5cd72d0 859// get reg suitable for writing
860static signed char get_reg_w(const signed char regmap[], signed char r)
861{
862 return r == 0 ? -1 : get_reg(regmap, r);
863}
864
53358c1d 865// get reg as mask bit (1 << hr)
866static u_int get_regm(const signed char regmap[], signed char r)
867{
868 return (1u << (get_reg(regmap, r) & 31)) & ~(1u << 31);
869}
870
9de8a0c3 871static signed char get_reg_temp(const signed char regmap[])
872{
873 int hr;
874 for (hr = 0; hr < HOST_REGS; hr++) {
875 if (hr == EXCLUDE_REG)
876 continue;
877 if (regmap[hr] == (signed char)-1)
878 return hr;
879 }
57871462 880 return -1;
881}
882
883// Find a register that is available for two consecutive cycles
d1e4ebd9 884static signed char get_reg2(signed char regmap1[], const signed char regmap2[], int r)
57871462 885{
886 int hr;
887 for (hr=0;hr<HOST_REGS;hr++) if(hr!=EXCLUDE_REG&&regmap1[hr]==r&&regmap2[hr]==r) return hr;
888 return -1;
889}
890
53dc27f6 891// reverse reg map: mips -> host
892#define RRMAP_SIZE 64
893static void make_rregs(const signed char regmap[], signed char rrmap[RRMAP_SIZE],
894 u_int *regs_can_change)
895{
896 u_int r, hr, hr_can_change = 0;
897 memset(rrmap, -1, RRMAP_SIZE);
898 for (hr = 0; hr < HOST_REGS; )
899 {
900 r = regmap[hr];
901 rrmap[r & (RRMAP_SIZE - 1)] = hr;
902 // only add mips $1-$31+$lo, others shifted out
903 hr_can_change |= (uint64_t)1 << (hr + ((r - 1) & 32));
904 hr++;
905 if (hr == EXCLUDE_REG)
906 hr++;
907 }
908 hr_can_change |= 1u << (rrmap[33] & 31);
909 hr_can_change |= 1u << (rrmap[CCREG] & 31);
910 hr_can_change &= ~(1u << 31);
911 *regs_can_change = hr_can_change;
912}
913
914// same as get_reg, but takes rrmap
915static signed char get_rreg(signed char rrmap[RRMAP_SIZE], signed char r)
916{
917 assert(0 <= r && r < RRMAP_SIZE);
918 return rrmap[r];
919}
920
9de8a0c3 921static int count_free_regs(const signed char regmap[])
57871462 922{
923 int count=0;
924 int hr;
925 for(hr=0;hr<HOST_REGS;hr++)
926 {
927 if(hr!=EXCLUDE_REG) {
928 if(regmap[hr]<0) count++;
929 }
930 }
931 return count;
932}
933
9de8a0c3 934static void dirty_reg(struct regstat *cur, signed char reg)
57871462 935{
936 int hr;
9de8a0c3 937 if (!reg) return;
938 hr = get_reg(cur->regmap, reg);
939 if (hr >= 0)
940 cur->dirty |= 1<<hr;
57871462 941}
942
40fca85b 943static void set_const(struct regstat *cur, signed char reg, uint32_t value)
57871462 944{
945 int hr;
9de8a0c3 946 if (!reg) return;
947 hr = get_reg(cur->regmap, reg);
948 if (hr >= 0) {
949 cur->isconst |= 1<<hr;
950 current_constmap[hr] = value;
57871462 951 }
952}
953
40fca85b 954static void clear_const(struct regstat *cur, signed char reg)
57871462 955{
956 int hr;
9de8a0c3 957 if (!reg) return;
958 hr = get_reg(cur->regmap, reg);
959 if (hr >= 0)
960 cur->isconst &= ~(1<<hr);
57871462 961}
962
9de8a0c3 963static int is_const(const struct regstat *cur, signed char reg)
57871462 964{
965 int hr;
9de8a0c3 966 if (reg < 0) return 0;
967 if (!reg) return 1;
968 hr = get_reg(cur->regmap, reg);
969 if (hr >= 0)
970 return (cur->isconst>>hr)&1;
57871462 971 return 0;
972}
40fca85b 973
9de8a0c3 974static uint32_t get_const(const struct regstat *cur, signed char reg)
57871462 975{
976 int hr;
9de8a0c3 977 if (!reg) return 0;
978 hr = get_reg(cur->regmap, reg);
979 if (hr >= 0)
980 return current_constmap[hr];
981
982 SysPrintf("Unknown constant in r%d\n", reg);
7c3a5182 983 abort();
57871462 984}
985
986// Least soon needed registers
987// Look at the next ten instructions and see which registers
988// will be used. Try not to reallocate these.
90f98e7c 989static void lsn(u_char hsn[], int i)
57871462 990{
991 int j;
992 int b=-1;
993 for(j=0;j<9;j++)
994 {
995 if(i+j>=slen) {
996 j=slen-i-1;
997 break;
998 }
fe807a8a 999 if (dops[i+j].is_ujump)
57871462 1000 {
1001 // Don't go past an unconditonal jump
1002 j++;
1003 break;
1004 }
1005 }
1006 for(;j>=0;j--)
1007 {
cf95b4f0 1008 if(dops[i+j].rs1) hsn[dops[i+j].rs1]=j;
1009 if(dops[i+j].rs2) hsn[dops[i+j].rs2]=j;
1010 if(dops[i+j].rt1) hsn[dops[i+j].rt1]=j;
1011 if(dops[i+j].rt2) hsn[dops[i+j].rt2]=j;
1012 if(dops[i+j].itype==STORE || dops[i+j].itype==STORELR) {
57871462 1013 // Stores can allocate zero
cf95b4f0 1014 hsn[dops[i+j].rs1]=j;
1015 hsn[dops[i+j].rs2]=j;
57871462 1016 }
37387d8b 1017 if (ram_offset && (dops[i+j].is_load || dops[i+j].is_store))
1018 hsn[ROREG] = j;
57871462 1019 // On some architectures stores need invc_ptr
1020 #if defined(HOST_IMM8)
37387d8b 1021 if (dops[i+j].is_store)
1022 hsn[INVCP] = j;
57871462 1023 #endif
cf95b4f0 1024 if(i+j>=0&&(dops[i+j].itype==UJUMP||dops[i+j].itype==CJUMP||dops[i+j].itype==SJUMP))
57871462 1025 {
1026 hsn[CCREG]=j;
1027 b=j;
1028 }
1029 }
1030 if(b>=0)
1031 {
277718fa 1032 if(cinfo[i+b].ba>=start && cinfo[i+b].ba<(start+slen*4))
57871462 1033 {
1034 // Follow first branch
277718fa 1035 int t=(cinfo[i+b].ba-start)>>2;
57871462 1036 j=7-b;if(t+j>=slen) j=slen-t-1;
1037 for(;j>=0;j--)
1038 {
cf95b4f0 1039 if(dops[t+j].rs1) if(hsn[dops[t+j].rs1]>j+b+2) hsn[dops[t+j].rs1]=j+b+2;
1040 if(dops[t+j].rs2) if(hsn[dops[t+j].rs2]>j+b+2) hsn[dops[t+j].rs2]=j+b+2;
1041 //if(dops[t+j].rt1) if(hsn[dops[t+j].rt1]>j+b+2) hsn[dops[t+j].rt1]=j+b+2;
1042 //if(dops[t+j].rt2) if(hsn[dops[t+j].rt2]>j+b+2) hsn[dops[t+j].rt2]=j+b+2;
57871462 1043 }
1044 }
1045 // TODO: preferred register based on backward branch
1046 }
1047 // Delay slot should preferably not overwrite branch conditions or cycle count
fe807a8a 1048 if (i > 0 && dops[i-1].is_jump) {
cf95b4f0 1049 if(dops[i-1].rs1) if(hsn[dops[i-1].rs1]>1) hsn[dops[i-1].rs1]=1;
1050 if(dops[i-1].rs2) if(hsn[dops[i-1].rs2]>1) hsn[dops[i-1].rs2]=1;
57871462 1051 hsn[CCREG]=1;
1052 // ...or hash tables
1053 hsn[RHASH]=1;
1054 hsn[RHTBL]=1;
1055 }
1056 // Coprocessor load/store needs FTEMP, even if not declared
37387d8b 1057 if(dops[i].itype==C2LS) {
57871462 1058 hsn[FTEMP]=0;
1059 }
33a1eda1 1060 // Load/store L/R also uses FTEMP as a temporary register
1061 if (dops[i].itype == LOADLR || dops[i].itype == STORELR) {
57871462 1062 hsn[FTEMP]=0;
1063 }
57871462 1064 // Don't remove the miniht registers
cf95b4f0 1065 if(dops[i].itype==UJUMP||dops[i].itype==RJUMP)
57871462 1066 {
1067 hsn[RHASH]=0;
1068 hsn[RHTBL]=0;
1069 }
1070}
1071
1072// We only want to allocate registers if we're going to use them again soon
4149788d 1073static int needed_again(int r, int i)
57871462 1074{
1075 int j;
1076 int b=-1;
1077 int rn=10;
9f51b4b9 1078
fe807a8a 1079 if (i > 0 && dops[i-1].is_ujump)
57871462 1080 {
277718fa 1081 if(cinfo[i-1].ba<start || cinfo[i-1].ba>start+slen*4-4)
57871462 1082 return 0; // Don't need any registers if exiting the block
1083 }
1084 for(j=0;j<9;j++)
1085 {
1086 if(i+j>=slen) {
1087 j=slen-i-1;
1088 break;
1089 }
fe807a8a 1090 if (dops[i+j].is_ujump)
57871462 1091 {
1092 // Don't go past an unconditonal jump
1093 j++;
1094 break;
1095 }
a5cd72d0 1096 if (dops[i+j].is_exception)
57871462 1097 {
1098 break;
1099 }
1100 }
1101 for(;j>=1;j--)
1102 {
cf95b4f0 1103 if(dops[i+j].rs1==r) rn=j;
1104 if(dops[i+j].rs2==r) rn=j;
57871462 1105 if((unneeded_reg[i+j]>>r)&1) rn=10;
cf95b4f0 1106 if(i+j>=0&&(dops[i+j].itype==UJUMP||dops[i+j].itype==CJUMP||dops[i+j].itype==SJUMP))
57871462 1107 {
1108 b=j;
1109 }
1110 }
b7217e13 1111 if(rn<10) return 1;
581335b0 1112 (void)b;
57871462 1113 return 0;
1114}
1115
1116// Try to match register allocations at the end of a loop with those
1117// at the beginning
4149788d 1118static int loop_reg(int i, int r, int hr)
57871462 1119{
1120 int j,k;
1121 for(j=0;j<9;j++)
1122 {
1123 if(i+j>=slen) {
1124 j=slen-i-1;
1125 break;
1126 }
fe807a8a 1127 if (dops[i+j].is_ujump)
57871462 1128 {
1129 // Don't go past an unconditonal jump
1130 j++;
1131 break;
1132 }
1133 }
1134 k=0;
1135 if(i>0){
cf95b4f0 1136 if(dops[i-1].itype==UJUMP||dops[i-1].itype==CJUMP||dops[i-1].itype==SJUMP)
57871462 1137 k--;
1138 }
1139 for(;k<j;k++)
1140 {
00fa9369 1141 assert(r < 64);
1142 if((unneeded_reg[i+k]>>r)&1) return hr;
cf95b4f0 1143 if(i+k>=0&&(dops[i+k].itype==UJUMP||dops[i+k].itype==CJUMP||dops[i+k].itype==SJUMP))
57871462 1144 {
277718fa 1145 if(cinfo[i+k].ba>=start && cinfo[i+k].ba<(start+i*4))
57871462 1146 {
277718fa 1147 int t=(cinfo[i+k].ba-start)>>2;
57871462 1148 int reg=get_reg(regs[t].regmap_entry,r);
1149 if(reg>=0) return reg;
1150 //reg=get_reg(regs[t+1].regmap_entry,r);
1151 //if(reg>=0) return reg;
1152 }
1153 }
1154 }
1155 return hr;
1156}
1157
1158
1159// Allocate every register, preserving source/target regs
4149788d 1160static void alloc_all(struct regstat *cur,int i)
57871462 1161{
1162 int hr;
9f51b4b9 1163
57871462 1164 for(hr=0;hr<HOST_REGS;hr++) {
1165 if(hr!=EXCLUDE_REG) {
9de8a0c3 1166 if((cur->regmap[hr]!=dops[i].rs1)&&(cur->regmap[hr]!=dops[i].rs2)&&
1167 (cur->regmap[hr]!=dops[i].rt1)&&(cur->regmap[hr]!=dops[i].rt2))
57871462 1168 {
1169 cur->regmap[hr]=-1;
1170 cur->dirty&=~(1<<hr);
1171 }
1172 // Don't need zeros
9de8a0c3 1173 if(cur->regmap[hr]==0)
57871462 1174 {
1175 cur->regmap[hr]=-1;
1176 cur->dirty&=~(1<<hr);
1177 }
1178 }
1179 }
1180}
1181
d1e4ebd9 1182#ifndef NDEBUG
1183static int host_tempreg_in_use;
1184
1185static void host_tempreg_acquire(void)
1186{
1187 assert(!host_tempreg_in_use);
1188 host_tempreg_in_use = 1;
1189}
1190
1191static void host_tempreg_release(void)
1192{
1193 host_tempreg_in_use = 0;
1194}
1195#else
1196static void host_tempreg_acquire(void) {}
1197static void host_tempreg_release(void) {}
1198#endif
1199
32631e6a 1200#ifdef ASSEM_PRINT
8062d65a 1201extern void gen_interupt();
1202extern void do_insn_cmp();
d1e4ebd9 1203#define FUNCNAME(f) { f, " " #f }
8062d65a 1204static const struct {
d1e4ebd9 1205 void *addr;
8062d65a 1206 const char *name;
1207} function_names[] = {
1208 FUNCNAME(cc_interrupt),
1209 FUNCNAME(gen_interupt),
104df9d3 1210 FUNCNAME(ndrc_get_addr_ht),
8062d65a 1211 FUNCNAME(jump_handler_read8),
1212 FUNCNAME(jump_handler_read16),
1213 FUNCNAME(jump_handler_read32),
1214 FUNCNAME(jump_handler_write8),
1215 FUNCNAME(jump_handler_write16),
1216 FUNCNAME(jump_handler_write32),
9b495f6e 1217 FUNCNAME(ndrc_write_invalidate_one),
1218 FUNCNAME(ndrc_write_invalidate_many),
3968e69e 1219 FUNCNAME(jump_to_new_pc),
d1150cd6 1220 FUNCNAME(jump_break),
1221 FUNCNAME(jump_break_ds),
1222 FUNCNAME(jump_syscall),
1223 FUNCNAME(jump_syscall_ds),
a5cd72d0 1224 FUNCNAME(jump_overflow),
1225 FUNCNAME(jump_overflow_ds),
277718fa 1226 FUNCNAME(jump_addrerror),
1227 FUNCNAME(jump_addrerror_ds),
81dbbf4c 1228 FUNCNAME(call_gteStall),
8062d65a 1229 FUNCNAME(new_dyna_leave),
1230 FUNCNAME(pcsx_mtc0),
1231 FUNCNAME(pcsx_mtc0_ds),
277718fa 1232 FUNCNAME(execI),
1233#ifdef __aarch64__
1234 FUNCNAME(do_memhandler_pre),
1235 FUNCNAME(do_memhandler_post),
1236#endif
32631e6a 1237#ifdef DRC_DBG
33a1eda1 1238# ifdef __aarch64__
1239 FUNCNAME(do_insn_cmp_arm64),
1240# else
8062d65a 1241 FUNCNAME(do_insn_cmp),
33a1eda1 1242# endif
32631e6a 1243#endif
8062d65a 1244};
1245
d1e4ebd9 1246static const char *func_name(const void *a)
8062d65a 1247{
1248 int i;
1249 for (i = 0; i < sizeof(function_names)/sizeof(function_names[0]); i++)
1250 if (function_names[i].addr == a)
1251 return function_names[i].name;
1252 return "";
1253}
a5cd72d0 1254
1255static const char *fpofs_name(u_int ofs)
1256{
1257 u_int *p = (u_int *)&dynarec_local + ofs/sizeof(u_int);
1258 static char buf[64];
1259 switch (ofs) {
1260 #define ofscase(x) case LO_##x: return " ; " #x
1261 ofscase(next_interupt);
de6dbc52 1262 ofscase(cycle_count);
a5cd72d0 1263 ofscase(last_count);
1264 ofscase(pending_exception);
1265 ofscase(stop);
1266 ofscase(address);
1267 ofscase(lo);
1268 ofscase(hi);
1269 ofscase(PC);
1270 ofscase(cycle);
1271 ofscase(mem_rtab);
1272 ofscase(mem_wtab);
1273 ofscase(psxH_ptr);
1274 ofscase(invc_ptr);
1275 ofscase(ram_offset);
1276 #undef ofscase
1277 }
1278 buf[0] = 0;
1279 if (psxRegs.GPR.r <= p && p < &psxRegs.GPR.r[32])
1280 snprintf(buf, sizeof(buf), " ; r%d", (int)(p - psxRegs.GPR.r));
1281 else if (psxRegs.CP0.r <= p && p < &psxRegs.CP0.r[32])
1282 snprintf(buf, sizeof(buf), " ; cp0 $%d", (int)(p - psxRegs.CP0.r));
1283 else if (psxRegs.CP2D.r <= p && p < &psxRegs.CP2D.r[32])
1284 snprintf(buf, sizeof(buf), " ; cp2d $%d", (int)(p - psxRegs.CP2D.r));
1285 else if (psxRegs.CP2C.r <= p && p < &psxRegs.CP2C.r[32])
1286 snprintf(buf, sizeof(buf), " ; cp2c $%d", (int)(p - psxRegs.CP2C.r));
1287 return buf;
1288}
8062d65a 1289#else
1290#define func_name(x) ""
a5cd72d0 1291#define fpofs_name(x) ""
8062d65a 1292#endif
1293
57871462 1294#ifdef __i386__
1295#include "assem_x86.c"
1296#endif
1297#ifdef __x86_64__
1298#include "assem_x64.c"
1299#endif
1300#ifdef __arm__
1301#include "assem_arm.c"
1302#endif
be516ebe 1303#ifdef __aarch64__
1304#include "assem_arm64.c"
1305#endif
57871462 1306
2a014d73 1307static void *get_trampoline(const void *f)
1308{
d9e2b173 1309 struct ndrc_tramp *tramp = NDRC_WRITE_OFFSET(&ndrc->tramp);
2a014d73 1310 size_t i;
1311
d9e2b173 1312 for (i = 0; i < ARRAY_SIZE(tramp->f); i++) {
1313 if (tramp->f[i] == f || tramp->f[i] == NULL)
2a014d73 1314 break;
1315 }
d9e2b173 1316 if (i == ARRAY_SIZE(tramp->f)) {
2a014d73 1317 SysPrintf("trampoline table is full, last func %p\n", f);
1318 abort();
1319 }
d9e2b173 1320 if (tramp->f[i] == NULL) {
1321 start_tcache_write(&tramp->f[i], &tramp->f[i + 1]);
1322 tramp->f[i] = f;
1323 end_tcache_write(&tramp->f[i], &tramp->f[i + 1]);
1324#ifdef HAVE_LIBNX
1325 // invalidate the RX mirror (unsure if necessary, but just in case...)
1326 armDCacheFlush(&ndrc->tramp.f[i], sizeof(ndrc->tramp.f[i]));
1327#endif
2a014d73 1328 }
1329 return &ndrc->tramp.ops[i];
1330}
1331
1332static void emit_far_jump(const void *f)
1333{
1334 if (can_jump_or_call(f)) {
1335 emit_jmp(f);
1336 return;
1337 }
1338
1339 f = get_trampoline(f);
1340 emit_jmp(f);
1341}
1342
1343static void emit_far_call(const void *f)
1344{
1345 if (can_jump_or_call(f)) {
1346 emit_call(f);
1347 return;
1348 }
1349
1350 f = get_trampoline(f);
1351 emit_call(f);
1352}
1353
57871462 1354// Check if an address is already compiled
1355// but don't return addresses which are about to expire from the cache
4149788d 1356static void *check_addr(u_int vaddr)
57871462 1357{
df4dc2b1 1358 struct ht_entry *ht_bin = hash_table_get(vaddr);
1359 size_t i;
b14b6a8f 1360 for (i = 0; i < ARRAY_SIZE(ht_bin->vaddr); i++) {
df4dc2b1 1361 if (ht_bin->vaddr[i] == vaddr)
93c0345b 1362 if (doesnt_expire_soon(ht_bin->tcaddr[i]))
104df9d3 1363 return ht_bin->tcaddr[i];
57871462 1364 }
104df9d3 1365
1366 // refactor to get_addr_nocompile?
1367 u_int start_page = get_page_prev(vaddr);
1368 u_int page, end_page = get_page(vaddr);
1369
1370 stat_inc(stat_jump_in_lookups);
1371 for (page = start_page; page <= end_page; page++) {
1372 const struct block_info *block;
1373 for (block = blocks[page]; block != NULL; block = block->next) {
1374 if (vaddr < block->start)
1375 break;
1376 if (block->is_dirty || vaddr >= block->start + block->len)
1377 continue;
1378 if (!doesnt_expire_soon(ndrc->translation_cache + block->tc_offs))
1379 continue;
1380 for (i = 0; i < block->jump_in_cnt; i++)
1381 if (block->jump_in[i].vaddr == vaddr)
1382 break;
1383 if (i == block->jump_in_cnt)
1384 continue;
1385
1386 // Update existing entry with current address
1387 void *addr = block->jump_in[i].addr;
1388 if (ht_bin->vaddr[0] == vaddr) {
1389 ht_bin->tcaddr[0] = addr;
1390 return addr;
1391 }
1392 if (ht_bin->vaddr[1] == vaddr) {
1393 ht_bin->tcaddr[1] = addr;
1394 return addr;
1395 }
1396 // Insert into hash table with low priority.
1397 // Don't evict existing entries, as they are probably
1398 // addresses that are being accessed frequently.
1399 if (ht_bin->vaddr[0] == -1) {
1400 ht_bin->vaddr[0] = vaddr;
1401 ht_bin->tcaddr[0] = addr;
57871462 1402 }
104df9d3 1403 else if (ht_bin->vaddr[1] == -1) {
1404 ht_bin->vaddr[1] = vaddr;
1405 ht_bin->tcaddr[1] = addr;
1406 }
1407 return addr;
57871462 1408 }
57871462 1409 }
104df9d3 1410 return NULL;
57871462 1411}
1412
104df9d3 1413static void blocks_clear(struct block_info **head)
1414{
1415 struct block_info *cur, *next;
1416
1417 if ((cur = *head)) {
1418 *head = NULL;
1419 while (cur) {
1420 next = cur->next;
1421 free(cur);
1422 cur = next;
1423 }
1424 }
1425}
1426
93c0345b 1427static int blocks_remove_matching_addrs(struct block_info **head,
1428 u_int base_offs, int shift)
104df9d3 1429{
1430 struct block_info *next;
93c0345b 1431 int hit = 0;
104df9d3 1432 while (*head) {
93c0345b 1433 if ((((*head)->tc_offs ^ base_offs) >> shift) == 0) {
9b495f6e 1434 inv_debug("EXP: rm block %08x (tc_offs %x)\n", (*head)->start, (*head)->tc_offs);
104df9d3 1435 invalidate_block(*head);
1436 next = (*head)->next;
1437 free(*head);
1438 *head = next;
1439 stat_dec(stat_blocks);
93c0345b 1440 hit = 1;
104df9d3 1441 }
1442 else
1443 {
1444 head = &((*head)->next);
1445 }
1446 }
93c0345b 1447 return hit;
104df9d3 1448}
57871462 1449
1450// This is called when we write to a compiled block (see do_invstub)
b7ad2f2c 1451static void unlink_jumps_vaddr_range(u_int start, u_int end)
57871462 1452{
104df9d3 1453 u_int page, start_page = get_page(start), end_page = get_page(end - 1);
b7ad2f2c 1454 int i;
104df9d3 1455
1456 for (page = start_page; page <= end_page; page++) {
b7ad2f2c 1457 struct jump_info *ji = jumps[page];
1458 if (ji == NULL)
1459 continue;
1460 for (i = 0; i < ji->count; ) {
1461 if (ji->e[i].target_vaddr < start || ji->e[i].target_vaddr >= end) {
1462 i++;
104df9d3 1463 continue;
1464 }
b7ad2f2c 1465
1466 inv_debug("INV: rm link to %08x (tc_offs %zx)\n", ji->e[i].target_vaddr,
1467 (u_char *)ji->e[i].stub - ndrc->translation_cache);
1468 void *host_addr = find_extjump_insn(ji->e[i].stub);
104df9d3 1469 mark_clear_cache(host_addr);
b7ad2f2c 1470 set_jump_target(host_addr, ji->e[i].stub); // point back to dyna_linker stub
104df9d3 1471
104df9d3 1472 stat_dec(stat_links);
b7ad2f2c 1473 ji->count--;
1474 if (i < ji->count) {
1475 ji->e[i] = ji->e[ji->count];
1476 continue;
1477 }
1478 i++;
1479 }
1480 }
1481}
1482
1483static void unlink_jumps_tc_range(struct jump_info *ji, u_int base_offs, int shift)
1484{
1485 int i;
1486 if (ji == NULL)
1487 return;
1488 for (i = 0; i < ji->count; ) {
1489 u_int tc_offs = (u_char *)ji->e[i].stub - ndrc->translation_cache;
1490 if (((tc_offs ^ base_offs) >> shift) != 0) {
1491 i++;
1492 continue;
1493 }
1494
9b495f6e 1495 inv_debug("EXP: rm link to %08x (tc_offs %x)\n", ji->e[i].target_vaddr, tc_offs);
b7ad2f2c 1496 stat_dec(stat_links);
1497 ji->count--;
1498 if (i < ji->count) {
1499 ji->e[i] = ji->e[ji->count];
1500 continue;
104df9d3 1501 }
b7ad2f2c 1502 i++;
57871462 1503 }
104df9d3 1504}
9f51b4b9 1505
104df9d3 1506static void invalidate_block(struct block_info *block)
1507{
1508 u_int i;
f76eeef9 1509
104df9d3 1510 block->is_dirty = 1;
b7ad2f2c 1511 unlink_jumps_vaddr_range(block->start, block->start + block->len);
104df9d3 1512 for (i = 0; i < block->jump_in_cnt; i++)
1513 hash_table_remove(block->jump_in[i].vaddr);
57871462 1514}
9be4ba64 1515
104df9d3 1516static int invalidate_range(u_int start, u_int end,
1517 u32 *inv_start_ret, u32 *inv_end_ret)
9be4ba64 1518{
3280e616 1519 struct block_info *last_block = NULL;
104df9d3 1520 u_int start_page = get_page_prev(start);
1521 u_int end_page = get_page(end - 1);
1522 u_int start_m = pmmask(start);
ab4377be 1523 u_int end_m = pmmask(end - 1);
104df9d3 1524 u_int inv_start, inv_end;
1525 u_int blk_start_m, blk_end_m;
1526 u_int page;
1527 int hit = 0;
1528
1529 // additional area without code (to supplement invalid_code[]), [start, end)
9b495f6e 1530 // avoids excessive ndrc_write_invalidate*() calls
104df9d3 1531 inv_start = start_m & ~0xfff;
1532 inv_end = end_m | 0xfff;
1533
1534 for (page = start_page; page <= end_page; page++) {
1535 struct block_info *block;
1536 for (block = blocks[page]; block != NULL; block = block->next) {
1537 if (block->is_dirty)
1538 continue;
3280e616 1539 last_block = block;
104df9d3 1540 blk_end_m = pmmask(block->start + block->len);
1541 if (blk_end_m <= start_m) {
1542 inv_start = max(inv_start, blk_end_m);
1543 continue;
1544 }
1545 blk_start_m = pmmask(block->start);
1546 if (end_m <= blk_start_m) {
1547 inv_end = min(inv_end, blk_start_m - 1);
1548 continue;
9be4ba64 1549 }
104df9d3 1550 if (!block->source) // "hack" block - leave it alone
1551 continue;
1552
1553 hit++;
1554 invalidate_block(block);
1555 stat_inc(stat_inv_hits);
9be4ba64 1556 }
9be4ba64 1557 }
104df9d3 1558
3280e616 1559 if (!hit && last_block && last_block->source) {
1560 // could be some leftover unused block, uselessly trapping writes
1561 last_block->inv_near_misses++;
1562 if (last_block->inv_near_misses > 128) {
1563 invalidate_block(last_block);
1564 stat_inc(stat_inv_hits);
1565 hit++;
1566 }
1567 }
104df9d3 1568 if (hit) {
1569 do_clear_cache();
1570#ifdef USE_MINI_HT
1571 memset(mini_ht, -1, sizeof(mini_ht));
1572#endif
1573 }
3280e616 1574
104df9d3 1575 if (inv_start <= (start_m & ~0xfff) && inv_end >= (start_m | 0xfff))
1576 // the whole page is empty now
1577 mark_invalid_code(start, 1, 1);
1578
1579 if (inv_start_ret) *inv_start_ret = inv_start | (start & 0xe0000000);
1580 if (inv_end_ret) *inv_end_ret = inv_end | (end & 0xe0000000);
1581 return hit;
9be4ba64 1582}
1583
104df9d3 1584void new_dynarec_invalidate_range(unsigned int start, unsigned int end)
1585{
1586 invalidate_range(start, end, NULL, NULL);
1587}
1588
9b495f6e 1589static void ndrc_write_invalidate_many(u_int start, u_int end)
57871462 1590{
9be4ba64 1591 // this check is done by the caller
1592 //if (inv_code_start<=addr&&addr<=inv_code_end) { rhits++; return; }
9b495f6e 1593 int ret = invalidate_range(start, end, &inv_code_start, &inv_code_end);
1594#ifdef INV_DEBUG_W
1595 int invc = invalid_code[start >> 12];
1596 u_int len = end - start;
104df9d3 1597 if (ret)
9b495f6e 1598 printf("INV ADDR: %08x/%02x hit %d blocks\n", start, len, ret);
104df9d3 1599 else
9b495f6e 1600 printf("INV ADDR: %08x/%02x miss, inv %08x-%08x invc %d->%d\n", start, len,
1601 inv_code_start, inv_code_end, invc, invalid_code[start >> 12]);
1602 check_for_block_changes(start, end);
1603#endif
ece032e6 1604 stat_inc(stat_inv_addr_calls);
9b495f6e 1605 (void)ret;
1606}
1607
1608void ndrc_write_invalidate_one(u_int addr)
1609{
1610 ndrc_write_invalidate_many(addr, addr + 4);
57871462 1611}
9be4ba64 1612
dd3a91a1 1613// This is called when loading a save state.
1614// Anything could have changed, so invalidate everything.
104df9d3 1615void new_dynarec_invalidate_all_pages(void)
57871462 1616{
104df9d3 1617 struct block_info *block;
581335b0 1618 u_int page;
104df9d3 1619 for (page = 0; page < ARRAY_SIZE(blocks); page++) {
1620 for (block = blocks[page]; block != NULL; block = block->next) {
1621 if (block->is_dirty)
1622 continue;
1623 if (!block->source) // hack block?
1624 continue;
1625 invalidate_block(block);
1626 }
1627 }
1628
57871462 1629 #ifdef USE_MINI_HT
93c0345b 1630 memset(mini_ht, -1, sizeof(mini_ht));
57871462 1631 #endif
919981d0 1632 do_clear_cache();
57871462 1633}
1634
1635// Add an entry to jump_out after making a link
104df9d3 1636// src should point to code by emit_extjump()
b7ad2f2c 1637void ndrc_add_jump_out(u_int vaddr, void *src)
57871462 1638{
b7ad2f2c 1639 inv_debug("ndrc_add_jump_out: %p -> %x\n", src, vaddr);
1640 u_int page = get_page(vaddr);
1641 struct jump_info *ji;
1642
104df9d3 1643 stat_inc(stat_links);
b7ad2f2c 1644 check_extjump2(src);
1645 ji = jumps[page];
1646 if (ji == NULL) {
1647 ji = malloc(sizeof(*ji) + sizeof(ji->e[0]) * 16);
1648 ji->alloc = 16;
1649 ji->count = 0;
1650 }
1651 else if (ji->count >= ji->alloc) {
1652 ji->alloc += 16;
1653 ji = realloc(ji, sizeof(*ji) + sizeof(ji->e[0]) * ji->alloc);
1654 }
1655 jumps[page] = ji;
1656 ji->e[ji->count].target_vaddr = vaddr;
1657 ji->e[ji->count].stub = src;
1658 ji->count++;
57871462 1659}
1660
8062d65a 1661/* Register allocation */
1662
90f98e7c 1663static void alloc_set(struct regstat *cur, int reg, int hr)
1664{
1665 cur->regmap[hr] = reg;
1666 cur->dirty &= ~(1u << hr);
1667 cur->isconst &= ~(1u << hr);
1668 cur->noevict |= 1u << hr;
1669}
1670
1671static void evict_alloc_reg(struct regstat *cur, int i, int reg, int preferred_hr)
1672{
1673 u_char hsn[MAXREG+1];
1674 int j, r, hr;
1675 memset(hsn, 10, sizeof(hsn));
1676 lsn(hsn, i);
1677 //printf("hsn(%x): %d %d %d %d %d %d %d\n",start+i*4,hsn[cur->regmap[0]&63],hsn[cur->regmap[1]&63],hsn[cur->regmap[2]&63],hsn[cur->regmap[3]&63],hsn[cur->regmap[5]&63],hsn[cur->regmap[6]&63],hsn[cur->regmap[7]&63]);
1678 if(i>0) {
1679 // Don't evict the cycle count at entry points, otherwise the entry
1680 // stub will have to write it.
1681 if(dops[i].bt&&hsn[CCREG]>2) hsn[CCREG]=2;
1682 if (i>1 && hsn[CCREG] > 2 && dops[i-2].is_jump) hsn[CCREG]=2;
1683 for(j=10;j>=3;j--)
1684 {
1685 // Alloc preferred register if available
1686 if (!((cur->noevict >> preferred_hr) & 1)
1687 && hsn[cur->regmap[preferred_hr]] == j)
1688 {
1689 alloc_set(cur, reg, preferred_hr);
1690 return;
1691 }
1692 for(r=1;r<=MAXREG;r++)
1693 {
1694 if(hsn[r]==j&&r!=dops[i-1].rs1&&r!=dops[i-1].rs2&&r!=dops[i-1].rt1&&r!=dops[i-1].rt2) {
1695 for(hr=0;hr<HOST_REGS;hr++) {
1696 if (hr == EXCLUDE_REG || ((cur->noevict >> hr) & 1))
1697 continue;
1698 if(hr!=HOST_CCREG||j<hsn[CCREG]) {
1699 if(cur->regmap[hr]==r) {
1700 alloc_set(cur, reg, hr);
1701 return;
1702 }
1703 }
1704 }
1705 }
1706 }
1707 }
1708 }
1709 for(j=10;j>=0;j--)
1710 {
1711 for(r=1;r<=MAXREG;r++)
1712 {
1713 if(hsn[r]==j) {
1714 for(hr=0;hr<HOST_REGS;hr++) {
1715 if (hr == EXCLUDE_REG || ((cur->noevict >> hr) & 1))
1716 continue;
1717 if(cur->regmap[hr]==r) {
1718 alloc_set(cur, reg, hr);
1719 return;
1720 }
1721 }
1722 }
1723 }
1724 }
1725 SysPrintf("This shouldn't happen (evict_alloc_reg)\n");
1726 abort();
1727}
1728
8062d65a 1729// Note: registers are allocated clean (unmodified state)
1730// if you intend to modify the register, you must call dirty_reg().
1731static void alloc_reg(struct regstat *cur,int i,signed char reg)
1732{
1733 int r,hr;
b7ec323c 1734 int preferred_reg = PREFERRED_REG_FIRST
1735 + reg % (PREFERRED_REG_LAST - PREFERRED_REG_FIRST + 1);
1736 if (reg == CCREG) preferred_reg = HOST_CCREG;
1737 if (reg == PTEMP || reg == FTEMP) preferred_reg = 12;
1738 assert(PREFERRED_REG_FIRST != EXCLUDE_REG && EXCLUDE_REG != HOST_REGS);
53358c1d 1739 assert(reg >= 0);
8062d65a 1740
1741 // Don't allocate unused registers
1742 if((cur->u>>reg)&1) return;
1743
1744 // see if it's already allocated
90f98e7c 1745 if ((hr = get_reg(cur->regmap, reg)) >= 0) {
1746 cur->noevict |= 1u << hr;
53358c1d 1747 return;
90f98e7c 1748 }
8062d65a 1749
1750 // Keep the same mapping if the register was already allocated in a loop
1751 preferred_reg = loop_reg(i,reg,preferred_reg);
1752
1753 // Try to allocate the preferred register
90f98e7c 1754 if (cur->regmap[preferred_reg] == -1) {
1755 alloc_set(cur, reg, preferred_reg);
8062d65a 1756 return;
1757 }
1758 r=cur->regmap[preferred_reg];
1759 assert(r < 64);
1760 if((cur->u>>r)&1) {
90f98e7c 1761 alloc_set(cur, reg, preferred_reg);
8062d65a 1762 return;
1763 }
1764
1765 // Clear any unneeded registers
1766 // We try to keep the mapping consistent, if possible, because it
1767 // makes branches easier (especially loops). So we try to allocate
1768 // first (see above) before removing old mappings. If this is not
1769 // possible then go ahead and clear out the registers that are no
1770 // longer needed.
1771 for(hr=0;hr<HOST_REGS;hr++)
1772 {
1773 r=cur->regmap[hr];
1774 if(r>=0) {
1775 assert(r < 64);
1776 if((cur->u>>r)&1) {cur->regmap[hr]=-1;break;}
1777 }
1778 }
b7ec323c 1779
8062d65a 1780 // Try to allocate any available register, but prefer
1781 // registers that have not been used recently.
b7ec323c 1782 if (i > 0) {
1783 for (hr = PREFERRED_REG_FIRST; ; ) {
1784 if (cur->regmap[hr] < 0) {
1785 int oldreg = regs[i-1].regmap[hr];
1786 if (oldreg < 0 || (oldreg != dops[i-1].rs1 && oldreg != dops[i-1].rs2
1787 && oldreg != dops[i-1].rt1 && oldreg != dops[i-1].rt2))
1788 {
90f98e7c 1789 alloc_set(cur, reg, hr);
8062d65a 1790 return;
1791 }
1792 }
b7ec323c 1793 hr++;
1794 if (hr == EXCLUDE_REG)
1795 hr++;
1796 if (hr == HOST_REGS)
1797 hr = 0;
1798 if (hr == PREFERRED_REG_FIRST)
1799 break;
8062d65a 1800 }
1801 }
b7ec323c 1802
8062d65a 1803 // Try to allocate any available register
b7ec323c 1804 for (hr = PREFERRED_REG_FIRST; ; ) {
1805 if (cur->regmap[hr] < 0) {
90f98e7c 1806 alloc_set(cur, reg, hr);
8062d65a 1807 return;
1808 }
b7ec323c 1809 hr++;
1810 if (hr == EXCLUDE_REG)
1811 hr++;
1812 if (hr == HOST_REGS)
1813 hr = 0;
1814 if (hr == PREFERRED_REG_FIRST)
1815 break;
8062d65a 1816 }
1817
1818 // Ok, now we have to evict someone
1819 // Pick a register we hopefully won't need soon
90f98e7c 1820 evict_alloc_reg(cur, i, reg, preferred_reg);
8062d65a 1821}
1822
1823// Allocate a temporary register. This is done without regard to
1824// dirty status or whether the register we request is on the unneeded list
1825// Note: This will only allocate one register, even if called multiple times
1826static void alloc_reg_temp(struct regstat *cur,int i,signed char reg)
1827{
1828 int r,hr;
8062d65a 1829
1830 // see if it's already allocated
90f98e7c 1831 for (hr = 0; hr < HOST_REGS; hr++)
8062d65a 1832 {
90f98e7c 1833 if (hr != EXCLUDE_REG && cur->regmap[hr] == reg) {
1834 cur->noevict |= 1u << hr;
1835 return;
1836 }
8062d65a 1837 }
1838
1839 // Try to allocate any available register
1840 for(hr=HOST_REGS-1;hr>=0;hr--) {
1841 if(hr!=EXCLUDE_REG&&cur->regmap[hr]==-1) {
90f98e7c 1842 alloc_set(cur, reg, hr);
8062d65a 1843 return;
1844 }
1845 }
1846
1847 // Find an unneeded register
1848 for(hr=HOST_REGS-1;hr>=0;hr--)
1849 {
1850 r=cur->regmap[hr];
1851 if(r>=0) {
1852 assert(r < 64);
1853 if((cur->u>>r)&1) {
1854 if(i==0||((unneeded_reg[i-1]>>r)&1)) {
90f98e7c 1855 alloc_set(cur, reg, hr);
8062d65a 1856 return;
1857 }
1858 }
1859 }
1860 }
1861
1862 // Ok, now we have to evict someone
1863 // Pick a register we hopefully won't need soon
90f98e7c 1864 evict_alloc_reg(cur, i, reg, 0);
8062d65a 1865}
1866
ad49de89 1867static void mov_alloc(struct regstat *current,int i)
57871462 1868{
cf95b4f0 1869 if (dops[i].rs1 == HIREG || dops[i].rs1 == LOREG) {
9a3ccfeb 1870 alloc_cc(current,i); // for stalls
1871 dirty_reg(current,CCREG);
32631e6a 1872 }
1873
57871462 1874 // Note: Don't need to actually alloc the source registers
cf95b4f0 1875 //alloc_reg(current,i,dops[i].rs1);
1876 alloc_reg(current,i,dops[i].rt1);
ad49de89 1877
cf95b4f0 1878 clear_const(current,dops[i].rs1);
1879 clear_const(current,dops[i].rt1);
1880 dirty_reg(current,dops[i].rt1);
57871462 1881}
1882
ad49de89 1883static void shiftimm_alloc(struct regstat *current,int i)
57871462 1884{
cf95b4f0 1885 if(dops[i].opcode2<=0x3) // SLL/SRL/SRA
57871462 1886 {
cf95b4f0 1887 if(dops[i].rt1) {
1888 if(dops[i].rs1&&needed_again(dops[i].rs1,i)) alloc_reg(current,i,dops[i].rs1);
53dc27f6 1889 else dops[i].use_lt1=!!dops[i].rs1;
cf95b4f0 1890 alloc_reg(current,i,dops[i].rt1);
1891 dirty_reg(current,dops[i].rt1);
1892 if(is_const(current,dops[i].rs1)) {
1893 int v=get_const(current,dops[i].rs1);
277718fa 1894 if(dops[i].opcode2==0x00) set_const(current,dops[i].rt1,v<<cinfo[i].imm);
1895 if(dops[i].opcode2==0x02) set_const(current,dops[i].rt1,(u_int)v>>cinfo[i].imm);
1896 if(dops[i].opcode2==0x03) set_const(current,dops[i].rt1,v>>cinfo[i].imm);
dc49e339 1897 }
cf95b4f0 1898 else clear_const(current,dops[i].rt1);
57871462 1899 }
1900 }
dc49e339 1901 else
1902 {
cf95b4f0 1903 clear_const(current,dops[i].rs1);
1904 clear_const(current,dops[i].rt1);
dc49e339 1905 }
1906
cf95b4f0 1907 if(dops[i].opcode2>=0x38&&dops[i].opcode2<=0x3b) // DSLL/DSRL/DSRA
57871462 1908 {
9c45ca93 1909 assert(0);
57871462 1910 }
cf95b4f0 1911 if(dops[i].opcode2==0x3c) // DSLL32
57871462 1912 {
9c45ca93 1913 assert(0);
57871462 1914 }
cf95b4f0 1915 if(dops[i].opcode2==0x3e) // DSRL32
57871462 1916 {
9c45ca93 1917 assert(0);
57871462 1918 }
cf95b4f0 1919 if(dops[i].opcode2==0x3f) // DSRA32
57871462 1920 {
9c45ca93 1921 assert(0);
57871462 1922 }
1923}
1924
ad49de89 1925static void shift_alloc(struct regstat *current,int i)
57871462 1926{
cf95b4f0 1927 if(dops[i].rt1) {
cf95b4f0 1928 if(dops[i].rs1) alloc_reg(current,i,dops[i].rs1);
1929 if(dops[i].rs2) alloc_reg(current,i,dops[i].rs2);
1930 alloc_reg(current,i,dops[i].rt1);
1931 if(dops[i].rt1==dops[i].rs2) {
e1190b87 1932 alloc_reg_temp(current,i,-1);
277718fa 1933 cinfo[i].min_free_regs=1;
e1190b87 1934 }
cf95b4f0 1935 clear_const(current,dops[i].rs1);
1936 clear_const(current,dops[i].rs2);
1937 clear_const(current,dops[i].rt1);
1938 dirty_reg(current,dops[i].rt1);
57871462 1939 }
1940}
1941
ad49de89 1942static void alu_alloc(struct regstat *current,int i)
57871462 1943{
cf95b4f0 1944 if(dops[i].opcode2>=0x20&&dops[i].opcode2<=0x23) { // ADD/ADDU/SUB/SUBU
1945 if(dops[i].rt1) {
1946 if(dops[i].rs1&&dops[i].rs2) {
1947 alloc_reg(current,i,dops[i].rs1);
1948 alloc_reg(current,i,dops[i].rs2);
57871462 1949 }
1950 else {
cf95b4f0 1951 if(dops[i].rs1&&needed_again(dops[i].rs1,i)) alloc_reg(current,i,dops[i].rs1);
1952 if(dops[i].rs2&&needed_again(dops[i].rs2,i)) alloc_reg(current,i,dops[i].rs2);
57871462 1953 }
cf95b4f0 1954 alloc_reg(current,i,dops[i].rt1);
57871462 1955 }
277718fa 1956 if (dops[i].may_except) {
90f98e7c 1957 alloc_cc_optional(current, i); // for exceptions
277718fa 1958 alloc_reg_temp(current, i, -1);
1959 cinfo[i].min_free_regs = 1;
a5cd72d0 1960 }
57871462 1961 }
277718fa 1962 else if(dops[i].opcode2==0x2a||dops[i].opcode2==0x2b) { // SLT/SLTU
cf95b4f0 1963 if(dops[i].rt1) {
1964 alloc_reg(current,i,dops[i].rs1);
1965 alloc_reg(current,i,dops[i].rs2);
1966 alloc_reg(current,i,dops[i].rt1);
57871462 1967 }
57871462 1968 }
277718fa 1969 else if(dops[i].opcode2>=0x24&&dops[i].opcode2<=0x27) { // AND/OR/XOR/NOR
cf95b4f0 1970 if(dops[i].rt1) {
1971 if(dops[i].rs1&&dops[i].rs2) {
1972 alloc_reg(current,i,dops[i].rs1);
1973 alloc_reg(current,i,dops[i].rs2);
57871462 1974 }
1975 else
1976 {
cf95b4f0 1977 if(dops[i].rs1&&needed_again(dops[i].rs1,i)) alloc_reg(current,i,dops[i].rs1);
1978 if(dops[i].rs2&&needed_again(dops[i].rs2,i)) alloc_reg(current,i,dops[i].rs2);
57871462 1979 }
cf95b4f0 1980 alloc_reg(current,i,dops[i].rt1);
57871462 1981 }
1982 }
cf95b4f0 1983 clear_const(current,dops[i].rs1);
1984 clear_const(current,dops[i].rs2);
1985 clear_const(current,dops[i].rt1);
1986 dirty_reg(current,dops[i].rt1);
57871462 1987}
1988
ad49de89 1989static void imm16_alloc(struct regstat *current,int i)
57871462 1990{
cf95b4f0 1991 if(dops[i].rs1&&needed_again(dops[i].rs1,i)) alloc_reg(current,i,dops[i].rs1);
53dc27f6 1992 else dops[i].use_lt1=!!dops[i].rs1;
cf95b4f0 1993 if(dops[i].rt1) alloc_reg(current,i,dops[i].rt1);
a5cd72d0 1994 if(dops[i].opcode==0x0a||dops[i].opcode==0x0b) { // SLTI/SLTIU
cf95b4f0 1995 clear_const(current,dops[i].rs1);
1996 clear_const(current,dops[i].rt1);
57871462 1997 }
cf95b4f0 1998 else if(dops[i].opcode>=0x0c&&dops[i].opcode<=0x0e) { // ANDI/ORI/XORI
1999 if(is_const(current,dops[i].rs1)) {
2000 int v=get_const(current,dops[i].rs1);
277718fa 2001 if(dops[i].opcode==0x0c) set_const(current,dops[i].rt1,v&cinfo[i].imm);
2002 if(dops[i].opcode==0x0d) set_const(current,dops[i].rt1,v|cinfo[i].imm);
2003 if(dops[i].opcode==0x0e) set_const(current,dops[i].rt1,v^cinfo[i].imm);
57871462 2004 }
cf95b4f0 2005 else clear_const(current,dops[i].rt1);
57871462 2006 }
cf95b4f0 2007 else if(dops[i].opcode==0x08||dops[i].opcode==0x09) { // ADDI/ADDIU
2008 if(is_const(current,dops[i].rs1)) {
2009 int v=get_const(current,dops[i].rs1);
277718fa 2010 set_const(current,dops[i].rt1,v+cinfo[i].imm);
57871462 2011 }
cf95b4f0 2012 else clear_const(current,dops[i].rt1);
277718fa 2013 if (dops[i].may_except) {
90f98e7c 2014 alloc_cc_optional(current, i); // for exceptions
277718fa 2015 alloc_reg_temp(current, i, -1);
2016 cinfo[i].min_free_regs = 1;
a5cd72d0 2017 }
57871462 2018 }
2019 else {
277718fa 2020 set_const(current,dops[i].rt1,cinfo[i].imm<<16); // LUI
57871462 2021 }
cf95b4f0 2022 dirty_reg(current,dops[i].rt1);
57871462 2023}
2024
ad49de89 2025static void load_alloc(struct regstat *current,int i)
57871462 2026{
277718fa 2027 int need_temp = 0;
cf95b4f0 2028 clear_const(current,dops[i].rt1);
2029 //if(dops[i].rs1!=dops[i].rt1&&needed_again(dops[i].rs1,i)) clear_const(current,dops[i].rs1); // Does this help or hurt?
2030 if(!dops[i].rs1) current->u&=~1LL; // Allow allocating r0 if it's the source register
37387d8b 2031 if (needed_again(dops[i].rs1, i))
2032 alloc_reg(current, i, dops[i].rs1);
2033 if (ram_offset)
2034 alloc_reg(current, i, ROREG);
277718fa 2035 if (dops[i].may_except) {
90f98e7c 2036 alloc_cc_optional(current, i); // for exceptions
277718fa 2037 need_temp = 1;
2038 }
cf95b4f0 2039 if(dops[i].rt1&&!((current->u>>dops[i].rt1)&1)) {
2040 alloc_reg(current,i,dops[i].rt1);
a5cd72d0 2041 assert(get_reg_w(current->regmap, dops[i].rt1)>=0);
cf95b4f0 2042 dirty_reg(current,dops[i].rt1);
57871462 2043 // LWL/LWR need a temporary register for the old value
cf95b4f0 2044 if(dops[i].opcode==0x22||dops[i].opcode==0x26)
57871462 2045 {
2046 alloc_reg(current,i,FTEMP);
277718fa 2047 need_temp = 1;
57871462 2048 }
2049 }
2050 else
2051 {
373d1d07 2052 // Load to r0 or unneeded register (dummy load)
57871462 2053 // but we still need a register to calculate the address
cf95b4f0 2054 if(dops[i].opcode==0x22||dops[i].opcode==0x26)
535d208a 2055 alloc_reg(current,i,FTEMP); // LWL/LWR need another temporary
277718fa 2056 need_temp = 1;
2057 }
2058 if (need_temp) {
2059 alloc_reg_temp(current, i, -1);
2060 cinfo[i].min_free_regs = 1;
57871462 2061 }
2062}
2063
90f98e7c 2064// this may eat up to 7 registers
2065static void store_alloc(struct regstat *current, int i)
57871462 2066{
cf95b4f0 2067 clear_const(current,dops[i].rs2);
2068 if(!(dops[i].rs2)) current->u&=~1LL; // Allow allocating r0 if necessary
2069 if(needed_again(dops[i].rs1,i)) alloc_reg(current,i,dops[i].rs1);
2070 alloc_reg(current,i,dops[i].rs2);
37387d8b 2071 if (ram_offset)
2072 alloc_reg(current, i, ROREG);
57871462 2073 #if defined(HOST_IMM8)
2074 // On CPUs without 32-bit immediates we need a pointer to invalid_code
37387d8b 2075 alloc_reg(current, i, INVCP);
57871462 2076 #endif
277718fa 2077 if (dops[i].opcode == 0x2a || dops[i].opcode == 0x2e) { // SWL/SWL
57871462 2078 alloc_reg(current,i,FTEMP);
2079 }
90f98e7c 2080 if (dops[i].may_except)
2081 alloc_cc_optional(current, i); // for exceptions
57871462 2082 // We need a temporary register for address generation
2083 alloc_reg_temp(current,i,-1);
277718fa 2084 cinfo[i].min_free_regs=1;
57871462 2085}
2086
90f98e7c 2087static void c2ls_alloc(struct regstat *current, int i)
b9b61529 2088{
cf95b4f0 2089 clear_const(current,dops[i].rt1);
2090 if(needed_again(dops[i].rs1,i)) alloc_reg(current,i,dops[i].rs1);
b9b61529 2091 alloc_reg(current,i,FTEMP);
37387d8b 2092 if (ram_offset)
2093 alloc_reg(current, i, ROREG);
b9b61529 2094 #if defined(HOST_IMM8)
2095 // On CPUs without 32-bit immediates we need a pointer to invalid_code
37387d8b 2096 if (dops[i].opcode == 0x3a) // SWC2
b9b61529 2097 alloc_reg(current,i,INVCP);
2098 #endif
90f98e7c 2099 if (dops[i].may_except)
2100 alloc_cc_optional(current, i); // for exceptions
b9b61529 2101 // We need a temporary register for address generation
2102 alloc_reg_temp(current,i,-1);
277718fa 2103 cinfo[i].min_free_regs=1;
b9b61529 2104}
2105
57871462 2106#ifndef multdiv_alloc
4149788d 2107static void multdiv_alloc(struct regstat *current,int i)
57871462 2108{
2109 // case 0x18: MULT
2110 // case 0x19: MULTU
2111 // case 0x1A: DIV
2112 // case 0x1B: DIVU
cf95b4f0 2113 clear_const(current,dops[i].rs1);
2114 clear_const(current,dops[i].rs2);
32631e6a 2115 alloc_cc(current,i); // for stalls
90f98e7c 2116 dirty_reg(current,CCREG);
4ee246ed 2117 current->u &= ~(1ull << HIREG);
2118 current->u &= ~(1ull << LOREG);
2119 alloc_reg(current, i, HIREG);
2120 alloc_reg(current, i, LOREG);
2121 dirty_reg(current, HIREG);
2122 dirty_reg(current, LOREG);
2123 if ((dops[i].opcode2 & 0x3e) == 0x1a || (dops[i].rs1 && dops[i].rs2)) // div(u)
57871462 2124 {
4ee246ed 2125 alloc_reg(current, i, dops[i].rs1);
2126 alloc_reg(current, i, dops[i].rs2);
57871462 2127 }
4ee246ed 2128 // else multiply by zero is zero
57871462 2129}
2130#endif
2131
4149788d 2132static void cop0_alloc(struct regstat *current,int i)
57871462 2133{
cf95b4f0 2134 if(dops[i].opcode2==0) // MFC0
57871462 2135 {
cf95b4f0 2136 if(dops[i].rt1) {
2137 clear_const(current,dops[i].rt1);
cf95b4f0 2138 alloc_reg(current,i,dops[i].rt1);
2139 dirty_reg(current,dops[i].rt1);
57871462 2140 }
2141 }
cf95b4f0 2142 else if(dops[i].opcode2==4) // MTC0
57871462 2143 {
de6dbc52 2144 if (((source[i]>>11)&0x1e) == 12) {
2145 alloc_cc(current, i);
2146 dirty_reg(current, CCREG);
2147 }
cf95b4f0 2148 if(dops[i].rs1){
2149 clear_const(current,dops[i].rs1);
2150 alloc_reg(current,i,dops[i].rs1);
57871462 2151 alloc_all(current,i);
2152 }
2153 else {
2154 alloc_all(current,i); // FIXME: Keep r0
2155 current->u&=~1LL;
2156 alloc_reg(current,i,0);
2157 }
277718fa 2158 cinfo[i].min_free_regs = HOST_REGS;
57871462 2159 }
a5cd72d0 2160}
2161
2162static void rfe_alloc(struct regstat *current, int i)
2163{
2164 alloc_all(current, i);
277718fa 2165 cinfo[i].min_free_regs = HOST_REGS;
57871462 2166}
2167
81dbbf4c 2168static void cop2_alloc(struct regstat *current,int i)
57871462 2169{
cf95b4f0 2170 if (dops[i].opcode2 < 3) // MFC2/CFC2
57871462 2171 {
81dbbf4c 2172 alloc_cc(current,i); // for stalls
2173 dirty_reg(current,CCREG);
cf95b4f0 2174 if(dops[i].rt1){
2175 clear_const(current,dops[i].rt1);
2176 alloc_reg(current,i,dops[i].rt1);
2177 dirty_reg(current,dops[i].rt1);
57871462 2178 }
57871462 2179 }
cf95b4f0 2180 else if (dops[i].opcode2 > 3) // MTC2/CTC2
57871462 2181 {
cf95b4f0 2182 if(dops[i].rs1){
2183 clear_const(current,dops[i].rs1);
2184 alloc_reg(current,i,dops[i].rs1);
57871462 2185 }
2186 else {
2187 current->u&=~1LL;
2188 alloc_reg(current,i,0);
57871462 2189 }
2190 }
81dbbf4c 2191 alloc_reg_temp(current,i,-1);
277718fa 2192 cinfo[i].min_free_regs=1;
57871462 2193}
00fa9369 2194
4149788d 2195static void c2op_alloc(struct regstat *current,int i)
b9b61529 2196{
81dbbf4c 2197 alloc_cc(current,i); // for stalls
2198 dirty_reg(current,CCREG);
b9b61529 2199 alloc_reg_temp(current,i,-1);
2200}
57871462 2201
4149788d 2202static void syscall_alloc(struct regstat *current,int i)
57871462 2203{
2204 alloc_cc(current,i);
2205 dirty_reg(current,CCREG);
2206 alloc_all(current,i);
277718fa 2207 cinfo[i].min_free_regs=HOST_REGS;
57871462 2208 current->isconst=0;
2209}
2210
4149788d 2211static void delayslot_alloc(struct regstat *current,int i)
57871462 2212{
cf95b4f0 2213 switch(dops[i].itype) {
57871462 2214 case UJUMP:
2215 case CJUMP:
2216 case SJUMP:
2217 case RJUMP:
57871462 2218 case SYSCALL:
7139f3c8 2219 case HLECALL:
57871462 2220 case IMM16:
2221 imm16_alloc(current,i);
2222 break;
2223 case LOAD:
2224 case LOADLR:
2225 load_alloc(current,i);
2226 break;
2227 case STORE:
2228 case STORELR:
2229 store_alloc(current,i);
2230 break;
2231 case ALU:
2232 alu_alloc(current,i);
2233 break;
2234 case SHIFT:
2235 shift_alloc(current,i);
2236 break;
2237 case MULTDIV:
2238 multdiv_alloc(current,i);
2239 break;
2240 case SHIFTIMM:
2241 shiftimm_alloc(current,i);
2242 break;
2243 case MOV:
2244 mov_alloc(current,i);
2245 break;
2246 case COP0:
2247 cop0_alloc(current,i);
2248 break;
a5cd72d0 2249 case RFE:
2250 rfe_alloc(current,i);
81dbbf4c 2251 break;
b9b61529 2252 case COP2:
81dbbf4c 2253 cop2_alloc(current,i);
57871462 2254 break;
b9b61529 2255 case C2LS:
2256 c2ls_alloc(current,i);
2257 break;
b9b61529 2258 case C2OP:
2259 c2op_alloc(current,i);
2260 break;
57871462 2261 }
2262}
2263
b14b6a8f 2264static void add_stub(enum stub_type type, void *addr, void *retaddr,
2265 u_int a, uintptr_t b, uintptr_t c, u_int d, u_int e)
2266{
d1e4ebd9 2267 assert(stubcount < ARRAY_SIZE(stubs));
b14b6a8f 2268 stubs[stubcount].type = type;
2269 stubs[stubcount].addr = addr;
2270 stubs[stubcount].retaddr = retaddr;
2271 stubs[stubcount].a = a;
2272 stubs[stubcount].b = b;
2273 stubs[stubcount].c = c;
2274 stubs[stubcount].d = d;
2275 stubs[stubcount].e = e;
57871462 2276 stubcount++;
2277}
2278
b14b6a8f 2279static void add_stub_r(enum stub_type type, void *addr, void *retaddr,
81dbbf4c 2280 int i, int addr_reg, const struct regstat *i_regs, int ccadj, u_int reglist)
b14b6a8f 2281{
2282 add_stub(type, addr, retaddr, i, addr_reg, (uintptr_t)i_regs, ccadj, reglist);
2283}
2284
57871462 2285// Write out a single register
a22ccd6a 2286static void wb_register(signed char r, const signed char regmap[], u_int dirty)
57871462 2287{
2288 int hr;
2289 for(hr=0;hr<HOST_REGS;hr++) {
2290 if(hr!=EXCLUDE_REG) {
9de8a0c3 2291 if(regmap[hr]==r) {
57871462 2292 if((dirty>>hr)&1) {
ad49de89 2293 assert(regmap[hr]<64);
2294 emit_storereg(r,hr);
57871462 2295 }
a22ccd6a 2296 break;
57871462 2297 }
2298 }
2299 }
2300}
2301
8062d65a 2302static void wb_valid(signed char pre[],signed char entry[],u_int dirty_pre,u_int dirty,uint64_t u)
2303{
2304 //if(dirty_pre==dirty) return;
53358c1d 2305 int hr, r;
2306 for (hr = 0; hr < HOST_REGS; hr++) {
2307 r = pre[hr];
2308 if (r < 1 || r > 33 || ((u >> r) & 1))
2309 continue;
2310 if (((dirty_pre & ~dirty) >> hr) & 1)
2311 emit_storereg(r, hr);
8062d65a 2312 }
2313}
2314
687b4580 2315// trashes r2
2316static void pass_args(int a0, int a1)
2317{
2318 if(a0==1&&a1==0) {
2319 // must swap
2320 emit_mov(a0,2); emit_mov(a1,1); emit_mov(2,0);
2321 }
2322 else if(a0!=0&&a1==0) {
2323 emit_mov(a1,1);
2324 if (a0>=0) emit_mov(a0,0);
2325 }
2326 else {
2327 if(a0>=0&&a0!=0) emit_mov(a0,0);
2328 if(a1>=0&&a1!=1) emit_mov(a1,1);
2329 }
2330}
2331
a5cd72d0 2332static void alu_assemble(int i, const struct regstat *i_regs, int ccadj_)
57871462 2333{
cf95b4f0 2334 if(dops[i].opcode2>=0x20&&dops[i].opcode2<=0x23) { // ADD/ADDU/SUB/SUBU
a5cd72d0 2335 int do_oflow = dops[i].may_except; // ADD/SUB with exceptions enabled
2336 if (dops[i].rt1 || do_oflow) {
2337 int do_exception_check = 0;
2338 signed char s1, s2, t, tmp;
2339 t = get_reg_w(i_regs->regmap, dops[i].rt1);
2340 tmp = get_reg_temp(i_regs->regmap);
277718fa 2341 if (do_oflow)
2342 assert(tmp >= 0);
90f98e7c 2343 if (t < 0 && do_oflow)
2344 t = tmp;
a5cd72d0 2345 if (t >= 0) {
2346 s1 = get_reg(i_regs->regmap, dops[i].rs1);
2347 s2 = get_reg(i_regs->regmap, dops[i].rs2);
2348 if (dops[i].rs1 && dops[i].rs2) {
57871462 2349 assert(s1>=0);
2350 assert(s2>=0);
a5cd72d0 2351 if (dops[i].opcode2 & 2) {
2352 if (do_oflow) {
2353 emit_subs(s1, s2, tmp);
2354 do_exception_check = 1;
2355 }
2356 else
2357 emit_sub(s1,s2,t);
2358 }
2359 else {
2360 if (do_oflow) {
2361 emit_adds(s1, s2, tmp);
2362 do_exception_check = 1;
2363 }
2364 else
2365 emit_add(s1,s2,t);
2366 }
57871462 2367 }
cf95b4f0 2368 else if(dops[i].rs1) {
57871462 2369 if(s1>=0) emit_mov(s1,t);
cf95b4f0 2370 else emit_loadreg(dops[i].rs1,t);
57871462 2371 }
cf95b4f0 2372 else if(dops[i].rs2) {
a5cd72d0 2373 if (s2 < 0) {
2374 emit_loadreg(dops[i].rs2, t);
2375 s2 = t;
57871462 2376 }
a5cd72d0 2377 if (dops[i].opcode2 & 2) {
2378 if (do_oflow) {
2379 emit_negs(s2, tmp);
2380 do_exception_check = 1;
2381 }
2382 else
2383 emit_neg(s2, t);
57871462 2384 }
a5cd72d0 2385 else if (s2 != t)
2386 emit_mov(s2, t);
57871462 2387 }
a5cd72d0 2388 else
2389 emit_zeroreg(t);
2390 }
2391 if (do_exception_check) {
2392 void *jaddr = out;
2393 emit_jo(0);
2394 if (t >= 0 && tmp != t)
2395 emit_mov(tmp, t);
2396 add_stub_r(OVERFLOW_STUB, jaddr, out, i, 0, i_regs, ccadj_, 0);
57871462 2397 }
2398 }
2399 }
a5cd72d0 2400 else if(dops[i].opcode2==0x2a||dops[i].opcode2==0x2b) { // SLT/SLTU
cf95b4f0 2401 if(dops[i].rt1) {
ad49de89 2402 signed char s1l,s2l,t;
57871462 2403 {
a5cd72d0 2404 t=get_reg_w(i_regs->regmap, dops[i].rt1);
57871462 2405 //assert(t>=0);
2406 if(t>=0) {
cf95b4f0 2407 s1l=get_reg(i_regs->regmap,dops[i].rs1);
2408 s2l=get_reg(i_regs->regmap,dops[i].rs2);
2409 if(dops[i].rs2==0) // rx<r0
57871462 2410 {
cf95b4f0 2411 if(dops[i].opcode2==0x2a&&dops[i].rs1!=0) { // SLT
06e425d7 2412 assert(s1l>=0);
57871462 2413 emit_shrimm(s1l,31,t);
06e425d7 2414 }
2415 else // SLTU (unsigned can not be less than zero, 0<0)
57871462 2416 emit_zeroreg(t);
2417 }
cf95b4f0 2418 else if(dops[i].rs1==0) // r0<rx
57871462 2419 {
2420 assert(s2l>=0);
cf95b4f0 2421 if(dops[i].opcode2==0x2a) // SLT
57871462 2422 emit_set_gz32(s2l,t);
2423 else // SLTU (set if not zero)
2424 emit_set_nz32(s2l,t);
2425 }
2426 else{
2427 assert(s1l>=0);assert(s2l>=0);
cf95b4f0 2428 if(dops[i].opcode2==0x2a) // SLT
57871462 2429 emit_set_if_less32(s1l,s2l,t);
2430 else // SLTU
2431 emit_set_if_carry32(s1l,s2l,t);
2432 }
2433 }
2434 }
2435 }
2436 }
a5cd72d0 2437 else if(dops[i].opcode2>=0x24&&dops[i].opcode2<=0x27) { // AND/OR/XOR/NOR
cf95b4f0 2438 if(dops[i].rt1) {
ad49de89 2439 signed char s1l,s2l,tl;
a5cd72d0 2440 tl=get_reg_w(i_regs->regmap, dops[i].rt1);
57871462 2441 {
57871462 2442 if(tl>=0) {
cf95b4f0 2443 s1l=get_reg(i_regs->regmap,dops[i].rs1);
2444 s2l=get_reg(i_regs->regmap,dops[i].rs2);
2445 if(dops[i].rs1&&dops[i].rs2) {
57871462 2446 assert(s1l>=0);
2447 assert(s2l>=0);
cf95b4f0 2448 if(dops[i].opcode2==0x24) { // AND
57871462 2449 emit_and(s1l,s2l,tl);
2450 } else
cf95b4f0 2451 if(dops[i].opcode2==0x25) { // OR
57871462 2452 emit_or(s1l,s2l,tl);
2453 } else
cf95b4f0 2454 if(dops[i].opcode2==0x26) { // XOR
57871462 2455 emit_xor(s1l,s2l,tl);
2456 } else
cf95b4f0 2457 if(dops[i].opcode2==0x27) { // NOR
57871462 2458 emit_or(s1l,s2l,tl);
2459 emit_not(tl,tl);
2460 }
2461 }
2462 else
2463 {
cf95b4f0 2464 if(dops[i].opcode2==0x24) { // AND
57871462 2465 emit_zeroreg(tl);
2466 } else
cf95b4f0 2467 if(dops[i].opcode2==0x25||dops[i].opcode2==0x26) { // OR/XOR
2468 if(dops[i].rs1){
57871462 2469 if(s1l>=0) emit_mov(s1l,tl);
cf95b4f0 2470 else emit_loadreg(dops[i].rs1,tl); // CHECK: regmap_entry?
57871462 2471 }
2472 else
cf95b4f0 2473 if(dops[i].rs2){
57871462 2474 if(s2l>=0) emit_mov(s2l,tl);
cf95b4f0 2475 else emit_loadreg(dops[i].rs2,tl); // CHECK: regmap_entry?
57871462 2476 }
2477 else emit_zeroreg(tl);
2478 } else
cf95b4f0 2479 if(dops[i].opcode2==0x27) { // NOR
2480 if(dops[i].rs1){
57871462 2481 if(s1l>=0) emit_not(s1l,tl);
2482 else {
cf95b4f0 2483 emit_loadreg(dops[i].rs1,tl);
57871462 2484 emit_not(tl,tl);
2485 }
2486 }
2487 else
cf95b4f0 2488 if(dops[i].rs2){
57871462 2489 if(s2l>=0) emit_not(s2l,tl);
2490 else {
cf95b4f0 2491 emit_loadreg(dops[i].rs2,tl);
57871462 2492 emit_not(tl,tl);
2493 }
2494 }
2495 else emit_movimm(-1,tl);
2496 }
2497 }
2498 }
2499 }
2500 }
2501 }
2502}
2503
a5cd72d0 2504static void imm16_assemble(int i, const struct regstat *i_regs, int ccadj_)
57871462 2505{
cf95b4f0 2506 if (dops[i].opcode==0x0f) { // LUI
2507 if(dops[i].rt1) {
57871462 2508 signed char t;
a5cd72d0 2509 t=get_reg_w(i_regs->regmap, dops[i].rt1);
57871462 2510 //assert(t>=0);
2511 if(t>=0) {
2512 if(!((i_regs->isconst>>t)&1))
277718fa 2513 emit_movimm(cinfo[i].imm<<16,t);
57871462 2514 }
2515 }
2516 }
cf95b4f0 2517 if(dops[i].opcode==0x08||dops[i].opcode==0x09) { // ADDI/ADDIU
277718fa 2518 int is_addi = dops[i].may_except;
a5cd72d0 2519 if (dops[i].rt1 || is_addi) {
2520 signed char s, t, tmp;
2521 t=get_reg_w(i_regs->regmap, dops[i].rt1);
cf95b4f0 2522 s=get_reg(i_regs->regmap,dops[i].rs1);
2523 if(dops[i].rs1) {
a5cd72d0 2524 tmp = get_reg_temp(i_regs->regmap);
2525 if (is_addi) {
2526 assert(tmp >= 0);
2527 if (t < 0) t = tmp;
2528 }
57871462 2529 if(t>=0) {
2530 if(!((i_regs->isconst>>t)&1)) {
a5cd72d0 2531 int sum, do_exception_check = 0;
2532 if (s < 0) {
cf95b4f0 2533 if(i_regs->regmap_entry[t]!=dops[i].rs1) emit_loadreg(dops[i].rs1,t);
a5cd72d0 2534 if (is_addi) {
277718fa 2535 emit_addimm_and_set_flags3(t, cinfo[i].imm, tmp);
a5cd72d0 2536 do_exception_check = 1;
2537 }
57871462 2538 else
277718fa 2539 emit_addimm(t, cinfo[i].imm, t);
a5cd72d0 2540 } else {
2541 if (!((i_regs->wasconst >> s) & 1)) {
2542 if (is_addi) {
277718fa 2543 emit_addimm_and_set_flags3(s, cinfo[i].imm, tmp);
a5cd72d0 2544 do_exception_check = 1;
2545 }
2546 else
277718fa 2547 emit_addimm(s, cinfo[i].imm, t);
a5cd72d0 2548 }
2549 else {
277718fa 2550 int oflow = add_overflow(constmap[i][s], cinfo[i].imm, sum);
a5cd72d0 2551 if (is_addi && oflow)
2552 do_exception_check = 2;
2553 else
2554 emit_movimm(sum, t);
2555 }
2556 }
2557 if (do_exception_check) {
2558 void *jaddr = out;
2559 if (do_exception_check == 2)
2560 emit_jmp(0);
2561 else {
2562 emit_jo(0);
2563 if (tmp != t)
2564 emit_mov(tmp, t);
2565 }
2566 add_stub_r(OVERFLOW_STUB, jaddr, out, i, 0, i_regs, ccadj_, 0);
57871462 2567 }
2568 }
2569 }
2570 } else {
2571 if(t>=0) {
2572 if(!((i_regs->isconst>>t)&1))
277718fa 2573 emit_movimm(cinfo[i].imm,t);
57871462 2574 }
2575 }
2576 }
2577 }
cf95b4f0 2578 else if(dops[i].opcode==0x0a||dops[i].opcode==0x0b) { // SLTI/SLTIU
2579 if(dops[i].rt1) {
2580 //assert(dops[i].rs1!=0); // r0 might be valid, but it's probably a bug
ad49de89 2581 signed char sl,t;
a5cd72d0 2582 t=get_reg_w(i_regs->regmap, dops[i].rt1);
cf95b4f0 2583 sl=get_reg(i_regs->regmap,dops[i].rs1);
57871462 2584 //assert(t>=0);
2585 if(t>=0) {
cf95b4f0 2586 if(dops[i].rs1>0) {
2587 if(dops[i].opcode==0x0a) { // SLTI
57871462 2588 if(sl<0) {
cf95b4f0 2589 if(i_regs->regmap_entry[t]!=dops[i].rs1) emit_loadreg(dops[i].rs1,t);
277718fa 2590 emit_slti32(t,cinfo[i].imm,t);
57871462 2591 }else{
277718fa 2592 emit_slti32(sl,cinfo[i].imm,t);
57871462 2593 }
2594 }
2595 else { // SLTIU
2596 if(sl<0) {
cf95b4f0 2597 if(i_regs->regmap_entry[t]!=dops[i].rs1) emit_loadreg(dops[i].rs1,t);
277718fa 2598 emit_sltiu32(t,cinfo[i].imm,t);
57871462 2599 }else{
277718fa 2600 emit_sltiu32(sl,cinfo[i].imm,t);
57871462 2601 }
2602 }
57871462 2603 }else{
2604 // SLTI(U) with r0 is just stupid,
2605 // nonetheless examples can be found
cf95b4f0 2606 if(dops[i].opcode==0x0a) // SLTI
277718fa 2607 if(0<cinfo[i].imm) emit_movimm(1,t);
57871462 2608 else emit_zeroreg(t);
2609 else // SLTIU
2610 {
277718fa 2611 if(cinfo[i].imm) emit_movimm(1,t);
57871462 2612 else emit_zeroreg(t);
2613 }
2614 }
2615 }
2616 }
2617 }
cf95b4f0 2618 else if(dops[i].opcode>=0x0c&&dops[i].opcode<=0x0e) { // ANDI/ORI/XORI
2619 if(dops[i].rt1) {
7c3a5182 2620 signed char sl,tl;
a5cd72d0 2621 tl=get_reg_w(i_regs->regmap, dops[i].rt1);
cf95b4f0 2622 sl=get_reg(i_regs->regmap,dops[i].rs1);
57871462 2623 if(tl>=0 && !((i_regs->isconst>>tl)&1)) {
cf95b4f0 2624 if(dops[i].opcode==0x0c) //ANDI
57871462 2625 {
cf95b4f0 2626 if(dops[i].rs1) {
57871462 2627 if(sl<0) {
cf95b4f0 2628 if(i_regs->regmap_entry[tl]!=dops[i].rs1) emit_loadreg(dops[i].rs1,tl);
277718fa 2629 emit_andimm(tl,cinfo[i].imm,tl);
57871462 2630 }else{
2631 if(!((i_regs->wasconst>>sl)&1))
277718fa 2632 emit_andimm(sl,cinfo[i].imm,tl);
57871462 2633 else
277718fa 2634 emit_movimm(constmap[i][sl]&cinfo[i].imm,tl);
57871462 2635 }
2636 }
2637 else
2638 emit_zeroreg(tl);
57871462 2639 }
2640 else
2641 {
cf95b4f0 2642 if(dops[i].rs1) {
57871462 2643 if(sl<0) {
cf95b4f0 2644 if(i_regs->regmap_entry[tl]!=dops[i].rs1) emit_loadreg(dops[i].rs1,tl);
57871462 2645 }
cf95b4f0 2646 if(dops[i].opcode==0x0d) { // ORI
581335b0 2647 if(sl<0) {
277718fa 2648 emit_orimm(tl,cinfo[i].imm,tl);
581335b0 2649 }else{
2650 if(!((i_regs->wasconst>>sl)&1))
277718fa 2651 emit_orimm(sl,cinfo[i].imm,tl);
581335b0 2652 else
277718fa 2653 emit_movimm(constmap[i][sl]|cinfo[i].imm,tl);
581335b0 2654 }
57871462 2655 }
cf95b4f0 2656 if(dops[i].opcode==0x0e) { // XORI
581335b0 2657 if(sl<0) {
277718fa 2658 emit_xorimm(tl,cinfo[i].imm,tl);
581335b0 2659 }else{
2660 if(!((i_regs->wasconst>>sl)&1))
277718fa 2661 emit_xorimm(sl,cinfo[i].imm,tl);
581335b0 2662 else
277718fa 2663 emit_movimm(constmap[i][sl]^cinfo[i].imm,tl);
581335b0 2664 }
57871462 2665 }
2666 }
2667 else {
277718fa 2668 emit_movimm(cinfo[i].imm,tl);
57871462 2669 }
2670 }
2671 }
2672 }
2673 }
2674}
2675
2330734f 2676static void shiftimm_assemble(int i, const struct regstat *i_regs)
57871462 2677{
cf95b4f0 2678 if(dops[i].opcode2<=0x3) // SLL/SRL/SRA
57871462 2679 {
cf95b4f0 2680 if(dops[i].rt1) {
57871462 2681 signed char s,t;
a5cd72d0 2682 t=get_reg_w(i_regs->regmap, dops[i].rt1);
cf95b4f0 2683 s=get_reg(i_regs->regmap,dops[i].rs1);
57871462 2684 //assert(t>=0);
dc49e339 2685 if(t>=0&&!((i_regs->isconst>>t)&1)){
cf95b4f0 2686 if(dops[i].rs1==0)
57871462 2687 {
2688 emit_zeroreg(t);
2689 }
2690 else
2691 {
cf95b4f0 2692 if(s<0&&i_regs->regmap_entry[t]!=dops[i].rs1) emit_loadreg(dops[i].rs1,t);
277718fa 2693 if(cinfo[i].imm) {
cf95b4f0 2694 if(dops[i].opcode2==0) // SLL
57871462 2695 {
277718fa 2696 emit_shlimm(s<0?t:s,cinfo[i].imm,t);
57871462 2697 }
cf95b4f0 2698 if(dops[i].opcode2==2) // SRL
57871462 2699 {
277718fa 2700 emit_shrimm(s<0?t:s,cinfo[i].imm,t);
57871462 2701 }
cf95b4f0 2702 if(dops[i].opcode2==3) // SRA
57871462 2703 {
277718fa 2704 emit_sarimm(s<0?t:s,cinfo[i].imm,t);
57871462 2705 }
2706 }else{
2707 // Shift by zero
2708 if(s>=0 && s!=t) emit_mov(s,t);
2709 }
2710 }
2711 }
cf95b4f0 2712 //emit_storereg(dops[i].rt1,t); //DEBUG
57871462 2713 }
2714 }
cf95b4f0 2715 if(dops[i].opcode2>=0x38&&dops[i].opcode2<=0x3b) // DSLL/DSRL/DSRA
57871462 2716 {
9c45ca93 2717 assert(0);
57871462 2718 }
cf95b4f0 2719 if(dops[i].opcode2==0x3c) // DSLL32
57871462 2720 {
9c45ca93 2721 assert(0);
57871462 2722 }
cf95b4f0 2723 if(dops[i].opcode2==0x3e) // DSRL32
57871462 2724 {
9c45ca93 2725 assert(0);
57871462 2726 }
cf95b4f0 2727 if(dops[i].opcode2==0x3f) // DSRA32
57871462 2728 {
9c45ca93 2729 assert(0);
57871462 2730 }
2731}
2732
2733#ifndef shift_assemble
2330734f 2734static void shift_assemble(int i, const struct regstat *i_regs)
57871462 2735{
3968e69e 2736 signed char s,t,shift;
cf95b4f0 2737 if (dops[i].rt1 == 0)
3968e69e 2738 return;
cf95b4f0 2739 assert(dops[i].opcode2<=0x07); // SLLV/SRLV/SRAV
2740 t = get_reg(i_regs->regmap, dops[i].rt1);
2741 s = get_reg(i_regs->regmap, dops[i].rs1);
2742 shift = get_reg(i_regs->regmap, dops[i].rs2);
3968e69e 2743 if (t < 0)
2744 return;
2745
cf95b4f0 2746 if(dops[i].rs1==0)
3968e69e 2747 emit_zeroreg(t);
cf95b4f0 2748 else if(dops[i].rs2==0) {
3968e69e 2749 assert(s>=0);
2750 if(s!=t) emit_mov(s,t);
2751 }
2752 else {
2753 host_tempreg_acquire();
2754 emit_andimm(shift,31,HOST_TEMPREG);
cf95b4f0 2755 switch(dops[i].opcode2) {
3968e69e 2756 case 4: // SLLV
2757 emit_shl(s,HOST_TEMPREG,t);
2758 break;
2759 case 6: // SRLV
2760 emit_shr(s,HOST_TEMPREG,t);
2761 break;
2762 case 7: // SRAV
2763 emit_sar(s,HOST_TEMPREG,t);
2764 break;
2765 default:
2766 assert(0);
2767 }
2768 host_tempreg_release();
2769 }
57871462 2770}
3968e69e 2771
57871462 2772#endif
2773
8062d65a 2774enum {
2775 MTYPE_8000 = 0,
2776 MTYPE_8020,
2777 MTYPE_0000,
2778 MTYPE_A000,
2779 MTYPE_1F80,
2780};
2781
2782static int get_ptr_mem_type(u_int a)
2783{
2784 if(a < 0x00200000) {
2785 if(a<0x1000&&((start>>20)==0xbfc||(start>>24)==0xa0))
2786 // return wrong, must use memhandler for BIOS self-test to pass
2787 // 007 does similar stuff from a00 mirror, weird stuff
2788 return MTYPE_8000;
2789 return MTYPE_0000;
2790 }
2791 if(0x1f800000 <= a && a < 0x1f801000)
2792 return MTYPE_1F80;
2793 if(0x80200000 <= a && a < 0x80800000)
2794 return MTYPE_8020;
2795 if(0xa0000000 <= a && a < 0xa0200000)
2796 return MTYPE_A000;
2797 return MTYPE_8000;
2798}
2799
37387d8b 2800static int get_ro_reg(const struct regstat *i_regs, int host_tempreg_free)
2801{
2802 int r = get_reg(i_regs->regmap, ROREG);
2803 if (r < 0 && host_tempreg_free) {
2804 host_tempreg_acquire();
2805 emit_loadreg(ROREG, r = HOST_TEMPREG);
2806 }
2807 if (r < 0)
2808 abort();
2809 return r;
2810}
2811
2812static void *emit_fastpath_cmp_jump(int i, const struct regstat *i_regs,
277718fa 2813 int addr, int *offset_reg, int *addr_reg_override, int ccadj_)
8062d65a 2814{
2815 void *jaddr = NULL;
37387d8b 2816 int type = 0;
2817 int mr = dops[i].rs1;
277718fa 2818 assert(addr >= 0);
37387d8b 2819 *offset_reg = -1;
8062d65a 2820 if(((smrv_strong|smrv_weak)>>mr)&1) {
2821 type=get_ptr_mem_type(smrv[mr]);
2822 //printf("set %08x @%08x r%d %d\n", smrv[mr], start+i*4, mr, type);
2823 }
2824 else {
2825 // use the mirror we are running on
2826 type=get_ptr_mem_type(start);
2827 //printf("set nospec @%08x r%d %d\n", start+i*4, mr, type);
2828 }
2829
277718fa 2830 if (dops[i].may_except) {
2831 // alignment check
2832 u_int op = dops[i].opcode;
2833 int mask = ((op & 0x37) == 0x21 || op == 0x25) ? 1 : 3; // LH/SH/LHU
33a1eda1 2834 void *jaddr2;
277718fa 2835 emit_testimm(addr, mask);
33a1eda1 2836 jaddr2 = out;
277718fa 2837 emit_jne(0);
33a1eda1 2838 add_stub_r(ALIGNMENT_STUB, jaddr2, out, i, addr, i_regs, ccadj_, 0);
277718fa 2839 }
2840
8062d65a 2841 if(type==MTYPE_8020) { // RAM 80200000+ mirror
d1e4ebd9 2842 host_tempreg_acquire();
8062d65a 2843 emit_andimm(addr,~0x00e00000,HOST_TEMPREG);
2844 addr=*addr_reg_override=HOST_TEMPREG;
2845 type=0;
2846 }
2847 else if(type==MTYPE_0000) { // RAM 0 mirror
d1e4ebd9 2848 host_tempreg_acquire();
8062d65a 2849 emit_orimm(addr,0x80000000,HOST_TEMPREG);
2850 addr=*addr_reg_override=HOST_TEMPREG;
2851 type=0;
2852 }
2853 else if(type==MTYPE_A000) { // RAM A mirror
d1e4ebd9 2854 host_tempreg_acquire();
8062d65a 2855 emit_andimm(addr,~0x20000000,HOST_TEMPREG);
2856 addr=*addr_reg_override=HOST_TEMPREG;
2857 type=0;
2858 }
2859 else if(type==MTYPE_1F80) { // scratchpad
2860 if (psxH == (void *)0x1f800000) {
d1e4ebd9 2861 host_tempreg_acquire();
3968e69e 2862 emit_xorimm(addr,0x1f800000,HOST_TEMPREG);
8062d65a 2863 emit_cmpimm(HOST_TEMPREG,0x1000);
d1e4ebd9 2864 host_tempreg_release();
8062d65a 2865 jaddr=out;
2866 emit_jc(0);
2867 }
2868 else {
2869 // do the usual RAM check, jump will go to the right handler
2870 type=0;
2871 }
2872 }
2873
37387d8b 2874 if (type == 0) // need ram check
8062d65a 2875 {
2876 emit_cmpimm(addr,RAM_SIZE);
37387d8b 2877 jaddr = out;
8062d65a 2878 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
2879 // Hint to branch predictor that the branch is unlikely to be taken
37387d8b 2880 if (dops[i].rs1 >= 28)
8062d65a 2881 emit_jno_unlikely(0);
2882 else
2883 #endif
2884 emit_jno(0);
37387d8b 2885 if (ram_offset != 0)
2886 *offset_reg = get_ro_reg(i_regs, 0);
8062d65a 2887 }
2888
2889 return jaddr;
2890}
2891
687b4580 2892// return memhandler, or get directly accessable address and return 0
2893static void *get_direct_memhandler(void *table, u_int addr,
2894 enum stub_type type, uintptr_t *addr_host)
2895{
c979e8c2 2896 uintptr_t msb = 1ull << (sizeof(uintptr_t)*8 - 1);
687b4580 2897 uintptr_t l1, l2 = 0;
2898 l1 = ((uintptr_t *)table)[addr>>12];
c979e8c2 2899 if (!(l1 & msb)) {
687b4580 2900 uintptr_t v = l1 << 1;
2901 *addr_host = v + addr;
2902 return NULL;
2903 }
2904 else {
2905 l1 <<= 1;
2906 if (type == LOADB_STUB || type == LOADBU_STUB || type == STOREB_STUB)
2907 l2 = ((uintptr_t *)l1)[0x1000/4 + 0x1000/2 + (addr&0xfff)];
2908 else if (type == LOADH_STUB || type == LOADHU_STUB || type == STOREH_STUB)
c979e8c2 2909 l2 = ((uintptr_t *)l1)[0x1000/4 + (addr&0xfff)/2];
687b4580 2910 else
c979e8c2 2911 l2 = ((uintptr_t *)l1)[(addr&0xfff)/4];
2912 if (!(l2 & msb)) {
687b4580 2913 uintptr_t v = l2 << 1;
2914 *addr_host = v + (addr&0xfff);
2915 return NULL;
2916 }
2917 return (void *)(l2 << 1);
2918 }
2919}
2920
81dbbf4c 2921static u_int get_host_reglist(const signed char *regmap)
2922{
2923 u_int reglist = 0, hr;
2924 for (hr = 0; hr < HOST_REGS; hr++) {
2925 if (hr != EXCLUDE_REG && regmap[hr] >= 0)
2926 reglist |= 1 << hr;
2927 }
2928 return reglist;
2929}
2930
2931static u_int reglist_exclude(u_int reglist, int r1, int r2)
2932{
2933 if (r1 >= 0)
2934 reglist &= ~(1u << r1);
2935 if (r2 >= 0)
2936 reglist &= ~(1u << r2);
2937 return reglist;
2938}
2939
e3c6bdb5 2940// find a temp caller-saved register not in reglist (so assumed to be free)
2941static int reglist_find_free(u_int reglist)
2942{
2943 u_int free_regs = ~reglist & CALLER_SAVE_REGS;
2944 if (free_regs == 0)
2945 return -1;
2946 return __builtin_ctz(free_regs);
2947}
2948
37387d8b 2949static void do_load_word(int a, int rt, int offset_reg)
2950{
2951 if (offset_reg >= 0)
2952 emit_ldr_dualindexed(offset_reg, a, rt);
2953 else
2954 emit_readword_indexed(0, a, rt);
2955}
2956
2957static void do_store_word(int a, int ofs, int rt, int offset_reg, int preseve_a)
2958{
2959 if (offset_reg < 0) {
2960 emit_writeword_indexed(rt, ofs, a);
2961 return;
2962 }
2963 if (ofs != 0)
2964 emit_addimm(a, ofs, a);
2965 emit_str_dualindexed(offset_reg, a, rt);
2966 if (ofs != 0 && preseve_a)
2967 emit_addimm(a, -ofs, a);
2968}
2969
2970static void do_store_hword(int a, int ofs, int rt, int offset_reg, int preseve_a)
2971{
2972 if (offset_reg < 0) {
2973 emit_writehword_indexed(rt, ofs, a);
2974 return;
2975 }
2976 if (ofs != 0)
2977 emit_addimm(a, ofs, a);
2978 emit_strh_dualindexed(offset_reg, a, rt);
2979 if (ofs != 0 && preseve_a)
2980 emit_addimm(a, -ofs, a);
2981}
2982
2983static void do_store_byte(int a, int rt, int offset_reg)
2984{
2985 if (offset_reg >= 0)
2986 emit_strb_dualindexed(offset_reg, a, rt);
2987 else
2988 emit_writebyte_indexed(rt, 0, a);
2989}
2990
2330734f 2991static void load_assemble(int i, const struct regstat *i_regs, int ccadj_)
57871462 2992{
277718fa 2993 int addr = cinfo[i].addr;
2994 int s,tl;
57871462 2995 int offset;
b14b6a8f 2996 void *jaddr=0;
5bf843dc 2997 int memtarget=0,c=0;
37387d8b 2998 int offset_reg = -1;
2999 int fastio_reg_override = -1;
81dbbf4c 3000 u_int reglist=get_host_reglist(i_regs->regmap);
a5cd72d0 3001 tl=get_reg_w(i_regs->regmap, dops[i].rt1);
cf95b4f0 3002 s=get_reg(i_regs->regmap,dops[i].rs1);
277718fa 3003 offset=cinfo[i].imm;
57871462 3004 if(i_regs->regmap[HOST_CCREG]==CCREG) reglist&=~(1<<HOST_CCREG);
3005 if(s>=0) {
3006 c=(i_regs->wasconst>>s)&1;
af4ee1fe 3007 if (c) {
3008 memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
af4ee1fe 3009 }
57871462 3010 }
57871462 3011 //printf("load_assemble: c=%d\n",c);
643aeae3 3012 //if(c) printf("load_assemble: const=%lx\n",(long)constmap[i][s]+offset);
a5cd72d0 3013 if(tl<0 && ((!c||(((u_int)constmap[i][s]+offset)>>16)==0x1f80) || dops[i].rt1==0)) {
5bf843dc 3014 // could be FIFO, must perform the read
f18c0f46 3015 // ||dummy read
5bf843dc 3016 assem_debug("(forced read)\n");
277718fa 3017 tl = get_reg_temp(i_regs->regmap); // may be == addr
5bf843dc 3018 assert(tl>=0);
5bf843dc 3019 }
277718fa 3020 assert(addr >= 0);
535d208a 3021 if(tl>=0) {
3022 //printf("load_assemble: c=%d\n",c);
643aeae3 3023 //if(c) printf("load_assemble: const=%lx\n",(long)constmap[i][s]+offset);
535d208a 3024 reglist&=~(1<<tl);
1edfcc68 3025 if(!c) {
1edfcc68 3026 #ifdef R29_HACK
3027 // Strmnnrmn's speed hack
cf95b4f0 3028 if(dops[i].rs1!=29||start<0x80001000||start>=0x80000000+RAM_SIZE)
1edfcc68 3029 #endif
3030 {
37387d8b 3031 jaddr = emit_fastpath_cmp_jump(i, i_regs, addr,
277718fa 3032 &offset_reg, &fastio_reg_override, ccadj_);
535d208a 3033 }
1edfcc68 3034 }
37387d8b 3035 else if (ram_offset && memtarget) {
3036 offset_reg = get_ro_reg(i_regs, 0);
535d208a 3037 }
a5cd72d0 3038 int dummy=(dops[i].rt1==0)||(tl!=get_reg_w(i_regs->regmap, dops[i].rt1)); // ignore loads to r0 and unneeded reg
37387d8b 3039 switch (dops[i].opcode) {
3040 case 0x20: // LB
535d208a 3041 if(!c||memtarget) {
3042 if(!dummy) {
277718fa 3043 int a = addr;
37387d8b 3044 if (fastio_reg_override >= 0)
3045 a = fastio_reg_override;
b1570849 3046
37387d8b 3047 if (offset_reg >= 0)
3048 emit_ldrsb_dualindexed(offset_reg, a, tl);
3049 else
3050 emit_movsbl_indexed(0, a, tl);
57871462 3051 }
535d208a 3052 if(jaddr)
2330734f 3053 add_stub_r(LOADB_STUB,jaddr,out,i,addr,i_regs,ccadj_,reglist);
57871462 3054 }
535d208a 3055 else
2330734f 3056 inline_readstub(LOADB_STUB,i,constmap[i][s]+offset,i_regs->regmap,dops[i].rt1,ccadj_,reglist);
37387d8b 3057 break;
3058 case 0x21: // LH
535d208a 3059 if(!c||memtarget) {
3060 if(!dummy) {
277718fa 3061 int a = addr;
37387d8b 3062 if (fastio_reg_override >= 0)
3063 a = fastio_reg_override;
3064 if (offset_reg >= 0)
3065 emit_ldrsh_dualindexed(offset_reg, a, tl);
3066 else
3067 emit_movswl_indexed(0, a, tl);
57871462 3068 }
535d208a 3069 if(jaddr)
2330734f 3070 add_stub_r(LOADH_STUB,jaddr,out,i,addr,i_regs,ccadj_,reglist);
57871462 3071 }
535d208a 3072 else
2330734f 3073 inline_readstub(LOADH_STUB,i,constmap[i][s]+offset,i_regs->regmap,dops[i].rt1,ccadj_,reglist);
37387d8b 3074 break;
3075 case 0x23: // LW
535d208a 3076 if(!c||memtarget) {
3077 if(!dummy) {
37387d8b 3078 int a = addr;
3079 if (fastio_reg_override >= 0)
3080 a = fastio_reg_override;
3081 do_load_word(a, tl, offset_reg);
57871462 3082 }
535d208a 3083 if(jaddr)
2330734f 3084 add_stub_r(LOADW_STUB,jaddr,out,i,addr,i_regs,ccadj_,reglist);
57871462 3085 }
535d208a 3086 else
2330734f 3087 inline_readstub(LOADW_STUB,i,constmap[i][s]+offset,i_regs->regmap,dops[i].rt1,ccadj_,reglist);
37387d8b 3088 break;
3089 case 0x24: // LBU
535d208a 3090 if(!c||memtarget) {
3091 if(!dummy) {
277718fa 3092 int a = addr;
37387d8b 3093 if (fastio_reg_override >= 0)
3094 a = fastio_reg_override;
b1570849 3095
37387d8b 3096 if (offset_reg >= 0)
3097 emit_ldrb_dualindexed(offset_reg, a, tl);
3098 else
3099 emit_movzbl_indexed(0, a, tl);
57871462 3100 }
535d208a 3101 if(jaddr)
2330734f 3102 add_stub_r(LOADBU_STUB,jaddr,out,i,addr,i_regs,ccadj_,reglist);
57871462 3103 }
535d208a 3104 else
2330734f 3105 inline_readstub(LOADBU_STUB,i,constmap[i][s]+offset,i_regs->regmap,dops[i].rt1,ccadj_,reglist);
37387d8b 3106 break;
3107 case 0x25: // LHU
535d208a 3108 if(!c||memtarget) {
3109 if(!dummy) {
277718fa 3110 int a = addr;
37387d8b 3111 if (fastio_reg_override >= 0)
3112 a = fastio_reg_override;
3113 if (offset_reg >= 0)
3114 emit_ldrh_dualindexed(offset_reg, a, tl);
3115 else
3116 emit_movzwl_indexed(0, a, tl);
57871462 3117 }
535d208a 3118 if(jaddr)
2330734f 3119 add_stub_r(LOADHU_STUB,jaddr,out,i,addr,i_regs,ccadj_,reglist);
57871462 3120 }
535d208a 3121 else
2330734f 3122 inline_readstub(LOADHU_STUB,i,constmap[i][s]+offset,i_regs->regmap,dops[i].rt1,ccadj_,reglist);
37387d8b 3123 break;
37387d8b 3124 default:
9c45ca93 3125 assert(0);
57871462 3126 }
a5cd72d0 3127 } // tl >= 0
37387d8b 3128 if (fastio_reg_override == HOST_TEMPREG || offset_reg == HOST_TEMPREG)
d1e4ebd9 3129 host_tempreg_release();
57871462 3130}
3131
3132#ifndef loadlr_assemble
2330734f 3133static void loadlr_assemble(int i, const struct regstat *i_regs, int ccadj_)
57871462 3134{
277718fa 3135 int addr = cinfo[i].addr;
3136 int s,tl,temp,temp2;
3968e69e 3137 int offset;
3138 void *jaddr=0;
3139 int memtarget=0,c=0;
37387d8b 3140 int offset_reg = -1;
3141 int fastio_reg_override = -1;
81dbbf4c 3142 u_int reglist=get_host_reglist(i_regs->regmap);
a5cd72d0 3143 tl=get_reg_w(i_regs->regmap, dops[i].rt1);
cf95b4f0 3144 s=get_reg(i_regs->regmap,dops[i].rs1);
9de8a0c3 3145 temp=get_reg_temp(i_regs->regmap);
3968e69e 3146 temp2=get_reg(i_regs->regmap,FTEMP);
277718fa 3147 offset=cinfo[i].imm;
3968e69e 3148 reglist|=1<<temp;
277718fa 3149 assert(addr >= 0);
3968e69e 3150 if(s>=0) {
3151 c=(i_regs->wasconst>>s)&1;
3152 if(c) {
3153 memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
3154 }
3155 }
3156 if(!c) {
3157 emit_shlimm(addr,3,temp);
cf95b4f0 3158 if (dops[i].opcode==0x22||dops[i].opcode==0x26) {
3968e69e 3159 emit_andimm(addr,0xFFFFFFFC,temp2); // LWL/LWR
3160 }else{
3161 emit_andimm(addr,0xFFFFFFF8,temp2); // LDL/LDR
3162 }
37387d8b 3163 jaddr = emit_fastpath_cmp_jump(i, i_regs, temp2,
277718fa 3164 &offset_reg, &fastio_reg_override, ccadj_);
3968e69e 3165 }
3166 else {
37387d8b 3167 if (ram_offset && memtarget) {
3168 offset_reg = get_ro_reg(i_regs, 0);
3968e69e 3169 }
cf95b4f0 3170 if (dops[i].opcode==0x22||dops[i].opcode==0x26) {
3968e69e 3171 emit_movimm(((constmap[i][s]+offset)<<3)&24,temp); // LWL/LWR
3172 }else{
3173 emit_movimm(((constmap[i][s]+offset)<<3)&56,temp); // LDL/LDR
3174 }
3175 }
cf95b4f0 3176 if (dops[i].opcode==0x22||dops[i].opcode==0x26) { // LWL/LWR
3968e69e 3177 if(!c||memtarget) {
37387d8b 3178 int a = temp2;
3179 if (fastio_reg_override >= 0)
3180 a = fastio_reg_override;
3181 do_load_word(a, temp2, offset_reg);
3182 if (fastio_reg_override == HOST_TEMPREG || offset_reg == HOST_TEMPREG)
3183 host_tempreg_release();
2330734f 3184 if(jaddr) add_stub_r(LOADW_STUB,jaddr,out,i,temp2,i_regs,ccadj_,reglist);
3968e69e 3185 }
3186 else
2330734f 3187 inline_readstub(LOADW_STUB,i,(constmap[i][s]+offset)&0xFFFFFFFC,i_regs->regmap,FTEMP,ccadj_,reglist);
cf95b4f0 3188 if(dops[i].rt1) {
3968e69e 3189 assert(tl>=0);
3190 emit_andimm(temp,24,temp);
cf95b4f0 3191 if (dops[i].opcode==0x22) // LWL
3968e69e 3192 emit_xorimm(temp,24,temp);
3193 host_tempreg_acquire();
3194 emit_movimm(-1,HOST_TEMPREG);
cf95b4f0 3195 if (dops[i].opcode==0x26) {
3968e69e 3196 emit_shr(temp2,temp,temp2);
3197 emit_bic_lsr(tl,HOST_TEMPREG,temp,tl);
3198 }else{
3199 emit_shl(temp2,temp,temp2);
3200 emit_bic_lsl(tl,HOST_TEMPREG,temp,tl);
3201 }
3202 host_tempreg_release();
3203 emit_or(temp2,tl,tl);
3204 }
cf95b4f0 3205 //emit_storereg(dops[i].rt1,tl); // DEBUG
3968e69e 3206 }
cf95b4f0 3207 if (dops[i].opcode==0x1A||dops[i].opcode==0x1B) { // LDL/LDR
3968e69e 3208 assert(0);
3209 }
57871462 3210}
3211#endif
3212
9b495f6e 3213static void do_invstub(int n)
3214{
3215 literal_pool(20);
684b6816 3216 assem_debug("do_invstub %x\n", start + stubs[n].e*4);
9b495f6e 3217 u_int reglist = stubs[n].a;
3218 u_int addrr = stubs[n].b;
3219 int ofs_start = stubs[n].c;
3220 int ofs_end = stubs[n].d;
3221 int len = ofs_end - ofs_start;
3222 u_int rightr = 0;
3223
3224 set_jump_target(stubs[n].addr, out);
3225 save_regs(reglist);
9b495f6e 3226 if (addrr != 0 || ofs_start != 0)
3227 emit_addimm(addrr, ofs_start, 0);
3033d898 3228 emit_readword(&inv_code_start, 2);
3229 emit_readword(&inv_code_end, 3);
9b495f6e 3230 if (len != 0)
3231 emit_addimm(0, len + 4, (rightr = 1));
3232 emit_cmp(0, 2);
3233 emit_cmpcs(3, rightr);
3234 void *jaddr = out;
3235 emit_jc(0);
3236 void *func = (len != 0)
3237 ? (void *)ndrc_write_invalidate_many
3238 : (void *)ndrc_write_invalidate_one;
3239 emit_far_call(func);
3240 set_jump_target(jaddr, out);
3241 restore_regs(reglist);
3242 emit_jmp(stubs[n].retaddr);
3243}
3244
3245static void do_store_smc_check(int i, const struct regstat *i_regs, u_int reglist, int addr)
3246{
3247 if (HACK_ENABLED(NDHACK_NO_SMC_CHECK))
3248 return;
3249 // this can't be used any more since we started to check exact
3250 // block boundaries in invalidate_range()
3251 //if (i_regs->waswritten & (1<<dops[i].rs1))
3252 // return;
3253 // (naively) assume nobody will run code from stack
3254 if (dops[i].rs1 == 29)
3255 return;
3256
277718fa 3257 int j, imm_maxdiff = 32, imm_min = cinfo[i].imm, imm_max = cinfo[i].imm, count = 1;
9b495f6e 3258 if (i < slen - 1 && dops[i+1].is_store && dops[i+1].rs1 == dops[i].rs1
277718fa 3259 && abs(cinfo[i+1].imm - cinfo[i].imm) <= imm_maxdiff)
9b495f6e 3260 return;
3261 for (j = i - 1; j >= 0; j--) {
3262 if (!dops[j].is_store || dops[j].rs1 != dops[i].rs1
277718fa 3263 || abs(cinfo[j].imm - cinfo[j+1].imm) > imm_maxdiff)
9b495f6e 3264 break;
3265 count++;
277718fa 3266 if (imm_min > cinfo[j].imm)
3267 imm_min = cinfo[j].imm;
3268 if (imm_max < cinfo[j].imm)
3269 imm_max = cinfo[j].imm;
9b495f6e 3270 }
3271#if defined(HOST_IMM8)
3272 int ir = get_reg(i_regs->regmap, INVCP);
3273 assert(ir >= 0);
3274 host_tempreg_acquire();
3275 emit_ldrb_indexedsr12_reg(ir, addr, HOST_TEMPREG);
3276#else
3277 emit_cmpmem_indexedsr12_imm(invalid_code, addr, 1);
3278 #error not handled
3279#endif
3280#ifdef INVALIDATE_USE_COND_CALL
3281 if (count == 1) {
3282 emit_cmpimm(HOST_TEMPREG, 1);
3283 emit_callne(invalidate_addr_reg[addr]);
3284 host_tempreg_release();
3285 return;
3286 }
3287#endif
3288 void *jaddr = emit_cbz(HOST_TEMPREG, 0);
3289 host_tempreg_release();
277718fa 3290 imm_min -= cinfo[i].imm;
3291 imm_max -= cinfo[i].imm;
9b495f6e 3292 add_stub(INVCODE_STUB, jaddr, out, reglist|(1<<HOST_CCREG),
684b6816 3293 addr, imm_min, imm_max, i);
9b495f6e 3294}
3295
684b6816 3296// determines if code overwrite checking is needed only
3297// (also true non-existent 0x20000000 mirror that shouldn't matter)
3298#define is_ram_addr(a) !((a) & 0x5f800000)
3299
2330734f 3300static void store_assemble(int i, const struct regstat *i_regs, int ccadj_)
57871462 3301{
9c45ca93 3302 int s,tl;
277718fa 3303 int addr = cinfo[i].addr;
57871462 3304 int offset;
b14b6a8f 3305 void *jaddr=0;
37387d8b 3306 enum stub_type type=0;
666a299d 3307 int memtarget=0,c=0;
37387d8b 3308 int offset_reg = -1;
3309 int fastio_reg_override = -1;
684b6816 3310 u_int addr_const = ~0;
81dbbf4c 3311 u_int reglist=get_host_reglist(i_regs->regmap);
cf95b4f0 3312 tl=get_reg(i_regs->regmap,dops[i].rs2);
3313 s=get_reg(i_regs->regmap,dops[i].rs1);
277718fa 3314 offset=cinfo[i].imm;
57871462 3315 if(s>=0) {
3316 c=(i_regs->wasconst>>s)&1;
684b6816 3317 if (c) {
3318 addr_const = constmap[i][s] + offset;
3319 memtarget = ((signed int)addr_const) < (signed int)(0x80000000 + RAM_SIZE);
af4ee1fe 3320 }
57871462 3321 }
3322 assert(tl>=0);
277718fa 3323 assert(addr >= 0);
57871462 3324 if(i_regs->regmap[HOST_CCREG]==CCREG) reglist&=~(1<<HOST_CCREG);
684b6816 3325 reglist |= 1u << addr;
37387d8b 3326 if (!c) {
3327 jaddr = emit_fastpath_cmp_jump(i, i_regs, addr,
277718fa 3328 &offset_reg, &fastio_reg_override, ccadj_);
1edfcc68 3329 }
37387d8b 3330 else if (ram_offset && memtarget) {
3331 offset_reg = get_ro_reg(i_regs, 0);
57871462 3332 }
3333
37387d8b 3334 switch (dops[i].opcode) {
3335 case 0x28: // SB
57871462 3336 if(!c||memtarget) {
277718fa 3337 int a = addr;
37387d8b 3338 if (fastio_reg_override >= 0)
3339 a = fastio_reg_override;
3340 do_store_byte(a, tl, offset_reg);
3341 }
3342 type = STOREB_STUB;
3343 break;
3344 case 0x29: // SH
57871462 3345 if(!c||memtarget) {
277718fa 3346 int a = addr;
37387d8b 3347 if (fastio_reg_override >= 0)
3348 a = fastio_reg_override;
3349 do_store_hword(a, 0, tl, offset_reg, 1);
3350 }
3351 type = STOREH_STUB;
3352 break;
3353 case 0x2B: // SW
dadf55f2 3354 if(!c||memtarget) {
37387d8b 3355 int a = addr;
3356 if (fastio_reg_override >= 0)
3357 a = fastio_reg_override;
3358 do_store_word(a, 0, tl, offset_reg, 1);
3359 }
3360 type = STOREW_STUB;
3361 break;
37387d8b 3362 default:
9c45ca93 3363 assert(0);
57871462 3364 }
37387d8b 3365 if (fastio_reg_override == HOST_TEMPREG || offset_reg == HOST_TEMPREG)
d1e4ebd9 3366 host_tempreg_release();
684b6816 3367 if (jaddr) {
b96d3df7 3368 // PCSX store handlers don't check invcode again
2330734f 3369 add_stub_r(type,jaddr,out,i,addr,i_regs,ccadj_,reglist);
7a518516 3370 }
684b6816 3371 if (!c || is_ram_addr(addr_const))
3372 do_store_smc_check(i, i_regs, reglist, addr);
3373 if (c && !memtarget)
3374 inline_writestub(type, i, addr_const, i_regs->regmap, dops[i].rs2, ccadj_, reglist);
7a518516 3375 // basic current block modification detection..
3376 // not looking back as that should be in mips cache already
3968e69e 3377 // (see Spyro2 title->attract mode)
684b6816 3378 if (start + i*4 < addr_const && addr_const < start + slen*4) {
3379 SysPrintf("write to %08x hits block %08x, pc=%08x\n", addr_const, start, start+i*4);
7a518516 3380 assert(i_regs->regmap==regs[i].regmap); // not delay slot
3381 if(i_regs->regmap==regs[i].regmap) {
ad49de89 3382 load_all_consts(regs[i].regmap_entry,regs[i].wasdirty,i);
3383 wb_dirtys(regs[i].regmap_entry,regs[i].wasdirty);
7a518516 3384 emit_movimm(start+i*4+4,0);
643aeae3 3385 emit_writeword(0,&pcaddr);
d1e4ebd9 3386 emit_addimm(HOST_CCREG,2,HOST_CCREG);
104df9d3 3387 emit_far_call(ndrc_get_addr_ht);
d1e4ebd9 3388 emit_jmpreg(0);
7a518516 3389 }
3eaa7048 3390 }
57871462 3391}
3392
2330734f 3393static void storelr_assemble(int i, const struct regstat *i_regs, int ccadj_)
57871462 3394{
277718fa 3395 int addr = cinfo[i].addr;
9c45ca93 3396 int s,tl;
57871462 3397 int offset;
b14b6a8f 3398 void *jaddr=0;
37387d8b 3399 void *case1, *case23, *case3;
df4dc2b1 3400 void *done0, *done1, *done2;
af4ee1fe 3401 int memtarget=0,c=0;
37387d8b 3402 int offset_reg = -1;
684b6816 3403 u_int addr_const = ~0;
3404 u_int reglist = get_host_reglist(i_regs->regmap);
cf95b4f0 3405 tl=get_reg(i_regs->regmap,dops[i].rs2);
3406 s=get_reg(i_regs->regmap,dops[i].rs1);
277718fa 3407 offset=cinfo[i].imm;
57871462 3408 if(s>=0) {
684b6816 3409 c = (i_regs->isconst >> s) & 1;
3410 if (c) {
3411 addr_const = constmap[i][s] + offset;
3412 memtarget = ((signed int)addr_const) < (signed int)(0x80000000 + RAM_SIZE);
af4ee1fe 3413 }
57871462 3414 }
3415 assert(tl>=0);
277718fa 3416 assert(addr >= 0);
684b6816 3417 reglist |= 1u << addr;
1edfcc68 3418 if(!c) {
277718fa 3419 emit_cmpimm(addr, RAM_SIZE);
b14b6a8f 3420 jaddr=out;
1edfcc68 3421 emit_jno(0);
3422 }
3423 else
3424 {
cf95b4f0 3425 if(!memtarget||!dops[i].rs1) {
b14b6a8f 3426 jaddr=out;
535d208a 3427 emit_jmp(0);
57871462 3428 }
535d208a 3429 }
37387d8b 3430 if (ram_offset)
3431 offset_reg = get_ro_reg(i_regs, 0);
535d208a 3432
277718fa 3433 emit_testimm(addr,2);
37387d8b 3434 case23=out;
535d208a 3435 emit_jne(0);
277718fa 3436 emit_testimm(addr,1);
df4dc2b1 3437 case1=out;
535d208a 3438 emit_jne(0);
3439 // 0
37387d8b 3440 if (dops[i].opcode == 0x2A) { // SWL
3441 // Write msb into least significant byte
3442 if (dops[i].rs2) emit_rorimm(tl, 24, tl);
277718fa 3443 do_store_byte(addr, tl, offset_reg);
37387d8b 3444 if (dops[i].rs2) emit_rorimm(tl, 8, tl);
535d208a 3445 }
37387d8b 3446 else if (dops[i].opcode == 0x2E) { // SWR
3447 // Write entire word
277718fa 3448 do_store_word(addr, 0, tl, offset_reg, 1);
535d208a 3449 }
37387d8b 3450 done0 = out;
535d208a 3451 emit_jmp(0);
3452 // 1
df4dc2b1 3453 set_jump_target(case1, out);
37387d8b 3454 if (dops[i].opcode == 0x2A) { // SWL
3455 // Write two msb into two least significant bytes
3456 if (dops[i].rs2) emit_rorimm(tl, 16, tl);
684b6816 3457 do_store_hword(addr, -1, tl, offset_reg, 1);
37387d8b 3458 if (dops[i].rs2) emit_rorimm(tl, 16, tl);
535d208a 3459 }
37387d8b 3460 else if (dops[i].opcode == 0x2E) { // SWR
3461 // Write 3 lsb into three most significant bytes
277718fa 3462 do_store_byte(addr, tl, offset_reg);
37387d8b 3463 if (dops[i].rs2) emit_rorimm(tl, 8, tl);
684b6816 3464 do_store_hword(addr, 1, tl, offset_reg, 1);
37387d8b 3465 if (dops[i].rs2) emit_rorimm(tl, 24, tl);
535d208a 3466 }
df4dc2b1 3467 done1=out;
535d208a 3468 emit_jmp(0);
37387d8b 3469 // 2,3
3470 set_jump_target(case23, out);
277718fa 3471 emit_testimm(addr,1);
37387d8b 3472 case3 = out;
535d208a 3473 emit_jne(0);
37387d8b 3474 // 2
cf95b4f0 3475 if (dops[i].opcode==0x2A) { // SWL
37387d8b 3476 // Write 3 msb into three least significant bytes
3477 if (dops[i].rs2) emit_rorimm(tl, 8, tl);
277718fa 3478 do_store_hword(addr, -2, tl, offset_reg, 1);
37387d8b 3479 if (dops[i].rs2) emit_rorimm(tl, 16, tl);
277718fa 3480 do_store_byte(addr, tl, offset_reg);
37387d8b 3481 if (dops[i].rs2) emit_rorimm(tl, 8, tl);
535d208a 3482 }
37387d8b 3483 else if (dops[i].opcode == 0x2E) { // SWR
3484 // Write two lsb into two most significant bytes
277718fa 3485 do_store_hword(addr, 0, tl, offset_reg, 1);
535d208a 3486 }
37387d8b 3487 done2 = out;
535d208a 3488 emit_jmp(0);
3489 // 3
df4dc2b1 3490 set_jump_target(case3, out);
37387d8b 3491 if (dops[i].opcode == 0x2A) { // SWL
684b6816 3492 do_store_word(addr, -3, tl, offset_reg, 1);
535d208a 3493 }
37387d8b 3494 else if (dops[i].opcode == 0x2E) { // SWR
277718fa 3495 do_store_byte(addr, tl, offset_reg);
535d208a 3496 }
df4dc2b1 3497 set_jump_target(done0, out);
3498 set_jump_target(done1, out);
3499 set_jump_target(done2, out);
37387d8b 3500 if (offset_reg == HOST_TEMPREG)
3501 host_tempreg_release();
684b6816 3502 if (!c || !memtarget)
277718fa 3503 add_stub_r(STORELR_STUB,jaddr,out,i,addr,i_regs,ccadj_,reglist);
684b6816 3504 if (!c || is_ram_addr(addr_const))
3505 do_store_smc_check(i, i_regs, reglist, addr);
57871462 3506}
3507
2330734f 3508static void cop0_assemble(int i, const struct regstat *i_regs, int ccadj_)
8062d65a 3509{
cf95b4f0 3510 if(dops[i].opcode2==0) // MFC0
8062d65a 3511 {
a5cd72d0 3512 signed char t=get_reg_w(i_regs->regmap, dops[i].rt1);
8062d65a 3513 u_int copr=(source[i]>>11)&0x1f;
cf95b4f0 3514 if(t>=0&&dops[i].rt1!=0) {
8062d65a 3515 emit_readword(&reg_cop0[copr],t);
3516 }
3517 }
cf95b4f0 3518 else if(dops[i].opcode2==4) // MTC0
8062d65a 3519 {
de6dbc52 3520 int s = get_reg(i_regs->regmap, dops[i].rs1);
3521 int cc = get_reg(i_regs->regmap, CCREG);
8062d65a 3522 char copr=(source[i]>>11)&0x1f;
3523 assert(s>=0);
cf95b4f0 3524 wb_register(dops[i].rs1,i_regs->regmap,i_regs->dirty);
de6dbc52 3525 if (copr == 12 || copr == 13) {
8062d65a 3526 emit_readword(&last_count,HOST_TEMPREG);
de6dbc52 3527 if (cc != HOST_CCREG)
3528 emit_loadreg(CCREG, HOST_CCREG);
3529 emit_add(HOST_CCREG, HOST_TEMPREG, HOST_CCREG);
3530 emit_addimm(HOST_CCREG, ccadj_ + 2, HOST_CCREG);
3531 emit_writeword(HOST_CCREG, &psxRegs.cycle);
8062d65a 3532 if (is_delayslot) {
3533 // burn cycles to cause cc_interrupt, which will
3534 // reschedule next_interupt. Relies on CCREG from above.
3535 assem_debug("MTC0 DS %d\n", copr);
3536 emit_writeword(HOST_CCREG,&last_count);
3537 emit_movimm(0,HOST_CCREG);
3538 emit_storereg(CCREG,HOST_CCREG);
cf95b4f0 3539 emit_loadreg(dops[i].rs1,1);
8062d65a 3540 emit_movimm(copr,0);
2a014d73 3541 emit_far_call(pcsx_mtc0_ds);
cf95b4f0 3542 emit_loadreg(dops[i].rs1,s);
8062d65a 3543 return;
3544 }
3545 emit_movimm(start+i*4+4,HOST_TEMPREG);
3546 emit_writeword(HOST_TEMPREG,&pcaddr);
3547 emit_movimm(0,HOST_TEMPREG);
3548 emit_writeword(HOST_TEMPREG,&pending_exception);
3549 }
de6dbc52 3550 if( s != 1)
3551 emit_mov(s, 1);
3552 emit_movimm(copr, 0);
2a014d73 3553 emit_far_call(pcsx_mtc0);
de6dbc52 3554 if (copr == 12 || copr == 13) {
d7546062 3555 emit_readword(&psxRegs.cycle,HOST_CCREG);
de6dbc52 3556 emit_readword(&last_count,HOST_TEMPREG);
8062d65a 3557 emit_sub(HOST_CCREG,HOST_TEMPREG,HOST_CCREG);
de6dbc52 3558 //emit_writeword(HOST_TEMPREG,&last_count);
8062d65a 3559 assert(!is_delayslot);
9b495f6e 3560 emit_readword(&pending_exception,HOST_TEMPREG);
3561 emit_test(HOST_TEMPREG,HOST_TEMPREG);
d1e4ebd9 3562 void *jaddr = out;
3563 emit_jeq(0);
3564 emit_readword(&pcaddr, 0);
104df9d3 3565 emit_far_call(ndrc_get_addr_ht);
d1e4ebd9 3566 emit_jmpreg(0);
3567 set_jump_target(jaddr, out);
de6dbc52 3568 emit_addimm(HOST_CCREG, -ccadj_ - 2, HOST_CCREG);
3569 if (cc != HOST_CCREG)
3570 emit_storereg(CCREG, HOST_CCREG);
8062d65a 3571 }
cf95b4f0 3572 emit_loadreg(dops[i].rs1,s);
8062d65a 3573 }
8062d65a 3574}
3575
277718fa 3576static void rfe_assemble(int i, const struct regstat *i_regs)
8062d65a 3577{
a5cd72d0 3578 emit_readword(&psxRegs.CP0.n.SR, 0);
3579 emit_andimm(0, 0x3c, 1);
3580 emit_andimm(0, ~0xf, 0);
3581 emit_orrshr_imm(1, 2, 0);
3582 emit_writeword(0, &psxRegs.CP0.n.SR);
8062d65a 3583}
3584
e3c6bdb5 3585static int cop2_is_stalling_op(int i, int *cycles)
3586{
cf95b4f0 3587 if (dops[i].opcode == 0x3a) { // SWC2
e3c6bdb5 3588 *cycles = 0;
3589 return 1;
3590 }
cf95b4f0 3591 if (dops[i].itype == COP2 && (dops[i].opcode2 == 0 || dops[i].opcode2 == 2)) { // MFC2/CFC2
e3c6bdb5 3592 *cycles = 0;
3593 return 1;
3594 }
cf95b4f0 3595 if (dops[i].itype == C2OP) {
e3c6bdb5 3596 *cycles = gte_cycletab[source[i] & 0x3f];
3597 return 1;
3598 }
3599 // ... what about MTC2/CTC2/LWC2?
3600 return 0;
3601}
3602
3603#if 0
3604static void log_gte_stall(int stall, u_int cycle)
3605{
3606 if ((u_int)stall <= 44)
3607 printf("x stall %2d %u\n", stall, cycle + last_count);
e3c6bdb5 3608}
3609
3610static void emit_log_gte_stall(int i, int stall, u_int reglist)
3611{
3612 save_regs(reglist);
3613 if (stall > 0)
3614 emit_movimm(stall, 0);
3615 else
3616 emit_mov(HOST_TEMPREG, 0);
277718fa 3617 emit_addimm(HOST_CCREG, cinfo[i].ccadj, 1);
e3c6bdb5 3618 emit_far_call(log_gte_stall);
3619 restore_regs(reglist);
3620}
3621#endif
3622
32631e6a 3623static void cop2_do_stall_check(u_int op, int i, const struct regstat *i_regs, u_int reglist)
81dbbf4c 3624{
e3c6bdb5 3625 int j = i, other_gte_op_cycles = -1, stall = -MAXBLOCK, cycles_passed;
3626 int rtmp = reglist_find_free(reglist);
3627
32631e6a 3628 if (HACK_ENABLED(NDHACK_NO_STALLS))
81dbbf4c 3629 return;
81dbbf4c 3630 if (get_reg(i_regs->regmap, CCREG) != HOST_CCREG) {
3631 // happens occasionally... cc evicted? Don't bother then
3632 //printf("no cc %08x\n", start + i*4);
3633 return;
3634 }
cf95b4f0 3635 if (!dops[i].bt) {
e3c6bdb5 3636 for (j = i - 1; j >= 0; j--) {
cf95b4f0 3637 //if (dops[j].is_ds) break;
3638 if (cop2_is_stalling_op(j, &other_gte_op_cycles) || dops[j].bt)
e3c6bdb5 3639 break;
277718fa 3640 if (j > 0 && cinfo[j - 1].ccadj > cinfo[j].ccadj)
2330734f 3641 break;
e3c6bdb5 3642 }
32631e6a 3643 j = max(j, 0);
e3c6bdb5 3644 }
277718fa 3645 cycles_passed = cinfo[i].ccadj - cinfo[j].ccadj;
e3c6bdb5 3646 if (other_gte_op_cycles >= 0)
3647 stall = other_gte_op_cycles - cycles_passed;
3648 else if (cycles_passed >= 44)
3649 stall = 0; // can't stall
3650 if (stall == -MAXBLOCK && rtmp >= 0) {
3651 // unknown stall, do the expensive runtime check
32631e6a 3652 assem_debug("; cop2_do_stall_check\n");
e3c6bdb5 3653#if 0 // too slow
3654 save_regs(reglist);
3655 emit_movimm(gte_cycletab[op], 0);
277718fa 3656 emit_addimm(HOST_CCREG, cinfo[i].ccadj, 1);
e3c6bdb5 3657 emit_far_call(call_gteStall);
3658 restore_regs(reglist);
3659#else
3660 host_tempreg_acquire();
3661 emit_readword(&psxRegs.gteBusyCycle, rtmp);
277718fa 3662 emit_addimm(rtmp, -cinfo[i].ccadj, rtmp);
e3c6bdb5 3663 emit_sub(rtmp, HOST_CCREG, HOST_TEMPREG);
3664 emit_cmpimm(HOST_TEMPREG, 44);
3665 emit_cmovb_reg(rtmp, HOST_CCREG);
3666 //emit_log_gte_stall(i, 0, reglist);
3667 host_tempreg_release();
3668#endif
3669 }
3670 else if (stall > 0) {
3671 //emit_log_gte_stall(i, stall, reglist);
3672 emit_addimm(HOST_CCREG, stall, HOST_CCREG);
3673 }
3674
3675 // save gteBusyCycle, if needed
3676 if (gte_cycletab[op] == 0)
3677 return;
3678 other_gte_op_cycles = -1;
3679 for (j = i + 1; j < slen; j++) {
3680 if (cop2_is_stalling_op(j, &other_gte_op_cycles))
3681 break;
fe807a8a 3682 if (dops[j].is_jump) {
e3c6bdb5 3683 // check ds
3684 if (j + 1 < slen && cop2_is_stalling_op(j + 1, &other_gte_op_cycles))
3685 j++;
3686 break;
3687 }
3688 }
3689 if (other_gte_op_cycles >= 0)
3690 // will handle stall when assembling that op
3691 return;
277718fa 3692 cycles_passed = cinfo[min(j, slen -1)].ccadj - cinfo[i].ccadj;
e3c6bdb5 3693 if (cycles_passed >= 44)
3694 return;
3695 assem_debug("; save gteBusyCycle\n");
3696 host_tempreg_acquire();
3697#if 0
3698 emit_readword(&last_count, HOST_TEMPREG);
3699 emit_add(HOST_TEMPREG, HOST_CCREG, HOST_TEMPREG);
277718fa 3700 emit_addimm(HOST_TEMPREG, cinfo[i].ccadj, HOST_TEMPREG);
e3c6bdb5 3701 emit_addimm(HOST_TEMPREG, gte_cycletab[op]), HOST_TEMPREG);
3702 emit_writeword(HOST_TEMPREG, &psxRegs.gteBusyCycle);
3703#else
277718fa 3704 emit_addimm(HOST_CCREG, cinfo[i].ccadj + gte_cycletab[op], HOST_TEMPREG);
e3c6bdb5 3705 emit_writeword(HOST_TEMPREG, &psxRegs.gteBusyCycle);
3706#endif
3707 host_tempreg_release();
81dbbf4c 3708}
3709
32631e6a 3710static int is_mflohi(int i)
3711{
cf95b4f0 3712 return (dops[i].itype == MOV && (dops[i].rs1 == HIREG || dops[i].rs1 == LOREG));
32631e6a 3713}
3714
3715static int check_multdiv(int i, int *cycles)
3716{
cf95b4f0 3717 if (dops[i].itype != MULTDIV)
32631e6a 3718 return 0;
cf95b4f0 3719 if (dops[i].opcode2 == 0x18 || dops[i].opcode2 == 0x19) // MULT(U)
32631e6a 3720 *cycles = 11; // approx from 7 11 14
3721 else
3722 *cycles = 37;
3723 return 1;
3724}
3725
2330734f 3726static void multdiv_prepare_stall(int i, const struct regstat *i_regs, int ccadj_)
32631e6a 3727{
3728 int j, found = 0, c = 0;
3729 if (HACK_ENABLED(NDHACK_NO_STALLS))
3730 return;
3731 if (get_reg(i_regs->regmap, CCREG) != HOST_CCREG) {
3732 // happens occasionally... cc evicted? Don't bother then
3733 return;
3734 }
3735 for (j = i + 1; j < slen; j++) {
cf95b4f0 3736 if (dops[j].bt)
32631e6a 3737 break;
3738 if ((found = is_mflohi(j)))
3739 break;
fe807a8a 3740 if (dops[j].is_jump) {
32631e6a 3741 // check ds
3742 if (j + 1 < slen && (found = is_mflohi(j + 1)))
3743 j++;
3744 break;
3745 }
3746 }
3747 if (found)
3748 // handle all in multdiv_do_stall()
3749 return;
3750 check_multdiv(i, &c);
3751 assert(c > 0);
3752 assem_debug("; muldiv prepare stall %d\n", c);
3753 host_tempreg_acquire();
2330734f 3754 emit_addimm(HOST_CCREG, ccadj_ + c, HOST_TEMPREG);
32631e6a 3755 emit_writeword(HOST_TEMPREG, &psxRegs.muldivBusyCycle);
3756 host_tempreg_release();
3757}
3758
3759static void multdiv_do_stall(int i, const struct regstat *i_regs)
3760{
3761 int j, known_cycles = 0;
3762 u_int reglist = get_host_reglist(i_regs->regmap);
9de8a0c3 3763 int rtmp = get_reg_temp(i_regs->regmap);
32631e6a 3764 if (rtmp < 0)
3765 rtmp = reglist_find_free(reglist);
3766 if (HACK_ENABLED(NDHACK_NO_STALLS))
3767 return;
3768 if (get_reg(i_regs->regmap, CCREG) != HOST_CCREG || rtmp < 0) {
3769 // happens occasionally... cc evicted? Don't bother then
3770 //printf("no cc/rtmp %08x\n", start + i*4);
3771 return;
3772 }
cf95b4f0 3773 if (!dops[i].bt) {
32631e6a 3774 for (j = i - 1; j >= 0; j--) {
cf95b4f0 3775 if (dops[j].is_ds) break;
2330734f 3776 if (check_multdiv(j, &known_cycles))
32631e6a 3777 break;
3778 if (is_mflohi(j))
3779 // already handled by this op
3780 return;
277718fa 3781 if (dops[j].bt || (j > 0 && cinfo[j - 1].ccadj > cinfo[j].ccadj))
2330734f 3782 break;
32631e6a 3783 }
3784 j = max(j, 0);
3785 }
3786 if (known_cycles > 0) {
277718fa 3787 known_cycles -= cinfo[i].ccadj - cinfo[j].ccadj;
32631e6a 3788 assem_debug("; muldiv stall resolved %d\n", known_cycles);
3789 if (known_cycles > 0)
3790 emit_addimm(HOST_CCREG, known_cycles, HOST_CCREG);
3791 return;
3792 }
3793 assem_debug("; muldiv stall unresolved\n");
3794 host_tempreg_acquire();
3795 emit_readword(&psxRegs.muldivBusyCycle, rtmp);
277718fa 3796 emit_addimm(rtmp, -cinfo[i].ccadj, rtmp);
32631e6a 3797 emit_sub(rtmp, HOST_CCREG, HOST_TEMPREG);
3798 emit_cmpimm(HOST_TEMPREG, 37);
3799 emit_cmovb_reg(rtmp, HOST_CCREG);
3800 //emit_log_gte_stall(i, 0, reglist);
3801 host_tempreg_release();
3802}
3803
8062d65a 3804static void cop2_get_dreg(u_int copr,signed char tl,signed char temp)
3805{
3806 switch (copr) {
3807 case 1:
3808 case 3:
3809 case 5:
3810 case 8:
3811 case 9:
3812 case 10:
3813 case 11:
3814 emit_readword(&reg_cop2d[copr],tl);
3815 emit_signextend16(tl,tl);
3816 emit_writeword(tl,&reg_cop2d[copr]); // hmh
3817 break;
3818 case 7:
3819 case 16:
3820 case 17:
3821 case 18:
3822 case 19:
3823 emit_readword(&reg_cop2d[copr],tl);
3824 emit_andimm(tl,0xffff,tl);
3825 emit_writeword(tl,&reg_cop2d[copr]);
3826 break;
3827 case 15:
3828 emit_readword(&reg_cop2d[14],tl); // SXY2
3829 emit_writeword(tl,&reg_cop2d[copr]);
3830 break;
3831 case 28:
3832 case 29:
3968e69e 3833 c2op_mfc2_29_assemble(tl,temp);
8062d65a 3834 break;
3835 default:
3836 emit_readword(&reg_cop2d[copr],tl);
3837 break;
3838 }
3839}
3840
3841static void cop2_put_dreg(u_int copr,signed char sl,signed char temp)
3842{
3843 switch (copr) {
3844 case 15:
3845 emit_readword(&reg_cop2d[13],temp); // SXY1
3846 emit_writeword(sl,&reg_cop2d[copr]);
3847 emit_writeword(temp,&reg_cop2d[12]); // SXY0
3848 emit_readword(&reg_cop2d[14],temp); // SXY2
3849 emit_writeword(sl,&reg_cop2d[14]);
3850 emit_writeword(temp,&reg_cop2d[13]); // SXY1
3851 break;
3852 case 28:
3853 emit_andimm(sl,0x001f,temp);
3854 emit_shlimm(temp,7,temp);
3855 emit_writeword(temp,&reg_cop2d[9]);
3856 emit_andimm(sl,0x03e0,temp);
3857 emit_shlimm(temp,2,temp);
3858 emit_writeword(temp,&reg_cop2d[10]);
3859 emit_andimm(sl,0x7c00,temp);
3860 emit_shrimm(temp,3,temp);
3861 emit_writeword(temp,&reg_cop2d[11]);
3862 emit_writeword(sl,&reg_cop2d[28]);
3863 break;
3864 case 30:
3968e69e 3865 emit_xorsar_imm(sl,sl,31,temp);
be516ebe 3866#if defined(HAVE_ARMV5) || defined(__aarch64__)
8062d65a 3867 emit_clz(temp,temp);
3868#else
3869 emit_movs(temp,HOST_TEMPREG);
3870 emit_movimm(0,temp);
3871 emit_jeq((int)out+4*4);
3872 emit_addpl_imm(temp,1,temp);
3873 emit_lslpls_imm(HOST_TEMPREG,1,HOST_TEMPREG);
3874 emit_jns((int)out-2*4);
3875#endif
3876 emit_writeword(sl,&reg_cop2d[30]);
3877 emit_writeword(temp,&reg_cop2d[31]);
3878 break;
3879 case 31:
3880 break;
3881 default:
3882 emit_writeword(sl,&reg_cop2d[copr]);
3883 break;
3884 }
3885}
3886
2330734f 3887static void c2ls_assemble(int i, const struct regstat *i_regs, int ccadj_)
b9b61529 3888{
3889 int s,tl;
3890 int ar;
3891 int offset;
1fd1aceb 3892 int memtarget=0,c=0;
b14b6a8f 3893 void *jaddr2=NULL;
3894 enum stub_type type;
37387d8b 3895 int offset_reg = -1;
3896 int fastio_reg_override = -1;
684b6816 3897 u_int addr_const = ~0;
81dbbf4c 3898 u_int reglist=get_host_reglist(i_regs->regmap);
b9b61529 3899 u_int copr=(source[i]>>16)&0x1f;
cf95b4f0 3900 s=get_reg(i_regs->regmap,dops[i].rs1);
b9b61529 3901 tl=get_reg(i_regs->regmap,FTEMP);
277718fa 3902 offset=cinfo[i].imm;
b9b61529 3903 assert(tl>=0);
b9b61529 3904
b9b61529 3905 if(i_regs->regmap[HOST_CCREG]==CCREG)
3906 reglist&=~(1<<HOST_CCREG);
3907
3908 // get the address
277718fa 3909 ar = cinfo[i].addr;
3910 assert(ar >= 0);
cf95b4f0 3911 if (dops[i].opcode==0x3a) { // SWC2
277718fa 3912 reglist |= 1<<ar;
b9b61529 3913 }
684b6816 3914 if (s >= 0) {
3915 c = (i_regs->isconst >> s) & 1;
3916 if (c) {
3917 addr_const = constmap[i][s] + offset;
3918 memtarget = ((signed int)addr_const) < (signed int)(0x80000000 + RAM_SIZE);
3919 }
3920 }
b9b61529 3921
32631e6a 3922 cop2_do_stall_check(0, i, i_regs, reglist);
3923
cf95b4f0 3924 if (dops[i].opcode==0x3a) { // SWC2
3968e69e 3925 cop2_get_dreg(copr,tl,-1);
1fd1aceb 3926 type=STOREW_STUB;
b9b61529 3927 }
1fd1aceb 3928 else
b9b61529 3929 type=LOADW_STUB;
1fd1aceb 3930
3931 if(c&&!memtarget) {
b14b6a8f 3932 jaddr2=out;
1fd1aceb 3933 emit_jmp(0); // inline_readstub/inline_writestub?
b9b61529 3934 }
1fd1aceb 3935 else {
3936 if(!c) {
37387d8b 3937 jaddr2 = emit_fastpath_cmp_jump(i, i_regs, ar,
277718fa 3938 &offset_reg, &fastio_reg_override, ccadj_);
37387d8b 3939 }
3940 else if (ram_offset && memtarget) {
3941 offset_reg = get_ro_reg(i_regs, 0);
3942 }
3943 switch (dops[i].opcode) {
3944 case 0x32: { // LWC2
3945 int a = ar;
3946 if (fastio_reg_override >= 0)
3947 a = fastio_reg_override;
3948 do_load_word(a, tl, offset_reg);
3949 break;
1fd1aceb 3950 }
37387d8b 3951 case 0x3a: { // SWC2
1fd1aceb 3952 #ifdef DESTRUCTIVE_SHIFT
3953 if(!offset&&!c&&s>=0) emit_mov(s,ar);
3954 #endif
37387d8b 3955 int a = ar;
3956 if (fastio_reg_override >= 0)
3957 a = fastio_reg_override;
3958 do_store_word(a, 0, tl, offset_reg, 1);
3959 break;
3960 }
3961 default:
3962 assert(0);
1fd1aceb 3963 }
b9b61529 3964 }
37387d8b 3965 if (fastio_reg_override == HOST_TEMPREG || offset_reg == HOST_TEMPREG)
d1e4ebd9 3966 host_tempreg_release();
b9b61529 3967 if(jaddr2)
2330734f 3968 add_stub_r(type,jaddr2,out,i,ar,i_regs,ccadj_,reglist);
684b6816 3969 if (dops[i].opcode == 0x3a && (!c || is_ram_addr(addr_const))) // SWC2
9b495f6e 3970 do_store_smc_check(i, i_regs, reglist, ar);
684b6816 3971 if (dops[i].opcode == 0x32) { // LWC2
d1e4ebd9 3972 host_tempreg_acquire();
b9b61529 3973 cop2_put_dreg(copr,tl,HOST_TEMPREG);
d1e4ebd9 3974 host_tempreg_release();
b9b61529 3975 }
3976}
3977
81dbbf4c 3978static void cop2_assemble(int i, const struct regstat *i_regs)
8062d65a 3979{
81dbbf4c 3980 u_int copr = (source[i]>>11) & 0x1f;
9de8a0c3 3981 signed char temp = get_reg_temp(i_regs->regmap);
81dbbf4c 3982
32631e6a 3983 if (!HACK_ENABLED(NDHACK_NO_STALLS)) {
3984 u_int reglist = reglist_exclude(get_host_reglist(i_regs->regmap), temp, -1);
cf95b4f0 3985 if (dops[i].opcode2 == 0 || dops[i].opcode2 == 2) { // MFC2/CFC2
3986 signed char tl = get_reg(i_regs->regmap, dops[i].rt1);
32631e6a 3987 reglist = reglist_exclude(reglist, tl, -1);
81dbbf4c 3988 }
32631e6a 3989 cop2_do_stall_check(0, i, i_regs, reglist);
81dbbf4c 3990 }
cf95b4f0 3991 if (dops[i].opcode2==0) { // MFC2
a5cd72d0 3992 signed char tl=get_reg_w(i_regs->regmap, dops[i].rt1);
cf95b4f0 3993 if(tl>=0&&dops[i].rt1!=0)
8062d65a 3994 cop2_get_dreg(copr,tl,temp);
3995 }
cf95b4f0 3996 else if (dops[i].opcode2==4) { // MTC2
3997 signed char sl=get_reg(i_regs->regmap,dops[i].rs1);
8062d65a 3998 cop2_put_dreg(copr,sl,temp);
3999 }
cf95b4f0 4000 else if (dops[i].opcode2==2) // CFC2
8062d65a 4001 {
a5cd72d0 4002 signed char tl=get_reg_w(i_regs->regmap, dops[i].rt1);
cf95b4f0 4003 if(tl>=0&&dops[i].rt1!=0)
8062d65a 4004 emit_readword(&reg_cop2c[copr],tl);
4005 }
cf95b4f0 4006 else if (dops[i].opcode2==6) // CTC2
8062d65a 4007 {
cf95b4f0 4008 signed char sl=get_reg(i_regs->regmap,dops[i].rs1);
8062d65a 4009 switch(copr) {
4010 case 4:
4011 case 12:
4012 case 20:
4013 case 26:
4014 case 27:
4015 case 29:
4016 case 30:
4017 emit_signextend16(sl,temp);
4018 break;
4019 case 31:
3968e69e 4020 c2op_ctc2_31_assemble(sl,temp);
8062d65a 4021 break;
4022 default:
4023 temp=sl;
4024 break;
4025 }
4026 emit_writeword(temp,&reg_cop2c[copr]);
4027 assert(sl>=0);
4028 }
4029}
4030
3968e69e 4031static void do_unalignedwritestub(int n)
4032{
4033 assem_debug("do_unalignedwritestub %x\n",start+stubs[n].a*4);
4034 literal_pool(256);
4035 set_jump_target(stubs[n].addr, out);
4036
4037 int i=stubs[n].a;
4038 struct regstat *i_regs=(struct regstat *)stubs[n].c;
4039 int addr=stubs[n].b;
4040 u_int reglist=stubs[n].e;
4041 signed char *i_regmap=i_regs->regmap;
4042 int temp2=get_reg(i_regmap,FTEMP);
4043 int rt;
cf95b4f0 4044 rt=get_reg(i_regmap,dops[i].rs2);
3968e69e 4045 assert(rt>=0);
4046 assert(addr>=0);
cf95b4f0 4047 assert(dops[i].opcode==0x2a||dops[i].opcode==0x2e); // SWL/SWR only implemented
3968e69e 4048 reglist|=(1<<addr);
4049 reglist&=~(1<<temp2);
4050
3968e69e 4051 // don't bother with it and call write handler
4052 save_regs(reglist);
4053 pass_args(addr,rt);
4054 int cc=get_reg(i_regmap,CCREG);
4055 if(cc<0)
4056 emit_loadreg(CCREG,2);
2330734f 4057 emit_addimm(cc<0?2:cc,(int)stubs[n].d+1,2);
de6dbc52 4058 emit_movimm(start + i*4,3);
4059 emit_writeword(3,&psxRegs.pc);
cf95b4f0 4060 emit_far_call((dops[i].opcode==0x2a?jump_handle_swl:jump_handle_swr));
2330734f 4061 emit_addimm(0,-((int)stubs[n].d+1),cc<0?2:cc);
3968e69e 4062 if(cc<0)
4063 emit_storereg(CCREG,2);
4064 restore_regs(reglist);
4065 emit_jmp(stubs[n].retaddr); // return address
3968e69e 4066}
4067
a5cd72d0 4068static void do_overflowstub(int n)
4069{
4070 assem_debug("do_overflowstub %x\n", start + (u_int)stubs[n].a * 4);
4071 literal_pool(24);
4072 int i = stubs[n].a;
4073 struct regstat *i_regs = (struct regstat *)stubs[n].c;
4074 int ccadj = stubs[n].d;
4075 set_jump_target(stubs[n].addr, out);
4076 wb_dirtys(regs[i].regmap, regs[i].dirty);
4077 exception_assemble(i, i_regs, ccadj);
4078}
4079
277718fa 4080static void do_alignmentstub(int n)
4081{
4082 assem_debug("do_alignmentstub %x\n", start + (u_int)stubs[n].a * 4);
4083 literal_pool(24);
4084 int i = stubs[n].a;
4085 struct regstat *i_regs = (struct regstat *)stubs[n].c;
4086 int ccadj = stubs[n].d;
4087 int is_store = dops[i].itype == STORE || dops[i].opcode == 0x3A; // SWC2
4088 int cause = (dops[i].opcode & 3) << 28;
4089 cause |= is_store ? (R3000E_AdES << 2) : (R3000E_AdEL << 2);
4090 set_jump_target(stubs[n].addr, out);
4091 wb_dirtys(regs[i].regmap, regs[i].dirty);
4092 if (stubs[n].b != 1)
4093 emit_mov(stubs[n].b, 1); // faulting address
4094 emit_movimm(cause, 0);
4095 exception_assemble(i, i_regs, ccadj);
4096}
4097
57871462 4098#ifndef multdiv_assemble
4099void multdiv_assemble(int i,struct regstat *i_regs)
4100{
4101 printf("Need multdiv_assemble for this architecture.\n");
7c3a5182 4102 abort();
57871462 4103}
4104#endif
4105
2330734f 4106static void mov_assemble(int i, const struct regstat *i_regs)
57871462 4107{
cf95b4f0 4108 //if(dops[i].opcode2==0x10||dops[i].opcode2==0x12) { // MFHI/MFLO
4109 //if(dops[i].opcode2==0x11||dops[i].opcode2==0x13) { // MTHI/MTLO
4110 if(dops[i].rt1) {
7c3a5182 4111 signed char sl,tl;
a5cd72d0 4112 tl=get_reg_w(i_regs->regmap, dops[i].rt1);
57871462 4113 //assert(tl>=0);
4114 if(tl>=0) {
cf95b4f0 4115 sl=get_reg(i_regs->regmap,dops[i].rs1);
57871462 4116 if(sl>=0) emit_mov(sl,tl);
cf95b4f0 4117 else emit_loadreg(dops[i].rs1,tl);
57871462 4118 }
4119 }
cf95b4f0 4120 if (dops[i].rs1 == HIREG || dops[i].rs1 == LOREG) // MFHI/MFLO
32631e6a 4121 multdiv_do_stall(i, i_regs);
57871462 4122}
4123
3968e69e 4124// call interpreter, exception handler, things that change pc/regs/cycles ...
2330734f 4125static void call_c_cpu_handler(int i, const struct regstat *i_regs, int ccadj_, u_int pc, void *func)
57871462 4126{
4127 signed char ccreg=get_reg(i_regs->regmap,CCREG);
4128 assert(ccreg==HOST_CCREG);
4129 assert(!is_delayslot);
581335b0 4130 (void)ccreg;
3968e69e 4131
4132 emit_movimm(pc,3); // Get PC
4133 emit_readword(&last_count,2);
4134 emit_writeword(3,&psxRegs.pc);
2330734f 4135 emit_addimm(HOST_CCREG,ccadj_,HOST_CCREG);
3968e69e 4136 emit_add(2,HOST_CCREG,2);
4137 emit_writeword(2,&psxRegs.cycle);
bc7c5acb 4138 emit_addimm_ptr(FP,(u_char *)&psxRegs - (u_char *)&dynarec_local,0);
2a014d73 4139 emit_far_call(func);
4140 emit_far_jump(jump_to_new_pc);
3968e69e 4141}
4142
a5cd72d0 4143static void exception_assemble(int i, const struct regstat *i_regs, int ccadj_)
3968e69e 4144{
d1150cd6 4145 // 'break' tends to be littered around to catch things like
4146 // division by 0 and is almost never executed, so don't emit much code here
a5cd72d0 4147 void *func;
4148 if (dops[i].itype == ALU || dops[i].itype == IMM16)
4149 func = is_delayslot ? jump_overflow_ds : jump_overflow;
277718fa 4150 else if (dops[i].itype == LOAD || dops[i].itype == STORE)
4151 func = is_delayslot ? jump_addrerror_ds : jump_addrerror;
a5cd72d0 4152 else if (dops[i].opcode2 == 0x0C)
4153 func = is_delayslot ? jump_syscall_ds : jump_syscall;
4154 else
4155 func = is_delayslot ? jump_break_ds : jump_break;
277718fa 4156 if (get_reg(i_regs->regmap, CCREG) != HOST_CCREG) // evicted
4157 emit_loadreg(CCREG, HOST_CCREG);
d1150cd6 4158 emit_movimm(start + i*4, 2); // pc
4159 emit_addimm(HOST_CCREG, ccadj_ + CLOCK_ADJUST(1), HOST_CCREG);
4160 emit_far_jump(func);
7139f3c8 4161}
4162
bc7c5acb 4163static void hlecall_bad()
4164{
a5cd72d0 4165 assert(0);
bc7c5acb 4166}
4167
2330734f 4168static void hlecall_assemble(int i, const struct regstat *i_regs, int ccadj_)
7139f3c8 4169{
bc7c5acb 4170 void *hlefunc = hlecall_bad;
dd79da89 4171 uint32_t hleCode = source[i] & 0x03ffffff;
3968e69e 4172 if (hleCode < ARRAY_SIZE(psxHLEt))
4173 hlefunc = psxHLEt[hleCode];
4174
2330734f 4175 call_c_cpu_handler(i, i_regs, ccadj_, start + i*4+4, hlefunc);
57871462 4176}
4177
2330734f 4178static void intcall_assemble(int i, const struct regstat *i_regs, int ccadj_)
1e973cb0 4179{
2330734f 4180 call_c_cpu_handler(i, i_regs, ccadj_, start + i*4, execI);
1e973cb0 4181}
4182
8062d65a 4183static void speculate_mov(int rs,int rt)
4184{
4185 if(rt!=0) {
4186 smrv_strong_next|=1<<rt;
4187 smrv[rt]=smrv[rs];
4188 }
4189}
4190
4191static void speculate_mov_weak(int rs,int rt)
4192{
4193 if(rt!=0) {
4194 smrv_weak_next|=1<<rt;
4195 smrv[rt]=smrv[rs];
4196 }
4197}
4198
4199static void speculate_register_values(int i)
4200{
4201 if(i==0) {
4202 memcpy(smrv,psxRegs.GPR.r,sizeof(smrv));
4203 // gp,sp are likely to stay the same throughout the block
4204 smrv_strong_next=(1<<28)|(1<<29)|(1<<30);
4205 smrv_weak_next=~smrv_strong_next;
4206 //printf(" llr %08x\n", smrv[4]);
4207 }
4208 smrv_strong=smrv_strong_next;
4209 smrv_weak=smrv_weak_next;
cf95b4f0 4210 switch(dops[i].itype) {
8062d65a 4211 case ALU:
cf95b4f0 4212 if ((smrv_strong>>dops[i].rs1)&1) speculate_mov(dops[i].rs1,dops[i].rt1);
4213 else if((smrv_strong>>dops[i].rs2)&1) speculate_mov(dops[i].rs2,dops[i].rt1);
4214 else if((smrv_weak>>dops[i].rs1)&1) speculate_mov_weak(dops[i].rs1,dops[i].rt1);
4215 else if((smrv_weak>>dops[i].rs2)&1) speculate_mov_weak(dops[i].rs2,dops[i].rt1);
8062d65a 4216 else {
cf95b4f0 4217 smrv_strong_next&=~(1<<dops[i].rt1);
4218 smrv_weak_next&=~(1<<dops[i].rt1);
8062d65a 4219 }
4220 break;
4221 case SHIFTIMM:
cf95b4f0 4222 smrv_strong_next&=~(1<<dops[i].rt1);
4223 smrv_weak_next&=~(1<<dops[i].rt1);
8062d65a 4224 // fallthrough
4225 case IMM16:
cf95b4f0 4226 if(dops[i].rt1&&is_const(&regs[i],dops[i].rt1)) {
de6dbc52 4227 int hr = get_reg_w(regs[i].regmap, dops[i].rt1);
4228 u_int value;
8062d65a 4229 if(hr>=0) {
4230 if(get_final_value(hr,i,&value))
cf95b4f0 4231 smrv[dops[i].rt1]=value;
4232 else smrv[dops[i].rt1]=constmap[i][hr];
4233 smrv_strong_next|=1<<dops[i].rt1;
8062d65a 4234 }
4235 }
4236 else {
cf95b4f0 4237 if ((smrv_strong>>dops[i].rs1)&1) speculate_mov(dops[i].rs1,dops[i].rt1);
4238 else if((smrv_weak>>dops[i].rs1)&1) speculate_mov_weak(dops[i].rs1,dops[i].rt1);
8062d65a 4239 }
4240 break;
4241 case LOAD:
cf95b4f0 4242 if(start<0x2000&&(dops[i].rt1==26||(smrv[dops[i].rt1]>>24)==0xa0)) {
8062d65a 4243 // special case for BIOS
cf95b4f0 4244 smrv[dops[i].rt1]=0xa0000000;
4245 smrv_strong_next|=1<<dops[i].rt1;
8062d65a 4246 break;
4247 }
4248 // fallthrough
4249 case SHIFT:
4250 case LOADLR:
4251 case MOV:
cf95b4f0 4252 smrv_strong_next&=~(1<<dops[i].rt1);
4253 smrv_weak_next&=~(1<<dops[i].rt1);
8062d65a 4254 break;
4255 case COP0:
4256 case COP2:
cf95b4f0 4257 if(dops[i].opcode2==0||dops[i].opcode2==2) { // MFC/CFC
4258 smrv_strong_next&=~(1<<dops[i].rt1);
4259 smrv_weak_next&=~(1<<dops[i].rt1);
8062d65a 4260 }
4261 break;
4262 case C2LS:
cf95b4f0 4263 if (dops[i].opcode==0x32) { // LWC2
4264 smrv_strong_next&=~(1<<dops[i].rt1);
4265 smrv_weak_next&=~(1<<dops[i].rt1);
8062d65a 4266 }
4267 break;
4268 }
4269#if 0
4270 int r=4;
4271 printf("x %08x %08x %d %d c %08x %08x\n",smrv[r],start+i*4,
4272 ((smrv_strong>>r)&1),(smrv_weak>>r)&1,regs[i].isconst,regs[i].wasconst);
4273#endif
4274}
4275
2330734f 4276static void ujump_assemble(int i, const struct regstat *i_regs);
4277static void rjump_assemble(int i, const struct regstat *i_regs);
4278static void cjump_assemble(int i, const struct regstat *i_regs);
4279static void sjump_assemble(int i, const struct regstat *i_regs);
2330734f 4280
4281static int assemble(int i, const struct regstat *i_regs, int ccadj_)
57871462 4282{
2330734f 4283 int ds = 0;
4284 switch (dops[i].itype) {
57871462 4285 case ALU:
a5cd72d0 4286 alu_assemble(i, i_regs, ccadj_);
2330734f 4287 break;
57871462 4288 case IMM16:
a5cd72d0 4289 imm16_assemble(i, i_regs, ccadj_);
2330734f 4290 break;
57871462 4291 case SHIFT:
2330734f 4292 shift_assemble(i, i_regs);
4293 break;
57871462 4294 case SHIFTIMM:
2330734f 4295 shiftimm_assemble(i, i_regs);
4296 break;
57871462 4297 case LOAD:
2330734f 4298 load_assemble(i, i_regs, ccadj_);
4299 break;
57871462 4300 case LOADLR:
2330734f 4301 loadlr_assemble(i, i_regs, ccadj_);
4302 break;
57871462 4303 case STORE:
2330734f 4304 store_assemble(i, i_regs, ccadj_);
4305 break;
57871462 4306 case STORELR:
2330734f 4307 storelr_assemble(i, i_regs, ccadj_);
4308 break;
57871462 4309 case COP0:
2330734f 4310 cop0_assemble(i, i_regs, ccadj_);
4311 break;
a5cd72d0 4312 case RFE:
277718fa 4313 rfe_assemble(i, i_regs);
2330734f 4314 break;
b9b61529 4315 case COP2:
2330734f 4316 cop2_assemble(i, i_regs);
4317 break;
b9b61529 4318 case C2LS:
2330734f 4319 c2ls_assemble(i, i_regs, ccadj_);
4320 break;
b9b61529 4321 case C2OP:
2330734f 4322 c2op_assemble(i, i_regs);
4323 break;
57871462 4324 case MULTDIV:
2330734f 4325 multdiv_assemble(i, i_regs);
4326 multdiv_prepare_stall(i, i_regs, ccadj_);
32631e6a 4327 break;
57871462 4328 case MOV:
2330734f 4329 mov_assemble(i, i_regs);
4330 break;
4331 case SYSCALL:
a5cd72d0 4332 exception_assemble(i, i_regs, ccadj_);
2330734f 4333 break;
4334 case HLECALL:
4335 hlecall_assemble(i, i_regs, ccadj_);
4336 break;
4337 case INTCALL:
4338 intcall_assemble(i, i_regs, ccadj_);
4339 break;
4340 case UJUMP:
4341 ujump_assemble(i, i_regs);
4342 ds = 1;
4343 break;
4344 case RJUMP:
4345 rjump_assemble(i, i_regs);
4346 ds = 1;
4347 break;
4348 case CJUMP:
4349 cjump_assemble(i, i_regs);
4350 ds = 1;
4351 break;
4352 case SJUMP:
4353 sjump_assemble(i, i_regs);
4354 ds = 1;
4355 break;
24058131 4356 case NOP:
2330734f 4357 case OTHER:
2330734f 4358 // not handled, just skip
4359 break;
4360 default:
4361 assert(0);
4362 }
4363 return ds;
4364}
4365
4366static void ds_assemble(int i, const struct regstat *i_regs)
4367{
4368 speculate_register_values(i);
4369 is_delayslot = 1;
4370 switch (dops[i].itype) {
57871462 4371 case SYSCALL:
7139f3c8 4372 case HLECALL:
1e973cb0 4373 case INTCALL:
57871462 4374 case UJUMP:
4375 case RJUMP:
4376 case CJUMP:
4377 case SJUMP:
c43b5311 4378 SysPrintf("Jump in the delay slot. This is probably a bug.\n");
2330734f 4379 break;
4380 default:
277718fa 4381 assemble(i, i_regs, cinfo[i].ccadj);
57871462 4382 }
2330734f 4383 is_delayslot = 0;
57871462 4384}
4385
4386// Is the branch target a valid internal jump?
ad49de89 4387static int internal_branch(int addr)
57871462 4388{
4389 if(addr&1) return 0; // Indirect (register) jump
4390 if(addr>=start && addr<start+slen*4-4)
4391 {
71e490c5 4392 return 1;
57871462 4393 }
4394 return 0;
4395}
4396
ad49de89 4397static void wb_invalidate(signed char pre[],signed char entry[],uint64_t dirty,uint64_t u)
57871462 4398{
4399 int hr;
4400 for(hr=0;hr<HOST_REGS;hr++) {
4401 if(hr!=EXCLUDE_REG) {
4402 if(pre[hr]!=entry[hr]) {
4403 if(pre[hr]>=0) {
4404 if((dirty>>hr)&1) {
4405 if(get_reg(entry,pre[hr])<0) {
00fa9369 4406 assert(pre[hr]<64);
4407 if(!((u>>pre[hr])&1))
4408 emit_storereg(pre[hr],hr);
57871462 4409 }
4410 }
4411 }
4412 }
4413 }
4414 }
4415 // Move from one register to another (no writeback)
4416 for(hr=0;hr<HOST_REGS;hr++) {
4417 if(hr!=EXCLUDE_REG) {
4418 if(pre[hr]!=entry[hr]) {
9de8a0c3 4419 if(pre[hr]>=0&&pre[hr]<TEMPREG) {
57871462 4420 int nr;
4421 if((nr=get_reg(entry,pre[hr]))>=0) {
4422 emit_mov(hr,nr);
4423 }
4424 }
4425 }
4426 }
4427 }
4428}
57871462 4429
4430// Load the specified registers
4431// This only loads the registers given as arguments because
4432// we don't want to load things that will be overwritten
53358c1d 4433static inline void load_reg(signed char entry[], signed char regmap[], int rs)
57871462 4434{
53358c1d 4435 int hr = get_reg(regmap, rs);
4436 if (hr >= 0 && entry[hr] != regmap[hr])
4437 emit_loadreg(regmap[hr], hr);
4438}
4439
4440static void load_regs(signed char entry[], signed char regmap[], int rs1, int rs2)
4441{
4442 load_reg(entry, regmap, rs1);
4443 if (rs1 != rs2)
4444 load_reg(entry, regmap, rs2);
57871462 4445}
4446
4447// Load registers prior to the start of a loop
4448// so that they are not loaded within the loop
4449static void loop_preload(signed char pre[],signed char entry[])
4450{
4451 int hr;
53358c1d 4452 for (hr = 0; hr < HOST_REGS; hr++) {
4453 int r = entry[hr];
4454 if (r >= 0 && pre[hr] != r && get_reg(pre, r) < 0) {
4455 assem_debug("loop preload:\n");
4456 if (r < TEMPREG)
4457 emit_loadreg(r, hr);
57871462 4458 }
4459 }
4460}
4461
4462// Generate address for load/store instruction
277718fa 4463// goes to AGEN (or temp) for writes, FTEMP for LOADLR and cop1/2 loads
4464// AGEN is assigned by pass5b_preallocate2
4149788d 4465static void address_generation(int i, const struct regstat *i_regs, signed char entry[])
57871462 4466{
37387d8b 4467 if (dops[i].is_load || dops[i].is_store) {
277718fa 4468 int ra = -1;
4469 int agr = AGEN1 + (i&1);
cf95b4f0 4470 if(dops[i].itype==LOAD) {
277718fa 4471 if (!dops[i].may_except)
4472 ra = get_reg_w(i_regs->regmap, dops[i].rt1); // reuse dest for agen
4473 if (ra < 0)
4474 ra = get_reg_temp(i_regs->regmap);
57871462 4475 }
cf95b4f0 4476 if(dops[i].itype==LOADLR) {
57871462 4477 ra=get_reg(i_regs->regmap,FTEMP);
4478 }
cf95b4f0 4479 if(dops[i].itype==STORE||dops[i].itype==STORELR) {
57871462 4480 ra=get_reg(i_regs->regmap,agr);
9de8a0c3 4481 if(ra<0) ra=get_reg_temp(i_regs->regmap);
57871462 4482 }
37387d8b 4483 if(dops[i].itype==C2LS) {
277718fa 4484 if (dops[i].opcode == 0x32) // LWC2
57871462 4485 ra=get_reg(i_regs->regmap,FTEMP);
277718fa 4486 else { // SWC2
57871462 4487 ra=get_reg(i_regs->regmap,agr);
9de8a0c3 4488 if(ra<0) ra=get_reg_temp(i_regs->regmap);
57871462 4489 }
4490 }
277718fa 4491 int rs = get_reg(i_regs->regmap, dops[i].rs1);
4492 //if(ra>=0)
4493 {
4494 int offset = cinfo[i].imm;
4495 int add_offset = offset != 0;
33a1eda1 4496 int c = rs >= 0 && ((i_regs->wasconst >> rs) & 1);
cf95b4f0 4497 if(dops[i].rs1==0) {
57871462 4498 // Using r0 as a base address
277718fa 4499 assert(ra >= 0);
57871462 4500 if(!entry||entry[ra]!=agr) {
cf95b4f0 4501 if (dops[i].opcode==0x22||dops[i].opcode==0x26) {
57871462 4502 emit_movimm(offset&0xFFFFFFFC,ra); // LWL/LWR
57871462 4503 }else{
4504 emit_movimm(offset,ra);
4505 }
4506 } // else did it in the previous cycle
277718fa 4507 cinfo[i].addr = ra;
4508 add_offset = 0;
4509 }
4510 else if (rs < 0) {
4511 assert(ra >= 0);
4512 if (!entry || entry[ra] != dops[i].rs1)
4513 emit_loadreg(dops[i].rs1, ra);
4514 cinfo[i].addr = ra;
cf95b4f0 4515 //if(!entry||entry[ra]!=dops[i].rs1)
57871462 4516 // printf("poor load scheduling!\n");
4517 }
4518 else if(c) {
cf95b4f0 4519 if(dops[i].rs1!=dops[i].rt1||dops[i].itype!=LOAD) {
277718fa 4520 assert(ra >= 0);
57871462 4521 if(!entry||entry[ra]!=agr) {
cf95b4f0 4522 if (dops[i].opcode==0x22||dops[i].opcode==0x26) {
57871462 4523 emit_movimm((constmap[i][rs]+offset)&0xFFFFFFFC,ra); // LWL/LWR
57871462 4524 }else{
57871462 4525 emit_movimm(constmap[i][rs]+offset,ra);
8575a877 4526 regs[i].loadedconst|=1<<ra;
57871462 4527 }
4528 } // else did it in the previous cycle
277718fa 4529 cinfo[i].addr = ra;
4530 }
4531 else // else load_consts already did it
4532 cinfo[i].addr = rs;
4533 add_offset = 0;
57871462 4534 }
277718fa 4535 else
4536 cinfo[i].addr = rs;
4537 if (add_offset) {
4538 assert(ra >= 0);
57871462 4539 if(rs>=0) {
4540 emit_addimm(rs,offset,ra);
4541 }else{
4542 emit_addimm(ra,offset,ra);
4543 }
277718fa 4544 cinfo[i].addr = ra;
57871462 4545 }
4546 }
277718fa 4547 assert(cinfo[i].addr >= 0);
57871462 4548 }
4549 // Preload constants for next instruction
37387d8b 4550 if (dops[i+1].is_load || dops[i+1].is_store) {
57871462 4551 int agr,ra;
57871462 4552 // Actual address
4553 agr=AGEN1+((i+1)&1);
4554 ra=get_reg(i_regs->regmap,agr);
4555 if(ra>=0) {
cf95b4f0 4556 int rs=get_reg(regs[i+1].regmap,dops[i+1].rs1);
277718fa 4557 int offset=cinfo[i+1].imm;
57871462 4558 int c=(regs[i+1].wasconst>>rs)&1;
cf95b4f0 4559 if(c&&(dops[i+1].rs1!=dops[i+1].rt1||dops[i+1].itype!=LOAD)) {
4560 if (dops[i+1].opcode==0x22||dops[i+1].opcode==0x26) {
57871462 4561 emit_movimm((constmap[i+1][rs]+offset)&0xFFFFFFFC,ra); // LWL/LWR
cf95b4f0 4562 }else if (dops[i+1].opcode==0x1a||dops[i+1].opcode==0x1b) {
57871462 4563 emit_movimm((constmap[i+1][rs]+offset)&0xFFFFFFF8,ra); // LDL/LDR
4564 }else{
57871462 4565 emit_movimm(constmap[i+1][rs]+offset,ra);
8575a877 4566 regs[i+1].loadedconst|=1<<ra;
57871462 4567 }
4568 }
cf95b4f0 4569 else if(dops[i+1].rs1==0) {
57871462 4570 // Using r0 as a base address
cf95b4f0 4571 if (dops[i+1].opcode==0x22||dops[i+1].opcode==0x26) {
57871462 4572 emit_movimm(offset&0xFFFFFFFC,ra); // LWL/LWR
cf95b4f0 4573 }else if (dops[i+1].opcode==0x1a||dops[i+1].opcode==0x1b) {
57871462 4574 emit_movimm(offset&0xFFFFFFF8,ra); // LDL/LDR
4575 }else{
4576 emit_movimm(offset,ra);
4577 }
4578 }
4579 }
4580 }
4581}
4582
de6dbc52 4583static int get_final_value(int hr, int i, u_int *value)
57871462 4584{
4585 int reg=regs[i].regmap[hr];
4586 while(i<slen-1) {
4587 if(regs[i+1].regmap[hr]!=reg) break;
4588 if(!((regs[i+1].isconst>>hr)&1)) break;
cf95b4f0 4589 if(dops[i+1].bt) break;
57871462 4590 i++;
4591 }
4592 if(i<slen-1) {
fe807a8a 4593 if (dops[i].is_jump) {
57871462 4594 *value=constmap[i][hr];
4595 return 1;
4596 }
cf95b4f0 4597 if(!dops[i+1].bt) {
fe807a8a 4598 if (dops[i+1].is_jump) {
57871462 4599 // Load in delay slot, out-of-order execution
cf95b4f0 4600 if(dops[i+2].itype==LOAD&&dops[i+2].rs1==reg&&dops[i+2].rt1==reg&&((regs[i+1].wasconst>>hr)&1))
57871462 4601 {
57871462 4602 // Precompute load address
277718fa 4603 *value=constmap[i][hr]+cinfo[i+2].imm;
57871462 4604 return 1;
4605 }
4606 }
cf95b4f0 4607 if(dops[i+1].itype==LOAD&&dops[i+1].rs1==reg&&dops[i+1].rt1==reg)
57871462 4608 {
57871462 4609 // Precompute load address
277718fa 4610 *value=constmap[i][hr]+cinfo[i+1].imm;
4611 //printf("c=%x imm=%lx\n",(long)constmap[i][hr],cinfo[i+1].imm);
57871462 4612 return 1;
4613 }
4614 }
4615 }
4616 *value=constmap[i][hr];
643aeae3 4617 //printf("c=%lx\n",(long)constmap[i][hr]);
57871462 4618 if(i==slen-1) return 1;
00fa9369 4619 assert(reg < 64);
4620 return !((unneeded_reg[i+1]>>reg)&1);
57871462 4621}
4622
4623// Load registers with known constants
ad49de89 4624static void load_consts(signed char pre[],signed char regmap[],int i)
57871462 4625{
8575a877 4626 int hr,hr2;
4627 // propagate loaded constant flags
cf95b4f0 4628 if(i==0||dops[i].bt)
8575a877 4629 regs[i].loadedconst=0;
4630 else {
684b6816 4631 for (hr = 0; hr < HOST_REGS; hr++) {
4632 if (hr == EXCLUDE_REG || regmap[hr] < 0 || pre[hr] != regmap[hr])
4633 continue;
4634 if ((((regs[i-1].isconst & regs[i-1].loadedconst) >> hr) & 1)
4635 && regmap[hr] == regs[i-1].regmap[hr])
8575a877 4636 {
684b6816 4637 regs[i].loadedconst |= 1u << hr;
8575a877 4638 }
4639 }
4640 }
57871462 4641 // Load 32-bit regs
4642 for(hr=0;hr<HOST_REGS;hr++) {
4643 if(hr!=EXCLUDE_REG&&regmap[hr]>=0) {
4644 //if(entry[hr]!=regmap[hr]) {
8575a877 4645 if(!((regs[i].loadedconst>>hr)&1)) {
ad49de89 4646 assert(regmap[hr]<64);
4647 if(((regs[i].isconst>>hr)&1)&&regmap[hr]>0) {
de6dbc52 4648 u_int value, similar=0;
57871462 4649 if(get_final_value(hr,i,&value)) {
8575a877 4650 // see if some other register has similar value
4651 for(hr2=0;hr2<HOST_REGS;hr2++) {
4652 if(hr2!=EXCLUDE_REG&&((regs[i].loadedconst>>hr2)&1)) {
4653 if(is_similar_value(value,constmap[i][hr2])) {
4654 similar=1;
4655 break;
4656 }
4657 }
4658 }
4659 if(similar) {
de6dbc52 4660 u_int value2;
8575a877 4661 if(get_final_value(hr2,i,&value2)) // is this needed?
4662 emit_movimm_from(value2,hr2,value,hr);
4663 else
4664 emit_movimm(value,hr);
4665 }
4666 else if(value==0) {
57871462 4667 emit_zeroreg(hr);
4668 }
4669 else {
4670 emit_movimm(value,hr);
4671 }
4672 }
8575a877 4673 regs[i].loadedconst|=1<<hr;
57871462 4674 }
4675 }
4676 }
4677 }
57871462 4678}
ad49de89 4679
2330734f 4680static void load_all_consts(const signed char regmap[], u_int dirty, int i)
57871462 4681{
4682 int hr;
4683 // Load 32-bit regs
4684 for(hr=0;hr<HOST_REGS;hr++) {
4685 if(hr!=EXCLUDE_REG&&regmap[hr]>=0&&((dirty>>hr)&1)) {
ad49de89 4686 assert(regmap[hr] < 64);
4687 if(((regs[i].isconst>>hr)&1)&&regmap[hr]>0) {
57871462 4688 int value=constmap[i][hr];
4689 if(value==0) {
4690 emit_zeroreg(hr);
4691 }
4692 else {
4693 emit_movimm(value,hr);
4694 }
4695 }
4696 }
4697 }
57871462 4698}
4699
4700// Write out all dirty registers (except cycle count)
a22ccd6a 4701#ifndef wb_dirtys
4702static void wb_dirtys(const signed char i_regmap[], u_int i_dirty)
57871462 4703{
4704 int hr;
4705 for(hr=0;hr<HOST_REGS;hr++) {
4706 if(hr!=EXCLUDE_REG) {
4707 if(i_regmap[hr]>0) {
4708 if(i_regmap[hr]!=CCREG) {
4709 if((i_dirty>>hr)&1) {
00fa9369 4710 assert(i_regmap[hr]<64);
4711 emit_storereg(i_regmap[hr],hr);
57871462 4712 }
4713 }
4714 }
4715 }
4716 }
4717}
a22ccd6a 4718#endif
ad49de89 4719
57871462 4720// Write out dirty registers that we need to reload (pair with load_needed_regs)
4721// This writes the registers not written by store_regs_bt
a22ccd6a 4722static void wb_needed_dirtys(const signed char i_regmap[], u_int i_dirty, int addr)
57871462 4723{
4724 int hr;
4725 int t=(addr-start)>>2;
4726 for(hr=0;hr<HOST_REGS;hr++) {
4727 if(hr!=EXCLUDE_REG) {
4728 if(i_regmap[hr]>0) {
4729 if(i_regmap[hr]!=CCREG) {
ad49de89 4730 if(i_regmap[hr]==regs[t].regmap_entry[hr] && ((regs[t].dirty>>hr)&1)) {
57871462 4731 if((i_dirty>>hr)&1) {
00fa9369 4732 assert(i_regmap[hr]<64);
4733 emit_storereg(i_regmap[hr],hr);
57871462 4734 }
4735 }
4736 }
4737 }
4738 }
4739 }
4740}
4741
4742// Load all registers (except cycle count)
a22ccd6a 4743#ifndef load_all_regs
2330734f 4744static void load_all_regs(const signed char i_regmap[])
57871462 4745{
4746 int hr;
4747 for(hr=0;hr<HOST_REGS;hr++) {
4748 if(hr!=EXCLUDE_REG) {
4749 if(i_regmap[hr]==0) {
4750 emit_zeroreg(hr);
4751 }
4752 else
9de8a0c3 4753 if(i_regmap[hr]>0 && i_regmap[hr]<TEMPREG && i_regmap[hr]!=CCREG)
57871462 4754 {
4755 emit_loadreg(i_regmap[hr],hr);
4756 }
4757 }
4758 }
4759}
a22ccd6a 4760#endif
57871462 4761
4762// Load all current registers also needed by next instruction
2330734f 4763static void load_needed_regs(const signed char i_regmap[], const signed char next_regmap[])
57871462 4764{
a22ccd6a 4765 signed char regmap_sel[HOST_REGS];
57871462 4766 int hr;
a22ccd6a 4767 for (hr = 0; hr < HOST_REGS; hr++) {
4768 regmap_sel[hr] = -1;
4769 if (hr != EXCLUDE_REG)
4770 if (next_regmap[hr] == i_regmap[hr] || get_reg(next_regmap, i_regmap[hr]) >= 0)
4771 regmap_sel[hr] = i_regmap[hr];
57871462 4772 }
a22ccd6a 4773 load_all_regs(regmap_sel);
57871462 4774}
4775
4776// Load all regs, storing cycle count if necessary
2330734f 4777static void load_regs_entry(int t)
57871462 4778{
cf95b4f0 4779 if(dops[t].is_ds) emit_addimm(HOST_CCREG,CLOCK_ADJUST(1),HOST_CCREG);
277718fa 4780 else if(cinfo[t].ccadj) emit_addimm(HOST_CCREG,-cinfo[t].ccadj,HOST_CCREG);
57871462 4781 if(regs[t].regmap_entry[HOST_CCREG]!=CCREG) {
4782 emit_storereg(CCREG,HOST_CCREG);
4783 }
a22ccd6a 4784 load_all_regs(regs[t].regmap_entry);
57871462 4785}
4786
4787// Store dirty registers prior to branch
4149788d 4788static void store_regs_bt(signed char i_regmap[],uint64_t i_dirty,int addr)
57871462 4789{
ad49de89 4790 if(internal_branch(addr))
57871462 4791 {
4792 int t=(addr-start)>>2;
4793 int hr;
4794 for(hr=0;hr<HOST_REGS;hr++) {
4795 if(hr!=EXCLUDE_REG) {
4796 if(i_regmap[hr]>0 && i_regmap[hr]!=CCREG) {
ad49de89 4797 if(i_regmap[hr]!=regs[t].regmap_entry[hr] || !((regs[t].dirty>>hr)&1)) {
57871462 4798 if((i_dirty>>hr)&1) {
00fa9369 4799 assert(i_regmap[hr]<64);
4800 if(!((unneeded_reg[t]>>i_regmap[hr])&1))
4801 emit_storereg(i_regmap[hr],hr);
57871462 4802 }
4803 }
4804 }
4805 }
4806 }
4807 }
4808 else
4809 {
4810 // Branch out of this block, write out all dirty regs
ad49de89 4811 wb_dirtys(i_regmap,i_dirty);
57871462 4812 }
4813}
4814
4815// Load all needed registers for branch target
ad49de89 4816static void load_regs_bt(signed char i_regmap[],uint64_t i_dirty,int addr)
57871462 4817{
4818 //if(addr>=start && addr<(start+slen*4))
ad49de89 4819 if(internal_branch(addr))
57871462 4820 {
4821 int t=(addr-start)>>2;
4822 int hr;
4823 // Store the cycle count before loading something else
4824 if(i_regmap[HOST_CCREG]!=CCREG) {
4825 assert(i_regmap[HOST_CCREG]==-1);
4826 }
4827 if(regs[t].regmap_entry[HOST_CCREG]!=CCREG) {
4828 emit_storereg(CCREG,HOST_CCREG);
4829 }
4830 // Load 32-bit regs
4831 for(hr=0;hr<HOST_REGS;hr++) {
ea3d2e6e 4832 if(hr!=EXCLUDE_REG&&regs[t].regmap_entry[hr]>=0&&regs[t].regmap_entry[hr]<TEMPREG) {
00fa9369 4833 if(i_regmap[hr]!=regs[t].regmap_entry[hr]) {
57871462 4834 if(regs[t].regmap_entry[hr]==0) {
4835 emit_zeroreg(hr);
4836 }
4837 else if(regs[t].regmap_entry[hr]!=CCREG)
4838 {
4839 emit_loadreg(regs[t].regmap_entry[hr],hr);
4840 }
4841 }
4842 }
4843 }
57871462 4844 }
4845}
4846
ad49de89 4847static int match_bt(signed char i_regmap[],uint64_t i_dirty,int addr)
57871462 4848{
4849 if(addr>=start && addr<start+slen*4-4)
4850 {
4851 int t=(addr-start)>>2;
4852 int hr;
4853 if(regs[t].regmap_entry[HOST_CCREG]!=CCREG) return 0;
4854 for(hr=0;hr<HOST_REGS;hr++)
4855 {
4856 if(hr!=EXCLUDE_REG)
4857 {
4858 if(i_regmap[hr]!=regs[t].regmap_entry[hr])
4859 {
ea3d2e6e 4860 if(regs[t].regmap_entry[hr]>=0&&(regs[t].regmap_entry[hr]|64)<TEMPREG+64)
57871462 4861 {
4862 return 0;
4863 }
9f51b4b9 4864 else
57871462 4865 if((i_dirty>>hr)&1)
4866 {
ea3d2e6e 4867 if(i_regmap[hr]<TEMPREG)
57871462 4868 {
4869 if(!((unneeded_reg[t]>>i_regmap[hr])&1))
4870 return 0;
4871 }
ea3d2e6e 4872 else if(i_regmap[hr]>=64&&i_regmap[hr]<TEMPREG+64)
57871462 4873 {
00fa9369 4874 assert(0);
57871462 4875 }
4876 }
4877 }
4878 else // Same register but is it 32-bit or dirty?
4879 if(i_regmap[hr]>=0)
4880 {
4881 if(!((regs[t].dirty>>hr)&1))
4882 {
4883 if((i_dirty>>hr)&1)
4884 {
4885 if(!((unneeded_reg[t]>>i_regmap[hr])&1))
4886 {
4887 //printf("%x: dirty no match\n",addr);
4888 return 0;
4889 }
4890 }
4891 }
57871462 4892 }
4893 }
4894 }
57871462 4895 // Delay slots are not valid branch targets
fe807a8a 4896 //if(t>0&&(dops[t-1].is_jump) return 0;
57871462 4897 // Delay slots require additional processing, so do not match
cf95b4f0 4898 if(dops[t].is_ds) return 0;
57871462 4899 }
4900 else
4901 {
4902 int hr;
4903 for(hr=0;hr<HOST_REGS;hr++)
4904 {
4905 if(hr!=EXCLUDE_REG)
4906 {
4907 if(i_regmap[hr]>=0)
4908 {
4909 if(hr!=HOST_CCREG||i_regmap[hr]!=CCREG)
4910 {
4911 if((i_dirty>>hr)&1)
4912 {
4913 return 0;
4914 }
4915 }
4916 }
4917 }
4918 }
4919 }
4920 return 1;
4921}
4922
dd114d7d 4923#ifdef DRC_DBG
2330734f 4924static void drc_dbg_emit_do_cmp(int i, int ccadj_)
dd114d7d 4925{
4926 extern void do_insn_cmp();
3968e69e 4927 //extern int cycle;
81dbbf4c 4928 u_int hr, reglist = get_host_reglist(regs[i].regmap);
33a1eda1 4929 reglist |= get_host_reglist(regs[i].regmap_entry);
4930 reglist &= DRC_DBG_REGMASK;
dd114d7d 4931
40fca85b 4932 assem_debug("//do_insn_cmp %08x\n", start+i*4);
dd114d7d 4933 save_regs(reglist);
40fca85b 4934 // write out changed consts to match the interpreter
cf95b4f0 4935 if (i > 0 && !dops[i].bt) {
40fca85b 4936 for (hr = 0; hr < HOST_REGS; hr++) {
2330734f 4937 int reg = regs[i].regmap_entry[hr]; // regs[i-1].regmap[hr];
277718fa 4938 if (hr == EXCLUDE_REG || reg <= 0)
40fca85b 4939 continue;
4940 if (!((regs[i-1].isconst >> hr) & 1))
4941 continue;
4942 if (i > 1 && reg == regs[i-2].regmap[hr] && constmap[i-1][hr] == constmap[i-2][hr])
4943 continue;
4944 emit_movimm(constmap[i-1][hr],0);
4945 emit_storereg(reg, 0);
4946 }
4947 }
dd114d7d 4948 emit_movimm(start+i*4,0);
643aeae3 4949 emit_writeword(0,&pcaddr);
2330734f 4950 int cc = get_reg(regs[i].regmap_entry, CCREG);
4951 if (cc < 0)
4952 emit_loadreg(CCREG, cc = 0);
4953 emit_addimm(cc, ccadj_, 0);
4954 emit_writeword(0, &psxRegs.cycle);
2a014d73 4955 emit_far_call(do_insn_cmp);
643aeae3 4956 //emit_readword(&cycle,0);
dd114d7d 4957 //emit_addimm(0,2,0);
643aeae3 4958 //emit_writeword(0,&cycle);
3968e69e 4959 (void)get_reg2;
dd114d7d 4960 restore_regs(reglist);
40fca85b 4961 assem_debug("\\\\do_insn_cmp\n");
dd114d7d 4962}
4963#else
2330734f 4964#define drc_dbg_emit_do_cmp(x,y)
dd114d7d 4965#endif
4966
57871462 4967// Used when a branch jumps into the delay slot of another branch
7c3a5182 4968static void ds_assemble_entry(int i)
57871462 4969{
277718fa 4970 int t = (cinfo[i].ba - start) >> 2;
2330734f 4971 int ccadj_ = -CLOCK_ADJUST(1);
df4dc2b1 4972 if (!instr_addr[t])
4973 instr_addr[t] = out;
277718fa 4974 assem_debug("Assemble delay slot at %x\n",cinfo[i].ba);
57871462 4975 assem_debug("<->\n");
2330734f 4976 drc_dbg_emit_do_cmp(t, ccadj_);
57871462 4977 if(regs[t].regmap_entry[HOST_CCREG]==CCREG&&regs[t].regmap[HOST_CCREG]!=CCREG)
ad49de89 4978 wb_register(CCREG,regs[t].regmap_entry,regs[t].wasdirty);
cf95b4f0 4979 load_regs(regs[t].regmap_entry,regs[t].regmap,dops[t].rs1,dops[t].rs2);
57871462 4980 address_generation(t,&regs[t],regs[t].regmap_entry);
37387d8b 4981 if (ram_offset && (dops[t].is_load || dops[t].is_store))
53358c1d 4982 load_reg(regs[t].regmap_entry,regs[t].regmap,ROREG);
37387d8b 4983 if (dops[t].is_store)
53358c1d 4984 load_reg(regs[t].regmap_entry,regs[t].regmap,INVCP);
57871462 4985 is_delayslot=0;
2330734f 4986 switch (dops[t].itype) {
57871462 4987 case SYSCALL:
7139f3c8 4988 case HLECALL:
1e973cb0 4989 case INTCALL:
57871462 4990 case UJUMP:
4991 case RJUMP:
4992 case CJUMP:
4993 case SJUMP:
c43b5311 4994 SysPrintf("Jump in the delay slot. This is probably a bug.\n");
2330734f 4995 break;
4996 default:
4997 assemble(t, &regs[t], ccadj_);
57871462 4998 }
277718fa 4999 store_regs_bt(regs[t].regmap,regs[t].dirty,cinfo[i].ba+4);
5000 load_regs_bt(regs[t].regmap,regs[t].dirty,cinfo[i].ba+4);
5001 if(internal_branch(cinfo[i].ba+4))
57871462 5002 assem_debug("branch: internal\n");
5003 else
5004 assem_debug("branch: external\n");
277718fa 5005 assert(internal_branch(cinfo[i].ba+4));
5006 add_to_linker(out,cinfo[i].ba+4,internal_branch(cinfo[i].ba+4));
57871462 5007 emit_jmp(0);
5008}
5009
d1e4ebd9 5010// Load 2 immediates optimizing for small code size
5011static void emit_mov2imm_compact(int imm1,u_int rt1,int imm2,u_int rt2)
5012{
5013 emit_movimm(imm1,rt1);
5014 emit_movimm_from(imm1,rt1,imm2,rt2);
5015}
5016
2330734f 5017static void do_cc(int i, const signed char i_regmap[], int *adj,
5018 int addr, int taken, int invert)
57871462 5019{
2330734f 5020 int count, count_plus2;
b14b6a8f 5021 void *jaddr;
5022 void *idle=NULL;
b6e87b2b 5023 int t=0;
cf95b4f0 5024 if(dops[i].itype==RJUMP)
57871462 5025 {
5026 *adj=0;
5027 }
277718fa 5028 //if(cinfo[i].ba>=start && cinfo[i].ba<(start+slen*4))
5029 if(internal_branch(cinfo[i].ba))
57871462 5030 {
277718fa 5031 t=(cinfo[i].ba-start)>>2;
2330734f 5032 if(dops[t].is_ds) *adj=-CLOCK_ADJUST(1); // Branch into delay slot adds an extra cycle
277718fa 5033 else *adj=cinfo[t].ccadj;
57871462 5034 }
5035 else
5036 {
5037 *adj=0;
5038 }
277718fa 5039 count = cinfo[i].ccadj;
2330734f 5040 count_plus2 = count + CLOCK_ADJUST(2);
277718fa 5041 if(taken==TAKEN && i==(cinfo[i].ba-start)>>2 && source[i+1]==0) {
57871462 5042 // Idle loop
5043 if(count&1) emit_addimm_and_set_flags(2*(count+2),HOST_CCREG);
b14b6a8f 5044 idle=out;
57871462 5045 //emit_subfrommem(&idlecount,HOST_CCREG); // Count idle cycles
5046 emit_andimm(HOST_CCREG,3,HOST_CCREG);
b14b6a8f 5047 jaddr=out;
57871462 5048 emit_jmp(0);
5049 }
5050 else if(*adj==0||invert) {
2330734f 5051 int cycles = count_plus2;
b6e87b2b 5052 // faster loop HACK
bb4f300c 5053#if 0
b6e87b2b 5054 if (t&&*adj) {
5055 int rel=t-i;
5056 if(-NO_CYCLE_PENALTY_THR<rel&&rel<0)
2330734f 5057 cycles=*adj+count+2-*adj;
b6e87b2b 5058 }
bb4f300c 5059#endif
2330734f 5060 emit_addimm_and_set_flags(cycles, HOST_CCREG);
5061 jaddr = out;
57871462 5062 emit_jns(0);
5063 }
5064 else
5065 {
2330734f 5066 emit_cmpimm(HOST_CCREG, -count_plus2);
5067 jaddr = out;
57871462 5068 emit_jns(0);
5069 }
2330734f 5070 add_stub(CC_STUB,jaddr,idle?idle:out,(*adj==0||invert||idle)?0:count_plus2,i,addr,taken,0);
57871462 5071}
5072
b14b6a8f 5073static void do_ccstub(int n)
57871462 5074{
5075 literal_pool(256);
d1e4ebd9 5076 assem_debug("do_ccstub %x\n",start+(u_int)stubs[n].b*4);
b14b6a8f 5077 set_jump_target(stubs[n].addr, out);
5078 int i=stubs[n].b;
33a1eda1 5079 if (stubs[n].d != TAKEN) {
ad49de89 5080 wb_dirtys(branch_regs[i].regmap,branch_regs[i].dirty);
57871462 5081 }
5082 else {
277718fa 5083 if(internal_branch(cinfo[i].ba))
5084 wb_needed_dirtys(branch_regs[i].regmap,branch_regs[i].dirty,cinfo[i].ba);
57871462 5085 }
b14b6a8f 5086 if(stubs[n].c!=-1)
57871462 5087 {
5088 // Save PC as return address
6d75addf 5089 emit_movimm(stubs[n].c,0);
5090 emit_writeword(0,&pcaddr);
57871462 5091 }
5092 else
5093 {
5094 // Return address depends on which way the branch goes
cf95b4f0 5095 if(dops[i].itype==CJUMP||dops[i].itype==SJUMP)
57871462 5096 {
cf95b4f0 5097 int s1l=get_reg(branch_regs[i].regmap,dops[i].rs1);
5098 int s2l=get_reg(branch_regs[i].regmap,dops[i].rs2);
5099 if(dops[i].rs1==0)
57871462 5100 {
ad49de89 5101 s1l=s2l;
5102 s2l=-1;
57871462 5103 }
cf95b4f0 5104 else if(dops[i].rs2==0)
57871462 5105 {
ad49de89 5106 s2l=-1;
57871462 5107 }
5108 assert(s1l>=0);
5109 #ifdef DESTRUCTIVE_WRITEBACK
cf95b4f0 5110 if(dops[i].rs1) {
ad49de89 5111 if((branch_regs[i].dirty>>s1l)&&1)
cf95b4f0 5112 emit_loadreg(dops[i].rs1,s1l);
9f51b4b9 5113 }
57871462 5114 else {
ad49de89 5115 if((branch_regs[i].dirty>>s1l)&1)
cf95b4f0 5116 emit_loadreg(dops[i].rs2,s1l);
57871462 5117 }
5118 if(s2l>=0)
ad49de89 5119 if((branch_regs[i].dirty>>s2l)&1)
cf95b4f0 5120 emit_loadreg(dops[i].rs2,s2l);
57871462 5121 #endif
5122 int hr=0;
5194fb95 5123 int addr=-1,alt=-1,ntaddr=-1;
57871462 5124 while(hr<HOST_REGS)
5125 {
5126 if(hr!=EXCLUDE_REG && hr!=HOST_CCREG &&
9de8a0c3 5127 branch_regs[i].regmap[hr]!=dops[i].rs1 &&
5128 branch_regs[i].regmap[hr]!=dops[i].rs2 )
57871462 5129 {
5130 addr=hr++;break;
5131 }
5132 hr++;
5133 }
5134 while(hr<HOST_REGS)
5135 {
5136 if(hr!=EXCLUDE_REG && hr!=HOST_CCREG &&
9de8a0c3 5137 branch_regs[i].regmap[hr]!=dops[i].rs1 &&
5138 branch_regs[i].regmap[hr]!=dops[i].rs2 )
57871462 5139 {
5140 alt=hr++;break;
5141 }
5142 hr++;
5143 }
ecca05e3 5144 if ((dops[i].opcode & 0x3e) == 6) // BLEZ/BGTZ needs another register
57871462 5145 {
5146 while(hr<HOST_REGS)
5147 {
5148 if(hr!=EXCLUDE_REG && hr!=HOST_CCREG &&
9de8a0c3 5149 branch_regs[i].regmap[hr]!=dops[i].rs1 &&
5150 branch_regs[i].regmap[hr]!=dops[i].rs2 )
57871462 5151 {
5152 ntaddr=hr;break;
5153 }
5154 hr++;
5155 }
5156 assert(hr<HOST_REGS);
5157 }
ecca05e3 5158 if (dops[i].opcode == 4) // BEQ
57871462 5159 {
5160 #ifdef HAVE_CMOV_IMM
ad49de89 5161 if(s2l>=0) emit_cmp(s1l,s2l);
5162 else emit_test(s1l,s1l);
277718fa 5163 emit_cmov2imm_e_ne_compact(cinfo[i].ba,start+i*4+8,addr);
ad49de89 5164 #else
277718fa 5165 emit_mov2imm_compact(cinfo[i].ba,addr,start+i*4+8,alt);
ad49de89 5166 if(s2l>=0) emit_cmp(s1l,s2l);
5167 else emit_test(s1l,s1l);
5168 emit_cmovne_reg(alt,addr);
57871462 5169 #endif
57871462 5170 }
ecca05e3 5171 else if (dops[i].opcode == 5) // BNE
57871462 5172 {
5173 #ifdef HAVE_CMOV_IMM
ad49de89 5174 if(s2l>=0) emit_cmp(s1l,s2l);
5175 else emit_test(s1l,s1l);
277718fa 5176 emit_cmov2imm_e_ne_compact(start+i*4+8,cinfo[i].ba,addr);
ad49de89 5177 #else
277718fa 5178 emit_mov2imm_compact(start+i*4+8,addr,cinfo[i].ba,alt);
ad49de89 5179 if(s2l>=0) emit_cmp(s1l,s2l);
5180 else emit_test(s1l,s1l);
5181 emit_cmovne_reg(alt,addr);
57871462 5182 #endif
57871462 5183 }
ecca05e3 5184 else if (dops[i].opcode == 6) // BLEZ
57871462 5185 {
277718fa 5186 //emit_movimm(cinfo[i].ba,alt);
57871462 5187 //emit_movimm(start+i*4+8,addr);
277718fa 5188 emit_mov2imm_compact(cinfo[i].ba,alt,start+i*4+8,addr);
57871462 5189 emit_cmpimm(s1l,1);
57871462 5190 emit_cmovl_reg(alt,addr);
57871462 5191 }
ecca05e3 5192 else if (dops[i].opcode == 7) // BGTZ
57871462 5193 {
277718fa 5194 //emit_movimm(cinfo[i].ba,addr);
57871462 5195 //emit_movimm(start+i*4+8,ntaddr);
277718fa 5196 emit_mov2imm_compact(cinfo[i].ba,addr,start+i*4+8,ntaddr);
57871462 5197 emit_cmpimm(s1l,1);
57871462 5198 emit_cmovl_reg(ntaddr,addr);
57871462 5199 }
ecca05e3 5200 else if (dops[i].itype == SJUMP) // BLTZ/BGEZ
57871462 5201 {
277718fa 5202 //emit_movimm(cinfo[i].ba,alt);
57871462 5203 //emit_movimm(start+i*4+8,addr);
de6dbc52 5204 if (dops[i].rs1) {
5205 emit_mov2imm_compact(cinfo[i].ba,
5206 (dops[i].opcode2 & 1) ? addr : alt, start + i*4 + 8,
5207 (dops[i].opcode2 & 1) ? alt : addr);
5208 emit_test(s1l,s1l);
5209 emit_cmovs_reg(alt,addr);
5210 }
5211 else
5212 emit_movimm((dops[i].opcode2 & 1) ? cinfo[i].ba : start + i*4 + 8, addr);
57871462 5213 }
ecca05e3 5214 emit_writeword(addr, &pcaddr);
57871462 5215 }
5216 else
cf95b4f0 5217 if(dops[i].itype==RJUMP)
57871462 5218 {
cf95b4f0 5219 int r=get_reg(branch_regs[i].regmap,dops[i].rs1);
4919de1e 5220 if (ds_writes_rjump_rs(i)) {
57871462 5221 r=get_reg(branch_regs[i].regmap,RTEMP);
5222 }
643aeae3 5223 emit_writeword(r,&pcaddr);
57871462 5224 }
7c3a5182 5225 else {SysPrintf("Unknown branch type in do_ccstub\n");abort();}
57871462 5226 }
5227 // Update cycle count
5228 assert(branch_regs[i].regmap[HOST_CCREG]==CCREG||branch_regs[i].regmap[HOST_CCREG]==-1);
2330734f 5229 if(stubs[n].a) emit_addimm(HOST_CCREG,(int)stubs[n].a,HOST_CCREG);
2a014d73 5230 emit_far_call(cc_interrupt);
2330734f 5231 if(stubs[n].a) emit_addimm(HOST_CCREG,-(int)stubs[n].a,HOST_CCREG);
b14b6a8f 5232 if(stubs[n].d==TAKEN) {
277718fa 5233 if(internal_branch(cinfo[i].ba))
5234 load_needed_regs(branch_regs[i].regmap,regs[(cinfo[i].ba-start)>>2].regmap_entry);
cf95b4f0 5235 else if(dops[i].itype==RJUMP) {
57871462 5236 if(get_reg(branch_regs[i].regmap,RTEMP)>=0)
643aeae3 5237 emit_readword(&pcaddr,get_reg(branch_regs[i].regmap,RTEMP));
57871462 5238 else
cf95b4f0 5239 emit_loadreg(dops[i].rs1,get_reg(branch_regs[i].regmap,dops[i].rs1));
57871462 5240 }
b14b6a8f 5241 }else if(stubs[n].d==NOTTAKEN) {
57871462 5242 if(i<slen-2) load_needed_regs(branch_regs[i].regmap,regmap_pre[i+2]);
5243 else load_all_regs(branch_regs[i].regmap);
57871462 5244 }else{
5245 load_all_regs(branch_regs[i].regmap);
5246 }
d1e4ebd9 5247 if (stubs[n].retaddr)
5248 emit_jmp(stubs[n].retaddr);
5249 else
5250 do_jump_vaddr(stubs[n].e);
57871462 5251}
5252
104df9d3 5253static void add_to_linker(void *addr, u_int target, int is_internal)
57871462 5254{
643aeae3 5255 assert(linkcount < ARRAY_SIZE(link_addr));
5256 link_addr[linkcount].addr = addr;
5257 link_addr[linkcount].target = target;
104df9d3 5258 link_addr[linkcount].internal = is_internal;
57871462 5259 linkcount++;
5260}
5261
eba830cd 5262static void ujump_assemble_write_ra(int i)
5263{
5264 int rt;
5265 unsigned int return_address;
5266 rt=get_reg(branch_regs[i].regmap,31);
de6dbc52 5267 //assem_debug("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
eba830cd 5268 //assert(rt>=0);
5269 return_address=start+i*4+8;
5270 if(rt>=0) {
5271 #ifdef USE_MINI_HT
cf95b4f0 5272 if(internal_branch(return_address)&&dops[i+1].rt1!=31) {
eba830cd 5273 int temp=-1; // note: must be ds-safe
5274 #ifdef HOST_TEMPREG
5275 temp=HOST_TEMPREG;
5276 #endif
5277 if(temp>=0) do_miniht_insert(return_address,rt,temp);
5278 else emit_movimm(return_address,rt);
5279 }
5280 else
5281 #endif
5282 {
5283 #ifdef REG_PREFETCH
9f51b4b9 5284 if(temp>=0)
eba830cd 5285 {
643aeae3 5286 if(i_regmap[temp]!=PTEMP) emit_movimm((uintptr_t)hash_table_get(return_address),temp);
eba830cd 5287 }
5288 #endif
de6dbc52 5289 if (!((regs[i].loadedconst >> rt) & 1))
5290 emit_movimm(return_address, rt); // PC into link register
eba830cd 5291 #ifdef IMM_PREFETCH
df4dc2b1 5292 emit_prefetch(hash_table_get(return_address));
eba830cd 5293 #endif
5294 }
5295 }
5296}
5297
2330734f 5298static void ujump_assemble(int i, const struct regstat *i_regs)
57871462 5299{
277718fa 5300 if(i==(cinfo[i].ba-start)>>2) assem_debug("idle loop\n");
57871462 5301 address_generation(i+1,i_regs,regs[i].regmap_entry);
5302 #ifdef REG_PREFETCH
5303 int temp=get_reg(branch_regs[i].regmap,PTEMP);
cf95b4f0 5304 if(dops[i].rt1==31&&temp>=0)
57871462 5305 {
581335b0 5306 signed char *i_regmap=i_regs->regmap;
57871462 5307 int return_address=start+i*4+8;
9f51b4b9 5308 if(get_reg(branch_regs[i].regmap,31)>0)
643aeae3 5309 if(i_regmap[temp]==PTEMP) emit_movimm((uintptr_t)hash_table_get(return_address),temp);
57871462 5310 }
5311 #endif
de6dbc52 5312 if (dops[i].rt1 == 31)
eba830cd 5313 ujump_assemble_write_ra(i); // writeback ra for DS
4ef8f67d 5314 ds_assemble(i+1,i_regs);
5315 uint64_t bc_unneeded=branch_regs[i].u;
cf95b4f0 5316 bc_unneeded|=1|(1LL<<dops[i].rt1);
ad49de89 5317 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,bc_unneeded);
53358c1d 5318 load_reg(regs[i].regmap,branch_regs[i].regmap,CCREG);
57871462 5319 int cc,adj;
5320 cc=get_reg(branch_regs[i].regmap,CCREG);
5321 assert(cc==HOST_CCREG);
277718fa 5322 store_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,cinfo[i].ba);
57871462 5323 #ifdef REG_PREFETCH
cf95b4f0 5324 if(dops[i].rt1==31&&temp>=0) emit_prefetchreg(temp);
57871462 5325 #endif
277718fa 5326 do_cc(i,branch_regs[i].regmap,&adj,cinfo[i].ba,TAKEN,0);
5327 if(adj) emit_addimm(cc, cinfo[i].ccadj + CLOCK_ADJUST(2) - adj, cc);
5328 load_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,cinfo[i].ba);
5329 if(internal_branch(cinfo[i].ba))
57871462 5330 assem_debug("branch: internal\n");
5331 else
5332 assem_debug("branch: external\n");
277718fa 5333 if (internal_branch(cinfo[i].ba) && dops[(cinfo[i].ba-start)>>2].is_ds) {
57871462 5334 ds_assemble_entry(i);
5335 }
5336 else {
277718fa 5337 add_to_linker(out,cinfo[i].ba,internal_branch(cinfo[i].ba));
57871462 5338 emit_jmp(0);
5339 }
5340}
5341
eba830cd 5342static void rjump_assemble_write_ra(int i)
5343{
5344 int rt,return_address;
a5cd72d0 5345 rt=get_reg_w(branch_regs[i].regmap, dops[i].rt1);
de6dbc52 5346 //assem_debug("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
eba830cd 5347 assert(rt>=0);
5348 return_address=start+i*4+8;
5349 #ifdef REG_PREFETCH
9f51b4b9 5350 if(temp>=0)
eba830cd 5351 {
643aeae3 5352 if(i_regmap[temp]!=PTEMP) emit_movimm((uintptr_t)hash_table_get(return_address),temp);
eba830cd 5353 }
5354 #endif
de6dbc52 5355 if (!((regs[i].loadedconst >> rt) & 1))
5356 emit_movimm(return_address, rt); // PC into link register
eba830cd 5357 #ifdef IMM_PREFETCH
df4dc2b1 5358 emit_prefetch(hash_table_get(return_address));
eba830cd 5359 #endif
5360}
5361
2330734f 5362static void rjump_assemble(int i, const struct regstat *i_regs)
57871462 5363{
57871462 5364 int temp;
581335b0 5365 int rs,cc;
cf95b4f0 5366 rs=get_reg(branch_regs[i].regmap,dops[i].rs1);
57871462 5367 assert(rs>=0);
4919de1e 5368 if (ds_writes_rjump_rs(i)) {
57871462 5369 // Delay slot abuse, make a copy of the branch address register
5370 temp=get_reg(branch_regs[i].regmap,RTEMP);
5371 assert(temp>=0);
5372 assert(regs[i].regmap[temp]==RTEMP);
5373 emit_mov(rs,temp);
5374 rs=temp;
5375 }
5376 address_generation(i+1,i_regs,regs[i].regmap_entry);
5377 #ifdef REG_PREFETCH
cf95b4f0 5378 if(dops[i].rt1==31)
57871462 5379 {
5380 if((temp=get_reg(branch_regs[i].regmap,PTEMP))>=0) {
581335b0 5381 signed char *i_regmap=i_regs->regmap;
57871462 5382 int return_address=start+i*4+8;
643aeae3 5383 if(i_regmap[temp]==PTEMP) emit_movimm((uintptr_t)hash_table_get(return_address),temp);
57871462 5384 }
5385 }
5386 #endif
5387 #ifdef USE_MINI_HT
cf95b4f0 5388 if(dops[i].rs1==31) {
57871462 5389 int rh=get_reg(regs[i].regmap,RHASH);
5390 if(rh>=0) do_preload_rhash(rh);
5391 }
5392 #endif
de6dbc52 5393 if (dops[i].rt1 != 0)
eba830cd 5394 rjump_assemble_write_ra(i);
d5910d5d 5395 ds_assemble(i+1,i_regs);
5396 uint64_t bc_unneeded=branch_regs[i].u;
cf95b4f0 5397 bc_unneeded|=1|(1LL<<dops[i].rt1);
5398 bc_unneeded&=~(1LL<<dops[i].rs1);
ad49de89 5399 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,bc_unneeded);
cf95b4f0 5400 load_regs(regs[i].regmap,branch_regs[i].regmap,dops[i].rs1,CCREG);
57871462 5401 cc=get_reg(branch_regs[i].regmap,CCREG);
5402 assert(cc==HOST_CCREG);
581335b0 5403 (void)cc;
57871462 5404 #ifdef USE_MINI_HT
5405 int rh=get_reg(branch_regs[i].regmap,RHASH);
5406 int ht=get_reg(branch_regs[i].regmap,RHTBL);
cf95b4f0 5407 if(dops[i].rs1==31) {
57871462 5408 if(regs[i].regmap[rh]!=RHASH) do_preload_rhash(rh);
5409 do_preload_rhtbl(ht);
5410 do_rhash(rs,rh);
5411 }
5412 #endif
ad49de89 5413 store_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,-1);
57871462 5414 #ifdef DESTRUCTIVE_WRITEBACK
ad49de89 5415 if((branch_regs[i].dirty>>rs)&1) {
cf95b4f0 5416 if(dops[i].rs1!=dops[i+1].rt1&&dops[i].rs1!=dops[i+1].rt2) {
5417 emit_loadreg(dops[i].rs1,rs);
57871462 5418 }
5419 }
5420 #endif
5421 #ifdef REG_PREFETCH
cf95b4f0 5422 if(dops[i].rt1==31&&temp>=0) emit_prefetchreg(temp);
57871462 5423 #endif
5424 #ifdef USE_MINI_HT
cf95b4f0 5425 if(dops[i].rs1==31) {
57871462 5426 do_miniht_load(ht,rh);
5427 }
5428 #endif
5429 //do_cc(i,branch_regs[i].regmap,&adj,-1,TAKEN);
277718fa 5430 //if(adj) emit_addimm(cc,2*(cinfo[i].ccadj+2-adj),cc); // ??? - Shouldn't happen
57871462 5431 //assert(adj==0);
277718fa 5432 emit_addimm_and_set_flags(cinfo[i].ccadj + CLOCK_ADJUST(2), HOST_CCREG);
d1e4ebd9 5433 add_stub(CC_STUB,out,NULL,0,i,-1,TAKEN,rs);
a5cd72d0 5434 if (dops[i+1].itype == RFE)
911f2d55 5435 // special case for RFE
5436 emit_jmp(0);
5437 else
71e490c5 5438 emit_jns(0);
ad49de89 5439 //load_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,-1);
57871462 5440 #ifdef USE_MINI_HT
cf95b4f0 5441 if(dops[i].rs1==31) {
57871462 5442 do_miniht_jump(rs,rh,ht);
5443 }
5444 else
5445 #endif
5446 {
d1e4ebd9 5447 do_jump_vaddr(rs);
57871462 5448 }
57871462 5449 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
cf95b4f0 5450 if(dops[i].rt1!=31&&i<slen-2&&(((u_int)out)&7)) emit_mov(13,13);
57871462 5451 #endif
5452}
5453
2330734f 5454static void cjump_assemble(int i, const struct regstat *i_regs)
57871462 5455{
2330734f 5456 const signed char *i_regmap = i_regs->regmap;
57871462 5457 int cc;
5458 int match;
277718fa 5459 match=match_bt(branch_regs[i].regmap,branch_regs[i].dirty,cinfo[i].ba);
57871462 5460 assem_debug("match=%d\n",match);
ad49de89 5461 int s1l,s2l;
57871462 5462 int unconditional=0,nop=0;
57871462 5463 int invert=0;
277718fa 5464 int internal=internal_branch(cinfo[i].ba);
5465 if(i==(cinfo[i].ba-start)>>2) assem_debug("idle loop\n");
57871462 5466 if(!match) invert=1;
5467 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
277718fa 5468 if(i>(cinfo[i].ba-start)>>2) invert=1;
57871462 5469 #endif
3968e69e 5470 #ifdef __aarch64__
5471 invert=1; // because of near cond. branches
5472 #endif
9f51b4b9 5473
cf95b4f0 5474 if(dops[i].ooo) {
5475 s1l=get_reg(branch_regs[i].regmap,dops[i].rs1);
5476 s2l=get_reg(branch_regs[i].regmap,dops[i].rs2);
57871462 5477 }
5478 else {
cf95b4f0 5479 s1l=get_reg(i_regmap,dops[i].rs1);
5480 s2l=get_reg(i_regmap,dops[i].rs2);
57871462 5481 }
cf95b4f0 5482 if(dops[i].rs1==0&&dops[i].rs2==0)
57871462 5483 {
cf95b4f0 5484 if(dops[i].opcode&1) nop=1;
57871462 5485 else unconditional=1;
cf95b4f0 5486 //assert(dops[i].opcode!=5);
5487 //assert(dops[i].opcode!=7);
5488 //assert(dops[i].opcode!=0x15);
5489 //assert(dops[i].opcode!=0x17);
57871462 5490 }
cf95b4f0 5491 else if(dops[i].rs1==0)
57871462 5492 {
ad49de89 5493 s1l=s2l;
5494 s2l=-1;
57871462 5495 }
cf95b4f0 5496 else if(dops[i].rs2==0)
57871462 5497 {
ad49de89 5498 s2l=-1;
57871462 5499 }
5500
cf95b4f0 5501 if(dops[i].ooo) {
57871462 5502 // Out of order execution (delay slot first)
5503 //printf("OOOE\n");
5504 address_generation(i+1,i_regs,regs[i].regmap_entry);
5505 ds_assemble(i+1,i_regs);
5506 int adj;
5507 uint64_t bc_unneeded=branch_regs[i].u;
cf95b4f0 5508 bc_unneeded&=~((1LL<<dops[i].rs1)|(1LL<<dops[i].rs2));
57871462 5509 bc_unneeded|=1;
ad49de89 5510 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,bc_unneeded);
cf95b4f0 5511 load_regs(regs[i].regmap,branch_regs[i].regmap,dops[i].rs1,dops[i].rs2);
53358c1d 5512 load_reg(regs[i].regmap,branch_regs[i].regmap,CCREG);
57871462 5513 cc=get_reg(branch_regs[i].regmap,CCREG);
5514 assert(cc==HOST_CCREG);
9f51b4b9 5515 if(unconditional)
277718fa 5516 store_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,cinfo[i].ba);
5517 //do_cc(i,branch_regs[i].regmap,&adj,unconditional?cinfo[i].ba:-1,unconditional);
57871462 5518 //assem_debug("cycle count (adj)\n");
5519 if(unconditional) {
277718fa 5520 do_cc(i,branch_regs[i].regmap,&adj,cinfo[i].ba,TAKEN,0);
5521 if(i!=(cinfo[i].ba-start)>>2 || source[i+1]!=0) {
5522 if(adj) emit_addimm(cc, cinfo[i].ccadj + CLOCK_ADJUST(2) - adj, cc);
5523 load_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,cinfo[i].ba);
57871462 5524 if(internal)
5525 assem_debug("branch: internal\n");
5526 else
5527 assem_debug("branch: external\n");
277718fa 5528 if (internal && dops[(cinfo[i].ba-start)>>2].is_ds) {
57871462 5529 ds_assemble_entry(i);
5530 }
5531 else {
277718fa 5532 add_to_linker(out,cinfo[i].ba,internal);
57871462 5533 emit_jmp(0);
5534 }
5535 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5536 if(((u_int)out)&7) emit_addnop(0);
5537 #endif
5538 }
5539 }
5540 else if(nop) {
277718fa 5541 emit_addimm_and_set_flags(cinfo[i].ccadj + CLOCK_ADJUST(2), cc);
b14b6a8f 5542 void *jaddr=out;
57871462 5543 emit_jns(0);
b14b6a8f 5544 add_stub(CC_STUB,jaddr,out,0,i,start+i*4+8,NOTTAKEN,0);
57871462 5545 }
5546 else {
df4dc2b1 5547 void *taken = NULL, *nottaken = NULL, *nottaken1 = NULL;
57871462 5548 do_cc(i,branch_regs[i].regmap,&adj,-1,0,invert);
277718fa 5549 if(adj&&!invert) emit_addimm(cc, cinfo[i].ccadj + CLOCK_ADJUST(2) - adj, cc);
9f51b4b9 5550
57871462 5551 //printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5552 assert(s1l>=0);
cf95b4f0 5553 if(dops[i].opcode==4) // BEQ
57871462 5554 {
5555 if(s2l>=0) emit_cmp(s1l,s2l);
5556 else emit_test(s1l,s1l);
5557 if(invert){
df4dc2b1 5558 nottaken=out;
7c3a5182 5559 emit_jne(DJT_1);
57871462 5560 }else{
277718fa 5561 add_to_linker(out,cinfo[i].ba,internal);
57871462 5562 emit_jeq(0);
5563 }
5564 }
cf95b4f0 5565 if(dops[i].opcode==5) // BNE
57871462 5566 {
5567 if(s2l>=0) emit_cmp(s1l,s2l);
5568 else emit_test(s1l,s1l);
5569 if(invert){
df4dc2b1 5570 nottaken=out;
7c3a5182 5571 emit_jeq(DJT_1);
57871462 5572 }else{
277718fa 5573 add_to_linker(out,cinfo[i].ba,internal);
57871462 5574 emit_jne(0);
5575 }
5576 }
cf95b4f0 5577 if(dops[i].opcode==6) // BLEZ
57871462 5578 {
5579 emit_cmpimm(s1l,1);
5580 if(invert){
df4dc2b1 5581 nottaken=out;
7c3a5182 5582 emit_jge(DJT_1);
57871462 5583 }else{
277718fa 5584 add_to_linker(out,cinfo[i].ba,internal);
57871462 5585 emit_jl(0);
5586 }
5587 }
cf95b4f0 5588 if(dops[i].opcode==7) // BGTZ
57871462 5589 {
5590 emit_cmpimm(s1l,1);
5591 if(invert){
df4dc2b1 5592 nottaken=out;
7c3a5182 5593 emit_jl(DJT_1);
57871462 5594 }else{
277718fa 5595 add_to_linker(out,cinfo[i].ba,internal);
57871462 5596 emit_jge(0);
5597 }
5598 }
5599 if(invert) {
df4dc2b1 5600 if(taken) set_jump_target(taken, out);
57871462 5601 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
277718fa 5602 if (match && (!internal || !dops[(cinfo[i].ba-start)>>2].is_ds)) {
57871462 5603 if(adj) {
2330734f 5604 emit_addimm(cc,-adj,cc);
277718fa 5605 add_to_linker(out,cinfo[i].ba,internal);
57871462 5606 }else{
5607 emit_addnop(13);
277718fa 5608 add_to_linker(out,cinfo[i].ba,internal*2);
57871462 5609 }
5610 emit_jmp(0);
5611 }else
5612 #endif
5613 {
2330734f 5614 if(adj) emit_addimm(cc,-adj,cc);
277718fa 5615 store_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,cinfo[i].ba);
5616 load_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,cinfo[i].ba);
57871462 5617 if(internal)
5618 assem_debug("branch: internal\n");
5619 else
5620 assem_debug("branch: external\n");
277718fa 5621 if (internal && dops[(cinfo[i].ba - start) >> 2].is_ds) {
57871462 5622 ds_assemble_entry(i);
5623 }
5624 else {
277718fa 5625 add_to_linker(out,cinfo[i].ba,internal);
57871462 5626 emit_jmp(0);
5627 }
5628 }
df4dc2b1 5629 set_jump_target(nottaken, out);
57871462 5630 }
5631
df4dc2b1 5632 if(nottaken1) set_jump_target(nottaken1, out);
57871462 5633 if(adj) {
2330734f 5634 if(!invert) emit_addimm(cc,adj,cc);
57871462 5635 }
5636 } // (!unconditional)
5637 } // if(ooo)
5638 else
5639 {
5640 // In-order execution (branch first)
df4dc2b1 5641 void *taken = NULL, *nottaken = NULL, *nottaken1 = NULL;
57871462 5642 if(!unconditional&&!nop) {
57871462 5643 //printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5644 assert(s1l>=0);
cf95b4f0 5645 if((dops[i].opcode&0x2f)==4) // BEQ
57871462 5646 {
5647 if(s2l>=0) emit_cmp(s1l,s2l);
5648 else emit_test(s1l,s1l);
df4dc2b1 5649 nottaken=out;
7c3a5182 5650 emit_jne(DJT_2);
57871462 5651 }
cf95b4f0 5652 if((dops[i].opcode&0x2f)==5) // BNE
57871462 5653 {
5654 if(s2l>=0) emit_cmp(s1l,s2l);
5655 else emit_test(s1l,s1l);
df4dc2b1 5656 nottaken=out;
7c3a5182 5657 emit_jeq(DJT_2);
57871462 5658 }
cf95b4f0 5659 if((dops[i].opcode&0x2f)==6) // BLEZ
57871462 5660 {
5661 emit_cmpimm(s1l,1);
df4dc2b1 5662 nottaken=out;
7c3a5182 5663 emit_jge(DJT_2);
57871462 5664 }
cf95b4f0 5665 if((dops[i].opcode&0x2f)==7) // BGTZ
57871462 5666 {
5667 emit_cmpimm(s1l,1);
df4dc2b1 5668 nottaken=out;
7c3a5182 5669 emit_jl(DJT_2);
57871462 5670 }
5671 } // if(!unconditional)
5672 int adj;
5673 uint64_t ds_unneeded=branch_regs[i].u;
cf95b4f0 5674 ds_unneeded&=~((1LL<<dops[i+1].rs1)|(1LL<<dops[i+1].rs2));
57871462 5675 ds_unneeded|=1;
57871462 5676 // branch taken
5677 if(!nop) {
df4dc2b1 5678 if(taken) set_jump_target(taken, out);
57871462 5679 assem_debug("1:\n");
ad49de89 5680 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,ds_unneeded);
57871462 5681 // load regs
cf95b4f0 5682 load_regs(regs[i].regmap,branch_regs[i].regmap,dops[i+1].rs1,dops[i+1].rs2);
57871462 5683 address_generation(i+1,&branch_regs[i],0);
37387d8b 5684 if (ram_offset)
53358c1d 5685 load_reg(regs[i].regmap,branch_regs[i].regmap,ROREG);
ad49de89 5686 load_regs(regs[i].regmap,branch_regs[i].regmap,CCREG,INVCP);
57871462 5687 ds_assemble(i+1,&branch_regs[i]);
5688 cc=get_reg(branch_regs[i].regmap,CCREG);
5689 if(cc==-1) {
5690 emit_loadreg(CCREG,cc=HOST_CCREG);
5691 // CHECK: Is the following instruction (fall thru) allocated ok?
5692 }
5693 assert(cc==HOST_CCREG);
277718fa 5694 store_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,cinfo[i].ba);
5695 do_cc(i,i_regmap,&adj,cinfo[i].ba,TAKEN,0);
57871462 5696 assem_debug("cycle count (adj)\n");
277718fa 5697 if(adj) emit_addimm(cc, cinfo[i].ccadj + CLOCK_ADJUST(2) - adj, cc);
5698 load_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,cinfo[i].ba);
57871462 5699 if(internal)
5700 assem_debug("branch: internal\n");
5701 else
5702 assem_debug("branch: external\n");
277718fa 5703 if (internal && dops[(cinfo[i].ba - start) >> 2].is_ds) {
57871462 5704 ds_assemble_entry(i);
5705 }
5706 else {
277718fa 5707 add_to_linker(out,cinfo[i].ba,internal);
57871462 5708 emit_jmp(0);
5709 }
5710 }
5711 // branch not taken
57871462 5712 if(!unconditional) {
df4dc2b1 5713 if(nottaken1) set_jump_target(nottaken1, out);
5714 set_jump_target(nottaken, out);
57871462 5715 assem_debug("2:\n");
fe807a8a 5716 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,ds_unneeded);
37387d8b 5717 // load regs
fe807a8a 5718 load_regs(regs[i].regmap,branch_regs[i].regmap,dops[i+1].rs1,dops[i+1].rs2);
5719 address_generation(i+1,&branch_regs[i],0);
37387d8b 5720 if (ram_offset)
53358c1d 5721 load_reg(regs[i].regmap,branch_regs[i].regmap,ROREG);
37387d8b 5722 load_regs(regs[i].regmap,branch_regs[i].regmap,CCREG,INVCP);
fe807a8a 5723 ds_assemble(i+1,&branch_regs[i]);
57871462 5724 cc=get_reg(branch_regs[i].regmap,CCREG);
fe807a8a 5725 if (cc == -1) {
57871462 5726 // Cycle count isn't in a register, temporarily load it then write it out
5727 emit_loadreg(CCREG,HOST_CCREG);
277718fa 5728 emit_addimm_and_set_flags(cinfo[i].ccadj + CLOCK_ADJUST(2), HOST_CCREG);
b14b6a8f 5729 void *jaddr=out;
57871462 5730 emit_jns(0);
b14b6a8f 5731 add_stub(CC_STUB,jaddr,out,0,i,start+i*4+8,NOTTAKEN,0);
57871462 5732 emit_storereg(CCREG,HOST_CCREG);
5733 }
5734 else{
5735 cc=get_reg(i_regmap,CCREG);
5736 assert(cc==HOST_CCREG);
277718fa 5737 emit_addimm_and_set_flags(cinfo[i].ccadj + CLOCK_ADJUST(2), cc);
b14b6a8f 5738 void *jaddr=out;
57871462 5739 emit_jns(0);
fe807a8a 5740 add_stub(CC_STUB,jaddr,out,0,i,start+i*4+8,NOTTAKEN,0);
57871462 5741 }
5742 }
5743 }
5744}
5745
2330734f 5746static void sjump_assemble(int i, const struct regstat *i_regs)
57871462 5747{
2330734f 5748 const signed char *i_regmap = i_regs->regmap;
57871462 5749 int cc;
5750 int match;
277718fa 5751 match=match_bt(branch_regs[i].regmap,branch_regs[i].dirty,cinfo[i].ba);
2acc46cd 5752 assem_debug("smatch=%d ooo=%d\n", match, dops[i].ooo);
ad49de89 5753 int s1l;
57871462 5754 int unconditional=0,nevertaken=0;
57871462 5755 int invert=0;
277718fa 5756 int internal=internal_branch(cinfo[i].ba);
5757 if(i==(cinfo[i].ba-start)>>2) assem_debug("idle loop\n");
57871462 5758 if(!match) invert=1;
5759 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
277718fa 5760 if(i>(cinfo[i].ba-start)>>2) invert=1;
57871462 5761 #endif
3968e69e 5762 #ifdef __aarch64__
5763 invert=1; // because of near cond. branches
5764 #endif
57871462 5765
cf95b4f0 5766 //if(dops[i].opcode2>=0x10) return; // FIXME (BxxZAL)
5767 //assert(dops[i].opcode2<0x10||dops[i].rs1==0); // FIXME (BxxZAL)
57871462 5768
cf95b4f0 5769 if(dops[i].ooo) {
5770 s1l=get_reg(branch_regs[i].regmap,dops[i].rs1);
57871462 5771 }
5772 else {
cf95b4f0 5773 s1l=get_reg(i_regmap,dops[i].rs1);
57871462 5774 }
cf95b4f0 5775 if(dops[i].rs1==0)
57871462 5776 {
cf95b4f0 5777 if(dops[i].opcode2&1) unconditional=1;
57871462 5778 else nevertaken=1;
5779 // These are never taken (r0 is never less than zero)
cf95b4f0 5780 //assert(dops[i].opcode2!=0);
5781 //assert(dops[i].opcode2!=2);
5782 //assert(dops[i].opcode2!=0x10);
5783 //assert(dops[i].opcode2!=0x12);
57871462 5784 }
57871462 5785
cf95b4f0 5786 if(dops[i].ooo) {
57871462 5787 // Out of order execution (delay slot first)
5788 //printf("OOOE\n");
5789 address_generation(i+1,i_regs,regs[i].regmap_entry);
5790 ds_assemble(i+1,i_regs);
5791 int adj;
5792 uint64_t bc_unneeded=branch_regs[i].u;
cf95b4f0 5793 bc_unneeded&=~((1LL<<dops[i].rs1)|(1LL<<dops[i].rs2));
57871462 5794 bc_unneeded|=1;
ad49de89 5795 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,bc_unneeded);
cf95b4f0 5796 load_regs(regs[i].regmap,branch_regs[i].regmap,dops[i].rs1,dops[i].rs1);
53358c1d 5797 load_reg(regs[i].regmap,branch_regs[i].regmap,CCREG);
cf95b4f0 5798 if(dops[i].rt1==31) {
57871462 5799 int rt,return_address;
57871462 5800 rt=get_reg(branch_regs[i].regmap,31);
de6dbc52 5801 //assem_debug("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
57871462 5802 if(rt>=0) {
5803 // Save the PC even if the branch is not taken
5804 return_address=start+i*4+8;
5805 emit_movimm(return_address,rt); // PC into link register
5806 #ifdef IMM_PREFETCH
df4dc2b1 5807 if(!nevertaken) emit_prefetch(hash_table_get(return_address));
57871462 5808 #endif
5809 }
5810 }
5811 cc=get_reg(branch_regs[i].regmap,CCREG);
5812 assert(cc==HOST_CCREG);
9f51b4b9 5813 if(unconditional)
277718fa 5814 store_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,cinfo[i].ba);
5815 //do_cc(i,branch_regs[i].regmap,&adj,unconditional?cinfo[i].ba:-1,unconditional);
57871462 5816 assem_debug("cycle count (adj)\n");
5817 if(unconditional) {
277718fa 5818 do_cc(i,branch_regs[i].regmap,&adj,cinfo[i].ba,TAKEN,0);
5819 if(i!=(cinfo[i].ba-start)>>2 || source[i+1]!=0) {
5820 if(adj) emit_addimm(cc, cinfo[i].ccadj + CLOCK_ADJUST(2) - adj, cc);
5821 load_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,cinfo[i].ba);
57871462 5822 if(internal)
5823 assem_debug("branch: internal\n");
5824 else
5825 assem_debug("branch: external\n");
277718fa 5826 if (internal && dops[(cinfo[i].ba - start) >> 2].is_ds) {
57871462 5827 ds_assemble_entry(i);
5828 }
5829 else {
277718fa 5830 add_to_linker(out,cinfo[i].ba,internal);
57871462 5831 emit_jmp(0);
5832 }
5833 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5834 if(((u_int)out)&7) emit_addnop(0);
5835 #endif
5836 }
5837 }
5838 else if(nevertaken) {
277718fa 5839 emit_addimm_and_set_flags(cinfo[i].ccadj + CLOCK_ADJUST(2), cc);
b14b6a8f 5840 void *jaddr=out;
57871462 5841 emit_jns(0);
b14b6a8f 5842 add_stub(CC_STUB,jaddr,out,0,i,start+i*4+8,NOTTAKEN,0);
57871462 5843 }
5844 else {
df4dc2b1 5845 void *nottaken = NULL;
57871462 5846 do_cc(i,branch_regs[i].regmap,&adj,-1,0,invert);
277718fa 5847 if(adj&&!invert) emit_addimm(cc, cinfo[i].ccadj + CLOCK_ADJUST(2) - adj, cc);
57871462 5848 {
5849 assert(s1l>=0);
ecca05e3 5850 if ((dops[i].opcode2 & 1) == 0) // BLTZ/BLTZAL
57871462 5851 {
5852 emit_test(s1l,s1l);
5853 if(invert){
df4dc2b1 5854 nottaken=out;
7c3a5182 5855 emit_jns(DJT_1);
57871462 5856 }else{
277718fa 5857 add_to_linker(out,cinfo[i].ba,internal);
57871462 5858 emit_js(0);
5859 }
5860 }
ecca05e3 5861 else // BGEZ/BGEZAL
57871462 5862 {
5863 emit_test(s1l,s1l);
5864 if(invert){
df4dc2b1 5865 nottaken=out;
7c3a5182 5866 emit_js(DJT_1);
57871462 5867 }else{
277718fa 5868 add_to_linker(out,cinfo[i].ba,internal);
57871462 5869 emit_jns(0);
5870 }
5871 }
ad49de89 5872 }
9f51b4b9 5873
57871462 5874 if(invert) {
5875 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
277718fa 5876 if (match && (!internal || !dops[(cinfo[i].ba - start) >> 2].is_ds)) {
57871462 5877 if(adj) {
2330734f 5878 emit_addimm(cc,-adj,cc);
277718fa 5879 add_to_linker(out,cinfo[i].ba,internal);
57871462 5880 }else{
5881 emit_addnop(13);
277718fa 5882 add_to_linker(out,cinfo[i].ba,internal*2);
57871462 5883 }
5884 emit_jmp(0);
5885 }else
5886 #endif
5887 {
2330734f 5888 if(adj) emit_addimm(cc,-adj,cc);
277718fa 5889 store_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,cinfo[i].ba);
5890 load_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,cinfo[i].ba);
57871462 5891 if(internal)
5892 assem_debug("branch: internal\n");
5893 else
5894 assem_debug("branch: external\n");
277718fa 5895 if (internal && dops[(cinfo[i].ba - start) >> 2].is_ds) {
57871462 5896 ds_assemble_entry(i);
5897 }
5898 else {
277718fa 5899 add_to_linker(out,cinfo[i].ba,internal);
57871462 5900 emit_jmp(0);
5901 }
5902 }
df4dc2b1 5903 set_jump_target(nottaken, out);
57871462 5904 }
5905
5906 if(adj) {
2330734f 5907 if(!invert) emit_addimm(cc,adj,cc);
57871462 5908 }
5909 } // (!unconditional)
5910 } // if(ooo)
5911 else
5912 {
5913 // In-order execution (branch first)
5914 //printf("IOE\n");
df4dc2b1 5915 void *nottaken = NULL;
de6dbc52 5916 if (!unconditional && !nevertaken) {
ecca05e3 5917 assert(s1l >= 0);
5918 emit_test(s1l, s1l);
5919 }
5920 if (dops[i].rt1 == 31) {
5921 int rt, return_address;
5922 rt = get_reg(branch_regs[i].regmap,31);
5923 if(rt >= 0) {
a6491170 5924 // Save the PC even if the branch is not taken
ecca05e3 5925 return_address = start + i*4+8;
5926 emit_movimm(return_address, rt); // PC into link register
a6491170 5927 #ifdef IMM_PREFETCH
df4dc2b1 5928 emit_prefetch(hash_table_get(return_address));
a6491170 5929 #endif
5930 }
5931 }
de6dbc52 5932 if (!unconditional && !nevertaken) {
ecca05e3 5933 nottaken = out;
5934 if (!(dops[i].opcode2 & 1)) // BLTZ/BLTZAL
5935 emit_jns(DJT_1);
5936 else // BGEZ/BGEZAL
5937 emit_js(DJT_1);
5938 }
57871462 5939 int adj;
5940 uint64_t ds_unneeded=branch_regs[i].u;
cf95b4f0 5941 ds_unneeded&=~((1LL<<dops[i+1].rs1)|(1LL<<dops[i+1].rs2));
57871462 5942 ds_unneeded|=1;
57871462 5943 // branch taken
5944 if(!nevertaken) {
5945 //assem_debug("1:\n");
ad49de89 5946 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,ds_unneeded);
57871462 5947 // load regs
cf95b4f0 5948 load_regs(regs[i].regmap,branch_regs[i].regmap,dops[i+1].rs1,dops[i+1].rs2);
57871462 5949 address_generation(i+1,&branch_regs[i],0);
37387d8b 5950 if (ram_offset)
53358c1d 5951 load_reg(regs[i].regmap,branch_regs[i].regmap,ROREG);
ad49de89 5952 load_regs(regs[i].regmap,branch_regs[i].regmap,CCREG,INVCP);
57871462 5953 ds_assemble(i+1,&branch_regs[i]);
5954 cc=get_reg(branch_regs[i].regmap,CCREG);
5955 if(cc==-1) {
5956 emit_loadreg(CCREG,cc=HOST_CCREG);
5957 // CHECK: Is the following instruction (fall thru) allocated ok?
5958 }
5959 assert(cc==HOST_CCREG);
277718fa 5960 store_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,cinfo[i].ba);
5961 do_cc(i,i_regmap,&adj,cinfo[i].ba,TAKEN,0);
57871462 5962 assem_debug("cycle count (adj)\n");
277718fa 5963 if(adj) emit_addimm(cc, cinfo[i].ccadj + CLOCK_ADJUST(2) - adj, cc);
5964 load_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,cinfo[i].ba);
57871462 5965 if(internal)
5966 assem_debug("branch: internal\n");
5967 else
5968 assem_debug("branch: external\n");
277718fa 5969 if (internal && dops[(cinfo[i].ba - start) >> 2].is_ds) {
57871462 5970 ds_assemble_entry(i);
5971 }
5972 else {
277718fa 5973 add_to_linker(out,cinfo[i].ba,internal);
57871462 5974 emit_jmp(0);
5975 }
5976 }
5977 // branch not taken
57871462 5978 if(!unconditional) {
de6dbc52 5979 if (!nevertaken) {
5980 assert(nottaken);
5981 set_jump_target(nottaken, out);
5982 }
57871462 5983 assem_debug("1:\n");
fe807a8a 5984 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,ds_unneeded);
5985 load_regs(regs[i].regmap,branch_regs[i].regmap,dops[i+1].rs1,dops[i+1].rs2);
5986 address_generation(i+1,&branch_regs[i],0);
5a18ce2e 5987 if (ram_offset)
53358c1d 5988 load_reg(regs[i].regmap,branch_regs[i].regmap,ROREG);
5a18ce2e 5989 load_regs(regs[i].regmap,branch_regs[i].regmap,CCREG,INVCP);
fe807a8a 5990 ds_assemble(i+1,&branch_regs[i]);
57871462 5991 cc=get_reg(branch_regs[i].regmap,CCREG);
fe807a8a 5992 if (cc == -1) {
57871462 5993 // Cycle count isn't in a register, temporarily load it then write it out
5994 emit_loadreg(CCREG,HOST_CCREG);
277718fa 5995 emit_addimm_and_set_flags(cinfo[i].ccadj + CLOCK_ADJUST(2), HOST_CCREG);
b14b6a8f 5996 void *jaddr=out;
57871462 5997 emit_jns(0);
b14b6a8f 5998 add_stub(CC_STUB,jaddr,out,0,i,start+i*4+8,NOTTAKEN,0);
57871462 5999 emit_storereg(CCREG,HOST_CCREG);
6000 }
6001 else{
6002 cc=get_reg(i_regmap,CCREG);
6003 assert(cc==HOST_CCREG);
277718fa 6004 emit_addimm_and_set_flags(cinfo[i].ccadj + CLOCK_ADJUST(2), cc);
b14b6a8f 6005 void *jaddr=out;
57871462 6006 emit_jns(0);
fe807a8a 6007 add_stub(CC_STUB,jaddr,out,0,i,start+i*4+8,NOTTAKEN,0);
57871462 6008 }
6009 }
6010 }
6011}
6012
670c0f22 6013static void check_regmap(signed char *regmap)
6014{
6015#ifndef NDEBUG
6016 int i,j;
6017 for (i = 0; i < HOST_REGS; i++) {
6018 if (regmap[i] < 0)
6019 continue;
6020 for (j = i + 1; j < HOST_REGS; j++)
6021 assert(regmap[i] != regmap[j]);
6022 }
6023#endif
6024}
6025
4600ba03 6026#ifdef DISASM
2acc46cd 6027#include <inttypes.h>
53dc27f6 6028static char insn[MAXBLOCK][10];
6029
6030#define set_mnemonic(i_, n_) \
6031 strcpy(insn[i_], n_)
6032
2acc46cd 6033void print_regmap(const char *name, const signed char *regmap)
6034{
6035 char buf[5];
6036 int i, l;
6037 fputs(name, stdout);
6038 for (i = 0; i < HOST_REGS; i++) {
6039 l = 0;
6040 if (regmap[i] >= 0)
6041 l = snprintf(buf, sizeof(buf), "$%d", regmap[i]);
6042 for (; l < 3; l++)
6043 buf[l] = ' ';
6044 buf[l] = 0;
6045 printf(" r%d=%s", i, buf);
6046 }
6047 fputs("\n", stdout);
6048}
6049
57871462 6050 /* disassembly */
6051void disassemble_inst(int i)
6052{
cf95b4f0 6053 if (dops[i].bt) printf("*"); else printf(" ");
6054 switch(dops[i].itype) {
57871462 6055 case UJUMP:
277718fa 6056 printf (" %x: %s %8x\n",start+i*4,insn[i],cinfo[i].ba);break;
57871462 6057 case CJUMP:
277718fa 6058 printf (" %x: %s r%d,r%d,%8x\n",start+i*4,insn[i],dops[i].rs1,dops[i].rs2,i?start+i*4+4+((signed int)((unsigned int)source[i]<<16)>>14):cinfo[i].ba);break;
57871462 6059 case SJUMP:
cf95b4f0 6060 printf (" %x: %s r%d,%8x\n",start+i*4,insn[i],dops[i].rs1,start+i*4+4+((signed int)((unsigned int)source[i]<<16)>>14));break;
57871462 6061 case RJUMP:
ecca05e3 6062 if (dops[i].opcode2 == 9 && dops[i].rt1 != 31)
cf95b4f0 6063 printf (" %x: %s r%d,r%d\n",start+i*4,insn[i],dops[i].rt1,dops[i].rs1);
5067f341 6064 else
cf95b4f0 6065 printf (" %x: %s r%d\n",start+i*4,insn[i],dops[i].rs1);
5067f341 6066 break;
57871462 6067 case IMM16:
cf95b4f0 6068 if(dops[i].opcode==0xf) //LUI
277718fa 6069 printf (" %x: %s r%d,%4x0000\n",start+i*4,insn[i],dops[i].rt1,cinfo[i].imm&0xffff);
57871462 6070 else
277718fa 6071 printf (" %x: %s r%d,r%d,%d\n",start+i*4,insn[i],dops[i].rt1,dops[i].rs1,cinfo[i].imm);
57871462 6072 break;
6073 case LOAD:
6074 case LOADLR:
277718fa 6075 printf (" %x: %s r%d,r%d+%x\n",start+i*4,insn[i],dops[i].rt1,dops[i].rs1,cinfo[i].imm);
57871462 6076 break;
6077 case STORE:
6078 case STORELR:
277718fa 6079 printf (" %x: %s r%d,r%d+%x\n",start+i*4,insn[i],dops[i].rs2,dops[i].rs1,cinfo[i].imm);
57871462 6080 break;
6081 case ALU:
6082 case SHIFT:
cf95b4f0 6083 printf (" %x: %s r%d,r%d,r%d\n",start+i*4,insn[i],dops[i].rt1,dops[i].rs1,dops[i].rs2);
57871462 6084 break;
6085 case MULTDIV:
cf95b4f0 6086 printf (" %x: %s r%d,r%d\n",start+i*4,insn[i],dops[i].rs1,dops[i].rs2);
57871462 6087 break;
6088 case SHIFTIMM:
277718fa 6089 printf (" %x: %s r%d,r%d,%d\n",start+i*4,insn[i],dops[i].rt1,dops[i].rs1,cinfo[i].imm);
57871462 6090 break;
6091 case MOV:
cf95b4f0 6092 if((dops[i].opcode2&0x1d)==0x10)
6093 printf (" %x: %s r%d\n",start+i*4,insn[i],dops[i].rt1);
6094 else if((dops[i].opcode2&0x1d)==0x11)
6095 printf (" %x: %s r%d\n",start+i*4,insn[i],dops[i].rs1);
57871462 6096 else
6097 printf (" %x: %s\n",start+i*4,insn[i]);
6098 break;
6099 case COP0:
cf95b4f0 6100 if(dops[i].opcode2==0)
6101 printf (" %x: %s r%d,cpr0[%d]\n",start+i*4,insn[i],dops[i].rt1,(source[i]>>11)&0x1f); // MFC0
6102 else if(dops[i].opcode2==4)
6103 printf (" %x: %s r%d,cpr0[%d]\n",start+i*4,insn[i],dops[i].rs1,(source[i]>>11)&0x1f); // MTC0
57871462 6104 else printf (" %x: %s\n",start+i*4,insn[i]);
6105 break;
b9b61529 6106 case COP2:
cf95b4f0 6107 if(dops[i].opcode2<3)
6108 printf (" %x: %s r%d,cpr2[%d]\n",start+i*4,insn[i],dops[i].rt1,(source[i]>>11)&0x1f); // MFC2
6109 else if(dops[i].opcode2>3)
6110 printf (" %x: %s r%d,cpr2[%d]\n",start+i*4,insn[i],dops[i].rs1,(source[i]>>11)&0x1f); // MTC2
b9b61529 6111 else printf (" %x: %s\n",start+i*4,insn[i]);
6112 break;
b9b61529 6113 case C2LS:
277718fa 6114 printf (" %x: %s cpr2[%d],r%d+%x\n",start+i*4,insn[i],(source[i]>>16)&0x1f,dops[i].rs1,cinfo[i].imm);
b9b61529 6115 break;
1e973cb0 6116 case INTCALL:
6117 printf (" %x: %s (INTCALL)\n",start+i*4,insn[i]);
6118 break;
57871462 6119 default:
6120 //printf (" %s %8x\n",insn[i],source[i]);
6121 printf (" %x: %s\n",start+i*4,insn[i]);
6122 }
a5cd72d0 6123 #ifndef REGMAP_PRINT
2acc46cd 6124 return;
a5cd72d0 6125 #endif
33a1eda1 6126 printf("D: %x WD: %x U: %"PRIx64" hC: %x hWC: %x hLC: %x\n",
a5cd72d0 6127 regs[i].dirty, regs[i].wasdirty, unneeded_reg[i],
6128 regs[i].isconst, regs[i].wasconst, regs[i].loadedconst);
2acc46cd 6129 print_regmap("pre: ", regmap_pre[i]);
6130 print_regmap("entry: ", regs[i].regmap_entry);
6131 print_regmap("map: ", regs[i].regmap);
6132 if (dops[i].is_jump) {
6133 print_regmap("bentry:", branch_regs[i].regmap_entry);
6134 print_regmap("bmap: ", branch_regs[i].regmap);
6135 }
57871462 6136}
4600ba03 6137#else
53dc27f6 6138#define set_mnemonic(i_, n_)
4600ba03 6139static void disassemble_inst(int i) {}
6140#endif // DISASM
57871462 6141
d848b60a 6142#define DRC_TEST_VAL 0x74657374
6143
d9e2b173 6144static noinline void new_dynarec_test(void)
d848b60a 6145{
be516ebe 6146 int (*testfunc)(void);
d148d265 6147 void *beginning;
be516ebe 6148 int ret[2];
6149 size_t i;
d148d265 6150
687b4580 6151 // check structure linkage
7c3a5182 6152 if ((u_char *)rcnts - (u_char *)&psxRegs != sizeof(psxRegs))
687b4580 6153 {
7c3a5182 6154 SysPrintf("linkage_arm* miscompilation/breakage detected.\n");
687b4580 6155 }
6156
d9e2b173 6157 SysPrintf("(%p) testing if we can run recompiled code @%p...\n",
6158 new_dynarec_test, out);
6159 ((volatile u_int *)NDRC_WRITE_OFFSET(out))[0]++; // make the cache dirty
be516ebe 6160
6161 for (i = 0; i < ARRAY_SIZE(ret); i++) {
2a014d73 6162 out = ndrc->translation_cache;
be516ebe 6163 beginning = start_block();
6164 emit_movimm(DRC_TEST_VAL + i, 0); // test
6165 emit_ret();
6166 literal_pool(0);
6167 end_block(beginning);
6168 testfunc = beginning;
6169 ret[i] = testfunc();
6170 }
6171
6172 if (ret[0] == DRC_TEST_VAL && ret[1] == DRC_TEST_VAL + 1)
d848b60a 6173 SysPrintf("test passed.\n");
6174 else
be516ebe 6175 SysPrintf("test failed, will likely crash soon (r=%08x %08x)\n", ret[0], ret[1]);
2a014d73 6176 out = ndrc->translation_cache;
d848b60a 6177}
6178
dc990066 6179// clear the state completely, instead of just marking
6180// things invalid like invalidate_all_pages() does
919981d0 6181void new_dynarec_clear_full(void)
57871462 6182{
57871462 6183 int n;
2a014d73 6184 out = ndrc->translation_cache;
35775df7 6185 memset(invalid_code,1,sizeof(invalid_code));
6186 memset(hash_table,0xff,sizeof(hash_table));
57871462 6187 memset(mini_ht,-1,sizeof(mini_ht));
dc990066 6188 memset(shadow,0,sizeof(shadow));
57871462 6189 copy=shadow;
93c0345b 6190 expirep = EXPIRITY_OFFSET;
57871462 6191 pending_exception=0;
6192 literalcount=0;
57871462 6193 stop_after_jal=0;
9be4ba64 6194 inv_code_start=inv_code_end=~0;
7f94b097 6195 hack_addr=0;
39b71d9a 6196 f1_hack=0;
93c0345b 6197 for (n = 0; n < ARRAY_SIZE(blocks); n++)
6198 blocks_clear(&blocks[n]);
b7ad2f2c 6199 for (n = 0; n < ARRAY_SIZE(jumps); n++) {
6200 free(jumps[n]);
6201 jumps[n] = NULL;
6202 }
104df9d3 6203 stat_clear(stat_blocks);
6204 stat_clear(stat_links);
32631e6a 6205
d5aeda23 6206 cycle_multiplier_old = Config.cycle_multiplier;
32631e6a 6207 new_dynarec_hacks_old = new_dynarec_hacks;
dc990066 6208}
6209
919981d0 6210void new_dynarec_init(void)
dc990066 6211{
66ea165f 6212 SysPrintf("Init new dynarec, ndrc size %x\n", (int)sizeof(*ndrc));
1e212a25 6213
0aeb0cb9 6214#ifdef _3DS
6215 check_rosalina();
6216#endif
2a014d73 6217#ifdef BASE_ADDR_DYNAMIC
1e212a25 6218 #ifdef VITA
0aeb0cb9 6219 sceBlock = getVMBlock(); //sceKernelAllocMemBlockForVM("code", sizeof(*ndrc));
66ea165f 6220 if (sceBlock <= 0)
6221 SysPrintf("sceKernelAllocMemBlockForVM failed: %x\n", sceBlock);
2a014d73 6222 int ret = sceKernelGetMemBlockBase(sceBlock, (void **)&ndrc);
1e212a25 6223 if (ret < 0)
66ea165f 6224 SysPrintf("sceKernelGetMemBlockBase failed: %x\n", ret);
0aeb0cb9 6225 sceKernelOpenVMDomain();
6226 sceClibPrintf("translation_cache = 0x%08lx\n ", (long)ndrc->translation_cache);
6227 #elif defined(_MSC_VER)
6228 ndrc = VirtualAlloc(NULL, sizeof(*ndrc), MEM_COMMIT | MEM_RESERVE,
6229 PAGE_EXECUTE_READWRITE);
3039c914 6230 #elif defined(HAVE_LIBNX)
6231 Result rc = jitCreate(&g_jit, sizeof(*ndrc));
6232 if (R_FAILED(rc))
6233 SysPrintf("jitCreate failed: %08x\n", rc);
6234 SysPrintf("jitCreate: RX: %p RW: %p type: %d\n", g_jit.rx_addr, g_jit.rw_addr, g_jit.type);
d9e2b173 6235 jitTransitionToWritable(&g_jit);
3039c914 6236 ndrc = g_jit.rx_addr;
6237 ndrc_write_ofs = (char *)g_jit.rw_addr - (char *)ndrc;
d9e2b173 6238 memset(NDRC_WRITE_OFFSET(&ndrc->tramp), 0, sizeof(ndrc->tramp));
1e212a25 6239 #else
2a014d73 6240 uintptr_t desired_addr = 0;
3039c914 6241 int prot = PROT_READ | PROT_WRITE | PROT_EXEC;
6242 int flags = MAP_PRIVATE | MAP_ANONYMOUS;
6243 int fd = -1;
2a014d73 6244 #ifdef __ELF__
6245 extern char _end;
6246 desired_addr = ((uintptr_t)&_end + 0xffffff) & ~0xffffffl;
6247 #endif
d9e2b173 6248 #ifdef TC_WRITE_OFFSET
3039c914 6249 // mostly for testing
6250 fd = open("/dev/shm/pcsxr", O_CREAT | O_RDWR, 0600);
6251 ftruncate(fd, sizeof(*ndrc));
6252 void *mw = mmap(NULL, sizeof(*ndrc), PROT_READ | PROT_WRITE,
6253 (flags = MAP_SHARED), fd, 0);
6254 assert(mw != MAP_FAILED);
6255 prot = PROT_READ | PROT_EXEC;
6256 #endif
6257 ndrc = mmap((void *)desired_addr, sizeof(*ndrc), prot, flags, fd, 0);
2a014d73 6258 if (ndrc == MAP_FAILED) {
d848b60a 6259 SysPrintf("mmap() failed: %s\n", strerror(errno));
1e212a25 6260 abort();
d848b60a 6261 }
d9e2b173 6262 #ifdef TC_WRITE_OFFSET
3039c914 6263 ndrc_write_ofs = (char *)mw - (char *)ndrc;
6264 #endif
1e212a25 6265 #endif
6266#else
6267 #ifndef NO_WRITE_EXEC
bdeade46 6268 // not all systems allow execute in data segment by default
761fdd0a 6269 // size must be 4K aligned for 3DS?
6270 if (mprotect(ndrc, sizeof(*ndrc),
2a014d73 6271 PROT_READ | PROT_WRITE | PROT_EXEC) != 0)
d848b60a 6272 SysPrintf("mprotect() failed: %s\n", strerror(errno));
1e212a25 6273 #endif
dc990066 6274#endif
2a014d73 6275 out = ndrc->translation_cache;
dc990066 6276 new_dynarec_clear_full();
6277#ifdef HOST_IMM8
6278 // Copy this into local area so we don't have to put it in every literal pool
6279 invc_ptr=invalid_code;
6280#endif
57871462 6281 arch_init();
d848b60a 6282 new_dynarec_test();
33a1eda1 6283 ram_offset = (uintptr_t)psxM - 0x80000000;
b105cf4f 6284 if (ram_offset!=0)
c43b5311 6285 SysPrintf("warning: RAM is not directly mapped, performance will suffer\n");
398d6924 6286 SysPrintf("Mapped (RAM/scrp/ROM/LUTs/TC):\n");
6287 SysPrintf("%p/%p/%p/%p/%p\n", psxM, psxH, psxR, mem_rtab, out);
57871462 6288}
6289
919981d0 6290void new_dynarec_cleanup(void)
57871462 6291{
6292 int n;
2a014d73 6293#ifdef BASE_ADDR_DYNAMIC
1e212a25 6294 #ifdef VITA
66ea165f 6295 // sceBlock is managed by retroarch's bootstrap code
9c67c98f 6296 //sceKernelFreeMemBlock(sceBlock);
6297 //sceBlock = -1;
3039c914 6298 #elif defined(HAVE_LIBNX)
6299 jitClose(&g_jit);
6300 ndrc = NULL;
1e212a25 6301 #else
2a014d73 6302 if (munmap(ndrc, sizeof(*ndrc)) < 0)
1e212a25 6303 SysPrintf("munmap() failed\n");
3039c914 6304 ndrc = NULL;
bdeade46 6305 #endif
1e212a25 6306#endif
93c0345b 6307 for (n = 0; n < ARRAY_SIZE(blocks); n++)
6308 blocks_clear(&blocks[n]);
b7ad2f2c 6309 for (n = 0; n < ARRAY_SIZE(jumps); n++) {
6310 free(jumps[n]);
6311 jumps[n] = NULL;
6312 }
104df9d3 6313 stat_clear(stat_blocks);
6314 stat_clear(stat_links);
ece032e6 6315 new_dynarec_print_stats();
57871462 6316}
6317
03f55e6b 6318static u_int *get_source_start(u_int addr, u_int *limit)
57871462 6319{
33a1eda1 6320 if (addr < 0x00800000
6321 || (0x80000000 <= addr && addr < 0x80800000)
6322 || (0xa0000000 <= addr && addr < 0xa0800000))
a3203cf4 6323 {
03f55e6b 6324 // used for BIOS calls mostly?
33a1eda1 6325 *limit = (addr & 0xa0600000) + 0x00200000;
6326 return (u_int *)(psxM + (addr & 0x1fffff));
03f55e6b 6327 }
6328 else if (!Config.HLE && (
6329 /* (0x9fc00000 <= addr && addr < 0x9fc80000) ||*/
a3203cf4 6330 (0xbfc00000 <= addr && addr < 0xbfc80000)))
6331 {
6332 // BIOS. The multiplier should be much higher as it's uncached 8bit mem,
d5aeda23 6333 // but timings in PCSX are too tied to the interpreter's 2-per-insn assumption
d62c125a 6334 if (!HACK_ENABLED(NDHACK_OVERRIDE_CYCLE_M))
24058131 6335 cycle_multiplier_active = 200;
a3203cf4 6336
03f55e6b 6337 *limit = (addr & 0xfff00000) | 0x80000;
01d26796 6338 return (u_int *)((u_char *)psxR + (addr&0x7ffff));
03f55e6b 6339 }
581335b0 6340 return NULL;
03f55e6b 6341}
6342
6343static u_int scan_for_ret(u_int addr)
6344{
6345 u_int limit = 0;
6346 u_int *mem;
6347
6348 mem = get_source_start(addr, &limit);
6349 if (mem == NULL)
6350 return addr;
6351
6352 if (limit > addr + 0x1000)
6353 limit = addr + 0x1000;
6354 for (; addr < limit; addr += 4, mem++) {
6355 if (*mem == 0x03e00008) // jr $ra
6356 return addr + 8;
57871462 6357 }
581335b0 6358 return addr;
03f55e6b 6359}
6360
6361struct savestate_block {
6362 uint32_t addr;
6363 uint32_t regflags;
6364};
6365
6366static int addr_cmp(const void *p1_, const void *p2_)
6367{
6368 const struct savestate_block *p1 = p1_, *p2 = p2_;
6369 return p1->addr - p2->addr;
6370}
6371
6372int new_dynarec_save_blocks(void *save, int size)
6373{
104df9d3 6374 struct savestate_block *sblocks = save;
6375 int maxcount = size / sizeof(sblocks[0]);
03f55e6b 6376 struct savestate_block tmp_blocks[1024];
104df9d3 6377 struct block_info *block;
03f55e6b 6378 int p, s, d, o, bcnt;
6379 u_int addr;
6380
6381 o = 0;
104df9d3 6382 for (p = 0; p < ARRAY_SIZE(blocks); p++) {
03f55e6b 6383 bcnt = 0;
104df9d3 6384 for (block = blocks[p]; block != NULL; block = block->next) {
6385 if (block->is_dirty)
6386 continue;
6387 tmp_blocks[bcnt].addr = block->start;
6388 tmp_blocks[bcnt].regflags = block->reg_sv_flags;
03f55e6b 6389 bcnt++;
6390 }
6391 if (bcnt < 1)
6392 continue;
6393 qsort(tmp_blocks, bcnt, sizeof(tmp_blocks[0]), addr_cmp);
6394
6395 addr = tmp_blocks[0].addr;
6396 for (s = d = 0; s < bcnt; s++) {
6397 if (tmp_blocks[s].addr < addr)
6398 continue;
6399 if (d == 0 || tmp_blocks[d-1].addr != tmp_blocks[s].addr)
6400 tmp_blocks[d++] = tmp_blocks[s];
6401 addr = scan_for_ret(tmp_blocks[s].addr);
6402 }
6403
6404 if (o + d > maxcount)
6405 d = maxcount - o;
104df9d3 6406 memcpy(&sblocks[o], tmp_blocks, d * sizeof(sblocks[0]));
03f55e6b 6407 o += d;
6408 }
6409
104df9d3 6410 return o * sizeof(sblocks[0]);
03f55e6b 6411}
6412
6413void new_dynarec_load_blocks(const void *save, int size)
6414{
104df9d3 6415 const struct savestate_block *sblocks = save;
6416 int count = size / sizeof(sblocks[0]);
6417 struct block_info *block;
03f55e6b 6418 u_int regs_save[32];
104df9d3 6419 u_int page;
03f55e6b 6420 uint32_t f;
6421 int i, b;
6422
104df9d3 6423 // restore clean blocks, if any
6424 for (page = 0, b = i = 0; page < ARRAY_SIZE(blocks); page++) {
6425 for (block = blocks[page]; block != NULL; block = block->next, b++) {
6426 if (!block->is_dirty)
6427 continue;
6428 assert(block->source && block->copy);
6429 if (memcmp(block->source, block->copy, block->len))
6430 continue;
6431
6432 // see try_restore_block
6433 block->is_dirty = 0;
6434 mark_invalid_code(block->start, block->len, 0);
6435 i++;
6436 }
6437 }
6438 inv_debug("load_blocks: %d/%d clean blocks\n", i, b);
03f55e6b 6439
6440 // change GPRs for speculation to at least partially work..
6441 memcpy(regs_save, &psxRegs.GPR, sizeof(regs_save));
6442 for (i = 1; i < 32; i++)
6443 psxRegs.GPR.r[i] = 0x80000000;
6444
6445 for (b = 0; b < count; b++) {
104df9d3 6446 for (f = sblocks[b].regflags, i = 0; f; f >>= 1, i++) {
03f55e6b 6447 if (f & 1)
6448 psxRegs.GPR.r[i] = 0x1f800000;
6449 }
6450
104df9d3 6451 ndrc_get_addr_ht(sblocks[b].addr);
03f55e6b 6452
104df9d3 6453 for (f = sblocks[b].regflags, i = 0; f; f >>= 1, i++) {
03f55e6b 6454 if (f & 1)
6455 psxRegs.GPR.r[i] = 0x80000000;
6456 }
6457 }
6458
6459 memcpy(&psxRegs.GPR, regs_save, sizeof(regs_save));
6460}
6461
ece032e6 6462void new_dynarec_print_stats(void)
6463{
6464#ifdef STAT_PRINT
104df9d3 6465 printf("cc %3d,%3d,%3d lu%6d,%3d,%3d c%3d inv%3d,%3d tc_offs %zu b %u,%u\n",
ece032e6 6466 stat_bc_pre, stat_bc_direct, stat_bc_restore,
104df9d3 6467 stat_ht_lookups, stat_jump_in_lookups, stat_restore_tries,
6468 stat_restore_compares, stat_inv_addr_calls, stat_inv_hits,
6469 out - ndrc->translation_cache, stat_blocks, stat_links);
ece032e6 6470 stat_bc_direct = stat_bc_pre = stat_bc_restore =
104df9d3 6471 stat_ht_lookups = stat_jump_in_lookups = stat_restore_tries =
6472 stat_restore_compares = stat_inv_addr_calls = stat_inv_hits = 0;
ece032e6 6473#endif
6474}
6475
7f94b097 6476static int apply_hacks(void)
24058131 6477{
6478 int i;
6479 if (HACK_ENABLED(NDHACK_NO_COMPAT_HACKS))
7f94b097 6480 return 0;
24058131 6481 /* special hack(s) */
6482 for (i = 0; i < slen - 4; i++)
6483 {
6484 // lui a4, 0xf200; jal <rcnt_read>; addu a0, 2; slti v0, 28224
6485 if (source[i] == 0x3c04f200 && dops[i+1].itype == UJUMP
6486 && source[i+2] == 0x34840002 && dops[i+3].opcode == 0x0a
277718fa 6487 && cinfo[i+3].imm == 0x6e40 && dops[i+3].rs1 == 2)
24058131 6488 {
6489 SysPrintf("PE2 hack @%08x\n", start + (i+3)*4);
6490 dops[i + 3].itype = NOP;
6491 }
6492 }
6493 i = slen;
6494 if (i > 10 && source[i-1] == 0 && source[i-2] == 0x03e00008
6495 && source[i-4] == 0x8fbf0018 && source[i-6] == 0x00c0f809
6496 && dops[i-7].itype == STORE)
6497 {
6498 i = i-8;
6499 if (dops[i].itype == IMM16)
6500 i--;
6501 // swl r2, 15(r6); swr r2, 12(r6); sw r6, *; jalr r6
6502 if (dops[i].itype == STORELR && dops[i].rs1 == 6
6503 && dops[i-1].itype == STORELR && dops[i-1].rs1 == 6)
6504 {
7f94b097 6505 SysPrintf("F1 hack from %08x, old dst %08x\n", start, hack_addr);
6506 f1_hack = 1;
6507 return 1;
24058131 6508 }
6509 }
7f94b097 6510 return 0;
24058131 6511}
6512
de6dbc52 6513static int is_ld_use_hazard(int ld_rt, const struct decoded_insn *op)
03f55e6b 6514{
de6dbc52 6515 return ld_rt != 0 && (ld_rt == op->rs1 || ld_rt == op->rs2)
6516 && op->itype != LOADLR && op->itype != CJUMP && op->itype != SJUMP;
6517}
57871462 6518
de6dbc52 6519static void force_intcall(int i)
6520{
6521 memset(&dops[i], 0, sizeof(dops[i]));
6522 dops[i].itype = INTCALL;
6523 dops[i].rs1 = CCREG;
6524 dops[i].is_exception = 1;
6525 cinfo[i].ba = -1;
6526}
6527
6528static void disassemble_one(int i, u_int src)
6529{
6530 unsigned int type, op, op2, op3;
a22ccd6a 6531 enum ls_width_type ls_type = LS_32;
7ebfcedf 6532 memset(&dops[i], 0, sizeof(dops[i]));
277718fa 6533 memset(&cinfo[i], 0, sizeof(cinfo[i]));
6534 cinfo[i].ba = -1;
6535 cinfo[i].addr = -1;
de6dbc52 6536 dops[i].opcode = op = src >> 26;
277718fa 6537 op2 = 0;
a5cd72d0 6538 type = INTCALL;
6539 set_mnemonic(i, "???");
57871462 6540 switch(op)
6541 {
a5cd72d0 6542 case 0x00: set_mnemonic(i, "special");
de6dbc52 6543 op2 = src & 0x3f;
57871462 6544 switch(op2)
6545 {
53dc27f6 6546 case 0x00: set_mnemonic(i, "SLL"); type=SHIFTIMM; break;
6547 case 0x02: set_mnemonic(i, "SRL"); type=SHIFTIMM; break;
6548 case 0x03: set_mnemonic(i, "SRA"); type=SHIFTIMM; break;
6549 case 0x04: set_mnemonic(i, "SLLV"); type=SHIFT; break;
6550 case 0x06: set_mnemonic(i, "SRLV"); type=SHIFT; break;
6551 case 0x07: set_mnemonic(i, "SRAV"); type=SHIFT; break;
6552 case 0x08: set_mnemonic(i, "JR"); type=RJUMP; break;
6553 case 0x09: set_mnemonic(i, "JALR"); type=RJUMP; break;
6554 case 0x0C: set_mnemonic(i, "SYSCALL"); type=SYSCALL; break;
6555 case 0x0D: set_mnemonic(i, "BREAK"); type=SYSCALL; break;
53dc27f6 6556 case 0x10: set_mnemonic(i, "MFHI"); type=MOV; break;
6557 case 0x11: set_mnemonic(i, "MTHI"); type=MOV; break;
6558 case 0x12: set_mnemonic(i, "MFLO"); type=MOV; break;
6559 case 0x13: set_mnemonic(i, "MTLO"); type=MOV; break;
6560 case 0x18: set_mnemonic(i, "MULT"); type=MULTDIV; break;
6561 case 0x19: set_mnemonic(i, "MULTU"); type=MULTDIV; break;
6562 case 0x1A: set_mnemonic(i, "DIV"); type=MULTDIV; break;
6563 case 0x1B: set_mnemonic(i, "DIVU"); type=MULTDIV; break;
6564 case 0x20: set_mnemonic(i, "ADD"); type=ALU; break;
6565 case 0x21: set_mnemonic(i, "ADDU"); type=ALU; break;
6566 case 0x22: set_mnemonic(i, "SUB"); type=ALU; break;
6567 case 0x23: set_mnemonic(i, "SUBU"); type=ALU; break;
6568 case 0x24: set_mnemonic(i, "AND"); type=ALU; break;
6569 case 0x25: set_mnemonic(i, "OR"); type=ALU; break;
6570 case 0x26: set_mnemonic(i, "XOR"); type=ALU; break;
6571 case 0x27: set_mnemonic(i, "NOR"); type=ALU; break;
6572 case 0x2A: set_mnemonic(i, "SLT"); type=ALU; break;
6573 case 0x2B: set_mnemonic(i, "SLTU"); type=ALU; break;
57871462 6574 }
6575 break;
a5cd72d0 6576 case 0x01: set_mnemonic(i, "regimm");
6577 type = SJUMP;
de6dbc52 6578 op2 = (src >> 16) & 0x1f;
57871462 6579 switch(op2)
6580 {
a5cd72d0 6581 case 0x10: set_mnemonic(i, "BLTZAL"); break;
6582 case 0x11: set_mnemonic(i, "BGEZAL"); break;
6583 default:
6584 if (op2 & 1)
6585 set_mnemonic(i, "BGEZ");
6586 else
6587 set_mnemonic(i, "BLTZ");
57871462 6588 }
6589 break;
53dc27f6 6590 case 0x02: set_mnemonic(i, "J"); type=UJUMP; break;
6591 case 0x03: set_mnemonic(i, "JAL"); type=UJUMP; break;
6592 case 0x04: set_mnemonic(i, "BEQ"); type=CJUMP; break;
6593 case 0x05: set_mnemonic(i, "BNE"); type=CJUMP; break;
6594 case 0x06: set_mnemonic(i, "BLEZ"); type=CJUMP; break;
6595 case 0x07: set_mnemonic(i, "BGTZ"); type=CJUMP; break;
6596 case 0x08: set_mnemonic(i, "ADDI"); type=IMM16; break;
6597 case 0x09: set_mnemonic(i, "ADDIU"); type=IMM16; break;
6598 case 0x0A: set_mnemonic(i, "SLTI"); type=IMM16; break;
6599 case 0x0B: set_mnemonic(i, "SLTIU"); type=IMM16; break;
6600 case 0x0C: set_mnemonic(i, "ANDI"); type=IMM16; break;
6601 case 0x0D: set_mnemonic(i, "ORI"); type=IMM16; break;
6602 case 0x0E: set_mnemonic(i, "XORI"); type=IMM16; break;
6603 case 0x0F: set_mnemonic(i, "LUI"); type=IMM16; break;
a5cd72d0 6604 case 0x10: set_mnemonic(i, "COP0");
de6dbc52 6605 op2 = (src >> 21) & 0x1f;
a5cd72d0 6606 if (op2 & 0x10) {
de6dbc52 6607 op3 = src & 0x1f;
a5cd72d0 6608 switch (op3)
6609 {
6610 case 0x01: case 0x02: case 0x06: case 0x08: type = INTCALL; break;
6611 case 0x10: set_mnemonic(i, "RFE"); type=RFE; break;
6612 default: type = OTHER; break;
6613 }
6614 break;
6615 }
57871462 6616 switch(op2)
6617 {
a5cd72d0 6618 u32 rd;
6619 case 0x00:
6620 set_mnemonic(i, "MFC0");
de6dbc52 6621 rd = (src >> 11) & 0x1F;
a5cd72d0 6622 if (!(0x00000417u & (1u << rd)))
6623 type = COP0;
6624 break;
53dc27f6 6625 case 0x04: set_mnemonic(i, "MTC0"); type=COP0; break;
a5cd72d0 6626 case 0x02:
6627 case 0x06: type = INTCALL; break;
6628 default: type = OTHER; break;
57871462 6629 }
6630 break;
a5cd72d0 6631 case 0x11: set_mnemonic(i, "COP1");
de6dbc52 6632 op2 = (src >> 21) & 0x1f;
57871462 6633 break;
a5cd72d0 6634 case 0x12: set_mnemonic(i, "COP2");
de6dbc52 6635 op2 = (src >> 21) & 0x1f;
a5cd72d0 6636 if (op2 & 0x10) {
6637 type = OTHER;
de6dbc52 6638 if (gte_handlers[src & 0x3f] != NULL) {
53dc27f6 6639#ifdef DISASM
de6dbc52 6640 if (gte_regnames[src & 0x3f] != NULL)
6641 strcpy(insn[i], gte_regnames[src & 0x3f]);
bedfea38 6642 else
de6dbc52 6643 snprintf(insn[i], sizeof(insn[i]), "COP2 %x", src & 0x3f);
53dc27f6 6644#endif
a5cd72d0 6645 type = C2OP;
c7abc864 6646 }
6647 }
6648 else switch(op2)
b9b61529 6649 {
53dc27f6 6650 case 0x00: set_mnemonic(i, "MFC2"); type=COP2; break;
6651 case 0x02: set_mnemonic(i, "CFC2"); type=COP2; break;
6652 case 0x04: set_mnemonic(i, "MTC2"); type=COP2; break;
6653 case 0x06: set_mnemonic(i, "CTC2"); type=COP2; break;
b9b61529 6654 }
6655 break;
a5cd72d0 6656 case 0x13: set_mnemonic(i, "COP3");
de6dbc52 6657 op2 = (src >> 21) & 0x1f;
a5cd72d0 6658 break;
f9e9616e 6659 case 0x20: set_mnemonic(i, "LB"); type=LOAD; ls_type = LS_8; break;
6660 case 0x21: set_mnemonic(i, "LH"); type=LOAD; ls_type = LS_16; break;
6661 case 0x22: set_mnemonic(i, "LWL"); type=LOADLR; ls_type = LS_LR; break;
6662 case 0x23: set_mnemonic(i, "LW"); type=LOAD; ls_type = LS_32; break;
6663 case 0x24: set_mnemonic(i, "LBU"); type=LOAD; ls_type = LS_8; break;
6664 case 0x25: set_mnemonic(i, "LHU"); type=LOAD; ls_type = LS_16; break;
6665 case 0x26: set_mnemonic(i, "LWR"); type=LOADLR; ls_type = LS_LR; break;
6666 case 0x28: set_mnemonic(i, "SB"); type=STORE; ls_type = LS_8; break;
6667 case 0x29: set_mnemonic(i, "SH"); type=STORE; ls_type = LS_16; break;
6668 case 0x2A: set_mnemonic(i, "SWL"); type=STORELR; ls_type = LS_LR; break;
6669 case 0x2B: set_mnemonic(i, "SW"); type=STORE; ls_type = LS_32; break;
6670 case 0x2E: set_mnemonic(i, "SWR"); type=STORELR; ls_type = LS_LR; break;
6671 case 0x32: set_mnemonic(i, "LWC2"); type=C2LS; ls_type = LS_32; break;
6672 case 0x3A: set_mnemonic(i, "SWC2"); type=C2LS; ls_type = LS_32; break;
a5cd72d0 6673 case 0x3B:
de6dbc52 6674 if (Config.HLE && (src & 0x03ffffff) < ARRAY_SIZE(psxHLEt)) {
a5cd72d0 6675 set_mnemonic(i, "HLECALL");
6676 type = HLECALL;
6677 }
6678 break;
6679 default:
90ae6d4e 6680 break;
57871462 6681 }
a5cd72d0 6682 if (type == INTCALL)
de6dbc52 6683 SysPrintf("NI %08x @%08x (%08x)\n", src, start + i*4, start);
f9e9616e 6684 dops[i].itype = type;
6685 dops[i].opcode2 = op2;
6686 dops[i].ls_type = ls_type;
57871462 6687 /* Get registers/immediates */
53dc27f6 6688 dops[i].use_lt1=0;
bedfea38 6689 gte_rs[i]=gte_rt[i]=0;
a5cd72d0 6690 dops[i].rs1 = 0;
6691 dops[i].rs2 = 0;
6692 dops[i].rt1 = 0;
6693 dops[i].rt2 = 0;
57871462 6694 switch(type) {
6695 case LOAD:
de6dbc52 6696 dops[i].rs1 = (src >> 21) & 0x1f;
6697 dops[i].rt1 = (src >> 16) & 0x1f;
6698 cinfo[i].imm = (short)src;
57871462 6699 break;
6700 case STORE:
6701 case STORELR:
de6dbc52 6702 dops[i].rs1 = (src >> 21) & 0x1f;
6703 dops[i].rs2 = (src >> 16) & 0x1f;
6704 cinfo[i].imm = (short)src;
57871462 6705 break;
6706 case LOADLR:
6707 // LWL/LWR only load part of the register,
6708 // therefore the target register must be treated as a source too
de6dbc52 6709 dops[i].rs1 = (src >> 21) & 0x1f;
6710 dops[i].rs2 = (src >> 16) & 0x1f;
6711 dops[i].rt1 = (src >> 16) & 0x1f;
6712 cinfo[i].imm = (short)src;
57871462 6713 break;
6714 case IMM16:
cf95b4f0 6715 if (op==0x0f) dops[i].rs1=0; // LUI instruction has no source register
de6dbc52 6716 else dops[i].rs1 = (src >> 21) & 0x1f;
6717 dops[i].rs2 = 0;
6718 dops[i].rt1 = (src >> 16) & 0x1f;
57871462 6719 if(op>=0x0c&&op<=0x0e) { // ANDI/ORI/XORI
de6dbc52 6720 cinfo[i].imm = (unsigned short)src;
57871462 6721 }else{
de6dbc52 6722 cinfo[i].imm = (short)src;
57871462 6723 }
57871462 6724 break;
6725 case UJUMP:
57871462 6726 // The JAL instruction writes to r31.
6727 if (op&1) {
cf95b4f0 6728 dops[i].rt1=31;
57871462 6729 }
cf95b4f0 6730 dops[i].rs2=CCREG;
57871462 6731 break;
6732 case RJUMP:
de6dbc52 6733 dops[i].rs1 = (src >> 21) & 0x1f;
5067f341 6734 // The JALR instruction writes to rd.
57871462 6735 if (op2&1) {
de6dbc52 6736 dops[i].rt1 = (src >> 11) & 0x1f;
57871462 6737 }
cf95b4f0 6738 dops[i].rs2=CCREG;
57871462 6739 break;
6740 case CJUMP:
de6dbc52 6741 dops[i].rs1 = (src >> 21) & 0x1f;
6742 dops[i].rs2 = (src >> 16) & 0x1f;
57871462 6743 if(op&2) { // BGTZ/BLEZ
cf95b4f0 6744 dops[i].rs2=0;
57871462 6745 }
57871462 6746 break;
6747 case SJUMP:
de6dbc52 6748 dops[i].rs1 = (src >> 21) & 0x1f;
6749 dops[i].rs2 = CCREG;
a5cd72d0 6750 if (op2 == 0x10 || op2 == 0x11) { // BxxAL
6751 dops[i].rt1 = 31;
57871462 6752 // NOTE: If the branch is not taken, r31 is still overwritten
6753 }
57871462 6754 break;
57871462 6755 case ALU:
de6dbc52 6756 dops[i].rs1=(src>>21)&0x1f; // source
6757 dops[i].rs2=(src>>16)&0x1f; // subtract amount
6758 dops[i].rt1=(src>>11)&0x1f; // destination
57871462 6759 break;
6760 case MULTDIV:
de6dbc52 6761 dops[i].rs1=(src>>21)&0x1f; // source
6762 dops[i].rs2=(src>>16)&0x1f; // divisor
cf95b4f0 6763 dops[i].rt1=HIREG;
6764 dops[i].rt2=LOREG;
57871462 6765 break;
6766 case MOV:
cf95b4f0 6767 if(op2==0x10) dops[i].rs1=HIREG; // MFHI
6768 if(op2==0x11) dops[i].rt1=HIREG; // MTHI
6769 if(op2==0x12) dops[i].rs1=LOREG; // MFLO
6770 if(op2==0x13) dops[i].rt1=LOREG; // MTLO
de6dbc52 6771 if((op2&0x1d)==0x10) dops[i].rt1=(src>>11)&0x1f; // MFxx
6772 if((op2&0x1d)==0x11) dops[i].rs1=(src>>21)&0x1f; // MTxx
57871462 6773 break;
6774 case SHIFT:
de6dbc52 6775 dops[i].rs1=(src>>16)&0x1f; // target of shift
6776 dops[i].rs2=(src>>21)&0x1f; // shift amount
6777 dops[i].rt1=(src>>11)&0x1f; // destination
57871462 6778 break;
6779 case SHIFTIMM:
de6dbc52 6780 dops[i].rs1=(src>>16)&0x1f;
cf95b4f0 6781 dops[i].rs2=0;
de6dbc52 6782 dops[i].rt1=(src>>11)&0x1f;
6783 cinfo[i].imm=(src>>6)&0x1f;
57871462 6784 break;
6785 case COP0:
de6dbc52 6786 if(op2==0) dops[i].rt1=(src>>16)&0x1F; // MFC0
6787 if(op2==4) dops[i].rs1=(src>>16)&0x1F; // MTC0
6788 if(op2==4&&((src>>11)&0x1e)==12) dops[i].rs2=CCREG;
57871462 6789 break;
bedfea38 6790 case COP2:
de6dbc52 6791 if(op2<3) dops[i].rt1=(src>>16)&0x1F; // MFC2/CFC2
6792 if(op2>3) dops[i].rs1=(src>>16)&0x1F; // MTC2/CTC2
6793 int gr=(src>>11)&0x1F;
bedfea38 6794 switch(op2)
6795 {
6796 case 0x00: gte_rs[i]=1ll<<gr; break; // MFC2
6797 case 0x04: gte_rt[i]=1ll<<gr; break; // MTC2
0ff8c62c 6798 case 0x02: gte_rs[i]=1ll<<(gr+32); break; // CFC2
bedfea38 6799 case 0x06: gte_rt[i]=1ll<<(gr+32); break; // CTC2
6800 }
6801 break;
b9b61529 6802 case C2LS:
de6dbc52 6803 dops[i].rs1=(src>>21)&0x1F;
6804 cinfo[i].imm=(short)src;
6805 if(op==0x32) gte_rt[i]=1ll<<((src>>16)&0x1F); // LWC2
6806 else gte_rs[i]=1ll<<((src>>16)&0x1F); // SWC2
bedfea38 6807 break;
6808 case C2OP:
de6dbc52 6809 gte_rs[i]=gte_reg_reads[src&0x3f];
6810 gte_rt[i]=gte_reg_writes[src&0x3f];
2167bef6 6811 gte_rt[i]|=1ll<<63; // every op changes flags
de6dbc52 6812 if((src&0x3f)==GTE_MVMVA) {
6813 int v = (src >> 15) & 3;
587a5b1c 6814 gte_rs[i]&=~0xe3fll;
6815 if(v==3) gte_rs[i]|=0xe00ll;
6816 else gte_rs[i]|=3ll<<(v*2);
6817 }
b9b61529 6818 break;
57871462 6819 case SYSCALL:
7139f3c8 6820 case HLECALL:
1e973cb0 6821 case INTCALL:
cf95b4f0 6822 dops[i].rs1=CCREG;
57871462 6823 break;
6824 default:
a5cd72d0 6825 break;
57871462 6826 }
de6dbc52 6827}
6828
6829static noinline void pass1_disassemble(u_int pagelimit)
6830{
6831 int i, j, done = 0, ni_count = 0;
f9e9616e 6832 int ds_next = 0;
de6dbc52 6833
6834 for (i = 0; !done; i++)
6835 {
6836 int force_j_to_interpreter = 0;
6837 unsigned int type, op, op2;
6838
6839 disassemble_one(i, source[i]);
f9e9616e 6840 dops[i].is_ds = ds_next; ds_next = 0;
de6dbc52 6841 type = dops[i].itype;
6842 op = dops[i].opcode;
6843 op2 = dops[i].opcode2;
6844
57871462 6845 /* Calculate branch target addresses */
6846 if(type==UJUMP)
277718fa 6847 cinfo[i].ba=((start+i*4+4)&0xF0000000)|(((unsigned int)source[i]<<6)>>4);
cf95b4f0 6848 else if(type==CJUMP&&dops[i].rs1==dops[i].rs2&&(op&1))
277718fa 6849 cinfo[i].ba=start+i*4+8; // Ignore never taken branch
cf95b4f0 6850 else if(type==SJUMP&&dops[i].rs1==0&&!(op2&1))
277718fa 6851 cinfo[i].ba=start+i*4+8; // Ignore never taken branch
ad49de89 6852 else if(type==CJUMP||type==SJUMP)
277718fa 6853 cinfo[i].ba=start+i*4+4+((signed int)((unsigned int)source[i]<<16)>>14);
4919de1e 6854
6855 /* simplify always (not)taken branches */
cf95b4f0 6856 if (type == CJUMP && dops[i].rs1 == dops[i].rs2) {
6857 dops[i].rs1 = dops[i].rs2 = 0;
4919de1e 6858 if (!(op & 1)) {
cf95b4f0 6859 dops[i].itype = type = UJUMP;
6860 dops[i].rs2 = CCREG;
4919de1e 6861 }
6862 }
cf95b4f0 6863 else if (type == SJUMP && dops[i].rs1 == 0 && (op2 & 1))
6864 dops[i].itype = type = UJUMP;
4919de1e 6865
277718fa 6866 dops[i].is_jump = type == RJUMP || type == UJUMP || type == CJUMP || type == SJUMP;
6867 dops[i].is_ujump = type == RJUMP || type == UJUMP;
6868 dops[i].is_load = type == LOAD || type == LOADLR || op == 0x32; // LWC2
a5cd72d0 6869 dops[i].is_delay_load = (dops[i].is_load || (source[i] & 0xf3d00000) == 0x40000000); // MFC/CFC
277718fa 6870 dops[i].is_store = type == STORE || type == STORELR || op == 0x3a; // SWC2
6871 dops[i].is_exception = type == SYSCALL || type == HLECALL || type == INTCALL;
6872 dops[i].may_except = dops[i].is_exception || (type == ALU && (op2 == 0x20 || op2 == 0x22)) || op == 8;
f9e9616e 6873 ds_next = dops[i].is_jump;
277718fa 6874
6875 if (((op & 0x37) == 0x21 || op == 0x25) // LH/SH/LHU
6876 && ((cinfo[i].imm & 1) || Config.PreciseExceptions))
6877 dops[i].may_except = 1;
6878 if (((op & 0x37) == 0x23 || (op & 0x37) == 0x32) // LW/SW/LWC2/SWC2
6879 && ((cinfo[i].imm & 3) || Config.PreciseExceptions))
6880 dops[i].may_except = 1;
fe807a8a 6881
a5cd72d0 6882 /* rare messy cases to just pass over to the interpreter */
fe807a8a 6883 if (i > 0 && dops[i-1].is_jump) {
ecca05e3 6884 j = i - 1;
3e535354 6885 // branch in delay slot?
fe807a8a 6886 if (dops[i].is_jump) {
3e535354 6887 // don't handle first branch and call interpreter if it's hit
a5cd72d0 6888 SysPrintf("branch in DS @%08x (%08x)\n", start + i*4, start);
ecca05e3 6889 force_j_to_interpreter = 1;
3e535354 6890 }
de6dbc52 6891 // load delay detection through a branch
a5cd72d0 6892 else if (dops[i].is_delay_load && dops[i].rt1 != 0) {
de6dbc52 6893 const struct decoded_insn *dop = NULL;
6894 int t = -1;
6895 if (cinfo[i-1].ba != -1) {
6896 t = (cinfo[i-1].ba - start) / 4;
6897 if (t < 0 || t > i) {
6898 u_int limit = 0;
6899 u_int *mem = get_source_start(cinfo[i-1].ba, &limit);
6900 if (mem != NULL) {
6901 disassemble_one(MAXBLOCK - 1, mem[0]);
6902 dop = &dops[MAXBLOCK - 1];
6903 }
6904 }
6905 else
6906 dop = &dops[t];
6907 }
6908 if ((dop && is_ld_use_hazard(dops[i].rt1, dop))
6909 || (!dop && Config.PreciseExceptions)) {
3e535354 6910 // jump target wants DS result - potential load delay effect
a5cd72d0 6911 SysPrintf("load delay in DS @%08x (%08x)\n", start + i*4, start);
ecca05e3 6912 force_j_to_interpreter = 1;
de6dbc52 6913 if (0 <= t && t < i)
6914 dops[t + 1].bt = 1; // expected return from interpreter
3e535354 6915 }
cf95b4f0 6916 else if(i>=2&&dops[i-2].rt1==2&&dops[i].rt1==2&&dops[i].rs1!=2&&dops[i].rs2!=2&&dops[i-1].rs1!=2&&dops[i-1].rs2!=2&&
fe807a8a 6917 !(i>=3&&dops[i-3].is_jump)) {
3e535354 6918 // v0 overwrite like this is a sign of trouble, bail out
4149788d 6919 SysPrintf("v0 overwrite @%08x (%08x)\n", start + i*4, start);
ecca05e3 6920 force_j_to_interpreter = 1;
3e535354 6921 }
6922 }
a5cd72d0 6923 }
de6dbc52 6924 else if (i > 0 && dops[i-1].is_delay_load
6925 && is_ld_use_hazard(dops[i-1].rt1, &dops[i])
6926 && (i < 2 || !dops[i-2].is_ujump)) {
a5cd72d0 6927 SysPrintf("load delay @%08x (%08x)\n", start + i*4, start);
ecca05e3 6928 for (j = i - 1; j > 0 && dops[j-1].is_delay_load; j--)
6929 if (dops[j-1].rt1 != dops[i-1].rt1)
6930 break;
6931 force_j_to_interpreter = 1;
a5cd72d0 6932 }
ecca05e3 6933 if (force_j_to_interpreter) {
de6dbc52 6934 force_intcall(j);
a5cd72d0 6935 done = 2;
ecca05e3 6936 i = j; // don't compile the problematic branch/load/etc
3e535354 6937 }
de6dbc52 6938 if (dops[i].is_exception && i > 0 && dops[i-1].is_jump) {
6939 SysPrintf("exception in DS @%08x (%08x)\n", start + i*4, start);
6940 i--;
6941 force_intcall(i);
6942 done = 2;
6943 }
6944 if (i >= 2 && (source[i-2] & 0xffe0f800) == 0x40806000) // MTC0 $12
6945 dops[i].bt = 1;
6946 if (i >= 1 && (source[i-1] & 0xffe0f800) == 0x40806800) // MTC0 $13
6947 dops[i].bt = 1;
4919de1e 6948
3e535354 6949 /* Is this the end of the block? */
fe807a8a 6950 if (i > 0 && dops[i-1].is_ujump) {
0787af86 6951 if (dops[i-1].rt1 == 0) { // not jal
277718fa 6952 int found_bbranch = 0, t = (cinfo[i-1].ba - start) / 4;
0787af86 6953 if ((u_int)(t - i) < 64 && start + (t+64)*4 < pagelimit) {
6954 // scan for a branch back to i+1
6955 for (j = t; j < t + 64; j++) {
6956 int tmpop = source[j] >> 26;
6957 if (tmpop == 1 || ((tmpop & ~3) == 4)) {
6958 int t2 = j + 1 + (int)(signed short)source[j];
6959 if (t2 == i + 1) {
6960 //printf("blk expand %08x<-%08x\n", start + (i+1)*4, start + j*4);
6961 found_bbranch = 1;
6962 break;
6963 }
6964 }
6965 }
6966 }
6967 if (!found_bbranch)
6968 done = 2;
57871462 6969 }
6970 else {
6971 if(stop_after_jal) done=1;
6972 // Stop on BREAK
6973 if((source[i+1]&0xfc00003f)==0x0d) done=1;
6974 }
6975 // Don't recompile stuff that's already compiled
6976 if(check_addr(start+i*4+4)) done=1;
6977 // Don't get too close to the limit
d3201e39 6978 if (i > MAXBLOCK - 64)
6979 done = 1;
57871462 6980 }
a5cd72d0 6981 if (dops[i].itype == HLECALL)
dc4fa8bc 6982 done = 1;
a5cd72d0 6983 else if (dops[i].itype == INTCALL)
dc4fa8bc 6984 done = 2;
a5cd72d0 6985 else if (dops[i].is_exception)
d1150cd6 6986 done = stop_after_jal ? 1 : 2;
6987 if (done == 2) {
1e973cb0 6988 // Does the block continue due to a branch?
6989 for(j=i-1;j>=0;j--)
6990 {
277718fa 6991 if(cinfo[j].ba==start+i*4) done=j=0; // Branch into delay slot
6992 if(cinfo[j].ba==start+i*4+4) done=j=0;
6993 if(cinfo[j].ba==start+i*4+8) done=j=0;
1e973cb0 6994 }
6995 }
75dec299 6996 //assert(i<MAXBLOCK-1);
57871462 6997 if(start+i*4==pagelimit-4) done=1;
6998 assert(start+i*4<pagelimit);
d3201e39 6999 if (i == MAXBLOCK - 2)
7000 done = 1;
57871462 7001 // Stop if we're compiling junk
a5cd72d0 7002 if (dops[i].itype == INTCALL && (++ni_count > 8 || dops[i].opcode == 0x11)) {
57871462 7003 done=stop_after_jal=1;
c43b5311 7004 SysPrintf("Disabled speculative precompilation\n");
57871462 7005 }
7006 }
4bdc30ab 7007 while (i > 0 && dops[i-1].is_jump)
7008 i--;
7009 assert(i > 0);
7010 assert(!dops[i-1].is_jump);
7011 slen = i;
4149788d 7012}
7013
7014// Basic liveness analysis for MIPS registers
7015static noinline void pass2_unneeded_regs(int istart,int iend,int r)
7016{
7017 int i;
7018 uint64_t u,gte_u,b,gte_b;
7019 uint64_t temp_u,temp_gte_u=0;
7020 uint64_t gte_u_unknown=0;
7021 if (HACK_ENABLED(NDHACK_GTE_UNNEEDED))
7022 gte_u_unknown=~0ll;
7023 if(iend==slen-1) {
7024 u=1;
7025 gte_u=gte_u_unknown;
7026 }else{
7027 //u=unneeded_reg[iend+1];
7028 u=1;
7029 gte_u=gte_unneeded[iend+1];
7030 }
7031
7032 for (i=iend;i>=istart;i--)
7033 {
7034 //printf("unneeded registers i=%d (%d,%d) r=%d\n",i,istart,iend,r);
7035 if(dops[i].is_jump)
7036 {
7037 // If subroutine call, flag return address as a possible branch target
7038 if(dops[i].rt1==31 && i<slen-2) dops[i+2].bt=1;
7039
277718fa 7040 if(cinfo[i].ba<start || cinfo[i].ba>=(start+slen*4))
4149788d 7041 {
7042 // Branch out of this block, flush all regs
7043 u=1;
7044 gte_u=gte_u_unknown;
7045 branch_unneeded_reg[i]=u;
7046 // Merge in delay slot
7047 u|=(1LL<<dops[i+1].rt1)|(1LL<<dops[i+1].rt2);
7048 u&=~((1LL<<dops[i+1].rs1)|(1LL<<dops[i+1].rs2));
7049 u|=1;
7050 gte_u|=gte_rt[i+1];
7051 gte_u&=~gte_rs[i+1];
7052 }
7053 else
7054 {
7055 // Internal branch, flag target
277718fa 7056 dops[(cinfo[i].ba-start)>>2].bt=1;
7057 if(cinfo[i].ba<=start+i*4) {
4149788d 7058 // Backward branch
7059 if(dops[i].is_ujump)
7060 {
7061 // Unconditional branch
7062 temp_u=1;
7063 temp_gte_u=0;
7064 } else {
7065 // Conditional branch (not taken case)
7066 temp_u=unneeded_reg[i+2];
7067 temp_gte_u&=gte_unneeded[i+2];
7068 }
7069 // Merge in delay slot
7070 temp_u|=(1LL<<dops[i+1].rt1)|(1LL<<dops[i+1].rt2);
7071 temp_u&=~((1LL<<dops[i+1].rs1)|(1LL<<dops[i+1].rs2));
7072 temp_u|=1;
7073 temp_gte_u|=gte_rt[i+1];
7074 temp_gte_u&=~gte_rs[i+1];
7075 temp_u|=(1LL<<dops[i].rt1)|(1LL<<dops[i].rt2);
7076 temp_u&=~((1LL<<dops[i].rs1)|(1LL<<dops[i].rs2));
7077 temp_u|=1;
7078 temp_gte_u|=gte_rt[i];
7079 temp_gte_u&=~gte_rs[i];
7080 unneeded_reg[i]=temp_u;
7081 gte_unneeded[i]=temp_gte_u;
7082 // Only go three levels deep. This recursion can take an
7083 // excessive amount of time if there are a lot of nested loops.
7084 if(r<2) {
277718fa 7085 pass2_unneeded_regs((cinfo[i].ba-start)>>2,i-1,r+1);
4149788d 7086 }else{
277718fa 7087 unneeded_reg[(cinfo[i].ba-start)>>2]=1;
7088 gte_unneeded[(cinfo[i].ba-start)>>2]=gte_u_unknown;
4149788d 7089 }
7090 } /*else*/ if(1) {
7091 if (dops[i].is_ujump)
7092 {
7093 // Unconditional branch
277718fa 7094 u=unneeded_reg[(cinfo[i].ba-start)>>2];
7095 gte_u=gte_unneeded[(cinfo[i].ba-start)>>2];
4149788d 7096 branch_unneeded_reg[i]=u;
7097 // Merge in delay slot
7098 u|=(1LL<<dops[i+1].rt1)|(1LL<<dops[i+1].rt2);
7099 u&=~((1LL<<dops[i+1].rs1)|(1LL<<dops[i+1].rs2));
7100 u|=1;
7101 gte_u|=gte_rt[i+1];
7102 gte_u&=~gte_rs[i+1];
7103 } else {
7104 // Conditional branch
277718fa 7105 b=unneeded_reg[(cinfo[i].ba-start)>>2];
7106 gte_b=gte_unneeded[(cinfo[i].ba-start)>>2];
4149788d 7107 branch_unneeded_reg[i]=b;
7108 // Branch delay slot
7109 b|=(1LL<<dops[i+1].rt1)|(1LL<<dops[i+1].rt2);
7110 b&=~((1LL<<dops[i+1].rs1)|(1LL<<dops[i+1].rs2));
7111 b|=1;
7112 gte_b|=gte_rt[i+1];
7113 gte_b&=~gte_rs[i+1];
7114 u&=b;
7115 gte_u&=gte_b;
7116 if(i<slen-1) {
7117 branch_unneeded_reg[i]&=unneeded_reg[i+2];
7118 } else {
7119 branch_unneeded_reg[i]=1;
7120 }
7121 }
7122 }
7123 }
7124 }
4149788d 7125 //u=1; // DEBUG
7126 // Written registers are unneeded
7127 u|=1LL<<dops[i].rt1;
7128 u|=1LL<<dops[i].rt2;
7129 gte_u|=gte_rt[i];
7130 // Accessed registers are needed
7131 u&=~(1LL<<dops[i].rs1);
7132 u&=~(1LL<<dops[i].rs2);
7133 gte_u&=~gte_rs[i];
7134 if(gte_rs[i]&&dops[i].rt1&&(unneeded_reg[i+1]&(1ll<<dops[i].rt1)))
7135 gte_u|=gte_rs[i]&gte_unneeded[i+1]; // MFC2/CFC2 to dead register, unneeded
90f98e7c 7136 if (dops[i].may_except || dops[i].itype == RFE)
7137 {
7138 // SYSCALL instruction, etc or conditional exception
7139 u=1;
7140 }
4149788d 7141 // Source-target dependencies
7142 // R0 is always unneeded
7143 u|=1;
7144 // Save it
7145 unneeded_reg[i]=u;
7146 gte_unneeded[i]=gte_u;
7147 /*
7148 printf("ur (%d,%d) %x: ",istart,iend,start+i*4);
7149 printf("U:");
7150 int r;
7151 for(r=1;r<=CCREG;r++) {
7152 if((unneeded_reg[i]>>r)&1) {
7153 if(r==HIREG) printf(" HI");
7154 else if(r==LOREG) printf(" LO");
7155 else printf(" r%d",r);
7156 }
7157 }
7158 printf("\n");
7159 */
7160 }
7161}
57871462 7162
f9e9616e 7163static noinline void pass2a_unneeded_other(void)
7164{
7165 int i, j;
7166 for (i = 0; i < slen; i++)
7167 {
7168 // remove redundant alignment checks
7169 if (dops[i].may_except && (dops[i].is_load || dops[i].is_store)
7170 && dops[i].rt1 != dops[i].rs1 && !dops[i].is_ds)
7171 {
7172 int base = dops[i].rs1, lsb = cinfo[i].imm, ls_type = dops[i].ls_type;
7173 int mask = ls_type == LS_32 ? 3 : 1;
7174 lsb &= mask;
7175 for (j = i + 1; j < slen; j++) {
7176 if (dops[j].bt || dops[j].is_jump)
7177 break;
7178 if ((dops[j].is_load || dops[j].is_store) && dops[j].rs1 == base
7179 && dops[j].ls_type == ls_type && (cinfo[j].imm & mask) == lsb)
7180 dops[j].may_except = 0;
7181 if (dops[j].rt1 == base)
7182 break;
7183 }
7184 }
7185 }
7186}
7187
4149788d 7188static noinline void pass3_register_alloc(u_int addr)
7189{
57871462 7190 struct regstat current; // Current register allocations/status
6cc8d23c 7191 clear_all_regs(current.regmap_entry);
57871462 7192 clear_all_regs(current.regmap);
6cc8d23c 7193 current.wasdirty = current.dirty = 0;
7194 current.u = unneeded_reg[0];
7195 alloc_reg(&current, 0, CCREG);
7196 dirty_reg(&current, CCREG);
7197 current.wasconst = 0;
7198 current.isconst = 0;
7199 current.loadedconst = 0;
90f98e7c 7200 current.noevict = 0;
9b495f6e 7201 //current.waswritten = 0;
57871462 7202 int ds=0;
7203 int cc=0;
4149788d 7204 int hr;
7205 int i, j;
6ebf4adf 7206
4149788d 7207 if (addr & 1) {
57871462 7208 // First instruction is delay slot
7209 cc=-1;
cf95b4f0 7210 dops[1].bt=1;
57871462 7211 ds=1;
7212 unneeded_reg[0]=1;
57871462 7213 }
9f51b4b9 7214
57871462 7215 for(i=0;i<slen;i++)
7216 {
cf95b4f0 7217 if(dops[i].bt)
57871462 7218 {
57871462 7219 for(hr=0;hr<HOST_REGS;hr++)
7220 {
7221 // Is this really necessary?
7222 if(current.regmap[hr]==0) current.regmap[hr]=-1;
7223 }
7224 current.isconst=0;
9b495f6e 7225 //current.waswritten=0;
57871462 7226 }
24385cae 7227
57871462 7228 memcpy(regmap_pre[i],current.regmap,sizeof(current.regmap));
7229 regs[i].wasconst=current.isconst;
57871462 7230 regs[i].wasdirty=current.dirty;
6cc8d23c 7231 regs[i].dirty=0;
7232 regs[i].u=0;
7233 regs[i].isconst=0;
8575a877 7234 regs[i].loadedconst=0;
fe807a8a 7235 if (!dops[i].is_jump) {
57871462 7236 if(i+1<slen) {
cf95b4f0 7237 current.u=unneeded_reg[i+1]&~((1LL<<dops[i].rs1)|(1LL<<dops[i].rs2));
57871462 7238 current.u|=1;
57871462 7239 } else {
7240 current.u=1;
57871462 7241 }
7242 } else {
7243 if(i+1<slen) {
cf95b4f0 7244 current.u=branch_unneeded_reg[i]&~((1LL<<dops[i+1].rs1)|(1LL<<dops[i+1].rs2));
7245 current.u&=~((1LL<<dops[i].rs1)|(1LL<<dops[i].rs2));
57871462 7246 current.u|=1;
7ebfcedf 7247 } else {
7248 SysPrintf("oops, branch at end of block with no delay slot @%08x\n", start + i*4);
7249 abort();
7250 }
57871462 7251 }
f9e9616e 7252 assert(dops[i].is_ds == ds);
57871462 7253 if(ds) {
7254 ds=0; // Skip delay slot, already allocated as part of branch
7255 // ...but we need to alloc it in case something jumps here
7256 if(i+1<slen) {
7257 current.u=branch_unneeded_reg[i-1]&unneeded_reg[i+1];
57871462 7258 }else{
7259 current.u=branch_unneeded_reg[i-1];
57871462 7260 }
cf95b4f0 7261 current.u&=~((1LL<<dops[i].rs1)|(1LL<<dops[i].rs2));
57871462 7262 current.u|=1;
57871462 7263 struct regstat temp;
7264 memcpy(&temp,&current,sizeof(current));
7265 temp.wasdirty=temp.dirty;
57871462 7266 // TODO: Take into account unconditional branches, as below
7267 delayslot_alloc(&temp,i);
7268 memcpy(regs[i].regmap,temp.regmap,sizeof(temp.regmap));
7269 regs[i].wasdirty=temp.wasdirty;
57871462 7270 regs[i].dirty=temp.dirty;
57871462 7271 regs[i].isconst=0;
7272 regs[i].wasconst=0;
7273 current.isconst=0;
7274 // Create entry (branch target) regmap
7275 for(hr=0;hr<HOST_REGS;hr++)
7276 {
7277 int r=temp.regmap[hr];
7278 if(r>=0) {
7279 if(r!=regmap_pre[i][hr]) {
7280 regs[i].regmap_entry[hr]=-1;
7281 }
7282 else
7283 {
7c3a5182 7284 assert(r < 64);
57871462 7285 if((current.u>>r)&1) {
7286 regs[i].regmap_entry[hr]=-1;
7287 regs[i].regmap[hr]=-1;
7288 //Don't clear regs in the delay slot as the branch might need them
7289 //current.regmap[hr]=-1;
7290 }else
7291 regs[i].regmap_entry[hr]=r;
57871462 7292 }
7293 } else {
7294 // First instruction expects CCREG to be allocated
9f51b4b9 7295 if(i==0&&hr==HOST_CCREG)
57871462 7296 regs[i].regmap_entry[hr]=CCREG;
7297 else
7298 regs[i].regmap_entry[hr]=-1;
7299 }
7300 }
7301 }
7302 else { // Not delay slot
90f98e7c 7303 current.noevict = 0;
cf95b4f0 7304 switch(dops[i].itype) {
57871462 7305 case UJUMP:
7306 //current.isconst=0; // DEBUG
7307 //current.wasconst=0; // DEBUG
7308 //regs[i].wasconst=0; // DEBUG
cf95b4f0 7309 clear_const(&current,dops[i].rt1);
57871462 7310 alloc_cc(&current,i);
7311 dirty_reg(&current,CCREG);
cf95b4f0 7312 if (dops[i].rt1==31) {
57871462 7313 alloc_reg(&current,i,31);
7314 dirty_reg(&current,31);
cf95b4f0 7315 //assert(dops[i+1].rs1!=31&&dops[i+1].rs2!=31);
7316 //assert(dops[i+1].rt1!=dops[i].rt1);
57871462 7317 #ifdef REG_PREFETCH
7318 alloc_reg(&current,i,PTEMP);
7319 #endif
57871462 7320 }
cf95b4f0 7321 dops[i].ooo=1;
269bb29a 7322 delayslot_alloc(&current,i+1);
57871462 7323 //current.isconst=0; // DEBUG
7324 ds=1;
57871462 7325 break;
7326 case RJUMP:
7327 //current.isconst=0;
7328 //current.wasconst=0;
7329 //regs[i].wasconst=0;
cf95b4f0 7330 clear_const(&current,dops[i].rs1);
7331 clear_const(&current,dops[i].rt1);
57871462 7332 alloc_cc(&current,i);
7333 dirty_reg(&current,CCREG);
4919de1e 7334 if (!ds_writes_rjump_rs(i)) {
cf95b4f0 7335 alloc_reg(&current,i,dops[i].rs1);
7336 if (dops[i].rt1!=0) {
7337 alloc_reg(&current,i,dops[i].rt1);
7338 dirty_reg(&current,dops[i].rt1);
57871462 7339 #ifdef REG_PREFETCH
7340 alloc_reg(&current,i,PTEMP);
7341 #endif
7342 }
7343 #ifdef USE_MINI_HT
cf95b4f0 7344 if(dops[i].rs1==31) { // JALR
57871462 7345 alloc_reg(&current,i,RHASH);
57871462 7346 alloc_reg(&current,i,RHTBL);
57871462 7347 }
7348 #endif
7349 delayslot_alloc(&current,i+1);
7350 } else {
7351 // The delay slot overwrites our source register,
7352 // allocate a temporary register to hold the old value.
7353 current.isconst=0;
7354 current.wasconst=0;
7355 regs[i].wasconst=0;
7356 delayslot_alloc(&current,i+1);
7357 current.isconst=0;
7358 alloc_reg(&current,i,RTEMP);
7359 }
7360 //current.isconst=0; // DEBUG
cf95b4f0 7361 dops[i].ooo=1;
57871462 7362 ds=1;
7363 break;
7364 case CJUMP:
7365 //current.isconst=0;
7366 //current.wasconst=0;
7367 //regs[i].wasconst=0;
cf95b4f0 7368 clear_const(&current,dops[i].rs1);
7369 clear_const(&current,dops[i].rs2);
7370 if((dops[i].opcode&0x3E)==4) // BEQ/BNE
57871462 7371 {
7372 alloc_cc(&current,i);
7373 dirty_reg(&current,CCREG);
cf95b4f0 7374 if(dops[i].rs1) alloc_reg(&current,i,dops[i].rs1);
7375 if(dops[i].rs2) alloc_reg(&current,i,dops[i].rs2);
7376 if((dops[i].rs1&&(dops[i].rs1==dops[i+1].rt1||dops[i].rs1==dops[i+1].rt2))||
7377 (dops[i].rs2&&(dops[i].rs2==dops[i+1].rt1||dops[i].rs2==dops[i+1].rt2))) {
57871462 7378 // The delay slot overwrites one of our conditions.
7379 // Allocate the branch condition registers instead.
57871462 7380 current.isconst=0;
7381 current.wasconst=0;
7382 regs[i].wasconst=0;
cf95b4f0 7383 if(dops[i].rs1) alloc_reg(&current,i,dops[i].rs1);
7384 if(dops[i].rs2) alloc_reg(&current,i,dops[i].rs2);
57871462 7385 }
e1190b87 7386 else
7387 {
cf95b4f0 7388 dops[i].ooo=1;
e1190b87 7389 delayslot_alloc(&current,i+1);
7390 }
57871462 7391 }
7392 else
cf95b4f0 7393 if((dops[i].opcode&0x3E)==6) // BLEZ/BGTZ
57871462 7394 {
7395 alloc_cc(&current,i);
7396 dirty_reg(&current,CCREG);
cf95b4f0 7397 alloc_reg(&current,i,dops[i].rs1);
7398 if(dops[i].rs1&&(dops[i].rs1==dops[i+1].rt1||dops[i].rs1==dops[i+1].rt2)) {
57871462 7399 // The delay slot overwrites one of our conditions.
7400 // Allocate the branch condition registers instead.
57871462 7401 current.isconst=0;
7402 current.wasconst=0;
7403 regs[i].wasconst=0;
cf95b4f0 7404 if(dops[i].rs1) alloc_reg(&current,i,dops[i].rs1);
57871462 7405 }
e1190b87 7406 else
7407 {
cf95b4f0 7408 dops[i].ooo=1;
e1190b87 7409 delayslot_alloc(&current,i+1);
7410 }
57871462 7411 }
7412 else
7413 // Don't alloc the delay slot yet because we might not execute it
cf95b4f0 7414 if((dops[i].opcode&0x3E)==0x14) // BEQL/BNEL
57871462 7415 {
7416 current.isconst=0;
7417 current.wasconst=0;
7418 regs[i].wasconst=0;
7419 alloc_cc(&current,i);
7420 dirty_reg(&current,CCREG);
cf95b4f0 7421 alloc_reg(&current,i,dops[i].rs1);
7422 alloc_reg(&current,i,dops[i].rs2);
57871462 7423 }
7424 else
cf95b4f0 7425 if((dops[i].opcode&0x3E)==0x16) // BLEZL/BGTZL
57871462 7426 {
7427 current.isconst=0;
7428 current.wasconst=0;
7429 regs[i].wasconst=0;
7430 alloc_cc(&current,i);
7431 dirty_reg(&current,CCREG);
cf95b4f0 7432 alloc_reg(&current,i,dops[i].rs1);
57871462 7433 }
7434 ds=1;
7435 //current.isconst=0;
7436 break;
7437 case SJUMP:
cf95b4f0 7438 clear_const(&current,dops[i].rs1);
7439 clear_const(&current,dops[i].rt1);
57871462 7440 {
7441 alloc_cc(&current,i);
7442 dirty_reg(&current,CCREG);
cf95b4f0 7443 alloc_reg(&current,i,dops[i].rs1);
ecca05e3 7444 if (dops[i].rt1 == 31) { // BLTZAL/BGEZAL
57871462 7445 alloc_reg(&current,i,31);
7446 dirty_reg(&current,31);
57871462 7447 }
ecca05e3 7448 if ((dops[i].rs1 &&
7449 (dops[i].rs1==dops[i+1].rt1||dops[i].rs1==dops[i+1].rt2)) // The delay slot overwrites the branch condition.
7450 ||(dops[i].rt1 == 31 && dops[i].rs1 == 31) // overwrites it's own condition
cf95b4f0 7451 ||(dops[i].rt1==31&&(dops[i+1].rs1==31||dops[i+1].rs2==31||dops[i+1].rt1==31||dops[i+1].rt2==31))) { // DS touches $ra
57871462 7452 // Allocate the branch condition registers instead.
57871462 7453 current.isconst=0;
7454 current.wasconst=0;
7455 regs[i].wasconst=0;
cf95b4f0 7456 if(dops[i].rs1) alloc_reg(&current,i,dops[i].rs1);
57871462 7457 }
e1190b87 7458 else
7459 {
cf95b4f0 7460 dops[i].ooo=1;
e1190b87 7461 delayslot_alloc(&current,i+1);
7462 }
57871462 7463 }
57871462 7464 ds=1;
7465 //current.isconst=0;
7466 break;
57871462 7467 case IMM16:
7468 imm16_alloc(&current,i);
7469 break;
7470 case LOAD:
7471 case LOADLR:
7472 load_alloc(&current,i);
7473 break;
7474 case STORE:
7475 case STORELR:
7476 store_alloc(&current,i);
7477 break;
7478 case ALU:
7479 alu_alloc(&current,i);
7480 break;
7481 case SHIFT:
7482 shift_alloc(&current,i);
7483 break;
7484 case MULTDIV:
7485 multdiv_alloc(&current,i);
7486 break;
7487 case SHIFTIMM:
7488 shiftimm_alloc(&current,i);
7489 break;
7490 case MOV:
7491 mov_alloc(&current,i);
7492 break;
7493 case COP0:
7494 cop0_alloc(&current,i);
7495 break;
a5cd72d0 7496 case RFE:
7497 rfe_alloc(&current,i);
81dbbf4c 7498 break;
b9b61529 7499 case COP2:
81dbbf4c 7500 cop2_alloc(&current,i);
57871462 7501 break;
b9b61529 7502 case C2LS:
7503 c2ls_alloc(&current,i);
7504 break;
7505 case C2OP:
7506 c2op_alloc(&current,i);
7507 break;
57871462 7508 case SYSCALL:
7139f3c8 7509 case HLECALL:
1e973cb0 7510 case INTCALL:
57871462 7511 syscall_alloc(&current,i);
7512 break;
57871462 7513 }
9f51b4b9 7514
57871462 7515 // Create entry (branch target) regmap
7516 for(hr=0;hr<HOST_REGS;hr++)
7517 {
581335b0 7518 int r,or;
57871462 7519 r=current.regmap[hr];
7520 if(r>=0) {
7521 if(r!=regmap_pre[i][hr]) {
7522 // TODO: delay slot (?)
7523 or=get_reg(regmap_pre[i],r); // Get old mapping for this register
9de8a0c3 7524 if(or<0||r>=TEMPREG){
57871462 7525 regs[i].regmap_entry[hr]=-1;
7526 }
7527 else
7528 {
7529 // Just move it to a different register
7530 regs[i].regmap_entry[hr]=r;
7531 // If it was dirty before, it's still dirty
9de8a0c3 7532 if((regs[i].wasdirty>>or)&1) dirty_reg(&current,r);
57871462 7533 }
7534 }
7535 else
7536 {
7537 // Unneeded
7538 if(r==0){
7539 regs[i].regmap_entry[hr]=0;
7540 }
7541 else
7c3a5182 7542 {
7543 assert(r<64);
57871462 7544 if((current.u>>r)&1) {
7545 regs[i].regmap_entry[hr]=-1;
7546 //regs[i].regmap[hr]=-1;
7547 current.regmap[hr]=-1;
7548 }else
7549 regs[i].regmap_entry[hr]=r;
7550 }
57871462 7551 }
7552 } else {
7553 // Branches expect CCREG to be allocated at the target
9f51b4b9 7554 if(regmap_pre[i][hr]==CCREG)
57871462 7555 regs[i].regmap_entry[hr]=CCREG;
7556 else
7557 regs[i].regmap_entry[hr]=-1;
7558 }
7559 }
7560 memcpy(regs[i].regmap,current.regmap,sizeof(current.regmap));
7561 }
27727b63 7562
9b495f6e 7563#if 0 // see do_store_smc_check()
277718fa 7564 if(i>0&&(dops[i-1].itype==STORE||dops[i-1].itype==STORELR||(dops[i-1].itype==C2LS&&dops[i-1].opcode==0x3a))&&(u_int)cinfo[i-1].imm<0x800)
cf95b4f0 7565 current.waswritten|=1<<dops[i-1].rs1;
7566 current.waswritten&=~(1<<dops[i].rt1);
7567 current.waswritten&=~(1<<dops[i].rt2);
277718fa 7568 if((dops[i].itype==STORE||dops[i].itype==STORELR||(dops[i].itype==C2LS&&dops[i].opcode==0x3a))&&(u_int)cinfo[i].imm>=0x800)
cf95b4f0 7569 current.waswritten&=~(1<<dops[i].rs1);
9b495f6e 7570#endif
27727b63 7571
57871462 7572 /* Branch post-alloc */
7573 if(i>0)
7574 {
57871462 7575 current.wasdirty=current.dirty;
cf95b4f0 7576 switch(dops[i-1].itype) {
57871462 7577 case UJUMP:
7578 memcpy(&branch_regs[i-1],&current,sizeof(current));
7579 branch_regs[i-1].isconst=0;
7580 branch_regs[i-1].wasconst=0;
cf95b4f0 7581 branch_regs[i-1].u=branch_unneeded_reg[i-1]&~((1LL<<dops[i-1].rs1)|(1LL<<dops[i-1].rs2));
57871462 7582 alloc_cc(&branch_regs[i-1],i-1);
7583 dirty_reg(&branch_regs[i-1],CCREG);
cf95b4f0 7584 if(dops[i-1].rt1==31) { // JAL
57871462 7585 alloc_reg(&branch_regs[i-1],i-1,31);
7586 dirty_reg(&branch_regs[i-1],31);
57871462 7587 }
7588 memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
40fca85b 7589 memcpy(constmap[i],constmap[i-1],sizeof(constmap[i]));
57871462 7590 break;
7591 case RJUMP:
7592 memcpy(&branch_regs[i-1],&current,sizeof(current));
7593 branch_regs[i-1].isconst=0;
7594 branch_regs[i-1].wasconst=0;
cf95b4f0 7595 branch_regs[i-1].u=branch_unneeded_reg[i-1]&~((1LL<<dops[i-1].rs1)|(1LL<<dops[i-1].rs2));
57871462 7596 alloc_cc(&branch_regs[i-1],i-1);
7597 dirty_reg(&branch_regs[i-1],CCREG);
cf95b4f0 7598 alloc_reg(&branch_regs[i-1],i-1,dops[i-1].rs1);
7599 if(dops[i-1].rt1!=0) { // JALR
7600 alloc_reg(&branch_regs[i-1],i-1,dops[i-1].rt1);
7601 dirty_reg(&branch_regs[i-1],dops[i-1].rt1);
57871462 7602 }
7603 #ifdef USE_MINI_HT
cf95b4f0 7604 if(dops[i-1].rs1==31) { // JALR
57871462 7605 alloc_reg(&branch_regs[i-1],i-1,RHASH);
57871462 7606 alloc_reg(&branch_regs[i-1],i-1,RHTBL);
57871462 7607 }
7608 #endif
7609 memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
40fca85b 7610 memcpy(constmap[i],constmap[i-1],sizeof(constmap[i]));
57871462 7611 break;
7612 case CJUMP:
cf95b4f0 7613 if((dops[i-1].opcode&0x3E)==4) // BEQ/BNE
57871462 7614 {
7615 alloc_cc(&current,i-1);
7616 dirty_reg(&current,CCREG);
cf95b4f0 7617 if((dops[i-1].rs1&&(dops[i-1].rs1==dops[i].rt1||dops[i-1].rs1==dops[i].rt2))||
7618 (dops[i-1].rs2&&(dops[i-1].rs2==dops[i].rt1||dops[i-1].rs2==dops[i].rt2))) {
57871462 7619 // The delay slot overwrote one of our conditions
7620 // Delay slot goes after the test (in order)
cf95b4f0 7621 current.u=branch_unneeded_reg[i-1]&~((1LL<<dops[i].rs1)|(1LL<<dops[i].rs2));
57871462 7622 current.u|=1;
57871462 7623 delayslot_alloc(&current,i);
7624 current.isconst=0;
7625 }
7626 else
7627 {
cf95b4f0 7628 current.u=branch_unneeded_reg[i-1]&~((1LL<<dops[i-1].rs1)|(1LL<<dops[i-1].rs2));
57871462 7629 // Alloc the branch condition registers
cf95b4f0 7630 if(dops[i-1].rs1) alloc_reg(&current,i-1,dops[i-1].rs1);
7631 if(dops[i-1].rs2) alloc_reg(&current,i-1,dops[i-1].rs2);
57871462 7632 }
7633 memcpy(&branch_regs[i-1],&current,sizeof(current));
7634 branch_regs[i-1].isconst=0;
7635 branch_regs[i-1].wasconst=0;
7636 memcpy(&branch_regs[i-1].regmap_entry,&current.regmap,sizeof(current.regmap));
40fca85b 7637 memcpy(constmap[i],constmap[i-1],sizeof(constmap[i]));
57871462 7638 }
7639 else
cf95b4f0 7640 if((dops[i-1].opcode&0x3E)==6) // BLEZ/BGTZ
57871462 7641 {
7642 alloc_cc(&current,i-1);
7643 dirty_reg(&current,CCREG);
cf95b4f0 7644 if(dops[i-1].rs1==dops[i].rt1||dops[i-1].rs1==dops[i].rt2) {
57871462 7645 // The delay slot overwrote the branch condition
7646 // Delay slot goes after the test (in order)
cf95b4f0 7647 current.u=branch_unneeded_reg[i-1]&~((1LL<<dops[i].rs1)|(1LL<<dops[i].rs2));
57871462 7648 current.u|=1;
57871462 7649 delayslot_alloc(&current,i);
7650 current.isconst=0;
7651 }
7652 else
7653 {
cf95b4f0 7654 current.u=branch_unneeded_reg[i-1]&~(1LL<<dops[i-1].rs1);
57871462 7655 // Alloc the branch condition register
cf95b4f0 7656 alloc_reg(&current,i-1,dops[i-1].rs1);
57871462 7657 }
7658 memcpy(&branch_regs[i-1],&current,sizeof(current));
7659 branch_regs[i-1].isconst=0;
7660 branch_regs[i-1].wasconst=0;
7661 memcpy(&branch_regs[i-1].regmap_entry,&current.regmap,sizeof(current.regmap));
40fca85b 7662 memcpy(constmap[i],constmap[i-1],sizeof(constmap[i]));
57871462 7663 }
57871462 7664 break;
7665 case SJUMP:
57871462 7666 {
7667 alloc_cc(&current,i-1);
7668 dirty_reg(&current,CCREG);
cf95b4f0 7669 if(dops[i-1].rs1==dops[i].rt1||dops[i-1].rs1==dops[i].rt2) {
57871462 7670 // The delay slot overwrote the branch condition
7671 // Delay slot goes after the test (in order)
cf95b4f0 7672 current.u=branch_unneeded_reg[i-1]&~((1LL<<dops[i].rs1)|(1LL<<dops[i].rs2));
57871462 7673 current.u|=1;
57871462 7674 delayslot_alloc(&current,i);
7675 current.isconst=0;
7676 }
7677 else
7678 {
cf95b4f0 7679 current.u=branch_unneeded_reg[i-1]&~(1LL<<dops[i-1].rs1);
57871462 7680 // Alloc the branch condition register
cf95b4f0 7681 alloc_reg(&current,i-1,dops[i-1].rs1);
57871462 7682 }
7683 memcpy(&branch_regs[i-1],&current,sizeof(current));
7684 branch_regs[i-1].isconst=0;
7685 branch_regs[i-1].wasconst=0;
7686 memcpy(&branch_regs[i-1].regmap_entry,&current.regmap,sizeof(current.regmap));
40fca85b 7687 memcpy(constmap[i],constmap[i-1],sizeof(constmap[i]));
57871462 7688 }
57871462 7689 break;
57871462 7690 }
7691
fe807a8a 7692 if (dops[i-1].is_ujump)
57871462 7693 {
cf95b4f0 7694 if(dops[i-1].rt1==31) // JAL/JALR
57871462 7695 {
7696 // Subroutine call will return here, don't alloc any registers
57871462 7697 current.dirty=0;
7698 clear_all_regs(current.regmap);
7699 alloc_reg(&current,i,CCREG);
7700 dirty_reg(&current,CCREG);
7701 }
7702 else if(i+1<slen)
7703 {
7704 // Internal branch will jump here, match registers to caller
57871462 7705 current.dirty=0;
7706 clear_all_regs(current.regmap);
7707 alloc_reg(&current,i,CCREG);
7708 dirty_reg(&current,CCREG);
7709 for(j=i-1;j>=0;j--)
7710 {
277718fa 7711 if(cinfo[j].ba==start+i*4+4) {
57871462 7712 memcpy(current.regmap,branch_regs[j].regmap,sizeof(current.regmap));
57871462 7713 current.dirty=branch_regs[j].dirty;
7714 break;
7715 }
7716 }
7717 while(j>=0) {
277718fa 7718 if(cinfo[j].ba==start+i*4+4) {
57871462 7719 for(hr=0;hr<HOST_REGS;hr++) {
7720 if(current.regmap[hr]!=branch_regs[j].regmap[hr]) {
7721 current.regmap[hr]=-1;
7722 }
57871462 7723 current.dirty&=branch_regs[j].dirty;
7724 }
7725 }
7726 j--;
7727 }
7728 }
7729 }
7730 }
7731
7732 // Count cycles in between branches
277718fa 7733 cinfo[i].ccadj = CLOCK_ADJUST(cc);
a5cd72d0 7734 if (i > 0 && (dops[i-1].is_jump || dops[i].is_exception))
57871462 7735 {
7736 cc=0;
7737 }
71e490c5 7738#if !defined(DRC_DBG)
cf95b4f0 7739 else if(dops[i].itype==C2OP&&gte_cycletab[source[i]&0x3f]>2)
054175e9 7740 {
81dbbf4c 7741 // this should really be removed since the real stalls have been implemented,
7742 // but doing so causes sizeable perf regression against the older version
7743 u_int gtec = gte_cycletab[source[i] & 0x3f];
32631e6a 7744 cc += HACK_ENABLED(NDHACK_NO_STALLS) ? gtec/2 : 2;
fb407447 7745 }
cf95b4f0 7746 else if(i>1&&dops[i].itype==STORE&&dops[i-1].itype==STORE&&dops[i-2].itype==STORE&&!dops[i].bt)
5fdcbb5a 7747 {
7748 cc+=4;
7749 }
cf95b4f0 7750 else if(dops[i].itype==C2LS)
fb407447 7751 {
81dbbf4c 7752 // same as with C2OP
32631e6a 7753 cc += HACK_ENABLED(NDHACK_NO_STALLS) ? 4 : 2;
fb407447 7754 }
7755#endif
57871462 7756 else
7757 {
7758 cc++;
7759 }
7760
cf95b4f0 7761 if(!dops[i].is_ds) {
57871462 7762 regs[i].dirty=current.dirty;
7763 regs[i].isconst=current.isconst;
40fca85b 7764 memcpy(constmap[i],current_constmap,sizeof(constmap[i]));
57871462 7765 }
7766 for(hr=0;hr<HOST_REGS;hr++) {
7767 if(hr!=EXCLUDE_REG&&regs[i].regmap[hr]>=0) {
7768 if(regmap_pre[i][hr]!=regs[i].regmap[hr]) {
7769 regs[i].wasconst&=~(1<<hr);
7770 }
7771 }
7772 }
9b495f6e 7773 //regs[i].waswritten=current.waswritten;
57871462 7774 }
4149788d 7775}
9f51b4b9 7776
4149788d 7777static noinline void pass4_cull_unused_regs(void)
7778{
53358c1d 7779 u_int last_needed_regs[4] = {0,0,0,0};
4149788d 7780 u_int nr=0;
7781 int i;
9f51b4b9 7782
57871462 7783 for (i=slen-1;i>=0;i--)
7784 {
7785 int hr;
53358c1d 7786 __builtin_prefetch(regs[i-2].regmap);
fe807a8a 7787 if(dops[i].is_jump)
57871462 7788 {
277718fa 7789 if(cinfo[i].ba<start || cinfo[i].ba>=(start+slen*4))
57871462 7790 {
7791 // Branch out of this block, don't need anything
7792 nr=0;
7793 }
7794 else
7795 {
7796 // Internal branch
7797 // Need whatever matches the target
7798 nr=0;
277718fa 7799 int t=(cinfo[i].ba-start)>>2;
57871462 7800 for(hr=0;hr<HOST_REGS;hr++)
7801 {
7802 if(regs[i].regmap_entry[hr]>=0) {
7803 if(regs[i].regmap_entry[hr]==regs[t].regmap_entry[hr]) nr|=1<<hr;
7804 }
7805 }
7806 }
7807 // Conditional branch may need registers for following instructions
fe807a8a 7808 if (!dops[i].is_ujump)
57871462 7809 {
7810 if(i<slen-2) {
53358c1d 7811 nr |= last_needed_regs[(i+2) & 3];
57871462 7812 for(hr=0;hr<HOST_REGS;hr++)
7813 {
7814 if(regmap_pre[i+2][hr]>=0&&get_reg(regs[i+2].regmap_entry,regmap_pre[i+2][hr])<0) nr&=~(1<<hr);
7815 //if((regmap_entry[i+2][hr])>=0) if(!((nr>>hr)&1)) printf("%x-bogus(%d=%d)\n",start+i*4,hr,regmap_entry[i+2][hr]);
7816 }
7817 }
7818 }
7819 // Don't need stuff which is overwritten
f5955059 7820 //if(regs[i].regmap[hr]!=regmap_pre[i][hr]) nr&=~(1<<hr);
7821 //if(regs[i].regmap[hr]<0) nr&=~(1<<hr);
57871462 7822 // Merge in delay slot
53358c1d 7823 if (dops[i+1].rt1) nr &= ~get_regm(regs[i].regmap, dops[i+1].rt1);
7824 if (dops[i+1].rt2) nr &= ~get_regm(regs[i].regmap, dops[i+1].rt2);
7825 nr |= get_regm(regmap_pre[i], dops[i+1].rs1);
7826 nr |= get_regm(regmap_pre[i], dops[i+1].rs2);
7827 nr |= get_regm(regs[i].regmap_entry, dops[i+1].rs1);
7828 nr |= get_regm(regs[i].regmap_entry, dops[i+1].rs2);
7829 if (ram_offset && (dops[i+1].is_load || dops[i+1].is_store)) {
7830 nr |= get_regm(regmap_pre[i], ROREG);
7831 nr |= get_regm(regs[i].regmap_entry, ROREG);
7832 }
7833 if (dops[i+1].is_store) {
7834 nr |= get_regm(regmap_pre[i], INVCP);
7835 nr |= get_regm(regs[i].regmap_entry, INVCP);
57871462 7836 }
7837 }
277718fa 7838 else if (dops[i].is_exception)
57871462 7839 {
277718fa 7840 // SYSCALL instruction, etc
57871462 7841 nr=0;
7842 }
7843 else // Non-branch
7844 {
7845 if(i<slen-1) {
7846 for(hr=0;hr<HOST_REGS;hr++) {
7847 if(regmap_pre[i+1][hr]>=0&&get_reg(regs[i+1].regmap_entry,regmap_pre[i+1][hr])<0) nr&=~(1<<hr);
7848 if(regs[i].regmap[hr]!=regmap_pre[i+1][hr]) nr&=~(1<<hr);
7849 if(regs[i].regmap[hr]!=regmap_pre[i][hr]) nr&=~(1<<hr);
7850 if(regs[i].regmap[hr]<0) nr&=~(1<<hr);
7851 }
7852 }
7853 }
53358c1d 7854 // Overwritten registers are not needed
7855 if (dops[i].rt1) nr &= ~get_regm(regs[i].regmap, dops[i].rt1);
7856 if (dops[i].rt2) nr &= ~get_regm(regs[i].regmap, dops[i].rt2);
7857 nr &= ~get_regm(regs[i].regmap, FTEMP);
7858 // Source registers are needed
7859 nr |= get_regm(regmap_pre[i], dops[i].rs1);
7860 nr |= get_regm(regmap_pre[i], dops[i].rs2);
7861 nr |= get_regm(regs[i].regmap_entry, dops[i].rs1);
7862 nr |= get_regm(regs[i].regmap_entry, dops[i].rs2);
7863 if (ram_offset && (dops[i].is_load || dops[i].is_store)) {
7864 nr |= get_regm(regmap_pre[i], ROREG);
7865 nr |= get_regm(regs[i].regmap_entry, ROREG);
7866 }
7867 if (dops[i].is_store) {
7868 nr |= get_regm(regmap_pre[i], INVCP);
7869 nr |= get_regm(regs[i].regmap_entry, INVCP);
7870 }
7871
7872 if (i > 0 && !dops[i].bt && regs[i].wasdirty)
57871462 7873 for(hr=0;hr<HOST_REGS;hr++)
7874 {
57871462 7875 // Don't store a register immediately after writing it,
7876 // may prevent dual-issue.
7877 // But do so if this is a branch target, otherwise we
7878 // might have to load the register before the branch.
53358c1d 7879 if((regs[i].wasdirty>>hr)&1) {
7c3a5182 7880 if((regmap_pre[i][hr]>0&&!((unneeded_reg[i]>>regmap_pre[i][hr])&1))) {
9de8a0c3 7881 if(dops[i-1].rt1==regmap_pre[i][hr]) nr|=1<<hr;
7882 if(dops[i-1].rt2==regmap_pre[i][hr]) nr|=1<<hr;
57871462 7883 }
7c3a5182 7884 if((regs[i].regmap_entry[hr]>0&&!((unneeded_reg[i]>>regs[i].regmap_entry[hr])&1))) {
9de8a0c3 7885 if(dops[i-1].rt1==regs[i].regmap_entry[hr]) nr|=1<<hr;
7886 if(dops[i-1].rt2==regs[i].regmap_entry[hr]) nr|=1<<hr;
57871462 7887 }
7888 }
7889 }
7890 // Cycle count is needed at branches. Assume it is needed at the target too.
de6dbc52 7891 if (i == 0 || dops[i].bt || dops[i].may_except || dops[i].itype == CJUMP) {
57871462 7892 if(regmap_pre[i][HOST_CCREG]==CCREG) nr|=1<<HOST_CCREG;
7893 if(regs[i].regmap_entry[HOST_CCREG]==CCREG) nr|=1<<HOST_CCREG;
7894 }
7895 // Save it
53358c1d 7896 last_needed_regs[i & 3] = nr;
9f51b4b9 7897
57871462 7898 // Deallocate unneeded registers
7899 for(hr=0;hr<HOST_REGS;hr++)
7900 {
7901 if(!((nr>>hr)&1)) {
7902 if(regs[i].regmap_entry[hr]!=CCREG) regs[i].regmap_entry[hr]=-1;
fe807a8a 7903 if(dops[i].is_jump)
57871462 7904 {
37387d8b 7905 int map1 = 0, map2 = 0, temp = 0; // or -1 ??
7906 if (dops[i+1].is_load || dops[i+1].is_store)
7907 map1 = ROREG;
7908 if (dops[i+1].is_store)
7909 map2 = INVCP;
7910 if(dops[i+1].itype==LOADLR || dops[i+1].itype==STORELR || dops[i+1].itype==C2LS)
7911 temp = FTEMP;
9de8a0c3 7912 if(regs[i].regmap[hr]!=dops[i].rs1 && regs[i].regmap[hr]!=dops[i].rs2 &&
7913 regs[i].regmap[hr]!=dops[i].rt1 && regs[i].regmap[hr]!=dops[i].rt2 &&
7914 regs[i].regmap[hr]!=dops[i+1].rt1 && regs[i].regmap[hr]!=dops[i+1].rt2 &&
cf95b4f0 7915 regs[i].regmap[hr]!=dops[i+1].rs1 && regs[i].regmap[hr]!=dops[i+1].rs2 &&
9de8a0c3 7916 regs[i].regmap[hr]!=temp && regs[i].regmap[hr]!=PTEMP &&
57871462 7917 regs[i].regmap[hr]!=RHASH && regs[i].regmap[hr]!=RHTBL &&
7918 regs[i].regmap[hr]!=RTEMP && regs[i].regmap[hr]!=CCREG &&
37387d8b 7919 regs[i].regmap[hr]!=map1 && regs[i].regmap[hr]!=map2)
57871462 7920 {
7921 regs[i].regmap[hr]=-1;
7922 regs[i].isconst&=~(1<<hr);
a550c61c 7923 regs[i].dirty&=~(1<<hr);
7924 regs[i+1].wasdirty&=~(1<<hr);
9de8a0c3 7925 if(branch_regs[i].regmap[hr]!=dops[i].rs1 && branch_regs[i].regmap[hr]!=dops[i].rs2 &&
7926 branch_regs[i].regmap[hr]!=dops[i].rt1 && branch_regs[i].regmap[hr]!=dops[i].rt2 &&
7927 branch_regs[i].regmap[hr]!=dops[i+1].rt1 && branch_regs[i].regmap[hr]!=dops[i+1].rt2 &&
cf95b4f0 7928 branch_regs[i].regmap[hr]!=dops[i+1].rs1 && branch_regs[i].regmap[hr]!=dops[i+1].rs2 &&
9de8a0c3 7929 branch_regs[i].regmap[hr]!=temp && branch_regs[i].regmap[hr]!=PTEMP &&
57871462 7930 branch_regs[i].regmap[hr]!=RHASH && branch_regs[i].regmap[hr]!=RHTBL &&
7931 branch_regs[i].regmap[hr]!=RTEMP && branch_regs[i].regmap[hr]!=CCREG &&
37387d8b 7932 branch_regs[i].regmap[hr]!=map1 && branch_regs[i].regmap[hr]!=map2)
57871462 7933 {
7934 branch_regs[i].regmap[hr]=-1;
7935 branch_regs[i].regmap_entry[hr]=-1;
fe807a8a 7936 if (!dops[i].is_ujump)
57871462 7937 {
fe807a8a 7938 if (i < slen-2) {
57871462 7939 regmap_pre[i+2][hr]=-1;
79c75f1b 7940 regs[i+2].wasconst&=~(1<<hr);
57871462 7941 }
7942 }
7943 }
7944 }
7945 }
7946 else
7947 {
7948 // Non-branch
7949 if(i>0)
7950 {
37387d8b 7951 int map1 = -1, map2 = -1, temp=-1;
7952 if (dops[i].is_load || dops[i].is_store)
7953 map1 = ROREG;
7954 if (dops[i].is_store)
7955 map2 = INVCP;
7956 if (dops[i].itype==LOADLR || dops[i].itype==STORELR || dops[i].itype==C2LS)
7957 temp = FTEMP;
9de8a0c3 7958 if(regs[i].regmap[hr]!=dops[i].rt1 && regs[i].regmap[hr]!=dops[i].rt2 &&
cf95b4f0 7959 regs[i].regmap[hr]!=dops[i].rs1 && regs[i].regmap[hr]!=dops[i].rs2 &&
9de8a0c3 7960 regs[i].regmap[hr]!=temp && regs[i].regmap[hr]!=map1 && regs[i].regmap[hr]!=map2 &&
4b1c7cd1 7961 //(dops[i].itype!=SPAN||regs[i].regmap[hr]!=CCREG)
7962 regs[i].regmap[hr] != CCREG)
57871462 7963 {
cf95b4f0 7964 if(i<slen-1&&!dops[i].is_ds) {
ad49de89 7965 assert(regs[i].regmap[hr]<64);
afec9d44 7966 if(regmap_pre[i+1][hr]!=-1 || regs[i].regmap[hr]>0)
57871462 7967 if(regmap_pre[i+1][hr]!=regs[i].regmap[hr])
57871462 7968 {
c43b5311 7969 SysPrintf("fail: %x (%d %d!=%d)\n",start+i*4,hr,regmap_pre[i+1][hr],regs[i].regmap[hr]);
57871462 7970 assert(regmap_pre[i+1][hr]==regs[i].regmap[hr]);
7971 }
7972 regmap_pre[i+1][hr]=-1;
7973 if(regs[i+1].regmap_entry[hr]==CCREG) regs[i+1].regmap_entry[hr]=-1;
79c75f1b 7974 regs[i+1].wasconst&=~(1<<hr);
57871462 7975 }
7976 regs[i].regmap[hr]=-1;
7977 regs[i].isconst&=~(1<<hr);
a550c61c 7978 regs[i].dirty&=~(1<<hr);
7979 regs[i+1].wasdirty&=~(1<<hr);
57871462 7980 }
7981 }
7982 }
3968e69e 7983 } // if needed
7984 } // for hr
57871462 7985 }
4149788d 7986}
9f51b4b9 7987
4149788d 7988// If a register is allocated during a loop, try to allocate it for the
7989// entire loop, if possible. This avoids loading/storing registers
7990// inside of the loop.
7991static noinline void pass5a_preallocate1(void)
7992{
7993 int i, j, hr;
57871462 7994 signed char f_regmap[HOST_REGS];
7995 clear_all_regs(f_regmap);
7996 for(i=0;i<slen-1;i++)
7997 {
cf95b4f0 7998 if(dops[i].itype==UJUMP||dops[i].itype==CJUMP||dops[i].itype==SJUMP)
57871462 7999 {
277718fa 8000 if(cinfo[i].ba>=start && cinfo[i].ba<(start+i*4))
cf95b4f0 8001 if(dops[i+1].itype==NOP||dops[i+1].itype==MOV||dops[i+1].itype==ALU
8002 ||dops[i+1].itype==SHIFTIMM||dops[i+1].itype==IMM16||dops[i+1].itype==LOAD
a5cd72d0 8003 ||dops[i+1].itype==STORE||dops[i+1].itype==STORELR
8004 ||dops[i+1].itype==SHIFT
cf95b4f0 8005 ||dops[i+1].itype==COP2||dops[i+1].itype==C2LS||dops[i+1].itype==C2OP)
57871462 8006 {
277718fa 8007 int t=(cinfo[i].ba-start)>>2;
fe807a8a 8008 if(t > 0 && !dops[t-1].is_jump) // loop_preload can't handle jumps into delay slots
cf95b4f0 8009 if(t<2||(dops[t-2].itype!=UJUMP&&dops[t-2].itype!=RJUMP)||dops[t-2].rt1!=31) // call/ret assumes no registers allocated
57871462 8010 for(hr=0;hr<HOST_REGS;hr++)
8011 {
7c3a5182 8012 if(regs[i].regmap[hr]>=0) {
b372a952 8013 if(f_regmap[hr]!=regs[i].regmap[hr]) {
8014 // dealloc old register
8015 int n;
8016 for(n=0;n<HOST_REGS;n++)
8017 {
8018 if(f_regmap[n]==regs[i].regmap[hr]) {f_regmap[n]=-1;}
8019 }
8020 // and alloc new one
8021 f_regmap[hr]=regs[i].regmap[hr];
8022 }
8023 }
7c3a5182 8024 if(branch_regs[i].regmap[hr]>=0) {
b372a952 8025 if(f_regmap[hr]!=branch_regs[i].regmap[hr]) {
8026 // dealloc old register
8027 int n;
8028 for(n=0;n<HOST_REGS;n++)
8029 {
8030 if(f_regmap[n]==branch_regs[i].regmap[hr]) {f_regmap[n]=-1;}
8031 }
8032 // and alloc new one
8033 f_regmap[hr]=branch_regs[i].regmap[hr];
8034 }
8035 }
cf95b4f0 8036 if(dops[i].ooo) {
277718fa 8037 if(count_free_regs(regs[i].regmap)<=cinfo[i+1].min_free_regs)
e1190b87 8038 f_regmap[hr]=branch_regs[i].regmap[hr];
8039 }else{
277718fa 8040 if(count_free_regs(branch_regs[i].regmap)<=cinfo[i+1].min_free_regs)
57871462 8041 f_regmap[hr]=branch_regs[i].regmap[hr];
8042 }
8043 // Avoid dirty->clean transition
e1190b87 8044 #ifdef DESTRUCTIVE_WRITEBACK
57871462 8045 if(t>0) if(get_reg(regmap_pre[t],f_regmap[hr])>=0) if((regs[t].wasdirty>>get_reg(regmap_pre[t],f_regmap[hr]))&1) f_regmap[hr]=-1;
e1190b87 8046 #endif
8047 // This check is only strictly required in the DESTRUCTIVE_WRITEBACK
8048 // case above, however it's always a good idea. We can't hoist the
8049 // load if the register was already allocated, so there's no point
8050 // wasting time analyzing most of these cases. It only "succeeds"
8051 // when the mapping was different and the load can be replaced with
8052 // a mov, which is of negligible benefit. So such cases are
8053 // skipped below.
57871462 8054 if(f_regmap[hr]>0) {
198df76f 8055 if(regs[t].regmap[hr]==f_regmap[hr]||(regs[t].regmap_entry[hr]<0&&get_reg(regmap_pre[t],f_regmap[hr])<0)) {
57871462 8056 int r=f_regmap[hr];
8057 for(j=t;j<=i;j++)
8058 {
277718fa 8059 //printf("Test %x -> %x, %x %d/%d\n",start+i*4,cinfo[i].ba,start+j*4,hr,r);
57871462 8060 if(r<34&&((unneeded_reg[j]>>r)&1)) break;
00fa9369 8061 assert(r < 64);
9de8a0c3 8062 if(regs[j].regmap[hr]==f_regmap[hr]&&f_regmap[hr]<TEMPREG) {
277718fa 8063 //printf("Hit %x -> %x, %x %d/%d\n",start+i*4,cinfo[i].ba,start+j*4,hr,r);
57871462 8064 int k;
8065 if(regs[i].regmap[hr]==-1&&branch_regs[i].regmap[hr]==-1) {
670c0f22 8066 if(get_reg(regs[i].regmap,f_regmap[hr])>=0) break;
57871462 8067 if(get_reg(regs[i+2].regmap,f_regmap[hr])>=0) break;
57871462 8068 k=i;
8069 while(k>1&&regs[k-1].regmap[hr]==-1) {
277718fa 8070 if(count_free_regs(regs[k-1].regmap)<=cinfo[k-1].min_free_regs) {
e1190b87 8071 //printf("no free regs for store %x\n",start+(k-1)*4);
8072 break;
57871462 8073 }
57871462 8074 if(get_reg(regs[k-1].regmap,f_regmap[hr])>=0) {
8075 //printf("no-match due to different register\n");
8076 break;
8077 }
fe807a8a 8078 if (dops[k-2].is_jump) {
57871462 8079 //printf("no-match due to branch\n");
8080 break;
8081 }
8082 // call/ret fast path assumes no registers allocated
cf95b4f0 8083 if(k>2&&(dops[k-3].itype==UJUMP||dops[k-3].itype==RJUMP)&&dops[k-3].rt1==31) {
57871462 8084 break;
8085 }
57871462 8086 k--;
8087 }
57871462 8088 if(regs[k-1].regmap[hr]==f_regmap[hr]&&regmap_pre[k][hr]==f_regmap[hr]) {
8089 //printf("Extend r%d, %x ->\n",hr,start+k*4);
8090 while(k<i) {
8091 regs[k].regmap_entry[hr]=f_regmap[hr];
8092 regs[k].regmap[hr]=f_regmap[hr];
8093 regmap_pre[k+1][hr]=f_regmap[hr];
8094 regs[k].wasdirty&=~(1<<hr);
8095 regs[k].dirty&=~(1<<hr);
8096 regs[k].wasdirty|=(1<<hr)&regs[k-1].dirty;
8097 regs[k].dirty|=(1<<hr)&regs[k].wasdirty;
8098 regs[k].wasconst&=~(1<<hr);
8099 regs[k].isconst&=~(1<<hr);
8100 k++;
8101 }
8102 }
8103 else {
8104 //printf("Fail Extend r%d, %x ->\n",hr,start+k*4);
8105 break;
8106 }
8107 assert(regs[i-1].regmap[hr]==f_regmap[hr]);
8108 if(regs[i-1].regmap[hr]==f_regmap[hr]&&regmap_pre[i][hr]==f_regmap[hr]) {
8109 //printf("OK fill %x (r%d)\n",start+i*4,hr);
8110 regs[i].regmap_entry[hr]=f_regmap[hr];
8111 regs[i].regmap[hr]=f_regmap[hr];
8112 regs[i].wasdirty&=~(1<<hr);
8113 regs[i].dirty&=~(1<<hr);
8114 regs[i].wasdirty|=(1<<hr)&regs[i-1].dirty;
8115 regs[i].dirty|=(1<<hr)&regs[i-1].dirty;
8116 regs[i].wasconst&=~(1<<hr);
8117 regs[i].isconst&=~(1<<hr);
8118 branch_regs[i].regmap_entry[hr]=f_regmap[hr];
8119 branch_regs[i].wasdirty&=~(1<<hr);
8120 branch_regs[i].wasdirty|=(1<<hr)&regs[i].dirty;
8121 branch_regs[i].regmap[hr]=f_regmap[hr];
8122 branch_regs[i].dirty&=~(1<<hr);
8123 branch_regs[i].dirty|=(1<<hr)&regs[i].dirty;
8124 branch_regs[i].wasconst&=~(1<<hr);
8125 branch_regs[i].isconst&=~(1<<hr);
fe807a8a 8126 if (!dops[i].is_ujump) {
57871462 8127 regmap_pre[i+2][hr]=f_regmap[hr];
8128 regs[i+2].wasdirty&=~(1<<hr);
8129 regs[i+2].wasdirty|=(1<<hr)&regs[i].dirty;
57871462 8130 }
8131 }
8132 }
8133 for(k=t;k<j;k++) {
e1190b87 8134 // Alloc register clean at beginning of loop,
8135 // but may dirty it in pass 6
57871462 8136 regs[k].regmap_entry[hr]=f_regmap[hr];
8137 regs[k].regmap[hr]=f_regmap[hr];
57871462 8138 regs[k].dirty&=~(1<<hr);
8139 regs[k].wasconst&=~(1<<hr);
8140 regs[k].isconst&=~(1<<hr);
fe807a8a 8141 if (dops[k].is_jump) {
e1190b87 8142 branch_regs[k].regmap_entry[hr]=f_regmap[hr];
8143 branch_regs[k].regmap[hr]=f_regmap[hr];
8144 branch_regs[k].dirty&=~(1<<hr);
8145 branch_regs[k].wasconst&=~(1<<hr);
8146 branch_regs[k].isconst&=~(1<<hr);
fe807a8a 8147 if (!dops[k].is_ujump) {
e1190b87 8148 regmap_pre[k+2][hr]=f_regmap[hr];
8149 regs[k+2].wasdirty&=~(1<<hr);
e1190b87 8150 }
8151 }
8152 else
8153 {
8154 regmap_pre[k+1][hr]=f_regmap[hr];
8155 regs[k+1].wasdirty&=~(1<<hr);
8156 }
57871462 8157 }
8158 if(regs[j].regmap[hr]==f_regmap[hr])
8159 regs[j].regmap_entry[hr]=f_regmap[hr];
8160 break;
8161 }
8162 if(j==i) break;
8163 if(regs[j].regmap[hr]>=0)
8164 break;
8165 if(get_reg(regs[j].regmap,f_regmap[hr])>=0) {
8166 //printf("no-match due to different register\n");
8167 break;
8168 }
fe807a8a 8169 if (dops[j].is_ujump)
e1190b87 8170 {
8171 // Stop on unconditional branch
8172 break;
8173 }
cf95b4f0 8174 if(dops[j].itype==CJUMP||dops[j].itype==SJUMP)
e1190b87 8175 {
cf95b4f0 8176 if(dops[j].ooo) {
277718fa 8177 if(count_free_regs(regs[j].regmap)<=cinfo[j+1].min_free_regs)
e1190b87 8178 break;
8179 }else{
277718fa 8180 if(count_free_regs(branch_regs[j].regmap)<=cinfo[j+1].min_free_regs)
e1190b87 8181 break;
8182 }
8183 if(get_reg(branch_regs[j].regmap,f_regmap[hr])>=0) {
8184 //printf("no-match due to different register (branch)\n");
57871462 8185 break;
8186 }
8187 }
277718fa 8188 if(count_free_regs(regs[j].regmap)<=cinfo[j].min_free_regs) {
e1190b87 8189 //printf("No free regs for store %x\n",start+j*4);
8190 break;
8191 }
ad49de89 8192 assert(f_regmap[hr]<64);
57871462 8193 }
8194 }
8195 }
8196 }
8197 }
8198 }else{
198df76f 8199 // Non branch or undetermined branch target
57871462 8200 for(hr=0;hr<HOST_REGS;hr++)
8201 {
8202 if(hr!=EXCLUDE_REG) {
7c3a5182 8203 if(regs[i].regmap[hr]>=0) {
b372a952 8204 if(f_regmap[hr]!=regs[i].regmap[hr]) {
8205 // dealloc old register
8206 int n;
8207 for(n=0;n<HOST_REGS;n++)
8208 {
8209 if(f_regmap[n]==regs[i].regmap[hr]) {f_regmap[n]=-1;}
8210 }
4149788d 8211 // and alloc new one
8212 f_regmap[hr]=regs[i].regmap[hr];
8213 }
8214 }
8215 }
8216 }
8217 // Try to restore cycle count at branch targets
8218 if(dops[i].bt) {
8219 for(j=i;j<slen-1;j++) {
8220 if(regs[j].regmap[HOST_CCREG]!=-1) break;
277718fa 8221 if(count_free_regs(regs[j].regmap)<=cinfo[j].min_free_regs) {
4149788d 8222 //printf("no free regs for store %x\n",start+j*4);
8223 break;
8224 }
8225 }
8226 if(regs[j].regmap[HOST_CCREG]==CCREG) {
8227 int k=i;
8228 //printf("Extend CC, %x -> %x\n",start+k*4,start+j*4);
8229 while(k<j) {
8230 regs[k].regmap_entry[HOST_CCREG]=CCREG;
8231 regs[k].regmap[HOST_CCREG]=CCREG;
8232 regmap_pre[k+1][HOST_CCREG]=CCREG;
8233 regs[k+1].wasdirty|=1<<HOST_CCREG;
8234 regs[k].dirty|=1<<HOST_CCREG;
8235 regs[k].wasconst&=~(1<<HOST_CCREG);
8236 regs[k].isconst&=~(1<<HOST_CCREG);
8237 k++;
8238 }
8239 regs[j].regmap_entry[HOST_CCREG]=CCREG;
8240 }
8241 // Work backwards from the branch target
8242 if(j>i&&f_regmap[HOST_CCREG]==CCREG)
8243 {
8244 //printf("Extend backwards\n");
8245 int k;
8246 k=i;
8247 while(regs[k-1].regmap[HOST_CCREG]==-1) {
277718fa 8248 if(count_free_regs(regs[k-1].regmap)<=cinfo[k-1].min_free_regs) {
4149788d 8249 //printf("no free regs for store %x\n",start+(k-1)*4);
8250 break;
8251 }
8252 k--;
8253 }
8254 if(regs[k-1].regmap[HOST_CCREG]==CCREG) {
8255 //printf("Extend CC, %x ->\n",start+k*4);
8256 while(k<=i) {
8257 regs[k].regmap_entry[HOST_CCREG]=CCREG;
8258 regs[k].regmap[HOST_CCREG]=CCREG;
8259 regmap_pre[k+1][HOST_CCREG]=CCREG;
8260 regs[k+1].wasdirty|=1<<HOST_CCREG;
8261 regs[k].dirty|=1<<HOST_CCREG;
8262 regs[k].wasconst&=~(1<<HOST_CCREG);
8263 regs[k].isconst&=~(1<<HOST_CCREG);
8264 k++;
8265 }
8266 }
8267 else {
8268 //printf("Fail Extend CC, %x ->\n",start+k*4);
8269 }
8270 }
8271 }
a5cd72d0 8272 if(dops[i].itype!=STORE&&dops[i].itype!=STORELR&&dops[i].itype!=SHIFT&&
4149788d 8273 dops[i].itype!=NOP&&dops[i].itype!=MOV&&dops[i].itype!=ALU&&dops[i].itype!=SHIFTIMM&&
a5cd72d0 8274 dops[i].itype!=IMM16&&dops[i].itype!=LOAD)
4149788d 8275 {
8276 memcpy(f_regmap,regs[i].regmap,sizeof(f_regmap));
8277 }
8278 }
8279 }
8280}
8281
8282// This allocates registers (if possible) one instruction prior
8283// to use, which can avoid a load-use penalty on certain CPUs.
8284static noinline void pass5b_preallocate2(void)
8285{
8286 int i, hr;
8287 for(i=0;i<slen-1;i++)
8288 {
8289 if (!i || !dops[i-1].is_jump)
8290 {
8291 if(!dops[i+1].bt)
8292 {
277718fa 8293 int j, can_steal = 1;
8294 for (j = i; j < i + 2; j++) {
8295 int free_regs = 0;
8296 if (cinfo[j].min_free_regs == 0)
8297 continue;
8298 for (hr = 0; hr < HOST_REGS; hr++)
8299 if (hr != EXCLUDE_REG && regs[j].regmap[hr] < 0)
8300 free_regs++;
8301 if (free_regs <= cinfo[j].min_free_regs) {
8302 can_steal = 0;
8303 break;
8304 }
8305 }
8306 if (!can_steal)
8307 continue;
4149788d 8308 if(dops[i].itype==ALU||dops[i].itype==MOV||dops[i].itype==LOAD||dops[i].itype==SHIFTIMM||dops[i].itype==IMM16
a5cd72d0 8309 ||(dops[i].itype==COP2&&dops[i].opcode2<3))
4149788d 8310 {
8311 if(dops[i+1].rs1) {
8312 if((hr=get_reg(regs[i+1].regmap,dops[i+1].rs1))>=0)
8313 {
8314 if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
8315 {
8316 regs[i].regmap[hr]=regs[i+1].regmap[hr];
8317 regmap_pre[i+1][hr]=regs[i+1].regmap[hr];
8318 regs[i+1].regmap_entry[hr]=regs[i+1].regmap[hr];
8319 regs[i].isconst&=~(1<<hr);
8320 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
8321 constmap[i][hr]=constmap[i+1][hr];
8322 regs[i+1].wasdirty&=~(1<<hr);
8323 regs[i].dirty&=~(1<<hr);
8324 }
8325 }
8326 }
8327 if(dops[i+1].rs2) {
8328 if((hr=get_reg(regs[i+1].regmap,dops[i+1].rs2))>=0)
8329 {
8330 if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
8331 {
8332 regs[i].regmap[hr]=regs[i+1].regmap[hr];
8333 regmap_pre[i+1][hr]=regs[i+1].regmap[hr];
8334 regs[i+1].regmap_entry[hr]=regs[i+1].regmap[hr];
8335 regs[i].isconst&=~(1<<hr);
8336 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
8337 constmap[i][hr]=constmap[i+1][hr];
8338 regs[i+1].wasdirty&=~(1<<hr);
8339 regs[i].dirty&=~(1<<hr);
8340 }
8341 }
8342 }
8343 // Preload target address for load instruction (non-constant)
8344 if(dops[i+1].itype==LOAD&&dops[i+1].rs1&&get_reg(regs[i+1].regmap,dops[i+1].rs1)<0) {
a5cd72d0 8345 if((hr=get_reg_w(regs[i+1].regmap, dops[i+1].rt1))>=0)
4149788d 8346 {
8347 if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
8348 {
8349 regs[i].regmap[hr]=dops[i+1].rs1;
8350 regmap_pre[i+1][hr]=dops[i+1].rs1;
8351 regs[i+1].regmap_entry[hr]=dops[i+1].rs1;
8352 regs[i].isconst&=~(1<<hr);
8353 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
8354 constmap[i][hr]=constmap[i+1][hr];
8355 regs[i+1].wasdirty&=~(1<<hr);
8356 regs[i].dirty&=~(1<<hr);
8357 }
8358 }
8359 }
8360 // Load source into target register
8361 if(dops[i+1].use_lt1&&get_reg(regs[i+1].regmap,dops[i+1].rs1)<0) {
a5cd72d0 8362 if((hr=get_reg_w(regs[i+1].regmap, dops[i+1].rt1))>=0)
4149788d 8363 {
8364 if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
8365 {
8366 regs[i].regmap[hr]=dops[i+1].rs1;
8367 regmap_pre[i+1][hr]=dops[i+1].rs1;
8368 regs[i+1].regmap_entry[hr]=dops[i+1].rs1;
8369 regs[i].isconst&=~(1<<hr);
8370 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
8371 constmap[i][hr]=constmap[i+1][hr];
8372 regs[i+1].wasdirty&=~(1<<hr);
8373 regs[i].dirty&=~(1<<hr);
8374 }
8375 }
8376 }
8377 // Address for store instruction (non-constant)
277718fa 8378 if (dops[i+1].is_store) { // SB/SH/SW/SWC2
4149788d 8379 if(get_reg(regs[i+1].regmap,dops[i+1].rs1)<0) {
8380 hr=get_reg2(regs[i].regmap,regs[i+1].regmap,-1);
8381 if(hr<0) hr=get_reg_temp(regs[i+1].regmap);
8382 else {
8383 regs[i+1].regmap[hr]=AGEN1+((i+1)&1);
8384 regs[i+1].isconst&=~(1<<hr);
277718fa 8385 regs[i+1].dirty&=~(1<<hr);
8386 regs[i+2].wasdirty&=~(1<<hr);
4149788d 8387 }
8388 assert(hr>=0);
f0b91b78 8389 #if 0 // what is this for? double allocs $0 in ps1_rom.bin
4149788d 8390 if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
8391 {
8392 regs[i].regmap[hr]=dops[i+1].rs1;
8393 regmap_pre[i+1][hr]=dops[i+1].rs1;
8394 regs[i+1].regmap_entry[hr]=dops[i+1].rs1;
8395 regs[i].isconst&=~(1<<hr);
8396 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
8397 constmap[i][hr]=constmap[i+1][hr];
8398 regs[i+1].wasdirty&=~(1<<hr);
8399 regs[i].dirty&=~(1<<hr);
8400 }
f0b91b78 8401 #endif
4149788d 8402 }
8403 }
277718fa 8404 if (dops[i+1].itype == LOADLR || dops[i+1].opcode == 0x32) { // LWC2
4149788d 8405 if(get_reg(regs[i+1].regmap,dops[i+1].rs1)<0) {
8406 int nr;
8407 hr=get_reg(regs[i+1].regmap,FTEMP);
8408 assert(hr>=0);
8409 if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
8410 {
8411 regs[i].regmap[hr]=dops[i+1].rs1;
8412 regmap_pre[i+1][hr]=dops[i+1].rs1;
8413 regs[i+1].regmap_entry[hr]=dops[i+1].rs1;
8414 regs[i].isconst&=~(1<<hr);
8415 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
8416 constmap[i][hr]=constmap[i+1][hr];
8417 regs[i+1].wasdirty&=~(1<<hr);
8418 regs[i].dirty&=~(1<<hr);
8419 }
8420 else if((nr=get_reg2(regs[i].regmap,regs[i+1].regmap,-1))>=0)
8421 {
8422 // move it to another register
8423 regs[i+1].regmap[hr]=-1;
8424 regmap_pre[i+2][hr]=-1;
8425 regs[i+1].regmap[nr]=FTEMP;
8426 regmap_pre[i+2][nr]=FTEMP;
8427 regs[i].regmap[nr]=dops[i+1].rs1;
8428 regmap_pre[i+1][nr]=dops[i+1].rs1;
8429 regs[i+1].regmap_entry[nr]=dops[i+1].rs1;
8430 regs[i].isconst&=~(1<<nr);
8431 regs[i+1].isconst&=~(1<<nr);
8432 regs[i].dirty&=~(1<<nr);
8433 regs[i+1].wasdirty&=~(1<<nr);
8434 regs[i+1].dirty&=~(1<<nr);
8435 regs[i+2].wasdirty&=~(1<<nr);
8436 }
8437 }
8438 }
a5cd72d0 8439 if(dops[i+1].itype==LOAD||dops[i+1].itype==LOADLR||dops[i+1].itype==STORE||dops[i+1].itype==STORELR/*||dops[i+1].itype==C2LS*/) {
4149788d 8440 hr = -1;
8441 if(dops[i+1].itype==LOAD)
a5cd72d0 8442 hr=get_reg_w(regs[i+1].regmap, dops[i+1].rt1);
277718fa 8443 if (dops[i+1].itype == LOADLR || dops[i+1].opcode == 0x32) // LWC2
4149788d 8444 hr=get_reg(regs[i+1].regmap,FTEMP);
277718fa 8445 if (dops[i+1].is_store) {
4149788d 8446 hr=get_reg(regs[i+1].regmap,AGEN1+((i+1)&1));
8447 if(hr<0) hr=get_reg_temp(regs[i+1].regmap);
8448 }
8449 if(hr>=0&&regs[i].regmap[hr]<0) {
8450 int rs=get_reg(regs[i+1].regmap,dops[i+1].rs1);
8451 if(rs>=0&&((regs[i+1].wasconst>>rs)&1)) {
8452 regs[i].regmap[hr]=AGEN1+((i+1)&1);
8453 regmap_pre[i+1][hr]=AGEN1+((i+1)&1);
8454 regs[i+1].regmap_entry[hr]=AGEN1+((i+1)&1);
8455 regs[i].isconst&=~(1<<hr);
8456 regs[i+1].wasdirty&=~(1<<hr);
8457 regs[i].dirty&=~(1<<hr);
8458 }
b372a952 8459 }
8460 }
57871462 8461 }
8462 }
4149788d 8463 }
8464 }
8465}
8466
8467// Write back dirty registers as soon as we will no longer modify them,
8468// so that we don't end up with lots of writes at the branches.
8469static noinline void pass6_clean_registers(int istart, int iend, int wr)
8470{
53358c1d 8471 static u_int wont_dirty[MAXBLOCK];
8472 static u_int will_dirty[MAXBLOCK];
4149788d 8473 int i;
8474 int r;
8475 u_int will_dirty_i,will_dirty_next,temp_will_dirty;
8476 u_int wont_dirty_i,wont_dirty_next,temp_wont_dirty;
8477 if(iend==slen-1) {
8478 will_dirty_i=will_dirty_next=0;
8479 wont_dirty_i=wont_dirty_next=0;
8480 }else{
8481 will_dirty_i=will_dirty_next=will_dirty[iend+1];
8482 wont_dirty_i=wont_dirty_next=wont_dirty[iend+1];
8483 }
8484 for (i=iend;i>=istart;i--)
8485 {
8486 signed char rregmap_i[RRMAP_SIZE];
8487 u_int hr_candirty = 0;
8488 assert(HOST_REGS < 32);
8489 make_rregs(regs[i].regmap, rregmap_i, &hr_candirty);
8490 __builtin_prefetch(regs[i-1].regmap);
8491 if(dops[i].is_jump)
8492 {
8493 signed char branch_rregmap_i[RRMAP_SIZE];
8494 u_int branch_hr_candirty = 0;
8495 make_rregs(branch_regs[i].regmap, branch_rregmap_i, &branch_hr_candirty);
277718fa 8496 if(cinfo[i].ba<start || cinfo[i].ba>=(start+slen*4))
4149788d 8497 {
8498 // Branch out of this block, flush all regs
8499 will_dirty_i = 0;
8500 will_dirty_i |= 1u << (get_rreg(branch_rregmap_i, dops[i].rt1) & 31);
8501 will_dirty_i |= 1u << (get_rreg(branch_rregmap_i, dops[i].rt2) & 31);
8502 will_dirty_i |= 1u << (get_rreg(branch_rregmap_i, dops[i+1].rt1) & 31);
8503 will_dirty_i |= 1u << (get_rreg(branch_rregmap_i, dops[i+1].rt2) & 31);
8504 will_dirty_i |= 1u << (get_rreg(branch_rregmap_i, CCREG) & 31);
8505 will_dirty_i &= branch_hr_candirty;
8506 if (dops[i].is_ujump)
8507 {
8508 // Unconditional branch
8509 wont_dirty_i = 0;
8510 // Merge in delay slot (will dirty)
8511 will_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i].rt1) & 31);
8512 will_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i].rt2) & 31);
8513 will_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i+1].rt1) & 31);
8514 will_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i+1].rt2) & 31);
8515 will_dirty_i |= 1u << (get_rreg(rregmap_i, CCREG) & 31);
8516 will_dirty_i &= hr_candirty;
57871462 8517 }
4149788d 8518 else
8519 {
8520 // Conditional branch
8521 wont_dirty_i = wont_dirty_next;
8522 // Merge in delay slot (will dirty)
8523 // (the original code had no explanation why these 2 are commented out)
8524 //will_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i].rt1) & 31);
8525 //will_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i].rt2) & 31);
8526 will_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i+1].rt1) & 31);
8527 will_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i+1].rt2) & 31);
8528 will_dirty_i |= 1u << (get_rreg(rregmap_i, CCREG) & 31);
8529 will_dirty_i &= hr_candirty;
8530 }
8531 // Merge in delay slot (wont dirty)
8532 wont_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i].rt1) & 31);
8533 wont_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i].rt2) & 31);
8534 wont_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i+1].rt1) & 31);
8535 wont_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i+1].rt2) & 31);
8536 wont_dirty_i |= 1u << (get_rreg(rregmap_i, CCREG) & 31);
8537 wont_dirty_i |= 1u << (get_rreg(branch_rregmap_i, dops[i].rt1) & 31);
8538 wont_dirty_i |= 1u << (get_rreg(branch_rregmap_i, dops[i].rt2) & 31);
8539 wont_dirty_i |= 1u << (get_rreg(branch_rregmap_i, dops[i+1].rt1) & 31);
8540 wont_dirty_i |= 1u << (get_rreg(branch_rregmap_i, dops[i+1].rt2) & 31);
8541 wont_dirty_i |= 1u << (get_rreg(branch_rregmap_i, CCREG) & 31);
8542 wont_dirty_i &= ~(1u << 31);
8543 if(wr) {
8544 #ifndef DESTRUCTIVE_WRITEBACK
8545 branch_regs[i].dirty&=wont_dirty_i;
8546 #endif
8547 branch_regs[i].dirty|=will_dirty_i;
8548 }
8549 }
8550 else
8551 {
8552 // Internal branch
277718fa 8553 if(cinfo[i].ba<=start+i*4) {
4149788d 8554 // Backward branch
8555 if (dops[i].is_ujump)
8556 {
8557 // Unconditional branch
8558 temp_will_dirty=0;
8559 temp_wont_dirty=0;
8560 // Merge in delay slot (will dirty)
8561 temp_will_dirty |= 1u << (get_rreg(branch_rregmap_i, dops[i].rt1) & 31);
8562 temp_will_dirty |= 1u << (get_rreg(branch_rregmap_i, dops[i].rt2) & 31);
8563 temp_will_dirty |= 1u << (get_rreg(branch_rregmap_i, dops[i+1].rt1) & 31);
8564 temp_will_dirty |= 1u << (get_rreg(branch_rregmap_i, dops[i+1].rt2) & 31);
8565 temp_will_dirty |= 1u << (get_rreg(branch_rregmap_i, CCREG) & 31);
8566 temp_will_dirty &= branch_hr_candirty;
8567 temp_will_dirty |= 1u << (get_rreg(rregmap_i, dops[i].rt1) & 31);
8568 temp_will_dirty |= 1u << (get_rreg(rregmap_i, dops[i].rt2) & 31);
8569 temp_will_dirty |= 1u << (get_rreg(rregmap_i, dops[i+1].rt1) & 31);
8570 temp_will_dirty |= 1u << (get_rreg(rregmap_i, dops[i+1].rt2) & 31);
8571 temp_will_dirty |= 1u << (get_rreg(rregmap_i, CCREG) & 31);
8572 temp_will_dirty &= hr_candirty;
8573 } else {
8574 // Conditional branch (not taken case)
8575 temp_will_dirty=will_dirty_next;
8576 temp_wont_dirty=wont_dirty_next;
8577 // Merge in delay slot (will dirty)
8578 temp_will_dirty |= 1u << (get_rreg(branch_rregmap_i, dops[i].rt1) & 31);
8579 temp_will_dirty |= 1u << (get_rreg(branch_rregmap_i, dops[i].rt2) & 31);
8580 temp_will_dirty |= 1u << (get_rreg(branch_rregmap_i, dops[i+1].rt1) & 31);
8581 temp_will_dirty |= 1u << (get_rreg(branch_rregmap_i, dops[i+1].rt2) & 31);
8582 temp_will_dirty |= 1u << (get_rreg(branch_rregmap_i, CCREG) & 31);
8583 temp_will_dirty &= branch_hr_candirty;
8584 //temp_will_dirty |= 1u << (get_rreg(rregmap_i, dops[i].rt1) & 31);
8585 //temp_will_dirty |= 1u << (get_rreg(rregmap_i, dops[i].rt2) & 31);
8586 temp_will_dirty |= 1u << (get_rreg(rregmap_i, dops[i+1].rt1) & 31);
8587 temp_will_dirty |= 1u << (get_rreg(rregmap_i, dops[i+1].rt2) & 31);
8588 temp_will_dirty |= 1u << (get_rreg(rregmap_i, CCREG) & 31);
8589 temp_will_dirty &= hr_candirty;
8590 }
8591 // Merge in delay slot (wont dirty)
8592 temp_wont_dirty |= 1u << (get_rreg(rregmap_i, dops[i].rt1) & 31);
8593 temp_wont_dirty |= 1u << (get_rreg(rregmap_i, dops[i].rt2) & 31);
8594 temp_wont_dirty |= 1u << (get_rreg(rregmap_i, dops[i+1].rt1) & 31);
8595 temp_wont_dirty |= 1u << (get_rreg(rregmap_i, dops[i+1].rt2) & 31);
8596 temp_wont_dirty |= 1u << (get_rreg(rregmap_i, CCREG) & 31);
8597 temp_wont_dirty |= 1u << (get_rreg(branch_rregmap_i, dops[i].rt1) & 31);
8598 temp_wont_dirty |= 1u << (get_rreg(branch_rregmap_i, dops[i].rt2) & 31);
8599 temp_wont_dirty |= 1u << (get_rreg(branch_rregmap_i, dops[i+1].rt1) & 31);
8600 temp_wont_dirty |= 1u << (get_rreg(branch_rregmap_i, dops[i+1].rt2) & 31);
8601 temp_wont_dirty |= 1u << (get_rreg(branch_rregmap_i, CCREG) & 31);
8602 temp_wont_dirty &= ~(1u << 31);
8603 // Deal with changed mappings
8604 if(i<iend) {
8605 for(r=0;r<HOST_REGS;r++) {
8606 if(r!=EXCLUDE_REG) {
8607 if(regs[i].regmap[r]!=regmap_pre[i][r]) {
8608 temp_will_dirty&=~(1<<r);
8609 temp_wont_dirty&=~(1<<r);
8610 if(regmap_pre[i][r]>0 && regmap_pre[i][r]<34) {
8611 temp_will_dirty|=((unneeded_reg[i]>>regmap_pre[i][r])&1)<<r;
8612 temp_wont_dirty|=((unneeded_reg[i]>>regmap_pre[i][r])&1)<<r;
8613 } else {
8614 temp_will_dirty|=1<<r;
8615 temp_wont_dirty|=1<<r;
8616 }
8617 }
8618 }
8619 }
8620 }
8621 if(wr) {
8622 will_dirty[i]=temp_will_dirty;
8623 wont_dirty[i]=temp_wont_dirty;
277718fa 8624 pass6_clean_registers((cinfo[i].ba-start)>>2,i-1,0);
4149788d 8625 }else{
8626 // Limit recursion. It can take an excessive amount
8627 // of time if there are a lot of nested loops.
277718fa 8628 will_dirty[(cinfo[i].ba-start)>>2]=0;
8629 wont_dirty[(cinfo[i].ba-start)>>2]=-1;
57871462 8630 }
57871462 8631 }
4149788d 8632 /*else*/ if(1)
57871462 8633 {
4149788d 8634 if (dops[i].is_ujump)
8635 {
8636 // Unconditional branch
8637 will_dirty_i=0;
8638 wont_dirty_i=0;
277718fa 8639 //if(cinfo[i].ba>start+i*4) { // Disable recursion (for debugging)
4149788d 8640 for(r=0;r<HOST_REGS;r++) {
8641 if(r!=EXCLUDE_REG) {
277718fa 8642 if(branch_regs[i].regmap[r]==regs[(cinfo[i].ba-start)>>2].regmap_entry[r]) {
8643 will_dirty_i|=will_dirty[(cinfo[i].ba-start)>>2]&(1<<r);
8644 wont_dirty_i|=wont_dirty[(cinfo[i].ba-start)>>2]&(1<<r);
4149788d 8645 }
8646 if(branch_regs[i].regmap[r]>=0) {
277718fa 8647 will_dirty_i|=((unneeded_reg[(cinfo[i].ba-start)>>2]>>branch_regs[i].regmap[r])&1)<<r;
8648 wont_dirty_i|=((unneeded_reg[(cinfo[i].ba-start)>>2]>>branch_regs[i].regmap[r])&1)<<r;
4149788d 8649 }
8650 }
57871462 8651 }
4149788d 8652 //}
8653 // Merge in delay slot
8654 will_dirty_i |= 1u << (get_rreg(branch_rregmap_i, dops[i].rt1) & 31);
8655 will_dirty_i |= 1u << (get_rreg(branch_rregmap_i, dops[i].rt2) & 31);
8656 will_dirty_i |= 1u << (get_rreg(branch_rregmap_i, dops[i+1].rt1) & 31);
8657 will_dirty_i |= 1u << (get_rreg(branch_rregmap_i, dops[i+1].rt2) & 31);
8658 will_dirty_i |= 1u << (get_rreg(branch_rregmap_i, CCREG) & 31);
8659 will_dirty_i &= branch_hr_candirty;
8660 will_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i].rt1) & 31);
8661 will_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i].rt2) & 31);
8662 will_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i+1].rt1) & 31);
8663 will_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i+1].rt2) & 31);
8664 will_dirty_i |= 1u << (get_rreg(rregmap_i, CCREG) & 31);
8665 will_dirty_i &= hr_candirty;
8666 } else {
8667 // Conditional branch
8668 will_dirty_i=will_dirty_next;
8669 wont_dirty_i=wont_dirty_next;
277718fa 8670 //if(cinfo[i].ba>start+i*4) // Disable recursion (for debugging)
4149788d 8671 for(r=0;r<HOST_REGS;r++) {
8672 if(r!=EXCLUDE_REG) {
8673 signed char target_reg=branch_regs[i].regmap[r];
277718fa 8674 if(target_reg==regs[(cinfo[i].ba-start)>>2].regmap_entry[r]) {
8675 will_dirty_i&=will_dirty[(cinfo[i].ba-start)>>2]&(1<<r);
8676 wont_dirty_i|=wont_dirty[(cinfo[i].ba-start)>>2]&(1<<r);
4149788d 8677 }
8678 else if(target_reg>=0) {
277718fa 8679 will_dirty_i&=((unneeded_reg[(cinfo[i].ba-start)>>2]>>target_reg)&1)<<r;
8680 wont_dirty_i|=((unneeded_reg[(cinfo[i].ba-start)>>2]>>target_reg)&1)<<r;
4149788d 8681 }
8682 }
57871462 8683 }
4149788d 8684 // Merge in delay slot
8685 will_dirty_i |= 1u << (get_rreg(branch_rregmap_i, dops[i].rt1) & 31);
8686 will_dirty_i |= 1u << (get_rreg(branch_rregmap_i, dops[i].rt2) & 31);
8687 will_dirty_i |= 1u << (get_rreg(branch_rregmap_i, dops[i+1].rt1) & 31);
8688 will_dirty_i |= 1u << (get_rreg(branch_rregmap_i, dops[i+1].rt2) & 31);
8689 will_dirty_i |= 1u << (get_rreg(branch_rregmap_i, CCREG) & 31);
8690 will_dirty_i &= branch_hr_candirty;
8691 //will_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i].rt1) & 31);
8692 //will_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i].rt2) & 31);
8693 will_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i+1].rt1) & 31);
8694 will_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i+1].rt2) & 31);
8695 will_dirty_i |= 1u << (get_rreg(rregmap_i, CCREG) & 31);
8696 will_dirty_i &= hr_candirty;
57871462 8697 }
4149788d 8698 // Merge in delay slot (won't dirty)
8699 wont_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i].rt1) & 31);
8700 wont_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i].rt2) & 31);
8701 wont_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i+1].rt1) & 31);
8702 wont_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i+1].rt2) & 31);
8703 wont_dirty_i |= 1u << (get_rreg(rregmap_i, CCREG) & 31);
8704 wont_dirty_i |= 1u << (get_rreg(branch_rregmap_i, dops[i].rt1) & 31);
8705 wont_dirty_i |= 1u << (get_rreg(branch_rregmap_i, dops[i].rt2) & 31);
8706 wont_dirty_i |= 1u << (get_rreg(branch_rregmap_i, dops[i+1].rt1) & 31);
8707 wont_dirty_i |= 1u << (get_rreg(branch_rregmap_i, dops[i+1].rt2) & 31);
8708 wont_dirty_i |= 1u << (get_rreg(branch_rregmap_i, CCREG) & 31);
8709 wont_dirty_i &= ~(1u << 31);
8710 if(wr) {
8711 #ifndef DESTRUCTIVE_WRITEBACK
8712 branch_regs[i].dirty&=wont_dirty_i;
8713 #endif
8714 branch_regs[i].dirty|=will_dirty_i;
57871462 8715 }
8716 }
8717 }
57871462 8718 }
277718fa 8719 else if (dops[i].is_exception)
4149788d 8720 {
277718fa 8721 // SYSCALL instruction, etc
4149788d 8722 will_dirty_i=0;
8723 wont_dirty_i=0;
8724 }
8725 will_dirty_next=will_dirty_i;
8726 wont_dirty_next=wont_dirty_i;
8727 will_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i].rt1) & 31);
8728 will_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i].rt2) & 31);
8729 will_dirty_i |= 1u << (get_rreg(rregmap_i, CCREG) & 31);
8730 will_dirty_i &= hr_candirty;
8731 wont_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i].rt1) & 31);
8732 wont_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i].rt2) & 31);
8733 wont_dirty_i |= 1u << (get_rreg(rregmap_i, CCREG) & 31);
8734 wont_dirty_i &= ~(1u << 31);
8735 if (i > istart && !dops[i].is_jump) {
8736 // Don't store a register immediately after writing it,
8737 // may prevent dual-issue.
8738 wont_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i-1].rt1) & 31);
8739 wont_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i-1].rt2) & 31);
8740 }
8741 // Save it
8742 will_dirty[i]=will_dirty_i;
8743 wont_dirty[i]=wont_dirty_i;
8744 // Mark registers that won't be dirtied as not dirty
8745 if(wr) {
8746 regs[i].dirty|=will_dirty_i;
8747 #ifndef DESTRUCTIVE_WRITEBACK
8748 regs[i].dirty&=wont_dirty_i;
8749 if(dops[i].is_jump)
57871462 8750 {
4149788d 8751 if (i < iend-1 && !dops[i].is_ujump) {
8752 for(r=0;r<HOST_REGS;r++) {
8753 if(r!=EXCLUDE_REG) {
8754 if(regs[i].regmap[r]==regmap_pre[i+2][r]) {
8755 regs[i+2].wasdirty&=wont_dirty_i|~(1<<r);
8756 }else {/*printf("i: %x (%d) mismatch(+2): %d\n",start+i*4,i,r);assert(!((wont_dirty_i>>r)&1));*/}
57871462 8757 }
8758 }
8759 }
4149788d 8760 }
8761 else
8762 {
8763 if(i<iend) {
8764 for(r=0;r<HOST_REGS;r++) {
8765 if(r!=EXCLUDE_REG) {
8766 if(regs[i].regmap[r]==regmap_pre[i+1][r]) {
8767 regs[i+1].wasdirty&=wont_dirty_i|~(1<<r);
8768 }else {/*printf("i: %x (%d) mismatch(+1): %d\n",start+i*4,i,r);assert(!((wont_dirty_i>>r)&1));*/}
57871462 8769 }
8770 }
8771 }
4149788d 8772 }
8773 #endif
8774 }
8775 // Deal with changed mappings
8776 temp_will_dirty=will_dirty_i;
8777 temp_wont_dirty=wont_dirty_i;
8778 for(r=0;r<HOST_REGS;r++) {
8779 if(r!=EXCLUDE_REG) {
8780 int nr;
8781 if(regs[i].regmap[r]==regmap_pre[i][r]) {
8782 if(wr) {
8783 #ifndef DESTRUCTIVE_WRITEBACK
8784 regs[i].wasdirty&=wont_dirty_i|~(1<<r);
8785 #endif
8786 regs[i].wasdirty|=will_dirty_i&(1<<r);
57871462 8787 }
4149788d 8788 }
8789 else if(regmap_pre[i][r]>=0&&(nr=get_rreg(rregmap_i,regmap_pre[i][r]))>=0) {
8790 // Register moved to a different register
8791 will_dirty_i&=~(1<<r);
8792 wont_dirty_i&=~(1<<r);
8793 will_dirty_i|=((temp_will_dirty>>nr)&1)<<r;
8794 wont_dirty_i|=((temp_wont_dirty>>nr)&1)<<r;
8795 if(wr) {
8796 #ifndef DESTRUCTIVE_WRITEBACK
8797 regs[i].wasdirty&=wont_dirty_i|~(1<<r);
8798 #endif
8799 regs[i].wasdirty|=will_dirty_i&(1<<r);
8800 }
8801 }
8802 else {
8803 will_dirty_i&=~(1<<r);
8804 wont_dirty_i&=~(1<<r);
8805 if(regmap_pre[i][r]>0 && regmap_pre[i][r]<34) {
8806 will_dirty_i|=((unneeded_reg[i]>>regmap_pre[i][r])&1)<<r;
8807 wont_dirty_i|=((unneeded_reg[i]>>regmap_pre[i][r])&1)<<r;
8808 } else {
8809 wont_dirty_i|=1<<r;
8810 /*printf("i: %x (%d) mismatch: %d\n",start+i*4,i,r);assert(!((will_dirty>>r)&1));*/
57871462 8811 }
8812 }
8813 }
8814 }
8815 }
4149788d 8816}
8817
8818static noinline void pass10_expire_blocks(void)
8819{
93c0345b 8820 u_int step = MAX_OUTPUT_BLOCK_SIZE / PAGE_COUNT / 2;
8821 // not sizeof(ndrc->translation_cache) due to vita hack
8822 u_int step_mask = ((1u << TARGET_SIZE_2) - 1u) & ~(step - 1u);
8823 u_int end = (out - ndrc->translation_cache + EXPIRITY_OFFSET) & step_mask;
8824 u_int base_shift = __builtin_ctz(MAX_OUTPUT_BLOCK_SIZE);
8825 int hit;
8826
8827 for (; expirep != end; expirep = ((expirep + step) & step_mask))
4149788d 8828 {
93c0345b 8829 u_int base_offs = expirep & ~(MAX_OUTPUT_BLOCK_SIZE - 1);
8830 u_int block_i = expirep / step & (PAGE_COUNT - 1);
8831 u_int phase = (expirep >> (base_shift - 1)) & 1u;
8832 if (!(expirep & (MAX_OUTPUT_BLOCK_SIZE / 2 - 1))) {
9b495f6e 8833 inv_debug("EXP: base_offs %x/%lx phase %u\n", base_offs,
8834 (long)(out - ndrc->translation_cache), phase);
93c0345b 8835 }
8836
8837 if (!phase) {
8838 hit = blocks_remove_matching_addrs(&blocks[block_i], base_offs, base_shift);
8839 if (hit) {
8840 do_clear_cache();
8841 #ifdef USE_MINI_HT
8842 memset(mini_ht, -1, sizeof(mini_ht));
8843 #endif
8844 }
4149788d 8845 }
93c0345b 8846 else
b7ad2f2c 8847 unlink_jumps_tc_range(jumps[block_i], base_offs, base_shift);
4149788d 8848 }
8849}
8850
104df9d3 8851static struct block_info *new_block_info(u_int start, u_int len,
8852 const void *source, const void *copy, u_char *beginning, u_short jump_in_count)
8853{
8854 struct block_info **b_pptr;
8855 struct block_info *block;
8856 u_int page = get_page(start);
8857
8858 block = malloc(sizeof(*block) + jump_in_count * sizeof(block->jump_in[0]));
8859 assert(block);
8860 assert(jump_in_count > 0);
8861 block->source = source;
8862 block->copy = copy;
8863 block->start = start;
8864 block->len = len;
8865 block->reg_sv_flags = 0;
8866 block->tc_offs = beginning - ndrc->translation_cache;
8867 //block->tc_len = out - beginning;
8868 block->is_dirty = 0;
3280e616 8869 block->inv_near_misses = 0;
104df9d3 8870 block->jump_in_cnt = jump_in_count;
8871
93c0345b 8872 // insert sorted by start mirror-unmasked vaddr
104df9d3 8873 for (b_pptr = &blocks[page]; ; b_pptr = &((*b_pptr)->next)) {
8874 if (*b_pptr == NULL || (*b_pptr)->start >= start) {
8875 block->next = *b_pptr;
8876 *b_pptr = block;
8877 break;
8878 }
8879 }
8880 stat_inc(stat_blocks);
8881 return block;
8882}
8883
8884static int new_recompile_block(u_int addr)
4149788d 8885{
8886 u_int pagelimit = 0;
8887 u_int state_rflags = 0;
8888 int i;
8889
8890 assem_debug("NOTCOMPILED: addr = %x -> %p\n", addr, out);
8891
a5cd72d0 8892 if (addr & 3) {
8893 if (addr != hack_addr) {
8894 SysPrintf("game crash @%08x, ra=%08x\n", addr, psxRegs.GPR.n.ra);
8895 hack_addr = addr;
8896 }
8897 return -1;
8898 }
8899
4149788d 8900 // this is just for speculation
8901 for (i = 1; i < 32; i++) {
8902 if ((psxRegs.GPR.r[i] & 0xffff0000) == 0x1f800000)
8903 state_rflags |= 1 << i;
8904 }
8905
a5cd72d0 8906 start = addr;
4149788d 8907 new_dynarec_did_compile=1;
8908 if (Config.HLE && start == 0x80001000) // hlecall
8909 {
104df9d3 8910 void *beginning = start_block();
4149788d 8911
4149788d 8912 emit_movimm(start,0);
8913 emit_writeword(0,&pcaddr);
8914 emit_far_jump(new_dyna_leave);
8915 literal_pool(0);
8916 end_block(beginning);
104df9d3 8917 struct block_info *block = new_block_info(start, 4, NULL, NULL, beginning, 1);
8918 block->jump_in[0].vaddr = start;
8919 block->jump_in[0].addr = beginning;
4149788d 8920 return 0;
8921 }
8922 else if (f1_hack && hack_addr == 0) {
8923 void *beginning = start_block();
4149788d 8924 emit_movimm(start, 0);
8925 emit_writeword(0, &hack_addr);
8926 emit_readword(&psxRegs.GPR.n.sp, 0);
8927 emit_readptr(&mem_rtab, 1);
8928 emit_shrimm(0, 12, 2);
8929 emit_readptr_dualindexedx_ptrlen(1, 2, 1);
8930 emit_addimm(0, 0x18, 0);
8931 emit_adds_ptr(1, 1, 1);
8932 emit_ldr_dualindexed(1, 0, 0);
8933 emit_writeword(0, &psxRegs.GPR.r[26]); // lw k0, 0x18(sp)
104df9d3 8934 emit_far_call(ndrc_get_addr_ht);
4149788d 8935 emit_jmpreg(0); // jr k0
8936 literal_pool(0);
8937 end_block(beginning);
8938
104df9d3 8939 struct block_info *block = new_block_info(start, 4, NULL, NULL, beginning, 1);
8940 block->jump_in[0].vaddr = start;
8941 block->jump_in[0].addr = beginning;
4149788d 8942 SysPrintf("F1 hack to %08x\n", start);
8943 return 0;
8944 }
8945
d5aeda23 8946 cycle_multiplier_active = Config.cycle_multiplier_override && Config.cycle_multiplier == CYCLE_MULT_DEFAULT
8947 ? Config.cycle_multiplier_override : Config.cycle_multiplier;
4149788d 8948
8949 source = get_source_start(start, &pagelimit);
8950 if (source == NULL) {
8951 if (addr != hack_addr) {
8952 SysPrintf("Compile at bogus memory address: %08x\n", addr);
8953 hack_addr = addr;
8954 }
8955 //abort();
8956 return -1;
8957 }
8958
8959 /* Pass 1: disassemble */
8960 /* Pass 2: register dependencies, branch targets */
8961 /* Pass 3: register allocation */
8962 /* Pass 4: branch dependencies */
8963 /* Pass 5: pre-alloc */
8964 /* Pass 6: optimize clean/dirty state */
8965 /* Pass 7: flag 32-bit registers */
8966 /* Pass 8: assembly */
8967 /* Pass 9: linker */
8968 /* Pass 10: garbage collection / free memory */
8969
8970 /* Pass 1 disassembly */
8971
8972 pass1_disassemble(pagelimit);
8973
8974 int clear_hack_addr = apply_hacks();
8975
8976 /* Pass 2 - Register dependencies and branch targets */
8977
8978 pass2_unneeded_regs(0,slen-1,0);
8979
f9e9616e 8980 pass2a_unneeded_other();
8981
4149788d 8982 /* Pass 3 - Register allocation */
8983
8984 pass3_register_alloc(addr);
8985
8986 /* Pass 4 - Cull unused host registers */
8987
8988 pass4_cull_unused_regs();
8989
8990 /* Pass 5 - Pre-allocate registers */
8991
8992 pass5a_preallocate1();
8993 pass5b_preallocate2();
9f51b4b9 8994
57871462 8995 /* Pass 6 - Optimize clean/dirty state */
4149788d 8996 pass6_clean_registers(0, slen-1, 1);
9f51b4b9 8997
33a1eda1 8998 /* Pass 7 */
04fd948a 8999 for (i=slen-1;i>=0;i--)
9000 {
cf95b4f0 9001 if(dops[i].itype==CJUMP||dops[i].itype==SJUMP)
04fd948a 9002 {
9003 // Conditional branch
9004 if((source[i]>>16)!=0x1000&&i<slen-2) {
9005 // Mark this address as a branch target since it may be called
9006 // upon return from interrupt
cf95b4f0 9007 dops[i+2].bt=1;
04fd948a 9008 }
9009 }
9010 }
57871462 9011
57871462 9012 /* Pass 8 - Assembly */
9013 linkcount=0;stubcount=0;
4149788d 9014 is_delayslot=0;
57871462 9015 u_int dirty_pre=0;
d148d265 9016 void *beginning=start_block();
df4dc2b1 9017 void *instr_addr0_override = NULL;
4bdc30ab 9018 int ds = 0;
9ad4d757 9019
9ad4d757 9020 if (start == 0x80030000) {
3968e69e 9021 // nasty hack for the fastbios thing
96186eba 9022 // override block entry to this code
df4dc2b1 9023 instr_addr0_override = out;
9ad4d757 9024 emit_movimm(start,0);
96186eba 9025 // abuse io address var as a flag that we
9026 // have already returned here once
643aeae3 9027 emit_readword(&address,1);
9028 emit_writeword(0,&pcaddr);
9029 emit_writeword(0,&address);
9ad4d757 9030 emit_cmp(0,1);
3968e69e 9031 #ifdef __aarch64__
9032 emit_jeq(out + 4*2);
2a014d73 9033 emit_far_jump(new_dyna_leave);
3968e69e 9034 #else
643aeae3 9035 emit_jne(new_dyna_leave);
3968e69e 9036 #endif
9ad4d757 9037 }
57871462 9038 for(i=0;i<slen;i++)
9039 {
9de8a0c3 9040 __builtin_prefetch(regs[i+1].regmap);
670c0f22 9041 check_regmap(regmap_pre[i]);
9042 check_regmap(regs[i].regmap_entry);
9043 check_regmap(regs[i].regmap);
57871462 9044 //if(ds) printf("ds: ");
4600ba03 9045 disassemble_inst(i);
57871462 9046 if(ds) {
9047 ds=0; // Skip delay slot
cf95b4f0 9048 if(dops[i].bt) assem_debug("OOPS - branch into delay slot\n");
df4dc2b1 9049 instr_addr[i] = NULL;
57871462 9050 } else {
ffb0b9e0 9051 speculate_register_values(i);
57871462 9052 #ifndef DESTRUCTIVE_WRITEBACK
fe807a8a 9053 if (i < 2 || !dops[i-2].is_ujump)
57871462 9054 {
ad49de89 9055 wb_valid(regmap_pre[i],regs[i].regmap_entry,dirty_pre,regs[i].wasdirty,unneeded_reg[i]);
57871462 9056 }
fe807a8a 9057 if((dops[i].itype==CJUMP||dops[i].itype==SJUMP)) {
f776eb14 9058 dirty_pre=branch_regs[i].dirty;
9059 }else{
f776eb14 9060 dirty_pre=regs[i].dirty;
9061 }
57871462 9062 #endif
9063 // write back
fe807a8a 9064 if (i < 2 || !dops[i-2].is_ujump)
57871462 9065 {
ad49de89 9066 wb_invalidate(regmap_pre[i],regs[i].regmap_entry,regs[i].wasdirty,unneeded_reg[i]);
57871462 9067 loop_preload(regmap_pre[i],regs[i].regmap_entry);
9068 }
9069 // branch target entry point
df4dc2b1 9070 instr_addr[i] = out;
57871462 9071 assem_debug("<->\n");
277718fa 9072 drc_dbg_emit_do_cmp(i, cinfo[i].ccadj);
7f94b097 9073 if (clear_hack_addr) {
9074 emit_movimm(0, 0);
9075 emit_writeword(0, &hack_addr);
9076 clear_hack_addr = 0;
9077 }
dd114d7d 9078
57871462 9079 // load regs
9080 if(regs[i].regmap_entry[HOST_CCREG]==CCREG&&regs[i].regmap[HOST_CCREG]!=CCREG)
ad49de89 9081 wb_register(CCREG,regs[i].regmap_entry,regs[i].wasdirty);
cf95b4f0 9082 load_regs(regs[i].regmap_entry,regs[i].regmap,dops[i].rs1,dops[i].rs2);
57871462 9083 address_generation(i,&regs[i],regs[i].regmap_entry);
ad49de89 9084 load_consts(regmap_pre[i],regs[i].regmap,i);
fe807a8a 9085 if(dops[i].is_jump)
57871462 9086 {
9087 // Load the delay slot registers if necessary
cf95b4f0 9088 if(dops[i+1].rs1!=dops[i].rs1&&dops[i+1].rs1!=dops[i].rs2&&(dops[i+1].rs1!=dops[i].rt1||dops[i].rt1==0))
9089 load_regs(regs[i].regmap_entry,regs[i].regmap,dops[i+1].rs1,dops[i+1].rs1);
9090 if(dops[i+1].rs2!=dops[i+1].rs1&&dops[i+1].rs2!=dops[i].rs1&&dops[i+1].rs2!=dops[i].rs2&&(dops[i+1].rs2!=dops[i].rt1||dops[i].rt1==0))
9091 load_regs(regs[i].regmap_entry,regs[i].regmap,dops[i+1].rs2,dops[i+1].rs2);
37387d8b 9092 if (ram_offset && (dops[i+1].is_load || dops[i+1].is_store))
53358c1d 9093 load_reg(regs[i].regmap_entry,regs[i].regmap,ROREG);
37387d8b 9094 if (dops[i+1].is_store)
53358c1d 9095 load_reg(regs[i].regmap_entry,regs[i].regmap,INVCP);
57871462 9096 }
9097 else if(i+1<slen)
9098 {
9099 // Preload registers for following instruction
cf95b4f0 9100 if(dops[i+1].rs1!=dops[i].rs1&&dops[i+1].rs1!=dops[i].rs2)
9101 if(dops[i+1].rs1!=dops[i].rt1&&dops[i+1].rs1!=dops[i].rt2)
9102 load_regs(regs[i].regmap_entry,regs[i].regmap,dops[i+1].rs1,dops[i+1].rs1);
9103 if(dops[i+1].rs2!=dops[i+1].rs1&&dops[i+1].rs2!=dops[i].rs1&&dops[i+1].rs2!=dops[i].rs2)
9104 if(dops[i+1].rs2!=dops[i].rt1&&dops[i+1].rs2!=dops[i].rt2)
9105 load_regs(regs[i].regmap_entry,regs[i].regmap,dops[i+1].rs2,dops[i+1].rs2);
57871462 9106 }
9107 // TODO: if(is_ooo(i)) address_generation(i+1);
9a3ccfeb 9108 if (!dops[i].is_jump || dops[i].itype == CJUMP)
53358c1d 9109 load_reg(regs[i].regmap_entry,regs[i].regmap,CCREG);
37387d8b 9110 if (ram_offset && (dops[i].is_load || dops[i].is_store))
53358c1d 9111 load_reg(regs[i].regmap_entry,regs[i].regmap,ROREG);
37387d8b 9112 if (dops[i].is_store)
53358c1d 9113 load_reg(regs[i].regmap_entry,regs[i].regmap,INVCP);
2330734f 9114
277718fa 9115 ds = assemble(i, &regs[i], cinfo[i].ccadj);
2330734f 9116
fe807a8a 9117 if (dops[i].is_ujump)
57871462 9118 literal_pool(1024);
9119 else
9120 literal_pool_jumpover(256);
9121 }
9122 }
3d680478 9123
9124 assert(slen > 0);
cf95b4f0 9125 if (slen > 0 && dops[slen-1].itype == INTCALL) {
3d680478 9126 // no ending needed for this block since INTCALL never returns
9127 }
57871462 9128 // If the block did not end with an unconditional branch,
9129 // add a jump to the next instruction.
3d680478 9130 else if (i > 1) {
4bdc30ab 9131 if (!dops[i-2].is_ujump) {
fe807a8a 9132 assert(!dops[i-1].is_jump);
57871462 9133 assert(i==slen);
cf95b4f0 9134 if(dops[i-2].itype!=CJUMP&&dops[i-2].itype!=SJUMP) {
ad49de89 9135 store_regs_bt(regs[i-1].regmap,regs[i-1].dirty,start+i*4);
57871462 9136 if(regs[i-1].regmap[HOST_CCREG]!=CCREG)
9137 emit_loadreg(CCREG,HOST_CCREG);
277718fa 9138 emit_addimm(HOST_CCREG, cinfo[i-1].ccadj + CLOCK_ADJUST(1), HOST_CCREG);
57871462 9139 }
fe807a8a 9140 else
57871462 9141 {
ad49de89 9142 store_regs_bt(branch_regs[i-2].regmap,branch_regs[i-2].dirty,start+i*4);
57871462 9143 assert(branch_regs[i-2].regmap[HOST_CCREG]==CCREG);
9144 }
643aeae3 9145 add_to_linker(out,start+i*4,0);
57871462 9146 emit_jmp(0);
9147 }
9148 }
9149 else
9150 {
9151 assert(i>0);
fe807a8a 9152 assert(!dops[i-1].is_jump);
ad49de89 9153 store_regs_bt(regs[i-1].regmap,regs[i-1].dirty,start+i*4);
57871462 9154 if(regs[i-1].regmap[HOST_CCREG]!=CCREG)
9155 emit_loadreg(CCREG,HOST_CCREG);
277718fa 9156 emit_addimm(HOST_CCREG, cinfo[i-1].ccadj + CLOCK_ADJUST(1), HOST_CCREG);
643aeae3 9157 add_to_linker(out,start+i*4,0);
57871462 9158 emit_jmp(0);
9159 }
9160
57871462 9161 // Stubs
a5cd72d0 9162 for(i = 0; i < stubcount; i++)
57871462 9163 {
b14b6a8f 9164 switch(stubs[i].type)
57871462 9165 {
9166 case LOADB_STUB:
9167 case LOADH_STUB:
9168 case LOADW_STUB:
57871462 9169 case LOADBU_STUB:
9170 case LOADHU_STUB:
9171 do_readstub(i);break;
9172 case STOREB_STUB:
9173 case STOREH_STUB:
9174 case STOREW_STUB:
57871462 9175 do_writestub(i);break;
9176 case CC_STUB:
9177 do_ccstub(i);break;
9178 case INVCODE_STUB:
9179 do_invstub(i);break;
57871462 9180 case STORELR_STUB:
9181 do_unalignedwritestub(i);break;
a5cd72d0 9182 case OVERFLOW_STUB:
9183 do_overflowstub(i); break;
277718fa 9184 case ALIGNMENT_STUB:
9185 do_alignmentstub(i); break;
a5cd72d0 9186 default:
9187 assert(0);
57871462 9188 }
9189 }
9190
9ad4d757 9191 if (instr_addr0_override)
9192 instr_addr[0] = instr_addr0_override;
9193
93c0345b 9194#if 0
9195 /* check for improper expiration */
9196 for (i = 0; i < ARRAY_SIZE(jumps); i++) {
9197 int j;
9198 if (!jumps[i])
9199 continue;
9200 for (j = 0; j < jumps[i]->count; j++)
9201 assert(jumps[i]->e[j].stub < beginning || (u_char *)jumps[i]->e[j].stub > out);
9202 }
9203#endif
9204
57871462 9205 /* Pass 9 - Linker */
9206 for(i=0;i<linkcount;i++)
9207 {
643aeae3 9208 assem_debug("%p -> %8x\n",link_addr[i].addr,link_addr[i].target);
57871462 9209 literal_pool(64);
104df9d3 9210 if (!link_addr[i].internal)
57871462 9211 {
643aeae3 9212 void *stub = out;
9213 void *addr = check_addr(link_addr[i].target);
9214 emit_extjump(link_addr[i].addr, link_addr[i].target);
9215 if (addr) {
9216 set_jump_target(link_addr[i].addr, addr);
104df9d3 9217 ndrc_add_jump_out(link_addr[i].target,stub);
57871462 9218 }
643aeae3 9219 else
9220 set_jump_target(link_addr[i].addr, stub);
57871462 9221 }
9222 else
9223 {
9224 // Internal branch
643aeae3 9225 int target=(link_addr[i].target-start)>>2;
57871462 9226 assert(target>=0&&target<slen);
9227 assert(instr_addr[target]);
9228 //#ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
643aeae3 9229 //set_jump_target_fillslot(link_addr[i].addr,instr_addr[target],link_addr[i].ext>>1);
57871462 9230 //#else
643aeae3 9231 set_jump_target(link_addr[i].addr, instr_addr[target]);
57871462 9232 //#endif
9233 }
9234 }
3d680478 9235
9236 u_int source_len = slen*4;
cf95b4f0 9237 if (dops[slen-1].itype == INTCALL && source_len > 4)
3d680478 9238 // no need to treat the last instruction as compiled
9239 // as interpreter fully handles it
9240 source_len -= 4;
9241
9242 if ((u_char *)copy + source_len > (u_char *)shadow + sizeof(shadow))
9243 copy = shadow;
9244
57871462 9245 // External Branch Targets (jump_in)
104df9d3 9246 int jump_in_count = 1;
9247 assert(instr_addr[0]);
9248 for (i = 1; i < slen; i++)
9249 {
9250 if (dops[i].bt && instr_addr[i])
9251 jump_in_count++;
9252 }
9253
9254 struct block_info *block =
9255 new_block_info(start, slen * 4, source, copy, beginning, jump_in_count);
9256 block->reg_sv_flags = state_rflags;
9257
9258 int jump_in_i = 0;
9259 for (i = 0; i < slen; i++)
57871462 9260 {
104df9d3 9261 if ((i == 0 || dops[i].bt) && instr_addr[i])
57871462 9262 {
104df9d3 9263 assem_debug("%p (%d) <- %8x\n", instr_addr[i], i, start + i*4);
9264 u_int vaddr = start + i*4;
9265
9266 literal_pool(256);
9267 void *entry = out;
9268 load_regs_entry(i);
9269 if (entry == out)
9270 entry = instr_addr[i];
9271 else
9272 emit_jmp(instr_addr[i]);
9273
9274 block->jump_in[jump_in_i].vaddr = vaddr;
9275 block->jump_in[jump_in_i].addr = entry;
9276 jump_in_i++;
57871462 9277 }
9278 }
104df9d3 9279 assert(jump_in_i == jump_in_count);
9280 hash_table_add(block->jump_in[0].vaddr, block->jump_in[0].addr);
57871462 9281 // Write out the literal pool if necessary
9282 literal_pool(0);
9283 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
9284 // Align code
9285 if(((u_int)out)&7) emit_addnop(13);
9286 #endif
01d26796 9287 assert(out - (u_char *)beginning < MAX_OUTPUT_BLOCK_SIZE);
643aeae3 9288 //printf("shadow buffer: %p-%p\n",copy,(u_char *)copy+slen*4);
3d680478 9289 memcpy(copy, source, source_len);
9290 copy += source_len;
9f51b4b9 9291
d148d265 9292 end_block(beginning);
9f51b4b9 9293
57871462 9294 // If we're within 256K of the end of the buffer,
9295 // start over from the beginning. (Is 256K enough?)
2a014d73 9296 if (out > ndrc->translation_cache + sizeof(ndrc->translation_cache) - MAX_OUTPUT_BLOCK_SIZE)
9297 out = ndrc->translation_cache;
9f51b4b9 9298
57871462 9299 // Trap writes to any of the pages we compiled
104df9d3 9300 mark_invalid_code(start, slen*4, 0);
9f51b4b9 9301
57871462 9302 /* Pass 10 - Free memory by expiring oldest blocks */
9f51b4b9 9303
4149788d 9304 pass10_expire_blocks();
9305
37387d8b 9306#ifdef ASSEM_PRINT
9307 fflush(stdout);
9308#endif
ece032e6 9309 stat_inc(stat_bc_direct);
57871462 9310 return 0;
9311}
b9b61529 9312
9313// vim:shiftwidth=2:expandtab
ARM optimized PCSX fork