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drc: make hash table issues easier to debug
[pcsx_rearmed.git] / libpcsxcore / new_dynarec / new_dynarec.c
CommitLineData
57871462 1/* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
2 * Mupen64plus - new_dynarec.c *
20d507ba 3 * Copyright (C) 2009-2011 Ari64 *
57871462 4 * *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
9 * *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
14 * *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. *
19 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */
20
21#include <stdlib.h>
22#include <stdint.h> //include for uint64_t
23#include <assert.h>
d848b60a 24#include <errno.h>
4600ba03 25#include <sys/mman.h>
d148d265 26#ifdef __MACH__
27#include <libkern/OSCacheControl.h>
28#endif
1e212a25 29#ifdef _3DS
30#include <3ds_utils.h>
31#endif
3039c914 32#ifdef HAVE_LIBNX
33#include <switch.h>
34static Jit g_jit;
35#endif
57871462 36
d148d265 37#include "new_dynarec_config.h"
3968e69e 38#include "../psxhle.h"
39#include "../psxinterpreter.h"
de74f599 40#include "../psxcounters.h"
81dbbf4c 41#include "../gte.h"
42#include "emu_if.h" // emulator interface
a5cd72d0 43#include "linkage_offsets.h"
44#include "compiler_features.h"
cdc2da64 45#include "arm_features.h"
57871462 46
b14b6a8f 47#ifndef ARRAY_SIZE
48#define ARRAY_SIZE(x) (sizeof(x) / sizeof(x[0]))
49#endif
e3c6bdb5 50#ifndef min
51#define min(a, b) ((b) < (a) ? (b) : (a))
52#endif
32631e6a 53#ifndef max
54#define max(a, b) ((b) > (a) ? (b) : (a))
55#endif
b14b6a8f 56
4600ba03 57//#define DISASM
32631e6a 58//#define ASSEM_PRINT
a5cd72d0 59//#define REGMAP_PRINT // with DISASM only
9b495f6e 60//#define INV_DEBUG_W
ece032e6 61//#define STAT_PRINT
32631e6a 62
63#ifdef ASSEM_PRINT
64#define assem_debug printf
65#else
4600ba03 66#define assem_debug(...)
32631e6a 67#endif
68//#define inv_debug printf
4600ba03 69#define inv_debug(...)
57871462 70
71#ifdef __i386__
72#include "assem_x86.h"
73#endif
74#ifdef __x86_64__
75#include "assem_x64.h"
76#endif
77#ifdef __arm__
78#include "assem_arm.h"
79#endif
be516ebe 80#ifdef __aarch64__
81#include "assem_arm64.h"
82#endif
57871462 83
81dbbf4c 84#define RAM_SIZE 0x200000
d3201e39 85#define MAXBLOCK 2048
57871462 86#define MAX_OUTPUT_BLOCK_SIZE 262144
93c0345b 87#define EXPIRITY_OFFSET (MAX_OUTPUT_BLOCK_SIZE * 2)
88#define PAGE_COUNT 1024
2573466a 89
882a08fc 90#if defined(HAVE_CONDITIONAL_CALL) && !defined(DESTRUCTIVE_SHIFT)
91#define INVALIDATE_USE_COND_CALL
92#endif
93
66ea165f 94#ifdef VITA
95// apparently Vita has a 16MB limit, so either we cut tc in half,
96// or use this hack (it's a hack because tc size was designed to be power-of-2)
97#define TC_REDUCE_BYTES 4096
98#else
99#define TC_REDUCE_BYTES 0
100#endif
101
d9e2b173 102struct ndrc_tramp
103{
104 struct tramp_insns ops[2048 / sizeof(struct tramp_insns)];
105 const void *f[2048 / sizeof(void *)];
106};
107
2a014d73 108struct ndrc_mem
109{
66ea165f 110 u_char translation_cache[(1 << TARGET_SIZE_2) - TC_REDUCE_BYTES];
d9e2b173 111 struct ndrc_tramp tramp;
2a014d73 112};
113
114#ifdef BASE_ADDR_DYNAMIC
115static struct ndrc_mem *ndrc;
116#else
117static struct ndrc_mem ndrc_ __attribute__((aligned(4096)));
118static struct ndrc_mem *ndrc = &ndrc_;
119#endif
d9e2b173 120#ifdef TC_WRITE_OFFSET
3039c914 121# ifdef __GLIBC__
122# include <sys/types.h>
123# include <sys/stat.h>
124# include <fcntl.h>
125# include <unistd.h>
126# endif
127static long ndrc_write_ofs;
d9e2b173 128#define NDRC_WRITE_OFFSET(x) (void *)((char *)(x) + ndrc_write_ofs)
3039c914 129#else
d9e2b173 130#define NDRC_WRITE_OFFSET(x) (x)
3039c914 131#endif
2a014d73 132
b14b6a8f 133// stubs
134enum stub_type {
135 CC_STUB = 1,
a5cd72d0 136 //FP_STUB = 2,
b14b6a8f 137 LOADB_STUB = 3,
138 LOADH_STUB = 4,
139 LOADW_STUB = 5,
a5cd72d0 140 //LOADD_STUB = 6,
b14b6a8f 141 LOADBU_STUB = 7,
142 LOADHU_STUB = 8,
143 STOREB_STUB = 9,
144 STOREH_STUB = 10,
145 STOREW_STUB = 11,
a5cd72d0 146 //STORED_STUB = 12,
b14b6a8f 147 STORELR_STUB = 13,
148 INVCODE_STUB = 14,
a5cd72d0 149 OVERFLOW_STUB = 15,
277718fa 150 ALIGNMENT_STUB = 16,
b14b6a8f 151};
152
6cc8d23c 153// regmap_pre[i] - regs before [i] insn starts; dirty things here that
154// don't match .regmap will be written back
155// [i].regmap_entry - regs that must be set up if someone jumps here
156// [i].regmap - regs [i] insn will read/(over)write
2acc46cd 157// branch_regs[i].* - same as above but for branches, takes delay slot into account
57871462 158struct regstat
159{
6cc8d23c 160 signed char regmap_entry[HOST_REGS];
57871462 161 signed char regmap[HOST_REGS];
a22ccd6a 162 u_int wasdirty;
163 u_int dirty;
24058131 164 u_int wasconst; // before; for example 'lw r2, (r2)' wasconst is true
a5cd72d0 165 u_int isconst; // ... but isconst is false when r2 is known (hr)
8575a877 166 u_int loadedconst; // host regs that have constants loaded
90f98e7c 167 u_int noevict; // can't evict this hr (alloced by current op)
9b495f6e 168 //u_int waswritten; // MIPS regs that were used as store base before
a22ccd6a 169 uint64_t u;
57871462 170};
171
df4dc2b1 172struct ht_entry
173{
174 u_int vaddr[2];
175 void *tcaddr[2];
176};
177
b14b6a8f 178struct code_stub
179{
180 enum stub_type type;
181 void *addr;
182 void *retaddr;
183 u_int a;
184 uintptr_t b;
185 uintptr_t c;
186 u_int d;
187 u_int e;
188};
189
643aeae3 190struct link_entry
191{
192 void *addr;
193 u_int target;
104df9d3 194 u_int internal;
195};
196
197struct block_info
198{
199 struct block_info *next;
200 const void *source;
201 const void *copy;
202 u_int start; // vaddr of the block start
203 u_int len; // of the whole block source
204 u_int tc_offs;
205 //u_int tc_len;
206 u_int reg_sv_flags;
3280e616 207 u_char is_dirty;
208 u_char inv_near_misses;
104df9d3 209 u_short jump_in_cnt;
210 struct {
211 u_int vaddr;
212 void *addr;
213 } jump_in[0];
643aeae3 214};
215
b7ad2f2c 216struct jump_info
217{
218 int alloc;
219 int count;
220 struct {
221 u_int target_vaddr;
222 void *stub;
223 } e[0];
224};
225
cf95b4f0 226static struct decoded_insn
227{
228 u_char itype;
a5cd72d0 229 u_char opcode; // bits 31-26
230 u_char opcode2; // (depends on opcode)
cf95b4f0 231 u_char rs1;
232 u_char rs2;
233 u_char rt1;
234 u_char rt2;
53dc27f6 235 u_char use_lt1:1;
cf95b4f0 236 u_char bt:1;
cf95b4f0 237 u_char ooo:1;
238 u_char is_ds:1;
fe807a8a 239 u_char is_jump:1;
240 u_char is_ujump:1;
37387d8b 241 u_char is_load:1;
242 u_char is_store:1;
a5cd72d0 243 u_char is_delay_load:1; // is_load + MFC/CFC
244 u_char is_exception:1; // unconditional, also interp. fallback
245 u_char may_except:1; // might generate an exception
f9e9616e 246 u_char ls_type:2; // load/store type (ls_width_type)
cf95b4f0 247} dops[MAXBLOCK];
248
f9e9616e 249enum ls_width_type {
250 LS_8 = 0, LS_16, LS_32, LS_LR
251};
252
277718fa 253static struct compile_info
254{
255 int imm;
256 u_int ba;
257 int ccadj;
258 signed char min_free_regs;
259 signed char addr;
260 signed char reserved[2];
261} cinfo[MAXBLOCK];
262
398d6924 263 static u_char *out;
6d75addf 264 static char invalid_code[0x100000];
104df9d3 265 static struct ht_entry hash_table[65536];
93c0345b 266 static struct block_info *blocks[PAGE_COUNT];
b7ad2f2c 267 static struct jump_info *jumps[PAGE_COUNT];
e2b5e7aa 268 static u_int start;
269 static u_int *source;
bedfea38 270 static uint64_t gte_rs[MAXBLOCK]; // gte: 32 data and 32 ctl regs
271 static uint64_t gte_rt[MAXBLOCK];
272 static uint64_t gte_unneeded[MAXBLOCK];
ffb0b9e0 273 static u_int smrv[32]; // speculated MIPS register values
274 static u_int smrv_strong; // mask or regs that are likely to have correct values
275 static u_int smrv_weak; // same, but somewhat less likely
276 static u_int smrv_strong_next; // same, but after current insn executes
277 static u_int smrv_weak_next;
e2b5e7aa 278 static uint64_t unneeded_reg[MAXBLOCK];
e2b5e7aa 279 static uint64_t branch_unneeded_reg[MAXBLOCK];
6cc8d23c 280 // see 'struct regstat' for a description
2330734f 281 static signed char regmap_pre[MAXBLOCK][HOST_REGS];
40fca85b 282 // contains 'real' consts at [i] insn, but may differ from what's actually
283 // loaded in host reg as 'final' value is always loaded, see get_final_value()
284 static uint32_t current_constmap[HOST_REGS];
285 static uint32_t constmap[MAXBLOCK][HOST_REGS];
956f3129 286 static struct regstat regs[MAXBLOCK];
287 static struct regstat branch_regs[MAXBLOCK];
e2b5e7aa 288 static int slen;
df4dc2b1 289 static void *instr_addr[MAXBLOCK];
643aeae3 290 static struct link_entry link_addr[MAXBLOCK];
e2b5e7aa 291 static int linkcount;
b14b6a8f 292 static struct code_stub stubs[MAXBLOCK*3];
e2b5e7aa 293 static int stubcount;
294 static u_int literals[1024][2];
295 static int literalcount;
296 static int is_delayslot;
e2b5e7aa 297 static char shadow[1048576] __attribute__((aligned(16)));
298 static void *copy;
93c0345b 299 static u_int expirep;
e2b5e7aa 300 static u_int stop_after_jal;
7f94b097 301 static u_int f1_hack;
ece032e6 302#ifdef STAT_PRINT
303 static int stat_bc_direct;
304 static int stat_bc_pre;
305 static int stat_bc_restore;
104df9d3 306 static int stat_ht_lookups;
ece032e6 307 static int stat_jump_in_lookups;
308 static int stat_restore_tries;
309 static int stat_restore_compares;
310 static int stat_inv_addr_calls;
311 static int stat_inv_hits;
104df9d3 312 static int stat_blocks;
313 static int stat_links;
ece032e6 314 #define stat_inc(s) s++
104df9d3 315 #define stat_dec(s) s--
316 #define stat_clear(s) s = 0
ece032e6 317#else
318 #define stat_inc(s)
104df9d3 319 #define stat_dec(s)
320 #define stat_clear(s)
ece032e6 321#endif
e2b5e7aa 322
323 int new_dynarec_hacks;
d62c125a 324 int new_dynarec_hacks_pergame;
32631e6a 325 int new_dynarec_hacks_old;
e2b5e7aa 326 int new_dynarec_did_compile;
687b4580 327
d62c125a 328 #define HACK_ENABLED(x) ((new_dynarec_hacks | new_dynarec_hacks_pergame) & (x))
329
de6dbc52 330 extern int cycle_count; // ... until end of the timeslice, counts -N -> 0 (CCREG)
687b4580 331 extern int last_count; // last absolute target, often = next_interupt
332 extern int pcaddr;
333 extern int pending_exception;
334 extern int branch_target;
37387d8b 335 extern uintptr_t ram_offset;
d1e4ebd9 336 extern uintptr_t mini_ht[32][2];
57871462 337
338 /* registers that may be allocated */
339 /* 1-31 gpr */
7c3a5182 340#define LOREG 32 // lo
341#define HIREG 33 // hi
00fa9369 342//#define FSREG 34 // FPU status (FCSR)
de6dbc52 343//#define CSREG 35 // Coprocessor status
57871462 344#define CCREG 36 // Cycle count
345#define INVCP 37 // Pointer to invalid_code
1edfcc68 346//#define MMREG 38 // Pointer to memory_map
33a1eda1 347#define ROREG 39 // ram offset (if psxM != 0x80000000)
619e5ded 348#define TEMPREG 40
33a1eda1 349#define FTEMP 40 // Load/store temporary register (was fpu)
619e5ded 350#define PTEMP 41 // Prefetch temporary register
1edfcc68 351//#define TLREG 42 // TLB mapping offset
619e5ded 352#define RHASH 43 // Return address hash
353#define RHTBL 44 // Return address hash table address
354#define RTEMP 45 // JR/JALR address register
355#define MAXREG 45
277718fa 356#define AGEN1 46 // Address generation temporary register (pass5b_preallocate2)
1edfcc68 357//#define AGEN2 47 // Address generation temporary register
57871462 358
359 /* instruction types */
360#define NOP 0 // No operation
361#define LOAD 1 // Load
362#define STORE 2 // Store
363#define LOADLR 3 // Unaligned load
364#define STORELR 4 // Unaligned store
a5cd72d0 365#define MOV 5 // Move (hi/lo only)
57871462 366#define ALU 6 // Arithmetic/logic
367#define MULTDIV 7 // Multiply/divide
368#define SHIFT 8 // Shift by register
369#define SHIFTIMM 9// Shift by immediate
370#define IMM16 10 // 16-bit immediate
371#define RJUMP 11 // Unconditional jump to register
372#define UJUMP 12 // Unconditional jump
373#define CJUMP 13 // Conditional branch (BEQ/BNE/BGTZ/BLEZ)
374#define SJUMP 14 // Conditional branch (regimm format)
375#define COP0 15 // Coprocessor 0
a5cd72d0 376#define RFE 16
d1150cd6 377#define SYSCALL 22// SYSCALL,BREAK
a5cd72d0 378#define OTHER 23 // Other/unknown - do nothing
7139f3c8 379#define HLECALL 26// PCSX fake opcodes for HLE
b9b61529 380#define COP2 27 // Coprocessor 2 move
381#define C2LS 28 // Coprocessor 2 load/store
382#define C2OP 29 // Coprocessor 2 operation
1e973cb0 383#define INTCALL 30// Call interpreter to handle rare corner cases
57871462 384
57871462 385 /* branch codes */
386#define TAKEN 1
387#define NOTTAKEN 2
57871462 388
7c3a5182 389#define DJT_1 (void *)1l // no function, just a label in assem_debug log
390#define DJT_2 (void *)2l
391
57871462 392// asm linkage
57871462 393void dyna_linker();
57871462 394void cc_interrupt();
d1150cd6 395void jump_syscall (u_int u0, u_int u1, u_int pc);
396void jump_syscall_ds(u_int u0, u_int u1, u_int pc);
397void jump_break (u_int u0, u_int u1, u_int pc);
398void jump_break_ds(u_int u0, u_int u1, u_int pc);
a5cd72d0 399void jump_overflow (u_int u0, u_int u1, u_int pc);
400void jump_overflow_ds(u_int u0, u_int u1, u_int pc);
277718fa 401void jump_addrerror (u_int cause, u_int addr, u_int pc);
402void jump_addrerror_ds(u_int cause, u_int addr, u_int pc);
3968e69e 403void jump_to_new_pc();
81dbbf4c 404void call_gteStall();
7139f3c8 405void new_dyna_leave();
57871462 406
104df9d3 407void *ndrc_get_addr_ht_param(u_int vaddr, int can_compile);
408void *ndrc_get_addr_ht(u_int vaddr);
104df9d3 409void ndrc_add_jump_out(u_int vaddr, void *src);
9b495f6e 410void ndrc_write_invalidate_one(u_int addr);
411static void ndrc_write_invalidate_many(u_int addr, u_int end);
104df9d3 412
413static int new_recompile_block(u_int addr);
414static void invalidate_block(struct block_info *block);
a5cd72d0 415static void exception_assemble(int i, const struct regstat *i_regs, int ccadj_);
398d6924 416
57871462 417// Needed by assembler
a22ccd6a 418static void wb_register(signed char r, const signed char regmap[], u_int dirty);
419static void wb_dirtys(const signed char i_regmap[], u_int i_dirty);
420static void wb_needed_dirtys(const signed char i_regmap[], u_int i_dirty, int addr);
2330734f 421static void load_all_regs(const signed char i_regmap[]);
422static void load_needed_regs(const signed char i_regmap[], const signed char next_regmap[]);
e2b5e7aa 423static void load_regs_entry(int t);
2330734f 424static void load_all_consts(const signed char regmap[], u_int dirty, int i);
81dbbf4c 425static u_int get_host_reglist(const signed char *regmap);
e2b5e7aa 426
de6dbc52 427static int get_final_value(int hr, int i, u_int *value);
b14b6a8f 428static void add_stub(enum stub_type type, void *addr, void *retaddr,
429 u_int a, uintptr_t b, uintptr_t c, u_int d, u_int e);
430static void add_stub_r(enum stub_type type, void *addr, void *retaddr,
81dbbf4c 431 int i, int addr_reg, const struct regstat *i_regs, int ccadj, u_int reglist);
643aeae3 432static void add_to_linker(void *addr, u_int target, int ext);
687b4580 433static void *get_direct_memhandler(void *table, u_int addr,
434 enum stub_type type, uintptr_t *addr_host);
32631e6a 435static void cop2_do_stall_check(u_int op, int i, const struct regstat *i_regs, u_int reglist);
687b4580 436static void pass_args(int a0, int a1);
2a014d73 437static void emit_far_jump(const void *f);
438static void emit_far_call(const void *f);
57871462 439
9c67c98f 440#ifdef VITA
441#include <psp2/kernel/sysmem.h>
442static int sceBlock;
443// note: this interacts with RetroArch's Vita bootstrap code: bootstrap/vita/sbrk.c
444extern int getVMBlock();
445int _newlib_vm_size_user = sizeof(*ndrc);
446#endif
447
d148d265 448static void mprotect_w_x(void *start, void *end, int is_x)
449{
450#ifdef NO_WRITE_EXEC
1e212a25 451 #if defined(VITA)
452 // *Open* enables write on all memory that was
453 // allocated by sceKernelAllocMemBlockForVM()?
454 if (is_x)
455 sceKernelCloseVMDomain();
456 else
457 sceKernelOpenVMDomain();
3039c914 458 #elif defined(HAVE_LIBNX)
459 Result rc;
d9e2b173 460 // check to avoid the full flush in jitTransitionToExecutable()
461 if (g_jit.type != JitType_CodeMemory) {
462 if (is_x)
463 rc = jitTransitionToExecutable(&g_jit);
464 else
465 rc = jitTransitionToWritable(&g_jit);
466 if (R_FAILED(rc))
467 ;//SysPrintf("jitTransition %d %08x\n", is_x, rc);
468 }
469 #elif defined(TC_WRITE_OFFSET)
3039c914 470 // separated rx and rw areas are always available
1e212a25 471 #else
d148d265 472 u_long mstart = (u_long)start & ~4095ul;
473 u_long mend = (u_long)end;
474 if (mprotect((void *)mstart, mend - mstart,
475 PROT_READ | (is_x ? PROT_EXEC : PROT_WRITE)) != 0)
476 SysPrintf("mprotect(%c) failed: %s\n", is_x ? 'x' : 'w', strerror(errno));
1e212a25 477 #endif
d148d265 478#endif
479}
480
d9e2b173 481static void start_tcache_write(void *start, void *end)
d148d265 482{
483 mprotect_w_x(start, end, 0);
484}
485
486static void end_tcache_write(void *start, void *end)
487{
919981d0 488#if defined(__arm__) || defined(__aarch64__)
d148d265 489 size_t len = (char *)end - (char *)start;
490 #if defined(__BLACKBERRY_QNX__)
491 msync(start, len, MS_SYNC | MS_CACHE_ONLY | MS_INVALIDATE_ICACHE);
492 #elif defined(__MACH__)
493 sys_cache_control(kCacheFunctionPrepareForExecution, start, len);
494 #elif defined(VITA)
1e212a25 495 sceKernelSyncVMDomain(sceBlock, start, len);
496 #elif defined(_3DS)
497 ctr_flush_invalidate_cache();
3039c914 498 #elif defined(HAVE_LIBNX)
d9e2b173 499 if (g_jit.type == JitType_CodeMemory) {
500 armDCacheClean(start, len);
501 armICacheInvalidate((char *)start - ndrc_write_ofs, len);
aaece508 502 // as of v4.2.1 libnx lacks isb
503 __asm__ volatile("isb" ::: "memory");
d9e2b173 504 }
919981d0 505 #elif defined(__aarch64__)
506 // as of 2021, __clear_cache() is still broken on arm64
507 // so here is a custom one :(
508 clear_cache_arm64(start, end);
d148d265 509 #else
510 __clear_cache(start, end);
511 #endif
512 (void)len;
513#endif
514
515 mprotect_w_x(start, end, 1);
516}
517
518static void *start_block(void)
519{
520 u_char *end = out + MAX_OUTPUT_BLOCK_SIZE;
2a014d73 521 if (end > ndrc->translation_cache + sizeof(ndrc->translation_cache))
522 end = ndrc->translation_cache + sizeof(ndrc->translation_cache);
d9e2b173 523 start_tcache_write(NDRC_WRITE_OFFSET(out), NDRC_WRITE_OFFSET(end));
d148d265 524 return out;
525}
526
527static void end_block(void *start)
528{
d9e2b173 529 end_tcache_write(NDRC_WRITE_OFFSET(start), NDRC_WRITE_OFFSET(out));
d148d265 530}
531
af700b41 532#ifdef NDRC_CACHE_FLUSH_ALL
533
534static int needs_clear_cache;
535
536static void mark_clear_cache(void *target)
537{
538 if (!needs_clear_cache) {
d9e2b173 539 start_tcache_write(NDRC_WRITE_OFFSET(ndrc), NDRC_WRITE_OFFSET(ndrc + 1));
af700b41 540 needs_clear_cache = 1;
541 }
542}
543
544static void do_clear_cache(void)
545{
546 if (needs_clear_cache) {
d9e2b173 547 end_tcache_write(NDRC_WRITE_OFFSET(ndrc), NDRC_WRITE_OFFSET(ndrc + 1));
af700b41 548 needs_clear_cache = 0;
549 }
550}
551
552#else
553
919981d0 554// also takes care of w^x mappings when patching code
555static u_int needs_clear_cache[1<<(TARGET_SIZE_2-17)];
556
557static void mark_clear_cache(void *target)
558{
559 uintptr_t offset = (u_char *)target - ndrc->translation_cache;
560 u_int mask = 1u << ((offset >> 12) & 31);
561 if (!(needs_clear_cache[offset >> 17] & mask)) {
d9e2b173 562 char *start = (char *)NDRC_WRITE_OFFSET((uintptr_t)target & ~4095l);
919981d0 563 start_tcache_write(start, start + 4095);
564 needs_clear_cache[offset >> 17] |= mask;
565 }
566}
567
568// Clearing the cache is rather slow on ARM Linux, so mark the areas
569// that need to be cleared, and then only clear these areas once.
570static void do_clear_cache(void)
571{
572 int i, j;
573 for (i = 0; i < (1<<(TARGET_SIZE_2-17)); i++)
574 {
575 u_int bitmap = needs_clear_cache[i];
576 if (!bitmap)
577 continue;
578 for (j = 0; j < 32; j++)
579 {
580 u_char *start, *end;
93c0345b 581 if (!(bitmap & (1u << j)))
919981d0 582 continue;
583
584 start = ndrc->translation_cache + i*131072 + j*4096;
585 end = start + 4095;
586 for (j++; j < 32; j++) {
93c0345b 587 if (!(bitmap & (1u << j)))
919981d0 588 break;
589 end += 4096;
590 }
d9e2b173 591 end_tcache_write(NDRC_WRITE_OFFSET(start), NDRC_WRITE_OFFSET(end));
919981d0 592 }
593 needs_clear_cache[i] = 0;
594 }
595}
596
af700b41 597#endif // NDRC_CACHE_FLUSH_ALL
57871462 598
b6e87b2b 599#define NO_CYCLE_PENALTY_THR 12
600
32631e6a 601int cycle_multiplier_old;
24058131 602static int cycle_multiplier_active;
4e9dcd7f 603
604static int CLOCK_ADJUST(int x)
605{
24058131 606 int m = cycle_multiplier_active;
607 int s = (x >> 31) | 1;
a3203cf4 608 return (x * m + s * 50) / 100;
4e9dcd7f 609}
610
4919de1e 611static int ds_writes_rjump_rs(int i)
612{
ecca05e3 613 return dops[i].rs1 != 0
614 && (dops[i].rs1 == dops[i+1].rt1 || dops[i].rs1 == dops[i+1].rt2
615 || dops[i].rs1 == dops[i].rt1); // overwrites itself - same effect
4919de1e 616}
617
104df9d3 618// psx addr mirror masking (for invalidation)
619static u_int pmmask(u_int vaddr)
620{
621 vaddr &= ~0xe0000000;
622 if (vaddr < 0x01000000)
623 vaddr &= ~0x00e00000; // RAM mirrors
624 return vaddr;
625}
626
94d23bb9 627static u_int get_page(u_int vaddr)
57871462 628{
104df9d3 629 u_int page = pmmask(vaddr) >> 12;
93c0345b 630 if (page >= PAGE_COUNT / 2)
631 page = PAGE_COUNT / 2 + (page & (PAGE_COUNT / 2 - 1));
94d23bb9 632 return page;
633}
634
104df9d3 635// get a page for looking for a block that has vaddr
636// (needed because the block may start in previous page)
637static u_int get_page_prev(u_int vaddr)
d25604ca 638{
104df9d3 639 assert(MAXBLOCK <= (1 << 12));
640 u_int page = get_page(vaddr);
641 if (page & 511)
642 page--;
643 return page;
d25604ca 644}
94d23bb9 645
df4dc2b1 646static struct ht_entry *hash_table_get(u_int vaddr)
647{
648 return &hash_table[((vaddr>>16)^vaddr)&0xFFFF];
649}
650
04714958 651#define HASH_TABLE_BAD 0xbac
652
653static void hash_table_clear(void)
654{
655 struct ht_entry *ht_bin;
656 int i, j;
657 for (i = 0; i < ARRAY_SIZE(hash_table); i++) {
658 for (j = 0; j < ARRAY_SIZE(hash_table[i].vaddr); j++) {
659 hash_table[i].vaddr[j] = ~0;
660 hash_table[i].tcaddr[j] = (void *)(uintptr_t)HASH_TABLE_BAD;
661 }
662 }
663 // don't allow ~0 to hit
664 ht_bin = hash_table_get(~0);
665 for (j = 0; j < ARRAY_SIZE(ht_bin->vaddr); j++)
666 ht_bin->vaddr[j] = 1;
667}
668
104df9d3 669static void hash_table_add(u_int vaddr, void *tcaddr)
df4dc2b1 670{
104df9d3 671 struct ht_entry *ht_bin = hash_table_get(vaddr);
672 assert(tcaddr);
df4dc2b1 673 ht_bin->vaddr[1] = ht_bin->vaddr[0];
674 ht_bin->tcaddr[1] = ht_bin->tcaddr[0];
675 ht_bin->vaddr[0] = vaddr;
676 ht_bin->tcaddr[0] = tcaddr;
677}
678
104df9d3 679static void hash_table_remove(int vaddr)
680{
681 //printf("remove hash: %x\n",vaddr);
682 struct ht_entry *ht_bin = hash_table_get(vaddr);
683 if (ht_bin->vaddr[1] == vaddr) {
04714958 684 ht_bin->vaddr[1] = ~0;
685 ht_bin->tcaddr[1] = (void *)(uintptr_t)HASH_TABLE_BAD;
104df9d3 686 }
687 if (ht_bin->vaddr[0] == vaddr) {
688 ht_bin->vaddr[0] = ht_bin->vaddr[1];
689 ht_bin->tcaddr[0] = ht_bin->tcaddr[1];
04714958 690 ht_bin->vaddr[1] = ~0;
691 ht_bin->tcaddr[1] = (void *)(uintptr_t)HASH_TABLE_BAD;
104df9d3 692 }
693}
694
04714958 695static void mini_ht_clear(void)
696{
697#ifdef USE_MINI_HT
698 int i;
699 for (i = 0; i < ARRAY_SIZE(mini_ht) - 1; i++) {
700 mini_ht[i][0] = ~0;
701 mini_ht[i][1] = HASH_TABLE_BAD;
702 }
703 mini_ht[i][0] = 1;
704 mini_ht[i][1] = HASH_TABLE_BAD;
705#endif
706}
707
104df9d3 708static void mark_invalid_code(u_int vaddr, u_int len, char invalid)
398d6924 709{
ab4377be 710 u_int vaddr_m = vaddr & 0x1fffffff;
398d6924 711 u_int i, j;
ab4377be 712 for (i = vaddr_m & ~0xfff; i < vaddr_m + len; i += 0x1000) {
398d6924 713 // ram mirrors, but should not hurt bios
714 for (j = 0; j < 0x800000; j += 0x200000) {
715 invalid_code[(i|j) >> 12] =
716 invalid_code[(i|j|0x80000000u) >> 12] =
104df9d3 717 invalid_code[(i|j|0xa0000000u) >> 12] = invalid;
398d6924 718 }
719 }
882a08fc 720 if (!invalid && vaddr + len > inv_code_start && vaddr <= inv_code_end)
104df9d3 721 inv_code_start = inv_code_end = ~0;
398d6924 722}
723
93c0345b 724static int doesnt_expire_soon(u_char *tcaddr)
df4dc2b1 725{
93c0345b 726 u_int diff = (u_int)(tcaddr - out) & ((1u << TARGET_SIZE_2) - 1u);
727 return diff > EXPIRITY_OFFSET + MAX_OUTPUT_BLOCK_SIZE;
df4dc2b1 728}
729
9b495f6e 730static unused void check_for_block_changes(u_int start, u_int end)
731{
732 u_int start_page = get_page_prev(start);
733 u_int end_page = get_page(end - 1);
734 u_int page;
735
736 for (page = start_page; page <= end_page; page++) {
737 struct block_info *block;
738 for (block = blocks[page]; block != NULL; block = block->next) {
739 if (block->is_dirty)
740 continue;
741 if (memcmp(block->source, block->copy, block->len)) {
742 printf("bad block %08x-%08x %016llx %016llx @%08x\n",
743 block->start, block->start + block->len,
744 *(long long *)block->source, *(long long *)block->copy, psxRegs.pc);
745 fflush(stdout);
746 abort();
747 }
748 }
749 }
750}
751
104df9d3 752static void *try_restore_block(u_int vaddr, u_int start_page, u_int end_page)
398d6924 753{
104df9d3 754 void *found_clean = NULL;
755 u_int i, page;
398d6924 756
ece032e6 757 stat_inc(stat_restore_tries);
104df9d3 758 for (page = start_page; page <= end_page; page++) {
759 struct block_info *block;
760 for (block = blocks[page]; block != NULL; block = block->next) {
761 if (vaddr < block->start)
762 break;
763 if (!block->is_dirty || vaddr >= block->start + block->len)
764 continue;
765 for (i = 0; i < block->jump_in_cnt; i++)
766 if (block->jump_in[i].vaddr == vaddr)
767 break;
768 if (i == block->jump_in_cnt)
769 continue;
770 assert(block->source && block->copy);
771 stat_inc(stat_restore_compares);
772 if (memcmp(block->source, block->copy, block->len))
773 continue;
398d6924 774
3280e616 775 block->is_dirty = block->inv_near_misses = 0;
104df9d3 776 found_clean = block->jump_in[i].addr;
777 hash_table_add(vaddr, found_clean);
778 mark_invalid_code(block->start, block->len, 0);
779 stat_inc(stat_bc_restore);
780 inv_debug("INV: restored %08x %p (%d)\n", vaddr, found_clean, block->jump_in_cnt);
781 return found_clean;
398d6924 782 }
398d6924 783 }
104df9d3 784 return NULL;
398d6924 785}
786
de6dbc52 787// this doesn't normally happen
788static noinline u_int generate_exception(u_int pc)
789{
790 //if (execBreakCheck(&psxRegs, pc))
791 // return psxRegs.pc;
792
793 // generate an address or bus error
794 psxRegs.CP0.n.Cause &= 0x300;
795 psxRegs.CP0.n.EPC = pc;
796 if (pc & 3) {
797 psxRegs.CP0.n.Cause |= R3000E_AdEL << 2;
798 psxRegs.CP0.n.BadVAddr = pc;
799#ifdef DRC_DBG
800 last_count -= 2;
801#endif
802 } else
803 psxRegs.CP0.n.Cause |= R3000E_IBE << 2;
804 return (psxRegs.pc = 0x80000080);
805}
806
94d23bb9 807// Get address from virtual address
808// This is called from the recompiled JR/JALR instructions
104df9d3 809static void noinline *get_addr(u_int vaddr, int can_compile)
94d23bb9 810{
104df9d3 811 u_int start_page = get_page_prev(vaddr);
812 u_int i, page, end_page = get_page(vaddr);
813 void *found_clean = NULL;
398d6924 814
ece032e6 815 stat_inc(stat_jump_in_lookups);
104df9d3 816 for (page = start_page; page <= end_page; page++) {
817 const struct block_info *block;
818 for (block = blocks[page]; block != NULL; block = block->next) {
819 if (vaddr < block->start)
820 break;
821 if (block->is_dirty || vaddr >= block->start + block->len)
822 continue;
823 for (i = 0; i < block->jump_in_cnt; i++)
824 if (block->jump_in[i].vaddr == vaddr)
825 break;
826 if (i == block->jump_in_cnt)
827 continue;
828 found_clean = block->jump_in[i].addr;
829 hash_table_add(vaddr, found_clean);
830 return found_clean;
57871462 831 }
57871462 832 }
104df9d3 833 found_clean = try_restore_block(vaddr, start_page, end_page);
834 if (found_clean)
835 return found_clean;
836
837 if (!can_compile)
838 return NULL;
398d6924 839
840 int r = new_recompile_block(vaddr);
de6dbc52 841 if (likely(r == 0))
104df9d3 842 return ndrc_get_addr_ht(vaddr);
df4dc2b1 843
de6dbc52 844 return ndrc_get_addr_ht(generate_exception(vaddr));
57871462 845}
104df9d3 846
57871462 847// Look up address in hash table first
104df9d3 848void *ndrc_get_addr_ht_param(u_int vaddr, int can_compile)
57871462 849{
9b495f6e 850 //check_for_block_changes(vaddr, vaddr + MAXBLOCK);
df4dc2b1 851 const struct ht_entry *ht_bin = hash_table_get(vaddr);
277718fa 852 u_int vaddr_a = vaddr & ~3;
104df9d3 853 stat_inc(stat_ht_lookups);
277718fa 854 if (ht_bin->vaddr[0] == vaddr_a) return ht_bin->tcaddr[0];
855 if (ht_bin->vaddr[1] == vaddr_a) return ht_bin->tcaddr[1];
104df9d3 856 return get_addr(vaddr, can_compile);
857}
858
859void *ndrc_get_addr_ht(u_int vaddr)
860{
861 return ndrc_get_addr_ht_param(vaddr, 1);
57871462 862}
863
6cc8d23c 864static void clear_all_regs(signed char regmap[])
57871462 865{
6cc8d23c 866 memset(regmap, -1, sizeof(regmap[0]) * HOST_REGS);
57871462 867}
868
53358c1d 869// get_reg: get allocated host reg from mips reg
870// returns -1 if no such mips reg was allocated
cdc2da64 871#if defined(__arm__) && defined(HAVE_ARMV6) && HOST_REGS == 13 && EXCLUDE_REG == 11
872
873extern signed char get_reg(const signed char regmap[], signed char r);
874
875#else
876
9de8a0c3 877static signed char get_reg(const signed char regmap[], signed char r)
57871462 878{
879 int hr;
9de8a0c3 880 for (hr = 0; hr < HOST_REGS; hr++) {
881 if (hr == EXCLUDE_REG)
882 continue;
883 if (regmap[hr] == r)
884 return hr;
885 }
886 return -1;
887}
888
cdc2da64 889#endif
890
a5cd72d0 891// get reg suitable for writing
892static signed char get_reg_w(const signed char regmap[], signed char r)
893{
894 return r == 0 ? -1 : get_reg(regmap, r);
895}
896
53358c1d 897// get reg as mask bit (1 << hr)
898static u_int get_regm(const signed char regmap[], signed char r)
899{
900 return (1u << (get_reg(regmap, r) & 31)) & ~(1u << 31);
901}
902
9de8a0c3 903static signed char get_reg_temp(const signed char regmap[])
904{
905 int hr;
906 for (hr = 0; hr < HOST_REGS; hr++) {
907 if (hr == EXCLUDE_REG)
908 continue;
909 if (regmap[hr] == (signed char)-1)
910 return hr;
911 }
57871462 912 return -1;
913}
914
915// Find a register that is available for two consecutive cycles
d1e4ebd9 916static signed char get_reg2(signed char regmap1[], const signed char regmap2[], int r)
57871462 917{
918 int hr;
919 for (hr=0;hr<HOST_REGS;hr++) if(hr!=EXCLUDE_REG&&regmap1[hr]==r&&regmap2[hr]==r) return hr;
920 return -1;
921}
922
53dc27f6 923// reverse reg map: mips -> host
924#define RRMAP_SIZE 64
925static void make_rregs(const signed char regmap[], signed char rrmap[RRMAP_SIZE],
926 u_int *regs_can_change)
927{
928 u_int r, hr, hr_can_change = 0;
929 memset(rrmap, -1, RRMAP_SIZE);
930 for (hr = 0; hr < HOST_REGS; )
931 {
932 r = regmap[hr];
933 rrmap[r & (RRMAP_SIZE - 1)] = hr;
934 // only add mips $1-$31+$lo, others shifted out
935 hr_can_change |= (uint64_t)1 << (hr + ((r - 1) & 32));
936 hr++;
937 if (hr == EXCLUDE_REG)
938 hr++;
939 }
940 hr_can_change |= 1u << (rrmap[33] & 31);
941 hr_can_change |= 1u << (rrmap[CCREG] & 31);
942 hr_can_change &= ~(1u << 31);
943 *regs_can_change = hr_can_change;
944}
945
946// same as get_reg, but takes rrmap
947static signed char get_rreg(signed char rrmap[RRMAP_SIZE], signed char r)
948{
949 assert(0 <= r && r < RRMAP_SIZE);
950 return rrmap[r];
951}
952
9de8a0c3 953static int count_free_regs(const signed char regmap[])
57871462 954{
955 int count=0;
956 int hr;
957 for(hr=0;hr<HOST_REGS;hr++)
958 {
959 if(hr!=EXCLUDE_REG) {
960 if(regmap[hr]<0) count++;
961 }
962 }
963 return count;
964}
965
9de8a0c3 966static void dirty_reg(struct regstat *cur, signed char reg)
57871462 967{
968 int hr;
9de8a0c3 969 if (!reg) return;
970 hr = get_reg(cur->regmap, reg);
971 if (hr >= 0)
972 cur->dirty |= 1<<hr;
57871462 973}
974
40fca85b 975static void set_const(struct regstat *cur, signed char reg, uint32_t value)
57871462 976{
977 int hr;
9de8a0c3 978 if (!reg) return;
979 hr = get_reg(cur->regmap, reg);
980 if (hr >= 0) {
981 cur->isconst |= 1<<hr;
982 current_constmap[hr] = value;
57871462 983 }
984}
985
40fca85b 986static void clear_const(struct regstat *cur, signed char reg)
57871462 987{
988 int hr;
9de8a0c3 989 if (!reg) return;
990 hr = get_reg(cur->regmap, reg);
991 if (hr >= 0)
992 cur->isconst &= ~(1<<hr);
57871462 993}
994
9de8a0c3 995static int is_const(const struct regstat *cur, signed char reg)
57871462 996{
997 int hr;
9de8a0c3 998 if (reg < 0) return 0;
999 if (!reg) return 1;
1000 hr = get_reg(cur->regmap, reg);
1001 if (hr >= 0)
1002 return (cur->isconst>>hr)&1;
57871462 1003 return 0;
1004}
40fca85b 1005
9de8a0c3 1006static uint32_t get_const(const struct regstat *cur, signed char reg)
57871462 1007{
1008 int hr;
9de8a0c3 1009 if (!reg) return 0;
1010 hr = get_reg(cur->regmap, reg);
1011 if (hr >= 0)
1012 return current_constmap[hr];
1013
1014 SysPrintf("Unknown constant in r%d\n", reg);
7c3a5182 1015 abort();
57871462 1016}
1017
1018// Least soon needed registers
1019// Look at the next ten instructions and see which registers
1020// will be used. Try not to reallocate these.
90f98e7c 1021static void lsn(u_char hsn[], int i)
57871462 1022{
1023 int j;
1024 int b=-1;
1025 for(j=0;j<9;j++)
1026 {
1027 if(i+j>=slen) {
1028 j=slen-i-1;
1029 break;
1030 }
fe807a8a 1031 if (dops[i+j].is_ujump)
57871462 1032 {
1033 // Don't go past an unconditonal jump
1034 j++;
1035 break;
1036 }
1037 }
1038 for(;j>=0;j--)
1039 {
cf95b4f0 1040 if(dops[i+j].rs1) hsn[dops[i+j].rs1]=j;
1041 if(dops[i+j].rs2) hsn[dops[i+j].rs2]=j;
1042 if(dops[i+j].rt1) hsn[dops[i+j].rt1]=j;
1043 if(dops[i+j].rt2) hsn[dops[i+j].rt2]=j;
1044 if(dops[i+j].itype==STORE || dops[i+j].itype==STORELR) {
57871462 1045 // Stores can allocate zero
cf95b4f0 1046 hsn[dops[i+j].rs1]=j;
1047 hsn[dops[i+j].rs2]=j;
57871462 1048 }
37387d8b 1049 if (ram_offset && (dops[i+j].is_load || dops[i+j].is_store))
1050 hsn[ROREG] = j;
57871462 1051 // On some architectures stores need invc_ptr
1052 #if defined(HOST_IMM8)
37387d8b 1053 if (dops[i+j].is_store)
1054 hsn[INVCP] = j;
57871462 1055 #endif
cf95b4f0 1056 if(i+j>=0&&(dops[i+j].itype==UJUMP||dops[i+j].itype==CJUMP||dops[i+j].itype==SJUMP))
57871462 1057 {
1058 hsn[CCREG]=j;
1059 b=j;
1060 }
1061 }
1062 if(b>=0)
1063 {
277718fa 1064 if(cinfo[i+b].ba>=start && cinfo[i+b].ba<(start+slen*4))
57871462 1065 {
1066 // Follow first branch
277718fa 1067 int t=(cinfo[i+b].ba-start)>>2;
57871462 1068 j=7-b;if(t+j>=slen) j=slen-t-1;
1069 for(;j>=0;j--)
1070 {
cf95b4f0 1071 if(dops[t+j].rs1) if(hsn[dops[t+j].rs1]>j+b+2) hsn[dops[t+j].rs1]=j+b+2;
1072 if(dops[t+j].rs2) if(hsn[dops[t+j].rs2]>j+b+2) hsn[dops[t+j].rs2]=j+b+2;
1073 //if(dops[t+j].rt1) if(hsn[dops[t+j].rt1]>j+b+2) hsn[dops[t+j].rt1]=j+b+2;
1074 //if(dops[t+j].rt2) if(hsn[dops[t+j].rt2]>j+b+2) hsn[dops[t+j].rt2]=j+b+2;
57871462 1075 }
1076 }
1077 // TODO: preferred register based on backward branch
1078 }
1079 // Delay slot should preferably not overwrite branch conditions or cycle count
fe807a8a 1080 if (i > 0 && dops[i-1].is_jump) {
cf95b4f0 1081 if(dops[i-1].rs1) if(hsn[dops[i-1].rs1]>1) hsn[dops[i-1].rs1]=1;
1082 if(dops[i-1].rs2) if(hsn[dops[i-1].rs2]>1) hsn[dops[i-1].rs2]=1;
57871462 1083 hsn[CCREG]=1;
1084 // ...or hash tables
1085 hsn[RHASH]=1;
1086 hsn[RHTBL]=1;
1087 }
1088 // Coprocessor load/store needs FTEMP, even if not declared
37387d8b 1089 if(dops[i].itype==C2LS) {
57871462 1090 hsn[FTEMP]=0;
1091 }
33a1eda1 1092 // Load/store L/R also uses FTEMP as a temporary register
1093 if (dops[i].itype == LOADLR || dops[i].itype == STORELR) {
57871462 1094 hsn[FTEMP]=0;
1095 }
57871462 1096 // Don't remove the miniht registers
cf95b4f0 1097 if(dops[i].itype==UJUMP||dops[i].itype==RJUMP)
57871462 1098 {
1099 hsn[RHASH]=0;
1100 hsn[RHTBL]=0;
1101 }
1102}
1103
1104// We only want to allocate registers if we're going to use them again soon
4149788d 1105static int needed_again(int r, int i)
57871462 1106{
1107 int j;
1108 int b=-1;
1109 int rn=10;
9f51b4b9 1110
fe807a8a 1111 if (i > 0 && dops[i-1].is_ujump)
57871462 1112 {
277718fa 1113 if(cinfo[i-1].ba<start || cinfo[i-1].ba>start+slen*4-4)
57871462 1114 return 0; // Don't need any registers if exiting the block
1115 }
1116 for(j=0;j<9;j++)
1117 {
1118 if(i+j>=slen) {
1119 j=slen-i-1;
1120 break;
1121 }
fe807a8a 1122 if (dops[i+j].is_ujump)
57871462 1123 {
1124 // Don't go past an unconditonal jump
1125 j++;
1126 break;
1127 }
a5cd72d0 1128 if (dops[i+j].is_exception)
57871462 1129 {
1130 break;
1131 }
1132 }
1133 for(;j>=1;j--)
1134 {
cf95b4f0 1135 if(dops[i+j].rs1==r) rn=j;
1136 if(dops[i+j].rs2==r) rn=j;
57871462 1137 if((unneeded_reg[i+j]>>r)&1) rn=10;
cf95b4f0 1138 if(i+j>=0&&(dops[i+j].itype==UJUMP||dops[i+j].itype==CJUMP||dops[i+j].itype==SJUMP))
57871462 1139 {
1140 b=j;
1141 }
1142 }
b7217e13 1143 if(rn<10) return 1;
581335b0 1144 (void)b;
57871462 1145 return 0;
1146}
1147
1148// Try to match register allocations at the end of a loop with those
1149// at the beginning
4149788d 1150static int loop_reg(int i, int r, int hr)
57871462 1151{
1152 int j,k;
1153 for(j=0;j<9;j++)
1154 {
1155 if(i+j>=slen) {
1156 j=slen-i-1;
1157 break;
1158 }
fe807a8a 1159 if (dops[i+j].is_ujump)
57871462 1160 {
1161 // Don't go past an unconditonal jump
1162 j++;
1163 break;
1164 }
1165 }
1166 k=0;
1167 if(i>0){
cf95b4f0 1168 if(dops[i-1].itype==UJUMP||dops[i-1].itype==CJUMP||dops[i-1].itype==SJUMP)
57871462 1169 k--;
1170 }
1171 for(;k<j;k++)
1172 {
00fa9369 1173 assert(r < 64);
1174 if((unneeded_reg[i+k]>>r)&1) return hr;
cf95b4f0 1175 if(i+k>=0&&(dops[i+k].itype==UJUMP||dops[i+k].itype==CJUMP||dops[i+k].itype==SJUMP))
57871462 1176 {
277718fa 1177 if(cinfo[i+k].ba>=start && cinfo[i+k].ba<(start+i*4))
57871462 1178 {
277718fa 1179 int t=(cinfo[i+k].ba-start)>>2;
57871462 1180 int reg=get_reg(regs[t].regmap_entry,r);
1181 if(reg>=0) return reg;
1182 //reg=get_reg(regs[t+1].regmap_entry,r);
1183 //if(reg>=0) return reg;
1184 }
1185 }
1186 }
1187 return hr;
1188}
1189
1190
1191// Allocate every register, preserving source/target regs
4149788d 1192static void alloc_all(struct regstat *cur,int i)
57871462 1193{
1194 int hr;
9f51b4b9 1195
57871462 1196 for(hr=0;hr<HOST_REGS;hr++) {
1197 if(hr!=EXCLUDE_REG) {
9de8a0c3 1198 if((cur->regmap[hr]!=dops[i].rs1)&&(cur->regmap[hr]!=dops[i].rs2)&&
1199 (cur->regmap[hr]!=dops[i].rt1)&&(cur->regmap[hr]!=dops[i].rt2))
57871462 1200 {
1201 cur->regmap[hr]=-1;
1202 cur->dirty&=~(1<<hr);
1203 }
1204 // Don't need zeros
9de8a0c3 1205 if(cur->regmap[hr]==0)
57871462 1206 {
1207 cur->regmap[hr]=-1;
1208 cur->dirty&=~(1<<hr);
1209 }
1210 }
1211 }
1212}
1213
d1e4ebd9 1214#ifndef NDEBUG
1215static int host_tempreg_in_use;
1216
1217static void host_tempreg_acquire(void)
1218{
1219 assert(!host_tempreg_in_use);
1220 host_tempreg_in_use = 1;
1221}
1222
1223static void host_tempreg_release(void)
1224{
1225 host_tempreg_in_use = 0;
1226}
1227#else
1228static void host_tempreg_acquire(void) {}
1229static void host_tempreg_release(void) {}
1230#endif
1231
32631e6a 1232#ifdef ASSEM_PRINT
8062d65a 1233extern void gen_interupt();
1234extern void do_insn_cmp();
d1e4ebd9 1235#define FUNCNAME(f) { f, " " #f }
8062d65a 1236static const struct {
d1e4ebd9 1237 void *addr;
8062d65a 1238 const char *name;
1239} function_names[] = {
1240 FUNCNAME(cc_interrupt),
1241 FUNCNAME(gen_interupt),
104df9d3 1242 FUNCNAME(ndrc_get_addr_ht),
8062d65a 1243 FUNCNAME(jump_handler_read8),
1244 FUNCNAME(jump_handler_read16),
1245 FUNCNAME(jump_handler_read32),
1246 FUNCNAME(jump_handler_write8),
1247 FUNCNAME(jump_handler_write16),
1248 FUNCNAME(jump_handler_write32),
9b495f6e 1249 FUNCNAME(ndrc_write_invalidate_one),
1250 FUNCNAME(ndrc_write_invalidate_many),
3968e69e 1251 FUNCNAME(jump_to_new_pc),
d1150cd6 1252 FUNCNAME(jump_break),
1253 FUNCNAME(jump_break_ds),
1254 FUNCNAME(jump_syscall),
1255 FUNCNAME(jump_syscall_ds),
a5cd72d0 1256 FUNCNAME(jump_overflow),
1257 FUNCNAME(jump_overflow_ds),
277718fa 1258 FUNCNAME(jump_addrerror),
1259 FUNCNAME(jump_addrerror_ds),
81dbbf4c 1260 FUNCNAME(call_gteStall),
8062d65a 1261 FUNCNAME(new_dyna_leave),
1262 FUNCNAME(pcsx_mtc0),
1263 FUNCNAME(pcsx_mtc0_ds),
277718fa 1264 FUNCNAME(execI),
1265#ifdef __aarch64__
1266 FUNCNAME(do_memhandler_pre),
1267 FUNCNAME(do_memhandler_post),
1268#endif
32631e6a 1269#ifdef DRC_DBG
33a1eda1 1270# ifdef __aarch64__
1271 FUNCNAME(do_insn_cmp_arm64),
1272# else
8062d65a 1273 FUNCNAME(do_insn_cmp),
33a1eda1 1274# endif
32631e6a 1275#endif
8062d65a 1276};
1277
d1e4ebd9 1278static const char *func_name(const void *a)
8062d65a 1279{
1280 int i;
1281 for (i = 0; i < sizeof(function_names)/sizeof(function_names[0]); i++)
1282 if (function_names[i].addr == a)
1283 return function_names[i].name;
1284 return "";
1285}
a5cd72d0 1286
1287static const char *fpofs_name(u_int ofs)
1288{
1289 u_int *p = (u_int *)&dynarec_local + ofs/sizeof(u_int);
1290 static char buf[64];
1291 switch (ofs) {
1292 #define ofscase(x) case LO_##x: return " ; " #x
1293 ofscase(next_interupt);
de6dbc52 1294 ofscase(cycle_count);
a5cd72d0 1295 ofscase(last_count);
1296 ofscase(pending_exception);
1297 ofscase(stop);
1298 ofscase(address);
1299 ofscase(lo);
1300 ofscase(hi);
1301 ofscase(PC);
1302 ofscase(cycle);
1303 ofscase(mem_rtab);
1304 ofscase(mem_wtab);
1305 ofscase(psxH_ptr);
1306 ofscase(invc_ptr);
1307 ofscase(ram_offset);
1308 #undef ofscase
1309 }
1310 buf[0] = 0;
1311 if (psxRegs.GPR.r <= p && p < &psxRegs.GPR.r[32])
1312 snprintf(buf, sizeof(buf), " ; r%d", (int)(p - psxRegs.GPR.r));
1313 else if (psxRegs.CP0.r <= p && p < &psxRegs.CP0.r[32])
1314 snprintf(buf, sizeof(buf), " ; cp0 $%d", (int)(p - psxRegs.CP0.r));
1315 else if (psxRegs.CP2D.r <= p && p < &psxRegs.CP2D.r[32])
1316 snprintf(buf, sizeof(buf), " ; cp2d $%d", (int)(p - psxRegs.CP2D.r));
1317 else if (psxRegs.CP2C.r <= p && p < &psxRegs.CP2C.r[32])
1318 snprintf(buf, sizeof(buf), " ; cp2c $%d", (int)(p - psxRegs.CP2C.r));
1319 return buf;
1320}
8062d65a 1321#else
1322#define func_name(x) ""
a5cd72d0 1323#define fpofs_name(x) ""
8062d65a 1324#endif
1325
57871462 1326#ifdef __i386__
1327#include "assem_x86.c"
1328#endif
1329#ifdef __x86_64__
1330#include "assem_x64.c"
1331#endif
1332#ifdef __arm__
1333#include "assem_arm.c"
1334#endif
be516ebe 1335#ifdef __aarch64__
1336#include "assem_arm64.c"
1337#endif
57871462 1338
2a014d73 1339static void *get_trampoline(const void *f)
1340{
d9e2b173 1341 struct ndrc_tramp *tramp = NDRC_WRITE_OFFSET(&ndrc->tramp);
2a014d73 1342 size_t i;
1343
d9e2b173 1344 for (i = 0; i < ARRAY_SIZE(tramp->f); i++) {
1345 if (tramp->f[i] == f || tramp->f[i] == NULL)
2a014d73 1346 break;
1347 }
d9e2b173 1348 if (i == ARRAY_SIZE(tramp->f)) {
2a014d73 1349 SysPrintf("trampoline table is full, last func %p\n", f);
1350 abort();
1351 }
d9e2b173 1352 if (tramp->f[i] == NULL) {
1353 start_tcache_write(&tramp->f[i], &tramp->f[i + 1]);
1354 tramp->f[i] = f;
1355 end_tcache_write(&tramp->f[i], &tramp->f[i + 1]);
1356#ifdef HAVE_LIBNX
1357 // invalidate the RX mirror (unsure if necessary, but just in case...)
1358 armDCacheFlush(&ndrc->tramp.f[i], sizeof(ndrc->tramp.f[i]));
1359#endif
2a014d73 1360 }
1361 return &ndrc->tramp.ops[i];
1362}
1363
1364static void emit_far_jump(const void *f)
1365{
1366 if (can_jump_or_call(f)) {
1367 emit_jmp(f);
1368 return;
1369 }
1370
1371 f = get_trampoline(f);
1372 emit_jmp(f);
1373}
1374
1375static void emit_far_call(const void *f)
1376{
1377 if (can_jump_or_call(f)) {
1378 emit_call(f);
1379 return;
1380 }
1381
1382 f = get_trampoline(f);
1383 emit_call(f);
1384}
1385
57871462 1386// Check if an address is already compiled
1387// but don't return addresses which are about to expire from the cache
4149788d 1388static void *check_addr(u_int vaddr)
57871462 1389{
df4dc2b1 1390 struct ht_entry *ht_bin = hash_table_get(vaddr);
1391 size_t i;
b14b6a8f 1392 for (i = 0; i < ARRAY_SIZE(ht_bin->vaddr); i++) {
df4dc2b1 1393 if (ht_bin->vaddr[i] == vaddr)
93c0345b 1394 if (doesnt_expire_soon(ht_bin->tcaddr[i]))
104df9d3 1395 return ht_bin->tcaddr[i];
57871462 1396 }
104df9d3 1397
1398 // refactor to get_addr_nocompile?
1399 u_int start_page = get_page_prev(vaddr);
1400 u_int page, end_page = get_page(vaddr);
1401
1402 stat_inc(stat_jump_in_lookups);
1403 for (page = start_page; page <= end_page; page++) {
1404 const struct block_info *block;
1405 for (block = blocks[page]; block != NULL; block = block->next) {
1406 if (vaddr < block->start)
1407 break;
1408 if (block->is_dirty || vaddr >= block->start + block->len)
1409 continue;
1410 if (!doesnt_expire_soon(ndrc->translation_cache + block->tc_offs))
1411 continue;
1412 for (i = 0; i < block->jump_in_cnt; i++)
1413 if (block->jump_in[i].vaddr == vaddr)
1414 break;
1415 if (i == block->jump_in_cnt)
1416 continue;
1417
1418 // Update existing entry with current address
1419 void *addr = block->jump_in[i].addr;
1420 if (ht_bin->vaddr[0] == vaddr) {
1421 ht_bin->tcaddr[0] = addr;
1422 return addr;
1423 }
1424 if (ht_bin->vaddr[1] == vaddr) {
1425 ht_bin->tcaddr[1] = addr;
1426 return addr;
1427 }
1428 // Insert into hash table with low priority.
1429 // Don't evict existing entries, as they are probably
1430 // addresses that are being accessed frequently.
1431 if (ht_bin->vaddr[0] == -1) {
1432 ht_bin->vaddr[0] = vaddr;
1433 ht_bin->tcaddr[0] = addr;
57871462 1434 }
104df9d3 1435 else if (ht_bin->vaddr[1] == -1) {
1436 ht_bin->vaddr[1] = vaddr;
1437 ht_bin->tcaddr[1] = addr;
1438 }
1439 return addr;
57871462 1440 }
57871462 1441 }
104df9d3 1442 return NULL;
57871462 1443}
1444
104df9d3 1445static void blocks_clear(struct block_info **head)
1446{
1447 struct block_info *cur, *next;
1448
1449 if ((cur = *head)) {
1450 *head = NULL;
1451 while (cur) {
1452 next = cur->next;
1453 free(cur);
1454 cur = next;
1455 }
1456 }
1457}
1458
93c0345b 1459static int blocks_remove_matching_addrs(struct block_info **head,
1460 u_int base_offs, int shift)
104df9d3 1461{
1462 struct block_info *next;
93c0345b 1463 int hit = 0;
104df9d3 1464 while (*head) {
93c0345b 1465 if ((((*head)->tc_offs ^ base_offs) >> shift) == 0) {
9b495f6e 1466 inv_debug("EXP: rm block %08x (tc_offs %x)\n", (*head)->start, (*head)->tc_offs);
104df9d3 1467 invalidate_block(*head);
1468 next = (*head)->next;
1469 free(*head);
1470 *head = next;
1471 stat_dec(stat_blocks);
93c0345b 1472 hit = 1;
104df9d3 1473 }
1474 else
1475 {
1476 head = &((*head)->next);
1477 }
1478 }
93c0345b 1479 return hit;
104df9d3 1480}
57871462 1481
1482// This is called when we write to a compiled block (see do_invstub)
b7ad2f2c 1483static void unlink_jumps_vaddr_range(u_int start, u_int end)
57871462 1484{
104df9d3 1485 u_int page, start_page = get_page(start), end_page = get_page(end - 1);
b7ad2f2c 1486 int i;
104df9d3 1487
1488 for (page = start_page; page <= end_page; page++) {
b7ad2f2c 1489 struct jump_info *ji = jumps[page];
1490 if (ji == NULL)
1491 continue;
1492 for (i = 0; i < ji->count; ) {
1493 if (ji->e[i].target_vaddr < start || ji->e[i].target_vaddr >= end) {
1494 i++;
104df9d3 1495 continue;
1496 }
b7ad2f2c 1497
1498 inv_debug("INV: rm link to %08x (tc_offs %zx)\n", ji->e[i].target_vaddr,
1499 (u_char *)ji->e[i].stub - ndrc->translation_cache);
1500 void *host_addr = find_extjump_insn(ji->e[i].stub);
104df9d3 1501 mark_clear_cache(host_addr);
b7ad2f2c 1502 set_jump_target(host_addr, ji->e[i].stub); // point back to dyna_linker stub
104df9d3 1503
104df9d3 1504 stat_dec(stat_links);
b7ad2f2c 1505 ji->count--;
1506 if (i < ji->count) {
1507 ji->e[i] = ji->e[ji->count];
1508 continue;
1509 }
1510 i++;
1511 }
1512 }
1513}
1514
1515static void unlink_jumps_tc_range(struct jump_info *ji, u_int base_offs, int shift)
1516{
1517 int i;
1518 if (ji == NULL)
1519 return;
1520 for (i = 0; i < ji->count; ) {
1521 u_int tc_offs = (u_char *)ji->e[i].stub - ndrc->translation_cache;
1522 if (((tc_offs ^ base_offs) >> shift) != 0) {
1523 i++;
1524 continue;
1525 }
1526
9b495f6e 1527 inv_debug("EXP: rm link to %08x (tc_offs %x)\n", ji->e[i].target_vaddr, tc_offs);
b7ad2f2c 1528 stat_dec(stat_links);
1529 ji->count--;
1530 if (i < ji->count) {
1531 ji->e[i] = ji->e[ji->count];
1532 continue;
104df9d3 1533 }
b7ad2f2c 1534 i++;
57871462 1535 }
104df9d3 1536}
9f51b4b9 1537
104df9d3 1538static void invalidate_block(struct block_info *block)
1539{
1540 u_int i;
f76eeef9 1541
104df9d3 1542 block->is_dirty = 1;
b7ad2f2c 1543 unlink_jumps_vaddr_range(block->start, block->start + block->len);
104df9d3 1544 for (i = 0; i < block->jump_in_cnt; i++)
1545 hash_table_remove(block->jump_in[i].vaddr);
57871462 1546}
9be4ba64 1547
104df9d3 1548static int invalidate_range(u_int start, u_int end,
1549 u32 *inv_start_ret, u32 *inv_end_ret)
9be4ba64 1550{
3280e616 1551 struct block_info *last_block = NULL;
104df9d3 1552 u_int start_page = get_page_prev(start);
1553 u_int end_page = get_page(end - 1);
1554 u_int start_m = pmmask(start);
ab4377be 1555 u_int end_m = pmmask(end - 1);
104df9d3 1556 u_int inv_start, inv_end;
1557 u_int blk_start_m, blk_end_m;
1558 u_int page;
1559 int hit = 0;
1560
1561 // additional area without code (to supplement invalid_code[]), [start, end)
9b495f6e 1562 // avoids excessive ndrc_write_invalidate*() calls
104df9d3 1563 inv_start = start_m & ~0xfff;
1564 inv_end = end_m | 0xfff;
1565
1566 for (page = start_page; page <= end_page; page++) {
1567 struct block_info *block;
1568 for (block = blocks[page]; block != NULL; block = block->next) {
1569 if (block->is_dirty)
1570 continue;
3280e616 1571 last_block = block;
104df9d3 1572 blk_end_m = pmmask(block->start + block->len);
1573 if (blk_end_m <= start_m) {
1574 inv_start = max(inv_start, blk_end_m);
1575 continue;
1576 }
1577 blk_start_m = pmmask(block->start);
1578 if (end_m <= blk_start_m) {
1579 inv_end = min(inv_end, blk_start_m - 1);
1580 continue;
9be4ba64 1581 }
104df9d3 1582 if (!block->source) // "hack" block - leave it alone
1583 continue;
1584
1585 hit++;
1586 invalidate_block(block);
1587 stat_inc(stat_inv_hits);
9be4ba64 1588 }
9be4ba64 1589 }
104df9d3 1590
3280e616 1591 if (!hit && last_block && last_block->source) {
1592 // could be some leftover unused block, uselessly trapping writes
1593 last_block->inv_near_misses++;
1594 if (last_block->inv_near_misses > 128) {
1595 invalidate_block(last_block);
1596 stat_inc(stat_inv_hits);
1597 hit++;
1598 }
1599 }
104df9d3 1600 if (hit) {
1601 do_clear_cache();
04714958 1602 mini_ht_clear();
104df9d3 1603 }
3280e616 1604
104df9d3 1605 if (inv_start <= (start_m & ~0xfff) && inv_end >= (start_m | 0xfff))
1606 // the whole page is empty now
1607 mark_invalid_code(start, 1, 1);
1608
1609 if (inv_start_ret) *inv_start_ret = inv_start | (start & 0xe0000000);
1610 if (inv_end_ret) *inv_end_ret = inv_end | (end & 0xe0000000);
1611 return hit;
9be4ba64 1612}
1613
104df9d3 1614void new_dynarec_invalidate_range(unsigned int start, unsigned int end)
1615{
1616 invalidate_range(start, end, NULL, NULL);
1617}
1618
9b495f6e 1619static void ndrc_write_invalidate_many(u_int start, u_int end)
57871462 1620{
9be4ba64 1621 // this check is done by the caller
1622 //if (inv_code_start<=addr&&addr<=inv_code_end) { rhits++; return; }
9b495f6e 1623 int ret = invalidate_range(start, end, &inv_code_start, &inv_code_end);
1624#ifdef INV_DEBUG_W
1625 int invc = invalid_code[start >> 12];
1626 u_int len = end - start;
104df9d3 1627 if (ret)
9b495f6e 1628 printf("INV ADDR: %08x/%02x hit %d blocks\n", start, len, ret);
104df9d3 1629 else
9b495f6e 1630 printf("INV ADDR: %08x/%02x miss, inv %08x-%08x invc %d->%d\n", start, len,
1631 inv_code_start, inv_code_end, invc, invalid_code[start >> 12]);
1632 check_for_block_changes(start, end);
1633#endif
ece032e6 1634 stat_inc(stat_inv_addr_calls);
9b495f6e 1635 (void)ret;
1636}
1637
1638void ndrc_write_invalidate_one(u_int addr)
1639{
1640 ndrc_write_invalidate_many(addr, addr + 4);
57871462 1641}
9be4ba64 1642
dd3a91a1 1643// This is called when loading a save state.
1644// Anything could have changed, so invalidate everything.
104df9d3 1645void new_dynarec_invalidate_all_pages(void)
57871462 1646{
104df9d3 1647 struct block_info *block;
581335b0 1648 u_int page;
104df9d3 1649 for (page = 0; page < ARRAY_SIZE(blocks); page++) {
1650 for (block = blocks[page]; block != NULL; block = block->next) {
1651 if (block->is_dirty)
1652 continue;
1653 if (!block->source) // hack block?
1654 continue;
1655 invalidate_block(block);
1656 }
1657 }
1658
919981d0 1659 do_clear_cache();
04714958 1660 mini_ht_clear();
57871462 1661}
1662
1663// Add an entry to jump_out after making a link
104df9d3 1664// src should point to code by emit_extjump()
b7ad2f2c 1665void ndrc_add_jump_out(u_int vaddr, void *src)
57871462 1666{
b7ad2f2c 1667 inv_debug("ndrc_add_jump_out: %p -> %x\n", src, vaddr);
1668 u_int page = get_page(vaddr);
1669 struct jump_info *ji;
1670
104df9d3 1671 stat_inc(stat_links);
b7ad2f2c 1672 check_extjump2(src);
1673 ji = jumps[page];
1674 if (ji == NULL) {
1675 ji = malloc(sizeof(*ji) + sizeof(ji->e[0]) * 16);
1676 ji->alloc = 16;
1677 ji->count = 0;
1678 }
1679 else if (ji->count >= ji->alloc) {
1680 ji->alloc += 16;
1681 ji = realloc(ji, sizeof(*ji) + sizeof(ji->e[0]) * ji->alloc);
1682 }
1683 jumps[page] = ji;
1684 ji->e[ji->count].target_vaddr = vaddr;
1685 ji->e[ji->count].stub = src;
1686 ji->count++;
57871462 1687}
1688
8062d65a 1689/* Register allocation */
1690
90f98e7c 1691static void alloc_set(struct regstat *cur, int reg, int hr)
1692{
1693 cur->regmap[hr] = reg;
1694 cur->dirty &= ~(1u << hr);
1695 cur->isconst &= ~(1u << hr);
1696 cur->noevict |= 1u << hr;
1697}
1698
1699static void evict_alloc_reg(struct regstat *cur, int i, int reg, int preferred_hr)
1700{
1701 u_char hsn[MAXREG+1];
1702 int j, r, hr;
1703 memset(hsn, 10, sizeof(hsn));
1704 lsn(hsn, i);
1705 //printf("hsn(%x): %d %d %d %d %d %d %d\n",start+i*4,hsn[cur->regmap[0]&63],hsn[cur->regmap[1]&63],hsn[cur->regmap[2]&63],hsn[cur->regmap[3]&63],hsn[cur->regmap[5]&63],hsn[cur->regmap[6]&63],hsn[cur->regmap[7]&63]);
1706 if(i>0) {
1707 // Don't evict the cycle count at entry points, otherwise the entry
1708 // stub will have to write it.
1709 if(dops[i].bt&&hsn[CCREG]>2) hsn[CCREG]=2;
1710 if (i>1 && hsn[CCREG] > 2 && dops[i-2].is_jump) hsn[CCREG]=2;
1711 for(j=10;j>=3;j--)
1712 {
1713 // Alloc preferred register if available
1714 if (!((cur->noevict >> preferred_hr) & 1)
1715 && hsn[cur->regmap[preferred_hr]] == j)
1716 {
1717 alloc_set(cur, reg, preferred_hr);
1718 return;
1719 }
1720 for(r=1;r<=MAXREG;r++)
1721 {
1722 if(hsn[r]==j&&r!=dops[i-1].rs1&&r!=dops[i-1].rs2&&r!=dops[i-1].rt1&&r!=dops[i-1].rt2) {
1723 for(hr=0;hr<HOST_REGS;hr++) {
1724 if (hr == EXCLUDE_REG || ((cur->noevict >> hr) & 1))
1725 continue;
1726 if(hr!=HOST_CCREG||j<hsn[CCREG]) {
1727 if(cur->regmap[hr]==r) {
1728 alloc_set(cur, reg, hr);
1729 return;
1730 }
1731 }
1732 }
1733 }
1734 }
1735 }
1736 }
1737 for(j=10;j>=0;j--)
1738 {
1739 for(r=1;r<=MAXREG;r++)
1740 {
1741 if(hsn[r]==j) {
1742 for(hr=0;hr<HOST_REGS;hr++) {
1743 if (hr == EXCLUDE_REG || ((cur->noevict >> hr) & 1))
1744 continue;
1745 if(cur->regmap[hr]==r) {
1746 alloc_set(cur, reg, hr);
1747 return;
1748 }
1749 }
1750 }
1751 }
1752 }
1753 SysPrintf("This shouldn't happen (evict_alloc_reg)\n");
1754 abort();
1755}
1756
8062d65a 1757// Note: registers are allocated clean (unmodified state)
1758// if you intend to modify the register, you must call dirty_reg().
1759static void alloc_reg(struct regstat *cur,int i,signed char reg)
1760{
1761 int r,hr;
b7ec323c 1762 int preferred_reg = PREFERRED_REG_FIRST
1763 + reg % (PREFERRED_REG_LAST - PREFERRED_REG_FIRST + 1);
1764 if (reg == CCREG) preferred_reg = HOST_CCREG;
1765 if (reg == PTEMP || reg == FTEMP) preferred_reg = 12;
1766 assert(PREFERRED_REG_FIRST != EXCLUDE_REG && EXCLUDE_REG != HOST_REGS);
53358c1d 1767 assert(reg >= 0);
8062d65a 1768
1769 // Don't allocate unused registers
1770 if((cur->u>>reg)&1) return;
1771
1772 // see if it's already allocated
90f98e7c 1773 if ((hr = get_reg(cur->regmap, reg)) >= 0) {
1774 cur->noevict |= 1u << hr;
53358c1d 1775 return;
90f98e7c 1776 }
8062d65a 1777
1778 // Keep the same mapping if the register was already allocated in a loop
1779 preferred_reg = loop_reg(i,reg,preferred_reg);
1780
1781 // Try to allocate the preferred register
90f98e7c 1782 if (cur->regmap[preferred_reg] == -1) {
1783 alloc_set(cur, reg, preferred_reg);
8062d65a 1784 return;
1785 }
1786 r=cur->regmap[preferred_reg];
1787 assert(r < 64);
1788 if((cur->u>>r)&1) {
90f98e7c 1789 alloc_set(cur, reg, preferred_reg);
8062d65a 1790 return;
1791 }
1792
1793 // Clear any unneeded registers
1794 // We try to keep the mapping consistent, if possible, because it
1795 // makes branches easier (especially loops). So we try to allocate
1796 // first (see above) before removing old mappings. If this is not
1797 // possible then go ahead and clear out the registers that are no
1798 // longer needed.
1799 for(hr=0;hr<HOST_REGS;hr++)
1800 {
1801 r=cur->regmap[hr];
1802 if(r>=0) {
1803 assert(r < 64);
1804 if((cur->u>>r)&1) {cur->regmap[hr]=-1;break;}
1805 }
1806 }
b7ec323c 1807
8062d65a 1808 // Try to allocate any available register, but prefer
1809 // registers that have not been used recently.
b7ec323c 1810 if (i > 0) {
1811 for (hr = PREFERRED_REG_FIRST; ; ) {
1812 if (cur->regmap[hr] < 0) {
1813 int oldreg = regs[i-1].regmap[hr];
1814 if (oldreg < 0 || (oldreg != dops[i-1].rs1 && oldreg != dops[i-1].rs2
1815 && oldreg != dops[i-1].rt1 && oldreg != dops[i-1].rt2))
1816 {
90f98e7c 1817 alloc_set(cur, reg, hr);
8062d65a 1818 return;
1819 }
1820 }
b7ec323c 1821 hr++;
1822 if (hr == EXCLUDE_REG)
1823 hr++;
1824 if (hr == HOST_REGS)
1825 hr = 0;
1826 if (hr == PREFERRED_REG_FIRST)
1827 break;
8062d65a 1828 }
1829 }
b7ec323c 1830
8062d65a 1831 // Try to allocate any available register
b7ec323c 1832 for (hr = PREFERRED_REG_FIRST; ; ) {
1833 if (cur->regmap[hr] < 0) {
90f98e7c 1834 alloc_set(cur, reg, hr);
8062d65a 1835 return;
1836 }
b7ec323c 1837 hr++;
1838 if (hr == EXCLUDE_REG)
1839 hr++;
1840 if (hr == HOST_REGS)
1841 hr = 0;
1842 if (hr == PREFERRED_REG_FIRST)
1843 break;
8062d65a 1844 }
1845
1846 // Ok, now we have to evict someone
1847 // Pick a register we hopefully won't need soon
90f98e7c 1848 evict_alloc_reg(cur, i, reg, preferred_reg);
8062d65a 1849}
1850
1851// Allocate a temporary register. This is done without regard to
1852// dirty status or whether the register we request is on the unneeded list
1853// Note: This will only allocate one register, even if called multiple times
1854static void alloc_reg_temp(struct regstat *cur,int i,signed char reg)
1855{
1856 int r,hr;
8062d65a 1857
1858 // see if it's already allocated
90f98e7c 1859 for (hr = 0; hr < HOST_REGS; hr++)
8062d65a 1860 {
90f98e7c 1861 if (hr != EXCLUDE_REG && cur->regmap[hr] == reg) {
1862 cur->noevict |= 1u << hr;
1863 return;
1864 }
8062d65a 1865 }
1866
1867 // Try to allocate any available register
1868 for(hr=HOST_REGS-1;hr>=0;hr--) {
1869 if(hr!=EXCLUDE_REG&&cur->regmap[hr]==-1) {
90f98e7c 1870 alloc_set(cur, reg, hr);
8062d65a 1871 return;
1872 }
1873 }
1874
1875 // Find an unneeded register
1876 for(hr=HOST_REGS-1;hr>=0;hr--)
1877 {
1878 r=cur->regmap[hr];
1879 if(r>=0) {
1880 assert(r < 64);
1881 if((cur->u>>r)&1) {
1882 if(i==0||((unneeded_reg[i-1]>>r)&1)) {
90f98e7c 1883 alloc_set(cur, reg, hr);
8062d65a 1884 return;
1885 }
1886 }
1887 }
1888 }
1889
1890 // Ok, now we have to evict someone
1891 // Pick a register we hopefully won't need soon
90f98e7c 1892 evict_alloc_reg(cur, i, reg, 0);
8062d65a 1893}
1894
ad49de89 1895static void mov_alloc(struct regstat *current,int i)
57871462 1896{
cf95b4f0 1897 if (dops[i].rs1 == HIREG || dops[i].rs1 == LOREG) {
9a3ccfeb 1898 alloc_cc(current,i); // for stalls
1899 dirty_reg(current,CCREG);
32631e6a 1900 }
1901
57871462 1902 // Note: Don't need to actually alloc the source registers
cf95b4f0 1903 //alloc_reg(current,i,dops[i].rs1);
1904 alloc_reg(current,i,dops[i].rt1);
ad49de89 1905
cf95b4f0 1906 clear_const(current,dops[i].rs1);
1907 clear_const(current,dops[i].rt1);
1908 dirty_reg(current,dops[i].rt1);
57871462 1909}
1910
ad49de89 1911static void shiftimm_alloc(struct regstat *current,int i)
57871462 1912{
cf95b4f0 1913 if(dops[i].opcode2<=0x3) // SLL/SRL/SRA
57871462 1914 {
cf95b4f0 1915 if(dops[i].rt1) {
1916 if(dops[i].rs1&&needed_again(dops[i].rs1,i)) alloc_reg(current,i,dops[i].rs1);
53dc27f6 1917 else dops[i].use_lt1=!!dops[i].rs1;
cf95b4f0 1918 alloc_reg(current,i,dops[i].rt1);
1919 dirty_reg(current,dops[i].rt1);
1920 if(is_const(current,dops[i].rs1)) {
1921 int v=get_const(current,dops[i].rs1);
277718fa 1922 if(dops[i].opcode2==0x00) set_const(current,dops[i].rt1,v<<cinfo[i].imm);
1923 if(dops[i].opcode2==0x02) set_const(current,dops[i].rt1,(u_int)v>>cinfo[i].imm);
1924 if(dops[i].opcode2==0x03) set_const(current,dops[i].rt1,v>>cinfo[i].imm);
dc49e339 1925 }
cf95b4f0 1926 else clear_const(current,dops[i].rt1);
57871462 1927 }
1928 }
dc49e339 1929 else
1930 {
cf95b4f0 1931 clear_const(current,dops[i].rs1);
1932 clear_const(current,dops[i].rt1);
dc49e339 1933 }
1934
cf95b4f0 1935 if(dops[i].opcode2>=0x38&&dops[i].opcode2<=0x3b) // DSLL/DSRL/DSRA
57871462 1936 {
9c45ca93 1937 assert(0);
57871462 1938 }
cf95b4f0 1939 if(dops[i].opcode2==0x3c) // DSLL32
57871462 1940 {
9c45ca93 1941 assert(0);
57871462 1942 }
cf95b4f0 1943 if(dops[i].opcode2==0x3e) // DSRL32
57871462 1944 {
9c45ca93 1945 assert(0);
57871462 1946 }
cf95b4f0 1947 if(dops[i].opcode2==0x3f) // DSRA32
57871462 1948 {
9c45ca93 1949 assert(0);
57871462 1950 }
1951}
1952
ad49de89 1953static void shift_alloc(struct regstat *current,int i)
57871462 1954{
cf95b4f0 1955 if(dops[i].rt1) {
cf95b4f0 1956 if(dops[i].rs1) alloc_reg(current,i,dops[i].rs1);
1957 if(dops[i].rs2) alloc_reg(current,i,dops[i].rs2);
1958 alloc_reg(current,i,dops[i].rt1);
1959 if(dops[i].rt1==dops[i].rs2) {
e1190b87 1960 alloc_reg_temp(current,i,-1);
277718fa 1961 cinfo[i].min_free_regs=1;
e1190b87 1962 }
cf95b4f0 1963 clear_const(current,dops[i].rs1);
1964 clear_const(current,dops[i].rs2);
1965 clear_const(current,dops[i].rt1);
1966 dirty_reg(current,dops[i].rt1);
57871462 1967 }
1968}
1969
ad49de89 1970static void alu_alloc(struct regstat *current,int i)
57871462 1971{
cf95b4f0 1972 if(dops[i].opcode2>=0x20&&dops[i].opcode2<=0x23) { // ADD/ADDU/SUB/SUBU
1973 if(dops[i].rt1) {
1974 if(dops[i].rs1&&dops[i].rs2) {
1975 alloc_reg(current,i,dops[i].rs1);
1976 alloc_reg(current,i,dops[i].rs2);
57871462 1977 }
1978 else {
cf95b4f0 1979 if(dops[i].rs1&&needed_again(dops[i].rs1,i)) alloc_reg(current,i,dops[i].rs1);
1980 if(dops[i].rs2&&needed_again(dops[i].rs2,i)) alloc_reg(current,i,dops[i].rs2);
57871462 1981 }
cf95b4f0 1982 alloc_reg(current,i,dops[i].rt1);
57871462 1983 }
277718fa 1984 if (dops[i].may_except) {
90f98e7c 1985 alloc_cc_optional(current, i); // for exceptions
277718fa 1986 alloc_reg_temp(current, i, -1);
1987 cinfo[i].min_free_regs = 1;
a5cd72d0 1988 }
57871462 1989 }
277718fa 1990 else if(dops[i].opcode2==0x2a||dops[i].opcode2==0x2b) { // SLT/SLTU
cf95b4f0 1991 if(dops[i].rt1) {
1992 alloc_reg(current,i,dops[i].rs1);
1993 alloc_reg(current,i,dops[i].rs2);
1994 alloc_reg(current,i,dops[i].rt1);
57871462 1995 }
57871462 1996 }
277718fa 1997 else if(dops[i].opcode2>=0x24&&dops[i].opcode2<=0x27) { // AND/OR/XOR/NOR
cf95b4f0 1998 if(dops[i].rt1) {
1999 if(dops[i].rs1&&dops[i].rs2) {
2000 alloc_reg(current,i,dops[i].rs1);
2001 alloc_reg(current,i,dops[i].rs2);
57871462 2002 }
2003 else
2004 {
cf95b4f0 2005 if(dops[i].rs1&&needed_again(dops[i].rs1,i)) alloc_reg(current,i,dops[i].rs1);
2006 if(dops[i].rs2&&needed_again(dops[i].rs2,i)) alloc_reg(current,i,dops[i].rs2);
57871462 2007 }
cf95b4f0 2008 alloc_reg(current,i,dops[i].rt1);
57871462 2009 }
2010 }
cf95b4f0 2011 clear_const(current,dops[i].rs1);
2012 clear_const(current,dops[i].rs2);
2013 clear_const(current,dops[i].rt1);
2014 dirty_reg(current,dops[i].rt1);
57871462 2015}
2016
ad49de89 2017static void imm16_alloc(struct regstat *current,int i)
57871462 2018{
cf95b4f0 2019 if(dops[i].rs1&&needed_again(dops[i].rs1,i)) alloc_reg(current,i,dops[i].rs1);
53dc27f6 2020 else dops[i].use_lt1=!!dops[i].rs1;
cf95b4f0 2021 if(dops[i].rt1) alloc_reg(current,i,dops[i].rt1);
a5cd72d0 2022 if(dops[i].opcode==0x0a||dops[i].opcode==0x0b) { // SLTI/SLTIU
cf95b4f0 2023 clear_const(current,dops[i].rs1);
2024 clear_const(current,dops[i].rt1);
57871462 2025 }
cf95b4f0 2026 else if(dops[i].opcode>=0x0c&&dops[i].opcode<=0x0e) { // ANDI/ORI/XORI
2027 if(is_const(current,dops[i].rs1)) {
2028 int v=get_const(current,dops[i].rs1);
277718fa 2029 if(dops[i].opcode==0x0c) set_const(current,dops[i].rt1,v&cinfo[i].imm);
2030 if(dops[i].opcode==0x0d) set_const(current,dops[i].rt1,v|cinfo[i].imm);
2031 if(dops[i].opcode==0x0e) set_const(current,dops[i].rt1,v^cinfo[i].imm);
57871462 2032 }
cf95b4f0 2033 else clear_const(current,dops[i].rt1);
57871462 2034 }
cf95b4f0 2035 else if(dops[i].opcode==0x08||dops[i].opcode==0x09) { // ADDI/ADDIU
2036 if(is_const(current,dops[i].rs1)) {
2037 int v=get_const(current,dops[i].rs1);
277718fa 2038 set_const(current,dops[i].rt1,v+cinfo[i].imm);
57871462 2039 }
cf95b4f0 2040 else clear_const(current,dops[i].rt1);
277718fa 2041 if (dops[i].may_except) {
90f98e7c 2042 alloc_cc_optional(current, i); // for exceptions
277718fa 2043 alloc_reg_temp(current, i, -1);
2044 cinfo[i].min_free_regs = 1;
a5cd72d0 2045 }
57871462 2046 }
2047 else {
277718fa 2048 set_const(current,dops[i].rt1,cinfo[i].imm<<16); // LUI
57871462 2049 }
cf95b4f0 2050 dirty_reg(current,dops[i].rt1);
57871462 2051}
2052
ad49de89 2053static void load_alloc(struct regstat *current,int i)
57871462 2054{
277718fa 2055 int need_temp = 0;
cf95b4f0 2056 clear_const(current,dops[i].rt1);
2057 //if(dops[i].rs1!=dops[i].rt1&&needed_again(dops[i].rs1,i)) clear_const(current,dops[i].rs1); // Does this help or hurt?
2058 if(!dops[i].rs1) current->u&=~1LL; // Allow allocating r0 if it's the source register
37387d8b 2059 if (needed_again(dops[i].rs1, i))
2060 alloc_reg(current, i, dops[i].rs1);
2061 if (ram_offset)
2062 alloc_reg(current, i, ROREG);
277718fa 2063 if (dops[i].may_except) {
90f98e7c 2064 alloc_cc_optional(current, i); // for exceptions
277718fa 2065 need_temp = 1;
2066 }
cf95b4f0 2067 if(dops[i].rt1&&!((current->u>>dops[i].rt1)&1)) {
2068 alloc_reg(current,i,dops[i].rt1);
a5cd72d0 2069 assert(get_reg_w(current->regmap, dops[i].rt1)>=0);
cf95b4f0 2070 dirty_reg(current,dops[i].rt1);
57871462 2071 // LWL/LWR need a temporary register for the old value
cf95b4f0 2072 if(dops[i].opcode==0x22||dops[i].opcode==0x26)
57871462 2073 {
2074 alloc_reg(current,i,FTEMP);
277718fa 2075 need_temp = 1;
57871462 2076 }
2077 }
2078 else
2079 {
373d1d07 2080 // Load to r0 or unneeded register (dummy load)
57871462 2081 // but we still need a register to calculate the address
cf95b4f0 2082 if(dops[i].opcode==0x22||dops[i].opcode==0x26)
535d208a 2083 alloc_reg(current,i,FTEMP); // LWL/LWR need another temporary
277718fa 2084 need_temp = 1;
2085 }
2086 if (need_temp) {
2087 alloc_reg_temp(current, i, -1);
2088 cinfo[i].min_free_regs = 1;
57871462 2089 }
2090}
2091
90f98e7c 2092// this may eat up to 7 registers
2093static void store_alloc(struct regstat *current, int i)
57871462 2094{
cf95b4f0 2095 clear_const(current,dops[i].rs2);
2096 if(!(dops[i].rs2)) current->u&=~1LL; // Allow allocating r0 if necessary
2097 if(needed_again(dops[i].rs1,i)) alloc_reg(current,i,dops[i].rs1);
2098 alloc_reg(current,i,dops[i].rs2);
37387d8b 2099 if (ram_offset)
2100 alloc_reg(current, i, ROREG);
57871462 2101 #if defined(HOST_IMM8)
2102 // On CPUs without 32-bit immediates we need a pointer to invalid_code
37387d8b 2103 alloc_reg(current, i, INVCP);
57871462 2104 #endif
277718fa 2105 if (dops[i].opcode == 0x2a || dops[i].opcode == 0x2e) { // SWL/SWL
57871462 2106 alloc_reg(current,i,FTEMP);
2107 }
90f98e7c 2108 if (dops[i].may_except)
2109 alloc_cc_optional(current, i); // for exceptions
57871462 2110 // We need a temporary register for address generation
2111 alloc_reg_temp(current,i,-1);
277718fa 2112 cinfo[i].min_free_regs=1;
57871462 2113}
2114
90f98e7c 2115static void c2ls_alloc(struct regstat *current, int i)
b9b61529 2116{
cf95b4f0 2117 clear_const(current,dops[i].rt1);
2118 if(needed_again(dops[i].rs1,i)) alloc_reg(current,i,dops[i].rs1);
b9b61529 2119 alloc_reg(current,i,FTEMP);
37387d8b 2120 if (ram_offset)
2121 alloc_reg(current, i, ROREG);
b9b61529 2122 #if defined(HOST_IMM8)
2123 // On CPUs without 32-bit immediates we need a pointer to invalid_code
37387d8b 2124 if (dops[i].opcode == 0x3a) // SWC2
b9b61529 2125 alloc_reg(current,i,INVCP);
2126 #endif
90f98e7c 2127 if (dops[i].may_except)
2128 alloc_cc_optional(current, i); // for exceptions
b9b61529 2129 // We need a temporary register for address generation
2130 alloc_reg_temp(current,i,-1);
277718fa 2131 cinfo[i].min_free_regs=1;
b9b61529 2132}
2133
57871462 2134#ifndef multdiv_alloc
4149788d 2135static void multdiv_alloc(struct regstat *current,int i)
57871462 2136{
2137 // case 0x18: MULT
2138 // case 0x19: MULTU
2139 // case 0x1A: DIV
2140 // case 0x1B: DIVU
cf95b4f0 2141 clear_const(current,dops[i].rs1);
2142 clear_const(current,dops[i].rs2);
32631e6a 2143 alloc_cc(current,i); // for stalls
90f98e7c 2144 dirty_reg(current,CCREG);
4ee246ed 2145 current->u &= ~(1ull << HIREG);
2146 current->u &= ~(1ull << LOREG);
2147 alloc_reg(current, i, HIREG);
2148 alloc_reg(current, i, LOREG);
2149 dirty_reg(current, HIREG);
2150 dirty_reg(current, LOREG);
2151 if ((dops[i].opcode2 & 0x3e) == 0x1a || (dops[i].rs1 && dops[i].rs2)) // div(u)
57871462 2152 {
4ee246ed 2153 alloc_reg(current, i, dops[i].rs1);
2154 alloc_reg(current, i, dops[i].rs2);
57871462 2155 }
4ee246ed 2156 // else multiply by zero is zero
57871462 2157}
2158#endif
2159
4149788d 2160static void cop0_alloc(struct regstat *current,int i)
57871462 2161{
cf95b4f0 2162 if(dops[i].opcode2==0) // MFC0
57871462 2163 {
cf95b4f0 2164 if(dops[i].rt1) {
2165 clear_const(current,dops[i].rt1);
cf95b4f0 2166 alloc_reg(current,i,dops[i].rt1);
2167 dirty_reg(current,dops[i].rt1);
57871462 2168 }
2169 }
cf95b4f0 2170 else if(dops[i].opcode2==4) // MTC0
57871462 2171 {
de6dbc52 2172 if (((source[i]>>11)&0x1e) == 12) {
2173 alloc_cc(current, i);
2174 dirty_reg(current, CCREG);
2175 }
cf95b4f0 2176 if(dops[i].rs1){
2177 clear_const(current,dops[i].rs1);
2178 alloc_reg(current,i,dops[i].rs1);
57871462 2179 alloc_all(current,i);
2180 }
2181 else {
2182 alloc_all(current,i); // FIXME: Keep r0
2183 current->u&=~1LL;
2184 alloc_reg(current,i,0);
2185 }
277718fa 2186 cinfo[i].min_free_regs = HOST_REGS;
57871462 2187 }
a5cd72d0 2188}
2189
2190static void rfe_alloc(struct regstat *current, int i)
2191{
2192 alloc_all(current, i);
277718fa 2193 cinfo[i].min_free_regs = HOST_REGS;
57871462 2194}
2195
81dbbf4c 2196static void cop2_alloc(struct regstat *current,int i)
57871462 2197{
cf95b4f0 2198 if (dops[i].opcode2 < 3) // MFC2/CFC2
57871462 2199 {
81dbbf4c 2200 alloc_cc(current,i); // for stalls
2201 dirty_reg(current,CCREG);
cf95b4f0 2202 if(dops[i].rt1){
2203 clear_const(current,dops[i].rt1);
2204 alloc_reg(current,i,dops[i].rt1);
2205 dirty_reg(current,dops[i].rt1);
57871462 2206 }
57871462 2207 }
cf95b4f0 2208 else if (dops[i].opcode2 > 3) // MTC2/CTC2
57871462 2209 {
cf95b4f0 2210 if(dops[i].rs1){
2211 clear_const(current,dops[i].rs1);
2212 alloc_reg(current,i,dops[i].rs1);
57871462 2213 }
2214 else {
2215 current->u&=~1LL;
2216 alloc_reg(current,i,0);
57871462 2217 }
2218 }
81dbbf4c 2219 alloc_reg_temp(current,i,-1);
277718fa 2220 cinfo[i].min_free_regs=1;
57871462 2221}
00fa9369 2222
4149788d 2223static void c2op_alloc(struct regstat *current,int i)
b9b61529 2224{
81dbbf4c 2225 alloc_cc(current,i); // for stalls
2226 dirty_reg(current,CCREG);
b9b61529 2227 alloc_reg_temp(current,i,-1);
2228}
57871462 2229
4149788d 2230static void syscall_alloc(struct regstat *current,int i)
57871462 2231{
2232 alloc_cc(current,i);
2233 dirty_reg(current,CCREG);
2234 alloc_all(current,i);
277718fa 2235 cinfo[i].min_free_regs=HOST_REGS;
57871462 2236 current->isconst=0;
2237}
2238
4149788d 2239static void delayslot_alloc(struct regstat *current,int i)
57871462 2240{
cf95b4f0 2241 switch(dops[i].itype) {
57871462 2242 case UJUMP:
2243 case CJUMP:
2244 case SJUMP:
2245 case RJUMP:
57871462 2246 case SYSCALL:
7139f3c8 2247 case HLECALL:
57871462 2248 case IMM16:
2249 imm16_alloc(current,i);
2250 break;
2251 case LOAD:
2252 case LOADLR:
2253 load_alloc(current,i);
2254 break;
2255 case STORE:
2256 case STORELR:
2257 store_alloc(current,i);
2258 break;
2259 case ALU:
2260 alu_alloc(current,i);
2261 break;
2262 case SHIFT:
2263 shift_alloc(current,i);
2264 break;
2265 case MULTDIV:
2266 multdiv_alloc(current,i);
2267 break;
2268 case SHIFTIMM:
2269 shiftimm_alloc(current,i);
2270 break;
2271 case MOV:
2272 mov_alloc(current,i);
2273 break;
2274 case COP0:
2275 cop0_alloc(current,i);
2276 break;
a5cd72d0 2277 case RFE:
2278 rfe_alloc(current,i);
81dbbf4c 2279 break;
b9b61529 2280 case COP2:
81dbbf4c 2281 cop2_alloc(current,i);
57871462 2282 break;
b9b61529 2283 case C2LS:
2284 c2ls_alloc(current,i);
2285 break;
b9b61529 2286 case C2OP:
2287 c2op_alloc(current,i);
2288 break;
57871462 2289 }
2290}
2291
b14b6a8f 2292static void add_stub(enum stub_type type, void *addr, void *retaddr,
2293 u_int a, uintptr_t b, uintptr_t c, u_int d, u_int e)
2294{
d1e4ebd9 2295 assert(stubcount < ARRAY_SIZE(stubs));
b14b6a8f 2296 stubs[stubcount].type = type;
2297 stubs[stubcount].addr = addr;
2298 stubs[stubcount].retaddr = retaddr;
2299 stubs[stubcount].a = a;
2300 stubs[stubcount].b = b;
2301 stubs[stubcount].c = c;
2302 stubs[stubcount].d = d;
2303 stubs[stubcount].e = e;
57871462 2304 stubcount++;
2305}
2306
b14b6a8f 2307static void add_stub_r(enum stub_type type, void *addr, void *retaddr,
81dbbf4c 2308 int i, int addr_reg, const struct regstat *i_regs, int ccadj, u_int reglist)
b14b6a8f 2309{
2310 add_stub(type, addr, retaddr, i, addr_reg, (uintptr_t)i_regs, ccadj, reglist);
2311}
2312
57871462 2313// Write out a single register
a22ccd6a 2314static void wb_register(signed char r, const signed char regmap[], u_int dirty)
57871462 2315{
2316 int hr;
2317 for(hr=0;hr<HOST_REGS;hr++) {
2318 if(hr!=EXCLUDE_REG) {
9de8a0c3 2319 if(regmap[hr]==r) {
57871462 2320 if((dirty>>hr)&1) {
ad49de89 2321 assert(regmap[hr]<64);
2322 emit_storereg(r,hr);
57871462 2323 }
a22ccd6a 2324 break;
57871462 2325 }
2326 }
2327 }
2328}
2329
8062d65a 2330static void wb_valid(signed char pre[],signed char entry[],u_int dirty_pre,u_int dirty,uint64_t u)
2331{
2332 //if(dirty_pre==dirty) return;
53358c1d 2333 int hr, r;
2334 for (hr = 0; hr < HOST_REGS; hr++) {
2335 r = pre[hr];
2336 if (r < 1 || r > 33 || ((u >> r) & 1))
2337 continue;
2338 if (((dirty_pre & ~dirty) >> hr) & 1)
2339 emit_storereg(r, hr);
8062d65a 2340 }
2341}
2342
687b4580 2343// trashes r2
2344static void pass_args(int a0, int a1)
2345{
2346 if(a0==1&&a1==0) {
2347 // must swap
2348 emit_mov(a0,2); emit_mov(a1,1); emit_mov(2,0);
2349 }
2350 else if(a0!=0&&a1==0) {
2351 emit_mov(a1,1);
2352 if (a0>=0) emit_mov(a0,0);
2353 }
2354 else {
2355 if(a0>=0&&a0!=0) emit_mov(a0,0);
2356 if(a1>=0&&a1!=1) emit_mov(a1,1);
2357 }
2358}
2359
a5cd72d0 2360static void alu_assemble(int i, const struct regstat *i_regs, int ccadj_)
57871462 2361{
cf95b4f0 2362 if(dops[i].opcode2>=0x20&&dops[i].opcode2<=0x23) { // ADD/ADDU/SUB/SUBU
a5cd72d0 2363 int do_oflow = dops[i].may_except; // ADD/SUB with exceptions enabled
2364 if (dops[i].rt1 || do_oflow) {
2365 int do_exception_check = 0;
2366 signed char s1, s2, t, tmp;
2367 t = get_reg_w(i_regs->regmap, dops[i].rt1);
2368 tmp = get_reg_temp(i_regs->regmap);
277718fa 2369 if (do_oflow)
2370 assert(tmp >= 0);
90f98e7c 2371 if (t < 0 && do_oflow)
2372 t = tmp;
a5cd72d0 2373 if (t >= 0) {
2374 s1 = get_reg(i_regs->regmap, dops[i].rs1);
2375 s2 = get_reg(i_regs->regmap, dops[i].rs2);
2376 if (dops[i].rs1 && dops[i].rs2) {
57871462 2377 assert(s1>=0);
2378 assert(s2>=0);
a5cd72d0 2379 if (dops[i].opcode2 & 2) {
2380 if (do_oflow) {
2381 emit_subs(s1, s2, tmp);
2382 do_exception_check = 1;
2383 }
2384 else
2385 emit_sub(s1,s2,t);
2386 }
2387 else {
2388 if (do_oflow) {
2389 emit_adds(s1, s2, tmp);
2390 do_exception_check = 1;
2391 }
2392 else
2393 emit_add(s1,s2,t);
2394 }
57871462 2395 }
cf95b4f0 2396 else if(dops[i].rs1) {
57871462 2397 if(s1>=0) emit_mov(s1,t);
cf95b4f0 2398 else emit_loadreg(dops[i].rs1,t);
57871462 2399 }
cf95b4f0 2400 else if(dops[i].rs2) {
a5cd72d0 2401 if (s2 < 0) {
2402 emit_loadreg(dops[i].rs2, t);
2403 s2 = t;
57871462 2404 }
a5cd72d0 2405 if (dops[i].opcode2 & 2) {
2406 if (do_oflow) {
2407 emit_negs(s2, tmp);
2408 do_exception_check = 1;
2409 }
2410 else
2411 emit_neg(s2, t);
57871462 2412 }
a5cd72d0 2413 else if (s2 != t)
2414 emit_mov(s2, t);
57871462 2415 }
a5cd72d0 2416 else
2417 emit_zeroreg(t);
2418 }
2419 if (do_exception_check) {
2420 void *jaddr = out;
2421 emit_jo(0);
2422 if (t >= 0 && tmp != t)
2423 emit_mov(tmp, t);
2424 add_stub_r(OVERFLOW_STUB, jaddr, out, i, 0, i_regs, ccadj_, 0);
57871462 2425 }
2426 }
2427 }
a5cd72d0 2428 else if(dops[i].opcode2==0x2a||dops[i].opcode2==0x2b) { // SLT/SLTU
cf95b4f0 2429 if(dops[i].rt1) {
ad49de89 2430 signed char s1l,s2l,t;
57871462 2431 {
a5cd72d0 2432 t=get_reg_w(i_regs->regmap, dops[i].rt1);
57871462 2433 //assert(t>=0);
2434 if(t>=0) {
cf95b4f0 2435 s1l=get_reg(i_regs->regmap,dops[i].rs1);
2436 s2l=get_reg(i_regs->regmap,dops[i].rs2);
2437 if(dops[i].rs2==0) // rx<r0
57871462 2438 {
cf95b4f0 2439 if(dops[i].opcode2==0x2a&&dops[i].rs1!=0) { // SLT
06e425d7 2440 assert(s1l>=0);
57871462 2441 emit_shrimm(s1l,31,t);
06e425d7 2442 }
2443 else // SLTU (unsigned can not be less than zero, 0<0)
57871462 2444 emit_zeroreg(t);
2445 }
cf95b4f0 2446 else if(dops[i].rs1==0) // r0<rx
57871462 2447 {
2448 assert(s2l>=0);
cf95b4f0 2449 if(dops[i].opcode2==0x2a) // SLT
57871462 2450 emit_set_gz32(s2l,t);
2451 else // SLTU (set if not zero)
2452 emit_set_nz32(s2l,t);
2453 }
2454 else{
2455 assert(s1l>=0);assert(s2l>=0);
cf95b4f0 2456 if(dops[i].opcode2==0x2a) // SLT
57871462 2457 emit_set_if_less32(s1l,s2l,t);
2458 else // SLTU
2459 emit_set_if_carry32(s1l,s2l,t);
2460 }
2461 }
2462 }
2463 }
2464 }
a5cd72d0 2465 else if(dops[i].opcode2>=0x24&&dops[i].opcode2<=0x27) { // AND/OR/XOR/NOR
cf95b4f0 2466 if(dops[i].rt1) {
ad49de89 2467 signed char s1l,s2l,tl;
a5cd72d0 2468 tl=get_reg_w(i_regs->regmap, dops[i].rt1);
57871462 2469 {
57871462 2470 if(tl>=0) {
cf95b4f0 2471 s1l=get_reg(i_regs->regmap,dops[i].rs1);
2472 s2l=get_reg(i_regs->regmap,dops[i].rs2);
2473 if(dops[i].rs1&&dops[i].rs2) {
57871462 2474 assert(s1l>=0);
2475 assert(s2l>=0);
cf95b4f0 2476 if(dops[i].opcode2==0x24) { // AND
57871462 2477 emit_and(s1l,s2l,tl);
2478 } else
cf95b4f0 2479 if(dops[i].opcode2==0x25) { // OR
57871462 2480 emit_or(s1l,s2l,tl);
2481 } else
cf95b4f0 2482 if(dops[i].opcode2==0x26) { // XOR
57871462 2483 emit_xor(s1l,s2l,tl);
2484 } else
cf95b4f0 2485 if(dops[i].opcode2==0x27) { // NOR
57871462 2486 emit_or(s1l,s2l,tl);
2487 emit_not(tl,tl);
2488 }
2489 }
2490 else
2491 {
cf95b4f0 2492 if(dops[i].opcode2==0x24) { // AND
57871462 2493 emit_zeroreg(tl);
2494 } else
cf95b4f0 2495 if(dops[i].opcode2==0x25||dops[i].opcode2==0x26) { // OR/XOR
2496 if(dops[i].rs1){
57871462 2497 if(s1l>=0) emit_mov(s1l,tl);
cf95b4f0 2498 else emit_loadreg(dops[i].rs1,tl); // CHECK: regmap_entry?
57871462 2499 }
2500 else
cf95b4f0 2501 if(dops[i].rs2){
57871462 2502 if(s2l>=0) emit_mov(s2l,tl);
cf95b4f0 2503 else emit_loadreg(dops[i].rs2,tl); // CHECK: regmap_entry?
57871462 2504 }
2505 else emit_zeroreg(tl);
2506 } else
cf95b4f0 2507 if(dops[i].opcode2==0x27) { // NOR
2508 if(dops[i].rs1){
57871462 2509 if(s1l>=0) emit_not(s1l,tl);
2510 else {
cf95b4f0 2511 emit_loadreg(dops[i].rs1,tl);
57871462 2512 emit_not(tl,tl);
2513 }
2514 }
2515 else
cf95b4f0 2516 if(dops[i].rs2){
57871462 2517 if(s2l>=0) emit_not(s2l,tl);
2518 else {
cf95b4f0 2519 emit_loadreg(dops[i].rs2,tl);
57871462 2520 emit_not(tl,tl);
2521 }
2522 }
2523 else emit_movimm(-1,tl);
2524 }
2525 }
2526 }
2527 }
2528 }
2529 }
2530}
2531
a5cd72d0 2532static void imm16_assemble(int i, const struct regstat *i_regs, int ccadj_)
57871462 2533{
cf95b4f0 2534 if (dops[i].opcode==0x0f) { // LUI
2535 if(dops[i].rt1) {
57871462 2536 signed char t;
a5cd72d0 2537 t=get_reg_w(i_regs->regmap, dops[i].rt1);
57871462 2538 //assert(t>=0);
2539 if(t>=0) {
2540 if(!((i_regs->isconst>>t)&1))
277718fa 2541 emit_movimm(cinfo[i].imm<<16,t);
57871462 2542 }
2543 }
2544 }
cf95b4f0 2545 if(dops[i].opcode==0x08||dops[i].opcode==0x09) { // ADDI/ADDIU
277718fa 2546 int is_addi = dops[i].may_except;
a5cd72d0 2547 if (dops[i].rt1 || is_addi) {
2548 signed char s, t, tmp;
2549 t=get_reg_w(i_regs->regmap, dops[i].rt1);
cf95b4f0 2550 s=get_reg(i_regs->regmap,dops[i].rs1);
2551 if(dops[i].rs1) {
a5cd72d0 2552 tmp = get_reg_temp(i_regs->regmap);
2553 if (is_addi) {
2554 assert(tmp >= 0);
2555 if (t < 0) t = tmp;
2556 }
57871462 2557 if(t>=0) {
2558 if(!((i_regs->isconst>>t)&1)) {
a5cd72d0 2559 int sum, do_exception_check = 0;
2560 if (s < 0) {
cf95b4f0 2561 if(i_regs->regmap_entry[t]!=dops[i].rs1) emit_loadreg(dops[i].rs1,t);
a5cd72d0 2562 if (is_addi) {
277718fa 2563 emit_addimm_and_set_flags3(t, cinfo[i].imm, tmp);
a5cd72d0 2564 do_exception_check = 1;
2565 }
57871462 2566 else
277718fa 2567 emit_addimm(t, cinfo[i].imm, t);
a5cd72d0 2568 } else {
2569 if (!((i_regs->wasconst >> s) & 1)) {
2570 if (is_addi) {
277718fa 2571 emit_addimm_and_set_flags3(s, cinfo[i].imm, tmp);
a5cd72d0 2572 do_exception_check = 1;
2573 }
2574 else
277718fa 2575 emit_addimm(s, cinfo[i].imm, t);
a5cd72d0 2576 }
2577 else {
277718fa 2578 int oflow = add_overflow(constmap[i][s], cinfo[i].imm, sum);
a5cd72d0 2579 if (is_addi && oflow)
2580 do_exception_check = 2;
2581 else
2582 emit_movimm(sum, t);
2583 }
2584 }
2585 if (do_exception_check) {
2586 void *jaddr = out;
2587 if (do_exception_check == 2)
2588 emit_jmp(0);
2589 else {
2590 emit_jo(0);
2591 if (tmp != t)
2592 emit_mov(tmp, t);
2593 }
2594 add_stub_r(OVERFLOW_STUB, jaddr, out, i, 0, i_regs, ccadj_, 0);
57871462 2595 }
2596 }
2597 }
2598 } else {
2599 if(t>=0) {
2600 if(!((i_regs->isconst>>t)&1))
277718fa 2601 emit_movimm(cinfo[i].imm,t);
57871462 2602 }
2603 }
2604 }
2605 }
cf95b4f0 2606 else if(dops[i].opcode==0x0a||dops[i].opcode==0x0b) { // SLTI/SLTIU
2607 if(dops[i].rt1) {
2608 //assert(dops[i].rs1!=0); // r0 might be valid, but it's probably a bug
ad49de89 2609 signed char sl,t;
a5cd72d0 2610 t=get_reg_w(i_regs->regmap, dops[i].rt1);
cf95b4f0 2611 sl=get_reg(i_regs->regmap,dops[i].rs1);
57871462 2612 //assert(t>=0);
2613 if(t>=0) {
cf95b4f0 2614 if(dops[i].rs1>0) {
2615 if(dops[i].opcode==0x0a) { // SLTI
57871462 2616 if(sl<0) {
cf95b4f0 2617 if(i_regs->regmap_entry[t]!=dops[i].rs1) emit_loadreg(dops[i].rs1,t);
277718fa 2618 emit_slti32(t,cinfo[i].imm,t);
57871462 2619 }else{
277718fa 2620 emit_slti32(sl,cinfo[i].imm,t);
57871462 2621 }
2622 }
2623 else { // SLTIU
2624 if(sl<0) {
cf95b4f0 2625 if(i_regs->regmap_entry[t]!=dops[i].rs1) emit_loadreg(dops[i].rs1,t);
277718fa 2626 emit_sltiu32(t,cinfo[i].imm,t);
57871462 2627 }else{
277718fa 2628 emit_sltiu32(sl,cinfo[i].imm,t);
57871462 2629 }
2630 }
57871462 2631 }else{
2632 // SLTI(U) with r0 is just stupid,
2633 // nonetheless examples can be found
cf95b4f0 2634 if(dops[i].opcode==0x0a) // SLTI
277718fa 2635 if(0<cinfo[i].imm) emit_movimm(1,t);
57871462 2636 else emit_zeroreg(t);
2637 else // SLTIU
2638 {
277718fa 2639 if(cinfo[i].imm) emit_movimm(1,t);
57871462 2640 else emit_zeroreg(t);
2641 }
2642 }
2643 }
2644 }
2645 }
cf95b4f0 2646 else if(dops[i].opcode>=0x0c&&dops[i].opcode<=0x0e) { // ANDI/ORI/XORI
2647 if(dops[i].rt1) {
7c3a5182 2648 signed char sl,tl;
a5cd72d0 2649 tl=get_reg_w(i_regs->regmap, dops[i].rt1);
cf95b4f0 2650 sl=get_reg(i_regs->regmap,dops[i].rs1);
57871462 2651 if(tl>=0 && !((i_regs->isconst>>tl)&1)) {
cf95b4f0 2652 if(dops[i].opcode==0x0c) //ANDI
57871462 2653 {
cf95b4f0 2654 if(dops[i].rs1) {
57871462 2655 if(sl<0) {
cf95b4f0 2656 if(i_regs->regmap_entry[tl]!=dops[i].rs1) emit_loadreg(dops[i].rs1,tl);
277718fa 2657 emit_andimm(tl,cinfo[i].imm,tl);
57871462 2658 }else{
2659 if(!((i_regs->wasconst>>sl)&1))
277718fa 2660 emit_andimm(sl,cinfo[i].imm,tl);
57871462 2661 else
277718fa 2662 emit_movimm(constmap[i][sl]&cinfo[i].imm,tl);
57871462 2663 }
2664 }
2665 else
2666 emit_zeroreg(tl);
57871462 2667 }
2668 else
2669 {
cf95b4f0 2670 if(dops[i].rs1) {
57871462 2671 if(sl<0) {
cf95b4f0 2672 if(i_regs->regmap_entry[tl]!=dops[i].rs1) emit_loadreg(dops[i].rs1,tl);
57871462 2673 }
cf95b4f0 2674 if(dops[i].opcode==0x0d) { // ORI
581335b0 2675 if(sl<0) {
277718fa 2676 emit_orimm(tl,cinfo[i].imm,tl);
581335b0 2677 }else{
2678 if(!((i_regs->wasconst>>sl)&1))
277718fa 2679 emit_orimm(sl,cinfo[i].imm,tl);
581335b0 2680 else
277718fa 2681 emit_movimm(constmap[i][sl]|cinfo[i].imm,tl);
581335b0 2682 }
57871462 2683 }
cf95b4f0 2684 if(dops[i].opcode==0x0e) { // XORI
581335b0 2685 if(sl<0) {
277718fa 2686 emit_xorimm(tl,cinfo[i].imm,tl);
581335b0 2687 }else{
2688 if(!((i_regs->wasconst>>sl)&1))
277718fa 2689 emit_xorimm(sl,cinfo[i].imm,tl);
581335b0 2690 else
277718fa 2691 emit_movimm(constmap[i][sl]^cinfo[i].imm,tl);
581335b0 2692 }
57871462 2693 }
2694 }
2695 else {
277718fa 2696 emit_movimm(cinfo[i].imm,tl);
57871462 2697 }
2698 }
2699 }
2700 }
2701 }
2702}
2703
2330734f 2704static void shiftimm_assemble(int i, const struct regstat *i_regs)
57871462 2705{
cf95b4f0 2706 if(dops[i].opcode2<=0x3) // SLL/SRL/SRA
57871462 2707 {
cf95b4f0 2708 if(dops[i].rt1) {
57871462 2709 signed char s,t;
a5cd72d0 2710 t=get_reg_w(i_regs->regmap, dops[i].rt1);
cf95b4f0 2711 s=get_reg(i_regs->regmap,dops[i].rs1);
57871462 2712 //assert(t>=0);
dc49e339 2713 if(t>=0&&!((i_regs->isconst>>t)&1)){
cf95b4f0 2714 if(dops[i].rs1==0)
57871462 2715 {
2716 emit_zeroreg(t);
2717 }
2718 else
2719 {
cf95b4f0 2720 if(s<0&&i_regs->regmap_entry[t]!=dops[i].rs1) emit_loadreg(dops[i].rs1,t);
277718fa 2721 if(cinfo[i].imm) {
cf95b4f0 2722 if(dops[i].opcode2==0) // SLL
57871462 2723 {
277718fa 2724 emit_shlimm(s<0?t:s,cinfo[i].imm,t);
57871462 2725 }
cf95b4f0 2726 if(dops[i].opcode2==2) // SRL
57871462 2727 {
277718fa 2728 emit_shrimm(s<0?t:s,cinfo[i].imm,t);
57871462 2729 }
cf95b4f0 2730 if(dops[i].opcode2==3) // SRA
57871462 2731 {
277718fa 2732 emit_sarimm(s<0?t:s,cinfo[i].imm,t);
57871462 2733 }
2734 }else{
2735 // Shift by zero
2736 if(s>=0 && s!=t) emit_mov(s,t);
2737 }
2738 }
2739 }
cf95b4f0 2740 //emit_storereg(dops[i].rt1,t); //DEBUG
57871462 2741 }
2742 }
cf95b4f0 2743 if(dops[i].opcode2>=0x38&&dops[i].opcode2<=0x3b) // DSLL/DSRL/DSRA
57871462 2744 {
9c45ca93 2745 assert(0);
57871462 2746 }
cf95b4f0 2747 if(dops[i].opcode2==0x3c) // DSLL32
57871462 2748 {
9c45ca93 2749 assert(0);
57871462 2750 }
cf95b4f0 2751 if(dops[i].opcode2==0x3e) // DSRL32
57871462 2752 {
9c45ca93 2753 assert(0);
57871462 2754 }
cf95b4f0 2755 if(dops[i].opcode2==0x3f) // DSRA32
57871462 2756 {
9c45ca93 2757 assert(0);
57871462 2758 }
2759}
2760
2761#ifndef shift_assemble
2330734f 2762static void shift_assemble(int i, const struct regstat *i_regs)
57871462 2763{
3968e69e 2764 signed char s,t,shift;
cf95b4f0 2765 if (dops[i].rt1 == 0)
3968e69e 2766 return;
cf95b4f0 2767 assert(dops[i].opcode2<=0x07); // SLLV/SRLV/SRAV
2768 t = get_reg(i_regs->regmap, dops[i].rt1);
2769 s = get_reg(i_regs->regmap, dops[i].rs1);
2770 shift = get_reg(i_regs->regmap, dops[i].rs2);
3968e69e 2771 if (t < 0)
2772 return;
2773
cf95b4f0 2774 if(dops[i].rs1==0)
3968e69e 2775 emit_zeroreg(t);
cf95b4f0 2776 else if(dops[i].rs2==0) {
3968e69e 2777 assert(s>=0);
2778 if(s!=t) emit_mov(s,t);
2779 }
2780 else {
2781 host_tempreg_acquire();
2782 emit_andimm(shift,31,HOST_TEMPREG);
cf95b4f0 2783 switch(dops[i].opcode2) {
3968e69e 2784 case 4: // SLLV
2785 emit_shl(s,HOST_TEMPREG,t);
2786 break;
2787 case 6: // SRLV
2788 emit_shr(s,HOST_TEMPREG,t);
2789 break;
2790 case 7: // SRAV
2791 emit_sar(s,HOST_TEMPREG,t);
2792 break;
2793 default:
2794 assert(0);
2795 }
2796 host_tempreg_release();
2797 }
57871462 2798}
3968e69e 2799
57871462 2800#endif
2801
8062d65a 2802enum {
2803 MTYPE_8000 = 0,
2804 MTYPE_8020,
2805 MTYPE_0000,
2806 MTYPE_A000,
2807 MTYPE_1F80,
2808};
2809
2810static int get_ptr_mem_type(u_int a)
2811{
2812 if(a < 0x00200000) {
2813 if(a<0x1000&&((start>>20)==0xbfc||(start>>24)==0xa0))
2814 // return wrong, must use memhandler for BIOS self-test to pass
2815 // 007 does similar stuff from a00 mirror, weird stuff
2816 return MTYPE_8000;
2817 return MTYPE_0000;
2818 }
2819 if(0x1f800000 <= a && a < 0x1f801000)
2820 return MTYPE_1F80;
2821 if(0x80200000 <= a && a < 0x80800000)
2822 return MTYPE_8020;
2823 if(0xa0000000 <= a && a < 0xa0200000)
2824 return MTYPE_A000;
2825 return MTYPE_8000;
2826}
2827
37387d8b 2828static int get_ro_reg(const struct regstat *i_regs, int host_tempreg_free)
2829{
2830 int r = get_reg(i_regs->regmap, ROREG);
2831 if (r < 0 && host_tempreg_free) {
2832 host_tempreg_acquire();
2833 emit_loadreg(ROREG, r = HOST_TEMPREG);
2834 }
2835 if (r < 0)
2836 abort();
2837 return r;
2838}
2839
2840static void *emit_fastpath_cmp_jump(int i, const struct regstat *i_regs,
277718fa 2841 int addr, int *offset_reg, int *addr_reg_override, int ccadj_)
8062d65a 2842{
2843 void *jaddr = NULL;
37387d8b 2844 int type = 0;
2845 int mr = dops[i].rs1;
277718fa 2846 assert(addr >= 0);
37387d8b 2847 *offset_reg = -1;
8062d65a 2848 if(((smrv_strong|smrv_weak)>>mr)&1) {
2849 type=get_ptr_mem_type(smrv[mr]);
2850 //printf("set %08x @%08x r%d %d\n", smrv[mr], start+i*4, mr, type);
2851 }
2852 else {
2853 // use the mirror we are running on
2854 type=get_ptr_mem_type(start);
2855 //printf("set nospec @%08x r%d %d\n", start+i*4, mr, type);
2856 }
2857
277718fa 2858 if (dops[i].may_except) {
2859 // alignment check
2860 u_int op = dops[i].opcode;
2861 int mask = ((op & 0x37) == 0x21 || op == 0x25) ? 1 : 3; // LH/SH/LHU
33a1eda1 2862 void *jaddr2;
277718fa 2863 emit_testimm(addr, mask);
33a1eda1 2864 jaddr2 = out;
277718fa 2865 emit_jne(0);
33a1eda1 2866 add_stub_r(ALIGNMENT_STUB, jaddr2, out, i, addr, i_regs, ccadj_, 0);
277718fa 2867 }
2868
8062d65a 2869 if(type==MTYPE_8020) { // RAM 80200000+ mirror
d1e4ebd9 2870 host_tempreg_acquire();
8062d65a 2871 emit_andimm(addr,~0x00e00000,HOST_TEMPREG);
2872 addr=*addr_reg_override=HOST_TEMPREG;
2873 type=0;
2874 }
2875 else if(type==MTYPE_0000) { // RAM 0 mirror
d1e4ebd9 2876 host_tempreg_acquire();
8062d65a 2877 emit_orimm(addr,0x80000000,HOST_TEMPREG);
2878 addr=*addr_reg_override=HOST_TEMPREG;
2879 type=0;
2880 }
2881 else if(type==MTYPE_A000) { // RAM A mirror
d1e4ebd9 2882 host_tempreg_acquire();
8062d65a 2883 emit_andimm(addr,~0x20000000,HOST_TEMPREG);
2884 addr=*addr_reg_override=HOST_TEMPREG;
2885 type=0;
2886 }
2887 else if(type==MTYPE_1F80) { // scratchpad
2888 if (psxH == (void *)0x1f800000) {
d1e4ebd9 2889 host_tempreg_acquire();
3968e69e 2890 emit_xorimm(addr,0x1f800000,HOST_TEMPREG);
8062d65a 2891 emit_cmpimm(HOST_TEMPREG,0x1000);
d1e4ebd9 2892 host_tempreg_release();
8062d65a 2893 jaddr=out;
2894 emit_jc(0);
2895 }
2896 else {
2897 // do the usual RAM check, jump will go to the right handler
2898 type=0;
2899 }
2900 }
2901
37387d8b 2902 if (type == 0) // need ram check
8062d65a 2903 {
2904 emit_cmpimm(addr,RAM_SIZE);
37387d8b 2905 jaddr = out;
8062d65a 2906 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
2907 // Hint to branch predictor that the branch is unlikely to be taken
37387d8b 2908 if (dops[i].rs1 >= 28)
8062d65a 2909 emit_jno_unlikely(0);
2910 else
2911 #endif
2912 emit_jno(0);
37387d8b 2913 if (ram_offset != 0)
2914 *offset_reg = get_ro_reg(i_regs, 0);
8062d65a 2915 }
2916
2917 return jaddr;
2918}
2919
687b4580 2920// return memhandler, or get directly accessable address and return 0
2921static void *get_direct_memhandler(void *table, u_int addr,
2922 enum stub_type type, uintptr_t *addr_host)
2923{
c979e8c2 2924 uintptr_t msb = 1ull << (sizeof(uintptr_t)*8 - 1);
687b4580 2925 uintptr_t l1, l2 = 0;
2926 l1 = ((uintptr_t *)table)[addr>>12];
c979e8c2 2927 if (!(l1 & msb)) {
687b4580 2928 uintptr_t v = l1 << 1;
2929 *addr_host = v + addr;
2930 return NULL;
2931 }
2932 else {
2933 l1 <<= 1;
2934 if (type == LOADB_STUB || type == LOADBU_STUB || type == STOREB_STUB)
2935 l2 = ((uintptr_t *)l1)[0x1000/4 + 0x1000/2 + (addr&0xfff)];
2936 else if (type == LOADH_STUB || type == LOADHU_STUB || type == STOREH_STUB)
c979e8c2 2937 l2 = ((uintptr_t *)l1)[0x1000/4 + (addr&0xfff)/2];
687b4580 2938 else
c979e8c2 2939 l2 = ((uintptr_t *)l1)[(addr&0xfff)/4];
2940 if (!(l2 & msb)) {
687b4580 2941 uintptr_t v = l2 << 1;
2942 *addr_host = v + (addr&0xfff);
2943 return NULL;
2944 }
2945 return (void *)(l2 << 1);
2946 }
2947}
2948
81dbbf4c 2949static u_int get_host_reglist(const signed char *regmap)
2950{
2951 u_int reglist = 0, hr;
2952 for (hr = 0; hr < HOST_REGS; hr++) {
2953 if (hr != EXCLUDE_REG && regmap[hr] >= 0)
2954 reglist |= 1 << hr;
2955 }
2956 return reglist;
2957}
2958
2959static u_int reglist_exclude(u_int reglist, int r1, int r2)
2960{
2961 if (r1 >= 0)
2962 reglist &= ~(1u << r1);
2963 if (r2 >= 0)
2964 reglist &= ~(1u << r2);
2965 return reglist;
2966}
2967
e3c6bdb5 2968// find a temp caller-saved register not in reglist (so assumed to be free)
2969static int reglist_find_free(u_int reglist)
2970{
2971 u_int free_regs = ~reglist & CALLER_SAVE_REGS;
2972 if (free_regs == 0)
2973 return -1;
2974 return __builtin_ctz(free_regs);
2975}
2976
37387d8b 2977static void do_load_word(int a, int rt, int offset_reg)
2978{
2979 if (offset_reg >= 0)
2980 emit_ldr_dualindexed(offset_reg, a, rt);
2981 else
2982 emit_readword_indexed(0, a, rt);
2983}
2984
2985static void do_store_word(int a, int ofs, int rt, int offset_reg, int preseve_a)
2986{
2987 if (offset_reg < 0) {
2988 emit_writeword_indexed(rt, ofs, a);
2989 return;
2990 }
2991 if (ofs != 0)
2992 emit_addimm(a, ofs, a);
2993 emit_str_dualindexed(offset_reg, a, rt);
2994 if (ofs != 0 && preseve_a)
2995 emit_addimm(a, -ofs, a);
2996}
2997
2998static void do_store_hword(int a, int ofs, int rt, int offset_reg, int preseve_a)
2999{
3000 if (offset_reg < 0) {
3001 emit_writehword_indexed(rt, ofs, a);
3002 return;
3003 }
3004 if (ofs != 0)
3005 emit_addimm(a, ofs, a);
3006 emit_strh_dualindexed(offset_reg, a, rt);
3007 if (ofs != 0 && preseve_a)
3008 emit_addimm(a, -ofs, a);
3009}
3010
3011static void do_store_byte(int a, int rt, int offset_reg)
3012{
3013 if (offset_reg >= 0)
3014 emit_strb_dualindexed(offset_reg, a, rt);
3015 else
3016 emit_writebyte_indexed(rt, 0, a);
3017}
3018
2330734f 3019static void load_assemble(int i, const struct regstat *i_regs, int ccadj_)
57871462 3020{
277718fa 3021 int addr = cinfo[i].addr;
3022 int s,tl;
57871462 3023 int offset;
b14b6a8f 3024 void *jaddr=0;
5bf843dc 3025 int memtarget=0,c=0;
37387d8b 3026 int offset_reg = -1;
3027 int fastio_reg_override = -1;
81dbbf4c 3028 u_int reglist=get_host_reglist(i_regs->regmap);
a5cd72d0 3029 tl=get_reg_w(i_regs->regmap, dops[i].rt1);
cf95b4f0 3030 s=get_reg(i_regs->regmap,dops[i].rs1);
277718fa 3031 offset=cinfo[i].imm;
57871462 3032 if(i_regs->regmap[HOST_CCREG]==CCREG) reglist&=~(1<<HOST_CCREG);
3033 if(s>=0) {
3034 c=(i_regs->wasconst>>s)&1;
af4ee1fe 3035 if (c) {
3036 memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
af4ee1fe 3037 }
57871462 3038 }
57871462 3039 //printf("load_assemble: c=%d\n",c);
643aeae3 3040 //if(c) printf("load_assemble: const=%lx\n",(long)constmap[i][s]+offset);
a5cd72d0 3041 if(tl<0 && ((!c||(((u_int)constmap[i][s]+offset)>>16)==0x1f80) || dops[i].rt1==0)) {
5bf843dc 3042 // could be FIFO, must perform the read
f18c0f46 3043 // ||dummy read
5bf843dc 3044 assem_debug("(forced read)\n");
277718fa 3045 tl = get_reg_temp(i_regs->regmap); // may be == addr
5bf843dc 3046 assert(tl>=0);
5bf843dc 3047 }
277718fa 3048 assert(addr >= 0);
535d208a 3049 if(tl>=0) {
3050 //printf("load_assemble: c=%d\n",c);
643aeae3 3051 //if(c) printf("load_assemble: const=%lx\n",(long)constmap[i][s]+offset);
535d208a 3052 reglist&=~(1<<tl);
1edfcc68 3053 if(!c) {
1edfcc68 3054 #ifdef R29_HACK
3055 // Strmnnrmn's speed hack
cf95b4f0 3056 if(dops[i].rs1!=29||start<0x80001000||start>=0x80000000+RAM_SIZE)
1edfcc68 3057 #endif
3058 {
37387d8b 3059 jaddr = emit_fastpath_cmp_jump(i, i_regs, addr,
277718fa 3060 &offset_reg, &fastio_reg_override, ccadj_);
535d208a 3061 }
1edfcc68 3062 }
37387d8b 3063 else if (ram_offset && memtarget) {
3064 offset_reg = get_ro_reg(i_regs, 0);
535d208a 3065 }
a5cd72d0 3066 int dummy=(dops[i].rt1==0)||(tl!=get_reg_w(i_regs->regmap, dops[i].rt1)); // ignore loads to r0 and unneeded reg
37387d8b 3067 switch (dops[i].opcode) {
3068 case 0x20: // LB
535d208a 3069 if(!c||memtarget) {
3070 if(!dummy) {
277718fa 3071 int a = addr;
37387d8b 3072 if (fastio_reg_override >= 0)
3073 a = fastio_reg_override;
b1570849 3074
37387d8b 3075 if (offset_reg >= 0)
3076 emit_ldrsb_dualindexed(offset_reg, a, tl);
3077 else
3078 emit_movsbl_indexed(0, a, tl);
57871462 3079 }
535d208a 3080 if(jaddr)
2330734f 3081 add_stub_r(LOADB_STUB,jaddr,out,i,addr,i_regs,ccadj_,reglist);
57871462 3082 }
535d208a 3083 else
2330734f 3084 inline_readstub(LOADB_STUB,i,constmap[i][s]+offset,i_regs->regmap,dops[i].rt1,ccadj_,reglist);
37387d8b 3085 break;
3086 case 0x21: // LH
535d208a 3087 if(!c||memtarget) {
3088 if(!dummy) {
277718fa 3089 int a = addr;
37387d8b 3090 if (fastio_reg_override >= 0)
3091 a = fastio_reg_override;
3092 if (offset_reg >= 0)
3093 emit_ldrsh_dualindexed(offset_reg, a, tl);
3094 else
3095 emit_movswl_indexed(0, a, tl);
57871462 3096 }
535d208a 3097 if(jaddr)
2330734f 3098 add_stub_r(LOADH_STUB,jaddr,out,i,addr,i_regs,ccadj_,reglist);
57871462 3099 }
535d208a 3100 else
2330734f 3101 inline_readstub(LOADH_STUB,i,constmap[i][s]+offset,i_regs->regmap,dops[i].rt1,ccadj_,reglist);
37387d8b 3102 break;
3103 case 0x23: // LW
535d208a 3104 if(!c||memtarget) {
3105 if(!dummy) {
37387d8b 3106 int a = addr;
3107 if (fastio_reg_override >= 0)
3108 a = fastio_reg_override;
3109 do_load_word(a, tl, offset_reg);
57871462 3110 }
535d208a 3111 if(jaddr)
2330734f 3112 add_stub_r(LOADW_STUB,jaddr,out,i,addr,i_regs,ccadj_,reglist);
57871462 3113 }
535d208a 3114 else
2330734f 3115 inline_readstub(LOADW_STUB,i,constmap[i][s]+offset,i_regs->regmap,dops[i].rt1,ccadj_,reglist);
37387d8b 3116 break;
3117 case 0x24: // LBU
535d208a 3118 if(!c||memtarget) {
3119 if(!dummy) {
277718fa 3120 int a = addr;
37387d8b 3121 if (fastio_reg_override >= 0)
3122 a = fastio_reg_override;
b1570849 3123
37387d8b 3124 if (offset_reg >= 0)
3125 emit_ldrb_dualindexed(offset_reg, a, tl);
3126 else
3127 emit_movzbl_indexed(0, a, tl);
57871462 3128 }
535d208a 3129 if(jaddr)
2330734f 3130 add_stub_r(LOADBU_STUB,jaddr,out,i,addr,i_regs,ccadj_,reglist);
57871462 3131 }
535d208a 3132 else
2330734f 3133 inline_readstub(LOADBU_STUB,i,constmap[i][s]+offset,i_regs->regmap,dops[i].rt1,ccadj_,reglist);
37387d8b 3134 break;
3135 case 0x25: // LHU
535d208a 3136 if(!c||memtarget) {
3137 if(!dummy) {
277718fa 3138 int a = addr;
37387d8b 3139 if (fastio_reg_override >= 0)
3140 a = fastio_reg_override;
3141 if (offset_reg >= 0)
3142 emit_ldrh_dualindexed(offset_reg, a, tl);
3143 else
3144 emit_movzwl_indexed(0, a, tl);
57871462 3145 }
535d208a 3146 if(jaddr)
2330734f 3147 add_stub_r(LOADHU_STUB,jaddr,out,i,addr,i_regs,ccadj_,reglist);
57871462 3148 }
535d208a 3149 else
2330734f 3150 inline_readstub(LOADHU_STUB,i,constmap[i][s]+offset,i_regs->regmap,dops[i].rt1,ccadj_,reglist);
37387d8b 3151 break;
37387d8b 3152 default:
9c45ca93 3153 assert(0);
57871462 3154 }
a5cd72d0 3155 } // tl >= 0
37387d8b 3156 if (fastio_reg_override == HOST_TEMPREG || offset_reg == HOST_TEMPREG)
d1e4ebd9 3157 host_tempreg_release();
57871462 3158}
3159
3160#ifndef loadlr_assemble
2330734f 3161static void loadlr_assemble(int i, const struct regstat *i_regs, int ccadj_)
57871462 3162{
277718fa 3163 int addr = cinfo[i].addr;
3164 int s,tl,temp,temp2;
3968e69e 3165 int offset;
3166 void *jaddr=0;
3167 int memtarget=0,c=0;
37387d8b 3168 int offset_reg = -1;
3169 int fastio_reg_override = -1;
81dbbf4c 3170 u_int reglist=get_host_reglist(i_regs->regmap);
a5cd72d0 3171 tl=get_reg_w(i_regs->regmap, dops[i].rt1);
cf95b4f0 3172 s=get_reg(i_regs->regmap,dops[i].rs1);
9de8a0c3 3173 temp=get_reg_temp(i_regs->regmap);
3968e69e 3174 temp2=get_reg(i_regs->regmap,FTEMP);
277718fa 3175 offset=cinfo[i].imm;
3968e69e 3176 reglist|=1<<temp;
277718fa 3177 assert(addr >= 0);
3968e69e 3178 if(s>=0) {
3179 c=(i_regs->wasconst>>s)&1;
3180 if(c) {
3181 memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
3182 }
3183 }
3184 if(!c) {
3185 emit_shlimm(addr,3,temp);
cf95b4f0 3186 if (dops[i].opcode==0x22||dops[i].opcode==0x26) {
3968e69e 3187 emit_andimm(addr,0xFFFFFFFC,temp2); // LWL/LWR
3188 }else{
3189 emit_andimm(addr,0xFFFFFFF8,temp2); // LDL/LDR
3190 }
37387d8b 3191 jaddr = emit_fastpath_cmp_jump(i, i_regs, temp2,
277718fa 3192 &offset_reg, &fastio_reg_override, ccadj_);
3968e69e 3193 }
3194 else {
37387d8b 3195 if (ram_offset && memtarget) {
3196 offset_reg = get_ro_reg(i_regs, 0);
3968e69e 3197 }
cf95b4f0 3198 if (dops[i].opcode==0x22||dops[i].opcode==0x26) {
3968e69e 3199 emit_movimm(((constmap[i][s]+offset)<<3)&24,temp); // LWL/LWR
3200 }else{
3201 emit_movimm(((constmap[i][s]+offset)<<3)&56,temp); // LDL/LDR
3202 }
3203 }
cf95b4f0 3204 if (dops[i].opcode==0x22||dops[i].opcode==0x26) { // LWL/LWR
3968e69e 3205 if(!c||memtarget) {
37387d8b 3206 int a = temp2;
3207 if (fastio_reg_override >= 0)
3208 a = fastio_reg_override;
3209 do_load_word(a, temp2, offset_reg);
3210 if (fastio_reg_override == HOST_TEMPREG || offset_reg == HOST_TEMPREG)
3211 host_tempreg_release();
2330734f 3212 if(jaddr) add_stub_r(LOADW_STUB,jaddr,out,i,temp2,i_regs,ccadj_,reglist);
3968e69e 3213 }
3214 else
2330734f 3215 inline_readstub(LOADW_STUB,i,(constmap[i][s]+offset)&0xFFFFFFFC,i_regs->regmap,FTEMP,ccadj_,reglist);
cf95b4f0 3216 if(dops[i].rt1) {
3968e69e 3217 assert(tl>=0);
3218 emit_andimm(temp,24,temp);
cf95b4f0 3219 if (dops[i].opcode==0x22) // LWL
3968e69e 3220 emit_xorimm(temp,24,temp);
3221 host_tempreg_acquire();
3222 emit_movimm(-1,HOST_TEMPREG);
cf95b4f0 3223 if (dops[i].opcode==0x26) {
3968e69e 3224 emit_shr(temp2,temp,temp2);
3225 emit_bic_lsr(tl,HOST_TEMPREG,temp,tl);
3226 }else{
3227 emit_shl(temp2,temp,temp2);
3228 emit_bic_lsl(tl,HOST_TEMPREG,temp,tl);
3229 }
3230 host_tempreg_release();
3231 emit_or(temp2,tl,tl);
3232 }
cf95b4f0 3233 //emit_storereg(dops[i].rt1,tl); // DEBUG
3968e69e 3234 }
cf95b4f0 3235 if (dops[i].opcode==0x1A||dops[i].opcode==0x1B) { // LDL/LDR
3968e69e 3236 assert(0);
3237 }
57871462 3238}
3239#endif
3240
9b495f6e 3241static void do_invstub(int n)
3242{
3243 literal_pool(20);
684b6816 3244 assem_debug("do_invstub %x\n", start + stubs[n].e*4);
9b495f6e 3245 u_int reglist = stubs[n].a;
3246 u_int addrr = stubs[n].b;
3247 int ofs_start = stubs[n].c;
3248 int ofs_end = stubs[n].d;
3249 int len = ofs_end - ofs_start;
3250 u_int rightr = 0;
3251
3252 set_jump_target(stubs[n].addr, out);
3253 save_regs(reglist);
9b495f6e 3254 if (addrr != 0 || ofs_start != 0)
3255 emit_addimm(addrr, ofs_start, 0);
3033d898 3256 emit_readword(&inv_code_start, 2);
3257 emit_readword(&inv_code_end, 3);
9b495f6e 3258 if (len != 0)
3259 emit_addimm(0, len + 4, (rightr = 1));
3260 emit_cmp(0, 2);
3261 emit_cmpcs(3, rightr);
3262 void *jaddr = out;
3263 emit_jc(0);
3264 void *func = (len != 0)
3265 ? (void *)ndrc_write_invalidate_many
3266 : (void *)ndrc_write_invalidate_one;
3267 emit_far_call(func);
3268 set_jump_target(jaddr, out);
3269 restore_regs(reglist);
3270 emit_jmp(stubs[n].retaddr);
3271}
3272
3273static void do_store_smc_check(int i, const struct regstat *i_regs, u_int reglist, int addr)
3274{
3275 if (HACK_ENABLED(NDHACK_NO_SMC_CHECK))
3276 return;
3277 // this can't be used any more since we started to check exact
3278 // block boundaries in invalidate_range()
3279 //if (i_regs->waswritten & (1<<dops[i].rs1))
3280 // return;
3281 // (naively) assume nobody will run code from stack
3282 if (dops[i].rs1 == 29)
3283 return;
3284
277718fa 3285 int j, imm_maxdiff = 32, imm_min = cinfo[i].imm, imm_max = cinfo[i].imm, count = 1;
9b495f6e 3286 if (i < slen - 1 && dops[i+1].is_store && dops[i+1].rs1 == dops[i].rs1
277718fa 3287 && abs(cinfo[i+1].imm - cinfo[i].imm) <= imm_maxdiff)
9b495f6e 3288 return;
3289 for (j = i - 1; j >= 0; j--) {
3290 if (!dops[j].is_store || dops[j].rs1 != dops[i].rs1
277718fa 3291 || abs(cinfo[j].imm - cinfo[j+1].imm) > imm_maxdiff)
9b495f6e 3292 break;
3293 count++;
277718fa 3294 if (imm_min > cinfo[j].imm)
3295 imm_min = cinfo[j].imm;
3296 if (imm_max < cinfo[j].imm)
3297 imm_max = cinfo[j].imm;
9b495f6e 3298 }
3299#if defined(HOST_IMM8)
3300 int ir = get_reg(i_regs->regmap, INVCP);
3301 assert(ir >= 0);
3302 host_tempreg_acquire();
3303 emit_ldrb_indexedsr12_reg(ir, addr, HOST_TEMPREG);
3304#else
3305 emit_cmpmem_indexedsr12_imm(invalid_code, addr, 1);
3306 #error not handled
3307#endif
3308#ifdef INVALIDATE_USE_COND_CALL
3309 if (count == 1) {
3310 emit_cmpimm(HOST_TEMPREG, 1);
3311 emit_callne(invalidate_addr_reg[addr]);
3312 host_tempreg_release();
3313 return;
3314 }
3315#endif
3316 void *jaddr = emit_cbz(HOST_TEMPREG, 0);
3317 host_tempreg_release();
277718fa 3318 imm_min -= cinfo[i].imm;
3319 imm_max -= cinfo[i].imm;
9b495f6e 3320 add_stub(INVCODE_STUB, jaddr, out, reglist|(1<<HOST_CCREG),
684b6816 3321 addr, imm_min, imm_max, i);
9b495f6e 3322}
3323
684b6816 3324// determines if code overwrite checking is needed only
3325// (also true non-existent 0x20000000 mirror that shouldn't matter)
3326#define is_ram_addr(a) !((a) & 0x5f800000)
3327
2330734f 3328static void store_assemble(int i, const struct regstat *i_regs, int ccadj_)
57871462 3329{
9c45ca93 3330 int s,tl;
277718fa 3331 int addr = cinfo[i].addr;
57871462 3332 int offset;
b14b6a8f 3333 void *jaddr=0;
37387d8b 3334 enum stub_type type=0;
666a299d 3335 int memtarget=0,c=0;
37387d8b 3336 int offset_reg = -1;
3337 int fastio_reg_override = -1;
684b6816 3338 u_int addr_const = ~0;
81dbbf4c 3339 u_int reglist=get_host_reglist(i_regs->regmap);
cf95b4f0 3340 tl=get_reg(i_regs->regmap,dops[i].rs2);
3341 s=get_reg(i_regs->regmap,dops[i].rs1);
277718fa 3342 offset=cinfo[i].imm;
57871462 3343 if(s>=0) {
3344 c=(i_regs->wasconst>>s)&1;
684b6816 3345 if (c) {
3346 addr_const = constmap[i][s] + offset;
3347 memtarget = ((signed int)addr_const) < (signed int)(0x80000000 + RAM_SIZE);
af4ee1fe 3348 }
57871462 3349 }
3350 assert(tl>=0);
277718fa 3351 assert(addr >= 0);
57871462 3352 if(i_regs->regmap[HOST_CCREG]==CCREG) reglist&=~(1<<HOST_CCREG);
684b6816 3353 reglist |= 1u << addr;
37387d8b 3354 if (!c) {
3355 jaddr = emit_fastpath_cmp_jump(i, i_regs, addr,
277718fa 3356 &offset_reg, &fastio_reg_override, ccadj_);
1edfcc68 3357 }
37387d8b 3358 else if (ram_offset && memtarget) {
3359 offset_reg = get_ro_reg(i_regs, 0);
57871462 3360 }
3361
37387d8b 3362 switch (dops[i].opcode) {
3363 case 0x28: // SB
57871462 3364 if(!c||memtarget) {
277718fa 3365 int a = addr;
37387d8b 3366 if (fastio_reg_override >= 0)
3367 a = fastio_reg_override;
3368 do_store_byte(a, tl, offset_reg);
3369 }
3370 type = STOREB_STUB;
3371 break;
3372 case 0x29: // SH
57871462 3373 if(!c||memtarget) {
277718fa 3374 int a = addr;
37387d8b 3375 if (fastio_reg_override >= 0)
3376 a = fastio_reg_override;
3377 do_store_hword(a, 0, tl, offset_reg, 1);
3378 }
3379 type = STOREH_STUB;
3380 break;
3381 case 0x2B: // SW
dadf55f2 3382 if(!c||memtarget) {
37387d8b 3383 int a = addr;
3384 if (fastio_reg_override >= 0)
3385 a = fastio_reg_override;
3386 do_store_word(a, 0, tl, offset_reg, 1);
3387 }
3388 type = STOREW_STUB;
3389 break;
37387d8b 3390 default:
9c45ca93 3391 assert(0);
57871462 3392 }
37387d8b 3393 if (fastio_reg_override == HOST_TEMPREG || offset_reg == HOST_TEMPREG)
d1e4ebd9 3394 host_tempreg_release();
684b6816 3395 if (jaddr) {
b96d3df7 3396 // PCSX store handlers don't check invcode again
2330734f 3397 add_stub_r(type,jaddr,out,i,addr,i_regs,ccadj_,reglist);
7a518516 3398 }
684b6816 3399 if (!c || is_ram_addr(addr_const))
3400 do_store_smc_check(i, i_regs, reglist, addr);
3401 if (c && !memtarget)
3402 inline_writestub(type, i, addr_const, i_regs->regmap, dops[i].rs2, ccadj_, reglist);
7a518516 3403 // basic current block modification detection..
3404 // not looking back as that should be in mips cache already
3968e69e 3405 // (see Spyro2 title->attract mode)
684b6816 3406 if (start + i*4 < addr_const && addr_const < start + slen*4) {
3407 SysPrintf("write to %08x hits block %08x, pc=%08x\n", addr_const, start, start+i*4);
7a518516 3408 assert(i_regs->regmap==regs[i].regmap); // not delay slot
3409 if(i_regs->regmap==regs[i].regmap) {
ad49de89 3410 load_all_consts(regs[i].regmap_entry,regs[i].wasdirty,i);
3411 wb_dirtys(regs[i].regmap_entry,regs[i].wasdirty);
7a518516 3412 emit_movimm(start+i*4+4,0);
643aeae3 3413 emit_writeword(0,&pcaddr);
d1e4ebd9 3414 emit_addimm(HOST_CCREG,2,HOST_CCREG);
104df9d3 3415 emit_far_call(ndrc_get_addr_ht);
d1e4ebd9 3416 emit_jmpreg(0);
7a518516 3417 }
3eaa7048 3418 }
57871462 3419}
3420
2330734f 3421static void storelr_assemble(int i, const struct regstat *i_regs, int ccadj_)
57871462 3422{
277718fa 3423 int addr = cinfo[i].addr;
9c45ca93 3424 int s,tl;
57871462 3425 int offset;
b14b6a8f 3426 void *jaddr=0;
37387d8b 3427 void *case1, *case23, *case3;
df4dc2b1 3428 void *done0, *done1, *done2;
af4ee1fe 3429 int memtarget=0,c=0;
37387d8b 3430 int offset_reg = -1;
684b6816 3431 u_int addr_const = ~0;
3432 u_int reglist = get_host_reglist(i_regs->regmap);
cf95b4f0 3433 tl=get_reg(i_regs->regmap,dops[i].rs2);
3434 s=get_reg(i_regs->regmap,dops[i].rs1);
277718fa 3435 offset=cinfo[i].imm;
57871462 3436 if(s>=0) {
684b6816 3437 c = (i_regs->isconst >> s) & 1;
3438 if (c) {
3439 addr_const = constmap[i][s] + offset;
3440 memtarget = ((signed int)addr_const) < (signed int)(0x80000000 + RAM_SIZE);
af4ee1fe 3441 }
57871462 3442 }
3443 assert(tl>=0);
277718fa 3444 assert(addr >= 0);
684b6816 3445 reglist |= 1u << addr;
1edfcc68 3446 if(!c) {
277718fa 3447 emit_cmpimm(addr, RAM_SIZE);
b14b6a8f 3448 jaddr=out;
1edfcc68 3449 emit_jno(0);
3450 }
3451 else
3452 {
cf95b4f0 3453 if(!memtarget||!dops[i].rs1) {
b14b6a8f 3454 jaddr=out;
535d208a 3455 emit_jmp(0);
57871462 3456 }
535d208a 3457 }
37387d8b 3458 if (ram_offset)
3459 offset_reg = get_ro_reg(i_regs, 0);
535d208a 3460
277718fa 3461 emit_testimm(addr,2);
37387d8b 3462 case23=out;
535d208a 3463 emit_jne(0);
277718fa 3464 emit_testimm(addr,1);
df4dc2b1 3465 case1=out;
535d208a 3466 emit_jne(0);
3467 // 0
37387d8b 3468 if (dops[i].opcode == 0x2A) { // SWL
3469 // Write msb into least significant byte
3470 if (dops[i].rs2) emit_rorimm(tl, 24, tl);
277718fa 3471 do_store_byte(addr, tl, offset_reg);
37387d8b 3472 if (dops[i].rs2) emit_rorimm(tl, 8, tl);
535d208a 3473 }
37387d8b 3474 else if (dops[i].opcode == 0x2E) { // SWR
3475 // Write entire word
277718fa 3476 do_store_word(addr, 0, tl, offset_reg, 1);
535d208a 3477 }
37387d8b 3478 done0 = out;
535d208a 3479 emit_jmp(0);
3480 // 1
df4dc2b1 3481 set_jump_target(case1, out);
37387d8b 3482 if (dops[i].opcode == 0x2A) { // SWL
3483 // Write two msb into two least significant bytes
3484 if (dops[i].rs2) emit_rorimm(tl, 16, tl);
684b6816 3485 do_store_hword(addr, -1, tl, offset_reg, 1);
37387d8b 3486 if (dops[i].rs2) emit_rorimm(tl, 16, tl);
535d208a 3487 }
37387d8b 3488 else if (dops[i].opcode == 0x2E) { // SWR
3489 // Write 3 lsb into three most significant bytes
277718fa 3490 do_store_byte(addr, tl, offset_reg);
37387d8b 3491 if (dops[i].rs2) emit_rorimm(tl, 8, tl);
684b6816 3492 do_store_hword(addr, 1, tl, offset_reg, 1);
37387d8b 3493 if (dops[i].rs2) emit_rorimm(tl, 24, tl);
535d208a 3494 }
df4dc2b1 3495 done1=out;
535d208a 3496 emit_jmp(0);
37387d8b 3497 // 2,3
3498 set_jump_target(case23, out);
277718fa 3499 emit_testimm(addr,1);
37387d8b 3500 case3 = out;
535d208a 3501 emit_jne(0);
37387d8b 3502 // 2
cf95b4f0 3503 if (dops[i].opcode==0x2A) { // SWL
37387d8b 3504 // Write 3 msb into three least significant bytes
3505 if (dops[i].rs2) emit_rorimm(tl, 8, tl);
277718fa 3506 do_store_hword(addr, -2, tl, offset_reg, 1);
37387d8b 3507 if (dops[i].rs2) emit_rorimm(tl, 16, tl);
277718fa 3508 do_store_byte(addr, tl, offset_reg);
37387d8b 3509 if (dops[i].rs2) emit_rorimm(tl, 8, tl);
535d208a 3510 }
37387d8b 3511 else if (dops[i].opcode == 0x2E) { // SWR
3512 // Write two lsb into two most significant bytes
277718fa 3513 do_store_hword(addr, 0, tl, offset_reg, 1);
535d208a 3514 }
37387d8b 3515 done2 = out;
535d208a 3516 emit_jmp(0);
3517 // 3
df4dc2b1 3518 set_jump_target(case3, out);
37387d8b 3519 if (dops[i].opcode == 0x2A) { // SWL
684b6816 3520 do_store_word(addr, -3, tl, offset_reg, 1);
535d208a 3521 }
37387d8b 3522 else if (dops[i].opcode == 0x2E) { // SWR
277718fa 3523 do_store_byte(addr, tl, offset_reg);
535d208a 3524 }
df4dc2b1 3525 set_jump_target(done0, out);
3526 set_jump_target(done1, out);
3527 set_jump_target(done2, out);
37387d8b 3528 if (offset_reg == HOST_TEMPREG)
3529 host_tempreg_release();
684b6816 3530 if (!c || !memtarget)
277718fa 3531 add_stub_r(STORELR_STUB,jaddr,out,i,addr,i_regs,ccadj_,reglist);
684b6816 3532 if (!c || is_ram_addr(addr_const))
3533 do_store_smc_check(i, i_regs, reglist, addr);
57871462 3534}
3535
2330734f 3536static void cop0_assemble(int i, const struct regstat *i_regs, int ccadj_)
8062d65a 3537{
cf95b4f0 3538 if(dops[i].opcode2==0) // MFC0
8062d65a 3539 {
a5cd72d0 3540 signed char t=get_reg_w(i_regs->regmap, dops[i].rt1);
8062d65a 3541 u_int copr=(source[i]>>11)&0x1f;
cf95b4f0 3542 if(t>=0&&dops[i].rt1!=0) {
8062d65a 3543 emit_readword(&reg_cop0[copr],t);
3544 }
3545 }
cf95b4f0 3546 else if(dops[i].opcode2==4) // MTC0
8062d65a 3547 {
de6dbc52 3548 int s = get_reg(i_regs->regmap, dops[i].rs1);
3549 int cc = get_reg(i_regs->regmap, CCREG);
8062d65a 3550 char copr=(source[i]>>11)&0x1f;
3551 assert(s>=0);
cf95b4f0 3552 wb_register(dops[i].rs1,i_regs->regmap,i_regs->dirty);
de6dbc52 3553 if (copr == 12 || copr == 13) {
8062d65a 3554 emit_readword(&last_count,HOST_TEMPREG);
de6dbc52 3555 if (cc != HOST_CCREG)
3556 emit_loadreg(CCREG, HOST_CCREG);
3557 emit_add(HOST_CCREG, HOST_TEMPREG, HOST_CCREG);
3558 emit_addimm(HOST_CCREG, ccadj_ + 2, HOST_CCREG);
3559 emit_writeword(HOST_CCREG, &psxRegs.cycle);
8062d65a 3560 if (is_delayslot) {
3561 // burn cycles to cause cc_interrupt, which will
3562 // reschedule next_interupt. Relies on CCREG from above.
3563 assem_debug("MTC0 DS %d\n", copr);
3564 emit_writeword(HOST_CCREG,&last_count);
3565 emit_movimm(0,HOST_CCREG);
3566 emit_storereg(CCREG,HOST_CCREG);
cf95b4f0 3567 emit_loadreg(dops[i].rs1,1);
8062d65a 3568 emit_movimm(copr,0);
2a014d73 3569 emit_far_call(pcsx_mtc0_ds);
cf95b4f0 3570 emit_loadreg(dops[i].rs1,s);
8062d65a 3571 return;
3572 }
3573 emit_movimm(start+i*4+4,HOST_TEMPREG);
3574 emit_writeword(HOST_TEMPREG,&pcaddr);
3575 emit_movimm(0,HOST_TEMPREG);
3576 emit_writeword(HOST_TEMPREG,&pending_exception);
3577 }
de6dbc52 3578 if( s != 1)
3579 emit_mov(s, 1);
3580 emit_movimm(copr, 0);
2a014d73 3581 emit_far_call(pcsx_mtc0);
de6dbc52 3582 if (copr == 12 || copr == 13) {
d7546062 3583 emit_readword(&psxRegs.cycle,HOST_CCREG);
de6dbc52 3584 emit_readword(&last_count,HOST_TEMPREG);
8062d65a 3585 emit_sub(HOST_CCREG,HOST_TEMPREG,HOST_CCREG);
de6dbc52 3586 //emit_writeword(HOST_TEMPREG,&last_count);
8062d65a 3587 assert(!is_delayslot);
9b495f6e 3588 emit_readword(&pending_exception,HOST_TEMPREG);
3589 emit_test(HOST_TEMPREG,HOST_TEMPREG);
d1e4ebd9 3590 void *jaddr = out;
3591 emit_jeq(0);
3592 emit_readword(&pcaddr, 0);
104df9d3 3593 emit_far_call(ndrc_get_addr_ht);
d1e4ebd9 3594 emit_jmpreg(0);
3595 set_jump_target(jaddr, out);
de6dbc52 3596 emit_addimm(HOST_CCREG, -ccadj_ - 2, HOST_CCREG);
3597 if (cc != HOST_CCREG)
3598 emit_storereg(CCREG, HOST_CCREG);
8062d65a 3599 }
cf95b4f0 3600 emit_loadreg(dops[i].rs1,s);
8062d65a 3601 }
8062d65a 3602}
3603
277718fa 3604static void rfe_assemble(int i, const struct regstat *i_regs)
8062d65a 3605{
a5cd72d0 3606 emit_readword(&psxRegs.CP0.n.SR, 0);
3607 emit_andimm(0, 0x3c, 1);
3608 emit_andimm(0, ~0xf, 0);
3609 emit_orrshr_imm(1, 2, 0);
3610 emit_writeword(0, &psxRegs.CP0.n.SR);
8062d65a 3611}
3612
e3c6bdb5 3613static int cop2_is_stalling_op(int i, int *cycles)
3614{
cf95b4f0 3615 if (dops[i].opcode == 0x3a) { // SWC2
e3c6bdb5 3616 *cycles = 0;
3617 return 1;
3618 }
cf95b4f0 3619 if (dops[i].itype == COP2 && (dops[i].opcode2 == 0 || dops[i].opcode2 == 2)) { // MFC2/CFC2
e3c6bdb5 3620 *cycles = 0;
3621 return 1;
3622 }
cf95b4f0 3623 if (dops[i].itype == C2OP) {
e3c6bdb5 3624 *cycles = gte_cycletab[source[i] & 0x3f];
3625 return 1;
3626 }
3627 // ... what about MTC2/CTC2/LWC2?
3628 return 0;
3629}
3630
3631#if 0
3632static void log_gte_stall(int stall, u_int cycle)
3633{
3634 if ((u_int)stall <= 44)
3635 printf("x stall %2d %u\n", stall, cycle + last_count);
e3c6bdb5 3636}
3637
3638static void emit_log_gte_stall(int i, int stall, u_int reglist)
3639{
3640 save_regs(reglist);
3641 if (stall > 0)
3642 emit_movimm(stall, 0);
3643 else
3644 emit_mov(HOST_TEMPREG, 0);
277718fa 3645 emit_addimm(HOST_CCREG, cinfo[i].ccadj, 1);
e3c6bdb5 3646 emit_far_call(log_gte_stall);
3647 restore_regs(reglist);
3648}
3649#endif
3650
32631e6a 3651static void cop2_do_stall_check(u_int op, int i, const struct regstat *i_regs, u_int reglist)
81dbbf4c 3652{
e3c6bdb5 3653 int j = i, other_gte_op_cycles = -1, stall = -MAXBLOCK, cycles_passed;
3654 int rtmp = reglist_find_free(reglist);
3655
32631e6a 3656 if (HACK_ENABLED(NDHACK_NO_STALLS))
81dbbf4c 3657 return;
81dbbf4c 3658 if (get_reg(i_regs->regmap, CCREG) != HOST_CCREG) {
3659 // happens occasionally... cc evicted? Don't bother then
3660 //printf("no cc %08x\n", start + i*4);
3661 return;
3662 }
cf95b4f0 3663 if (!dops[i].bt) {
e3c6bdb5 3664 for (j = i - 1; j >= 0; j--) {
cf95b4f0 3665 //if (dops[j].is_ds) break;
3666 if (cop2_is_stalling_op(j, &other_gte_op_cycles) || dops[j].bt)
e3c6bdb5 3667 break;
277718fa 3668 if (j > 0 && cinfo[j - 1].ccadj > cinfo[j].ccadj)
2330734f 3669 break;
e3c6bdb5 3670 }
32631e6a 3671 j = max(j, 0);
e3c6bdb5 3672 }
277718fa 3673 cycles_passed = cinfo[i].ccadj - cinfo[j].ccadj;
e3c6bdb5 3674 if (other_gte_op_cycles >= 0)
3675 stall = other_gte_op_cycles - cycles_passed;
3676 else if (cycles_passed >= 44)
3677 stall = 0; // can't stall
3678 if (stall == -MAXBLOCK && rtmp >= 0) {
3679 // unknown stall, do the expensive runtime check
32631e6a 3680 assem_debug("; cop2_do_stall_check\n");
e3c6bdb5 3681#if 0 // too slow
3682 save_regs(reglist);
3683 emit_movimm(gte_cycletab[op], 0);
277718fa 3684 emit_addimm(HOST_CCREG, cinfo[i].ccadj, 1);
e3c6bdb5 3685 emit_far_call(call_gteStall);
3686 restore_regs(reglist);
3687#else
3688 host_tempreg_acquire();
3689 emit_readword(&psxRegs.gteBusyCycle, rtmp);
277718fa 3690 emit_addimm(rtmp, -cinfo[i].ccadj, rtmp);
e3c6bdb5 3691 emit_sub(rtmp, HOST_CCREG, HOST_TEMPREG);
3692 emit_cmpimm(HOST_TEMPREG, 44);
3693 emit_cmovb_reg(rtmp, HOST_CCREG);
3694 //emit_log_gte_stall(i, 0, reglist);
3695 host_tempreg_release();
3696#endif
3697 }
3698 else if (stall > 0) {
3699 //emit_log_gte_stall(i, stall, reglist);
3700 emit_addimm(HOST_CCREG, stall, HOST_CCREG);
3701 }
3702
3703 // save gteBusyCycle, if needed
3704 if (gte_cycletab[op] == 0)
3705 return;
3706 other_gte_op_cycles = -1;
3707 for (j = i + 1; j < slen; j++) {
3708 if (cop2_is_stalling_op(j, &other_gte_op_cycles))
3709 break;
fe807a8a 3710 if (dops[j].is_jump) {
e3c6bdb5 3711 // check ds
3712 if (j + 1 < slen && cop2_is_stalling_op(j + 1, &other_gte_op_cycles))
3713 j++;
3714 break;
3715 }
3716 }
3717 if (other_gte_op_cycles >= 0)
3718 // will handle stall when assembling that op
3719 return;
277718fa 3720 cycles_passed = cinfo[min(j, slen -1)].ccadj - cinfo[i].ccadj;
e3c6bdb5 3721 if (cycles_passed >= 44)
3722 return;
3723 assem_debug("; save gteBusyCycle\n");
3724 host_tempreg_acquire();
3725#if 0
3726 emit_readword(&last_count, HOST_TEMPREG);
3727 emit_add(HOST_TEMPREG, HOST_CCREG, HOST_TEMPREG);
277718fa 3728 emit_addimm(HOST_TEMPREG, cinfo[i].ccadj, HOST_TEMPREG);
e3c6bdb5 3729 emit_addimm(HOST_TEMPREG, gte_cycletab[op]), HOST_TEMPREG);
3730 emit_writeword(HOST_TEMPREG, &psxRegs.gteBusyCycle);
3731#else
277718fa 3732 emit_addimm(HOST_CCREG, cinfo[i].ccadj + gte_cycletab[op], HOST_TEMPREG);
e3c6bdb5 3733 emit_writeword(HOST_TEMPREG, &psxRegs.gteBusyCycle);
3734#endif
3735 host_tempreg_release();
81dbbf4c 3736}
3737
32631e6a 3738static int is_mflohi(int i)
3739{
cf95b4f0 3740 return (dops[i].itype == MOV && (dops[i].rs1 == HIREG || dops[i].rs1 == LOREG));
32631e6a 3741}
3742
3743static int check_multdiv(int i, int *cycles)
3744{
cf95b4f0 3745 if (dops[i].itype != MULTDIV)
32631e6a 3746 return 0;
cf95b4f0 3747 if (dops[i].opcode2 == 0x18 || dops[i].opcode2 == 0x19) // MULT(U)
32631e6a 3748 *cycles = 11; // approx from 7 11 14
3749 else
3750 *cycles = 37;
3751 return 1;
3752}
3753
2330734f 3754static void multdiv_prepare_stall(int i, const struct regstat *i_regs, int ccadj_)
32631e6a 3755{
3756 int j, found = 0, c = 0;
3757 if (HACK_ENABLED(NDHACK_NO_STALLS))
3758 return;
3759 if (get_reg(i_regs->regmap, CCREG) != HOST_CCREG) {
3760 // happens occasionally... cc evicted? Don't bother then
3761 return;
3762 }
3763 for (j = i + 1; j < slen; j++) {
cf95b4f0 3764 if (dops[j].bt)
32631e6a 3765 break;
3766 if ((found = is_mflohi(j)))
3767 break;
fe807a8a 3768 if (dops[j].is_jump) {
32631e6a 3769 // check ds
3770 if (j + 1 < slen && (found = is_mflohi(j + 1)))
3771 j++;
3772 break;
3773 }
3774 }
3775 if (found)
3776 // handle all in multdiv_do_stall()
3777 return;
3778 check_multdiv(i, &c);
3779 assert(c > 0);
3780 assem_debug("; muldiv prepare stall %d\n", c);
3781 host_tempreg_acquire();
2330734f 3782 emit_addimm(HOST_CCREG, ccadj_ + c, HOST_TEMPREG);
32631e6a 3783 emit_writeword(HOST_TEMPREG, &psxRegs.muldivBusyCycle);
3784 host_tempreg_release();
3785}
3786
3787static void multdiv_do_stall(int i, const struct regstat *i_regs)
3788{
3789 int j, known_cycles = 0;
3790 u_int reglist = get_host_reglist(i_regs->regmap);
9de8a0c3 3791 int rtmp = get_reg_temp(i_regs->regmap);
32631e6a 3792 if (rtmp < 0)
3793 rtmp = reglist_find_free(reglist);
3794 if (HACK_ENABLED(NDHACK_NO_STALLS))
3795 return;
3796 if (get_reg(i_regs->regmap, CCREG) != HOST_CCREG || rtmp < 0) {
3797 // happens occasionally... cc evicted? Don't bother then
3798 //printf("no cc/rtmp %08x\n", start + i*4);
3799 return;
3800 }
cf95b4f0 3801 if (!dops[i].bt) {
32631e6a 3802 for (j = i - 1; j >= 0; j--) {
cf95b4f0 3803 if (dops[j].is_ds) break;
2330734f 3804 if (check_multdiv(j, &known_cycles))
32631e6a 3805 break;
3806 if (is_mflohi(j))
3807 // already handled by this op
3808 return;
277718fa 3809 if (dops[j].bt || (j > 0 && cinfo[j - 1].ccadj > cinfo[j].ccadj))
2330734f 3810 break;
32631e6a 3811 }
3812 j = max(j, 0);
3813 }
3814 if (known_cycles > 0) {
277718fa 3815 known_cycles -= cinfo[i].ccadj - cinfo[j].ccadj;
32631e6a 3816 assem_debug("; muldiv stall resolved %d\n", known_cycles);
3817 if (known_cycles > 0)
3818 emit_addimm(HOST_CCREG, known_cycles, HOST_CCREG);
3819 return;
3820 }
3821 assem_debug("; muldiv stall unresolved\n");
3822 host_tempreg_acquire();
3823 emit_readword(&psxRegs.muldivBusyCycle, rtmp);
277718fa 3824 emit_addimm(rtmp, -cinfo[i].ccadj, rtmp);
32631e6a 3825 emit_sub(rtmp, HOST_CCREG, HOST_TEMPREG);
3826 emit_cmpimm(HOST_TEMPREG, 37);
3827 emit_cmovb_reg(rtmp, HOST_CCREG);
3828 //emit_log_gte_stall(i, 0, reglist);
3829 host_tempreg_release();
3830}
3831
8062d65a 3832static void cop2_get_dreg(u_int copr,signed char tl,signed char temp)
3833{
3834 switch (copr) {
3835 case 1:
3836 case 3:
3837 case 5:
3838 case 8:
3839 case 9:
3840 case 10:
3841 case 11:
3842 emit_readword(&reg_cop2d[copr],tl);
3843 emit_signextend16(tl,tl);
3844 emit_writeword(tl,&reg_cop2d[copr]); // hmh
3845 break;
3846 case 7:
3847 case 16:
3848 case 17:
3849 case 18:
3850 case 19:
3851 emit_readword(&reg_cop2d[copr],tl);
3852 emit_andimm(tl,0xffff,tl);
3853 emit_writeword(tl,&reg_cop2d[copr]);
3854 break;
3855 case 15:
3856 emit_readword(&reg_cop2d[14],tl); // SXY2
3857 emit_writeword(tl,&reg_cop2d[copr]);
3858 break;
3859 case 28:
3860 case 29:
3968e69e 3861 c2op_mfc2_29_assemble(tl,temp);
8062d65a 3862 break;
3863 default:
3864 emit_readword(&reg_cop2d[copr],tl);
3865 break;
3866 }
3867}
3868
3869static void cop2_put_dreg(u_int copr,signed char sl,signed char temp)
3870{
3871 switch (copr) {
3872 case 15:
3873 emit_readword(&reg_cop2d[13],temp); // SXY1
3874 emit_writeword(sl,&reg_cop2d[copr]);
3875 emit_writeword(temp,&reg_cop2d[12]); // SXY0
3876 emit_readword(&reg_cop2d[14],temp); // SXY2
3877 emit_writeword(sl,&reg_cop2d[14]);
3878 emit_writeword(temp,&reg_cop2d[13]); // SXY1
3879 break;
3880 case 28:
3881 emit_andimm(sl,0x001f,temp);
3882 emit_shlimm(temp,7,temp);
3883 emit_writeword(temp,&reg_cop2d[9]);
3884 emit_andimm(sl,0x03e0,temp);
3885 emit_shlimm(temp,2,temp);
3886 emit_writeword(temp,&reg_cop2d[10]);
3887 emit_andimm(sl,0x7c00,temp);
3888 emit_shrimm(temp,3,temp);
3889 emit_writeword(temp,&reg_cop2d[11]);
3890 emit_writeword(sl,&reg_cop2d[28]);
3891 break;
3892 case 30:
3968e69e 3893 emit_xorsar_imm(sl,sl,31,temp);
be516ebe 3894#if defined(HAVE_ARMV5) || defined(__aarch64__)
8062d65a 3895 emit_clz(temp,temp);
3896#else
3897 emit_movs(temp,HOST_TEMPREG);
3898 emit_movimm(0,temp);
3899 emit_jeq((int)out+4*4);
3900 emit_addpl_imm(temp,1,temp);
3901 emit_lslpls_imm(HOST_TEMPREG,1,HOST_TEMPREG);
3902 emit_jns((int)out-2*4);
3903#endif
3904 emit_writeword(sl,&reg_cop2d[30]);
3905 emit_writeword(temp,&reg_cop2d[31]);
3906 break;
3907 case 31:
3908 break;
3909 default:
3910 emit_writeword(sl,&reg_cop2d[copr]);
3911 break;
3912 }
3913}
3914
2330734f 3915static void c2ls_assemble(int i, const struct regstat *i_regs, int ccadj_)
b9b61529 3916{
3917 int s,tl;
3918 int ar;
3919 int offset;
1fd1aceb 3920 int memtarget=0,c=0;
b14b6a8f 3921 void *jaddr2=NULL;
3922 enum stub_type type;
37387d8b 3923 int offset_reg = -1;
3924 int fastio_reg_override = -1;
684b6816 3925 u_int addr_const = ~0;
81dbbf4c 3926 u_int reglist=get_host_reglist(i_regs->regmap);
b9b61529 3927 u_int copr=(source[i]>>16)&0x1f;
cf95b4f0 3928 s=get_reg(i_regs->regmap,dops[i].rs1);
b9b61529 3929 tl=get_reg(i_regs->regmap,FTEMP);
277718fa 3930 offset=cinfo[i].imm;
b9b61529 3931 assert(tl>=0);
b9b61529 3932
b9b61529 3933 if(i_regs->regmap[HOST_CCREG]==CCREG)
3934 reglist&=~(1<<HOST_CCREG);
3935
3936 // get the address
277718fa 3937 ar = cinfo[i].addr;
3938 assert(ar >= 0);
cf95b4f0 3939 if (dops[i].opcode==0x3a) { // SWC2
277718fa 3940 reglist |= 1<<ar;
b9b61529 3941 }
684b6816 3942 if (s >= 0) {
3943 c = (i_regs->isconst >> s) & 1;
3944 if (c) {
3945 addr_const = constmap[i][s] + offset;
3946 memtarget = ((signed int)addr_const) < (signed int)(0x80000000 + RAM_SIZE);
3947 }
3948 }
b9b61529 3949
32631e6a 3950 cop2_do_stall_check(0, i, i_regs, reglist);
3951
cf95b4f0 3952 if (dops[i].opcode==0x3a) { // SWC2
3968e69e 3953 cop2_get_dreg(copr,tl,-1);
1fd1aceb 3954 type=STOREW_STUB;
b9b61529 3955 }
1fd1aceb 3956 else
b9b61529 3957 type=LOADW_STUB;
1fd1aceb 3958
3959 if(c&&!memtarget) {
b14b6a8f 3960 jaddr2=out;
1fd1aceb 3961 emit_jmp(0); // inline_readstub/inline_writestub?
b9b61529 3962 }
1fd1aceb 3963 else {
3964 if(!c) {
37387d8b 3965 jaddr2 = emit_fastpath_cmp_jump(i, i_regs, ar,
277718fa 3966 &offset_reg, &fastio_reg_override, ccadj_);
37387d8b 3967 }
3968 else if (ram_offset && memtarget) {
3969 offset_reg = get_ro_reg(i_regs, 0);
3970 }
3971 switch (dops[i].opcode) {
3972 case 0x32: { // LWC2
3973 int a = ar;
3974 if (fastio_reg_override >= 0)
3975 a = fastio_reg_override;
3976 do_load_word(a, tl, offset_reg);
3977 break;
1fd1aceb 3978 }
37387d8b 3979 case 0x3a: { // SWC2
1fd1aceb 3980 #ifdef DESTRUCTIVE_SHIFT
3981 if(!offset&&!c&&s>=0) emit_mov(s,ar);
3982 #endif
37387d8b 3983 int a = ar;
3984 if (fastio_reg_override >= 0)
3985 a = fastio_reg_override;
3986 do_store_word(a, 0, tl, offset_reg, 1);
3987 break;
3988 }
3989 default:
3990 assert(0);
1fd1aceb 3991 }
b9b61529 3992 }
37387d8b 3993 if (fastio_reg_override == HOST_TEMPREG || offset_reg == HOST_TEMPREG)
d1e4ebd9 3994 host_tempreg_release();
b9b61529 3995 if(jaddr2)
2330734f 3996 add_stub_r(type,jaddr2,out,i,ar,i_regs,ccadj_,reglist);
684b6816 3997 if (dops[i].opcode == 0x3a && (!c || is_ram_addr(addr_const))) // SWC2
9b495f6e 3998 do_store_smc_check(i, i_regs, reglist, ar);
684b6816 3999 if (dops[i].opcode == 0x32) { // LWC2
d1e4ebd9 4000 host_tempreg_acquire();
b9b61529 4001 cop2_put_dreg(copr,tl,HOST_TEMPREG);
d1e4ebd9 4002 host_tempreg_release();
b9b61529 4003 }
4004}
4005
81dbbf4c 4006static void cop2_assemble(int i, const struct regstat *i_regs)
8062d65a 4007{
81dbbf4c 4008 u_int copr = (source[i]>>11) & 0x1f;
9de8a0c3 4009 signed char temp = get_reg_temp(i_regs->regmap);
81dbbf4c 4010
32631e6a 4011 if (!HACK_ENABLED(NDHACK_NO_STALLS)) {
4012 u_int reglist = reglist_exclude(get_host_reglist(i_regs->regmap), temp, -1);
cf95b4f0 4013 if (dops[i].opcode2 == 0 || dops[i].opcode2 == 2) { // MFC2/CFC2
4014 signed char tl = get_reg(i_regs->regmap, dops[i].rt1);
32631e6a 4015 reglist = reglist_exclude(reglist, tl, -1);
81dbbf4c 4016 }
32631e6a 4017 cop2_do_stall_check(0, i, i_regs, reglist);
81dbbf4c 4018 }
cf95b4f0 4019 if (dops[i].opcode2==0) { // MFC2
a5cd72d0 4020 signed char tl=get_reg_w(i_regs->regmap, dops[i].rt1);
cf95b4f0 4021 if(tl>=0&&dops[i].rt1!=0)
8062d65a 4022 cop2_get_dreg(copr,tl,temp);
4023 }
cf95b4f0 4024 else if (dops[i].opcode2==4) { // MTC2
4025 signed char sl=get_reg(i_regs->regmap,dops[i].rs1);
8062d65a 4026 cop2_put_dreg(copr,sl,temp);
4027 }
cf95b4f0 4028 else if (dops[i].opcode2==2) // CFC2
8062d65a 4029 {
a5cd72d0 4030 signed char tl=get_reg_w(i_regs->regmap, dops[i].rt1);
cf95b4f0 4031 if(tl>=0&&dops[i].rt1!=0)
8062d65a 4032 emit_readword(&reg_cop2c[copr],tl);
4033 }
cf95b4f0 4034 else if (dops[i].opcode2==6) // CTC2
8062d65a 4035 {
cf95b4f0 4036 signed char sl=get_reg(i_regs->regmap,dops[i].rs1);
8062d65a 4037 switch(copr) {
4038 case 4:
4039 case 12:
4040 case 20:
4041 case 26:
4042 case 27:
4043 case 29:
4044 case 30:
4045 emit_signextend16(sl,temp);
4046 break;
4047 case 31:
3968e69e 4048 c2op_ctc2_31_assemble(sl,temp);
8062d65a 4049 break;
4050 default:
4051 temp=sl;
4052 break;
4053 }
4054 emit_writeword(temp,&reg_cop2c[copr]);
4055 assert(sl>=0);
4056 }
4057}
4058
3968e69e 4059static void do_unalignedwritestub(int n)
4060{
4061 assem_debug("do_unalignedwritestub %x\n",start+stubs[n].a*4);
4062 literal_pool(256);
4063 set_jump_target(stubs[n].addr, out);
4064
4065 int i=stubs[n].a;
4066 struct regstat *i_regs=(struct regstat *)stubs[n].c;
4067 int addr=stubs[n].b;
4068 u_int reglist=stubs[n].e;
4069 signed char *i_regmap=i_regs->regmap;
4070 int temp2=get_reg(i_regmap,FTEMP);
4071 int rt;
cf95b4f0 4072 rt=get_reg(i_regmap,dops[i].rs2);
3968e69e 4073 assert(rt>=0);
4074 assert(addr>=0);
cf95b4f0 4075 assert(dops[i].opcode==0x2a||dops[i].opcode==0x2e); // SWL/SWR only implemented
3968e69e 4076 reglist|=(1<<addr);
4077 reglist&=~(1<<temp2);
4078
3968e69e 4079 // don't bother with it and call write handler
4080 save_regs(reglist);
4081 pass_args(addr,rt);
4082 int cc=get_reg(i_regmap,CCREG);
4083 if(cc<0)
4084 emit_loadreg(CCREG,2);
2330734f 4085 emit_addimm(cc<0?2:cc,(int)stubs[n].d+1,2);
de6dbc52 4086 emit_movimm(start + i*4,3);
4087 emit_writeword(3,&psxRegs.pc);
cf95b4f0 4088 emit_far_call((dops[i].opcode==0x2a?jump_handle_swl:jump_handle_swr));
2330734f 4089 emit_addimm(0,-((int)stubs[n].d+1),cc<0?2:cc);
3968e69e 4090 if(cc<0)
4091 emit_storereg(CCREG,2);
4092 restore_regs(reglist);
4093 emit_jmp(stubs[n].retaddr); // return address
3968e69e 4094}
4095
a5cd72d0 4096static void do_overflowstub(int n)
4097{
4098 assem_debug("do_overflowstub %x\n", start + (u_int)stubs[n].a * 4);
4099 literal_pool(24);
4100 int i = stubs[n].a;
4101 struct regstat *i_regs = (struct regstat *)stubs[n].c;
4102 int ccadj = stubs[n].d;
4103 set_jump_target(stubs[n].addr, out);
4104 wb_dirtys(regs[i].regmap, regs[i].dirty);
4105 exception_assemble(i, i_regs, ccadj);
4106}
4107
277718fa 4108static void do_alignmentstub(int n)
4109{
4110 assem_debug("do_alignmentstub %x\n", start + (u_int)stubs[n].a * 4);
4111 literal_pool(24);
4112 int i = stubs[n].a;
4113 struct regstat *i_regs = (struct regstat *)stubs[n].c;
4114 int ccadj = stubs[n].d;
4115 int is_store = dops[i].itype == STORE || dops[i].opcode == 0x3A; // SWC2
4116 int cause = (dops[i].opcode & 3) << 28;
4117 cause |= is_store ? (R3000E_AdES << 2) : (R3000E_AdEL << 2);
4118 set_jump_target(stubs[n].addr, out);
4119 wb_dirtys(regs[i].regmap, regs[i].dirty);
4120 if (stubs[n].b != 1)
4121 emit_mov(stubs[n].b, 1); // faulting address
4122 emit_movimm(cause, 0);
4123 exception_assemble(i, i_regs, ccadj);
4124}
4125
57871462 4126#ifndef multdiv_assemble
4127void multdiv_assemble(int i,struct regstat *i_regs)
4128{
4129 printf("Need multdiv_assemble for this architecture.\n");
7c3a5182 4130 abort();
57871462 4131}
4132#endif
4133
2330734f 4134static void mov_assemble(int i, const struct regstat *i_regs)
57871462 4135{
cf95b4f0 4136 //if(dops[i].opcode2==0x10||dops[i].opcode2==0x12) { // MFHI/MFLO
4137 //if(dops[i].opcode2==0x11||dops[i].opcode2==0x13) { // MTHI/MTLO
4138 if(dops[i].rt1) {
7c3a5182 4139 signed char sl,tl;
a5cd72d0 4140 tl=get_reg_w(i_regs->regmap, dops[i].rt1);
57871462 4141 //assert(tl>=0);
4142 if(tl>=0) {
cf95b4f0 4143 sl=get_reg(i_regs->regmap,dops[i].rs1);
57871462 4144 if(sl>=0) emit_mov(sl,tl);
cf95b4f0 4145 else emit_loadreg(dops[i].rs1,tl);
57871462 4146 }
4147 }
cf95b4f0 4148 if (dops[i].rs1 == HIREG || dops[i].rs1 == LOREG) // MFHI/MFLO
32631e6a 4149 multdiv_do_stall(i, i_regs);
57871462 4150}
4151
3968e69e 4152// call interpreter, exception handler, things that change pc/regs/cycles ...
2330734f 4153static void call_c_cpu_handler(int i, const struct regstat *i_regs, int ccadj_, u_int pc, void *func)
57871462 4154{
4155 signed char ccreg=get_reg(i_regs->regmap,CCREG);
4156 assert(ccreg==HOST_CCREG);
4157 assert(!is_delayslot);
581335b0 4158 (void)ccreg;
3968e69e 4159
4160 emit_movimm(pc,3); // Get PC
4161 emit_readword(&last_count,2);
4162 emit_writeword(3,&psxRegs.pc);
2330734f 4163 emit_addimm(HOST_CCREG,ccadj_,HOST_CCREG);
3968e69e 4164 emit_add(2,HOST_CCREG,2);
4165 emit_writeword(2,&psxRegs.cycle);
bc7c5acb 4166 emit_addimm_ptr(FP,(u_char *)&psxRegs - (u_char *)&dynarec_local,0);
2a014d73 4167 emit_far_call(func);
4168 emit_far_jump(jump_to_new_pc);
3968e69e 4169}
4170
a5cd72d0 4171static void exception_assemble(int i, const struct regstat *i_regs, int ccadj_)
3968e69e 4172{
d1150cd6 4173 // 'break' tends to be littered around to catch things like
4174 // division by 0 and is almost never executed, so don't emit much code here
a5cd72d0 4175 void *func;
4176 if (dops[i].itype == ALU || dops[i].itype == IMM16)
4177 func = is_delayslot ? jump_overflow_ds : jump_overflow;
277718fa 4178 else if (dops[i].itype == LOAD || dops[i].itype == STORE)
4179 func = is_delayslot ? jump_addrerror_ds : jump_addrerror;
a5cd72d0 4180 else if (dops[i].opcode2 == 0x0C)
4181 func = is_delayslot ? jump_syscall_ds : jump_syscall;
4182 else
4183 func = is_delayslot ? jump_break_ds : jump_break;
277718fa 4184 if (get_reg(i_regs->regmap, CCREG) != HOST_CCREG) // evicted
4185 emit_loadreg(CCREG, HOST_CCREG);
d1150cd6 4186 emit_movimm(start + i*4, 2); // pc
4187 emit_addimm(HOST_CCREG, ccadj_ + CLOCK_ADJUST(1), HOST_CCREG);
4188 emit_far_jump(func);
7139f3c8 4189}
4190
bc7c5acb 4191static void hlecall_bad()
4192{
a5cd72d0 4193 assert(0);
bc7c5acb 4194}
4195
2330734f 4196static void hlecall_assemble(int i, const struct regstat *i_regs, int ccadj_)
7139f3c8 4197{
bc7c5acb 4198 void *hlefunc = hlecall_bad;
dd79da89 4199 uint32_t hleCode = source[i] & 0x03ffffff;
3968e69e 4200 if (hleCode < ARRAY_SIZE(psxHLEt))
4201 hlefunc = psxHLEt[hleCode];
4202
2330734f 4203 call_c_cpu_handler(i, i_regs, ccadj_, start + i*4+4, hlefunc);
57871462 4204}
4205
2330734f 4206static void intcall_assemble(int i, const struct regstat *i_regs, int ccadj_)
1e973cb0 4207{
2330734f 4208 call_c_cpu_handler(i, i_regs, ccadj_, start + i*4, execI);
1e973cb0 4209}
4210
8062d65a 4211static void speculate_mov(int rs,int rt)
4212{
4213 if(rt!=0) {
4214 smrv_strong_next|=1<<rt;
4215 smrv[rt]=smrv[rs];
4216 }
4217}
4218
4219static void speculate_mov_weak(int rs,int rt)
4220{
4221 if(rt!=0) {
4222 smrv_weak_next|=1<<rt;
4223 smrv[rt]=smrv[rs];
4224 }
4225}
4226
4227static void speculate_register_values(int i)
4228{
4229 if(i==0) {
4230 memcpy(smrv,psxRegs.GPR.r,sizeof(smrv));
4231 // gp,sp are likely to stay the same throughout the block
4232 smrv_strong_next=(1<<28)|(1<<29)|(1<<30);
4233 smrv_weak_next=~smrv_strong_next;
4234 //printf(" llr %08x\n", smrv[4]);
4235 }
4236 smrv_strong=smrv_strong_next;
4237 smrv_weak=smrv_weak_next;
cf95b4f0 4238 switch(dops[i].itype) {
8062d65a 4239 case ALU:
cf95b4f0 4240 if ((smrv_strong>>dops[i].rs1)&1) speculate_mov(dops[i].rs1,dops[i].rt1);
4241 else if((smrv_strong>>dops[i].rs2)&1) speculate_mov(dops[i].rs2,dops[i].rt1);
4242 else if((smrv_weak>>dops[i].rs1)&1) speculate_mov_weak(dops[i].rs1,dops[i].rt1);
4243 else if((smrv_weak>>dops[i].rs2)&1) speculate_mov_weak(dops[i].rs2,dops[i].rt1);
8062d65a 4244 else {
cf95b4f0 4245 smrv_strong_next&=~(1<<dops[i].rt1);
4246 smrv_weak_next&=~(1<<dops[i].rt1);
8062d65a 4247 }
4248 break;
4249 case SHIFTIMM:
cf95b4f0 4250 smrv_strong_next&=~(1<<dops[i].rt1);
4251 smrv_weak_next&=~(1<<dops[i].rt1);
8062d65a 4252 // fallthrough
4253 case IMM16:
cf95b4f0 4254 if(dops[i].rt1&&is_const(&regs[i],dops[i].rt1)) {
de6dbc52 4255 int hr = get_reg_w(regs[i].regmap, dops[i].rt1);
4256 u_int value;
8062d65a 4257 if(hr>=0) {
4258 if(get_final_value(hr,i,&value))
cf95b4f0 4259 smrv[dops[i].rt1]=value;
4260 else smrv[dops[i].rt1]=constmap[i][hr];
4261 smrv_strong_next|=1<<dops[i].rt1;
8062d65a 4262 }
4263 }
4264 else {
cf95b4f0 4265 if ((smrv_strong>>dops[i].rs1)&1) speculate_mov(dops[i].rs1,dops[i].rt1);
4266 else if((smrv_weak>>dops[i].rs1)&1) speculate_mov_weak(dops[i].rs1,dops[i].rt1);
8062d65a 4267 }
4268 break;
4269 case LOAD:
cf95b4f0 4270 if(start<0x2000&&(dops[i].rt1==26||(smrv[dops[i].rt1]>>24)==0xa0)) {
8062d65a 4271 // special case for BIOS
cf95b4f0 4272 smrv[dops[i].rt1]=0xa0000000;
4273 smrv_strong_next|=1<<dops[i].rt1;
8062d65a 4274 break;
4275 }
4276 // fallthrough
4277 case SHIFT:
4278 case LOADLR:
4279 case MOV:
cf95b4f0 4280 smrv_strong_next&=~(1<<dops[i].rt1);
4281 smrv_weak_next&=~(1<<dops[i].rt1);
8062d65a 4282 break;
4283 case COP0:
4284 case COP2:
cf95b4f0 4285 if(dops[i].opcode2==0||dops[i].opcode2==2) { // MFC/CFC
4286 smrv_strong_next&=~(1<<dops[i].rt1);
4287 smrv_weak_next&=~(1<<dops[i].rt1);
8062d65a 4288 }
4289 break;
4290 case C2LS:
cf95b4f0 4291 if (dops[i].opcode==0x32) { // LWC2
4292 smrv_strong_next&=~(1<<dops[i].rt1);
4293 smrv_weak_next&=~(1<<dops[i].rt1);
8062d65a 4294 }
4295 break;
4296 }
4297#if 0
4298 int r=4;
4299 printf("x %08x %08x %d %d c %08x %08x\n",smrv[r],start+i*4,
4300 ((smrv_strong>>r)&1),(smrv_weak>>r)&1,regs[i].isconst,regs[i].wasconst);
4301#endif
4302}
4303
2330734f 4304static void ujump_assemble(int i, const struct regstat *i_regs);
4305static void rjump_assemble(int i, const struct regstat *i_regs);
4306static void cjump_assemble(int i, const struct regstat *i_regs);
4307static void sjump_assemble(int i, const struct regstat *i_regs);
2330734f 4308
4309static int assemble(int i, const struct regstat *i_regs, int ccadj_)
57871462 4310{
2330734f 4311 int ds = 0;
4312 switch (dops[i].itype) {
57871462 4313 case ALU:
a5cd72d0 4314 alu_assemble(i, i_regs, ccadj_);
2330734f 4315 break;
57871462 4316 case IMM16:
a5cd72d0 4317 imm16_assemble(i, i_regs, ccadj_);
2330734f 4318 break;
57871462 4319 case SHIFT:
2330734f 4320 shift_assemble(i, i_regs);
4321 break;
57871462 4322 case SHIFTIMM:
2330734f 4323 shiftimm_assemble(i, i_regs);
4324 break;
57871462 4325 case LOAD:
2330734f 4326 load_assemble(i, i_regs, ccadj_);
4327 break;
57871462 4328 case LOADLR:
2330734f 4329 loadlr_assemble(i, i_regs, ccadj_);
4330 break;
57871462 4331 case STORE:
2330734f 4332 store_assemble(i, i_regs, ccadj_);
4333 break;
57871462 4334 case STORELR:
2330734f 4335 storelr_assemble(i, i_regs, ccadj_);
4336 break;
57871462 4337 case COP0:
2330734f 4338 cop0_assemble(i, i_regs, ccadj_);
4339 break;
a5cd72d0 4340 case RFE:
277718fa 4341 rfe_assemble(i, i_regs);
2330734f 4342 break;
b9b61529 4343 case COP2:
2330734f 4344 cop2_assemble(i, i_regs);
4345 break;
b9b61529 4346 case C2LS:
2330734f 4347 c2ls_assemble(i, i_regs, ccadj_);
4348 break;
b9b61529 4349 case C2OP:
2330734f 4350 c2op_assemble(i, i_regs);
4351 break;
57871462 4352 case MULTDIV:
2330734f 4353 multdiv_assemble(i, i_regs);
4354 multdiv_prepare_stall(i, i_regs, ccadj_);
32631e6a 4355 break;
57871462 4356 case MOV:
2330734f 4357 mov_assemble(i, i_regs);
4358 break;
4359 case SYSCALL:
a5cd72d0 4360 exception_assemble(i, i_regs, ccadj_);
2330734f 4361 break;
4362 case HLECALL:
4363 hlecall_assemble(i, i_regs, ccadj_);
4364 break;
4365 case INTCALL:
4366 intcall_assemble(i, i_regs, ccadj_);
4367 break;
4368 case UJUMP:
4369 ujump_assemble(i, i_regs);
4370 ds = 1;
4371 break;
4372 case RJUMP:
4373 rjump_assemble(i, i_regs);
4374 ds = 1;
4375 break;
4376 case CJUMP:
4377 cjump_assemble(i, i_regs);
4378 ds = 1;
4379 break;
4380 case SJUMP:
4381 sjump_assemble(i, i_regs);
4382 ds = 1;
4383 break;
24058131 4384 case NOP:
2330734f 4385 case OTHER:
2330734f 4386 // not handled, just skip
4387 break;
4388 default:
4389 assert(0);
4390 }
4391 return ds;
4392}
4393
4394static void ds_assemble(int i, const struct regstat *i_regs)
4395{
4396 speculate_register_values(i);
4397 is_delayslot = 1;
4398 switch (dops[i].itype) {
57871462 4399 case SYSCALL:
7139f3c8 4400 case HLECALL:
1e973cb0 4401 case INTCALL:
57871462 4402 case UJUMP:
4403 case RJUMP:
4404 case CJUMP:
4405 case SJUMP:
c43b5311 4406 SysPrintf("Jump in the delay slot. This is probably a bug.\n");
2330734f 4407 break;
4408 default:
277718fa 4409 assemble(i, i_regs, cinfo[i].ccadj);
57871462 4410 }
2330734f 4411 is_delayslot = 0;
57871462 4412}
4413
4414// Is the branch target a valid internal jump?
ad49de89 4415static int internal_branch(int addr)
57871462 4416{
4417 if(addr&1) return 0; // Indirect (register) jump
4418 if(addr>=start && addr<start+slen*4-4)
4419 {
71e490c5 4420 return 1;
57871462 4421 }
4422 return 0;
4423}
4424
ad49de89 4425static void wb_invalidate(signed char pre[],signed char entry[],uint64_t dirty,uint64_t u)
57871462 4426{
4427 int hr;
4428 for(hr=0;hr<HOST_REGS;hr++) {
4429 if(hr!=EXCLUDE_REG) {
4430 if(pre[hr]!=entry[hr]) {
4431 if(pre[hr]>=0) {
4432 if((dirty>>hr)&1) {
4433 if(get_reg(entry,pre[hr])<0) {
00fa9369 4434 assert(pre[hr]<64);
4435 if(!((u>>pre[hr])&1))
4436 emit_storereg(pre[hr],hr);
57871462 4437 }
4438 }
4439 }
4440 }
4441 }
4442 }
4443 // Move from one register to another (no writeback)
4444 for(hr=0;hr<HOST_REGS;hr++) {
4445 if(hr!=EXCLUDE_REG) {
4446 if(pre[hr]!=entry[hr]) {
9de8a0c3 4447 if(pre[hr]>=0&&pre[hr]<TEMPREG) {
57871462 4448 int nr;
4449 if((nr=get_reg(entry,pre[hr]))>=0) {
4450 emit_mov(hr,nr);
4451 }
4452 }
4453 }
4454 }
4455 }
4456}
57871462 4457
4458// Load the specified registers
4459// This only loads the registers given as arguments because
4460// we don't want to load things that will be overwritten
53358c1d 4461static inline void load_reg(signed char entry[], signed char regmap[], int rs)
57871462 4462{
53358c1d 4463 int hr = get_reg(regmap, rs);
4464 if (hr >= 0 && entry[hr] != regmap[hr])
4465 emit_loadreg(regmap[hr], hr);
4466}
4467
4468static void load_regs(signed char entry[], signed char regmap[], int rs1, int rs2)
4469{
4470 load_reg(entry, regmap, rs1);
4471 if (rs1 != rs2)
4472 load_reg(entry, regmap, rs2);
57871462 4473}
4474
4475// Load registers prior to the start of a loop
4476// so that they are not loaded within the loop
4477static void loop_preload(signed char pre[],signed char entry[])
4478{
4479 int hr;
53358c1d 4480 for (hr = 0; hr < HOST_REGS; hr++) {
4481 int r = entry[hr];
4482 if (r >= 0 && pre[hr] != r && get_reg(pre, r) < 0) {
4483 assem_debug("loop preload:\n");
4484 if (r < TEMPREG)
4485 emit_loadreg(r, hr);
57871462 4486 }
4487 }
4488}
4489
4490// Generate address for load/store instruction
277718fa 4491// goes to AGEN (or temp) for writes, FTEMP for LOADLR and cop1/2 loads
4492// AGEN is assigned by pass5b_preallocate2
4149788d 4493static void address_generation(int i, const struct regstat *i_regs, signed char entry[])
57871462 4494{
37387d8b 4495 if (dops[i].is_load || dops[i].is_store) {
277718fa 4496 int ra = -1;
4497 int agr = AGEN1 + (i&1);
cf95b4f0 4498 if(dops[i].itype==LOAD) {
277718fa 4499 if (!dops[i].may_except)
4500 ra = get_reg_w(i_regs->regmap, dops[i].rt1); // reuse dest for agen
4501 if (ra < 0)
4502 ra = get_reg_temp(i_regs->regmap);
57871462 4503 }
cf95b4f0 4504 if(dops[i].itype==LOADLR) {
57871462 4505 ra=get_reg(i_regs->regmap,FTEMP);
4506 }
cf95b4f0 4507 if(dops[i].itype==STORE||dops[i].itype==STORELR) {
57871462 4508 ra=get_reg(i_regs->regmap,agr);
9de8a0c3 4509 if(ra<0) ra=get_reg_temp(i_regs->regmap);
57871462 4510 }
37387d8b 4511 if(dops[i].itype==C2LS) {
277718fa 4512 if (dops[i].opcode == 0x32) // LWC2
57871462 4513 ra=get_reg(i_regs->regmap,FTEMP);
277718fa 4514 else { // SWC2
57871462 4515 ra=get_reg(i_regs->regmap,agr);
9de8a0c3 4516 if(ra<0) ra=get_reg_temp(i_regs->regmap);
57871462 4517 }
4518 }
277718fa 4519 int rs = get_reg(i_regs->regmap, dops[i].rs1);
4520 //if(ra>=0)
4521 {
4522 int offset = cinfo[i].imm;
4523 int add_offset = offset != 0;
33a1eda1 4524 int c = rs >= 0 && ((i_regs->wasconst >> rs) & 1);
cf95b4f0 4525 if(dops[i].rs1==0) {
57871462 4526 // Using r0 as a base address
277718fa 4527 assert(ra >= 0);
57871462 4528 if(!entry||entry[ra]!=agr) {
cf95b4f0 4529 if (dops[i].opcode==0x22||dops[i].opcode==0x26) {
57871462 4530 emit_movimm(offset&0xFFFFFFFC,ra); // LWL/LWR
57871462 4531 }else{
4532 emit_movimm(offset,ra);
4533 }
4534 } // else did it in the previous cycle
277718fa 4535 cinfo[i].addr = ra;
4536 add_offset = 0;
4537 }
4538 else if (rs < 0) {
4539 assert(ra >= 0);
4540 if (!entry || entry[ra] != dops[i].rs1)
4541 emit_loadreg(dops[i].rs1, ra);
4542 cinfo[i].addr = ra;
cf95b4f0 4543 //if(!entry||entry[ra]!=dops[i].rs1)
57871462 4544 // printf("poor load scheduling!\n");
4545 }
4546 else if(c) {
cf95b4f0 4547 if(dops[i].rs1!=dops[i].rt1||dops[i].itype!=LOAD) {
277718fa 4548 assert(ra >= 0);
57871462 4549 if(!entry||entry[ra]!=agr) {
cf95b4f0 4550 if (dops[i].opcode==0x22||dops[i].opcode==0x26) {
57871462 4551 emit_movimm((constmap[i][rs]+offset)&0xFFFFFFFC,ra); // LWL/LWR
57871462 4552 }else{
57871462 4553 emit_movimm(constmap[i][rs]+offset,ra);
8575a877 4554 regs[i].loadedconst|=1<<ra;
57871462 4555 }
4556 } // else did it in the previous cycle
277718fa 4557 cinfo[i].addr = ra;
4558 }
4559 else // else load_consts already did it
4560 cinfo[i].addr = rs;
4561 add_offset = 0;
57871462 4562 }
277718fa 4563 else
4564 cinfo[i].addr = rs;
4565 if (add_offset) {
4566 assert(ra >= 0);
57871462 4567 if(rs>=0) {
4568 emit_addimm(rs,offset,ra);
4569 }else{
4570 emit_addimm(ra,offset,ra);
4571 }
277718fa 4572 cinfo[i].addr = ra;
57871462 4573 }
4574 }
277718fa 4575 assert(cinfo[i].addr >= 0);
57871462 4576 }
4577 // Preload constants for next instruction
37387d8b 4578 if (dops[i+1].is_load || dops[i+1].is_store) {
57871462 4579 int agr,ra;
57871462 4580 // Actual address
4581 agr=AGEN1+((i+1)&1);
4582 ra=get_reg(i_regs->regmap,agr);
4583 if(ra>=0) {
cf95b4f0 4584 int rs=get_reg(regs[i+1].regmap,dops[i+1].rs1);
277718fa 4585 int offset=cinfo[i+1].imm;
57871462 4586 int c=(regs[i+1].wasconst>>rs)&1;
cf95b4f0 4587 if(c&&(dops[i+1].rs1!=dops[i+1].rt1||dops[i+1].itype!=LOAD)) {
4588 if (dops[i+1].opcode==0x22||dops[i+1].opcode==0x26) {
57871462 4589 emit_movimm((constmap[i+1][rs]+offset)&0xFFFFFFFC,ra); // LWL/LWR
cf95b4f0 4590 }else if (dops[i+1].opcode==0x1a||dops[i+1].opcode==0x1b) {
57871462 4591 emit_movimm((constmap[i+1][rs]+offset)&0xFFFFFFF8,ra); // LDL/LDR
4592 }else{
57871462 4593 emit_movimm(constmap[i+1][rs]+offset,ra);
8575a877 4594 regs[i+1].loadedconst|=1<<ra;
57871462 4595 }
4596 }
cf95b4f0 4597 else if(dops[i+1].rs1==0) {
57871462 4598 // Using r0 as a base address
cf95b4f0 4599 if (dops[i+1].opcode==0x22||dops[i+1].opcode==0x26) {
57871462 4600 emit_movimm(offset&0xFFFFFFFC,ra); // LWL/LWR
cf95b4f0 4601 }else if (dops[i+1].opcode==0x1a||dops[i+1].opcode==0x1b) {
57871462 4602 emit_movimm(offset&0xFFFFFFF8,ra); // LDL/LDR
4603 }else{
4604 emit_movimm(offset,ra);
4605 }
4606 }
4607 }
4608 }
4609}
4610
de6dbc52 4611static int get_final_value(int hr, int i, u_int *value)
57871462 4612{
4613 int reg=regs[i].regmap[hr];
4614 while(i<slen-1) {
4615 if(regs[i+1].regmap[hr]!=reg) break;
4616 if(!((regs[i+1].isconst>>hr)&1)) break;
cf95b4f0 4617 if(dops[i+1].bt) break;
57871462 4618 i++;
4619 }
4620 if(i<slen-1) {
fe807a8a 4621 if (dops[i].is_jump) {
57871462 4622 *value=constmap[i][hr];
4623 return 1;
4624 }
cf95b4f0 4625 if(!dops[i+1].bt) {
fe807a8a 4626 if (dops[i+1].is_jump) {
57871462 4627 // Load in delay slot, out-of-order execution
cf95b4f0 4628 if(dops[i+2].itype==LOAD&&dops[i+2].rs1==reg&&dops[i+2].rt1==reg&&((regs[i+1].wasconst>>hr)&1))
57871462 4629 {
57871462 4630 // Precompute load address
277718fa 4631 *value=constmap[i][hr]+cinfo[i+2].imm;
57871462 4632 return 1;
4633 }
4634 }
cf95b4f0 4635 if(dops[i+1].itype==LOAD&&dops[i+1].rs1==reg&&dops[i+1].rt1==reg)
57871462 4636 {
57871462 4637 // Precompute load address
277718fa 4638 *value=constmap[i][hr]+cinfo[i+1].imm;
4639 //printf("c=%x imm=%lx\n",(long)constmap[i][hr],cinfo[i+1].imm);
57871462 4640 return 1;
4641 }
4642 }
4643 }
4644 *value=constmap[i][hr];
643aeae3 4645 //printf("c=%lx\n",(long)constmap[i][hr]);
57871462 4646 if(i==slen-1) return 1;
00fa9369 4647 assert(reg < 64);
4648 return !((unneeded_reg[i+1]>>reg)&1);
57871462 4649}
4650
4651// Load registers with known constants
ad49de89 4652static void load_consts(signed char pre[],signed char regmap[],int i)
57871462 4653{
8575a877 4654 int hr,hr2;
4655 // propagate loaded constant flags
cf95b4f0 4656 if(i==0||dops[i].bt)
8575a877 4657 regs[i].loadedconst=0;
4658 else {
684b6816 4659 for (hr = 0; hr < HOST_REGS; hr++) {
4660 if (hr == EXCLUDE_REG || regmap[hr] < 0 || pre[hr] != regmap[hr])
4661 continue;
4662 if ((((regs[i-1].isconst & regs[i-1].loadedconst) >> hr) & 1)
4663 && regmap[hr] == regs[i-1].regmap[hr])
8575a877 4664 {
684b6816 4665 regs[i].loadedconst |= 1u << hr;
8575a877 4666 }
4667 }
4668 }
57871462 4669 // Load 32-bit regs
4670 for(hr=0;hr<HOST_REGS;hr++) {
4671 if(hr!=EXCLUDE_REG&&regmap[hr]>=0) {
4672 //if(entry[hr]!=regmap[hr]) {
8575a877 4673 if(!((regs[i].loadedconst>>hr)&1)) {
ad49de89 4674 assert(regmap[hr]<64);
4675 if(((regs[i].isconst>>hr)&1)&&regmap[hr]>0) {
de6dbc52 4676 u_int value, similar=0;
57871462 4677 if(get_final_value(hr,i,&value)) {
8575a877 4678 // see if some other register has similar value
4679 for(hr2=0;hr2<HOST_REGS;hr2++) {
4680 if(hr2!=EXCLUDE_REG&&((regs[i].loadedconst>>hr2)&1)) {
4681 if(is_similar_value(value,constmap[i][hr2])) {
4682 similar=1;
4683 break;
4684 }
4685 }
4686 }
4687 if(similar) {
de6dbc52 4688 u_int value2;
8575a877 4689 if(get_final_value(hr2,i,&value2)) // is this needed?
4690 emit_movimm_from(value2,hr2,value,hr);
4691 else
4692 emit_movimm(value,hr);
4693 }
4694 else if(value==0) {
57871462 4695 emit_zeroreg(hr);
4696 }
4697 else {
4698 emit_movimm(value,hr);
4699 }
4700 }
8575a877 4701 regs[i].loadedconst|=1<<hr;
57871462 4702 }
4703 }
4704 }
4705 }
57871462 4706}
ad49de89 4707
2330734f 4708static void load_all_consts(const signed char regmap[], u_int dirty, int i)
57871462 4709{
4710 int hr;
4711 // Load 32-bit regs
4712 for(hr=0;hr<HOST_REGS;hr++) {
4713 if(hr!=EXCLUDE_REG&&regmap[hr]>=0&&((dirty>>hr)&1)) {
ad49de89 4714 assert(regmap[hr] < 64);
4715 if(((regs[i].isconst>>hr)&1)&&regmap[hr]>0) {
57871462 4716 int value=constmap[i][hr];
4717 if(value==0) {
4718 emit_zeroreg(hr);
4719 }
4720 else {
4721 emit_movimm(value,hr);
4722 }
4723 }
4724 }
4725 }
57871462 4726}
4727
4728// Write out all dirty registers (except cycle count)
a22ccd6a 4729#ifndef wb_dirtys
4730static void wb_dirtys(const signed char i_regmap[], u_int i_dirty)
57871462 4731{
4732 int hr;
4733 for(hr=0;hr<HOST_REGS;hr++) {
4734 if(hr!=EXCLUDE_REG) {
4735 if(i_regmap[hr]>0) {
4736 if(i_regmap[hr]!=CCREG) {
4737 if((i_dirty>>hr)&1) {
00fa9369 4738 assert(i_regmap[hr]<64);
4739 emit_storereg(i_regmap[hr],hr);
57871462 4740 }
4741 }
4742 }
4743 }
4744 }
4745}
a22ccd6a 4746#endif
ad49de89 4747
57871462 4748// Write out dirty registers that we need to reload (pair with load_needed_regs)
4749// This writes the registers not written by store_regs_bt
a22ccd6a 4750static void wb_needed_dirtys(const signed char i_regmap[], u_int i_dirty, int addr)
57871462 4751{
4752 int hr;
4753 int t=(addr-start)>>2;
4754 for(hr=0;hr<HOST_REGS;hr++) {
4755 if(hr!=EXCLUDE_REG) {
4756 if(i_regmap[hr]>0) {
4757 if(i_regmap[hr]!=CCREG) {
ad49de89 4758 if(i_regmap[hr]==regs[t].regmap_entry[hr] && ((regs[t].dirty>>hr)&1)) {
57871462 4759 if((i_dirty>>hr)&1) {
00fa9369 4760 assert(i_regmap[hr]<64);
4761 emit_storereg(i_regmap[hr],hr);
57871462 4762 }
4763 }
4764 }
4765 }
4766 }
4767 }
4768}
4769
4770// Load all registers (except cycle count)
a22ccd6a 4771#ifndef load_all_regs
2330734f 4772static void load_all_regs(const signed char i_regmap[])
57871462 4773{
4774 int hr;
4775 for(hr=0;hr<HOST_REGS;hr++) {
4776 if(hr!=EXCLUDE_REG) {
4777 if(i_regmap[hr]==0) {
4778 emit_zeroreg(hr);
4779 }
4780 else
9de8a0c3 4781 if(i_regmap[hr]>0 && i_regmap[hr]<TEMPREG && i_regmap[hr]!=CCREG)
57871462 4782 {
4783 emit_loadreg(i_regmap[hr],hr);
4784 }
4785 }
4786 }
4787}
a22ccd6a 4788#endif
57871462 4789
4790// Load all current registers also needed by next instruction
2330734f 4791static void load_needed_regs(const signed char i_regmap[], const signed char next_regmap[])
57871462 4792{
a22ccd6a 4793 signed char regmap_sel[HOST_REGS];
57871462 4794 int hr;
a22ccd6a 4795 for (hr = 0; hr < HOST_REGS; hr++) {
4796 regmap_sel[hr] = -1;
4797 if (hr != EXCLUDE_REG)
4798 if (next_regmap[hr] == i_regmap[hr] || get_reg(next_regmap, i_regmap[hr]) >= 0)
4799 regmap_sel[hr] = i_regmap[hr];
57871462 4800 }
a22ccd6a 4801 load_all_regs(regmap_sel);
57871462 4802}
4803
4804// Load all regs, storing cycle count if necessary
2330734f 4805static void load_regs_entry(int t)
57871462 4806{
cf95b4f0 4807 if(dops[t].is_ds) emit_addimm(HOST_CCREG,CLOCK_ADJUST(1),HOST_CCREG);
277718fa 4808 else if(cinfo[t].ccadj) emit_addimm(HOST_CCREG,-cinfo[t].ccadj,HOST_CCREG);
57871462 4809 if(regs[t].regmap_entry[HOST_CCREG]!=CCREG) {
4810 emit_storereg(CCREG,HOST_CCREG);
4811 }
a22ccd6a 4812 load_all_regs(regs[t].regmap_entry);
57871462 4813}
4814
4815// Store dirty registers prior to branch
4149788d 4816static void store_regs_bt(signed char i_regmap[],uint64_t i_dirty,int addr)
57871462 4817{
ad49de89 4818 if(internal_branch(addr))
57871462 4819 {
4820 int t=(addr-start)>>2;
4821 int hr;
4822 for(hr=0;hr<HOST_REGS;hr++) {
4823 if(hr!=EXCLUDE_REG) {
4824 if(i_regmap[hr]>0 && i_regmap[hr]!=CCREG) {
ad49de89 4825 if(i_regmap[hr]!=regs[t].regmap_entry[hr] || !((regs[t].dirty>>hr)&1)) {
57871462 4826 if((i_dirty>>hr)&1) {
00fa9369 4827 assert(i_regmap[hr]<64);
4828 if(!((unneeded_reg[t]>>i_regmap[hr])&1))
4829 emit_storereg(i_regmap[hr],hr);
57871462 4830 }
4831 }
4832 }
4833 }
4834 }
4835 }
4836 else
4837 {
4838 // Branch out of this block, write out all dirty regs
ad49de89 4839 wb_dirtys(i_regmap,i_dirty);
57871462 4840 }
4841}
4842
4843// Load all needed registers for branch target
ad49de89 4844static void load_regs_bt(signed char i_regmap[],uint64_t i_dirty,int addr)
57871462 4845{
4846 //if(addr>=start && addr<(start+slen*4))
ad49de89 4847 if(internal_branch(addr))
57871462 4848 {
4849 int t=(addr-start)>>2;
4850 int hr;
4851 // Store the cycle count before loading something else
4852 if(i_regmap[HOST_CCREG]!=CCREG) {
4853 assert(i_regmap[HOST_CCREG]==-1);
4854 }
4855 if(regs[t].regmap_entry[HOST_CCREG]!=CCREG) {
4856 emit_storereg(CCREG,HOST_CCREG);
4857 }
4858 // Load 32-bit regs
4859 for(hr=0;hr<HOST_REGS;hr++) {
ea3d2e6e 4860 if(hr!=EXCLUDE_REG&&regs[t].regmap_entry[hr]>=0&&regs[t].regmap_entry[hr]<TEMPREG) {
00fa9369 4861 if(i_regmap[hr]!=regs[t].regmap_entry[hr]) {
57871462 4862 if(regs[t].regmap_entry[hr]==0) {
4863 emit_zeroreg(hr);
4864 }
4865 else if(regs[t].regmap_entry[hr]!=CCREG)
4866 {
4867 emit_loadreg(regs[t].regmap_entry[hr],hr);
4868 }
4869 }
4870 }
4871 }
57871462 4872 }
4873}
4874
ad49de89 4875static int match_bt(signed char i_regmap[],uint64_t i_dirty,int addr)
57871462 4876{
4877 if(addr>=start && addr<start+slen*4-4)
4878 {
4879 int t=(addr-start)>>2;
4880 int hr;
4881 if(regs[t].regmap_entry[HOST_CCREG]!=CCREG) return 0;
4882 for(hr=0;hr<HOST_REGS;hr++)
4883 {
4884 if(hr!=EXCLUDE_REG)
4885 {
4886 if(i_regmap[hr]!=regs[t].regmap_entry[hr])
4887 {
ea3d2e6e 4888 if(regs[t].regmap_entry[hr]>=0&&(regs[t].regmap_entry[hr]|64)<TEMPREG+64)
57871462 4889 {
4890 return 0;
4891 }
9f51b4b9 4892 else
57871462 4893 if((i_dirty>>hr)&1)
4894 {
ea3d2e6e 4895 if(i_regmap[hr]<TEMPREG)
57871462 4896 {
4897 if(!((unneeded_reg[t]>>i_regmap[hr])&1))
4898 return 0;
4899 }
ea3d2e6e 4900 else if(i_regmap[hr]>=64&&i_regmap[hr]<TEMPREG+64)
57871462 4901 {
00fa9369 4902 assert(0);
57871462 4903 }
4904 }
4905 }
4906 else // Same register but is it 32-bit or dirty?
4907 if(i_regmap[hr]>=0)
4908 {
4909 if(!((regs[t].dirty>>hr)&1))
4910 {
4911 if((i_dirty>>hr)&1)
4912 {
4913 if(!((unneeded_reg[t]>>i_regmap[hr])&1))
4914 {
4915 //printf("%x: dirty no match\n",addr);
4916 return 0;
4917 }
4918 }
4919 }
57871462 4920 }
4921 }
4922 }
57871462 4923 // Delay slots are not valid branch targets
fe807a8a 4924 //if(t>0&&(dops[t-1].is_jump) return 0;
57871462 4925 // Delay slots require additional processing, so do not match
cf95b4f0 4926 if(dops[t].is_ds) return 0;
57871462 4927 }
4928 else
4929 {
4930 int hr;
4931 for(hr=0;hr<HOST_REGS;hr++)
4932 {
4933 if(hr!=EXCLUDE_REG)
4934 {
4935 if(i_regmap[hr]>=0)
4936 {
4937 if(hr!=HOST_CCREG||i_regmap[hr]!=CCREG)
4938 {
4939 if((i_dirty>>hr)&1)
4940 {
4941 return 0;
4942 }
4943 }
4944 }
4945 }
4946 }
4947 }
4948 return 1;
4949}
4950
dd114d7d 4951#ifdef DRC_DBG
2330734f 4952static void drc_dbg_emit_do_cmp(int i, int ccadj_)
dd114d7d 4953{
4954 extern void do_insn_cmp();
3968e69e 4955 //extern int cycle;
81dbbf4c 4956 u_int hr, reglist = get_host_reglist(regs[i].regmap);
33a1eda1 4957 reglist |= get_host_reglist(regs[i].regmap_entry);
4958 reglist &= DRC_DBG_REGMASK;
dd114d7d 4959
40fca85b 4960 assem_debug("//do_insn_cmp %08x\n", start+i*4);
dd114d7d 4961 save_regs(reglist);
40fca85b 4962 // write out changed consts to match the interpreter
cf95b4f0 4963 if (i > 0 && !dops[i].bt) {
40fca85b 4964 for (hr = 0; hr < HOST_REGS; hr++) {
2330734f 4965 int reg = regs[i].regmap_entry[hr]; // regs[i-1].regmap[hr];
277718fa 4966 if (hr == EXCLUDE_REG || reg <= 0)
40fca85b 4967 continue;
4968 if (!((regs[i-1].isconst >> hr) & 1))
4969 continue;
4970 if (i > 1 && reg == regs[i-2].regmap[hr] && constmap[i-1][hr] == constmap[i-2][hr])
4971 continue;
4972 emit_movimm(constmap[i-1][hr],0);
4973 emit_storereg(reg, 0);
4974 }
4975 }
4f13a577 4976 if (dops[i].opcode == 0x0f) { // LUI
4977 emit_movimm(cinfo[i].imm << 16, 0);
4978 emit_storereg(dops[i].rt1, 0);
4979 }
dd114d7d 4980 emit_movimm(start+i*4,0);
643aeae3 4981 emit_writeword(0,&pcaddr);
2330734f 4982 int cc = get_reg(regs[i].regmap_entry, CCREG);
4983 if (cc < 0)
4984 emit_loadreg(CCREG, cc = 0);
4985 emit_addimm(cc, ccadj_, 0);
4986 emit_writeword(0, &psxRegs.cycle);
2a014d73 4987 emit_far_call(do_insn_cmp);
643aeae3 4988 //emit_readword(&cycle,0);
dd114d7d 4989 //emit_addimm(0,2,0);
643aeae3 4990 //emit_writeword(0,&cycle);
3968e69e 4991 (void)get_reg2;
dd114d7d 4992 restore_regs(reglist);
40fca85b 4993 assem_debug("\\\\do_insn_cmp\n");
dd114d7d 4994}
4f13a577 4995static void drc_dbg_emit_wb_dirtys(int i, const struct regstat *i_regs)
4996{
4997 // write-out non-consts, consts are likely different because of get_final_value()
4998 if (i_regs->dirty & ~i_regs->loadedconst) {
4999 assem_debug("/ drc_dbg_wb\n");
5000 wb_dirtys(i_regs->regmap, i_regs->dirty & ~i_regs->loadedconst);
5001 assem_debug("\\ drc_dbg_wb\n");
5002 }
5003}
dd114d7d 5004#else
2330734f 5005#define drc_dbg_emit_do_cmp(x,y)
4f13a577 5006#define drc_dbg_emit_wb_dirtys(x,y)
dd114d7d 5007#endif
5008
57871462 5009// Used when a branch jumps into the delay slot of another branch
7c3a5182 5010static void ds_assemble_entry(int i)
57871462 5011{
277718fa 5012 int t = (cinfo[i].ba - start) >> 2;
2330734f 5013 int ccadj_ = -CLOCK_ADJUST(1);
df4dc2b1 5014 if (!instr_addr[t])
5015 instr_addr[t] = out;
277718fa 5016 assem_debug("Assemble delay slot at %x\n",cinfo[i].ba);
57871462 5017 assem_debug("<->\n");
2330734f 5018 drc_dbg_emit_do_cmp(t, ccadj_);
57871462 5019 if(regs[t].regmap_entry[HOST_CCREG]==CCREG&&regs[t].regmap[HOST_CCREG]!=CCREG)
ad49de89 5020 wb_register(CCREG,regs[t].regmap_entry,regs[t].wasdirty);
cf95b4f0 5021 load_regs(regs[t].regmap_entry,regs[t].regmap,dops[t].rs1,dops[t].rs2);
57871462 5022 address_generation(t,&regs[t],regs[t].regmap_entry);
37387d8b 5023 if (ram_offset && (dops[t].is_load || dops[t].is_store))
53358c1d 5024 load_reg(regs[t].regmap_entry,regs[t].regmap,ROREG);
37387d8b 5025 if (dops[t].is_store)
53358c1d 5026 load_reg(regs[t].regmap_entry,regs[t].regmap,INVCP);
57871462 5027 is_delayslot=0;
2330734f 5028 switch (dops[t].itype) {
57871462 5029 case SYSCALL:
7139f3c8 5030 case HLECALL:
1e973cb0 5031 case INTCALL:
57871462 5032 case UJUMP:
5033 case RJUMP:
5034 case CJUMP:
5035 case SJUMP:
c43b5311 5036 SysPrintf("Jump in the delay slot. This is probably a bug.\n");
2330734f 5037 break;
5038 default:
5039 assemble(t, &regs[t], ccadj_);
57871462 5040 }
277718fa 5041 store_regs_bt(regs[t].regmap,regs[t].dirty,cinfo[i].ba+4);
5042 load_regs_bt(regs[t].regmap,regs[t].dirty,cinfo[i].ba+4);
5043 if(internal_branch(cinfo[i].ba+4))
57871462 5044 assem_debug("branch: internal\n");
5045 else
5046 assem_debug("branch: external\n");
277718fa 5047 assert(internal_branch(cinfo[i].ba+4));
5048 add_to_linker(out,cinfo[i].ba+4,internal_branch(cinfo[i].ba+4));
57871462 5049 emit_jmp(0);
5050}
5051
d1e4ebd9 5052// Load 2 immediates optimizing for small code size
5053static void emit_mov2imm_compact(int imm1,u_int rt1,int imm2,u_int rt2)
5054{
5055 emit_movimm(imm1,rt1);
5056 emit_movimm_from(imm1,rt1,imm2,rt2);
5057}
5058
2330734f 5059static void do_cc(int i, const signed char i_regmap[], int *adj,
5060 int addr, int taken, int invert)
57871462 5061{
2330734f 5062 int count, count_plus2;
b14b6a8f 5063 void *jaddr;
5064 void *idle=NULL;
b6e87b2b 5065 int t=0;
cf95b4f0 5066 if(dops[i].itype==RJUMP)
57871462 5067 {
5068 *adj=0;
5069 }
277718fa 5070 //if(cinfo[i].ba>=start && cinfo[i].ba<(start+slen*4))
5071 if(internal_branch(cinfo[i].ba))
57871462 5072 {
277718fa 5073 t=(cinfo[i].ba-start)>>2;
2330734f 5074 if(dops[t].is_ds) *adj=-CLOCK_ADJUST(1); // Branch into delay slot adds an extra cycle
277718fa 5075 else *adj=cinfo[t].ccadj;
57871462 5076 }
5077 else
5078 {
5079 *adj=0;
5080 }
277718fa 5081 count = cinfo[i].ccadj;
2330734f 5082 count_plus2 = count + CLOCK_ADJUST(2);
277718fa 5083 if(taken==TAKEN && i==(cinfo[i].ba-start)>>2 && source[i+1]==0) {
57871462 5084 // Idle loop
5085 if(count&1) emit_addimm_and_set_flags(2*(count+2),HOST_CCREG);
b14b6a8f 5086 idle=out;
57871462 5087 //emit_subfrommem(&idlecount,HOST_CCREG); // Count idle cycles
5088 emit_andimm(HOST_CCREG,3,HOST_CCREG);
b14b6a8f 5089 jaddr=out;
57871462 5090 emit_jmp(0);
5091 }
5092 else if(*adj==0||invert) {
2330734f 5093 int cycles = count_plus2;
b6e87b2b 5094 // faster loop HACK
bb4f300c 5095#if 0
b6e87b2b 5096 if (t&&*adj) {
5097 int rel=t-i;
5098 if(-NO_CYCLE_PENALTY_THR<rel&&rel<0)
2330734f 5099 cycles=*adj+count+2-*adj;
b6e87b2b 5100 }
bb4f300c 5101#endif
2330734f 5102 emit_addimm_and_set_flags(cycles, HOST_CCREG);
5103 jaddr = out;
57871462 5104 emit_jns(0);
5105 }
5106 else
5107 {
2330734f 5108 emit_cmpimm(HOST_CCREG, -count_plus2);
5109 jaddr = out;
57871462 5110 emit_jns(0);
5111 }
2330734f 5112 add_stub(CC_STUB,jaddr,idle?idle:out,(*adj==0||invert||idle)?0:count_plus2,i,addr,taken,0);
57871462 5113}
5114
b14b6a8f 5115static void do_ccstub(int n)
57871462 5116{
5117 literal_pool(256);
d1e4ebd9 5118 assem_debug("do_ccstub %x\n",start+(u_int)stubs[n].b*4);
b14b6a8f 5119 set_jump_target(stubs[n].addr, out);
5120 int i=stubs[n].b;
33a1eda1 5121 if (stubs[n].d != TAKEN) {
ad49de89 5122 wb_dirtys(branch_regs[i].regmap,branch_regs[i].dirty);
57871462 5123 }
5124 else {
277718fa 5125 if(internal_branch(cinfo[i].ba))
5126 wb_needed_dirtys(branch_regs[i].regmap,branch_regs[i].dirty,cinfo[i].ba);
57871462 5127 }
b14b6a8f 5128 if(stubs[n].c!=-1)
57871462 5129 {
5130 // Save PC as return address
6d75addf 5131 emit_movimm(stubs[n].c,0);
5132 emit_writeword(0,&pcaddr);
57871462 5133 }
5134 else
5135 {
5136 // Return address depends on which way the branch goes
cf95b4f0 5137 if(dops[i].itype==CJUMP||dops[i].itype==SJUMP)
57871462 5138 {
cf95b4f0 5139 int s1l=get_reg(branch_regs[i].regmap,dops[i].rs1);
5140 int s2l=get_reg(branch_regs[i].regmap,dops[i].rs2);
5141 if(dops[i].rs1==0)
57871462 5142 {
ad49de89 5143 s1l=s2l;
5144 s2l=-1;
57871462 5145 }
cf95b4f0 5146 else if(dops[i].rs2==0)
57871462 5147 {
ad49de89 5148 s2l=-1;
57871462 5149 }
5150 assert(s1l>=0);
5151 #ifdef DESTRUCTIVE_WRITEBACK
cf95b4f0 5152 if(dops[i].rs1) {
ad49de89 5153 if((branch_regs[i].dirty>>s1l)&&1)
cf95b4f0 5154 emit_loadreg(dops[i].rs1,s1l);
9f51b4b9 5155 }
57871462 5156 else {
ad49de89 5157 if((branch_regs[i].dirty>>s1l)&1)
cf95b4f0 5158 emit_loadreg(dops[i].rs2,s1l);
57871462 5159 }
5160 if(s2l>=0)
ad49de89 5161 if((branch_regs[i].dirty>>s2l)&1)
cf95b4f0 5162 emit_loadreg(dops[i].rs2,s2l);
57871462 5163 #endif
5164 int hr=0;
5194fb95 5165 int addr=-1,alt=-1,ntaddr=-1;
57871462 5166 while(hr<HOST_REGS)
5167 {
5168 if(hr!=EXCLUDE_REG && hr!=HOST_CCREG &&
9de8a0c3 5169 branch_regs[i].regmap[hr]!=dops[i].rs1 &&
5170 branch_regs[i].regmap[hr]!=dops[i].rs2 )
57871462 5171 {
5172 addr=hr++;break;
5173 }
5174 hr++;
5175 }
5176 while(hr<HOST_REGS)
5177 {
5178 if(hr!=EXCLUDE_REG && hr!=HOST_CCREG &&
9de8a0c3 5179 branch_regs[i].regmap[hr]!=dops[i].rs1 &&
5180 branch_regs[i].regmap[hr]!=dops[i].rs2 )
57871462 5181 {
5182 alt=hr++;break;
5183 }
5184 hr++;
5185 }
ecca05e3 5186 if ((dops[i].opcode & 0x3e) == 6) // BLEZ/BGTZ needs another register
57871462 5187 {
5188 while(hr<HOST_REGS)
5189 {
5190 if(hr!=EXCLUDE_REG && hr!=HOST_CCREG &&
9de8a0c3 5191 branch_regs[i].regmap[hr]!=dops[i].rs1 &&
5192 branch_regs[i].regmap[hr]!=dops[i].rs2 )
57871462 5193 {
5194 ntaddr=hr;break;
5195 }
5196 hr++;
5197 }
5198 assert(hr<HOST_REGS);
5199 }
ecca05e3 5200 if (dops[i].opcode == 4) // BEQ
57871462 5201 {
5202 #ifdef HAVE_CMOV_IMM
ad49de89 5203 if(s2l>=0) emit_cmp(s1l,s2l);
5204 else emit_test(s1l,s1l);
277718fa 5205 emit_cmov2imm_e_ne_compact(cinfo[i].ba,start+i*4+8,addr);
ad49de89 5206 #else
277718fa 5207 emit_mov2imm_compact(cinfo[i].ba,addr,start+i*4+8,alt);
ad49de89 5208 if(s2l>=0) emit_cmp(s1l,s2l);
5209 else emit_test(s1l,s1l);
5210 emit_cmovne_reg(alt,addr);
57871462 5211 #endif
57871462 5212 }
ecca05e3 5213 else if (dops[i].opcode == 5) // BNE
57871462 5214 {
5215 #ifdef HAVE_CMOV_IMM
ad49de89 5216 if(s2l>=0) emit_cmp(s1l,s2l);
5217 else emit_test(s1l,s1l);
277718fa 5218 emit_cmov2imm_e_ne_compact(start+i*4+8,cinfo[i].ba,addr);
ad49de89 5219 #else
277718fa 5220 emit_mov2imm_compact(start+i*4+8,addr,cinfo[i].ba,alt);
ad49de89 5221 if(s2l>=0) emit_cmp(s1l,s2l);
5222 else emit_test(s1l,s1l);
5223 emit_cmovne_reg(alt,addr);
57871462 5224 #endif
57871462 5225 }
ecca05e3 5226 else if (dops[i].opcode == 6) // BLEZ
57871462 5227 {
277718fa 5228 //emit_movimm(cinfo[i].ba,alt);
57871462 5229 //emit_movimm(start+i*4+8,addr);
277718fa 5230 emit_mov2imm_compact(cinfo[i].ba,alt,start+i*4+8,addr);
57871462 5231 emit_cmpimm(s1l,1);
57871462 5232 emit_cmovl_reg(alt,addr);
57871462 5233 }
ecca05e3 5234 else if (dops[i].opcode == 7) // BGTZ
57871462 5235 {
277718fa 5236 //emit_movimm(cinfo[i].ba,addr);
57871462 5237 //emit_movimm(start+i*4+8,ntaddr);
277718fa 5238 emit_mov2imm_compact(cinfo[i].ba,addr,start+i*4+8,ntaddr);
57871462 5239 emit_cmpimm(s1l,1);
57871462 5240 emit_cmovl_reg(ntaddr,addr);
57871462 5241 }
ecca05e3 5242 else if (dops[i].itype == SJUMP) // BLTZ/BGEZ
57871462 5243 {
277718fa 5244 //emit_movimm(cinfo[i].ba,alt);
57871462 5245 //emit_movimm(start+i*4+8,addr);
de6dbc52 5246 if (dops[i].rs1) {
5247 emit_mov2imm_compact(cinfo[i].ba,
5248 (dops[i].opcode2 & 1) ? addr : alt, start + i*4 + 8,
5249 (dops[i].opcode2 & 1) ? alt : addr);
5250 emit_test(s1l,s1l);
5251 emit_cmovs_reg(alt,addr);
5252 }
5253 else
5254 emit_movimm((dops[i].opcode2 & 1) ? cinfo[i].ba : start + i*4 + 8, addr);
57871462 5255 }
ecca05e3 5256 emit_writeword(addr, &pcaddr);
57871462 5257 }
5258 else
cf95b4f0 5259 if(dops[i].itype==RJUMP)
57871462 5260 {
cf95b4f0 5261 int r=get_reg(branch_regs[i].regmap,dops[i].rs1);
4919de1e 5262 if (ds_writes_rjump_rs(i)) {
57871462 5263 r=get_reg(branch_regs[i].regmap,RTEMP);
5264 }
643aeae3 5265 emit_writeword(r,&pcaddr);
57871462 5266 }
7c3a5182 5267 else {SysPrintf("Unknown branch type in do_ccstub\n");abort();}
57871462 5268 }
5269 // Update cycle count
5270 assert(branch_regs[i].regmap[HOST_CCREG]==CCREG||branch_regs[i].regmap[HOST_CCREG]==-1);
2330734f 5271 if(stubs[n].a) emit_addimm(HOST_CCREG,(int)stubs[n].a,HOST_CCREG);
2a014d73 5272 emit_far_call(cc_interrupt);
2330734f 5273 if(stubs[n].a) emit_addimm(HOST_CCREG,-(int)stubs[n].a,HOST_CCREG);
b14b6a8f 5274 if(stubs[n].d==TAKEN) {
277718fa 5275 if(internal_branch(cinfo[i].ba))
5276 load_needed_regs(branch_regs[i].regmap,regs[(cinfo[i].ba-start)>>2].regmap_entry);
cf95b4f0 5277 else if(dops[i].itype==RJUMP) {
57871462 5278 if(get_reg(branch_regs[i].regmap,RTEMP)>=0)
643aeae3 5279 emit_readword(&pcaddr,get_reg(branch_regs[i].regmap,RTEMP));
57871462 5280 else
cf95b4f0 5281 emit_loadreg(dops[i].rs1,get_reg(branch_regs[i].regmap,dops[i].rs1));
57871462 5282 }
b14b6a8f 5283 }else if(stubs[n].d==NOTTAKEN) {
57871462 5284 if(i<slen-2) load_needed_regs(branch_regs[i].regmap,regmap_pre[i+2]);
5285 else load_all_regs(branch_regs[i].regmap);
57871462 5286 }else{
5287 load_all_regs(branch_regs[i].regmap);
5288 }
d1e4ebd9 5289 if (stubs[n].retaddr)
5290 emit_jmp(stubs[n].retaddr);
5291 else
5292 do_jump_vaddr(stubs[n].e);
57871462 5293}
5294
104df9d3 5295static void add_to_linker(void *addr, u_int target, int is_internal)
57871462 5296{
643aeae3 5297 assert(linkcount < ARRAY_SIZE(link_addr));
5298 link_addr[linkcount].addr = addr;
5299 link_addr[linkcount].target = target;
104df9d3 5300 link_addr[linkcount].internal = is_internal;
57871462 5301 linkcount++;
5302}
5303
eba830cd 5304static void ujump_assemble_write_ra(int i)
5305{
5306 int rt;
5307 unsigned int return_address;
5308 rt=get_reg(branch_regs[i].regmap,31);
de6dbc52 5309 //assem_debug("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
eba830cd 5310 //assert(rt>=0);
5311 return_address=start+i*4+8;
5312 if(rt>=0) {
5313 #ifdef USE_MINI_HT
cf95b4f0 5314 if(internal_branch(return_address)&&dops[i+1].rt1!=31) {
eba830cd 5315 int temp=-1; // note: must be ds-safe
5316 #ifdef HOST_TEMPREG
5317 temp=HOST_TEMPREG;
5318 #endif
5319 if(temp>=0) do_miniht_insert(return_address,rt,temp);
5320 else emit_movimm(return_address,rt);
5321 }
5322 else
5323 #endif
5324 {
5325 #ifdef REG_PREFETCH
9f51b4b9 5326 if(temp>=0)
eba830cd 5327 {
643aeae3 5328 if(i_regmap[temp]!=PTEMP) emit_movimm((uintptr_t)hash_table_get(return_address),temp);
eba830cd 5329 }
5330 #endif
de6dbc52 5331 if (!((regs[i].loadedconst >> rt) & 1))
5332 emit_movimm(return_address, rt); // PC into link register
eba830cd 5333 #ifdef IMM_PREFETCH
df4dc2b1 5334 emit_prefetch(hash_table_get(return_address));
eba830cd 5335 #endif
5336 }
5337 }
5338}
5339
2330734f 5340static void ujump_assemble(int i, const struct regstat *i_regs)
57871462 5341{
277718fa 5342 if(i==(cinfo[i].ba-start)>>2) assem_debug("idle loop\n");
57871462 5343 address_generation(i+1,i_regs,regs[i].regmap_entry);
5344 #ifdef REG_PREFETCH
5345 int temp=get_reg(branch_regs[i].regmap,PTEMP);
cf95b4f0 5346 if(dops[i].rt1==31&&temp>=0)
57871462 5347 {
581335b0 5348 signed char *i_regmap=i_regs->regmap;
57871462 5349 int return_address=start+i*4+8;
9f51b4b9 5350 if(get_reg(branch_regs[i].regmap,31)>0)
643aeae3 5351 if(i_regmap[temp]==PTEMP) emit_movimm((uintptr_t)hash_table_get(return_address),temp);
57871462 5352 }
5353 #endif
de6dbc52 5354 if (dops[i].rt1 == 31)
eba830cd 5355 ujump_assemble_write_ra(i); // writeback ra for DS
4ef8f67d 5356 ds_assemble(i+1,i_regs);
5357 uint64_t bc_unneeded=branch_regs[i].u;
cf95b4f0 5358 bc_unneeded|=1|(1LL<<dops[i].rt1);
ad49de89 5359 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,bc_unneeded);
53358c1d 5360 load_reg(regs[i].regmap,branch_regs[i].regmap,CCREG);
57871462 5361 int cc,adj;
5362 cc=get_reg(branch_regs[i].regmap,CCREG);
5363 assert(cc==HOST_CCREG);
277718fa 5364 store_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,cinfo[i].ba);
57871462 5365 #ifdef REG_PREFETCH
cf95b4f0 5366 if(dops[i].rt1==31&&temp>=0) emit_prefetchreg(temp);
57871462 5367 #endif
277718fa 5368 do_cc(i,branch_regs[i].regmap,&adj,cinfo[i].ba,TAKEN,0);
5369 if(adj) emit_addimm(cc, cinfo[i].ccadj + CLOCK_ADJUST(2) - adj, cc);
5370 load_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,cinfo[i].ba);
5371 if(internal_branch(cinfo[i].ba))
57871462 5372 assem_debug("branch: internal\n");
5373 else
5374 assem_debug("branch: external\n");
277718fa 5375 if (internal_branch(cinfo[i].ba) && dops[(cinfo[i].ba-start)>>2].is_ds) {
57871462 5376 ds_assemble_entry(i);
5377 }
5378 else {
277718fa 5379 add_to_linker(out,cinfo[i].ba,internal_branch(cinfo[i].ba));
57871462 5380 emit_jmp(0);
5381 }
5382}
5383
eba830cd 5384static void rjump_assemble_write_ra(int i)
5385{
5386 int rt,return_address;
a5cd72d0 5387 rt=get_reg_w(branch_regs[i].regmap, dops[i].rt1);
de6dbc52 5388 //assem_debug("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
eba830cd 5389 assert(rt>=0);
5390 return_address=start+i*4+8;
5391 #ifdef REG_PREFETCH
9f51b4b9 5392 if(temp>=0)
eba830cd 5393 {
643aeae3 5394 if(i_regmap[temp]!=PTEMP) emit_movimm((uintptr_t)hash_table_get(return_address),temp);
eba830cd 5395 }
5396 #endif
de6dbc52 5397 if (!((regs[i].loadedconst >> rt) & 1))
5398 emit_movimm(return_address, rt); // PC into link register
eba830cd 5399 #ifdef IMM_PREFETCH
df4dc2b1 5400 emit_prefetch(hash_table_get(return_address));
eba830cd 5401 #endif
5402}
5403
2330734f 5404static void rjump_assemble(int i, const struct regstat *i_regs)
57871462 5405{
57871462 5406 int temp;
581335b0 5407 int rs,cc;
cf95b4f0 5408 rs=get_reg(branch_regs[i].regmap,dops[i].rs1);
57871462 5409 assert(rs>=0);
4919de1e 5410 if (ds_writes_rjump_rs(i)) {
57871462 5411 // Delay slot abuse, make a copy of the branch address register
5412 temp=get_reg(branch_regs[i].regmap,RTEMP);
5413 assert(temp>=0);
5414 assert(regs[i].regmap[temp]==RTEMP);
5415 emit_mov(rs,temp);
5416 rs=temp;
5417 }
5418 address_generation(i+1,i_regs,regs[i].regmap_entry);
5419 #ifdef REG_PREFETCH
cf95b4f0 5420 if(dops[i].rt1==31)
57871462 5421 {
5422 if((temp=get_reg(branch_regs[i].regmap,PTEMP))>=0) {
581335b0 5423 signed char *i_regmap=i_regs->regmap;
57871462 5424 int return_address=start+i*4+8;
643aeae3 5425 if(i_regmap[temp]==PTEMP) emit_movimm((uintptr_t)hash_table_get(return_address),temp);
57871462 5426 }
5427 }
5428 #endif
5429 #ifdef USE_MINI_HT
cf95b4f0 5430 if(dops[i].rs1==31) {
57871462 5431 int rh=get_reg(regs[i].regmap,RHASH);
5432 if(rh>=0) do_preload_rhash(rh);
5433 }
5434 #endif
de6dbc52 5435 if (dops[i].rt1 != 0)
eba830cd 5436 rjump_assemble_write_ra(i);
d5910d5d 5437 ds_assemble(i+1,i_regs);
5438 uint64_t bc_unneeded=branch_regs[i].u;
cf95b4f0 5439 bc_unneeded|=1|(1LL<<dops[i].rt1);
5440 bc_unneeded&=~(1LL<<dops[i].rs1);
ad49de89 5441 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,bc_unneeded);
cf95b4f0 5442 load_regs(regs[i].regmap,branch_regs[i].regmap,dops[i].rs1,CCREG);
57871462 5443 cc=get_reg(branch_regs[i].regmap,CCREG);
5444 assert(cc==HOST_CCREG);
581335b0 5445 (void)cc;
57871462 5446 #ifdef USE_MINI_HT
5447 int rh=get_reg(branch_regs[i].regmap,RHASH);
5448 int ht=get_reg(branch_regs[i].regmap,RHTBL);
cf95b4f0 5449 if(dops[i].rs1==31) {
57871462 5450 if(regs[i].regmap[rh]!=RHASH) do_preload_rhash(rh);
5451 do_preload_rhtbl(ht);
5452 do_rhash(rs,rh);
5453 }
5454 #endif
ad49de89 5455 store_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,-1);
57871462 5456 #ifdef DESTRUCTIVE_WRITEBACK
ad49de89 5457 if((branch_regs[i].dirty>>rs)&1) {
cf95b4f0 5458 if(dops[i].rs1!=dops[i+1].rt1&&dops[i].rs1!=dops[i+1].rt2) {
5459 emit_loadreg(dops[i].rs1,rs);
57871462 5460 }
5461 }
5462 #endif
5463 #ifdef REG_PREFETCH
cf95b4f0 5464 if(dops[i].rt1==31&&temp>=0) emit_prefetchreg(temp);
57871462 5465 #endif
5466 #ifdef USE_MINI_HT
cf95b4f0 5467 if(dops[i].rs1==31) {
57871462 5468 do_miniht_load(ht,rh);
5469 }
5470 #endif
5471 //do_cc(i,branch_regs[i].regmap,&adj,-1,TAKEN);
277718fa 5472 //if(adj) emit_addimm(cc,2*(cinfo[i].ccadj+2-adj),cc); // ??? - Shouldn't happen
57871462 5473 //assert(adj==0);
277718fa 5474 emit_addimm_and_set_flags(cinfo[i].ccadj + CLOCK_ADJUST(2), HOST_CCREG);
d1e4ebd9 5475 add_stub(CC_STUB,out,NULL,0,i,-1,TAKEN,rs);
a5cd72d0 5476 if (dops[i+1].itype == RFE)
911f2d55 5477 // special case for RFE
5478 emit_jmp(0);
5479 else
71e490c5 5480 emit_jns(0);
ad49de89 5481 //load_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,-1);
57871462 5482 #ifdef USE_MINI_HT
cf95b4f0 5483 if(dops[i].rs1==31) {
57871462 5484 do_miniht_jump(rs,rh,ht);
5485 }
5486 else
5487 #endif
5488 {
d1e4ebd9 5489 do_jump_vaddr(rs);
57871462 5490 }
57871462 5491 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
cf95b4f0 5492 if(dops[i].rt1!=31&&i<slen-2&&(((u_int)out)&7)) emit_mov(13,13);
57871462 5493 #endif
5494}
5495
2330734f 5496static void cjump_assemble(int i, const struct regstat *i_regs)
57871462 5497{
2330734f 5498 const signed char *i_regmap = i_regs->regmap;
57871462 5499 int cc;
5500 int match;
277718fa 5501 match=match_bt(branch_regs[i].regmap,branch_regs[i].dirty,cinfo[i].ba);
57871462 5502 assem_debug("match=%d\n",match);
ad49de89 5503 int s1l,s2l;
57871462 5504 int unconditional=0,nop=0;
57871462 5505 int invert=0;
277718fa 5506 int internal=internal_branch(cinfo[i].ba);
5507 if(i==(cinfo[i].ba-start)>>2) assem_debug("idle loop\n");
57871462 5508 if(!match) invert=1;
5509 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
277718fa 5510 if(i>(cinfo[i].ba-start)>>2) invert=1;
57871462 5511 #endif
3968e69e 5512 #ifdef __aarch64__
5513 invert=1; // because of near cond. branches
5514 #endif
9f51b4b9 5515
cf95b4f0 5516 if(dops[i].ooo) {
5517 s1l=get_reg(branch_regs[i].regmap,dops[i].rs1);
5518 s2l=get_reg(branch_regs[i].regmap,dops[i].rs2);
57871462 5519 }
5520 else {
cf95b4f0 5521 s1l=get_reg(i_regmap,dops[i].rs1);
5522 s2l=get_reg(i_regmap,dops[i].rs2);
57871462 5523 }
cf95b4f0 5524 if(dops[i].rs1==0&&dops[i].rs2==0)
57871462 5525 {
cf95b4f0 5526 if(dops[i].opcode&1) nop=1;
57871462 5527 else unconditional=1;
cf95b4f0 5528 //assert(dops[i].opcode!=5);
5529 //assert(dops[i].opcode!=7);
5530 //assert(dops[i].opcode!=0x15);
5531 //assert(dops[i].opcode!=0x17);
57871462 5532 }
cf95b4f0 5533 else if(dops[i].rs1==0)
57871462 5534 {
ad49de89 5535 s1l=s2l;
5536 s2l=-1;
57871462 5537 }
cf95b4f0 5538 else if(dops[i].rs2==0)
57871462 5539 {
ad49de89 5540 s2l=-1;
57871462 5541 }
5542
cf95b4f0 5543 if(dops[i].ooo) {
57871462 5544 // Out of order execution (delay slot first)
5545 //printf("OOOE\n");
5546 address_generation(i+1,i_regs,regs[i].regmap_entry);
5547 ds_assemble(i+1,i_regs);
5548 int adj;
5549 uint64_t bc_unneeded=branch_regs[i].u;
cf95b4f0 5550 bc_unneeded&=~((1LL<<dops[i].rs1)|(1LL<<dops[i].rs2));
57871462 5551 bc_unneeded|=1;
ad49de89 5552 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,bc_unneeded);
cf95b4f0 5553 load_regs(regs[i].regmap,branch_regs[i].regmap,dops[i].rs1,dops[i].rs2);
53358c1d 5554 load_reg(regs[i].regmap,branch_regs[i].regmap,CCREG);
57871462 5555 cc=get_reg(branch_regs[i].regmap,CCREG);
5556 assert(cc==HOST_CCREG);
9f51b4b9 5557 if(unconditional)
277718fa 5558 store_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,cinfo[i].ba);
5559 //do_cc(i,branch_regs[i].regmap,&adj,unconditional?cinfo[i].ba:-1,unconditional);
57871462 5560 //assem_debug("cycle count (adj)\n");
5561 if(unconditional) {
277718fa 5562 do_cc(i,branch_regs[i].regmap,&adj,cinfo[i].ba,TAKEN,0);
5563 if(i!=(cinfo[i].ba-start)>>2 || source[i+1]!=0) {
5564 if(adj) emit_addimm(cc, cinfo[i].ccadj + CLOCK_ADJUST(2) - adj, cc);
5565 load_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,cinfo[i].ba);
57871462 5566 if(internal)
5567 assem_debug("branch: internal\n");
5568 else
5569 assem_debug("branch: external\n");
277718fa 5570 if (internal && dops[(cinfo[i].ba-start)>>2].is_ds) {
57871462 5571 ds_assemble_entry(i);
5572 }
5573 else {
277718fa 5574 add_to_linker(out,cinfo[i].ba,internal);
57871462 5575 emit_jmp(0);
5576 }
5577 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5578 if(((u_int)out)&7) emit_addnop(0);
5579 #endif
5580 }
5581 }
5582 else if(nop) {
277718fa 5583 emit_addimm_and_set_flags(cinfo[i].ccadj + CLOCK_ADJUST(2), cc);
b14b6a8f 5584 void *jaddr=out;
57871462 5585 emit_jns(0);
b14b6a8f 5586 add_stub(CC_STUB,jaddr,out,0,i,start+i*4+8,NOTTAKEN,0);
57871462 5587 }
5588 else {
df4dc2b1 5589 void *taken = NULL, *nottaken = NULL, *nottaken1 = NULL;
57871462 5590 do_cc(i,branch_regs[i].regmap,&adj,-1,0,invert);
277718fa 5591 if(adj&&!invert) emit_addimm(cc, cinfo[i].ccadj + CLOCK_ADJUST(2) - adj, cc);
9f51b4b9 5592
57871462 5593 //printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5594 assert(s1l>=0);
cf95b4f0 5595 if(dops[i].opcode==4) // BEQ
57871462 5596 {
5597 if(s2l>=0) emit_cmp(s1l,s2l);
5598 else emit_test(s1l,s1l);
5599 if(invert){
df4dc2b1 5600 nottaken=out;
7c3a5182 5601 emit_jne(DJT_1);
57871462 5602 }else{
277718fa 5603 add_to_linker(out,cinfo[i].ba,internal);
57871462 5604 emit_jeq(0);
5605 }
5606 }
cf95b4f0 5607 if(dops[i].opcode==5) // BNE
57871462 5608 {
5609 if(s2l>=0) emit_cmp(s1l,s2l);
5610 else emit_test(s1l,s1l);
5611 if(invert){
df4dc2b1 5612 nottaken=out;
7c3a5182 5613 emit_jeq(DJT_1);
57871462 5614 }else{
277718fa 5615 add_to_linker(out,cinfo[i].ba,internal);
57871462 5616 emit_jne(0);
5617 }
5618 }
cf95b4f0 5619 if(dops[i].opcode==6) // BLEZ
57871462 5620 {
5621 emit_cmpimm(s1l,1);
5622 if(invert){
df4dc2b1 5623 nottaken=out;
7c3a5182 5624 emit_jge(DJT_1);
57871462 5625 }else{
277718fa 5626 add_to_linker(out,cinfo[i].ba,internal);
57871462 5627 emit_jl(0);
5628 }
5629 }
cf95b4f0 5630 if(dops[i].opcode==7) // BGTZ
57871462 5631 {
5632 emit_cmpimm(s1l,1);
5633 if(invert){
df4dc2b1 5634 nottaken=out;
7c3a5182 5635 emit_jl(DJT_1);
57871462 5636 }else{
277718fa 5637 add_to_linker(out,cinfo[i].ba,internal);
57871462 5638 emit_jge(0);
5639 }
5640 }
5641 if(invert) {
df4dc2b1 5642 if(taken) set_jump_target(taken, out);
57871462 5643 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
277718fa 5644 if (match && (!internal || !dops[(cinfo[i].ba-start)>>2].is_ds)) {
57871462 5645 if(adj) {
2330734f 5646 emit_addimm(cc,-adj,cc);
277718fa 5647 add_to_linker(out,cinfo[i].ba,internal);
57871462 5648 }else{
5649 emit_addnop(13);
277718fa 5650 add_to_linker(out,cinfo[i].ba,internal*2);
57871462 5651 }
5652 emit_jmp(0);
5653 }else
5654 #endif
5655 {
2330734f 5656 if(adj) emit_addimm(cc,-adj,cc);
277718fa 5657 store_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,cinfo[i].ba);
5658 load_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,cinfo[i].ba);
57871462 5659 if(internal)
5660 assem_debug("branch: internal\n");
5661 else
5662 assem_debug("branch: external\n");
277718fa 5663 if (internal && dops[(cinfo[i].ba - start) >> 2].is_ds) {
57871462 5664 ds_assemble_entry(i);
5665 }
5666 else {
277718fa 5667 add_to_linker(out,cinfo[i].ba,internal);
57871462 5668 emit_jmp(0);
5669 }
5670 }
df4dc2b1 5671 set_jump_target(nottaken, out);
57871462 5672 }
5673
df4dc2b1 5674 if(nottaken1) set_jump_target(nottaken1, out);
57871462 5675 if(adj) {
2330734f 5676 if(!invert) emit_addimm(cc,adj,cc);
57871462 5677 }
5678 } // (!unconditional)
5679 } // if(ooo)
5680 else
5681 {
5682 // In-order execution (branch first)
df4dc2b1 5683 void *taken = NULL, *nottaken = NULL, *nottaken1 = NULL;
57871462 5684 if(!unconditional&&!nop) {
57871462 5685 //printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5686 assert(s1l>=0);
cf95b4f0 5687 if((dops[i].opcode&0x2f)==4) // BEQ
57871462 5688 {
5689 if(s2l>=0) emit_cmp(s1l,s2l);
5690 else emit_test(s1l,s1l);
df4dc2b1 5691 nottaken=out;
7c3a5182 5692 emit_jne(DJT_2);
57871462 5693 }
cf95b4f0 5694 if((dops[i].opcode&0x2f)==5) // BNE
57871462 5695 {
5696 if(s2l>=0) emit_cmp(s1l,s2l);
5697 else emit_test(s1l,s1l);
df4dc2b1 5698 nottaken=out;
7c3a5182 5699 emit_jeq(DJT_2);
57871462 5700 }
cf95b4f0 5701 if((dops[i].opcode&0x2f)==6) // BLEZ
57871462 5702 {
5703 emit_cmpimm(s1l,1);
df4dc2b1 5704 nottaken=out;
7c3a5182 5705 emit_jge(DJT_2);
57871462 5706 }
cf95b4f0 5707 if((dops[i].opcode&0x2f)==7) // BGTZ
57871462 5708 {
5709 emit_cmpimm(s1l,1);
df4dc2b1 5710 nottaken=out;
7c3a5182 5711 emit_jl(DJT_2);
57871462 5712 }
5713 } // if(!unconditional)
5714 int adj;
5715 uint64_t ds_unneeded=branch_regs[i].u;
cf95b4f0 5716 ds_unneeded&=~((1LL<<dops[i+1].rs1)|(1LL<<dops[i+1].rs2));
57871462 5717 ds_unneeded|=1;
57871462 5718 // branch taken
5719 if(!nop) {
df4dc2b1 5720 if(taken) set_jump_target(taken, out);
57871462 5721 assem_debug("1:\n");
ad49de89 5722 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,ds_unneeded);
57871462 5723 // load regs
cf95b4f0 5724 load_regs(regs[i].regmap,branch_regs[i].regmap,dops[i+1].rs1,dops[i+1].rs2);
57871462 5725 address_generation(i+1,&branch_regs[i],0);
37387d8b 5726 if (ram_offset)
53358c1d 5727 load_reg(regs[i].regmap,branch_regs[i].regmap,ROREG);
ad49de89 5728 load_regs(regs[i].regmap,branch_regs[i].regmap,CCREG,INVCP);
57871462 5729 ds_assemble(i+1,&branch_regs[i]);
4f13a577 5730 drc_dbg_emit_wb_dirtys(i+1, &branch_regs[i]);
57871462 5731 cc=get_reg(branch_regs[i].regmap,CCREG);
5732 if(cc==-1) {
5733 emit_loadreg(CCREG,cc=HOST_CCREG);
5734 // CHECK: Is the following instruction (fall thru) allocated ok?
5735 }
5736 assert(cc==HOST_CCREG);
277718fa 5737 store_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,cinfo[i].ba);
5738 do_cc(i,i_regmap,&adj,cinfo[i].ba,TAKEN,0);
57871462 5739 assem_debug("cycle count (adj)\n");
277718fa 5740 if(adj) emit_addimm(cc, cinfo[i].ccadj + CLOCK_ADJUST(2) - adj, cc);
5741 load_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,cinfo[i].ba);
57871462 5742 if(internal)
5743 assem_debug("branch: internal\n");
5744 else
5745 assem_debug("branch: external\n");
277718fa 5746 if (internal && dops[(cinfo[i].ba - start) >> 2].is_ds) {
57871462 5747 ds_assemble_entry(i);
5748 }
5749 else {
277718fa 5750 add_to_linker(out,cinfo[i].ba,internal);
57871462 5751 emit_jmp(0);
5752 }
5753 }
5754 // branch not taken
57871462 5755 if(!unconditional) {
df4dc2b1 5756 if(nottaken1) set_jump_target(nottaken1, out);
5757 set_jump_target(nottaken, out);
57871462 5758 assem_debug("2:\n");
fe807a8a 5759 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,ds_unneeded);
37387d8b 5760 // load regs
fe807a8a 5761 load_regs(regs[i].regmap,branch_regs[i].regmap,dops[i+1].rs1,dops[i+1].rs2);
5762 address_generation(i+1,&branch_regs[i],0);
37387d8b 5763 if (ram_offset)
53358c1d 5764 load_reg(regs[i].regmap,branch_regs[i].regmap,ROREG);
37387d8b 5765 load_regs(regs[i].regmap,branch_regs[i].regmap,CCREG,INVCP);
fe807a8a 5766 ds_assemble(i+1,&branch_regs[i]);
57871462 5767 cc=get_reg(branch_regs[i].regmap,CCREG);
fe807a8a 5768 if (cc == -1) {
57871462 5769 // Cycle count isn't in a register, temporarily load it then write it out
5770 emit_loadreg(CCREG,HOST_CCREG);
277718fa 5771 emit_addimm_and_set_flags(cinfo[i].ccadj + CLOCK_ADJUST(2), HOST_CCREG);
b14b6a8f 5772 void *jaddr=out;
57871462 5773 emit_jns(0);
b14b6a8f 5774 add_stub(CC_STUB,jaddr,out,0,i,start+i*4+8,NOTTAKEN,0);
57871462 5775 emit_storereg(CCREG,HOST_CCREG);
5776 }
5777 else{
5778 cc=get_reg(i_regmap,CCREG);
5779 assert(cc==HOST_CCREG);
277718fa 5780 emit_addimm_and_set_flags(cinfo[i].ccadj + CLOCK_ADJUST(2), cc);
b14b6a8f 5781 void *jaddr=out;
57871462 5782 emit_jns(0);
fe807a8a 5783 add_stub(CC_STUB,jaddr,out,0,i,start+i*4+8,NOTTAKEN,0);
57871462 5784 }
5785 }
5786 }
5787}
5788
2330734f 5789static void sjump_assemble(int i, const struct regstat *i_regs)
57871462 5790{
2330734f 5791 const signed char *i_regmap = i_regs->regmap;
57871462 5792 int cc;
5793 int match;
277718fa 5794 match=match_bt(branch_regs[i].regmap,branch_regs[i].dirty,cinfo[i].ba);
2acc46cd 5795 assem_debug("smatch=%d ooo=%d\n", match, dops[i].ooo);
ad49de89 5796 int s1l;
57871462 5797 int unconditional=0,nevertaken=0;
57871462 5798 int invert=0;
277718fa 5799 int internal=internal_branch(cinfo[i].ba);
5800 if(i==(cinfo[i].ba-start)>>2) assem_debug("idle loop\n");
57871462 5801 if(!match) invert=1;
5802 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
277718fa 5803 if(i>(cinfo[i].ba-start)>>2) invert=1;
57871462 5804 #endif
3968e69e 5805 #ifdef __aarch64__
5806 invert=1; // because of near cond. branches
5807 #endif
57871462 5808
cf95b4f0 5809 //if(dops[i].opcode2>=0x10) return; // FIXME (BxxZAL)
5810 //assert(dops[i].opcode2<0x10||dops[i].rs1==0); // FIXME (BxxZAL)
57871462 5811
cf95b4f0 5812 if(dops[i].ooo) {
5813 s1l=get_reg(branch_regs[i].regmap,dops[i].rs1);
57871462 5814 }
5815 else {
cf95b4f0 5816 s1l=get_reg(i_regmap,dops[i].rs1);
57871462 5817 }
cf95b4f0 5818 if(dops[i].rs1==0)
57871462 5819 {
cf95b4f0 5820 if(dops[i].opcode2&1) unconditional=1;
57871462 5821 else nevertaken=1;
5822 // These are never taken (r0 is never less than zero)
cf95b4f0 5823 //assert(dops[i].opcode2!=0);
5824 //assert(dops[i].opcode2!=2);
5825 //assert(dops[i].opcode2!=0x10);
5826 //assert(dops[i].opcode2!=0x12);
57871462 5827 }
57871462 5828
cf95b4f0 5829 if(dops[i].ooo) {
57871462 5830 // Out of order execution (delay slot first)
5831 //printf("OOOE\n");
5832 address_generation(i+1,i_regs,regs[i].regmap_entry);
5833 ds_assemble(i+1,i_regs);
5834 int adj;
5835 uint64_t bc_unneeded=branch_regs[i].u;
cf95b4f0 5836 bc_unneeded&=~((1LL<<dops[i].rs1)|(1LL<<dops[i].rs2));
57871462 5837 bc_unneeded|=1;
ad49de89 5838 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,bc_unneeded);
cf95b4f0 5839 load_regs(regs[i].regmap,branch_regs[i].regmap,dops[i].rs1,dops[i].rs1);
53358c1d 5840 load_reg(regs[i].regmap,branch_regs[i].regmap,CCREG);
cf95b4f0 5841 if(dops[i].rt1==31) {
57871462 5842 int rt,return_address;
57871462 5843 rt=get_reg(branch_regs[i].regmap,31);
de6dbc52 5844 //assem_debug("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
57871462 5845 if(rt>=0) {
5846 // Save the PC even if the branch is not taken
5847 return_address=start+i*4+8;
5848 emit_movimm(return_address,rt); // PC into link register
5849 #ifdef IMM_PREFETCH
df4dc2b1 5850 if(!nevertaken) emit_prefetch(hash_table_get(return_address));
57871462 5851 #endif
5852 }
5853 }
5854 cc=get_reg(branch_regs[i].regmap,CCREG);
5855 assert(cc==HOST_CCREG);
9f51b4b9 5856 if(unconditional)
277718fa 5857 store_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,cinfo[i].ba);
5858 //do_cc(i,branch_regs[i].regmap,&adj,unconditional?cinfo[i].ba:-1,unconditional);
57871462 5859 assem_debug("cycle count (adj)\n");
5860 if(unconditional) {
277718fa 5861 do_cc(i,branch_regs[i].regmap,&adj,cinfo[i].ba,TAKEN,0);
5862 if(i!=(cinfo[i].ba-start)>>2 || source[i+1]!=0) {
5863 if(adj) emit_addimm(cc, cinfo[i].ccadj + CLOCK_ADJUST(2) - adj, cc);
5864 load_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,cinfo[i].ba);
57871462 5865 if(internal)
5866 assem_debug("branch: internal\n");
5867 else
5868 assem_debug("branch: external\n");
277718fa 5869 if (internal && dops[(cinfo[i].ba - start) >> 2].is_ds) {
57871462 5870 ds_assemble_entry(i);
5871 }
5872 else {
277718fa 5873 add_to_linker(out,cinfo[i].ba,internal);
57871462 5874 emit_jmp(0);
5875 }
5876 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5877 if(((u_int)out)&7) emit_addnop(0);
5878 #endif
5879 }
5880 }
5881 else if(nevertaken) {
277718fa 5882 emit_addimm_and_set_flags(cinfo[i].ccadj + CLOCK_ADJUST(2), cc);
b14b6a8f 5883 void *jaddr=out;
57871462 5884 emit_jns(0);
b14b6a8f 5885 add_stub(CC_STUB,jaddr,out,0,i,start+i*4+8,NOTTAKEN,0);
57871462 5886 }
5887 else {
df4dc2b1 5888 void *nottaken = NULL;
57871462 5889 do_cc(i,branch_regs[i].regmap,&adj,-1,0,invert);
277718fa 5890 if(adj&&!invert) emit_addimm(cc, cinfo[i].ccadj + CLOCK_ADJUST(2) - adj, cc);
57871462 5891 {
5892 assert(s1l>=0);
ecca05e3 5893 if ((dops[i].opcode2 & 1) == 0) // BLTZ/BLTZAL
57871462 5894 {
5895 emit_test(s1l,s1l);
5896 if(invert){
df4dc2b1 5897 nottaken=out;
7c3a5182 5898 emit_jns(DJT_1);
57871462 5899 }else{
277718fa 5900 add_to_linker(out,cinfo[i].ba,internal);
57871462 5901 emit_js(0);
5902 }
5903 }
ecca05e3 5904 else // BGEZ/BGEZAL
57871462 5905 {
5906 emit_test(s1l,s1l);
5907 if(invert){
df4dc2b1 5908 nottaken=out;
7c3a5182 5909 emit_js(DJT_1);
57871462 5910 }else{
277718fa 5911 add_to_linker(out,cinfo[i].ba,internal);
57871462 5912 emit_jns(0);
5913 }
5914 }
ad49de89 5915 }
9f51b4b9 5916
57871462 5917 if(invert) {
5918 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
277718fa 5919 if (match && (!internal || !dops[(cinfo[i].ba - start) >> 2].is_ds)) {
57871462 5920 if(adj) {
2330734f 5921 emit_addimm(cc,-adj,cc);
277718fa 5922 add_to_linker(out,cinfo[i].ba,internal);
57871462 5923 }else{
5924 emit_addnop(13);
277718fa 5925 add_to_linker(out,cinfo[i].ba,internal*2);
57871462 5926 }
5927 emit_jmp(0);
5928 }else
5929 #endif
5930 {
2330734f 5931 if(adj) emit_addimm(cc,-adj,cc);
277718fa 5932 store_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,cinfo[i].ba);
5933 load_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,cinfo[i].ba);
57871462 5934 if(internal)
5935 assem_debug("branch: internal\n");
5936 else
5937 assem_debug("branch: external\n");
277718fa 5938 if (internal && dops[(cinfo[i].ba - start) >> 2].is_ds) {
57871462 5939 ds_assemble_entry(i);
5940 }
5941 else {
277718fa 5942 add_to_linker(out,cinfo[i].ba,internal);
57871462 5943 emit_jmp(0);
5944 }
5945 }
df4dc2b1 5946 set_jump_target(nottaken, out);
57871462 5947 }
5948
5949 if(adj) {
2330734f 5950 if(!invert) emit_addimm(cc,adj,cc);
57871462 5951 }
5952 } // (!unconditional)
5953 } // if(ooo)
5954 else
5955 {
5956 // In-order execution (branch first)
5957 //printf("IOE\n");
df4dc2b1 5958 void *nottaken = NULL;
de6dbc52 5959 if (!unconditional && !nevertaken) {
ecca05e3 5960 assert(s1l >= 0);
5961 emit_test(s1l, s1l);
5962 }
5963 if (dops[i].rt1 == 31) {
5964 int rt, return_address;
5965 rt = get_reg(branch_regs[i].regmap,31);
5966 if(rt >= 0) {
a6491170 5967 // Save the PC even if the branch is not taken
ecca05e3 5968 return_address = start + i*4+8;
5969 emit_movimm(return_address, rt); // PC into link register
a6491170 5970 #ifdef IMM_PREFETCH
df4dc2b1 5971 emit_prefetch(hash_table_get(return_address));
a6491170 5972 #endif
5973 }
5974 }
de6dbc52 5975 if (!unconditional && !nevertaken) {
ecca05e3 5976 nottaken = out;
5977 if (!(dops[i].opcode2 & 1)) // BLTZ/BLTZAL
5978 emit_jns(DJT_1);
5979 else // BGEZ/BGEZAL
5980 emit_js(DJT_1);
5981 }
57871462 5982 int adj;
5983 uint64_t ds_unneeded=branch_regs[i].u;
cf95b4f0 5984 ds_unneeded&=~((1LL<<dops[i+1].rs1)|(1LL<<dops[i+1].rs2));
57871462 5985 ds_unneeded|=1;
57871462 5986 // branch taken
5987 if(!nevertaken) {
5988 //assem_debug("1:\n");
ad49de89 5989 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,ds_unneeded);
57871462 5990 // load regs
cf95b4f0 5991 load_regs(regs[i].regmap,branch_regs[i].regmap,dops[i+1].rs1,dops[i+1].rs2);
57871462 5992 address_generation(i+1,&branch_regs[i],0);
37387d8b 5993 if (ram_offset)
53358c1d 5994 load_reg(regs[i].regmap,branch_regs[i].regmap,ROREG);
ad49de89 5995 load_regs(regs[i].regmap,branch_regs[i].regmap,CCREG,INVCP);
57871462 5996 ds_assemble(i+1,&branch_regs[i]);
5997 cc=get_reg(branch_regs[i].regmap,CCREG);
5998 if(cc==-1) {
5999 emit_loadreg(CCREG,cc=HOST_CCREG);
6000 // CHECK: Is the following instruction (fall thru) allocated ok?
6001 }
6002 assert(cc==HOST_CCREG);
277718fa 6003 store_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,cinfo[i].ba);
6004 do_cc(i,i_regmap,&adj,cinfo[i].ba,TAKEN,0);
57871462 6005 assem_debug("cycle count (adj)\n");
277718fa 6006 if(adj) emit_addimm(cc, cinfo[i].ccadj + CLOCK_ADJUST(2) - adj, cc);
6007 load_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,cinfo[i].ba);
57871462 6008 if(internal)
6009 assem_debug("branch: internal\n");
6010 else
6011 assem_debug("branch: external\n");
277718fa 6012 if (internal && dops[(cinfo[i].ba - start) >> 2].is_ds) {
57871462 6013 ds_assemble_entry(i);
6014 }
6015 else {
277718fa 6016 add_to_linker(out,cinfo[i].ba,internal);
57871462 6017 emit_jmp(0);
6018 }
6019 }
6020 // branch not taken
57871462 6021 if(!unconditional) {
de6dbc52 6022 if (!nevertaken) {
6023 assert(nottaken);
6024 set_jump_target(nottaken, out);
6025 }
57871462 6026 assem_debug("1:\n");
fe807a8a 6027 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,ds_unneeded);
6028 load_regs(regs[i].regmap,branch_regs[i].regmap,dops[i+1].rs1,dops[i+1].rs2);
6029 address_generation(i+1,&branch_regs[i],0);
5a18ce2e 6030 if (ram_offset)
53358c1d 6031 load_reg(regs[i].regmap,branch_regs[i].regmap,ROREG);
5a18ce2e 6032 load_regs(regs[i].regmap,branch_regs[i].regmap,CCREG,INVCP);
fe807a8a 6033 ds_assemble(i+1,&branch_regs[i]);
57871462 6034 cc=get_reg(branch_regs[i].regmap,CCREG);
fe807a8a 6035 if (cc == -1) {
57871462 6036 // Cycle count isn't in a register, temporarily load it then write it out
6037 emit_loadreg(CCREG,HOST_CCREG);
277718fa 6038 emit_addimm_and_set_flags(cinfo[i].ccadj + CLOCK_ADJUST(2), HOST_CCREG);
b14b6a8f 6039 void *jaddr=out;
57871462 6040 emit_jns(0);
b14b6a8f 6041 add_stub(CC_STUB,jaddr,out,0,i,start+i*4+8,NOTTAKEN,0);
57871462 6042 emit_storereg(CCREG,HOST_CCREG);
6043 }
6044 else{
6045 cc=get_reg(i_regmap,CCREG);
6046 assert(cc==HOST_CCREG);
277718fa 6047 emit_addimm_and_set_flags(cinfo[i].ccadj + CLOCK_ADJUST(2), cc);
b14b6a8f 6048 void *jaddr=out;
57871462 6049 emit_jns(0);
fe807a8a 6050 add_stub(CC_STUB,jaddr,out,0,i,start+i*4+8,NOTTAKEN,0);
57871462 6051 }
6052 }
6053 }
6054}
6055
670c0f22 6056static void check_regmap(signed char *regmap)
6057{
6058#ifndef NDEBUG
6059 int i,j;
6060 for (i = 0; i < HOST_REGS; i++) {
6061 if (regmap[i] < 0)
6062 continue;
6063 for (j = i + 1; j < HOST_REGS; j++)
6064 assert(regmap[i] != regmap[j]);
6065 }
6066#endif
6067}
6068
4600ba03 6069#ifdef DISASM
2acc46cd 6070#include <inttypes.h>
53dc27f6 6071static char insn[MAXBLOCK][10];
6072
6073#define set_mnemonic(i_, n_) \
6074 strcpy(insn[i_], n_)
6075
2acc46cd 6076void print_regmap(const char *name, const signed char *regmap)
6077{
6078 char buf[5];
6079 int i, l;
6080 fputs(name, stdout);
6081 for (i = 0; i < HOST_REGS; i++) {
6082 l = 0;
6083 if (regmap[i] >= 0)
6084 l = snprintf(buf, sizeof(buf), "$%d", regmap[i]);
6085 for (; l < 3; l++)
6086 buf[l] = ' ';
6087 buf[l] = 0;
6088 printf(" r%d=%s", i, buf);
6089 }
6090 fputs("\n", stdout);
6091}
6092
57871462 6093 /* disassembly */
6094void disassemble_inst(int i)
6095{
cf95b4f0 6096 if (dops[i].bt) printf("*"); else printf(" ");
6097 switch(dops[i].itype) {
57871462 6098 case UJUMP:
277718fa 6099 printf (" %x: %s %8x\n",start+i*4,insn[i],cinfo[i].ba);break;
57871462 6100 case CJUMP:
277718fa 6101 printf (" %x: %s r%d,r%d,%8x\n",start+i*4,insn[i],dops[i].rs1,dops[i].rs2,i?start+i*4+4+((signed int)((unsigned int)source[i]<<16)>>14):cinfo[i].ba);break;
57871462 6102 case SJUMP:
cf95b4f0 6103 printf (" %x: %s r%d,%8x\n",start+i*4,insn[i],dops[i].rs1,start+i*4+4+((signed int)((unsigned int)source[i]<<16)>>14));break;
57871462 6104 case RJUMP:
ecca05e3 6105 if (dops[i].opcode2 == 9 && dops[i].rt1 != 31)
cf95b4f0 6106 printf (" %x: %s r%d,r%d\n",start+i*4,insn[i],dops[i].rt1,dops[i].rs1);
5067f341 6107 else
cf95b4f0 6108 printf (" %x: %s r%d\n",start+i*4,insn[i],dops[i].rs1);
5067f341 6109 break;
57871462 6110 case IMM16:
cf95b4f0 6111 if(dops[i].opcode==0xf) //LUI
277718fa 6112 printf (" %x: %s r%d,%4x0000\n",start+i*4,insn[i],dops[i].rt1,cinfo[i].imm&0xffff);
57871462 6113 else
277718fa 6114 printf (" %x: %s r%d,r%d,%d\n",start+i*4,insn[i],dops[i].rt1,dops[i].rs1,cinfo[i].imm);
57871462 6115 break;
6116 case LOAD:
6117 case LOADLR:
277718fa 6118 printf (" %x: %s r%d,r%d+%x\n",start+i*4,insn[i],dops[i].rt1,dops[i].rs1,cinfo[i].imm);
57871462 6119 break;
6120 case STORE:
6121 case STORELR:
277718fa 6122 printf (" %x: %s r%d,r%d+%x\n",start+i*4,insn[i],dops[i].rs2,dops[i].rs1,cinfo[i].imm);
57871462 6123 break;
6124 case ALU:
6125 case SHIFT:
cf95b4f0 6126 printf (" %x: %s r%d,r%d,r%d\n",start+i*4,insn[i],dops[i].rt1,dops[i].rs1,dops[i].rs2);
57871462 6127 break;
6128 case MULTDIV:
cf95b4f0 6129 printf (" %x: %s r%d,r%d\n",start+i*4,insn[i],dops[i].rs1,dops[i].rs2);
57871462 6130 break;
6131 case SHIFTIMM:
277718fa 6132 printf (" %x: %s r%d,r%d,%d\n",start+i*4,insn[i],dops[i].rt1,dops[i].rs1,cinfo[i].imm);
57871462 6133 break;
6134 case MOV:
cf95b4f0 6135 if((dops[i].opcode2&0x1d)==0x10)
6136 printf (" %x: %s r%d\n",start+i*4,insn[i],dops[i].rt1);
6137 else if((dops[i].opcode2&0x1d)==0x11)
6138 printf (" %x: %s r%d\n",start+i*4,insn[i],dops[i].rs1);
57871462 6139 else
6140 printf (" %x: %s\n",start+i*4,insn[i]);
6141 break;
6142 case COP0:
cf95b4f0 6143 if(dops[i].opcode2==0)
6144 printf (" %x: %s r%d,cpr0[%d]\n",start+i*4,insn[i],dops[i].rt1,(source[i]>>11)&0x1f); // MFC0
6145 else if(dops[i].opcode2==4)
6146 printf (" %x: %s r%d,cpr0[%d]\n",start+i*4,insn[i],dops[i].rs1,(source[i]>>11)&0x1f); // MTC0
57871462 6147 else printf (" %x: %s\n",start+i*4,insn[i]);
6148 break;
b9b61529 6149 case COP2:
cf95b4f0 6150 if(dops[i].opcode2<3)
6151 printf (" %x: %s r%d,cpr2[%d]\n",start+i*4,insn[i],dops[i].rt1,(source[i]>>11)&0x1f); // MFC2
6152 else if(dops[i].opcode2>3)
6153 printf (" %x: %s r%d,cpr2[%d]\n",start+i*4,insn[i],dops[i].rs1,(source[i]>>11)&0x1f); // MTC2
b9b61529 6154 else printf (" %x: %s\n",start+i*4,insn[i]);
6155 break;
b9b61529 6156 case C2LS:
277718fa 6157 printf (" %x: %s cpr2[%d],r%d+%x\n",start+i*4,insn[i],(source[i]>>16)&0x1f,dops[i].rs1,cinfo[i].imm);
b9b61529 6158 break;
1e973cb0 6159 case INTCALL:
6160 printf (" %x: %s (INTCALL)\n",start+i*4,insn[i]);
6161 break;
57871462 6162 default:
6163 //printf (" %s %8x\n",insn[i],source[i]);
6164 printf (" %x: %s\n",start+i*4,insn[i]);
6165 }
a5cd72d0 6166 #ifndef REGMAP_PRINT
2acc46cd 6167 return;
a5cd72d0 6168 #endif
33a1eda1 6169 printf("D: %x WD: %x U: %"PRIx64" hC: %x hWC: %x hLC: %x\n",
a5cd72d0 6170 regs[i].dirty, regs[i].wasdirty, unneeded_reg[i],
6171 regs[i].isconst, regs[i].wasconst, regs[i].loadedconst);
2acc46cd 6172 print_regmap("pre: ", regmap_pre[i]);
6173 print_regmap("entry: ", regs[i].regmap_entry);
6174 print_regmap("map: ", regs[i].regmap);
6175 if (dops[i].is_jump) {
6176 print_regmap("bentry:", branch_regs[i].regmap_entry);
6177 print_regmap("bmap: ", branch_regs[i].regmap);
6178 }
57871462 6179}
4600ba03 6180#else
53dc27f6 6181#define set_mnemonic(i_, n_)
4600ba03 6182static void disassemble_inst(int i) {}
6183#endif // DISASM
57871462 6184
d848b60a 6185#define DRC_TEST_VAL 0x74657374
6186
d9e2b173 6187static noinline void new_dynarec_test(void)
d848b60a 6188{
be516ebe 6189 int (*testfunc)(void);
d148d265 6190 void *beginning;
be516ebe 6191 int ret[2];
6192 size_t i;
d148d265 6193
687b4580 6194 // check structure linkage
7c3a5182 6195 if ((u_char *)rcnts - (u_char *)&psxRegs != sizeof(psxRegs))
687b4580 6196 {
7c3a5182 6197 SysPrintf("linkage_arm* miscompilation/breakage detected.\n");
687b4580 6198 }
6199
d9e2b173 6200 SysPrintf("(%p) testing if we can run recompiled code @%p...\n",
6201 new_dynarec_test, out);
6202 ((volatile u_int *)NDRC_WRITE_OFFSET(out))[0]++; // make the cache dirty
be516ebe 6203
6204 for (i = 0; i < ARRAY_SIZE(ret); i++) {
2a014d73 6205 out = ndrc->translation_cache;
be516ebe 6206 beginning = start_block();
6207 emit_movimm(DRC_TEST_VAL + i, 0); // test
6208 emit_ret();
6209 literal_pool(0);
6210 end_block(beginning);
6211 testfunc = beginning;
6212 ret[i] = testfunc();
6213 }
6214
6215 if (ret[0] == DRC_TEST_VAL && ret[1] == DRC_TEST_VAL + 1)
d848b60a 6216 SysPrintf("test passed.\n");
6217 else
be516ebe 6218 SysPrintf("test failed, will likely crash soon (r=%08x %08x)\n", ret[0], ret[1]);
2a014d73 6219 out = ndrc->translation_cache;
d848b60a 6220}
6221
42eb665e 6222static int get_cycle_multiplier(void)
6223{
6224 return Config.cycle_multiplier_override && Config.cycle_multiplier == CYCLE_MULT_DEFAULT
6225 ? Config.cycle_multiplier_override : Config.cycle_multiplier;
6226}
6227
dc990066 6228// clear the state completely, instead of just marking
6229// things invalid like invalidate_all_pages() does
919981d0 6230void new_dynarec_clear_full(void)
57871462 6231{
57871462 6232 int n;
2a014d73 6233 out = ndrc->translation_cache;
35775df7 6234 memset(invalid_code,1,sizeof(invalid_code));
dc990066 6235 memset(shadow,0,sizeof(shadow));
04714958 6236 hash_table_clear();
6237 mini_ht_clear();
57871462 6238 copy=shadow;
93c0345b 6239 expirep = EXPIRITY_OFFSET;
57871462 6240 pending_exception=0;
6241 literalcount=0;
57871462 6242 stop_after_jal=0;
9be4ba64 6243 inv_code_start=inv_code_end=~0;
7f94b097 6244 hack_addr=0;
39b71d9a 6245 f1_hack=0;
93c0345b 6246 for (n = 0; n < ARRAY_SIZE(blocks); n++)
6247 blocks_clear(&blocks[n]);
b7ad2f2c 6248 for (n = 0; n < ARRAY_SIZE(jumps); n++) {
6249 free(jumps[n]);
6250 jumps[n] = NULL;
6251 }
104df9d3 6252 stat_clear(stat_blocks);
6253 stat_clear(stat_links);
32631e6a 6254
42eb665e 6255 if (cycle_multiplier_old != Config.cycle_multiplier
6256 || new_dynarec_hacks_old != new_dynarec_hacks)
6257 {
6258 SysPrintf("ndrc config: mul=%d, ha=%x, pex=%d\n",
6259 get_cycle_multiplier(), new_dynarec_hacks, Config.PreciseExceptions);
6260 }
d5aeda23 6261 cycle_multiplier_old = Config.cycle_multiplier;
32631e6a 6262 new_dynarec_hacks_old = new_dynarec_hacks;
dc990066 6263}
6264
919981d0 6265void new_dynarec_init(void)
dc990066 6266{
66ea165f 6267 SysPrintf("Init new dynarec, ndrc size %x\n", (int)sizeof(*ndrc));
1e212a25 6268
0aeb0cb9 6269#ifdef _3DS
6270 check_rosalina();
6271#endif
2a014d73 6272#ifdef BASE_ADDR_DYNAMIC
1e212a25 6273 #ifdef VITA
0aeb0cb9 6274 sceBlock = getVMBlock(); //sceKernelAllocMemBlockForVM("code", sizeof(*ndrc));
66ea165f 6275 if (sceBlock <= 0)
6276 SysPrintf("sceKernelAllocMemBlockForVM failed: %x\n", sceBlock);
2a014d73 6277 int ret = sceKernelGetMemBlockBase(sceBlock, (void **)&ndrc);
1e212a25 6278 if (ret < 0)
66ea165f 6279 SysPrintf("sceKernelGetMemBlockBase failed: %x\n", ret);
0aeb0cb9 6280 sceKernelOpenVMDomain();
6281 sceClibPrintf("translation_cache = 0x%08lx\n ", (long)ndrc->translation_cache);
6282 #elif defined(_MSC_VER)
6283 ndrc = VirtualAlloc(NULL, sizeof(*ndrc), MEM_COMMIT | MEM_RESERVE,
6284 PAGE_EXECUTE_READWRITE);
3039c914 6285 #elif defined(HAVE_LIBNX)
6286 Result rc = jitCreate(&g_jit, sizeof(*ndrc));
6287 if (R_FAILED(rc))
6288 SysPrintf("jitCreate failed: %08x\n", rc);
6289 SysPrintf("jitCreate: RX: %p RW: %p type: %d\n", g_jit.rx_addr, g_jit.rw_addr, g_jit.type);
d9e2b173 6290 jitTransitionToWritable(&g_jit);
3039c914 6291 ndrc = g_jit.rx_addr;
6292 ndrc_write_ofs = (char *)g_jit.rw_addr - (char *)ndrc;
d9e2b173 6293 memset(NDRC_WRITE_OFFSET(&ndrc->tramp), 0, sizeof(ndrc->tramp));
1e212a25 6294 #else
2a014d73 6295 uintptr_t desired_addr = 0;
3039c914 6296 int prot = PROT_READ | PROT_WRITE | PROT_EXEC;
6297 int flags = MAP_PRIVATE | MAP_ANONYMOUS;
6298 int fd = -1;
2a014d73 6299 #ifdef __ELF__
6300 extern char _end;
6301 desired_addr = ((uintptr_t)&_end + 0xffffff) & ~0xffffffl;
6302 #endif
d9e2b173 6303 #ifdef TC_WRITE_OFFSET
3039c914 6304 // mostly for testing
6305 fd = open("/dev/shm/pcsxr", O_CREAT | O_RDWR, 0600);
6306 ftruncate(fd, sizeof(*ndrc));
6307 void *mw = mmap(NULL, sizeof(*ndrc), PROT_READ | PROT_WRITE,
6308 (flags = MAP_SHARED), fd, 0);
6309 assert(mw != MAP_FAILED);
6310 prot = PROT_READ | PROT_EXEC;
6311 #endif
6312 ndrc = mmap((void *)desired_addr, sizeof(*ndrc), prot, flags, fd, 0);
2a014d73 6313 if (ndrc == MAP_FAILED) {
d848b60a 6314 SysPrintf("mmap() failed: %s\n", strerror(errno));
1e212a25 6315 abort();
d848b60a 6316 }
d9e2b173 6317 #ifdef TC_WRITE_OFFSET
3039c914 6318 ndrc_write_ofs = (char *)mw - (char *)ndrc;
6319 #endif
1e212a25 6320 #endif
6321#else
6322 #ifndef NO_WRITE_EXEC
bdeade46 6323 // not all systems allow execute in data segment by default
761fdd0a 6324 // size must be 4K aligned for 3DS?
6325 if (mprotect(ndrc, sizeof(*ndrc),
2a014d73 6326 PROT_READ | PROT_WRITE | PROT_EXEC) != 0)
d848b60a 6327 SysPrintf("mprotect() failed: %s\n", strerror(errno));
1e212a25 6328 #endif
dc990066 6329#endif
2a014d73 6330 out = ndrc->translation_cache;
dc990066 6331 new_dynarec_clear_full();
6332#ifdef HOST_IMM8
6333 // Copy this into local area so we don't have to put it in every literal pool
6334 invc_ptr=invalid_code;
6335#endif
57871462 6336 arch_init();
d848b60a 6337 new_dynarec_test();
33a1eda1 6338 ram_offset = (uintptr_t)psxM - 0x80000000;
b105cf4f 6339 if (ram_offset!=0)
c43b5311 6340 SysPrintf("warning: RAM is not directly mapped, performance will suffer\n");
398d6924 6341 SysPrintf("Mapped (RAM/scrp/ROM/LUTs/TC):\n");
6342 SysPrintf("%p/%p/%p/%p/%p\n", psxM, psxH, psxR, mem_rtab, out);
57871462 6343}
6344
919981d0 6345void new_dynarec_cleanup(void)
57871462 6346{
6347 int n;
2a014d73 6348#ifdef BASE_ADDR_DYNAMIC
1e212a25 6349 #ifdef VITA
66ea165f 6350 // sceBlock is managed by retroarch's bootstrap code
9c67c98f 6351 //sceKernelFreeMemBlock(sceBlock);
6352 //sceBlock = -1;
3039c914 6353 #elif defined(HAVE_LIBNX)
6354 jitClose(&g_jit);
6355 ndrc = NULL;
1e212a25 6356 #else
2a014d73 6357 if (munmap(ndrc, sizeof(*ndrc)) < 0)
1e212a25 6358 SysPrintf("munmap() failed\n");
3039c914 6359 ndrc = NULL;
bdeade46 6360 #endif
1e212a25 6361#endif
93c0345b 6362 for (n = 0; n < ARRAY_SIZE(blocks); n++)
6363 blocks_clear(&blocks[n]);
b7ad2f2c 6364 for (n = 0; n < ARRAY_SIZE(jumps); n++) {
6365 free(jumps[n]);
6366 jumps[n] = NULL;
6367 }
104df9d3 6368 stat_clear(stat_blocks);
6369 stat_clear(stat_links);
ece032e6 6370 new_dynarec_print_stats();
57871462 6371}
6372
03f55e6b 6373static u_int *get_source_start(u_int addr, u_int *limit)
57871462 6374{
33a1eda1 6375 if (addr < 0x00800000
6376 || (0x80000000 <= addr && addr < 0x80800000)
6377 || (0xa0000000 <= addr && addr < 0xa0800000))
a3203cf4 6378 {
03f55e6b 6379 // used for BIOS calls mostly?
33a1eda1 6380 *limit = (addr & 0xa0600000) + 0x00200000;
6381 return (u_int *)(psxM + (addr & 0x1fffff));
03f55e6b 6382 }
a5539d92 6383 else if (
03f55e6b 6384 /* (0x9fc00000 <= addr && addr < 0x9fc80000) ||*/
a5539d92 6385 (0xbfc00000 <= addr && addr < 0xbfc80000))
a3203cf4 6386 {
6387 // BIOS. The multiplier should be much higher as it's uncached 8bit mem,
d5aeda23 6388 // but timings in PCSX are too tied to the interpreter's 2-per-insn assumption
d62c125a 6389 if (!HACK_ENABLED(NDHACK_OVERRIDE_CYCLE_M))
24058131 6390 cycle_multiplier_active = 200;
a3203cf4 6391
03f55e6b 6392 *limit = (addr & 0xfff00000) | 0x80000;
01d26796 6393 return (u_int *)((u_char *)psxR + (addr&0x7ffff));
03f55e6b 6394 }
581335b0 6395 return NULL;
03f55e6b 6396}
6397
6398static u_int scan_for_ret(u_int addr)
6399{
6400 u_int limit = 0;
6401 u_int *mem;
6402
6403 mem = get_source_start(addr, &limit);
6404 if (mem == NULL)
6405 return addr;
6406
6407 if (limit > addr + 0x1000)
6408 limit = addr + 0x1000;
6409 for (; addr < limit; addr += 4, mem++) {
6410 if (*mem == 0x03e00008) // jr $ra
6411 return addr + 8;
57871462 6412 }
581335b0 6413 return addr;
03f55e6b 6414}
6415
6416struct savestate_block {
6417 uint32_t addr;
6418 uint32_t regflags;
6419};
6420
6421static int addr_cmp(const void *p1_, const void *p2_)
6422{
6423 const struct savestate_block *p1 = p1_, *p2 = p2_;
6424 return p1->addr - p2->addr;
6425}
6426
6427int new_dynarec_save_blocks(void *save, int size)
6428{
104df9d3 6429 struct savestate_block *sblocks = save;
6430 int maxcount = size / sizeof(sblocks[0]);
03f55e6b 6431 struct savestate_block tmp_blocks[1024];
104df9d3 6432 struct block_info *block;
03f55e6b 6433 int p, s, d, o, bcnt;
6434 u_int addr;
6435
6436 o = 0;
104df9d3 6437 for (p = 0; p < ARRAY_SIZE(blocks); p++) {
03f55e6b 6438 bcnt = 0;
104df9d3 6439 for (block = blocks[p]; block != NULL; block = block->next) {
6440 if (block->is_dirty)
6441 continue;
6442 tmp_blocks[bcnt].addr = block->start;
6443 tmp_blocks[bcnt].regflags = block->reg_sv_flags;
03f55e6b 6444 bcnt++;
6445 }
6446 if (bcnt < 1)
6447 continue;
6448 qsort(tmp_blocks, bcnt, sizeof(tmp_blocks[0]), addr_cmp);
6449
6450 addr = tmp_blocks[0].addr;
6451 for (s = d = 0; s < bcnt; s++) {
6452 if (tmp_blocks[s].addr < addr)
6453 continue;
6454 if (d == 0 || tmp_blocks[d-1].addr != tmp_blocks[s].addr)
6455 tmp_blocks[d++] = tmp_blocks[s];
6456 addr = scan_for_ret(tmp_blocks[s].addr);
6457 }
6458
6459 if (o + d > maxcount)
6460 d = maxcount - o;
104df9d3 6461 memcpy(&sblocks[o], tmp_blocks, d * sizeof(sblocks[0]));
03f55e6b 6462 o += d;
6463 }
6464
104df9d3 6465 return o * sizeof(sblocks[0]);
03f55e6b 6466}
6467
6468void new_dynarec_load_blocks(const void *save, int size)
6469{
104df9d3 6470 const struct savestate_block *sblocks = save;
6471 int count = size / sizeof(sblocks[0]);
6472 struct block_info *block;
03f55e6b 6473 u_int regs_save[32];
104df9d3 6474 u_int page;
03f55e6b 6475 uint32_t f;
6476 int i, b;
6477
104df9d3 6478 // restore clean blocks, if any
6479 for (page = 0, b = i = 0; page < ARRAY_SIZE(blocks); page++) {
6480 for (block = blocks[page]; block != NULL; block = block->next, b++) {
6481 if (!block->is_dirty)
6482 continue;
6483 assert(block->source && block->copy);
6484 if (memcmp(block->source, block->copy, block->len))
6485 continue;
6486
6487 // see try_restore_block
6488 block->is_dirty = 0;
6489 mark_invalid_code(block->start, block->len, 0);
6490 i++;
6491 }
6492 }
6493 inv_debug("load_blocks: %d/%d clean blocks\n", i, b);
03f55e6b 6494
6495 // change GPRs for speculation to at least partially work..
6496 memcpy(regs_save, &psxRegs.GPR, sizeof(regs_save));
6497 for (i = 1; i < 32; i++)
6498 psxRegs.GPR.r[i] = 0x80000000;
6499
6500 for (b = 0; b < count; b++) {
104df9d3 6501 for (f = sblocks[b].regflags, i = 0; f; f >>= 1, i++) {
03f55e6b 6502 if (f & 1)
6503 psxRegs.GPR.r[i] = 0x1f800000;
6504 }
6505
104df9d3 6506 ndrc_get_addr_ht(sblocks[b].addr);
03f55e6b 6507
104df9d3 6508 for (f = sblocks[b].regflags, i = 0; f; f >>= 1, i++) {
03f55e6b 6509 if (f & 1)
6510 psxRegs.GPR.r[i] = 0x80000000;
6511 }
6512 }
6513
6514 memcpy(&psxRegs.GPR, regs_save, sizeof(regs_save));
6515}
6516
ece032e6 6517void new_dynarec_print_stats(void)
6518{
6519#ifdef STAT_PRINT
104df9d3 6520 printf("cc %3d,%3d,%3d lu%6d,%3d,%3d c%3d inv%3d,%3d tc_offs %zu b %u,%u\n",
ece032e6 6521 stat_bc_pre, stat_bc_direct, stat_bc_restore,
104df9d3 6522 stat_ht_lookups, stat_jump_in_lookups, stat_restore_tries,
6523 stat_restore_compares, stat_inv_addr_calls, stat_inv_hits,
6524 out - ndrc->translation_cache, stat_blocks, stat_links);
ece032e6 6525 stat_bc_direct = stat_bc_pre = stat_bc_restore =
104df9d3 6526 stat_ht_lookups = stat_jump_in_lookups = stat_restore_tries =
6527 stat_restore_compares = stat_inv_addr_calls = stat_inv_hits = 0;
ece032e6 6528#endif
6529}
6530
de74f599 6531static void force_intcall(int i)
6532{
6533 memset(&dops[i], 0, sizeof(dops[i]));
6534 dops[i].itype = INTCALL;
6535 dops[i].rs1 = CCREG;
6536 dops[i].is_exception = 1;
6537 cinfo[i].ba = -1;
6538}
6539
7f94b097 6540static int apply_hacks(void)
24058131 6541{
6542 int i;
6543 if (HACK_ENABLED(NDHACK_NO_COMPAT_HACKS))
7f94b097 6544 return 0;
24058131 6545 /* special hack(s) */
6546 for (i = 0; i < slen - 4; i++)
6547 {
6548 // lui a4, 0xf200; jal <rcnt_read>; addu a0, 2; slti v0, 28224
6549 if (source[i] == 0x3c04f200 && dops[i+1].itype == UJUMP
6550 && source[i+2] == 0x34840002 && dops[i+3].opcode == 0x0a
277718fa 6551 && cinfo[i+3].imm == 0x6e40 && dops[i+3].rs1 == 2)
24058131 6552 {
6553 SysPrintf("PE2 hack @%08x\n", start + (i+3)*4);
6554 dops[i + 3].itype = NOP;
6555 }
6556 }
6557 i = slen;
6558 if (i > 10 && source[i-1] == 0 && source[i-2] == 0x03e00008
6559 && source[i-4] == 0x8fbf0018 && source[i-6] == 0x00c0f809
6560 && dops[i-7].itype == STORE)
6561 {
6562 i = i-8;
6563 if (dops[i].itype == IMM16)
6564 i--;
6565 // swl r2, 15(r6); swr r2, 12(r6); sw r6, *; jalr r6
6566 if (dops[i].itype == STORELR && dops[i].rs1 == 6
6567 && dops[i-1].itype == STORELR && dops[i-1].rs1 == 6)
6568 {
7f94b097 6569 SysPrintf("F1 hack from %08x, old dst %08x\n", start, hack_addr);
6570 f1_hack = 1;
6571 return 1;
24058131 6572 }
6573 }
de74f599 6574 if (Config.HLE)
6575 {
6576 if (start <= psxRegs.biosBranchCheck && psxRegs.biosBranchCheck < start + i*4)
6577 {
6578 i = (psxRegs.biosBranchCheck - start) / 4u + 23;
6579 if (dops[i].is_jump && !dops[i+1].bt)
6580 {
6581 force_intcall(i);
6582 dops[i+1].is_ds = 0;
6583 }
6584 }
6585 }
7f94b097 6586 return 0;
24058131 6587}
6588
25427adf 6589static int is_ld_use_hazard(const struct decoded_insn *op_ld,
6590 const struct decoded_insn *op)
03f55e6b 6591{
25427adf 6592 if (op_ld->rt1 == 0 || (op_ld->rt1 != op->rs1 && op_ld->rt1 != op->rs2))
6593 return 0;
6594 if (op_ld->itype == LOADLR && op->itype == LOADLR)
6595 return op_ld->rt1 == op_ld->rs1;
6596 return op->itype != CJUMP && op->itype != SJUMP;
de6dbc52 6597}
57871462 6598
de6dbc52 6599static void disassemble_one(int i, u_int src)
6600{
6601 unsigned int type, op, op2, op3;
a22ccd6a 6602 enum ls_width_type ls_type = LS_32;
7ebfcedf 6603 memset(&dops[i], 0, sizeof(dops[i]));
277718fa 6604 memset(&cinfo[i], 0, sizeof(cinfo[i]));
6605 cinfo[i].ba = -1;
6606 cinfo[i].addr = -1;
de6dbc52 6607 dops[i].opcode = op = src >> 26;
277718fa 6608 op2 = 0;
a5cd72d0 6609 type = INTCALL;
6610 set_mnemonic(i, "???");
57871462 6611 switch(op)
6612 {
a5cd72d0 6613 case 0x00: set_mnemonic(i, "special");
de6dbc52 6614 op2 = src & 0x3f;
57871462 6615 switch(op2)
6616 {
53dc27f6 6617 case 0x00: set_mnemonic(i, "SLL"); type=SHIFTIMM; break;
6618 case 0x02: set_mnemonic(i, "SRL"); type=SHIFTIMM; break;
6619 case 0x03: set_mnemonic(i, "SRA"); type=SHIFTIMM; break;
6620 case 0x04: set_mnemonic(i, "SLLV"); type=SHIFT; break;
6621 case 0x06: set_mnemonic(i, "SRLV"); type=SHIFT; break;
6622 case 0x07: set_mnemonic(i, "SRAV"); type=SHIFT; break;
6623 case 0x08: set_mnemonic(i, "JR"); type=RJUMP; break;
6624 case 0x09: set_mnemonic(i, "JALR"); type=RJUMP; break;
6625 case 0x0C: set_mnemonic(i, "SYSCALL"); type=SYSCALL; break;
6626 case 0x0D: set_mnemonic(i, "BREAK"); type=SYSCALL; break;
53dc27f6 6627 case 0x10: set_mnemonic(i, "MFHI"); type=MOV; break;
6628 case 0x11: set_mnemonic(i, "MTHI"); type=MOV; break;
6629 case 0x12: set_mnemonic(i, "MFLO"); type=MOV; break;
6630 case 0x13: set_mnemonic(i, "MTLO"); type=MOV; break;
6631 case 0x18: set_mnemonic(i, "MULT"); type=MULTDIV; break;
6632 case 0x19: set_mnemonic(i, "MULTU"); type=MULTDIV; break;
6633 case 0x1A: set_mnemonic(i, "DIV"); type=MULTDIV; break;
6634 case 0x1B: set_mnemonic(i, "DIVU"); type=MULTDIV; break;
6635 case 0x20: set_mnemonic(i, "ADD"); type=ALU; break;
6636 case 0x21: set_mnemonic(i, "ADDU"); type=ALU; break;
6637 case 0x22: set_mnemonic(i, "SUB"); type=ALU; break;
6638 case 0x23: set_mnemonic(i, "SUBU"); type=ALU; break;
6639 case 0x24: set_mnemonic(i, "AND"); type=ALU; break;
6640 case 0x25: set_mnemonic(i, "OR"); type=ALU; break;
6641 case 0x26: set_mnemonic(i, "XOR"); type=ALU; break;
6642 case 0x27: set_mnemonic(i, "NOR"); type=ALU; break;
6643 case 0x2A: set_mnemonic(i, "SLT"); type=ALU; break;
6644 case 0x2B: set_mnemonic(i, "SLTU"); type=ALU; break;
57871462 6645 }
6646 break;
a5cd72d0 6647 case 0x01: set_mnemonic(i, "regimm");
6648 type = SJUMP;
de6dbc52 6649 op2 = (src >> 16) & 0x1f;
57871462 6650 switch(op2)
6651 {
a5cd72d0 6652 case 0x10: set_mnemonic(i, "BLTZAL"); break;
6653 case 0x11: set_mnemonic(i, "BGEZAL"); break;
6654 default:
6655 if (op2 & 1)
6656 set_mnemonic(i, "BGEZ");
6657 else
6658 set_mnemonic(i, "BLTZ");
57871462 6659 }
6660 break;
53dc27f6 6661 case 0x02: set_mnemonic(i, "J"); type=UJUMP; break;
6662 case 0x03: set_mnemonic(i, "JAL"); type=UJUMP; break;
6663 case 0x04: set_mnemonic(i, "BEQ"); type=CJUMP; break;
6664 case 0x05: set_mnemonic(i, "BNE"); type=CJUMP; break;
6665 case 0x06: set_mnemonic(i, "BLEZ"); type=CJUMP; break;
6666 case 0x07: set_mnemonic(i, "BGTZ"); type=CJUMP; break;
6667 case 0x08: set_mnemonic(i, "ADDI"); type=IMM16; break;
6668 case 0x09: set_mnemonic(i, "ADDIU"); type=IMM16; break;
6669 case 0x0A: set_mnemonic(i, "SLTI"); type=IMM16; break;
6670 case 0x0B: set_mnemonic(i, "SLTIU"); type=IMM16; break;
6671 case 0x0C: set_mnemonic(i, "ANDI"); type=IMM16; break;
6672 case 0x0D: set_mnemonic(i, "ORI"); type=IMM16; break;
6673 case 0x0E: set_mnemonic(i, "XORI"); type=IMM16; break;
6674 case 0x0F: set_mnemonic(i, "LUI"); type=IMM16; break;
a5cd72d0 6675 case 0x10: set_mnemonic(i, "COP0");
de6dbc52 6676 op2 = (src >> 21) & 0x1f;
a5cd72d0 6677 if (op2 & 0x10) {
de6dbc52 6678 op3 = src & 0x1f;
a5cd72d0 6679 switch (op3)
6680 {
6681 case 0x01: case 0x02: case 0x06: case 0x08: type = INTCALL; break;
6682 case 0x10: set_mnemonic(i, "RFE"); type=RFE; break;
6683 default: type = OTHER; break;
6684 }
6685 break;
6686 }
57871462 6687 switch(op2)
6688 {
a5cd72d0 6689 u32 rd;
6690 case 0x00:
6691 set_mnemonic(i, "MFC0");
de6dbc52 6692 rd = (src >> 11) & 0x1F;
a5cd72d0 6693 if (!(0x00000417u & (1u << rd)))
6694 type = COP0;
6695 break;
53dc27f6 6696 case 0x04: set_mnemonic(i, "MTC0"); type=COP0; break;
a5cd72d0 6697 case 0x02:
6698 case 0x06: type = INTCALL; break;
6699 default: type = OTHER; break;
57871462 6700 }
6701 break;
a5cd72d0 6702 case 0x11: set_mnemonic(i, "COP1");
de6dbc52 6703 op2 = (src >> 21) & 0x1f;
57871462 6704 break;
a5cd72d0 6705 case 0x12: set_mnemonic(i, "COP2");
de6dbc52 6706 op2 = (src >> 21) & 0x1f;
a5cd72d0 6707 if (op2 & 0x10) {
6708 type = OTHER;
de6dbc52 6709 if (gte_handlers[src & 0x3f] != NULL) {
53dc27f6 6710#ifdef DISASM
de6dbc52 6711 if (gte_regnames[src & 0x3f] != NULL)
6712 strcpy(insn[i], gte_regnames[src & 0x3f]);
bedfea38 6713 else
de6dbc52 6714 snprintf(insn[i], sizeof(insn[i]), "COP2 %x", src & 0x3f);
53dc27f6 6715#endif
a5cd72d0 6716 type = C2OP;
c7abc864 6717 }
6718 }
6719 else switch(op2)
b9b61529 6720 {
53dc27f6 6721 case 0x00: set_mnemonic(i, "MFC2"); type=COP2; break;
6722 case 0x02: set_mnemonic(i, "CFC2"); type=COP2; break;
6723 case 0x04: set_mnemonic(i, "MTC2"); type=COP2; break;
6724 case 0x06: set_mnemonic(i, "CTC2"); type=COP2; break;
b9b61529 6725 }
6726 break;
a5cd72d0 6727 case 0x13: set_mnemonic(i, "COP3");
de6dbc52 6728 op2 = (src >> 21) & 0x1f;
a5cd72d0 6729 break;
f9e9616e 6730 case 0x20: set_mnemonic(i, "LB"); type=LOAD; ls_type = LS_8; break;
6731 case 0x21: set_mnemonic(i, "LH"); type=LOAD; ls_type = LS_16; break;
6732 case 0x22: set_mnemonic(i, "LWL"); type=LOADLR; ls_type = LS_LR; break;
6733 case 0x23: set_mnemonic(i, "LW"); type=LOAD; ls_type = LS_32; break;
6734 case 0x24: set_mnemonic(i, "LBU"); type=LOAD; ls_type = LS_8; break;
6735 case 0x25: set_mnemonic(i, "LHU"); type=LOAD; ls_type = LS_16; break;
6736 case 0x26: set_mnemonic(i, "LWR"); type=LOADLR; ls_type = LS_LR; break;
6737 case 0x28: set_mnemonic(i, "SB"); type=STORE; ls_type = LS_8; break;
6738 case 0x29: set_mnemonic(i, "SH"); type=STORE; ls_type = LS_16; break;
6739 case 0x2A: set_mnemonic(i, "SWL"); type=STORELR; ls_type = LS_LR; break;
6740 case 0x2B: set_mnemonic(i, "SW"); type=STORE; ls_type = LS_32; break;
6741 case 0x2E: set_mnemonic(i, "SWR"); type=STORELR; ls_type = LS_LR; break;
6742 case 0x32: set_mnemonic(i, "LWC2"); type=C2LS; ls_type = LS_32; break;
6743 case 0x3A: set_mnemonic(i, "SWC2"); type=C2LS; ls_type = LS_32; break;
a5cd72d0 6744 case 0x3B:
de6dbc52 6745 if (Config.HLE && (src & 0x03ffffff) < ARRAY_SIZE(psxHLEt)) {
a5cd72d0 6746 set_mnemonic(i, "HLECALL");
6747 type = HLECALL;
6748 }
6749 break;
6750 default:
90ae6d4e 6751 break;
57871462 6752 }
a5cd72d0 6753 if (type == INTCALL)
de6dbc52 6754 SysPrintf("NI %08x @%08x (%08x)\n", src, start + i*4, start);
f9e9616e 6755 dops[i].itype = type;
6756 dops[i].opcode2 = op2;
6757 dops[i].ls_type = ls_type;
57871462 6758 /* Get registers/immediates */
53dc27f6 6759 dops[i].use_lt1=0;
bedfea38 6760 gte_rs[i]=gte_rt[i]=0;
a5cd72d0 6761 dops[i].rs1 = 0;
6762 dops[i].rs2 = 0;
6763 dops[i].rt1 = 0;
6764 dops[i].rt2 = 0;
57871462 6765 switch(type) {
6766 case LOAD:
de6dbc52 6767 dops[i].rs1 = (src >> 21) & 0x1f;
6768 dops[i].rt1 = (src >> 16) & 0x1f;
6769 cinfo[i].imm = (short)src;
57871462 6770 break;
6771 case STORE:
6772 case STORELR:
de6dbc52 6773 dops[i].rs1 = (src >> 21) & 0x1f;
6774 dops[i].rs2 = (src >> 16) & 0x1f;
6775 cinfo[i].imm = (short)src;
57871462 6776 break;
6777 case LOADLR:
6778 // LWL/LWR only load part of the register,
6779 // therefore the target register must be treated as a source too
de6dbc52 6780 dops[i].rs1 = (src >> 21) & 0x1f;
6781 dops[i].rs2 = (src >> 16) & 0x1f;
6782 dops[i].rt1 = (src >> 16) & 0x1f;
6783 cinfo[i].imm = (short)src;
57871462 6784 break;
6785 case IMM16:
cf95b4f0 6786 if (op==0x0f) dops[i].rs1=0; // LUI instruction has no source register
de6dbc52 6787 else dops[i].rs1 = (src >> 21) & 0x1f;
6788 dops[i].rs2 = 0;
6789 dops[i].rt1 = (src >> 16) & 0x1f;
57871462 6790 if(op>=0x0c&&op<=0x0e) { // ANDI/ORI/XORI
de6dbc52 6791 cinfo[i].imm = (unsigned short)src;
57871462 6792 }else{
de6dbc52 6793 cinfo[i].imm = (short)src;
57871462 6794 }
57871462 6795 break;
6796 case UJUMP:
57871462 6797 // The JAL instruction writes to r31.
6798 if (op&1) {
cf95b4f0 6799 dops[i].rt1=31;
57871462 6800 }
cf95b4f0 6801 dops[i].rs2=CCREG;
57871462 6802 break;
6803 case RJUMP:
de6dbc52 6804 dops[i].rs1 = (src >> 21) & 0x1f;
5067f341 6805 // The JALR instruction writes to rd.
57871462 6806 if (op2&1) {
de6dbc52 6807 dops[i].rt1 = (src >> 11) & 0x1f;
57871462 6808 }
cf95b4f0 6809 dops[i].rs2=CCREG;
57871462 6810 break;
6811 case CJUMP:
de6dbc52 6812 dops[i].rs1 = (src >> 21) & 0x1f;
6813 dops[i].rs2 = (src >> 16) & 0x1f;
57871462 6814 if(op&2) { // BGTZ/BLEZ
cf95b4f0 6815 dops[i].rs2=0;
57871462 6816 }
57871462 6817 break;
6818 case SJUMP:
de6dbc52 6819 dops[i].rs1 = (src >> 21) & 0x1f;
6820 dops[i].rs2 = CCREG;
a5cd72d0 6821 if (op2 == 0x10 || op2 == 0x11) { // BxxAL
6822 dops[i].rt1 = 31;
57871462 6823 // NOTE: If the branch is not taken, r31 is still overwritten
6824 }
57871462 6825 break;
57871462 6826 case ALU:
de6dbc52 6827 dops[i].rs1=(src>>21)&0x1f; // source
6828 dops[i].rs2=(src>>16)&0x1f; // subtract amount
6829 dops[i].rt1=(src>>11)&0x1f; // destination
57871462 6830 break;
6831 case MULTDIV:
de6dbc52 6832 dops[i].rs1=(src>>21)&0x1f; // source
6833 dops[i].rs2=(src>>16)&0x1f; // divisor
cf95b4f0 6834 dops[i].rt1=HIREG;
6835 dops[i].rt2=LOREG;
57871462 6836 break;
6837 case MOV:
cf95b4f0 6838 if(op2==0x10) dops[i].rs1=HIREG; // MFHI
6839 if(op2==0x11) dops[i].rt1=HIREG; // MTHI
6840 if(op2==0x12) dops[i].rs1=LOREG; // MFLO
6841 if(op2==0x13) dops[i].rt1=LOREG; // MTLO
de6dbc52 6842 if((op2&0x1d)==0x10) dops[i].rt1=(src>>11)&0x1f; // MFxx
6843 if((op2&0x1d)==0x11) dops[i].rs1=(src>>21)&0x1f; // MTxx
57871462 6844 break;
6845 case SHIFT:
de6dbc52 6846 dops[i].rs1=(src>>16)&0x1f; // target of shift
6847 dops[i].rs2=(src>>21)&0x1f; // shift amount
6848 dops[i].rt1=(src>>11)&0x1f; // destination
57871462 6849 break;
6850 case SHIFTIMM:
de6dbc52 6851 dops[i].rs1=(src>>16)&0x1f;
cf95b4f0 6852 dops[i].rs2=0;
de6dbc52 6853 dops[i].rt1=(src>>11)&0x1f;
6854 cinfo[i].imm=(src>>6)&0x1f;
57871462 6855 break;
6856 case COP0:
de6dbc52 6857 if(op2==0) dops[i].rt1=(src>>16)&0x1F; // MFC0
6858 if(op2==4) dops[i].rs1=(src>>16)&0x1F; // MTC0
6859 if(op2==4&&((src>>11)&0x1e)==12) dops[i].rs2=CCREG;
57871462 6860 break;
bedfea38 6861 case COP2:
de6dbc52 6862 if(op2<3) dops[i].rt1=(src>>16)&0x1F; // MFC2/CFC2
6863 if(op2>3) dops[i].rs1=(src>>16)&0x1F; // MTC2/CTC2
6864 int gr=(src>>11)&0x1F;
bedfea38 6865 switch(op2)
6866 {
6867 case 0x00: gte_rs[i]=1ll<<gr; break; // MFC2
6868 case 0x04: gte_rt[i]=1ll<<gr; break; // MTC2
0ff8c62c 6869 case 0x02: gte_rs[i]=1ll<<(gr+32); break; // CFC2
bedfea38 6870 case 0x06: gte_rt[i]=1ll<<(gr+32); break; // CTC2
6871 }
6872 break;
b9b61529 6873 case C2LS:
de6dbc52 6874 dops[i].rs1=(src>>21)&0x1F;
6875 cinfo[i].imm=(short)src;
6876 if(op==0x32) gte_rt[i]=1ll<<((src>>16)&0x1F); // LWC2
6877 else gte_rs[i]=1ll<<((src>>16)&0x1F); // SWC2
bedfea38 6878 break;
6879 case C2OP:
de6dbc52 6880 gte_rs[i]=gte_reg_reads[src&0x3f];
6881 gte_rt[i]=gte_reg_writes[src&0x3f];
2167bef6 6882 gte_rt[i]|=1ll<<63; // every op changes flags
de6dbc52 6883 if((src&0x3f)==GTE_MVMVA) {
6884 int v = (src >> 15) & 3;
587a5b1c 6885 gte_rs[i]&=~0xe3fll;
6886 if(v==3) gte_rs[i]|=0xe00ll;
6887 else gte_rs[i]|=3ll<<(v*2);
6888 }
b9b61529 6889 break;
57871462 6890 case SYSCALL:
7139f3c8 6891 case HLECALL:
1e973cb0 6892 case INTCALL:
cf95b4f0 6893 dops[i].rs1=CCREG;
57871462 6894 break;
6895 default:
a5cd72d0 6896 break;
57871462 6897 }
de6dbc52 6898}
6899
6900static noinline void pass1_disassemble(u_int pagelimit)
6901{
6902 int i, j, done = 0, ni_count = 0;
f9e9616e 6903 int ds_next = 0;
de6dbc52 6904
6905 for (i = 0; !done; i++)
6906 {
6907 int force_j_to_interpreter = 0;
6908 unsigned int type, op, op2;
6909
6910 disassemble_one(i, source[i]);
f9e9616e 6911 dops[i].is_ds = ds_next; ds_next = 0;
de6dbc52 6912 type = dops[i].itype;
6913 op = dops[i].opcode;
6914 op2 = dops[i].opcode2;
6915
57871462 6916 /* Calculate branch target addresses */
6917 if(type==UJUMP)
277718fa 6918 cinfo[i].ba=((start+i*4+4)&0xF0000000)|(((unsigned int)source[i]<<6)>>4);
cf95b4f0 6919 else if(type==CJUMP&&dops[i].rs1==dops[i].rs2&&(op&1))
277718fa 6920 cinfo[i].ba=start+i*4+8; // Ignore never taken branch
cf95b4f0 6921 else if(type==SJUMP&&dops[i].rs1==0&&!(op2&1))
277718fa 6922 cinfo[i].ba=start+i*4+8; // Ignore never taken branch
ad49de89 6923 else if(type==CJUMP||type==SJUMP)
277718fa 6924 cinfo[i].ba=start+i*4+4+((signed int)((unsigned int)source[i]<<16)>>14);
4919de1e 6925
6926 /* simplify always (not)taken branches */
cf95b4f0 6927 if (type == CJUMP && dops[i].rs1 == dops[i].rs2) {
6928 dops[i].rs1 = dops[i].rs2 = 0;
4919de1e 6929 if (!(op & 1)) {
cf95b4f0 6930 dops[i].itype = type = UJUMP;
6931 dops[i].rs2 = CCREG;
4919de1e 6932 }
6933 }
cf95b4f0 6934 else if (type == SJUMP && dops[i].rs1 == 0 && (op2 & 1))
6935 dops[i].itype = type = UJUMP;
4919de1e 6936
277718fa 6937 dops[i].is_jump = type == RJUMP || type == UJUMP || type == CJUMP || type == SJUMP;
6938 dops[i].is_ujump = type == RJUMP || type == UJUMP;
6939 dops[i].is_load = type == LOAD || type == LOADLR || op == 0x32; // LWC2
a5cd72d0 6940 dops[i].is_delay_load = (dops[i].is_load || (source[i] & 0xf3d00000) == 0x40000000); // MFC/CFC
277718fa 6941 dops[i].is_store = type == STORE || type == STORELR || op == 0x3a; // SWC2
6942 dops[i].is_exception = type == SYSCALL || type == HLECALL || type == INTCALL;
6943 dops[i].may_except = dops[i].is_exception || (type == ALU && (op2 == 0x20 || op2 == 0x22)) || op == 8;
f9e9616e 6944 ds_next = dops[i].is_jump;
277718fa 6945
6946 if (((op & 0x37) == 0x21 || op == 0x25) // LH/SH/LHU
6947 && ((cinfo[i].imm & 1) || Config.PreciseExceptions))
6948 dops[i].may_except = 1;
6949 if (((op & 0x37) == 0x23 || (op & 0x37) == 0x32) // LW/SW/LWC2/SWC2
6950 && ((cinfo[i].imm & 3) || Config.PreciseExceptions))
6951 dops[i].may_except = 1;
fe807a8a 6952
a5cd72d0 6953 /* rare messy cases to just pass over to the interpreter */
fe807a8a 6954 if (i > 0 && dops[i-1].is_jump) {
ecca05e3 6955 j = i - 1;
3e535354 6956 // branch in delay slot?
fe807a8a 6957 if (dops[i].is_jump) {
3e535354 6958 // don't handle first branch and call interpreter if it's hit
a5cd72d0 6959 SysPrintf("branch in DS @%08x (%08x)\n", start + i*4, start);
ecca05e3 6960 force_j_to_interpreter = 1;
3e535354 6961 }
de6dbc52 6962 // load delay detection through a branch
a5cd72d0 6963 else if (dops[i].is_delay_load && dops[i].rt1 != 0) {
de6dbc52 6964 const struct decoded_insn *dop = NULL;
6965 int t = -1;
6966 if (cinfo[i-1].ba != -1) {
6967 t = (cinfo[i-1].ba - start) / 4;
6968 if (t < 0 || t > i) {
6969 u_int limit = 0;
6970 u_int *mem = get_source_start(cinfo[i-1].ba, &limit);
6971 if (mem != NULL) {
6972 disassemble_one(MAXBLOCK - 1, mem[0]);
6973 dop = &dops[MAXBLOCK - 1];
6974 }
6975 }
6976 else
6977 dop = &dops[t];
6978 }
25427adf 6979 if ((dop && is_ld_use_hazard(&dops[i], dop))
de6dbc52 6980 || (!dop && Config.PreciseExceptions)) {
3e535354 6981 // jump target wants DS result - potential load delay effect
a5cd72d0 6982 SysPrintf("load delay in DS @%08x (%08x)\n", start + i*4, start);
ecca05e3 6983 force_j_to_interpreter = 1;
de6dbc52 6984 if (0 <= t && t < i)
6985 dops[t + 1].bt = 1; // expected return from interpreter
3e535354 6986 }
cf95b4f0 6987 else if(i>=2&&dops[i-2].rt1==2&&dops[i].rt1==2&&dops[i].rs1!=2&&dops[i].rs2!=2&&dops[i-1].rs1!=2&&dops[i-1].rs2!=2&&
fe807a8a 6988 !(i>=3&&dops[i-3].is_jump)) {
3e535354 6989 // v0 overwrite like this is a sign of trouble, bail out
4149788d 6990 SysPrintf("v0 overwrite @%08x (%08x)\n", start + i*4, start);
ecca05e3 6991 force_j_to_interpreter = 1;
3e535354 6992 }
6993 }
a5cd72d0 6994 }
de6dbc52 6995 else if (i > 0 && dops[i-1].is_delay_load
25427adf 6996 && is_ld_use_hazard(&dops[i-1], &dops[i])
de6dbc52 6997 && (i < 2 || !dops[i-2].is_ujump)) {
a5cd72d0 6998 SysPrintf("load delay @%08x (%08x)\n", start + i*4, start);
ecca05e3 6999 for (j = i - 1; j > 0 && dops[j-1].is_delay_load; j--)
7000 if (dops[j-1].rt1 != dops[i-1].rt1)
7001 break;
7002 force_j_to_interpreter = 1;
a5cd72d0 7003 }
ecca05e3 7004 if (force_j_to_interpreter) {
de6dbc52 7005 force_intcall(j);
a5cd72d0 7006 done = 2;
ecca05e3 7007 i = j; // don't compile the problematic branch/load/etc
3e535354 7008 }
de6dbc52 7009 if (dops[i].is_exception && i > 0 && dops[i-1].is_jump) {
7010 SysPrintf("exception in DS @%08x (%08x)\n", start + i*4, start);
7011 i--;
7012 force_intcall(i);
7013 done = 2;
7014 }
7015 if (i >= 2 && (source[i-2] & 0xffe0f800) == 0x40806000) // MTC0 $12
7016 dops[i].bt = 1;
7017 if (i >= 1 && (source[i-1] & 0xffe0f800) == 0x40806800) // MTC0 $13
7018 dops[i].bt = 1;
4919de1e 7019
3e535354 7020 /* Is this the end of the block? */
fe807a8a 7021 if (i > 0 && dops[i-1].is_ujump) {
0787af86 7022 if (dops[i-1].rt1 == 0) { // not jal
277718fa 7023 int found_bbranch = 0, t = (cinfo[i-1].ba - start) / 4;
0787af86 7024 if ((u_int)(t - i) < 64 && start + (t+64)*4 < pagelimit) {
7025 // scan for a branch back to i+1
7026 for (j = t; j < t + 64; j++) {
7027 int tmpop = source[j] >> 26;
7028 if (tmpop == 1 || ((tmpop & ~3) == 4)) {
7029 int t2 = j + 1 + (int)(signed short)source[j];
7030 if (t2 == i + 1) {
7031 //printf("blk expand %08x<-%08x\n", start + (i+1)*4, start + j*4);
7032 found_bbranch = 1;
7033 break;
7034 }
7035 }
7036 }
7037 }
7038 if (!found_bbranch)
7039 done = 2;
57871462 7040 }
7041 else {
7042 if(stop_after_jal) done=1;
7043 // Stop on BREAK
7044 if((source[i+1]&0xfc00003f)==0x0d) done=1;
7045 }
7046 // Don't recompile stuff that's already compiled
7047 if(check_addr(start+i*4+4)) done=1;
7048 // Don't get too close to the limit
d3201e39 7049 if (i > MAXBLOCK - 64)
7050 done = 1;
57871462 7051 }
a5cd72d0 7052 if (dops[i].itype == HLECALL)
dc4fa8bc 7053 done = 1;
a5cd72d0 7054 else if (dops[i].itype == INTCALL)
dc4fa8bc 7055 done = 2;
a5cd72d0 7056 else if (dops[i].is_exception)
d1150cd6 7057 done = stop_after_jal ? 1 : 2;
7058 if (done == 2) {
1e973cb0 7059 // Does the block continue due to a branch?
7060 for(j=i-1;j>=0;j--)
7061 {
277718fa 7062 if(cinfo[j].ba==start+i*4) done=j=0; // Branch into delay slot
7063 if(cinfo[j].ba==start+i*4+4) done=j=0;
7064 if(cinfo[j].ba==start+i*4+8) done=j=0;
1e973cb0 7065 }
7066 }
75dec299 7067 //assert(i<MAXBLOCK-1);
57871462 7068 if(start+i*4==pagelimit-4) done=1;
7069 assert(start+i*4<pagelimit);
d3201e39 7070 if (i == MAXBLOCK - 2)
7071 done = 1;
57871462 7072 // Stop if we're compiling junk
a5cd72d0 7073 if (dops[i].itype == INTCALL && (++ni_count > 8 || dops[i].opcode == 0x11)) {
57871462 7074 done=stop_after_jal=1;
c43b5311 7075 SysPrintf("Disabled speculative precompilation\n");
57871462 7076 }
7077 }
4bdc30ab 7078 while (i > 0 && dops[i-1].is_jump)
7079 i--;
7080 assert(i > 0);
7081 assert(!dops[i-1].is_jump);
7082 slen = i;
4149788d 7083}
7084
7085// Basic liveness analysis for MIPS registers
7086static noinline void pass2_unneeded_regs(int istart,int iend,int r)
7087{
7088 int i;
7089 uint64_t u,gte_u,b,gte_b;
7090 uint64_t temp_u,temp_gte_u=0;
7091 uint64_t gte_u_unknown=0;
7092 if (HACK_ENABLED(NDHACK_GTE_UNNEEDED))
7093 gte_u_unknown=~0ll;
7094 if(iend==slen-1) {
7095 u=1;
7096 gte_u=gte_u_unknown;
7097 }else{
7098 //u=unneeded_reg[iend+1];
7099 u=1;
7100 gte_u=gte_unneeded[iend+1];
7101 }
7102
7103 for (i=iend;i>=istart;i--)
7104 {
7105 //printf("unneeded registers i=%d (%d,%d) r=%d\n",i,istart,iend,r);
7106 if(dops[i].is_jump)
7107 {
7108 // If subroutine call, flag return address as a possible branch target
7109 if(dops[i].rt1==31 && i<slen-2) dops[i+2].bt=1;
7110
277718fa 7111 if(cinfo[i].ba<start || cinfo[i].ba>=(start+slen*4))
4149788d 7112 {
7113 // Branch out of this block, flush all regs
7114 u=1;
7115 gte_u=gte_u_unknown;
7116 branch_unneeded_reg[i]=u;
7117 // Merge in delay slot
7118 u|=(1LL<<dops[i+1].rt1)|(1LL<<dops[i+1].rt2);
7119 u&=~((1LL<<dops[i+1].rs1)|(1LL<<dops[i+1].rs2));
7120 u|=1;
7121 gte_u|=gte_rt[i+1];
7122 gte_u&=~gte_rs[i+1];
7123 }
7124 else
7125 {
7126 // Internal branch, flag target
277718fa 7127 dops[(cinfo[i].ba-start)>>2].bt=1;
7128 if(cinfo[i].ba<=start+i*4) {
4149788d 7129 // Backward branch
7130 if(dops[i].is_ujump)
7131 {
7132 // Unconditional branch
7133 temp_u=1;
7134 temp_gte_u=0;
7135 } else {
7136 // Conditional branch (not taken case)
7137 temp_u=unneeded_reg[i+2];
7138 temp_gte_u&=gte_unneeded[i+2];
7139 }
7140 // Merge in delay slot
7141 temp_u|=(1LL<<dops[i+1].rt1)|(1LL<<dops[i+1].rt2);
7142 temp_u&=~((1LL<<dops[i+1].rs1)|(1LL<<dops[i+1].rs2));
7143 temp_u|=1;
7144 temp_gte_u|=gte_rt[i+1];
7145 temp_gte_u&=~gte_rs[i+1];
7146 temp_u|=(1LL<<dops[i].rt1)|(1LL<<dops[i].rt2);
7147 temp_u&=~((1LL<<dops[i].rs1)|(1LL<<dops[i].rs2));
7148 temp_u|=1;
7149 temp_gte_u|=gte_rt[i];
7150 temp_gte_u&=~gte_rs[i];
7151 unneeded_reg[i]=temp_u;
7152 gte_unneeded[i]=temp_gte_u;
7153 // Only go three levels deep. This recursion can take an
7154 // excessive amount of time if there are a lot of nested loops.
7155 if(r<2) {
277718fa 7156 pass2_unneeded_regs((cinfo[i].ba-start)>>2,i-1,r+1);
4149788d 7157 }else{
277718fa 7158 unneeded_reg[(cinfo[i].ba-start)>>2]=1;
7159 gte_unneeded[(cinfo[i].ba-start)>>2]=gte_u_unknown;
4149788d 7160 }
7161 } /*else*/ if(1) {
7162 if (dops[i].is_ujump)
7163 {
7164 // Unconditional branch
277718fa 7165 u=unneeded_reg[(cinfo[i].ba-start)>>2];
7166 gte_u=gte_unneeded[(cinfo[i].ba-start)>>2];
4149788d 7167 branch_unneeded_reg[i]=u;
7168 // Merge in delay slot
7169 u|=(1LL<<dops[i+1].rt1)|(1LL<<dops[i+1].rt2);
7170 u&=~((1LL<<dops[i+1].rs1)|(1LL<<dops[i+1].rs2));
7171 u|=1;
7172 gte_u|=gte_rt[i+1];
7173 gte_u&=~gte_rs[i+1];
7174 } else {
7175 // Conditional branch
277718fa 7176 b=unneeded_reg[(cinfo[i].ba-start)>>2];
7177 gte_b=gte_unneeded[(cinfo[i].ba-start)>>2];
4149788d 7178 branch_unneeded_reg[i]=b;
7179 // Branch delay slot
7180 b|=(1LL<<dops[i+1].rt1)|(1LL<<dops[i+1].rt2);
7181 b&=~((1LL<<dops[i+1].rs1)|(1LL<<dops[i+1].rs2));
7182 b|=1;
7183 gte_b|=gte_rt[i+1];
7184 gte_b&=~gte_rs[i+1];
7185 u&=b;
7186 gte_u&=gte_b;
7187 if(i<slen-1) {
7188 branch_unneeded_reg[i]&=unneeded_reg[i+2];
7189 } else {
7190 branch_unneeded_reg[i]=1;
7191 }
7192 }
7193 }
7194 }
7195 }
4149788d 7196 //u=1; // DEBUG
7197 // Written registers are unneeded
7198 u|=1LL<<dops[i].rt1;
7199 u|=1LL<<dops[i].rt2;
7200 gte_u|=gte_rt[i];
7201 // Accessed registers are needed
7202 u&=~(1LL<<dops[i].rs1);
7203 u&=~(1LL<<dops[i].rs2);
7204 gte_u&=~gte_rs[i];
7205 if(gte_rs[i]&&dops[i].rt1&&(unneeded_reg[i+1]&(1ll<<dops[i].rt1)))
7206 gte_u|=gte_rs[i]&gte_unneeded[i+1]; // MFC2/CFC2 to dead register, unneeded
90f98e7c 7207 if (dops[i].may_except || dops[i].itype == RFE)
7208 {
7209 // SYSCALL instruction, etc or conditional exception
7210 u=1;
7211 }
4149788d 7212 // Source-target dependencies
7213 // R0 is always unneeded
7214 u|=1;
7215 // Save it
7216 unneeded_reg[i]=u;
7217 gte_unneeded[i]=gte_u;
7218 /*
7219 printf("ur (%d,%d) %x: ",istart,iend,start+i*4);
7220 printf("U:");
7221 int r;
7222 for(r=1;r<=CCREG;r++) {
7223 if((unneeded_reg[i]>>r)&1) {
7224 if(r==HIREG) printf(" HI");
7225 else if(r==LOREG) printf(" LO");
7226 else printf(" r%d",r);
7227 }
7228 }
7229 printf("\n");
7230 */
7231 }
7232}
57871462 7233
f9e9616e 7234static noinline void pass2a_unneeded_other(void)
7235{
7236 int i, j;
7237 for (i = 0; i < slen; i++)
7238 {
7239 // remove redundant alignment checks
7240 if (dops[i].may_except && (dops[i].is_load || dops[i].is_store)
7241 && dops[i].rt1 != dops[i].rs1 && !dops[i].is_ds)
7242 {
7243 int base = dops[i].rs1, lsb = cinfo[i].imm, ls_type = dops[i].ls_type;
7244 int mask = ls_type == LS_32 ? 3 : 1;
7245 lsb &= mask;
7246 for (j = i + 1; j < slen; j++) {
7247 if (dops[j].bt || dops[j].is_jump)
7248 break;
7249 if ((dops[j].is_load || dops[j].is_store) && dops[j].rs1 == base
7250 && dops[j].ls_type == ls_type && (cinfo[j].imm & mask) == lsb)
7251 dops[j].may_except = 0;
7252 if (dops[j].rt1 == base)
7253 break;
7254 }
7255 }
7256 }
7257}
7258
4149788d 7259static noinline void pass3_register_alloc(u_int addr)
7260{
57871462 7261 struct regstat current; // Current register allocations/status
6cc8d23c 7262 clear_all_regs(current.regmap_entry);
57871462 7263 clear_all_regs(current.regmap);
6cc8d23c 7264 current.wasdirty = current.dirty = 0;
7265 current.u = unneeded_reg[0];
7266 alloc_reg(&current, 0, CCREG);
7267 dirty_reg(&current, CCREG);
7268 current.wasconst = 0;
7269 current.isconst = 0;
7270 current.loadedconst = 0;
90f98e7c 7271 current.noevict = 0;
9b495f6e 7272 //current.waswritten = 0;
57871462 7273 int ds=0;
7274 int cc=0;
4149788d 7275 int hr;
7276 int i, j;
6ebf4adf 7277
4149788d 7278 if (addr & 1) {
57871462 7279 // First instruction is delay slot
7280 cc=-1;
cf95b4f0 7281 dops[1].bt=1;
57871462 7282 ds=1;
7283 unneeded_reg[0]=1;
57871462 7284 }
9f51b4b9 7285
57871462 7286 for(i=0;i<slen;i++)
7287 {
cf95b4f0 7288 if(dops[i].bt)
57871462 7289 {
57871462 7290 for(hr=0;hr<HOST_REGS;hr++)
7291 {
7292 // Is this really necessary?
7293 if(current.regmap[hr]==0) current.regmap[hr]=-1;
7294 }
7295 current.isconst=0;
9b495f6e 7296 //current.waswritten=0;
57871462 7297 }
24385cae 7298
57871462 7299 memcpy(regmap_pre[i],current.regmap,sizeof(current.regmap));
7300 regs[i].wasconst=current.isconst;
57871462 7301 regs[i].wasdirty=current.dirty;
6cc8d23c 7302 regs[i].dirty=0;
7303 regs[i].u=0;
7304 regs[i].isconst=0;
8575a877 7305 regs[i].loadedconst=0;
fe807a8a 7306 if (!dops[i].is_jump) {
57871462 7307 if(i+1<slen) {
cf95b4f0 7308 current.u=unneeded_reg[i+1]&~((1LL<<dops[i].rs1)|(1LL<<dops[i].rs2));
57871462 7309 current.u|=1;
57871462 7310 } else {
7311 current.u=1;
57871462 7312 }
7313 } else {
7314 if(i+1<slen) {
cf95b4f0 7315 current.u=branch_unneeded_reg[i]&~((1LL<<dops[i+1].rs1)|(1LL<<dops[i+1].rs2));
7316 current.u&=~((1LL<<dops[i].rs1)|(1LL<<dops[i].rs2));
57871462 7317 current.u|=1;
7ebfcedf 7318 } else {
7319 SysPrintf("oops, branch at end of block with no delay slot @%08x\n", start + i*4);
7320 abort();
7321 }
57871462 7322 }
f9e9616e 7323 assert(dops[i].is_ds == ds);
57871462 7324 if(ds) {
7325 ds=0; // Skip delay slot, already allocated as part of branch
7326 // ...but we need to alloc it in case something jumps here
7327 if(i+1<slen) {
7328 current.u=branch_unneeded_reg[i-1]&unneeded_reg[i+1];
57871462 7329 }else{
7330 current.u=branch_unneeded_reg[i-1];
57871462 7331 }
cf95b4f0 7332 current.u&=~((1LL<<dops[i].rs1)|(1LL<<dops[i].rs2));
57871462 7333 current.u|=1;
57871462 7334 struct regstat temp;
7335 memcpy(&temp,&current,sizeof(current));
7336 temp.wasdirty=temp.dirty;
57871462 7337 // TODO: Take into account unconditional branches, as below
7338 delayslot_alloc(&temp,i);
7339 memcpy(regs[i].regmap,temp.regmap,sizeof(temp.regmap));
7340 regs[i].wasdirty=temp.wasdirty;
57871462 7341 regs[i].dirty=temp.dirty;
57871462 7342 regs[i].isconst=0;
7343 regs[i].wasconst=0;
7344 current.isconst=0;
7345 // Create entry (branch target) regmap
7346 for(hr=0;hr<HOST_REGS;hr++)
7347 {
7348 int r=temp.regmap[hr];
7349 if(r>=0) {
7350 if(r!=regmap_pre[i][hr]) {
7351 regs[i].regmap_entry[hr]=-1;
7352 }
7353 else
7354 {
7c3a5182 7355 assert(r < 64);
57871462 7356 if((current.u>>r)&1) {
7357 regs[i].regmap_entry[hr]=-1;
7358 regs[i].regmap[hr]=-1;
7359 //Don't clear regs in the delay slot as the branch might need them
7360 //current.regmap[hr]=-1;
7361 }else
7362 regs[i].regmap_entry[hr]=r;
57871462 7363 }
7364 } else {
7365 // First instruction expects CCREG to be allocated
9f51b4b9 7366 if(i==0&&hr==HOST_CCREG)
57871462 7367 regs[i].regmap_entry[hr]=CCREG;
7368 else
7369 regs[i].regmap_entry[hr]=-1;
7370 }
7371 }
7372 }
7373 else { // Not delay slot
90f98e7c 7374 current.noevict = 0;
cf95b4f0 7375 switch(dops[i].itype) {
57871462 7376 case UJUMP:
7377 //current.isconst=0; // DEBUG
7378 //current.wasconst=0; // DEBUG
7379 //regs[i].wasconst=0; // DEBUG
cf95b4f0 7380 clear_const(&current,dops[i].rt1);
57871462 7381 alloc_cc(&current,i);
7382 dirty_reg(&current,CCREG);
cf95b4f0 7383 if (dops[i].rt1==31) {
57871462 7384 alloc_reg(&current,i,31);
7385 dirty_reg(&current,31);
cf95b4f0 7386 //assert(dops[i+1].rs1!=31&&dops[i+1].rs2!=31);
7387 //assert(dops[i+1].rt1!=dops[i].rt1);
57871462 7388 #ifdef REG_PREFETCH
7389 alloc_reg(&current,i,PTEMP);
7390 #endif
57871462 7391 }
cf95b4f0 7392 dops[i].ooo=1;
269bb29a 7393 delayslot_alloc(&current,i+1);
57871462 7394 //current.isconst=0; // DEBUG
7395 ds=1;
57871462 7396 break;
7397 case RJUMP:
7398 //current.isconst=0;
7399 //current.wasconst=0;
7400 //regs[i].wasconst=0;
cf95b4f0 7401 clear_const(&current,dops[i].rs1);
7402 clear_const(&current,dops[i].rt1);
57871462 7403 alloc_cc(&current,i);
7404 dirty_reg(&current,CCREG);
4919de1e 7405 if (!ds_writes_rjump_rs(i)) {
cf95b4f0 7406 alloc_reg(&current,i,dops[i].rs1);
7407 if (dops[i].rt1!=0) {
7408 alloc_reg(&current,i,dops[i].rt1);
7409 dirty_reg(&current,dops[i].rt1);
57871462 7410 #ifdef REG_PREFETCH
7411 alloc_reg(&current,i,PTEMP);
7412 #endif
7413 }
7414 #ifdef USE_MINI_HT
cf95b4f0 7415 if(dops[i].rs1==31) { // JALR
57871462 7416 alloc_reg(&current,i,RHASH);
57871462 7417 alloc_reg(&current,i,RHTBL);
57871462 7418 }
7419 #endif
7420 delayslot_alloc(&current,i+1);
7421 } else {
7422 // The delay slot overwrites our source register,
7423 // allocate a temporary register to hold the old value.
7424 current.isconst=0;
7425 current.wasconst=0;
7426 regs[i].wasconst=0;
7427 delayslot_alloc(&current,i+1);
7428 current.isconst=0;
7429 alloc_reg(&current,i,RTEMP);
7430 }
7431 //current.isconst=0; // DEBUG
cf95b4f0 7432 dops[i].ooo=1;
57871462 7433 ds=1;
7434 break;
7435 case CJUMP:
7436 //current.isconst=0;
7437 //current.wasconst=0;
7438 //regs[i].wasconst=0;
cf95b4f0 7439 clear_const(&current,dops[i].rs1);
7440 clear_const(&current,dops[i].rs2);
7441 if((dops[i].opcode&0x3E)==4) // BEQ/BNE
57871462 7442 {
7443 alloc_cc(&current,i);
7444 dirty_reg(&current,CCREG);
cf95b4f0 7445 if(dops[i].rs1) alloc_reg(&current,i,dops[i].rs1);
7446 if(dops[i].rs2) alloc_reg(&current,i,dops[i].rs2);
7447 if((dops[i].rs1&&(dops[i].rs1==dops[i+1].rt1||dops[i].rs1==dops[i+1].rt2))||
7448 (dops[i].rs2&&(dops[i].rs2==dops[i+1].rt1||dops[i].rs2==dops[i+1].rt2))) {
57871462 7449 // The delay slot overwrites one of our conditions.
7450 // Allocate the branch condition registers instead.
57871462 7451 current.isconst=0;
7452 current.wasconst=0;
7453 regs[i].wasconst=0;
cf95b4f0 7454 if(dops[i].rs1) alloc_reg(&current,i,dops[i].rs1);
7455 if(dops[i].rs2) alloc_reg(&current,i,dops[i].rs2);
57871462 7456 }
e1190b87 7457 else
7458 {
cf95b4f0 7459 dops[i].ooo=1;
e1190b87 7460 delayslot_alloc(&current,i+1);
7461 }
57871462 7462 }
7463 else
cf95b4f0 7464 if((dops[i].opcode&0x3E)==6) // BLEZ/BGTZ
57871462 7465 {
7466 alloc_cc(&current,i);
7467 dirty_reg(&current,CCREG);
cf95b4f0 7468 alloc_reg(&current,i,dops[i].rs1);
7469 if(dops[i].rs1&&(dops[i].rs1==dops[i+1].rt1||dops[i].rs1==dops[i+1].rt2)) {
57871462 7470 // The delay slot overwrites one of our conditions.
7471 // Allocate the branch condition registers instead.
57871462 7472 current.isconst=0;
7473 current.wasconst=0;
7474 regs[i].wasconst=0;
cf95b4f0 7475 if(dops[i].rs1) alloc_reg(&current,i,dops[i].rs1);
57871462 7476 }
e1190b87 7477 else
7478 {
cf95b4f0 7479 dops[i].ooo=1;
e1190b87 7480 delayslot_alloc(&current,i+1);
7481 }
57871462 7482 }
7483 else
7484 // Don't alloc the delay slot yet because we might not execute it
cf95b4f0 7485 if((dops[i].opcode&0x3E)==0x14) // BEQL/BNEL
57871462 7486 {
7487 current.isconst=0;
7488 current.wasconst=0;
7489 regs[i].wasconst=0;
7490 alloc_cc(&current,i);
7491 dirty_reg(&current,CCREG);
cf95b4f0 7492 alloc_reg(&current,i,dops[i].rs1);
7493 alloc_reg(&current,i,dops[i].rs2);
57871462 7494 }
7495 else
cf95b4f0 7496 if((dops[i].opcode&0x3E)==0x16) // BLEZL/BGTZL
57871462 7497 {
7498 current.isconst=0;
7499 current.wasconst=0;
7500 regs[i].wasconst=0;
7501 alloc_cc(&current,i);
7502 dirty_reg(&current,CCREG);
cf95b4f0 7503 alloc_reg(&current,i,dops[i].rs1);
57871462 7504 }
7505 ds=1;
7506 //current.isconst=0;
7507 break;
7508 case SJUMP:
cf95b4f0 7509 clear_const(&current,dops[i].rs1);
7510 clear_const(&current,dops[i].rt1);
57871462 7511 {
7512 alloc_cc(&current,i);
7513 dirty_reg(&current,CCREG);
cf95b4f0 7514 alloc_reg(&current,i,dops[i].rs1);
ecca05e3 7515 if (dops[i].rt1 == 31) { // BLTZAL/BGEZAL
57871462 7516 alloc_reg(&current,i,31);
7517 dirty_reg(&current,31);
57871462 7518 }
ecca05e3 7519 if ((dops[i].rs1 &&
7520 (dops[i].rs1==dops[i+1].rt1||dops[i].rs1==dops[i+1].rt2)) // The delay slot overwrites the branch condition.
7521 ||(dops[i].rt1 == 31 && dops[i].rs1 == 31) // overwrites it's own condition
cf95b4f0 7522 ||(dops[i].rt1==31&&(dops[i+1].rs1==31||dops[i+1].rs2==31||dops[i+1].rt1==31||dops[i+1].rt2==31))) { // DS touches $ra
57871462 7523 // Allocate the branch condition registers instead.
57871462 7524 current.isconst=0;
7525 current.wasconst=0;
7526 regs[i].wasconst=0;
cf95b4f0 7527 if(dops[i].rs1) alloc_reg(&current,i,dops[i].rs1);
57871462 7528 }
e1190b87 7529 else
7530 {
cf95b4f0 7531 dops[i].ooo=1;
e1190b87 7532 delayslot_alloc(&current,i+1);
7533 }
57871462 7534 }
57871462 7535 ds=1;
7536 //current.isconst=0;
7537 break;
57871462 7538 case IMM16:
7539 imm16_alloc(&current,i);
7540 break;
7541 case LOAD:
7542 case LOADLR:
7543 load_alloc(&current,i);
7544 break;
7545 case STORE:
7546 case STORELR:
7547 store_alloc(&current,i);
7548 break;
7549 case ALU:
7550 alu_alloc(&current,i);
7551 break;
7552 case SHIFT:
7553 shift_alloc(&current,i);
7554 break;
7555 case MULTDIV:
7556 multdiv_alloc(&current,i);
7557 break;
7558 case SHIFTIMM:
7559 shiftimm_alloc(&current,i);
7560 break;
7561 case MOV:
7562 mov_alloc(&current,i);
7563 break;
7564 case COP0:
7565 cop0_alloc(&current,i);
7566 break;
a5cd72d0 7567 case RFE:
7568 rfe_alloc(&current,i);
81dbbf4c 7569 break;
b9b61529 7570 case COP2:
81dbbf4c 7571 cop2_alloc(&current,i);
57871462 7572 break;
b9b61529 7573 case C2LS:
7574 c2ls_alloc(&current,i);
7575 break;
7576 case C2OP:
7577 c2op_alloc(&current,i);
7578 break;
57871462 7579 case SYSCALL:
7139f3c8 7580 case HLECALL:
1e973cb0 7581 case INTCALL:
57871462 7582 syscall_alloc(&current,i);
7583 break;
57871462 7584 }
9f51b4b9 7585
57871462 7586 // Create entry (branch target) regmap
7587 for(hr=0;hr<HOST_REGS;hr++)
7588 {
581335b0 7589 int r,or;
57871462 7590 r=current.regmap[hr];
7591 if(r>=0) {
7592 if(r!=regmap_pre[i][hr]) {
7593 // TODO: delay slot (?)
7594 or=get_reg(regmap_pre[i],r); // Get old mapping for this register
9de8a0c3 7595 if(or<0||r>=TEMPREG){
57871462 7596 regs[i].regmap_entry[hr]=-1;
7597 }
7598 else
7599 {
7600 // Just move it to a different register
7601 regs[i].regmap_entry[hr]=r;
7602 // If it was dirty before, it's still dirty
9de8a0c3 7603 if((regs[i].wasdirty>>or)&1) dirty_reg(&current,r);
57871462 7604 }
7605 }
7606 else
7607 {
7608 // Unneeded
7609 if(r==0){
7610 regs[i].regmap_entry[hr]=0;
7611 }
7612 else
7c3a5182 7613 {
7614 assert(r<64);
57871462 7615 if((current.u>>r)&1) {
7616 regs[i].regmap_entry[hr]=-1;
7617 //regs[i].regmap[hr]=-1;
7618 current.regmap[hr]=-1;
7619 }else
7620 regs[i].regmap_entry[hr]=r;
7621 }
57871462 7622 }
7623 } else {
7624 // Branches expect CCREG to be allocated at the target
9f51b4b9 7625 if(regmap_pre[i][hr]==CCREG)
57871462 7626 regs[i].regmap_entry[hr]=CCREG;
7627 else
7628 regs[i].regmap_entry[hr]=-1;
7629 }
7630 }
7631 memcpy(regs[i].regmap,current.regmap,sizeof(current.regmap));
7632 }
27727b63 7633
9b495f6e 7634#if 0 // see do_store_smc_check()
277718fa 7635 if(i>0&&(dops[i-1].itype==STORE||dops[i-1].itype==STORELR||(dops[i-1].itype==C2LS&&dops[i-1].opcode==0x3a))&&(u_int)cinfo[i-1].imm<0x800)
cf95b4f0 7636 current.waswritten|=1<<dops[i-1].rs1;
7637 current.waswritten&=~(1<<dops[i].rt1);
7638 current.waswritten&=~(1<<dops[i].rt2);
277718fa 7639 if((dops[i].itype==STORE||dops[i].itype==STORELR||(dops[i].itype==C2LS&&dops[i].opcode==0x3a))&&(u_int)cinfo[i].imm>=0x800)
cf95b4f0 7640 current.waswritten&=~(1<<dops[i].rs1);
9b495f6e 7641#endif
27727b63 7642
57871462 7643 /* Branch post-alloc */
7644 if(i>0)
7645 {
57871462 7646 current.wasdirty=current.dirty;
cf95b4f0 7647 switch(dops[i-1].itype) {
57871462 7648 case UJUMP:
7649 memcpy(&branch_regs[i-1],&current,sizeof(current));
7650 branch_regs[i-1].isconst=0;
7651 branch_regs[i-1].wasconst=0;
cf95b4f0 7652 branch_regs[i-1].u=branch_unneeded_reg[i-1]&~((1LL<<dops[i-1].rs1)|(1LL<<dops[i-1].rs2));
57871462 7653 alloc_cc(&branch_regs[i-1],i-1);
7654 dirty_reg(&branch_regs[i-1],CCREG);
cf95b4f0 7655 if(dops[i-1].rt1==31) { // JAL
57871462 7656 alloc_reg(&branch_regs[i-1],i-1,31);
7657 dirty_reg(&branch_regs[i-1],31);
57871462 7658 }
7659 memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
40fca85b 7660 memcpy(constmap[i],constmap[i-1],sizeof(constmap[i]));
57871462 7661 break;
7662 case RJUMP:
7663 memcpy(&branch_regs[i-1],&current,sizeof(current));
7664 branch_regs[i-1].isconst=0;
7665 branch_regs[i-1].wasconst=0;
cf95b4f0 7666 branch_regs[i-1].u=branch_unneeded_reg[i-1]&~((1LL<<dops[i-1].rs1)|(1LL<<dops[i-1].rs2));
57871462 7667 alloc_cc(&branch_regs[i-1],i-1);
7668 dirty_reg(&branch_regs[i-1],CCREG);
cf95b4f0 7669 alloc_reg(&branch_regs[i-1],i-1,dops[i-1].rs1);
7670 if(dops[i-1].rt1!=0) { // JALR
7671 alloc_reg(&branch_regs[i-1],i-1,dops[i-1].rt1);
7672 dirty_reg(&branch_regs[i-1],dops[i-1].rt1);
57871462 7673 }
7674 #ifdef USE_MINI_HT
cf95b4f0 7675 if(dops[i-1].rs1==31) { // JALR
57871462 7676 alloc_reg(&branch_regs[i-1],i-1,RHASH);
57871462 7677 alloc_reg(&branch_regs[i-1],i-1,RHTBL);
57871462 7678 }
7679 #endif
7680 memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
40fca85b 7681 memcpy(constmap[i],constmap[i-1],sizeof(constmap[i]));
57871462 7682 break;
7683 case CJUMP:
cf95b4f0 7684 if((dops[i-1].opcode&0x3E)==4) // BEQ/BNE
57871462 7685 {
7686 alloc_cc(&current,i-1);
7687 dirty_reg(&current,CCREG);
cf95b4f0 7688 if((dops[i-1].rs1&&(dops[i-1].rs1==dops[i].rt1||dops[i-1].rs1==dops[i].rt2))||
7689 (dops[i-1].rs2&&(dops[i-1].rs2==dops[i].rt1||dops[i-1].rs2==dops[i].rt2))) {
57871462 7690 // The delay slot overwrote one of our conditions
7691 // Delay slot goes after the test (in order)
cf95b4f0 7692 current.u=branch_unneeded_reg[i-1]&~((1LL<<dops[i].rs1)|(1LL<<dops[i].rs2));
57871462 7693 current.u|=1;
57871462 7694 delayslot_alloc(&current,i);
7695 current.isconst=0;
7696 }
7697 else
7698 {
cf95b4f0 7699 current.u=branch_unneeded_reg[i-1]&~((1LL<<dops[i-1].rs1)|(1LL<<dops[i-1].rs2));
57871462 7700 // Alloc the branch condition registers
cf95b4f0 7701 if(dops[i-1].rs1) alloc_reg(&current,i-1,dops[i-1].rs1);
7702 if(dops[i-1].rs2) alloc_reg(&current,i-1,dops[i-1].rs2);
57871462 7703 }
7704 memcpy(&branch_regs[i-1],&current,sizeof(current));
7705 branch_regs[i-1].isconst=0;
7706 branch_regs[i-1].wasconst=0;
7707 memcpy(&branch_regs[i-1].regmap_entry,&current.regmap,sizeof(current.regmap));
40fca85b 7708 memcpy(constmap[i],constmap[i-1],sizeof(constmap[i]));
57871462 7709 }
7710 else
cf95b4f0 7711 if((dops[i-1].opcode&0x3E)==6) // BLEZ/BGTZ
57871462 7712 {
7713 alloc_cc(&current,i-1);
7714 dirty_reg(&current,CCREG);
cf95b4f0 7715 if(dops[i-1].rs1==dops[i].rt1||dops[i-1].rs1==dops[i].rt2) {
57871462 7716 // The delay slot overwrote the branch condition
7717 // Delay slot goes after the test (in order)
cf95b4f0 7718 current.u=branch_unneeded_reg[i-1]&~((1LL<<dops[i].rs1)|(1LL<<dops[i].rs2));
57871462 7719 current.u|=1;
57871462 7720 delayslot_alloc(&current,i);
7721 current.isconst=0;
7722 }
7723 else
7724 {
cf95b4f0 7725 current.u=branch_unneeded_reg[i-1]&~(1LL<<dops[i-1].rs1);
57871462 7726 // Alloc the branch condition register
cf95b4f0 7727 alloc_reg(&current,i-1,dops[i-1].rs1);
57871462 7728 }
7729 memcpy(&branch_regs[i-1],&current,sizeof(current));
7730 branch_regs[i-1].isconst=0;
7731 branch_regs[i-1].wasconst=0;
7732 memcpy(&branch_regs[i-1].regmap_entry,&current.regmap,sizeof(current.regmap));
40fca85b 7733 memcpy(constmap[i],constmap[i-1],sizeof(constmap[i]));
57871462 7734 }
57871462 7735 break;
7736 case SJUMP:
57871462 7737 {
7738 alloc_cc(&current,i-1);
7739 dirty_reg(&current,CCREG);
cf95b4f0 7740 if(dops[i-1].rs1==dops[i].rt1||dops[i-1].rs1==dops[i].rt2) {
57871462 7741 // The delay slot overwrote the branch condition
7742 // Delay slot goes after the test (in order)
cf95b4f0 7743 current.u=branch_unneeded_reg[i-1]&~((1LL<<dops[i].rs1)|(1LL<<dops[i].rs2));
57871462 7744 current.u|=1;
57871462 7745 delayslot_alloc(&current,i);
7746 current.isconst=0;
7747 }
7748 else
7749 {
cf95b4f0 7750 current.u=branch_unneeded_reg[i-1]&~(1LL<<dops[i-1].rs1);
57871462 7751 // Alloc the branch condition register
cf95b4f0 7752 alloc_reg(&current,i-1,dops[i-1].rs1);
57871462 7753 }
7754 memcpy(&branch_regs[i-1],&current,sizeof(current));
7755 branch_regs[i-1].isconst=0;
7756 branch_regs[i-1].wasconst=0;
7757 memcpy(&branch_regs[i-1].regmap_entry,&current.regmap,sizeof(current.regmap));
40fca85b 7758 memcpy(constmap[i],constmap[i-1],sizeof(constmap[i]));
57871462 7759 }
57871462 7760 break;
57871462 7761 }
7762
fe807a8a 7763 if (dops[i-1].is_ujump)
57871462 7764 {
cf95b4f0 7765 if(dops[i-1].rt1==31) // JAL/JALR
57871462 7766 {
7767 // Subroutine call will return here, don't alloc any registers
57871462 7768 current.dirty=0;
7769 clear_all_regs(current.regmap);
7770 alloc_reg(&current,i,CCREG);
7771 dirty_reg(&current,CCREG);
7772 }
7773 else if(i+1<slen)
7774 {
7775 // Internal branch will jump here, match registers to caller
57871462 7776 current.dirty=0;
7777 clear_all_regs(current.regmap);
7778 alloc_reg(&current,i,CCREG);
7779 dirty_reg(&current,CCREG);
7780 for(j=i-1;j>=0;j--)
7781 {
277718fa 7782 if(cinfo[j].ba==start+i*4+4) {
57871462 7783 memcpy(current.regmap,branch_regs[j].regmap,sizeof(current.regmap));
57871462 7784 current.dirty=branch_regs[j].dirty;
7785 break;
7786 }
7787 }
7788 while(j>=0) {
277718fa 7789 if(cinfo[j].ba==start+i*4+4) {
57871462 7790 for(hr=0;hr<HOST_REGS;hr++) {
7791 if(current.regmap[hr]!=branch_regs[j].regmap[hr]) {
7792 current.regmap[hr]=-1;
7793 }
57871462 7794 current.dirty&=branch_regs[j].dirty;
7795 }
7796 }
7797 j--;
7798 }
7799 }
7800 }
7801 }
7802
7803 // Count cycles in between branches
277718fa 7804 cinfo[i].ccadj = CLOCK_ADJUST(cc);
a5cd72d0 7805 if (i > 0 && (dops[i-1].is_jump || dops[i].is_exception))
57871462 7806 {
7807 cc=0;
7808 }
71e490c5 7809#if !defined(DRC_DBG)
cf95b4f0 7810 else if(dops[i].itype==C2OP&&gte_cycletab[source[i]&0x3f]>2)
054175e9 7811 {
81dbbf4c 7812 // this should really be removed since the real stalls have been implemented,
7813 // but doing so causes sizeable perf regression against the older version
7814 u_int gtec = gte_cycletab[source[i] & 0x3f];
32631e6a 7815 cc += HACK_ENABLED(NDHACK_NO_STALLS) ? gtec/2 : 2;
fb407447 7816 }
cf95b4f0 7817 else if(i>1&&dops[i].itype==STORE&&dops[i-1].itype==STORE&&dops[i-2].itype==STORE&&!dops[i].bt)
5fdcbb5a 7818 {
7819 cc+=4;
7820 }
cf95b4f0 7821 else if(dops[i].itype==C2LS)
fb407447 7822 {
81dbbf4c 7823 // same as with C2OP
32631e6a 7824 cc += HACK_ENABLED(NDHACK_NO_STALLS) ? 4 : 2;
fb407447 7825 }
7826#endif
57871462 7827 else
7828 {
7829 cc++;
7830 }
7831
cf95b4f0 7832 if(!dops[i].is_ds) {
57871462 7833 regs[i].dirty=current.dirty;
7834 regs[i].isconst=current.isconst;
40fca85b 7835 memcpy(constmap[i],current_constmap,sizeof(constmap[i]));
57871462 7836 }
7837 for(hr=0;hr<HOST_REGS;hr++) {
7838 if(hr!=EXCLUDE_REG&&regs[i].regmap[hr]>=0) {
7839 if(regmap_pre[i][hr]!=regs[i].regmap[hr]) {
7840 regs[i].wasconst&=~(1<<hr);
7841 }
7842 }
7843 }
9b495f6e 7844 //regs[i].waswritten=current.waswritten;
57871462 7845 }
4149788d 7846}
9f51b4b9 7847
4149788d 7848static noinline void pass4_cull_unused_regs(void)
7849{
53358c1d 7850 u_int last_needed_regs[4] = {0,0,0,0};
4149788d 7851 u_int nr=0;
7852 int i;
9f51b4b9 7853
57871462 7854 for (i=slen-1;i>=0;i--)
7855 {
7856 int hr;
53358c1d 7857 __builtin_prefetch(regs[i-2].regmap);
fe807a8a 7858 if(dops[i].is_jump)
57871462 7859 {
277718fa 7860 if(cinfo[i].ba<start || cinfo[i].ba>=(start+slen*4))
57871462 7861 {
7862 // Branch out of this block, don't need anything
7863 nr=0;
7864 }
7865 else
7866 {
7867 // Internal branch
7868 // Need whatever matches the target
7869 nr=0;
277718fa 7870 int t=(cinfo[i].ba-start)>>2;
57871462 7871 for(hr=0;hr<HOST_REGS;hr++)
7872 {
7873 if(regs[i].regmap_entry[hr]>=0) {
7874 if(regs[i].regmap_entry[hr]==regs[t].regmap_entry[hr]) nr|=1<<hr;
7875 }
7876 }
7877 }
7878 // Conditional branch may need registers for following instructions
fe807a8a 7879 if (!dops[i].is_ujump)
57871462 7880 {
7881 if(i<slen-2) {
53358c1d 7882 nr |= last_needed_regs[(i+2) & 3];
57871462 7883 for(hr=0;hr<HOST_REGS;hr++)
7884 {
7885 if(regmap_pre[i+2][hr]>=0&&get_reg(regs[i+2].regmap_entry,regmap_pre[i+2][hr])<0) nr&=~(1<<hr);
7886 //if((regmap_entry[i+2][hr])>=0) if(!((nr>>hr)&1)) printf("%x-bogus(%d=%d)\n",start+i*4,hr,regmap_entry[i+2][hr]);
7887 }
7888 }
7889 }
7890 // Don't need stuff which is overwritten
f5955059 7891 //if(regs[i].regmap[hr]!=regmap_pre[i][hr]) nr&=~(1<<hr);
7892 //if(regs[i].regmap[hr]<0) nr&=~(1<<hr);
57871462 7893 // Merge in delay slot
53358c1d 7894 if (dops[i+1].rt1) nr &= ~get_regm(regs[i].regmap, dops[i+1].rt1);
7895 if (dops[i+1].rt2) nr &= ~get_regm(regs[i].regmap, dops[i+1].rt2);
7896 nr |= get_regm(regmap_pre[i], dops[i+1].rs1);
7897 nr |= get_regm(regmap_pre[i], dops[i+1].rs2);
7898 nr |= get_regm(regs[i].regmap_entry, dops[i+1].rs1);
7899 nr |= get_regm(regs[i].regmap_entry, dops[i+1].rs2);
7900 if (ram_offset && (dops[i+1].is_load || dops[i+1].is_store)) {
7901 nr |= get_regm(regmap_pre[i], ROREG);
7902 nr |= get_regm(regs[i].regmap_entry, ROREG);
7903 }
7904 if (dops[i+1].is_store) {
7905 nr |= get_regm(regmap_pre[i], INVCP);
7906 nr |= get_regm(regs[i].regmap_entry, INVCP);
57871462 7907 }
7908 }
277718fa 7909 else if (dops[i].is_exception)
57871462 7910 {
277718fa 7911 // SYSCALL instruction, etc
57871462 7912 nr=0;
7913 }
7914 else // Non-branch
7915 {
7916 if(i<slen-1) {
7917 for(hr=0;hr<HOST_REGS;hr++) {
7918 if(regmap_pre[i+1][hr]>=0&&get_reg(regs[i+1].regmap_entry,regmap_pre[i+1][hr])<0) nr&=~(1<<hr);
7919 if(regs[i].regmap[hr]!=regmap_pre[i+1][hr]) nr&=~(1<<hr);
7920 if(regs[i].regmap[hr]!=regmap_pre[i][hr]) nr&=~(1<<hr);
7921 if(regs[i].regmap[hr]<0) nr&=~(1<<hr);
7922 }
7923 }
7924 }
53358c1d 7925 // Overwritten registers are not needed
7926 if (dops[i].rt1) nr &= ~get_regm(regs[i].regmap, dops[i].rt1);
7927 if (dops[i].rt2) nr &= ~get_regm(regs[i].regmap, dops[i].rt2);
7928 nr &= ~get_regm(regs[i].regmap, FTEMP);
7929 // Source registers are needed
7930 nr |= get_regm(regmap_pre[i], dops[i].rs1);
7931 nr |= get_regm(regmap_pre[i], dops[i].rs2);
7932 nr |= get_regm(regs[i].regmap_entry, dops[i].rs1);
7933 nr |= get_regm(regs[i].regmap_entry, dops[i].rs2);
7934 if (ram_offset && (dops[i].is_load || dops[i].is_store)) {
7935 nr |= get_regm(regmap_pre[i], ROREG);
7936 nr |= get_regm(regs[i].regmap_entry, ROREG);
7937 }
7938 if (dops[i].is_store) {
7939 nr |= get_regm(regmap_pre[i], INVCP);
7940 nr |= get_regm(regs[i].regmap_entry, INVCP);
7941 }
7942
7943 if (i > 0 && !dops[i].bt && regs[i].wasdirty)
57871462 7944 for(hr=0;hr<HOST_REGS;hr++)
7945 {
57871462 7946 // Don't store a register immediately after writing it,
7947 // may prevent dual-issue.
7948 // But do so if this is a branch target, otherwise we
7949 // might have to load the register before the branch.
53358c1d 7950 if((regs[i].wasdirty>>hr)&1) {
7c3a5182 7951 if((regmap_pre[i][hr]>0&&!((unneeded_reg[i]>>regmap_pre[i][hr])&1))) {
9de8a0c3 7952 if(dops[i-1].rt1==regmap_pre[i][hr]) nr|=1<<hr;
7953 if(dops[i-1].rt2==regmap_pre[i][hr]) nr|=1<<hr;
57871462 7954 }
7c3a5182 7955 if((regs[i].regmap_entry[hr]>0&&!((unneeded_reg[i]>>regs[i].regmap_entry[hr])&1))) {
9de8a0c3 7956 if(dops[i-1].rt1==regs[i].regmap_entry[hr]) nr|=1<<hr;
7957 if(dops[i-1].rt2==regs[i].regmap_entry[hr]) nr|=1<<hr;
57871462 7958 }
7959 }
7960 }
7961 // Cycle count is needed at branches. Assume it is needed at the target too.
de6dbc52 7962 if (i == 0 || dops[i].bt || dops[i].may_except || dops[i].itype == CJUMP) {
57871462 7963 if(regmap_pre[i][HOST_CCREG]==CCREG) nr|=1<<HOST_CCREG;
7964 if(regs[i].regmap_entry[HOST_CCREG]==CCREG) nr|=1<<HOST_CCREG;
7965 }
7966 // Save it
53358c1d 7967 last_needed_regs[i & 3] = nr;
9f51b4b9 7968
57871462 7969 // Deallocate unneeded registers
7970 for(hr=0;hr<HOST_REGS;hr++)
7971 {
7972 if(!((nr>>hr)&1)) {
7973 if(regs[i].regmap_entry[hr]!=CCREG) regs[i].regmap_entry[hr]=-1;
fe807a8a 7974 if(dops[i].is_jump)
57871462 7975 {
37387d8b 7976 int map1 = 0, map2 = 0, temp = 0; // or -1 ??
7977 if (dops[i+1].is_load || dops[i+1].is_store)
7978 map1 = ROREG;
7979 if (dops[i+1].is_store)
7980 map2 = INVCP;
7981 if(dops[i+1].itype==LOADLR || dops[i+1].itype==STORELR || dops[i+1].itype==C2LS)
7982 temp = FTEMP;
9de8a0c3 7983 if(regs[i].regmap[hr]!=dops[i].rs1 && regs[i].regmap[hr]!=dops[i].rs2 &&
7984 regs[i].regmap[hr]!=dops[i].rt1 && regs[i].regmap[hr]!=dops[i].rt2 &&
7985 regs[i].regmap[hr]!=dops[i+1].rt1 && regs[i].regmap[hr]!=dops[i+1].rt2 &&
cf95b4f0 7986 regs[i].regmap[hr]!=dops[i+1].rs1 && regs[i].regmap[hr]!=dops[i+1].rs2 &&
9de8a0c3 7987 regs[i].regmap[hr]!=temp && regs[i].regmap[hr]!=PTEMP &&
57871462 7988 regs[i].regmap[hr]!=RHASH && regs[i].regmap[hr]!=RHTBL &&
7989 regs[i].regmap[hr]!=RTEMP && regs[i].regmap[hr]!=CCREG &&
37387d8b 7990 regs[i].regmap[hr]!=map1 && regs[i].regmap[hr]!=map2)
57871462 7991 {
7992 regs[i].regmap[hr]=-1;
7993 regs[i].isconst&=~(1<<hr);
a550c61c 7994 regs[i].dirty&=~(1<<hr);
7995 regs[i+1].wasdirty&=~(1<<hr);
9de8a0c3 7996 if(branch_regs[i].regmap[hr]!=dops[i].rs1 && branch_regs[i].regmap[hr]!=dops[i].rs2 &&
7997 branch_regs[i].regmap[hr]!=dops[i].rt1 && branch_regs[i].regmap[hr]!=dops[i].rt2 &&
7998 branch_regs[i].regmap[hr]!=dops[i+1].rt1 && branch_regs[i].regmap[hr]!=dops[i+1].rt2 &&
cf95b4f0 7999 branch_regs[i].regmap[hr]!=dops[i+1].rs1 && branch_regs[i].regmap[hr]!=dops[i+1].rs2 &&
9de8a0c3 8000 branch_regs[i].regmap[hr]!=temp && branch_regs[i].regmap[hr]!=PTEMP &&
57871462 8001 branch_regs[i].regmap[hr]!=RHASH && branch_regs[i].regmap[hr]!=RHTBL &&
8002 branch_regs[i].regmap[hr]!=RTEMP && branch_regs[i].regmap[hr]!=CCREG &&
37387d8b 8003 branch_regs[i].regmap[hr]!=map1 && branch_regs[i].regmap[hr]!=map2)
57871462 8004 {
8005 branch_regs[i].regmap[hr]=-1;
8006 branch_regs[i].regmap_entry[hr]=-1;
fe807a8a 8007 if (!dops[i].is_ujump)
57871462 8008 {
fe807a8a 8009 if (i < slen-2) {
57871462 8010 regmap_pre[i+2][hr]=-1;
79c75f1b 8011 regs[i+2].wasconst&=~(1<<hr);
57871462 8012 }
8013 }
8014 }
8015 }
8016 }
8017 else
8018 {
8019 // Non-branch
8020 if(i>0)
8021 {
37387d8b 8022 int map1 = -1, map2 = -1, temp=-1;
8023 if (dops[i].is_load || dops[i].is_store)
8024 map1 = ROREG;
8025 if (dops[i].is_store)
8026 map2 = INVCP;
8027 if (dops[i].itype==LOADLR || dops[i].itype==STORELR || dops[i].itype==C2LS)
8028 temp = FTEMP;
9de8a0c3 8029 if(regs[i].regmap[hr]!=dops[i].rt1 && regs[i].regmap[hr]!=dops[i].rt2 &&
cf95b4f0 8030 regs[i].regmap[hr]!=dops[i].rs1 && regs[i].regmap[hr]!=dops[i].rs2 &&
9de8a0c3 8031 regs[i].regmap[hr]!=temp && regs[i].regmap[hr]!=map1 && regs[i].regmap[hr]!=map2 &&
4b1c7cd1 8032 //(dops[i].itype!=SPAN||regs[i].regmap[hr]!=CCREG)
8033 regs[i].regmap[hr] != CCREG)
57871462 8034 {
cf95b4f0 8035 if(i<slen-1&&!dops[i].is_ds) {
ad49de89 8036 assert(regs[i].regmap[hr]<64);
afec9d44 8037 if(regmap_pre[i+1][hr]!=-1 || regs[i].regmap[hr]>0)
57871462 8038 if(regmap_pre[i+1][hr]!=regs[i].regmap[hr])
57871462 8039 {
c43b5311 8040 SysPrintf("fail: %x (%d %d!=%d)\n",start+i*4,hr,regmap_pre[i+1][hr],regs[i].regmap[hr]);
57871462 8041 assert(regmap_pre[i+1][hr]==regs[i].regmap[hr]);
8042 }
8043 regmap_pre[i+1][hr]=-1;
8044 if(regs[i+1].regmap_entry[hr]==CCREG) regs[i+1].regmap_entry[hr]=-1;
79c75f1b 8045 regs[i+1].wasconst&=~(1<<hr);
57871462 8046 }
8047 regs[i].regmap[hr]=-1;
8048 regs[i].isconst&=~(1<<hr);
a550c61c 8049 regs[i].dirty&=~(1<<hr);
8050 regs[i+1].wasdirty&=~(1<<hr);
57871462 8051 }
8052 }
8053 }
3968e69e 8054 } // if needed
8055 } // for hr
57871462 8056 }
4149788d 8057}
9f51b4b9 8058
4149788d 8059// If a register is allocated during a loop, try to allocate it for the
8060// entire loop, if possible. This avoids loading/storing registers
8061// inside of the loop.
8062static noinline void pass5a_preallocate1(void)
8063{
8064 int i, j, hr;
57871462 8065 signed char f_regmap[HOST_REGS];
8066 clear_all_regs(f_regmap);
8067 for(i=0;i<slen-1;i++)
8068 {
cf95b4f0 8069 if(dops[i].itype==UJUMP||dops[i].itype==CJUMP||dops[i].itype==SJUMP)
57871462 8070 {
277718fa 8071 if(cinfo[i].ba>=start && cinfo[i].ba<(start+i*4))
cf95b4f0 8072 if(dops[i+1].itype==NOP||dops[i+1].itype==MOV||dops[i+1].itype==ALU
8073 ||dops[i+1].itype==SHIFTIMM||dops[i+1].itype==IMM16||dops[i+1].itype==LOAD
a5cd72d0 8074 ||dops[i+1].itype==STORE||dops[i+1].itype==STORELR
8075 ||dops[i+1].itype==SHIFT
cf95b4f0 8076 ||dops[i+1].itype==COP2||dops[i+1].itype==C2LS||dops[i+1].itype==C2OP)
57871462 8077 {
277718fa 8078 int t=(cinfo[i].ba-start)>>2;
fe807a8a 8079 if(t > 0 && !dops[t-1].is_jump) // loop_preload can't handle jumps into delay slots
cf95b4f0 8080 if(t<2||(dops[t-2].itype!=UJUMP&&dops[t-2].itype!=RJUMP)||dops[t-2].rt1!=31) // call/ret assumes no registers allocated
57871462 8081 for(hr=0;hr<HOST_REGS;hr++)
8082 {
7c3a5182 8083 if(regs[i].regmap[hr]>=0) {
b372a952 8084 if(f_regmap[hr]!=regs[i].regmap[hr]) {
8085 // dealloc old register
8086 int n;
8087 for(n=0;n<HOST_REGS;n++)
8088 {
8089 if(f_regmap[n]==regs[i].regmap[hr]) {f_regmap[n]=-1;}
8090 }
8091 // and alloc new one
8092 f_regmap[hr]=regs[i].regmap[hr];
8093 }
8094 }
7c3a5182 8095 if(branch_regs[i].regmap[hr]>=0) {
b372a952 8096 if(f_regmap[hr]!=branch_regs[i].regmap[hr]) {
8097 // dealloc old register
8098 int n;
8099 for(n=0;n<HOST_REGS;n++)
8100 {
8101 if(f_regmap[n]==branch_regs[i].regmap[hr]) {f_regmap[n]=-1;}
8102 }
8103 // and alloc new one
8104 f_regmap[hr]=branch_regs[i].regmap[hr];
8105 }
8106 }
cf95b4f0 8107 if(dops[i].ooo) {
277718fa 8108 if(count_free_regs(regs[i].regmap)<=cinfo[i+1].min_free_regs)
e1190b87 8109 f_regmap[hr]=branch_regs[i].regmap[hr];
8110 }else{
277718fa 8111 if(count_free_regs(branch_regs[i].regmap)<=cinfo[i+1].min_free_regs)
57871462 8112 f_regmap[hr]=branch_regs[i].regmap[hr];
8113 }
8114 // Avoid dirty->clean transition
e1190b87 8115 #ifdef DESTRUCTIVE_WRITEBACK
57871462 8116 if(t>0) if(get_reg(regmap_pre[t],f_regmap[hr])>=0) if((regs[t].wasdirty>>get_reg(regmap_pre[t],f_regmap[hr]))&1) f_regmap[hr]=-1;
e1190b87 8117 #endif
8118 // This check is only strictly required in the DESTRUCTIVE_WRITEBACK
8119 // case above, however it's always a good idea. We can't hoist the
8120 // load if the register was already allocated, so there's no point
8121 // wasting time analyzing most of these cases. It only "succeeds"
8122 // when the mapping was different and the load can be replaced with
8123 // a mov, which is of negligible benefit. So such cases are
8124 // skipped below.
57871462 8125 if(f_regmap[hr]>0) {
198df76f 8126 if(regs[t].regmap[hr]==f_regmap[hr]||(regs[t].regmap_entry[hr]<0&&get_reg(regmap_pre[t],f_regmap[hr])<0)) {
57871462 8127 int r=f_regmap[hr];
8128 for(j=t;j<=i;j++)
8129 {
277718fa 8130 //printf("Test %x -> %x, %x %d/%d\n",start+i*4,cinfo[i].ba,start+j*4,hr,r);
57871462 8131 if(r<34&&((unneeded_reg[j]>>r)&1)) break;
00fa9369 8132 assert(r < 64);
9de8a0c3 8133 if(regs[j].regmap[hr]==f_regmap[hr]&&f_regmap[hr]<TEMPREG) {
277718fa 8134 //printf("Hit %x -> %x, %x %d/%d\n",start+i*4,cinfo[i].ba,start+j*4,hr,r);
57871462 8135 int k;
8136 if(regs[i].regmap[hr]==-1&&branch_regs[i].regmap[hr]==-1) {
670c0f22 8137 if(get_reg(regs[i].regmap,f_regmap[hr])>=0) break;
57871462 8138 if(get_reg(regs[i+2].regmap,f_regmap[hr])>=0) break;
57871462 8139 k=i;
8140 while(k>1&&regs[k-1].regmap[hr]==-1) {
277718fa 8141 if(count_free_regs(regs[k-1].regmap)<=cinfo[k-1].min_free_regs) {
e1190b87 8142 //printf("no free regs for store %x\n",start+(k-1)*4);
8143 break;
57871462 8144 }
57871462 8145 if(get_reg(regs[k-1].regmap,f_regmap[hr])>=0) {
8146 //printf("no-match due to different register\n");
8147 break;
8148 }
fe807a8a 8149 if (dops[k-2].is_jump) {
57871462 8150 //printf("no-match due to branch\n");
8151 break;
8152 }
8153 // call/ret fast path assumes no registers allocated
cf95b4f0 8154 if(k>2&&(dops[k-3].itype==UJUMP||dops[k-3].itype==RJUMP)&&dops[k-3].rt1==31) {
57871462 8155 break;
8156 }
57871462 8157 k--;
8158 }
57871462 8159 if(regs[k-1].regmap[hr]==f_regmap[hr]&&regmap_pre[k][hr]==f_regmap[hr]) {
8160 //printf("Extend r%d, %x ->\n",hr,start+k*4);
8161 while(k<i) {
8162 regs[k].regmap_entry[hr]=f_regmap[hr];
8163 regs[k].regmap[hr]=f_regmap[hr];
8164 regmap_pre[k+1][hr]=f_regmap[hr];
8165 regs[k].wasdirty&=~(1<<hr);
8166 regs[k].dirty&=~(1<<hr);
8167 regs[k].wasdirty|=(1<<hr)&regs[k-1].dirty;
8168 regs[k].dirty|=(1<<hr)&regs[k].wasdirty;
8169 regs[k].wasconst&=~(1<<hr);
8170 regs[k].isconst&=~(1<<hr);
8171 k++;
8172 }
8173 }
8174 else {
8175 //printf("Fail Extend r%d, %x ->\n",hr,start+k*4);
8176 break;
8177 }
8178 assert(regs[i-1].regmap[hr]==f_regmap[hr]);
8179 if(regs[i-1].regmap[hr]==f_regmap[hr]&&regmap_pre[i][hr]==f_regmap[hr]) {
8180 //printf("OK fill %x (r%d)\n",start+i*4,hr);
8181 regs[i].regmap_entry[hr]=f_regmap[hr];
8182 regs[i].regmap[hr]=f_regmap[hr];
8183 regs[i].wasdirty&=~(1<<hr);
8184 regs[i].dirty&=~(1<<hr);
8185 regs[i].wasdirty|=(1<<hr)&regs[i-1].dirty;
8186 regs[i].dirty|=(1<<hr)&regs[i-1].dirty;
8187 regs[i].wasconst&=~(1<<hr);
8188 regs[i].isconst&=~(1<<hr);
8189 branch_regs[i].regmap_entry[hr]=f_regmap[hr];
8190 branch_regs[i].wasdirty&=~(1<<hr);
8191 branch_regs[i].wasdirty|=(1<<hr)&regs[i].dirty;
8192 branch_regs[i].regmap[hr]=f_regmap[hr];
8193 branch_regs[i].dirty&=~(1<<hr);
8194 branch_regs[i].dirty|=(1<<hr)&regs[i].dirty;
8195 branch_regs[i].wasconst&=~(1<<hr);
8196 branch_regs[i].isconst&=~(1<<hr);
fe807a8a 8197 if (!dops[i].is_ujump) {
57871462 8198 regmap_pre[i+2][hr]=f_regmap[hr];
8199 regs[i+2].wasdirty&=~(1<<hr);
8200 regs[i+2].wasdirty|=(1<<hr)&regs[i].dirty;
57871462 8201 }
8202 }
8203 }
8204 for(k=t;k<j;k++) {
e1190b87 8205 // Alloc register clean at beginning of loop,
8206 // but may dirty it in pass 6
57871462 8207 regs[k].regmap_entry[hr]=f_regmap[hr];
8208 regs[k].regmap[hr]=f_regmap[hr];
57871462 8209 regs[k].dirty&=~(1<<hr);
8210 regs[k].wasconst&=~(1<<hr);
8211 regs[k].isconst&=~(1<<hr);
fe807a8a 8212 if (dops[k].is_jump) {
e1190b87 8213 branch_regs[k].regmap_entry[hr]=f_regmap[hr];
8214 branch_regs[k].regmap[hr]=f_regmap[hr];
8215 branch_regs[k].dirty&=~(1<<hr);
8216 branch_regs[k].wasconst&=~(1<<hr);
8217 branch_regs[k].isconst&=~(1<<hr);
fe807a8a 8218 if (!dops[k].is_ujump) {
e1190b87 8219 regmap_pre[k+2][hr]=f_regmap[hr];
8220 regs[k+2].wasdirty&=~(1<<hr);
e1190b87 8221 }
8222 }
8223 else
8224 {
8225 regmap_pre[k+1][hr]=f_regmap[hr];
8226 regs[k+1].wasdirty&=~(1<<hr);
8227 }
57871462 8228 }
8229 if(regs[j].regmap[hr]==f_regmap[hr])
8230 regs[j].regmap_entry[hr]=f_regmap[hr];
8231 break;
8232 }
8233 if(j==i) break;
8234 if(regs[j].regmap[hr]>=0)
8235 break;
8236 if(get_reg(regs[j].regmap,f_regmap[hr])>=0) {
8237 //printf("no-match due to different register\n");
8238 break;
8239 }
fe807a8a 8240 if (dops[j].is_ujump)
e1190b87 8241 {
8242 // Stop on unconditional branch
8243 break;
8244 }
cf95b4f0 8245 if(dops[j].itype==CJUMP||dops[j].itype==SJUMP)
e1190b87 8246 {
cf95b4f0 8247 if(dops[j].ooo) {
277718fa 8248 if(count_free_regs(regs[j].regmap)<=cinfo[j+1].min_free_regs)
e1190b87 8249 break;
8250 }else{
277718fa 8251 if(count_free_regs(branch_regs[j].regmap)<=cinfo[j+1].min_free_regs)
e1190b87 8252 break;
8253 }
8254 if(get_reg(branch_regs[j].regmap,f_regmap[hr])>=0) {
8255 //printf("no-match due to different register (branch)\n");
57871462 8256 break;
8257 }
8258 }
277718fa 8259 if(count_free_regs(regs[j].regmap)<=cinfo[j].min_free_regs) {
e1190b87 8260 //printf("No free regs for store %x\n",start+j*4);
8261 break;
8262 }
ad49de89 8263 assert(f_regmap[hr]<64);
57871462 8264 }
8265 }
8266 }
8267 }
8268 }
8269 }else{
198df76f 8270 // Non branch or undetermined branch target
57871462 8271 for(hr=0;hr<HOST_REGS;hr++)
8272 {
8273 if(hr!=EXCLUDE_REG) {
7c3a5182 8274 if(regs[i].regmap[hr]>=0) {
b372a952 8275 if(f_regmap[hr]!=regs[i].regmap[hr]) {
8276 // dealloc old register
8277 int n;
8278 for(n=0;n<HOST_REGS;n++)
8279 {
8280 if(f_regmap[n]==regs[i].regmap[hr]) {f_regmap[n]=-1;}
8281 }
4149788d 8282 // and alloc new one
8283 f_regmap[hr]=regs[i].regmap[hr];
8284 }
8285 }
8286 }
8287 }
8288 // Try to restore cycle count at branch targets
8289 if(dops[i].bt) {
8290 for(j=i;j<slen-1;j++) {
8291 if(regs[j].regmap[HOST_CCREG]!=-1) break;
277718fa 8292 if(count_free_regs(regs[j].regmap)<=cinfo[j].min_free_regs) {
4149788d 8293 //printf("no free regs for store %x\n",start+j*4);
8294 break;
8295 }
8296 }
8297 if(regs[j].regmap[HOST_CCREG]==CCREG) {
8298 int k=i;
8299 //printf("Extend CC, %x -> %x\n",start+k*4,start+j*4);
8300 while(k<j) {
8301 regs[k].regmap_entry[HOST_CCREG]=CCREG;
8302 regs[k].regmap[HOST_CCREG]=CCREG;
8303 regmap_pre[k+1][HOST_CCREG]=CCREG;
8304 regs[k+1].wasdirty|=1<<HOST_CCREG;
8305 regs[k].dirty|=1<<HOST_CCREG;
8306 regs[k].wasconst&=~(1<<HOST_CCREG);
8307 regs[k].isconst&=~(1<<HOST_CCREG);
8308 k++;
8309 }
8310 regs[j].regmap_entry[HOST_CCREG]=CCREG;
8311 }
8312 // Work backwards from the branch target
8313 if(j>i&&f_regmap[HOST_CCREG]==CCREG)
8314 {
8315 //printf("Extend backwards\n");
8316 int k;
8317 k=i;
8318 while(regs[k-1].regmap[HOST_CCREG]==-1) {
277718fa 8319 if(count_free_regs(regs[k-1].regmap)<=cinfo[k-1].min_free_regs) {
4149788d 8320 //printf("no free regs for store %x\n",start+(k-1)*4);
8321 break;
8322 }
8323 k--;
8324 }
8325 if(regs[k-1].regmap[HOST_CCREG]==CCREG) {
8326 //printf("Extend CC, %x ->\n",start+k*4);
8327 while(k<=i) {
8328 regs[k].regmap_entry[HOST_CCREG]=CCREG;
8329 regs[k].regmap[HOST_CCREG]=CCREG;
8330 regmap_pre[k+1][HOST_CCREG]=CCREG;
8331 regs[k+1].wasdirty|=1<<HOST_CCREG;
8332 regs[k].dirty|=1<<HOST_CCREG;
8333 regs[k].wasconst&=~(1<<HOST_CCREG);
8334 regs[k].isconst&=~(1<<HOST_CCREG);
8335 k++;
8336 }
8337 }
8338 else {
8339 //printf("Fail Extend CC, %x ->\n",start+k*4);
8340 }
8341 }
8342 }
a5cd72d0 8343 if(dops[i].itype!=STORE&&dops[i].itype!=STORELR&&dops[i].itype!=SHIFT&&
4149788d 8344 dops[i].itype!=NOP&&dops[i].itype!=MOV&&dops[i].itype!=ALU&&dops[i].itype!=SHIFTIMM&&
a5cd72d0 8345 dops[i].itype!=IMM16&&dops[i].itype!=LOAD)
4149788d 8346 {
8347 memcpy(f_regmap,regs[i].regmap,sizeof(f_regmap));
8348 }
8349 }
8350 }
8351}
8352
8353// This allocates registers (if possible) one instruction prior
8354// to use, which can avoid a load-use penalty on certain CPUs.
8355static noinline void pass5b_preallocate2(void)
8356{
8357 int i, hr;
8358 for(i=0;i<slen-1;i++)
8359 {
8360 if (!i || !dops[i-1].is_jump)
8361 {
8362 if(!dops[i+1].bt)
8363 {
277718fa 8364 int j, can_steal = 1;
8365 for (j = i; j < i + 2; j++) {
8366 int free_regs = 0;
8367 if (cinfo[j].min_free_regs == 0)
8368 continue;
8369 for (hr = 0; hr < HOST_REGS; hr++)
8370 if (hr != EXCLUDE_REG && regs[j].regmap[hr] < 0)
8371 free_regs++;
8372 if (free_regs <= cinfo[j].min_free_regs) {
8373 can_steal = 0;
8374 break;
8375 }
8376 }
8377 if (!can_steal)
8378 continue;
4149788d 8379 if(dops[i].itype==ALU||dops[i].itype==MOV||dops[i].itype==LOAD||dops[i].itype==SHIFTIMM||dops[i].itype==IMM16
a5cd72d0 8380 ||(dops[i].itype==COP2&&dops[i].opcode2<3))
4149788d 8381 {
8382 if(dops[i+1].rs1) {
8383 if((hr=get_reg(regs[i+1].regmap,dops[i+1].rs1))>=0)
8384 {
8385 if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
8386 {
8387 regs[i].regmap[hr]=regs[i+1].regmap[hr];
8388 regmap_pre[i+1][hr]=regs[i+1].regmap[hr];
8389 regs[i+1].regmap_entry[hr]=regs[i+1].regmap[hr];
8390 regs[i].isconst&=~(1<<hr);
8391 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
8392 constmap[i][hr]=constmap[i+1][hr];
8393 regs[i+1].wasdirty&=~(1<<hr);
8394 regs[i].dirty&=~(1<<hr);
8395 }
8396 }
8397 }
8398 if(dops[i+1].rs2) {
8399 if((hr=get_reg(regs[i+1].regmap,dops[i+1].rs2))>=0)
8400 {
8401 if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
8402 {
8403 regs[i].regmap[hr]=regs[i+1].regmap[hr];
8404 regmap_pre[i+1][hr]=regs[i+1].regmap[hr];
8405 regs[i+1].regmap_entry[hr]=regs[i+1].regmap[hr];
8406 regs[i].isconst&=~(1<<hr);
8407 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
8408 constmap[i][hr]=constmap[i+1][hr];
8409 regs[i+1].wasdirty&=~(1<<hr);
8410 regs[i].dirty&=~(1<<hr);
8411 }
8412 }
8413 }
8414 // Preload target address for load instruction (non-constant)
8415 if(dops[i+1].itype==LOAD&&dops[i+1].rs1&&get_reg(regs[i+1].regmap,dops[i+1].rs1)<0) {
a5cd72d0 8416 if((hr=get_reg_w(regs[i+1].regmap, dops[i+1].rt1))>=0)
4149788d 8417 {
8418 if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
8419 {
8420 regs[i].regmap[hr]=dops[i+1].rs1;
8421 regmap_pre[i+1][hr]=dops[i+1].rs1;
8422 regs[i+1].regmap_entry[hr]=dops[i+1].rs1;
8423 regs[i].isconst&=~(1<<hr);
8424 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
8425 constmap[i][hr]=constmap[i+1][hr];
8426 regs[i+1].wasdirty&=~(1<<hr);
8427 regs[i].dirty&=~(1<<hr);
8428 }
8429 }
8430 }
8431 // Load source into target register
8432 if(dops[i+1].use_lt1&&get_reg(regs[i+1].regmap,dops[i+1].rs1)<0) {
a5cd72d0 8433 if((hr=get_reg_w(regs[i+1].regmap, dops[i+1].rt1))>=0)
4149788d 8434 {
8435 if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
8436 {
8437 regs[i].regmap[hr]=dops[i+1].rs1;
8438 regmap_pre[i+1][hr]=dops[i+1].rs1;
8439 regs[i+1].regmap_entry[hr]=dops[i+1].rs1;
8440 regs[i].isconst&=~(1<<hr);
8441 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
8442 constmap[i][hr]=constmap[i+1][hr];
8443 regs[i+1].wasdirty&=~(1<<hr);
8444 regs[i].dirty&=~(1<<hr);
8445 }
8446 }
8447 }
8448 // Address for store instruction (non-constant)
277718fa 8449 if (dops[i+1].is_store) { // SB/SH/SW/SWC2
4149788d 8450 if(get_reg(regs[i+1].regmap,dops[i+1].rs1)<0) {
8451 hr=get_reg2(regs[i].regmap,regs[i+1].regmap,-1);
8452 if(hr<0) hr=get_reg_temp(regs[i+1].regmap);
8453 else {
8454 regs[i+1].regmap[hr]=AGEN1+((i+1)&1);
8455 regs[i+1].isconst&=~(1<<hr);
277718fa 8456 regs[i+1].dirty&=~(1<<hr);
8457 regs[i+2].wasdirty&=~(1<<hr);
4149788d 8458 }
8459 assert(hr>=0);
f0b91b78 8460 #if 0 // what is this for? double allocs $0 in ps1_rom.bin
4149788d 8461 if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
8462 {
8463 regs[i].regmap[hr]=dops[i+1].rs1;
8464 regmap_pre[i+1][hr]=dops[i+1].rs1;
8465 regs[i+1].regmap_entry[hr]=dops[i+1].rs1;
8466 regs[i].isconst&=~(1<<hr);
8467 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
8468 constmap[i][hr]=constmap[i+1][hr];
8469 regs[i+1].wasdirty&=~(1<<hr);
8470 regs[i].dirty&=~(1<<hr);
8471 }
f0b91b78 8472 #endif
4149788d 8473 }
8474 }
277718fa 8475 if (dops[i+1].itype == LOADLR || dops[i+1].opcode == 0x32) { // LWC2
4149788d 8476 if(get_reg(regs[i+1].regmap,dops[i+1].rs1)<0) {
8477 int nr;
8478 hr=get_reg(regs[i+1].regmap,FTEMP);
8479 assert(hr>=0);
8480 if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
8481 {
8482 regs[i].regmap[hr]=dops[i+1].rs1;
8483 regmap_pre[i+1][hr]=dops[i+1].rs1;
8484 regs[i+1].regmap_entry[hr]=dops[i+1].rs1;
8485 regs[i].isconst&=~(1<<hr);
8486 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
8487 constmap[i][hr]=constmap[i+1][hr];
8488 regs[i+1].wasdirty&=~(1<<hr);
8489 regs[i].dirty&=~(1<<hr);
8490 }
8491 else if((nr=get_reg2(regs[i].regmap,regs[i+1].regmap,-1))>=0)
8492 {
8493 // move it to another register
8494 regs[i+1].regmap[hr]=-1;
8495 regmap_pre[i+2][hr]=-1;
8496 regs[i+1].regmap[nr]=FTEMP;
8497 regmap_pre[i+2][nr]=FTEMP;
8498 regs[i].regmap[nr]=dops[i+1].rs1;
8499 regmap_pre[i+1][nr]=dops[i+1].rs1;
8500 regs[i+1].regmap_entry[nr]=dops[i+1].rs1;
8501 regs[i].isconst&=~(1<<nr);
8502 regs[i+1].isconst&=~(1<<nr);
8503 regs[i].dirty&=~(1<<nr);
8504 regs[i+1].wasdirty&=~(1<<nr);
8505 regs[i+1].dirty&=~(1<<nr);
8506 regs[i+2].wasdirty&=~(1<<nr);
8507 }
8508 }
8509 }
a5cd72d0 8510 if(dops[i+1].itype==LOAD||dops[i+1].itype==LOADLR||dops[i+1].itype==STORE||dops[i+1].itype==STORELR/*||dops[i+1].itype==C2LS*/) {
4149788d 8511 hr = -1;
8512 if(dops[i+1].itype==LOAD)
a5cd72d0 8513 hr=get_reg_w(regs[i+1].regmap, dops[i+1].rt1);
277718fa 8514 if (dops[i+1].itype == LOADLR || dops[i+1].opcode == 0x32) // LWC2
4149788d 8515 hr=get_reg(regs[i+1].regmap,FTEMP);
277718fa 8516 if (dops[i+1].is_store) {
4149788d 8517 hr=get_reg(regs[i+1].regmap,AGEN1+((i+1)&1));
8518 if(hr<0) hr=get_reg_temp(regs[i+1].regmap);
8519 }
8520 if(hr>=0&&regs[i].regmap[hr]<0) {
8521 int rs=get_reg(regs[i+1].regmap,dops[i+1].rs1);
8522 if(rs>=0&&((regs[i+1].wasconst>>rs)&1)) {
8523 regs[i].regmap[hr]=AGEN1+((i+1)&1);
8524 regmap_pre[i+1][hr]=AGEN1+((i+1)&1);
8525 regs[i+1].regmap_entry[hr]=AGEN1+((i+1)&1);
8526 regs[i].isconst&=~(1<<hr);
8527 regs[i+1].wasdirty&=~(1<<hr);
8528 regs[i].dirty&=~(1<<hr);
8529 }
b372a952 8530 }
8531 }
57871462 8532 }
8533 }
4149788d 8534 }
8535 }
8536}
8537
8538// Write back dirty registers as soon as we will no longer modify them,
8539// so that we don't end up with lots of writes at the branches.
8540static noinline void pass6_clean_registers(int istart, int iend, int wr)
8541{
53358c1d 8542 static u_int wont_dirty[MAXBLOCK];
8543 static u_int will_dirty[MAXBLOCK];
4149788d 8544 int i;
8545 int r;
8546 u_int will_dirty_i,will_dirty_next,temp_will_dirty;
8547 u_int wont_dirty_i,wont_dirty_next,temp_wont_dirty;
8548 if(iend==slen-1) {
8549 will_dirty_i=will_dirty_next=0;
8550 wont_dirty_i=wont_dirty_next=0;
8551 }else{
8552 will_dirty_i=will_dirty_next=will_dirty[iend+1];
8553 wont_dirty_i=wont_dirty_next=wont_dirty[iend+1];
8554 }
8555 for (i=iend;i>=istart;i--)
8556 {
8557 signed char rregmap_i[RRMAP_SIZE];
8558 u_int hr_candirty = 0;
8559 assert(HOST_REGS < 32);
8560 make_rregs(regs[i].regmap, rregmap_i, &hr_candirty);
8561 __builtin_prefetch(regs[i-1].regmap);
8562 if(dops[i].is_jump)
8563 {
8564 signed char branch_rregmap_i[RRMAP_SIZE];
8565 u_int branch_hr_candirty = 0;
8566 make_rregs(branch_regs[i].regmap, branch_rregmap_i, &branch_hr_candirty);
277718fa 8567 if(cinfo[i].ba<start || cinfo[i].ba>=(start+slen*4))
4149788d 8568 {
8569 // Branch out of this block, flush all regs
8570 will_dirty_i = 0;
8571 will_dirty_i |= 1u << (get_rreg(branch_rregmap_i, dops[i].rt1) & 31);
8572 will_dirty_i |= 1u << (get_rreg(branch_rregmap_i, dops[i].rt2) & 31);
8573 will_dirty_i |= 1u << (get_rreg(branch_rregmap_i, dops[i+1].rt1) & 31);
8574 will_dirty_i |= 1u << (get_rreg(branch_rregmap_i, dops[i+1].rt2) & 31);
8575 will_dirty_i |= 1u << (get_rreg(branch_rregmap_i, CCREG) & 31);
8576 will_dirty_i &= branch_hr_candirty;
8577 if (dops[i].is_ujump)
8578 {
8579 // Unconditional branch
8580 wont_dirty_i = 0;
8581 // Merge in delay slot (will dirty)
8582 will_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i].rt1) & 31);
8583 will_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i].rt2) & 31);
8584 will_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i+1].rt1) & 31);
8585 will_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i+1].rt2) & 31);
8586 will_dirty_i |= 1u << (get_rreg(rregmap_i, CCREG) & 31);
8587 will_dirty_i &= hr_candirty;
57871462 8588 }
4149788d 8589 else
8590 {
8591 // Conditional branch
8592 wont_dirty_i = wont_dirty_next;
8593 // Merge in delay slot (will dirty)
8594 // (the original code had no explanation why these 2 are commented out)
8595 //will_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i].rt1) & 31);
8596 //will_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i].rt2) & 31);
8597 will_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i+1].rt1) & 31);
8598 will_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i+1].rt2) & 31);
8599 will_dirty_i |= 1u << (get_rreg(rregmap_i, CCREG) & 31);
8600 will_dirty_i &= hr_candirty;
8601 }
8602 // Merge in delay slot (wont dirty)
8603 wont_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i].rt1) & 31);
8604 wont_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i].rt2) & 31);
8605 wont_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i+1].rt1) & 31);
8606 wont_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i+1].rt2) & 31);
8607 wont_dirty_i |= 1u << (get_rreg(rregmap_i, CCREG) & 31);
8608 wont_dirty_i |= 1u << (get_rreg(branch_rregmap_i, dops[i].rt1) & 31);
8609 wont_dirty_i |= 1u << (get_rreg(branch_rregmap_i, dops[i].rt2) & 31);
8610 wont_dirty_i |= 1u << (get_rreg(branch_rregmap_i, dops[i+1].rt1) & 31);
8611 wont_dirty_i |= 1u << (get_rreg(branch_rregmap_i, dops[i+1].rt2) & 31);
8612 wont_dirty_i |= 1u << (get_rreg(branch_rregmap_i, CCREG) & 31);
8613 wont_dirty_i &= ~(1u << 31);
8614 if(wr) {
8615 #ifndef DESTRUCTIVE_WRITEBACK
8616 branch_regs[i].dirty&=wont_dirty_i;
8617 #endif
8618 branch_regs[i].dirty|=will_dirty_i;
8619 }
8620 }
8621 else
8622 {
8623 // Internal branch
277718fa 8624 if(cinfo[i].ba<=start+i*4) {
4149788d 8625 // Backward branch
8626 if (dops[i].is_ujump)
8627 {
8628 // Unconditional branch
8629 temp_will_dirty=0;
8630 temp_wont_dirty=0;
8631 // Merge in delay slot (will dirty)
8632 temp_will_dirty |= 1u << (get_rreg(branch_rregmap_i, dops[i].rt1) & 31);
8633 temp_will_dirty |= 1u << (get_rreg(branch_rregmap_i, dops[i].rt2) & 31);
8634 temp_will_dirty |= 1u << (get_rreg(branch_rregmap_i, dops[i+1].rt1) & 31);
8635 temp_will_dirty |= 1u << (get_rreg(branch_rregmap_i, dops[i+1].rt2) & 31);
8636 temp_will_dirty |= 1u << (get_rreg(branch_rregmap_i, CCREG) & 31);
8637 temp_will_dirty &= branch_hr_candirty;
8638 temp_will_dirty |= 1u << (get_rreg(rregmap_i, dops[i].rt1) & 31);
8639 temp_will_dirty |= 1u << (get_rreg(rregmap_i, dops[i].rt2) & 31);
8640 temp_will_dirty |= 1u << (get_rreg(rregmap_i, dops[i+1].rt1) & 31);
8641 temp_will_dirty |= 1u << (get_rreg(rregmap_i, dops[i+1].rt2) & 31);
8642 temp_will_dirty |= 1u << (get_rreg(rregmap_i, CCREG) & 31);
8643 temp_will_dirty &= hr_candirty;
8644 } else {
8645 // Conditional branch (not taken case)
8646 temp_will_dirty=will_dirty_next;
8647 temp_wont_dirty=wont_dirty_next;
8648 // Merge in delay slot (will dirty)
8649 temp_will_dirty |= 1u << (get_rreg(branch_rregmap_i, dops[i].rt1) & 31);
8650 temp_will_dirty |= 1u << (get_rreg(branch_rregmap_i, dops[i].rt2) & 31);
8651 temp_will_dirty |= 1u << (get_rreg(branch_rregmap_i, dops[i+1].rt1) & 31);
8652 temp_will_dirty |= 1u << (get_rreg(branch_rregmap_i, dops[i+1].rt2) & 31);
8653 temp_will_dirty |= 1u << (get_rreg(branch_rregmap_i, CCREG) & 31);
8654 temp_will_dirty &= branch_hr_candirty;
8655 //temp_will_dirty |= 1u << (get_rreg(rregmap_i, dops[i].rt1) & 31);
8656 //temp_will_dirty |= 1u << (get_rreg(rregmap_i, dops[i].rt2) & 31);
8657 temp_will_dirty |= 1u << (get_rreg(rregmap_i, dops[i+1].rt1) & 31);
8658 temp_will_dirty |= 1u << (get_rreg(rregmap_i, dops[i+1].rt2) & 31);
8659 temp_will_dirty |= 1u << (get_rreg(rregmap_i, CCREG) & 31);
8660 temp_will_dirty &= hr_candirty;
8661 }
8662 // Merge in delay slot (wont dirty)
8663 temp_wont_dirty |= 1u << (get_rreg(rregmap_i, dops[i].rt1) & 31);
8664 temp_wont_dirty |= 1u << (get_rreg(rregmap_i, dops[i].rt2) & 31);
8665 temp_wont_dirty |= 1u << (get_rreg(rregmap_i, dops[i+1].rt1) & 31);
8666 temp_wont_dirty |= 1u << (get_rreg(rregmap_i, dops[i+1].rt2) & 31);
8667 temp_wont_dirty |= 1u << (get_rreg(rregmap_i, CCREG) & 31);
8668 temp_wont_dirty |= 1u << (get_rreg(branch_rregmap_i, dops[i].rt1) & 31);
8669 temp_wont_dirty |= 1u << (get_rreg(branch_rregmap_i, dops[i].rt2) & 31);
8670 temp_wont_dirty |= 1u << (get_rreg(branch_rregmap_i, dops[i+1].rt1) & 31);
8671 temp_wont_dirty |= 1u << (get_rreg(branch_rregmap_i, dops[i+1].rt2) & 31);
8672 temp_wont_dirty |= 1u << (get_rreg(branch_rregmap_i, CCREG) & 31);
8673 temp_wont_dirty &= ~(1u << 31);
8674 // Deal with changed mappings
8675 if(i<iend) {
8676 for(r=0;r<HOST_REGS;r++) {
8677 if(r!=EXCLUDE_REG) {
8678 if(regs[i].regmap[r]!=regmap_pre[i][r]) {
8679 temp_will_dirty&=~(1<<r);
8680 temp_wont_dirty&=~(1<<r);
8681 if(regmap_pre[i][r]>0 && regmap_pre[i][r]<34) {
8682 temp_will_dirty|=((unneeded_reg[i]>>regmap_pre[i][r])&1)<<r;
8683 temp_wont_dirty|=((unneeded_reg[i]>>regmap_pre[i][r])&1)<<r;
8684 } else {
8685 temp_will_dirty|=1<<r;
8686 temp_wont_dirty|=1<<r;
8687 }
8688 }
8689 }
8690 }
8691 }
8692 if(wr) {
8693 will_dirty[i]=temp_will_dirty;
8694 wont_dirty[i]=temp_wont_dirty;
277718fa 8695 pass6_clean_registers((cinfo[i].ba-start)>>2,i-1,0);
4149788d 8696 }else{
8697 // Limit recursion. It can take an excessive amount
8698 // of time if there are a lot of nested loops.
277718fa 8699 will_dirty[(cinfo[i].ba-start)>>2]=0;
8700 wont_dirty[(cinfo[i].ba-start)>>2]=-1;
57871462 8701 }
57871462 8702 }
4149788d 8703 /*else*/ if(1)
57871462 8704 {
4149788d 8705 if (dops[i].is_ujump)
8706 {
8707 // Unconditional branch
8708 will_dirty_i=0;
8709 wont_dirty_i=0;
277718fa 8710 //if(cinfo[i].ba>start+i*4) { // Disable recursion (for debugging)
4149788d 8711 for(r=0;r<HOST_REGS;r++) {
8712 if(r!=EXCLUDE_REG) {
277718fa 8713 if(branch_regs[i].regmap[r]==regs[(cinfo[i].ba-start)>>2].regmap_entry[r]) {
8714 will_dirty_i|=will_dirty[(cinfo[i].ba-start)>>2]&(1<<r);
8715 wont_dirty_i|=wont_dirty[(cinfo[i].ba-start)>>2]&(1<<r);
4149788d 8716 }
8717 if(branch_regs[i].regmap[r]>=0) {
277718fa 8718 will_dirty_i|=((unneeded_reg[(cinfo[i].ba-start)>>2]>>branch_regs[i].regmap[r])&1)<<r;
8719 wont_dirty_i|=((unneeded_reg[(cinfo[i].ba-start)>>2]>>branch_regs[i].regmap[r])&1)<<r;
4149788d 8720 }
8721 }
57871462 8722 }
4149788d 8723 //}
8724 // Merge in delay slot
8725 will_dirty_i |= 1u << (get_rreg(branch_rregmap_i, dops[i].rt1) & 31);
8726 will_dirty_i |= 1u << (get_rreg(branch_rregmap_i, dops[i].rt2) & 31);
8727 will_dirty_i |= 1u << (get_rreg(branch_rregmap_i, dops[i+1].rt1) & 31);
8728 will_dirty_i |= 1u << (get_rreg(branch_rregmap_i, dops[i+1].rt2) & 31);
8729 will_dirty_i |= 1u << (get_rreg(branch_rregmap_i, CCREG) & 31);
8730 will_dirty_i &= branch_hr_candirty;
8731 will_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i].rt1) & 31);
8732 will_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i].rt2) & 31);
8733 will_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i+1].rt1) & 31);
8734 will_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i+1].rt2) & 31);
8735 will_dirty_i |= 1u << (get_rreg(rregmap_i, CCREG) & 31);
8736 will_dirty_i &= hr_candirty;
8737 } else {
8738 // Conditional branch
8739 will_dirty_i=will_dirty_next;
8740 wont_dirty_i=wont_dirty_next;
277718fa 8741 //if(cinfo[i].ba>start+i*4) // Disable recursion (for debugging)
4149788d 8742 for(r=0;r<HOST_REGS;r++) {
8743 if(r!=EXCLUDE_REG) {
8744 signed char target_reg=branch_regs[i].regmap[r];
277718fa 8745 if(target_reg==regs[(cinfo[i].ba-start)>>2].regmap_entry[r]) {
8746 will_dirty_i&=will_dirty[(cinfo[i].ba-start)>>2]&(1<<r);
8747 wont_dirty_i|=wont_dirty[(cinfo[i].ba-start)>>2]&(1<<r);
4149788d 8748 }
8749 else if(target_reg>=0) {
277718fa 8750 will_dirty_i&=((unneeded_reg[(cinfo[i].ba-start)>>2]>>target_reg)&1)<<r;
8751 wont_dirty_i|=((unneeded_reg[(cinfo[i].ba-start)>>2]>>target_reg)&1)<<r;
4149788d 8752 }
8753 }
57871462 8754 }
4149788d 8755 // Merge in delay slot
8756 will_dirty_i |= 1u << (get_rreg(branch_rregmap_i, dops[i].rt1) & 31);
8757 will_dirty_i |= 1u << (get_rreg(branch_rregmap_i, dops[i].rt2) & 31);
8758 will_dirty_i |= 1u << (get_rreg(branch_rregmap_i, dops[i+1].rt1) & 31);
8759 will_dirty_i |= 1u << (get_rreg(branch_rregmap_i, dops[i+1].rt2) & 31);
8760 will_dirty_i |= 1u << (get_rreg(branch_rregmap_i, CCREG) & 31);
8761 will_dirty_i &= branch_hr_candirty;
8762 //will_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i].rt1) & 31);
8763 //will_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i].rt2) & 31);
8764 will_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i+1].rt1) & 31);
8765 will_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i+1].rt2) & 31);
8766 will_dirty_i |= 1u << (get_rreg(rregmap_i, CCREG) & 31);
8767 will_dirty_i &= hr_candirty;
57871462 8768 }
4149788d 8769 // Merge in delay slot (won't dirty)
8770 wont_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i].rt1) & 31);
8771 wont_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i].rt2) & 31);
8772 wont_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i+1].rt1) & 31);
8773 wont_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i+1].rt2) & 31);
8774 wont_dirty_i |= 1u << (get_rreg(rregmap_i, CCREG) & 31);
8775 wont_dirty_i |= 1u << (get_rreg(branch_rregmap_i, dops[i].rt1) & 31);
8776 wont_dirty_i |= 1u << (get_rreg(branch_rregmap_i, dops[i].rt2) & 31);
8777 wont_dirty_i |= 1u << (get_rreg(branch_rregmap_i, dops[i+1].rt1) & 31);
8778 wont_dirty_i |= 1u << (get_rreg(branch_rregmap_i, dops[i+1].rt2) & 31);
8779 wont_dirty_i |= 1u << (get_rreg(branch_rregmap_i, CCREG) & 31);
8780 wont_dirty_i &= ~(1u << 31);
8781 if(wr) {
8782 #ifndef DESTRUCTIVE_WRITEBACK
8783 branch_regs[i].dirty&=wont_dirty_i;
8784 #endif
8785 branch_regs[i].dirty|=will_dirty_i;
57871462 8786 }
8787 }
8788 }
57871462 8789 }
277718fa 8790 else if (dops[i].is_exception)
4149788d 8791 {
277718fa 8792 // SYSCALL instruction, etc
4149788d 8793 will_dirty_i=0;
8794 wont_dirty_i=0;
8795 }
8796 will_dirty_next=will_dirty_i;
8797 wont_dirty_next=wont_dirty_i;
8798 will_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i].rt1) & 31);
8799 will_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i].rt2) & 31);
8800 will_dirty_i |= 1u << (get_rreg(rregmap_i, CCREG) & 31);
8801 will_dirty_i &= hr_candirty;
8802 wont_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i].rt1) & 31);
8803 wont_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i].rt2) & 31);
8804 wont_dirty_i |= 1u << (get_rreg(rregmap_i, CCREG) & 31);
8805 wont_dirty_i &= ~(1u << 31);
8806 if (i > istart && !dops[i].is_jump) {
8807 // Don't store a register immediately after writing it,
8808 // may prevent dual-issue.
8809 wont_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i-1].rt1) & 31);
8810 wont_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i-1].rt2) & 31);
8811 }
8812 // Save it
8813 will_dirty[i]=will_dirty_i;
8814 wont_dirty[i]=wont_dirty_i;
8815 // Mark registers that won't be dirtied as not dirty
8816 if(wr) {
8817 regs[i].dirty|=will_dirty_i;
8818 #ifndef DESTRUCTIVE_WRITEBACK
8819 regs[i].dirty&=wont_dirty_i;
8820 if(dops[i].is_jump)
57871462 8821 {
4149788d 8822 if (i < iend-1 && !dops[i].is_ujump) {
8823 for(r=0;r<HOST_REGS;r++) {
8824 if(r!=EXCLUDE_REG) {
8825 if(regs[i].regmap[r]==regmap_pre[i+2][r]) {
8826 regs[i+2].wasdirty&=wont_dirty_i|~(1<<r);
8827 }else {/*printf("i: %x (%d) mismatch(+2): %d\n",start+i*4,i,r);assert(!((wont_dirty_i>>r)&1));*/}
57871462 8828 }
8829 }
8830 }
4149788d 8831 }
8832 else
8833 {
8834 if(i<iend) {
8835 for(r=0;r<HOST_REGS;r++) {
8836 if(r!=EXCLUDE_REG) {
8837 if(regs[i].regmap[r]==regmap_pre[i+1][r]) {
8838 regs[i+1].wasdirty&=wont_dirty_i|~(1<<r);
8839 }else {/*printf("i: %x (%d) mismatch(+1): %d\n",start+i*4,i,r);assert(!((wont_dirty_i>>r)&1));*/}
57871462 8840 }
8841 }
8842 }
4149788d 8843 }
8844 #endif
8845 }
8846 // Deal with changed mappings
8847 temp_will_dirty=will_dirty_i;
8848 temp_wont_dirty=wont_dirty_i;
8849 for(r=0;r<HOST_REGS;r++) {
8850 if(r!=EXCLUDE_REG) {
8851 int nr;
8852 if(regs[i].regmap[r]==regmap_pre[i][r]) {
8853 if(wr) {
8854 #ifndef DESTRUCTIVE_WRITEBACK
8855 regs[i].wasdirty&=wont_dirty_i|~(1<<r);
8856 #endif
8857 regs[i].wasdirty|=will_dirty_i&(1<<r);
57871462 8858 }
4149788d 8859 }
8860 else if(regmap_pre[i][r]>=0&&(nr=get_rreg(rregmap_i,regmap_pre[i][r]))>=0) {
8861 // Register moved to a different register
8862 will_dirty_i&=~(1<<r);
8863 wont_dirty_i&=~(1<<r);
8864 will_dirty_i|=((temp_will_dirty>>nr)&1)<<r;
8865 wont_dirty_i|=((temp_wont_dirty>>nr)&1)<<r;
8866 if(wr) {
8867 #ifndef DESTRUCTIVE_WRITEBACK
8868 regs[i].wasdirty&=wont_dirty_i|~(1<<r);
8869 #endif
8870 regs[i].wasdirty|=will_dirty_i&(1<<r);
8871 }
8872 }
8873 else {
8874 will_dirty_i&=~(1<<r);
8875 wont_dirty_i&=~(1<<r);
8876 if(regmap_pre[i][r]>0 && regmap_pre[i][r]<34) {
8877 will_dirty_i|=((unneeded_reg[i]>>regmap_pre[i][r])&1)<<r;
8878 wont_dirty_i|=((unneeded_reg[i]>>regmap_pre[i][r])&1)<<r;
8879 } else {
8880 wont_dirty_i|=1<<r;
8881 /*printf("i: %x (%d) mismatch: %d\n",start+i*4,i,r);assert(!((will_dirty>>r)&1));*/
57871462 8882 }
8883 }
8884 }
8885 }
8886 }
4149788d 8887}
8888
8889static noinline void pass10_expire_blocks(void)
8890{
93c0345b 8891 u_int step = MAX_OUTPUT_BLOCK_SIZE / PAGE_COUNT / 2;
8892 // not sizeof(ndrc->translation_cache) due to vita hack
8893 u_int step_mask = ((1u << TARGET_SIZE_2) - 1u) & ~(step - 1u);
8894 u_int end = (out - ndrc->translation_cache + EXPIRITY_OFFSET) & step_mask;
8895 u_int base_shift = __builtin_ctz(MAX_OUTPUT_BLOCK_SIZE);
8896 int hit;
8897
8898 for (; expirep != end; expirep = ((expirep + step) & step_mask))
4149788d 8899 {
93c0345b 8900 u_int base_offs = expirep & ~(MAX_OUTPUT_BLOCK_SIZE - 1);
8901 u_int block_i = expirep / step & (PAGE_COUNT - 1);
8902 u_int phase = (expirep >> (base_shift - 1)) & 1u;
8903 if (!(expirep & (MAX_OUTPUT_BLOCK_SIZE / 2 - 1))) {
9b495f6e 8904 inv_debug("EXP: base_offs %x/%lx phase %u\n", base_offs,
8905 (long)(out - ndrc->translation_cache), phase);
93c0345b 8906 }
8907
8908 if (!phase) {
8909 hit = blocks_remove_matching_addrs(&blocks[block_i], base_offs, base_shift);
8910 if (hit) {
8911 do_clear_cache();
04714958 8912 mini_ht_clear();
93c0345b 8913 }
4149788d 8914 }
93c0345b 8915 else
b7ad2f2c 8916 unlink_jumps_tc_range(jumps[block_i], base_offs, base_shift);
4149788d 8917 }
8918}
8919
104df9d3 8920static struct block_info *new_block_info(u_int start, u_int len,
8921 const void *source, const void *copy, u_char *beginning, u_short jump_in_count)
8922{
8923 struct block_info **b_pptr;
8924 struct block_info *block;
8925 u_int page = get_page(start);
8926
8927 block = malloc(sizeof(*block) + jump_in_count * sizeof(block->jump_in[0]));
8928 assert(block);
8929 assert(jump_in_count > 0);
8930 block->source = source;
8931 block->copy = copy;
8932 block->start = start;
8933 block->len = len;
8934 block->reg_sv_flags = 0;
8935 block->tc_offs = beginning - ndrc->translation_cache;
8936 //block->tc_len = out - beginning;
8937 block->is_dirty = 0;
3280e616 8938 block->inv_near_misses = 0;
104df9d3 8939 block->jump_in_cnt = jump_in_count;
8940
93c0345b 8941 // insert sorted by start mirror-unmasked vaddr
104df9d3 8942 for (b_pptr = &blocks[page]; ; b_pptr = &((*b_pptr)->next)) {
8943 if (*b_pptr == NULL || (*b_pptr)->start >= start) {
8944 block->next = *b_pptr;
8945 *b_pptr = block;
8946 break;
8947 }
8948 }
8949 stat_inc(stat_blocks);
8950 return block;
8951}
8952
8953static int new_recompile_block(u_int addr)
4149788d 8954{
8955 u_int pagelimit = 0;
8956 u_int state_rflags = 0;
8957 int i;
8958
8959 assem_debug("NOTCOMPILED: addr = %x -> %p\n", addr, out);
8960
a5cd72d0 8961 if (addr & 3) {
8962 if (addr != hack_addr) {
8963 SysPrintf("game crash @%08x, ra=%08x\n", addr, psxRegs.GPR.n.ra);
8964 hack_addr = addr;
8965 }
8966 return -1;
8967 }
8968
4149788d 8969 // this is just for speculation
8970 for (i = 1; i < 32; i++) {
8971 if ((psxRegs.GPR.r[i] & 0xffff0000) == 0x1f800000)
8972 state_rflags |= 1 << i;
8973 }
8974
a5cd72d0 8975 start = addr;
4149788d 8976 new_dynarec_did_compile=1;
8977 if (Config.HLE && start == 0x80001000) // hlecall
8978 {
104df9d3 8979 void *beginning = start_block();
4149788d 8980
4149788d 8981 emit_movimm(start,0);
8982 emit_writeword(0,&pcaddr);
8983 emit_far_jump(new_dyna_leave);
8984 literal_pool(0);
8985 end_block(beginning);
104df9d3 8986 struct block_info *block = new_block_info(start, 4, NULL, NULL, beginning, 1);
8987 block->jump_in[0].vaddr = start;
8988 block->jump_in[0].addr = beginning;
4149788d 8989 return 0;
8990 }
8991 else if (f1_hack && hack_addr == 0) {
8992 void *beginning = start_block();
4149788d 8993 emit_movimm(start, 0);
8994 emit_writeword(0, &hack_addr);
8995 emit_readword(&psxRegs.GPR.n.sp, 0);
8996 emit_readptr(&mem_rtab, 1);
8997 emit_shrimm(0, 12, 2);
8998 emit_readptr_dualindexedx_ptrlen(1, 2, 1);
8999 emit_addimm(0, 0x18, 0);
9000 emit_adds_ptr(1, 1, 1);
9001 emit_ldr_dualindexed(1, 0, 0);
9002 emit_writeword(0, &psxRegs.GPR.r[26]); // lw k0, 0x18(sp)
104df9d3 9003 emit_far_call(ndrc_get_addr_ht);
4149788d 9004 emit_jmpreg(0); // jr k0
9005 literal_pool(0);
9006 end_block(beginning);
9007
104df9d3 9008 struct block_info *block = new_block_info(start, 4, NULL, NULL, beginning, 1);
9009 block->jump_in[0].vaddr = start;
9010 block->jump_in[0].addr = beginning;
4149788d 9011 SysPrintf("F1 hack to %08x\n", start);
9012 return 0;
9013 }
9014
42eb665e 9015 cycle_multiplier_active = get_cycle_multiplier();
4149788d 9016
9017 source = get_source_start(start, &pagelimit);
9018 if (source == NULL) {
9019 if (addr != hack_addr) {
42eb665e 9020 SysPrintf("Compile at bogus memory address: %08x, ra=%x\n",
9021 addr, psxRegs.GPR.n.ra);
4149788d 9022 hack_addr = addr;
9023 }
9024 //abort();
9025 return -1;
9026 }
9027
9028 /* Pass 1: disassemble */
9029 /* Pass 2: register dependencies, branch targets */
9030 /* Pass 3: register allocation */
9031 /* Pass 4: branch dependencies */
9032 /* Pass 5: pre-alloc */
9033 /* Pass 6: optimize clean/dirty state */
9034 /* Pass 7: flag 32-bit registers */
9035 /* Pass 8: assembly */
9036 /* Pass 9: linker */
9037 /* Pass 10: garbage collection / free memory */
9038
9039 /* Pass 1 disassembly */
9040
9041 pass1_disassemble(pagelimit);
9042
9043 int clear_hack_addr = apply_hacks();
9044
9045 /* Pass 2 - Register dependencies and branch targets */
9046
9047 pass2_unneeded_regs(0,slen-1,0);
9048
f9e9616e 9049 pass2a_unneeded_other();
9050
4149788d 9051 /* Pass 3 - Register allocation */
9052
9053 pass3_register_alloc(addr);
9054
9055 /* Pass 4 - Cull unused host registers */
9056
9057 pass4_cull_unused_regs();
9058
9059 /* Pass 5 - Pre-allocate registers */
9060
9061 pass5a_preallocate1();
9062 pass5b_preallocate2();
9f51b4b9 9063
57871462 9064 /* Pass 6 - Optimize clean/dirty state */
4149788d 9065 pass6_clean_registers(0, slen-1, 1);
9f51b4b9 9066
33a1eda1 9067 /* Pass 7 */
04fd948a 9068 for (i=slen-1;i>=0;i--)
9069 {
cf95b4f0 9070 if(dops[i].itype==CJUMP||dops[i].itype==SJUMP)
04fd948a 9071 {
9072 // Conditional branch
9073 if((source[i]>>16)!=0x1000&&i<slen-2) {
9074 // Mark this address as a branch target since it may be called
9075 // upon return from interrupt
cf95b4f0 9076 dops[i+2].bt=1;
04fd948a 9077 }
9078 }
9079 }
57871462 9080
57871462 9081 /* Pass 8 - Assembly */
9082 linkcount=0;stubcount=0;
4149788d 9083 is_delayslot=0;
57871462 9084 u_int dirty_pre=0;
d148d265 9085 void *beginning=start_block();
df4dc2b1 9086 void *instr_addr0_override = NULL;
4bdc30ab 9087 int ds = 0;
9ad4d757 9088
9ad4d757 9089 if (start == 0x80030000) {
3968e69e 9090 // nasty hack for the fastbios thing
96186eba 9091 // override block entry to this code
df4dc2b1 9092 instr_addr0_override = out;
9ad4d757 9093 emit_movimm(start,0);
96186eba 9094 // abuse io address var as a flag that we
9095 // have already returned here once
643aeae3 9096 emit_readword(&address,1);
9097 emit_writeword(0,&pcaddr);
9098 emit_writeword(0,&address);
9ad4d757 9099 emit_cmp(0,1);
3968e69e 9100 #ifdef __aarch64__
9101 emit_jeq(out + 4*2);
2a014d73 9102 emit_far_jump(new_dyna_leave);
3968e69e 9103 #else
643aeae3 9104 emit_jne(new_dyna_leave);
3968e69e 9105 #endif
9ad4d757 9106 }
57871462 9107 for(i=0;i<slen;i++)
9108 {
9de8a0c3 9109 __builtin_prefetch(regs[i+1].regmap);
670c0f22 9110 check_regmap(regmap_pre[i]);
9111 check_regmap(regs[i].regmap_entry);
9112 check_regmap(regs[i].regmap);
57871462 9113 //if(ds) printf("ds: ");
4600ba03 9114 disassemble_inst(i);
57871462 9115 if(ds) {
9116 ds=0; // Skip delay slot
cf95b4f0 9117 if(dops[i].bt) assem_debug("OOPS - branch into delay slot\n");
df4dc2b1 9118 instr_addr[i] = NULL;
57871462 9119 } else {
ffb0b9e0 9120 speculate_register_values(i);
57871462 9121 #ifndef DESTRUCTIVE_WRITEBACK
fe807a8a 9122 if (i < 2 || !dops[i-2].is_ujump)
57871462 9123 {
ad49de89 9124 wb_valid(regmap_pre[i],regs[i].regmap_entry,dirty_pre,regs[i].wasdirty,unneeded_reg[i]);
57871462 9125 }
fe807a8a 9126 if((dops[i].itype==CJUMP||dops[i].itype==SJUMP)) {
f776eb14 9127 dirty_pre=branch_regs[i].dirty;
9128 }else{
f776eb14 9129 dirty_pre=regs[i].dirty;
9130 }
57871462 9131 #endif
9132 // write back
fe807a8a 9133 if (i < 2 || !dops[i-2].is_ujump)
57871462 9134 {
ad49de89 9135 wb_invalidate(regmap_pre[i],regs[i].regmap_entry,regs[i].wasdirty,unneeded_reg[i]);
57871462 9136 loop_preload(regmap_pre[i],regs[i].regmap_entry);
9137 }
9138 // branch target entry point
df4dc2b1 9139 instr_addr[i] = out;
57871462 9140 assem_debug("<->\n");
277718fa 9141 drc_dbg_emit_do_cmp(i, cinfo[i].ccadj);
7f94b097 9142 if (clear_hack_addr) {
9143 emit_movimm(0, 0);
9144 emit_writeword(0, &hack_addr);
9145 clear_hack_addr = 0;
9146 }
dd114d7d 9147
57871462 9148 // load regs
9149 if(regs[i].regmap_entry[HOST_CCREG]==CCREG&&regs[i].regmap[HOST_CCREG]!=CCREG)
ad49de89 9150 wb_register(CCREG,regs[i].regmap_entry,regs[i].wasdirty);
cf95b4f0 9151 load_regs(regs[i].regmap_entry,regs[i].regmap,dops[i].rs1,dops[i].rs2);
57871462 9152 address_generation(i,&regs[i],regs[i].regmap_entry);
ad49de89 9153 load_consts(regmap_pre[i],regs[i].regmap,i);
fe807a8a 9154 if(dops[i].is_jump)
57871462 9155 {
9156 // Load the delay slot registers if necessary
cf95b4f0 9157 if(dops[i+1].rs1!=dops[i].rs1&&dops[i+1].rs1!=dops[i].rs2&&(dops[i+1].rs1!=dops[i].rt1||dops[i].rt1==0))
9158 load_regs(regs[i].regmap_entry,regs[i].regmap,dops[i+1].rs1,dops[i+1].rs1);
9159 if(dops[i+1].rs2!=dops[i+1].rs1&&dops[i+1].rs2!=dops[i].rs1&&dops[i+1].rs2!=dops[i].rs2&&(dops[i+1].rs2!=dops[i].rt1||dops[i].rt1==0))
9160 load_regs(regs[i].regmap_entry,regs[i].regmap,dops[i+1].rs2,dops[i+1].rs2);
37387d8b 9161 if (ram_offset && (dops[i+1].is_load || dops[i+1].is_store))
53358c1d 9162 load_reg(regs[i].regmap_entry,regs[i].regmap,ROREG);
37387d8b 9163 if (dops[i+1].is_store)
53358c1d 9164 load_reg(regs[i].regmap_entry,regs[i].regmap,INVCP);
57871462 9165 }
9166 else if(i+1<slen)
9167 {
9168 // Preload registers for following instruction
cf95b4f0 9169 if(dops[i+1].rs1!=dops[i].rs1&&dops[i+1].rs1!=dops[i].rs2)
9170 if(dops[i+1].rs1!=dops[i].rt1&&dops[i+1].rs1!=dops[i].rt2)
9171 load_regs(regs[i].regmap_entry,regs[i].regmap,dops[i+1].rs1,dops[i+1].rs1);
9172 if(dops[i+1].rs2!=dops[i+1].rs1&&dops[i+1].rs2!=dops[i].rs1&&dops[i+1].rs2!=dops[i].rs2)
9173 if(dops[i+1].rs2!=dops[i].rt1&&dops[i+1].rs2!=dops[i].rt2)
9174 load_regs(regs[i].regmap_entry,regs[i].regmap,dops[i+1].rs2,dops[i+1].rs2);
57871462 9175 }
9176 // TODO: if(is_ooo(i)) address_generation(i+1);
9a3ccfeb 9177 if (!dops[i].is_jump || dops[i].itype == CJUMP)
53358c1d 9178 load_reg(regs[i].regmap_entry,regs[i].regmap,CCREG);
37387d8b 9179 if (ram_offset && (dops[i].is_load || dops[i].is_store))
53358c1d 9180 load_reg(regs[i].regmap_entry,regs[i].regmap,ROREG);
37387d8b 9181 if (dops[i].is_store)
53358c1d 9182 load_reg(regs[i].regmap_entry,regs[i].regmap,INVCP);
2330734f 9183
277718fa 9184 ds = assemble(i, &regs[i], cinfo[i].ccadj);
2330734f 9185
4f13a577 9186 drc_dbg_emit_wb_dirtys(i, &regs[i]);
fe807a8a 9187 if (dops[i].is_ujump)
57871462 9188 literal_pool(1024);
9189 else
9190 literal_pool_jumpover(256);
9191 }
9192 }
3d680478 9193
9194 assert(slen > 0);
cf95b4f0 9195 if (slen > 0 && dops[slen-1].itype == INTCALL) {
3d680478 9196 // no ending needed for this block since INTCALL never returns
9197 }
57871462 9198 // If the block did not end with an unconditional branch,
9199 // add a jump to the next instruction.
3d680478 9200 else if (i > 1) {
4bdc30ab 9201 if (!dops[i-2].is_ujump) {
fe807a8a 9202 assert(!dops[i-1].is_jump);
57871462 9203 assert(i==slen);
cf95b4f0 9204 if(dops[i-2].itype!=CJUMP&&dops[i-2].itype!=SJUMP) {
ad49de89 9205 store_regs_bt(regs[i-1].regmap,regs[i-1].dirty,start+i*4);
57871462 9206 if(regs[i-1].regmap[HOST_CCREG]!=CCREG)
9207 emit_loadreg(CCREG,HOST_CCREG);
277718fa 9208 emit_addimm(HOST_CCREG, cinfo[i-1].ccadj + CLOCK_ADJUST(1), HOST_CCREG);
57871462 9209 }
fe807a8a 9210 else
57871462 9211 {
ad49de89 9212 store_regs_bt(branch_regs[i-2].regmap,branch_regs[i-2].dirty,start+i*4);
57871462 9213 assert(branch_regs[i-2].regmap[HOST_CCREG]==CCREG);
9214 }
643aeae3 9215 add_to_linker(out,start+i*4,0);
57871462 9216 emit_jmp(0);
9217 }
9218 }
9219 else
9220 {
9221 assert(i>0);
fe807a8a 9222 assert(!dops[i-1].is_jump);
ad49de89 9223 store_regs_bt(regs[i-1].regmap,regs[i-1].dirty,start+i*4);
57871462 9224 if(regs[i-1].regmap[HOST_CCREG]!=CCREG)
9225 emit_loadreg(CCREG,HOST_CCREG);
277718fa 9226 emit_addimm(HOST_CCREG, cinfo[i-1].ccadj + CLOCK_ADJUST(1), HOST_CCREG);
643aeae3 9227 add_to_linker(out,start+i*4,0);
57871462 9228 emit_jmp(0);
9229 }
9230
57871462 9231 // Stubs
a5cd72d0 9232 for(i = 0; i < stubcount; i++)
57871462 9233 {
b14b6a8f 9234 switch(stubs[i].type)
57871462 9235 {
9236 case LOADB_STUB:
9237 case LOADH_STUB:
9238 case LOADW_STUB:
57871462 9239 case LOADBU_STUB:
9240 case LOADHU_STUB:
9241 do_readstub(i);break;
9242 case STOREB_STUB:
9243 case STOREH_STUB:
9244 case STOREW_STUB:
57871462 9245 do_writestub(i);break;
9246 case CC_STUB:
9247 do_ccstub(i);break;
9248 case INVCODE_STUB:
9249 do_invstub(i);break;
57871462 9250 case STORELR_STUB:
9251 do_unalignedwritestub(i);break;
a5cd72d0 9252 case OVERFLOW_STUB:
9253 do_overflowstub(i); break;
277718fa 9254 case ALIGNMENT_STUB:
9255 do_alignmentstub(i); break;
a5cd72d0 9256 default:
9257 assert(0);
57871462 9258 }
9259 }
9260
9ad4d757 9261 if (instr_addr0_override)
9262 instr_addr[0] = instr_addr0_override;
9263
93c0345b 9264#if 0
9265 /* check for improper expiration */
9266 for (i = 0; i < ARRAY_SIZE(jumps); i++) {
9267 int j;
9268 if (!jumps[i])
9269 continue;
9270 for (j = 0; j < jumps[i]->count; j++)
9271 assert(jumps[i]->e[j].stub < beginning || (u_char *)jumps[i]->e[j].stub > out);
9272 }
9273#endif
9274
57871462 9275 /* Pass 9 - Linker */
9276 for(i=0;i<linkcount;i++)
9277 {
643aeae3 9278 assem_debug("%p -> %8x\n",link_addr[i].addr,link_addr[i].target);
57871462 9279 literal_pool(64);
104df9d3 9280 if (!link_addr[i].internal)
57871462 9281 {
643aeae3 9282 void *stub = out;
9283 void *addr = check_addr(link_addr[i].target);
9284 emit_extjump(link_addr[i].addr, link_addr[i].target);
9285 if (addr) {
9286 set_jump_target(link_addr[i].addr, addr);
104df9d3 9287 ndrc_add_jump_out(link_addr[i].target,stub);
57871462 9288 }
643aeae3 9289 else
9290 set_jump_target(link_addr[i].addr, stub);
57871462 9291 }
9292 else
9293 {
9294 // Internal branch
643aeae3 9295 int target=(link_addr[i].target-start)>>2;
57871462 9296 assert(target>=0&&target<slen);
9297 assert(instr_addr[target]);
9298 //#ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
643aeae3 9299 //set_jump_target_fillslot(link_addr[i].addr,instr_addr[target],link_addr[i].ext>>1);
57871462 9300 //#else
643aeae3 9301 set_jump_target(link_addr[i].addr, instr_addr[target]);
57871462 9302 //#endif
9303 }
9304 }
3d680478 9305
9306 u_int source_len = slen*4;
cf95b4f0 9307 if (dops[slen-1].itype == INTCALL && source_len > 4)
3d680478 9308 // no need to treat the last instruction as compiled
9309 // as interpreter fully handles it
9310 source_len -= 4;
9311
9312 if ((u_char *)copy + source_len > (u_char *)shadow + sizeof(shadow))
9313 copy = shadow;
9314
57871462 9315 // External Branch Targets (jump_in)
104df9d3 9316 int jump_in_count = 1;
9317 assert(instr_addr[0]);
9318 for (i = 1; i < slen; i++)
9319 {
9320 if (dops[i].bt && instr_addr[i])
9321 jump_in_count++;
9322 }
9323
9324 struct block_info *block =
9325 new_block_info(start, slen * 4, source, copy, beginning, jump_in_count);
9326 block->reg_sv_flags = state_rflags;
9327
9328 int jump_in_i = 0;
9329 for (i = 0; i < slen; i++)
57871462 9330 {
104df9d3 9331 if ((i == 0 || dops[i].bt) && instr_addr[i])
57871462 9332 {
104df9d3 9333 assem_debug("%p (%d) <- %8x\n", instr_addr[i], i, start + i*4);
9334 u_int vaddr = start + i*4;
9335
9336 literal_pool(256);
9337 void *entry = out;
9338 load_regs_entry(i);
9339 if (entry == out)
9340 entry = instr_addr[i];
9341 else
9342 emit_jmp(instr_addr[i]);
9343
9344 block->jump_in[jump_in_i].vaddr = vaddr;
9345 block->jump_in[jump_in_i].addr = entry;
9346 jump_in_i++;
57871462 9347 }
9348 }
104df9d3 9349 assert(jump_in_i == jump_in_count);
9350 hash_table_add(block->jump_in[0].vaddr, block->jump_in[0].addr);
57871462 9351 // Write out the literal pool if necessary
9352 literal_pool(0);
9353 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
9354 // Align code
9355 if(((u_int)out)&7) emit_addnop(13);
9356 #endif
01d26796 9357 assert(out - (u_char *)beginning < MAX_OUTPUT_BLOCK_SIZE);
643aeae3 9358 //printf("shadow buffer: %p-%p\n",copy,(u_char *)copy+slen*4);
3d680478 9359 memcpy(copy, source, source_len);
9360 copy += source_len;
9f51b4b9 9361
d148d265 9362 end_block(beginning);
9f51b4b9 9363
57871462 9364 // If we're within 256K of the end of the buffer,
9365 // start over from the beginning. (Is 256K enough?)
2a014d73 9366 if (out > ndrc->translation_cache + sizeof(ndrc->translation_cache) - MAX_OUTPUT_BLOCK_SIZE)
9367 out = ndrc->translation_cache;
9f51b4b9 9368
57871462 9369 // Trap writes to any of the pages we compiled
104df9d3 9370 mark_invalid_code(start, slen*4, 0);
9f51b4b9 9371
57871462 9372 /* Pass 10 - Free memory by expiring oldest blocks */
9f51b4b9 9373
4149788d 9374 pass10_expire_blocks();
9375
37387d8b 9376#ifdef ASSEM_PRINT
9377 fflush(stdout);
9378#endif
ece032e6 9379 stat_inc(stat_bc_direct);
57871462 9380 return 0;
9381}
b9b61529 9382
9383// vim:shiftwidth=2:expandtab
ARM optimized PCSX fork