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drc: add apparently missing ROREG loading
[pcsx_rearmed.git] / libpcsxcore / new_dynarec / new_dynarec.c
CommitLineData
57871462 1/* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
2 * Mupen64plus - new_dynarec.c *
20d507ba 3 * Copyright (C) 2009-2011 Ari64 *
57871462 4 * *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
9 * *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
14 * *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. *
19 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */
20
21#include <stdlib.h>
22#include <stdint.h> //include for uint64_t
23#include <assert.h>
d848b60a 24#include <errno.h>
4600ba03 25#include <sys/mman.h>
d148d265 26#ifdef __MACH__
27#include <libkern/OSCacheControl.h>
28#endif
1e212a25 29#ifdef _3DS
30#include <3ds_utils.h>
31#endif
57871462 32
d148d265 33#include "new_dynarec_config.h"
3968e69e 34#include "../psxhle.h"
35#include "../psxinterpreter.h"
81dbbf4c 36#include "../gte.h"
37#include "emu_if.h" // emulator interface
57871462 38
d1e4ebd9 39#define noinline __attribute__((noinline,noclone))
b14b6a8f 40#ifndef ARRAY_SIZE
41#define ARRAY_SIZE(x) (sizeof(x) / sizeof(x[0]))
42#endif
e3c6bdb5 43#ifndef min
44#define min(a, b) ((b) < (a) ? (b) : (a))
45#endif
32631e6a 46#ifndef max
47#define max(a, b) ((b) > (a) ? (b) : (a))
48#endif
b14b6a8f 49
4600ba03 50//#define DISASM
32631e6a 51//#define ASSEM_PRINT
d1150cd6 52//#define REG_ALLOC_PRINT
32631e6a 53
54#ifdef ASSEM_PRINT
55#define assem_debug printf
56#else
4600ba03 57#define assem_debug(...)
32631e6a 58#endif
59//#define inv_debug printf
4600ba03 60#define inv_debug(...)
57871462 61
62#ifdef __i386__
63#include "assem_x86.h"
64#endif
65#ifdef __x86_64__
66#include "assem_x64.h"
67#endif
68#ifdef __arm__
69#include "assem_arm.h"
70#endif
be516ebe 71#ifdef __aarch64__
72#include "assem_arm64.h"
73#endif
57871462 74
81dbbf4c 75#define RAM_SIZE 0x200000
57871462 76#define MAXBLOCK 4096
77#define MAX_OUTPUT_BLOCK_SIZE 262144
2573466a 78
66ea165f 79#ifdef VITA
80// apparently Vita has a 16MB limit, so either we cut tc in half,
81// or use this hack (it's a hack because tc size was designed to be power-of-2)
82#define TC_REDUCE_BYTES 4096
83#else
84#define TC_REDUCE_BYTES 0
85#endif
86
2a014d73 87struct ndrc_mem
88{
66ea165f 89 u_char translation_cache[(1 << TARGET_SIZE_2) - TC_REDUCE_BYTES];
2a014d73 90 struct
91 {
92 struct tramp_insns ops[2048 / sizeof(struct tramp_insns)];
93 const void *f[2048 / sizeof(void *)];
94 } tramp;
95};
96
97#ifdef BASE_ADDR_DYNAMIC
98static struct ndrc_mem *ndrc;
99#else
100static struct ndrc_mem ndrc_ __attribute__((aligned(4096)));
101static struct ndrc_mem *ndrc = &ndrc_;
102#endif
103
b14b6a8f 104// stubs
105enum stub_type {
106 CC_STUB = 1,
107 FP_STUB = 2,
108 LOADB_STUB = 3,
109 LOADH_STUB = 4,
110 LOADW_STUB = 5,
111 LOADD_STUB = 6,
112 LOADBU_STUB = 7,
113 LOADHU_STUB = 8,
114 STOREB_STUB = 9,
115 STOREH_STUB = 10,
116 STOREW_STUB = 11,
117 STORED_STUB = 12,
118 STORELR_STUB = 13,
119 INVCODE_STUB = 14,
120};
121
6cc8d23c 122// regmap_pre[i] - regs before [i] insn starts; dirty things here that
123// don't match .regmap will be written back
124// [i].regmap_entry - regs that must be set up if someone jumps here
125// [i].regmap - regs [i] insn will read/(over)write
2acc46cd 126// branch_regs[i].* - same as above but for branches, takes delay slot into account
57871462 127struct regstat
128{
6cc8d23c 129 signed char regmap_entry[HOST_REGS];
57871462 130 signed char regmap[HOST_REGS];
57871462 131 uint64_t wasdirty;
132 uint64_t dirty;
133 uint64_t u;
24058131 134 u_int wasconst; // before; for example 'lw r2, (r2)' wasconst is true
135 u_int isconst; // ... but isconst is false when r2 is known
8575a877 136 u_int loadedconst; // host regs that have constants loaded
137 u_int waswritten; // MIPS regs that were used as store base before
57871462 138};
139
de5a60c3 140// note: asm depends on this layout
57871462 141struct ll_entry
142{
143 u_int vaddr;
de5a60c3 144 u_int reg_sv_flags;
57871462 145 void *addr;
146 struct ll_entry *next;
147};
148
df4dc2b1 149struct ht_entry
150{
151 u_int vaddr[2];
152 void *tcaddr[2];
153};
154
b14b6a8f 155struct code_stub
156{
157 enum stub_type type;
158 void *addr;
159 void *retaddr;
160 u_int a;
161 uintptr_t b;
162 uintptr_t c;
163 u_int d;
164 u_int e;
165};
166
643aeae3 167struct link_entry
168{
169 void *addr;
170 u_int target;
171 u_int ext;
172};
173
cf95b4f0 174static struct decoded_insn
175{
176 u_char itype;
177 u_char opcode;
178 u_char opcode2;
179 u_char rs1;
180 u_char rs2;
181 u_char rt1;
182 u_char rt2;
183 u_char lt1;
184 u_char bt:1;
cf95b4f0 185 u_char ooo:1;
186 u_char is_ds:1;
fe807a8a 187 u_char is_jump:1;
188 u_char is_ujump:1;
37387d8b 189 u_char is_load:1;
190 u_char is_store:1;
cf95b4f0 191} dops[MAXBLOCK];
192
e2b5e7aa 193 // used by asm:
194 u_char *out;
df4dc2b1 195 struct ht_entry hash_table[65536] __attribute__((aligned(16)));
e2b5e7aa 196 struct ll_entry *jump_in[4096] __attribute__((aligned(16)));
197 struct ll_entry *jump_dirty[4096];
198
199 static struct ll_entry *jump_out[4096];
200 static u_int start;
201 static u_int *source;
202 static char insn[MAXBLOCK][10];
bedfea38 203 static uint64_t gte_rs[MAXBLOCK]; // gte: 32 data and 32 ctl regs
204 static uint64_t gte_rt[MAXBLOCK];
205 static uint64_t gte_unneeded[MAXBLOCK];
ffb0b9e0 206 static u_int smrv[32]; // speculated MIPS register values
207 static u_int smrv_strong; // mask or regs that are likely to have correct values
208 static u_int smrv_weak; // same, but somewhat less likely
209 static u_int smrv_strong_next; // same, but after current insn executes
210 static u_int smrv_weak_next;
e2b5e7aa 211 static int imm[MAXBLOCK];
212 static u_int ba[MAXBLOCK];
e2b5e7aa 213 static uint64_t unneeded_reg[MAXBLOCK];
e2b5e7aa 214 static uint64_t branch_unneeded_reg[MAXBLOCK];
6cc8d23c 215 // see 'struct regstat' for a description
2330734f 216 static signed char regmap_pre[MAXBLOCK][HOST_REGS];
40fca85b 217 // contains 'real' consts at [i] insn, but may differ from what's actually
218 // loaded in host reg as 'final' value is always loaded, see get_final_value()
219 static uint32_t current_constmap[HOST_REGS];
220 static uint32_t constmap[MAXBLOCK][HOST_REGS];
956f3129 221 static struct regstat regs[MAXBLOCK];
222 static struct regstat branch_regs[MAXBLOCK];
e2b5e7aa 223 static signed char minimum_free_regs[MAXBLOCK];
224 static u_int needed_reg[MAXBLOCK];
225 static u_int wont_dirty[MAXBLOCK];
226 static u_int will_dirty[MAXBLOCK];
227 static int ccadj[MAXBLOCK];
228 static int slen;
df4dc2b1 229 static void *instr_addr[MAXBLOCK];
643aeae3 230 static struct link_entry link_addr[MAXBLOCK];
e2b5e7aa 231 static int linkcount;
b14b6a8f 232 static struct code_stub stubs[MAXBLOCK*3];
e2b5e7aa 233 static int stubcount;
234 static u_int literals[1024][2];
235 static int literalcount;
236 static int is_delayslot;
e2b5e7aa 237 static char shadow[1048576] __attribute__((aligned(16)));
238 static void *copy;
239 static int expirep;
240 static u_int stop_after_jal;
7f94b097 241 static u_int f1_hack;
e2b5e7aa 242
243 int new_dynarec_hacks;
d62c125a 244 int new_dynarec_hacks_pergame;
32631e6a 245 int new_dynarec_hacks_old;
e2b5e7aa 246 int new_dynarec_did_compile;
687b4580 247
d62c125a 248 #define HACK_ENABLED(x) ((new_dynarec_hacks | new_dynarec_hacks_pergame) & (x))
249
687b4580 250 extern int cycle_count; // ... until end of the timeslice, counts -N -> 0
251 extern int last_count; // last absolute target, often = next_interupt
252 extern int pcaddr;
253 extern int pending_exception;
254 extern int branch_target;
37387d8b 255 extern uintptr_t ram_offset;
d1e4ebd9 256 extern uintptr_t mini_ht[32][2];
57871462 257 extern u_char restore_candidate[512];
57871462 258
259 /* registers that may be allocated */
260 /* 1-31 gpr */
7c3a5182 261#define LOREG 32 // lo
262#define HIREG 33 // hi
00fa9369 263//#define FSREG 34 // FPU status (FCSR)
57871462 264#define CSREG 35 // Coprocessor status
265#define CCREG 36 // Cycle count
266#define INVCP 37 // Pointer to invalid_code
1edfcc68 267//#define MMREG 38 // Pointer to memory_map
37387d8b 268#define ROREG 39 // ram offset (if rdram!=0x80000000)
619e5ded 269#define TEMPREG 40
270#define FTEMP 40 // FPU temporary register
271#define PTEMP 41 // Prefetch temporary register
1edfcc68 272//#define TLREG 42 // TLB mapping offset
619e5ded 273#define RHASH 43 // Return address hash
274#define RHTBL 44 // Return address hash table address
275#define RTEMP 45 // JR/JALR address register
276#define MAXREG 45
277#define AGEN1 46 // Address generation temporary register
1edfcc68 278//#define AGEN2 47 // Address generation temporary register
279//#define MGEN1 48 // Maptable address generation temporary register
280//#define MGEN2 49 // Maptable address generation temporary register
619e5ded 281#define BTREG 50 // Branch target temporary register
57871462 282
283 /* instruction types */
284#define NOP 0 // No operation
285#define LOAD 1 // Load
286#define STORE 2 // Store
287#define LOADLR 3 // Unaligned load
288#define STORELR 4 // Unaligned store
9f51b4b9 289#define MOV 5 // Move
57871462 290#define ALU 6 // Arithmetic/logic
291#define MULTDIV 7 // Multiply/divide
292#define SHIFT 8 // Shift by register
293#define SHIFTIMM 9// Shift by immediate
294#define IMM16 10 // 16-bit immediate
295#define RJUMP 11 // Unconditional jump to register
296#define UJUMP 12 // Unconditional jump
297#define CJUMP 13 // Conditional branch (BEQ/BNE/BGTZ/BLEZ)
298#define SJUMP 14 // Conditional branch (regimm format)
299#define COP0 15 // Coprocessor 0
300#define COP1 16 // Coprocessor 1
301#define C1LS 17 // Coprocessor 1 load/store
ad49de89 302//#define FJUMP 18 // Conditional branch (floating point)
00fa9369 303//#define FLOAT 19 // Floating point unit
304//#define FCONV 20 // Convert integer to float
305//#define FCOMP 21 // Floating point compare (sets FSREG)
d1150cd6 306#define SYSCALL 22// SYSCALL,BREAK
57871462 307#define OTHER 23 // Other
308#define SPAN 24 // Branch/delay slot spans 2 pages
309#define NI 25 // Not implemented
7139f3c8 310#define HLECALL 26// PCSX fake opcodes for HLE
b9b61529 311#define COP2 27 // Coprocessor 2 move
312#define C2LS 28 // Coprocessor 2 load/store
313#define C2OP 29 // Coprocessor 2 operation
1e973cb0 314#define INTCALL 30// Call interpreter to handle rare corner cases
57871462 315
57871462 316 /* branch codes */
317#define TAKEN 1
318#define NOTTAKEN 2
319#define NULLDS 3
320
7c3a5182 321#define DJT_1 (void *)1l // no function, just a label in assem_debug log
322#define DJT_2 (void *)2l
323
57871462 324// asm linkage
3968e69e 325int new_recompile_block(u_int addr);
57871462 326void *get_addr_ht(u_int vaddr);
327void invalidate_block(u_int block);
328void invalidate_addr(u_int addr);
329void remove_hash(int vaddr);
57871462 330void dyna_linker();
331void dyna_linker_ds();
332void verify_code();
57871462 333void verify_code_ds();
334void cc_interrupt();
335void fp_exception();
336void fp_exception_ds();
d1150cd6 337void jump_syscall (u_int u0, u_int u1, u_int pc);
338void jump_syscall_ds(u_int u0, u_int u1, u_int pc);
339void jump_break (u_int u0, u_int u1, u_int pc);
340void jump_break_ds(u_int u0, u_int u1, u_int pc);
3968e69e 341void jump_to_new_pc();
81dbbf4c 342void call_gteStall();
7139f3c8 343void new_dyna_leave();
57871462 344
57871462 345// Needed by assembler
2330734f 346static void wb_register(signed char r, const signed char regmap[], uint64_t dirty);
347static void wb_dirtys(const signed char i_regmap[], uint64_t i_dirty);
348static void wb_needed_dirtys(const signed char i_regmap[], uint64_t i_dirty, int addr);
349static void load_all_regs(const signed char i_regmap[]);
350static void load_needed_regs(const signed char i_regmap[], const signed char next_regmap[]);
e2b5e7aa 351static void load_regs_entry(int t);
2330734f 352static void load_all_consts(const signed char regmap[], u_int dirty, int i);
81dbbf4c 353static u_int get_host_reglist(const signed char *regmap);
e2b5e7aa 354
3968e69e 355static int verify_dirty(const u_int *ptr);
e2b5e7aa 356static int get_final_value(int hr, int i, int *value);
b14b6a8f 357static void add_stub(enum stub_type type, void *addr, void *retaddr,
358 u_int a, uintptr_t b, uintptr_t c, u_int d, u_int e);
359static void add_stub_r(enum stub_type type, void *addr, void *retaddr,
81dbbf4c 360 int i, int addr_reg, const struct regstat *i_regs, int ccadj, u_int reglist);
643aeae3 361static void add_to_linker(void *addr, u_int target, int ext);
37387d8b 362static void *emit_fastpath_cmp_jump(int i, const struct regstat *i_regs,
363 int addr, int *offset_reg, int *addr_reg_override);
687b4580 364static void *get_direct_memhandler(void *table, u_int addr,
365 enum stub_type type, uintptr_t *addr_host);
32631e6a 366static void cop2_do_stall_check(u_int op, int i, const struct regstat *i_regs, u_int reglist);
687b4580 367static void pass_args(int a0, int a1);
2a014d73 368static void emit_far_jump(const void *f);
369static void emit_far_call(const void *f);
57871462 370
9c67c98f 371#ifdef VITA
372#include <psp2/kernel/sysmem.h>
373static int sceBlock;
374// note: this interacts with RetroArch's Vita bootstrap code: bootstrap/vita/sbrk.c
375extern int getVMBlock();
376int _newlib_vm_size_user = sizeof(*ndrc);
377#endif
378
d148d265 379static void mprotect_w_x(void *start, void *end, int is_x)
380{
381#ifdef NO_WRITE_EXEC
1e212a25 382 #if defined(VITA)
383 // *Open* enables write on all memory that was
384 // allocated by sceKernelAllocMemBlockForVM()?
385 if (is_x)
386 sceKernelCloseVMDomain();
387 else
388 sceKernelOpenVMDomain();
389 #else
d148d265 390 u_long mstart = (u_long)start & ~4095ul;
391 u_long mend = (u_long)end;
392 if (mprotect((void *)mstart, mend - mstart,
393 PROT_READ | (is_x ? PROT_EXEC : PROT_WRITE)) != 0)
394 SysPrintf("mprotect(%c) failed: %s\n", is_x ? 'x' : 'w', strerror(errno));
1e212a25 395 #endif
d148d265 396#endif
397}
398
399static void start_tcache_write(void *start, void *end)
400{
401 mprotect_w_x(start, end, 0);
402}
403
404static void end_tcache_write(void *start, void *end)
405{
919981d0 406#if defined(__arm__) || defined(__aarch64__)
d148d265 407 size_t len = (char *)end - (char *)start;
408 #if defined(__BLACKBERRY_QNX__)
409 msync(start, len, MS_SYNC | MS_CACHE_ONLY | MS_INVALIDATE_ICACHE);
410 #elif defined(__MACH__)
411 sys_cache_control(kCacheFunctionPrepareForExecution, start, len);
412 #elif defined(VITA)
1e212a25 413 sceKernelSyncVMDomain(sceBlock, start, len);
414 #elif defined(_3DS)
415 ctr_flush_invalidate_cache();
919981d0 416 #elif defined(__aarch64__)
417 // as of 2021, __clear_cache() is still broken on arm64
418 // so here is a custom one :(
419 clear_cache_arm64(start, end);
d148d265 420 #else
421 __clear_cache(start, end);
422 #endif
423 (void)len;
424#endif
425
426 mprotect_w_x(start, end, 1);
427}
428
429static void *start_block(void)
430{
431 u_char *end = out + MAX_OUTPUT_BLOCK_SIZE;
2a014d73 432 if (end > ndrc->translation_cache + sizeof(ndrc->translation_cache))
433 end = ndrc->translation_cache + sizeof(ndrc->translation_cache);
d148d265 434 start_tcache_write(out, end);
435 return out;
436}
437
438static void end_block(void *start)
439{
440 end_tcache_write(start, out);
441}
442
919981d0 443// also takes care of w^x mappings when patching code
444static u_int needs_clear_cache[1<<(TARGET_SIZE_2-17)];
445
446static void mark_clear_cache(void *target)
447{
448 uintptr_t offset = (u_char *)target - ndrc->translation_cache;
449 u_int mask = 1u << ((offset >> 12) & 31);
450 if (!(needs_clear_cache[offset >> 17] & mask)) {
451 char *start = (char *)((uintptr_t)target & ~4095l);
452 start_tcache_write(start, start + 4095);
453 needs_clear_cache[offset >> 17] |= mask;
454 }
455}
456
457// Clearing the cache is rather slow on ARM Linux, so mark the areas
458// that need to be cleared, and then only clear these areas once.
459static void do_clear_cache(void)
460{
461 int i, j;
462 for (i = 0; i < (1<<(TARGET_SIZE_2-17)); i++)
463 {
464 u_int bitmap = needs_clear_cache[i];
465 if (!bitmap)
466 continue;
467 for (j = 0; j < 32; j++)
468 {
469 u_char *start, *end;
470 if (!(bitmap & (1<<j)))
471 continue;
472
473 start = ndrc->translation_cache + i*131072 + j*4096;
474 end = start + 4095;
475 for (j++; j < 32; j++) {
476 if (!(bitmap & (1<<j)))
477 break;
478 end += 4096;
479 }
480 end_tcache_write(start, end);
481 }
482 needs_clear_cache[i] = 0;
483 }
484}
485
57871462 486//#define DEBUG_CYCLE_COUNT 1
487
b6e87b2b 488#define NO_CYCLE_PENALTY_THR 12
489
26bd3dad 490int cycle_multiplier = CYCLE_MULT_DEFAULT; // 100 for 1.0
a3203cf4 491int cycle_multiplier_override;
32631e6a 492int cycle_multiplier_old;
24058131 493static int cycle_multiplier_active;
4e9dcd7f 494
495static int CLOCK_ADJUST(int x)
496{
24058131 497 int m = cycle_multiplier_active;
498 int s = (x >> 31) | 1;
a3203cf4 499 return (x * m + s * 50) / 100;
4e9dcd7f 500}
501
4919de1e 502static int ds_writes_rjump_rs(int i)
503{
cf95b4f0 504 return dops[i].rs1 != 0 && (dops[i].rs1 == dops[i+1].rt1 || dops[i].rs1 == dops[i+1].rt2);
4919de1e 505}
506
94d23bb9 507static u_int get_page(u_int vaddr)
57871462 508{
0ce47d46 509 u_int page=vaddr&~0xe0000000;
510 if (page < 0x1000000)
511 page &= ~0x0e00000; // RAM mirrors
512 page>>=12;
57871462 513 if(page>2048) page=2048+(page&2047);
94d23bb9 514 return page;
515}
516
d25604ca 517// no virtual mem in PCSX
518static u_int get_vpage(u_int vaddr)
519{
520 return get_page(vaddr);
521}
94d23bb9 522
df4dc2b1 523static struct ht_entry *hash_table_get(u_int vaddr)
524{
525 return &hash_table[((vaddr>>16)^vaddr)&0xFFFF];
526}
527
528static void hash_table_add(struct ht_entry *ht_bin, u_int vaddr, void *tcaddr)
529{
530 ht_bin->vaddr[1] = ht_bin->vaddr[0];
531 ht_bin->tcaddr[1] = ht_bin->tcaddr[0];
532 ht_bin->vaddr[0] = vaddr;
533 ht_bin->tcaddr[0] = tcaddr;
534}
535
536// some messy ari64's code, seems to rely on unsigned 32bit overflow
537static int doesnt_expire_soon(void *tcaddr)
538{
539 u_int diff = (u_int)((u_char *)tcaddr - out) << (32-TARGET_SIZE_2);
540 return diff > (u_int)(0x60000000 + (MAX_OUTPUT_BLOCK_SIZE << (32-TARGET_SIZE_2)));
541}
542
94d23bb9 543// Get address from virtual address
544// This is called from the recompiled JR/JALR instructions
d1e4ebd9 545void noinline *get_addr(u_int vaddr)
94d23bb9 546{
547 u_int page=get_page(vaddr);
548 u_int vpage=get_vpage(vaddr);
57871462 549 struct ll_entry *head;
550 //printf("TRACE: count=%d next=%d (get_addr %x,page %d)\n",Count,next_interupt,vaddr,page);
551 head=jump_in[page];
552 while(head!=NULL) {
de5a60c3 553 if(head->vaddr==vaddr) {
643aeae3 554 //printf("TRACE: count=%d next=%d (get_addr match %x: %p)\n",Count,next_interupt,vaddr,head->addr);
df4dc2b1 555 hash_table_add(hash_table_get(vaddr), vaddr, head->addr);
57871462 556 return head->addr;
557 }
558 head=head->next;
559 }
560 head=jump_dirty[vpage];
561 while(head!=NULL) {
de5a60c3 562 if(head->vaddr==vaddr) {
643aeae3 563 //printf("TRACE: count=%d next=%d (get_addr match dirty %x: %p)\n",Count,next_interupt,vaddr,head->addr);
57871462 564 // Don't restore blocks which are about to expire from the cache
df4dc2b1 565 if (doesnt_expire_soon(head->addr))
566 if (verify_dirty(head->addr)) {
57871462 567 //printf("restore candidate: %x (%d) d=%d\n",vaddr,page,invalid_code[vaddr>>12]);
568 invalid_code[vaddr>>12]=0;
9be4ba64 569 inv_code_start=inv_code_end=~0;
57871462 570 if(vpage<2048) {
57871462 571 restore_candidate[vpage>>3]|=1<<(vpage&7);
572 }
573 else restore_candidate[page>>3]|=1<<(page&7);
df4dc2b1 574 struct ht_entry *ht_bin = hash_table_get(vaddr);
575 if (ht_bin->vaddr[0] == vaddr)
576 ht_bin->tcaddr[0] = head->addr; // Replace existing entry
57871462 577 else
df4dc2b1 578 hash_table_add(ht_bin, vaddr, head->addr);
579
57871462 580 return head->addr;
581 }
582 }
583 head=head->next;
584 }
585 //printf("TRACE: count=%d next=%d (get_addr no-match %x)\n",Count,next_interupt,vaddr);
586 int r=new_recompile_block(vaddr);
587 if(r==0) return get_addr(vaddr);
588 // Execute in unmapped page, generate pagefault execption
589 Status|=2;
590 Cause=(vaddr<<31)|0x8;
591 EPC=(vaddr&1)?vaddr-5:vaddr;
592 BadVAddr=(vaddr&~1);
593 Context=(Context&0xFF80000F)|((BadVAddr>>9)&0x007FFFF0);
594 EntryHi=BadVAddr&0xFFFFE000;
595 return get_addr_ht(0x80000000);
596}
597// Look up address in hash table first
598void *get_addr_ht(u_int vaddr)
599{
600 //printf("TRACE: count=%d next=%d (get_addr_ht %x)\n",Count,next_interupt,vaddr);
df4dc2b1 601 const struct ht_entry *ht_bin = hash_table_get(vaddr);
602 if (ht_bin->vaddr[0] == vaddr) return ht_bin->tcaddr[0];
603 if (ht_bin->vaddr[1] == vaddr) return ht_bin->tcaddr[1];
57871462 604 return get_addr(vaddr);
605}
606
6cc8d23c 607static void clear_all_regs(signed char regmap[])
57871462 608{
6cc8d23c 609 memset(regmap, -1, sizeof(regmap[0]) * HOST_REGS);
57871462 610}
611
d1e4ebd9 612static signed char get_reg(const signed char regmap[],int r)
57871462 613{
614 int hr;
615 for (hr=0;hr<HOST_REGS;hr++) if(hr!=EXCLUDE_REG&&regmap[hr]==r) return hr;
616 return -1;
617}
618
619// Find a register that is available for two consecutive cycles
d1e4ebd9 620static signed char get_reg2(signed char regmap1[], const signed char regmap2[], int r)
57871462 621{
622 int hr;
623 for (hr=0;hr<HOST_REGS;hr++) if(hr!=EXCLUDE_REG&&regmap1[hr]==r&&regmap2[hr]==r) return hr;
624 return -1;
625}
626
627int count_free_regs(signed char regmap[])
628{
629 int count=0;
630 int hr;
631 for(hr=0;hr<HOST_REGS;hr++)
632 {
633 if(hr!=EXCLUDE_REG) {
634 if(regmap[hr]<0) count++;
635 }
636 }
637 return count;
638}
639
640void dirty_reg(struct regstat *cur,signed char reg)
641{
642 int hr;
643 if(!reg) return;
644 for (hr=0;hr<HOST_REGS;hr++) {
645 if((cur->regmap[hr]&63)==reg) {
646 cur->dirty|=1<<hr;
647 }
648 }
649}
650
40fca85b 651static void set_const(struct regstat *cur, signed char reg, uint32_t value)
57871462 652{
653 int hr;
654 if(!reg) return;
655 for (hr=0;hr<HOST_REGS;hr++) {
656 if(cur->regmap[hr]==reg) {
657 cur->isconst|=1<<hr;
956f3129 658 current_constmap[hr]=value;
57871462 659 }
57871462 660 }
661}
662
40fca85b 663static void clear_const(struct regstat *cur, signed char reg)
57871462 664{
665 int hr;
666 if(!reg) return;
667 for (hr=0;hr<HOST_REGS;hr++) {
668 if((cur->regmap[hr]&63)==reg) {
669 cur->isconst&=~(1<<hr);
670 }
671 }
672}
673
40fca85b 674static int is_const(struct regstat *cur, signed char reg)
57871462 675{
676 int hr;
79c75f1b 677 if(reg<0) return 0;
57871462 678 if(!reg) return 1;
679 for (hr=0;hr<HOST_REGS;hr++) {
680 if((cur->regmap[hr]&63)==reg) {
681 return (cur->isconst>>hr)&1;
682 }
683 }
684 return 0;
685}
40fca85b 686
687static uint32_t get_const(struct regstat *cur, signed char reg)
57871462 688{
689 int hr;
690 if(!reg) return 0;
691 for (hr=0;hr<HOST_REGS;hr++) {
692 if(cur->regmap[hr]==reg) {
956f3129 693 return current_constmap[hr];
57871462 694 }
695 }
c43b5311 696 SysPrintf("Unknown constant in r%d\n",reg);
7c3a5182 697 abort();
57871462 698}
699
700// Least soon needed registers
701// Look at the next ten instructions and see which registers
702// will be used. Try not to reallocate these.
703void lsn(u_char hsn[], int i, int *preferred_reg)
704{
705 int j;
706 int b=-1;
707 for(j=0;j<9;j++)
708 {
709 if(i+j>=slen) {
710 j=slen-i-1;
711 break;
712 }
fe807a8a 713 if (dops[i+j].is_ujump)
57871462 714 {
715 // Don't go past an unconditonal jump
716 j++;
717 break;
718 }
719 }
720 for(;j>=0;j--)
721 {
cf95b4f0 722 if(dops[i+j].rs1) hsn[dops[i+j].rs1]=j;
723 if(dops[i+j].rs2) hsn[dops[i+j].rs2]=j;
724 if(dops[i+j].rt1) hsn[dops[i+j].rt1]=j;
725 if(dops[i+j].rt2) hsn[dops[i+j].rt2]=j;
726 if(dops[i+j].itype==STORE || dops[i+j].itype==STORELR) {
57871462 727 // Stores can allocate zero
cf95b4f0 728 hsn[dops[i+j].rs1]=j;
729 hsn[dops[i+j].rs2]=j;
57871462 730 }
37387d8b 731 if (ram_offset && (dops[i+j].is_load || dops[i+j].is_store))
732 hsn[ROREG] = j;
57871462 733 // On some architectures stores need invc_ptr
734 #if defined(HOST_IMM8)
37387d8b 735 if (dops[i+j].is_store)
736 hsn[INVCP] = j;
57871462 737 #endif
cf95b4f0 738 if(i+j>=0&&(dops[i+j].itype==UJUMP||dops[i+j].itype==CJUMP||dops[i+j].itype==SJUMP))
57871462 739 {
740 hsn[CCREG]=j;
741 b=j;
742 }
743 }
744 if(b>=0)
745 {
746 if(ba[i+b]>=start && ba[i+b]<(start+slen*4))
747 {
748 // Follow first branch
749 int t=(ba[i+b]-start)>>2;
750 j=7-b;if(t+j>=slen) j=slen-t-1;
751 for(;j>=0;j--)
752 {
cf95b4f0 753 if(dops[t+j].rs1) if(hsn[dops[t+j].rs1]>j+b+2) hsn[dops[t+j].rs1]=j+b+2;
754 if(dops[t+j].rs2) if(hsn[dops[t+j].rs2]>j+b+2) hsn[dops[t+j].rs2]=j+b+2;
755 //if(dops[t+j].rt1) if(hsn[dops[t+j].rt1]>j+b+2) hsn[dops[t+j].rt1]=j+b+2;
756 //if(dops[t+j].rt2) if(hsn[dops[t+j].rt2]>j+b+2) hsn[dops[t+j].rt2]=j+b+2;
57871462 757 }
758 }
759 // TODO: preferred register based on backward branch
760 }
761 // Delay slot should preferably not overwrite branch conditions or cycle count
fe807a8a 762 if (i > 0 && dops[i-1].is_jump) {
cf95b4f0 763 if(dops[i-1].rs1) if(hsn[dops[i-1].rs1]>1) hsn[dops[i-1].rs1]=1;
764 if(dops[i-1].rs2) if(hsn[dops[i-1].rs2]>1) hsn[dops[i-1].rs2]=1;
57871462 765 hsn[CCREG]=1;
766 // ...or hash tables
767 hsn[RHASH]=1;
768 hsn[RHTBL]=1;
769 }
770 // Coprocessor load/store needs FTEMP, even if not declared
37387d8b 771 if(dops[i].itype==C2LS) {
57871462 772 hsn[FTEMP]=0;
773 }
774 // Load L/R also uses FTEMP as a temporary register
cf95b4f0 775 if(dops[i].itype==LOADLR) {
57871462 776 hsn[FTEMP]=0;
777 }
b7918751 778 // Also SWL/SWR/SDL/SDR
cf95b4f0 779 if(dops[i].opcode==0x2a||dops[i].opcode==0x2e||dops[i].opcode==0x2c||dops[i].opcode==0x2d) {
57871462 780 hsn[FTEMP]=0;
781 }
57871462 782 // Don't remove the miniht registers
cf95b4f0 783 if(dops[i].itype==UJUMP||dops[i].itype==RJUMP)
57871462 784 {
785 hsn[RHASH]=0;
786 hsn[RHTBL]=0;
787 }
788}
789
790// We only want to allocate registers if we're going to use them again soon
791int needed_again(int r, int i)
792{
793 int j;
794 int b=-1;
795 int rn=10;
9f51b4b9 796
fe807a8a 797 if (i > 0 && dops[i-1].is_ujump)
57871462 798 {
799 if(ba[i-1]<start || ba[i-1]>start+slen*4-4)
800 return 0; // Don't need any registers if exiting the block
801 }
802 for(j=0;j<9;j++)
803 {
804 if(i+j>=slen) {
805 j=slen-i-1;
806 break;
807 }
fe807a8a 808 if (dops[i+j].is_ujump)
57871462 809 {
810 // Don't go past an unconditonal jump
811 j++;
812 break;
813 }
cf95b4f0 814 if(dops[i+j].itype==SYSCALL||dops[i+j].itype==HLECALL||dops[i+j].itype==INTCALL||((source[i+j]&0xfc00003f)==0x0d))
57871462 815 {
816 break;
817 }
818 }
819 for(;j>=1;j--)
820 {
cf95b4f0 821 if(dops[i+j].rs1==r) rn=j;
822 if(dops[i+j].rs2==r) rn=j;
57871462 823 if((unneeded_reg[i+j]>>r)&1) rn=10;
cf95b4f0 824 if(i+j>=0&&(dops[i+j].itype==UJUMP||dops[i+j].itype==CJUMP||dops[i+j].itype==SJUMP))
57871462 825 {
826 b=j;
827 }
828 }
b7217e13 829 if(rn<10) return 1;
581335b0 830 (void)b;
57871462 831 return 0;
832}
833
834// Try to match register allocations at the end of a loop with those
835// at the beginning
836int loop_reg(int i, int r, int hr)
837{
838 int j,k;
839 for(j=0;j<9;j++)
840 {
841 if(i+j>=slen) {
842 j=slen-i-1;
843 break;
844 }
fe807a8a 845 if (dops[i+j].is_ujump)
57871462 846 {
847 // Don't go past an unconditonal jump
848 j++;
849 break;
850 }
851 }
852 k=0;
853 if(i>0){
cf95b4f0 854 if(dops[i-1].itype==UJUMP||dops[i-1].itype==CJUMP||dops[i-1].itype==SJUMP)
57871462 855 k--;
856 }
857 for(;k<j;k++)
858 {
00fa9369 859 assert(r < 64);
860 if((unneeded_reg[i+k]>>r)&1) return hr;
cf95b4f0 861 if(i+k>=0&&(dops[i+k].itype==UJUMP||dops[i+k].itype==CJUMP||dops[i+k].itype==SJUMP))
57871462 862 {
863 if(ba[i+k]>=start && ba[i+k]<(start+i*4))
864 {
865 int t=(ba[i+k]-start)>>2;
866 int reg=get_reg(regs[t].regmap_entry,r);
867 if(reg>=0) return reg;
868 //reg=get_reg(regs[t+1].regmap_entry,r);
869 //if(reg>=0) return reg;
870 }
871 }
872 }
873 return hr;
874}
875
876
877// Allocate every register, preserving source/target regs
878void alloc_all(struct regstat *cur,int i)
879{
880 int hr;
9f51b4b9 881
57871462 882 for(hr=0;hr<HOST_REGS;hr++) {
883 if(hr!=EXCLUDE_REG) {
cf95b4f0 884 if(((cur->regmap[hr]&63)!=dops[i].rs1)&&((cur->regmap[hr]&63)!=dops[i].rs2)&&
885 ((cur->regmap[hr]&63)!=dops[i].rt1)&&((cur->regmap[hr]&63)!=dops[i].rt2))
57871462 886 {
887 cur->regmap[hr]=-1;
888 cur->dirty&=~(1<<hr);
889 }
890 // Don't need zeros
891 if((cur->regmap[hr]&63)==0)
892 {
893 cur->regmap[hr]=-1;
894 cur->dirty&=~(1<<hr);
895 }
896 }
897 }
898}
899
d1e4ebd9 900#ifndef NDEBUG
901static int host_tempreg_in_use;
902
903static void host_tempreg_acquire(void)
904{
905 assert(!host_tempreg_in_use);
906 host_tempreg_in_use = 1;
907}
908
909static void host_tempreg_release(void)
910{
911 host_tempreg_in_use = 0;
912}
913#else
914static void host_tempreg_acquire(void) {}
915static void host_tempreg_release(void) {}
916#endif
917
32631e6a 918#ifdef ASSEM_PRINT
8062d65a 919extern void gen_interupt();
920extern void do_insn_cmp();
d1e4ebd9 921#define FUNCNAME(f) { f, " " #f }
8062d65a 922static const struct {
d1e4ebd9 923 void *addr;
8062d65a 924 const char *name;
925} function_names[] = {
926 FUNCNAME(cc_interrupt),
927 FUNCNAME(gen_interupt),
928 FUNCNAME(get_addr_ht),
929 FUNCNAME(get_addr),
930 FUNCNAME(jump_handler_read8),
931 FUNCNAME(jump_handler_read16),
932 FUNCNAME(jump_handler_read32),
933 FUNCNAME(jump_handler_write8),
934 FUNCNAME(jump_handler_write16),
935 FUNCNAME(jump_handler_write32),
936 FUNCNAME(invalidate_addr),
3968e69e 937 FUNCNAME(jump_to_new_pc),
d1150cd6 938 FUNCNAME(jump_break),
939 FUNCNAME(jump_break_ds),
940 FUNCNAME(jump_syscall),
941 FUNCNAME(jump_syscall_ds),
81dbbf4c 942 FUNCNAME(call_gteStall),
8062d65a 943 FUNCNAME(new_dyna_leave),
944 FUNCNAME(pcsx_mtc0),
945 FUNCNAME(pcsx_mtc0_ds),
32631e6a 946#ifdef DRC_DBG
8062d65a 947 FUNCNAME(do_insn_cmp),
32631e6a 948#endif
3968e69e 949#ifdef __arm__
950 FUNCNAME(verify_code),
951#endif
8062d65a 952};
953
d1e4ebd9 954static const char *func_name(const void *a)
8062d65a 955{
956 int i;
957 for (i = 0; i < sizeof(function_names)/sizeof(function_names[0]); i++)
958 if (function_names[i].addr == a)
959 return function_names[i].name;
960 return "";
961}
962#else
963#define func_name(x) ""
964#endif
965
57871462 966#ifdef __i386__
967#include "assem_x86.c"
968#endif
969#ifdef __x86_64__
970#include "assem_x64.c"
971#endif
972#ifdef __arm__
973#include "assem_arm.c"
974#endif
be516ebe 975#ifdef __aarch64__
976#include "assem_arm64.c"
977#endif
57871462 978
2a014d73 979static void *get_trampoline(const void *f)
980{
981 size_t i;
982
983 for (i = 0; i < ARRAY_SIZE(ndrc->tramp.f); i++) {
984 if (ndrc->tramp.f[i] == f || ndrc->tramp.f[i] == NULL)
985 break;
986 }
987 if (i == ARRAY_SIZE(ndrc->tramp.f)) {
988 SysPrintf("trampoline table is full, last func %p\n", f);
989 abort();
990 }
991 if (ndrc->tramp.f[i] == NULL) {
992 start_tcache_write(&ndrc->tramp.f[i], &ndrc->tramp.f[i + 1]);
993 ndrc->tramp.f[i] = f;
994 end_tcache_write(&ndrc->tramp.f[i], &ndrc->tramp.f[i + 1]);
995 }
996 return &ndrc->tramp.ops[i];
997}
998
999static void emit_far_jump(const void *f)
1000{
1001 if (can_jump_or_call(f)) {
1002 emit_jmp(f);
1003 return;
1004 }
1005
1006 f = get_trampoline(f);
1007 emit_jmp(f);
1008}
1009
1010static void emit_far_call(const void *f)
1011{
1012 if (can_jump_or_call(f)) {
1013 emit_call(f);
1014 return;
1015 }
1016
1017 f = get_trampoline(f);
1018 emit_call(f);
1019}
1020
57871462 1021// Add virtual address mapping to linked list
1022void ll_add(struct ll_entry **head,int vaddr,void *addr)
1023{
1024 struct ll_entry *new_entry;
1025 new_entry=malloc(sizeof(struct ll_entry));
1026 assert(new_entry!=NULL);
1027 new_entry->vaddr=vaddr;
de5a60c3 1028 new_entry->reg_sv_flags=0;
57871462 1029 new_entry->addr=addr;
1030 new_entry->next=*head;
1031 *head=new_entry;
1032}
1033
de5a60c3 1034void ll_add_flags(struct ll_entry **head,int vaddr,u_int reg_sv_flags,void *addr)
57871462 1035{
7139f3c8 1036 ll_add(head,vaddr,addr);
de5a60c3 1037 (*head)->reg_sv_flags=reg_sv_flags;
57871462 1038}
1039
1040// Check if an address is already compiled
1041// but don't return addresses which are about to expire from the cache
1042void *check_addr(u_int vaddr)
1043{
df4dc2b1 1044 struct ht_entry *ht_bin = hash_table_get(vaddr);
1045 size_t i;
b14b6a8f 1046 for (i = 0; i < ARRAY_SIZE(ht_bin->vaddr); i++) {
df4dc2b1 1047 if (ht_bin->vaddr[i] == vaddr)
1048 if (doesnt_expire_soon((u_char *)ht_bin->tcaddr[i] - MAX_OUTPUT_BLOCK_SIZE))
1049 if (isclean(ht_bin->tcaddr[i]))
1050 return ht_bin->tcaddr[i];
57871462 1051 }
94d23bb9 1052 u_int page=get_page(vaddr);
57871462 1053 struct ll_entry *head;
1054 head=jump_in[page];
df4dc2b1 1055 while (head != NULL) {
1056 if (head->vaddr == vaddr) {
1057 if (doesnt_expire_soon(head->addr)) {
57871462 1058 // Update existing entry with current address
df4dc2b1 1059 if (ht_bin->vaddr[0] == vaddr) {
1060 ht_bin->tcaddr[0] = head->addr;
57871462 1061 return head->addr;
1062 }
df4dc2b1 1063 if (ht_bin->vaddr[1] == vaddr) {
1064 ht_bin->tcaddr[1] = head->addr;
57871462 1065 return head->addr;
1066 }
1067 // Insert into hash table with low priority.
1068 // Don't evict existing entries, as they are probably
1069 // addresses that are being accessed frequently.
df4dc2b1 1070 if (ht_bin->vaddr[0] == -1) {
1071 ht_bin->vaddr[0] = vaddr;
1072 ht_bin->tcaddr[0] = head->addr;
1073 }
1074 else if (ht_bin->vaddr[1] == -1) {
1075 ht_bin->vaddr[1] = vaddr;
1076 ht_bin->tcaddr[1] = head->addr;
57871462 1077 }
1078 return head->addr;
1079 }
1080 }
1081 head=head->next;
1082 }
1083 return 0;
1084}
1085
1086void remove_hash(int vaddr)
1087{
1088 //printf("remove hash: %x\n",vaddr);
df4dc2b1 1089 struct ht_entry *ht_bin = hash_table_get(vaddr);
1090 if (ht_bin->vaddr[1] == vaddr) {
1091 ht_bin->vaddr[1] = -1;
1092 ht_bin->tcaddr[1] = NULL;
57871462 1093 }
df4dc2b1 1094 if (ht_bin->vaddr[0] == vaddr) {
1095 ht_bin->vaddr[0] = ht_bin->vaddr[1];
1096 ht_bin->tcaddr[0] = ht_bin->tcaddr[1];
1097 ht_bin->vaddr[1] = -1;
1098 ht_bin->tcaddr[1] = NULL;
57871462 1099 }
1100}
1101
943f42f3 1102static void ll_remove_matching_addrs(struct ll_entry **head,
1103 uintptr_t base_offs_s, int shift)
57871462 1104{
1105 struct ll_entry *next;
1106 while(*head) {
943f42f3 1107 uintptr_t o1 = (u_char *)(*head)->addr - ndrc->translation_cache;
1108 uintptr_t o2 = o1 - MAX_OUTPUT_BLOCK_SIZE;
1109 if ((o1 >> shift) == base_offs_s || (o2 >> shift) == base_offs_s)
57871462 1110 {
643aeae3 1111 inv_debug("EXP: Remove pointer to %p (%x)\n",(*head)->addr,(*head)->vaddr);
57871462 1112 remove_hash((*head)->vaddr);
1113 next=(*head)->next;
1114 free(*head);
1115 *head=next;
1116 }
1117 else
1118 {
1119 head=&((*head)->next);
1120 }
1121 }
1122}
1123
1124// Remove all entries from linked list
1125void ll_clear(struct ll_entry **head)
1126{
1127 struct ll_entry *cur;
1128 struct ll_entry *next;
581335b0 1129 if((cur=*head)) {
57871462 1130 *head=0;
1131 while(cur) {
1132 next=cur->next;
1133 free(cur);
1134 cur=next;
1135 }
1136 }
1137}
1138
1139// Dereference the pointers and remove if it matches
943f42f3 1140static void ll_kill_pointers(struct ll_entry *head,
1141 uintptr_t base_offs_s, int shift)
57871462 1142{
1143 while(head) {
943f42f3 1144 u_char *ptr = get_pointer(head->addr);
1145 uintptr_t o1 = ptr - ndrc->translation_cache;
1146 uintptr_t o2 = o1 - MAX_OUTPUT_BLOCK_SIZE;
1147 inv_debug("EXP: Lookup pointer to %p at %p (%x)\n",ptr,head->addr,head->vaddr);
1148 if ((o1 >> shift) == base_offs_s || (o2 >> shift) == base_offs_s)
57871462 1149 {
643aeae3 1150 inv_debug("EXP: Kill pointer at %p (%x)\n",head->addr,head->vaddr);
d148d265 1151 void *host_addr=find_extjump_insn(head->addr);
919981d0 1152 mark_clear_cache(host_addr);
df4dc2b1 1153 set_jump_target(host_addr, head->addr);
57871462 1154 }
1155 head=head->next;
1156 }
1157}
1158
1159// This is called when we write to a compiled block (see do_invstub)
d1e4ebd9 1160static void invalidate_page(u_int page)
57871462 1161{
57871462 1162 struct ll_entry *head;
1163 struct ll_entry *next;
1164 head=jump_in[page];
1165 jump_in[page]=0;
1166 while(head!=NULL) {
1167 inv_debug("INVALIDATE: %x\n",head->vaddr);
1168 remove_hash(head->vaddr);
1169 next=head->next;
1170 free(head);
1171 head=next;
1172 }
1173 head=jump_out[page];
1174 jump_out[page]=0;
1175 while(head!=NULL) {
643aeae3 1176 inv_debug("INVALIDATE: kill pointer to %x (%p)\n",head->vaddr,head->addr);
d148d265 1177 void *host_addr=find_extjump_insn(head->addr);
919981d0 1178 mark_clear_cache(host_addr);
3d680478 1179 set_jump_target(host_addr, head->addr); // point back to dyna_linker
57871462 1180 next=head->next;
1181 free(head);
1182 head=next;
1183 }
57871462 1184}
9be4ba64 1185
1186static void invalidate_block_range(u_int block, u_int first, u_int last)
57871462 1187{
94d23bb9 1188 u_int page=get_page(block<<12);
57871462 1189 //printf("first=%d last=%d\n",first,last);
f76eeef9 1190 invalidate_page(page);
57871462 1191 assert(first+5>page); // NB: this assumes MAXBLOCK<=4096 (4 pages)
1192 assert(last<page+5);
1193 // Invalidate the adjacent pages if a block crosses a 4K boundary
1194 while(first<page) {
1195 invalidate_page(first);
1196 first++;
1197 }
1198 for(first=page+1;first<last;first++) {
1199 invalidate_page(first);
1200 }
919981d0 1201 do_clear_cache();
9f51b4b9 1202
57871462 1203 // Don't trap writes
1204 invalid_code[block]=1;
f76eeef9 1205
57871462 1206 #ifdef USE_MINI_HT
1207 memset(mini_ht,-1,sizeof(mini_ht));
1208 #endif
1209}
9be4ba64 1210
1211void invalidate_block(u_int block)
1212{
1213 u_int page=get_page(block<<12);
1214 u_int vpage=get_vpage(block<<12);
1215 inv_debug("INVALIDATE: %x (%d)\n",block<<12,page);
1216 //inv_debug("invalid_code[block]=%d\n",invalid_code[block]);
1217 u_int first,last;
1218 first=last=page;
1219 struct ll_entry *head;
1220 head=jump_dirty[vpage];
1221 //printf("page=%d vpage=%d\n",page,vpage);
1222 while(head!=NULL) {
9be4ba64 1223 if(vpage>2047||(head->vaddr>>12)==block) { // Ignore vaddr hash collision
01d26796 1224 u_char *start, *end;
1225 get_bounds(head->addr, &start, &end);
1226 //printf("start: %p end: %p\n", start, end);
1227 if (page < 2048 && start >= rdram && end < rdram+RAM_SIZE) {
1228 if (((start-rdram)>>12) <= page && ((end-1-rdram)>>12) >= page) {
1229 if ((((start-rdram)>>12)&2047) < first) first = ((start-rdram)>>12)&2047;
1230 if ((((end-1-rdram)>>12)&2047) > last) last = ((end-1-rdram)>>12)&2047;
9be4ba64 1231 }
1232 }
9be4ba64 1233 }
1234 head=head->next;
1235 }
1236 invalidate_block_range(block,first,last);
1237}
1238
57871462 1239void invalidate_addr(u_int addr)
1240{
9be4ba64 1241 //static int rhits;
1242 // this check is done by the caller
1243 //if (inv_code_start<=addr&&addr<=inv_code_end) { rhits++; return; }
d25604ca 1244 u_int page=get_vpage(addr);
9be4ba64 1245 if(page<2048) { // RAM
1246 struct ll_entry *head;
1247 u_int addr_min=~0, addr_max=0;
4a35de07 1248 u_int mask=RAM_SIZE-1;
1249 u_int addr_main=0x80000000|(addr&mask);
9be4ba64 1250 int pg1;
4a35de07 1251 inv_code_start=addr_main&~0xfff;
1252 inv_code_end=addr_main|0xfff;
9be4ba64 1253 pg1=page;
1254 if (pg1>0) {
1255 // must check previous page too because of spans..
1256 pg1--;
1257 inv_code_start-=0x1000;
1258 }
1259 for(;pg1<=page;pg1++) {
1260 for(head=jump_dirty[pg1];head!=NULL;head=head->next) {
01d26796 1261 u_char *start_h, *end_h;
1262 u_int start, end;
1263 get_bounds(head->addr, &start_h, &end_h);
1264 start = (uintptr_t)start_h - ram_offset;
1265 end = (uintptr_t)end_h - ram_offset;
4a35de07 1266 if(start<=addr_main&&addr_main<end) {
9be4ba64 1267 if(start<addr_min) addr_min=start;
1268 if(end>addr_max) addr_max=end;
1269 }
4a35de07 1270 else if(addr_main<start) {
9be4ba64 1271 if(start<inv_code_end)
1272 inv_code_end=start-1;
1273 }
1274 else {
1275 if(end>inv_code_start)
1276 inv_code_start=end;
1277 }
1278 }
1279 }
1280 if (addr_min!=~0) {
1281 inv_debug("INV ADDR: %08x hit %08x-%08x\n", addr, addr_min, addr_max);
1282 inv_code_start=inv_code_end=~0;
1283 invalidate_block_range(addr>>12,(addr_min&mask)>>12,(addr_max&mask)>>12);
1284 return;
1285 }
1286 else {
4a35de07 1287 inv_code_start=(addr&~mask)|(inv_code_start&mask);
1288 inv_code_end=(addr&~mask)|(inv_code_end&mask);
d25604ca 1289 inv_debug("INV ADDR: %08x miss, inv %08x-%08x, sk %d\n", addr, inv_code_start, inv_code_end, 0);
9be4ba64 1290 return;
d25604ca 1291 }
9be4ba64 1292 }
57871462 1293 invalidate_block(addr>>12);
1294}
9be4ba64 1295
dd3a91a1 1296// This is called when loading a save state.
1297// Anything could have changed, so invalidate everything.
919981d0 1298void invalidate_all_pages(void)
57871462 1299{
581335b0 1300 u_int page;
57871462 1301 for(page=0;page<4096;page++)
1302 invalidate_page(page);
1303 for(page=0;page<1048576;page++)
1304 if(!invalid_code[page]) {
1305 restore_candidate[(page&2047)>>3]|=1<<(page&7);
1306 restore_candidate[((page&2047)>>3)+256]|=1<<(page&7);
1307 }
57871462 1308 #ifdef USE_MINI_HT
1309 memset(mini_ht,-1,sizeof(mini_ht));
1310 #endif
919981d0 1311 do_clear_cache();
57871462 1312}
1313
d1e4ebd9 1314static void do_invstub(int n)
1315{
1316 literal_pool(20);
1317 u_int reglist=stubs[n].a;
1318 set_jump_target(stubs[n].addr, out);
1319 save_regs(reglist);
1320 if(stubs[n].b!=0) emit_mov(stubs[n].b,0);
2a014d73 1321 emit_far_call(invalidate_addr);
d1e4ebd9 1322 restore_regs(reglist);
1323 emit_jmp(stubs[n].retaddr); // return address
1324}
1325
57871462 1326// Add an entry to jump_out after making a link
d1e4ebd9 1327// src should point to code by emit_extjump2()
3d680478 1328void add_jump_out(u_int vaddr,void *src)
57871462 1329{
94d23bb9 1330 u_int page=get_page(vaddr);
3d680478 1331 inv_debug("add_jump_out: %p -> %x (%d)\n",src,vaddr,page);
d1e4ebd9 1332 check_extjump2(src);
57871462 1333 ll_add(jump_out+page,vaddr,src);
3d680478 1334 //inv_debug("add_jump_out: to %p\n",get_pointer(src));
57871462 1335}
1336
1337// If a code block was found to be unmodified (bit was set in
1338// restore_candidate) and it remains unmodified (bit is clear
1339// in invalid_code) then move the entries for that 4K page from
1340// the dirty list to the clean list.
1341void clean_blocks(u_int page)
1342{
1343 struct ll_entry *head;
1344 inv_debug("INV: clean_blocks page=%d\n",page);
1345 head=jump_dirty[page];
1346 while(head!=NULL) {
1347 if(!invalid_code[head->vaddr>>12]) {
1348 // Don't restore blocks which are about to expire from the cache
df4dc2b1 1349 if (doesnt_expire_soon(head->addr)) {
581335b0 1350 if(verify_dirty(head->addr)) {
01d26796 1351 u_char *start, *end;
643aeae3 1352 //printf("Possibly Restore %x (%p)\n",head->vaddr, head->addr);
57871462 1353 u_int i;
1354 u_int inv=0;
01d26796 1355 get_bounds(head->addr, &start, &end);
1356 if (start - rdram < RAM_SIZE) {
1357 for (i = (start-rdram+0x80000000)>>12; i <= (end-1-rdram+0x80000000)>>12; i++) {
57871462 1358 inv|=invalid_code[i];
1359 }
1360 }
4cb76aa4 1361 else if((signed int)head->vaddr>=(signed int)0x80000000+RAM_SIZE) {
57871462 1362 inv=1;
1363 }
1364 if(!inv) {
df4dc2b1 1365 void *clean_addr = get_clean_addr(head->addr);
1366 if (doesnt_expire_soon(clean_addr)) {
57871462 1367 u_int ppage=page;
643aeae3 1368 inv_debug("INV: Restored %x (%p/%p)\n",head->vaddr, head->addr, clean_addr);
57871462 1369 //printf("page=%x, addr=%x\n",page,head->vaddr);
1370 //assert(head->vaddr>>12==(page|0x80000));
de5a60c3 1371 ll_add_flags(jump_in+ppage,head->vaddr,head->reg_sv_flags,clean_addr);
df4dc2b1 1372 struct ht_entry *ht_bin = hash_table_get(head->vaddr);
1373 if (ht_bin->vaddr[0] == head->vaddr)
1374 ht_bin->tcaddr[0] = clean_addr; // Replace existing entry
1375 if (ht_bin->vaddr[1] == head->vaddr)
1376 ht_bin->tcaddr[1] = clean_addr; // Replace existing entry
57871462 1377 }
1378 }
1379 }
1380 }
1381 }
1382 head=head->next;
1383 }
1384}
1385
8062d65a 1386/* Register allocation */
1387
1388// Note: registers are allocated clean (unmodified state)
1389// if you intend to modify the register, you must call dirty_reg().
1390static void alloc_reg(struct regstat *cur,int i,signed char reg)
1391{
1392 int r,hr;
b7ec323c 1393 int preferred_reg = PREFERRED_REG_FIRST
1394 + reg % (PREFERRED_REG_LAST - PREFERRED_REG_FIRST + 1);
1395 if (reg == CCREG) preferred_reg = HOST_CCREG;
1396 if (reg == PTEMP || reg == FTEMP) preferred_reg = 12;
1397 assert(PREFERRED_REG_FIRST != EXCLUDE_REG && EXCLUDE_REG != HOST_REGS);
8062d65a 1398
1399 // Don't allocate unused registers
1400 if((cur->u>>reg)&1) return;
1401
1402 // see if it's already allocated
1403 for(hr=0;hr<HOST_REGS;hr++)
1404 {
1405 if(cur->regmap[hr]==reg) return;
1406 }
1407
1408 // Keep the same mapping if the register was already allocated in a loop
1409 preferred_reg = loop_reg(i,reg,preferred_reg);
1410
1411 // Try to allocate the preferred register
1412 if(cur->regmap[preferred_reg]==-1) {
1413 cur->regmap[preferred_reg]=reg;
1414 cur->dirty&=~(1<<preferred_reg);
1415 cur->isconst&=~(1<<preferred_reg);
1416 return;
1417 }
1418 r=cur->regmap[preferred_reg];
1419 assert(r < 64);
1420 if((cur->u>>r)&1) {
1421 cur->regmap[preferred_reg]=reg;
1422 cur->dirty&=~(1<<preferred_reg);
1423 cur->isconst&=~(1<<preferred_reg);
1424 return;
1425 }
1426
1427 // Clear any unneeded registers
1428 // We try to keep the mapping consistent, if possible, because it
1429 // makes branches easier (especially loops). So we try to allocate
1430 // first (see above) before removing old mappings. If this is not
1431 // possible then go ahead and clear out the registers that are no
1432 // longer needed.
1433 for(hr=0;hr<HOST_REGS;hr++)
1434 {
1435 r=cur->regmap[hr];
1436 if(r>=0) {
1437 assert(r < 64);
1438 if((cur->u>>r)&1) {cur->regmap[hr]=-1;break;}
1439 }
1440 }
b7ec323c 1441
8062d65a 1442 // Try to allocate any available register, but prefer
1443 // registers that have not been used recently.
b7ec323c 1444 if (i > 0) {
1445 for (hr = PREFERRED_REG_FIRST; ; ) {
1446 if (cur->regmap[hr] < 0) {
1447 int oldreg = regs[i-1].regmap[hr];
1448 if (oldreg < 0 || (oldreg != dops[i-1].rs1 && oldreg != dops[i-1].rs2
1449 && oldreg != dops[i-1].rt1 && oldreg != dops[i-1].rt2))
1450 {
8062d65a 1451 cur->regmap[hr]=reg;
1452 cur->dirty&=~(1<<hr);
1453 cur->isconst&=~(1<<hr);
1454 return;
1455 }
1456 }
b7ec323c 1457 hr++;
1458 if (hr == EXCLUDE_REG)
1459 hr++;
1460 if (hr == HOST_REGS)
1461 hr = 0;
1462 if (hr == PREFERRED_REG_FIRST)
1463 break;
8062d65a 1464 }
1465 }
b7ec323c 1466
8062d65a 1467 // Try to allocate any available register
b7ec323c 1468 for (hr = PREFERRED_REG_FIRST; ; ) {
1469 if (cur->regmap[hr] < 0) {
8062d65a 1470 cur->regmap[hr]=reg;
1471 cur->dirty&=~(1<<hr);
1472 cur->isconst&=~(1<<hr);
1473 return;
1474 }
b7ec323c 1475 hr++;
1476 if (hr == EXCLUDE_REG)
1477 hr++;
1478 if (hr == HOST_REGS)
1479 hr = 0;
1480 if (hr == PREFERRED_REG_FIRST)
1481 break;
8062d65a 1482 }
1483
1484 // Ok, now we have to evict someone
1485 // Pick a register we hopefully won't need soon
1486 u_char hsn[MAXREG+1];
1487 memset(hsn,10,sizeof(hsn));
1488 int j;
1489 lsn(hsn,i,&preferred_reg);
1490 //printf("eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",cur->regmap[0],cur->regmap[1],cur->regmap[2],cur->regmap[3],cur->regmap[5],cur->regmap[6],cur->regmap[7]);
1491 //printf("hsn(%x): %d %d %d %d %d %d %d\n",start+i*4,hsn[cur->regmap[0]&63],hsn[cur->regmap[1]&63],hsn[cur->regmap[2]&63],hsn[cur->regmap[3]&63],hsn[cur->regmap[5]&63],hsn[cur->regmap[6]&63],hsn[cur->regmap[7]&63]);
1492 if(i>0) {
1493 // Don't evict the cycle count at entry points, otherwise the entry
1494 // stub will have to write it.
cf95b4f0 1495 if(dops[i].bt&&hsn[CCREG]>2) hsn[CCREG]=2;
fe807a8a 1496 if (i>1 && hsn[CCREG] > 2 && dops[i-2].is_jump) hsn[CCREG]=2;
8062d65a 1497 for(j=10;j>=3;j--)
1498 {
1499 // Alloc preferred register if available
1500 if(hsn[r=cur->regmap[preferred_reg]&63]==j) {
1501 for(hr=0;hr<HOST_REGS;hr++) {
1502 // Evict both parts of a 64-bit register
1503 if((cur->regmap[hr]&63)==r) {
1504 cur->regmap[hr]=-1;
1505 cur->dirty&=~(1<<hr);
1506 cur->isconst&=~(1<<hr);
1507 }
1508 }
1509 cur->regmap[preferred_reg]=reg;
1510 return;
1511 }
1512 for(r=1;r<=MAXREG;r++)
1513 {
cf95b4f0 1514 if(hsn[r]==j&&r!=dops[i-1].rs1&&r!=dops[i-1].rs2&&r!=dops[i-1].rt1&&r!=dops[i-1].rt2) {
8062d65a 1515 for(hr=0;hr<HOST_REGS;hr++) {
1516 if(hr!=HOST_CCREG||j<hsn[CCREG]) {
1517 if(cur->regmap[hr]==r) {
1518 cur->regmap[hr]=reg;
1519 cur->dirty&=~(1<<hr);
1520 cur->isconst&=~(1<<hr);
1521 return;
1522 }
1523 }
1524 }
1525 }
1526 }
1527 }
1528 }
1529 for(j=10;j>=0;j--)
1530 {
1531 for(r=1;r<=MAXREG;r++)
1532 {
1533 if(hsn[r]==j) {
8062d65a 1534 for(hr=0;hr<HOST_REGS;hr++) {
1535 if(cur->regmap[hr]==r) {
1536 cur->regmap[hr]=reg;
1537 cur->dirty&=~(1<<hr);
1538 cur->isconst&=~(1<<hr);
1539 return;
1540 }
1541 }
1542 }
1543 }
1544 }
7c3a5182 1545 SysPrintf("This shouldn't happen (alloc_reg)");abort();
8062d65a 1546}
1547
1548// Allocate a temporary register. This is done without regard to
1549// dirty status or whether the register we request is on the unneeded list
1550// Note: This will only allocate one register, even if called multiple times
1551static void alloc_reg_temp(struct regstat *cur,int i,signed char reg)
1552{
1553 int r,hr;
1554 int preferred_reg = -1;
1555
1556 // see if it's already allocated
1557 for(hr=0;hr<HOST_REGS;hr++)
1558 {
1559 if(hr!=EXCLUDE_REG&&cur->regmap[hr]==reg) return;
1560 }
1561
1562 // Try to allocate any available register
1563 for(hr=HOST_REGS-1;hr>=0;hr--) {
1564 if(hr!=EXCLUDE_REG&&cur->regmap[hr]==-1) {
1565 cur->regmap[hr]=reg;
1566 cur->dirty&=~(1<<hr);
1567 cur->isconst&=~(1<<hr);
1568 return;
1569 }
1570 }
1571
1572 // Find an unneeded register
1573 for(hr=HOST_REGS-1;hr>=0;hr--)
1574 {
1575 r=cur->regmap[hr];
1576 if(r>=0) {
1577 assert(r < 64);
1578 if((cur->u>>r)&1) {
1579 if(i==0||((unneeded_reg[i-1]>>r)&1)) {
1580 cur->regmap[hr]=reg;
1581 cur->dirty&=~(1<<hr);
1582 cur->isconst&=~(1<<hr);
1583 return;
1584 }
1585 }
1586 }
1587 }
1588
1589 // Ok, now we have to evict someone
1590 // Pick a register we hopefully won't need soon
1591 // TODO: we might want to follow unconditional jumps here
1592 // TODO: get rid of dupe code and make this into a function
1593 u_char hsn[MAXREG+1];
1594 memset(hsn,10,sizeof(hsn));
1595 int j;
1596 lsn(hsn,i,&preferred_reg);
1597 //printf("hsn: %d %d %d %d %d %d %d\n",hsn[cur->regmap[0]&63],hsn[cur->regmap[1]&63],hsn[cur->regmap[2]&63],hsn[cur->regmap[3]&63],hsn[cur->regmap[5]&63],hsn[cur->regmap[6]&63],hsn[cur->regmap[7]&63]);
1598 if(i>0) {
1599 // Don't evict the cycle count at entry points, otherwise the entry
1600 // stub will have to write it.
cf95b4f0 1601 if(dops[i].bt&&hsn[CCREG]>2) hsn[CCREG]=2;
fe807a8a 1602 if (i>1 && hsn[CCREG] > 2 && dops[i-2].is_jump) hsn[CCREG]=2;
8062d65a 1603 for(j=10;j>=3;j--)
1604 {
1605 for(r=1;r<=MAXREG;r++)
1606 {
cf95b4f0 1607 if(hsn[r]==j&&r!=dops[i-1].rs1&&r!=dops[i-1].rs2&&r!=dops[i-1].rt1&&r!=dops[i-1].rt2) {
8062d65a 1608 for(hr=0;hr<HOST_REGS;hr++) {
1609 if(hr!=HOST_CCREG||hsn[CCREG]>2) {
1610 if(cur->regmap[hr]==r) {
1611 cur->regmap[hr]=reg;
1612 cur->dirty&=~(1<<hr);
1613 cur->isconst&=~(1<<hr);
1614 return;
1615 }
1616 }
1617 }
1618 }
1619 }
1620 }
1621 }
1622 for(j=10;j>=0;j--)
1623 {
1624 for(r=1;r<=MAXREG;r++)
1625 {
1626 if(hsn[r]==j) {
8062d65a 1627 for(hr=0;hr<HOST_REGS;hr++) {
1628 if(cur->regmap[hr]==r) {
1629 cur->regmap[hr]=reg;
1630 cur->dirty&=~(1<<hr);
1631 cur->isconst&=~(1<<hr);
1632 return;
1633 }
1634 }
1635 }
1636 }
1637 }
7c3a5182 1638 SysPrintf("This shouldn't happen");abort();
8062d65a 1639}
1640
ad49de89 1641static void mov_alloc(struct regstat *current,int i)
57871462 1642{
cf95b4f0 1643 if (dops[i].rs1 == HIREG || dops[i].rs1 == LOREG) {
9a3ccfeb 1644 alloc_cc(current,i); // for stalls
1645 dirty_reg(current,CCREG);
32631e6a 1646 }
1647
57871462 1648 // Note: Don't need to actually alloc the source registers
cf95b4f0 1649 //alloc_reg(current,i,dops[i].rs1);
1650 alloc_reg(current,i,dops[i].rt1);
ad49de89 1651
cf95b4f0 1652 clear_const(current,dops[i].rs1);
1653 clear_const(current,dops[i].rt1);
1654 dirty_reg(current,dops[i].rt1);
57871462 1655}
1656
ad49de89 1657static void shiftimm_alloc(struct regstat *current,int i)
57871462 1658{
cf95b4f0 1659 if(dops[i].opcode2<=0x3) // SLL/SRL/SRA
57871462 1660 {
cf95b4f0 1661 if(dops[i].rt1) {
1662 if(dops[i].rs1&&needed_again(dops[i].rs1,i)) alloc_reg(current,i,dops[i].rs1);
1663 else dops[i].lt1=dops[i].rs1;
1664 alloc_reg(current,i,dops[i].rt1);
1665 dirty_reg(current,dops[i].rt1);
1666 if(is_const(current,dops[i].rs1)) {
1667 int v=get_const(current,dops[i].rs1);
1668 if(dops[i].opcode2==0x00) set_const(current,dops[i].rt1,v<<imm[i]);
1669 if(dops[i].opcode2==0x02) set_const(current,dops[i].rt1,(u_int)v>>imm[i]);
1670 if(dops[i].opcode2==0x03) set_const(current,dops[i].rt1,v>>imm[i]);
dc49e339 1671 }
cf95b4f0 1672 else clear_const(current,dops[i].rt1);
57871462 1673 }
1674 }
dc49e339 1675 else
1676 {
cf95b4f0 1677 clear_const(current,dops[i].rs1);
1678 clear_const(current,dops[i].rt1);
dc49e339 1679 }
1680
cf95b4f0 1681 if(dops[i].opcode2>=0x38&&dops[i].opcode2<=0x3b) // DSLL/DSRL/DSRA
57871462 1682 {
9c45ca93 1683 assert(0);
57871462 1684 }
cf95b4f0 1685 if(dops[i].opcode2==0x3c) // DSLL32
57871462 1686 {
9c45ca93 1687 assert(0);
57871462 1688 }
cf95b4f0 1689 if(dops[i].opcode2==0x3e) // DSRL32
57871462 1690 {
9c45ca93 1691 assert(0);
57871462 1692 }
cf95b4f0 1693 if(dops[i].opcode2==0x3f) // DSRA32
57871462 1694 {
9c45ca93 1695 assert(0);
57871462 1696 }
1697}
1698
ad49de89 1699static void shift_alloc(struct regstat *current,int i)
57871462 1700{
cf95b4f0 1701 if(dops[i].rt1) {
1702 if(dops[i].opcode2<=0x07) // SLLV/SRLV/SRAV
57871462 1703 {
cf95b4f0 1704 if(dops[i].rs1) alloc_reg(current,i,dops[i].rs1);
1705 if(dops[i].rs2) alloc_reg(current,i,dops[i].rs2);
1706 alloc_reg(current,i,dops[i].rt1);
1707 if(dops[i].rt1==dops[i].rs2) {
e1190b87 1708 alloc_reg_temp(current,i,-1);
1709 minimum_free_regs[i]=1;
1710 }
57871462 1711 } else { // DSLLV/DSRLV/DSRAV
00fa9369 1712 assert(0);
57871462 1713 }
cf95b4f0 1714 clear_const(current,dops[i].rs1);
1715 clear_const(current,dops[i].rs2);
1716 clear_const(current,dops[i].rt1);
1717 dirty_reg(current,dops[i].rt1);
57871462 1718 }
1719}
1720
ad49de89 1721static void alu_alloc(struct regstat *current,int i)
57871462 1722{
cf95b4f0 1723 if(dops[i].opcode2>=0x20&&dops[i].opcode2<=0x23) { // ADD/ADDU/SUB/SUBU
1724 if(dops[i].rt1) {
1725 if(dops[i].rs1&&dops[i].rs2) {
1726 alloc_reg(current,i,dops[i].rs1);
1727 alloc_reg(current,i,dops[i].rs2);
57871462 1728 }
1729 else {
cf95b4f0 1730 if(dops[i].rs1&&needed_again(dops[i].rs1,i)) alloc_reg(current,i,dops[i].rs1);
1731 if(dops[i].rs2&&needed_again(dops[i].rs2,i)) alloc_reg(current,i,dops[i].rs2);
57871462 1732 }
cf95b4f0 1733 alloc_reg(current,i,dops[i].rt1);
57871462 1734 }
57871462 1735 }
cf95b4f0 1736 if(dops[i].opcode2==0x2a||dops[i].opcode2==0x2b) { // SLT/SLTU
1737 if(dops[i].rt1) {
1738 alloc_reg(current,i,dops[i].rs1);
1739 alloc_reg(current,i,dops[i].rs2);
1740 alloc_reg(current,i,dops[i].rt1);
57871462 1741 }
57871462 1742 }
cf95b4f0 1743 if(dops[i].opcode2>=0x24&&dops[i].opcode2<=0x27) { // AND/OR/XOR/NOR
1744 if(dops[i].rt1) {
1745 if(dops[i].rs1&&dops[i].rs2) {
1746 alloc_reg(current,i,dops[i].rs1);
1747 alloc_reg(current,i,dops[i].rs2);
57871462 1748 }
1749 else
1750 {
cf95b4f0 1751 if(dops[i].rs1&&needed_again(dops[i].rs1,i)) alloc_reg(current,i,dops[i].rs1);
1752 if(dops[i].rs2&&needed_again(dops[i].rs2,i)) alloc_reg(current,i,dops[i].rs2);
57871462 1753 }
cf95b4f0 1754 alloc_reg(current,i,dops[i].rt1);
57871462 1755 }
1756 }
cf95b4f0 1757 if(dops[i].opcode2>=0x2c&&dops[i].opcode2<=0x2f) { // DADD/DADDU/DSUB/DSUBU
00fa9369 1758 assert(0);
57871462 1759 }
cf95b4f0 1760 clear_const(current,dops[i].rs1);
1761 clear_const(current,dops[i].rs2);
1762 clear_const(current,dops[i].rt1);
1763 dirty_reg(current,dops[i].rt1);
57871462 1764}
1765
ad49de89 1766static void imm16_alloc(struct regstat *current,int i)
57871462 1767{
cf95b4f0 1768 if(dops[i].rs1&&needed_again(dops[i].rs1,i)) alloc_reg(current,i,dops[i].rs1);
1769 else dops[i].lt1=dops[i].rs1;
1770 if(dops[i].rt1) alloc_reg(current,i,dops[i].rt1);
1771 if(dops[i].opcode==0x18||dops[i].opcode==0x19) { // DADDI/DADDIU
00fa9369 1772 assert(0);
57871462 1773 }
cf95b4f0 1774 else if(dops[i].opcode==0x0a||dops[i].opcode==0x0b) { // SLTI/SLTIU
1775 clear_const(current,dops[i].rs1);
1776 clear_const(current,dops[i].rt1);
57871462 1777 }
cf95b4f0 1778 else if(dops[i].opcode>=0x0c&&dops[i].opcode<=0x0e) { // ANDI/ORI/XORI
1779 if(is_const(current,dops[i].rs1)) {
1780 int v=get_const(current,dops[i].rs1);
1781 if(dops[i].opcode==0x0c) set_const(current,dops[i].rt1,v&imm[i]);
1782 if(dops[i].opcode==0x0d) set_const(current,dops[i].rt1,v|imm[i]);
1783 if(dops[i].opcode==0x0e) set_const(current,dops[i].rt1,v^imm[i]);
57871462 1784 }
cf95b4f0 1785 else clear_const(current,dops[i].rt1);
57871462 1786 }
cf95b4f0 1787 else if(dops[i].opcode==0x08||dops[i].opcode==0x09) { // ADDI/ADDIU
1788 if(is_const(current,dops[i].rs1)) {
1789 int v=get_const(current,dops[i].rs1);
1790 set_const(current,dops[i].rt1,v+imm[i]);
57871462 1791 }
cf95b4f0 1792 else clear_const(current,dops[i].rt1);
57871462 1793 }
1794 else {
cf95b4f0 1795 set_const(current,dops[i].rt1,imm[i]<<16); // LUI
57871462 1796 }
cf95b4f0 1797 dirty_reg(current,dops[i].rt1);
57871462 1798}
1799
ad49de89 1800static void load_alloc(struct regstat *current,int i)
57871462 1801{
cf95b4f0 1802 clear_const(current,dops[i].rt1);
1803 //if(dops[i].rs1!=dops[i].rt1&&needed_again(dops[i].rs1,i)) clear_const(current,dops[i].rs1); // Does this help or hurt?
1804 if(!dops[i].rs1) current->u&=~1LL; // Allow allocating r0 if it's the source register
37387d8b 1805 if (needed_again(dops[i].rs1, i))
1806 alloc_reg(current, i, dops[i].rs1);
1807 if (ram_offset)
1808 alloc_reg(current, i, ROREG);
cf95b4f0 1809 if(dops[i].rt1&&!((current->u>>dops[i].rt1)&1)) {
1810 alloc_reg(current,i,dops[i].rt1);
1811 assert(get_reg(current->regmap,dops[i].rt1)>=0);
1812 if(dops[i].opcode==0x27||dops[i].opcode==0x37) // LWU/LD
57871462 1813 {
ad49de89 1814 assert(0);
57871462 1815 }
cf95b4f0 1816 else if(dops[i].opcode==0x1A||dops[i].opcode==0x1B) // LDL/LDR
57871462 1817 {
ad49de89 1818 assert(0);
57871462 1819 }
cf95b4f0 1820 dirty_reg(current,dops[i].rt1);
57871462 1821 // LWL/LWR need a temporary register for the old value
cf95b4f0 1822 if(dops[i].opcode==0x22||dops[i].opcode==0x26)
57871462 1823 {
1824 alloc_reg(current,i,FTEMP);
1825 alloc_reg_temp(current,i,-1);
e1190b87 1826 minimum_free_regs[i]=1;
57871462 1827 }
1828 }
1829 else
1830 {
373d1d07 1831 // Load to r0 or unneeded register (dummy load)
57871462 1832 // but we still need a register to calculate the address
cf95b4f0 1833 if(dops[i].opcode==0x22||dops[i].opcode==0x26)
535d208a 1834 {
1835 alloc_reg(current,i,FTEMP); // LWL/LWR need another temporary
1836 }
57871462 1837 alloc_reg_temp(current,i,-1);
e1190b87 1838 minimum_free_regs[i]=1;
cf95b4f0 1839 if(dops[i].opcode==0x1A||dops[i].opcode==0x1B) // LDL/LDR
535d208a 1840 {
ad49de89 1841 assert(0);
535d208a 1842 }
57871462 1843 }
1844}
1845
1846void store_alloc(struct regstat *current,int i)
1847{
cf95b4f0 1848 clear_const(current,dops[i].rs2);
1849 if(!(dops[i].rs2)) current->u&=~1LL; // Allow allocating r0 if necessary
1850 if(needed_again(dops[i].rs1,i)) alloc_reg(current,i,dops[i].rs1);
1851 alloc_reg(current,i,dops[i].rs2);
1852 if(dops[i].opcode==0x2c||dops[i].opcode==0x2d||dops[i].opcode==0x3f) { // 64-bit SDL/SDR/SD
ad49de89 1853 assert(0);
57871462 1854 }
37387d8b 1855 if (ram_offset)
1856 alloc_reg(current, i, ROREG);
57871462 1857 #if defined(HOST_IMM8)
1858 // On CPUs without 32-bit immediates we need a pointer to invalid_code
37387d8b 1859 alloc_reg(current, i, INVCP);
57871462 1860 #endif
cf95b4f0 1861 if(dops[i].opcode==0x2a||dops[i].opcode==0x2e||dops[i].opcode==0x2c||dops[i].opcode==0x2d) { // SWL/SWL/SDL/SDR
57871462 1862 alloc_reg(current,i,FTEMP);
1863 }
1864 // We need a temporary register for address generation
1865 alloc_reg_temp(current,i,-1);
e1190b87 1866 minimum_free_regs[i]=1;
57871462 1867}
1868
1869void c1ls_alloc(struct regstat *current,int i)
1870{
cf95b4f0 1871 clear_const(current,dops[i].rt1);
57871462 1872 alloc_reg(current,i,CSREG); // Status
57871462 1873}
1874
b9b61529 1875void c2ls_alloc(struct regstat *current,int i)
1876{
cf95b4f0 1877 clear_const(current,dops[i].rt1);
1878 if(needed_again(dops[i].rs1,i)) alloc_reg(current,i,dops[i].rs1);
b9b61529 1879 alloc_reg(current,i,FTEMP);
37387d8b 1880 if (ram_offset)
1881 alloc_reg(current, i, ROREG);
b9b61529 1882 #if defined(HOST_IMM8)
1883 // On CPUs without 32-bit immediates we need a pointer to invalid_code
37387d8b 1884 if (dops[i].opcode == 0x3a) // SWC2
b9b61529 1885 alloc_reg(current,i,INVCP);
1886 #endif
1887 // We need a temporary register for address generation
1888 alloc_reg_temp(current,i,-1);
e1190b87 1889 minimum_free_regs[i]=1;
b9b61529 1890}
1891
57871462 1892#ifndef multdiv_alloc
1893void multdiv_alloc(struct regstat *current,int i)
1894{
1895 // case 0x18: MULT
1896 // case 0x19: MULTU
1897 // case 0x1A: DIV
1898 // case 0x1B: DIVU
1899 // case 0x1C: DMULT
1900 // case 0x1D: DMULTU
1901 // case 0x1E: DDIV
1902 // case 0x1F: DDIVU
cf95b4f0 1903 clear_const(current,dops[i].rs1);
1904 clear_const(current,dops[i].rs2);
32631e6a 1905 alloc_cc(current,i); // for stalls
cf95b4f0 1906 if(dops[i].rs1&&dops[i].rs2)
57871462 1907 {
cf95b4f0 1908 if((dops[i].opcode2&4)==0) // 32-bit
57871462 1909 {
1910 current->u&=~(1LL<<HIREG);
1911 current->u&=~(1LL<<LOREG);
1912 alloc_reg(current,i,HIREG);
1913 alloc_reg(current,i,LOREG);
cf95b4f0 1914 alloc_reg(current,i,dops[i].rs1);
1915 alloc_reg(current,i,dops[i].rs2);
57871462 1916 dirty_reg(current,HIREG);
1917 dirty_reg(current,LOREG);
1918 }
1919 else // 64-bit
1920 {
00fa9369 1921 assert(0);
57871462 1922 }
1923 }
1924 else
1925 {
1926 // Multiply by zero is zero.
1927 // MIPS does not have a divide by zero exception.
1928 // The result is undefined, we return zero.
1929 alloc_reg(current,i,HIREG);
1930 alloc_reg(current,i,LOREG);
57871462 1931 dirty_reg(current,HIREG);
1932 dirty_reg(current,LOREG);
1933 }
1934}
1935#endif
1936
1937void cop0_alloc(struct regstat *current,int i)
1938{
cf95b4f0 1939 if(dops[i].opcode2==0) // MFC0
57871462 1940 {
cf95b4f0 1941 if(dops[i].rt1) {
1942 clear_const(current,dops[i].rt1);
57871462 1943 alloc_all(current,i);
cf95b4f0 1944 alloc_reg(current,i,dops[i].rt1);
1945 dirty_reg(current,dops[i].rt1);
57871462 1946 }
1947 }
cf95b4f0 1948 else if(dops[i].opcode2==4) // MTC0
57871462 1949 {
cf95b4f0 1950 if(dops[i].rs1){
1951 clear_const(current,dops[i].rs1);
1952 alloc_reg(current,i,dops[i].rs1);
57871462 1953 alloc_all(current,i);
1954 }
1955 else {
1956 alloc_all(current,i); // FIXME: Keep r0
1957 current->u&=~1LL;
1958 alloc_reg(current,i,0);
1959 }
1960 }
1961 else
1962 {
1963 // TLBR/TLBWI/TLBWR/TLBP/ERET
cf95b4f0 1964 assert(dops[i].opcode2==0x10);
57871462 1965 alloc_all(current,i);
1966 }
e1190b87 1967 minimum_free_regs[i]=HOST_REGS;
57871462 1968}
1969
81dbbf4c 1970static void cop2_alloc(struct regstat *current,int i)
57871462 1971{
cf95b4f0 1972 if (dops[i].opcode2 < 3) // MFC2/CFC2
57871462 1973 {
81dbbf4c 1974 alloc_cc(current,i); // for stalls
1975 dirty_reg(current,CCREG);
cf95b4f0 1976 if(dops[i].rt1){
1977 clear_const(current,dops[i].rt1);
1978 alloc_reg(current,i,dops[i].rt1);
1979 dirty_reg(current,dops[i].rt1);
57871462 1980 }
57871462 1981 }
cf95b4f0 1982 else if (dops[i].opcode2 > 3) // MTC2/CTC2
57871462 1983 {
cf95b4f0 1984 if(dops[i].rs1){
1985 clear_const(current,dops[i].rs1);
1986 alloc_reg(current,i,dops[i].rs1);
57871462 1987 }
1988 else {
1989 current->u&=~1LL;
1990 alloc_reg(current,i,0);
57871462 1991 }
1992 }
81dbbf4c 1993 alloc_reg_temp(current,i,-1);
e1190b87 1994 minimum_free_regs[i]=1;
57871462 1995}
00fa9369 1996
b9b61529 1997void c2op_alloc(struct regstat *current,int i)
1998{
81dbbf4c 1999 alloc_cc(current,i); // for stalls
2000 dirty_reg(current,CCREG);
b9b61529 2001 alloc_reg_temp(current,i,-1);
2002}
57871462 2003
2004void syscall_alloc(struct regstat *current,int i)
2005{
2006 alloc_cc(current,i);
2007 dirty_reg(current,CCREG);
2008 alloc_all(current,i);
e1190b87 2009 minimum_free_regs[i]=HOST_REGS;
57871462 2010 current->isconst=0;
2011}
2012
2013void delayslot_alloc(struct regstat *current,int i)
2014{
cf95b4f0 2015 switch(dops[i].itype) {
57871462 2016 case UJUMP:
2017 case CJUMP:
2018 case SJUMP:
2019 case RJUMP:
57871462 2020 case SYSCALL:
7139f3c8 2021 case HLECALL:
57871462 2022 case SPAN:
7c3a5182 2023 assem_debug("jump in the delay slot. this shouldn't happen.\n");//abort();
c43b5311 2024 SysPrintf("Disabled speculative precompilation\n");
57871462 2025 stop_after_jal=1;
2026 break;
2027 case IMM16:
2028 imm16_alloc(current,i);
2029 break;
2030 case LOAD:
2031 case LOADLR:
2032 load_alloc(current,i);
2033 break;
2034 case STORE:
2035 case STORELR:
2036 store_alloc(current,i);
2037 break;
2038 case ALU:
2039 alu_alloc(current,i);
2040 break;
2041 case SHIFT:
2042 shift_alloc(current,i);
2043 break;
2044 case MULTDIV:
2045 multdiv_alloc(current,i);
2046 break;
2047 case SHIFTIMM:
2048 shiftimm_alloc(current,i);
2049 break;
2050 case MOV:
2051 mov_alloc(current,i);
2052 break;
2053 case COP0:
2054 cop0_alloc(current,i);
2055 break;
2056 case COP1:
81dbbf4c 2057 break;
b9b61529 2058 case COP2:
81dbbf4c 2059 cop2_alloc(current,i);
57871462 2060 break;
2061 case C1LS:
2062 c1ls_alloc(current,i);
2063 break;
b9b61529 2064 case C2LS:
2065 c2ls_alloc(current,i);
2066 break;
b9b61529 2067 case C2OP:
2068 c2op_alloc(current,i);
2069 break;
57871462 2070 }
2071}
2072
2073// Special case where a branch and delay slot span two pages in virtual memory
2074static void pagespan_alloc(struct regstat *current,int i)
2075{
2076 current->isconst=0;
2077 current->wasconst=0;
2078 regs[i].wasconst=0;
e1190b87 2079 minimum_free_regs[i]=HOST_REGS;
57871462 2080 alloc_all(current,i);
2081 alloc_cc(current,i);
2082 dirty_reg(current,CCREG);
cf95b4f0 2083 if(dops[i].opcode==3) // JAL
57871462 2084 {
2085 alloc_reg(current,i,31);
2086 dirty_reg(current,31);
2087 }
cf95b4f0 2088 if(dops[i].opcode==0&&(dops[i].opcode2&0x3E)==8) // JR/JALR
57871462 2089 {
cf95b4f0 2090 alloc_reg(current,i,dops[i].rs1);
2091 if (dops[i].rt1!=0) {
2092 alloc_reg(current,i,dops[i].rt1);
2093 dirty_reg(current,dops[i].rt1);
57871462 2094 }
2095 }
cf95b4f0 2096 if((dops[i].opcode&0x2E)==4) // BEQ/BNE/BEQL/BNEL
57871462 2097 {
cf95b4f0 2098 if(dops[i].rs1) alloc_reg(current,i,dops[i].rs1);
2099 if(dops[i].rs2) alloc_reg(current,i,dops[i].rs2);
57871462 2100 }
2101 else
cf95b4f0 2102 if((dops[i].opcode&0x2E)==6) // BLEZ/BGTZ/BLEZL/BGTZL
57871462 2103 {
cf95b4f0 2104 if(dops[i].rs1) alloc_reg(current,i,dops[i].rs1);
57871462 2105 }
57871462 2106 //else ...
2107}
2108
b14b6a8f 2109static void add_stub(enum stub_type type, void *addr, void *retaddr,
2110 u_int a, uintptr_t b, uintptr_t c, u_int d, u_int e)
2111{
d1e4ebd9 2112 assert(stubcount < ARRAY_SIZE(stubs));
b14b6a8f 2113 stubs[stubcount].type = type;
2114 stubs[stubcount].addr = addr;
2115 stubs[stubcount].retaddr = retaddr;
2116 stubs[stubcount].a = a;
2117 stubs[stubcount].b = b;
2118 stubs[stubcount].c = c;
2119 stubs[stubcount].d = d;
2120 stubs[stubcount].e = e;
57871462 2121 stubcount++;
2122}
2123
b14b6a8f 2124static void add_stub_r(enum stub_type type, void *addr, void *retaddr,
81dbbf4c 2125 int i, int addr_reg, const struct regstat *i_regs, int ccadj, u_int reglist)
b14b6a8f 2126{
2127 add_stub(type, addr, retaddr, i, addr_reg, (uintptr_t)i_regs, ccadj, reglist);
2128}
2129
57871462 2130// Write out a single register
2330734f 2131static void wb_register(signed char r, const signed char regmap[], uint64_t dirty)
57871462 2132{
2133 int hr;
2134 for(hr=0;hr<HOST_REGS;hr++) {
2135 if(hr!=EXCLUDE_REG) {
2136 if((regmap[hr]&63)==r) {
2137 if((dirty>>hr)&1) {
ad49de89 2138 assert(regmap[hr]<64);
2139 emit_storereg(r,hr);
57871462 2140 }
2141 }
2142 }
2143 }
2144}
2145
8062d65a 2146static void wb_valid(signed char pre[],signed char entry[],u_int dirty_pre,u_int dirty,uint64_t u)
2147{
2148 //if(dirty_pre==dirty) return;
2149 int hr,reg;
2150 for(hr=0;hr<HOST_REGS;hr++) {
2151 if(hr!=EXCLUDE_REG) {
2152 reg=pre[hr];
2153 if(((~u)>>(reg&63))&1) {
2154 if(reg>0) {
2155 if(((dirty_pre&~dirty)>>hr)&1) {
2156 if(reg>0&&reg<34) {
2157 emit_storereg(reg,hr);
2158 }
2159 else if(reg>=64) {
2160 assert(0);
2161 }
2162 }
2163 }
2164 }
2165 }
2166 }
2167}
2168
687b4580 2169// trashes r2
2170static void pass_args(int a0, int a1)
2171{
2172 if(a0==1&&a1==0) {
2173 // must swap
2174 emit_mov(a0,2); emit_mov(a1,1); emit_mov(2,0);
2175 }
2176 else if(a0!=0&&a1==0) {
2177 emit_mov(a1,1);
2178 if (a0>=0) emit_mov(a0,0);
2179 }
2180 else {
2181 if(a0>=0&&a0!=0) emit_mov(a0,0);
2182 if(a1>=0&&a1!=1) emit_mov(a1,1);
2183 }
2184}
2185
2330734f 2186static void alu_assemble(int i, const struct regstat *i_regs)
57871462 2187{
cf95b4f0 2188 if(dops[i].opcode2>=0x20&&dops[i].opcode2<=0x23) { // ADD/ADDU/SUB/SUBU
2189 if(dops[i].rt1) {
57871462 2190 signed char s1,s2,t;
cf95b4f0 2191 t=get_reg(i_regs->regmap,dops[i].rt1);
57871462 2192 if(t>=0) {
cf95b4f0 2193 s1=get_reg(i_regs->regmap,dops[i].rs1);
2194 s2=get_reg(i_regs->regmap,dops[i].rs2);
2195 if(dops[i].rs1&&dops[i].rs2) {
57871462 2196 assert(s1>=0);
2197 assert(s2>=0);
cf95b4f0 2198 if(dops[i].opcode2&2) emit_sub(s1,s2,t);
57871462 2199 else emit_add(s1,s2,t);
2200 }
cf95b4f0 2201 else if(dops[i].rs1) {
57871462 2202 if(s1>=0) emit_mov(s1,t);
cf95b4f0 2203 else emit_loadreg(dops[i].rs1,t);
57871462 2204 }
cf95b4f0 2205 else if(dops[i].rs2) {
57871462 2206 if(s2>=0) {
cf95b4f0 2207 if(dops[i].opcode2&2) emit_neg(s2,t);
57871462 2208 else emit_mov(s2,t);
2209 }
2210 else {
cf95b4f0 2211 emit_loadreg(dops[i].rs2,t);
2212 if(dops[i].opcode2&2) emit_neg(t,t);
57871462 2213 }
2214 }
2215 else emit_zeroreg(t);
2216 }
2217 }
2218 }
cf95b4f0 2219 if(dops[i].opcode2>=0x2c&&dops[i].opcode2<=0x2f) { // DADD/DADDU/DSUB/DSUBU
00fa9369 2220 assert(0);
57871462 2221 }
cf95b4f0 2222 if(dops[i].opcode2==0x2a||dops[i].opcode2==0x2b) { // SLT/SLTU
2223 if(dops[i].rt1) {
ad49de89 2224 signed char s1l,s2l,t;
57871462 2225 {
cf95b4f0 2226 t=get_reg(i_regs->regmap,dops[i].rt1);
57871462 2227 //assert(t>=0);
2228 if(t>=0) {
cf95b4f0 2229 s1l=get_reg(i_regs->regmap,dops[i].rs1);
2230 s2l=get_reg(i_regs->regmap,dops[i].rs2);
2231 if(dops[i].rs2==0) // rx<r0
57871462 2232 {
cf95b4f0 2233 if(dops[i].opcode2==0x2a&&dops[i].rs1!=0) { // SLT
06e425d7 2234 assert(s1l>=0);
57871462 2235 emit_shrimm(s1l,31,t);
06e425d7 2236 }
2237 else // SLTU (unsigned can not be less than zero, 0<0)
57871462 2238 emit_zeroreg(t);
2239 }
cf95b4f0 2240 else if(dops[i].rs1==0) // r0<rx
57871462 2241 {
2242 assert(s2l>=0);
cf95b4f0 2243 if(dops[i].opcode2==0x2a) // SLT
57871462 2244 emit_set_gz32(s2l,t);
2245 else // SLTU (set if not zero)
2246 emit_set_nz32(s2l,t);
2247 }
2248 else{
2249 assert(s1l>=0);assert(s2l>=0);
cf95b4f0 2250 if(dops[i].opcode2==0x2a) // SLT
57871462 2251 emit_set_if_less32(s1l,s2l,t);
2252 else // SLTU
2253 emit_set_if_carry32(s1l,s2l,t);
2254 }
2255 }
2256 }
2257 }
2258 }
cf95b4f0 2259 if(dops[i].opcode2>=0x24&&dops[i].opcode2<=0x27) { // AND/OR/XOR/NOR
2260 if(dops[i].rt1) {
ad49de89 2261 signed char s1l,s2l,tl;
cf95b4f0 2262 tl=get_reg(i_regs->regmap,dops[i].rt1);
57871462 2263 {
57871462 2264 if(tl>=0) {
cf95b4f0 2265 s1l=get_reg(i_regs->regmap,dops[i].rs1);
2266 s2l=get_reg(i_regs->regmap,dops[i].rs2);
2267 if(dops[i].rs1&&dops[i].rs2) {
57871462 2268 assert(s1l>=0);
2269 assert(s2l>=0);
cf95b4f0 2270 if(dops[i].opcode2==0x24) { // AND
57871462 2271 emit_and(s1l,s2l,tl);
2272 } else
cf95b4f0 2273 if(dops[i].opcode2==0x25) { // OR
57871462 2274 emit_or(s1l,s2l,tl);
2275 } else
cf95b4f0 2276 if(dops[i].opcode2==0x26) { // XOR
57871462 2277 emit_xor(s1l,s2l,tl);
2278 } else
cf95b4f0 2279 if(dops[i].opcode2==0x27) { // NOR
57871462 2280 emit_or(s1l,s2l,tl);
2281 emit_not(tl,tl);
2282 }
2283 }
2284 else
2285 {
cf95b4f0 2286 if(dops[i].opcode2==0x24) { // AND
57871462 2287 emit_zeroreg(tl);
2288 } else
cf95b4f0 2289 if(dops[i].opcode2==0x25||dops[i].opcode2==0x26) { // OR/XOR
2290 if(dops[i].rs1){
57871462 2291 if(s1l>=0) emit_mov(s1l,tl);
cf95b4f0 2292 else emit_loadreg(dops[i].rs1,tl); // CHECK: regmap_entry?
57871462 2293 }
2294 else
cf95b4f0 2295 if(dops[i].rs2){
57871462 2296 if(s2l>=0) emit_mov(s2l,tl);
cf95b4f0 2297 else emit_loadreg(dops[i].rs2,tl); // CHECK: regmap_entry?
57871462 2298 }
2299 else emit_zeroreg(tl);
2300 } else
cf95b4f0 2301 if(dops[i].opcode2==0x27) { // NOR
2302 if(dops[i].rs1){
57871462 2303 if(s1l>=0) emit_not(s1l,tl);
2304 else {
cf95b4f0 2305 emit_loadreg(dops[i].rs1,tl);
57871462 2306 emit_not(tl,tl);
2307 }
2308 }
2309 else
cf95b4f0 2310 if(dops[i].rs2){
57871462 2311 if(s2l>=0) emit_not(s2l,tl);
2312 else {
cf95b4f0 2313 emit_loadreg(dops[i].rs2,tl);
57871462 2314 emit_not(tl,tl);
2315 }
2316 }
2317 else emit_movimm(-1,tl);
2318 }
2319 }
2320 }
2321 }
2322 }
2323 }
2324}
2325
2330734f 2326static void imm16_assemble(int i, const struct regstat *i_regs)
57871462 2327{
cf95b4f0 2328 if (dops[i].opcode==0x0f) { // LUI
2329 if(dops[i].rt1) {
57871462 2330 signed char t;
cf95b4f0 2331 t=get_reg(i_regs->regmap,dops[i].rt1);
57871462 2332 //assert(t>=0);
2333 if(t>=0) {
2334 if(!((i_regs->isconst>>t)&1))
2335 emit_movimm(imm[i]<<16,t);
2336 }
2337 }
2338 }
cf95b4f0 2339 if(dops[i].opcode==0x08||dops[i].opcode==0x09) { // ADDI/ADDIU
2340 if(dops[i].rt1) {
57871462 2341 signed char s,t;
cf95b4f0 2342 t=get_reg(i_regs->regmap,dops[i].rt1);
2343 s=get_reg(i_regs->regmap,dops[i].rs1);
2344 if(dops[i].rs1) {
57871462 2345 //assert(t>=0);
2346 //assert(s>=0);
2347 if(t>=0) {
2348 if(!((i_regs->isconst>>t)&1)) {
2349 if(s<0) {
cf95b4f0 2350 if(i_regs->regmap_entry[t]!=dops[i].rs1) emit_loadreg(dops[i].rs1,t);
57871462 2351 emit_addimm(t,imm[i],t);
2352 }else{
2353 if(!((i_regs->wasconst>>s)&1))
2354 emit_addimm(s,imm[i],t);
2355 else
2356 emit_movimm(constmap[i][s]+imm[i],t);
2357 }
2358 }
2359 }
2360 } else {
2361 if(t>=0) {
2362 if(!((i_regs->isconst>>t)&1))
2363 emit_movimm(imm[i],t);
2364 }
2365 }
2366 }
2367 }
cf95b4f0 2368 if(dops[i].opcode==0x18||dops[i].opcode==0x19) { // DADDI/DADDIU
2369 if(dops[i].rt1) {
7c3a5182 2370 signed char sl,tl;
cf95b4f0 2371 tl=get_reg(i_regs->regmap,dops[i].rt1);
2372 sl=get_reg(i_regs->regmap,dops[i].rs1);
57871462 2373 if(tl>=0) {
cf95b4f0 2374 if(dops[i].rs1) {
57871462 2375 assert(sl>=0);
7c3a5182 2376 emit_addimm(sl,imm[i],tl);
57871462 2377 } else {
2378 emit_movimm(imm[i],tl);
57871462 2379 }
2380 }
2381 }
2382 }
cf95b4f0 2383 else if(dops[i].opcode==0x0a||dops[i].opcode==0x0b) { // SLTI/SLTIU
2384 if(dops[i].rt1) {
2385 //assert(dops[i].rs1!=0); // r0 might be valid, but it's probably a bug
ad49de89 2386 signed char sl,t;
cf95b4f0 2387 t=get_reg(i_regs->regmap,dops[i].rt1);
2388 sl=get_reg(i_regs->regmap,dops[i].rs1);
57871462 2389 //assert(t>=0);
2390 if(t>=0) {
cf95b4f0 2391 if(dops[i].rs1>0) {
2392 if(dops[i].opcode==0x0a) { // SLTI
57871462 2393 if(sl<0) {
cf95b4f0 2394 if(i_regs->regmap_entry[t]!=dops[i].rs1) emit_loadreg(dops[i].rs1,t);
57871462 2395 emit_slti32(t,imm[i],t);
2396 }else{
2397 emit_slti32(sl,imm[i],t);
2398 }
2399 }
2400 else { // SLTIU
2401 if(sl<0) {
cf95b4f0 2402 if(i_regs->regmap_entry[t]!=dops[i].rs1) emit_loadreg(dops[i].rs1,t);
57871462 2403 emit_sltiu32(t,imm[i],t);
2404 }else{
2405 emit_sltiu32(sl,imm[i],t);
2406 }
2407 }
57871462 2408 }else{
2409 // SLTI(U) with r0 is just stupid,
2410 // nonetheless examples can be found
cf95b4f0 2411 if(dops[i].opcode==0x0a) // SLTI
57871462 2412 if(0<imm[i]) emit_movimm(1,t);
2413 else emit_zeroreg(t);
2414 else // SLTIU
2415 {
2416 if(imm[i]) emit_movimm(1,t);
2417 else emit_zeroreg(t);
2418 }
2419 }
2420 }
2421 }
2422 }
cf95b4f0 2423 else if(dops[i].opcode>=0x0c&&dops[i].opcode<=0x0e) { // ANDI/ORI/XORI
2424 if(dops[i].rt1) {
7c3a5182 2425 signed char sl,tl;
cf95b4f0 2426 tl=get_reg(i_regs->regmap,dops[i].rt1);
2427 sl=get_reg(i_regs->regmap,dops[i].rs1);
57871462 2428 if(tl>=0 && !((i_regs->isconst>>tl)&1)) {
cf95b4f0 2429 if(dops[i].opcode==0x0c) //ANDI
57871462 2430 {
cf95b4f0 2431 if(dops[i].rs1) {
57871462 2432 if(sl<0) {
cf95b4f0 2433 if(i_regs->regmap_entry[tl]!=dops[i].rs1) emit_loadreg(dops[i].rs1,tl);
57871462 2434 emit_andimm(tl,imm[i],tl);
2435 }else{
2436 if(!((i_regs->wasconst>>sl)&1))
2437 emit_andimm(sl,imm[i],tl);
2438 else
2439 emit_movimm(constmap[i][sl]&imm[i],tl);
2440 }
2441 }
2442 else
2443 emit_zeroreg(tl);
57871462 2444 }
2445 else
2446 {
cf95b4f0 2447 if(dops[i].rs1) {
57871462 2448 if(sl<0) {
cf95b4f0 2449 if(i_regs->regmap_entry[tl]!=dops[i].rs1) emit_loadreg(dops[i].rs1,tl);
57871462 2450 }
cf95b4f0 2451 if(dops[i].opcode==0x0d) { // ORI
581335b0 2452 if(sl<0) {
2453 emit_orimm(tl,imm[i],tl);
2454 }else{
2455 if(!((i_regs->wasconst>>sl)&1))
2456 emit_orimm(sl,imm[i],tl);
2457 else
2458 emit_movimm(constmap[i][sl]|imm[i],tl);
2459 }
57871462 2460 }
cf95b4f0 2461 if(dops[i].opcode==0x0e) { // XORI
581335b0 2462 if(sl<0) {
2463 emit_xorimm(tl,imm[i],tl);
2464 }else{
2465 if(!((i_regs->wasconst>>sl)&1))
2466 emit_xorimm(sl,imm[i],tl);
2467 else
2468 emit_movimm(constmap[i][sl]^imm[i],tl);
2469 }
57871462 2470 }
2471 }
2472 else {
2473 emit_movimm(imm[i],tl);
57871462 2474 }
2475 }
2476 }
2477 }
2478 }
2479}
2480
2330734f 2481static void shiftimm_assemble(int i, const struct regstat *i_regs)
57871462 2482{
cf95b4f0 2483 if(dops[i].opcode2<=0x3) // SLL/SRL/SRA
57871462 2484 {
cf95b4f0 2485 if(dops[i].rt1) {
57871462 2486 signed char s,t;
cf95b4f0 2487 t=get_reg(i_regs->regmap,dops[i].rt1);
2488 s=get_reg(i_regs->regmap,dops[i].rs1);
57871462 2489 //assert(t>=0);
dc49e339 2490 if(t>=0&&!((i_regs->isconst>>t)&1)){
cf95b4f0 2491 if(dops[i].rs1==0)
57871462 2492 {
2493 emit_zeroreg(t);
2494 }
2495 else
2496 {
cf95b4f0 2497 if(s<0&&i_regs->regmap_entry[t]!=dops[i].rs1) emit_loadreg(dops[i].rs1,t);
57871462 2498 if(imm[i]) {
cf95b4f0 2499 if(dops[i].opcode2==0) // SLL
57871462 2500 {
2501 emit_shlimm(s<0?t:s,imm[i],t);
2502 }
cf95b4f0 2503 if(dops[i].opcode2==2) // SRL
57871462 2504 {
2505 emit_shrimm(s<0?t:s,imm[i],t);
2506 }
cf95b4f0 2507 if(dops[i].opcode2==3) // SRA
57871462 2508 {
2509 emit_sarimm(s<0?t:s,imm[i],t);
2510 }
2511 }else{
2512 // Shift by zero
2513 if(s>=0 && s!=t) emit_mov(s,t);
2514 }
2515 }
2516 }
cf95b4f0 2517 //emit_storereg(dops[i].rt1,t); //DEBUG
57871462 2518 }
2519 }
cf95b4f0 2520 if(dops[i].opcode2>=0x38&&dops[i].opcode2<=0x3b) // DSLL/DSRL/DSRA
57871462 2521 {
9c45ca93 2522 assert(0);
57871462 2523 }
cf95b4f0 2524 if(dops[i].opcode2==0x3c) // DSLL32
57871462 2525 {
9c45ca93 2526 assert(0);
57871462 2527 }
cf95b4f0 2528 if(dops[i].opcode2==0x3e) // DSRL32
57871462 2529 {
9c45ca93 2530 assert(0);
57871462 2531 }
cf95b4f0 2532 if(dops[i].opcode2==0x3f) // DSRA32
57871462 2533 {
9c45ca93 2534 assert(0);
57871462 2535 }
2536}
2537
2538#ifndef shift_assemble
2330734f 2539static void shift_assemble(int i, const struct regstat *i_regs)
57871462 2540{
3968e69e 2541 signed char s,t,shift;
cf95b4f0 2542 if (dops[i].rt1 == 0)
3968e69e 2543 return;
cf95b4f0 2544 assert(dops[i].opcode2<=0x07); // SLLV/SRLV/SRAV
2545 t = get_reg(i_regs->regmap, dops[i].rt1);
2546 s = get_reg(i_regs->regmap, dops[i].rs1);
2547 shift = get_reg(i_regs->regmap, dops[i].rs2);
3968e69e 2548 if (t < 0)
2549 return;
2550
cf95b4f0 2551 if(dops[i].rs1==0)
3968e69e 2552 emit_zeroreg(t);
cf95b4f0 2553 else if(dops[i].rs2==0) {
3968e69e 2554 assert(s>=0);
2555 if(s!=t) emit_mov(s,t);
2556 }
2557 else {
2558 host_tempreg_acquire();
2559 emit_andimm(shift,31,HOST_TEMPREG);
cf95b4f0 2560 switch(dops[i].opcode2) {
3968e69e 2561 case 4: // SLLV
2562 emit_shl(s,HOST_TEMPREG,t);
2563 break;
2564 case 6: // SRLV
2565 emit_shr(s,HOST_TEMPREG,t);
2566 break;
2567 case 7: // SRAV
2568 emit_sar(s,HOST_TEMPREG,t);
2569 break;
2570 default:
2571 assert(0);
2572 }
2573 host_tempreg_release();
2574 }
57871462 2575}
3968e69e 2576
57871462 2577#endif
2578
8062d65a 2579enum {
2580 MTYPE_8000 = 0,
2581 MTYPE_8020,
2582 MTYPE_0000,
2583 MTYPE_A000,
2584 MTYPE_1F80,
2585};
2586
2587static int get_ptr_mem_type(u_int a)
2588{
2589 if(a < 0x00200000) {
2590 if(a<0x1000&&((start>>20)==0xbfc||(start>>24)==0xa0))
2591 // return wrong, must use memhandler for BIOS self-test to pass
2592 // 007 does similar stuff from a00 mirror, weird stuff
2593 return MTYPE_8000;
2594 return MTYPE_0000;
2595 }
2596 if(0x1f800000 <= a && a < 0x1f801000)
2597 return MTYPE_1F80;
2598 if(0x80200000 <= a && a < 0x80800000)
2599 return MTYPE_8020;
2600 if(0xa0000000 <= a && a < 0xa0200000)
2601 return MTYPE_A000;
2602 return MTYPE_8000;
2603}
2604
37387d8b 2605static int get_ro_reg(const struct regstat *i_regs, int host_tempreg_free)
2606{
2607 int r = get_reg(i_regs->regmap, ROREG);
2608 if (r < 0 && host_tempreg_free) {
2609 host_tempreg_acquire();
2610 emit_loadreg(ROREG, r = HOST_TEMPREG);
2611 }
2612 if (r < 0)
2613 abort();
2614 return r;
2615}
2616
2617static void *emit_fastpath_cmp_jump(int i, const struct regstat *i_regs,
2618 int addr, int *offset_reg, int *addr_reg_override)
8062d65a 2619{
2620 void *jaddr = NULL;
37387d8b 2621 int type = 0;
2622 int mr = dops[i].rs1;
2623 *offset_reg = -1;
8062d65a 2624 if(((smrv_strong|smrv_weak)>>mr)&1) {
2625 type=get_ptr_mem_type(smrv[mr]);
2626 //printf("set %08x @%08x r%d %d\n", smrv[mr], start+i*4, mr, type);
2627 }
2628 else {
2629 // use the mirror we are running on
2630 type=get_ptr_mem_type(start);
2631 //printf("set nospec @%08x r%d %d\n", start+i*4, mr, type);
2632 }
2633
2634 if(type==MTYPE_8020) { // RAM 80200000+ mirror
d1e4ebd9 2635 host_tempreg_acquire();
8062d65a 2636 emit_andimm(addr,~0x00e00000,HOST_TEMPREG);
2637 addr=*addr_reg_override=HOST_TEMPREG;
2638 type=0;
2639 }
2640 else if(type==MTYPE_0000) { // RAM 0 mirror
d1e4ebd9 2641 host_tempreg_acquire();
8062d65a 2642 emit_orimm(addr,0x80000000,HOST_TEMPREG);
2643 addr=*addr_reg_override=HOST_TEMPREG;
2644 type=0;
2645 }
2646 else if(type==MTYPE_A000) { // RAM A mirror
d1e4ebd9 2647 host_tempreg_acquire();
8062d65a 2648 emit_andimm(addr,~0x20000000,HOST_TEMPREG);
2649 addr=*addr_reg_override=HOST_TEMPREG;
2650 type=0;
2651 }
2652 else if(type==MTYPE_1F80) { // scratchpad
2653 if (psxH == (void *)0x1f800000) {
d1e4ebd9 2654 host_tempreg_acquire();
3968e69e 2655 emit_xorimm(addr,0x1f800000,HOST_TEMPREG);
8062d65a 2656 emit_cmpimm(HOST_TEMPREG,0x1000);
d1e4ebd9 2657 host_tempreg_release();
8062d65a 2658 jaddr=out;
2659 emit_jc(0);
2660 }
2661 else {
2662 // do the usual RAM check, jump will go to the right handler
2663 type=0;
2664 }
2665 }
2666
37387d8b 2667 if (type == 0) // need ram check
8062d65a 2668 {
2669 emit_cmpimm(addr,RAM_SIZE);
37387d8b 2670 jaddr = out;
8062d65a 2671 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
2672 // Hint to branch predictor that the branch is unlikely to be taken
37387d8b 2673 if (dops[i].rs1 >= 28)
8062d65a 2674 emit_jno_unlikely(0);
2675 else
2676 #endif
2677 emit_jno(0);
37387d8b 2678 if (ram_offset != 0)
2679 *offset_reg = get_ro_reg(i_regs, 0);
8062d65a 2680 }
2681
2682 return jaddr;
2683}
2684
687b4580 2685// return memhandler, or get directly accessable address and return 0
2686static void *get_direct_memhandler(void *table, u_int addr,
2687 enum stub_type type, uintptr_t *addr_host)
2688{
c979e8c2 2689 uintptr_t msb = 1ull << (sizeof(uintptr_t)*8 - 1);
687b4580 2690 uintptr_t l1, l2 = 0;
2691 l1 = ((uintptr_t *)table)[addr>>12];
c979e8c2 2692 if (!(l1 & msb)) {
687b4580 2693 uintptr_t v = l1 << 1;
2694 *addr_host = v + addr;
2695 return NULL;
2696 }
2697 else {
2698 l1 <<= 1;
2699 if (type == LOADB_STUB || type == LOADBU_STUB || type == STOREB_STUB)
2700 l2 = ((uintptr_t *)l1)[0x1000/4 + 0x1000/2 + (addr&0xfff)];
2701 else if (type == LOADH_STUB || type == LOADHU_STUB || type == STOREH_STUB)
c979e8c2 2702 l2 = ((uintptr_t *)l1)[0x1000/4 + (addr&0xfff)/2];
687b4580 2703 else
c979e8c2 2704 l2 = ((uintptr_t *)l1)[(addr&0xfff)/4];
2705 if (!(l2 & msb)) {
687b4580 2706 uintptr_t v = l2 << 1;
2707 *addr_host = v + (addr&0xfff);
2708 return NULL;
2709 }
2710 return (void *)(l2 << 1);
2711 }
2712}
2713
81dbbf4c 2714static u_int get_host_reglist(const signed char *regmap)
2715{
2716 u_int reglist = 0, hr;
2717 for (hr = 0; hr < HOST_REGS; hr++) {
2718 if (hr != EXCLUDE_REG && regmap[hr] >= 0)
2719 reglist |= 1 << hr;
2720 }
2721 return reglist;
2722}
2723
2724static u_int reglist_exclude(u_int reglist, int r1, int r2)
2725{
2726 if (r1 >= 0)
2727 reglist &= ~(1u << r1);
2728 if (r2 >= 0)
2729 reglist &= ~(1u << r2);
2730 return reglist;
2731}
2732
e3c6bdb5 2733// find a temp caller-saved register not in reglist (so assumed to be free)
2734static int reglist_find_free(u_int reglist)
2735{
2736 u_int free_regs = ~reglist & CALLER_SAVE_REGS;
2737 if (free_regs == 0)
2738 return -1;
2739 return __builtin_ctz(free_regs);
2740}
2741
37387d8b 2742static void do_load_word(int a, int rt, int offset_reg)
2743{
2744 if (offset_reg >= 0)
2745 emit_ldr_dualindexed(offset_reg, a, rt);
2746 else
2747 emit_readword_indexed(0, a, rt);
2748}
2749
2750static void do_store_word(int a, int ofs, int rt, int offset_reg, int preseve_a)
2751{
2752 if (offset_reg < 0) {
2753 emit_writeword_indexed(rt, ofs, a);
2754 return;
2755 }
2756 if (ofs != 0)
2757 emit_addimm(a, ofs, a);
2758 emit_str_dualindexed(offset_reg, a, rt);
2759 if (ofs != 0 && preseve_a)
2760 emit_addimm(a, -ofs, a);
2761}
2762
2763static void do_store_hword(int a, int ofs, int rt, int offset_reg, int preseve_a)
2764{
2765 if (offset_reg < 0) {
2766 emit_writehword_indexed(rt, ofs, a);
2767 return;
2768 }
2769 if (ofs != 0)
2770 emit_addimm(a, ofs, a);
2771 emit_strh_dualindexed(offset_reg, a, rt);
2772 if (ofs != 0 && preseve_a)
2773 emit_addimm(a, -ofs, a);
2774}
2775
2776static void do_store_byte(int a, int rt, int offset_reg)
2777{
2778 if (offset_reg >= 0)
2779 emit_strb_dualindexed(offset_reg, a, rt);
2780 else
2781 emit_writebyte_indexed(rt, 0, a);
2782}
2783
2330734f 2784static void load_assemble(int i, const struct regstat *i_regs, int ccadj_)
57871462 2785{
7c3a5182 2786 int s,tl,addr;
57871462 2787 int offset;
b14b6a8f 2788 void *jaddr=0;
5bf843dc 2789 int memtarget=0,c=0;
37387d8b 2790 int offset_reg = -1;
2791 int fastio_reg_override = -1;
81dbbf4c 2792 u_int reglist=get_host_reglist(i_regs->regmap);
cf95b4f0 2793 tl=get_reg(i_regs->regmap,dops[i].rt1);
2794 s=get_reg(i_regs->regmap,dops[i].rs1);
57871462 2795 offset=imm[i];
57871462 2796 if(i_regs->regmap[HOST_CCREG]==CCREG) reglist&=~(1<<HOST_CCREG);
2797 if(s>=0) {
2798 c=(i_regs->wasconst>>s)&1;
af4ee1fe 2799 if (c) {
2800 memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
af4ee1fe 2801 }
57871462 2802 }
57871462 2803 //printf("load_assemble: c=%d\n",c);
643aeae3 2804 //if(c) printf("load_assemble: const=%lx\n",(long)constmap[i][s]+offset);
57871462 2805 // FIXME: Even if the load is a NOP, we should check for pagefaults...
581335b0 2806 if((tl<0&&(!c||(((u_int)constmap[i][s]+offset)>>16)==0x1f80))
cf95b4f0 2807 ||dops[i].rt1==0) {
5bf843dc 2808 // could be FIFO, must perform the read
f18c0f46 2809 // ||dummy read
5bf843dc 2810 assem_debug("(forced read)\n");
2811 tl=get_reg(i_regs->regmap,-1);
2812 assert(tl>=0);
5bf843dc 2813 }
2814 if(offset||s<0||c) addr=tl;
2815 else addr=s;
535d208a 2816 //if(tl<0) tl=get_reg(i_regs->regmap,-1);
2817 if(tl>=0) {
2818 //printf("load_assemble: c=%d\n",c);
643aeae3 2819 //if(c) printf("load_assemble: const=%lx\n",(long)constmap[i][s]+offset);
535d208a 2820 assert(tl>=0); // Even if the load is a NOP, we must check for pagefaults and I/O
2821 reglist&=~(1<<tl);
1edfcc68 2822 if(!c) {
1edfcc68 2823 #ifdef R29_HACK
2824 // Strmnnrmn's speed hack
cf95b4f0 2825 if(dops[i].rs1!=29||start<0x80001000||start>=0x80000000+RAM_SIZE)
1edfcc68 2826 #endif
2827 {
37387d8b 2828 jaddr = emit_fastpath_cmp_jump(i, i_regs, addr,
2829 &offset_reg, &fastio_reg_override);
535d208a 2830 }
1edfcc68 2831 }
37387d8b 2832 else if (ram_offset && memtarget) {
2833 offset_reg = get_ro_reg(i_regs, 0);
535d208a 2834 }
cf95b4f0 2835 int dummy=(dops[i].rt1==0)||(tl!=get_reg(i_regs->regmap,dops[i].rt1)); // ignore loads to r0 and unneeded reg
37387d8b 2836 switch (dops[i].opcode) {
2837 case 0x20: // LB
535d208a 2838 if(!c||memtarget) {
2839 if(!dummy) {
37387d8b 2840 int a = tl;
2841 if (!c) a = addr;
2842 if (fastio_reg_override >= 0)
2843 a = fastio_reg_override;
b1570849 2844
37387d8b 2845 if (offset_reg >= 0)
2846 emit_ldrsb_dualindexed(offset_reg, a, tl);
2847 else
2848 emit_movsbl_indexed(0, a, tl);
57871462 2849 }
535d208a 2850 if(jaddr)
2330734f 2851 add_stub_r(LOADB_STUB,jaddr,out,i,addr,i_regs,ccadj_,reglist);
57871462 2852 }
535d208a 2853 else
2330734f 2854 inline_readstub(LOADB_STUB,i,constmap[i][s]+offset,i_regs->regmap,dops[i].rt1,ccadj_,reglist);
37387d8b 2855 break;
2856 case 0x21: // LH
535d208a 2857 if(!c||memtarget) {
2858 if(!dummy) {
37387d8b 2859 int a = tl;
2860 if (!c) a = addr;
2861 if (fastio_reg_override >= 0)
2862 a = fastio_reg_override;
2863 if (offset_reg >= 0)
2864 emit_ldrsh_dualindexed(offset_reg, a, tl);
2865 else
2866 emit_movswl_indexed(0, a, tl);
57871462 2867 }
535d208a 2868 if(jaddr)
2330734f 2869 add_stub_r(LOADH_STUB,jaddr,out,i,addr,i_regs,ccadj_,reglist);
57871462 2870 }
535d208a 2871 else
2330734f 2872 inline_readstub(LOADH_STUB,i,constmap[i][s]+offset,i_regs->regmap,dops[i].rt1,ccadj_,reglist);
37387d8b 2873 break;
2874 case 0x23: // LW
535d208a 2875 if(!c||memtarget) {
2876 if(!dummy) {
37387d8b 2877 int a = addr;
2878 if (fastio_reg_override >= 0)
2879 a = fastio_reg_override;
2880 do_load_word(a, tl, offset_reg);
57871462 2881 }
535d208a 2882 if(jaddr)
2330734f 2883 add_stub_r(LOADW_STUB,jaddr,out,i,addr,i_regs,ccadj_,reglist);
57871462 2884 }
535d208a 2885 else
2330734f 2886 inline_readstub(LOADW_STUB,i,constmap[i][s]+offset,i_regs->regmap,dops[i].rt1,ccadj_,reglist);
37387d8b 2887 break;
2888 case 0x24: // LBU
535d208a 2889 if(!c||memtarget) {
2890 if(!dummy) {
37387d8b 2891 int a = tl;
2892 if (!c) a = addr;
2893 if (fastio_reg_override >= 0)
2894 a = fastio_reg_override;
b1570849 2895
37387d8b 2896 if (offset_reg >= 0)
2897 emit_ldrb_dualindexed(offset_reg, a, tl);
2898 else
2899 emit_movzbl_indexed(0, a, tl);
57871462 2900 }
535d208a 2901 if(jaddr)
2330734f 2902 add_stub_r(LOADBU_STUB,jaddr,out,i,addr,i_regs,ccadj_,reglist);
57871462 2903 }
535d208a 2904 else
2330734f 2905 inline_readstub(LOADBU_STUB,i,constmap[i][s]+offset,i_regs->regmap,dops[i].rt1,ccadj_,reglist);
37387d8b 2906 break;
2907 case 0x25: // LHU
535d208a 2908 if(!c||memtarget) {
2909 if(!dummy) {
37387d8b 2910 int a = tl;
2911 if(!c) a = addr;
2912 if (fastio_reg_override >= 0)
2913 a = fastio_reg_override;
2914 if (offset_reg >= 0)
2915 emit_ldrh_dualindexed(offset_reg, a, tl);
2916 else
2917 emit_movzwl_indexed(0, a, tl);
57871462 2918 }
535d208a 2919 if(jaddr)
2330734f 2920 add_stub_r(LOADHU_STUB,jaddr,out,i,addr,i_regs,ccadj_,reglist);
57871462 2921 }
535d208a 2922 else
2330734f 2923 inline_readstub(LOADHU_STUB,i,constmap[i][s]+offset,i_regs->regmap,dops[i].rt1,ccadj_,reglist);
37387d8b 2924 break;
2925 case 0x27: // LWU
2926 case 0x37: // LD
2927 default:
9c45ca93 2928 assert(0);
57871462 2929 }
535d208a 2930 }
37387d8b 2931 if (fastio_reg_override == HOST_TEMPREG || offset_reg == HOST_TEMPREG)
d1e4ebd9 2932 host_tempreg_release();
57871462 2933}
2934
2935#ifndef loadlr_assemble
2330734f 2936static void loadlr_assemble(int i, const struct regstat *i_regs, int ccadj_)
57871462 2937{
3968e69e 2938 int s,tl,temp,temp2,addr;
2939 int offset;
2940 void *jaddr=0;
2941 int memtarget=0,c=0;
37387d8b 2942 int offset_reg = -1;
2943 int fastio_reg_override = -1;
81dbbf4c 2944 u_int reglist=get_host_reglist(i_regs->regmap);
cf95b4f0 2945 tl=get_reg(i_regs->regmap,dops[i].rt1);
2946 s=get_reg(i_regs->regmap,dops[i].rs1);
3968e69e 2947 temp=get_reg(i_regs->regmap,-1);
2948 temp2=get_reg(i_regs->regmap,FTEMP);
2949 addr=get_reg(i_regs->regmap,AGEN1+(i&1));
2950 assert(addr<0);
2951 offset=imm[i];
3968e69e 2952 reglist|=1<<temp;
2953 if(offset||s<0||c) addr=temp2;
2954 else addr=s;
2955 if(s>=0) {
2956 c=(i_regs->wasconst>>s)&1;
2957 if(c) {
2958 memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
2959 }
2960 }
2961 if(!c) {
2962 emit_shlimm(addr,3,temp);
cf95b4f0 2963 if (dops[i].opcode==0x22||dops[i].opcode==0x26) {
3968e69e 2964 emit_andimm(addr,0xFFFFFFFC,temp2); // LWL/LWR
2965 }else{
2966 emit_andimm(addr,0xFFFFFFF8,temp2); // LDL/LDR
2967 }
37387d8b 2968 jaddr = emit_fastpath_cmp_jump(i, i_regs, temp2,
2969 &offset_reg, &fastio_reg_override);
3968e69e 2970 }
2971 else {
37387d8b 2972 if (ram_offset && memtarget) {
2973 offset_reg = get_ro_reg(i_regs, 0);
3968e69e 2974 }
cf95b4f0 2975 if (dops[i].opcode==0x22||dops[i].opcode==0x26) {
3968e69e 2976 emit_movimm(((constmap[i][s]+offset)<<3)&24,temp); // LWL/LWR
2977 }else{
2978 emit_movimm(((constmap[i][s]+offset)<<3)&56,temp); // LDL/LDR
2979 }
2980 }
cf95b4f0 2981 if (dops[i].opcode==0x22||dops[i].opcode==0x26) { // LWL/LWR
3968e69e 2982 if(!c||memtarget) {
37387d8b 2983 int a = temp2;
2984 if (fastio_reg_override >= 0)
2985 a = fastio_reg_override;
2986 do_load_word(a, temp2, offset_reg);
2987 if (fastio_reg_override == HOST_TEMPREG || offset_reg == HOST_TEMPREG)
2988 host_tempreg_release();
2330734f 2989 if(jaddr) add_stub_r(LOADW_STUB,jaddr,out,i,temp2,i_regs,ccadj_,reglist);
3968e69e 2990 }
2991 else
2330734f 2992 inline_readstub(LOADW_STUB,i,(constmap[i][s]+offset)&0xFFFFFFFC,i_regs->regmap,FTEMP,ccadj_,reglist);
cf95b4f0 2993 if(dops[i].rt1) {
3968e69e 2994 assert(tl>=0);
2995 emit_andimm(temp,24,temp);
cf95b4f0 2996 if (dops[i].opcode==0x22) // LWL
3968e69e 2997 emit_xorimm(temp,24,temp);
2998 host_tempreg_acquire();
2999 emit_movimm(-1,HOST_TEMPREG);
cf95b4f0 3000 if (dops[i].opcode==0x26) {
3968e69e 3001 emit_shr(temp2,temp,temp2);
3002 emit_bic_lsr(tl,HOST_TEMPREG,temp,tl);
3003 }else{
3004 emit_shl(temp2,temp,temp2);
3005 emit_bic_lsl(tl,HOST_TEMPREG,temp,tl);
3006 }
3007 host_tempreg_release();
3008 emit_or(temp2,tl,tl);
3009 }
cf95b4f0 3010 //emit_storereg(dops[i].rt1,tl); // DEBUG
3968e69e 3011 }
cf95b4f0 3012 if (dops[i].opcode==0x1A||dops[i].opcode==0x1B) { // LDL/LDR
3968e69e 3013 assert(0);
3014 }
57871462 3015}
3016#endif
3017
2330734f 3018static void store_assemble(int i, const struct regstat *i_regs, int ccadj_)
57871462 3019{
9c45ca93 3020 int s,tl;
57871462 3021 int addr,temp;
3022 int offset;
b14b6a8f 3023 void *jaddr=0;
37387d8b 3024 enum stub_type type=0;
666a299d 3025 int memtarget=0,c=0;
57871462 3026 int agr=AGEN1+(i&1);
37387d8b 3027 int offset_reg = -1;
3028 int fastio_reg_override = -1;
81dbbf4c 3029 u_int reglist=get_host_reglist(i_regs->regmap);
cf95b4f0 3030 tl=get_reg(i_regs->regmap,dops[i].rs2);
3031 s=get_reg(i_regs->regmap,dops[i].rs1);
57871462 3032 temp=get_reg(i_regs->regmap,agr);
3033 if(temp<0) temp=get_reg(i_regs->regmap,-1);
3034 offset=imm[i];
3035 if(s>=0) {
3036 c=(i_regs->wasconst>>s)&1;
af4ee1fe 3037 if(c) {
3038 memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
af4ee1fe 3039 }
57871462 3040 }
3041 assert(tl>=0);
3042 assert(temp>=0);
57871462 3043 if(i_regs->regmap[HOST_CCREG]==CCREG) reglist&=~(1<<HOST_CCREG);
3044 if(offset||s<0||c) addr=temp;
3045 else addr=s;
37387d8b 3046 if (!c) {
3047 jaddr = emit_fastpath_cmp_jump(i, i_regs, addr,
3048 &offset_reg, &fastio_reg_override);
1edfcc68 3049 }
37387d8b 3050 else if (ram_offset && memtarget) {
3051 offset_reg = get_ro_reg(i_regs, 0);
57871462 3052 }
3053
37387d8b 3054 switch (dops[i].opcode) {
3055 case 0x28: // SB
57871462 3056 if(!c||memtarget) {
37387d8b 3057 int a = temp;
3058 if (!c) a = addr;
3059 if (fastio_reg_override >= 0)
3060 a = fastio_reg_override;
3061 do_store_byte(a, tl, offset_reg);
3062 }
3063 type = STOREB_STUB;
3064 break;
3065 case 0x29: // SH
57871462 3066 if(!c||memtarget) {
37387d8b 3067 int a = temp;
3068 if (!c) a = addr;
3069 if (fastio_reg_override >= 0)
3070 a = fastio_reg_override;
3071 do_store_hword(a, 0, tl, offset_reg, 1);
3072 }
3073 type = STOREH_STUB;
3074 break;
3075 case 0x2B: // SW
dadf55f2 3076 if(!c||memtarget) {
37387d8b 3077 int a = addr;
3078 if (fastio_reg_override >= 0)
3079 a = fastio_reg_override;
3080 do_store_word(a, 0, tl, offset_reg, 1);
3081 }
3082 type = STOREW_STUB;
3083 break;
3084 case 0x3F: // SD
3085 default:
9c45ca93 3086 assert(0);
57871462 3087 }
37387d8b 3088 if (fastio_reg_override == HOST_TEMPREG || offset_reg == HOST_TEMPREG)
d1e4ebd9 3089 host_tempreg_release();
b96d3df7 3090 if(jaddr) {
3091 // PCSX store handlers don't check invcode again
3092 reglist|=1<<addr;
2330734f 3093 add_stub_r(type,jaddr,out,i,addr,i_regs,ccadj_,reglist);
b96d3df7 3094 jaddr=0;
3095 }
cf95b4f0 3096 if(!(i_regs->waswritten&(1<<dops[i].rs1)) && !HACK_ENABLED(NDHACK_NO_SMC_CHECK)) {
57871462 3097 if(!c||memtarget) {
3098 #ifdef DESTRUCTIVE_SHIFT
3099 // The x86 shift operation is 'destructive'; it overwrites the
3100 // source register, so we need to make a copy first and use that.
3101 addr=temp;
3102 #endif
3103 #if defined(HOST_IMM8)
3104 int ir=get_reg(i_regs->regmap,INVCP);
3105 assert(ir>=0);
3106 emit_cmpmem_indexedsr12_reg(ir,addr,1);
3107 #else
643aeae3 3108 emit_cmpmem_indexedsr12_imm(invalid_code,addr,1);
57871462 3109 #endif
0bbd1454 3110 #if defined(HAVE_CONDITIONAL_CALL) && !defined(DESTRUCTIVE_SHIFT)
3111 emit_callne(invalidate_addr_reg[addr]);
3112 #else
b14b6a8f 3113 void *jaddr2 = out;
57871462 3114 emit_jne(0);
b14b6a8f 3115 add_stub(INVCODE_STUB,jaddr2,out,reglist|(1<<HOST_CCREG),addr,0,0,0);
0bbd1454 3116 #endif
57871462 3117 }
3118 }
7a518516 3119 u_int addr_val=constmap[i][s]+offset;
3eaa7048 3120 if(jaddr) {
2330734f 3121 add_stub_r(type,jaddr,out,i,addr,i_regs,ccadj_,reglist);
3eaa7048 3122 } else if(c&&!memtarget) {
2330734f 3123 inline_writestub(type,i,addr_val,i_regs->regmap,dops[i].rs2,ccadj_,reglist);
7a518516 3124 }
3125 // basic current block modification detection..
3126 // not looking back as that should be in mips cache already
3968e69e 3127 // (see Spyro2 title->attract mode)
7a518516 3128 if(c&&start+i*4<addr_val&&addr_val<start+slen*4) {
c43b5311 3129 SysPrintf("write to %08x hits block %08x, pc=%08x\n",addr_val,start,start+i*4);
7a518516 3130 assert(i_regs->regmap==regs[i].regmap); // not delay slot
3131 if(i_regs->regmap==regs[i].regmap) {
ad49de89 3132 load_all_consts(regs[i].regmap_entry,regs[i].wasdirty,i);
3133 wb_dirtys(regs[i].regmap_entry,regs[i].wasdirty);
7a518516 3134 emit_movimm(start+i*4+4,0);
643aeae3 3135 emit_writeword(0,&pcaddr);
d1e4ebd9 3136 emit_addimm(HOST_CCREG,2,HOST_CCREG);
2a014d73 3137 emit_far_call(get_addr_ht);
d1e4ebd9 3138 emit_jmpreg(0);
7a518516 3139 }
3eaa7048 3140 }
57871462 3141}
3142
2330734f 3143static void storelr_assemble(int i, const struct regstat *i_regs, int ccadj_)
57871462 3144{
9c45ca93 3145 int s,tl;
57871462 3146 int temp;
57871462 3147 int offset;
b14b6a8f 3148 void *jaddr=0;
37387d8b 3149 void *case1, *case23, *case3;
df4dc2b1 3150 void *done0, *done1, *done2;
af4ee1fe 3151 int memtarget=0,c=0;
fab5d06d 3152 int agr=AGEN1+(i&1);
37387d8b 3153 int offset_reg = -1;
81dbbf4c 3154 u_int reglist=get_host_reglist(i_regs->regmap);
cf95b4f0 3155 tl=get_reg(i_regs->regmap,dops[i].rs2);
3156 s=get_reg(i_regs->regmap,dops[i].rs1);
fab5d06d 3157 temp=get_reg(i_regs->regmap,agr);
3158 if(temp<0) temp=get_reg(i_regs->regmap,-1);
57871462 3159 offset=imm[i];
3160 if(s>=0) {
3161 c=(i_regs->isconst>>s)&1;
af4ee1fe 3162 if(c) {
3163 memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
af4ee1fe 3164 }
57871462 3165 }
3166 assert(tl>=0);
535d208a 3167 assert(temp>=0);
1edfcc68 3168 if(!c) {
3169 emit_cmpimm(s<0||offset?temp:s,RAM_SIZE);
3170 if(!offset&&s!=temp) emit_mov(s,temp);
b14b6a8f 3171 jaddr=out;
1edfcc68 3172 emit_jno(0);
3173 }
3174 else
3175 {
cf95b4f0 3176 if(!memtarget||!dops[i].rs1) {
b14b6a8f 3177 jaddr=out;
535d208a 3178 emit_jmp(0);
57871462 3179 }
535d208a 3180 }
37387d8b 3181 if (ram_offset)
3182 offset_reg = get_ro_reg(i_regs, 0);
535d208a 3183
cf95b4f0 3184 if (dops[i].opcode==0x2C||dops[i].opcode==0x2D) { // SDL/SDR
9c45ca93 3185 assert(0);
535d208a 3186 }
57871462 3187
535d208a 3188 emit_testimm(temp,2);
37387d8b 3189 case23=out;
535d208a 3190 emit_jne(0);
3191 emit_testimm(temp,1);
df4dc2b1 3192 case1=out;
535d208a 3193 emit_jne(0);
3194 // 0
37387d8b 3195 if (dops[i].opcode == 0x2A) { // SWL
3196 // Write msb into least significant byte
3197 if (dops[i].rs2) emit_rorimm(tl, 24, tl);
3198 do_store_byte(temp, tl, offset_reg);
3199 if (dops[i].rs2) emit_rorimm(tl, 8, tl);
535d208a 3200 }
37387d8b 3201 else if (dops[i].opcode == 0x2E) { // SWR
3202 // Write entire word
3203 do_store_word(temp, 0, tl, offset_reg, 1);
535d208a 3204 }
37387d8b 3205 done0 = out;
535d208a 3206 emit_jmp(0);
3207 // 1
df4dc2b1 3208 set_jump_target(case1, out);
37387d8b 3209 if (dops[i].opcode == 0x2A) { // SWL
3210 // Write two msb into two least significant bytes
3211 if (dops[i].rs2) emit_rorimm(tl, 16, tl);
3212 do_store_hword(temp, -1, tl, offset_reg, 0);
3213 if (dops[i].rs2) emit_rorimm(tl, 16, tl);
535d208a 3214 }
37387d8b 3215 else if (dops[i].opcode == 0x2E) { // SWR
3216 // Write 3 lsb into three most significant bytes
3217 do_store_byte(temp, tl, offset_reg);
3218 if (dops[i].rs2) emit_rorimm(tl, 8, tl);
3219 do_store_hword(temp, 1, tl, offset_reg, 0);
3220 if (dops[i].rs2) emit_rorimm(tl, 24, tl);
535d208a 3221 }
df4dc2b1 3222 done1=out;
535d208a 3223 emit_jmp(0);
37387d8b 3224 // 2,3
3225 set_jump_target(case23, out);
535d208a 3226 emit_testimm(temp,1);
37387d8b 3227 case3 = out;
535d208a 3228 emit_jne(0);
37387d8b 3229 // 2
cf95b4f0 3230 if (dops[i].opcode==0x2A) { // SWL
37387d8b 3231 // Write 3 msb into three least significant bytes
3232 if (dops[i].rs2) emit_rorimm(tl, 8, tl);
3233 do_store_hword(temp, -2, tl, offset_reg, 1);
3234 if (dops[i].rs2) emit_rorimm(tl, 16, tl);
3235 do_store_byte(temp, tl, offset_reg);
3236 if (dops[i].rs2) emit_rorimm(tl, 8, tl);
535d208a 3237 }
37387d8b 3238 else if (dops[i].opcode == 0x2E) { // SWR
3239 // Write two lsb into two most significant bytes
3240 do_store_hword(temp, 0, tl, offset_reg, 1);
535d208a 3241 }
37387d8b 3242 done2 = out;
535d208a 3243 emit_jmp(0);
3244 // 3
df4dc2b1 3245 set_jump_target(case3, out);
37387d8b 3246 if (dops[i].opcode == 0x2A) { // SWL
3247 do_store_word(temp, -3, tl, offset_reg, 0);
535d208a 3248 }
37387d8b 3249 else if (dops[i].opcode == 0x2E) { // SWR
3250 do_store_byte(temp, tl, offset_reg);
535d208a 3251 }
df4dc2b1 3252 set_jump_target(done0, out);
3253 set_jump_target(done1, out);
3254 set_jump_target(done2, out);
37387d8b 3255 if (offset_reg == HOST_TEMPREG)
3256 host_tempreg_release();
535d208a 3257 if(!c||!memtarget)
2330734f 3258 add_stub_r(STORELR_STUB,jaddr,out,i,temp,i_regs,ccadj_,reglist);
cf95b4f0 3259 if(!(i_regs->waswritten&(1<<dops[i].rs1)) && !HACK_ENABLED(NDHACK_NO_SMC_CHECK)) {
57871462 3260 #if defined(HOST_IMM8)
3261 int ir=get_reg(i_regs->regmap,INVCP);
3262 assert(ir>=0);
3263 emit_cmpmem_indexedsr12_reg(ir,temp,1);
3264 #else
643aeae3 3265 emit_cmpmem_indexedsr12_imm(invalid_code,temp,1);
57871462 3266 #endif
535d208a 3267 #if defined(HAVE_CONDITIONAL_CALL) && !defined(DESTRUCTIVE_SHIFT)
3268 emit_callne(invalidate_addr_reg[temp]);
3269 #else
b14b6a8f 3270 void *jaddr2 = out;
57871462 3271 emit_jne(0);
b14b6a8f 3272 add_stub(INVCODE_STUB,jaddr2,out,reglist|(1<<HOST_CCREG),temp,0,0,0);
535d208a 3273 #endif
57871462 3274 }
57871462 3275}
3276
2330734f 3277static void cop0_assemble(int i, const struct regstat *i_regs, int ccadj_)
8062d65a 3278{
cf95b4f0 3279 if(dops[i].opcode2==0) // MFC0
8062d65a 3280 {
cf95b4f0 3281 signed char t=get_reg(i_regs->regmap,dops[i].rt1);
8062d65a 3282 u_int copr=(source[i]>>11)&0x1f;
3283 //assert(t>=0); // Why does this happen? OOT is weird
cf95b4f0 3284 if(t>=0&&dops[i].rt1!=0) {
8062d65a 3285 emit_readword(&reg_cop0[copr],t);
3286 }
3287 }
cf95b4f0 3288 else if(dops[i].opcode2==4) // MTC0
8062d65a 3289 {
cf95b4f0 3290 signed char s=get_reg(i_regs->regmap,dops[i].rs1);
8062d65a 3291 char copr=(source[i]>>11)&0x1f;
3292 assert(s>=0);
cf95b4f0 3293 wb_register(dops[i].rs1,i_regs->regmap,i_regs->dirty);
8062d65a 3294 if(copr==9||copr==11||copr==12||copr==13) {
3295 emit_readword(&last_count,HOST_TEMPREG);
3296 emit_loadreg(CCREG,HOST_CCREG); // TODO: do proper reg alloc
3297 emit_add(HOST_CCREG,HOST_TEMPREG,HOST_CCREG);
2330734f 3298 emit_addimm(HOST_CCREG,ccadj_,HOST_CCREG);
8062d65a 3299 emit_writeword(HOST_CCREG,&Count);
3300 }
3301 // What a mess. The status register (12) can enable interrupts,
3302 // so needs a special case to handle a pending interrupt.
3303 // The interrupt must be taken immediately, because a subsequent
3304 // instruction might disable interrupts again.
3305 if(copr==12||copr==13) {
3306 if (is_delayslot) {
3307 // burn cycles to cause cc_interrupt, which will
3308 // reschedule next_interupt. Relies on CCREG from above.
3309 assem_debug("MTC0 DS %d\n", copr);
3310 emit_writeword(HOST_CCREG,&last_count);
3311 emit_movimm(0,HOST_CCREG);
3312 emit_storereg(CCREG,HOST_CCREG);
cf95b4f0 3313 emit_loadreg(dops[i].rs1,1);
8062d65a 3314 emit_movimm(copr,0);
2a014d73 3315 emit_far_call(pcsx_mtc0_ds);
cf95b4f0 3316 emit_loadreg(dops[i].rs1,s);
8062d65a 3317 return;
3318 }
3319 emit_movimm(start+i*4+4,HOST_TEMPREG);
3320 emit_writeword(HOST_TEMPREG,&pcaddr);
3321 emit_movimm(0,HOST_TEMPREG);
3322 emit_writeword(HOST_TEMPREG,&pending_exception);
3323 }
8062d65a 3324 if(s==HOST_CCREG)
cf95b4f0 3325 emit_loadreg(dops[i].rs1,1);
8062d65a 3326 else if(s!=1)
3327 emit_mov(s,1);
3328 emit_movimm(copr,0);
2a014d73 3329 emit_far_call(pcsx_mtc0);
8062d65a 3330 if(copr==9||copr==11||copr==12||copr==13) {
3331 emit_readword(&Count,HOST_CCREG);
3332 emit_readword(&next_interupt,HOST_TEMPREG);
2330734f 3333 emit_addimm(HOST_CCREG,-ccadj_,HOST_CCREG);
8062d65a 3334 emit_sub(HOST_CCREG,HOST_TEMPREG,HOST_CCREG);
3335 emit_writeword(HOST_TEMPREG,&last_count);
3336 emit_storereg(CCREG,HOST_CCREG);
3337 }
3338 if(copr==12||copr==13) {
3339 assert(!is_delayslot);
3340 emit_readword(&pending_exception,14);
3341 emit_test(14,14);
d1e4ebd9 3342 void *jaddr = out;
3343 emit_jeq(0);
3344 emit_readword(&pcaddr, 0);
3345 emit_addimm(HOST_CCREG,2,HOST_CCREG);
2a014d73 3346 emit_far_call(get_addr_ht);
d1e4ebd9 3347 emit_jmpreg(0);
3348 set_jump_target(jaddr, out);
8062d65a 3349 }
cf95b4f0 3350 emit_loadreg(dops[i].rs1,s);
8062d65a 3351 }
3352 else
3353 {
cf95b4f0 3354 assert(dops[i].opcode2==0x10);
8062d65a 3355 //if((source[i]&0x3f)==0x10) // RFE
3356 {
3357 emit_readword(&Status,0);
3358 emit_andimm(0,0x3c,1);
3359 emit_andimm(0,~0xf,0);
3360 emit_orrshr_imm(1,2,0);
3361 emit_writeword(0,&Status);
3362 }
3363 }
3364}
3365
2330734f 3366static void cop1_unusable(int i, const struct regstat *i_regs)
8062d65a 3367{
3368 // XXX: should just just do the exception instead
3369 //if(!cop1_usable)
3370 {
3371 void *jaddr=out;
3372 emit_jmp(0);
3373 add_stub_r(FP_STUB,jaddr,out,i,0,i_regs,is_delayslot,0);
3374 }
3375}
3376
2330734f 3377static void cop1_assemble(int i, const struct regstat *i_regs)
8062d65a 3378{
3379 cop1_unusable(i, i_regs);
3380}
3381
2330734f 3382static void c1ls_assemble(int i, const struct regstat *i_regs)
57871462 3383{
3d624f89 3384 cop1_unusable(i, i_regs);
57871462 3385}
3386
8062d65a 3387// FP_STUB
3388static void do_cop1stub(int n)
3389{
3390 literal_pool(256);
3391 assem_debug("do_cop1stub %x\n",start+stubs[n].a*4);
3392 set_jump_target(stubs[n].addr, out);
3393 int i=stubs[n].a;
3394// int rs=stubs[n].b;
3395 struct regstat *i_regs=(struct regstat *)stubs[n].c;
3396 int ds=stubs[n].d;
3397 if(!ds) {
3398 load_all_consts(regs[i].regmap_entry,regs[i].wasdirty,i);
3399 //if(i_regs!=&regs[i]) printf("oops: regs[i]=%x i_regs=%x",(int)&regs[i],(int)i_regs);
3400 }
3401 //else {printf("fp exception in delay slot\n");}
3402 wb_dirtys(i_regs->regmap_entry,i_regs->wasdirty);
3403 if(regs[i].regmap_entry[HOST_CCREG]!=CCREG) emit_loadreg(CCREG,HOST_CCREG);
3404 emit_movimm(start+(i-ds)*4,EAX); // Get PC
2330734f 3405 emit_addimm(HOST_CCREG,ccadj[i],HOST_CCREG); // CHECK: is this right? There should probably be an extra cycle...
2a014d73 3406 emit_far_jump(ds?fp_exception_ds:fp_exception);
8062d65a 3407}
3408
e3c6bdb5 3409static int cop2_is_stalling_op(int i, int *cycles)
3410{
cf95b4f0 3411 if (dops[i].opcode == 0x3a) { // SWC2
e3c6bdb5 3412 *cycles = 0;
3413 return 1;
3414 }
cf95b4f0 3415 if (dops[i].itype == COP2 && (dops[i].opcode2 == 0 || dops[i].opcode2 == 2)) { // MFC2/CFC2
e3c6bdb5 3416 *cycles = 0;
3417 return 1;
3418 }
cf95b4f0 3419 if (dops[i].itype == C2OP) {
e3c6bdb5 3420 *cycles = gte_cycletab[source[i] & 0x3f];
3421 return 1;
3422 }
3423 // ... what about MTC2/CTC2/LWC2?
3424 return 0;
3425}
3426
3427#if 0
3428static void log_gte_stall(int stall, u_int cycle)
3429{
3430 if ((u_int)stall <= 44)
3431 printf("x stall %2d %u\n", stall, cycle + last_count);
e3c6bdb5 3432}
3433
3434static void emit_log_gte_stall(int i, int stall, u_int reglist)
3435{
3436 save_regs(reglist);
3437 if (stall > 0)
3438 emit_movimm(stall, 0);
3439 else
3440 emit_mov(HOST_TEMPREG, 0);
2330734f 3441 emit_addimm(HOST_CCREG, ccadj[i], 1);
e3c6bdb5 3442 emit_far_call(log_gte_stall);
3443 restore_regs(reglist);
3444}
3445#endif
3446
32631e6a 3447static void cop2_do_stall_check(u_int op, int i, const struct regstat *i_regs, u_int reglist)
81dbbf4c 3448{
e3c6bdb5 3449 int j = i, other_gte_op_cycles = -1, stall = -MAXBLOCK, cycles_passed;
3450 int rtmp = reglist_find_free(reglist);
3451
32631e6a 3452 if (HACK_ENABLED(NDHACK_NO_STALLS))
81dbbf4c 3453 return;
81dbbf4c 3454 if (get_reg(i_regs->regmap, CCREG) != HOST_CCREG) {
3455 // happens occasionally... cc evicted? Don't bother then
3456 //printf("no cc %08x\n", start + i*4);
3457 return;
3458 }
cf95b4f0 3459 if (!dops[i].bt) {
e3c6bdb5 3460 for (j = i - 1; j >= 0; j--) {
cf95b4f0 3461 //if (dops[j].is_ds) break;
3462 if (cop2_is_stalling_op(j, &other_gte_op_cycles) || dops[j].bt)
e3c6bdb5 3463 break;
2330734f 3464 if (j > 0 && ccadj[j - 1] > ccadj[j])
3465 break;
e3c6bdb5 3466 }
32631e6a 3467 j = max(j, 0);
e3c6bdb5 3468 }
2330734f 3469 cycles_passed = ccadj[i] - ccadj[j];
e3c6bdb5 3470 if (other_gte_op_cycles >= 0)
3471 stall = other_gte_op_cycles - cycles_passed;
3472 else if (cycles_passed >= 44)
3473 stall = 0; // can't stall
3474 if (stall == -MAXBLOCK && rtmp >= 0) {
3475 // unknown stall, do the expensive runtime check
32631e6a 3476 assem_debug("; cop2_do_stall_check\n");
e3c6bdb5 3477#if 0 // too slow
3478 save_regs(reglist);
3479 emit_movimm(gte_cycletab[op], 0);
2330734f 3480 emit_addimm(HOST_CCREG, ccadj[i], 1);
e3c6bdb5 3481 emit_far_call(call_gteStall);
3482 restore_regs(reglist);
3483#else
3484 host_tempreg_acquire();
3485 emit_readword(&psxRegs.gteBusyCycle, rtmp);
2330734f 3486 emit_addimm(rtmp, -ccadj[i], rtmp);
e3c6bdb5 3487 emit_sub(rtmp, HOST_CCREG, HOST_TEMPREG);
3488 emit_cmpimm(HOST_TEMPREG, 44);
3489 emit_cmovb_reg(rtmp, HOST_CCREG);
3490 //emit_log_gte_stall(i, 0, reglist);
3491 host_tempreg_release();
3492#endif
3493 }
3494 else if (stall > 0) {
3495 //emit_log_gte_stall(i, stall, reglist);
3496 emit_addimm(HOST_CCREG, stall, HOST_CCREG);
3497 }
3498
3499 // save gteBusyCycle, if needed
3500 if (gte_cycletab[op] == 0)
3501 return;
3502 other_gte_op_cycles = -1;
3503 for (j = i + 1; j < slen; j++) {
3504 if (cop2_is_stalling_op(j, &other_gte_op_cycles))
3505 break;
fe807a8a 3506 if (dops[j].is_jump) {
e3c6bdb5 3507 // check ds
3508 if (j + 1 < slen && cop2_is_stalling_op(j + 1, &other_gte_op_cycles))
3509 j++;
3510 break;
3511 }
3512 }
3513 if (other_gte_op_cycles >= 0)
3514 // will handle stall when assembling that op
3515 return;
2330734f 3516 cycles_passed = ccadj[min(j, slen -1)] - ccadj[i];
e3c6bdb5 3517 if (cycles_passed >= 44)
3518 return;
3519 assem_debug("; save gteBusyCycle\n");
3520 host_tempreg_acquire();
3521#if 0
3522 emit_readword(&last_count, HOST_TEMPREG);
3523 emit_add(HOST_TEMPREG, HOST_CCREG, HOST_TEMPREG);
2330734f 3524 emit_addimm(HOST_TEMPREG, ccadj[i], HOST_TEMPREG);
e3c6bdb5 3525 emit_addimm(HOST_TEMPREG, gte_cycletab[op]), HOST_TEMPREG);
3526 emit_writeword(HOST_TEMPREG, &psxRegs.gteBusyCycle);
3527#else
2330734f 3528 emit_addimm(HOST_CCREG, ccadj[i] + gte_cycletab[op], HOST_TEMPREG);
e3c6bdb5 3529 emit_writeword(HOST_TEMPREG, &psxRegs.gteBusyCycle);
3530#endif
3531 host_tempreg_release();
81dbbf4c 3532}
3533
32631e6a 3534static int is_mflohi(int i)
3535{
cf95b4f0 3536 return (dops[i].itype == MOV && (dops[i].rs1 == HIREG || dops[i].rs1 == LOREG));
32631e6a 3537}
3538
3539static int check_multdiv(int i, int *cycles)
3540{
cf95b4f0 3541 if (dops[i].itype != MULTDIV)
32631e6a 3542 return 0;
cf95b4f0 3543 if (dops[i].opcode2 == 0x18 || dops[i].opcode2 == 0x19) // MULT(U)
32631e6a 3544 *cycles = 11; // approx from 7 11 14
3545 else
3546 *cycles = 37;
3547 return 1;
3548}
3549
2330734f 3550static void multdiv_prepare_stall(int i, const struct regstat *i_regs, int ccadj_)
32631e6a 3551{
3552 int j, found = 0, c = 0;
3553 if (HACK_ENABLED(NDHACK_NO_STALLS))
3554 return;
3555 if (get_reg(i_regs->regmap, CCREG) != HOST_CCREG) {
3556 // happens occasionally... cc evicted? Don't bother then
3557 return;
3558 }
3559 for (j = i + 1; j < slen; j++) {
cf95b4f0 3560 if (dops[j].bt)
32631e6a 3561 break;
3562 if ((found = is_mflohi(j)))
3563 break;
fe807a8a 3564 if (dops[j].is_jump) {
32631e6a 3565 // check ds
3566 if (j + 1 < slen && (found = is_mflohi(j + 1)))
3567 j++;
3568 break;
3569 }
3570 }
3571 if (found)
3572 // handle all in multdiv_do_stall()
3573 return;
3574 check_multdiv(i, &c);
3575 assert(c > 0);
3576 assem_debug("; muldiv prepare stall %d\n", c);
3577 host_tempreg_acquire();
2330734f 3578 emit_addimm(HOST_CCREG, ccadj_ + c, HOST_TEMPREG);
32631e6a 3579 emit_writeword(HOST_TEMPREG, &psxRegs.muldivBusyCycle);
3580 host_tempreg_release();
3581}
3582
3583static void multdiv_do_stall(int i, const struct regstat *i_regs)
3584{
3585 int j, known_cycles = 0;
3586 u_int reglist = get_host_reglist(i_regs->regmap);
3587 int rtmp = get_reg(i_regs->regmap, -1);
3588 if (rtmp < 0)
3589 rtmp = reglist_find_free(reglist);
3590 if (HACK_ENABLED(NDHACK_NO_STALLS))
3591 return;
3592 if (get_reg(i_regs->regmap, CCREG) != HOST_CCREG || rtmp < 0) {
3593 // happens occasionally... cc evicted? Don't bother then
3594 //printf("no cc/rtmp %08x\n", start + i*4);
3595 return;
3596 }
cf95b4f0 3597 if (!dops[i].bt) {
32631e6a 3598 for (j = i - 1; j >= 0; j--) {
cf95b4f0 3599 if (dops[j].is_ds) break;
2330734f 3600 if (check_multdiv(j, &known_cycles))
32631e6a 3601 break;
3602 if (is_mflohi(j))
3603 // already handled by this op
3604 return;
2330734f 3605 if (dops[j].bt || (j > 0 && ccadj[j - 1] > ccadj[j]))
3606 break;
32631e6a 3607 }
3608 j = max(j, 0);
3609 }
3610 if (known_cycles > 0) {
2330734f 3611 known_cycles -= ccadj[i] - ccadj[j];
32631e6a 3612 assem_debug("; muldiv stall resolved %d\n", known_cycles);
3613 if (known_cycles > 0)
3614 emit_addimm(HOST_CCREG, known_cycles, HOST_CCREG);
3615 return;
3616 }
3617 assem_debug("; muldiv stall unresolved\n");
3618 host_tempreg_acquire();
3619 emit_readword(&psxRegs.muldivBusyCycle, rtmp);
2330734f 3620 emit_addimm(rtmp, -ccadj[i], rtmp);
32631e6a 3621 emit_sub(rtmp, HOST_CCREG, HOST_TEMPREG);
3622 emit_cmpimm(HOST_TEMPREG, 37);
3623 emit_cmovb_reg(rtmp, HOST_CCREG);
3624 //emit_log_gte_stall(i, 0, reglist);
3625 host_tempreg_release();
3626}
3627
8062d65a 3628static void cop2_get_dreg(u_int copr,signed char tl,signed char temp)
3629{
3630 switch (copr) {
3631 case 1:
3632 case 3:
3633 case 5:
3634 case 8:
3635 case 9:
3636 case 10:
3637 case 11:
3638 emit_readword(&reg_cop2d[copr],tl);
3639 emit_signextend16(tl,tl);
3640 emit_writeword(tl,&reg_cop2d[copr]); // hmh
3641 break;
3642 case 7:
3643 case 16:
3644 case 17:
3645 case 18:
3646 case 19:
3647 emit_readword(&reg_cop2d[copr],tl);
3648 emit_andimm(tl,0xffff,tl);
3649 emit_writeword(tl,&reg_cop2d[copr]);
3650 break;
3651 case 15:
3652 emit_readword(&reg_cop2d[14],tl); // SXY2
3653 emit_writeword(tl,&reg_cop2d[copr]);
3654 break;
3655 case 28:
3656 case 29:
3968e69e 3657 c2op_mfc2_29_assemble(tl,temp);
8062d65a 3658 break;
3659 default:
3660 emit_readword(&reg_cop2d[copr],tl);
3661 break;
3662 }
3663}
3664
3665static void cop2_put_dreg(u_int copr,signed char sl,signed char temp)
3666{
3667 switch (copr) {
3668 case 15:
3669 emit_readword(&reg_cop2d[13],temp); // SXY1
3670 emit_writeword(sl,&reg_cop2d[copr]);
3671 emit_writeword(temp,&reg_cop2d[12]); // SXY0
3672 emit_readword(&reg_cop2d[14],temp); // SXY2
3673 emit_writeword(sl,&reg_cop2d[14]);
3674 emit_writeword(temp,&reg_cop2d[13]); // SXY1
3675 break;
3676 case 28:
3677 emit_andimm(sl,0x001f,temp);
3678 emit_shlimm(temp,7,temp);
3679 emit_writeword(temp,&reg_cop2d[9]);
3680 emit_andimm(sl,0x03e0,temp);
3681 emit_shlimm(temp,2,temp);
3682 emit_writeword(temp,&reg_cop2d[10]);
3683 emit_andimm(sl,0x7c00,temp);
3684 emit_shrimm(temp,3,temp);
3685 emit_writeword(temp,&reg_cop2d[11]);
3686 emit_writeword(sl,&reg_cop2d[28]);
3687 break;
3688 case 30:
3968e69e 3689 emit_xorsar_imm(sl,sl,31,temp);
be516ebe 3690#if defined(HAVE_ARMV5) || defined(__aarch64__)
8062d65a 3691 emit_clz(temp,temp);
3692#else
3693 emit_movs(temp,HOST_TEMPREG);
3694 emit_movimm(0,temp);
3695 emit_jeq((int)out+4*4);
3696 emit_addpl_imm(temp,1,temp);
3697 emit_lslpls_imm(HOST_TEMPREG,1,HOST_TEMPREG);
3698 emit_jns((int)out-2*4);
3699#endif
3700 emit_writeword(sl,&reg_cop2d[30]);
3701 emit_writeword(temp,&reg_cop2d[31]);
3702 break;
3703 case 31:
3704 break;
3705 default:
3706 emit_writeword(sl,&reg_cop2d[copr]);
3707 break;
3708 }
3709}
3710
2330734f 3711static void c2ls_assemble(int i, const struct regstat *i_regs, int ccadj_)
b9b61529 3712{
3713 int s,tl;
3714 int ar;
3715 int offset;
1fd1aceb 3716 int memtarget=0,c=0;
b14b6a8f 3717 void *jaddr2=NULL;
3718 enum stub_type type;
b9b61529 3719 int agr=AGEN1+(i&1);
37387d8b 3720 int offset_reg = -1;
3721 int fastio_reg_override = -1;
81dbbf4c 3722 u_int reglist=get_host_reglist(i_regs->regmap);
b9b61529 3723 u_int copr=(source[i]>>16)&0x1f;
cf95b4f0 3724 s=get_reg(i_regs->regmap,dops[i].rs1);
b9b61529 3725 tl=get_reg(i_regs->regmap,FTEMP);
3726 offset=imm[i];
cf95b4f0 3727 assert(dops[i].rs1>0);
b9b61529 3728 assert(tl>=0);
b9b61529 3729
b9b61529 3730 if(i_regs->regmap[HOST_CCREG]==CCREG)
3731 reglist&=~(1<<HOST_CCREG);
3732
3733 // get the address
cf95b4f0 3734 if (dops[i].opcode==0x3a) { // SWC2
b9b61529 3735 ar=get_reg(i_regs->regmap,agr);
3736 if(ar<0) ar=get_reg(i_regs->regmap,-1);
3737 reglist|=1<<ar;
3738 } else { // LWC2
3739 ar=tl;
3740 }
1fd1aceb 3741 if(s>=0) c=(i_regs->wasconst>>s)&1;
3742 memtarget=c&&(((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE);
b9b61529 3743 if (!offset&&!c&&s>=0) ar=s;
3744 assert(ar>=0);
3745
32631e6a 3746 cop2_do_stall_check(0, i, i_regs, reglist);
3747
cf95b4f0 3748 if (dops[i].opcode==0x3a) { // SWC2
3968e69e 3749 cop2_get_dreg(copr,tl,-1);
1fd1aceb 3750 type=STOREW_STUB;
b9b61529 3751 }
1fd1aceb 3752 else
b9b61529 3753 type=LOADW_STUB;
1fd1aceb 3754
3755 if(c&&!memtarget) {
b14b6a8f 3756 jaddr2=out;
1fd1aceb 3757 emit_jmp(0); // inline_readstub/inline_writestub?
b9b61529 3758 }
1fd1aceb 3759 else {
3760 if(!c) {
37387d8b 3761 jaddr2 = emit_fastpath_cmp_jump(i, i_regs, ar,
3762 &offset_reg, &fastio_reg_override);
3763 }
3764 else if (ram_offset && memtarget) {
3765 offset_reg = get_ro_reg(i_regs, 0);
3766 }
3767 switch (dops[i].opcode) {
3768 case 0x32: { // LWC2
3769 int a = ar;
3770 if (fastio_reg_override >= 0)
3771 a = fastio_reg_override;
3772 do_load_word(a, tl, offset_reg);
3773 break;
1fd1aceb 3774 }
37387d8b 3775 case 0x3a: { // SWC2
1fd1aceb 3776 #ifdef DESTRUCTIVE_SHIFT
3777 if(!offset&&!c&&s>=0) emit_mov(s,ar);
3778 #endif
37387d8b 3779 int a = ar;
3780 if (fastio_reg_override >= 0)
3781 a = fastio_reg_override;
3782 do_store_word(a, 0, tl, offset_reg, 1);
3783 break;
3784 }
3785 default:
3786 assert(0);
1fd1aceb 3787 }
b9b61529 3788 }
37387d8b 3789 if (fastio_reg_override == HOST_TEMPREG || offset_reg == HOST_TEMPREG)
d1e4ebd9 3790 host_tempreg_release();
b9b61529 3791 if(jaddr2)
2330734f 3792 add_stub_r(type,jaddr2,out,i,ar,i_regs,ccadj_,reglist);
cf95b4f0 3793 if(dops[i].opcode==0x3a) // SWC2
3794 if(!(i_regs->waswritten&(1<<dops[i].rs1)) && !HACK_ENABLED(NDHACK_NO_SMC_CHECK)) {
b9b61529 3795#if defined(HOST_IMM8)
3796 int ir=get_reg(i_regs->regmap,INVCP);
3797 assert(ir>=0);
3798 emit_cmpmem_indexedsr12_reg(ir,ar,1);
3799#else
643aeae3 3800 emit_cmpmem_indexedsr12_imm(invalid_code,ar,1);
b9b61529 3801#endif
0bbd1454 3802 #if defined(HAVE_CONDITIONAL_CALL) && !defined(DESTRUCTIVE_SHIFT)
3803 emit_callne(invalidate_addr_reg[ar]);
3804 #else
b14b6a8f 3805 void *jaddr3 = out;
b9b61529 3806 emit_jne(0);
b14b6a8f 3807 add_stub(INVCODE_STUB,jaddr3,out,reglist|(1<<HOST_CCREG),ar,0,0,0);
0bbd1454 3808 #endif
b9b61529 3809 }
cf95b4f0 3810 if (dops[i].opcode==0x32) { // LWC2
d1e4ebd9 3811 host_tempreg_acquire();
b9b61529 3812 cop2_put_dreg(copr,tl,HOST_TEMPREG);
d1e4ebd9 3813 host_tempreg_release();
b9b61529 3814 }
3815}
3816
81dbbf4c 3817static void cop2_assemble(int i, const struct regstat *i_regs)
8062d65a 3818{
81dbbf4c 3819 u_int copr = (source[i]>>11) & 0x1f;
3820 signed char temp = get_reg(i_regs->regmap, -1);
3821
32631e6a 3822 if (!HACK_ENABLED(NDHACK_NO_STALLS)) {
3823 u_int reglist = reglist_exclude(get_host_reglist(i_regs->regmap), temp, -1);
cf95b4f0 3824 if (dops[i].opcode2 == 0 || dops[i].opcode2 == 2) { // MFC2/CFC2
3825 signed char tl = get_reg(i_regs->regmap, dops[i].rt1);
32631e6a 3826 reglist = reglist_exclude(reglist, tl, -1);
81dbbf4c 3827 }
32631e6a 3828 cop2_do_stall_check(0, i, i_regs, reglist);
81dbbf4c 3829 }
cf95b4f0 3830 if (dops[i].opcode2==0) { // MFC2
3831 signed char tl=get_reg(i_regs->regmap,dops[i].rt1);
3832 if(tl>=0&&dops[i].rt1!=0)
8062d65a 3833 cop2_get_dreg(copr,tl,temp);
3834 }
cf95b4f0 3835 else if (dops[i].opcode2==4) { // MTC2
3836 signed char sl=get_reg(i_regs->regmap,dops[i].rs1);
8062d65a 3837 cop2_put_dreg(copr,sl,temp);
3838 }
cf95b4f0 3839 else if (dops[i].opcode2==2) // CFC2
8062d65a 3840 {
cf95b4f0 3841 signed char tl=get_reg(i_regs->regmap,dops[i].rt1);
3842 if(tl>=0&&dops[i].rt1!=0)
8062d65a 3843 emit_readword(&reg_cop2c[copr],tl);
3844 }
cf95b4f0 3845 else if (dops[i].opcode2==6) // CTC2
8062d65a 3846 {
cf95b4f0 3847 signed char sl=get_reg(i_regs->regmap,dops[i].rs1);
8062d65a 3848 switch(copr) {
3849 case 4:
3850 case 12:
3851 case 20:
3852 case 26:
3853 case 27:
3854 case 29:
3855 case 30:
3856 emit_signextend16(sl,temp);
3857 break;
3858 case 31:
3968e69e 3859 c2op_ctc2_31_assemble(sl,temp);
8062d65a 3860 break;
3861 default:
3862 temp=sl;
3863 break;
3864 }
3865 emit_writeword(temp,&reg_cop2c[copr]);
3866 assert(sl>=0);
3867 }
3868}
3869
3968e69e 3870static void do_unalignedwritestub(int n)
3871{
3872 assem_debug("do_unalignedwritestub %x\n",start+stubs[n].a*4);
3873 literal_pool(256);
3874 set_jump_target(stubs[n].addr, out);
3875
3876 int i=stubs[n].a;
3877 struct regstat *i_regs=(struct regstat *)stubs[n].c;
3878 int addr=stubs[n].b;
3879 u_int reglist=stubs[n].e;
3880 signed char *i_regmap=i_regs->regmap;
3881 int temp2=get_reg(i_regmap,FTEMP);
3882 int rt;
cf95b4f0 3883 rt=get_reg(i_regmap,dops[i].rs2);
3968e69e 3884 assert(rt>=0);
3885 assert(addr>=0);
cf95b4f0 3886 assert(dops[i].opcode==0x2a||dops[i].opcode==0x2e); // SWL/SWR only implemented
3968e69e 3887 reglist|=(1<<addr);
3888 reglist&=~(1<<temp2);
3889
3968e69e 3890 // don't bother with it and call write handler
3891 save_regs(reglist);
3892 pass_args(addr,rt);
3893 int cc=get_reg(i_regmap,CCREG);
3894 if(cc<0)
3895 emit_loadreg(CCREG,2);
2330734f 3896 emit_addimm(cc<0?2:cc,(int)stubs[n].d+1,2);
cf95b4f0 3897 emit_far_call((dops[i].opcode==0x2a?jump_handle_swl:jump_handle_swr));
2330734f 3898 emit_addimm(0,-((int)stubs[n].d+1),cc<0?2:cc);
3968e69e 3899 if(cc<0)
3900 emit_storereg(CCREG,2);
3901 restore_regs(reglist);
3902 emit_jmp(stubs[n].retaddr); // return address
3968e69e 3903}
3904
57871462 3905#ifndef multdiv_assemble
3906void multdiv_assemble(int i,struct regstat *i_regs)
3907{
3908 printf("Need multdiv_assemble for this architecture.\n");
7c3a5182 3909 abort();
57871462 3910}
3911#endif
3912
2330734f 3913static void mov_assemble(int i, const struct regstat *i_regs)
57871462 3914{
cf95b4f0 3915 //if(dops[i].opcode2==0x10||dops[i].opcode2==0x12) { // MFHI/MFLO
3916 //if(dops[i].opcode2==0x11||dops[i].opcode2==0x13) { // MTHI/MTLO
3917 if(dops[i].rt1) {
7c3a5182 3918 signed char sl,tl;
cf95b4f0 3919 tl=get_reg(i_regs->regmap,dops[i].rt1);
57871462 3920 //assert(tl>=0);
3921 if(tl>=0) {
cf95b4f0 3922 sl=get_reg(i_regs->regmap,dops[i].rs1);
57871462 3923 if(sl>=0) emit_mov(sl,tl);
cf95b4f0 3924 else emit_loadreg(dops[i].rs1,tl);
57871462 3925 }
3926 }
cf95b4f0 3927 if (dops[i].rs1 == HIREG || dops[i].rs1 == LOREG) // MFHI/MFLO
32631e6a 3928 multdiv_do_stall(i, i_regs);
57871462 3929}
3930
3968e69e 3931// call interpreter, exception handler, things that change pc/regs/cycles ...
2330734f 3932static void call_c_cpu_handler(int i, const struct regstat *i_regs, int ccadj_, u_int pc, void *func)
57871462 3933{
3934 signed char ccreg=get_reg(i_regs->regmap,CCREG);
3935 assert(ccreg==HOST_CCREG);
3936 assert(!is_delayslot);
581335b0 3937 (void)ccreg;
3968e69e 3938
3939 emit_movimm(pc,3); // Get PC
3940 emit_readword(&last_count,2);
3941 emit_writeword(3,&psxRegs.pc);
2330734f 3942 emit_addimm(HOST_CCREG,ccadj_,HOST_CCREG);
3968e69e 3943 emit_add(2,HOST_CCREG,2);
3944 emit_writeword(2,&psxRegs.cycle);
2a014d73 3945 emit_far_call(func);
3946 emit_far_jump(jump_to_new_pc);
3968e69e 3947}
3948
2330734f 3949static void syscall_assemble(int i, const struct regstat *i_regs, int ccadj_)
3968e69e 3950{
d1150cd6 3951 // 'break' tends to be littered around to catch things like
3952 // division by 0 and is almost never executed, so don't emit much code here
3953 void *func = (dops[i].opcode2 == 0x0C)
3954 ? (is_delayslot ? jump_syscall_ds : jump_syscall)
3955 : (is_delayslot ? jump_break_ds : jump_break);
2acc46cd 3956 assert(get_reg(i_regs->regmap, CCREG) == HOST_CCREG);
d1150cd6 3957 emit_movimm(start + i*4, 2); // pc
3958 emit_addimm(HOST_CCREG, ccadj_ + CLOCK_ADJUST(1), HOST_CCREG);
3959 emit_far_jump(func);
7139f3c8 3960}
3961
2330734f 3962static void hlecall_assemble(int i, const struct regstat *i_regs, int ccadj_)
7139f3c8 3963{
3968e69e 3964 void *hlefunc = psxNULL;
dd79da89 3965 uint32_t hleCode = source[i] & 0x03ffffff;
3968e69e 3966 if (hleCode < ARRAY_SIZE(psxHLEt))
3967 hlefunc = psxHLEt[hleCode];
3968
2330734f 3969 call_c_cpu_handler(i, i_regs, ccadj_, start + i*4+4, hlefunc);
57871462 3970}
3971
2330734f 3972static void intcall_assemble(int i, const struct regstat *i_regs, int ccadj_)
1e973cb0 3973{
2330734f 3974 call_c_cpu_handler(i, i_regs, ccadj_, start + i*4, execI);
1e973cb0 3975}
3976
8062d65a 3977static void speculate_mov(int rs,int rt)
3978{
3979 if(rt!=0) {
3980 smrv_strong_next|=1<<rt;
3981 smrv[rt]=smrv[rs];
3982 }
3983}
3984
3985static void speculate_mov_weak(int rs,int rt)
3986{
3987 if(rt!=0) {
3988 smrv_weak_next|=1<<rt;
3989 smrv[rt]=smrv[rs];
3990 }
3991}
3992
3993static void speculate_register_values(int i)
3994{
3995 if(i==0) {
3996 memcpy(smrv,psxRegs.GPR.r,sizeof(smrv));
3997 // gp,sp are likely to stay the same throughout the block
3998 smrv_strong_next=(1<<28)|(1<<29)|(1<<30);
3999 smrv_weak_next=~smrv_strong_next;
4000 //printf(" llr %08x\n", smrv[4]);
4001 }
4002 smrv_strong=smrv_strong_next;
4003 smrv_weak=smrv_weak_next;
cf95b4f0 4004 switch(dops[i].itype) {
8062d65a 4005 case ALU:
cf95b4f0 4006 if ((smrv_strong>>dops[i].rs1)&1) speculate_mov(dops[i].rs1,dops[i].rt1);
4007 else if((smrv_strong>>dops[i].rs2)&1) speculate_mov(dops[i].rs2,dops[i].rt1);
4008 else if((smrv_weak>>dops[i].rs1)&1) speculate_mov_weak(dops[i].rs1,dops[i].rt1);
4009 else if((smrv_weak>>dops[i].rs2)&1) speculate_mov_weak(dops[i].rs2,dops[i].rt1);
8062d65a 4010 else {
cf95b4f0 4011 smrv_strong_next&=~(1<<dops[i].rt1);
4012 smrv_weak_next&=~(1<<dops[i].rt1);
8062d65a 4013 }
4014 break;
4015 case SHIFTIMM:
cf95b4f0 4016 smrv_strong_next&=~(1<<dops[i].rt1);
4017 smrv_weak_next&=~(1<<dops[i].rt1);
8062d65a 4018 // fallthrough
4019 case IMM16:
cf95b4f0 4020 if(dops[i].rt1&&is_const(&regs[i],dops[i].rt1)) {
4021 int value,hr=get_reg(regs[i].regmap,dops[i].rt1);
8062d65a 4022 if(hr>=0) {
4023 if(get_final_value(hr,i,&value))
cf95b4f0 4024 smrv[dops[i].rt1]=value;
4025 else smrv[dops[i].rt1]=constmap[i][hr];
4026 smrv_strong_next|=1<<dops[i].rt1;
8062d65a 4027 }
4028 }
4029 else {
cf95b4f0 4030 if ((smrv_strong>>dops[i].rs1)&1) speculate_mov(dops[i].rs1,dops[i].rt1);
4031 else if((smrv_weak>>dops[i].rs1)&1) speculate_mov_weak(dops[i].rs1,dops[i].rt1);
8062d65a 4032 }
4033 break;
4034 case LOAD:
cf95b4f0 4035 if(start<0x2000&&(dops[i].rt1==26||(smrv[dops[i].rt1]>>24)==0xa0)) {
8062d65a 4036 // special case for BIOS
cf95b4f0 4037 smrv[dops[i].rt1]=0xa0000000;
4038 smrv_strong_next|=1<<dops[i].rt1;
8062d65a 4039 break;
4040 }
4041 // fallthrough
4042 case SHIFT:
4043 case LOADLR:
4044 case MOV:
cf95b4f0 4045 smrv_strong_next&=~(1<<dops[i].rt1);
4046 smrv_weak_next&=~(1<<dops[i].rt1);
8062d65a 4047 break;
4048 case COP0:
4049 case COP2:
cf95b4f0 4050 if(dops[i].opcode2==0||dops[i].opcode2==2) { // MFC/CFC
4051 smrv_strong_next&=~(1<<dops[i].rt1);
4052 smrv_weak_next&=~(1<<dops[i].rt1);
8062d65a 4053 }
4054 break;
4055 case C2LS:
cf95b4f0 4056 if (dops[i].opcode==0x32) { // LWC2
4057 smrv_strong_next&=~(1<<dops[i].rt1);
4058 smrv_weak_next&=~(1<<dops[i].rt1);
8062d65a 4059 }
4060 break;
4061 }
4062#if 0
4063 int r=4;
4064 printf("x %08x %08x %d %d c %08x %08x\n",smrv[r],start+i*4,
4065 ((smrv_strong>>r)&1),(smrv_weak>>r)&1,regs[i].isconst,regs[i].wasconst);
4066#endif
4067}
4068
2330734f 4069static void ujump_assemble(int i, const struct regstat *i_regs);
4070static void rjump_assemble(int i, const struct regstat *i_regs);
4071static void cjump_assemble(int i, const struct regstat *i_regs);
4072static void sjump_assemble(int i, const struct regstat *i_regs);
4073static void pagespan_assemble(int i, const struct regstat *i_regs);
4074
4075static int assemble(int i, const struct regstat *i_regs, int ccadj_)
57871462 4076{
2330734f 4077 int ds = 0;
4078 switch (dops[i].itype) {
57871462 4079 case ALU:
2330734f 4080 alu_assemble(i, i_regs);
4081 break;
57871462 4082 case IMM16:
2330734f 4083 imm16_assemble(i, i_regs);
4084 break;
57871462 4085 case SHIFT:
2330734f 4086 shift_assemble(i, i_regs);
4087 break;
57871462 4088 case SHIFTIMM:
2330734f 4089 shiftimm_assemble(i, i_regs);
4090 break;
57871462 4091 case LOAD:
2330734f 4092 load_assemble(i, i_regs, ccadj_);
4093 break;
57871462 4094 case LOADLR:
2330734f 4095 loadlr_assemble(i, i_regs, ccadj_);
4096 break;
57871462 4097 case STORE:
2330734f 4098 store_assemble(i, i_regs, ccadj_);
4099 break;
57871462 4100 case STORELR:
2330734f 4101 storelr_assemble(i, i_regs, ccadj_);
4102 break;
57871462 4103 case COP0:
2330734f 4104 cop0_assemble(i, i_regs, ccadj_);
4105 break;
57871462 4106 case COP1:
2330734f 4107 cop1_assemble(i, i_regs);
4108 break;
57871462 4109 case C1LS:
2330734f 4110 c1ls_assemble(i, i_regs);
4111 break;
b9b61529 4112 case COP2:
2330734f 4113 cop2_assemble(i, i_regs);
4114 break;
b9b61529 4115 case C2LS:
2330734f 4116 c2ls_assemble(i, i_regs, ccadj_);
4117 break;
b9b61529 4118 case C2OP:
2330734f 4119 c2op_assemble(i, i_regs);
4120 break;
57871462 4121 case MULTDIV:
2330734f 4122 multdiv_assemble(i, i_regs);
4123 multdiv_prepare_stall(i, i_regs, ccadj_);
32631e6a 4124 break;
57871462 4125 case MOV:
2330734f 4126 mov_assemble(i, i_regs);
4127 break;
4128 case SYSCALL:
4129 syscall_assemble(i, i_regs, ccadj_);
4130 break;
4131 case HLECALL:
4132 hlecall_assemble(i, i_regs, ccadj_);
4133 break;
4134 case INTCALL:
4135 intcall_assemble(i, i_regs, ccadj_);
4136 break;
4137 case UJUMP:
4138 ujump_assemble(i, i_regs);
4139 ds = 1;
4140 break;
4141 case RJUMP:
4142 rjump_assemble(i, i_regs);
4143 ds = 1;
4144 break;
4145 case CJUMP:
4146 cjump_assemble(i, i_regs);
4147 ds = 1;
4148 break;
4149 case SJUMP:
4150 sjump_assemble(i, i_regs);
4151 ds = 1;
4152 break;
4153 case SPAN:
4154 pagespan_assemble(i, i_regs);
4155 break;
24058131 4156 case NOP:
2330734f 4157 case OTHER:
4158 case NI:
4159 // not handled, just skip
4160 break;
4161 default:
4162 assert(0);
4163 }
4164 return ds;
4165}
4166
4167static void ds_assemble(int i, const struct regstat *i_regs)
4168{
4169 speculate_register_values(i);
4170 is_delayslot = 1;
4171 switch (dops[i].itype) {
57871462 4172 case SYSCALL:
7139f3c8 4173 case HLECALL:
1e973cb0 4174 case INTCALL:
57871462 4175 case SPAN:
4176 case UJUMP:
4177 case RJUMP:
4178 case CJUMP:
4179 case SJUMP:
c43b5311 4180 SysPrintf("Jump in the delay slot. This is probably a bug.\n");
2330734f 4181 break;
4182 default:
4183 assemble(i, i_regs, ccadj[i]);
57871462 4184 }
2330734f 4185 is_delayslot = 0;
57871462 4186}
4187
4188// Is the branch target a valid internal jump?
ad49de89 4189static int internal_branch(int addr)
57871462 4190{
4191 if(addr&1) return 0; // Indirect (register) jump
4192 if(addr>=start && addr<start+slen*4-4)
4193 {
71e490c5 4194 return 1;
57871462 4195 }
4196 return 0;
4197}
4198
ad49de89 4199static void wb_invalidate(signed char pre[],signed char entry[],uint64_t dirty,uint64_t u)
57871462 4200{
4201 int hr;
4202 for(hr=0;hr<HOST_REGS;hr++) {
4203 if(hr!=EXCLUDE_REG) {
4204 if(pre[hr]!=entry[hr]) {
4205 if(pre[hr]>=0) {
4206 if((dirty>>hr)&1) {
4207 if(get_reg(entry,pre[hr])<0) {
00fa9369 4208 assert(pre[hr]<64);
4209 if(!((u>>pre[hr])&1))
4210 emit_storereg(pre[hr],hr);
57871462 4211 }
4212 }
4213 }
4214 }
4215 }
4216 }
4217 // Move from one register to another (no writeback)
4218 for(hr=0;hr<HOST_REGS;hr++) {
4219 if(hr!=EXCLUDE_REG) {
4220 if(pre[hr]!=entry[hr]) {
4221 if(pre[hr]>=0&&(pre[hr]&63)<TEMPREG) {
4222 int nr;
4223 if((nr=get_reg(entry,pre[hr]))>=0) {
4224 emit_mov(hr,nr);
4225 }
4226 }
4227 }
4228 }
4229 }
4230}
57871462 4231
4232// Load the specified registers
4233// This only loads the registers given as arguments because
4234// we don't want to load things that will be overwritten
ad49de89 4235static void load_regs(signed char entry[],signed char regmap[],int rs1,int rs2)
57871462 4236{
4237 int hr;
4238 // Load 32-bit regs
4239 for(hr=0;hr<HOST_REGS;hr++) {
4240 if(hr!=EXCLUDE_REG&&regmap[hr]>=0) {
4241 if(entry[hr]!=regmap[hr]) {
4242 if(regmap[hr]==rs1||regmap[hr]==rs2)
4243 {
4244 if(regmap[hr]==0) {
4245 emit_zeroreg(hr);
4246 }
4247 else
4248 {
4249 emit_loadreg(regmap[hr],hr);
4250 }
4251 }
4252 }
4253 }
4254 }
57871462 4255}
4256
4257// Load registers prior to the start of a loop
4258// so that they are not loaded within the loop
4259static void loop_preload(signed char pre[],signed char entry[])
4260{
4261 int hr;
4262 for(hr=0;hr<HOST_REGS;hr++) {
4263 if(hr!=EXCLUDE_REG) {
4264 if(pre[hr]!=entry[hr]) {
4265 if(entry[hr]>=0) {
4266 if(get_reg(pre,entry[hr])<0) {
4267 assem_debug("loop preload:\n");
4268 //printf("loop preload: %d\n",hr);
4269 if(entry[hr]==0) {
4270 emit_zeroreg(hr);
4271 }
4272 else if(entry[hr]<TEMPREG)
4273 {
4274 emit_loadreg(entry[hr],hr);
4275 }
4276 else if(entry[hr]-64<TEMPREG)
4277 {
4278 emit_loadreg(entry[hr],hr);
4279 }
4280 }
4281 }
4282 }
4283 }
4284 }
4285}
4286
4287// Generate address for load/store instruction
b9b61529 4288// goes to AGEN for writes, FTEMP for LOADLR and cop1/2 loads
2330734f 4289void address_generation(int i, const struct regstat *i_regs, signed char entry[])
57871462 4290{
37387d8b 4291 if (dops[i].is_load || dops[i].is_store) {
5194fb95 4292 int ra=-1;
57871462 4293 int agr=AGEN1+(i&1);
cf95b4f0 4294 if(dops[i].itype==LOAD) {
4295 ra=get_reg(i_regs->regmap,dops[i].rt1);
9f51b4b9 4296 if(ra<0) ra=get_reg(i_regs->regmap,-1);
535d208a 4297 assert(ra>=0);
57871462 4298 }
cf95b4f0 4299 if(dops[i].itype==LOADLR) {
57871462 4300 ra=get_reg(i_regs->regmap,FTEMP);
4301 }
cf95b4f0 4302 if(dops[i].itype==STORE||dops[i].itype==STORELR) {
57871462 4303 ra=get_reg(i_regs->regmap,agr);
4304 if(ra<0) ra=get_reg(i_regs->regmap,-1);
4305 }
37387d8b 4306 if(dops[i].itype==C2LS) {
cf95b4f0 4307 if ((dops[i].opcode&0x3b)==0x31||(dops[i].opcode&0x3b)==0x32) // LWC1/LDC1/LWC2/LDC2
57871462 4308 ra=get_reg(i_regs->regmap,FTEMP);
1fd1aceb 4309 else { // SWC1/SDC1/SWC2/SDC2
57871462 4310 ra=get_reg(i_regs->regmap,agr);
4311 if(ra<0) ra=get_reg(i_regs->regmap,-1);
4312 }
4313 }
cf95b4f0 4314 int rs=get_reg(i_regs->regmap,dops[i].rs1);
57871462 4315 if(ra>=0) {
4316 int offset=imm[i];
4317 int c=(i_regs->wasconst>>rs)&1;
cf95b4f0 4318 if(dops[i].rs1==0) {
57871462 4319 // Using r0 as a base address
57871462 4320 if(!entry||entry[ra]!=agr) {
cf95b4f0 4321 if (dops[i].opcode==0x22||dops[i].opcode==0x26) {
57871462 4322 emit_movimm(offset&0xFFFFFFFC,ra); // LWL/LWR
cf95b4f0 4323 }else if (dops[i].opcode==0x1a||dops[i].opcode==0x1b) {
57871462 4324 emit_movimm(offset&0xFFFFFFF8,ra); // LDL/LDR
4325 }else{
4326 emit_movimm(offset,ra);
4327 }
4328 } // else did it in the previous cycle
4329 }
4330 else if(rs<0) {
cf95b4f0 4331 if(!entry||entry[ra]!=dops[i].rs1)
4332 emit_loadreg(dops[i].rs1,ra);
4333 //if(!entry||entry[ra]!=dops[i].rs1)
57871462 4334 // printf("poor load scheduling!\n");
4335 }
4336 else if(c) {
cf95b4f0 4337 if(dops[i].rs1!=dops[i].rt1||dops[i].itype!=LOAD) {
57871462 4338 if(!entry||entry[ra]!=agr) {
cf95b4f0 4339 if (dops[i].opcode==0x22||dops[i].opcode==0x26) {
57871462 4340 emit_movimm((constmap[i][rs]+offset)&0xFFFFFFFC,ra); // LWL/LWR
cf95b4f0 4341 }else if (dops[i].opcode==0x1a||dops[i].opcode==0x1b) {
57871462 4342 emit_movimm((constmap[i][rs]+offset)&0xFFFFFFF8,ra); // LDL/LDR
4343 }else{
57871462 4344 emit_movimm(constmap[i][rs]+offset,ra);
8575a877 4345 regs[i].loadedconst|=1<<ra;
57871462 4346 }
4347 } // else did it in the previous cycle
4348 } // else load_consts already did it
4349 }
cf95b4f0 4350 if(offset&&!c&&dops[i].rs1) {
57871462 4351 if(rs>=0) {
4352 emit_addimm(rs,offset,ra);
4353 }else{
4354 emit_addimm(ra,offset,ra);
4355 }
4356 }
4357 }
4358 }
4359 // Preload constants for next instruction
37387d8b 4360 if (dops[i+1].is_load || dops[i+1].is_store) {
57871462 4361 int agr,ra;
57871462 4362 // Actual address
4363 agr=AGEN1+((i+1)&1);
4364 ra=get_reg(i_regs->regmap,agr);
4365 if(ra>=0) {
cf95b4f0 4366 int rs=get_reg(regs[i+1].regmap,dops[i+1].rs1);
57871462 4367 int offset=imm[i+1];
4368 int c=(regs[i+1].wasconst>>rs)&1;
cf95b4f0 4369 if(c&&(dops[i+1].rs1!=dops[i+1].rt1||dops[i+1].itype!=LOAD)) {
4370 if (dops[i+1].opcode==0x22||dops[i+1].opcode==0x26) {
57871462 4371 emit_movimm((constmap[i+1][rs]+offset)&0xFFFFFFFC,ra); // LWL/LWR
cf95b4f0 4372 }else if (dops[i+1].opcode==0x1a||dops[i+1].opcode==0x1b) {
57871462 4373 emit_movimm((constmap[i+1][rs]+offset)&0xFFFFFFF8,ra); // LDL/LDR
4374 }else{
57871462 4375 emit_movimm(constmap[i+1][rs]+offset,ra);
8575a877 4376 regs[i+1].loadedconst|=1<<ra;
57871462 4377 }
4378 }
cf95b4f0 4379 else if(dops[i+1].rs1==0) {
57871462 4380 // Using r0 as a base address
cf95b4f0 4381 if (dops[i+1].opcode==0x22||dops[i+1].opcode==0x26) {
57871462 4382 emit_movimm(offset&0xFFFFFFFC,ra); // LWL/LWR
cf95b4f0 4383 }else if (dops[i+1].opcode==0x1a||dops[i+1].opcode==0x1b) {
57871462 4384 emit_movimm(offset&0xFFFFFFF8,ra); // LDL/LDR
4385 }else{
4386 emit_movimm(offset,ra);
4387 }
4388 }
4389 }
4390 }
4391}
4392
e2b5e7aa 4393static int get_final_value(int hr, int i, int *value)
57871462 4394{
4395 int reg=regs[i].regmap[hr];
4396 while(i<slen-1) {
4397 if(regs[i+1].regmap[hr]!=reg) break;
4398 if(!((regs[i+1].isconst>>hr)&1)) break;
cf95b4f0 4399 if(dops[i+1].bt) break;
57871462 4400 i++;
4401 }
4402 if(i<slen-1) {
fe807a8a 4403 if (dops[i].is_jump) {
57871462 4404 *value=constmap[i][hr];
4405 return 1;
4406 }
cf95b4f0 4407 if(!dops[i+1].bt) {
fe807a8a 4408 if (dops[i+1].is_jump) {
57871462 4409 // Load in delay slot, out-of-order execution
cf95b4f0 4410 if(dops[i+2].itype==LOAD&&dops[i+2].rs1==reg&&dops[i+2].rt1==reg&&((regs[i+1].wasconst>>hr)&1))
57871462 4411 {
57871462 4412 // Precompute load address
4413 *value=constmap[i][hr]+imm[i+2];
4414 return 1;
4415 }
4416 }
cf95b4f0 4417 if(dops[i+1].itype==LOAD&&dops[i+1].rs1==reg&&dops[i+1].rt1==reg)
57871462 4418 {
57871462 4419 // Precompute load address
4420 *value=constmap[i][hr]+imm[i+1];
643aeae3 4421 //printf("c=%x imm=%lx\n",(long)constmap[i][hr],imm[i+1]);
57871462 4422 return 1;
4423 }
4424 }
4425 }
4426 *value=constmap[i][hr];
643aeae3 4427 //printf("c=%lx\n",(long)constmap[i][hr]);
57871462 4428 if(i==slen-1) return 1;
00fa9369 4429 assert(reg < 64);
4430 return !((unneeded_reg[i+1]>>reg)&1);
57871462 4431}
4432
4433// Load registers with known constants
ad49de89 4434static void load_consts(signed char pre[],signed char regmap[],int i)
57871462 4435{
8575a877 4436 int hr,hr2;
4437 // propagate loaded constant flags
cf95b4f0 4438 if(i==0||dops[i].bt)
8575a877 4439 regs[i].loadedconst=0;
4440 else {
4441 for(hr=0;hr<HOST_REGS;hr++) {
4442 if(hr!=EXCLUDE_REG&&regmap[hr]>=0&&((regs[i-1].isconst>>hr)&1)&&pre[hr]==regmap[hr]
4443 &&regmap[hr]==regs[i-1].regmap[hr]&&((regs[i-1].loadedconst>>hr)&1))
4444 {
4445 regs[i].loadedconst|=1<<hr;
4446 }
4447 }
4448 }
57871462 4449 // Load 32-bit regs
4450 for(hr=0;hr<HOST_REGS;hr++) {
4451 if(hr!=EXCLUDE_REG&&regmap[hr]>=0) {
4452 //if(entry[hr]!=regmap[hr]) {
8575a877 4453 if(!((regs[i].loadedconst>>hr)&1)) {
ad49de89 4454 assert(regmap[hr]<64);
4455 if(((regs[i].isconst>>hr)&1)&&regmap[hr]>0) {
8575a877 4456 int value,similar=0;
57871462 4457 if(get_final_value(hr,i,&value)) {
8575a877 4458 // see if some other register has similar value
4459 for(hr2=0;hr2<HOST_REGS;hr2++) {
4460 if(hr2!=EXCLUDE_REG&&((regs[i].loadedconst>>hr2)&1)) {
4461 if(is_similar_value(value,constmap[i][hr2])) {
4462 similar=1;
4463 break;
4464 }
4465 }
4466 }
4467 if(similar) {
4468 int value2;
4469 if(get_final_value(hr2,i,&value2)) // is this needed?
4470 emit_movimm_from(value2,hr2,value,hr);
4471 else
4472 emit_movimm(value,hr);
4473 }
4474 else if(value==0) {
57871462 4475 emit_zeroreg(hr);
4476 }
4477 else {
4478 emit_movimm(value,hr);
4479 }
4480 }
8575a877 4481 regs[i].loadedconst|=1<<hr;
57871462 4482 }
4483 }
4484 }
4485 }
57871462 4486}
ad49de89 4487
2330734f 4488static void load_all_consts(const signed char regmap[], u_int dirty, int i)
57871462 4489{
4490 int hr;
4491 // Load 32-bit regs
4492 for(hr=0;hr<HOST_REGS;hr++) {
4493 if(hr!=EXCLUDE_REG&&regmap[hr]>=0&&((dirty>>hr)&1)) {
ad49de89 4494 assert(regmap[hr] < 64);
4495 if(((regs[i].isconst>>hr)&1)&&regmap[hr]>0) {
57871462 4496 int value=constmap[i][hr];
4497 if(value==0) {
4498 emit_zeroreg(hr);
4499 }
4500 else {
4501 emit_movimm(value,hr);
4502 }
4503 }
4504 }
4505 }
57871462 4506}
4507
4508// Write out all dirty registers (except cycle count)
2330734f 4509static void wb_dirtys(const signed char i_regmap[], uint64_t i_dirty)
57871462 4510{
4511 int hr;
4512 for(hr=0;hr<HOST_REGS;hr++) {
4513 if(hr!=EXCLUDE_REG) {
4514 if(i_regmap[hr]>0) {
4515 if(i_regmap[hr]!=CCREG) {
4516 if((i_dirty>>hr)&1) {
00fa9369 4517 assert(i_regmap[hr]<64);
4518 emit_storereg(i_regmap[hr],hr);
57871462 4519 }
4520 }
4521 }
4522 }
4523 }
4524}
ad49de89 4525
57871462 4526// Write out dirty registers that we need to reload (pair with load_needed_regs)
4527// This writes the registers not written by store_regs_bt
2330734f 4528static void wb_needed_dirtys(const signed char i_regmap[], uint64_t i_dirty, int addr)
57871462 4529{
4530 int hr;
4531 int t=(addr-start)>>2;
4532 for(hr=0;hr<HOST_REGS;hr++) {
4533 if(hr!=EXCLUDE_REG) {
4534 if(i_regmap[hr]>0) {
4535 if(i_regmap[hr]!=CCREG) {
ad49de89 4536 if(i_regmap[hr]==regs[t].regmap_entry[hr] && ((regs[t].dirty>>hr)&1)) {
57871462 4537 if((i_dirty>>hr)&1) {
00fa9369 4538 assert(i_regmap[hr]<64);
4539 emit_storereg(i_regmap[hr],hr);
57871462 4540 }
4541 }
4542 }
4543 }
4544 }
4545 }
4546}
4547
4548// Load all registers (except cycle count)
2330734f 4549static void load_all_regs(const signed char i_regmap[])
57871462 4550{
4551 int hr;
4552 for(hr=0;hr<HOST_REGS;hr++) {
4553 if(hr!=EXCLUDE_REG) {
4554 if(i_regmap[hr]==0) {
4555 emit_zeroreg(hr);
4556 }
4557 else
ea3d2e6e 4558 if(i_regmap[hr]>0 && (i_regmap[hr]&63)<TEMPREG && i_regmap[hr]!=CCREG)
57871462 4559 {
4560 emit_loadreg(i_regmap[hr],hr);
4561 }
4562 }
4563 }
4564}
4565
4566// Load all current registers also needed by next instruction
2330734f 4567static void load_needed_regs(const signed char i_regmap[], const signed char next_regmap[])
57871462 4568{
4569 int hr;
4570 for(hr=0;hr<HOST_REGS;hr++) {
4571 if(hr!=EXCLUDE_REG) {
4572 if(get_reg(next_regmap,i_regmap[hr])>=0) {
4573 if(i_regmap[hr]==0) {
4574 emit_zeroreg(hr);
4575 }
4576 else
ea3d2e6e 4577 if(i_regmap[hr]>0 && (i_regmap[hr]&63)<TEMPREG && i_regmap[hr]!=CCREG)
57871462 4578 {
4579 emit_loadreg(i_regmap[hr],hr);
4580 }
4581 }
4582 }
4583 }
4584}
4585
4586// Load all regs, storing cycle count if necessary
2330734f 4587static void load_regs_entry(int t)
57871462 4588{
4589 int hr;
cf95b4f0 4590 if(dops[t].is_ds) emit_addimm(HOST_CCREG,CLOCK_ADJUST(1),HOST_CCREG);
2330734f 4591 else if(ccadj[t]) emit_addimm(HOST_CCREG,-ccadj[t],HOST_CCREG);
57871462 4592 if(regs[t].regmap_entry[HOST_CCREG]!=CCREG) {
4593 emit_storereg(CCREG,HOST_CCREG);
4594 }
4595 // Load 32-bit regs
4596 for(hr=0;hr<HOST_REGS;hr++) {
ea3d2e6e 4597 if(regs[t].regmap_entry[hr]>=0&&regs[t].regmap_entry[hr]<TEMPREG) {
57871462 4598 if(regs[t].regmap_entry[hr]==0) {
4599 emit_zeroreg(hr);
4600 }
4601 else if(regs[t].regmap_entry[hr]!=CCREG)
4602 {
4603 emit_loadreg(regs[t].regmap_entry[hr],hr);
4604 }
4605 }
4606 }
57871462 4607}
4608
4609// Store dirty registers prior to branch
ad49de89 4610void store_regs_bt(signed char i_regmap[],uint64_t i_dirty,int addr)
57871462 4611{
ad49de89 4612 if(internal_branch(addr))
57871462 4613 {
4614 int t=(addr-start)>>2;
4615 int hr;
4616 for(hr=0;hr<HOST_REGS;hr++) {
4617 if(hr!=EXCLUDE_REG) {
4618 if(i_regmap[hr]>0 && i_regmap[hr]!=CCREG) {
ad49de89 4619 if(i_regmap[hr]!=regs[t].regmap_entry[hr] || !((regs[t].dirty>>hr)&1)) {
57871462 4620 if((i_dirty>>hr)&1) {
00fa9369 4621 assert(i_regmap[hr]<64);
4622 if(!((unneeded_reg[t]>>i_regmap[hr])&1))
4623 emit_storereg(i_regmap[hr],hr);
57871462 4624 }
4625 }
4626 }
4627 }
4628 }
4629 }
4630 else
4631 {
4632 // Branch out of this block, write out all dirty regs
ad49de89 4633 wb_dirtys(i_regmap,i_dirty);
57871462 4634 }
4635}
4636
4637// Load all needed registers for branch target
ad49de89 4638static void load_regs_bt(signed char i_regmap[],uint64_t i_dirty,int addr)
57871462 4639{
4640 //if(addr>=start && addr<(start+slen*4))
ad49de89 4641 if(internal_branch(addr))
57871462 4642 {
4643 int t=(addr-start)>>2;
4644 int hr;
4645 // Store the cycle count before loading something else
4646 if(i_regmap[HOST_CCREG]!=CCREG) {
4647 assert(i_regmap[HOST_CCREG]==-1);
4648 }
4649 if(regs[t].regmap_entry[HOST_CCREG]!=CCREG) {
4650 emit_storereg(CCREG,HOST_CCREG);
4651 }
4652 // Load 32-bit regs
4653 for(hr=0;hr<HOST_REGS;hr++) {
ea3d2e6e 4654 if(hr!=EXCLUDE_REG&&regs[t].regmap_entry[hr]>=0&&regs[t].regmap_entry[hr]<TEMPREG) {
00fa9369 4655 if(i_regmap[hr]!=regs[t].regmap_entry[hr]) {
57871462 4656 if(regs[t].regmap_entry[hr]==0) {
4657 emit_zeroreg(hr);
4658 }
4659 else if(regs[t].regmap_entry[hr]!=CCREG)
4660 {
4661 emit_loadreg(regs[t].regmap_entry[hr],hr);
4662 }
4663 }
4664 }
4665 }
57871462 4666 }
4667}
4668
ad49de89 4669static int match_bt(signed char i_regmap[],uint64_t i_dirty,int addr)
57871462 4670{
4671 if(addr>=start && addr<start+slen*4-4)
4672 {
4673 int t=(addr-start)>>2;
4674 int hr;
4675 if(regs[t].regmap_entry[HOST_CCREG]!=CCREG) return 0;
4676 for(hr=0;hr<HOST_REGS;hr++)
4677 {
4678 if(hr!=EXCLUDE_REG)
4679 {
4680 if(i_regmap[hr]!=regs[t].regmap_entry[hr])
4681 {
ea3d2e6e 4682 if(regs[t].regmap_entry[hr]>=0&&(regs[t].regmap_entry[hr]|64)<TEMPREG+64)
57871462 4683 {
4684 return 0;
4685 }
9f51b4b9 4686 else
57871462 4687 if((i_dirty>>hr)&1)
4688 {
ea3d2e6e 4689 if(i_regmap[hr]<TEMPREG)
57871462 4690 {
4691 if(!((unneeded_reg[t]>>i_regmap[hr])&1))
4692 return 0;
4693 }
ea3d2e6e 4694 else if(i_regmap[hr]>=64&&i_regmap[hr]<TEMPREG+64)
57871462 4695 {
00fa9369 4696 assert(0);
57871462 4697 }
4698 }
4699 }
4700 else // Same register but is it 32-bit or dirty?
4701 if(i_regmap[hr]>=0)
4702 {
4703 if(!((regs[t].dirty>>hr)&1))
4704 {
4705 if((i_dirty>>hr)&1)
4706 {
4707 if(!((unneeded_reg[t]>>i_regmap[hr])&1))
4708 {
4709 //printf("%x: dirty no match\n",addr);
4710 return 0;
4711 }
4712 }
4713 }
57871462 4714 }
4715 }
4716 }
57871462 4717 // Delay slots are not valid branch targets
fe807a8a 4718 //if(t>0&&(dops[t-1].is_jump) return 0;
57871462 4719 // Delay slots require additional processing, so do not match
cf95b4f0 4720 if(dops[t].is_ds) return 0;
57871462 4721 }
4722 else
4723 {
4724 int hr;
4725 for(hr=0;hr<HOST_REGS;hr++)
4726 {
4727 if(hr!=EXCLUDE_REG)
4728 {
4729 if(i_regmap[hr]>=0)
4730 {
4731 if(hr!=HOST_CCREG||i_regmap[hr]!=CCREG)
4732 {
4733 if((i_dirty>>hr)&1)
4734 {
4735 return 0;
4736 }
4737 }
4738 }
4739 }
4740 }
4741 }
4742 return 1;
4743}
4744
dd114d7d 4745#ifdef DRC_DBG
2330734f 4746static void drc_dbg_emit_do_cmp(int i, int ccadj_)
dd114d7d 4747{
4748 extern void do_insn_cmp();
3968e69e 4749 //extern int cycle;
81dbbf4c 4750 u_int hr, reglist = get_host_reglist(regs[i].regmap);
dd114d7d 4751
40fca85b 4752 assem_debug("//do_insn_cmp %08x\n", start+i*4);
dd114d7d 4753 save_regs(reglist);
40fca85b 4754 // write out changed consts to match the interpreter
cf95b4f0 4755 if (i > 0 && !dops[i].bt) {
40fca85b 4756 for (hr = 0; hr < HOST_REGS; hr++) {
2330734f 4757 int reg = regs[i].regmap_entry[hr]; // regs[i-1].regmap[hr];
40fca85b 4758 if (hr == EXCLUDE_REG || reg < 0)
4759 continue;
4760 if (!((regs[i-1].isconst >> hr) & 1))
4761 continue;
4762 if (i > 1 && reg == regs[i-2].regmap[hr] && constmap[i-1][hr] == constmap[i-2][hr])
4763 continue;
4764 emit_movimm(constmap[i-1][hr],0);
4765 emit_storereg(reg, 0);
4766 }
4767 }
dd114d7d 4768 emit_movimm(start+i*4,0);
643aeae3 4769 emit_writeword(0,&pcaddr);
2330734f 4770 int cc = get_reg(regs[i].regmap_entry, CCREG);
4771 if (cc < 0)
4772 emit_loadreg(CCREG, cc = 0);
4773 emit_addimm(cc, ccadj_, 0);
4774 emit_writeword(0, &psxRegs.cycle);
2a014d73 4775 emit_far_call(do_insn_cmp);
643aeae3 4776 //emit_readword(&cycle,0);
dd114d7d 4777 //emit_addimm(0,2,0);
643aeae3 4778 //emit_writeword(0,&cycle);
3968e69e 4779 (void)get_reg2;
dd114d7d 4780 restore_regs(reglist);
40fca85b 4781 assem_debug("\\\\do_insn_cmp\n");
dd114d7d 4782}
4783#else
2330734f 4784#define drc_dbg_emit_do_cmp(x,y)
dd114d7d 4785#endif
4786
57871462 4787// Used when a branch jumps into the delay slot of another branch
7c3a5182 4788static void ds_assemble_entry(int i)
57871462 4789{
2330734f 4790 int t = (ba[i] - start) >> 2;
4791 int ccadj_ = -CLOCK_ADJUST(1);
df4dc2b1 4792 if (!instr_addr[t])
4793 instr_addr[t] = out;
57871462 4794 assem_debug("Assemble delay slot at %x\n",ba[i]);
4795 assem_debug("<->\n");
2330734f 4796 drc_dbg_emit_do_cmp(t, ccadj_);
57871462 4797 if(regs[t].regmap_entry[HOST_CCREG]==CCREG&&regs[t].regmap[HOST_CCREG]!=CCREG)
ad49de89 4798 wb_register(CCREG,regs[t].regmap_entry,regs[t].wasdirty);
cf95b4f0 4799 load_regs(regs[t].regmap_entry,regs[t].regmap,dops[t].rs1,dops[t].rs2);
57871462 4800 address_generation(t,&regs[t],regs[t].regmap_entry);
37387d8b 4801 if (ram_offset && (dops[t].is_load || dops[t].is_store))
4802 load_regs(regs[t].regmap_entry,regs[t].regmap,ROREG,ROREG);
4803 if (dops[t].is_store)
ad49de89 4804 load_regs(regs[t].regmap_entry,regs[t].regmap,INVCP,INVCP);
57871462 4805 is_delayslot=0;
2330734f 4806 switch (dops[t].itype) {
57871462 4807 case SYSCALL:
7139f3c8 4808 case HLECALL:
1e973cb0 4809 case INTCALL:
57871462 4810 case SPAN:
4811 case UJUMP:
4812 case RJUMP:
4813 case CJUMP:
4814 case SJUMP:
c43b5311 4815 SysPrintf("Jump in the delay slot. This is probably a bug.\n");
2330734f 4816 break;
4817 default:
4818 assemble(t, &regs[t], ccadj_);
57871462 4819 }
ad49de89 4820 store_regs_bt(regs[t].regmap,regs[t].dirty,ba[i]+4);
4821 load_regs_bt(regs[t].regmap,regs[t].dirty,ba[i]+4);
4822 if(internal_branch(ba[i]+4))
57871462 4823 assem_debug("branch: internal\n");
4824 else
4825 assem_debug("branch: external\n");
ad49de89 4826 assert(internal_branch(ba[i]+4));
4827 add_to_linker(out,ba[i]+4,internal_branch(ba[i]+4));
57871462 4828 emit_jmp(0);
4829}
4830
7c3a5182 4831static void emit_extjump(void *addr, u_int target)
4832{
4833 emit_extjump2(addr, target, dyna_linker);
4834}
4835
4836static void emit_extjump_ds(void *addr, u_int target)
4837{
4838 emit_extjump2(addr, target, dyna_linker_ds);
4839}
4840
d1e4ebd9 4841// Load 2 immediates optimizing for small code size
4842static void emit_mov2imm_compact(int imm1,u_int rt1,int imm2,u_int rt2)
4843{
4844 emit_movimm(imm1,rt1);
4845 emit_movimm_from(imm1,rt1,imm2,rt2);
4846}
4847
2330734f 4848static void do_cc(int i, const signed char i_regmap[], int *adj,
4849 int addr, int taken, int invert)
57871462 4850{
2330734f 4851 int count, count_plus2;
b14b6a8f 4852 void *jaddr;
4853 void *idle=NULL;
b6e87b2b 4854 int t=0;
cf95b4f0 4855 if(dops[i].itype==RJUMP)
57871462 4856 {
4857 *adj=0;
4858 }
4859 //if(ba[i]>=start && ba[i]<(start+slen*4))
ad49de89 4860 if(internal_branch(ba[i]))
57871462 4861 {
b6e87b2b 4862 t=(ba[i]-start)>>2;
2330734f 4863 if(dops[t].is_ds) *adj=-CLOCK_ADJUST(1); // Branch into delay slot adds an extra cycle
57871462 4864 else *adj=ccadj[t];
4865 }
4866 else
4867 {
4868 *adj=0;
4869 }
2330734f 4870 count = ccadj[i];
4871 count_plus2 = count + CLOCK_ADJUST(2);
57871462 4872 if(taken==TAKEN && i==(ba[i]-start)>>2 && source[i+1]==0) {
4873 // Idle loop
4874 if(count&1) emit_addimm_and_set_flags(2*(count+2),HOST_CCREG);
b14b6a8f 4875 idle=out;
57871462 4876 //emit_subfrommem(&idlecount,HOST_CCREG); // Count idle cycles
4877 emit_andimm(HOST_CCREG,3,HOST_CCREG);
b14b6a8f 4878 jaddr=out;
57871462 4879 emit_jmp(0);
4880 }
4881 else if(*adj==0||invert) {
2330734f 4882 int cycles = count_plus2;
b6e87b2b 4883 // faster loop HACK
bb4f300c 4884#if 0
b6e87b2b 4885 if (t&&*adj) {
4886 int rel=t-i;
4887 if(-NO_CYCLE_PENALTY_THR<rel&&rel<0)
2330734f 4888 cycles=*adj+count+2-*adj;
b6e87b2b 4889 }
bb4f300c 4890#endif
2330734f 4891 emit_addimm_and_set_flags(cycles, HOST_CCREG);
4892 jaddr = out;
57871462 4893 emit_jns(0);
4894 }
4895 else
4896 {
2330734f 4897 emit_cmpimm(HOST_CCREG, -count_plus2);
4898 jaddr = out;
57871462 4899 emit_jns(0);
4900 }
2330734f 4901 add_stub(CC_STUB,jaddr,idle?idle:out,(*adj==0||invert||idle)?0:count_plus2,i,addr,taken,0);
57871462 4902}
4903
b14b6a8f 4904static void do_ccstub(int n)
57871462 4905{
4906 literal_pool(256);
d1e4ebd9 4907 assem_debug("do_ccstub %x\n",start+(u_int)stubs[n].b*4);
b14b6a8f 4908 set_jump_target(stubs[n].addr, out);
4909 int i=stubs[n].b;
4910 if(stubs[n].d==NULLDS) {
57871462 4911 // Delay slot instruction is nullified ("likely" branch)
ad49de89 4912 wb_dirtys(regs[i].regmap,regs[i].dirty);
57871462 4913 }
b14b6a8f 4914 else if(stubs[n].d!=TAKEN) {
ad49de89 4915 wb_dirtys(branch_regs[i].regmap,branch_regs[i].dirty);
57871462 4916 }
4917 else {
ad49de89 4918 if(internal_branch(ba[i]))
4919 wb_needed_dirtys(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]);
57871462 4920 }
b14b6a8f 4921 if(stubs[n].c!=-1)
57871462 4922 {
4923 // Save PC as return address
b14b6a8f 4924 emit_movimm(stubs[n].c,EAX);
643aeae3 4925 emit_writeword(EAX,&pcaddr);
57871462 4926 }
4927 else
4928 {
4929 // Return address depends on which way the branch goes
cf95b4f0 4930 if(dops[i].itype==CJUMP||dops[i].itype==SJUMP)
57871462 4931 {
cf95b4f0 4932 int s1l=get_reg(branch_regs[i].regmap,dops[i].rs1);
4933 int s2l=get_reg(branch_regs[i].regmap,dops[i].rs2);
4934 if(dops[i].rs1==0)
57871462 4935 {
ad49de89 4936 s1l=s2l;
4937 s2l=-1;
57871462 4938 }
cf95b4f0 4939 else if(dops[i].rs2==0)
57871462 4940 {
ad49de89 4941 s2l=-1;
57871462 4942 }
4943 assert(s1l>=0);
4944 #ifdef DESTRUCTIVE_WRITEBACK
cf95b4f0 4945 if(dops[i].rs1) {
ad49de89 4946 if((branch_regs[i].dirty>>s1l)&&1)
cf95b4f0 4947 emit_loadreg(dops[i].rs1,s1l);
9f51b4b9 4948 }
57871462 4949 else {
ad49de89 4950 if((branch_regs[i].dirty>>s1l)&1)
cf95b4f0 4951 emit_loadreg(dops[i].rs2,s1l);
57871462 4952 }
4953 if(s2l>=0)
ad49de89 4954 if((branch_regs[i].dirty>>s2l)&1)
cf95b4f0 4955 emit_loadreg(dops[i].rs2,s2l);
57871462 4956 #endif
4957 int hr=0;
5194fb95 4958 int addr=-1,alt=-1,ntaddr=-1;
57871462 4959 while(hr<HOST_REGS)
4960 {
4961 if(hr!=EXCLUDE_REG && hr!=HOST_CCREG &&
cf95b4f0 4962 (branch_regs[i].regmap[hr]&63)!=dops[i].rs1 &&
4963 (branch_regs[i].regmap[hr]&63)!=dops[i].rs2 )
57871462 4964 {
4965 addr=hr++;break;
4966 }
4967 hr++;
4968 }
4969 while(hr<HOST_REGS)
4970 {
4971 if(hr!=EXCLUDE_REG && hr!=HOST_CCREG &&
cf95b4f0 4972 (branch_regs[i].regmap[hr]&63)!=dops[i].rs1 &&
4973 (branch_regs[i].regmap[hr]&63)!=dops[i].rs2 )
57871462 4974 {
4975 alt=hr++;break;
4976 }
4977 hr++;
4978 }
cf95b4f0 4979 if((dops[i].opcode&0x2E)==6) // BLEZ/BGTZ needs another register
57871462 4980 {
4981 while(hr<HOST_REGS)
4982 {
4983 if(hr!=EXCLUDE_REG && hr!=HOST_CCREG &&
cf95b4f0 4984 (branch_regs[i].regmap[hr]&63)!=dops[i].rs1 &&
4985 (branch_regs[i].regmap[hr]&63)!=dops[i].rs2 )
57871462 4986 {
4987 ntaddr=hr;break;
4988 }
4989 hr++;
4990 }
4991 assert(hr<HOST_REGS);
4992 }
cf95b4f0 4993 if((dops[i].opcode&0x2f)==4) // BEQ
57871462 4994 {
4995 #ifdef HAVE_CMOV_IMM
ad49de89 4996 if(s2l>=0) emit_cmp(s1l,s2l);
4997 else emit_test(s1l,s1l);
4998 emit_cmov2imm_e_ne_compact(ba[i],start+i*4+8,addr);
4999 #else
5000 emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
5001 if(s2l>=0) emit_cmp(s1l,s2l);
5002 else emit_test(s1l,s1l);
5003 emit_cmovne_reg(alt,addr);
57871462 5004 #endif
57871462 5005 }
cf95b4f0 5006 if((dops[i].opcode&0x2f)==5) // BNE
57871462 5007 {
5008 #ifdef HAVE_CMOV_IMM
ad49de89 5009 if(s2l>=0) emit_cmp(s1l,s2l);
5010 else emit_test(s1l,s1l);
5011 emit_cmov2imm_e_ne_compact(start+i*4+8,ba[i],addr);
5012 #else
5013 emit_mov2imm_compact(start+i*4+8,addr,ba[i],alt);
5014 if(s2l>=0) emit_cmp(s1l,s2l);
5015 else emit_test(s1l,s1l);
5016 emit_cmovne_reg(alt,addr);
57871462 5017 #endif
57871462 5018 }
cf95b4f0 5019 if((dops[i].opcode&0x2f)==6) // BLEZ
57871462 5020 {
5021 //emit_movimm(ba[i],alt);
5022 //emit_movimm(start+i*4+8,addr);
5023 emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
5024 emit_cmpimm(s1l,1);
57871462 5025 emit_cmovl_reg(alt,addr);
57871462 5026 }
cf95b4f0 5027 if((dops[i].opcode&0x2f)==7) // BGTZ
57871462 5028 {
5029 //emit_movimm(ba[i],addr);
5030 //emit_movimm(start+i*4+8,ntaddr);
5031 emit_mov2imm_compact(ba[i],addr,start+i*4+8,ntaddr);
5032 emit_cmpimm(s1l,1);
57871462 5033 emit_cmovl_reg(ntaddr,addr);
57871462 5034 }
cf95b4f0 5035 if((dops[i].opcode==1)&&(dops[i].opcode2&0x2D)==0) // BLTZ
57871462 5036 {
5037 //emit_movimm(ba[i],alt);
5038 //emit_movimm(start+i*4+8,addr);
5039 emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
ad49de89 5040 emit_test(s1l,s1l);
57871462 5041 emit_cmovs_reg(alt,addr);
5042 }
cf95b4f0 5043 if((dops[i].opcode==1)&&(dops[i].opcode2&0x2D)==1) // BGEZ
57871462 5044 {
5045 //emit_movimm(ba[i],addr);
5046 //emit_movimm(start+i*4+8,alt);
5047 emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
ad49de89 5048 emit_test(s1l,s1l);
57871462 5049 emit_cmovs_reg(alt,addr);
5050 }
cf95b4f0 5051 if(dops[i].opcode==0x11 && dops[i].opcode2==0x08 ) {
57871462 5052 if(source[i]&0x10000) // BC1T
5053 {
5054 //emit_movimm(ba[i],alt);
5055 //emit_movimm(start+i*4+8,addr);
5056 emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
5057 emit_testimm(s1l,0x800000);
5058 emit_cmovne_reg(alt,addr);
5059 }
5060 else // BC1F
5061 {
5062 //emit_movimm(ba[i],addr);
5063 //emit_movimm(start+i*4+8,alt);
5064 emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
5065 emit_testimm(s1l,0x800000);
5066 emit_cmovne_reg(alt,addr);
5067 }
5068 }
643aeae3 5069 emit_writeword(addr,&pcaddr);
57871462 5070 }
5071 else
cf95b4f0 5072 if(dops[i].itype==RJUMP)
57871462 5073 {
cf95b4f0 5074 int r=get_reg(branch_regs[i].regmap,dops[i].rs1);
4919de1e 5075 if (ds_writes_rjump_rs(i)) {
57871462 5076 r=get_reg(branch_regs[i].regmap,RTEMP);
5077 }
643aeae3 5078 emit_writeword(r,&pcaddr);
57871462 5079 }
7c3a5182 5080 else {SysPrintf("Unknown branch type in do_ccstub\n");abort();}
57871462 5081 }
5082 // Update cycle count
5083 assert(branch_regs[i].regmap[HOST_CCREG]==CCREG||branch_regs[i].regmap[HOST_CCREG]==-1);
2330734f 5084 if(stubs[n].a) emit_addimm(HOST_CCREG,(int)stubs[n].a,HOST_CCREG);
2a014d73 5085 emit_far_call(cc_interrupt);
2330734f 5086 if(stubs[n].a) emit_addimm(HOST_CCREG,-(int)stubs[n].a,HOST_CCREG);
b14b6a8f 5087 if(stubs[n].d==TAKEN) {
ad49de89 5088 if(internal_branch(ba[i]))
57871462 5089 load_needed_regs(branch_regs[i].regmap,regs[(ba[i]-start)>>2].regmap_entry);
cf95b4f0 5090 else if(dops[i].itype==RJUMP) {
57871462 5091 if(get_reg(branch_regs[i].regmap,RTEMP)>=0)
643aeae3 5092 emit_readword(&pcaddr,get_reg(branch_regs[i].regmap,RTEMP));
57871462 5093 else
cf95b4f0 5094 emit_loadreg(dops[i].rs1,get_reg(branch_regs[i].regmap,dops[i].rs1));
57871462 5095 }
b14b6a8f 5096 }else if(stubs[n].d==NOTTAKEN) {
57871462 5097 if(i<slen-2) load_needed_regs(branch_regs[i].regmap,regmap_pre[i+2]);
5098 else load_all_regs(branch_regs[i].regmap);
b14b6a8f 5099 }else if(stubs[n].d==NULLDS) {
57871462 5100 // Delay slot instruction is nullified ("likely" branch)
5101 if(i<slen-2) load_needed_regs(regs[i].regmap,regmap_pre[i+2]);
5102 else load_all_regs(regs[i].regmap);
5103 }else{
5104 load_all_regs(branch_regs[i].regmap);
5105 }
d1e4ebd9 5106 if (stubs[n].retaddr)
5107 emit_jmp(stubs[n].retaddr);
5108 else
5109 do_jump_vaddr(stubs[n].e);
57871462 5110}
5111
643aeae3 5112static void add_to_linker(void *addr, u_int target, int ext)
57871462 5113{
643aeae3 5114 assert(linkcount < ARRAY_SIZE(link_addr));
5115 link_addr[linkcount].addr = addr;
5116 link_addr[linkcount].target = target;
5117 link_addr[linkcount].ext = ext;
57871462 5118 linkcount++;
5119}
5120
eba830cd 5121static void ujump_assemble_write_ra(int i)
5122{
5123 int rt;
5124 unsigned int return_address;
5125 rt=get_reg(branch_regs[i].regmap,31);
5126 assem_debug("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5127 //assert(rt>=0);
5128 return_address=start+i*4+8;
5129 if(rt>=0) {
5130 #ifdef USE_MINI_HT
cf95b4f0 5131 if(internal_branch(return_address)&&dops[i+1].rt1!=31) {
eba830cd 5132 int temp=-1; // note: must be ds-safe
5133 #ifdef HOST_TEMPREG
5134 temp=HOST_TEMPREG;
5135 #endif
5136 if(temp>=0) do_miniht_insert(return_address,rt,temp);
5137 else emit_movimm(return_address,rt);
5138 }
5139 else
5140 #endif
5141 {
5142 #ifdef REG_PREFETCH
9f51b4b9 5143 if(temp>=0)
eba830cd 5144 {
643aeae3 5145 if(i_regmap[temp]!=PTEMP) emit_movimm((uintptr_t)hash_table_get(return_address),temp);
eba830cd 5146 }
5147 #endif
5148 emit_movimm(return_address,rt); // PC into link register
5149 #ifdef IMM_PREFETCH
df4dc2b1 5150 emit_prefetch(hash_table_get(return_address));
eba830cd 5151 #endif
5152 }
5153 }
5154}
5155
2330734f 5156static void ujump_assemble(int i, const struct regstat *i_regs)
57871462 5157{
eba830cd 5158 int ra_done=0;
57871462 5159 if(i==(ba[i]-start)>>2) assem_debug("idle loop\n");
5160 address_generation(i+1,i_regs,regs[i].regmap_entry);
5161 #ifdef REG_PREFETCH
5162 int temp=get_reg(branch_regs[i].regmap,PTEMP);
cf95b4f0 5163 if(dops[i].rt1==31&&temp>=0)
57871462 5164 {
581335b0 5165 signed char *i_regmap=i_regs->regmap;
57871462 5166 int return_address=start+i*4+8;
9f51b4b9 5167 if(get_reg(branch_regs[i].regmap,31)>0)
643aeae3 5168 if(i_regmap[temp]==PTEMP) emit_movimm((uintptr_t)hash_table_get(return_address),temp);
57871462 5169 }
5170 #endif
cf95b4f0 5171 if(dops[i].rt1==31&&(dops[i].rt1==dops[i+1].rs1||dops[i].rt1==dops[i+1].rs2)) {
eba830cd 5172 ujump_assemble_write_ra(i); // writeback ra for DS
5173 ra_done=1;
57871462 5174 }
4ef8f67d 5175 ds_assemble(i+1,i_regs);
5176 uint64_t bc_unneeded=branch_regs[i].u;
cf95b4f0 5177 bc_unneeded|=1|(1LL<<dops[i].rt1);
ad49de89 5178 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,bc_unneeded);
5179 load_regs(regs[i].regmap,branch_regs[i].regmap,CCREG,CCREG);
cf95b4f0 5180 if(!ra_done&&dops[i].rt1==31)
eba830cd 5181 ujump_assemble_write_ra(i);
57871462 5182 int cc,adj;
5183 cc=get_reg(branch_regs[i].regmap,CCREG);
5184 assert(cc==HOST_CCREG);
ad49de89 5185 store_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]);
57871462 5186 #ifdef REG_PREFETCH
cf95b4f0 5187 if(dops[i].rt1==31&&temp>=0) emit_prefetchreg(temp);
57871462 5188 #endif
5189 do_cc(i,branch_regs[i].regmap,&adj,ba[i],TAKEN,0);
2330734f 5190 if(adj) emit_addimm(cc, ccadj[i] + CLOCK_ADJUST(2) - adj, cc);
ad49de89 5191 load_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]);
5192 if(internal_branch(ba[i]))
57871462 5193 assem_debug("branch: internal\n");
5194 else
5195 assem_debug("branch: external\n");
cf95b4f0 5196 if (internal_branch(ba[i]) && dops[(ba[i]-start)>>2].is_ds) {
57871462 5197 ds_assemble_entry(i);
5198 }
5199 else {
ad49de89 5200 add_to_linker(out,ba[i],internal_branch(ba[i]));
57871462 5201 emit_jmp(0);
5202 }
5203}
5204
eba830cd 5205static void rjump_assemble_write_ra(int i)
5206{
5207 int rt,return_address;
cf95b4f0 5208 assert(dops[i+1].rt1!=dops[i].rt1);
5209 assert(dops[i+1].rt2!=dops[i].rt1);
5210 rt=get_reg(branch_regs[i].regmap,dops[i].rt1);
eba830cd 5211 assem_debug("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5212 assert(rt>=0);
5213 return_address=start+i*4+8;
5214 #ifdef REG_PREFETCH
9f51b4b9 5215 if(temp>=0)
eba830cd 5216 {
643aeae3 5217 if(i_regmap[temp]!=PTEMP) emit_movimm((uintptr_t)hash_table_get(return_address),temp);
eba830cd 5218 }
5219 #endif
5220 emit_movimm(return_address,rt); // PC into link register
5221 #ifdef IMM_PREFETCH
df4dc2b1 5222 emit_prefetch(hash_table_get(return_address));
eba830cd 5223 #endif
5224}
5225
2330734f 5226static void rjump_assemble(int i, const struct regstat *i_regs)
57871462 5227{
57871462 5228 int temp;
581335b0 5229 int rs,cc;
eba830cd 5230 int ra_done=0;
cf95b4f0 5231 rs=get_reg(branch_regs[i].regmap,dops[i].rs1);
57871462 5232 assert(rs>=0);
4919de1e 5233 if (ds_writes_rjump_rs(i)) {
57871462 5234 // Delay slot abuse, make a copy of the branch address register
5235 temp=get_reg(branch_regs[i].regmap,RTEMP);
5236 assert(temp>=0);
5237 assert(regs[i].regmap[temp]==RTEMP);
5238 emit_mov(rs,temp);
5239 rs=temp;
5240 }
5241 address_generation(i+1,i_regs,regs[i].regmap_entry);
5242 #ifdef REG_PREFETCH
cf95b4f0 5243 if(dops[i].rt1==31)
57871462 5244 {
5245 if((temp=get_reg(branch_regs[i].regmap,PTEMP))>=0) {
581335b0 5246 signed char *i_regmap=i_regs->regmap;
57871462 5247 int return_address=start+i*4+8;
643aeae3 5248 if(i_regmap[temp]==PTEMP) emit_movimm((uintptr_t)hash_table_get(return_address),temp);
57871462 5249 }
5250 }
5251 #endif
5252 #ifdef USE_MINI_HT
cf95b4f0 5253 if(dops[i].rs1==31) {
57871462 5254 int rh=get_reg(regs[i].regmap,RHASH);
5255 if(rh>=0) do_preload_rhash(rh);
5256 }
5257 #endif
cf95b4f0 5258 if(dops[i].rt1!=0&&(dops[i].rt1==dops[i+1].rs1||dops[i].rt1==dops[i+1].rs2)) {
eba830cd 5259 rjump_assemble_write_ra(i);
5260 ra_done=1;
57871462 5261 }
d5910d5d 5262 ds_assemble(i+1,i_regs);
5263 uint64_t bc_unneeded=branch_regs[i].u;
cf95b4f0 5264 bc_unneeded|=1|(1LL<<dops[i].rt1);
5265 bc_unneeded&=~(1LL<<dops[i].rs1);
ad49de89 5266 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,bc_unneeded);
cf95b4f0 5267 load_regs(regs[i].regmap,branch_regs[i].regmap,dops[i].rs1,CCREG);
5268 if(!ra_done&&dops[i].rt1!=0)
eba830cd 5269 rjump_assemble_write_ra(i);
57871462 5270 cc=get_reg(branch_regs[i].regmap,CCREG);
5271 assert(cc==HOST_CCREG);
581335b0 5272 (void)cc;
57871462 5273 #ifdef USE_MINI_HT
5274 int rh=get_reg(branch_regs[i].regmap,RHASH);
5275 int ht=get_reg(branch_regs[i].regmap,RHTBL);
cf95b4f0 5276 if(dops[i].rs1==31) {
57871462 5277 if(regs[i].regmap[rh]!=RHASH) do_preload_rhash(rh);
5278 do_preload_rhtbl(ht);
5279 do_rhash(rs,rh);
5280 }
5281 #endif
ad49de89 5282 store_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,-1);
57871462 5283 #ifdef DESTRUCTIVE_WRITEBACK
ad49de89 5284 if((branch_regs[i].dirty>>rs)&1) {
cf95b4f0 5285 if(dops[i].rs1!=dops[i+1].rt1&&dops[i].rs1!=dops[i+1].rt2) {
5286 emit_loadreg(dops[i].rs1,rs);
57871462 5287 }
5288 }
5289 #endif
5290 #ifdef REG_PREFETCH
cf95b4f0 5291 if(dops[i].rt1==31&&temp>=0) emit_prefetchreg(temp);
57871462 5292 #endif
5293 #ifdef USE_MINI_HT
cf95b4f0 5294 if(dops[i].rs1==31) {
57871462 5295 do_miniht_load(ht,rh);
5296 }
5297 #endif
5298 //do_cc(i,branch_regs[i].regmap,&adj,-1,TAKEN);
5299 //if(adj) emit_addimm(cc,2*(ccadj[i]+2-adj),cc); // ??? - Shouldn't happen
5300 //assert(adj==0);
2330734f 5301 emit_addimm_and_set_flags(ccadj[i] + CLOCK_ADJUST(2), HOST_CCREG);
d1e4ebd9 5302 add_stub(CC_STUB,out,NULL,0,i,-1,TAKEN,rs);
cf95b4f0 5303 if(dops[i+1].itype==COP0&&(source[i+1]&0x3f)==0x10)
911f2d55 5304 // special case for RFE
5305 emit_jmp(0);
5306 else
71e490c5 5307 emit_jns(0);
ad49de89 5308 //load_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,-1);
57871462 5309 #ifdef USE_MINI_HT
cf95b4f0 5310 if(dops[i].rs1==31) {
57871462 5311 do_miniht_jump(rs,rh,ht);
5312 }
5313 else
5314 #endif
5315 {
d1e4ebd9 5316 do_jump_vaddr(rs);
57871462 5317 }
57871462 5318 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
cf95b4f0 5319 if(dops[i].rt1!=31&&i<slen-2&&(((u_int)out)&7)) emit_mov(13,13);
57871462 5320 #endif
5321}
5322
2330734f 5323static void cjump_assemble(int i, const struct regstat *i_regs)
57871462 5324{
2330734f 5325 const signed char *i_regmap = i_regs->regmap;
57871462 5326 int cc;
5327 int match;
ad49de89 5328 match=match_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]);
57871462 5329 assem_debug("match=%d\n",match);
ad49de89 5330 int s1l,s2l;
57871462 5331 int unconditional=0,nop=0;
57871462 5332 int invert=0;
ad49de89 5333 int internal=internal_branch(ba[i]);
57871462 5334 if(i==(ba[i]-start)>>2) assem_debug("idle loop\n");
57871462 5335 if(!match) invert=1;
5336 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5337 if(i>(ba[i]-start)>>2) invert=1;
5338 #endif
3968e69e 5339 #ifdef __aarch64__
5340 invert=1; // because of near cond. branches
5341 #endif
9f51b4b9 5342
cf95b4f0 5343 if(dops[i].ooo) {
5344 s1l=get_reg(branch_regs[i].regmap,dops[i].rs1);
5345 s2l=get_reg(branch_regs[i].regmap,dops[i].rs2);
57871462 5346 }
5347 else {
cf95b4f0 5348 s1l=get_reg(i_regmap,dops[i].rs1);
5349 s2l=get_reg(i_regmap,dops[i].rs2);
57871462 5350 }
cf95b4f0 5351 if(dops[i].rs1==0&&dops[i].rs2==0)
57871462 5352 {
cf95b4f0 5353 if(dops[i].opcode&1) nop=1;
57871462 5354 else unconditional=1;
cf95b4f0 5355 //assert(dops[i].opcode!=5);
5356 //assert(dops[i].opcode!=7);
5357 //assert(dops[i].opcode!=0x15);
5358 //assert(dops[i].opcode!=0x17);
57871462 5359 }
cf95b4f0 5360 else if(dops[i].rs1==0)
57871462 5361 {
ad49de89 5362 s1l=s2l;
5363 s2l=-1;
57871462 5364 }
cf95b4f0 5365 else if(dops[i].rs2==0)
57871462 5366 {
ad49de89 5367 s2l=-1;
57871462 5368 }
5369
cf95b4f0 5370 if(dops[i].ooo) {
57871462 5371 // Out of order execution (delay slot first)
5372 //printf("OOOE\n");
5373 address_generation(i+1,i_regs,regs[i].regmap_entry);
5374 ds_assemble(i+1,i_regs);
5375 int adj;
5376 uint64_t bc_unneeded=branch_regs[i].u;
cf95b4f0 5377 bc_unneeded&=~((1LL<<dops[i].rs1)|(1LL<<dops[i].rs2));
57871462 5378 bc_unneeded|=1;
ad49de89 5379 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,bc_unneeded);
cf95b4f0 5380 load_regs(regs[i].regmap,branch_regs[i].regmap,dops[i].rs1,dops[i].rs2);
ad49de89 5381 load_regs(regs[i].regmap,branch_regs[i].regmap,CCREG,CCREG);
57871462 5382 cc=get_reg(branch_regs[i].regmap,CCREG);
5383 assert(cc==HOST_CCREG);
9f51b4b9 5384 if(unconditional)
ad49de89 5385 store_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]);
57871462 5386 //do_cc(i,branch_regs[i].regmap,&adj,unconditional?ba[i]:-1,unconditional);
5387 //assem_debug("cycle count (adj)\n");
5388 if(unconditional) {
5389 do_cc(i,branch_regs[i].regmap,&adj,ba[i],TAKEN,0);
5390 if(i!=(ba[i]-start)>>2 || source[i+1]!=0) {
2330734f 5391 if(adj) emit_addimm(cc, ccadj[i] + CLOCK_ADJUST(2) - adj, cc);
ad49de89 5392 load_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]);
57871462 5393 if(internal)
5394 assem_debug("branch: internal\n");
5395 else
5396 assem_debug("branch: external\n");
cf95b4f0 5397 if (internal && dops[(ba[i]-start)>>2].is_ds) {
57871462 5398 ds_assemble_entry(i);
5399 }
5400 else {
643aeae3 5401 add_to_linker(out,ba[i],internal);
57871462 5402 emit_jmp(0);
5403 }
5404 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5405 if(((u_int)out)&7) emit_addnop(0);
5406 #endif
5407 }
5408 }
5409 else if(nop) {
2330734f 5410 emit_addimm_and_set_flags(ccadj[i] + CLOCK_ADJUST(2), cc);
b14b6a8f 5411 void *jaddr=out;
57871462 5412 emit_jns(0);
b14b6a8f 5413 add_stub(CC_STUB,jaddr,out,0,i,start+i*4+8,NOTTAKEN,0);
57871462 5414 }
5415 else {
df4dc2b1 5416 void *taken = NULL, *nottaken = NULL, *nottaken1 = NULL;
57871462 5417 do_cc(i,branch_regs[i].regmap,&adj,-1,0,invert);
2330734f 5418 if(adj&&!invert) emit_addimm(cc, ccadj[i] + CLOCK_ADJUST(2) - adj, cc);
9f51b4b9 5419
57871462 5420 //printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5421 assert(s1l>=0);
cf95b4f0 5422 if(dops[i].opcode==4) // BEQ
57871462 5423 {
5424 if(s2l>=0) emit_cmp(s1l,s2l);
5425 else emit_test(s1l,s1l);
5426 if(invert){
df4dc2b1 5427 nottaken=out;
7c3a5182 5428 emit_jne(DJT_1);
57871462 5429 }else{
643aeae3 5430 add_to_linker(out,ba[i],internal);
57871462 5431 emit_jeq(0);
5432 }
5433 }
cf95b4f0 5434 if(dops[i].opcode==5) // BNE
57871462 5435 {
5436 if(s2l>=0) emit_cmp(s1l,s2l);
5437 else emit_test(s1l,s1l);
5438 if(invert){
df4dc2b1 5439 nottaken=out;
7c3a5182 5440 emit_jeq(DJT_1);
57871462 5441 }else{
643aeae3 5442 add_to_linker(out,ba[i],internal);
57871462 5443 emit_jne(0);
5444 }
5445 }
cf95b4f0 5446 if(dops[i].opcode==6) // BLEZ
57871462 5447 {
5448 emit_cmpimm(s1l,1);
5449 if(invert){
df4dc2b1 5450 nottaken=out;
7c3a5182 5451 emit_jge(DJT_1);
57871462 5452 }else{
643aeae3 5453 add_to_linker(out,ba[i],internal);
57871462 5454 emit_jl(0);
5455 }
5456 }
cf95b4f0 5457 if(dops[i].opcode==7) // BGTZ
57871462 5458 {
5459 emit_cmpimm(s1l,1);
5460 if(invert){
df4dc2b1 5461 nottaken=out;
7c3a5182 5462 emit_jl(DJT_1);
57871462 5463 }else{
643aeae3 5464 add_to_linker(out,ba[i],internal);
57871462 5465 emit_jge(0);
5466 }
5467 }
5468 if(invert) {
df4dc2b1 5469 if(taken) set_jump_target(taken, out);
57871462 5470 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
cf95b4f0 5471 if (match && (!internal || !dops[(ba[i]-start)>>2].is_ds)) {
57871462 5472 if(adj) {
2330734f 5473 emit_addimm(cc,-adj,cc);
643aeae3 5474 add_to_linker(out,ba[i],internal);
57871462 5475 }else{
5476 emit_addnop(13);
643aeae3 5477 add_to_linker(out,ba[i],internal*2);
57871462 5478 }
5479 emit_jmp(0);
5480 }else
5481 #endif
5482 {
2330734f 5483 if(adj) emit_addimm(cc,-adj,cc);
ad49de89 5484 store_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]);
5485 load_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]);
57871462 5486 if(internal)
5487 assem_debug("branch: internal\n");
5488 else
5489 assem_debug("branch: external\n");
cf95b4f0 5490 if (internal && dops[(ba[i] - start) >> 2].is_ds) {
57871462 5491 ds_assemble_entry(i);
5492 }
5493 else {
643aeae3 5494 add_to_linker(out,ba[i],internal);
57871462 5495 emit_jmp(0);
5496 }
5497 }
df4dc2b1 5498 set_jump_target(nottaken, out);
57871462 5499 }
5500
df4dc2b1 5501 if(nottaken1) set_jump_target(nottaken1, out);
57871462 5502 if(adj) {
2330734f 5503 if(!invert) emit_addimm(cc,adj,cc);
57871462 5504 }
5505 } // (!unconditional)
5506 } // if(ooo)
5507 else
5508 {
5509 // In-order execution (branch first)
df4dc2b1 5510 void *taken = NULL, *nottaken = NULL, *nottaken1 = NULL;
57871462 5511 if(!unconditional&&!nop) {
57871462 5512 //printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5513 assert(s1l>=0);
cf95b4f0 5514 if((dops[i].opcode&0x2f)==4) // BEQ
57871462 5515 {
5516 if(s2l>=0) emit_cmp(s1l,s2l);
5517 else emit_test(s1l,s1l);
df4dc2b1 5518 nottaken=out;
7c3a5182 5519 emit_jne(DJT_2);
57871462 5520 }
cf95b4f0 5521 if((dops[i].opcode&0x2f)==5) // BNE
57871462 5522 {
5523 if(s2l>=0) emit_cmp(s1l,s2l);
5524 else emit_test(s1l,s1l);
df4dc2b1 5525 nottaken=out;
7c3a5182 5526 emit_jeq(DJT_2);
57871462 5527 }
cf95b4f0 5528 if((dops[i].opcode&0x2f)==6) // BLEZ
57871462 5529 {
5530 emit_cmpimm(s1l,1);
df4dc2b1 5531 nottaken=out;
7c3a5182 5532 emit_jge(DJT_2);
57871462 5533 }
cf95b4f0 5534 if((dops[i].opcode&0x2f)==7) // BGTZ
57871462 5535 {
5536 emit_cmpimm(s1l,1);
df4dc2b1 5537 nottaken=out;
7c3a5182 5538 emit_jl(DJT_2);
57871462 5539 }
5540 } // if(!unconditional)
5541 int adj;
5542 uint64_t ds_unneeded=branch_regs[i].u;
cf95b4f0 5543 ds_unneeded&=~((1LL<<dops[i+1].rs1)|(1LL<<dops[i+1].rs2));
57871462 5544 ds_unneeded|=1;
57871462 5545 // branch taken
5546 if(!nop) {
df4dc2b1 5547 if(taken) set_jump_target(taken, out);
57871462 5548 assem_debug("1:\n");
ad49de89 5549 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,ds_unneeded);
57871462 5550 // load regs
cf95b4f0 5551 load_regs(regs[i].regmap,branch_regs[i].regmap,dops[i+1].rs1,dops[i+1].rs2);
57871462 5552 address_generation(i+1,&branch_regs[i],0);
37387d8b 5553 if (ram_offset)
5554 load_regs(regs[i].regmap,branch_regs[i].regmap,ROREG,ROREG);
ad49de89 5555 load_regs(regs[i].regmap,branch_regs[i].regmap,CCREG,INVCP);
57871462 5556 ds_assemble(i+1,&branch_regs[i]);
5557 cc=get_reg(branch_regs[i].regmap,CCREG);
5558 if(cc==-1) {
5559 emit_loadreg(CCREG,cc=HOST_CCREG);
5560 // CHECK: Is the following instruction (fall thru) allocated ok?
5561 }
5562 assert(cc==HOST_CCREG);
ad49de89 5563 store_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]);
57871462 5564 do_cc(i,i_regmap,&adj,ba[i],TAKEN,0);
5565 assem_debug("cycle count (adj)\n");
2330734f 5566 if(adj) emit_addimm(cc, ccadj[i] + CLOCK_ADJUST(2) - adj, cc);
ad49de89 5567 load_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]);
57871462 5568 if(internal)
5569 assem_debug("branch: internal\n");
5570 else
5571 assem_debug("branch: external\n");
cf95b4f0 5572 if (internal && dops[(ba[i] - start) >> 2].is_ds) {
57871462 5573 ds_assemble_entry(i);
5574 }
5575 else {
643aeae3 5576 add_to_linker(out,ba[i],internal);
57871462 5577 emit_jmp(0);
5578 }
5579 }
5580 // branch not taken
57871462 5581 if(!unconditional) {
df4dc2b1 5582 if(nottaken1) set_jump_target(nottaken1, out);
5583 set_jump_target(nottaken, out);
57871462 5584 assem_debug("2:\n");
fe807a8a 5585 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,ds_unneeded);
37387d8b 5586 // load regs
fe807a8a 5587 load_regs(regs[i].regmap,branch_regs[i].regmap,dops[i+1].rs1,dops[i+1].rs2);
5588 address_generation(i+1,&branch_regs[i],0);
37387d8b 5589 if (ram_offset)
5590 load_regs(regs[i].regmap,branch_regs[i].regmap,ROREG,ROREG);
5591 load_regs(regs[i].regmap,branch_regs[i].regmap,CCREG,INVCP);
fe807a8a 5592 ds_assemble(i+1,&branch_regs[i]);
57871462 5593 cc=get_reg(branch_regs[i].regmap,CCREG);
fe807a8a 5594 if (cc == -1) {
57871462 5595 // Cycle count isn't in a register, temporarily load it then write it out
5596 emit_loadreg(CCREG,HOST_CCREG);
2330734f 5597 emit_addimm_and_set_flags(ccadj[i] + CLOCK_ADJUST(2), HOST_CCREG);
b14b6a8f 5598 void *jaddr=out;
57871462 5599 emit_jns(0);
b14b6a8f 5600 add_stub(CC_STUB,jaddr,out,0,i,start+i*4+8,NOTTAKEN,0);
57871462 5601 emit_storereg(CCREG,HOST_CCREG);
5602 }
5603 else{
5604 cc=get_reg(i_regmap,CCREG);
5605 assert(cc==HOST_CCREG);
2330734f 5606 emit_addimm_and_set_flags(ccadj[i] + CLOCK_ADJUST(2), cc);
b14b6a8f 5607 void *jaddr=out;
57871462 5608 emit_jns(0);
fe807a8a 5609 add_stub(CC_STUB,jaddr,out,0,i,start+i*4+8,NOTTAKEN,0);
57871462 5610 }
5611 }
5612 }
5613}
5614
2330734f 5615static void sjump_assemble(int i, const struct regstat *i_regs)
57871462 5616{
2330734f 5617 const signed char *i_regmap = i_regs->regmap;
57871462 5618 int cc;
5619 int match;
ad49de89 5620 match=match_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]);
2acc46cd 5621 assem_debug("smatch=%d ooo=%d\n", match, dops[i].ooo);
ad49de89 5622 int s1l;
57871462 5623 int unconditional=0,nevertaken=0;
57871462 5624 int invert=0;
ad49de89 5625 int internal=internal_branch(ba[i]);
57871462 5626 if(i==(ba[i]-start)>>2) assem_debug("idle loop\n");
57871462 5627 if(!match) invert=1;
5628 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5629 if(i>(ba[i]-start)>>2) invert=1;
5630 #endif
3968e69e 5631 #ifdef __aarch64__
5632 invert=1; // because of near cond. branches
5633 #endif
57871462 5634
cf95b4f0 5635 //if(dops[i].opcode2>=0x10) return; // FIXME (BxxZAL)
5636 //assert(dops[i].opcode2<0x10||dops[i].rs1==0); // FIXME (BxxZAL)
57871462 5637
cf95b4f0 5638 if(dops[i].ooo) {
5639 s1l=get_reg(branch_regs[i].regmap,dops[i].rs1);
57871462 5640 }
5641 else {
cf95b4f0 5642 s1l=get_reg(i_regmap,dops[i].rs1);
57871462 5643 }
cf95b4f0 5644 if(dops[i].rs1==0)
57871462 5645 {
cf95b4f0 5646 if(dops[i].opcode2&1) unconditional=1;
57871462 5647 else nevertaken=1;
5648 // These are never taken (r0 is never less than zero)
cf95b4f0 5649 //assert(dops[i].opcode2!=0);
5650 //assert(dops[i].opcode2!=2);
5651 //assert(dops[i].opcode2!=0x10);
5652 //assert(dops[i].opcode2!=0x12);
57871462 5653 }
57871462 5654
cf95b4f0 5655 if(dops[i].ooo) {
57871462 5656 // Out of order execution (delay slot first)
5657 //printf("OOOE\n");
5658 address_generation(i+1,i_regs,regs[i].regmap_entry);
5659 ds_assemble(i+1,i_regs);
5660 int adj;
5661 uint64_t bc_unneeded=branch_regs[i].u;
cf95b4f0 5662 bc_unneeded&=~((1LL<<dops[i].rs1)|(1LL<<dops[i].rs2));
57871462 5663 bc_unneeded|=1;
ad49de89 5664 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,bc_unneeded);
cf95b4f0 5665 load_regs(regs[i].regmap,branch_regs[i].regmap,dops[i].rs1,dops[i].rs1);
ad49de89 5666 load_regs(regs[i].regmap,branch_regs[i].regmap,CCREG,CCREG);
cf95b4f0 5667 if(dops[i].rt1==31) {
57871462 5668 int rt,return_address;
57871462 5669 rt=get_reg(branch_regs[i].regmap,31);
5670 assem_debug("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5671 if(rt>=0) {
5672 // Save the PC even if the branch is not taken
5673 return_address=start+i*4+8;
5674 emit_movimm(return_address,rt); // PC into link register
5675 #ifdef IMM_PREFETCH
df4dc2b1 5676 if(!nevertaken) emit_prefetch(hash_table_get(return_address));
57871462 5677 #endif
5678 }
5679 }
5680 cc=get_reg(branch_regs[i].regmap,CCREG);
5681 assert(cc==HOST_CCREG);
9f51b4b9 5682 if(unconditional)
ad49de89 5683 store_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]);
57871462 5684 //do_cc(i,branch_regs[i].regmap,&adj,unconditional?ba[i]:-1,unconditional);
5685 assem_debug("cycle count (adj)\n");
5686 if(unconditional) {
5687 do_cc(i,branch_regs[i].regmap,&adj,ba[i],TAKEN,0);
5688 if(i!=(ba[i]-start)>>2 || source[i+1]!=0) {
2330734f 5689 if(adj) emit_addimm(cc, ccadj[i] + CLOCK_ADJUST(2) - adj, cc);
ad49de89 5690 load_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]);
57871462 5691 if(internal)
5692 assem_debug("branch: internal\n");
5693 else
5694 assem_debug("branch: external\n");
cf95b4f0 5695 if (internal && dops[(ba[i] - start) >> 2].is_ds) {
57871462 5696 ds_assemble_entry(i);
5697 }
5698 else {
643aeae3 5699 add_to_linker(out,ba[i],internal);
57871462 5700 emit_jmp(0);
5701 }
5702 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5703 if(((u_int)out)&7) emit_addnop(0);
5704 #endif
5705 }
5706 }
5707 else if(nevertaken) {
2330734f 5708 emit_addimm_and_set_flags(ccadj[i] + CLOCK_ADJUST(2), cc);
b14b6a8f 5709 void *jaddr=out;
57871462 5710 emit_jns(0);
b14b6a8f 5711 add_stub(CC_STUB,jaddr,out,0,i,start+i*4+8,NOTTAKEN,0);
57871462 5712 }
5713 else {
df4dc2b1 5714 void *nottaken = NULL;
57871462 5715 do_cc(i,branch_regs[i].regmap,&adj,-1,0,invert);
2330734f 5716 if(adj&&!invert) emit_addimm(cc, ccadj[i] + CLOCK_ADJUST(2) - adj, cc);
57871462 5717 {
5718 assert(s1l>=0);
cf95b4f0 5719 if((dops[i].opcode2&0xf)==0) // BLTZ/BLTZAL
57871462 5720 {
5721 emit_test(s1l,s1l);
5722 if(invert){
df4dc2b1 5723 nottaken=out;
7c3a5182 5724 emit_jns(DJT_1);
57871462 5725 }else{
643aeae3 5726 add_to_linker(out,ba[i],internal);
57871462 5727 emit_js(0);
5728 }
5729 }
cf95b4f0 5730 if((dops[i].opcode2&0xf)==1) // BGEZ/BLTZAL
57871462 5731 {
5732 emit_test(s1l,s1l);
5733 if(invert){
df4dc2b1 5734 nottaken=out;
7c3a5182 5735 emit_js(DJT_1);
57871462 5736 }else{
643aeae3 5737 add_to_linker(out,ba[i],internal);
57871462 5738 emit_jns(0);
5739 }
5740 }
ad49de89 5741 }
9f51b4b9 5742
57871462 5743 if(invert) {
5744 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
cf95b4f0 5745 if (match && (!internal || !dops[(ba[i] - start) >> 2].is_ds)) {
57871462 5746 if(adj) {
2330734f 5747 emit_addimm(cc,-adj,cc);
643aeae3 5748 add_to_linker(out,ba[i],internal);
57871462 5749 }else{
5750 emit_addnop(13);
643aeae3 5751 add_to_linker(out,ba[i],internal*2);
57871462 5752 }
5753 emit_jmp(0);
5754 }else
5755 #endif
5756 {
2330734f 5757 if(adj) emit_addimm(cc,-adj,cc);
ad49de89 5758 store_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]);
5759 load_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]);
57871462 5760 if(internal)
5761 assem_debug("branch: internal\n");
5762 else
5763 assem_debug("branch: external\n");
cf95b4f0 5764 if (internal && dops[(ba[i] - start) >> 2].is_ds) {
57871462 5765 ds_assemble_entry(i);
5766 }
5767 else {
643aeae3 5768 add_to_linker(out,ba[i],internal);
57871462 5769 emit_jmp(0);
5770 }
5771 }
df4dc2b1 5772 set_jump_target(nottaken, out);
57871462 5773 }
5774
5775 if(adj) {
2330734f 5776 if(!invert) emit_addimm(cc,adj,cc);
57871462 5777 }
5778 } // (!unconditional)
5779 } // if(ooo)
5780 else
5781 {
5782 // In-order execution (branch first)
5783 //printf("IOE\n");
df4dc2b1 5784 void *nottaken = NULL;
cf95b4f0 5785 if(dops[i].rt1==31) {
a6491170 5786 int rt,return_address;
a6491170 5787 rt=get_reg(branch_regs[i].regmap,31);
5788 if(rt>=0) {
5789 // Save the PC even if the branch is not taken
5790 return_address=start+i*4+8;
5791 emit_movimm(return_address,rt); // PC into link register
5792 #ifdef IMM_PREFETCH
df4dc2b1 5793 emit_prefetch(hash_table_get(return_address));
a6491170 5794 #endif
5795 }
5796 }
57871462 5797 if(!unconditional) {
5798 //printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
57871462 5799 assert(s1l>=0);
cf95b4f0 5800 if((dops[i].opcode2&0x0d)==0) // BLTZ/BLTZL/BLTZAL/BLTZALL
57871462 5801 {
5802 emit_test(s1l,s1l);
df4dc2b1 5803 nottaken=out;
7c3a5182 5804 emit_jns(DJT_1);
57871462 5805 }
cf95b4f0 5806 if((dops[i].opcode2&0x0d)==1) // BGEZ/BGEZL/BGEZAL/BGEZALL
57871462 5807 {
5808 emit_test(s1l,s1l);
df4dc2b1 5809 nottaken=out;
7c3a5182 5810 emit_js(DJT_1);
57871462 5811 }
57871462 5812 } // if(!unconditional)
5813 int adj;
5814 uint64_t ds_unneeded=branch_regs[i].u;
cf95b4f0 5815 ds_unneeded&=~((1LL<<dops[i+1].rs1)|(1LL<<dops[i+1].rs2));
57871462 5816 ds_unneeded|=1;
57871462 5817 // branch taken
5818 if(!nevertaken) {
5819 //assem_debug("1:\n");
ad49de89 5820 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,ds_unneeded);
57871462 5821 // load regs
cf95b4f0 5822 load_regs(regs[i].regmap,branch_regs[i].regmap,dops[i+1].rs1,dops[i+1].rs2);
57871462 5823 address_generation(i+1,&branch_regs[i],0);
37387d8b 5824 if (ram_offset)
5825 load_regs(regs[i].regmap,branch_regs[i].regmap,ROREG,ROREG);
ad49de89 5826 load_regs(regs[i].regmap,branch_regs[i].regmap,CCREG,INVCP);
57871462 5827 ds_assemble(i+1,&branch_regs[i]);
5828 cc=get_reg(branch_regs[i].regmap,CCREG);
5829 if(cc==-1) {
5830 emit_loadreg(CCREG,cc=HOST_CCREG);
5831 // CHECK: Is the following instruction (fall thru) allocated ok?
5832 }
5833 assert(cc==HOST_CCREG);
ad49de89 5834 store_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]);
57871462 5835 do_cc(i,i_regmap,&adj,ba[i],TAKEN,0);
5836 assem_debug("cycle count (adj)\n");
2330734f 5837 if(adj) emit_addimm(cc, ccadj[i] + CLOCK_ADJUST(2) - adj, cc);
ad49de89 5838 load_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]);
57871462 5839 if(internal)
5840 assem_debug("branch: internal\n");
5841 else
5842 assem_debug("branch: external\n");
cf95b4f0 5843 if (internal && dops[(ba[i] - start) >> 2].is_ds) {
57871462 5844 ds_assemble_entry(i);
5845 }
5846 else {
643aeae3 5847 add_to_linker(out,ba[i],internal);
57871462 5848 emit_jmp(0);
5849 }
5850 }
5851 // branch not taken
57871462 5852 if(!unconditional) {
df4dc2b1 5853 set_jump_target(nottaken, out);
57871462 5854 assem_debug("1:\n");
fe807a8a 5855 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,ds_unneeded);
5856 load_regs(regs[i].regmap,branch_regs[i].regmap,dops[i+1].rs1,dops[i+1].rs2);
5857 address_generation(i+1,&branch_regs[i],0);
5a18ce2e 5858 if (ram_offset)
5859 load_regs(regs[i].regmap,branch_regs[i].regmap,ROREG,ROREG);
5860 load_regs(regs[i].regmap,branch_regs[i].regmap,CCREG,INVCP);
fe807a8a 5861 ds_assemble(i+1,&branch_regs[i]);
57871462 5862 cc=get_reg(branch_regs[i].regmap,CCREG);
fe807a8a 5863 if (cc == -1) {
57871462 5864 // Cycle count isn't in a register, temporarily load it then write it out
5865 emit_loadreg(CCREG,HOST_CCREG);
2330734f 5866 emit_addimm_and_set_flags(ccadj[i] + CLOCK_ADJUST(2), HOST_CCREG);
b14b6a8f 5867 void *jaddr=out;
57871462 5868 emit_jns(0);
b14b6a8f 5869 add_stub(CC_STUB,jaddr,out,0,i,start+i*4+8,NOTTAKEN,0);
57871462 5870 emit_storereg(CCREG,HOST_CCREG);
5871 }
5872 else{
5873 cc=get_reg(i_regmap,CCREG);
5874 assert(cc==HOST_CCREG);
2330734f 5875 emit_addimm_and_set_flags(ccadj[i] + CLOCK_ADJUST(2), cc);
b14b6a8f 5876 void *jaddr=out;
57871462 5877 emit_jns(0);
fe807a8a 5878 add_stub(CC_STUB,jaddr,out,0,i,start+i*4+8,NOTTAKEN,0);
57871462 5879 }
5880 }
5881 }
5882}
5883
2330734f 5884static void pagespan_assemble(int i, const struct regstat *i_regs)
57871462 5885{
cf95b4f0 5886 int s1l=get_reg(i_regs->regmap,dops[i].rs1);
5887 int s2l=get_reg(i_regs->regmap,dops[i].rs2);
df4dc2b1 5888 void *taken = NULL;
5889 void *nottaken = NULL;
57871462 5890 int unconditional=0;
cf95b4f0 5891 if(dops[i].rs1==0)
57871462 5892 {
ad49de89 5893 s1l=s2l;
5894 s2l=-1;
57871462 5895 }
cf95b4f0 5896 else if(dops[i].rs2==0)
57871462 5897 {
ad49de89 5898 s2l=-1;
57871462 5899 }
5900 int hr=0;
581335b0 5901 int addr=-1,alt=-1,ntaddr=-1;
57871462 5902 if(i_regs->regmap[HOST_BTREG]<0) {addr=HOST_BTREG;}
5903 else {
5904 while(hr<HOST_REGS)
5905 {
5906 if(hr!=EXCLUDE_REG && hr!=HOST_CCREG &&
cf95b4f0 5907 (i_regs->regmap[hr]&63)!=dops[i].rs1 &&
5908 (i_regs->regmap[hr]&63)!=dops[i].rs2 )
57871462 5909 {
5910 addr=hr++;break;
5911 }
5912 hr++;
5913 }
5914 }
5915 while(hr<HOST_REGS)
5916 {
5917 if(hr!=EXCLUDE_REG && hr!=HOST_CCREG && hr!=HOST_BTREG &&
cf95b4f0 5918 (i_regs->regmap[hr]&63)!=dops[i].rs1 &&
5919 (i_regs->regmap[hr]&63)!=dops[i].rs2 )
57871462 5920 {
5921 alt=hr++;break;
5922 }
5923 hr++;
5924 }
cf95b4f0 5925 if((dops[i].opcode&0x2E)==6) // BLEZ/BGTZ needs another register
57871462 5926 {
5927 while(hr<HOST_REGS)
5928 {
5929 if(hr!=EXCLUDE_REG && hr!=HOST_CCREG && hr!=HOST_BTREG &&
cf95b4f0 5930 (i_regs->regmap[hr]&63)!=dops[i].rs1 &&
5931 (i_regs->regmap[hr]&63)!=dops[i].rs2 )
57871462 5932 {
5933 ntaddr=hr;break;
5934 }
5935 hr++;
5936 }
5937 }
5938 assert(hr<HOST_REGS);
cf95b4f0 5939 if((dops[i].opcode&0x2e)==4||dops[i].opcode==0x11) { // BEQ/BNE/BEQL/BNEL/BC1
ad49de89 5940 load_regs(regs[i].regmap_entry,regs[i].regmap,CCREG,CCREG);
57871462 5941 }
2330734f 5942 emit_addimm(HOST_CCREG, ccadj[i] + CLOCK_ADJUST(2), HOST_CCREG);
cf95b4f0 5943 if(dops[i].opcode==2) // J
57871462 5944 {
5945 unconditional=1;
5946 }
cf95b4f0 5947 if(dops[i].opcode==3) // JAL
57871462 5948 {
5949 // TODO: mini_ht
5950 int rt=get_reg(i_regs->regmap,31);
5951 emit_movimm(start+i*4+8,rt);
5952 unconditional=1;
5953 }
cf95b4f0 5954 if(dops[i].opcode==0&&(dops[i].opcode2&0x3E)==8) // JR/JALR
57871462 5955 {
5956 emit_mov(s1l,addr);
cf95b4f0 5957 if(dops[i].opcode2==9) // JALR
57871462 5958 {
cf95b4f0 5959 int rt=get_reg(i_regs->regmap,dops[i].rt1);
57871462 5960 emit_movimm(start+i*4+8,rt);
5961 }
5962 }
cf95b4f0 5963 if((dops[i].opcode&0x3f)==4) // BEQ
57871462 5964 {
cf95b4f0 5965 if(dops[i].rs1==dops[i].rs2)
57871462 5966 {
5967 unconditional=1;
5968 }
5969 else
5970 #ifdef HAVE_CMOV_IMM
ad49de89 5971 if(1) {
57871462 5972 if(s2l>=0) emit_cmp(s1l,s2l);
5973 else emit_test(s1l,s1l);
5974 emit_cmov2imm_e_ne_compact(ba[i],start+i*4+8,addr);
5975 }
5976 else
5977 #endif
5978 {
5979 assert(s1l>=0);
5980 emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
57871462 5981 if(s2l>=0) emit_cmp(s1l,s2l);
5982 else emit_test(s1l,s1l);
5983 emit_cmovne_reg(alt,addr);
5984 }
5985 }
cf95b4f0 5986 if((dops[i].opcode&0x3f)==5) // BNE
57871462 5987 {
5988 #ifdef HAVE_CMOV_IMM
ad49de89 5989 if(s2l>=0) emit_cmp(s1l,s2l);
5990 else emit_test(s1l,s1l);
5991 emit_cmov2imm_e_ne_compact(start+i*4+8,ba[i],addr);
5992 #else
5993 assert(s1l>=0);
5994 emit_mov2imm_compact(start+i*4+8,addr,ba[i],alt);
5995 if(s2l>=0) emit_cmp(s1l,s2l);
5996 else emit_test(s1l,s1l);
5997 emit_cmovne_reg(alt,addr);
57871462 5998 #endif
57871462 5999 }
cf95b4f0 6000 if((dops[i].opcode&0x3f)==0x14) // BEQL
57871462 6001 {
57871462 6002 if(s2l>=0) emit_cmp(s1l,s2l);
6003 else emit_test(s1l,s1l);
df4dc2b1 6004 if(nottaken) set_jump_target(nottaken, out);
6005 nottaken=out;
57871462 6006 emit_jne(0);
6007 }
cf95b4f0 6008 if((dops[i].opcode&0x3f)==0x15) // BNEL
57871462 6009 {
57871462 6010 if(s2l>=0) emit_cmp(s1l,s2l);
6011 else emit_test(s1l,s1l);
df4dc2b1 6012 nottaken=out;
57871462 6013 emit_jeq(0);
df4dc2b1 6014 if(taken) set_jump_target(taken, out);
57871462 6015 }
cf95b4f0 6016 if((dops[i].opcode&0x3f)==6) // BLEZ
57871462 6017 {
6018 emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
6019 emit_cmpimm(s1l,1);
57871462 6020 emit_cmovl_reg(alt,addr);
57871462 6021 }
cf95b4f0 6022 if((dops[i].opcode&0x3f)==7) // BGTZ
57871462 6023 {
6024 emit_mov2imm_compact(ba[i],addr,start+i*4+8,ntaddr);
6025 emit_cmpimm(s1l,1);
57871462 6026 emit_cmovl_reg(ntaddr,addr);
57871462 6027 }
cf95b4f0 6028 if((dops[i].opcode&0x3f)==0x16) // BLEZL
57871462 6029 {
cf95b4f0 6030 assert((dops[i].opcode&0x3f)!=0x16);
57871462 6031 }
cf95b4f0 6032 if((dops[i].opcode&0x3f)==0x17) // BGTZL
57871462 6033 {
cf95b4f0 6034 assert((dops[i].opcode&0x3f)!=0x17);
57871462 6035 }
cf95b4f0 6036 assert(dops[i].opcode!=1); // BLTZ/BGEZ
57871462 6037
6038 //FIXME: Check CSREG
cf95b4f0 6039 if(dops[i].opcode==0x11 && dops[i].opcode2==0x08 ) {
57871462 6040 if((source[i]&0x30000)==0) // BC1F
6041 {
6042 emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
6043 emit_testimm(s1l,0x800000);
6044 emit_cmovne_reg(alt,addr);
6045 }
6046 if((source[i]&0x30000)==0x10000) // BC1T
6047 {
6048 emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
6049 emit_testimm(s1l,0x800000);
6050 emit_cmovne_reg(alt,addr);
6051 }
6052 if((source[i]&0x30000)==0x20000) // BC1FL
6053 {
6054 emit_testimm(s1l,0x800000);
df4dc2b1 6055 nottaken=out;
57871462 6056 emit_jne(0);
6057 }
6058 if((source[i]&0x30000)==0x30000) // BC1TL
6059 {
6060 emit_testimm(s1l,0x800000);
df4dc2b1 6061 nottaken=out;
57871462 6062 emit_jeq(0);
6063 }
6064 }
6065
6066 assert(i_regs->regmap[HOST_CCREG]==CCREG);
ad49de89 6067 wb_dirtys(regs[i].regmap,regs[i].dirty);
fe807a8a 6068 if(unconditional)
57871462 6069 {
6070 emit_movimm(ba[i],HOST_BTREG);
6071 }
6072 else if(addr!=HOST_BTREG)
6073 {
6074 emit_mov(addr,HOST_BTREG);
6075 }
6076 void *branch_addr=out;
6077 emit_jmp(0);
6078 int target_addr=start+i*4+5;
6079 void *stub=out;
6080 void *compiled_target_addr=check_addr(target_addr);
643aeae3 6081 emit_extjump_ds(branch_addr, target_addr);
57871462 6082 if(compiled_target_addr) {
df4dc2b1 6083 set_jump_target(branch_addr, compiled_target_addr);
3d680478 6084 add_jump_out(target_addr,stub);
57871462 6085 }
df4dc2b1 6086 else set_jump_target(branch_addr, stub);
57871462 6087}
6088
6089// Assemble the delay slot for the above
6090static void pagespan_ds()
6091{
6092 assem_debug("initial delay slot:\n");
6093 u_int vaddr=start+1;
94d23bb9 6094 u_int page=get_page(vaddr);
6095 u_int vpage=get_vpage(vaddr);
57871462 6096 ll_add(jump_dirty+vpage,vaddr,(void *)out);
3d680478 6097 do_dirty_stub_ds(slen*4);
57871462 6098 ll_add(jump_in+page,vaddr,(void *)out);
6099 assert(regs[0].regmap_entry[HOST_CCREG]==CCREG);
6100 if(regs[0].regmap[HOST_CCREG]!=CCREG)
ad49de89 6101 wb_register(CCREG,regs[0].regmap_entry,regs[0].wasdirty);
57871462 6102 if(regs[0].regmap[HOST_BTREG]!=BTREG)
643aeae3 6103 emit_writeword(HOST_BTREG,&branch_target);
cf95b4f0 6104 load_regs(regs[0].regmap_entry,regs[0].regmap,dops[0].rs1,dops[0].rs2);
57871462 6105 address_generation(0,&regs[0],regs[0].regmap_entry);
37387d8b 6106 if (ram_offset && (dops[0].is_load || dops[0].is_store))
6107 load_regs(regs[0].regmap_entry,regs[0].regmap,ROREG,ROREG);
6108 if (dops[0].is_store)
ad49de89 6109 load_regs(regs[0].regmap_entry,regs[0].regmap,INVCP,INVCP);
57871462 6110 is_delayslot=0;
2330734f 6111 switch (dops[0].itype) {
57871462 6112 case SYSCALL:
7139f3c8 6113 case HLECALL:
1e973cb0 6114 case INTCALL:
57871462 6115 case SPAN:
6116 case UJUMP:
6117 case RJUMP:
6118 case CJUMP:
6119 case SJUMP:
c43b5311 6120 SysPrintf("Jump in the delay slot. This is probably a bug.\n");
2330734f 6121 break;
6122 default:
6123 assemble(0, &regs[0], 0);
57871462 6124 }
6125 int btaddr=get_reg(regs[0].regmap,BTREG);
6126 if(btaddr<0) {
6127 btaddr=get_reg(regs[0].regmap,-1);
643aeae3 6128 emit_readword(&branch_target,btaddr);
57871462 6129 }
6130 assert(btaddr!=HOST_CCREG);
6131 if(regs[0].regmap[HOST_CCREG]!=CCREG) emit_loadreg(CCREG,HOST_CCREG);
6132#ifdef HOST_IMM8
d1e4ebd9 6133 host_tempreg_acquire();
57871462 6134 emit_movimm(start+4,HOST_TEMPREG);
6135 emit_cmp(btaddr,HOST_TEMPREG);
d1e4ebd9 6136 host_tempreg_release();
57871462 6137#else
6138 emit_cmpimm(btaddr,start+4);
6139#endif
df4dc2b1 6140 void *branch = out;
57871462 6141 emit_jeq(0);
ad49de89 6142 store_regs_bt(regs[0].regmap,regs[0].dirty,-1);
d1e4ebd9 6143 do_jump_vaddr(btaddr);
df4dc2b1 6144 set_jump_target(branch, out);
ad49de89 6145 store_regs_bt(regs[0].regmap,regs[0].dirty,start+4);
6146 load_regs_bt(regs[0].regmap,regs[0].dirty,start+4);
57871462 6147}
6148
670c0f22 6149static void check_regmap(signed char *regmap)
6150{
6151#ifndef NDEBUG
6152 int i,j;
6153 for (i = 0; i < HOST_REGS; i++) {
6154 if (regmap[i] < 0)
6155 continue;
6156 for (j = i + 1; j < HOST_REGS; j++)
6157 assert(regmap[i] != regmap[j]);
6158 }
6159#endif
6160}
6161
57871462 6162// Basic liveness analysis for MIPS registers
670c0f22 6163static void unneeded_registers(int istart,int iend,int r)
57871462 6164{
6165 int i;
00fa9369 6166 uint64_t u,gte_u,b,gte_b;
6167 uint64_t temp_u,temp_gte_u=0;
0ff8c62c 6168 uint64_t gte_u_unknown=0;
d62c125a 6169 if (HACK_ENABLED(NDHACK_GTE_UNNEEDED))
0ff8c62c 6170 gte_u_unknown=~0ll;
57871462 6171 if(iend==slen-1) {
00fa9369 6172 u=1;
0ff8c62c 6173 gte_u=gte_u_unknown;
57871462 6174 }else{
00fa9369 6175 //u=unneeded_reg[iend+1];
6176 u=1;
0ff8c62c 6177 gte_u=gte_unneeded[iend+1];
57871462 6178 }
bedfea38 6179
57871462 6180 for (i=iend;i>=istart;i--)
6181 {
6182 //printf("unneeded registers i=%d (%d,%d) r=%d\n",i,istart,iend,r);
fe807a8a 6183 if(dops[i].is_jump)
57871462 6184 {
6185 // If subroutine call, flag return address as a possible branch target
cf95b4f0 6186 if(dops[i].rt1==31 && i<slen-2) dops[i+2].bt=1;
9f51b4b9 6187
57871462 6188 if(ba[i]<start || ba[i]>=(start+slen*4))
6189 {
6190 // Branch out of this block, flush all regs
6191 u=1;
0ff8c62c 6192 gte_u=gte_u_unknown;
57871462 6193 branch_unneeded_reg[i]=u;
57871462 6194 // Merge in delay slot
cf95b4f0 6195 u|=(1LL<<dops[i+1].rt1)|(1LL<<dops[i+1].rt2);
6196 u&=~((1LL<<dops[i+1].rs1)|(1LL<<dops[i+1].rs2));
00fa9369 6197 u|=1;
bedfea38 6198 gte_u|=gte_rt[i+1];
6199 gte_u&=~gte_rs[i+1];
57871462 6200 }
6201 else
6202 {
6203 // Internal branch, flag target
cf95b4f0 6204 dops[(ba[i]-start)>>2].bt=1;
57871462 6205 if(ba[i]<=start+i*4) {
6206 // Backward branch
fe807a8a 6207 if(dops[i].is_ujump)
57871462 6208 {
6209 // Unconditional branch
00fa9369 6210 temp_u=1;
bedfea38 6211 temp_gte_u=0;
57871462 6212 } else {
6213 // Conditional branch (not taken case)
6214 temp_u=unneeded_reg[i+2];
bedfea38 6215 temp_gte_u&=gte_unneeded[i+2];
57871462 6216 }
6217 // Merge in delay slot
cf95b4f0 6218 temp_u|=(1LL<<dops[i+1].rt1)|(1LL<<dops[i+1].rt2);
6219 temp_u&=~((1LL<<dops[i+1].rs1)|(1LL<<dops[i+1].rs2));
00fa9369 6220 temp_u|=1;
bedfea38 6221 temp_gte_u|=gte_rt[i+1];
6222 temp_gte_u&=~gte_rs[i+1];
cf95b4f0 6223 temp_u|=(1LL<<dops[i].rt1)|(1LL<<dops[i].rt2);
6224 temp_u&=~((1LL<<dops[i].rs1)|(1LL<<dops[i].rs2));
00fa9369 6225 temp_u|=1;
bedfea38 6226 temp_gte_u|=gte_rt[i];
6227 temp_gte_u&=~gte_rs[i];
57871462 6228 unneeded_reg[i]=temp_u;
bedfea38 6229 gte_unneeded[i]=temp_gte_u;
57871462 6230 // Only go three levels deep. This recursion can take an
6231 // excessive amount of time if there are a lot of nested loops.
6232 if(r<2) {
6233 unneeded_registers((ba[i]-start)>>2,i-1,r+1);
6234 }else{
6235 unneeded_reg[(ba[i]-start)>>2]=1;
0ff8c62c 6236 gte_unneeded[(ba[i]-start)>>2]=gte_u_unknown;
57871462 6237 }
6238 } /*else*/ if(1) {
fe807a8a 6239 if (dops[i].is_ujump)
57871462 6240 {
6241 // Unconditional branch
6242 u=unneeded_reg[(ba[i]-start)>>2];
bedfea38 6243 gte_u=gte_unneeded[(ba[i]-start)>>2];
57871462 6244 branch_unneeded_reg[i]=u;
57871462 6245 // Merge in delay slot
cf95b4f0 6246 u|=(1LL<<dops[i+1].rt1)|(1LL<<dops[i+1].rt2);
6247 u&=~((1LL<<dops[i+1].rs1)|(1LL<<dops[i+1].rs2));
00fa9369 6248 u|=1;
bedfea38 6249 gte_u|=gte_rt[i+1];
6250 gte_u&=~gte_rs[i+1];
57871462 6251 } else {
6252 // Conditional branch
6253 b=unneeded_reg[(ba[i]-start)>>2];
00fa9369 6254 gte_b=gte_unneeded[(ba[i]-start)>>2];
57871462 6255 branch_unneeded_reg[i]=b;
57871462 6256 // Branch delay slot
cf95b4f0 6257 b|=(1LL<<dops[i+1].rt1)|(1LL<<dops[i+1].rt2);
6258 b&=~((1LL<<dops[i+1].rs1)|(1LL<<dops[i+1].rs2));
00fa9369 6259 b|=1;
6260 gte_b|=gte_rt[i+1];
6261 gte_b&=~gte_rs[i+1];
fe807a8a 6262 u&=b;
6263 gte_u&=gte_b;
57871462 6264 if(i<slen-1) {
6265 branch_unneeded_reg[i]&=unneeded_reg[i+2];
57871462 6266 } else {
6267 branch_unneeded_reg[i]=1;
57871462 6268 }
6269 }
6270 }
6271 }
6272 }
cf95b4f0 6273 else if(dops[i].itype==SYSCALL||dops[i].itype==HLECALL||dops[i].itype==INTCALL)
57871462 6274 {
6275 // SYSCALL instruction (software interrupt)
6276 u=1;
57871462 6277 }
cf95b4f0 6278 else if(dops[i].itype==COP0 && (source[i]&0x3f)==0x18)
57871462 6279 {
6280 // ERET instruction (return from interrupt)
6281 u=1;
57871462 6282 }
00fa9369 6283 //u=1; // DEBUG
57871462 6284 // Written registers are unneeded
cf95b4f0 6285 u|=1LL<<dops[i].rt1;
6286 u|=1LL<<dops[i].rt2;
bedfea38 6287 gte_u|=gte_rt[i];
57871462 6288 // Accessed registers are needed
cf95b4f0 6289 u&=~(1LL<<dops[i].rs1);
6290 u&=~(1LL<<dops[i].rs2);
bedfea38 6291 gte_u&=~gte_rs[i];
cf95b4f0 6292 if(gte_rs[i]&&dops[i].rt1&&(unneeded_reg[i+1]&(1ll<<dops[i].rt1)))
cbbd8dd7 6293 gte_u|=gte_rs[i]&gte_unneeded[i+1]; // MFC2/CFC2 to dead register, unneeded
57871462 6294 // Source-target dependencies
57871462 6295 // R0 is always unneeded
00fa9369 6296 u|=1;
57871462 6297 // Save it
6298 unneeded_reg[i]=u;
bedfea38 6299 gte_unneeded[i]=gte_u;
57871462 6300 /*
6301 printf("ur (%d,%d) %x: ",istart,iend,start+i*4);
6302 printf("U:");
6303 int r;
6304 for(r=1;r<=CCREG;r++) {
6305 if((unneeded_reg[i]>>r)&1) {
6306 if(r==HIREG) printf(" HI");
6307 else if(r==LOREG) printf(" LO");
6308 else printf(" r%d",r);
6309 }
6310 }
00fa9369 6311 printf("\n");
6312 */
252c20fc 6313 }
57871462 6314}
6315
71e490c5 6316// Write back dirty registers as soon as we will no longer modify them,
6317// so that we don't end up with lots of writes at the branches.
6318void clean_registers(int istart,int iend,int wr)
57871462 6319{
71e490c5 6320 int i;
6321 int r;
6322 u_int will_dirty_i,will_dirty_next,temp_will_dirty;
6323 u_int wont_dirty_i,wont_dirty_next,temp_wont_dirty;
6324 if(iend==slen-1) {
6325 will_dirty_i=will_dirty_next=0;
6326 wont_dirty_i=wont_dirty_next=0;
6327 }else{
6328 will_dirty_i=will_dirty_next=will_dirty[iend+1];
6329 wont_dirty_i=wont_dirty_next=wont_dirty[iend+1];
6330 }
6331 for (i=iend;i>=istart;i--)
57871462 6332 {
fe807a8a 6333 if(dops[i].is_jump)
57871462 6334 {
71e490c5 6335 if(ba[i]<start || ba[i]>=(start+slen*4))
57871462 6336 {
71e490c5 6337 // Branch out of this block, flush all regs
fe807a8a 6338 if (dops[i].is_ujump)
57871462 6339 {
6340 // Unconditional branch
6341 will_dirty_i=0;
6342 wont_dirty_i=0;
6343 // Merge in delay slot (will dirty)
6344 for(r=0;r<HOST_REGS;r++) {
6345 if(r!=EXCLUDE_REG) {
cf95b4f0 6346 if((branch_regs[i].regmap[r]&63)==dops[i].rt1) will_dirty_i|=1<<r;
6347 if((branch_regs[i].regmap[r]&63)==dops[i].rt2) will_dirty_i|=1<<r;
6348 if((branch_regs[i].regmap[r]&63)==dops[i+1].rt1) will_dirty_i|=1<<r;
6349 if((branch_regs[i].regmap[r]&63)==dops[i+1].rt2) will_dirty_i|=1<<r;
57871462 6350 if((branch_regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
6351 if(branch_regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
6352 if(branch_regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
cf95b4f0 6353 if((regs[i].regmap[r]&63)==dops[i].rt1) will_dirty_i|=1<<r;
6354 if((regs[i].regmap[r]&63)==dops[i].rt2) will_dirty_i|=1<<r;
6355 if((regs[i].regmap[r]&63)==dops[i+1].rt1) will_dirty_i|=1<<r;
6356 if((regs[i].regmap[r]&63)==dops[i+1].rt2) will_dirty_i|=1<<r;
57871462 6357 if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
6358 if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
6359 if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
6360 }
6361 }
6362 }
6363 else
6364 {
6365 // Conditional branch
6366 will_dirty_i=0;
6367 wont_dirty_i=wont_dirty_next;
6368 // Merge in delay slot (will dirty)
6369 for(r=0;r<HOST_REGS;r++) {
6370 if(r!=EXCLUDE_REG) {
fe807a8a 6371 if (1) { // !dops[i].likely) {
57871462 6372 // Might not dirty if likely branch is not taken
cf95b4f0 6373 if((branch_regs[i].regmap[r]&63)==dops[i].rt1) will_dirty_i|=1<<r;
6374 if((branch_regs[i].regmap[r]&63)==dops[i].rt2) will_dirty_i|=1<<r;
6375 if((branch_regs[i].regmap[r]&63)==dops[i+1].rt1) will_dirty_i|=1<<r;
6376 if((branch_regs[i].regmap[r]&63)==dops[i+1].rt2) will_dirty_i|=1<<r;
57871462 6377 if((branch_regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
6378 if(branch_regs[i].regmap[r]==0) will_dirty_i&=~(1<<r);
6379 if(branch_regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
cf95b4f0 6380 //if((regs[i].regmap[r]&63)==dops[i].rt1) will_dirty_i|=1<<r;
6381 //if((regs[i].regmap[r]&63)==dops[i].rt2) will_dirty_i|=1<<r;
6382 if((regs[i].regmap[r]&63)==dops[i+1].rt1) will_dirty_i|=1<<r;
6383 if((regs[i].regmap[r]&63)==dops[i+1].rt2) will_dirty_i|=1<<r;
57871462 6384 if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
6385 if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
6386 if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
6387 }
6388 }
6389 }
6390 }
6391 // Merge in delay slot (wont dirty)
6392 for(r=0;r<HOST_REGS;r++) {
6393 if(r!=EXCLUDE_REG) {
cf95b4f0 6394 if((regs[i].regmap[r]&63)==dops[i].rt1) wont_dirty_i|=1<<r;
6395 if((regs[i].regmap[r]&63)==dops[i].rt2) wont_dirty_i|=1<<r;
6396 if((regs[i].regmap[r]&63)==dops[i+1].rt1) wont_dirty_i|=1<<r;
6397 if((regs[i].regmap[r]&63)==dops[i+1].rt2) wont_dirty_i|=1<<r;
57871462 6398 if(regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
cf95b4f0 6399 if((branch_regs[i].regmap[r]&63)==dops[i].rt1) wont_dirty_i|=1<<r;
6400 if((branch_regs[i].regmap[r]&63)==dops[i].rt2) wont_dirty_i|=1<<r;
6401 if((branch_regs[i].regmap[r]&63)==dops[i+1].rt1) wont_dirty_i|=1<<r;
6402 if((branch_regs[i].regmap[r]&63)==dops[i+1].rt2) wont_dirty_i|=1<<r;
57871462 6403 if(branch_regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
6404 }
6405 }
6406 if(wr) {
6407 #ifndef DESTRUCTIVE_WRITEBACK
6408 branch_regs[i].dirty&=wont_dirty_i;
6409 #endif
6410 branch_regs[i].dirty|=will_dirty_i;
6411 }
6412 }
6413 else
6414 {
6415 // Internal branch
6416 if(ba[i]<=start+i*4) {
6417 // Backward branch
fe807a8a 6418 if (dops[i].is_ujump)
57871462 6419 {
6420 // Unconditional branch
6421 temp_will_dirty=0;
6422 temp_wont_dirty=0;
6423 // Merge in delay slot (will dirty)
6424 for(r=0;r<HOST_REGS;r++) {
6425 if(r!=EXCLUDE_REG) {
cf95b4f0 6426 if((branch_regs[i].regmap[r]&63)==dops[i].rt1) temp_will_dirty|=1<<r;
6427 if((branch_regs[i].regmap[r]&63)==dops[i].rt2) temp_will_dirty|=1<<r;
6428 if((branch_regs[i].regmap[r]&63)==dops[i+1].rt1) temp_will_dirty|=1<<r;
6429 if((branch_regs[i].regmap[r]&63)==dops[i+1].rt2) temp_will_dirty|=1<<r;
57871462 6430 if((branch_regs[i].regmap[r]&63)>33) temp_will_dirty&=~(1<<r);
6431 if(branch_regs[i].regmap[r]<=0) temp_will_dirty&=~(1<<r);
6432 if(branch_regs[i].regmap[r]==CCREG) temp_will_dirty|=1<<r;
cf95b4f0 6433 if((regs[i].regmap[r]&63)==dops[i].rt1) temp_will_dirty|=1<<r;
6434 if((regs[i].regmap[r]&63)==dops[i].rt2) temp_will_dirty|=1<<r;
6435 if((regs[i].regmap[r]&63)==dops[i+1].rt1) temp_will_dirty|=1<<r;
6436 if((regs[i].regmap[r]&63)==dops[i+1].rt2) temp_will_dirty|=1<<r;
57871462 6437 if((regs[i].regmap[r]&63)>33) temp_will_dirty&=~(1<<r);
6438 if(regs[i].regmap[r]<=0) temp_will_dirty&=~(1<<r);
6439 if(regs[i].regmap[r]==CCREG) temp_will_dirty|=1<<r;
6440 }
6441 }
6442 } else {
6443 // Conditional branch (not taken case)
6444 temp_will_dirty=will_dirty_next;
6445 temp_wont_dirty=wont_dirty_next;
6446 // Merge in delay slot (will dirty)
6447 for(r=0;r<HOST_REGS;r++) {
6448 if(r!=EXCLUDE_REG) {
fe807a8a 6449 if (1) { // !dops[i].likely) {
57871462 6450 // Will not dirty if likely branch is not taken
cf95b4f0 6451 if((branch_regs[i].regmap[r]&63)==dops[i].rt1) temp_will_dirty|=1<<r;
6452 if((branch_regs[i].regmap[r]&63)==dops[i].rt2) temp_will_dirty|=1<<r;
6453 if((branch_regs[i].regmap[r]&63)==dops[i+1].rt1) temp_will_dirty|=1<<r;
6454 if((branch_regs[i].regmap[r]&63)==dops[i+1].rt2) temp_will_dirty|=1<<r;
57871462 6455 if((branch_regs[i].regmap[r]&63)>33) temp_will_dirty&=~(1<<r);
6456 if(branch_regs[i].regmap[r]==0) temp_will_dirty&=~(1<<r);
6457 if(branch_regs[i].regmap[r]==CCREG) temp_will_dirty|=1<<r;
cf95b4f0 6458 //if((regs[i].regmap[r]&63)==dops[i].rt1) temp_will_dirty|=1<<r;
6459 //if((regs[i].regmap[r]&63)==dops[i].rt2) temp_will_dirty|=1<<r;
6460 if((regs[i].regmap[r]&63)==dops[i+1].rt1) temp_will_dirty|=1<<r;
6461 if((regs[i].regmap[r]&63)==dops[i+1].rt2) temp_will_dirty|=1<<r;
57871462 6462 if((regs[i].regmap[r]&63)>33) temp_will_dirty&=~(1<<r);
6463 if(regs[i].regmap[r]<=0) temp_will_dirty&=~(1<<r);
6464 if(regs[i].regmap[r]==CCREG) temp_will_dirty|=1<<r;
6465 }
6466 }
6467 }
6468 }
6469 // Merge in delay slot (wont dirty)
6470 for(r=0;r<HOST_REGS;r++) {
6471 if(r!=EXCLUDE_REG) {
cf95b4f0 6472 if((regs[i].regmap[r]&63)==dops[i].rt1) temp_wont_dirty|=1<<r;
6473 if((regs[i].regmap[r]&63)==dops[i].rt2) temp_wont_dirty|=1<<r;
6474 if((regs[i].regmap[r]&63)==dops[i+1].rt1) temp_wont_dirty|=1<<r;
6475 if((regs[i].regmap[r]&63)==dops[i+1].rt2) temp_wont_dirty|=1<<r;
57871462 6476 if(regs[i].regmap[r]==CCREG) temp_wont_dirty|=1<<r;
cf95b4f0 6477 if((branch_regs[i].regmap[r]&63)==dops[i].rt1) temp_wont_dirty|=1<<r;
6478 if((branch_regs[i].regmap[r]&63)==dops[i].rt2) temp_wont_dirty|=1<<r;
6479 if((branch_regs[i].regmap[r]&63)==dops[i+1].rt1) temp_wont_dirty|=1<<r;
6480 if((branch_regs[i].regmap[r]&63)==dops[i+1].rt2) temp_wont_dirty|=1<<r;
57871462 6481 if(branch_regs[i].regmap[r]==CCREG) temp_wont_dirty|=1<<r;
6482 }
6483 }
6484 // Deal with changed mappings
6485 if(i<iend) {
6486 for(r=0;r<HOST_REGS;r++) {
6487 if(r!=EXCLUDE_REG) {
6488 if(regs[i].regmap[r]!=regmap_pre[i][r]) {
6489 temp_will_dirty&=~(1<<r);
6490 temp_wont_dirty&=~(1<<r);
6491 if((regmap_pre[i][r]&63)>0 && (regmap_pre[i][r]&63)<34) {
6492 temp_will_dirty|=((unneeded_reg[i]>>(regmap_pre[i][r]&63))&1)<<r;
6493 temp_wont_dirty|=((unneeded_reg[i]>>(regmap_pre[i][r]&63))&1)<<r;
6494 } else {
6495 temp_will_dirty|=1<<r;
6496 temp_wont_dirty|=1<<r;
6497 }
6498 }
6499 }
6500 }
6501 }
6502 if(wr) {
6503 will_dirty[i]=temp_will_dirty;
6504 wont_dirty[i]=temp_wont_dirty;
6505 clean_registers((ba[i]-start)>>2,i-1,0);
6506 }else{
6507 // Limit recursion. It can take an excessive amount
6508 // of time if there are a lot of nested loops.
6509 will_dirty[(ba[i]-start)>>2]=0;
6510 wont_dirty[(ba[i]-start)>>2]=-1;
6511 }
6512 }
6513 /*else*/ if(1)
6514 {
fe807a8a 6515 if (dops[i].is_ujump)
57871462 6516 {
6517 // Unconditional branch
6518 will_dirty_i=0;
6519 wont_dirty_i=0;
6520 //if(ba[i]>start+i*4) { // Disable recursion (for debugging)
6521 for(r=0;r<HOST_REGS;r++) {
6522 if(r!=EXCLUDE_REG) {
6523 if(branch_regs[i].regmap[r]==regs[(ba[i]-start)>>2].regmap_entry[r]) {
6524 will_dirty_i|=will_dirty[(ba[i]-start)>>2]&(1<<r);
6525 wont_dirty_i|=wont_dirty[(ba[i]-start)>>2]&(1<<r);
6526 }
e3234ecf 6527 if(branch_regs[i].regmap[r]>=0) {
6528 will_dirty_i|=((unneeded_reg[(ba[i]-start)>>2]>>(branch_regs[i].regmap[r]&63))&1)<<r;
6529 wont_dirty_i|=((unneeded_reg[(ba[i]-start)>>2]>>(branch_regs[i].regmap[r]&63))&1)<<r;
6530 }
57871462 6531 }
6532 }
6533 //}
6534 // Merge in delay slot
6535 for(r=0;r<HOST_REGS;r++) {
6536 if(r!=EXCLUDE_REG) {
cf95b4f0 6537 if((branch_regs[i].regmap[r]&63)==dops[i].rt1) will_dirty_i|=1<<r;
6538 if((branch_regs[i].regmap[r]&63)==dops[i].rt2) will_dirty_i|=1<<r;
6539 if((branch_regs[i].regmap[r]&63)==dops[i+1].rt1) will_dirty_i|=1<<r;
6540 if((branch_regs[i].regmap[r]&63)==dops[i+1].rt2) will_dirty_i|=1<<r;
57871462 6541 if((branch_regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
6542 if(branch_regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
6543 if(branch_regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
cf95b4f0 6544 if((regs[i].regmap[r]&63)==dops[i].rt1) will_dirty_i|=1<<r;
6545 if((regs[i].regmap[r]&63)==dops[i].rt2) will_dirty_i|=1<<r;
6546 if((regs[i].regmap[r]&63)==dops[i+1].rt1) will_dirty_i|=1<<r;
6547 if((regs[i].regmap[r]&63)==dops[i+1].rt2) will_dirty_i|=1<<r;
57871462 6548 if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
6549 if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
6550 if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
6551 }
6552 }
6553 } else {
6554 // Conditional branch
6555 will_dirty_i=will_dirty_next;
6556 wont_dirty_i=wont_dirty_next;
6557 //if(ba[i]>start+i*4) { // Disable recursion (for debugging)
6558 for(r=0;r<HOST_REGS;r++) {
6559 if(r!=EXCLUDE_REG) {
e3234ecf 6560 signed char target_reg=branch_regs[i].regmap[r];
6561 if(target_reg==regs[(ba[i]-start)>>2].regmap_entry[r]) {
57871462 6562 will_dirty_i&=will_dirty[(ba[i]-start)>>2]&(1<<r);
6563 wont_dirty_i|=wont_dirty[(ba[i]-start)>>2]&(1<<r);
6564 }
e3234ecf 6565 else if(target_reg>=0) {
6566 will_dirty_i&=((unneeded_reg[(ba[i]-start)>>2]>>(target_reg&63))&1)<<r;
6567 wont_dirty_i|=((unneeded_reg[(ba[i]-start)>>2]>>(target_reg&63))&1)<<r;
57871462 6568 }
57871462 6569 }
6570 }
6571 //}
6572 // Merge in delay slot
6573 for(r=0;r<HOST_REGS;r++) {
6574 if(r!=EXCLUDE_REG) {
fe807a8a 6575 if (1) { // !dops[i].likely) {
57871462 6576 // Might not dirty if likely branch is not taken
cf95b4f0 6577 if((branch_regs[i].regmap[r]&63)==dops[i].rt1) will_dirty_i|=1<<r;
6578 if((branch_regs[i].regmap[r]&63)==dops[i].rt2) will_dirty_i|=1<<r;
6579 if((branch_regs[i].regmap[r]&63)==dops[i+1].rt1) will_dirty_i|=1<<r;
6580 if((branch_regs[i].regmap[r]&63)==dops[i+1].rt2) will_dirty_i|=1<<r;
57871462 6581 if((branch_regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
6582 if(branch_regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
6583 if(branch_regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
cf95b4f0 6584 //if((regs[i].regmap[r]&63)==dops[i].rt1) will_dirty_i|=1<<r;
6585 //if((regs[i].regmap[r]&63)==dops[i].rt2) will_dirty_i|=1<<r;
6586 if((regs[i].regmap[r]&63)==dops[i+1].rt1) will_dirty_i|=1<<r;
6587 if((regs[i].regmap[r]&63)==dops[i+1].rt2) will_dirty_i|=1<<r;
57871462 6588 if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
6589 if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
6590 if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
6591 }
6592 }
6593 }
6594 }
e3234ecf 6595 // Merge in delay slot (won't dirty)
57871462 6596 for(r=0;r<HOST_REGS;r++) {
6597 if(r!=EXCLUDE_REG) {
cf95b4f0 6598 if((regs[i].regmap[r]&63)==dops[i].rt1) wont_dirty_i|=1<<r;
6599 if((regs[i].regmap[r]&63)==dops[i].rt2) wont_dirty_i|=1<<r;
6600 if((regs[i].regmap[r]&63)==dops[i+1].rt1) wont_dirty_i|=1<<r;
6601 if((regs[i].regmap[r]&63)==dops[i+1].rt2) wont_dirty_i|=1<<r;
57871462 6602 if(regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
cf95b4f0 6603 if((branch_regs[i].regmap[r]&63)==dops[i].rt1) wont_dirty_i|=1<<r;
6604 if((branch_regs[i].regmap[r]&63)==dops[i].rt2) wont_dirty_i|=1<<r;
6605 if((branch_regs[i].regmap[r]&63)==dops[i+1].rt1) wont_dirty_i|=1<<r;
6606 if((branch_regs[i].regmap[r]&63)==dops[i+1].rt2) wont_dirty_i|=1<<r;
57871462 6607 if(branch_regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
6608 }
6609 }
6610 if(wr) {
6611 #ifndef DESTRUCTIVE_WRITEBACK
6612 branch_regs[i].dirty&=wont_dirty_i;
6613 #endif
6614 branch_regs[i].dirty|=will_dirty_i;
6615 }
6616 }
6617 }
6618 }
cf95b4f0 6619 else if(dops[i].itype==SYSCALL||dops[i].itype==HLECALL||dops[i].itype==INTCALL)
57871462 6620 {
6621 // SYSCALL instruction (software interrupt)
6622 will_dirty_i=0;
6623 wont_dirty_i=0;
6624 }
cf95b4f0 6625 else if(dops[i].itype==COP0 && (source[i]&0x3f)==0x18)
57871462 6626 {
6627 // ERET instruction (return from interrupt)
6628 will_dirty_i=0;
6629 wont_dirty_i=0;
6630 }
6631 will_dirty_next=will_dirty_i;
6632 wont_dirty_next=wont_dirty_i;
6633 for(r=0;r<HOST_REGS;r++) {
6634 if(r!=EXCLUDE_REG) {
cf95b4f0 6635 if((regs[i].regmap[r]&63)==dops[i].rt1) will_dirty_i|=1<<r;
6636 if((regs[i].regmap[r]&63)==dops[i].rt2) will_dirty_i|=1<<r;
57871462 6637 if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
6638 if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
6639 if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
cf95b4f0 6640 if((regs[i].regmap[r]&63)==dops[i].rt1) wont_dirty_i|=1<<r;
6641 if((regs[i].regmap[r]&63)==dops[i].rt2) wont_dirty_i|=1<<r;
57871462 6642 if(regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
6643 if(i>istart) {
fe807a8a 6644 if (!dops[i].is_jump)
57871462 6645 {
6646 // Don't store a register immediately after writing it,
6647 // may prevent dual-issue.
cf95b4f0 6648 if((regs[i].regmap[r]&63)==dops[i-1].rt1) wont_dirty_i|=1<<r;
6649 if((regs[i].regmap[r]&63)==dops[i-1].rt2) wont_dirty_i|=1<<r;
57871462 6650 }
6651 }
6652 }
6653 }
6654 // Save it
6655 will_dirty[i]=will_dirty_i;
6656 wont_dirty[i]=wont_dirty_i;
6657 // Mark registers that won't be dirtied as not dirty
6658 if(wr) {
57871462 6659 regs[i].dirty|=will_dirty_i;
6660 #ifndef DESTRUCTIVE_WRITEBACK
6661 regs[i].dirty&=wont_dirty_i;
fe807a8a 6662 if(dops[i].is_jump)
57871462 6663 {
fe807a8a 6664 if (i < iend-1 && !dops[i].is_ujump) {
57871462 6665 for(r=0;r<HOST_REGS;r++) {
6666 if(r!=EXCLUDE_REG) {
6667 if(regs[i].regmap[r]==regmap_pre[i+2][r]) {
6668 regs[i+2].wasdirty&=wont_dirty_i|~(1<<r);
581335b0 6669 }else {/*printf("i: %x (%d) mismatch(+2): %d\n",start+i*4,i,r);assert(!((wont_dirty_i>>r)&1));*/}
57871462 6670 }
6671 }
6672 }
6673 }
6674 else
6675 {
6676 if(i<iend) {
6677 for(r=0;r<HOST_REGS;r++) {
6678 if(r!=EXCLUDE_REG) {
6679 if(regs[i].regmap[r]==regmap_pre[i+1][r]) {
6680 regs[i+1].wasdirty&=wont_dirty_i|~(1<<r);
581335b0 6681 }else {/*printf("i: %x (%d) mismatch(+1): %d\n",start+i*4,i,r);assert(!((wont_dirty_i>>r)&1));*/}
57871462 6682 }
6683 }
6684 }
6685 }
6686 #endif
6687 //}
6688 }
6689 // Deal with changed mappings
6690 temp_will_dirty=will_dirty_i;
6691 temp_wont_dirty=wont_dirty_i;
6692 for(r=0;r<HOST_REGS;r++) {
6693 if(r!=EXCLUDE_REG) {
6694 int nr;
6695 if(regs[i].regmap[r]==regmap_pre[i][r]) {
6696 if(wr) {
6697 #ifndef DESTRUCTIVE_WRITEBACK
6698 regs[i].wasdirty&=wont_dirty_i|~(1<<r);
6699 #endif
6700 regs[i].wasdirty|=will_dirty_i&(1<<r);
6701 }
6702 }
f776eb14 6703 else if(regmap_pre[i][r]>=0&&(nr=get_reg(regs[i].regmap,regmap_pre[i][r]))>=0) {
57871462 6704 // Register moved to a different register
6705 will_dirty_i&=~(1<<r);
6706 wont_dirty_i&=~(1<<r);
6707 will_dirty_i|=((temp_will_dirty>>nr)&1)<<r;
6708 wont_dirty_i|=((temp_wont_dirty>>nr)&1)<<r;
6709 if(wr) {
6710 #ifndef DESTRUCTIVE_WRITEBACK
6711 regs[i].wasdirty&=wont_dirty_i|~(1<<r);
6712 #endif
6713 regs[i].wasdirty|=will_dirty_i&(1<<r);
6714 }
6715 }
6716 else {
6717 will_dirty_i&=~(1<<r);
6718 wont_dirty_i&=~(1<<r);
6719 if((regmap_pre[i][r]&63)>0 && (regmap_pre[i][r]&63)<34) {
6720 will_dirty_i|=((unneeded_reg[i]>>(regmap_pre[i][r]&63))&1)<<r;
6721 wont_dirty_i|=((unneeded_reg[i]>>(regmap_pre[i][r]&63))&1)<<r;
6722 } else {
6723 wont_dirty_i|=1<<r;
581335b0 6724 /*printf("i: %x (%d) mismatch: %d\n",start+i*4,i,r);assert(!((will_dirty>>r)&1));*/
57871462 6725 }
6726 }
6727 }
6728 }
6729 }
6730}
6731
4600ba03 6732#ifdef DISASM
2acc46cd 6733#include <inttypes.h>
6734void print_regmap(const char *name, const signed char *regmap)
6735{
6736 char buf[5];
6737 int i, l;
6738 fputs(name, stdout);
6739 for (i = 0; i < HOST_REGS; i++) {
6740 l = 0;
6741 if (regmap[i] >= 0)
6742 l = snprintf(buf, sizeof(buf), "$%d", regmap[i]);
6743 for (; l < 3; l++)
6744 buf[l] = ' ';
6745 buf[l] = 0;
6746 printf(" r%d=%s", i, buf);
6747 }
6748 fputs("\n", stdout);
6749}
6750
57871462 6751 /* disassembly */
6752void disassemble_inst(int i)
6753{
cf95b4f0 6754 if (dops[i].bt) printf("*"); else printf(" ");
6755 switch(dops[i].itype) {
57871462 6756 case UJUMP:
6757 printf (" %x: %s %8x\n",start+i*4,insn[i],ba[i]);break;
6758 case CJUMP:
cf95b4f0 6759 printf (" %x: %s r%d,r%d,%8x\n",start+i*4,insn[i],dops[i].rs1,dops[i].rs2,i?start+i*4+4+((signed int)((unsigned int)source[i]<<16)>>14):*ba);break;
57871462 6760 case SJUMP:
cf95b4f0 6761 printf (" %x: %s r%d,%8x\n",start+i*4,insn[i],dops[i].rs1,start+i*4+4+((signed int)((unsigned int)source[i]<<16)>>14));break;
57871462 6762 case RJUMP:
cf95b4f0 6763 if (dops[i].opcode==0x9&&dops[i].rt1!=31)
6764 printf (" %x: %s r%d,r%d\n",start+i*4,insn[i],dops[i].rt1,dops[i].rs1);
5067f341 6765 else
cf95b4f0 6766 printf (" %x: %s r%d\n",start+i*4,insn[i],dops[i].rs1);
5067f341 6767 break;
57871462 6768 case SPAN:
cf95b4f0 6769 printf (" %x: %s (pagespan) r%d,r%d,%8x\n",start+i*4,insn[i],dops[i].rs1,dops[i].rs2,ba[i]);break;
57871462 6770 case IMM16:
cf95b4f0 6771 if(dops[i].opcode==0xf) //LUI
6772 printf (" %x: %s r%d,%4x0000\n",start+i*4,insn[i],dops[i].rt1,imm[i]&0xffff);
57871462 6773 else
cf95b4f0 6774 printf (" %x: %s r%d,r%d,%d\n",start+i*4,insn[i],dops[i].rt1,dops[i].rs1,imm[i]);
57871462 6775 break;
6776 case LOAD:
6777 case LOADLR:
cf95b4f0 6778 printf (" %x: %s r%d,r%d+%x\n",start+i*4,insn[i],dops[i].rt1,dops[i].rs1,imm[i]);
57871462 6779 break;
6780 case STORE:
6781 case STORELR:
cf95b4f0 6782 printf (" %x: %s r%d,r%d+%x\n",start+i*4,insn[i],dops[i].rs2,dops[i].rs1,imm[i]);
57871462 6783 break;
6784 case ALU:
6785 case SHIFT:
cf95b4f0 6786 printf (" %x: %s r%d,r%d,r%d\n",start+i*4,insn[i],dops[i].rt1,dops[i].rs1,dops[i].rs2);
57871462 6787 break;
6788 case MULTDIV:
cf95b4f0 6789 printf (" %x: %s r%d,r%d\n",start+i*4,insn[i],dops[i].rs1,dops[i].rs2);
57871462 6790 break;
6791 case SHIFTIMM:
cf95b4f0 6792 printf (" %x: %s r%d,r%d,%d\n",start+i*4,insn[i],dops[i].rt1,dops[i].rs1,imm[i]);
57871462 6793 break;
6794 case MOV:
cf95b4f0 6795 if((dops[i].opcode2&0x1d)==0x10)
6796 printf (" %x: %s r%d\n",start+i*4,insn[i],dops[i].rt1);
6797 else if((dops[i].opcode2&0x1d)==0x11)
6798 printf (" %x: %s r%d\n",start+i*4,insn[i],dops[i].rs1);
57871462 6799 else
6800 printf (" %x: %s\n",start+i*4,insn[i]);
6801 break;
6802 case COP0:
cf95b4f0 6803 if(dops[i].opcode2==0)
6804 printf (" %x: %s r%d,cpr0[%d]\n",start+i*4,insn[i],dops[i].rt1,(source[i]>>11)&0x1f); // MFC0
6805 else if(dops[i].opcode2==4)
6806 printf (" %x: %s r%d,cpr0[%d]\n",start+i*4,insn[i],dops[i].rs1,(source[i]>>11)&0x1f); // MTC0
57871462 6807 else printf (" %x: %s\n",start+i*4,insn[i]);
6808 break;
6809 case COP1:
cf95b4f0 6810 if(dops[i].opcode2<3)
6811 printf (" %x: %s r%d,cpr1[%d]\n",start+i*4,insn[i],dops[i].rt1,(source[i]>>11)&0x1f); // MFC1
6812 else if(dops[i].opcode2>3)
6813 printf (" %x: %s r%d,cpr1[%d]\n",start+i*4,insn[i],dops[i].rs1,(source[i]>>11)&0x1f); // MTC1
57871462 6814 else printf (" %x: %s\n",start+i*4,insn[i]);
6815 break;
b9b61529 6816 case COP2:
cf95b4f0 6817 if(dops[i].opcode2<3)
6818 printf (" %x: %s r%d,cpr2[%d]\n",start+i*4,insn[i],dops[i].rt1,(source[i]>>11)&0x1f); // MFC2
6819 else if(dops[i].opcode2>3)
6820 printf (" %x: %s r%d,cpr2[%d]\n",start+i*4,insn[i],dops[i].rs1,(source[i]>>11)&0x1f); // MTC2
b9b61529 6821 else printf (" %x: %s\n",start+i*4,insn[i]);
6822 break;
57871462 6823 case C1LS:
cf95b4f0 6824 printf (" %x: %s cpr1[%d],r%d+%x\n",start+i*4,insn[i],(source[i]>>16)&0x1f,dops[i].rs1,imm[i]);
57871462 6825 break;
b9b61529 6826 case C2LS:
cf95b4f0 6827 printf (" %x: %s cpr2[%d],r%d+%x\n",start+i*4,insn[i],(source[i]>>16)&0x1f,dops[i].rs1,imm[i]);
b9b61529 6828 break;
1e973cb0 6829 case INTCALL:
6830 printf (" %x: %s (INTCALL)\n",start+i*4,insn[i]);
6831 break;
57871462 6832 default:
6833 //printf (" %s %8x\n",insn[i],source[i]);
6834 printf (" %x: %s\n",start+i*4,insn[i]);
6835 }
2acc46cd 6836 return;
6837 printf("D: %"PRIu64" WD: %"PRIu64" U: %"PRIu64"\n",
6838 regs[i].dirty, regs[i].wasdirty, unneeded_reg[i]);
6839 print_regmap("pre: ", regmap_pre[i]);
6840 print_regmap("entry: ", regs[i].regmap_entry);
6841 print_regmap("map: ", regs[i].regmap);
6842 if (dops[i].is_jump) {
6843 print_regmap("bentry:", branch_regs[i].regmap_entry);
6844 print_regmap("bmap: ", branch_regs[i].regmap);
6845 }
57871462 6846}
4600ba03 6847#else
6848static void disassemble_inst(int i) {}
6849#endif // DISASM
57871462 6850
d848b60a 6851#define DRC_TEST_VAL 0x74657374
6852
be516ebe 6853static void new_dynarec_test(void)
d848b60a 6854{
be516ebe 6855 int (*testfunc)(void);
d148d265 6856 void *beginning;
be516ebe 6857 int ret[2];
6858 size_t i;
d148d265 6859
687b4580 6860 // check structure linkage
7c3a5182 6861 if ((u_char *)rcnts - (u_char *)&psxRegs != sizeof(psxRegs))
687b4580 6862 {
7c3a5182 6863 SysPrintf("linkage_arm* miscompilation/breakage detected.\n");
687b4580 6864 }
6865
761fdd0a 6866 SysPrintf("testing if we can run recompiled code @%p...\n", out);
be516ebe 6867 ((volatile u_int *)out)[0]++; // make cache dirty
6868
6869 for (i = 0; i < ARRAY_SIZE(ret); i++) {
2a014d73 6870 out = ndrc->translation_cache;
be516ebe 6871 beginning = start_block();
6872 emit_movimm(DRC_TEST_VAL + i, 0); // test
6873 emit_ret();
6874 literal_pool(0);
6875 end_block(beginning);
6876 testfunc = beginning;
6877 ret[i] = testfunc();
6878 }
6879
6880 if (ret[0] == DRC_TEST_VAL && ret[1] == DRC_TEST_VAL + 1)
d848b60a 6881 SysPrintf("test passed.\n");
6882 else
be516ebe 6883 SysPrintf("test failed, will likely crash soon (r=%08x %08x)\n", ret[0], ret[1]);
2a014d73 6884 out = ndrc->translation_cache;
d848b60a 6885}
6886
dc990066 6887// clear the state completely, instead of just marking
6888// things invalid like invalidate_all_pages() does
919981d0 6889void new_dynarec_clear_full(void)
57871462 6890{
57871462 6891 int n;
2a014d73 6892 out = ndrc->translation_cache;
35775df7 6893 memset(invalid_code,1,sizeof(invalid_code));
6894 memset(hash_table,0xff,sizeof(hash_table));
57871462 6895 memset(mini_ht,-1,sizeof(mini_ht));
6896 memset(restore_candidate,0,sizeof(restore_candidate));
dc990066 6897 memset(shadow,0,sizeof(shadow));
57871462 6898 copy=shadow;
6899 expirep=16384; // Expiry pointer, +2 blocks
6900 pending_exception=0;
6901 literalcount=0;
57871462 6902 stop_after_jal=0;
9be4ba64 6903 inv_code_start=inv_code_end=~0;
7f94b097 6904 hack_addr=0;
39b71d9a 6905 f1_hack=0;
57871462 6906 // TLB
dc990066 6907 for(n=0;n<4096;n++) ll_clear(jump_in+n);
6908 for(n=0;n<4096;n++) ll_clear(jump_out+n);
6909 for(n=0;n<4096;n++) ll_clear(jump_dirty+n);
32631e6a 6910
6911 cycle_multiplier_old = cycle_multiplier;
6912 new_dynarec_hacks_old = new_dynarec_hacks;
dc990066 6913}
6914
919981d0 6915void new_dynarec_init(void)
dc990066 6916{
66ea165f 6917 SysPrintf("Init new dynarec, ndrc size %x\n", (int)sizeof(*ndrc));
1e212a25 6918
0aeb0cb9 6919#ifdef _3DS
6920 check_rosalina();
6921#endif
2a014d73 6922#ifdef BASE_ADDR_DYNAMIC
1e212a25 6923 #ifdef VITA
0aeb0cb9 6924 sceBlock = getVMBlock(); //sceKernelAllocMemBlockForVM("code", sizeof(*ndrc));
66ea165f 6925 if (sceBlock <= 0)
6926 SysPrintf("sceKernelAllocMemBlockForVM failed: %x\n", sceBlock);
2a014d73 6927 int ret = sceKernelGetMemBlockBase(sceBlock, (void **)&ndrc);
1e212a25 6928 if (ret < 0)
66ea165f 6929 SysPrintf("sceKernelGetMemBlockBase failed: %x\n", ret);
0aeb0cb9 6930 sceKernelOpenVMDomain();
6931 sceClibPrintf("translation_cache = 0x%08lx\n ", (long)ndrc->translation_cache);
6932 #elif defined(_MSC_VER)
6933 ndrc = VirtualAlloc(NULL, sizeof(*ndrc), MEM_COMMIT | MEM_RESERVE,
6934 PAGE_EXECUTE_READWRITE);
1e212a25 6935 #else
2a014d73 6936 uintptr_t desired_addr = 0;
6937 #ifdef __ELF__
6938 extern char _end;
6939 desired_addr = ((uintptr_t)&_end + 0xffffff) & ~0xffffffl;
6940 #endif
6941 ndrc = mmap((void *)desired_addr, sizeof(*ndrc),
1e212a25 6942 PROT_READ | PROT_WRITE | PROT_EXEC,
6943 MAP_PRIVATE | MAP_ANONYMOUS, -1, 0);
2a014d73 6944 if (ndrc == MAP_FAILED) {
d848b60a 6945 SysPrintf("mmap() failed: %s\n", strerror(errno));
1e212a25 6946 abort();
d848b60a 6947 }
1e212a25 6948 #endif
6949#else
6950 #ifndef NO_WRITE_EXEC
bdeade46 6951 // not all systems allow execute in data segment by default
761fdd0a 6952 // size must be 4K aligned for 3DS?
6953 if (mprotect(ndrc, sizeof(*ndrc),
2a014d73 6954 PROT_READ | PROT_WRITE | PROT_EXEC) != 0)
d848b60a 6955 SysPrintf("mprotect() failed: %s\n", strerror(errno));
1e212a25 6956 #endif
dc990066 6957#endif
2a014d73 6958 out = ndrc->translation_cache;
2573466a 6959 cycle_multiplier=200;
dc990066 6960 new_dynarec_clear_full();
6961#ifdef HOST_IMM8
6962 // Copy this into local area so we don't have to put it in every literal pool
6963 invc_ptr=invalid_code;
6964#endif
57871462 6965 arch_init();
d848b60a 6966 new_dynarec_test();
01d26796 6967 ram_offset=(uintptr_t)rdram-0x80000000;
b105cf4f 6968 if (ram_offset!=0)
c43b5311 6969 SysPrintf("warning: RAM is not directly mapped, performance will suffer\n");
57871462 6970}
6971
919981d0 6972void new_dynarec_cleanup(void)
57871462 6973{
6974 int n;
2a014d73 6975#ifdef BASE_ADDR_DYNAMIC
1e212a25 6976 #ifdef VITA
66ea165f 6977 // sceBlock is managed by retroarch's bootstrap code
9c67c98f 6978 //sceKernelFreeMemBlock(sceBlock);
6979 //sceBlock = -1;
1e212a25 6980 #else
2a014d73 6981 if (munmap(ndrc, sizeof(*ndrc)) < 0)
1e212a25 6982 SysPrintf("munmap() failed\n");
bdeade46 6983 #endif
1e212a25 6984#endif
57871462 6985 for(n=0;n<4096;n++) ll_clear(jump_in+n);
6986 for(n=0;n<4096;n++) ll_clear(jump_out+n);
6987 for(n=0;n<4096;n++) ll_clear(jump_dirty+n);
6988 #ifdef ROM_COPY
c43b5311 6989 if (munmap (ROM_COPY, 67108864) < 0) {SysPrintf("munmap() failed\n");}
57871462 6990 #endif
6991}
6992
03f55e6b 6993static u_int *get_source_start(u_int addr, u_int *limit)
57871462 6994{
03f55e6b 6995 if (addr < 0x00200000 ||
a3203cf4 6996 (0xa0000000 <= addr && addr < 0xa0200000))
6997 {
03f55e6b 6998 // used for BIOS calls mostly?
6999 *limit = (addr&0xa0000000)|0x00200000;
01d26796 7000 return (u_int *)(rdram + (addr&0x1fffff));
03f55e6b 7001 }
7002 else if (!Config.HLE && (
7003 /* (0x9fc00000 <= addr && addr < 0x9fc80000) ||*/
a3203cf4 7004 (0xbfc00000 <= addr && addr < 0xbfc80000)))
7005 {
7006 // BIOS. The multiplier should be much higher as it's uncached 8bit mem,
7007 // but timings in PCSX are too tied to the interpreter's BIAS
d62c125a 7008 if (!HACK_ENABLED(NDHACK_OVERRIDE_CYCLE_M))
24058131 7009 cycle_multiplier_active = 200;
a3203cf4 7010
03f55e6b 7011 *limit = (addr & 0xfff00000) | 0x80000;
01d26796 7012 return (u_int *)((u_char *)psxR + (addr&0x7ffff));
03f55e6b 7013 }
7014 else if (addr >= 0x80000000 && addr < 0x80000000+RAM_SIZE) {
7015 *limit = (addr & 0x80600000) + 0x00200000;
01d26796 7016 return (u_int *)(rdram + (addr&0x1fffff));
03f55e6b 7017 }
581335b0 7018 return NULL;
03f55e6b 7019}
7020
7021static u_int scan_for_ret(u_int addr)
7022{
7023 u_int limit = 0;
7024 u_int *mem;
7025
7026 mem = get_source_start(addr, &limit);
7027 if (mem == NULL)
7028 return addr;
7029
7030 if (limit > addr + 0x1000)
7031 limit = addr + 0x1000;
7032 for (; addr < limit; addr += 4, mem++) {
7033 if (*mem == 0x03e00008) // jr $ra
7034 return addr + 8;
57871462 7035 }
581335b0 7036 return addr;
03f55e6b 7037}
7038
7039struct savestate_block {
7040 uint32_t addr;
7041 uint32_t regflags;
7042};
7043
7044static int addr_cmp(const void *p1_, const void *p2_)
7045{
7046 const struct savestate_block *p1 = p1_, *p2 = p2_;
7047 return p1->addr - p2->addr;
7048}
7049
7050int new_dynarec_save_blocks(void *save, int size)
7051{
7052 struct savestate_block *blocks = save;
7053 int maxcount = size / sizeof(blocks[0]);
7054 struct savestate_block tmp_blocks[1024];
7055 struct ll_entry *head;
7056 int p, s, d, o, bcnt;
7057 u_int addr;
7058
7059 o = 0;
b14b6a8f 7060 for (p = 0; p < ARRAY_SIZE(jump_in); p++) {
03f55e6b 7061 bcnt = 0;
7062 for (head = jump_in[p]; head != NULL; head = head->next) {
7063 tmp_blocks[bcnt].addr = head->vaddr;
7064 tmp_blocks[bcnt].regflags = head->reg_sv_flags;
7065 bcnt++;
7066 }
7067 if (bcnt < 1)
7068 continue;
7069 qsort(tmp_blocks, bcnt, sizeof(tmp_blocks[0]), addr_cmp);
7070
7071 addr = tmp_blocks[0].addr;
7072 for (s = d = 0; s < bcnt; s++) {
7073 if (tmp_blocks[s].addr < addr)
7074 continue;
7075 if (d == 0 || tmp_blocks[d-1].addr != tmp_blocks[s].addr)
7076 tmp_blocks[d++] = tmp_blocks[s];
7077 addr = scan_for_ret(tmp_blocks[s].addr);
7078 }
7079
7080 if (o + d > maxcount)
7081 d = maxcount - o;
7082 memcpy(&blocks[o], tmp_blocks, d * sizeof(blocks[0]));
7083 o += d;
7084 }
7085
7086 return o * sizeof(blocks[0]);
7087}
7088
7089void new_dynarec_load_blocks(const void *save, int size)
7090{
7091 const struct savestate_block *blocks = save;
7092 int count = size / sizeof(blocks[0]);
7093 u_int regs_save[32];
7094 uint32_t f;
7095 int i, b;
7096
7097 get_addr(psxRegs.pc);
7098
7099 // change GPRs for speculation to at least partially work..
7100 memcpy(regs_save, &psxRegs.GPR, sizeof(regs_save));
7101 for (i = 1; i < 32; i++)
7102 psxRegs.GPR.r[i] = 0x80000000;
7103
7104 for (b = 0; b < count; b++) {
7105 for (f = blocks[b].regflags, i = 0; f; f >>= 1, i++) {
7106 if (f & 1)
7107 psxRegs.GPR.r[i] = 0x1f800000;
7108 }
7109
7110 get_addr(blocks[b].addr);
7111
7112 for (f = blocks[b].regflags, i = 0; f; f >>= 1, i++) {
7113 if (f & 1)
7114 psxRegs.GPR.r[i] = 0x80000000;
7115 }
7116 }
7117
7118 memcpy(&psxRegs.GPR, regs_save, sizeof(regs_save));
7119}
7120
7f94b097 7121static int apply_hacks(void)
24058131 7122{
7123 int i;
7124 if (HACK_ENABLED(NDHACK_NO_COMPAT_HACKS))
7f94b097 7125 return 0;
24058131 7126 /* special hack(s) */
7127 for (i = 0; i < slen - 4; i++)
7128 {
7129 // lui a4, 0xf200; jal <rcnt_read>; addu a0, 2; slti v0, 28224
7130 if (source[i] == 0x3c04f200 && dops[i+1].itype == UJUMP
7131 && source[i+2] == 0x34840002 && dops[i+3].opcode == 0x0a
7132 && imm[i+3] == 0x6e40 && dops[i+3].rs1 == 2)
7133 {
7134 SysPrintf("PE2 hack @%08x\n", start + (i+3)*4);
7135 dops[i + 3].itype = NOP;
7136 }
7137 }
7138 i = slen;
7139 if (i > 10 && source[i-1] == 0 && source[i-2] == 0x03e00008
7140 && source[i-4] == 0x8fbf0018 && source[i-6] == 0x00c0f809
7141 && dops[i-7].itype == STORE)
7142 {
7143 i = i-8;
7144 if (dops[i].itype == IMM16)
7145 i--;
7146 // swl r2, 15(r6); swr r2, 12(r6); sw r6, *; jalr r6
7147 if (dops[i].itype == STORELR && dops[i].rs1 == 6
7148 && dops[i-1].itype == STORELR && dops[i-1].rs1 == 6)
7149 {
7f94b097 7150 SysPrintf("F1 hack from %08x, old dst %08x\n", start, hack_addr);
7151 f1_hack = 1;
7152 return 1;
24058131 7153 }
7154 }
7f94b097 7155 return 0;
24058131 7156}
7157
3968e69e 7158int new_recompile_block(u_int addr)
03f55e6b 7159{
7160 u_int pagelimit = 0;
7161 u_int state_rflags = 0;
7162 int i;
7163
1a4301c4 7164 assem_debug("NOTCOMPILED: addr = %x -> %p\n", addr, out);
57871462 7165 //printf("TRACE: count=%d next=%d (compile %x)\n",Count,next_interupt,addr);
9f51b4b9 7166 //if(debug)
57871462 7167 //printf("fpu mapping=%x enabled=%x\n",(Status & 0x04000000)>>26,(Status & 0x20000000)>>29);
03f55e6b 7168
7169 // this is just for speculation
7170 for (i = 1; i < 32; i++) {
7171 if ((psxRegs.GPR.r[i] & 0xffff0000) == 0x1f800000)
7172 state_rflags |= 1 << i;
7173 }
7174
57871462 7175 start = (u_int)addr&~3;
7c3a5182 7176 //assert(((u_int)addr&1)==0); // start-in-delay-slot flag
2f546f9a 7177 new_dynarec_did_compile=1;
9ad4d757 7178 if (Config.HLE && start == 0x80001000) // hlecall
560e4a12 7179 {
7139f3c8 7180 // XXX: is this enough? Maybe check hleSoftCall?
d148d265 7181 void *beginning=start_block();
7139f3c8 7182 u_int page=get_page(start);
d148d265 7183
7139f3c8 7184 invalid_code[start>>12]=0;
7185 emit_movimm(start,0);
643aeae3 7186 emit_writeword(0,&pcaddr);
2a014d73 7187 emit_far_jump(new_dyna_leave);
15776b68 7188 literal_pool(0);
d148d265 7189 end_block(beginning);
03f55e6b 7190 ll_add_flags(jump_in+page,start,state_rflags,(void *)beginning);
7139f3c8 7191 return 0;
7192 }
7f94b097 7193 else if (f1_hack && hack_addr == 0) {
39b71d9a 7194 void *beginning = start_block();
7195 u_int page = get_page(start);
7f94b097 7196 emit_movimm(start, 0);
7197 emit_writeword(0, &hack_addr);
39b71d9a 7198 emit_readword(&psxRegs.GPR.n.sp, 0);
7199 emit_readptr(&mem_rtab, 1);
7200 emit_shrimm(0, 12, 2);
7201 emit_readptr_dualindexedx_ptrlen(1, 2, 1);
7202 emit_addimm(0, 0x18, 0);
7203 emit_adds_ptr(1, 1, 1);
7204 emit_ldr_dualindexed(1, 0, 0);
7205 emit_writeword(0, &psxRegs.GPR.r[26]); // lw k0, 0x18(sp)
7206 emit_far_call(get_addr_ht);
7207 emit_jmpreg(0); // jr k0
7208 literal_pool(0);
7209 end_block(beginning);
7210
7211 ll_add_flags(jump_in + page, start, state_rflags, beginning);
7212 SysPrintf("F1 hack to %08x\n", start);
39b71d9a 7213 return 0;
7214 }
03f55e6b 7215
24058131 7216 cycle_multiplier_active = cycle_multiplier_override && cycle_multiplier == CYCLE_MULT_DEFAULT
7217 ? cycle_multiplier_override : cycle_multiplier;
7218
03f55e6b 7219 source = get_source_start(start, &pagelimit);
7220 if (source == NULL) {
7221 SysPrintf("Compile at bogus memory address: %08x\n", addr);
7c3a5182 7222 abort();
57871462 7223 }
7224
7225 /* Pass 1: disassemble */
7226 /* Pass 2: register dependencies, branch targets */
7227 /* Pass 3: register allocation */
7228 /* Pass 4: branch dependencies */
7229 /* Pass 5: pre-alloc */
7230 /* Pass 6: optimize clean/dirty state */
7231 /* Pass 7: flag 32-bit registers */
7232 /* Pass 8: assembly */
7233 /* Pass 9: linker */
7234 /* Pass 10: garbage collection / free memory */
7235
03f55e6b 7236 int j;
57871462 7237 int done=0;
7238 unsigned int type,op,op2;
7239
7240 //printf("addr = %x source = %x %x\n", addr,source,source[0]);
9f51b4b9 7241
57871462 7242 /* Pass 1 disassembly */
7243
7ebfcedf 7244 for (i = 0; !done; i++)
7245 {
7246 memset(&dops[i], 0, sizeof(dops[i]));
cf95b4f0 7247 op2=0;
e1190b87 7248 minimum_free_regs[i]=0;
cf95b4f0 7249 dops[i].opcode=op=source[i]>>26;
57871462 7250 switch(op)
7251 {
7252 case 0x00: strcpy(insn[i],"special"); type=NI;
7253 op2=source[i]&0x3f;
7254 switch(op2)
7255 {
7256 case 0x00: strcpy(insn[i],"SLL"); type=SHIFTIMM; break;
7257 case 0x02: strcpy(insn[i],"SRL"); type=SHIFTIMM; break;
7258 case 0x03: strcpy(insn[i],"SRA"); type=SHIFTIMM; break;
7259 case 0x04: strcpy(insn[i],"SLLV"); type=SHIFT; break;
7260 case 0x06: strcpy(insn[i],"SRLV"); type=SHIFT; break;
7261 case 0x07: strcpy(insn[i],"SRAV"); type=SHIFT; break;
7262 case 0x08: strcpy(insn[i],"JR"); type=RJUMP; break;
7263 case 0x09: strcpy(insn[i],"JALR"); type=RJUMP; break;
7264 case 0x0C: strcpy(insn[i],"SYSCALL"); type=SYSCALL; break;
d1150cd6 7265 case 0x0D: strcpy(insn[i],"BREAK"); type=SYSCALL; break;
57871462 7266 case 0x0F: strcpy(insn[i],"SYNC"); type=OTHER; break;
7267 case 0x10: strcpy(insn[i],"MFHI"); type=MOV; break;
7268 case 0x11: strcpy(insn[i],"MTHI"); type=MOV; break;
7269 case 0x12: strcpy(insn[i],"MFLO"); type=MOV; break;
7270 case 0x13: strcpy(insn[i],"MTLO"); type=MOV; break;
57871462 7271 case 0x18: strcpy(insn[i],"MULT"); type=MULTDIV; break;
7272 case 0x19: strcpy(insn[i],"MULTU"); type=MULTDIV; break;
7273 case 0x1A: strcpy(insn[i],"DIV"); type=MULTDIV; break;
7274 case 0x1B: strcpy(insn[i],"DIVU"); type=MULTDIV; break;
57871462 7275 case 0x20: strcpy(insn[i],"ADD"); type=ALU; break;
7276 case 0x21: strcpy(insn[i],"ADDU"); type=ALU; break;
7277 case 0x22: strcpy(insn[i],"SUB"); type=ALU; break;
7278 case 0x23: strcpy(insn[i],"SUBU"); type=ALU; break;
7279 case 0x24: strcpy(insn[i],"AND"); type=ALU; break;
7280 case 0x25: strcpy(insn[i],"OR"); type=ALU; break;
7281 case 0x26: strcpy(insn[i],"XOR"); type=ALU; break;
7282 case 0x27: strcpy(insn[i],"NOR"); type=ALU; break;
7283 case 0x2A: strcpy(insn[i],"SLT"); type=ALU; break;
7284 case 0x2B: strcpy(insn[i],"SLTU"); type=ALU; break;
57871462 7285 case 0x30: strcpy(insn[i],"TGE"); type=NI; break;
7286 case 0x31: strcpy(insn[i],"TGEU"); type=NI; break;
7287 case 0x32: strcpy(insn[i],"TLT"); type=NI; break;
7288 case 0x33: strcpy(insn[i],"TLTU"); type=NI; break;
7289 case 0x34: strcpy(insn[i],"TEQ"); type=NI; break;
7290 case 0x36: strcpy(insn[i],"TNE"); type=NI; break;
71e490c5 7291#if 0
7f2607ea 7292 case 0x14: strcpy(insn[i],"DSLLV"); type=SHIFT; break;
7293 case 0x16: strcpy(insn[i],"DSRLV"); type=SHIFT; break;
7294 case 0x17: strcpy(insn[i],"DSRAV"); type=SHIFT; break;
7295 case 0x1C: strcpy(insn[i],"DMULT"); type=MULTDIV; break;
7296 case 0x1D: strcpy(insn[i],"DMULTU"); type=MULTDIV; break;
7297 case 0x1E: strcpy(insn[i],"DDIV"); type=MULTDIV; break;
7298 case 0x1F: strcpy(insn[i],"DDIVU"); type=MULTDIV; break;
7299 case 0x2C: strcpy(insn[i],"DADD"); type=ALU; break;
7300 case 0x2D: strcpy(insn[i],"DADDU"); type=ALU; break;
7301 case 0x2E: strcpy(insn[i],"DSUB"); type=ALU; break;
7302 case 0x2F: strcpy(insn[i],"DSUBU"); type=ALU; break;
57871462 7303 case 0x38: strcpy(insn[i],"DSLL"); type=SHIFTIMM; break;
7304 case 0x3A: strcpy(insn[i],"DSRL"); type=SHIFTIMM; break;
7305 case 0x3B: strcpy(insn[i],"DSRA"); type=SHIFTIMM; break;
7306 case 0x3C: strcpy(insn[i],"DSLL32"); type=SHIFTIMM; break;
7307 case 0x3E: strcpy(insn[i],"DSRL32"); type=SHIFTIMM; break;
7308 case 0x3F: strcpy(insn[i],"DSRA32"); type=SHIFTIMM; break;
7f2607ea 7309#endif
57871462 7310 }
7311 break;
7312 case 0x01: strcpy(insn[i],"regimm"); type=NI;
7313 op2=(source[i]>>16)&0x1f;
7314 switch(op2)
7315 {
7316 case 0x00: strcpy(insn[i],"BLTZ"); type=SJUMP; break;
7317 case 0x01: strcpy(insn[i],"BGEZ"); type=SJUMP; break;
4919de1e 7318 //case 0x02: strcpy(insn[i],"BLTZL"); type=SJUMP; break;
7319 //case 0x03: strcpy(insn[i],"BGEZL"); type=SJUMP; break;
7320 //case 0x08: strcpy(insn[i],"TGEI"); type=NI; break;
7321 //case 0x09: strcpy(insn[i],"TGEIU"); type=NI; break;
7322 //case 0x0A: strcpy(insn[i],"TLTI"); type=NI; break;
7323 //case 0x0B: strcpy(insn[i],"TLTIU"); type=NI; break;
7324 //case 0x0C: strcpy(insn[i],"TEQI"); type=NI; break;
7325 //case 0x0E: strcpy(insn[i],"TNEI"); type=NI; break;
57871462 7326 case 0x10: strcpy(insn[i],"BLTZAL"); type=SJUMP; break;
7327 case 0x11: strcpy(insn[i],"BGEZAL"); type=SJUMP; break;
4919de1e 7328 //case 0x12: strcpy(insn[i],"BLTZALL"); type=SJUMP; break;
7329 //case 0x13: strcpy(insn[i],"BGEZALL"); type=SJUMP; break;
57871462 7330 }
7331 break;
7332 case 0x02: strcpy(insn[i],"J"); type=UJUMP; break;
7333 case 0x03: strcpy(insn[i],"JAL"); type=UJUMP; break;
7334 case 0x04: strcpy(insn[i],"BEQ"); type=CJUMP; break;
7335 case 0x05: strcpy(insn[i],"BNE"); type=CJUMP; break;
7336 case 0x06: strcpy(insn[i],"BLEZ"); type=CJUMP; break;
7337 case 0x07: strcpy(insn[i],"BGTZ"); type=CJUMP; break;
7338 case 0x08: strcpy(insn[i],"ADDI"); type=IMM16; break;
7339 case 0x09: strcpy(insn[i],"ADDIU"); type=IMM16; break;
7340 case 0x0A: strcpy(insn[i],"SLTI"); type=IMM16; break;
7341 case 0x0B: strcpy(insn[i],"SLTIU"); type=IMM16; break;
7342 case 0x0C: strcpy(insn[i],"ANDI"); type=IMM16; break;
7343 case 0x0D: strcpy(insn[i],"ORI"); type=IMM16; break;
7344 case 0x0E: strcpy(insn[i],"XORI"); type=IMM16; break;
7345 case 0x0F: strcpy(insn[i],"LUI"); type=IMM16; break;
7346 case 0x10: strcpy(insn[i],"cop0"); type=NI;
7347 op2=(source[i]>>21)&0x1f;
7348 switch(op2)
7349 {
7350 case 0x00: strcpy(insn[i],"MFC0"); type=COP0; break;
00fa9369 7351 case 0x02: strcpy(insn[i],"CFC0"); type=COP0; break;
57871462 7352 case 0x04: strcpy(insn[i],"MTC0"); type=COP0; break;
00fa9369 7353 case 0x06: strcpy(insn[i],"CTC0"); type=COP0; break;
7354 case 0x10: strcpy(insn[i],"RFE"); type=COP0; break;
57871462 7355 }
7356 break;
00fa9369 7357 case 0x11: strcpy(insn[i],"cop1"); type=COP1;
57871462 7358 op2=(source[i]>>21)&0x1f;
57871462 7359 break;
71e490c5 7360#if 0
57871462 7361 case 0x14: strcpy(insn[i],"BEQL"); type=CJUMP; break;
7362 case 0x15: strcpy(insn[i],"BNEL"); type=CJUMP; break;
7363 case 0x16: strcpy(insn[i],"BLEZL"); type=CJUMP; break;
7364 case 0x17: strcpy(insn[i],"BGTZL"); type=CJUMP; break;
7365 case 0x18: strcpy(insn[i],"DADDI"); type=IMM16; break;
7366 case 0x19: strcpy(insn[i],"DADDIU"); type=IMM16; break;
7367 case 0x1A: strcpy(insn[i],"LDL"); type=LOADLR; break;
7368 case 0x1B: strcpy(insn[i],"LDR"); type=LOADLR; break;
996cc15d 7369#endif
57871462 7370 case 0x20: strcpy(insn[i],"LB"); type=LOAD; break;
7371 case 0x21: strcpy(insn[i],"LH"); type=LOAD; break;
7372 case 0x22: strcpy(insn[i],"LWL"); type=LOADLR; break;
7373 case 0x23: strcpy(insn[i],"LW"); type=LOAD; break;
7374 case 0x24: strcpy(insn[i],"LBU"); type=LOAD; break;
7375 case 0x25: strcpy(insn[i],"LHU"); type=LOAD; break;
7376 case 0x26: strcpy(insn[i],"LWR"); type=LOADLR; break;
71e490c5 7377#if 0
57871462 7378 case 0x27: strcpy(insn[i],"LWU"); type=LOAD; break;
64bd6f82 7379#endif
57871462 7380 case 0x28: strcpy(insn[i],"SB"); type=STORE; break;
7381 case 0x29: strcpy(insn[i],"SH"); type=STORE; break;
7382 case 0x2A: strcpy(insn[i],"SWL"); type=STORELR; break;
7383 case 0x2B: strcpy(insn[i],"SW"); type=STORE; break;
71e490c5 7384#if 0
57871462 7385 case 0x2C: strcpy(insn[i],"SDL"); type=STORELR; break;
7386 case 0x2D: strcpy(insn[i],"SDR"); type=STORELR; break;
996cc15d 7387#endif
57871462 7388 case 0x2E: strcpy(insn[i],"SWR"); type=STORELR; break;
7389 case 0x2F: strcpy(insn[i],"CACHE"); type=NOP; break;
7390 case 0x30: strcpy(insn[i],"LL"); type=NI; break;
7391 case 0x31: strcpy(insn[i],"LWC1"); type=C1LS; break;
71e490c5 7392#if 0
57871462 7393 case 0x34: strcpy(insn[i],"LLD"); type=NI; break;
7394 case 0x35: strcpy(insn[i],"LDC1"); type=C1LS; break;
7395 case 0x37: strcpy(insn[i],"LD"); type=LOAD; break;
996cc15d 7396#endif
57871462 7397 case 0x38: strcpy(insn[i],"SC"); type=NI; break;
7398 case 0x39: strcpy(insn[i],"SWC1"); type=C1LS; break;
71e490c5 7399#if 0
57871462 7400 case 0x3C: strcpy(insn[i],"SCD"); type=NI; break;
7401 case 0x3D: strcpy(insn[i],"SDC1"); type=C1LS; break;
7402 case 0x3F: strcpy(insn[i],"SD"); type=STORE; break;
996cc15d 7403#endif
b9b61529 7404 case 0x12: strcpy(insn[i],"COP2"); type=NI;
7405 op2=(source[i]>>21)&0x1f;
be516ebe 7406 //if (op2 & 0x10)
bedfea38 7407 if (source[i]&0x3f) { // use this hack to support old savestates with patched gte insns
c7abc864 7408 if (gte_handlers[source[i]&0x3f]!=NULL) {
bedfea38 7409 if (gte_regnames[source[i]&0x3f]!=NULL)
7410 strcpy(insn[i],gte_regnames[source[i]&0x3f]);
7411 else
7412 snprintf(insn[i], sizeof(insn[i]), "COP2 %x", source[i]&0x3f);
c7abc864 7413 type=C2OP;
7414 }
7415 }
7416 else switch(op2)
b9b61529 7417 {
7418 case 0x00: strcpy(insn[i],"MFC2"); type=COP2; break;
7419 case 0x02: strcpy(insn[i],"CFC2"); type=COP2; break;
7420 case 0x04: strcpy(insn[i],"MTC2"); type=COP2; break;
7421 case 0x06: strcpy(insn[i],"CTC2"); type=COP2; break;
b9b61529 7422 }
7423 break;
7424 case 0x32: strcpy(insn[i],"LWC2"); type=C2LS; break;
7425 case 0x3A: strcpy(insn[i],"SWC2"); type=C2LS; break;
7426 case 0x3B: strcpy(insn[i],"HLECALL"); type=HLECALL; break;
90ae6d4e 7427 default: strcpy(insn[i],"???"); type=NI;
c43b5311 7428 SysPrintf("NI %08x @%08x (%08x)\n", source[i], addr + i*4, addr);
90ae6d4e 7429 break;
57871462 7430 }
cf95b4f0 7431 dops[i].itype=type;
7432 dops[i].opcode2=op2;
57871462 7433 /* Get registers/immediates */
cf95b4f0 7434 dops[i].lt1=0;
bedfea38 7435 gte_rs[i]=gte_rt[i]=0;
57871462 7436 switch(type) {
7437 case LOAD:
cf95b4f0 7438 dops[i].rs1=(source[i]>>21)&0x1f;
7439 dops[i].rs2=0;
7440 dops[i].rt1=(source[i]>>16)&0x1f;
7441 dops[i].rt2=0;
57871462 7442 imm[i]=(short)source[i];
7443 break;
7444 case STORE:
7445 case STORELR:
cf95b4f0 7446 dops[i].rs1=(source[i]>>21)&0x1f;
7447 dops[i].rs2=(source[i]>>16)&0x1f;
7448 dops[i].rt1=0;
7449 dops[i].rt2=0;
57871462 7450 imm[i]=(short)source[i];
57871462 7451 break;
7452 case LOADLR:
7453 // LWL/LWR only load part of the register,
7454 // therefore the target register must be treated as a source too
cf95b4f0 7455 dops[i].rs1=(source[i]>>21)&0x1f;
7456 dops[i].rs2=(source[i]>>16)&0x1f;
7457 dops[i].rt1=(source[i]>>16)&0x1f;
7458 dops[i].rt2=0;
57871462 7459 imm[i]=(short)source[i];
57871462 7460 break;
7461 case IMM16:
cf95b4f0 7462 if (op==0x0f) dops[i].rs1=0; // LUI instruction has no source register
7463 else dops[i].rs1=(source[i]>>21)&0x1f;
7464 dops[i].rs2=0;
7465 dops[i].rt1=(source[i]>>16)&0x1f;
7466 dops[i].rt2=0;
57871462 7467 if(op>=0x0c&&op<=0x0e) { // ANDI/ORI/XORI
7468 imm[i]=(unsigned short)source[i];
7469 }else{
7470 imm[i]=(short)source[i];
7471 }
57871462 7472 break;
7473 case UJUMP:
cf95b4f0 7474 dops[i].rs1=0;
7475 dops[i].rs2=0;
7476 dops[i].rt1=0;
7477 dops[i].rt2=0;
57871462 7478 // The JAL instruction writes to r31.
7479 if (op&1) {
cf95b4f0 7480 dops[i].rt1=31;
57871462 7481 }
cf95b4f0 7482 dops[i].rs2=CCREG;
57871462 7483 break;
7484 case RJUMP:
cf95b4f0 7485 dops[i].rs1=(source[i]>>21)&0x1f;
7486 dops[i].rs2=0;
7487 dops[i].rt1=0;
7488 dops[i].rt2=0;
5067f341 7489 // The JALR instruction writes to rd.
57871462 7490 if (op2&1) {
cf95b4f0 7491 dops[i].rt1=(source[i]>>11)&0x1f;
57871462 7492 }
cf95b4f0 7493 dops[i].rs2=CCREG;
57871462 7494 break;
7495 case CJUMP:
cf95b4f0 7496 dops[i].rs1=(source[i]>>21)&0x1f;
7497 dops[i].rs2=(source[i]>>16)&0x1f;
7498 dops[i].rt1=0;
7499 dops[i].rt2=0;
57871462 7500 if(op&2) { // BGTZ/BLEZ
cf95b4f0 7501 dops[i].rs2=0;
57871462 7502 }
57871462 7503 break;
7504 case SJUMP:
cf95b4f0 7505 dops[i].rs1=(source[i]>>21)&0x1f;
7506 dops[i].rs2=CCREG;
7507 dops[i].rt1=0;
7508 dops[i].rt2=0;
57871462 7509 if(op2&0x10) { // BxxAL
cf95b4f0 7510 dops[i].rt1=31;
57871462 7511 // NOTE: If the branch is not taken, r31 is still overwritten
7512 }
57871462 7513 break;
57871462 7514 case ALU:
cf95b4f0 7515 dops[i].rs1=(source[i]>>21)&0x1f; // source
7516 dops[i].rs2=(source[i]>>16)&0x1f; // subtract amount
7517 dops[i].rt1=(source[i]>>11)&0x1f; // destination
7518 dops[i].rt2=0;
57871462 7519 break;
7520 case MULTDIV:
cf95b4f0 7521 dops[i].rs1=(source[i]>>21)&0x1f; // source
7522 dops[i].rs2=(source[i]>>16)&0x1f; // divisor
7523 dops[i].rt1=HIREG;
7524 dops[i].rt2=LOREG;
57871462 7525 break;
7526 case MOV:
cf95b4f0 7527 dops[i].rs1=0;
7528 dops[i].rs2=0;
7529 dops[i].rt1=0;
7530 dops[i].rt2=0;
7531 if(op2==0x10) dops[i].rs1=HIREG; // MFHI
7532 if(op2==0x11) dops[i].rt1=HIREG; // MTHI
7533 if(op2==0x12) dops[i].rs1=LOREG; // MFLO
7534 if(op2==0x13) dops[i].rt1=LOREG; // MTLO
7535 if((op2&0x1d)==0x10) dops[i].rt1=(source[i]>>11)&0x1f; // MFxx
7536 if((op2&0x1d)==0x11) dops[i].rs1=(source[i]>>21)&0x1f; // MTxx
57871462 7537 break;
7538 case SHIFT:
cf95b4f0 7539 dops[i].rs1=(source[i]>>16)&0x1f; // target of shift
7540 dops[i].rs2=(source[i]>>21)&0x1f; // shift amount
7541 dops[i].rt1=(source[i]>>11)&0x1f; // destination
7542 dops[i].rt2=0;
57871462 7543 break;
7544 case SHIFTIMM:
cf95b4f0 7545 dops[i].rs1=(source[i]>>16)&0x1f;
7546 dops[i].rs2=0;
7547 dops[i].rt1=(source[i]>>11)&0x1f;
7548 dops[i].rt2=0;
57871462 7549 imm[i]=(source[i]>>6)&0x1f;
7550 // DSxx32 instructions
7551 if(op2>=0x3c) imm[i]|=0x20;
57871462 7552 break;
7553 case COP0:
cf95b4f0 7554 dops[i].rs1=0;
7555 dops[i].rs2=0;
7556 dops[i].rt1=0;
7557 dops[i].rt2=0;
7558 if(op2==0||op2==2) dops[i].rt1=(source[i]>>16)&0x1F; // MFC0/CFC0
7559 if(op2==4||op2==6) dops[i].rs1=(source[i]>>16)&0x1F; // MTC0/CTC0
7560 if(op2==4&&((source[i]>>11)&0x1f)==12) dops[i].rt2=CSREG; // Status
7561 if(op2==16) if((source[i]&0x3f)==0x18) dops[i].rs2=CCREG; // ERET
57871462 7562 break;
7563 case COP1:
cf95b4f0 7564 dops[i].rs1=0;
7565 dops[i].rs2=0;
7566 dops[i].rt1=0;
7567 dops[i].rt2=0;
7568 if(op2<3) dops[i].rt1=(source[i]>>16)&0x1F; // MFC1/DMFC1/CFC1
7569 if(op2>3) dops[i].rs1=(source[i]>>16)&0x1F; // MTC1/DMTC1/CTC1
7570 dops[i].rs2=CSREG;
57871462 7571 break;
bedfea38 7572 case COP2:
cf95b4f0 7573 dops[i].rs1=0;
7574 dops[i].rs2=0;
7575 dops[i].rt1=0;
7576 dops[i].rt2=0;
7577 if(op2<3) dops[i].rt1=(source[i]>>16)&0x1F; // MFC2/CFC2
7578 if(op2>3) dops[i].rs1=(source[i]>>16)&0x1F; // MTC2/CTC2
7579 dops[i].rs2=CSREG;
bedfea38 7580 int gr=(source[i]>>11)&0x1F;
7581 switch(op2)
7582 {
7583 case 0x00: gte_rs[i]=1ll<<gr; break; // MFC2
7584 case 0x04: gte_rt[i]=1ll<<gr; break; // MTC2
0ff8c62c 7585 case 0x02: gte_rs[i]=1ll<<(gr+32); break; // CFC2
bedfea38 7586 case 0x06: gte_rt[i]=1ll<<(gr+32); break; // CTC2
7587 }
7588 break;
57871462 7589 case C1LS:
cf95b4f0 7590 dops[i].rs1=(source[i]>>21)&0x1F;
7591 dops[i].rs2=CSREG;
7592 dops[i].rt1=0;
7593 dops[i].rt2=0;
57871462 7594 imm[i]=(short)source[i];
7595 break;
b9b61529 7596 case C2LS:
cf95b4f0 7597 dops[i].rs1=(source[i]>>21)&0x1F;
7598 dops[i].rs2=0;
7599 dops[i].rt1=0;
7600 dops[i].rt2=0;
b9b61529 7601 imm[i]=(short)source[i];
bedfea38 7602 if(op==0x32) gte_rt[i]=1ll<<((source[i]>>16)&0x1F); // LWC2
7603 else gte_rs[i]=1ll<<((source[i]>>16)&0x1F); // SWC2
7604 break;
7605 case C2OP:
cf95b4f0 7606 dops[i].rs1=0;
7607 dops[i].rs2=0;
7608 dops[i].rt1=0;
7609 dops[i].rt2=0;
2167bef6 7610 gte_rs[i]=gte_reg_reads[source[i]&0x3f];
7611 gte_rt[i]=gte_reg_writes[source[i]&0x3f];
7612 gte_rt[i]|=1ll<<63; // every op changes flags
587a5b1c 7613 if((source[i]&0x3f)==GTE_MVMVA) {
7614 int v = (source[i] >> 15) & 3;
7615 gte_rs[i]&=~0xe3fll;
7616 if(v==3) gte_rs[i]|=0xe00ll;
7617 else gte_rs[i]|=3ll<<(v*2);
7618 }
b9b61529 7619 break;
57871462 7620 case SYSCALL:
7139f3c8 7621 case HLECALL:
1e973cb0 7622 case INTCALL:
cf95b4f0 7623 dops[i].rs1=CCREG;
7624 dops[i].rs2=0;
7625 dops[i].rt1=0;
7626 dops[i].rt2=0;
57871462 7627 break;
7628 default:
cf95b4f0 7629 dops[i].rs1=0;
7630 dops[i].rs2=0;
7631 dops[i].rt1=0;
7632 dops[i].rt2=0;
57871462 7633 }
7634 /* Calculate branch target addresses */
7635 if(type==UJUMP)
7636 ba[i]=((start+i*4+4)&0xF0000000)|(((unsigned int)source[i]<<6)>>4);
cf95b4f0 7637 else if(type==CJUMP&&dops[i].rs1==dops[i].rs2&&(op&1))
57871462 7638 ba[i]=start+i*4+8; // Ignore never taken branch
cf95b4f0 7639 else if(type==SJUMP&&dops[i].rs1==0&&!(op2&1))
57871462 7640 ba[i]=start+i*4+8; // Ignore never taken branch
ad49de89 7641 else if(type==CJUMP||type==SJUMP)
57871462 7642 ba[i]=start+i*4+4+((signed int)((unsigned int)source[i]<<16)>>14);
7643 else ba[i]=-1;
4919de1e 7644
7645 /* simplify always (not)taken branches */
cf95b4f0 7646 if (type == CJUMP && dops[i].rs1 == dops[i].rs2) {
7647 dops[i].rs1 = dops[i].rs2 = 0;
4919de1e 7648 if (!(op & 1)) {
cf95b4f0 7649 dops[i].itype = type = UJUMP;
7650 dops[i].rs2 = CCREG;
4919de1e 7651 }
7652 }
cf95b4f0 7653 else if (type == SJUMP && dops[i].rs1 == 0 && (op2 & 1))
7654 dops[i].itype = type = UJUMP;
4919de1e 7655
fe807a8a 7656 dops[i].is_jump = (dops[i].itype == RJUMP || dops[i].itype == UJUMP || dops[i].itype == CJUMP || dops[i].itype == SJUMP);
7657 dops[i].is_ujump = (dops[i].itype == RJUMP || dops[i].itype == UJUMP); // || (source[i] >> 16) == 0x1000 // beq r0,r0
37387d8b 7658 dops[i].is_load = (dops[i].itype == LOAD || dops[i].itype == LOADLR || op == 0x32); // LWC2
7659 dops[i].is_store = (dops[i].itype == STORE || dops[i].itype == STORELR || op == 0x3a); // SWC2
fe807a8a 7660
4919de1e 7661 /* messy cases to just pass over to the interpreter */
fe807a8a 7662 if (i > 0 && dops[i-1].is_jump) {
3e535354 7663 int do_in_intrp=0;
7664 // branch in delay slot?
fe807a8a 7665 if (dops[i].is_jump) {
3e535354 7666 // don't handle first branch and call interpreter if it's hit
c43b5311 7667 SysPrintf("branch in delay slot @%08x (%08x)\n", addr + i*4, addr);
3e535354 7668 do_in_intrp=1;
7669 }
7670 // basic load delay detection
cf95b4f0 7671 else if((type==LOAD||type==LOADLR||type==COP0||type==COP2||type==C2LS)&&dops[i].rt1!=0) {
3e535354 7672 int t=(ba[i-1]-start)/4;
cf95b4f0 7673 if(0 <= t && t < i &&(dops[i].rt1==dops[t].rs1||dops[i].rt1==dops[t].rs2)&&dops[t].itype!=CJUMP&&dops[t].itype!=SJUMP) {
3e535354 7674 // jump target wants DS result - potential load delay effect
c43b5311 7675 SysPrintf("load delay @%08x (%08x)\n", addr + i*4, addr);
3e535354 7676 do_in_intrp=1;
cf95b4f0 7677 dops[t+1].bt=1; // expected return from interpreter
3e535354 7678 }
cf95b4f0 7679 else if(i>=2&&dops[i-2].rt1==2&&dops[i].rt1==2&&dops[i].rs1!=2&&dops[i].rs2!=2&&dops[i-1].rs1!=2&&dops[i-1].rs2!=2&&
fe807a8a 7680 !(i>=3&&dops[i-3].is_jump)) {
3e535354 7681 // v0 overwrite like this is a sign of trouble, bail out
c43b5311 7682 SysPrintf("v0 overwrite @%08x (%08x)\n", addr + i*4, addr);
3e535354 7683 do_in_intrp=1;
7684 }
7685 }
7ebfcedf 7686 if (do_in_intrp) {
7687 memset(&dops[i-1], 0, sizeof(dops[i-1]));
7688 dops[i-1].itype = INTCALL;
7689 dops[i-1].rs1 = CCREG;
7690 ba[i-1] = -1;
7691 done = 2;
3e535354 7692 i--; // don't compile the DS
26869094 7693 }
3e535354 7694 }
4919de1e 7695
3e535354 7696 /* Is this the end of the block? */
fe807a8a 7697 if (i > 0 && dops[i-1].is_ujump) {
cf95b4f0 7698 if(dops[i-1].rt1==0) { // Continue past subroutine call (JAL)
1e973cb0 7699 done=2;
57871462 7700 }
7701 else {
7702 if(stop_after_jal) done=1;
7703 // Stop on BREAK
7704 if((source[i+1]&0xfc00003f)==0x0d) done=1;
7705 }
7706 // Don't recompile stuff that's already compiled
7707 if(check_addr(start+i*4+4)) done=1;
7708 // Don't get too close to the limit
7709 if(i>MAXBLOCK/2) done=1;
7710 }
d1150cd6 7711 if (dops[i].itype == SYSCALL || dops[i].itype == HLECALL || dops[i].itype == INTCALL)
7712 done = stop_after_jal ? 1 : 2;
7713 if (done == 2) {
1e973cb0 7714 // Does the block continue due to a branch?
7715 for(j=i-1;j>=0;j--)
7716 {
2a706964 7717 if(ba[j]==start+i*4) done=j=0; // Branch into delay slot
1e973cb0 7718 if(ba[j]==start+i*4+4) done=j=0;
7719 if(ba[j]==start+i*4+8) done=j=0;
7720 }
7721 }
75dec299 7722 //assert(i<MAXBLOCK-1);
57871462 7723 if(start+i*4==pagelimit-4) done=1;
7724 assert(start+i*4<pagelimit);
7725 if (i==MAXBLOCK-1) done=1;
7726 // Stop if we're compiling junk
cf95b4f0 7727 if(dops[i].itype==NI&&dops[i].opcode==0x11) {
57871462 7728 done=stop_after_jal=1;
c43b5311 7729 SysPrintf("Disabled speculative precompilation\n");
57871462 7730 }
7731 }
7732 slen=i;
fe807a8a 7733 if (dops[i-1].is_jump) {
57871462 7734 if(start+i*4==pagelimit) {
cf95b4f0 7735 dops[i-1].itype=SPAN;
57871462 7736 }
7737 }
7738 assert(slen>0);
7739
7f94b097 7740 int clear_hack_addr = apply_hacks();
39b71d9a 7741
57871462 7742 /* Pass 2 - Register dependencies and branch targets */
7743
7744 unneeded_registers(0,slen-1,0);
9f51b4b9 7745
57871462 7746 /* Pass 3 - Register allocation */
7747
7748 struct regstat current; // Current register allocations/status
6cc8d23c 7749 clear_all_regs(current.regmap_entry);
57871462 7750 clear_all_regs(current.regmap);
6cc8d23c 7751 current.wasdirty = current.dirty = 0;
7752 current.u = unneeded_reg[0];
7753 alloc_reg(&current, 0, CCREG);
7754 dirty_reg(&current, CCREG);
7755 current.wasconst = 0;
7756 current.isconst = 0;
7757 current.loadedconst = 0;
7758 current.waswritten = 0;
57871462 7759 int ds=0;
7760 int cc=0;
5194fb95 7761 int hr=-1;
6ebf4adf 7762
57871462 7763 if((u_int)addr&1) {
7764 // First instruction is delay slot
7765 cc=-1;
cf95b4f0 7766 dops[1].bt=1;
57871462 7767 ds=1;
7768 unneeded_reg[0]=1;
57871462 7769 current.regmap[HOST_BTREG]=BTREG;
7770 }
9f51b4b9 7771
57871462 7772 for(i=0;i<slen;i++)
7773 {
cf95b4f0 7774 if(dops[i].bt)
57871462 7775 {
7776 int hr;
7777 for(hr=0;hr<HOST_REGS;hr++)
7778 {
7779 // Is this really necessary?
7780 if(current.regmap[hr]==0) current.regmap[hr]=-1;
7781 }
7782 current.isconst=0;
27727b63 7783 current.waswritten=0;
57871462 7784 }
24385cae 7785
57871462 7786 memcpy(regmap_pre[i],current.regmap,sizeof(current.regmap));
7787 regs[i].wasconst=current.isconst;
57871462 7788 regs[i].wasdirty=current.dirty;
6cc8d23c 7789 regs[i].dirty=0;
7790 regs[i].u=0;
7791 regs[i].isconst=0;
8575a877 7792 regs[i].loadedconst=0;
fe807a8a 7793 if (!dops[i].is_jump) {
57871462 7794 if(i+1<slen) {
cf95b4f0 7795 current.u=unneeded_reg[i+1]&~((1LL<<dops[i].rs1)|(1LL<<dops[i].rs2));
57871462 7796 current.u|=1;
57871462 7797 } else {
7798 current.u=1;
57871462 7799 }
7800 } else {
7801 if(i+1<slen) {
cf95b4f0 7802 current.u=branch_unneeded_reg[i]&~((1LL<<dops[i+1].rs1)|(1LL<<dops[i+1].rs2));
7803 current.u&=~((1LL<<dops[i].rs1)|(1LL<<dops[i].rs2));
57871462 7804 current.u|=1;
7ebfcedf 7805 } else {
7806 SysPrintf("oops, branch at end of block with no delay slot @%08x\n", start + i*4);
7807 abort();
7808 }
57871462 7809 }
cf95b4f0 7810 dops[i].is_ds=ds;
57871462 7811 if(ds) {
7812 ds=0; // Skip delay slot, already allocated as part of branch
7813 // ...but we need to alloc it in case something jumps here
7814 if(i+1<slen) {
7815 current.u=branch_unneeded_reg[i-1]&unneeded_reg[i+1];
57871462 7816 }else{
7817 current.u=branch_unneeded_reg[i-1];
57871462 7818 }
cf95b4f0 7819 current.u&=~((1LL<<dops[i].rs1)|(1LL<<dops[i].rs2));
57871462 7820 current.u|=1;
57871462 7821 struct regstat temp;
7822 memcpy(&temp,&current,sizeof(current));
7823 temp.wasdirty=temp.dirty;
57871462 7824 // TODO: Take into account unconditional branches, as below
7825 delayslot_alloc(&temp,i);
7826 memcpy(regs[i].regmap,temp.regmap,sizeof(temp.regmap));
7827 regs[i].wasdirty=temp.wasdirty;
57871462 7828 regs[i].dirty=temp.dirty;
57871462 7829 regs[i].isconst=0;
7830 regs[i].wasconst=0;
7831 current.isconst=0;
7832 // Create entry (branch target) regmap
7833 for(hr=0;hr<HOST_REGS;hr++)
7834 {
7835 int r=temp.regmap[hr];
7836 if(r>=0) {
7837 if(r!=regmap_pre[i][hr]) {
7838 regs[i].regmap_entry[hr]=-1;
7839 }
7840 else
7841 {
7c3a5182 7842 assert(r < 64);
57871462 7843 if((current.u>>r)&1) {
7844 regs[i].regmap_entry[hr]=-1;
7845 regs[i].regmap[hr]=-1;
7846 //Don't clear regs in the delay slot as the branch might need them
7847 //current.regmap[hr]=-1;
7848 }else
7849 regs[i].regmap_entry[hr]=r;
57871462 7850 }
7851 } else {
7852 // First instruction expects CCREG to be allocated
9f51b4b9 7853 if(i==0&&hr==HOST_CCREG)
57871462 7854 regs[i].regmap_entry[hr]=CCREG;
7855 else
7856 regs[i].regmap_entry[hr]=-1;
7857 }
7858 }
7859 }
7860 else { // Not delay slot
cf95b4f0 7861 switch(dops[i].itype) {
57871462 7862 case UJUMP:
7863 //current.isconst=0; // DEBUG
7864 //current.wasconst=0; // DEBUG
7865 //regs[i].wasconst=0; // DEBUG
cf95b4f0 7866 clear_const(&current,dops[i].rt1);
57871462 7867 alloc_cc(&current,i);
7868 dirty_reg(&current,CCREG);
cf95b4f0 7869 if (dops[i].rt1==31) {
57871462 7870 alloc_reg(&current,i,31);
7871 dirty_reg(&current,31);
cf95b4f0 7872 //assert(dops[i+1].rs1!=31&&dops[i+1].rs2!=31);
7873 //assert(dops[i+1].rt1!=dops[i].rt1);
57871462 7874 #ifdef REG_PREFETCH
7875 alloc_reg(&current,i,PTEMP);
7876 #endif
57871462 7877 }
cf95b4f0 7878 dops[i].ooo=1;
269bb29a 7879 delayslot_alloc(&current,i+1);
57871462 7880 //current.isconst=0; // DEBUG
7881 ds=1;
7882 //printf("i=%d, isconst=%x\n",i,current.isconst);
7883 break;
7884 case RJUMP:
7885 //current.isconst=0;
7886 //current.wasconst=0;
7887 //regs[i].wasconst=0;
cf95b4f0 7888 clear_const(&current,dops[i].rs1);
7889 clear_const(&current,dops[i].rt1);
57871462 7890 alloc_cc(&current,i);
7891 dirty_reg(&current,CCREG);
4919de1e 7892 if (!ds_writes_rjump_rs(i)) {
cf95b4f0 7893 alloc_reg(&current,i,dops[i].rs1);
7894 if (dops[i].rt1!=0) {
7895 alloc_reg(&current,i,dops[i].rt1);
7896 dirty_reg(&current,dops[i].rt1);
7897 assert(dops[i+1].rs1!=dops[i].rt1&&dops[i+1].rs2!=dops[i].rt1);
7898 assert(dops[i+1].rt1!=dops[i].rt1);
57871462 7899 #ifdef REG_PREFETCH
7900 alloc_reg(&current,i,PTEMP);
7901 #endif
7902 }
7903 #ifdef USE_MINI_HT
cf95b4f0 7904 if(dops[i].rs1==31) { // JALR
57871462 7905 alloc_reg(&current,i,RHASH);
57871462 7906 alloc_reg(&current,i,RHTBL);
57871462 7907 }
7908 #endif
7909 delayslot_alloc(&current,i+1);
7910 } else {
7911 // The delay slot overwrites our source register,
7912 // allocate a temporary register to hold the old value.
7913 current.isconst=0;
7914 current.wasconst=0;
7915 regs[i].wasconst=0;
7916 delayslot_alloc(&current,i+1);
7917 current.isconst=0;
7918 alloc_reg(&current,i,RTEMP);
7919 }
7920 //current.isconst=0; // DEBUG
cf95b4f0 7921 dops[i].ooo=1;
57871462 7922 ds=1;
7923 break;
7924 case CJUMP:
7925 //current.isconst=0;
7926 //current.wasconst=0;
7927 //regs[i].wasconst=0;
cf95b4f0 7928 clear_const(&current,dops[i].rs1);
7929 clear_const(&current,dops[i].rs2);
7930 if((dops[i].opcode&0x3E)==4) // BEQ/BNE
57871462 7931 {
7932 alloc_cc(&current,i);
7933 dirty_reg(&current,CCREG);
cf95b4f0 7934 if(dops[i].rs1) alloc_reg(&current,i,dops[i].rs1);
7935 if(dops[i].rs2) alloc_reg(&current,i,dops[i].rs2);
7936 if((dops[i].rs1&&(dops[i].rs1==dops[i+1].rt1||dops[i].rs1==dops[i+1].rt2))||
7937 (dops[i].rs2&&(dops[i].rs2==dops[i+1].rt1||dops[i].rs2==dops[i+1].rt2))) {
57871462 7938 // The delay slot overwrites one of our conditions.
7939 // Allocate the branch condition registers instead.
57871462 7940 current.isconst=0;
7941 current.wasconst=0;
7942 regs[i].wasconst=0;
cf95b4f0 7943 if(dops[i].rs1) alloc_reg(&current,i,dops[i].rs1);
7944 if(dops[i].rs2) alloc_reg(&current,i,dops[i].rs2);
57871462 7945 }
e1190b87 7946 else
7947 {
cf95b4f0 7948 dops[i].ooo=1;
e1190b87 7949 delayslot_alloc(&current,i+1);
7950 }
57871462 7951 }
7952 else
cf95b4f0 7953 if((dops[i].opcode&0x3E)==6) // BLEZ/BGTZ
57871462 7954 {
7955 alloc_cc(&current,i);
7956 dirty_reg(&current,CCREG);
cf95b4f0 7957 alloc_reg(&current,i,dops[i].rs1);
7958 if(dops[i].rs1&&(dops[i].rs1==dops[i+1].rt1||dops[i].rs1==dops[i+1].rt2)) {
57871462 7959 // The delay slot overwrites one of our conditions.
7960 // Allocate the branch condition registers instead.
57871462 7961 current.isconst=0;
7962 current.wasconst=0;
7963 regs[i].wasconst=0;
cf95b4f0 7964 if(dops[i].rs1) alloc_reg(&current,i,dops[i].rs1);
57871462 7965 }
e1190b87 7966 else
7967 {
cf95b4f0 7968 dops[i].ooo=1;
e1190b87 7969 delayslot_alloc(&current,i+1);
7970 }
57871462 7971 }
7972 else
7973 // Don't alloc the delay slot yet because we might not execute it
cf95b4f0 7974 if((dops[i].opcode&0x3E)==0x14) // BEQL/BNEL
57871462 7975 {
7976 current.isconst=0;
7977 current.wasconst=0;
7978 regs[i].wasconst=0;
7979 alloc_cc(&current,i);
7980 dirty_reg(&current,CCREG);
cf95b4f0 7981 alloc_reg(&current,i,dops[i].rs1);
7982 alloc_reg(&current,i,dops[i].rs2);
57871462 7983 }
7984 else
cf95b4f0 7985 if((dops[i].opcode&0x3E)==0x16) // BLEZL/BGTZL
57871462 7986 {
7987 current.isconst=0;
7988 current.wasconst=0;
7989 regs[i].wasconst=0;
7990 alloc_cc(&current,i);
7991 dirty_reg(&current,CCREG);
cf95b4f0 7992 alloc_reg(&current,i,dops[i].rs1);
57871462 7993 }
7994 ds=1;
7995 //current.isconst=0;
7996 break;
7997 case SJUMP:
7998 //current.isconst=0;
7999 //current.wasconst=0;
8000 //regs[i].wasconst=0;
cf95b4f0 8001 clear_const(&current,dops[i].rs1);
8002 clear_const(&current,dops[i].rt1);
8003 //if((dops[i].opcode2&0x1E)==0x0) // BLTZ/BGEZ
8004 if((dops[i].opcode2&0x0E)==0x0) // BLTZ/BGEZ
57871462 8005 {
8006 alloc_cc(&current,i);
8007 dirty_reg(&current,CCREG);
cf95b4f0 8008 alloc_reg(&current,i,dops[i].rs1);
8009 if (dops[i].rt1==31) { // BLTZAL/BGEZAL
57871462 8010 alloc_reg(&current,i,31);
8011 dirty_reg(&current,31);
57871462 8012 //#ifdef REG_PREFETCH
8013 //alloc_reg(&current,i,PTEMP);
8014 //#endif
57871462 8015 }
cf95b4f0 8016 if((dops[i].rs1&&(dops[i].rs1==dops[i+1].rt1||dops[i].rs1==dops[i+1].rt2)) // The delay slot overwrites the branch condition.
8017 ||(dops[i].rt1==31&&(dops[i+1].rs1==31||dops[i+1].rs2==31||dops[i+1].rt1==31||dops[i+1].rt2==31))) { // DS touches $ra
57871462 8018 // Allocate the branch condition registers instead.
57871462 8019 current.isconst=0;
8020 current.wasconst=0;
8021 regs[i].wasconst=0;
cf95b4f0 8022 if(dops[i].rs1) alloc_reg(&current,i,dops[i].rs1);
57871462 8023 }
e1190b87 8024 else
8025 {
cf95b4f0 8026 dops[i].ooo=1;
e1190b87 8027 delayslot_alloc(&current,i+1);
8028 }
57871462 8029 }
8030 else
8031 // Don't alloc the delay slot yet because we might not execute it
cf95b4f0 8032 if((dops[i].opcode2&0x1E)==0x2) // BLTZL/BGEZL
57871462 8033 {
8034 current.isconst=0;
8035 current.wasconst=0;
8036 regs[i].wasconst=0;
8037 alloc_cc(&current,i);
8038 dirty_reg(&current,CCREG);
cf95b4f0 8039 alloc_reg(&current,i,dops[i].rs1);
57871462 8040 }
8041 ds=1;
8042 //current.isconst=0;
8043 break;
57871462 8044 case IMM16:
8045 imm16_alloc(&current,i);
8046 break;
8047 case LOAD:
8048 case LOADLR:
8049 load_alloc(&current,i);
8050 break;
8051 case STORE:
8052 case STORELR:
8053 store_alloc(&current,i);
8054 break;
8055 case ALU:
8056 alu_alloc(&current,i);
8057 break;
8058 case SHIFT:
8059 shift_alloc(&current,i);
8060 break;
8061 case MULTDIV:
8062 multdiv_alloc(&current,i);
8063 break;
8064 case SHIFTIMM:
8065 shiftimm_alloc(&current,i);
8066 break;
8067 case MOV:
8068 mov_alloc(&current,i);
8069 break;
8070 case COP0:
8071 cop0_alloc(&current,i);
8072 break;
8073 case COP1:
81dbbf4c 8074 break;
b9b61529 8075 case COP2:
81dbbf4c 8076 cop2_alloc(&current,i);
57871462 8077 break;
8078 case C1LS:
8079 c1ls_alloc(&current,i);
8080 break;
b9b61529 8081 case C2LS:
8082 c2ls_alloc(&current,i);
8083 break;
8084 case C2OP:
8085 c2op_alloc(&current,i);
8086 break;
57871462 8087 case SYSCALL:
7139f3c8 8088 case HLECALL:
1e973cb0 8089 case INTCALL:
57871462 8090 syscall_alloc(&current,i);
8091 break;
8092 case SPAN:
8093 pagespan_alloc(&current,i);
8094 break;
8095 }
9f51b4b9 8096
57871462 8097 // Create entry (branch target) regmap
8098 for(hr=0;hr<HOST_REGS;hr++)
8099 {
581335b0 8100 int r,or;
57871462 8101 r=current.regmap[hr];
8102 if(r>=0) {
8103 if(r!=regmap_pre[i][hr]) {
8104 // TODO: delay slot (?)
8105 or=get_reg(regmap_pre[i],r); // Get old mapping for this register
8106 if(or<0||(r&63)>=TEMPREG){
8107 regs[i].regmap_entry[hr]=-1;
8108 }
8109 else
8110 {
8111 // Just move it to a different register
8112 regs[i].regmap_entry[hr]=r;
8113 // If it was dirty before, it's still dirty
8114 if((regs[i].wasdirty>>or)&1) dirty_reg(&current,r&63);
8115 }
8116 }
8117 else
8118 {
8119 // Unneeded
8120 if(r==0){
8121 regs[i].regmap_entry[hr]=0;
8122 }
8123 else
7c3a5182 8124 {
8125 assert(r<64);
57871462 8126 if((current.u>>r)&1) {
8127 regs[i].regmap_entry[hr]=-1;
8128 //regs[i].regmap[hr]=-1;
8129 current.regmap[hr]=-1;
8130 }else
8131 regs[i].regmap_entry[hr]=r;
8132 }
57871462 8133 }
8134 } else {
8135 // Branches expect CCREG to be allocated at the target
9f51b4b9 8136 if(regmap_pre[i][hr]==CCREG)
57871462 8137 regs[i].regmap_entry[hr]=CCREG;
8138 else
8139 regs[i].regmap_entry[hr]=-1;
8140 }
8141 }
8142 memcpy(regs[i].regmap,current.regmap,sizeof(current.regmap));
8143 }
27727b63 8144
cf95b4f0 8145 if(i>0&&(dops[i-1].itype==STORE||dops[i-1].itype==STORELR||(dops[i-1].itype==C2LS&&dops[i-1].opcode==0x3a))&&(u_int)imm[i-1]<0x800)
8146 current.waswritten|=1<<dops[i-1].rs1;
8147 current.waswritten&=~(1<<dops[i].rt1);
8148 current.waswritten&=~(1<<dops[i].rt2);
8149 if((dops[i].itype==STORE||dops[i].itype==STORELR||(dops[i].itype==C2LS&&dops[i].opcode==0x3a))&&(u_int)imm[i]>=0x800)
8150 current.waswritten&=~(1<<dops[i].rs1);
27727b63 8151
57871462 8152 /* Branch post-alloc */
8153 if(i>0)
8154 {
57871462 8155 current.wasdirty=current.dirty;
cf95b4f0 8156 switch(dops[i-1].itype) {
57871462 8157 case UJUMP:
8158 memcpy(&branch_regs[i-1],&current,sizeof(current));
8159 branch_regs[i-1].isconst=0;
8160 branch_regs[i-1].wasconst=0;
cf95b4f0 8161 branch_regs[i-1].u=branch_unneeded_reg[i-1]&~((1LL<<dops[i-1].rs1)|(1LL<<dops[i-1].rs2));
57871462 8162 alloc_cc(&branch_regs[i-1],i-1);
8163 dirty_reg(&branch_regs[i-1],CCREG);
cf95b4f0 8164 if(dops[i-1].rt1==31) { // JAL
57871462 8165 alloc_reg(&branch_regs[i-1],i-1,31);
8166 dirty_reg(&branch_regs[i-1],31);
57871462 8167 }
8168 memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
40fca85b 8169 memcpy(constmap[i],constmap[i-1],sizeof(constmap[i]));
57871462 8170 break;
8171 case RJUMP:
8172 memcpy(&branch_regs[i-1],&current,sizeof(current));
8173 branch_regs[i-1].isconst=0;
8174 branch_regs[i-1].wasconst=0;
cf95b4f0 8175 branch_regs[i-1].u=branch_unneeded_reg[i-1]&~((1LL<<dops[i-1].rs1)|(1LL<<dops[i-1].rs2));
57871462 8176 alloc_cc(&branch_regs[i-1],i-1);
8177 dirty_reg(&branch_regs[i-1],CCREG);
cf95b4f0 8178 alloc_reg(&branch_regs[i-1],i-1,dops[i-1].rs1);
8179 if(dops[i-1].rt1!=0) { // JALR
8180 alloc_reg(&branch_regs[i-1],i-1,dops[i-1].rt1);
8181 dirty_reg(&branch_regs[i-1],dops[i-1].rt1);
57871462 8182 }
8183 #ifdef USE_MINI_HT
cf95b4f0 8184 if(dops[i-1].rs1==31) { // JALR
57871462 8185 alloc_reg(&branch_regs[i-1],i-1,RHASH);
57871462 8186 alloc_reg(&branch_regs[i-1],i-1,RHTBL);
57871462 8187 }
8188 #endif
8189 memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
40fca85b 8190 memcpy(constmap[i],constmap[i-1],sizeof(constmap[i]));
57871462 8191 break;
8192 case CJUMP:
cf95b4f0 8193 if((dops[i-1].opcode&0x3E)==4) // BEQ/BNE
57871462 8194 {
8195 alloc_cc(&current,i-1);
8196 dirty_reg(&current,CCREG);
cf95b4f0 8197 if((dops[i-1].rs1&&(dops[i-1].rs1==dops[i].rt1||dops[i-1].rs1==dops[i].rt2))||
8198 (dops[i-1].rs2&&(dops[i-1].rs2==dops[i].rt1||dops[i-1].rs2==dops[i].rt2))) {
57871462 8199 // The delay slot overwrote one of our conditions
8200 // Delay slot goes after the test (in order)
cf95b4f0 8201 current.u=branch_unneeded_reg[i-1]&~((1LL<<dops[i].rs1)|(1LL<<dops[i].rs2));
57871462 8202 current.u|=1;
57871462 8203 delayslot_alloc(&current,i);
8204 current.isconst=0;
8205 }
8206 else
8207 {
cf95b4f0 8208 current.u=branch_unneeded_reg[i-1]&~((1LL<<dops[i-1].rs1)|(1LL<<dops[i-1].rs2));
57871462 8209 // Alloc the branch condition registers
cf95b4f0 8210 if(dops[i-1].rs1) alloc_reg(&current,i-1,dops[i-1].rs1);
8211 if(dops[i-1].rs2) alloc_reg(&current,i-1,dops[i-1].rs2);
57871462 8212 }
8213 memcpy(&branch_regs[i-1],&current,sizeof(current));
8214 branch_regs[i-1].isconst=0;
8215 branch_regs[i-1].wasconst=0;
8216 memcpy(&branch_regs[i-1].regmap_entry,&current.regmap,sizeof(current.regmap));
40fca85b 8217 memcpy(constmap[i],constmap[i-1],sizeof(constmap[i]));
57871462 8218 }
8219 else
cf95b4f0 8220 if((dops[i-1].opcode&0x3E)==6) // BLEZ/BGTZ
57871462 8221 {
8222 alloc_cc(&current,i-1);
8223 dirty_reg(&current,CCREG);
cf95b4f0 8224 if(dops[i-1].rs1==dops[i].rt1||dops[i-1].rs1==dops[i].rt2) {
57871462 8225 // The delay slot overwrote the branch condition
8226 // Delay slot goes after the test (in order)
cf95b4f0 8227 current.u=branch_unneeded_reg[i-1]&~((1LL<<dops[i].rs1)|(1LL<<dops[i].rs2));
57871462 8228 current.u|=1;
57871462 8229 delayslot_alloc(&current,i);
8230 current.isconst=0;
8231 }
8232 else
8233 {
cf95b4f0 8234 current.u=branch_unneeded_reg[i-1]&~(1LL<<dops[i-1].rs1);
57871462 8235 // Alloc the branch condition register
cf95b4f0 8236 alloc_reg(&current,i-1,dops[i-1].rs1);
57871462 8237 }
8238 memcpy(&branch_regs[i-1],&current,sizeof(current));
8239 branch_regs[i-1].isconst=0;
8240 branch_regs[i-1].wasconst=0;
8241 memcpy(&branch_regs[i-1].regmap_entry,&current.regmap,sizeof(current.regmap));
40fca85b 8242 memcpy(constmap[i],constmap[i-1],sizeof(constmap[i]));
57871462 8243 }
8244 else
8245 // Alloc the delay slot in case the branch is taken
cf95b4f0 8246 if((dops[i-1].opcode&0x3E)==0x14) // BEQL/BNEL
57871462 8247 {
8248 memcpy(&branch_regs[i-1],&current,sizeof(current));
cf95b4f0 8249 branch_regs[i-1].u=(branch_unneeded_reg[i-1]&~((1LL<<dops[i].rs1)|(1LL<<dops[i].rs2)|(1LL<<dops[i].rt1)|(1LL<<dops[i].rt2)))|1;
57871462 8250 alloc_cc(&branch_regs[i-1],i);
8251 dirty_reg(&branch_regs[i-1],CCREG);
8252 delayslot_alloc(&branch_regs[i-1],i);
8253 branch_regs[i-1].isconst=0;
8254 alloc_reg(&current,i,CCREG); // Not taken path
8255 dirty_reg(&current,CCREG);
8256 memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
8257 }
8258 else
cf95b4f0 8259 if((dops[i-1].opcode&0x3E)==0x16) // BLEZL/BGTZL
57871462 8260 {
8261 memcpy(&branch_regs[i-1],&current,sizeof(current));
cf95b4f0 8262 branch_regs[i-1].u=(branch_unneeded_reg[i-1]&~((1LL<<dops[i].rs1)|(1LL<<dops[i].rs2)|(1LL<<dops[i].rt1)|(1LL<<dops[i].rt2)))|1;
57871462 8263 alloc_cc(&branch_regs[i-1],i);
8264 dirty_reg(&branch_regs[i-1],CCREG);
8265 delayslot_alloc(&branch_regs[i-1],i);
8266 branch_regs[i-1].isconst=0;
8267 alloc_reg(&current,i,CCREG); // Not taken path
8268 dirty_reg(&current,CCREG);
8269 memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
8270 }
8271 break;
8272 case SJUMP:
cf95b4f0 8273 //if((dops[i-1].opcode2&0x1E)==0) // BLTZ/BGEZ
8274 if((dops[i-1].opcode2&0x0E)==0) // BLTZ/BGEZ
57871462 8275 {
8276 alloc_cc(&current,i-1);
8277 dirty_reg(&current,CCREG);
cf95b4f0 8278 if(dops[i-1].rs1==dops[i].rt1||dops[i-1].rs1==dops[i].rt2) {
57871462 8279 // The delay slot overwrote the branch condition
8280 // Delay slot goes after the test (in order)
cf95b4f0 8281 current.u=branch_unneeded_reg[i-1]&~((1LL<<dops[i].rs1)|(1LL<<dops[i].rs2));
57871462 8282 current.u|=1;
57871462 8283 delayslot_alloc(&current,i);
8284 current.isconst=0;
8285 }
8286 else
8287 {
cf95b4f0 8288 current.u=branch_unneeded_reg[i-1]&~(1LL<<dops[i-1].rs1);
57871462 8289 // Alloc the branch condition register
cf95b4f0 8290 alloc_reg(&current,i-1,dops[i-1].rs1);
57871462 8291 }
8292 memcpy(&branch_regs[i-1],&current,sizeof(current));
8293 branch_regs[i-1].isconst=0;
8294 branch_regs[i-1].wasconst=0;
8295 memcpy(&branch_regs[i-1].regmap_entry,&current.regmap,sizeof(current.regmap));
40fca85b 8296 memcpy(constmap[i],constmap[i-1],sizeof(constmap[i]));
57871462 8297 }
8298 else
8299 // Alloc the delay slot in case the branch is taken
cf95b4f0 8300 if((dops[i-1].opcode2&0x1E)==2) // BLTZL/BGEZL
57871462 8301 {
8302 memcpy(&branch_regs[i-1],&current,sizeof(current));
cf95b4f0 8303 branch_regs[i-1].u=(branch_unneeded_reg[i-1]&~((1LL<<dops[i].rs1)|(1LL<<dops[i].rs2)|(1LL<<dops[i].rt1)|(1LL<<dops[i].rt2)))|1;
57871462 8304 alloc_cc(&branch_regs[i-1],i);
8305 dirty_reg(&branch_regs[i-1],CCREG);
8306 delayslot_alloc(&branch_regs[i-1],i);
8307 branch_regs[i-1].isconst=0;
8308 alloc_reg(&current,i,CCREG); // Not taken path
8309 dirty_reg(&current,CCREG);
8310 memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
8311 }
8312 // FIXME: BLTZAL/BGEZAL
cf95b4f0 8313 if(dops[i-1].opcode2&0x10) { // BxxZAL
57871462 8314 alloc_reg(&branch_regs[i-1],i-1,31);
8315 dirty_reg(&branch_regs[i-1],31);
57871462 8316 }
8317 break;
57871462 8318 }
8319
fe807a8a 8320 if (dops[i-1].is_ujump)
57871462 8321 {
cf95b4f0 8322 if(dops[i-1].rt1==31) // JAL/JALR
57871462 8323 {
8324 // Subroutine call will return here, don't alloc any registers
57871462 8325 current.dirty=0;
8326 clear_all_regs(current.regmap);
8327 alloc_reg(&current,i,CCREG);
8328 dirty_reg(&current,CCREG);
8329 }
8330 else if(i+1<slen)
8331 {
8332 // Internal branch will jump here, match registers to caller
57871462 8333 current.dirty=0;
8334 clear_all_regs(current.regmap);
8335 alloc_reg(&current,i,CCREG);
8336 dirty_reg(&current,CCREG);
8337 for(j=i-1;j>=0;j--)
8338 {
8339 if(ba[j]==start+i*4+4) {
8340 memcpy(current.regmap,branch_regs[j].regmap,sizeof(current.regmap));
57871462 8341 current.dirty=branch_regs[j].dirty;
8342 break;
8343 }
8344 }
8345 while(j>=0) {
8346 if(ba[j]==start+i*4+4) {
8347 for(hr=0;hr<HOST_REGS;hr++) {
8348 if(current.regmap[hr]!=branch_regs[j].regmap[hr]) {
8349 current.regmap[hr]=-1;
8350 }
57871462 8351 current.dirty&=branch_regs[j].dirty;
8352 }
8353 }
8354 j--;
8355 }
8356 }
8357 }
8358 }
8359
8360 // Count cycles in between branches
2330734f 8361 ccadj[i] = CLOCK_ADJUST(cc);
fe807a8a 8362 if (i > 0 && (dops[i-1].is_jump || dops[i].itype == SYSCALL || dops[i].itype == HLECALL))
57871462 8363 {
8364 cc=0;
8365 }
71e490c5 8366#if !defined(DRC_DBG)
cf95b4f0 8367 else if(dops[i].itype==C2OP&&gte_cycletab[source[i]&0x3f]>2)
054175e9 8368 {
81dbbf4c 8369 // this should really be removed since the real stalls have been implemented,
8370 // but doing so causes sizeable perf regression against the older version
8371 u_int gtec = gte_cycletab[source[i] & 0x3f];
32631e6a 8372 cc += HACK_ENABLED(NDHACK_NO_STALLS) ? gtec/2 : 2;
fb407447 8373 }
cf95b4f0 8374 else if(i>1&&dops[i].itype==STORE&&dops[i-1].itype==STORE&&dops[i-2].itype==STORE&&!dops[i].bt)
5fdcbb5a 8375 {
8376 cc+=4;
8377 }
cf95b4f0 8378 else if(dops[i].itype==C2LS)
fb407447 8379 {
81dbbf4c 8380 // same as with C2OP
32631e6a 8381 cc += HACK_ENABLED(NDHACK_NO_STALLS) ? 4 : 2;
fb407447 8382 }
8383#endif
57871462 8384 else
8385 {
8386 cc++;
8387 }
8388
cf95b4f0 8389 if(!dops[i].is_ds) {
57871462 8390 regs[i].dirty=current.dirty;
8391 regs[i].isconst=current.isconst;
40fca85b 8392 memcpy(constmap[i],current_constmap,sizeof(constmap[i]));
57871462 8393 }
8394 for(hr=0;hr<HOST_REGS;hr++) {
8395 if(hr!=EXCLUDE_REG&&regs[i].regmap[hr]>=0) {
8396 if(regmap_pre[i][hr]!=regs[i].regmap[hr]) {
8397 regs[i].wasconst&=~(1<<hr);
8398 }
8399 }
8400 }
8401 if(current.regmap[HOST_BTREG]==BTREG) current.regmap[HOST_BTREG]=-1;
27727b63 8402 regs[i].waswritten=current.waswritten;
57871462 8403 }
9f51b4b9 8404
57871462 8405 /* Pass 4 - Cull unused host registers */
9f51b4b9 8406
57871462 8407 uint64_t nr=0;
9f51b4b9 8408
57871462 8409 for (i=slen-1;i>=0;i--)
8410 {
8411 int hr;
fe807a8a 8412 if(dops[i].is_jump)
57871462 8413 {
8414 if(ba[i]<start || ba[i]>=(start+slen*4))
8415 {
8416 // Branch out of this block, don't need anything
8417 nr=0;
8418 }
8419 else
8420 {
8421 // Internal branch
8422 // Need whatever matches the target
8423 nr=0;
8424 int t=(ba[i]-start)>>2;
8425 for(hr=0;hr<HOST_REGS;hr++)
8426 {
8427 if(regs[i].regmap_entry[hr]>=0) {
8428 if(regs[i].regmap_entry[hr]==regs[t].regmap_entry[hr]) nr|=1<<hr;
8429 }
8430 }
8431 }
8432 // Conditional branch may need registers for following instructions
fe807a8a 8433 if (!dops[i].is_ujump)
57871462 8434 {
8435 if(i<slen-2) {
8436 nr|=needed_reg[i+2];
8437 for(hr=0;hr<HOST_REGS;hr++)
8438 {
8439 if(regmap_pre[i+2][hr]>=0&&get_reg(regs[i+2].regmap_entry,regmap_pre[i+2][hr])<0) nr&=~(1<<hr);
8440 //if((regmap_entry[i+2][hr])>=0) if(!((nr>>hr)&1)) printf("%x-bogus(%d=%d)\n",start+i*4,hr,regmap_entry[i+2][hr]);
8441 }
8442 }
8443 }
8444 // Don't need stuff which is overwritten
f5955059 8445 //if(regs[i].regmap[hr]!=regmap_pre[i][hr]) nr&=~(1<<hr);
8446 //if(regs[i].regmap[hr]<0) nr&=~(1<<hr);
57871462 8447 // Merge in delay slot
8448 for(hr=0;hr<HOST_REGS;hr++)
8449 {
fe807a8a 8450 if(dops[i+1].rt1&&dops[i+1].rt1==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
8451 if(dops[i+1].rt2&&dops[i+1].rt2==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
cf95b4f0 8452 if(dops[i+1].rs1==regmap_pre[i][hr]) nr|=1<<hr;
8453 if(dops[i+1].rs2==regmap_pre[i][hr]) nr|=1<<hr;
8454 if(dops[i+1].rs1==regs[i].regmap_entry[hr]) nr|=1<<hr;
8455 if(dops[i+1].rs2==regs[i].regmap_entry[hr]) nr|=1<<hr;
37387d8b 8456 if(ram_offset && (dops[i+1].is_load || dops[i+1].is_store)) {
8457 if(regmap_pre[i][hr]==ROREG) nr|=1<<hr;
8458 if(regs[i].regmap_entry[hr]==ROREG) nr|=1<<hr;
8459 }
8460 if(dops[i+1].is_store) {
57871462 8461 if(regmap_pre[i][hr]==INVCP) nr|=1<<hr;
8462 if(regs[i].regmap_entry[hr]==INVCP) nr|=1<<hr;
8463 }
8464 }
8465 }
cf95b4f0 8466 else if(dops[i].itype==SYSCALL||dops[i].itype==HLECALL||dops[i].itype==INTCALL)
57871462 8467 {
8468 // SYSCALL instruction (software interrupt)
8469 nr=0;
8470 }
cf95b4f0 8471 else if(dops[i].itype==COP0 && (source[i]&0x3f)==0x18)
57871462 8472 {
8473 // ERET instruction (return from interrupt)
8474 nr=0;
8475 }
8476 else // Non-branch
8477 {
8478 if(i<slen-1) {
8479 for(hr=0;hr<HOST_REGS;hr++) {
8480 if(regmap_pre[i+1][hr]>=0&&get_reg(regs[i+1].regmap_entry,regmap_pre[i+1][hr])<0) nr&=~(1<<hr);
8481 if(regs[i].regmap[hr]!=regmap_pre[i+1][hr]) nr&=~(1<<hr);
8482 if(regs[i].regmap[hr]!=regmap_pre[i][hr]) nr&=~(1<<hr);
8483 if(regs[i].regmap[hr]<0) nr&=~(1<<hr);
8484 }
8485 }
8486 }
8487 for(hr=0;hr<HOST_REGS;hr++)
8488 {
8489 // Overwritten registers are not needed
cf95b4f0 8490 if(dops[i].rt1&&dops[i].rt1==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
8491 if(dops[i].rt2&&dops[i].rt2==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
57871462 8492 if(FTEMP==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
8493 // Source registers are needed
cf95b4f0 8494 if(dops[i].rs1==regmap_pre[i][hr]) nr|=1<<hr;
8495 if(dops[i].rs2==regmap_pre[i][hr]) nr|=1<<hr;
8496 if(dops[i].rs1==regs[i].regmap_entry[hr]) nr|=1<<hr;
8497 if(dops[i].rs2==regs[i].regmap_entry[hr]) nr|=1<<hr;
37387d8b 8498 if(ram_offset && (dops[i].is_load || dops[i].is_store)) {
8499 if(regmap_pre[i][hr]==ROREG) nr|=1<<hr;
8500 if(regs[i].regmap_entry[hr]==ROREG) nr|=1<<hr;
8501 }
8502 if(dops[i].is_store) {
57871462 8503 if(regmap_pre[i][hr]==INVCP) nr|=1<<hr;
8504 if(regs[i].regmap_entry[hr]==INVCP) nr|=1<<hr;
8505 }
8506 // Don't store a register immediately after writing it,
8507 // may prevent dual-issue.
8508 // But do so if this is a branch target, otherwise we
8509 // might have to load the register before the branch.
cf95b4f0 8510 if(i>0&&!dops[i].bt&&((regs[i].wasdirty>>hr)&1)) {
7c3a5182 8511 if((regmap_pre[i][hr]>0&&!((unneeded_reg[i]>>regmap_pre[i][hr])&1))) {
cf95b4f0 8512 if(dops[i-1].rt1==(regmap_pre[i][hr]&63)) nr|=1<<hr;
8513 if(dops[i-1].rt2==(regmap_pre[i][hr]&63)) nr|=1<<hr;
57871462 8514 }
7c3a5182 8515 if((regs[i].regmap_entry[hr]>0&&!((unneeded_reg[i]>>regs[i].regmap_entry[hr])&1))) {
cf95b4f0 8516 if(dops[i-1].rt1==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
8517 if(dops[i-1].rt2==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
57871462 8518 }
8519 }
8520 }
8521 // Cycle count is needed at branches. Assume it is needed at the target too.
cf95b4f0 8522 if(i==0||dops[i].bt||dops[i].itype==CJUMP||dops[i].itype==SPAN) {
57871462 8523 if(regmap_pre[i][HOST_CCREG]==CCREG) nr|=1<<HOST_CCREG;
8524 if(regs[i].regmap_entry[HOST_CCREG]==CCREG) nr|=1<<HOST_CCREG;
8525 }
8526 // Save it
8527 needed_reg[i]=nr;
9f51b4b9 8528
57871462 8529 // Deallocate unneeded registers
8530 for(hr=0;hr<HOST_REGS;hr++)
8531 {
8532 if(!((nr>>hr)&1)) {
8533 if(regs[i].regmap_entry[hr]!=CCREG) regs[i].regmap_entry[hr]=-1;
fe807a8a 8534 if(dops[i].is_jump)
57871462 8535 {
37387d8b 8536 int map1 = 0, map2 = 0, temp = 0; // or -1 ??
8537 if (dops[i+1].is_load || dops[i+1].is_store)
8538 map1 = ROREG;
8539 if (dops[i+1].is_store)
8540 map2 = INVCP;
8541 if(dops[i+1].itype==LOADLR || dops[i+1].itype==STORELR || dops[i+1].itype==C2LS)
8542 temp = FTEMP;
cf95b4f0 8543 if((regs[i].regmap[hr]&63)!=dops[i].rs1 && (regs[i].regmap[hr]&63)!=dops[i].rs2 &&
8544 (regs[i].regmap[hr]&63)!=dops[i].rt1 && (regs[i].regmap[hr]&63)!=dops[i].rt2 &&
8545 (regs[i].regmap[hr]&63)!=dops[i+1].rt1 && (regs[i].regmap[hr]&63)!=dops[i+1].rt2 &&
8546 regs[i].regmap[hr]!=dops[i+1].rs1 && regs[i].regmap[hr]!=dops[i+1].rs2 &&
57871462 8547 (regs[i].regmap[hr]&63)!=temp && regs[i].regmap[hr]!=PTEMP &&
8548 regs[i].regmap[hr]!=RHASH && regs[i].regmap[hr]!=RHTBL &&
8549 regs[i].regmap[hr]!=RTEMP && regs[i].regmap[hr]!=CCREG &&
37387d8b 8550 regs[i].regmap[hr]!=map1 && regs[i].regmap[hr]!=map2)
57871462 8551 {
8552 regs[i].regmap[hr]=-1;
8553 regs[i].isconst&=~(1<<hr);
a550c61c 8554 regs[i].dirty&=~(1<<hr);
8555 regs[i+1].wasdirty&=~(1<<hr);
cf95b4f0 8556 if((branch_regs[i].regmap[hr]&63)!=dops[i].rs1 && (branch_regs[i].regmap[hr]&63)!=dops[i].rs2 &&
8557 (branch_regs[i].regmap[hr]&63)!=dops[i].rt1 && (branch_regs[i].regmap[hr]&63)!=dops[i].rt2 &&
8558 (branch_regs[i].regmap[hr]&63)!=dops[i+1].rt1 && (branch_regs[i].regmap[hr]&63)!=dops[i+1].rt2 &&
8559 branch_regs[i].regmap[hr]!=dops[i+1].rs1 && branch_regs[i].regmap[hr]!=dops[i+1].rs2 &&
57871462 8560 (branch_regs[i].regmap[hr]&63)!=temp && branch_regs[i].regmap[hr]!=PTEMP &&
8561 branch_regs[i].regmap[hr]!=RHASH && branch_regs[i].regmap[hr]!=RHTBL &&
8562 branch_regs[i].regmap[hr]!=RTEMP && branch_regs[i].regmap[hr]!=CCREG &&
37387d8b 8563 branch_regs[i].regmap[hr]!=map1 && branch_regs[i].regmap[hr]!=map2)
57871462 8564 {
8565 branch_regs[i].regmap[hr]=-1;
8566 branch_regs[i].regmap_entry[hr]=-1;
fe807a8a 8567 if (!dops[i].is_ujump)
57871462 8568 {
fe807a8a 8569 if (i < slen-2) {
57871462 8570 regmap_pre[i+2][hr]=-1;
79c75f1b 8571 regs[i+2].wasconst&=~(1<<hr);
57871462 8572 }
8573 }
8574 }
8575 }
8576 }
8577 else
8578 {
8579 // Non-branch
8580 if(i>0)
8581 {
37387d8b 8582 int map1 = -1, map2 = -1, temp=-1;
8583 if (dops[i].is_load || dops[i].is_store)
8584 map1 = ROREG;
8585 if (dops[i].is_store)
8586 map2 = INVCP;
8587 if (dops[i].itype==LOADLR || dops[i].itype==STORELR || dops[i].itype==C2LS)
8588 temp = FTEMP;
cf95b4f0 8589 if((regs[i].regmap[hr]&63)!=dops[i].rt1 && (regs[i].regmap[hr]&63)!=dops[i].rt2 &&
8590 regs[i].regmap[hr]!=dops[i].rs1 && regs[i].regmap[hr]!=dops[i].rs2 &&
37387d8b 8591 (regs[i].regmap[hr]&63)!=temp && regs[i].regmap[hr]!=map1 && regs[i].regmap[hr]!=map2 &&
4b1c7cd1 8592 //(dops[i].itype!=SPAN||regs[i].regmap[hr]!=CCREG)
8593 regs[i].regmap[hr] != CCREG)
57871462 8594 {
cf95b4f0 8595 if(i<slen-1&&!dops[i].is_ds) {
ad49de89 8596 assert(regs[i].regmap[hr]<64);
afec9d44 8597 if(regmap_pre[i+1][hr]!=-1 || regs[i].regmap[hr]>0)
57871462 8598 if(regmap_pre[i+1][hr]!=regs[i].regmap[hr])
57871462 8599 {
c43b5311 8600 SysPrintf("fail: %x (%d %d!=%d)\n",start+i*4,hr,regmap_pre[i+1][hr],regs[i].regmap[hr]);
57871462 8601 assert(regmap_pre[i+1][hr]==regs[i].regmap[hr]);
8602 }
8603 regmap_pre[i+1][hr]=-1;
8604 if(regs[i+1].regmap_entry[hr]==CCREG) regs[i+1].regmap_entry[hr]=-1;
79c75f1b 8605 regs[i+1].wasconst&=~(1<<hr);
57871462 8606 }
8607 regs[i].regmap[hr]=-1;
8608 regs[i].isconst&=~(1<<hr);
a550c61c 8609 regs[i].dirty&=~(1<<hr);
8610 regs[i+1].wasdirty&=~(1<<hr);
57871462 8611 }
8612 }
8613 }
3968e69e 8614 } // if needed
8615 } // for hr
57871462 8616 }
9f51b4b9 8617
57871462 8618 /* Pass 5 - Pre-allocate registers */
9f51b4b9 8619
57871462 8620 // If a register is allocated during a loop, try to allocate it for the
8621 // entire loop, if possible. This avoids loading/storing registers
8622 // inside of the loop.
9f51b4b9 8623
57871462 8624 signed char f_regmap[HOST_REGS];
8625 clear_all_regs(f_regmap);
8626 for(i=0;i<slen-1;i++)
8627 {
cf95b4f0 8628 if(dops[i].itype==UJUMP||dops[i].itype==CJUMP||dops[i].itype==SJUMP)
57871462 8629 {
9f51b4b9 8630 if(ba[i]>=start && ba[i]<(start+i*4))
cf95b4f0 8631 if(dops[i+1].itype==NOP||dops[i+1].itype==MOV||dops[i+1].itype==ALU
8632 ||dops[i+1].itype==SHIFTIMM||dops[i+1].itype==IMM16||dops[i+1].itype==LOAD
8633 ||dops[i+1].itype==STORE||dops[i+1].itype==STORELR||dops[i+1].itype==C1LS
8634 ||dops[i+1].itype==SHIFT||dops[i+1].itype==COP1
8635 ||dops[i+1].itype==COP2||dops[i+1].itype==C2LS||dops[i+1].itype==C2OP)
57871462 8636 {
8637 int t=(ba[i]-start)>>2;
fe807a8a 8638 if(t > 0 && !dops[t-1].is_jump) // loop_preload can't handle jumps into delay slots
cf95b4f0 8639 if(t<2||(dops[t-2].itype!=UJUMP&&dops[t-2].itype!=RJUMP)||dops[t-2].rt1!=31) // call/ret assumes no registers allocated
57871462 8640 for(hr=0;hr<HOST_REGS;hr++)
8641 {
7c3a5182 8642 if(regs[i].regmap[hr]>=0) {
b372a952 8643 if(f_regmap[hr]!=regs[i].regmap[hr]) {
8644 // dealloc old register
8645 int n;
8646 for(n=0;n<HOST_REGS;n++)
8647 {
8648 if(f_regmap[n]==regs[i].regmap[hr]) {f_regmap[n]=-1;}
8649 }
8650 // and alloc new one
8651 f_regmap[hr]=regs[i].regmap[hr];
8652 }
8653 }
7c3a5182 8654 if(branch_regs[i].regmap[hr]>=0) {
b372a952 8655 if(f_regmap[hr]!=branch_regs[i].regmap[hr]) {
8656 // dealloc old register
8657 int n;
8658 for(n=0;n<HOST_REGS;n++)
8659 {
8660 if(f_regmap[n]==branch_regs[i].regmap[hr]) {f_regmap[n]=-1;}
8661 }
8662 // and alloc new one
8663 f_regmap[hr]=branch_regs[i].regmap[hr];
8664 }
8665 }
cf95b4f0 8666 if(dops[i].ooo) {
9f51b4b9 8667 if(count_free_regs(regs[i].regmap)<=minimum_free_regs[i+1])
e1190b87 8668 f_regmap[hr]=branch_regs[i].regmap[hr];
8669 }else{
9f51b4b9 8670 if(count_free_regs(branch_regs[i].regmap)<=minimum_free_regs[i+1])
57871462 8671 f_regmap[hr]=branch_regs[i].regmap[hr];
8672 }
8673 // Avoid dirty->clean transition
e1190b87 8674 #ifdef DESTRUCTIVE_WRITEBACK
57871462 8675 if(t>0) if(get_reg(regmap_pre[t],f_regmap[hr])>=0) if((regs[t].wasdirty>>get_reg(regmap_pre[t],f_regmap[hr]))&1) f_regmap[hr]=-1;
e1190b87 8676 #endif
8677 // This check is only strictly required in the DESTRUCTIVE_WRITEBACK
8678 // case above, however it's always a good idea. We can't hoist the
8679 // load if the register was already allocated, so there's no point
8680 // wasting time analyzing most of these cases. It only "succeeds"
8681 // when the mapping was different and the load can be replaced with
8682 // a mov, which is of negligible benefit. So such cases are
8683 // skipped below.
57871462 8684 if(f_regmap[hr]>0) {
198df76f 8685 if(regs[t].regmap[hr]==f_regmap[hr]||(regs[t].regmap_entry[hr]<0&&get_reg(regmap_pre[t],f_regmap[hr])<0)) {
57871462 8686 int r=f_regmap[hr];
8687 for(j=t;j<=i;j++)
8688 {
8689 //printf("Test %x -> %x, %x %d/%d\n",start+i*4,ba[i],start+j*4,hr,r);
8690 if(r<34&&((unneeded_reg[j]>>r)&1)) break;
00fa9369 8691 assert(r < 64);
57871462 8692 if(regs[j].regmap[hr]==f_regmap[hr]&&(f_regmap[hr]&63)<TEMPREG) {
8693 //printf("Hit %x -> %x, %x %d/%d\n",start+i*4,ba[i],start+j*4,hr,r);
8694 int k;
8695 if(regs[i].regmap[hr]==-1&&branch_regs[i].regmap[hr]==-1) {
670c0f22 8696 if(get_reg(regs[i].regmap,f_regmap[hr])>=0) break;
57871462 8697 if(get_reg(regs[i+2].regmap,f_regmap[hr])>=0) break;
57871462 8698 k=i;
8699 while(k>1&&regs[k-1].regmap[hr]==-1) {
e1190b87 8700 if(count_free_regs(regs[k-1].regmap)<=minimum_free_regs[k-1]) {
8701 //printf("no free regs for store %x\n",start+(k-1)*4);
8702 break;
57871462 8703 }
57871462 8704 if(get_reg(regs[k-1].regmap,f_regmap[hr])>=0) {
8705 //printf("no-match due to different register\n");
8706 break;
8707 }
fe807a8a 8708 if (dops[k-2].is_jump) {
57871462 8709 //printf("no-match due to branch\n");
8710 break;
8711 }
8712 // call/ret fast path assumes no registers allocated
cf95b4f0 8713 if(k>2&&(dops[k-3].itype==UJUMP||dops[k-3].itype==RJUMP)&&dops[k-3].rt1==31) {
57871462 8714 break;
8715 }
57871462 8716 k--;
8717 }
57871462 8718 if(regs[k-1].regmap[hr]==f_regmap[hr]&&regmap_pre[k][hr]==f_regmap[hr]) {
8719 //printf("Extend r%d, %x ->\n",hr,start+k*4);
8720 while(k<i) {
8721 regs[k].regmap_entry[hr]=f_regmap[hr];
8722 regs[k].regmap[hr]=f_regmap[hr];
8723 regmap_pre[k+1][hr]=f_regmap[hr];
8724 regs[k].wasdirty&=~(1<<hr);
8725 regs[k].dirty&=~(1<<hr);
8726 regs[k].wasdirty|=(1<<hr)&regs[k-1].dirty;
8727 regs[k].dirty|=(1<<hr)&regs[k].wasdirty;
8728 regs[k].wasconst&=~(1<<hr);
8729 regs[k].isconst&=~(1<<hr);
8730 k++;
8731 }
8732 }
8733 else {
8734 //printf("Fail Extend r%d, %x ->\n",hr,start+k*4);
8735 break;
8736 }
8737 assert(regs[i-1].regmap[hr]==f_regmap[hr]);
8738 if(regs[i-1].regmap[hr]==f_regmap[hr]&&regmap_pre[i][hr]==f_regmap[hr]) {
8739 //printf("OK fill %x (r%d)\n",start+i*4,hr);
8740 regs[i].regmap_entry[hr]=f_regmap[hr];
8741 regs[i].regmap[hr]=f_regmap[hr];
8742 regs[i].wasdirty&=~(1<<hr);
8743 regs[i].dirty&=~(1<<hr);
8744 regs[i].wasdirty|=(1<<hr)&regs[i-1].dirty;
8745 regs[i].dirty|=(1<<hr)&regs[i-1].dirty;
8746 regs[i].wasconst&=~(1<<hr);
8747 regs[i].isconst&=~(1<<hr);
8748 branch_regs[i].regmap_entry[hr]=f_regmap[hr];
8749 branch_regs[i].wasdirty&=~(1<<hr);
8750 branch_regs[i].wasdirty|=(1<<hr)&regs[i].dirty;
8751 branch_regs[i].regmap[hr]=f_regmap[hr];
8752 branch_regs[i].dirty&=~(1<<hr);
8753 branch_regs[i].dirty|=(1<<hr)&regs[i].dirty;
8754 branch_regs[i].wasconst&=~(1<<hr);
8755 branch_regs[i].isconst&=~(1<<hr);
fe807a8a 8756 if (!dops[i].is_ujump) {
57871462 8757 regmap_pre[i+2][hr]=f_regmap[hr];
8758 regs[i+2].wasdirty&=~(1<<hr);
8759 regs[i+2].wasdirty|=(1<<hr)&regs[i].dirty;
57871462 8760 }
8761 }
8762 }
8763 for(k=t;k<j;k++) {
e1190b87 8764 // Alloc register clean at beginning of loop,
8765 // but may dirty it in pass 6
57871462 8766 regs[k].regmap_entry[hr]=f_regmap[hr];
8767 regs[k].regmap[hr]=f_regmap[hr];
57871462 8768 regs[k].dirty&=~(1<<hr);
8769 regs[k].wasconst&=~(1<<hr);
8770 regs[k].isconst&=~(1<<hr);
fe807a8a 8771 if (dops[k].is_jump) {
e1190b87 8772 branch_regs[k].regmap_entry[hr]=f_regmap[hr];
8773 branch_regs[k].regmap[hr]=f_regmap[hr];
8774 branch_regs[k].dirty&=~(1<<hr);
8775 branch_regs[k].wasconst&=~(1<<hr);
8776 branch_regs[k].isconst&=~(1<<hr);
fe807a8a 8777 if (!dops[k].is_ujump) {
e1190b87 8778 regmap_pre[k+2][hr]=f_regmap[hr];
8779 regs[k+2].wasdirty&=~(1<<hr);
e1190b87 8780 }
8781 }
8782 else
8783 {
8784 regmap_pre[k+1][hr]=f_regmap[hr];
8785 regs[k+1].wasdirty&=~(1<<hr);
8786 }
57871462 8787 }
8788 if(regs[j].regmap[hr]==f_regmap[hr])
8789 regs[j].regmap_entry[hr]=f_regmap[hr];
8790 break;
8791 }
8792 if(j==i) break;
8793 if(regs[j].regmap[hr]>=0)
8794 break;
8795 if(get_reg(regs[j].regmap,f_regmap[hr])>=0) {
8796 //printf("no-match due to different register\n");
8797 break;
8798 }
fe807a8a 8799 if (dops[j].is_ujump)
e1190b87 8800 {
8801 // Stop on unconditional branch
8802 break;
8803 }
cf95b4f0 8804 if(dops[j].itype==CJUMP||dops[j].itype==SJUMP)
e1190b87 8805 {
cf95b4f0 8806 if(dops[j].ooo) {
9f51b4b9 8807 if(count_free_regs(regs[j].regmap)<=minimum_free_regs[j+1])
e1190b87 8808 break;
8809 }else{
9f51b4b9 8810 if(count_free_regs(branch_regs[j].regmap)<=minimum_free_regs[j+1])
e1190b87 8811 break;
8812 }
8813 if(get_reg(branch_regs[j].regmap,f_regmap[hr])>=0) {
8814 //printf("no-match due to different register (branch)\n");
57871462 8815 break;
8816 }
8817 }
e1190b87 8818 if(count_free_regs(regs[j].regmap)<=minimum_free_regs[j]) {
8819 //printf("No free regs for store %x\n",start+j*4);
8820 break;
8821 }
ad49de89 8822 assert(f_regmap[hr]<64);
57871462 8823 }
8824 }
8825 }
8826 }
8827 }
8828 }else{
198df76f 8829 // Non branch or undetermined branch target
57871462 8830 for(hr=0;hr<HOST_REGS;hr++)
8831 {
8832 if(hr!=EXCLUDE_REG) {
7c3a5182 8833 if(regs[i].regmap[hr]>=0) {
b372a952 8834 if(f_regmap[hr]!=regs[i].regmap[hr]) {
8835 // dealloc old register
8836 int n;
8837 for(n=0;n<HOST_REGS;n++)
8838 {
8839 if(f_regmap[n]==regs[i].regmap[hr]) {f_regmap[n]=-1;}
8840 }
8841 // and alloc new one
8842 f_regmap[hr]=regs[i].regmap[hr];
8843 }
8844 }
57871462 8845 }
8846 }
8847 // Try to restore cycle count at branch targets
cf95b4f0 8848 if(dops[i].bt) {
57871462 8849 for(j=i;j<slen-1;j++) {
8850 if(regs[j].regmap[HOST_CCREG]!=-1) break;
e1190b87 8851 if(count_free_regs(regs[j].regmap)<=minimum_free_regs[j]) {
8852 //printf("no free regs for store %x\n",start+j*4);
8853 break;
57871462 8854 }
57871462 8855 }
8856 if(regs[j].regmap[HOST_CCREG]==CCREG) {
8857 int k=i;
8858 //printf("Extend CC, %x -> %x\n",start+k*4,start+j*4);
8859 while(k<j) {
8860 regs[k].regmap_entry[HOST_CCREG]=CCREG;
8861 regs[k].regmap[HOST_CCREG]=CCREG;
8862 regmap_pre[k+1][HOST_CCREG]=CCREG;
8863 regs[k+1].wasdirty|=1<<HOST_CCREG;
8864 regs[k].dirty|=1<<HOST_CCREG;
8865 regs[k].wasconst&=~(1<<HOST_CCREG);
8866 regs[k].isconst&=~(1<<HOST_CCREG);
8867 k++;
8868 }
9f51b4b9 8869 regs[j].regmap_entry[HOST_CCREG]=CCREG;
57871462 8870 }
8871 // Work backwards from the branch target
8872 if(j>i&&f_regmap[HOST_CCREG]==CCREG)
8873 {
8874 //printf("Extend backwards\n");
8875 int k;
8876 k=i;
8877 while(regs[k-1].regmap[HOST_CCREG]==-1) {
e1190b87 8878 if(count_free_regs(regs[k-1].regmap)<=minimum_free_regs[k-1]) {
8879 //printf("no free regs for store %x\n",start+(k-1)*4);
8880 break;
57871462 8881 }
57871462 8882 k--;
8883 }
8884 if(regs[k-1].regmap[HOST_CCREG]==CCREG) {
8885 //printf("Extend CC, %x ->\n",start+k*4);
8886 while(k<=i) {
8887 regs[k].regmap_entry[HOST_CCREG]=CCREG;
8888 regs[k].regmap[HOST_CCREG]=CCREG;
8889 regmap_pre[k+1][HOST_CCREG]=CCREG;
8890 regs[k+1].wasdirty|=1<<HOST_CCREG;
8891 regs[k].dirty|=1<<HOST_CCREG;
8892 regs[k].wasconst&=~(1<<HOST_CCREG);
8893 regs[k].isconst&=~(1<<HOST_CCREG);
8894 k++;
8895 }
8896 }
8897 else {
8898 //printf("Fail Extend CC, %x ->\n",start+k*4);
8899 }
8900 }
8901 }
cf95b4f0 8902 if(dops[i].itype!=STORE&&dops[i].itype!=STORELR&&dops[i].itype!=C1LS&&dops[i].itype!=SHIFT&&
8903 dops[i].itype!=NOP&&dops[i].itype!=MOV&&dops[i].itype!=ALU&&dops[i].itype!=SHIFTIMM&&
8904 dops[i].itype!=IMM16&&dops[i].itype!=LOAD&&dops[i].itype!=COP1)
57871462 8905 {
8906 memcpy(f_regmap,regs[i].regmap,sizeof(f_regmap));
8907 }
8908 }
8909 }
9f51b4b9 8910
57871462 8911 // This allocates registers (if possible) one instruction prior
8912 // to use, which can avoid a load-use penalty on certain CPUs.
8913 for(i=0;i<slen-1;i++)
8914 {
fe807a8a 8915 if (!i || !dops[i-1].is_jump)
57871462 8916 {
cf95b4f0 8917 if(!dops[i+1].bt)
57871462 8918 {
cf95b4f0 8919 if(dops[i].itype==ALU||dops[i].itype==MOV||dops[i].itype==LOAD||dops[i].itype==SHIFTIMM||dops[i].itype==IMM16
8920 ||((dops[i].itype==COP1||dops[i].itype==COP2)&&dops[i].opcode2<3))
57871462 8921 {
cf95b4f0 8922 if(dops[i+1].rs1) {
8923 if((hr=get_reg(regs[i+1].regmap,dops[i+1].rs1))>=0)
57871462 8924 {
8925 if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
8926 {
8927 regs[i].regmap[hr]=regs[i+1].regmap[hr];
8928 regmap_pre[i+1][hr]=regs[i+1].regmap[hr];
8929 regs[i+1].regmap_entry[hr]=regs[i+1].regmap[hr];
8930 regs[i].isconst&=~(1<<hr);
8931 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
8932 constmap[i][hr]=constmap[i+1][hr];
8933 regs[i+1].wasdirty&=~(1<<hr);
8934 regs[i].dirty&=~(1<<hr);
8935 }
8936 }
8937 }
cf95b4f0 8938 if(dops[i+1].rs2) {
8939 if((hr=get_reg(regs[i+1].regmap,dops[i+1].rs2))>=0)
57871462 8940 {
8941 if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
8942 {
8943 regs[i].regmap[hr]=regs[i+1].regmap[hr];
8944 regmap_pre[i+1][hr]=regs[i+1].regmap[hr];
8945 regs[i+1].regmap_entry[hr]=regs[i+1].regmap[hr];
8946 regs[i].isconst&=~(1<<hr);
8947 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
8948 constmap[i][hr]=constmap[i+1][hr];
8949 regs[i+1].wasdirty&=~(1<<hr);
8950 regs[i].dirty&=~(1<<hr);
8951 }
8952 }
8953 }
198df76f 8954 // Preload target address for load instruction (non-constant)
cf95b4f0 8955 if(dops[i+1].itype==LOAD&&dops[i+1].rs1&&get_reg(regs[i+1].regmap,dops[i+1].rs1)<0) {
8956 if((hr=get_reg(regs[i+1].regmap,dops[i+1].rt1))>=0)
57871462 8957 {
8958 if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
8959 {
cf95b4f0 8960 regs[i].regmap[hr]=dops[i+1].rs1;
8961 regmap_pre[i+1][hr]=dops[i+1].rs1;
8962 regs[i+1].regmap_entry[hr]=dops[i+1].rs1;
57871462 8963 regs[i].isconst&=~(1<<hr);
8964 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
8965 constmap[i][hr]=constmap[i+1][hr];
8966 regs[i+1].wasdirty&=~(1<<hr);
8967 regs[i].dirty&=~(1<<hr);
8968 }
8969 }
8970 }
9f51b4b9 8971 // Load source into target register
cf95b4f0 8972 if(dops[i+1].lt1&&get_reg(regs[i+1].regmap,dops[i+1].rs1)<0) {
8973 if((hr=get_reg(regs[i+1].regmap,dops[i+1].rt1))>=0)
57871462 8974 {
8975 if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
8976 {
cf95b4f0 8977 regs[i].regmap[hr]=dops[i+1].rs1;
8978 regmap_pre[i+1][hr]=dops[i+1].rs1;
8979 regs[i+1].regmap_entry[hr]=dops[i+1].rs1;
57871462 8980 regs[i].isconst&=~(1<<hr);
8981 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
8982 constmap[i][hr]=constmap[i+1][hr];
8983 regs[i+1].wasdirty&=~(1<<hr);
8984 regs[i].dirty&=~(1<<hr);
8985 }
8986 }
8987 }
198df76f 8988 // Address for store instruction (non-constant)
cf95b4f0 8989 if(dops[i+1].itype==STORE||dops[i+1].itype==STORELR
8990 ||(dops[i+1].opcode&0x3b)==0x39||(dops[i+1].opcode&0x3b)==0x3a) { // SB/SH/SW/SD/SWC1/SDC1/SWC2/SDC2
8991 if(get_reg(regs[i+1].regmap,dops[i+1].rs1)<0) {
57871462 8992 hr=get_reg2(regs[i].regmap,regs[i+1].regmap,-1);
8993 if(hr<0) hr=get_reg(regs[i+1].regmap,-1);
6cc8d23c 8994 else {
8995 regs[i+1].regmap[hr]=AGEN1+((i+1)&1);
8996 regs[i+1].isconst&=~(1<<hr);
8997 }
57871462 8998 assert(hr>=0);
8999 if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
9000 {
cf95b4f0 9001 regs[i].regmap[hr]=dops[i+1].rs1;
9002 regmap_pre[i+1][hr]=dops[i+1].rs1;
9003 regs[i+1].regmap_entry[hr]=dops[i+1].rs1;
57871462 9004 regs[i].isconst&=~(1<<hr);
9005 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
9006 constmap[i][hr]=constmap[i+1][hr];
9007 regs[i+1].wasdirty&=~(1<<hr);
9008 regs[i].dirty&=~(1<<hr);
9009 }
9010 }
9011 }
cf95b4f0 9012 if(dops[i+1].itype==LOADLR||(dops[i+1].opcode&0x3b)==0x31||(dops[i+1].opcode&0x3b)==0x32) { // LWC1/LDC1, LWC2/LDC2
9013 if(get_reg(regs[i+1].regmap,dops[i+1].rs1)<0) {
57871462 9014 int nr;
9015 hr=get_reg(regs[i+1].regmap,FTEMP);
9016 assert(hr>=0);
9017 if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
9018 {
cf95b4f0 9019 regs[i].regmap[hr]=dops[i+1].rs1;
9020 regmap_pre[i+1][hr]=dops[i+1].rs1;
9021 regs[i+1].regmap_entry[hr]=dops[i+1].rs1;
57871462 9022 regs[i].isconst&=~(1<<hr);
9023 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
9024 constmap[i][hr]=constmap[i+1][hr];
9025 regs[i+1].wasdirty&=~(1<<hr);
9026 regs[i].dirty&=~(1<<hr);
9027 }
9028 else if((nr=get_reg2(regs[i].regmap,regs[i+1].regmap,-1))>=0)
9029 {
9030 // move it to another register
9031 regs[i+1].regmap[hr]=-1;
9032 regmap_pre[i+2][hr]=-1;
9033 regs[i+1].regmap[nr]=FTEMP;
9034 regmap_pre[i+2][nr]=FTEMP;
cf95b4f0 9035 regs[i].regmap[nr]=dops[i+1].rs1;
9036 regmap_pre[i+1][nr]=dops[i+1].rs1;
9037 regs[i+1].regmap_entry[nr]=dops[i+1].rs1;
57871462 9038 regs[i].isconst&=~(1<<nr);
9039 regs[i+1].isconst&=~(1<<nr);
9040 regs[i].dirty&=~(1<<nr);
9041 regs[i+1].wasdirty&=~(1<<nr);
9042 regs[i+1].dirty&=~(1<<nr);
9043 regs[i+2].wasdirty&=~(1<<nr);
9044 }
9045 }
9046 }
cf95b4f0 9047 if(dops[i+1].itype==LOAD||dops[i+1].itype==LOADLR||dops[i+1].itype==STORE||dops[i+1].itype==STORELR/*||dops[i+1].itype==C1LS||||dops[i+1].itype==C2LS*/) {
9048 if(dops[i+1].itype==LOAD)
9049 hr=get_reg(regs[i+1].regmap,dops[i+1].rt1);
9050 if(dops[i+1].itype==LOADLR||(dops[i+1].opcode&0x3b)==0x31||(dops[i+1].opcode&0x3b)==0x32) // LWC1/LDC1, LWC2/LDC2
57871462 9051 hr=get_reg(regs[i+1].regmap,FTEMP);
cf95b4f0 9052 if(dops[i+1].itype==STORE||dops[i+1].itype==STORELR||(dops[i+1].opcode&0x3b)==0x39||(dops[i+1].opcode&0x3b)==0x3a) { // SWC1/SDC1/SWC2/SDC2
57871462 9053 hr=get_reg(regs[i+1].regmap,AGEN1+((i+1)&1));
9054 if(hr<0) hr=get_reg(regs[i+1].regmap,-1);
9055 }
9056 if(hr>=0&&regs[i].regmap[hr]<0) {
cf95b4f0 9057 int rs=get_reg(regs[i+1].regmap,dops[i+1].rs1);
57871462 9058 if(rs>=0&&((regs[i+1].wasconst>>rs)&1)) {
9059 regs[i].regmap[hr]=AGEN1+((i+1)&1);
9060 regmap_pre[i+1][hr]=AGEN1+((i+1)&1);
9061 regs[i+1].regmap_entry[hr]=AGEN1+((i+1)&1);
9062 regs[i].isconst&=~(1<<hr);
9063 regs[i+1].wasdirty&=~(1<<hr);
9064 regs[i].dirty&=~(1<<hr);
9065 }
9066 }
9067 }
9068 }
9069 }
9070 }
9071 }
9f51b4b9 9072
57871462 9073 /* Pass 6 - Optimize clean/dirty state */
9074 clean_registers(0,slen-1,1);
9f51b4b9 9075
57871462 9076 /* Pass 7 - Identify 32-bit registers */
04fd948a 9077 for (i=slen-1;i>=0;i--)
9078 {
cf95b4f0 9079 if(dops[i].itype==CJUMP||dops[i].itype==SJUMP)
04fd948a 9080 {
9081 // Conditional branch
9082 if((source[i]>>16)!=0x1000&&i<slen-2) {
9083 // Mark this address as a branch target since it may be called
9084 // upon return from interrupt
cf95b4f0 9085 dops[i+2].bt=1;
04fd948a 9086 }
9087 }
9088 }
57871462 9089
cf95b4f0 9090 if(dops[slen-1].itype==SPAN) {
9091 dops[slen-1].bt=1; // Mark as a branch target so instruction can restart after exception
57871462 9092 }
4600ba03 9093
d1150cd6 9094#ifdef REG_ALLOC_PRINT
57871462 9095 /* Debug/disassembly */
57871462 9096 for(i=0;i<slen;i++)
9097 {
9098 printf("U:");
9099 int r;
9100 for(r=1;r<=CCREG;r++) {
9101 if((unneeded_reg[i]>>r)&1) {
9102 if(r==HIREG) printf(" HI");
9103 else if(r==LOREG) printf(" LO");
9104 else printf(" r%d",r);
9105 }
9106 }
57871462 9107 printf("\n");
9108 #if defined(__i386__) || defined(__x86_64__)
9109 printf("pre: eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",regmap_pre[i][0],regmap_pre[i][1],regmap_pre[i][2],regmap_pre[i][3],regmap_pre[i][5],regmap_pre[i][6],regmap_pre[i][7]);
9110 #endif
9111 #ifdef __arm__
9112 printf("pre: r0=%d r1=%d r2=%d r3=%d r4=%d r5=%d r6=%d r7=%d r8=%d r9=%d r10=%d r12=%d\n",regmap_pre[i][0],regmap_pre[i][1],regmap_pre[i][2],regmap_pre[i][3],regmap_pre[i][4],regmap_pre[i][5],regmap_pre[i][6],regmap_pre[i][7],regmap_pre[i][8],regmap_pre[i][9],regmap_pre[i][10],regmap_pre[i][12]);
9113 #endif
7c3a5182 9114 #if defined(__i386__) || defined(__x86_64__)
57871462 9115 printf("needs: ");
9116 if(needed_reg[i]&1) printf("eax ");
9117 if((needed_reg[i]>>1)&1) printf("ecx ");
9118 if((needed_reg[i]>>2)&1) printf("edx ");
9119 if((needed_reg[i]>>3)&1) printf("ebx ");
9120 if((needed_reg[i]>>5)&1) printf("ebp ");
9121 if((needed_reg[i]>>6)&1) printf("esi ");
9122 if((needed_reg[i]>>7)&1) printf("edi ");
57871462 9123 printf("\n");
57871462 9124 printf("entry: eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",regs[i].regmap_entry[0],regs[i].regmap_entry[1],regs[i].regmap_entry[2],regs[i].regmap_entry[3],regs[i].regmap_entry[5],regs[i].regmap_entry[6],regs[i].regmap_entry[7]);
9125 printf("dirty: ");
9126 if(regs[i].wasdirty&1) printf("eax ");
9127 if((regs[i].wasdirty>>1)&1) printf("ecx ");
9128 if((regs[i].wasdirty>>2)&1) printf("edx ");
9129 if((regs[i].wasdirty>>3)&1) printf("ebx ");
9130 if((regs[i].wasdirty>>5)&1) printf("ebp ");
9131 if((regs[i].wasdirty>>6)&1) printf("esi ");
9132 if((regs[i].wasdirty>>7)&1) printf("edi ");
9133 #endif
9134 #ifdef __arm__
9135 printf("entry: r0=%d r1=%d r2=%d r3=%d r4=%d r5=%d r6=%d r7=%d r8=%d r9=%d r10=%d r12=%d\n",regs[i].regmap_entry[0],regs[i].regmap_entry[1],regs[i].regmap_entry[2],regs[i].regmap_entry[3],regs[i].regmap_entry[4],regs[i].regmap_entry[5],regs[i].regmap_entry[6],regs[i].regmap_entry[7],regs[i].regmap_entry[8],regs[i].regmap_entry[9],regs[i].regmap_entry[10],regs[i].regmap_entry[12]);
9136 printf("dirty: ");
9137 if(regs[i].wasdirty&1) printf("r0 ");
9138 if((regs[i].wasdirty>>1)&1) printf("r1 ");
9139 if((regs[i].wasdirty>>2)&1) printf("r2 ");
9140 if((regs[i].wasdirty>>3)&1) printf("r3 ");
9141 if((regs[i].wasdirty>>4)&1) printf("r4 ");
9142 if((regs[i].wasdirty>>5)&1) printf("r5 ");
9143 if((regs[i].wasdirty>>6)&1) printf("r6 ");
9144 if((regs[i].wasdirty>>7)&1) printf("r7 ");
9145 if((regs[i].wasdirty>>8)&1) printf("r8 ");
9146 if((regs[i].wasdirty>>9)&1) printf("r9 ");
9147 if((regs[i].wasdirty>>10)&1) printf("r10 ");
9148 if((regs[i].wasdirty>>12)&1) printf("r12 ");
9149 #endif
9150 printf("\n");
9151 disassemble_inst(i);
9152 //printf ("ccadj[%d] = %d\n",i,ccadj[i]);
9153 #if defined(__i386__) || defined(__x86_64__)
9154 printf("eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d dirty: ",regs[i].regmap[0],regs[i].regmap[1],regs[i].regmap[2],regs[i].regmap[3],regs[i].regmap[5],regs[i].regmap[6],regs[i].regmap[7]);
9155 if(regs[i].dirty&1) printf("eax ");
9156 if((regs[i].dirty>>1)&1) printf("ecx ");
9157 if((regs[i].dirty>>2)&1) printf("edx ");
9158 if((regs[i].dirty>>3)&1) printf("ebx ");
9159 if((regs[i].dirty>>5)&1) printf("ebp ");
9160 if((regs[i].dirty>>6)&1) printf("esi ");
9161 if((regs[i].dirty>>7)&1) printf("edi ");
9162 #endif
9163 #ifdef __arm__
9164 printf("r0=%d r1=%d r2=%d r3=%d r4=%d r5=%d r6=%d r7=%d r8=%d r9=%d r10=%d r12=%d dirty: ",regs[i].regmap[0],regs[i].regmap[1],regs[i].regmap[2],regs[i].regmap[3],regs[i].regmap[4],regs[i].regmap[5],regs[i].regmap[6],regs[i].regmap[7],regs[i].regmap[8],regs[i].regmap[9],regs[i].regmap[10],regs[i].regmap[12]);
9165 if(regs[i].dirty&1) printf("r0 ");
9166 if((regs[i].dirty>>1)&1) printf("r1 ");
9167 if((regs[i].dirty>>2)&1) printf("r2 ");
9168 if((regs[i].dirty>>3)&1) printf("r3 ");
9169 if((regs[i].dirty>>4)&1) printf("r4 ");
9170 if((regs[i].dirty>>5)&1) printf("r5 ");
9171 if((regs[i].dirty>>6)&1) printf("r6 ");
9172 if((regs[i].dirty>>7)&1) printf("r7 ");
9173 if((regs[i].dirty>>8)&1) printf("r8 ");
9174 if((regs[i].dirty>>9)&1) printf("r9 ");
9175 if((regs[i].dirty>>10)&1) printf("r10 ");
9176 if((regs[i].dirty>>12)&1) printf("r12 ");
9177 #endif
9178 printf("\n");
9179 if(regs[i].isconst) {
9180 printf("constants: ");
9181 #if defined(__i386__) || defined(__x86_64__)
643aeae3 9182 if(regs[i].isconst&1) printf("eax=%x ",(u_int)constmap[i][0]);
9183 if((regs[i].isconst>>1)&1) printf("ecx=%x ",(u_int)constmap[i][1]);
9184 if((regs[i].isconst>>2)&1) printf("edx=%x ",(u_int)constmap[i][2]);
9185 if((regs[i].isconst>>3)&1) printf("ebx=%x ",(u_int)constmap[i][3]);
9186 if((regs[i].isconst>>5)&1) printf("ebp=%x ",(u_int)constmap[i][5]);
9187 if((regs[i].isconst>>6)&1) printf("esi=%x ",(u_int)constmap[i][6]);
9188 if((regs[i].isconst>>7)&1) printf("edi=%x ",(u_int)constmap[i][7]);
57871462 9189 #endif
7c3a5182 9190 #if defined(__arm__) || defined(__aarch64__)
643aeae3 9191 int r;
9192 for (r = 0; r < ARRAY_SIZE(constmap[i]); r++)
9193 if ((regs[i].isconst >> r) & 1)
9194 printf(" r%d=%x", r, (u_int)constmap[i][r]);
57871462 9195 #endif
9196 printf("\n");
9197 }
fe807a8a 9198 if(dops[i].is_jump) {
57871462 9199 #if defined(__i386__) || defined(__x86_64__)
9200 printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d dirty: ",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
9201 if(branch_regs[i].dirty&1) printf("eax ");
9202 if((branch_regs[i].dirty>>1)&1) printf("ecx ");
9203 if((branch_regs[i].dirty>>2)&1) printf("edx ");
9204 if((branch_regs[i].dirty>>3)&1) printf("ebx ");
9205 if((branch_regs[i].dirty>>5)&1) printf("ebp ");
9206 if((branch_regs[i].dirty>>6)&1) printf("esi ");
9207 if((branch_regs[i].dirty>>7)&1) printf("edi ");
9208 #endif
9209 #ifdef __arm__
9210 printf("branch(%d): r0=%d r1=%d r2=%d r3=%d r4=%d r5=%d r6=%d r7=%d r8=%d r9=%d r10=%d r12=%d dirty: ",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[4],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7],branch_regs[i].regmap[8],branch_regs[i].regmap[9],branch_regs[i].regmap[10],branch_regs[i].regmap[12]);
9211 if(branch_regs[i].dirty&1) printf("r0 ");
9212 if((branch_regs[i].dirty>>1)&1) printf("r1 ");
9213 if((branch_regs[i].dirty>>2)&1) printf("r2 ");
9214 if((branch_regs[i].dirty>>3)&1) printf("r3 ");
9215 if((branch_regs[i].dirty>>4)&1) printf("r4 ");
9216 if((branch_regs[i].dirty>>5)&1) printf("r5 ");
9217 if((branch_regs[i].dirty>>6)&1) printf("r6 ");
9218 if((branch_regs[i].dirty>>7)&1) printf("r7 ");
9219 if((branch_regs[i].dirty>>8)&1) printf("r8 ");
9220 if((branch_regs[i].dirty>>9)&1) printf("r9 ");
9221 if((branch_regs[i].dirty>>10)&1) printf("r10 ");
9222 if((branch_regs[i].dirty>>12)&1) printf("r12 ");
9223 #endif
57871462 9224 }
9225 }
d1150cd6 9226#endif // REG_ALLOC_PRINT
57871462 9227
9228 /* Pass 8 - Assembly */
9229 linkcount=0;stubcount=0;
9230 ds=0;is_delayslot=0;
57871462 9231 u_int dirty_pre=0;
d148d265 9232 void *beginning=start_block();
57871462 9233 if((u_int)addr&1) {
9234 ds=1;
9235 pagespan_ds();
9236 }
df4dc2b1 9237 void *instr_addr0_override = NULL;
9ad4d757 9238
9ad4d757 9239 if (start == 0x80030000) {
3968e69e 9240 // nasty hack for the fastbios thing
96186eba 9241 // override block entry to this code
df4dc2b1 9242 instr_addr0_override = out;
9ad4d757 9243 emit_movimm(start,0);
96186eba 9244 // abuse io address var as a flag that we
9245 // have already returned here once
643aeae3 9246 emit_readword(&address,1);
9247 emit_writeword(0,&pcaddr);
9248 emit_writeword(0,&address);
9ad4d757 9249 emit_cmp(0,1);
3968e69e 9250 #ifdef __aarch64__
9251 emit_jeq(out + 4*2);
2a014d73 9252 emit_far_jump(new_dyna_leave);
3968e69e 9253 #else
643aeae3 9254 emit_jne(new_dyna_leave);
3968e69e 9255 #endif
9ad4d757 9256 }
57871462 9257 for(i=0;i<slen;i++)
9258 {
670c0f22 9259 check_regmap(regmap_pre[i]);
9260 check_regmap(regs[i].regmap_entry);
9261 check_regmap(regs[i].regmap);
57871462 9262 //if(ds) printf("ds: ");
4600ba03 9263 disassemble_inst(i);
57871462 9264 if(ds) {
9265 ds=0; // Skip delay slot
cf95b4f0 9266 if(dops[i].bt) assem_debug("OOPS - branch into delay slot\n");
df4dc2b1 9267 instr_addr[i] = NULL;
57871462 9268 } else {
ffb0b9e0 9269 speculate_register_values(i);
57871462 9270 #ifndef DESTRUCTIVE_WRITEBACK
fe807a8a 9271 if (i < 2 || !dops[i-2].is_ujump)
57871462 9272 {
ad49de89 9273 wb_valid(regmap_pre[i],regs[i].regmap_entry,dirty_pre,regs[i].wasdirty,unneeded_reg[i]);
57871462 9274 }
fe807a8a 9275 if((dops[i].itype==CJUMP||dops[i].itype==SJUMP)) {
f776eb14 9276 dirty_pre=branch_regs[i].dirty;
9277 }else{
f776eb14 9278 dirty_pre=regs[i].dirty;
9279 }
57871462 9280 #endif
9281 // write back
fe807a8a 9282 if (i < 2 || !dops[i-2].is_ujump)
57871462 9283 {
ad49de89 9284 wb_invalidate(regmap_pre[i],regs[i].regmap_entry,regs[i].wasdirty,unneeded_reg[i]);
57871462 9285 loop_preload(regmap_pre[i],regs[i].regmap_entry);
9286 }
9287 // branch target entry point
df4dc2b1 9288 instr_addr[i] = out;
57871462 9289 assem_debug("<->\n");
2330734f 9290 drc_dbg_emit_do_cmp(i, ccadj[i]);
7f94b097 9291 if (clear_hack_addr) {
9292 emit_movimm(0, 0);
9293 emit_writeword(0, &hack_addr);
9294 clear_hack_addr = 0;
9295 }
dd114d7d 9296
57871462 9297 // load regs
9298 if(regs[i].regmap_entry[HOST_CCREG]==CCREG&&regs[i].regmap[HOST_CCREG]!=CCREG)
ad49de89 9299 wb_register(CCREG,regs[i].regmap_entry,regs[i].wasdirty);
cf95b4f0 9300 load_regs(regs[i].regmap_entry,regs[i].regmap,dops[i].rs1,dops[i].rs2);
57871462 9301 address_generation(i,&regs[i],regs[i].regmap_entry);
ad49de89 9302 load_consts(regmap_pre[i],regs[i].regmap,i);
fe807a8a 9303 if(dops[i].is_jump)
57871462 9304 {
9305 // Load the delay slot registers if necessary
cf95b4f0 9306 if(dops[i+1].rs1!=dops[i].rs1&&dops[i+1].rs1!=dops[i].rs2&&(dops[i+1].rs1!=dops[i].rt1||dops[i].rt1==0))
9307 load_regs(regs[i].regmap_entry,regs[i].regmap,dops[i+1].rs1,dops[i+1].rs1);
9308 if(dops[i+1].rs2!=dops[i+1].rs1&&dops[i+1].rs2!=dops[i].rs1&&dops[i+1].rs2!=dops[i].rs2&&(dops[i+1].rs2!=dops[i].rt1||dops[i].rt1==0))
9309 load_regs(regs[i].regmap_entry,regs[i].regmap,dops[i+1].rs2,dops[i+1].rs2);
37387d8b 9310 if (ram_offset && (dops[i+1].is_load || dops[i+1].is_store))
9311 load_regs(regs[i].regmap_entry,regs[i].regmap,ROREG,ROREG);
9312 if (dops[i+1].is_store)
ad49de89 9313 load_regs(regs[i].regmap_entry,regs[i].regmap,INVCP,INVCP);
57871462 9314 }
9315 else if(i+1<slen)
9316 {
9317 // Preload registers for following instruction
cf95b4f0 9318 if(dops[i+1].rs1!=dops[i].rs1&&dops[i+1].rs1!=dops[i].rs2)
9319 if(dops[i+1].rs1!=dops[i].rt1&&dops[i+1].rs1!=dops[i].rt2)
9320 load_regs(regs[i].regmap_entry,regs[i].regmap,dops[i+1].rs1,dops[i+1].rs1);
9321 if(dops[i+1].rs2!=dops[i+1].rs1&&dops[i+1].rs2!=dops[i].rs1&&dops[i+1].rs2!=dops[i].rs2)
9322 if(dops[i+1].rs2!=dops[i].rt1&&dops[i+1].rs2!=dops[i].rt2)
9323 load_regs(regs[i].regmap_entry,regs[i].regmap,dops[i+1].rs2,dops[i+1].rs2);
57871462 9324 }
9325 // TODO: if(is_ooo(i)) address_generation(i+1);
9a3ccfeb 9326 if (!dops[i].is_jump || dops[i].itype == CJUMP)
ad49de89 9327 load_regs(regs[i].regmap_entry,regs[i].regmap,CCREG,CCREG);
37387d8b 9328 if (ram_offset && (dops[i].is_load || dops[i].is_store))
9329 load_regs(regs[i].regmap_entry,regs[i].regmap,ROREG,ROREG);
9330 if (dops[i].is_store)
ad49de89 9331 load_regs(regs[i].regmap_entry,regs[i].regmap,INVCP,INVCP);
2330734f 9332
9333 ds = assemble(i, &regs[i], ccadj[i]);
9334
fe807a8a 9335 if (dops[i].is_ujump)
57871462 9336 literal_pool(1024);
9337 else
9338 literal_pool_jumpover(256);
9339 }
9340 }
3d680478 9341
9342 assert(slen > 0);
cf95b4f0 9343 if (slen > 0 && dops[slen-1].itype == INTCALL) {
3d680478 9344 // no ending needed for this block since INTCALL never returns
9345 }
57871462 9346 // If the block did not end with an unconditional branch,
9347 // add a jump to the next instruction.
3d680478 9348 else if (i > 1) {
fe807a8a 9349 if (!dops[i-2].is_ujump && dops[i-1].itype != SPAN) {
9350 assert(!dops[i-1].is_jump);
57871462 9351 assert(i==slen);
cf95b4f0 9352 if(dops[i-2].itype!=CJUMP&&dops[i-2].itype!=SJUMP) {
ad49de89 9353 store_regs_bt(regs[i-1].regmap,regs[i-1].dirty,start+i*4);
57871462 9354 if(regs[i-1].regmap[HOST_CCREG]!=CCREG)
9355 emit_loadreg(CCREG,HOST_CCREG);
2330734f 9356 emit_addimm(HOST_CCREG, ccadj[i-1] + CLOCK_ADJUST(1), HOST_CCREG);
57871462 9357 }
fe807a8a 9358 else
57871462 9359 {
ad49de89 9360 store_regs_bt(branch_regs[i-2].regmap,branch_regs[i-2].dirty,start+i*4);
57871462 9361 assert(branch_regs[i-2].regmap[HOST_CCREG]==CCREG);
9362 }
643aeae3 9363 add_to_linker(out,start+i*4,0);
57871462 9364 emit_jmp(0);
9365 }
9366 }
9367 else
9368 {
9369 assert(i>0);
fe807a8a 9370 assert(!dops[i-1].is_jump);
ad49de89 9371 store_regs_bt(regs[i-1].regmap,regs[i-1].dirty,start+i*4);
57871462 9372 if(regs[i-1].regmap[HOST_CCREG]!=CCREG)
9373 emit_loadreg(CCREG,HOST_CCREG);
2330734f 9374 emit_addimm(HOST_CCREG, ccadj[i-1] + CLOCK_ADJUST(1), HOST_CCREG);
643aeae3 9375 add_to_linker(out,start+i*4,0);
57871462 9376 emit_jmp(0);
9377 }
9378
9379 // TODO: delay slot stubs?
9380 // Stubs
9381 for(i=0;i<stubcount;i++)
9382 {
b14b6a8f 9383 switch(stubs[i].type)
57871462 9384 {
9385 case LOADB_STUB:
9386 case LOADH_STUB:
9387 case LOADW_STUB:
9388 case LOADD_STUB:
9389 case LOADBU_STUB:
9390 case LOADHU_STUB:
9391 do_readstub(i);break;
9392 case STOREB_STUB:
9393 case STOREH_STUB:
9394 case STOREW_STUB:
9395 case STORED_STUB:
9396 do_writestub(i);break;
9397 case CC_STUB:
9398 do_ccstub(i);break;
9399 case INVCODE_STUB:
9400 do_invstub(i);break;
9401 case FP_STUB:
9402 do_cop1stub(i);break;
9403 case STORELR_STUB:
9404 do_unalignedwritestub(i);break;
9405 }
9406 }
9407
9ad4d757 9408 if (instr_addr0_override)
9409 instr_addr[0] = instr_addr0_override;
9410
57871462 9411 /* Pass 9 - Linker */
9412 for(i=0;i<linkcount;i++)
9413 {
643aeae3 9414 assem_debug("%p -> %8x\n",link_addr[i].addr,link_addr[i].target);
57871462 9415 literal_pool(64);
643aeae3 9416 if (!link_addr[i].ext)
57871462 9417 {
643aeae3 9418 void *stub = out;
9419 void *addr = check_addr(link_addr[i].target);
9420 emit_extjump(link_addr[i].addr, link_addr[i].target);
9421 if (addr) {
9422 set_jump_target(link_addr[i].addr, addr);
3d680478 9423 add_jump_out(link_addr[i].target,stub);
57871462 9424 }
643aeae3 9425 else
9426 set_jump_target(link_addr[i].addr, stub);
57871462 9427 }
9428 else
9429 {
9430 // Internal branch
643aeae3 9431 int target=(link_addr[i].target-start)>>2;
57871462 9432 assert(target>=0&&target<slen);
9433 assert(instr_addr[target]);
9434 //#ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
643aeae3 9435 //set_jump_target_fillslot(link_addr[i].addr,instr_addr[target],link_addr[i].ext>>1);
57871462 9436 //#else
643aeae3 9437 set_jump_target(link_addr[i].addr, instr_addr[target]);
57871462 9438 //#endif
9439 }
9440 }
3d680478 9441
9442 u_int source_len = slen*4;
cf95b4f0 9443 if (dops[slen-1].itype == INTCALL && source_len > 4)
3d680478 9444 // no need to treat the last instruction as compiled
9445 // as interpreter fully handles it
9446 source_len -= 4;
9447
9448 if ((u_char *)copy + source_len > (u_char *)shadow + sizeof(shadow))
9449 copy = shadow;
9450
57871462 9451 // External Branch Targets (jump_in)
57871462 9452 for(i=0;i<slen;i++)
9453 {
cf95b4f0 9454 if(dops[i].bt||i==0)
57871462 9455 {
9456 if(instr_addr[i]) // TODO - delay slots (=null)
9457 {
9458 u_int vaddr=start+i*4;
94d23bb9 9459 u_int page=get_page(vaddr);
9460 u_int vpage=get_vpage(vaddr);
57871462 9461 literal_pool(256);
57871462 9462 {
df4dc2b1 9463 assem_debug("%p (%d) <- %8x\n",instr_addr[i],i,start+i*4);
57871462 9464 assem_debug("jump_in: %x\n",start+i*4);
df4dc2b1 9465 ll_add(jump_dirty+vpage,vaddr,out);
3d680478 9466 void *entry_point = do_dirty_stub(i, source_len);
df4dc2b1 9467 ll_add_flags(jump_in+page,vaddr,state_rflags,entry_point);
57871462 9468 // If there was an existing entry in the hash table,
9469 // replace it with the new address.
9470 // Don't add new entries. We'll insert the
9471 // ones that actually get used in check_addr().
df4dc2b1 9472 struct ht_entry *ht_bin = hash_table_get(vaddr);
9473 if (ht_bin->vaddr[0] == vaddr)
9474 ht_bin->tcaddr[0] = entry_point;
9475 if (ht_bin->vaddr[1] == vaddr)
9476 ht_bin->tcaddr[1] = entry_point;
57871462 9477 }
57871462 9478 }
9479 }
9480 }
9481 // Write out the literal pool if necessary
9482 literal_pool(0);
9483 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
9484 // Align code
9485 if(((u_int)out)&7) emit_addnop(13);
9486 #endif
01d26796 9487 assert(out - (u_char *)beginning < MAX_OUTPUT_BLOCK_SIZE);
643aeae3 9488 //printf("shadow buffer: %p-%p\n",copy,(u_char *)copy+slen*4);
3d680478 9489 memcpy(copy, source, source_len);
9490 copy += source_len;
9f51b4b9 9491
d148d265 9492 end_block(beginning);
9f51b4b9 9493
57871462 9494 // If we're within 256K of the end of the buffer,
9495 // start over from the beginning. (Is 256K enough?)
2a014d73 9496 if (out > ndrc->translation_cache + sizeof(ndrc->translation_cache) - MAX_OUTPUT_BLOCK_SIZE)
9497 out = ndrc->translation_cache;
9f51b4b9 9498
57871462 9499 // Trap writes to any of the pages we compiled
9500 for(i=start>>12;i<=(start+slen*4)>>12;i++) {
9501 invalid_code[i]=0;
57871462 9502 }
9be4ba64 9503 inv_code_start=inv_code_end=~0;
71e490c5 9504
b96d3df7 9505 // for PCSX we need to mark all mirrors too
b12c9fb8 9506 if(get_page(start)<(RAM_SIZE>>12))
9507 for(i=start>>12;i<=(start+slen*4)>>12;i++)
b96d3df7 9508 invalid_code[((u_int)0x00000000>>12)|(i&0x1ff)]=
9509 invalid_code[((u_int)0x80000000>>12)|(i&0x1ff)]=
9510 invalid_code[((u_int)0xa0000000>>12)|(i&0x1ff)]=0;
9f51b4b9 9511
57871462 9512 /* Pass 10 - Free memory by expiring oldest blocks */
9f51b4b9 9513
2a014d73 9514 int end=(((out-ndrc->translation_cache)>>(TARGET_SIZE_2-16))+16384)&65535;
57871462 9515 while(expirep!=end)
9516 {
9517 int shift=TARGET_SIZE_2-3; // Divide into 8 blocks
943f42f3 9518 uintptr_t base_offs = ((uintptr_t)(expirep >> 13) << shift); // Base offset of this block
9519 uintptr_t base_offs_s = base_offs >> shift;
57871462 9520 inv_debug("EXP: Phase %d\n",expirep);
9521 switch((expirep>>11)&3)
9522 {
9523 case 0:
9524 // Clear jump_in and jump_dirty
943f42f3 9525 ll_remove_matching_addrs(jump_in+(expirep&2047),base_offs_s,shift);
9526 ll_remove_matching_addrs(jump_dirty+(expirep&2047),base_offs_s,shift);
9527 ll_remove_matching_addrs(jump_in+2048+(expirep&2047),base_offs_s,shift);
9528 ll_remove_matching_addrs(jump_dirty+2048+(expirep&2047),base_offs_s,shift);
57871462 9529 break;
9530 case 1:
9531 // Clear pointers
943f42f3 9532 ll_kill_pointers(jump_out[expirep&2047],base_offs_s,shift);
9533 ll_kill_pointers(jump_out[(expirep&2047)+2048],base_offs_s,shift);
57871462 9534 break;
9535 case 2:
9536 // Clear hash table
9537 for(i=0;i<32;i++) {
df4dc2b1 9538 struct ht_entry *ht_bin = &hash_table[((expirep&2047)<<5)+i];
943f42f3 9539 uintptr_t o1 = (u_char *)ht_bin->tcaddr[1] - ndrc->translation_cache;
9540 uintptr_t o2 = o1 - MAX_OUTPUT_BLOCK_SIZE;
9541 if ((o1 >> shift) == base_offs_s || (o2 >> shift) == base_offs_s) {
df4dc2b1 9542 inv_debug("EXP: Remove hash %x -> %p\n",ht_bin->vaddr[1],ht_bin->tcaddr[1]);
9543 ht_bin->vaddr[1] = -1;
9544 ht_bin->tcaddr[1] = NULL;
9545 }
943f42f3 9546 o1 = (u_char *)ht_bin->tcaddr[0] - ndrc->translation_cache;
9547 o2 = o1 - MAX_OUTPUT_BLOCK_SIZE;
9548 if ((o1 >> shift) == base_offs_s || (o2 >> shift) == base_offs_s) {
df4dc2b1 9549 inv_debug("EXP: Remove hash %x -> %p\n",ht_bin->vaddr[0],ht_bin->tcaddr[0]);
9550 ht_bin->vaddr[0] = ht_bin->vaddr[1];
9551 ht_bin->tcaddr[0] = ht_bin->tcaddr[1];
9552 ht_bin->vaddr[1] = -1;
9553 ht_bin->tcaddr[1] = NULL;
57871462 9554 }
9555 }
9556 break;
9557 case 3:
9558 // Clear jump_out
9f51b4b9 9559 if((expirep&2047)==0)
dd3a91a1 9560 do_clear_cache();
943f42f3 9561 ll_remove_matching_addrs(jump_out+(expirep&2047),base_offs_s,shift);
9562 ll_remove_matching_addrs(jump_out+2048+(expirep&2047),base_offs_s,shift);
57871462 9563 break;
9564 }
9565 expirep=(expirep+1)&65535;
9566 }
37387d8b 9567#ifdef ASSEM_PRINT
9568 fflush(stdout);
9569#endif
57871462 9570 return 0;
9571}
b9b61529 9572
9573// vim:shiftwidth=2:expandtab
ARM optimized PCSX fork