notaz.gp2x.de / pcsx_rearmed.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
drc: handle upto 64k page size
[pcsx_rearmed.git] / libpcsxcore / new_dynarec / new_dynarec.c
CommitLineData
57871462 1/* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
2 * Mupen64plus - new_dynarec.c *
20d507ba 3 * Copyright (C) 2009-2011 Ari64 *
57871462 4 * *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
9 * *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
14 * *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. *
19 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */
20
21#include <stdlib.h>
22#include <stdint.h> //include for uint64_t
23#include <assert.h>
d848b60a 24#include <errno.h>
4600ba03 25#include <sys/mman.h>
899d08bd 26#include <unistd.h>
d148d265 27#ifdef __MACH__
28#include <libkern/OSCacheControl.h>
29#endif
1e212a25 30#ifdef _3DS
31#include <3ds_utils.h>
32#endif
3039c914 33#ifdef HAVE_LIBNX
34#include <switch.h>
35static Jit g_jit;
36#endif
57871462 37
d148d265 38#include "new_dynarec_config.h"
3968e69e 39#include "../psxhle.h"
40#include "../psxinterpreter.h"
de74f599 41#include "../psxcounters.h"
81dbbf4c 42#include "../gte.h"
43#include "emu_if.h" // emulator interface
a5cd72d0 44#include "linkage_offsets.h"
45#include "compiler_features.h"
cdc2da64 46#include "arm_features.h"
57871462 47
b14b6a8f 48#ifndef ARRAY_SIZE
49#define ARRAY_SIZE(x) (sizeof(x) / sizeof(x[0]))
50#endif
e3c6bdb5 51#ifndef min
52#define min(a, b) ((b) < (a) ? (b) : (a))
53#endif
32631e6a 54#ifndef max
55#define max(a, b) ((b) > (a) ? (b) : (a))
56#endif
b14b6a8f 57
4600ba03 58//#define DISASM
32631e6a 59//#define ASSEM_PRINT
a5cd72d0 60//#define REGMAP_PRINT // with DISASM only
9b495f6e 61//#define INV_DEBUG_W
ece032e6 62//#define STAT_PRINT
32631e6a 63
64#ifdef ASSEM_PRINT
65#define assem_debug printf
66#else
4600ba03 67#define assem_debug(...)
32631e6a 68#endif
69//#define inv_debug printf
4600ba03 70#define inv_debug(...)
57871462 71
72#ifdef __i386__
73#include "assem_x86.h"
74#endif
75#ifdef __x86_64__
76#include "assem_x64.h"
77#endif
78#ifdef __arm__
79#include "assem_arm.h"
80#endif
be516ebe 81#ifdef __aarch64__
82#include "assem_arm64.h"
83#endif
57871462 84
81dbbf4c 85#define RAM_SIZE 0x200000
d3201e39 86#define MAXBLOCK 2048
57871462 87#define MAX_OUTPUT_BLOCK_SIZE 262144
93c0345b 88#define EXPIRITY_OFFSET (MAX_OUTPUT_BLOCK_SIZE * 2)
89#define PAGE_COUNT 1024
2573466a 90
882a08fc 91#if defined(HAVE_CONDITIONAL_CALL) && !defined(DESTRUCTIVE_SHIFT)
92#define INVALIDATE_USE_COND_CALL
93#endif
94
66ea165f 95#ifdef VITA
96// apparently Vita has a 16MB limit, so either we cut tc in half,
97// or use this hack (it's a hack because tc size was designed to be power-of-2)
98#define TC_REDUCE_BYTES 4096
99#else
100#define TC_REDUCE_BYTES 0
101#endif
102
d9e2b173 103struct ndrc_tramp
104{
105 struct tramp_insns ops[2048 / sizeof(struct tramp_insns)];
106 const void *f[2048 / sizeof(void *)];
107};
108
2a014d73 109struct ndrc_mem
110{
66ea165f 111 u_char translation_cache[(1 << TARGET_SIZE_2) - TC_REDUCE_BYTES];
d9e2b173 112 struct ndrc_tramp tramp;
2a014d73 113};
114
2a014d73 115static struct ndrc_mem *ndrc;
899d08bd 116#ifndef BASE_ADDR_DYNAMIC
117// reserve .bss space with upto 64k page size in mind
118static char ndrc_bss[((sizeof(*ndrc) + 65535) & ~65535) + 65536];
2a014d73 119#endif
d9e2b173 120#ifdef TC_WRITE_OFFSET
3039c914 121# ifdef __GLIBC__
122# include <sys/types.h>
123# include <sys/stat.h>
124# include <fcntl.h>
3039c914 125# endif
126static long ndrc_write_ofs;
d9e2b173 127#define NDRC_WRITE_OFFSET(x) (void *)((char *)(x) + ndrc_write_ofs)
3039c914 128#else
d9e2b173 129#define NDRC_WRITE_OFFSET(x) (x)
3039c914 130#endif
2a014d73 131
b14b6a8f 132// stubs
133enum stub_type {
134 CC_STUB = 1,
a5cd72d0 135 //FP_STUB = 2,
b14b6a8f 136 LOADB_STUB = 3,
137 LOADH_STUB = 4,
138 LOADW_STUB = 5,
a5cd72d0 139 //LOADD_STUB = 6,
b14b6a8f 140 LOADBU_STUB = 7,
141 LOADHU_STUB = 8,
142 STOREB_STUB = 9,
143 STOREH_STUB = 10,
144 STOREW_STUB = 11,
a5cd72d0 145 //STORED_STUB = 12,
b14b6a8f 146 STORELR_STUB = 13,
147 INVCODE_STUB = 14,
a5cd72d0 148 OVERFLOW_STUB = 15,
277718fa 149 ALIGNMENT_STUB = 16,
b14b6a8f 150};
151
6cc8d23c 152// regmap_pre[i] - regs before [i] insn starts; dirty things here that
153// don't match .regmap will be written back
154// [i].regmap_entry - regs that must be set up if someone jumps here
155// [i].regmap - regs [i] insn will read/(over)write
2acc46cd 156// branch_regs[i].* - same as above but for branches, takes delay slot into account
57871462 157struct regstat
158{
6cc8d23c 159 signed char regmap_entry[HOST_REGS];
57871462 160 signed char regmap[HOST_REGS];
a22ccd6a 161 u_int wasdirty;
162 u_int dirty;
24058131 163 u_int wasconst; // before; for example 'lw r2, (r2)' wasconst is true
a5cd72d0 164 u_int isconst; // ... but isconst is false when r2 is known (hr)
8575a877 165 u_int loadedconst; // host regs that have constants loaded
90f98e7c 166 u_int noevict; // can't evict this hr (alloced by current op)
9b495f6e 167 //u_int waswritten; // MIPS regs that were used as store base before
a22ccd6a 168 uint64_t u;
57871462 169};
170
df4dc2b1 171struct ht_entry
172{
173 u_int vaddr[2];
174 void *tcaddr[2];
175};
176
b14b6a8f 177struct code_stub
178{
179 enum stub_type type;
180 void *addr;
181 void *retaddr;
182 u_int a;
183 uintptr_t b;
184 uintptr_t c;
185 u_int d;
186 u_int e;
187};
188
643aeae3 189struct link_entry
190{
191 void *addr;
192 u_int target;
104df9d3 193 u_int internal;
194};
195
196struct block_info
197{
198 struct block_info *next;
199 const void *source;
200 const void *copy;
201 u_int start; // vaddr of the block start
202 u_int len; // of the whole block source
203 u_int tc_offs;
204 //u_int tc_len;
205 u_int reg_sv_flags;
3280e616 206 u_char is_dirty;
207 u_char inv_near_misses;
104df9d3 208 u_short jump_in_cnt;
209 struct {
210 u_int vaddr;
211 void *addr;
212 } jump_in[0];
643aeae3 213};
214
b7ad2f2c 215struct jump_info
216{
217 int alloc;
218 int count;
219 struct {
220 u_int target_vaddr;
221 void *stub;
222 } e[0];
223};
224
cf95b4f0 225static struct decoded_insn
226{
227 u_char itype;
a5cd72d0 228 u_char opcode; // bits 31-26
229 u_char opcode2; // (depends on opcode)
cf95b4f0 230 u_char rs1;
231 u_char rs2;
232 u_char rt1;
233 u_char rt2;
53dc27f6 234 u_char use_lt1:1;
cf95b4f0 235 u_char bt:1;
cf95b4f0 236 u_char ooo:1;
237 u_char is_ds:1;
fe807a8a 238 u_char is_jump:1;
239 u_char is_ujump:1;
37387d8b 240 u_char is_load:1;
241 u_char is_store:1;
a5cd72d0 242 u_char is_delay_load:1; // is_load + MFC/CFC
243 u_char is_exception:1; // unconditional, also interp. fallback
244 u_char may_except:1; // might generate an exception
f9e9616e 245 u_char ls_type:2; // load/store type (ls_width_type)
cf95b4f0 246} dops[MAXBLOCK];
247
f9e9616e 248enum ls_width_type {
249 LS_8 = 0, LS_16, LS_32, LS_LR
250};
251
277718fa 252static struct compile_info
253{
254 int imm;
255 u_int ba;
256 int ccadj;
257 signed char min_free_regs;
258 signed char addr;
259 signed char reserved[2];
260} cinfo[MAXBLOCK];
261
398d6924 262 static u_char *out;
6d75addf 263 static char invalid_code[0x100000];
104df9d3 264 static struct ht_entry hash_table[65536];
93c0345b 265 static struct block_info *blocks[PAGE_COUNT];
b7ad2f2c 266 static struct jump_info *jumps[PAGE_COUNT];
e2b5e7aa 267 static u_int start;
268 static u_int *source;
bedfea38 269 static uint64_t gte_rs[MAXBLOCK]; // gte: 32 data and 32 ctl regs
270 static uint64_t gte_rt[MAXBLOCK];
271 static uint64_t gte_unneeded[MAXBLOCK];
ffb0b9e0 272 static u_int smrv[32]; // speculated MIPS register values
273 static u_int smrv_strong; // mask or regs that are likely to have correct values
274 static u_int smrv_weak; // same, but somewhat less likely
275 static u_int smrv_strong_next; // same, but after current insn executes
276 static u_int smrv_weak_next;
e2b5e7aa 277 static uint64_t unneeded_reg[MAXBLOCK];
e2b5e7aa 278 static uint64_t branch_unneeded_reg[MAXBLOCK];
6cc8d23c 279 // see 'struct regstat' for a description
2330734f 280 static signed char regmap_pre[MAXBLOCK][HOST_REGS];
40fca85b 281 // contains 'real' consts at [i] insn, but may differ from what's actually
282 // loaded in host reg as 'final' value is always loaded, see get_final_value()
283 static uint32_t current_constmap[HOST_REGS];
284 static uint32_t constmap[MAXBLOCK][HOST_REGS];
956f3129 285 static struct regstat regs[MAXBLOCK];
286 static struct regstat branch_regs[MAXBLOCK];
e2b5e7aa 287 static int slen;
df4dc2b1 288 static void *instr_addr[MAXBLOCK];
643aeae3 289 static struct link_entry link_addr[MAXBLOCK];
e2b5e7aa 290 static int linkcount;
b14b6a8f 291 static struct code_stub stubs[MAXBLOCK*3];
e2b5e7aa 292 static int stubcount;
293 static u_int literals[1024][2];
294 static int literalcount;
295 static int is_delayslot;
e2b5e7aa 296 static char shadow[1048576] __attribute__((aligned(16)));
297 static void *copy;
93c0345b 298 static u_int expirep;
e2b5e7aa 299 static u_int stop_after_jal;
7f94b097 300 static u_int f1_hack;
ece032e6 301#ifdef STAT_PRINT
302 static int stat_bc_direct;
303 static int stat_bc_pre;
304 static int stat_bc_restore;
104df9d3 305 static int stat_ht_lookups;
ece032e6 306 static int stat_jump_in_lookups;
307 static int stat_restore_tries;
308 static int stat_restore_compares;
309 static int stat_inv_addr_calls;
310 static int stat_inv_hits;
104df9d3 311 static int stat_blocks;
312 static int stat_links;
ece032e6 313 #define stat_inc(s) s++
104df9d3 314 #define stat_dec(s) s--
315 #define stat_clear(s) s = 0
ece032e6 316#else
317 #define stat_inc(s)
104df9d3 318 #define stat_dec(s)
319 #define stat_clear(s)
ece032e6 320#endif
e2b5e7aa 321
322 int new_dynarec_hacks;
d62c125a 323 int new_dynarec_hacks_pergame;
32631e6a 324 int new_dynarec_hacks_old;
e2b5e7aa 325 int new_dynarec_did_compile;
687b4580 326
d62c125a 327 #define HACK_ENABLED(x) ((new_dynarec_hacks | new_dynarec_hacks_pergame) & (x))
328
de6dbc52 329 extern int cycle_count; // ... until end of the timeslice, counts -N -> 0 (CCREG)
687b4580 330 extern int last_count; // last absolute target, often = next_interupt
331 extern int pcaddr;
332 extern int pending_exception;
333 extern int branch_target;
37387d8b 334 extern uintptr_t ram_offset;
d1e4ebd9 335 extern uintptr_t mini_ht[32][2];
57871462 336
337 /* registers that may be allocated */
338 /* 1-31 gpr */
7c3a5182 339#define LOREG 32 // lo
340#define HIREG 33 // hi
00fa9369 341//#define FSREG 34 // FPU status (FCSR)
de6dbc52 342//#define CSREG 35 // Coprocessor status
57871462 343#define CCREG 36 // Cycle count
344#define INVCP 37 // Pointer to invalid_code
1edfcc68 345//#define MMREG 38 // Pointer to memory_map
33a1eda1 346#define ROREG 39 // ram offset (if psxM != 0x80000000)
619e5ded 347#define TEMPREG 40
33a1eda1 348#define FTEMP 40 // Load/store temporary register (was fpu)
619e5ded 349#define PTEMP 41 // Prefetch temporary register
1edfcc68 350//#define TLREG 42 // TLB mapping offset
619e5ded 351#define RHASH 43 // Return address hash
352#define RHTBL 44 // Return address hash table address
353#define RTEMP 45 // JR/JALR address register
354#define MAXREG 45
277718fa 355#define AGEN1 46 // Address generation temporary register (pass5b_preallocate2)
1edfcc68 356//#define AGEN2 47 // Address generation temporary register
57871462 357
358 /* instruction types */
359#define NOP 0 // No operation
360#define LOAD 1 // Load
361#define STORE 2 // Store
362#define LOADLR 3 // Unaligned load
363#define STORELR 4 // Unaligned store
a5cd72d0 364#define MOV 5 // Move (hi/lo only)
57871462 365#define ALU 6 // Arithmetic/logic
366#define MULTDIV 7 // Multiply/divide
367#define SHIFT 8 // Shift by register
368#define SHIFTIMM 9// Shift by immediate
369#define IMM16 10 // 16-bit immediate
370#define RJUMP 11 // Unconditional jump to register
371#define UJUMP 12 // Unconditional jump
372#define CJUMP 13 // Conditional branch (BEQ/BNE/BGTZ/BLEZ)
373#define SJUMP 14 // Conditional branch (regimm format)
374#define COP0 15 // Coprocessor 0
a5cd72d0 375#define RFE 16
d1150cd6 376#define SYSCALL 22// SYSCALL,BREAK
a5cd72d0 377#define OTHER 23 // Other/unknown - do nothing
7139f3c8 378#define HLECALL 26// PCSX fake opcodes for HLE
b9b61529 379#define COP2 27 // Coprocessor 2 move
380#define C2LS 28 // Coprocessor 2 load/store
381#define C2OP 29 // Coprocessor 2 operation
1e973cb0 382#define INTCALL 30// Call interpreter to handle rare corner cases
57871462 383
57871462 384 /* branch codes */
385#define TAKEN 1
386#define NOTTAKEN 2
57871462 387
7c3a5182 388#define DJT_1 (void *)1l // no function, just a label in assem_debug log
389#define DJT_2 (void *)2l
390
57871462 391// asm linkage
57871462 392void dyna_linker();
57871462 393void cc_interrupt();
d1150cd6 394void jump_syscall (u_int u0, u_int u1, u_int pc);
395void jump_syscall_ds(u_int u0, u_int u1, u_int pc);
396void jump_break (u_int u0, u_int u1, u_int pc);
397void jump_break_ds(u_int u0, u_int u1, u_int pc);
a5cd72d0 398void jump_overflow (u_int u0, u_int u1, u_int pc);
399void jump_overflow_ds(u_int u0, u_int u1, u_int pc);
277718fa 400void jump_addrerror (u_int cause, u_int addr, u_int pc);
401void jump_addrerror_ds(u_int cause, u_int addr, u_int pc);
3968e69e 402void jump_to_new_pc();
81dbbf4c 403void call_gteStall();
7139f3c8 404void new_dyna_leave();
57871462 405
104df9d3 406void *ndrc_get_addr_ht_param(u_int vaddr, int can_compile);
407void *ndrc_get_addr_ht(u_int vaddr);
104df9d3 408void ndrc_add_jump_out(u_int vaddr, void *src);
9b495f6e 409void ndrc_write_invalidate_one(u_int addr);
410static void ndrc_write_invalidate_many(u_int addr, u_int end);
104df9d3 411
412static int new_recompile_block(u_int addr);
413static void invalidate_block(struct block_info *block);
a5cd72d0 414static void exception_assemble(int i, const struct regstat *i_regs, int ccadj_);
398d6924 415
57871462 416// Needed by assembler
a22ccd6a 417static void wb_register(signed char r, const signed char regmap[], u_int dirty);
418static void wb_dirtys(const signed char i_regmap[], u_int i_dirty);
419static void wb_needed_dirtys(const signed char i_regmap[], u_int i_dirty, int addr);
2330734f 420static void load_all_regs(const signed char i_regmap[]);
421static void load_needed_regs(const signed char i_regmap[], const signed char next_regmap[]);
e2b5e7aa 422static void load_regs_entry(int t);
2330734f 423static void load_all_consts(const signed char regmap[], u_int dirty, int i);
81dbbf4c 424static u_int get_host_reglist(const signed char *regmap);
e2b5e7aa 425
de6dbc52 426static int get_final_value(int hr, int i, u_int *value);
b14b6a8f 427static void add_stub(enum stub_type type, void *addr, void *retaddr,
428 u_int a, uintptr_t b, uintptr_t c, u_int d, u_int e);
429static void add_stub_r(enum stub_type type, void *addr, void *retaddr,
81dbbf4c 430 int i, int addr_reg, const struct regstat *i_regs, int ccadj, u_int reglist);
643aeae3 431static void add_to_linker(void *addr, u_int target, int ext);
687b4580 432static void *get_direct_memhandler(void *table, u_int addr,
433 enum stub_type type, uintptr_t *addr_host);
32631e6a 434static void cop2_do_stall_check(u_int op, int i, const struct regstat *i_regs, u_int reglist);
687b4580 435static void pass_args(int a0, int a1);
2a014d73 436static void emit_far_jump(const void *f);
437static void emit_far_call(const void *f);
57871462 438
9c67c98f 439#ifdef VITA
440#include <psp2/kernel/sysmem.h>
441static int sceBlock;
442// note: this interacts with RetroArch's Vita bootstrap code: bootstrap/vita/sbrk.c
443extern int getVMBlock();
444int _newlib_vm_size_user = sizeof(*ndrc);
445#endif
446
d148d265 447static void mprotect_w_x(void *start, void *end, int is_x)
448{
449#ifdef NO_WRITE_EXEC
1e212a25 450 #if defined(VITA)
451 // *Open* enables write on all memory that was
452 // allocated by sceKernelAllocMemBlockForVM()?
453 if (is_x)
454 sceKernelCloseVMDomain();
455 else
456 sceKernelOpenVMDomain();
3039c914 457 #elif defined(HAVE_LIBNX)
458 Result rc;
d9e2b173 459 // check to avoid the full flush in jitTransitionToExecutable()
460 if (g_jit.type != JitType_CodeMemory) {
461 if (is_x)
462 rc = jitTransitionToExecutable(&g_jit);
463 else
464 rc = jitTransitionToWritable(&g_jit);
465 if (R_FAILED(rc))
466 ;//SysPrintf("jitTransition %d %08x\n", is_x, rc);
467 }
468 #elif defined(TC_WRITE_OFFSET)
3039c914 469 // separated rx and rw areas are always available
1e212a25 470 #else
d148d265 471 u_long mstart = (u_long)start & ~4095ul;
472 u_long mend = (u_long)end;
473 if (mprotect((void *)mstart, mend - mstart,
474 PROT_READ | (is_x ? PROT_EXEC : PROT_WRITE)) != 0)
475 SysPrintf("mprotect(%c) failed: %s\n", is_x ? 'x' : 'w', strerror(errno));
1e212a25 476 #endif
d148d265 477#endif
478}
479
d9e2b173 480static void start_tcache_write(void *start, void *end)
d148d265 481{
482 mprotect_w_x(start, end, 0);
483}
484
485static void end_tcache_write(void *start, void *end)
486{
919981d0 487#if defined(__arm__) || defined(__aarch64__)
d148d265 488 size_t len = (char *)end - (char *)start;
489 #if defined(__BLACKBERRY_QNX__)
490 msync(start, len, MS_SYNC | MS_CACHE_ONLY | MS_INVALIDATE_ICACHE);
491 #elif defined(__MACH__)
492 sys_cache_control(kCacheFunctionPrepareForExecution, start, len);
493 #elif defined(VITA)
1e212a25 494 sceKernelSyncVMDomain(sceBlock, start, len);
495 #elif defined(_3DS)
496 ctr_flush_invalidate_cache();
3039c914 497 #elif defined(HAVE_LIBNX)
d9e2b173 498 if (g_jit.type == JitType_CodeMemory) {
499 armDCacheClean(start, len);
500 armICacheInvalidate((char *)start - ndrc_write_ofs, len);
aaece508 501 // as of v4.2.1 libnx lacks isb
502 __asm__ volatile("isb" ::: "memory");
d9e2b173 503 }
919981d0 504 #elif defined(__aarch64__)
505 // as of 2021, __clear_cache() is still broken on arm64
506 // so here is a custom one :(
507 clear_cache_arm64(start, end);
d148d265 508 #else
509 __clear_cache(start, end);
510 #endif
511 (void)len;
512#endif
513
514 mprotect_w_x(start, end, 1);
515}
516
517static void *start_block(void)
518{
519 u_char *end = out + MAX_OUTPUT_BLOCK_SIZE;
2a014d73 520 if (end > ndrc->translation_cache + sizeof(ndrc->translation_cache))
521 end = ndrc->translation_cache + sizeof(ndrc->translation_cache);
d9e2b173 522 start_tcache_write(NDRC_WRITE_OFFSET(out), NDRC_WRITE_OFFSET(end));
d148d265 523 return out;
524}
525
526static void end_block(void *start)
527{
d9e2b173 528 end_tcache_write(NDRC_WRITE_OFFSET(start), NDRC_WRITE_OFFSET(out));
d148d265 529}
530
af700b41 531#ifdef NDRC_CACHE_FLUSH_ALL
532
533static int needs_clear_cache;
534
535static void mark_clear_cache(void *target)
536{
537 if (!needs_clear_cache) {
d9e2b173 538 start_tcache_write(NDRC_WRITE_OFFSET(ndrc), NDRC_WRITE_OFFSET(ndrc + 1));
af700b41 539 needs_clear_cache = 1;
540 }
541}
542
543static void do_clear_cache(void)
544{
545 if (needs_clear_cache) {
d9e2b173 546 end_tcache_write(NDRC_WRITE_OFFSET(ndrc), NDRC_WRITE_OFFSET(ndrc + 1));
af700b41 547 needs_clear_cache = 0;
548 }
549}
550
551#else
552
919981d0 553// also takes care of w^x mappings when patching code
554static u_int needs_clear_cache[1<<(TARGET_SIZE_2-17)];
555
556static void mark_clear_cache(void *target)
557{
558 uintptr_t offset = (u_char *)target - ndrc->translation_cache;
559 u_int mask = 1u << ((offset >> 12) & 31);
560 if (!(needs_clear_cache[offset >> 17] & mask)) {
d9e2b173 561 char *start = (char *)NDRC_WRITE_OFFSET((uintptr_t)target & ~4095l);
919981d0 562 start_tcache_write(start, start + 4095);
563 needs_clear_cache[offset >> 17] |= mask;
564 }
565}
566
567// Clearing the cache is rather slow on ARM Linux, so mark the areas
568// that need to be cleared, and then only clear these areas once.
569static void do_clear_cache(void)
570{
571 int i, j;
572 for (i = 0; i < (1<<(TARGET_SIZE_2-17)); i++)
573 {
574 u_int bitmap = needs_clear_cache[i];
575 if (!bitmap)
576 continue;
577 for (j = 0; j < 32; j++)
578 {
579 u_char *start, *end;
93c0345b 580 if (!(bitmap & (1u << j)))
919981d0 581 continue;
582
583 start = ndrc->translation_cache + i*131072 + j*4096;
584 end = start + 4095;
585 for (j++; j < 32; j++) {
93c0345b 586 if (!(bitmap & (1u << j)))
919981d0 587 break;
588 end += 4096;
589 }
d9e2b173 590 end_tcache_write(NDRC_WRITE_OFFSET(start), NDRC_WRITE_OFFSET(end));
919981d0 591 }
592 needs_clear_cache[i] = 0;
593 }
594}
595
af700b41 596#endif // NDRC_CACHE_FLUSH_ALL
57871462 597
b6e87b2b 598#define NO_CYCLE_PENALTY_THR 12
599
32631e6a 600int cycle_multiplier_old;
24058131 601static int cycle_multiplier_active;
4e9dcd7f 602
603static int CLOCK_ADJUST(int x)
604{
24058131 605 int m = cycle_multiplier_active;
606 int s = (x >> 31) | 1;
a3203cf4 607 return (x * m + s * 50) / 100;
4e9dcd7f 608}
609
4919de1e 610static int ds_writes_rjump_rs(int i)
611{
ecca05e3 612 return dops[i].rs1 != 0
613 && (dops[i].rs1 == dops[i+1].rt1 || dops[i].rs1 == dops[i+1].rt2
614 || dops[i].rs1 == dops[i].rt1); // overwrites itself - same effect
4919de1e 615}
616
104df9d3 617// psx addr mirror masking (for invalidation)
618static u_int pmmask(u_int vaddr)
619{
620 vaddr &= ~0xe0000000;
621 if (vaddr < 0x01000000)
622 vaddr &= ~0x00e00000; // RAM mirrors
623 return vaddr;
624}
625
94d23bb9 626static u_int get_page(u_int vaddr)
57871462 627{
104df9d3 628 u_int page = pmmask(vaddr) >> 12;
93c0345b 629 if (page >= PAGE_COUNT / 2)
630 page = PAGE_COUNT / 2 + (page & (PAGE_COUNT / 2 - 1));
94d23bb9 631 return page;
632}
633
104df9d3 634// get a page for looking for a block that has vaddr
635// (needed because the block may start in previous page)
636static u_int get_page_prev(u_int vaddr)
d25604ca 637{
104df9d3 638 assert(MAXBLOCK <= (1 << 12));
639 u_int page = get_page(vaddr);
640 if (page & 511)
641 page--;
642 return page;
d25604ca 643}
94d23bb9 644
df4dc2b1 645static struct ht_entry *hash_table_get(u_int vaddr)
646{
647 return &hash_table[((vaddr>>16)^vaddr)&0xFFFF];
648}
649
04714958 650#define HASH_TABLE_BAD 0xbac
651
652static void hash_table_clear(void)
653{
654 struct ht_entry *ht_bin;
655 int i, j;
656 for (i = 0; i < ARRAY_SIZE(hash_table); i++) {
657 for (j = 0; j < ARRAY_SIZE(hash_table[i].vaddr); j++) {
658 hash_table[i].vaddr[j] = ~0;
659 hash_table[i].tcaddr[j] = (void *)(uintptr_t)HASH_TABLE_BAD;
660 }
661 }
662 // don't allow ~0 to hit
663 ht_bin = hash_table_get(~0);
664 for (j = 0; j < ARRAY_SIZE(ht_bin->vaddr); j++)
665 ht_bin->vaddr[j] = 1;
666}
667
104df9d3 668static void hash_table_add(u_int vaddr, void *tcaddr)
df4dc2b1 669{
104df9d3 670 struct ht_entry *ht_bin = hash_table_get(vaddr);
671 assert(tcaddr);
df4dc2b1 672 ht_bin->vaddr[1] = ht_bin->vaddr[0];
673 ht_bin->tcaddr[1] = ht_bin->tcaddr[0];
674 ht_bin->vaddr[0] = vaddr;
675 ht_bin->tcaddr[0] = tcaddr;
676}
677
104df9d3 678static void hash_table_remove(int vaddr)
679{
680 //printf("remove hash: %x\n",vaddr);
681 struct ht_entry *ht_bin = hash_table_get(vaddr);
682 if (ht_bin->vaddr[1] == vaddr) {
04714958 683 ht_bin->vaddr[1] = ~0;
684 ht_bin->tcaddr[1] = (void *)(uintptr_t)HASH_TABLE_BAD;
104df9d3 685 }
686 if (ht_bin->vaddr[0] == vaddr) {
687 ht_bin->vaddr[0] = ht_bin->vaddr[1];
688 ht_bin->tcaddr[0] = ht_bin->tcaddr[1];
04714958 689 ht_bin->vaddr[1] = ~0;
690 ht_bin->tcaddr[1] = (void *)(uintptr_t)HASH_TABLE_BAD;
104df9d3 691 }
692}
693
04714958 694static void mini_ht_clear(void)
695{
696#ifdef USE_MINI_HT
697 int i;
698 for (i = 0; i < ARRAY_SIZE(mini_ht) - 1; i++) {
699 mini_ht[i][0] = ~0;
700 mini_ht[i][1] = HASH_TABLE_BAD;
701 }
702 mini_ht[i][0] = 1;
703 mini_ht[i][1] = HASH_TABLE_BAD;
704#endif
705}
706
104df9d3 707static void mark_invalid_code(u_int vaddr, u_int len, char invalid)
398d6924 708{
ab4377be 709 u_int vaddr_m = vaddr & 0x1fffffff;
398d6924 710 u_int i, j;
ab4377be 711 for (i = vaddr_m & ~0xfff; i < vaddr_m + len; i += 0x1000) {
398d6924 712 // ram mirrors, but should not hurt bios
713 for (j = 0; j < 0x800000; j += 0x200000) {
714 invalid_code[(i|j) >> 12] =
715 invalid_code[(i|j|0x80000000u) >> 12] =
104df9d3 716 invalid_code[(i|j|0xa0000000u) >> 12] = invalid;
398d6924 717 }
718 }
882a08fc 719 if (!invalid && vaddr + len > inv_code_start && vaddr <= inv_code_end)
104df9d3 720 inv_code_start = inv_code_end = ~0;
398d6924 721}
722
93c0345b 723static int doesnt_expire_soon(u_char *tcaddr)
df4dc2b1 724{
93c0345b 725 u_int diff = (u_int)(tcaddr - out) & ((1u << TARGET_SIZE_2) - 1u);
726 return diff > EXPIRITY_OFFSET + MAX_OUTPUT_BLOCK_SIZE;
df4dc2b1 727}
728
9b495f6e 729static unused void check_for_block_changes(u_int start, u_int end)
730{
731 u_int start_page = get_page_prev(start);
732 u_int end_page = get_page(end - 1);
733 u_int page;
734
735 for (page = start_page; page <= end_page; page++) {
736 struct block_info *block;
737 for (block = blocks[page]; block != NULL; block = block->next) {
738 if (block->is_dirty)
739 continue;
740 if (memcmp(block->source, block->copy, block->len)) {
741 printf("bad block %08x-%08x %016llx %016llx @%08x\n",
742 block->start, block->start + block->len,
743 *(long long *)block->source, *(long long *)block->copy, psxRegs.pc);
744 fflush(stdout);
745 abort();
746 }
747 }
748 }
749}
750
104df9d3 751static void *try_restore_block(u_int vaddr, u_int start_page, u_int end_page)
398d6924 752{
104df9d3 753 void *found_clean = NULL;
754 u_int i, page;
398d6924 755
ece032e6 756 stat_inc(stat_restore_tries);
104df9d3 757 for (page = start_page; page <= end_page; page++) {
758 struct block_info *block;
759 for (block = blocks[page]; block != NULL; block = block->next) {
760 if (vaddr < block->start)
761 break;
762 if (!block->is_dirty || vaddr >= block->start + block->len)
763 continue;
764 for (i = 0; i < block->jump_in_cnt; i++)
765 if (block->jump_in[i].vaddr == vaddr)
766 break;
767 if (i == block->jump_in_cnt)
768 continue;
769 assert(block->source && block->copy);
770 stat_inc(stat_restore_compares);
771 if (memcmp(block->source, block->copy, block->len))
772 continue;
398d6924 773
3280e616 774 block->is_dirty = block->inv_near_misses = 0;
104df9d3 775 found_clean = block->jump_in[i].addr;
776 hash_table_add(vaddr, found_clean);
777 mark_invalid_code(block->start, block->len, 0);
778 stat_inc(stat_bc_restore);
779 inv_debug("INV: restored %08x %p (%d)\n", vaddr, found_clean, block->jump_in_cnt);
780 return found_clean;
398d6924 781 }
398d6924 782 }
104df9d3 783 return NULL;
398d6924 784}
785
de6dbc52 786// this doesn't normally happen
787static noinline u_int generate_exception(u_int pc)
788{
789 //if (execBreakCheck(&psxRegs, pc))
790 // return psxRegs.pc;
791
792 // generate an address or bus error
793 psxRegs.CP0.n.Cause &= 0x300;
794 psxRegs.CP0.n.EPC = pc;
795 if (pc & 3) {
796 psxRegs.CP0.n.Cause |= R3000E_AdEL << 2;
797 psxRegs.CP0.n.BadVAddr = pc;
798#ifdef DRC_DBG
799 last_count -= 2;
800#endif
801 } else
802 psxRegs.CP0.n.Cause |= R3000E_IBE << 2;
803 return (psxRegs.pc = 0x80000080);
804}
805
94d23bb9 806// Get address from virtual address
807// This is called from the recompiled JR/JALR instructions
104df9d3 808static void noinline *get_addr(u_int vaddr, int can_compile)
94d23bb9 809{
104df9d3 810 u_int start_page = get_page_prev(vaddr);
811 u_int i, page, end_page = get_page(vaddr);
812 void *found_clean = NULL;
398d6924 813
ece032e6 814 stat_inc(stat_jump_in_lookups);
104df9d3 815 for (page = start_page; page <= end_page; page++) {
816 const struct block_info *block;
817 for (block = blocks[page]; block != NULL; block = block->next) {
818 if (vaddr < block->start)
819 break;
820 if (block->is_dirty || vaddr >= block->start + block->len)
821 continue;
822 for (i = 0; i < block->jump_in_cnt; i++)
823 if (block->jump_in[i].vaddr == vaddr)
824 break;
825 if (i == block->jump_in_cnt)
826 continue;
827 found_clean = block->jump_in[i].addr;
828 hash_table_add(vaddr, found_clean);
829 return found_clean;
57871462 830 }
57871462 831 }
104df9d3 832 found_clean = try_restore_block(vaddr, start_page, end_page);
833 if (found_clean)
834 return found_clean;
835
836 if (!can_compile)
837 return NULL;
398d6924 838
839 int r = new_recompile_block(vaddr);
de6dbc52 840 if (likely(r == 0))
104df9d3 841 return ndrc_get_addr_ht(vaddr);
df4dc2b1 842
de6dbc52 843 return ndrc_get_addr_ht(generate_exception(vaddr));
57871462 844}
104df9d3 845
57871462 846// Look up address in hash table first
104df9d3 847void *ndrc_get_addr_ht_param(u_int vaddr, int can_compile)
57871462 848{
9b495f6e 849 //check_for_block_changes(vaddr, vaddr + MAXBLOCK);
df4dc2b1 850 const struct ht_entry *ht_bin = hash_table_get(vaddr);
277718fa 851 u_int vaddr_a = vaddr & ~3;
104df9d3 852 stat_inc(stat_ht_lookups);
277718fa 853 if (ht_bin->vaddr[0] == vaddr_a) return ht_bin->tcaddr[0];
854 if (ht_bin->vaddr[1] == vaddr_a) return ht_bin->tcaddr[1];
104df9d3 855 return get_addr(vaddr, can_compile);
856}
857
858void *ndrc_get_addr_ht(u_int vaddr)
859{
860 return ndrc_get_addr_ht_param(vaddr, 1);
57871462 861}
862
6cc8d23c 863static void clear_all_regs(signed char regmap[])
57871462 864{
6cc8d23c 865 memset(regmap, -1, sizeof(regmap[0]) * HOST_REGS);
57871462 866}
867
53358c1d 868// get_reg: get allocated host reg from mips reg
869// returns -1 if no such mips reg was allocated
cdc2da64 870#if defined(__arm__) && defined(HAVE_ARMV6) && HOST_REGS == 13 && EXCLUDE_REG == 11
871
872extern signed char get_reg(const signed char regmap[], signed char r);
873
874#else
875
9de8a0c3 876static signed char get_reg(const signed char regmap[], signed char r)
57871462 877{
878 int hr;
9de8a0c3 879 for (hr = 0; hr < HOST_REGS; hr++) {
880 if (hr == EXCLUDE_REG)
881 continue;
882 if (regmap[hr] == r)
883 return hr;
884 }
885 return -1;
886}
887
cdc2da64 888#endif
889
a5cd72d0 890// get reg suitable for writing
891static signed char get_reg_w(const signed char regmap[], signed char r)
892{
893 return r == 0 ? -1 : get_reg(regmap, r);
894}
895
53358c1d 896// get reg as mask bit (1 << hr)
897static u_int get_regm(const signed char regmap[], signed char r)
898{
899 return (1u << (get_reg(regmap, r) & 31)) & ~(1u << 31);
900}
901
9de8a0c3 902static signed char get_reg_temp(const signed char regmap[])
903{
904 int hr;
905 for (hr = 0; hr < HOST_REGS; hr++) {
906 if (hr == EXCLUDE_REG)
907 continue;
908 if (regmap[hr] == (signed char)-1)
909 return hr;
910 }
57871462 911 return -1;
912}
913
914// Find a register that is available for two consecutive cycles
d1e4ebd9 915static signed char get_reg2(signed char regmap1[], const signed char regmap2[], int r)
57871462 916{
917 int hr;
918 for (hr=0;hr<HOST_REGS;hr++) if(hr!=EXCLUDE_REG&&regmap1[hr]==r&&regmap2[hr]==r) return hr;
919 return -1;
920}
921
53dc27f6 922// reverse reg map: mips -> host
923#define RRMAP_SIZE 64
924static void make_rregs(const signed char regmap[], signed char rrmap[RRMAP_SIZE],
925 u_int *regs_can_change)
926{
927 u_int r, hr, hr_can_change = 0;
928 memset(rrmap, -1, RRMAP_SIZE);
929 for (hr = 0; hr < HOST_REGS; )
930 {
931 r = regmap[hr];
932 rrmap[r & (RRMAP_SIZE - 1)] = hr;
933 // only add mips $1-$31+$lo, others shifted out
934 hr_can_change |= (uint64_t)1 << (hr + ((r - 1) & 32));
935 hr++;
936 if (hr == EXCLUDE_REG)
937 hr++;
938 }
939 hr_can_change |= 1u << (rrmap[33] & 31);
940 hr_can_change |= 1u << (rrmap[CCREG] & 31);
941 hr_can_change &= ~(1u << 31);
942 *regs_can_change = hr_can_change;
943}
944
945// same as get_reg, but takes rrmap
946static signed char get_rreg(signed char rrmap[RRMAP_SIZE], signed char r)
947{
948 assert(0 <= r && r < RRMAP_SIZE);
949 return rrmap[r];
950}
951
9de8a0c3 952static int count_free_regs(const signed char regmap[])
57871462 953{
954 int count=0;
955 int hr;
956 for(hr=0;hr<HOST_REGS;hr++)
957 {
958 if(hr!=EXCLUDE_REG) {
959 if(regmap[hr]<0) count++;
960 }
961 }
962 return count;
963}
964
9de8a0c3 965static void dirty_reg(struct regstat *cur, signed char reg)
57871462 966{
967 int hr;
9de8a0c3 968 if (!reg) return;
969 hr = get_reg(cur->regmap, reg);
970 if (hr >= 0)
971 cur->dirty |= 1<<hr;
57871462 972}
973
40fca85b 974static void set_const(struct regstat *cur, signed char reg, uint32_t value)
57871462 975{
976 int hr;
9de8a0c3 977 if (!reg) return;
978 hr = get_reg(cur->regmap, reg);
979 if (hr >= 0) {
980 cur->isconst |= 1<<hr;
981 current_constmap[hr] = value;
57871462 982 }
983}
984
40fca85b 985static void clear_const(struct regstat *cur, signed char reg)
57871462 986{
987 int hr;
9de8a0c3 988 if (!reg) return;
989 hr = get_reg(cur->regmap, reg);
990 if (hr >= 0)
991 cur->isconst &= ~(1<<hr);
57871462 992}
993
9de8a0c3 994static int is_const(const struct regstat *cur, signed char reg)
57871462 995{
996 int hr;
9de8a0c3 997 if (reg < 0) return 0;
998 if (!reg) return 1;
999 hr = get_reg(cur->regmap, reg);
1000 if (hr >= 0)
1001 return (cur->isconst>>hr)&1;
57871462 1002 return 0;
1003}
40fca85b 1004
9de8a0c3 1005static uint32_t get_const(const struct regstat *cur, signed char reg)
57871462 1006{
1007 int hr;
9de8a0c3 1008 if (!reg) return 0;
1009 hr = get_reg(cur->regmap, reg);
1010 if (hr >= 0)
1011 return current_constmap[hr];
1012
1013 SysPrintf("Unknown constant in r%d\n", reg);
7c3a5182 1014 abort();
57871462 1015}
1016
1017// Least soon needed registers
1018// Look at the next ten instructions and see which registers
1019// will be used. Try not to reallocate these.
90f98e7c 1020static void lsn(u_char hsn[], int i)
57871462 1021{
1022 int j;
1023 int b=-1;
1024 for(j=0;j<9;j++)
1025 {
1026 if(i+j>=slen) {
1027 j=slen-i-1;
1028 break;
1029 }
fe807a8a 1030 if (dops[i+j].is_ujump)
57871462 1031 {
1032 // Don't go past an unconditonal jump
1033 j++;
1034 break;
1035 }
1036 }
1037 for(;j>=0;j--)
1038 {
cf95b4f0 1039 if(dops[i+j].rs1) hsn[dops[i+j].rs1]=j;
1040 if(dops[i+j].rs2) hsn[dops[i+j].rs2]=j;
1041 if(dops[i+j].rt1) hsn[dops[i+j].rt1]=j;
1042 if(dops[i+j].rt2) hsn[dops[i+j].rt2]=j;
1043 if(dops[i+j].itype==STORE || dops[i+j].itype==STORELR) {
57871462 1044 // Stores can allocate zero
cf95b4f0 1045 hsn[dops[i+j].rs1]=j;
1046 hsn[dops[i+j].rs2]=j;
57871462 1047 }
37387d8b 1048 if (ram_offset && (dops[i+j].is_load || dops[i+j].is_store))
1049 hsn[ROREG] = j;
57871462 1050 // On some architectures stores need invc_ptr
1051 #if defined(HOST_IMM8)
37387d8b 1052 if (dops[i+j].is_store)
1053 hsn[INVCP] = j;
57871462 1054 #endif
cf95b4f0 1055 if(i+j>=0&&(dops[i+j].itype==UJUMP||dops[i+j].itype==CJUMP||dops[i+j].itype==SJUMP))
57871462 1056 {
1057 hsn[CCREG]=j;
1058 b=j;
1059 }
1060 }
1061 if(b>=0)
1062 {
277718fa 1063 if(cinfo[i+b].ba>=start && cinfo[i+b].ba<(start+slen*4))
57871462 1064 {
1065 // Follow first branch
277718fa 1066 int t=(cinfo[i+b].ba-start)>>2;
57871462 1067 j=7-b;if(t+j>=slen) j=slen-t-1;
1068 for(;j>=0;j--)
1069 {
cf95b4f0 1070 if(dops[t+j].rs1) if(hsn[dops[t+j].rs1]>j+b+2) hsn[dops[t+j].rs1]=j+b+2;
1071 if(dops[t+j].rs2) if(hsn[dops[t+j].rs2]>j+b+2) hsn[dops[t+j].rs2]=j+b+2;
1072 //if(dops[t+j].rt1) if(hsn[dops[t+j].rt1]>j+b+2) hsn[dops[t+j].rt1]=j+b+2;
1073 //if(dops[t+j].rt2) if(hsn[dops[t+j].rt2]>j+b+2) hsn[dops[t+j].rt2]=j+b+2;
57871462 1074 }
1075 }
1076 // TODO: preferred register based on backward branch
1077 }
1078 // Delay slot should preferably not overwrite branch conditions or cycle count
fe807a8a 1079 if (i > 0 && dops[i-1].is_jump) {
cf95b4f0 1080 if(dops[i-1].rs1) if(hsn[dops[i-1].rs1]>1) hsn[dops[i-1].rs1]=1;
1081 if(dops[i-1].rs2) if(hsn[dops[i-1].rs2]>1) hsn[dops[i-1].rs2]=1;
57871462 1082 hsn[CCREG]=1;
1083 // ...or hash tables
1084 hsn[RHASH]=1;
1085 hsn[RHTBL]=1;
1086 }
1087 // Coprocessor load/store needs FTEMP, even if not declared
37387d8b 1088 if(dops[i].itype==C2LS) {
57871462 1089 hsn[FTEMP]=0;
1090 }
33a1eda1 1091 // Load/store L/R also uses FTEMP as a temporary register
1092 if (dops[i].itype == LOADLR || dops[i].itype == STORELR) {
57871462 1093 hsn[FTEMP]=0;
1094 }
57871462 1095 // Don't remove the miniht registers
cf95b4f0 1096 if(dops[i].itype==UJUMP||dops[i].itype==RJUMP)
57871462 1097 {
1098 hsn[RHASH]=0;
1099 hsn[RHTBL]=0;
1100 }
1101}
1102
1103// We only want to allocate registers if we're going to use them again soon
4149788d 1104static int needed_again(int r, int i)
57871462 1105{
1106 int j;
1107 int b=-1;
1108 int rn=10;
9f51b4b9 1109
fe807a8a 1110 if (i > 0 && dops[i-1].is_ujump)
57871462 1111 {
277718fa 1112 if(cinfo[i-1].ba<start || cinfo[i-1].ba>start+slen*4-4)
57871462 1113 return 0; // Don't need any registers if exiting the block
1114 }
1115 for(j=0;j<9;j++)
1116 {
1117 if(i+j>=slen) {
1118 j=slen-i-1;
1119 break;
1120 }
fe807a8a 1121 if (dops[i+j].is_ujump)
57871462 1122 {
1123 // Don't go past an unconditonal jump
1124 j++;
1125 break;
1126 }
a5cd72d0 1127 if (dops[i+j].is_exception)
57871462 1128 {
1129 break;
1130 }
1131 }
1132 for(;j>=1;j--)
1133 {
cf95b4f0 1134 if(dops[i+j].rs1==r) rn=j;
1135 if(dops[i+j].rs2==r) rn=j;
57871462 1136 if((unneeded_reg[i+j]>>r)&1) rn=10;
cf95b4f0 1137 if(i+j>=0&&(dops[i+j].itype==UJUMP||dops[i+j].itype==CJUMP||dops[i+j].itype==SJUMP))
57871462 1138 {
1139 b=j;
1140 }
1141 }
b7217e13 1142 if(rn<10) return 1;
581335b0 1143 (void)b;
57871462 1144 return 0;
1145}
1146
1147// Try to match register allocations at the end of a loop with those
1148// at the beginning
4149788d 1149static int loop_reg(int i, int r, int hr)
57871462 1150{
1151 int j,k;
1152 for(j=0;j<9;j++)
1153 {
1154 if(i+j>=slen) {
1155 j=slen-i-1;
1156 break;
1157 }
fe807a8a 1158 if (dops[i+j].is_ujump)
57871462 1159 {
1160 // Don't go past an unconditonal jump
1161 j++;
1162 break;
1163 }
1164 }
1165 k=0;
1166 if(i>0){
cf95b4f0 1167 if(dops[i-1].itype==UJUMP||dops[i-1].itype==CJUMP||dops[i-1].itype==SJUMP)
57871462 1168 k--;
1169 }
1170 for(;k<j;k++)
1171 {
00fa9369 1172 assert(r < 64);
1173 if((unneeded_reg[i+k]>>r)&1) return hr;
cf95b4f0 1174 if(i+k>=0&&(dops[i+k].itype==UJUMP||dops[i+k].itype==CJUMP||dops[i+k].itype==SJUMP))
57871462 1175 {
277718fa 1176 if(cinfo[i+k].ba>=start && cinfo[i+k].ba<(start+i*4))
57871462 1177 {
277718fa 1178 int t=(cinfo[i+k].ba-start)>>2;
57871462 1179 int reg=get_reg(regs[t].regmap_entry,r);
1180 if(reg>=0) return reg;
1181 //reg=get_reg(regs[t+1].regmap_entry,r);
1182 //if(reg>=0) return reg;
1183 }
1184 }
1185 }
1186 return hr;
1187}
1188
1189
1190// Allocate every register, preserving source/target regs
4149788d 1191static void alloc_all(struct regstat *cur,int i)
57871462 1192{
1193 int hr;
9f51b4b9 1194
57871462 1195 for(hr=0;hr<HOST_REGS;hr++) {
1196 if(hr!=EXCLUDE_REG) {
9de8a0c3 1197 if((cur->regmap[hr]!=dops[i].rs1)&&(cur->regmap[hr]!=dops[i].rs2)&&
1198 (cur->regmap[hr]!=dops[i].rt1)&&(cur->regmap[hr]!=dops[i].rt2))
57871462 1199 {
1200 cur->regmap[hr]=-1;
1201 cur->dirty&=~(1<<hr);
1202 }
1203 // Don't need zeros
9de8a0c3 1204 if(cur->regmap[hr]==0)
57871462 1205 {
1206 cur->regmap[hr]=-1;
1207 cur->dirty&=~(1<<hr);
1208 }
1209 }
1210 }
1211}
1212
d1e4ebd9 1213#ifndef NDEBUG
1214static int host_tempreg_in_use;
1215
1216static void host_tempreg_acquire(void)
1217{
1218 assert(!host_tempreg_in_use);
1219 host_tempreg_in_use = 1;
1220}
1221
1222static void host_tempreg_release(void)
1223{
1224 host_tempreg_in_use = 0;
1225}
1226#else
1227static void host_tempreg_acquire(void) {}
1228static void host_tempreg_release(void) {}
1229#endif
1230
32631e6a 1231#ifdef ASSEM_PRINT
8062d65a 1232extern void gen_interupt();
1233extern void do_insn_cmp();
d1e4ebd9 1234#define FUNCNAME(f) { f, " " #f }
8062d65a 1235static const struct {
d1e4ebd9 1236 void *addr;
8062d65a 1237 const char *name;
1238} function_names[] = {
1239 FUNCNAME(cc_interrupt),
1240 FUNCNAME(gen_interupt),
104df9d3 1241 FUNCNAME(ndrc_get_addr_ht),
8062d65a 1242 FUNCNAME(jump_handler_read8),
1243 FUNCNAME(jump_handler_read16),
1244 FUNCNAME(jump_handler_read32),
1245 FUNCNAME(jump_handler_write8),
1246 FUNCNAME(jump_handler_write16),
1247 FUNCNAME(jump_handler_write32),
9b495f6e 1248 FUNCNAME(ndrc_write_invalidate_one),
1249 FUNCNAME(ndrc_write_invalidate_many),
3968e69e 1250 FUNCNAME(jump_to_new_pc),
d1150cd6 1251 FUNCNAME(jump_break),
1252 FUNCNAME(jump_break_ds),
1253 FUNCNAME(jump_syscall),
1254 FUNCNAME(jump_syscall_ds),
a5cd72d0 1255 FUNCNAME(jump_overflow),
1256 FUNCNAME(jump_overflow_ds),
277718fa 1257 FUNCNAME(jump_addrerror),
1258 FUNCNAME(jump_addrerror_ds),
81dbbf4c 1259 FUNCNAME(call_gteStall),
8062d65a 1260 FUNCNAME(new_dyna_leave),
1261 FUNCNAME(pcsx_mtc0),
1262 FUNCNAME(pcsx_mtc0_ds),
277718fa 1263 FUNCNAME(execI),
1264#ifdef __aarch64__
1265 FUNCNAME(do_memhandler_pre),
1266 FUNCNAME(do_memhandler_post),
1267#endif
32631e6a 1268#ifdef DRC_DBG
33a1eda1 1269# ifdef __aarch64__
1270 FUNCNAME(do_insn_cmp_arm64),
1271# else
8062d65a 1272 FUNCNAME(do_insn_cmp),
33a1eda1 1273# endif
32631e6a 1274#endif
8062d65a 1275};
1276
d1e4ebd9 1277static const char *func_name(const void *a)
8062d65a 1278{
1279 int i;
1280 for (i = 0; i < sizeof(function_names)/sizeof(function_names[0]); i++)
1281 if (function_names[i].addr == a)
1282 return function_names[i].name;
1283 return "";
1284}
a5cd72d0 1285
1286static const char *fpofs_name(u_int ofs)
1287{
1288 u_int *p = (u_int *)&dynarec_local + ofs/sizeof(u_int);
1289 static char buf[64];
1290 switch (ofs) {
1291 #define ofscase(x) case LO_##x: return " ; " #x
1292 ofscase(next_interupt);
de6dbc52 1293 ofscase(cycle_count);
a5cd72d0 1294 ofscase(last_count);
1295 ofscase(pending_exception);
1296 ofscase(stop);
1297 ofscase(address);
1298 ofscase(lo);
1299 ofscase(hi);
1300 ofscase(PC);
1301 ofscase(cycle);
1302 ofscase(mem_rtab);
1303 ofscase(mem_wtab);
1304 ofscase(psxH_ptr);
1305 ofscase(invc_ptr);
1306 ofscase(ram_offset);
1307 #undef ofscase
1308 }
1309 buf[0] = 0;
1310 if (psxRegs.GPR.r <= p && p < &psxRegs.GPR.r[32])
1311 snprintf(buf, sizeof(buf), " ; r%d", (int)(p - psxRegs.GPR.r));
1312 else if (psxRegs.CP0.r <= p && p < &psxRegs.CP0.r[32])
1313 snprintf(buf, sizeof(buf), " ; cp0 $%d", (int)(p - psxRegs.CP0.r));
1314 else if (psxRegs.CP2D.r <= p && p < &psxRegs.CP2D.r[32])
1315 snprintf(buf, sizeof(buf), " ; cp2d $%d", (int)(p - psxRegs.CP2D.r));
1316 else if (psxRegs.CP2C.r <= p && p < &psxRegs.CP2C.r[32])
1317 snprintf(buf, sizeof(buf), " ; cp2c $%d", (int)(p - psxRegs.CP2C.r));
1318 return buf;
1319}
8062d65a 1320#else
1321#define func_name(x) ""
a5cd72d0 1322#define fpofs_name(x) ""
8062d65a 1323#endif
1324
57871462 1325#ifdef __i386__
1326#include "assem_x86.c"
1327#endif
1328#ifdef __x86_64__
1329#include "assem_x64.c"
1330#endif
1331#ifdef __arm__
1332#include "assem_arm.c"
1333#endif
be516ebe 1334#ifdef __aarch64__
1335#include "assem_arm64.c"
1336#endif
57871462 1337
2a014d73 1338static void *get_trampoline(const void *f)
1339{
d9e2b173 1340 struct ndrc_tramp *tramp = NDRC_WRITE_OFFSET(&ndrc->tramp);
2a014d73 1341 size_t i;
1342
d9e2b173 1343 for (i = 0; i < ARRAY_SIZE(tramp->f); i++) {
1344 if (tramp->f[i] == f || tramp->f[i] == NULL)
2a014d73 1345 break;
1346 }
d9e2b173 1347 if (i == ARRAY_SIZE(tramp->f)) {
2a014d73 1348 SysPrintf("trampoline table is full, last func %p\n", f);
1349 abort();
1350 }
d9e2b173 1351 if (tramp->f[i] == NULL) {
1352 start_tcache_write(&tramp->f[i], &tramp->f[i + 1]);
1353 tramp->f[i] = f;
1354 end_tcache_write(&tramp->f[i], &tramp->f[i + 1]);
1355#ifdef HAVE_LIBNX
1356 // invalidate the RX mirror (unsure if necessary, but just in case...)
1357 armDCacheFlush(&ndrc->tramp.f[i], sizeof(ndrc->tramp.f[i]));
1358#endif
2a014d73 1359 }
1360 return &ndrc->tramp.ops[i];
1361}
1362
1363static void emit_far_jump(const void *f)
1364{
1365 if (can_jump_or_call(f)) {
1366 emit_jmp(f);
1367 return;
1368 }
1369
1370 f = get_trampoline(f);
1371 emit_jmp(f);
1372}
1373
1374static void emit_far_call(const void *f)
1375{
1376 if (can_jump_or_call(f)) {
1377 emit_call(f);
1378 return;
1379 }
1380
1381 f = get_trampoline(f);
1382 emit_call(f);
1383}
1384
57871462 1385// Check if an address is already compiled
1386// but don't return addresses which are about to expire from the cache
4149788d 1387static void *check_addr(u_int vaddr)
57871462 1388{
df4dc2b1 1389 struct ht_entry *ht_bin = hash_table_get(vaddr);
1390 size_t i;
b14b6a8f 1391 for (i = 0; i < ARRAY_SIZE(ht_bin->vaddr); i++) {
df4dc2b1 1392 if (ht_bin->vaddr[i] == vaddr)
93c0345b 1393 if (doesnt_expire_soon(ht_bin->tcaddr[i]))
104df9d3 1394 return ht_bin->tcaddr[i];
57871462 1395 }
104df9d3 1396
1397 // refactor to get_addr_nocompile?
1398 u_int start_page = get_page_prev(vaddr);
1399 u_int page, end_page = get_page(vaddr);
1400
1401 stat_inc(stat_jump_in_lookups);
1402 for (page = start_page; page <= end_page; page++) {
1403 const struct block_info *block;
1404 for (block = blocks[page]; block != NULL; block = block->next) {
1405 if (vaddr < block->start)
1406 break;
1407 if (block->is_dirty || vaddr >= block->start + block->len)
1408 continue;
1409 if (!doesnt_expire_soon(ndrc->translation_cache + block->tc_offs))
1410 continue;
1411 for (i = 0; i < block->jump_in_cnt; i++)
1412 if (block->jump_in[i].vaddr == vaddr)
1413 break;
1414 if (i == block->jump_in_cnt)
1415 continue;
1416
1417 // Update existing entry with current address
1418 void *addr = block->jump_in[i].addr;
1419 if (ht_bin->vaddr[0] == vaddr) {
1420 ht_bin->tcaddr[0] = addr;
1421 return addr;
1422 }
1423 if (ht_bin->vaddr[1] == vaddr) {
1424 ht_bin->tcaddr[1] = addr;
1425 return addr;
1426 }
1427 // Insert into hash table with low priority.
1428 // Don't evict existing entries, as they are probably
1429 // addresses that are being accessed frequently.
1430 if (ht_bin->vaddr[0] == -1) {
1431 ht_bin->vaddr[0] = vaddr;
1432 ht_bin->tcaddr[0] = addr;
57871462 1433 }
104df9d3 1434 else if (ht_bin->vaddr[1] == -1) {
1435 ht_bin->vaddr[1] = vaddr;
1436 ht_bin->tcaddr[1] = addr;
1437 }
1438 return addr;
57871462 1439 }
57871462 1440 }
104df9d3 1441 return NULL;
57871462 1442}
1443
104df9d3 1444static void blocks_clear(struct block_info **head)
1445{
1446 struct block_info *cur, *next;
1447
1448 if ((cur = *head)) {
1449 *head = NULL;
1450 while (cur) {
1451 next = cur->next;
1452 free(cur);
1453 cur = next;
1454 }
1455 }
1456}
1457
93c0345b 1458static int blocks_remove_matching_addrs(struct block_info **head,
1459 u_int base_offs, int shift)
104df9d3 1460{
1461 struct block_info *next;
93c0345b 1462 int hit = 0;
104df9d3 1463 while (*head) {
93c0345b 1464 if ((((*head)->tc_offs ^ base_offs) >> shift) == 0) {
9b495f6e 1465 inv_debug("EXP: rm block %08x (tc_offs %x)\n", (*head)->start, (*head)->tc_offs);
104df9d3 1466 invalidate_block(*head);
1467 next = (*head)->next;
1468 free(*head);
1469 *head = next;
1470 stat_dec(stat_blocks);
93c0345b 1471 hit = 1;
104df9d3 1472 }
1473 else
1474 {
1475 head = &((*head)->next);
1476 }
1477 }
93c0345b 1478 return hit;
104df9d3 1479}
57871462 1480
1481// This is called when we write to a compiled block (see do_invstub)
b7ad2f2c 1482static void unlink_jumps_vaddr_range(u_int start, u_int end)
57871462 1483{
104df9d3 1484 u_int page, start_page = get_page(start), end_page = get_page(end - 1);
b7ad2f2c 1485 int i;
104df9d3 1486
1487 for (page = start_page; page <= end_page; page++) {
b7ad2f2c 1488 struct jump_info *ji = jumps[page];
1489 if (ji == NULL)
1490 continue;
1491 for (i = 0; i < ji->count; ) {
1492 if (ji->e[i].target_vaddr < start || ji->e[i].target_vaddr >= end) {
1493 i++;
104df9d3 1494 continue;
1495 }
b7ad2f2c 1496
1497 inv_debug("INV: rm link to %08x (tc_offs %zx)\n", ji->e[i].target_vaddr,
1498 (u_char *)ji->e[i].stub - ndrc->translation_cache);
1499 void *host_addr = find_extjump_insn(ji->e[i].stub);
104df9d3 1500 mark_clear_cache(host_addr);
b7ad2f2c 1501 set_jump_target(host_addr, ji->e[i].stub); // point back to dyna_linker stub
104df9d3 1502
104df9d3 1503 stat_dec(stat_links);
b7ad2f2c 1504 ji->count--;
1505 if (i < ji->count) {
1506 ji->e[i] = ji->e[ji->count];
1507 continue;
1508 }
1509 i++;
1510 }
1511 }
1512}
1513
1514static void unlink_jumps_tc_range(struct jump_info *ji, u_int base_offs, int shift)
1515{
1516 int i;
1517 if (ji == NULL)
1518 return;
1519 for (i = 0; i < ji->count; ) {
1520 u_int tc_offs = (u_char *)ji->e[i].stub - ndrc->translation_cache;
1521 if (((tc_offs ^ base_offs) >> shift) != 0) {
1522 i++;
1523 continue;
1524 }
1525
9b495f6e 1526 inv_debug("EXP: rm link to %08x (tc_offs %x)\n", ji->e[i].target_vaddr, tc_offs);
b7ad2f2c 1527 stat_dec(stat_links);
1528 ji->count--;
1529 if (i < ji->count) {
1530 ji->e[i] = ji->e[ji->count];
1531 continue;
104df9d3 1532 }
b7ad2f2c 1533 i++;
57871462 1534 }
104df9d3 1535}
9f51b4b9 1536
104df9d3 1537static void invalidate_block(struct block_info *block)
1538{
1539 u_int i;
f76eeef9 1540
104df9d3 1541 block->is_dirty = 1;
b7ad2f2c 1542 unlink_jumps_vaddr_range(block->start, block->start + block->len);
104df9d3 1543 for (i = 0; i < block->jump_in_cnt; i++)
1544 hash_table_remove(block->jump_in[i].vaddr);
57871462 1545}
9be4ba64 1546
104df9d3 1547static int invalidate_range(u_int start, u_int end,
1548 u32 *inv_start_ret, u32 *inv_end_ret)
9be4ba64 1549{
3280e616 1550 struct block_info *last_block = NULL;
104df9d3 1551 u_int start_page = get_page_prev(start);
1552 u_int end_page = get_page(end - 1);
1553 u_int start_m = pmmask(start);
ab4377be 1554 u_int end_m = pmmask(end - 1);
104df9d3 1555 u_int inv_start, inv_end;
1556 u_int blk_start_m, blk_end_m;
1557 u_int page;
1558 int hit = 0;
1559
1560 // additional area without code (to supplement invalid_code[]), [start, end)
9b495f6e 1561 // avoids excessive ndrc_write_invalidate*() calls
104df9d3 1562 inv_start = start_m & ~0xfff;
1563 inv_end = end_m | 0xfff;
1564
1565 for (page = start_page; page <= end_page; page++) {
1566 struct block_info *block;
1567 for (block = blocks[page]; block != NULL; block = block->next) {
1568 if (block->is_dirty)
1569 continue;
3280e616 1570 last_block = block;
104df9d3 1571 blk_end_m = pmmask(block->start + block->len);
1572 if (blk_end_m <= start_m) {
1573 inv_start = max(inv_start, blk_end_m);
1574 continue;
1575 }
1576 blk_start_m = pmmask(block->start);
1577 if (end_m <= blk_start_m) {
1578 inv_end = min(inv_end, blk_start_m - 1);
1579 continue;
9be4ba64 1580 }
104df9d3 1581 if (!block->source) // "hack" block - leave it alone
1582 continue;
1583
1584 hit++;
1585 invalidate_block(block);
1586 stat_inc(stat_inv_hits);
9be4ba64 1587 }
9be4ba64 1588 }
104df9d3 1589
3280e616 1590 if (!hit && last_block && last_block->source) {
1591 // could be some leftover unused block, uselessly trapping writes
1592 last_block->inv_near_misses++;
1593 if (last_block->inv_near_misses > 128) {
1594 invalidate_block(last_block);
1595 stat_inc(stat_inv_hits);
1596 hit++;
1597 }
1598 }
104df9d3 1599 if (hit) {
1600 do_clear_cache();
04714958 1601 mini_ht_clear();
104df9d3 1602 }
3280e616 1603
104df9d3 1604 if (inv_start <= (start_m & ~0xfff) && inv_end >= (start_m | 0xfff))
1605 // the whole page is empty now
1606 mark_invalid_code(start, 1, 1);
1607
1608 if (inv_start_ret) *inv_start_ret = inv_start | (start & 0xe0000000);
1609 if (inv_end_ret) *inv_end_ret = inv_end | (end & 0xe0000000);
1610 return hit;
9be4ba64 1611}
1612
104df9d3 1613void new_dynarec_invalidate_range(unsigned int start, unsigned int end)
1614{
1615 invalidate_range(start, end, NULL, NULL);
1616}
1617
9b495f6e 1618static void ndrc_write_invalidate_many(u_int start, u_int end)
57871462 1619{
9be4ba64 1620 // this check is done by the caller
1621 //if (inv_code_start<=addr&&addr<=inv_code_end) { rhits++; return; }
9b495f6e 1622 int ret = invalidate_range(start, end, &inv_code_start, &inv_code_end);
1623#ifdef INV_DEBUG_W
1624 int invc = invalid_code[start >> 12];
1625 u_int len = end - start;
104df9d3 1626 if (ret)
9b495f6e 1627 printf("INV ADDR: %08x/%02x hit %d blocks\n", start, len, ret);
104df9d3 1628 else
9b495f6e 1629 printf("INV ADDR: %08x/%02x miss, inv %08x-%08x invc %d->%d\n", start, len,
1630 inv_code_start, inv_code_end, invc, invalid_code[start >> 12]);
1631 check_for_block_changes(start, end);
1632#endif
ece032e6 1633 stat_inc(stat_inv_addr_calls);
9b495f6e 1634 (void)ret;
1635}
1636
1637void ndrc_write_invalidate_one(u_int addr)
1638{
1639 ndrc_write_invalidate_many(addr, addr + 4);
57871462 1640}
9be4ba64 1641
dd3a91a1 1642// This is called when loading a save state.
1643// Anything could have changed, so invalidate everything.
104df9d3 1644void new_dynarec_invalidate_all_pages(void)
57871462 1645{
104df9d3 1646 struct block_info *block;
581335b0 1647 u_int page;
104df9d3 1648 for (page = 0; page < ARRAY_SIZE(blocks); page++) {
1649 for (block = blocks[page]; block != NULL; block = block->next) {
1650 if (block->is_dirty)
1651 continue;
1652 if (!block->source) // hack block?
1653 continue;
1654 invalidate_block(block);
1655 }
1656 }
1657
919981d0 1658 do_clear_cache();
04714958 1659 mini_ht_clear();
57871462 1660}
1661
1662// Add an entry to jump_out after making a link
104df9d3 1663// src should point to code by emit_extjump()
b7ad2f2c 1664void ndrc_add_jump_out(u_int vaddr, void *src)
57871462 1665{
b7ad2f2c 1666 inv_debug("ndrc_add_jump_out: %p -> %x\n", src, vaddr);
1667 u_int page = get_page(vaddr);
1668 struct jump_info *ji;
1669
104df9d3 1670 stat_inc(stat_links);
b7ad2f2c 1671 check_extjump2(src);
1672 ji = jumps[page];
1673 if (ji == NULL) {
1674 ji = malloc(sizeof(*ji) + sizeof(ji->e[0]) * 16);
1675 ji->alloc = 16;
1676 ji->count = 0;
1677 }
1678 else if (ji->count >= ji->alloc) {
1679 ji->alloc += 16;
1680 ji = realloc(ji, sizeof(*ji) + sizeof(ji->e[0]) * ji->alloc);
1681 }
1682 jumps[page] = ji;
1683 ji->e[ji->count].target_vaddr = vaddr;
1684 ji->e[ji->count].stub = src;
1685 ji->count++;
57871462 1686}
1687
8062d65a 1688/* Register allocation */
1689
90f98e7c 1690static void alloc_set(struct regstat *cur, int reg, int hr)
1691{
1692 cur->regmap[hr] = reg;
1693 cur->dirty &= ~(1u << hr);
1694 cur->isconst &= ~(1u << hr);
1695 cur->noevict |= 1u << hr;
1696}
1697
1698static void evict_alloc_reg(struct regstat *cur, int i, int reg, int preferred_hr)
1699{
1700 u_char hsn[MAXREG+1];
1701 int j, r, hr;
1702 memset(hsn, 10, sizeof(hsn));
1703 lsn(hsn, i);
1704 //printf("hsn(%x): %d %d %d %d %d %d %d\n",start+i*4,hsn[cur->regmap[0]&63],hsn[cur->regmap[1]&63],hsn[cur->regmap[2]&63],hsn[cur->regmap[3]&63],hsn[cur->regmap[5]&63],hsn[cur->regmap[6]&63],hsn[cur->regmap[7]&63]);
1705 if(i>0) {
1706 // Don't evict the cycle count at entry points, otherwise the entry
1707 // stub will have to write it.
1708 if(dops[i].bt&&hsn[CCREG]>2) hsn[CCREG]=2;
1709 if (i>1 && hsn[CCREG] > 2 && dops[i-2].is_jump) hsn[CCREG]=2;
1710 for(j=10;j>=3;j--)
1711 {
1712 // Alloc preferred register if available
1713 if (!((cur->noevict >> preferred_hr) & 1)
1714 && hsn[cur->regmap[preferred_hr]] == j)
1715 {
1716 alloc_set(cur, reg, preferred_hr);
1717 return;
1718 }
1719 for(r=1;r<=MAXREG;r++)
1720 {
1721 if(hsn[r]==j&&r!=dops[i-1].rs1&&r!=dops[i-1].rs2&&r!=dops[i-1].rt1&&r!=dops[i-1].rt2) {
1722 for(hr=0;hr<HOST_REGS;hr++) {
1723 if (hr == EXCLUDE_REG || ((cur->noevict >> hr) & 1))
1724 continue;
1725 if(hr!=HOST_CCREG||j<hsn[CCREG]) {
1726 if(cur->regmap[hr]==r) {
1727 alloc_set(cur, reg, hr);
1728 return;
1729 }
1730 }
1731 }
1732 }
1733 }
1734 }
1735 }
1736 for(j=10;j>=0;j--)
1737 {
1738 for(r=1;r<=MAXREG;r++)
1739 {
1740 if(hsn[r]==j) {
1741 for(hr=0;hr<HOST_REGS;hr++) {
1742 if (hr == EXCLUDE_REG || ((cur->noevict >> hr) & 1))
1743 continue;
1744 if(cur->regmap[hr]==r) {
1745 alloc_set(cur, reg, hr);
1746 return;
1747 }
1748 }
1749 }
1750 }
1751 }
1752 SysPrintf("This shouldn't happen (evict_alloc_reg)\n");
1753 abort();
1754}
1755
8062d65a 1756// Note: registers are allocated clean (unmodified state)
1757// if you intend to modify the register, you must call dirty_reg().
1758static void alloc_reg(struct regstat *cur,int i,signed char reg)
1759{
1760 int r,hr;
b7ec323c 1761 int preferred_reg = PREFERRED_REG_FIRST
1762 + reg % (PREFERRED_REG_LAST - PREFERRED_REG_FIRST + 1);
1763 if (reg == CCREG) preferred_reg = HOST_CCREG;
1764 if (reg == PTEMP || reg == FTEMP) preferred_reg = 12;
1765 assert(PREFERRED_REG_FIRST != EXCLUDE_REG && EXCLUDE_REG != HOST_REGS);
53358c1d 1766 assert(reg >= 0);
8062d65a 1767
1768 // Don't allocate unused registers
1769 if((cur->u>>reg)&1) return;
1770
1771 // see if it's already allocated
90f98e7c 1772 if ((hr = get_reg(cur->regmap, reg)) >= 0) {
1773 cur->noevict |= 1u << hr;
53358c1d 1774 return;
90f98e7c 1775 }
8062d65a 1776
1777 // Keep the same mapping if the register was already allocated in a loop
1778 preferred_reg = loop_reg(i,reg,preferred_reg);
1779
1780 // Try to allocate the preferred register
90f98e7c 1781 if (cur->regmap[preferred_reg] == -1) {
1782 alloc_set(cur, reg, preferred_reg);
8062d65a 1783 return;
1784 }
1785 r=cur->regmap[preferred_reg];
1786 assert(r < 64);
1787 if((cur->u>>r)&1) {
90f98e7c 1788 alloc_set(cur, reg, preferred_reg);
8062d65a 1789 return;
1790 }
1791
1792 // Clear any unneeded registers
1793 // We try to keep the mapping consistent, if possible, because it
1794 // makes branches easier (especially loops). So we try to allocate
1795 // first (see above) before removing old mappings. If this is not
1796 // possible then go ahead and clear out the registers that are no
1797 // longer needed.
1798 for(hr=0;hr<HOST_REGS;hr++)
1799 {
1800 r=cur->regmap[hr];
1801 if(r>=0) {
1802 assert(r < 64);
1803 if((cur->u>>r)&1) {cur->regmap[hr]=-1;break;}
1804 }
1805 }
b7ec323c 1806
8062d65a 1807 // Try to allocate any available register, but prefer
1808 // registers that have not been used recently.
b7ec323c 1809 if (i > 0) {
1810 for (hr = PREFERRED_REG_FIRST; ; ) {
1811 if (cur->regmap[hr] < 0) {
1812 int oldreg = regs[i-1].regmap[hr];
1813 if (oldreg < 0 || (oldreg != dops[i-1].rs1 && oldreg != dops[i-1].rs2
1814 && oldreg != dops[i-1].rt1 && oldreg != dops[i-1].rt2))
1815 {
90f98e7c 1816 alloc_set(cur, reg, hr);
8062d65a 1817 return;
1818 }
1819 }
b7ec323c 1820 hr++;
1821 if (hr == EXCLUDE_REG)
1822 hr++;
1823 if (hr == HOST_REGS)
1824 hr = 0;
1825 if (hr == PREFERRED_REG_FIRST)
1826 break;
8062d65a 1827 }
1828 }
b7ec323c 1829
8062d65a 1830 // Try to allocate any available register
b7ec323c 1831 for (hr = PREFERRED_REG_FIRST; ; ) {
1832 if (cur->regmap[hr] < 0) {
90f98e7c 1833 alloc_set(cur, reg, hr);
8062d65a 1834 return;
1835 }
b7ec323c 1836 hr++;
1837 if (hr == EXCLUDE_REG)
1838 hr++;
1839 if (hr == HOST_REGS)
1840 hr = 0;
1841 if (hr == PREFERRED_REG_FIRST)
1842 break;
8062d65a 1843 }
1844
1845 // Ok, now we have to evict someone
1846 // Pick a register we hopefully won't need soon
90f98e7c 1847 evict_alloc_reg(cur, i, reg, preferred_reg);
8062d65a 1848}
1849
1850// Allocate a temporary register. This is done without regard to
1851// dirty status or whether the register we request is on the unneeded list
1852// Note: This will only allocate one register, even if called multiple times
1853static void alloc_reg_temp(struct regstat *cur,int i,signed char reg)
1854{
1855 int r,hr;
8062d65a 1856
1857 // see if it's already allocated
90f98e7c 1858 for (hr = 0; hr < HOST_REGS; hr++)
8062d65a 1859 {
90f98e7c 1860 if (hr != EXCLUDE_REG && cur->regmap[hr] == reg) {
1861 cur->noevict |= 1u << hr;
1862 return;
1863 }
8062d65a 1864 }
1865
1866 // Try to allocate any available register
1867 for(hr=HOST_REGS-1;hr>=0;hr--) {
1868 if(hr!=EXCLUDE_REG&&cur->regmap[hr]==-1) {
90f98e7c 1869 alloc_set(cur, reg, hr);
8062d65a 1870 return;
1871 }
1872 }
1873
1874 // Find an unneeded register
1875 for(hr=HOST_REGS-1;hr>=0;hr--)
1876 {
1877 r=cur->regmap[hr];
1878 if(r>=0) {
1879 assert(r < 64);
1880 if((cur->u>>r)&1) {
1881 if(i==0||((unneeded_reg[i-1]>>r)&1)) {
90f98e7c 1882 alloc_set(cur, reg, hr);
8062d65a 1883 return;
1884 }
1885 }
1886 }
1887 }
1888
1889 // Ok, now we have to evict someone
1890 // Pick a register we hopefully won't need soon
90f98e7c 1891 evict_alloc_reg(cur, i, reg, 0);
8062d65a 1892}
1893
ad49de89 1894static void mov_alloc(struct regstat *current,int i)
57871462 1895{
cf95b4f0 1896 if (dops[i].rs1 == HIREG || dops[i].rs1 == LOREG) {
9a3ccfeb 1897 alloc_cc(current,i); // for stalls
1898 dirty_reg(current,CCREG);
32631e6a 1899 }
1900
57871462 1901 // Note: Don't need to actually alloc the source registers
cf95b4f0 1902 //alloc_reg(current,i,dops[i].rs1);
1903 alloc_reg(current,i,dops[i].rt1);
ad49de89 1904
cf95b4f0 1905 clear_const(current,dops[i].rs1);
1906 clear_const(current,dops[i].rt1);
1907 dirty_reg(current,dops[i].rt1);
57871462 1908}
1909
ad49de89 1910static void shiftimm_alloc(struct regstat *current,int i)
57871462 1911{
cf95b4f0 1912 if(dops[i].opcode2<=0x3) // SLL/SRL/SRA
57871462 1913 {
cf95b4f0 1914 if(dops[i].rt1) {
1915 if(dops[i].rs1&&needed_again(dops[i].rs1,i)) alloc_reg(current,i,dops[i].rs1);
53dc27f6 1916 else dops[i].use_lt1=!!dops[i].rs1;
cf95b4f0 1917 alloc_reg(current,i,dops[i].rt1);
1918 dirty_reg(current,dops[i].rt1);
1919 if(is_const(current,dops[i].rs1)) {
1920 int v=get_const(current,dops[i].rs1);
277718fa 1921 if(dops[i].opcode2==0x00) set_const(current,dops[i].rt1,v<<cinfo[i].imm);
1922 if(dops[i].opcode2==0x02) set_const(current,dops[i].rt1,(u_int)v>>cinfo[i].imm);
1923 if(dops[i].opcode2==0x03) set_const(current,dops[i].rt1,v>>cinfo[i].imm);
dc49e339 1924 }
cf95b4f0 1925 else clear_const(current,dops[i].rt1);
57871462 1926 }
1927 }
dc49e339 1928 else
1929 {
cf95b4f0 1930 clear_const(current,dops[i].rs1);
1931 clear_const(current,dops[i].rt1);
dc49e339 1932 }
1933
cf95b4f0 1934 if(dops[i].opcode2>=0x38&&dops[i].opcode2<=0x3b) // DSLL/DSRL/DSRA
57871462 1935 {
9c45ca93 1936 assert(0);
57871462 1937 }
cf95b4f0 1938 if(dops[i].opcode2==0x3c) // DSLL32
57871462 1939 {
9c45ca93 1940 assert(0);
57871462 1941 }
cf95b4f0 1942 if(dops[i].opcode2==0x3e) // DSRL32
57871462 1943 {
9c45ca93 1944 assert(0);
57871462 1945 }
cf95b4f0 1946 if(dops[i].opcode2==0x3f) // DSRA32
57871462 1947 {
9c45ca93 1948 assert(0);
57871462 1949 }
1950}
1951
ad49de89 1952static void shift_alloc(struct regstat *current,int i)
57871462 1953{
cf95b4f0 1954 if(dops[i].rt1) {
cf95b4f0 1955 if(dops[i].rs1) alloc_reg(current,i,dops[i].rs1);
1956 if(dops[i].rs2) alloc_reg(current,i,dops[i].rs2);
1957 alloc_reg(current,i,dops[i].rt1);
1958 if(dops[i].rt1==dops[i].rs2) {
e1190b87 1959 alloc_reg_temp(current,i,-1);
277718fa 1960 cinfo[i].min_free_regs=1;
e1190b87 1961 }
cf95b4f0 1962 clear_const(current,dops[i].rs1);
1963 clear_const(current,dops[i].rs2);
1964 clear_const(current,dops[i].rt1);
1965 dirty_reg(current,dops[i].rt1);
57871462 1966 }
1967}
1968
ad49de89 1969static void alu_alloc(struct regstat *current,int i)
57871462 1970{
cf95b4f0 1971 if(dops[i].opcode2>=0x20&&dops[i].opcode2<=0x23) { // ADD/ADDU/SUB/SUBU
1972 if(dops[i].rt1) {
1973 if(dops[i].rs1&&dops[i].rs2) {
1974 alloc_reg(current,i,dops[i].rs1);
1975 alloc_reg(current,i,dops[i].rs2);
57871462 1976 }
1977 else {
cf95b4f0 1978 if(dops[i].rs1&&needed_again(dops[i].rs1,i)) alloc_reg(current,i,dops[i].rs1);
1979 if(dops[i].rs2&&needed_again(dops[i].rs2,i)) alloc_reg(current,i,dops[i].rs2);
57871462 1980 }
cf95b4f0 1981 alloc_reg(current,i,dops[i].rt1);
57871462 1982 }
277718fa 1983 if (dops[i].may_except) {
90f98e7c 1984 alloc_cc_optional(current, i); // for exceptions
277718fa 1985 alloc_reg_temp(current, i, -1);
1986 cinfo[i].min_free_regs = 1;
a5cd72d0 1987 }
57871462 1988 }
277718fa 1989 else if(dops[i].opcode2==0x2a||dops[i].opcode2==0x2b) { // SLT/SLTU
cf95b4f0 1990 if(dops[i].rt1) {
1991 alloc_reg(current,i,dops[i].rs1);
1992 alloc_reg(current,i,dops[i].rs2);
1993 alloc_reg(current,i,dops[i].rt1);
57871462 1994 }
57871462 1995 }
277718fa 1996 else if(dops[i].opcode2>=0x24&&dops[i].opcode2<=0x27) { // AND/OR/XOR/NOR
cf95b4f0 1997 if(dops[i].rt1) {
1998 if(dops[i].rs1&&dops[i].rs2) {
1999 alloc_reg(current,i,dops[i].rs1);
2000 alloc_reg(current,i,dops[i].rs2);
57871462 2001 }
2002 else
2003 {
cf95b4f0 2004 if(dops[i].rs1&&needed_again(dops[i].rs1,i)) alloc_reg(current,i,dops[i].rs1);
2005 if(dops[i].rs2&&needed_again(dops[i].rs2,i)) alloc_reg(current,i,dops[i].rs2);
57871462 2006 }
cf95b4f0 2007 alloc_reg(current,i,dops[i].rt1);
57871462 2008 }
2009 }
cf95b4f0 2010 clear_const(current,dops[i].rs1);
2011 clear_const(current,dops[i].rs2);
2012 clear_const(current,dops[i].rt1);
2013 dirty_reg(current,dops[i].rt1);
57871462 2014}
2015
ad49de89 2016static void imm16_alloc(struct regstat *current,int i)
57871462 2017{
cf95b4f0 2018 if(dops[i].rs1&&needed_again(dops[i].rs1,i)) alloc_reg(current,i,dops[i].rs1);
53dc27f6 2019 else dops[i].use_lt1=!!dops[i].rs1;
cf95b4f0 2020 if(dops[i].rt1) alloc_reg(current,i,dops[i].rt1);
a5cd72d0 2021 if(dops[i].opcode==0x0a||dops[i].opcode==0x0b) { // SLTI/SLTIU
cf95b4f0 2022 clear_const(current,dops[i].rs1);
2023 clear_const(current,dops[i].rt1);
57871462 2024 }
cf95b4f0 2025 else if(dops[i].opcode>=0x0c&&dops[i].opcode<=0x0e) { // ANDI/ORI/XORI
2026 if(is_const(current,dops[i].rs1)) {
2027 int v=get_const(current,dops[i].rs1);
277718fa 2028 if(dops[i].opcode==0x0c) set_const(current,dops[i].rt1,v&cinfo[i].imm);
2029 if(dops[i].opcode==0x0d) set_const(current,dops[i].rt1,v|cinfo[i].imm);
2030 if(dops[i].opcode==0x0e) set_const(current,dops[i].rt1,v^cinfo[i].imm);
57871462 2031 }
cf95b4f0 2032 else clear_const(current,dops[i].rt1);
57871462 2033 }
cf95b4f0 2034 else if(dops[i].opcode==0x08||dops[i].opcode==0x09) { // ADDI/ADDIU
2035 if(is_const(current,dops[i].rs1)) {
2036 int v=get_const(current,dops[i].rs1);
277718fa 2037 set_const(current,dops[i].rt1,v+cinfo[i].imm);
57871462 2038 }
cf95b4f0 2039 else clear_const(current,dops[i].rt1);
277718fa 2040 if (dops[i].may_except) {
90f98e7c 2041 alloc_cc_optional(current, i); // for exceptions
277718fa 2042 alloc_reg_temp(current, i, -1);
2043 cinfo[i].min_free_regs = 1;
a5cd72d0 2044 }
57871462 2045 }
2046 else {
277718fa 2047 set_const(current,dops[i].rt1,cinfo[i].imm<<16); // LUI
57871462 2048 }
cf95b4f0 2049 dirty_reg(current,dops[i].rt1);
57871462 2050}
2051
ad49de89 2052static void load_alloc(struct regstat *current,int i)
57871462 2053{
277718fa 2054 int need_temp = 0;
cf95b4f0 2055 clear_const(current,dops[i].rt1);
2056 //if(dops[i].rs1!=dops[i].rt1&&needed_again(dops[i].rs1,i)) clear_const(current,dops[i].rs1); // Does this help or hurt?
2057 if(!dops[i].rs1) current->u&=~1LL; // Allow allocating r0 if it's the source register
37387d8b 2058 if (needed_again(dops[i].rs1, i))
2059 alloc_reg(current, i, dops[i].rs1);
2060 if (ram_offset)
2061 alloc_reg(current, i, ROREG);
277718fa 2062 if (dops[i].may_except) {
90f98e7c 2063 alloc_cc_optional(current, i); // for exceptions
277718fa 2064 need_temp = 1;
2065 }
cf95b4f0 2066 if(dops[i].rt1&&!((current->u>>dops[i].rt1)&1)) {
2067 alloc_reg(current,i,dops[i].rt1);
a5cd72d0 2068 assert(get_reg_w(current->regmap, dops[i].rt1)>=0);
cf95b4f0 2069 dirty_reg(current,dops[i].rt1);
57871462 2070 // LWL/LWR need a temporary register for the old value
cf95b4f0 2071 if(dops[i].opcode==0x22||dops[i].opcode==0x26)
57871462 2072 {
2073 alloc_reg(current,i,FTEMP);
277718fa 2074 need_temp = 1;
57871462 2075 }
2076 }
2077 else
2078 {
373d1d07 2079 // Load to r0 or unneeded register (dummy load)
57871462 2080 // but we still need a register to calculate the address
cf95b4f0 2081 if(dops[i].opcode==0x22||dops[i].opcode==0x26)
535d208a 2082 alloc_reg(current,i,FTEMP); // LWL/LWR need another temporary
277718fa 2083 need_temp = 1;
2084 }
2085 if (need_temp) {
2086 alloc_reg_temp(current, i, -1);
2087 cinfo[i].min_free_regs = 1;
57871462 2088 }
2089}
2090
90f98e7c 2091// this may eat up to 7 registers
2092static void store_alloc(struct regstat *current, int i)
57871462 2093{
cf95b4f0 2094 clear_const(current,dops[i].rs2);
2095 if(!(dops[i].rs2)) current->u&=~1LL; // Allow allocating r0 if necessary
2096 if(needed_again(dops[i].rs1,i)) alloc_reg(current,i,dops[i].rs1);
2097 alloc_reg(current,i,dops[i].rs2);
37387d8b 2098 if (ram_offset)
2099 alloc_reg(current, i, ROREG);
57871462 2100 #if defined(HOST_IMM8)
2101 // On CPUs without 32-bit immediates we need a pointer to invalid_code
37387d8b 2102 alloc_reg(current, i, INVCP);
57871462 2103 #endif
277718fa 2104 if (dops[i].opcode == 0x2a || dops[i].opcode == 0x2e) { // SWL/SWL
57871462 2105 alloc_reg(current,i,FTEMP);
2106 }
90f98e7c 2107 if (dops[i].may_except)
2108 alloc_cc_optional(current, i); // for exceptions
57871462 2109 // We need a temporary register for address generation
2110 alloc_reg_temp(current,i,-1);
277718fa 2111 cinfo[i].min_free_regs=1;
57871462 2112}
2113
90f98e7c 2114static void c2ls_alloc(struct regstat *current, int i)
b9b61529 2115{
cf95b4f0 2116 clear_const(current,dops[i].rt1);
2117 if(needed_again(dops[i].rs1,i)) alloc_reg(current,i,dops[i].rs1);
b9b61529 2118 alloc_reg(current,i,FTEMP);
37387d8b 2119 if (ram_offset)
2120 alloc_reg(current, i, ROREG);
b9b61529 2121 #if defined(HOST_IMM8)
2122 // On CPUs without 32-bit immediates we need a pointer to invalid_code
37387d8b 2123 if (dops[i].opcode == 0x3a) // SWC2
b9b61529 2124 alloc_reg(current,i,INVCP);
2125 #endif
90f98e7c 2126 if (dops[i].may_except)
2127 alloc_cc_optional(current, i); // for exceptions
b9b61529 2128 // We need a temporary register for address generation
2129 alloc_reg_temp(current,i,-1);
277718fa 2130 cinfo[i].min_free_regs=1;
b9b61529 2131}
2132
57871462 2133#ifndef multdiv_alloc
4149788d 2134static void multdiv_alloc(struct regstat *current,int i)
57871462 2135{
2136 // case 0x18: MULT
2137 // case 0x19: MULTU
2138 // case 0x1A: DIV
2139 // case 0x1B: DIVU
cf95b4f0 2140 clear_const(current,dops[i].rs1);
2141 clear_const(current,dops[i].rs2);
32631e6a 2142 alloc_cc(current,i); // for stalls
90f98e7c 2143 dirty_reg(current,CCREG);
4ee246ed 2144 current->u &= ~(1ull << HIREG);
2145 current->u &= ~(1ull << LOREG);
2146 alloc_reg(current, i, HIREG);
2147 alloc_reg(current, i, LOREG);
2148 dirty_reg(current, HIREG);
2149 dirty_reg(current, LOREG);
2150 if ((dops[i].opcode2 & 0x3e) == 0x1a || (dops[i].rs1 && dops[i].rs2)) // div(u)
57871462 2151 {
4ee246ed 2152 alloc_reg(current, i, dops[i].rs1);
2153 alloc_reg(current, i, dops[i].rs2);
57871462 2154 }
4ee246ed 2155 // else multiply by zero is zero
57871462 2156}
2157#endif
2158
4149788d 2159static void cop0_alloc(struct regstat *current,int i)
57871462 2160{
cf95b4f0 2161 if(dops[i].opcode2==0) // MFC0
57871462 2162 {
cf95b4f0 2163 if(dops[i].rt1) {
2164 clear_const(current,dops[i].rt1);
cf95b4f0 2165 alloc_reg(current,i,dops[i].rt1);
2166 dirty_reg(current,dops[i].rt1);
57871462 2167 }
2168 }
cf95b4f0 2169 else if(dops[i].opcode2==4) // MTC0
57871462 2170 {
de6dbc52 2171 if (((source[i]>>11)&0x1e) == 12) {
2172 alloc_cc(current, i);
2173 dirty_reg(current, CCREG);
2174 }
cf95b4f0 2175 if(dops[i].rs1){
2176 clear_const(current,dops[i].rs1);
2177 alloc_reg(current,i,dops[i].rs1);
57871462 2178 alloc_all(current,i);
2179 }
2180 else {
2181 alloc_all(current,i); // FIXME: Keep r0
2182 current->u&=~1LL;
2183 alloc_reg(current,i,0);
2184 }
277718fa 2185 cinfo[i].min_free_regs = HOST_REGS;
57871462 2186 }
a5cd72d0 2187}
2188
2189static void rfe_alloc(struct regstat *current, int i)
2190{
2191 alloc_all(current, i);
277718fa 2192 cinfo[i].min_free_regs = HOST_REGS;
57871462 2193}
2194
81dbbf4c 2195static void cop2_alloc(struct regstat *current,int i)
57871462 2196{
cf95b4f0 2197 if (dops[i].opcode2 < 3) // MFC2/CFC2
57871462 2198 {
81dbbf4c 2199 alloc_cc(current,i); // for stalls
2200 dirty_reg(current,CCREG);
cf95b4f0 2201 if(dops[i].rt1){
2202 clear_const(current,dops[i].rt1);
2203 alloc_reg(current,i,dops[i].rt1);
2204 dirty_reg(current,dops[i].rt1);
57871462 2205 }
57871462 2206 }
cf95b4f0 2207 else if (dops[i].opcode2 > 3) // MTC2/CTC2
57871462 2208 {
cf95b4f0 2209 if(dops[i].rs1){
2210 clear_const(current,dops[i].rs1);
2211 alloc_reg(current,i,dops[i].rs1);
57871462 2212 }
2213 else {
2214 current->u&=~1LL;
2215 alloc_reg(current,i,0);
57871462 2216 }
2217 }
81dbbf4c 2218 alloc_reg_temp(current,i,-1);
277718fa 2219 cinfo[i].min_free_regs=1;
57871462 2220}
00fa9369 2221
4149788d 2222static void c2op_alloc(struct regstat *current,int i)
b9b61529 2223{
81dbbf4c 2224 alloc_cc(current,i); // for stalls
2225 dirty_reg(current,CCREG);
b9b61529 2226 alloc_reg_temp(current,i,-1);
2227}
57871462 2228
4149788d 2229static void syscall_alloc(struct regstat *current,int i)
57871462 2230{
2231 alloc_cc(current,i);
2232 dirty_reg(current,CCREG);
2233 alloc_all(current,i);
277718fa 2234 cinfo[i].min_free_regs=HOST_REGS;
57871462 2235 current->isconst=0;
2236}
2237
4149788d 2238static void delayslot_alloc(struct regstat *current,int i)
57871462 2239{
cf95b4f0 2240 switch(dops[i].itype) {
57871462 2241 case UJUMP:
2242 case CJUMP:
2243 case SJUMP:
2244 case RJUMP:
57871462 2245 case SYSCALL:
7139f3c8 2246 case HLECALL:
57871462 2247 case IMM16:
2248 imm16_alloc(current,i);
2249 break;
2250 case LOAD:
2251 case LOADLR:
2252 load_alloc(current,i);
2253 break;
2254 case STORE:
2255 case STORELR:
2256 store_alloc(current,i);
2257 break;
2258 case ALU:
2259 alu_alloc(current,i);
2260 break;
2261 case SHIFT:
2262 shift_alloc(current,i);
2263 break;
2264 case MULTDIV:
2265 multdiv_alloc(current,i);
2266 break;
2267 case SHIFTIMM:
2268 shiftimm_alloc(current,i);
2269 break;
2270 case MOV:
2271 mov_alloc(current,i);
2272 break;
2273 case COP0:
2274 cop0_alloc(current,i);
2275 break;
a5cd72d0 2276 case RFE:
2277 rfe_alloc(current,i);
81dbbf4c 2278 break;
b9b61529 2279 case COP2:
81dbbf4c 2280 cop2_alloc(current,i);
57871462 2281 break;
b9b61529 2282 case C2LS:
2283 c2ls_alloc(current,i);
2284 break;
b9b61529 2285 case C2OP:
2286 c2op_alloc(current,i);
2287 break;
57871462 2288 }
2289}
2290
b14b6a8f 2291static void add_stub(enum stub_type type, void *addr, void *retaddr,
2292 u_int a, uintptr_t b, uintptr_t c, u_int d, u_int e)
2293{
d1e4ebd9 2294 assert(stubcount < ARRAY_SIZE(stubs));
b14b6a8f 2295 stubs[stubcount].type = type;
2296 stubs[stubcount].addr = addr;
2297 stubs[stubcount].retaddr = retaddr;
2298 stubs[stubcount].a = a;
2299 stubs[stubcount].b = b;
2300 stubs[stubcount].c = c;
2301 stubs[stubcount].d = d;
2302 stubs[stubcount].e = e;
57871462 2303 stubcount++;
2304}
2305
b14b6a8f 2306static void add_stub_r(enum stub_type type, void *addr, void *retaddr,
81dbbf4c 2307 int i, int addr_reg, const struct regstat *i_regs, int ccadj, u_int reglist)
b14b6a8f 2308{
2309 add_stub(type, addr, retaddr, i, addr_reg, (uintptr_t)i_regs, ccadj, reglist);
2310}
2311
57871462 2312// Write out a single register
a22ccd6a 2313static void wb_register(signed char r, const signed char regmap[], u_int dirty)
57871462 2314{
2315 int hr;
2316 for(hr=0;hr<HOST_REGS;hr++) {
2317 if(hr!=EXCLUDE_REG) {
9de8a0c3 2318 if(regmap[hr]==r) {
57871462 2319 if((dirty>>hr)&1) {
ad49de89 2320 assert(regmap[hr]<64);
2321 emit_storereg(r,hr);
57871462 2322 }
a22ccd6a 2323 break;
57871462 2324 }
2325 }
2326 }
2327}
2328
8062d65a 2329static void wb_valid(signed char pre[],signed char entry[],u_int dirty_pre,u_int dirty,uint64_t u)
2330{
2331 //if(dirty_pre==dirty) return;
53358c1d 2332 int hr, r;
2333 for (hr = 0; hr < HOST_REGS; hr++) {
2334 r = pre[hr];
2335 if (r < 1 || r > 33 || ((u >> r) & 1))
2336 continue;
2337 if (((dirty_pre & ~dirty) >> hr) & 1)
2338 emit_storereg(r, hr);
8062d65a 2339 }
2340}
2341
687b4580 2342// trashes r2
2343static void pass_args(int a0, int a1)
2344{
2345 if(a0==1&&a1==0) {
2346 // must swap
2347 emit_mov(a0,2); emit_mov(a1,1); emit_mov(2,0);
2348 }
2349 else if(a0!=0&&a1==0) {
2350 emit_mov(a1,1);
2351 if (a0>=0) emit_mov(a0,0);
2352 }
2353 else {
2354 if(a0>=0&&a0!=0) emit_mov(a0,0);
2355 if(a1>=0&&a1!=1) emit_mov(a1,1);
2356 }
2357}
2358
a5cd72d0 2359static void alu_assemble(int i, const struct regstat *i_regs, int ccadj_)
57871462 2360{
cf95b4f0 2361 if(dops[i].opcode2>=0x20&&dops[i].opcode2<=0x23) { // ADD/ADDU/SUB/SUBU
a5cd72d0 2362 int do_oflow = dops[i].may_except; // ADD/SUB with exceptions enabled
2363 if (dops[i].rt1 || do_oflow) {
2364 int do_exception_check = 0;
2365 signed char s1, s2, t, tmp;
2366 t = get_reg_w(i_regs->regmap, dops[i].rt1);
2367 tmp = get_reg_temp(i_regs->regmap);
277718fa 2368 if (do_oflow)
2369 assert(tmp >= 0);
90f98e7c 2370 if (t < 0 && do_oflow)
2371 t = tmp;
a5cd72d0 2372 if (t >= 0) {
2373 s1 = get_reg(i_regs->regmap, dops[i].rs1);
2374 s2 = get_reg(i_regs->regmap, dops[i].rs2);
2375 if (dops[i].rs1 && dops[i].rs2) {
57871462 2376 assert(s1>=0);
2377 assert(s2>=0);
a5cd72d0 2378 if (dops[i].opcode2 & 2) {
2379 if (do_oflow) {
2380 emit_subs(s1, s2, tmp);
2381 do_exception_check = 1;
2382 }
2383 else
2384 emit_sub(s1,s2,t);
2385 }
2386 else {
2387 if (do_oflow) {
2388 emit_adds(s1, s2, tmp);
2389 do_exception_check = 1;
2390 }
2391 else
2392 emit_add(s1,s2,t);
2393 }
57871462 2394 }
cf95b4f0 2395 else if(dops[i].rs1) {
57871462 2396 if(s1>=0) emit_mov(s1,t);
cf95b4f0 2397 else emit_loadreg(dops[i].rs1,t);
57871462 2398 }
cf95b4f0 2399 else if(dops[i].rs2) {
a5cd72d0 2400 if (s2 < 0) {
2401 emit_loadreg(dops[i].rs2, t);
2402 s2 = t;
57871462 2403 }
a5cd72d0 2404 if (dops[i].opcode2 & 2) {
2405 if (do_oflow) {
2406 emit_negs(s2, tmp);
2407 do_exception_check = 1;
2408 }
2409 else
2410 emit_neg(s2, t);
57871462 2411 }
a5cd72d0 2412 else if (s2 != t)
2413 emit_mov(s2, t);
57871462 2414 }
a5cd72d0 2415 else
2416 emit_zeroreg(t);
2417 }
2418 if (do_exception_check) {
2419 void *jaddr = out;
2420 emit_jo(0);
2421 if (t >= 0 && tmp != t)
2422 emit_mov(tmp, t);
2423 add_stub_r(OVERFLOW_STUB, jaddr, out, i, 0, i_regs, ccadj_, 0);
57871462 2424 }
2425 }
2426 }
a5cd72d0 2427 else if(dops[i].opcode2==0x2a||dops[i].opcode2==0x2b) { // SLT/SLTU
cf95b4f0 2428 if(dops[i].rt1) {
ad49de89 2429 signed char s1l,s2l,t;
57871462 2430 {
a5cd72d0 2431 t=get_reg_w(i_regs->regmap, dops[i].rt1);
57871462 2432 //assert(t>=0);
2433 if(t>=0) {
cf95b4f0 2434 s1l=get_reg(i_regs->regmap,dops[i].rs1);
2435 s2l=get_reg(i_regs->regmap,dops[i].rs2);
2436 if(dops[i].rs2==0) // rx<r0
57871462 2437 {
cf95b4f0 2438 if(dops[i].opcode2==0x2a&&dops[i].rs1!=0) { // SLT
06e425d7 2439 assert(s1l>=0);
57871462 2440 emit_shrimm(s1l,31,t);
06e425d7 2441 }
2442 else // SLTU (unsigned can not be less than zero, 0<0)
57871462 2443 emit_zeroreg(t);
2444 }
cf95b4f0 2445 else if(dops[i].rs1==0) // r0<rx
57871462 2446 {
2447 assert(s2l>=0);
cf95b4f0 2448 if(dops[i].opcode2==0x2a) // SLT
57871462 2449 emit_set_gz32(s2l,t);
2450 else // SLTU (set if not zero)
2451 emit_set_nz32(s2l,t);
2452 }
2453 else{
2454 assert(s1l>=0);assert(s2l>=0);
cf95b4f0 2455 if(dops[i].opcode2==0x2a) // SLT
57871462 2456 emit_set_if_less32(s1l,s2l,t);
2457 else // SLTU
2458 emit_set_if_carry32(s1l,s2l,t);
2459 }
2460 }
2461 }
2462 }
2463 }
a5cd72d0 2464 else if(dops[i].opcode2>=0x24&&dops[i].opcode2<=0x27) { // AND/OR/XOR/NOR
cf95b4f0 2465 if(dops[i].rt1) {
ad49de89 2466 signed char s1l,s2l,tl;
a5cd72d0 2467 tl=get_reg_w(i_regs->regmap, dops[i].rt1);
57871462 2468 {
57871462 2469 if(tl>=0) {
cf95b4f0 2470 s1l=get_reg(i_regs->regmap,dops[i].rs1);
2471 s2l=get_reg(i_regs->regmap,dops[i].rs2);
2472 if(dops[i].rs1&&dops[i].rs2) {
57871462 2473 assert(s1l>=0);
2474 assert(s2l>=0);
cf95b4f0 2475 if(dops[i].opcode2==0x24) { // AND
57871462 2476 emit_and(s1l,s2l,tl);
2477 } else
cf95b4f0 2478 if(dops[i].opcode2==0x25) { // OR
57871462 2479 emit_or(s1l,s2l,tl);
2480 } else
cf95b4f0 2481 if(dops[i].opcode2==0x26) { // XOR
57871462 2482 emit_xor(s1l,s2l,tl);
2483 } else
cf95b4f0 2484 if(dops[i].opcode2==0x27) { // NOR
57871462 2485 emit_or(s1l,s2l,tl);
2486 emit_not(tl,tl);
2487 }
2488 }
2489 else
2490 {
cf95b4f0 2491 if(dops[i].opcode2==0x24) { // AND
57871462 2492 emit_zeroreg(tl);
2493 } else
cf95b4f0 2494 if(dops[i].opcode2==0x25||dops[i].opcode2==0x26) { // OR/XOR
2495 if(dops[i].rs1){
57871462 2496 if(s1l>=0) emit_mov(s1l,tl);
cf95b4f0 2497 else emit_loadreg(dops[i].rs1,tl); // CHECK: regmap_entry?
57871462 2498 }
2499 else
cf95b4f0 2500 if(dops[i].rs2){
57871462 2501 if(s2l>=0) emit_mov(s2l,tl);
cf95b4f0 2502 else emit_loadreg(dops[i].rs2,tl); // CHECK: regmap_entry?
57871462 2503 }
2504 else emit_zeroreg(tl);
2505 } else
cf95b4f0 2506 if(dops[i].opcode2==0x27) { // NOR
2507 if(dops[i].rs1){
57871462 2508 if(s1l>=0) emit_not(s1l,tl);
2509 else {
cf95b4f0 2510 emit_loadreg(dops[i].rs1,tl);
57871462 2511 emit_not(tl,tl);
2512 }
2513 }
2514 else
cf95b4f0 2515 if(dops[i].rs2){
57871462 2516 if(s2l>=0) emit_not(s2l,tl);
2517 else {
cf95b4f0 2518 emit_loadreg(dops[i].rs2,tl);
57871462 2519 emit_not(tl,tl);
2520 }
2521 }
2522 else emit_movimm(-1,tl);
2523 }
2524 }
2525 }
2526 }
2527 }
2528 }
2529}
2530
a5cd72d0 2531static void imm16_assemble(int i, const struct regstat *i_regs, int ccadj_)
57871462 2532{
cf95b4f0 2533 if (dops[i].opcode==0x0f) { // LUI
2534 if(dops[i].rt1) {
57871462 2535 signed char t;
a5cd72d0 2536 t=get_reg_w(i_regs->regmap, dops[i].rt1);
57871462 2537 //assert(t>=0);
2538 if(t>=0) {
2539 if(!((i_regs->isconst>>t)&1))
277718fa 2540 emit_movimm(cinfo[i].imm<<16,t);
57871462 2541 }
2542 }
2543 }
cf95b4f0 2544 if(dops[i].opcode==0x08||dops[i].opcode==0x09) { // ADDI/ADDIU
277718fa 2545 int is_addi = dops[i].may_except;
a5cd72d0 2546 if (dops[i].rt1 || is_addi) {
2547 signed char s, t, tmp;
2548 t=get_reg_w(i_regs->regmap, dops[i].rt1);
cf95b4f0 2549 s=get_reg(i_regs->regmap,dops[i].rs1);
2550 if(dops[i].rs1) {
a5cd72d0 2551 tmp = get_reg_temp(i_regs->regmap);
2552 if (is_addi) {
2553 assert(tmp >= 0);
2554 if (t < 0) t = tmp;
2555 }
57871462 2556 if(t>=0) {
2557 if(!((i_regs->isconst>>t)&1)) {
a5cd72d0 2558 int sum, do_exception_check = 0;
2559 if (s < 0) {
cf95b4f0 2560 if(i_regs->regmap_entry[t]!=dops[i].rs1) emit_loadreg(dops[i].rs1,t);
a5cd72d0 2561 if (is_addi) {
277718fa 2562 emit_addimm_and_set_flags3(t, cinfo[i].imm, tmp);
a5cd72d0 2563 do_exception_check = 1;
2564 }
57871462 2565 else
277718fa 2566 emit_addimm(t, cinfo[i].imm, t);
a5cd72d0 2567 } else {
2568 if (!((i_regs->wasconst >> s) & 1)) {
2569 if (is_addi) {
277718fa 2570 emit_addimm_and_set_flags3(s, cinfo[i].imm, tmp);
a5cd72d0 2571 do_exception_check = 1;
2572 }
2573 else
277718fa 2574 emit_addimm(s, cinfo[i].imm, t);
a5cd72d0 2575 }
2576 else {
277718fa 2577 int oflow = add_overflow(constmap[i][s], cinfo[i].imm, sum);
a5cd72d0 2578 if (is_addi && oflow)
2579 do_exception_check = 2;
2580 else
2581 emit_movimm(sum, t);
2582 }
2583 }
2584 if (do_exception_check) {
2585 void *jaddr = out;
2586 if (do_exception_check == 2)
2587 emit_jmp(0);
2588 else {
2589 emit_jo(0);
2590 if (tmp != t)
2591 emit_mov(tmp, t);
2592 }
2593 add_stub_r(OVERFLOW_STUB, jaddr, out, i, 0, i_regs, ccadj_, 0);
57871462 2594 }
2595 }
2596 }
2597 } else {
2598 if(t>=0) {
2599 if(!((i_regs->isconst>>t)&1))
277718fa 2600 emit_movimm(cinfo[i].imm,t);
57871462 2601 }
2602 }
2603 }
2604 }
cf95b4f0 2605 else if(dops[i].opcode==0x0a||dops[i].opcode==0x0b) { // SLTI/SLTIU
2606 if(dops[i].rt1) {
2607 //assert(dops[i].rs1!=0); // r0 might be valid, but it's probably a bug
ad49de89 2608 signed char sl,t;
a5cd72d0 2609 t=get_reg_w(i_regs->regmap, dops[i].rt1);
cf95b4f0 2610 sl=get_reg(i_regs->regmap,dops[i].rs1);
57871462 2611 //assert(t>=0);
2612 if(t>=0) {
cf95b4f0 2613 if(dops[i].rs1>0) {
2614 if(dops[i].opcode==0x0a) { // SLTI
57871462 2615 if(sl<0) {
cf95b4f0 2616 if(i_regs->regmap_entry[t]!=dops[i].rs1) emit_loadreg(dops[i].rs1,t);
277718fa 2617 emit_slti32(t,cinfo[i].imm,t);
57871462 2618 }else{
277718fa 2619 emit_slti32(sl,cinfo[i].imm,t);
57871462 2620 }
2621 }
2622 else { // SLTIU
2623 if(sl<0) {
cf95b4f0 2624 if(i_regs->regmap_entry[t]!=dops[i].rs1) emit_loadreg(dops[i].rs1,t);
277718fa 2625 emit_sltiu32(t,cinfo[i].imm,t);
57871462 2626 }else{
277718fa 2627 emit_sltiu32(sl,cinfo[i].imm,t);
57871462 2628 }
2629 }
57871462 2630 }else{
2631 // SLTI(U) with r0 is just stupid,
2632 // nonetheless examples can be found
cf95b4f0 2633 if(dops[i].opcode==0x0a) // SLTI
277718fa 2634 if(0<cinfo[i].imm) emit_movimm(1,t);
57871462 2635 else emit_zeroreg(t);
2636 else // SLTIU
2637 {
277718fa 2638 if(cinfo[i].imm) emit_movimm(1,t);
57871462 2639 else emit_zeroreg(t);
2640 }
2641 }
2642 }
2643 }
2644 }
cf95b4f0 2645 else if(dops[i].opcode>=0x0c&&dops[i].opcode<=0x0e) { // ANDI/ORI/XORI
2646 if(dops[i].rt1) {
7c3a5182 2647 signed char sl,tl;
a5cd72d0 2648 tl=get_reg_w(i_regs->regmap, dops[i].rt1);
cf95b4f0 2649 sl=get_reg(i_regs->regmap,dops[i].rs1);
57871462 2650 if(tl>=0 && !((i_regs->isconst>>tl)&1)) {
cf95b4f0 2651 if(dops[i].opcode==0x0c) //ANDI
57871462 2652 {
cf95b4f0 2653 if(dops[i].rs1) {
57871462 2654 if(sl<0) {
cf95b4f0 2655 if(i_regs->regmap_entry[tl]!=dops[i].rs1) emit_loadreg(dops[i].rs1,tl);
277718fa 2656 emit_andimm(tl,cinfo[i].imm,tl);
57871462 2657 }else{
2658 if(!((i_regs->wasconst>>sl)&1))
277718fa 2659 emit_andimm(sl,cinfo[i].imm,tl);
57871462 2660 else
277718fa 2661 emit_movimm(constmap[i][sl]&cinfo[i].imm,tl);
57871462 2662 }
2663 }
2664 else
2665 emit_zeroreg(tl);
57871462 2666 }
2667 else
2668 {
cf95b4f0 2669 if(dops[i].rs1) {
57871462 2670 if(sl<0) {
cf95b4f0 2671 if(i_regs->regmap_entry[tl]!=dops[i].rs1) emit_loadreg(dops[i].rs1,tl);
57871462 2672 }
cf95b4f0 2673 if(dops[i].opcode==0x0d) { // ORI
581335b0 2674 if(sl<0) {
277718fa 2675 emit_orimm(tl,cinfo[i].imm,tl);
581335b0 2676 }else{
2677 if(!((i_regs->wasconst>>sl)&1))
277718fa 2678 emit_orimm(sl,cinfo[i].imm,tl);
581335b0 2679 else
277718fa 2680 emit_movimm(constmap[i][sl]|cinfo[i].imm,tl);
581335b0 2681 }
57871462 2682 }
cf95b4f0 2683 if(dops[i].opcode==0x0e) { // XORI
581335b0 2684 if(sl<0) {
277718fa 2685 emit_xorimm(tl,cinfo[i].imm,tl);
581335b0 2686 }else{
2687 if(!((i_regs->wasconst>>sl)&1))
277718fa 2688 emit_xorimm(sl,cinfo[i].imm,tl);
581335b0 2689 else
277718fa 2690 emit_movimm(constmap[i][sl]^cinfo[i].imm,tl);
581335b0 2691 }
57871462 2692 }
2693 }
2694 else {
277718fa 2695 emit_movimm(cinfo[i].imm,tl);
57871462 2696 }
2697 }
2698 }
2699 }
2700 }
2701}
2702
2330734f 2703static void shiftimm_assemble(int i, const struct regstat *i_regs)
57871462 2704{
cf95b4f0 2705 if(dops[i].opcode2<=0x3) // SLL/SRL/SRA
57871462 2706 {
cf95b4f0 2707 if(dops[i].rt1) {
57871462 2708 signed char s,t;
a5cd72d0 2709 t=get_reg_w(i_regs->regmap, dops[i].rt1);
cf95b4f0 2710 s=get_reg(i_regs->regmap,dops[i].rs1);
57871462 2711 //assert(t>=0);
dc49e339 2712 if(t>=0&&!((i_regs->isconst>>t)&1)){
cf95b4f0 2713 if(dops[i].rs1==0)
57871462 2714 {
2715 emit_zeroreg(t);
2716 }
2717 else
2718 {
cf95b4f0 2719 if(s<0&&i_regs->regmap_entry[t]!=dops[i].rs1) emit_loadreg(dops[i].rs1,t);
277718fa 2720 if(cinfo[i].imm) {
cf95b4f0 2721 if(dops[i].opcode2==0) // SLL
57871462 2722 {
277718fa 2723 emit_shlimm(s<0?t:s,cinfo[i].imm,t);
57871462 2724 }
cf95b4f0 2725 if(dops[i].opcode2==2) // SRL
57871462 2726 {
277718fa 2727 emit_shrimm(s<0?t:s,cinfo[i].imm,t);
57871462 2728 }
cf95b4f0 2729 if(dops[i].opcode2==3) // SRA
57871462 2730 {
277718fa 2731 emit_sarimm(s<0?t:s,cinfo[i].imm,t);
57871462 2732 }
2733 }else{
2734 // Shift by zero
2735 if(s>=0 && s!=t) emit_mov(s,t);
2736 }
2737 }
2738 }
cf95b4f0 2739 //emit_storereg(dops[i].rt1,t); //DEBUG
57871462 2740 }
2741 }
cf95b4f0 2742 if(dops[i].opcode2>=0x38&&dops[i].opcode2<=0x3b) // DSLL/DSRL/DSRA
57871462 2743 {
9c45ca93 2744 assert(0);
57871462 2745 }
cf95b4f0 2746 if(dops[i].opcode2==0x3c) // DSLL32
57871462 2747 {
9c45ca93 2748 assert(0);
57871462 2749 }
cf95b4f0 2750 if(dops[i].opcode2==0x3e) // DSRL32
57871462 2751 {
9c45ca93 2752 assert(0);
57871462 2753 }
cf95b4f0 2754 if(dops[i].opcode2==0x3f) // DSRA32
57871462 2755 {
9c45ca93 2756 assert(0);
57871462 2757 }
2758}
2759
2760#ifndef shift_assemble
2330734f 2761static void shift_assemble(int i, const struct regstat *i_regs)
57871462 2762{
3968e69e 2763 signed char s,t,shift;
cf95b4f0 2764 if (dops[i].rt1 == 0)
3968e69e 2765 return;
cf95b4f0 2766 assert(dops[i].opcode2<=0x07); // SLLV/SRLV/SRAV
2767 t = get_reg(i_regs->regmap, dops[i].rt1);
2768 s = get_reg(i_regs->regmap, dops[i].rs1);
2769 shift = get_reg(i_regs->regmap, dops[i].rs2);
3968e69e 2770 if (t < 0)
2771 return;
2772
cf95b4f0 2773 if(dops[i].rs1==0)
3968e69e 2774 emit_zeroreg(t);
cf95b4f0 2775 else if(dops[i].rs2==0) {
3968e69e 2776 assert(s>=0);
2777 if(s!=t) emit_mov(s,t);
2778 }
2779 else {
2780 host_tempreg_acquire();
2781 emit_andimm(shift,31,HOST_TEMPREG);
cf95b4f0 2782 switch(dops[i].opcode2) {
3968e69e 2783 case 4: // SLLV
2784 emit_shl(s,HOST_TEMPREG,t);
2785 break;
2786 case 6: // SRLV
2787 emit_shr(s,HOST_TEMPREG,t);
2788 break;
2789 case 7: // SRAV
2790 emit_sar(s,HOST_TEMPREG,t);
2791 break;
2792 default:
2793 assert(0);
2794 }
2795 host_tempreg_release();
2796 }
57871462 2797}
3968e69e 2798
57871462 2799#endif
2800
8062d65a 2801enum {
2802 MTYPE_8000 = 0,
2803 MTYPE_8020,
2804 MTYPE_0000,
2805 MTYPE_A000,
2806 MTYPE_1F80,
2807};
2808
2809static int get_ptr_mem_type(u_int a)
2810{
2811 if(a < 0x00200000) {
2812 if(a<0x1000&&((start>>20)==0xbfc||(start>>24)==0xa0))
2813 // return wrong, must use memhandler for BIOS self-test to pass
2814 // 007 does similar stuff from a00 mirror, weird stuff
2815 return MTYPE_8000;
2816 return MTYPE_0000;
2817 }
2818 if(0x1f800000 <= a && a < 0x1f801000)
2819 return MTYPE_1F80;
2820 if(0x80200000 <= a && a < 0x80800000)
2821 return MTYPE_8020;
2822 if(0xa0000000 <= a && a < 0xa0200000)
2823 return MTYPE_A000;
2824 return MTYPE_8000;
2825}
2826
37387d8b 2827static int get_ro_reg(const struct regstat *i_regs, int host_tempreg_free)
2828{
2829 int r = get_reg(i_regs->regmap, ROREG);
2830 if (r < 0 && host_tempreg_free) {
2831 host_tempreg_acquire();
2832 emit_loadreg(ROREG, r = HOST_TEMPREG);
2833 }
2834 if (r < 0)
2835 abort();
2836 return r;
2837}
2838
2839static void *emit_fastpath_cmp_jump(int i, const struct regstat *i_regs,
277718fa 2840 int addr, int *offset_reg, int *addr_reg_override, int ccadj_)
8062d65a 2841{
2842 void *jaddr = NULL;
37387d8b 2843 int type = 0;
2844 int mr = dops[i].rs1;
277718fa 2845 assert(addr >= 0);
37387d8b 2846 *offset_reg = -1;
8062d65a 2847 if(((smrv_strong|smrv_weak)>>mr)&1) {
2848 type=get_ptr_mem_type(smrv[mr]);
2849 //printf("set %08x @%08x r%d %d\n", smrv[mr], start+i*4, mr, type);
2850 }
2851 else {
2852 // use the mirror we are running on
2853 type=get_ptr_mem_type(start);
2854 //printf("set nospec @%08x r%d %d\n", start+i*4, mr, type);
2855 }
2856
277718fa 2857 if (dops[i].may_except) {
2858 // alignment check
2859 u_int op = dops[i].opcode;
2860 int mask = ((op & 0x37) == 0x21 || op == 0x25) ? 1 : 3; // LH/SH/LHU
33a1eda1 2861 void *jaddr2;
277718fa 2862 emit_testimm(addr, mask);
33a1eda1 2863 jaddr2 = out;
277718fa 2864 emit_jne(0);
33a1eda1 2865 add_stub_r(ALIGNMENT_STUB, jaddr2, out, i, addr, i_regs, ccadj_, 0);
277718fa 2866 }
2867
8062d65a 2868 if(type==MTYPE_8020) { // RAM 80200000+ mirror
d1e4ebd9 2869 host_tempreg_acquire();
8062d65a 2870 emit_andimm(addr,~0x00e00000,HOST_TEMPREG);
2871 addr=*addr_reg_override=HOST_TEMPREG;
2872 type=0;
2873 }
2874 else if(type==MTYPE_0000) { // RAM 0 mirror
d1e4ebd9 2875 host_tempreg_acquire();
8062d65a 2876 emit_orimm(addr,0x80000000,HOST_TEMPREG);
2877 addr=*addr_reg_override=HOST_TEMPREG;
2878 type=0;
2879 }
2880 else if(type==MTYPE_A000) { // RAM A mirror
d1e4ebd9 2881 host_tempreg_acquire();
8062d65a 2882 emit_andimm(addr,~0x20000000,HOST_TEMPREG);
2883 addr=*addr_reg_override=HOST_TEMPREG;
2884 type=0;
2885 }
2886 else if(type==MTYPE_1F80) { // scratchpad
2887 if (psxH == (void *)0x1f800000) {
d1e4ebd9 2888 host_tempreg_acquire();
3968e69e 2889 emit_xorimm(addr,0x1f800000,HOST_TEMPREG);
8062d65a 2890 emit_cmpimm(HOST_TEMPREG,0x1000);
d1e4ebd9 2891 host_tempreg_release();
8062d65a 2892 jaddr=out;
2893 emit_jc(0);
2894 }
2895 else {
2896 // do the usual RAM check, jump will go to the right handler
2897 type=0;
2898 }
2899 }
2900
37387d8b 2901 if (type == 0) // need ram check
8062d65a 2902 {
2903 emit_cmpimm(addr,RAM_SIZE);
37387d8b 2904 jaddr = out;
8062d65a 2905 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
2906 // Hint to branch predictor that the branch is unlikely to be taken
37387d8b 2907 if (dops[i].rs1 >= 28)
8062d65a 2908 emit_jno_unlikely(0);
2909 else
2910 #endif
2911 emit_jno(0);
37387d8b 2912 if (ram_offset != 0)
2913 *offset_reg = get_ro_reg(i_regs, 0);
8062d65a 2914 }
2915
2916 return jaddr;
2917}
2918
687b4580 2919// return memhandler, or get directly accessable address and return 0
2920static void *get_direct_memhandler(void *table, u_int addr,
2921 enum stub_type type, uintptr_t *addr_host)
2922{
c979e8c2 2923 uintptr_t msb = 1ull << (sizeof(uintptr_t)*8 - 1);
687b4580 2924 uintptr_t l1, l2 = 0;
2925 l1 = ((uintptr_t *)table)[addr>>12];
c979e8c2 2926 if (!(l1 & msb)) {
687b4580 2927 uintptr_t v = l1 << 1;
2928 *addr_host = v + addr;
2929 return NULL;
2930 }
2931 else {
2932 l1 <<= 1;
2933 if (type == LOADB_STUB || type == LOADBU_STUB || type == STOREB_STUB)
2934 l2 = ((uintptr_t *)l1)[0x1000/4 + 0x1000/2 + (addr&0xfff)];
2935 else if (type == LOADH_STUB || type == LOADHU_STUB || type == STOREH_STUB)
c979e8c2 2936 l2 = ((uintptr_t *)l1)[0x1000/4 + (addr&0xfff)/2];
687b4580 2937 else
c979e8c2 2938 l2 = ((uintptr_t *)l1)[(addr&0xfff)/4];
2939 if (!(l2 & msb)) {
687b4580 2940 uintptr_t v = l2 << 1;
2941 *addr_host = v + (addr&0xfff);
2942 return NULL;
2943 }
2944 return (void *)(l2 << 1);
2945 }
2946}
2947
81dbbf4c 2948static u_int get_host_reglist(const signed char *regmap)
2949{
2950 u_int reglist = 0, hr;
2951 for (hr = 0; hr < HOST_REGS; hr++) {
2952 if (hr != EXCLUDE_REG && regmap[hr] >= 0)
2953 reglist |= 1 << hr;
2954 }
2955 return reglist;
2956}
2957
2958static u_int reglist_exclude(u_int reglist, int r1, int r2)
2959{
2960 if (r1 >= 0)
2961 reglist &= ~(1u << r1);
2962 if (r2 >= 0)
2963 reglist &= ~(1u << r2);
2964 return reglist;
2965}
2966
e3c6bdb5 2967// find a temp caller-saved register not in reglist (so assumed to be free)
2968static int reglist_find_free(u_int reglist)
2969{
2970 u_int free_regs = ~reglist & CALLER_SAVE_REGS;
2971 if (free_regs == 0)
2972 return -1;
2973 return __builtin_ctz(free_regs);
2974}
2975
37387d8b 2976static void do_load_word(int a, int rt, int offset_reg)
2977{
2978 if (offset_reg >= 0)
2979 emit_ldr_dualindexed(offset_reg, a, rt);
2980 else
2981 emit_readword_indexed(0, a, rt);
2982}
2983
2984static void do_store_word(int a, int ofs, int rt, int offset_reg, int preseve_a)
2985{
2986 if (offset_reg < 0) {
2987 emit_writeword_indexed(rt, ofs, a);
2988 return;
2989 }
2990 if (ofs != 0)
2991 emit_addimm(a, ofs, a);
2992 emit_str_dualindexed(offset_reg, a, rt);
2993 if (ofs != 0 && preseve_a)
2994 emit_addimm(a, -ofs, a);
2995}
2996
2997static void do_store_hword(int a, int ofs, int rt, int offset_reg, int preseve_a)
2998{
2999 if (offset_reg < 0) {
3000 emit_writehword_indexed(rt, ofs, a);
3001 return;
3002 }
3003 if (ofs != 0)
3004 emit_addimm(a, ofs, a);
3005 emit_strh_dualindexed(offset_reg, a, rt);
3006 if (ofs != 0 && preseve_a)
3007 emit_addimm(a, -ofs, a);
3008}
3009
3010static void do_store_byte(int a, int rt, int offset_reg)
3011{
3012 if (offset_reg >= 0)
3013 emit_strb_dualindexed(offset_reg, a, rt);
3014 else
3015 emit_writebyte_indexed(rt, 0, a);
3016}
3017
2330734f 3018static void load_assemble(int i, const struct regstat *i_regs, int ccadj_)
57871462 3019{
277718fa 3020 int addr = cinfo[i].addr;
3021 int s,tl;
57871462 3022 int offset;
b14b6a8f 3023 void *jaddr=0;
5bf843dc 3024 int memtarget=0,c=0;
37387d8b 3025 int offset_reg = -1;
3026 int fastio_reg_override = -1;
81dbbf4c 3027 u_int reglist=get_host_reglist(i_regs->regmap);
a5cd72d0 3028 tl=get_reg_w(i_regs->regmap, dops[i].rt1);
cf95b4f0 3029 s=get_reg(i_regs->regmap,dops[i].rs1);
277718fa 3030 offset=cinfo[i].imm;
57871462 3031 if(i_regs->regmap[HOST_CCREG]==CCREG) reglist&=~(1<<HOST_CCREG);
3032 if(s>=0) {
3033 c=(i_regs->wasconst>>s)&1;
af4ee1fe 3034 if (c) {
3035 memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
af4ee1fe 3036 }
57871462 3037 }
57871462 3038 //printf("load_assemble: c=%d\n",c);
643aeae3 3039 //if(c) printf("load_assemble: const=%lx\n",(long)constmap[i][s]+offset);
a5cd72d0 3040 if(tl<0 && ((!c||(((u_int)constmap[i][s]+offset)>>16)==0x1f80) || dops[i].rt1==0)) {
5bf843dc 3041 // could be FIFO, must perform the read
f18c0f46 3042 // ||dummy read
5bf843dc 3043 assem_debug("(forced read)\n");
277718fa 3044 tl = get_reg_temp(i_regs->regmap); // may be == addr
5bf843dc 3045 assert(tl>=0);
5bf843dc 3046 }
277718fa 3047 assert(addr >= 0);
535d208a 3048 if(tl>=0) {
3049 //printf("load_assemble: c=%d\n",c);
643aeae3 3050 //if(c) printf("load_assemble: const=%lx\n",(long)constmap[i][s]+offset);
535d208a 3051 reglist&=~(1<<tl);
1edfcc68 3052 if(!c) {
1edfcc68 3053 #ifdef R29_HACK
3054 // Strmnnrmn's speed hack
cf95b4f0 3055 if(dops[i].rs1!=29||start<0x80001000||start>=0x80000000+RAM_SIZE)
1edfcc68 3056 #endif
3057 {
37387d8b 3058 jaddr = emit_fastpath_cmp_jump(i, i_regs, addr,
277718fa 3059 &offset_reg, &fastio_reg_override, ccadj_);
535d208a 3060 }
1edfcc68 3061 }
37387d8b 3062 else if (ram_offset && memtarget) {
3063 offset_reg = get_ro_reg(i_regs, 0);
535d208a 3064 }
a5cd72d0 3065 int dummy=(dops[i].rt1==0)||(tl!=get_reg_w(i_regs->regmap, dops[i].rt1)); // ignore loads to r0 and unneeded reg
37387d8b 3066 switch (dops[i].opcode) {
3067 case 0x20: // LB
535d208a 3068 if(!c||memtarget) {
3069 if(!dummy) {
277718fa 3070 int a = addr;
37387d8b 3071 if (fastio_reg_override >= 0)
3072 a = fastio_reg_override;
b1570849 3073
37387d8b 3074 if (offset_reg >= 0)
3075 emit_ldrsb_dualindexed(offset_reg, a, tl);
3076 else
3077 emit_movsbl_indexed(0, a, tl);
57871462 3078 }
535d208a 3079 if(jaddr)
2330734f 3080 add_stub_r(LOADB_STUB,jaddr,out,i,addr,i_regs,ccadj_,reglist);
57871462 3081 }
535d208a 3082 else
2330734f 3083 inline_readstub(LOADB_STUB,i,constmap[i][s]+offset,i_regs->regmap,dops[i].rt1,ccadj_,reglist);
37387d8b 3084 break;
3085 case 0x21: // LH
535d208a 3086 if(!c||memtarget) {
3087 if(!dummy) {
277718fa 3088 int a = addr;
37387d8b 3089 if (fastio_reg_override >= 0)
3090 a = fastio_reg_override;
3091 if (offset_reg >= 0)
3092 emit_ldrsh_dualindexed(offset_reg, a, tl);
3093 else
3094 emit_movswl_indexed(0, a, tl);
57871462 3095 }
535d208a 3096 if(jaddr)
2330734f 3097 add_stub_r(LOADH_STUB,jaddr,out,i,addr,i_regs,ccadj_,reglist);
57871462 3098 }
535d208a 3099 else
2330734f 3100 inline_readstub(LOADH_STUB,i,constmap[i][s]+offset,i_regs->regmap,dops[i].rt1,ccadj_,reglist);
37387d8b 3101 break;
3102 case 0x23: // LW
535d208a 3103 if(!c||memtarget) {
3104 if(!dummy) {
37387d8b 3105 int a = addr;
3106 if (fastio_reg_override >= 0)
3107 a = fastio_reg_override;
3108 do_load_word(a, tl, offset_reg);
57871462 3109 }
535d208a 3110 if(jaddr)
2330734f 3111 add_stub_r(LOADW_STUB,jaddr,out,i,addr,i_regs,ccadj_,reglist);
57871462 3112 }
535d208a 3113 else
2330734f 3114 inline_readstub(LOADW_STUB,i,constmap[i][s]+offset,i_regs->regmap,dops[i].rt1,ccadj_,reglist);
37387d8b 3115 break;
3116 case 0x24: // LBU
535d208a 3117 if(!c||memtarget) {
3118 if(!dummy) {
277718fa 3119 int a = addr;
37387d8b 3120 if (fastio_reg_override >= 0)
3121 a = fastio_reg_override;
b1570849 3122
37387d8b 3123 if (offset_reg >= 0)
3124 emit_ldrb_dualindexed(offset_reg, a, tl);
3125 else
3126 emit_movzbl_indexed(0, a, tl);
57871462 3127 }
535d208a 3128 if(jaddr)
2330734f 3129 add_stub_r(LOADBU_STUB,jaddr,out,i,addr,i_regs,ccadj_,reglist);
57871462 3130 }
535d208a 3131 else
2330734f 3132 inline_readstub(LOADBU_STUB,i,constmap[i][s]+offset,i_regs->regmap,dops[i].rt1,ccadj_,reglist);
37387d8b 3133 break;
3134 case 0x25: // LHU
535d208a 3135 if(!c||memtarget) {
3136 if(!dummy) {
277718fa 3137 int a = addr;
37387d8b 3138 if (fastio_reg_override >= 0)
3139 a = fastio_reg_override;
3140 if (offset_reg >= 0)
3141 emit_ldrh_dualindexed(offset_reg, a, tl);
3142 else
3143 emit_movzwl_indexed(0, a, tl);
57871462 3144 }
535d208a 3145 if(jaddr)
2330734f 3146 add_stub_r(LOADHU_STUB,jaddr,out,i,addr,i_regs,ccadj_,reglist);
57871462 3147 }
535d208a 3148 else
2330734f 3149 inline_readstub(LOADHU_STUB,i,constmap[i][s]+offset,i_regs->regmap,dops[i].rt1,ccadj_,reglist);
37387d8b 3150 break;
37387d8b 3151 default:
9c45ca93 3152 assert(0);
57871462 3153 }
a5cd72d0 3154 } // tl >= 0
37387d8b 3155 if (fastio_reg_override == HOST_TEMPREG || offset_reg == HOST_TEMPREG)
d1e4ebd9 3156 host_tempreg_release();
57871462 3157}
3158
3159#ifndef loadlr_assemble
2330734f 3160static void loadlr_assemble(int i, const struct regstat *i_regs, int ccadj_)
57871462 3161{
277718fa 3162 int addr = cinfo[i].addr;
3163 int s,tl,temp,temp2;
3968e69e 3164 int offset;
3165 void *jaddr=0;
3166 int memtarget=0,c=0;
37387d8b 3167 int offset_reg = -1;
3168 int fastio_reg_override = -1;
81dbbf4c 3169 u_int reglist=get_host_reglist(i_regs->regmap);
a5cd72d0 3170 tl=get_reg_w(i_regs->regmap, dops[i].rt1);
cf95b4f0 3171 s=get_reg(i_regs->regmap,dops[i].rs1);
9de8a0c3 3172 temp=get_reg_temp(i_regs->regmap);
3968e69e 3173 temp2=get_reg(i_regs->regmap,FTEMP);
277718fa 3174 offset=cinfo[i].imm;
3968e69e 3175 reglist|=1<<temp;
277718fa 3176 assert(addr >= 0);
3968e69e 3177 if(s>=0) {
3178 c=(i_regs->wasconst>>s)&1;
3179 if(c) {
3180 memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
3181 }
3182 }
3183 if(!c) {
3184 emit_shlimm(addr,3,temp);
cf95b4f0 3185 if (dops[i].opcode==0x22||dops[i].opcode==0x26) {
3968e69e 3186 emit_andimm(addr,0xFFFFFFFC,temp2); // LWL/LWR
3187 }else{
3188 emit_andimm(addr,0xFFFFFFF8,temp2); // LDL/LDR
3189 }
37387d8b 3190 jaddr = emit_fastpath_cmp_jump(i, i_regs, temp2,
277718fa 3191 &offset_reg, &fastio_reg_override, ccadj_);
3968e69e 3192 }
3193 else {
37387d8b 3194 if (ram_offset && memtarget) {
3195 offset_reg = get_ro_reg(i_regs, 0);
3968e69e 3196 }
cf95b4f0 3197 if (dops[i].opcode==0x22||dops[i].opcode==0x26) {
3968e69e 3198 emit_movimm(((constmap[i][s]+offset)<<3)&24,temp); // LWL/LWR
3199 }else{
3200 emit_movimm(((constmap[i][s]+offset)<<3)&56,temp); // LDL/LDR
3201 }
3202 }
cf95b4f0 3203 if (dops[i].opcode==0x22||dops[i].opcode==0x26) { // LWL/LWR
3968e69e 3204 if(!c||memtarget) {
37387d8b 3205 int a = temp2;
3206 if (fastio_reg_override >= 0)
3207 a = fastio_reg_override;
3208 do_load_word(a, temp2, offset_reg);
3209 if (fastio_reg_override == HOST_TEMPREG || offset_reg == HOST_TEMPREG)
3210 host_tempreg_release();
2330734f 3211 if(jaddr) add_stub_r(LOADW_STUB,jaddr,out,i,temp2,i_regs,ccadj_,reglist);
3968e69e 3212 }
3213 else
2330734f 3214 inline_readstub(LOADW_STUB,i,(constmap[i][s]+offset)&0xFFFFFFFC,i_regs->regmap,FTEMP,ccadj_,reglist);
cf95b4f0 3215 if(dops[i].rt1) {
3968e69e 3216 assert(tl>=0);
3217 emit_andimm(temp,24,temp);
cf95b4f0 3218 if (dops[i].opcode==0x22) // LWL
3968e69e 3219 emit_xorimm(temp,24,temp);
3220 host_tempreg_acquire();
3221 emit_movimm(-1,HOST_TEMPREG);
cf95b4f0 3222 if (dops[i].opcode==0x26) {
3968e69e 3223 emit_shr(temp2,temp,temp2);
3224 emit_bic_lsr(tl,HOST_TEMPREG,temp,tl);
3225 }else{
3226 emit_shl(temp2,temp,temp2);
3227 emit_bic_lsl(tl,HOST_TEMPREG,temp,tl);
3228 }
3229 host_tempreg_release();
3230 emit_or(temp2,tl,tl);
3231 }
cf95b4f0 3232 //emit_storereg(dops[i].rt1,tl); // DEBUG
3968e69e 3233 }
cf95b4f0 3234 if (dops[i].opcode==0x1A||dops[i].opcode==0x1B) { // LDL/LDR
3968e69e 3235 assert(0);
3236 }
57871462 3237}
3238#endif
3239
9b495f6e 3240static void do_invstub(int n)
3241{
3242 literal_pool(20);
684b6816 3243 assem_debug("do_invstub %x\n", start + stubs[n].e*4);
9b495f6e 3244 u_int reglist = stubs[n].a;
3245 u_int addrr = stubs[n].b;
3246 int ofs_start = stubs[n].c;
3247 int ofs_end = stubs[n].d;
3248 int len = ofs_end - ofs_start;
3249 u_int rightr = 0;
3250
3251 set_jump_target(stubs[n].addr, out);
3252 save_regs(reglist);
9b495f6e 3253 if (addrr != 0 || ofs_start != 0)
3254 emit_addimm(addrr, ofs_start, 0);
3033d898 3255 emit_readword(&inv_code_start, 2);
3256 emit_readword(&inv_code_end, 3);
9b495f6e 3257 if (len != 0)
3258 emit_addimm(0, len + 4, (rightr = 1));
3259 emit_cmp(0, 2);
3260 emit_cmpcs(3, rightr);
3261 void *jaddr = out;
3262 emit_jc(0);
3263 void *func = (len != 0)
3264 ? (void *)ndrc_write_invalidate_many
3265 : (void *)ndrc_write_invalidate_one;
3266 emit_far_call(func);
3267 set_jump_target(jaddr, out);
3268 restore_regs(reglist);
3269 emit_jmp(stubs[n].retaddr);
3270}
3271
3272static void do_store_smc_check(int i, const struct regstat *i_regs, u_int reglist, int addr)
3273{
3274 if (HACK_ENABLED(NDHACK_NO_SMC_CHECK))
3275 return;
3276 // this can't be used any more since we started to check exact
3277 // block boundaries in invalidate_range()
3278 //if (i_regs->waswritten & (1<<dops[i].rs1))
3279 // return;
3280 // (naively) assume nobody will run code from stack
3281 if (dops[i].rs1 == 29)
3282 return;
3283
277718fa 3284 int j, imm_maxdiff = 32, imm_min = cinfo[i].imm, imm_max = cinfo[i].imm, count = 1;
9b495f6e 3285 if (i < slen - 1 && dops[i+1].is_store && dops[i+1].rs1 == dops[i].rs1
277718fa 3286 && abs(cinfo[i+1].imm - cinfo[i].imm) <= imm_maxdiff)
9b495f6e 3287 return;
3288 for (j = i - 1; j >= 0; j--) {
3289 if (!dops[j].is_store || dops[j].rs1 != dops[i].rs1
277718fa 3290 || abs(cinfo[j].imm - cinfo[j+1].imm) > imm_maxdiff)
9b495f6e 3291 break;
3292 count++;
277718fa 3293 if (imm_min > cinfo[j].imm)
3294 imm_min = cinfo[j].imm;
3295 if (imm_max < cinfo[j].imm)
3296 imm_max = cinfo[j].imm;
9b495f6e 3297 }
3298#if defined(HOST_IMM8)
3299 int ir = get_reg(i_regs->regmap, INVCP);
3300 assert(ir >= 0);
3301 host_tempreg_acquire();
3302 emit_ldrb_indexedsr12_reg(ir, addr, HOST_TEMPREG);
3303#else
3304 emit_cmpmem_indexedsr12_imm(invalid_code, addr, 1);
3305 #error not handled
3306#endif
3307#ifdef INVALIDATE_USE_COND_CALL
3308 if (count == 1) {
3309 emit_cmpimm(HOST_TEMPREG, 1);
3310 emit_callne(invalidate_addr_reg[addr]);
3311 host_tempreg_release();
3312 return;
3313 }
3314#endif
3315 void *jaddr = emit_cbz(HOST_TEMPREG, 0);
3316 host_tempreg_release();
277718fa 3317 imm_min -= cinfo[i].imm;
3318 imm_max -= cinfo[i].imm;
9b495f6e 3319 add_stub(INVCODE_STUB, jaddr, out, reglist|(1<<HOST_CCREG),
684b6816 3320 addr, imm_min, imm_max, i);
9b495f6e 3321}
3322
684b6816 3323// determines if code overwrite checking is needed only
3324// (also true non-existent 0x20000000 mirror that shouldn't matter)
3325#define is_ram_addr(a) !((a) & 0x5f800000)
3326
2330734f 3327static void store_assemble(int i, const struct regstat *i_regs, int ccadj_)
57871462 3328{
9c45ca93 3329 int s,tl;
277718fa 3330 int addr = cinfo[i].addr;
57871462 3331 int offset;
b14b6a8f 3332 void *jaddr=0;
37387d8b 3333 enum stub_type type=0;
666a299d 3334 int memtarget=0,c=0;
37387d8b 3335 int offset_reg = -1;
3336 int fastio_reg_override = -1;
684b6816 3337 u_int addr_const = ~0;
81dbbf4c 3338 u_int reglist=get_host_reglist(i_regs->regmap);
cf95b4f0 3339 tl=get_reg(i_regs->regmap,dops[i].rs2);
3340 s=get_reg(i_regs->regmap,dops[i].rs1);
277718fa 3341 offset=cinfo[i].imm;
57871462 3342 if(s>=0) {
3343 c=(i_regs->wasconst>>s)&1;
684b6816 3344 if (c) {
3345 addr_const = constmap[i][s] + offset;
3346 memtarget = ((signed int)addr_const) < (signed int)(0x80000000 + RAM_SIZE);
af4ee1fe 3347 }
57871462 3348 }
3349 assert(tl>=0);
277718fa 3350 assert(addr >= 0);
57871462 3351 if(i_regs->regmap[HOST_CCREG]==CCREG) reglist&=~(1<<HOST_CCREG);
684b6816 3352 reglist |= 1u << addr;
37387d8b 3353 if (!c) {
3354 jaddr = emit_fastpath_cmp_jump(i, i_regs, addr,
277718fa 3355 &offset_reg, &fastio_reg_override, ccadj_);
1edfcc68 3356 }
37387d8b 3357 else if (ram_offset && memtarget) {
3358 offset_reg = get_ro_reg(i_regs, 0);
57871462 3359 }
3360
37387d8b 3361 switch (dops[i].opcode) {
3362 case 0x28: // SB
57871462 3363 if(!c||memtarget) {
277718fa 3364 int a = addr;
37387d8b 3365 if (fastio_reg_override >= 0)
3366 a = fastio_reg_override;
3367 do_store_byte(a, tl, offset_reg);
3368 }
3369 type = STOREB_STUB;
3370 break;
3371 case 0x29: // SH
57871462 3372 if(!c||memtarget) {
277718fa 3373 int a = addr;
37387d8b 3374 if (fastio_reg_override >= 0)
3375 a = fastio_reg_override;
3376 do_store_hword(a, 0, tl, offset_reg, 1);
3377 }
3378 type = STOREH_STUB;
3379 break;
3380 case 0x2B: // SW
dadf55f2 3381 if(!c||memtarget) {
37387d8b 3382 int a = addr;
3383 if (fastio_reg_override >= 0)
3384 a = fastio_reg_override;
3385 do_store_word(a, 0, tl, offset_reg, 1);
3386 }
3387 type = STOREW_STUB;
3388 break;
37387d8b 3389 default:
9c45ca93 3390 assert(0);
57871462 3391 }
37387d8b 3392 if (fastio_reg_override == HOST_TEMPREG || offset_reg == HOST_TEMPREG)
d1e4ebd9 3393 host_tempreg_release();
684b6816 3394 if (jaddr) {
b96d3df7 3395 // PCSX store handlers don't check invcode again
2330734f 3396 add_stub_r(type,jaddr,out,i,addr,i_regs,ccadj_,reglist);
7a518516 3397 }
684b6816 3398 if (!c || is_ram_addr(addr_const))
3399 do_store_smc_check(i, i_regs, reglist, addr);
3400 if (c && !memtarget)
3401 inline_writestub(type, i, addr_const, i_regs->regmap, dops[i].rs2, ccadj_, reglist);
7a518516 3402 // basic current block modification detection..
3403 // not looking back as that should be in mips cache already
3968e69e 3404 // (see Spyro2 title->attract mode)
684b6816 3405 if (start + i*4 < addr_const && addr_const < start + slen*4) {
3406 SysPrintf("write to %08x hits block %08x, pc=%08x\n", addr_const, start, start+i*4);
7a518516 3407 assert(i_regs->regmap==regs[i].regmap); // not delay slot
3408 if(i_regs->regmap==regs[i].regmap) {
ad49de89 3409 load_all_consts(regs[i].regmap_entry,regs[i].wasdirty,i);
3410 wb_dirtys(regs[i].regmap_entry,regs[i].wasdirty);
7a518516 3411 emit_movimm(start+i*4+4,0);
643aeae3 3412 emit_writeword(0,&pcaddr);
d1e4ebd9 3413 emit_addimm(HOST_CCREG,2,HOST_CCREG);
104df9d3 3414 emit_far_call(ndrc_get_addr_ht);
d1e4ebd9 3415 emit_jmpreg(0);
7a518516 3416 }
3eaa7048 3417 }
57871462 3418}
3419
2330734f 3420static void storelr_assemble(int i, const struct regstat *i_regs, int ccadj_)
57871462 3421{
277718fa 3422 int addr = cinfo[i].addr;
9c45ca93 3423 int s,tl;
57871462 3424 int offset;
b14b6a8f 3425 void *jaddr=0;
37387d8b 3426 void *case1, *case23, *case3;
df4dc2b1 3427 void *done0, *done1, *done2;
af4ee1fe 3428 int memtarget=0,c=0;
37387d8b 3429 int offset_reg = -1;
684b6816 3430 u_int addr_const = ~0;
3431 u_int reglist = get_host_reglist(i_regs->regmap);
cf95b4f0 3432 tl=get_reg(i_regs->regmap,dops[i].rs2);
3433 s=get_reg(i_regs->regmap,dops[i].rs1);
277718fa 3434 offset=cinfo[i].imm;
57871462 3435 if(s>=0) {
684b6816 3436 c = (i_regs->isconst >> s) & 1;
3437 if (c) {
3438 addr_const = constmap[i][s] + offset;
3439 memtarget = ((signed int)addr_const) < (signed int)(0x80000000 + RAM_SIZE);
af4ee1fe 3440 }
57871462 3441 }
3442 assert(tl>=0);
277718fa 3443 assert(addr >= 0);
684b6816 3444 reglist |= 1u << addr;
1edfcc68 3445 if(!c) {
277718fa 3446 emit_cmpimm(addr, RAM_SIZE);
b14b6a8f 3447 jaddr=out;
1edfcc68 3448 emit_jno(0);
3449 }
3450 else
3451 {
cf95b4f0 3452 if(!memtarget||!dops[i].rs1) {
b14b6a8f 3453 jaddr=out;
535d208a 3454 emit_jmp(0);
57871462 3455 }
535d208a 3456 }
37387d8b 3457 if (ram_offset)
3458 offset_reg = get_ro_reg(i_regs, 0);
535d208a 3459
277718fa 3460 emit_testimm(addr,2);
37387d8b 3461 case23=out;
535d208a 3462 emit_jne(0);
277718fa 3463 emit_testimm(addr,1);
df4dc2b1 3464 case1=out;
535d208a 3465 emit_jne(0);
3466 // 0
37387d8b 3467 if (dops[i].opcode == 0x2A) { // SWL
3468 // Write msb into least significant byte
3469 if (dops[i].rs2) emit_rorimm(tl, 24, tl);
277718fa 3470 do_store_byte(addr, tl, offset_reg);
37387d8b 3471 if (dops[i].rs2) emit_rorimm(tl, 8, tl);
535d208a 3472 }
37387d8b 3473 else if (dops[i].opcode == 0x2E) { // SWR
3474 // Write entire word
277718fa 3475 do_store_word(addr, 0, tl, offset_reg, 1);
535d208a 3476 }
37387d8b 3477 done0 = out;
535d208a 3478 emit_jmp(0);
3479 // 1
df4dc2b1 3480 set_jump_target(case1, out);
37387d8b 3481 if (dops[i].opcode == 0x2A) { // SWL
3482 // Write two msb into two least significant bytes
3483 if (dops[i].rs2) emit_rorimm(tl, 16, tl);
684b6816 3484 do_store_hword(addr, -1, tl, offset_reg, 1);
37387d8b 3485 if (dops[i].rs2) emit_rorimm(tl, 16, tl);
535d208a 3486 }
37387d8b 3487 else if (dops[i].opcode == 0x2E) { // SWR
3488 // Write 3 lsb into three most significant bytes
277718fa 3489 do_store_byte(addr, tl, offset_reg);
37387d8b 3490 if (dops[i].rs2) emit_rorimm(tl, 8, tl);
684b6816 3491 do_store_hword(addr, 1, tl, offset_reg, 1);
37387d8b 3492 if (dops[i].rs2) emit_rorimm(tl, 24, tl);
535d208a 3493 }
df4dc2b1 3494 done1=out;
535d208a 3495 emit_jmp(0);
37387d8b 3496 // 2,3
3497 set_jump_target(case23, out);
277718fa 3498 emit_testimm(addr,1);
37387d8b 3499 case3 = out;
535d208a 3500 emit_jne(0);
37387d8b 3501 // 2
cf95b4f0 3502 if (dops[i].opcode==0x2A) { // SWL
37387d8b 3503 // Write 3 msb into three least significant bytes
3504 if (dops[i].rs2) emit_rorimm(tl, 8, tl);
277718fa 3505 do_store_hword(addr, -2, tl, offset_reg, 1);
37387d8b 3506 if (dops[i].rs2) emit_rorimm(tl, 16, tl);
277718fa 3507 do_store_byte(addr, tl, offset_reg);
37387d8b 3508 if (dops[i].rs2) emit_rorimm(tl, 8, tl);
535d208a 3509 }
37387d8b 3510 else if (dops[i].opcode == 0x2E) { // SWR
3511 // Write two lsb into two most significant bytes
277718fa 3512 do_store_hword(addr, 0, tl, offset_reg, 1);
535d208a 3513 }
37387d8b 3514 done2 = out;
535d208a 3515 emit_jmp(0);
3516 // 3
df4dc2b1 3517 set_jump_target(case3, out);
37387d8b 3518 if (dops[i].opcode == 0x2A) { // SWL
684b6816 3519 do_store_word(addr, -3, tl, offset_reg, 1);
535d208a 3520 }
37387d8b 3521 else if (dops[i].opcode == 0x2E) { // SWR
277718fa 3522 do_store_byte(addr, tl, offset_reg);
535d208a 3523 }
df4dc2b1 3524 set_jump_target(done0, out);
3525 set_jump_target(done1, out);
3526 set_jump_target(done2, out);
37387d8b 3527 if (offset_reg == HOST_TEMPREG)
3528 host_tempreg_release();
684b6816 3529 if (!c || !memtarget)
277718fa 3530 add_stub_r(STORELR_STUB,jaddr,out,i,addr,i_regs,ccadj_,reglist);
684b6816 3531 if (!c || is_ram_addr(addr_const))
3532 do_store_smc_check(i, i_regs, reglist, addr);
57871462 3533}
3534
2330734f 3535static void cop0_assemble(int i, const struct regstat *i_regs, int ccadj_)
8062d65a 3536{
cf95b4f0 3537 if(dops[i].opcode2==0) // MFC0
8062d65a 3538 {
a5cd72d0 3539 signed char t=get_reg_w(i_regs->regmap, dops[i].rt1);
8062d65a 3540 u_int copr=(source[i]>>11)&0x1f;
cf95b4f0 3541 if(t>=0&&dops[i].rt1!=0) {
8062d65a 3542 emit_readword(&reg_cop0[copr],t);
3543 }
3544 }
cf95b4f0 3545 else if(dops[i].opcode2==4) // MTC0
8062d65a 3546 {
de6dbc52 3547 int s = get_reg(i_regs->regmap, dops[i].rs1);
3548 int cc = get_reg(i_regs->regmap, CCREG);
8062d65a 3549 char copr=(source[i]>>11)&0x1f;
3550 assert(s>=0);
cf95b4f0 3551 wb_register(dops[i].rs1,i_regs->regmap,i_regs->dirty);
de6dbc52 3552 if (copr == 12 || copr == 13) {
8062d65a 3553 emit_readword(&last_count,HOST_TEMPREG);
de6dbc52 3554 if (cc != HOST_CCREG)
3555 emit_loadreg(CCREG, HOST_CCREG);
3556 emit_add(HOST_CCREG, HOST_TEMPREG, HOST_CCREG);
3557 emit_addimm(HOST_CCREG, ccadj_ + 2, HOST_CCREG);
3558 emit_writeword(HOST_CCREG, &psxRegs.cycle);
8062d65a 3559 if (is_delayslot) {
3560 // burn cycles to cause cc_interrupt, which will
3561 // reschedule next_interupt. Relies on CCREG from above.
3562 assem_debug("MTC0 DS %d\n", copr);
3563 emit_writeword(HOST_CCREG,&last_count);
3564 emit_movimm(0,HOST_CCREG);
3565 emit_storereg(CCREG,HOST_CCREG);
cf95b4f0 3566 emit_loadreg(dops[i].rs1,1);
8062d65a 3567 emit_movimm(copr,0);
2a014d73 3568 emit_far_call(pcsx_mtc0_ds);
cf95b4f0 3569 emit_loadreg(dops[i].rs1,s);
8062d65a 3570 return;
3571 }
3572 emit_movimm(start+i*4+4,HOST_TEMPREG);
3573 emit_writeword(HOST_TEMPREG,&pcaddr);
3574 emit_movimm(0,HOST_TEMPREG);
3575 emit_writeword(HOST_TEMPREG,&pending_exception);
3576 }
de6dbc52 3577 if( s != 1)
3578 emit_mov(s, 1);
3579 emit_movimm(copr, 0);
2a014d73 3580 emit_far_call(pcsx_mtc0);
de6dbc52 3581 if (copr == 12 || copr == 13) {
d7546062 3582 emit_readword(&psxRegs.cycle,HOST_CCREG);
de6dbc52 3583 emit_readword(&last_count,HOST_TEMPREG);
8062d65a 3584 emit_sub(HOST_CCREG,HOST_TEMPREG,HOST_CCREG);
de6dbc52 3585 //emit_writeword(HOST_TEMPREG,&last_count);
8062d65a 3586 assert(!is_delayslot);
9b495f6e 3587 emit_readword(&pending_exception,HOST_TEMPREG);
3588 emit_test(HOST_TEMPREG,HOST_TEMPREG);
d1e4ebd9 3589 void *jaddr = out;
3590 emit_jeq(0);
3591 emit_readword(&pcaddr, 0);
104df9d3 3592 emit_far_call(ndrc_get_addr_ht);
d1e4ebd9 3593 emit_jmpreg(0);
3594 set_jump_target(jaddr, out);
de6dbc52 3595 emit_addimm(HOST_CCREG, -ccadj_ - 2, HOST_CCREG);
3596 if (cc != HOST_CCREG)
3597 emit_storereg(CCREG, HOST_CCREG);
8062d65a 3598 }
cf95b4f0 3599 emit_loadreg(dops[i].rs1,s);
8062d65a 3600 }
8062d65a 3601}
3602
277718fa 3603static void rfe_assemble(int i, const struct regstat *i_regs)
8062d65a 3604{
a5cd72d0 3605 emit_readword(&psxRegs.CP0.n.SR, 0);
3606 emit_andimm(0, 0x3c, 1);
3607 emit_andimm(0, ~0xf, 0);
3608 emit_orrshr_imm(1, 2, 0);
3609 emit_writeword(0, &psxRegs.CP0.n.SR);
8062d65a 3610}
3611
e3c6bdb5 3612static int cop2_is_stalling_op(int i, int *cycles)
3613{
cf95b4f0 3614 if (dops[i].opcode == 0x3a) { // SWC2
e3c6bdb5 3615 *cycles = 0;
3616 return 1;
3617 }
cf95b4f0 3618 if (dops[i].itype == COP2 && (dops[i].opcode2 == 0 || dops[i].opcode2 == 2)) { // MFC2/CFC2
e3c6bdb5 3619 *cycles = 0;
3620 return 1;
3621 }
cf95b4f0 3622 if (dops[i].itype == C2OP) {
e3c6bdb5 3623 *cycles = gte_cycletab[source[i] & 0x3f];
3624 return 1;
3625 }
3626 // ... what about MTC2/CTC2/LWC2?
3627 return 0;
3628}
3629
3630#if 0
3631static void log_gte_stall(int stall, u_int cycle)
3632{
3633 if ((u_int)stall <= 44)
3634 printf("x stall %2d %u\n", stall, cycle + last_count);
e3c6bdb5 3635}
3636
3637static void emit_log_gte_stall(int i, int stall, u_int reglist)
3638{
3639 save_regs(reglist);
3640 if (stall > 0)
3641 emit_movimm(stall, 0);
3642 else
3643 emit_mov(HOST_TEMPREG, 0);
277718fa 3644 emit_addimm(HOST_CCREG, cinfo[i].ccadj, 1);
e3c6bdb5 3645 emit_far_call(log_gte_stall);
3646 restore_regs(reglist);
3647}
3648#endif
3649
32631e6a 3650static void cop2_do_stall_check(u_int op, int i, const struct regstat *i_regs, u_int reglist)
81dbbf4c 3651{
e3c6bdb5 3652 int j = i, other_gte_op_cycles = -1, stall = -MAXBLOCK, cycles_passed;
3653 int rtmp = reglist_find_free(reglist);
3654
32631e6a 3655 if (HACK_ENABLED(NDHACK_NO_STALLS))
81dbbf4c 3656 return;
81dbbf4c 3657 if (get_reg(i_regs->regmap, CCREG) != HOST_CCREG) {
3658 // happens occasionally... cc evicted? Don't bother then
3659 //printf("no cc %08x\n", start + i*4);
3660 return;
3661 }
cf95b4f0 3662 if (!dops[i].bt) {
e3c6bdb5 3663 for (j = i - 1; j >= 0; j--) {
cf95b4f0 3664 //if (dops[j].is_ds) break;
3665 if (cop2_is_stalling_op(j, &other_gte_op_cycles) || dops[j].bt)
e3c6bdb5 3666 break;
277718fa 3667 if (j > 0 && cinfo[j - 1].ccadj > cinfo[j].ccadj)
2330734f 3668 break;
e3c6bdb5 3669 }
32631e6a 3670 j = max(j, 0);
e3c6bdb5 3671 }
277718fa 3672 cycles_passed = cinfo[i].ccadj - cinfo[j].ccadj;
e3c6bdb5 3673 if (other_gte_op_cycles >= 0)
3674 stall = other_gte_op_cycles - cycles_passed;
3675 else if (cycles_passed >= 44)
3676 stall = 0; // can't stall
3677 if (stall == -MAXBLOCK && rtmp >= 0) {
3678 // unknown stall, do the expensive runtime check
32631e6a 3679 assem_debug("; cop2_do_stall_check\n");
e3c6bdb5 3680#if 0 // too slow
3681 save_regs(reglist);
3682 emit_movimm(gte_cycletab[op], 0);
277718fa 3683 emit_addimm(HOST_CCREG, cinfo[i].ccadj, 1);
e3c6bdb5 3684 emit_far_call(call_gteStall);
3685 restore_regs(reglist);
3686#else
3687 host_tempreg_acquire();
3688 emit_readword(&psxRegs.gteBusyCycle, rtmp);
277718fa 3689 emit_addimm(rtmp, -cinfo[i].ccadj, rtmp);
e3c6bdb5 3690 emit_sub(rtmp, HOST_CCREG, HOST_TEMPREG);
3691 emit_cmpimm(HOST_TEMPREG, 44);
3692 emit_cmovb_reg(rtmp, HOST_CCREG);
3693 //emit_log_gte_stall(i, 0, reglist);
3694 host_tempreg_release();
3695#endif
3696 }
3697 else if (stall > 0) {
3698 //emit_log_gte_stall(i, stall, reglist);
3699 emit_addimm(HOST_CCREG, stall, HOST_CCREG);
3700 }
3701
3702 // save gteBusyCycle, if needed
3703 if (gte_cycletab[op] == 0)
3704 return;
3705 other_gte_op_cycles = -1;
3706 for (j = i + 1; j < slen; j++) {
3707 if (cop2_is_stalling_op(j, &other_gte_op_cycles))
3708 break;
fe807a8a 3709 if (dops[j].is_jump) {
e3c6bdb5 3710 // check ds
3711 if (j + 1 < slen && cop2_is_stalling_op(j + 1, &other_gte_op_cycles))
3712 j++;
3713 break;
3714 }
3715 }
3716 if (other_gte_op_cycles >= 0)
3717 // will handle stall when assembling that op
3718 return;
277718fa 3719 cycles_passed = cinfo[min(j, slen -1)].ccadj - cinfo[i].ccadj;
e3c6bdb5 3720 if (cycles_passed >= 44)
3721 return;
3722 assem_debug("; save gteBusyCycle\n");
3723 host_tempreg_acquire();
3724#if 0
3725 emit_readword(&last_count, HOST_TEMPREG);
3726 emit_add(HOST_TEMPREG, HOST_CCREG, HOST_TEMPREG);
277718fa 3727 emit_addimm(HOST_TEMPREG, cinfo[i].ccadj, HOST_TEMPREG);
e3c6bdb5 3728 emit_addimm(HOST_TEMPREG, gte_cycletab[op]), HOST_TEMPREG);
3729 emit_writeword(HOST_TEMPREG, &psxRegs.gteBusyCycle);
3730#else
277718fa 3731 emit_addimm(HOST_CCREG, cinfo[i].ccadj + gte_cycletab[op], HOST_TEMPREG);
e3c6bdb5 3732 emit_writeword(HOST_TEMPREG, &psxRegs.gteBusyCycle);
3733#endif
3734 host_tempreg_release();
81dbbf4c 3735}
3736
32631e6a 3737static int is_mflohi(int i)
3738{
cf95b4f0 3739 return (dops[i].itype == MOV && (dops[i].rs1 == HIREG || dops[i].rs1 == LOREG));
32631e6a 3740}
3741
3742static int check_multdiv(int i, int *cycles)
3743{
cf95b4f0 3744 if (dops[i].itype != MULTDIV)
32631e6a 3745 return 0;
cf95b4f0 3746 if (dops[i].opcode2 == 0x18 || dops[i].opcode2 == 0x19) // MULT(U)
32631e6a 3747 *cycles = 11; // approx from 7 11 14
3748 else
3749 *cycles = 37;
3750 return 1;
3751}
3752
2330734f 3753static void multdiv_prepare_stall(int i, const struct regstat *i_regs, int ccadj_)
32631e6a 3754{
3755 int j, found = 0, c = 0;
3756 if (HACK_ENABLED(NDHACK_NO_STALLS))
3757 return;
3758 if (get_reg(i_regs->regmap, CCREG) != HOST_CCREG) {
3759 // happens occasionally... cc evicted? Don't bother then
3760 return;
3761 }
3762 for (j = i + 1; j < slen; j++) {
cf95b4f0 3763 if (dops[j].bt)
32631e6a 3764 break;
3765 if ((found = is_mflohi(j)))
3766 break;
fe807a8a 3767 if (dops[j].is_jump) {
32631e6a 3768 // check ds
3769 if (j + 1 < slen && (found = is_mflohi(j + 1)))
3770 j++;
3771 break;
3772 }
3773 }
3774 if (found)
3775 // handle all in multdiv_do_stall()
3776 return;
3777 check_multdiv(i, &c);
3778 assert(c > 0);
3779 assem_debug("; muldiv prepare stall %d\n", c);
3780 host_tempreg_acquire();
2330734f 3781 emit_addimm(HOST_CCREG, ccadj_ + c, HOST_TEMPREG);
32631e6a 3782 emit_writeword(HOST_TEMPREG, &psxRegs.muldivBusyCycle);
3783 host_tempreg_release();
3784}
3785
3786static void multdiv_do_stall(int i, const struct regstat *i_regs)
3787{
3788 int j, known_cycles = 0;
3789 u_int reglist = get_host_reglist(i_regs->regmap);
9de8a0c3 3790 int rtmp = get_reg_temp(i_regs->regmap);
32631e6a 3791 if (rtmp < 0)
3792 rtmp = reglist_find_free(reglist);
3793 if (HACK_ENABLED(NDHACK_NO_STALLS))
3794 return;
3795 if (get_reg(i_regs->regmap, CCREG) != HOST_CCREG || rtmp < 0) {
3796 // happens occasionally... cc evicted? Don't bother then
3797 //printf("no cc/rtmp %08x\n", start + i*4);
3798 return;
3799 }
cf95b4f0 3800 if (!dops[i].bt) {
32631e6a 3801 for (j = i - 1; j >= 0; j--) {
cf95b4f0 3802 if (dops[j].is_ds) break;
2330734f 3803 if (check_multdiv(j, &known_cycles))
32631e6a 3804 break;
3805 if (is_mflohi(j))
3806 // already handled by this op
3807 return;
277718fa 3808 if (dops[j].bt || (j > 0 && cinfo[j - 1].ccadj > cinfo[j].ccadj))
2330734f 3809 break;
32631e6a 3810 }
3811 j = max(j, 0);
3812 }
3813 if (known_cycles > 0) {
277718fa 3814 known_cycles -= cinfo[i].ccadj - cinfo[j].ccadj;
32631e6a 3815 assem_debug("; muldiv stall resolved %d\n", known_cycles);
3816 if (known_cycles > 0)
3817 emit_addimm(HOST_CCREG, known_cycles, HOST_CCREG);
3818 return;
3819 }
3820 assem_debug("; muldiv stall unresolved\n");
3821 host_tempreg_acquire();
3822 emit_readword(&psxRegs.muldivBusyCycle, rtmp);
277718fa 3823 emit_addimm(rtmp, -cinfo[i].ccadj, rtmp);
32631e6a 3824 emit_sub(rtmp, HOST_CCREG, HOST_TEMPREG);
3825 emit_cmpimm(HOST_TEMPREG, 37);
3826 emit_cmovb_reg(rtmp, HOST_CCREG);
3827 //emit_log_gte_stall(i, 0, reglist);
3828 host_tempreg_release();
3829}
3830
8062d65a 3831static void cop2_get_dreg(u_int copr,signed char tl,signed char temp)
3832{
3833 switch (copr) {
3834 case 1:
3835 case 3:
3836 case 5:
3837 case 8:
3838 case 9:
3839 case 10:
3840 case 11:
3841 emit_readword(&reg_cop2d[copr],tl);
3842 emit_signextend16(tl,tl);
3843 emit_writeword(tl,&reg_cop2d[copr]); // hmh
3844 break;
3845 case 7:
3846 case 16:
3847 case 17:
3848 case 18:
3849 case 19:
3850 emit_readword(&reg_cop2d[copr],tl);
3851 emit_andimm(tl,0xffff,tl);
3852 emit_writeword(tl,&reg_cop2d[copr]);
3853 break;
3854 case 15:
3855 emit_readword(&reg_cop2d[14],tl); // SXY2
3856 emit_writeword(tl,&reg_cop2d[copr]);
3857 break;
3858 case 28:
3859 case 29:
3968e69e 3860 c2op_mfc2_29_assemble(tl,temp);
8062d65a 3861 break;
3862 default:
3863 emit_readword(&reg_cop2d[copr],tl);
3864 break;
3865 }
3866}
3867
3868static void cop2_put_dreg(u_int copr,signed char sl,signed char temp)
3869{
3870 switch (copr) {
3871 case 15:
3872 emit_readword(&reg_cop2d[13],temp); // SXY1
3873 emit_writeword(sl,&reg_cop2d[copr]);
3874 emit_writeword(temp,&reg_cop2d[12]); // SXY0
3875 emit_readword(&reg_cop2d[14],temp); // SXY2
3876 emit_writeword(sl,&reg_cop2d[14]);
3877 emit_writeword(temp,&reg_cop2d[13]); // SXY1
3878 break;
3879 case 28:
3880 emit_andimm(sl,0x001f,temp);
3881 emit_shlimm(temp,7,temp);
3882 emit_writeword(temp,&reg_cop2d[9]);
3883 emit_andimm(sl,0x03e0,temp);
3884 emit_shlimm(temp,2,temp);
3885 emit_writeword(temp,&reg_cop2d[10]);
3886 emit_andimm(sl,0x7c00,temp);
3887 emit_shrimm(temp,3,temp);
3888 emit_writeword(temp,&reg_cop2d[11]);
3889 emit_writeword(sl,&reg_cop2d[28]);
3890 break;
3891 case 30:
3968e69e 3892 emit_xorsar_imm(sl,sl,31,temp);
be516ebe 3893#if defined(HAVE_ARMV5) || defined(__aarch64__)
8062d65a 3894 emit_clz(temp,temp);
3895#else
3896 emit_movs(temp,HOST_TEMPREG);
3897 emit_movimm(0,temp);
3898 emit_jeq((int)out+4*4);
3899 emit_addpl_imm(temp,1,temp);
3900 emit_lslpls_imm(HOST_TEMPREG,1,HOST_TEMPREG);
3901 emit_jns((int)out-2*4);
3902#endif
3903 emit_writeword(sl,&reg_cop2d[30]);
3904 emit_writeword(temp,&reg_cop2d[31]);
3905 break;
3906 case 31:
3907 break;
3908 default:
3909 emit_writeword(sl,&reg_cop2d[copr]);
3910 break;
3911 }
3912}
3913
2330734f 3914static void c2ls_assemble(int i, const struct regstat *i_regs, int ccadj_)
b9b61529 3915{
3916 int s,tl;
3917 int ar;
3918 int offset;
1fd1aceb 3919 int memtarget=0,c=0;
b14b6a8f 3920 void *jaddr2=NULL;
3921 enum stub_type type;
37387d8b 3922 int offset_reg = -1;
3923 int fastio_reg_override = -1;
684b6816 3924 u_int addr_const = ~0;
81dbbf4c 3925 u_int reglist=get_host_reglist(i_regs->regmap);
b9b61529 3926 u_int copr=(source[i]>>16)&0x1f;
cf95b4f0 3927 s=get_reg(i_regs->regmap,dops[i].rs1);
b9b61529 3928 tl=get_reg(i_regs->regmap,FTEMP);
277718fa 3929 offset=cinfo[i].imm;
b9b61529 3930 assert(tl>=0);
b9b61529 3931
b9b61529 3932 if(i_regs->regmap[HOST_CCREG]==CCREG)
3933 reglist&=~(1<<HOST_CCREG);
3934
3935 // get the address
277718fa 3936 ar = cinfo[i].addr;
3937 assert(ar >= 0);
cf95b4f0 3938 if (dops[i].opcode==0x3a) { // SWC2
277718fa 3939 reglist |= 1<<ar;
b9b61529 3940 }
684b6816 3941 if (s >= 0) {
3942 c = (i_regs->isconst >> s) & 1;
3943 if (c) {
3944 addr_const = constmap[i][s] + offset;
3945 memtarget = ((signed int)addr_const) < (signed int)(0x80000000 + RAM_SIZE);
3946 }
3947 }
b9b61529 3948
32631e6a 3949 cop2_do_stall_check(0, i, i_regs, reglist);
3950
cf95b4f0 3951 if (dops[i].opcode==0x3a) { // SWC2
3968e69e 3952 cop2_get_dreg(copr,tl,-1);
1fd1aceb 3953 type=STOREW_STUB;
b9b61529 3954 }
1fd1aceb 3955 else
b9b61529 3956 type=LOADW_STUB;
1fd1aceb 3957
3958 if(c&&!memtarget) {
b14b6a8f 3959 jaddr2=out;
1fd1aceb 3960 emit_jmp(0); // inline_readstub/inline_writestub?
b9b61529 3961 }
1fd1aceb 3962 else {
3963 if(!c) {
37387d8b 3964 jaddr2 = emit_fastpath_cmp_jump(i, i_regs, ar,
277718fa 3965 &offset_reg, &fastio_reg_override, ccadj_);
37387d8b 3966 }
3967 else if (ram_offset && memtarget) {
3968 offset_reg = get_ro_reg(i_regs, 0);
3969 }
3970 switch (dops[i].opcode) {
3971 case 0x32: { // LWC2
3972 int a = ar;
3973 if (fastio_reg_override >= 0)
3974 a = fastio_reg_override;
3975 do_load_word(a, tl, offset_reg);
3976 break;
1fd1aceb 3977 }
37387d8b 3978 case 0x3a: { // SWC2
1fd1aceb 3979 #ifdef DESTRUCTIVE_SHIFT
3980 if(!offset&&!c&&s>=0) emit_mov(s,ar);
3981 #endif
37387d8b 3982 int a = ar;
3983 if (fastio_reg_override >= 0)
3984 a = fastio_reg_override;
3985 do_store_word(a, 0, tl, offset_reg, 1);
3986 break;
3987 }
3988 default:
3989 assert(0);
1fd1aceb 3990 }
b9b61529 3991 }
37387d8b 3992 if (fastio_reg_override == HOST_TEMPREG || offset_reg == HOST_TEMPREG)
d1e4ebd9 3993 host_tempreg_release();
b9b61529 3994 if(jaddr2)
2330734f 3995 add_stub_r(type,jaddr2,out,i,ar,i_regs,ccadj_,reglist);
684b6816 3996 if (dops[i].opcode == 0x3a && (!c || is_ram_addr(addr_const))) // SWC2
9b495f6e 3997 do_store_smc_check(i, i_regs, reglist, ar);
684b6816 3998 if (dops[i].opcode == 0x32) { // LWC2
d1e4ebd9 3999 host_tempreg_acquire();
b9b61529 4000 cop2_put_dreg(copr,tl,HOST_TEMPREG);
d1e4ebd9 4001 host_tempreg_release();
b9b61529 4002 }
4003}
4004
81dbbf4c 4005static void cop2_assemble(int i, const struct regstat *i_regs)
8062d65a 4006{
81dbbf4c 4007 u_int copr = (source[i]>>11) & 0x1f;
9de8a0c3 4008 signed char temp = get_reg_temp(i_regs->regmap);
81dbbf4c 4009
32631e6a 4010 if (!HACK_ENABLED(NDHACK_NO_STALLS)) {
4011 u_int reglist = reglist_exclude(get_host_reglist(i_regs->regmap), temp, -1);
cf95b4f0 4012 if (dops[i].opcode2 == 0 || dops[i].opcode2 == 2) { // MFC2/CFC2
4013 signed char tl = get_reg(i_regs->regmap, dops[i].rt1);
32631e6a 4014 reglist = reglist_exclude(reglist, tl, -1);
81dbbf4c 4015 }
32631e6a 4016 cop2_do_stall_check(0, i, i_regs, reglist);
81dbbf4c 4017 }
cf95b4f0 4018 if (dops[i].opcode2==0) { // MFC2
a5cd72d0 4019 signed char tl=get_reg_w(i_regs->regmap, dops[i].rt1);
cf95b4f0 4020 if(tl>=0&&dops[i].rt1!=0)
8062d65a 4021 cop2_get_dreg(copr,tl,temp);
4022 }
cf95b4f0 4023 else if (dops[i].opcode2==4) { // MTC2
4024 signed char sl=get_reg(i_regs->regmap,dops[i].rs1);
8062d65a 4025 cop2_put_dreg(copr,sl,temp);
4026 }
cf95b4f0 4027 else if (dops[i].opcode2==2) // CFC2
8062d65a 4028 {
a5cd72d0 4029 signed char tl=get_reg_w(i_regs->regmap, dops[i].rt1);
cf95b4f0 4030 if(tl>=0&&dops[i].rt1!=0)
8062d65a 4031 emit_readword(&reg_cop2c[copr],tl);
4032 }
cf95b4f0 4033 else if (dops[i].opcode2==6) // CTC2
8062d65a 4034 {
cf95b4f0 4035 signed char sl=get_reg(i_regs->regmap,dops[i].rs1);
8062d65a 4036 switch(copr) {
4037 case 4:
4038 case 12:
4039 case 20:
4040 case 26:
4041 case 27:
4042 case 29:
4043 case 30:
4044 emit_signextend16(sl,temp);
4045 break;
4046 case 31:
3968e69e 4047 c2op_ctc2_31_assemble(sl,temp);
8062d65a 4048 break;
4049 default:
4050 temp=sl;
4051 break;
4052 }
4053 emit_writeword(temp,&reg_cop2c[copr]);
4054 assert(sl>=0);
4055 }
4056}
4057
3968e69e 4058static void do_unalignedwritestub(int n)
4059{
4060 assem_debug("do_unalignedwritestub %x\n",start+stubs[n].a*4);
4061 literal_pool(256);
4062 set_jump_target(stubs[n].addr, out);
4063
4064 int i=stubs[n].a;
4065 struct regstat *i_regs=(struct regstat *)stubs[n].c;
4066 int addr=stubs[n].b;
4067 u_int reglist=stubs[n].e;
4068 signed char *i_regmap=i_regs->regmap;
4069 int temp2=get_reg(i_regmap,FTEMP);
4070 int rt;
cf95b4f0 4071 rt=get_reg(i_regmap,dops[i].rs2);
3968e69e 4072 assert(rt>=0);
4073 assert(addr>=0);
cf95b4f0 4074 assert(dops[i].opcode==0x2a||dops[i].opcode==0x2e); // SWL/SWR only implemented
3968e69e 4075 reglist|=(1<<addr);
4076 reglist&=~(1<<temp2);
4077
3968e69e 4078 // don't bother with it and call write handler
4079 save_regs(reglist);
4080 pass_args(addr,rt);
4081 int cc=get_reg(i_regmap,CCREG);
4082 if(cc<0)
4083 emit_loadreg(CCREG,2);
2330734f 4084 emit_addimm(cc<0?2:cc,(int)stubs[n].d+1,2);
de6dbc52 4085 emit_movimm(start + i*4,3);
4086 emit_writeword(3,&psxRegs.pc);
cf95b4f0 4087 emit_far_call((dops[i].opcode==0x2a?jump_handle_swl:jump_handle_swr));
2330734f 4088 emit_addimm(0,-((int)stubs[n].d+1),cc<0?2:cc);
3968e69e 4089 if(cc<0)
4090 emit_storereg(CCREG,2);
4091 restore_regs(reglist);
4092 emit_jmp(stubs[n].retaddr); // return address
3968e69e 4093}
4094
a5cd72d0 4095static void do_overflowstub(int n)
4096{
4097 assem_debug("do_overflowstub %x\n", start + (u_int)stubs[n].a * 4);
4098 literal_pool(24);
4099 int i = stubs[n].a;
4100 struct regstat *i_regs = (struct regstat *)stubs[n].c;
4101 int ccadj = stubs[n].d;
4102 set_jump_target(stubs[n].addr, out);
4103 wb_dirtys(regs[i].regmap, regs[i].dirty);
4104 exception_assemble(i, i_regs, ccadj);
4105}
4106
277718fa 4107static void do_alignmentstub(int n)
4108{
4109 assem_debug("do_alignmentstub %x\n", start + (u_int)stubs[n].a * 4);
4110 literal_pool(24);
4111 int i = stubs[n].a;
4112 struct regstat *i_regs = (struct regstat *)stubs[n].c;
4113 int ccadj = stubs[n].d;
4114 int is_store = dops[i].itype == STORE || dops[i].opcode == 0x3A; // SWC2
4115 int cause = (dops[i].opcode & 3) << 28;
4116 cause |= is_store ? (R3000E_AdES << 2) : (R3000E_AdEL << 2);
4117 set_jump_target(stubs[n].addr, out);
4118 wb_dirtys(regs[i].regmap, regs[i].dirty);
4119 if (stubs[n].b != 1)
4120 emit_mov(stubs[n].b, 1); // faulting address
4121 emit_movimm(cause, 0);
4122 exception_assemble(i, i_regs, ccadj);
4123}
4124
57871462 4125#ifndef multdiv_assemble
4126void multdiv_assemble(int i,struct regstat *i_regs)
4127{
4128 printf("Need multdiv_assemble for this architecture.\n");
7c3a5182 4129 abort();
57871462 4130}
4131#endif
4132
2330734f 4133static void mov_assemble(int i, const struct regstat *i_regs)
57871462 4134{
cf95b4f0 4135 //if(dops[i].opcode2==0x10||dops[i].opcode2==0x12) { // MFHI/MFLO
4136 //if(dops[i].opcode2==0x11||dops[i].opcode2==0x13) { // MTHI/MTLO
4137 if(dops[i].rt1) {
7c3a5182 4138 signed char sl,tl;
a5cd72d0 4139 tl=get_reg_w(i_regs->regmap, dops[i].rt1);
57871462 4140 //assert(tl>=0);
4141 if(tl>=0) {
cf95b4f0 4142 sl=get_reg(i_regs->regmap,dops[i].rs1);
57871462 4143 if(sl>=0) emit_mov(sl,tl);
cf95b4f0 4144 else emit_loadreg(dops[i].rs1,tl);
57871462 4145 }
4146 }
cf95b4f0 4147 if (dops[i].rs1 == HIREG || dops[i].rs1 == LOREG) // MFHI/MFLO
32631e6a 4148 multdiv_do_stall(i, i_regs);
57871462 4149}
4150
3968e69e 4151// call interpreter, exception handler, things that change pc/regs/cycles ...
2330734f 4152static void call_c_cpu_handler(int i, const struct regstat *i_regs, int ccadj_, u_int pc, void *func)
57871462 4153{
4154 signed char ccreg=get_reg(i_regs->regmap,CCREG);
4155 assert(ccreg==HOST_CCREG);
4156 assert(!is_delayslot);
581335b0 4157 (void)ccreg;
3968e69e 4158
4159 emit_movimm(pc,3); // Get PC
4160 emit_readword(&last_count,2);
4161 emit_writeword(3,&psxRegs.pc);
2330734f 4162 emit_addimm(HOST_CCREG,ccadj_,HOST_CCREG);
3968e69e 4163 emit_add(2,HOST_CCREG,2);
4164 emit_writeword(2,&psxRegs.cycle);
bc7c5acb 4165 emit_addimm_ptr(FP,(u_char *)&psxRegs - (u_char *)&dynarec_local,0);
2a014d73 4166 emit_far_call(func);
4167 emit_far_jump(jump_to_new_pc);
3968e69e 4168}
4169
a5cd72d0 4170static void exception_assemble(int i, const struct regstat *i_regs, int ccadj_)
3968e69e 4171{
d1150cd6 4172 // 'break' tends to be littered around to catch things like
4173 // division by 0 and is almost never executed, so don't emit much code here
a5cd72d0 4174 void *func;
4175 if (dops[i].itype == ALU || dops[i].itype == IMM16)
4176 func = is_delayslot ? jump_overflow_ds : jump_overflow;
277718fa 4177 else if (dops[i].itype == LOAD || dops[i].itype == STORE)
4178 func = is_delayslot ? jump_addrerror_ds : jump_addrerror;
a5cd72d0 4179 else if (dops[i].opcode2 == 0x0C)
4180 func = is_delayslot ? jump_syscall_ds : jump_syscall;
4181 else
4182 func = is_delayslot ? jump_break_ds : jump_break;
277718fa 4183 if (get_reg(i_regs->regmap, CCREG) != HOST_CCREG) // evicted
4184 emit_loadreg(CCREG, HOST_CCREG);
d1150cd6 4185 emit_movimm(start + i*4, 2); // pc
4186 emit_addimm(HOST_CCREG, ccadj_ + CLOCK_ADJUST(1), HOST_CCREG);
4187 emit_far_jump(func);
7139f3c8 4188}
4189
bc7c5acb 4190static void hlecall_bad()
4191{
a5cd72d0 4192 assert(0);
bc7c5acb 4193}
4194
2330734f 4195static void hlecall_assemble(int i, const struct regstat *i_regs, int ccadj_)
7139f3c8 4196{
bc7c5acb 4197 void *hlefunc = hlecall_bad;
dd79da89 4198 uint32_t hleCode = source[i] & 0x03ffffff;
3968e69e 4199 if (hleCode < ARRAY_SIZE(psxHLEt))
4200 hlefunc = psxHLEt[hleCode];
4201
2330734f 4202 call_c_cpu_handler(i, i_regs, ccadj_, start + i*4+4, hlefunc);
57871462 4203}
4204
2330734f 4205static void intcall_assemble(int i, const struct regstat *i_regs, int ccadj_)
1e973cb0 4206{
2330734f 4207 call_c_cpu_handler(i, i_regs, ccadj_, start + i*4, execI);
1e973cb0 4208}
4209
8062d65a 4210static void speculate_mov(int rs,int rt)
4211{
4212 if(rt!=0) {
4213 smrv_strong_next|=1<<rt;
4214 smrv[rt]=smrv[rs];
4215 }
4216}
4217
4218static void speculate_mov_weak(int rs,int rt)
4219{
4220 if(rt!=0) {
4221 smrv_weak_next|=1<<rt;
4222 smrv[rt]=smrv[rs];
4223 }
4224}
4225
4226static void speculate_register_values(int i)
4227{
4228 if(i==0) {
4229 memcpy(smrv,psxRegs.GPR.r,sizeof(smrv));
4230 // gp,sp are likely to stay the same throughout the block
4231 smrv_strong_next=(1<<28)|(1<<29)|(1<<30);
4232 smrv_weak_next=~smrv_strong_next;
4233 //printf(" llr %08x\n", smrv[4]);
4234 }
4235 smrv_strong=smrv_strong_next;
4236 smrv_weak=smrv_weak_next;
cf95b4f0 4237 switch(dops[i].itype) {
8062d65a 4238 case ALU:
cf95b4f0 4239 if ((smrv_strong>>dops[i].rs1)&1) speculate_mov(dops[i].rs1,dops[i].rt1);
4240 else if((smrv_strong>>dops[i].rs2)&1) speculate_mov(dops[i].rs2,dops[i].rt1);
4241 else if((smrv_weak>>dops[i].rs1)&1) speculate_mov_weak(dops[i].rs1,dops[i].rt1);
4242 else if((smrv_weak>>dops[i].rs2)&1) speculate_mov_weak(dops[i].rs2,dops[i].rt1);
8062d65a 4243 else {
cf95b4f0 4244 smrv_strong_next&=~(1<<dops[i].rt1);
4245 smrv_weak_next&=~(1<<dops[i].rt1);
8062d65a 4246 }
4247 break;
4248 case SHIFTIMM:
cf95b4f0 4249 smrv_strong_next&=~(1<<dops[i].rt1);
4250 smrv_weak_next&=~(1<<dops[i].rt1);
8062d65a 4251 // fallthrough
4252 case IMM16:
cf95b4f0 4253 if(dops[i].rt1&&is_const(&regs[i],dops[i].rt1)) {
de6dbc52 4254 int hr = get_reg_w(regs[i].regmap, dops[i].rt1);
4255 u_int value;
8062d65a 4256 if(hr>=0) {
4257 if(get_final_value(hr,i,&value))
cf95b4f0 4258 smrv[dops[i].rt1]=value;
4259 else smrv[dops[i].rt1]=constmap[i][hr];
4260 smrv_strong_next|=1<<dops[i].rt1;
8062d65a 4261 }
4262 }
4263 else {
cf95b4f0 4264 if ((smrv_strong>>dops[i].rs1)&1) speculate_mov(dops[i].rs1,dops[i].rt1);
4265 else if((smrv_weak>>dops[i].rs1)&1) speculate_mov_weak(dops[i].rs1,dops[i].rt1);
8062d65a 4266 }
4267 break;
4268 case LOAD:
cf95b4f0 4269 if(start<0x2000&&(dops[i].rt1==26||(smrv[dops[i].rt1]>>24)==0xa0)) {
8062d65a 4270 // special case for BIOS
cf95b4f0 4271 smrv[dops[i].rt1]=0xa0000000;
4272 smrv_strong_next|=1<<dops[i].rt1;
8062d65a 4273 break;
4274 }
4275 // fallthrough
4276 case SHIFT:
4277 case LOADLR:
4278 case MOV:
cf95b4f0 4279 smrv_strong_next&=~(1<<dops[i].rt1);
4280 smrv_weak_next&=~(1<<dops[i].rt1);
8062d65a 4281 break;
4282 case COP0:
4283 case COP2:
cf95b4f0 4284 if(dops[i].opcode2==0||dops[i].opcode2==2) { // MFC/CFC
4285 smrv_strong_next&=~(1<<dops[i].rt1);
4286 smrv_weak_next&=~(1<<dops[i].rt1);
8062d65a 4287 }
4288 break;
4289 case C2LS:
cf95b4f0 4290 if (dops[i].opcode==0x32) { // LWC2
4291 smrv_strong_next&=~(1<<dops[i].rt1);
4292 smrv_weak_next&=~(1<<dops[i].rt1);
8062d65a 4293 }
4294 break;
4295 }
4296#if 0
4297 int r=4;
4298 printf("x %08x %08x %d %d c %08x %08x\n",smrv[r],start+i*4,
4299 ((smrv_strong>>r)&1),(smrv_weak>>r)&1,regs[i].isconst,regs[i].wasconst);
4300#endif
4301}
4302
2330734f 4303static void ujump_assemble(int i, const struct regstat *i_regs);
4304static void rjump_assemble(int i, const struct regstat *i_regs);
4305static void cjump_assemble(int i, const struct regstat *i_regs);
4306static void sjump_assemble(int i, const struct regstat *i_regs);
2330734f 4307
4308static int assemble(int i, const struct regstat *i_regs, int ccadj_)
57871462 4309{
2330734f 4310 int ds = 0;
4311 switch (dops[i].itype) {
57871462 4312 case ALU:
a5cd72d0 4313 alu_assemble(i, i_regs, ccadj_);
2330734f 4314 break;
57871462 4315 case IMM16:
a5cd72d0 4316 imm16_assemble(i, i_regs, ccadj_);
2330734f 4317 break;
57871462 4318 case SHIFT:
2330734f 4319 shift_assemble(i, i_regs);
4320 break;
57871462 4321 case SHIFTIMM:
2330734f 4322 shiftimm_assemble(i, i_regs);
4323 break;
57871462 4324 case LOAD:
2330734f 4325 load_assemble(i, i_regs, ccadj_);
4326 break;
57871462 4327 case LOADLR:
2330734f 4328 loadlr_assemble(i, i_regs, ccadj_);
4329 break;
57871462 4330 case STORE:
2330734f 4331 store_assemble(i, i_regs, ccadj_);
4332 break;
57871462 4333 case STORELR:
2330734f 4334 storelr_assemble(i, i_regs, ccadj_);
4335 break;
57871462 4336 case COP0:
2330734f 4337 cop0_assemble(i, i_regs, ccadj_);
4338 break;
a5cd72d0 4339 case RFE:
277718fa 4340 rfe_assemble(i, i_regs);
2330734f 4341 break;
b9b61529 4342 case COP2:
2330734f 4343 cop2_assemble(i, i_regs);
4344 break;
b9b61529 4345 case C2LS:
2330734f 4346 c2ls_assemble(i, i_regs, ccadj_);
4347 break;
b9b61529 4348 case C2OP:
2330734f 4349 c2op_assemble(i, i_regs);
4350 break;
57871462 4351 case MULTDIV:
2330734f 4352 multdiv_assemble(i, i_regs);
4353 multdiv_prepare_stall(i, i_regs, ccadj_);
32631e6a 4354 break;
57871462 4355 case MOV:
2330734f 4356 mov_assemble(i, i_regs);
4357 break;
4358 case SYSCALL:
a5cd72d0 4359 exception_assemble(i, i_regs, ccadj_);
2330734f 4360 break;
4361 case HLECALL:
4362 hlecall_assemble(i, i_regs, ccadj_);
4363 break;
4364 case INTCALL:
4365 intcall_assemble(i, i_regs, ccadj_);
4366 break;
4367 case UJUMP:
4368 ujump_assemble(i, i_regs);
4369 ds = 1;
4370 break;
4371 case RJUMP:
4372 rjump_assemble(i, i_regs);
4373 ds = 1;
4374 break;
4375 case CJUMP:
4376 cjump_assemble(i, i_regs);
4377 ds = 1;
4378 break;
4379 case SJUMP:
4380 sjump_assemble(i, i_regs);
4381 ds = 1;
4382 break;
24058131 4383 case NOP:
2330734f 4384 case OTHER:
2330734f 4385 // not handled, just skip
4386 break;
4387 default:
4388 assert(0);
4389 }
4390 return ds;
4391}
4392
4393static void ds_assemble(int i, const struct regstat *i_regs)
4394{
4395 speculate_register_values(i);
4396 is_delayslot = 1;
4397 switch (dops[i].itype) {
57871462 4398 case SYSCALL:
7139f3c8 4399 case HLECALL:
1e973cb0 4400 case INTCALL:
57871462 4401 case UJUMP:
4402 case RJUMP:
4403 case CJUMP:
4404 case SJUMP:
c43b5311 4405 SysPrintf("Jump in the delay slot. This is probably a bug.\n");
2330734f 4406 break;
4407 default:
277718fa 4408 assemble(i, i_regs, cinfo[i].ccadj);
57871462 4409 }
2330734f 4410 is_delayslot = 0;
57871462 4411}
4412
4413// Is the branch target a valid internal jump?
ad49de89 4414static int internal_branch(int addr)
57871462 4415{
4416 if(addr&1) return 0; // Indirect (register) jump
4417 if(addr>=start && addr<start+slen*4-4)
4418 {
71e490c5 4419 return 1;
57871462 4420 }
4421 return 0;
4422}
4423
ad49de89 4424static void wb_invalidate(signed char pre[],signed char entry[],uint64_t dirty,uint64_t u)
57871462 4425{
4426 int hr;
4427 for(hr=0;hr<HOST_REGS;hr++) {
4428 if(hr!=EXCLUDE_REG) {
4429 if(pre[hr]!=entry[hr]) {
4430 if(pre[hr]>=0) {
4431 if((dirty>>hr)&1) {
4432 if(get_reg(entry,pre[hr])<0) {
00fa9369 4433 assert(pre[hr]<64);
4434 if(!((u>>pre[hr])&1))
4435 emit_storereg(pre[hr],hr);
57871462 4436 }
4437 }
4438 }
4439 }
4440 }
4441 }
4442 // Move from one register to another (no writeback)
4443 for(hr=0;hr<HOST_REGS;hr++) {
4444 if(hr!=EXCLUDE_REG) {
4445 if(pre[hr]!=entry[hr]) {
9de8a0c3 4446 if(pre[hr]>=0&&pre[hr]<TEMPREG) {
57871462 4447 int nr;
4448 if((nr=get_reg(entry,pre[hr]))>=0) {
4449 emit_mov(hr,nr);
4450 }
4451 }
4452 }
4453 }
4454 }
4455}
57871462 4456
4457// Load the specified registers
4458// This only loads the registers given as arguments because
4459// we don't want to load things that will be overwritten
53358c1d 4460static inline void load_reg(signed char entry[], signed char regmap[], int rs)
57871462 4461{
53358c1d 4462 int hr = get_reg(regmap, rs);
4463 if (hr >= 0 && entry[hr] != regmap[hr])
4464 emit_loadreg(regmap[hr], hr);
4465}
4466
4467static void load_regs(signed char entry[], signed char regmap[], int rs1, int rs2)
4468{
4469 load_reg(entry, regmap, rs1);
4470 if (rs1 != rs2)
4471 load_reg(entry, regmap, rs2);
57871462 4472}
4473
4474// Load registers prior to the start of a loop
4475// so that they are not loaded within the loop
4476static void loop_preload(signed char pre[],signed char entry[])
4477{
4478 int hr;
53358c1d 4479 for (hr = 0; hr < HOST_REGS; hr++) {
4480 int r = entry[hr];
4481 if (r >= 0 && pre[hr] != r && get_reg(pre, r) < 0) {
4482 assem_debug("loop preload:\n");
4483 if (r < TEMPREG)
4484 emit_loadreg(r, hr);
57871462 4485 }
4486 }
4487}
4488
4489// Generate address for load/store instruction
277718fa 4490// goes to AGEN (or temp) for writes, FTEMP for LOADLR and cop1/2 loads
4491// AGEN is assigned by pass5b_preallocate2
4149788d 4492static void address_generation(int i, const struct regstat *i_regs, signed char entry[])
57871462 4493{
37387d8b 4494 if (dops[i].is_load || dops[i].is_store) {
277718fa 4495 int ra = -1;
4496 int agr = AGEN1 + (i&1);
cf95b4f0 4497 if(dops[i].itype==LOAD) {
277718fa 4498 if (!dops[i].may_except)
4499 ra = get_reg_w(i_regs->regmap, dops[i].rt1); // reuse dest for agen
4500 if (ra < 0)
4501 ra = get_reg_temp(i_regs->regmap);
57871462 4502 }
cf95b4f0 4503 if(dops[i].itype==LOADLR) {
57871462 4504 ra=get_reg(i_regs->regmap,FTEMP);
4505 }
cf95b4f0 4506 if(dops[i].itype==STORE||dops[i].itype==STORELR) {
57871462 4507 ra=get_reg(i_regs->regmap,agr);
9de8a0c3 4508 if(ra<0) ra=get_reg_temp(i_regs->regmap);
57871462 4509 }
37387d8b 4510 if(dops[i].itype==C2LS) {
277718fa 4511 if (dops[i].opcode == 0x32) // LWC2
57871462 4512 ra=get_reg(i_regs->regmap,FTEMP);
277718fa 4513 else { // SWC2
57871462 4514 ra=get_reg(i_regs->regmap,agr);
9de8a0c3 4515 if(ra<0) ra=get_reg_temp(i_regs->regmap);
57871462 4516 }
4517 }
277718fa 4518 int rs = get_reg(i_regs->regmap, dops[i].rs1);
4519 //if(ra>=0)
4520 {
4521 int offset = cinfo[i].imm;
4522 int add_offset = offset != 0;
33a1eda1 4523 int c = rs >= 0 && ((i_regs->wasconst >> rs) & 1);
cf95b4f0 4524 if(dops[i].rs1==0) {
57871462 4525 // Using r0 as a base address
277718fa 4526 assert(ra >= 0);
57871462 4527 if(!entry||entry[ra]!=agr) {
cf95b4f0 4528 if (dops[i].opcode==0x22||dops[i].opcode==0x26) {
57871462 4529 emit_movimm(offset&0xFFFFFFFC,ra); // LWL/LWR
57871462 4530 }else{
4531 emit_movimm(offset,ra);
4532 }
4533 } // else did it in the previous cycle
277718fa 4534 cinfo[i].addr = ra;
4535 add_offset = 0;
4536 }
4537 else if (rs < 0) {
4538 assert(ra >= 0);
4539 if (!entry || entry[ra] != dops[i].rs1)
4540 emit_loadreg(dops[i].rs1, ra);
4541 cinfo[i].addr = ra;
cf95b4f0 4542 //if(!entry||entry[ra]!=dops[i].rs1)
57871462 4543 // printf("poor load scheduling!\n");
4544 }
4545 else if(c) {
cf95b4f0 4546 if(dops[i].rs1!=dops[i].rt1||dops[i].itype!=LOAD) {
277718fa 4547 assert(ra >= 0);
57871462 4548 if(!entry||entry[ra]!=agr) {
cf95b4f0 4549 if (dops[i].opcode==0x22||dops[i].opcode==0x26) {
57871462 4550 emit_movimm((constmap[i][rs]+offset)&0xFFFFFFFC,ra); // LWL/LWR
57871462 4551 }else{
57871462 4552 emit_movimm(constmap[i][rs]+offset,ra);
8575a877 4553 regs[i].loadedconst|=1<<ra;
57871462 4554 }
4555 } // else did it in the previous cycle
277718fa 4556 cinfo[i].addr = ra;
4557 }
4558 else // else load_consts already did it
4559 cinfo[i].addr = rs;
4560 add_offset = 0;
57871462 4561 }
277718fa 4562 else
4563 cinfo[i].addr = rs;
4564 if (add_offset) {
4565 assert(ra >= 0);
57871462 4566 if(rs>=0) {
4567 emit_addimm(rs,offset,ra);
4568 }else{
4569 emit_addimm(ra,offset,ra);
4570 }
277718fa 4571 cinfo[i].addr = ra;
57871462 4572 }
4573 }
277718fa 4574 assert(cinfo[i].addr >= 0);
57871462 4575 }
4576 // Preload constants for next instruction
37387d8b 4577 if (dops[i+1].is_load || dops[i+1].is_store) {
57871462 4578 int agr,ra;
57871462 4579 // Actual address
4580 agr=AGEN1+((i+1)&1);
4581 ra=get_reg(i_regs->regmap,agr);
4582 if(ra>=0) {
cf95b4f0 4583 int rs=get_reg(regs[i+1].regmap,dops[i+1].rs1);
277718fa 4584 int offset=cinfo[i+1].imm;
57871462 4585 int c=(regs[i+1].wasconst>>rs)&1;
cf95b4f0 4586 if(c&&(dops[i+1].rs1!=dops[i+1].rt1||dops[i+1].itype!=LOAD)) {
4587 if (dops[i+1].opcode==0x22||dops[i+1].opcode==0x26) {
57871462 4588 emit_movimm((constmap[i+1][rs]+offset)&0xFFFFFFFC,ra); // LWL/LWR
cf95b4f0 4589 }else if (dops[i+1].opcode==0x1a||dops[i+1].opcode==0x1b) {
57871462 4590 emit_movimm((constmap[i+1][rs]+offset)&0xFFFFFFF8,ra); // LDL/LDR
4591 }else{
57871462 4592 emit_movimm(constmap[i+1][rs]+offset,ra);
8575a877 4593 regs[i+1].loadedconst|=1<<ra;
57871462 4594 }
4595 }
cf95b4f0 4596 else if(dops[i+1].rs1==0) {
57871462 4597 // Using r0 as a base address
cf95b4f0 4598 if (dops[i+1].opcode==0x22||dops[i+1].opcode==0x26) {
57871462 4599 emit_movimm(offset&0xFFFFFFFC,ra); // LWL/LWR
cf95b4f0 4600 }else if (dops[i+1].opcode==0x1a||dops[i+1].opcode==0x1b) {
57871462 4601 emit_movimm(offset&0xFFFFFFF8,ra); // LDL/LDR
4602 }else{
4603 emit_movimm(offset,ra);
4604 }
4605 }
4606 }
4607 }
4608}
4609
de6dbc52 4610static int get_final_value(int hr, int i, u_int *value)
57871462 4611{
4612 int reg=regs[i].regmap[hr];
4613 while(i<slen-1) {
4614 if(regs[i+1].regmap[hr]!=reg) break;
4615 if(!((regs[i+1].isconst>>hr)&1)) break;
cf95b4f0 4616 if(dops[i+1].bt) break;
57871462 4617 i++;
4618 }
4619 if(i<slen-1) {
fe807a8a 4620 if (dops[i].is_jump) {
57871462 4621 *value=constmap[i][hr];
4622 return 1;
4623 }
cf95b4f0 4624 if(!dops[i+1].bt) {
fe807a8a 4625 if (dops[i+1].is_jump) {
57871462 4626 // Load in delay slot, out-of-order execution
cf95b4f0 4627 if(dops[i+2].itype==LOAD&&dops[i+2].rs1==reg&&dops[i+2].rt1==reg&&((regs[i+1].wasconst>>hr)&1))
57871462 4628 {
57871462 4629 // Precompute load address
277718fa 4630 *value=constmap[i][hr]+cinfo[i+2].imm;
57871462 4631 return 1;
4632 }
4633 }
cf95b4f0 4634 if(dops[i+1].itype==LOAD&&dops[i+1].rs1==reg&&dops[i+1].rt1==reg)
57871462 4635 {
57871462 4636 // Precompute load address
277718fa 4637 *value=constmap[i][hr]+cinfo[i+1].imm;
4638 //printf("c=%x imm=%lx\n",(long)constmap[i][hr],cinfo[i+1].imm);
57871462 4639 return 1;
4640 }
4641 }
4642 }
4643 *value=constmap[i][hr];
643aeae3 4644 //printf("c=%lx\n",(long)constmap[i][hr]);
57871462 4645 if(i==slen-1) return 1;
00fa9369 4646 assert(reg < 64);
4647 return !((unneeded_reg[i+1]>>reg)&1);
57871462 4648}
4649
4650// Load registers with known constants
ad49de89 4651static void load_consts(signed char pre[],signed char regmap[],int i)
57871462 4652{
8575a877 4653 int hr,hr2;
4654 // propagate loaded constant flags
cf95b4f0 4655 if(i==0||dops[i].bt)
8575a877 4656 regs[i].loadedconst=0;
4657 else {
684b6816 4658 for (hr = 0; hr < HOST_REGS; hr++) {
4659 if (hr == EXCLUDE_REG || regmap[hr] < 0 || pre[hr] != regmap[hr])
4660 continue;
4661 if ((((regs[i-1].isconst & regs[i-1].loadedconst) >> hr) & 1)
4662 && regmap[hr] == regs[i-1].regmap[hr])
8575a877 4663 {
684b6816 4664 regs[i].loadedconst |= 1u << hr;
8575a877 4665 }
4666 }
4667 }
57871462 4668 // Load 32-bit regs
4669 for(hr=0;hr<HOST_REGS;hr++) {
4670 if(hr!=EXCLUDE_REG&&regmap[hr]>=0) {
4671 //if(entry[hr]!=regmap[hr]) {
8575a877 4672 if(!((regs[i].loadedconst>>hr)&1)) {
ad49de89 4673 assert(regmap[hr]<64);
4674 if(((regs[i].isconst>>hr)&1)&&regmap[hr]>0) {
de6dbc52 4675 u_int value, similar=0;
57871462 4676 if(get_final_value(hr,i,&value)) {
8575a877 4677 // see if some other register has similar value
4678 for(hr2=0;hr2<HOST_REGS;hr2++) {
4679 if(hr2!=EXCLUDE_REG&&((regs[i].loadedconst>>hr2)&1)) {
4680 if(is_similar_value(value,constmap[i][hr2])) {
4681 similar=1;
4682 break;
4683 }
4684 }
4685 }
4686 if(similar) {
de6dbc52 4687 u_int value2;
8575a877 4688 if(get_final_value(hr2,i,&value2)) // is this needed?
4689 emit_movimm_from(value2,hr2,value,hr);
4690 else
4691 emit_movimm(value,hr);
4692 }
4693 else if(value==0) {
57871462 4694 emit_zeroreg(hr);
4695 }
4696 else {
4697 emit_movimm(value,hr);
4698 }
4699 }
8575a877 4700 regs[i].loadedconst|=1<<hr;
57871462 4701 }
4702 }
4703 }
4704 }
57871462 4705}
ad49de89 4706
2330734f 4707static void load_all_consts(const signed char regmap[], u_int dirty, int i)
57871462 4708{
4709 int hr;
4710 // Load 32-bit regs
4711 for(hr=0;hr<HOST_REGS;hr++) {
4712 if(hr!=EXCLUDE_REG&&regmap[hr]>=0&&((dirty>>hr)&1)) {
ad49de89 4713 assert(regmap[hr] < 64);
4714 if(((regs[i].isconst>>hr)&1)&&regmap[hr]>0) {
57871462 4715 int value=constmap[i][hr];
4716 if(value==0) {
4717 emit_zeroreg(hr);
4718 }
4719 else {
4720 emit_movimm(value,hr);
4721 }
4722 }
4723 }
4724 }
57871462 4725}
4726
4727// Write out all dirty registers (except cycle count)
a22ccd6a 4728#ifndef wb_dirtys
4729static void wb_dirtys(const signed char i_regmap[], u_int i_dirty)
57871462 4730{
4731 int hr;
4732 for(hr=0;hr<HOST_REGS;hr++) {
4733 if(hr!=EXCLUDE_REG) {
4734 if(i_regmap[hr]>0) {
4735 if(i_regmap[hr]!=CCREG) {
4736 if((i_dirty>>hr)&1) {
00fa9369 4737 assert(i_regmap[hr]<64);
4738 emit_storereg(i_regmap[hr],hr);
57871462 4739 }
4740 }
4741 }
4742 }
4743 }
4744}
a22ccd6a 4745#endif
ad49de89 4746
57871462 4747// Write out dirty registers that we need to reload (pair with load_needed_regs)
4748// This writes the registers not written by store_regs_bt
a22ccd6a 4749static void wb_needed_dirtys(const signed char i_regmap[], u_int i_dirty, int addr)
57871462 4750{
4751 int hr;
4752 int t=(addr-start)>>2;
4753 for(hr=0;hr<HOST_REGS;hr++) {
4754 if(hr!=EXCLUDE_REG) {
4755 if(i_regmap[hr]>0) {
4756 if(i_regmap[hr]!=CCREG) {
ad49de89 4757 if(i_regmap[hr]==regs[t].regmap_entry[hr] && ((regs[t].dirty>>hr)&1)) {
57871462 4758 if((i_dirty>>hr)&1) {
00fa9369 4759 assert(i_regmap[hr]<64);
4760 emit_storereg(i_regmap[hr],hr);
57871462 4761 }
4762 }
4763 }
4764 }
4765 }
4766 }
4767}
4768
4769// Load all registers (except cycle count)
a22ccd6a 4770#ifndef load_all_regs
2330734f 4771static void load_all_regs(const signed char i_regmap[])
57871462 4772{
4773 int hr;
4774 for(hr=0;hr<HOST_REGS;hr++) {
4775 if(hr!=EXCLUDE_REG) {
4776 if(i_regmap[hr]==0) {
4777 emit_zeroreg(hr);
4778 }
4779 else
9de8a0c3 4780 if(i_regmap[hr]>0 && i_regmap[hr]<TEMPREG && i_regmap[hr]!=CCREG)
57871462 4781 {
4782 emit_loadreg(i_regmap[hr],hr);
4783 }
4784 }
4785 }
4786}
a22ccd6a 4787#endif
57871462 4788
4789// Load all current registers also needed by next instruction
2330734f 4790static void load_needed_regs(const signed char i_regmap[], const signed char next_regmap[])
57871462 4791{
a22ccd6a 4792 signed char regmap_sel[HOST_REGS];
57871462 4793 int hr;
a22ccd6a 4794 for (hr = 0; hr < HOST_REGS; hr++) {
4795 regmap_sel[hr] = -1;
4796 if (hr != EXCLUDE_REG)
4797 if (next_regmap[hr] == i_regmap[hr] || get_reg(next_regmap, i_regmap[hr]) >= 0)
4798 regmap_sel[hr] = i_regmap[hr];
57871462 4799 }
a22ccd6a 4800 load_all_regs(regmap_sel);
57871462 4801}
4802
4803// Load all regs, storing cycle count if necessary
2330734f 4804static void load_regs_entry(int t)
57871462 4805{
cf95b4f0 4806 if(dops[t].is_ds) emit_addimm(HOST_CCREG,CLOCK_ADJUST(1),HOST_CCREG);
277718fa 4807 else if(cinfo[t].ccadj) emit_addimm(HOST_CCREG,-cinfo[t].ccadj,HOST_CCREG);
57871462 4808 if(regs[t].regmap_entry[HOST_CCREG]!=CCREG) {
4809 emit_storereg(CCREG,HOST_CCREG);
4810 }
a22ccd6a 4811 load_all_regs(regs[t].regmap_entry);
57871462 4812}
4813
4814// Store dirty registers prior to branch
4149788d 4815static void store_regs_bt(signed char i_regmap[],uint64_t i_dirty,int addr)
57871462 4816{
ad49de89 4817 if(internal_branch(addr))
57871462 4818 {
4819 int t=(addr-start)>>2;
4820 int hr;
4821 for(hr=0;hr<HOST_REGS;hr++) {
4822 if(hr!=EXCLUDE_REG) {
4823 if(i_regmap[hr]>0 && i_regmap[hr]!=CCREG) {
ad49de89 4824 if(i_regmap[hr]!=regs[t].regmap_entry[hr] || !((regs[t].dirty>>hr)&1)) {
57871462 4825 if((i_dirty>>hr)&1) {
00fa9369 4826 assert(i_regmap[hr]<64);
4827 if(!((unneeded_reg[t]>>i_regmap[hr])&1))
4828 emit_storereg(i_regmap[hr],hr);
57871462 4829 }
4830 }
4831 }
4832 }
4833 }
4834 }
4835 else
4836 {
4837 // Branch out of this block, write out all dirty regs
ad49de89 4838 wb_dirtys(i_regmap,i_dirty);
57871462 4839 }
4840}
4841
4842// Load all needed registers for branch target
ad49de89 4843static void load_regs_bt(signed char i_regmap[],uint64_t i_dirty,int addr)
57871462 4844{
4845 //if(addr>=start && addr<(start+slen*4))
ad49de89 4846 if(internal_branch(addr))
57871462 4847 {
4848 int t=(addr-start)>>2;
4849 int hr;
4850 // Store the cycle count before loading something else
4851 if(i_regmap[HOST_CCREG]!=CCREG) {
4852 assert(i_regmap[HOST_CCREG]==-1);
4853 }
4854 if(regs[t].regmap_entry[HOST_CCREG]!=CCREG) {
4855 emit_storereg(CCREG,HOST_CCREG);
4856 }
4857 // Load 32-bit regs
4858 for(hr=0;hr<HOST_REGS;hr++) {
ea3d2e6e 4859 if(hr!=EXCLUDE_REG&&regs[t].regmap_entry[hr]>=0&&regs[t].regmap_entry[hr]<TEMPREG) {
00fa9369 4860 if(i_regmap[hr]!=regs[t].regmap_entry[hr]) {
57871462 4861 if(regs[t].regmap_entry[hr]==0) {
4862 emit_zeroreg(hr);
4863 }
4864 else if(regs[t].regmap_entry[hr]!=CCREG)
4865 {
4866 emit_loadreg(regs[t].regmap_entry[hr],hr);
4867 }
4868 }
4869 }
4870 }
57871462 4871 }
4872}
4873
ad49de89 4874static int match_bt(signed char i_regmap[],uint64_t i_dirty,int addr)
57871462 4875{
4876 if(addr>=start && addr<start+slen*4-4)
4877 {
4878 int t=(addr-start)>>2;
4879 int hr;
4880 if(regs[t].regmap_entry[HOST_CCREG]!=CCREG) return 0;
4881 for(hr=0;hr<HOST_REGS;hr++)
4882 {
4883 if(hr!=EXCLUDE_REG)
4884 {
4885 if(i_regmap[hr]!=regs[t].regmap_entry[hr])
4886 {
ea3d2e6e 4887 if(regs[t].regmap_entry[hr]>=0&&(regs[t].regmap_entry[hr]|64)<TEMPREG+64)
57871462 4888 {
4889 return 0;
4890 }
9f51b4b9 4891 else
57871462 4892 if((i_dirty>>hr)&1)
4893 {
ea3d2e6e 4894 if(i_regmap[hr]<TEMPREG)
57871462 4895 {
4896 if(!((unneeded_reg[t]>>i_regmap[hr])&1))
4897 return 0;
4898 }
ea3d2e6e 4899 else if(i_regmap[hr]>=64&&i_regmap[hr]<TEMPREG+64)
57871462 4900 {
00fa9369 4901 assert(0);
57871462 4902 }
4903 }
4904 }
4905 else // Same register but is it 32-bit or dirty?
4906 if(i_regmap[hr]>=0)
4907 {
4908 if(!((regs[t].dirty>>hr)&1))
4909 {
4910 if((i_dirty>>hr)&1)
4911 {
4912 if(!((unneeded_reg[t]>>i_regmap[hr])&1))
4913 {
4914 //printf("%x: dirty no match\n",addr);
4915 return 0;
4916 }
4917 }
4918 }
57871462 4919 }
4920 }
4921 }
57871462 4922 // Delay slots are not valid branch targets
fe807a8a 4923 //if(t>0&&(dops[t-1].is_jump) return 0;
57871462 4924 // Delay slots require additional processing, so do not match
cf95b4f0 4925 if(dops[t].is_ds) return 0;
57871462 4926 }
4927 else
4928 {
4929 int hr;
4930 for(hr=0;hr<HOST_REGS;hr++)
4931 {
4932 if(hr!=EXCLUDE_REG)
4933 {
4934 if(i_regmap[hr]>=0)
4935 {
4936 if(hr!=HOST_CCREG||i_regmap[hr]!=CCREG)
4937 {
4938 if((i_dirty>>hr)&1)
4939 {
4940 return 0;
4941 }
4942 }
4943 }
4944 }
4945 }
4946 }
4947 return 1;
4948}
4949
dd114d7d 4950#ifdef DRC_DBG
2330734f 4951static void drc_dbg_emit_do_cmp(int i, int ccadj_)
dd114d7d 4952{
4953 extern void do_insn_cmp();
3968e69e 4954 //extern int cycle;
81dbbf4c 4955 u_int hr, reglist = get_host_reglist(regs[i].regmap);
33a1eda1 4956 reglist |= get_host_reglist(regs[i].regmap_entry);
4957 reglist &= DRC_DBG_REGMASK;
dd114d7d 4958
40fca85b 4959 assem_debug("//do_insn_cmp %08x\n", start+i*4);
dd114d7d 4960 save_regs(reglist);
40fca85b 4961 // write out changed consts to match the interpreter
cf95b4f0 4962 if (i > 0 && !dops[i].bt) {
40fca85b 4963 for (hr = 0; hr < HOST_REGS; hr++) {
2330734f 4964 int reg = regs[i].regmap_entry[hr]; // regs[i-1].regmap[hr];
277718fa 4965 if (hr == EXCLUDE_REG || reg <= 0)
40fca85b 4966 continue;
4967 if (!((regs[i-1].isconst >> hr) & 1))
4968 continue;
4969 if (i > 1 && reg == regs[i-2].regmap[hr] && constmap[i-1][hr] == constmap[i-2][hr])
4970 continue;
4971 emit_movimm(constmap[i-1][hr],0);
4972 emit_storereg(reg, 0);
4973 }
4974 }
4f13a577 4975 if (dops[i].opcode == 0x0f) { // LUI
4976 emit_movimm(cinfo[i].imm << 16, 0);
4977 emit_storereg(dops[i].rt1, 0);
4978 }
dd114d7d 4979 emit_movimm(start+i*4,0);
643aeae3 4980 emit_writeword(0,&pcaddr);
2330734f 4981 int cc = get_reg(regs[i].regmap_entry, CCREG);
4982 if (cc < 0)
4983 emit_loadreg(CCREG, cc = 0);
4984 emit_addimm(cc, ccadj_, 0);
4985 emit_writeword(0, &psxRegs.cycle);
2a014d73 4986 emit_far_call(do_insn_cmp);
643aeae3 4987 //emit_readword(&cycle,0);
dd114d7d 4988 //emit_addimm(0,2,0);
643aeae3 4989 //emit_writeword(0,&cycle);
3968e69e 4990 (void)get_reg2;
dd114d7d 4991 restore_regs(reglist);
40fca85b 4992 assem_debug("\\\\do_insn_cmp\n");
dd114d7d 4993}
4f13a577 4994static void drc_dbg_emit_wb_dirtys(int i, const struct regstat *i_regs)
4995{
4996 // write-out non-consts, consts are likely different because of get_final_value()
4997 if (i_regs->dirty & ~i_regs->loadedconst) {
4998 assem_debug("/ drc_dbg_wb\n");
4999 wb_dirtys(i_regs->regmap, i_regs->dirty & ~i_regs->loadedconst);
5000 assem_debug("\\ drc_dbg_wb\n");
5001 }
5002}
dd114d7d 5003#else
2330734f 5004#define drc_dbg_emit_do_cmp(x,y)
4f13a577 5005#define drc_dbg_emit_wb_dirtys(x,y)
dd114d7d 5006#endif
5007
57871462 5008// Used when a branch jumps into the delay slot of another branch
7c3a5182 5009static void ds_assemble_entry(int i)
57871462 5010{
277718fa 5011 int t = (cinfo[i].ba - start) >> 2;
2330734f 5012 int ccadj_ = -CLOCK_ADJUST(1);
df4dc2b1 5013 if (!instr_addr[t])
5014 instr_addr[t] = out;
277718fa 5015 assem_debug("Assemble delay slot at %x\n",cinfo[i].ba);
57871462 5016 assem_debug("<->\n");
2330734f 5017 drc_dbg_emit_do_cmp(t, ccadj_);
57871462 5018 if(regs[t].regmap_entry[HOST_CCREG]==CCREG&&regs[t].regmap[HOST_CCREG]!=CCREG)
ad49de89 5019 wb_register(CCREG,regs[t].regmap_entry,regs[t].wasdirty);
cf95b4f0 5020 load_regs(regs[t].regmap_entry,regs[t].regmap,dops[t].rs1,dops[t].rs2);
57871462 5021 address_generation(t,&regs[t],regs[t].regmap_entry);
37387d8b 5022 if (ram_offset && (dops[t].is_load || dops[t].is_store))
53358c1d 5023 load_reg(regs[t].regmap_entry,regs[t].regmap,ROREG);
37387d8b 5024 if (dops[t].is_store)
53358c1d 5025 load_reg(regs[t].regmap_entry,regs[t].regmap,INVCP);
57871462 5026 is_delayslot=0;
2330734f 5027 switch (dops[t].itype) {
57871462 5028 case SYSCALL:
7139f3c8 5029 case HLECALL:
1e973cb0 5030 case INTCALL:
57871462 5031 case UJUMP:
5032 case RJUMP:
5033 case CJUMP:
5034 case SJUMP:
c43b5311 5035 SysPrintf("Jump in the delay slot. This is probably a bug.\n");
2330734f 5036 break;
5037 default:
5038 assemble(t, &regs[t], ccadj_);
57871462 5039 }
277718fa 5040 store_regs_bt(regs[t].regmap,regs[t].dirty,cinfo[i].ba+4);
5041 load_regs_bt(regs[t].regmap,regs[t].dirty,cinfo[i].ba+4);
5042 if(internal_branch(cinfo[i].ba+4))
57871462 5043 assem_debug("branch: internal\n");
5044 else
5045 assem_debug("branch: external\n");
277718fa 5046 assert(internal_branch(cinfo[i].ba+4));
5047 add_to_linker(out,cinfo[i].ba+4,internal_branch(cinfo[i].ba+4));
57871462 5048 emit_jmp(0);
5049}
5050
d1e4ebd9 5051// Load 2 immediates optimizing for small code size
5052static void emit_mov2imm_compact(int imm1,u_int rt1,int imm2,u_int rt2)
5053{
5054 emit_movimm(imm1,rt1);
5055 emit_movimm_from(imm1,rt1,imm2,rt2);
5056}
5057
2330734f 5058static void do_cc(int i, const signed char i_regmap[], int *adj,
5059 int addr, int taken, int invert)
57871462 5060{
2330734f 5061 int count, count_plus2;
b14b6a8f 5062 void *jaddr;
5063 void *idle=NULL;
b6e87b2b 5064 int t=0;
cf95b4f0 5065 if(dops[i].itype==RJUMP)
57871462 5066 {
5067 *adj=0;
5068 }
277718fa 5069 //if(cinfo[i].ba>=start && cinfo[i].ba<(start+slen*4))
5070 if(internal_branch(cinfo[i].ba))
57871462 5071 {
277718fa 5072 t=(cinfo[i].ba-start)>>2;
2330734f 5073 if(dops[t].is_ds) *adj=-CLOCK_ADJUST(1); // Branch into delay slot adds an extra cycle
277718fa 5074 else *adj=cinfo[t].ccadj;
57871462 5075 }
5076 else
5077 {
5078 *adj=0;
5079 }
277718fa 5080 count = cinfo[i].ccadj;
2330734f 5081 count_plus2 = count + CLOCK_ADJUST(2);
277718fa 5082 if(taken==TAKEN && i==(cinfo[i].ba-start)>>2 && source[i+1]==0) {
57871462 5083 // Idle loop
5084 if(count&1) emit_addimm_and_set_flags(2*(count+2),HOST_CCREG);
b14b6a8f 5085 idle=out;
57871462 5086 //emit_subfrommem(&idlecount,HOST_CCREG); // Count idle cycles
5087 emit_andimm(HOST_CCREG,3,HOST_CCREG);
b14b6a8f 5088 jaddr=out;
57871462 5089 emit_jmp(0);
5090 }
5091 else if(*adj==0||invert) {
2330734f 5092 int cycles = count_plus2;
b6e87b2b 5093 // faster loop HACK
bb4f300c 5094#if 0
b6e87b2b 5095 if (t&&*adj) {
5096 int rel=t-i;
5097 if(-NO_CYCLE_PENALTY_THR<rel&&rel<0)
2330734f 5098 cycles=*adj+count+2-*adj;
b6e87b2b 5099 }
bb4f300c 5100#endif
2330734f 5101 emit_addimm_and_set_flags(cycles, HOST_CCREG);
5102 jaddr = out;
57871462 5103 emit_jns(0);
5104 }
5105 else
5106 {
2330734f 5107 emit_cmpimm(HOST_CCREG, -count_plus2);
5108 jaddr = out;
57871462 5109 emit_jns(0);
5110 }
2330734f 5111 add_stub(CC_STUB,jaddr,idle?idle:out,(*adj==0||invert||idle)?0:count_plus2,i,addr,taken,0);
57871462 5112}
5113
b14b6a8f 5114static void do_ccstub(int n)
57871462 5115{
5116 literal_pool(256);
d1e4ebd9 5117 assem_debug("do_ccstub %x\n",start+(u_int)stubs[n].b*4);
b14b6a8f 5118 set_jump_target(stubs[n].addr, out);
5119 int i=stubs[n].b;
33a1eda1 5120 if (stubs[n].d != TAKEN) {
ad49de89 5121 wb_dirtys(branch_regs[i].regmap,branch_regs[i].dirty);
57871462 5122 }
5123 else {
277718fa 5124 if(internal_branch(cinfo[i].ba))
5125 wb_needed_dirtys(branch_regs[i].regmap,branch_regs[i].dirty,cinfo[i].ba);
57871462 5126 }
b14b6a8f 5127 if(stubs[n].c!=-1)
57871462 5128 {
5129 // Save PC as return address
6d75addf 5130 emit_movimm(stubs[n].c,0);
5131 emit_writeword(0,&pcaddr);
57871462 5132 }
5133 else
5134 {
5135 // Return address depends on which way the branch goes
cf95b4f0 5136 if(dops[i].itype==CJUMP||dops[i].itype==SJUMP)
57871462 5137 {
cf95b4f0 5138 int s1l=get_reg(branch_regs[i].regmap,dops[i].rs1);
5139 int s2l=get_reg(branch_regs[i].regmap,dops[i].rs2);
5140 if(dops[i].rs1==0)
57871462 5141 {
ad49de89 5142 s1l=s2l;
5143 s2l=-1;
57871462 5144 }
cf95b4f0 5145 else if(dops[i].rs2==0)
57871462 5146 {
ad49de89 5147 s2l=-1;
57871462 5148 }
5149 assert(s1l>=0);
5150 #ifdef DESTRUCTIVE_WRITEBACK
cf95b4f0 5151 if(dops[i].rs1) {
ad49de89 5152 if((branch_regs[i].dirty>>s1l)&&1)
cf95b4f0 5153 emit_loadreg(dops[i].rs1,s1l);
9f51b4b9 5154 }
57871462 5155 else {
ad49de89 5156 if((branch_regs[i].dirty>>s1l)&1)
cf95b4f0 5157 emit_loadreg(dops[i].rs2,s1l);
57871462 5158 }
5159 if(s2l>=0)
ad49de89 5160 if((branch_regs[i].dirty>>s2l)&1)
cf95b4f0 5161 emit_loadreg(dops[i].rs2,s2l);
57871462 5162 #endif
5163 int hr=0;
5194fb95 5164 int addr=-1,alt=-1,ntaddr=-1;
57871462 5165 while(hr<HOST_REGS)
5166 {
5167 if(hr!=EXCLUDE_REG && hr!=HOST_CCREG &&
9de8a0c3 5168 branch_regs[i].regmap[hr]!=dops[i].rs1 &&
5169 branch_regs[i].regmap[hr]!=dops[i].rs2 )
57871462 5170 {
5171 addr=hr++;break;
5172 }
5173 hr++;
5174 }
5175 while(hr<HOST_REGS)
5176 {
5177 if(hr!=EXCLUDE_REG && hr!=HOST_CCREG &&
9de8a0c3 5178 branch_regs[i].regmap[hr]!=dops[i].rs1 &&
5179 branch_regs[i].regmap[hr]!=dops[i].rs2 )
57871462 5180 {
5181 alt=hr++;break;
5182 }
5183 hr++;
5184 }
ecca05e3 5185 if ((dops[i].opcode & 0x3e) == 6) // BLEZ/BGTZ needs another register
57871462 5186 {
5187 while(hr<HOST_REGS)
5188 {
5189 if(hr!=EXCLUDE_REG && hr!=HOST_CCREG &&
9de8a0c3 5190 branch_regs[i].regmap[hr]!=dops[i].rs1 &&
5191 branch_regs[i].regmap[hr]!=dops[i].rs2 )
57871462 5192 {
5193 ntaddr=hr;break;
5194 }
5195 hr++;
5196 }
5197 assert(hr<HOST_REGS);
5198 }
ecca05e3 5199 if (dops[i].opcode == 4) // BEQ
57871462 5200 {
5201 #ifdef HAVE_CMOV_IMM
ad49de89 5202 if(s2l>=0) emit_cmp(s1l,s2l);
5203 else emit_test(s1l,s1l);
277718fa 5204 emit_cmov2imm_e_ne_compact(cinfo[i].ba,start+i*4+8,addr);
ad49de89 5205 #else
277718fa 5206 emit_mov2imm_compact(cinfo[i].ba,addr,start+i*4+8,alt);
ad49de89 5207 if(s2l>=0) emit_cmp(s1l,s2l);
5208 else emit_test(s1l,s1l);
5209 emit_cmovne_reg(alt,addr);
57871462 5210 #endif
57871462 5211 }
ecca05e3 5212 else if (dops[i].opcode == 5) // BNE
57871462 5213 {
5214 #ifdef HAVE_CMOV_IMM
ad49de89 5215 if(s2l>=0) emit_cmp(s1l,s2l);
5216 else emit_test(s1l,s1l);
277718fa 5217 emit_cmov2imm_e_ne_compact(start+i*4+8,cinfo[i].ba,addr);
ad49de89 5218 #else
277718fa 5219 emit_mov2imm_compact(start+i*4+8,addr,cinfo[i].ba,alt);
ad49de89 5220 if(s2l>=0) emit_cmp(s1l,s2l);
5221 else emit_test(s1l,s1l);
5222 emit_cmovne_reg(alt,addr);
57871462 5223 #endif
57871462 5224 }
ecca05e3 5225 else if (dops[i].opcode == 6) // BLEZ
57871462 5226 {
277718fa 5227 //emit_movimm(cinfo[i].ba,alt);
57871462 5228 //emit_movimm(start+i*4+8,addr);
277718fa 5229 emit_mov2imm_compact(cinfo[i].ba,alt,start+i*4+8,addr);
57871462 5230 emit_cmpimm(s1l,1);
57871462 5231 emit_cmovl_reg(alt,addr);
57871462 5232 }
ecca05e3 5233 else if (dops[i].opcode == 7) // BGTZ
57871462 5234 {
277718fa 5235 //emit_movimm(cinfo[i].ba,addr);
57871462 5236 //emit_movimm(start+i*4+8,ntaddr);
277718fa 5237 emit_mov2imm_compact(cinfo[i].ba,addr,start+i*4+8,ntaddr);
57871462 5238 emit_cmpimm(s1l,1);
57871462 5239 emit_cmovl_reg(ntaddr,addr);
57871462 5240 }
ecca05e3 5241 else if (dops[i].itype == SJUMP) // BLTZ/BGEZ
57871462 5242 {
277718fa 5243 //emit_movimm(cinfo[i].ba,alt);
57871462 5244 //emit_movimm(start+i*4+8,addr);
de6dbc52 5245 if (dops[i].rs1) {
5246 emit_mov2imm_compact(cinfo[i].ba,
5247 (dops[i].opcode2 & 1) ? addr : alt, start + i*4 + 8,
5248 (dops[i].opcode2 & 1) ? alt : addr);
5249 emit_test(s1l,s1l);
5250 emit_cmovs_reg(alt,addr);
5251 }
5252 else
5253 emit_movimm((dops[i].opcode2 & 1) ? cinfo[i].ba : start + i*4 + 8, addr);
57871462 5254 }
ecca05e3 5255 emit_writeword(addr, &pcaddr);
57871462 5256 }
5257 else
cf95b4f0 5258 if(dops[i].itype==RJUMP)
57871462 5259 {
cf95b4f0 5260 int r=get_reg(branch_regs[i].regmap,dops[i].rs1);
4919de1e 5261 if (ds_writes_rjump_rs(i)) {
57871462 5262 r=get_reg(branch_regs[i].regmap,RTEMP);
5263 }
643aeae3 5264 emit_writeword(r,&pcaddr);
57871462 5265 }
7c3a5182 5266 else {SysPrintf("Unknown branch type in do_ccstub\n");abort();}
57871462 5267 }
5268 // Update cycle count
5269 assert(branch_regs[i].regmap[HOST_CCREG]==CCREG||branch_regs[i].regmap[HOST_CCREG]==-1);
2330734f 5270 if(stubs[n].a) emit_addimm(HOST_CCREG,(int)stubs[n].a,HOST_CCREG);
2a014d73 5271 emit_far_call(cc_interrupt);
2330734f 5272 if(stubs[n].a) emit_addimm(HOST_CCREG,-(int)stubs[n].a,HOST_CCREG);
b14b6a8f 5273 if(stubs[n].d==TAKEN) {
277718fa 5274 if(internal_branch(cinfo[i].ba))
5275 load_needed_regs(branch_regs[i].regmap,regs[(cinfo[i].ba-start)>>2].regmap_entry);
cf95b4f0 5276 else if(dops[i].itype==RJUMP) {
57871462 5277 if(get_reg(branch_regs[i].regmap,RTEMP)>=0)
643aeae3 5278 emit_readword(&pcaddr,get_reg(branch_regs[i].regmap,RTEMP));
57871462 5279 else
cf95b4f0 5280 emit_loadreg(dops[i].rs1,get_reg(branch_regs[i].regmap,dops[i].rs1));
57871462 5281 }
b14b6a8f 5282 }else if(stubs[n].d==NOTTAKEN) {
57871462 5283 if(i<slen-2) load_needed_regs(branch_regs[i].regmap,regmap_pre[i+2]);
5284 else load_all_regs(branch_regs[i].regmap);
57871462 5285 }else{
5286 load_all_regs(branch_regs[i].regmap);
5287 }
d1e4ebd9 5288 if (stubs[n].retaddr)
5289 emit_jmp(stubs[n].retaddr);
5290 else
5291 do_jump_vaddr(stubs[n].e);
57871462 5292}
5293
104df9d3 5294static void add_to_linker(void *addr, u_int target, int is_internal)
57871462 5295{
643aeae3 5296 assert(linkcount < ARRAY_SIZE(link_addr));
5297 link_addr[linkcount].addr = addr;
5298 link_addr[linkcount].target = target;
104df9d3 5299 link_addr[linkcount].internal = is_internal;
57871462 5300 linkcount++;
5301}
5302
eba830cd 5303static void ujump_assemble_write_ra(int i)
5304{
5305 int rt;
5306 unsigned int return_address;
5307 rt=get_reg(branch_regs[i].regmap,31);
de6dbc52 5308 //assem_debug("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
eba830cd 5309 //assert(rt>=0);
5310 return_address=start+i*4+8;
5311 if(rt>=0) {
5312 #ifdef USE_MINI_HT
cf95b4f0 5313 if(internal_branch(return_address)&&dops[i+1].rt1!=31) {
eba830cd 5314 int temp=-1; // note: must be ds-safe
5315 #ifdef HOST_TEMPREG
5316 temp=HOST_TEMPREG;
5317 #endif
5318 if(temp>=0) do_miniht_insert(return_address,rt,temp);
5319 else emit_movimm(return_address,rt);
5320 }
5321 else
5322 #endif
5323 {
5324 #ifdef REG_PREFETCH
9f51b4b9 5325 if(temp>=0)
eba830cd 5326 {
643aeae3 5327 if(i_regmap[temp]!=PTEMP) emit_movimm((uintptr_t)hash_table_get(return_address),temp);
eba830cd 5328 }
5329 #endif
de6dbc52 5330 if (!((regs[i].loadedconst >> rt) & 1))
5331 emit_movimm(return_address, rt); // PC into link register
eba830cd 5332 #ifdef IMM_PREFETCH
df4dc2b1 5333 emit_prefetch(hash_table_get(return_address));
eba830cd 5334 #endif
5335 }
5336 }
5337}
5338
2330734f 5339static void ujump_assemble(int i, const struct regstat *i_regs)
57871462 5340{
277718fa 5341 if(i==(cinfo[i].ba-start)>>2) assem_debug("idle loop\n");
57871462 5342 address_generation(i+1,i_regs,regs[i].regmap_entry);
5343 #ifdef REG_PREFETCH
5344 int temp=get_reg(branch_regs[i].regmap,PTEMP);
cf95b4f0 5345 if(dops[i].rt1==31&&temp>=0)
57871462 5346 {
581335b0 5347 signed char *i_regmap=i_regs->regmap;
57871462 5348 int return_address=start+i*4+8;
9f51b4b9 5349 if(get_reg(branch_regs[i].regmap,31)>0)
643aeae3 5350 if(i_regmap[temp]==PTEMP) emit_movimm((uintptr_t)hash_table_get(return_address),temp);
57871462 5351 }
5352 #endif
de6dbc52 5353 if (dops[i].rt1 == 31)
eba830cd 5354 ujump_assemble_write_ra(i); // writeback ra for DS
4ef8f67d 5355 ds_assemble(i+1,i_regs);
5356 uint64_t bc_unneeded=branch_regs[i].u;
cf95b4f0 5357 bc_unneeded|=1|(1LL<<dops[i].rt1);
ad49de89 5358 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,bc_unneeded);
53358c1d 5359 load_reg(regs[i].regmap,branch_regs[i].regmap,CCREG);
57871462 5360 int cc,adj;
5361 cc=get_reg(branch_regs[i].regmap,CCREG);
5362 assert(cc==HOST_CCREG);
277718fa 5363 store_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,cinfo[i].ba);
57871462 5364 #ifdef REG_PREFETCH
cf95b4f0 5365 if(dops[i].rt1==31&&temp>=0) emit_prefetchreg(temp);
57871462 5366 #endif
277718fa 5367 do_cc(i,branch_regs[i].regmap,&adj,cinfo[i].ba,TAKEN,0);
5368 if(adj) emit_addimm(cc, cinfo[i].ccadj + CLOCK_ADJUST(2) - adj, cc);
5369 load_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,cinfo[i].ba);
5370 if(internal_branch(cinfo[i].ba))
57871462 5371 assem_debug("branch: internal\n");
5372 else
5373 assem_debug("branch: external\n");
277718fa 5374 if (internal_branch(cinfo[i].ba) && dops[(cinfo[i].ba-start)>>2].is_ds) {
57871462 5375 ds_assemble_entry(i);
5376 }
5377 else {
277718fa 5378 add_to_linker(out,cinfo[i].ba,internal_branch(cinfo[i].ba));
57871462 5379 emit_jmp(0);
5380 }
5381}
5382
eba830cd 5383static void rjump_assemble_write_ra(int i)
5384{
5385 int rt,return_address;
a5cd72d0 5386 rt=get_reg_w(branch_regs[i].regmap, dops[i].rt1);
de6dbc52 5387 //assem_debug("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
eba830cd 5388 assert(rt>=0);
5389 return_address=start+i*4+8;
5390 #ifdef REG_PREFETCH
9f51b4b9 5391 if(temp>=0)
eba830cd 5392 {
643aeae3 5393 if(i_regmap[temp]!=PTEMP) emit_movimm((uintptr_t)hash_table_get(return_address),temp);
eba830cd 5394 }
5395 #endif
de6dbc52 5396 if (!((regs[i].loadedconst >> rt) & 1))
5397 emit_movimm(return_address, rt); // PC into link register
eba830cd 5398 #ifdef IMM_PREFETCH
df4dc2b1 5399 emit_prefetch(hash_table_get(return_address));
eba830cd 5400 #endif
5401}
5402
2330734f 5403static void rjump_assemble(int i, const struct regstat *i_regs)
57871462 5404{
57871462 5405 int temp;
581335b0 5406 int rs,cc;
cf95b4f0 5407 rs=get_reg(branch_regs[i].regmap,dops[i].rs1);
57871462 5408 assert(rs>=0);
4919de1e 5409 if (ds_writes_rjump_rs(i)) {
57871462 5410 // Delay slot abuse, make a copy of the branch address register
5411 temp=get_reg(branch_regs[i].regmap,RTEMP);
5412 assert(temp>=0);
5413 assert(regs[i].regmap[temp]==RTEMP);
5414 emit_mov(rs,temp);
5415 rs=temp;
5416 }
5417 address_generation(i+1,i_regs,regs[i].regmap_entry);
5418 #ifdef REG_PREFETCH
cf95b4f0 5419 if(dops[i].rt1==31)
57871462 5420 {
5421 if((temp=get_reg(branch_regs[i].regmap,PTEMP))>=0) {
581335b0 5422 signed char *i_regmap=i_regs->regmap;
57871462 5423 int return_address=start+i*4+8;
643aeae3 5424 if(i_regmap[temp]==PTEMP) emit_movimm((uintptr_t)hash_table_get(return_address),temp);
57871462 5425 }
5426 }
5427 #endif
5428 #ifdef USE_MINI_HT
cf95b4f0 5429 if(dops[i].rs1==31) {
57871462 5430 int rh=get_reg(regs[i].regmap,RHASH);
5431 if(rh>=0) do_preload_rhash(rh);
5432 }
5433 #endif
de6dbc52 5434 if (dops[i].rt1 != 0)
eba830cd 5435 rjump_assemble_write_ra(i);
d5910d5d 5436 ds_assemble(i+1,i_regs);
5437 uint64_t bc_unneeded=branch_regs[i].u;
cf95b4f0 5438 bc_unneeded|=1|(1LL<<dops[i].rt1);
5439 bc_unneeded&=~(1LL<<dops[i].rs1);
ad49de89 5440 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,bc_unneeded);
cf95b4f0 5441 load_regs(regs[i].regmap,branch_regs[i].regmap,dops[i].rs1,CCREG);
57871462 5442 cc=get_reg(branch_regs[i].regmap,CCREG);
5443 assert(cc==HOST_CCREG);
581335b0 5444 (void)cc;
57871462 5445 #ifdef USE_MINI_HT
5446 int rh=get_reg(branch_regs[i].regmap,RHASH);
5447 int ht=get_reg(branch_regs[i].regmap,RHTBL);
cf95b4f0 5448 if(dops[i].rs1==31) {
57871462 5449 if(regs[i].regmap[rh]!=RHASH) do_preload_rhash(rh);
5450 do_preload_rhtbl(ht);
5451 do_rhash(rs,rh);
5452 }
5453 #endif
ad49de89 5454 store_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,-1);
57871462 5455 #ifdef DESTRUCTIVE_WRITEBACK
ad49de89 5456 if((branch_regs[i].dirty>>rs)&1) {
cf95b4f0 5457 if(dops[i].rs1!=dops[i+1].rt1&&dops[i].rs1!=dops[i+1].rt2) {
5458 emit_loadreg(dops[i].rs1,rs);
57871462 5459 }
5460 }
5461 #endif
5462 #ifdef REG_PREFETCH
cf95b4f0 5463 if(dops[i].rt1==31&&temp>=0) emit_prefetchreg(temp);
57871462 5464 #endif
5465 #ifdef USE_MINI_HT
cf95b4f0 5466 if(dops[i].rs1==31) {
57871462 5467 do_miniht_load(ht,rh);
5468 }
5469 #endif
5470 //do_cc(i,branch_regs[i].regmap,&adj,-1,TAKEN);
277718fa 5471 //if(adj) emit_addimm(cc,2*(cinfo[i].ccadj+2-adj),cc); // ??? - Shouldn't happen
57871462 5472 //assert(adj==0);
277718fa 5473 emit_addimm_and_set_flags(cinfo[i].ccadj + CLOCK_ADJUST(2), HOST_CCREG);
d1e4ebd9 5474 add_stub(CC_STUB,out,NULL,0,i,-1,TAKEN,rs);
a5cd72d0 5475 if (dops[i+1].itype == RFE)
911f2d55 5476 // special case for RFE
5477 emit_jmp(0);
5478 else
71e490c5 5479 emit_jns(0);
ad49de89 5480 //load_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,-1);
57871462 5481 #ifdef USE_MINI_HT
cf95b4f0 5482 if(dops[i].rs1==31) {
57871462 5483 do_miniht_jump(rs,rh,ht);
5484 }
5485 else
5486 #endif
5487 {
d1e4ebd9 5488 do_jump_vaddr(rs);
57871462 5489 }
57871462 5490 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
cf95b4f0 5491 if(dops[i].rt1!=31&&i<slen-2&&(((u_int)out)&7)) emit_mov(13,13);
57871462 5492 #endif
5493}
5494
2330734f 5495static void cjump_assemble(int i, const struct regstat *i_regs)
57871462 5496{
2330734f 5497 const signed char *i_regmap = i_regs->regmap;
57871462 5498 int cc;
5499 int match;
277718fa 5500 match=match_bt(branch_regs[i].regmap,branch_regs[i].dirty,cinfo[i].ba);
57871462 5501 assem_debug("match=%d\n",match);
ad49de89 5502 int s1l,s2l;
57871462 5503 int unconditional=0,nop=0;
57871462 5504 int invert=0;
277718fa 5505 int internal=internal_branch(cinfo[i].ba);
5506 if(i==(cinfo[i].ba-start)>>2) assem_debug("idle loop\n");
57871462 5507 if(!match) invert=1;
5508 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
277718fa 5509 if(i>(cinfo[i].ba-start)>>2) invert=1;
57871462 5510 #endif
3968e69e 5511 #ifdef __aarch64__
5512 invert=1; // because of near cond. branches
5513 #endif
9f51b4b9 5514
cf95b4f0 5515 if(dops[i].ooo) {
5516 s1l=get_reg(branch_regs[i].regmap,dops[i].rs1);
5517 s2l=get_reg(branch_regs[i].regmap,dops[i].rs2);
57871462 5518 }
5519 else {
cf95b4f0 5520 s1l=get_reg(i_regmap,dops[i].rs1);
5521 s2l=get_reg(i_regmap,dops[i].rs2);
57871462 5522 }
cf95b4f0 5523 if(dops[i].rs1==0&&dops[i].rs2==0)
57871462 5524 {
cf95b4f0 5525 if(dops[i].opcode&1) nop=1;
57871462 5526 else unconditional=1;
cf95b4f0 5527 //assert(dops[i].opcode!=5);
5528 //assert(dops[i].opcode!=7);
5529 //assert(dops[i].opcode!=0x15);
5530 //assert(dops[i].opcode!=0x17);
57871462 5531 }
cf95b4f0 5532 else if(dops[i].rs1==0)
57871462 5533 {
ad49de89 5534 s1l=s2l;
5535 s2l=-1;
57871462 5536 }
cf95b4f0 5537 else if(dops[i].rs2==0)
57871462 5538 {
ad49de89 5539 s2l=-1;
57871462 5540 }
5541
cf95b4f0 5542 if(dops[i].ooo) {
57871462 5543 // Out of order execution (delay slot first)
5544 //printf("OOOE\n");
5545 address_generation(i+1,i_regs,regs[i].regmap_entry);
5546 ds_assemble(i+1,i_regs);
5547 int adj;
5548 uint64_t bc_unneeded=branch_regs[i].u;
cf95b4f0 5549 bc_unneeded&=~((1LL<<dops[i].rs1)|(1LL<<dops[i].rs2));
57871462 5550 bc_unneeded|=1;
ad49de89 5551 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,bc_unneeded);
cf95b4f0 5552 load_regs(regs[i].regmap,branch_regs[i].regmap,dops[i].rs1,dops[i].rs2);
53358c1d 5553 load_reg(regs[i].regmap,branch_regs[i].regmap,CCREG);
57871462 5554 cc=get_reg(branch_regs[i].regmap,CCREG);
5555 assert(cc==HOST_CCREG);
9f51b4b9 5556 if(unconditional)
277718fa 5557 store_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,cinfo[i].ba);
5558 //do_cc(i,branch_regs[i].regmap,&adj,unconditional?cinfo[i].ba:-1,unconditional);
57871462 5559 //assem_debug("cycle count (adj)\n");
5560 if(unconditional) {
277718fa 5561 do_cc(i,branch_regs[i].regmap,&adj,cinfo[i].ba,TAKEN,0);
5562 if(i!=(cinfo[i].ba-start)>>2 || source[i+1]!=0) {
5563 if(adj) emit_addimm(cc, cinfo[i].ccadj + CLOCK_ADJUST(2) - adj, cc);
5564 load_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,cinfo[i].ba);
57871462 5565 if(internal)
5566 assem_debug("branch: internal\n");
5567 else
5568 assem_debug("branch: external\n");
277718fa 5569 if (internal && dops[(cinfo[i].ba-start)>>2].is_ds) {
57871462 5570 ds_assemble_entry(i);
5571 }
5572 else {
277718fa 5573 add_to_linker(out,cinfo[i].ba,internal);
57871462 5574 emit_jmp(0);
5575 }
5576 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5577 if(((u_int)out)&7) emit_addnop(0);
5578 #endif
5579 }
5580 }
5581 else if(nop) {
277718fa 5582 emit_addimm_and_set_flags(cinfo[i].ccadj + CLOCK_ADJUST(2), cc);
b14b6a8f 5583 void *jaddr=out;
57871462 5584 emit_jns(0);
b14b6a8f 5585 add_stub(CC_STUB,jaddr,out,0,i,start+i*4+8,NOTTAKEN,0);
57871462 5586 }
5587 else {
df4dc2b1 5588 void *taken = NULL, *nottaken = NULL, *nottaken1 = NULL;
57871462 5589 do_cc(i,branch_regs[i].regmap,&adj,-1,0,invert);
277718fa 5590 if(adj&&!invert) emit_addimm(cc, cinfo[i].ccadj + CLOCK_ADJUST(2) - adj, cc);
9f51b4b9 5591
57871462 5592 //printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5593 assert(s1l>=0);
cf95b4f0 5594 if(dops[i].opcode==4) // BEQ
57871462 5595 {
5596 if(s2l>=0) emit_cmp(s1l,s2l);
5597 else emit_test(s1l,s1l);
5598 if(invert){
df4dc2b1 5599 nottaken=out;
7c3a5182 5600 emit_jne(DJT_1);
57871462 5601 }else{
277718fa 5602 add_to_linker(out,cinfo[i].ba,internal);
57871462 5603 emit_jeq(0);
5604 }
5605 }
cf95b4f0 5606 if(dops[i].opcode==5) // BNE
57871462 5607 {
5608 if(s2l>=0) emit_cmp(s1l,s2l);
5609 else emit_test(s1l,s1l);
5610 if(invert){
df4dc2b1 5611 nottaken=out;
7c3a5182 5612 emit_jeq(DJT_1);
57871462 5613 }else{
277718fa 5614 add_to_linker(out,cinfo[i].ba,internal);
57871462 5615 emit_jne(0);
5616 }
5617 }
cf95b4f0 5618 if(dops[i].opcode==6) // BLEZ
57871462 5619 {
5620 emit_cmpimm(s1l,1);
5621 if(invert){
df4dc2b1 5622 nottaken=out;
7c3a5182 5623 emit_jge(DJT_1);
57871462 5624 }else{
277718fa 5625 add_to_linker(out,cinfo[i].ba,internal);
57871462 5626 emit_jl(0);
5627 }
5628 }
cf95b4f0 5629 if(dops[i].opcode==7) // BGTZ
57871462 5630 {
5631 emit_cmpimm(s1l,1);
5632 if(invert){
df4dc2b1 5633 nottaken=out;
7c3a5182 5634 emit_jl(DJT_1);
57871462 5635 }else{
277718fa 5636 add_to_linker(out,cinfo[i].ba,internal);
57871462 5637 emit_jge(0);
5638 }
5639 }
5640 if(invert) {
df4dc2b1 5641 if(taken) set_jump_target(taken, out);
57871462 5642 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
277718fa 5643 if (match && (!internal || !dops[(cinfo[i].ba-start)>>2].is_ds)) {
57871462 5644 if(adj) {
2330734f 5645 emit_addimm(cc,-adj,cc);
277718fa 5646 add_to_linker(out,cinfo[i].ba,internal);
57871462 5647 }else{
5648 emit_addnop(13);
277718fa 5649 add_to_linker(out,cinfo[i].ba,internal*2);
57871462 5650 }
5651 emit_jmp(0);
5652 }else
5653 #endif
5654 {
2330734f 5655 if(adj) emit_addimm(cc,-adj,cc);
277718fa 5656 store_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,cinfo[i].ba);
5657 load_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,cinfo[i].ba);
57871462 5658 if(internal)
5659 assem_debug("branch: internal\n");
5660 else
5661 assem_debug("branch: external\n");
277718fa 5662 if (internal && dops[(cinfo[i].ba - start) >> 2].is_ds) {
57871462 5663 ds_assemble_entry(i);
5664 }
5665 else {
277718fa 5666 add_to_linker(out,cinfo[i].ba,internal);
57871462 5667 emit_jmp(0);
5668 }
5669 }
df4dc2b1 5670 set_jump_target(nottaken, out);
57871462 5671 }
5672
df4dc2b1 5673 if(nottaken1) set_jump_target(nottaken1, out);
57871462 5674 if(adj) {
2330734f 5675 if(!invert) emit_addimm(cc,adj,cc);
57871462 5676 }
5677 } // (!unconditional)
5678 } // if(ooo)
5679 else
5680 {
5681 // In-order execution (branch first)
df4dc2b1 5682 void *taken = NULL, *nottaken = NULL, *nottaken1 = NULL;
57871462 5683 if(!unconditional&&!nop) {
57871462 5684 //printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5685 assert(s1l>=0);
cf95b4f0 5686 if((dops[i].opcode&0x2f)==4) // BEQ
57871462 5687 {
5688 if(s2l>=0) emit_cmp(s1l,s2l);
5689 else emit_test(s1l,s1l);
df4dc2b1 5690 nottaken=out;
7c3a5182 5691 emit_jne(DJT_2);
57871462 5692 }
cf95b4f0 5693 if((dops[i].opcode&0x2f)==5) // BNE
57871462 5694 {
5695 if(s2l>=0) emit_cmp(s1l,s2l);
5696 else emit_test(s1l,s1l);
df4dc2b1 5697 nottaken=out;
7c3a5182 5698 emit_jeq(DJT_2);
57871462 5699 }
cf95b4f0 5700 if((dops[i].opcode&0x2f)==6) // BLEZ
57871462 5701 {
5702 emit_cmpimm(s1l,1);
df4dc2b1 5703 nottaken=out;
7c3a5182 5704 emit_jge(DJT_2);
57871462 5705 }
cf95b4f0 5706 if((dops[i].opcode&0x2f)==7) // BGTZ
57871462 5707 {
5708 emit_cmpimm(s1l,1);
df4dc2b1 5709 nottaken=out;
7c3a5182 5710 emit_jl(DJT_2);
57871462 5711 }
5712 } // if(!unconditional)
5713 int adj;
5714 uint64_t ds_unneeded=branch_regs[i].u;
cf95b4f0 5715 ds_unneeded&=~((1LL<<dops[i+1].rs1)|(1LL<<dops[i+1].rs2));
57871462 5716 ds_unneeded|=1;
57871462 5717 // branch taken
5718 if(!nop) {
df4dc2b1 5719 if(taken) set_jump_target(taken, out);
57871462 5720 assem_debug("1:\n");
ad49de89 5721 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,ds_unneeded);
57871462 5722 // load regs
cf95b4f0 5723 load_regs(regs[i].regmap,branch_regs[i].regmap,dops[i+1].rs1,dops[i+1].rs2);
57871462 5724 address_generation(i+1,&branch_regs[i],0);
37387d8b 5725 if (ram_offset)
53358c1d 5726 load_reg(regs[i].regmap,branch_regs[i].regmap,ROREG);
ad49de89 5727 load_regs(regs[i].regmap,branch_regs[i].regmap,CCREG,INVCP);
57871462 5728 ds_assemble(i+1,&branch_regs[i]);
4f13a577 5729 drc_dbg_emit_wb_dirtys(i+1, &branch_regs[i]);
57871462 5730 cc=get_reg(branch_regs[i].regmap,CCREG);
5731 if(cc==-1) {
5732 emit_loadreg(CCREG,cc=HOST_CCREG);
5733 // CHECK: Is the following instruction (fall thru) allocated ok?
5734 }
5735 assert(cc==HOST_CCREG);
277718fa 5736 store_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,cinfo[i].ba);
5737 do_cc(i,i_regmap,&adj,cinfo[i].ba,TAKEN,0);
57871462 5738 assem_debug("cycle count (adj)\n");
277718fa 5739 if(adj) emit_addimm(cc, cinfo[i].ccadj + CLOCK_ADJUST(2) - adj, cc);
5740 load_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,cinfo[i].ba);
57871462 5741 if(internal)
5742 assem_debug("branch: internal\n");
5743 else
5744 assem_debug("branch: external\n");
277718fa 5745 if (internal && dops[(cinfo[i].ba - start) >> 2].is_ds) {
57871462 5746 ds_assemble_entry(i);
5747 }
5748 else {
277718fa 5749 add_to_linker(out,cinfo[i].ba,internal);
57871462 5750 emit_jmp(0);
5751 }
5752 }
5753 // branch not taken
57871462 5754 if(!unconditional) {
df4dc2b1 5755 if(nottaken1) set_jump_target(nottaken1, out);
5756 set_jump_target(nottaken, out);
57871462 5757 assem_debug("2:\n");
fe807a8a 5758 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,ds_unneeded);
37387d8b 5759 // load regs
fe807a8a 5760 load_regs(regs[i].regmap,branch_regs[i].regmap,dops[i+1].rs1,dops[i+1].rs2);
5761 address_generation(i+1,&branch_regs[i],0);
37387d8b 5762 if (ram_offset)
53358c1d 5763 load_reg(regs[i].regmap,branch_regs[i].regmap,ROREG);
37387d8b 5764 load_regs(regs[i].regmap,branch_regs[i].regmap,CCREG,INVCP);
fe807a8a 5765 ds_assemble(i+1,&branch_regs[i]);
57871462 5766 cc=get_reg(branch_regs[i].regmap,CCREG);
fe807a8a 5767 if (cc == -1) {
57871462 5768 // Cycle count isn't in a register, temporarily load it then write it out
5769 emit_loadreg(CCREG,HOST_CCREG);
277718fa 5770 emit_addimm_and_set_flags(cinfo[i].ccadj + CLOCK_ADJUST(2), HOST_CCREG);
b14b6a8f 5771 void *jaddr=out;
57871462 5772 emit_jns(0);
b14b6a8f 5773 add_stub(CC_STUB,jaddr,out,0,i,start+i*4+8,NOTTAKEN,0);
57871462 5774 emit_storereg(CCREG,HOST_CCREG);
5775 }
5776 else{
5777 cc=get_reg(i_regmap,CCREG);
5778 assert(cc==HOST_CCREG);
277718fa 5779 emit_addimm_and_set_flags(cinfo[i].ccadj + CLOCK_ADJUST(2), cc);
b14b6a8f 5780 void *jaddr=out;
57871462 5781 emit_jns(0);
fe807a8a 5782 add_stub(CC_STUB,jaddr,out,0,i,start+i*4+8,NOTTAKEN,0);
57871462 5783 }
5784 }
5785 }
5786}
5787
2330734f 5788static void sjump_assemble(int i, const struct regstat *i_regs)
57871462 5789{
2330734f 5790 const signed char *i_regmap = i_regs->regmap;
57871462 5791 int cc;
5792 int match;
277718fa 5793 match=match_bt(branch_regs[i].regmap,branch_regs[i].dirty,cinfo[i].ba);
2acc46cd 5794 assem_debug("smatch=%d ooo=%d\n", match, dops[i].ooo);
ad49de89 5795 int s1l;
57871462 5796 int unconditional=0,nevertaken=0;
57871462 5797 int invert=0;
277718fa 5798 int internal=internal_branch(cinfo[i].ba);
5799 if(i==(cinfo[i].ba-start)>>2) assem_debug("idle loop\n");
57871462 5800 if(!match) invert=1;
5801 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
277718fa 5802 if(i>(cinfo[i].ba-start)>>2) invert=1;
57871462 5803 #endif
3968e69e 5804 #ifdef __aarch64__
5805 invert=1; // because of near cond. branches
5806 #endif
57871462 5807
cf95b4f0 5808 //if(dops[i].opcode2>=0x10) return; // FIXME (BxxZAL)
5809 //assert(dops[i].opcode2<0x10||dops[i].rs1==0); // FIXME (BxxZAL)
57871462 5810
cf95b4f0 5811 if(dops[i].ooo) {
5812 s1l=get_reg(branch_regs[i].regmap,dops[i].rs1);
57871462 5813 }
5814 else {
cf95b4f0 5815 s1l=get_reg(i_regmap,dops[i].rs1);
57871462 5816 }
cf95b4f0 5817 if(dops[i].rs1==0)
57871462 5818 {
cf95b4f0 5819 if(dops[i].opcode2&1) unconditional=1;
57871462 5820 else nevertaken=1;
5821 // These are never taken (r0 is never less than zero)
cf95b4f0 5822 //assert(dops[i].opcode2!=0);
5823 //assert(dops[i].opcode2!=2);
5824 //assert(dops[i].opcode2!=0x10);
5825 //assert(dops[i].opcode2!=0x12);
57871462 5826 }
57871462 5827
cf95b4f0 5828 if(dops[i].ooo) {
57871462 5829 // Out of order execution (delay slot first)
5830 //printf("OOOE\n");
5831 address_generation(i+1,i_regs,regs[i].regmap_entry);
5832 ds_assemble(i+1,i_regs);
5833 int adj;
5834 uint64_t bc_unneeded=branch_regs[i].u;
cf95b4f0 5835 bc_unneeded&=~((1LL<<dops[i].rs1)|(1LL<<dops[i].rs2));
57871462 5836 bc_unneeded|=1;
ad49de89 5837 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,bc_unneeded);
cf95b4f0 5838 load_regs(regs[i].regmap,branch_regs[i].regmap,dops[i].rs1,dops[i].rs1);
53358c1d 5839 load_reg(regs[i].regmap,branch_regs[i].regmap,CCREG);
cf95b4f0 5840 if(dops[i].rt1==31) {
57871462 5841 int rt,return_address;
57871462 5842 rt=get_reg(branch_regs[i].regmap,31);
de6dbc52 5843 //assem_debug("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
57871462 5844 if(rt>=0) {
5845 // Save the PC even if the branch is not taken
5846 return_address=start+i*4+8;
5847 emit_movimm(return_address,rt); // PC into link register
5848 #ifdef IMM_PREFETCH
df4dc2b1 5849 if(!nevertaken) emit_prefetch(hash_table_get(return_address));
57871462 5850 #endif
5851 }
5852 }
5853 cc=get_reg(branch_regs[i].regmap,CCREG);
5854 assert(cc==HOST_CCREG);
9f51b4b9 5855 if(unconditional)
277718fa 5856 store_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,cinfo[i].ba);
5857 //do_cc(i,branch_regs[i].regmap,&adj,unconditional?cinfo[i].ba:-1,unconditional);
57871462 5858 assem_debug("cycle count (adj)\n");
5859 if(unconditional) {
277718fa 5860 do_cc(i,branch_regs[i].regmap,&adj,cinfo[i].ba,TAKEN,0);
5861 if(i!=(cinfo[i].ba-start)>>2 || source[i+1]!=0) {
5862 if(adj) emit_addimm(cc, cinfo[i].ccadj + CLOCK_ADJUST(2) - adj, cc);
5863 load_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,cinfo[i].ba);
57871462 5864 if(internal)
5865 assem_debug("branch: internal\n");
5866 else
5867 assem_debug("branch: external\n");
277718fa 5868 if (internal && dops[(cinfo[i].ba - start) >> 2].is_ds) {
57871462 5869 ds_assemble_entry(i);
5870 }
5871 else {
277718fa 5872 add_to_linker(out,cinfo[i].ba,internal);
57871462 5873 emit_jmp(0);
5874 }
5875 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5876 if(((u_int)out)&7) emit_addnop(0);
5877 #endif
5878 }
5879 }
5880 else if(nevertaken) {
277718fa 5881 emit_addimm_and_set_flags(cinfo[i].ccadj + CLOCK_ADJUST(2), cc);
b14b6a8f 5882 void *jaddr=out;
57871462 5883 emit_jns(0);
b14b6a8f 5884 add_stub(CC_STUB,jaddr,out,0,i,start+i*4+8,NOTTAKEN,0);
57871462 5885 }
5886 else {
df4dc2b1 5887 void *nottaken = NULL;
57871462 5888 do_cc(i,branch_regs[i].regmap,&adj,-1,0,invert);
277718fa 5889 if(adj&&!invert) emit_addimm(cc, cinfo[i].ccadj + CLOCK_ADJUST(2) - adj, cc);
57871462 5890 {
5891 assert(s1l>=0);
ecca05e3 5892 if ((dops[i].opcode2 & 1) == 0) // BLTZ/BLTZAL
57871462 5893 {
5894 emit_test(s1l,s1l);
5895 if(invert){
df4dc2b1 5896 nottaken=out;
7c3a5182 5897 emit_jns(DJT_1);
57871462 5898 }else{
277718fa 5899 add_to_linker(out,cinfo[i].ba,internal);
57871462 5900 emit_js(0);
5901 }
5902 }
ecca05e3 5903 else // BGEZ/BGEZAL
57871462 5904 {
5905 emit_test(s1l,s1l);
5906 if(invert){
df4dc2b1 5907 nottaken=out;
7c3a5182 5908 emit_js(DJT_1);
57871462 5909 }else{
277718fa 5910 add_to_linker(out,cinfo[i].ba,internal);
57871462 5911 emit_jns(0);
5912 }
5913 }
ad49de89 5914 }
9f51b4b9 5915
57871462 5916 if(invert) {
5917 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
277718fa 5918 if (match && (!internal || !dops[(cinfo[i].ba - start) >> 2].is_ds)) {
57871462 5919 if(adj) {
2330734f 5920 emit_addimm(cc,-adj,cc);
277718fa 5921 add_to_linker(out,cinfo[i].ba,internal);
57871462 5922 }else{
5923 emit_addnop(13);
277718fa 5924 add_to_linker(out,cinfo[i].ba,internal*2);
57871462 5925 }
5926 emit_jmp(0);
5927 }else
5928 #endif
5929 {
2330734f 5930 if(adj) emit_addimm(cc,-adj,cc);
277718fa 5931 store_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,cinfo[i].ba);
5932 load_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,cinfo[i].ba);
57871462 5933 if(internal)
5934 assem_debug("branch: internal\n");
5935 else
5936 assem_debug("branch: external\n");
277718fa 5937 if (internal && dops[(cinfo[i].ba - start) >> 2].is_ds) {
57871462 5938 ds_assemble_entry(i);
5939 }
5940 else {
277718fa 5941 add_to_linker(out,cinfo[i].ba,internal);
57871462 5942 emit_jmp(0);
5943 }
5944 }
df4dc2b1 5945 set_jump_target(nottaken, out);
57871462 5946 }
5947
5948 if(adj) {
2330734f 5949 if(!invert) emit_addimm(cc,adj,cc);
57871462 5950 }
5951 } // (!unconditional)
5952 } // if(ooo)
5953 else
5954 {
5955 // In-order execution (branch first)
5956 //printf("IOE\n");
df4dc2b1 5957 void *nottaken = NULL;
de6dbc52 5958 if (!unconditional && !nevertaken) {
ecca05e3 5959 assert(s1l >= 0);
5960 emit_test(s1l, s1l);
5961 }
5962 if (dops[i].rt1 == 31) {
5963 int rt, return_address;
5964 rt = get_reg(branch_regs[i].regmap,31);
5965 if(rt >= 0) {
a6491170 5966 // Save the PC even if the branch is not taken
ecca05e3 5967 return_address = start + i*4+8;
5968 emit_movimm(return_address, rt); // PC into link register
a6491170 5969 #ifdef IMM_PREFETCH
df4dc2b1 5970 emit_prefetch(hash_table_get(return_address));
a6491170 5971 #endif
5972 }
5973 }
de6dbc52 5974 if (!unconditional && !nevertaken) {
ecca05e3 5975 nottaken = out;
5976 if (!(dops[i].opcode2 & 1)) // BLTZ/BLTZAL
5977 emit_jns(DJT_1);
5978 else // BGEZ/BGEZAL
5979 emit_js(DJT_1);
5980 }
57871462 5981 int adj;
5982 uint64_t ds_unneeded=branch_regs[i].u;
cf95b4f0 5983 ds_unneeded&=~((1LL<<dops[i+1].rs1)|(1LL<<dops[i+1].rs2));
57871462 5984 ds_unneeded|=1;
57871462 5985 // branch taken
5986 if(!nevertaken) {
5987 //assem_debug("1:\n");
ad49de89 5988 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,ds_unneeded);
57871462 5989 // load regs
cf95b4f0 5990 load_regs(regs[i].regmap,branch_regs[i].regmap,dops[i+1].rs1,dops[i+1].rs2);
57871462 5991 address_generation(i+1,&branch_regs[i],0);
37387d8b 5992 if (ram_offset)
53358c1d 5993 load_reg(regs[i].regmap,branch_regs[i].regmap,ROREG);
ad49de89 5994 load_regs(regs[i].regmap,branch_regs[i].regmap,CCREG,INVCP);
57871462 5995 ds_assemble(i+1,&branch_regs[i]);
5996 cc=get_reg(branch_regs[i].regmap,CCREG);
5997 if(cc==-1) {
5998 emit_loadreg(CCREG,cc=HOST_CCREG);
5999 // CHECK: Is the following instruction (fall thru) allocated ok?
6000 }
6001 assert(cc==HOST_CCREG);
277718fa 6002 store_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,cinfo[i].ba);
6003 do_cc(i,i_regmap,&adj,cinfo[i].ba,TAKEN,0);
57871462 6004 assem_debug("cycle count (adj)\n");
277718fa 6005 if(adj) emit_addimm(cc, cinfo[i].ccadj + CLOCK_ADJUST(2) - adj, cc);
6006 load_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,cinfo[i].ba);
57871462 6007 if(internal)
6008 assem_debug("branch: internal\n");
6009 else
6010 assem_debug("branch: external\n");
277718fa 6011 if (internal && dops[(cinfo[i].ba - start) >> 2].is_ds) {
57871462 6012 ds_assemble_entry(i);
6013 }
6014 else {
277718fa 6015 add_to_linker(out,cinfo[i].ba,internal);
57871462 6016 emit_jmp(0);
6017 }
6018 }
6019 // branch not taken
57871462 6020 if(!unconditional) {
de6dbc52 6021 if (!nevertaken) {
6022 assert(nottaken);
6023 set_jump_target(nottaken, out);
6024 }
57871462 6025 assem_debug("1:\n");
fe807a8a 6026 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,ds_unneeded);
6027 load_regs(regs[i].regmap,branch_regs[i].regmap,dops[i+1].rs1,dops[i+1].rs2);
6028 address_generation(i+1,&branch_regs[i],0);
5a18ce2e 6029 if (ram_offset)
53358c1d 6030 load_reg(regs[i].regmap,branch_regs[i].regmap,ROREG);
5a18ce2e 6031 load_regs(regs[i].regmap,branch_regs[i].regmap,CCREG,INVCP);
fe807a8a 6032 ds_assemble(i+1,&branch_regs[i]);
57871462 6033 cc=get_reg(branch_regs[i].regmap,CCREG);
fe807a8a 6034 if (cc == -1) {
57871462 6035 // Cycle count isn't in a register, temporarily load it then write it out
6036 emit_loadreg(CCREG,HOST_CCREG);
277718fa 6037 emit_addimm_and_set_flags(cinfo[i].ccadj + CLOCK_ADJUST(2), HOST_CCREG);
b14b6a8f 6038 void *jaddr=out;
57871462 6039 emit_jns(0);
b14b6a8f 6040 add_stub(CC_STUB,jaddr,out,0,i,start+i*4+8,NOTTAKEN,0);
57871462 6041 emit_storereg(CCREG,HOST_CCREG);
6042 }
6043 else{
6044 cc=get_reg(i_regmap,CCREG);
6045 assert(cc==HOST_CCREG);
277718fa 6046 emit_addimm_and_set_flags(cinfo[i].ccadj + CLOCK_ADJUST(2), cc);
b14b6a8f 6047 void *jaddr=out;
57871462 6048 emit_jns(0);
fe807a8a 6049 add_stub(CC_STUB,jaddr,out,0,i,start+i*4+8,NOTTAKEN,0);
57871462 6050 }
6051 }
6052 }
6053}
6054
670c0f22 6055static void check_regmap(signed char *regmap)
6056{
6057#ifndef NDEBUG
6058 int i,j;
6059 for (i = 0; i < HOST_REGS; i++) {
6060 if (regmap[i] < 0)
6061 continue;
6062 for (j = i + 1; j < HOST_REGS; j++)
6063 assert(regmap[i] != regmap[j]);
6064 }
6065#endif
6066}
6067
4600ba03 6068#ifdef DISASM
2acc46cd 6069#include <inttypes.h>
53dc27f6 6070static char insn[MAXBLOCK][10];
6071
6072#define set_mnemonic(i_, n_) \
6073 strcpy(insn[i_], n_)
6074
2acc46cd 6075void print_regmap(const char *name, const signed char *regmap)
6076{
6077 char buf[5];
6078 int i, l;
6079 fputs(name, stdout);
6080 for (i = 0; i < HOST_REGS; i++) {
6081 l = 0;
6082 if (regmap[i] >= 0)
6083 l = snprintf(buf, sizeof(buf), "$%d", regmap[i]);
6084 for (; l < 3; l++)
6085 buf[l] = ' ';
6086 buf[l] = 0;
6087 printf(" r%d=%s", i, buf);
6088 }
6089 fputs("\n", stdout);
6090}
6091
57871462 6092 /* disassembly */
6093void disassemble_inst(int i)
6094{
cf95b4f0 6095 if (dops[i].bt) printf("*"); else printf(" ");
6096 switch(dops[i].itype) {
57871462 6097 case UJUMP:
277718fa 6098 printf (" %x: %s %8x\n",start+i*4,insn[i],cinfo[i].ba);break;
57871462 6099 case CJUMP:
277718fa 6100 printf (" %x: %s r%d,r%d,%8x\n",start+i*4,insn[i],dops[i].rs1,dops[i].rs2,i?start+i*4+4+((signed int)((unsigned int)source[i]<<16)>>14):cinfo[i].ba);break;
57871462 6101 case SJUMP:
cf95b4f0 6102 printf (" %x: %s r%d,%8x\n",start+i*4,insn[i],dops[i].rs1,start+i*4+4+((signed int)((unsigned int)source[i]<<16)>>14));break;
57871462 6103 case RJUMP:
ecca05e3 6104 if (dops[i].opcode2 == 9 && dops[i].rt1 != 31)
cf95b4f0 6105 printf (" %x: %s r%d,r%d\n",start+i*4,insn[i],dops[i].rt1,dops[i].rs1);
5067f341 6106 else
cf95b4f0 6107 printf (" %x: %s r%d\n",start+i*4,insn[i],dops[i].rs1);
5067f341 6108 break;
57871462 6109 case IMM16:
cf95b4f0 6110 if(dops[i].opcode==0xf) //LUI
277718fa 6111 printf (" %x: %s r%d,%4x0000\n",start+i*4,insn[i],dops[i].rt1,cinfo[i].imm&0xffff);
57871462 6112 else
277718fa 6113 printf (" %x: %s r%d,r%d,%d\n",start+i*4,insn[i],dops[i].rt1,dops[i].rs1,cinfo[i].imm);
57871462 6114 break;
6115 case LOAD:
6116 case LOADLR:
277718fa 6117 printf (" %x: %s r%d,r%d+%x\n",start+i*4,insn[i],dops[i].rt1,dops[i].rs1,cinfo[i].imm);
57871462 6118 break;
6119 case STORE:
6120 case STORELR:
277718fa 6121 printf (" %x: %s r%d,r%d+%x\n",start+i*4,insn[i],dops[i].rs2,dops[i].rs1,cinfo[i].imm);
57871462 6122 break;
6123 case ALU:
6124 case SHIFT:
cf95b4f0 6125 printf (" %x: %s r%d,r%d,r%d\n",start+i*4,insn[i],dops[i].rt1,dops[i].rs1,dops[i].rs2);
57871462 6126 break;
6127 case MULTDIV:
cf95b4f0 6128 printf (" %x: %s r%d,r%d\n",start+i*4,insn[i],dops[i].rs1,dops[i].rs2);
57871462 6129 break;
6130 case SHIFTIMM:
277718fa 6131 printf (" %x: %s r%d,r%d,%d\n",start+i*4,insn[i],dops[i].rt1,dops[i].rs1,cinfo[i].imm);
57871462 6132 break;
6133 case MOV:
cf95b4f0 6134 if((dops[i].opcode2&0x1d)==0x10)
6135 printf (" %x: %s r%d\n",start+i*4,insn[i],dops[i].rt1);
6136 else if((dops[i].opcode2&0x1d)==0x11)
6137 printf (" %x: %s r%d\n",start+i*4,insn[i],dops[i].rs1);
57871462 6138 else
6139 printf (" %x: %s\n",start+i*4,insn[i]);
6140 break;
6141 case COP0:
cf95b4f0 6142 if(dops[i].opcode2==0)
6143 printf (" %x: %s r%d,cpr0[%d]\n",start+i*4,insn[i],dops[i].rt1,(source[i]>>11)&0x1f); // MFC0
6144 else if(dops[i].opcode2==4)
6145 printf (" %x: %s r%d,cpr0[%d]\n",start+i*4,insn[i],dops[i].rs1,(source[i]>>11)&0x1f); // MTC0
57871462 6146 else printf (" %x: %s\n",start+i*4,insn[i]);
6147 break;
b9b61529 6148 case COP2:
cf95b4f0 6149 if(dops[i].opcode2<3)
6150 printf (" %x: %s r%d,cpr2[%d]\n",start+i*4,insn[i],dops[i].rt1,(source[i]>>11)&0x1f); // MFC2
6151 else if(dops[i].opcode2>3)
6152 printf (" %x: %s r%d,cpr2[%d]\n",start+i*4,insn[i],dops[i].rs1,(source[i]>>11)&0x1f); // MTC2
b9b61529 6153 else printf (" %x: %s\n",start+i*4,insn[i]);
6154 break;
b9b61529 6155 case C2LS:
277718fa 6156 printf (" %x: %s cpr2[%d],r%d+%x\n",start+i*4,insn[i],(source[i]>>16)&0x1f,dops[i].rs1,cinfo[i].imm);
b9b61529 6157 break;
1e973cb0 6158 case INTCALL:
6159 printf (" %x: %s (INTCALL)\n",start+i*4,insn[i]);
6160 break;
57871462 6161 default:
6162 //printf (" %s %8x\n",insn[i],source[i]);
6163 printf (" %x: %s\n",start+i*4,insn[i]);
6164 }
a5cd72d0 6165 #ifndef REGMAP_PRINT
2acc46cd 6166 return;
a5cd72d0 6167 #endif
33a1eda1 6168 printf("D: %x WD: %x U: %"PRIx64" hC: %x hWC: %x hLC: %x\n",
a5cd72d0 6169 regs[i].dirty, regs[i].wasdirty, unneeded_reg[i],
6170 regs[i].isconst, regs[i].wasconst, regs[i].loadedconst);
2acc46cd 6171 print_regmap("pre: ", regmap_pre[i]);
6172 print_regmap("entry: ", regs[i].regmap_entry);
6173 print_regmap("map: ", regs[i].regmap);
6174 if (dops[i].is_jump) {
6175 print_regmap("bentry:", branch_regs[i].regmap_entry);
6176 print_regmap("bmap: ", branch_regs[i].regmap);
6177 }
57871462 6178}
4600ba03 6179#else
53dc27f6 6180#define set_mnemonic(i_, n_)
4600ba03 6181static void disassemble_inst(int i) {}
6182#endif // DISASM
57871462 6183
d848b60a 6184#define DRC_TEST_VAL 0x74657374
6185
d9e2b173 6186static noinline void new_dynarec_test(void)
d848b60a 6187{
be516ebe 6188 int (*testfunc)(void);
d148d265 6189 void *beginning;
be516ebe 6190 int ret[2];
6191 size_t i;
d148d265 6192
687b4580 6193 // check structure linkage
7c3a5182 6194 if ((u_char *)rcnts - (u_char *)&psxRegs != sizeof(psxRegs))
687b4580 6195 {
7c3a5182 6196 SysPrintf("linkage_arm* miscompilation/breakage detected.\n");
687b4580 6197 }
6198
d9e2b173 6199 SysPrintf("(%p) testing if we can run recompiled code @%p...\n",
6200 new_dynarec_test, out);
6201 ((volatile u_int *)NDRC_WRITE_OFFSET(out))[0]++; // make the cache dirty
be516ebe 6202
6203 for (i = 0; i < ARRAY_SIZE(ret); i++) {
2a014d73 6204 out = ndrc->translation_cache;
be516ebe 6205 beginning = start_block();
6206 emit_movimm(DRC_TEST_VAL + i, 0); // test
6207 emit_ret();
6208 literal_pool(0);
6209 end_block(beginning);
6210 testfunc = beginning;
6211 ret[i] = testfunc();
6212 }
6213
6214 if (ret[0] == DRC_TEST_VAL && ret[1] == DRC_TEST_VAL + 1)
d848b60a 6215 SysPrintf("test passed.\n");
6216 else
be516ebe 6217 SysPrintf("test failed, will likely crash soon (r=%08x %08x)\n", ret[0], ret[1]);
2a014d73 6218 out = ndrc->translation_cache;
d848b60a 6219}
6220
42eb665e 6221static int get_cycle_multiplier(void)
6222{
6223 return Config.cycle_multiplier_override && Config.cycle_multiplier == CYCLE_MULT_DEFAULT
6224 ? Config.cycle_multiplier_override : Config.cycle_multiplier;
6225}
6226
dc990066 6227// clear the state completely, instead of just marking
6228// things invalid like invalidate_all_pages() does
919981d0 6229void new_dynarec_clear_full(void)
57871462 6230{
57871462 6231 int n;
2a014d73 6232 out = ndrc->translation_cache;
35775df7 6233 memset(invalid_code,1,sizeof(invalid_code));
dc990066 6234 memset(shadow,0,sizeof(shadow));
04714958 6235 hash_table_clear();
6236 mini_ht_clear();
57871462 6237 copy=shadow;
93c0345b 6238 expirep = EXPIRITY_OFFSET;
57871462 6239 pending_exception=0;
6240 literalcount=0;
57871462 6241 stop_after_jal=0;
9be4ba64 6242 inv_code_start=inv_code_end=~0;
7f94b097 6243 hack_addr=0;
39b71d9a 6244 f1_hack=0;
93c0345b 6245 for (n = 0; n < ARRAY_SIZE(blocks); n++)
6246 blocks_clear(&blocks[n]);
b7ad2f2c 6247 for (n = 0; n < ARRAY_SIZE(jumps); n++) {
6248 free(jumps[n]);
6249 jumps[n] = NULL;
6250 }
104df9d3 6251 stat_clear(stat_blocks);
6252 stat_clear(stat_links);
32631e6a 6253
42eb665e 6254 if (cycle_multiplier_old != Config.cycle_multiplier
6255 || new_dynarec_hacks_old != new_dynarec_hacks)
6256 {
6257 SysPrintf("ndrc config: mul=%d, ha=%x, pex=%d\n",
6258 get_cycle_multiplier(), new_dynarec_hacks, Config.PreciseExceptions);
6259 }
d5aeda23 6260 cycle_multiplier_old = Config.cycle_multiplier;
32631e6a 6261 new_dynarec_hacks_old = new_dynarec_hacks;
dc990066 6262}
6263
899d08bd 6264static int pgsize(void)
6265{
6266#ifdef _SC_PAGESIZE
6267 return sysconf(_SC_PAGESIZE);
6268#else
6269 return 4096;
6270#endif
6271}
6272
919981d0 6273void new_dynarec_init(void)
dc990066 6274{
899d08bd 6275 int align = pgsize() - 1;
6276 SysPrintf("Init new dynarec, ndrc size %x, pgsize %d\n",
6277 (int)sizeof(*ndrc), align + 1);
1e212a25 6278
0aeb0cb9 6279#ifdef _3DS
6280 check_rosalina();
6281#endif
2a014d73 6282#ifdef BASE_ADDR_DYNAMIC
1e212a25 6283 #ifdef VITA
0aeb0cb9 6284 sceBlock = getVMBlock(); //sceKernelAllocMemBlockForVM("code", sizeof(*ndrc));
66ea165f 6285 if (sceBlock <= 0)
6286 SysPrintf("sceKernelAllocMemBlockForVM failed: %x\n", sceBlock);
2a014d73 6287 int ret = sceKernelGetMemBlockBase(sceBlock, (void **)&ndrc);
1e212a25 6288 if (ret < 0)
66ea165f 6289 SysPrintf("sceKernelGetMemBlockBase failed: %x\n", ret);
0aeb0cb9 6290 sceKernelOpenVMDomain();
6291 sceClibPrintf("translation_cache = 0x%08lx\n ", (long)ndrc->translation_cache);
6292 #elif defined(_MSC_VER)
6293 ndrc = VirtualAlloc(NULL, sizeof(*ndrc), MEM_COMMIT | MEM_RESERVE,
6294 PAGE_EXECUTE_READWRITE);
3039c914 6295 #elif defined(HAVE_LIBNX)
6296 Result rc = jitCreate(&g_jit, sizeof(*ndrc));
6297 if (R_FAILED(rc))
6298 SysPrintf("jitCreate failed: %08x\n", rc);
6299 SysPrintf("jitCreate: RX: %p RW: %p type: %d\n", g_jit.rx_addr, g_jit.rw_addr, g_jit.type);
d9e2b173 6300 jitTransitionToWritable(&g_jit);
3039c914 6301 ndrc = g_jit.rx_addr;
6302 ndrc_write_ofs = (char *)g_jit.rw_addr - (char *)ndrc;
d9e2b173 6303 memset(NDRC_WRITE_OFFSET(&ndrc->tramp), 0, sizeof(ndrc->tramp));
1e212a25 6304 #else
2a014d73 6305 uintptr_t desired_addr = 0;
3039c914 6306 int prot = PROT_READ | PROT_WRITE | PROT_EXEC;
6307 int flags = MAP_PRIVATE | MAP_ANONYMOUS;
6308 int fd = -1;
2a014d73 6309 #ifdef __ELF__
6310 extern char _end;
6311 desired_addr = ((uintptr_t)&_end + 0xffffff) & ~0xffffffl;
6312 #endif
d9e2b173 6313 #ifdef TC_WRITE_OFFSET
3039c914 6314 // mostly for testing
6315 fd = open("/dev/shm/pcsxr", O_CREAT | O_RDWR, 0600);
6316 ftruncate(fd, sizeof(*ndrc));
6317 void *mw = mmap(NULL, sizeof(*ndrc), PROT_READ | PROT_WRITE,
6318 (flags = MAP_SHARED), fd, 0);
6319 assert(mw != MAP_FAILED);
6320 prot = PROT_READ | PROT_EXEC;
6321 #endif
6322 ndrc = mmap((void *)desired_addr, sizeof(*ndrc), prot, flags, fd, 0);
2a014d73 6323 if (ndrc == MAP_FAILED) {
d848b60a 6324 SysPrintf("mmap() failed: %s\n", strerror(errno));
1e212a25 6325 abort();
d848b60a 6326 }
d9e2b173 6327 #ifdef TC_WRITE_OFFSET
3039c914 6328 ndrc_write_ofs = (char *)mw - (char *)ndrc;
6329 #endif
1e212a25 6330 #endif
6331#else
6332 #ifndef NO_WRITE_EXEC
899d08bd 6333 ndrc = (struct ndrc_mem *)((size_t)(ndrc_bss + align) & ~align);
bdeade46 6334 // not all systems allow execute in data segment by default
761fdd0a 6335 // size must be 4K aligned for 3DS?
6336 if (mprotect(ndrc, sizeof(*ndrc),
2a014d73 6337 PROT_READ | PROT_WRITE | PROT_EXEC) != 0)
899d08bd 6338 SysPrintf("mprotect(%p) failed: %s\n", ndrc, strerror(errno));
1e212a25 6339 #endif
dc990066 6340#endif
2a014d73 6341 out = ndrc->translation_cache;
dc990066 6342 new_dynarec_clear_full();
6343#ifdef HOST_IMM8
6344 // Copy this into local area so we don't have to put it in every literal pool
6345 invc_ptr=invalid_code;
6346#endif
57871462 6347 arch_init();
d848b60a 6348 new_dynarec_test();
33a1eda1 6349 ram_offset = (uintptr_t)psxM - 0x80000000;
b105cf4f 6350 if (ram_offset!=0)
c43b5311 6351 SysPrintf("warning: RAM is not directly mapped, performance will suffer\n");
398d6924 6352 SysPrintf("Mapped (RAM/scrp/ROM/LUTs/TC):\n");
6353 SysPrintf("%p/%p/%p/%p/%p\n", psxM, psxH, psxR, mem_rtab, out);
57871462 6354}
6355
919981d0 6356void new_dynarec_cleanup(void)
57871462 6357{
6358 int n;
2a014d73 6359#ifdef BASE_ADDR_DYNAMIC
1e212a25 6360 #ifdef VITA
66ea165f 6361 // sceBlock is managed by retroarch's bootstrap code
9c67c98f 6362 //sceKernelFreeMemBlock(sceBlock);
6363 //sceBlock = -1;
3039c914 6364 #elif defined(HAVE_LIBNX)
6365 jitClose(&g_jit);
6366 ndrc = NULL;
1e212a25 6367 #else
2a014d73 6368 if (munmap(ndrc, sizeof(*ndrc)) < 0)
1e212a25 6369 SysPrintf("munmap() failed\n");
3039c914 6370 ndrc = NULL;
bdeade46 6371 #endif
1e212a25 6372#endif
93c0345b 6373 for (n = 0; n < ARRAY_SIZE(blocks); n++)
6374 blocks_clear(&blocks[n]);
b7ad2f2c 6375 for (n = 0; n < ARRAY_SIZE(jumps); n++) {
6376 free(jumps[n]);
6377 jumps[n] = NULL;
6378 }
104df9d3 6379 stat_clear(stat_blocks);
6380 stat_clear(stat_links);
ece032e6 6381 new_dynarec_print_stats();
57871462 6382}
6383
03f55e6b 6384static u_int *get_source_start(u_int addr, u_int *limit)
57871462 6385{
33a1eda1 6386 if (addr < 0x00800000
6387 || (0x80000000 <= addr && addr < 0x80800000)
6388 || (0xa0000000 <= addr && addr < 0xa0800000))
a3203cf4 6389 {
03f55e6b 6390 // used for BIOS calls mostly?
33a1eda1 6391 *limit = (addr & 0xa0600000) + 0x00200000;
6392 return (u_int *)(psxM + (addr & 0x1fffff));
03f55e6b 6393 }
a5539d92 6394 else if (
03f55e6b 6395 /* (0x9fc00000 <= addr && addr < 0x9fc80000) ||*/
a5539d92 6396 (0xbfc00000 <= addr && addr < 0xbfc80000))
a3203cf4 6397 {
6398 // BIOS. The multiplier should be much higher as it's uncached 8bit mem,
d5aeda23 6399 // but timings in PCSX are too tied to the interpreter's 2-per-insn assumption
d62c125a 6400 if (!HACK_ENABLED(NDHACK_OVERRIDE_CYCLE_M))
24058131 6401 cycle_multiplier_active = 200;
a3203cf4 6402
03f55e6b 6403 *limit = (addr & 0xfff00000) | 0x80000;
01d26796 6404 return (u_int *)((u_char *)psxR + (addr&0x7ffff));
03f55e6b 6405 }
581335b0 6406 return NULL;
03f55e6b 6407}
6408
6409static u_int scan_for_ret(u_int addr)
6410{
6411 u_int limit = 0;
6412 u_int *mem;
6413
6414 mem = get_source_start(addr, &limit);
6415 if (mem == NULL)
6416 return addr;
6417
6418 if (limit > addr + 0x1000)
6419 limit = addr + 0x1000;
6420 for (; addr < limit; addr += 4, mem++) {
6421 if (*mem == 0x03e00008) // jr $ra
6422 return addr + 8;
57871462 6423 }
581335b0 6424 return addr;
03f55e6b 6425}
6426
6427struct savestate_block {
6428 uint32_t addr;
6429 uint32_t regflags;
6430};
6431
6432static int addr_cmp(const void *p1_, const void *p2_)
6433{
6434 const struct savestate_block *p1 = p1_, *p2 = p2_;
6435 return p1->addr - p2->addr;
6436}
6437
6438int new_dynarec_save_blocks(void *save, int size)
6439{
104df9d3 6440 struct savestate_block *sblocks = save;
6441 int maxcount = size / sizeof(sblocks[0]);
03f55e6b 6442 struct savestate_block tmp_blocks[1024];
104df9d3 6443 struct block_info *block;
03f55e6b 6444 int p, s, d, o, bcnt;
6445 u_int addr;
6446
6447 o = 0;
104df9d3 6448 for (p = 0; p < ARRAY_SIZE(blocks); p++) {
03f55e6b 6449 bcnt = 0;
104df9d3 6450 for (block = blocks[p]; block != NULL; block = block->next) {
6451 if (block->is_dirty)
6452 continue;
6453 tmp_blocks[bcnt].addr = block->start;
6454 tmp_blocks[bcnt].regflags = block->reg_sv_flags;
03f55e6b 6455 bcnt++;
6456 }
6457 if (bcnt < 1)
6458 continue;
6459 qsort(tmp_blocks, bcnt, sizeof(tmp_blocks[0]), addr_cmp);
6460
6461 addr = tmp_blocks[0].addr;
6462 for (s = d = 0; s < bcnt; s++) {
6463 if (tmp_blocks[s].addr < addr)
6464 continue;
6465 if (d == 0 || tmp_blocks[d-1].addr != tmp_blocks[s].addr)
6466 tmp_blocks[d++] = tmp_blocks[s];
6467 addr = scan_for_ret(tmp_blocks[s].addr);
6468 }
6469
6470 if (o + d > maxcount)
6471 d = maxcount - o;
104df9d3 6472 memcpy(&sblocks[o], tmp_blocks, d * sizeof(sblocks[0]));
03f55e6b 6473 o += d;
6474 }
6475
104df9d3 6476 return o * sizeof(sblocks[0]);
03f55e6b 6477}
6478
6479void new_dynarec_load_blocks(const void *save, int size)
6480{
104df9d3 6481 const struct savestate_block *sblocks = save;
6482 int count = size / sizeof(sblocks[0]);
6483 struct block_info *block;
03f55e6b 6484 u_int regs_save[32];
104df9d3 6485 u_int page;
03f55e6b 6486 uint32_t f;
6487 int i, b;
6488
104df9d3 6489 // restore clean blocks, if any
6490 for (page = 0, b = i = 0; page < ARRAY_SIZE(blocks); page++) {
6491 for (block = blocks[page]; block != NULL; block = block->next, b++) {
6492 if (!block->is_dirty)
6493 continue;
6494 assert(block->source && block->copy);
6495 if (memcmp(block->source, block->copy, block->len))
6496 continue;
6497
6498 // see try_restore_block
6499 block->is_dirty = 0;
6500 mark_invalid_code(block->start, block->len, 0);
6501 i++;
6502 }
6503 }
6504 inv_debug("load_blocks: %d/%d clean blocks\n", i, b);
03f55e6b 6505
6506 // change GPRs for speculation to at least partially work..
6507 memcpy(regs_save, &psxRegs.GPR, sizeof(regs_save));
6508 for (i = 1; i < 32; i++)
6509 psxRegs.GPR.r[i] = 0x80000000;
6510
6511 for (b = 0; b < count; b++) {
104df9d3 6512 for (f = sblocks[b].regflags, i = 0; f; f >>= 1, i++) {
03f55e6b 6513 if (f & 1)
6514 psxRegs.GPR.r[i] = 0x1f800000;
6515 }
6516
104df9d3 6517 ndrc_get_addr_ht(sblocks[b].addr);
03f55e6b 6518
104df9d3 6519 for (f = sblocks[b].regflags, i = 0; f; f >>= 1, i++) {
03f55e6b 6520 if (f & 1)
6521 psxRegs.GPR.r[i] = 0x80000000;
6522 }
6523 }
6524
6525 memcpy(&psxRegs.GPR, regs_save, sizeof(regs_save));
6526}
6527
ece032e6 6528void new_dynarec_print_stats(void)
6529{
6530#ifdef STAT_PRINT
104df9d3 6531 printf("cc %3d,%3d,%3d lu%6d,%3d,%3d c%3d inv%3d,%3d tc_offs %zu b %u,%u\n",
ece032e6 6532 stat_bc_pre, stat_bc_direct, stat_bc_restore,
104df9d3 6533 stat_ht_lookups, stat_jump_in_lookups, stat_restore_tries,
6534 stat_restore_compares, stat_inv_addr_calls, stat_inv_hits,
6535 out - ndrc->translation_cache, stat_blocks, stat_links);
ece032e6 6536 stat_bc_direct = stat_bc_pre = stat_bc_restore =
104df9d3 6537 stat_ht_lookups = stat_jump_in_lookups = stat_restore_tries =
6538 stat_restore_compares = stat_inv_addr_calls = stat_inv_hits = 0;
ece032e6 6539#endif
6540}
6541
de74f599 6542static void force_intcall(int i)
6543{
6544 memset(&dops[i], 0, sizeof(dops[i]));
6545 dops[i].itype = INTCALL;
6546 dops[i].rs1 = CCREG;
6547 dops[i].is_exception = 1;
6548 cinfo[i].ba = -1;
6549}
6550
7f94b097 6551static int apply_hacks(void)
24058131 6552{
6553 int i;
6554 if (HACK_ENABLED(NDHACK_NO_COMPAT_HACKS))
7f94b097 6555 return 0;
24058131 6556 /* special hack(s) */
6557 for (i = 0; i < slen - 4; i++)
6558 {
6559 // lui a4, 0xf200; jal <rcnt_read>; addu a0, 2; slti v0, 28224
6560 if (source[i] == 0x3c04f200 && dops[i+1].itype == UJUMP
6561 && source[i+2] == 0x34840002 && dops[i+3].opcode == 0x0a
277718fa 6562 && cinfo[i+3].imm == 0x6e40 && dops[i+3].rs1 == 2)
24058131 6563 {
6564 SysPrintf("PE2 hack @%08x\n", start + (i+3)*4);
6565 dops[i + 3].itype = NOP;
6566 }
6567 }
6568 i = slen;
6569 if (i > 10 && source[i-1] == 0 && source[i-2] == 0x03e00008
6570 && source[i-4] == 0x8fbf0018 && source[i-6] == 0x00c0f809
6571 && dops[i-7].itype == STORE)
6572 {
6573 i = i-8;
6574 if (dops[i].itype == IMM16)
6575 i--;
6576 // swl r2, 15(r6); swr r2, 12(r6); sw r6, *; jalr r6
6577 if (dops[i].itype == STORELR && dops[i].rs1 == 6
6578 && dops[i-1].itype == STORELR && dops[i-1].rs1 == 6)
6579 {
7f94b097 6580 SysPrintf("F1 hack from %08x, old dst %08x\n", start, hack_addr);
6581 f1_hack = 1;
6582 return 1;
24058131 6583 }
6584 }
de74f599 6585 if (Config.HLE)
6586 {
6587 if (start <= psxRegs.biosBranchCheck && psxRegs.biosBranchCheck < start + i*4)
6588 {
6589 i = (psxRegs.biosBranchCheck - start) / 4u + 23;
6590 if (dops[i].is_jump && !dops[i+1].bt)
6591 {
6592 force_intcall(i);
6593 dops[i+1].is_ds = 0;
6594 }
6595 }
6596 }
7f94b097 6597 return 0;
24058131 6598}
6599
25427adf 6600static int is_ld_use_hazard(const struct decoded_insn *op_ld,
6601 const struct decoded_insn *op)
03f55e6b 6602{
25427adf 6603 if (op_ld->rt1 == 0 || (op_ld->rt1 != op->rs1 && op_ld->rt1 != op->rs2))
6604 return 0;
6605 if (op_ld->itype == LOADLR && op->itype == LOADLR)
6606 return op_ld->rt1 == op_ld->rs1;
6607 return op->itype != CJUMP && op->itype != SJUMP;
de6dbc52 6608}
57871462 6609
de6dbc52 6610static void disassemble_one(int i, u_int src)
6611{
6612 unsigned int type, op, op2, op3;
a22ccd6a 6613 enum ls_width_type ls_type = LS_32;
7ebfcedf 6614 memset(&dops[i], 0, sizeof(dops[i]));
277718fa 6615 memset(&cinfo[i], 0, sizeof(cinfo[i]));
6616 cinfo[i].ba = -1;
6617 cinfo[i].addr = -1;
de6dbc52 6618 dops[i].opcode = op = src >> 26;
277718fa 6619 op2 = 0;
a5cd72d0 6620 type = INTCALL;
6621 set_mnemonic(i, "???");
57871462 6622 switch(op)
6623 {
a5cd72d0 6624 case 0x00: set_mnemonic(i, "special");
de6dbc52 6625 op2 = src & 0x3f;
57871462 6626 switch(op2)
6627 {
53dc27f6 6628 case 0x00: set_mnemonic(i, "SLL"); type=SHIFTIMM; break;
6629 case 0x02: set_mnemonic(i, "SRL"); type=SHIFTIMM; break;
6630 case 0x03: set_mnemonic(i, "SRA"); type=SHIFTIMM; break;
6631 case 0x04: set_mnemonic(i, "SLLV"); type=SHIFT; break;
6632 case 0x06: set_mnemonic(i, "SRLV"); type=SHIFT; break;
6633 case 0x07: set_mnemonic(i, "SRAV"); type=SHIFT; break;
6634 case 0x08: set_mnemonic(i, "JR"); type=RJUMP; break;
6635 case 0x09: set_mnemonic(i, "JALR"); type=RJUMP; break;
6636 case 0x0C: set_mnemonic(i, "SYSCALL"); type=SYSCALL; break;
6637 case 0x0D: set_mnemonic(i, "BREAK"); type=SYSCALL; break;
53dc27f6 6638 case 0x10: set_mnemonic(i, "MFHI"); type=MOV; break;
6639 case 0x11: set_mnemonic(i, "MTHI"); type=MOV; break;
6640 case 0x12: set_mnemonic(i, "MFLO"); type=MOV; break;
6641 case 0x13: set_mnemonic(i, "MTLO"); type=MOV; break;
6642 case 0x18: set_mnemonic(i, "MULT"); type=MULTDIV; break;
6643 case 0x19: set_mnemonic(i, "MULTU"); type=MULTDIV; break;
6644 case 0x1A: set_mnemonic(i, "DIV"); type=MULTDIV; break;
6645 case 0x1B: set_mnemonic(i, "DIVU"); type=MULTDIV; break;
6646 case 0x20: set_mnemonic(i, "ADD"); type=ALU; break;
6647 case 0x21: set_mnemonic(i, "ADDU"); type=ALU; break;
6648 case 0x22: set_mnemonic(i, "SUB"); type=ALU; break;
6649 case 0x23: set_mnemonic(i, "SUBU"); type=ALU; break;
6650 case 0x24: set_mnemonic(i, "AND"); type=ALU; break;
6651 case 0x25: set_mnemonic(i, "OR"); type=ALU; break;
6652 case 0x26: set_mnemonic(i, "XOR"); type=ALU; break;
6653 case 0x27: set_mnemonic(i, "NOR"); type=ALU; break;
6654 case 0x2A: set_mnemonic(i, "SLT"); type=ALU; break;
6655 case 0x2B: set_mnemonic(i, "SLTU"); type=ALU; break;
57871462 6656 }
6657 break;
a5cd72d0 6658 case 0x01: set_mnemonic(i, "regimm");
6659 type = SJUMP;
de6dbc52 6660 op2 = (src >> 16) & 0x1f;
57871462 6661 switch(op2)
6662 {
a5cd72d0 6663 case 0x10: set_mnemonic(i, "BLTZAL"); break;
6664 case 0x11: set_mnemonic(i, "BGEZAL"); break;
6665 default:
6666 if (op2 & 1)
6667 set_mnemonic(i, "BGEZ");
6668 else
6669 set_mnemonic(i, "BLTZ");
57871462 6670 }
6671 break;
53dc27f6 6672 case 0x02: set_mnemonic(i, "J"); type=UJUMP; break;
6673 case 0x03: set_mnemonic(i, "JAL"); type=UJUMP; break;
6674 case 0x04: set_mnemonic(i, "BEQ"); type=CJUMP; break;
6675 case 0x05: set_mnemonic(i, "BNE"); type=CJUMP; break;
6676 case 0x06: set_mnemonic(i, "BLEZ"); type=CJUMP; break;
6677 case 0x07: set_mnemonic(i, "BGTZ"); type=CJUMP; break;
6678 case 0x08: set_mnemonic(i, "ADDI"); type=IMM16; break;
6679 case 0x09: set_mnemonic(i, "ADDIU"); type=IMM16; break;
6680 case 0x0A: set_mnemonic(i, "SLTI"); type=IMM16; break;
6681 case 0x0B: set_mnemonic(i, "SLTIU"); type=IMM16; break;
6682 case 0x0C: set_mnemonic(i, "ANDI"); type=IMM16; break;
6683 case 0x0D: set_mnemonic(i, "ORI"); type=IMM16; break;
6684 case 0x0E: set_mnemonic(i, "XORI"); type=IMM16; break;
6685 case 0x0F: set_mnemonic(i, "LUI"); type=IMM16; break;
a5cd72d0 6686 case 0x10: set_mnemonic(i, "COP0");
de6dbc52 6687 op2 = (src >> 21) & 0x1f;
a5cd72d0 6688 if (op2 & 0x10) {
de6dbc52 6689 op3 = src & 0x1f;
a5cd72d0 6690 switch (op3)
6691 {
6692 case 0x01: case 0x02: case 0x06: case 0x08: type = INTCALL; break;
6693 case 0x10: set_mnemonic(i, "RFE"); type=RFE; break;
6694 default: type = OTHER; break;
6695 }
6696 break;
6697 }
57871462 6698 switch(op2)
6699 {
a5cd72d0 6700 u32 rd;
6701 case 0x00:
6702 set_mnemonic(i, "MFC0");
de6dbc52 6703 rd = (src >> 11) & 0x1F;
a5cd72d0 6704 if (!(0x00000417u & (1u << rd)))
6705 type = COP0;
6706 break;
53dc27f6 6707 case 0x04: set_mnemonic(i, "MTC0"); type=COP0; break;
a5cd72d0 6708 case 0x02:
6709 case 0x06: type = INTCALL; break;
6710 default: type = OTHER; break;
57871462 6711 }
6712 break;
a5cd72d0 6713 case 0x11: set_mnemonic(i, "COP1");
de6dbc52 6714 op2 = (src >> 21) & 0x1f;
57871462 6715 break;
a5cd72d0 6716 case 0x12: set_mnemonic(i, "COP2");
de6dbc52 6717 op2 = (src >> 21) & 0x1f;
a5cd72d0 6718 if (op2 & 0x10) {
6719 type = OTHER;
de6dbc52 6720 if (gte_handlers[src & 0x3f] != NULL) {
53dc27f6 6721#ifdef DISASM
de6dbc52 6722 if (gte_regnames[src & 0x3f] != NULL)
6723 strcpy(insn[i], gte_regnames[src & 0x3f]);
bedfea38 6724 else
de6dbc52 6725 snprintf(insn[i], sizeof(insn[i]), "COP2 %x", src & 0x3f);
53dc27f6 6726#endif
a5cd72d0 6727 type = C2OP;
c7abc864 6728 }
6729 }
6730 else switch(op2)
b9b61529 6731 {
53dc27f6 6732 case 0x00: set_mnemonic(i, "MFC2"); type=COP2; break;
6733 case 0x02: set_mnemonic(i, "CFC2"); type=COP2; break;
6734 case 0x04: set_mnemonic(i, "MTC2"); type=COP2; break;
6735 case 0x06: set_mnemonic(i, "CTC2"); type=COP2; break;
b9b61529 6736 }
6737 break;
a5cd72d0 6738 case 0x13: set_mnemonic(i, "COP3");
de6dbc52 6739 op2 = (src >> 21) & 0x1f;
a5cd72d0 6740 break;
f9e9616e 6741 case 0x20: set_mnemonic(i, "LB"); type=LOAD; ls_type = LS_8; break;
6742 case 0x21: set_mnemonic(i, "LH"); type=LOAD; ls_type = LS_16; break;
6743 case 0x22: set_mnemonic(i, "LWL"); type=LOADLR; ls_type = LS_LR; break;
6744 case 0x23: set_mnemonic(i, "LW"); type=LOAD; ls_type = LS_32; break;
6745 case 0x24: set_mnemonic(i, "LBU"); type=LOAD; ls_type = LS_8; break;
6746 case 0x25: set_mnemonic(i, "LHU"); type=LOAD; ls_type = LS_16; break;
6747 case 0x26: set_mnemonic(i, "LWR"); type=LOADLR; ls_type = LS_LR; break;
6748 case 0x28: set_mnemonic(i, "SB"); type=STORE; ls_type = LS_8; break;
6749 case 0x29: set_mnemonic(i, "SH"); type=STORE; ls_type = LS_16; break;
6750 case 0x2A: set_mnemonic(i, "SWL"); type=STORELR; ls_type = LS_LR; break;
6751 case 0x2B: set_mnemonic(i, "SW"); type=STORE; ls_type = LS_32; break;
6752 case 0x2E: set_mnemonic(i, "SWR"); type=STORELR; ls_type = LS_LR; break;
6753 case 0x32: set_mnemonic(i, "LWC2"); type=C2LS; ls_type = LS_32; break;
6754 case 0x3A: set_mnemonic(i, "SWC2"); type=C2LS; ls_type = LS_32; break;
a5cd72d0 6755 case 0x3B:
de6dbc52 6756 if (Config.HLE && (src & 0x03ffffff) < ARRAY_SIZE(psxHLEt)) {
a5cd72d0 6757 set_mnemonic(i, "HLECALL");
6758 type = HLECALL;
6759 }
6760 break;
6761 default:
90ae6d4e 6762 break;
57871462 6763 }
a5cd72d0 6764 if (type == INTCALL)
de6dbc52 6765 SysPrintf("NI %08x @%08x (%08x)\n", src, start + i*4, start);
f9e9616e 6766 dops[i].itype = type;
6767 dops[i].opcode2 = op2;
6768 dops[i].ls_type = ls_type;
57871462 6769 /* Get registers/immediates */
53dc27f6 6770 dops[i].use_lt1=0;
bedfea38 6771 gte_rs[i]=gte_rt[i]=0;
a5cd72d0 6772 dops[i].rs1 = 0;
6773 dops[i].rs2 = 0;
6774 dops[i].rt1 = 0;
6775 dops[i].rt2 = 0;
57871462 6776 switch(type) {
6777 case LOAD:
de6dbc52 6778 dops[i].rs1 = (src >> 21) & 0x1f;
6779 dops[i].rt1 = (src >> 16) & 0x1f;
6780 cinfo[i].imm = (short)src;
57871462 6781 break;
6782 case STORE:
6783 case STORELR:
de6dbc52 6784 dops[i].rs1 = (src >> 21) & 0x1f;
6785 dops[i].rs2 = (src >> 16) & 0x1f;
6786 cinfo[i].imm = (short)src;
57871462 6787 break;
6788 case LOADLR:
6789 // LWL/LWR only load part of the register,
6790 // therefore the target register must be treated as a source too
de6dbc52 6791 dops[i].rs1 = (src >> 21) & 0x1f;
6792 dops[i].rs2 = (src >> 16) & 0x1f;
6793 dops[i].rt1 = (src >> 16) & 0x1f;
6794 cinfo[i].imm = (short)src;
57871462 6795 break;
6796 case IMM16:
cf95b4f0 6797 if (op==0x0f) dops[i].rs1=0; // LUI instruction has no source register
de6dbc52 6798 else dops[i].rs1 = (src >> 21) & 0x1f;
6799 dops[i].rs2 = 0;
6800 dops[i].rt1 = (src >> 16) & 0x1f;
57871462 6801 if(op>=0x0c&&op<=0x0e) { // ANDI/ORI/XORI
de6dbc52 6802 cinfo[i].imm = (unsigned short)src;
57871462 6803 }else{
de6dbc52 6804 cinfo[i].imm = (short)src;
57871462 6805 }
57871462 6806 break;
6807 case UJUMP:
57871462 6808 // The JAL instruction writes to r31.
6809 if (op&1) {
cf95b4f0 6810 dops[i].rt1=31;
57871462 6811 }
cf95b4f0 6812 dops[i].rs2=CCREG;
57871462 6813 break;
6814 case RJUMP:
de6dbc52 6815 dops[i].rs1 = (src >> 21) & 0x1f;
5067f341 6816 // The JALR instruction writes to rd.
57871462 6817 if (op2&1) {
de6dbc52 6818 dops[i].rt1 = (src >> 11) & 0x1f;
57871462 6819 }
cf95b4f0 6820 dops[i].rs2=CCREG;
57871462 6821 break;
6822 case CJUMP:
de6dbc52 6823 dops[i].rs1 = (src >> 21) & 0x1f;
6824 dops[i].rs2 = (src >> 16) & 0x1f;
57871462 6825 if(op&2) { // BGTZ/BLEZ
cf95b4f0 6826 dops[i].rs2=0;
57871462 6827 }
57871462 6828 break;
6829 case SJUMP:
de6dbc52 6830 dops[i].rs1 = (src >> 21) & 0x1f;
6831 dops[i].rs2 = CCREG;
a5cd72d0 6832 if (op2 == 0x10 || op2 == 0x11) { // BxxAL
6833 dops[i].rt1 = 31;
57871462 6834 // NOTE: If the branch is not taken, r31 is still overwritten
6835 }
57871462 6836 break;
57871462 6837 case ALU:
de6dbc52 6838 dops[i].rs1=(src>>21)&0x1f; // source
6839 dops[i].rs2=(src>>16)&0x1f; // subtract amount
6840 dops[i].rt1=(src>>11)&0x1f; // destination
57871462 6841 break;
6842 case MULTDIV:
de6dbc52 6843 dops[i].rs1=(src>>21)&0x1f; // source
6844 dops[i].rs2=(src>>16)&0x1f; // divisor
cf95b4f0 6845 dops[i].rt1=HIREG;
6846 dops[i].rt2=LOREG;
57871462 6847 break;
6848 case MOV:
cf95b4f0 6849 if(op2==0x10) dops[i].rs1=HIREG; // MFHI
6850 if(op2==0x11) dops[i].rt1=HIREG; // MTHI
6851 if(op2==0x12) dops[i].rs1=LOREG; // MFLO
6852 if(op2==0x13) dops[i].rt1=LOREG; // MTLO
de6dbc52 6853 if((op2&0x1d)==0x10) dops[i].rt1=(src>>11)&0x1f; // MFxx
6854 if((op2&0x1d)==0x11) dops[i].rs1=(src>>21)&0x1f; // MTxx
57871462 6855 break;
6856 case SHIFT:
de6dbc52 6857 dops[i].rs1=(src>>16)&0x1f; // target of shift
6858 dops[i].rs2=(src>>21)&0x1f; // shift amount
6859 dops[i].rt1=(src>>11)&0x1f; // destination
57871462 6860 break;
6861 case SHIFTIMM:
de6dbc52 6862 dops[i].rs1=(src>>16)&0x1f;
cf95b4f0 6863 dops[i].rs2=0;
de6dbc52 6864 dops[i].rt1=(src>>11)&0x1f;
6865 cinfo[i].imm=(src>>6)&0x1f;
57871462 6866 break;
6867 case COP0:
de6dbc52 6868 if(op2==0) dops[i].rt1=(src>>16)&0x1F; // MFC0
6869 if(op2==4) dops[i].rs1=(src>>16)&0x1F; // MTC0
6870 if(op2==4&&((src>>11)&0x1e)==12) dops[i].rs2=CCREG;
57871462 6871 break;
bedfea38 6872 case COP2:
de6dbc52 6873 if(op2<3) dops[i].rt1=(src>>16)&0x1F; // MFC2/CFC2
6874 if(op2>3) dops[i].rs1=(src>>16)&0x1F; // MTC2/CTC2
6875 int gr=(src>>11)&0x1F;
bedfea38 6876 switch(op2)
6877 {
6878 case 0x00: gte_rs[i]=1ll<<gr; break; // MFC2
6879 case 0x04: gte_rt[i]=1ll<<gr; break; // MTC2
0ff8c62c 6880 case 0x02: gte_rs[i]=1ll<<(gr+32); break; // CFC2
bedfea38 6881 case 0x06: gte_rt[i]=1ll<<(gr+32); break; // CTC2
6882 }
6883 break;
b9b61529 6884 case C2LS:
de6dbc52 6885 dops[i].rs1=(src>>21)&0x1F;
6886 cinfo[i].imm=(short)src;
6887 if(op==0x32) gte_rt[i]=1ll<<((src>>16)&0x1F); // LWC2
6888 else gte_rs[i]=1ll<<((src>>16)&0x1F); // SWC2
bedfea38 6889 break;
6890 case C2OP:
de6dbc52 6891 gte_rs[i]=gte_reg_reads[src&0x3f];
6892 gte_rt[i]=gte_reg_writes[src&0x3f];
2167bef6 6893 gte_rt[i]|=1ll<<63; // every op changes flags
de6dbc52 6894 if((src&0x3f)==GTE_MVMVA) {
6895 int v = (src >> 15) & 3;
587a5b1c 6896 gte_rs[i]&=~0xe3fll;
6897 if(v==3) gte_rs[i]|=0xe00ll;
6898 else gte_rs[i]|=3ll<<(v*2);
6899 }
b9b61529 6900 break;
57871462 6901 case SYSCALL:
7139f3c8 6902 case HLECALL:
1e973cb0 6903 case INTCALL:
cf95b4f0 6904 dops[i].rs1=CCREG;
57871462 6905 break;
6906 default:
a5cd72d0 6907 break;
57871462 6908 }
de6dbc52 6909}
6910
6911static noinline void pass1_disassemble(u_int pagelimit)
6912{
6913 int i, j, done = 0, ni_count = 0;
f9e9616e 6914 int ds_next = 0;
de6dbc52 6915
6916 for (i = 0; !done; i++)
6917 {
6918 int force_j_to_interpreter = 0;
6919 unsigned int type, op, op2;
6920
6921 disassemble_one(i, source[i]);
f9e9616e 6922 dops[i].is_ds = ds_next; ds_next = 0;
de6dbc52 6923 type = dops[i].itype;
6924 op = dops[i].opcode;
6925 op2 = dops[i].opcode2;
6926
57871462 6927 /* Calculate branch target addresses */
6928 if(type==UJUMP)
277718fa 6929 cinfo[i].ba=((start+i*4+4)&0xF0000000)|(((unsigned int)source[i]<<6)>>4);
cf95b4f0 6930 else if(type==CJUMP&&dops[i].rs1==dops[i].rs2&&(op&1))
277718fa 6931 cinfo[i].ba=start+i*4+8; // Ignore never taken branch
cf95b4f0 6932 else if(type==SJUMP&&dops[i].rs1==0&&!(op2&1))
277718fa 6933 cinfo[i].ba=start+i*4+8; // Ignore never taken branch
ad49de89 6934 else if(type==CJUMP||type==SJUMP)
277718fa 6935 cinfo[i].ba=start+i*4+4+((signed int)((unsigned int)source[i]<<16)>>14);
4919de1e 6936
6937 /* simplify always (not)taken branches */
cf95b4f0 6938 if (type == CJUMP && dops[i].rs1 == dops[i].rs2) {
6939 dops[i].rs1 = dops[i].rs2 = 0;
4919de1e 6940 if (!(op & 1)) {
cf95b4f0 6941 dops[i].itype = type = UJUMP;
6942 dops[i].rs2 = CCREG;
4919de1e 6943 }
6944 }
cf95b4f0 6945 else if (type == SJUMP && dops[i].rs1 == 0 && (op2 & 1))
6946 dops[i].itype = type = UJUMP;
4919de1e 6947
277718fa 6948 dops[i].is_jump = type == RJUMP || type == UJUMP || type == CJUMP || type == SJUMP;
6949 dops[i].is_ujump = type == RJUMP || type == UJUMP;
6950 dops[i].is_load = type == LOAD || type == LOADLR || op == 0x32; // LWC2
a5cd72d0 6951 dops[i].is_delay_load = (dops[i].is_load || (source[i] & 0xf3d00000) == 0x40000000); // MFC/CFC
277718fa 6952 dops[i].is_store = type == STORE || type == STORELR || op == 0x3a; // SWC2
6953 dops[i].is_exception = type == SYSCALL || type == HLECALL || type == INTCALL;
6954 dops[i].may_except = dops[i].is_exception || (type == ALU && (op2 == 0x20 || op2 == 0x22)) || op == 8;
f9e9616e 6955 ds_next = dops[i].is_jump;
277718fa 6956
6957 if (((op & 0x37) == 0x21 || op == 0x25) // LH/SH/LHU
6958 && ((cinfo[i].imm & 1) || Config.PreciseExceptions))
6959 dops[i].may_except = 1;
6960 if (((op & 0x37) == 0x23 || (op & 0x37) == 0x32) // LW/SW/LWC2/SWC2
6961 && ((cinfo[i].imm & 3) || Config.PreciseExceptions))
6962 dops[i].may_except = 1;
fe807a8a 6963
a5cd72d0 6964 /* rare messy cases to just pass over to the interpreter */
fe807a8a 6965 if (i > 0 && dops[i-1].is_jump) {
ecca05e3 6966 j = i - 1;
3e535354 6967 // branch in delay slot?
fe807a8a 6968 if (dops[i].is_jump) {
3e535354 6969 // don't handle first branch and call interpreter if it's hit
a5cd72d0 6970 SysPrintf("branch in DS @%08x (%08x)\n", start + i*4, start);
ecca05e3 6971 force_j_to_interpreter = 1;
3e535354 6972 }
de6dbc52 6973 // load delay detection through a branch
a5cd72d0 6974 else if (dops[i].is_delay_load && dops[i].rt1 != 0) {
de6dbc52 6975 const struct decoded_insn *dop = NULL;
6976 int t = -1;
6977 if (cinfo[i-1].ba != -1) {
6978 t = (cinfo[i-1].ba - start) / 4;
6979 if (t < 0 || t > i) {
6980 u_int limit = 0;
6981 u_int *mem = get_source_start(cinfo[i-1].ba, &limit);
6982 if (mem != NULL) {
6983 disassemble_one(MAXBLOCK - 1, mem[0]);
6984 dop = &dops[MAXBLOCK - 1];
6985 }
6986 }
6987 else
6988 dop = &dops[t];
6989 }
25427adf 6990 if ((dop && is_ld_use_hazard(&dops[i], dop))
de6dbc52 6991 || (!dop && Config.PreciseExceptions)) {
3e535354 6992 // jump target wants DS result - potential load delay effect
a5cd72d0 6993 SysPrintf("load delay in DS @%08x (%08x)\n", start + i*4, start);
ecca05e3 6994 force_j_to_interpreter = 1;
de6dbc52 6995 if (0 <= t && t < i)
6996 dops[t + 1].bt = 1; // expected return from interpreter
3e535354 6997 }
cf95b4f0 6998 else if(i>=2&&dops[i-2].rt1==2&&dops[i].rt1==2&&dops[i].rs1!=2&&dops[i].rs2!=2&&dops[i-1].rs1!=2&&dops[i-1].rs2!=2&&
fe807a8a 6999 !(i>=3&&dops[i-3].is_jump)) {
3e535354 7000 // v0 overwrite like this is a sign of trouble, bail out
4149788d 7001 SysPrintf("v0 overwrite @%08x (%08x)\n", start + i*4, start);
ecca05e3 7002 force_j_to_interpreter = 1;
3e535354 7003 }
7004 }
a5cd72d0 7005 }
de6dbc52 7006 else if (i > 0 && dops[i-1].is_delay_load
25427adf 7007 && is_ld_use_hazard(&dops[i-1], &dops[i])
de6dbc52 7008 && (i < 2 || !dops[i-2].is_ujump)) {
a5cd72d0 7009 SysPrintf("load delay @%08x (%08x)\n", start + i*4, start);
ecca05e3 7010 for (j = i - 1; j > 0 && dops[j-1].is_delay_load; j--)
7011 if (dops[j-1].rt1 != dops[i-1].rt1)
7012 break;
7013 force_j_to_interpreter = 1;
a5cd72d0 7014 }
ecca05e3 7015 if (force_j_to_interpreter) {
de6dbc52 7016 force_intcall(j);
a5cd72d0 7017 done = 2;
ecca05e3 7018 i = j; // don't compile the problematic branch/load/etc
3e535354 7019 }
de6dbc52 7020 if (dops[i].is_exception && i > 0 && dops[i-1].is_jump) {
7021 SysPrintf("exception in DS @%08x (%08x)\n", start + i*4, start);
7022 i--;
7023 force_intcall(i);
7024 done = 2;
7025 }
7026 if (i >= 2 && (source[i-2] & 0xffe0f800) == 0x40806000) // MTC0 $12
7027 dops[i].bt = 1;
7028 if (i >= 1 && (source[i-1] & 0xffe0f800) == 0x40806800) // MTC0 $13
7029 dops[i].bt = 1;
4919de1e 7030
3e535354 7031 /* Is this the end of the block? */
fe807a8a 7032 if (i > 0 && dops[i-1].is_ujump) {
0787af86 7033 if (dops[i-1].rt1 == 0) { // not jal
277718fa 7034 int found_bbranch = 0, t = (cinfo[i-1].ba - start) / 4;
0787af86 7035 if ((u_int)(t - i) < 64 && start + (t+64)*4 < pagelimit) {
7036 // scan for a branch back to i+1
7037 for (j = t; j < t + 64; j++) {
7038 int tmpop = source[j] >> 26;
7039 if (tmpop == 1 || ((tmpop & ~3) == 4)) {
7040 int t2 = j + 1 + (int)(signed short)source[j];
7041 if (t2 == i + 1) {
7042 //printf("blk expand %08x<-%08x\n", start + (i+1)*4, start + j*4);
7043 found_bbranch = 1;
7044 break;
7045 }
7046 }
7047 }
7048 }
7049 if (!found_bbranch)
7050 done = 2;
57871462 7051 }
7052 else {
7053 if(stop_after_jal) done=1;
7054 // Stop on BREAK
7055 if((source[i+1]&0xfc00003f)==0x0d) done=1;
7056 }
7057 // Don't recompile stuff that's already compiled
7058 if(check_addr(start+i*4+4)) done=1;
7059 // Don't get too close to the limit
d3201e39 7060 if (i > MAXBLOCK - 64)
7061 done = 1;
57871462 7062 }
a5cd72d0 7063 if (dops[i].itype == HLECALL)
dc4fa8bc 7064 done = 1;
a5cd72d0 7065 else if (dops[i].itype == INTCALL)
dc4fa8bc 7066 done = 2;
a5cd72d0 7067 else if (dops[i].is_exception)
d1150cd6 7068 done = stop_after_jal ? 1 : 2;
7069 if (done == 2) {
1e973cb0 7070 // Does the block continue due to a branch?
7071 for(j=i-1;j>=0;j--)
7072 {
277718fa 7073 if(cinfo[j].ba==start+i*4) done=j=0; // Branch into delay slot
7074 if(cinfo[j].ba==start+i*4+4) done=j=0;
7075 if(cinfo[j].ba==start+i*4+8) done=j=0;
1e973cb0 7076 }
7077 }
75dec299 7078 //assert(i<MAXBLOCK-1);
57871462 7079 if(start+i*4==pagelimit-4) done=1;
7080 assert(start+i*4<pagelimit);
d3201e39 7081 if (i == MAXBLOCK - 2)
7082 done = 1;
57871462 7083 // Stop if we're compiling junk
a5cd72d0 7084 if (dops[i].itype == INTCALL && (++ni_count > 8 || dops[i].opcode == 0x11)) {
57871462 7085 done=stop_after_jal=1;
c43b5311 7086 SysPrintf("Disabled speculative precompilation\n");
57871462 7087 }
7088 }
4bdc30ab 7089 while (i > 0 && dops[i-1].is_jump)
7090 i--;
7091 assert(i > 0);
7092 assert(!dops[i-1].is_jump);
7093 slen = i;
4149788d 7094}
7095
7096// Basic liveness analysis for MIPS registers
7097static noinline void pass2_unneeded_regs(int istart,int iend,int r)
7098{
7099 int i;
7100 uint64_t u,gte_u,b,gte_b;
7101 uint64_t temp_u,temp_gte_u=0;
7102 uint64_t gte_u_unknown=0;
7103 if (HACK_ENABLED(NDHACK_GTE_UNNEEDED))
7104 gte_u_unknown=~0ll;
7105 if(iend==slen-1) {
7106 u=1;
7107 gte_u=gte_u_unknown;
7108 }else{
7109 //u=unneeded_reg[iend+1];
7110 u=1;
7111 gte_u=gte_unneeded[iend+1];
7112 }
7113
7114 for (i=iend;i>=istart;i--)
7115 {
7116 //printf("unneeded registers i=%d (%d,%d) r=%d\n",i,istart,iend,r);
7117 if(dops[i].is_jump)
7118 {
7119 // If subroutine call, flag return address as a possible branch target
7120 if(dops[i].rt1==31 && i<slen-2) dops[i+2].bt=1;
7121
277718fa 7122 if(cinfo[i].ba<start || cinfo[i].ba>=(start+slen*4))
4149788d 7123 {
7124 // Branch out of this block, flush all regs
7125 u=1;
7126 gte_u=gte_u_unknown;
7127 branch_unneeded_reg[i]=u;
7128 // Merge in delay slot
7129 u|=(1LL<<dops[i+1].rt1)|(1LL<<dops[i+1].rt2);
7130 u&=~((1LL<<dops[i+1].rs1)|(1LL<<dops[i+1].rs2));
7131 u|=1;
7132 gte_u|=gte_rt[i+1];
7133 gte_u&=~gte_rs[i+1];
7134 }
7135 else
7136 {
7137 // Internal branch, flag target
277718fa 7138 dops[(cinfo[i].ba-start)>>2].bt=1;
7139 if(cinfo[i].ba<=start+i*4) {
4149788d 7140 // Backward branch
7141 if(dops[i].is_ujump)
7142 {
7143 // Unconditional branch
7144 temp_u=1;
7145 temp_gte_u=0;
7146 } else {
7147 // Conditional branch (not taken case)
7148 temp_u=unneeded_reg[i+2];
7149 temp_gte_u&=gte_unneeded[i+2];
7150 }
7151 // Merge in delay slot
7152 temp_u|=(1LL<<dops[i+1].rt1)|(1LL<<dops[i+1].rt2);
7153 temp_u&=~((1LL<<dops[i+1].rs1)|(1LL<<dops[i+1].rs2));
7154 temp_u|=1;
7155 temp_gte_u|=gte_rt[i+1];
7156 temp_gte_u&=~gte_rs[i+1];
7157 temp_u|=(1LL<<dops[i].rt1)|(1LL<<dops[i].rt2);
7158 temp_u&=~((1LL<<dops[i].rs1)|(1LL<<dops[i].rs2));
7159 temp_u|=1;
7160 temp_gte_u|=gte_rt[i];
7161 temp_gte_u&=~gte_rs[i];
7162 unneeded_reg[i]=temp_u;
7163 gte_unneeded[i]=temp_gte_u;
7164 // Only go three levels deep. This recursion can take an
7165 // excessive amount of time if there are a lot of nested loops.
7166 if(r<2) {
277718fa 7167 pass2_unneeded_regs((cinfo[i].ba-start)>>2,i-1,r+1);
4149788d 7168 }else{
277718fa 7169 unneeded_reg[(cinfo[i].ba-start)>>2]=1;
7170 gte_unneeded[(cinfo[i].ba-start)>>2]=gte_u_unknown;
4149788d 7171 }
7172 } /*else*/ if(1) {
7173 if (dops[i].is_ujump)
7174 {
7175 // Unconditional branch
277718fa 7176 u=unneeded_reg[(cinfo[i].ba-start)>>2];
7177 gte_u=gte_unneeded[(cinfo[i].ba-start)>>2];
4149788d 7178 branch_unneeded_reg[i]=u;
7179 // Merge in delay slot
7180 u|=(1LL<<dops[i+1].rt1)|(1LL<<dops[i+1].rt2);
7181 u&=~((1LL<<dops[i+1].rs1)|(1LL<<dops[i+1].rs2));
7182 u|=1;
7183 gte_u|=gte_rt[i+1];
7184 gte_u&=~gte_rs[i+1];
7185 } else {
7186 // Conditional branch
277718fa 7187 b=unneeded_reg[(cinfo[i].ba-start)>>2];
7188 gte_b=gte_unneeded[(cinfo[i].ba-start)>>2];
4149788d 7189 branch_unneeded_reg[i]=b;
7190 // Branch delay slot
7191 b|=(1LL<<dops[i+1].rt1)|(1LL<<dops[i+1].rt2);
7192 b&=~((1LL<<dops[i+1].rs1)|(1LL<<dops[i+1].rs2));
7193 b|=1;
7194 gte_b|=gte_rt[i+1];
7195 gte_b&=~gte_rs[i+1];
7196 u&=b;
7197 gte_u&=gte_b;
7198 if(i<slen-1) {
7199 branch_unneeded_reg[i]&=unneeded_reg[i+2];
7200 } else {
7201 branch_unneeded_reg[i]=1;
7202 }
7203 }
7204 }
7205 }
7206 }
4149788d 7207 //u=1; // DEBUG
7208 // Written registers are unneeded
7209 u|=1LL<<dops[i].rt1;
7210 u|=1LL<<dops[i].rt2;
7211 gte_u|=gte_rt[i];
7212 // Accessed registers are needed
7213 u&=~(1LL<<dops[i].rs1);
7214 u&=~(1LL<<dops[i].rs2);
7215 gte_u&=~gte_rs[i];
7216 if(gte_rs[i]&&dops[i].rt1&&(unneeded_reg[i+1]&(1ll<<dops[i].rt1)))
7217 gte_u|=gte_rs[i]&gte_unneeded[i+1]; // MFC2/CFC2 to dead register, unneeded
90f98e7c 7218 if (dops[i].may_except || dops[i].itype == RFE)
7219 {
7220 // SYSCALL instruction, etc or conditional exception
7221 u=1;
7222 }
4149788d 7223 // Source-target dependencies
7224 // R0 is always unneeded
7225 u|=1;
7226 // Save it
7227 unneeded_reg[i]=u;
7228 gte_unneeded[i]=gte_u;
7229 /*
7230 printf("ur (%d,%d) %x: ",istart,iend,start+i*4);
7231 printf("U:");
7232 int r;
7233 for(r=1;r<=CCREG;r++) {
7234 if((unneeded_reg[i]>>r)&1) {
7235 if(r==HIREG) printf(" HI");
7236 else if(r==LOREG) printf(" LO");
7237 else printf(" r%d",r);
7238 }
7239 }
7240 printf("\n");
7241 */
7242 }
7243}
57871462 7244
f9e9616e 7245static noinline void pass2a_unneeded_other(void)
7246{
7247 int i, j;
7248 for (i = 0; i < slen; i++)
7249 {
7250 // remove redundant alignment checks
7251 if (dops[i].may_except && (dops[i].is_load || dops[i].is_store)
7252 && dops[i].rt1 != dops[i].rs1 && !dops[i].is_ds)
7253 {
7254 int base = dops[i].rs1, lsb = cinfo[i].imm, ls_type = dops[i].ls_type;
7255 int mask = ls_type == LS_32 ? 3 : 1;
7256 lsb &= mask;
7257 for (j = i + 1; j < slen; j++) {
7258 if (dops[j].bt || dops[j].is_jump)
7259 break;
7260 if ((dops[j].is_load || dops[j].is_store) && dops[j].rs1 == base
7261 && dops[j].ls_type == ls_type && (cinfo[j].imm & mask) == lsb)
7262 dops[j].may_except = 0;
7263 if (dops[j].rt1 == base)
7264 break;
7265 }
7266 }
7267 }
7268}
7269
4149788d 7270static noinline void pass3_register_alloc(u_int addr)
7271{
57871462 7272 struct regstat current; // Current register allocations/status
6cc8d23c 7273 clear_all_regs(current.regmap_entry);
57871462 7274 clear_all_regs(current.regmap);
6cc8d23c 7275 current.wasdirty = current.dirty = 0;
7276 current.u = unneeded_reg[0];
7277 alloc_reg(&current, 0, CCREG);
7278 dirty_reg(&current, CCREG);
7279 current.wasconst = 0;
7280 current.isconst = 0;
7281 current.loadedconst = 0;
90f98e7c 7282 current.noevict = 0;
9b495f6e 7283 //current.waswritten = 0;
57871462 7284 int ds=0;
7285 int cc=0;
4149788d 7286 int hr;
7287 int i, j;
6ebf4adf 7288
4149788d 7289 if (addr & 1) {
57871462 7290 // First instruction is delay slot
7291 cc=-1;
cf95b4f0 7292 dops[1].bt=1;
57871462 7293 ds=1;
7294 unneeded_reg[0]=1;
57871462 7295 }
9f51b4b9 7296
57871462 7297 for(i=0;i<slen;i++)
7298 {
cf95b4f0 7299 if(dops[i].bt)
57871462 7300 {
57871462 7301 for(hr=0;hr<HOST_REGS;hr++)
7302 {
7303 // Is this really necessary?
7304 if(current.regmap[hr]==0) current.regmap[hr]=-1;
7305 }
7306 current.isconst=0;
9b495f6e 7307 //current.waswritten=0;
57871462 7308 }
24385cae 7309
57871462 7310 memcpy(regmap_pre[i],current.regmap,sizeof(current.regmap));
7311 regs[i].wasconst=current.isconst;
57871462 7312 regs[i].wasdirty=current.dirty;
6cc8d23c 7313 regs[i].dirty=0;
7314 regs[i].u=0;
7315 regs[i].isconst=0;
8575a877 7316 regs[i].loadedconst=0;
fe807a8a 7317 if (!dops[i].is_jump) {
57871462 7318 if(i+1<slen) {
cf95b4f0 7319 current.u=unneeded_reg[i+1]&~((1LL<<dops[i].rs1)|(1LL<<dops[i].rs2));
57871462 7320 current.u|=1;
57871462 7321 } else {
7322 current.u=1;
57871462 7323 }
7324 } else {
7325 if(i+1<slen) {
cf95b4f0 7326 current.u=branch_unneeded_reg[i]&~((1LL<<dops[i+1].rs1)|(1LL<<dops[i+1].rs2));
7327 current.u&=~((1LL<<dops[i].rs1)|(1LL<<dops[i].rs2));
57871462 7328 current.u|=1;
7ebfcedf 7329 } else {
7330 SysPrintf("oops, branch at end of block with no delay slot @%08x\n", start + i*4);
7331 abort();
7332 }
57871462 7333 }
f9e9616e 7334 assert(dops[i].is_ds == ds);
57871462 7335 if(ds) {
7336 ds=0; // Skip delay slot, already allocated as part of branch
7337 // ...but we need to alloc it in case something jumps here
7338 if(i+1<slen) {
7339 current.u=branch_unneeded_reg[i-1]&unneeded_reg[i+1];
57871462 7340 }else{
7341 current.u=branch_unneeded_reg[i-1];
57871462 7342 }
cf95b4f0 7343 current.u&=~((1LL<<dops[i].rs1)|(1LL<<dops[i].rs2));
57871462 7344 current.u|=1;
57871462 7345 struct regstat temp;
7346 memcpy(&temp,&current,sizeof(current));
7347 temp.wasdirty=temp.dirty;
57871462 7348 // TODO: Take into account unconditional branches, as below
7349 delayslot_alloc(&temp,i);
7350 memcpy(regs[i].regmap,temp.regmap,sizeof(temp.regmap));
7351 regs[i].wasdirty=temp.wasdirty;
57871462 7352 regs[i].dirty=temp.dirty;
57871462 7353 regs[i].isconst=0;
7354 regs[i].wasconst=0;
7355 current.isconst=0;
7356 // Create entry (branch target) regmap
7357 for(hr=0;hr<HOST_REGS;hr++)
7358 {
7359 int r=temp.regmap[hr];
7360 if(r>=0) {
7361 if(r!=regmap_pre[i][hr]) {
7362 regs[i].regmap_entry[hr]=-1;
7363 }
7364 else
7365 {
7c3a5182 7366 assert(r < 64);
57871462 7367 if((current.u>>r)&1) {
7368 regs[i].regmap_entry[hr]=-1;
7369 regs[i].regmap[hr]=-1;
7370 //Don't clear regs in the delay slot as the branch might need them
7371 //current.regmap[hr]=-1;
7372 }else
7373 regs[i].regmap_entry[hr]=r;
57871462 7374 }
7375 } else {
7376 // First instruction expects CCREG to be allocated
9f51b4b9 7377 if(i==0&&hr==HOST_CCREG)
57871462 7378 regs[i].regmap_entry[hr]=CCREG;
7379 else
7380 regs[i].regmap_entry[hr]=-1;
7381 }
7382 }
7383 }
7384 else { // Not delay slot
90f98e7c 7385 current.noevict = 0;
cf95b4f0 7386 switch(dops[i].itype) {
57871462 7387 case UJUMP:
7388 //current.isconst=0; // DEBUG
7389 //current.wasconst=0; // DEBUG
7390 //regs[i].wasconst=0; // DEBUG
cf95b4f0 7391 clear_const(&current,dops[i].rt1);
57871462 7392 alloc_cc(&current,i);
7393 dirty_reg(&current,CCREG);
cf95b4f0 7394 if (dops[i].rt1==31) {
57871462 7395 alloc_reg(&current,i,31);
7396 dirty_reg(&current,31);
cf95b4f0 7397 //assert(dops[i+1].rs1!=31&&dops[i+1].rs2!=31);
7398 //assert(dops[i+1].rt1!=dops[i].rt1);
57871462 7399 #ifdef REG_PREFETCH
7400 alloc_reg(&current,i,PTEMP);
7401 #endif
57871462 7402 }
cf95b4f0 7403 dops[i].ooo=1;
269bb29a 7404 delayslot_alloc(&current,i+1);
57871462 7405 //current.isconst=0; // DEBUG
7406 ds=1;
57871462 7407 break;
7408 case RJUMP:
7409 //current.isconst=0;
7410 //current.wasconst=0;
7411 //regs[i].wasconst=0;
cf95b4f0 7412 clear_const(&current,dops[i].rs1);
7413 clear_const(&current,dops[i].rt1);
57871462 7414 alloc_cc(&current,i);
7415 dirty_reg(&current,CCREG);
4919de1e 7416 if (!ds_writes_rjump_rs(i)) {
cf95b4f0 7417 alloc_reg(&current,i,dops[i].rs1);
7418 if (dops[i].rt1!=0) {
7419 alloc_reg(&current,i,dops[i].rt1);
7420 dirty_reg(&current,dops[i].rt1);
57871462 7421 #ifdef REG_PREFETCH
7422 alloc_reg(&current,i,PTEMP);
7423 #endif
7424 }
7425 #ifdef USE_MINI_HT
cf95b4f0 7426 if(dops[i].rs1==31) { // JALR
57871462 7427 alloc_reg(&current,i,RHASH);
57871462 7428 alloc_reg(&current,i,RHTBL);
57871462 7429 }
7430 #endif
7431 delayslot_alloc(&current,i+1);
7432 } else {
7433 // The delay slot overwrites our source register,
7434 // allocate a temporary register to hold the old value.
7435 current.isconst=0;
7436 current.wasconst=0;
7437 regs[i].wasconst=0;
7438 delayslot_alloc(&current,i+1);
7439 current.isconst=0;
7440 alloc_reg(&current,i,RTEMP);
7441 }
7442 //current.isconst=0; // DEBUG
cf95b4f0 7443 dops[i].ooo=1;
57871462 7444 ds=1;
7445 break;
7446 case CJUMP:
7447 //current.isconst=0;
7448 //current.wasconst=0;
7449 //regs[i].wasconst=0;
cf95b4f0 7450 clear_const(&current,dops[i].rs1);
7451 clear_const(&current,dops[i].rs2);
7452 if((dops[i].opcode&0x3E)==4) // BEQ/BNE
57871462 7453 {
7454 alloc_cc(&current,i);
7455 dirty_reg(&current,CCREG);
cf95b4f0 7456 if(dops[i].rs1) alloc_reg(&current,i,dops[i].rs1);
7457 if(dops[i].rs2) alloc_reg(&current,i,dops[i].rs2);
7458 if((dops[i].rs1&&(dops[i].rs1==dops[i+1].rt1||dops[i].rs1==dops[i+1].rt2))||
7459 (dops[i].rs2&&(dops[i].rs2==dops[i+1].rt1||dops[i].rs2==dops[i+1].rt2))) {
57871462 7460 // The delay slot overwrites one of our conditions.
7461 // Allocate the branch condition registers instead.
57871462 7462 current.isconst=0;
7463 current.wasconst=0;
7464 regs[i].wasconst=0;
cf95b4f0 7465 if(dops[i].rs1) alloc_reg(&current,i,dops[i].rs1);
7466 if(dops[i].rs2) alloc_reg(&current,i,dops[i].rs2);
57871462 7467 }
e1190b87 7468 else
7469 {
cf95b4f0 7470 dops[i].ooo=1;
e1190b87 7471 delayslot_alloc(&current,i+1);
7472 }
57871462 7473 }
7474 else
cf95b4f0 7475 if((dops[i].opcode&0x3E)==6) // BLEZ/BGTZ
57871462 7476 {
7477 alloc_cc(&current,i);
7478 dirty_reg(&current,CCREG);
cf95b4f0 7479 alloc_reg(&current,i,dops[i].rs1);
7480 if(dops[i].rs1&&(dops[i].rs1==dops[i+1].rt1||dops[i].rs1==dops[i+1].rt2)) {
57871462 7481 // The delay slot overwrites one of our conditions.
7482 // Allocate the branch condition registers instead.
57871462 7483 current.isconst=0;
7484 current.wasconst=0;
7485 regs[i].wasconst=0;
cf95b4f0 7486 if(dops[i].rs1) alloc_reg(&current,i,dops[i].rs1);
57871462 7487 }
e1190b87 7488 else
7489 {
cf95b4f0 7490 dops[i].ooo=1;
e1190b87 7491 delayslot_alloc(&current,i+1);
7492 }
57871462 7493 }
7494 else
7495 // Don't alloc the delay slot yet because we might not execute it
cf95b4f0 7496 if((dops[i].opcode&0x3E)==0x14) // BEQL/BNEL
57871462 7497 {
7498 current.isconst=0;
7499 current.wasconst=0;
7500 regs[i].wasconst=0;
7501 alloc_cc(&current,i);
7502 dirty_reg(&current,CCREG);
cf95b4f0 7503 alloc_reg(&current,i,dops[i].rs1);
7504 alloc_reg(&current,i,dops[i].rs2);
57871462 7505 }
7506 else
cf95b4f0 7507 if((dops[i].opcode&0x3E)==0x16) // BLEZL/BGTZL
57871462 7508 {
7509 current.isconst=0;
7510 current.wasconst=0;
7511 regs[i].wasconst=0;
7512 alloc_cc(&current,i);
7513 dirty_reg(&current,CCREG);
cf95b4f0 7514 alloc_reg(&current,i,dops[i].rs1);
57871462 7515 }
7516 ds=1;
7517 //current.isconst=0;
7518 break;
7519 case SJUMP:
cf95b4f0 7520 clear_const(&current,dops[i].rs1);
7521 clear_const(&current,dops[i].rt1);
57871462 7522 {
7523 alloc_cc(&current,i);
7524 dirty_reg(&current,CCREG);
cf95b4f0 7525 alloc_reg(&current,i,dops[i].rs1);
ecca05e3 7526 if (dops[i].rt1 == 31) { // BLTZAL/BGEZAL
57871462 7527 alloc_reg(&current,i,31);
7528 dirty_reg(&current,31);
57871462 7529 }
ecca05e3 7530 if ((dops[i].rs1 &&
7531 (dops[i].rs1==dops[i+1].rt1||dops[i].rs1==dops[i+1].rt2)) // The delay slot overwrites the branch condition.
7532 ||(dops[i].rt1 == 31 && dops[i].rs1 == 31) // overwrites it's own condition
cf95b4f0 7533 ||(dops[i].rt1==31&&(dops[i+1].rs1==31||dops[i+1].rs2==31||dops[i+1].rt1==31||dops[i+1].rt2==31))) { // DS touches $ra
57871462 7534 // Allocate the branch condition registers instead.
57871462 7535 current.isconst=0;
7536 current.wasconst=0;
7537 regs[i].wasconst=0;
cf95b4f0 7538 if(dops[i].rs1) alloc_reg(&current,i,dops[i].rs1);
57871462 7539 }
e1190b87 7540 else
7541 {
cf95b4f0 7542 dops[i].ooo=1;
e1190b87 7543 delayslot_alloc(&current,i+1);
7544 }
57871462 7545 }
57871462 7546 ds=1;
7547 //current.isconst=0;
7548 break;
57871462 7549 case IMM16:
7550 imm16_alloc(&current,i);
7551 break;
7552 case LOAD:
7553 case LOADLR:
7554 load_alloc(&current,i);
7555 break;
7556 case STORE:
7557 case STORELR:
7558 store_alloc(&current,i);
7559 break;
7560 case ALU:
7561 alu_alloc(&current,i);
7562 break;
7563 case SHIFT:
7564 shift_alloc(&current,i);
7565 break;
7566 case MULTDIV:
7567 multdiv_alloc(&current,i);
7568 break;
7569 case SHIFTIMM:
7570 shiftimm_alloc(&current,i);
7571 break;
7572 case MOV:
7573 mov_alloc(&current,i);
7574 break;
7575 case COP0:
7576 cop0_alloc(&current,i);
7577 break;
a5cd72d0 7578 case RFE:
7579 rfe_alloc(&current,i);
81dbbf4c 7580 break;
b9b61529 7581 case COP2:
81dbbf4c 7582 cop2_alloc(&current,i);
57871462 7583 break;
b9b61529 7584 case C2LS:
7585 c2ls_alloc(&current,i);
7586 break;
7587 case C2OP:
7588 c2op_alloc(&current,i);
7589 break;
57871462 7590 case SYSCALL:
7139f3c8 7591 case HLECALL:
1e973cb0 7592 case INTCALL:
57871462 7593 syscall_alloc(&current,i);
7594 break;
57871462 7595 }
9f51b4b9 7596
57871462 7597 // Create entry (branch target) regmap
7598 for(hr=0;hr<HOST_REGS;hr++)
7599 {
581335b0 7600 int r,or;
57871462 7601 r=current.regmap[hr];
7602 if(r>=0) {
7603 if(r!=regmap_pre[i][hr]) {
7604 // TODO: delay slot (?)
7605 or=get_reg(regmap_pre[i],r); // Get old mapping for this register
9de8a0c3 7606 if(or<0||r>=TEMPREG){
57871462 7607 regs[i].regmap_entry[hr]=-1;
7608 }
7609 else
7610 {
7611 // Just move it to a different register
7612 regs[i].regmap_entry[hr]=r;
7613 // If it was dirty before, it's still dirty
9de8a0c3 7614 if((regs[i].wasdirty>>or)&1) dirty_reg(&current,r);
57871462 7615 }
7616 }
7617 else
7618 {
7619 // Unneeded
7620 if(r==0){
7621 regs[i].regmap_entry[hr]=0;
7622 }
7623 else
7c3a5182 7624 {
7625 assert(r<64);
57871462 7626 if((current.u>>r)&1) {
7627 regs[i].regmap_entry[hr]=-1;
7628 //regs[i].regmap[hr]=-1;
7629 current.regmap[hr]=-1;
7630 }else
7631 regs[i].regmap_entry[hr]=r;
7632 }
57871462 7633 }
7634 } else {
7635 // Branches expect CCREG to be allocated at the target
9f51b4b9 7636 if(regmap_pre[i][hr]==CCREG)
57871462 7637 regs[i].regmap_entry[hr]=CCREG;
7638 else
7639 regs[i].regmap_entry[hr]=-1;
7640 }
7641 }
7642 memcpy(regs[i].regmap,current.regmap,sizeof(current.regmap));
7643 }
27727b63 7644
9b495f6e 7645#if 0 // see do_store_smc_check()
277718fa 7646 if(i>0&&(dops[i-1].itype==STORE||dops[i-1].itype==STORELR||(dops[i-1].itype==C2LS&&dops[i-1].opcode==0x3a))&&(u_int)cinfo[i-1].imm<0x800)
cf95b4f0 7647 current.waswritten|=1<<dops[i-1].rs1;
7648 current.waswritten&=~(1<<dops[i].rt1);
7649 current.waswritten&=~(1<<dops[i].rt2);
277718fa 7650 if((dops[i].itype==STORE||dops[i].itype==STORELR||(dops[i].itype==C2LS&&dops[i].opcode==0x3a))&&(u_int)cinfo[i].imm>=0x800)
cf95b4f0 7651 current.waswritten&=~(1<<dops[i].rs1);
9b495f6e 7652#endif
27727b63 7653
57871462 7654 /* Branch post-alloc */
7655 if(i>0)
7656 {
57871462 7657 current.wasdirty=current.dirty;
cf95b4f0 7658 switch(dops[i-1].itype) {
57871462 7659 case UJUMP:
7660 memcpy(&branch_regs[i-1],&current,sizeof(current));
7661 branch_regs[i-1].isconst=0;
7662 branch_regs[i-1].wasconst=0;
cf95b4f0 7663 branch_regs[i-1].u=branch_unneeded_reg[i-1]&~((1LL<<dops[i-1].rs1)|(1LL<<dops[i-1].rs2));
57871462 7664 alloc_cc(&branch_regs[i-1],i-1);
7665 dirty_reg(&branch_regs[i-1],CCREG);
cf95b4f0 7666 if(dops[i-1].rt1==31) { // JAL
57871462 7667 alloc_reg(&branch_regs[i-1],i-1,31);
7668 dirty_reg(&branch_regs[i-1],31);
57871462 7669 }
7670 memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
40fca85b 7671 memcpy(constmap[i],constmap[i-1],sizeof(constmap[i]));
57871462 7672 break;
7673 case RJUMP:
7674 memcpy(&branch_regs[i-1],&current,sizeof(current));
7675 branch_regs[i-1].isconst=0;
7676 branch_regs[i-1].wasconst=0;
cf95b4f0 7677 branch_regs[i-1].u=branch_unneeded_reg[i-1]&~((1LL<<dops[i-1].rs1)|(1LL<<dops[i-1].rs2));
57871462 7678 alloc_cc(&branch_regs[i-1],i-1);
7679 dirty_reg(&branch_regs[i-1],CCREG);
cf95b4f0 7680 alloc_reg(&branch_regs[i-1],i-1,dops[i-1].rs1);
7681 if(dops[i-1].rt1!=0) { // JALR
7682 alloc_reg(&branch_regs[i-1],i-1,dops[i-1].rt1);
7683 dirty_reg(&branch_regs[i-1],dops[i-1].rt1);
57871462 7684 }
7685 #ifdef USE_MINI_HT
cf95b4f0 7686 if(dops[i-1].rs1==31) { // JALR
57871462 7687 alloc_reg(&branch_regs[i-1],i-1,RHASH);
57871462 7688 alloc_reg(&branch_regs[i-1],i-1,RHTBL);
57871462 7689 }
7690 #endif
7691 memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
40fca85b 7692 memcpy(constmap[i],constmap[i-1],sizeof(constmap[i]));
57871462 7693 break;
7694 case CJUMP:
cf95b4f0 7695 if((dops[i-1].opcode&0x3E)==4) // BEQ/BNE
57871462 7696 {
7697 alloc_cc(&current,i-1);
7698 dirty_reg(&current,CCREG);
cf95b4f0 7699 if((dops[i-1].rs1&&(dops[i-1].rs1==dops[i].rt1||dops[i-1].rs1==dops[i].rt2))||
7700 (dops[i-1].rs2&&(dops[i-1].rs2==dops[i].rt1||dops[i-1].rs2==dops[i].rt2))) {
57871462 7701 // The delay slot overwrote one of our conditions
7702 // Delay slot goes after the test (in order)
cf95b4f0 7703 current.u=branch_unneeded_reg[i-1]&~((1LL<<dops[i].rs1)|(1LL<<dops[i].rs2));
57871462 7704 current.u|=1;
57871462 7705 delayslot_alloc(&current,i);
7706 current.isconst=0;
7707 }
7708 else
7709 {
cf95b4f0 7710 current.u=branch_unneeded_reg[i-1]&~((1LL<<dops[i-1].rs1)|(1LL<<dops[i-1].rs2));
57871462 7711 // Alloc the branch condition registers
cf95b4f0 7712 if(dops[i-1].rs1) alloc_reg(&current,i-1,dops[i-1].rs1);
7713 if(dops[i-1].rs2) alloc_reg(&current,i-1,dops[i-1].rs2);
57871462 7714 }
7715 memcpy(&branch_regs[i-1],&current,sizeof(current));
7716 branch_regs[i-1].isconst=0;
7717 branch_regs[i-1].wasconst=0;
7718 memcpy(&branch_regs[i-1].regmap_entry,&current.regmap,sizeof(current.regmap));
40fca85b 7719 memcpy(constmap[i],constmap[i-1],sizeof(constmap[i]));
57871462 7720 }
7721 else
cf95b4f0 7722 if((dops[i-1].opcode&0x3E)==6) // BLEZ/BGTZ
57871462 7723 {
7724 alloc_cc(&current,i-1);
7725 dirty_reg(&current,CCREG);
cf95b4f0 7726 if(dops[i-1].rs1==dops[i].rt1||dops[i-1].rs1==dops[i].rt2) {
57871462 7727 // The delay slot overwrote the branch condition
7728 // Delay slot goes after the test (in order)
cf95b4f0 7729 current.u=branch_unneeded_reg[i-1]&~((1LL<<dops[i].rs1)|(1LL<<dops[i].rs2));
57871462 7730 current.u|=1;
57871462 7731 delayslot_alloc(&current,i);
7732 current.isconst=0;
7733 }
7734 else
7735 {
cf95b4f0 7736 current.u=branch_unneeded_reg[i-1]&~(1LL<<dops[i-1].rs1);
57871462 7737 // Alloc the branch condition register
cf95b4f0 7738 alloc_reg(&current,i-1,dops[i-1].rs1);
57871462 7739 }
7740 memcpy(&branch_regs[i-1],&current,sizeof(current));
7741 branch_regs[i-1].isconst=0;
7742 branch_regs[i-1].wasconst=0;
7743 memcpy(&branch_regs[i-1].regmap_entry,&current.regmap,sizeof(current.regmap));
40fca85b 7744 memcpy(constmap[i],constmap[i-1],sizeof(constmap[i]));
57871462 7745 }
57871462 7746 break;
7747 case SJUMP:
57871462 7748 {
7749 alloc_cc(&current,i-1);
7750 dirty_reg(&current,CCREG);
cf95b4f0 7751 if(dops[i-1].rs1==dops[i].rt1||dops[i-1].rs1==dops[i].rt2) {
57871462 7752 // The delay slot overwrote the branch condition
7753 // Delay slot goes after the test (in order)
cf95b4f0 7754 current.u=branch_unneeded_reg[i-1]&~((1LL<<dops[i].rs1)|(1LL<<dops[i].rs2));
57871462 7755 current.u|=1;
57871462 7756 delayslot_alloc(&current,i);
7757 current.isconst=0;
7758 }
7759 else
7760 {
cf95b4f0 7761 current.u=branch_unneeded_reg[i-1]&~(1LL<<dops[i-1].rs1);
57871462 7762 // Alloc the branch condition register
cf95b4f0 7763 alloc_reg(&current,i-1,dops[i-1].rs1);
57871462 7764 }
7765 memcpy(&branch_regs[i-1],&current,sizeof(current));
7766 branch_regs[i-1].isconst=0;
7767 branch_regs[i-1].wasconst=0;
7768 memcpy(&branch_regs[i-1].regmap_entry,&current.regmap,sizeof(current.regmap));
40fca85b 7769 memcpy(constmap[i],constmap[i-1],sizeof(constmap[i]));
57871462 7770 }
57871462 7771 break;
57871462 7772 }
7773
fe807a8a 7774 if (dops[i-1].is_ujump)
57871462 7775 {
cf95b4f0 7776 if(dops[i-1].rt1==31) // JAL/JALR
57871462 7777 {
7778 // Subroutine call will return here, don't alloc any registers
57871462 7779 current.dirty=0;
7780 clear_all_regs(current.regmap);
7781 alloc_reg(&current,i,CCREG);
7782 dirty_reg(&current,CCREG);
7783 }
7784 else if(i+1<slen)
7785 {
7786 // Internal branch will jump here, match registers to caller
57871462 7787 current.dirty=0;
7788 clear_all_regs(current.regmap);
7789 alloc_reg(&current,i,CCREG);
7790 dirty_reg(&current,CCREG);
7791 for(j=i-1;j>=0;j--)
7792 {
277718fa 7793 if(cinfo[j].ba==start+i*4+4) {
57871462 7794 memcpy(current.regmap,branch_regs[j].regmap,sizeof(current.regmap));
57871462 7795 current.dirty=branch_regs[j].dirty;
7796 break;
7797 }
7798 }
7799 while(j>=0) {
277718fa 7800 if(cinfo[j].ba==start+i*4+4) {
57871462 7801 for(hr=0;hr<HOST_REGS;hr++) {
7802 if(current.regmap[hr]!=branch_regs[j].regmap[hr]) {
7803 current.regmap[hr]=-1;
7804 }
57871462 7805 current.dirty&=branch_regs[j].dirty;
7806 }
7807 }
7808 j--;
7809 }
7810 }
7811 }
7812 }
7813
7814 // Count cycles in between branches
277718fa 7815 cinfo[i].ccadj = CLOCK_ADJUST(cc);
a5cd72d0 7816 if (i > 0 && (dops[i-1].is_jump || dops[i].is_exception))
57871462 7817 {
7818 cc=0;
7819 }
71e490c5 7820#if !defined(DRC_DBG)
cf95b4f0 7821 else if(dops[i].itype==C2OP&&gte_cycletab[source[i]&0x3f]>2)
054175e9 7822 {
81dbbf4c 7823 // this should really be removed since the real stalls have been implemented,
7824 // but doing so causes sizeable perf regression against the older version
7825 u_int gtec = gte_cycletab[source[i] & 0x3f];
32631e6a 7826 cc += HACK_ENABLED(NDHACK_NO_STALLS) ? gtec/2 : 2;
fb407447 7827 }
cf95b4f0 7828 else if(i>1&&dops[i].itype==STORE&&dops[i-1].itype==STORE&&dops[i-2].itype==STORE&&!dops[i].bt)
5fdcbb5a 7829 {
7830 cc+=4;
7831 }
cf95b4f0 7832 else if(dops[i].itype==C2LS)
fb407447 7833 {
81dbbf4c 7834 // same as with C2OP
32631e6a 7835 cc += HACK_ENABLED(NDHACK_NO_STALLS) ? 4 : 2;
fb407447 7836 }
7837#endif
57871462 7838 else
7839 {
7840 cc++;
7841 }
7842
cf95b4f0 7843 if(!dops[i].is_ds) {
57871462 7844 regs[i].dirty=current.dirty;
7845 regs[i].isconst=current.isconst;
40fca85b 7846 memcpy(constmap[i],current_constmap,sizeof(constmap[i]));
57871462 7847 }
7848 for(hr=0;hr<HOST_REGS;hr++) {
7849 if(hr!=EXCLUDE_REG&&regs[i].regmap[hr]>=0) {
7850 if(regmap_pre[i][hr]!=regs[i].regmap[hr]) {
7851 regs[i].wasconst&=~(1<<hr);
7852 }
7853 }
7854 }
9b495f6e 7855 //regs[i].waswritten=current.waswritten;
57871462 7856 }
4149788d 7857}
9f51b4b9 7858
4149788d 7859static noinline void pass4_cull_unused_regs(void)
7860{
53358c1d 7861 u_int last_needed_regs[4] = {0,0,0,0};
4149788d 7862 u_int nr=0;
7863 int i;
9f51b4b9 7864
57871462 7865 for (i=slen-1;i>=0;i--)
7866 {
7867 int hr;
53358c1d 7868 __builtin_prefetch(regs[i-2].regmap);
fe807a8a 7869 if(dops[i].is_jump)
57871462 7870 {
277718fa 7871 if(cinfo[i].ba<start || cinfo[i].ba>=(start+slen*4))
57871462 7872 {
7873 // Branch out of this block, don't need anything
7874 nr=0;
7875 }
7876 else
7877 {
7878 // Internal branch
7879 // Need whatever matches the target
7880 nr=0;
277718fa 7881 int t=(cinfo[i].ba-start)>>2;
57871462 7882 for(hr=0;hr<HOST_REGS;hr++)
7883 {
7884 if(regs[i].regmap_entry[hr]>=0) {
7885 if(regs[i].regmap_entry[hr]==regs[t].regmap_entry[hr]) nr|=1<<hr;
7886 }
7887 }
7888 }
7889 // Conditional branch may need registers for following instructions
fe807a8a 7890 if (!dops[i].is_ujump)
57871462 7891 {
7892 if(i<slen-2) {
53358c1d 7893 nr |= last_needed_regs[(i+2) & 3];
57871462 7894 for(hr=0;hr<HOST_REGS;hr++)
7895 {
7896 if(regmap_pre[i+2][hr]>=0&&get_reg(regs[i+2].regmap_entry,regmap_pre[i+2][hr])<0) nr&=~(1<<hr);
7897 //if((regmap_entry[i+2][hr])>=0) if(!((nr>>hr)&1)) printf("%x-bogus(%d=%d)\n",start+i*4,hr,regmap_entry[i+2][hr]);
7898 }
7899 }
7900 }
7901 // Don't need stuff which is overwritten
f5955059 7902 //if(regs[i].regmap[hr]!=regmap_pre[i][hr]) nr&=~(1<<hr);
7903 //if(regs[i].regmap[hr]<0) nr&=~(1<<hr);
57871462 7904 // Merge in delay slot
53358c1d 7905 if (dops[i+1].rt1) nr &= ~get_regm(regs[i].regmap, dops[i+1].rt1);
7906 if (dops[i+1].rt2) nr &= ~get_regm(regs[i].regmap, dops[i+1].rt2);
7907 nr |= get_regm(regmap_pre[i], dops[i+1].rs1);
7908 nr |= get_regm(regmap_pre[i], dops[i+1].rs2);
7909 nr |= get_regm(regs[i].regmap_entry, dops[i+1].rs1);
7910 nr |= get_regm(regs[i].regmap_entry, dops[i+1].rs2);
7911 if (ram_offset && (dops[i+1].is_load || dops[i+1].is_store)) {
7912 nr |= get_regm(regmap_pre[i], ROREG);
7913 nr |= get_regm(regs[i].regmap_entry, ROREG);
7914 }
7915 if (dops[i+1].is_store) {
7916 nr |= get_regm(regmap_pre[i], INVCP);
7917 nr |= get_regm(regs[i].regmap_entry, INVCP);
57871462 7918 }
7919 }
277718fa 7920 else if (dops[i].is_exception)
57871462 7921 {
277718fa 7922 // SYSCALL instruction, etc
57871462 7923 nr=0;
7924 }
7925 else // Non-branch
7926 {
7927 if(i<slen-1) {
7928 for(hr=0;hr<HOST_REGS;hr++) {
7929 if(regmap_pre[i+1][hr]>=0&&get_reg(regs[i+1].regmap_entry,regmap_pre[i+1][hr])<0) nr&=~(1<<hr);
7930 if(regs[i].regmap[hr]!=regmap_pre[i+1][hr]) nr&=~(1<<hr);
7931 if(regs[i].regmap[hr]!=regmap_pre[i][hr]) nr&=~(1<<hr);
7932 if(regs[i].regmap[hr]<0) nr&=~(1<<hr);
7933 }
7934 }
7935 }
53358c1d 7936 // Overwritten registers are not needed
7937 if (dops[i].rt1) nr &= ~get_regm(regs[i].regmap, dops[i].rt1);
7938 if (dops[i].rt2) nr &= ~get_regm(regs[i].regmap, dops[i].rt2);
7939 nr &= ~get_regm(regs[i].regmap, FTEMP);
7940 // Source registers are needed
7941 nr |= get_regm(regmap_pre[i], dops[i].rs1);
7942 nr |= get_regm(regmap_pre[i], dops[i].rs2);
7943 nr |= get_regm(regs[i].regmap_entry, dops[i].rs1);
7944 nr |= get_regm(regs[i].regmap_entry, dops[i].rs2);
7945 if (ram_offset && (dops[i].is_load || dops[i].is_store)) {
7946 nr |= get_regm(regmap_pre[i], ROREG);
7947 nr |= get_regm(regs[i].regmap_entry, ROREG);
7948 }
7949 if (dops[i].is_store) {
7950 nr |= get_regm(regmap_pre[i], INVCP);
7951 nr |= get_regm(regs[i].regmap_entry, INVCP);
7952 }
7953
7954 if (i > 0 && !dops[i].bt && regs[i].wasdirty)
57871462 7955 for(hr=0;hr<HOST_REGS;hr++)
7956 {
57871462 7957 // Don't store a register immediately after writing it,
7958 // may prevent dual-issue.
7959 // But do so if this is a branch target, otherwise we
7960 // might have to load the register before the branch.
53358c1d 7961 if((regs[i].wasdirty>>hr)&1) {
7c3a5182 7962 if((regmap_pre[i][hr]>0&&!((unneeded_reg[i]>>regmap_pre[i][hr])&1))) {
9de8a0c3 7963 if(dops[i-1].rt1==regmap_pre[i][hr]) nr|=1<<hr;
7964 if(dops[i-1].rt2==regmap_pre[i][hr]) nr|=1<<hr;
57871462 7965 }
7c3a5182 7966 if((regs[i].regmap_entry[hr]>0&&!((unneeded_reg[i]>>regs[i].regmap_entry[hr])&1))) {
9de8a0c3 7967 if(dops[i-1].rt1==regs[i].regmap_entry[hr]) nr|=1<<hr;
7968 if(dops[i-1].rt2==regs[i].regmap_entry[hr]) nr|=1<<hr;
57871462 7969 }
7970 }
7971 }
7972 // Cycle count is needed at branches. Assume it is needed at the target too.
de6dbc52 7973 if (i == 0 || dops[i].bt || dops[i].may_except || dops[i].itype == CJUMP) {
57871462 7974 if(regmap_pre[i][HOST_CCREG]==CCREG) nr|=1<<HOST_CCREG;
7975 if(regs[i].regmap_entry[HOST_CCREG]==CCREG) nr|=1<<HOST_CCREG;
7976 }
7977 // Save it
53358c1d 7978 last_needed_regs[i & 3] = nr;
9f51b4b9 7979
57871462 7980 // Deallocate unneeded registers
7981 for(hr=0;hr<HOST_REGS;hr++)
7982 {
7983 if(!((nr>>hr)&1)) {
7984 if(regs[i].regmap_entry[hr]!=CCREG) regs[i].regmap_entry[hr]=-1;
fe807a8a 7985 if(dops[i].is_jump)
57871462 7986 {
37387d8b 7987 int map1 = 0, map2 = 0, temp = 0; // or -1 ??
7988 if (dops[i+1].is_load || dops[i+1].is_store)
7989 map1 = ROREG;
7990 if (dops[i+1].is_store)
7991 map2 = INVCP;
7992 if(dops[i+1].itype==LOADLR || dops[i+1].itype==STORELR || dops[i+1].itype==C2LS)
7993 temp = FTEMP;
9de8a0c3 7994 if(regs[i].regmap[hr]!=dops[i].rs1 && regs[i].regmap[hr]!=dops[i].rs2 &&
7995 regs[i].regmap[hr]!=dops[i].rt1 && regs[i].regmap[hr]!=dops[i].rt2 &&
7996 regs[i].regmap[hr]!=dops[i+1].rt1 && regs[i].regmap[hr]!=dops[i+1].rt2 &&
cf95b4f0 7997 regs[i].regmap[hr]!=dops[i+1].rs1 && regs[i].regmap[hr]!=dops[i+1].rs2 &&
9de8a0c3 7998 regs[i].regmap[hr]!=temp && regs[i].regmap[hr]!=PTEMP &&
57871462 7999 regs[i].regmap[hr]!=RHASH && regs[i].regmap[hr]!=RHTBL &&
8000 regs[i].regmap[hr]!=RTEMP && regs[i].regmap[hr]!=CCREG &&
37387d8b 8001 regs[i].regmap[hr]!=map1 && regs[i].regmap[hr]!=map2)
57871462 8002 {
8003 regs[i].regmap[hr]=-1;
8004 regs[i].isconst&=~(1<<hr);
a550c61c 8005 regs[i].dirty&=~(1<<hr);
8006 regs[i+1].wasdirty&=~(1<<hr);
9de8a0c3 8007 if(branch_regs[i].regmap[hr]!=dops[i].rs1 && branch_regs[i].regmap[hr]!=dops[i].rs2 &&
8008 branch_regs[i].regmap[hr]!=dops[i].rt1 && branch_regs[i].regmap[hr]!=dops[i].rt2 &&
8009 branch_regs[i].regmap[hr]!=dops[i+1].rt1 && branch_regs[i].regmap[hr]!=dops[i+1].rt2 &&
cf95b4f0 8010 branch_regs[i].regmap[hr]!=dops[i+1].rs1 && branch_regs[i].regmap[hr]!=dops[i+1].rs2 &&
9de8a0c3 8011 branch_regs[i].regmap[hr]!=temp && branch_regs[i].regmap[hr]!=PTEMP &&
57871462 8012 branch_regs[i].regmap[hr]!=RHASH && branch_regs[i].regmap[hr]!=RHTBL &&
8013 branch_regs[i].regmap[hr]!=RTEMP && branch_regs[i].regmap[hr]!=CCREG &&
37387d8b 8014 branch_regs[i].regmap[hr]!=map1 && branch_regs[i].regmap[hr]!=map2)
57871462 8015 {
8016 branch_regs[i].regmap[hr]=-1;
8017 branch_regs[i].regmap_entry[hr]=-1;
fe807a8a 8018 if (!dops[i].is_ujump)
57871462 8019 {
fe807a8a 8020 if (i < slen-2) {
57871462 8021 regmap_pre[i+2][hr]=-1;
79c75f1b 8022 regs[i+2].wasconst&=~(1<<hr);
57871462 8023 }
8024 }
8025 }
8026 }
8027 }
8028 else
8029 {
8030 // Non-branch
8031 if(i>0)
8032 {
37387d8b 8033 int map1 = -1, map2 = -1, temp=-1;
8034 if (dops[i].is_load || dops[i].is_store)
8035 map1 = ROREG;
8036 if (dops[i].is_store)
8037 map2 = INVCP;
8038 if (dops[i].itype==LOADLR || dops[i].itype==STORELR || dops[i].itype==C2LS)
8039 temp = FTEMP;
9de8a0c3 8040 if(regs[i].regmap[hr]!=dops[i].rt1 && regs[i].regmap[hr]!=dops[i].rt2 &&
cf95b4f0 8041 regs[i].regmap[hr]!=dops[i].rs1 && regs[i].regmap[hr]!=dops[i].rs2 &&
9de8a0c3 8042 regs[i].regmap[hr]!=temp && regs[i].regmap[hr]!=map1 && regs[i].regmap[hr]!=map2 &&
4b1c7cd1 8043 //(dops[i].itype!=SPAN||regs[i].regmap[hr]!=CCREG)
8044 regs[i].regmap[hr] != CCREG)
57871462 8045 {
cf95b4f0 8046 if(i<slen-1&&!dops[i].is_ds) {
ad49de89 8047 assert(regs[i].regmap[hr]<64);
afec9d44 8048 if(regmap_pre[i+1][hr]!=-1 || regs[i].regmap[hr]>0)
57871462 8049 if(regmap_pre[i+1][hr]!=regs[i].regmap[hr])
57871462 8050 {
c43b5311 8051 SysPrintf("fail: %x (%d %d!=%d)\n",start+i*4,hr,regmap_pre[i+1][hr],regs[i].regmap[hr]);
57871462 8052 assert(regmap_pre[i+1][hr]==regs[i].regmap[hr]);
8053 }
8054 regmap_pre[i+1][hr]=-1;
8055 if(regs[i+1].regmap_entry[hr]==CCREG) regs[i+1].regmap_entry[hr]=-1;
79c75f1b 8056 regs[i+1].wasconst&=~(1<<hr);
57871462 8057 }
8058 regs[i].regmap[hr]=-1;
8059 regs[i].isconst&=~(1<<hr);
a550c61c 8060 regs[i].dirty&=~(1<<hr);
8061 regs[i+1].wasdirty&=~(1<<hr);
57871462 8062 }
8063 }
8064 }
3968e69e 8065 } // if needed
8066 } // for hr
57871462 8067 }
4149788d 8068}
9f51b4b9 8069
4149788d 8070// If a register is allocated during a loop, try to allocate it for the
8071// entire loop, if possible. This avoids loading/storing registers
8072// inside of the loop.
8073static noinline void pass5a_preallocate1(void)
8074{
8075 int i, j, hr;
57871462 8076 signed char f_regmap[HOST_REGS];
8077 clear_all_regs(f_regmap);
8078 for(i=0;i<slen-1;i++)
8079 {
cf95b4f0 8080 if(dops[i].itype==UJUMP||dops[i].itype==CJUMP||dops[i].itype==SJUMP)
57871462 8081 {
277718fa 8082 if(cinfo[i].ba>=start && cinfo[i].ba<(start+i*4))
cf95b4f0 8083 if(dops[i+1].itype==NOP||dops[i+1].itype==MOV||dops[i+1].itype==ALU
8084 ||dops[i+1].itype==SHIFTIMM||dops[i+1].itype==IMM16||dops[i+1].itype==LOAD
a5cd72d0 8085 ||dops[i+1].itype==STORE||dops[i+1].itype==STORELR
8086 ||dops[i+1].itype==SHIFT
cf95b4f0 8087 ||dops[i+1].itype==COP2||dops[i+1].itype==C2LS||dops[i+1].itype==C2OP)
57871462 8088 {
277718fa 8089 int t=(cinfo[i].ba-start)>>2;
fe807a8a 8090 if(t > 0 && !dops[t-1].is_jump) // loop_preload can't handle jumps into delay slots
cf95b4f0 8091 if(t<2||(dops[t-2].itype!=UJUMP&&dops[t-2].itype!=RJUMP)||dops[t-2].rt1!=31) // call/ret assumes no registers allocated
57871462 8092 for(hr=0;hr<HOST_REGS;hr++)
8093 {
7c3a5182 8094 if(regs[i].regmap[hr]>=0) {
b372a952 8095 if(f_regmap[hr]!=regs[i].regmap[hr]) {
8096 // dealloc old register
8097 int n;
8098 for(n=0;n<HOST_REGS;n++)
8099 {
8100 if(f_regmap[n]==regs[i].regmap[hr]) {f_regmap[n]=-1;}
8101 }
8102 // and alloc new one
8103 f_regmap[hr]=regs[i].regmap[hr];
8104 }
8105 }
7c3a5182 8106 if(branch_regs[i].regmap[hr]>=0) {
b372a952 8107 if(f_regmap[hr]!=branch_regs[i].regmap[hr]) {
8108 // dealloc old register
8109 int n;
8110 for(n=0;n<HOST_REGS;n++)
8111 {
8112 if(f_regmap[n]==branch_regs[i].regmap[hr]) {f_regmap[n]=-1;}
8113 }
8114 // and alloc new one
8115 f_regmap[hr]=branch_regs[i].regmap[hr];
8116 }
8117 }
cf95b4f0 8118 if(dops[i].ooo) {
277718fa 8119 if(count_free_regs(regs[i].regmap)<=cinfo[i+1].min_free_regs)
e1190b87 8120 f_regmap[hr]=branch_regs[i].regmap[hr];
8121 }else{
277718fa 8122 if(count_free_regs(branch_regs[i].regmap)<=cinfo[i+1].min_free_regs)
57871462 8123 f_regmap[hr]=branch_regs[i].regmap[hr];
8124 }
8125 // Avoid dirty->clean transition
e1190b87 8126 #ifdef DESTRUCTIVE_WRITEBACK
57871462 8127 if(t>0) if(get_reg(regmap_pre[t],f_regmap[hr])>=0) if((regs[t].wasdirty>>get_reg(regmap_pre[t],f_regmap[hr]))&1) f_regmap[hr]=-1;
e1190b87 8128 #endif
8129 // This check is only strictly required in the DESTRUCTIVE_WRITEBACK
8130 // case above, however it's always a good idea. We can't hoist the
8131 // load if the register was already allocated, so there's no point
8132 // wasting time analyzing most of these cases. It only "succeeds"
8133 // when the mapping was different and the load can be replaced with
8134 // a mov, which is of negligible benefit. So such cases are
8135 // skipped below.
57871462 8136 if(f_regmap[hr]>0) {
198df76f 8137 if(regs[t].regmap[hr]==f_regmap[hr]||(regs[t].regmap_entry[hr]<0&&get_reg(regmap_pre[t],f_regmap[hr])<0)) {
57871462 8138 int r=f_regmap[hr];
8139 for(j=t;j<=i;j++)
8140 {
277718fa 8141 //printf("Test %x -> %x, %x %d/%d\n",start+i*4,cinfo[i].ba,start+j*4,hr,r);
57871462 8142 if(r<34&&((unneeded_reg[j]>>r)&1)) break;
00fa9369 8143 assert(r < 64);
9de8a0c3 8144 if(regs[j].regmap[hr]==f_regmap[hr]&&f_regmap[hr]<TEMPREG) {
277718fa 8145 //printf("Hit %x -> %x, %x %d/%d\n",start+i*4,cinfo[i].ba,start+j*4,hr,r);
57871462 8146 int k;
8147 if(regs[i].regmap[hr]==-1&&branch_regs[i].regmap[hr]==-1) {
670c0f22 8148 if(get_reg(regs[i].regmap,f_regmap[hr])>=0) break;
57871462 8149 if(get_reg(regs[i+2].regmap,f_regmap[hr])>=0) break;
57871462 8150 k=i;
8151 while(k>1&&regs[k-1].regmap[hr]==-1) {
277718fa 8152 if(count_free_regs(regs[k-1].regmap)<=cinfo[k-1].min_free_regs) {
e1190b87 8153 //printf("no free regs for store %x\n",start+(k-1)*4);
8154 break;
57871462 8155 }
57871462 8156 if(get_reg(regs[k-1].regmap,f_regmap[hr])>=0) {
8157 //printf("no-match due to different register\n");
8158 break;
8159 }
fe807a8a 8160 if (dops[k-2].is_jump) {
57871462 8161 //printf("no-match due to branch\n");
8162 break;
8163 }
8164 // call/ret fast path assumes no registers allocated
cf95b4f0 8165 if(k>2&&(dops[k-3].itype==UJUMP||dops[k-3].itype==RJUMP)&&dops[k-3].rt1==31) {
57871462 8166 break;
8167 }
57871462 8168 k--;
8169 }
57871462 8170 if(regs[k-1].regmap[hr]==f_regmap[hr]&&regmap_pre[k][hr]==f_regmap[hr]) {
8171 //printf("Extend r%d, %x ->\n",hr,start+k*4);
8172 while(k<i) {
8173 regs[k].regmap_entry[hr]=f_regmap[hr];
8174 regs[k].regmap[hr]=f_regmap[hr];
8175 regmap_pre[k+1][hr]=f_regmap[hr];
8176 regs[k].wasdirty&=~(1<<hr);
8177 regs[k].dirty&=~(1<<hr);
8178 regs[k].wasdirty|=(1<<hr)&regs[k-1].dirty;
8179 regs[k].dirty|=(1<<hr)&regs[k].wasdirty;
8180 regs[k].wasconst&=~(1<<hr);
8181 regs[k].isconst&=~(1<<hr);
8182 k++;
8183 }
8184 }
8185 else {
8186 //printf("Fail Extend r%d, %x ->\n",hr,start+k*4);
8187 break;
8188 }
8189 assert(regs[i-1].regmap[hr]==f_regmap[hr]);
8190 if(regs[i-1].regmap[hr]==f_regmap[hr]&&regmap_pre[i][hr]==f_regmap[hr]) {
8191 //printf("OK fill %x (r%d)\n",start+i*4,hr);
8192 regs[i].regmap_entry[hr]=f_regmap[hr];
8193 regs[i].regmap[hr]=f_regmap[hr];
8194 regs[i].wasdirty&=~(1<<hr);
8195 regs[i].dirty&=~(1<<hr);
8196 regs[i].wasdirty|=(1<<hr)&regs[i-1].dirty;
8197 regs[i].dirty|=(1<<hr)&regs[i-1].dirty;
8198 regs[i].wasconst&=~(1<<hr);
8199 regs[i].isconst&=~(1<<hr);
8200 branch_regs[i].regmap_entry[hr]=f_regmap[hr];
8201 branch_regs[i].wasdirty&=~(1<<hr);
8202 branch_regs[i].wasdirty|=(1<<hr)&regs[i].dirty;
8203 branch_regs[i].regmap[hr]=f_regmap[hr];
8204 branch_regs[i].dirty&=~(1<<hr);
8205 branch_regs[i].dirty|=(1<<hr)&regs[i].dirty;
8206 branch_regs[i].wasconst&=~(1<<hr);
8207 branch_regs[i].isconst&=~(1<<hr);
fe807a8a 8208 if (!dops[i].is_ujump) {
57871462 8209 regmap_pre[i+2][hr]=f_regmap[hr];
8210 regs[i+2].wasdirty&=~(1<<hr);
8211 regs[i+2].wasdirty|=(1<<hr)&regs[i].dirty;
57871462 8212 }
8213 }
8214 }
8215 for(k=t;k<j;k++) {
e1190b87 8216 // Alloc register clean at beginning of loop,
8217 // but may dirty it in pass 6
57871462 8218 regs[k].regmap_entry[hr]=f_regmap[hr];
8219 regs[k].regmap[hr]=f_regmap[hr];
57871462 8220 regs[k].dirty&=~(1<<hr);
8221 regs[k].wasconst&=~(1<<hr);
8222 regs[k].isconst&=~(1<<hr);
fe807a8a 8223 if (dops[k].is_jump) {
e1190b87 8224 branch_regs[k].regmap_entry[hr]=f_regmap[hr];
8225 branch_regs[k].regmap[hr]=f_regmap[hr];
8226 branch_regs[k].dirty&=~(1<<hr);
8227 branch_regs[k].wasconst&=~(1<<hr);
8228 branch_regs[k].isconst&=~(1<<hr);
fe807a8a 8229 if (!dops[k].is_ujump) {
e1190b87 8230 regmap_pre[k+2][hr]=f_regmap[hr];
8231 regs[k+2].wasdirty&=~(1<<hr);
e1190b87 8232 }
8233 }
8234 else
8235 {
8236 regmap_pre[k+1][hr]=f_regmap[hr];
8237 regs[k+1].wasdirty&=~(1<<hr);
8238 }
57871462 8239 }
8240 if(regs[j].regmap[hr]==f_regmap[hr])
8241 regs[j].regmap_entry[hr]=f_regmap[hr];
8242 break;
8243 }
8244 if(j==i) break;
8245 if(regs[j].regmap[hr]>=0)
8246 break;
8247 if(get_reg(regs[j].regmap,f_regmap[hr])>=0) {
8248 //printf("no-match due to different register\n");
8249 break;
8250 }
fe807a8a 8251 if (dops[j].is_ujump)
e1190b87 8252 {
8253 // Stop on unconditional branch
8254 break;
8255 }
cf95b4f0 8256 if(dops[j].itype==CJUMP||dops[j].itype==SJUMP)
e1190b87 8257 {
cf95b4f0 8258 if(dops[j].ooo) {
277718fa 8259 if(count_free_regs(regs[j].regmap)<=cinfo[j+1].min_free_regs)
e1190b87 8260 break;
8261 }else{
277718fa 8262 if(count_free_regs(branch_regs[j].regmap)<=cinfo[j+1].min_free_regs)
e1190b87 8263 break;
8264 }
8265 if(get_reg(branch_regs[j].regmap,f_regmap[hr])>=0) {
8266 //printf("no-match due to different register (branch)\n");
57871462 8267 break;
8268 }
8269 }
277718fa 8270 if(count_free_regs(regs[j].regmap)<=cinfo[j].min_free_regs) {
e1190b87 8271 //printf("No free regs for store %x\n",start+j*4);
8272 break;
8273 }
ad49de89 8274 assert(f_regmap[hr]<64);
57871462 8275 }
8276 }
8277 }
8278 }
8279 }
8280 }else{
198df76f 8281 // Non branch or undetermined branch target
57871462 8282 for(hr=0;hr<HOST_REGS;hr++)
8283 {
8284 if(hr!=EXCLUDE_REG) {
7c3a5182 8285 if(regs[i].regmap[hr]>=0) {
b372a952 8286 if(f_regmap[hr]!=regs[i].regmap[hr]) {
8287 // dealloc old register
8288 int n;
8289 for(n=0;n<HOST_REGS;n++)
8290 {
8291 if(f_regmap[n]==regs[i].regmap[hr]) {f_regmap[n]=-1;}
8292 }
4149788d 8293 // and alloc new one
8294 f_regmap[hr]=regs[i].regmap[hr];
8295 }
8296 }
8297 }
8298 }
8299 // Try to restore cycle count at branch targets
8300 if(dops[i].bt) {
8301 for(j=i;j<slen-1;j++) {
8302 if(regs[j].regmap[HOST_CCREG]!=-1) break;
277718fa 8303 if(count_free_regs(regs[j].regmap)<=cinfo[j].min_free_regs) {
4149788d 8304 //printf("no free regs for store %x\n",start+j*4);
8305 break;
8306 }
8307 }
8308 if(regs[j].regmap[HOST_CCREG]==CCREG) {
8309 int k=i;
8310 //printf("Extend CC, %x -> %x\n",start+k*4,start+j*4);
8311 while(k<j) {
8312 regs[k].regmap_entry[HOST_CCREG]=CCREG;
8313 regs[k].regmap[HOST_CCREG]=CCREG;
8314 regmap_pre[k+1][HOST_CCREG]=CCREG;
8315 regs[k+1].wasdirty|=1<<HOST_CCREG;
8316 regs[k].dirty|=1<<HOST_CCREG;
8317 regs[k].wasconst&=~(1<<HOST_CCREG);
8318 regs[k].isconst&=~(1<<HOST_CCREG);
8319 k++;
8320 }
8321 regs[j].regmap_entry[HOST_CCREG]=CCREG;
8322 }
8323 // Work backwards from the branch target
8324 if(j>i&&f_regmap[HOST_CCREG]==CCREG)
8325 {
8326 //printf("Extend backwards\n");
8327 int k;
8328 k=i;
8329 while(regs[k-1].regmap[HOST_CCREG]==-1) {
277718fa 8330 if(count_free_regs(regs[k-1].regmap)<=cinfo[k-1].min_free_regs) {
4149788d 8331 //printf("no free regs for store %x\n",start+(k-1)*4);
8332 break;
8333 }
8334 k--;
8335 }
8336 if(regs[k-1].regmap[HOST_CCREG]==CCREG) {
8337 //printf("Extend CC, %x ->\n",start+k*4);
8338 while(k<=i) {
8339 regs[k].regmap_entry[HOST_CCREG]=CCREG;
8340 regs[k].regmap[HOST_CCREG]=CCREG;
8341 regmap_pre[k+1][HOST_CCREG]=CCREG;
8342 regs[k+1].wasdirty|=1<<HOST_CCREG;
8343 regs[k].dirty|=1<<HOST_CCREG;
8344 regs[k].wasconst&=~(1<<HOST_CCREG);
8345 regs[k].isconst&=~(1<<HOST_CCREG);
8346 k++;
8347 }
8348 }
8349 else {
8350 //printf("Fail Extend CC, %x ->\n",start+k*4);
8351 }
8352 }
8353 }
a5cd72d0 8354 if(dops[i].itype!=STORE&&dops[i].itype!=STORELR&&dops[i].itype!=SHIFT&&
4149788d 8355 dops[i].itype!=NOP&&dops[i].itype!=MOV&&dops[i].itype!=ALU&&dops[i].itype!=SHIFTIMM&&
a5cd72d0 8356 dops[i].itype!=IMM16&&dops[i].itype!=LOAD)
4149788d 8357 {
8358 memcpy(f_regmap,regs[i].regmap,sizeof(f_regmap));
8359 }
8360 }
8361 }
8362}
8363
8364// This allocates registers (if possible) one instruction prior
8365// to use, which can avoid a load-use penalty on certain CPUs.
8366static noinline void pass5b_preallocate2(void)
8367{
8368 int i, hr;
8369 for(i=0;i<slen-1;i++)
8370 {
8371 if (!i || !dops[i-1].is_jump)
8372 {
8373 if(!dops[i+1].bt)
8374 {
277718fa 8375 int j, can_steal = 1;
8376 for (j = i; j < i + 2; j++) {
8377 int free_regs = 0;
8378 if (cinfo[j].min_free_regs == 0)
8379 continue;
8380 for (hr = 0; hr < HOST_REGS; hr++)
8381 if (hr != EXCLUDE_REG && regs[j].regmap[hr] < 0)
8382 free_regs++;
8383 if (free_regs <= cinfo[j].min_free_regs) {
8384 can_steal = 0;
8385 break;
8386 }
8387 }
8388 if (!can_steal)
8389 continue;
4149788d 8390 if(dops[i].itype==ALU||dops[i].itype==MOV||dops[i].itype==LOAD||dops[i].itype==SHIFTIMM||dops[i].itype==IMM16
a5cd72d0 8391 ||(dops[i].itype==COP2&&dops[i].opcode2<3))
4149788d 8392 {
8393 if(dops[i+1].rs1) {
8394 if((hr=get_reg(regs[i+1].regmap,dops[i+1].rs1))>=0)
8395 {
8396 if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
8397 {
8398 regs[i].regmap[hr]=regs[i+1].regmap[hr];
8399 regmap_pre[i+1][hr]=regs[i+1].regmap[hr];
8400 regs[i+1].regmap_entry[hr]=regs[i+1].regmap[hr];
8401 regs[i].isconst&=~(1<<hr);
8402 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
8403 constmap[i][hr]=constmap[i+1][hr];
8404 regs[i+1].wasdirty&=~(1<<hr);
8405 regs[i].dirty&=~(1<<hr);
8406 }
8407 }
8408 }
8409 if(dops[i+1].rs2) {
8410 if((hr=get_reg(regs[i+1].regmap,dops[i+1].rs2))>=0)
8411 {
8412 if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
8413 {
8414 regs[i].regmap[hr]=regs[i+1].regmap[hr];
8415 regmap_pre[i+1][hr]=regs[i+1].regmap[hr];
8416 regs[i+1].regmap_entry[hr]=regs[i+1].regmap[hr];
8417 regs[i].isconst&=~(1<<hr);
8418 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
8419 constmap[i][hr]=constmap[i+1][hr];
8420 regs[i+1].wasdirty&=~(1<<hr);
8421 regs[i].dirty&=~(1<<hr);
8422 }
8423 }
8424 }
8425 // Preload target address for load instruction (non-constant)
8426 if(dops[i+1].itype==LOAD&&dops[i+1].rs1&&get_reg(regs[i+1].regmap,dops[i+1].rs1)<0) {
a5cd72d0 8427 if((hr=get_reg_w(regs[i+1].regmap, dops[i+1].rt1))>=0)
4149788d 8428 {
8429 if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
8430 {
8431 regs[i].regmap[hr]=dops[i+1].rs1;
8432 regmap_pre[i+1][hr]=dops[i+1].rs1;
8433 regs[i+1].regmap_entry[hr]=dops[i+1].rs1;
8434 regs[i].isconst&=~(1<<hr);
8435 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
8436 constmap[i][hr]=constmap[i+1][hr];
8437 regs[i+1].wasdirty&=~(1<<hr);
8438 regs[i].dirty&=~(1<<hr);
8439 }
8440 }
8441 }
8442 // Load source into target register
8443 if(dops[i+1].use_lt1&&get_reg(regs[i+1].regmap,dops[i+1].rs1)<0) {
a5cd72d0 8444 if((hr=get_reg_w(regs[i+1].regmap, dops[i+1].rt1))>=0)
4149788d 8445 {
8446 if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
8447 {
8448 regs[i].regmap[hr]=dops[i+1].rs1;
8449 regmap_pre[i+1][hr]=dops[i+1].rs1;
8450 regs[i+1].regmap_entry[hr]=dops[i+1].rs1;
8451 regs[i].isconst&=~(1<<hr);
8452 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
8453 constmap[i][hr]=constmap[i+1][hr];
8454 regs[i+1].wasdirty&=~(1<<hr);
8455 regs[i].dirty&=~(1<<hr);
8456 }
8457 }
8458 }
8459 // Address for store instruction (non-constant)
277718fa 8460 if (dops[i+1].is_store) { // SB/SH/SW/SWC2
4149788d 8461 if(get_reg(regs[i+1].regmap,dops[i+1].rs1)<0) {
8462 hr=get_reg2(regs[i].regmap,regs[i+1].regmap,-1);
8463 if(hr<0) hr=get_reg_temp(regs[i+1].regmap);
8464 else {
8465 regs[i+1].regmap[hr]=AGEN1+((i+1)&1);
8466 regs[i+1].isconst&=~(1<<hr);
277718fa 8467 regs[i+1].dirty&=~(1<<hr);
8468 regs[i+2].wasdirty&=~(1<<hr);
4149788d 8469 }
8470 assert(hr>=0);
f0b91b78 8471 #if 0 // what is this for? double allocs $0 in ps1_rom.bin
4149788d 8472 if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
8473 {
8474 regs[i].regmap[hr]=dops[i+1].rs1;
8475 regmap_pre[i+1][hr]=dops[i+1].rs1;
8476 regs[i+1].regmap_entry[hr]=dops[i+1].rs1;
8477 regs[i].isconst&=~(1<<hr);
8478 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
8479 constmap[i][hr]=constmap[i+1][hr];
8480 regs[i+1].wasdirty&=~(1<<hr);
8481 regs[i].dirty&=~(1<<hr);
8482 }
f0b91b78 8483 #endif
4149788d 8484 }
8485 }
277718fa 8486 if (dops[i+1].itype == LOADLR || dops[i+1].opcode == 0x32) { // LWC2
4149788d 8487 if(get_reg(regs[i+1].regmap,dops[i+1].rs1)<0) {
8488 int nr;
8489 hr=get_reg(regs[i+1].regmap,FTEMP);
8490 assert(hr>=0);
8491 if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
8492 {
8493 regs[i].regmap[hr]=dops[i+1].rs1;
8494 regmap_pre[i+1][hr]=dops[i+1].rs1;
8495 regs[i+1].regmap_entry[hr]=dops[i+1].rs1;
8496 regs[i].isconst&=~(1<<hr);
8497 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
8498 constmap[i][hr]=constmap[i+1][hr];
8499 regs[i+1].wasdirty&=~(1<<hr);
8500 regs[i].dirty&=~(1<<hr);
8501 }
8502 else if((nr=get_reg2(regs[i].regmap,regs[i+1].regmap,-1))>=0)
8503 {
8504 // move it to another register
8505 regs[i+1].regmap[hr]=-1;
8506 regmap_pre[i+2][hr]=-1;
8507 regs[i+1].regmap[nr]=FTEMP;
8508 regmap_pre[i+2][nr]=FTEMP;
8509 regs[i].regmap[nr]=dops[i+1].rs1;
8510 regmap_pre[i+1][nr]=dops[i+1].rs1;
8511 regs[i+1].regmap_entry[nr]=dops[i+1].rs1;
8512 regs[i].isconst&=~(1<<nr);
8513 regs[i+1].isconst&=~(1<<nr);
8514 regs[i].dirty&=~(1<<nr);
8515 regs[i+1].wasdirty&=~(1<<nr);
8516 regs[i+1].dirty&=~(1<<nr);
8517 regs[i+2].wasdirty&=~(1<<nr);
8518 }
8519 }
8520 }
a5cd72d0 8521 if(dops[i+1].itype==LOAD||dops[i+1].itype==LOADLR||dops[i+1].itype==STORE||dops[i+1].itype==STORELR/*||dops[i+1].itype==C2LS*/) {
4149788d 8522 hr = -1;
8523 if(dops[i+1].itype==LOAD)
a5cd72d0 8524 hr=get_reg_w(regs[i+1].regmap, dops[i+1].rt1);
277718fa 8525 if (dops[i+1].itype == LOADLR || dops[i+1].opcode == 0x32) // LWC2
4149788d 8526 hr=get_reg(regs[i+1].regmap,FTEMP);
277718fa 8527 if (dops[i+1].is_store) {
4149788d 8528 hr=get_reg(regs[i+1].regmap,AGEN1+((i+1)&1));
8529 if(hr<0) hr=get_reg_temp(regs[i+1].regmap);
8530 }
8531 if(hr>=0&&regs[i].regmap[hr]<0) {
8532 int rs=get_reg(regs[i+1].regmap,dops[i+1].rs1);
8533 if(rs>=0&&((regs[i+1].wasconst>>rs)&1)) {
8534 regs[i].regmap[hr]=AGEN1+((i+1)&1);
8535 regmap_pre[i+1][hr]=AGEN1+((i+1)&1);
8536 regs[i+1].regmap_entry[hr]=AGEN1+((i+1)&1);
8537 regs[i].isconst&=~(1<<hr);
8538 regs[i+1].wasdirty&=~(1<<hr);
8539 regs[i].dirty&=~(1<<hr);
8540 }
b372a952 8541 }
8542 }
57871462 8543 }
8544 }
4149788d 8545 }
8546 }
8547}
8548
8549// Write back dirty registers as soon as we will no longer modify them,
8550// so that we don't end up with lots of writes at the branches.
8551static noinline void pass6_clean_registers(int istart, int iend, int wr)
8552{
53358c1d 8553 static u_int wont_dirty[MAXBLOCK];
8554 static u_int will_dirty[MAXBLOCK];
4149788d 8555 int i;
8556 int r;
8557 u_int will_dirty_i,will_dirty_next,temp_will_dirty;
8558 u_int wont_dirty_i,wont_dirty_next,temp_wont_dirty;
8559 if(iend==slen-1) {
8560 will_dirty_i=will_dirty_next=0;
8561 wont_dirty_i=wont_dirty_next=0;
8562 }else{
8563 will_dirty_i=will_dirty_next=will_dirty[iend+1];
8564 wont_dirty_i=wont_dirty_next=wont_dirty[iend+1];
8565 }
8566 for (i=iend;i>=istart;i--)
8567 {
8568 signed char rregmap_i[RRMAP_SIZE];
8569 u_int hr_candirty = 0;
8570 assert(HOST_REGS < 32);
8571 make_rregs(regs[i].regmap, rregmap_i, &hr_candirty);
8572 __builtin_prefetch(regs[i-1].regmap);
8573 if(dops[i].is_jump)
8574 {
8575 signed char branch_rregmap_i[RRMAP_SIZE];
8576 u_int branch_hr_candirty = 0;
8577 make_rregs(branch_regs[i].regmap, branch_rregmap_i, &branch_hr_candirty);
277718fa 8578 if(cinfo[i].ba<start || cinfo[i].ba>=(start+slen*4))
4149788d 8579 {
8580 // Branch out of this block, flush all regs
8581 will_dirty_i = 0;
8582 will_dirty_i |= 1u << (get_rreg(branch_rregmap_i, dops[i].rt1) & 31);
8583 will_dirty_i |= 1u << (get_rreg(branch_rregmap_i, dops[i].rt2) & 31);
8584 will_dirty_i |= 1u << (get_rreg(branch_rregmap_i, dops[i+1].rt1) & 31);
8585 will_dirty_i |= 1u << (get_rreg(branch_rregmap_i, dops[i+1].rt2) & 31);
8586 will_dirty_i |= 1u << (get_rreg(branch_rregmap_i, CCREG) & 31);
8587 will_dirty_i &= branch_hr_candirty;
8588 if (dops[i].is_ujump)
8589 {
8590 // Unconditional branch
8591 wont_dirty_i = 0;
8592 // Merge in delay slot (will dirty)
8593 will_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i].rt1) & 31);
8594 will_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i].rt2) & 31);
8595 will_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i+1].rt1) & 31);
8596 will_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i+1].rt2) & 31);
8597 will_dirty_i |= 1u << (get_rreg(rregmap_i, CCREG) & 31);
8598 will_dirty_i &= hr_candirty;
57871462 8599 }
4149788d 8600 else
8601 {
8602 // Conditional branch
8603 wont_dirty_i = wont_dirty_next;
8604 // Merge in delay slot (will dirty)
8605 // (the original code had no explanation why these 2 are commented out)
8606 //will_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i].rt1) & 31);
8607 //will_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i].rt2) & 31);
8608 will_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i+1].rt1) & 31);
8609 will_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i+1].rt2) & 31);
8610 will_dirty_i |= 1u << (get_rreg(rregmap_i, CCREG) & 31);
8611 will_dirty_i &= hr_candirty;
8612 }
8613 // Merge in delay slot (wont dirty)
8614 wont_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i].rt1) & 31);
8615 wont_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i].rt2) & 31);
8616 wont_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i+1].rt1) & 31);
8617 wont_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i+1].rt2) & 31);
8618 wont_dirty_i |= 1u << (get_rreg(rregmap_i, CCREG) & 31);
8619 wont_dirty_i |= 1u << (get_rreg(branch_rregmap_i, dops[i].rt1) & 31);
8620 wont_dirty_i |= 1u << (get_rreg(branch_rregmap_i, dops[i].rt2) & 31);
8621 wont_dirty_i |= 1u << (get_rreg(branch_rregmap_i, dops[i+1].rt1) & 31);
8622 wont_dirty_i |= 1u << (get_rreg(branch_rregmap_i, dops[i+1].rt2) & 31);
8623 wont_dirty_i |= 1u << (get_rreg(branch_rregmap_i, CCREG) & 31);
8624 wont_dirty_i &= ~(1u << 31);
8625 if(wr) {
8626 #ifndef DESTRUCTIVE_WRITEBACK
8627 branch_regs[i].dirty&=wont_dirty_i;
8628 #endif
8629 branch_regs[i].dirty|=will_dirty_i;
8630 }
8631 }
8632 else
8633 {
8634 // Internal branch
277718fa 8635 if(cinfo[i].ba<=start+i*4) {
4149788d 8636 // Backward branch
8637 if (dops[i].is_ujump)
8638 {
8639 // Unconditional branch
8640 temp_will_dirty=0;
8641 temp_wont_dirty=0;
8642 // Merge in delay slot (will dirty)
8643 temp_will_dirty |= 1u << (get_rreg(branch_rregmap_i, dops[i].rt1) & 31);
8644 temp_will_dirty |= 1u << (get_rreg(branch_rregmap_i, dops[i].rt2) & 31);
8645 temp_will_dirty |= 1u << (get_rreg(branch_rregmap_i, dops[i+1].rt1) & 31);
8646 temp_will_dirty |= 1u << (get_rreg(branch_rregmap_i, dops[i+1].rt2) & 31);
8647 temp_will_dirty |= 1u << (get_rreg(branch_rregmap_i, CCREG) & 31);
8648 temp_will_dirty &= branch_hr_candirty;
8649 temp_will_dirty |= 1u << (get_rreg(rregmap_i, dops[i].rt1) & 31);
8650 temp_will_dirty |= 1u << (get_rreg(rregmap_i, dops[i].rt2) & 31);
8651 temp_will_dirty |= 1u << (get_rreg(rregmap_i, dops[i+1].rt1) & 31);
8652 temp_will_dirty |= 1u << (get_rreg(rregmap_i, dops[i+1].rt2) & 31);
8653 temp_will_dirty |= 1u << (get_rreg(rregmap_i, CCREG) & 31);
8654 temp_will_dirty &= hr_candirty;
8655 } else {
8656 // Conditional branch (not taken case)
8657 temp_will_dirty=will_dirty_next;
8658 temp_wont_dirty=wont_dirty_next;
8659 // Merge in delay slot (will dirty)
8660 temp_will_dirty |= 1u << (get_rreg(branch_rregmap_i, dops[i].rt1) & 31);
8661 temp_will_dirty |= 1u << (get_rreg(branch_rregmap_i, dops[i].rt2) & 31);
8662 temp_will_dirty |= 1u << (get_rreg(branch_rregmap_i, dops[i+1].rt1) & 31);
8663 temp_will_dirty |= 1u << (get_rreg(branch_rregmap_i, dops[i+1].rt2) & 31);
8664 temp_will_dirty |= 1u << (get_rreg(branch_rregmap_i, CCREG) & 31);
8665 temp_will_dirty &= branch_hr_candirty;
8666 //temp_will_dirty |= 1u << (get_rreg(rregmap_i, dops[i].rt1) & 31);
8667 //temp_will_dirty |= 1u << (get_rreg(rregmap_i, dops[i].rt2) & 31);
8668 temp_will_dirty |= 1u << (get_rreg(rregmap_i, dops[i+1].rt1) & 31);
8669 temp_will_dirty |= 1u << (get_rreg(rregmap_i, dops[i+1].rt2) & 31);
8670 temp_will_dirty |= 1u << (get_rreg(rregmap_i, CCREG) & 31);
8671 temp_will_dirty &= hr_candirty;
8672 }
8673 // Merge in delay slot (wont dirty)
8674 temp_wont_dirty |= 1u << (get_rreg(rregmap_i, dops[i].rt1) & 31);
8675 temp_wont_dirty |= 1u << (get_rreg(rregmap_i, dops[i].rt2) & 31);
8676 temp_wont_dirty |= 1u << (get_rreg(rregmap_i, dops[i+1].rt1) & 31);
8677 temp_wont_dirty |= 1u << (get_rreg(rregmap_i, dops[i+1].rt2) & 31);
8678 temp_wont_dirty |= 1u << (get_rreg(rregmap_i, CCREG) & 31);
8679 temp_wont_dirty |= 1u << (get_rreg(branch_rregmap_i, dops[i].rt1) & 31);
8680 temp_wont_dirty |= 1u << (get_rreg(branch_rregmap_i, dops[i].rt2) & 31);
8681 temp_wont_dirty |= 1u << (get_rreg(branch_rregmap_i, dops[i+1].rt1) & 31);
8682 temp_wont_dirty |= 1u << (get_rreg(branch_rregmap_i, dops[i+1].rt2) & 31);
8683 temp_wont_dirty |= 1u << (get_rreg(branch_rregmap_i, CCREG) & 31);
8684 temp_wont_dirty &= ~(1u << 31);
8685 // Deal with changed mappings
8686 if(i<iend) {
8687 for(r=0;r<HOST_REGS;r++) {
8688 if(r!=EXCLUDE_REG) {
8689 if(regs[i].regmap[r]!=regmap_pre[i][r]) {
8690 temp_will_dirty&=~(1<<r);
8691 temp_wont_dirty&=~(1<<r);
8692 if(regmap_pre[i][r]>0 && regmap_pre[i][r]<34) {
8693 temp_will_dirty|=((unneeded_reg[i]>>regmap_pre[i][r])&1)<<r;
8694 temp_wont_dirty|=((unneeded_reg[i]>>regmap_pre[i][r])&1)<<r;
8695 } else {
8696 temp_will_dirty|=1<<r;
8697 temp_wont_dirty|=1<<r;
8698 }
8699 }
8700 }
8701 }
8702 }
8703 if(wr) {
8704 will_dirty[i]=temp_will_dirty;
8705 wont_dirty[i]=temp_wont_dirty;
277718fa 8706 pass6_clean_registers((cinfo[i].ba-start)>>2,i-1,0);
4149788d 8707 }else{
8708 // Limit recursion. It can take an excessive amount
8709 // of time if there are a lot of nested loops.
277718fa 8710 will_dirty[(cinfo[i].ba-start)>>2]=0;
8711 wont_dirty[(cinfo[i].ba-start)>>2]=-1;
57871462 8712 }
57871462 8713 }
4149788d 8714 /*else*/ if(1)
57871462 8715 {
4149788d 8716 if (dops[i].is_ujump)
8717 {
8718 // Unconditional branch
8719 will_dirty_i=0;
8720 wont_dirty_i=0;
277718fa 8721 //if(cinfo[i].ba>start+i*4) { // Disable recursion (for debugging)
4149788d 8722 for(r=0;r<HOST_REGS;r++) {
8723 if(r!=EXCLUDE_REG) {
277718fa 8724 if(branch_regs[i].regmap[r]==regs[(cinfo[i].ba-start)>>2].regmap_entry[r]) {
8725 will_dirty_i|=will_dirty[(cinfo[i].ba-start)>>2]&(1<<r);
8726 wont_dirty_i|=wont_dirty[(cinfo[i].ba-start)>>2]&(1<<r);
4149788d 8727 }
8728 if(branch_regs[i].regmap[r]>=0) {
277718fa 8729 will_dirty_i|=((unneeded_reg[(cinfo[i].ba-start)>>2]>>branch_regs[i].regmap[r])&1)<<r;
8730 wont_dirty_i|=((unneeded_reg[(cinfo[i].ba-start)>>2]>>branch_regs[i].regmap[r])&1)<<r;
4149788d 8731 }
8732 }
57871462 8733 }
4149788d 8734 //}
8735 // Merge in delay slot
8736 will_dirty_i |= 1u << (get_rreg(branch_rregmap_i, dops[i].rt1) & 31);
8737 will_dirty_i |= 1u << (get_rreg(branch_rregmap_i, dops[i].rt2) & 31);
8738 will_dirty_i |= 1u << (get_rreg(branch_rregmap_i, dops[i+1].rt1) & 31);
8739 will_dirty_i |= 1u << (get_rreg(branch_rregmap_i, dops[i+1].rt2) & 31);
8740 will_dirty_i |= 1u << (get_rreg(branch_rregmap_i, CCREG) & 31);
8741 will_dirty_i &= branch_hr_candirty;
8742 will_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i].rt1) & 31);
8743 will_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i].rt2) & 31);
8744 will_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i+1].rt1) & 31);
8745 will_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i+1].rt2) & 31);
8746 will_dirty_i |= 1u << (get_rreg(rregmap_i, CCREG) & 31);
8747 will_dirty_i &= hr_candirty;
8748 } else {
8749 // Conditional branch
8750 will_dirty_i=will_dirty_next;
8751 wont_dirty_i=wont_dirty_next;
277718fa 8752 //if(cinfo[i].ba>start+i*4) // Disable recursion (for debugging)
4149788d 8753 for(r=0;r<HOST_REGS;r++) {
8754 if(r!=EXCLUDE_REG) {
8755 signed char target_reg=branch_regs[i].regmap[r];
277718fa 8756 if(target_reg==regs[(cinfo[i].ba-start)>>2].regmap_entry[r]) {
8757 will_dirty_i&=will_dirty[(cinfo[i].ba-start)>>2]&(1<<r);
8758 wont_dirty_i|=wont_dirty[(cinfo[i].ba-start)>>2]&(1<<r);
4149788d 8759 }
8760 else if(target_reg>=0) {
277718fa 8761 will_dirty_i&=((unneeded_reg[(cinfo[i].ba-start)>>2]>>target_reg)&1)<<r;
8762 wont_dirty_i|=((unneeded_reg[(cinfo[i].ba-start)>>2]>>target_reg)&1)<<r;
4149788d 8763 }
8764 }
57871462 8765 }
4149788d 8766 // Merge in delay slot
8767 will_dirty_i |= 1u << (get_rreg(branch_rregmap_i, dops[i].rt1) & 31);
8768 will_dirty_i |= 1u << (get_rreg(branch_rregmap_i, dops[i].rt2) & 31);
8769 will_dirty_i |= 1u << (get_rreg(branch_rregmap_i, dops[i+1].rt1) & 31);
8770 will_dirty_i |= 1u << (get_rreg(branch_rregmap_i, dops[i+1].rt2) & 31);
8771 will_dirty_i |= 1u << (get_rreg(branch_rregmap_i, CCREG) & 31);
8772 will_dirty_i &= branch_hr_candirty;
8773 //will_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i].rt1) & 31);
8774 //will_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i].rt2) & 31);
8775 will_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i+1].rt1) & 31);
8776 will_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i+1].rt2) & 31);
8777 will_dirty_i |= 1u << (get_rreg(rregmap_i, CCREG) & 31);
8778 will_dirty_i &= hr_candirty;
57871462 8779 }
4149788d 8780 // Merge in delay slot (won't dirty)
8781 wont_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i].rt1) & 31);
8782 wont_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i].rt2) & 31);
8783 wont_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i+1].rt1) & 31);
8784 wont_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i+1].rt2) & 31);
8785 wont_dirty_i |= 1u << (get_rreg(rregmap_i, CCREG) & 31);
8786 wont_dirty_i |= 1u << (get_rreg(branch_rregmap_i, dops[i].rt1) & 31);
8787 wont_dirty_i |= 1u << (get_rreg(branch_rregmap_i, dops[i].rt2) & 31);
8788 wont_dirty_i |= 1u << (get_rreg(branch_rregmap_i, dops[i+1].rt1) & 31);
8789 wont_dirty_i |= 1u << (get_rreg(branch_rregmap_i, dops[i+1].rt2) & 31);
8790 wont_dirty_i |= 1u << (get_rreg(branch_rregmap_i, CCREG) & 31);
8791 wont_dirty_i &= ~(1u << 31);
8792 if(wr) {
8793 #ifndef DESTRUCTIVE_WRITEBACK
8794 branch_regs[i].dirty&=wont_dirty_i;
8795 #endif
8796 branch_regs[i].dirty|=will_dirty_i;
57871462 8797 }
8798 }
8799 }
57871462 8800 }
277718fa 8801 else if (dops[i].is_exception)
4149788d 8802 {
277718fa 8803 // SYSCALL instruction, etc
4149788d 8804 will_dirty_i=0;
8805 wont_dirty_i=0;
8806 }
8807 will_dirty_next=will_dirty_i;
8808 wont_dirty_next=wont_dirty_i;
8809 will_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i].rt1) & 31);
8810 will_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i].rt2) & 31);
8811 will_dirty_i |= 1u << (get_rreg(rregmap_i, CCREG) & 31);
8812 will_dirty_i &= hr_candirty;
8813 wont_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i].rt1) & 31);
8814 wont_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i].rt2) & 31);
8815 wont_dirty_i |= 1u << (get_rreg(rregmap_i, CCREG) & 31);
8816 wont_dirty_i &= ~(1u << 31);
8817 if (i > istart && !dops[i].is_jump) {
8818 // Don't store a register immediately after writing it,
8819 // may prevent dual-issue.
8820 wont_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i-1].rt1) & 31);
8821 wont_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i-1].rt2) & 31);
8822 }
8823 // Save it
8824 will_dirty[i]=will_dirty_i;
8825 wont_dirty[i]=wont_dirty_i;
8826 // Mark registers that won't be dirtied as not dirty
8827 if(wr) {
8828 regs[i].dirty|=will_dirty_i;
8829 #ifndef DESTRUCTIVE_WRITEBACK
8830 regs[i].dirty&=wont_dirty_i;
8831 if(dops[i].is_jump)
57871462 8832 {
4149788d 8833 if (i < iend-1 && !dops[i].is_ujump) {
8834 for(r=0;r<HOST_REGS;r++) {
8835 if(r!=EXCLUDE_REG) {
8836 if(regs[i].regmap[r]==regmap_pre[i+2][r]) {
8837 regs[i+2].wasdirty&=wont_dirty_i|~(1<<r);
8838 }else {/*printf("i: %x (%d) mismatch(+2): %d\n",start+i*4,i,r);assert(!((wont_dirty_i>>r)&1));*/}
57871462 8839 }
8840 }
8841 }
4149788d 8842 }
8843 else
8844 {
8845 if(i<iend) {
8846 for(r=0;r<HOST_REGS;r++) {
8847 if(r!=EXCLUDE_REG) {
8848 if(regs[i].regmap[r]==regmap_pre[i+1][r]) {
8849 regs[i+1].wasdirty&=wont_dirty_i|~(1<<r);
8850 }else {/*printf("i: %x (%d) mismatch(+1): %d\n",start+i*4,i,r);assert(!((wont_dirty_i>>r)&1));*/}
57871462 8851 }
8852 }
8853 }
4149788d 8854 }
8855 #endif
8856 }
8857 // Deal with changed mappings
8858 temp_will_dirty=will_dirty_i;
8859 temp_wont_dirty=wont_dirty_i;
8860 for(r=0;r<HOST_REGS;r++) {
8861 if(r!=EXCLUDE_REG) {
8862 int nr;
8863 if(regs[i].regmap[r]==regmap_pre[i][r]) {
8864 if(wr) {
8865 #ifndef DESTRUCTIVE_WRITEBACK
8866 regs[i].wasdirty&=wont_dirty_i|~(1<<r);
8867 #endif
8868 regs[i].wasdirty|=will_dirty_i&(1<<r);
57871462 8869 }
4149788d 8870 }
8871 else if(regmap_pre[i][r]>=0&&(nr=get_rreg(rregmap_i,regmap_pre[i][r]))>=0) {
8872 // Register moved to a different register
8873 will_dirty_i&=~(1<<r);
8874 wont_dirty_i&=~(1<<r);
8875 will_dirty_i|=((temp_will_dirty>>nr)&1)<<r;
8876 wont_dirty_i|=((temp_wont_dirty>>nr)&1)<<r;
8877 if(wr) {
8878 #ifndef DESTRUCTIVE_WRITEBACK
8879 regs[i].wasdirty&=wont_dirty_i|~(1<<r);
8880 #endif
8881 regs[i].wasdirty|=will_dirty_i&(1<<r);
8882 }
8883 }
8884 else {
8885 will_dirty_i&=~(1<<r);
8886 wont_dirty_i&=~(1<<r);
8887 if(regmap_pre[i][r]>0 && regmap_pre[i][r]<34) {
8888 will_dirty_i|=((unneeded_reg[i]>>regmap_pre[i][r])&1)<<r;
8889 wont_dirty_i|=((unneeded_reg[i]>>regmap_pre[i][r])&1)<<r;
8890 } else {
8891 wont_dirty_i|=1<<r;
8892 /*printf("i: %x (%d) mismatch: %d\n",start+i*4,i,r);assert(!((will_dirty>>r)&1));*/
57871462 8893 }
8894 }
8895 }
8896 }
8897 }
4149788d 8898}
8899
8900static noinline void pass10_expire_blocks(void)
8901{
93c0345b 8902 u_int step = MAX_OUTPUT_BLOCK_SIZE / PAGE_COUNT / 2;
8903 // not sizeof(ndrc->translation_cache) due to vita hack
8904 u_int step_mask = ((1u << TARGET_SIZE_2) - 1u) & ~(step - 1u);
8905 u_int end = (out - ndrc->translation_cache + EXPIRITY_OFFSET) & step_mask;
8906 u_int base_shift = __builtin_ctz(MAX_OUTPUT_BLOCK_SIZE);
8907 int hit;
8908
8909 for (; expirep != end; expirep = ((expirep + step) & step_mask))
4149788d 8910 {
93c0345b 8911 u_int base_offs = expirep & ~(MAX_OUTPUT_BLOCK_SIZE - 1);
8912 u_int block_i = expirep / step & (PAGE_COUNT - 1);
8913 u_int phase = (expirep >> (base_shift - 1)) & 1u;
8914 if (!(expirep & (MAX_OUTPUT_BLOCK_SIZE / 2 - 1))) {
9b495f6e 8915 inv_debug("EXP: base_offs %x/%lx phase %u\n", base_offs,
8916 (long)(out - ndrc->translation_cache), phase);
93c0345b 8917 }
8918
8919 if (!phase) {
8920 hit = blocks_remove_matching_addrs(&blocks[block_i], base_offs, base_shift);
8921 if (hit) {
8922 do_clear_cache();
04714958 8923 mini_ht_clear();
93c0345b 8924 }
4149788d 8925 }
93c0345b 8926 else
b7ad2f2c 8927 unlink_jumps_tc_range(jumps[block_i], base_offs, base_shift);
4149788d 8928 }
8929}
8930
104df9d3 8931static struct block_info *new_block_info(u_int start, u_int len,
8932 const void *source, const void *copy, u_char *beginning, u_short jump_in_count)
8933{
8934 struct block_info **b_pptr;
8935 struct block_info *block;
8936 u_int page = get_page(start);
8937
8938 block = malloc(sizeof(*block) + jump_in_count * sizeof(block->jump_in[0]));
8939 assert(block);
8940 assert(jump_in_count > 0);
8941 block->source = source;
8942 block->copy = copy;
8943 block->start = start;
8944 block->len = len;
8945 block->reg_sv_flags = 0;
8946 block->tc_offs = beginning - ndrc->translation_cache;
8947 //block->tc_len = out - beginning;
8948 block->is_dirty = 0;
3280e616 8949 block->inv_near_misses = 0;
104df9d3 8950 block->jump_in_cnt = jump_in_count;
8951
93c0345b 8952 // insert sorted by start mirror-unmasked vaddr
104df9d3 8953 for (b_pptr = &blocks[page]; ; b_pptr = &((*b_pptr)->next)) {
8954 if (*b_pptr == NULL || (*b_pptr)->start >= start) {
8955 block->next = *b_pptr;
8956 *b_pptr = block;
8957 break;
8958 }
8959 }
8960 stat_inc(stat_blocks);
8961 return block;
8962}
8963
8964static int new_recompile_block(u_int addr)
4149788d 8965{
8966 u_int pagelimit = 0;
8967 u_int state_rflags = 0;
8968 int i;
8969
8970 assem_debug("NOTCOMPILED: addr = %x -> %p\n", addr, out);
8971
a5cd72d0 8972 if (addr & 3) {
8973 if (addr != hack_addr) {
8974 SysPrintf("game crash @%08x, ra=%08x\n", addr, psxRegs.GPR.n.ra);
8975 hack_addr = addr;
8976 }
8977 return -1;
8978 }
8979
4149788d 8980 // this is just for speculation
8981 for (i = 1; i < 32; i++) {
8982 if ((psxRegs.GPR.r[i] & 0xffff0000) == 0x1f800000)
8983 state_rflags |= 1 << i;
8984 }
8985
a5cd72d0 8986 start = addr;
4149788d 8987 new_dynarec_did_compile=1;
8988 if (Config.HLE && start == 0x80001000) // hlecall
8989 {
104df9d3 8990 void *beginning = start_block();
4149788d 8991
4149788d 8992 emit_movimm(start,0);
8993 emit_writeword(0,&pcaddr);
8994 emit_far_jump(new_dyna_leave);
8995 literal_pool(0);
8996 end_block(beginning);
104df9d3 8997 struct block_info *block = new_block_info(start, 4, NULL, NULL, beginning, 1);
8998 block->jump_in[0].vaddr = start;
8999 block->jump_in[0].addr = beginning;
4149788d 9000 return 0;
9001 }
9002 else if (f1_hack && hack_addr == 0) {
9003 void *beginning = start_block();
4149788d 9004 emit_movimm(start, 0);
9005 emit_writeword(0, &hack_addr);
9006 emit_readword(&psxRegs.GPR.n.sp, 0);
9007 emit_readptr(&mem_rtab, 1);
9008 emit_shrimm(0, 12, 2);
9009 emit_readptr_dualindexedx_ptrlen(1, 2, 1);
9010 emit_addimm(0, 0x18, 0);
9011 emit_adds_ptr(1, 1, 1);
9012 emit_ldr_dualindexed(1, 0, 0);
9013 emit_writeword(0, &psxRegs.GPR.r[26]); // lw k0, 0x18(sp)
104df9d3 9014 emit_far_call(ndrc_get_addr_ht);
4149788d 9015 emit_jmpreg(0); // jr k0
9016 literal_pool(0);
9017 end_block(beginning);
9018
104df9d3 9019 struct block_info *block = new_block_info(start, 4, NULL, NULL, beginning, 1);
9020 block->jump_in[0].vaddr = start;
9021 block->jump_in[0].addr = beginning;
4149788d 9022 SysPrintf("F1 hack to %08x\n", start);
9023 return 0;
9024 }
9025
42eb665e 9026 cycle_multiplier_active = get_cycle_multiplier();
4149788d 9027
9028 source = get_source_start(start, &pagelimit);
9029 if (source == NULL) {
9030 if (addr != hack_addr) {
42eb665e 9031 SysPrintf("Compile at bogus memory address: %08x, ra=%x\n",
9032 addr, psxRegs.GPR.n.ra);
4149788d 9033 hack_addr = addr;
9034 }
9035 //abort();
9036 return -1;
9037 }
9038
9039 /* Pass 1: disassemble */
9040 /* Pass 2: register dependencies, branch targets */
9041 /* Pass 3: register allocation */
9042 /* Pass 4: branch dependencies */
9043 /* Pass 5: pre-alloc */
9044 /* Pass 6: optimize clean/dirty state */
9045 /* Pass 7: flag 32-bit registers */
9046 /* Pass 8: assembly */
9047 /* Pass 9: linker */
9048 /* Pass 10: garbage collection / free memory */
9049
9050 /* Pass 1 disassembly */
9051
9052 pass1_disassemble(pagelimit);
9053
9054 int clear_hack_addr = apply_hacks();
9055
9056 /* Pass 2 - Register dependencies and branch targets */
9057
9058 pass2_unneeded_regs(0,slen-1,0);
9059
f9e9616e 9060 pass2a_unneeded_other();
9061
4149788d 9062 /* Pass 3 - Register allocation */
9063
9064 pass3_register_alloc(addr);
9065
9066 /* Pass 4 - Cull unused host registers */
9067
9068 pass4_cull_unused_regs();
9069
9070 /* Pass 5 - Pre-allocate registers */
9071
9072 pass5a_preallocate1();
9073 pass5b_preallocate2();
9f51b4b9 9074
57871462 9075 /* Pass 6 - Optimize clean/dirty state */
4149788d 9076 pass6_clean_registers(0, slen-1, 1);
9f51b4b9 9077
33a1eda1 9078 /* Pass 7 */
04fd948a 9079 for (i=slen-1;i>=0;i--)
9080 {
cf95b4f0 9081 if(dops[i].itype==CJUMP||dops[i].itype==SJUMP)
04fd948a 9082 {
9083 // Conditional branch
9084 if((source[i]>>16)!=0x1000&&i<slen-2) {
9085 // Mark this address as a branch target since it may be called
9086 // upon return from interrupt
cf95b4f0 9087 dops[i+2].bt=1;
04fd948a 9088 }
9089 }
9090 }
57871462 9091
57871462 9092 /* Pass 8 - Assembly */
9093 linkcount=0;stubcount=0;
4149788d 9094 is_delayslot=0;
57871462 9095 u_int dirty_pre=0;
d148d265 9096 void *beginning=start_block();
df4dc2b1 9097 void *instr_addr0_override = NULL;
4bdc30ab 9098 int ds = 0;
9ad4d757 9099
65722e04 9100 if ((Config.HLE && start == 0x80000080) || start == 0x80030000) {
df4dc2b1 9101 instr_addr0_override = out;
65722e04 9102 emit_movimm(start, 0);
9103 if (start == 0x80030000) {
9104 // for BiosBootBypass() to work
9105 // io address var abused as a "already been here" flag
9106 emit_readword(&address, 1);
9107 emit_writeword(0, &pcaddr);
9108 emit_writeword(0, &address);
9109 emit_cmp(0, 1);
9110 }
9111 else {
9112 emit_readword(&psxRegs.cpuInRecursion, 1);
9113 emit_writeword(0, &pcaddr);
9114 emit_test(1, 1);
9115 }
3968e69e 9116 #ifdef __aarch64__
9117 emit_jeq(out + 4*2);
2a014d73 9118 emit_far_jump(new_dyna_leave);
3968e69e 9119 #else
643aeae3 9120 emit_jne(new_dyna_leave);
3968e69e 9121 #endif
9ad4d757 9122 }
57871462 9123 for(i=0;i<slen;i++)
9124 {
9de8a0c3 9125 __builtin_prefetch(regs[i+1].regmap);
670c0f22 9126 check_regmap(regmap_pre[i]);
9127 check_regmap(regs[i].regmap_entry);
9128 check_regmap(regs[i].regmap);
57871462 9129 //if(ds) printf("ds: ");
4600ba03 9130 disassemble_inst(i);
57871462 9131 if(ds) {
9132 ds=0; // Skip delay slot
cf95b4f0 9133 if(dops[i].bt) assem_debug("OOPS - branch into delay slot\n");
df4dc2b1 9134 instr_addr[i] = NULL;
57871462 9135 } else {
ffb0b9e0 9136 speculate_register_values(i);
57871462 9137 #ifndef DESTRUCTIVE_WRITEBACK
fe807a8a 9138 if (i < 2 || !dops[i-2].is_ujump)
57871462 9139 {
ad49de89 9140 wb_valid(regmap_pre[i],regs[i].regmap_entry,dirty_pre,regs[i].wasdirty,unneeded_reg[i]);
57871462 9141 }
fe807a8a 9142 if((dops[i].itype==CJUMP||dops[i].itype==SJUMP)) {
f776eb14 9143 dirty_pre=branch_regs[i].dirty;
9144 }else{
f776eb14 9145 dirty_pre=regs[i].dirty;
9146 }
57871462 9147 #endif
9148 // write back
fe807a8a 9149 if (i < 2 || !dops[i-2].is_ujump)
57871462 9150 {
ad49de89 9151 wb_invalidate(regmap_pre[i],regs[i].regmap_entry,regs[i].wasdirty,unneeded_reg[i]);
57871462 9152 loop_preload(regmap_pre[i],regs[i].regmap_entry);
9153 }
9154 // branch target entry point
df4dc2b1 9155 instr_addr[i] = out;
57871462 9156 assem_debug("<->\n");
277718fa 9157 drc_dbg_emit_do_cmp(i, cinfo[i].ccadj);
7f94b097 9158 if (clear_hack_addr) {
9159 emit_movimm(0, 0);
9160 emit_writeword(0, &hack_addr);
9161 clear_hack_addr = 0;
9162 }
dd114d7d 9163
57871462 9164 // load regs
9165 if(regs[i].regmap_entry[HOST_CCREG]==CCREG&&regs[i].regmap[HOST_CCREG]!=CCREG)
ad49de89 9166 wb_register(CCREG,regs[i].regmap_entry,regs[i].wasdirty);
cf95b4f0 9167 load_regs(regs[i].regmap_entry,regs[i].regmap,dops[i].rs1,dops[i].rs2);
57871462 9168 address_generation(i,&regs[i],regs[i].regmap_entry);
ad49de89 9169 load_consts(regmap_pre[i],regs[i].regmap,i);
fe807a8a 9170 if(dops[i].is_jump)
57871462 9171 {
9172 // Load the delay slot registers if necessary
cf95b4f0 9173 if(dops[i+1].rs1!=dops[i].rs1&&dops[i+1].rs1!=dops[i].rs2&&(dops[i+1].rs1!=dops[i].rt1||dops[i].rt1==0))
9174 load_regs(regs[i].regmap_entry,regs[i].regmap,dops[i+1].rs1,dops[i+1].rs1);
9175 if(dops[i+1].rs2!=dops[i+1].rs1&&dops[i+1].rs2!=dops[i].rs1&&dops[i+1].rs2!=dops[i].rs2&&(dops[i+1].rs2!=dops[i].rt1||dops[i].rt1==0))
9176 load_regs(regs[i].regmap_entry,regs[i].regmap,dops[i+1].rs2,dops[i+1].rs2);
37387d8b 9177 if (ram_offset && (dops[i+1].is_load || dops[i+1].is_store))
53358c1d 9178 load_reg(regs[i].regmap_entry,regs[i].regmap,ROREG);
37387d8b 9179 if (dops[i+1].is_store)
53358c1d 9180 load_reg(regs[i].regmap_entry,regs[i].regmap,INVCP);
57871462 9181 }
9182 else if(i+1<slen)
9183 {
9184 // Preload registers for following instruction
cf95b4f0 9185 if(dops[i+1].rs1!=dops[i].rs1&&dops[i+1].rs1!=dops[i].rs2)
9186 if(dops[i+1].rs1!=dops[i].rt1&&dops[i+1].rs1!=dops[i].rt2)
9187 load_regs(regs[i].regmap_entry,regs[i].regmap,dops[i+1].rs1,dops[i+1].rs1);
9188 if(dops[i+1].rs2!=dops[i+1].rs1&&dops[i+1].rs2!=dops[i].rs1&&dops[i+1].rs2!=dops[i].rs2)
9189 if(dops[i+1].rs2!=dops[i].rt1&&dops[i+1].rs2!=dops[i].rt2)
9190 load_regs(regs[i].regmap_entry,regs[i].regmap,dops[i+1].rs2,dops[i+1].rs2);
57871462 9191 }
9192 // TODO: if(is_ooo(i)) address_generation(i+1);
9a3ccfeb 9193 if (!dops[i].is_jump || dops[i].itype == CJUMP)
53358c1d 9194 load_reg(regs[i].regmap_entry,regs[i].regmap,CCREG);
37387d8b 9195 if (ram_offset && (dops[i].is_load || dops[i].is_store))
53358c1d 9196 load_reg(regs[i].regmap_entry,regs[i].regmap,ROREG);
37387d8b 9197 if (dops[i].is_store)
53358c1d 9198 load_reg(regs[i].regmap_entry,regs[i].regmap,INVCP);
2330734f 9199
277718fa 9200 ds = assemble(i, &regs[i], cinfo[i].ccadj);
2330734f 9201
4f13a577 9202 drc_dbg_emit_wb_dirtys(i, &regs[i]);
fe807a8a 9203 if (dops[i].is_ujump)
57871462 9204 literal_pool(1024);
9205 else
9206 literal_pool_jumpover(256);
9207 }
9208 }
3d680478 9209
9210 assert(slen > 0);
cf95b4f0 9211 if (slen > 0 && dops[slen-1].itype == INTCALL) {
3d680478 9212 // no ending needed for this block since INTCALL never returns
9213 }
57871462 9214 // If the block did not end with an unconditional branch,
9215 // add a jump to the next instruction.
3d680478 9216 else if (i > 1) {
4bdc30ab 9217 if (!dops[i-2].is_ujump) {
fe807a8a 9218 assert(!dops[i-1].is_jump);
57871462 9219 assert(i==slen);
cf95b4f0 9220 if(dops[i-2].itype!=CJUMP&&dops[i-2].itype!=SJUMP) {
ad49de89 9221 store_regs_bt(regs[i-1].regmap,regs[i-1].dirty,start+i*4);
57871462 9222 if(regs[i-1].regmap[HOST_CCREG]!=CCREG)
9223 emit_loadreg(CCREG,HOST_CCREG);
277718fa 9224 emit_addimm(HOST_CCREG, cinfo[i-1].ccadj + CLOCK_ADJUST(1), HOST_CCREG);
57871462 9225 }
fe807a8a 9226 else
57871462 9227 {
ad49de89 9228 store_regs_bt(branch_regs[i-2].regmap,branch_regs[i-2].dirty,start+i*4);
57871462 9229 assert(branch_regs[i-2].regmap[HOST_CCREG]==CCREG);
9230 }
643aeae3 9231 add_to_linker(out,start+i*4,0);
57871462 9232 emit_jmp(0);
9233 }
9234 }
9235 else
9236 {
9237 assert(i>0);
fe807a8a 9238 assert(!dops[i-1].is_jump);
ad49de89 9239 store_regs_bt(regs[i-1].regmap,regs[i-1].dirty,start+i*4);
57871462 9240 if(regs[i-1].regmap[HOST_CCREG]!=CCREG)
9241 emit_loadreg(CCREG,HOST_CCREG);
277718fa 9242 emit_addimm(HOST_CCREG, cinfo[i-1].ccadj + CLOCK_ADJUST(1), HOST_CCREG);
643aeae3 9243 add_to_linker(out,start+i*4,0);
57871462 9244 emit_jmp(0);
9245 }
9246
57871462 9247 // Stubs
a5cd72d0 9248 for(i = 0; i < stubcount; i++)
57871462 9249 {
b14b6a8f 9250 switch(stubs[i].type)
57871462 9251 {
9252 case LOADB_STUB:
9253 case LOADH_STUB:
9254 case LOADW_STUB:
57871462 9255 case LOADBU_STUB:
9256 case LOADHU_STUB:
9257 do_readstub(i);break;
9258 case STOREB_STUB:
9259 case STOREH_STUB:
9260 case STOREW_STUB:
57871462 9261 do_writestub(i);break;
9262 case CC_STUB:
9263 do_ccstub(i);break;
9264 case INVCODE_STUB:
9265 do_invstub(i);break;
57871462 9266 case STORELR_STUB:
9267 do_unalignedwritestub(i);break;
a5cd72d0 9268 case OVERFLOW_STUB:
9269 do_overflowstub(i); break;
277718fa 9270 case ALIGNMENT_STUB:
9271 do_alignmentstub(i); break;
a5cd72d0 9272 default:
9273 assert(0);
57871462 9274 }
9275 }
9276
9ad4d757 9277 if (instr_addr0_override)
9278 instr_addr[0] = instr_addr0_override;
9279
93c0345b 9280#if 0
9281 /* check for improper expiration */
9282 for (i = 0; i < ARRAY_SIZE(jumps); i++) {
9283 int j;
9284 if (!jumps[i])
9285 continue;
9286 for (j = 0; j < jumps[i]->count; j++)
9287 assert(jumps[i]->e[j].stub < beginning || (u_char *)jumps[i]->e[j].stub > out);
9288 }
9289#endif
9290
57871462 9291 /* Pass 9 - Linker */
9292 for(i=0;i<linkcount;i++)
9293 {
643aeae3 9294 assem_debug("%p -> %8x\n",link_addr[i].addr,link_addr[i].target);
57871462 9295 literal_pool(64);
104df9d3 9296 if (!link_addr[i].internal)
57871462 9297 {
643aeae3 9298 void *stub = out;
9299 void *addr = check_addr(link_addr[i].target);
9300 emit_extjump(link_addr[i].addr, link_addr[i].target);
9301 if (addr) {
9302 set_jump_target(link_addr[i].addr, addr);
104df9d3 9303 ndrc_add_jump_out(link_addr[i].target,stub);
57871462 9304 }
643aeae3 9305 else
9306 set_jump_target(link_addr[i].addr, stub);
57871462 9307 }
9308 else
9309 {
9310 // Internal branch
643aeae3 9311 int target=(link_addr[i].target-start)>>2;
57871462 9312 assert(target>=0&&target<slen);
9313 assert(instr_addr[target]);
9314 //#ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
643aeae3 9315 //set_jump_target_fillslot(link_addr[i].addr,instr_addr[target],link_addr[i].ext>>1);
57871462 9316 //#else
643aeae3 9317 set_jump_target(link_addr[i].addr, instr_addr[target]);
57871462 9318 //#endif
9319 }
9320 }
3d680478 9321
9322 u_int source_len = slen*4;
cf95b4f0 9323 if (dops[slen-1].itype == INTCALL && source_len > 4)
3d680478 9324 // no need to treat the last instruction as compiled
9325 // as interpreter fully handles it
9326 source_len -= 4;
9327
9328 if ((u_char *)copy + source_len > (u_char *)shadow + sizeof(shadow))
9329 copy = shadow;
9330
57871462 9331 // External Branch Targets (jump_in)
104df9d3 9332 int jump_in_count = 1;
9333 assert(instr_addr[0]);
9334 for (i = 1; i < slen; i++)
9335 {
9336 if (dops[i].bt && instr_addr[i])
9337 jump_in_count++;
9338 }
9339
9340 struct block_info *block =
9341 new_block_info(start, slen * 4, source, copy, beginning, jump_in_count);
9342 block->reg_sv_flags = state_rflags;
9343
9344 int jump_in_i = 0;
9345 for (i = 0; i < slen; i++)
57871462 9346 {
104df9d3 9347 if ((i == 0 || dops[i].bt) && instr_addr[i])
57871462 9348 {
104df9d3 9349 assem_debug("%p (%d) <- %8x\n", instr_addr[i], i, start + i*4);
9350 u_int vaddr = start + i*4;
9351
9352 literal_pool(256);
9353 void *entry = out;
9354 load_regs_entry(i);
9355 if (entry == out)
9356 entry = instr_addr[i];
9357 else
9358 emit_jmp(instr_addr[i]);
9359
9360 block->jump_in[jump_in_i].vaddr = vaddr;
9361 block->jump_in[jump_in_i].addr = entry;
9362 jump_in_i++;
57871462 9363 }
9364 }
104df9d3 9365 assert(jump_in_i == jump_in_count);
9366 hash_table_add(block->jump_in[0].vaddr, block->jump_in[0].addr);
57871462 9367 // Write out the literal pool if necessary
9368 literal_pool(0);
9369 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
9370 // Align code
9371 if(((u_int)out)&7) emit_addnop(13);
9372 #endif
01d26796 9373 assert(out - (u_char *)beginning < MAX_OUTPUT_BLOCK_SIZE);
643aeae3 9374 //printf("shadow buffer: %p-%p\n",copy,(u_char *)copy+slen*4);
3d680478 9375 memcpy(copy, source, source_len);
9376 copy += source_len;
9f51b4b9 9377
d148d265 9378 end_block(beginning);
9f51b4b9 9379
57871462 9380 // If we're within 256K of the end of the buffer,
9381 // start over from the beginning. (Is 256K enough?)
2a014d73 9382 if (out > ndrc->translation_cache + sizeof(ndrc->translation_cache) - MAX_OUTPUT_BLOCK_SIZE)
9383 out = ndrc->translation_cache;
9f51b4b9 9384
57871462 9385 // Trap writes to any of the pages we compiled
104df9d3 9386 mark_invalid_code(start, slen*4, 0);
9f51b4b9 9387
57871462 9388 /* Pass 10 - Free memory by expiring oldest blocks */
9f51b4b9 9389
4149788d 9390 pass10_expire_blocks();
9391
37387d8b 9392#ifdef ASSEM_PRINT
9393 fflush(stdout);
9394#endif
ece032e6 9395 stat_inc(stat_bc_direct);
57871462 9396 return 0;
9397}
b9b61529 9398
9399// vim:shiftwidth=2:expandtab
ARM optimized PCSX fork